Patent ID: 7543094
Filing Date: 2009-06-02
Classification: G06F

Abstract:
1. A method of performing contiguous write transactions between a processor and a bus agent on a processor bus, comprising: detecting, by the bus agent, a request for a write cycle; asserting, by the bus agent, a target ready signal in response to the write cycle during a first clock cycle of a data transfer phase of a prior write cycle, wherein the target ready signal is a one-cycle pulse; asserting, by the bus agent, response signals in a next clock cycle following the clock cycle in which the target ready signal is asserted; asserting, by the processor, a data busy signal for the write cycle in the next clock cycle following the clock cycle in which the response signals are asserted; and asserting, by the processor, data for the write cycle when the data busy signal is asserted detecting, by the bus agent, a request for each of a plurality of contiguous write cycles; asserting, by the bus agent, the target ready signal in response to each contiguous write cycle during a first clock cycle of a data transfer phase of a prior contiguous write cycle; asserting, by the bus agent, response signals for each contiguous write cycle in a next clock cycle following the clock cycle in which the target ready signal is asserted; asserting, by the processor, the data busy signal for each contiguous write cycle in the next clock cycle following the clock cycle in which the response signals are asserted; and asserting, by the processor, data for each contiguous write cycle when the data busy signal is asserted.