Patent ID: 6519666
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A shared bus master arbitration circuitry, in a data communication system, for allocating access to a shared bus connected to a plurality of data processing devices and resources, wherein the shared bus is located between a higher-priority system resource, a lower-priority system resource, and a peripheral device, comprising:a shared bus arbiter for dynamically determining the highest priority request between a number of shared bus requests and granting control of the shared bus to the highest priority request; and wherein the arbiter utilizing a three-level priority hierarchy arbitration scheme, the highest priority level given to short message transfer requests on the higher-priority system resource, the intermediate priority level given to short message transfer requests on the lower-priority system resource, only if there are no outstanding higher priority level requests, and the lowest priority level given for long burst transfers, only if there are no outstanding short message transfer requests.