Patent ID: 6331953
Filing Date: 2001-12-18
Classification: G11C,H01L

Abstract:
A method of erasing a memory cell that comprises a first region and a second region with a channel therebetween and a gate above said channel, and a charge trapping region that contains a first amount of charge, the method comprising:a) applying a voltage across said gate and said first region in accordance with a coarse erase sequence of voltages so that a portion of said first amount of charge is removed from said charge trapping region;b) detecting the read current generated in response to the voltage applied in step a); andc) comparing the detected read current of step b) with a predetermined threshold current value, wherein should the detected current vary from a predetermined erase verified current value by at least a predetermined amount, then steps a)-c) are repeated, and should the detected current vary from said predetermined erase verified current by an amount less than said predetermined amount, then a voltage is applied across said first region in accordance with a fine erase sequence of voltages so that a portion of said first amount of charge is removed from said charge trapping region.