Patent ID: 7882408
Filing Date: 2011-02-01
Classification: H03K

Abstract:
1. A method of operating an integrated circuit comprising: writing a first bit pattern into a first memory using a plurality of first control signals transmitted to the first memory, wherein the first control signals are transmitted with a first timing setting, the first timing setting including one or more first delay settings between control signals; reading a second bit pattern from the first memory using a plurality of second control signals transmitted to the first memory, wherein the second control signals are transmitted with the first timing setting; comparing the first bit pattern and the second bit pattern; if the first bit pattern is the same as the second bit pattern, writing a third bit pattern into the first memory using the first control signals transmitted to the first memory with a second timing setting, the second timing setting including one or more second delay settings between control signals, wherein at least one of the second delay settings is different than the corresponding first delay setting; reading a fourth bit pattern from the first memory using the second control signals transmitted with the second timing setting; comparing the third bit pattern and the fourth bit pattern; and if the third bit pattern is different from the fourth bit pattern, using the first or second control signals transmitted with the first timing setting when reading or writing to a second memory.