Patent ID: 8989333
Filing Date: 2015-03-24
Classification: H04L

Abstract:
1. A clock data recovery method comprising: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating, in a data interpolator, the first digital signal in accordance with phase information to generate interpolation data; receiving, in a phase detector, the interpolation data from the data interpolator and outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; receiving the interpolation data, which is output from the data interpolator and is the same as the interpolation data that is received in the phase detector, and performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.