Patent ID: 8670454
Filing Date: 2014-03-11
Classification: H04L

Abstract:
1. A system, comprising: input nodes to receive data cells; a linecard, which includes a set of host buffers, wherein the set of host buffers is coupled to a given input node; output nodes to output the data cells; and a switch which is physically separate from the linecard and which includes: wherein, for each data cell in at least some of the data cells, the system uses an occupancy of the switch-ingress buffers to dynamically determine a given switch-ingress buffer in the set of switch-ingress buffers to which the data cell is to be sent from a given host buffer in the set of host buffers, and wherein the linecard maintains a data structure that maps the given switch-ingress buffer to a set of virtual queues for one or more of the host buffers, wherein an entry for the data structure identifies the set of virtual queues from which the given switch-ingress buffer accepts data cells, wherein, if a data cell associated with a data stream is currently in one of the switch-ingress buffers, a subsequent data cell associated with the data stream is assigned to the one of the switch-ingress buffers; and wherein, in the absence of the data cell associated with the data stream in one of the switch-ingress buffers, the subsequent data cell associated with the data stream is assigned to one of the switch-ingress buffers, which can be an arbitrary one of the switch-ingress buffers.