Patent ID: 7037783
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A method of manufacturing a split gate type semiconductor memory device, comprising: forming a gate insulating film and a conductive layer on a semiconductor substrate; forming mask patterns on the conductive layer which define at least a pair of first openings that expose the conductive layer; forming intergate oxide films by selective thermal oxidation of the conductive layer exposed by the mask patterns; defining a second opening by removing a portion of the mask patterns between the intergate oxide films; forming spacers on inner walls of the second opening; defining a third opening by etching the conductive layer, exposing the gate insulating film, by using the mask patterns, the spacers, and the intergate oxide films as etch masks; forming a source region by ionic implanting a dopant into the third opening; forming an insulating film plug by filling the third opening; exposing side faces of the insulating film plug by removing the mask patterns and the spacers; forming a pair of floating gates by dry etching portions of the conductive layer using the intergate oxide films as an etch mask to expose the gate insulating film; forming tunnel insulating films on the side walls of each floating gate; forming a spacer type control gate by self aligning on side walls of the insulating film plug; and forming drain regions in the semiconductor substrate near an outer region of the control gate.