Patent ID: 6591230
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A coprocessor for synthesis of a digital signal corresponding to a sum of sinusoids, comprising:a plurality of parameter registers for storing parameters corresponding to a previous sample point in a frame, the plurality of parameter registers comprising an amplitude register, a delta amplitude register, a phase register, a difference register, and a delta difference register; a first adder for adding the contents of the amplitude register and the delta amplitude register to produce a current amplitude value for a current sample point in the frame, the first adder having an output coupled to the amplitude register to update the contents thereof; a second adder for adding the contents of the difference register and the delta difference register, the second adder having an output coupled to the difference register to update the contents thereof; a third adder having inputs coupled to the output of the second adder and to the phase register, for adding at least a portion of the output of the second adder to the contents of the phase register to produce a current phase value for the current sample point in the frame, the third adder having an output coupled to the phase register to update the contents thereof; sine function calculator circuitry, having inputs coupled to the output of the first adder and to the output of the third adder, for generating a digital value corresponding to a sine of the current value at the current amplitude value; and accumulator circuitry, for adding the digital value at the output of the sine function calculator circuitry to previously calculated digital values for the current sample point in the frame.