Patent ID: 6154390
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A sensing circuit for a multi-bit memory cell in a memory array, the memory array having memory cells with a plurality of threshold voltages coupled to word lines and data lines, the sensing circuit for determining data of the memory cell by sensing an output on a data line coupled to the memory cell, the sensing circuit comprising:a gate-to-source voltage driver responsive to a memory cell bit address; anda logic circuit responsive to the memory cell bit address for determining said data, the logic circuit adapted to respond to a first memory cell bit address by providing a first logic state indicating whether the output of said data line corresponds to one of a low threshold voltage group and a high threshold voltage group, and the logic circuit adapted to respond to a second memory cell bit address by providing a second logic state indicating whether the output of said data line corresponds to one of an outer threshold voltage group and an inner threshold voltage group.