Patent ID: 6463575
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A method of a cell-layout in an integrated circuit device, comprising:a first step of establishing a plurality of cut lines in vertical and horizontal directions to divide a substrate; a second step of considering the entire substrate as one cell-layout region and assigning all the cells included in an integrated circuit in said cell-layout region; a third step of defining as one cluster a set of a plurality of cells within said cell-layout region; a fourth step of determining a direction of the cut line to division-process said cell-layout region; a fifth step of selecting one cut line per row or column of the cell-layout region on the substrate among non-processed cut lines in the horizontal or vertical direction based on the determined direction; a sixth step of determining a cell to be placed in said cell-layout region by implementing a Min-Cut division in a cluster unit with respect to said cut line selected at said fifth step, thereby dividing the substrate into smaller regions and implementing said division in parallel with respect to a plurality of said cut lines.