Patent ID: 7812630
Filing Date: 2010-10-12
Classification: H03K

Abstract:
1. A latch circuit comprising: a feedback circuit including two first input terminals, a first output terminal, and at least one signal-output-circuit having two second input terminals and a second output terminal, the signal-output-circuit outputting second output-signal from the second output terminal, only when logic signals having same logic level are input to the two second input terminals; and an input circuit inputting signals having same phase to the two first input terminals of the feedback circuit in synchronization with a clock signal; wherein, in the feedback circuit, positive feedback using a certain number of amplification stages is applied to the first input terminals, and the first output terminal is coupled to the second output terminal of the at least one signal-output-circuit at least one of the two first input terminals is coupled to at least one of the two second input terminals of the at least one signal-output-circuit.