Patent ID: 7285831
Filing Date: 2007-10-23
Classification: H01L

Abstract:
1. A complementary metal oxide semiconductor (CMOS) device comprising: a first device active region including at least one pair of active regions having a first active region that has a first width and a second active region for forming a contact that has a second width, wherein the first width is less than the second width and the first active region and the second active region are non-overlapping; a first gate arranged on the first device active region; a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region and the first gate; a second device active region having a third width greater than the first width; a second gate arranged on the second device active region; and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region and the second gate, wherein the first width and the third width are configured to substantially balance an electron mobility and a hole mobility in the CMOS device.