Patent ID: 7781292
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. A method of fabricating an electronic device, comprising: forming a dielectric isolation in a semiconductor substrate, said dielectric isolation extending in a direction perpendicular to a top surface of said substrate into said substrate a first distance, said dielectric isolation surrounding a first region and a second region of said substrate, a top surface of said dielectric isolation coplanar with said top surface of said substrate; forming a dielectric region in said second region of said substrate; said dielectric region extending in said perpendicular direction into said substrate a second distance, said first distance greater than said second distance; forming a field effect transistor in said first region a source and a drain of said field effect transistor each abutting said dielectric isolation in said first region; and forming a lateral double diffused metal-oxide-silicon (LDMOS) device in said second region, a body and a well of said LDMOS device each abutting said dielectric isolation in said second region, wherein said dielectric region is in said well.