Patent ID: 6810498
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, comprising:a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM; a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors; a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors; wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops.