Patent ID: 7091069
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method of forming an ultra thin fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structure comprising the steps of: providing a SOI structure comprising a dummy gate that has an upper surface that is coplanar with an upper surface of a planarizing material, said dummy gate is located on a sacrificial oxide that is positioned atop a top Si-containing layer of a SOI substrate; removing the dummy gate to provide a gate opening that exposes a portion of the underlying sacrificial oxide layer, said gate opening defining a device channel in said top Si-containing layer; implanting ions into the device channel, said ions comprise nitrogen or flourine; removing the sacrificial oxide layer to expose the device channel; recessing the device channel to provide a recessed device channel; and forming the gate, including gate dielectric and gate electrode in said opening atop the recessed device channel.