Patent ID: 8791372
Filing Date: 2014-07-29
Classification: H05K,Y10T

Abstract:
1. A device comprising: one or more first planar conductive layers; one or more second planar conductive layers substantially parallel to the one or more first planar conductive layers; and a core dielectric disposed between the one or more first planar conductive layers and the one or more second planar conductive layers, the core dielectric having one or more plated through holes (PTHs), wherein the one or more PTHs comprise at least one non-connected PTH that is embedded within the core dielectric and that is not connected to an electrically conductive path and at least one interconnected PTH that is electrically connected to one or more traces that provide one or more electrically conductive paths to the at least one interconnected PTH from the one or more first planar conductive layers and the one or more second planar conductive layers, wherein the at least one non-connected PTH reduces an impedance discontinuity of the device, wherein the interior wall of the one or more PTHs is coated with a layer of magnetic material, and wherein the magnetic material modifies the internal and external magnetic environment of the core dielectric by decreasing impedance discontinuity of signals by increasing inductance of the one or more PTHs; the core dielectric further comprising one or more PTH vias that are each created as a hole through the dielectric layer, wherein an interior surface area of the hole of each of the one or more PTH vias is coated with a first layer comprising a magnetic material, wherein the first layer is further coated with a second layer comprising an electrically conductive metal material, and wherein inside the second layer there is deposited a resin that fills an internal cavity of the hole.