Patent ID: 8819309
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. Apparatus for buffering received data transaction requests, said apparatus comprising: shared buffer circuitry configured to store, in order of reception time at said shared buffer circuitry, data transaction requests received from one or more data transaction sources; low latency identifying circuitry configured to identify low latency data transaction requests associated with low latency handling from among said data transaction requests received from said one or more data transaction sources and stored in said shared buffer circuitry; output selection circuitry configured to select a data transaction request for output from said shared buffer circuitry and to operate in a selectable one of: rate detection circuitry configured to detect a rate of output of low latency data transaction requests from said shared buffer circuitry; and bypass control circuitry configured to compare said rate with a threshold value and to control said output selection circuitry to operate in one of: