Patent ID: 8589942
Filing Date: 2013-11-19
Classification: G01S

Abstract:
1. An embedded processor comprising: a memory storing a plurality of hard real time (HRT) threads and a plurality of non-real time (NRT) threads, each HRT thread and each NRT thread including a corresponding plurality of instructions, wherein each HRT thread includes a corresponding HRT thread identifier (ID) and each NRT thread includes a corresponding NRT thread ID; a HRT thread table specifying a temporal order in which processing time is allocated to the HRT threads, wherein the HRT thread table comprises a plurality of entries, each entry corresponding to an execution cycle and associated with one of the HRT thread IDs; a HRT thread scheduler coupled to the HRT thread table, the HRT thread scheduler configured to, for each execution cycle, access the HRT thread table to retrieve the HRT thread ID associated with the HRT thread table entry corresponding to the execution cycle and to determine whether one or more resources are available to a particular HRT thread identified by the retrieved HRT thread ID; a NRT thread table comprising a sequential list of one or more of the NRT thread IDs, wherein the NRT threads corresponding to the NRT thread IDs are allocated processing time unused by a HRT thread in the order defined by the sequential list; a NRT thread scheduler coupled to the NRT thread table, the NRT thread scheduler configured to, in response to the HRT thread scheduler determining that the one or more resources are not available to the particular HRT thread for the execution cycle, access the NRT thread table to retrieve the NRT thread ID at a current position in the sequential list and to determine whether the one or more resources are available to a first NRT thread identified by the retrieved NRT thread ID; a round-robin scheduler coupled to the thread selector and to the memory, the round-robin scheduler configured to, in response to the NRT thread scheduler determining that the one or more resources are not available to the first NRT thread, identify a schedulable NRT thread from the plurality of NRT threads; and a thread selector coupled to the HRT thread scheduler, the NRT thread scheduler, and the memory, the thread selector configured to, for each execution cycle: retrieve from the memory an instruction of the particular HRT thread in response to the HRT thread scheduler determining that the one or more resources are available to the particular HRT thread for the execution cycle; retrieve from the memory an instruction of the first NRT thread identified by the NRT thread ID retrieved in response to the HRT thread scheduler determining that the one or more resources are not available to the particular HRT thread for the execution cycle, in response to the NRT thread scheduler determining that the one or more resources are available to the first NRT thread for the execution cycle; and retrieve from the memory an instruction of the schedulable NRT thread in response to the round-robin scheduler identifying the schedulable NRT thread.