Patent ID: 9142561
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of first semiconductor regions extending in a first direction, the plurality of first semiconductor regions being arranged in a direction crossing the first direction; a plurality of control gate electrodes provided on an upper side of the plurality of first semiconductor regions, the plurality of control gate electrodes extending in a second direction different from the first direction, and the plurality of control gate electrodes being arranged in a direction crossing the second direction; a charge storage layer provided in a position, each of the plurality of first semiconductor regions and each of the plurality of control gate electrodes cross in the position; a first insulating film provided between the charge storage layer and each of the plurality of first semiconductor regions; a second insulating film provided between the charge storage layer and each of the plurality of control gate electrodes; and an element isolation region provided between adjacent ones of the plurality of first semiconductor regions, the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side, each of the plurality of control gate electrodes being in contact with a second portion other than the first portion of the charge storage layer via the second insulating film, the charge storage layer including a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer, and a length from a lower end of the silicon-containing layer to an upper end of the element isolation region being the same as a length from the lower end of the silicon-containing layer to a junction between the silicon-containing layer and the silicide-containing layer.