Patent ID: 9189590
Filing Date: 2015-11-17
Classification: G06F,Y02P

Abstract:
1. A method for manufacturing a semiconductor device, the method comprising: using a dummy pattern insertion program to generate a dummy-based circuit layout; determining whether the dummy-based circuit layout complies with a set of circuit layout design rules; using the dummy pattern insertion program to generate a first dummy-inserted circuit layout; checking whether the first dummy-inserted circuit layout complies with at least one of a set of dummy pattern check rules and a set of pattern density rules; using the dummy pattern insertion program to generate a second dummy-inserted circuit layout; examining whether the second dummy-inserted circuit layout complies with at least one of the set of circuit layout design rules, the set of dummy pattern check rules, and the set of pattern density rules; approving, using a device that includes hardware, the dummy pattern insertion program based on the determining, the checking, and the examining; generating a semiconductor device layout design using the dummy pattern insertion program; and manufacturing the semiconductor device using the semiconductor device layout design and a manufacturing apparatus.