Patent ID: 6127706
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A buried contact structure on a semiconductor substrate, said buried contact structure comprising:a gate insulator over a portion of said substrate;a gate electrode over said gate insulator;a gate sidewall structure on the sidewall of said gate electrode;a lightly doped junction region in said substrate under said gate sidewall structure;a doped junction region in said substrate abutting said lightly doped junction region, said doped junction region being located aside from said gate insulator and extended outward from said lightly doped junction region;a doped buried contact region having a planar top surface with a profile without trench in said substrate being formed next to said doped junction region and extended outward from said doped junction region to an isolation region;a silicon interconnect layer on said isolation region and on a first portion of said doped buried contact region locating at the edge abutting said isolation region; anda shielding layer of silicon oxide on a second portion of said planar top surface of said doped buried contact region uncovered by said silicon interconnect layer, a lateral side of said shielding layer being justified with and uncovered an inner lateral side of said silicon interconnect layer, thereby preventing said doped buried contact region from etching and providing said planar top surface of without trench.