Patent ID: 7692433
Filing Date: 2010-04-06
Classification: G01R

Abstract:
1. A probe card assembly for testing a semiconductor wafer comprising: a plurality of individual substrates each comprising a plurality of probes configured to contact dies of the semiconductor wafer and first electrically conductive internal paths connected to the probes, the individual substrates arranged in an away having an outer perimeter; an electrical interface connectable to a tester configured to control testing of the dies; and electrical connections between the electrical interface and the first electrically conductive internal paths of the individual substrate, wherein at least one of the individual substrates has a shape that comprises three approximately ninety degree angles and two obtuse angles, and a first edge of the individual substrate between the two obtuse angles is part of the outer perimeter of the array, wherein the first edge comprises a cut line wherein ones of the first electrically conductive internal paths are spaced apart from the cut line, and wherein a second plurality of electrically conductive internal paths are not connected to the probes and extend to the cut line.