Patent ID: 6236686
Filing Date: 2001-05-22
Classification: H03M,H04L

Abstract:
A data processing equipment for conducting the whitener encoding to suppress DC bias in transmit data in a communication device, comprising:a parallel-to-serial converter for converting parallel transmit data into serial transmit data;a scrambler for generating randomized transmit data supplied from the parallel-to-serial converter;a demultiplexer for distributing the transmit data supplied from the scrambler into a high-order bit and a low-order bit, where said transmit data to be supplied from said demultiplexer are sectioned by an arbitrary bit number n;a first counter which counts by +(2m+1) when 2-bit symbol data in a data section have a logical level of `10`, counts by +(2m-1) when said 2-bit symbol data have a logical level of `11`, counts by -(2m-1) when said 2-bit symbol data have a logical level of `01` and counts by -(2m+1) when said 2-bit symbol data have a logical level of `00`, where m is an integer to satisfy m1 and n is an even number to satisfy n.gtoreq.4;a second counter which counts by +(2m+1) when said 2-bit symbol data, in all data sections before said data section, have a logical level of `10`, counts by +(2m-1) when said 2-bit symbol data have a logical level of `11, counts by -(2m-1) when said 2-bit symbol data have a logical level of `01` and counts by -(2m+1) when said 2-bit symbol data have a logical level of `00`, where m is an integer to satisfy m.gtoreq.1;means for comparing a sign but of said first counter with a sign bit of said second counter;two bit-inversion circuits which invert between `1` and `0` the data in said data sectional according to the result of said comparing means;two n/2-bit shift registers which delay the data in said data section by n-bits; andtwo bit-stuff circuits which insert two stuff bits to said delayed n-bit data supplied from said two n/2-bit shift registers and output said stuff-bit-inserted n-bit data to said two bit-inversion circuits.