Patent ID: 6442088
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a cell block including a plurality of memory cells coupled to a plurality of word lines; a bit line pair including first and second bit lines coupled to said cell block; a sense amplifier coupled to said first and second bit lines; first and second select gates provided between said cell block and said sense amplifier, and coupled to said first and second bit lines, respectively; a first equalizer circuit coupled to first parts of said first and second bit lines which are at a side of said cell block with respect to said first and second select gates, said first equalizer circuit configured to equalize potentials on said first parts of said first and second bit lines; and a second equalizer circuit coupled to second parts of said first and second bit lines which are at a side of said sense amplifier with respect to said first and second select gates, said second equalizer circuit configured to equalize potentials on said second parts of said first and second bit lines, wherein said first and second equalizer circuits equalize the potentials on said first and second parts of said first and second bit lines independently from each other.