Patent ID: 6767810
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A method for fabricating an integrated circuit located between isolation trenches at the surface of a semiconductor chip for, comprising the steps of:depositing a first photoresist layer over a chip surface and opening a window in a first layer between first isolation regions in said surface; implanting, at high energy and high dose, ions of a first conductivity type into said surface through said window, creating a first well of a first conductivity type; removing said first photoresist layer; depositing a second photoresist layer over said chip surface and opening a window in said second layer between second isolation regions in said surface, said second isolation regions nested within said first isolation regions; implanting, at high energy and low dose, ions of the opposite conductivity type into said surface through said window, creating, by partial doping compensation, a region of lower doping concentration of the first conductivity type embedded in said first well, resulting in a regional resistivity higher than the resistivity of the first well; removing said second photoresist layer; forming gate structures for a MOS transistor positioned in the surface space between said second isolation regions; depositing a third photoresist layer over said chip surface and opening a window in a third layer between said second isolation regions in said surface; implanting, at medium energy and medium dose, ions of the opposite conductivity type into said surface through said window and through said gate structures, creating a second well of opposite conductivity type close to and substantially parallel to said surface; implanting, at low energy and high dose, ions of the first conductivity type into said surface through said window, creating drain extension regions of said MOS transistor; implanting, at low energy and low dose, ions of the opposite conductivity type into said surface through said window and through said gate structures, adjusting the gate voltage Vt of said MOS transistor; removing said third photoresist layer; forming insulating sidewalls on said gate, deep source and drain regions of said MOS transistor, and contact region of said second well, whereby said contact region is spaced from said MOS transistor by a predetermined distance.