Patent ID: 6191990
Filing Date: 2001-02-20
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device comprising:a memory array including dynamic memory cells each made up of a storage capacitor and an address selecting MOSFET, with the gate of said address selecting MOSFET being connected to a word line, one source-drain being connected to a bit line which intersect said word line, and another source-drain being connected to a storage node corresponding to one electrode of said storage capacitor, and with a plate electrode corresponding to another electrode of this storage capacitor being supplied with a certain voltage; amplifying MOSFETs of sense amplifiers which amplify small voltages derived from information charges of said storage capacitors read out onto the bit lines; and column switch MOSFETs which select said bit lines;a read/write section including main amplifiers for reading out stored data from memory cells selected by said column switch; anda logic circuit section which implements the input/output operation of data with said read/write section,wherein two capacitors, each having a first electrode which is a plate electrode with the same structure as said storage capacitors and a second electrode which is multiple commonly-connected storage nodes of said storage capacitors, are arranged in serial connection, disposed contiguously to said read/write section, and connected between the operation voltage lines of said read/write section.