Patent ID: 6808988
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A process for making a flash memory core having source and drain regions, comprising the steps of:providing at least one silicon substrate; establishing at least one tunnel oxide layer on the silicon substrate after said step of providing said at least one silicon substrate; establishing plural stacks on the tunnel oxide layer after said step of establishing said at least one tunnel oxide layer, each stack including a first polysilicon layer; implanting channel stop dopant in the silicon substrate after said step of establishing said plural stacks; depositing a field oxide material on at least portions of the silicon substrate over the channel stop dopant after said step of implanting said channel stop dopant; forming at least one interpoly dielectric layer on at least some of the stacks after said step of depositing said field oxide material; depositing at least one second polysilicon layer on at least a portion of the interpoly dielectric layer after said step of forming said at least one interpoly dielectric layer, such that plural memory cell control gates are established; and after the step of establishing plural memory cell control gates, establishing isolation trenches in the substrate.