Patent ID: 6720999
Filing Date: 2004-04-13
Classification: H04N

Abstract:
A processing system for an imager device comprising in an integrated, monolithic system:a two-dimensional array source of imager signals; a correlated double sample (CDS) circuit for receiving imager signals; a variable gain amplifier (VGA) circuit configured to be selectably settable at one of a plurality of predetermined data resolution levels; an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit; a black level clamp connected to said ADC; a gain circuit coupled to said ADC, said gain circuit configured to produce an output signal of selected magnitude; a compander connected to said gain circuit and configured to receive a digital input of predetermined bit-width and to produce a digital output of selectably reduced bit-width; horizontal and vertical timing circuitry configured to control receipt of pixel intensity signals from a two-dimensional array source; and a multiplexer connected to said compander and said gain circuit, enabling selection between outputs of said gain circuit and said compander.