Patent ID: 9064752
Filing Date: 2015-06-23
Classification: G02F,H01L

Abstract:
1. An array substrate comprising: a substrate including a pixel region; trenches formed in the substrate and having a depth from a surface of the substrate; a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose ends of the data pattern; a semiconductor layer on the gate insulating layer over the gate electrode; a data connection portion on the gate insulating layer and contacting adjacent data patterns through the contact holes; a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode, wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and wherein the source electrode extends from the data connection portion and on the semiconductor layer.