Patent ID: 8044475
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A chip package comprising: a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and said CMOS device, and a microlens over said optical filter, said passivation layer and said CMOS device; a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer and an electroplated gold layer having a thickness between 1 and 50 micrometers on said gold seed layer; a transparent substrate over said semiconductor chip, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip; and a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joining said semiconductor chip and a top end joining said transparent substrate, wherein said spacer is horizontally between said microlens and said metal bump.