Patent ID: 7163860
Filing Date: 2007-01-16
Classification: H01L,Y10S

Abstract:
1. A process for fabricating a charge trapping dielectric flash memory device comprising: providing a semiconductor substrate having formed thereon a bottom oxide layer; depositing on the bottom oxide layer a charge trapping dielectric charge storage layer, wherein the charge storage layer comprises a charge trapping dielectric material having a reduced hydrogen content relative to a hydrogen content of a conventional charge trapping dielectric storage layer; depositing on the charge storage layer a top oxide layer; depositing on the top oxide layer a control gate electrode layer, whereby a gate stack comprising the bottom oxide layer, the charge storage layer, the top oxide layer and the control gate electrode is provided; forming an oxide layer over at least the gate stack; depositing a spacer layer over the gate stack, wherein the spacer layer comprises a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material; and etching the spacer layer to form a gate stack spacer adjacent the gate stack, wherein hydrogen substantially does not migrate into the gate stack from either the gate stack spacer or from the charge storage layer, during subsequent processing or in use.