Patent ID: 6815749
Filing Date: 2004-11-09
Classification: H01L

Abstract:
An integrated circuit having a device layer of semiconductor with a device layer thickness of less than 100 nm above an array insulating layer and containing an array of DRAM cells including a trench capacitor connected by a buried strap to a horizontal pass transistor formed in said device layer, said pass transistor having an internal contact adjacent said trench, in which:said set of trench capacitors have center electrodes insulated by a capacitor insulator, said center electrodes having a top surface below a bottom surface of said device layer; said buried strap is formed from strap conductive material extending vertically in said trenches to a level below said bottom surface of said device layer and laterally outside said trenches and underneath said internal contact of said pass transistor, whereby said strap conductive material makes electrical contact with said bottom surface to form said buried straps; and top insulating material having a top insulator thickness extending up to a surface of said device layer in said trenches above said strap conductive material and abutting a vertical surface of said internal contact of said pass transistor.