Patent ID: 6242303
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method for manufacturing an erasable programmable memory on a semiconductor substrate, said method comprising:forming isolation regions on said semiconductor substrate to define active areas and expose a tunnel region and a control region;forming a conductive structure with an uneven surface on a portion of said control region and exposing a portion of said control region of said semiconductor substrate;performing an ion implantation to implant dopants into said tunnel region and said control region of said semiconductor substrate and form doped tunnel region and doped control region in said semiconductor substrate, wherein said doped control region and said conductive structure serve as a control gate;forming an inter-poly dielectric on said control gate, a tunnel dielectric and a non-tunnel dielectric on said doped tunnel region;forming a floating gate on said semiconductor substrate, said floating gate covering said tunnel dielectric and exposing a portion of said inter-poly dielectric;forming an inter-layer dielectric on said floating gate; andetching said inter-layer dielectric and said inter-poly dielectric to form a contract window and expose a portion of said control gate.