Patent ID: 8296708
Filing Date: 2012-10-23
Classification: G06F

Abstract:
1. A computer-implemented method for generating at least one placement for an integrated circuit (IC), wherein the integrated circuit (IC) comprises a plurality of device modules, the method comprising using a computer to perform the steps of: a. receiving a plurality of constraints for generating at least one placement for the integrated circuit (IC), wherein each constraint is assigned a priority; b. forming, using the computer, a constraint hierarchy tree comprising a root node, a plurality of internal nodes and a plurality of leaf nodes according to the plurality of constraints, wherein the root node represents the placement of the integrated circuit (IC), each of the internal nodes represents a constraint for its corresponding set of the device modules respectively and each of the leaf nodes represents its corresponding device module respectively, the step comprising the sub-steps of: c. generating at least one placement for the integrated circuit (IC) by satisfying each of the constraints in the hierarchy tree from the bottom to the top of the tree sequentially.