Patent ID: 6088748
Filing Date: 2000-07-11
Classification: H04L

Abstract:
A computer system comprising:a processor;a first bus interface unit coupled to said processor;a memory coupled to said first bus interface unit;a mezzanine bus coupled to said first bus interface unit;a second bus interface unit coupled between said mezzanine bus and a peripheral bus;an isochronous data port coupled to said first bus interface unit;a plurality of isochronous devices coupled to said isochronous data port; andan isochronous bus coupled between said isochronous data port and said first bus interface unit;wherein said isochronous data port is configured to acquire data from said plurality of isochronous devices and to output frames of time-dependent data on said isochronous data bus;wherein a first frame is partitioned into a plurality of data channels, wherein each data channel corresponds to one of said plurality of isochronous devices; andwherein each of said plurality of data channels corresponding to said plurality of isochronous devices is partitioned into a plurality of bit time slots, wherein a number of bit time slots allocated to said each data channel exceeds a number of samples of the corresponding isochronous device during a period of said first frame.