Patent ID: 7537866
Filing Date: 2009-05-26
Classification: G03F,H01L

Abstract:
1. A method of transferring a circuit design layout to a layer of an integrated circuit (IC), the method comprising: using a resolution enhancement technique (RET) to define one or more fine-line patterns in a first masking layer, one of removing and designating for removal portions of the fine-line pattern(s) not needed to implement the circuit design and protecting desired portions of the fine-line features defined in the first masking layer; patterning the first masking layer, thereby forming a patterned first masking layer; forming a second masking layer over the patterned first masking layer; defining a plurality of coarse features of the circuit design layout in the second masking layer, patterning the second masking layer; and patterning the IC layer using a composite mask formed by the patterned first masking layer and the patterned second masking layer.