Patent ID: 6406970
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory cell, comprising:providing a semiconductor wafer having a substrate; forming a plurality of trenches in the substrate, the trenches including sidewalls; depositing a first oxide layer over the substrate; depositing a first semiconductor material over the first oxide layer; removing a top portion of the semiconductor material, leaving a portion of the first semiconductor material remaining within the trenches; removing a top portion of the first oxide layer to a level below the top of the first semiconductor material within the trenches; forming a nitride layer over the exposed semiconductor substrate within the trenches; depositing a second semiconductor layer over the nitride layer; exposing the wafer to a vertical dopant implantation process to dope the top surfaces of the second semiconductor layer, leaving the second semiconductor layer undoped on the sidewalls of the trenches; removing the undoped second semiconductor layer from the trench sidewalls; and oxidizing the doped second semiconductor layer disposed over the first semiconductor material.