Patent ID: 9053923
Filing Date: 2015-06-09
Classification: G03F,H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: forming etch resistant fill control topographical features that overlie a semiconductor substrate and that define an etch resistant fill control confinement well; depositing a block copolymer into the etch resistant fill control confinement well; and phase separating the block copolymer into an etchable phase and an etch resistant phase defining a phase separated block copolymer, wherein the etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well, wherein the etch resistant plug is configured to prevent any opening from being formed continuously through the phase separated block copolymer that is in the etch resistant fill control confinement well when the phase separated block copolymer is etched to remove at least a portion of the etchable phase.