Patent ID: 6411545
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A non-volatile latch comprising:first and second read/write bias nodes; first and second complementary output nodes; first and second first conductivity type MOS transistors having sources coupled to a first voltage potential, a drain of said first MOS transistor coupled to said first complementary output node and a drain of said second MOS transistor coupled to said second complementary output node, each of said first and second MOS transistors having a gate cross coupled to the drain of the other one of said first and second MOS transistor; and third and fourth second conductivity type MOS floating gate transistors, a source of said third MOS transistor coupled to said first read/write bias node and a source of said fourth MOS transistor coupled to said second read/write bias node, a drain of said third MOS transistor coupled to said first complementary output node and a drain of said fourth MOS transistor coupled to said second complementary output node, each of said third and fourth MOS transistors having a gate cross coupled to the source of the other one of said third and fourth MOS transistors.