Patent ID: 9041089
Filing Date: 2015-05-26
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory structure, comprising: a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row along a first direction, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region; a first select transistor on the first OD region, wherein the first select transistor comprises a select gate extending along a second direction; a floating gate transistor on the second OD region, wherein the floating gate transistor is serially coupled to the first select transistor, and wherein the floating gate transistor comprises a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions, wherein an entire perimeter of the floating gate is located directly on the isolation region; and a second select transistor on the third OD region serially coupled to the floating gate transistor, wherein the second select transistor comprises a word line extending along the second direction.