Patent ID: 8874979
Filing Date: 2014-10-28
Classification: G06F,G11C,H03M

Abstract:
1. A method for bank sparing in a 3D memory device having a plurality of ranks, each rank having a plurality of banks, the method comprising: detecting, by a memory controller, a first error in the 3D memory device; detecting, by the memory controller, a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select; sending a command from the memory controller to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element based on detecting the second error, wherein the second element is in a second rank of the 3D memory device, the second rank is a spare rank that does not have an associated chip select that is addressable by the memory controller, and wherein the first element and second element are each either a bank or a bank group; and correcting the first error using an error control code.