Patent ID: 6208563
Filing Date: 2001-03-27
Classification: G11C

Abstract:
A semiconductor memory device in which a word line is selected based on a row address, and a bit line is selected based on a column address, and in which, in each write or read cycle, a plurality bits of data are written to or read from memory cells as a burst, said semiconductor memory device comprising:a plurality of write/read circuits for reading data from selected memory cells to data lines and writing data from said data lines to selected memory cells;a column selector for distributing data from an input/output line to said data lines, and outputting data from said data lines to said input/output line;a plurality of data latches inserted into data line circuit portions between said column selector and said write/read circuits, for temporarily storing data to be written to or read from said memory cells as a burst; andwherein, in a write cycle, after data stored in said latches is written into memory cells and after elapsing a predetermined time period required for a precharge operation of said bit lines, the next write cycle is started, and, in a read cycle, after data is read out from memory cells into said data latches and after performing a precharge operation of said bit lines, the next read cycle is started.