Patent ID: 6184947
Filing Date: 2001-02-06
Classification: G02F

Abstract:
A thin film transistor matrix comprising:an insulating substrate;a plurality of thin film transistors disposed in a row and column matrix pattern on said insulating substrate, each thin film transistor having a gate electrode, a source electrode and a drain electrode;a pixel electrode formed on said insulating substrate and connected to the source electrode of each of said plurality of thin film transistors;a plurality of gate bus lines disposed along a row direction on said insulating substrate, each gate bus line being connected to the gate electrode and including a first lamination of a first metal layer and a first semiconductor layer disposed directly under the first metal layer along substantially the entire length of the gate bus line; anda plurality of drain bus lines disposed along a column direction on said insulating substrate, each drain bus line being connected to the drain electrode and including a second lamination of a second metal layer and a second semiconductor layer disposed directly under the second metal layer along substantially the entire length of the drain bus line.