Patent ID: 9006094
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising: providing a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate; forming a first high dielectric constant (high-k) gate dielectric layer comprising a first high-k dielectric material in said gate cavity and on a portion of said semiconductor substrate, wherein said first high-k gate dielectric layer has a horizontal portion located on said portion of said semiconductor substrate and vertical portions extending upward from said horizontal portion; forming a band-gap-disrupting dielectric layer comprising a dielectric material having a different band gap than said first high-k gate dielectric material directly on said horizontal portion of said first high-k gate dielectric layer; forming a second high-k gate dielectric layer comprising a second high-k dielectric material having a different band gap than said band-gap-disrupting dielectric of said band-gap-disrupting dielectric layer, wherein said second high-k gate dielectric layer has a horizontal portion located directly on a topmost surface of said band-gap-disrupting dielectric layer and vertical portions extending upward from said horizontal portion and in direct physical contact with vertical portions of said first high-k gate dielectric layer; and patterning a stack of said first high-k gate dielectric layer, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer to form a stratified gate dielectric stack of a first high-k gate dielectric, a band-gap-disrupting dielectric, and a second high-k gate dielectric, wherein a first atomic interface between said band-gap-disrupting dielectric and said first high-k gate dielectric is spaced from a second atomic interface between said band-gap-disrupting dielectric and said second high-k gate dielectric by at least one continuous atomic layer of said dielectric material of said band-gap-disrupting dielectric within said stratified gate dielectric stack and wherein said topmost surface of said band-gap-disrupting dielectric is located beneath a topmost surface of said vertical portions of said first and second high-k gate dielectrics.