Patent ID: 6118720
Filing Date: 2000-09-12
Classification: H03K

Abstract:
Memory circuitry comprising:a plurality of memory cells operatively arranged in a two-dimensional array of intersecting rows and columns of such cells;a plurality of data in conductors, each of which is associated with a respective one of the columns and configured to selectively supply data to the cells in the associated column;a plurality of data out conductors, each of which is associated with a respective one of the columns and configured to selectively respond to data in the cells in the associated column;a plurality of write enable conductors, each of which is associated with a respective one of the rows and configured to enable writing of data from the data in conductors to the cells in the associated row;a plurality of read enable conductors, each of which is associated with a respective one of the rows and configured to enable reading of data from the cells in the associated row to the data out conductors; androw addressing circuitry configured to allow selection of the read enable conductors in alternative first and second modes, wherein in the first mode each of the read enable conductors is individually selectable to read data from the cells in only the row associated with the selected read enable conductor to the data out conductors, and wherein in the second mode multiple read enable conductors are selectable in parallel to cause each data out conductor to convey a signal which is a logical combination of the data stored in the cells in (1) the column associated with that data out conductor and (2) the rows associated with the selected read enable conductors.