Patent ID: 6108745
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A computer system that implements multi-cache line interleaving comprising:a processor that generates an m bit address to facilitate memory accesses, wherein address bits of the m bit address are arranged in ascending order from a least significant 0 address bit to a most significant m-1 address bit;a main memory unit that is 2.sup.h bytes wide and is addressed via bank bits, row bits, and l column bits;a cache memory coupled to the processor, the cache memory holding a subset of contents of the main memory unit, wherein the cache memory is organized into a series of cache lines, and each cache line is 2.sup.q bytes wide; andmemory controller coupled between the main memory unit and the cache memory, wherein the memory controller generates from the m bit address the bank, row, and column bits required by the main memory unit, with each address bit more significant than the h-1 address bit and less significant than the q+1 address bit mapped to a column bit, one or more address bits more significant than the q address bit and less significant than the h+l-1 address bit used to generate a first set of one or more bank bits, one or more address bits more significant than the q address bit and less significant than the h+1 address bit mapped to column bits, and one or more address bits mapped to row bits.