Patent ID: 6034920
Filing Date: 2000-03-07
Classification: G11C

Abstract:
A semiconductor memory device, comprising:an address buffer having an input and an output;a pre-decoder circuit coupled to receive the output of the address buffer;a memory array coupled to receive an output of the pre-decoder circuit;a main amplifier coupled to receive an output of the memory array;an address transition detector (ATD) pulse generator circuit coupled to receive the output of the address buffer;a pulse delay circuit coupled to receive an output of the address transition detector pulse generator circuit, and the pulse delay circuit coupled to provide a main amplifier signal to the main amplifier; anda voltage generator generating a back gate voltage, the voltage generator coupled to provide the back gate voltage to cells in the memory array and as a low voltage supply for the address transition detector (ATD) pulse generator circuit and the pulse delay circuit;the address transition detector (ATD) pulse generator and the pulse delay circuit having a delay that is controlled by the back gate voltage and has a reduced dependency on a high voltage supply of the memory device.