Patent ID: 6396727
Filing Date: 2002-05-28
Classification: H01L

Abstract:
An integrated circuit memory device comprising:a substrate; an address decoder coupled to an address bus to receive an address, the address decoder being structured to generate row and column address signals corresponding to the address; a memory array fabricated on the substrate, the memory array including a plurality of memory cells arranged in rows and columns, a plurality of row circuits fabricated on the substrate, each of the row circuits being coupled through a respective word line to a respective row of memory cells and being constructed to activate the respective row of memory cells responsive to a respective one of the row address signals, the array further including a sense amplifier fabricated on the substrate for each column of the array, the sense amplifier being coupled to a pair of complimentary digit lines for the respective column, at least one of the complimentary digit lines being coupled to each memory cell in the respective column, the digit lines for each column extending parallel and adjacent each other and having a first thickness in a direction normal to the substrate surface; a data path coupled to data bus, the data path being structured to couple data to or from a memory cell in the activated row of memory cells and a column corresponding to the column address; and a conductive path disposed on the substrate having a second thickness in the direction normal to the substrate surface, the second thickness being greater than the first thickness.