Patent ID: 7793293
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. In a computer system, an arrangement for coordinating scheduling of threads on a plurality of processor sets (PSETs), each of said plurality of PSETs having a plurality of processors, comprising: a first processor set (PSET) having a first plurality of processors and a first set of scheduling resources, said first set of scheduling resources including at least two of a first thread launcher, a first thread balancer, and a first thread stealer; and a second processor set (PSET) having a second plurality of processors and a second set of scheduling resources, said second set of scheduling resources including at least two of a second thread launcher, a second thread balancer, and a second thread stealer, wherein said first set of scheduling resources is configured to schedule threads assigned to said first PSET only among processors of said first plurality of processors and said second set of scheduling resources is configured to schedule threads assigned to said second PSET only among processors of said second plurality of processors, wherein each of the first thread launcher and second thread launcher is configured to launch a thread on a corresponding processor of a corresponding one of the first and second PSETS, wherein each of the first thread balancer and second thread balancer is configured to balance threads across processors by shifting threads from one or more processors to one or more other processors according to processor loads in a corresponding one of the first and second PSETs, and wherein each of the first thread stealer and second thread stealer is configured to shift a thread from one processor to another idle processor of a corresponding one of the first and second PSETs.