Patent ID: 8934591
Filing Date: 2015-01-13
Classification: H04L

Abstract:
1. A clock and data recovery (CDR) circuit, comprising: an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit, wherein, a rate ratio of input serial data to any of clock signals provided by the n-phase clock is m; n/m is a natural number greater than 2, m is a natural number greater than zero; the sampling and edge detection unit comprises: a first sampling group, an edge detection group and a second sampling group; the first sampling group comprises n samplers, and the n samplers in the first sampling group sample the input serial data using n clocks provided by the n-phase clock respectively, wherein a clock used by an i-th sampler in the first sampling group is an i-th clock provided by the n-phase clock where 0≦i<n; the edge detection group comprises n edge detectors, and the n edge detectors are adapted to detect an edge between adjacent sampling points sampled by the first sampling group, wherein a j-th edge detector in the edge detection group is adapted to detect an edge between adjacent sampling points sampled by j-th and (j+1)-th samplers in the first sampling group where 0≦j<n−1, and wherein an (n−1)-th edge detector in the edge detection group is adapted to detect an edge between adjacent sampling points sampled by (n−1)-th and 0-th samplers in the first sampling group; the second sampling group comprises n samplers, and the n samplers in the second sampling group are adapted to sample edge information detected by the n edge detectors respectively, wherein an i-th sampler in the second sampling group is adapted to sample edge information detected by an i-th edge detector where 0≦i<n; the edge determination unit comprises n/m counting units, wherein a k-th counting unit is adapted to count a sum of sampled edge information from m samplers in the second sampling group whose numbers can be marked as k+n/m×t where t is a natural number ranging from 0 to m−1; when a counting value of an s-th counting unit of the n/m counting units reaches a predetermined modulus, the s-th counting unit disables or resets all other counting units of the n/m counting units, and outputs a valid signal to the clock picking unit, where 0≦k<n/m, 0≦s<n/m; sampling clocks for the first sampling group, sampling clocks for the second sampling group and counting clocks for each of the counting units are provided by the n-phase clock; the clock picking unit is adapted to select, upon receiving the valid signal output from the s-th counting unit, m clocks from the n clocks provided by the n-phase clock, each of which has a largest phase difference with one of m corresponding clock groups, and to determine a logical sum of the m clocks having the largest phase differences to be a recovered clock, wherein a t-th corresponding clock group of the m corresponding clock groups comprises two clocks, numbered (s+n/m×t) and (s+n/m×t+1); the data picking unit is adapted to sample the input serial data using the recovered clock obtained by the clock picking unit, sampled data being recovered data of the CDR circuit.