Patent ID: 7600023
Filing Date: 2009-10-06
Classification: G06F,H04L

Abstract:
1. A system for balancing crossbar bandwidth in a multiprocessing system, comprising: a crossbar switch connected to shared memory resources, the crossbar switch having a plurality of links each to a plurality of processors in the multiprocessing system; a plurality of synchronizers provided in the crossbar switch, the plurality of synchronizers configured to receive micropackets from the plurality of links, the plurality of synchronizers converting at least some of the received micropackets to higher speeds for the crossbar switch by inserting invalid micropackets; at least one wait register in the crossbar switch, the at least one wait register encoded for each possible number of valid micropackets in a maximum length micropacket expected to be received over the plurality of links, the at least one wait register not accepting invalid micropackets; a bypass path around the at least one wait register; an arbitrator operatively associated with the at least one wait register and the bypass path, the arbitrator determining which micropackets are output from the crossbar switch only if a threshold is satisfied; and a routing agent operatively associated with the at least one wait register and the bypass path, the routing agent writing only valid micropackets to the wait register, the routing agent routing both valid and invalid micropackets past the wait register if the wait register is empty and the threshold is satisfied.