Patent ID: 7164604
Filing Date: 2007-01-16
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory, comprising: a memory cell, composed of a memory cell transistor having a floating gate and a control gate and a memory cell selecting transistor; a word line, connected to a gate of the memory cell selecting transistor; a bit line, connected to a drain of the memory cell; a reference cell, composed of a reference cell transistor, which has a same structure as the memory cell transistor and to a floating gate of which a predetermined potential is applied, and a reference cell selecting transistor; a reference word line, connected to agate of the reference cell selecting transistor; a reference bit line, connected to a drain of the reference cell; a column decoder, for selecting the bit line of the memory cell in response to an input column address; a differential sense amplifier, for comparing/deciding a current of the selected bit line and a current of the reference bit line in a reading operation; and a reference word line potential generating circuit for generating a reference word line potential applied to the reference word line; wherein the reference word line potential is a first potential between a potential applied to the selected word line and a potential applied to the unselected word line.