Patent ID: 7826271
Filing Date: 2010-11-02
Classification: G11C

Abstract:
1. A nonvolatile memory, comprising: an array of memory cells, wherein each memory cell is programmable to a respective target state; read/write circuits for reading and programming a group of memory cells in parallel; a program index for each memory cell of the group under programming, the program index of a memory cell indicating the last programming voltage level used to program the memory cell; said read/write circuits performing programming that comprises: (a) applying a programming voltage as a series of incrementing voltage pulses in a programming pass to the group of memory cells; and (b) allowing programming or inhibiting programming of a memory cell during the programming pass according to the program index of the cell; and wherein said read/write circuits performing programming further comprising: (c) verifying the memory cells of the group relative to their respective target states; (d) updating the program index for a memory cell not verified by a predetermined increment to reflect the last programming voltage level to be used in a next programming pass, and enabling the memory cell not verified for further programming in the next programming pass; and (e) repeating (a) to (d) until the memory cells of the group have been verified relative to their respective target threshold voltage levels.