Patent ID: 7099193
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a NAND cell with a plurality of electrically data rewritable memory cells being connected in series; word lines connected to control gates of said memory cells; a common source line connectable to one end of said NAND cell; a bit line connectable to a remaining end of said NAND cell; and a word line control circuit, wherein said word line control circuit supplies a word line of a selected memory cell with a write voltage for writing data into this memory cell, supplies a word line of a memory cell located on the common source line side by N (N is an integer greater than or equal to 2) cells from said selected memory cell with a reference voltage for causing this memory cell to cut off, supplies an auxiliary voltage less than said write voltage to respective word lines of N−1 memory cells located between said selected memory cell and said memory cell at the position of said N cells, and supplies to word lines of remaining memory cells an intermediate voltage between said write voltage and said reference voltage.