Patent ID: 7510908
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A wafer level method of packaging integrated circuits comprising: cutting a matrix of channels in a semiconductor wafer; dispensing a light blocking filler material into the channels; and dicing the semiconductor wafer by cutting the wafer along the channels and through the light blocking filler material, wherein the dicing cuts are narrower than the channels such that some of the light blocking filler material covers at least portions of side walls of the dice that are singulated by the dicing operation, wherein dispensing the light blocking filler material in the channels comprises: applying the light blocking filler material to a stamp having a multiplicity of dispensing fins; and aligning the stamp over the semiconductor wafer such that the multiplicity of dispensing fins is aligned with the channels, thereby allowing the light blocking filler material to dispense into the channels.