Patent ID: 6088775
Filing Date: 2000-07-11
Classification: G11B

Abstract:
A data access controller comprising:means of memorizing data;means of generating addresses for making access to said memory means in correspondence to multiple kinds of processes; andmeans of providing the addresses on a time-slice basis for said memory means,wherein said memory means is accessed for data reading and writing at addresses given on a time-slice basis by said address providing means, and said address generation means generates addresses such that reading-out of data from a certain memory address by a certain one of the multiple kinds of processes takes place earlier by a prescribed time than writing of data to a memory address by a certain other process of said multiple kinds of processes, wherein said multiple kinds of processes include a data modulation process, a data demodulation process, an ECC encoding process for appending C1 and C2 parities to data, and an error detection/correction process which is based on the C1 and C2 parities.