Patent ID: 9147595
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; and a plurality of active pillars disposed on the substrate and spaced apart from each other by first trenches and second trenches which are alternately arrayed, each of the active pillars including an active region stacked on a buried metal silicide pattern; a filling insulation layer that fills the first trenches; and a partial insulation layer disposed in the second trenches and having an upper surface that is level with bottom surfaces of the buried metal silicide patterns; capping insulation patterns disposed on the plurality of active pillars; spacers disposed on sidewalls of the capping insulation patterns, the spacers extending onto sidewalls of the transistor active regions of the second trenches under the capping insulation patterns, wherein lower surfaces of the spacers are level with upper surfaces of the buried metal silicide patterns; and a lower insulation pattern extending between spacers on sidewalls and defining an air gap between the partial insulation layer and the lower insulation pattern.