Patent ID: 6285622
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A semiconductor device comprising:a first internal potential generating circuit including:a first detector for detecting a deviation of an internal potential from a predetermined level,a buffer circuit for receiving an output of said first detector,a control circuit for supplying a clock enable signal which becomes disable regardless of an output of said buffer circuit when an activation signal indicates an inactive state, and is responsive to the output of said buffer circuit when said activation signal indicates an active state,a first oscillator for oscillating a first clock signal in response to said clock enable signal, anda first charge pump for generating said internal potential at an output node, according to said first clock signal; anda second internal potential generating circuit including:a second detector for detecting a deviation of the internal potential from said predetermined level, said second detector being ahead of said first detector in detecting,a second oscillator for oscillating a second clock signal in response to the output of said second detector, anda second charge pump for generating said internal potential at said output node, according to said second clock signal.