Patent ID: 6990567
Filing Date: 2006-01-24
Classification: G06F

Abstract:
1. An apparatus comprising: a processor (i) comprising a number of internal general purpose registers and (ii) configured to manipulate contents of said internal general purpose registers in response to instruction codes of a first instruction set; a processor interface circuit coupled to said processor; a memory interface circuit coupled to a memory device; an extension stack coupled between said processor interface and said memory interface and configured to (i) receive data from and present data to said memory interface circuit and (ii) receive data from and present data to said processor interface circuit; a translator circuit (i) coupled between said processor interface and said memory interface and (ii) configured to implement a stack using one or more of said internal general purpose registers of said processor and said extension stack; a first multiplexer circuit configured to multiplex data received from (i) said memory interface circuit, (ii) said extension stack and (iii) said translator circuit for presentation to said processor interface circuit; and a second multiplexer circuit configured to (i) multiplex data received from said processor interface circuit and data received from said extension stack for presentation to a first input of said memory interface circuit and (ii) multiplex address information received from said processor interface circuit and address information received from said translator circuit for presentation to a second input of said memory interface circuit.