Patent ID: 6148009
Filing Date: 2000-11-14
Classification: H03L,H04J

Abstract:
A timing signal supplying device in a doubled timing synchronous system having a doubled timing signal supplying circuit with a transmitting buffer and a timing signal receiving circuit, said device comprising:a timing signal adjusting portion for feeding back a timing signal for said timing signal receiving circuit and a frequency signal of said transmitting buffer to regenerate a timing signal and for comparing a timing signal with an external input timing signal to detect and correct an error of a timing signal; anda timing signal transmitting portion for sequentially transmitting the corrected signal of said timing signal adjusting portion and the regenerated timing signal to said timing signal receiving circuit, wherein said timing signal adjusting portion is comprised of: a receiving buffer for inputting the timing signal and the clock signal from said transmitting buffer; a multiplexer for connecting an input timing signal, upon an initial operation of the system, to an output terminal thereof and for connecting an output timing signal inputted from said receiving buffer, upon a normal operation of the system, to an output terminal thereof; a timing signal regenerator connected to said multiplexer, said receiving buffer and said transmitting buffer, for inputting the clock signal from said receiving buffer to generate a regenerated timing signal in accordance with a synchronous timing signal inputted from said multiplexer; and a timing signal comparing processor connected to said timing signal regenerator and a phase locked loop circuit, for detecting timing error in the input timing signal and the regenerated timing signal to output the detected timing error to said phase locked loop circuit.