Patent ID: 6145051
Filing Date: 2000-11-07
Classification: G06F,G11C

Abstract:
A memory controller for use with a host requiring access to a nonvolatile memory, the controller being responsive to commands and logical block addresses (LBA's) received from the host, a group of LBAs for identifying one or more information blocks to be accessed in the nonvolatile memory, each of the information blocks including a plurality of N sectors, the nonvolatile memory including a plurality of selectively erasable block locations, each of the block locations having a plurality of physical block address locations (PBA locations), each of the PBA locations for storing a portion of an information block, the controller being operative to develop physical block addresses (PBA's) for addressing corresponding ones of the PBA locations, the controller also being operative to access portions of an information block stored in more than one of the block locations, whereby the controller avoids transfer of a particular information block from one block location to another block location each time the host requests that a portion of the particular information block be rewritten.