Patent ID: 6204121
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method of fabricating a bottom electrode of a capacitor, comprising:providing a substrate wherein a transistor is formed thereon and the transistor contains a source/drain region;forming a dielectric layer having a contact hole over the substrate wherein a portion of the source/drain region is exposed by the contact hole;forming a doped polysilicon layer over the substrate to fill the contact hole;forming an insulating layer on the doped polysilicon layer;forming an amorphous silicon layer on the insulating layer;defining the amorphous silicon layer, the insulating layer and the doped polysilicon layer to form a main structure of the bottom electrode directly above the contact hole;forming amorphous silicon spacers on sidewalls of the main structure; andforming a hemispherical grained silicon layer on the amorphous silicon layer and the amorphous silicon spacers.