Patent ID: 8351248
Filing Date: 2013-01-08
Classification: G11C

Abstract:
1. An integrated circuit (IC), comprising: a memory cell having a first PMOS transistor formed in N-type semiconductor material having a first PMOS source coupled to a PMOS bias terminal providing a PMOS bias voltage and a first PMOS drain coupled to a first intermediate node; a first NMOS transistor formed in P-type semiconductor material having a first NMOS source coupled to an NMOS bias terminal providing an NMOS bias voltage and a first NMOS drain coupled to the first intermediate node; and wherein the N-type semiconductor material forms an N-well in the P-type semiconductor material; a well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material, wherein the well bias line: wherein the well bias voltage is a positive voltage and the well bias line is coupled to the N-well; wherein the first PMOS transistor comprises: