Patent ID: 6073227
Filing Date: 2000-06-06
Classification: G06F

Abstract:
An electrical circuit for moving data blocks from a source memory unit to a target memory unit by means of a data path, wherein the data blocks moved are not framed in the source memory and the target memory, comprising a circuit for performing a framing with a granularity equal to the width of the data path, said circuit comprising:means for generating read addresses in the source memory,means for generating write addresses in the target memory, andstorage means with a capacity equal to that of the content of a single block, said storage means being subdivided into sub-blocks with a size which corresponds to the framing granularity, said storage means comprising a list in which the writing of blocks originating from the source memory is done in sub-blocks by means of a pointer contained in a first register DSWP initialized at a value equal to the framing deviation between the source memory and the target memory, and in which the reading of blocks to be transferred to the target memory is done in sub-blocks by means of a pointer contained in a second register DSRP.