Patent ID: 6714448
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A method of programming a multi-level memory device comprising:applying a plurality of programming pulses to a set of memory cells of the memory device to place an amount of charge on a floating gate of each of said memory cells, said programming pulses increasing incrementally in voltage to increase the amount of charge on the floating gate until the amount of charge on the floating gate is equal to a desired amount of charge corresponding to a desired memory state of the memory cell; applying a plurality of verify pulses to the set of memory cells, each one of said verify pulses being applied after each one of the said programming pulses in an alternating manner, wherein said set of memory cells consists of a first subset of memory cells having a first desired memory state equal to a highest voltage memory state in which the cell has a highest amount of charge and a second subset of memory cells in which each memory cell has a respective second desired memory state that is less than the highest memory state; determining that each memory cell in the second subset of memory cells has been programmed to the respective second desired voltage memory state of each cell; and applying a maximum voltage programming pulse to each memory cell in the first subset of memory cells, wherein said maximum voltage programming pulse is equal to a voltage threshold level that results in the memory cell being in the first desired voltage memory state.