Patent ID: 7003635
Filing Date: 2006-02-21
Classification: G06F

Abstract:
1. A method of ensuring data consistency in a computer system having a plurality of data processing entities and a shared memory organized into a plurality of memory blocks, at least some of the data processing entities configured to issue requests for selected memory blocks, the method comprising: issuing from a plurality of data processing entities a sequence of writes targeting a given memory block; linking the writes to the given memory block into a write chain, the write chain specifying a last data processing entity in the sequence, and being free from having one or more reads targeting the given memory block; at each data processing entity in the write chain other than the last data processing entity, storing information that identifies the next data processing entity in the write chain; and at each data processing entity in the write chain other than the last data processing entity, ensuring that the prior data processing entity completed its write before completing the current write.