Patent ID: 6642589
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:(a) forming an isolation region in a silicon substrate having a principal surface to define first and second active regions; (b) forming a gate insulating film in the first and second active regions; (c) forming a conductive gate electrode layer on the gate insulating film; (d) pattering the gate electrode layer and the gate insulating film to form a first insulated gate on the first active region and a second insulated gate on the second active region; (e) implanting n-type impurity ions into the first and second active regions to a first depth to form first and second extension regions on both sides of each of the first and second insulated gates; (f) masking the second active region and implanting indium ions at a first dose into the first active region to a second depth deeper than the first depth; and (g) masking the first active region and implanting indium ions at a second dose smaller than the first dose into the second active region to a third depth deeper than the first depth.