Patent ID: 7009604
Filing Date: 2006-03-07
Classification: G09G

Abstract:
1. A frame detector configured to operate in a plurality of frame detection modes, the frame detector comprising: a measurement unit configured to generate data indicative of a duration of each of a plurality of pulses included in a composite synchronization signal; a counter configured to generate data indicative of a number of successive occurrences of pulses having a same duration; a memory coupled to the measurement unit and the counter and configured to store pattern data detected during each of a plurality of fields, wherein the pattern data for each field includes data indicative of two or more pulse durations generated by the measurement unit, wherein the pattern data for each field further includes data indicative of two or more counts generated by the counter, wherein each count is associated with a respective one of the two or more pulse durations; a control unit coupled to the memory and configured to perform a comparison of the pattern data stored during each of the plurality of fields and to identify which pattern data identifies a first field in a frame dependent on the comparison; and a mode register coupled to the control unit; wherein storing one value of a plurality of values in the mode register determines a corresponding mode of operation of the frame detector, and wherein one of the corresponding modes is a training mode in which the frame detector is supplied with the composite synchronization signal and a frame signal corresponding to the frame signal encoded in the composite synchronization signal.