Patent ID: 6770963
Filing Date: 2004-08-03
Classification: H01L

Abstract:
An IC package, comprising:an IC chip mounting surface periphery defining a chip mounting surface; a first plurality of electrically isolated conductive package bonding lands distally spaced apart from said chip mounting surface periphery; a second plurality of spaced apart, electrically isolated annular power-ring bonding segments; each one of said second plurality of annular power-ring bonding segments being disposed and extended annularly along and disposed and extended distally from said IC chip mounting surface periphery to a respective annular extent and a respective distal lateral width, said annular extent and said lateral width defining a respective maximum available number (Nm) of sequentially ordered annularly spaced apart bonding locations; wherein, for each of said second plurality of annular power-ring bonding segments, a respective selected combination (Nb) of sequentially ordered annularly spaced apart bonding locations may be selected from respective combinations of said Nm bonding locations at a time, where both Nb and Nm are integers and Nb is less than Nm; whereby each said annular bonding segment provides a respective contiguous annular electrode for connecting respective ones of a corresponding set of Nb conductive members arranged in corresponding annularly spaced sequential order to corresponding annularly spaced sequentially ordered chip power bonding pads of a respective power net disposed on an IC chip mounted on said IC chip mounting surface.