Patent ID: 7477226
Filing Date: 2009-01-13
Classification: G09G,G11C

Abstract:
1. A shift register having a plurality of stages, each stage comprising: first, second, and third driving voltage supply lines; at least two clock signal supply lines; an output buffer having an output pull-up transistor and first arid second output pull-down transistors; a first controller having an input connected to a start signal supply line and an output connected to a first node; and a second controller having an input connected to the first and second voltage supply lines and an output connected to gates of the first and second output pull-down transistors, wherein high voltages are alternately applied to gates of the first and second output pull-down transistors every predetermined frame; wherein the first and second output pull-down transistors are connected to second and third nodes, respectively; and wherein first and second driving voltages supplied to the first and second voltage supply lines have voltages alternately inverted with respect to each other every predetermined frame.