Patent ID: 7227219
Filing Date: 2007-06-05
Classification: H01L

Abstract:
1. A charge trapping memory cell comprising: a well in a semiconductor body, said well being doped to a first conductivity type, a source region and a drain region formed at a top side of the semiconductor body and doped to a second conductivity type tat is opposite the first conductivity type; a trench formed in the semiconductor body, said trench extending into the doped well below the source and drain regions; a first gate electrode located at least in a bottom portion of the trench, said first gate electrode electrically insulated from the well by a gate dielectric; a second gate electrode extending into the trench toward said first gate electrode and arranged in the trench above the first gate electrode and electrically insulated from the first gate electrode; and a storage layer sequence comprising first and second boundary layers and a storage layer, said storage layer provided for charge trapping being sandwiched between said first and second boundary layers, and at least portions of the storage layer sequence being arranged between the second gate electrode and the doped well and/or between the second gate electrode and the source and drain regions.