Patent ID: 8522122
Filing Date: 2013-08-27
Classification: G06F,H03M

Abstract:
1. A method for locating and correcting a memory channel failure, or alternately for correcting up to t_c chip failures and detecting up to t_d chip failures in the presence of up to u chips that are marked as suspect, wherein u is a value equal to or greater than zero, t_c represents a number of simultaneous chip errors configured to be corrected and t_d represents a number of simultaneous chip errors configured to be detected or corrected, the method comprising: computing syndromes of data retrieved from a memory in a memory system comprising M channels; performing a first stage of decoding using a decoder configured to perform u-erasure, t_c error correction, and t_d error detection, the performing a first stage resulting in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state; declaring an uncorrectable error state in response to a syndrome of the recovered estimated errors not being the same as the computed syndromes of data retrieved from the memory; performing a second stage of decoding in response to the uncorrectable error state being declared, the performing a second stage comprising attempting to correct u erasures and a channel error in M iterations, changing a channel location in each iteration; and declaring a correctable error state in response to exactly one of the M iterations being successful.