Patent ID: 8756467
Filing Date: 2014-06-17
Classification: G01R

Abstract:
1. An integrated circuit comprising: a first input interconnect; a second input interconnect; an output interconnect; a shift register selected from a boundary scan register and a test data register; a bypass register; a select register; an instruction register; a test access port (TAP) controller coupled to the first input interconnect, the instruction register, and the select register, wherein the TAP controller is configured to shift a select value provided on the first input interconnect into the select register, and the TAP controller is configured to shift an opcode provided on the first input interconnect into the instruction register, and wherein the select value may be a first select value assigned to the integrated circuit or the select value may be a different second select value assigned to a second integrated circuit that is coupled to the second input interconnect; select register decode circuitry configured to control, based on the select value, which of a plurality of test data output signals is provided to the output interconnect, wherein the plurality of test data output signals includes at least a first test data output signal and a second test data output signal, and wherein the first test data output signal is provided by the shift register, and the second test data output signal is received from the second integrated circuit through the second input interconnect; and instruction decode circuitry, wherein the instruction decode circuitry is configured to map the opcode to an instruction to be executed by the TAP controller, wherein the instruction decode circuitry maps the opcode to a first instruction when the select value is the first select value, and the instruction decode circuitry maps the opcode to a second instruction when the select value is the second select value, wherein the first instruction, when executed, causes a value in the shift register to be clocked out on the output interconnect, and the second instruction, when executed, causes a value in the bypass register to be clocked out on the output interconnect.