Patent ID: 6049897
Filing Date: 2000-04-11
Classification: G06F

Abstract:
An apparatus used for checking for segment limit violations during memory access in a microprocessor capable of executing a plurality of types of memory accesses wherein each type of memory access includes accessing information of a different length in a segment of memory, said segment of memory having an address representative of the last address location within said segment of memory, said apparatus comprising:(a) an instruction decoder which establishes limit generation microcode to generate a plurality of limits from said representative address and said length of each type of memory access;(b) an instruction issue unit coupled to said instruction decoder for receiving said limit generation microcode and staging said limit generation microcode for execution;(c) an execution unit coupled to said instruction issue unit for executing said limit generation microcode and generating said plurality of limits; and(c) a plurality of registers coupled to said execution unit, said plurality of registers receiving said plurality of limits.