Patent ID: 6734063
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of producing a non-volatile memory cell with:a semiconductor structure selected from the group consisting of a semiconductor body and a semiconductor layer and having a surface; buried bit lines formed at the surface of the semiconductor structure and conductor strips on the surface applied to the bit lines; a source region and a drain region each connected by one of the bit lines; a gate dielectric formed on the surface at least between the source region and the drain region; a gate electrode disposed on the gate dielectric; and a word line electrically connected to the gate electrode, the word line crossing the bit lines and being electrically insulated from the bit lines; the method which comprises the following steps: in a first step, providing a semiconductor structure; in a second step, depositing a gate dielectric comprising a storage layer for trapping charge carriers; in a third step, depositing a layer for forming the gate electrode; in a fourth step, forming openings in the layer and forming spacers at sidewalls in the openings; in a fifth step, implanting a dopant through the openings to form the buried bit lines; in a sixth step, applying the conductor strips onto the buried bit lines, and applying electrically insulating cover layers onto the conductor strips; in a seventh step, applying at least one word line layer electrically connecting the gate electrode, and applying a hard mask layer on top of the at least one word line layer, the hard mask layer being used to structure the gate electrode and the at least one word line layer to form a word line stack; in an eighth step, etching on both sides of the word line stack between the bit lines anisotropically down into the semiconductor structure to a level below the source region and the drain region to form etch holes that are self-aligned to the word line stack; and in a ninth step, filling the etch holes with an electrically insulating material.