Patent ID: 9021169
Filing Date: 2015-04-28
Classification: G06F

Abstract:
1. A bus system, comprising: a plurality of master devices, each configured to issue a transaction request having a first transaction identifier with a first bit width; a slave device configured to respond to the transaction request having a second transaction identifier with a second bit width and to supply a transaction response having the second transaction identifier to the plurality of master devices, wherein the second bit width of the second transaction identifier is smaller than the first bit width of the first transaction identifier; a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to: wherein the ID converter comprises a register array configured to store the first transaction identifier and the second transaction identifier as a mapping entry, and wherein the ID converter further comprises a slave interface coupled to one of the plurality of the master devices, and a master interface coupled to the slave device, wherein the ID converter further comprises a read mapping unit, wherein the read mapping unit comprises: