Patent ID: 7739545
Filing Date: 2010-06-15
Classification: G01R

Abstract:
1. A computer system, comprising a computer system having a connection module having a plurality of chips mounted thereon, said chips of said connection module including a clock controller, a cache controller chip, a memory interface with memory controller and cache data chips, and a plurality of microprocessor chips, and wherein said processing chips are coupled for communication among said chips on said connection module with elastic interface multi-bit buses between the processing chips also having connection module spare nets for spare bits forming a spare network of a plurality of spare nets able to repair one or more of said elastic interface multi-bit buses such that upon repair it operates even when there is a fault in the connection module, and wherein programmable electronic fuses in said module record information about chips in said module as recorded information as to known manufacturing faults of said chips of said module, said fuses' recorded information being updatable after testing of the module to record information about any known repair by a spare bit on a spare net of said spare network, said spare nets being fully testable by checking logic for testing said spare nets on the connection module when the multi-bit buses' nets are not spared just as all normal elastic interface multi-bit buses' nets' functional bus bits are tested for function and environmental tests allowing a spare net to be used at any step in the manufacture testing or at a customer's office as a spare net to know it has met all required testing like all other functional bus bits, and wherein said checking logic is configured such that for every cycle that a value is put on one of the multi-bit buses, during testing, that said value put on the one multi-bit bus matches another value of a spare net which can be checked for operation.