Patent ID: 6778623
Filing Date: 2004-08-17
Classification: H03L,H04J,H04L

Abstract:
A circuit for synchronizing a frame clock in a data transmitting system, the circuit comprising a phase detector having at least two inputs and an output connected to the input of a voltage-controlled oscillator via a filter, at least one input of the phase detector is supplied with a clock derived from the data transmitted by the system and at least another input is supplied with an output signal of a voltage-controlled oscillator conducted over a divider such that the clock exhibits a multiple clock frequency compared to the frame clock; the divider comprises a variable divider having a variable division factor, and is connected to a frame clock phase detector for setting the division factor; the frame clock phase detector is supplied with the frame clock, the output signal of the variable divider and at least one clock signal of an output divider that divides the output signal of the voltage-controlled oscillator into an output frame clock; and the frame clock phase detector is configured for the output of a pulse that temporarily one of raises or lowers the division factor of the divider dependent on the maximum phase jitter of the clocks when the frame clock and the output frame clock deviate.