Patent ID: 6127717
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A totally self-aligned transistor with polysilicon shallow trench isolation comprising:a substrate layer, the substrate layer formed to define a plateau region having an elevation higher than the substrate layer;at least one shallow trench, the at least one shallow trench disposed adjacent to the plateau region;at least one aligning nitride island formed on top of the plateau region, the at least one nitride island defining an exposed outer area adjacent a first side of the plateau region;an oxide spacer, the oxide spacer disposed in the at least one shallow trench along the first side of the plateau region, and extending upwards to substantially cover the exposed outer area;a channel area, the channel area disposed on a top side of the plateau region and adjacent the at least one nitride island opposite to the exposed outer area;a source region and a drain region defined by removal of the at least one aligning nitride island;at least one channel dopant deposited in the channel area of the plateau region; anda gate disposed above the channel area, the gate defined by the deposition of a metal substance.