Patent ID: 6483347
Filing Date: 2002-11-19
Classification: G11C,H03K

Abstract:
A buffer circuit having an input terminal and an output terminal, comprising:a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal; a second inverter having an input node coupled to a reference voltage and to an output node; a third inverter having an input node non-invertingly coupled to the output terminal and an output node non-invertingly coupled to the output terminal; a fourth inverter having an input node non-invertingly coupled to the output node of the second inverter and an output node non-invertingly coupled to the output node of the second inverter; a fifth inverter having an input node coupled to the output node of the fist inverter and an output node coupled to the output node of the second inverter; and a sixth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output node of the first inverter.