Patent ID: 7782991
Filing Date: 2010-08-24
Classification: H03H,H04L

Abstract:
1. A multirate processing circuit, comprising a resampling filter accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate; a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate; and a subsequent discrete time processor, communicatively coupled to an output of the discrete time processor, the subsequent discrete time processor processing, at an integer power of two multiple of the first clock rate, samples produced at the output of the discrete time processor, the subsequent discrete time processor further excluding from the processing selected samples so as to effectively perform discrete time processing of the samples produced at the output of the discrete time processor at the integer power of two multiple of the second clock rate.