Patent ID: 7419864
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation insulating film, which defines first and second low-voltage transistor forming regions and first and second high-voltage transistor forming regions, on a semiconductor substrate; forming a first gate insulating film on the semiconductor substrate in the first and second high-voltage transistor forming regions; forming a second gate insulating film on the semiconductor substrate in the first and second low-voltage transistor forming regions; forming an undoped conductive film on the first and second gate insulating films; implanting selectively a first conductivity type impurity into the conductive film in the first low-voltage transistor forming region and the first and second high-voltage transistor forming regions; patterning the conductive film after the first conductivity type impurity is implanted, to form first and second gate electrodes in the first and second low-voltage transistor forming regions respectively and form third and fourth gate electrodes in the first and second high-voltage transistor forming regions respectively; forming selectively first and second source/drain extensions of first conductivity type on the semiconductor substrate beside the first and third gate electrodes respectively; forming selectively third and fourth source/drain extensions of second conductivity type, which is opposite to the first conductivity type, on the semiconductor substrate beside the second and fourth gate electrodes respectively; forming first to fourth insulating sidewalls beside the first to fourth gate electrodes respectively; forming low-voltage first conductivity type source/drain region away from side surfaces of the first gate electrode at a first interval after the first to fourth insulating sidewalls are formed, and forming high-voltage first conductivity type source/drain region away from side surfaces of the third gate electrode at a second interval that is wider than the first interval; forming low-voltage second conductivity type source/drain region away from side surfaces of the second gate electrode at the first interval after the first to fourth insulating sidewalls are formed, and forming high-voltage second conductivity type source/drain region away from side surfaces of the fourth gate electrode at the third interval that is wider than the first interval; and introducing a second conductivity type impurity into the second gate electrode.