Patent ID: 9104401
Filing Date: 2015-08-11
Classification: G06F,G11C

Abstract:
1. A flash memory apparatus with a serial interface, comprising: a command receiver, coupled to a clock pin and a data input pin of the flash memory apparatus, and sequentially receiving a plurality of command data through the data input pin and the clock pin; a command decoder, coupled to the command receiver, receiving a command sequence which comprises a first command data and a second command data, and comparing the command sequence with a reference sequence to generate a reset signal; and a core circuit, coupled to the command decoder, for receiving the reset signal to activate a reset operation according to the reset signal, wherein the first command data represents that the reset operation of the flash memory apparatus is ready to be activated, the second command data represents activating the reset operation of the flash memory apparatus, and an occurrence sequence of all of the command data in the command sequence is fixed.