Patent ID: 6721230
Filing Date: 2004-04-13
Classification: G11C

Abstract:
An integrated memory, comprising:memory cells disposed in at least first and second memory cell blocks; read amplifiers; data lines respectively connected to said read amplifiers; writable register circuits to be written from outside the memory; each of said memory cells respectively read out through one of said read amplifiers and one of said data lines connected to said one read amplifier; at least a dedicated one of said data lines being associated with each of said memory cell blocks for reading data from said memory cell blocks; at least a dedicated one of said register circuits being associated with each of said memory cell blocks; said register circuits adapted to store data and to compare the stored data with data applied to a respective one of said register circuits; and said dedicated one of said register circuits associated with a given one of said memory cell blocks being connected to said dedicated one of said data lines associated with said given memory cell block, said dedicated one of said register circuits adapted to compare data read out of said given memory cell block with the data stored in said dedicated one of said register circuits.