Patent ID: 6292237
Filing Date: 2001-09-18
Classification: G02F,G09G

Abstract:
A substrate for an active-matrix liquid crystal display device, comprising:a plurality of data lines and a plurality of gate lines arranged in a matrix on the substrate;thin-film transistors, having pixel electrodes connected thereto so as to form desired pixel regions, arranged on both sides of each data line corresponding to the respective gate line, the plurality of gate lines being arranged so that the pixel electrodes on both sides of each data line are controlled by signals from corresponding paired gate lines sandwiching the pixel electrodes arranged on both sides of the data line; anda first capacitor electrode being located on the other gate line paired with the one controlling gate line which drives one of first and second pixel regions positioned between the adjacent data lines, said first capacitor electrode linearly extending across a central line of said adjacent data lines from the vicinity of the data line located in proximity with the pixel electrode corresponding to said first pixel region to said thin-film transistor which is connected to the pixel electrode corresponding to said second pixel region and which is controlled by a signal from the other gate line; anda second capacitor electrode extending from said first capacitor electrode and passing through the pixel electrode corresponding to said first pixel region so that said second capacitor electrode partially overlaps with said pixel electrode, said second capacitor electrode being electrically connected to said pixel electrode;wherein the other gate line is located below said first capacitor electrode and said second capacitor electrode and has an outer configuration matching the outer configurations of said first capacitor electrode and said second capacitor electrode; andwherein a storage capacitor corresponding to each of said first and second pixel regions is formed by said first and second capacitor electrodes corresponding to each of said first and second pixel regions and by the other gate line located below said first and second capacitor electrodes.