Patent ID: 6803644
Filing Date: 2004-10-12
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit device comprising:a semiconductor substrate of a second conductivity type; a plurality of first well regions of a first conductivity type formed in said semiconductor substrate; at least a first zener diode and a second zener diode connected in series and comprised of (i) one of said first well regions, (ii) at least two spaced-apart, second well regions of said second conductivity type formed in said one first well region, each of said second well regions being associated with different ones of said zener diodes, (iii) first semiconductor regions of said first conductivity type formed in said second well regions, respectively, and (iv) second semiconductor regions of said second conductivity type formed at a bottom portion of said first semiconductor regions, respectively, and each being smaller in area, defined by a planar pattern thereof, than said first semiconductor region corresponding thereto; an insulation film formed over a primary face of said semiconductor substrate; a plurality of first connection holes for providing electrical connections therethrough to said first semiconductor regions and a plurality of second connection holes for providing electrical connections therethrough to said second well regions being formed in said insulation film; and a wiring formed over said insulation film and connecting said first connection holes which are for electrical connection to the first semiconductor region of said first zener diode and said second connection holes which are for electrical connection to the second well region of said second zener diode, wherein said first connection holes associated with said first zener diode are arranged in a region located outside a junction formed between said first semiconductor region and said second semiconductor region of said first zener diode, wherein a first PN junction is formed between ones of said first semiconductor regions and corresponding ones of said second semiconductor regions and functions as a diode device, and a second PN junction is formed between said one first well region and said second well regions, respectively, and has a breakdown voltage greater than that of said first PN junction, wherein a junction depth of each of said first semiconductor regions in a region in which said first PN junction is formed is shallower than that of each of said first semiconductor regions in a region in which said first PN junction is not formed, and wherein a MISFET is formed in another one of said first well regions.