Patent ID: 6947342
Filing Date: 2005-09-20
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: a memory cell array including a plurality of memory cells, the memory cells being connected to a plurality of pairs of complementary bit lines; a first voltage decreasing section for generating a predetermined voltage lower than a power supply voltage; a precharge circuit for generating a precharge voltage lower than the power supply voltage; and an equalizing section to which the predetermined voltage is supplied from the first voltage decreasing section and the precharge voltage from precharge circuit, and which performs an equalizing operation to charge the pairs of complementary bit lines to a predetermined equal potential before reading of information from the memory cells to the pairs of complementary bit lines, wherein the equalizing section is formed by a first equalizing section, which is provided at one side of the memory cell array, and a second equalizing section, which is provided at the other side of the memory cell array, the first voltage decreasing section supplies an electric power to the first equalizing section for equalizing a selected pair of complementary bit lines and their corresponding node lines, and the precharge circuit supplies an electric power to the second equalizing section for precharging the plurality of pairs of complementary bit lines.