Patent ID: 6385759
Filing Date: 2002-05-07
Classification: G06F

Abstract:
In a logic circuit having a plurality of gate paths leading from a plurality of input flip-flops to a plurality of output flip-flops, at least some of said input and output flip-flops being triggered by a triggering edge of a first clock and at least some of said input and output flip-flops being triggered by a triggering edge of a second clock, said first and second clocks having a smallest common multiplier period (SCMP);a method for reducing the memory capacity requirement for static timing analysis; the method comprising the steps of: a) starting at the output flip-flop end of each said path, conducting a depth first search to the input end of each said path to set said triggering edges at respective input flip-flops to TE(C,e,n,m) where C=the clock number defined by its rise time, fall time and period; e=rise or fall depending on whether the respective flip-flop is rising edge triggered or falling edge triggered; n is an edge number and n=O and m=number of cycles in multi-cycle path or zero if path is not multi-cycle and propagating the list of input flip-flop triggering edges to the output flip-flop inputs; b) determining output triggering edges at said output flip-flops wherein for each such output flip-flop having an incoming list of N input flip-flop triggering edges (TET1 . . . TETN), assigning a triggering edge (nte) from said list by calculating nte=&LeftCeiling;MAX&af;(TET1,â€¦&it;â€ƒ,TETN)-TET&af;(C,e,0,0)&RightCeiling;pwhere triggering edge time (TET) is defined as TET&af;(C,e,n,m)={r+np;if&it;â€ƒ&it;(e=rise)r+np;if&it;â€ƒ&it;(e=fall)where: C is a clock (r,f,p), 0&lE;n&lE;(SCMP)/p, and p is clock period; andc) propagating said output triggering edges backward in the form of a list at each net of all said paths.