Patent ID: 6156637
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method of depositing a dielectric ply structure to improve the planarity of electronic devices integrated on a semiconductor substrate, which devices include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, said lines being isolated from one another by a first dielectric layer which also fills gaps therebetween and each having an upper conductive layer, the method comprising the following steps:depositing a second dielectric layer to planarize the surface of the semiconductor substrate;rapid thermal annealing to reflow the second dielectric layers;dry etching the dielectric layers to an extent that exposes the conductive layers of the lines after the rapid thermal annealing step; andforming conductive interconnection lines on the exposed conductive layers of the lines, the interconnection lines being transverse to the lines.