Patent ID: 8239841
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A method, in a data processing system, for prefetching irregular memory references into a software controlled cache, the method comprising: receiving source code that is to be compiled; analyzing the source code to identify at least one of a plurality of loops that contain an irregular memory reference; determining if the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization; responsive to an indication that the irregular memory reference may be optimized, determining if the irregular memory reference is valid for prefetching; responsive to an indication that the irregular memory reference is valid for prefetching, inserting a store statement for an address of the irregular memory reference into the at least one of the plurality of loops; inserting a runtime library call into a prefetch runtime library for the irregular memory reference, wherein data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked; and wherein determining if the irregular memory reference within the at least one of the plurality of loops is the candidate for optimization comprises: determining if a computed address accessed by the irregular memory reference is an affine function of a loop index variable; responsive to the address failing to be the affine function of the loop index variable, determining if there is a loop-carried dependency between statements used in the computed address; and responsive to failure to identify any loop-carried dependencies, indicating the irregular memory reference as the candidate for optimization.