Patent ID: 6456058
Filing Date: 2002-09-24
Classification: G01R,H03K

Abstract:
A full wave level detector having an input node for receiving an input signal and an output node for providing a corresponding output signal, said detector comprising:an amplifier coupled to receive said input signal through a first resistor (R1) on an input terminal thereof; first and second switching devices having control terminals thereof coupled to said input terminal of said amplifier; second (R2), third (R3) and fourth (R4) resistors coupled to an output terminal of said amplifier, said second resistor being coupled to said input terminal of said amplifier and said third and fourth resistors being respectively coupled to a first current carrying terminal of said first and second switching devices; a first current mirror having first and second legs thereof respectively coupling a second current carrying terminal of each of said first and second switching devices to a first supply voltage source, said second current carrying terminal of said second switching device defining a circuit node; a second current mirror having first and second legs thereof, said first leg thereof coupling a second supply voltage source to said circuit node; a third current mirror having first and second legs thereof respectively coupled through a fifth resistor (R5) to a reference voltage source and said second leg thereof coupled to said second leg of said second current mirror; and an output driver coupling said circuit node to said output node and providing said output signal to the output node, wherein said output signal is at a first logic level when an absolute value of said input signal is less than R1/R2 times said reference voltage and wherein said output signal is at a second logic level when an absolute value of said input signal is greater than R1/R2 times said reference voltage.