Patent ID: 6604174
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A multiport cache system comprising:a cache having a plurality of ways each having a plurality of lines, each line having a plurality of data locations; a tag having a plurality of tag entries, each tag entry corresponding to one of the data locations, each tag entry having an identification indicating which one of a plurality of processes is assigned to a corresponding one of the data locations; and a memory controller having: a Tag Allocation Controller (TAC) dynamically allocating the plurality of processes to the plurality of ways, the TAC reallocating the plurality of processes to the plurality of ways based on periodic evaluations of system performance; and a way assignment memory having entries each defining which way is assigned to which process; a processes-to-cache multiplexor, coupled to a plurality of buses and to write ports of the cache, having a plurality of multiplexors each having input coupled to the buses and one output coupled to one of the write ports of the cache; and a cache-to-processes multiplexor, coupled to a plurality of buses to read ports of the cache, having a plurality of multiplexors each having inputs coupled to the buses and one output coupled to one of the read ports of the cache.