Patent ID: 6789099
Filing Date: 2004-09-07
Classification: G06F

Abstract:
An N-bit two level lookahead adder for adding two N-bit numbers, comprising summing means for calculating alternative partial M-bit sums;a first set of carry modules for generating gi, pi and ki signals for each of the N bits; a second set of carry modules, responsive to said gi, pi and ki signals, for generating a set of M-bit G, P and K signals therefrom, each of said set of carry modules having a sense amplifier connected to a logic evaluation module containing two connecting nodes connected to said sense amplifier, and a chain of source follower transistors having a first node, a final node and a set of intermediate nodes controllably connected to both said two connecting nodes by first and second sets of connecting transistors, first precharge means for precharging each of said set of two connecting nodes to ground; means for charging said first node to a reference voltage other than ground in an evaluation mode; and a set of output modules, responsive to said set of carry signals, for selecting alternative partial sums and connecting a selected set of said alternative partial sums to a set of output terminals.