Patent ID: 7498636
Filing Date: 2009-03-03
Classification: H01L

Abstract:
1. A semiconductor device including a semiconductor layer having a channel region and a diffusion region sandwiching said channel region, and an element separation layer formed on a supporting substrate through a first insulating layer, said semiconductor device comprising: a gate electrode formed on said channel region of said semiconductor layer through a second insulating layer; a third insulating layer formed on said element separation layer, said semiconductor layer, and said gate electrode; a first wiring layer formed on said third insulating layer; a first conductor penetrating said third insulating layer, said element separation layer, and said first insulating layer so as to electrically connect to said supporting substrate; a second conductor penetrating said third insulating layer so as to electrically connect to said gate electrode; a third conductor penetrating said third insulating layer so as to electrically connect to said diffusion region of said semiconductor layer; a top layer wire formed on said first wiring layer through a fourth insulating layer so as to provide electrical connection between said first conductor and said second conductor or said third conductor; and an electrode pad formed on said top layer wire to provide electrical connection to said top layer wire.