Patent ID: 6104208
Filing Date: 2000-08-15
Classification: G11C,H03K

Abstract:
An integrated circuit, comprising:a programmable function block;a plurality of configurable memory array blocks, wherein each of said configurable memory array blocks includes,at least one configurable memory array that can be configured to store a variable length data word, wherein each of said configurable memory arrays includes,a plurality of memory cells suitable for storing a data word, wherein certain ones of said plurality of memory cells can be configurably arranged in a row-wise manner forming thereby a row of memory cells having an associated variable row length based upon a particular data word length of a particular data word to be stored in the memory array, wherein said row width being set by said programmable function block to accommodate said variable length data word;a plurality of direct connectors between the plurality of configurable memory array blocks; anda control circuit for providing control signals, said control circuit characterizes said data to be stored and based upon said characterization provides signals to said plurality of configurable memory array blocks, said signals direct selected ones of said plurality of configurable memory array blocks to configure their respective memory arrays so as to store said characterized data, andwherein said signals direct selected one or more of said direct connectors to directly connect at least two selected ones of said plurality of configurable memory array blocks so as to store said characterized data when a single configurable memory array block could not store said characterized data.