Patent ID: 6486505
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A dynamic random access memory device including a transistor device, the memory device comprising:a first source/drain region disposed in a semiconductor body; a second source/drain region disposed in the semiconductor body, the second source/drain region being spaced from the first source/drain region by a channel region; a plug contact extending out from the first source/drain region; a dielectric layer overlying the channel region; a gate electrode overlying the dielectric layer, the gate electrode including: a polysilicon layer spaced a first distance from the plug contact; and a conductive layer disposed over the polysilicon layer and spaced a second distance from the plug contact, the second distance being greater than the first distance, the conductive layer having a lower resistivity than the polysilicon layer; an insulating region disposed between the gate electrode and the plug contact; and a capacitor with a first plate coupled to the second source drain region.