Patent ID: 8149622
Filing Date: 2012-04-03
Classification: G11C

Abstract:
1. A memory system on a single chip, comprising: a NAND flash memory having a status register and a plurality of NAND cells, said plurality of NAND cells having a plurality of bit lines, a plurality of source lines in parallel with said bit lines, and a plurality of word lines perpendicular to said bit lines and said source lines; a NOR flash memory having a status register and a plurality of NOR cells, each of said NOR cells being formed by a symmetrical 2-NAND cell string and having a drain connected to a bit line, a source connected to a source line in parallel with said bit line and two floating gates connected to two word lines perpendicular to said bit line and said source line; an address bus shared by said NAND and NOR flash memories, and a data bus shared by said NAND and NOR flash memories; wherein both said address bus and said data bus are bi-directional for receiving external inputs to said memory system and transmitting outputs from said memory system, and said NAND and NOR flash memories are manufactured by a unified NAND manufacturing process and same NAND cells.