Patent ID: 9214531
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of: (a) providing a substrate; (b) forming at least two gate trenches in the substrate; (c) forming a first dielectric layer lining inner surfaces of the gate trenches; (d) forming a first polysilicon structure in the gate trenches; (e) forming at least a first trench, wherein the first trench is positioned between the neighboring gate trenches; (f) forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench; (g) after the step of forming the second polysilicon structure of the first conductive type, forming a dielectric structure in the first trench, wherein the dielectric structure at least extends upward to the body region; (h) forming a body region of the first conductive type between the gate trenches, wherein the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance; (i) forming a source region of a second conductive type in an upper portion of the body region; (j) forming an interlayer dielectric layer on the first polysilicon structure to define a source contact window aligned to the first trench; (k) forming at least a heavily doped region of the first conductive type in the body region; and (l) forming a source metal layer in the source contact window for electrically connecting to the heavily doped region and the source region.