Patent ID: 8908410
Filing Date: 2014-12-09
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element; a third line extending through a plurality of the memory mats; a second variable resistance element connected between the third line and the second line of each of the plurality of memory mats; a dummy memory cell; and a fourth line connected to the second line via the dummy memory cell, wherein the fourth line is set to a first potential when a memory mat corresponding to the fourth line is selected, and is set to a second potential when the memory mat corresponding to the fourth line is unselected, the second potential being different from the first potential.