Patent ID: 7546481
Filing Date: 2009-06-09
Classification: G06F

Abstract:
1. A clock control circuit built in a semiconductor integrated circuit including an input/output circuit for performing an input/output operation based on an external master clock signal, and a processor for performing control operation in accordance with a program, to generate a reference bus clock signal which is the basis for the operation of said processor, based on the master clock signal, said clock control circuit comprising: a divider unit which divides the master clock signal in response to a falling timing of the master clock signal to generate a divided clock signal; a multiplier unit which multiplies a frequency of the master clock signal by n (where n is an integer equal to or larger than three) to generate a multiplied signal synchronized to a rising timing of the master clock signal; a counter which is reset each time the master clock signal rises, and counts up one by one each time the multiplied signal rises; a comparator which outputs a comparison result signal at a first level when a count value of said counter is less than n−1, and sets the comparison result signal to a second level different from the first level when the count value is n−1; a logical OR gate which outputs a logical OR of the comparison result signal and the multiplied signal to output a multiplied clock signal; and a selector unit which selects one of the divided clock signal and the multiplied clock signal and outputs the signal selected by said selector unit as the reference bus clock signal.