Patent ID: 6202123
Filing Date: 2001-03-13
Classification: G06F,G11C

Abstract:
A system comprising:a computer; anda microcomputer formed on a single chip, and coupled to said computer;wherein said microcomputer hasa read only memory storing a program,a serial communication unit which communicates with said computer,a clock signal circuit providing a clock signal having a frequency,a measuring unit which obtains a number of cycles of said clock signal in a period represented by reference data which is transferred to said serial communication unit from said computer,a central processing unit, coupled to receive said clock signal from said clock signal circuit and operating in accordance with said clock signal, anda flash memory which stores data and in which data is electrically erased by an execution of an erase operation, said erase operation being executed in a period which is determined by a number of cycles of said clock signal which said central processing unit allocates as an erase time,wherein said central processing unit calculates a time of one cycle of said clock signal from said period represented by said reference data and the number of cycles obtained by said measuring unit, and calculates a number of cycles of said clock signal to be allocated as said erase time of data stored in said flash memory.