Patent ID: 6330664
Filing Date: 2001-12-11
Classification: G06F

Abstract:
Arrangement for instruction processing comprising a multi-stage pipeline arrangement to which instructions are delivered from at least one instruction source and a storing arrangement for storing jump address information for jump instructions, wherein the storing arrangement comprises at least one FIFO-register and conditional jump target address information is stored in said at least one FIFO-register while at least the jump instructions are stored in said pipeline arrangement whereby the conditional jump target address information is delivered from said at least one FIFO-register, and said pipeline arrangement comprises at least a first pipeline path and a second pipeline path, one of which being current executing instructions and the other a non-current pipeline, so arranged that when a conditional jump is taken, the pipeline paths are switched so that the non-current pipeline path becomes current and vice versa in such a way that continuous prefetching of the instructions is enabled irrespective of a number of conditional jumps and irrespective of whether the conditional jumps are taken or not.