Patent ID: 6313766
Filing Date: 2001-11-06
Classification: H04N

Abstract:
A computer system, comprising:a logic device to receive a bit stream of variable length encoded information, the logic device to output a fixed length value corresponding to one of a plurality of variable length codes received as part of the bit stream of variable length encoded information to a destination in a system memory, where the fixed length value is an index to a table of coefficients, where the logic device includes a register to receive the bit stream of variable length encoded information and a decode circuit coupled to receive a plurality of bits of variable length encoded information from the register and outputs the fixed length value, and where the plurality of bits includes the one of the plurality of variable length codes; anda processor to receive the fixed length value by reading the fixed length value from the destination location in the system memory, and to perform a write of a coefficient to the system memory device using the table of coefficients, the coefficient corresponding to the fixed length value received from the logic device, where the processor uses the index to read from the table of coefficients to determine the coefficient corresponding to the fixed length value.