Patent ID: 8987748
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a silicon-containing semiconductor substrate; a first well of a first conductivity type disposed in said substrate; a first gate structure disposed over said first well, said first gate structure including a first gate dielectric layer disposed on said substrate and a first gate electrode disposed over said gate dielectric layer; first lightly doped drain (LDD) layers of a second conductivity type disposed in said first well adjacent to said first gate structure, said second conductivity type being an opposite polarity from said first conductivity type; first epitaxial source drain regions of said second conductivity type disposed in said substrate adjacent to said first gate structure, said first epitaxial source drain regions extending under source drain epitaxial spacers abutting said first gate structure and culminating in first stressor tips, such that said first stressor tips are furthest lateral extension of said first epitaxial source drain regions under said first gate structure; and a first anti-punch-through layer of said first conductivity type disposed in said first well under said first gate structure, so that said first anti-punch-through layer extends above and below said first stressor tips, said first anti-punch-through layer having an average doping density of 3·10