Patent ID: 7237210
Filing Date: 2007-06-26
Classification: G01R

Abstract:
1. A method for managing functional verification of a parameterizable design, the method comprising: creating a testbench: configuring the testbench using hardware design language configurations, the testbench having one or more parameterizable components, wherein the hardware design language configurations provide an indication of which of the one or more parameterizable components are used to configure the testbench, wherein configuring the testbench comprises instantiating a component of a generic design in the testbench, the testbench having testbench signals and the component having a plurality of ports, the testbench signals being wired to all of the ports; determining whether the parameterizable design is a chip-specific design that requires different ports or a different number of ports than the generic design; in response to determining that the parameterizable design is a chip-specific design, instantiating in the testbench one or more special components, the special components being wired to the same ports as the generic design; observing values in the testbench; automatically configuring a verification environment to match the parameterizable design based on the observed values in the testbench to facilitate verification of the parameterizable design; and performing verification of the parameterizable design.