Patent ID: 6137132
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A structure of buried bit line flash EEPROM cell with a trench floating gate comprising:a composite layer formed on a semiconductor substrate, said composite layer having a trench, which is with a bottom coming down into said semiconductor substrate, thereby forming a remnant portion of said composite layer, said remnant portion of composite layer comprising:a pad oxide layer formed on said semiconductor substrate, a phosphorus doped dielectric layer formed on said pad oxide layer, anda first isolation layer formed on said phosphorus doped dielectric layer;an oxynitride layer formed on a surface of said semiconductor substrate which is in sidewalls and bottom of said trench;a first conductive layer formed in said semiconductor substrate of said remnant portion of said composite layer to serve as buried bit line;a second conductive layer formed in said trench so as to form said trench floating gate;a second isolation formed on said second conductive layer and said first isolation; anda third conductive layer formed on said second isolation.