Patent ID: 6594728
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A cache memory accessed by an address, said cache memory comprising:a first array of RAM cells containing a first plurality of sets of cells; a second array of RAM cells containing a second plurality of sets of cells and operating at about the same time as said first array, wherein said RAM cells of said first array are interleaved such that a first cell within a first set of said first plurality of sets corresponds to a first way and each subsequent cell within said first set corresponds to ways alternating between a second way and said first way, and said RAM cells of said second array are interleaved such that a second cell within a second set of said second plurality of sets corresponds to said second way and each subsequent cell within said second set corresponds to ways alternating between said first and second ways, and wherein said first and second sets are each associated with a particular bit position; a decoder coupled to said first array and said second array for enabling said first and second arrays at about the same time; a first multiplexer coupled to said first set for outputting selected contents of said first array; and a second multiplexer coupled to said second set for outputting selected contents of said second array at about the same time as said first multiplexer.