Patent ID: 7848172
Filing Date: 2010-12-07
Classification: G11C

Abstract:
1. A memory circuit, comprising: a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells; a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays; wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.