Patent ID: 6185324
Filing Date: 2001-02-06
Classification: G01N,H01L

Abstract:
A semiconductor failure analysis system comprising:means for detecting electrical fail bits in a semiconductor chip or in a wafer;means for memorizing kinds of predetermined shaped patterns and a plurality of data compression methods corresponding to the kinds of predetermined shaped patterns and identified information corresponding to the kinds of predetermined shaped patterns;means for dividing a first area of the semiconductor chip or the wafer into a plurality of second areas;means for specifying a third area covering only a portion of an entire surface area of one of the second areas in which said electrical fail bits are distributed;means for dividing the specified third area into a number of shapes in accordance with the kinds of predetermined shaped patterns;means for discriminating a kind of a predetermined shaped pattern from a thus divided shape of said specified third area;means for performing data compression of the electrical fail bits forming said thus divided shape by using one of said data compression methods corresponding to the kind of said predetermined shaped pattern thus discriminated,means for abstracting a representative shaped pattern of the third area from the discriminated shaped patterns;means for displaying a wafer picture and the identified information of the abstracted shaped pattern in the wafer picture; andmeans for displaying the electrical fail bits distribution of the third area.