Patent ID: 8493089
Filing Date: 2013-07-23
Classification: G11C,H03K

Abstract:
1. A configurable die stack arrangement comprising: a first configurable integrated circuit die located on a first substrate, the first configurable integrated circuit die comprising: a first configuration memory management circuit comprising an interface to the first array; a second configurable integrated circuit die located on a second substrate, the second substrate different than the first substrate, the second configurable integrated circuit die comprising: a second configuration memory management circuit comprising an interface to the second array; and a signal coupled to both the first configuration memory management circuit and the second configuration memory management circuit, wherein the first configuration memory management circuit further comprises a control circuit to control the signal, and wherein an output of the first configuration memory is coupled to an input of the second logic element, and the configurable die stack arrangement is configured such that data transmitted from the output of the first configuration memory to the input of the second logic element is time domain multiplexed and in high speed bursts.