Patent ID: 6618698
Filing Date: 2003-09-09
Classification: G06F

Abstract:
A method for use in a software-driven multiprocessor emulation system, wherein there are a plurality of emulation processors, each emulation processor containing an execution unit for processing multiple types of logic gate functions, with means provided for each emulation processor to switch from one logic gate function to a next logic gate function in a switched-emulation sequence of different gate functions, and wherein the switched-emulation sequence of each of the plurality of processors enables emulating a subset of gates in a hardware arrangement in which logic gates are of any type that the emulation processors functionally represent for a sequence of clock cycles, and wherein a plurality of multiplexors having outputs respectively connected to the emulation processors and having inputs respectively connected to each of the other emulation processors, and bus means connected to the multiplexors to enable an output from any emulation processor to be transferred to an input of any other of the emulation processors, an embedded control store in each of the emulation processors to store software logic-representing signals for controlling operations of the emulation processor, an embedded data store in each of the emulation processors to receive input for, and data generated by the same emulation processor under control of software signals stored in the embedded control store in the same emulation processor, and bus controls to transmit data on the bus from any emulation processor through a connected multiplexor under control of software signals stored in the embedded control store to control computational emulation of the hardware arrangement by operation of the plurality of emulation processors under software control, comprising the steps of:on an integrated circuit, arranging said plurality of emulation processors to form a plurality of clusters of processors such that the setup and storing of results calculated by each of said plurality of emulation processors within each of said plurality of clusters is done in parallel, but the output of one of said emulation processors within each of said plurality of clusters is made available as the input of said emulation processors within each of said plurality of clusters via a set of â€˜cascadeâ€™ connections to intermediate values used in the emulation engine by tapping said intermediate values from one emulation processor within one of said plurality of clusters, and feeding said intermediate values to the next emulation processor within said one of said plurality of clusters via said cascade connections to exploit a time differential between data flow where time is measured as the time taken to perform a single emulation step.