Patent ID: 8964918
Filing Date: 2015-02-24
Classification: G01R,G06F,H04B,H04J,H04L

Abstract:
1. An integrated circuit comprising: A. a serial data input lead; B. a serial data output lead; C. a clock signal input lead; D. a mode select signal input lead; E. first data communication circuitry having a data input coupled to the serial data input lead, a data output coupled to the serial data output lead, a clock input coupled to the clock signal input lead, and a mode input coupled to the mode select signal input lead, the first data communication circuitry operating in at least three different states and changing states in response to clock signals and mode select signals on the respective clock signal input lead and the mode select signal input lead to communicate serial data in a sequence of states, the communication states including a header state, a data communication state, and a trailer state; and F. second data communication circuitry having a data input coupled to the serial data input lead, a data output coupled to the serial data output lead, a clock input coupled to the mode select signal input lead, and a mode input coupled to the clock signal input lead, the second data communication circuitry operating in at least three different states and changing states in response to clock signals and mode select signals on the respective mode select signal input lead and the clock signal input lead to communicate serial data in a sequence of states, the communication states including a header state, a data communication state, and a trailer state.