Patent ID: 6175516
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A semiconductor device comprising:a first memory array having a plurality of first memory cells;a second memory array having a plurality of second memory cells;a first data line formed in a first layer, extending in a first direction and provided for said first memory array;a second data line formed in said first layer extending in said first direction and provided for said second memory array; anda third data line formed in a second layer which is different from said first layer and extending in a second direction perpendicular to said first direction;wherein said first data line and said third data line are connected by a conductive material filled in a through hole;wherein said second data line and said third data line are connected by a conductive material filled in a through hole;wherein when data read out from a selected memory cell of said plurality of said first memory cells is given to said first data line, said second data line and said second memory array are electrically isolated; andwherein when data read out from a selected memory cell of said plurality of said second memory cells is given to said second data line, said first data line and said first memory array are electrically isolated.