Patent ID: 9083470
Filing Date: 2015-07-14
Classification: H04B

Abstract:
1. An optical receiver for receiving an optical signal that has been subjected to quadrature phase modulation, comprising: at least two independent CDR circuits for clock extraction, identification and data regeneration of at least two electric signals regenerated from the received optical signal that has been subjected to the quadrature phase modulation; a synchronization circuit to synchronize at least two first data strings respectively output from the CDR circuits; a bit shift circuit to bit shift at least one of at least two second data strings output from the synchronization circuit; a pattern changing circuit to lane swap and polarity invert at least one of the at least two second data strings output from the bit shift circuit; a multiplexing circuit to multiplex at least two third data strings output from the pattern changing circuit; a signal check circuit to verify multiplexed data output from the multiplexing circuit; and a bit shift pattern change control circuit connected to control the bit shift circuit and the pattern changing circuit based on a result of data verification from the signal check circuit, detect a correct combination of correct regenerated data, and establish signal conduction, wherein the bit shift pattern change circuit repeatedly changes control contents of the bit shift circuit and the pattern changing circuit until the result of the data verification output from the signal check circuit becomes a predetermined result, and detects the correct combination of the correct regenerated data to establish signal conduction, wherein, when multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a first control content and multiplexed data output from the multiplexing circuit in a case where the bit shift circuit and the pattern changing circuit are controlled with a second control content are the same, the bit shift pattern change control circuit controls the bit shift circuit and the pattern changing circuit with one of the first control content or the second control content, and wherein the bit shift pattern change control circuit controls so as to verify one of an odd number of bits or an even number of bits among the multiplexed data.