Patent ID: 7235480
Filing Date: 2007-06-26
Classification: H01L

Abstract:
1. A semiconductor processing method of forming integrated circuitry comprising: forming a plurality of conductive lines over a substrate, some of the conductive lines being formed over a memory array area of the substrate, other of the conductive lines being formed over a peripheral area of the substrate proximate the memory array area, the other conductive lines having a first insulative material disposed over respective top portions thereof and a different second insulative material over the first insulative material; forming a masking layer over the plurality of conductive lines; forming two openings through the masking layer over the peripheral area without forming any openings through the masking layer over the memory array area, a first opening being received over a first conductive line, a second opening being received over a second conductive line; providing impurity through the first opening and into the substrate proximate the first conductive line and forming diffusion regions within dimensions of the first opening; and forming a contact opening underneath the second opening over the second conductive line completely through the second insulative material, but not completely through the first insulative material.