Patent ID: 7679137
Filing Date: 2010-03-16
Classification: H01L

Abstract:
1. A recessed gate MOS transistor device, comprising: a substrate having thereon a gate trench, wherein the gate trench has a sidewall and a bottom surface; a source diffusion region disposed on the sidewall of the gate trench; a drain diffusion region disposed on the sidewall of the gate trench opposite to the source diffusion region; a gate channel region being situated at the bottom surface of the gate trench and between the source diffusion region and the drain diffusion region; a gate oxide layer formed on the sidewall and bottom surface of the gate trench, wherein the gate oxide layer has a first thickness at the sidewall of the gate trench and has a second thickness at the bottom surface of the gate trench, and wherein the first thickness is not equal to the second thickness, wherein both of the source and drain diffusion regions extend along the sidewall of the gate trench and reach the gate oxide layer of the second thickness; and a gate conductor inlaid in the gate trench.