Patent ID: 6975398
Filing Date: 2005-12-13
Classification: G03F,H01L

Abstract:
1. A method of determining overlay error in an integrated circuit made by a lithographic process comprising: creating a first layer of the integrated circuit having at least one circuit area including a first active circuit feature and a kerf area adjacent to the circuit area substantially free of active circuit features, the first layer kerf area including a first measurement feature corresponding substantially to the first layer active circuit feature and separated from the first layer active circuit feature by a distance, the first measurement feature replicating a feature of the corresponding first layer active circuit feature selected from the group consisting of size, pitch and shape of the first layer active circuit feature and proximity of the first layer active circuit feature to any other structure; creating a second layer of the integrated circuit having at least one circuit area including a second active circuit feature and a kerf area adjacent to the circuit area substantially free of active circuit features, the circuit and kerf areas of the first and second layers being substantially superimposed, the second layer kerf area including a second measurement feature corresponding substantially to the second layer active circuit feature and separated therefrom by a distance, the second measurement feature replicating a feature of the corresponding second layer active circuit feature selected from the group consisting of size, pitch and shape of the second layer active circuit feature and proximity of the second layer active circuit feature to any other structure, the distance of separation between the separated second layer active circuit feature and the second layer kerf measurement feature in the direction that the overlay error is to be determined being the same as the distance of separation between the separated first layer active circuit feature and the first layer kerf measurement feature in such direction, the second layer kerf measurement feature being displaced from the first layer kerf measurement feature compared to the first and second active circuit features in a direction perpendicular to the direction that the overlay error is to be determined; determining a common point of reference of each of the first and second layer kerf measurement features; and measuring distance of separation in the direction of overlay error between the common points of reference of each of the first and second layer kerf measurement features to determine overlay error of the first and second active circuit features.