Patent ID: 6707745
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array of dynamic memory cells; a refresh control module having a refresh timer, which generates a refresh timing signal used to determine an execution timing of a refreshing operation of the memory cell array, the refresh control module causing the memory cell array to execute the refreshing operation in response to at least the refresh timing signal; a temperature detection module having a temperature sensing element, which includes a specific pn junction area set in a cutoff state out of pn junction areas formed on an identical semiconductor substrate with the memory cell array and outputs a leak current running through the specific pn junction area, the temperature detection module detecting a temperature change of the semiconductor memory device in response to the leak current output from the temperature sensing element; and a temperature characteristic regulation module that regulates a generation period of the refresh timing signal, based on a result of the detection by the temperature detection module.