Patent ID: 6803282
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of fabricating MOSFET transistors in a semiconductor device, comprising the steps of:providing a semiconductor device substrate; implanting a first transistor region associated with a first transistor device in the semiconductor device substrate to adjust a threshold voltage associated with the first transistor device and concurrently implanting a portion of a second transistor region in the semiconductor device substrate associated with a second transistor device in the semiconductor device to form source/drain regions associated with the second transistor device with a channel region between said source/drain regions; then forming a first gate oxide structure overlying a channel region in the first transistor region, the first gate oxide structure having a first thickness and forming a second gate oxide structure overlying the channel region in the second transistor region, the second gate oxide structure having a second thickness, the second thickness being greater than the first thickness.