Patent ID: 6512804
Filing Date: 2003-01-28
Classification: H04J,H04L,Y10S

Abstract:
Apparatus for synchronizing parallel digital data transmitted across a plurality of serial data channels, comprising:a plurality of regenerators for receiving serial data from the plurality of serial data channels, respectively, each regenerator generating parallel data and a data clock based on the serial data from the respective serial data channel; a clock tree for generating a synchronous clock for synchronizing the parallel data; and a plurality of FIFO buffers each associated with a regenerator, each FIFO buffer for storing the respective parallel data, wherein the respective parallel data is stored in each respective FIFO buffer based on the respective data clock and the parallel data is read from the FIFO buffer based on the synchronous clock and wherein the FIFO buffers are optimized for jitter; each FIFO buffer of the plurality of FIFO buffers including: a data store having a plurality of parallel data locations for storing the parallel data in response to a location select signal and for writing the parallel data in response to a write select signal, a synchronous repetitive counter for generating a synchronous count for incrementally selecting each data location based on the synchronous clock; a demultiplexer coupled between the synchronous counter and the plurality of storage locations for enabling a selected location to store the parallel data using the select signal which is generated by the demultiplexer based on the synchronous count; a data repetitive counter for generating a data count for incrementally selecting each data location based on the data clock; and a multiplexer coupled between the data counter and the plurality of storage locations for reading the parallel data of a data location selected based on the data count; wherein the synchronous counter is configured to count about 180 degrees out of phase with the count of the data counter in the absence of jitter between the synchronous clock and the data clock so that the synchronizing apparatus is optimized for jitter.