Patent ID: 7064993
Filing Date: 2006-06-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell storing data; a pair of bit lines connected to said memory cell; a sense amplifier provided corresponding to said pair of bit lines and activated in response to a sense amplifier activation signal; a pair of I/O lines transmitting said data input/output to/from said memory cell via said pair of bit lines; and a connection gate circuit provided between said pair of bit lines and said pair of I/O lines and electrically connecting said pair of bit lines to said pair of I/O lines when said sense amplifier activation signal and a column selection signal selecting said pair of bit lines are both activated; wherein said connection gate circuit includes first and second gates connected in series between said pair of bit lines and said pair of I/O lines, said first gate conducts in response to said sense amplifier activation signal, and said second gate conducts in response to said column selection signal.