Patent ID: 8347157
Filing Date: 2013-01-01
Classification: G01R

Abstract:
1. An integrated circuit containing multiplexer control circuitry comprising: A. a first flip-flop having a data input connected with a remove signal input lead, a non-inverting output connected with a remove select signal output lead, a non-inverting clock input connected with a clock input lead carrying an Update IR/DR signal, and a reset input; B. first gate circuitry having a reset input connected with a reset signal lead, a replace state input, and an output connected with the reset input of the first flip-flop; C. a second flip-flop having a data input, a clock input connected with a test mode select in lead, an output connected with the replace state input of the first gate circuitry, and a set input; D. a third flip-flop having a data input connected to a fixed logic level, a clock input connected with a test mode select in lead, an output connected with the data input of the second flip-flop, and a set input; and E. second gate circuitry having an input connected to the reset signal lead, a replace state input connected with a replace state lead, and an output connected with the set inputs of the second and third flip-flops.