Patent ID: 6087235
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method for fabricating a field effect transistor having a drain extension implant, a source extension implant, a gate dielectric, a gate structure disposed over said gate dielectric, and a first spacer disposed on sidewalls of said gate dielectric and of said gate structure, the method including the steps of:A. selectively growing an elevated drain contact structure on said drain extension implant, said elevated drain contact structure having a drain facetted surface facing toward said first spacer on said sidewall of said gate structure;B. selectively growing an elevated source contact structure on said source extension implant, said elevated source contact structure having a source facetted surface facing toward said first spacer on said sidewall of said gate structure;C. forming a second spacer to cover said drain facetted surface and said source facetted surface;D. doping said elevated drain contact structure and said elevated source contact structure that is exposed with a dopant, after said step C;E. activating said dopant within said elevated drain contact structure and said elevated source contact structure;F. forming silicide on said elevated drain contact structure and said elevated source contact structure that is exposed, after said step E;forming a gate capping layer on said gate structure before said step A to prevent selective growth of said gate structure into a mushroom-shaped structure during said step A;etching said gate capping layer on said gate structure, after said step C and before said step D;doping said gate structure with said dopant during said step D;activating said dopant within said gate structure during said step E; andforming silicide on said gate structure during said step F.