Patent ID: 9076682
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first gate structure provided in a cell transistor region of a substrate, the first gate structure including a floating gate electrode, a first dielectric layer pattern covering a whole upper surface of the floating gate electrode, a control gate electrode on the first dielectric layer pattern, the control gate electrode including a first metal silicide pattern; a second gate structure provided in a selecting transistor region of the substrate, the second gate structure including a first conductive layer pattern, a second dielectric layer pattern covering a portion of an upper surface of the first conductive layer pattern, a first gate electrode, wherein the first gate electrode includes a polysilicon layer pattern formed on the second dielectric layer pattern, and electrically connected to the first conductive layer pattern, a second metal silicide pattern formed on the polysilicon layer pattern; and a third gate structure provided in a peripheral circuit region of the substrate, the third gate structure including a second conductive layer pattern, a third dielectric layer pattern including a plurality of opening portions on the second conductive layer pattern, a second gate electrode and a third metal silicide pattern, wherein the second gate electrode is disposed in respective opening portions and contacts the second conductive layer pattern, wherein an upper surface portion of the third metal silicide pattern includes concavo-convex portions.