Patent ID: 9069605
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A multi-core processor comprising: a first sequencer of a first sequencer type to execute one or more threads and including a first portion of a distributed user-level scheduler; a second sequencer of a second sequencer type to execute one or more shreds and including a second portion of the distributed user-level scheduler, wherein the first sequencer is visible to an operating system (OS) and the second sequencer is invisible to the OS, the first and second sequencers being computationally asymmetric; and a work queue coupled to the first sequencer and the second sequencer, the work queue to store a descriptor for each of one or more pending shreds, and wherein the first sequencer and the second sequencer are to determine whether the corresponding sequencer is capable of execution of a shred of the one or more pending shreds, and if so, to remove the corresponding descriptor from the work queue for execution of the shred by the corresponding sequencer.