Patent ID: 6764946
Filing Date: 2004-07-20
Classification: G03F,H01L,Y10S

Abstract:
A method of forming an integrated circuit line on a wafer using a lithographic technique, comprising;providing the wafer, the wafer including a substrate and, over the substrate, each of a photo resist layer and an underlying layer to be processed under the photo resist layer; exposing and developing the photo resist layer to form a photo resist line, the photo resist line having a line width smaller than a desired line width of the integrated circuit line; coating the photo resist line with a reactive coating; and reacting the photo resist line with the coating to form a mask line having a line width corresponding to the desired line width of the integrated circuit line and with a smaller line edge roughness (LER) than of the photo resist line; and wherein a difference between a critical dimension of the photo resist line and a critical dimension of the mask line is about 30 nanometers to about 60 nanometers.