Patent ID: 6359820
Filing Date: 2002-03-19
Classification: G11C

Abstract:
A method for checking the operation of memory cells in an integrated memory, which comprises:providing an integrated memory having addressable memory cells in a matrix-like memory cell array along column lines and row lines; the memory cells combined to form groups of column lines and row lines each addressed with column addresses and row addresses; each of the column addresses and row addresses including an address part addressing the respective groups of column lines and row lines; successively testing the memory cells in an intersection of one of the groups of column lines and one of the groups of row lines for faults, and then testing memory cells of another group of column lines or row lines; comparing faulty respective address parts of the memory cells recognized as being faulty; further processing the address of a faulty memory cell if a address part of the faulty memory cell matches another address part of another faulty memory cell, and not further processing the addresses of other faulty memory cells.