Patent ID: 6732223
Filing Date: 2004-05-04
Classification: G06F,H04L

Abstract:
A dynamic random access memory device (DRAM), comprising:at least one memory bank; control logic associated with the at least one memory bank to control at least one of data and commands within the DRAM, wherein the control logic comprises at least one read counter associated with a FIFO, wherein the at least one read counter comprises at least one register configured to indicate a previous read counter setting for the at least one read counter and wherein the at least one register comprises: a first register and a second register, together indicating a current read counter setting; and a third register which, in combination with the second register, indicates the previous read counter setting of the at least one read counter; and a FIFO associated with the control logic, the control logic further configured for simultaneous reading and writing the at least one of data and commands from the FIFO.