Patent ID: 6026227
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A field programmable gate array (FPGA), comprising:a plurality of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including first and second look-up tables, each look-up table having a set of address inputs and an output, the address inputs of both look-up tables receiving signals from a common set of cell inputs, each logic cell also having an AND logic gate provided therein with a pair of gate inputs selectively connected to two cell inputs and with a gate output connected to one address input of both look-up tables, the outputs of said first and second look-up tables selectively connected to respective first and second cell outputs, each logic cell also including an output multiplexer selectively connected to a third cell output and having first and second multiplexer inputs connected to the respective first and second look-up table outputs and further having a control input selectively connected to an additional cell input.