Patent ID: 7203264
Filing Date: 2007-04-10
Classification: G11C

Abstract:
1. A high-stability shift circuit using amorphous silicon thin film transistors is applied to shift register circuits that are composed of amorphous silicon thin film transistors, and stages are connected in serial and send the output signals to the gate lines in the panel; initially, a serial-start signal is fed into a first stage, and input signals for the rest stages are from the output signal of the next-former stage individually; a first clock-pulse terminal and a second clock-pulse terminal for odd stages of the shift register circuit are respectively supplied by the first clock-pulse signal and the second clock-pulse signal that are out-of-phase to each other; an input terminal of the odd stage also includes a reset terminal that receives the output signal of the next-latter stage; and each odd stage of the stages comprising of: a first transistor whose gate connects to the input terminal and the drain connects to a high-level supply voltage; a second transistor whose gate connects to the reset terminal, the source connects to the first clock-pulse terminal, and the drain and the source of the first transistor form a first node; a third transistor whose drain connects to the first node and the source connects to the second clock-pulse terminal; a fourth transistor whose gate connects to the first clock-pulse terminal, the drain connects to the high-level supply voltage, and the source and the gate of the third transistor form a second node; a fifth transistor whose gate connects to the first node, the drain connects to the second node, and the source connects to a low-level supply voltage; a sixth transistor whose gate connects to the second clock-pulse terminal, the drain connects to the first clock-pulse terminal, and the source connects to the second node; a seventh transistor whose gate connects to the first node, the drain connects to the first clock-pulse terminal, the source connects to an output terminal; a capacitor is connected between the first node and the output terminal; an eighth transistor whose gate connects to the second node, the drain connects to the output terminal, and the source connects to the second clock-pulse terminal; and a ninth transistor whose gate connects to the second clock-pulse terminal, the drain connects to the output terminal, and the source connects to the first clock-pulse terminal.