Patent ID: 6366115
Filing Date: 2002-04-02
Classification: G01R,H03K

Abstract:
A buffer circuit for correcting signal path and temperature-related timing errors present in a propagating signal, comprising:a signal path for conveying a test signal to a predetermined downstream node, said test signal having associated desired timing relationships between its rising and falling edges, a delay circuit in said signal path, comprising: an input connected to receive said test signal, an output, a rising edge delay circuit connected between said input and output, a falling edge delay circuit connected between said input and output, said delay circuit arranged to receive first and second error correction signals and to propagate said test signal from said input to said output with said test signal's rising and falling edges delayed by said rising and falling edge delay circuits, respectively, with the duration of said delays varying in accordance with said correction signals, said test signal propagated via said signal path from said delay circuit output to said predetermined downstream node, said test signal at said predetermined downstream node having timing relationships between its rising and falling edges, a signal path error correction circuit arranged to produce said first error correction signal such that the error between said desired timing relationships and said timing relationships at said predetermined downstream node induced by the signal path followed by said test signal as it propagates to said predetermined downstream node is reduced, and a temperature-related error correction circuit arranged to produce said second error correction signal such that the error between said desired timing relationships and the timing relationships at said downstream node which arises due to thermal effects that occur when propagating a test signal having a duty cycle other than 50% through said signal path is reduced.