Patent ID: 7406565
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. A multi-processor system that conforms to a cache coherency protocol, the system comprising: a processor that transmits a source request for a data fill associated with a cache line in response to a cache miss, the processor having a processor pipeline that executes program instructions with data from a given speculative fill of at least two a speculative fills that are received from two or more other processors of the multi-processor system in response to a source request, the speculative fills being copies of the requested data fill that have undetermined coherency states; and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the given speculative fill, the backup system initiating a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline continuing execution of program instructions if the given speculative fill is determined to be coherent.