Patent ID: 9159826
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate embedded with an isolation feature; a protrusion structure disposed over the substrate and protruding out of a surface of substrate, wherein the protrusion structure includes a bottom portion, a top portion and a middle portion interposed between the bottom and top portions; a drain region formed in the substrate and extending in the bottom portion of the protrusion structure; a gate stack disposed over the substrate, wherein the gate stack has a planar portion parallel to the surface of substrate, and wherein the gate stack wraps around the middle portion of the protrusion structure; a source region formed in the top portion of the protrusion structure, the source region has a top surface; wherein the drain region has a doping type different from that of the source region; an isolation dielectric layer disposed over the substrate, wherein the isolation dielectric layer has a top surface being substantially coplanar with a top surface of the gate stack and the top surface of the gate stack is below the top surface of the source region, and wherein the isolation dielectric layer is continuous around the gate stack; a gate contact extending through the isolation dielectric layer and landing on the gate stack, wherein the planar portion of the gate stack is disposed on the first dielectric material layer and laterally spanning away from the protrusion structure to a farthest end, the planar portion of the gate stack includes a top surface substantially in parallel with the surface of the substrate, the planar portion of the gate stack includes a sidewall at the farthest end, and the gate contact directly contacts the top surface of the gate stack and the sidewall of the gate stack; and a drain contact extending through the isolation dielectric layer and landing on a top surface of the drain region and a sidewall of the drain region.