Patent ID: 7186664
Filing Date: 2007-03-06
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a conductive structure in an integrated circuit, the method comprising: forming a silicon-germanium layer; forming a silicon nitride mask layer over the silicon-germanium layer; removing a portion of the silicon nitride mask layer to expose a first region of the silicon-germanium layer; oxidizing the exposed first region of the silicon-germanium layer, wherein a second region of the silicon-germanium layer covered by the silicon nitride layer remains un-oxidized; after oxidizing, removing remaining portions of the silicon nitride mask layer; depositing a metallic layer over the first and second regions of the silicon-germanium layer; and annealing the integrated circuit to substitute metal from the metallic layer for the un-oxidized silicon-germanium of the second region to form the conductive structure.