Patent ID: 6812104
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method of manufacturing a MIS type semiconductor device, the method comprising:laminating a first insulating film and a dummy gate selectively on a first semiconductor layer; selectively growing a semiconductor material in a solid phase, with the dummy gate used as a mask, thereby forming a second semiconductor layer with an obtuse-angled side wall, the second semiconductor layer sandwiching the dummy gate; injecting an impurity into a surface of the second semiconductor layer with the dummy gate used as a mask, thereby forming a diffusion layer whose lower surface is higher than a surface of the first semiconductor layer; removing the first insulating film and the dummy gate to expose a recess portion including a bottom surface and a taper portion with an inclination substantially equal to an inclination of the side wall of the second semiconductor layer; forming a gate insulating film on the bottom surface and the taper portion of the recess portion; forming a gate electrode on the gate insulating film; forming an interlayer insulating film on the second semiconductor layer; and selectively removing the interlayer insulating film to form a contact hole on a surface of the diffusion layer.