Patent ID: 6438096
Filing Date: 2002-08-20
Classification: G11B

Abstract:
An optical disk comprising a land track and a groove track, wherein each of the land track and the groove track includes a plurality of sectors, each of the plurality of sectors includes a sector address region and a data region, and the sector address region includes a plurality of address blocks,further wherein the sector address region includes a first address block group including a plurality of address blocks immediately adjacent to each other in a circumferential direction and a second address block group including a plurality of address blocks immediately adjacent to each other in the circumferential direction, each of the plurality of address blocks included in the first address block group includes data of a clock synchronization signal and an address number, each of the plurality of address blocks included in the second address block group includes data of a dock synchronization signal and an address number, the first address block group and the second address block group are disposed so as to be shifted oppositely in a radial direction with respect to a track central axis by substantially half of a track pitch, a length of data of the dock synchronization signal included in a leading address block among the plurality of address blocks included in the first address block group is greater than a length of data of the clock synchronization signal included in an address block other than the leading address block, among the plurality of address blocks included in the first address block group, and a length of data of the clock synchronization signal included in a leading address block among the plurality of address blocks included in the second address block group is greater than a length of data of the clock synchronization signal included in an address block other than the leading address block, among the plurality of address blocks included in the second address block group, wherein the length of data of the clock synchronization signals included in the leading address blocks of the first and second address block groups are equal and the length of data of the clock synchronization included in the address blocks other than the leading address block of the first and second address block groups are equal.