Patent ID: 6576989
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A panel assembly of packaged integrated circuit devices comprising:a conductive substrate panel having at least one array of device areas, and defining a plurality of locking passageways positioned about an inactive buffer area which surrounds the periphery of the array of device areas, said locking passageways extending inwardly from a topside of the panel toward a bottom side thereof; and a molded cap that is molded over the panel topside to encapsulate the device areas of the array and the inactive buffer area, said molded cap further having integrally formed, conforming locking stem portions that extend into each of the locking passageways such that each of the locking stems have substantially the same shape and size as the locking passageway into which each of the locking stems extend, the locking stems configured to lock the molded cap to the substrate panel such that during singulation of the device areas, said molded cap will not separate from the substrate panel at the inactive buffer area.