Patent ID: 9075742
Filing Date: 2015-07-07
Classification: G06F,G11C

Abstract:
1. A memory device comprising: a writing device that writes data bits, check bits for error corrections, and k (k being an integer equal to or greater than 1) overhead bit(s) into a memory, each bit of the k overhead bit(s) corresponding to each group of k bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the k overhead bit(s) indicating whether the corresponding bit group has been inverted; a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory; a correcting unit that corrects an error in the data bits and the overhead bit(s) read from the memory, based on the check bits read from the memory; and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed, and does not invert the data bits contained in the bit group corresponding to the overhead bit and outputs the data bits as the data read from the memory when the error-corrected overhead bit indicates that inversion has not been performed.