Patent ID: 7629652
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate of a rectangular shape having a main surface; a plurality of input electrode pads formed over said main surface along a first relatively long side of said semiconductor substrate; a plurality of output electrode pads formed over said main surface along a second relatively long side of said semiconductor substrate, opposing to said first relatively long side; an internal circuit formed over said main surface between said plurality of input electrode pads and said plurality of output electrode pads, said internal circuit providing predetermined output signals to said plurality of output electrode pads; a plurality of protective elements for protecting said internal circuit from an electro-static breakdown formed over said main surface, said plurality of protective elements being electrically connected to said plurality of output electrode pads, respectively; a plurality of signal wirings for providing said predetermined output signals to said plurality of output electrode pads, first ends of said plurality of signal wirings being connected to said internal circuit and the opposing, second ends of said plurality of signal wirings being connected to said plurality of protective elements, respectively; and a plurality of dummy wirings which are formed over said protective elements, which are formed under said output electrode pads and which are not connected to said protective elements and said internal circuit; wherein each of said plurality of protective elements is formed over said main surface below a respective one of said plurality of output electrode pads, wherein each of the second ends of said plurality of signal wirings is electrically connected to the respective protective element of said plurality of protective elements over an area in which said plurality of protective elements are formed and below said plurality of output electrode pads, and wherein, in the direction in which said second relatively long side is extended, the number of said dummy wirings disposed in a peripheral edge portion of said semiconductor substrate is larger than the number of said dummy wirings disposed in a central portion of said semiconductor substrate.