Patent ID: 8411118
Filing Date: 2013-04-02
Classification: G09G

Abstract:
1. A flat panel display, comprising: a data interface configured to receive an image signal comprising a pixel data signal, a pixel clock signal, a vertical synchronization pulse signal, and a horizontal synchronization pulse signal; a scaler control circuit which has a first counter configured to receive the pixel clock signal and the vertical synchronization pulse signal in order to count a number of pulses of an independent pulse signal between two adjacent vertical synchronization pulses, a second counter configured to receive the pixel clock signal and the horizontal synchronization pulse signal in order to count a number of pulses of the independent pulse signal between two adjacent horizontal synchronization pulses, a math arithmetic unit connected to the first and the second counters and configured to provide a division operation to two counting results output from the first and second counters, a program arithmetic unit connected to the math arithmetic unit and configured to modify a division operation result output from the math arithmetic unit, and a scaler unit connected to the program arithmetic unit and configured to directly receive the pixel data signal in order to scale a resolution of the image signal; and a pulse generator connected to the scaler control circuit and configured to provide the independent pulse signal to the scaler control circuit; wherein the scaler control circuit is configured to determine a vertical resolution of the image signal by counting a number of pulses of the independent pulse signal respectively between two adjacent vertical synchronization pulses and between two adjacent horizontal synchronization pulses.