Patent ID: 6567895
Filing Date: 2003-05-20
Classification: G06F

Abstract:
The method of operating a multiple execution unit processor having an instruction pipeline and a loop cache memory capable of storing N execute packets, wherein N is an integer greater than zero, said method comprising the steps of:providing a loop cache memory for storing N execute packets wherein N is an integer greater than zero; building a software pipelined loop kernel of length n execute packets in said loop cache memory, wherein n is an integer greater than 0 and less than or equal to N; stalling said instruction pipeline; executing at least one iteration of said software pipelined loop kernel by issuing for each iteration said software pipelined loop kernel of n execute packets in said loop cache memory; detecting a loop exit condition; and resuming said instruction pipeline; wherein said building step comprises the steps of: signaling said processor via an instruction to begin building a software pipelined loop of length n clock cycles in said loop cache memory; inputting m clock cycles of loop building instructions to said processor, wherein m is greater than n and at each clock cycle m, one or more instructions are input; accumulating each of said m clock cycles of loop building instructions into said loop cache memory at one of said an execute packet locations; and wherein said accumulating step comprises the steps of: storing the first of said m clock cycles of loop-building instructions into the first of said n execute packet locations; calculating a new execute packet location by incrementing the execute packet location by one, and resetting the execute packet location to said first execute packet location if the incremented location is past the last of said n execute packet locations; storing the second of said m clock cycles of loop-building instructions into said new execute packet location; and repeating said calculating a new execute packet location step and said storing a clock cycle of loop-building instructions step until each of said m clock cycles of loop-building instructions has been stored in said loop cache memory.