Patent ID: 6456563
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A semiconductor memory device that operates in synchronization with a clock signal, comprising:an input circuit for taking in a plurality of external control signals in response to said clock signal changing from a first level to a second level; a decoder for selectively causing a first or second internal control signal to attain an active level according to the plurality of external control signals taken into said input circuit; a signal generating circuit for causing a third internal control signal to attain an active level in response to a predetermined time period having elapsed since said first internal control signal attained the active level and in response to a level of said clock signal changing; and a read/write circuit for performing part of a data read/write operation in response to said first internal control signal attaining the active level and for performing rest of said data read/write operation in response to said second and third internal control signals both attaining the active level.