Patent ID: 7470997
Filing Date: 2008-12-30
Classification: H01L

Abstract:
1. A semiconductor chip with a wirebonded wire, comprising: a silicon substrate; an active device in and on said silicon substrate; a first dielectric layer over said silicon substrate; an interconnecting metallization structure over said first dielectric layer, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said interconnecting metallization structure comprises a copper pad having a top surface and a sidewall, wherein said top surface has a first region and a second region between said sidewall and said first region; a second dielectric layer between said first and second metal layers; a passivation layer over said interconnecting metallization structure, on said second region and over said first and second dielectric layers, wherein an opening in said passivation layer is over said first region; an aluminum cap comprising a first portion directly over said first region and a second portion directly over said passivation layer, wherein said aluminum cap is connected to said copper pad through said opening in said passivation layer, and wherein said aluminum cap has a width greater than that of said opening in said passivation layer; an adhesion/barrier layer on said aluminum cap; and a gold layer on said adhesion/barrier layer and directly over said first and second portions of said aluminum cap, wherein said gold layer comprises a gold seed layer and an electroplated gold layer on said gold seed layer, wherein said electroplated gold layer has a thickness between 2 and 20 micrometers, and wherein said wirebonded wire is joined with said gold layer.