Patent ID: 6326268
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A process for fabricating a bit-line for a MONOS Flash cell device, the process comprising the steps of:providing a semiconductor substrate;growing a pad silicon oxide layer overlying said semiconductor substrate;forming a silicon nitride layer overlying said silicon oxide layer, said silicon nitride layer having an upper surface;performing a shallow trench isolation etch to form a trench in said semiconductor substrate;depositing silicon oxide to fill said trench;performing a chemical-mechanical-polishing process to planarize said silicon oxide and forming a planar surface continuous with said upper surface of said silicon nitride layer;removing said silicon nitride layer and said pad silicon oxide layer; anddepositing an oxide-nitride-oxide layer to overlie said semiconductor substrates wherein said silicon oxide functions as said bit-line oxide layer.