Patent ID: 6480415
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A method of manufacturing a nonvolatile semiconductor memory device including a memory array which comprises a plurality of memory cells in which predetermined voltages are applied to selected memory cells to change threshold voltages thereof, thereby storing data therein according to the difference between the threshold voltages, and which is provided with spare memory cells, and a latch circuit connected to bit lines of the memory array through a transmission switch, wherein at least substitutional information for replacing a defective bit with the spare memory cell is stored in the memory array, and the substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit, comprising the steps of:effecting writing and reading on the memory array in a wafer state to detect a defective bit and writing substitutional information for replacing the detected defective bit with the spare memory cell into a predetermined memory cell of the memory array; and thereafter cutting the wafer every nonvolatile semiconductor memory device chips and encapsulating the same into packages respectively, effecting writing and reading on the memory array in the package state to detect a defective bit, writing substitutional information for replacing the detected defective bit with the spare memory cell into a predetermined memory cell of the memory array, and extracting the normally-written memory cell.