Patent ID: 6421702
Filing Date: 2002-07-16
Classification: G06F

Abstract:
A computer system, comprising:a processor configured to run a non-real-time operating system and to receive a periodic time-slice interrupt; a memory coupled to the processor and configured to store the non-real-time operating system; a system clock configured to generate a clock signal; a peripheral isochronous device coupled to the processor and to the system clock, wherein the peripheral isochronous device is configured to receive the clock signal and to send or receive isochronous data at a rate dependent on the clock signal; and interrupt generation circuitry coupled to the processor and configured to generate the periodic time-slice interrupt dependent on the clock signal; wherein the non-real-time operating system is configured to initiate execution of a pending isochronous task when the processor receives the periodic time-slice interrupt so that execution of the pending isochronous task is synchronized with the rate the isochronous data is sent or received by the peripheral isochronous device.