Patent ID: 9209095
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method of fabricating a bipolar transistor device on a wafer, the method comprising the steps of: forming fin hardmasks on the wafer; forming a dummy gate on the wafer, over the fin hardmasks; forming spacers on opposite sides of the dummy gate; doping the wafer to form emitter and collector regions on both sides of the dummy gate; depositing a dielectric filler layer onto the wafer, surrounding the dummy gate; removing the dummy gate selective to the dielectric filler layer so as to form a trench in the dielectric filler layer, wherein removal of the dummy gate exposes the fin hardmasks present on the wafer within the trench; patterning fins in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device; recessing the fins in the base region; re-growing the base region from an epitaxial SiGe, Ge or III-V semiconductor material; and forming a contact to the base region.