Patent ID: 6077742
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A method for fabricating an array of dynamic random access memory (DRAM) cells having zigzag-shaped stacked capacitors on a semiconductor substrates, comprising the steps of:providing said semiconductor substrate having device areas surrounded by field oxide areas, and each device area having a field effect transistor (FET), each of said transistors having a polycide gate electrode and source/drain contact areas;forming a planar first insulating layer over said device areas and said field oxide areas;forming contact openings in said first insulating layer to said source/drain contact areas;depositing a first polysilicon layer over said first insulating layer and filling said contact openings;depositing a silicide layer over said first polysilicon layer;photoresist masking and anisotropic plasma etching said silicide layer and said first polysilicon layer to said first insulating layer to form polycide bit lines and extending over some of said contact openings to provide bit line contacts, and concurrently leaving portions of said first polysilicon layer in remaining said contact openings to said source/drain areas to form node contacts for said stacked capacitors;depositing a second insulating layer over said bit lines and over said node contacts, and thereafter forming said stacked capacitors by;selectively and anisotropically etching openings in said second insulating layer to said node contacts for said stacked capacitors,depositing and blanket etching back a second polysilicon layer to said second insulating layer thereby leaving portions of said second polysilicon layer in said openings to form electrical contacts to said node contacts,depositing a third insulating layer;depositing a multilayer of two insulator types having alternate layers composed of one insulator type and the other layers composed of the second insulator type, and said second insulator type, composed of a borosilicate glass (BSG), and having a different etch rate than said second insulator type,masking and anisotropically plasma etching recesses having vertical sidewalls in said multilayer and said third insulating layer to said second insulating layer and exposing said electrical contacts to said node contacts,isotropically etching said multilayer in sate vertical sidewalls having said alternate layers with said different etch rates, and thereby forming a zigzag-shaped profile in said sidewalls,depositing a conformal amorphous silicon layer over and in said recesses and annealing to form a hemispherical grain (HSG) layer for capacitor bottom electrodes,depositing and etching back a fourth insulating layer to fill said recesses and exposing said HSG layer on the top surface of said multilayer,selectively etching back and removing said HSG layer on said top surface of said multilayer, while said fourth insulating layer prevents etching of said HSG layer in said recesses,isotropically removing said fourth insulating layer and said multilayer to form an array of freestanding said capacitor bottom electrodes having zigzag sidewall profiles with said HSG structure on inner surfaces of said capacitor bottom electrodes,forming an interelectrode dielectric layer on said bottom electrodes,depositing and patterning & fourth polysilicon layer and patterning to form the capacitor top electrodes and thereby completing said array of DRAM cells.