Patent ID: 7607114
Filing Date: 2009-10-20
Classification: G03F,G06F,Y02P

Abstract:
1. A method of designing a mask layout comprising the steps of: providing to a software tool a circuit design comprising a plurality of design layers comprising features arranged on a two-dimensional plane, said design layers aligned to one another along a third dimension; and using said software tool to perform the steps of: identifying a selected one of said plurality of design layers including a critical feature comprising critical feature edges to be formed on a substrate; identifying a constraining region associated with an influencing feature on one of said plurality of design layers different than said selected design layer, wherein said influencing feature interacts with said critical feature, said constraining region being associated with one or more constraints; determining a tolerance band associated with said critical feature, wherein said tolerance band defines an enclosed region within which said critical feature edges of said critical feature when formed on the substrate would satisfy a predetermined criterion, and wherein said tolerance band comprises at least one edge that is constrained in accordance with said one or more constraints associated with said constraining region; and pre-selecting a subset of said plurality of design layers so that each of said subset of layers comprises a critical feature; ranking said subset according to a predetermined criterion prior to said step of identifying a selected one of said plurality of design layers; and performing, for each of said subset in the order of said ranking, said step of identifying a selected one of said plurality of design layers, said step of identifying a constraining region and said step of determining a tolerance band.