Patent ID: 7441100
Filing Date: 2008-10-21
Classification: G06F

Abstract:
1. A method of synchronizing a plurality of processors of a multi-processor computer system on a synchronization point, said method comprising: creating a circular reference arrangement for said plurality of processors, wherein a first processor from among said plurality of processors is designated said lead processor and a second processor from among said plurality of processors is designated said tail processor, and wherein said lead processor is adjacent to said tail processor in said circular reference arrangement; triggering a first set of processors to enter an entry holding loop in response to said first set of processors encountering said synchronization point before said lead processor associated with said plurality of processors; triggering said first set of processors to enter an exit holding loop in response to said lead processor encountering said synchronization point, said first set of processors entering said exit holding loop in a cascading manner starting with said lead processor following a sequence established by said circular reference arrangement, with each processor of said first set of processors being triggered by its immediate predecessor in said sequence; and triggering said plurality of processors to leave said exit holding loop in response to said tail processor associated with said plurality of processors encountering said synchronization point, said plurality of processors leaving said exit holding loop in a cascading manner starting with said tail processor following said sequence established by said circular reference arrangement, with each processor of said plurality of processors being triggered by its immediate predecessor in said sequence.