Patent ID: 7749904
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A method of forming an integrated circuit having a dual damascene interconnect structure comprising: providing a substrate having a first etched region therein; filling said first etched region with a first protective layer, wherein said first protective layer is a BARC material having a high etch rate, and said high etch rate BARC material has the following properties: it may be etched at least 25% or more faster than layers through which said first and second etched openings are made; it completely fills said first etched region; and it absorbs light at a wavelength used to expose said resist; etching back said first protective layer to form a recessed plug within said first etched opening; coating said substrate and said recessed plug with a second protective layer; coating said second protective layer with a resist layer; patterning said resist layer and said second protective layer to define an opening encompassing said first etched opening wherein said second protective layer within said opening is removed and wherein said first protective layer remains within said first etched opening; thereafter forming a second etched region encompassing a top portion of said first etched region; thereafter removing said resist layer and said first and second protective layers; and thereafter filling said first and second etched regions with a conductive material to complete formation of said dual damascene interconnect.