Patent ID: 6751112
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A content addressable memory cell comprising:a word line; a first bit line; a second bit line; a pair of transistors arranged to store a first bit of data at a first point and a second bit of data that is the complement of the first bit of data at a second point; a first transistor coupled to the word line, the first bit line and the first point; a second transistor coupled to the word line, the second bit line and the second point; a p-channel match transistor switchable to a first state in response to a first predetermined relationship between the first and second bits and third and fourth bits transmitted on the first bit line and the second bit line and switchable to a second state in response to a second predetermined relationship between the first and second bits and the third and fourth bits; a p-channel third transistor coupling the first bit line, first point and match transistor; and a p-channel fourth transistor coupling the second bit line, second point and match transistor.