Patent ID: 6559787
Filing Date: 2003-05-06
Classification: H03K

Abstract:
For use in an analog-to-digital converter (ADC), an ADC stage capable of receiving a differential analog input signal, quantizing said differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of said differential analog input signal, said ADC stage comprising:a first comparator coupled to said differential analog input signal, wherein said first comparator is enabled and compares a first differential input and a second differential input of said differential analog input signal when a received LATCH signal is enabled and is disabled when said received LATCH signal is disabled; and a second comparator coupled to said differential analog input signal in parallel with said first comparator, wherein an input stage of said second comparator is substantially identical to an input stage of said first comparator and said second comparator is enabled and compares said first differential input and said second differential input of said differential analog input signal when said received LATCH signal is disabled and is disabled when said received LATCH signal is enabled.