Patent ID: 7152151
Filing Date: 2006-12-19
Classification: G06F

Abstract:
1. A multi-processor system comprising: an arrangement of a plurality of processor nodes, each having a processor, memory and a communications bus interface; a plurality of parallel point-to-point communication busses disposed between pairs of said communications bus interfaces such that data may be moved between processor nodes; one or more I/O busses disposed to communicate with all said processor nodes; and one or more configurable digital signal processing frameworks selectable disposed in series between said communication bus or I/O bus, having an input buffer for receiving data from processor node, an input data manipulator for manipulating said buffered data, a digital down converter for scaling said manipulated data, a signal processing node containing one or more signal processing circuits defined by programmable logic for processing said scaled data, an output data manipulator for converting said processed data from a first representation to a second representation, and an output data buffer separate from said input buffer for presenting said converted data to a second processor node.