Patent ID: 6436766
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A process for fabricating a memory cell comprising:depositing a hard mask overlying an ONO layer, wherein the hard mask comprises a material selected from the group consisting of polysilicon and silicon, the ONO layer is formed over a semiconductor substrate having a principal surface, and the ONO layer has a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer, and a second silicon dioxide layer overlying the silicon nitride layer; applying a layer of resist overlying the hard mask; patterning the hard mask; doping the semiconductor substrate with boron using the hard mask as a doping mask; doping the semiconductor substrate with an n-type dopant using the hard mask as a doping mask; etching the exposed ONO layer to expose part of the semiconductor substrate; forming a bit-line oxide region overlying the exposed semiconductor substrate; and removing the hard mask.