Patent ID: 6748516
Filing Date: 2004-06-08
Classification: G06F

Abstract:
A signal processor for performing digital signal processing instructions, the signal processor comprising:at least one signal processing unit including, a primary stage to execute a primary digital signal processing sub-instruction of a single digital signal processing instruction based upon current data, the primary digital processing sub-instruction being a dyadic instruction having a primary main operation and a primary sub operation; and a shadow stage to simultaneously execute a shadow digital signal processing sub-instruction of the single digital signal processing instruction based upon delayed data; wherein: the primary stage includes a first multiplier and a first adder; the shadow stage includes a second multiplier and a second adder; each of the first and second adders and the first and second multipliers have a multiplexer at their respective inputs to configure the signal processing unit to simultaneously execute the primary and shadow digital signal processing sub-instructions, respectively; and the at least one signal processing unit further includes an accumulator having registers to couple to the first multiplier or the first adder of the primary stage to provide operands or to store results therefrom for the primary digital signal processing sub-instruction and to couple to the second multiplier or the second adder of the shadow stage to provide operands or to store results therefrom for the shadow digital signal processing sub-instruction, respectively, the accumulator having registers to couple to a buffer memory to store digital signal processed outputs generated by the primary and shadow digital signal processing sub-instructions, respectively.