Patent ID: 6018783
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A register access controller for controlling coupling of a selected register, of a plurality of registers, to a bus interface during a zero-wait continuous burst transfer of data from the plurality of registers to the bus interface, the register access controller comprising:a respective output driver, coupled between a respective register of the plurality of registers and the bus interface, that turns on to couple the respective register to the bus interface and that turns off to decouple the respective register from the bus interface;a clock signal input for accepting a clock signal having a periodic transition for every period of the clock signal, a selected register of the plurality of registers being chosen at every periodic transition of the clock signal for coupling to the bus interface, a register control signal turning on the respective output driver of the selected register; anda driver delaying unit, coupled to the clock signal input and each respective output driver, for providing an enable control signal which turns the respective output driver of each of the plurality of registers off for a predetermined delay time at each periodic transition of the clock signal, wherein the respective output driver of the selected register is turned on by the register control signal for a remainder time after the predetermined delay time during each period of the clock signal.