Patent ID: 6014751
Filing Date: 2000-01-11
Classification: G06F,Y02D

Abstract:
Apparatus for operating an integrated circuit in a full-power state and in first and second reduced power states, the integrated circuit including a first set of functional units required to perform a cache coherency operation and a second set of functional units not required to perform the cache coherency operation, the apparatus comprising:a first input to receive a configuration signal, the configuration signal indicating whether the integrated circuit transitions from the full-power state to the first or to the second reduced power statea second input to receive a power-down signal, the power-down signal transitioning the integrated circuit from the full-power state to either the first or to the second reduced power state in accordance with the configuration signal;a third input to receive an access signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a device external to the integrated circuit; andpower-reduction logic to transition the integrated circuit from the full-power state to the first or to the second reduced power state in accordance with the configuration signal and responsive to the power-down signal, and to enable the integrated circuit to perform a cache coherency operation in both the first and second reduced power states by:(1) when in the first reduced power state, continually propagating a clock signal to the first set of functional units, within the integrated circuit, required to perform a cache coherency operation; and(2) when in the second reduced power state, gating a clock signal to both the first and the second sets of functional units within the integrated circuit and to propagate the clock signal to the first set of functional units, but not the second set of functional units, in response to the access signal.