Patent ID: 8139409
Filing Date: 2012-03-20
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a semiconductor substrate; a logic layer fabricated front-end-of-the-line (FEOL) on the semiconductor substrate, the logic layer including active circuitry; a cross-point memory array fabricated back-end-of-the-line (BEOL) directly above and in contact with the semiconductor substrate, the cross-point memory array including a positional voltage adjuster circuit included in the active circuitry and configured to access a memory cell associated with a X-line conductive array line and a Y-line conductive array line in a slice, the positional voltage adjuster circuit being configured to apply a modified read voltage to compensate for one or more voltage drops associated with the X-line conductive array line between the positional voltage adjuster circuit and the memory cell.