Patent ID: 6545306
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A semiconductor memory device comprising:a substrate; transistors formed on the substrate, each of the transistors having a gate electrode structure including a gate electrode, a gate electrode capping pattern formed on the gate electrode, and sidewall spacers formed on sidewalls of the gate electrode and the gate electrode capping pattern, and having a source region and a drain region; an interlevel dielectric layer, including a bit line contact hole and a lower electrode contact hole, formed over an entire surface of the substrate including the transistors and having high selectivity with respect to the gate electrode capping pattern and the sidewall spacers; a bit line connector formed within the bit line contact hole of the interlevel dielectric layer and connected to a drain region of at least one of the transistors; a bit line formed on the interlevel dielectric layer and electrically connected to the bit line connector; a bit line capping pattern covering the bit line; a capacitor lower electrode connector, formed within the lower electrode contact hole of the interlevel dielectric layer, that extends to a same level as a top surface of the bit line capping pattern; and a capacitor formed on the capacitor lower electrode connector, the capacitor including a lower electrode, a dielectric layer, and an upper electrode.