Patent ID: 9214933
Filing Date: 2015-12-15
Classification: H03K

Abstract:
1. A circuit, comprising: a first power node configured to carry a first voltage, a voltage level of the first voltage being K·V a second power node configured to carry a second voltage, a voltage level of the second voltage being the zero reference level; an output node; K P-type transistors serially coupled between the first power node and the output node, each of the K P-type transistors being denoted as an i-th transistor of the K P-type transistors, i being an order index ranging from 1 to K, a smaller order index i being used to denote a transistor closer to the first power node, and a gate of the i-th transistor is configured to receive: K N-type transistors serially coupled between the second power node and the output node, each of the K N-type transistors being denoted as an j-th transistor of the K N-type transistors, j being an order index ranging from 1 to K, a smaller order index j being used to denote a transistor closer to the second power node, and a gate of the j-th transistor is configured to receive: