Patent ID: 6908845
Filing Date: 2005-06-21
Classification: H01L

Abstract:
1. A method of constructing art electronic assembly, comprising: forming a plurality of plugs in a first substrate; manufacturing a first integrated circuit on a first side of the first substrate, the first substrate and the first integrated circuit jointly forming a first die; removing the plugs to leave a plurality of openings in the first substrate; forming a seed layer in each opening and as a contact on a second side of the first substrate opposing the first side; plating a plurality of conductive members, each conductive member having a respective portion being plated on a portion of the seed layer in the respective opening to form a via in each respective opening and being plated on a contact of the respective seed layer on the second side of the first substrate to form a bump on each respective contact and standing proud of the substrate; and locating the first die on a second component having a circuit, the first integrated circuit being connected through the material of the bump and the via of each conductive members to the circuit of the second component.