Patent ID: 9048840
Filing Date: 2015-06-02
Classification: H03K

Abstract:
1. An integrated circuit comprising: a first circuit configured to generate a first pair of complementary input signals in response to a first control input signal; a second circuit configured to generate a first pair of complementary output signals and a second pair of complementary output signals in response to said first pair of complementary input signals, a first bias signal, and a second bias signal; a third circuit configured to (i) receive a supply voltage, a ground potential, and a bias input signal, and (ii) generate said first and said second bias signals in response to said supply voltage, said ground potential, and said bias input signal; a first complementary pair of transistors configured to drive a first series output of said integrated circuit in response to a true signal of said first pair of complementary output signals and a true signal of said second pair of complementary output signals; and a second complementary pair of transistors configured to drive a first shunt output of said integrated circuit in response to a complement signal of said first pair of complementary output signals and a complement signal of said second pair of complementary output signals.