Patent ID: 6090665
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method of producing source regions of a flash EEPROM cell array which comprises the following steps:forming a layer structure on a substrate, the layer structure including a lower silicon oxide layer, a polysilicon layer on the lower silicon layer, and an upper silicon oxide layer on the polysilicon layer;etching a trench through at least the upper silicon oxide layer and the polysilicon layer and forming a channel region for each cell of a flash EEPROM cell array;setting a thickness of the lower silicon oxide layer of the cells by thermal oxidation and forming an insulation between the polysilicon layer and the trench;forming a floating-gate electrode respectively extending into the trench of a cell;producing an insulation layer on the floating gate electrode of the cells;forming word lines on the insulation layer which, above the floating-gate electrodes, act as control-gate electrodes;applying a photomask at least partly covering the word lines and leaving exposed a region between the word lines; andproducing source regions with self-alignment between the respective word lines by implanting a dopant.