Patent ID: 6943414
Filing Date: 2005-09-13
Classification: H01L

Abstract:
1. An integrated circuit chip formed in a semiconductor substrate, comprising: a first interconnect metal layer in said semiconductor substrate; a first intermetallic dielectric layer in said semiconductor substrate situated over said first interconnect metal layer; a metal resistor in said semiconductor substrate situated over said first intermetallic dielectric layer, said metal resistor being only connected to a second interconnect metal layer; a dielectric cap layer in said semiconductor substrate patterned on said metal resistor; a second intermetallic dielectric layer in said semiconductor substrate formed over said dielectric cap layer and said metal resistor; said second interconnect metal layer in said semiconductor substrate being situated over said second interinetallic dielectric layer; a first intermediate via in said semiconductor substrate connected to a first terminal of said metal resistor, said first intermediate via being further connected to a first metal segment patterned in said second interconnect metal layer; a second intermediate via in said semiconductor substrate connected to a second terminal of said metal resistor, said second intermediate via being further connected to a second metal segment patterned in said second interconnect metal layer.