Patent ID: 9171634
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A memory device comprising: an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line, each column group having an active mode of operation where a read operation is able to be performed on an activated memory cell within that column group, and a non-active mode of operation where said read operation is not able to be performed; precharge circuitry configured, for each column group, to precharge a voltage on the associated read bit line to a first voltage level prior to said read operation; each memory cell comprising coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell; reference line control circuitry configured, for each reference line having an associated column group in said active mode of operation, to connect that reference line to a second voltage level different to said first voltage level, and configured for each reference line not having an associated column group in said active mode of operation to disconnect that reference line from said second voltage level; and word line boosting circuitry configured to generate an asserted word line signal at a boosted voltage level on the read word line associated with the row of memory cells to be activated during said read operation; during said read operation the coupling circuitry associated with each activated memory cell is configured to be activated by the asserted word line signal and to selectively discharge the associated read bit line towards the second voltage level present on said associated reference line dependent on a data value stored within that activated memory cell; and for each reference line not having an associated column group in said active mode of operation, the action of the reference line control circuitry disconnecting that reference line from the second voltage level serving to remove a leakage current path through the coupling circuitry of each memory cell of that associated column group.