Patent ID: 7747808
Filing Date: 2010-06-29
Classification: G06F

Abstract:
1. A host controller for use in a bus communication device having a host microprocessor and a system memory, the host controller comprising: a first interface for direct connection to a memory bus which connects the host microprocessor and the system memory, such that the host controller is adapted to act only as a slave on the memory bus; an internal memory configured into at least two distinct sections to store a plurality of transfer-based transfer descriptors including a first section configured to store a plurality of transfer-based transfer descriptor headers, and a second section configured to store a plurality of transfer-based transfer descriptor payloads, the respective transfer-based transfer descriptors received through the first interface, said internal memory having a plurality of transfer-based transfer descriptor header and transfer-based transfer descriptor payload locations mapped in the host microprocessor, said first section of the internal memory is sub-divided into two sub-parts, and is adapted to consecutively store transfer descriptor headers relating to periodic transfers in a first subpart, and to consecutively store transfer descriptor headers relating to asynchronous transfers in a second sub-part; and a second interface, for connection to an external bus, wherein the host controller is adapted to: