Patent ID: 6218240
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method for forming a low voltage coefficient capacitor, comprising the steps of:providing a substrate having a first region and a second region, wherein the first region is for forming a capacitor and the second region is for forming a gate;forming a gate dielectric layer over the substrate;forming a polysihcon layer on the gate dielectric layer;forming a first dielectric layer on the polysilicon layer;patterning the first dielectric layer to expose a portion of the polysilicon layer in the first region;implanting ions into the exposed portion of the polysilicon layer to form a doped polysilicon region in the first region;forming a silicide layer conformal to the substrate;forming a second dielectric layer on the silicide layer;forming a conductive layer on the second dielectric layer;patterning the conductive layer, the second dielectic layer and the silicide layer to form a capacitor structure on the doped polysilicon region in the first region;removing the first dielectric layer;patterning the polysilicon layer and the gate dielectric layer to form a gate structure in the second region;performing a healing process to eliminate defects in exposed surfaces of the capacitor structure and the gate structure;forming a lightly doped drain in the second region;forming spacers on each sidewall of the capacitor structure, the gate structure and the doped polysilicon region, respectively; andforming a source/drain region in the second region.