Patent ID: 6708269
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A microprocessor system, comprising:a first microprocessor coupled to a second microprocessor, the first and second microprocessors capable of speculative processing, the second microprocessor including: a front end to fetch instructions; a memory order buffer (MOB) coupled to the front end to receive microoperations associated with the fetched instructions, the MOB having a set of buffers to hold data associated with executed microoperations; and a data access control (DAC) unit coupled to the MOB and to a cache by a bus, the DAC having request buffers related to controlling a subsequent loading and storing of the data between the cache and the MOB, the MOB and the DAC being responsive to one of a plurality of different types of fence requests to force completion of at least one of the microoperations by draining data in the set of buffers of the MOB or data in the request buffers of the DAC, and delaying completion of other microoperations associated with the first microprocessor while the data is drained, the different types of fence requests corresponding to different types of memory operations or memory types.