Patent ID: 7865635
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each of the CPU cores breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, the buffer device comprising: a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein when the plurality of CPU cores is two CPU cores each of which includes an odd-number port for outputting an odd-number line of the data lines and an even-number port for outputting an even-number line of the data lines as the ports, and the two CPU cores are arranged symmetrically about the reference line, odd-number line buffers connected to the odd-number ports out of the line buffers are arranged symmetrically about the reference line and even-number line buffers connected to the even-number ports out of the line buffers are arranged symmetrically about the reference line, and when the even-number port of each of the two CPU cores is arranged on the reference line side, the odd-number line buffers are arranged on the reference line side, and when the odd-number port of each of the two CPU cores is arranged on the reference line side, the even-number line buffers are arranged on the reference line side.