Patent ID: 6671851
Filing Date: 2003-12-30
Classification: H03M,H04L

Abstract:
A rate matching circuit for adjusting the number of bits in a data block, the data block comprising a plurality of interleaved words generated by the action of an interleaving circuit on a coded output generated by the action of a coding circuit on a digital input, the coded output having a greater number of bits than the digital input, the rate matching circuit having means for adjusting the number of bits in the data block using a rate matching pattern to provide data bits for transmission during respective frames of a transmission channel, and means for selecting the rate matching pattern as a function of an interleaving depth, a bit deletion/repetition rate and said digital input, wherein a bit deletion/repetition pattern is selected to ensure that the deleted or repeated bits are not required to enable all bits from the digital input to be reconstructed.