Patent ID: 9099177
Filing Date: 2015-08-04
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines extending in an X direction parallel to a principal plane of a semiconductor substrate; a plurality of diode layers formed over the word lines; a plurality of laminated bodies being formed cyclically in the X direction and respectively having first gate semiconductor layers formed over the diode layers in the manner of extending in a Y direction intersecting the X direction and being parallel to the principal plane of the semiconductor substrate, a plurality of second gate semiconductor layers formed over the first gate semiconductor layers in the manner of extending in the Y direction and being laminated to each other through insulation layers, and third gate semiconductor layers formed over the second gate semiconductor layers in the manner of extending in the Y direction; a plurality of first channel layers formed between the first gate semiconductor layers through insulation layers and coupled electrically to the diode layers; a plurality of first gate insulation film layers formed on a +X side and a −X side of the sides of the second gate semiconductor layers and the third gate semiconductor layers; a plurality of second channel layers formed cyclically in the Y direction on the +X side of the sides of the second gate semiconductor layers and the third gate semiconductor layers through the first gate insulation film layers and coupled electrically to the first channel layers; a plurality of first resistance change material layers being formed cyclically in the Y direction on the +X side of the sides of the second gate semiconductor layers through the first gate insulation film layers and the second channel layers, being coupled electrically to the first channel layers, and comprising a material the resistance value of which varies in response to a flowing electric current; a plurality of third channel layers formed cyclically in the Y direction on the −X side of the sides of the second gate semiconductor layers and the third gate semiconductor layers through the first gate insulation film layers and coupled electrically to the first channel layers; a plurality of second resistance change material layers being formed cyclically in the Y direction on the −X side of the sides of the second gate semiconductor layers through the first gate semiconductor layers and the third channel layers, being coupled electrically to the first channel layers, and comprising a material the resistance value of which varies in response to a flowing electric current; and a plurality of bit lines formed vertically over the respective word lines on the basis of the principal plane of the semiconductor substrate in the manner of extending in the X direction and coupled electrically to the second channels and the third channels, wherein the respective word lines are bundled with other word lines, wherein the respective bit lines are bundled with other bit lines, and wherein two of the bit lines formed vertically over respective bundled two word lines in the word lines are separated electrically.