Patent ID: 6566612
Filing Date: 2003-05-20
Classification: H01L,Y10T

Abstract:
An electronic assembly comprising:a semiconductor chip having a top surface overlayed by a layer of insulating material containing a first multiplicity of via openings each filled with a solder bump on top of a bond pad, said layer of insulating material having a thickness between about 20 &mgr;m and about 200 &mgr;m, and a circuit board having a top surface formed with a second multiplicity of conductive pads positioned in a mirror image relationship to said first multiplicity of via openings on said semiconductor chip, said top surface of the circuit board intimately joins said top surface of the semiconductor chip with an underfill layer disposed thereinbetween such that electrical communication between said first multiplicity of via openings filled with said solder bumps and said corresponding second multiplicity of conductive pads is established.