Patent ID: 6531387
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for fabricating an integrated circuit or circuits in a wafer, the method comprising polishing the wafer, wherein the wafer comprises (i) a semiconductor substrate, (ii) a dielectric formed over the semiconductor substrate, the dielectric having a plurality of trenches therein, and (iii) a conductive material formed on the dielectric and in the trenches;wherein the polishing operation comprises polishing the conductive material to remove the conductive material from the top surface of the dielectric; wherein the dielectric and the conductive material in the trenches form a first structure and a second structure spaced from the first structure, wherein each of the first and second structures have the same distance between corresponding points of adjacent trenches, wherein the first structure is adjoined on at least two opposite sides by first regions which do not have said conductive material or in which said conductive material has a lower density than in the first structure, and the second structure is adjoined on at least two opposite sides by second regions which do not have said conductive material or in which said conductive material has a lower density than in the second structure, wherein the second regions are disjoint from the first regions or overlap the first regions; wherein the second structure is smaller in size than the first structure; after the polishing operation, estimating an erosion in the first structure by measuring an erosion in the second structure with a probe that comes as close as 2 &mgr;m or closer to the wafer at the location of the second structure.