Patent ID: 6436773
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method for fabricating a test field effect transistor on a semiconductor substrate, the method including the steps of:A. depositing a layer of gate dielectric material on said semiconductor substrate; B. depositing a layer of gate electrode material on said layer of gate dielectric material; C. forming a dummy structure on said gate electrode material, wherein said dummy structure is disposed over a shaped area of said gate electrode material and of said semiconductor substrate, and wherein said dummy structure has at least one sidewall around a perimeter of said shaped area; D. forming a spacer structure to surround said at least one sidewall of said dummy structure outside of said perimeter of said shaped area; wherein said spacer structure has a width extending out from said perimeter of said shaped area; E. etching away said dummy structure such that said shaped area of said gate electrode material is exposed and such that said spacer structure remains outside of said perimeter of said shaped area; F. etching away any exposed regions of said gate electrode material and of said gate dielectric material not under said spacer structure, wherein said gate dielectric material remaining under said spacer structure forms a gate dielectric of said test field effect transistor, and wherein said gate electrode material remaining under said spacer structure forms a gate electrode of said test field effect transistor, and wherein said gate dielectric and said gate electrode are formed outside of said perimeter of said shaped area on said semiconductor substrate; and G. implanting a drain and source dopant into exposed regions of said semiconductor substrate to form a first drain or source junction from said drain and source dopant being implanted into said semiconductor substrate within said shaped area surrounded by said gate dielectric and said gate electrode, and to form a second drain or source junction from said drain and source dopant being implanted into said semiconductor substrate outside said shaped area beyond said gate dielectric and said gate electrode; and wherein a width of said test field effect transistor is said perimeter of said shaped area, and wherein a length of said test field effect transistor is the width of said gate dielectric and said gate electrode extending out from said perimeter of said shaped area.