Patent ID: 6161205
Filing Date: 2000-12-12
Classification: G01R,G06K

Abstract:
A testing system for evaluating a plurality of integrated circuit chips, comprising:an interrogator unit having a radio communication range, the interrogator unit including data evaluation circuitry configured to transmit interrogating information via radio communication and to receive test data from the plurality of integrated circuits via radio communication; anda plurality of integrated circuit chips respectively configured to be positioned remotely from the interrogator unit, but within the radio communication range, respective integrated circuit chips including operational circuitry, and test interface circuitry electrically coupled to the operational circuitry and configured to receive the interrogating information from the data evaluation circuitry of the interrogator unit, the test interface circuitry being configured to test cycle the operational circuitry according to the interrogating information, the test interface circuitry being configured to transmit via radio communication test data output by the operational circuitry in response to the interrogating information back to the data evaluation circuitry of the interrogator unit, the data evaluation circuitry of the interrogator unit being configured to examine the test data to determine for respective ones of the integrated circuit chips whether the chip is defective.