Patent ID: 6326831
Filing Date: 2001-12-04
Classification: H03K

Abstract:
A level shift circuit comprising:a first and a second controllable semiconductor devices each having an electrode acting as a potential reference and connected to a common potential, the potential reference electrode and a main electrode being electrically connected together while a conduction signal is being input between the potential reference electrode and a control electrode;a DC power supply having one electrode connected to an external circuit at its predetermined site varying between the common potential and a predetermined high potential, the DC power supply having a voltage lower than a voltage between said two potentials;first and second load resistors each having one end connected to the other electrode of the DC power supply and having the other end connected to the main electrode of a corresponding one of the first and second controllable semiconductor devices; anda logic circuit operating under said DC power supply;wherein a pulse-like conduction signal is input to each of the control electrodes of the first and second controllable semiconductor devices with different timings so that said conduction through the controllable semiconductor devices causes a pulse-like voltage drop in said first and second load resistors, the voltage drop being then communicated to said logic circuit as a signal;wherein the level shift circuit includes signal-disabling means for preventing a signal corresponding to a pulse-like voltage drop from being communicated to said logic circuit when the voltage drop simultaneously occurs in the first and second load resistors;wherein said signal-disabling means masks a first load resistor signal corresponding to a voltage drop in the first load resistor and communicated to said logic circuit, using a second load resistor masking signal generated based on a voltage drop in the second load resistor, while masking a second load resistor signal corresponding to a voltage drop in the second load resistor and communicated to said logic circuit, using a first load resistor masking signal generated based on a voltage drop in the first load resistor;wherein a pulse width of the second load resistor masking signal is wider than a pulse width of the first load resistor signal communicated to the logic circuit; andwherein a pulse width of the first load resistor masking signal is wider than a pulse width of the second load resistor signal communicated to the logic circuit.