Patent ID: 6713381
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of forming a semiconductor device comprising:forming a first interconnect overlying a semiconductor device substrate; forming a second interconnect overlying portions of the first interconnect, wherein the second interconnect is further characterized as a copper interconnect having a bond pad portion; forming a conductive barrier layer over the bond pad portion; forming an oxidation-resistant layer over the conductive barrier layer; forming a passivation layer overlying the oxidation-resistant layer; and forming a partial opening in the passivation layer, wherein a depth of the partial opening is less than a thickness of the passivation layer in a region of the passivation layer where the partial opening is formed; forming a die coat layer over the passivation layer; forming an opening in the die coat layer, wherein forming the opening in the die coat layer exposes the partial opening in the passivation layer and further includes partially removing the passivation layer about an edge region of the partial opening in the passivation layer; etching through the partial opening in the passivation layer to expose the conductive barrier layer after forming the opening in the die coat layer; and forming a pad limiting metal over the conductive barrier layer, wherein the pad limiting metal layer includes a chromium layer and wherein the chromium layer contacts the conductive barrier layer; and forming a conductive bump over the pad limiting metal layer.