Patent ID: 6707398
Filing Date: 2004-03-16
Classification: G06F,H03M

Abstract:
A method for execution by a microprocessor to pack bit streams of variable lengths, the method comprising:receiving a first bit segment from a first vector register; receiving a second bit segment from a second vector register; determining whether or not a sum of a first bit length of the first bit segment and a second bit length of the second bit segment is larger than a required length; generating a third bit segment from the first and second bit segments, the third bit segment generated from concatenating the first bit segment and a beginning portion of the second bit segment such that a third bit length of the third bit segment is equal to the required length when the sum is larger than the required length, the third bit segment generated from concatenating the first and second bit segments when the sum is not larger than the required length; and outputting the third bit segment in a third vector register; wherein the above operations are performed in response to the microprocessor receiving a first single instruction.