Patent ID: 6173386
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A parallel processor, comprising:a plurality of parallel processing elements, each of the elements comprising a respective central processing unit;a fault signal generator for generating a global fault signal for being supplied to the elements to trigger all of said elements to enter a debug mode of operation, said generator generating said fault signal in response to one of a debug enable signal supplied to said processor from a source external to said processor and a global exception signal, the debug mode of operation being a single step mode of operation, the global fault signal indicating that an error condition has occurred in one of the elements, the processor also comprising an exception handling mechanism that stores an exception identification value that uniquely identifies the one of the elements in which the error condition has occurred, the value stored in the mechanism being readable by a processing system external to the processor, the mechanism also generating the global exception signal in response to another exception signal generated by the one element.