Patent ID: 7519087
Filing Date: 2009-04-14
Classification: G06F,H03K

Abstract:
1. A frequency multiply circuit comprising: a synchronous delay circuit including a period measuring delay circuit for measuring a period of an input signal and a plurality of delay reproducing delay circuits, each delay reproducing delay circuit having a delay time thereof variably set according to a frequency-multiplication factor and based on the period of the input signal measured by said period measuring delay circuit and delaying the input signal by the set delay time to output the delayed signal; a multiplexing circuit, receiving a plurality of signals that have different phases and are output from said synchronous delay circuit, for multiplexing said plurality of signals received; and a control circuit for variably setting a ratio among a number of delay stages of said period measuring delay circuit and numbers of delay stages of said plurality of delay reproducing delay circuits an output signal obtained by multiplying a frequency of the input signal being output from said multiplexing circuit.