Patent ID: 8817552
Filing Date: 2014-08-26
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory layers arranged in multilayer, each memory layer including a plurality of first lines, a plurality of second lines, and a plurality of memory cells selected by said first lines and said second lines; a pulse generator operative to generate pulses required for data access to an access target memory cell in said plurality of memory cells; and a control circuit operative to control said pulse generator such that the pulse output from said pulse generator has energy in accordance with the memory layer to which said access target memory cell belongs, wherein said control circuit controls said pulse generator based on said address of said access target memory cell and a parameter previously set at each of said memory layers; and a current limiter operative to limit current flowing in said access target memory cell on access to said access target memory cell, wherein said current limiter sets a limit value of current in accordance with an address of said access target memory cell.