Patent ID: 8184468
Filing Date: 2012-05-22
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including a plurality of nonvolatile memory cells arranged in rows and columns, each of the plurality of memory cells having a variable resistance level depending on data stored therein; a plurality of word lines, each of the word lines being coupled with the columns of nonvolatile memory cells; a plurality of local bit lines, each of the local bit lines being coupled with the rows of nonvolatile memory cells; at least one write global bit line to supply write data to the memory cell array, the at least one write global bit line selectively coupled with the plurality of local bit lines; at least one read global bit line to supply read data to the memory cell array, the at least one read global bit line selectively coupled with the plurality local bit lines; and a controller configured to permit the at least one write global bit line and the at least one read global bit line to have different voltage levels than each other during a standby period, wherein the controller permits the at least one write global bit line to float and the at least one read global bit line to discharge during the standby period.