Patent ID: 6509592
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A ferroelectric memory comprising:a well region, which is defined in a semiconductor substrate and extends in a direction; a bit line also extending in the direction; a source line also extending in the direction; first, second and third memory cells, which are formed in this order on the well region and arranged in the direction; a first active region for electrically connecting the first memory cell and the bit line together; a second active region for electrically connecting the first memory cell and the source line together; a third active region for electrically connecting the second memory cell and the bit line together; a fourth active region for electrically connecting the second memory cell and the source line together; a fifth active region for electrically connecting the third memory cell and the bit line together; and a sixth active region for electrically connecting the third memory cell and the source line together, wherein the first and third active regions are the same active region, and wherein the fourth and sixth active regions are the same active region.