Patent ID: 6816411
Filing Date: 2004-11-09
Classification: G11C

Abstract:
A non-volatile semiconductor storage device comprising:a NAND column having a plurality of memory cell transistors connected in series by a current passage; a plurality of word lines connected to gates of the plurality of memory cell transistors in the NAND column; word line drive circuits which drive the plurality of word lines; a bit line connected to one end of the NAND column via a selection gate transistor; a bit line drive circuit which drives the bit line; a source line connected to the other end of the NAND column via a selection gate transistor; a source line drive circuit which drives the source line; and a potential supply circuit which supplies a potential to a semiconductor region in the NAND column in which the plurality of memory cell transistors are formed; wherein in deletion verification which verifies that the contents stored in the plurality of memory cell transistors have been deleted, a read is executed on each of the plurality of word lines, and in the read, the word line drive circuit provides the selected one of the plurality of word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.