Patent ID: 6819971
Filing Date: 2004-11-16
Classification: G06F

Abstract:
An apparatus for setting an overflow flag based on a shift value and input data for one of a plurality of operations executed in a bit manipulation unit (BMU), the apparatus comprising:a first logic circuit, for a first subset of the plurality of operations, setting a first overflow value based on the left shift value and the input data, wherein the first logic circuit comprises: a saturator forming a combination of the number of most significant bits (MSBs) of the input data and the shift value, the most significant bits corresponding to bits at positions for a set of guard bits in the input data and at least one bit of the input data; and an exponent/compare module comparing a number of redundant sign bits based on the combination, the exponent/compare module setting the first overflow value based on the comparison; a second logic circuit, for a second subset of the plurality of operations, setting a second overflow value based on the right shift value and the input data, wherein the second logic circuit comprises: an exponent module generating an exponent for the input data, the exponent module including means for prepending a sign to the exponent to generate a value corresponding to a number of redundant sign bits; a combiner combining the shift amount with the value corresponding to the number of redundant sign bits to form a combined value; a comparator generating the comparison as the difference between the combined value and the most significant bits of the input data wherein the second overflow value is set based on the comparison; and a selector providing either the first or the second overflow value as the overflow flag based on a signal identifying the one of the plurality of operations executed by the BMU.