Patent ID: 8951860
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device having a memory cell region having a memory mat where a plurality of memory cells are formed, a peripheral circuit region, and a scribe region, comprising the steps of: (a) forming a first gate insulation film over a principal face of a semiconductor substrate in said memory cell region; (b) forming a first conductive film and an insulation film in sequence over said first gate insulation film in said memory cell region; (c) forming a plurality of first patterns comprised of a laminated film of a selective gate electrode comprising said first conductive film and said insulation film in a first direction in said memory cell region by processing said insulation film and said first conductive film in sequence; (d) after said step (c), removing said insulation film configuring the upper part of said first pattern located on the outermost side of said memory mat in a second direction perpendicular to said first direction and forming a second pattern comprised of said selective gate electrode on the outermost side of said memory mat in said second direction; (e) after said step (d), forming a second gate insulation film with which said first patterns and said second pattern in said memory cell region are covered over the principal face of said semiconductor substrate; (f) forming a second conductive film over said second gate insulation film; (g) leaving said second conductive film over both the side faces of each of said first patterns and both the side faces of said second pattern by applying anisotropic etching to said second conductive film; and (h) removing a part of said second conductive film and forming memory gate electrodes comprising said second conductive film over one side faces of said first patterns and one side face of said second pattern.