Patent ID: 6208703
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A one stage first-in-first-out synchronizer, comprising:a first write flip-flop which generates a write pointer;a first read flip-flop which generates a read pointer;a second write flip-flop, which receives as input the read pointer;a second read flip-flop, which receives as input the write pointer;a write clock input which provides a write clock signal to the first write flip-flop and the second write flip-flop;a write input;a not full output;first write logic gating means, for generating the not full output from the write pointer and an output of the second write flip-flop;second write logic gating means for generating an input to the first write flip-flop from the write input and the not full output;a read clock input which provides a read clock signal to the first read flip-flop and the second read flip-flop;a read input;a not empty output;first read logic gating means, for generating the not empty output from the read pointer and an output of the second read flip-flop; and,second read logic gating means for generating an input to the first read flip-flop from the read input and the not empty output.