Patent ID: 6888377
Filing Date: 2005-05-03
Classification: H03K

Abstract:
1. A limited switch dynamic logic circuit comprising: a dynamic node; precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal; a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal; static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output; and a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.