Patent ID: 7579868
Filing Date: 2009-08-25
Classification: H03K

Abstract:
1. An integrated circuit device containing a field programmable gate away having an architecture for routing channels comprising: a first plurality of routing channels having a first direction; a second plurality of routing channels having a second direction perpendicular to said first direction, said first plurality of routing channels intersecting said second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in said routing channels; a first number of reprogrammable elements disposed at intersections in a first one of said plurality of matrices, said first number of reprogrammable elements disposed on said intersecting interconnect conductors in a first pattern; a second number of reprogrammable elements disposed at intersections in a second one of said plurality of matrices, said second number of reprogrammable elements greater than said first number of reprogrammable elements, and said second number of reprogrammable elements disposed on said intersecting interconnect conductors in a second pattern distinct from said first pattern; a third number of reprogrammable elements disposed at intersections in a third one of said plurality of matrices, said third number of reprogrammable elements greater than said second number of reprogrammable elements, and said third number of reprogrammable elements disposed on said intersecting interconnect conductors in a third pattern distinct from said first pattern and said second pattern; and a plurality of logic blocks coupled to one another through said first plurality of routing channels and said second plurality of routing channels, wherein each one of said plurality of logic blocks comprises a plurality of clusters, each one of said plurality of logic clusters comprising a plurality of lookup tables each having a plurality of inputs and an output and a D flip-flop having an input and an output.