Patent ID: 8618853
Filing Date: 2013-12-31
Classification: G11C,H03L

Abstract:
1. A device comprising; a plurality of flip-flop circuits each of which includes input, output and clock nodes, the flip-flop circuits being connected such that an output node of a preceding one of the flip-flop circuits is connected to an input node of a succeeding one of the flip-flop circuits, the clock nodes of flip-flop circuits being connected in common to a clock input node; a circuit node supplied with a clock signal; a gate circuit supplied between the circuit node and the clock input node and configured to be controlled in open and close states thereof in response to a first signal derived from the output node of a first one of the flip-flop circuits; and a first circuit configured to receive a second signal from the output node of a second one of the flip-flop circuits, that is prior to the first one of flip-flop circuits, and to perform an operation in response to the second signal.