Patent ID: 8830101
Filing Date: 2014-09-09
Classification: H03M

Abstract:
1. A digital-to-analog converter comprising: an array of at least two digital input streams; a differential output, comprising a positive and a negative output; an input connected to a main clock; an array of inputs having as many inputs as digital input streams, connected to an array of clocks, wherein only one of the said clocks is active (logic high) at any time; an array of differential pairs of PMOS switches having as many pairs as digital input streams, wherein the drains of the first switch from each pair are all connected together and further connected to the said positive output, and the drains of the second switch from each pair are all connected together and further connected to the said negative output; a switch driver being connected to the said digital inputs, to the said main clock, to the said array of clock inputs, and to the gates of the said array of PMOS switches, the switch driver further comprising: