Patent ID: 6046939
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A semiconductor nonvolatile memory, comprising;a plurality of memory cells in which data is programmed electrically together for all memory cells of selected sector according to the data and are arranged in the form of a matrix;a plurality of data latch circuits provided for every bit line;a means for transforming sector units of page program data to the data latch circuits;an error correcting means for reading the page program data in units of the memory cells of the selected sector and correcting error bits when there are less than a predetermined number of error bits in the page read data;a means for detecting whether or not there are unprogrammed memory cells in every programming operation, in which the data is programmed according to the page program data by repeatedly performing a plurality of programming operations via a verify/reading operation;a means for counting the number of the unprogrammed memory cells when there are the unprogrammed memory cells after a predetermined number of programming operations are repeatedly carried out; anda means for ending the data programming while leaving the unprogrammed memory cells when the number of the unprogrammed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.