Patent ID: 8675679
Filing Date: 2014-03-18
Classification: G06F

Abstract:
1. A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor, cause the processor to: send an address from a sending device to a receiving device via an address channel of a bus, the bus including the address channel, a write channel, and a read channel; receive data from the receiving device via the read channel of the bus; and concurrently send a portion of a payload from the sending device to the receiving device via the write channel of the bus and another portion of the payload from the sending a device to the receiving device via the address channel of the bus, wherein, when sending multiple sequential portions of the payload via the bus concurrently, data ordering preference is given to the write channel over the address channel by sending a first sequential portion of the multiple sequential portions via the write channel of the bus and sending a subsequent sequential portion of the multiple sequential portions via the address channel of the bus.