Patent ID: 9154332
Filing Date: 2015-10-06
Classification: H04L

Abstract:
1. A computing apparatus, said computing apparatus comprising: a memory device; a transmitter; a receiver; and a processing system configured to control the transmitter and receiver, wherein the processing system of the computing apparatus is configured to: be interconnected in a network to one or more connected computing apparatuses via conduits providing bidirectional links for independent streams of symbols in both directions, transmissions toward all links being executed synchronously at a locally generated symbol period and one specified symbol being a cell start symbol which identifies the beginning of a cell comprising a contiguous sequence of a predefined number of symbols; transmit additionally a locally determined number of idle symbols before the start of a subsequent cell, the number of said idle symbols having an allowed range for adjustment purposes between predefined lower and upper limits; transmit said cell start symbol simultaneously to all connected computing apparatuses; apply the same number of said idle symbols in said transmissions toward each of said connected computing apparatuses; and measure a timing offset for a received cell start symbol relative to its own transmitted cell start symbol in units of its own symbol period or any other units, including the positive or negative direction of said measured timing offset, said measured timing offset being used for determining the number of the idle symbols to be applied with which in collaboration with the connected computing apparatuses in said network constraining the cell start symbols of the connected computing apparatuses into a predefined timing window establishing an alignment of the cell transmissions within the network, wherein, for the purpose of said measured timing offset, said cell start symbol can be substituted by any other defined symbol position within the cell.