Patent ID: 6088822
Filing Date: 2000-07-11
Classification: G01R

Abstract:
An integrated circuit, comprising:a) a serial data input pin and a serial data output pin;b) on-chip functional circuitry and test logic;c) a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal;d) a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation;wherein in the second mode the data adaptor is supplied with parallel data and control signals from said on-chip functional circuitry and includes first conversion circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits and data bits for communicating off chip via the test access port controller under the control of said incoming clock signal, wherein the flow control bits are generated responsive to receipt of said parallel data and control signals from said on-chip functional circuitry, said data adaptor receiving from off chip via the serial data input pin a sequence of serial bits including flow control bits and data bits and including second conversion circuitry for converting said sequence of serial bits into parallel data and control signals for said on-chip functional circuitry, the control signals being generated responsive to receipt of said flow control bits.