Patent ID: 6418490
Filing Date: 2002-07-09
Classification: H01L,H05K

Abstract:
An information handling system, comprising:a substrate having first and second sides, the first side of the substrate including first and second system buses extending in a â€œYâ€  direction and an inter-system bus extending in an â€œXâ€  direction substantially perpendicular to said â€œYâ€  direction; a first chip carrier having a multiplicity of pairs of system connection points, each pair of system connection points comprising electrically interconnected first and second system connection points, the set of first system connection points being arranged in a first pattern adjacent a first edge of the first chip carrier, and the set of second system connection points being arranged in a second pattern adjacent a second edge of the first chip carrier, such that the second pattern is the virtual mirror of the first pattern, the set of first system connection points being coupled to the first system bus; the first chip carrier also having a multiplicity of pairs of inter-system connection points, each pair of inter-system connection points comprising electrically interconnected first and second inter-system connection points, the set of first inter-system connection points being arranged in a third pattern adjacent a third edge of the first chip carrier, and the set of second inter-system connection points being arranged in a fourth pattern adjacent a fourth edge of the first chip carrier, the set of first inter-system connection points being coupled to the inter-system bus; a second chip carrier having a multiplicity of system connection points adjacent a first edge of the second chip carrier and being coupled to the second system bus, and having a multiplicity of inter-system connection points adjacent a second edge of the second chip carrier and being coupled to the inter-system bus; a third chip carrier having a multiplicity of system connection points adjacent a first edge of the third chip carrier and being coupled to the first system bus adjacent the first edge of the first chip carrier; and a fourth chip carrier having a multiplicity of system connection points adjacent a first edge of the fourth chip carrier and being coupled to the second system bus adjacent the first edge of the second chip carrier; wherein the third chip carrier processes information on the first system bus, the fourth chip carrier processes information on the second system bus, and the first and second chip carriers communicate information between the first system bus and the second system bus.