Patent ID: 8037119
Filing Date: 2011-10-11
Classification: G06F

Abstract:
1. A multipurpose functional unit for a processor, the functional unit comprising: an input section configured to receive an opcode designating one of a plurality of supported operations to be performed and one or more operands on which the designated operation is to be performed, the input section being further configured to generate a plurality of control and data signals in response to the received opcode and operands; a multiplication pipeline including a multiplier circuit having a height and a width, at least one of the height or the width being less than a double-precision mantissa size, the multiplication pipeline being coupled to receive a first subset of the control and data signals from the input section, the multiplication pipeline being configured to select a plurality of factors based on the received control and data signals and to operate the multiplier circuit to compute one or more products from the plurality of factors, the factors including M wherein in the event the opcode designates an operation other than a double-precision multiplication (DMUL) operation, M wherein in the event that the opcode designates the DMUL operation, for each of a plurality of iterations within the functional unit: a first portion and a second portion of a mantissa of a first input operand are selected as inputs M an addition pipeline coupled to receive one or more products from the multiplication pipeline, the addition pipeline being configured to perform an addition operation using the one or more products to produce an operation result, wherein in the event the opcode designates an operation other than a DMUL operation, the operation result comprises M wherein in the event the opcode designates the DMUL operation, the addition pipeline adds the products M wherein the plurality of supported operations includes the DMUL operation that is executed using multiple iterations through at least a portion of the multiplication pipeline and at least a portion of the addition pipeline, a unary function approximation (UFA) operation, and a planar interpolation (PI) operation wherein: the UFA operation for an input operand x and a unary function ƒ(x) to be approximated includes computation of a quadratic polynomial of the form: wherein x the PI operation for input coordinates (x, y) includes computation of a planar function U(x, y) of the form: wherein A, B, and C are interpolation parameters and A is an offset term that depends at least in part on the interpolation parameter C.