Patent ID: 8514640
Filing Date: 2013-08-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells connected to plural word lines and plural bit lines, the plural bit lines including a first bit line, a second bit line, a third bit line, and a fourth bit line, the first bit line to the fourth bit line being adjacent to each other, the second bit line being arranged between the first bit line and the third bit line, the third bit line being arranged between the second bit line and the fourth bit line; sense amplifiers connected to the bit lines, the sense amplifiers including a first sense amplifier and a second sense amplifier; a first transistor arranged between the first bit line and the first sense amplifier; a second transistor arranged between the second bit line and the second sense amplifier; a third transistor arranged between the third bit line and the second sense amplifier; and a fourth transistor arranged between the fourth bit line and the first sense amplifier, wherein the first sense amplifier is connectable to the first bit line via the first transistor or to the fourth bit line via the fourth transistor, and the second sense amplifier is connectable to the second bit line via the second transistor or to the third bit line via the third transistor.