Patent ID: 6232217
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from said fluorinated silica glass dielectric layer, comprising the steps of:providing a semiconductor structure having a semiconductor device structure formed therein;forming a metal line over said semiconductor structure; said metal line being electrically connected with said semiconductor device structure;forming an insulating layer over said semiconductor structure, covering said metal line;forming a fluorinated silica glass dielectric layer over said insulating layer;planarizing said fluorinated silica glass dielectric layer to form a planarized fluorinated silica glass dielectric layer;patterning said planarized fluorinated silica glass dielectric layer and said insulating layer to form a via opening to said metal line and exposing portions of said patterned fluorinated silica glass dielectric layer within said via opening;treating said via opening with a plasma selected from the group consisting of an N-containing plasma, an H-containing plasma, and a combination thereof, wherein said exposed portions of said patterned fluorinated silica glass dielectric layer within said via opening are converted to a barrier layer that prevents said outgassing from said patterned fluorinated silica glass dielectric layer; the plasma treatment being conducted at:a temperature from about 0 to 520.degree. C.;a pressure from about 0.001 to 10 Torr;a power from about 20 to 2000 W; andfor from about 3 to 300 seconds; andforming a metal interconnect within said barrier lined via opening.