Patent ID: 6757875
Filing Date: 2004-06-29
Classification: G03F,G05B

Abstract:
A method of evaluating a deviation between patterns successively formed on a wafer to fabricate a semiconductor device, comprising the steps of:storing CAD data used to form the successively formed patterns of the semiconductor device; obtaining an image with a microscope of an already formed one of the patterns on the semiconductor wafer; displaying the image obtained with the microscope on a monitor; reading first CAD data used to form the already formed pattern of the semiconductor device; displaying the first CAD data with the displayed image of the already formed pattern as a first overlapped image on the monitor to enable evaluation of a deviation in formation of the already formed pattern; reading second CAD data to be used to form a successive pattern of the semiconductor device that will be connected to the already formed pattern; and displaying the second CAD data with the displayed image of the already formed pattern and the first CAD data as a second overlapped image on the monitor to enable evaluation of a deviation of the successively formed pattern from the already formed pattern.