Patent ID: 8824271
Filing Date: 2014-09-02
Classification: H04L

Abstract:
1. An ODFM receiver, comprising: an FFT/IFFT operation core; and a scheduler, the scheduler managing input/output timings of FFT/IFFT operations and control signals for simultaneously sharing the FFT/IFFT operating core, wherein the FFF/IFFF operating core simultaneously supports a decimation-in-time (DIT) FFT/IFFT operation and a decimation-in-frequency (DIF) FFT/IFFT operation; wherein interface specifications in the FFT/IFFT operating core interfacing with the scheduler are used for sending and receiving signals via Rx Input (RI), Sharing Input (SI), Sharing Output (SO), and Extra Output (EO) ports; wherein for a channel estimation to simultaneously operate three FFT/IFFT operations, the single FFT/IFFT operation core is shared in an OFDM symbol for processing DIT-FFF, DIF-IFFT, DIT-FFT operations in turn, and an operating clock over 4 times of an FFT input data rate is used.