Patent ID: 7238567
Filing Date: 2007-07-03
Classification: H01L

Abstract:
1. A method for forming a CMOS, comprising: providing a substrate having a PMOS region and an NMOS region; forming an epitaxial SiGe layer outwardly from the substrate in the PMOS region and the NMOS region; forming an epitaxial Si layer outwardly from the SiGe layer in the PMOS region and the NMOS region; removing the epitaxial Si layer from the PMOS region, the epitaxial Si layer remaining in the NMOS region; depositing a high K gate dielectric outwardly from the SiGe layer in the PMOS region; depositing a gate dielectric outwardly from the epitaxial Si layer in the NMOS region; forming gate structures in the PMOS region and the NMOS region; and forming metal source and a metal drains in the PMOS region.