Patent ID: 6888747
Filing Date: 2005-05-03
Classification: G11C,H01L

Abstract:
1. A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising: applying a first fraction of a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line; applying the first fraction of the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line; and applying a second fraction of the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell through a diode and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line, wherein the other bit lines are coupled to the second source/drain regions of such non-selected memory cells through diodes.