Patent ID: 6405150
Filing Date: 2002-06-11
Classification: G01R,G11C

Abstract:
A program storage device, readable by a pattern generator, which stores a series of variable length instructions that direct said pattern generator to test an integrated circuit chip through a test port on said chip;each variable length instruction including a respective set of at least one serial bit stream for use in said test, and a code which indicates the number of bit streams in said set; each serial bit stream in each respective set consisting of a selectable number of bits which start on a word boundary and range in increments of one bit from a predetermined minimum to a predetermined maximum; a respective series of unused bits, that start immediately after each serial bit stream which is not an integer number of bits, and which end on a word boundary; and, each respective set, which has multiple bit streams, being stored in said storage device such that corresponding words of said multiple bit streams are interleaved.