Patent ID: 7477072
Filing Date: 2009-01-13
Classification: H03K

Abstract:
1. A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic, said circuit comprising: a block of memory cells comprising a look-up table of a configurable logic block; a reset signal comprising a plurality of reset bits coupled to a first plurality of nodes of said block of memory cells, wherein each reset bit resets a value stored in a corresponding memory cell inside said look-up table by coupling a voltage to a data input of said corresponding memory cell storing said value, and a set signal comprising a plurality of set bits coupled to a second plurality of nodes of said block of memory cells, wherein each set bit sets a corresponding memory cell inside said look-up table, said reset bits and said set bits enabling selectively resetting and setting initial values for memory cells inside said look-up table during partial reconfiguration of said device.