Patent ID: 8335954
Filing Date: 2012-12-18
Classification: G01R

Abstract:
1. A method that accepts a compressed scan pattern stored in an ATE (automatic test equipment) for generating a decompressed scan pattern in a decompressor for testing a scan-based integrated circuit, said decompressor accepting the compressed scan patterns via compressed scan inputs for generating the decompressed scan patterns, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the decompressor, the decompressor comprising one or more programmable shift registers connected to said compressed scan inputs and a combinational logic network connected to said compressed scan inputs and said shift register outputs for connecting the outputs of said combinational logic network to selected scan inputs of all said scan chains, said method comprising: a) placing said decompressor between said ATE and said scan-based integrated circuit; b) transmitting said compressed scan pattern stored in said ATE to said decompressor for generating said decompressed scan pattern to test manufacturing faults in said scan-based integrated circuit; and c) comparing a test response of said scan-based integrated circuit with an expected test response.