Patent ID: 6534840
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A semiconductor device comprising:a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; an upper insulating film formed on the gate electrode; a trench isolation film self-aligned with the gate electrode, the upper surface of the isolation film being located at a level higher than the upper surface of the gate electrode, the lower surface of the isolation film being located at a level lower than the upper surface of the substrate at least on a cross section of the device taken in a gate length direction; source/drain diffused regions defined in respective regions of the substrate beside the gate electrode; and source/drain contacts formed between the sidewall insulating film and the isolation film and self-aligned with the gate electrode to make electrical contact with the source/drain diffused regions; and a sidewall insulating film interposed between the source/drain contacts and a stack of the gate electrode and the upper insulating film, wherein the size of the gate electrode as measured in the gate width direction is larger than that of the source/drain contacts, and the gate electrode protrudes laterally on both sides of the source/drain contacts in the gate width direction.