Patent ID: 9208867
Filing Date: 2015-12-08
Classification: G11C,H01L

Abstract:
1. An electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts disposed over every other of the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines extending in the third direction and being coupled to the source line contacts; contacts disposed over the active regions over which the source line contacts are not disposed; variable resistance elements disposed over and coupled to the contacts, respectively; bit line contacts disposed over and coupled to the variable resistance elements, respectively; and bit lines extending in a fourth direction intersecting the first to third directions and be coupled to the bit line contacts.