Patent ID: 6127222
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method for providing at least one flash memory cell on a semiconductor substrate, the at least one flash memory cell including a gate stack, a source and a drain having dopants of a first conductivity type, the method comprising the sequential steps of:(a) providing a floating gate for the gate stack, the floating gate having a thickness which allows a dopant to be implanted through the floating gate in the region of the semiconductor;(b) providing a side implant, the step of providing a side implant including the steps of(b1) providing a mask having an aperture therein, the mask for implanting a region of the semiconductor under the gate stack, the aperture located above the region, and(b2) implanting a dopant in a direction substantially perpendicular to a surface of the semiconductor device, the dopant traveling through the aperture and through the floating gate, the dopant having a second conductivity type that is different from the first conductivity type if the side implant is a drain side implant; and(c) providing an implant in at least one of the drain and the source of the at least one flash memory cell.