Patent ID: 6479888
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor chip having a first main surface and a second main surface opposite to said first main surface, said semiconductor chip having first and second electrodes formed on said first main surface and a third electrode formed on said second main surface; a first lead having an inner lead and an outer lead which is continuous with said inner lead, said inner lead of said first lead having a first portion which is disposed on said first main surface of said semiconductor chip and being electrically connected to said first electrode via a first bump electrode; a second lead having an inner lead and outer leads which are continuous with said inner lead, said inner lead of said second lead having a first portion which is disposed on said first main surface of said semiconductor chip and being electrically connected to said second electrode via second bump electrodes, said outer leads extending from said first portion of said second lead to form a branch connection; a third lead of a plate shape being disposed on said second main surface of said semiconductor chip and being electrically connected to said third electrode of said semiconductor chip by a conductive adhesive, a periphery of said third lead being terminated at the vicinity of a periphery of said second main surface of said semiconductor chip; and a resin member sealing said semiconductor chip, said first and second bump electrodes, and said inner leads of said first and second leads, said outer leads of said first and second leads extending outwardly from said resin member, a rear surface of said third lead being exposed from said resin member; wherein said outer leads of said first and second leads extend in a first direction, wherein said first portion of said second lead has a tabular shape portion in a plan view and a width of said tabular shape portion in a second direction substantially perpendicular to said first direction is greater than a total width of all of said outer leads of said second lead in said second direction, wherein said outer leads of said first and second leads are bended such that tips of said outer leads of said first and second leads are positioned at the substantially same level as said rear surface of said third lead in a thickness direction of said semiconductor chip and at the vicinity of said periphery of said third lead.