Patent ID: 6662331
Filing Date: 2003-12-09
Classification: H03M

Abstract:
A turbo decoding circuit having a first and second operational mode of operation, comprising:(a) a first functional loop for use in the first operational mode, the first loop including: (1) a write interleaver having an input and an output; (2) a dual port extrinsic memory having an input and an output, the input being coupled to the write interleaver output; (3) a read interleaver having an input and an output, the input being coupled to the output of the dual port extrinsic memory; (4) a buffer circuit having an input and an output, the input of the buffer being coupled to the output of the read interleaver; and (5) a log-MAP decoder having an input and an output, the input being coupled to the output of the buffer and the output of the log-MAP decoder being coupled to the write interleaver; and (b) a second functional loop for use in the second operational mode, the fir second loop including: (1) the dual port extrinsic memory; (2) the buffer circuit, the input of the buffer circuit being coupled to the output of the dual port extrinsic memory; and (3) the log-MAP decoder, the input of the log-MAP decoder being coupled to the output of the buffer circuit, and the output of the log-MAP decoder being coupled to the input to the dual port extrinsic memory.