Patent ID: 6031256
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A wide voltage operation regime double heterojunction bipolar transistor comprising:a substrate comprised of GaAs material;a buffer layer comprised of GaAs material on said substrate;a collector layer comprised of In.sub.0.49 Ga.sub.0.51 P material on said buffer layer;a base layer comprised of GaAs material on said collector layer;an emitter layer comprised of GaAs material on said base layer;a five-period superlatticed confinement layer on said emitter layer, said confinement layer comprising a barrier layer formed from undoped In.sub.0.49 Ga.sub.0.51 P material and a quantum well layer formed from GaAs material; andan ohmic contact layer comprised of GaAs material on said five-period superlatticed confinement layer.