Patent ID: 6260126
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A method for enabling overlapped performance of data processing actions during data transfers between a memory system and a host processor, said memory system including a memory processor which enables said data transfers and a state queue which holds a plurality of states, each state comprising a self contained procedure for determining a readiness to execute of an associated task, said method comprising:determining an amount of available time during a data transfer;causing said memory processor to execute a first state from said state queue during said data transfer if said available time exceeds or is equal to an estimated execution time of said first state;if a task associated with said first state is found to be ready to execute, listing said task on a task work queue for execution subsequent to said data transfer.after execution of said first state, determining remaining time from said available time; andcausing said memory processor to execute a second state from said state queue during said data transfer if said remaining time exceeds or is equal to an estimated execution time of said second state,wherein said remaining time is determined by subtracting actual execution time for said first task from said available time.