Patent ID: 8222916
Filing Date: 2012-07-17
Classification: G01R

Abstract:
1. A Single Event Transient (SET) measurement circuit comprising: a first SR latch coupled to a set input and a reset input; a second SR latch coupled to the set input and the reset input; a dual-input inverter having a first input coupled to an output of the first SR latch, a second input coupled to an output of the second SR latch, and an output; and a target having an input coupled to the output of the dual-input inverter, and an output; wherein the dual-input inverter comprises: a first P-channel transistor having a gate coupled to the first input; a second P-channel transistor having a gate coupled to the second input; a first N-channel transistor having a gate coupled to the first input; and a second N-channel transistor having a gate coupled to the second input.