Patent ID: 6615377
Filing Date: 2003-09-02
Classification: G01R

Abstract:
An integrated circuit having a normal-operation mode of operation, a test-drive mode of operation, and a test-readout mode of operation, said integrated circuit comprising: drive-signal means for receiving drive-signal vectors;captured-signal means for providing captured-signal vectors during said normal-operation mode and during said test-drive mode, said captured-signal vectors being functionally related to said drive-signal vectors during said test-drive mode; test-port means for interfacing with a circuit tester during said test-readout mode; and queue means for storing contents, said contents including selected ones of said captured-signal vectors, said queue means having plural queue locations for storing respective ones of said captured-signal vectors, said queue means being coupled to said captured-signal means for receiving said captured-signal vectors during said normal-operation mode and said test-drive mode, said queue means being coupled to said test-port means for providing at least some of said contents thereto via said test-port means during said test-readout mode.