Patent ID: 7263572
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A bus bridge that is connected between a high-speed bus line and a low-speed bus line, wherein a high-speed device is connected to the high-speed bus line and a low-speed device is connected to the low-speed bus line, comprising: a buffer unit that temporarily stores data that is read from the low-speed device via the low-speed bus line; a register that stores a value of a valid flag that indicates that valid data is stored in the buffer unit; and a control logic unit that performs a control to successively transfer the data from the low-speed device to the high-speed device a predetermined number times, wherein the control includes releasing the high-speed bus line before completion of reading of the data from the low-speed device, storing the data read from the low-speed device in the buffer unit, setting a value in the register to indicate that valid data is stored in the buffer unit, confirming, at a following access in a series of accesses to the high-speed device, that a value stored in the register indicates that valid data is stored in the buffer unit, outputting the data from the buffer unit to the high-speed device and outputting dummy data to the high-speed device at a first access in the series of accesses to the high-speed device.