Patent ID: 6065106
Filing Date: 2000-05-16
Classification: G01R,G06F

Abstract:
A method for debugging a processor within a data processing system, the processor having a multi-word instruction register, comprising the steps of:executing system code from the multi-word instruction register in an instruction execution pipeline in a normal operational manner;halting the normal operation of the processor by saying at least a first partially executed instruction to an external test system;inhibiting fetching of instructions into the multi-word instruction register;transferring a first sequence of debug code instructions into the multi-word instruction register from the external test system;executing the sequence of debug code instructions in the processor's multi-word instruction register to perform a debug operation on the processor; andresuming execution of the system code in the multi-word instruction register by restoring at least the first partially executed instruction to the multi-word instruction register from the external test system, enabling fetching of instructions and starting normal operation of the processor.