Patent ID: 6212631
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A computer system comprising:at least one microprocessor having an L2 cache, the L2 cache further having error checking and correcting capability (ECC);at least one memory, said at least one memory including either all ECC capable memory or any combination of ECC capable and non-ECC capable memory; andbasic input output system (BIOS) firmware including an L2 cache support feature, the L2 cache support feature having three user-selectable options, the three options including i) L2 cache ECC ON for enabling L2 cache ECC, ii) L2 cache ECC OFF for not enabling L2 cache ECC, and iii) L2 cache ECC AUTO for automatically enabling or not enabling L2 cache ECC in response to a detection of the presence of a) all ECC capable memory or b) any combination of ECC and non-ECC capable memory, respectively.