Patent ID: 8084325
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a recess pattern in a substrate; forming a gate dielectric layer over the recess pattern; forming a gate electrode over the gate dielectric layer inside the recess pattern, wherein the gate electrode does not extend above a surface of the substrate; forming a gate hard mask pattern over the gate electrode and upper corners of the recess pattern; forming a barrier layer over the gate hard mask pattern; forming an interlayer dielectric layer over the barrier layer; forming a contact hole by performing a self aligned contact (SAC) etching by using an etch selectivity between the interlayer dielectric layer and the barrier layer, wherein the substrate between the gate hard mask pattern and an adjacent gate hard mask pattern is recessed to a predetermined depth; and forming a plug over the substrate between the gate hard mask pattern and the adjacent gate hard mask pattern by filling the contact hole.