Patent ID: 9065653
Filing Date: 2015-06-23
Classification: G01R,H04L

Abstract:
1. An internal jitter tolerance tester with an internal jitter generator, the jitter tolerance tester comprising: a loop filter with a predetermined gain and a predetermined delay; an internal accumulated jitter generator to generate an accumulated jitter and output the generated accumulated jitter to a gain multiplier; the gain multiplier to be connected to an output of the loop filter and be connected to an output of the internal accumulated jitter generator; and a phase rotator controller to be connected to an output of the gain multiplier and to generate a jitter-equipped clock signal, wherein the internal accumulated jitter generator comprises, a pseudorandom binary sequence (PRBS) generator to generate 1 and −1 randomly; a subsequent accumulator to be connected to an output of the pseudorandom binary sequence generator and accumulate a random signal; a lowpass filter to be connected between the pseudorandom binary sequence generator or be connected to an output of the subsequent accumulator, the lowpass filter eliminating a high frequency spur and a quantization noise; and a gain controller to be connected to an output of the subsequent accumulator or be connected to an output of the lowpass filter, the gain controller controlling an amount of the accumulated jitter.