Patent ID: 7994037
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A method of forming a gate dielectric material, the method comprising: forming a first dielectric base material on a first active region, said first active region comprising a first portion having a first well doping of a first conductivity type and a second portion having a second well doping of a second conductivity type; forming a second dielectric base material on a second active region, said second active region comprising a first portion having said first well doping and a second portion having said second well doping; forming a mask that exposes said second portions of said first and second active regions and covers said first portions of said first and second active regions; selectively removing only an upper portion of said exposed portion of said first dielectric base material and completely removing said exposed portion of said second dielectric base material using said mask, wherein a portion of said first dielectric material remains above said second portion of said first active region; removing said mask; and forming a further dielectric material above said first and second active regions so as to obtain a first gate dielectric material comprised of said first dielectric base material and said further dielectric material on said first portion of said first active region, a second gate dielectric material comprised of said remaining portion of said first dielectric base material and said further dielectric material on said second portion of said first active region, a third gate dielectric material comprised of said second dielectric base material and said further dielectric material on said first portion of said second active region, and a fourth gate dielectric material comprised of said further dielectric material on said second portion of said second active region, wherein a thickness of each of said second and third gate dielectric materials are less than a thickness of said first gate dielectric material and a thickness of said fourth gate dielectric material is less than said thicknesses of each of said first, second and third gate dielectric materials.