Patent ID: 6362502
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A dynamic random access memory (DRAM) cell circuit, comprising:a substrate having a surface; a voltage terminal; a word line; a bit line running transversely to said word line; and a plurality of memory cells each containing: a memory transistor having a channel region, a control gate electrode, a floating gate electrode, a first source/drain region, and a second source drain region; a transfer transistor having a gate electrode, a first source/drain region and a second source/drain region, said word line connected to said gate electrode of said transfer transistor; a first dielectric layer disposed between and isolating said floating gate electrode of said memory transistor from said channel region of said memory transistor, and said floating gate electrode connected to said first source/drain region of said transfer transistor; a second dielectric layer disposed between and isolating said control gate electrode of said memory transistor from said floating gate electrode of said memory transistor, and said control gate electrode connected to said word line; an insulating layer; said first source/drain region of said memory transistor connected to said bit line; and said second source/drain region of said memory transistor and said second source/drain region of said transfer transistor connected to said voltage terminal; said first source/drain region of said memory transistor, said channel region of said memory transistor and said second source/drain region of said memory transistor adjoining said surface of said substrate and are disposed next to one another in said substrate; said insulating layer being disposed on said substrate and having a depression formed therein defined by sidewalls and a bottom reaching down to said channel region of said memory transistor; said first source/drain region of said transfer transistor being disposed on said first dielectric layer at said bottom of said depression; and said second source/drain region of said transfer transistor being disposed on said insulating layer.