Patent ID: 8069427
Filing Date: 2011-11-29
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit comprising: performing, via a processor, a circuit simulation of a cell with changing a peripheral parameter that specifies a relationship between a layout pattern of said cell and a peripheral pattern around said cell, said peripheral parameter affecting electrical characteristics of said cell; generating, via the processor, a delay function expressing a delay value of said cell as a function of said peripheral parameter, based on a result of said circuit simulation; generating, via the processor, a layout data indicating a layout of said semiconductor integrated circuit, based on a cell-based design technique; referring, via the processor, to said generated layout data to extract said peripheral parameter associated with a target cell included in said semiconductor integrated circuit; and calculating, via the processor, a delay value of said target cell by using said extracted peripheral parameter and said delay function, wherein said cell includes a first transistor placed near a boundary of said cell, wherein a second transistor is supposed to be placed adjacent to said first transistor across said boundary, and said peripheral parameter specifies a relative position of a layout pattern of said second transistor with respect to a layout pattern of said first transistor.