Patent ID: 6102964
Filing Date: 2000-08-15
Classification: G01R,G06F,G06Q,Y10S

Abstract:
In a compiler for fitting electronic designs on target hardware devices, which devices have multiple levels of hierarchical containment together defining placement of logic from the electronic designs onto the target hardware devices, a method of fitting a changed electronic design which is changed from an original electronic design that was previously compiled, the changed electronic design including an unchanged portion which is unchanged from the original electronic design and a changed portion which is changed from the original electronic design, the method comprising:(a) providing the unchanged portion of the changed electronic design on an unchanged region of a target hardware device on which the unchanged portion of the original electronic design was placed during the previous compilation;(b) specifying one or more levels of hierarchical containment to relax; and(c) attempting to place the changed electronic design on the target hardware device while allowing the unchanged portion of the changed electronic design to change its placement within the unchanged region of the target hardware device but only insofar as permitted within the specified one or more hierarchical containment levels.