Patent ID: 6125465
Filing Date: 2000-09-26
Classification: G01R

Abstract:
A method for LBIST testing a chip, said chip comprises a plurality of functional units each functional unit includes at least a logic section, and a control system including a plurality of clock control macros each clock control macro is for each functional unit, the control system is for supplying system clocks and control signals to the logic sections of the functional units, the method comprising the steps of:independently enabling, by the control system, each of said clock control macros for each of said functional units to be tested so that said each functional unit can be tested independently from remain functional units and for generating system clocks for said each functional unit to be tested;selectively testing logic sections of functional units that are generated with the system clocks for intermittent faults to characterize any chip problems;if intermittent faults are found, isolating the tested logic sections of the functional units that generate the found intermittent faults, then, disabling the logic sections that are found with the intermittent faults for preventing from generating any intermittent LBIST signature, said disabling is performed by disabling the generation of system clocks to said functional units that are isolated in the isolating step in order to remove the faulty functional units from further testing during the LBIST testing.