Patent ID: 7681043
Filing Date: 2010-03-16
Classification: G11C

Abstract:
1. A set top box, comprising: a chip that comprises a chip interface, a processor, and a memory array, wherein the processor is coupled to the memory array and the chip interface via one or more buses, wherein the memory array comprises non-volatile memory, wherein the non-volatile memory comprises a first bank of mode control bits, a second bank of mode control bits, device identification bits, first encryption key bits, second encryption key bits, and memory management bits, wherein the first bank of mode control bits comprises an encryption engine mode control bit that selects between data encryption standard (DES) and triple data encryption standard (3DES), a data output mode control bit that enables or disables a data output interface of the set top box, a test port mode control bit that enables or disables access to test ports of the set top box, and reserved bits that enable or disable features or functions of the set top box, wherein the second bank of mode control bits comprises first bits, a first lock bit that locks the first bits, second bits, and a second lock bit that locks the second bits, wherein the memory management bits comprises programming bits that indicate programming status and cyclic redundancy check (CRC) bits, wherein, during a programming cycle, a first bit of the memory management bits is programmed and the first bank of mode control bits are programmed, wherein a second bit of the memory management bits is programmed to complete the programming cycle such that a portion of the non-volatile memory bits covered by the CRC bits is not further modified, wherein the portion of the non-volatile memory bits covered by the CRC bits comprises the device identification bits, the first encryption key bits, the second encryption key bits, and the first bank of mode bits, and wherein the CRC bits do not cover the second bank of mode control bits and the memory management bits.