Patent ID: 9098486
Filing Date: 2015-08-04
Classification: G01R,G06F,G11C

Abstract:
1. An integrated circuit device comprising: a first memory that is operable to use a first normal mode clock having a first clock domain characteristic for a normal mode; a second memory that is operable to use a second normal mode clock having a second clock domain characteristic for the normal mode, wherein the first clock domain characteristic differs from the second clock domain characteristic; a first switching circuit that is arranged to receive the first normal mode clock and an initial test clock and to selectively output to the first memory either the first normal mode clock when the normal mode is selected or the initial test clock as a first test clock when a testing mode is selected; a second switching circuit that is arranged to receive the second normal mode clock and the initial test clock and to selectively output to the second memory either the second normal mode clock when the normal mode is selected or the initial test clock as a second test clock when the testing mode is selected; a built-in-self-test (BIST) switching circuit that is arranged to receive and output the first test clock when the first memory is being tested and to receive and output the second test clock when the second memory is being tested; and a built-in-self-test (BIST) circuit that is arranged to receive and use the first test clock for testing the first memory and to receive and use the second test clock for testing the second memory.