Patent ID: 7569466
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing a semiconductor substrate comprising at least one nFET device region and at least one pFET device region, which are separated by an isolation region; forming a first metal gate stack within said at least one nFET device region, said first metal gate stack having nFET behavior and comprising a rare earth metal-containing layer and a first metal layer located on said rare-earth metal-containing layer, wherein said first metal layer is the sole metal gate layer within the nFET device region and said rare-earth metal-containing layer having outer vertical edges that extend beyond outer vertical edges of said first metal layer; and forming a second metal gate stack within said at least one pFET device region, said second metal gate stack having pFET behavior and comprising a second metal layer that may be the same or different from the first metal layer, wherein said first metal layer and said second metal layer do not include a Si-containing gate electrode thereon and said second metal layer is the sole metal gate layer within the pFET device region.