Patent ID: 8502307
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semiconductor carrier including a first side and a second side opposite the first side; an FET in a first area of the semiconductor carrier, a drain of the FET being electrically coupled to a drain contact area at the first side and a source of the FET being electrically coupled to a source contact area at the second side; first circuit elements in a second area of the semiconductor carrier, the second area being electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending from the first side to the second side; an interconnection level electrically interconnecting the first circuit elements at the second side, the interconnection level being electrically insulated from the source contact area in the entire second area via an insulating layer; and a conductive pathway extending through the semiconductor carrier from the first side to the second side, the conductive pathway being electrically insulated from the semiconductor carrier surrounding the conductive pathway; and wherein at least one of the first circuit elements is electrically coupled to a contact area at the first side via a trench contact.