Patent ID: 6306708
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method for fabricating an electrically erasable programmable read only memory, comprising:providing a substrate having at least a strip of a active area formed thereon, and two isolation structures on the two sides of the active area formed therein;forming an oxide layer on the substrate;forming a trench in the oxide layer to expose the substrate area designated for a source, the trench being perpendicular to the active area;filling the trench with a polysilicon layer to form a polysilicon pillar;implanting ions into the polysilicon pillar and the substrate area designated for the source;performing an annealing process to drive the ions into the substrate area designated for the source;removing the oxide layer;forming a first dielectric layer to cover the polysilicon pillar and the substrate;depositing a first doped polysilicon layer on the substrate;patterning the first doped polysilicon layer to form two floating gates in parallel with the polysilicon pillar, the two floating gates covering the sidewall and the top portion of the polysilicon pillar, respectively;removing the exposed first dielectric layer;forming a second dielectric layer on the substrate;forming a conformal second dielectric layer covering the two floating gates and the substrate;forming a second doped polysilicon layer on the substrate and patterning the second doped polysilicon layer into two control gates in parallel with the polysilicon pillar, the two control gates covering the sidewall and the top portion of the two floating gates; andimplanting ions into the substrate area designated for two drains using the control gates as a mask.