Patent ID: 6333935
Filing Date: 2001-12-25
Classification: G06F,H04J

Abstract:
Apparatus for concurrently processing a plurality of time-division multiplexed data streams merged into a single data stream containing a plurality of data words and characterized by state vectors, said apparatus comprising:(a) read-write memory means having a plurality of addressable memory locations for storing said state vectors;(b) a pipeline for:(i) during an initial clock cycle:(1) receiving an input data word from one of said data streams;(2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream;(3) receiving said predefined memory location address of said input state vector;(ii) during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector;(iii) during a final clock cycle:(1) transferring said output data word to an outgoing data stream;(2) transferring said output state vector to said predefined memory location address in said memory means;(c) control means coupled to said memory means and to said pipeline for synchronizing operation thereof;(d) a null cycle generator coupled to said pipeline and to said control means, said null cycle generator for inserting null cycles into said concurrently processed data streams at regular time intervals and for outputting a NULL signal to said control means during each of said null cycles; and,(e) multiplexer means coupled between said control means and said read-write memory means for multiplexing access to said read-write memory means between:(i) said control means and said pipeline; and,(ii) an alternate control means;wherein said control means inhibits read access to said read-write memory means by said control means and by said pipeline during output of said NULL signal and inhibits write access to said read-write memory means by said pipeline during output of an OUTGOING NULL replica of said NULL signal by said pipeline during said final clock cycle, thereby enabling read access to said read-write memory means by said alternate control means during output of said NULL signal and enabling write access to said read-write memory means by said alternate control means during output of said OUTGOING NULL signal.