Patent ID: 8612685
Filing Date: 2013-12-17
Classification: G06F

Abstract:
1. A processor, comprising: a cache memory; an instruction issuing unit for issuing an access instruction to a main storage memory based on an access instruction word in a program referring to said main storage memory; a cache control unit that controls a use of said cache memory at a time of an access to the main storage memory from the program during operation by referring to an operation mode of designating use/no-use of said cache memory and a designation of said use of said cache memory in an access instruction issued by said instruction issuing unit; and an operation mode setting unit for changeably setting operation mode information indicative of said operation mode, wherein said operation mode setting unit comprises: wherein said instruction issuing unit issues to said cache control unit an access instruction with cache use for using said cache memory or an access instruction without cache use for not using said cache memory, based on said operation mode and a designation of cache use in said access instruction word, wherein said cache control unit controls said use of said cache memory according to said access instruction from said instruction issuing unit, wherein said instruction issuing unit, when said operation mode designates use of a cache and said access instruction word designates a use of a cache, issues to said cache control unit said access instruction with cache use, and wherein said instruction issuing unit, when said operation mode designates use of a cache and said access instruction word designates no use of a cache, issues to said cache control unit said access instruction without cache use.