Patent ID: 7308320
Filing Date: 2007-12-11
Classification: G06F

Abstract:
1. A processor, comprising a processor core for executing an instruction in a pipeline processing; a data memory accessed by said processor core; and an extended arithmetic unit, connected to an exterior of said processor core, for processing an extended instruction decoded in said processor core in the pipeline processing, said extended arithmetic unit executing an arithmetic operation by using arithmetic operation data retained in a register file in said processor core, and outputting a result of an arithmetic operation directly to a pipeline stage processing after an executing stage processing in said processor core, said processor core receiving the result of the arithmetic operation executed by said extended arithmetic unit and inputted therefrom into said register file in said processor core, wherein said extended arithmetic unit outputs to said processor core an arithmetic operation result invalidating signal that invalidates an execution result of an arithmetic operation executed in said processor core, and said processor core, if the invalidating signal is asserted, controls the pipeline not to stall, in case that a value of a destination register number in an extended instruction code and a value of a register number read out by a succeeding instruction coincide with each other.