Patent ID: 6853023
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A semiconductor memory cell configuration, comprising: bit lines; word lines; dynamic memory cells disposed in a matrix and having trench capacitors and vertical selection transistors, said trench capacitors being connected to associated ones of said vertical selection transistors in a substantially parallel direction to the bit lines, each of said dynamic memory cells having: a trench capacitor having: a block-shaped inner electrode; a dielectric intermediate layer surrounding said inner electrode; and an outer electrode in contact with said dielectric intermediate layer; a vertical selection transistor disposed substantially above said trench capacitor and having: a layer sequence disposed offset from said inner electrode of said trench capacitor, said layer sequence having: a first electrode connected to a respective one of said bit lines; an active intermediate layer; and a second electrode connected to said inner electrode of said trench capacitor; an insulating layer; and a gate electrode layer connected to a respective one of said word lines, said gate electrode layer and said insulating layer completely surrounding said active intermediate layer, said one word line and said one bit line crossing one another; and said trench capacitors and associated ones of said vertical selection transistors of said dynamic memory cells being disposed in rows respectively along said bit lines and in columns respectively along said word lines directly following one another and in each case with a substantially equal spacing from said bit lines.