Patent ID: 6192467
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A processor comprising:a plurality of registers;a register renaming unit coupled to the plurality of registers to provide an architectural register file to store packed data operands, each of the packed data operands having a plurality of data elements; anda decoder, coupled to said register renaming unit, to convert instructions into a first and second set of packed data instructions that each specify one or more registers in the architectural register file, the first set of packed data instructions specifying an operation to be executed on all of the data elements of one or more packed data operands stored in the specified one or more registers, the second set of packed data instructions specifying an operation to be executed on only a subset of the data elements of one or more packed data operands stored in the specified one or more registers; anda partial-width execution unit, coupled to the decoder, to execute operations specified by either the first or the second set of packed data instructions.