Patent ID: 7779375
Filing Date: 2010-08-17
Classification: G01R

Abstract:
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a first local clock signal for each of a plurality of latches of a computer circuit having at least one data input originating from an asynchronous clock domain of the computer circuit with respect to the plurality of latches; wherein the deactivation mechanism is configured to allow a second local clock signal for each of the plurality of latches to remain active, so as to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the plurality of latches to downstream latches with respect to the plurality of latches during at-speed testing.