Patent ID: 6185700
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A program evaluation device for evaluating a program stored in a memory circuit, said program having a main routine, first and second sub-routines, said main routine including a plurality of instructions containing a first call instruction whose execution causes a call of said first sub-routine, said first sub-routine including a plurality of instructions containing a second call instruction whose execution causes a call of said second sub-routine and a first return instruction whose execution causes a return to said main routine, and said second sub-routine including a plurality of instructions containing a second return instruction whose execution causes a return to said first sub-routine, said program evaluation device comprising:an evaluation processor executing said program and having a stack memory and a stack pointer, said stack memory having a plurality of storage regions, a first one of said storage regions being used to store a first return address for returning the execution of said program from said first sub-routine to said main routine, a second one of said storage regions being used to store a second return address for returning the execution of said program from said second sub-routine to said first sub-routine, said stack pointer producing stack address information that points one of said storage regions of said stack memory, said stack address information being changed in one direction each time when at least one of said first and second call instructions is executed and in an opposite direction each time when at least one of said first and second return instructions is executed;a latch circuit coupled to said evaluation processor to latch, in response to execution of said first call instruction, the stack address information from said stack pointer; anda comparison circuit having a first input side coupled to said evaluation processor to receive the stack address information from said stack pointer which is changeable and a second input side coupled to said latch circuit to receive the stack address information from said latch circuit which is latched therein, said comparison circuit outputting a coincident signal when the information at said first input side is coincident with the information at said second input side and supplying said coincident signal to said evaluation processor to inform said evaluation processor of completion of the execution of said first sub-routine.