Patent ID: 6477078
Filing Date: 2002-11-05
Classification: G11C

Abstract:
An integrated memory, comprising:a plurality of memory cells, each one of said plurality of said memory cells including a ferroelectric memory transistor having a control electrode with a ferroelectric layer that can assume at least two different polarization states; a plurality of word lines that essentially run in a first direction; a plurality of bit lines that essentially run in a second direction that is perpendicular to the first direction; and a plurality of control lines that essentially run in the second direction; each one of said memory transistors including a controllable path that connects one of said plurality of said bit lines to one of said plurality of said control lines; said control electrode of each one of said memory transistors is connected to one of said plurality of said word lines; a respective one of said plurality of said control lines is configured between two of said plurality of said bit lines and is connected to said two of said plurality of said bit lines by said controllable paths of a plurality of said memory transistors; said controllable paths of said memory transistors are configured parallel to said plurality of said bit lines and parallel to said control lines; and ones of said memory transistors that are connected to a given one of said plurality of said bit lines have common source/drain regions.