Patent ID: 8260982
Filing Date: 2012-09-04
Classification: G06F,H04L

Abstract:
1. A method for synchronizing data between two clock domains comprising: delaying a first data write to a FIFO queue from a first (write) clock domain by up to one write clock cycle thereby reducing latency between subsequent data writes to said FIFO queue and data reads from said FIFO queue into a second (read) clock domain by said up to one write clock cycle, said first (write) clock domain and said second (read) clock domain having equivalent frequencies, said first (write) clock domain and said second (read) clock domain having any phase relationship with respect to each other; delaying a first data read of said FIFO queue by up to a first read clock cycle occurring after said up to one write clock cycle to achieve a meta-stable data storage condition; writing a first data element into a first position of said FIFO queue; delaying said first data read of said FIFO queue by up to a second read clock cycle to achieve a stable data storage condition; reading said first data element from said first position of said FIFO queue; writing data to each position in said FIFO queue by writing data to a position in said FIFO queue on a write clock cycle and writing to a next position of said FIFO queue on a next write clock cycle, said next position of said FIFO queue being said first position of said FIFO queue when a last position of said FIFO queue was written on said write clock cycle; and reading each written data position in said FIFO queue less than two read clock cycles after said written data position of said FIFO queue receives data from said first (write) clock domain.