Patent ID: 6242774
Filing Date: 2001-06-05
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a substrate having a first conductivity type and a substrate doping concentration;a first well region disposed within the substrate, the first well region having a second conductivity type;a second well region disposed within the substrate, the second well region having the first conductivity type;a drain region disposed within the substrate, the drain region having the second conductivity type;a source region disposed within the substrate, the source region having the second conductivity type;a first dielectric layer disposed betweena first gate and the substrate, wherein the first gate has a first sidewall;a second gate having a second sidewall, the second gate being self-aligned to the first gate bya second dielectric layer disposed between the first sidewall and the second sidewall, said second dielectric layer further disposed between said second gate and said substrate, said second dielectric layer extending at least partially over said source region and exclusive of said drain region, said second dielectric layer comprising different material than said first dielectric layer; anda channel region including a first portion and a second portion disposed in the substrate, said channel region disposed within the second well region and between the drain region and the source region, wherein the first portion of the channel region is separated from a portion of the first gate by the first dielectric layer, and the second portion of the channel region is separated from a portion of the second gate by the second dielectric layer.