Patent ID: 9112740
Filing Date: 2015-08-18
Classification: H04B,H04L

Abstract:
1. A decision feedback equalizer, comprising a first weighting addition circuit that adds an input signal and weighted versions of first to nth feedback signals together, n being an integer not less than 2; a second weighting addition circuit that adds together the input signal and weighted versions of the first to nth feedback signals; a first decision circuit that decides whether or not the result of addition by the first weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to a plurality of latch circuits, the first decision circuit operating in synchronism with a clock signal; the plurality of latch circuits sequentially holding decision results of the first decision circuit in synchronism with the clock signal, the plurality of latch circuits outputting the contents held by component registers thereof as the second to nth feedback signals, respectively; and a second decision circuit that decides whether or not the result of the addition by the second weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision as the first feedback signal, the second decision circuit operating in synchronism with the clock signal.