Patent ID: 8154075
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a plurality of trenches in parallel with each other on a surface of the semiconductor substrate; insulation layers each formed on a bottom surface of each of the plurality of trenches; a select gate electrode formed in a direction perpendicular to the plurality of trenches on the surface of the semiconductor substrate and side walls of the plurality of trenches via a first gate insulating film; a memory gate electrode formed on the surface of the semiconductor substrate and side walls of the plurality of trenches via a second gate insulating film formed of a multilayer film including a charge storage layer, the memory gate electrode formed adjacent to the select gate electrode via an insulating film in a direction perpendicular to the plurality of trenches; and source/drain regions each formed on the surface of the semiconductor substrate between each pair of the plurality of trenches and sandwiching the select gate electrode and the memory gate electrode; wherein a difference between a height of a surface of the select gate electrode and a height of a surface of the memory gate electrode is equal to or greater than a difference between a height of a surface of the insulation layers each formed on the bottom surface of each of the trenches and a height of a surface of the source drain regions.