Patent ID: 7617410
Filing Date: 2009-11-10
Classification: G06F

Abstract:
1. An apparatus for adjusting a logical time of day (TOD)-clock for a computer system having multiple CPUs, each CPU having an associated physical clock providing a time base for executing operations that is stepping to a common oscillator, and an associated logical TOD clock, said apparatus comprising: means associated with a physical clock provided for a CPU in said computer system for detecting propagation of a carry at a pre-determined bit position of said physical clock; means, responsive to said detecting of a carry of a pre-determined bit position, for updating of a TOD-clock offset value (d) to be added to a physical clock value (Tr) value to obtain a logical TOD clock value (Tb) for use by a CPU in said system, wherein each CPU computes a new logical TOD clock value in synchronization, said new logical TOD clock value taking effect simultaneously for said multiple CPUs.