Patent ID: 6512552
Filing Date: 2003-01-28
Classification: H04N

Abstract:
A method of operating a digital video processor in response to audio, video and subpicture data streams, the digital video processor including a CPU and a memory and the subpicture data streams comprising a serial stream of subpicture units (â€œSPU'sâ€ ) wherein a start of each of the SPU's has a presentation time stamp (â€œPTSâ€ ) associated therewith, the method comprising:continuously demultiplexing, storing and decoding the audio and video data streams and playing back corresponding frames of audio and video; continuously demultiplexing, storing and decoding a first subpicture data stream and playing back first subpicture data in synchronization with the playback of frames of video data; continuously storing PTS values associated with SPU's in the first subpicture data stream; detecting a command instructing a transition form the first subpicture data stream to a second subpicture data stream; storing a PTS value associated with a first complete SPU of the second subpicture data stream so that it follows a PTS value associated with a last complete SPU in the first subpicture data stream; continuously storing PTS values associated with the SPU's in the second subpicture data stream; playing back the first subpicture data stream in synchronization with corresponding frames of video according to the stored PTS values associated with the SPU'of the first subpicture data stream; and playing back the second subpicture data stream in synchronization with corresponding frames of video according to the stored PTS values associated with the SPU's of the second subpicture data stream, thereby providing a transition from the first to the second subpicture data streams without playing back any partial SPU's in either of the first or the second subpicture data streams and without any interruption to the continuous demultiplexing, storing and decoding of the audio and video data streams.