Patent ID: 6795879
Filing Date: 2004-09-21
Classification: G06F

Abstract:
Apparatus for storing a record of wait states occurring during the operation of a digital signal processor, the digital signal processor having components generating a ready signal having a first logic state resulting in a non-wait condition for an execution unit of the digital signal processor, the components generating the ready signal with a second logic state resulting in a wait condition for the execution unit, the apparatus comprising:a signal generating unit having a plurality of ready signals applied thereto, the signal generating unit providing a first result signal when all the ready signals applied thereto have a first logic state, the signal generating unit providing a second result signal when at least one of the logic signal applied thereto has a second logic state; a stall analyzer unit having the ready signals applied thereto, the stall analyzer unit generating a signal group identifying a component generating a ready signal having a second logic state; and a storage unit storing the first result signals and the signal groups generated each clock cycle, wherein the first result signals and the signal groups are stored in a plurality of sequences, wherein a first result signal is stored in a first sequence for each clock cycle having no second logic state ready signals, the second result signal is stored in the first sequence for each clock cycle having at least one second logic state signal.