Patent ID: 6576509
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising the steps of:(a) forming a first MISFET in a first region on the main surface of a semiconductor substrate, forming a second MISFET in a second region, and forming a first insulating film over the first MISFET and over the second MISFET over the main surface of the semiconductor substrate; (b) forming a first connection hole in the first insulating film in the first region, and burying a first plug in the first connection hole, including (b-1) forming a first electrically conducting film for constituting the first plug on the first insulating film and in the first connection hole, wherein said first plug is electrically connected to either one of a source and drain of the first MISFET, and (b-2) removing the first electrically conducting film on the first insulating film by etching the first electrically conducting film so that the upper surface of the first electrically conducting film in the first connection hole is retracted down from the upper edge of the first connection hole; (c) forming a second connection hole in the first insulating film in the second region, burying a second plug on the first plug in the first connection hole in a manner that the first plug and the second plug are electrically connected together, and burying a third plug in the second connection hole so as to be electrically connected to either a source or drain of the second MISFET; and (d) forming a first wiring on the first insulating film in the first region, and electrically connecting either the source or the drain of the first MISFET to the first wiring through the first plug and the second plug in the first connection hole.