Patent ID: 7204914
Filing Date: 2007-04-17
Classification: D21C,G01N,G05B,Y10S

Abstract:
1. A system for controlling a processor, comprising: at least one sampling port connected to a stage of said processor and configured to sample a reactant product from the processor; a controller having inputs that provide measurements of the at least one property of the reactant product and that provide a target value for the at least one reactant property; said controller having error calculation units configured to compare the at least one reactant property to the target value in need to control at least one processing parameter of the processor based on measurements of the at least one property of the reactant product such that changes to the at least one processing parameter maintain-the target value for said at least one property of the reactant product; and a dead time compensator included in said controller and including a process evaluator configured to evaluate said at least one property to determine if said at least one effect has been realized at a plurality of sequential times offset from a dead time wherein said dead time relates to a time before at least one effect of at least one of said changes to the at least one processing parameter is fully realized in said at least one property of the reactant product, wherein the dead time compensator comprises: