Patent ID: 8091000
Filing Date: 2012-01-03
Classification: G06F,G11C

Abstract:
1. A method comprising: tracking a number of errors associated with a cache location of a cache memory within a processor; determining if the cache location includes a defect based on the number of errors and an error limit, wherein the error limit is variable over time; after determining that the cache location includes the defect, determining if it is allowable to disable the cache location, including determining an amount of cache locations disabled within a set, determining if the amount of cache locations disabled within the set has reached a limit of cache locations within the set capable of being disabled, and determining it is allowable to disable the cache location in response to determining that the amount of cache locations disabled has not reached the limit of cache locations capable of being disabled within the set; and disabling the cache location in response to determining the cache location includes the defect and determining it is allowable to disable the cache location.