Patent ID: 7181579
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. An integrated memory, comprising: a plurality of memory cells in a memory cell array, the memory cells being combined to form individually addressable normal units; a plurality of redundant units of memory cells for respectively replacing one of the normal units on an address basis; a memory unit for storing, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units; a comparison unit connected to an address bus in the memory and to an output of the memory unit, the comparison unit comparing an address which is present on the address bus with an address stored in the memory unit and activating one of the redundant units in the event of a match being identified; and a test circuit activated by a test mode signal and operable to reset the memory unit to an initial state and to store an identification code for one of the redundant units in the memory unit for subsequently writing the identification code to the one of the redundant units, wherein the identification code represents a position of the one of the redundant units in the memory cell array, and each of the redundant units is discriminated by a respective identification code.