Patent ID: 6806754
Filing Date: 2004-10-19
Classification: H03K

Abstract:
A differential solid state delay line reducing duty cycle distortion in differential solid state delay lines, comprising:n number of substantially identical differential delay cells, each cell of said n number of differential delay cells including a first input associated with a first output and a second input associated with a second output, at least one present of process asymmetry, layout asymmetry and duty-cycle-induced signal distortion regarding circuitry between the first input and the first output in comparison to circuitry between the second input and the second output, each cell of said n number of differential delay cells being connected in series for forming said differential solid state delay line and an even number of said n number of differential delay cells being cross-connected using a twisted line interconnect between differential delay cells having the first output of a preceding one cell of said n number of differential delay cells being connected to the second input of a succeeding one cell of said n number of differential delay cells and the second output of said preceding one cell of said n number of differential delay cells being connected to the first input of said succeeding one cell of said n number of differential delay cells reducing duty cycle distortion in the circuitry between the first input and the first output in comparison to the circuitry between the second input and the second output.