Patent ID: 6542988
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A method for sharing load instruction processing in a processor that includes a load buffer and an annex and that facilitates precise exception handling for out-of-order and speculative load instructions, comprising:tracking an age of a load instruction with a load buffer age indicator in a load buffer, wherein the load buffer age indicator comprises a first plurality of stage bits; determining whether data specified in the load instruction has been retrieved; if the data specified in the load instruction has been retrieved, sending from the load buffer to an annex the load instruction, the data that has been retrieved, and the load buffer age indicator; formatting the first plurality of stage bits into an annex age indicator if the data specified in the load instruction has been retrieved, wherein the annex age indicator comprises a second plurality of stage bits; tracking the age of the load instruction with the annex age indicator in the annex, if the data specified in the load instruction has been retrieved; detecting that a second instruction has caused a precise trap to occur; determining, when the precise trap has occurred, whether the load instruction was issued before the second instruction; and invalidating the load instruction when the precise trap has occurred and the load instruction was not issued before the second instruction.