Patent ID: 7943483
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: preparing a semiconductor substrate including a memory cell region having a memory cell transistor and a peripheral circuit region having a high voltage transistor; forming a first insulating film above the semiconductor substrate situated in the memory cell region and a second insulating film thicker than the first insulating film above the semiconductor substrate situated in the peripheral circuit region; forming a polysilicon film on the first and the second insulating films; forming a silicon nitride film on the polysilicon film; forming a mask pattern on the silicon nitride film for defining a plurality of openings for forming element isolation trenches in the memory cell region and the peripheral circuit region; removing the polysilicon film according to the mask pattern to expose the first and the second insulating films; completely removing the exposed first insulating film in the memory cell region to expose the semiconductor substrate and partially removing the exposed second insulating film in the peripheral circuit region such that a predetermined thickness of the exposed second insulating film remains unremoved; etching the exposed semiconductor substrate in the memory cell region to form a trench having a first depth; removing the remaining second insulating film in the peripheral circuit region to expose the semiconductor substrate; simultaneously etching the exposed semiconductor substrate in the peripheral circuit region and the trench formed in the memory cell region to form a first element isolation trench having a second depth greater than the first depth in the memory cell region and a second element isolation trench having a third depth less than the second depth in the peripheral circuit region; and filling an element isolation insulating film in the first and the second element isolation trenches.