Patent ID: 7683421
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A NAND-type flash memory device, comprising: first and second impurity regions formed in a semiconductor substrate; first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions, the first and second selection gate patterns being adjacent to the first and second impurity regions, respectively; a plurality of cell gate patterns disposed between the first and second selection gate patterns; a first anti-punchthrough impurity region adjacent to the first impurity region that overlaps a first edge of the first selection gate pattern, wherein the first anti-punchthrough impurity region is eccentric to a center of the first selection date pattern; and a second anti-punchthrough impurity region adjacent to the second impurity region that overlaps a second edge of the second selection gate pattern; wherein the semiconductor substrate between the first and second anti-punchthrough impurity regions has a substantially uniform impurity concentration along a direction parallel to a surface of the semiconductor substrate.