Patent ID: 6221716
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method of manufacturing a flash memory cell device, comprising the steps of:forming a tunneling oxide film and a first ploysilicon layer on a semiconductor substrate and then patterning said first polysilicon layer by etching process using a floating gate mask;forming a cell source at a cell area by performing a cell source ion injection process;forming sequentially a dielectric film and a second polysilicon layer, and then pattering said second polysilicon layer while opening a portion of said first polysilicon layer pattern so that a gate electrode can be formed at a peripheral circuit area;performing sequentially a LDD ion injection process, a spacer forming process, a peripheral circuit source/drain ion injection process and a thermal process for activating injected ions to form a transistor of a LDD structure, wherein during the process of forming the spacer, a spacer is formed even at the sidewall of said second polysilicon pattern on the cell area;etching the first and second polysilicon layer patterns at the cell area by performing a self aligned etching process using the control gate mask and said spacer, thereby forming a floating gate and a control gate surrounding one side of said floating gate; andforming a cell source line and a cell drain by performing a cell source self aligned etching process and a cell source/drain ion injection process.