Patent ID: 7026866
Filing Date: 2006-04-11
Classification: H03F

Abstract:
1. An amplifier comprising at least one output and first and second supply rails, the amplifier further comprising offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail, the offset cancellation logic further being operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals, wherein the offset cancellation logic comprises a digital-to-analog converter (DAC), a first up/down counter, a second up/down counter, and calibration control logic, the calibration control logic being operable to configure the amplifier for the calibration and normal operation modes, the calibration control logic further being operable during the calibration mode to control the first and second counters and the DAC via one of the counters to generate the first and second offset cancellation signals, the DAC being operable during normal operation mode to generate the third offset cancellation signal.