Patent ID: 7871877
Filing Date: 2011-01-18
Classification: H01L

Abstract:
1. A method, comprising: forming an implantation mask above a silicon-based layer, said implantation mask covering a portion of said silicon-based layer adjacent to a channel region of a transistor to be formed in and above said silicon-based layer; bombarding said silicon-based layer with a first ionic species to implant the first ionic species into said silicon-based layer to a specified first depth while maintaining a reduced concentration of said first ionic species at a surface area of said silicon-based layer to define a first implant region, said first ionic species having the same valence and a different covalent radius compared to silicon; implanting a second ionic species to a specified second depth into said silicon-based layer to define a second implant region separate from said first implant region, said specified second depth being less than said specified first depth, said second ionic species having the same valence as silicon; performing an anneal process to re-crystallize said silicon-based layer after implanting said first and second ionic species so as to form a strained silicon-based material near said surface area; and forming a gate electrode structure above said silicon-based layer so as to define said channel region including said strained silicon-based material.