Patent ID: 6424197
Filing Date: 2002-07-23
Classification: H03K

Abstract:
An analog front end semiconductor chip for processing signals from an image sensor semiconductor chip in response to externally generated timing signals, comprising:a clock input for receiving one of said externally generated timing signals; a first programmable delay circuit coupled to said clock input for delaying a rising edge of a first timing signal by a first amount; a second programmable delay circuit coupled to said clock input for delaying a falling edge of said first timing signal by a second amount; combining logic coupled to said first and second delay circuits for producing an output clock having a rising edge that is delayed by said first amount, and having a falling edge that is delayed by said second amount, wherein said first and second amounts can be different; and a comparison circuit for comparing a programmed rising edge delay to a programmed falling edge delay, and (i) if said rising edge delay is greater than said falling edge delay, for providing a control signal to said combining logic to cause said combining logic to perform an AND function of timing pulses from said first and second delay circuits, and (ii) if said rising edge delay is less than said falling edge delay, for providing a control signal to said combining logic to cause said combining logic to perform an OR function of timing pulses from said first and second delay circuits.