Patent ID: 8482317
Filing Date: 2013-07-09
Classification: H03K

Abstract:
1. A comparator comprising: (a) an input stage including first and second input transistors; (b) a first current mirror coupled to the first input transistor and a second current mirror coupled to the second input transistor, the first current mirror including a first diode-connected transistor and a first current mirror output transistor, the second current mirror including a second diode-connected transistor and a second current mirror output transistor; (c) each of the first and second input transistors, the first and second diode-connected transistors, and the first and second current mirror output transistors having a source, a drain, and a gate, the sources of the first and second input transistors being coupled to a first reference voltage, the gates of the first and second input transistors being coupled to first and second input signals, respectively, the drain of the first input transistor being coupled to the drain and the gate of the first diode-connected transistor and the gate of the first current mirror output transistor, the drain of the second input transistor being coupled to the drain and the gate of the second diode-connected transistor and the gate of the second current mirror output transistor, the sources of the first and second current mirror output transistors being coupled to a second reference voltage, and the sources of the first and second diode-connected transistors being coupled to the drains of the first and second current mirror output transistors, respectively; and (d) a latch circuit coupled to the drains of the first and second current mirror output transistors.