Patent ID: 8914430
Filing Date: 2014-12-16
Classification: G06F

Abstract:
1. A processor, comprising: an instruction execution pipeline implemented with circuitry disposed on a semiconductor chip, said instruction execution pipeline comprising: an instruction fetch unit to fetch instructions; an instruction decode unit to decode the instructions; and functional units to execute the instructions, a functional unit of the functional units to perform at least three different floating point instructions and having exponent difference calculation logic, a multiplier and an adder to support a first of the at least three different floating point instructions which is a multiply-add instruction, said functional unit also having a rounder to support a second of the at least three different floating point instructions which is a vector round instruction that specifies how many binary places each mantissa value of a vector of floating point values is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add instruction and said vector round instruction, wherein said vector round instruction is a different instruction than said multiply-add instruction, and wherein the functional unit is also able to perform at least one other instruction which is different than the multiply-add instruction and different than the vector round instruction.