Patent ID: 7833823
Filing Date: 2010-11-16
Classification: G11C,H01L

Abstract:
1. A method of forming a programmable memory element comprising the steps of: forming a first conductive layer by depositing a first conductive material on a sidewall of a first dielectric layer, said first conductive layer having a first surface in contact with said sidewall of said first dielectric layer, a second surface spaced apart from said first surface by the thickness of said first conductive layer, and a third surface having a width corresponding to the thickness of said first conductive layer; forming a second dielectric layer in contact with said second surface of said first conductive layer; forming a layer of programmable resistance material by depositing programmable resistance material on a sidewall of a third dielectric layer atop said first and second dielectric layers, said layer of programmable resistance material having a first surface having a width corresponding to the thickness of said programmable resistance material.