Patent ID: 7808103
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A leadless package comprising: a plurality of lower conducting layer patterns disposed separately from one another; an insulating layer pattern on the plurality of lower conducting layer patterns; a plurality of upper conducting layer patterns disposed separately from one another, wherein the plurality of upper conducting layer patterns is on the insulating layer pattern; at least one semiconductor chip disposed on the plurality of upper conducting layer patterns; a hole pattern formed in the plurality of upper conducting layer patterns and in the insulating layer pattern, so that a part of the top surface of the plurality of lower conducting layer patterns is exposed; a first electrical connector electrically connecting the at least one semiconductor chip and the plurality of upper conducting layer patterns; a second electrical connector electrically connecting the plurality of upper conducting layer patterns and the part of the top surface of the lower conducting layer patterns exposed by the hole pattern; and a third electrical connector electrically connecting the part of the top surface of the lower conducting layer patterns exposed by the hole pattern with the at least one semiconductor chip, wherein the first, second, and third electrical connectors comprise bonding wires.