Patent ID: 7719306
Filing Date: 2010-05-18
Classification: H03K

Abstract:
1. An output buffer for an electronic device comprising: a first logic unit comprising a first terminal, a second terminal coupled to a power supply terminal, and a third terminal, for controlling an electrical connection between the second terminal of the first logic unit and the third terminal of the first logic unit according to an input signal from the first terminal of the first logic unit; a second logic unit comprising a first terminal coupled to the first terminal of the first logic unit, a second terminal coupled to a ground terminal, and a third terminal, for controlling an electrical connection between the third terminal of the second logic unit and the second terminal of the second logic unit according to the input signal from the first terminal of the second logic unit; a first transistor comprising a first terminal coupled to the third terminal of the first logic unit, a second terminal coupled to a power supply terminal, and a third terminal, for controlling an electrical connection between the second terminal of the first transistor and the third terminal of the first transistor according to a signal from the first terminal of the first transistor; a second transistor comprising a first terminal coupled to the third terminal of the second logic unit, a second terminal coupled to the ground terminal, and a third terminal, for controlling an electrical connection between the third terminal of the second transistor and the second terminal of the second transistor according to a signal from the first terminal of the second transistor; and a control unit for controlling a conduction order of the first transistor and the second transistor, comprising: