Patent ID: 7843234
Filing Date: 2010-11-30
Classification: H03K

Abstract:
1. A driver circuit, comprising: a driver configured to switch a current source and a current sink to a load via a single node; and a predriver having first and second cross-coupled inverters that include a first and second NFET and a first and second PFET responsive to an input signal, the first inverter being configured to control the switching of the current source to the load and the second inverter being configured to control the switching of the current sink to the load; wherein: the first NFET is larger than the second PFET, creating unequal delays between the output of the first inverter falling to logic zero and the output of the second inverter rising to logic one; the second NFET is larger than the first PFET, creating unequal delays between the output of the second inverter falling to logic zero and the output of the first inverter rising to logic one; the cross-coupling between the first and second inverters and buffer connections of the first and second inverters to said driver are configured such that: the first and second inverters are further configured to remove both the current source and the current sink from the load concurrently to allow tristate operation of the driver.