Patent ID: 6501120
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A method for fabricating a memory cell structure comprising:providing a semiconductor substrate; forming within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode; forming over the field effect transistor (FET) device, and in electrical communication with one of the pair of source/drain regions within the field effect transistor (FET) device, a capacitor structure having a sidewall; and forming over the field effect transistor (FET) device, and in electrical communication with the other of the pair of source/drain regions within the field effect transistor (FET) device, a bitline stud layer adjacent to and extending above the sidewall of the capacitor structure, wherein the bitline stud layer is separated from the sidewall of the capacitor structure at least in part by an air gap void.