Patent ID: 6765825
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A differential Electrically-Erasable and Programmable Read-Only Memory (EEPROM) memory in which a memory cell comprises:a first floating gate transistor comprising a first control gate terminal, a first floating gate, a first source terminal, and a first drain terminal, the first drain terminal coupled to a first differential bit line, the first control gate terminal coupled to a first word line, the first source terminal coupled to a current source or sink; and a second floating gate transistor comprising a second control gate terminal, a second floating gate, a second source terminal, and a second drain terminal, the second drain terminal coupled to a second differential bit line, the second control gate terminal coupled to a second word line, the second source terminal coupled to the current source or sink, wherein the memory further comprises a circuit component configured to identify a binary bit stored by the memory cell depending on which of the first or second floating gate transistors draws more current during a read operation.