Patent ID: 7719302
Filing Date: 2010-05-18
Classification: G01R

Abstract:
1. A method for monitoring interconnect resistance within a semiconductor chip assembly, comprising: (a) given a semiconductor chip assembly including a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having unit terminals in conductive communication with the contacts, for each of a plurality of monitored elements each including a conductive interconnect interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip, comparing a variable voltage drop across such monitored element with a reference voltage drop across a monitor reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly, so as to detect when a resistance of such monitored element is over threshold; and (b) determining whether to indicate an action condition based on a result of step (a), wherein step of comparing is performed with hysteresis such that step (a) detects the resistance of a given one of the monitored elements to be over threshold only when the resistance of such given monitored element exceeds the resistance of the respective reference element by more than a predetermined first threshold value, and after the resistance of the given monitored element has been detected to be over threshold, step (a) detects the resistance to be below threshold only when the resistance of such given monitored element falls lower than the resistance of the monitored reference element by more than a predetermined second threshold value.