Patent ID: 7163859
Filing Date: 2007-01-16
Classification: H01L

Abstract:
1. A method of fabricating a capacitor on a semiconductor device comprising: providing a semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer having a first etch rate R removing a portion of the interlayer dielectric layer to form an interlayer dielectric pattern, the interlayer dielectric pattern comprising an opening, the opening comprising an inner wall and an upper peripheral edge, and exposing a predetermined surface region of the semiconductor substrate; forming a silicide pattern on the predetermined surface region of the semiconductor substrate; forming a lower electrode layer on the interlayer dielectric pattern and the silicide pattern; forming a sacrificial layer on the lower electrode layer, the sacrificial layer having a second etch rate R removing a portion of the sacrificial layer and the lower electrode layer formed on the interlayer dielectric pattern to expose an upper surface of the interlayer dielectric pattern, thereby forming a sacrificial pattern and a lower electrode; and removing the sacrificial pattern at the etch rate R forming a dielectric layer on the lower electrode, the dielectric layer extending across the upper surface of the interlayer dielectric pattern; and forming an upper electrode layer on the dielectric layer.