Patent ID: 8964494
Filing Date: 2015-02-24
Classification: G11C

Abstract:
1. A memory, comprising: a group of four adjacent memory cells in a first array of memory cells; a folded digit sense circuit directly coupled to a first memory cell and a second memory cell of the four adjacent memory cells and configured to determine a replacement IO signal; a first open digit sense circuit operably coupled to a third memory cell of the four adjacent memory cells; a second open digit sense circuit operably coupled to a fourth memory cell of the four adjacent memory cells; at least two memory cells in a second array of memory cells for determining an IO signal; and a data switch comprising inputs operably coupled to the IO signal from the second array and to the replacement IO signal from the folded digit sense circuit, the data switch configured to select and output the replacement IO signal rather than the IO signal in a repair configuration wherein both the IO signal and the replacement IO signal are determined in a same memory cycle.