Patent ID: 8236660
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A method of fabricating a structure comprising: forming at least one FET gate stack on an upper surface of a semiconductor substrate; forming a source extension region and a drain extension region within the semiconductor substrate at the footprint of the at least one FET gate stack; forming recessed regions on opposite sides of the at least one FET gate stack and within the semiconductor substrate; and forming embedded stressor elements substantially within the recessed regions, wherein each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, an upper layer of a second epitaxy doped semiconductor material located atop the lower layer, wherein the lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material, and at least one monolayer of dopant located within the upper layer, the at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.