Patent ID: 7688107
Filing Date: 2010-03-30
Classification: G09G,G11C

Abstract:
1. A shift register comprising: registers at m stages (m is an arbitrary integer number, m≧2) each including a first clocked inverter and a second clocked inverter; wherein a first clocked inverter at a (2n−1)-th stage (n is an arbitrary integer, m≧2n≧2) operates in accordance with a first output from a second clocked inverter at a (2n−2)-th stage, an output from a second clocked inverter at a (2n−1)-th stage, and a first clock signal; wherein a second clocked inverter at the (2n−1)-th stage operates in accordance with a second output from a first clocked inverter at the (2n−2)-th stage, an output from the first clocked inverter at the (2n−1)-th stage, and the first clock signal; wherein the second output is an inversion signal of the first output; wherein a first clocked inverter at a 2n-th stage (n is an arbitrary integer, m≧2n≧2) operates in accordance with a third output from a second clocked inverter at the (2n−1)-th stage, an output from a second clocked inverter at the 2n-th stage, and a second clock signal; wherein the second clocked inverter at the 2n-th stage operates in accordance with a fourth output from the first clocked inverter at the (2n−1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second clock signal; wherein the fourth output is an inversion signal of the third output; wherein the second clock signal is an inversion signal of the first clock signal.