Patent ID: 8355277
Filing Date: 2013-01-15
Classification: G11C

Abstract:
1. A static random access memory (SRAM) system configured to operate in a low power data retention mode comprising: a SRAM cell array coupled between high and low supply nodes, a difference between voltages at the supply nodes defining a data retention voltage during the low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply, the main power switch disconnecting the one of the high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell, the monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in the data retention voltage before data destruction occurs in the SRAM cell array due to the reduction in the data retention voltage; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.