Patent ID: 6101135
Filing Date: 2000-08-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells;a write driver for transmitting an input data to the plurality of memory cells;a sense amplifier for amplifying and outputting data transmitted from the plurality of memory cells in response to a control signal;a data input buffer for buffering a data signal;an address input buffer for buffering an address signal;a data output buffer;an address compare bypass enabling circuit for generating a delayed address signal and generating bypass control signals in response to a comparison of the address signal with the delayed address signal;a multiplexer for selecting either the delayed address signal or the address signal;a bypass control circuit for bypassing write operations to the memory by writing to the data output buffer one of a plurality of bypass data signals in response to the bypass control signals; andan output enabling circuit for creating a data output control signal enabling the data output buffer and disabling the sense amplifier during a bypass operation.