Patent ID: 6873568
Filing Date: 2005-03-29
Classification: G11C

Abstract:
1. A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering said sense amplifiers, said circuit comprising: (a) a first delay circuit for delaying a word line timing pulse by a first predetermined period; (b) a first logic circuit for logically combining said word line timing pulse and said delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit; (c) a second delay circuit for delaying said word line timing pulse by a second predetermined period; and (d) a second logic circuit for logically combining said word line timing pulse and said second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein said second predetermined time period is selected so that ones of a plurality of column access devices are activated after said sense amplifier power supply circuit is enabled.