Patent ID: 8188765
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. An asynchronous pipeline circuit with variable request signal delay, said circuit comprising: a first stage processing a first set of data bits to generate a second set of data bits; a second stage connected in series to said first stage; and a request signal path transmitting a request signal from said first stage to said second stage as said first set of data bits is being processed, said second stage initiating processing of said second set of data bits upon receipt of said request signal, and said request signal path comprising a variable delay line that automatically and selectively applies one of a plurality of different request signal delays to said request signal so as to allow delay of said request signal along said request signal path, said one of said plurality of different request signal delays being automatically and selectively applied so that the transit time for said request signal along said request signal path approximates the actual processing time required by said first stage to completely process said first set of data bits.