Patent ID: 8637887
Filing Date: 2014-01-28
Classification: H01L

Abstract:
1. A chip package, comprising: a carrier including a thermal pad, a plurality of electrodes, and an insulator partially encapsulating the electrodes, wherein the electrodes are exposed at a top surface of the carrier; a wall portion disposed on and circumscribing the top surface of the carrier, the wall portion forming a cavity; at least one chip disposed on the thermal pad within the cavity, the chip being electrically connected to the exposed top surfaces of the electrodes; and an encapsulant disposed within the cavity and encapsulating the at least one chip; wherein a bottom surface of the thermal pad is exposed but bottom surfaces of the electrodes are not exposed, such that the package may be mounted directly to an external device without short circuiting the electrodes; and wherein each of the electrodes is recessed from a lateral surface of the carrier to thereby form a cavity in the lateral surface of the carrier.