Patent ID: 6366150
Filing Date: 2002-04-02
Classification: G06F,H03K,H04L

Abstract:
A digital delay line having a variable delay comprising:a first delay circuit and a second delay circuit, each of the first delay circuit and the second delay circuit comprising a plurality of delay elements connected to each other in series; and a first decoder for selecting one of the plurality of delay elements of the first delay circuit and an adjacent delay element directly connected to the delay element selected by the first decoder, according to a count value transferred from a first flip flop circuit; and a second decoder for selecting one of the plurality of delay elements of the second delay circuit and an adjacent delay element directly connected to the delay element selected by the second decoder, according to a count value transmitted from a second flip-flop circuit, wherein delay times of each of the first and second delay circuits is determined by the delay element selected and the adjacent delay element directly connected to the delay element selected.