Patent ID: 9070713
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A method of fabricating a power semiconductor device, the method comprising: forming a drain region of a first conductive type; forming a drift region of the first conductive type on the drain region; forming a first body region of a second conductive type below an upper surface of the drift region; forming a second body region of the second conductive type having a depth shallower than a depth of the first body region below the upper surface of the drift region and in the first body region; forming a third body region of the second conductive type protruded downwards from a lower end of the first body region to a position shallower than that of an upper surface of the drain region; forming a source region of the first conductive type having a depth shallower than the depth of the second body region below the upper surface of the drift region and in the first body region; forming a gate insulating layer on a channel region of the first body region and on the drift region; forming a gate electrode on the gate insulating layer; forming a source electrode electrically connected to the source region; and forming a drain electrode electrically connected to the drain region.