Patent ID: 6445044
Filing Date: 2002-09-03
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate; a first region having a first conductivity type formed in the substrate; a second region having a second conductivity type formed in the first region having the first conductivity type; a first active device positioned in the first region, the first active device including a first doped active region; a second active device positioned in the second region, the second active device including a second doped active region; a spacer formed on one of the first region and the second region; and a trench disposed from the surface of the substrate in the substrate at a position between the first and second active devices, wherein one side of the trench is aligned with the spacer, wherein the substrate at a base of the trench is defined by a highly doped third region formed in the substrate through the trench, wherein the highly doped third region has a conductivity type selected from the group consisting of the first conductivity type when the trench is disposed in the first region and the second conductivity type when the trench is disposed in the second region, wherein the highly doped third region is doped by a same first dopant of the first doped active region when the highly doped third region is in the first region, wherein the highly doped third region is doped by a same second dopant of the second doped active region when the highly doped third region is in the second region.