Patent ID: 7955932
Filing Date: 2011-06-07
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of manufacturing a single electron transistor, comprising: forming source/drain layers disposed apart on a substrate and forming at least one nanowire channel connecting the source/drain layers; forming a sacrificial layer defining a space that overlaps a partial area of the nanowire chennel to select a location for a quantum dot in the nanowire channel; forming a plurality of oxide channel areas in the nanowire channel, at least one of the plurality of the oxide channel areas being formed through the space defined by the sacrificial layer and insulating at least one portion of the nanowire channel from an adjacent portion of the nanowire channel, and the quantum dot being in the at least one portion of the nanowire channel insulated from the adjacent portion of the nanowire channel by the at least one of the plurality of oxide channel areas; and forming a gate electrode that surrounds the quantum dot.