Patent ID: 6221709
Filing Date: 2001-04-24
Classification: H01L,Y10S

Abstract:
A method of fabricating non-LDD p-channel and LDD n-channel devices in a CMOS circuit, comprising:forming gate electrodes for p-channel and n-channel transistors over n-type and p-type silicon regions that define isolated active areas of the device, wherein the gate electrode for the p-channel transistor has a width which is less than a minimum channel length required for the p-channel transistor;implanting an n-type dopant into the p-type silicon region to form lightly doped source and drain regions of the n-channel transistor;forming a first insulating layer over the gate electrodes and the n-type and p-type silicon regions after implanting the n-type dopant, wherein the first insulating layer has a thickness which, taken on each side of the gate electrode for the p-channel transistor and combined with the width of the gate electrode for the p-channel transistor, exceeds the minimum channel length for the p-channel transistor;implanting a p+ type dopant through the first insulating layer into the n-type silicon region to form low resistivity source and drain regions of the p-channel transistor;forming a second insulating layer over the first insulating layer;etching the first and second insulating layers to form sidewall spacers over the silicon regions adjacent to the gate electrodes; andimplanting an n+ type dopant impurity into the p-type silicon region after forming the sidewall spacers to form low resistivity portions of source and drain regions of the n-channel transistors,wherein the p-channel transistor is formed without lightly dosed source and drain regions.