Patent ID: 6829321
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A shift overflow detection circuit for a shifter having a data bit length of M and a shift control value bit length of N comprising:a plurality of circuit elements disposed in M rows and N columns, each circuit element(i,d) of the i-th row and the d-th column having two inputs and an output, a circuit element of a last column generating an output of said shift overflow detection circuit, wherein: if d=2n*2i where n is in the range 1&lE;n&lE;((M/2i+1)âˆ’1), then element(i,d) is an OR gate having a first input connected to said output of element(iâˆ’l,d+2i) and a second input connected to said output of element(iâˆ’1, d), if d=2n*2i+2j where n is in the range 1&lE;n&lE;((M/2i+1)âˆ’1) and j is in the range 0&lE;j&lE;iâˆ’1, then element(i,d) is a multiplexer having a first input connected to said output of element(iâˆ’1,d), a second input connected to said output of element(iâˆ’1,d+2i) and a control input receiving the i-bit of said shift control value, if d=(2+1)*2i, where n is in the range 1&lE;n&lE; ((M/2i+1)âˆ’1) and j is in the range 0&lE;j&lE;iâˆ’1, then element(i,d) is a multiplexer having a first input connected to said output of element (iâˆ’1,d), a second input receiving 0 and a control input receiving the i-bit of said shift control value, and for all other combinations of i and d, there is no element(i,d).