Patent ID: 7137079
Filing Date: 2006-11-14
Classification: G06F

Abstract:
1. A method of creating a design for a semiconductor memory and an associated memory cell array, comprising: a. providing a leaf cell design for use by a memory compiler for a semiconductor memory, the leaf cell design further comprising a power management circuit design as a leaf cell for a memory circuit and a control supply voltage; b. acquiring a user input describing a parameter of a circuit, the circuit to comprise the leaf cell design; c. providing a user-selectable option to selectively allow enablement of an ultra low power feature; and d. creating a semiconductor memory design by the memory compiler which incorporates the power management circuit in a compiled semiconductor memory macro when the user-selectable option is enabled wherein the control supply voltage includes a netlist identifier which is unique with respect to a netlist identifier for a control supply voltage of the memory cell array.