Patent ID: 6643803
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A digital system comprising a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit, wherein the processor comprises:system resources including registers and at least one memory circuit; an instruction pipeline operable to decode the sequence of instructions, access operands from system resources, and store results in the system resources; test port circuitry for receiving test commands from a remote test host; emulation circuitry for debug events connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a debut event and to leave the debug suspend state to resume execution of the sequence of instruction in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state; and further comprising detection circuitry operable to detect a bubble in the instruction pipeline during which no system resource is being accessed in response to executing the sequence of instructions; and jamming circuitry connected to the instruction pipeline operable to jam an access for a system resource in response to an access command received by the test port circuitry into the bubble detected by the detection circuitry, whereby the access of the system resources in response to the access command is performed without delaying the instruction pipeline when the processor is not in the debug suspend state.