Patent ID: 7953907
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. A first-in first-out (FIFO) memory supporting input and output condition monitoring and a coordinated error response, the FIFO memory comprising: a buffer memory storing payload data, the payload data comprising a frame of data to be sent to a host; a FIFO register with an input and an output, the input and the output supporting separate input and output data rates, the input of the FIFO register being coupled to the buffer memory; a host connection coupled to the output of the FIFO register, the host connection sending the frame of data to the host; and a header generator coupled to the host connection, the header generator creating a header that is added to the payload data; a state machine coupled to the buffer memory, the FIFO register, the header generator, and the host connection, the state machine having logic supporting different error responses corresponding to error type, a state of the buffer memory, and a state of the host connection, wherein the error type includes states corresponding to i) a first error type caused by an abort from a controller, ii) a second error type at the buffer memory, iii) a third error type at the FIFO register output, and iv) a fourth error type occurring between the FIFO and a host.