Patent ID: 6197624
Filing Date: 2001-03-06
Classification: G02F,H01L

Abstract:
A method of manufacturing a semiconductor device including at least a bottom-gate TFT being formed on an insulating surface, said method comprising:forming a gate electrode over the insulating surface;forming a gate insulating film over the gate electrode;forming an amorphous semiconductor film over the gate electrode having the gate insulating interposed therebetween;irradiating the amorphous semiconductor film with a light to crystallize the amorphous semiconductor film to form a crystalline semiconductor film;forming a buffer layer over the crystalline semiconductor film;introducing a first impurity element for controlling a threshold voltage into at least a portion of the crystalline semiconductor film through the buffer layer; andactivating the first impurity element,wherein a channel forming region of the bottom-gate TFT is formed in the portion of the crystalline semiconductor film,wherein a first portion of the channel forming region is defined in the vicinity of a surface on a side farther from the insulating surface, while a second portion of the channel region is defined in the vicinity of an interface between the channel forming region and the gate insulating film,wherein a concentration of the first impurity element in the channel forming region decreases from the first portion to the second portion of the channel forming region.