Patent ID: 6767788
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, which comprises:providing a substrate; forming a first insulating interlayer having a plurality of first contact holes over the substrate; forming a plurality of first metal lines in the first contact holes; sequentially forming second and third insulating interlayers over the first insulating interlayer and the first metal lines; forming a plurality of first trenches in the third insulating interlayer so that at least one of the first trenches corresponds to the first metal lines; forming a first via hole in the second insulating interlayer below the first trenches corresponding to the first metal lines; sequentially forming a first barrier metal film, a first conductive layer, an insulating film, and a second conductive layer over the third insulating interlayer including the first via hole and the first trenches to expose a region of the third insulating interlayer; forming a plurality of second trenches in the exposed third insulating interlayer so that at least one of the second trenches corresponds to the first metal lines; forming a second via hole in the second insulating interlayer below the second trenches corresponding to the first metal lines; forming a second barrier metal film and a third conductive layer on the whole surface; and performing a polishing process to form a first barrier metal pattern and a capacitor in the first via hole and the first trench and to form a second metal line in the second via hole and the second trench, wherein the second metal line and the capacitor have the same level and profile.