Patent ID: 8835240
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising steps as follows: providing an first conductive-type metal-oxide-semiconductor (MOS) transistor and a second conductive-type MOS transistor on a substrate; forming a first stress-inducing dielectric layer and a first capping layer in sequence on the first conductive-type MOS transistor and the second conductive-type MOS transistor; removing a portion of the first capping layer which is disposed on the second conductive-type transistor; performing a thermal annealing after the portion of first capping layer disposed on the PMOS transistor is removed; removing a portion of the first stress-inducing dielectric layer which is disposed on the second conductive-type transistor after the thermal annealing; forming a second stress-inducing dielectric layer and a second capping layer stacking in sequence on the second conductive-type MOS transistor and a remaining portion of the first capping layer disposed on the first conductive-type transistor; removing portions of the second stress-inducing dielectric layer and the second capping layer which are disposed on the first conductive-type MOS transistor by using the remaining portion of the first capping layer as an etching stop layer; and removing the first capping layer.