Patent ID: 6937364
Filing Date: 2005-08-30
Classification: H04N

Abstract:
1. An image processing circuit driven by a clock signal for processing data expressed by a plurality of bits, comprising: a level determining section for determining whether or not a value of input data is smaller than a preset value; and a clock control section for supplying a clock signal that makes a bit corresponding to the preset value active, when said level determining section determines that the value of the input data is not smaller than the preset value and interrupting supply of a clock signal that makes a bit corresponding to the preset value active, when said level determining section determines that the value of the input data is smaller than the preset value, wherein said level determining section delays the result of determination by preset delay time from when values of successively input data items are changed from a value which is not smaller than the preset value to a value which is smaller than the preset value until the preset delay time has elapsed in a case where the values of the successively input data items are changed from the value which is not smaller than the preset value to the value which is smaller than the preset value.