Patent ID: 7366037
Filing Date: 2008-04-29
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a bit line; a pulse signal generation circuit for outputting a precharge pulse signal, the precharge pulse signal is at first level for a predetermined time interval independent of clock frequency; a precharge circuit for precharging the bit line to a predetermined potential based on the precharge pulse signal; a plurality of memory cells connected to the bit line, a selected one of the memory cells maintaining or discharging the precharged bit line according to a signal held by the selected memory cell; word lines for selecting the memory cells; and a latch circuit for holding a signal according to the potential of the bit line the predetermined time interval after the precharging of the bit line is stopped and the memory cell is selected based on the precharge pulse signal wherein the precharge circuit and the latch circuit are included in an output buffer of the semiconductor memory.