Patent ID: 7675343
Filing Date: 2010-03-09
Classification: G09G

Abstract:
1. A level shifter comprising: a first transistor comprising a first electrode coupled to a first power source for supplying a first voltage, a second electrode coupled to a first output terminal, and a control electrode coupled to a second output terminal; a second transistor comprising a first electrode coupled to the first power source, a second electrode coupled to the second output terminal, and a control electrode coupled to the first output terminal; a third transistor comprising a first electrode receiving a first input signal, and a second electrode coupled to the second output terminal; a fourth transistor comprising a first electrode receiving a second input signal that is an inverted signal of the first input signal, and a second electrode coupled to the first output terminal; a first capacitor comprising a first terminal coupled to a control electrode of the fourth transistor at a node X, and a second terminal receiving the first input signal; a second capacitor comprising a first terminal coupled to a control electrode of the third transistor at a node Y, and a second terminal receiving the second input signal; a fifth transistor comprising a control electrode directly coupled to the second terminal of the first capacitor and the first input signal, a first electrode coupled to the control electrode of the fourth transistor and the first terminal of the first capacitor at said node X, and a second electrode coupled to a second power source for supplying a voltage corresponding to a predetermined voltage; and a sixth transistor comprising a control electrode directly coupled to the second terminal of the second capacitor and the second input signal, a first electrode coupled to the control electrode of the third transistor and the first terminal of the second capacitor at said node Y, and a second electrode coupled to the second power source, wherein the fifth transistor is configured to apply a voltage corresponding to a sum of substantially the first input signal voltage and the predetermined voltage to said node X, when turned on by the first input signal, and wherein the sixth transistor is configured to apply a voltage corresponding to a sum of substantially the second input signal voltage and the predetermined voltage to said node Y, when turned on by the second input signal.