Patent ID: 6504755
Filing Date: 2003-01-07
Classification: G11C,H01L

Abstract:
A semiconductor memory device, comprising:a first insulation film on a semiconductor substrate; a second insulation film on the first insulation film; a second MOS (Metal Oxide Semiconductor) transistor in which a channel current flows in the vertical direction to a surface of the second insulation film by being controlled by a word line, and a write data line electrode as a write data line; wherein the first insulation film, the second insulation film, the second MOS transistor and the write data line electrode are stacked orderly on a channel of a first MOS (Metal Oxide Semiconductor) transistor formed on the semiconductor substrate; wherein charges are injected from the write data line by way of a channel of the second MOS transistor into the second insulation film, and the charges are stored in a storage node comprising either charge traps in the second insulation film or an interface between the first insulation film and the second insulation film to thereby hold information and with the information being detected by a change of a current due to a change of a threshold voltage of the first MOS transistor; and wherein a charge injection is performed by flows of electrons and holes caused by tunneling between the first MOS transistor which is controlled by a read data line and the second MOS transistor which is controlled by the write data line and the word line.