Patent ID: 6867724
Filing Date: 2005-03-15
Classification: H03M

Abstract:
1. An input stage for an analog-digital converter, said stage comprising: a buffer having an input terminal that receives an analog signal, and an output terminal; a first switched capacitor circuit structure suitable for sampling the analog signal with a preset sampling period, the first switched capacitor circuit including first and second sampling switches coupled respectively with the output terminal and the input terminal of said buffer, said first and second sampling switches being controlled respectively by first and second signals to close respectively for a first interval of time and for a successive second interval of time of a first semi-sampling period of said sampling period; and a second switched capacitor circuit structure connected to a reference voltage and to said buffer and suitable for generating said second signal with a voltage value greater in absolute value than the value of said analog signal for the duration of said second interval of time of the semi-sampling period.