Patent ID: 6399442
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor, the method comprising in sequence: a first step of growing a first gate oxide layer over a silicon substrate, a second step of depositing a first polysilicon layer over said first gate oxide layer, a third step of selectively etching and removing said first polysilicon layer in order to define the floating gate of said memory cell, a fourth step of introducing dopant in order to obtain source and drain regions of said memory cell, a fifth step of depositing a dielectric layer, a sixth step of selectively etching and removing said dielectric layer and said first polysilicon layer in a region wherein said logic transistor will be formed, a seventh step of depositing a second polysilicon layer, an eighth step of selectively etching and removing said second polysilicon layer in order to define the gate of said logic transistor and the control gate of said memory cell, and further comprising between said sixth step and said seventh step a first sub-step of removing said first gate oxide layer in said region for said logic transistor, and a second sub-step of growing a second gate oxide layer over said region, said second gate oxide layer having a different thickness than a thickness of said first gate oxide layer.