Patent ID: 6438053
Filing Date: 2002-08-20
Classification: G11C

Abstract:
An integrated memory, comprising:bit lines; word lines intersecting said bit lines at points of intersection; memory cells disposed at said points of intersection between said word lines and said bit lines; at least one reference word line intersecting said bit lines at points of intersection; reference cells disposed at said points of intersection between said at least one reference word line and said bit lines, said reference cells generate a reference potential on said bit lines before an access operation to one of said memory cells; a redundant word line intersecting said bits lines at points of intersection; redundant memory cells disposed at said points of intersection between said redundant word line and said bit lines; and a programmable activation unit having a programming state governing if said redundant word line connected to said redundant memory cells replaces one of said word lines connected to said memory cells or said at least one reference word line connected to said reference cells during operation of the integrated memory.