Patent ID: 7313023
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. A non-volatile memory comprising: an array of memory storage units formed into a plurality of columns; a plurality of bit lines corresponding to each of the columns, wherein the memory storage units of a given column are connectable to the corresponding bit line; a plurality of sense circuits each connectable to one or more bit lines whereby the data content of memory storage units connected to a corresponding connected bit line can be sensed; and at least one switch formed on each of said bit lines for the partition thereof into a first portion that remains connectable to the corresponding sense circuit and second portion not connectable to the corresponding sense circuit, wherein the bit lines are orderable as alternating odd and even bit lines, the sense circuits connectable to the odd bit lines formed along a first side of the array and the sense circuits connectable to the even bit lines formed along the side of the array opposite to the first side, wherein said switches partition the array into a plurality of segment, and wherein between each pair of adjacent segments of the array are situated in an alternating manner one of either a switch on each of said even bits lines controlled by a common select line or a switch on each of said odd bits lines controlled by a common select line.