Patent ID: 6163473
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A memory adapted to be responsive to mask and data bit sources comprising a plurality of selectively maskable memory cells, circuitry connected for combining the mask and data bits derived by said sources to derive plural encoded bits having values such that (i) a first combination of the plural encoded bits indicates a first data value and that a cell for storing the encoded bits is not to be masked, (ii) a second combination of the plural encoded bits indicates a second data value and that a cell for storing the encoded bits is not to be masked, and (iii) a third combination of the plural encoded bits indicates a cell for storing the encoded bits is to be masked, each of the selectively maskable memory cells having connections for enabling the cell to be responsive to and store the plural encoded bits associated with that cell as derived by the combining circuitry, each of the maskable cells including output circuitry connected to be responsive to the combination of bits stored in the cell for (a) performing readout associated with the first and second combination of values, and (b) preventing readout of the cell in response to the third combination of values.