Patent ID: 6701401
Filing Date: 2004-03-02
Classification: G06F

Abstract:
A method for testing a USB port, which comprises the steps of:reading in an I/O base address of a USB host controller; initializing a parallel port; testing whether the GND signal is disconnected by setting the D1 and D2 pins of the parallel at high voltages and measuring the D3 pin of the parallel port; testing whether the VCC signal is disconnected by setting the D1 and D2 pins of the parallel at low voltages and measuring the D0 pin of the parallel port; testing whether the D+ and Dâˆ’ form a short circuit with GND by setting the D1 and D2 pins of the parallel port at high voltages and reading the statuses of the D+ and Dâˆ’ from the USB host controller; testing whether D+ and Dâˆ’ form a short circuit with VCC by setting the D1 and D2 pins of the parallel port at low voltages and reading the statuses of the D+ and Dâˆ’ from the USB host controller; testing whether D+ and Dâˆ’ are disconnected by setting the D1 and D2 pins of the parallel port at low voltages and then at high voltages and reading the statuses of the D+ and Dâˆ’ from the USB host controller; testing whether D+ and Dâˆ’ form a short circuit by setting the D1 and D2 pins of the parallel port first at high voltages and then at low voltages and reading the statuses of the D+ and Dâˆ’ from the USB host controller; and displaying the test result.