Patent ID: 7170787
Filing Date: 2007-01-30
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus comprising: a memory array having a plurality of nonvolatile memory cells; a stepped-up/down power supply circuit for generating a first voltage for supplying to a nonvolatile memory cell from an external power voltage; and a stepped-down power supply unit for generating a second voltage for supplying to an internal circuit from the external power voltage, wherein in an operating mode, said stepped-down power supply unit generates the second voltage by stepped down from the external power voltage and supplies the second voltage to said internal logical circuits, and wherein in a standby mode, said stepped-down power supply unit determines the level of the external power voltage, and when the external power voltage is lower than a determination voltage level, supplies the external power voltage as the second voltage to said internal logical circuits, and when the external power voltage is higher than the determination voltage level, supplies a level shifted voltage, which is level shifted by the threshold voltage of a first MOS transistor, from the external power voltage as the second voltage to said internal logical circuits.