Patent ID: 7193254
Filing Date: 2007-03-20
Classification: H01L

Abstract:
1. A semiconductor device structure, comprising: a p-type channel field effect transistor (“PFET”); an n-type channel field effect transistor (“NFET”); a first stressed film disposed over both said PFET and said NFET, said first stressed film having a first portion imparting a first magnitude compressive stress to a conduction channel of said PFET, said first stressed film further having a second portion overlying said NFET, said second portion not imparting said first magnitude compressive stress to a conduction channel of said NFET, said second portion including an ion concentration not present in said first portion such that said second portion imparts one of a compressive stress having a magnitude much lower than said first magnitude, zero stress, or a tensile stress to said conduction channel of said NFET; a second stressed film overlying said PFET and said NFET, said second stressed film imparting a tensile stress to said conduction channel of said NFET; and an intermediate layer overlying said PFET between said first and said second stressed films, said intermediate layer not overlying said NFET.