Patent ID: 6389689
Filing Date: 2002-05-21
Classification: H01L,Y10T

Abstract:
A method of making a plurality of semiconductor packages, the method comprising:providing a substrate comprising a metal core layer having first and second insulative layers respectively laminated on opposing surfaces of the metal core layer, a plurality of sets of circuit patterns on the first insulative layer opposite the metal core layer, and a plurality of apertures through the substrate, wherein each aperture is associated with at least one of the sets of circuit patterns, and the circuit patterns of each set each include a first end proximate to one of the apertures and an opposite second end; providing plurality of semiconductor chips each having a first surface with a plurality of bond pads thereon; attaching the first surface of each semiconductor chip to the second insulative layer opposite the metal core layer using an adhesive layer so that each semiconductor chip is opposite one of the sets of circuit patterns and each bond pad is superimposed by one of the apertures; electrically connecting the bond pads of each chip to the first ends of the respective opposing circuit patterns through the respective superimposed aperture; applying an encapsulant material into each aperture so as to cover the superimposed bond pads; fusing solder balls to the second ends of the circuit patterns of each set of circuit patterns; and severing the substrate around each semiconductor chip so as to singulate a plurality of the packages.