Patent ID: 6362531
Filing Date: 2002-03-26
Classification: H01L

Abstract:
An electronic device, comprising:a substrate; a system of N contiguous levels of interconnect metallurgy on the substrate, wherein each level is formed at a different elevation above the substrate, wherein level N is coupled to the substrate, and wherein N is a positive integer of at least 3; a first group of metallic etch stops at level M, wherein M is an integer no less than 3 and no greater than N; a second group of metallic etch stops at level Mâˆ’1, wherein the second group of metallic etch stops conductively contacts the first group of metallic etch stops in an overlapping multilevel matrix pattern; a cylindrical space that encompasses: levels 1, 2, . . . Mâˆ’1 above the first group of metallic etch stops, and levels 1, 2, . . . , Mâˆ’2 above the second group of metallic etch stops; and a bond pad within the first cylindrical space, wherein the bond pad is substantially formed at level K, wherein K is a positive integer of at least 1 and no greater than Mâˆ’2, wherein the bond pad is conductively coupled to both the first group of metallic etch stops and the second group of metallic etch stops, and wherein the bond pad includes a surface having an exposed portion.