Patent ID: 6383860
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device placed between a first interconnection and a second interconnection, comprising the steps of:preparing a substrate having a dielectric member and a first semiconductor layer formed thereon successively; forming on a surface of said first semiconductor layer, a conductive layer having impurity of a first conductivity type provided therein that becomes one of source/drain regions; forming a first interlayer insulating film on said substrate; forming a gate electrode having upper and lower surfaces on said first interlayer insulating film; forming a second interlayer insulating film on said gate electrode; forming a contact hole that penetrates said first interlayer insulating film, said gate electrode and said second interlayer insulating film to reach a surface of said conductive layer; forming a second semiconductor layer within said contact hole on said conductive layer by epitaxial growth to fill in said contact hole; and implanting impurity of the first conductivity type in a surface of said second semiconductor layer to form a region that becomes the other of said source/drain regions and a channel region sandwiched between the one and the other of said source/drain regions.