Patent ID: 7042276
Filing Date: 2006-05-09
Classification: G11C,H02M

Abstract:
1. A semiconductor circuit comprising: a voltage generating circuit including a first node, a second node and a third node, the first node being supplied with a first potential, the second node being supplied with a second potential, lower than the first potential, and said voltage generating circuit outputting a third potential, higher than the first potential, to the third node, the voltage generating circuit further including: wherein the first potential is supplied to the fifth node, wherein the first charge pump circuit outputs a first signal which varies between a high level and a low level, alternately, the high level of the first signal being higher than the first potential, and wherein a gate of the first MOSFET receives a second signal which varies between a high level and a low level, alternately, the high level of the second signal being lower than the high level of the first signal; wherein the second charge pump circuit outputs a third signal which varies between a high level and low level, alternately, the high level of the third signal being equal to the high level of second signal, wherein the third signal is supplied to the third node via the rectifier MOSFET, and wherein a gate of the rectifier MOSFET is coupled to the fourth node.