Patent ID: 8392690
Filing Date: 2013-03-05
Classification: G06F

Abstract:
1. A management method for reducing the utilisation rate of random access memory (RAM) utilized in flash memory, the method comprising the steps of: (a) constructing a physical memory set from a plurality of physical memory blocks in the flash memory; (b) constructing a logical set from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set during the step (a), and the data stored in each of the logical blocks in the logical set are stored in one number of physical memory blocks of the physical memory set; (c) defining a data-accessing table which is located between the logical block and the physical memory set and defining a mapping table which is located between the physical memory set and the logical blocks during the step (b), wherein the mapping table comprises a hash function, a logical set table, a physical memory set table, and a set status table, wherein the physical memory set table records a plurality of set status indexes corresponding to a plurality of physical memory sets, and a plurality of data-storing statuses associated with the physical memory sets are listed in the set status table to be inquired by the set status indexes, and wherein a quotient of the hash function based on the logical blocks is a logical set number, and a remainder of the hash function is an inter-set number; (d) determining whether the data are either read from or written to the flash memory, wherein if the data are read from the flash memory, proceed to step (f), and if the data are written to flash memory, proceed to step (e); (e) writing the data to the flash memory and updating the mapping table, wherein the data are written to the flash memory and the mapping table is updated based on the relationship of the mapping table between the physical memory set and the logical blocks; and (f) reading an index of the data, wherein the data stored in the flash memory are read based on the relationship of the mapping table between the physical memory set and the logical blocks.