Patent ID: 7412638
Filing Date: 2008-08-12
Classification: G01R

Abstract:
1. A method of controlling test data with a boundary latch module having a plurality of latches to facilitate testing an external signal path of an integrated circuit concurrently with logic built-in self testing of the integrated circuit, the method comprising: (i) providing a plurality of selection devices coupled to a plurality latches of a boundary latch module, the plurality of selection devices for selecting initialization data to store in the plurality of latches of the boundary latch module of the integrated circuit; (ii) utilizing the plurality of selection devices to select the initialization data from a plurality of scan paths of the integrated circuit; (iii) providing the initialization data from at least one of the plurality of latches as at least one output of the integrated circuit for testing at least one external signal path of the integrated circuit; (iv) providing another selection device in the another boundary latch module, the another selection device for selecting an external datum provided by an external input to the integrated circuit or a test-pattern datum from test-pattern generator logic of the integrated circuit; (v) utilizing the another selection device to select the external datum or the test-pattern datum as a datum for capture in at least one of the plurality of latches of the another boundary latch module; and (vi) providing the datum captured by the at least one of the plurality of latches of the another boundary latch module as at least one input to a multiple-input signature register, the multiple-input signature register storing a signature of the integrated circuit resulting from the logic built-in self-testing.