Patent ID: 8869014
Filing Date: 2014-10-21
Classification: G06F,G11C,H03M

Abstract:
1. A memory apparatus comprising: a memory block comprising a plurality of memory cells, each memory cell configured to operate with multi-level signals; a low density parity check (LDPC) coder configured to LDPC encode data values to provide LDPC encoded data values to be written into the memory cells; an interleaver configured to interleave the LDPC encoded data values in accordance with bit interleaved code modulation to generate interleaved LDPC encoded data values; a pulse amplitude modulator operatively coupled to both (i) the interleaver and (ii) the memory block, the pulse amplitude modulator configured to modulate the interleaved LDPC encoded data values for the memory block; and a mapper configured to map the interleaved LDPC encoded data values to modulation codes in accordance with a constellation map, wherein the mapper is configured to (i) map a least significant bit to a modulation code corresponding to a lowest channel, and (ii) map a most significant bit to a modulation code corresponding to a highest channel.