Patent ID: 7298005
Filing Date: 2007-11-20
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising: a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and comprise respective main parts and respective ends; a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area; wherein each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, so as to comprise a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.