Patent ID: 6675341
Filing Date: 2004-01-06
Classification: G06F,H03M

Abstract:
A method of correcting multiple errors in a digital n-bit error correction-coded word, each word comprising a plurality of b-bit packages, said method comprising:receiving from a data source an n-bit word, n being an integer; executing an error correction code on said received n-bit word to correct up to a first predetermined number of errors in a predetermined distribution in said data word, said executing an error correction code including generating a syndrome for said n-bit data word, and detecting an error in excess of said predetermined number of errors in said predetermined distribution; determining a complemented word by complementing said n-bit word in response to detecting an error in excess of said predetermined number of errors; storing said complemented word in said data source; retrieving said complemented word from said data source; determining a re-complemented word by complementing said complemented word retrieved from said data source; executing an error correction code on said re-complemented word to determined said error in excess of said predetermined number of errors is a hard error caused by a faulty element in said data source; determining a position of a b-bit package within said n-bit word, said b-bit package including said hard error, b being an integer; determining an error pattern for said b-bit package using said position and said syndrome; and correcting said n-bit word using said error pattern.