Patent ID: 8035188
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. A semiconductor device having an integrated circuit on a semiconductor substrate, wherein one electrode pad for acceleration test is disposed along the periphery of the semiconductor substrate so that the electrode pad is connected to plural circuits in the integrated circuit which are designed so as to be supplied with different powers or signals; one electrode pad for wire bonding to be connected to the plural circuits is disposed adjacent to the one electrode pad for acceleration test, along the periphery of the semiconductor substrate; and the semiconductor device further includes: a test start signal generation circuit for generating a test start signal which instructs a start of an acceleration test for the plural circuits, the test start signal generation circuit being disposed on the semiconductor substrate; and a delay circuit for delaying the generated test start signal; wherein the plural circuits include a first circuit to which the test start signal from the test start signal generation circuit is inputted, and a second circuit to which the test start signal delayed by the delay circuit is inputted, and the first circuit and the second circuit operate in different time zones during the acceleration test.