Patent ID: 8103993
Filing Date: 2012-01-24
Classification: G06F

Abstract:
1. A design structure for at least one of designing, manufacturing, and testing a design, the design structure embodied by computer-readable program code that is stored in a non-transitory storage medium, which, when the program code is executed, simulates an apparatus for dynamically allocating lanes to a plurality of PCI Express connectors, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of: identifying whether a PCI Express device is installed into each PCI Express connector; identifying historic data traffic for each PCI Express device installed into the plurality of PCI Express connectors; and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector including assigning the lanes to each PCI Express connector in dependence upon the historic data traffic.