Patent ID: 7528431
Filing Date: 2009-05-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first interlayer insulating layer on a semiconductor substrate; a second interlayer insulating layer on the first interlayer insulating layer; at least two contact plugs penetrating the second interlayer insulating layer and extending to the first interlayer insulating layer; an insulating layer pattern covering the second interlayer insulating layer between the neighboring contact plugs, the insulating layer pattern being formed of a material that has an etch rate lower than that of the second interlayer insulating layer; an isolation pattern extending from the insulating layer pattern and penetrating the second interlayer insulating layer between the neighboring contact plugs, the isolation pattern being formed of an insulating material having an etch rate lower than that of the second interlayer insulating layer; and storage electrodes contacting a top surface and formed on sidewalls of the contact plugs.