Patent ID: 6365955
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A cylindrical capacitor structure, especially suitable for fabricating dynamic random access memory, comprising:a substrate; a plurality of conductive sections, an etching stop layer, a first insulation layer and a plurality of bit line structures stacked sequentially on top of the substrate, wherein each bit line structure is constructed from a bit line, a cap layer on top of the bit line and spacers on the sidewalls; a second insulation layer over the bit line structure, wherein the second insulation above the spacers has a plurality of cylindrical openings, and the second insulation layer, the first insulation layer and the etching stop layer between the spacers has a plurality of node contact openings under the cylindrical opening, and neighboring cylindrical openings are linked by narrow gaps; a plurality of upper electrodes each located on a portion of the sidewalls of the cylindrical openings and the node contact openings but completely filled a portion of the gaps; a plurality of dielectric layers on the surface of the upper electrode; a plurality of node contacts that fills the inner surface of the node contact openings in the dielectric layer, wherein the node contacts are electrically connected to the conductive sections; and a plurality of lower electrodes that fills the inner surface of the cylindrical openings in the dielectric layer, wherein the lower electrodes are electrically connected with the respective node contacts.