Patent ID: 8416251
Filing Date: 2013-04-09
Classification: G06F,G06T,G09G,H04N

Abstract:
1. A stream based memory access system for a video processor for executing video processing operations, comprising: a scalar execution unit configured to execute scalar video processing operations; a vector execution unit configured to execute vector video processing operations; a frame buffer memory for storing data for the scalar execution unit and the vector execution unit; and a memory interface for implementing communication between the scalar execution unit and the vector execution unit and the frame buffer memory, wherein the frame buffer memory comprises a plurality of tiles and wherein the memory interface implements a first stream comprising a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit and wherein said memory interface is operable to initiate prefetching of tiles of said first sequential access of tiles and said second sequential access of tiles, and wherein said memory interface is operable to prefetch an adjustable number of tiles of at least one of the first stream and the second stream to compensate for a latency of at least one of the first stream and the second stream.