Patent ID: 6620677
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of processing a semiconductor wafer having at least one array region and at least one support region, the array region including a plurality of vertical dynamic random access memory (DRAM) cells and the support region including a region reserved for support circuitry for the vertical DRAM cells, the array and support regions including a plurality of isolation trenches formed therein, the wafer including a pad nitride disposed thereon, wherein the method comprises:disposing a support liner over the wafer support region; disposing a first insulating layer over the wafer; and planarizing the wafer to remove the first insulating layer from at least the support region and leave a portion of the first insulating layer in the array region, wherein the support liner in the wafer support region protects the isolation trench top surface during the planarization of the wafer, further comprising etching back the isolation trenches to a predetermined height below a top surface of the pad nitride after forming the plurality of isolation trenches, wherein removing the first insulating layer from a top surface of the wafer comprises leaving a portion of the first insulating layer disposed over the support liner in the support region.