Patent ID: 6233670
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A superscalar processor including data storage means for storing data and executing a plurality of instructions under pipeline control using data stored in said data storage means, wherein each of said instructions includes a source address indicating an address in said data storage means in which data to be used for executing the instruction is stored and a destination address indicating an address in said data storage means in which the executed data should be stored, said superscalar processor comprising:simultaneously executable instruction detecting means for detecting simultaneously executable instructions out of the plurality of instructions;a plurality of pipeline processing executing means for executing respective instructions detected by said simultaneously executable instruction detecting means in parallel under pipeline control,each of said plurality of pipeline processing executing means including an instruction executing means for executing sequentially given instructions under pipeline control;address coincidence detecting means for detecting coincidence between a source address included in a first instruction executed by one of said plurality of pipeline processing executing means and a destination address included in a second instruction executed earlier than the first instruction by the one or at least one another of said plurality of pipeline processing executing means; anddirect application means responsive to said address coincidence detecting means indicating the coincidence for directly applying an execution result data obtained by the one or the at least one another pipeline processing executing means executing the second instruction to an instruction executing means in the one pipeline processing executing means executing the first instruction.