Patent ID: 6366508
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A memory array comprising:a zone of memory elements arranged in rows and columns, including a first set of non-redundant columns and a first redundant column; a first data node; and a column multiplexer having a first section which is coupled to the first set of non-redundant columns and the first redundant column and comprises: a selectable non-redundant path through the first section for each of the non-redundant columns, which extends from a respective one of the non-redundant columns in the first set to the first data node; a selectable redundant path through the first section, which extends from the first redundant column to the first data node; a respective column select line for each of the non-redundant paths; a non-redundant column select switch in each of the non-redundant paths, which comprises a select terminal and is coupled in series between a respective one of the non-redundant columns in the first set and the first data node; a redundant column select switch in the first redundant path, which comprises a select terminal and is coupled in series between the first redundant column and the first data node; and wherein each of the column select lines is switchably coupled to either the select terminal of the respective non-redundant column select switch or the select terminal of the redundant column select switch such that the redundant path is interchangeable with any one of the non-redundant paths for the non-redundant columns in the first set.