Patent ID: 8290044
Filing Date: 2012-10-16
Classification: H04N

Abstract:
1. A non-transitory computer readable medium storing: a sum-of-absolute-differences (SAD) instruction specifying a first source register, a second source register, and a destination register distinct from the first source register and from the second source register, the destination register to store SAD operation results that, when executed by a processing unit, causes the processing unit to perform two independent SAD operations, the two independent SAD operations including a first SAD operation based on a first pair of corresponding sections of the first source register and the second source register and a second SAD operation based on a second pair of corresponding sections of the first source register and the second source register, wherein each section of the first pair of corresponding sections is different than each section of the second pair of corresponding sections, wherein the first SAD operation is independent of the each section of the second pair of corresponding sections, and wherein the second SAD operation is independent of each section of the first pair of corresponding sections, a result of the first SAD operation being stored in a first section of the destination register and a result of the second SAD operation being stored in a second section of the destination register.