Patent ID: 6197645
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of forming an IGFET, comprising the steps of:forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface;depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region, wherein the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer;implanting a dopant into the elevated source and drain regions; anddiffusing the dopant from the elevated source and drain regions into the underlying source and drain regions.