Patent ID: 6035112
Filing Date: 2000-03-07
Classification: G01R,G06F

Abstract:
A method for producing a cell library for use with a logic simulation apparatus, said cell library including information on a plurality of cells, each cell having a function represented in accordance with a truth table model as a combination of a plurality of patterns, each pattern including an input signal and an output signal, and method comprising the steps of:providing the information of each cell to the logic simulation apparatus;determining whether the input signal of the patterns of the cell include edge signals including a rising edge signal or a falling edge signal;selecting the patterns that are determined to include the edge signals;separating the selected patterns from the truth table model of the cell;developing each of the selected patters into two associated patterns, the two associated patterns include associated input signals different from each other in level in accordance with the edge signals; andadding a virtual memory to each of the developed associated patterns.