Patent ID: 6144219
Filing Date: 2000-11-07
Classification: G11C

Abstract:
An isolation circuit for isolating data input to a memory controller device during low power conditions, comprising:a first low power indicator input signal having an active state;a second low power indicator input signal having an active state;a digital logic blcok having an output and having a first input connected to said first low power indicator signal and a second inut connected to said second low power indicator signal, and having a NAND gate an input connected to said first low power indicator input signal, a NOR gate with an input connected to an output of said NAND gate, and a Flip-Flop with one input connected to an output of said NOR gate and another input connected to said first low power indicator input signal;wherein in response to said first and said second low power indicator input signals entering its respective active state, said output of said digital logic block enters a logic state to signify a lower power condition has occurred.