Patent ID: 6101129
Filing Date: 2000-08-08
Classification: G11C

Abstract:
In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to the respective rows of the memory cells, a plurality of bit lines coupled to the respective columns of the memory cells, each of the memory cells comprising a source and a drain and capable of storing a respective bit, the columns of memory cells arranged in a plurality of sets, and an internal voltage supply pump capable of generating an internal pump voltage for erasing the memory cells in one set of columns at a time in an embedded chip erase mode, a method for fast chip erase of the memory cells comprising the steps of:(a) providing an acceleration voltage greater than the internal pump voltage;(b) providing an erase write command;(c) performing a fast erase operation on the memory cells, comprising the step of coupling the acceleration voltage to the sources of the memory cells in a plurality of sectors simultaneously; and(d) performing a fast preprogramming operation on the memory cells prior to the step of performing the fast erase operation.