Patent ID: 9093516
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A heterostructure field effect transistor comprising: a semiconductor wire having a longitudinal direction and a transversal direction; a source region in the longitudinal direction of the semiconductor wire; a drain region in the longitudinal direction of the semiconductor wire; a channel region in between the source region and drain region and in the longitudinal direction of the semiconductor wire; a source core region in the transversal direction of the semiconductor wire; a source shell region disposed around the source core region, the source shell region having a thickness; a drain core region in the transversal direction of the semiconductor wire; a drain shell region disposed around the drain core region, the drain shell region having a thickness; a channel core region in the transversal direction of the semiconductor wire; a channel shell region disposed around the channel core region, the channel shell region having a thickness; and a gate structure disposed around the channel region, the gate structure comprising a gate dielectric layer disposed around and in contact with the channel region and a gate layer disposed around and in contact with the gate dielectric layer, wherein the thickness of the channel shell region is smaller than the thickness of the source shell region, wherein the thickness of the channel shell region is smaller than the thickness of the drain shell region, and wherein the source shell region, the drain shell region, and the channel shell region are each quantum well regions.