Patent ID: 7475187
Filing Date: 2009-01-06
Classification: G11C,H03M

Abstract:
1. An interface circuit implemented in a semiconductor memory chip having a memory core, the interface circuit being connectable to a shared read and write data/command-and-address bus and comprising: a serial output terminal connectable to a serial input terminal of an interface circuit of another memory chip or to a serial input terminal of a memory controller; a serial input terminal for receiving a serial stream of data/command-and-address signals from a serial output terminal of an interface circuit of another memory chip or from a serial output terminal of a memory controller; a reference clock receiving terminal for receiving a reference clock signal; a read and write data/command-and-address signal re-driver/transmitter path for re-driving read data signals and write data/command-and-address signals not destined for the semiconductor memory chip and received at the serial input terminal; and a main signal path leading from a parallel read data input terminal to the serial output terminal for transmitting read data from the memory core and from the serial input terminal to a parallel write data/command-and-address signal output terminal to transfer parallel write data/command-and-address signals to the memory core and including: