Patent ID: 6646923
Filing Date: 2003-11-11
Classification: G11C,H01L

Abstract:
A method of operating a semiconductor memory device having split gate-type non-volatile memory cells including first electrodes respectively connected with a plurality of bit lines, control gates respectively connected with a plurality of word lines, and second electrodes connected with a common line, the method comprising the steps of:erasing data of the plurality of memory cells by respectively applying a first voltage to the common line, the first voltage to the plurality of bit lines, a negative voltage lower than the first voltage to the substrate of the memory cells, and a high voltage to the plurality of word lines; performing a programming operation with respect to a selected cell among the plurality of memory cells by respectively applying the first voltage to the bit line of the selected cell, a power voltage to the bit line of the non-selected cells, a second voltage to the word line of the selected cell, the first voltage to the word line of the non-selected cells, the high voltage to the common line of the selected cell, the first voltage to the common line of the non-selected cells, and the negative voltage to the substrate of the memory cells; and performing a reading operation with respect to the selected cell among the plurality of memory cells by respectively applying a read voltage to the bit line of the selected cell, the first voltage to the bit line of the non-selected cells, a reference voltage to the word line of the selected cell, the first voltage to the word line of the non-selected cells, the first voltage to the common line of the selected and non-selected cells, and the first voltage to the substrate of the memory cells.