Patent ID: 9172524
Filing Date: 2015-10-27
Classification: G01S,H03L,H04B,H04L

Abstract:
1. A delay lock loop (DLL), comprising: a local signal generation unit configured to generate an early and late delayed signal pair m(t+τ+Δ/2) and m(t+τ−Δ/2) with respect to a total time 0<t<T, T being a real number, early and late delayed, respectively, based on a phase delay τ and a delay value difference Δ, wherein τ and Δ are real numbers, with respect to a signal pulse train of a time-multiplexed binary offset carrier (TMBOC)(6,1,4/33)-modulated received signal m(t); early and late correlation units configured to generate early binary offset carrier (BOC)(1,1) partial correlation functions {P early and late BOC(1,1) sub-correlation units configured to generate early and late BOC(1,1) sub-correlation functions S an early BOC(6,1) sub-correlation unit configured to obtain a first early intermediate correlation function Q a late BOC(6,1) sub-correlation unit configured to obtain a first late intermediate correlation function Q early and late combination units configured to generate an early main correlation function R a numerical control oscillator (NCO) configured to determine a phase delay τ for the TMBOC(6,1,4/33)-modulated received signal m(t) based on a discrimination output of a discrimination function based on values of the early and late main correlation functions, and to output the determined phase delay τ to the local signal generation unit; wherein the elimination operation is an operation satisfying algebraic relations in which |A|+|B|−|A−B|=0 when real numbers A and B are AB≦0 and |A|+|B|−|A−B|>0 when the real numbers A and B are AB>0.