Patent ID: 9159449
Filing Date: 2015-10-13
Classification: G09G,G11C

Abstract:
1. A shift register comprising a plurality of stages, each of the stages outputting k composite pulses (where k is a natural number greater than 1), each of the composite pulses comprising an A-scan pulse and a B-scan pulse, wherein at least one of the stages comprises: k A-sub-stages, each of the A-sub-stages controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse; a B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the at least one B-reset node and any one B-clock pulse; and a scan output controller for generating k A-scan pulses based on the voltages at the respective A-set nodes of the A-sub-stages and the A-clock pulses supplied respectively to the A-sub-stages, generating k B-scan pulses based on the B-carry pulse and k BA-clock pulses, and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as a corresponding one of the composite pulses.