Patent ID: 8555040
Filing Date: 2013-10-08
Classification: G06F

Abstract:
1. An indirect branch predictor comprising: a branch prediction memory comprising a plurality of entries, wherein each entry is configured to store a target address corresponding to a previously-executed indirect branch instruction and a corresponding validation tag corresponding to the previously-executed indirect branch instruction, wherein the validation tag is derived at least in part from at least a portion of a program counter address (PC) of the previously-executed branch instruction, wherein the branch prediction memory is coupled to receive an index selecting at least a first entry of the plurality of entries, wherein the branch prediction memory is configured to output a first target address and a first validation tag from the first entry in response to the index; and a control circuit coupled to the branch prediction memory and coupled to receive the first validation tag, wherein the control circuit is configured to compare the first validation tag to corresponding state for a current indirect branch instruction, and wherein the control circuit is configured to inhibit speculative processing of instructions at the first target address responsive to the first validation tag not matching the corresponding states for the current indirect branch instruction because the first target address corresponds to a different indirect branch instruction, and wherein the control circuit is further configured to inhibit speculative processing of instructions at a sequential address to the current indirect branch instruction responsive to the first validation tag not matching the corresponding states for the current indirect branch instruction.