Patent ID: 8008711
Filing Date: 2011-08-30
Classification: H01L

Abstract:
1. An insulated gate transistor comprising: a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface; a first semiconductor layer of a second conductivity type which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first portion which includes a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a bottom surface forming a substantially flat surface substantially parallel to said first main surface; a first main trench passing from said first main surface through the bottom surface of a first portion of said flat region of said first semiconductor layer, said first main trench comprising a bottom portion situated just below said first semiconductor layer in said semiconductor substrate; an insulating film formed on said first main trench so that each of said bottom portion and a side surface of said first main trench is covered with said insulating film; a control gate formed over said insulating film and filled into said first main trench; a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said first portion of said flat region of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer; a first main electrode formed on said top surface of said second semiconductor layer and said first side diffusion region of said first portion of said first semiconductor layer; a third semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said third semiconductor layer, wherein said first side surface of said second semiconductor layer is joined to said side surface of said first main trench, said first side diffusion region in said first portion is situated just above said third semiconductor layer, a bottom surface of said first side diffusion region is curved such that a depth of said first side diffusion region between said first main surface and the bottom surface of said first side diffusion region continuously decreases from a position of largest depth, where the first side diffusion region contacts the flat region, to a position within the first side diffusion region which is furthest away from the flat region, and a bottom surface of said second side diffusion region is curved such that a depth of said second side diffusion region between said first main surface and a bottom surface of said second side diffusion region continuously decreases from a position of largest depth, where the second side diffusion region contacts the flat region, to a position within the second side diffusion region which is furthest away from the flat region; said insulated gate transistor further comprises: a second main trench which passes from said first main surface through a bottom surface of a second portion of said flat region of said first semiconductor layer, and comprises a bottom portion situated just below said first semiconductor layer in said semiconductor substrate; and a first auxiliary trench passing from said first main surface through said curved bottom surface of said first side diffusion region and comprising a bottom portion situated below said first side diffusion region in said semiconductor substrate, wherein said first and second main trenches are arranged in parallel to sandwich said flat region of said first semiconductor layer therebetween.