Patent ID: 6160429
Filing Date: 2000-12-12
Classification: H03K

Abstract:
A power-on reset buffer circuit having an output node, the circuit comprising:a. a comparator having a positive input terminal, a negative input terminal, and an output coupled to the output node of the circuit, wherein said comparator is powered by a high-potential power rail and a low-potential power rail;b. a first threshold branch having an output coupled to said positive terminal of said comparator and a low-potential node coupled to the low-potential power rail, wherein said first threshold branch includes a first potential drop device and a second potential drop device, wherein said first potential drop device includes a resistor having a high-potential node coupled to the high-potential power rail and a low-potential node coupled to said positive terminal of said comparator; andc. a second threshold branch having an output coupled to said negative terminal of said comparator and a low-potential node coupled to the low-potential power rail, wherein said second threshold branch includes a third potential drop device and a fourth potential drop device, wherein said third potential drop device includes a diode means and a resistor, said diode means having a high-potential node coupled to the high-potential power rail and a low-potential node coupled to a high-potential node of said resistor of said third potential drop device, and wherein a low-potential node of said resistor of said third potential drop device is coupled to said negative terminal of said comparator,wherein said first threshold branch is designed to produce at said output of said first threshold branch a first potential at said positive terminal that is higher than a second potential supplied by said second threshold branch at said output of said second threshold branch to said negative terminal, and wherein said second potential drop device and said fourth potential drop device provide substantially equivalent potential drops.