Patent ID: 7974128
Filing Date: 2011-07-05
Classification: G11C

Abstract:
1. A flash memory device comprising: control logic adapted to generate a first flag signal during a program interval of each of a plurality of program loops, wherein a program voltage is supplied to a selected word line in accordance with the first flag signal; a high voltage generator circuit adapted to generate the program voltage and generate a second flag signal during the program interval, wherein the second flag signal indicates whether the program voltage has been restored to a target voltage; a dip signal generator circuit adapted to generate a dip signal in accordance with the first and second flag signals, wherein the dip signal indicates whether the program voltage has dropped below the target voltage; a restoration signal generator circuit adapted to generate, in accordance with the dip signal and the first and second flag signals, a restoration signal indicating whether the program voltage has been restored to the target voltage; and, a first end signal generator circuit adapted to generate a first end signal in accordance with the restoration signal, wherein the control logic is adapted to deactivate the first flag signal, when the first end signal is generated, in order to terminate the program interval.