Patent ID: 8619930
Filing Date: 2013-12-31
Classification: G11C,H04L

Abstract:
1. A synchronization circuit configured to synchronize received data, the synchronization circuit comprising: a determiner configured to determine whether or not data with a phase of internal clock is able to be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit configured to accept the data and the internal clock, to capture the data with the phase of the internal clock and to synchronize the data, when the determiner determines that the synchronization circuit is able to stably capture the data with the phase of the internal clock; and a second flip-flop configured to accept the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, to capture the data with the phase of the inverted internal clock, and to synchronize the data, when the determiner determines that the synchronization circuit is not able to stably capture the data with the phase of the internal clock.