Patent ID: 6218246
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A fabrication method of triple polysilicon flash EEPROM arrays, comprising:forming a gate oxide layer on a semiconductor substrate having a source and a drain;forming a first polysilicon strip on said gate oxide layer in a first direction;forming a dielectric layer on said first polysilicon strip;forming second polysilicon strips on said dielectric layer in a second direction which is perpendicular to the first direction;forming oxide strips respectively on said second polysilicon strips;forming spacers at both side-walls of said oxide strips and said second polysilicon strips respectively formed thereon;forming polysilicon layer over the oxide strips, along the spacers and over the dielectric layer;forming in the second direction masking strips which define erase gate regions on said polysilicon layer; andforming individual erase gates and floating gates by sequentially etching the polysilicon layer, the dielectric layer and the first polysilicon strip.