Patent ID: 7302532
Filing Date: 2007-11-27
Classification: G06F

Abstract:
1. A central processing unit, comprising: (A) a microprocessor; (B) a main memory having a plurality of data storage sections, one section having a first set of addresses and a second section having a second set of addresses; (C) a microprocessor interface coupled to the microprocessor and the main memory, such microprocessor interface comprising: (D) wherein the main memory interface comprises: wherein the data rebuffering section is adapted to selectively couple data from any one of a plurality of bi-directional data ports to a bi-directional data port of the microprocessor selectively in accordance with a control signal and wherein the data rebuffering section includes: a selector responsive to the control signal for coupled data between a selected one of the bi-directional data ports and the microprocessor; and wherein the data rebuffering section includes a data distribution unit having a plurality of bi-directional ports each one of the bi-directional ports being coupled to a corresponding one of: