Patent ID: 7271477
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. A power semiconductor device package comprising: a plurality of power semiconductor chips which are arranged in a laminated structure so that said plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another by connecting electrode wirings, which are formed on the surfaces opposing to each other, in a direct manner with a conductive member, said plurality of power semiconductor chips being sealed in a sealing resin as one body, a first electrode wiring formed on the bottom surface of a first power semiconductor chip as the bottom layer among said plurality of power semiconductor chips arranged in said laminated structure being connected to a lead frame, a second electrode wiring formed on the upper surface of a second power semiconductor chip as the top layer among said plurality of power semiconductor chips being connected to a metallic frame, a wire strap, or a bonding wire, which are connected to the lead frame, the electrode wirings formed on the surfaces, which are opposed to each other, of said plurality of power semiconductor chips being connected to external terminals, the lead frame being extended as an external electrode, and current flowing through each of said plurality of power semiconductor chips in a vertical direction of the laminated structure.