Patent ID: 6356610
Filing Date: 2002-03-12
Classification: G06F,H04L

Abstract:
A system for avoiding unstable data transfer between digital devices, said system comprising:a digital transmitter device which transmits a data signal and a first clock signal; and a digital receiver device coupled to receive said data signal and said first clock signal, said digital receiver device comprising: a clock generator circuit coupled to receive said first clock signal and for generating a second clock signal; a clock monitor circuit coupled to receive said first clock signal and said second clock signal, wherein said clock monitor circuit detects a potential unstable operating condition for said digital receiver device by monitoring the set-up time criterion and the hold time criterion of the transitions within said second clock signal; in response to detecting said potential unstable operating condition, said clock monitor circuit generates an adjust signal causing said clock generator circuit to manipulate the phase of said second clock signal with respect to the phase of said first clock signal in order to remove said potential unstable operating condition; and internal circuitry coupled to receive said data signal and said second clock signal.