Patent ID: 6258651
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method for making an integrated circuit device, said method comprising:providing a substrate having a transfer field effect transistor (FET) with a first gate electrode and a first source/drain region formed in and on a embedded DRAM region of said substrate and having a logic FET with a second gate electrode and a second source/drain region formed in and on a logic circuit region of said substrate;depositing a dielectric layer over said exposing surface of said transfer FET and above of said logic FET;polishing said dielectric layer until upper surface of said first gate electrode and said second gate electrode is exposed;forming a photoresist layer over said dielectric layer and said first gate electrode;etching said dielectric layer until upper surface of said logic FET is exposed;removing said photoresist layer; andsimultaneously depositing a self-aligned silicide layer over said exposed second gate electrode, over said second source/drain region and over said exposed first gate electrode.