Patent ID: 6751756
Filing Date: 2004-06-15
Classification: G06F,G11C

Abstract:
In a data processing system having an instruction processor, a storage system, a read buffer and a first level cache, the instruction processor retrieving stored instruction from the storage system and storing the retrieved instructions in the read buffer, with the instructions previously stored in the read buffer provided to the first level cache, the instruction processor selecting and executing instructions from the first level cache and read buffer, and retrieving one or more instructions from the storage system if a desired instruction is not currently stored in the first level cache or read buffer, the instruction processor further having error detection circuits for providing an error signal in response to detecting a parity error in a corrupted instruction, and retry circuits for causing the instruction processor to discard the corrupted instruction and to again retrieve the discarded instruction from the storage system in response to receiving the error signal, a selectable error injection system, comprising:programmable storage means for storing identifiers, each identifier specifying respective predetermined ones of the stored instructions in the read buffer; and corruption means coupled to the read buffer and to said programmable storage means for selectively corrupting said predetermined ones of the stored instructions when said stored instructions are provided from the read buffer to the first level cache.