Patent ID: 8956789
Filing Date: 2015-02-17
Classification: G03F,H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer; selectively etching an absorber layer of the mask blank using the first patterned photoresist layer to form a first patterned mask that includes fiducials; mounting the first patterned mask on a second chuck and determining a non-flatness compensation for the first patterned mask mounted on the first chuck relative to being mounted on the second chuck using the fiducials; mounting the first patterned mask on the first chuck and patterning a second photoresist layer overlying the first patterned mask to form a second patterned photoresist layer including a device pattern that has been adjusted using the non-flatness compensation; and selectively etching the absorber layer of the first patterned mask using the second patterned photoresist layer to form a second patterned mask that includes the device pattern.