Patent ID: 6055207
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A synchronous semiconductor memory device comprising:a memory cell array having at least two banks each being divided into a plurality of blocks, wherein each of the blocks has a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns;internal clock signal generating means for generating an internal clock signal synchronized with an external clock signal;column address decoding means for decoding a column address for addressing one of the columns to generate a first address as block selection-information and a second address as column selection-information;column selecting means for selecting one of the columns corresponding to the first address in response to the second address synchronized with a Nth cycle, wherein N is an integer, of the internal clock signal after disabling an addressed column at a (N-1)th cycle previous to the Nth cycle of the internal clock signal in response to a predetermined column disable signal that is distinct from the second address; andcolumn disable signal generating means for generating the column disable signal only when the first address corresponding to column activated at the (N-1)th cycle of the internal clock signal is activated during the Nth cycle of the internal clock signal,wherein said column disable signal generating means comprises:a latch circuit for latching a signal;a switching circuit for transferring the first address to the latch circuit in response to the internal clock signal; anda logic circuit for mixing the internal clock signal and the first address applied through the switching circuit, the logic circuit outputting the column disable signal in accordance with the mixed result.