Patent ID: 6163182
Filing Date: 2000-12-19
Classification: H03J,H03K

Abstract:
An integrated circuit comprising a programmable frequency divider having a first input for receiving a signal having an input frequency, a second input for receiving a control signal, and an output, the programmable frequency divider comprising:a first frequency divider having an input constituting the input of the programmable frequency divider, and an output for supplying a signal having an intermediate frequency whose value is 2.P times lower than that of the input frequency, in which P is a predetermined integer,a second frequency divider having an input connected to the output of the first frequency divider, and an output constituting the output of the programmable frequency divider for supplying a signal having an output frequency whose value is K times lower than that of the intermediate frequency, in which K is a real number whose value is determined by the value of the control signal,characterized in that, with P being higher than or equal to N, the first frequency divider comprises a frequency divider circuit having a symmetrical input for receiving a signal having a first frequency, and a symmetrical output for providing a signal having a second frequency whose value is 2.N times lower than that of the first frequency, in which N is a predetermined integer which is at least equal to 2, the frequency divider being composed of memory cells realized in ECL technology, each having a symmetrical data input, a symmetrical clock input and a symmetrical data output, characterized in that the frequency divider comprises 2.N memory cells of the above-mentioned type, the data output of the i.sup.th memory cell, referred to as memory cell of rank i, being connected, for i=1 to 2.N-1, to the data input of the memory cell of rank i+1, the data output of the memory cell of rank 2.N being cross-connected to the data input of the memory cell of rank 1, the data output of one of the memory cells constituting the output of the frequency divider circuit, the clock input of each memory cell of an odd rank being connected to the symmetrical input of the frequency divider circuit, the clock input of each memory cell of an even rank being cross-connected to said symmetrical input.