Patent ID: 8592273
Filing Date: 2013-11-26
Classification: H01L

Abstract:
1. A method of manufacturing a non-volatile memory device, comprising: forming a first dielectric pattern and a floating gate pattern on an active region of a semiconductor substrate defined by a device isolation pattern of the semiconductor substrate, the floating gate pattern extending in a first direction and the device isolation pattern being exposed through a recess between a pair of the floating gate patterns adjacent to each other in a second direction substantially perpendicular to the first direction; forming a second dielectric layer to cover the floating gate pattern and the device isolation pattern exposed through the recess; forming a control gate layer on the second dielectric layer to a thickness to fill up the recess; partially removing the control gate layer to form a plurality of control gate lines extending in the second direction such that the second dielectric layer is exposed through a gap space between a pair of the plurality of control gate lines adjacent to each other in the first direction; forming a first etch-proof layer on a sidewall of the plurality of control gate lines that is exposed to the gap space, the first etch-proof layer including an oxide; sequentially removing the second dielectric layer and the floating gate pattern under the second dielectric layer exposed through the gap space to form a second dielectric pattern extending in the second direction and a floating gate electrode under the second dielectric pattern by a unit of a memory cell, so that the floating gate electrode, the second dielectric pattern and the control gate line are stacked at each of the memory cells to form a conductive stack structure at each cell; and forming a spacer layer on sidewalls of the conductive stack structure.