Patent ID: 7236117
Filing Date: 2007-06-26
Classification: H03M

Abstract:
1. A circuit for mismatch correction, comprising: a sample-and-hold logic control circuit that is arranged to provide a ping/pong select signal such that the ping/pong select signal corresponds to a first logic level during ping phases and corresponds to a second logic level during pong phases, and further arranged to provide a plurality of switch control signals, wherein the sample-and-hold logic circuit alternates between the ping phases and the pong phases during a normal operation; a ping-pong sample-and-hold circuit that includes a ping data path and a pong data path, wherein the ping-pong sample-and-hold circuit is arranged to provide a sampled image signal, based, in part, on a sample-and-hold input signal and the plurality of switch control signals such that the ping data path is employed during the ping phases and the pong data path is employed during the pong phases; an analog-to-digital converter circuit that is arranged to provide a digital image signal from a conversion input signal that is based, in part, on the sampled image signal; a digital adjustment circuit that is arranged to provide a digital output signal from the digital image signal by providing an offset and a gain to the digital image signal such that the offset is based on an offset control signal, and the gain is based on a gain control signal; and a ping-pong mismatch correction circuit that is arranged to provide the offset control signal and the gain control signal, based, in part, on the ping/pong select signal, a gain value, and an offset value; and further arranged to determine the gain value and the offset value during a calibration phase such that, during the normal operation the digital output signal is substantially corrected for a mismatch between the ping and pong data paths.