Patent ID: 8451965
Filing Date: 2013-05-28
Classification: H03L,H04L

Abstract:
1. A semiconductor integrated device comprising: a digitally controlled oscillator configured to generate an oscillation signal having a frequency depending on a first digital signal; a counter configured to count the number of pulses of the oscillation signal to output a counted value as a second digital signal in synchronization with a reference signal; a time to digital converter configured to generate a third digital signal corresponding to a phase difference between the oscillation signal and the reference signal; an adder configured to generate a fourth digital signal by adding the second digital signal to the third digital signal; and a control signal generator configured to generate the first digital signal based on a value obtained by accumulating a frequency command word in synchronization with the reference signal and the fourth digital signal in such a manner that the frequency of the oscillation signal approaches a predetermined frequency, wherein the time to digital converter is configured to comprise: a frequency-divider configured to frequency-divide the oscillation signal to generate a plurality of frequency-divided signals; a plurality of impedance elements configured to voltage-divide the frequency-divided signals to generate a plurality of delay signals of the oscillation signal; and a phase difference detector configured to output the third digital signal corresponding to the phase difference between the reference signal and the oscillation signal by comparing the reference signal with each of the delay signals.