Patent ID: 6558977
Filing Date: 2003-05-06
Classification: H01L,Y10S

Abstract:
A method for fabricating a semiconductor device comprising a first semiconductor chip and a second semiconductor chip mounted on the first semiconductor chip with respective electrodes of the first and second semiconductor chips being electrically connected to each other, the method comprising the steps of:preparing a wafer including first semiconductor chip formation regions each having a first electrode disposed on an upper surface thereof to form the first semiconductor chip and a second semiconductor chip having a second electrode disposed on an upper surface thereof; mounting the second semiconductor chip on each of the chip formation regions of the wafer and providing electrical connection between the first and second electrodes; forming a resin layer between each of the chip formation regions of the wafer and the second semiconductor chip; polishing a lower surface of the second semiconductor chip with the second semiconductor chip being mounted on the wafer; separating the wafer into the individual chip formation regions and individually forming bonded structures each composed of the second semiconductor chip mounted on the first semiconductor chip; and sealing the second semiconductor chip on the first semiconductor chip with a sealing resin.