Patent ID: 6515894
Filing Date: 2003-02-04
Classification: G06F,G11C

Abstract:
A semiconductor circuit comprising:a first memory block having a plurality of first memory cells coupled to a plurality of first bit lines extending in a first direction; a second memory block having a plurality of second memory cells coupled to a plurality of second bit lines extending in said first direction; a first and second wiring line each extending in said first direction and each laid across said first and second memory blocks; a plurality of first switches coupled between said first wiring line and each of said plurality of first bit lines; a plurality of second switches coupled between said first wiring line and each of said plurality of second bit lines; a plurality of third switches coupled between said second wiring line and each of said plurality of first bit lines; a plurality of fourth switches coupled between said second wiring line and each of said plurality of second bit lines; and a precharge circuit coupled to said first wiring line, wherein said first and second wiring lines are formed on a different layer than said plurality of first and second bit lines.