Patent ID: 9099555
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A tunnel field effect transistor comprising: a channel made of an intrinsic semi-conductor material; source and drain extension regions on either side of said channel, in contact with the intrinsic semi-conductor material of said channel, said source extension region being made of a semi-conductor material doped according to a first type of P or N doping and said drain extension region being made of a semi-conductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions and extending respectively above the source and drain extension regions; a gate structure surmounting said channel and laid out such that an end of said channel is not covered by the gate structure on the side of the source extension region, said gate structure comprising: a drain isolating arrangement for forming a drain isolating space between the respective sides of said gate structure and said drain conductive region opposite each other; a source isolating arrangement for forming a source isolating space between the respective sides of said gate structure and said source conductive region opposite each other, said source isolating arrangement comprising a first and a second dielectric spacer each having a first and a second lateral face; wherein said source extension region has a thickness strictly greater than that of the channel such that said source extension region has an increased thickness opposite said gate dielectric layer; wherein the first face of said first spacer is in contact with the side of said gate zone followed by the side of said gate dielectric layer such that said first face covers the whole of the side of said dielectric layer; wherein the second face of said first spacer is in contact with the first face of said second spacer and extends along the side of the increased thickness of the source extension region; wherein the first spacer covers the upper surface of the end of said channel not covered by the gate structure and has a length strictly below 5 nm, said length being measured along the longitudinal direction of said channel.