Patent ID: 6878988
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. An electrically programmable nonvolatile memory array, comprising: a semiconductor substrate of first conductivity type; columns of spaced apart source/drain (S/D) regions defined on said semiconductor substrate; a channel region between said source/drain (S/D) regions; a first dielectric layer disposed on said source/drain (S/D) regions; columns of assistant gates stacked on said first dielectric layer, wherein each of said assistant gates has a top surface and sidewalls, wherein at least one end of each said columns of assistant gates partially overlaps with a doped pickup well formed in said semiconductor substrate, and wherein a bit line voltage is provided to said doped pickup well; a second dielectric layer comprising a charge-trapping layer uniformly disposed on said top surface and sidewalls of said assistant gate and disposed on said channel region, wherein said second dielectric layer produces a recessed trough between said source/drain (S/D) regions; and rows of word lines laid on said second dielectric layer, said rows of word lines intersecting said columns of assistant gates; wherein, when programming a memory cell defined by a specific row of said word lines of said electrically programmable non-volatile memory array, only two columns of said assistants gates next to said memory cell are biased to a voltage V