Patent ID: 6208184
Filing Date: 2001-03-27
Classification: G11B

Abstract:
A method of delaying a transition in a digital data stream fed to a write head of a storage device by a predetermined time interval when the transition occurs at a clock phase following the clock phase during which a preceding transition has occurred, for pre-compensating for intersymbol nonlinear interference effects produced when reading stored data, the method comprising the steps of:inputting the digital data stream and a clock signal to a first circuit;outputting, from the first circuit, a pair of digital data streams including a first digital data stream which has a first logic value when a transition of the input digital data stream occurs during a clock phase that is not successive to a clock phase during which a transition of the input digital data stream has occurred, and a second digital data stream which has the first logic value when a transition of the input digital data stream occurs during a clock phase following a clock phase during which a transition has occurred in the input digital data stream;feeding the first and second digital data streams and the clock signal to respective inputs of a second circuit; andoutputting, from the second circuit, an output digital data stream directed to the write head, in which transitions immediately following a preceding transition are delayed by the predetermined time interval, by sampling the first and second digital data streams with a first pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a different time interval and such that the difference between the different time intervals is equal to the predetermined time interval, and recombining the first and second digital data streams output from the pair of flip-flops through a logic XOR gate into the output digital data stream.