Patent ID: 6799217
Filing Date: 2004-09-28
Classification: G06F

Abstract:
An interconnect port configured to couple a plurality of nodes, each node including a plurality of processors, a memory system, and an interconnect chipset, the interconnect port comprising:a physical layer configured to either receive or transmit electrical signals; a signal protocol layer coupled to the physical layer and configured to define a relationship with either the received or the transmitted electrical signal; a command protocol layer coupled to the signal protocol layer and configured to generate either a request for data in response to the received electrical signal or a reply in response to preparing the transmitted electrical signal; and a coherence protocol layer coupled to the command protocol layer and configured to provide a set of legal transactions for data in response to either the request for data or the reply, wherein the physical layer, the signal protocol layer and the command protocol layer are symmetrical and the coherence protocol layer is asymmetrical.