Patent ID: 7089437
Filing Date: 2006-08-08
Classification: G06F,Y02D

Abstract:
1. Apparatus for measuring the power consumed by a digital signal processor bus during a selected clock cycles, the apparatus comprising: a unit for counting the logic state transitions on the bus during the selected clock cycles; a technique for determining the power consumption on the bus for each logic state transitions, wherein the bus power consumption is determined by the number of logic state transitions multiplied by the power consumption for each logic state transitions; the unit including a plurality of transition detection circuits, each transition detection circuit coupled to one of the bus conductors; a storage component, the storage component storing on the output terminal a first signal representative of a logic state of the coupled bus conductor; a delay component coupled to the output terminal of the storage unit, the output terminal of the delay component storing a delayed signal, the delayed signal being the first signal delayed by a clock cycle; and a difference component coupled to the output terminal of the storage component and the output terminal of the delay component, the difference component generating a result signal when the first signal and the delayed signal are different.