Patent ID: 6353332
Filing Date: 2002-03-05
Classification: G11C

Abstract:
A method for implementing a content addressable memory function using a dual-port random-access memory (RAM) circuit, the dual-port RAM including an array of memory cells arranged in a plurality of columns and a plurality of rows, the method comprising:storing a plurality of decoded â€œone hotâ€  data words in the array of memory cells such that each decoded â€œone hotâ€  data word is stored in an associated column of said memory cells; performing a data match operation by reading a selected row of the plurality of rows in response to an applied match data value, wherein each memory cell of the selected row contains a data bit value from one of the plurality of â€œone hotâ€  data words; and generating a match signal if any of the bit values stored in the selected row includes a logic â€œ1â€  bit value.