Patent ID: 8148206
Filing Date: 2012-04-03
Classification: H01L

Abstract:
1. A method for packaging an integrated circuit, the method comprising: providing a ground plane, the ground plane having a first side, the first side having a recessed area shaped to receive an integrated circuit die, and a second side opposite the first side, wherein the integrated circuit die having a first surface with active circuitry, a second surface, and an edge generally orthogonal to the first and second surfaces; attaching the second surface of the integrated circuit die to the recessed area; filling a space between the edge of the integrated circuit die and the first side of the ground plane with a fill material; forming an encapsulant layer at least partially over the second side of the ground plane; forming a first insulating layer on the first side of the ground plane and the first surface of the integrated circuit die; patterning the first insulating layer to expose contacts on the first surface of the integrated circuit die; and plating electrical conductors on the first insulating layer and the contacts.