Patent ID: 8168521
Filing Date: 2012-05-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a first recess in a substrate; forming a gate insulation layer in the first recess; forming a barrier layer on the gate insulation layer; forming a preliminary nucleation layer having a first resistance on the barrier layer; changing the preliminary nucleation layer to a nucleation layer having a second resistance that is less than the first resistance; forming a conductive layer on the nucleation layer; and partially etching the conductive layer, the nucleation layer, the barrier layer and the gate insulation layer to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern, wherein the preliminary nucleation layer includes tungsten having a β crystalline phase and the nucleation layer includes tungsten having an α crystalline phase.