Patent ID: 6551890
Filing Date: 2003-04-22
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor having only two capacitor electrodes, whereina first layer of polycrystalline silicon is deposited on a surface of a semiconductor body, in which first layer of polycrystalline silicon there is formed a first pattern of conductors with a base electrode and a first capacitor electrode, and in which also an emitter window is etched, which is situated within the base electrode, wherein the base region of the transistor in the semiconductor body is formed from an edge of the base electrode adjoining the emitter window, by implantation of ions through the emitter window and by diffusion of a dopant, a second layer of polycrystalline silicon is deposited wherein a second pattern of conductors is formed with an emitter electrode and a second capacitor electrode, and the emitter region of the transistor in the base region is formed from the emitter electrode by diffusion of a dopant, characterized in that after deposition of the first layer of polycrystalline silicon on the surface of the semiconductor body, a first layer of an insulating material is deposited on this layer, whereafter both the first pattern of conductors and the emitter window are simultaneously etched in both layers, after which the side faces of the conductors and the wall of the emitter window are simultaneously provided with a layer of an insulating material by depositing a second layer of an insulating material and anisotropically etching this layer until parts thereof extending parallel to the surface have been removed and discontinuing said anisotropically etching prior to any conductive layers beneath the second layer of insulating material being etched.