Patent ID: 6526490
Filing Date: 2003-02-25
Classification: G06F

Abstract:
A processing system comprising: a memory having a plurality of locations; a processor, said processor being connected with said memory and including a memory map identifying locations within said memory at which specified data are stored, wherein said memory map is arranged such that data associated with an application are stored at the same location every time an application is run, and wherein said processor is arranged to run each application during specified processing time slots; and a monitor, said monitor containing information as to locations in said memory where data associated with each application are stored and containing information as to the time slots during which said processor should be running each application, wherein said monitor is connected such as to receive signals indicative of memory locations being addressed and application being run, and wherein said monitor is arranged to check whether the correct memory locations are being addressed and whether the correct application is being run in a given time slot.