Patent ID: 6048799
Filing Date: 2000-04-11
Classification: B82Y,G03F,H01L

Abstract:
A process for fabricating a semiconductor device, comprising the steps of:forming a layer of planarization material on a topographic substrate surface wherein the planarization material has a viscosity of about 20 cp (centipoise) to about 40,000 cp during planarization;at least partially solidifying a first area of the layer of planarization material wherein the first area is proximate to the perimeter of the layer of planarization material and substantially surrounds a second area of the layer of planarization material;contacting the layer of planarization material with a flat surface of an object with sufficient force to substantially transfer the surface flatness from the flat surface of the object to the layer of planarization material wherein the planarization material in the first area is sufficiently solidified to substantially confine the planarization material in the second area throughout the height of the planarization material in the first area when the object with the flat surface is placed in contact therewith;solidifying the layer of planarization material while in contact with the flat surface of the object wherein the planarization material undergoes a reduction in volume of less than about 10%; andseparating the flat surface of the object from contact with the layer of planarization material.