Patent ID: 6912699
Filing Date: 2005-06-28
Classification: H01L

Abstract:
1. A testing design for flip chip connection process, comprising: a substrate; a plurality of connections, formed on said substrate; at least one integrated device having a first surface and an opposite second surface; a plurality of first type of bumps adapted for transferring testing signals, formed on the second surface of said at least one integrated device; and a plurality of second type of bumps adapted for transferring display signals, formed on the second surface of said at least one integrated device and spatially separated from said plurality of first type of bumps, wherein said plurality of first type of bumps and said plurality of second type of bumps, in operation, are located between the second surface of said at least one integrated device and said substrate such that at least one of said plurality of first type of bumps is electrically connected to two neighboring connections of said plurality of connections to form an electrical channel for testing for flip chip connection process; and wherein in operation, a testing signal passes from one of the two neighboring connections through said at least one integrated device to the other of the two neighboring connections.