Patent ID: 6721211
Filing Date: 2004-04-13
Classification: G11C,H02M

Abstract:
A voltage generator for semiconductor memory device, comprising:an output voltage controller to generate a pull-up signal for a pull-up operation and a pull-down signal for controlling a pull-down operation, the pull-up signal having a level substantially equivalent to an internal power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, and a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage; and an output driver to generate a stable cell plate voltage in response to the pull-up signal and the pull-down signal; wherein the output voltage controller comprises: a voltage divider to divide the internal power supply voltage and generate the cell plate reference voltage; a bias voltage generator to receive the cell plate reference voltage and to generate a p-bias voltage and an n-bias voltage; a gate voltage generator to receive the cell plate reference voltage, the p-bias voltage and the n-bias voltage, and to generate a p-gate voltage and an n-gate voltage; a pull-up controller to receive the cell plate reference voltage, the p-bias voltage, the n-bias voltage and the cell plate voltage, and to generate the pull-up signal: and a pull-down controller to receive the n-bias voltage, the n-bias voltage, the p-gate voltage, the n-gate voltage and the cell plate voltage, and to generate the pull-down signal.