Patent ID: 7026714
Filing Date: 2006-04-11
Classification: H01L

Abstract:
1. An integrated circuit comprising: a substrate; a first dielectric layer adjacent said substrate; at least one trench in said first dielectric layer; a liner comprising metal within said at least one trench; a first conductive region comprising copper within said at least one trench; a cap layer comprising metal on said first conductive region; a second dielectric layer over said first conductive region and said cap layer; a dielectric etch stop and diffusion barrier layer over said second dielectric layer; a via over said first conductive region and through said second dielectric layer and said cap layer; a diffusion barrier layer on sidewalls of said via; an alloy seed layer comprising copper and at least one of tantalum, molybdenum, chromium, and tungsten over said diffusion barrier, said alloy seed layer also over said dielectric etch stop and diffusion barrier layer, said alloy seed layer in contact with said first conductive region; and a second conductive region comprising copper over said alloy seed layer.