Patent ID: 7482849
Filing Date: 2009-01-27
Classification: H03K

Abstract:
1. A clock signal synchronizing device to be used with a synchronization of clock signals, comprising: a first delay means with a variably controllable delay time, in which a clock signal or a signal obtained therefrom is input, is loaded with the variably controllable delay time, and is output as a delayed clock signal; a second delay means with a first constant delay time, the first constant delay time chosen based on a delay caused during evaluation of control signals by an evaluating means; and a phase comparator for comparing a phase of the clock signal or of the signal obtained therefrom with a phase of the delayed clock signal or of a signal obtained therefrom, wherein additionally a means is provided for activating and/or deactivating said clock signal synchronizing device as a function of the control signals evaluated by the evaluating means.