Patent ID: 7082074
Filing Date: 2006-07-25
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first memory bank including a plurality of first memory cell arrays each of which has a plurality of first memory cells at intersections of a plurality of first word lines and a plurality of first data lines and a plurality of first sense amplifiers which are coupled to the plurality of first data lines; a second memory bank including a plurality of second memory cell arrays each of which has a plurality of second memory cells at intersections of a plurality of second word lines and a plurality of second data lines and a plurality of second sense amplifiers which are coupled to the plurality of second data lines; and a voltage generator including a first voltage limiter corresponding to the first memory bank and a second voltage limiter corresponding to the second memory bank, wherein the first and second voltage limiters each receive a first voltage and generate a second voltage smaller than the first voltage, wherein the plurality of first and second sense amplifiers are supplied with the second voltage from the voltage generator, wherein a drivabiity of the voltage generator is raised by controlling the first voltage limiter when a first bank active command indicating an activation of the first memory bank is inputted, and then the drivability of the voltage generator is lowered after a predetermined term passes, and wherein the drivability of the voltage generator is raised by controlling the second voltage limiter when a second bank active command indicating an activation of the second memory bank is inputted, and then the drivability of the voltage generator is lowered after a predetermined term passes.