Patent ID: 6446146
Filing Date: 2002-09-03
Classification: G06F,H04J,H04L

Abstract:
A line terminator, which terminates plural lines, each having a different line speed, comprising:a clock generator for the plural lines for generating clock signals, each corresponding to each line speed; a line switching circuit for specifying one of the plural lines; a selector for outputting data of one of the plural lines, which is specified by the line switching circuit; and a common processing circuit commonly provided for the plural lines respectively having different line speeds for processing data of the one line output from the selector, according to a clock corresponding to the line speed generated in the clock generator, wherein the common processing circuit extracts an over head of the data of the one line output from the selector according to the clock corresponding to the speed of the one line, and further includes: an interface section having an area for storing monitored information in the extracted overhead in the corresponding address corresponding to the status of the monitored information, and a firmware for collecting the monitored information stored in the interface section.