Patent ID: 6235564
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method of manufacturing a MISFET; comprising the steps of:(a) preparing a semiconductor substrate;(b) forming a gate insulation film on a surface of said semiconductor substrate;(c) forming a dummy gate on and in contact with a surface of said gate insulation film;(d) implanting an impurity into said semiconductor substrate in a self-aligned manner, using said dummy gate as a mask;(e) forming an interlayer insulation film covering said dummy gate to cover the surface of said semiconductor substrate entirely;(f) reducing the thickness of said interlayer insulation film to expose a top surface of said dummy gate;(g) removing said dummy gate, with said interlayer insulation film and said gate insulation film unremoved; and(h) forming a gate electrode on and in contact with said surface of said gate insulation film in a space created by the removal of said dummy gate.