Patent ID: 8436663
Filing Date: 2013-05-07
Classification: H03K

Abstract:
1. A circuit, comprising: a first E-mode transistor and a second E-mode transistor each having a source, a drain, a gate that controls a channel between the source and the drain, and a gate-source junction, wherein each E-mode transistor conducts between the source and the drain if a gate-source voltage that is applied between the gate and the source is more positive than a positive threshold voltage, and does not conduct between the source and the drain otherwise, a first D-mode transistor and a second D-mode transistor each having a source, a drain, a gate that controls a channel between the source and the drain, and a gate-source junction, wherein each D-mode transistor does not conduct between the source and the drain if a gate-source voltage that is applied between the gate and the source is more negative than a negative threshold voltage, and conducts between the source and the drain otherwise, a component that generates a voltage drop connected between the drain of the second E-mode transistor and the source of the second D-mode transistor, wherein the drain of the first E-mode transistor is connected to the source of the first D-mode transistor, wherein a feedback connection connects the drain of the second E-mode transistor to the gate of the second D-mode transistor, wherein the gate of the second D-mode transistor is connected to the gate of the first D-mode transistor, wherein the sources of the first and second E-mode transistors are coupled to a first voltage level supply voltage node, wherein the drains of the first and second D-mode transistors are coupled to a second voltage level supply voltage node, wherein the gate of the first E-mode transistor is coupled to an input signal node, and wherein the drain of the second E-mode transistor is coupled to an output signal node.