Patent ID: 6504411
Filing Date: 2003-01-07
Classification: H03K

Abstract:
A redundant latch circuit resistant to single event upsets (SEUs) and comprising:a plurality of latches, each latch having a set input for receiving a respective redundant set signal, a reset input for receiving a respective redundant reset signal, and an output indicating a set or reset state of a respective latch; a majority voting circuit having inputs connected to the outputs of said latches, and an output indicating a set state for the redundant latch circuit based upon a majority of said latches being in the set state and indicating a reset state otherwise; and a feedback reset circuit having inputs connected to the outputs of said latches, and outputs connected to the reset inputs of said latches for switching at least one latch back to the reset state from an SEU-induced change to the set state when at least one other latch remains in the reset state to thereby provide resistance to SEUs.