Patent ID: 6324113
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:a pair of memory cores each having a plurality of memory cells including capacitors and both storing data supplied corresponding to a write command, said data being identical to each other;a refresh signal generating circuit for generating a refresh signal for retaining said data written in said memory cells;a refresh controlling circuit for supplying said refresh signal to one of said memory cores and operating the memory core as a refresh core to perform refresh and write operations; anda read controlling circuit for supplying a read signal for reading said data from said memory cells, to another one of said memory cores not supplied with said refresh signal and operating the memory core as a read core to perform read and write operations, whereinwrite cycle time as an operation specification is set to be longer than the actual time required for each of said memory cores to perform the write operation.