Patent ID: 7880494
Filing Date: 2011-02-01
Classification: G01R,H01L

Abstract:
1. A method of measuring parasitic capacitance in a semiconductor, said method comprising: providing a first test structure comprising a first conductive comb structure and a second conductive comb structure complementary to the first comb, each of said first and second conductive comb structures being formed in a first interconnect layer, and a third conductive comb structure and a fourth conductive comb structure complementary to the third comb, each said third and fourth conductive comb structures being formed in a second interconnect layer; applying a first bias to the first and the fourth conductive comb structures, and a second bias to the second and the third conductive comb structures; measuring a first capacitance on said first test structure between said first bias and said second bias; providing a second test structure comprising a fifth conductive comb structure and a sixth conductive comb structure complementary to the fifth conductive comb structure, both being formed in the first interconnect layer, and a seventh conductive comb structure and an eighth conductive comb structure complementary to the seventh conductive comb structure, both being formed in the second interconnect layer; applying the first bias to the fifth and the eight conductive comb structures, and the second bias to the sixth and the seventh conductive comb structures; measuring a second capacitance on the second test structure between the first bias and the second bias; and calculating a parasitic capacitance C