Patent ID: 7741865
Filing Date: 2010-06-22
Classification: H03K

Abstract:
1. A programmable logic device (PLD) comprising: a plurality of configuration memory cells adapted to store configuration data bits of a user design, each cell having at least one input node to receive a configuration bit and Q and QN output nodes to provide the configuration bit; a plurality of address lines coupled to the configuration memory cells; a plurality of bitlines coupled to the input nodes of the configuration memory cells; logic circuitry coupled to the address lines and the bitlines of the memory cell array and adapted to select between a soft error upset (SEU)-hardened mode and a programmable mode for the memory cells, the logic circuitry adapted to force the address lines and bitlines to predetermined logical values in the SEU-hardened mode, wherein the address lines and bitlines force the Q and QN output nodes of each memory cell to predetermined logical values; and a mask programmable connection associated with each memory cell for connecting one of the Q and ON output nodes of the cell to configurable resources of the PLD, wherein in the SEU-hardened mode and with the mask programmable connections programmed, the memory cells provide configuration data bits having the predetermined logical values of the connected Q and QN output nodes to the configurable resources.