Patent ID: 6754123
Filing Date: 2004-06-22
Classification: G11C

Abstract:
A sensing circuit for determining the logic state of a memory cell in a resistive memory array wherein each memory cell has current control isolation, the logic state of the memory cell being determined relative to a reference cell having a pre-selected logic state, comprising:(a) a memory cell sensing circuit adapted to determine a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and to determine a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell, (b) a reference cell sensing circuit adapted to determine a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and to determine a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell, (c) an isolation circuit for applying an isolation voltage to turn off a current control element associated with each unselected memory cell, the isolation voltage being applied so as to reverse bias the current control element when the first bias voltage and the second bias voltage are applied to the memory cell and the reference cell, (d) an adjusting circuit for modifying at least one of (i) the first memory cell voltage and (ii) the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage at the first bias voltage, and (e) a state determining circuit for determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell at the second bias voltage.