Patent ID: 7927782
Filing Date: 2011-04-19
Classification: G03F,H01L,Y10T

Abstract:
1. A method of fabricating an integrated circuit chip including random logic circuits, comprising: providing a semiconductor substrate defining a first active region of a first random logic cell separated by an intervening border region from a second active region of a second random logic cell; forming a layer of gate electrode material over the first active region, the second active region and the border region; forming a layer of hard mask material over the layer of gate electrode material; forming a first layer of photoresist material over the layer of hard mask material; patterning the first layer of photoresist material by selective exposure through a first mask to define a gate electrode line pattern; selectively etching the layer of hard mask material using the gate electrode pattern, resulting in formation of at least three elongated gate electrode structures, the elongation of each gate electrode extending in a direction across the first active region, the intervening border region and the second active region; removing the patterned first layer of photoresist material; forming a second layer of photoresist material over the layer of hard mask material; patterning the second layer of photoresist material by selective exposure through a second mask to define a trim pattern; selectively etching the layer of hard mask material using the trim pattern, resulting in formation of a space extending transversely to the direction of elongation and removing portions of the gate electrode structures extending across the border region, to provide a composite pattern that redefines the gate electrode structures into distinct sets of gate electrodes, a first set extending across the first active region and terminating in a border region extension directed toward the second cell and a second set extending across the second active region and terminating in a border region extension directed toward the first cell; and transferring the composite pattern to the layer of gate electrode material.