Patent ID: 9147078
Filing Date: 2015-09-29
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a processing unit including a plurality of hardware components including a plurality of memory elements collectively storing an architected state for the processing unit; security logic disposed in the processing unit and configured to perform at least one secure clear operation that restricts access to data stored in at least a subset of the plurality of memory elements; and an instruction unit disposed in the processing unit and configured to decode instructions from at least one instruction stream and associated with an instruction set architecture, wherein the instruction set architecture defines a secure clear instruction that targets at least one memory element in the processing unit, and wherein the instruction unit is configured to, in response to receiving the secure clear instruction in an instruction stream in connection with performing a context switch from an outgoing context to an incoming context, decode the secure clear instruction and cause the security logic to perform the secure clear operation to restrict access, by program code associated with the incoming context, to data stored in the at least one memory element during execution of program code associated with the outgoing context, wherein the at least one memory element stores residual internal architected state information of the processing unit for the outgoing context that is not overwritten when restoring the incoming context, wherein the secure clear operation restricts access by the program code to the residual internal architected state information of the processing unit for the outgoing context, wherein the secure clear instruction is associated with program code having a first privilege, and wherein the secure clear operation is configured to clear an address translation data structure by overwriting any entries in the address translation data structure not associated with the first privilege.