Patent ID: 6049894
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A method, comprising the steps of:(a) on an integrated circuit of a first device, receiving signals of a bus cycle on a parallel bus, said parallel bus being coupled to said integrated circuit, wherein said signals comprise bus data and a correct parity data, said correct parity data corresponding to said bus data;(b) on said integrated circuit, simulating receipt of a bus error condition when there is no actual bus error condition on said parallel bus, wherein said step of simulating receipt of a bus error condition comprises the steps of receiving said correct parity data and generating an incorrect parity data based on said correct parity data;(c) detecting said simulated bus error condition on said integrated circuit in response to said incorrect parity data, and asserting a signal on said parallel bus indicative of said simulated bus error condition; and(d) setting a bit of a status register in said integrated circuit of said first device to log said simulated bus error condition.