Patent ID: 6240012
Filing Date: 2001-05-29
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array comprising memory cell units arranged in an array form, said memory cell units each comprising at least one memory cell and at least one selection transistor;at least one selection gate line formed by continuously extending the gates of said selection transistors; andat least one control gate line formed by continuously extending the gates of said memory cells;a row decoder for selecting said at least one selection gate line and said at least one control gate line to control the potentials thereof, said row decoder comprising transistors;at least one first wiring each for connecting corresponding one of said at least one control gate line to a corresponding one of said transistors in said row decoder, respectively; andat least one second wiring each for connecting corresponding one of said at least one selection gate line to a corresponding one of said transistors in said row decoder,wherein said at least one first wiring is different in structure from said at least one second wiring.