Patent ID: 6417708
Filing Date: 2002-07-09
Classification: H03K,H04L

Abstract:
A differential output buffer comprising:logic high and logic low voltage supply terminals; first and second complementary data inputs; a differential output stage comprising first and second differential data outputs and first and second output stage control inputs; first and second adjustable controlled current sources; a first push-pull circuit biased between the logic high and logic low voltage supply terminals and having first and second inputs coupled to the first and second data inputs and an output coupled to the first output stage control input, wherein the output of the first push-pull circuit has a rise time controlled by the the first controlled current source and a fall time controlled by the second controlled current source; and a second push-pull circuit biased between the logic high and logic low voltage supply terminals and having first and second inputs coupled to the first and second data inputs and an output coupled to the second output stage control input, wherein the output of the second push-pull circuit has a rise time controlled by the first controlled current source and a fall time controlled by the second controlled current source.