Patent ID: 6214671
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method of forming a dual gate, comprising the steps of:providing a substrate with an isolation structure therein;forming a first well with a first conductive type and a second well with a second conductive type in the substrate, wherein the first well and the second well are isolated from each other by the isolation structure;forming a gate oxide layer on the substrate;forming a doped polysilicon layer on the gate oxide layer;doping a part of the doped polysilicon layer positioned on the first well to make a doped polysilicon layer with the first conductive type;doping the doped polysilicon layer positioned on the second well to make a doped polysilicon layer with the second conductive type;forming an undoped polysilicon layer to form a first gate on the first well and to form a second gate on the second well, wherein the first gate comprises the doped polysilicon layer with the first conductive type and the second gate comprises the doped polysilicon layer with the second conductive type;forming a first oxide layer on a top surface of the undoped polysilicon layer by thermally oxidizing the undoped polysilicon layer;forming a second oxide layer over the substrate and covering the first oxide layer;etching back the second oxide layer and the first oxide layer to form spacers on the sidewalls of the first gate and of the second gate and to expose the undoped polysilicon layer;and forming a silicide layer on the exposed, undoped polysilicon layer.removing an exposed portion of the gate oxide layers and forming a silicide layer on the exposed, undoped polysilicon layer.