Patent ID: 6697909
Filing Date: 2004-02-24
Classification: G06F,G11C

Abstract:
A method for refreshing data in a cache memory, comprising the steps of:verifying a request address received from a processor using TAG addresses associated with the cache memory, said cache memory comprising a plurality of memory sub-arrays; and if the request address is verified, accessing a wordline corresponding to the request address in one of the plurality of sub-arrays of the cache memory to perform a data access operation; and generating refresh addresses for performing a refresh operation to refresh data stored in each of the sub-arrays other than the one sub-array in which said data access operation is performed, wherein each of the refresh addresses addresses a wordline in a corresponding one of the plurality of sub-arrays other than the one sub-array in which said data access operation is performed and wherein each of the refresh addresses includes a priority indicator representing priority of replacement of data corresponding to that refresh address, and a wordline address to address a wordline in a corresponding sub-array of the cache memory.