Patent ID: 8938575
Filing Date: 2015-01-20
Classification: G06F,G11C

Abstract:
1. A multi-state memory system with minimized half-select currents, the system comprising: a plurality of arrays of row conductors and column conductors; a plurality of storage cells each capable of being placed into any of three or more physical states, each storage cell connected between a different combination of a row conductor and a column conductor; and an encoder connected to receive data bits for storage and to apply activation signals m the row conductors and column conductors to write information to the storage cells, the encoder programmed to: encode the data bits entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; apply a predetermined one-dimensional one-to-one mapping that increases the value of at most one entry in the array according to half-select currents of the storage cells to obtain a mapped array; and write entries of the mapped array into the storage cells.