Patent ID: 6524903
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising steps of:(a) introducing an impurity to a semiconductor substrate to form a first impurity layer of a first conductivity type having a first peak in impurity concentration distribution; (b) introducing another impurity into the semiconductor substrate to form a second impurity layer of the first conductivity type having a second peak in impurity concentration distribution; (c) after formation of a gate electrode of an MISFET, forming source and drain extension regions of a second conductivity type in the semiconductor substrate; and (d) after formation of side wall spacers on the side walls of the gate electrode, forming source and drain diffusion regions of the second conductivity type of the MISFET in the semiconductor substrate, wherein the first peak exists in a region shallower than a junction depth of the source and drain diffusion regions, wherein in the step (b), the second peak is formed to exist in a region deeper than a channel region of the MISFET and shallower than the first peak such that an impurity concentration of the channel region is less than that of the second peak, and wherein the mass of impurity constituting the second impurity layer is greater than the mass of impurity constituting the semiconductor substrate.