Patent ID: 6700142
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A method for manufacturing a semiconductor wafer having a predetermined global functionality, comprising:a) fabricating an integrated circuit on a body of semiconductor material having a top surface, a bottom surface and a peripheral edge between said top surface and said bottom surface, said integrated circuit including: i) a working set of discrete functional modules, the discrete functional modules in said working set being of generally identical dimensions and being arranged into a rectangular array of rows and columns, said rectangular array having a boundary including four corners, said rectangular array having a discrete functional module at each one of said four corners; ii) a space being defined between each corner and said peripheral edge, each space being insufficient to accommodate a discrete functional module between the corner and the periphery in a rectangular arrangement with the discrete functional module at the corner of said rectangular array; iii) a spare set of discrete functional modules formed between said boundary and said peripheral edge; b) testing the discrete functional modules in said working set; c) if the testing determines that all the discrete functional modules in said working set are operational, then completing the manufacturing of said semiconductor wafer such that only the discrete functional modules in said working set provide said predetermined global functionality; and d) if the testing reveals that one or more discrete functional modules in said working set are defective, then functionally replacing the defective discrete functional modules in said working set with a corresponding number of discrete functional modules in said spare set to provide said predetermined global functionality.