Patent ID: 6094730
Filing Date: 2000-07-25
Classification: G06F

Abstract:
A test and diagnosis system for testing an embedded microprocessor of a product under test, comprising:an ASIC, wherein the ASIC includes both the embedded microprocessor of the product under test and a debug assist logic means, the debug assist logic means for monitoring information from the embedded microprocessor of the product under test, the debug assist logic means electrically coupled to the embedded microprocessor of the product under test and including a plurality of storage means, the plurality of storage means including at least a first storage set means for storing a control set of match conditions, wherein responsive to a match of monitored information and the conditions set in the control set, the debug assist logic means generates an interrupt to the embedded microprocessor of the product under test; anddebug software stored on a first memory means, the first memory means electrically coupled to the embedded processor of the product under test.