Patent ID: 6204689
Filing Date: 2001-03-20
Classification: H03K

Abstract:
A programmable logic device comprising:an array of configurable logic elements (CLES) arranged in rows and columns;a first set of long lines extending along a column of CLEs in a regular pattern;a first set of intermediate-length buses extending along the column of CLEs in a regular pattern;a first set of programmable interconnection points (PIPs) for coupling the intermediate length buses to CLEs in the column of CLEs in a regular pattern;a second set of PIPs for coupling the long lines to the intermediate length buses in a regular pattern; anda third set of PIPs located at a first edge of the column of CLEs, wherein the third set of PIPs programmably couples the long lines to the intermediate length buses at the first edge, and wherein the regular pattern of connections between the long lines and the intermediate length buses is maintained by the third set of PIPs.