Patent ID: 6329853
Filing Date: 2001-12-11
Classification: H03L

Abstract:
A PLL circuit comprising an oscillation circuit having a PLL loop including a charge pump circuit coupled between a voltage controlled oscillation circuit, and a phase comparing circuit which receives an external clock signal and compares phases of an output signal of the voltage controlled oscillation circuit and the received clock signal, the PLL loop generates a control voltage for the voltage controlled oscillation circuit depending upon a phase comparison result of the phase comparing circuit and generates an output signal of a specified frequency which is locked to a frequency of the clock signal; and a boost-up circuit which receives the clock signal and the output signal to generate a control signal to said charge pump circuit that causes the control voltage to shift in a direction that the voltage controlled oscillation circuit oscillates at the specified frequency in response to when the frequency of the output signal assumes a lower limit value or less than that of a predetermined range including the specified frequency with respect thereto and further cause the control voltage to shift in the direction that the voltage controlled oscillation circuit oscillates at the specified frequency in response to when the frequency of the output signal assumes an upper limit value or more than that of the predetermined range and interrupts shifting of the control voltage when the frequency of the output signal is in the predetermined range, whereby a ringing of the frequency of the output signal when the PLL circuit is started, is suppressed.