Patent ID: 6536008
Filing Date: 2003-03-18
Classification: G01R

Abstract:
A fault injection circuit for use in injecting a fault at the primary output of a boundary scan cell in an integrated circuit, said boundary scan cell having at least one primary input, a primary output associated with each said at least one primary input, a shift register element, an update latch having an input connected to the output of said shift register element and a control input, and an output selector responsive to an output control input associated with each said primary output for selectively applying either said associated primary input or the output of said update latch to said output control input, comprising:a Fault Flag latch for storing a Fault Flag and having an input connected to the output of shift register element, an output for a Fault Flag signal and a control input responsive to an active control signal for loading the output of said shift register element into said Fault Flag latch; first logic means connected to the control input of each said Fault Flag latch and said update latch for controlling loading of data into said latches; second logic means associated with each said primary output and responsive to an active Fault Enable signal and the output of said Fault Flag latch for producing a fault inject signal and having an output connected to said control input of said output selector for applying said fault inject signal thereto; each said output selector being responsive to an active fault inject signal by applying the output of said update latch to its associated control input to thereby inject a fault stored in said update latch to its associated primary output and responsive to an inactive fault inject signal by connecting its associated primary input to its associated primary output.