Patent ID: 6455386
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of manufacturing integrated circuits including high and low voltage MOS transistors of same type, including the steps of:a) forming insulated gate structures; b) forming lightly-doped drain/source regions; c) depositing an insulating layer; d) forming a mask above the gates of the high voltage transistors after depositing the insulating layer, the mask extending laterally beyond said gates; e) etching the insulating layer, through openings in the mask, to leave spacers, formed from the insulating layer, on the edges of the low voltage transistor gates; f) implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and g) forming, in a self-aligned way, a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.