Patent ID: 6211023
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate having a gate structure comprising a gate oxide layer and a gate, the substrate being doped by a selected-type dopant, the method further comprising:forming an oxide liner spacer on each side of the gate structure;performing a first ion implantation process, using the gate structure as a mask, to form a base doped region deep inside the substrate on each side of the gate structure, wherein the base doped region comprises a first-type dopant with a first dopant density, in which the first type dopant is opposite to the selected-type dopant of the substrate;performing a second ion implantation process to form a lightly doped region on each side of the gate structure in the based doped region, wherein the lightly doped region comprises the first-type dopant with a second dopant density and wherein the lightly doped region includes a higher dopant density than the base doped region;performing a third ion implantation process to form an anti-punchthrough region between the base doped region and the lightly doped region in the substrate, wherein the anti-punchthrough region comprises a selected-type dopant with a third dopant density;forming a sidewall spacer on the oxide liner spacer, which is on each side of the gate structure; andperforming a forth ion implantation process, using the gate structure, the liner spacer, and the sidewall spacer as a mask, to form a heavily doped region abutting the lightly doped region, the anti-punch-through region, and the base doped region in order to serve together with the lightly doped region as an interchangeable source/drain region of the MOS transistor, wherein the heavily doped region comprises the first-type dopant with a fourth dopant density, wherein the heavily doped region includes a bottom that is separated from the substrate by the base doped region, and wherein the based doped region is disposed below the lightly doped region, the anti-punch through region, and the heavily doped region to reduce junction capacitance.