Patent ID: 6094378
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) comprising:an array of memory cells;an access transistor connected to one of the memory cells and digit line, such that the access device has a drain connected to the digit line, and a source connected to the one memory cell;a word line coupled to a gate connection of the access transistor;an n-channel enhancement mode transistor having a source connection, drain connection and a gate connection, the source connection is coupled to the digit line, and the drain is selectively coupled to either a write driver circuit or an I/O sense amplifier circuit; anda voltage boot circuit-connected to the gate of the n-channel enhancement mode transistor, the voltage boot circuit provides a signal having a voltage that is equal to at least an external DRAM supply voltage plus a threshold voltage of the n-channel enhancement mode transistor.