Patent ID: 8697557
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method, comprising: forming a gate electrode structure above a semiconducting substrate, the gate electrode structure comprising at least a gate insulation layer positioned above said substrate, a gate electrode positioned above said gate insulation layer, a first sidewall spacer positioned proximate said gate electrode, and a gate cap layer positioned on said gate electrode; forming an etch stop layer above said gate cap layer and above a surface of said substrate proximate said gate electrode structure; forming a layer of spacer material above said etch stop layer; performing a first planarization process to remove the portion of said layer of spacer material positioned above said gate electrode, the portion of said etch stop layer positioned above said gate electrode, and said gate cap layer so as to thereby expose an upper surface of said gate electrode; and after performing said first planarization process and exposing said upper surface of said gate electrode, performing a first anisotropic etching process on said layer of spacer material to define a second sidewall spacer while using said etch stop layer as an etch stop during said first etching process.