Patent ID: 6594179
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A floating gate type nonvolatile semiconductor memory having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, a plurality of word lines connected to said memory cells and a plurality of bit lines connected to said memory cells, wherein:said plurality of word lines are each connected to a row of gate electrodes of said memory cells with one voltage supplied from a cell drain voltage source exclusively connected to drain electrodes of either even-numbered memory cells or odd-numbered memory cells among said memory cells through a plurality of select lines in units of individual rows; another voltage supplied from said cell drain voltage source is connected to said plurality of bit lines sequentially via a data write circuit and a multiplexer circuit; and said bit lines are each connected to a row of source electrodes of said memory cells and at least two sets each constituted of a data write circuit and a multiplexer circuit are provided with at least one set connected to the ends of said plurality of bit lines on each side.