Patent ID: 6275437
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A semiconductor memory device having a refresh-type memory cell array, the device comprising:an address buffer to receive external address information and generate an internal address signal during a read/write operation;a write address register to store the internal address signal received by the address buffer during an external write operation, and output that stored internal address signal as a write address signal until a following external write operation;a refresh circuit to generate refresh operation requests and to generate a refresh address signal for refreshing the memory cells of the memory cell array during a refresh operation;a control circuit to generate an internal control signal, the internal control signal comprising a read selecting signal generated during a pulsed read operation, a write selecting signal generated during a pulsed write operation, and a refresh selecting signal generated during a refresh operation, and to generate a refresh blocking signal to disable refresh operation requests during an access subinterval of each external read/write operation during which the device performs the pulsed read or write operation;an address multiplexer to select one of the internal address signal, the write address signal and the refresh address signal as an array address signal, based on the internal control signal;row and column decoders to address one or more cells of the memory cell array based on the array address signal;a data input register to store data input information received during an external write operation until a following external write operation;a comparator to compare the internal address signal with the write address signal during a read operation; anda data output multiplexer to select either the data input information stored in the data input register, or data output from one or more cells of the memory cell array, based on an output signal of the comparator during a read operation, wherein the data output multiplexer selects the data input information stored in the data input register when the internal address signal matches the write address signal, and otherwise selects the data from the memory cells.