Patent ID: 6546529
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A method for determining and applying coupling guidelines across design hierarchies in an integrated circuit designed using a hierarchical design process, the method comprising:creating an overall flat wire routing map across design hierarchies of the integrated circuit designed using a hierarchical design process, wherein said integrated circuit includes a plurality of independently designed interconnected units; identifying coupled wire segments on the integrated circuit; tracing wire interconnection patterns on the integrated circuit from sources to receivers using said flat wire routing map; deriving electrical parameters for said coupled wire segments using said flat wire routing map and said wire interconnection patterns; generating a coupling guideline table containing coupling guideline parameters for a plurality of electrical parameters; applying said coupling guideline parameters to said electrical parameters for said coupled wire segments; and generating report data of said electrical parameters for said coupled wire segments that fail to comply with said coupling guideline parameters.