Patent ID: 6111811
Filing Date: 2000-08-29
Classification: G11C

Abstract:
In a synchronous semiconductor device that receives a system clock signal, an output buffer comprising:an output node;a first drive device that couples the output node to a first logic voltage in response to the potential at a first drive node;a second drive device that couples the output to a second logic voltage in response to the potential at a second drive node; anda first pre-drive circuit coupled to the first drive node, the first pre-drive circuit including,a first charge device having a first charge path and a first pre-drive node, the first charge device coupling the first drive node to a charge potential when the first pre-drive node is at an enable potential and providing a high impedance path between the first drive node and the charge potential when the first pre-drive node is at a disable potential, andat least one first enable device having a first enable path coupled between the first pre-drive node and an enable potential, the first enable device providing a low impedance first enable path when the system clock signal is at a first clock level, and a high impedance first enable path when the system clock signal is at a second clock level; andat least one first disable device having a first disable path coupled between the first pre-drive node and a disable potential, the first disable device providing a low impedance first disable path when the system clock signal is at the second clock level, and a high impedance first disable path when the system clock signal is at the first clock level.