Patent ID: 6483340
Filing Date: 2002-11-19
Classification: H03K

Abstract:
An output buffer circuit comprising:an output transistor section, said output transistor section comprising: an output terminal; a first transistor of a first conductive type of which one end of the source-drain line is connected to a high potential power supply and the other end thereof is connected to said output terminal; a second transistor of the first conductive type having a larger driving capability than that of said first transistor of the first conductive type and of which one end of the source-drain line is connected to the high potential power supply and the other end thereof is connected to said output terminal; a first transistor of a second conductive type of which one end of the source-drain line is connected to a low potential power supply and the other end thereof is connected to said output terminal; a second transistor of the second conductive type having a larger driving capability than that of said first transistor of the second conductive type and of which one end of the source-drain line is connected to a low potential power supply and the other end thereof is connected to said output terminal; a first logic gate including a first input terminal to which an input signal is inputted and a first driving output terminal to be connected to a gate of said first transistor of the first conductive type; a second logic gate including a second input terminal to which said input signal is inputted and a second driving output terminal to be connected to a gate of said first transistor of the second conductive type; a first switch circuit connected between the gate of said second transistor of the first conductive type and said second driving output terminal and including a first transfer gate so that conduction thereof is controlled by a control signal; and a second switch circuit connected between the gate of said second transistor of the second conductive type and said first driving output terminal and including a second transfer gate so that conduction thereof is controlled by a control signal.