Patent ID: 6134118
Filing Date: 2000-10-17
Classification: H01L,H01R,H05K,Y02P,Y10T

Abstract:
A semiconductor chip package, comprising:a substrate having a plurality of terminals;a semiconductor chip on said substrate, said semiconductor chip including;a plurality of bond pads,a first insulation layer covering said chip,a first plurality of holes in said first insulation layer exposing said bond pads,a metal layer deposited over said first insulation layer to form an electrical contact with said bond pads,a second insulation layer deposited over said metal layer, anda second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points such that said metal layer routes respective bond pads to corresponding external connection points; andelectrically conductive epoxy applied between said external connection points of said semiconductor chip and said terminals of said substrate, thereby electrically connecting said semiconductor chip to said substrate.