Patent ID: 6088257
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A ferroelectric random access memory device comprising:a substrate defined by a plurality of rows and columns;a plurality of word lines extending along the plurality of rows;a plurality of plate lines extending along the plurality of rows;a plurality of bit lines extending along the plurality of columns;a memory cell array having a plurality of memory cells arranged in a matrix form, each memory cell including a switch having a first, a second, and a control terminal and a capacitor having a first and a second electrode and a ferroelectric material inserted between the first and second electrodes, the first terminal of the switch being connected to a corresponding bit line of the plurality of bit lines, the second terminal of the switch being connected to the first electrode of the capacitor, the control terminal of the switch being connected to a corresponding word line of the plurality of word lines, and the second electrode of the capacitor being connected to a corresponding plate line of the plurality of plate lines;means for precharging each of the plurality of bit lines to a predetermined precharge voltage level;means for generating a voltage pulse signal having a first voltage level, the voltage pulse signal being applied to at least one plate line of the plurality of plate lines corresponding to a selected word line of the plurality of word lines thereby polarizing the ferroelectric material in a predetermined direction;means for generating a reference signal having a second voltage level;means for generating a first and a second complementary drive signals; andmeans for comparing the reference signal to a voltage on a bit line corresponding to the selected word line and for applying the first or second complementary drive signals to the capacitor responsive to the comparison.