Patent ID: 7860472
Filing Date: 2010-12-28
Classification: H04J,H04L

Abstract:
1. A receiver circuit, comprising: conversion circuit for converting a format of a signal with sampling said signal based on a sampling clock signal; clock data recovery circuit for generating said sampling clock signal having a phase depending on said signal inputted to said conversion circuit; delay circuit for performing delay control to a phase of a clock input signal according to a delay control signal; selector for selecting, during a speed test, said clock input signal delayed by said delay circuit to input to said conversion circuit; wherein said conversion circuit outputs a plurality of output signal, and said clock data recovery circuit comprises: phase control circuit which compares said plurality of output signal, and outputs a phase control code for controlling said phase of said sampling clock signal based on a comparison result of said plurality of output signal; recovery clock generating circuit which generates said sampling clock signal having a phase depending on said phase control code, and outputs it to said conversion circuit; and counter which counts phase advances or delays according to said comparison result, wherein, when said counter counts a predetermined number, said phase control code is varied by a predetermined amount and a counter value of said counter is reset.