Patent ID: 7554392
Filing Date: 2009-06-30
Classification: H03F

Abstract:
1. A multiple power mode amplifier, comprising: (a) an input impedance matching network having an input configured to receive an input signal; (b) a first driver operably coupled to the input impedance matching network and configured to amplify the input signal and provide a first driver output signal therefrom; (c) a first impedance matching network operably connected to the first driver and configured to receive the first driver output signal and provide a first impedance matching network output signal therefrom; (d) a second driver operably coupled to the second impedance matching network and configured to amplify the first impedance matching network output signal and provide a second driver output signal therefrom; (e) a second impedance matching network operably connected to the second driver and configured to receive the second driver output signal and provide a second impedance matching network output signal therefrom; (f) a third impedance matching network operably connected to the second impedance matching network and configured to receive the second impedance matching network output signal and provide a third impedance matching network output signal therefrom; (g) a power stage operably coupled to the third impedance matching network and configured to amplify the third impedance matching network output signal and provide a power stage output signal therefrom; (h) a fourth impedance matching network operably connected to the power stage and configured to receive the power stage output signal and provide a fourth impedance matching network output signal therefrom; (i) a fifth impedance matching network operably connected to the fourth impedance matching network and configured to receive the fourth impedance matching network output signal and provide a fifth impedance matching network output signal therefrom; (j) an impedance transformation network operably coupled between a first node located between the second and third impedance matching networks and a second node located between the fourth and fifth impedance matching networks; and (k) voltage control circuitry operably connected to the first driver, the second driver and the power stage, and configured to adjust quiescent (Q) currents corresponding to the first and second drivers, and to turn the power stage on and off; wherein the power mode amplifier is further configured to operate in high-, mid- and low-power modes such that in a high-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second and third impedance matching networks, the power stage, and the fourth and fifth impedance matching networks while the power stage is turned on and Q-currents of the first and second drivers are set to a high level by the voltage control circuitry, in a mid-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second impedance matching network, the impedance transformation network, and the fifth impedance matching network while the power stage is turned off and Q-currents of the first and second drivers are set to a middle level by the voltage control circuitry, and in a low-power mode the input signal traverses the input impedance matching network, the first driver, the first impedance matching network, the second driver, the second impedance matching network, the impedance transformation network, and the fifth impedance matching network while the power stage is turned off and Q-currents of the first and second drivers are set to a low level by the voltage control circuitry.