Patent ID: 8997103
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A computer-implemented method for processing memory barrier instructions, the method comprising: receiving a first memory barrier instruction for a first thread group that includes multiple parallel execution threads; blocking the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order; receiving, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads; coalescing the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction; tagging each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands; combining the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream; transmitting the tagged memory command stream and memory transactions for the first thread group that are prior to the first memory barrier instruction in program order to a memory management unit to process the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order, the first set of memory transactions, the first memory barrier instruction, and the second memory barrier instruction; determining that the memory transactions for the first thread group that are prior to the first memory barrier instruction in program order and the first set of memory transactions are committed to memory; and releasing both the first memory barrier instruction to allow the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order to be executed and the second memory barrier instruction to allow the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order to be executed.