Patent ID: 6448183
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method for forming a portion of a semiconductor element on a wafer comprising the steps of:depositing an insulation layer on a lower thin film on which there is formed a semiconductor element electrode or a metal wiring pattern, and then planarizing an upper surface of the insulation layer; forming a photosensitive film pattern over the upper surface having a contact or via hole pattern in which inner walls of the contact holes or via holes smoothly curve downward to reach an upper surface of the insulation layer, by depositing a photosensitive film on an upper surface of the insulation layer and developing the photosensitive film through a light exposure process using a mask on which there is formed a contact hole or via-hole pattern, thereby forming the photosensitive film pattern in which inner walls of the photosensitive film pattern are in a stepped pattern, wherein in order to form the stepped pattern of the inner walls of the photosensitive film pattern, the temperature is continuously varied during the depositing of the photosensitive film, and then hard baking the photosensitive film pattern such that the stepped pattern of the inner wall is smoothed; dry-etching the insulation layer using the photosensitive film pattern as a mask to form contact holes or via holes; removing the photosensitive film pattern, then depositing a barrier metal and tungsten to fill the contact holes or the via holes; and performing a chemical mechanical polishing process to remove the barrier metal and the tungsten from the upper surface of the insulation layer until the upper surface of the insulation layer is exposed and a planar surface is obtained.