Patent ID: 8913414
Filing Date: 2014-12-16
Classification: G11C

Abstract:
1. A semiconductor apparatus including a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips, wherein, in a normal mode, an uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an adjoining semiconductor chip through an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines, the at least one semiconductor chip other than the uppermost semiconductor chip logically combining the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals, and wherein, in a scan mode, a corresponding internal information signal outputted from a semiconductor chip selected among the plurality of semiconductor chips is sequentially transferred through the plurality of through-semiconductor chip lines, and the internal information signal of the selected semiconductor chip is not combined with the internal information signals of the non-selected semiconductor chips.