Patent ID: 6114896
Filing Date: 2000-09-05
Classification: H03K

Abstract:
A method of reducing the disabled capacitance of a complementary multiplexer so as to increase the number of channels being multiplexed for a predetermined level of capacitance, the method comprising the steps of:(a) providing an integrated circuit having:a plurality of switched buffers where each of the switched buffers includes one input terminal and complementary high and low output terminals,a first unidirectional current device, anda second unidirectional current device;(b) operatively connecting the high output terminals of each of the plurality of switched buffers to the anode of the first unidirectional current device within the integrated circuit;(c) operatively connecting the low output terminals of each of the plurality of switched buffers to the cathode of the second unidirectional current device within the integrated circuit; and(d) operatively connecting the cathode of the first unidirectional current device to the anode of the second unidirectional current device within the integrated circuit to thereby provide an output terminal for the multiplexer.