Patent ID: 7818744
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A method comprising: reserving a first in, first out (FIFO) buffer within a shared memory of a multicore chip multiprocessor (CMP) system for data communication between a leading thread and a trailing thread, including a buffer head variable to write data to the FIFO buffer and a buffer tail variable to read data from the FIFO buffer; executing the leading thread within a first processor of the CMP system; simultaneously executing the trailing tread within a second processor of the CMP system; writing, by the leading thread, data to the FIFO buffer according to a local buffer head variable; delaying the leading thread, by updating of the buffer head variable according to the local buffer head variable until an amount of data written to the FIFO buffer equals a predetermined data unit size; reading, by the trailing thread, data from the FIFO buffer according to a local buffer tail variable; and delaying the trailing thread, by updating of the buffer tail variable according to the local buffer tail variable until an amount of data read from the FIFO buffer equals the predetermined data unit size; wherein prior to reserving, the method further comprises: replicating an application into two communicating threads, the leading thread and the trailing thread; repeating, by the trailing thread, computations performed by the leading thread during execution of the application; and restricting the trailing thread from passing data to the leading thread.