Patent ID: 6363464
Filing Date: 2002-03-26
Classification: G06F

Abstract:
A system having first and second controllers respectively operating at a given point in time as active and standby controllers, each of said first and second controllers comprisinga system processor, FIFO memory associated with said system processor, a shadow processor, said system processor, memory and shadow processor connected via a system bus; wherein the system processor of the active controller writes data into its associated FIFO memory; wherein the shadow processor of the active controller continuously monitors said data writes performed by its associated active system processor; wherein the shadow processor writes a copy of said data and accompanying write memory address into the input FIFO of the shadow processor of the standby controller via said data pathway; wherein the shadow processor of the standby controller supplies the fill level of its input FIFO to the shadow processor of the active controller; and when said fill level reaches a first predetermined value, the active shadow processor responds thereto by decreasing the rate at which the active processor is writing data into the system memory, until such time the standby shadow processor unloads its fill level below a second predetermined value.