Patent ID: 6484191
Filing Date: 2002-11-19
Classification: G06T

Abstract:
An apparatus for calculating local variance in an array of digital signals, said apparatus comprising:a first squaring device arranged to receive an input signal and provide a first signal indicative of a first value, the first value being equal to a square of the input value, said input signal being one of a plurality of signals within a window defined in the array, said plurality of signals indicative of a plurality of values; a first recursive sum device arranged to receive said first signal and provide a second signal indicative of a second value, the second value being equal to a sum of the squares of the plurality of values; a second recursive sum device arranged to receive said input signal and provide a third signal indicative of a third value, the third value being equal to a sum of the plurality of values; a second squaring device arranged to receive said third signal and provide a fourth signal indicative of a fourth value, the fourth value being equal to a square of the third value; a first dividing device arranged to receive said fourth signal and provide a fifth signal indicative of a fifth value, the fifth value being equal to the fourth value divided by the number of signals in said plurality of signals; a first subtracting device arranged to receive said second and fifth signals and provide a sixth signal indicative of a sixth value, the sixth value being equal to the second value minus the fifth value; and a second dividing device arranged to receive said sixth signal and provide an output signal indicative of a variance of the plurality of values; wherein the first recursive sum device comprises: a first recursive stage including, a first delay device arranged to receive said first signal and delay said first signal for a first predetermined number of clock cycles, said first delay device providing a seventh signal indicative of a seventh value, said seventh signal having been delayed by said first delay device for said first predetermined number of clock cycles, a first adding device arranged to receive said first signal and a ninth signal and provide an eighth signal indicative of an eighth value, the eighth value being equal to a sum of the first value and a ninth value indicated by said ninth signal, a second subtracting device arranged to receive said seventh and eighth signals and provide a tenth signal indicative of a tenth value, the tenth value being equal to a difference between the eighth and seventh values, and a second delay device arranged to receive said tenth signal and delay said tenth signal for a second predetermined number of clock cycles, said second delay device providing said ninth signal, said ninth signal having been delayed by said second delay device for said second predetermined number of clock cycles; and a second recursive stage including, a third delay device arranged to receive said tenth signal and delay said tenth signal for a third predetermined number of clock cycles, said third delay device providing an eleventh signal indicative of an eleventh value, said eleventh signal having been delayed by said third delay device for said third predetermined number of clock cycles, a second adding device arranged to receive said tenth signal and a twelfth signal and provide a thirteenth signal indicative of a thirteenth value, the thirteenth value being equal to a sum of the tenth value and a twelfth value indicated by said twelfth signal, a third subtracting device arranged to receive said eleventh and thirteenth signals and provide a fourteenth signal indicative of a fourteenth value, the fourteenth value being equal to a difference between the thirteenth and eleventh values, and a fourth delay device arranged to receive said fourteenth signal and delay said fourteenth signal for a fourth predetermined number of clock cycles, said fourth delay providing said second signal.