Patent ID: 6664584
Filing Date: 2003-12-16
Classification: H01L

Abstract:
A memory device, comprising:an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising: a bottom electrode having a bottom electrode metal component; a top electrode having a top electrode metal component; a dielectric layer interposed between the bottom electrode and the top electrode; and at least one metal oxynitride barrier layer having a baffler metal component, wherein the baffler metal component is different from the bottom electrode metal component or wherein the baffler metal component is different from the top electrode metal component, wherein the at least one metal oxynitride barrier layer is interposed between the dielectric layer and the bottom electrode or wherein the at least one metal oxynitride layer is interposed between the dielectric layer and the top electrode; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.