Patent ID: 6609143
Filing Date: 2003-08-19
Classification: G06F

Abstract:
An arithmetic logic unit for receiving data words X and Y and outputting a data word Z, where X and Y are each composed of a predetermined plural number of data units, each data unit having a predetermined number of bits, comprising:a register for storing and outputting a received data as the data word Z; a plurality of selectors, each selecting and outputting one of the plurality of data units of which the data word Y is made up; a plurality of multipliers respectively corresponding to the plurality of selectors, each of the plurality of multipliers multiplying together the data unit of the data word Y selected by the corresponding selector and a corresponding data unit of the plurality of data units of which the data word X is made up and outputting the result; a shifter for bit shifting each output of the plurality of multipliers according to digit positions of the data unit in the data word X and the data unit in the data word Y which are input to each of the plurality of multipliers and outputting the result; and an adder for accumulating an output of the shifter and inputting the sum to the register, wherein a series of operations are repeated in which the respective selectors select a data unit that has not been selected by the respective selectors from the data units of the data word Y, the shifter performs the bit shifting, and the adder performs the accumulation.