Patent ID: 7660942
Filing Date: 2010-02-09
Classification: G06F,G11C

Abstract:
1. A memory chip comprising: a first input configured to receive an address/command word; a first output configured to drive an address/command word; circuitry configured to determine from contents of the address/command word if the address/command word is directed to the memory chip; an array capable of storing data; and a self time block configured to determine a performance of the array and to drive a timing signal to the array, the timing signal responsive to the determination of the performance of the array; wherein the memory chip is configured to make a read from or write to the array for address/command words determined to be directed to the memory chip; if the address/command word is determined to not be directed to memory chip, the memory chip is configured to re-drive the address/command word onto the first output; if the address/command word is determined to be directed to the memory chip, the memory chip is configured to not re-drive the address/command word onto the first output; the self time block further comprising a ring oscillator having a frequency that tracks an access time of the array; the self time block further comprising: a counter having a plurality of bits, the counter configured to count responsive to a first clock, the counter being reset by a first value of an output of the ring oscillator; a register configured to receive a value of the counter when the output of the ring oscillator transitions to the first value; and a decode that decodes a value in the register and produces a self timing signal coupled to the array, the array configured to use the self timing signal to time at least a portion of an access to the array.