Patent ID: 6327215
Filing Date: 2001-12-04
Classification: G11C

Abstract:
A bit switch decode circuit, comprising:a first number of sense amplifier banks;a first number of local bit select lines wherein each of said local bit select lines is at a high level or a low level;a second number of sense amplifiers in each of said sense amplifier banks, wherein each of said sense amplifiers has a first input and a second input;a first transistor in each of said sense amplifier banks wherein each of said first transistors is an N channel field effect transistor having a source connected to a first data line, a drain connected to said first input of one of said sense amplifiers in that said sense amplifier bank, a gate, and a threshold voltage;a second transistor in each of said sense amplifier banks wherein each of said second transistors is an N channel field effect transistor having a source connected to a second data line, a drain connected to said second input of one of said sense amplifiers in that said sense amplifier bank, a gate, and a threshold voltage;a third transistor in each of said sense amplifier banks, wherein each of said third transistors is an N channel field effect transistor having a source connected to said gates of each of said first and said second transistors in that said sense amplifier bank, a drain connected to one of said local bit select lines, a gate, and said threshold voltage;a global bit select line, wherein said global bit select line is at said high level or said low level; anda voltage source connected to said global bit line wherein said voltage source supplies a selecting voltage between said gates of each of said third transistors and ground potential when said global bit line is at said low level and a voltage about equal to said threshold voltage between said gates of each of said third transistors and ground potential when said global bit line is at said high level and a voltage about equal to said threshold voltage.