Patent ID: 6040219
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method for manufacturing a power semiconductor device, comprising the steps of:(a) forming a conductive collector region in a semiconductor substrate;(b) forming a first insulating film over collector region, the first insulating film exposing a first portion of the collector region;(c) forming a conductive base region in the exposed first portion of the collector region;(d) forming a second insulating film over the collector region, the second insulating film exposing a second portion of the collector region and a third portion of the base region;(f) implanting first impurities for the emitter region into the third portion of the base region;(g) implanting second impurities for the channel stop region into the second portion of the collector region;(h) simultaneously forming a third insulating film over the collector region, forming a conductive emitter region by diffusing the first implanted impurities, and forming a channel stop region by diffusing the second implanted impurities;(i) removing portions of the first, second, and third insulating films over the base, emitter, and channel stop regions to create a remaining insulating film in a field region between the base region and the channel stop region;(j) forming a semi-insulating polycrystalline silicon (SIPOS) film over the semiconductor substrate and the remaining insulating layer, such that parts of the base region, the emitter region, and the channel stop region are exposed;(k) forming a base electrode contacting the base region;(l) forming an emitter electrode contacting the emitter region; and(m) forming an equipotential metal ring contacting the channel stop region.