Patent ID: 6876573
Filing Date: 2005-04-05
Classification: G11C

Abstract:
1. A semiconductor device, comprising: a memory array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to any of the plurality of word lines and any of the plurality of bit lines; a peripheral circuit including a circuit which selects the corresponding memory cell in the memory array, a circuit which amplifies information retained in the selected memory cell, and a circuit which effects writing on the selected memory cell, based on a write data signal; and a logic circuit having a logic function, said semiconductor device being formed on one semiconductor chip as a semiconductor integrated circuit, wherein each of the memory cells comprises a flip-flop circuit including a first CMOS inverter and a second CMOS inverter, and transmission MOS transistors respectively connected between the flip-flop circuit and each pair of bit lines connected to input/output nodes of the flip-flop circuit, wherein an operating voltage of the memory cell is set higher than an operating voltage of the peripheral circuit, and a gate insulating film for MOS transistors included in the memory cell is thicker than a gate insulating film for MOS transistors included in the peripheral circuit, and wherein the logic circuit includes a flip-flop circuit, an operating voltage of the flip-flop circuit is set higher than the operating voltage of the peripheral circuit, a gate insulating film for MOS transistors included in the flip-flop circuit is formed of the same material as the gate insulating film for the MOS transistors included in the memory cell and has the same thickness as the gate insulating film for the MOS transistors included in the memory cell.