Patent ID: 7463234
Filing Date: 2008-12-09
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a pixel array portion having signal lines and scanning lines horizontally and vertically aligned, and pixel transistors formed in the vicinity of each intersection of said signal line and said scanning line; a plurality of first latch circuits configured to latch digital gradation data consisting of a plurality of bits in different timings, said plurality of first latch circuits being provided corresponding to every multiple signal lines; a plurality of second latch circuits which are provided in accordance with each of a plurality of said first latch circuits and latch data latched by each of a plurality of said first latch circuits at the same time; a plurality of D/A converters which are provided in accordance with each of a plurality of second latch circuits and convert latch data latched by each of a plurality of said second latch circuits into analog gradation voltage; and a plurality of signal line selection circuits configured to drive a plurality of signal lines, respectively, each of said signal line selection circuits being provided corresponding to each of said plurality of D/A converters, wherein the number of each of the first latches, second latches, the D/A converters and the signal line selection circuits provided are less than the number of signal lines.