Patent ID: 8587329
Filing Date: 2013-11-19
Classification: G01D,G01F,H03K

Abstract:
1. A circuit arrangement for determination of a measuring capacitance, the circuit arrangement comprising: a) a measuring circuit portion comprising: b) a reference circuit portion comprising: c) a square wave generator coupled to said first switch arrangement and said second switch arrangement, wherein said square wave generator is configured to simultaneously switch said first switch arrangement and said second switch arrangement to said open state for a first time interval and then simultaneously switch said first switch arrangement and said second switch arrangement to said closed state for a second time interval at a constant frequency equal to the reciprocal of the sum of said first time interval and said second time interval, thereby generating a first periodic signal comprising a time curve of a charging voltage of said measuring capacitance and a second periodic signal comprising a time curve of a charging voltage of said reference capacitance; d) a first low-pass filter of a first order directly coupled to said measuring capacitance, wherein said first low-pass filter is configured to form an arithmetic mean value of said first periodic signal; e) a second low-pass filter of a first order directly coupled to said reference capacitance, wherein said second low-pass filter is configured to form an arithmetic mean value of said second periodic signal; and f) a comparator having a first input coupled to said first low-pass filter to receive said arithmetic mean value of said first periodic signal and a second input coupled to said second low-pass filter to receive said arithmetic mean value of said second periodic signal, wherein said comparator is configured to emit a signal when said arithmetic mean value of said first periodic signal drops below said arithmetic mean value of said second periodic signal.