Patent ID: 7868397
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A vertical semiconductor device, comprising: a first base layer of a first conductivity type; second base layers of a second conductivity type selectively formed at one main surface of said first base layer; emitter layers of said first conductivity type selectively formed at respective surfaces of said second base layers opposite to said first base layer; an electric field relaxing structure selectively formed at said one main surface of said first base layer outside and away from an outermost second base layer of said second base layers; gate electrodes to be electrically connected with at least said second base layer via respective gate insulating films; an emitter electrode to be electrically connected with said second base layer and said emitter layers; a buffer layer of said first conductive type formed on the other main surface of said first base layer; a collector layer of said second conductivity type formed at a main surface of said buffer layer opposite to said base layer except a region below said electric field relaxing structure; and a collector electrode layer formed on said main surface of said buffer layer so as to be electrically connected with said collector layer, wherein an edge of said collector layer in the side of said electric field relaxing structure is located inside from an edge of said base layer in the side of said electric field relaxing structure by a distance equal to or more than a thickness of said first base layer.