Patent ID: 8194090
Filing Date: 2012-06-05
Classification: G09G

Abstract:
1. A method of controlling a frame memory using a memory control circuit comprising: receiving data representing values of pixels constituting each of a plurality of frames in an order of the frames, and supplying the data to the frame memory; and generating address signals that specify addresses of the frame memory to be accessed and control signals that command reading from or writing to the frame memory, and supplying the generated address and control signals to the frame memory such that data representing values of pixels constituting a previous frame previously written to the frame memory are read from the frame memory and data representing values of pixels constituting a next frame next to the previous frame are written to the frame memory, wherein the generating and supplying are performed such that the reading from the frame memory includes i) starting to read data representing values of pixels constituting a particular previous frame from the frame memory before the receiving of the data representing values of pixels constituting the next frame starts, ii) stopping to read data representing values of pixels constituting the particular previous frame from the frame memory when first data representing values of a portion of the pixels constituting the particular previous frame are read, and iii) re-starting to read data representing values of pixels constituting the particular previous frame from the frame memory after the receiving of the data representing values of pixels constituting the next frame starts.