Patent ID: 6100757
Filing Date: 2000-08-08
Classification: H03F,H03H

Abstract:
A method of controlling time delay of a signal, comprising:applying a first bias voltage at a first node of a variable time delay network to control time delay of said signal when passing through said variable time delay network, said variable time delay network including:a first segment and a second segment, said first and second segments connected in parallel to form said variable time delay network, said first segment including:a first varactor diode and an inductive element connected in series at an anode electrode of said first varactor, a cathode electrode of said first varactor diode connected to said first node;and said second segment including:a second varactor and a bypass capacitor connected in series at a cathode electrode of said second varactor, said cathode electrode of said second varactor connected at a second node, an anode electrode of said second varactor connected to said first node;applying a second bias voltage at said second to node to create in said first and second segments an approximately equal and opposite polarity reactance while applying said first bias voltage at said first node of said variable time delay network.