Patent ID: 7869261
Filing Date: 2011-01-11
Classification: G11C

Abstract:
1. A semiconductor memory comprising a plurality of memory cells, which are disposed in a matrix, and a pair of bit lines, which are disposed for each column of the memory cells; each of the memory cells comprising: a pair of inverters, which are cross-coupled and each of whose output terminals is connected through a path to a corresponding one of the bit lines; a first switching unit, which is provided between one of the bit lines and the output terminal of a corresponding one of the inverters; and a second switching unit, which is provided between the other of the bit lines and the output terminal of the other of the inverters; wherein: the first switching unit comprises a first transfer-gate which is conductive during a reading operation and a writing operation and a second transfer-gate which is conductive during the writing operation; the second switching unit comprises a third transfer-gate which is conductive during the reading operation and the writing operation and a fourth transfer-gate which is conductive during the writing operation; and a conductance of each of the first switching unit and the second switching unit is adjustable, both of the first and second switching units are utilized for the reading operation and the writing operation, and each of the first and second switching units is controlled to be conductive such that the conductance of each switching unit be larger for the writing operation than for the reading operation; and each of the memory cells comprising: a p-type transistor and an n-type transistor, which are coupled in series between a write column line or a write word line and a ground voltage, gates of which are coupled to a complementary write word line or a complementary write column line respectively, and a coupling point of which is coupled to gates of the second and fourth transfer-gates; wherein: the write column line and the write word line are activated in the writing operation, and the complementary write column line and the complementary write word line are complementarily activated to the write column line and the write word line respectively.