Patent ID: 6678643
Filing Date: 2004-01-13
Classification: G01R

Abstract:
A semiconductor test system, comprising:an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test on design data of the LSI device; an event memory for storing the event data obtained directly from the event file in two separate types of data, one showing an integer multiple of a reference clock cycle and the other showing fractions of the reference clock cycle; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; means for displaying the test pattern applied to the LSI device under test and changing the test pattern by partially modifying the event data in the event file in real time, wherein such chances in the test pattern include a change of a particular timing of an event; a result data file for storing a response output of the LSI device under test; and means for evaluating design of the LSI device based on the data stored in the result data file and producing a testbench based on results of the evaluation for executing device logic simulation in the design stage of the LSI device under test, thereby incorporating the test results in the design of the LSI device.