Patent ID: 7199609
Filing Date: 2007-04-03
Classification: H03K

Abstract:
1. A method of forming a field programmable gate array architecture having a plurality of input/output pads comprising: providing a plurality of logic clusters; providing a plurality of input/output clusters; providing a plurality of input/output buffers; providing a plurality of dedicated input/output first-in/first-out memory blocks, said dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of said plurality of input/output pads; providing an input/output block controller programmably coupled to said plurality of dedicated input/output first-in/first-out memory blocks, wherein said input/output block controller comprises a dedicated FIFO flag logic block and an input/output FIFO block controller cluster; and providing a routing interconnect architecture programmably coupling said logic clusters, said input/output buffers and said input/output clusters, wherein said dedicated input/output first-in/first-out memory blocks are programmably coupled between said input/output buffers and said input/output clusters.