Patent ID: 6271681
Filing Date: 2001-08-07
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of regions of programmable logic, each of which includes a register having a clock signal input terminal, a data signal input terminal, and a data signal output terminal and configured to respond to a clock signal applied to the clock signal input terminal by applying to the data signal output terminal a data output signal indicative of the signal concurrently applied to the data signal input terminal;a clock signal input pin connected to the clock signal input terminals of the registers;a plurality of tri-state drivers, each having a data signal input connection, a data signal output connection, and an output enable signal connection and being configured to respond to a signal applied to the output enable signal connection by applying to the data signal output connection a signal indicative of the signal concurrently applied to the data signal input connection or a high impedance depending on the signal applied to the output enable signal connection;programmable logic connector circuitry configured to selectively connect the data output signal terminals of the registers to the data signal input and output enable signal inputs of the tri-state drivers; anda plurality of data signal output pins, each of which is connected to the data signal output connection of a respective one of the tri-state drivers, wherein the signal path length from the clock signal input pin to each register clock input signal terminal and from each register data signal output terminal through the programmable logic connector circuitry and the tri-state drivers to the data signal output pins is such that delay between application of a clock signal to the clock signal input pin and application of a data output signal from a register to a data signal output pin is within the PCI TCO time interval.