Patent ID: 9215104
Filing Date: 2015-12-15
Classification: H04L

Abstract:
1. A decision feedback equalizer (DFE), comprising: a first delay cell including a first group of binary weighted sets of flip-flops to be selectably included or excluded to form various delay paths of various lengths of delay based on various binary control numbers, the first delay cell to receive a data signal and output a first signal based on a first sample of the data signal on a falling edge of a clock signal and a first delay path formed with first selected one or more members of the first group of binary weighted sets of flip-flops based on a first binary control number; a second delay cell coupled to the first delay cell and including a second group of binary weighted sets of flip-flops to be selectably included or excluded to form various delay paths of various lengths of delay based on various binary control numbers, the second delay cell to receive the data signal and to output a second signal based on a second sample of the data signal on a rising edge of the clock signal and a second delay path formed with second selected one or more members of the second group of binary weighted sets of flip-flops based on a second binary control number; and a multiplexer coupled to the first delay cell and the second delay cell to receive the first signal and the second signal, the multiplexer to output a tap signal based on the first signal and the second signal.