Patent ID: 6020228
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device having an n-channel MIS transistor and a p-channel MIS transistor formed in a semiconductor substrate, comprising:(a) a step of forming a p-well and an n-well in the semiconductor substrate;(b) a step of forming over the semiconductor substrate a first mask that covers a p-channel MIS transistor formation region and a p-well power supply region and exposes an n-channel MIS transistor formation region and an n-well power supply region;(c) a step of introducing a p type impurity for making a p.sup.- type semiconductor region into a region of the semiconductor substrate exposed from the first mask in an inclined direction with respect to the principal surface of the semiconductor substrate;(d) a step of introducing an n type impurity for making an n.sup.+ type semiconductor region into a region of the semiconductor substrate exposed from the first mask;(e) a step of forming over the semiconductor substrate a second mask that covers an n-channel MIS transistor formation region and an n-well power supply region and exposes a p-channel MIS transistor formation region and a p-well power supply region;(f) a step of introducing an n type impurity for making an n.sup.- type semiconductor region into a region of the semiconductor substrate exposed from the second mask in an inclined direction with respect to the principal surface of the semiconductor substrate; and(g) a step of introducing a p type impurity for making a p.sup.+ type semiconductor region into a region of the semiconductor substrate exposed from the second mask.