Patent ID: 6229185
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A CMOS integrated circuit, comprising:a P-type semiconductor layer;an N-type semiconductor well provided in said P-type semiconductor layer to form a junction therebetween;a PMOS transistor formed in said N-type semiconductor well, said PMOS transistor having its source terminal connected to a first voltage source;an N-type contact region formed in said N-type semiconductor layer and connected to said first voltage source;an NMOS transistor formed on said P-type semiconductor layer, and NMOS transistor having its source terminal connected to a second voltage source;a P-type contact region formed in said P-type semiconductor layer and connected to said second voltage source; anda P-type carrier-releasing region having one portion formed in said N-type semiconductor well and another portion formed in said P-type semiconductor layer to span said junction.