Patent ID: 6177325
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for forming a self-aligned bipolar junction transistor (BJT) having a reduced size and reduced parasitic resistor and parasitic capacitance effects comprising the steps of:forming a first base region, an emitter region and a second base region over a semiconductor substrate,forming a pair of nitride spacers, each adjacent to said emitter region,doping said first and second base regions with an impurity of a first conductivity type,removing said pair of nitride spacers,forming trench regions through said emitter region in the area of the removed spacers,filling said trenches with a dielectric, anddoping said emitter region with an impurity of a second conductivity type to form a self-aligned bipolar junction transistor (BJT) having a reduced size and reduced parasitic resistor and capacitance effects.