Patent ID: 7978511
Filing Date: 2011-07-12
Classification: G11C

Abstract:
1. A method for operating a memory device having a plurality of memory cells logically arranged in rows and columns, the method comprising: selecting one or more memory cells of a particular row to be programmed; and inhibiting two ore more adjacent memory cells of the particular row from programming; wherein any two memory cells of the particular row that are selected for programming are separated by two or more inhibited adjacent memory cells therebetween, regardless of an intended pattern of data values to be programmed into the particular row; and wherein inhibiting the two or more adjacent memory cells comprises biasing a first data line coupled to a first inhibited memory cell to a first inhibit voltage and biasing a second data line coupled to a second inhibited memory cell to a second inhibit voltage where the first inhibit voltage and the second inhibit voltage are different.