Patent ID: 8779951
Filing Date: 2014-07-15
Classification: G01R,G04F,H03K,H03M

Abstract:
1. A multi-bit delta-sigma time digitizer circuit, which measures a rising timing interval between a first clock signal and a second clock signal, the circuit comprising: a delay array which includes a plurality of delay selection circuits respectively including a delay element and a multiplexer, and is configured to delay one of the first clock signal and the second clock signal; a phase comparator configured to calculate a time difference according to an output signal of the delay array; an integrator configured to integrate the time difference output from the phase comparator; a flash A/D converter configured to execute digital conversion according to an integration result of the integrator; a ring oscillation circuit configured to include the delay array; a counter configured to measure a number of pulses of a clock signal which passes through the ring oscillation circuit; a memory configured to store a delay value of the delay element calculated from an oscillation frequency based on the number of pulses; and a processor configured to correct an output result of the A/D converter based on the delay value stored in the memory when the rising timing interval between the first clock signal and the second clock signal input to the delay array is measured.