Patent ID: 6020231
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A method of forming a lightly doped drain region (LDD) in an integrated circuit device comprising:providing a semiconductor substrate comprising a first well region, a first gate dielectric layer, and a first polysilicon gate electrode, said first gate dielectric layer overlying said first well region, and said first polysilicon gate electrode overlying said first gate dielectric layer; said first polysilicon gate electrode having a length of about 0.35 micron and less;forming a first thermal oxide thickness overlying said first polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions of said first gate dielectric layer, said first thermal oxide thickness being greater than said second thermal oxide thickness;angle implanting a first impurity through said first thermal oxide thickness and said second thermal oxide thickness into said first well region to form first LDD regions; andimplanting a second impurity through said second thermal oxide thickness into said first well region to form first source/drain regions;wherein said first gate electrode includes an edge overlying said first gate dielectric layer, said edge having a substantially round corner region which reduces gate edge stress on said first gate dielectric layer, said substantially round corner including a radius of curvature of about 250 .ANG. and greater to reduce a gate edge stress, thereby improving said gate dielectric layer.