Patent ID: 6487120
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of data-erasable memory cells including gate electrodes, for storing data; a plurality of word lines coupled with the gate electrodes of said plurality of memory cells; a first voltage output circuit supplied with a first voltage, for outputting a second voltage obtained by boosting the first voltage; a second voltage output circuit coupled with said first voltage output circuit, for generating a third voltage whose voltage value is smaller than a value of the second voltage and which is variably set to at least two values based on the second voltage; an equalizer circuit coupled with said first and second voltage output circuits, for short-circuiting an output node of the second voltage and an output node of the third voltage in response to a first control signal; and a row decoder circuit coupled with said second voltage output circuit, for setting potentials of said plurality of word lines based on the third voltage.