Patent ID: 7526689
Filing Date: 2009-04-28
Classification: G11C

Abstract:
1. A system for testing a set of address lines, said set of address lines having at least a first group and a second group, said system comprising: at least one memory device having a set of address inputs that are connected to said first group and said second group at different times; and a processor subsystem coupled to said memory device, the processor subsystem being programmed to: pre-load a first set of predetermined data into a first set of locations of said at least one memory device and write a second set of predetermined data into a second set of locations of said at least one memory device that is associated with said first set of locations, said first and said second sets of locations being chosen such that each of said set of address inputs is exercised in accessing said first and said second sets of locations; and read said first and said second sets of locations to determine if they are correctly accessed by using said first and said second sets of predetermined data.