Patent ID: 8402448
Filing Date: 2013-03-19
Classification: G06F

Abstract:
1. A processing unit for executing a machine language code comprising: a register for a program counter; execution circuitry configured to execute the machine language code which is compiled and encrypted based on an expected state of the program counter of the processing unit by a compiler extern to a chip on which the processing unit resides; a fetcher configured to fetch a word from an address of a program memory connectable to the processing unit, wherein the address corresponds to the current state of the program counter and, the program counter being configured to be incremented upon fetching in accordance to a length of the respective word; a decryption unit configured to decrypt the word fetched from the program memory; an instruction decoder configured to analyze the decrypted word, decide as to whether the decrypted word belongs to an instruction encompassing a further word or not and, if the instruction does not encompass a further word, drive the execution circuitry according to the instruction.