Patent ID: 7122869
Filing Date: 2006-10-17
Classification: H01L

Abstract:
1. A non-volatile semiconductor memory device, comprising: a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and is substantially the same therewith and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line, wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line; and the pair of selection gate transistors have substantially the same structure, each of the pair of transistors has a portion in which the impurity concentration of the channel region thereof is different in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film, and the concentration distribution of impurity of the channel region of each transistor is different from that of the channel region of the memory cell.