Patent ID: 6522020
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A wafer-level package comprising:a semiconductor chip having a plurality of bond pads at a top surface thereof; a substrate bonded to the top surface of the semiconductor chip, and provided with recess portions at each of opposite edge portions thereof not facing the bond pads, said substrate being provided with metal lines each extending from a portion of the substrate arranged adjacent one of the bond pads, to a bottom surface of one of the recess portions; metal wires electrically connecting the bond pads to the metal lines, respectively; a lead frame having inner leads each firmly fitted in one of the recess portions of the substrate and electrically connected to one of the metal lines, and outer leads formed to have a step structure extending toward a bottom surface of said wafer-level package and not extending past a lateral edge portion of the semiconductor chip; and an encapsulation material completely encapsulating the top surface of the semiconductor chip including the substrate and the metal wires while allowing only the outer leads of the lead frame to be exposed.