Patent ID: 6570227
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A 5T CMOS static RAM cell of the type in which a one state or a zero state is written thereto from a single bit line, comprising:a first inverter define by serially connected complementary MOS transistors (TA/TC) serially connected between a voltage source and a circuit ground and forming a first data node (1) between the transistors (TA/TC); a second inverter defined by serially connected complementary MOS transistors (TB/TD) serially connected between the voltage source and the circuit ground and forming a second data node (2) between the transistors (TB/TD); the gates of the transistors (JA/TC) of the first inverter connected and to the second node (2); the gates of the transistors (TB/TD) of the second inverter connected together and to a bit line (BL) through an access transistor (TE); and a PN diode connected between the first data node (1) and the connected together gate of the transistors (TB/TD) of the second inverter, the diode being reversed biased during a write one operation.