Patent ID: 6260159
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A bridge for a multi-processor system, the bridge comprising:a first processor bus interface for connection to an I/O bus of a first processing set, the first processing set including memory;a second processor bus interface for connection to an I/O bus of a second processing set, the second processing set including memory;a device bus interface for connection to a device bus;a bridge control mechanism configured to be operable to permit direct memory access to the memory of the processing sets by a device on the device bus, to arbitrate between the first and the second processing sets for access to the bridge in a first, split, mode, and to monitor lockstep operation of the first and second processing sets in a second, combined, mode; anda dirty RAM mechanism in the bridge for monitoring regions of processor set memory modified by direct memory access by the device on the device bus.