Patent ID: 7644342
Filing Date: 2010-01-05
Classification: G06F,H03M

Abstract:
1. A semiconductor device, comprising: A pieces of memory cell areas, each of which includes a plurality of memory cells; a plurality of buffers, each of which is coupled to one of the memory cell areas to temporarily store data to be written into said memory cell area and data read out from the memory cell area; and an error correction circuit including a coder configured to generate check bits for error correcting and to attach said check bits to data to be written into said memory cell areas and a decoder configured to process for error correcting said data read out from said memory cell areas with said generated check bits, said error correction circuit treats K=B×A bits (where B denotes a natural number) as an information bit length, generates H check bits for said information bit length, and treats (K+H) bit data as a unit to be written or read at a time from or to said A pieces of memory cell areas.