Patent ID: 9106399
Filing Date: 2015-08-11
Classification: H03L,H04L

Abstract:
1. A circuit for receiving a digital signal comprising: at least three samplers for sampling the digital signal, each sampler having a clock input, wherein the samplers include an edge sampler and a data sampler and an adaptive sampler; edge clock circuitry to generate an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance with the edge clock signal; data clock circuitry to generate a data clock signal, coupled to the data sampler to sample the digital signal in accordance with the data clock signal; and adaptive clock circuitry to generate an adaptive clock signal, coupled to the adaptive sampler to sample the digital signal in accordance with the adaptive clock signal, and to phase shift the adaptive clock signal so as to sample the digital signal at selected phases in a data eye of the digital signal.