Patent ID: 7834671
Filing Date: 2010-11-16
Classification: G09G

Abstract:
1. An analog buffer comprising: a first transistor comprising a drain for receiving a first supply voltage, a source for outputting an output voltage, and a gate; a second transistor comprising a drain for receiving a second supply voltage, a source coupled to the source of the first transistor, and a gate; a first capacitor comprising a first end coupled to the gate of the first transistor, and a second end; a second capacitor comprising a first end coupled to the gate of the second transistor, and a second end; a first switch comprising a first end coupled to the second end of the first capacitor, and a second end coupled to the source of the first transistor; a second switch comprising a first end coupled to the second end of the second capacitor, and a second end coupled to the source of the second transistor; a third switch comprising a first end for receiving a first reference voltage, and a second end coupled to the first end of the first capacitor; a fourth switch comprising a first end for receiving a second reference voltage, and a second end coupled to the first end of the second capacitor; a fifth switch comprising a first end for receiving an input voltage, and a second end coupled to the second end of the first capacitor; a sixth switch comprising a first end for receiving the input voltage, and a second end coupled to the second end of the second capacitor; a seventh switch comprising a first end coupled to the gate of the first transistor, and a second end coupled to the source of the first transistor; an eighth switch comprising a first end coupled to the gate of the second transistor, and a second end coupled to the source of the second transistor; a ninth switch comprising a first end coupled to the first end of the first capacitor, and a second end coupled to the gate of the first transistor; and a tenth switch comprising a first end coupled to the first end of the second capacitor, and a second end coupled to the gate of the second transistor; wherein the analog buffer performs a voltage compensation operation for generating the output voltage based on the first reference voltage and the second reference voltage, the first, second, third and fourth switches are controlled by a first control signal, the fifth and sixth switches are controlled by a second control signal, the ninth and tenth switches are controlled by a first enable control signal, and the seventh and eighth switches are controlled by a second enable control signal.