Patent ID: 7232724
Filing Date: 2007-06-19
Classification: H01L

Abstract:
1. A method of fabricating a flash memory cell in a wafer, comprising: forming a first dielectric layer and a charge trapping layer of a triple layer dielectric-charge trapping-dielectric stack over a substrate; selectively etching the dielectric and charge trapping layers down to the substrate to form a bitline opening in a bitline region; implanting a dopant ion species into the substrate associated with the bitline opening to form a bitline; performing a radical oxidation process after forming the bitline to form a second dielectric layer of the triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and filling the bitline opening; and forming a wordline structure over the second dielectric layer, thereby covering the triple layer dielectric-charge trapping-dielectric stack and the bitline region.