Patent ID: 7749806
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A fabricating process of a chip package structure, comprising: providing a first substrate having a plurality of first bonding pads; providing a second substrate having a plurality of second bonding pads; forming a plurality of bumps on the first bonding pads of the first substrate; forming a first two-stage adhesive layer on the first substrate; B-stagizing the first two-stage adhesive layer to form a first B-staged adhesive layer, wherein a method for forming the first B-staged adhesive layer comprises; forming a plurality of first two-stage adhesive pillars to surround the bumps; and B-stagizing the first two-stage adhesive pillars to form a plurality of first B-staged adhesive pillars; forming a second two-stage adhesive layer on the second substrate; B-stagizing the second two-stage adhesive layer to form a second B-staged adhesive layer, wherein a method for forming the second B-staged adhesive layer comprises: forming a plurality of second two-stage adhesive pillars on the second bonding pads; and B-stagizing the second two-stage adhesive pillars to form a plurality of second B-staged adhesive pillars, wherein the first B-staged adhesive pillars are conductive when the second B-staged adhesive pillars are non-conductive or the first B-staged adhesive pillars are non-conductive when the second B-staged adhesive pillars are conductive; and bonding the first substrate and the second substrate via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.