Patent ID: 7601564
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method of manufacturing an anti-fuse element comprising an anti-fuse portion and a memory cell portion other than the anti-fuse portion, each of which includes a MOSFET type gate capacitor, the method comprising: forming an element isolation region in a semiconductor substrate to prepare first and second element forming regions in which the anti-fuse portion and the memory cell portion are formed, respectively; forming a sacrifice oxide film in at least the first and second element forming regions on the semiconductor substrate, thereafter implanting impurity ions therein to form a well and a channel each having a conductive type different from that of the semiconductor substrate in the semiconductor substrate, removing the sacrifice oxide film therefrom, and then forming a gate insulating film on the semiconductor substrate; depositing a gate electrode semiconductor layer which is to become a gate electrode on the gate oxide film, and forming a mask having a pattern to cover the whole of the first element forming region in which the anti-fuse portion is formed on the gate electrode semiconductor layer and not to cover a region which becomes a memory cell portion gate electrode in the second element forming region in which the memory cell portion is formed; implanting impurity ions in the gate electrode semiconductor layer via the mask to introduce the impurities into the memory cell portion gate electrode forming region, and then removing the mask therefrom; forming a resist pattern in accordance with shapes of an anti-fuse gate electrode and a memory cell portion gate electrode on the gate electrode semiconductor layer, and etching the pattern to form the respective gate electrodes; forming a second gate insulating film in such a manner as to cover the gate insulating film on the semiconductor substrate and the whole of the gate electrodes, and thereafter removing a region other than at least a channel region to form side walls which cover the gate electrodes; forming a resist pattern in a portion other than the gate electrodes and the side walls on the gate insulating film, and implanting source/drain ions therein to form source/drain diffusion layers in the element forming regions of the semiconductor substrate; and performing a setting operation so that a depletion ratio of the gate electrode of the anti-fuse portion is different from that of the gate electrode of the memory cell portion, and the depletion ratio of the gate electrode of the anti-fuse portion is lower than that of the gate electrode of the memory cell portion.