Patent ID: 8365036
Filing Date: 2013-01-29
Classification: G06F

Abstract:
1. A method for performing error correction of data of a memory array including storage locations arranged in rows and columns, the method comprising: reading a group of data bits of a data unit from a row of storage locations of a memory array, wherein the group of data bits includes a first subgroup of data bits and a second subgroup of data bits, wherein the first subgroup of data bits are stored in a first group of storage locations of the row and the second subgroup of data bits are stored in a second group of storage locations of the row, wherein the first group of storage locations are located at interleaved positions in the row with respect to the second group of storage locations; reading a group of error correction bits, the group of error correction bits including a first subgroup of error correction bits and a second subgroup of error correction bits; performing a first error correction operation by error correction circuitry using the first subgroup of error correction bits and the first subgroup of data bits to produce a first subgroup of correct data bits; performing a second error correction operation by error correction circuitry using the second subgroup of error correction bits and the second subgroup of data bits to produce a second subgroup of correct data bits; and providing a data unit of correct data bits, wherein the data unit of correct data bits includes the first subgroup of correct data bits and the second subgroup of correct data bits.