Patent ID: 6509611
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having an upper surface and first and second side surfaces substantially parallel to each other; a channel region arranged between said first and second side surfaces within said substrate; source/drain regions formed in said substrate and separated by said channel region; a gate electrode arranged on said upper surface and said first and second side surfaces of said substrate with a gate dielectric layer therebetween; and said substrate further having third and fourth side surfaces substantially parallel to each other and substantially perpendicular to said first and second side surfaces, wherein said source/drain regions are formed in first and second portions of said upper surface, respectively, said first and second portions of said upper surface abutting said third and fourth side surfaces of said substrate, respectively, and separated by said channel region and wherein said source/drain regions extend from said first and second portions of said upper surface to said third and fourth side surfaces of said substrate, respectively.