Patent ID: 6401191
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device, said integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to the CPU, said integrated circuit chip further comprising an external communication port on to said communication bus and on the integrated circuit chip, said external computer device being connected to said external communication port and comprising a processor and a second memory local to said processor of said external computer device, said port having an internal connection to the bus of an internal parallel signal format and an external connection having a data width smaller than the width of said parallel signal format, said second memory being accessible by said CPU through said port, said port forming part of the memory address space of said CPU from which instructions may be fetched, whereby said port may be addressed by execution of an instruction by said CPU and wherein the CPU is operable on execution of an instruction to generate bit packets defining a memory access, the bit packets including a destination identifier capable of identifying that an access to said second memory is intended, wherein the port comprises means for determining if the destination identifier indicates that the packet is intended for off-chip communication through said port.