Patent ID: 7336534
Filing Date: 2008-02-26
Classification: G11C

Abstract:
1. A non-volatile memory device, which is provided within an electronic device having a logic circuit, the non-volatile memory device comprising: a SRAM latch contained in a memory cell controlled by the logic circuit; a SONOS, silicon-oxide-nitride-oxide-silicon, transistor disposed within the memory cell and electrically connected via a first terminal directly to a Vcc node of the electronic device, without a recall transistor connected therebetween, and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device; a pass transistor disposed in the memory cell between the SRAM latch and the SONOS transistor and configured to control read, program, and erase operations of the SONOS transistor, wherein a first pass transistor terminal connected to a second SONOS terminal, and a second pass transistor terminal connected to said SRAM latch; and a switch mechanism configured to controllably place said Vcc node in and out of a floating state depending on the operation being performed by said pass transistor.