Patent ID: 6628259
Filing Date: 2003-09-30
Classification: G09G

Abstract:
A drive circuit of a display unit which has a plurality of source lines and gate lines, transistors provided as switching devices at intersections between the gate lines and the source lines, and display pixels arranged in a matrix form to be controlled by the transistors, wherein image data outputted from the source lines is displayed in accordance with signals from the gate lines on the display pixels, comprising:a control circuit for generating a clock signal consisting of a first clock pulse signal and a second clock pulse signal, in which a reading period when said first clock pulse signal is generated and a transferring period when said second clock pulse signal is generated appear alternately, and the frequency of said second clock pulse signal in the transferring period is lower than that of said first clock pulse signal in the reading period; source drivers being cascade-connected at a plurality of stages, in which the source driver at a first stage is inputted a start pulse signal, and the source drivers at respective steps are inputted digital image data signals and the clock signals, and the source driver in which the start pulse signal is inputted reads the digital image data signal in the reading period; and a shift register provided in each of the source drivers, transferring the start pulse signal during the transferring period toward the source driver at one next stage per one transferring period so as to transfer the start pulse signal in order from the source driver at the first stage up to the source driver at the final stage.