Patent ID: 6503764
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A method of making stacked capacitor in high density DRAM circuit, comprising the steps of:(a) forming a contact plug in an insulating layer on a semiconductor substrate; (b) forming a first conductor layer, a first barrier metal layer, a first transition metal layer, and a sacrificial layer in sequence; (c) patterning said first conductor layer, said first barrier metal layer, said first transition metal layer, and said sacrificial layer stopping on said insulating layer; (d) forming a second barrier metal layer and then etch back to form a barrier metal spacer; (e) removing said sacrificial layer to form a recess between said barrier metal spacer; (f) forming a second transition metal layer and then etch back to form a transition metal spacer; (g) forming a high dielectric constant layer.