Patent ID: 7564971
Filing Date: 2009-07-21
Classification: G06F

Abstract:
1. A signal processing apparatus for performing modular multiplication for use in a signal processing system, the apparatus comprising: a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for determining the carry input value Carry-in of the current clock from the carry value cin for correction of the previous clock and receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock.