Patent ID: 6181162
Filing Date: 2001-01-30
Classification: H03K

Abstract:
A programmable integrated circuit comprising:a first plurality of conductors, each of which extends along a first dimension of an array;a second plurality of conductors, each of which extends along a second dimension of said array, said second plurality of conductors programmably coupled to said first plurality of conductors; anda plurality of logic array blocks, wherein each logic array block comprises:a plurality of programmable logic elements, wherein a programmable logic element comprises at least one programmable logic element input and at least one programmable logic element output;an input multiplexer region for programmably coupling said first plurality of conductors to said programmable logic element inputs and said second plurality of conductors; andan output multiplexer region for programmably coupling said programmable logic element outputs and said second plurality of conductors to said first plurality of conductors,wherein a number of programmable connections between said input multiplexer region and said first plurality of conductors is about equal to a number of programmable connections between said output multiplexer region and said first plurality of conductors.