Patent ID: 7107200
Filing Date: 2006-09-12
Classification: G06F

Abstract:
1. A method for predicting a clock skew for an incomplete integrated circuit design including at least one clock design figure for routing a clock signal, said method comprising: selecting, from the top, a first metal layer including at least one clock design figure; placing, if a minimum clocks skew is to be predicted, clock source locations on the clock design figure in accordance with a first predetermined minimum distance between adjacent clock source locations; placing, if a maximum clock skew is to be predicted, a clock source location on a first clock design figure having a largest size in the first layer, such that the clock source location has a largest distance from a via to a lower layer; placing, if an intermediate clock skew is to be predicted, clock source locations on intersections between the clock design figure and a virtual clock grid created for the first metal layer, the virtual clock grid having a predetermined offset from a design boundary and a predetermined pitch between grid lines; and calculating a clock skew of the incomplete integrated circuit design using the placed clock source locations.