Patent ID: 6979897
Filing Date: 2005-12-27
Classification: H01L

Abstract:
1. A package substrate for improving electrical performance comprising: a first insulating layer having a top surface and a bottom surface; a plurality of groups of inner fingers formed on the top surface of the first insulating layer for electrically connecting to a chip; a plurality of outer fingers formed on the top surface of the first insulating layer for electrically connecting to the chip; a plurality of outer through holes formed through the first insulating layer and electrically connected to the corresponding outer fingers; a plurality of inner through holes formed through the first insulating layer and electrically connected to the corresponding inner fingers; and a ground/power layer located on the bottom surface of the first insulating layer, and having a plurality of openings, wherein a group of the inner through holes including at least two of the inner through holes passes through and is corresponding to one of the plurality of openings to be electrically isolated from the ground/power layer.