Patent ID: 6576970
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A bonding pad of a semiconductor device comprising:a first interlayer insulating layer formed on a semiconductor substrate; a conductive layer pattern formed on a region of the first interlayer insulating layer; a second interlayer insulating layer formed on the first interlayer insulating layer and on the conductive layer pattern; a first metal pad formed on the second interlayer insulating layer, the first metal pad overlying the conductive layer pattern; a third interlayer insulating layer formed on the second interlayer insulating layer and on the first metal pad; a second metal pad formed on the third interlayer insulating layer, wherein the second metal pad is arranged in direct contact with the first metal pad and the conductive layer pattern; and a protective layer formed on the third interlayer insulating layer and on the second metal pad, wherein a pad window region is formed through the protective layer to expose a region of the second metal pad.