Patent ID: 8976802
Filing Date: 2015-03-10
Classification: H04L

Abstract:
1. An allocation circuit for a switch having N input ports and M output ports, comprising an arbitration mechanism, wherein, during a given arbitration decision cycle, the arbitration mechanism is configured to: maintain, until expiration, a set of mappings from a subset of the N input ports to a subset of the M output ports, wherein the set of mappings were determined during an arbitration decision cycle up to K cycles preceding the given arbitration decision cycle, based on requests for the subset of the M output ports in flits associated with packets at the subset of the N input ports; and match other flits associated with other packets at a remainder of the N input ports which include requests to a remainder of the M output ports so that the remainder of the N input ports is mapped to the remainder of the M output ports, wherein the matching involves an arbitration technique and a solution space that is smaller than the N input ports and the M output ports.