Patent ID: 7899052
Filing Date: 2011-03-01
Classification: H04L

Abstract:
1. A memory structure for use with a dual-speed Ethernet device, the memory structure comprising: an Address Resolution Table comprising a plurality of locations, each of said locations being configured to store a packet destination address, wherein the Address Resolution Table is configured to: a Packet Storage Table configured to: a single buffer per packet mechanism configured to receive an individual packet, wherein the single buffer per packet mechanism is configured to perform only one transmit descriptor read per said individual packet and execute a first single access in order to locate the entire packet and a second single access to access the packet destination address at the indexed location using the key, wherein the entire packet is to be transmitted, wherein the memory structure implements memory arbitration for at least six types of memory accesses, and wherein the memory structure facilitates full-duplex, non-blocked Ethernet switch operations at wire speeds.