Patent ID: 6438627
Filing Date: 2002-08-20
Classification: G06F

Abstract:
A computer system having a burst transfer cycle for transferring data, comprising:an expansion bus having address signals and control signals, said control signals indicating the start and the end of the burst transfer cycle, the burst transfer cycle providing incremented address signals at periodic intervals in the burst transfer cycle; a decoder, said decoder coupled to the control signals of said expansion bus to detect the start and the end of the burst transfer cycle; a counter, said counter coupled to said decoder and said expansion bus, said counter storing said address signals at the start of said cycle, incrementing said stored address signals during said cycle and presenting the incremented address signals as a counter output in advance of the incremented address signals of the burst transfer cycle as provided on said expansion bus; and a multiplexer, said multiplexer coupled to the address signals of said expansion bus and to said counter output, said multiplexer coupling the counter output to said multiplexer output during the burst transfer cycle and coupling the address signals to said multiplexer output when the computer system is not performing said burst transfer cycle.