Patent ID: 6938193
Filing Date: 2005-08-30
Classification: G06F,G11C

Abstract:
1. An ECC circuit-containing semiconductor memory device comprising: error correcting code generation means including a circuit having a function to generate an error correcting code consisting of plural bits on the basis of a data consisting of plural bits; data storage means for storing said plural bits of said data; error correcting code storage means for storing said plural bits of said error correcting code; and decoding means including a circuit having a function to generate a syndrome for error correction by calculation processing on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, and a circuit having a function to correct an error of each bit of said data, wherein the functions of said error correcting code generation means and said decoding means are carried out by a shared circuit such that said shared circuit generates said error correcting code and said syndrome, said error correcting code generation means has a function to generate, in a test mode, a memory testing error correcting code such that a data row of said memory testing error correcting code has the same repeat pattern of a data row of said data on the basis of said data, and said pattern includes, as arbitrary two bits, four types of patterns: (0 0) (0 1), (1 0) and (1 1).