Patent ID: 7129097
Filing Date: 2006-10-31
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of making an integrated circuit chip, comprising the steps of: providing a chip substrate; forming a plurality of active devices on said substrate; forming at least one dielectric layer over said substrate and said active devices, said dielectric layer containing a plurality of electrically conductive vias for making electrical connections to said active devices; forming a conductive layer over said at least one dielectric layer, said step of forming a conductive layer comprising: (a) forming a first sublayer of carbon nanotubes oriented in a first direction parallel to said conductive layer, wherein said step of forming a first sublayer of carbon nanotubes comprises the steps of: (b) forming a second sublayer of carbon nanotubes oriented in a second direction parallel to said first conductive layer, said first direction and said second direction forming a non-zero angle, wherein said step of forming a second sublayer of carbon nanotubes comprises the steps of: