Patent ID: 6350694
Filing Date: 2002-02-26
Classification: G11C,H01L

Abstract:
A method of removing micro scratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structure, comprising the steps of:providing a semiconductor surface, at least one layer of dielectric having been deposited over said semiconductor surface, a pattern of interconnect metal having been created in the surface of said at least one layer of dielectric, a layer of metal having been deposited over the surface of said at least one layer of dielectric, filling said pattern of interconnect metal; chemical mechanical polishing said layer of metal having been deposited over the surface of said at least one layer of dielectric down to the surface of said pattern of interconnect metal created in the surface of said at least one layer of dielectric, creating a polished surface comprising exposed surfaces of said pattern of interconnect metal, said polished surface further comprising said at least one layer of dielectric; and plasma etching said polished surface.