Patent ID: 9012321
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of bit line structures on a substrate, the bit line structures being spaced apart from each other by a first groove, each of the bit line structures extending in a first direction and including a bit line and an insulation capping line, the substrate including an active region and a word line, the active region being defined by a device isolating film; forming a multi-film spacer on two side walls of each of the plurality of bit line structures, the multi-film spacer having an outermost region including a nitride film; exposing a part of a top surface of the active region by etching a lower insulating film of a bottom surface of the first groove by using the multi-film spacer as a mask; forming a sacrificial film in the first groove to cover the plurality of bit line structures and the multi-film spacer, the sacrificial film being including a spin on hardmask (SOH) material; forming a second groove by removing the sacrificial film that is exposed by a first mask pattern, the second groove extending in a second direction perpendicular to the first direction and exposing a region corresponding to the word line; forming a first insulating film in the second groove, the first insulating film including an oxide material; forming a third groove that exposes a part of a top surface of the active region by removing the remaining sacrificial film by using the first insulating film as a mask; forming a conductive film in the third groove such that the conductive film is electrically connected to the active region, the conductive film including a polysilicon material; removing a top portion of the conductive film; and forming a metal film to cover the conductive film, the first insulating film, the plurality of bit line structures, and the multi-film spacer.