Patent ID: 6836445
Filing Date: 2004-12-28
Classification: G11C

Abstract:
A memory device which includes at least one bank having first and second unit blocks, each containing a plurality of cell arrays and first and second decoding units for decoding an inputted column address and outputting column selecting signals of the first and second unit blocks, comprising:a column address transmitting unit for simultaneously enabling the first and second decoding unit, regardless of a bit select block signal, which selects the first or second unit blocks, of the inputted column address during a test mode; a first combining circuit for combining test data outputted by the column selecting signal of the first unit blocks and detecting an error of the test data in the test mode; a second combining circuit for combining test data outputted by the column selecting signal of the second unit blocks and detecting an error of the test data in the test mode; and a first and a second output pads for individually outputting each of outputted signals from the first and second combining circuits.