Patent ID: 6385123
Filing Date: 2002-05-07
Classification: G11C

Abstract:
An integrated circuit, comprising:a first decoder unit having a number 1 inputs for receiving input signals to be decoded and a number n outputs to be activated in dependence on the input signals; a second decoder unit connected in parallel with said first decoder unit, said second decoder unit having 1 inputs for receiving the input signals to be decoded differently from said first decoder unit and n outputs to be activated in dependence on the input signals; said inputs of said second decoder unit being connected to a respective one of said inputs of said first decoder unit; n lines to be selected and each connected to a respective one of said outputs of said first and second decoder units; in a first operating mode, said first decoder unit determining, via said outputs thereof, a potential of said lines to be selected, and, in a second operating mode, said second decoder unit determining, via said outputs thereof, the potentials of said lines to be selected; and said first decoder unit having at least one additional input for feeding in a further input signal for additionally influencing an activation of said outputs of said first decoder unit, and the further input signal received via said additional input of said first decoder unit determining a number of said outputs to be activated in each case simultaneously by said first decoder unit.