Patent ID: 6448121
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A process of forming a naturally high Vt P-MOS device simultaneously with N-MOS and P-MOS surface channel devices, comprising the steps of:forming N-tank regions; forming P-tank regions; forming transistor regions within the N-tank and P-tank regions; implanting P-type doping ions near the surface of the P-tank regions; implanting N-type doping ions near the surface of at least one of the transistor regions within the N-tank regions; forming gate oxide on each of the transistor regions; forming N-type polysilicon gate electrodes on the transistor regions in P-tank and N-tank regions while simultaneously forming at least one of undoped and P-type polysilicon gate electrode over other transistor regions within N-tank regions; implanting n-type doping ions into P-tank regions to form N-MOS transistor source/drain regions; and implanting p-type doping ions into N-tank regions to form P-MOS transistor source/drain regions while intentionally blocking the majority of the implant ions from penetration into the N-type polysilicon gate electrodes within N-tank regions.