Patent ID: 7468916
Filing Date: 2008-12-23
Classification: G11C

Abstract:
1. A row driving circuit of non-volatile memory for driving memory units of a first memory block and a second memory block according to an address, the address being decoded into a first decoding signal and a second decoding signal, the first memory block comprising N word lines, each word line of the first memory block being coupled to a plurality of memory units of the first memory block, the second memory block comprising N word lines, each word line of the second memory block being coupled to a plurality of memory units of the second memory block, the first memory block or the second memory block being selected by the row driving circuit according to the first decoding signal, a K th word line of the first memory block being selected according to the second decoding signal when the first memory block is selected, a K th word line of the second memory block being selected according to the second decoding signal when the second memory block is selected, the row driving circuit comprising: N level shift up circuits, wherein a K N level shift down circuits, wherein a K a first word line driving circuit comprising: a second word line driving circuit comprising: