Patent ID: 6084818
Filing Date: 2000-07-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged in rows and columns, and divided into a plurality of memory cell blocks in rows and columns;a plurality of main word lines in a row direction of said memory cell array, shared by a plurality of said memory cell blocks arranged in the row direction;a plurality of subordinate word lines corresponding to memory cell rows in said memory cell blocks, having a first plurality of subordinate word lines provided for each said main word line;a main row select circuit provided for said memory cell array, selectively activating said main word line in response to an address signal;a subordinate row select circuit provided for said memory cell array, indicating a selected subordinate word line of said first plurality of subordinate word lines in response to said address signal;a block select circuit indicating a selected memory cell block in response to said address signal;a plurality of block select lines activated in response to a selection indication from said block select circuit; anda plurality of drive circuits each provided for said subordinate word line, each driving a potential of an associated subordinate word line in response to an indication from said subordinate row select circuit and to activation of an associated said block select line and said main word line, each said drive circuit includinga first switch circuit transmitting a potential level from said main word line in response to activation of said block select line, anda hold circuit activated in response to an output level from said first switch circuit and to an indication from said subordinate row select circuit to hold selection indicating information for said associated subordinate word line and drive a potential of said associated subordinate word line; whereinsaid main row select circuit and said block select circuit reset a level of said main word line and a level of said block select line after said selection indicating information is transmitted to said hold circuit.