Patent ID: 8255837
Filing Date: 2012-08-28
Classification: G03F

Abstract:
1. A method of designing a double patterning mask set for a layout of a chip, the method comprising: designating a first pattern set; designating a second pattern set; designing a cell comprising a left boundary and a right boundary, wherein all left-boundary patterns in the cell are in a same pattern set selected from a pattern set group substantially comprising the first pattern set and the second pattern set, and all right-boundary patterns in the cell are in a same pattern set selected from the pattern set group; switching the left-boundary patterns to a different pattern set in the first pattern set and the second pattern set; switching the right-boundary patterns to a different pattern set in the first pattern set and the second pattern set; creating a first patterned mask by transferring patterns in the first pattern set into a first mask of the double patterning mask set; and creating a second patterned mask by transferring patterns in the second pattern set into a second mask of the double patterning mask set.