Patent ID: 8426309
Filing Date: 2013-04-23
Classification: B82Y,C01B,H01L

Abstract:
1. A method of manufacturing a solid state electronic nanostructure including at least one graphene layer segment, comprising the steps of: depositing or forming the graphene layer segment on a support; depositing a protective sacrificial layer over the graphene layer segment; depositing an electrically insulating layer over the protective sacrificial layer; etching one or more openings in the electrically insulating layer; removing the protective sacrificial layer to form a cavity between the graphene layer segment and the electrically insulating layer, thereby passivating the graphene layer segment; depositing an electrically conductive material into the one or more openings in the electrically insulating layer to form one or more electrical contacts with the graphene layer segment; and depositing or forming one or more additional solid state electronic nanocomponents on or above the electrically insulating layer in electrical contact with the graphene layer segment through said electrical contacts.