Patent ID: 8601536
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A bus monitor for enhancing system security of system on chip, it is characterized in that the bus monitor disposed between a system bus and a system control unit comprises a configuration unit, a condition judgment unit, an effective data selection unit, a hardware algorithm unit and a comparative output unit, wherein: the configuration unit is adapted to install and store a configured information required to be monitored from a bus control signal and to update the state of the bus monitor; the condition judgment unit is incorporated with a current bus behavior information given by the bus control signal, based on the configured information of the configuration unit, to determine whether a monitoring process shall be enabled, and a control signal is produced to the effective data selection unit if the monitoring process is required; the effective data selection unit, based on a control information of the condition judgment unit and the configured information of the configuration unit, transmits a bus monitoring to-be-calculated data which is selected from a bus address of bus access, a bus master device number, a bus reading data or writing data, and a secret key in the configuration unit to the hardware algorithm unit and informs the hardware algorithm unit to operate the to-be-calculated data; the hardware algorithm unit, based on the control signal transmitted from the configuration unit and the condition judgment unit, operates the to-be-calculated data output from the effective data selection unit and transmits a final calculation result to the comparative output unit; and the comparative output unit compares the output result of the hardware algorithm unit with a preset condition of the configuration unit and transmits an alarm signal to the system control unit if the output result of the hardware algorithm unit is discordance with the preset condition of the configuration unit.