Patent ID: 9196352
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A static random access memory (SRAM) unit cell layout structure, comprising: a semiconductor substrate comprising a first active area and a second active area parallel to the first active area; a first gate line passing through a surface of the first active area and a surface of the second active area; a first slot contact disposed on the first active area and the second active area both on a same side of the first gate line; a third active area and a fourth active area both parallel to the second active area, the second active area positioned between the first active area and the third active area, the third active area positioned between the second active area and the fourth active area; a second gate line passing through a surface of the third active area and a surface of the fourth active area; and a second slot contact disposed on the third active area and the fourth active area both on a same side of the second gate line.