Patent ID: 8856197
Filing Date: 2014-10-07
Classification: G06F

Abstract:
1. A system for processing data, the system comprising: a matrix of N rows and M columns of processing units, where N and M are integers greater than zero, wherein each processing unit includes at least one logic circuit and each logic circuit is configured to perform a bit operation; memory configured to store an array of N rows and M columns of commands, wherein each command of the array of N rows and M columns of commands defines a configuration of the bit operation of one processing unit of the matrix of N rows and M columns of processing units; a controller configured to control the matrix of N rows and M columns of processing units using the array of N rows and M columns of commands stored in the memory to process at least one input data word having N bits to generate at least one output data word having M bits; and wherein the at least one logic circuit includes a first logic circuit configured to performs a bit copy operation to copy a value of one or more input data bits to one or more output data bits, a second logic circuit configured to perform a bit set operation to set values of the one or more output data bits to one, a third logic circuit configured to perform a bit reset operation to set the values of the one or more output data bits to zero, and a fourth logic circuit configured to perform of a bit inverse operation to set the values of one or more output data bits to complements of the values of the one or more input data bits.