Patent ID: 7885130
Filing Date: 2011-02-08
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a K (K is a natural number greater than or equal to 2) number of memory cells that are connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N (N is a natural number greater than or equal to 2) number of groups; and an N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, wherein after a sense amplifier circuit of a first group terminates operation., a sense amplifier circuit of a second group different from the first group operates, and subsequent sense amplifier circuits sequentially operate before a sense amplifier circuit of an n-th group operates, and each of the N number of data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits.