Patent ID: 6085208
Filing Date: 2000-07-04
Classification: G06F,H03M

Abstract:
A microprocessor, comprising:a leading one prediction unit configured to predict a position of a leading one value within a result mantissa value corresponding to a first floating point subtraction operation performed upon a first floating point number and a second floating point number, wherein said leading one prediction unit is coupled to receive a first operand corresponding to said first floating point number and a second operand corresponding to said second floating point number, wherein said leading one prediction unit is configured to generate a prediction string including a prediction value for each bit position within said result mantissa value, wherein each prediction value within said prediction string is generated by utilizing values from a second bit position within said first operand and from a first bit position within said second operand, wherein an indication of said position of said leading one value within said result mantissa value is given by a bit position of a most significant asserted prediction value within said prediction string;wherein said prediction string is generated according to a prediction that said first floating point number includes a first exponent value that is one greater than a second exponent value included in said second floating point number.