Patent ID: 6316311
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of forming borderless contacts, which is applied to form an embedded dynamic random access memory on a substrate having at least a metal oxide semiconductor transistor located at a logic region of the substrate, which comprises a gate, a source/drain region and a cap insulating layer on the gate, and a shallow trench isolation structure thereon, comprising the steps of:forming an etching step layer on the substrate to cover the metal oxide semiconductor transistor and the shallow trench isolation structure;forming a dielectric layer on the etching stop layer;forming a defined first mask layer on the dielectric layer, wherein the defined first mask layer has a first opening over the gate and wherein a portion of the dielectric layer is exposed in the first opening;removing the dielectric layer exposed in the first opening, the etching stop layer and the cap insulating layer under the exposed dielectric layer to form a first contact window exposing the gate;removing the defined first mask layer;forming a defined second mask layer on the dielectric layer, wherein the defined second mask layer has a second opening over the source/drain region and a portion of the shallow trench isolation, wherein a portion of the dielectric layer is exposed in the second opening;removing the dielectric layer exposed by the second opening and the etching stop layer to form a second contact window exposing the source/drain region of the same metal oxide semiconductor transistor and a portion of the shallow trench isolation; andremoving the defined second mask layer.