Patent ID: 6785842
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A method for error recovery in a RISC data processing system having a pipeline history cache and a pipeline including multiple stages, comprising the steps of:fetching a plurality of instructions, wherein fetching a plurality of instructions comprises sequentially fetching a plurality of instructions, each instruction having an instruction fetch address; storing the instruction fetch address of each instruction in the pipeline history cache after fetching the respective instruction, wherein the pipeline history cache comprises a memory register file including a stage register for each pipeline stage; executing or at least partially executing each instruction after fetching the respective instruction to hereby generate a result for the respective instruction; validating the result of each instruction prior to executing or at least partially executing each subsequent instruction; implementing a state change for each instruction in response to validating the result of the respective instruction; and if an error is detected in said step of validating the result of an instruction, then performing the following steps: fetching the respective instruction utilizing the instruction fetch address stored in the pipeline history cache, and re-executing or at least partially re-executing the respective instruction.