Patent ID: 8311126
Filing Date: 2012-11-13
Classification: G06F,G09G

Abstract:
1. A receiver, including: circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, wherein the sequence of K-bit fragments is a sequence of M-fragment groups, each of the fragments in each of the groups has a different phase within the group, the circuitry is configured to recover the K-bit words of video data during active video intervals and to recover packing phase data that have been transmitted to at least some of the inputs during at least some blanking intervals between the active video intervals, the packing phase data indicate the phase of one of the fragments transmitted at a known checkpoint, and the circuitry is configured to generate at least one control bit in response to the packing phase data and to assert each said control bit to the subsystem to set said subsystem in a state corresponding to said phase of said one of the fragments transmitted at the known checkpoint.