Patent ID: 9081061
Filing Date: 2015-07-14
Classification: G01R

Abstract:
1. A scan flip-flop, comprising: a multiplexer; a flip-flop having an input connected to an output of the multiplexer; and a logic circuit, wherein the flip-flop includes a transmission gate for transferring a signal from the input of the flip-flop to an output of the scan flip-flop, wherein the transmission gate includes first and second sets of switches, the first and second sets including respective first and second clock-controlled switches, wherein the first and second clock-controlled switches are connected in parallel with one another, and wherein each of the first and second sets of switches includes a first switch and a second switch, and wherein the logic circuit, in a first mode of operation, enables clock signals for reception by the first and second switches of the first and second sets of switches of the transmission gate, and in a second mode of operation, inhibits the clock signals from reaching the first and second clock-controlled switches of the first and second sets of switches of the transmission gate.