Patent ID: 6114725
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A semiconductor memory device comprising:a substrate:an array of cells having pillars formed on said substrate, said pillars being arranged in rows and columns, said rows forming bitlines of said cell and said columns forming wordlines of said cell, each of said pillars extending upward and having an upper region doped with a first type of impurity, a middle region doped with a second type of impurity, and a lower region doped with said first type of impurity, said middle region being between said upper and lower regions;gate regions formed on pillar sidewalls which are opposite each other along said rows, over said middle region to control the resistance between said upper and said lower regions; and isolation regions formed on one sidewall of alternating pillars along said rows, functionally isolating each pillar from one of said gate regions for preventing one of said gate regions from turning on a pillar device of said memory device.