Patent ID: 7836374
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A method of operating a processor-based system having a memory controller and a memory module containing a memory device, the method comprising: storing in the memory module identifying information corresponding to memory cells having relatively weak data retention characteristics; transferring the identifying information from the memory module to the memory controller; generating first refresh addresses in the memory device by incrementing a counter in the memory device, generating second refresh addresses in the controller by incrementally counting in synchronism with the incrementing of the counter in the memory device so that the second refresh addresses generated in the controller correspond to respective ones of the first refresh addresses generated in the memory device; determining in the memory controller a third refresh address corresponding to memory cells currently being refreshed in the memory device by using the second refresh addresses generated in the controller; comparing each of the second refresh addresses to the identifying information transferred to the memory controller to identify a characteristic of the identifying information that matches the characteristic of each of the third refresh addresses; and in the event a match is found, refreshing the memory cells corresponding to the identifying information that is being compared to each of the third refresh addresses.