Patent ID: 8722501
Filing Date: 2014-05-13
Classification: H01L

Abstract:
1. A method for manufacturing multi-gate transistor device, comprising: providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer formed thereon, and the gate layer covering a portion of the patterned semiconductor layer, wherein the patterned semiconductor layer protrudes from a surface of the semiconductor substrate and comprises sidewalls perpendicular to the surface of the semiconductor substrate; forming a multiple insulating layer on the semiconductor substrate, the multiple insulating layer covering the patterned semiconductor layer and the gate layer, wherein the multiple insulating layer sequentially comprises a first insulating layer a second insulating layer and a third insulating layer sandwiched between the first insulating layer and the second insulating layer; performing a first etching process to remove a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer on the sidewalls of the patterned semiconductor layer; performing a second etching process to remove the second spacer and a portion of the first spacer to form a third spacer around the gate layer, and simultaneously to expose a portion of the third insulating layer, wherein the first insulating layer and the third insulating layer still covering the patterned semiconductor layer; performing a third etching process to remove the exposed third insulating layer to expose the first insulating layer, and the first insulating layer still covering the patterned semiconductor layer; and removing the exposed first insulating layer to expose the patterned semiconductor layer.