Patent ID: 8748934
Filing Date: 2014-06-10
Classification: H01L

Abstract:
1. A vertical selection transistor, comprising: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively, in which a vertical MOS transistor comprises the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the gate stack, and a vertical diode comprises the third semiconductor layer and the fourth semiconductor layer; and wherein a thickness of each of the first, second, third and fourth semiconductor layers is within a range from 10 nm to 200 nm.