Patent ID: 8410611
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a semiconductor substrate having an internal circuit at an upper portion thereof; an interlayer insulating layer disposed on the internal circuit; at least one internal power line and at least one internal ground line extending over the semiconductor substrate and at least one of which is disposed on or in the interlayer insulating layer, and each said at least one internal power line being electrically connected to a power terminal of the internal circuit, and each said at least one internal ground line being electrically connected to a ground terminal of the internal circuit; a power chip pad and a ground chip pad disposed on the interlayer insulating layer; a passivation layer extending over the interlayer insulating layer; a redistributed power line, wherein one portion of the redistributed power line extends over the passivation layer, and other portions of the redistributed power line pass through the passivation layer and are electrically conductively connected to the at least one internal power line and to the power chip pad, respectively, such that the redistributed power line directly electrically connects the at least one internal power line to the power chip pad; and a redistributed ground line, wherein one portion of the redistributed ground line extends over the passivation layer, and other portions of the redistributed ground line pass through the passivation layer and are electrically conductively connected to the at least one internal ground line and to the ground chip pad, respectively, such that the redistributed ground line directly electrically connects the at least one internal ground line to the ground chip pad.