Patent ID: 6404670
Filing Date: 2002-06-11
Classification: G11C,H01L

Abstract:
A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further comprising:a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells; a memory cell read/write voltage control means for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array; and a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.