Patent ID: 6683928
Filing Date: 2004-01-27
Classification: H03L

Abstract:
A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay segment and a coarse delay segment, the delay compensation circuit comprising:(a) a system clack input receiving system clock; (b) a first path coupled to the system clock input, the first path consisting of a plurality of controllable fine delay elements; (c) a second path coupled to the system clock input in parallel with the fine delay elements, the second path including a single coarse delay element; (d) a phase detector having a pair of inputs coupled to outputs from the first and second path and a pair of outputs; and (e) a counter having inputs coupled to the outputs from the phase detector and to the system clock, for providing an output result for adjusting the number of fine delay elements in the first path; and (f) the counter providing said output result to a fine delay counter of in the main delay line when delays of the first and second paths are substantially equal.