Patent ID: 8856490
Filing Date: 2014-10-07
Classification: G06F

Abstract:
1. A system for accessing multiple page sizes in a memory, the system comprising: a control device issuing a virtual address of a requested memory page within a memory storage device, said virtual address (VA) having a first number of bits forming an effective address (EA) corresponding to a physical address of a requested memory page; and a translation look-aside buffer (TLB) having page table entries, each page table entry having effective page number (EPN) field and page size field indicating a memory page size, said EPN and page size field used in mapping said virtual address (VA) to a corresponding physical memory address location of an associated memory page, and each said table entry providing an exclusion bit of a first logic value set to enable access to said whole page excluding a smaller page size range within the memory page, a logic device receiving said VA and evaluating said effective address portion against a corresponding effective page number field of each said one or more page table entries to match said VA to said physical address of a requested memory page, said logic device returning a physical address that maps to the portion of the memory page outside the smaller page size range when said exclusion bit is set for that table entry.