Patent ID: 8563376
Filing Date: 2013-10-22
Classification: B82Y,H01L

Abstract:
1. A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate and a top semiconductor layer on the buried insulating layer, the semiconductor hybrid structure comprising: a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one bulk CMOS device directly on the semiconductor substrate; the at least one nanowire mesh device comprising: a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate such that the top semiconductor layer forms a part of the semiconductor nanowires, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region including a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region; the at least one bulk CMOS device comprising: a semiconductor layer directly on the semiconductor substrate and only in the bulk CMOS device; and a gate region including a gate conductor over at least a portion of the semiconductor layer.