Patent ID: 6845140
Filing Date: 2005-01-18
Classification: G09G,G11C

Abstract:
1. A shift register including a plurality of cascade-connected stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising: a carry buffer for providing a next stage with a carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having an inverted phase with respect to the first clock signal; a pull-up part for providing an output terminal with a first scan line driving signal corresponding to the first clock signal or the second clock signal; a pull-down part for providing the output terminal with a first power voltage; a pull-up driver part for turning on the pull-up part in response to the carry signal provided from a previous stage and turning off the pull-up part in response to a is second scan line driving signal of the next stage; and a pull-down driver part for turning off the pull-down part in response to the carry signal provided from the previous stage and turning on the pull-up part in response to the second scan line driving signal of the next stage.