Patent ID: 7761721
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. An environmentally hardened architecture comprising: at least one hybrid processor including an environmentally-hardened processing section and an environmentally-sensitive processing section; a high speed bus having environmentally-sensitive interfaces, at least one environmentally-sensitive interface configured to pass data to and from the environmentally-sensitive processing section of the at least one hybrid processor and at least one environmentally-sensitive interface configured to pass data to and from the environmentally-hardened processing section of the at least one hybrid processor; an environmentally hardened bus having environmentally-hardened interfaces, at least one environmentally-hardened interface configured to pass data to and from the environmentally-hardened processing section of the at least one hybrid processor; and an environmentally-hardened processor communicatively coupled to at least one environmentally-sensitive interface of the high speed bus and communicatively coupled to at least one environmentally-hardened interface of the environmentally hardened bus, wherein the environmentally-hardened processor is configured to process critical applications in the environmentally-hardened processing section of the at least one hybrid processor during an environmental event.