Patent ID: 8610467
Filing Date: 2013-12-17
Classification: G11C

Abstract:
1. A sample and hold circuit, comprising: a plurality of switches; a first capacitor selectively coupled to a first input signal by at least one of the plurality of switches; an operational amplifier having a first input selectively coupled to the first capacitor by at least one of the plurality of switches, a second input, and a first output; a second capacitor selectively coupled to the first capacitor by at least one of the plurality of switches and selectively coupled between the first input of the operational amplifier and the first output of the operational amplifier by at least one of the plurality of switches; a third capacitor selectively coupled to the first capacitor by at least one of the plurality of switches and selectively coupled between the first input of the operational amplifier and the first output of the operational amplifier by at least one of the plurality of switches, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample the first input signal in a sample phase, the first capacitor is configured to transfer a charge based on the sampled first input signal to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and the third capacitor are configured to alternate between holding the transferred charge and resetting in back-to-back hold phases, wherein in the hold phase when the first capacitor is coupled to the second capacitor, the third capacitor is ohmically isolated from the first capacitor and the second capacitor.