Patent ID: 9087601
Filing Date: 2015-07-21
Classification: G11C

Abstract:
1. A method of operating non-volatile storage that includes a plurality of non-volatile storage elements arranged as NAND strings and a plurality of word lines, each of the NAND strings having a first select transistor at a first end of the NAND string and a second select transistor at a second end of the NAND string, wherein the first select transistor is coupled to a first select line and the second select transistor is coupled to a second select line, wherein each of the NAND strings is associated with a bit line out of a plurality of bit lines and each of the NAND strings is associated with a common source line, the method comprising: applying a sequence of programming voltages to a selected word line of the plurality of word lines during a programming process having a plurality of program loops, the selected word line associated with a group of the non-volatile storage elements; locking out non-volatile storage elements that pass programming in a given program loop from being programmed in future program loops of the programming process; and applying a gate-to-source voltage (Vgs) to the first select transistor of a first of the NAND strings while applying each of the programming voltages to the selected word line, including applying a first voltage to the first select line and a second voltage to either the bit line associated with the first NAND string or the common source line associated with the first NAND string while applying the programming voltage for a given program loop to the selected word line, including progressively lowering the maximum magnitude of the difference of the first voltage minus the second voltage from one program loop to the next program loop a plurality of times, wherein the maximum magnitude has a high level, a low level, and at least one intermediate level for different program loops when the first NAND string is not selected for programming.