Patent ID: 6810475
Filing Date: 2004-10-26
Classification: G06F

Abstract:
A digital system having a processor comprising a processor pipeline with a plurality of pipeline stages, a plurality of protected resources connected to receive data from certain ones of the plurality of pipeline stages and a pipeline protection mechanism, wherein the pipeline protection mechanism comprises:a set of shadow registers; interlock circuitry for anticipating a particular access conflicts for each protected resource of the plurality of protected resources between the pipeline stages, an output of the interlock detection circuitry being controllably connected to the set of shadow registers, the interlock circuitry comprising a stall vector filter, wherein the stall vector filter has a plurality of select filter stages connected in a serial manner such that each of the select filter stages is associated with a corresponding protected resource; and the set of shadow registers being interconnected with the processor pipeline such that a particular data item from a first pipeline stage can be redirected from a protected resource into a selected shadow register only in response to an the particular access conflict anticipated by the interlock circuitry so that a resource access conflict is resolved without stalling the processor pipeline.