Patent ID: 9159649
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A microelectronic package comprising: a microelectronic die; a plurality of electrically conductive layers; a plurality of electrically insulating layers including: a first electrically insulating layer closer to the microelectronic die than any other electrically insulating layer, the first electrically insulating layer having a first glass transition temperature, a first coefficient of thermal expansion, and a first modulus of elasticity; a second electrically insulating layer having a second glass transition temperature, a second coefficient of thermal expansion, and a second modulus of elasticity, wherein the second modulus of elasticity is greater than the first modulus of elasticity; and a third electrically insulating layer having a third glass transition temperature, a third coefficient of thermal expansion, and a third modulus of elasticity, wherein: the second coefficient of thermal expansion at a temperature less than the second glass transition temperature is less than the first coefficient of thermal expansion at a temperature less than the first glass transition temperature; and the third coefficient of thermal expansion at a temperature greater than the third glass transition temperature is less than the first coefficient of thermal expansion at a temperature greater than the first glass transition temperature.