Patent ID: 9166025
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A method, comprising: forming a fin in a semiconductor substrate; performing at least one first epitaxial deposition process to form at least one layer of epi semiconductor cladding material around an exposed portion of said fin; performing at least one etching process to pattern said at least one layer of cladding material and said fin, thereby resulting in a patterned portion of said fin being positioned under the patterned said at least one layer of cladding material, said patterned at least one layer of cladding material having an upper portion and a plurality of substantially vertically oriented legs extending downward from said upper portion; performing at least one etching process to selectively remove said patterned fin relative to said patterned at least one layer of cladding material and thereby form an opening under said patterned at least one layer of cladding material; forming a sacrificial gate structure all around at least a portion of said upper portion of said at least one layer of cladding material; with said sacrificial gate structure in position, performing a second epitaxial deposition process to form an epi semiconductor source/drain region on each of said substantially vertically oriented legs; removing said sacrificial gate structure; and forming a final gate structure all around at least a portion of said upper portion of said at least one layer of cladding material.