Patent ID: 8261222
Filing Date: 2012-09-04
Classification: G01R,G06F

Abstract:
1. A method of analyzing a semiconductor device, which analyzes a defect caused by a variation in the semiconductor device having a circuit driven by a clock signal, the method comprising: predicting a variation in the semiconductor device using timing information, which is information as to how much variation in the clock signal must be produced to result in non-operation of the circuit, the timing information being included in design data information of the semiconductor device; testing an operation state of the semiconductor device targeted for analysis, using a semiconductor test equipment; analyzing a cause of non-operation of the semiconductor device, based upon a prediction result of the variation and a test result of the operation state of the semiconductor device; analyzing a cause of non-operation by the method of analyzing the semiconductor device, wherein a semiconductor device in which the timing operation is rendered adjustable by insertion of a delay after fabrication is adopted as a target of analysis; deciding an insertion position of a delay and a delay amount to be inserted in the semiconductor device, based upon an analysis result of the cause of the non-operation; and inserting a delay of the decided amount at the decided delay insertion position in the semiconductor device to adjust the semiconductor device; with regard to the semiconductor device including first and second flip-flops each supplied with a common clock signal for outputting data in response to the clock signal, the second flip-flop receiving as an input output data from the first flip-flop, in predicting the variation of the semiconductor device, deriving a signal propagation time between the first and second flip-flops of the semiconductor device from design data of the semiconductor device, in advance; in inspecting operation state of the semiconductor device, setting a prescribed value to a data input of the first flip-flop in the semiconductor device; causing the first and second flip-flops to operate at a prescribed clock period; and deciding operation/non-operation of the second flip-flop by comparing output data of the second flip-flop with an expected value; and in deciding the delay insertion position and an amount of delay, in a case where the second flip-flop is in non-operation owing to a variation between a clock arrival time of the first flip-flop and a clock arrival time of the second flip-flop, based upon a determination that a difference has developed between the clock arrival time of the first flip-flop and the clock arrival time of the second flip-flop that will not satisfy a prescribed conditional expression defined in relation to the difference between the clock arrival time of the first flip-flop and the clock arrival time of the second flip-flop, the signal propagation time between the first and second flip-flops derived in advance, and the clock period; inserting a first and/or second delay into a clock signal path to a clock path to the first flip-flop and/or clock path to the second flip-flop in such a manner that the difference between the clock arrival time of the first flip-flop and the clock arrival time of the second flip-flop will satisfy the prescribed conditional expression in relation to the signal propagation time between the first and second flip-flops and the clock period; and adjusting a variation, which prevails at time of fabrication, in the clock path to the first and/or the second flip-flop.