Patent ID: 8547719
Filing Date: 2013-10-01
Classification: G11C

Abstract:
1. A stacked memory device comprising: a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells; a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information; and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit, wherein the at least one second active circuit unit includes a plurality of main decoders, each of the at least one second active circuit interposed between at least two of the memory layers, and wherein the first active circuit unit, the at least one second active circuit unit, and the memory layers are in separate layers from each other.