Patent ID: 6321297
Filing Date: 2001-11-20
Classification: G06F

Abstract:
An apparatus comprising:a plurality of cache memories arranged into a cache hierarchy to cache data resident at a storage location accessed by a processor, each of said plurality of cache memories having a separate location field for every other of said plurality of cache memories that is higher in the cache hierarchy than said each of said plurality of cache memories, wherein at least one of said plurality of cache memories has a cache line containing an address tag corresponding to an address of said storage location, said cache line also having said data stored therein;a write buffer coupled to said processor and at least one of said cache memories and having resident therein new data which is to be written from said processor to said storage location and also to said cache line, if said address tag corresponding to said address of said storage location is present in said at least one of said cache memories; andsaid write buffer also including with said new data, location information as to where in said at least one of said cache memories said address tag is located if said address tag is present in said at least one of said cache memories, said location information having been retrieved from said at least one of said cache memories in response to a cache access;wherein said write buffer includes a separate field for each of said at least one of said cache memories to store said location information;wherein said location information in said write buffer eliminates a need for a tag compare to write said new data to said at least one of said cache memories.