Patent ID: 6509223
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A method for making an embedded memory metal oxide semiconductor (MOS), the method comprising:providing a semiconductor wafer, with a memory array area and a periphery circuits region defined on the surface of a silicon substrate of the semiconductor wafer; forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer; performing a first ion implantation process in the undoped polysilicon layer in the memory array area to transform the undoped polysilicon layer in the memory array area into a doped polysilicon layer; forming a protective layer and a first photoresist layer, respectively, on the surface of the semiconductor wafer; performing a first photolithographic process so as to define a plurality of gate patterns in the first photoresist layer in the memory array area; applying the patterns in the first photoresist layer as a hard mask for etching the protective layer and the doped polysilicon layer in the memory array area down to the surface of the first dielectric layer; performing a second ion implantation process for forming lightly doped drains(LDD) of a plurality of MOS devices in the memory array area; removing the first photoresist layer; forming a first silicon nitride layer and a second dielectric layer, respectively, on the surface of the semiconductor wafer and covering the surfaces of each gate in the memory array area; removing the second dielectric layer, the first silicon nitride layer and the protective layer in the periphery circuits region; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second photolithographic process so as to define a plurality of gate patterns in the second photoresist layer in the periphery circuits region; applying the patterns in the second photoresist layer as a hard mask to etch the undoped polysilicon layer in the periphery circuits region down to the surface of the first dielectric layer, so as to form gates of a plurality of MOS devices in the periphery circuits region; performing a third ion implantation process so as to form lightly doped drains(LDD) of each MOS device in the periphery circuits region; removing the second photoresist layer; forming a second silicon nitride layer on the surface of the semiconductor wafer, and covering the surfaces of each gate in the periphery circuits region; performing an etching process for removing part of the second silicon nitride layer in the periphery circuits region so as to form a spacer on either side of each gate in the periphery circuits region; and performing a fourth ion implantation process so as to form a source and drain of each MOS in the periphery circuits region.