Patent ID: 6441436
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A DRAM unit comprising:a SOI substrate including: a first insulating layer formed on a substrate; a first semiconductor layer having a first conductivity type positioned on the first insulating layer; a second insulating layer formed on the first semiconductor layer; and a second semiconductor layer having a first conductivity type formed on the second insulating layer; a MOS transistor including a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively; a first oxidation region formed in the first semiconductor layer below the source; and a second oxidation region formed in the first semiconductor layer below the drain; wherein both the first and the second oxidation region are contiguous with the second insulating layer, but not with the first insulating layer, wherein applying a bias voltage to the first semiconductor layer via a well pick-up having a first conductivity type in the SOI substrate to allow the first and second oxidation regions to reduce the source/drain parasitic capacitance.