Patent ID: 8384451
Filing Date: 2013-02-26
Classification: H03L

Abstract:
1. A PLL circuit comprising: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count a clock pulse of an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output the interval as a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to normalize the third counted value into a first phase difference corresponding to the number of clock pulses of the output clock signal; an operating circuit to obtain a subtraction value by subtracting the first phase difference from the second counted value and to subtract the subtraction value from the first counted value to generate a phase difference signal indicating a second phase difference between the reference clock signal and the output clock signal; and an oscillator circuit to change a frequency of the output clock signal based on the phase difference signal, wherein the phase difference normalizing circuit changes the normalizing coefficient until the second phase difference at a first value and the second phase difference at a second value appear at random when the second phase difference at the first value or the second phase difference at the second value consecutively appears after the PLL is locked.