Patent ID: 7577040
Filing Date: 2009-08-18
Classification: G11C,H01L

Abstract:
1. A memory device having a plurality of dual port static random access memory (SRAM) cells, each of which comprises: at least one pair of cross-coupled inverters connected between a power line and complementary power line; a first pass gate transistor connecting the cross-coupled inverters to a first bit line; a second pass gate transistor connecting the cross-coupled inverters to a first complementary bit line; a third pass gate transistor connecting the cross-coupled inverters to a second bit line; a fourth pass gate transistor connecting the cross-coupled inverters to a second complementary bit line, wherein the first bit line, the first complementary bit line, the second bit line, and the second complementary bit line are located on a first metal layer in the memory device; a first word line coupled to gates of the first and second pass gate transistors, located on a second metal layer in the memory device; and a second word line coupled to gates of the third and fourth pass gate transistors, located on a third metal layer in the memory device, wherein the first, second and third metal layers are at different levels, and wherein the second metal layer is higher than the first metal layer and the third metal layer is higher than the second metal layer.