Patent ID: 6157237
Filing Date: 2000-12-05
Classification: G06F,H03K

Abstract:
A clock distribution network having n levels, n being an integer greater than 1, the clock distribution network comprising:a logic circuit having:a plurality of first predefined areas, each of said first predefined areas containing substantially only clocked logic elements; anda second predefined area containing substantially only unclocked logic elements; anda (n-1)th-level buffer disposed outside of said logic circuit and coupled to one of said first predefined areas in said plurality of first predefined areas,wherein said (n-1)th-level buffer is configured to output a clock signal;said one of said first predefined areas contains a plurality of nth-level buffers, each nth-level buffer of said plurality of nth-level buffers being coupled to receive said clock signal outputted by said (n-1)th-level buffer;each said nth-level buffer of said plurality of nth-level buffers is further configured to distribute said clock signal from said (n-1)th-level buffer to a predetermined number of said clocked logic elements in said one of said first predefined areas, said predetermined number of said clocked logic elements being selected from a finite set of allowed numbers of clocked logic elements wherein said finite set includes a plurality of said allowed numbers of clocked logic elements; andanother (n-1)th level buffer wherein said (n-1)th-level buffer and said another (n-1)th level buffer are a plurality of (n-1)th-level buffers; and said another (n-1)th-level buffer is coupled to another plurality of said nth level buffers, said another plurality of said nth level buffers being contained in another first predefined area of said plurality of first predefined areas.