Patent ID: 7110279
Filing Date: 2006-09-19
Classification: G11C

Abstract:
1. A memory comprising: a plurality of bit lines; a plurality of word lines arranged to intersect with said plurality of bit lines; and a plurality of storage means, each connected at an intersection of said plurality of bit lines and said plurality of word lines, wherein a selected at least one of said plurality of word lines and a selected at least one of said plurality of bit lines corresponding to non-rewritten one of said plurality of storage means are activated while keeping a potential difference therebetween at a level not more than a prescribed value, and wherein a length of a period is differentiated for applying a voltage for rewriting to said selected at least one of said plurality of word lines and to said selected at least one of said plurality of bit lines corresponding to a rewritten one of said plurality of storage means from the length of a transition period of the potential of at least either said selected one of said plurality of word lines or said selected one of said plurality of bit lines corresponding to said non-rewritten one of said plurality of storage means, when performing a read operation on a selected one of said plurality of said storage means connected to said selected one of said plurality of word lines, and thereafter performing a rewrite operation on at least one of selected plurality of storage means or performing no rewrite operation on said selected one of said plurality of storage means.