Patent ID: 7975170
Filing Date: 2011-07-05
Classification: G11C

Abstract:
1. An integrated circuit device, comprising: an array containing a plurality of memory cells; and a refresh scheduler configured to refresh the memory cells according to a plurality of refresh intervals, wherein a first memory cell is assigned a first refresh interval, and a second memory cell is assigned a second refresh interval, the refresh intervals being assigned to one of first or second refresh interval categories; a memory accessible by the refresh scheduler, the memory storing the refresh intervals assigned to each of the memory cells; a frequency generator outputting a predetermined base frequency; first and second counters associated with the first and second refresh interval categories, the first and second counters each receiving an output of the frequency generator; the refresh scheduler generating refresh pulses for refreshing the memory pages in accordance with the associated refresh intervals in response to the counters, and wherein the refresh scheduler is configured to pipeline refresh executions in response to the indication of the first or second refresh interval.