Patent ID: 6885598
Filing Date: 2005-04-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a shared-scheme sense amplifier; a bit line connected to the sense amplifier; first and second select transistors arranged on both sides of the sense amplifier and connected to the bit line; a first memory cell array connected to the bit line via the first select transistor, the first memory cell array including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor; a second memory cell array connected to the bit line via the second select transistor, the second memory cell array including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor; a setting circuit which controls the first and second select transistors, thereby setting the first and second memory cell arrays in an operative state at the same time; and a control circuit which performs a test at the same time for the first and second memory cell arrays, which are set in the operative state at the same time by the setting circuit.