Patent ID: 8158446
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing an insulating layer on a semiconductor substrate; forming a groove portion in a dicing region of said insulating layer and forming a via hole in an internal circuit formation region of said insulating layer; providing a first resist film on said insulating layer; providing a second resist film to cover said first resist film; selectively removing said second resist film, forming an interconnect opening according to an interconnect trench in a region covering an internal circuit formation region of said second resist film, and forming a position aligning opening in a region covering said dicing region of said second resist film; detecting a positional relationship between said groove portion formed in said insulating layer and said position aligning opening of said second resist film so as to detect whether said interconnect opening of said second resist film exists at a predetermined position with respect to said via hole of said insulating layer; and when it is detected that said interconnect opening of said second resist film exists at said predetermined position, selectively removing said first resist film and said insulating layer in accordance with said interconnect opening of said second resist film and said position aligning opening, and forming an interconnect trench according to said interconnect opening of said second resist film and an opening according to said position aligning opening of said second resist film in said insulating layer, wherein, in said selectively removing of the second resist film, when said semiconductor substrate is seen in plan view from the side of a substrate surface, a region of said position aligning opening is formed to cover said groove portion.