Patent ID: 6222210
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A single wafer single metal periodic table group III-V semiconductor material enhancement mode field-effect transistor p-channel and n-channel complementary pair device comprising the combination of:a plurality of periodic table group III-V semiconductor material layers received on a wafer substrate member, said layers including a buried undoped charge carrier channel layer;a masking inorganic dielectric material layer covering an outermost of said semiconductor material layers and having selected mask apertures therein;a p-channel transistor gate window aperture through at least one semiconductor layer covering said channel layer, said p-channel gate window aperture being in registration with one of said masking inorganic dielectric material layer mask apertures;a p-channel transistor Schottky barrier gate element received in charge carrier flow-controlling proximity of said channel layer in said p-channel transistor gate window aperture;p-channel transistor source and drain current conductor elements located on charge carrier flow upstream and downstream sides of said p-channel gate window aperture and each comprising stacks of locally doped registered successive layer semiconductor material extending orthogonal of said semiconductor material layers between conductor element ends at said outermost semiconductor material layer and at said channel layer;p-channel transistor source and drain ohmic contact elements received on said outermost semiconductor material layer each in registration with other non-gate of said mask apertures and in electrical connection therein with one of said p-channel current conductor element outermost semiconductor material layer stack ends;a n-channel transistor gate window aperture through at least one semiconductor layer covering said channel layer, said n-channel gate window aperture being in registration with one of said masking inorganic dielectric material layer mask apertures;a n-channel transistor Schottky barrier gate element received in charge carrier flow-controlling proximity of said channel layer in said n-channel transistor gate window aperture;n-channel transistor source and drain current conductor elements located on charge carrier flow upstream and downstream sides of said n-channel gate window aperture and each comprising stacks of locally doped registered successive layer semiconductor material extending orthogonal of said semiconductor material layers between conductor element ends at said outermost semiconductor material layer and at said channel layer;n-channel transistor source and drain ohmic contact elements received on said outermost semiconductor material layer each in registration with other non-gate of said mask apertures and in electrical connection therein with one of said n-channel current conductor element outermost semiconductor material layer stack ends;said p-channel and n-channel transistor source and drain current conductor elements having doping impurity distributions determined in cross sectional location and configuration by ion implantation mask element portions of said masking inorganic dielectric material layer during complementary pair device fabrication;said p-channel and n-channel gate elements and said p-channel and n-channel source and drain ohmic contact elements all being comprised of a same metallic common composition.