Patent ID: 6839828
Filing Date: 2005-01-04
Classification: G06F

Abstract:
1. A processor designed to operate in a plurality of modes for processing vector and scalar instructions, where a vector instruction identifies a single operation to be performed on a plurality of data elements, and a scalar instruction identifies a single operation to be performed on a single data element, comprising: one or more register, files, each for storing data directly usable as scalar data vector data and address information; a parallel vector unit coupled to receive data from the one or more register files and comprising a plurality of functional units configurable to operate in a vector operation mode and a scalar operation mode, the parallel vector unit includes means for tightly coupling a plurality of the functional units to perform an operation specified by a current instruction; wherein under a vector operation mode the parallel vector unit performs, in parallel, a single vector operation on a plurality of data elements, the operations performed on the plurality of data elements each being performed by a different functional unit of the parallel vector unit; and wherein under a scalar operation mode the parallel vector unit performs a scalar operation on a data element received from the one or more register files in a functional unit within the parallel vector unit.