Patent ID: 8759176
Filing Date: 2014-06-24
Classification: H01L,Y10S

Abstract:
1. A method for forming a memory array, the method comprising: forming a conductor rail above a substrate, the conductor rail having a rail width; forming a layer of etchable material above the conductor rail; forming a layer of photoresist over the etchable material; patterning and developing the photoresist to form a plurality of photoresist pillars, each photoresist pillar having a first width less than about 0.3 micron and larger than the rail width, wherein the plurality of photoresist pillars are configured with the first width to survive mechanical stresses encountered prior to an etching; shrinking the photoresist pillars to a shrunk width smaller than the first width and substantially equal to the rail width; etching the etchable material to form a plurality of etched pillars, wherein each etched pillar is substantially aligned with the conductor rail and has a width substantially equal to the rail width; and forming the memory array comprising a plurality of memory cells, wherein each memory cell comprises one of the etched pillars.