Patent ID: 7675337
Filing Date: 2010-03-09
Classification: H03K

Abstract:
1. A duty cycle correcting circuit comprising: a first duty ratio correcting unit configured to widen a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock; a second duty ratio correcting unit configured to narrow the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock; a clock selecting unit configured to selectively output the first corrected clock or the second corrected clock as an output clock in response to the detection signal; and a duty ratio detecting unit configured to detect a duty ratio of the output clock, thereby generating the detection signal, wherein the first duty ratio correcting unit comprises: a first control section configured to receive the detection signal and to generate a first coarse control signal and a plurality of first fine control signals in response to a first coarse state signal and a first fine state signal; a first variable coarse delay section configured to coarsely delay the input clock to output a first variable coarse delay clock and a second variable coarse delay clock in response to the first coarse control signal, and to output the first coarse state signal; a first variable fine delay section configured to output a first variable fine delay clock from the first variable coarse delay clock and the second variable coarse delay clock in response to the plurality of first fine control signals, and to output the first fine state signal; a first fixed coarse delay section configured to coarsely delay the input clock by a fixed time, thereby outputting a first fixed coarse delay clock and a second fixed coarse delay clock; a first fixed fine delay section configured to output a first fixed fine delay clock from the first fixed coarse delay clock and the second fixed coarse delay clock; and a logical sum operating section configured to perform a logical sum operation on the first variable fine delay clock and the first fixed fine delay clock to output the first corrected clock.