Patent ID: 8687761
Filing Date: 2014-04-01
Classification: G09G,G11C

Abstract:
1. A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a system clock and a driving control voltage, wherein the Nth gate line is employed to transmit the Nth gate signal; a first input unit, electrically connected to the pull-up unit, for outputting the driving control voltage according to a first input signal; a first pull-down unit, electrically connected to the first input unit, for pulling down the driving control voltage according to a first control signal and a second input signal, the first pull-down unit comprising: a second pull-down unit, electrically connected to the first input unit and the Nth gate line, for pulling down the Nth gate signal according to the driving control voltage; wherein the first control signal and the second input signal are the (N+1)th gate signal.