Patent ID: 7080215
Filing Date: 2006-07-18
Classification: G06F

Abstract:
1. A multiprocessor apparatus having a plurality of processor units capable of executing an application processing independently, a shared memory for storing therein data commonly utilized by each processor unit upon executing the application processing, and a bus for interconnecting the plurality of processor units and the shared memory, each processor unit comprising: a processor for carrying out a command executing processing for the application processing; a local memory unit provided between the processor and the bus and utilized for storing therein a copy of the whole data of the shared memory; and a copy circuit for controlling the local memory unit, when the contents of the shared memory are updated by any other processor unit, so as to update the local memory with the same contents as the shared memory, wherein when the processor requests a piece of data that shall be stored in the shared memory with a data reading command, then the local memory unit responds to the reading command to read the corresponding piece of data from the copied data stored in the local memory unit and supplies the piece of data to the processor, and wherein the local memory unit provided in each processor unit comprising: a copy memory having a set of regions for storing therein a copy of all data pieces constituting the whole data of the shared memory; a first buffer for temporarily holding therein address information delivered from the processor for executing the reading command and the resulting read data; a second buffer for temporarily holding therein an address and data as a target of update request delivered from the processor to the shared memory, and contents of the shared memory updated by any processor of the plurality of processor units supplied through the bus; and a memory access arbitration circuit arranged to respond to the control of the copy circuit so as to effect arbitration on the reading access to the copy memory based on the reading command delivered from the processor and update access for updating the contents of the copy memory in accordance with the contents held in the second buffer.