Patent ID: 6858441
Filing Date: 2005-02-22
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor workpiece; forming an insulating layer over the workpiece; defining in a single step a pattern for a plurality of alignment marks and a pattern for a plurality of conductive lines within the insulating layer, the alignment marks having a topography; filling the alignment mark and conductive line patterns with a conductive material to form conductive lines; forming a masking layer over the conductive lines; removing at least a portion of the conductive material from the alignment mark pattern, wherein the alignment marks may be used for alignment of subsequent layers of the semiconductor device; removing the masking layer from over the conductive lines, depositing a magnetic stack layer over the insulating layer, conductive lines; and alignment marks, the magnetic stack layer having a top surface, wherein the magnetic stack layer partially fills the alignment marks, wherein the topography of the alignment marks is visible in the top surface of the magnetic stack layer; and patterning the magnetic stack layer to form a magnetic tunnel junction (MTJ) over at least one of the conductive lines, using the topography of the alignment marks visible in the top surface of the magnetic stack layer to align the MTJ to the conductive lines.