Patent ID: 7800134
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. An integrated circuit device, comprising: a semiconductor substrate having a plurality of transistors therein; a first electrically insulating layer on first and second ones of the plurality of transistors, said first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile stress in a channel region of the first one of the plurality of transistors; a second electrically insulating layer on the second one and a third one of the plurality of transistors, said second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive stress in a channel region of the third one of the plurality of transistors; an interlayer dielectric layer on said first and second electrically insulating layers; and a contact plug that extends through the first and second electrically insulating layers and through a portion of an etching stop layer extending between the first and second electrically insulating layers, and electrically contacts a gate electrode of the second one of the plurality of transistors.