Patent ID: 7813159
Filing Date: 2010-10-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first resistive memory element, a second resistive memory element, and a third resistive memory element forming a first memory cell; a first transistor having a first gate electrode, a first source/drain electrode, and a second source/drain electrode, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element; a second transistor having a second gate electrode, a third source/drain electrode, and a fourth source/drain electrode, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element; a first bit line connected to the other terminal of the third resistive memory element; a second bit line connected to the other terminal of each of the first resistive memory element and the second resistive memory element; a first word line connected to the first gate electrode; and a second word line connected to the second gate electrode.