Patent ID: 6130165
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which a plurality of active elements are provided extending along separate parallel lines, and comprising gate regions made up of a second conducting layer, an intermediate dielectric layer and a third conducting layer, said regions being insulated from each other by at least one insulation region to form said architecture, the word lines being defined photolithographically by protective strips, wherein the process comprises the following steps:a vertical profile etching for complete removal of unprotected areas of the first conducting layer, of the second conducting layer, and of the intermediate dielectric layer respectively, the vertical profile etching including forming a protective layer on at least the second conductive layer; anda following isotropic etching of the third conducting layer without removal of portions of the second conductive layer, if steps are adjacent the third conducting layer before the following isotropic etching and the steps are projecting in a lateral direction with respect to at least one of the first conducting, intermediate dielectric, and second conducting layers, then, the following isotropic etching extending its action in the lateral direction to remove the steps.