Patent ID: 9001570
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A memory configurable to be used in a retention till access (RTA) mode, the memory comprising: an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location; an address flop configured to save the latched address bus and to generate a flopped address; a first block address pre-decoder stage configured to generate a pre-decoded latched address to a retention till access (RTA) generation logic in response to the latched address bus; and a second block address pre-decoder stage comprising a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address; wherein the RTA generation logic is configured to generate an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location.