Patent ID: 6808981
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A method of forming a memory array comprising the steps of:(a) forming a plurality of deep trenches in a Si-containing substrate in an array portion of a memory cell, said plurality of deep trenches being arranged in rows and columns and including at least collar filled divot regions which are filled with a strap placeholder material; (b) forming double-gated vertical MOSFETs in said plurality of deep trenches, wherein said double-gated vertical MOSFETs include at least two gates on opposing sidewalls and exposed gate conductors, wherein one of said sidewalls also contains a buried-strap region; (c) forming wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductors, wherein said wordlines are formed in said column direction; (d) protecting said array portion of said memory cell; (e) forming support MOSFETs while said array portion is protected; (f) protecting said support MOSFETs; (g) forming sidewalls spacers on said double-gated vertical MOSFETs; (h) forming bitlines on said Si-containing substrate that are orthogonal to said wordlines; and (i) forming isolation trench regions into said Si-containing substrate adjacent to said rows of deep trenches, wherein said isolation trench regions have a depth that is deeper than abutting bitline diffusion regions.