Patent ID: 7355836
Filing Date: 2008-04-08
Classification: H01G

Abstract:
1. An array capacitor comprising: a. a plurality of ground planes inside a dielectric substrate, each ground plane comprising a plurality of ground-plane-sections, wherein the plurality of ground-plane-sections are independent sheets, the ground-plane-sections being mutually electrically isolated; b. a plurality of ground vias, the ground vias electrically connecting the ground planes together, the ground vias being connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals; c. a plurality of power planes inside the dielectric substrate, the power planes and the ground planes being arranged alternately inside the dielectric substrate, each power plane comprising a plurality of power-plane-sections, wherein the plurality of power-plane-sections are independent sheets, the power-plane-sections being mutually electrically isolated; and d. a plurality of power vias, the power vias electrically connecting the power planes together, the power vias being connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.