Patent ID: 7656031
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A stackable semiconductor package having metal pin within through holes of package, comprising: an interconnect board having a dielectric substrate with a first surface and an opposite second surface; a plurality of electrically conductive circuit patterns on each of said first surface and said second surface of said dielectric substrate, a semiconductor chip having a plurality of input/output (I/O) pad at said first surface and said opposite second surface; a plurality of conductive connecting means, wherein each of said conductive connecting means is electrically connected between an I/O pad of said semiconductor chip and a respective bond finger of said circuit patterns of a surface of said dielectric substrate; a resin encapsulant having first surface and second opposing surface, a plurality of through holes being disposed outside a periphery of said semiconductor chip and being extended vertically across all of a thickness of said stackable semiconductor package between said first surface of said resin encapsulant and said second surface of said interconnect board; a plurality of metal pins being inserted in said through holes, being unbent in said first direction and said second direction, extending vertically across a first surface and a second surface of said through hole, and having two exposed ends to serve as connecting means for upper and lower stacking; and a plurality of conductive bonds contacting said metal pins and said circuit patterns, and providing electrical continuity between said metal pins and said circuit patterns.