Patent ID: 6429536
Filing Date: 2002-08-06
Classification: H01L,H05K,Y02P

Abstract:
A semiconductor device comprising:a substrate having opposing upper and lower surfaces, the upper surface of the substrate being provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring; at least a surface-mountable device connected across the ground ring and the power ring, the surface-mountable device comprising two end contacts and at least a bonding section formed on the surface-mountable device between the two end contacts; a chip disposed on the upper surface of the substrate, the chip having a plurality of bonding pads located about the periphery thereof; at least a first bonding wire having one end connected to one of the bonding pads of the chip and the other end connected to the bonding section on the surface-mountable device; and at least a second bonding wire having one end connected to the bonding section on the surface-mountable device and the other end connected to the power ring; wherein the bonding section comprises a dielectric material formed on the surface-mountable device and a bonding region formed on the dielectric material.