Patent ID: 8053345
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method for fabricating a field effect transistor, comprising: stacking an active layer and a capping layer on a substrate; forming a source electrode and a drain electrode on the capping layer; sequentially forming a dielectric layer and a first resist layer on the substrate; forming a second resist layer with first and second openings on the first resist layer between the source electrode and the drain electrode; exposing the dielectric layer by removing the first resist layer in the bottom of the first opening, which is adjacent to the source electrode, by a linewidth smaller than the inlet of the first opening; removing the dielectric layer in the bottom of the first opening and the first resist layer in the bottom of the second opening to expose the capping layer to the first opening and expose the dielectric layer to the second opening; and forming a gate electrode and a field plate respectively in the first opening and the second opening.