Patent ID: 6198355
Filing Date: 2001-03-06
Classification: H03D,H03L

Abstract:
A phase detector, comprising:a first input for receiving a reference clock signal;a second input for receiving a comparison signal;a first latch device coupled to the first input and being supplied the reference clock signal such that a pulse is generated in response to each positive-going edge of the reference clock signal;a second latch device coupled to the first input and being supplied the reference clock signal such that a pulse is generated in response to each negative-going edge of the reference clock signal;a first combinatorial logic device coupled to outputs of the first and second latch devices, for producing a doubled reference signal having a frequency twice that of the reference clock signal and having a pulse therein corresponding to each pulse generated by the first and second latch devices;a third latch device coupled to the second input and being supplied the comparison signal such that a comparison pulse signal is generated in response to each positive-going edge of the comparison signal; anda charge pump device having a first control input coupled to the first combinatorial logic device for receiving the doubled reference signal and a second control input coupled to the third latch device for receiving the comparison pulse signal, the charge pump device producing a phase detector output representative of a phase difference between the phase of the comparison pulse signal and the phase of the doubled reference signal.