Patent ID: 9158684
Filing Date: 2015-10-13
Classification: G06F,G11C,Y02D

Abstract:
1. A memory module comprising: a first plurality of data signal lines forming a first data bus; a second plurality of data signal lines forming a second data bus; a third plurality of data signal lines forming a data bus; a data manager coupled to the data bus, the first data bus, and the second data bus, wherein the memory module is couplable to a memory controller of a host system using the data bus, a control bus, and an address bus; a non-volatile memory subsystem coupled to the data manager using the first data bus, the non-volatile memory subsystem operable to communicate data signals with the data manager by way of the first data bus; a volatile memory subsystem coupled to the data manager using the second data bus, the volatile memory subsystem operable to communicate data signals with the data manager by way of the second data bus; and a controller operable to receive one or more memory access commands from the memory controller of the host system by way of the control bus and the address bus, the controller operable to generate at least one of a first, second and third plurality of signals in response to the one or more memory access commands received from the memory controller of the host system, the controller operable to direct (i) operation of the non-volatile memory subsystem using the first plurality of signals, (ii) operation of the volatile memory subsystem using the second plurality of signals, and (iii) operation of the data manager using the third plurality of signals.