Patent ID: 6429509
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor die; and an electronic circuit located on said die; and a first via having a first via top portion beginning at a top surface of said die and extending through said die to a first via bottom portion on a bottom surface of said die; and a second via having a second via top portion beginning at said top surface of said die and extending through said die to a second via bottom portion on said bottom surface of said die, said second via being substantially filled with dielectric material adapted to provide support for said semiconductor die; and an input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said I/O interconnect structure being located within an area on the bottom surface of said die and further being arranged so as to comprise a portion of a chip scale package integrated with said semiconductor die; and an I/O signal line coupled to said electronic circuit and said I/O interconnect structure by passing through said first via; wherein electrical signals can be communicated through said I/O signal line and said I/O interconnect structure between said electronic circuit and a second semiconductor device, which second semiconductor device is separate from the first semiconductor device.