Patent ID: 6668334
Filing Date: 2003-12-23
Classification: G01R,H03K,H04L

Abstract:
An apparatus for detecting and asserting a loss-of-clock signal in response to a disruption of an input clock signal having a rising edge, a falling edge, a frequency and a period, comprising:a) a frequency-to-current converter which generates a charging current substantially proportional to the frequency of said input clock signal; b) a capacitor for accepting said charging current which is coupled to said frequency-to-current converter and which has a terminal voltage that changes in response to said charging current; c) an edge detector receiving said input clock signal as an input and asserting an output pulse on at least one of the rising edge or the falling edge of said input clock signal; d) a first switch coupled to said capacitor such that said terminal voltage is discharged to a reference potential when said first switch is closed, and wherein said first switch is controlled by said edge detector to close when said edge detector output pulse is asserted; and e) a comparator having a first input coupled to said capacitor and an output, said output asserting said loss of clock signal when said terminal voltage of said capacitor passes a trip voltage, such that a time delay between said input clock signal disruption and said loss-of-clock signal generation is substantially proportional to the period of said input clock signal.