Patent ID: 7769003
Filing Date: 2010-08-03
Classification: H04L

Abstract:
1. A data packet switch having a plurality of input and output ports comprising: switch fabric for steering data packets from any one of said input ports to any one of said output ports, including a plurality of refreshless dynamic memory buffers associated with a plurality of connections between said input and output ports, one refreshless dynamic memory buffer per connection, each of said refreshless dynamic memory buffers being adapted to store at least one data packet for a minimum specified storing time period; writing structure adapted for writing said data packet in all of said refreshless dynamic memory buffers connected to said input ports through which said data packet is received; and reading structure adapted for reading only once said data packets from selected ones of said refreshless dynamic memory buffers connected to said output ports through which said data packets are to be transmitted, before said minimum specified storing time period of said data packets has elapsed.