Patent ID: 9171916
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having a source region of a first conductivity type and a drain region of the first conductivity type formed proximate to a surface of the substrate; an extended drain region of the first conductivity type disposed in the substrate, the extended drain region having the drain region formed therein; a gate positioned over the surface and between the source region and the drain region, the gate configured to receive a voltage; an interlayer-dielectric region positioned over at least one of the surface or the gate, the interlayer-dielectric region having a thickness ranging between 2.5 microns and 4.0 microns for supporting breakdown voltages ranging between 800 volts and 900 volts while maintaining a relatively constant on-state resistance per unit area; a first field plate at least partially positioned over the gate and configured to shape an electrical field generated at least partially between the source region and the drain region when the voltage is applied to the gate, the first field plate electrically connected to the gate; a second field plate at least partially positioned over the drain region, the second field plate electrically connected to the drain region; a LOCOS region disposed between the source region and the drain region, wherein the extended drain region at least partially extends below the LOCOS region; and a reduced surface field (RESURF) region disposed in the extended drain region, wherein the first field plate and the second field plate are disposed directly over the interlayer-dielectric region, wherein the first field plate is disposed over the reduced surface field (RESURF) region.