Patent ID: 8325861
Filing Date: 2012-12-04
Classification: H03L

Abstract:
1. A receiver, comprising: first and second receiver units, each of which includes at least one receiver circuit, wherein the first receiver unit is to output first data and the second receiver unit is to output second data, wherein the first receiver unit receives a first clock signal and the second receiver unit receives a second clock signal distinct from the first clock signal; a multiplexer to select one of the first data and second data as output data of the receiver in accordance with a control signal; and a calibration logic, wherein data output by the first and second receiver units are coupled to the calibration logic, and the calibration logic is to compare the first data with the second data to provide updates for calibrating one of the first and second clock signals in accordance with the control signal; wherein the receiver is for receiving a respective Jth data stream, and at least one of the first and second clock signals is coupled to a respective other receiver for receiving a different respective data stream.