Patent ID: 6389083
Filing Date: 2002-05-14
Classification: H03M,H04L

Abstract:
A Trellis decoder for demodulating a signal with a symbol therein subjected to modulation for trellis coding in a transmitting side to a signal expressed with N-bit two-valued signs (N: natural number not less than 4) for each of the I axis and Q axis and correcting an error in a received symbol expressed with an X-bit sign from a most significant bit to a X-th bit (X: natural number not less than 3 and smaller than N) from the high order bit in the demodulated signal, said Trellis decoder comprising:a pre-circuit for outputting any of â€œX-power of 2â€  number of signs each expressed with X bits and different from each other according to a sign for â€œX+1â€  bits from the most significant bit to the â€œX+1â€ th bit from the high order bit in the demodulated signal; an area determining circuit for outputting any of â€œ(Xâˆ’1) power of 2â€  number of signs each expressed with â€œXâˆ’1â€  bits and different from each other according to a sign expressed with any X bits outputted from said pre-circuit; a Viterbi decoder for correcting an error for a value of a sign for a least significant bit in the received symbol; a convolutional coder for executing recoding according to a result of error correction by said Viterbi decoder and outputting an estimated value of a sign for the least significant bit in the received symbol obtained by the operation for convolution; a selection circuit for identifying a value of a sign for the â€œXâˆ’1â€  bit from the most significant bit to the â€œXâˆ’1â€ th bit from the high order bit in the received symbol according to a sign of â€œX+1â€  bits consisting of a sign of any â€œXâˆ’1â€  bits outputted from said area determining circuit, a sign of the most significant bit in the received symbol, and a 1-bit sign outputted from said convolutional coder; and a delay circuit for receiving a sign for any â€œXâˆ’1â€  bits outputted from said area determining circuit and a sign for the most significant bit in the demodulated signal and inputting a sign for the X bits as a total of the bits above into said selection circuit in synchronism to the 1-bit sign outputted from said convolutional coder.