Patent ID: 6309937
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method, comprising:(a) providing an integrated circuit substrate with a transistor gate member extending therefrom, the member being bounded by a first spacer and a second spacer;(b) doping a source region and a drain region of the substrate, the first spacer masking a first region of the substrate between the source region and the member and the second spacer masking a second region of the substrate between the drain region and the member during said doping;(c) removing the first spacer and the second spacer after said doping;(d) establishing a first source/drain extension in the first region and a second source/drain extension in the second region by doping the first region and the second region after said removing;(e) heating the substrate after said establishing to simultaneously activate dopant provided by said doping the source region and the drain region and dopant provided by said doping the first region and the second region;(f) forming a third spacer on the first region and a fourth spacer on the second region; and(g) providing a silicide contact with at least one of the member, the source region, and the drain region after the third spacers and the fourth spacer are formed.