Patent ID: 6212111
Filing Date: 2001-04-03
Classification: G11C

Abstract:
A memory device, comprising:an array of memory cells arranged in rows and columns;an external address circuit for receiving an external address corresponding to a row and a column of the memory array;a column counter for sequentially generating a series of internal addresses corresponding to a sequence of columns in the memory array;an address control circuit receiving the external address and the internal address, the address control circuit accessing columns of the memory array according to the external address responsive to a first control signal and accessing columns of the memory array according to the internal address responsive to a second control signal; anda redundant column selection circuit, the redundant column selection circuit comprising:a first comparison circuit comparing the external address to a record of defective columns and generating an external address defect signal if the external address matches an address of a defective column in the array;a second comparison circuit comparing the internal address to a record of defective columns and generating an internal address defect signal if the internal address matches an address of a defective column in the array; anda redundant column control circuit substituting a redundant column for a defective column responsive to the first and second control signal so that the comparison of the external and internal addresses to the addresses of defective columns occurs before the address control circuit determines whether the columns of the memory array will be accessed according to the external address responsive to a first control signal or the internal address responsive to a second control signal.