Patent ID: 7733147
Filing Date: 2010-06-08
Classification: H03K,H03L

Abstract:
1. A delay circuit in a delay locked loop comprising: a first delay circuit unit configured to delay an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal; and a second delay circuit unit coupled with the first delay circuit, the second delay circuit configured to delay the first delay signal and the second delay signal by delay time, which corresponds to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal, wherein the first delay circuit unit includes: a plurality of first unit delayers configured to form the single delay line; and a plurality of switching elements coupled to the plurality of first unit delayers, wherein the first delay circuit unit is further configured to output the first delay signal and the second delay signal in order that the first delay signal differs from the second delay signal in delay time, and wherein the delay time difference between the first delay signal and the second delay signal corresponds to the delay of at least one of the first unit delayers.