Patent ID: 6103580
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of forming buried channel MOSFETs in an integrated circuit comprising:providing a semiconductor substrate;providing field oxide isolation regions overlying said substrate isolating active device regions;cleaning the surface of said substrate in said active device regions;depositing a doped silicate glass layer overlying said field oxide regions and said substrate;etching said doped silicate glass to remove said doped silicate glass layer in all areas except where counter-doped junctions of said buried channel MOSFETs are planned;annealing said substrate and said doped silicate glass to diffuse ions from said doped silicate glass into said substrate and thereby forming said counter-doped junctions;etching away all of remaining said doped silicate glass;thereafter, cleaning said surface of said substrate in said active device regions;depositing a gate oxide layer overlying said field oxide regions and said substrate;depositing a doped polysilicon layer overlying said gate oxide;etching said doped polysilicon layer to form polysilicon gates of said MOSFETs overlying said counter-doped junctions;forming silicon dioxide spacers on the sidewalls of said polysilicon gates;depositing a silicon nitride layer overlying said polysilicon gates;etching said silicon nitride layer to form silicon nitride spacers on said silicon dioxide spacers;implanting ions into said substrate through exposed areas of said substrate adjacent to said nitride spacers and thereby forming source and drain regions of said MOSFETS;annealing said substrate to activate said implanted ions and to outwardly diffuse said ions from said source and drain regions into said substrate and thereby forming lightly doped regions adjacent to said source and drain regions and connecting said source and drain regions to said counter-doped junctions;depositing an interlevel dielectric overlying the surfaces of said MOSFETs and said field oxide isolation regions;etching an opening through said interlevel dielectric to one of said source and drain regions;depositing a metal layer overlying said interlevel dielectric and filling said opening;etching said metal layer to form metal connective traces;depositing a passivation layer overlying said metal connective traces and said interlevel dielectric; andcompleting said integrated circuit.