Patent ID: 8921174
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A method for fabricating a complementary tunneling field effect transistor NTFET and PTFET based on a standard CMOS IC process, comprising: (1) Preparing a substrate: a lightly-doped or low concentration-doped P-type semiconductor substrate; (2) Performing thermal oxidation initially and depositing a nitride layer; (3) Fabricating an STI isolation for an active region through shallow trench isolation technology, and removing the nitride layer; (4) Exposing an active region of each of an NTFET and a PTFET simultaneously by photolithography using a P-well mask for an NMOS in a CMOS, and performing P-well implantation, N-channel implantation and N-threshold-adjustment implantation with the NMOS; (5) Exposing the active region of each of the NTFET and the PTFET simultaneously by photolithography using a N-well mask for an PMOS in the CMOS, and performing N-well implantation, P-channel implantation and P-threshold-adjustment implantation with the PMOS; (6) Removing an oxide previously grown and growing a gate dielectric layer; (7) Depositing a material for a gate and then performing photolithography and etching to form a pattern of the gate; (8) Forming a source of the PTFET and a drain of the NTFET doped consistent with a source and drain of the NMOS through ion implantation using a photoresist and the gate as masks, with an implantation concentration of 1×10 (9) Forming a source of the NTFET and a drain of the PTFET doped consistent with a source and drain of the PMOS through ion implantation using the photoresist and the gate as masks, with an implantation concentration of 1×10 (10) Performing a rapid high-temperature annealing to activate impurities; and (11) Performing subsequent processes such as depositing a passivation layer, opening a contact hole and metallization, so that the complementary tunneling field effect transistor NTFET and PTFET is fabricated.