Patent ID: 6143636
Filing Date: 2000-11-07
Classification: G11C,H01L

Abstract:
A method of forming a memory array, the method comprising the steps of:forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;forming a plurality of first source/drain regions, of a second conductivity type, each of the first source/drain regions formed proximally to an interface between a pillar and the substrate;forming a plurality of second source/drain regions, of a second conductivity type, each of the second source/drain regions formed within one of the pillars and distal to the substrate and separate from the first/source drain/region;forming a gate dielectric on at least a portion of the side surface of the pillars;forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;forming a plurality of control gates, each of the control gates formed substantially adjacent to one of the floating gates and insulated therefrom;forming a intergate dielectric, interposed between ones of the floating gates and one of the control gates;forming a plurality of gate lines that interconnect one of the control gates;forming at least one first source/drain interconnection line interconnecting one of the first source/drain regions; andforming a plurality of data lines, each data line interconnecting one of the second source drain/regions.