Patent ID: 7068653
Filing Date: 2006-06-27
Classification: H04L

Abstract:
1. A data packet switching node to be used in an asynchronous digital network, comprising: an input stage, cutting data packets into segments of constant length; a switching matrix for switching, said switching matrix having input ports and output ports supporting identical bit rates B; and an output stage reconstructing said data packets from said segments supplied by said output ports of said switching matrix, wherein said input stage comprises at least one input interface with a bit rate equal to a multiple of B, ki*B, and means for splitting data packets received on said interface into segments distributed to ki input ports of said switching matrix; said output stage comprises at least one output interface with a bit rate equal to a multiple of B, ko*B, and means for reconstructing a data packet with a bit rate equal to ko*B by concatenating segments supplied by ko output ports of said switching matrix; and ki*ko>1.