Patent ID: 9070714
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A process comprising: forming a dual-gate over a semiconductor wafer, the semiconductor wafer having a first surface and a second surface, the semiconductor wafer including a drain region of a first conductivity type proximal to the second surface and an epitaxial region formed proximal to the first surface and extending from the first surface to the drain region, the dual-gate including a first gate region and a second gate region, the first gate region and the second gate region forming a gap there between; implanting a first body region of a second conductivity type through the first gate region and a second body region of the second conductivity type through the second gate region; implanting a first source region of the first conductivity type in the first body region and a second source region of the first conductivity type in the second body region; and forming a conductive layer over the dual-gate to connect the first gate region and the second gate region together and for reducing an effective resistance of the dual-gate.