Patent ID: 8704347
Filing Date: 2014-04-22
Classification: H01L

Abstract:
1. A chip-sized wafer level packaged device comprising: a chip embodying a device, said chip having a surface, an opposed surface, and bond pads at said surface; a chip-sized silicon packaging layer overlying an opposed surface of said chip, said packaging layer comprising a material having thermal expansion characteristics similar to those of said semiconductor wafer, the silicon packaging layer having a surface facing away from said chip, and openings extending through said packaging layer at locations overlying said bond pads, the chip and the packaging layer having edge surfaces extending away from the surface of the chip and the surface of the packaging layer, respectively; a ball grid array formed over said surface of said packaging layer and being electrically coupled to said bond pads; an insulating layer coating inner surfaces of at least some of the openings; a compliant layer including platforms formed of compliant material different from a material of the insulating layer overlying said surface of said packaging layer, each of said platforms having formed thereon a ball of said ball grid array; and an adhesive layer overlying said silicon packaging layer and underlying said platforms, wherein said platforms are bonded to said silicon packaging layer through said adhesive layer.