Patent ID: 8547758
Filing Date: 2013-10-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a page buffer configured to store data received from selected memory cells in response to a read command; a first register configured to store first data received from the page buffer in response to a first control signal; a second register configured to store second data received from the page buffer in response to a second control signal; a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers; a multiplexer configured to receive the first and second data in response to third and fourth control signals and alternately output the first and second data in response to a data output signal; and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.