Patent ID: 6909125
Filing Date: 2005-06-21
Classification: H01L

Abstract:
1. An electronic device, comprising a. a substrate, having a top surface and a bottom surface; b. a buried layer near the top surface, electrically communicable to a drain terminal; c. a body region, having a second top surface, a second bottom surface and a second side surface, a portion of the side surface contacting a gate region communicable to a gate terminal; d. a channel region, having a third top surface, a third bottom surface, and a third side surface, the third side surface contacting the body region, the third bottom surface being substantially coplanar to the second bottom surfaces and contacting the buried layer, the third top surface being substantially coplanar to the second top surface and electrically communicable to a source region; and e. the source region, projecting upward from the channel region, electrically communicable to a source terminal.