Patent ID: 6625784
Filing Date: 2003-09-23
Classification: G01R,G06F

Abstract:
An integrated circuit device comprising plural logic circuits and plural flip-flop circuits disposed between said plural logic circuits,wherein each of said flip-flop circuits includes: a first input port for receiving a scan test signal; a second input port connected to corresponding one of said logic circuits for receiving, as a data signal, an output of said logic circuit according to a scan test signal input to said logic circuit; a third input port for receiving a control signal for switching input to said flip-flop circuit between said scan test signal and said data signal; a fourth input port for receiving a hold signal; a first output port connected to said logic circuit for transferring said scan test signal to said logic circuit; and a second output port for outputting said data signal and said scan test signal, a scan test circuit is formed by serially connecting said plural flip-flop circuits by successively connecting said second output port of an arbitrary flip-flop circuit among said plural flip-flop circuits to said first input port of another of said flip-flop circuits disposed at a next stage, and an output value output from said first output port is fixed in receiving said hold signal at said fourth input port.