Patent ID: 6289413
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy, said cached SDRAM comprising:a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data;a randomly addressable row register for storing a row of data latched by the sense amplifiers;a select logic gating means, disposed between the sense amplifiers and said row register, for selectively gating the row of data present on the bit lines to said row register in accordance to particular synchronous memory operations of said cached SDRAM being performed, wherein data to be input into said cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array and wherein data to be output from said cached SDRAM during a Read operation is read out only from said row register, the row of data contained in said row register first having been read from the memory bank array to the sense amplifiers and then selectively gated to said row register in accordance with the particular synchronous memory operations; andmeans for programming said cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively.