Patent ID: 6091630
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A semiconductor memory, comprising:a plurality of memory cells arranged in a matrix, each memory cell havinga static memory cell formed on a surface of a substrate having first and second data storage nodes, the memory cell coupled between first and second voltage terminals;a first transfer transistor having a first transfer gate formed on the surface of the substrate and disposed between a first sense node and the first data storage node;second transfer transistor having a second transfer gate formed on the surface of the substrate and disposed between a second sense node and a second data storage node; andactive gate isolation structures having gates formed on the surface of the substrate and disposed between the first and second data storage nodes, the gates of the active gate isolation structures coupled to the second voltage terminal;a plurality of word lines coupling together a row transfer gates;a plurality of first bit lines coupling together a column of first sense nodes; anda plurality of second bit lines coupling together a column of second sense nodes.