Patent ID: 6815621
Filing Date: 2004-11-09
Classification: H01L,H05K

Abstract:
A chip scale package, comprising:a package body having a bottom surface, the bottom surface including upper and lower surface regions aligned on opposite sides of the bottom surface; an electronic chip supported by an upper surface of said package body; and external signal terminals electrically connected to said electronic chip and extending through said package body from the upper surface to the lower surface so as to project from the bottom surface of said package body, said external signal terminals including a first set of terminals which transmit first signals of the electronic chip and which project from the upper surface region of the bottom surface, and a second set of terminals which transmit second signals of the electronic chip and which project from the lower surface region of the bottom surface, wherein a signal frequency of the first signals is lower than a signal frequency of the second signals, and wherein an average spacing between the first set of terminals is greater than an average spacing between the second set of terminals.