Patent ID: 7263013
Filing Date: 2007-08-28
Classification: G11C

Abstract:
1. A synchronous memory device operating synchronized with an operational clock, which comprises: a synchronous write recovery time controlling means which receives a control signal for performing an auto-precharge operation and delays out the control signal as long as a certain clock section of the operational clock corresponding to a write recovery time; an asynchronous write recovery time controlling means for delaying out the control signal coupled thereto as long as a fixed delay time corresponding to the write recovery time; a selecting means for choosing the synchronous write recovery time controlling means or the asynchronous write recovery time controlling means; and an auto-precharge controlling means which outputs as an auto-precharge execution signal used in performing the auto-precharge operation a signal outputted from the synchronous write recovery time controlling means or the asynchronous write recovery time controlling means in response to a write command.