Patent ID: 7089401
Filing Date: 2006-08-08
Classification: G06F,G11B

Abstract:
1. A data relay controller for use with an external device for transferring a data block between a buffer memory and a computer, wherein the data block includes a plurality of sectors, each containing main data and sub data, and parity data set in relation with the plurality of sectors, the data relay controller comprising: an address generation circuit for generating address data that designates access addresses of the buffer memory in a predetermined order in accordance with a writing or reading head address of the main data provided from the external device; an access circuit connected to the address generation circuit for writing the main data to or reading the main data from the buffer memory in accordance with the address data; a counter for counting the main data that is written to the buffer memory or read from the buffer memory to generate a count value; and an address skip control circuit connected to the address generation circuit for skipping address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.