Patent ID: 6408361
Filing Date: 2002-06-18
Classification: G06F

Abstract:
An apparatus for performing transactions in a single ported cache memory, including a cache directory partitioned into ways containing tag addresses, the apparatus comprising:a cache controller coupled to the cache memory; the cache directory portion partitioned into ways containing tag addresses and tag address statuses; and the cache controller performing the steps of: receiving first and second transactions, the transactions containing respective tag addresses and candidate statuses; reading all the ways for the first transaction during a first clock cycle, wherein the reading includes comparing the received tag addresses for the first transaction to tag addresses stored in the ways and the stored tag address statuses to a predetermined value during a first clock cycle; and reading for the second transaction, during a second clock cycle, solely the ways that are not being updated for the first transaction, while also updating, during the second clock cycle, one of the ways that contains a matching stored tag address and tag address status for the first transaction.