Patent ID: 8405595
Filing Date: 2013-03-26
Classification: G09G

Abstract:
1. A display device comprising: a display panel in which data lines and gate lines cross each other; a timing controller configured to output a single gate pulse modulation control signal (“FLK signal”) and I-phase (where I is an integer equal to or more than 2) gate shift clocks which are sequentially delayed; an FLK dividing circuit configured to divide the single FLK signal to output J (where J is an integer equal to or more than 2 and smaller than I) FLK signals; a data driving circuit configured to convert digital video data into data voltages to supply the data voltages for the data lines; and a gate driving circuit configured to generate gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals, and to sequentially supply the modulated gate pulses for the gate lines.