Patent ID: 6078636
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A counter circuit for counting a number represented by n bits ranging from lowest to highest significance, the counter circuit comprising:first to n-th flip-flop circuits each corresponding to a different one of the n bits, each having a first signal input terminal, a second signal input terminal and a count signal output terminal, each for receiving a synchronization signal, for receiving in a first cycle of the synchronization signal when counting starts, a first input signal inputted into said first signal input terminal and outputting an output signal in accordance with the first input signal from the count signal output terminal while the synchronization signal remains in a first logic state, for latching the output signal in accordance with said first input signal while the synchronization signal remains in a second logic state following the first logic state, for receiving, in a cycle following the first cycle of the synchronization signal after the counting starts, a second input signal inputted into said second input signal terminal while the synchronization signal remains in the first logic state, and for outputting the output signal in accordance with said second input signal from the count signal output terminal while the synchronization signal remains in the second logic state following the first logic state, thereby obtaining first to n-th bit count signals;first to n-th latch circuits each corresponding to a different one of the n bits, each for receiving the output signal from said flip-flop circuit corresponding to the same bit, and in the first cycle of said synchronization signal when counting starts, for latching the output signal from the flip-flop circuit corresponding to the same bit and outputting first and second signals, and for setting a logic level of said second signal in accordance with a control signal irrespective of a logic level of the output signal from the flip-flop circuit corresponding to the same bit;first to n-th, first logic circuits, each corresponding to a different one of the n bits, each for receiving the output signal from said flip-flop circuit corresponding to the same bit, each of the second to n-th, first logic circuits for receiving a carry signal, for outputting a third signal when the output signal from the flip-flop circuit corresponding to the same bit and the carry signal differ in logic level, and for feeding the third signal as said first input signal to said flip-flop circuit corresponding to the same bit; andfirst to n-th, second logic circuits, each corresponding to a different one of the n bits, each for receiving the output signal from said flip-flop circuit corresponding to the same bit, each of the second to n-th, second logic circuits for receiving the carry signal from one of the second logic circuits corresponding to a less significant bit and said second signal outputted from the latch circuit corresponding to the same bit, and outputting said carry signal to one of each of the first and second logic circuits corresponding to a more significant bit when the output signal from the corresponding flip-flop circuit and the second signal outputted from the latch circuit corresponding to the same bit differ from each other in logic level.