Patent ID: 6747500
Filing Date: 2004-06-08
Classification: H03H,H03K

Abstract:
A low voltage low power delay circuit for determining a delay time interval comprising:a bias circuit portion for generating first and second bias signals; a ramp generator portion comprising at least one capacitor and a first transistor coupled to a first terminal of the at least one capacitor, the ramp generator generating a voltage ramp signal wherein a voltage change rate of the voltage ramp signal is controlled by a current level in the first transistor, the first transistor having a gate coupled to the bias circuit portion such that the current level in the first transistor is controlled by the first bias signal, the ramp generator further comprising a switch coupled to the at least one capacitor, the switch being operable by a reset signal so as to reset the voltage on the at least one capacitor; a comparator portion comprising a second transistor having a gate coupled to receive the voltage ramp signal, wherein a switching threshold voltage at the gate of the second transistor is controlled by a current level in a third transistor coupled to the second transistor, the third transistor having a gate coupled to the bias circuit portion such that the current level in the third transistor is controlled by the second bias signal; and wherein a relationship between the voltage change rate of the ramp signal and the switching threshold voltage is at least partially governed by the first and second bias signals such that the delay time interval determined by the delay circuit tends to be stabilized against variations in a supply voltage supplied to the delay circuit during normal operation.