Patent ID: 6515317
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A charge coupled device comprising:a semiconductor substrate having an N-well with a plurality of peaks; a plurality of P-wells in said N-well, wherein one of said peaks is formed between each pair of said plurality of P-wells, a plurality of trenches equivalent in number and corresponding to said plurality of P-wells wherein each said trench extends into the upper portion of each of said corresponding P-well, wherein the sides along the bottoms of each said trench are rounded by annealing, and wherein p-type channel stop is formed in the bottom of each of said plurality of trenches; N-channels formed in each sidewall of each of said plurality of trenches; a plurality of P1 lines wherein each of said P1 lines connects a plurality of P1 gates formed over said trenches; and a plurality of P3 lines wherein each of said P3 lines connects a plurality of P3 gates formed over said trenches.