Patent ID: 6526480
Filing Date: 2003-02-25
Classification: G06F

Abstract:
Cache apparatuses which are provided for every plurality of processors, mutually connected by a bus, and connected to a main storage by the bus, each comprising:a cache memory in which a part of data in the main storage is held on a cache line unit basis, and a status of the data held in the cache line is distinguished by three kinds of statuses including Valid, Invalid, and Unknown; and a cache controller processing the data held in the relevant cache line in accordance with the status of Valid, Invalid, or Unknown when a processing request is received from a self processor or another cache apparatus, and, after the processing, changing the status of the holding data in the relevant cache line to a predetermined status determined in order to keep a cache coherence, wherein when a reading request to the cache line holding data whose validity is unknown is issued, said cache controller discriminates whether providing of speculation data to a requesting source is permitted or inhibited, provides the data whose validity is unknown as speculation data to the requesting source when the permission of the providing is determined, and obtaining valid data from the other cache apparatus or said main storage and providing it to the requesting source when the inhibition of the providing is determined.