Patent ID: 6226338
Filing Date: 2001-05-01
Classification: G06F,H04J,H04L

Abstract:
A multiple-channel data communication buffer comprising a transmit first-in-first-out (""FIFO"") circuit and a receive FIFO circuit, wherein the transmit and receive FIFO circuits each comprise:a single memory device having a data input, a data output, a write address input, a read address input and a plurality of logical channels from the data input to the data output;a write channel number input which identifies a selected one of the plurality of logical channels;a read channel number input which identifies a selected one of the plurality of logical channels;a write pointer array coupled to the write channel number input and comprising a write pointer for each of the logical channels, wherein the write pointer array applies a selected one of the write pointers to the write address input based on the write channel number input; anda read pointer array coupled to the read channel number input and comprising a read pointer for each of the logical channels, wherein the read pointer array applies a selected one of the read pointers to the read address input based on the read channel number input.