Patent ID: 7601607
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method of fabrication of an interconnect opening for a semiconductor device; comprising the steps of: forming a lower interconnect and an insulating layer over a semiconductor structure; forming a first hardmask over said lower interconnect and said insulating layer; forming a dielectric layer over said first hardmask layer; forming a second hardmask over said dielectric layer; in a first etch step, etching a first interconnect opening in said first hardmask, said dielectric layer and said second hardmask layer; in a second etch step, etching the first and second hardmask overhangs and the dielectric layer form a first overhang-less interconnect opening; the second etch step essentially removes said first and second hardmask overhangs; forming an interconnect in said first overhang-less interconnect opening.