Patent ID: 9171929
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A field effect transistor (FET) comprising: a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, a length parallel to the first surface, and the channel portion is a germanium channel portion; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material, wherein a portion of each of the two S/D regions extending downward from the second surface is lower than the first surface, thereby defining a second height greater than the first height.