Patent ID: 6175322
Filing Date: 2001-01-16
Classification: H03M

Abstract:
An nth order Delta-Sigma Modulator (DSM) where n is at least one, the DSM having:an input for receiving a 1-bit input signal;a first delay element for delaying the received 1-bit input signal;a quantizer for requantizing a p-bit signal to 1-bit form, the requantized signal being an output signal of the processor; anda plurality of signal combiners, includinga first combiner for forming an integral of an additive combination of the product of the input signal and a first coefficient and of the product of the output signal and a second coefficient,at least one intermediate combiner each for forming an integral of an additive combination of the product of the input signal and a first coefficient and of the product of the output signal and a second coefficient, and of the integral of the preceding stage, anda final combiner for forming an additive combination of the product of the input signal and a first coefficient and of the integral of the preceding stage to form the p-bit signal which is requantized by the quantizer to form the 1-bit output signal,wherein the input signal is fed to the first combiner and intermediate combiners via the first delay element corresponding to the delay through a combiner, and to the final combiner without such delay,wherein the 1-bit output signal of the quantizer is fed-back to the combiners via a second delay element having a delay substantially equal to that of the first delay element, andwherein the final combiner receives from its preceding combiner a p-bit signal corresponding in timing to the input signal received by the final combiner.