Patent ID: 6441670
Filing Date: 2002-08-27
Classification: H03K

Abstract:
A receiver circuit for a semiconductor integrated circuit device comprising:a pass gate device having a first input for receiving input logic voltages, a gate input connected to a first voltage supply source operating at a first voltage level, and an output connected to a first node, said pass gate passing a received high logic level input voltage to said first node and providing high voltage protection for said receiver by limiting the voltage passed to said first node; a first inverter device having a connection to a second voltage supply source, a connection to ground, and an output defining a second node, said first inverter device for receiving said input voltage and pulling down said input voltage for output at said second node when said input voltage is high, and pulling up said input voltage to said limited voltage level for output at said second node when said input voltage switches to a low voltage; a first transistor device for connecting said first inverter device to said second voltage supply source; a positive feedback circuit responsive to said pulled down voltage at said second node for turning off said first transistor device to thereby prevent leakage current to ground through said first inverter device, and enabling activation of said transistor device to facilitate pulling up voltage at said second node via said inverter device, wherein stable switching voltages is achieved at said second node in a manner that eliminates leakage current between said second voltage supply source and a receiver input.