Patent ID: 6356990
Filing Date: 2002-03-12
Classification: G06F,Y02D

Abstract:
A cache memory that can be accessed via an effective address having a tag field, a line index field, and a byte field, said cache memory comprising:a directory; a memory array associated with said directory, wherein said memory array includes a plurality of congruence classes and each of said congruence classes includes a plurality of sets, wherein said memory array includes a set prediction array integrated within said memory array via an association of a line entry within said set prediction array to a congruence class within said memory array such that said line entry within said set prediction array and said congruence class are accessed in a same cycle, wherein said line entry within said set prediction array includes a plurality of set prediction resolution slots, the number of said plurality of set prediction resolution slots does not correspond to the number of sets within each of said congruence classes, and one of said plurality of prediction resolution slots is selected during said cache access by a subset of bits from said tag field; and a translation lookaside buffer for determining whether or not said cache memory stores data associated with an effective address, in response to said cache access by said effective address.