Patent ID: 6084906
Filing Date: 2000-07-04
Classification: H04L

Abstract:
An article of manufacture comprising:a processor accessible storage structure embodied in an integrated circuit; anda processor executable routine stored in the storage structure, wherein the executable routine includes instructions for causing a processor to operate to configure data and energy loadings of K sub-channels of a high speed data transmission system so that it achieves a data rate R, the instructions including directions to the processor to execute the following operations:(a) determining K signal-to-noise ratios associated with K sub-channels; and(b) determining data capacities of each of the K sub-channels based on an evaluation of the following parameters:i) the K signal-to-noise ratios; andii) said data rate R; andiii) a number N.sub.ch of the K sub-channels having a non-zero bit capacity; andwherein the data capacities can be determined by the processor executing one or more iterations of the operations of step (b) and N.sub.ch is calculated during each iteration.