Patent ID: 7653758
Filing Date: 2010-01-26
Classification: G11C

Abstract:
1. A memory system comprising a memory controller and at least one memory board, the memory board comprising a digital data buffer having at least one data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, the buffer further having a clock output for providing an output clock signal to the data destination device and a phase-locked loop with a clock input, a feedback input, a feedback output and a plurality of clock outputs; wherein: the data path has a first data register with a data input, a clock input and a data output; the data path has a second data register with a data input, a clock input and a data output; the data input of the buffer is connected to the data input of the first data register; the data output of the first data register is connected to the data input of the second data register; the data output of the buffer is connected to the data output of the second data register; the clock input of the buffer is connected to the clock input of the the first data register; the clock input of the buffer is connected to the clock input of the phase-locked loop; a first clock output of the phase-locked loop provides a feedback clock signal for application to the feedback input of the phase-locked loop; a second clock output of the phase-locked loop provides a clock signal shifted in phase by a fraction of the clock period with respect to the feedback clock signal for application to the clock input of the second data register; and a third clock output of the phase-locked loop provides a clock signal shifted in phase by an amount of 180 deg. plus a fraction of the clock period with respect to the feedback clock signal for application to the clock input of the data destination device.