Patent ID: 8213252
Filing Date: 2012-07-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array, comprising: a plurality of sub memory cell arrays each comprising a plurality of first memory cells connected between a plurality of first wordlines and a plurality of first bitlines, and a plurality of second memory cells connected between a plurality of second wordlines and a plurality of second bitlines, wherein the plurality of sub memory cells are arranged in a direction of the first bitlines; and a plurality of sense amplifier circuits arranged alternately with the plurality of sub memory cell arrays and each comprising a first amplifier configured to amplify one of the first bitline and the second bitline to a first voltage level in response to a first sensing control signal, and a second amplifier configured to amplify one of the first bitline and the second bitline to the first voltage level in response to a second sensing control signal; a power supply configured to supply the first voltage to the plurality of sense amplifier circuits; and a controller configured to determine an activation order of the first sensing control signal and the second sensing control signal according to an address, and to adjust a time interval between activation time points of the first and second sensing control signals input to each sense amplifier circuit according to a distance between the power supply and the sense amplifier circuit.