Patent ID: 6631088
Filing Date: 2003-10-07
Classification: G11C

Abstract:
An addressing method for a twin MONOS metal bit line array, comprising:a) labeling word lines from a low word line address to a high word line address, b) labeling control gate lines from a low control gate address to a high control gate address, c) labeling bit lines from a low bit line address number to a high bit line address number with an additional designation as â€œevenâ€  and â€œoddâ€  for each said address number, d) selecting a set of three dimensional addresses â€œXâ€ , â€œYâ€  and â€œZâ€ , e) selecting said word line address as the â€œXâ€  address, f) selecting said control gate address as a function of the â€œXâ€  and the â€œZâ€  addresses, g) selecting said bit line address as a function of the â€œYâ€  and â€œZâ€  addresses and whether the control gate address is â€œevenâ€  or â€œoddâ€ .