Patent ID: 6452856
Filing Date: 2002-09-17
Classification: G11C,H01L,H03K

Abstract:
An address decoder for a memory device, the address decoder comprising:a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein at least one non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the capacitor providing a coupling ratio greater than 1.0, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.