Patent ID: 6252278
Filing Date: 2001-06-26
Classification: H01L

Abstract:
An LDMOS transistor formed in a N-type substrate, said transistor comprising:a polysilicon gate atop said N-type substrate, said polysilicon gate comprising a the gate oxide layer of about 200 angstroms and a polysilicon layer, said polysilicon gate having a source side and a drain side;a P-type well formed in said N-type substrate extending from said source side to under said polysilicon gate;a N.sup.+ source region formed in said P-type well and adjacent to said polysilicon gate;a N.sup.+ drain region formed in said N-type substrate and in said drain side of said polysilicon gate; anda lightly doped N.sup.- drift region in said N-type substrate between said N.sup.+ drain region and said polysilicon gate, wherein said N-type drift region does not extend below said polysilicon gate and is doped to about 6 e 13 or 1 e14ions/cm.sup.2.