Patent ID: 6631460
Filing Date: 2003-10-07
Classification: G06F

Abstract:
A computer system comprising:memory storing a compiled program including: a store instruction; a load instruction scheduled before the store instruction; and a check instruction; a processor executing the compiled program; physical registers holding data for the compiled program, a portion of the physical registers forming a register stack which wraps around when full; N-bit current wraparound count state that tracks physical register remapping events which cause the register stack to wraparound or unwrap; an advanced load address table having entries corresponding to load instructions, each entry having at least one memory range field defining a range of memory locations accessed by a corresponding load instruction, a physical register number field corresponding to a physical register accessed in the corresponding load instruction, and an N-bit register wraparound field which corresponds to the N-bit current wraparound count state for the corresponding load instruction; and wherein the check instruction accesses the advanced load address table to determine whether the store instruction and the load instruction potentially accessed a common memory location.