Patent ID: 6274934
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A semiconductor device comprising:a plurality of normal electronic circuits formed at a main surface of a semiconductor substrate;a spare electronic circuit formed at said main surface of said semiconductor substrate; anda normal electronic circuit interconnection for electrically connecting said normal electronic circuits with each other, said normal electronic circuit interconnection including normal conductive layers formed above said main surface of said semiconductor substrate to respectively extend substantially in parallel with a plurality of layers which are substantially in parallel with said main surface and having a substantially minimum limit width under an applied design rule,space between said normal conductive layers being defined so as not to allow another conductive layer to newly be formed under said design rule in almost all regions except for a predetermined region, anda spare path for an electronic circuit interconnection being provided so as to form an electronic circuit interconnection which connects said spare electronic circuit with said normal electronic circuit interconnection without making a change in interconnection which is accompanied by change in arrangement of said normal electronic circuit interconnection under said design rule if change in interconnection becomes necessary in said predetermined region in order to use said spare electronic circuit.