Patent ID: 6300241
Filing Date: 2001-10-09
Classification: G02F

Abstract:
A process of forming a reflective electrode comprising:forming a highest intermetal dielectric layer on top of a highest layer of interconnect metallization;planarizing the highest intermetal dielectric;creatine a via in the highest intermetal dielectric;lining the walls of the via with a liner layer;filling the via with an electrically conductive material;forming an electrode adhesion layer on top of the highest intermetal dielectric and the via;forming an electrode layer on top of the electrode adhesion layer; andforming a reflectance enhancing coating on top of the electrode layer, the reflectance enhancing coating generating constructive interference of light waves reflected by the electrode layer, andwherein the step of planarizing the highest intermetal dielectric includes the steps of forming SOG on top of the highest intermetal dielectric, etching the SOG and the intermetal dielectric, and chemical mechanical polishing the etched intermetal dielectric.