Patent ID: 6118706
Filing Date: 2000-09-12
Classification: G11C

Abstract:
A method of operating FLASH memory comprising the steps of:disposing an array of memory cells in rows and columns and in at least one sector, each of said memory cells consisting of a dual gate N-Channel transistor having a floating gate for storing an electronic charge said charge having one of multiple value distributions, each value distribution determining a stored binary logic state, each sector consisting of a set of said array of memory cells disposed in an isolated N-type semiconductor well within a P-type substrate;connecting a first source-drain terminal of each dual gate N-Channel transistor to virtual ground;connecting a second source-drain terminal of each dual gate N-Channel transistor within each column of said array to a corresponding bit line;connecting a control gate of each dual gate N-Channel transistor within each row to a corresponding word line; andsimultaneously applying a high voltage to each word line of a selected sector of said memory cells and applying a ground voltage to a back gate of said isolated N-type semiconductor well corresponding to said selected sector, thereby simultaneously clearing data stored in each memory cell of said selected sector.