Patent ID: 6717833
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A semiconductor device comprising:a first memory array having a plurality of first memory cells; a second memory array having a plurality of second memory cells; a first data line formed in a first layer, extending in a first direction and provided for said first memory array, wherein data readout from a selected memory cell of said plurality of first memory cells is provided to said first data line; a second data line formed in said first layer, extending in said first direction and provided for said second memory array, wherein data read out from a selected memory cell of said plurality of second memory cells is provided to said second data line; and a third data line formed in a second layer which is different from said first layer and extending in a second direction perpendicular to said first direction, said third data line being provided for said first and second data lines, wherein said third data line is formed on said first memory array and said second memory array.