Patent ID: 6465818
Filing Date: 2002-10-15
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells, each of which is arranged at a corresponding one of intersections, at which bit lines intersect word lines, said memory cell array having at least two separation transistor groups including a plurality of separating transistors, each of which is provided in each of said bit lines said separating transistors in one of said separating transistor groups being turned OFF such that said memory cell array is divided into first and second banks; a first sense amplifier arranged on one side of said memory cell array in a bit line direction, said first sense amplifier being connected to said bit lines of said first bank to sense signals of said bit lines of said first bank; a second sense amplifier arranged on the other side of said memory cell array in said bit line direction, said second sense amplifier being connected to said bit lines of said second bank to sense signals of said bit lines of said second bank; a row decoder for selectively driving said word lines of said memory cell array; and a parallel control circuit for allowing one of said first and second banks to perform a data writing or erasing operation while allowing the other of said first and second banks to perform a data reading operation.