Patent ID: 7449265
Filing Date: 2008-11-11
Classification: G03F

Abstract:
1. A method of aligning layers on a wafer comprising: creating a first multi-dimensional target in a first mask, the first multi-dimensional target comprising a plurality of first segmented lines, a plurality of second segmented lines perpendicular to the plurality of first segmented lines, and a plurality of third segmented lines parallel to the plurality of first segmented lines; establishing a first patterned layer on the wafer, the first patterned layer comprising a first target area having the first multi-dimensional target therein; creating a second multi-dimensional target in a second mask, the second multi-dimensional target comprising a plurality of fourth segmented lines, and a plurality of fifth segmented lines perpendicular to the plurality of fourth segmented lines; and aligning the second mask with the first patterned layer on the wafer using the first multi-dimensional target and second multi-dimensional target.