Patent ID: 6084480
Filing Date: 2000-07-04
Classification: H03L

Abstract:
A PLL circuit wherein the pull-in time is reduced, comprises:a voltage controlled oscillator including a control terminal;a frequency divider which divides a frequency of an output signal from the voltage controlled oscillator;a phase detector which compares a phase of a standard signal and a frequency-divided signal, and outputs an advanced phase signal and a delayed phase signal;a low pass filter, including a capacitor, for eliminating a high frequency component and noise of said advanced phase signal and said delayed phase signal;a charge pump which charges and discharges, depending upon said advanced phase signal and said delayed phase signal, said capacitor in said low pass filter;a plurality of voltage suppliers which supply the control terminal of said voltage controlled oscillator with voltages which correspond to desired voltages decided by output frequencies from said voltage controlled oscillator, when an output from said low pass filter is not connected with said control terminal of said voltage controlled oscillator,wherein each of said voltage suppliers comprises a capacitor which is connected between said low pass filter and said control terminal of said voltage controlled oscillator; anda switch which selectively connects said control terminal of said voltage controlled oscillator with any one of said voltage suppliers.