Patent ID: 8060728
Filing Date: 2011-11-15
Classification: G06F

Abstract:
1. A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: at runtime, receiving instructions for detecting conflicts between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, wherein the instructions are inserted in program code prior to runtime, wherein the conflicts between the memory addresses are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime; wherein while executing the program code, executing the instructions causes a processor to generate one or more stop indicators corresponding to any detected conflict between the memory addresses, wherein a given stop indicator indicates a memory hazard; and receiving instructions for generating predicate values, wherein executing the instructions for generating predicate values causes the processor to generate one or more predicate values based on the one or more stop indicators, wherein the one or more predicate values specify elements for which the operations may safely be performed in parallel for a set of consecutive elements in at least one of the vectors.