Patent ID: 8247271
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A structure fabrication method, comprising: providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side, wherein N is at least 2; bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors; polishing the bottom side of the interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield after said bonding the integrated circuit to the top side is performed; and forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors, wherein the interposing shield comprises a shield material, wherein the shield material comprises a first semiconductor material, wherein each electric conductor of the N electric conductors comprises an electrical pad, wherein said bonding comprises bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors, wherein after said bonding and before said polishing, the shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient, and wherein said polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.