Patent ID: 8448030
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A method for generating addresses for memories and simultaneously testing the memories using a single Built-in Self Testing (BIST) controller, each of the memories comprising one or more memory locations, the method comprising: a. selecting a memory of the memories based on a pre-defined rule, each of the memories having a corresponding pre-defined number of physical rows; b. comparing the pre-defined number of physical rows of the selected memory with the pre-defined number of physical rows of other memories; c. extending size of an address-width register to form an extended address-width register based on the comparison performed in (b); d. generating an extended width address using the extended address-width register, wherein the extended width address is used to generate addresses for the memories; and e. performing read and write operations on the memories using the single BIST controller based on pre-defined rules, wherein the read and write operations provide testing of the memories.