Patent ID: 8031548
Filing Date: 2011-10-04
Classification: G11C

Abstract:
1. A voltage stabilization circuit in a semiconductor memory apparatus comprising: a control signal generating unit configured to generate a control signal that is enabled when a supply voltage is unstable; and a voltage level maintaining unit coupled with the control signal generating unit, the voltage level maintaining unit configured to selectively control an equivalent capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal, wherein the supply voltage is unstable at an entry into a power-down mode or at an exit from the power-down mode, the voltage level maintaining unit electrically connects one terminal of each of the capacitors to control the equivalent capacitance when the control signal is enabled, and electrically disconnects one terminal of each of the capacitors to control the equivalent capacitance when the control signal is disabled, each other terminal of the capacitors is coupled with a ground terminal, and the control signal generating unit enables the control signal for a set time at the entry into the power-down mode and enables the control signal for the set time at the exit from the power-down mode.