Patent ID: 6680544
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A bump arrangement of a flip-chip comprising:a conductive bump array formed at a core of said flip-chip; a first ring of conductive bumps surrounding said conductive bump array, most portions of said first ring of conductive bumps being connected responsively to power terminals; a second ring of conductive bumps surrounding said first ring, each of conductive bumps of said first ring having a conductive bump of said second ring aligned therewith, and most portions of said second ring of conductive bumps being connected responsively to a ground terminal; and a third ring of conducive bumps surrounded and staggered with respect to said second ring of conductive bumps, most portions of said conductive bumps of said third ring being connected to I/O signal terminals, and said third ring, said second ring, and said first ring of conductive bumps being connected to conductive traces of at least one interconnection layer through vias and a redistribution layer, wherein said redistribution layer is interposed between a passivation layer and the most upper interconnection layer of said at least one interconnection layer.