Patent ID: 9099194
Filing Date: 2015-08-04
Classification: G06F,G11C,H01L,H04L

Abstract:
1. A memory component comprising; a memory core; a first circuit to receive external commands, the external commands including a read command that specifies transmitting data accessed from the memory core, and a write command that specifies storing data, provided to the memory component, in the memory core; a second circuit to transmit data onto an external bus in response to a read command; pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration, wherein the pattern register circuitry includes at least first and second data pattern registers to provide the first and second data patterns, respectively, wherein at least one of the first and second data pattern registers is loaded with at least one of the first and second data patterns in response to a write command received during the calibration; and an input to receive a reset signal, wherein the first and second data pattern registers are set to be predefined values upon receipt of the reset signal.