Patent ID: 7947554
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. A semiconductor device fabrication method comprising: forming, on a semiconductor substrate, a plurality of first semiconductor elements using electrons as carriers side by side, and a plurality of second semiconductor elements using holes as carriers side by side; forming sidewall spacers of gate electrodes of the first semiconductor elements and the second semiconductor elements; removing at least surface portions of the sidewall spacers of the gate electrodes of the first semiconductor elements and the second semiconductor elements; depositing a first insulating film having one of tensile stress and compression stress on source/drain regions and the gate electrodes of the first semiconductor elements and the second semiconductor elements, the first insulating film not closing a spacing between the gate electrodes of the first semiconductor elements and a spacing between the second semiconductor elements; depositing a second insulating film on the first insulating film; removing the first insulating and the second insulating film deposited on one of the first semiconductor elements and the second semiconductor elements; depositing a third insulating film having the other one of tensile stress and compression stress on the source/drain regions and the gate electrodes of the first semiconductor elements and the second semiconductor elements; and removing the third insulating film deposited on the other one of the first semiconductor elements and the second semiconductor elements.