Patent ID: 7020003
Filing Date: 2006-03-28
Classification: G11C

Abstract:
1. A device for compensating a semiconductor memory defect, suitable for a semiconductor memory, said semiconductor memory including a control unit, an address decoder circuit, and a sensing circuit, said device comprising: a memory array, comprising a memory region having a plurality of memory cells, said memory array being coupled to said address decoder circuit and said sensing circuit for storing data, wherein if said memory array has a defect, said memory array is divided into a plurality of sub-memory regions, one of said plurality of sub-memory regions is defectless, and wherein said memory array is replaced with said defectless sub-memory region for storing data; a selection circuit, coupled to said control unit, said selection circuit selecting one of said memory region and said defectless sub-memory region to store data; and a first input address buffer, coupled to said control unit and said address decoder circuit, said first input address buffer including an address input port and an address output port, said address input port receiving a most significant bit address signal; wherein if said memory array is defectless, said selection circuit outputs a selection signal to select said memory region to store data and makes said control unit control said address output port to output said most significant bit address signal to said address decoder circuit; if said memory array has said defect, said selection circuit outputs a selection signal to select said defectless memory region to store data and makes said control unit control said address output port to output said selection signal to said address decoder circuit.