Patent ID: 6642555
Filing Date: 2003-11-04
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising a plurality of memory cells formed in a substrate, each memory cell including a first transistor having a first conductivity type and a second transistor having a second conductivity type different to the first conductivity type,each memory cell comprising: a first active region being formed in the substrate, and channels of the first transistor being formed therein, wherein four of said first transistors are provided in series in the first active region; a second active region being formed in the substrate, and channels of the second transistors being formed therein, wherein two of said second transistors are provided in series in the second active region; two word lines of a parallel stripe form laid perpendicularly intersecting the first active region and running between a plurality of cells and serving also as gate electrodes of word transistors of the first conductivity type; and two common gate lines arranged in parallel between the two word lines perpendicularly intersecting both of the first and second active regions and each connecting a gate of a drive transistor of the first conductivity type with a gate of a load transistor of the second conductivity type; said first and second active regions being arranged so that the directions of channel current flows of the first and second transistors become parallel to each other in each cell, and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current, wherein patterns of interconnections serving as gate electrodes of the first and second transistors are arranged to all perpendicularly intersect the first or second active region where intersecting the first or second active region.