Patent ID: 7542342
Filing Date: 2009-06-02
Classification: G11C,H01L

Abstract:
1. A multiple time programmable (MTP) memory cell, comprising: a floating gate PMOS transistor including a source that forms a first terminal of the memory cell, a drain and a gate; a high voltage NMOS transistor including a source, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell; and an n-well capacitor including a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell; wherein the floating gate PMOS transistor can store a logic state; and wherein combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state stored by the floating gate PMOS transistor.