Patent ID: 6136650
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A fabrication method for a three-dimensional flash array structure, the method comprising steps of:forming a first oxide layer on a substrate;forming a plurality of billet-shaped control gates on the first oxide layer, wherein each of billet-shaped control gates comprises a metal silicide layer and a conducting layer;forming a first dielectric layer on the billet-shaped control gates and the first oxide layer;forming a plurality of billet-shaped word lines, wherein an orientation of the billet-shaped word lines is approximately perpendicular to that of the billet-shaped control gates;forming a second oxide layer on the first dielectric layer between adjacent billet-shaped word lines until a surface of the second oxide layer is approximately level with a surface of the billet-shaped word lines;forming a tunneling oxide layer on the billet-shaped word lines and the second oxide layer;forming a plurality of block-shaped floating gates on the tunneling oxide layer, wherein the block-shaped floating gates are located on stacks of the billet-shaped word lines and the billet-shaped control gates;performing an ion implantation step, with the block-shaped floating gates serving as implantation masks, so that a plurality of first doped regions and a plurality of second doped regions are formed in the billet-shaped word line;forming a third oxide layer on the tunneling oxide layer on both sides of the block-shaped floating gates until a surface of the third oxide layer is approximately level with a surface of the bolck-shaped floating gates;forming a second dielectric layer on the block-shaped floating gates and the third oxide layer;forming a plurality of bit lines on the second dielectric layer, wherein each of the bit lines comprises a conducting layer and a metal silicide layer, and the bit lines are approximately parallel to the billet-shaped control gates; andforming a planarized polysilicon dielectric layer on the second dielectric layer for completely covering the bit lines.