Patent ID: 8631214
Filing Date: 2014-01-14
Classification: G06F

Abstract:
1. A memory control circuit comprising: an input buffer having a variable storage capacity and configured to capture and store data in synchronization with a first clock signal; an output buffer having the variable storage capacity and configured to output stored data in synchronization with the first clock signal; a counter configured to cyclically count from a first value to a second value on the basis of the first clock signal; an issuing unit configured to issue a write command if a count value of the counter is a third value and issue a read command if the count value is a fourth value; a first controller configured to write, according to the issuance of the write command, the data stored in the input buffer in a memory in synchronization with a second clock signal and read out, according to the issuance of the read command, an amount of data storable by the output buffer from the memory in synchronization with the second clock signal and write the read out data in the output buffer; a register configured to store a first setting value concerning the storage capacity, a second setting value concerning the second value, and a third setting value concerning one of the third and fourth values to be capable of changing each of the setting values; and a second controller configured to control the input buffer, the output buffer, the counter, and the issuing unit to set the storage capacity, the second value, and one of the third and fourth values respectively to values corresponding to the first, second and third setting values.