Patent ID: 7280401
Filing Date: 2007-10-09
Classification: G11C

Abstract:
1. A memory array circuit comprising: memory cells; first read bit lines coupled to a first subset of the memory cells; first NAND gates coupled to the first read bit lines, wherein each of the first NAND gates has two inputs that are coupled to two of the first read bit lines; first transistors, each of the first transistors having an input coupled to an output of one of the first NAND gates; a first global bit line coupled to each of the first transistors; second read bit lines coupled to a second subset of the memory cells; second NAND gates coupled to the second read bit lines, wherein each of the second NAND gates has two inputs that are coupled to two of the second read bit lines; second transistors, each of the second transistors having an input coupled to an output of one of the second NAND gates; a second global bit line coupled to each of the second transistors; and a third NAND gate having a first input coupled to the first global bit line and a second input coupled to the second global bit line.