Patent ID: 6504789
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a latency length setting circuit for variably setting latency length, said latency length being a period from the time that an instruction to read data stored in a memory cell is performed to when said data is read out from said memory cell and output outside; and a control circuit for controlling such that a read operating period from when said instruction to read data is performed to when reading of said data is completed is proportional to said latency length; a sense amplifier for reading data stored in said memory cell, wherein said control circuit synchronizes said read operating period to a sense amplifier activation period where said sense amplifier is activated, wherein said sense amplifier includes: a differential amplifier that operates during said sense amplifier activation period to output data stored in said memory cell, an equalizer for short-circuiting differential output terminals of said differential amplifier during said sense amplifier activation period, bias circuits for supplying bias voltages to differential input terminals of said differential amplifier during said sense amplifier activation period, a reference cell for supplying a mean voltage of a first voltage applied to one differential input terminal when said memory cell is an on cell, and a second voltage applied to said one differential input terminal when said memory cell is an off cell, to an other differential input terminal, and current detectors for detecting currents flowing in said reference cell and an object memory cell to be read respectively.