Patent ID: 7676646
Filing Date: 2010-03-09
Classification: G06F

Abstract:
1. A wide register processing unit, comprising: a wide register set including a plurality of wide registers, each having a wider bit length than supported in a main register set, at least one of the wide registers to store data associated with packet scheduling that is loaded from a memory location; a wide processing unit configured to perform logic operations on data having a wider bit length stored by one or more of the wide registers in the wide register set, where the wide processing unit is configured to operate independently of a main processing unit used for processing contents in the main register set; and an interlocking mechanism to provide a first thread exclusive access to at least one memory location, the first thread to store data from the memory location into the wide register for processing by the wide processing unit, wherein the interlocking mechanism is configured to record in a link-listed table that a second thread is to be provided exclusive access to the at least one memory location upon release by the first thread, when processing by the first thread is complete, the interlocking mechanism is configured to release exclusive access to the at least one memory location from the first thread and provide exclusive access to the second thread according to the link-listed table, the second thread to write the data from the wide register used by the first thread to at least another wide register for subsequent use by the second thread.