Patent ID: 7598587
Filing Date: 2009-10-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate of p type; a semiconductor layer of n type provided on said semiconductor substrate; a first buried impurity region of n type provided at an interface between said semiconductor substrate and said semiconductor layer; a second buried impurity region of p type provided at an interface between said semiconductor layer and said first buried impurity region; a first impurity region of n type provided in an upper surface of said semiconductor layer above said second buried impurity region; and a second impurity region of p type provided apart from said first impurity region in said upper surface of said semiconductor layer above said first buried impurity region so as to surround said first impurity region in a perspective view from said upper surface toward said semiconductor substrate therebelow, wherein, upon applying a higher potential to said first impurity region than to said second impurity region, said second impurity region and said second buried impurity region are electrically isolated from each other by a depletion layer, and said first impurity region and said first buried impurity region are electrically isolated from each other by a depletion layer.