Patent ID: 6528736
Filing Date: 2003-03-04
Classification: H05K

Abstract:
A printed circuit board having at least two conductor layers and adapted for reduced interfacial shear stresses, comprising:a laminate substrate having: a top layer forming a first major surface and having a first conductor pattern formed thereon; a bottom layer forming a second major surface opposed to the first major surface and having a second conductor pattern formed thereon; and a middle layer selectively etched to isolate selected portions of the first and second surfaces and define interconnect regions therebetween having a predetermined height; a compliant adhesive layer comprised of a low modulus material having a first major surface secured to a second major surface of the substrate, and a second major surface; and a base having a first major surface secured to the second major surface of the adhesive layer; wherein the low modulus material and the height of the interconnect regions are selected such that their combination provides said reduced interfacial shear stresses.