Patent ID: 8924449
Filing Date: 2014-12-30
Classification: G06F

Abstract:
1. A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being a preset output symbol rate, fs being a frequency of input clock, the method comprising: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs−1; when N=fs−1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N≠fs−1, waiting for the next rising edge of the input clock after letting the counter N add 1; and letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.