Patent ID: 7230448
Filing Date: 2007-06-12
Classification: H04L

Abstract:
1. An on-DRAM termination resistance control circuit for adjusting a resistance within a semiconductor memory device that performs an on-DRAM termination operation, comprising: push-up resistance adjusting means for adjusting resistances of a first inner resistor and a second inner resistor based on an external reference resistor; pull-down resistance adjusting means for adjusting a resistance of a third inner resistor based on the second inner resistor that is adjusted by the push-up resistance adjusting means; and resistance adjustment control means for controlling the operations of the push-up resistance adjusting means and the pull-down resistance adjusting means for a predetermined commanded adjustment time, wherein the resistance adjustment control means includes a ring oscillator controlling means for outputting a control signal to start an operation and finish the operation for the predetermined commanded adjustment time depending on an external resistance adjust command.