Patent ID: 7547630
Filing Date: 2009-06-16
Classification: H01L

Abstract:
1. A semiconductor apparatus comprising: a semiconductor chip having edges, a first surface and a second surface, the first surface including first contact pads near the respective edges and active components remote from the edges; vias extending from the first to the second surface and positioned between the first pads and the respective edges, the vias having a diameter, an insulating coat, and a metal-filled core; each via having on the first surface a routing trace to one pad, and on the second surface a metal bump; seals against microcracks located between the vias and the respective nearest edge, and seals against thermo-mechanical stress located between the vias and the active components; a workpiece having a third surface including second contact pads matching the locations of the vias; and the chip vertically stacked on the workpiece so that the third surface faces the second surface and each second contact pad is aligned and in electrical contact with the corresponding via bump.