Patent ID: 7921323
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A method, comprising: providing two or more separate signal processing circuits, each one of said two or more signal processing circuits including multiple ASIC devices that each includes a respective packet router; providing a high bandwidth interconnection medium coupled between said signal processing circuits to form a reconfigurable communications infrastructure of said two or more signal processing circuits, the two or more signal processing circuits being selectively segregatable from each other, and the respective ASIC devices of each one of said two or more signal processing circuits being directly coupled to said high bandwidth interconnection medium by a respective common interface provided for the ASIC devices of each of said two or more signal processing circuits with no other processing device intervening between the high bandwidth interconnection medium and said respective ASIC devices; and selectively communicating data between said two or more signal processing circuits by selectively routing data through the packet router of each of the respective ASIC devices of each one of said signal processing circuits across a first common interface to the high bandwidth interconnection medium and to an other one of said signal processing circuits through a second common interface to the packet router of each of the respective ASIC devices of said other one of said signal processing circuits without routing said data through any other intervening processing device between each respective ASIC device and the high bandwidth interconnection medium.