Patent ID: 8392856
Filing Date: 2013-03-05
Classification: G06F,H01L,Y02P

Abstract:
1. A semiconductor device comprising: a plurality of line features including at least one real feature which includes a gate electrode portion and a protruding portion protruding beyond the gate electrode portion by a predetermined distance, and at least one dummy feature placed in parallel with the at least one real feature, wherein two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features extending in parallel so as to be evenly spaced, the parallel running line features have an identical width while at least one end portions of the parallel running line features form line end portions substantially flush with one another, line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features so that the distances between the line end portions and corresponding line end portions of the line end portion uniformization dummy features are equal, the line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features, wherein both end portions of the parallel running line features form the line end portion terminated so that the line end portions are substantially flush with one another, and features forming mirror images of the line end portions about a line are formed on extensions of the line end portions forming both end portions of the parallel running line features so that the distances between the line end portions and corresponding line end portions of the features are equal.