Patent ID: 8637942
Filing Date: 2014-01-28
Classification: C09K,H01L

Abstract:
1. A semiconductor transistor comprising: a gate insulating layer formed on a semiconductor substrate; a gate pattern formed on the gate insulating layer, the gate pattern including a patterned metal nitride layer on the gate insulating layer, a gate electrode layer on the patterned metal nitride layer, and a gate capping layer pattern on the gate electrode layer; a first gate spacer on a first side of the gate pattern; and a second spacer on a second side of the gate pattern, wherein the gate insulating layer extends outside of the first and second gate spacers, the first gate spacer is separate from the second gate spacer, and the metal nitride layer has a larger width than the gate electrode layer such that sidewalls of the metal nitride layer are spaced apart from sidewalls of the gate electrode layer.