Patent ID: 8987829
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a p-channel semiconductor active region having a p-type source region and a p-type drain region; an n-channel semiconductor active region having an n-type source region and an n-type drain region; an element isolation insulating layer which electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region; and an insulating layer made of a material different from that of the element isolation insulating layer, and being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region to apply a compression stress in the channel length direction to a channel of the p-channel semiconductor active region, wherein, the p-channel semiconductor active region is surrounded by the insulating layer, which is in contact with the both ends, in the channel length direction, of the p-channel semiconductor active region, and the p-channel semiconductor active region is surrounded by the element isolation insulating layer, which is in contact with side surfaces, approximately parallel to the channel length direction, of the p-channel semiconductor active region, and the n-channel semiconductor active region is surrounded by the element isolation insulating layer.