Patent ID: 8159020
Filing Date: 2012-04-17
Classification: G11C,H01L

Abstract:
1. Nonvolatile two-transistor semiconductor memory cell comprising: a memory transistor having a predetermined threshold voltage, which has a source region and drain region with a channel region lying in between in a substrate, a first memory transistor insulation layer, a charge storage layer, a second memory transistor insulation layer and a memory transistor control layer being formed at the surface of the channel region; and a selection transistor having a predetermined threshold voltage, which has a source and drain region with a channel region lying in between in the substrate, a first selection transistor insulation layer and a selection transistor control layer being formed at the surface of the channel region; wherein a selection transistor threshold in the selection transistor and a memory transistor threshold in the memory transistor are different due to different insulation layers and are raised by an increased substrate doping and, wherein the selection transistor control layer is formed differently from the charge storage layer for correction of the threshold raising in the selection transistor, the charge storage layer and the selection transistor control layer each having a metallic layer; and wherein the metallic layer of the selection transistor control layer is formed from a different material than the metallic layer of the charge storage layer such that a change in the work function in the selection transistor forces back the threshold voltage of the selection transistor to thereby reduce electric fields responsible for tunneling in the memory transistor.