Patent ID: 7732326
Filing Date: 2010-06-08
Classification: H01L

Abstract:
1. A method for processing a semiconductor structure defining a metallization layer comprising the steps of: providing a substrate having a top surface, said top surface defining said metallization layer; capping said metallization layer with a thin stop layer deposited to a thickness of less than 100 Å over said top surface; depositing an inter-metal dielectric (IMD) layer over said thin stop layer; depositing and patterning a resist layer to define a patterned mask over said IMD layer; etching an upper portion of said IMD layer to remove material according to said patterned mask using an oxygen-containing etchant gas; etching a lower portion of said IMD layer to remove material according to said patterned mask using an oxygen-free etchant gas to expose said thin stop layer, wherein said upper portion and said lower portion of said IMD layer are formed of a same material with no etch stop layer formed of a different material therebetween; removing said resist layer; removing said exposed thin stop layer using an etchant gas free from oxygen; and filling an opening in said IMD layer with a metal to form an upper metallization layer, wherein said opening is formed by said steps of etching said upper portion and said lower portion of said IMD layer.