Patent ID: 7564663
Filing Date: 2009-07-21
Classification: H02H,H03F,H03K

Abstract:
1. An integrated circuit comprising: a first RF port; a second RF port; a limiter section disposed between the first RF port and second RF port; and a detector section, coupled to the limiter section and coupled to an RF signal path between the first RF port and the second RF port, the detector section configured to detect a power level of an input signal received on an input port comprising one of the first and second RF ports, and to couple first and second detector output signals, distinct from the input signal, to first and second ports of the limiter section, causing the limiter section to limit the input signal; wherein the input signal may have a positive or negative voltage polarity at any instant, and wherein the difference between the first and second detector output signals at the first and second ports of the limiter section causes the limiter section to limit the input signal independently of the voltage polarity of the input signal.