Patent ID: 6030869
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A method for fabricating a nonvolatile semiconductor memory device, comprising the steps of:a) forming a stacked gate portion by stacking a tunnel insulating film, a floating gate, a capacitive insulating film and a control gate in this order over a top face of a semiconductor substrate of a first conductivity type;b) forming first and second diffusion layers each of a second conductivity type by implanting first impurity ions of the second conductivity type and second impurity ions of the second conductivity type, respectively, using the stacked gate portion as a mask in an active region of the semiconductor substrate, the first and second diffusion layers forming a portion of a drain region; andc) forming a third diffusion layer of a first conductivity type surrounding the bottom of the portion of the drain region of the second conductivity type, which portion is formed of the first and second diffusion layers, the third diffusion layer comprising third impurity ions of the first conductivity type;d) forming a sidewall on a side face of the stacked gate portion; ande) forming a fourth diffusion layer of the second conductivity type to complete the drain region by implanting fourth impurity ions of the second conductivity type using the stacked gate portion and the sidewall as a mask, the drain region being formed of the first, second, and fourth diffusion layers,wherein the first diffusion layer is formed so as to exhibit an overlap with a portion of the stacked gate portion when viewed from above, andthe fourth diffusion layer, the second diffusion layer and the first diffusion layer are formed so as to be arranged in this order along a direction from an edge of the sidewall to an edge of the gate stacked portion in a region beneath the top face of the semiconductor substrate.