Patent ID: 9214400
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an SOI wafer, which comprises a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; MOSFETs formed in the SOI wafer, wherein each of the MOSFETs comprises a back gate and a back gate isolation region being formed under the back gate, the back gate and the back gate isolation region being formed in the semiconductor substrate; and a shallow trench isolation formed between adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein the shallow trench isolation comprises: wherein a PN junction is formed between the back gate and the back gate isolation region of the each of the MOSFETs and below the shallow trench isolation; and wherein another PN junction is formed between back gate isolation regions, which abut each other, of the adjacent MOSFETs.