Patent ID: 6751142
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of data lines; a plurality of word lines crossing said data lines; dummy word lines crossing said data lines; a memory cell array including a plurality of memory cells arranged at cross-points of said plurality of word lines and data lines; dummy cells arranged at cross-points of said dummy word lines and said data lines; and a sense amplifier coupled to said data lines; wherein said memory cell array is arranged between said dummy cells and said sense amplifier, wherein each of the plurality of memory cells includes a read MOS transistor and a write MOS transistor, wherein each of said dummy cells includes a first dummy read MOS transistor and a first dummy write MOS transistor, wherein a current flowing through a channel region of the write MOS transistor flows in a direction that crosses a surface of the semiconductor substrate, wherein a current flowing through a channel region of the first dummy write MOS transistor flows in a direction that crosses the surface of the semiconductor substrate.