Patent ID: 9190513
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A n-channel double diffusion MOS transistor, comprising: a p-type semiconductor substrate; a p-type epitaxial layer formed on the p-type semiconductor substrate through epitaxial growth; a n-type buried layer provided in a boundary between the p-type semiconductor substrate and the p-type epitaxial layer; a p-type body layer provided in a surface portion of the p-type epitaxial layer; a n-type source layer provided in the p-type body layer and defining a double diffusion structure together with the p-type body layer; a n-type drift layer provided in a surface portion of the p-type epitaxial layer in spaced relation from the p-type body layer to define a channel region between the n-type source layer and the n-type drift layer; a n-type drain layer provided in a surface portion of the p-type epitaxial layer in spaced relation from the channel region and in contact with the n-type drift layer; a p-type buried layer buried in the p-type epitaxial layer between the n-type drift layer and the n-type buried layer and being in contact with an upper surface of the n-type buried layer, and being absent from a region present under the p-type body layer, and being spaced apart from the n-type drift layer, and having a lower impurity concentration than the n-type buried layer; a gate insulation film provided in a surface of the p-type epitaxial layer on the channel region; and a gate electrode provided in opposed relation to the channel region with intervention of the gate insulation film.