Patent ID: 7852655
Filing Date: 2010-12-14
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a first p-type active region; a second p-type active region formed in a first direction a first distance away from the first p-type active region; a first n-type active region formed a second distance away from the first p-type active region between the first p-type active region and the second p-type active region; a second n-type active region formed a third distance away from the first p-type active region between the first p-type active region and the second p-type active region, the third distance being longer than the second distance; a first n-type transistor having a first gate electrode formed on the first p-type active region; a third n-type transistor having a third gate electrode formed on the first p-type active region; a second n-type transistor having a second gate electrode formed on the second p-type active region; a fourth n-type transistor having a fourth gate electrode formed on the second p-type active region; a first p-type transistor having a fifth gate electrode formed on the first n-type active region; a second p-type transistor having a sixth gate electrode formed on the second n-type active region; a first contact connected to the fifth gate electrode of the first p-type transistor; a second contact connected to a second drain electrode of the second p-type transistor; a third contact connected to the sixth gate electrode of the second p-type transistor; a fourth contact connected to the first drain electrode of the first p-type transistor; a fifth contact connected to a third drain electrode of the first n-type transistor; and a sixth contact connected to a fourth drain electrode of the second n-type transistor; wherein: the first contact, the second contact and the sixth contact are electrically connected to each other, the third contact, the fourth contact and the fifth contact are electrically connected to each other, the third gate electrode and the fifth gate electrode are electrically connected to each other, the fourth gate electrode and the sixth gate electrode are electrically connected to each other, the first contact is arranged between the second p-type active region and the first n-type active region, the third contact is arranged between the first p-type active region and the second n-type active region, the first gate electrode is arranged in a second direction perpendicular to the first direction with respect to the third gate electrode, and the fourth gate electrode is arranged in the second direction with respect to the second gate electrode, and wherein: the fifth gate electrode and the sixth gate electrode extend in the first direction, and a pair of the first gate electrode and the second gate electrode, a pair of the third gate electrode and the fourth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction, or the first gate electrode and the second gate electrode extend in the first direction, and a pair of the third gate electrode and the fourth gate electrode, a pair of the fifth gate electrode and the sixth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction, or the third gate electrode and the fourth gate electrode extend in the first direction, and a pair of the first gate electrode and the second gate electrode, a pair of the fifth gate electrode and the sixth gate electrode, or a combination thereof is configured to extend obliquely with respect to the first direction.