Patent ID: 7586337
Filing Date: 2009-09-08
Classification: G06F

Abstract:
1. A clock switching circuit comprising: a selector which outputs a first control signal when a first clock signal is selected by a selection signal and a first permission signal is not enabled, and which outputs a second control signal when the second clock signal is selected by the selection signal and a second permission signal is not enabled, the selection signal selecting either of the first clock signal and the second clock signal; a first stabilizer which receives and holds the first control signal timed with the first clock signal, and which outputs the second permission signal; a second stabilizer which receives and holds the second control signal timed with the second clock signal, and which outputs the first permission signal; a first gating cell circuit which is operative in response to the second permission signal to latch and output the first clock signal as a first output clock signal; a second gating cell circuit which is operative in response to the first permission signal to latch and output the second clock signal as a second output clock signal; an output circuit which outputs the first output clock signal output from said first gating cell circuit or the second output clock signal from said second gating cell circuit as the output clock signal; a first latch which is operative in response to the first permission signal to prevent said selector from outputting the first control signal; and a second latch which is operative in response to the second permission signal to prevent said selector from outputting the second control signal.