Patent ID: 6656841
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of forming a multi-layer conductive line, comprising the steps of:(a) forming a lower conductive line on a semiconductor substrate in which a lower layer is formed; (b) performing a wet cleaning process to remove impurities remaining on the entire structure and etch an exposed portion of the lower conductive line; (c) performing a selective growth process to form a sacrificial barrier layer at the etched portion of the lower conductive line that was etched in the step (b); (d) forming an interlayer insulating film on the entire structure; (e) etching the interlayer insulating film by means of a dual damascene process so that the sacrificial barrier layer is exposed, to form a dual damascene pattern; and (f) depositing an electroplating film to bury the dual damascene pattern and then performing a chemical mechanical polishing process to form an upper conductive line.