Patent ID: 7336752
Filing Date: 2008-02-26
Classification: H03L

Abstract:
1. A delay locked loop comprising: a digitally controlled delay line circuit which selectively enables delay elements to provide coarse phase adjustment in the delay locked loop; an analog delay line circuit which provides a fine phase adjustment in the delay locked loop in response to a control signal; a phase comparator configured to compare an input clock signal and an output clock signal; a first detection circuit providing a first condition signal in response to an output clock signal rising edge occurring after a rising edge of the input clock signal; a second detection circuit providing a second condition signal in response to the output clock signal rising edge occurring after a falling edge of the input clock signal; and a lock detector circuit configured to hold the digitally controlled delay line circuit at a fixed delay in response to the lock detector circuit detecting that the first and second condition signals are present while the analog delay line circuit provides for fine phase adjustment.