Patent ID: 6314442
Filing Date: 2001-11-06
Classification: G06F

Abstract:
A floating-point arithmetic unit comprising:an arithmetic operation portion receiving mantissa data in a first floating-point data and mantissa data in a second floating-point data, for performing arithmetic operation of the data;an increment portion connected to said arithmetic operation portion, receiving the arithmetic result made by said arithmetic operation portion, specifying a bit in said arithmetic result as a least significant bit (LSB) on the assumption that either no overflow shift of the most significant bit (MSB) in said arithmetic result occurs, or cancellation shift of the MSB in said arithmetic result occurs, and for applying increment to said specified LSB;a round-off decision portion receiving the arithmetic result made by said arithmetic operation portion, for deciding whether to round up a bit in a position one place lower than the LSB in said arithmetic result on the basis of said arithmetic result; anda first selector receiving the arithmetic result made by said arithmetic operation portion, the arithmetic result made by said increment portion, and the decision result made by said round-off decision portion, for selectively outputting one of the arithmetic result from said increment portion and the arithmetic result from said arithmetic operation portion in accordance with the decision result from said round-off decision portion.