Patent ID: 6274393
Filing Date: 2001-08-14
Classification: H01L,Y10S

Abstract:
A method of processing a wafer/mask combination, comprising the steps of:a. providing a wafer and a mask layer, with the mask layer positioned on the wafer, wherein the mask layer includes at least one submicron opening, located over a test area on the wafer that is not used to form active circuit areas on the wafer;b. applying a marking technique to form a mark on the test area of the wafer through said opening in the mask layer;c. removing only a portion of the mask layer from the wafer, said portion being over the test area of the wafer, while keeping the remainder of the mask layer on the wafer; andd. inspecting the test area of the wafer, while keeping said remainder of the mask layer on the wafer, for the presence of the mark to determine whether the opening extends completely through the mask layer.