Patent ID: 6264851
Filing Date: 2001-07-24
Classification: C23F,H05K

Abstract:
An electroless plating process for fabricating a substrate for primary printing of printed circuit wiring patterns, comprising the steps of:a) bonding a copper foil to an insulating base by heat and pressure means;b) removing said copper foil from said insulating base, thereby forming an adhesion promoting surface on said insulating base;c) forming a resist layer on said adhesion promoting surface;d) forming imagewise openings through said resist layer to a surface of said insulating base, said imagewise openings being defined by sidewalls and a bottom surface, thereby leaving undeveloped, upper resist surfaces;e) depositing on said upper resist surfaces comprising said sidewalls and said bottom surface of said imagewise openings, a seed layer consisting essentially of a non-precious or noble metal and alloys therefrom;f) selectively removing said seed layer from said upper surfaces of said resist layer by mechanical grinding in a liquid medium of said seed layer, while retaining seed layer portions in said imagewise openings defined by sidewall and bottom surfaces;g) depositing, by a non-electrolytic process, a conductive material onto the surface of the retained seed layer portions in said imagewise openings, andh) chemically polishing said conductive material.