Patent ID: 6800510
Filing Date: 2004-10-05
Classification: G02F,H01L

Abstract:
A method of controlling a capacitance of a TFT-LCD storage capacitor, comprising the steps of:forming a first conductive layer on a transparent substrate; patterning the first conductive layer to form a gate and a bottom electrode on the transparent substrate; forming a first silicon nitride layer on the transparent substrate; forming a dielectric layer on the first silicon nitride layer; forming a second silicon nitride layer on the dielectric layer; forming an undoped amorphous silicon layer on the second silicon nitride layer; forming a doped amorphous silicon layer on the undoped amorphous silicon layer, wherein an etching selectivity ratio of the undoped and doped amorphous silicon layers over the dielectric layer is not less than about 5.0;sequentially patterning the doped amorphous silicon layer, the undoped amorphous silicon layer, and the second silicon nitride layer to form a stacked layer on the dielectric layer over the gate; forming a second conductive layer on the transparent substrate; sequentially patterning the second conductive layer and the doped amorphous silicon layer to form a source and a drain on either side of the gate; forming a passivation layer over the transparent substrate; patterning the passivation layer to form a contact window to expose the source or drain; forming a transparent conductive layer on the passivation layer and in the contact window; and patterning the transparent conductive layer to form a pixel electrode to connect the exposed source or drain through the contact window electrically, and an overlap between the pixel electrode and the bottom electrode forming a storage capacitor.