Patent ID: 6436770
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of fabrication of a vertical transistor; comprising the steps of:a) forming isolation regions in a substrate; said isolation regions defining an active area; b) forming a source region in said active area; c) forming a dielectric layer over said active area and said isolation regions; d) forming a barrier layer over said dielectric layer; e) forming an opening in said barrier layer; said opening at least partially over said active area; f) forming a gate layer in said opening; g) forming an insulating layer over said conductive layer and said barrier layer; h) forming a gate opening through said insulating layer, said gate layer and said dielectric layer to expose said source region; said gate opening defines at least by sidewalls of said conductive layer; i) forming a gate dielectric spacers over said sidewalls of said gate layer; j) forming a conductive plug filling said gate opening; k) removing said insulating layer; l) forming a drain region in top and side portions of said conductive plug and forming doped gate regions in said gate layer; the remaining portions of said conductive plug comprise a channel region; m) forming an interlevel dielectric layer over said barrier layer, said gate layer, and said conductive plug; and n) forming contacts through said interlevel dielectric layer to said doped gate regions, said drain region and said source region.