Patent ID: 8461902
Filing Date: 2013-06-11
Classification: H03K

Abstract:
1. A multiplexer (MUX) circuit comprising: an initial MUX stage comprising a plurality of initial stage MUX units to receive a plurality of input bits, each of the plurality of initial stage MUX units having a respective select bit input, the initial MUX stage controlled with at least a first select bit and a second select bit assigned to the select bit inputs of the initial stage MUX units; a final MUX stage coupled to the initial MUX stage and having a final stage MUX unit to provide one of the plurality of input bits as an output bit, the final stage MUX unit having a respective select bit input, the final MUX stage controlled with at least a third select bit assigned to the select bit input of the final stage MUX unit; and an intermediate MUX stage coupled between the initial MUX stage and the final MUX stage, the intermediate MUX stage comprising a plurality of intermediate stage MUX units, each of the plurality of intermediate stage MUX units having a respective select bit input, the intermediate MUX stage controlled at least in part with the first select bit or the second select bit assigned to the select bit inputs of the intermediate stage MUX units.