Patent ID: 9048820
Filing Date: 2015-06-02
Classification: H03K

Abstract:
1. A duty cycle calibration circuit for a high-speed full-differential clock, comprising: a first adjustment stage ADJ 1 , a first buffer stage BUF 1 , a second adjustment stage ADJ 2 , a second buffer stage BUF 2 , and a duty cycle detection stage DCD, wherein: a first and a second signal input terminal at the left side of the first adjustment stage ADJ output signals OUT output signals OUTB output signals OUT output signals CKO+ and CKO− from a first and a second signal output terminal of the second buffer stage BUF output signal CP from a first signal output terminal of the duty cycle detection stage DCD is fed back and connected to a third signal input terminal of the first adjustment stage ADJ output signal CN from a second signal output terminal of the duty cycle detection stage DCD is connected to a fourth signal input terminal of the first adjustment stage ADJ CP and CN signals are positive control voltage and negative control voltages, respectively; the first adjustment stage ADJ the first adjustment stage or the second adjustment stage comprises: a first transistor M source electrodes and substrates of M grid electrodes of M drain electrode of M drain electrode of M substrates of M