Patent ID: 6084307
Filing Date: 2000-07-04
Classification: H01L,Y10S

Abstract:
A memory device comprising:a multi-level digit line pair fabricated in an X-Y plane extending along a portion of a surface of a semiconductor die, the multi-level digit line pair having a first digit line having a width and second digit line having a width, the digit line pair having a vertical twist therein such that the first digit line is located below the second digit line on one horizontal side of the vertical twist and located above the second digit line as an upper digit line on an opposite horizontal side of the twist, the first digit line and the second digit line of the multi-level digit line pair being vertically offset and vertically aligned within the width of each digit line of the multi-level digit line pair along the length thereof on the one horizontal side of the vertical twist and on the opposite horizontal side of the vertical twist, the multi-level digit line pair located in the X-Y plane on the one horizontal side of the vertical twist and located in the X-Y plane on the opposite horizontal side of the vertical twist.