Patent ID: 7940546
Filing Date: 2011-05-10
Classification: G11C

Abstract:
1. A ROM array comprising: a plurality of columns of memory cells; each column of memory cells being coupled to a shared bit line, said shared bit line being shared by that column of memory cells with an adjacent column of memory cells; each column of memory cells being connected to its own associated reference line; and each reference line having associated switch circuitry arranged to selectively couple that reference line to a reference potential, wherein said associated switch circuitry of each reference line couples that reference line to said reference potential when a read operation is performed on a memory cell of the associated column of memory cells, said associated switch circuitry of each reference line decouples that reference line from said reference potential when a read operation is performed on a memory cell of said adjacent column of memory cells, and the associated switch circuitry of each reference line associated with the columns of memory cells connected to the shared bit line decouples those reference lines from said reference potential when the shared bit line is being pre-charged prior to said read operation.