Patent ID: 6304482
Filing Date: 2001-10-16
Classification: G11C

Abstract:
An apparatus of reducing power consumption of single-ended Static Random Access Memory (hereinafter referred as SRAM) comprising:an extra column of memory cell for storing bit status at least;a majority detector that is to determine the value of bit status of a written data and to write said value of bit status into said extra column of memory cell;a data scrambler that is to convert said written data into a storage data in a format with a minority of 0 bits based on said correspondent value of bit status and to write said storage data into said single-ended SRAM; anda data de-scrambler that is to convert said storage data read from said single-ended SRAM into its original format based on said correspondent value of bit status stored in said extra column of memory cell and to output the data in its original format.