Patent ID: 8490062
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A method for automatic identification of execution phases in load test data, comprising: receiving load test data indicating processor utilization for a plurality of threads over a period of time; dividing the period of time of the load test data into a plurality of intervals; for each pair of proximate intervals of the plurality of intervals, determining whether a statistical characterization of thread-wise processor utilization for a first interval of the pair of intervals is statistically indistinguishable from a statistical characterization of thread-wise processor utilization for a second interval of the pair of intervals; combining the pair of proximate intervals into a single interval when it is determined that the statistical characterization of processor utilization for the first interval is statistically indistinguishable from the statistical characterization of processor utilization for the second interval, for each of the plurality of threads; and dividing each of the pair of proximate intervals into subintervals when it is determined that the statistical characterization of processor utilization for the first interval is not statistically indistinguishable from the statistical characterization of processor utilization for the second interval, for at least one of the plurality of threads, wherein one or more execution phases are automatically identified as occurring between proximate intervals that are not substantially equivalent, wherein the steps of receiving the load test data, dividing the period of time, determining indistinguishablity, combining proximate intervals, and dividing proximate intervals are performed using one or more computer systems.