Patent ID: 7960199
Filing Date: 2011-06-14
Classification: G02F,H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate, the method comprising: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming source and drain electrodes and a semiconductor layer in a channel between the source and drain electrodes, and forming a channel protective film on the semiconductor layer to protect the semiconductor layer in the channel; forming the drain electrode on the gate insulating film; and forming a pixel electrode such that substantially all of the pixel electrode overlapping the drain electrode contacts the drain electrode, wherein forming the source and drain electrodes, the semiconductor layer and the channel protective film comprises: sequentially forming first and second semiconductor layers and a source/drain metal layer on the gate insulating film; forming a photo-resist pattern having a step coverage on the source/drain metal layer using a partial exposure mask; patterning the first and second semiconductor layers and the source/drain metal layer using the photo-resist pattern to provide an active layer, an ohmic contact layer and source and drain electrodes; ashing the photo-resist pattern; patterning the source/drain metal layer and the ohmic contact layer corresponding to the channel using the ashed photo-resist pattern to expose the active layer in the channel; exposing a surface of the exposed active layer to at least one of Ox or Nx to provide the channel protective film on the exposed active layer; and removing the ashed photo-resist pattern.