Patent ID: 9129688
Filing Date: 2015-09-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first string including a first memory cell, a first select transistor, and a second select transistor; a second string including a second memory cell, a third select transistor, and a fourth select transistor; a first bit line coupled to a first terminal of the first select transistor; a second bit line coupled to a first terminal of the third select transistor; a source line coupled to both a first terminal of the second select transistor and a first terminal of the fourth select transistor; a first bit line select transistor, a first terminal of the first bit line select transistor being coupled to the first bit line, a second terminal of the first bit line select transistor being coupled to the source line; a second bit line select transistor, a first terminal of the second bit line select transistor being coupled to the first bit line, a second terminal of the second bit line select transistor being coupled to a sense amplifier; a third bit line select transistor, a first terminal of the third bit line select transistor being coupled to the second bit line, a second terminal of the third bit line select transistor being coupled to the source line; a fourth bit line select transistor, a first terminal of the fourth bit line select transistor being coupled to the second bit line, a second terminal of the fourth bit line select transistor being coupled to the sense amplifier; a first well formed in a substrate; and a second well formed in the first well, the second well including a first area, wherein the first memory cell, the second memory cell, the first bit line select transistor, the second bit line select transistor, the third bit line select transistor, and the fourth bit line select transistor are formed in the first area, and the first bit line select transistor, the second bit line select transistor, the third bit line select transistor, and the fourth bit line select transistor are disposed between the sense amplifier and at least one of the first string and the second string, and when an erase operation is performed, a first voltage is applied to at least one of gates of the first bit line select transistor to the fourth bit line select transistor, and then an erase voltage is applied to the second well.