Patent ID: 7068063
Filing Date: 2006-06-27
Classification: H03K

Abstract:
1. An output buffer circuit comprising: an input terminal for receiving an input signal; an output terminal for outputting an output signal; a first inverter connected to the input terminal, the first inverter outputting a first signal having a slow rise up and fall down characteristic; a second inverter connected to the input terminal, the second inverter outputting a second signal having the slow rise up and fall down characteristic; a pull up control circuit connected to the input terminal, the pull up control circuit including a delay circuit that is connected to the input terminal and that has third inverters connected in series that provide a delayed input signal, the pull up control circuit pulling up a voltage of the first signal under control of the delayed input signal during a predetermined time from a time when the input signal is changed from “L” level to “H” level; a pull down control circuit connected to the input terminal, the pull down control circuit pulling down a voltage of the second signal during a predetermined time from a time when the input signal is changed from “H” level to “L” level; a first output transistor having a source connected to a first power source potential node, a drain connected to the output terminal and a gate connected to the first inverter so as to receive the first signal; and a second output transistor having a source connected to a second power source potential node, a drain connected to the output terminal and a gate connected to the second inverter so as to receive the second signal.