Patent ID: 6779143
Filing Date: 2004-08-17
Classification: G01R

Abstract:
An integrated circuit comprising:(i) a circuit portion having at least one circuit portion latch operable to store a signal value that is reset to a predetermined reset value upon receipt of a reset signal by said circuit portion; and (ii) one or more serial test scan chains each having a plurality of scan chain cells, at least one of said serial test scan chains being operable to store and apply test signals to said circuit portion as part of testing for correct operation of said circuit portion, said test signals being applied to said circuit portion under control of a scan enable signal and synchronously with a clock signal; wherein (iii) said serial test scan chain includes a reset signal generating scan chain cell operable when storing a predetermined reset signal value to generate said reset signal under control of said scan enable signal and independently of and asynchronous with said clock signal.