Patent ID: 8438519
Filing Date: 2013-05-07
Classification: G06F

Abstract:
1. A method of manufacturing an integrated circuit, comprising: specifying a design layout for said integrated circuit, said design layout including proposed dimensions of a plurality of vias and leads in or on one or more interlayer dielectrics of said integrated circuit, and locations of via nodes formed by intersection of said vias and said leads; and performing an electromigration reliability rule-check for at least one of said via nodes by using a computer, including: a) a branch interaction effect, which includes a modification of a current density value of a lead (J b) a width effect, wherein the relative importance factor of the width effect equals the width of the individual lead divided by the width of the narrowest lead of the via node, and c) a length effect, based on properties of the individual lead to generate a modified effective current density; said length effect assigned a value ranging from greater than zero to one, based on one of three different rules: long, short, and mixed length of the individual lead as compared to a threshold length of back stress effects to occur; wherein said modified effective current density for at least one of said leads is equal to a simulated current density multiplied by a branch interaction factor having a value ranging from greater than zero to one, and wherein said branch interaction factor is equal to one when said lead is located in an uppermost interlayer dielectric layer of said integrated circuit, and said branch interaction factor is between one and zero when said lead is located in an underlying interlayer dielectric layer of said integrated circuit and said lead intersects with a bottom diffusion barrier layer of an overlying via.