Patent ID: 7194712
Filing Date: 2007-03-20
Classification: G06F

Abstract:
1. A method for identifying line-end features in a layout for an integrated circuit, comprising: receiving the layout for the integrated circuit; selecting a polygon from the layout; marking a line-end seed on the polygon; wherein marking the line-end seed on the polygon involves performing a linear search of the polygon to identify and mark each line-end seed on the feature; wherein the line-end seed is a horizontal edge in a boundary representation of the polygon; wherein both vertices of the horizontal edge are convex (downward) vertices; and wherein a length of the horizontal edge is less than a given maximum line-end width; determining if the line-end seed is associated with a line feature; if so, marking a line-end feature in the line feature; and using the line-end feature for lithography verification of the layout.