Patent ID: 7298668
Filing Date: 2007-11-20
Classification: G11C

Abstract:
1. A memory module with bus architecture, comprising: a module board including a first surface and a second surface; a plurality of memory components respectively containing memory chips each comprising a memory cell array including memory cells for storing data, wherein a number of the memory components is arranged on the first surface of the module board on first and second sides of the first surface in first and second rows and a remaining number of the memory components is arranged on the second surface of the module board on first and second sides of the second surface in first and second rows; a control component arranged on the first surface of the module board, for controlling the memory chips; a plurality of control buses for transmitting a select signal from the control component to a number of the memory chips for selection of one of the memory chips for storing data, wherein the same number of memory chips is connected to each of the control buses; a plurality of address buses for transmitting address signals from the control component to a number of the memory chips for selection of one of the memory cells of a selected memory chip, wherein the same number of memory chips is connected to each of the address buses; and a plurality of clock buses for transmitting a clock signal from the control component to a number of the memory chips for clock-synchronous operation of the memory chips, wherein the same number of memory chips is connected to each of the clock buses; wherein the number of control buses matches the number of clock buses, and the number of memory chips connected to each of the control buses is the same as the number of memory chips connected to each of the clock buses.