Patent ID: 6432774
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of fabricating memory cell with vertical transistor, comprising:providing a semiconductor substrate; forming a pad layer on the surface of the substrate; forming a deep trench in the substrate; forming a trench capacitor at the lower portion of the deep trench; forming a collar oxide layer on sidewalls of the upper portion of said deep trench that is above trench capacitor; forming a first conductive layer above said trench capacitor and fills said deep trench; etching said first conductive layer to a first predetermined depth in said deep trench to form a first opening; removing a portion of said collar oxide layer above said first conductive layer; forming a second conductive layer to fill said first opening; performing an planarization process to remove said second conductive layer over said pad layer; patterning said pad layer, said substrate, said second conductive layer, said collar oxide layer and said first conductive layer to a second predetermined depth to form a second opening; forming a first insulating layer on both of the said pad layer and said second conductive layer to fill said second opening; removing a portion of said first insulating layer to form a Shallow Trench Isolation; removing the portion of both sides of said Shallow Trench Isolation and said second conductive layer to a third predetermined depth to form a third opening, in which the residual second conductive layer forms a buried strap; removing said pad layer to expose said surface of the substrate; forming a second insulating layer on the exposed surface of said substrate and the surface of said buried strap; forming a well at the upper portion of the substrate; removing said second insulating layer; forming a third insulating layer on the exposed surface of said substrate and the surface of said buried strap to form a gate oxide; sequentially forming a third conductive layer and a fourth conductive layer to fill the fourth opening and to cover the surface of both the substrate and the shallow trench isolation; patterning the third conductive layer and the fourth conductive layer to form a gate; forming source and drain regions; and forming a fourth insulating layer.