Patent ID: 9159387
Filing Date: 2015-10-13
Classification: G11C

Abstract:
1. A memory chip comprising: a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted; a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel; a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area; a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block; a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel; a write timing control unit suitable for controlling operation timing of the serial-parallel conversion unit; a write timing interface unit suitable for transmitting write timing information of the write timing control unit to a write timing interlayer channel; a write timing receiving unit suitable for receiving the write timing information of the write timing interlayer channel; a data exchange unit suitable for controlling data exchange between the write data receiving unit and the core area and data exchange between the read data transmitting unit and the core area; and a write bus control unit suitable for controlling data transfer timing at which the data exchange unit transfers data from the write data receiving unit to the core area, using the write timing information transferred from the write timing receiving unit, wherein enablement of the data processing block, the write data transmitting unit, and the read data receiving unit depends on whether the memory chip is set as master or slave.