Patent ID: 9058463
Filing Date: 2015-06-16
Classification: G06F

Abstract:
1. A system, comprising: a formal verification engine running on a host, which in operation, automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level; a protocol checking engine running on a host, which in operation, checks and validates completeness and correctness of the reference specification; a micro architect engine running on a host, which in operation, implements the IC design protocol at the micro-architectural level using a synthesizable package generated from the formally verified reference specification; a dynamic verification (DV) engine running on a host, which in operation, dynamically verifies the implementation of the IC design protocol at the micro-architectural level and incorporates all incremental changes to the IC design protocol in real time based on a DV reference model generated from the extended state tables of the reference specification.