Patent ID: 7126853
Filing Date: 2006-10-24
Classification: G11C

Abstract:
1. A memory comprising: a group of memory sections functionally arranged in section rows and section columns, each memory section comprising (a) a multiplicity of storage memory cells functionally arranged in cell rows and cell columns and (b) multiple local bit lines each electrically connected to the memory cells in a different one of the cell columns; multiple global bit lines allocated into global bit line sets respectively corresponding to the section columns, each global bit line in each global bit line set associated with a different plurality of the local bit lines in each of the memory sections of the corresponding section column; multiple data lines respectively corresponding to the section columns, each data line associated with the global bit lines for the corresponding section column; a sense amplifier having a data input terminal, a reference input terminal, and an output terminal for providing an output signal indicative of a comparison between signals at the input terminals; a reference current source for providing the reference input terminal with a reference current; and selection/connection circuitry for selecting each local bit line, the selection/connection circuitry being operable to electrically connect each selected local bit line in each memory section of each of the section rows and section columns to the data input terminal by way of (a