Patent ID: 6525647
Filing Date: 2003-02-25
Classification: B61D,G05B

Abstract:
A method of verifying the authenticity of signals to be inputted into an apparatus, said method comprising the steps of:(a) generating twin representations for each of said signals to be inputted into said apparatus, said twin representations embodying either a logic one or a logic zero depending on the state of said signal corresponding thereto; (b) inverting, for each of said signals, one of said twin representations; (c) conveying, for each of said signals, (i) an uninverted one of said twin representations to a location in a first input register and (ii) said inverted one of said twin representations to a mirror-imaged location in a second input register, so that the bit order of said second input register is the reverse of that of said first input register; (d) monitoring at least one of said input registers for whether any bit in said locations therein has changed; (e) reading, whenever any such change is detected, both of said input registers for said bits in said locations thereof such that (i) said bits in said first input register are conveyed to a first work register and (ii) said bits in said second input register are re-inverted, reordered to match again the order of said bits read from said first input register, and conveyed to a second work register; (f) comparing each said bit read from one of said work registers with its corresponding twin bit read from the other of said work registers; and (g) commanding said apparatus to (i) operate according to the dictates of said signal(s) should each bit read from said one work register match its corresponding twin bit read from said other work register and (ii) take protective action should any one of said bits read from said one work register fail to match its corresponding twin bit read from said other work register.