Patent ID: 6770925
Filing Date: 2004-08-03
Classification: G11C,H01L

Abstract:
A structure of a flash memory, comprising:a first conductive type substrate; a deep well of second conductive type which is formed in the substrate; a first well of first conductive type which is formed in the substrate but not deeper than the deep well; two stacked gate structures formed on the substrate, wherein the two stacked gate structures are separated with each other with a distance; a second well of second conductive type which is formed in the substrate but not deeper than the first well, wherein the two stacked gate structures are disposed on the surface of the second well; a source region of first conductive type which is formed in and surrounded by the second well, wherein the edge of the source region is connected with the two stacked structures; two drain regions of first conductive type which is formed at the two sides of the source region in the substrate, wherein the edges of the two drain regions are connected with the two stacked gate structures and the second well; and a contact formed across the junction of the source region and the second well to make the source region and the second well short circuit.