Patent ID: 6791355
Filing Date: 2004-09-14
Classification: H03K

Abstract:
In a integrated circuit having a plurality of interconnected logic cells, potentially including at least one defective logic cell, a plurality of spare cells dispersed within the integrated circuit for the replacement of any said defective logic cells, each spare cell comprising:a configurable combinatorial network (CCN) implementing any of a plurality of sum of product logical functions, said CCN having a plurality of equation input terminals that receive control signals which configure the CCN to perform one or more specified logical functions, a plurality of functional input terminals; and one or more output terminals selectively connectable to the integrated circuit through a D flip-flop to replace a defective logic cell, so as to receive variable data signals, from the integrated circuit and to output to the integrated circuit a result of the specified logical function performed upon the data signals, wherein a clock pin of the D flip-flop is connected to a preexisting clock tree in an area of the integrated circuit wherein has been determined that a need for defective cell replacement is highly probable.