Patent ID: 7013355
Filing Date: 2006-03-14
Classification: G06F

Abstract:
1. A device communicating via a serial bus comprising: an internal bus; an internal bus arbiter for controlling said internal bus; a stored device address for identifying said device; a receiver coupled to said serial bus for receiving a predetermined first signal and an address bit by bit; a detector responsive to detecting the predetermined first signal to activate said device for serial communication by causing the assertion of a request signal supplied to the internal bus arbiter; a comparator coupled to match each bit of the received address as it is being received with a corresponding bit of said stored device address; and an address match logic responsive to, either a mismatching of an address bit from said comparator to deactivate said device for serial communication by causing the de-assertion of the request signal supplied to the internal bus arbiter immediately upon detecting said mismatched bit, or a matching of all address bits to issue a predetermined second signal to said serial bus to acknowledge an address match.