Patent ID: 6041401
Filing Date: 2000-03-21
Classification: G06F,Y02D

Abstract:
A computer system, comprising:a bus;a main memory array coupled to the bus;a microprocessor coupled to the bus; anda disk drive coupled to the microprocessor, the disk drive adapted to be spun down to save power:wherein the microprocessor generates a special cycle responsive to the disk drive being spun down;a circuit including:a cache memory device coupled to the bus, the cache memory device having a chip select input;a special cycle decoder coupled to the bus for asserting a first signal if the special cycle is detected; anda chip selector coupled to the chip select input of the cache memory device, the chip select generator deasserting the chip select input if the first signal is asserted, wherein the cache memory device is placed into the low power state in response to the chip select signal being deasserted;wherein the special cycle is a halt special cycle, and wherein the microprocessor generates the halt special cycle on the bus if the microprocessor executes a halt instruction, the halt instruction causing operation of the microprocessor to cease and to place the microprocessor into low power consumption mode.