Patent ID: 6212656
Filing Date: 2001-04-03
Classification: G01R

Abstract:
A method for designing scan mode circuitry for testing electrical interconnections within an integrated circuit design, the method comprising:identifying each one of a plurality of scan-flops that will be part of the scan mode circuitry;declaring each one of the plurality of scan-flops as being part of a valid scan path and writing the plurality of scan-flops to an executable file;executing a Unix c-shell script for creating a plurality of scan sub-chains from the plurality of scan-flops, such that the creating includes defining a plurality of holding tanks for storing each of the scan sub-chains;declaring a scan path for each of the scan sub-chains that are stored in each of the plurality of holding tanks;declaring a set of test signals for each of the scan sub-chains; andstitching each of the scan sub-chains of the plurality of scan-flops that are part of the executable file.