Patent ID: 8923375
Filing Date: 2014-12-30
Classification: G01R,H03L,H04B,H04L

Abstract:
1. A method for performing a jitter tolerance test, the method comprising: receiving an input signal at an input signal frequency; generating a first clock signal based on the input signal frequency, the first clock signal phase shifted by approximately 180 degrees from the input signal; generating a second clock signal based on the first clock signal, the second clock signal phase shifted by a first amount in a first direction; generating a third clock signal based on the first clock signal, the third clock signal phase shifted by a second amount in a direction opposite to the first direction; comparing values of the input signal at three distinct latch times, the three latch times based on the first clock signal, second clock signal and third clock signal; and indicating the jitter tolerance test has been passed responsive to the values of the input signal matching after being latched at the three latch times.