Patent ID: 6319770
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor, comprising the following steps:sequentially forming a first sacrificial layer, an intermediate layer and a second sacrificial layer on a substrate;forming an aperture on the first sacrificial layer, the intermediate layer and the second sacrificial layer; forming an annular groove in the inner circumferential surface of the aperture by removing a fixed depth of the intermediate layer;filling the aperture and the annular groove with a first amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer, wherein the second amorphous silicon layer has a lower impurity concentration than those of the first amorphous silicon layer and the third amorphous silicon layer, and the first amorphous silicon layer and the second amorphous silicon layer fill into the annular groove forms an annular ring;removing the first sacrificial layer and the second sacrificial layer to reveal the first amorphous silicon layer;removing a predetermined depth of the first amorphous silicon layer to reveal the second amorphous silicon layer;removing the intermediate layer to reveal the first amorphous silicon layer at the annular ring; and forming a plurality of hemispherical grains on the first amorphous silicon layer, the second amorphous silicon layer and the third amorphous silicon layer.