Patent ID: 6304097
Filing Date: 2001-10-16
Classification: G01R

Abstract:
A system for modeling a target interconnect capacitance, the system comprising:a test structure formed on an IC chip comprising:an interconnect configuration formed on the IC chip and comprising a test interconnect and a target interconnect, the interconnect configuration having the target interconnect capacitance between the test and target interconnects;a test interconnect charging circuit formed on the IC chip and connected to the test interconnect, the test interconnect charging circuit being configured to place a test charge on the test interconnect; anda target interconnect charging circuit formed on the IC chip and connected to the target interconnect, the target interconnect charging circuit being configured to draw a target interconnect charging current from the target interconnect in response to the test charge to place an opposite charge on the target interconnect that is induced by the target interconnect capacitance;a current meter connected to the target interconnect charging circuit and configured to make a measurement of the target interconnect charging current, whereby a measurement of the target interconnect capacitance may be computed from the measurement of the target interconnect charging current.