Patent ID: 6911854
Filing Date: 2005-06-28
Classification: G06F,H03K

Abstract:
1. A clock skew tolerant clocking scheme comprising: a data stream; a clock signal, said clock signal having a clock cycle, said clock signal comprising a plurality of clock pulses, each of said clock pulses of said plurality of clock pulses comprising a clock pulse rising edge and a clock pulse falling edge and a clock pulse width between said clock pulse rising edge and said clock pulse falling edge; a first pulse signal, said first pulse signal comprising a plurality of first pulses, each of said first pulses of said plurality of first pulses comprising a first pulse rising edge and a first pulse falling edge and a first pulse width between said first pulse rising edge and said first pulse falling edge, said first pulse signal being generated by a first local pulse generator, said first pulse signal being derived from said clock signal such that each of said first pulses of said plurality of first pulses corresponds to one of said clock pulses of said plurality of clock pulses and each of said first pulse rising edges of said first pulses are generated by a corresponding clock pulse rising edge of said corresponding one of said plurality of clock pulses, said first pulse width being less than fifty percent of said clock pulse width; a second pulse signal, said second pulse signal comprising a plurality of second pulses, each of said second pulses of said plurality of second pulses comprising a second pulse rising edge and a second pulse falling edge and a second pulse width between said second pulse rising edge and said second pulse falling edge, said second pulse signal being generated by a second local pulse generator, said second pulse signal being derived from said clock signal such that each of said second pulses of said plurality of second pulses corresponds to one of said clock pulses of said plurality of clock pulses and each of said second pulse rising edges of said second pulses are generated by a corresponding clock pulse falling edge of said corresponding one of said plurality of clock pulses, said second pulse width being less than fifty percent of said clock pulse width; a first transparent pulse latch, said first pulse signal being operatively coupled to said first transparent pulse latch; a second transparent pulse latch, said second pulse signal being operatively coupled to said second transparent pulse latch; wherein, for each clock pulse of said plurality of clock pulses of said clock signal there is a first pulse of said plurality of first pulses of said first pulse signal generated by a rising edge of said clock pulse and a corresponding second pulse of said plurality of second pulses of said second pulse signal generated by a falling edge of said clock pulse; further wherein, there is a frequency dependent separation window between a falling edge of said first pulse and rising edge of said corresponding second pulse such that race conditions are avoided.