Patent ID: 8305109
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A logic circuit comprising: a depletion-type transistor in which a high power supply potential is applied to one of a source and a drain and a gate is connected to the other of the source and the drain; and an enhancement-type transistor in which one of a source and a drain is connected to the gate of the depletion-type transistor and a low power supply potential is applied to the other of the source and the drain, wherein the depletion-type transistor and the enhancement-type transistor each comprise: wherein a thickness of the oxide semiconductor layer of the depletion-type transistor is larger than a thickness of the oxide semiconductor layer of the enhancement-type transistor, wherein a first signal is input to the first gate electrode of the enhancement-type transistor, wherein a potential of a portion where the enhancement-type transistor and the depletion-type transistor are connected to each other is output as a second signal, and wherein one of the depletion-type transistor and the enhancement-type transistor comprises a second gate electrode.