Patent ID: 8081511
Filing Date: 2011-12-20
Classification: G11C

Abstract:
1. An apparatus comprising: a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and third and fourth redundancy interleave groups of redundant columns; first and second data latches configured to store data read from the first and second interleave groups of regular columns, respectively; third and fourth redundant data latches configured to store data read from the third and fourth redundancy interleave groups of redundant columns, respectively; a multiplexer comprising at least four inputs, each of which is electrically coupled to a respective one of the first and second data latches and the third and fourth redundant data latches; and a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme.