Patent ID: 8542179
Filing Date: 2013-09-24
Classification: G09G,G11C

Abstract:
1. A gate signal line driving circuit which applies a high voltage to gate signal lines in a signal high period and applies a low voltage to the gate signal lines in a signal low period different from the signal high period, comprising: a high voltage application switching element which is put into an ON state in response to the signal high period to apply the high voltage to the gate signal lines and which is put into an OFF state in response to the signal low period; first and second low voltage application switching elements which are connected in parallel to the gate signal lines and which apply the low voltage to the gate signal lines when the first and second low voltage application switching elements are in the ON state; a control voltage output circuit which includes a holding capacitor that supplies an ON signal toward at least one of the switch inputs of the first and second low voltage application switching elements in the signal low period; a first control switching element which is put into an ON state in a first period including the high and low periods and which puts the first low voltage application switching element into an OFF state; a second control switching element which is put into an ON state in a second period that is different from the first period and includes the high and low periods and which transmits the ON signal to the first low voltage application switching element; a third control switching element which is put into an ON state in the second period and which puts the second low voltage application switching element into an OFF state; a fourth control switching element which is put into an ON state in the first period and which transmits the ON signal to the second low voltage application switching element; and a shift register control circuit which controls ON/OFF of the first to fourth control switching elements, wherein the shift register control circuit puts the first to fourth control switching elements into an ON state in a startup period before the first and second periods and supplies an initial voltage that causes electric charge to be stored in the holding capacitor, the electric charge supplying the ON signal to the holding capacitor through the first and third control switching elements, and wherein the shift register control circuit puts the first and fourth control switching elements into an ON state and the second and third control switching elements into an OFF state in the first period and puts the second and third control switching elements into an ON state and the first and fourth control switching elements into an OFF state in the second period.