Patent ID: 8927372
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a first insulating layer, a metal dielectric pattern and a gate electrode on a substrate; forming a second insulating layer on the first insulating layer and the gate electrode; forming a first discharge site in the second insulating layer; forming a plurality of sacrificial spacers on the second insulating layer to face opposing sidewalls of the gate electrode; and performing an ion injecting process using the sacrificial spacers as a mask to form a plurality of doped regions in portions of the substrate adjacent to the opposing sidewalls of the gate electrode, wherein the forming of the gate electrode and the metal dielectric pattern comprises: forming a metal dielectric on the substrate; forming a conductive layer on the metal dielectric, wherein the conductive layer includes a polysilicon layer and the metal dielectric includes one of a hafnium oxide layer (HfO patterning the conductive layer and the metal dielectric to form the gate electrode on the first insulating layer and the metal dielectric pattern between the first insulating layer and the gate electrode.