Patent ID: 8604557
Filing Date: 2013-12-10
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of said first n-type transistor via a contact plug and a drain of said first p-type transistor via a shared contact plug; and a second wiring layer having a first conductive portion electrically connected to said first interconnecting portion; wherein said second wiring layer includes said first conductive portion adjacent to a first wiring of power line which supplies a first power supply voltage to be supplied to the first p-type transistor and a second wiring of power line which supplies a second power supply voltage to be supplied to the first n-type transistor in said second wiring layer, wherein a portion of a first bit line is provided in the second wiring layer and a distance between said first conductive portion and said portion of first bit line is larger than a distance between the said first conductive portion and said first wiring of power line, wherein said second wiring layer is formed in a layer above said first wiring layer.