Patent ID: 6359324
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A pair of semiconductor devices configured for a push-pull operation, comprising:a first device, comprising: a first n-doped region; a first p-doped region; a p-doped channel situated between said first n-doped and first p-doped regions, wherein a first depletion region exists within said channel when a reverse bias voltage is applied across said first n-doped and first p-doped regions; and a first photosensitive region comprising a relatively high p-doped region situated within said p-doped channel and partially including said first depletion region when said reverse bias voltage is applied across said first n-doped and first p-doped regions, wherein hole-electron pairs are generated from said partial first depletion region within said first photosensitive region in response to an incident light upon said first photosensitive region; a second device, comprising: a second p-doped region; a second n-doped region; an n-doped channel situated between said second n-doped and second p-doped regions, wherein a second depletion region exists within said n-doped channel when a reverse bias voltage is applied across said second n-doped and second p-doped regions; and a second photosensitive region comprising a relatively high n-doped region situated within said n-doped channel and partially including said second depletion region when said reverse bias voltage is applied across said second n-doped and second p-doped regions, wherein hole-electron pairs are generated from said partial second depletion region within said second photosensitive region in response to said incident light upon said second photosensitive region; a first impedance load connected to said first n-doped region for receiving a first bias voltage; a second impedance load connected to said second p-doped region for receiving a third bias voltage; and wherein said first p-doped region and said second n-doped region are coupled together to a third bias voltage, and wherein said first bias voltage is more positive than said third bias voltage, and further wherein said third bias voltage is more positive than said second positive voltage.