Patent ID: 7590023
Filing Date: 2009-09-15
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a test internal voltage supply means for generating a test internal voltage based on a reference voltage; a level detecting means for detecting a level of an internal voltage based on the reference voltage and for producing an internal voltage driving signal; a standby internal voltage generating means for supplying an standby internal voltage in response to the internal voltage driving signal in a standby mode; a mode detecting means for detecting the level of the internal voltage based on the test internal voltage and producing a plurality of mode signals; a plurality of active internal voltage generating means for supplying the internal voltage in an active mode, wherein the active internal voltage generating means is driven by one of a plurality of active high voltage driving signals; a supplementary active internal voltage generating means for additionally supplying a supplementary internal voltage when an amount of an external voltage is not sufficient in the active mode; and an active control means for selectively driving the plurality of active internal voltage generating means and the supplementary active internal voltage generating means in response to the plurality of mode signals and the internal voltage driving signal.