Patent ID: 6560690
Filing Date: 2003-05-06
Classification: G06F

Abstract:
A method for accessing a particular one of at least one cache line, referenced by a linear address, in an global/non-global-linear-addressed cache memory, comprising:predicting a global/non-global value of a data block referenced by the linear address, the global/non-global value indicating whether the data block is shared among a plurality of processes; combining a process identifier with the linear address to form the global/non-global linear address if the predicted global/non-global value indicates that the data block is non-shared, otherwise, setting the global/non-global linear address to the linear address; and comparing the global/non-global linear address with each of at least one tag, each of the at least one tag corresponding to each of the at least one cache line, to determine if the global/non-global linear address matches any of the at least one tag.