Patent ID: 6269138
Filing Date: 2001-07-31
Classification: H03K

Abstract:
A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line comprising a number of low power binary counter blocks corresponding to the number of bits of the counter, the low power binary counter blocks being connected in series and each comprising a flip-flop as memory means consuming a minimum amount of power when disabled and which is activated only when a value of a respective data output connection of the memory means has to be changed, in which a data output connection of the flip-flop is connected to an input terminal of a first inverter, an output terminal of which is connected to a data input connection of the flip-flop, the data output connection of the flip-flop being further connected to an input terminal of an AND gate, an output terminal of which is connected to a block output terminal, a block input terminal being connected to another input terminal of the AND gate and an input terminal of a second inverter, the output terminal thereof being connected to an enable input connection of the flip-flop.