Patent ID: 6581172
Filing Date: 2003-06-17
Classification: G01R,G11C

Abstract:
A system for testing a plurality of integrated circuits mounted on a common substrate, the substrate having a first signal port adapted to be coupled to a testing device, the testing system comprising one or more failure processors mounted on the substrate, each failure processor having a second signal port coupled to the first signal port, and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested by that failure processor, each of the test ports being coupled to a respective one of the integrated circuits, each failure processor being constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits, each failure processor further being constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.