Patent ID: 8049530
Filing Date: 2011-11-01
Classification: H03K

Abstract:
1. A method for calibrating the impedance at a plurality of nodes in an integrated circuit, comprising: evaluating for each group of a plurality of groups of node circuitry an impedance of a model representative of an impedance of the node circuitry in each group, wherein each group comprises at least one node circuitry, wherein each model is proximate to its associated node circuitry group, wherein each node circuitry comprises X N-channel enable transistors and X P-channel enable transistors, where X is an integer; and in response to each evaluated impedance, generating a plurality of sets of control signals for each node circuitry group to calibrate the impedance of the node circuitry in each group, wherein each set of control signals comprises 2X control signals sent to one model and to that model's associated node circuitry, the 2X control signals being independent of each other, and wherein the plurality of control signals are unique to its associated group, wherein each model and its proximate associated node circuitry group are confined to an area of a surface of the integrated circuit, and wherein the areas are distributed about the surface of the integrated circuit.