Patent ID: 6750493
Filing Date: 2004-06-15
Classification: G11C,H01L

Abstract:
A semiconductor storage device comprising:a first memory cell block having a plurality of memory cells connected together in series, each of the memory cells comprising a cell transistor and a ferroelectric capacitor, the ferroelectric capacitor having an electrode at one end and an electrode at the other end which are connected to a source and a drain of the cell transistor, respectively; a first block selection transistor which selects the first memory cell block; a first metal interconnect connected between one end of the first memory cell block and one end of a current path in the first block selection transistor; a first bit line connected to the other end of the current path in the first block selection transistor; a second bit line arranged adjacent to the first bit line; and second and third block selection transistors each having a current path one end of which is connected to the second bit line, wherein interconnects connected to gate electrodes of the second and third block selection transistors are disposed below the first metal interconnect.