Patent ID: 6232807
Filing Date: 2001-05-15
Classification: H03L

Abstract:
A pulse generating circuit comprising a first pulse generating means receiving an input clock signal for generating a first pulse in synchronism with the clock signal, a first P-channel MOS transistor having a source connected to a high voltage supply, a gate connected to an output of the first pulse generating means and a drain connected to an output line, a first delay means having a first predetermined delay time and having an input connected to the output line, a second pulse generating means having an input connected to an output of the first delay means, for generating a second pulse in synchronism with a level transition of the output of the first delay means, a first N-channel MOS transistor having a drain connected to the output line, a gate connected to an output of the second pulse generating means and a source connected to ground, and a detecting means connected to the output of the first pulse generating means and also connected to the output line, for bringing the output line to a low level when the input clock signal changes from a low level to a high level in the condition that the output line is at a high level.