Patent ID: 6330190
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A non-volatile memory device having a first memory cell structure, comprising:a semiconductor substrate of first conductivity type having a surface;a first well region disposed in the substrate adjacent the surface thereof, the first well region of second conductivity type opposite to the conductivity of the first conductivity type;a second well region of first conductivity type disposed in the first well region adjacent the surface;a floating gate overlying the surface, the floating gate having a first end and a second end;a control gate at least partially overlying the floating gate;a drain region provided at the first end of the floating gate; anda source region provided at the second end of the floating gate;wherein, to perform an erase operation on the first memory cell structure, a negative potential is applied to the control gate, the source and drain regions are disconnected from any potential source, a first positive potential is applied to the first well region, and a second positive potential is applied to the second well region disposed within the first well region,wherein the difference of magnitude of the applied negative potential and the applied second positive potential is no more than 3 volts in absolute term.