Patent ID: 6965660
Filing Date: 2005-11-15
Classification: H03L

Abstract:
1. A digital phase-locked loop having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock signal in a normal operating state of the digital phase-locked loop, the digital phase-locked loop having: (a) a phase detector for identifying a phase deviation ΔΦ between the reference clock signal and a feedback clock signal; (b) a resettable counter, which generates a digital phase deviation signal corresponding to the identified phase deviation ΔΦ; (c) a resettable digital filter for filtering the digital phase deviation signal generated; (d) a digitally controlled oscillator circuit for generating the output clock signal as a function of a filtered digital phase deviation signal; (e) a resettable feedback frequency divider which divides the output clock signal for generating the feedback clock signal with an adjustable frequency division ratio; characterized by an integrated reset circuit, which resets the counter, the digital filter and the feedback frequency divider as long as the digital phase deviation signal exceeds an adjustable digital threshold value.