Patent ID: 9170818
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A processing device comprising: a plurality of physical registers; a register map comprising a first map entry that is associated with a first architectural register, the first map entry being adapted to store a first identifier of a first physical register of the plurality of physical registers such that a program instruction that accesses the first architectural register results in an access of the first physical register; a first free register list comprising a first free register entry adapted to store a second identifier for a second physical register of the plurality of physical registers, wherein the second physical register is not mapped to the first architectural register, and wherein the first free register entry includes a valid entry indicator; a first checkpoint map comprising a first checkpoint entry that is associated with the first map entry, wherein the first checkpoint entry is adapted to store the first identifier in response to a first program instruction; a scoreboard comprising a first scoreboard entry that is associated with the first physical register, wherein the first scoreboard entry includes a read counter that indicates a number of outstanding reads to the first physical register, a checkpoint indicator that indicates when the first identifier is stored in the first checkpoint entry, and a free tag indicator to store a location identifier for locating an identifier of a physical register in the first free register list; checkpoint logic adapted to: a renaming logic adapted to: