Patent ID: 6131182
Filing Date: 2000-10-10
Classification: G06F

Abstract:
A method for compiling and optimizing high performance control logic from a high level design language logic description using self-resetting complimentary metal oxide semiconductor (SRCMOS) logic array macros (SLAMs), comprising the steps of:(a) partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure;(b) mapping each logic partition to the target SLAM structure wherein the mapping includes the steps of:(b1) optimizing each logic partition using a two-level logic optimization technique:(b2) mapping the resulting two-level logic description of each logic partition to a FIRST OR--STROBED INVERTER--SECOND OR format by Boolean transformations; and(b3) converting the FIRST OR--STROBED INVERTER--SECOND OR format into FIRST OR--STROBED LOGIC GATE--SECOND OR format by combining related circuits;(c) creating a configuration and relative layout for the internal structure for each SLAM;(d) creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM;(e) assembling the partitions implemented as SLAMs with other macros in the unit;(f) resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs;(g) changing the external specifications of the various SLAMs, and repeating stages (b)-(f) as necessary;(h) analyzing the performance of the unit;(i) if the step (h) of analyzing determines that the unit does meet the predetermined metrics, automatically compiling the schematic and layout of each individual SLAM within the unit based on the configuration and relative layout created in step (c); and(j) assembling the various macros that comprise the unit and analyzing the design of the unit for design rule violations.