Patent ID: 8122285
Filing Date: 2012-02-21
Classification: G06F

Abstract:
1. A computer comprising: a memory that stores a BIOS; a CPU that executes the BIOS; and a root port connected to the CPU through a primary bus and to a PCI express path through a secondary bus, the root port functioning as a PCI express bridge; wherein the root port detects a failure on the PCI express path, and then issues a SMI (System Maintenance Interrupt) to the CPU; on the receipt of the SMI, the CPU executes the BIOS to issue, through the root port, a PCI express reset to the PCI express path on which the failure has occurred; and the memory stores a device driver for controlling a PCI express device; and the CPU executes the device driver to detect a PCI express device included in the PCI express path that has received the PCI express reset, and then to disable the use of the detected PCI express device.