Patent ID: 6718514
Filing Date: 2004-04-06
Classification: H03M

Abstract:
A parity checking device for receiving data and checking errors in the data in a data communication system, comprising:a controller for determining loop occurring times according to the length of the data and the number of bits to be shifted according to the data or XOR operation results and determining whether the data has an error based on a final XOR operation result; a first register and a second register for temporarily storing the data or the XOR operation results under the control of the controller; a shifter for receiving the output of the first register and shifting the received bits by the determined number of bits received from the controller; and an operation unit for receiving the outputs of the shifter and the second register, performing an XOR operation between the received data from the shifter and the second register, and outputting an XOR operation result under the control of the controller, wherein said controller is connected to said first register, said second register, said shifter, and said operation unit for providing a control signal.