Patent ID: 8799544
Filing Date: 2014-08-05
Classification: G06F,H04L

Abstract:
1. A system on chip, comprising: a master device, configured to send a transmission request that carries an identifier (ID) indicating a serial number of the master device; a first extending module, configured to add N bits into the ID carried in the transmission request, wherein N varies according to interconnection structures that the transmission request passes through and is a positive integer equal to a sum of bits added by all interconnection structures in a longest loop of the system into the ID carried in the transmission request; a first interconnection structure, configured to add M bits into the ID carried in the transmission request output by the first extending module, wherein M is a positive integer equal to a number of bits added by the first interconnection structure into the ID carried in the transmission request that passes through the first interconnection structure; a first subtracting module, configured to subtract M bits from the ID carried in the transmission request output by the first interconnection structure when a slave device to be accessed by the master device is not a slave device connected with the first interconnection structure; a second interconnection structure, configured to extend the ID carried in the transmission request output by the first subtracting module, and output an extended transmission request until the transmission request is sent to the slave device to be accessed; and wherein the slave device is configured to receive and process the transmission request output by the second interconnection structure or an interconnection structure next to the second interconnection structure in a direction of sending the transmission request.