Patent ID: 6770520
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A method for forming a floating gate, comprising:providing a semiconductor substrate, wherein a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed on the semiconductor substrate, and the surface of the conducting layer is covered by the patterned hard mask layer to form a gate; etching the conducting layer to a predetermined depth to form an indentation using the patterned hard mask layer as a mask; thermally oxidizing the conducting layer to form an oxide layer on the surface of the conducting layer, wherein a portion of the oxide layer is covered under the patterned hard mask layer; sequentially etching the oxide layer and the conducting layer to form a multiple tip conducting layer as a floating gate using the patterned hard mask layer as a mask, leaving the portion of the oxide layer covered under the pattered hard mask layer; and removing the patterned hard mask layer.