Patent ID: 7917871
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. A pattern data generation method comprising: using a computer for: creating at least one modification guide to modify a modification target point contained in pattern data for a formation of at least one interconnect layer of a semiconductor device on a wafer; evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in electric characteristics of the interconnect layer of the semiconductor device formed in accordance with the pattern data; selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides; determining a guideline to judge whether to modify the modification target point contained in the pattern data before modifying the modification target point; and modifying the modification target point in accordance with the selected modification guide when the guideline is satisfied, wherein when the pattern data containing the modification target point is design pattern data for a critical path or a pattern adjacent to the critical path, the judgment guideline is set to be more severe than when the pattern data containing the modification target point is not the design pattern data for the critical path or the pattern adjacent to the critical path.