Patent ID: 9059210
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a sacrificial gate electrode layer over a sacrificial gate dielectric layer; forming sidewall spacers on both sides of the dummy gate structure; performing a deep pre-amorphization implant; performing an ion implantation to form heavily doped source/drain regions in the semiconductor substrate; removing the sidewall spacers; after removing the sidewall spacers, forming a stress material layer over the dummy gate structure; performing an annealing process; after the annealing process, removing the stress material layer; forming an interlayer dielectric layer surrounding the dummy gate structure; removing the dummy gate structure to form a groove in the interlayer dielectric layer; forming a high-k dielectric layer and a metal gate structure in the groove; forming contact holes that expose at least part of the heavily doped source/drain regions; and forming a self-aligned silicide over exposed portions of the heavily doped source/drain regions.