Patent ID: 6115770
Filing Date: 2000-09-05
Classification: G06F

Abstract:
An electronic circuit coupled between a priority bus and a secondary bus for coordinating overlapping access requests received from each bus, said electronic circuit comprising:a target data storage location coupled between said priority bus and said secondary bus;a priority access interface coupled between said target data storage location and said priority bus that controls execution of a priority access to said target data storage location from said priority bus, responsive to an access request for said priority access received from said priority bus;a secondary access interface coupled between said target data storage location and said secondary bus that controls execution of a secondary access to said target data storage location from said secondary bus, responsive to an access request for said secondary access received from said secondary bus; anda priority control module coupled to said priority access interface and to said target data storage location that causes execution of said secondary access from said secondary bus to be temporarily blocked during execution of said priority access and in response to said access request for said priority access from said priority bus, and wherein execution of said blocked secondary access is automatically unblocked after execution of said priority access independent of a subsequent request for said secondary access to said target data storage location from said secondary bus.