Patent ID: 8769469
Filing Date: 2014-07-01
Classification: G06F

Abstract:
1. A system for use with circuit layout design data including at least one of disposition of a set of differential pairs and a set of bond wire pairs, the set of differential pairs including a first differential pair, a second differential pair and a third differential pair, the set of bond wire pairs including a first bond wire pair, a second bond wire pair and a third bond wire pair, said system comprising: a layout portion operable to receive the circuit layout design data; a memory for storing data relating to a plurality of amounts of crosstalk, the memory further comprising: a modifier operable to modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover; an optimizer coupled to the memory for generating optimized circuit layout design data by comparing amounts of crosstalk from the plurality of amounts of crosstalk stored in the memory; and a layout designer coupled to the optimizer operable to output the optimized circuit layout design data, wherein said crosstalk calculating portion is further operable to determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data, and wherein said optimizer is operable to compare the first amount of crosstalk with the second amount of crosstalk to generate the optimized circuit layout design data.