Patent ID: 6448649
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A semiconductor device having a multi-layered wiring structure on a semiconductor substrate, comprising:a) a first wiring layer having a predetermined wiring width and a predetermined shape on a semiconductor substrate, said first wiring layer having sidewalls; b) first conductive sidewall spacers composed of a first inner titanium nitride film and a first outer tungsten film formed on said sidewalls of said first wiring layer; said first conductive sidewall spacers not under said first wiring layer; c) an inter metal dielectric layer covering said first wiring layer and said first conductive sidewall spacers; a d) a via in said inter metal dielectric layer over at least a portion of said first conductive sidewall spacers, said via having a width smaller than the total width of said first conductive sidewall spacers and said first wiring layer; e) a first plug in said via electrically connected to at least said first conductive spacer; said first plug having a top, bottom and sides; said first plug has a dimple; f) a second wiring layer having a predetermined wiring width and a predetermined shape; said second wiring layer over and contacting a portion of said first plug; said second wiring layer having sidewalls; and g) second conductive sidewall spacers composed of a second inner titanium nitride film and a second outer tungsten film on said sidewalls of said second wiring layer; said second conductive sidewall spacers not under said second wiring layer; said second inner titanium nitride film is at least partially located within said dimple.