Patent ID: 8997027
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A method for modifying an integrated circuit layout design, the method comprising: providing an initial integrated circuit layout design; correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design; fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments; performing both a bridging condition simulation and a pinching condition simulation on the fragmented layout design, wherein each of the bridging and pinching condition simulations comprises manipulating the fragmented layout design according to various process conditionals that have the potential to result in bridging errors and pinching errors, respectively; calculating, by using a computer, a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation; modifying the fragmented layout design by moving the at least one fragment in accordance with the required movement to generate a modified design; and performing optical proximity correction (OPC) on the modified layout design; and determining that there is a conflict between a required movement to correct a bridging condition and a required movement to correct a pinching condition, and resolving the conflict by determining a priority of movement between the required movement to correct the bridging condition and the requirement movement to correct the pinching condition, and performing the movement according to the priority.