Patent ID: 8476684
Filing Date: 2013-07-02
Classification: H01L

Abstract:
1. A method of forming a transistor, the method comprising: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, forming a gate region between the drain and source; forming a buried layer of a second type of semiconductor beneath the transistor; forming a plug region of the second type of semiconductor around the transistor; forming a screening element over the transistor, wherein the screening element is configured to shield the gate region from electric field gradients; wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source; and forming an intermediate region by doping the semiconductor so as to form the second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.