Patent ID: 8304917
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A multi-chip stacked package comprising: a mother chip being a two-layer structure consisting of a semiconductor layer and an organic layer, wherein a plurality of electrodes are disposed on a first active surface of the semiconductor layer and a redistribution layer is embedded in the organic layer, the redistribution layer having an upper surface and a lower surface unexposed from the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer, wherein the first terminals are electrically connected with the corresponding second terminals through the redistribution layer, and the organic layer completely covers a back surface of the semiconductor layer opposite to the first active surface of the semiconductor layer; a substrate, wherein the mother chip is mounted on the substrate with the first active surface facing the substrate so that the electrodes of the mother chip are electrically connected to the substrate and the organic layer is on the opposite surface of the semiconductor layer from the substrate; a daughter chip attached onto the mother chip, wherein a second active surface of the daughter chip is in contact with the organic layer with a plurality of bonding pads of the daughter chip bonded to the first terminals; and a plurality of electrically connecting components electrically connecting the second terminals to the substrate.