Patent ID: 7180128
Filing Date: 2007-02-20
Classification: G11C,H01L

Abstract:
1. A non-volatile memory, comprising: a substrate; a first row of memory cells comprising a plurality of memory cells, disposed on the substrate, wherein the first row of memory cells comprising: a tunneling dielectric layer, disposed between the floating gates and the substrate; a first source/drain region, disposed in the substrate on one side of the first row of memory cells; a second source/drain region, disposed in the substrate on the other side of the first row of memory cells; and a second row of memory cells comprising a plurality of memory cells having structures identical to those of the first row of memory cells, wherein the first and the second row of memory cells are connected by the second source/drain region, and the selected gates of the first row of memory cells are connected to the selected gates of the second row of memory cells through a plurality of select gate lines and each select gate line is substantially perpendicular to the control gate line.