Patent ID: 6571375
Filing Date: 2003-05-27
Classification: G06F

Abstract:
A method comprising:linking a plurality of design verification checks associated with a language representation of a hardware design by determining dependency relationships among the plurality of design verification checks, each of the plurality of design verification checks representing a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals among one or more variables in the language representation of the hardware design; and wherein said determining dependency relationships among the plurality of design verification checks includes for each design verification check of the plurality of design verification checks disabling, in an internal representation of the hardware design, those of the other plurality of design verification checks that are dependent on the design verification check, evaluating the design verification check with reference to the internal representation of the hardware design, and enabling all of the plurality of design verification checks in the internal representation of the hardware design in anticipation of subsequent dependency relationship analysis.