Patent ID: 6288947
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A memory device having a plurality of pipelatch circuits storing data from memory cells via global input/output lines, a pipelatch input control means to selectively couple the pipelatch circuit to the global input/output lines in response to a pipelatch control signal, and a pipe count signal generator to control a data path between the pipelatch circuits and an output driver, wherein the pipelatch input control means comprises:a first control signal generator receiving a first control signal and global input/output line signals and producing a pass gate control signal;a second control signal generator receiving the first control signal and the pass gate control signal and producing a plurality of second control signals;a third control signal generator receiving the pass gate control signal and producing a third control signal by combining the pass gate control signal and a delay signal of the pass gate control signal; anda fourth control signal generator receiving the first control signal, the plurality of second control signals and the third control signal and producing the pipelatch control signal.