Patent ID: 8698528
Filing Date: 2014-04-15
Classification: H03L,H04L

Abstract:
1. An apparatus, comprising: an integration circuit that integrates values between a start edge and an end edge of input data and outputs an integration value at timing of the end edge as a data center value, based on a first clock signal or that integrates values between a data center and a next data center for a unit interval of the input data and outputs an integration value at timing of the data center as an edge value, based on a second clock signal; a sampling circuit that samples a value of a data edge of the input data, based on the first clock signal or a value of the data center, based on the second clock signal; a first determination circuit that determines a data value using the integration value of the integration circuit; a second determination circuit that determines a data value using the sampling value of the sampling circuit; a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit; and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the first clock signal or the second clock signal.