Patent ID: 7971166
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. A method performed by a computer of testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process, said method comprising: generating testbench design code for a device design from a design source containing hardware design language code; performing, by said computer, a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches, and/or registers within the device design will be stable or unstable under a gating condition; then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition; or then ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition.