Patent ID: 9099168
Filing Date: 2015-08-04
Classification: G11C

Abstract:
1. An integrated circuit comprising: a positive power supply node; a first plurality of PMOS transistors coupled in series and coupled to the positive power supply node, wherein gates of the plurality of PMOS transistors are coupled to a clock signal; a plurality of diodes coupled between the first plurality of PMOS transistors and an electrical ground; a charging node; a second plurality of PMOS transistors configured to form current mirrors with each other, wherein each of the second plurality of PMOS transistors is coupled between the positive power supply node and the charging node; a third plurality of PMOS transistors, each coupled between one of the second plurality of PMOS transistors and the charging node, wherein a gate of each of the third plurality of PMOS transistors is coupled to a drain of one of the first plurality of PMOS transistors; and a PMOS transistor forming current mirrors with the second plurality of PMOS transistors, wherein a drain of the PMOS transistor is coupled to the charging node.