Patent ID: 6509776
Filing Date: 2003-01-21
Classification: H03K,H03L,Y10S

Abstract:
A DLL (delay locked loop) circuit comprising a signal propagation system and a delay control system, andwherein said signal propagation system comprises: a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal, and said delay control system comprises: a sampling circuit which outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of said delayed clock signal; a phase comparing circuit which compares said first clock signal as a first comparison input signal and said reference clock signal as a second comparison input signal in phase to output a phase difference; and a delay control circuit which generates said delay control signal based on said phase difference from said phase comparing circuit to output to said delay circuit of said signal propagation system, wherein said sampling circuit comprises: a frequency divider which divides a frequency of said delayed clock signal into 1/n to generate a division signal; and a selection output circuit which selectively outputs a pulse corresponding to each of said pulses of said delayed clock signal based on said division signal.