Patent ID: 6288587
Filing Date: 2001-09-11
Classification: G04F,H03K

Abstract:
A cyclic CMOS Time-to-Digital Converter with deep subnanosecond resolution, comprising:a realized coupling control circuit composed of first and second control circuit NAND gates, wherein the first control circuit NAND gate couples an input pulse and a loopback output pulse to the beginning of a cyclic delay line for a next pulse shrinking cycle, and the second control circuit NAND gate provides a RESET input terminal for resetting said cycling delay line back to a correct stable state; anda counter used to count the circulation times of the input pulse in said cyclic delay line, said circulation times representing a measurement output of said Time-to-Digital Converter,wherein said cyclic delay line is composed of an even number of homogeneous NOT gates and said first and second control circuit NAND gates.