Patent ID: 6175885
Filing Date: 2001-01-16
Classification: H03K,H03M,H04L

Abstract:
A device for the series-to-parallel conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal with a period T, the device being designed to convert said series signal into n parallel logic signals, the device comprising:a series input comprising a first input terminal and a second input terminal, the differential signal being received between said first and second input terminals;a parallel output comprising n output terminals to deliver the n parallel logic signals;a clock circuit to deliver n clock signals with a period nT that are staggered with respect to one another by a time interval equal to T; andn sample-and-hold units for obtaining samples of said series signal staggered with respect to one another by a time interval equal to T, each sample-and-hold unit comprising a first input and a second input respectively connected to said first and second input terminals, a control input to receive one of said n clock signals and an output connected to one of the output terminals of the parallel output to deliver a sample;wherein the sample-and-hold units simultaneously amplify the samples of said series signal;wherein each sample-and-hold unit has a master part to sample said series signal and amplify the resulting samples, and a slave part to store said samples;wherein the master part comprises:a first connection gate connected, on the one hand, to the first input of the sample-and-hold unit and, on the other hand, to an input of a first inverter and to an output of a second inverter; anda second connection gate connected, on the one hand, to the second input of the sample-and-hold unit and, on the other hand, to an output of the first inverter and to an input of the second inverter;wherein the first and second connection gates are controlled by a first pair of control signals coming from said clock signal applied to the control input of the sample-and-hold unit.