Patent ID: 9136241
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A manufacturing method of a chip package, comprising: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer, wherein a spacer layer of single material is disposed therebetween and defines a plurality of cavities respectively exposing the device regions, wherein each cavity is defined within a perimeter having sides not extending beyond immediate adjacent scribe lines, wherein the spacer layer has a plurality of independent through holes disposed at each of the sides of the perimeter and surrounding and neighboring the edge of each cavity, and wherein each through hole itself does not completely surround any device region; filling an adhesive material in the through holes wherein the single material of the spacer layer is adhesive and different from the adhesive material, and wherein the adhesive material and the single material of the spacer layer are non-electrically conductive; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.