Patent ID: 6853039
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A dual-gate CMOS semiconductor device comprising: a semiconductor substrate having an NMOS region and a PMOS region; a first polycrystalline silicon layer formed on the NMOS region of the semiconductor substrate, the first polycrystalline silicon layer having N type impurities; a second polycrystalline silicon layer formed on the PMOS region of the semiconductor substrate, the second polycrystalline silicon layer having P type impurities; and a first conductive layer formed on the first and second polycrystalline silicon layers, the first conductive layer having an opening between the first and second polycrystalline silicon layers, wherein the first and second polycrystalline silicon layers and the first conductive layer are a gate electrode, and wherein the first conductive layer is a tungsten silicide layer and an insulating layer almost equal in height to the first conductive layer is formed in the opening.