Patent ID: 6320222
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A dual-gated transistor on a substrate, comprising:a first source/drain region, a body region, and a second source/drain region, the body region having opposing sidewall surfaces, and wherein the body region includes a fully depleted structure;a first gate located on a first on one of the opposing sidewall surfaces; anda second gate located on a second one of the opposing sidewall surfaces, the dual-gated transistor formed by a method comprising:forming a first source/drain region on the substrate;vertically forming a body region on the first source/drain region, wherein vertically forming the body region includes vertically growing an epitaxial layer, such that the body region is formed as a high quality single crystalline structure, and wherein the body region is defined to have a width which is sufficiently thin, vis-a-vis a doping concentration (NA) of the body region such that a bulk charge (QB) is negligible in transistor operation;forming a second source/drain region on the body region;forming a first gate on a first one of the opposing sidewall surfaces, and separated by a first oxide; andforming a second gate on a second one of the opposing sidewall surfaces, and separated by a second oxide such that a threshold voltage for the transistor depends only on a thickness of the first and the second oxides and the width of the body region.