Patent ID: 6609164
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A direct memory access system, comprising:a central processing unit; a DMA unit; a random access memory; a data source/destination unit; a common bus, such bus interconnecting the central processing unit, the direct memory access controller and the random access memory; a local cache memory coupled to the central processing unit; wherein the direct memory access controller controls the flow of the data between the random access memory and the data source/destination unit; wherein the DMA unit comprises: a pair of address registers, a first one of such registers storing an address for the random access memory and a second one of such registers storing a copy of such address; a multiplexer having an output coupled to the common bus and having a pair of inputs, each one of such pair of inputs being coupled to a corresponding one of the pair of registers; a controller for coupling a first one of the registers to the common bus to provide an address for the random access memory during a first common bus cycle and for coupling the second one of the pair of registers to the bus to provide an address for the random access memory during a subsequent common bus cycle.