Patent ID: 7577795
Filing Date: 2009-08-18
Classification: G06F

Abstract:
1. A data caching method comprising: storing portions of data in slower main memory associated with at least one Central Processing Unit (CPU) comprising a processor or a microprocessor; transferring data to and from a faster memory comprising a cache memory structure located between at least one CPU and said main memory; with said cache structure further comprising an individual L1 cache memory communicating first to an associated L2 cache memory to check said associated L2 cache memory, to obtain a copy of a particular cache line of data at a given L2 cache location prior to reading data from, reading data to, or modifying cached data at said given L2 cache location; providing for each previously stored cache line in said L2 cache memory to have an ownership state exclusive to a particular identified CPU or an ownership state of exclusive to no CPU; determining when a given previously stored cache line in said L2 cache no longer exists in a particular L1 cache memory location with any ownership state; and then sending a signal to said associated L2 cache memory indicating that said ownership=state of said given previously stored cache line in said L1 cache memory has changed from an state of exclusive to a particular identified CPU to an ownership state of exclusive to no CPU with said L2 cache memory thereby being updated to indicate that said given previously stored cache line in said L2 cache is disowned; whereby no cross interrogation or invalidation is necessary when said given cache line is to be returned for a request from any L1 cache, thereby improving overall system performance.