Patent ID: 7768828
Filing Date: 2010-08-03
Classification: G11C

Abstract:
1. A flash memory device, comprising: a memory cell array including a plurality of memory blocks; a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not an inputted block address corresponds to a multi-bit memory block based on the stored multi-bit/single-bit information and outputting a multi-bit/single-bit flag signal indicative of whether the inputted block address corresponds to a multi-bit memory block; a read/write circuit for selectively performing multi-bit and single-bit read/program operations of a memory block corresponding to the inputted block address; and control logic for controlling the read/write circuit such that the read/write circuit performs multi-bit or single-bit read/program operations based on the multi-bit/single-bit flag signal, wherein the read/write circuit stores the multi-bit/single-bit information to a selected memory block in a program operation of the selected memory block under control of the control logic.