Patent ID: 7093166
Filing Date: 2006-08-15
Classification: G11C

Abstract:
1. An information handling system comprising: at least one microprocessor; a physical memory coupled to said at least one microprocessor, said physical memory configured to store an operating system; and a physical memory testing subsystem configured for a) querying the operating system for the size of said physical memory and a number of microprocessors, b) in response to the number of microprocessors, creating memory tester threads equal in number to the number of microprocessors, c) in response to the size of said physical memory, allocating memory chunks of a virtual memory to be equal to the size of said physical memory, d) dividing the allocated memory chunks equally among the memory tester threads, e) creating a scanner thread, and f) executing the memory tester threads and scanner thread, wherein a memory tester thread performs an actual memory test algorithm, and wherein the scanner thread is configured to maintain the allocated memory in physical memory for a duration of physical memory testing by the memory tester threads.