Patent ID: 6209114
Filing Date: 2001-03-27
Classification: H03M

Abstract:
A programmable logic device, comprising:control circuitry, for receiving program instructions and for generating control signals responsive thereto;a data bus; anda Chien search execution unit coupled to the data bus, for executing a Chien search instruction under the control of the control circuitry, and comprising:a plurality of finite field multipliers, each for performing finite field multiplication upon a symbol value and a coefficient to produce a product;finite field addition circuitry, for performing finite field addition of the products from the plurality of finite field multipliers to produce a final sum;zero detection circuitry, coupled to an output of the finite field addition circuitry, for generating a root detection signal responsive to the final sum equaling zero;error magnitude and position circuitry, coupled to receive the root detection signal, for storing error magnitude and position values in selected registers responsive to receiving the root detection signal;a symbol register, having outputs coupled to the plurality of finite field multipliers, for storing the symbol values; anda coefficient register, having outputs coupled to the plurality of finite field multipliers, and having inputs coupled to outputs of the plurality of finite field multipliers, for storing the coefficients applied to the plurality of finite field multipliers, and for storing the products from the plurality of finite field multipliers.