Patent ID: 9013007
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A depletion normally-on type MOS transistor, comprising: a well region having a first conductivity type formed on a semiconductor substrate; a gate insulating film formed on the well region; a gate electrode formed on the gate insulating film, the gate electrode having a second conductivity type different from the first conductivity type; source and drain regions formed on respective sides of the gate electrode and within the well region, the source and drain regions having the second conductivity type; a first low concentration impurity region having the second conductivity type and being formed below the gate insulating film between the source and drain regions and within the well region, the first low concentration impurity region and the gate electrode having the same conductivity type to achieve normally-on operation of the MOS transistor; and a second low concentration impurity region having the first conductivity type and being formed within the well region and below the first low concentration impurity region between the source and drain regions, the second low concentration impurity region having a maximum peak concentration not greater than that of the first low concentration impurity region and greater than that of the well region.