Patent ID: 6046951
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A process for controlling a read circuit of a memory array comprising the steps of:selecting at least one memory cell of a row of the memory array by generating a selection signal for the corresponding word line of the row, while generating an additional selection signal propagated over an additional word line of an additional row of memory cells, this additional row being arranged in an exterior vicinity of the memory array and configured to exhibit conditions of propagation of the additional signal which are analogous to those of each row of the memory array;using the additional selection signal to select a first reference memory cell structurally analogous to the memory cells of the memory array and having predetermined contents, the first reference memory cell being placed at an intersection of the additional row and of a first column of column memory cells which is arranged in the exterior vicinity of the memory array and is configured to exhibit a column capacitance of predetermined value with respect to a value of column capacitance of each column of the memory array;detecting a reading of the contents of the first reference cell in a zone of the additional column which is spaced substantially by a height of a column of the memory array from a site of generation of the additional selection signal; andactivating the read circuit only if the detection occurs so as to allow the reading of the contents of the selected memory cell or cells of the memory array.