Patent ID: 6184085
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of forming a memory cell having a floating gate therein, comprising the steps of:forming a first electrically insulating layer on a surface of a semiconductor substrate;forming a first conductive layer on the first electrically insulating layer, opposite the surface;forming a second electrically insulating layer on the first conductive layer, opposite the first electrically insulating layer;patterning the second electrically insulating and the first conductive layer to define a floating gate electrode having exposed sidewalls;etching the first electrically insulating layer to define a recess therein that undercuts a portion of the floating gate electrode extending adjacent the exposed sidewalls;oxidizing the exposed sidewalls and the undercut portion of the floating gate electrode to define sidewall insulating spacers; andforming a control electrode on the second electrically insulating layer, opposite the floating gate electrode.