Patent ID: 9082750
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: a device isolation layer defining an active region in a substrate; a tunnel insulating layer on the active region; a charge storage pattern on the tunnel insulating layer, wherein the charge storage pattern comprises an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall; a blocking layer on the charge storage pattern, wherein the blocking layer comprises a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern and a spacer covering the edge portion of the charge storage pattern and exposing a portion of the gate dielectric layer covering the upper surface of the charge storage pattern; and a gate electrode on the blocking layer, wherein a thickness of a first portion of the blocking layer covering the edge portion of the charge storage pattern is greater than a thickness of a second portion of the blocking layer covering the sidewall of the charge storage pattern, and the spacer is between the gate dielectric layer and the gate electrode.