Patent ID: 6795942
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A method for redundancy analysis of a semiconductor memory, wherein the memory comprises regular memory elements and redundant memory elements, and wherein the method uses an iterative sequence, comprising:(a) testing each of a set of regular memory elements for defects, and recording the number of defects found; (b) if the number of defects in one of the regular memory elements exceeds a defect threshold, recording an address of that element, removing the element from the set of elements being tested, reducing the defect threshold, and then reducing a number of available redundant memory elements; (c) if the number of defects in one of the regular memory elements does not exceed the defect threshold, reduce the defect threshold; and (d) reiterating (a), (b) and (c) until the defect threshold reaches a predetermined acceptable level.