Patent ID: 7626843
Filing Date: 2009-12-01
Classification: G11C

Abstract:
1. A dynamic random access memory comprising: a first transistor having a first gate electrode, a first source electrode and a first drain electrode, the first drain electrode being configured as a first input voltage terminal; a second transistor having a second gate electrode, a second source electrode and a second drain electrode, wherein the second source electrode is connected to the first source electrode of the first transistor; and a comparator connected to the second drain electrode, and preconfigured with a reference current; wherein a first parasitic capacitor is formed between the first gate electrode and the first source electrode of the first transistor, and the first parasitic capacitor retains the input voltage for a predetermined period of time; and a first input voltage or a second input voltage is applied to the first drain electrode when the first transistor is in an on-state and the second transistor is in an off-state; and a second voltage which is greater than the first and second input voltages is applied to the second drain electrode when the first transistor is in an off-state and the second transistor is in an on-state.