Patent ID: 6570236
Filing Date: 2003-05-27
Classification: G11C,H01L

Abstract:
A semiconductor device comprising a drain diffusion layer, which is formed on a semiconductor substrate and is in common to first and second transistors that make up a memory cell pair, a source diffusion layer for said first transistor and a source diffusion layer for said second transistor, which are formed on said semiconductor substrate in a manner whereby they are spaced from the drain diffusion layer by predetermined intervals so as to sandwich the drain diffusion layer, a first word line, which is coupled to a gate electrode of said first transistor, a second word line, which is coupled to a gate electrode of said second transistor, a bit line, which is arranged from a first wiring layer above said semiconductor substrate and is connected to said drain diffusion layer, and a source line, which is arranged from a second wiring layer above said first wiring layer above said semiconductor substrate, wherein the writing of information is performed by connection or non-connection of the respective source diffusion layers of said first and second transistors with said source line.