Patent ID: 8370557
Filing Date: 2013-02-05
Classification: G11C

Abstract:
1. A memory system, comprising: a main memory comprising a plurality of single-ported memory banks, each memory bank comprising a first number of entries; parallel busses configured to enable simultaneous writing to and reading from different ones of the single-ported memory banks; a sideband memory comprising the first number of entries, each of the entries in the sideband memory mapping to a corresponding one of the entries in one of the memory banks in the main memory, the sideband memory being configured to allow parallel read and write accesses to the sideband memory per cycle; switching circuitry configured to direct read and write operations to either the main memory or the sideband memory; and control logic configured to track to which of the memory banks in the main memory each of the entries in the sideband memory corresponds, and to deterministically control the switching circuitry in response to memory address information to effect a pattern of access to the main memory and the sideband memory such that the memory system performs like a fully provisioned dual-ported memory, wherein when a read operation and a write operation simultaneous with the read operation are both directed to entries in a first one of the single-ported memory banks in the main memory that are not present in the sideband memory, the control logic is further configured to direct the read operation to the first single-ported memory bank in the main memory and the write operation to the sideband memory.