Patent ID: 9105351
Filing Date: 2015-08-11
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a bit line; four or more word lines; a first memory block and a second memory block, each comprising a sub bit line, a precharge transistor, and a plurality of memory cells; and an amplifier circuit connected to the bit line through a drain and a source of a reading transistor and to the sub bit lines of the first memory block and the second memory block, wherein the plurality of memory cells each comprises a transistor and a capacitor, wherein a drain of the transistor in the first memory block is connected to one of the sub bit line of the first memory block and the bit line, wherein an electrode of the capacitor in the first memory block is connected to the other of the sub bit line of the first memory block and the bit line, wherein a drain of the transistor in the second memory block is connected to one of the sub bit line of the second memory block and the bit line, wherein an electrode of the capacitor in the second memory block is connected to the other of the sub bit line of the second memory block and the bit line, wherein a source of the precharge transistor in the first memory block is connected to the sub bit line of the first memory block, and wherein a source of the precharge transistor in the second memory block is connected to the sub bit line of the second memory block.