Patent ID: 6240048
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A synchronous type dynamic random access memory (SDRAM) comprising:a memory cell array section having an address decoder section and a sense amplifier section;a power down signal generating section generating a first power down signal and a second power down signal based on a clock enable signal, an external clock signal, a signal specific to said SDRAM and a write burst signal, wherein said first power down signal is inactive during a predetermined time period synchronous with said specific signal, and said second power down signal is inactive during a time period during which said write burst signal is supplied;a control signal generating section generating a control signal based on a command signal when said first power down signal is inactive; andan accessing section accessing said memory cell array section based on an external address signal and an external data signal in response to said control signal when said first power down signal or said second power down signals is inactive.