Patent ID: 8441885
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. An apparatus, comprising: a word line decoder receiving address decode signals and outputting a word line decoder signal; a word line clock gating structure coupled to an internal node and receiving a word line clock signal having an active phase and an inactive phase for each period of the word line clock signal, configured to output a word line signal during the active phase of the word line clock signal, responsive to the word line decoder signal; and latch input circuitry coupled between the word line decoder signal and the word line clock gating structure, configured to output the word line decoder signal to the internal node during an inactive phase of the word line clock signal; wherein the address decode signals have a set up time requirement relative to the rising edge of the word line clock signal that begins the active phase of the word line clock signal, and a zero or less hold time requirement relative to the rising edge of the word line clock signal.