Patent ID: 6586299
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A mixed mode process for integration circuits comprising:providing a semiconductor substrate, a surface of the semiconductor substrate comprising at least a conductive region, a metal-oxide-semiconductor (MOS) transistor region and a capacitor region; sequentially forming a gate oxide layer, a first conductive layer, a first silicide layer and a first oxide layer on the semiconductor substrate; performing a first photo-etching-process (PEP) to remove portions of the first oxide layer, first silicide layer and the first conductive layer to simultaneously form a first stacked structure and a second stacked structure respectively in the MOS transistor region and the capacitor region; sequentially forming a second oxide layer and a second conductive layer on the semiconductor substrate to cover the first and second stacked structures; performing a second PEP to remove portions of the second conductive layer to simultaneously form a conductive wire and a top electrode plate of a capacitor respectively in the conductive region and on the second stacked structure; forming a dielectric layer on the semiconductor substrate to cover the conductive wire, the first stacked structure, the top electrode plate and the second stacked structure; performing an etching process to remove portions of the dielectric layer and the second oxide layer to form a spacer on either sides of the conductive wire, the top electrode plate and the second stacked structure; and performing a self-aligned silicide (salicide) process to form a second silicide layer respectively on the conductive wire, the top electrode plate and portions of the surface of the semiconductor substrate adjacent to either sides of the first stacked structure in the MOS transistor region.