Patent ID: 6980036
Filing Date: 2005-12-27
Classification: H03K

Abstract:
1. A semiconductor device comprising: a frequency multiplier at an input terminal of the semiconductor device that receives a clock signal having a predetermined frequency, and that generates a first internal clock signal having a frequency that is greater than the predetermined frequency, a latency controller that controls a latency of the semiconductor device in response to the first internal clock signal and that generates a second internal clock signal according to the latency control result, a data output buffer that outputs test output data for the semiconductor device in response to the first and second internal clock signals, wherein the frequency multiplier comprises: a first pulse signal generating circuit that receives a first clock signal and a second clock signal having the same frequency and that generates a first pulse signal having a first pulse width when a level of the first clock signal is greater than a level of the second clock signal, a second pulse signal generating circuit that is enabled in response to a first control signal, and that generates a second pulse signal having a second pulse width when a level of a received reference voltage is greater than a level of the first clock signal, and an OR circuit that receives the first pulse signal and the second pulse signal, that logically sums the first pulse signal and the second pulse signal, and that outputs the logically summed signal as the first internal clock signal.