Patent ID: 7426529
Filing Date: 2008-09-16
Classification: G06F

Abstract:
1. A processor, comprising: a source register having a source register content; a destination register; a calculating unit for performing a calculation using the source register content, wherein the calculation is performable in several calculation cycles, and in each cycle only one portion of the source register content is usable, and wherein the calculating unit comprises a calculating unit auxiliary device having an intermediate buffer and a bit-slice staple, the intermediate buffer comprising a smaller memory capacity than the source register or the destination register; a data bus which is connected to the source register, the destination register, and the calculating unit; and a processor controller which is operable during the calculation to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand via the data bus, so that after performance of the several calculation cycles the source register content is supplied to the destination register, wherein the processor controller is implemented to fill the intermediate buffer of the calculating unit auxiliary device with a new portion of the source register content when a load control signal is received from the intermediate buffer.