Patent ID: 6886116
Filing Date: 2005-04-26
Classification: G06F

Abstract:
1. A system for validating error detection logic, the system comprising: a plurality of information paths, each one of the paths having associated therewith an error detection logic, each one of the paths having a plurality of information bits; a test word buffer for receiving a test word, the test word indicating a particular one of the plurality of information bits in a particular one of the information paths to be corrupted; a plurality of fault injectors responsive to the test word received by the buffer, each one of the fault injectors being disposed in a corresponding one of the information paths prior to the associated the error detection logic, each one of the fault injectors corrupting a selected one of the information bits in the corresponding one of the information paths in response to the test word received by the buffer to test whether the associated error detection logic detects the injected fault; and wherein the test word buffer stores an indication as to whether software or a processor used to control information flow through the logic is to be tested for response to a detected fault.