Patent ID: 6083790
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method for fabricating an array of Y-shaped multi-fin stacked capacitors on dynamic random access memory (DRAM) devices comprising the steps of:providing a semiconductor substrate having field oxide areas surrounding device areas and said device areas having semiconductor devices;depositing a first insulating layer over said device areas and said field oxide areas;planarizing said first insulating layer;depositing a first polysilicon layer on said planar first insulating layer;depositing a refractory metal silicide layer on said first polysilicon layer to form a polycide layer;patterning said polycide layer to form bit lines for memory cells of said DRAM devices;depositing a conformal second insulating layer and a conformal etch-stop layer over said bit lines;conformally depositing a multilayer composed of a third insulating layer, a second polysilicon layer, a fourth insulating layer, a third polysilicon layer, and a fifth insulating layer over said bit lines;etching capacitor node contact openings in said multilayer, in said etch-stop layer, in said second insulating layer, and in said first insulating layer to said device areas on said substrate;depositing a fourth polysilicon layer sufficiently thick to fill said capacitor node contact openings;patterning said fourth polysilicon layer and said multilayer to said etch-stop layer for forming Y-shaped multi-fin bottom electrodes for said stacked capacitors conforming to said bit lines;isotropically etching said third, fourth, and fifth insulating layers exposed in sidewalls of said patterned multilayer to provide free-standing said Y-shaped multi-fin bottom electrodes, resulting from said conformal multilayer over said bit lines;forming an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a fifth polysilicon layer to form top electrodes thereby completing said array of Y-shaped multi-fin stacked capacitors for said DRAM devices.