Patent ID: 6198158
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A memory circuit, comprising:a semiconductor substrate;address, data, and command busses disposed on the substrate;an address decoder disposed in the substrate and coupled to the address bus;a read/write circuit disposed in the substrate and coupled to the address decoder;a data input/output circuit disposed in the substrate and coupled to the data bus and to the read/write circuit;a control circuit disposed in the substrate and coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit; andan array of memory cells arranged in rows and columns and coupled to the address decoder and the read/write circuit, the array including,a first portion of the substrate having a surface;dielectric runners extending out from the surface and being substantially parallel to one another, the dielectric runners defining trenches therebetween, the trenches having bottoms formed by the surface;recessed memory cells disposed in the trench bottoms;a second portion of the substrate disposed on the dielectric runners;elevated memory cells disposed in the second substrate portion; andword lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective one of the rows.