Patent ID: 7930601
Filing Date: 2011-04-19
Classification: G11C

Abstract:
1. A method for implementing at speed bit fail mapping of a memory system embedded on a chip with Array Built In Self Testing (ABIST) system, comprising: testing said chip with an external tester comprising an off-chip device by applying an external clock operating at a first frequency to said chip; generating an internal high speed multiple of said external clock at said first frequency to sequence ABIST bit fail testing of said embedded memory system; detecting which cycle of said high speed multiplied clock corresponds to a fail occurring during ABIST testing of said memory system; performing a predetermined number of ABIST runs before issuing a bypass order substituting said external clock for said high speed multiplied clock; using said external clock of said external tester to read bit fail data out to said external tester storing a location of a said fail in a memory in said ATE tester upon recognition of said fail without requiring a scan operation off said chip to said ATE tester; applying an internal high speed clock to said ABIST system until a plurality of runs have been completed to store real time fail data; applying said external clock to said ABIST system after said plurality of runs; and then unloading real time fail data into said off-chip device.