Patent ID: 8988919
Filing Date: 2015-03-24
Classification: G11C,H01L,H03L

Abstract:
1. A method for synchronizing a plurality of stacked semiconductor devices interconnected by through electrodes, the method comprising: providing a clock signal on a first through electrode to each of the plurality of stacked semiconductor devices; providing a command/address signal on a second through electrode to each of the plurality of stacked semiconductor devices, whereby a selected one of the plurality of stacked semiconductor devices is selected; providing a delay clock signal on a third through electrode to each of the plurality of stacked semiconductor devices; receiving a feedback clock signal synchronized with the delay clock signal from the selected one of the plurality of stacked semiconductor devices on a fourth through electrode; adjusting the delay of the delay clock signal in accordance with a difference between a phase of the feedback clock signal and a phase of the clock signal; and receiving a data signal from the selected one of the plurality of stacked semiconductor devices in synchronization with the adjusted delay clock signal on a fifth through electrode.