Patent ID: 8274081
Filing Date: 2012-09-25
Classification: H01L

Abstract:
1. A semiconductor construction comprising: a semiconductor material base which comprises a projection between a pair of openings; the projection having an upper region over a lower region; the upper region being at least 75% amorphous, and the lower region being entirely crystalline; one or more dielectric materials within said openings to fill the openings; at least one transistor gate over the upper region of the projection; at least two source/drain regions that extend into the upper region of the projection, and that do not extend into the lower region of the projection; the source/drain regions extending only partially into the upper region of the projection to leave some of the upper region between bottoms of the source/drain regions and a top of the lower region; and wherein the upper region corresponds to less than or equal to about one-third of a total length of the projection.