Patent ID: 8824295
Filing Date: 2014-09-02
Classification: G06F,H04L

Abstract:
1. A system using a protocol for data transfer, the system comprising: a chip including a first register to send data through a link; and a connected chip including a second register to receive data through the link, wherein the link forms a transfer network, wherein the transfer network uses the protocol for data transfer, wherein the transfer network includes at least two virtual channels that share the link, wherein at least one virtual channel selected from the at least two virtual channels is a low-latency virtual channel, wherein the protocol for data transfer employs packet based data transfer using a common address space, wherein packets from the low-latency virtual channel complete on the link before other data is sent, wherein a higher priority packet can start being transmitted while a lower priority packet is already being transmitted if the lower priority packet is not on the low-latency virtual channel, wherein an availability of data reception capability in the connected chip is indicated to the chip as a credit token sent from the connected chip to the chip, and wherein packets from the low-latency virtual channel complete after other data when the low-latency channel has no credit token.