Patent ID: 6160287
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A flash memory, comprising:a substrate;an oxide layer, formed on the substrate;a gate, having a first side wall and a second side wall formed on the substrate, wherein the gate further comprises a first polysilicon layer on the oxide layer, a first inter-poly dielectric layer on the first polysilicon layer, and a second polysilicon layer on the first inter-poly dielectric layer;a second inter-poly dielectric layer, covering a part of top surface the gate and the first side wall of the gate;a spacer, covering the second inter-poly dielectric layer on the first side wall;a tunnel diffusion region, next to the second side wall in the substrate; andextending to a portion of the substrate under the gate;a doped region. next to the spacer in the substrate; anda select gate layer, covering the gate, the spacer, the tunnel oxide layer, and extending perpendicular to the second polysilicon layer.