Patent ID: 6060926
Filing Date: 2000-05-09
Classification: G01F,H03K

Abstract:
A low-power pulse conditioning circuit comprising:a. a first switch terminal having a first leg for electrical connection to a DC power source and a second leg;b. a second switch terminal having a first leg for electrical connection to ground and a second leg electrically coupled to said second leg of said first switch terminal; andc. a latch circuit having an output and an input electrically coupled to said second legs of said switch terminals;d. said latch circuit providing at said output a first logic state output when said input is provided with a high logic state and a second logic state output when said input is provided with a low logic state;e. a filter circuit in series between said input of said latch circuit and said second legs of said switch terminals; andf. wherein a switch closure at said first switch terminal following a switch closure at said second switch terminal provides said high logic state at said input of said latch circuit, a switch closure at said second switch terminal following a switch closure at said first switch terminal provides said low logic state at said input of said latch circuit, and consecutive switch closures at one said switch terminal without closure of the other said switch terminal will not result in a state change at said output of said latch.