Patent ID: 8582363
Filing Date: 2013-11-12
Classification: G11C

Abstract:
1. A NOR flash nonvolatile memory device comprises: at least one array block of NOR flash memory cells wherein the NOR flash memory cells are arranged in rows and columns, wherein the at least one block comprises a plurality of block sections of dual charge retaining transistor NOR flash cells and each of the dual charge retaining transistor NOR flash memory cells comprises at least two serially connected charge retaining transistors; a plurality of local bit lines connected such that a drain/source of a first of the at least two charge retaining transistors on each column of NOR flash memory cells is connected to one local bit line; a plurality of local source lines connected such that a source/drain of a second of the at least two charge retaining transistors on each column of NOR flash memory cells is connected to one local source line; a plurality of global bit lines connected such that at least one of the local bit lines is in communication with one global bit line; a plurality of bit line gating transistors, each bit line gating transistor connected between one local bit line and its associated global bit line; a plurality of global source lines connected such that at least one of the local source lines is in communication with one global source line; a plurality of source line gating transistors, each source line gating transistor connected between one local source line and its associated global source line; a plurality of word lines connected such that a control gate of each of the first charge retaining transistors on each row of NOR flash memory cells is connected to one word line and the control gates of the second charge retaining transistors on the row of NOR flash memory cells is connected to a separate word line; a row voltage control circuit connected to each word line connected to the control gates of each row of charge retaining transistors of the NOR flash memory cells; and a column voltage control circuit connected to each of the bit lines and source lines connected to the columns of the array of NOR flash memory cells; wherein the row voltage control circuit generates erase voltage signals for strongly and deeply erasing each block section of the array block for the correction of over-erasure such that a threshold voltage level of the dual charge retaining transistor NOR flash cells of a selected block section is less than the upper voltage limit of a first program state, generates over-erase verifying signals for verifying that each page of charge retaining transistors is then verified that the threshold voltage level of each charge retaining transistor is greater than a lower voltage limit of the first program state and generates program voltage signals for programming those charge retaining transistors that have their threshold voltage level less than the lower voltage limit of the first program state; wherein if any of the charge retaining transistors one selected page has their threshold voltage levels less than a lower voltage limit of the first program state, the row voltage control circuit and the column voltage repetitively generates programming voltage signals and over-erase verifying voltage signals until those charge retaining transistors of the one selected page have their threshold voltage levels greater than the lower voltage limit of the first program state; and wherein the row voltage control circuit selects one block section of a plurality of block sections of the block of dual charge retaining transistor NOR flash for erasing and verifying followed the another of the block sections with each block section being sequentially erased and verified.