Patent ID: 7468283
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method for fabricating test structures on a wafer for integrated circuits, the method comprising: providing a semiconductor substrate; forming a plurality of integrated circuit chip structures on the semiconductor substrate; forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures; and forming a first contact structure and a second contact structure, the second contact structure being adjacent to the first contact structure, the first contact structure being coupled to a first MOS device in the plurality of MOS devices and the second contact structure being coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1, and wherein at least two or more of the MOS devices are formed between the first contact structure and the second contact structure.