Patent ID: 6964903
Filing Date: 2005-11-15
Classification: H01L,H03D

Abstract:
1. A method of fabricating a transistor on a substrate, the method comprising: forming a first source/drain region on the substrate; vertically forming a body region on the first source/drain region as a fully depleted structure, forming a second source/drain region on the body region to form a column on the substrate, the body region having opposing sidewall surfaces on the column; forming a first gate on a first one of the opposing sidewall surfaces after forming the column, the first gate separated from the first one of the opposing sidewall surfaces by a first oxide layer; and forming a second gate on a second one of the opposing sidewall surfaces after forming the column, the second gate separated from the second one of the opposing sidewall surfaces by a second oxide layer, wherein vertically forming the body region includes vertically growing an epitaxial layer such that the body region is formed having a width and a doping concentration such that a threshold voltage is substantially independent of bulk charge in the body region in transistor operation.