Patent ID: 6597229
Filing Date: 2003-07-22
Classification: H03K,H04L

Abstract:
An interface circuit comprising:a signal sending means having a first switching means and a second switching means which are alternately turned ON in accordance with a binary input signal, said signal sending means located on a first integrated circuit; a first transmission path and a second transmission path connecting said first integrated circuit to a second integrated circuit; and a signal receiving means located on said second integrated circuit, said signal receiving means having a first current supplying means connected through said first signal transmission path to said first switching means and operated to feed a current with a predetermined value from said first current supplying means through said first signal transmission path when said first switching means is turned ON and a second current supplying means connected through said second transmission path to said second switching means and operated to feed a current with a predetermined value from said second current supplying means through said second transmission path when said second switching means is turned ON, whereby said signal receiving means detects a change in voltages generated depending on availability of current supply at said first current supplying means or said second current supplying means and outputs it in the form of a binary output signal, wherein said first current supplying means and said second current supplying means comprise elements of a current mirror of said signal receiving means.