Patent ID: 6519202
Filing Date: 2003-02-11
Classification: G11C

Abstract:
An apparatus, comprising:a plurality of input-output circuits that include one or more redundant input-output circuits and one or more non-redundant input-output circuits, the one or more redundant input-output circuits include a first redundant input-output circuit, the one or more non-redundant input-output circuits include a second non-redundant input-output circuit, each non-redundant input-output circuit contains a plurality of sub input-output circuits; a first group of redundant memory columns couples to the first redundant input-output circuit; a second group of non-redundant memory columns couples to the second non-redundant input-output circuit, a fewer amount of memory columns exist in the first group of redundant memory columns than in the second group of non-redundant memory columns; a first fuse coupled to the second non-redundant input-output circuit, the first fuse to indicate whether one or more memory columns are defective in the second group of non-redundant memory columns; and a second sub input-output select fuse coupled to a first circuit, the first circuit to identify which sub-input-output circuit is coupled to the one or more defective memory columns.