Patent ID: 6832117
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A processor, comprising:a processor core for executing an instruction in a pipeline processing; a data memory accessed by said processor core; and an extended arithmetic unit, connected to an exterior of said processor core, for processing an extended instruction decoded in said processor core in the pipeline processing, said extended arithmetic unit executing an arithmetic operation by using arithmetic operation data retained in a register file in said processor core, and outputting a result of an arithmetic operation directly to a pipeline stage processing after an executing stage processing in said processor core, said processor core receiving the result of the arithmetic operation executed by said extended arithmetic unit and inputted therefrom into said register file in said processor core, wherein said processor core includes a pipeline controller for flushing or stopping the pipeline processing in said extended arithmetic unit, and said extended arithmetic unit further comprising a first stage arithmetic circuit, a second stage arithmetic circuit, and a memory access controller configured to control direct access of said data memory by the extended arithmetic unit after an execution of the arithmetic operation by said first stage arithmetic circuit, and to provide said second stage arithmetic circuit with read out data from said data memory as input data for succeeding pipeline processing.