Patent ID: 8772056
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A method, comprising: providing a semiconductor substrate; forming a first plurality of shallow trench isolation (STI) features within a device region of the semiconductor substrate, wherein the first plurality of STI features define a plurality of active regions each having a first geometry with a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction; and forming a second plurality of STI features within a dummy region of the semiconductor substrate, wherein the dummy region is adjacent the device region and the second plurality of STI features define a plurality of dummy active regions each having a second geometry with a third dimension in the first direction and a fourth dimension in the second direction, wherein the plurality of dummy active regions are all aligned with the plurality of active regions; and wherein the first dimension of each of the active regions is parallel to the third dimension of each of the dummy active regions.