Patent ID: 7566624
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A method for producing a transistor structure with a lightly doped drain (LDD), the method comprising: structuring a gate electrode on a gate dielectric, the gate dielectric being on a substantially planar upper surface of a semiconductor body or substrate; etching the semiconductor body or substrate to form sloping sidewalls on regions adjacent to the gate electrode, the sloping sidewalls sloping downward from the gate electrode; depositing a spacer layer over at least part of the sloping sidewalls and the gate electrode; anisotropically back-etching the spacer layer to form spacers, the spacers at least partially covering source-side and drain-side sidewalls of the gate electrode and the sloping sidewalls; using the gate electrode as a mask, implanting dopant in the semiconductor body or substrate to form a source region, a drain region, and regions of lower dopant concentration, the regions of lower dopant concentration being adjacent to the source and drain regions and adjacent to a channel between the source and drain regions; wherein implanting dopant is performed at a first angle relative to the upper surface of the semiconductor body or substrate to form the source and drain regions, wherein implanting dopant at a first angle is performed after formation of the spacers; and wherein implanting dopant is performed at a second angle relative to the upper surface of the semiconductor body or substrate, and through the spacers, to form the regions of lower dopant concentration, the first angle being greater than the second angle.