Patent ID: 7649558
Filing Date: 2010-01-19
Classification: H04N

Abstract:
1. An integrated circuit comprising: a plurality of first sets of pixels, each first set comprising a plurality of subsets of pixels; a plurality of first circuits each coupled to an output from a respective subset; a plurality of second circuits, each of which is coupled to outputs from the first circuits associated with a respective one of the first sets; a first bus for each first set coupled to the outputs of the associated first circuits, each first circuit configured to selectively connect the respective subset to a respective first bus; a second bus for receiving signals from each of the sets, each second circuit configured to selectively connect the respective set to the respective second bus; a readout circuit for receiving signals from the first and second buses; and a third circuit coupled to each first bus for selectively isolating each first set from the readout circuit, the third circuit comprising a first switch for selectively connecting the first bus to a predetermined voltage.