Patent ID: 8239429
Filing Date: 2012-08-07
Classification: H03K

Abstract:
1. Output buffer into which first and second input signals are applied and that delivers an output signal, said output signal being switchable between a high logical level and a low logical level, and vice versa, said buffer comprising a first switching stage comprising: first high switching means to switch said output signal from said low logical level to said high logical level; first low switching means to switch said output signal from said high logical level to said low logical level; first high and low control means acting on said first high and low switching means respectively, said first high and low control means receiving said first and second input signals, respectively; first high and low memory points, the output from the first high control means and the input to said first high switching means being connected to the first high memory point, the first high memory point further connected to the first low control means and to a second high control means, the output from the first low control means and the input to said first low switching means being connected to the first low memory point, the first low memory point further connected to the first high control means and to a second low control means; wherein said buffer comprises a second offset switching stage installed in cascade downstream from said first switching stage and comprising: second high switching means of said output signal; second low switching means of said output signal; and second high and low control means acting on said second high and low switching means respectively, through upstream high and low control points respectively, said second high and low control means receiving said first and second input signals respectively, said upstream high and low control points being delayed in time with respect to said high and low memory points, respectively and wherein the second high control means includes an inverter that includes an input connected to the first input signal and an output connected to the second high switching means and is connected to a power supply and the first high memory point; and wherein the second high control means is connected to the second high switching means.