Patent ID: 6093604
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of manufacturing a flash memory device comprising the steps of:forming a first insulating layer on a substrate of a first conductivity type;forming a second insulating layer on said first insulating layer;patterning said second insulating layer to form two open regions spaced apart from each other on said substrate;implanting an impurity in said substrate through said open regions to thereby form source and drain regions of a second conductivity type in said substrate;selectively removing said first insulating layer to expose said source and drain regions formed in said substrate;forming a first semiconductor layer of the second conductivity type in contact with said source and drain regions, on the surface of said remaining first and second insulating layers and in said open regions;patterning said first semiconductor layer to form source and drain electrodes of a T-shaped rail structure, and removing said remaining second insulating layer;forming a third insulating layer on exposed portions of the source and drain electrodes and the remaining first insulating layer including said source and drain electrodes;forming a second semiconductor layer of the second conductivity type on said third insulating layer;patterning said second semiconductor layer such that a floating gate of an I-shaped rail structure overlaps said source and drain electrodes;forming a fourth insulating layer on exposed portions of the second semiconductor layer and third insulating layer including said floating gate; andforming and patterning a third semiconductor layer on said fourth insulating layer to form a control gate.