Patent ID: 6879540
Filing Date: 2005-04-12
Classification: G11C

Abstract:
1. A synchronous semiconductor memory device comprising: a memory cell array having dynamic memory cells arranged in a matrix form; and a command decoder configured to decode a plurality of commands in synchronism with an external clock signal, the plurality of commands being set by combinations of logical levels of a plurality of control pins at input timing of a first command and at input timing of a second command one cycle after the input timing of the first command, the plurality of control pins including a chip select pin, a function pin and a power down pin, the command decoder including: a first decode section which determines a read operation; a second decode section which determines a write operation; and a third decode section which determines an auto-refresh operation, wherein setting of an auto-refresh command is performed at the input timing of the first command and determined only by a combination of the logical levels of the chip select pin, the function pin and the power down pin at the input timing of the first command.