Patent ID: 6589713
Filing Date: 2003-07-08
Classification: G03F,Y10S

Abstract:
A method of fabricating reduced pitch in an integrated circuit, the integrated circuit including a patterned photoresist layer, the patterned photoresist layer being patterned in accordance with a pattern on a mask or reticle and exposure to a first radiation at a lithographic wavelength, the method comprising the steps of:providing a second radiation to at least one area of the patterned photoresist layer, the patterned photoresist layer including a developed exposed area, the developed exposed area including sidewalls and a bottom; transforming the sidewalls of the developed exposed area to change a width of the developed exposed area in response to the second radiation; and positioning the pattern on the mask or reticle relative to the patterned photoresist layer so that the pattern on the mask or reticle is not aligned with the patterned photoresist layer.