Patent ID: 6684319
Filing Date: 2004-01-27
Classification: G06F

Abstract:
A very long instruction word processing system, including a memory unit, a decoder unit, and an instruction register, wherein said system minimizes power consumption and processing time, said system comprising:a prefetch instruction buffer, wherein said prefetch instruction buffer stores a plurality of prefetch instructions received from the memory unit; a prefetch instruction flag bit, wherein said prefetch instruction flag bit is decoded by the decoder unit and said prefetch instruction flag bit indicates that said prefetch instructions are to be placed into said buffer; a prefetch instruction control unit, wherein said control unit receives said prefetch instruction flag bit from the decoder unit and wherein said control unit facilitates the placement of said prefetch instructions into said buffer; and a multiplexer, wherein said multiplexer receives a select input flag bit and said multiplexer outputs a plurality of instructions to the instruction register based on said select input flag bit.