Patent ID: 8300484
Filing Date: 2012-10-30
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array including a plurality of memory cells storing data; a first bit line transmitting data stored in a selected one of the memory cells; a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current; a second bit line selectively connected to the first bit line via the first sense amplifier; a second sense amplifier determining a level of the signal voltage of the second bit line; and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of either or both of the first and second sense amplifiers in accordance with a detection result of the temperature, wherein the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.