Patent ID: 7355534
Filing Date: 2008-04-08
Classification: G09G,H03M

Abstract:
1. A serial-to-parallel conversion circuit comprising: a clock generator for generating first to i-th clock signals; and first to i-th stage circuits, wherein the first to i-th stage circuits convert digital data inputted serially at x Hz into 2 wherein the j-th clock signals are inputted to the j-th stage circuit, wherein the k-th stage circuit comprises first to fifth D-latch circuits each of which comprising a clocked inverter, wherein the first and second D-latch circuits are connected in series between an input terminal of the k-th stage circuit and a first output terminal of the k-th stage circuit, wherein the third to fifth D-latch circuits are connected in series between the input terminal of the k-th stage circuit and a second output terminal of the k-th stage circuit, wherein the second, third and fifth D-latch circuits latch an input signal of the k-th stage circuit when the k-th clock signal is high, wherein the first and fourth D-latch circuits latch the input signal of the k-th stage circuit when the k-th clock signal is low, wherein letter i denotes a natural number, wherein letter j denotes a natural number no more than i, wherein letter k denotes a natural number no more than i and not equal to j, and wherein letter x denotes a positive number.