Patent ID: 6372525
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of forming an EEPROM plasma damage test structure comprising:(a) providing a silicon wafer with a region of a first conductivity type; (b) forming a field oxide on said wafer with regions of active silicon exposed in a first opening, a second opening, and a third opening in said field oxide; (c) implanting ions of a second conductivity type into said first opening and said second opening while masking said third opening, thereby forming a first conductive region in said first opening and control gate region in said second opening; (d) forming a gate oxide in each of said openings by thermal oxidation; (e) masking said gate oxide to define a tunnel oxide window in said first opening and etching said gate oxide in said window; (f) forming a tunnel oxide in said window; (g) depositing a polysilicon gate stack layer over said wafer; (h) patterning said gate stack layer to form a floating polysilicon gate which bridges over said respective gate oxide in said third opening, extending in one direction, passing over a first region of said field oxide and terminating in a first pad over and completely covering said tunnel oxide window and extending in another direction, passing over a second portion of said field oxide and terminating in a second pad which partially covers said respective gate oxide in said second opening; (i) forming source/drain elements, aligned to said floating polysilicon gate in said third opening by implanting ions of said second conductivity type into said wafer thereby forming a MOSFET in said third opening; (j) depositing an interlevel dielectric layer on said wafer; (k) planarizing said interlevel dielectric layer; (l) forming a plurality of conductive contacts through contact openings in said interlevel dielectric layer connecting to said first conductive region, said control gate, and said source/drain elements; (m) patterning a metal layer over said interlevel dielectric layer to form an antenna connected by wiring to respective said contacts which, in turn, connect to said first conductive region, two probe pads, each one connected by wiring to respective said contacts which, in turn connect to said source and said drain elements, and a third probe pad connected by wiring to respective said contacts which, in turn, connect to said control gate; (n) depositing an insulative layer over said wafer; and (o) patterning an opening in said insulative layer to expose said antenna.