Patent ID: 6140839
Filing Date: 2000-10-31
Classification: H03K

Abstract:
A field programmable architecture for compute-intensive applications, comprising:a section level interconnect channel;a first logic cluster for implementing control logic, comprising a plurality of logic blocks interconnected by a local interconnect channel that is in communication with said section level interconnect channel; anda second logic cluster for implementing data path operations, comprising a plurality of programable logic blocks interconnected by a cluster level interconnect channel that is in communication with said section level interconnect channel,said programable logic blocks each configured to perform operations on two N-bit operands and comprising:(a) a stack of N bit-slice logic elements each having two data bit inputs, a data bit output a multiply bit input, a carry-in bit input a carry-out bit output a programable operation select circuit for processing inputs received by said two data bit inputs and said multiply bit input, and a 1-bit full adder circuit for generating a sum-bit output and said carry-bit output in response to information received from said operation select circuit and said carry-in bit input the carry-in bit input of each successive bit slice logic element being connected to the carry-out bit output of the preceding bit-slice logic element; and(b) control means for programming the operation select circuits of each of said bit slice logic elements in order to selectively configure said programmable logic block to implement one of a ripple carry adder subtracter and partial multiplier,said programable logic blocks of said second logic cluster having a different configuration than the logic blocks of said first logic cluster such that said programable logic blocks provide a more area-efficient realization of adders, subtracters and partial multipliers than the logic blocks of said first logic cluster.