Patent ID: 6441487
Filing Date: 2002-08-27
Classification: G06F,H01L

Abstract:
A chip scale package comprising in combination:a. an integrated circuit formed upon a semiconductor die, said semiconductor die having a front surface and an opposing rear surface, said semiconductor die including a plurality of conductive bond pads formed upon the front surface thereof for making electrical interconnections to said integrated circuit; b. a patterned metal layer formed over the front surface of said semiconductor die, said patterned metal layer providing a plurality of solder bump pads upon the front surface of said semiconductor die, and said patterned metal layer electrically coupling said conductive bond pads to said plurality of solder bump pads each of said solder bump pads having a predetermined solder bump pad diameter; c. a plurality of ductile solder balls, each of said ductile solder balls being secured to a corresponding one of said solder bump pads, each of said ductile solder balls having a generally flattened spherical shape after being secured to its respective solder bump pad each of said ductile solder balls extending above its respective solder bump pad by a predetermined height after being secured thereto, and each of said ductile solder balls having a predetermined diameter measuring at least 9 mils (0.009 inch), said predetermined height of each of aid ductile solder balls being substantially 70% or more of said predetermined solder bump pad diameter.