Patent ID: 6091705
Filing Date: 2000-07-18
Classification: G01R,H04J,H04L

Abstract:
A method for implementing a system interconnect for transporting a first cell containing a plurality of data between a plurality of nodes wherein said system interconnect includes: a first unidirectional path between each pair of adjacent nodes of said plurality of nodes, said first unidirectional path includes an incoming end and an outgoing end and a first plurality of signal lines and a frequency reference line, said pair of adjacent nodes having a source node and a receiver node, each of said plurality of nodes includes an input section connected to said incoming end of an input path, and an output section connected to said outgoing end of an output path, said method comprising steps of:(a) providing a frequency reference signal on said frequency reference line to said plurality of nodes;(b) generating, by a phase lock loop frequency multiplier, a node clock based on said frequency reference signal, said node clock having the same frequency for each of said plurality of nodes, said source node having a source node clock and said receiver node having a receiver node clock;(c) transmitting said first cell from said output section of said source node to said input section of said receiver node over said first unidirectional path, by emitting a plurality of data transitions representing said first cell, onto said first plurality of signal lines at said outgoing end of said first unidirectional path; and(d) receiving said data transitions from said first plurality of signal lines at said incoming end of said first unidirectional path at said input section of said receiver node.