Patent ID: 6369624
Filing Date: 2002-04-09
Classification: H03K,H03L

Abstract:
A circuit comprising:a phase detector circuit receiving a reference clock signal; a charge pump circuit coupled to the phase detector circuit; a voltage controlled oscillator coupled to the charge pump, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs; and a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a first clock output, wherein the voltage controlled oscillator output comprises a plurality of delay stages, a delay stage comprising: a second multiplexer having inputs coupled to a first of the voltage controlled oscillator outputs, and a second of the voltage controlled oscillator outputs; a first buffer coupled between the second multiplexer and a third of the voltage controlled oscillator outputs; a third multiplexer having inputs coupled to the third of the voltage controlled oscillator outputs and a fourth of the voltage controlled oscillator outputs; and a second buffer coupled between the third multiplexer and the second of the voltage controlled oscillator outputs.