Patent ID: 8230206
Filing Date: 2012-07-24
Classification: G06F

Abstract:
1. A computer system, comprising: a triggering device; and a motherboard, connected to the triggering device, further comprising: wherein an erasing signal, for erasing the memory, is outputted to the memory from the counter according to a triggering signal outputted from the triggering device while a boosting procedure cannot be successfully executed, wherein the counter further comprises N numbers of D-Type Flip Flops coupled in series, wherein a signal with a first level is outputted to a signal-input terminal of a first-stage D-Type Flip Flop from a voltage-power source, each signal-input terminal of a second-stage to a Nth-stage D-Type Flip Flop is connected to a signal-output terminal of the prior stage D-Type Flip Flop, the triggering signal is transmitted to clock terminals of the N numbers of D-Type Flip Flops from the triggering device, and the erasing signal is outputted from a complementary-signal-output terminal of the Nth-stage D-Type Flip Flop.