Patent ID: 6954820
Filing Date: 2005-10-11
Classification: G06F

Abstract:
1. A bus bridge that is connected to a first bus and a second bus different from the first bus, and relays data between a first device connected to the first bus and a second device connected to the second bus, comprising: an externally-writable memory including primary memory areas corresponding to the first and second buses; registering means for registering relay information, showing an amount of data to be relayed from a target to a master, in a primary memory area corresponding to one of the first and second buses to which the target is connected, the target being one of the first and second devices that is a data source whereas the master being a different one of the first and second devices that is a data destination; storing means for storing data read from the target into a temporary storage; and master functioning means corresponding to the first and second buses, wherein master functioning means corresponding to the bus to which the target is connected (a) reads data from the target while occupying the bus until an amount of data stored in the temporary storage reaches the amount shown by the relay information in the primary memory area, and (b) releases the bus once the amount of data in the temporary storage has reached the amount shown by the relay information; wherein the relay information shows one out of (a) a number of sets of data to be relayed, each set of data having a bit length equivalent to a width of the bus, and (b) a total size of data to be relayed.