Patent ID: 6624488
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A MOSFET device, comprising:a silicon substrate having a flat top surface and having source/drain regions and a channel region between said source/drain regions, wherein said source/drain regions and said channel region are formed under said top surface of said substrate; a gate stack; a gate insulator layer between the substrate and the gate stack; and an epitaxial silicon layer between the gate insulator layer and the substrate, wherein said gate insulator layer is formed of a high-k insulator comprising titanium oxide (TiO2) and in direct contact with said epitaxial silicon layer, and wherein said epitaxial silicon layer is formed on and in direct contact with said top surface of said substrate after forming said source/drain regions, and said epitaxial silicon layer has a thickness of from 20 Angstroms to 30 nanometers and is patterned to have a substantially same width as that of said gate stack and said gate insulator layer in a gate length direction.