Patent ID: 6316298
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A fabrication method for a flash memory device comprising the steps of:providing a substrate with a plurality of gate structures wherein each gate structure comprises a gate oxide layer, a floating gate is positioned on the gate oxide layer with a cap layer on the floating gate, and a spacer is located on sidewalls of the cap layer, the floating gate and the gate oxide layer;forming a patterned photoresist on the substrate;forming a trench in the substrate on one side of the gate structure using the photoresist, the cap layer and the spacer as masks, wherein the trench is formed in every other space between the gate structures;removing the patterned photoresist;conducting a self-aligned oxidation process to form a first dielectric layer on the substrate;forming a source region in the substrate under a part of the first dielectric layer at a bottom of the trench;conducting a threshold voltage adjustment implantation;removing the cap layer, the spacer and the first dielectric layer;forming a conformal second dielectric layer on the substrate;forming a conductive layer on the substrate;defining the conductive layer, the second dielectric layer and the floating gate to convert the conductive layer into a control gate; andforming a third dielectric layer on sidewalls of the control gate, the second dielectric layer and the floating gate.