Patent ID: 6373105
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A latch-up protection circuit integrated with a CMOS circuitry on a semiconductor substrate, the CMOS circuitry being powered by a first voltage and a second voltage via a first power rail and a second power rail, respectively, where full levels at the first power rail and the second power rail ensure that no latch-up triggering path exists in the CMOS circuitry during steady state; the latch-up protection circuit comprising:a well of a first conductivity type formed in the semiconductor substrate to establish a junction therebetween; a first diffusion region of the first conductivity type formed in the well and connected to the first power rail; a second diffusion region of a second conductivity type formed in the well and connected to the second power rail, the second diffusion region being spaced from the junction by a first spacing; and a third diffusion region of the second conductivity type formed in the well and connected to a third power rail, the third diffusion region being spaced from the second diffusion region by a second spacing smaller than the first spacing; wherein a current is generated between the second diffusion region and the third diffusion region to reduce a potential difference between the first power rail and the second power rail when the first power rail has a temporary potential within those of the second power rail and the third power rail during a power-on sequence.