Patent ID: 7600143
Filing Date: 2009-10-06
Classification: G06F

Abstract:
1. A method of data transfer using programmable delay, comprising: providing a plurality of alternative data paths, each of the data paths being programmably selectable based on a state of one or more control signals, and each of the data paths providing a different data transfer delay to reach an output register; receiving a data block at a first instant in time within a first master clock cycle; determining one of a plurality of master clock cycles to be used as a second master clock cycle; programmably selecting one of the alternative data paths based on the state of the one or more control signals to utilize its corresponding data transfer delay in providing the data block to the output register to accommodate a data storage mechanism between an external cache and a front side bus, wherein at least one of the data transfer delays comprises an amount of time greater than the first master clock cycle; and transmitting the received data block from the output register at a second instant in time within the second master clock cycle.