Patent ID: 7262990
Filing Date: 2007-08-28
Classification: G11C

Abstract:
1. A semiconductor memory device including phase-change cells whose states change to a reset resistance state or a set resistance state in response to an applied current pulse, comprising: a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein a minimum current amount of the first through n-th stages is larger than a reference current amount and current amounts of the first through n-th stages are sequentially reduced; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.