Patent ID: 7851827
Filing Date: 2010-12-14
Classification: B82Y,G11C,H01L

Abstract:
1. A back-side trap non-volatile memory cell, comprising: a channel region; an access gate insulator formed over the channel region; an access gate formed over the access gate insulator; a trap material; a charge blocking material formed beneath the trap material; a back-side gate formed beneath the charge blocking material; and one or more sub-layers of dielectric material formed over the trap material and beneath the channel region; wherein a conduction band offset of at least one of the one or more sub-layers of dielectric material is less than a conduction band offset of the trap material; and wherein a conduction band offset of any one of the one or more sub-layers of dielectric material is less than a conduction band offset of any other sub-layer of dielectric material located between that one sub-layer of dielectric material and the trap material.