Patent ID: 8450175
Filing Date: 2013-05-28
Classification: H01L

Abstract:
1. A method of forming a vertical transistor and at least a conductive line electrically coupled therewith, comprising: forming trenches in semiconductive material, the semiconductive material between the trenches comprising an elevationally outer source/drain portion and an elevationally mid-channel portion there-below; forming masking material across bases of the trenches; ion implanting conductivity modifying impurity through the masking material received over the trench bases and through the trench bases into semiconductive material there-below, and providing the impurity into semiconductive material received between the trenches below the mid-channel portion and forming an elevationally inner source/drain below the mid-channel portion, the inner source/drain comprising said semiconductive material between the trenches which has the impurity therein; forming a conductive line laterally over and electrically coupled to at least one of opposing sides of the inner source/drain; and forming a gate elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion, a gate dielectric being provided laterally between the gate and the mid-channel portion.