Patent ID: 6611920
Filing Date: 2003-08-26
Classification: G06F,Y02D

Abstract:
A power control system for an integrated circuit, comprising:a global clock generator, a clock distribution network in communication with the global clock generator, a plurality of functional unit blocks each in communication with the global clock generator, and a hierarchical power control system comprising: first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block, wherein at least one of the first or second power controllers comprises: an OR gate having inputs for an enable signal and an override signal, a NAND gate having inputs for a clock signal and for an output of the OR gate, an inverter having an input for the override signal, an AND gate having an input for a disable signal and an output of the inverter, and a NOR gate having inputs for an output of the AND gate and an output for the NAND gate.