Patent ID: 7256636
Filing Date: 2007-08-14
Classification: H03L

Abstract:
1. A voltage controlled delay line (VCDL) comprising: a plurality of cells, wherein each of the plurality of cells includes two or more inputs and an output, and wherein each of the plurality of cells is configured to provide a delay, and is further configured to operate in one of a first mode providing an interpolation function or a second mode providing a multiplexer function; wherein, when providing the multiplexer function, one of the two or more inputs is selected such that it is operatively coupled to the output; wherein, when providing the interpolation function, two of the two or more inputs are selected such that each of the selected two inputs is operatively coupled to the output; and wherein the VCDL further includes two or more selection circuits, wherein each of the two or more selection circuits is associated with a corresponding one of the two or more inputs, and wherein each selection circuit is configured to, when enabled, operatively couples its corresponding input to the output.