Patent ID: 6363511
Filing Date: 2002-03-26
Classification: G11B,H03M

Abstract:
A device for detecting and correcting errors in error correction coded (ECC) data blocks, each ECC data block comprising a plurality of columns and rows, the ECC data blocks being read from a storage medium sequentially in rows, the device comprising:on-the-fly row correcting circuitry configured to sequentially receive the rows of an ECC data block for detecting errors in each of the received rows and for correcting up to a first predetermined number of the errors in each of the received rows; column correction circuitry coupled to the row correction circuitry to sequentially receive the row error corrected rows of the ECC data block for detected uncorrected errors, wherein the column correction circuitry is configured to correct uncorrected errors remaining in the columns of the ECC data block after the up to a first predetermined number of errors in each row have been corrected; and repeat correction circuitry coupled to the column correction circuitry for detecting and correcting remaining uncorrected errors in the ECC data block after on-the-fly row correction and column correction.