Patent ID: 6750513
Filing Date: 2004-06-15
Classification: G09G,H01L,H04M

Abstract:
A PDP (Plane Display Panel) driver IC incorporating at least one semiconductor device comprising an N-channel insulated-gate field-effect transistor on an SOI (Silicon On Insulator) substrate having an N-type device-deforming region, the N-channel insulated-gate field-effect transistor including high concentration N-type and P-type layers both in contact with a source electrode, a gate insulating film/gate electrode in contact with the high concentration N-type layer, a high concentration N-type layer in contact with a drain electrode disposed in a lateral direction via a field oxide film contacting the gate electrode, and a p-type semiconductor layer (p-body layer) contacting the gate oxide film and the high concentration N-type and P-type layers both in contact with the source electrode,wherein, when a distance from an end of the field oxide film contacting the high concentration N-type layer in contact with the drain electrode to ends of the gate electrode and the gate oxide film both in contact with the high concentration N-type layer contacting the source electrode is defined as a source-drain distance, the N-channel insulated-gate field-effect transistor further comprises; an N-type layer having a concentration higher than a concentration of an N-type layer in contact with the p-body layer, formed in a region covering at most 95% of the source-drain distance between the p-body layer and the drain electrode in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.