Patent ID: 6566213
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:forming a gate defining a channel interposed between a source and a drain formed within an active layer of a semiconductor substrate wherein the source includes a main source region and a source extension region and the drain includes a main drain region and a drain extension region; forming a spacer on a sidewall of the gate; and forming a multi-thickness silicide layer on the source and the drain, the multi-thickness silicide layer comprising a first portion formed on the main source region and the main drain region and a second portion formed on the source extension region and the drain extension region by selectively etching the spacer, wherein the second portion of the multi-thickness silicide layer formed on the source extension region and the drain extension region is thinner than the first portion of the multi-thickness silicide layer formed on the main source region and the main drain region.