Patent ID: 8312404
Filing Date: 2012-11-13
Classification: G06F,H01L

Abstract:
1. A method of modeling bond wires and corresponding pads in an integrated circuit (IC) package design for predicting noise effects of the bond wires and the corresponding pads in IC signal transmission paths, the method comprising: a) using a computer, setting parameters related to an IC package layout geometry of a group of bond wires and their corresponding pads; b) sub-dividing said group of bond wires and their corresponding pads into regions, each region including a portion of each bond wire or its corresponding pad, and generating dissection planes for said regions comprising said bond wires according to wire loop type, curvature of wires, landing locations of wires and existence of power and ground planes, dissecting a vertical region by horizontal dissection planes at flat tops of said bond wires, and dissecting a horizontal dissection region by unevenly spaced vertical planes; c) performing with a computer 3D simulations on said regions comprising said corresponding pads, and a 2D simulation for each dissection plane; d) constructing equivalent circuit models for said group of bond wires and their corresponding pads based on results from said 3D and 2D simulations; and e) inputting said equivalent circuit models into a circuit simulator, and modifying said layout to meet noise targets.