Patent ID: 6337816
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A column redundancy circuit for a semiconductor memory, comprising:a memory array including a plurality of array units respectively having a plurality of normal memory cells and a plurality of redundancy memory cells, each array unit outputting a normal data stored in the normal memory cell, and outputting a redundancy data stored in the redundancy memory cell; a column redundancy unit for outputting a redundancy enable signal according to a column address, a row address and a fuse short state, said column redundancy unit including a plurality of enable units for respectively outputting a column address true signal or a column address bar signal according to the row address and the fuse state; and a switch unit for selecting one of the normal data and the redundancy data from the memory array according to a logical state of the redundancy enable signal, and for outputting the selected data to a main amplifier, wherein each enable unit includes a switching transistor being switched according to the row address; a first transmission gate for outputting the column address true signal according to an ON/OFF state of the switching transistor; and a second transmission gate for outputting the column address bar signal according to the ON/OFF state of the switching transistor, the first and second transmission gates having a complementary relationship.