Patent ID: 7383468
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. An apparatus comprising: an error detection component to control the detection of errors in information stored in a processor resource between stores of new information in the processor resource; and a comparison component coupled to the error detection component, the comparison component to receive the information from the processor resource, to determine whether the information is valid, and to output a signal to indicate an error condition if the information is invalid, wherein the processor resource is selected from the group consisting of a cache, at least one translation lookaside buffer (TLB), at least one region identification (RID), at least one protection key register, at least one model specific register (MSR), a control register access bus (CRAB) including at least one MSR coupled to the CRAB, a CRAB coupled to at least one other CRAB, and a TLB coupled to a MSR which is coupled to a CRAB.