Patent ID: 7030440
Filing Date: 2006-04-18
Classification: H01L

Abstract:
1. A DRAM array comprising: a substrate; a double well, comprising a shallow well of a first dopant type substantially contained within a deeper well of a second dopant type, formed within the substrate; at least two adjacent DRAM memory cells disposed on the substrate within said double well, the memory cells being electrically isolated from each other by a shallow isolation trench and each said memory cell including an access transistor and a storage capacitor electrically connected by a conducting channel to the access transistor, wherein the access transistor has a top surface with a height to the substrate corresponding to a height of a top surface of the storage capacitor, and the storage capacitor including; a capacitor trench having a base and side walls disposed within the double well, the base of said trench and a portion of its sidewalls extending to the deeper well of said double well wherein it forms a top plate of a storage capacitor; a capacitor dielectric disposed over a substantial portion of the sidewall of said trench, a remaining portion of the sidewalls contained within the upper well being exposed; a conducting layer disposed within and over said trench and conformally covering said capacitor dielectric and said exposed portion of the sidewalls, said conducting layer forming a bottom plate of said storage capacitor.