Patent ID: 8392660
Filing Date: 2013-03-05
Classification: G06F

Abstract:
1. A cache system, comprising: a plurality of processing units operative to access a main memory device or lower-level cache; a plurality of caches coupled in one-to-one correspondence to the processing units; and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory or the lower-level cache and the caches, wherein the controller includes: wherein when a first cache, corresponding to a first processing unit of the plurality of units which sends an address to the controller, does not include a first entry which is least recently used among the plurality of caches, the logic circuit transfers a second entry which is least recently used in the first cache to a second cache which includes an entry that is least recently used among the plurality of caches, the second cache corresponding to a second processing unit of the plurality of the processing units, and wherein the first information includes for each of the caches: