Patent ID: 7219272
Filing Date: 2007-05-15
Classification: G06F,G11C

Abstract:
1. A semiconductor device, comprising: an SRAM memory which stores data and parity bits, wherein the SRAM memory comprises local bus; a global bus; an error correction circuit; a write data generation circuit; and a parity bit generation circuit which generates the parity bits for predetermined bits of the data; wherein the latch type sense amplifier, the write amplifier circuit and some of the SRAM memory cells are each connected between said pairs of data lines, further wherein each of the latch type sense amplifiers reads the data and the parity bits from the SRAM cells, holds the data and outputs to the local bus, further wherein the error correction circuit reads the data and parity bits from the local bus, corrects the data with the parity bits and outputs the corrected data to the write data generation circuit. further wherein the write data generation circuit replaces a part of the corrected data with write data input from the global bus and outputs the replaced data back to the local bus, further wherein the parity bit generation circuit generates new parity bits based on the replaced data and outputs new parity bits to the local bus, and further wherein the write amplifier circuits inputs only a part of the replaced data from the local bus, which is different between the replaced data and the data held in the latch type sense amplifier, into the data lines.