Patent ID: 6950908
Filing Date: 2005-09-27
Classification: G06F

Abstract:
1. A cache memory control method in a multiprocessor system, formed by a plurality of processors respectively having cache memories, for executing a plurality of threads whose execution sequence is defined, the method comprising: executing a first thread by a first processor of said processors; executing a second thread by a second processor of said processors; and executing a third thread by a third processor of said processors, wherein, when said first processor executing said first thread writes data, said first processor writes said data in said cache memory of said first processor; when there is a cache line corresponding to a writing target address of said data, in said cache memory of said second processor executing said second thread positioned posterior to said first thread in the execution sequence, said first processor updates said cache memory of said second processor; and when there is a cache line corresponding to the writing target address of said data, in said cache memory of said third processor executing said third thread prior to said first thread in the execution sequence, said first processor records in said cache memory of said third processor that said first processor executing said first thread has written data into the cache line of said first processor, and wherein, when the data written into the cache line by said first processor is based on speculative processing, when said third processor executing said third thread retrieves data from said cache memory of said third processor that corresponds to a memory address in a same cache line as the cache line written into said cache memory of said first processor, said third processor treats the retrieved data as possibly invalid, and wherein the retrieved data is later determined to be valid or invalid based on whether or not the speculative processing performed by said first processor is canceled.