Patent ID: 8584072
Filing Date: 2013-11-12
Classification: G06F

Abstract:
1. In an automated design process for an integrated circuit, a method comprising: using a computer to present a user with a simulation environment; within the simulation environment, providing the user with a choice to select between parasitic simulation modes of varying accuracy, said modes including a mode without parasitic and a plurality of modes including parasitics with a varying degree of accuracy; wherein said mode without parasitics includes a schematic mode representation of the circuit; wherein at least one of said modes that includes parasitics includes a schematic mode representation of the circuit having parasitic estimate values generated on the schematic of the circuit using layout estimates; and wherein at least one of said modes that includes parasitics includes a layout mode representation of the circuit in which an approximation of parasitics is extracted from a layout representation of the circuit; receiving a selection from the user from among said modes; in response to a user selection that includes a layout mode representation of a portion of the circuit that includes one or more nets and instances connected to the one or more nets, producing a coupling model for use in the layout representation of the circuit that models parasitic coupling interactions between the one or more nets and the instances connected to the one or more nets; wherein producing the coupling model includes receiving an indication from the user of one or more attributes of connection of the coupling model to the layout representation of the circuit; and performing simulation tests for the circuit at the selected degree of accuracy.