Patent ID: 6339809
Filing Date: 2002-01-15
Classification: G06F,G11C

Abstract:
A buffer access control circuit for carrying out a process of updating an address one by one when consecutively accessing an upper buffer and a lower buffer as an access destination with respect to a buffer which is divided into the upper buffer and the lower buffer which are assigned the same address, said buffer access control circuit comprising:a first latch circuit which latches data in response to generating a lower buffer access signal for accessing the lower buffer; a second latch circuit which latches said data in response to generating an upper buffer access signal for accessing the upper buffer; a detection circuit which detects whether data latched by said first latch circuit and data latched by said second latch circuit match; and a modifying circuit which inputs said data to said first and second latch circuits, or inverts said data and inputs said inverted data to said first and second latch circuits when one of the upper and lower buffer access signals is generated and said detection circuit detects the match.