Patent ID: 6137309
Filing Date: 2000-10-24
Classification: H03K

Abstract:
An Exclusive-OR gate having four, two-by-two complementary, inputs A and NA, and B and NB and two complementary outputs, XOR and NXOR, the Exclusive-OR gate comprising:a first supply node;a second supply node; anda first cell and a second cell, each cell comprising:an output node;a first P type arm and a second P type arm, the two P type arms being parallel-connected, and each of the two P type arms comprising a first P type MOS transistor and a second P type MOS transistor, the two P type MOS transistors being series-connected between the output node of that cell and the first supply node, with the node between the two series-connected P type MOS transistors being an intermediate node; anda first N type arm and a second N type arm, the two N type arms being parallel-connected, and each of the two N type arms comprising a first N type MOS transistor and a second N type MOS transistor, the two N type MOS transistors being series-connected between the output node of that cell and the second supply node, with the node between the two series-connected N type MOS transistors being an intermediate node; andpotential imposing means for preventing at least one of the intermediate nodes from being in a floating state for all possible transitions of the logic states of the inputs,wherein:the control gates of the two transistors of each of the first P type arm, the second P type arm, the first N type arm, and the second N type arm of each cell are coupled to receive one of the four pairs of inputs {A,B}, {NA,B}, {A,NB}, or {NA,NB} or the reverse of one of these four pairs;the two same-type arms of a cell receive two-by-two complementary input pairs;the two N type arms of the first cell arc coupled to receive the same pairs of inputs as the two P type arms of the second cell; andthe two P type arms of the first cell are coupled to receive the same pairs of inputs as the two N type arms of the second cell.