Patent ID: 7945880
Filing Date: 2011-05-17
Classification: G06F

Abstract:
1. A method of retiming a circuit, the method comprising: with a processor performing at least one of computing an upper bound and a lower bound for a clock period of a clock signal in response to a netlist of a circuit, wherein the clock signal clocks the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; generating a largest arrival time and a smallest arrival time of input signals for each node of the circuit; computing an upper bound and a lower bound of a retiming value for each node of the circuit, wherein the computed upper bound and lower bound of a retiming value for each node determines if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper and lower bounds of the retiming value and the largest and smallest arrival times for input signals for each node.