Patent ID: 6154869
Filing Date: 2000-11-28
Classification: H03M

Abstract:
A circuit for generating error position indicators in Reed-Solomon decoding, comprising:a root detection circuit, for sequentially evaluating an error locator polynomial corresponding to a plurality of data words corresponding to error locator polynomial coefficients, for each of a plurality of elements in a finite field, and for generating a zero signal responsive to identifying a root of the error locator polynomial;an error position register comprising a plurality of stages, each of the error position register stages having a data input and having a control input;a decoder, coupled to the root detection circuit and to the error position register, for sequentially enabling the plurality of error position register stages responsive to the root detection circuit generating the zero signal;an index counter for generating a count corresponding to the member of a finite field for which the root detection circuit is evaluating the error locator polynomial; anda subtractor for subtracting the count from a constant corresponding to the number of members of the finite field, the subtractor having an output coupled to the data input of each of the plurality of register stages of the error position register stages.