Patent ID: 9208130
Filing Date: 2015-12-08
Classification: G06F,H03K,H03L,H04L

Abstract:
1. A phase interpolator comprising: a first plurality of digital-to-analog converters coupled to receive a first phase of a clock signal; a second plurality of digital-to-analog converters coupled to receive a second phase of the clock signal; a third plurality of digital-to-analog converters coupled to both the first phase of the clock signal and the second phase of the clock; wherein each digital-to-analog converter of the third plurality of digital-to-analog converters is configurable to receive either the first phase of the clock signal or the second phase of the clock signal; and a control circuit coupled to generate control signals for the third plurality of digital-to-analog converters based upon a phase code associated with a phase of an output clock signal, wherein the control signals configure digital-to-analog converters of the third plurality of digital-to-analog converters to receive either the first phase of the clock signal or the second phase of the clock signal.