Patent ID: 8054105
Filing Date: 2011-11-08
Classification: G11C,H03M

Abstract:
1. A sample hold circuit, comprising: a sample unit, configured to sample an input signal when the sample hold circuit is in a first state, wherein the input signal comprises a waveform signal and a ground signal, and the sample unit comprises: a direct current (DC) voltage elimination unit, coupled to the sample unit, configured to lower a predetermined percentage of a DC voltage in the input signal sampled by the sample unit when the sample hold circuit is in the first state, and configured to eliminate a residual percentage of the DC voltage when the sample hold circuit is in a second state; and a hold unit, coupled to the sample unit and the DC voltage elimination unit, configured to output an alternating current (AC) signal in the input signal sampled by the sample unit when the sample hold circuit is in the second state; wherein the first switch, the second switch, the third switch, and the sixth switch are controlled by a first signal to be turned on in the first state and to be turned off in the second state; wherein the fourth switch and the fifth switch are controlled by a second signal to be turned off in the first state and to be turned on in the second state.