Patent ID: 7671639
Filing Date: 2010-03-02
Classification: H03K

Abstract:
1. An electronic circuit comprising a drive unit, which generates at least one drive signal, two or more power semiconductor switches each having a first and a second main terminal, which power semiconductor switches are synchronously switchable switched synchronously by the drive signal, the first and the second main terminals of the power semiconductor switches in each case being electrically connected in parallel among one another, for each of the power semiconductor switches a first and a second electrically conductive connection for connection to the drive unit, a first inductance in each of the first electrically conductive connections, a second inductance in each of the second electrically conductive connections, the first inductance being coupled to the second inductance for each of the power semiconductor switches wherein a respective common-mode rejection inductor is provided for each of the power semiconductor switches, in each case a first winding of the common-mode rejection inductor forming the second inductance and in that for each common-mode rejection inductor a common-mode inductance L D,i (G) is chosen which is greater than a minimum common-mode inductance L D (G) where where ΔL E is a maximum difference L Exi −L E,j between two emitter inductance L E,I and L E,j where i≠jε{1,2,3}, I SC is a short-circuit current of the power semiconductor switches and ΔI G is a maximum permissible difference I i −I j between two gate currents I i and I j , where i≠jε{1,2,3}.