Patent ID: 6295315
Filing Date: 2001-09-25
Classification: H04L

Abstract:
In an integrated circuit, a built-in, self-test vernier period measurement system for measuring a varying period in a periodic signal waveform that is generated by the integrated circuit and has first and second waveform features, comprising:first and second matched solid-state oscillators that are included in the integrated circuit and generate respective first and second oscillation signals with substantially matched frequencies, the first and second oscillators being repeatedly triggered with respect to the respective first and second waveform features;a coincidence detector that is included in the integrated circuit and detects when selected portions of the first and second oscillation signals are coincident with each other;a counter that repeatedly provides a measurement count of the periods of at least one of the first and second oscillation signals from when it is triggered to when it is coincident with the other of the first and second oscillation signals, wherein plural successive measurement counts are obtained for the varying period and in which the system further comprises a measurement data analysis system for providing a jitter analysis of the varying period based upon the plural measurement counts.