Patent ID: 8659166
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A memory device comprising a laminated chip package laminated a plurality of memory chips each having a plurality of memory cells and a controller chip having a control circuit controlling read/write from/to the plurality of memory cells, the laminated chip package and the controller chip being laminated, wherein each of the memory chips comprising: a device region in which the plurality of memory cells are formed; a resin insulating layer made of an insulating resin formed outside the device region; and a plurality of first wiring electrodes connected to the plurality of memory cells and extending from the device region to the top of the resin insulating layer; wherein an interposed chip equal in outside dimension to the memory chip and having no semiconductor element is laminated between the laminated chip package and the controller chip, wherein the interposed chip has a plurality of second wiring electrodes formed in a common arrangement pattern in common with an arrangement pattern of a plurality of wiring electrodes for controller formed on the controller chip and connected to the control circuit, the second wiring electrodes being overlaid with the wiring electrodes for controller, wherein side surfaces of the plurality of memory chips and a side surface of the interposed chip form a common wiring side surface in which the surfaces are joined together without forming a step, and the first wiring electrodes are connected to the second wiring electrodes within the common wiring side surface, and wherein the controller chip is laid on the interposed chip, and the plurality of wiring electrodes for controller are connected to the plurality of second wiring electrodes.