Patent ID: 6153485
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method for fabricating field effect transistors having low sheet resistance gate electrodes comprising the steps of:a) providing a substrate;b) forming shallow trench isolation regions surrounding and electrically isolating device areas;c) forming a gate oxide layer on said device areas;d) depositing a polysilicon layer over said substrate;e) depositing a silicon nitride layer on said polysilicon layer;f) patterning said silicon nitride layer and said polysilicon layer to form electrodes over said device areas and over said shallow trench isolation regions; said electrodes having cap layers formed from the patterned silicon nitride layer thereover;g) forming sidewall spacers on said electrodes; said sidewall spacers are composed of silicon nitride;h) forming source/drain regions by ion implantation adjacent to said sidewall spacers in said device areas;i) depositing a first metal layer on said source/drain regions and annealing said substrate to form a first metal silicide on said source/drain regions;j) depositing an interlevel dielectric layer on said substrate;k) chemical mechanically polishing said interlevel dielectric layer down to said cap layers on said electrodes;l) etching back said interlevel dielectric layer to a level below the top of said electrodes; the etching back of said interlevel dielectric layer so that the top of said interlevel dielectric layer is below said top of said electrode by a distance in a range of between about 500 and 1000 .ANG.; and etching back said sidewall spacer exposing a top portion of said electrodes; and removing said cap layers over said electrodes; and implanting ions in said electrodes composed of said polysilicon layer thereby amorphizing the surface of said polysilicon layer, where said source/drain contact areas are protected by said second insulating layerm) depositing a second metal layer and annealing to form a second metal silicide layer on said electrodes while leaving on said insulating layer unreacted portions of said second metal layer;n) stripping said unreacted second metal layer on said second insulating layer, thereby completing said field effect transistors having said low sheet resistance.