Patent ID: 6809567
Filing Date: 2004-10-26
Classification: G06F,H03K,H03L

Abstract:
A circuit for generating multiple-phase clocks, comprising:a voltage-controlled oscillator (â€œVCOâ€ ) having a plurality of VCO cells cascaded in a ring structure to generate VCO output clocks; and a clock divider for receiving the VCO output clocks, the clock divider further comprising: a counter having a plurality of counter outputs, wherein the counter outputs cycle through a plurality of states; and a plurality of shift registers, wherein each shift register in the plurality of shift registers further comprises a plurality of registers, each shift register being coupled with the VCO output clocks, and at least one register in each shift register being coupled to a counter output to produce the multiple-phase clocks from the plurality of shift registers wherein a number of multiple-phase clocks is greater than a number of VCO output clocks.