Patent ID: 8791735
Filing Date: 2014-07-29
Classification: H03L,H04L

Abstract:
1. A receiving circuit comprising: a sampling circuit configured to sample an input data signal in synchronization with a first clock signal to obtain boundary data, and sample the input data signal in synchronization with a second clock signal to obtain center data; a decision feedback equalizer configured to perform equalization and binary decision on the center data using an equalization coefficient, and output a first output data signal; a first comparator circuit configured to perform binary decision on the boundary data and output a second output data signal; a phase detection circuit configured to detect phase information of the input data signal based on the first output data signal and the second output data signal; a phase difference computation circuit configured to calculate a phase difference of the first output data signal based on the equalization coefficient; a first phase adjustment circuit configured to adjust a phase of the first clock signal based on the phase information; and a second phase adjustment circuit configured to adjust a phase of the second clock signal based on the phase information and the phase difference.