Patent ID: 8706998
Filing Date: 2014-04-22
Classification: G06F,G11C

Abstract:
1. A method for managing a flash memory, which comprises the steps of: providing a plurality of flash chips forming the flash memory and organized in a plurality of physical blocks that can be deleted separately, the physical blocks having a limited maximum deletion frequency, the physical blocks being addressed by way of logic block addresses are converted into physical block addresses by way of an address table, wherein in each physical block a deletion counter is run in which a number of deletions of the physical block is counted, the flash memory having two regions with different types of the flash chips including a first region containing single-level flash chips having a large maximum deletion frequency, and a second region having multi-level flash chips having a lower maximum deletion frequency than said first region; when writing to the flash memory, initially carrying out an address conversion of logic addresses into physical addresses such that all the physical blocks of the first region are written; when all the physical blocks of the first region have been written and a further write process is to be carried out, copying the physical block in the first region having a lowest deletion counter into a blank physical block in the second region; in the address table, switching the physical block addresses assigned to the logic block addresses of these physical blocks; and deleting the physical block in the first region and the physical block is written with new data.