Patent ID: 8854897
Filing Date: 2014-10-07
Classification: G11C

Abstract:
1. A bit-line voltage controller, adapted to a static random access memory apparatus, comprising: a controller, receiving a bank selection signal and a clock signal, and deciding a pull-up time period, a pull-down time period, and a voltage keeping time period according to the bank selection signal and the clock signal; a voltage pull-up circuit, coupled to the controller, the voltage pull-up circuit pulling up a bit-line power according to a first reference voltage; a voltage pull-down circuit, coupled to the controller, the voltage pull-down circuit pulling down the bit-line power according to a second reference voltage; and a voltage keeping circuit, coupled to the controller, the voltage keeping circuit keeping the bit-line power equal to a output voltage during the voltage keeping time period, wherein, the voltage keeping time period is after the pull-up time period and the pull-down time period.