Patent ID: 8019921
Filing Date: 2011-09-13
Classification: G06F,Y02D

Abstract:
1. An apparatus comprising: a memory controller circuit configured to communicate a command to a memory module including a memory buffer and a memory device, the command indicating one of a plurality of modes of operation, wherein in a first mode of the plurality of modes of operation, a first signal is communicated between the memory controller circuit and the memory buffer circuit during a memory operation, and in a second mode of the plurality of modes of operation, the first signal is not communicated between the memory controller circuit and the memory buffer circuit during the memory operation, wherein when the memory device has a 4-bit data width, when the memory operation is a write operation, in the first mode, the memory controller circuit is configured to transmit to the memory buffer circuit one data strobe signal per four bits of data, and in the second mode, the memory controller circuit is configured to transmit to the memory buffer circuit one data strobe signal per eight bits of data, and wherein when the memory device has a 4-bit data width, when the memory operation is a read operation, in the first mode, the memory controller circuit is configured to receive from the memory buffer circuit one data strobe signal per four bits of data, and in the second mode, the memory controller circuit is configured to receive from the memory buffer circuit one data strobe signal per eight bits of data.