Patent ID: 8174129
Filing Date: 2012-05-08
Classification: H01L

Abstract:
1. A semiconductor package assembly comprising: a silicon-based package substrate having a thickness of less than about 200 μm; a semiconductor chip comprising at least one low-k dielectric layer having a k value of less than about 3.0; a plurality of solder bumps interposed between the semiconductor chip and a first surface of the silicon-based package substrate; a plurality of under bump metallizations formed on the first surface of the silicon-based package substrate disposed to receive the plurality of solder bumps and forming an outer perimeter; a plurality of BGA balls overlying the first surface of the silicon-based package substrate; and a plurality of conductive traces disposed on the silicon-based substrate each having a horizontal portion and each coupling at least one of the under bump metallizations to at least one of the BGA balls.