Patent ID: 6728835
Filing Date: 2004-04-27
Classification: G06F

Abstract:
In a data processing system having a first processor, which executes a release ownership instruction, with a dedicated first level cache memory, the improvement comprising:a. A dedicated system controller containing a dedicated second level cache memory whereby a cache miss within said dedicated first level cache memory results in a data request to said dedicated system controller; b. A release ownership signal associated with said release ownership instruction to indicate that said first processor does not soon expect to utilize said requested data a second time by marking said requested data as least recently used within said dedicated system controller upon a cache hit within said second level cache memory; c. a second processor and a shared third level storage unit wherein a cache miss of said dedicated second level cache memory results in a subsequent data request to said shared third level storage unit; and d. wherein said data request is immediately flushed from said dedicated second level cache memory after said shared third level storage unit honors said subsequent requested data only if said release ownership signal is present and said instruction is a write instruction.