Patent ID: 6977859
Filing Date: 2005-12-20
Classification: G11C

Abstract:
1. A semiconductor memory device adapted to have an interface compatible with a static random access memory, comprising: a cell array including a plurality of DRAM (dynamic random access memory) cells, each having a port for a write system and a port for a read system; an address holding circuit for holding an externally input address; a refresh address generation circuit for generating a refresh address; and a comparator circuit for comparing the refresh address output from said refresh address generation circuit with the address held in said address holding circuit; and a control circuit for performing control so that, when the comparison result indicates that the refresh address does not match the address, a read or write operation using one of the ports for the write and read systems of selected one of said DRAM cells and a refresh operation using the other of the ports for the write and read systems are performed in parallel, and when the comparison result indicates that the refresh address matches the address, the refresh operation is stopped.