Patent ID: 6240033
Filing Date: 2001-05-29
Classification: G11C

Abstract:
An integrated circuit having a number of replace address signal generators, each generating a replace address signal for activating a redundant memory location to replace a defective memory cell, comprising:a program address generation circuit, in response to a test mode signal and an address signal, for generating a program address signal; anda number of anti-fuse unit circuits, each anti-fuse unit circuit connected to said each replace address signal generator and including an anti-fuse element, wherein the anti-fuse unit circuit is selected by the program address signal and the anti-fuse element contained in the selected anti-fuse unit circuit is programmed by using a voltage signal to thereby activate a corresponding replace address generator, wherein the anti-fuse unit circuit further includes:an anti-fuse selection circuit, in an anti-fuse programming procedure, for programming the anti-fuse element in response to the program address signal and a programming voltage signal, and, in an anti-fuse state reading operation, for generating a state signal in response to the external voltage signal and the power-up signal;an anti-fuse state evaluation circuit, in the anti-fuse state reading operation, for generating a regulated state signal in response to the external voltage signal and the power-up signal; anda latch circuit for latching the regulated state signal and for generating a latched signal representing the regulated state signal to be coupled to the corresponding replace address signal generator.