Patent ID: 6253278
Filing Date: 2001-06-26
Classification: G06F,G11C,Y02D

Abstract:
A computer memory comprising:a first memory module including a first plurality of memory components, each of which having a plurality of data outputs of a first data width and at least one timing signal output;a second memory module including a second plurality of memory components, each of which having a plurality of data outputs of a second data width and at least one timing signal output, said second data width being different than said first data width, a number of said first plurality of memory components is different than a number of said second plurality of memory components;a plurality of data lines coupling each of said plurality of data outputs of each of said first plurality of memory components to a respective one of each of said plurality of data outputs of each of said second plurality of memory components; anda plurality of timing signal lines coupling each of said at least one timing signal output of each of said first plurality of memory components to a respective one of said at least one timing signal output of each of said second plurality of memory components in a one-to-one correspondence.