Patent ID: 7141862
Filing Date: 2006-11-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer; a first element isolation region defining a high breakdown voltage transistor forming region in the semiconductor layer; a second element isolation region including a trench dielectric layer defining a low voltage driving transistor forming region in the semiconductor layer; a high breakdown voltage transistor formed in the high breakdown voltage transistor forming region; a low voltage driving transistor formed in the low voltage driving transistor forming region; an offset dielectric layer alleviating an electric field of the high breakdown voltage transistor formed in the high breakdown voltage transistor forming region; and a gate dielectric layer comprising the high voltage transistor formed on the offset dielectric layer, wherein an upper end of the offset dielectric layer is beak shaped and an outer edge of the gate dielectric layer is located between the first element isolation region and an edge of the offset dielectric layer.