Patent ID: 6535009
Filing Date: 2003-03-18
Classification: G01R

Abstract:
In combination with a semiconductor wafer having a multiplicity of semiconductor chips and a kerf, a configuration for carrying out burn-in processing operations of the semiconductor chips on the semiconductor wafer, the configuration comprising:a plurality of built-in-self-test (BIST) units disposed in the semiconductor wafer and carrying out the burn-in processing operations on the semiconductor chips on the semiconductor wafer, wherein substantially all of the semiconductor chips on the semiconductor wafer are each connected to a respective one of said BIST units, the burn-in processing operations subjecting the semiconductor chips to externally supplied voltages at an elevated temperature; lines routed in the kerf on the semiconductor wafer and connected to said BIST units, said lines supplying a supply voltage, a clock signal, and command and control signals to said BIST units; electrical fuses for storing burn-in test results for a later evaluation, said fuses connected to said BIST units and disposed in the kerf on the semiconductor wafer; and said BIST units being programmable using fuses provided in the kerf.