Patent ID: 7911873
Filing Date: 2011-03-22
Classification: G11C,H03L

Abstract:
1. A delay locked loop (DLL) circuit, the DLL circuit comprising: a clock divider circuit that provides a reference clock signal; a phase detector circuit that receives the reference clock signal and a delay line output signal and provides an error signal; a delay control finite state machine that receives the error signal and provides coarse and fine control signals and C-locked and F-locked signals; a delay circuit including a coarse delay line that receives the coarse control signal and a fine delay line that receives the fine control signal and a signal from the coarse delay line and provides the delay line output signal; and a low pass filter that receives the coarse and fine control signals and the C-locked and F-locked signals and provides an output measurement that filters out instantaneous fluctuations in one or more of these signals.