Patent ID: 6700162
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A chip structure, comprising:a substrate having a plurality of electric devices that are disposed on a surface of the substrate; a first built-up layer located on the surface of the substrate, and the first built-up layer including a dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the dielectric body of the first built-up layer and is electrically connected to the electric devices; a passivation layer disposed on the first built-up layer and provided with at least one opening exposing the first interconnection scheme; and a second built-up layer arranged over the passivation layer, the second built-up layer provided with a second interconnection scheme, the second interconnection scheme electrically connected to the first interconnection layer by passing through the opening of the passivation layer, the trace thickness of the second interconnection scheme larger than that of the first interconnection scheme, wherein a signal is transmitted from one of the electric devices to the first interconnection scheme, then passes through the passivation layer, and finally is transmitted to the second interconnection scheme, and further, the signal is transmitted from the second interconnection scheme to the first interconnection scheme by passing through the passivation layer, and finally is transmitted to the other one or more of the electric devices.