Patent ID: 7380038
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A multi-core computer system, comprising: a first processor core on a die and a second processor core on the die; a first priority register associated with the first processor core and a second priority register associated with the second processor core, wherein at least the second priority register is configured to be assigned on a per-thread basis; and an arbiter circuit operatively coupled to the first processor core and the second processor core, wherein the arbiter circuit allocates access to a shared resource available to the first processor core and the second processor core based on a first vector stored in the first priority register and a second vector stored in the second priority register, wherein at least the first vector comprises a plurality of values, and wherein a first value of the plurality of values corresponds to the shared resource and a second value of the plurality of values corresponds to an additional resource.