Patent ID: 6732247
Filing Date: 2004-05-04
Classification: G06F

Abstract:
A processor comprising:a plurality of functional processing units; a multi-ported memory having a plurality of ports and a plurality of memory banks, the plurality of memory banks connected in pipelined fashion to achieve pipelined address lines and pipelined data lines; and a bus which couples the multi-ported memory to the plurality of functional processing units, the bus being coupled to the plurality of ports of the multi-port memory to allow parallel access to multiple memory banks of the multi-ported memory during a first clock cycle, wherein the plurality of functional processing units, the multi-ported memory and the bus are packaged within a processor chip set, the processor chip set including at least one die; wherein during a second clock cycle a given port of the plurality of ports carries a plurality of data, each one of said plurality of data having an address corresponding to a unique one of said plurality of memory banks.