Patent ID: 7370254
Filing Date: 2008-05-06
Classification: G01R,G11C

Abstract:
1. A method for compressing a test response in an integrated circuit, comprising: inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain; producing at least two intermediate values at least partially determined by the test value via logic; loading at least a portion of the intermediate values into plural memory elements; producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.