Patent ID: 6451651
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method of manufacturing DRAM device comprising:forming MOS transistors on a substrate; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer; forming a conductive layer for forming bit lines, a subsidiary silicon oxide layer, and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer, said subsidiary silicon oxide layer, and said subsidiary silicon nitride layer; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer, said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern; forming storage node contacts, storage nodes, a dielectric layer, and plate electrodes at a cell area; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed.