Patent ID: 7310269
Filing Date: 2007-12-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having memory cells arrayed in a matrix, which are connected to a word line and a bit line and store n values (n: natural number more than 3); and a control circuit which controls each potential of the word line and the bit line in accordance with input data, and writes data to the memory cells, the control circuit carrying out a write operation to write a threshold voltage of k value (k≦n) to the memory cell, and charging the bit line through an N channel MOS transistor having one end connected to the bit line and a gate set at an intermediate potential, and thereafter changing the word line potential m times and verifying whether or not the memory cell reaches a target m threshold value (m≦k) by detecting a potential of another end of the N channel MOS transistor at each potential of the word line.