Patent ID: 6125068
Filing Date: 2000-09-26
Classification: G11C

Abstract:
A memory chip or module package comprising:(a) a plurality of package data lines;(b) a plurality of package address lines;(c) a plurality of package control lines;(d) a first group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package control lines;(e) a second group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package control lines;(f) a memory access control unit;wherein the first group of memory sub-packages contain at least one defective memory sub-package;wherein the second group of memory sub-packages also contain at least one defective memory sub-package;wherein the second group of memory sub-packages occupy some or all overlapping memory address regions with the first group of memory sub-packages;wherein the memory access control unit enables either the first group of memory sub-packages or the second group of memory sub-packages, at the appropriate memory timing cycles, according to the memory address regions.