Patent ID: 6275442
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A memory system comprising a decoder circuit, wherein the decoder circuit accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, the decoder comprising:a plurality of pre-decoding circuits, each pre-decoding circuit connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements, each pre-decoding circuit producing an output that is set in response to a unique state of the subset of the plurality of address lines;a plurality of latches having an input and an output, each latch input connected to an output of a respective one of the plurality of pre-decoding circuits; anda plurality of AND gates, each AND gate having a plurality of inputs and an output, each latch output connected to an AND gate input, and each AND gate output being one of the plurality of decode lines.