Patent ID: 8850164
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A microprocessor configured to receive first, second, and third program-adjacent macroinstructions of the instruction set architecture of the microprocessor, wherein the first macroinstruction instructs the microprocessor to move a first operand to a first architectural register of the microprocessor from a second architectural register of the microprocessor, wherein the second macroinstruction instructs the microprocessor to perform an arithmetic/logic operation using the first operand in the second architectural register and a second operand in a third architectural register of the microprocessor to generate a result, to load the result back into the first architectural register, and to update condition codes based on the result, wherein the third macroinstruction instructs the microprocessor to jump to a target address if the updated condition codes satisfy a condition specified by the third macroinstruction and to otherwise execute the next sequential instruction, the microprocessor comprising: a hardware execution unit; and an instruction translator, configured to simultaneously translate the first, second, and third program-adjacent macroinstructions into a single micro-operation for execution by the hardware execution unit; wherein the single micro-operation instructs the hardware execution unit to perform the arithmetic/logic operation using the first operand in the second architectural register and the second operand in third architectural register to generate the result, to load the result back into the first architectural register, to update the condition codes based on the result, and to jump to the target address if the updated condition codes satisfy the condition specified by the third macroinstruction and to otherwise execute the next sequential instruction.