Patent ID: 7116332
Filing Date: 2006-10-03
Classification: G06T

Abstract:
1. A computer-readable medium having computer-executable instructions communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, wherein the computer-executable instructions perform: receiving at least one instruction having at least one graphics data argument by the 3-D API; formatting said at least one instruction for use with the hardware procedural shader; providing said at least one formatted instruction to said hardware procedural shader; processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware procedural shader without accessing the main memory stack of the host computing system; outputting the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction; communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, and said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the vertex shader the fractional portion of said at least one floating point number; and wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.