Patent ID: 8399919
Filing Date: 2013-03-19
Classification: H01L

Abstract:
1. A unit block circuit of a semiconductor device, comprising: a first well; a first pickup unit configured to form a closed loop over the first well; a first transistor comprising a first gate and a first active region, and formed within the closed loop of the first pickup unit; and a first reservoir capacitor formed in a spare within the first pickup unit and arranged in a major-axis direction of the first gate of the first transistor, wherein the first reservoir capacitor comprises a second active region and a second gate, the second gate being formed over the second active region and extending in a direction substantially equal to the major-axis direction of the first gate, portions of the second active region on opposite sides of the second gate are electrically shorted together, the second active region has a width substantially equal to a width of the first active region of the first transistor, and the second gate has a width substantially equal to a width of a region covering the first gate and any other gates of the first transistor and the area between them.