Patent ID: 9153580
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a MOS transistor having a gate finger structure including a plurality of gate terminals; a first signal line formed at each of two ends of the plurality of gate terminals, connected to one end of one gate terminal, and formed in a direction parallel to a gate width direction; a second signal line formed in a direction perpendicular to the gate width direction in a region outside an active region of the transistor, and connected to the first signal line; a third signal line connected to each drain on the active region, formed in the direction perpendicular to the gate width direction, and having a line width smaller than a gate width of the transistor, wherein the third signal line does not overlap the second signal line; a fourth signal line connected to a source and formed in the direction parallel to the gate width direction; and a fifth signal line connected to the fourth signal line and formed in an arrangement where the fifth signal line does not overlap the second signal line.