Patent ID: 8796834
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A stack package comprising: a core layer having a first surface and a second surface opposite the first surface, and including first circuit wiring lines formed on the first surface; at least two unit packages stacked on the second surface of the core layer; and via patterns passing through the core layer and at least one of the stacked unit packages, each unit package comprising: a first semiconductor device having first bonding pads and first bumps formed on the first bonding pads; a first resin layer formed to cover upper and side surfaces of the first semiconductor device; wherein the via patterns pass through the core layer, the first and second resin layers, and the second circuit wiring lines of at least one of the stacked unit packages, and wherein the via patterns do not to pass through the second resin layer in an uppermost unit package which is positioned uppermost among the stacked unit packages.