Patent ID: 6815307
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method for fabricating a trench capacitor, comprising:providing a substrate having thereon a pad layer; etching in order of said pad layer and said substrate to form a deep trench; doping said deep trench to form a buried diffusion plate in said substrate at a lower portion of said deep trench; lining said deep trench with a node dielectric layer; performing a first polysilicon deposition and recess etching to embed a first polysilicon (Poly1) layer on said node dielectric layer at said lower portion of said deep trench, and said first polysilicon (Poly1) layer having a top surface, wherein said top surface of said first polysilicon layer and sidewall of said deep trench define a first recess; forming a collar oxide layer on sidewall of said first recess; performing a second polysilicon deposition and recess etching to embed a second polysilicon (Poly2) layer on said first polysilicon (Poly1) layer; forming a mask layer partially masking said collar oxide layer; removing said collar oxide layer not masked by said mask layer and said second polysilicon (Poly2) layer; removing said mask layer; and performing a third polysilicon deposition and recess etching to embed a third polysilicon (Poly3) layer on said second polysilicon (Poly2) layer.