Patent ID: 6297534
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A power semiconductor device comprising:a first conductivity type active layer provided on an insulation region;a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions, a drain current flowing from said first conductivity type source layer to said first conductivity type drain layer through said first conductivity type semiconductor regions,wherein said plurality of first and second conductivity type semiconductor regions are formed above said insulation region with said first conductivity type active layer interposed therebetween.