Patent ID: 7200066
Filing Date: 2007-04-03
Classification: G11C

Abstract:
1. A power supply system for memory means, comprising: a memory means for reading and writing data coupled to a regulated supply voltage; voltage calibration signals read out from said memory means and coupled to a voltage regulator and an amplifier means; said voltage regulator receiving an unregulated supply voltage, a bandgap reference voltage and said voltage calibration signals and generating at its output a regulated supply voltage which is adjusted by a first feedback loop which includes said memory means, said voltage calibration signals, and said regulated supply voltage; a power-on-reset signal generated from said bandgap reference voltage and said regulated supply voltage to inhibit read/write operations to said memory means during power-up; a supply voltage flag generated from said bandgap reference voltage, said voltage calibration signals, and said regulated supply, said supply voltage flag enabling read/write operations for said memory means, where said supply voltage flag is adjusted by a second feedback loop including said memory means, said voltage calibration signals, and said regulated supply voltage.