Patent ID: 6472261
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method for forming a contact in an integrated circuit device, comprising:forming a gate electrode on a substrate surface, the gate electrode having a capping layer of a first material on an upper surface of the gate electrode leaving sides of the electrode exposed; forming sidewalls alongside the gate electrode, the sidewalls including: a first region of a second material selectively etchable over the first material and formed to a selected thickness on both a side of the gate electrode and the substrate surface adjacent the gate electrode, and a second region of the first material on the second material formed on the first region alongside the gate electrode and over the substrate surface, wherein the first region of each sidewall is an L-shaped oxide layer formed by reoxidizing the substrate and the exposed sides of the gate electrode;forming an interlevel dielectric layer of the second material over the gate electrode, sidewalls, and substrate; etching an opening through the interlevel dielectric layer to expose a portion of the substrate, wherein the gate electrode is protected by the sidewalls and the capping layer; forming a conductive plug in the opening in contact with the exposed portion of the substrate by: depositing a conductive material over the interlevel dielectric layer and filling the opening; and etching back the conductive material to form a plug having an upper surface approximately coplanar with an upper surface of the interlevel dielectric layer; and forming an interconnect over the interlevel dielectric and the conductive plug.