Patent ID: 6253272
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A method for suspending and resuming tasks in a multi-tasking integrated circuit interfacing two I/O buses wherein said multi-tasking integrated circuit interfacing two I/O buses includes an on-chip sequencer that executes a plurality of routines to control operation of a plurality of I/O bus interface circuits within said multi-tasking integrated circuit interfacing two I/O buses, said method comprising:suspending execution of a first routine, that is used with a first I/O bus interface circuit in said multi-tasking integrated circuit interfacing two I/O buses, by executing a single instruction to branch from said first routine to a second routine,wherein executing said single instruction includes writing a return address for the first routine in a first storage location, and branching to said second routine; andsaid single instruction is executed by said on-chip sequencer; andreturning from said second routine to said first routine by executing a single instruction that restores said return address in said first storage location, and that causes said on-chip sequencer to resume execution of said first routine at said return address.