Patent ID: 8301842
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. An apparatus for allocating entries in a set associative cache memory, the apparatus comprising: an array, configured to provide a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit, wherein the first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request, wherein the first PLRU vector is a tree of bits comprising a plurality of levels; and toggling logic, configured to receive the first PLRU vector and to toggle predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request, wherein the second PLRU vector specifies a second entry different from the first entry from the same set, wherein the predetermined bits comprise bits of a predetermined one of the plurality of levels of the tree.