Patent ID: 6507516
Filing Date: 2003-01-14
Classification: G11C,H01L

Abstract:
An electrically erasable programmable read only memory cell, comprising:a first well of P-type conductivity; an N-well coupler region formed within the first well of P-type conductivity; a N-well window region formed within the first well of P-type conductivity and spaced apart from the N-well coupler region; a first P+type region formed within the N-well window region; a second P+type region formed within the N-well window region and spaced apart from the first P+type region; a first contact which couples a first bit line to the first P+type region; a second contact which couples a second bit line to the second P+type region; a single polysilicon layer disposed over the N-well coupler region and the N-well window region which defines a floating gate of the electrically erasable programmable read only memory cell.