Patent ID: 7646233
Filing Date: 2010-01-12
Classification: H03K

Abstract:
1. A level shifting circuit, comprising: a first driver p-type junction field effect transistor (JFET) of a having a source coupled to a reference supply node, a drain coupled to an output node, and a gate coupled to a first driver control node; a second driver n-type JFET having a source coupled to a boosted supply node and a drain coupled to the output node; and a first charge pump circuit coupled between the first driver control node and an input node coupled to receive an input signal, the first charge pump circuit coupling a first terminal of a first capacitor between the reference supply node and a power supply node in response to the input signal; wherein the power supply node is coupled to receive a power supply potential, the reference supply node is coupled to receive a reference potential, the boosted power supply node is coupled to receive a boosted potential, the power supply potential is positive with respect to the reference potential, and the boosted potential is negative with respect to the reference potential.