Patent ID: 8659532
Filing Date: 2014-02-25
Classification: H01L,H03K

Abstract:
1. A display device comprising: a pixel comprising a first transistor; and a driving circuit electrically connected to a gate of the first transistor, the driving circuit comprising a first circuit comprising a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor, wherein a gate of the eighth transistor is electrically connected to a gate of the tenth transistor, wherein one of a source and a drain of the tenth transistor is electrically connected to a gate of the ninth transistor, wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the ninth transistor, wherein a first power source potential is applied to the other of the source and the drain of the second transistor, wherein the first power source potential is applied to the other of the source and the drain of the fourth transistor, wherein the first power source potential is applied to the other of the source and the drain of the sixth transistor, wherein the first power source potential is applied to the other of the source and the drain of the eighth transistor, and wherein the first power source potential is applied to the other of the source and the drain of the tenth transistor.