Patent ID: 7718448
Filing Date: 2010-05-18
Classification: H01L

Abstract:
1. A method of measuring misalignment in a plurality of transistor arrays, each transistor array of the plurality of transistor arrays having a plurality of transistors, the plurality of transistors including a first transistor and a second transistor, each first transistor having a first channel that lies between and touches a drain region and a first source region, and a first gate that lies over the first channel, each second transistor having a second channel that lies between and touches the drain region and a second source region, and a second gate that lies over the second channel, the first gate and the second gate in each transistor array being electrically isolated, the method comprising: applying voltages to the plurality of transistors; measuring a value for the first transistor in each transistor array to determine a plurality of first measured values such that each first transistor has a first measured value, and a value for the second transistor in each transistor array to determine a plurality of second measured values such that each second transistor has a second measured value, a first measured value being measured after voltages have been applied to the drain region, the first source region, the first channel, and the first gate of a first transistor, a second measured value being measured after voltages have been applied to the drain region, the second source region, the second channel, and the second gate of a second transistor; determining a first statistical measure from the plurality of first measured values, and a second statistical measure from the plurality of second measured values; and determining a difference between the first statistical measure and the second statistical measure.