Patent ID: 7463539
Filing Date: 2008-12-09
Classification: G11C

Abstract:
1. A method for operating memory device for a read operation, the memory device including an array of memory cells with bit lines selectively connectable to sense amplifiers, the method comprising: pre-charging a first set of selected bit lines to a pre-charge voltage and coupling the first set of selected bit lines to a set of sense amplifiers; sensing data from cells coupled to the first set of selected bit lines; transferring charge from the first set of selected bit lines to corresponding members of a second set of bit lines in response to address signals; discharging charged bit lines other than the second set of bit lines in response to said address signals; after said transferring charge and said discharging, pre-charging the second set of bit lines to the pre-charge voltage and coupling the second set of selected bit lines to said set of sense amplifiers in response to said address signals; and sensing data from cells coupled to the second set of bit lines.