Patent ID: 6468861
Filing Date: 2002-10-22
Classification: G11C,H01L

Abstract:
A method for manufacturing a non-volatile semiconductor memory having a plurality of memory cells with an insulative trap gate, the method comprising steps of:forming striped patterns extending in a word line direction on a substrate; forming side wall insulating films on both side walls of the striped patterns by depositing an insulating film on said striped pattern and etching throughout the surface of the insulating film; selectively removing said striped patterns; depositing a gate insulating film including a trap gate insulating film on the exposed substrate; and depositing a conductive layer throughout on the surface and removing an upper part of said conductive layer except for a region between said side wall insulating films, wherein memory cells constructed of the gate insulating film and the conductive layer separated by said side wall insulating film are formed.