Patent ID: 8208277
Filing Date: 2012-06-26
Classification: G11C,Y10T

Abstract:
1. A memory module, comprising: a first rank of memory devices; a second rank of memory devices, the first rank of memory devices and the second rank of memory devices grouped into a plurality of memory device stacks; and a hub including a plurality of DQ signals operably shared between memory devices of the first rank of memory devices and memory devices of the second rank of memory devices, wherein each individual memory device stack of the plurality of memory device stacks includes a memory device from the first rank of memory devices and a memory device from the second rank of memory devices, wherein each individual memory device stack of the plurality of memory device stacks includes a first memory device operably coupled to a first portion of a plurality of DQ signals and a second memory device operably coupled to a different, second portion of the plurality of DQ signals.