Patent ID: 8148785
Filing Date: 2012-04-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate of a first conductivity type; a first well layer of a second conductivity type disposed in a surface portion of the substrate; a second well layer of the first conductivity type disposed in a surface portion of the first well layer; a third well layer of the first conductivity type disposed in the surface portion of the first well layer, the third well layer being spaced apart from the second well layer; a depletion-type MOSFET disposed in the second well layer; and an enhancement-type MOSFET disposed in the third well layer; wherein the depletion-type MOSFET comprises: a first drain layer of the second conductivity type disposed in a surface portion of the second well layer; a first source layer of the second conductivity type disposed in the surface portion of the second well layer, the first source layer being spaced apart from the first drain layer; a depletion layer of the second conductivity type disposed in the surface portion of the second well layer, the depletion layer being in contact with the first drain layer and the first source layer; a first pickup layer of the first conductivity type disposed in the surface portion of the second well layer; and a first gate electrode above the depletion layer with a first gate oxide film interposed between the depletion layer and the first gate electrode; and wherein the enhancement-type MOSFET comprises: a second drain layer of the second conductivity type disposed in a surface portion of the third well layer; a second source layer of the second conductivity type disposed in the surface portion of the third well layer, the second source layer being spaced apart from the second drain layer; a channel layer of the first conductivity type disposed in the surface portion of the third well layer, the channel layer being in contact with the second drain layer and the second source layer; a second pickup layer of the first conductivity type disposed in the surface portion of the third well layer; and a second gate electrode above the channel layer with a second gate oxide film interposed between the channel layer and the second gate electrode; the semiconductor device further comprising: an output terminal connected electrically to the first gate electrode, the first source layer, the second gate electrode and the second drain layer; a high-potential-side terminal connected electrically to the first drain layer; and a low-potential-side terminal connected electrically to the first pickup layer, the second source layer and the second pickup layer.