Patent ID: 6590579
Filing Date: 2003-07-08
Classification: G06T

Abstract:
Apparatus comprising:a memory containing a plurality of texture tiles and an output having a plurality of pixels capable of being traversed in horizontal bands and vertical columns defining a plurality of segments; said output capable of having a primitive displayed thereon and a texture displayed on said primitive; a cache containing a subset of said plurality of texture tiles; a graphics processor connected to said cache and said memory, said processor using said texture tile to map said texture on said plurality of pixels on said output, said processor using a texture tile from said subset when a processor required texture tile is in said cache and from said plurality of texture tiles in said memory when said processor required texture tile is not in said cache; a plurality of registers in said cache, each of said registers associated with each of said plurality of texture tiles in said subset of said plurality of texture tiles in said cache, said register having an entry recording when a texture tile in a first segment is in a spatial position to be reused in a second traverse; and said graphics processor replaces a texture tile in said cache using said entries in said register when said processor uses a texture tile from said memory with said texture tile from said memory based on replacing the least likely texture tile to be reused of said texture tiles in said cache.