Patent ID: 6807504
Filing Date: 2004-10-19
Classification: G06F

Abstract:
An apparatus for testing I/O ports of a computer motherboard operationally under control of a test code, comprising:a circuit board; a first connector electrically connected to the circuit board, including a plurality of parallel interface data pins, a plurality of parallel interface status pins and a plurality of parallel interface control pins, for establishing electrical connections with corresponding pins of a parallel port of the computer motherboard; a first test circuit coupled to the first connector, comprising a logic device coupled to logically operate the parallel interface data pins and the parallel interface control pins on the first connector and to provide a set of logic signals to a portion of the parallel interface status pins on the first connector; a second connector electrically connected to the circuit board, including a pair of universal serial bus (USB) interface differential data pins, for establishing electrical connections with corresponding pins of a USB port of the computer motherboard; and a second test circuit coupled to the second connector, comprising: a first resistor connected between a first voltage source and one of the USB interface differential data pins; a second resistor connected between a second voltage source and the other USB interface differential data pin; and a third resistor connected between the pair of USB interface differential data pins; wherein the first, the second and the third resistors are connected in series.