Patent ID: 6678817
Filing Date: 2004-01-13
Classification: G06F,G11C

Abstract:
A multi-architecture computer system capable of implementing a native instruction set architecture (ISA) and an emulated ISA comprising:a memory subsystem of a native ISA; a fetch engine of the native ISA, said fetch engine being electrically connected to the memory subsystem of the native ISA wherein the fetch engine accesses the memory subsystem to retrieve a line of instructions from the memory subsystem; an engine of an emulated ISA, wherein the engine of the emulated ISA is electrically connected to the fetch engine and interfaces with the fetch engine using a handshake protocol, wherein the engine of the emulated ISA receives a line of instructions and a fetch complete signal from the fetch engine; a fetch address queue that stores a fetch address for the line of instructions retrieved from the memory subsystem, wherein the fetch address queue is controlled by the fetch complete signal such that the fetch address is stored in the fetch address queue until the fetch complete signal is received; a macroinstruction queue that receives a line of instructions from the fetch engine; a queue in the emulation engine that stores the fetch addresses, wherein the queue in the engine of the emulated ISA mirrors the fetch address queue, and wherein the fetch addresses progress through pipeline stages of the fetch engine and the engine of the emulated ISA synchronously; and pipeline advance logic that controls progression of the fetch addresses through the pipeline stages, wherein the pipeline advance logic receives a delayed version of the fetch complete signal and advances the fetch addresses through the fetch engine and the engine of the emulated ISA based on the delayed version of the fetch complete signal.