Patent ID: 6465805
Filing Date: 2002-10-15
Classification: G11C,H01L

Abstract:
A decoder for a memory device, comprising:a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; and a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer; a number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars, wherein each single crystalline vertical floating gate transistor includes; an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer; an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer; and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and a floating gate opposing the ultra thin single crystalline vertical body region; a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array; and wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors and serves as a control gate.