Patent ID: 7680224
Filing Date: 2010-03-16
Classification: H03D,H03J,H04L

Abstract:
1. An automatic frequency control circuit for a receiver circuit, the circuit comprising: a first time measurement timer having a clock input configured to receive a reference clock signal, an enable input configured to receive a received data signal, and a first ready output configured to become active when the first time measurement timer counts a predetermined number of reference clock cycles when the first time measurement timer is enabled, where the first time measurement timer is enabled responsive to a first logic state of the received data signal; a second time measurement timer having a clock input configured to receive the reference clock signal, an enable input configured to receive the received data signal, and a second ready output configured to become active when the second time measurement timer counts the predetermined number of reference clock cycles when the second time measurement timer is enabled, where the second time measurement timer is enabled responsive to a second logic state of the received data signal; a first counter having a clock input configured to receive a baseband data signal of the receiver, an enable input configured to receive the received data signal, a stop input coupled to the first ready output of the first time measurement timer, and an output for a count value of the first counter, where the first counter is enabled responsive to the first logic state of the received data signal; a second counter having a clock input configured to receive a baseband data signal of the receiver, an enable input configured to receive the received data signal, a stop input coupled to the second ready output of the second time measurement timer, and an output for a count value of the second counter, where the second counter is enabled responsive to the second logic state of the received data signal; a subtractor having a first input coupled to the output of the first counter and a second input coupled to the output of the second counter, and an output for a difference of the count values of the first and second counters; an AND logic gate having a first input coupled to the ready output of the first time measurement counter, a second input coupled to the ready output of the second time measurement counter, and an output; a first latch having an input, an enable input coupled to the output of the AND logic gate, and an output; a second latch having an input coupled to the output of the first latch, an enable input configured to receive a control signal, and an output; and an adder having a first input coupled to the output of the subtractor, a second input coupled to the output of the second latch, and an output coupled to the input of the first latch.