Patent ID: 6920593
Filing Date: 2005-07-19
Classification: G11C

Abstract:
1. An apparatus for logically verifying a memory control circuit, comprising: a request unit for issuing a memory access request to the memory control circuit in accordance with a predetermined test program; a first holding unit for holding a transaction issued from said request unit to the memory control circuit; a second holding unit for holding a transaction issued from the memory control circuit to a memory to be accessed in response to the transaction; a comparison unit for comparing the transactions held in said first and second holding units every time a transaction is issued to the memory control circuit; a deletion unit for deleting the transactions from said first and second holding units when it is determined as a result of comparison that the two transactions are equivalent to each other; and a verification unit for outputting a verification error when the transaction remains in at least one of said first and second holding units after the test program quits.