Patent ID: 6335283
Filing Date: 2002-01-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a silicon oxide inter-layer dielectric having an upper surface and overlying a substrate; forming a plurality of spaced apart openings in the inter-layer dielectric; filling the openings with copper (Cu) or a Cu alloy to form a pattern comprising spaced apart neighboring interconnect members each having an upper surface; planarizing such that the upper surface of neighboring interconnect members is substantially coplanar with the upper surface of the inter-layer dielectric; treating the planarized surface with a nitrogen plasma to convert an upper portion of the inter-layer dielectric between neighboring interconnect members to a silicon oxynitride upper portion leaving a main silicon oxide region thereunder; and depositing a capping layer on the inter-layer dielectric and on the upper surface of the neighboring interconnect members.