Patent ID: 7473619
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a semiconductor substrate having a scribe lane region and a cell region; forming a gate pattern on the cell region; forming a lower interlayer insulating layer covering the gate pattern on the semiconductor substrate; forming a first interlayer insulating layer on the lower interlayer insulating layer; forming a preliminary alignment key pattern and a bit line pattern on the first interlayer insulating layer of the scribe lane region and the cell region respectively; forming a second interlayer insulating layer to cover the preliminary alignment key pattern and the bit line pattern; and patterning the second interlayer insulating layer, the first interlayer insulating layer and the lower interlayer insulating layer, thereby forming an alignment key trench having a predetermined width by the preliminary alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.