Patent ID: 6657967
Filing Date: 2003-12-02
Classification: H04J,H04L

Abstract:
A coding apparatus, comprising:an optical receiver for converting an optical signal into an electric signal data and generating a clock signal; a demultiplexer for demultiplexing said electric signal data and outputting demultiplexed data in the form of plurality of demultiplexed signals; a coding means for generating a FEC (Forward Error Correction) code by adding to said demultiplexed data additional parity bits and dummy bits for each demultiplexed signal in said data; a dummy bit elimination device which eliminates dummy bits from said FEC coded signals; said dummy bit elimination device including: (i) a converter for eliminating only dummy bits from FEC code supplied thereto so as to output only said FEC code; and (ii) a Phase Locking Loop for regenerating said clock signal and feeding write and read clock signals to said converter; a multiplexer for multiplexing outputs from said dummy bit elimination device; and an optical sender for converting an output of said multiplexer into an optical signal; wherein said dummy bit elimination device is inserted between said coding means and said multiplexer so that the outputs of said coding means are fed to said dummy bit elimination device and outputs of said dummy bit elimination device are fed to said multiplexer.