Patent ID: 6380088
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method for forming an MOS transistor comprising:providing a substrate; forming a pad dielectric layer over said substrate; forming an etch stop layer over said pad dielectric; creating shallow trench isolations in the substrate pad oxide, and etch stop layers; active areas of said substrate located between said shallow trench isolations; forming holes in said shallow trench isolations which expose sidewalls of said substrate in said active area; doping said sidewalls of said substrate in the active area where said holes are; forming conductive material in said holes and said conductive material are source and drain regions; removing the etch stop layer exposing sidewalls of said conductive material oxidizing the exposed sidewalls of said conductive material; forming spacers on top of the pad dielectric layer and on the sidewalls of the oxidized portions of the conductive material; removing the pad dielectric layer from the structure but not from under the spacers; forming a gate dielectric layer on said substrate in said active area between said spacers; and forming a gate electrode on said gate dielectric layer.