Patent ID: 6392955
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A memory device, comprising:a memory array; an address circuit coupled to the memory array, wherein the address circuit includes: an address register; a burst logic coupled to the address register; a first write address register coupled to the burst logic; a second write address register coupled to the first write address register; a first compare circuit coupled to the address register and the first write address register; a second compare circuit coupled to the address register and the second write address register; and a first selective connector coupled to the second write address register and the memory array; and a read circuit coupled to the memory array; a write circuit coupled to the memory array, wherein the write circuit includes: a first data input register; a second data input register coupled to the first data input register; a selective connector coupled to the first data input register and the second data input register; and a write driver coupled to the selective connector; and a control circuit coupled to the address circuit, the read circuit, and the write circuit.