Patent ID: 6339560
Filing Date: 2002-01-15
Classification: G11C

Abstract:
A dynamic semiconductor memory device for writing/reading out data in/from a memory cell via a write/read circuit as determined by a word line selected by a row address and a bit line selected by a column address, and temporally holding burst-written/read data by a data latch arranged on a data line connected to said write/read circuit, said device comprising:an address transition detector detecting an address change to generate an operation start instruction signal starting a write/read cycle; and a read-after-write transition detector detecting a change from a write mode to a read mode to generate a read-after-write instruction signal, wherein when the read-after-write instruction signal is generated, data held by said write/read circuit is transferred to said data latch, and when the data is held by said data latch and read is done for the same row address, the data held by said data latch is read out and output.