Patent ID: 6100127
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of forming a MOS transistor in a semiconductor substrate, said method comprising the steps of:forming an isolation region in said semiconductor substrate, said isolation region separating said semiconductor substrate into an ESD protective region for at least one transistor and a functional region for a plurality of integrated circuit devices;forming a gate insulator layer on said ESD protective region and said functional region;forming a polysilicon layer on said gate insulator layer;patterning said polysilicon layer to form a gate structure;doping said semiconductor substrate with a first concentration of a first dopant type using said gate structure as a first doping mask, for forming a lightly doped active region in said ESD protective region and in said functional region;forming an insulator layer over said semiconductor substrate and said gate structure;defining a resistor pattern located aside said gate structure on said ESD protective region by forming and patterning a photoresist layer;removing a portion of said insulating layer and of said gate insulator layer utilizing said photoresist layer as a mask, for forming a spacer structure surrounding said gate structure and for forming a resistor region under said resistor pattern on said ESD protective region;removing said photoresist layer;doping said semiconductor substrate with a second concentration of said first dopant type using said spacer structure, said gate structure, and said resistor region as a second doping mask, for placing a plurality of dopants in an active region of said ESD protective region and said functional region;first thermal annealing said semiconductor substrate to drive in and activate said plurality of dopants, to form a shallow junction region in a source region and a drain region of said ESD protective region and said functional region;forming a metal layer on said semiconductor substrate;second thermal annealing said semiconductor substrate to form a metal silicide layer on a top surface of said gate structure, a top surface of said source region and a top surface of said drain region, and to leave an unreacted metal layer on said isolation region, said spacer structure, and said resistor region; andremoving said unreacted metal layer from said isolation region, said spacer structure, and said resistor region.