Patent ID: 6463519
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A multi-CPU unit having a plurality of CPU units which are used for multi-CPU control operation, wherein each of said CPU units comprises:a device memory for handling device data; a shared memory comprising a two-port memory which has only a data storing area for each of said CPU units itself in which data can be written and read to/from each of said CPU units itself and the other CPU-unit; an OS to which the sequence of data transfer is written; and a microprocessor for transferring data between each of said CPU units itself and the other CPU-unit on the basis of the sequence which is written to said OS, wherein each of said microprocessors writes said device data which is stored in said device memory to said data storing area in each of said CPU units itself in the shared memory of each of said CPU units itself and directly reads the device data which is stored in said shared memory in the other CPU-unit to said device memory in each of said CPU units itself.