Patent ID: 6094733
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A semiconductor memory device tester comprising:a test pattern generator for generating a DC characteristic test pattern and a function test pattern;a first memory for storing abnormality occurrence information on a semiconductor memory device;a second memory for storing a test sequence;a third memory for storing abnormality occurrence information on a memory cell array of the semiconductor memory device;a fourth memory for storing an arithmetic operation algorithm used for replacing an abnormal portion of the memory cell array with a spare row/column;an arithmetic operation unit for performing an arithmetic operation, so as to replace an abnormal portion of the memory cell array, identified by the abnormality occurrence information stored in the third memory, with a spare row/column in accordance with the arithmetic operation algorithm; anda processor for performing first processing and second processing, said first processing including:(i) a step of causing the test pattern generator to execute a first function test in accordance with the test sequence, said first function test being a test for detecting an abnormal portion of the memory cell array of the semiconductor memory device; and(ii) a step of storing abnormality occurrence information on the memory cell array in the third memory if the abnormal portion is detected in the first function test, andsaid second processing including:(i) a step of causing the test pattern generator to execute both a DC characteristic test and a second function test after the first processing in accordance with the test sequence, said DC characteristic test being a test for detecting a DC characteristic of the semiconductor memory device, said second function test being a test for detecting an abnormal portion of the semiconductor memory device other than the memory cell array;(ii) a step of storing abnormality occurrence information on the semiconductor memory device except for the memory cell array in the first memory if the abnormal portion is detected in at least one of said DC characteristic test and the second function test; and(iii) a step of causing the arithmetic operation unit to execute the arithmetic operation for replacing the abnormal portion with the spare row/column in parallel to both said DC characteristic test and said second function test.