Patent ID: 8520460
Filing Date: 2013-08-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; a command generating circuit configured to issue one of a read command, a write command, and a refresh command based on to an input signal; a control section configured to select a selection bank from said plurality of banks based on said bank address when said read command or said write command is issued from said command generating circuit, perform a read operation or a write operation on said selection bank based on said row address and said column address, and perform a refresh operation on said selection bank when said refresh command is issued immediately after said read command or said write command, wherein said command generating circuit issues said read command or said write command based on a first input signal or a second input signal, when said first input signal or second input signal is supplied as said input signal, wherein said command generating circuit issues said refresh command immediately after said read command or said write command based on a third input signal, when said third input signal is supplied as said input signal immediately after said first input signal or said second input signal, wherein said input section inputs said address of said bank address, said row address and said column address for every X clocks (X is an integer equal to or greater than 2), and wherein said command generating circuit issues said read command or said write command based on said first input signal or said second input signal, when said first input signal or said second input signal is supplied in a first clock of said X clocks, and issues said refresh command immediately after said read command or said write command based on a third input signal, when said third input signal is supplied in a clock next to said first clock.