Patent ID: 6026038
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells and a plurality of corresponding reference cells;a plurality of memory cell word lines each associated with one of said memory cells;a plurality of reference cell word lines each associated with one of said reference cells;a plurality of first subword line drivers each driving one of said memory cell word lines;a plurality of second subword-line drivers each driving one of said reference cell word lines;a first power line connected to said first subword line drivers;a second line connected to said second subword line drivers;wherein during an operation mode a ground potential is applied to said first and second power lines, andwherein during a test mode there is supplied to either group of said memory cell word lines and reference cell word lines a ground potential through one of the first and second power lines, and there is supplied to the other group of said memory cell word lines and reference cell word lines a stress potential different from the ground potential through the other one of first and second power lines.