Patent ID: 6037812
Filing Date: 2000-03-14
Classification: H03K,H03L

Abstract:
A clock signal synthesizer for generating a synthesized clock signal, the clock signal synthesizer comprising:a multi-stage delay line that includes a plurality of variable delay elements, each delay element providing an output, and wherein a first element of the plurality of elements receives a reference clock signal as an input;a plurality of differential XOR gates disposed such that the two outputs of each consecutive pair of delay elements in the multi-stage delay line are provided as inputs to a corresponding one of the differential XOR gates:a multi-input differential NOR gate connected to receive an output from each of the differential XOR gates, the differential NOR gate providing the synthesized clock signal as an output;delay locked loop logic circuitry that receives the reference clock signal and the output of a final delay element in the multi-stage delay line as inputs and provides a multi-bit vector as an output; anda current digital-to-analog converter that receives the multi-bit vector as an input and mirrors a corresponding control current to each of the delay elements in the multi-stage delay line such that the amount of mirrored current controls the delay of the delay elements.