Patent ID: 6025647
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device, comprising:a plurality of slot pads arranged along a periphery of the redistribution layer, the plurality of slot pads being formed from the patterned metallization layer;an array of bump pads being arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads being formed from the patterned metallization layer, wherein each bump pad of the array of bump pads has a surface area that is selected to substantially equalize a capacitance parameter associated with an interconnection between a first selected one of the plurality of slot pads and a first bump pad of the array of bump pads; anda plurality of traces formed from the patterned metallization layer being configured to interconnect the plurality of slot pads to the array of bump pads, such that each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces.