Patent ID: 8659453
Filing Date: 2014-02-25
Classification: H03M

Abstract:
1. A digital radio frequency memory (DRFM) comprising: a splitter configured to receive and distribute an RF signal; a plurality of analog to digital converters (ADCs) coupled to said splitter, each ADC defining a channel and each of said plurality of ADCs being time interleaved; a clock circuit configured to produce a plurality of clock signals, wherein each clock signal is applied to each of the plurality of ADCs at a time different than a time the clock signal is applied to each other ADC to time interleave the plurality of ADCs; a plurality of SDAC circuits, each SDAC circuit coupled to an output of a corresponding ADC for processing digital samples belonging to the channel defined by the corresponding ADC, wherein each SDAC circuit comprises: a plurality of DACs, wherein each DAC is coupled to at least one of said SDAC circuits to receive the output DAC value from one of said plurality of SDAC circuits and each of said plurality of DACs is time interleaved; and a combiner configured to combine time interleaved outputs from said plurality of DACs.