Patent ID: 8928369
Filing Date: 2015-01-06
Classification: H03K

Abstract:
1. An apparatus comprising: a frequency divider comprising: a first latch configured to receive a clock signal and a complement of the clock signal and to generate a first latch first output and a first latch second output; and a second latch coupled to the first latch in a toggle-flop configuration, wherein the second latch is configured to receive the clock signal and the complement of the clock signal and to generate a second latch first output and a second latch second output; a first output circuit comprising: a second output circuit configured to receive the complement of the clock signal, the second latch first output, and the second latch second output; wherein the first output circuit is configured to generate a first in-phase reference signal and a second in-phase reference signal and the second output circuit is configured to generate a first quadrature signal and a second quadrature signal.