Patent ID: 6414526
Filing Date: 2002-07-02
Classification: H03L

Abstract:
A delay-locked loop (DLL) circuit comprising:a delay line having a delay that can be varied for delaying a periodic input signal having a period T, said delay line providing a plurality of delayed periodic signals each delayed relative to the periodic input signal by a respective fraction of the delay; and a control circuit connected to said delay line for locking the delay to the period T, said control circuit comprising a sequence-detector circuit for detecting in the plurality of delayed periodic signals sequences of digital values indicative of the delay and for varying the delay based upon the type of sequences detected so that the delay is locked to the period T; said sequence-detector circuit detecting transitions from a first logic level to a second logic level between consecutive bits of a word in which each bit corresponds to a respective delayed periodic signal, the word being reflective of the digital values of the plurality of delayed periodic signals when sample.