Patent ID: 7180127
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type and a surface; a trench formed into the substrate surface; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region formed in the substrate therebetween, wherein the first region is formed underneath the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the substrate surface; an electrically conductive floating gate having lower and upper portions, wherein the lower portion is disposed in the trench adjacent to and insulated from the channel region first portion, and wherein the upper portion extends above the substrate surface and includes a lateral protrusion that extends in a direction substantially parallel to the substrate surface; and an electrically conductive control gate that is disposed over and insulated from the channel region second portion, and is disposed laterally adjacent to and insulated from the floating gate lateral protrusion.