Patent ID: 6751278
Filing Date: 2004-06-15
Classification: H04B

Abstract:
A loop error detector in a PN (Pseudo Noise) code timing tracking loop, comprising:a first multiplexer for receiving an early I-channel signal and an early Q-channel signal, and alternately selecting the received early I and Q-channel signals at a Â½-chip period; a first accumulator for accumulating the early I and Q-channel signals multiplexed by the first multiplexer for a specific chip period; a second multiplexer for receiving a late I-channel signal and a late Q-channel signal, and alternately selecting the received late I and Q-channel signals at a Â½-chip period; a second accumulator for accumulating the late I and Q-channel signals multiplexed by the second multiplexer for the specific chip period; an operator for calculating a sum and a difference of the early and late I-channel signals accumulated by the first and second accumulators, calculating a sum and a difference of the early and late Q-channel signals, and multiplying the sums by the differences; and an adder for adding values obtained by multiplying the sums by the differences and outputting the added value as a loop error signal.