Patent ID: 6218694
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A semiconductor memory device comprising:a source region formed in the shape of a band;a drain region formed in the shape of a band in opposition to said source region;a first interconnect which is provided in a layer above said source region and which makes connection thereto;a second interconnect which is provided in a layer above said drain region, which makes connection thereto and which is provided on the same layer as said first interconnect; anda third interconnect, which is provided on the same layer as said first and second interconnects and which is provided so as to laterally cross said source and drain regions, this semiconductor memory device further comprising:a first contact region that is provided with a plurality of contacts in said source/drain region on one side of said third interconnect, and a second contact region that is provided with a plurality of contacts in said source/drain region on the other side of said third interconnect, said source region being connected via the contacts of said first contact region to said first interconnect, and said drain region being connected via the contacts of said first contact region to the second interconnect; andan interconnect layer having a resistance value that is lower than said source/drain region is provided below the third interconnect, along said source/drain region, said source region of said first contact region and said source region of said second contact region being connected by said interconnect layer having a lower resistance value than said source region, and said drain region of said first contact region and said drain region of the second contact region being connected by said interconnect layer having a lower resistance than said drain region.