Patent ID: 6710386
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A semiconductor memory device comprising:a first, second, third and fourth memory cells, an interval between said first and second memory cells being set in a first distance, an interval between said third and fourth memory cells being set in a second distance which is longer than said first distance, said first, second, third and fourth memory cells each having a cell transistor, a ferroelectric capacitor connected in parallel to said cell transistor, said ferroelectric capacitor having a bottom electrode, a top electrode and a ferroelectric film provided between said bottom and top electrodes, and said cell transistor having a source and drain terminals; a first wiring having a first and second ends and a center portion positioned at the same direction from said first and second ends, said first end of said first wiring being connected to said top electrode of said ferroclectric capacitor of said first memory cell, said second end of said first wiring being connected to said top electrode of said ferroelectric capacitor of said second memory cell; a first contact provided between said bottom electrode of said ferroelectric capacitor and one side of said source and drain terminals of said cell transistor; a second contact provided between said center portion of said first wiring and another side of said source and drain terminals of said cell transistor of said first and second memory cells connected in series, said second contact being arranged in the perpendicular direction with respect to the array direction of said first and second memory cells and at an interval between said third and fourth memory cells; a second wiring having said third, fourth ends and a center portion positioned at the same direction from said first and second ends, said third end of said second wiring being connected to said top electrode of said ferroelectric capacitor of said third memory cell, said fourth end of said second wiring being connected to said top electrode of said ferroelectric capacitor of said fourth memory cell; and a third contact provided between said center portion of said second wiring and one of said source and drain terminals of said cell transistor of said third and fourth memory cells connected in series, and said third contact being arranged with said second contact at an interval between said third and fourth memory cells.