Patent ID: 8683163
Filing Date: 2014-03-25
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a processor constructed to operate under control of a stored program comprising a sequence of program instructions selected from a predetermined instruction set; a master processor provided on the same integrated circuit as said processor operable to request access to storage locations of said processor, wherein said processor is configured to function as a slave with respect to the master processor; an interface circuit provided on the same integrated circuit as said processor which is operable to provide a common interface for both an external master apparatus and for said master processor to signal requests for access to storage locations of said processor, wherein said processor is configured to function as a slave with respect to the external master apparatus; and at least one of a control means and a controller operable to provide access between the storage locations and the interface circuit in response to the requests only at predetermined points in the execution of the stored program by said processor, wherein said one of the control means and the controller comprise a generic communication instruction of the processor instruction set, the generic communication instruction being available for execution only at said predetermined points by said processor in dependence upon a position of the generic communication instructions within the sequence of stored processor instructions as specified at program time such that execution timing of the stored processor instructions is independent of whether or not a request is supplied by one of said external master apparatus and said master processor at run time to said interface circuit, and wherein debug instructions are passed via said generic communication instruction; wherein the master processor and the external master apparatus are operable to access storage locations of said processor during real time operation of said processor without altering the timing and functionality of said processor, and are further adapted to provide at least one of control and debugging of said processor.