Patent ID: 8071441
Filing Date: 2011-12-06
Classification: H01L

Abstract:
1. A method of forming a DRAM array, comprising: forming a gate stack over a memory array region of a semiconductor substrate; the gate stack comprising, in ascending order from the substrate, a gate dielectric layer, a semiconductor material-containing layer, and at least one electrically conductive metal-containing layer over the semiconductor material-containing layer; forming a patterned mask over the gate stack, the patterned mask comprising carbon; providing the semiconductor substrate having the gate stack and patterned mask thereon within a reaction chamber; while the semiconductor substrate is within the reaction chamber, etching through the at least one metal-containing layer and only partially through the semiconductor material-containing layer; the etching utilizing Cl while the semiconductor substrate is within the reaction chamber, removing the patterned mask using O 2 and top power only within the chamber; the removal of the patterned mask exposing top surfaces of the projections; while the semiconductor substrate is within the reaction chamber and after removing the patterned mask, utilizing silicon tetrachloride and one or both of an oxygen-containing reactant and a nitrogen-containing reactant to form protective material along the top surfaces and along the opposing sidewalls; while the semiconductor substrate is within the reaction chamber, anisotropically etching the protective material to remove the protective material from the top surfaces while leaving the protective material along the opposing sidewalls; the anisotropic etching utilizing CF while the semiconductor substrate is within the reaction chamber and after the anisotropic etching of the protective material, etching through a remaining portion of the semiconductor material to transform the projections into transistor gates; the etching through the remaining portion of the semiconductor material forming sidewall segments of the transistor gates; said sidewall segments having exposed semiconductor material of the semiconductor material-containing layer; the etching through the remaining portion of the semiconductor material utilizing HBr and O while the semiconductor substrate is within the reaction chamber, oxidizing the exposed semiconductor material; forming source/drain regions within the semiconductor substrate adjacent the opposing sidewalls of the transistor gates; and forming capacitors in electrical contact with some of the source/drain regions and forming bitlines in electrical contact with others of the source/drain regions; the transistor gates gatedly coupling the capacitors with the bitlines; the transistor gates thus being incorporated into DRAM unit cells over the memory array region of the semiconductor substrate.