Patent ID: 6150205
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method of fabricating a dual gate, comprising:providing a first conductive type region and a second conductive type region isolated by an isolation structure;forming a polysilicon layer on the first and the second conductive type regions;forming a diffusion layer containing second type conductive ions on a second part of the polysilicon layer which covers the second conductive type region;implanting first conductive ions into a part of the first conductive region which covers the first conductive type region;performing a first thermal process;forming a metal layer;performing a second thermal process, so that the metal layer is transformed into a metal silicide layer;forming a dielectric layer on the metal layer; andpatterning the dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer to form a dual gate.