Patent ID: 8200940
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A method for performing a reduction operation in a multi-threaded computing device, the method comprising: receiving an active mask for a single-instruction, multiple data (SIMD) thread group; mapping an input lane value of a first thread to a first output lane value of the first thread to provide a first input for the reduction operation; determining that the active mask indicates that execution of a second thread is disabled; mapping, based on the active mask and the reduction operation, an input lane value of an active thread in the SIMD thread group as a second output lane value for the first thread to replace an invalid value of the second thread with a valid value and to provide a second input for the reduction operation; and converting the reduction operation into a move operation to map the valid value as the second output lane value for the first thread when the input lane value for an active thread is not available.