Patent ID: 7439109
Filing Date: 2008-10-21
Classification: H01L,Y10S

Abstract:
1. A method of forming an integrated circuit structure, said method comprising: forming an insulator on a first substrate structure; bonding a second substrate structure to said insulator to form a laminated structure having a first substrate with a first crystalline orientation below said insulator, and a second substrate with a second crystalline orientation above said insulator; forming first openings in said second substrate down to said insulator; forming second openings in said insulator through said first openings to expose said first substrate, wherein said second openings are smaller than said first openings; growing material on said first substrate through said second openings to fill said first openings to produce a surface at the top of said laminated structure that has first portions having said first type of crystalline orientation and second portions having said second type of crystalline orientation; forming first-type transistors above said first portions of said surface; and forming second-type transistors above said second portions of said surface, wherein ones of said first portions of said surface that are formed above said second openings in said insulator comprise non-floating substrate portions, and wherein remaining ones of said first portions and all of said second portions of said surface comprise floating substrate portions.