Patent ID: 6303993
Filing Date: 2001-10-16
Classification: G01R,H05K

Abstract:
A plate for receiving a plurality of contact bumps on a semiconductor die during the testing thereof, said bump comprising:a bump plate integrally formed in a semiconductor substrate, said bump plate having a plurality of contact bump receiving sites formed in said semiconductor substrate bump plate corresponding to a pattern of said plurality of contact bumps on said semiconductor die during said testing thereof, at least one of said plurality of contact bump receiving sites having a plurality of sidewalls and having a plurality of conductive traces located on at least portions of said plurality of sidewalls of said at least one contact bump receiving site for contact said plurality of conductive traces on said substrate and for contacting with a corresponding contact bump of said plurality of contact bumps received at said at least one contact bump receiving site, said plurality of conductive traces forming an array of rows and columns interconnecting each contact bump receiving site to at least one adjacent contact bump receiving site.