Patent ID: 6387814
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method of fabricating a stringerless flash memory, the method comprising:forming a silicon oxide layer on a surface of a semiconductor substrate; forming a plurality of rows of layer stacks on the silicon oxide layer, a shallow trench being formed between two adjacent layer stacks, each layer stack comprising a polysilicon layer and a sacrificial layer, each side wall of the layer stack intersecting the bottom of the shallow trench at an angle of approximately between 88 and 92 degrees; depositing a high density plasma chemical vapor deposition (HDPCVD) silicon oxide layer to cover the layer stacks and the shallow trenches; planarizing the HDPCVD silicon oxide layer to expose the sacrificial layer; removing the sacrificial layer; forming an insulating layer and a word line layer on the polysilicon layer, respectively; forming a photoresist layer on the word line layer, the photoresist layer defining a position for forming a word line; performing a first etching process to remove portions of the word line layer not covered by the photoresist layer, the first etching process having a first selectivity of polysilicon to silicon oxide; performing a second etching process to remove portions of the insulating layer not covered by the photoresist layer, the second etching process having a second selectivity of polysilicon to silicon oxide; and performing a third etching process to etch the polysilicon layer, the third etching process having a third selectivity of polysilicon to silicon oxide.