Patent ID: 8486823
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A through via process, comprising: providing a semiconductor substrate, comprising: an integrated circuit (IC) component formed on said semiconductor substrate; an interlayer dielectric (ILD) layer formed on said semiconductor substrate and covering said IC component, and a contact plug formed in said ILD layer and electrically connected to said IC component; forming at least one via hole subsequent to the contact plug formation, said via hole extending through said ILD layer and a portion of said semiconductor substrate; depositing a passivation layer lining the bottom and sidewalls of said via hole; after depositing said passivation layer, depositing a conductive material layer on said ILD layer to fill said via hole; removing said conductive material layer outside the via hole to expose said conductive material layer and the top of said contact plug, wherein said conductive material layer remaining in said via hole forms a via plug; removing a portion of the passivation layer after the conductive material layer is deposited; and after removing the portion of the passivation layer, forming an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of said interconnection structure is electrically connected to the exposed portions of said contact plug and said via plug.