Patent ID: 6599680
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A method for forming a cells array of mask read only memory, comprising:forming a first dielectric layer on a substrate; forming a first polysilicon layer on said first dielectric layer; forming a second dielectric layer on said first polysilicon layer; performing a first pattern transform process, wherein said first dielectric layer is used as an etch stop layer, part of said second dielectric layer and part of said first polysilicon layer being removed to form a plurality of gate structures; doping by using said gate structures as a mask to form a plurality of doped regions in said substrate and then forming a plurality of spacers on the sidewalls of said gate structures, such that the sidewall of each said gate structure is surrounded by one said spacer, wherein forming order of said doped regions and said spacers are exchangeable; forming a second polysilicon layer on said substrate, said second polysilicon layer covering the exposed part of said substrate which is not covered by said gate structures or said spacers, wherein said gate structures are not covered by said second polysilicon layer; treating said second polysilicon by an oxidation process such that a silicon oxide layer is formed on said second polysilicon layer; removing said second dielectric layer; forming a third polysilicon layer over said substrate, said third polysilicon layer conformally covering said silicon oxide layer, said spacers and residual said first polysilicon layers; forming a third dielectric layer on said third polysilicon layer; performing a second pattern transform process, such that said third polysilicon layer and residual said first polysilicon layer are transferred into a plurality of conductor lines for word lines; forming a fourth dielectric layer on part of said substrate that is not covered by residual said first polysilicon layer, said second polysilicon layer or said spacers, wherein thickness of said fourth dielectric layer is essentially equal to the summation of thickness of said first polysilicon layer, thickness of said third polysilicon layer and said third dielectric layer; removing said third dielectric layer; forming a metal silicide layer on said third polysilicon layer; forming a code photoresist over said substrate, wherein said code photoresist covers part of residual said first polysilicon; and performing an ions implantation process, such that a plurality of ions are implanted into part of said substrate which is not under said code photoresist.