Patent ID: 6910123
Filing Date: 2005-06-21
Classification: G06F

Abstract:
1. A processor having a changeable architected state, comprising: instruction memory for storing instructions; an instruction pipeline, wherein an instruction which passes entirely through the pipeline alters the architected state and wherein the pipeline comprises circuitry for fetching instructions from the instruction memory into the pipeline; an annul word memory for storing an annul code having a plurality of annul bits, each annul bit having a one-to-one correspondence to one instruction of a group of instructions in the pipeline; and circuitry for preventing one or more selected instructions in the group from altering the architected state in response to the corresponding annul bit of the annul code; wherein the instruction pipeline further comprises a plurality of execution units; wherein the plurality of execution units are operable such that in a given clock cycle an integer number N of the plurality of execution units are scheduled to execute; wherein the circuitry for preventing one or more selected instructions in the group from altering the architected state comprises circuitry for coupling annul bits to respective ones of the plurality of execution units; and wherein the circuitry for coupling the annul bits to respective ones of the plurality of execution units comprises circuitry for coupling only the integer number N of the annul bits to the plurality of execution units which are scheduled to execute in the given clock cycle whereby on an immediately following clock cycle annul bits beginning at an N+1 annul bit are coupled to execution units scheduled to execute of that following cycle.