Patent ID: 7208373
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A method of forming a memory cell array, comprising: providing a semiconductor substrate having a surface; providing a plurality of insulation grooves in said semiconductor substrate, providing a plurality of isolation trenches in said semiconductor substrate, said isolation trenches extending in a first direction, thereby defining a plurality of active areas, each of said active areas being delimited by two isolation trenches along a second direction perpendicular to said first direction, and each of said active areas being delimited by two insulation grooves along said first direction, each of said active areas having a width w and a length l, said width w being measured along said second direction, and said length l being measured along said first direction; providing an insulating material in each of said isolation trenches and in an upper portion of said insulation grooves; providing at least one transistor in each of said active areas, by providing a first and a second source/drain regions, forming a channel which is disposed between said first and second source/drain regions and providing a gate electrode for controlling an electrical current flow between said first and second source/drain regions; providing a plurality of storage capacitors comprising a first and a second capacitor electrodes as well as a capacitor dielectric disposed between said first and second capacitor electrodes; connecting said first source/drain region of one of said transistors with a corresponding one of said second capacitor electrodes; wherein providing a gate electrode comprises etching the insulating material in the isolation trenches at a portion adjacent to the channel so that a portion of said channel is uncovered, said portion having the shape of ridge comprising a top side and two lateral sides wherein providing a gate electrode does not comprise recessing an upper surface portion of the substrate material; providing a gate insulating layer on said top side and said two lateral sides; and providing a conducting material on said gate insulating layer so that as a result said gate electrode is disposed along said top side and said two lateral sides of the channel, wherein said step of etching said insulating material in said isolation trenches is performed as a step in which said insulating material is locally etched, wherein said insulating material in said upper portion of said insulation grooves is maintained.