Patent ID: 8871589
Filing Date: 2014-10-28
Classification: H01L

Abstract:
1. A method of forming a semiconductor construction, comprising: patterning a semiconductor material to form a plurality of linear segments of the semiconductor material extending upwardly from a base of the semiconductor material, the segments being spaced from one another by intervening trenches; individual linear segments comprising sidewall surfaces; forming protective material along the sidewall surfaces; while the protective material is along the sidewall surfaces, etching into the base to form cavities under the linear segments; forming metal-containing lines within the cavities; patterning each of the linear segments into a plurality of vertically-oriented transistor pedestals; the transistor pedestals extending upwardly from the metal-containing lines; the transistor pedestals forming an array comprising rows and columns; the metal-containing lines extending along columns of the array to interconnect transistor pedestals along said columns, and the metal-containing lines thus being incorporated into digit lines; the digit lines only comprising metal-containing materials; and forming access lines extending along rows of the array to interconnect transistor pedestals along said rows.