Patent ID: 8546241
Filing Date: 2013-10-01
Classification: H01L

Abstract:
1. A method for forming a semiconductor device with stress trench isolation, comprising: providing a silicon substrate; forming first trenches and second trenches on the silicon substrate, wherein an extension direction of the first trenches is perpendicular to that of the second trenches; forming a first dielectric layer, which is under tensile stress, in the first trenches and forming a second dielectric layer in the second trenches; and forming a gate stack on a portion of the silicon substrate surrounded by the first trenches and the second trenches, wherein a channel length direction under the gate stack is parallel to the extension direction of the first trenches, the silicon substrate has {100} crystal indices, and the extension direction of the first trenches is along <110>crystal orientation; and wherein the semiconductor device comprises at least one NMOS transistor and at least one PMOS transistor; wherein a tensile strain in a channel width direction for both NMOS and PMOS is formed by the first dielectric layer under tensile stress, which is filled the first trenches in parallel to the channel length direction; channel regions of the NMOS and the PMOS are both under the tensile strain in the channel width direction; and the channel length direction of the NMOS and the channel length direction of the PMOS are both parallel to the extension direction of the first trenches.