Patent ID: 6171914
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method of simultaneously fabricating source/drain regions and LDD regions in the fabrication of an integrated circuit device comprising:forming a gate electrode in an active area on the surface of a semiconductor substrate;covering said gate electrode and said semiconductor substrate with a resist layer;exposing said resist layer in said active area wherein a portion of said resist layer overlying planned said LDD regions is exposed to a first dosage/energy and portion of said resist layer overlying planned said source/drain regions is exposed to a second dosage/energy and wherein a portion of said resist layer outside of said active area is not exposed;developing said resist layer to leave a resist mask having a first thickness in areas not exposed and to leave a resist mask having a second thickness in areas exposed to said first dosage/energy and to leave no resist mask in areas exposed to said second dosage/energy; andimplanting ions into said semiconductor substrate adjacent to said gate electrode wherein said ions implanted through no resist mask form said source/drain regions and wherein said ions implanted through said resist mask having said second thickness form said LDD regions to complete said simultaneous fabrication of said source/drain regions and said LDD regions in the fabrication of an integrated circuit device.