Patent ID: 6678780
Filing Date: 2004-01-13
Classification: G06F

Abstract:
A circuit, comprising:an AGP bus, wherein the AGP bus is adapted to couple to an AGP port of a bus interface circuit, wherein the AGP bus supports AGP and PCI protocols; an AGP bus master operably coupled to the AGP bus, wherein the AGP bus master utilizes an AGP request portion of the AGP bus to issue AGP bus master requests; and a PCI bus master operably coupled to the AGP bus, wherein the PCI bus master utilizes a PCI request portion of the AGP bus to issue PCI bus master requests wherein the bus interface circuit receives the AGP and PCI bus master requests from the AGP and PCI bus masters, respectively, and issues bus master grants in response, wherein each of the bus master grants is classified as one of an AGP grant and a PCI grant based on status signals included in the AGP bus and the AGP bus master is configured to have an AGP identification select that differs from a PCI identification select of the PCI bus master.