Patent ID: 6038350
Filing Date: 2000-03-14
Classification: G06F,H04N

Abstract:
An apparatus for processing input digital data, said apparatus comprising:a first processor block comprising;(a) an input serial access memory unit for receiving an input digital data signal,(b) a first data memory unit for receiving the input data signal from said input serial access memory unit, and(c) a first one-dimensional array of arithmetic logic units for receiving said input data signal from said first data memory, processing said input data signal and outputting a processed data signal;a second processor block comprising;(i) a second data memory unit for receiving said processed data signal from said first array of logic units,(ii) a second one-dimensional array of arithmetic logic units for receiving said processed data signal from said second memory unit, and(iii) an output serial access memory unit for receiving said processed signal from said second array of logic units and for outputting said processed signal.