Patent ID: 6387796
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:providing a semiconductor chip having a top surface and a bottom Surface opposite the top surface, wherein the top surface includes a circuit formation area and an electrode formation area, wherein the circuit formation area includes an integrated circuit, and wherein the electrode formation area includes a plurality of pad electrodes, said plurality of pad electrodes including a first pad electrode having a potential level applied thereto and a second pad electrode which receives a signal; forming a first insulation layer on the circuit formation area; forming a first Circuit pattern on the first insulation layer; forming a second insulation layer on the first circuit pattern having a first through hole for exposing the first circuit pattern; forming a second circuit pattern on the second insulation layer having a second through hole for exposing the first circuit pattern; connecting the first circuit pattern to the first pad electrode and the second circuit pattern to the second pad electrode; and forming a plurality of first external electrodes electrically connected to said second circuit pattern and a plurality of second external electrodes electrically connected to said first circuit pattern through the first and second through holes.