Patent ID: 7770087
Filing Date: 2010-08-03
Classification: H03M,H04L

Abstract:
1. A serial concatenated convolutional code decoder, comprising: at least one processing loop module comprising a permutation module, an inner decoder module, a depermutation module, and an outer decoder module; and wherein said inner decoder module is subdivided into a plurality of inner decoding engines configured for concurrently performing a decoding operation based on an inner convolutional code means for communicating each of a plurality of codeblock segments comprising a different selected portion of a codeblock, in parallel, to a respective one of said plurality of inner decoding engines; wherein each of said plurality of codeblock segments is comprised of at least one overlap bit portion and a non-overlap bit portion, said overlap bit portion comprising soft-decision bits included within two or more codeblock segments, and said non-overlap bits portion comprising soft-decision bits included within a single codeblock segment.