Patent ID: 6356927
Filing Date: 2002-03-12
Classification: G06F

Abstract:
A rounding unit for use in connection with a floating point processor, the floating point processor generating a result floating point value representing as elected arithmetic operation applied to at least one input floating point value, the result floating point value comprising an exponent field and a fraction field, the fraction field comprising a plurality of digit locations each having at least one digit, the rounding unit being configured to receive the result floating point value from the floating point process and generate therefrom a rounded result floating point value, the rounding unit comprising:A. a rounding position mask generator configured to generate a rounding position mask from an exponent value in the exponent field, the rounding position mask identifying one of the digit locations of the fraction field at which a correction value is to be applied; B. a result mask generator configured to generate a result mask, the result mask identifying the digit location of the fraction field at which the correction value is to be applied, as well as at least some of the digit locations that are more significant ones thereof; C. a rounded value generator configured to generate the correction value and generate the rounded floating point value in relation to the correction value, the rounding position mask and the result mask.