Patent ID: 7435621
Filing Date: 2008-10-14
Classification: H01L

Abstract:
1. A method of fabricating wafer level package, comprising: providing a wafer having a front surface and a rear surface; forming a plurality of fosses on the front surface of the wafer; forming an insulating layer on a surface of each fosse; forming a conductive layer on part of the front surface of the wafer and the insulating layer of each fosse; forming a solder layer on the conductive layer above each fosse; attaching a first substrate to the front surface of the wafer; forming a plurality of holes on the rear surface of the wafer, and the holes positioned corresponding to the fosses, and each hole baring the solder layer; attaching a second substrate to the rear surface of the wafer, and the second substrate having a plurality of conductive pillars correspondingly inserted into the holes for connecting the solder layers; and forming a plurality of conductive structures on the second substrate.