Patent ID: 6788609
Filing Date: 2004-09-07
Classification: G06F,G11C

Abstract:
A storage device employing a flash memory which is divided into a plurality of physical sectors identified by physical addresses, wherein said flash memory carries out a write operation of a write data into a selected one of said plurality of physical sectors in response to a logical address accompanied with said write data from a host system, said storage device including:a memory controller which generates a physical address in response to said host logical address for said data write operation of said write data from said host system, wherein said memory controller carries out a physical address calculation, using a preceding value related to a preceding physical address for a preceding data write operation and using a modifying value for a current data write operation, and said memory controller generates a current physical address for said current data write operation based upon said physical address calculation, and wherein said memory controller carries out said preceding data write operation in which a preceding write data from said host system is written into said selected one of said plurality of physical sectors identified by said preceding physical address generated from a preceding host logical address, and said memory controller carries out said current data write operation in which a current write data from said host system is written into another selected sector of said plurality of physical sectors identified by said current physical address generated from a current host logical address that is identical to said preceding host logical address.