Patent ID: 8255440
Filing Date: 2012-08-28
Classification: H03K,H03M

Abstract:
1. A method comprising: identifying a size of a programmable chip lookup table (LUT); identifying a plurality of main equations, wherein the plurality of main equations are Exclusive OR (XOR) expressions; generating, by using a processor configured to generate centroids, a plurality of centroids including a first centroid, wherein the plurality of centroids are randomly generated, wherein the first centroid has a weight corresponding to the size of the programmable chip lookup table (LUT) maintained in memory coupled to the processor; associating, by using the processor, the first centroid with a first subset of the plurality of main equations based on a distance between the first centroid and each equation of the first subset of the plurality of main equations, wherein the distance is a difference between number of bit positions in a vector associated with said each equation of the first subset of the plurality of main equations and number of bit positions in a vector associated with the first centroid, wherein a main equation is associated with one of the plurality of centroids having the most common bit positions; and modifying the first centroid to form a modified first centroid, wherein the modified first centroid has a higher number of common bit positions with the first subset of the plurality of main equations than the first centroid.