Patent ID: 9148572
Filing Date: 2015-09-29
Classification: H04N

Abstract:
1. A timing generator of an imaging device, comprising: a clock division circuit configured to output dot clocks in a first cycle to a display which includes a counter being configured to count the number of the dot clocks being output for a synchronization period which is a display cycle for a display line, the dot clocks corresponding to a synchronization signal being used when an image is displayed on the display; and a display control section configured to determine whether or not the number of the dot clocks in the synchronization period is expected to exceed a maximum value of the counter, length of the synchronization period being based on at least a frame rate of an image sensor configured to output image data indicating the image of an object, the display control section including a selector element being configured to switch from the first cycle to a second cycle which is longer than the first cycle, if the number of dot clocks in the synchronization period is expected to exceed the maximum value of the counter.