Patent ID: 6445215
Filing Date: 2002-09-03
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising a decoder circuit provided on a chip, said decoder circuit having an array of a plurality of logic circuits performing a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of states of a plurality of externally inputted binary signals, each of said logic circuits comprising:at least a first transistor means having a drain; and at least a second transistor having a gate receiving a first input signal and a drain forming a common node with said drain of said first transistor means, said second transistor comprising a MOS field-effect transistor, said MOS field-effect transistor having a source receiving an inverse signal inverse to a second signal combined for logic operation with said first input signal inputted to said gate of said MOS field-effect transistor, said common node being an output of said logic circuit and directly connected to an inverter having a CMOS transistor structure for outputting an output signal, whereby, with said inverter, said logic circuit comprises a basic unit, said MOS field-effect transistor being arranged such that the adjacent ones of said logic circuits share a source diffusion layer.