Patent ID: 8350321
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A method of forming a semiconductor having a saddle fin transistor, the method comprising: forming an isolation layer defining an active region; forming an elevated region by etching a first gate recess to a first depth in the isolation layer and a second gate recess to a second depth in the active region; forming a first trench and a second trench by etching the first and second gate recesses to a third depth and a fourth depth, respectively; filling the trenches with conductive material to form gate electrodes; and forming a landing contact plug on the elevated region, wherein a width of the first trench is narrower than a width of the first gate recess and a width of the second trench is narrower than a width of the second recess, and either of the third and fourth depths are greater than either of the first and second depths.