Patent ID: 6680243
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A method for forming shallow junctions in an integrated circuit in a substrate comprising:masking the substrate with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate, prior to formation of a gate electrode layer, implanting a first dopant substantially within a first depth zone through the second portions of the substrate, where the first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth, substantially removing the first mask from the substrate, annealing the substrate for a first time to form a noncontiguous buried insulating layer substantially within the first depth zone in the second portions of the substrate, forming a gate electrode layer on the substrate masking the substrate with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate, where the fourth portions of the substrate at least partially overlap the second portions of the substrate, implanting a second dopant substantially within a second depth zone through the fourth portions of the substrate, where the second depth zone extends from an upper surface of the substrate to the first depth, and annealing the substrate for a second time to activate the shallow junctions formed substantially within the second depth zone in the fourth portions of the substrate, where the shallow junctions have a depth that is substantially limited by the noncontiguous buried insulating layer that starts at the first depth.