Patent ID: 6215159
Filing Date: 2001-04-10
Classification: G05F,H03K

Abstract:
A semiconducter integrated circuit device comprising:a first logic circuit comprised of MOS transistors having a first threshold voltage lower than a potential of a first power supply line; anda P-channel MOS transistor having a second threshold value, an absolute value of the second threshold value being larger than an absolute value of the first threshold voltage,wherein a first node connected to a virtual power supply line of the first logic circuit is connected to a drain of the P-channel MOS transistor, and wherein the first power supply line is connected to a source of the P-channel MOS transistor, and a signal in which low level indicates a voltage lower than a potential of the ground line and high level indicates a voltage equal to the potential of the first power supply line is applied to the gate of the P-channel MOS transistor, whereby the P-channel MOS transistor is caused to undergo ON/OFF control.