Patent ID: 8028212
Filing Date: 2011-09-27
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. logic circuitry; B. parallel scan paths coupled to the logic circuitry, each scan path having a scan input and a scan output; C. stimulus data circuitry having a serial input, control inputs, a serial output, and parallel outputs coupled with the scan inputs of the parallel scan paths; D. header data circuitry having a serial input connected with the serial output of the stimulus data circuitry, control inputs, and a command output; E. response data circuitry having parallel inputs coupled with the scan outputs, control inputs, a serial input, and a serial output; F. header return circuitry having an input connected with the command output of the header data circuitry, control inputs, and a serial output connected with the serial input of the response data circuitry; and G. controller circuitry having control outputs connected with the control inputs of the scan paths, the stimulus data circuitry, the header data circuitry, the response data circuitry, and the header return circuitry, a clock input, and a command input connected with the command output of the header data circuitry.