Patent ID: 7763507
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A method, comprising: conformally depositing a first stress-inducing dielectric layer above a first plurality of gate electrode structures and a second plurality of gate electrode structures of a semiconductor device, said first and second gate electrode structures being at least partially formed above a semiconductor layer; forming an etch control layer on said first stress-inducing layer using a non-conformal deposition process so as to obtain a specified fill height of said first stress-inducing layer and said etch control layer in a space between adjacent two of said gate electrode structures, said specified fill height corresponding to at least one half of a height of said first and second pluralities of gate electrode structures; selectively removing said etch control layer and first stress-inducing layer from above said second plurality of gate electrode structures; depositing a second stress-inducing dielectric layer above said etch control layer and said first stress-inducing layer and said second plurality of gate electrode structures; and selectively removing said second stress inducing layer from above said first stress-inducing layer by performing an etch process and using said etch control layer as an etch stop.