Patent ID: 6144227
Filing Date: 2000-11-07
Classification: H03K

Abstract:
An MOS logic circuit, comprising:a plurality of N-type DTMOS transistors for performing logic operations, each having a threshold voltage;a plurality of P-type DTMOS transistors for performing logic operations, each having a threshold voltage; andan inverter connected to outputs of said plurality of N-type and P-type DTMOS transistors, said inverter including an N-type MOS transistor and a P-type MOS transistor,wherein an absolute value of a threshold voltage of said P-type DTMOS transistor is larger than an absolute value of a threshold voltage of said N-type MOS transistor to prevent leakage of a stationary penetrating current through said inverter, orwherein an absolute value of a threshold voltage of said N-type DTMOS transistor is larger than an absolute value of a threshold voltage of said P-type MOS transistor to prevent leakage of a stationary penetrating current through said inverter.