Patent ID: 6869809
Filing Date: 2005-03-22
Classification: H01L

Abstract:
1. A wafer level testing and bumping process, wherein the wafer has an active surface and at least a fuse line buried inside the wafer, the process comprising the steps of: forming at least a flip-chip bonding pad and at least a test pad on the active surface such that the test pads are positioned at a peripheral section of the active surface and are electrically connected to the flip-chip bonding pad; forming at least a fuse window on the active surface such that the upper surface of the fuse window is at a level below the active surface for decreasing the thickness of the structure above the fuse line; testing the wafer electrically through the test pad to obtain a plurality of test results; after testing the wafer, determining whether or not to cut the fuse line by shining a laser beam through the fuse window according to the test results; after the step of determining whether or not to cut the fuse line, forming a patterned passivation layer over the active surface of the wafer, wherein the passivation layer fills the fuse window and covers the test pad but exposes the flip-chip bonding pad; and attaching a bump to the flip-chip bonding pad.