Patent ID: 9136835
Filing Date: 2015-09-15
Classification: H03K

Abstract:
1. A switch circuit comprising: a transmission unit configured to transmit a signal through a single transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the single transistor to a fixed potential when the single transistor is turned OFF, and to separate the back gate of the single transistor from the fixed potential when the single transistor is turned ON, wherein the source of the single transistor is connected to an input terminal of the transmission unit, and the drain of the single transistor is connected to an output terminal of the transmission unit, wherein a value of the resistor is set so that a parasitic capacitance of the back gate is ignorable on a transmission path of the signal, wherein the transmission unit includes a second resistor connected between a back gate and a source of the first N-channel transistor, and the back gate control unit includes wherein the source of the first P-channel transistor and the source of the first N-channel transistor are connected to an input terminal of the transmission unit, and the drain of the first P-channel transistor and the drain of the first N-channel transistor are connected to an output terminal of the transmission unit, and wherein the enable signal is input to the gate of the first P-channel transistor and the gate of the second N-channel transistor; and a signal, in which the enable signal is inverted, is input to the gate of the second P-channel transistor and the gate of the first N-channel transistor, and further comprising an inverter configured to invert the enable signal, and a level shifter, arranged at a pre-stage of the inverter and configured to convert amplitude of a control signal that controls the back gate control unit.