Patent ID: 7501874
Filing Date: 2009-03-10
Classification: H03K

Abstract:
1. A level shift circuit comprising: a first current path and a second current path disposed in parallel to a supply having a first voltage amplitude and respectively connected in series to a first transistor of a first polarity and a second transistor of the first polarity and a third transistor of a second polarity; a connection point connecting the second transistor and the third transistor in the first current path connected to a control terminal of the first transistor of the second current path and a connection point connecting the second transistor and the third transistor in the second current path connected to a control terminal of the first transistor of the first current path; an input signal having a second voltage amplitude smaller than the first voltage amplitude respectively input by a control terminal of the second transistor of the first current path and a control terminal of the second transistor of the second current path; the second voltage amplitude of the input signal level shifted to the first voltage amplitude and output from the connection point connecting the second transistor and the third transistor in the first current path or the second current path; and an input voltage converter circuit wherein the input signal undergoes voltage conversion and a converted signal is respectively supplied to a control terminal of the third transistor of the first current path and the second current path; the input voltage converter circuit adds an offset voltage corresponding to a threshold of the third transistor with respect to the second voltage amplitude; wherein the input voltage converter circuit connects in series a fourth transistor of the first polarity and a fifth transistor of the second polarity, which are both voltage driven, between a terminal to which one of two voltages forming the second voltage amplitude is applied and a terminal to which the input signal is applied; the fourth transistor has a threshold identical to a threshold of the second transistor and a gate terminal and a drain terminal thereof are mutually connected; the fifth transistor has a threshold identical to the threshold of the third transistor and a gate terminal and a drain terminal thereof are mutually connected; the gate terminal of the fourth transistor and the fifth transistor are connected to the terminal to which the input signal is applied via a common capacitor; a connection point connecting the fourth transistor and the fifth transistor is connected to the control terminal of the third transistor of the first current path or the second current path; and an output rise characteristic from a threshold of the fifth transistor is steeper than an output rise characteristic from a threshold of the fourth transistor.