Patent ID: 7175092
Filing Date: 2007-02-13
Classification: G06K,H03M

Abstract:
1. A least-significant-bit-optimized analog-to-digital converter circuit, comprising: an analog-to-digital converter having a first reference voltage input terminal, a second reference voltage input terminal, an analog data input terminal, and a digital data output terminal providing data in an N-bit representation, where N is a positive integer greater than 1; a first reference voltage source that provides a first reference voltage to said first reference voltage input terminal; a second reference voltage source that provides a second reference voltage to said second reference voltage input terminal; a detector that detects an excitation and that provides an analog signal responsive to said excitation to said analog data input terminal; and a microprocessor-based controller that controls said first reference voltage and said second reference voltage; whereby said microprocessor-based controller adjusts at least one of said first and said second reference voltages to cause N-bit range of said analog-to-digital converter to substantially span a dynamic range of said excitation as detected by said detector, thereby optimizing a value of a least-significant bit of said analog-to-digital converter with respect to said excitation.