Patent ID: 7370294
Filing Date: 2008-05-06
Classification: G06F

Abstract:
1. A computer-readable medium with computer-readable instructions written thereon for implementing a method of reducing leakage current in an integrated circuit, the method comprising: determining a block of logic gates within an integrated circuit such that all logic gates in the block are connected to a single power-gating transistor; estimating a maximum width of the power-gating transistor based on a maximum power consumption of the block of logic gates; determining a signal arrival time for each of a plurality of logic gates of the block; determining a plurality of groups of logic gates within the block according to a first grouping scheme, wherein each group is formed based on signal arrival times; determining a first reduction amount representing a maximum amount the width of the gating transistor is enabled to be reduced based on the first grouping scheme; determining a plurality of groups of logic gates within the block according to a second grouping scheme, wherein each group is formed based on signal arrival times; determining a second reduction amount representing a maximum amount the width of the gating transistor is enabled to be reduced based on the second grouping scheme; and reducing the estimated maximum width of the power-gating transistor by an amount equal to the greater of the first reduction amount or the second reduction amount.