Patent ID: 6507579
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A switching system for switching data with rate conversion between a high speed bus and a low speed bus, comprising:a) a double buffered data memory having a read-only port and a write only port; b) a plurality of registers and selectors for receiving and storing successive bytes of data in a frame from one of said high speed bus and said low speed bus into said data memory via one of said write-only port and read-only port, respectively; and c) a connection memory containing a plurality of entries each having a first bit indicating whether a data byte has been copied to said data memory from one of said registers, an additional plurality of bits identifying connection addresses for said received bytes of data; and a further plurality of index bits for addressing and reading said data memory via the other of said one of said write-only port and said read-only port in the event said first bit is set and thereafter outputting addressed data bytes to the other one of said high-speed bus and low-speed bus.