Patent ID: 9064962
Filing Date: 2015-06-23
Classification: G02F,H01L

Abstract:
1. A thin film transistor array substrate, comprising: a thin film transistor having a source electrode and a drain electrode; a first interlayer insulating film provided on the source electrode and the drain electrode, the first interlayer insulating film having a first through hole formed in a region where the drain electrode is arranged, the first through hole having a bottom that partially exposes a top surface of an underlying layer on which the drain electrode is formed; a first common electrode disposed on a part of the first interlayer insulating film and a second common electrode disposed within the first through hole; a second interlayer insulating film provided on the first interlayer insulating film and the first and second common electrodes, the second interlayer insulating film having a second through hole formed within a region where the first through hole is arranged; and an upper layer electrode provided on the second interlayer insulating film and in the second through hole, wherein the drain electrode has a portion covered by the first interlayer insulating film, and a portion that is in contact with the second common electrode within the first through hole, and wherein the second common electrode within the first through hole is in contact with a portion of the upper layer electrode arranged in the second through hole, and is also in contact with the top surface of the underlying layer that is partially exposed at the bottom of the first through hole.