Patent ID: 6778966
Filing Date: 2004-08-17
Classification: G10L,H03G,H04R

Abstract:
A segmented mapping converter comprising a plurality of first tier data inputs, a command enable input, a plurality of first tier segment transform processors each including a segment selection processor, responsive to an associated one of the first tier data inputs and the command enable input, which establishes an associated output set comprising a coefficient set and a value-of-a-variable set in accordance with the value of the associated first tier data input and the command enable input, and a transform processor, responsive to the output set, which establishes a corresponding first tier output value, first tier select or combine logic responsive to the plurality of first tier output values established by the plurality of first tier segment transform processors for establishing a first tier select/combine output signal, first test logic for examining the first tier select/combine output signal and, in response thereto, providing a data output or providing a first command enable signal for further calculation, a second tier segment transform processor including a segment selection processor, responsive to a second tier data input and the first command enable signal, which establishes an output set comprising a coefficient set and a value-of-a-variable set in accordance with the second data input and the first command enable signal, and a transform processor, responsive to the output set, which establishes a corresponding second output value, and second test logic for examining the second output value and, in response there, providing a data output or providing an enable signal for further calculation.