Patent ID: 6782522
Filing Date: 2004-08-24
Classification: H01L,H05K

Abstract:
A semiconductor device in which a semiconductor electronic part having connecting terminals in a checkered pattern is solder-mounted on a multilayer circuit board having wiring patterns and lands, the semiconductor device comprising:first wiring patterns forming a part of the wiring patterns; first lands forming a part of the lands and linked with the first wiring patterns; first terminals forming a part of the connecting terminals and connectable with the first lands; second wiring patterns forming a part of the wiring patterns and wider an the first wiring patterns; second lands forming a part of the lands and linked with the second wiring patterns; and second terminals forming a part of the connecting terminals connectable with the second lands, wherein two adjoining lands are spaced from each other to allow only one of the first wiring patterns to pass through, the second lands are formed in at least the first outermost line of at least the first uppermost layer of the multilayer circuit board, the second terminals are allocated in at least the first outermost line among the connecting terminals, and wherein no second land is formed in the second outermost line of the first uppermost layer of the multilayer circuit board.