Patent ID: 6465838
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A structure of flash memory, comprising:a substrate; a plurality of device isolation structures, distributed into a plurality of regions of device isolation structures in the substrate, wherein the device isolation structures from two regions do not intersect with one another; a plurality of strip-shaped sources, wherein each strip-shaped source is provided in the substrate between each region of device isolation structures; a plurality of tunneling oxide layers, covering the substrate where the sources are located; a plurality of groups of block-shaped drains, wherein each block-shaped drain is provided in the substrate at a location exposed by the tunneling oxide layers between two device isolation structures of one region of device isolation structures; a plurality of groups of polysilicon blocks, each group of polysilicon blocks comprises a plurality of polysilicon blocks that do not intersect with one another, each polysilicon block being placed on one tunneling oxide layer and overlapping two neighboring device isolation structures of one region of device isolation structures so as to form a floating gate; a plurality of silicon oxide cap layers located on the polysilicon blocks, respectively; a plurality of first silicon oxide layers formed on sidewalls of each group of polysilicon blocks, respectively; a plurality of first polysilicon layers respectively formed on the first silicon oxide layers over the respective sidewalls of each group of polysilicon blocks to connect the polysilicon blocks of each group of polysilicon blocks to one another, the first polysilicon layers operating as control gates for bit lines; a plurality of second silicon oxide layers covering surfaces of the first polysilicon layers, respectively; a plurality of second polysilicon layers respectively located on the tunneling silicon oxide layers above the sources, and covering a part of the silicon oxide cap layers, the second polysilicon layers operating as erasure gates; a dielectric layer over the substrate; a plurality of groups of plugs, each group of plugs including a plurality of plugs, each group of plugs electrically connecting to each group of drains correspondingly; and a plurality of conductive lines provided on the dielectric layer, wherein the conductive lines do not intersect with one another, and each of the conductive lines is electrically connected to one group of plugs at an upper end of one plug thereof, the conductive lines operating as bit lines.