Patent ID: 7381986
Filing Date: 2008-06-03
Classification: G01R,H01L

Abstract:
1. A semiconductor wafer, comprising: a semiconductor substrate; a plurality of integrated circuit chips formed in said substrate; said plurality of integrated circuit chips being formed in said semiconductor substrate to create a plurality of rows separated one row from another by a respective row kerf there between and a plurality of columns separated one column row from another by a respective column kerf; first, second, third and fourth tester interface circuits formed on said substrate; said first and said second tester interface circuit being coupled to each of said integrated circuit chips formed in said semiconductor substrate through first and second respective wiring paths located in said row kerfs; said third and said fourth tester interface circuit being coupled to each of said integrated circuit chips formed in said semiconductor substrate through third and fourth respective wiring paths located in said column kerfs; and each of said wiring paths having a plurality of distinct stimulus busses in each respective kerf area for providing each integrated circuit chip coupled thereto with power, parallel serial scan data, clock, control, chip enable data enable signals; and an output means for obtaining the response of said integrated circuit chips to such inputs.