Patent ID: 8153472
Filing Date: 2012-04-10
Classification: H01L,H05K

Abstract:
1. An embedded chip package process, comprising: providing a first substrate, wherein the first substrate has a first patterned circuit layer thereon and the first patterned circuit layer has at least a first bonding pad, and a first chip is disposed on the first bonding pad and electrically connected to the first patterned circuit layer by performing a flip-chip bonding process; providing a second substrate, wherein the second substrate has a second patterned circuit layer thereon and the second patterned circuit layer has at least a second bonding pad; covering a dielectric material layer over the first patterned circuit layer and the first chip; performing a compression process to cover the second substrate over the dielectric material layer and embed the second patterned circuit layer of the second substrate into the dielectric material layer; performing a curing process to cure the dielectric material layer after the step of performing the compression process; forming at least a conductive plug through the dielectric material layer to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process; and removing the first substrate, the second substrate and a portion of the at least a conductive plug after the step of forming the conductive plug.