Patent ID: 7251715
Filing Date: 2007-07-31
Classification: G11C

Abstract:
1. A double data rate memory device, comprising: a first memory array; a second memory array; a mux control adapted to receive control signals; a first pipeline coupled to the first memory array and the second memory array, wherein the first pipeline passes data from one of the first memory array and the second memory array and through the first pipeline on a first clock edge; a second pipeline coupled to the first memory array and the second memory array, wherein the second pipeline passes data from the first memory array and the second memory array and through the second pipeline on a second clock edge; wherein the first pipeline further comprises a first data mux connected to the mux control, the first memory array and the second memory array, the first data mux being adapted to direct data from one of the first memory array and the second memory array to the first pipeline; and wherein the second pipeline further comprises a second data mux connected to the mux control, the first memory array and the second memory array, the second data mux being adapted to direct data from one of the first memory array and the second memory array to the second pipeline.