Patent ID: 8936972
Filing Date: 2015-01-20
Classification: B82Y,H01L

Abstract:
1. A method of fabricating a field effect transistor (FET) device, comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer having an SOI layer over a buried oxide (BOX), wherein the SOI layer is present between a buried nitride layer beneath the SOI layer and a nitride cap above the SOI layer; etching the SOI layer, the buried nitride layer and the nitride cap to form nanowire cores and pads in the SOI layer, wherein the pads are attached at opposite ends of the nanowire cores in a ladder-like configuration, wherein the buried nitride layer is present beneath each of the nanowire cores and the nitride cap is present on top of each of the nanowire cores, and wherein sidewalls of the nanowire cores are exposed; suspending the nanowire cores over the BOX; forming epitaxial sidewalls over the sidewalls of the nanowires cores; removing the buried nitride layer and the nitride cap from the nanowire cores; and forming a gate stack that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls, wherein the portions of the nanowire cores and the epitaxial sidewalls surrounded by the gate stack serve as channels of the device, wherein the pads and portions of the nanowire cores and the epitaxial sidewalls that extend out from the gate stack serve as source and drain regions of the device.