Patent ID: 8581260
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A semiconductor device comprising: a memory including a memory cell array comprising a first thin film transistor and a driver circuit portion comprising a second thin film transistor, wherein the memory cell array and the driver circuit portion are provided over a substrate having an insulating surface, wherein the first thin film transistor comprises: a first gate electrode layer; a first semiconductor layer including a first source region, a first drain region, and a first channel formation region; and a first gate insulating layer, wherein the second thin film transistor comprises: a second gate electrode layer; a second semiconductor layer including a second source region, a second drain region, and a second channel formation region that is thinner than the first channel formation region; and a second gate insulating layer that is thinner than the first gate insulating layer, wherein the memory includes a booster circuit over the substrate, and wherein the booster circuit includes a third thin film transistor which includes a third gate electrode layer; a third semiconductor layer including a third source region, a third drain region, and a third channel formation region that is thicker than the second channel formation region of the second semiconductor layer; and a third gate insulating layer.