Patent ID: 7045758
Filing Date: 2006-05-16
Classification: H01L,H04N

Abstract:
1. A CMOS imaging system comprising an array of pixels arranged into rows and columns on an imaging area, the columns being divided into first and second series of columns alternating with one another such that the pixels of the columns of each series are offset by a predetermined amount from the pixels of the columns of the other series; each said column having a column amplifier FET having a source electrode and a drain electrode; at least one pair of conductors associated with the first series of columns, with the source and drain electrodes of the column amplifier FETs of the first series of columns being respectively connected thereto; at least one pair of conductors associated with the second series of columns, with the source and drain electrodes of the column amplifier FETs of the second series of columns being respectively connected thereto; first and second output amplifiers each including an additional FET and a feedback path coupled to the respective pair of conductors of the respective series of columns; and image control circuitry coupled to the pixels of said imager; wherein corresponding pixels of the first and second series of columns are diagonally offset from one another; wherein the pixels are arranged in pairs of pixel regions arranged diagonally on two sides of a pixel control region such that the pairs of pixel regions each extend diagonally defining diagonal zones between successive pairs of pixel regions of that series; and wherein the pixels of the other series of columns of pixels are situated within said diagonal zones.