Patent ID: 7502390
Filing Date: 2009-03-10
Classification: H03M,H04L

Abstract:
1. An apparatus comprising: an input circuit configured to generate a plurality of data paths in response to an input data signal having a plurality of data items sequentially presented in a first order; a storage circuit configured to store each of said data paths in a respective shift register chain; and an output circuit configured to generate an output data signal in response to each of said shift register chains, wherein (i) said output data signal presents said data items in a second order different from said first order, (ii) a first group of said shift register chains having a first number of registers is configured to have a first delay, a second group of said shift register chains having a second number of registers different from said first number of registers is configured to have a second delay and a third group of shift register chains having said second number of shift registers is configured to have said second delay, (iii) said input circuit transfers said input data to said shift register chains according to a first shift order and said output circuit reads said output data from said shift register chains according to a second shift order different from said first shift order, (iv) said configuration of said shift register chains is configured to enable said output circuit to present said data in said second order while generating a delay less than a total number of said plurality of shift register chains, and (v) said second order comprises an interleaved order.