Patent ID: 8962391
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of fabricating a packaged semiconductor device, comprising: forming a first dielectric layer on an active face of a semiconductor wafer comprising an array of semiconductor die, wherein each semiconductor die comprises a plurality of pads arranged in a pad ring around the periphery of the die on an active face of the die and wherein the first dielectric layer comprises a first region terminated on each die within the pad ring and a further region on each die between the pad ring and an edge of the die, such that an area around the pad ring on each die is clear of the first dielectric layer; forming a plurality of tracks in a conductive layer on the active face and the first dielectric layer, wherein each track on a die is connected to one of the plurality of pads and comprises a lower portion formed on one of the plurality of pads and an upper portion which is formed on the first dielectric layer and wherein at least one of the plurality of tracks comprises an upper portion which is formed on the further region of the first dielectric layer; forming a second dielectric layer over each semiconductor die, wherein the second dielectric layer is arranged to encapsulate the active face; forming a plurality of solder elements, each of the solder elements being electrically connected to an upper portion of a track; and dicing the semiconductor wafer into a plurality of packaged semiconductor devices.