Patent ID: 6301314
Filing Date: 2001-10-09
Classification: H03M

Abstract:
A Viterbi decoding apparatus comprising:a branch metric calculating circuit for calculating a branch metric on the basis of an input signal;an ACS circuit for selecting a path of high likelihood on the basis of the branch metric calculated at the branch metric calculating circuit to output a state metric;a path memory circuit for storing the selected path information obtained by the ACS circuit;a normalization circuit for normalizing the state metric outputted from the ACS circuit;a state metric memory circuit for storing the state metric normalized at the normalization circuit; anda maximum likelihood decoding judgment circuit for selecting a maximum likelihood path on the basis of memory content of the path memory circuit,wherein the normalization circuit carries out normalization processing of all state metrics on the basis of whether or not a state metric outputted from the ACS circuit is at least a set value determined in advance.