Patent ID: 6245490
Filing Date: 2001-06-12
Classification: H01L,H05K,Y10T

Abstract:
A method of manufacturing a semiconductor package, said method comprising the steps of:preparing a board which has an upper surface and a lower surface, a chip mounting area and circuit patterns at said upper surface, and metal pads at said lower surface, said circuit patterns being disposed around said chip mounting area, and said metal pads being electrically connected to said circuit patterns;providing a discrete plate of metal having a thickness;subsequently physically setting the metal plate atop said lower surface over said metal pads and attaching the metal plate over said lower surface of the board, whereby the attached metal plate covers said metal pads;with said metal plate covering said metal pads, removing by etching portions of said metal plate located to the sides of said metal pads and thereby leaving remaining portions of the metal plate on said metal pads so as to form metal patterns on said metal pads, each of the metal patterns having a top surface, a bottom surface resting on a respective one of the metal pads, and a side surface extending downwardly from the top surface to the bottom surface thereof, the metal patterns each having a height corresponding to the thickness of said metal plate;subsequently plating both the top and the side surfaces of said metal patterns, to form metal bumps, with a material that prevents the metal patterns from oxidizing and facilitates the ability of the bumps to be mounted to external electronics;attaching a semiconductor chip to the chip mounting area at the upper surface of the board;bonding the semiconductor chip to the circuit patterns with bonding wires; andencapsulating the semiconductor chip, the circuit patterns, and the bonding wires to form a package body.