Patent ID: 9021316
Filing Date: 2015-04-28
Classification: G06F,G11C

Abstract:
1. A method of detecting a fault attack in a circuit having a plurality of registers, each register identified by an address, the method comprising: storing in a memory an address present on an address bus during a write operation to one register of said plurality of registers; comparing data stored in a first register of said plurality of registers to a reference value to determine if the data stored in the first register has been modified; asserting a first alert signal if the comparison of data stored in the first register to the reference value indicates the data stored in the first register has been modified; comparing, in response to the assertion of the first alert signal, an address identifying said first register with said stored address; generating a first error signal if the comparison of the address identifying said first register to said stored address indicates the address identifying said first register is different from said stored address; comparing data stored in a second register of said plurality of registers to a second reference value to determine if the data stored in the second register has been modified; and upon a determination that the first register has been modified during the write operation and the second register has been modified during the write operation, generating a second error signal.