Patent ID: 7538020
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A chip packaging process, comprising the steps of: providing a chip having a plurality of contacts thereon; forming a protective layer on the chip, wherein the protective layer has a plurality of first openings exposing the respective contacts on the chip; forming an under-bump-metallurgy layer over the protective layer and the contacts; forming a patterned photoresist layer over the under-bump-metallurgy layer, wherein the patterned photoresist layer has a plurality of second openings located above the respective first openings; forming a plurality of bumps inside the second openings above their corresponding contacts, wherein the level of the surface of the bumps away from the protective layer is lower than the surface of the patterned photoresist layer away from the protective layer; etching the bumps to planarize the top surface of the bumps, wherein the bumps are encapsulated by the patterned photoresist layer except the top surface of the bumps; removing the patterned photoresist layer after the top surface of the bumps are planarized; removing the under-bump-metallurgy layer not covered by the bumps to form a plurality of under-bump-metallurgy pads, wherein the bumps are electrically connected to the contacts through their corresponding under-bump-metallurgy pads; providing a circuit board having a plurality of bonding pads thereon; and bonding the chip and the circuit board by providing a single conductive direction bonding film therebetween, wherein the planarized surfaces of the bumps are electrically connected to the bonding pads through the single conductive direction bonding film.