Patent ID: 6452861
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory array including a plurality of memory cells arranged in multiple rows and columns, a plurality of word lines respectively provided corresponding to said multiple rows, and a plurality of bit line pairs respectively provided corresponding to said multiple columns; a row select circuit for selecting one of said plurality of word lines according to a row address signal and for activating each memory cell corresponding to the selected word line; a column select circuit for selecting N bit line pairs (N being an integer at least 1) of said plurality of bit line pairs according to a column address signal; a write data inverting circuit for receiving externally supplied N data signals and for outputting each data signal inverted or uninverted based on a data control signal; a write circuit for writing N data signals output from said write data inverting circuit into N memory cells that are rendered active by said row select circuit via N bit line pairs selected by said column select circuit; and a plurality of address signal input terminals for inputting said row address signal and said column address signal at different timing, wherein said data control signal is input along with said column address signal using an address signal input terminal among said plurality of address signal input terminals which is not used for inputting of said column address signal.