Patent ID: 7643041
Filing Date: 2010-01-05
Classification: G09G

Abstract:
1. A display controller comprising: a grayscale clock generation section that generates a grayscale clock signal including N continuous grayscale pulses from a first grayscale pulse to an Nth grayscale pulse within a predetermined period starting from a reference timing, N being an integer greater than three; and a plurality of grayscale pulse setting registers, a first grayscale pulse setting register of the plurality of grayscale pulse setting registers setting an interval between the reference timing and a rising edge or falling edge of the first grayscale pulse of the N continuous grayscale pulses, an (i)th grayscale setting register of the plurality of grayscale setting registers setting an interval between a rising edge or a falling edge of an (i−1)th grayscale pulse of the N continuous grayscale pulses and a rising edge or a falling edge of an (i)th grayscale pulse of the N continuous grayscale pulses, the (i)th grayscale pulse following the (i−1)th grayscale pulse, i being an integer ranging from 2 to N, the reference timing being a falling edge of a disable signal that specifies a horizontal display period, the horizontal display period being a period that starts at the falling edge of the disable signal and ends at a rising edge of a next disable signal, the grayscale clock generation section supplying the grayscale clock signal to a data driver, the data driver generating a pulse width modulated signal having a pulse width that is determined based on a number of pulses of the grayscale clock signal corresponding to grayscale data, and the data driver drives a plurality of data lines based on the pulse width modulated signal.