Patent ID: 7506293
Filing Date: 2009-03-17
Classification: G06F

Abstract:
1. A computer-implemented method of creating and using a library for a static timing analysis (STA) of a circuit design, the circuit design including a plurality of sequential cells, the method comprising: generating interdependent clock-to-output delay values for a plurality of setup/hold time pairs defined by at least one of said plurality of sequential cells; identifying a subset of the plurality of setup/hold time pairs that produce a selected clock-to-output delay value in said at least one of said plurality of sequential cells; utilizing the subset of setup/hold time pairs to generate the library; and utilizing the library to perform STA on the circuit design by analyzing each sequential cell to generate an associated setup skew and an associated hold skew, and comparing the associated setup skew and associated hold skew with a selected setup/hold time pair stored in the library.