Patent ID: 8370605
Filing Date: 2013-02-05
Classification: G06F

Abstract:
1. A system, comprising: a first processor; a second processor; a first graphics processing unit for generating a first video signal; a second graphics processing unit for generating a second video signal; one or more peripheral devices; a switch matrix coupled to the first processor, the second processor, the first graphics processing unit, the second graphics processing unit, and the peripheral devices, wherein the switch matrix comprises programmable data paths between the processors, the graphics processing units, and the peripheral devices; processor-readable memory; and software encoded in the processor-readable memory, comprising: a first operating system (OS) executed by the first processor; a second OS executed by the second processor, wherein the first OS has a faster boot time than the second OS and the first processor has a faster boot time than the second processor; when the processors are booting UP, the switch matrix configures the data to couple the first processor and the graphics processing units so the first processor initially controls the graphics processing units; when the second processor has booted up, the matrix scheduling engine configures the data paths in the switch matrix to couple the second processor and the graphics processing units so the second processor takes control of the graphics processing units from the first processor; a matrix scheduling engine running on the operating systems, wherein the matrix scheduling engine configures the data paths in the switch matrix to couple the processors and the graphics processing units, to couple the processors and the peripheral devices, and when the second processor fails, configuring the data paths in the switch matrix to couple the first processor and the graphics processing units so the first processor takes control of the graphics processing units from the second processor; and a media interface switch engine running on the operating systems, wherein the media interface switch engine detects presence of the peripheral devices and configures the data paths in the switch matrix to couple the processors and the peripheral devices.