Patent ID: 6351837
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A built-in self-test (BIST) circuit for a DRAM comprising:a producer for producing a sequence of macro-instructions corresponding to a sequence of test patterns for input to said DRAM, said sequence of macro-instructions for implementing an underlying test algorithm; a scheduler for processing each individual macro-instruction in said sequence of macro-instructions into a sequence of one-hot encoded test patterns, each one-hot encoded test pattern including a memory command portion; a first-in first-out queue for synchronizing the provision of macro-instructions to said scheduler from said producer; an encoder for mapping said memory command portion of said one-hot encoded test pattern generated by said scheduler to a code defined by the DRAM; an output buffer for serving as a buffer between the BIST circuit and the DRAM; a delay buffer for delaying an expected memory response; and a comparator for comparing an output response of the DRAM with the expected memory response from said delay buffer to determine if the function of the DRAM is correct.