Patent ID: 8077363
Filing Date: 2011-12-13
Classification: H04N

Abstract:
1. A block matching circuit, comprising: a first storage area for storing scanning image data that is pixel data corresponding to each one of pixels arranged in J rows and K columns contained in a scanning area that is an image area to be subjected to comparison in block matching; a second storage area for storing target image data that is pixel data corresponding to each one of pixels arranged in M rows and N columns contained in a target area that is an image area functioning as a standard for said comparison in said block matching, J, K, M and N being integers satisfying J>M and K>N; M×N operation circuits for obtaining pixel difference values indicative of differences between corresponding pixels, said pixel difference values being obtained between comparison image data and said target image data, said comparison image data being pixel data corresponding to each one of pixels arranged in M rows and N columns contained in each one of a plurality of comparison areas that are obtained by scanning said scanning area; M×N selection circuits for selecting said comparison image data for each one of said comparison areas from said first storage area and outputting the selected comparison image data to said operation circuits; an accumulation circuit for obtaining respective cumulative totals for said comparison areas, said cumulative totals each being given by accumulating said pixel difference values; and a matching judgment section for comparing said respective cumulative totals obtained for said comparison areas to specify said comparison area providing the minimum of said cumulative totals.