Patent ID: 6677730
Filing Date: 2004-01-13
Classification: H02J,H02M

Abstract:
A solid-state pulse battery charger wherein input power from a primary source is stored as a potential charge in a capacitor bank, said capacitor bank then disconnected from said input power source through a dual timing means, said capacitor then connected to a battery to receive the potential charge, the charge then discharged into said battery from said capacitor, said battery then disconnected from said capacitor through said dual timing means, said capacitor then re-connected to said input power source completing a two phase switching cycle comprising:a. a means for providing input power; b. a means for timing a signal and a current flow in two phases, a charge phase and a discharge phase, through either a first channel output for charging said capacitor bank, or a second channel output for discharging stored energy from said capacitor into said battery, the current flowing from said first channel output through a first optical isolator and through a first NPN power transistor, said first transistor activating a first pair of N-channel MOSFETs with voltage stored as the potential charge in said capacitor bank, said capacitor disconnecting from said input power means by said timing means; c. said means for timing current flow connecting to said second channel output, current flowing from said second channel through a second optical isolator and through a second NPN power transistor, said second transistor activating a second pair of N-channel MOSFETs, said capacitor connecting to said battery, the potential charge discharging into said battery, said timing means disconnecting said capacitor from said battery, and connecting said capacitor to said power means.