Patent ID: 6597220
Filing Date: 2003-07-22
Classification: H03K

Abstract:
A semiconductor integrated circuit device comprising:a first logic circuit including MIS transistors, located on a first area of the semiconductor integrated circuit device; a second logic circuit including MIS transistors, located on a second area of the semiconductor integrated circuit device; a first monitoring circuit including MIS transistors which outputs a first oscillation signal; a second monitoring circuit including MIS transistors which outputs a second oscillation signal; a first control circuit which receives a first reference clock signal and the first oscillation signal and applies a first substrate bias voltage to MIS transistors of the first logic circuit and the first monitoring circuit according to a first difference between the first reference clock signal and the first oscillation signal; and a second control circuit which receives a second reference clock signal and the second oscillation signal and applies a second substrate bias voltage to MIS transistors of the second logic circuit and the second monitoring circuit according to a second difference between the second reference clock signal and the second oscillation signal; wherein the first monitoring circuit is located in close proximity to the first area and the second monitoring circuit is located close to the second area, such that the inequality of circuit characteristics of the first logic circuit and the second logic circuit due to a manufacturing process of the semiconductor integrated circuit device is reduced.