Patent ID: 9214389
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A method of forming a memory array, comprising: forming an assembly comprising an upper level over a lower level; the lower level comprising circuitry; the upper level comprising semiconductor material within a memory array region and comprising insulative material laterally outward of the semiconductor material in a region peripheral to the memory array region; forming first trenches extending into the semiconductor material; forming second trenches extending into the semiconductor material; the first and second trenches patterning a plurality of pedestals from the semiconductor material; the second trenches extending into the peripheral region; forming contact openings within the peripheral region and extending downwardly from the second trenches to the first level of circuitry; and forming conductive material within the second trenches and within the contact openings; the conductive material forming sense/access lines within the second trenches and forming electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.