Patent ID: 6348813
Filing Date: 2002-02-19
Classification: H03K

Abstract:
A global switch matrix (GSM) for use within a programmably configurable integrated circuit (IC), where the IC has a first plurality, S of segments distributed within a logic-functions providing region of the IC, where each segment has one or more logic blocks, said global switch matrix providing programmably-definable interconnection between logic blocks of different ones of said segments and said GSM comprising:(a) a second plurality, L of longlines extending across the logic-functions providing region of the IC; (b) a third plurality, F of GSM-feeding lines crossing with the longlines and extending into the logic-functions providing region for coupling GSM-feed signals to the GSM, the GSM-feed signals including logic result signals produced by logic blocks of the S segments; (c) a fourth plurality, M of programmably-controllable multiplexers each having an output port and a fifth plurality, N of input receiving points, each input receiving point being operatively coupled to a respective one of the F GSM-feeding lines, (c.1) wherein the output port of each of the programmably-controllable multiplexers can be programmably switched between a high impedance state and an active state; and (c.2) wherein respective subsets of M/L of the M multiplexers are distributively disposed along and coupled to respective ones of the L longlines.