Patent ID: 6058043
Filing Date: 2000-05-02
Classification: G11C,H01L,Y10S

Abstract:
A method of programming a nonvolatile memory cell in a chip, said cell comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, further referred to as the floating-gate channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and a program gate capacitively coupled through a dielectric layer to said floating gate, said method comprising the steps of:applying a first high voltage to said program gate thereby coupling a second positive voltage to said floating gate of said cell;applying a third low voltage to said control gate;applying a fourth voltage equal or higher than the supply voltage to said drain region of said cell; andapplying a fifth low negative voltage to the substrate;to thereby cause a current to flow from the source region of said cell towards the floating-gate channel of said cell while achieving programming of said memory cell.