Patent ID: 7396700
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A method for fabricating a thermally enhanced semiconductor device, the method comprising the steps of: preparing a support plate having an opening that penetrates through the support plate; mounting the support plate on a heat sink that covers the opening; attaching a surface of at least one semiconductor chip to the heat sink and receiving the chip in the opening of the support plate; forming an insulating layer to cover the chip and the support plate and fill in a gap between the chip and the support plate; forming a plurality of vias in the insulating layer to expose a plurality of electrode pads on the chip; forming a conductive layer on the insulating layer and the exposed electrode pads; forming a patterened resist layer on the conductive layer, with a predetermined part of the conductive layer exposed from the patterned resist layer; performing an electroplating process to deposit a patterned circuit layer on the predetermined part of the conductive layer, and the patterned circuit layer is formed with a plurality of conductive traces and conductive vias, and is electrically connected directly to the electrode pads of the chip by the conductive vias, wherein the conductive vias are disposed onto the electrode pads; and removing the resist layer and the conductive layer underneath the resist layer.