Patent ID: 6370661
Filing Date: 2002-04-09
Classification: G11C

Abstract:
An apparatus in a microprocessor for testing memory within the microprocessor, the apparatus comprising:test management logic, configured to accept test parameters from a source external to the microprocessor and to produce a specific test program using said test parameters, wherein said test management logic comprises a non-specific test program stored in a control ROM, and wherein said non-specific test program comprises a sequence of micro instructions, and wherein said sequence of micro instructions comprises a plurality of non-specific test operands, and wherein said test parameters are inserted in place of said plurality of non-specific test operands within said sequence of micro instructions to produce said specific test program, said test parameters comprising: an address data entity, for prescribing a start address for said specific test program; and a pattern data entity, for prescribing a data pattern to write to said start address; and test execution logic, coupled to said test management logic, configured to execute said specific test program.