Patent ID: 7026218
Filing Date: 2006-04-11
Classification: H01L

Abstract:
1. A method of forming a PMOS transistor comprising: forming a gate dielectric layer over a semiconductor substrate; forming a SiGe layer over the gate dielectric layer; doping the SiGe layer with indium that inhibits boron from passing through the SiGe layer and diffusing into the underlying gate dielectric layer; forming a gate electrode layer over the indium doped SiGe layer; patterning the gate electrode layer, indium doped SiGe layer and gate dielectric layer to form a gate structure; doping the patterned gate electrode layer with boron to establish a desired work function associated with the transistor; and doping exposed portions of the substrate adjacent the gate structure to form source and drain regions in the semiconductor substrate on opposite sides of the gate structure, and defining a channel region therebetween.