Patent ID: 8693278
Filing Date: 2014-04-08
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of first local bit lines; a first global bit line corresponding to the first local bit lines, the first global bit line being longer in length than the first local bit lines; a plurality first local switch control lines; a plurality of main switch control lines corresponding to the first local switch control lines, the main switch control lines being respectively longer in length than the first local switch control lines; a plurality of first hierarchical switches respectively controlling electrical connections between the first local bit lines and the first global bit line in response to potentials of the first local switch control lines; a plurality of first local switch drivers respectively driving the first local switch control lines in response to potentials of the main switch control lines; a plurality of main switch drivers respectively activating the main switch control lines selectively; a plurality of second local bit lines; a second global bit line corresponding to the second local bit lines, the second global bit line being longer in length than the second local bit lines; a plurality of second local switch control lines being longer in length than the main switch control lines; a plurality of second hierarchical switches respectively controlling electrical connections between the second local bit lines and the second global bit line in response to potentials of the second local switch control lines; and a plurality of second local switch drivers respectively driving the second local switch control lines in response to the potentials of the main switch control lines.