Patent ID: 6343043
Filing Date: 2002-01-29
Classification: G11C

Abstract:
A dynamic random access memory comprising;a plurality of blocks each provided with a plurality of word lines selected by an X address, a plurality of a bit lines and a plurality of memory cells for data storage connected to said word lines and said bit lines; a refresh decision-making circuit that detects whether or not a refresh is requested for said plurality of memory cells based upon a control signal provided from the outside and makes a decision with regard to a mode thereof; a refresh timer that is activated when the result of the decision-making performed by said refresh decision-making circuit indicate a self refresh mode to generate a timing signal; a generator that generates a counter control clock that is synchronous with said timing signal; a refresh counter that is activated when said results of said decision-making performed by said refresh decision-making circuit indicate said self refresh mode to generate and output a refresh address for a refresh in synchronization with said counter control clock; an X address buffer that stores said refresh address when said result of said decision-making performed by said refresh decision-making circuit indicates said self refresh mode and stores an X address provided from the outside when said result of said decision-making performed by said refresh decision-maldng circuit do not indicate said self refresh mode; a means for latching that latches block selection information indicating whether or not a refresh needs to be performed for the blocks provided from the outside with specific timing; an X pre-decoder that pre-decodes the address stored in said X address buffer to select the block and outputs a pre-decode signal containing said selection information; an X decoder that decodes said pre-decode signal and selects a word line corresponding to said memory cells within the block selected by said X pre-decoder; a means for operation prohibition that compares said block selection information latched by said means for latching with said refresh address and prohibits operation of said generator if said refresh address indicates a block that does not need to be refreshed; and a means for clock route changing that provides said timing signal to said refresh counter instead of said counter control clock when the operation of said generator is prohibited.