Patent ID: 8866116
Filing Date: 2014-10-21
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a substrate including a first region and a second region; a lower wiring disposed on the substrate in the first region; a wiring-insulating layer interposed between the lower wiring and the substrate; a diode disposed on the lower wiring, the diode having a seed portion and a bulk portion sequentially stacked; a variable resistance element electrically coupled to the diode; a gate electrode comprising a conductive material and disposed on the substrate in the second region, the lower wiring including substantially the same conductive material as the gate electrode; and a capping semiconductor pattern disposed on the gate electrode; and a gate insulating layer interposed between the gate electrode and the substrate, wherein the conductive material of the lower wiring connected to the diode is at a same level above the substrate as the conductive material of the gate electrode, and wherein the capping semiconductor pattern comprises substantially the same semiconductor material as a semiconductor material included in the seed portion.