Patent ID: 6437600
Filing Date: 2002-08-20
Classification: H03K

Abstract:
A synchronous memory device comprising:an array of memory cells for storing data received on a data communication line; an output driver circuit for outputting data read from the array of memory cells, the output driver circuit comprising: a push-pull output circuit comprising a pullup output transistor having a drain connected to the data communication line, and a pulldown output transistor having a drain connected to the data communication line; a first adjustable circuit connected to a source of the pullup output transistor for adjusting a resistance between the source of the pullup output transistor and a first reference voltage, the first adjustable circuit comprises a first plurality of transistors connected in parallel and each having a drain connected to the source of the pullup transistor and the first reference voltage; and a second adjustable circuit connected to a source of the pulldown output transistor for adjusting a resistance between the source of the pulldown output transistor and a second reference voltage, the second adjustable circuit comprises a second plurality of transistors connected in parallel and each having a drain connected to the source of the pulldown transistor and the second reference voltage.