Patent ID: 6925592
Filing Date: 2005-08-02
Classification: H03M

Abstract:
1. A turbo decoder comprising: a first and a second error correction decoder for error-correction decoding encoded data; an interleaver memory for storing a soft output decoded result calculated by said first decoder as an interleaver input sequence; and an interleave address generator for generating write addresses for storing said interleaver input sequence in said interleaver memory, and read addresses for randomly reading an interleaver input sequence stored in said interleaver memory, wherein said interleave address generator adds an offset to a symbol number for said interleaver input sequence for correction, and converts the corrected symbol number for said interleaver input sequence to generate the read address when an address for randomly reading the interleaver input sequence stored in said interleaver memory exceeds the number of bits resulting from a subtraction of tail bits from the number of information bits of the interleaver input sequence.