Patent ID: 6275553
Filing Date: 2001-08-14
Classification: H03L

Abstract:
A digital PLL circuit comprising:a PLL circuit comprising a reference oscillator, a voltage-controlled oscillator and a 1/N frequency divider dividing the oscillation output of said voltage-controlled oscillator by means of said 1/N frequency divider, comparing the phases of an output signal of said 1/N frequency divider and an output signal of said reference oscillator, controlling the oscillator frequency of said voltage-controlled oscillator, and extracting an oscillation output of said voltage-controlled oscillator;a signal generation circuit generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said PLL circuit but differing phase; anda phase detection circuit comprising a signal selecting circuit that is capable of selecting a signal from said signal generation circuit, a variable frequency divider circuit that divides the frequency of an output of said signal selecting circuit, said output of said signal selecting circuit being also an output of said digital PLL circuit, a phase comparator circuit that compares the phases of a reference signal and the output signal from said variable frequency divider circuit, an up/down counter that detects a difference in phase of said phase comparator circuit, a digital filter that is provided between said up/down counter and said signal selecting circuit, said phase detection circuit selecting the signal from said signal generation circuit based on the output of said up/down counter;wherein in said phase detection circuit a clock that is synchronized with the phase of said reference signal is obtained by said phase detection circuit, and said oscillation output is phase-compared N times by said PLL circuit in a time between two of said reference signals of said phase detection circuit.