Patent ID: 9190001
Filing Date: 2015-11-17
Classification: G02B,G02F,G09G,H04N

Abstract:
1. A liquid crystal display device at least comprising: a plurality of gate signal lines; a plurality of source signal lines; pixels disposed so as to correspond to intersections between the gate signal lines and the source signal lines; a gate driver that selectively outputs a gate pulse to the plurality of gate signal lines; and a control circuit that controls a pulse period of the gate pulse, wherein each of the pixels includes a plurality of sub-pixels selected through a gate signal line in an n-th line, a first control capacitor is connected between a pixel electrode of at least one sub-pixel among the plurality of sub-pixels and a common signal line through a first switching element whose gate electrode is connected to one of gate signal lines in (n+1)-th and subsequent lines, the control circuit selectively switches between a first output mode in which a pulse period of a gate pulse to be output to the gate signal line in the n-th line and a pulse period of a gate pulse to be output to the one of the gate signal lines in the (n+1)-th and subsequent lines partially overlap and a second output mode in which the pulse periods do not overlap, the number of sub-pixels per pixel is greater than or equal to three, assuming that the at least one sub-pixel among the plurality of sub-pixels is called a specific sub-pixel and a sub-pixel other than the specific sub-pixel is called a normal sub-pixel, the number of normal sub-pixels is greater than or equal to two, and a pixel circuit included in each of the plurality of sub-pixels has a configuration in which a potential difference is generated between the normal sub-pixels at least in the second output mode so that the normal sub-pixels are divided into a relatively-high-luminance sub-pixel and a low-luminance sub-pixel in response to writing of a source signal through the source signal line, the normal sub-pixels include a first normal sub-pixel and a second normal sub-pixel, the first normal sub-pixel has a first holding capacitor line that, along with a first pixel electrode, forms a holding capacitor, the second normal sub-pixel has a second holding capacitor line that, along with a second pixel electrode, forms a holding capacitor, and holding capacitor control signals having opposite phases are applied to the first holding capacitor line and the second holding capacitor line in the first output mode and the second output mode so that a potential difference is generated between the first normal sub-pixel and the second normal sub-pixel.