Patent ID: 7627741
Filing Date: 2009-12-01
Classification: G06F

Abstract:
1. An instruction processing circuit comprising: an instruction source for producing successive instructions; an execution circuit having operand inputs for receiving operands selected by the instructions and a control input for controlling execution of operations applied to the operands; and an instruction decoder having an instruction input coupled to the instruction source and a control output coupled to the control input of the execution circuit, the instruction decoder being arranged to generate successive control signals at the control output under control of respective ones of the instructions, the instruction decoder comprising: wherein at least one of the freezing circuits comprises a freezing register with an input and an output, and a multiplexer with a first input coupled to the instruction source, a second input coupled to the output of the freezing register, an output coupled to the input of the freezing register and to the sub-decoding circuit that is coupled to the freezing circuit, and a control input coupled to the predecoding circuit.