Patent ID: 8597979
Filing Date: 2013-12-03
Classification: H01L,H02M,Y02B

Abstract:
1. A panel-level package technique for fabricating a plurality of small, three dimensional, active and small passive electronic component packages, comprising the steps of: a) placing a regular, initial array of a larger perimeter planar electronic component having coplanar terminals on a temporary adhesive film supported on a planar surface; b) immersing the initial array of the larger components in a liquid phase, temporary bonding material; c) curing the temporary bonding material for creating a base panel layer encapsulating and securing the initial array of the larger perimeter planar components; d) removing a top layer of the cured, temporary bonding material from the base panel layer to expose top faces of, and any coplanar terminals presented on the top faces of the initial array of the larger perimeter planar electronic component; e) placing and attaching a second smaller perimeter, planar component presenting coplanar terminals on each exposed top face of the larger perimeter coplanar components encapsulated in the base panel layer; f) forming a stand-alone solid solder pillar on each terminal of the larger component in the base panel exposed on the top face of the base panel layer outside the perimeter of each attached second smaller perimeter planar component extending upward to an elevation above any coplanar terminals on top faces of the array of attached second smaller perimeter planar component; g) immersing the solder pillars and the second smaller perimeter, planar components in a liquid phase permanent, electrically insulating, bonding material of initial array of the larger perimeter planar components encapsulated in the base panel layer; h) curing the layer of permanent, electrically insulating, bonding material panel layer of a encapsulating the array second smaller perimeter planar components and solder pillars permanently bonded to the regular array of the larger perimeter planar components held in the cured, temporary bonding material of the base panel layer; i) removing a top layer of the cured, second panel layer of permanent, electrically insulating, bonding material for (A) establishing a perimeter planar top surface, (B) exposing coplanar end faces of the solder pillars establishing via connections electrically connected to the terminals on the top faces of the larger perimeter planar components, and (C) exposing any terminal faces presented on the top surface of the second smaller perimeter planar component forming a regular array of small, three-dimensional electronic component packages encapsulated in the permanent, electrically insulating, bonding material of the second panel layer bonded to the temporary bonding material of the base panel layer; j) ablating intersecting singulation channels through the second panel layer along each side of each small, three dimensional electronic component packages, penetrating down to the top surface of the base panel layer of temporary bonding material; k) lifting the base and second planer layers of encapsulated three dimensional electronic component packages from the supporting perimeter planar surface; l) removing the temporary adhesive film from a bottom surface of the base panel layer of temporary bonding material exposing bottom faces and any coplanar terminals on the bottom faces of the initial array of the larger perimeter planar components; and m) dissolving and removing the base panel layer of temporary bonding material for singulating the three dimensional, electronic component packages permanently bonded together by the permanent, electrically insulating, bonding material.