Patent ID: 6854098
Filing Date: 2005-02-08
Classification: G06F

Abstract:
1. A method for performing technology mapping on a design that is not bounded to a particular technology, the method comprising: mapping the design to the technology and optimizing the design for the technology by iteratively: selecting from the design a candidate sub-network; identifying at least one replacement sub-network from a storage structure that stores replacement sub-networks that are bound to the technology, wherein at least some of the replacement sub-networks comprises multiple circuit elements; determining whether to replace the selected candidate sub-network with the replacement sub-network using at least one cost function; if determined to replace the selected candidate sub-network, replacing the selected candidate sub-network in the design with the replacement sub-network; and wherein, during an iteration, a first candidate sub-network is replaced in the design with a first replacement sub-network, and during another iteration, a second candidate sub-network is replaced by a second replacement sub-network, the second candidate sub-network being comprised of at least one but not all circuit elements of the first replacement sub-network.