Patent ID: 6718403
Filing Date: 2004-04-06
Classification: G06F

Abstract:
A processor suitable for use in a data processing system, comprising:first and second functional units for processing instructions executable by the processor, each functional unit being enabled to generate a direct event signal and an indirect event signal, wherein each event signal indicates the occurrence of a corresponding instruction processing event in the processor; a bus shared by the first and second functional units wherein a set of first indirect event signals is connected to the shared bus when the first functional unit is a master of the shared bus and a set of second indirect event signals is connected to the shared bus when the second functional unit is a master of the shared bus; and a performance monitor unit (PMU) including a plurality of performance monitor counters suitable for counting instruction processing events, wherein the PMU is connected to the shared bus and to the set of direct event signals such that, during any selected cycle, each direct event signal may be monitored by at least one of the counters and further wherein at least a portion of the indirect event signals associated with the functional unit that is master of the shared bus may be monitored by at least one of the counters.