Patent ID: 6667923
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A RAM data memory configured for generating predictable noise or interference related components coherent with each write cycle, essentially independent of the data content of said RAM data memory, said RAM data memory comprising:a plurality of memory cells, each of which being comprised of two sets of cross-coupled transistors wherein each of said cells is capable of holding a data bit having a â€œ1â€  or a â€œ0â€  value; a plurality of memory bytes wherein each of said bytes is comprised of a plurality of concurrently addressable memory cells; an address circuit for selectively addressing one of said memory bytes and selecting said memory byte to be read or written and thus form a portion of a read or a write cycle, respectively; write sequencing logic for removing charge from said selectively addressed cross-coupled transistors comprising said selectively addressed memory cells of said selectively addressed memory byte having an initial byte value before adding charge to said selectively addressed cross-coupled transistors of said selectively addressed memory cells of said selectively addressed byte to cause said memory byte to correspond to a desired byte value; and whereby current transitions associated with said removing and said adding of charge from said memory cells of said memory bytes are essentially independent of any relationship between said initial byte value and said desired byte value.