Patent ID: 6643807
Filing Date: 2003-11-04
Classification: G11C

Abstract:
An integrated circuit comprising read/write memory having a plurality of memory devices, each of said memory devices having a unique address, and a built-in self-test (BIST) engine, said BIST engine comprising:a controller responsive to a test enable signal and operative to generate and store test data in said read/write memory; a comparator operative to compare retrieved data read from said read/write memory and said test data during a single pass test, said comparator identifying failed cycles where said retrieved data does not correspond to said test data; a diagnostic unit operative to store said failed cycles and being operative to store failed data and failing address during said single pass test, wherein said BIST engine stops only at each of said failed cycles during said single pass test; and a BIST clock operative to receive signals from said comparator when said failed cycles are identified by said comparator, wherein said signals gate off said BIST clock thereby stopping said BIST engine at each said failed cycles.