Patent ID: 7167889
Filing Date: 2007-01-23
Classification: G06F

Abstract:
1. A system for decimal multiplication in a superscalar processor comprising: a first pipeline including: a first register; a second register; a third register; an execution unit including a bit logic unit and a binary adder in operable communication with said first register, said second register, and said third register; a first rotator in operable communication with said first register and said execution unit; and a carry register in operable communication with said execution unit; a second pipeline comprising: a fourth register; a fifth register; a sixth register; a second execution unit including another bit logic unit and another binary adder in operable communication with said fourth register, said fifth register, and said sixth register; and a rotator in operable communication with said fourth register and said execution unit; a third pipeline comprising: a seventh register; a eighth register; a ninth register; a decimal adder in operable communication with said seventh register and said eighth register, a rotator in operable communication with said ninth register; a general register for storage and retrieval of data; an operand buffer for obtaining a first operand and a second operand; and a communication bus for communication among at least two of said first pipeline, said second pipeline, said third pipeline, said general register and said operand buffer.