Patent ID: 8354740
Filing Date: 2013-01-15
Classification: H01L

Abstract:
1. A top-side cooled semiconductor package with stacked interconnection plates comprising: a circuit substrate having a plurality of terminal leads for external electrical connection; at least one semiconductor die whose bottom surface is bonded atop the circuit substrate; a three dimensionally formed, elevation-adaptive low thermal and electrical resistance intimate interconnection plate to bond and interconnect a top contact area of said at least one semiconductor die with said circuit substrate, said intimate interconnection plate further comprising a plurality of dimples positioned thereon contacting with the top metalized contact areas of the semiconductor die, wherein each of the plurality of dimples having a female portion positioned on the top surface of said intimate interconnection plate and a male portion protruded from the bottom surface of said intimate interconnection plate; and a low thermal resistance stacked interconnection plate, stacked and bonded atop the intimate interconnection plate, adding effective top-side cooling to the semiconductor package, said stacked interconnection plate further comprising: a plurality of male top dimples positioned thereon and protruded from the bottom surface of said stacked interconnection plate whereby the plurality of male top dimples being locked in place with the plurality of dimples of the intimate interconnection plate.