Patent ID: 6099744
Filing Date: 2000-08-08
Classification: H01G

Abstract:
A fabrication technique for a test sample to characterize pyroelectric and ferroelectric thin films for use in uncooled infrared focal plane arrays operated at an approximate 60 Hz modulation, the fabrication technique comprising:applying a SiO.sub.2 layer to a silicon wafer substrate to provide a thin electrically isolating thermal oxide layer;depositing Cr and Pt to said thin electrically isolating thermal oxide layer to provide a guard layer and as a resistance thermometer;lifting off excess material from the guard layer;blanket depositing a layer of ZrO.sub.2 to the guard layer;etching isolation vias into said ZrO.sub.2 layer;depositing Cr and Pt to said etched ZrO.sub.2 layer to provide a bottom electrode pattern and as a resistance thermometer;lifting off excess Cr and Pt material from said bottom electrode pattern as a partially layered wafer;delineating saw lines on said partially layered wafer;sawing said wafer along said delineated saw lines as a machined wafer;rinsing said machined wafer with acetone then methanol as a rinsed machined wafer;depositing a pyroelectric film on said rinsed machined wafer;annealing said pyroelectric film to form a perovskite;etching isolation vias on said perovskite;cleaning said etched perovskite isolation vias as a perovskite layer;depositing a Cr and Pt layer on said perovskite layer to form a pattern top electrode and as a resistance thermometer;lifting off resultant excess Cr and Pt material from said pattern top electrode to form a cleaned pattern top electrode;depositing, at approximately 45 degrees Celsius, a layer of SiO.sub.2 to cover steps on said cleaned pattern top electrode to provide a layered cleaned pattern top electrode;ecthing isolation vias on said layered cleaned pattern top electrode;depositing a Cr and Pt layer on said layered cleaned pattern top electrode to form a pattern heater layer;lifting off resultant excess Cr and Pt material from said pattern heater layer;depositing Cr and Au on said pattern heater layer for a bonding pads layer;lifting off resultant excess material from said bonding pads layer to result in a test sample;mounting said resultant test sample in a chip carrier, whereby energizing said pattern heater layer varies a temperature of the test unit cell to achieve the approximate 60 Hz modulation so that voltage measurements of resistance thermometer layers and electrode layers achieve a direct measurement of thin film temperature responsitivity.