Patent ID: 7768299
Filing Date: 2010-08-03
Classification: H03K

Abstract:
1. An apparatus for mitigating leakage currents caused by input voltages, comprising: a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node; a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state; a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state; wherein the floating node is coupled to a source of a p-channel transistor within a driver circuit, the p-channel transistor having a gate coupled to the positive voltage supply; and wherein an output enable signal is configured to place the apparatus in the second state to prevent leakage currents from passing through the source of the p-channel transistor and into the positive voltage supply when the driver circuit is configured to receive a voltage signal.