Patent ID: 8319354
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; an insulating layer over said first and second metal layers and said dielectric layer, wherein said insulating layer comprises a nitride layer; a first metal interconnect having a first contact point at a bottom of a first opening in said insulating layer, wherein said first opening is over said first contact point; a second metal interconnect having a second contact point at a bottom of a second opening in said insulating layer, wherein said second opening is over said second contact point; a third metal interconnect having a third contact point at a bottom of a third opening in said insulating layer, wherein said third opening is over said third contact point, wherein said first, second and third metal interconnects comprise electroplated copper, wherein said first, second and third contact points are aligned in a first line, wherein said second contact point is between said first and third contact points; a patterned metal layer on said first, second and third contact points and over said insulating layer, wherein said patterned metal layer comprises a first adhesion layer and a third metal layer over said first adhesion layer, wherein said third metal layer has a sidewall not covered by said first adhesion layer, wherein said patterned metal layer comprises a first metal trace over said insulating layer, wherein said first metal trace is connected to said first contact point through said first opening, a first contact pad connected to said first contact point through said first metal trace, wherein said first contact pad is not vertically over said first contact point, a second metal trace over said insulating layer, wherein said second metal trace is connected to said second contact point through said second opening, a second contact pad connected to said second contact point through said second metal trace, wherein said second contact pad is not vertically over said second contact point, a third metal trace over said insulating layer, wherein said third metal trace is connected to said third contact point through said third opening, and a third contact pad connected to said third contact point through said third metal trace, wherein said third contact pad is not vertically over said third contact point, wherein said second metal trace extends between said first and third contact pads; a first metal bump on said first contact pad and not vertically over said first contact point, wherein said first metal bump comprises a second adhesion layer and a gold layer with a height between 1 and 50 micrometers over said second adhesion layer; a second metal bump on said second contact pad and not vertically over said second contact point; and a third metal bump on said third contact pad and not vertically over said third contact point, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line.