Patent ID: 6765433
Filing Date: 2004-07-20
Classification: G05F,G06F

Abstract:
An integrated circuit having a plurality of signal input circuits, each signal input circuit comprising:an input/output pin; an input buffer associated with said pin; and means for controlling connection of said pin to said input buffer, said means for controlling having a first input connected to said pin, a second input connected to a low-power signal line, and an output connected to said input buffer, said means for controlling responsive to an input signal transition on said pin and a low-power control signal asserted on said low-power signal line which is indicative of said powered-down mode of the integrated circuit, such that a) whenever the low-power control signal is not asserted, said pin being connected to said input buffer by said means for controlling, b) whenever the low-power control signal is asserted and no input signal transition is sensed at said first input by said means for controlling, said pin being isolated from the input buffer by said means for controlling, thereby preventing current leakage through the input buffer, and c) whenever the low-power control signal is asserted and an input signal transition is sensed at said first input by said means for controlling, said pin being reconnected to the input buffer by said means for controlling.