Patent ID: 6974770
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A method of providing self-aligning features on a semiconductor device comprising the steps of: providing a substrate with a dielectric layer that defines at least one line of metallization; recessing the top surface of said at least one line of metallization below the top surface of said dielectric layer; capping said at least one line of metallization with a barrier layer deposited over the top surface of said substrate, said barrier layer defining a top surface that follows the contours of the top surface of said at least one line of metallization and said dielectric; depositing a layer of liner material over said barrier layer, said layer also following the contours of said at least one line of metallization and said dielectric; planarizing said layer of liner material so as to remove high areas such that the low areas of said liner material remain; and etching selected features in said dielectric layer of said substrate by using said remaining low areas of said liner material as a hard mask.