Patent ID: 8207603
Filing Date: 2012-06-26
Classification: H01L

Abstract:
1. A chip-stacked package structure with a leadframe having inner leads, each inner lead having a plurality of transfer pads, comprising: said leadframe, composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, said die pad being provided between said plurality of inner leads arranged in rows facing each other, positions of a top surface of each of said inner leads in said leadframe being partially coated with an insulation layer and a plurality of metal pads are selectively formed on said insulation layer to define said respective pads; a plurality of offset chip-stacked structures, being set on said die pad and electrically connected to said plurality of inner leads arranged in rows facing each other, wherein each said offset chip-stacked structure comprises: an encapsulant, covering said plurality of offset chip-stacked structures and said leadframe, said plurality of outer leads extending out of said encapsulant; and at least a bus bar being provided between said plurality of inner leads arranged in rows facing each other and said die pad.