Patent ID: 6571264
Filing Date: 2003-05-27
Classification: G06F

Abstract:
A floating-point arithmetic device comprising:first control means for comparing signs of two input operands with each other and generating a control signal in accordance with the compared result; significand output means for calculating a difference between exponents of said input operands, outputting a significand of one of said input operands with a larger one of said exponents as it is, shifting a significand of the other input operand with a smaller one of said exponents by the calculated exponent difference and outputting the shifted significand; a multiplexer for selecting said larger exponent in response to said control signal from said first control means; a first bit inverter for inverting said significand with said larger exponent from said significand output means for subtraction in response to said control signal from said first control means; an adder for adding said shifted significand with said smaller exponent from said significand output means and an output value from said first bit inverter; leading-zero anticipation means for anticipating the consecutiveness of leading zeros from said significand with said larger exponent and said shifted significand with said smaller exponent from said significand output means; leading-zero counting means for counting the number of said leading zeros anticipated by said leading-zero anticipation means; second control means for estimating a rounding condition to store an output value from said adder in a specific bits number; a left shifter for shifting the output value from said adder to the left by said number counted by said leading-zero counting means; a second bit inverter for taking two's complement of an output value from said left shifter if the output value from said adder is negative; an incrementer for incrementing an output value from said second bit inverter by one under the control of said second control means to provide a final significand; a compensation shifter for shifting the final significand from said incrementer to perform digit compensation when it is in the maximum; an exponent subtracter for subtracting said number counted by said leading-zero counting means from said larger exponent selected by said multiplexer; and a decrementer for decrementing an output exponent from said exponent subtracter by one to provide a final exponent.