Patent ID: 7898275
Filing Date: 2011-03-01
Classification: G01R,H01L

Abstract:
1. An apparatus for testing a semiconductor die which comprises: (a) a package having a cavity therein; (b) a plurality of terminals in said package disposed at the periphery of said cavity; (c) a semiconductor die to be tested having a plurality of bond pads thereon, said die disposed in said cavity; (d) an interconnecting layer having electrically conductive paths thereon disposed in said cavity, each of said paths having first and second spaced apart regions thereon, said first region of each path being aligned with and contacting a said bond pad, said first region including a compliant bump probe tip having a first predetermined height above said layer and further including a standoff on said layer having a second predetermined height above said layer less than said first height; and (e) an interconnection between said second spaced apart region of each of said paths and one of said plurality of terminals.