Patent ID: 6902961
Filing Date: 2005-06-07
Classification: H01L

Abstract:
1. A method of forming a CMOS thin film transistor device on a substrate having an NMOS area, a PMOS area and a circuit area, the NMOS area having a first doped area, a lightly doped area and a first gate area, and the PMOS area having a second doped area and a second gate area, the method comprising the steps of: (a) forming a semiconductor layer on the substrate; (b) performing a first patterning process using a first photomask on the semiconductor layer to form a first semiconductor island and a second semiconductor island on part of the substrate, wherein the first semiconductor island is located in the NMOS area and the second semiconductor island is located in the PMOS area; (c) forming a dielectric layer on the first semiconductor island, the second semiconductor island and the substrate; (d) forming a metal layer on the dielectric layer; (e) performing a second patterning process using a second photomask to form a first photoresist layer on the metal layer located in the lightly doped area, the first gate area, the PMOS area and the circuit area; (f) using the first photoresist layer as a mask, removing part of the metal layer to form a first metal layer in the lightly doped area and the first gate area, a second metal layer in the PMOS area and a third metal layer in the circuit area, wherein the third metal layer electrically connects the first metal layer and the second metal layer; (g) using the first and the second metal layers as masks, performing an n (h) performing a dry etching procedure to remove part of the first photoresist layer, part of the first metal layer and part of the second metal layer, thus forming a first gate with a symmetrical cone shape, a remaining second metal layer and a remaining first photoresist layer, and exposing the dielectric layer in the lightly doped area, wherein a bottom width of the first gate is narrower than that of the first metal layer, and the symmetrically coned shape is gradually thinner from bottom to top; (i) using the first gate and the remaining second metal layer as masks, performing an n (j) removing the remaining first photoresist layer and thus forming an NMOS element in the NMOS area; (k) performing a third patterning process using a third photomask to remove the remaining second metal layer in the second doped area, thus forming a second gate on the dielectric layer in the second gate area; and (l) performing a p