Patent ID: 6389507
Filing Date: 2002-05-14
Classification: H04L,Y10S

Abstract:
A memory device, comprising:a main data memory for storing a plurality of entries in the memory device; an address map and overflow data memory for storing an address map of the entries in the main data memory, the address map comprising an intended address location (IAL) and an actual physical location (APL) wherein the IAL indicates the external memory address of each entry and the APL indicates the actual memory locations for each entry within the memory device; a controller for controlling the operation of the main data memory and the address map and overflow data memory using the IAL and APL in order to operate the memory device as one or more of a CAM and a RAM, the controller further comprising a comparator that compares each bit of an incoming piece of data with each bit of each entry of a bin in the memory device and search tree logic unit that sorts through the entries in the memory device to reduce the number of bit-by-bit comparisons performed by the comparator by selecting a bin of the memory device.