Patent ID: 6442075
Filing Date: 2002-08-27
Classification: G11C

Abstract:
An erasing method for a nonvolatile semiconductor memory device comprising: floating-gate field-effect transistors, which have a control gate, a floating gate, a drain, and a source, and enable electric writing and erasing of information, disposed in a matrix configuration on a substrate or on a well; a plurality of row lines connected to the control gate of each floating-gate field-effect transistor arrayed in a row direction; and a plurality of column lines connected to the drain of each floating-gate field-effect transistor arrayed in a column direction, the source of each floating-gate field-effect transistor constituting a block being connected in common,wherein the erasing operation is conducted in the block units with use of a Fowler-Nordheim tunneling phenomenon; and comprises a first step for lowering threshold voltages of all the floating-gate field-effect transistors within the block to a voltage higher than 0, and equal to or lower than a first specified voltage in an erased state; a second step for lowering the threshold voltages to a voltage equal to or lower than a second specified voltage that is lower than the first specified voltage; and a third step for raising the threshold voltages to a voltage higher than 0.