Patent ID: 6177306
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a DRAM device with a silicide layer on a gate of a MOS transistor in a memory region, the method comprising:providing a semiconductor substrate, having the memory region and a periphery region;sequentially forming a gate oxide layer and a polysilicon layer to cover both the memory region and the periphery region over the semiconductor substrate;forming a first transistor at the periphery region, in which the first transistor comprises a first gate structure and a first interchangeable source/drain region, wherein the first gate structure comprises a portion of the polysilicon layer and the gate oxide layer remained after being patterned in the periphery region, and the polysilicon layer and the gate oxide layer at the memory region are remained to cover the whole memory region;forming a silicide layer on the polysilicon layer remained in both the memory region and the periphery region and the first interchangeable source/drain region;forming an insulation layer over the semiconductor substrate; andforming a second transistor at the memory region, in which the second transistor comprises a second gate structure and a second interchangeable source/drain region, wherein the second gate structure comprises a portion of the polysilicon layer and the silicide layer in the memory region remained after being patterned, while the second source/drain region is free of the silicide layer.