Patent ID: 6535427
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array having cell-based bit lines and nonvolatile memory cells connected thereto, said nonvolatile memory cell is selected according to address signals in an address selection period; a bit line to which a signal voltage of said cell-based bit line is transmitted; a cell-based bit line decoder circuit for connecting said cell-based bit line in said memory cell array to said bit line in said address selection period according to said address signal; a sense bit line to which a signal voltage of said bit line is transmitted; a separation circuit connected between said sense bit line and said bit line, for electrically separating said sense bit line from said bit line; a sense line to which a signal voltage of said sense bit line is transmitted; a bias circuit connected between said sense line and said sense bit line, for supplying said sense bit line with a predefined voltage; a load circuit connected to said sense line; an amplifier circuit supplied with a voltage of said sense line and a reference voltage, for amplifying a difference between both voltages; and a first initialization circuit activated according to a first control signal in said address selection period, for supplying said sense line with a specified voltage.