Patent ID: 6265270
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method of fabricating a mask ROM (read only memory) device, said method comprising the steps of:(a) forming an array of MOS transistors on a semiconductor substrate, each of the MOS transistors comprising a gate oxide film, a gate electrode, a source region and a drain region;(b) depositing a USG (undoped silicon glass) layer over the substrate;(c) depositing a BPSG (boron-phosphorous silicon glass) layer over said USG layer;(d) performing a planarization process;(e) forming contacts on portions of said BPSG layer, the portions being located over the source and drain regions;(f) forming metal electrodes on the contacts;(g) forming a passivation layer over the substrate;(h) forming a photoresist layer over said passivation layer and removing selected portions of said photoresist layer to partially expose said passivation layer in accordance with a ROM code, the selected portions being located over selected gate electrodes respectively;(i) etching through the exposed portions of said passivation layer to form openings and expose portions of said BPSG layer within the openings;(j) etching the exposed portions of said BPSG layer within the openings to a remained thickness;(k) implanting ROM code ions into said substrate adjacent to the selected gate electrodes through the openings;(l) removing said photoresist layer;(m) forming a thin passivation layer over the substrate;(n) activating the implanted ROM code ions by annealing said device at a temperature within a range of 420.degree. C. to 550.degree. C. in an atmosphere of N.sub.2 or N.sub.2 /H.sub.2 mixture.