Patent ID: 6563341
Filing Date: 2003-05-13
Classification: H01L,H03K

Abstract:
A tri-state buffer circuit that outputs one of three possible states, the tri-state buffer circuit comprising:an AND device that obtains a logical product of an input signal and a control signal, inverts the logical product and outputs the same, the AND device including at least a first P-channel transistor; a second P-channel transistor having a gate that is supplied with a signal outputted from the AND device and a source that is supplied with a first power supply voltage; a first N-channel transistor that is complementarily connected with the second P-channel transistor, the first N-channel transistor having a gate that is supplied with a signal outputted from the AND device and a drain that outputs an output signal; and a second N-channel transistor connected between the first N-channel transistor and a second power supply voltage, the second N-channel transistor has a gate that is supplied with the control signal and allows a current to flow from a source of the first N-channel transistor to the second power supply voltage according to the control signal, and the first P-channel transistor and the second P-channel transistor are formed on the same impurity diffusion region.