Patent ID: 7595673
Filing Date: 2009-09-29
Classification: H03L

Abstract:
1. A clock signal generator for generating clock signals to an integrated circuit comprising: a delay-locked loop is configured to generate a plurality of mutually delayed clock phases based on a reference clock signal and to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control word, wherein said output signal is a first clock signal; an inverter arranged to generate an inverse of the output signal; a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal; wherein the delay-locked loop is configured to select the output signal of the delay-locked loop among the plurality of clock phases such an inversion of an MSB of the first control word results in a 180° phase shift in the output signal of the delay-locked loop; the clock-signal generator is configured to output both the first and the second clock signal; and in that the clock-signal generation unit comprises a control unit arranged to generate the first control word based on a second control word and the clock-invert signal, wherein the control unit is configured generate the MSB of the first control word as a copy of an MSB of the second control word when the clock-invert signal has a first value and as an inverse of the MSB of the second control word when the clock-invert signal has a second value.