Patent ID: 6180448
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory device having a cell array region and a peripheral circuit region surrounding the cell array region, comprising the steps of:forming a plurality of cell storage electrodes over a semiconductor substrate in the cell array region;forming a plurality of dummy storage electrodes over the semiconductor substrate in the cell array region, and around the plurality of cell storage electrodes, the dummy storage electrodes having dummy sidewalls of an inclined profile facing toward the peripheral circuit region; andforming a plate electrode in the cell array region over the plurality of cell storage electrodes and over the plurality of dummy storage electrodes,wherein the step of forming the plurality of dummy storage electrodes comprises the substeps of:forming a conductive layer over the semiconductor substrate;forming a plurality of photoresist patterns over the conductive layer in the cell array region;forming a plurality of spacers on photoresist sidewalls of the photoresist patterns;performing a first dry etching process to anisotropically etch the conductive layer to an intermediate depth using the photoresist patterns and the spacers as an etching mask, thereby forming a conductive layer having a stepped surface;depositing a plurality of polymers having an inclined profile onto the stepped surface adjacent to the peripheral circuit region;eliminating the photoresist pattern; andperforming a second dry etching process to anisotropically etch the stepped conductive layer using the spacers and the polymers as an etching mask thereby forming a plurality of cylindrical dummy storage electrodes having inclined dummy sidewalls on an outermost edge of the cell array region.