Patent ID: 7713817
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A semiconductor processing method, comprising: providing an electrically insulative material and a pair of electrical nodes over a substrate; the electrical nodes being a first node and a second node, a first opening extending through the electrically insulative material to the first node and a second opening extending through the electrically insulative material to the second node; the second node being higher than the first node over the substrate, and accordingly the first opening being deeper than the second opening; the first node having a first surface exposed within the first opening and the second node having a second surface exposed within the second opening; the first surface being suitable for electroless plating and the second surface not being suitable for electroless plating; electroless plating a first conductive material within the first opening and from the first surface to form a first conductive material plug that only partially fills the first opening; the electroless plating of the first conductive material being conducted while exposing the first and second surfaces to electroless plating conditions, and while the second surface is not suitable for electroless plating; after forming the first material plug, activating the second surface to render the second surface suitable for electroless plating; after activating the second surface, electroless plating a second conductive material within the first and second openings, the second conductive material within the first opening forming a second conductive material plug extending upwardly from the first conductive material plug, and the second material within the second opening forming a second conductive material plug extending upwardly from the second surface; and wherein the first and second conductive materials are different compositions relative to one another.