Patent ID: 8691651
Filing Date: 2014-04-08
Classification: H01L

Abstract:
1. A method of forming a non-planar FET, comprising: providing a substrate, wherein an active region, an isolation region, and a peripheral region are defined on the substrate; forming a first patterned mask layer on the substrate; forming a plurality of first trenches in the isolation region by patterning the substrate by using the first patterned mask layer as a mask, and forming a plurality of first shallow trench isolations by filling a first insulation layer in the first trenches; patterning the first patterned mask layer to form a second patterned mask layer; forming a plurality of second trenches in the active region by patterning the substrate by using the second patterned mask layer as a mask, and forming a plurality of second shallow trench isolations by filling a second insulation layer in the second trenches; after forming the first shallow trench isolations and the second shallow trench isolations, forming a plurality of fin structures by removing a part of each second shallow trench isolation and exposing a part of the substrate in the presence of the second patterned mask layer, wherein the exposed substrate becomes the fin structures, and the fin structures and the second shallow trench isolations are arranged alternatingly; forming a conductive layer on the substrate in the active region and the peripheral region to cover each fin structure; and patterning the conductive layer to make the conductive layer in the peripheral region become a gate of a planar field effect transistor and make the conductive layer in the active region become a gate of a non-planar FET.