Patent ID: 6737346
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method for fabricating an integrated circuit structure, the method comprising:depositing a conductive layer above an insulating material; patterning the conductive layer to form a plurality of first metal features and at least one second metal feature, wherein the first metal features and the at least one second metal feature have a substantially equal thickness, Tmet, above the insulating material, and the first metal features have a substantially standard distance, Smet, between parallel edges of adjacent ones of the first metal features, and the at least one second metal feature is connected to one or more of the first metal features in proximity to an intersection area of the conductive layer, wherein an intersection area is a roughly rectangular area that includes at least one metal feature corner, parts of at least one other metal feature that are in close proximity to the at least one metal feature corner, and a portion of a dielectric layer that will be located between the at least one metal feature corner and the parts of the at least one other metal feature; and depositing the dielectric layer having a thickness, TIDL, over the conductive layer.