Patent ID: 7072448
Filing Date: 2006-07-04
Classification: H04M

Abstract:
1. A device for detecting a transmission of a plain old telephone service (POTS) communication signal and/or a digital subscriber loop (DSL) communication signal in a communication network, wherein the communications network includes a publicly switched telephone network (PSTN) having one or more local subscriber loops associated therewith, wherein at least one of the local subscriber loops includes an unshielded twisted pair (UTP) for transmitting the POTS and DSL communication signals, the device comprising: a housing; and a filter circuit contained in the housing, wherein the filter circuit is adapted to communicatively interface with the communication network, and wherein the filter circuit includes: a first conductive lead and a second conductive lead, wherein each of the first and second leads includes: wherein the first circuit path further includes a first inductor and a second inductor, wherein the first indicator is electrically connected between the first and second inductors, and wherein the first circuit path is in series with first and second conductive leads when each second electrical engagement means electrically engages the filter circuit; wherein the second circuit path further includes a first capacitor and a second capacitor, wherein the second indicator is electrically connected between the first and second capacitors, and wherein the second circuit path is in series with first and second conductive leads when each second electrical engagement means electrically engages the filter circuit; wherein inductance values for each of the first and second inductors and capacitance values for each of the first and second capacitors are such that only the POTS communication signal is permitted to pass through the first circuit path and only the DSL communication signal is permitted to pass through the second circuit path; and wherein the second circuit path further includes a logical AND gate, wherein the logical AND gate includes a first logic input, a second logic input, and an output; wherein the logical AND gate is electrically connected between the first capacitor and the second indicator such that the first logic input is connected to the first capacitor, the second logic input is connected to a DC voltage source, and the output is connected to the second indicator.