Patent ID: 6295630
Filing Date: 2001-09-25
Classification: G06F,H01L

Abstract:
A method for measuring an overlap length of each of a plurality of MISFETs varying in gate length (L), each of said MISFETs being formed in a surface region or in a well of said surface region of a semiconductor substrate, comprising the steps of:applying a predetermined voltage to a gate of each of said MISFETs to keep each of said MISFETs turned OFF;measuring a between gate/semiconductor substrate capacitance (C.sub.GB) or a between gate/well capacitance (C.sub.GB) in each of said gate lengths (L) of said MISFETs to obtain a capacitance measurement result;finding out the dependency of said capacitance (C.sub.GB) on each of said gate lengths (L) in each of said MISFETs on the basis of said capacitance measurement result; anddetermining an overlap length (.DELTA.L) on the basis of said dependency of said capacitance (C.sub.GB) on each of said gate lengths (L), said gate overlapping both a source and said drain through said overlap length (.DELTA.L) in each of said MISFETS.