Patent ID: 7724781
Filing Date: 2010-05-25
Classification: H04J

Abstract:
1. A receive virtual concatenation processor comprising: an input buffer adapted to receive and store time-slot interleaved data portions flowing through concatenated channels; wherein said concatenated channels include contiguously and virtually concatenated channels; a matrix transposer adapted to read the time-slot interleaved data portions stored in the input buffer and to output per time-slot data portions; a marriage network adapted to convert the per time-slot data portions to per-channel data portions; an alignment logic adapted to align the per time-slot data portions which are misaligned by more than a predefined number of time-slots; a time-slot counter adapted to count a time-slot associated with each of the data portions of the time-slot interleaved data; wherein the input buffer and the matrix transposer are cooperatively adapted to align the time-slots which are misaligned only by less than the predefined number of time-slots; and a memory.