Patent ID: 6141692
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A multi-processor computer system comprising:a global interconnect;a plurality of n nodes, each node having:a local interconnect;at least one processor, said processor being coupled to the local interconnect;a cache associated with each processor;a main memory coupled to the local interconnect, said main memory being equally accessible to all processors within its respective node;a global interface which couples the global interconnect to the local interconnect of its respective node, said global interface including a transaction filter, a tag memory, home agent, a slave agent, and a request agent, said transaction filter routes cache coherency transactions from said local interconnect through a local physical address-to-global address translator to said request agent, said transaction filter routes input/output transactions from said local interconnect through an I/O input queue to said request agent, and said tag memory stores a permission status entry for each of said routed cache coherency transactions and said routed input/output transactions; andat least one input buffer associated with each home agent and each slave agent and forming a portion of said global interface, each input buffer associated with said each home agent and said each slave agent of each global interface of each of the plurality of n nodes sized to contain a number of storage locations corresponding to at least a maximum number of outstanding transaction requests receivable at each node of the plurality of nodes, the maximum number of outstanding transaction requests being the outstanding transaction requests together issuable by all of said plurality of n nodes.