Patent ID: 7664929
Filing Date: 2010-02-16
Classification: G06F

Abstract:
1. A data processing apparatus, the apparatus comprising: an instruction addressing unit; an instruction memory system arranged to output an instruction word, containing a plurality of instructions, in response to an instruction address from the instruction addressing unit, the instruction memory system comprising a plurality of memory units, arranged to output respective parts of the instruction word in parallel; an instruction execution unit, comprising a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units; an instruction address modification circuit arranged to modify translation of the instruction address into a physical address for a particular one of the memory units relative to other ones of the memory units and to change generation of instruction words from instructions from different memory units during execution of a program, the instruction address modification circuit being configured to modify an address translation between supplying a first instruction address for a first instruction word and supplying a second instruction address for a second instruction word, the second instruction word being different from the first instruction word and including a copy of a part of the first instruction word, so that the part of the first instruction word is re-used in the second instruction word thereby reducing memory needed to store the program, wherein the instruction address modification circuit includes an offset register which is directly connected to an output of a functional unit of the plurality of functional units, the functional unit updating an offset value in the offset register during the execution of the program, and wherein the instruction address modification circuit is operationally coupled to a controller that provides the instruction address, and to one of the plurality of the functional units that provides an adjust signal to the instruction address modification circuit, and wherein the controller is distinct from the functional unit; the instruction address modification circuit being configured to modify the translation in response to the adjust signal and to provide a modified translated address to one of the plurality of the memory units.