Patent ID: 6651198
Filing Date: 2003-11-18
Classification: G01R

Abstract:
A system for testing the operation of on-chip modules and the interconnections between those on-chip modules, comprising:an output scan cell operable to capture an output signal of a first on-chip module, the captured output signal used to verify the proper operation of the first on-chip module and a signal path from the output of the first on-chip module to the output scan cell; an input scan cell operable to forward a test signal to an input of a second on-chip module via the output scan cell, the forwarded test signal used to verify the proper operation of the second on-chip module and a signal path from the output scan cell to the input of the second on-chip module thereby verifying the proper operation of an interconnection signal path between the output of the first on-chip module and the input of the second on-chip module; and a mode select signal which selects an operational mode of the output scan cell, the mode select signal being either input test mode or output test mode.