Patent ID: 8996955
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A data storage system comprising: a memory circuit; and a control circuit to receive data bits provided for storage in memory cells of the memory circuit, wherein the control circuit compares each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value, wherein the control circuit generates encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells, wherein the control circuit prevents any of the data bits from being stored in the memory cells determined to have unstable values, and wherein the control circuit generates redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.