Patent ID: 6292046
Filing Date: 2001-09-18
Classification: H01L

Abstract:
In a semiconductor device having at least a positive, low impedance, power bus (Vdd) and a negative, low impedance, power bus (Vss) and at least one input or output signal line terminating at a pad, said at least one signal line having at least one circuit element susceptible to damage from a high voltage transient surge, a protection circuit comprising:a first charge dissipation circuit positioned between and coupling said pad to said positive power bus; said first charge dissipation circuit having capacitive coupling between a gate and drain electrode for detecting negative transient voltage spikes at said pad and for biasing said charge dissipation circuit into a low impedance path to shunt said voltage transient to said positive power bus;a second charge dissipation circuit positioned between and coupling said pad to said negative power bus; said second charge dissipation circuit having capacitive coupling between a gate and drain electrode for detecting positive transient voltage spikes at said pad and for biasing said charge dissipation circuit into a low impedance path to shunt said voltage transient to said negative power bus;a first plurality of transistors with a first bipolar transistor having an emitter coupled to said pad and a second bipolar transistor having a base coupled to said power bus and includes a plurality of base-emitter junctions coupled therebetween; anda second plurality of transistors with a first bipolar transistor having a base electrode coupled to said pad and a second bipolar transistor having an emitter electrode coupled to said power bus and includes a plurality of base-emitter junctions coupled therebetween; said first and second plurality of transistors providing a discharge path in parallel with said first and second charge dissipation circuits.