Patent ID: 6185132
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A sensing current reduction device for a semiconductor memory device, comprising:a memory cell array consisting of a plurality of sub-cell arrays;a first decoder means for decoding a plurality of row address signals, and outputting a global word line selection signal;a second decoder means for decoding a plurality of column address signals, and outputting a global column line selection signal;a selection means for receiving the plurality of row address signals and the plurality of column address signals, and outputting a sub-cell array selection signal in order to select one of the plurality of sub-cell arrays;a third decoder means for outputting a signal enabling the sub-cell array according to the sub-cell array selection signal and the global word line selection signal; anda sense amplifier means for sensing/amplifying and outputting a data according to the sub-cell array selection signal and the global column line selection signal.