Patent ID: 7187036
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. An SRAM cell formed on an insulator substrate, the cell comprising: at least one active region formed on the insulator substrate and with a continuous silicide layer formed thereon serving as an intra-cell connection layer connecting at least a drain node of a PMOS transistor to a drain node of an NMOS transistor formed on the insulator substrate, the two transistors forming a first inverter; said continuous silicide layer further forming a sidewall butted connection structure used in conjunction with a gate interconnect layer and connecting the drain nodes of the transistors of the first inverter to gates of at least two transistors of a second inverter, wherein the continuous silicide layer consists of a first silicide film formed of silicon from the active region and a second silicide film formed of silicon from the gate interconnect layer.