Patent ID: 6954399
Filing Date: 2005-10-11
Classification: G11C

Abstract:
1. A column repair circuit of a semiconductor memory device including a plurality of memory cell array blocks, wherein a part of the plurality of memory cell array blocks has the different number of wordlines, comprising: a predecoder for decoding a row address; a block selector for generating block selecting signals to select the memory cell array blocks in response to output signals from the predecoder; a unit selector for generating unit selecting signals in response to a refresh mode signal, a row repair control signal, a row repair identifying signal, a row active signal and the block selecting signals; wherein the unit selecting signals select a unit of a wordline corresponding to the selected memory cell array block; and a fuse means for generating a column repair control signal in response to a column repair test signal and the unit selecting signals; wherein the column repair control signal is activated when a column repair is performed on the selected memory cell array block.