Patent ID: 8140801
Filing Date: 2012-03-20
Classification: G06F

Abstract:
1. A method in a processor for semi-synchronously copying data from a first portion of a single volatile memory to a second portion of the single volatile memory, the method comprising: receiving, in a processor, a call for a semi-synchronous memory copy operation comprising operational code and a set of operands, wherein the set of operands comprises at least wherein the semi-synchronous memory copy operation preserves temporal persistence of validity for the virtual source address and the virtual target address by setting a flag bit, wherein preserving temporal persistence of validity includes during the semi-synchronous memory copy operation, wherein the semi-synchronous memory copy operation operates semi-synchronously with the processor to provide maximum processor utilization such that the processor is able to execute at least one additional instruction on another section of the single volatile memory during the semi-synchronous memory copy operation; placing in a queue the memory copy operation for execution by a memory controller, wherein the queue is coupled to the memory controller; and continuing to execute at least one subsequent instruction during the semi-synchronous memory copy operation as the subsequent instruction becomes available from an instruction pipeline.