Patent ID: 6275061
Filing Date: 2001-08-14
Classification: G09G

Abstract:
A test method of a substrate comprising pixel electrodes arranged to form a matrix, a plurality of scanning lines arranged along the rows of said pixel electrodes, a plurality of storage capacitor lines coupled to a plurality of storage capacitor electrodes arranged along said scanning lines and applied a first voltage thereto, a plurality of signal lines arranged along the columns of the pixel electrodes and applied a fourth voltage which is in the range from a second voltage to a third voltage higher than said second voltage, a plurality of switching elements arranged in the vicinity of crossing points between said scanning lines and said signal lines and selectively applying said fourth voltage from said signal lines to said pixel electrodes, said method comprising the steps of:setting the switching elements associated with plural of said scanning lines ON state;applying voltages to said signal lines and said storage capacitor lines so that each potential difference between the storage capacitor lines and storage capacitor electrodes is substantially equal to or higher than a maximum potential difference between the first voltage and the fourth voltage; andmaintaining said each potential difference between the storage capacitor lines and storage capacitor electrodes for a predetermined period.