Patent ID: 6353241
Filing Date: 2002-03-05
Classification: H01L

Abstract:
Memory circuitry comprising:a substrate; a substrate memory array area and a substrate peripheral area spaced from the substrate memory array area; a plurality of spaced conductive lines disposed in the substrate memory array area and a plurality of spaced conductive lines disposed in the substrate peripheral area, a first two of the plurality of conductive lines disposed in the array area being adjacent one another and being jointly received over memory array substrate active area in at least a first cross section taken perpendicular to the first two lines, a second two of the plurality of conductive lines disposed in the peripheral area being adjacent one another and being jointly received over peripheral substrate active area in at least a second cross section taken perpendicular to the second two lines, the first two lines and the second two lines collectively having a common maximum width, the first two conductive lines in the array area being laterally spaced from one another a first distance in the first cross section, the second two conductive lines in the peripheral area being laterally spaced from one another in the second cross section a second distance which is greater than the first distance, each of the first two conductive lines in the array area in the first cross section having electrically insulative caps received thereover, each of the second two conductive lines in the second cross section being void of electrically insulative caps received thereover; the first two conductive lines and the second two conductive lines having respective elevational thicknesses in the first and second cross sections which are different from one another, the elevational thicknesses of the second two lines in the second cross section being less than the elevational thicknesses of the first two lines in the first cross section; and a first pair of insulative spacers received laterally over sidewalls of the first two conductive lines in the first cross section and having respective maximum lateral width dimensions, a second pair of insulative spacers received laterally over sidewalls of the second two conductive lines in the second cross section, the respective maximum lateral width dimensions of the first and second pairs of spacers in the respective first and second cross sections being substantially equal.