Patent ID: 6677191
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A method of producing a top gate thin-film transistor, comprising the steps of:forming source and drain electrodes on an insulating substrates; forming doped silicon source and drain regions on the insulating substrate, wherein the source and drain regions at least partially overlay the source and drain electrodes, respectively; subjecting the face of the substrate on which the source and drain regions are formed to plasma treatment to form a doped surface layer having impurity atoms diffused therein; forming an amorphous silicon layer on the doped surface layer over the spacing between the source and drain regions and at least partially overlying the source and drain regions, wherein the amorphous silicon layer is separated from the source and drain electrodes by the source and drain regions, respectively; forming an insulated gate structure over the amorphous silicon layer comprising a gate insulator and an upper gate conductor, the gate conductor being patterned to be narrower than the spacing between the source and drain regions; and laser annealing areas of the amorphous silicon layer not shielded by the gate conductor to form polysilicon portions having the impurities diffused therein.