Patent ID: 7477717
Filing Date: 2009-01-13
Classification: H03M

Abstract:
1. An input receiver circuit for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal, comprising: an input for receiving the high-speed input signal; a plurality of integration elements; a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal; a controller for controlling the switch; and a plurality of receivers for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, wherein each of the plurality of receivers further coupled to a latch each having a data input and a data take over control input, each of the output signals can be fed to a data input of one of the latches, the data take over control inputs of the latches are connected to the controller, the controller comprises a clock signal input for receiving a clock signal in a temporal relationship with the high-speed input signal, the controller being further formed such that it generates data take over control signals having fixed phase relationships with regard to the clock signal to control a data take over by the latches and that it controls the switch with fixed phase relationships with regard to the clock signal.