Patent ID: 6519694
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A processor comprising a register unit having a set of registers, an arithmetic logic unit and a load/store unit, the load/store unit being connected to at least one of the arithmetic logic unit and the register unit by a data path and having an error flag that, when set, marks as invalid a datum received from an external storage element following a load which has resulted in an error, the processor further comprising symbolic entity generating hardware operatively arranged in said data path from the load/store unit so as to generate and transmit a symbolic entity to said at least one of the arithmetic logic unit and the register unit when an invalid datum is output from the load/store unit for said at least one of the arithmetic logic unit and the register unit, the datum determined invalid by error recognition hardware in the symbolic entity generator responsive to the error flag being set, the arithmetic logic unit being configured to propagate the symbolic entity, when present in an operand of an operation carried out by the arithmetic logic unit, to a result of the operation.