Patent ID: 6023427
Filing Date: 2000-02-08
Classification: G11C

Abstract:
A flash memory device comprising:control logic;an input buffer connected to the control logic;an output buffer connected to the control logic;command execution logic connected to a memory controller of the flash memory device;an internal state machine connected to the command execution logic;a voltage pump connected to the internal state machine comprising:first and second output voltage nodes;a first pump capacitor, having first and second connections, the second terminal of the first pump capacitor coupled to receive a first clock signal;a second pump capacitor, having first and second connections, the second terminal of the second pump capacitor coupled to receive a second clock signal;a first PFET pump switch, having a source coupled to the first input voltage node, a drain coupled to the first terminal of the first pump capacitor, a gate, and a body electrically coupled to the second input voltage node; anda second PFET pump switch, having a source coupled to the first input voltage node, a drain coupled to the first terminal of the second pump capacitor and to the gate of the first PFET pump switch, a gate coupled to the drain of the first PFET pump switch, and a body coupled to the second input voltage node.an interface circuit connected to the first and second input voltage nodes and connected to the internal state machine; anda plurality of memory cell blocks connected to the interface circuit.