Patent ID: 6962849
Filing Date: 2005-11-08
Classification: H01L

Abstract:
1. A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming a charge trapping dielectric layer over the substrate; forming a hardmask over the charge trapping dielectric layer; patterning the hardmask to form a plurality of hardmask features having a first spacing therebetween; forming a spacer material over the patterned hardmask; patterning the spacer material to form spacers adjacent the hardmask features and defining a second spacing between the hardmask features that is less than the first spacing; performing a bitline implant through the charge trapping dielectric to establish buried bitlines within the substrate having a width corresponding to the second spacing; removing the entire patterned hardmask and all the spacers associated with the patterned hardmask; forming a wordline material over the charge trapping dielectric layer; and patterning the wordline material to form wordlines that overlie the bitlines.