Patent ID: 6339260
Filing Date: 2002-01-15
Classification: H01L,Y10T

Abstract:
A chip size package, comprising:a semiconductor chip having a plurality of chip pads formed thereon; an insulating film tape having a plurality of holes, wherein the semiconductor chip is attached to the bottom surface of the insulating film tape; metal pattern units formed on the insulating film tape; a solder mask covering portions of the insulating film tape and portions of the metal pattern units; metal pattern unit electroplates formed on portions of the metal pattern units which are not covered by the solder mask; a plurality of wires electrically connecting each of the chip pads and corresponding metal pattern unit electroplate, wherein at least two wires are provided with respect to each metal pattern unit having a first wire bonded between each of the chip pads and corresponding metal pattern unit electroplate and a second wire bonded between two points of the metal pattern unit electroplate, each of the two points being disposed on a line that is 90Â° with respect to the first wire; and a molding resin for sealing side surfaces and a bottom surface of the semiconductor chip.