Patent ID: 6069828
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second bit line pairs, each of said bit line pairs having first and second bit lines;a boosted voltage generating circuit for constantly generating a boosted voltage having a voltage level higher than a voltage level of a power supply voltage supplied to an input thereof;a sense amplifier for sensing and amplifying a potential difference between the first and second bit lines of said first and second bit line pairs;a first charging/equalizing circuit, responsive to a first charging/equalizing control signal having a first voltage level equal to the voltage level of the boosted voltage, for charging said first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing said first and second bit lines of said first bit line pair at the same first equalized voltage level;a second charging/equalizing circuit, responsive to a second charging/equalizing control signal having a first voltage level equal to the voltage level of the boosted voltage, for charging said first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing said first and second bit lines of said second bit line pair at the same second equalized voltage level;a first switch, responsive a first switch control signal having a first voltage level equal to the voltage level of the boosted voltage, for selectively connecting said first bit line pair to said sense amplifier; anda second switch, responsive to a second switch control signal having a first voltage level equal to the voltage level of the boosted voltage, for selectively connecting said second bit line pair to said sense amplifier.