Patent ID: 9196717
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A high voltage metal-oxide-semiconductor (HV MOS) transistor device comprising: a substrate comprising at least an insulating region formed thereon, the substrate comprising a first conductivity type; a gate positioned on the substrate and covering a portion of the insulating region; a drain region and a source region having a second conductivity type formed at respective sides of the gate in the substrate, and the second conductivity type being complementary to the first conductivity type; a deep well region formed in the substrate, the deep well region comprising the second conductivity type; a first implant region having the second conductivity type formed under the insulating region; and a second implant region formed near the source region, the second implant region is spaced apart from the insulating region by the deep well region, wherein the second implant region comprises a plurality of islanding regions, wherein the insulating region covers the entire first implant region, and a width of the first implant region is equal to a width of the insulating region.