Patent ID: 6055594
Filing Date: 2000-04-25
Classification: G06F

Abstract:
An integrated circuit device for performing byte accessible memory operations with an external memory module having memory integrated circuit (IC) chips, said integrated circuit device comprising:a first internal data bus having a plurality of individual byte portions;a plurality of multiplexers coupled to said first internal data bus wherein each multiplexer of said plurality of multiplexers is coupled to a respective byte portion of said plurality of individual byte portions of said first internal data bus;a plurality of registers coupled to said plurality of multiplexers wherein each register is coupled to an output of a respective multiplexer of said plurality of multiplexers;a second internal data bus for coupling to said external memory module, said second internal data bus having a plurality of individual byte portions wherein each byte portion is coupled to an output of a respective register, wherein further, each byte portion of said second internal data bus is also coupled back to an input of its associated multiplexer;a single chip enable pad for commonly controlling all memory IC chips of said memory module; anda state machine circuit for performing partial word write operations by:preloading a full word of data from said external memory module into said plurality of registers by controlling all of said plurality of multiplexers to select inputs coupled to said respective byte portions of said second internal data bus; and then bymerging individual byte data from said first internal data bus into said full word by controlling only a portion of said plurality of multiplexers to select inputs coupled to said respective byte portions of said first internal data bus.