Patent ID: 6889237
Filing Date: 2005-05-03
Classification: G06T

Abstract:
1. An integrated circuit comprising: a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three, the two-dimensional pyramid filter architecture of order 2N−1 including, said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following: a pyramid filtered output signal corresponding to the summation by the first summer circuit of output signals produced by four one-dimensional pyramid filters of order 2N−1; and a pyramid filtered output signal corresponding to an output signal produced by summing signal sample matrices of order [2(N−1)−1] in the second summer circuit; wherein the respective pyramid filtered output signals in said two dimensional pyramid filter architecture are summed by a third summer circuit on respective clock cycles of said two dimensional pyramid filter architecture.