Patent ID: 6470304
Filing Date: 2002-10-22
Classification: G11C,H01L

Abstract:
A memory core circuit design to be fabricated into a semiconductor substrate, comprising:a polysilicon layer being routed over the semiconductor substrate, the polysilicon layer is configured to define six gates of a six transistor core cell, the six transistor core cell having four transistors that define cross-coupled inverters, the cross-coupled inverters are electrically cross-coupled by a multi-layer cross-coupling which includes: a portion of the polysilicon layer; a portion of a first metallization line that is routed from a first metallization layer; and a portion of a second metallization line that is routed from a second metallization layer; wherein the multi-layer cross-coupling is substantially included within an area of the semiconductor substrate defined by the cross-coupled inverters such that a physical size of the six transistor core cell is substantially reduced.