Patent ID: 7074665
Filing Date: 2006-07-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising steps of: (a) forming a gate electrode of a MISFET over an element forming region of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein said element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method; (b) after said step (a), implanting ions in said element forming region of said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type; (c) after said step (b), forming a side wall spacer on a side surface of said gate electrode; (d) after said step (c), implanting ions in said element forming region of said first semiconductor region to form a third semiconductor region of said second conductivity type; (e) after said step (c), implanting ions in said element forming region of said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and (f) after said steps (d) and (e), forming a cobalt suicide layer in said third semiconductor region, wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region, and wherein a depth of said fourth semiconductor region is greater than a depth of said third semiconductor region.