Patent ID: 6433372
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of forming a multi-gate FET comprising:providing a substrate having spaced apart shallow trench isolation structures; forming a dielectric layer on the substrate between the spaced apart shallow trench isolation structures; forming a plurality of separated, non-overlapping insulated gates on the dielectric layer between the spaced apart shallow trench isolation structures, each of the gates having electrically insulating material on at least top, bottom and two opposing side surfaces of the gates; depositing a layer of electrically conductive material between the insulated gates; planarizing the layer of conductive material down to the insulating material on the top surface of the insulated gates to expose the insulating material and form at least one region of the conductive material defined by and between the insulating material on the gates; and implanting diffusion regions into the substrate adjacent to, and beneath a portion of, two distal ones of the plurality of insulated gates for defining therebetween in the substrate a channel region of the multi-gate FET that is controlled by the two distal ones of the insulated gates and conductive region between them.