Patent ID: 6680222
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A method of making a Split-Gate Virtual-Phase CCD cell, comprising the steps of:providing a substrate of first conductivity type; forming a dielectric layer on top of the substrate; forming a buried channel of second conductivity type in the substrate; implanting impurities of first conductivity type adjacent to the buried channel to form the channel stops; forming clocked gates using a single deposition layer, wherein said clocked gates formed from said single deposition layer are separated into several clocked gate regions using an etching mask deposited on said layer; said etching mask being formed by standard lithography technigues together with an isotropic material deposition and an anisotropic etch-back process resulting in very narrow gaps between said clocked gate regions; forming a virtual phase region of first conductivity type adjacent to said clocked gates in said buried channel; and forming a LOD anti-blooming drain structure adjacent to said virtual phase region by a self-aligned diffusion process utilizing an enclosed â€œdoughnut shapedâ€  mask.