Patent ID: 8766352
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a pipe channel layer formed over a substrate; a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line; a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line; a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer; an insulating barrier layer formed to completely surround the multi-layer formed on the pipe channel layer; a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers; and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.