Patent ID: 7111119
Filing Date: 2006-09-19
Classification: G06F

Abstract:
1. An information processing device which processes information using a plurality of processors, comprising: one or more first processors that have one or a plurality of first local memories; one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor, selected from among said first processors, has, and directly reading read information from said target first local memory; address map memory means for storing a first address map in which the first local memory addresses for each of said one or more first processors are recorded, wherein each of said one or more second processors performs one of acquiring the first local memory address of said target first processor from said first address map, writing said write information into the acquired first local memory address, and reading said read information from the acquired first local memory address; and a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises: a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory, or an operation of said transfer without storing said write information in said relay memory.