Patent ID: 6256770
Filing Date: 2001-07-03
Classification: G01R

Abstract:
A method of implementing test capabilities in a circuit expressed in a design-level description using hardware description language code, the design-level description including a plurality of hardware description language processes describing operations of the circuit, the method comprising the steps of:allocating portions of specified scan chains to different modules of the circuit based on an analysis of the design-level description and without specifying scan ordering for particular ones of the modules;ordering scan chain representations for at least a given one of the modules of the circuit based on a functional relationship between data carriers in one or more of the hardware description language processes, wherein the data carriers correspond to specific types of elements in the circuit, such that the scan chain representations for at least the given module of the circuit are ordered using information visible in the hardware description language code of the design-level description; andinserting scan assignment statements in the hardware description language code of the design-level description associated with one or more of the hardware description language processes, prior to applying a synthesis process to the design-level description of at least the given module of the circuit, such that a gate-level description of at least the given module of the circuit generated by the synthesis process applied to the design-level description includes the allocated portions of the scan chains for use in testing the circuit.