Patent ID: 6363463
Filing Date: 2002-03-26
Classification: G06F,G11C

Abstract:
In a computer system having a processor, a system memory, a flash memory, a memory controller, an apparatus comprising:a memory address/window detector coupled to said processor, said memory controller, a first input of a first logic gate and a first input of a second logic gate, said first logic gate having an output coupled to said memory controller and a second input for receiving a system memory access enable signal; a memory window control coupled to said system memory, said memory controller, said flash memory, said memory address/window detector, an output of a third logic gate and a first input of a fourth logic gate, said fourth logic gate having a second input for receiving a flash memory programming enable signal; a system memory access enable register coupled to an output of said second logic gate, a second input of said first logic gate, and an input of said third logic gate, wherein said memory window control is only accessible when said system memory access enable register is set to disabled; a flash memory programming enable register coupled to an output of said fourth logic gate; and a flash memory programming circuit coupled to said flash memory programming enable register and said flash memory, wherein said flash memory programming enable register is disabled if said system memory access enable register is set to enabled.