Patent ID: 6346834
Filing Date: 2002-02-12
Classification: H03K

Abstract:
A power-on reset (POR) circuit of a semiconductor device, comprising:a power supply terminal configured to receive a power supply voltage; a ground terminal configured to receive a ground voltage; a differential amplifier for sensing a difference in voltage between a first input terminal and a second input terminal to generate an output signal; a non-inverting input control circuit for controlling a voltage of the first input terminal of the differential amplifier; and an inverting input control circuit for controlling a voltage of the second input terminal of the differential amplifier; wherein the non-inverting input control circuit comprises a enhancement mode NMOS transistor coupled between the power supply terminal and the first input terminal of the differential amplifier; wherein the inverting input control circuit comprises a depletion mode transistor coupled between the power supply terminal and the second input terminal of the differential amplifier; wherein the non-inverting input control circuit further comprises a first MOS transistor having a drain and a gate each coupled to the first input terminal of the differential amplifier and a source coupled to the ground terminal; and wherein the inverting input control circuit further comprises a second MOS transistor having a drain coupled to the second input terminal, a source coupled to the ground terminal and a gate coupled to the first input terminal.