Patent ID: 7673190
Filing Date: 2010-03-02
Classification: G06F

Abstract:
1. A pipelined instruction processor having a number of pipelined stages, comprising: an instruction queue for storing one or more instructions; an instruction selector for selecting a selected instruction from the instruction queue and for providing the selected instruction to the pipelined stages of the instruction processor for execution; a parity error detector for identifying which, if any, of the one or more instructions in the instruction queue, including the selected instruction, have a parity error, the parity error detector identifying which, if any, of the one or more instructions in the instruction queue have a parity error prior to the instruction selector selecting the selected instruction for execution by the pipelined stages of the instruction processor, the parity error detector setting a parity error bit for each of those queued instructions that have been identified as having a parity error, wherein the parity error bit, when set, indicates that the corresponding queued instruction has a parity error; and an error handler for issuing a parity error abort message if the instruction selected by the instruction selector has a parity error.