Patent ID: 6502216
Filing Date: 2002-12-31
Classification: G01R,G11C

Abstract:
A memory device testing apparatus for testing a memory device comprising:a pattern generator which generates an address signal that indicates an address of said memory device, an input pattern signal to be input to said memory device, and an expectation value pattern signal to be read out from said memory device based on said input pattern signal; a signal input/output unit which provides said input pattern signal to said memory device at said address indicated by said address signal and outputs an output pattern signal from said address of said memory device; a comparator which compares said output pattern signal output from said memory device with said expectation value pattern signal output from said pattern generator and outputs fail data which indicates existence of a failure when there is a failure spot in said memory device; and a failure analysis memory unit which has: a data storing memory, in which said fail data output from said comparator is written into an address corresponding to said address of said failure spot in said memory device, and a compact memory, input of which is electrically connected to an output of said data storing memory, and a failure information, which indicates that there is said failure spot in said memory device, is written into said compact memory based on said fail data that is previously written into and read out from said data storing memory.