Patent ID: 6327686
Filing Date: 2001-12-04
Classification: G01R

Abstract:
A method of evaluating test patterns for testing critical circuit paths on an electronic device for timing faults, comprising the steps of:determining a logical model for at least a portion of a circuit design, the circuit design having a plurality of circuit paths, each individual one of the plurality of circuit paths having a starting point and an ending point, the logical model providing at least a logical value transition at the starting point, the transition providing a uniquely defined logical value at the ending point of each individual one of the plurality of circuit paths;selecting an individual one of the circuit paths;determining a trial test pattern disposed to electrically exercise the selected one of the circuit paths;inserting an inverted logical value at a selected time at a first selected location on the circuit path, said logical value remaining inverted for a predetermined variable time; anddetermining whether the inverted logical value at the first selected location at the selected period of time results in an incorrect logical value at a second selected location on the circuit path.