Patent ID: 7380227
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A computer implemented method, comprising: identifying a violation of a first asymmetric enclosure design rule for a geometry on a first layer of an electronic circuit design layout enclosing a geometry on a second layer of the electronic circuit design layout, wherein the width of the geometry on the second layer is known; determining a patch width from a geometric expansion of each edge of the geometry on the second layer by a first predetermined size factor and using the known width of the geometry on the second layer; determining a patch starting edge from the geometric expansion; determining a patch direction based on the determined patch starting edge and the geometric expansion; determining a patch length, wherein determining the patch length comprises adding the known width of the geometry on the second layer to the first asymmetric enclosure design rule; constructing a patch on the first layer according to the determined patch width, the determined patch starting edge, the determined patch direction, and the determined patch length.