Patent ID: 6791370
Filing Date: 2004-09-14
Classification: H03K

Abstract:
A circuit for reducing clock signal skew comprising:at least a first and second complementary clock signal input/output line connected to receive first and second complementary clock input signals and to transmit first and second complementary clock output signals, wherein the complementary clock input signals vary between low and high states at regular intervals and have a skewed time lag relative to each other; first and second inverters each having an input and an output, said input of said first inverter connected to said output of said second inverter and to said first clock signal input/output line and said input of said second inverter connected to said output of said first inverter and to said second clock signal input/output line, wherein the first and second inverters function to reduce the skew present in the complementary clock input signals; and first and second input buffer circuits for receiving first and second external complementary clock signals and respectively supplying said external complementary clock signals to said first and second complementary clock signal input/output line, wherein each of said first and second input buffer circuits comprises: an input for receiving one of said first and second external complementary clock signals; an input for receiving a reference voltage signal; a differential amplifier coupled to said inputs, said differential amplifier having an output terminal for providing a latch signal in response to the external clock signal in comparison to the reference voltage signal, the latch signal having a first or second state; a buffer circuit inverter connected to said output terminal of said differential amplifier, said buffer circuit inverter generating a first internal clock signal when the latch signal is in a first state, and a second, complementary internal clock signal when the latch signal is in a second state; and an input line for transmitting said first or second internal clock signal, said input line connected to one of said first and second complementary clock signal input/output lines.