Patent ID: 6489807
Filing Date: 2002-12-03
Classification: H03K

Abstract:
An output buffer for outputting an output datum having a predetermined voltage level and predetermined slew-rate as a function of an input datum and a first enabling signal that causes the output buffer to operate in a normal state or a high impedance state, the output buffer comprising:an output stage comprising at least one pull-up transistor and at least one pull-down transistor; an enabling circuit receiving as inputs the input datum and a second enabling signal and generating a pull-up control signal and a pull-down control signal either in phase or in phase opposition based upon whether the second enabling signal is active or disabled, the second enabling signal being a delayed replica of the first enabling signal; a slew-rate regulation circuit for producing a pull-up slew rate regulation signal and a pull-down slew rate regulation signal based upon the first enabling signal and the input datum; at least one pull-up driving circuit for driving said at least one pull-up transistor based upon the pull-up control signal, said at least one pull-up driving circuit comprising at least one NOR logic gate having first and second inputs, the first input of said NOR logic gate receiving an inverted pull-up control signal and the second input of said NOR logic gate receiving the pull-up slew-rate regulation signal, the second input of said NOR logic gate having a greater resistance than a resistance of the first input of said NOR logic gate; and at least one pull-down driving circuit for driving said at least one pull-down transistor based upon the pull-down control signal, said at least one pull-down driving circuit comprising at least one NAND logic gate having first and second inputs, the first input of said NAND logic gate receiving an inverted pull-down control signal and the second input of said NAND logic gate receiving the pull-down slew-rate regulation signal, the first input of said NAND logic gate having a greater resistance than a resistance of the second input of said NAND logic gate.