Patent ID: 8933503
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. A strained channel transistor, comprising: a gate electrode over a semiconductor crystal substrate, wherein an interatomic distance between neighboring atoms in the semiconductor crystal is defined by a substrate lattice spacing; sidewall spacers on the gate electrode; source and drain regions formed entirely within the semiconductor crystal substrate on opposite sides of the gate electrode, the source and drain regions each having a planar uppermost surface; a strained layer formed on an upper surface of the semiconductor crystal substrate and overlying the planar uppermost surface of the source and drain regions, the strained layer having a non-planar upper surface and extends from an isolation region toward the sidewall spacers; and a channel region formed beneath the gate electrode between the source and drain regions, the strained layer configured to provide stress to the channel region; wherein no portion of the strained layer lies beneath the upper surface of the semiconductor crystal substrate, and no portion of the strained layer physically contacts the sidewall spacers; wherein the stressor layer is about 200 to 1000 Å thick; wherein the substrate lattice spacing under the gate electrode is adjusted at least 0.10% compared to other portions of the semiconductor substrate; and wherein the substrate lattice spacing is about 5.4 Å at about 25° C.