Patent ID: 8412980
Filing Date: 2013-04-02
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a plurality of redundant execution pipelines disposed on at least one integrated circuit device; issue logic coupled to the plurality of redundant execution pipelines, the issue logic configured to concurrently issue a plurality of non-stability critical instructions to the plurality of redundant execution pipelines such that the plurality of non-stability critical instructions are executed in parallel by the plurality of redundant execution pipelines, the issue logic further configured to concurrently issue a plurality of instances of a stability critical instruction to multiple redundant execution pipelines from the plurality of redundant execution pipelines such that the multiple instances of the stability critical instruction are executed in parallel by the multiple redundant execution pipelines; and fault detection logic coupled to the multiple redundant execution pipelines and configured to determine a fault during execution of at least one instance of the stability critical instruction, wherein the fault detection logic is configured to initiate a pipeline flush and re-execution of the stability critical instruction in response to determining a first fault during a first attempt to execute the stability critical instruction, initiate a pipeline flush and restore to a last known good state in response to determining a second fault during a second attempt to execute the stability critical instruction, and initiate a restore to a last known good state on a different processing core in response to determining a third fault during a third attempt to execute the stability critical instruction.