Patent ID: 6150878
Filing Date: 2000-11-21
Classification: H01L

Abstract:
An integrated circuit arrangement comprising:transistors having predetermined upper voltage limits, whereinthe transistors are connected to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of said transistors, by a multi-layer metal structure;and at least one voltage reducer connected along said multi-layer metal structure between said external voltage source and said first plurality of said transistors, wherein:said plurality of transistors each comprise a first gate oxide and said voltage reducer transistor comprises a second gate oxide and wherein said second gate oxide is thicker than the first gate oxide, a thickness of said first gate oxide being not greater than 80 angstroms and a thickness of said second gate oxide being not greater than 110 angstroms,and wherein said at least one voltage reducer comprises an N-transistor having a source connected to said external voltage source, a gate connected to said external voltage source and to ground via a voltage divider including a capacitor and a drain connected to at least some of said first plurality of transistors.