Patent ID: 6615296
Filing Date: 2003-09-02
Classification: G06F

Abstract:
In a multi-processor electronic system employing a FIFO for data communication between processors, the system including a data bus having a bus latency associated therewith, the system further including first and second electronic modules connected to said bus and in communication with each other through said bus, the first module including a first processor, a first memory, and a First-In-First-Out (FIFO) memory, the first processor being electronically connected to the FIFO, the second module containing a second processor and a second memory, a method of providing improved speed FIFO data transfers comprising the steps of:providing a first FIFO READ pointer within the first memory; providing both a second FIFO READ pointer and a FIFO WRITE pointer within the second memory; (a) upon the occurrence of the first processor reading data from the FIFO, (a1) counting a number n of data that the first processor reads; and (a2) waiting until n reaches a pre-determined number N then incrementing the second READ pointer by N, where N is greater than one; (b) the second processor comparing the second READ pointer and the WRITE pointer to determine whether the FIFO is full; and (c) if the FIFO is not full then the second processor writing data into N number of locations within the FIFO.