Patent ID: 8943377
Filing Date: 2015-01-27
Classification: G01R,G06F,G11C

Abstract:
1. An integrated circuit comprising: a Logic Built-in Self-Test (LBIST) structure operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic, the LBIST structure positioned on chip with the at least one selection of core logic, the test program specifying at least one operation for the LBIST structure to run on at least one test pattern through the at least one selection of core logic, the at least one operation comprising at least one type of operation of a plurality of types of operations; the LBIST structure operative to control the at least one type of operation of the plurality of types of operations performed on the at least one selection of core logic, while running the at least one operation of the test program, by activating at least one control signal of a plurality of control signals received as inputs to the at least one selection of core logic, wherein one or more control signals of the plurality of control signals is associated with each type of operation of the plurality of types of operations; and the LBIST structure comprising a monitoring logic structure operative to detect the at least one type of operation actually performed on the at least one selection of core logic while the test program is running by monitoring the at least one control signal of the plurality of control signals activated by the LBIST structure while the LBIST structure runs the test program.