Patent ID: 9184179
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A method of forming a field effect transistor (FET) device, the method comprising: forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer, an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer in the recess, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe.