Patent ID: 6523091
Filing Date: 2003-02-18
Classification: G06F

Abstract:
A circuit that selects a candidate to mark as overwritable in the event of a cache miss, comprising:logic that receives a cache access request, wherein said cache access request is associated with a main memory address; logic that determines whether the contents of said main memory address are present in a data cache; logic that associates, when the contents of said main memory address are not present in said data cache, said main memory address with a set within said data cache, wherein said set includes a plurality of ways; logic that determines whether any of said plurality of ways is an invalid way; logic that selects, if said invalid way exists, said invalid way as the candidate; cache replacement logic that selects, where no said invalid way exists among said set, a way among said set as a preliminary candidate, wherein said cache replacement logic is based on the state of at least one affected resource.