Patent ID: 8866214
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. A transistor structure, comprising: a substrate having a surface and overlying said surface of said substrate, a source comprised of a first layer of semiconductor material; a drain comprised of a second layer of semiconductor material; and a channel comprised of a third layer of semiconductor material, said channel being disposed vertically to and perpendicular with respect to said surface of said substrate between a first surface of said first layer of semiconductor material of said source and a first surface of said second layer of semiconductor material of said drain, said channel being coupled to a gate conductor that surrounds said channel via a layer of gate dielectric material that is disposed between said gate conductor and said channel, where said gate conductor is comprised of a first layer of first electrically conductive material having a first work function that surrounds a first portion of a length of said channel, and where said gate conductor is further comprised of a second layer of second electrically conductive material having a second work function that surrounds a second portion of the length of said channel, where said first layer of first electrically conductive material and said second layer of second electrically conductive material are disposed vertically adjacent to one another and together surround the length of said channel, further comprising a first layer of dielectric material having a bottom surface disposed on and overlying a second surface of one of said first layer of semiconductor material or said second layer of semiconductor material in dependence on whether said source or said drain is disposed vertically above the channel, where said layer of gate dielectric material is disposed on a top surface of said first layer of dielectric material and on side surfaces of said first layer of dielectric material, a second layer of dielectric material disposed upon said layer of gate dielectric material and upon a top surface of said gate conductor; a first electrical contact formed through a portion of said second layer of dielectric material and through a portion of said layer of gate dielectric material that is disposed on the top surface of said layer of dielectric material, said first electrical contact also being formed through said first layer of dielectric material to conductively connect to said second surface of one of said first layer of semiconductor material or said second layer of semiconductor material in dependence on whether said source or said drain is disposed vertically above the channel; a second electrical contact formed through said second layer of dielectric material to conductively connect to said gate conductor; and a third layer of dielectric material comprising a semiconductor oxide, said third layer of dielectric material being disposed between and in contact with said first layer of semiconductor material or said second layer of semiconductor material, in dependence on whether said source or said drain is disposed vertically above the channel, and an overlying portion of said layer of gate dielectric material that is disposed beneath said gate conductor.