Patent ID: 6087845
Filing Date: 2000-07-11
Classification: G01R,H01L,H05K

Abstract:
An apparatus for testing an array of semiconductor dice located on a wafer, said wafer having a first side having said array of semiconductor dice located thereon and a second side, comprising:a first support member configured to receive said array of semiconductor dice located on said wafer in a predetermined orientation, said first support member including:a biasing assembly located thereon, said biasing assembly biasing said array of semiconductor dice located on said wafer in a first direction by engaging said second side of said wafer;a second support member configured to receive said wafer therein and to selectively engage said first support member to retain said array of semiconductor dice located on said wafer therebetween; anda substrate including:electrical traces oriented to establish electrical contact with said array of semiconductor dice located on said first side of said wafer, said substrate retained by said array of semiconductor dice located on said first side of said wafer by said first support member engaging a portion of said second support member and biased against said array of semiconductor dice located on said first side of said wafer by said biasing assembly located on said first support member engaging said second side of said wafer.