Patent ID: 7205192
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: forming an inter-layer dielectric layer on a semiconductor substrate; forming a contact hole by etching the inter-layer dielectric layer selectively; forming a suicide layer at the bottom of the contact hole; forming a diffusion barrier layer on the silicide layer and on sides of the contact hole, without filling up the trench, to thereby make an empty trench without any etching process; filling up the empty trench with a single oxidation barrier layer on the diffusion barrier layer; removing the diffusion barrier layer and the oxidation barrier layer until the inter-layer dielectric layer is exposed; forming a bottom electrode of a capacitor contacting the diffusion barrier layer and the oxidation barrier layer; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer.