Patent ID: 6569760
Filing Date: 2003-05-27
Classification: H01L,Y10S

Abstract:
A method for fabricating a via openings, comprising the steps of:providing a semiconductor structure; forming a low-k layer upon the semiconductor structure; forming a via opening within the low-k layer; forming an inert polymer liner layer upon the low-k layer and within the via opening; wherein the inert polymer liner layer is a (CF2)n polymer formed under the conditions including: a pressure from about 5 to 200 mTorr; power from about 50 to 500 W; and from about 10 to 300 sccm CH2F2 in from about 5 to 200 sccm Ar carrier gas; forming, by photolithography and etching, a structure opening within the low-k layer; and forming a planarized metal structure within the structure opening.