Patent ID: 6072743
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A semiconductor memory device formed at a memory region of a main surface of a semiconductor substrate, comprising:a plurality of memory blocks arranged to surround the center of the memory region of the main surface of said semiconductor substrate, each said memory block including:(a) a plurality of word lines;(b) a plurality of bit lines crossing said plurality of word lines;(c) a plurality of memory cells corresponding to crossings of said plurality of word lines and said plurality of bit lines;(d) a row decoder connected to said plurality of word lines; and(e) a column decoder selecting a bit line from among said plurality of bit lines; anda control circuit arranged at a center portion of the memory region of said main surface of said semiconductor substrate for providing control signal to said plurality of memory blocks, said control circuit including:(a) a master control circuit arranged at a center of said control circuit and generating a reference signal by which all of said plurality of memory blocks operate accordingly; and(b) a plurality of local control circuits arranged to surround said master control circuit, each local control circuit receiving said reference signal to output said control signal to a corresponding memory block.