Patent ID: 6618315
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A non-volatile, electrically alterable semiconductor memory comprising:at least one array of memory cells arranged in a plurality of rows and a plurality of columns; a write circuit for simultaneously writing a selected number of memory cells; a plurality of doped semiconductor regions extending transversely to the rows and dividing the memory cells of each row into a plurality of subsets of memory cells, each subset of memory cells within the same doped semiconductor region defining an independently erasable memory block; a plurality of column packets, each column packet comprising at least one column of memory cells, the number of columns of memory cells in each column packet being greater than or equal to the selected number of memory cells; and a column selection circuit for selecting columns of memory cells such that columns of memory cells comprising memory cells that are simultaneously written by said write circuit are distributed among said plurality of column packets so as to be a maximum distance from one another within each column packet.