Patent ID: 6872594
Filing Date: 2005-03-29
Classification: H01L

Abstract:
1. A method of fabricating an electronic component having semiconductor chips stacked on one another and connected via rewiring planes and through contacts formed at sawn edges of the semiconductor chip, the method which comprises the following steps: providing a semiconductor wafer with semiconductor chips arranged in rows and columns and sawing track regions therebetween; applying an insulating layer for protection and for insulation of an active top side of the semiconductor chips; forming through contact holes in the sawing track regions, the contact holes having a diameter greater than a width of a saw blade for dicing the semiconductor wafer; coating an inner wall of the through contact holes with at least one of an adhesion promoter and a solderable surface coating; filling the through contact holes with solder material to form through contacts; patterning the insulating layer by uncovering contact areas on the active top side of the semiconductor chip and applying interconnects for rewiring on the insulating layer, the interconnects for rewiring connecting individual contact areas to the through contacts; dicing the semiconductor wafer to form semiconductor chips; and stacking a plurality of semiconductor chips to form an electronic component.