Patent ID: 6395631
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A method for forming within a low dielectric constant dielectric layer upon a semiconductor substrate employed within an integrated circuit microelectronics fabrication a patterned microelectronics conductor layer employing lift off of a hard mask layer comprising:providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer within which are conductor regions therein forming a first patterned microelectronics conductor layer; forming over the first patterned microelectronics conductor layer a low dielectric constant dielectric layer; forming over the low dielectric constant dielectric layer a hard mask layer; forming over the hard mask layer a first patterned photoresist etch mask layer; etching, while employing a first subtractive etching environment and the first patterned photoresist etch mask layer, a pattern into and through the hard mask layer; etching, while employing a second etching environment and the patterned hard mask layer, the pattern into and through the low dielectric constant dielectric layer to the underlying conductor regions and stripping the first patterned photoresist etch mask layer; forming over the patterned hard mask layer a microelectronics conductor layer; and delaminating and lifting off the patterned hard mask layer employing wet chemical treatment, to leave behind a second patterned microelectronics conductor layer.