Patent ID: 6309918
Filing Date: 2001-10-30
Classification: H01L,Y10S

Abstract:
A manufacturable GaAs VFET process comprising the steps of:providing a substrate structure including a doped GaAs supporting substrate, a lightly doped first epitaxial layer including GaAs positioned on a first surface of the supporting substrate, and a heavily doped second epitaxial layer including GaAs positioned on the first epitaxial layer;depositing a temperature tolerant conductive layer on the second epitaxial layer;patterning the conductive layer to define a plurality of source areas underlying portions of patterned conductive layer;using the portions of patterned conductive layer, etching a plurality of gate trenches into the first epitaxial layer of the substrate structure adjacent the source areas, the gate trenches having bottoms spaced vertically from the second epitaxial layer;implanting material in the bottoms of the gate trenches to form implanted gate areas in the gate trenches and activating the implanted gate areas;depositing a gate contact in communication with the implanted gate areas by depositing a thin metal layer on the implanted gate areas to reduce gate resistance wherein the step of etching the plurality of gate trenches included undercutting the portions of patterned conductive layer to prevent metal from being deposited on trench sides during the step of depositing the thin metal layer on the implanted gate areas;depositing a source contact in communication with the portions of patterned conductive layer overlying the source areas; anddepositing a drain contact on a second surface of the substrate structure.