Patent ID: 6124733
Filing Date: 2000-09-26
Classification: H03K

Abstract:
A buffer comprising:a first inverter having an input providing the buffer input and an output providing the buffer output, the first inverter comprising:a first PMOS transistor having a source to drain path coupling Vdd to the buffer output and a gate coupled to the buffer input; anda first NMOS transistor having a source to drain path coupling the buffer output to Vss and a gate coupled to the buffer input;a second PMOS transistor;a second NMOS transistor; anda threshold altering means coupled to the buffer input, the buffer output and to the second PMOS and NMOS transistors, the threshold altering means enabling the source to drain path of the second NMOS transistor to provide Vss to the buffer output for a first time period after the buffer input transitions from low to high, the first time period beginning after the buffer output transitions in response to the low to high buffer input transition and potentially ending before the input transitions from high back to low, the threshold altering means preventing the source to drain path of the second NMOS transistor from providing Vss to the buffer output before and after the first time period, the threshold altering means further enabling the source to drain path of the second PMOS transistor to provide Vdd to the buffer output for a second time period after the buffer input transitions from high to low, the second time period beginning after the buffer output transitions in response to the high to low buffer input transition and potentially ending before the buffer input transitions from low back to high, the threshold altering means preventing the source to drain path of the second PMOS transistor from providing Vdd to the buffer output before and after the second time period.