Patent ID: 8458443
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A processor for use in connection with a system memory, the processor comprising: a load unit for fetching a first instruction from a first unique instruction queue and processing the first instruction, the processing comprising (i) reading data out of the system memory, and (ii) storing the read data in a first data queue; an execution unit for fetching a second instruction from a second unique instruction queue and processing the second instruction, the processing comprising (i) reading the data from the first data queue, (ii) processing the data, and (iii) storing the processed data in a second data queue; a store unit for fetching a third instruction from a third unique instruction queue and processing the third instruction, the processing comprising (i) reading the processed data from the second data queue, and (ii) storing the processed data in the system memory; and a sequencer for managing distribution of instructions to the first, second, and third instruction queues.