Patent ID: 8943510
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A system comprising: one or more processors; one or more memories; a first thread, stored in the one or more memories and executable on the one or more processors, the first thread including a critical section of the first thread; a second thread, stored in the one or more memories and executable on the one or more processors, the second thread including a critical section of the second thread; and an execution engine, stored in the one or more memories and configured to cause execution of the first and second threads on the one or more processors using a mutual-exclusion algorithm that resists m faults, and at least prevents simultaneous execution of the critical section of the first thread and the critical section of the second thread by satisfying a hamming-distance-(m+1) property after the system experiences a soft error and when (i) one thread of the first and second threads is in a critical section, (ii) and another thread of the first and second threads is waiting in a loop to enter its critical section, wherein the soft error is a temporary hardware failure that alters a processor component, wherein m is an integer and not less than 1.