Patent ID: 7394299
Filing Date: 2008-07-01
Classification: G06F

Abstract:
1. A digital clock frequency multiplier for increasing an input frequency of an input clock signal, the digital clock frequency multiplier comprising: a generator that receives the input clock signal and a high frequency digital signal and divides a count (N a first counter that receives the input clock signal and the high frequency digital signal and generates the count N a divider coupled to the first counter that divides the count N a first latch coupled to the divider that stores predetermined values of the number of cycles C; a second counter that receives the high frequency digital signal and counts the cycles thereof; a comparator, coupled to the second counter and the first latch, that compares the counted cycles from the second counter with the predetermined values of the number of cycles C stored in the first latch; an edge generator coupled to the comparator for generating pulse signals when the counted cycles from the second counter are equal to the predetermined values of the number of cycles C stored in the first latch; and an output clock generator coupled to the edge generator for receiving the pulse signals and generating the output clock signal therefrom.