Patent ID: 6058456
Filing Date: 2000-05-02
Classification: G06F

Abstract:
A computer system comprising:a processor;a memory device;a cache connected to said processor and said memory device, having a plurality of cache blocks for storing memory blocks corresponding to addresses of said memory device;program instructions residing in said memory device and executed by said processor, for monitoring relative usage of said cache by instruction and data classes of values, by detecting instruction read requests and data read requests, and selecting a desired ratio of cache usage by said classes from among a plurality of available ratios, wherein said plurality of available ratios includes instruction/data cache block usage ratios of 1:1, 1:2, and 2:1;a 2-bit facility to indicate which of said instruction/data cache block usage ratios is to be used as said desired ratio of cache usage; anda cache-replacement mechanism for evicting cache blocks within said cache which restricts replacement of an evicted cache block to a particular one of said instruction and data classes of values based on said desired ratio of cache usage.