Patent ID: 6411669
Filing Date: 2002-06-25
Classification: H03K,H03L

Abstract:
A dual-modulus prescaler comprising:a voltage controlled oscillator (VOC) for generating a clock signal; a programmable counter for generating mode control signal; a first frequency-dividing circuit connected to the VOC and including a first flip-flop circuit for generating a latch control signal upon latching of the clock signal, a latch for selectively latching the clock signal during an enabled time of the latch control signal, a second flip-flop circuit for generating a first frequency divided signal by frequency-dividing an output clock signal of the latch, a third flip-flop circuit for generating a second frequency divided signal and a third frequency divided signal by frequency-dividing the first frequency divided signal, and an AND gate circuit connected to the third flip-flop circuit and the first flip-flop circuit; a second frequency-dividing circuit connected to the first frequency-dividing circuit and having (nâˆ’1) stages of flip-flop circuits for generating a plurality of frequency divided signals by frequency-dividing the second frequency divided signal, wherein n is a natural number equal to or greater than 2; a logic operation circuit connected to the first frequency-dividing circuit and the second frequency-dividing circuit, for generating a frequency-dividing mode control signal and supplying the frequency-dividing mode control signal to the first frequency-dividing circuit; wherein the logic operation circuit generates the frequency-dividing mode control signal by performing a logic multiplication operation on a plurality of the frequency divided signals of the second frequency-dividing circuit and the mode control signal of the programmable counter, and outputs the frequency-dividing mode control signal to the AND gate circuit of the first frequency-dividing circuit, and wherein the AND gate circuit generates a control signal by performing a logic multiplication operation on the second frequency divided signal, the third frequency divided signal and the frequency-dividing mode control signal, and outputs the control signal to the first flip-flop circuit, and wherein the first flip-flop circuit thereby controls the frequency-dividing mode according to the control signal.