Patent ID: 8941246
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an interposer substrate having a first surface provided with an external connection terminal and a second surface provided with an internal connection terminal; a chip stacked body, disposed on the second surface of the interposer substrate, having plural semiconductor chips sequentially stacked, the plural semiconductor chips being electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and a first bump electrode connecting between the through electrodes, the lowermost semiconductor chip being electrically connected to the interposer substrate via at least one semiconductor chip having the through electrode, and an uppermost semiconductor chip in the stacking order having a rewiring layer provided on a surface thereof; and an interface chip mounted on the uppermost semiconductor chip, electrically connected to the uppermost semiconductor chip via a second bump electrode, and electrically connected to the internal connection terminal via the rewiring layer.