Patent ID: 6483288
Filing Date: 2002-11-19
Classification: H03L,H04L

Abstract:
An engagement detection circuit for detecting and indicating the engagement condition of a phase control circuit in response to a data signal and a clock pulse comprising:a phase detector; a counter element having its input coupled to said detector and comprising an incrementer/decrementer, wherein said incrementer/decrementer is controlled by said phase detector so that its incrementing input or decrementing input is activated depending on a phase difference between the data signal and the clock pulse, and wherein incrementing and decrementing counts take place with different incrementations, wherein the decrement is greater than the increment; a flip-flop, coupled to the output of said counter element, so that when the clock pulse and the data signal are coupled to the input of said phase detector, its output controls said counter element, and wherein said flip-flop, connected to said counter element, is set or reset depending on the reading of said counter element; a low-pass element connected to the output of said flip-flop; and a trigger element coupled to the output of said low-pass element for providing at its output a signal when the output of low-pass element exceeds a preset threshold value.