Patent ID: 6751157
Filing Date: 2004-06-15
Classification: G06F,G11C

Abstract:
A memory system comprising:an array of memory cells, wherein each of the memory cells must be periodically refreshed to retain a data value; a terminal for receiving an external clock signal; a terminal for receiving an external access signal that is activated to indicate a requested read or write access to the array; a refresh controller configured to periodically activate a refresh request signal; and a memory array sequencer coupled to receive the external clock signal, the external access signal, and the refresh request signal, the memory array sequencer including: means for sequentially activating and then de-activating a first set of timing signals; means for enabling the first set of timing signals to implement a read or write access to the array if the external access signal is activated; and means for sequentially activating and then de-activating a second set of timing signals to implement a refresh access to the array if the refresh request signal is activated, wherein one of the first and second sets of timing signals is activated in response to the de-activation of a timing signal in the other one of the first and second sets of timing signals.