Patent ID: 6317154
Filing Date: 2001-11-13
Classification: H01L,H04N

Abstract:
An apparatus comprising:a sensor array having a plurality of groups of photocells that form substantially the entire sensor array, each group of photocells being coupled to provide output voltages on a respective bitline, each photocell in a group having a reset device coupled to reset a photodetector in response to a reset signal being asserted, a sample device coupled to provide a low impedance path between the photodetector and a storage device, a second storage device and a second sample device coupled between (1) the storage and sample devices and (2) the photodetector, and a readout circuit coupled between the storage device and the respective bitline to provide an output voltage in response to an address signal being asserted; anda controller coupled to control the sensor array by asserting a sample signal and a reset signal to generate a reset voltage at a storage node of each photocell in a first group of photocells in the sensor array, and asserting a second sample signal, while asserting the reset signal, to generate a second voltage at a second node of each photocell in the first group; and thendeasserting the reset signal prior to deasserting the sample signal so that the reset voltage is captured at the storage node; and thenasserting a first address signal to read the captured reset voltage at the storage node, waiting an integration period after deasserting the reset signal, deasserting the second sample signal at the end of an integration period for the first group before reading an exposed voltage at the storage node, and generating a difference between the exposed voltage and the captured reset voltage.