Patent ID: 7395392
Filing Date: 2008-07-01
Classification: G06F

Abstract:
1. A storage system which performs processing for one or more storages by a plurality of processors, comprising: a plurality of channel adapters that store data received from a host computer in a cache memory or a plurality of disk adapters which store data stored in the cache memory in the storages, the plurality of processors, wherein each of said plurality of channel adapters or disk adapters comprises a processor of the plurality of processors; a plurality of local memories which are respectively provided for said plurality of processors, wherein each of said plurality of channel adapters or disk adapters comprises a local memory of the plurality of local memories; a memory for storing control information communicated between said plurality of channel adapters or said plurality of disk adapters; a controller connected to said memory for storing control information; and one or more intermediate devices connected to said plurality of processors and said controller so that communications are possible, wherein each of said plurality of local memories has a plurality of local memory addresses and local memory regions respectively corresponding to said plurality of local memory addresses, wherein a first intermediate device that is connected to one processor of said plurality of processors transmits to said controller a first access message including a designated value which is a value designated by the one processor of said plurality of processors, wherein said controller receives the first access message from said first intermediate device, specifies a local memory address corresponding to the designated value included in said received first access message, and transmits a second access message including the specified local memory address to two or more other processors of said plurality of processors, said two or more other processors being different from said one processor of said plurality of processors, wherein a second intermediate device respectively connected to said two or more other processors receives said second access message, and said second intermediate device or said two or more other processors access the local memory regions of two or more local memories respectively corresponding to said two or more other processors, which are local memory regions corresponding to local memory addresses included in said second access message, wherein said controller controls the locking on and locking off of each of the local memory addresses, wherein, in cases where the local memory address corresponding to the designated value included in said received first access message is locked off, said controller locks on this local memory address, and said first access message is subsequently processed, and said controller locks off said local memory address at a timing following the transmission of said second access message, wherein, in cases where the local memory address corresponding to the designated value included in said received first access message is locked on, said controller executes the processing of said first access message after said local memory address is locked off, wherein said plurality of processors send a request to said controller requesting that the local memory address corresponding to the local memory region be locked on before reading out data from this local memory region of the local memory prepared for each of said plurality of processors, wherein said controller transmits notification to said plurality of processors as to whether or not the local memory addresses that are the object of requests from said plurality of processors have been successfully locked on, and wherein, in cases where notification that locking on has been successfully accomplished is received by said plurality of processors, said plurality of processors read out data from said local memory regions.