Patent ID: 7782990
Filing Date: 2010-08-24
Classification: H03L,H04L

Abstract:
1. A method of oversampling a signal in an integrated circuit, the method comprising: receiving a reference clock signal; generating at least one delayed clock signal based upon the reference clock signal, each delayed clock signal having a different phase; receiving an input data signal; generating at least one delayed data signal based upon the input data signal; and generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal, selected from the at least one delayed clock signal and the reference clock signal, and a data signal, selected from the at least one delayed data signal and the input data signal, wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals and wherein each data signal of the at least one delayed data signal and the input data signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals, and wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used with each data signal of the at least one delayed data signal and the input data signal to generate the plurality of phase-shifted output signals.