Patent ID: 8352835
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A method for data verification in a storage subsystem by at least one processor device in communication with at least one memory device, the method comprising: asynchronously submitting a read of data to nonvolatile storage media; asynchronously submitting a read of a first checksum signature to a solid state, sidefile memory location of a storage controller in the storage subsystem, wherein asynchronously submitting the read of the first checksum signature to the solid state, sidefile memory location includes submitting the read to a storage module of the storage controller responsible for the nonvolatile storage media and the first checksum signature is representative of the data previously written to the nonvolatile storage media and the solid state sidefile memory location is one of an available plurality of solid state sidefile memory locations associated with each of an available plurality of storage modules in the storage controller; calculating a second checksum signature from the read of the data; and comparing the first and second checksum signatures, wherein if a match is not determined, reporting a critical event.