Patent ID: 7200721
Filing Date: 2007-04-03
Classification: G11C

Abstract:
1. A computer-implemented method for testing memory operations in a multiprocessor data processing arrangement, comprising: logically partitioning a selected portion of memory into partitions respectively associated with a plurality of threads; assigning disjoint sets of values to the threads for writing to the associated partitions; wherein each partition is defined by a beginning offset, an ending offset, a contiguous byte count, and an increment value, the beginning offset being a position in the selected portion of memory, relative to a starting address of the portion of memory, at which the partition begins, the ending offset being a position in the selected portion of memory, relative to the starting address of the portion of memory, at which the partition ends, the contiguous byte count being a number of consecutively addressed bytes that belong to the partition, and the increment value being a number of bytes that are not in the partition and that separate two sets of contiguously addressed bytes of the partition; writing the sets of values to memory by the plurality of threads; verifying that values in the memory are consistent with the values written by the plurality of threads; measuring performance characteristics of the data processing system while writing the values; and selectively adjusting, in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads.