Patent ID: 6316815
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for forming a trench isolation structure in a semiconductor substrate, comprising the steps of(a) forming a first layer overlying the semiconductor substrate;(b) forming a second layer overlying said first layer;(c) patterning said second layer and said first layer to expose a portion of said semiconductor substrate, and etching said semiconductor substrate from the exposed portion thereof to form at least a trench having an exposed surface;(d) forming a liner layer to cover the exposed surface of said trench;(e) coating a photoresist layer filling said trench and overlying the patterned second layer (oxidation barrier layer);(f) removing a portion of said photoresist layer to expose an upper surface of said second layer laterally adjacent said trench, the upper surface of said trench adjacent second layer portion being the surface opposite to the surface between said semiconductor substrate and said trench adjacent second layer portion;(g) etching said trench adjacent second layer portion from the exposed upper surface thereof to said first layer to create an empty space and to leave a remaining second layer portion;(h) removing said photoresist layer;(i) depositing a dielectric to fill said trench and form a dielectric stud defined by said trench, the patterned first layer, and said remaining second layer portion;(j) removing said remaining second layer portion to leave an exposed portion of the patterned first layer, and(k) removing the exposed portion of the patterned first layer.