Patent ID: 7796136
Filing Date: 2010-09-14
Classification: G06F,G09G

Abstract:
1. An image signal processing apparatus comprising: an image pickup device that outputs an image signal obtained by picking up an image from a subject; a signal processing circuit that subjects the image signal output from said image pickup device to signal processing; a VRAM (Video Random Access Memory) section composed of at least three VRAM areas that store the image signals output from said signal processing circuit, each of the output image signals being written selectively into one of the VRAM areas, wherein the number of the VRAM areas is changeable; a VRAM management information storing section that stores management information including information indicating writing order of the corresponding VRAM area for which writing is to be completed, and information indicating that the corresponding VRAM area is the last VRAM area for which writing has been lastly completed; a compression circuit that reads an image signal stored in the corresponding VRAM area for which writing has been completed based on the management information stored by said VRAM management information storing section, at a first reading speed in accordance with the writing order, and subjects the read image signal to compression processing, wherein the management information further includes memory write information indicating whether or not reading of an image signal to said compression circuit from the corresponding VRAM area is completed; an image display processing circuit that reads an image signal stored in the last VRAM area, based on the management information stored by said VRAM management information storing section, at a second reading speed, and subjects the read image signal to image display processing, wherein the management information further includes memory read information indicating whether or not reading of an image signal from the last VRAM area is being carried out; and a memory controller that: