Patent ID: 6434641
Filing Date: 2002-08-13
Classification: G06F

Abstract:
For use in a data processing system including multiple data processors coupled to a shared main memory, the shared main memory for receiving requests from the data processors to access a data item in the shared main memory, ones of the data processors being coupled to one or more cache memories for storing the data items retrieved from the shared main memory, and wherein the shared main memory stores directory state information that is used to determine when coherency operations must be initiated to maintain memory coherency between the shared main memory and the cache memories, a system for filtering ones of the requests received by the main memory, comprising:a storage device to store predetermined ones of the requests until processing of the requests is completed; directory logic coupled to said storage device, said directory logic to receive the directory state information from the shared main memory and to designate ones of said stored requests as deferred requests, wherein each of said deferred requests will only be designated as completely processed when an associated predetermined one of said coherency operations is completed; compare logic coupled to said storage device to receive each of said predetermined ones of the requests as said predetermined ones of the requests are provided by the data processors, and to generate, for each of said predetermined ones of the requests, compare signals if one or more of said stored requests is requesting access to the same data item as any other received one of said predetermined ones of the requests wherein said compare logic includes link address generation circuits to generate said compare signals to include, for each of said predetermined ones of the requests that is requesting access to the same data item as one or more of said stored requests, a respective link address, said respective link address to point to an address within said storage device that stores a predetermined one of said one or more stored requests that is requesting access to the same data item as said each of said predetermined ones of the requests; and storage write control logic coupled to said compare logic to receive said compare signals, and to cause any requests for which compare signals were generated by said compare logic to be stored in said storage device as deferred requests.