Patent ID: 7838927
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A multi-drain power electronic device, comprising: a drain semiconductor layer formed on a semiconductor substrate of a first type of conductivity, the drain semiconductor layer including a first semiconductor layer on said semiconductor substrate, a second semiconductor layer above the first semiconductor layer, and a semiconductor surface layer above the second semiconductor layer, the first semiconductor layer and surface layer each having the first type of conductivity and the second semiconductor layer having a second type of conductivity; a plurality of body regions of the second type of conductivity formed in said semiconductor surface layer; a first plurality of column regions of the first type of conductivity formed in said drain semiconductor layer; and a second plurality of column regions of the second type of conductivity in said drain semiconductor layer, each of the column regions of the first plurality being laterally defined by consecutive column regions of the second plurality, each of the column regions of the second plurality being laterally delimited, by consecutive column regions of the first plurality, said second plurality of column regions being vertically aligned with said plurality of body regions, respectively, and each column region of said first plurality of column regions including a plurality of doped regions of the first type of conductivity positioned in contact with, and on top of, one another in the second semiconductor layer, wherein each column region of said second plurality of column regions has a maximum width less than a maximum width of each column region of said first plurality of column regions.