Patent ID: 8377776
Filing Date: 2013-02-19
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: providing a substrate, the substrate comprising a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area; forming a first well of a first conductivity type in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area; forming two separate second wells of a second conductivity type in the first well in each of the high voltage circuit area and the medium voltage circuit area; forming two separate isolation structures respectively in the second wells in each of the high voltage circuit area and the medium voltage circuit area; forming a first gate dielectric layer in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area; removing the first gate dielectric layer in the medium voltage circuit area and the low voltage circuit area; forming a second gate dielectric layer in each of the medium voltage circuit area and the low voltage circuit area, wherein a thickness of the second gate dielectric layer is smaller than a thickness of the first gate dielectric layer; forming a gate on the first gate dielectric layer in the high voltage circuit area and on the second gate dielectric layer in each of the medium voltage circuit area and the low voltage circuit area; and forming two source and drain regions of the second conductivity type respectively in the second wells beside the gate in each of the high voltage circuit area and the medium voltage circuit area and in the first well beside the gate in the low voltage circuit area.