Patent ID: 8766225
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A storage device comprising: a plurality of row lines arranged parallel to one another; a plurality of column lines arranged parallel to one another to intersect with the row lines; and a memory cell which is disposed at each of intersections of the row lines and the column lines and which comprises a resistance-change element and a diode connected in series to the resistance-change element, the diode comprising a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region of a semiconductor containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type, wherein an impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region, and a thickness of the second semiconductor region in a stacking direction is less than about 100 nm and is shorter than a distance of a depletion layer defined by (2∈Vd/eN)