Patent ID: 7889554
Filing Date: 2011-02-15
Classification: G06F,G11C

Abstract:
1. In a memory system including re-programmable non-volatile memory cells organized into distinct blocks of a minimum number of memory cells that are simultaneously erasable and a buffer memory, the blocks of memory cells being further organized into a plurality of sub-arrays that individually have at least one storage register associated therewith, a method of operating the system, comprising: receiving user data to be programmed into the memory system and temporarily storing the received user data in the buffer memory, transferring user data from the buffer memory to the storage registers, a portion of the user data stored in the buffer memory being moved into one of the storage registers at a time, storing in at least one of the blocks a record of the individual blocks that are identified for storing user data that includes logical addresses assigned to the individual blocks identified for storing user data, accessing the record in response to receiving logical addresses by determining the physical addresses that correspond with the received logical addresses, programming user data in parallel from their associated storage registers into a plurality of physical blocks within a plurality of sub-arrays in response to receiving logical addresses; and storing, in at least one other block different than the blocks identified for storing user data, information of physical characteristics of the blocks identified to store user data or their operation.