Patent ID: 7633143
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. A semiconductor package primarily comprising: a plurality of leads and a die pad of a leadframe, the die pad including a first die-attaching area and a second die-attaching area, wherein the first die-attaching area and the second die-attaching area are horizontally disposed; a first chip disposed on the first die-attaching area; a second chip disposed on the second die-attaching area in side-by-side relationship with the first chip; and an encapsulant encapsulating a plurality of internal lead portions of the leads, the die pad, the first chip, and the second chip; wherein the thickness of the second chip is larger than the one of the first chip, and the second die-attaching area is downset relative to the first die-attaching area in a manner that a bottom surface of the encapsulant is closer to the second die-attaching area than to the first die-attaching area.