Patent ID: 8134202
Filing Date: 2012-03-13
Classification: H01L

Abstract:
1. A capacitorless one-transistor (1T) semiconductor device, comprising: a buried insulating layer on a substrate; an active region on the buried insulating layer, the active region including a source region, a drain region, and a floating body between the source region and the drain region; and a gate pattern on the floating body, wherein the floating body includes a main floating body and a first upper floating body directly contacting and being integral with each other, top surfaces of the main floating body and at least one of the source region and the drain region facing away from the buried insulating layer being substantially coplanar, and the first upper floating body being between the main floating body and the gate pattern, and wherein the floating body further includes a flank floating body, the flank floating body having a top surface at a lower height than a top surface of the upper floating body, the flank floating body being positioned between the main floating body and at least one of the source and drain regions.