Patent ID: 6159806
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method for forming a semiconductor device, said method comprising:providing a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on said substrate;sequentially forming a polysilicon layer, a conductive layer, and a first dielectric layer on said gate oxide layer;patterning to etch said first dielectric layer, said conductive layer, said polysilicon layer, and said gate oxide layer to form an interior gate and a peripheral gate;implanting first ions into said substrate of the interior and the peripheral circuit;conformal depositing a second dielectric layer above said substrate, interior gate and peripheral gate, wherein etching second dielectric layer to form a spacer of the interior gate and the peripheral gate;conformal depositing third dielectric layer above said substrate of interior and a peripheral circuit,blanket forming a first photoresist layer on said third dielectric layer of the interior circuit;implanting second ions of the same conductive type into said substrate of peripheral circuit to form a source/drain by using said peripheral gate, said spacer and a portion of said third dielectric layer which runs along said spacer as a mask;removing the first photoresist layer;blanket depositing an inter-polysilicon dielectric on the dielectric layer;forming a second photoresist layer having first pattern on said a inter-polysilicon dielectric of interior circuit and second pattern on said a inter-polysilicon dielectric of periphery circuit; andanisotropically etching the inter-polysilicon dielectric of interior and peripheral circuit to form a plurality of contacts.