Patent ID: 8900939
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A method of fabricating a transistor, the method comprising: forming a first layer structure comprising Aluminum Nitride, Aluminum Gallium Nitride or Gallium Nitride above laterally extending source, drain and gate regions of a semiconductor body; forming a barrier material layer above the first layer structure with a substantially uniform thickness throughout the source, drain and gate regions, the barrier material layer comprising at least one of Aluminum Gallium Nitride and Indium Aluminum Nitride; forming an enhanced channel charge inducing material layer (ECCIML) on the barrier material layer in the source, drain and gate regions, the ECCIML layer comprising at least one of Aluminum Nitride, Aluminum Gallium Nitride and Indium Aluminum Nitride; oxidizing the ECCIML layer to thin the ECCIML layer and to form Aluminum Oxide above the barrier material layer in at least a portion of the gate region without altering the thickness of the barrier material layer; forming a gate structure above at least a portion of the gate region with at least a portion of the gate structure extending downward to and at least partially engaging a top surface of the Aluminum Oxide in the gate region; forming a source structure above at least a first portion of the ECCIML layer in the source region; forming a drain structure above at least a second portion of the ECCIML layer in the drain region; forming a source structure electrode in the source region in contact with the 2DEG or 2DHG; and forming a drain structure electrode in the drain region in contact with the 2DEG or 2DHG.