Patent ID: 7961543
Filing Date: 2011-06-14
Classification: G11C

Abstract:
1. A semiconductor memory device that refreshes a plurality of memory banks installed therein, the semiconductor memory device comprising: a command receiver/decoder that receives an externally supplied command, decodes the command, and outputs a refresh instruction when a decoded result indicates that the command is an auto-refresh command; a refresh command generating circuit that outputs a refresh command a predetermined number of times determined as the number of word lines to be subjected to a refresh operation in response to receipt of the refresh instruction; and a refresh address counter that counts up an address designating a memory bank and a word line every time the refresh command is received, wherein the refresh command generating circuit comprises a refresh number control circuit that controls the predetermined number of times that the refresh command is to be output in response to one refresh instruction, and the predetermined number of times is equal to the number of refresh operations in the case in which each of the plurality of memory banks is refreshed and, after a count value designating a word line of the refresh address counter has been changed, a part of the plurality of memory banks, the number of the part of the plurality of memory banks being greater than or equal to one and less than the number of the plurality of memory banks, is further refreshed.