Patent ID: 7571422
Filing Date: 2009-08-04
Classification: G03F

Abstract:
1. A method for generating a design rule map having a spatially varying design rule overlay budget, the method comprising: providing a design data file that characterizes a fabrication process used for forming a pattern on a semiconductor substrate where information contained in the design data file includes pattern information concerning patterns formed on a first layer of a semiconductor substrate and pattern information concerning patterns formed on a second layer that is formed over the first layer of a semiconductor substrate; processing the information contained in the design data file to generate a design map that includes a spatially varying overlay error budget for the design map using a computer processor, comprising: where the spatially varying overlay error budget defines a localized tolerance to overlay errors for different spatial locations on the design map, with portions of the map having a pattern that is relatively tolerant of overlay error having a relatively larger overlay error budget and portions of the map having a pattern that is relatively intolerant of overlay error having a relatively smaller overlay error budget, thereby defining an design map having a spatially varying overlay error budget.