Patent ID: 6756792
Filing Date: 2004-06-29
Classification: G01R,G11C

Abstract:
An apparatus for measuring parasitic capacitances of an integrated circuit, comprising:a test structure having a first conductor and a second conductor; a reference structure having a third conductor; a first switch for selectively connecting said first conductor to a first voltage source and a second switch for selectively connecting said first conductor to ground potential; a third switch for selectively connecting said third conductor to a second voltage source and a fourth switch for selectively connecting said third conductor to ground potential; said reference structure having a fourth conductor connected to said third switch for selectively connecting said fourth conductor to said second voltage source and to said fourth switch for selectively connecting said fourth conductor to ground potential; wherein a coupling capacitance between said first conductor and said second conductor substantially equals a coupling capacitance between said third conductor and said fourth conductor; wherein said first, second, third, and fourth conductors are constructed such that said first and second conductors and said third and fourth conductors respectively have substantially equally large inherent capacitances; and wherein said second conductor is directly connected to reference potential, such that said first conductor and said second conductor can assume mutually different potentials.