Patent ID: 8076723
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A power transistor device comprising: a substrate of a first conductivity type; a buffer layer of a second conductivity type opposite to the first conductivity type disposed on the substrate, the buffer layer having a top surface; a pillar of semiconductor material having a bottom that adjoins the buffer layer, a top surface, first and second sidewall portions, a first lateral width, and a first thickness that extends from the top surface down to the bottom; a body region of the first conductivity type in the pillar; a first region of the second conductivity type in the pillar, the first region being disposed at the top surface, the body region separating the first region of the pillar from a drift region that extends from the body region to the bottom, the drift region being of the second conductivity type; first and second dielectric layers that respectively cover the first and second sidewall portions from at least just beneath the body region down to the bottom; and a gate member disposed adjacent to and insulated from the body region.