Patent ID: 7314788
Filing Date: 2008-01-01
Classification: H01L

Abstract:
1. A method for use in manufacturing a CMOS device cell, comprising: forming a first CMOS transistor in a first CMOS transistor doped region that is located in a first doped well of the CMOS device cell, wherein the first CMOS transistor doped region is configured to be biased with a power supply potential; forming a second CMOS transistor in a second CMOS transistor doped region that is located in a second doped well of the CMOS device cell, wherein the second CMOS transistor doped region is configured to be biased with a ground potential, and wherein the first and second doped wells have opposite dopant types; forming a first tap cell doped region in the first doped well, wherein the first tap cell doped region has the same dopant type as the first doped well and a higher dopant concentration relative to the first doped well; and forming a second tap cell doped region in the second doped well, wherein the second tap cell doped region has the same dopant type as the second doped well and a higher dopant concentration relative to the second doped well, and wherein each of the first and second tap cell doped regions is configured to be biased with a potential that is different relative to each of the power supply and ground potentials.