Patent ID: 6191023
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating an integrated circuit and other devices on a substrate, the method comprising the following steps:providing a substrate;providing said substrate with a layer of dielectric, termed an interlevel dielectric (ILD) over the substrate;providing a first level of metal wiring being defined and embedded in a first layer of insulator over the layer of dielectric;depositing a blanket of passivating dielectric layer (IMD) over the defined said first level of metal wiring;patterning and etching the said passivating dielectric (IMD) to form special interlocking grid structures with open contact regions to underlying first level metal wiring;depositing a blanket of a metal barrier layer;patterning and defining the said metal barrier layer on top of the interlocking grid structures;depositing a blanket of a metal layer for metal pad formation on top of the interlocking grid structures;patterning and defining the said metal pad layer to form metal pads on interlocking grid structures;repeating the above process stops to construct multilevel pad structures by this robust method to form metal pad contact structures for chips and IC's.