Patent ID: 7225346
Filing Date: 2007-05-29
Classification: G06F,Y02D

Abstract:
1. An information processor including a central processing unit having an instruction execution module, said central processing unit having a normal mode for operating said instruction execution module and an execution halt mode for halting said instruction execution module; said information processor comprising: a voltage controlling module for causing said instruction execution module to execute a voltage reduction instruction for placing said central processing unit into a low-voltage operation mode in which the operating voltage of said central processing unit is lowered from the operating voltage in said normal mode when said central processing unit switches from said normal mode to said execution halt mode; a mode controlling module for placing said central processing unit into a low-voltage halt mode in which said instruction execution module is halted under the operating voltage for said low-voltage operation mode after said voltage controlling module places said central processing unit into said low-voltage operation mode; wherein said central processing unit periodically receives an interrupt request, said interrupt request being an interval timer interrupt provided periodically to said central processing unit to cause said instruction execution module to execute periodically a set of instructions for detecting an executable process; and when said mode controlling module places said central processing unit into said low-voltage operation mode in response to said interval timer interrupt, said voltage controlling module causes said instruction execution module to execute a voltage raise instruction to place said central processing unit into said normal mode, provided that an executable process is detected; and if no executable process is detected, said mode controlling module places said central processing unit into said low-voltage halt mode.