Patent ID: 6888766
Filing Date: 2005-05-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell block which includes a memory cell unit having a plurality of memory cells each containing a ferroelectric capacitor, and a test memory cell unit having a plurality of test memory cells, wherein a layout pattern of said test memory cells is identical to a layout pattern of said memory cells, and wherein said test memory cell unit is provided adjacently to said memory cell unit; and a sense amplifier externally connected to said memory cell block, wherein said plurality of memory cells and said plurality of test memory cells are arranged in a same number of rows, said memory cell block comprises a plurality of test auxiliary memory cell units, said test auxiliary memory cell units each comprise a plurality of test auxiliary memory cells arranged in said same number of rows, a layout pattern of said test auxiliary memory cells is identical to the layout pattern of said memory cells, and each of said plurality of test auxiliary memory cells is activated by an activation signal which is externally input to said test auxiliary memory cell units, and is connected to said sense amplifier by a bit line which is common with each of the plurality of memory cells and each of the plurality of test memory cells contained in a same row.