Patent ID: 6204687
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A programmable logic device including:a plurality of configurable logic blocks connected by configurable interconnect resources;a configuration memory array including a plurality of cells coupled to the configurable logic blocks and the configurable interconnect resources;an input terminal for receiving a configuration bit stream including a header word and a second word;a bidirectional configuration bus;a plurality of configuration registers respectively having first data terminals connected to the bidirectional configuration bus and second data terminals connected to the configuration memory array; anda bus interface circuit connected between the input terminal and the bidirectional configuration bus, the bus interface circuit including an address decoder for decoding an register address field from the header word and for transmitting a register enable signal to a selected configuration register when the register address field matches a predetermined address value assigned to the selected configuration register, wherein the selected configuration register is enabled by the register enable signal to receive the second word from the data bus.