Patent ID: 8990501
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. A multiple processor system including: a first cluster including a first plurality of processors associated with a first cluster cache, wherein at least one of the first plurality of processors is associated with a first private cache level, wherein at least a portion of data in the first private cache level that is not maintained to be coherent is always not cached in a shared cache level included in the first cluster cache and data cached in the shared cached level is maintained to be coherent in the first private cache level; a second cluster including a second plurality of processors associated with a second cluster cache, wherein at least one of the second plurality of processors is associated with a second private cache level; a first communication interface connected to the first cluster via a first electrically non-shared interconnect, wherein the first communication interface is not included in the first cluster; a second communication interface connected to the second cluster via a second electrically non-shared interconnect, wherein the second communication interface is not included in the second cluster; an on-chip component comprising a first memory controller; an off-chip component comprising a second memory controller; a switch routing data between the first communication interface, the second communication interface, the first memory controller, and the second memory controller, wherein the first memory controller communicates with the first cluster and the second cluster via the switch; and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster; wherein: