Patent ID: 6483765
Filing Date: 2002-11-19
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell arrays; bit line sense amplifier arrays, each of which includes a bit line sense amplifier, arranged between shared memory cell arrays, and at least one switching array arranged between the bit line sense amplifiers and the memory cell arrays being corresponding to the bit line sense amplifiers, respectively, for switching connection states therebetween; and a bit line selection control means for controlling repeatedly activation and precharge periods of respective memory cell arrays and providing control signals corresponding to the activation and precharge periods of the switching arrays, wherein at the present activation period, the control signals are divisionally provided as follows: when the control signal is a high voltage level, a first mode for maintaining the high voltage level during a precharge period and successively an activation period, a second mode for lowering it to a ground voltage level during successively an activation period after maintaining the high voltage level during the precharge period; when the control signal is a power voltage level, a third mode for maintaining a power voltage level during a precharge period and raising it to a high voltage level during successively activation period when the control signal is a power voltage level at the present activation period, a fourth mode for maintaining the power voltage level during a precharge period and thereafter lowering to the ground voltage level during a successive activation period, a fifth mode for maintaining the power voltage level during the precharge period and the successive activation period; when the control signals is the ground voltage level, a sixth mode for raising to the power voltage level at the precharge period when the control signal is the ground voltage level at the present activation period and thereafter to a high voltage level at a successive activation period, a seventh mode for raising to the power voltage level at the precharge period and thereafter maintaining the power voltage level at a successive activation period, and an eighth mode for raising to the power voltage level at the precharge period and thereafter lowering to the ground voltage level at a successive activation period; and the bit line selection control means provides control signals of modes corresponding to the activation states of the respective memory cell arrays to the switching arrays.