Patent ID: 6651231
Filing Date: 2003-11-18
Classification: G01R,G06F

Abstract:
A clock synchronizing circuit comprising a plurality of sequential circuits which operate based on a single clock signal, each of said sequential circuits sampling input data and changing output data at both a rising edge and a falling edge of the clock signal, each of said sequential circuits including;an input selector unit which receives two inputs and selects one of the two inputs in accordance with a control signal as an output, wherein an output of a selected one of said sequential circuits is input as one input of a sequential input selector unit in a sequential circuit at a subsequent stage, thereby forming a scan pass in said sequential circuits; a pair of latch units latching data alternately in accordance with the clock signal, both latch units receiving as an input the output of said input selector unit; and an output selector unit which selects and outputs an output of said latch units in accordance with the clock signal.