Patent ID: 6809396
Filing Date: 2004-10-26
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate having a surface doped to form a first base region; a film formed on the surface with a first opening over an edge of the first base region; a first conductive spacer formed along a first sidewall of the first opening to define a first emitter region within the first base region, wherein the first conductive spacer electrically contacts the first emitter region formed within the first base region; a second conductive spacer formed on the surface along a second sidewall of the first opening to define a first collector region of the integrated circuit, wherein the second conductive spacer electrically contacts the first collector region formed in the substrate outside the first base region, wherein the first emitter, first collector and first base regions operate as a PNP transistor, wherein the first base region is doped to have a first conductivity type and the first emitter and first collector regions are doped to have a second conductivity type, wherein the film includes conductive layer having a first portion for contacting the first conductive spacer at the first sidewall and a second portion for contacting the second conductive spacer along the second sidewall, wherein the film is formed with a second opening over a second base region formed in the semiconductor substrate to have the first conductivity types; a first semiconductor material disposed in the first opening between the first and second conductive spacers for contacting the first base region; and first and second dielectric spacers formed to electrically isolate the first and second conductive spacers from the first semiconductor material.