Patent ID: 8012826
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device comprising: forming a mask insulator on a silicon oxide film on a semiconductor substrate; patterning the mask insulator into a device isolation pattern; forming a device isolation trench in the semiconductor substrate using the patterned mask insulator as a mask; filling an isolation dielectric in the device isolation trench to form device isolation, thereby separating a silicon substrate surface to active regions; removing the mask insulator and the silicon oxide film to expose a surface of the active region; forming a gate dielectric on the active region; depositing a first conductive film on a whole surface of the gate dielectric; forming a slit in the first conductive film, the gate dielectric, and the semiconductor substrate so as to include at least end portion of the active region; forming an inter-electrode dielectric on a whole face of the first conductive film including an inner face of the slit; depositing a second conductive film on the inter-electrode dielectric; patterning the second conductive film, the inter-electrode dielectric, the first conductive film, and the gate dielectric to form a gate electrode of a memory cell transistor and a gate electrode of a select transistor; introducing dopant to the semiconductor substrate using the gate electrodes of the memory cell transistor and the select transistor as masks to form source/drain; forming a first wiring electrically connected to the source/drain; and forming a second wiring electrically connected to the first conductive film of the select transistor.