Patent ID: 6569720
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method for fabricating a thin-film transistor, which comprises the following steps:a step of preparing a substrate, a step of forming a thin semiconductor film on said substrate, a step of forming a gate-insulating film on said substrate, said gate-insulating film having a two-layered structure of a gate nitride layer and a gate oxide layer, a step of forming a gate electrode on said substrate, a step of implanting a dopant selectively in said thin semiconductor film to form a source region and a drain region of the thin-film transistor, a controlled rapid thermal annealing (RTA) step of activating the implanted dopant for controlling the threshold voltage (Vth) of the thin-film transistor, wherein said controlled RTA step is performed at an annealing temperature which is not greater than 600Â° C. such that increasing the annealing temperature decreases the threshold voltage, and decreasing the annealing temperature increases the threshold voltage, a step of forming a wiring electrode in electrical contact with one of said source region and said drain region, a step of forming a passivation layer on said substrate, a step of forming a contact hole at the other one of said source region and said drain region through the passivation layer, and a step of forming a metal contact film in said contact hole.