Patent ID: 6453370
Filing Date: 2002-09-17
Classification: G06F

Abstract:
A method of using bank tag registers in a multi-bank memory device capable of non-sequential access to avoid a background operation collision included in a memory bank in a multi-bank type memory by a memory controller, wherein the memory controller includes a plurality of bank registers each of which is associated with one of the plurality of memory banks, wherein a bank register associated with a particular bank is arranged to store a particular bank number that defines the number of the bank in which information is stored, a bank status that indicates the status of the particular bank, and a bank counter, and wherein the memory controller further includes an adjustable bank number comparator unit coupled to each of the plurality of bank registers, comprising:receiving an incoming system address request, wherein the incoming system address request includes a requested bank number such that operating characteristics of the particular bank are used to configure the adjustable comparator; locating a bank register corresponding to the requested bank number by the bank number comparator; determining the bank status of the bank associated with the requested bank number; determining a bank entry status based upon the determined bank status; and accessing the requested memory bank when the bank entry status identifies that the requested bank is open.