Patent ID: 8826219
Filing Date: 2014-09-02
Classification: G06F

Abstract:
1. A method used for the physical design validation of an integrated circuit comprising: generating data of terminals of components in an integrated circuit according to layout data of the integrated circuit, wherein each component includes a plurality of input and output terminals, the data including one or more of names of the components, names of the terminals and coordinates of the terminals; comparing, with a computer, an original circuit netlist of the integrated circuit that includes data of components with the layout data of the integrated circuit; assigning labels to the terminals of the components in the integrated circuit according to the data of the terminals and results of the comparison, wherein a matching component between the original circuit netlist and the layout data is assigned a label for each terminal in the matching component representing data of the terminal; and locating a position of a short circuit based on the labels of the matching component using a short path calculation.