Patent ID: 6016309
Filing Date: 2000-01-18
Classification: H04L

Abstract:
An asynchronous interface apparatus comprising a microcontroller connected to an asynchronous device through an asynchronous data link and including an adapter for automatically adapting an asynchronous communication data flow between said microcontroller and the asynchronous device, said adapter including logical circuitry for receiving an input signal from said asynchronous device, for analyzing the input signal to automatically identify configuration parameters of the asynchronous data link, and for providing the identified configuration parameters to said microcontroller for adapting communication with the asynchronous device said logical circuitry having at least one control system for monitoring the input signal received from the asynchronous device to detect a number of data bits, a parity type and a number of stop bits per data character in the asynchronous communication data flow, each said control system including:a control circuit receiving the input signal;a clock generator for providing a clock signal to said control circuit and for varying the frequency of said clock signal responsive to a signal from said control circuit to enable said control circuit to detect a transmission speed on the asynchronous data link;a timer circuit controlled by said control circuit for synchronizing bit counting of the communication data flow so as to identify the number of data bits per character;a parity checker for calculating the parity of the data bits, the calculated parity being transmitted to said control circuit to validate a parity type; anda plurality of counters driven by said control circuit for counting the number of times an identified configuration of parameters containing one or two stop bits is detected so as to validate an identified configuration and to generate a valid configuration signal for delivery to said microcontroller indicating that a valid configuration has been detected by said logical circuitry.