Patent ID: 6144576
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A memory system, comprising:a first memory module having a first electrical connector coupled to a bus, the first electrical connector to receive a set of signals, the set of signals to be serially routed through a first plurality of memory devices of the first memory module to a second electrical connector on the first memory module, wherein the first plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the first memory module, the second electrical connector coupled to a last memory device of the first plurality of memory devices connected in series of the first memory module; anda second memory module connected in series with the first memory module, wherein the second memory module has a first electrical connector coupled to the second electrical connector of the first memory module to receive the set of signals, the set of signals to be serially routed through a second plurality of memory devices of the second memory module to a second electrical connector on the second memory module, wherein the second plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the second memory module, the second electrical connector coupled to a last memory device of the second plurality of memory devices connected in series of the second memory module.