Patent ID: 8299517
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having an active region; a trench structure defined within the active region, the trench structure including an upper trench region adjacent to a surface of the active region and having a lower boundary located at a first corner of inner walls of the trench structure and oriented in a plane substantially parallel with the surface of the active region, a lower trench region having an upper boundary located at a second corner of the inner walls of the trench structure and oriented in a plane substantially parallel with the surface of the active region, and a buffer trench region interposed between the lower boundary of the upper trench region and the upper boundary of the lower trench region, wherein a width of the lower trench region is greater than a width of the upper trench region and wherein the inner walls of the trench structure are curved throughout the lower trench region and throughout the buffer trench region; a gate electrode disposed in the trench structure; and a gate dielectric layer interposed between the gate electrode and the trench structure.