Patent ID: 7345920
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A method of operating a memory cell comprising a gate, source and drain regions in a substrate region, and including a top dielectric, a charge trapping structure having parts corresponding to the source and drain regions, and a bottom dielectric between the gate and the substrate region, the method comprising: selecting a part of the charge trapping structure corresponding to one of the source region or the drain region, to determine a charge storage state of the selected part of the charge trapping structure; applying a first bias arrangement to determine the charge storage state of the selected part of the charge trapping structure, wherein the first bias arrangement induces at least a reverse biased band-to-band current component through one of the source region or the drain; and measuring at least the reverse biased band-to-band current component flowing between the substrate region and one of the source region or the drain region to determine the charge storage state of the selected part of the charge trapping structure.