Patent ID: 9064804
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method for forming a twin bit cell structure for a flash memory device, the method comprising: providing a semiconductor substrate including a surface region; forming a gate dielectric layer overlying the surface region; forming a polysilicon gate structure overlying the gate dielectric layer; forming first and second undercut regions underneath the polysilicon gate structure in first and second portions of the gate dielectric layer; exposing the semiconductor substrate, the gate dielectric layer, the undercut regions, and the polysilicon gate structure to an oxidizing environment to cause: depositing a silicon nitride material over the first and second silicon oxide layers and filling the undercut regions; selectively etching a first portion of the silicon nitride material overlapped by the polysilicon gate structure; maintaining a second portion the silicon nitride material in an insert region in a portion of each of the undercut regions; and forming a sidewall spacer structure, wherein the sidewall spacer structure is formed so as to overlie each of the side surfaces of the polysilicon gate structure, to overlie exposed surfaces of the silicon nitride material, and to overlie an exposed surface portion of the second oxide layer, wherein the sidewall spacer structure contacts the exposed surfaces of the silicon nitride material at a contact interface, and wherein the contact interface is overlapped by the polysilicon gate structure in the undercut regions underneath the polysilicon gate structure.