Patent ID: 6778624
Filing Date: 2004-08-17
Classification: G11B,H03L

Abstract:
A digital PLL circuit for receiving input read data read from a disc storage medium and providing an output sync signal and synchronized read data with jitter substantially eliminated, the circuit comprising:means for generating a variable-rate internal sync signal, a length of each period of said internal sync signal being determined as an initial count value supplied at the end of a previous period, and a fiducial point being set at a fixed position of each period of said internal sync signal; means for calculating, for each pulse of said input read data, a phase difference between the input read data pulse and said fiducial point of an internal sync signal period concurrent with said input read data pulse by subtracting one from the other; means for calculating a fed-back count value on the basis of said phase difference and phase differences calculated so far; adding means for adding said fed-back count value to a given count value to obtain said initial count value; means for frequency-bisecting said internal sync signal into said output sync signal; means for generating said synchronized read data from said input read data and said output sync signal; and means for limiting said fed-back count value to a predetermined range so as to limit said internal sync signal to a desired range.