Patent ID: 7254757
Filing Date: 2007-08-07
Classification: G11C

Abstract:
1. A flash memory test system comprising: a test processor to control tests of semiconductor memory devices; a programmable power supply connected to and controlled by said test processor; a direct current (DC) parameter measurement unit connected to and controlled by said test processor; an algorithmic pattern generator connected to and controlled by said test processor, said algorithmic pattern generator having a first memory that stores failure information and a second memory that stores failure address information corresponding to the failure information of the first memory, whereby different data can be supplied to identical addresses in each of a plurality of Devices Under Test (DUTs) during a parallel test of a specific item; a timing generator connected to and controlled by said test processor; pin electronics connected to and controlled by said test processor, and internally having a driver and a comparator; and a wave shape formatter that processes information supplied from the algorithmic pattern generator and the timing generator, and supplies the processed information to the pin electronics.