Patent ID: 6434069
Filing Date: 2002-08-13
Classification: G11C

Abstract:
In a data memory circuit, a method for amplifying and latching a signal indicative of data comprising:providing a first data latch node having a first capacitance; providing a second data latch node having a second capacitance; providing a first data line, having a greater capacitance than said first capacitance, for selective connection to the first latch node; providing a second data line, having a greater capacitance than said second capacitance, for selective connection to the second latch node; in a first phase, isolating the first and second data lines from the respective latch nodes and pre-charging and equalizing said first and second data lines; and in a second phase, connecting said first and second latch nodes to said first and second data lines, respectively, permitting a differential voltage signal to be established between said first and second data lines, passing said differential voltage signal to said first and second latch nodes such that said differential voltage signal is present between said first and second latch notes; and repeating said steps of said first phase while simultaneously latching and amplifying said differential voltage signal present between said first and second latch nodes.