Patent ID: 6420197
Filing Date: 2002-07-16
Classification: H01L,H01S

Abstract:
A method of fabricating a semiconductor device, the method comprising the steps of:forming a strain reducing layer having a second thermal expansion coefficient T2 on a substrate having a first thermal expansion coefficient T1, said strain reducing thermal layer being made of silicon, InP, diamond or BP; and forming a semiconductor layer having a third thermal expansion coefficient T3 on the strain reducing layer, the semiconductor layer being made of a nitride compound represented by AlyGa1âˆ’yâˆ’zInzN (0&lE;y&lE;1, 0&lE;z&lE;1), the second thermal expansion coefficient T2 being lower than the first thermal expansion coefficient T1, the third thermal expansion coefficient T3 being lower than the first thermal expansion coefficient T and higher than the second thermal expansion coefficient T2.