Patent ID: 7403966
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A high speed circuit for performing an arithmetic function comprising one of a group consisting of division and square root applied to a number and provide a result of the arithmetic function based on partial iterations, comprising: a counter for providing a count to identify a current partial iteration; a comparator having a first input for receiving the number, a second input, and an output; register means for storing a current estimate of the result of the arithmetic function as applied to the number based on previous partial iterations, for providing an output representative of a next partial iteration, and for updating the result based on the output of the comparator, wherein the register means has a first input coupled to the output of the comparator, a second input coupled to the counter, and an output; storage means for storing an inverse of the arithmetic function of the current estimate and having an output on which is provided the inverse of the arithmetic function of the current estimate of the result; incremental means having an input coupled to the output of the register means for providing, on an output, an incremental effect, wherein the incremental effect is a value that when added to the inverse of the mathematical function of the current estimate is equal to the inverse function of a next current estimate plus the next partial iteration; and summing means, having an output coupled to the second input of the comparator, a first input coupled to the output of the storage means, a second input coupled to the incremental means, for providing on the output a sum of the incremental effect and the inverse of the arithmetic function of the current estimate.