Patent ID: 6350668
Filing Date: 2002-02-26
Classification: H01L,H05K,Y02P

Abstract:
A method of manufacturing semiconductor chip packages comprising:providing a semiconductor wafer containing a plurality of chips; forming a first dielectric layer over a surface of the wafer; forming a first plurality of holes in the dielectric layer, the holes corresponding with the locations of contact pads on the surface of the wafer; depositing a first conductive layer on a surface of the first dielectric layer; patterning the first conductive layer to form traces, each of the traces extending from one of the first plurality of holes; depositing a second dielectric layer over the first dielectric layer and the first conductive layer; forming a second plurality of holes in the second dielectric layer, each of the second plurality of holes corresponding with the location of at least one of the traces; depositing a second conductive layer over the second dielectric layer, the second conductive layer extending into the second plurality of holes; removing a portion of the second conductive layer, leaving the second conductive layer in the second plurality of holes; forming a first plurality of conductive bumps in the second plurality of holes; depositing an encapsulant layer covering the first plurality of conductive bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; and forming a second plurality of bumps on the exposed portions of the first plurality of bumps.