Patent ID: 7193911
Filing Date: 2007-03-20
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a memory cell array; and a page buffer coupled to the memory cell array and including a first register having a first input unit to receive first program data, a second input unit to receive first erase data, a first delay component coupled to the first input unit, and a second delay component coupled to the second input unit, wherein the first input unit is configured to transfer the first program data to a first node of the first register according to a first data input signal, and the second input unit is configured to transfer the first erase program to a second node of the first register according to a second data input signal, wherein the first and second delay components are used to delay an input of the first and second data input signals, respectively, to the first and second input units, and provide an additional time to input the first program data and first erase data, respectively, into the first and second input units during a check board program operation.