Patent ID: 7773443
Filing Date: 2010-08-10
Classification: G11C

Abstract:
1. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of: driving a selected word line to a selected word line bias voltage; driving a selected bit line to a selected bit line bias voltage; precharging a sense node to a precharge sense voltage; summing, at the sense node, a selected bit line current and a reference current having a magnitude between the first and second nominal current levels; then developing a voltage on the sense node that increases to a higher voltage for one data state, and decreases to a lower voltage for the other data state, while the selected bit line remains substantially at the selected bit line bias voltage; and comparing the sense node voltage with a sense reference voltage to determine the selected memory cell data state.