Patent ID: 6706635
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method for forming a high precision analog capacitor on a semiconductor substrate, the method comprising:forming a field oxide layer over a portion of the substrate; forming a polysilicon layer over the field oxide layer; forming a silicide over the polysilicon layer, thereby defining a bottom plate of the capacitor; forming a first interlayer dielectric over the substrate; forming a capacitor masking pattern over the substrate; etching the first interlayer dielectric using the capacitor masking pattern as a mask and the silicide as an etch stop, thereby defining a capacitor region; forming a thin dielectric over the substrate; forming a contact masking pattern over the substrate; etching the thin dielectric and the first interlayer dielectric using the contact masking pattern as a mask and the silicide as an etch stop to form a bottom plate contact hole; depositing a metal over the substrate, thereby filling the capacitor region and the bottom plate contact hole; and planarizing the metal, wherein a top plate of the capacitor and an electrical connection to the bottom plate of the capacitor are defined, and wherein the top plate of the capacitor and the electrical connection to the bottom plate of the capacitor are laterally isolated by the first interlayer dielectric.