Patent ID: 6990044
Filing Date: 2006-01-24
Classification: G06F

Abstract:
1. A composite memory device, comprising: a first asynchronous memory device; a second synchronous memory device configured to operate in a page mode; a third synchronous memory device configured to operate in a burst mode; a memory bus configured to transfer data among the first through the third memory devices; a first memory controller configured to control data transfer operation between the first memory device and the memory bus; a second memory controller configured to control data transfer operation between the second memory device and the memory bus; and a third memory controller configured to control data transfer operation between the third memory device and the memory bus, wherein the first through the third memory devices are controlled by an external memory controller to exchange data with an external system bus, and when one of the first through the third memory devices exchanges data with the external system bus, the rest two memory devices are allowed to exchange data via the memory bus.