Patent ID: 6834339
Filing Date: 2004-12-21
Classification: G06F

Abstract:
A microprocessor comprising:a first PLA that outputs a first PLA microcode based on an instruction code and a state signal; a second PLA that outputs a second PLA microcode and a comparison determination signal based on the instruction code, the state signal, and a slow mode setting signal; a selecting means that selects either the first PLA microcode or the second PLA microcode according to the comparison determination signal, and outputs the selected one as a microcode; and a control means that activates one of the first and second PLAs and deactivates the other according to the comparison determination signal, wherein the second PLA processes several instructions among all the instructions to be processed by the first PLA, the second PLA including: a first register that stores instruction codes and state signals for the several instructions; a second register that stores microcodes that correspond to the instruction codes and the state signals stored in the first register; and a comparison control circuit that compares data in the first register with the instruction codes and the state signals input in a slow mode set according to the slow mode setting signal, and outputs the comparison result as the comparison determination signal, and when the comparison determination signal indicates a matching state, the second PLA outputs the microcode corresponding to the matched data in the first register from the second register as a second PLA microcode.