Patent ID: 6323690
Filing Date: 2001-11-27
Classification: G06F,H03K

Abstract:
A method for forming a logic circuit by using a computer which is able to access a storage device storing a library describing at least a logic function of each of cells, comprising the steps of:inputting a first logic circuit which is described by a plurality of cells and connecting relationships of said plurality of cells;converting said plurality of cells of said first logic circuit into selectors using said library, so that a second logic circuit which is described by a plurality of selectors and connecting relationships of said plurality of selectors and has a same logic function with said first logic circuit is generated;replacing at least a partial circuit of said second logic circuit into another partial circuit having a same logic function, wherein a delay time of said another partial circuit is smaller than that of said partial circuit, so that a third logic circuit is generated; andmapping selectors of said third logic circuit into cells, so that a fourth logic circuit is generated.