Patent ID: 6700151
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A single polysilicon reprogrammable memory cell useful in a memory array having select and access lines, the memory cell comprising:a MOS field effect transistor having a gate, a gate dielectric underlying the gate, and first and second doped semiconductor regions underlying both the gate dielectric and the gate in a spaced apart relationship to define a channel region there between; a MOS data storage element having a conductive structure, an ultra-thin dielectric underlying the conductive structure, and a first doped semiconductor region underlying both the ultra-thin dielectric and the conductive structure, said ultra-thin dielectric being formed at the same time as said gate dielectric, the first doped semiconductor region of the MOS data storage element being coupled to the first doped semiconductor region of the MOS field effect transistor, said ultra-thin dielectric being capable of being selectively broken down into one of a plurality of breakdown states, wherein each of the MOS data storage elements comprises an inversion-enabled region underlying both the ultra-thin dielectric and the conductive structure and adjacent to the first doped region of the MOS data storage element, further wherein said conductive structure is formed at the same time as said gate; a select line segment coupled to the gate of the MOS field effect transistor; a first access line segment coupled to the second doped semiconductor region of the MOS field effect transistor; and a second access line segment coupled to the conductive structure of the MOS data storage element.