Patent ID: 6407406
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A CMOS circuit comprising:a Ge sacrifice layer formed on a silicon substrate, wherein the Ge sacrifice layer has an uneven surface and a lattice constant different from that of said silicon substrate; an n-type buffer layer formed on the uneven surface of said Ge sacrifice layer; a p-type buffer layer formed on the uneven surface of said Ge sacrifice layer; an n-type strained silicon layer formed above said n-type buffer layer and having a lattice constant different from that of said n-type buffer layer; a p-type strained silicon layer formed above said p-type buffer layer and having a lattice constant different from that of said p-type buffer layer; an n-type SiGe layer formed on said n-type strained silicon layer, a strained Si layer formed on said n-type SiGe layer, and a p-type strained SiGe layer formed on said p-type strained silicon layer.