Patent ID: 6294939
Filing Date: 2001-09-25
Classification: G11C,H03K

Abstract:
A data input buffer circuit for an asynchronous device, comprising:a first circuit for asynchronously receiving a data input signal; anda second circuit for asynchronously generating a data output signal representation of the data input signal, the data output signal having a rising edge transition which is delayed a first time delay following a first edge transition appearing on the data input signal, and a falling edge transition which is delayed a second time delay following a second edge transition appearing on the data input signal, wherein the first time delay is substantially the same as the second time delay, the second circuit comprising:an asynchronous logical true circuit path which generates a logical true representation of the data input signal;an asynchronous logical complement circuit path which generates a logical complement representation of the data input signal, wherein triggering edge transitions appearing on the logical true representation signal and the logical complement representation signal generate edge transitions appearing on the data output signal; anda latch element responsive to the logical true and logical complement signal representations generated by the logical true and logical complement circuit paths, respectively, the data output signal generated by the second circuit being responsive to an output of the latch element; whereinthe logical true and complement signal representations are concurrently placed in a deasserting logic state a period of time prior to a triggering edge transition appearing on either the logical true signal representation or the logical complement signal representation; andthe output of the latch element is maintained in a prior state during the period of time the logical true and complement signal representations are concurrently placed in the deasserting logic state.