Patent ID: 8324094
Filing Date: 2012-12-04
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising: forming, on an insulating layer, a plurality of first mask layers and a second mask layer which is arranged between the first mask layers and has a width larger than that of a first mask layer, the first mask layers and the second mask layer being arrayed at equal spaces; reducing a width of each of the first mask layers and the second mask layer by selectively etching the first mask layers and the second mask layer; forming a plurality of sidewalls on side surfaces of the first mask layers and the second mask layer; removing the first mask layers and the second mask layer to leave the sidewalls; selectively etching the insulating layer using the sidewalls as a mask to form, in the insulating layer, a plurality of first trenches and a second trench which is arranged between the first trenches and has a width larger than that of a first trench; and burying a conductor in the first trenches and the second trench to form, in the insulating layer, a plurality of first interconnection layers and a second interconnection layer having a width larger than that of a first interconnection layer.