Patent ID: 7701292
Filing Date: 2010-04-20
Classification: H03G

Abstract:
1. A circuit comprising: a first amplifier with a first gain factor, the first amplifier coupled to an input node and configured to generate a first intermediate signal; a feedback resistor to provide a feedback path for the first intermediate signal to be fed back to the input node; a first attenuator with a first attenuation factor, the first attenuator configured to receive the first intermediate signal and to generate second intermediate signal; a second attenuator with a second attenuation factor, the second attenuator coupled to the input node and configured to generate a third intermediate signal; a second amplifier with a second gain factor, the second amplifier configured to receive the third intermediate signal and to generate a fourth intermediate signal; and a summing circuit configured to generate an output signal using the second intermediate signal and the fourth intermediate signal, wherein the first amplifier, the feedback resistor, the first attenuator, the second attenuator, and the summing circuit are arranged such the output signal is substantially free of a noise component from the first amplifier.