Patent ID: 7728662
Filing Date: 2010-06-01
Classification: H03F

Abstract:
1. A power amplifier circuit comprising: a first transistor directly coupled to an input terminal, to receive a non-delayed input signal, and in response, provide an output signal; a delay circuit configured to introduce a first delay to the non-delayed input signal, thereby creating a delayed input signal, wherein the delayed input signal is delayed relative to the non-delayed input signal received by the first transistor; a second transistor coupled to the input terminal via the first delay circuit, to receive the delayed input signal, and in response, provide a first delayed output signal; an impedance inverter circuit coupled to the first transistor, to provide an impedance inversion and introduce a second delay to the output signal, thereby creating a second delayed output signal; a node connecting an output of the impedance inverter circuit and an output of the second transistor, the node configured to combine the first and second delayed output signals, thereby creating an amplified output signal; a level control circuit configured to provide a level control signal that causes the first transistor to become enabled in a low power mode, and causes the second transistor to become enabled in a high power mode; and a bias control circuitry to enable the first and second transistors in response-to the level control signal, wherein the bias control circuitry enables the first transistor to operate in a saturated mode when the level control signal indicates a low power mode, wherein the second transistor is disabled in the low power mode, and enables the second transistor to operate in the saturated mode when the level control signal indicates a high power mode, wherein both the first and second transistors are enabled in the high power mode.