Patent ID: 6717206
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A structure of an embedded channel write/erase flash memory cell, comprising mainly:an N-substrate; a flash memory cell region comprising mainly: a deep P-well formed in said substrate; N-well formed in said deep P-well, a deep p-type region and a shallow p-type region being implanted in predetermined positions of said N-well; a first n-type region formed at one side of said shallow p-type region and in said deep p-type region in said N-well to be used as a drain; a second n-type region formed at the other side of said shallow p-type region in said N-well to be used as a source; and a stacked gate formed on said N-well; and a CMOS device region comprising mainly: a first deep P-well formed in said substrate; a first N-well formed in said first deep P-well, a plurality of p-type regions being implanted in predetermined positions of said first N-well; a second deep P-well formed in said substrate; and a second N-well formed in said second deep P-well, a plurality of p-type regions being implanted in predetermined positions of said second N-well.