Patent ID: 6078513
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A self-booting memory cell with a compare gate comprising:a pair of bit lines including a true bit line and a complement bit line, for conducting a data bit and a complement of the data bit to the memory cell;a word line for indicating when to write data from the bit lines to a row containing the memory cell;a column-select line for indicating when to write data from the bit lines to a column containing the memory cell;first storage transistor means having a first gate for dynamically storing a state of the memory cell;second storage transistor means having a second gate for dynamically storing a complement of the state of the memory cell;first pass transistor means having a gate controlled by a first boosted node, for connecting the true bit line to the first gate during a write operation;second pass transistor means having a gate controlled by a second boosted node, for connecting the complement bit line to the second gate during the write operation;first select transistor means, coupled between the word line and the first boosted node, with a gate controlled by the column-select line, for isolating the first boosted node from the word line when the column-select signal is low;second select transistor means, coupled between the word line and the second boosted node, with a gate controlled by the column-select line, for isolating the second boosted node from the word line when the column-select signal is low;a match line;first match transistor means, coupled to the first storage transistor means, for discharging current from the match line to the first storage transistor means during a compare operation, having a gate controlled by a first bit line of the pair of bit lines, the first bit line receiving a test data bit during the compare operation; andsecond match transistor means, coupled to the second storage transistor means, for discharging current from the match line to the second storage transistor means during the compare operation, having a gate controlled by a second bit line of the pair of bit lines, the second bit line receiving a complement of the test data bit during the compare operation;whereby the first and second storage transistor means and the first and second match transistor means are a compare gate.