Patent ID: 7245533
Filing Date: 2007-07-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix; a control circuit which controls the potential on the word lines and bit lines according to input data and which controls the operations of writing data into, reading data from, and erasing data from the memory cells; a data storage circuit which is connected to the bit lines and which stores data under the control of the control circuit; a well region in which a part of the data storage circuit and the memory cell array are formed; a wiring line which connects the data storage circuit and the control circuit; and a high-voltage transistor which is connected to the line in such a manner that the transistor is inserted in the wiring line and which is turned off in the operation of erasing data.