Patent ID: 8592898
Filing Date: 2013-11-26
Classification: H01L

Abstract:
1. An integrated circuit comprising: a semiconductor substrate having an array portion and a logic portion; at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate, and wherein the first and second pillars are in the substrate array portion; a gate electrode formed in the substrate array portion and adjacent sidewalls of the U-shaped semiconductor structure and between the first and second pillars; and at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions.