Patent ID: 8107309
Filing Date: 2012-01-31
Classification: G11C

Abstract:
1. A method of using a memory cell employing a field effect transistor including a word line and a bit line, comprising the actions of: a. heating the field effect transistor to a first predetermined temperature sufficient to support a bias temperature instability in the field effect transistor; b. driving the bit line to a high voltage state; c. driving the word line to a predetermined voltage state that causes the bias temperature instability in the field effect transistor; d. maintaining the first predetermined temperature, the high voltage state on the bit line and the predetermined voltage state on the word line for an amount of time sufficient to change a threshold voltage of the field effect transistor to a state where a desired data value is stored on the field effect transistor; and e. cooling the field effect transistor to a second predetermined temperature that is cooler than the first predetermined temperature after the amount of time has expired.