Patent ID: 6807081
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A semiconductor memory circuit formed on a SOI comprising:two inverters connected between first and second storage nodes, an input node of each inverter being connected to an output node of the other inverter, wherein said inverters each includes: plural first MOS transistors with a first conductivity type, connected in series between a line of a first power supply potential and the output node, and whose gate electrodes are all connected to the input node; and a MOS second transistor with a second conductivity type, connected between a line of a second power supply potential and the output node, and whose gate electrode is connected to the input node, wherein each said first MOS transistor has a body region provided beneath the sate electrode, and the body region of each said first MOS transistor is spaced apart from the body region of another said first MOS transistor.