Patent ID: 8053750
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A phase change memory device comprising: a silicon substrate having a cell region and a peripheral region; a first insulation layer formed on the silicon substrate in the cell region of the silicon substrate and having a plurality of holes; cell switching elements formed in the holes of the first insulation layer; heat sinks formed on the cell switching elements; heaters, one of which is formed on a center portion of each of the heat sink; spacers formed on the heat sinks to surround the heaters; a gate formed in the peripheral region of the silicon substrate and comprising a stack structure including a gate insulation layer, a first conductive layer, a second conductive layer, and a hard mask layer; a second insulation layer formed on the peripheral and cell regions of the silicon substrate which is formed with the spacers, the heaters, the heat sinks and the gate, wherein the second insulation layer is formed to expose the spacers and the heaters of the cell region and the hard mask layer of the peripheral region; and stack patterns of a phase change layer and a top electrode formed on the heaters, wherein the cell switching elements comprise vertical PN diodes having a stack structure comprising an N-type silicon layer and a P-type silicon layer.