Patent ID: 7262111
Filing Date: 2007-08-28
Classification: H01L

Abstract:
1. A method for manufacturing a deep connection structure in a semiconductor device of the type comprising an epitaxial silicon layer on a substrate, said method comprising the steps of: etching a first shallow trench, a second shallow trench, and a third shallow trench in said epitaxial silicon layer down through a first portion of a thickness of said epitaxial silicon layer; doping a portion of said epitaxial silicon layer located between said first shallow trench and said second shallow trench to form a first doped layer in said epitaxial silicon layer; doping a portion of said epitaxial silicon layer located at a bottom of said second shallow trench to create a second doped layer in said epitaxial silicon layer; doping a portion of said epitaxial silicon layer located between said second shallow trench and said third shallow trench to form a third doped layer in said epitaxial silicon layer; depositing an oxide layer to fill said first, second and third shallow trenches; diffusing said second doped layer vertically down to contact said substrate; and diffusing said first doped layer and said third doped layer vertically down to contact said second doped layer.