Patent ID: 8987741
Filing Date: 2015-03-24
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel, comprising: a substrate comprising pixel areas, each pixel area being divided into an upper pixel area and a lower pixel area that do not overlap in a first direction perpendicular to a plane of the substrate; a gate line and a data line disposed on the substrate and extending along edges of a first pixel area of the pixel areas; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor and comprising: a first common electrode overlapped in the first direction by the upper pixel electrode, in the upper pixel area of the first pixel area; a second common electrode overlapping in the first direction the lower pixel electrode, in the lower pixel area of the first pixel area, a common voltage supply line disposed along an edge of the substrate and directly connected to the second common electrode; and a common electrode line disposed on the substrate and connected to the common voltage supply line and connected to the first common electrode, wherein: