Patent ID: 6092269
Filing Date: 2000-07-25
Classification: H01G,Y10T

Abstract:
A method for fabricating a high energy density multilayer capacitor having an energy density of at least 0.5 J/cm.sup.3, said capacitor comprising a plurality of interleaved, vacuum-deposited metal electrode layers, each layer separated by vacuum-deposited, radiation-cured polymer dielectric layers, thereby defining an active region, said interleaved metal electrode layers terminating at opposite ends in a multilayer sputtered, solder-coated termination strip, said method comprising:(a) forming a multilayer capacitor array comprising a plurality of alternating metal layers and polymer layers on a substrate in a continuous, one-step process in a vacuum, wherein(i) each said metal layer is formed by metal evaporation,(ii) each said polymer layer is formed by first depositing a monomer layer on a said metal layer and radiation-curing said monomer layer to form said polymer dielectric layer, and(iii) said forming said metal layer on said polymer layer is repeated many times to form said plurality of interleaved, vacuum-deposited metal electrode layers separated by said vacuum-deposited, radiation-cured polymer dielectric layers,(b) slicing said capacitor array into a plurality of strips along a first direction to form capacitor strips;(c) slicing said capacitor strips into individual capacitors along a second direction that is orthogonal to said first direction,wherein following said slicing said capacitor array into said plurality of strips, said metal electrode layers are recessed into said polymer layers along edges orthogonal to said opposite ends, thus creating a non-conducting region, to protect against arcing and leakage current between said metal electrode layers along said orthogonal edges.