Patent ID: 8486808
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A method comprising: forming first and second pillars over a semiconductor substrate, the first and second pillars being adjacent to each other with a space therebetween, the first pillar including a semiconductor body and a gate insulating film covering a side surface of the semiconductor body; depositing a conductive layer over the first and second pillars and the semiconductor substrate without completely filling the space so that a gap, that is free from being filled with the conductive layer, remains between the first and second pillars; depositing an insulating layer over the conductive layer by completely filling the gap; etching back the insulating layer until a top surface of the conductive layer is exposed so that an insulating side wall is formed to surround each of the first and second pillars and substantially complete filling of the gap with an intervention of a part of the conductive layer; selectively removing the conductive layer by using the insulating side wall as a mask to form a gate electrode, the gate electrode including a first cylindrical portion that surrounds the first pillar, a second cylindrical portion that surrounds the second pillar, a first horizontal portion that is in the space to connect respective parts of the first and second cylindrical portions to each other, and a second horizontal portion that spreads over the semiconductor substrate from remaining parts of the first and second cylindrical portions; depositing an interlayer insulating film over the gate electrode that includes the first and second cylindrical portions and the first and second horizontal portions; and selectively forming, in the interlayer insulating film, first and second conductors that are connected to the gate electrode and the semiconductor body of the first pillar, respectively.