Patent ID: 9097989
Filing Date: 2015-08-04
Classification: G03F

Abstract:
1. A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process comprising: creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers; creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns; measuring the targets on the masks; determining overlay variation between the masks; exposing and creating with one of the masks a first lithographic processing layer on a wafer; exposing and creating with another of the masks a second lithographic processing layer on the wafer, over the first layer; measuring the targets on the wafer at one or more of the layers; correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation.