Patent ID: 6265255
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method for forming a semiconductor device having shallow junctions, comprising:providing a semiconductor substrate having a shallow trench isolation region, a well region with a first conductivity and a well region with a second conductivity;forming a first gate on said well region with the first conductivity and forming a second gate on said well region with the second conductivity;forming a first diffusion source layer on said semiconductor substrate wherein said first diffusion source layer comprises nitrogen oxide;forming a first photoresist layer over said well region with the second conductivity;forming a diffusion source layer with the second conductivity by carrying out a first ion implantation with the second conductivity to dope a part of said diffusion source layer formed over said well region with the first conductivity;removing said first photoresist layer over said well region with the second conductivity;forming a second photoresist layer over said well region with the first conductivity;forming a second diffusion source layer with the first conductivity by carrying out a second ion implantation with the first conductivity to dope another part of said diffusion source layer formed over said well region with the second conductivity;removing said second photoresist layer on said well region with the first conductivity;forming spacers on sidewalls of said first gate and said second gate and said diffusion source layer and said second diffusion source layer;carrying out a third ion implantation with the first conductivity and fourth ion implantation with the second conductivity to dope respective said diffusion source layer with the first conductivity and said diffusion source layer with the second conductivity; andforming source/drain regions and shallow junctions in said well region with the second conductivity and said well region with the first conductivity, respectively.