Patent ID: 7239177
Filing Date: 2007-07-03
Classification: H03K

Abstract:
1. An off-chip circuit comprising: a pre-driver circuit; and a driver circuit; wherein an output of said pre-driver circuit is coupled to an input of said driver circuit; wherein said pre-driver circuit comprises: wherein said driver circuit comprises: wherein said push pull circuit comprises: wherein the gate of said first n-channel transistor is connected to said power supply to reduce an external signal level at the drain of said second n-channel transistor to avoid punch through of said second n-channel transistor; a feedback NAND circuit controlled by said driver enable signal node and said output node; an isolation circuit, said isolation circuit comprising: wherein said third p-channel transistor is coupled to said third n-channel transistor, and wherein said third n-channel transistor and said first n-channel transistor operate as transmission transistors; wherein the gate of said third p-channel transistor is connected to a second reference node; and wherein the gate of said third n-channel transistor is connected to said power supply to avoid punch through of said fourth n-channel transistor; wherein the gate of said fifth n-channel transistor is connected to said power supply to avoid punch through of said sixth n-channel transistor; wherein the gate said sixth n-channel transistor is connected to an output of said NAND circuit; and wherein said fifth n-channel transistor and said sixth n-channel transistor provide proper bias control for said isolation circuit and the output of said first p-channel transistor.