Patent ID: 7650555
Filing Date: 2010-01-19
Classification: G01R,H04L

Abstract:
1. A method of testing a device under test (DUT), the method comprising: programming a master tester and a slave tester with a first predefined data pattern including a plurality of bits; transmitting, by the slave tester, a high speed data signal including the first predefined data pattern to a plurality of receivers in a device under test (DUT), the transmitting being in response to a trigger signal initiated by the master tester; monitoring, by a trace logic analyzer (TLA) in the DUT, the high speed data signal transmitted by the slave tester to detect the first predefined data pattern therein, thus providing a detected received data pattern; storing, by the TLA, the detected received data pattern; transmitting, by the DUT, the detected received data pattern to the master tester, the detected received data pattern providing test data to the master tester on a per receiver basis; comparing, by the master tester, the detected received data pattern to the first predefined data pattern to determine if a particular receiver is functioning properly; and generating, by the master tester a pass result for the particular receiver if the comparing step indicates that the particular receiver is functioning properly and otherwise generating a fail result for the particular receiver.