Patent ID: 6437594
Filing Date: 2002-08-20
Classification: G01R

Abstract:
A semiconductor wafer test circuit for testing pass gate leakage, the test circuit comprising:a plurality of pass gates having varying channel widths; a plurality of latches, each of said plurality of latches connected to a corresponding one of said plurality of pass gates, each of said plurality of latches receiving a leakage signal from its corresponding pass gate connected thereto; an input circuit for supplying a test signal to each of said plurality of pass gates, said test signal having a preselected magnitude; wherein each of said plurality of pass gates outputs a leakage signal to its corresponding connected latch in response to said test signal, thereby causing said plurality of latches to assume one of a triggered state and an untriggered state; and, storage coupled to said plurality of latches for storing one of said triggered state and untriggered state for each of said plurality of latches.