Patent ID: 6300184
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of manufacturing a CMOS transistor, comprising the steps of:forming a device separation film a given region on a semiconductor substrate to define a PMOS transistor region and a NMOS transistor region;sequentially forming a gate oxide film, a polysilicon film and an oxide film and then removing said oxide on which gate will be formed to expose a given region of said polysilicon film;implanting different impurity ions into the polysilicon film of said exposed NMOS transistor and PMOS transistor;forming a spacer at the side wall of the etched oxide film on the portion in which said gate will be formed and then forming a tungsten nitride film on the entire structure;forming a tungsten film on the entire structure so that the portion in which said gate will be formed can be buried, and then remaining a given portion of the portion in which said gate will be formed by blanket etching process;forming an insulating film on the entire structure and then remaining a nitride film on said tungsten film of the portion in which said gate will be formed by polishing process;removing said oxide film to remain a tungsten film, a nitride film and a spacer surrounding them, and then using them as a mask to etch said polysilicon film and said gate oxide film into which impurity are not implanted, thus forming a dual structure;forming an oxide film from said polysilicon film to on the underlying semiconductor substrate by means of selective oxidization process; andperforming low concentration impurity ion implantation process and high concentration impurity ion implantation process after forming a spacer at the side wall of the gate to form a junction region.