Patent ID: 6780552
Filing Date: 2004-08-24
Classification: G03F,H01L

Abstract:
A method for controlling quality of a lithographic structuring step performed in a lithographic structuring tool for structuring a pattern into a layer of a plate-like object, the method which comprises:providing a semiconductor wafer as the plate-like object; representing the quality by a group of at least two quality parameters including a first quality parameter representing a property of the pattern and a second quality parameter representing a property of the pattern being different than the property represented by the first quality parameter; measuring the first quality parameter in a first metrology tool; providing at least one value of the first quality parameter; calculating a width of a tolerance range for the second quality parameter in dependence on the at least one value of the first quality parameter; subsequently providing the plate-like object to the second metrology tool; measuring the second quality parameter in a second metrology tool; and comparing the second quality parameter with the width of the tolerance range that has been calculated; issuing an error signal if the second quality parameter exceeds the width of the tolerance range.