Patent ID: 6753675
Filing Date: 2004-06-22
Classification: H02M

Abstract:
A computer system, comprising:a data input device; a data output device; an address bus; a data bus; a control bus; and computing circuitry coupled to the data input and output devices, and the data, address, and control busses, the computing circuitry including a memory device that includes, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a control circuit coupled to the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, read/write circuit, and control circuit, the array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data; and a voltage generation circuit, including, a voltage pump circuit including a reference node and a pump feedback node, the voltage pump circuit developing on an output node an output voltage having a value that is a function of a reference voltage applied on the reference node and a feedback voltage on the feedback node; a feedback circuit coupled between the output node and the pump feedback node of the voltage pump circuit, the feedback circuit developing the pump feedback voltage in response to the output voltage; a coupling circuit coupled to the reference node and being adapted to receive a supply voltage and a control signal, the coupling circuit operable in response the control signal to control the value of a current supplied from the supply voltage to control the value of the reference voltage; and a voltage sensing circuit coupled to the reference node to receive the reference voltage and coupled to the coupling circuit, the voltage sensing circuit developing the control signal responsive to the reference voltage.