Patent ID: 6107124
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of fabricating a CCD comprising the steps of:sequentially forming a second conductivity type of well and BCCD region on a first conductivity type of substrate;sequentially forming a gate insulating layer and first polysilicon layer on the BCCD region, and patterning the first polysilicon layer, to form a first polysilicon gate;forming first lightly doped impurity regions in predetermined portions of the BCCD region, placed on both sides of the first polysilicon gate, using impurity ion implantation;forming a second polysilicon layer on the overall surface of the substrate including the first polysilicon gate, and patterning it, to form a second polysilicon gate;forming a second lightly doped impurity region and heavily doped impurity region in the BCCD region, by impurity ion implantation using the first and second polysilicon gates as a mask; andforming a third polysilicon layer on the overall surface of the substrate including the first and second polysilicon gates, and patterning it, to form a floating gate.