Patent ID: 6774649
Filing Date: 2004-08-10
Classification: G01R

Abstract:
A test system for conducting a function test of a semiconductor element on a wafer, the semiconductor element having terminal pads, the test system comprising:a voltage source delivering an output voltage and providing a supply voltage of the element being tested; a pin card having: a pin card board; supply contact pins arranged on said pin card board including one of said supply contact pins and another one of said supply contact pins; a resistance disposed on said pin card board; a read contact pin disposed on said pin card board and connected to said one of said supply contact pins through said resistance; said one of said supply contact pins and said read contact pin being configured to contact one of said terminal pads of the element being tested; said other one of said supply contact pins being configured to contact another one of said terminal pads of the element being tested; said read contact pin producing a high-impedance electrical read connection to said one of said terminal pads of the element being tested; said one of said supply contact pins and said other one of said supply contact pins each connected to the voltage source for applying the supply voltage to said one of said terminal pads and said other one of said terminal pads of the semiconductor element being tested; and a regulator controlling the output voltage based upon an electrical potential of said read contact pin.