Patent ID: 8420513
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A method of fabricating a thin film transistor, the method comprising: forming a buffer layer on a substrate; forming an amorphous semiconductor layer on the buffer layer; patterning the amorphous semiconductor layer to form an amorphous semiconductor pattern; forming a gate insulating layer on the amorphous semiconductor pattern; forming a semiconductor pattern access hole in the gate insulating layer; forming a metal layer on the substrate, the metal layer covering the gate insulating layer, and being in the semiconductor pattern access hole so as to be in contact therethrough with the amorphous semiconductor pattern; passing an electric current through the metal layer so as to convert the amorphous semiconductor pattern to a crystallized semiconductor pattern using heat generated by the electric current; patterning the metal layer to form a gate electrode corresponding to the crystallized semiconductor pattern; forming an interlayer insulating layer on the gate electrode; forming two first source/drain contact holes in the gate insulating layer and two source/drain contact holes in the interlayer insulating layer; and forming source and drain electrodes connected to the semiconductor layer through the first and second source/drain contact holes.