Patent ID: 8975141
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A method for fabricating a dual-workfunction FinFET structure, comprising: depositing an n-type workfunction material in a layer over a plurality of gate structures of each a PMOS and an NMOS and in a plurality of trenches between said gate structures; depositing a low-resistance material layer over the n-type workfunction material layer; depositing a deep ultraviolet light-absorbing oxide (DUOS material layer over the plurality of gate structures of the NMOS; etching the low-resistance material layer and the n-type workfunction material layer from the PMOS; etching the DUO material layer from over the NMOS; depositing a p-type workfunction material in a layer over the plurality of gate structures of the PMOS and in the plurality of trenches between said gate structures of the PMOS; and depositing a compressive stress material layer over the p-type workfunction material layer.