Patent ID: 7389485
Filing Date: 2008-06-17
Classification: G06F

Abstract:
1. A method of routing a user design in a programmable logic device (PLD) including both high-power interconnect resources and low-power interconnect resources, the method comprising: creating a first routed design by routing the user design in the PLD using a first cost function based on performance of the first routed design; wherein the first cost function assigns a higher cost to the low-power interconnect resources than to the high-power interconnect resources, and the assigned costs of the first cost function bias creation of the first routed design toward use of the high-power interconnect resources; identifying a plurality of identified nets in the first routed design, wherein the identified nets comprise non-critical nets in the first routed design and wherein the identified nets meet a criterion for high potential for power improvement; and creating a second routed design by rerouting at least one of the identified nets to utilize the low-power interconnect resources, using a second cost function different from the first cost function; wherein the second cost function assigns a higher cost to the high-power interconnect resources than to the low-power interconnect resources, and the assigned costs of the second cost function bias rerouting of at least one of the identified nets toward use of the low-power interconnect resources, and wherein identifying the plurality of identified nets in the first routed design comprises creating a sorted order of nets based on capacitance per load pin of each net in the first routed design.