Patent ID: 6440816
Filing Date: 2002-08-27
Classification: H01L,Y10S

Abstract:
A process for device fabrication, comprising:coating a wafer with a layer including SiO2, SiNx, and a first resist; defining shallow trench isolation and alignment patterns in the first resist; transferring the first resist pattern into the SiO2 and SiNx; removing the first resist; etching trenches to a depth suitable for shallow trench isolation; coating the wafer with a second photoresist; defining open areas around alignment marks; etching alignment mark trenches to a depth greater than the trench depth, suitable for alignment mark detection; removing the second resist and the SiNx; depositing SiO2 to fill the trenches for shallow trench isolation and partially fill the alignment mark trenches for alignment mark detection; and performing chemical mechanical polishing, leaving shallow trench isolation features and topographical alignment marks.