Patent ID: 6493359
Filing Date: 2002-12-10
Classification: H04J

Abstract:
A reconfigurable frame counter, comprising:a byte processor that receives framed data bytes of synchronous digital data, wherein the framed data bytes are at predetermined frame byte locations and the processor processes data bytes in predetermined frame byte locations in accordance with predetermined frame byte count values; and a frame byte counter for counting clock pulses that are each associated with the arrival of a framed data byte and for generating a frame byte count value that corresponds to the frame byte location of the currently received framed data byte, the frame byte counter having a programmable configuration start address value and a synchronization pulse input, wherein the frame byte counter, in response to a synchronization pulse on the synchronization pulse input, counts the clock pulses with an initial start count equal to the configuration start address value such that the frame byte count value indicates the frame byte location of the currently received framed data byte.