Patent ID: 7093042
Filing Date: 2006-08-15
Classification: G06F

Abstract:
1. A microcomputer, comprising: a CPU (a central processing unit); an erasable and programmable nonvolatile memory having a first area and a second area; a first designating means capable of designating a first state that said CPU is placed in execution of a program stored in said first area or a second state that said CPU is placed in execution of a program stored in said second area; and a second designating means capable of designating a third state that said CPU is placed in execution of a program stored in said first area after transition from said second state, wherein said first designating means is made up of an input circuit accepting a mode signal for transition to said first state or said second state in response to release of reset operation, and wherein said second designating means is made up of a first storage means to set first control information for transition to said third state, while being accessible to said CPU in said second state.