Patent ID: 6381184
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A circuit for transferring data in an array of memory cells arranged in rows and columns, comprising:a memory-cell array including a plurality of row lines, a plurality of pairs of complementary digit lines, and a plurality of memory cells arranged in rows and columns, each memory cell in each row having a control terminal coupled to a corresponding row line and a data terminal coupled to one of a pair of complementary digit lines; a plurality of sense amplifiers, each sense amplifier coupled to an associated pair of first and second complementary digit lines; a plurality of equilibration circuits, each equilibration circuit coupled between one of the pairs of complementary digit lines; and a control circuit coupled to the plurality of row lines, equilibration circuits, and sense amplifiers, the control circuit applying signals to the row lines, equilibration circuits, and sense amplifiers to store a group of test data bits in a first row of memory cells, and to thereafter transfer the stored group of test data bits from the first row through a plurality of rows in a desired sequence to an ending row of memory cells in the array.