Patent ID: 6959063
Filing Date: 2005-10-25
Classification: H03D,H03K,H03L

Abstract:
1. A phase-locked loop comprising: a phase detector that has a reference signal input that receives a reference clock signal and a comparison signal input that receives a comparison signal, wherein the phase detector generates a phase difference signal that represents a phase difference between the reference signal and a signal having twice the frequency of the comparison signal; a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal; a frequency divider that receives the phase-locked loop output signal and generates therefrom a divided frequency signal; and a circuit that generates the comparison signal from the divided frequency signal, wherein the comparison signal has one half the frequency of the divided frequency signal, wherein the phase detector comprises: a comparison circuit that compares a phase of the reference clock signal with a phase of a signal having a frequency that is twice that of the comparison signal.