Patent ID: 7127005
Filing Date: 2006-10-24
Classification: H03C,H04B,H04L

Abstract:
1. A signal deconstruction circuit for use in transmitter circuitry and configured for complementing modulation circuitry of said transmitter for digitally generating a non-constant envelope modulation signal, said deconstruction circuit comprising: a digital signal processor configured for deconstructing a predetermined signal having an undesirable property into one or more fragment signals which do not have said undesirable property, wherein signals derived from said fragment signals are subject to conversion to analog signals, processing by power efficient, dynamic-range limited analog circuits and recombination; wherein said undesirable property is a relatively high peak-to-average power ratio, said modulation circuitry comprises an Inverse Fourier transform processor and said deconstruction circuit is operative on said predetermined signal after said Inverse Fourier transform processor; and a phasor fragmentation engine, wherein said phasor fragmentation engine is capable of deconstructing said predetermined signal into one or more equal, or nearly equal, and constant, or nearly constant, amplitude fragment signals; wherein said phasor fragmentation engine is configured for converting sequences of complex time samples output from said Inverse Fourier transform processor into parallel sequences of two substantially equal magnitude phasors, substantially equal to Vmax/2, at two phases, wherein said phases of said two substantially equal magnitude phasors are calculated to be θ−φ and θ+φ, respectively, wherein φ=cos