Patent ID: 6104210
Filing Date: 2000-08-15
Classification: G06F,H03K

Abstract:
In a digital circuit, a method for avoiding contention in a data bus, comprising the steps of:providing a clock signal;providing for each bit of said data bus a first bus driver controlled by a first control signal synchronized to said clock signal;providing for each bit of said data bus a second bus driver controlled by a second control signal synchronized to said clock signal;including for each bit of said data bus a holding amplifier, said holding amplifier maintaining a data value of said bit, when neither said first bus driver nor said second bus driver is active; andactivating a selected one of said first bus driver and said second bus driver for a predetermined duration after the beginning of a phase of said clock signal to place a data value on said bit of said data bus by controlling an active phase of a corresponding one of said first and second control signals, said predetermined duration being shorter than the duration of said phase of said clock signal.