Patent ID: 6339540
Filing Date: 2002-01-15
Classification: G11C,H01L

Abstract:
A content addressable memory (CAM) array comprising:an array of non-volatile memory transistors arranged in a plurality of rows and columns, wherein each memory transistor has a gate, a first device terminal and a second device terminal, and wherein columns of memory transistors are configured to store words; a plurality of compare lines configured to receive a comparand word, wherein each compare line is coupled to the gate of each memory transistor in a row of the array; a first word line coupled to the first device terminal of each memory transistor in a first column of the array; a second word line coupled to the second device terminal of each memory transistor in the first column of the array, and to the first device terminal of each memory transistor in a second column of the array; a third word line coupled to the second device terminal of each memory transistor in the second column of the array; a first sense amplifier coupled to the first word line; a first supply voltage terminal coupled to the second word line; and a second sense amplifier coupled to the third word line.