Patent ID: 6374330
Filing Date: 2002-04-16
Classification: G06F

Abstract:
A method of maintaining cache coherency in a multi-processor computer system having a plurality of processing units, each processing unit having a cache hierarchy including at least first- and second-level caches, wherein the first cache level is upstream of the second cache level, the method comprising the steps of:loading a first value into a cache line block in a first-level cache of a processing unit, and into a sector of a cache line in a second-level cache of the processing unit, wherein the cache line in the second-level cache is comprised of a plurality of sectors corresponding to separate cache line blocks in the first-level cache; modifying the value in the cache line block in the first-level cache of the processing unit; and indicating at the second-level cache that the sector of the cache line in the second level cache has been modified at an upstream cache without modifying the sector of the cache line in the second-level cache.