Patent ID: 9034562
Filing Date: 2015-05-19
Classification: G03F,H01L

Abstract:
1. A method of forming a mask layer during manufacture of a semiconductor integrated circuit, comprising steps of: forming one or more pattern features in a mask material which are initially oversized apertures; forming one or more process assist features in said mask material which are holes proximate to said one or more pattern features; and performing a conformal shrink process whereby a shrink material is deposited on surfaces of said one or more pattern features and said one or more process assist features, wherein said one or more process assist features are sized such that said step of performing substantially fills and hence eliminates said holes, and wherein said step of performing is conducted such that depositional microloading caused by said one or more process assist features reduces an amount of shrink material deposited on surfaces of said oversized apertures such that said one or more pattern features have a desired critical dimension upon conclusion of said step of performing a conformal shrink process, but in an absence of said one or more process assist features said step of performing a conformal shrink process causes said oversized apertures to become smaller than said desired critical dimension.