Patent ID: 6329273
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method of manufacturing a flash memory device with minimal gate edge lifting, wherein the method comprises:(a) forming a gate stack on portions of a substrate forming gate stacks and exposed portions of the substrate wherein the gate stack includes a tunnel oxide formed on the substrate, a floating gate formed on the tunnel oxide, a layer of dielectric formed on the floating gate and a control gate formed on the layer of dielectric;(b) forming a layer of oxide on the gate stack and exposed portions of the substrate;(c) anisotropically etching the layer of oxide from a horizontal surface of the gate stack and from portions of the substrate on which a layer of oxide had been formed in step (b);(d) forming a layer of a solid source material on a portion of the substrate in which a source region is to be formed;(e) doping the layer of solid source material with first dopant ions;(f) diffusing the first dopant ions into the substrate to form a first source region;(g) doping the layer of solid source material with second dopant ions; and then(h) diffusing the second dopant ions into the substrate to form a second source region.