Patent ID: 7159156
Filing Date: 2007-01-02
Classification: G11C

Abstract:
1. A memory chip, comprising: memory cells having word lines, spare word lines, and bit lines; a data generator; a test logic connected to said data generator and to said memory cells for writing test data into and reading test data out from said memory cells; a first address register for supplying a first address for a selection of one of said word lines; a second address register for supplying a second address for a selection of one of said bit lines; a first selection decoder connected to said first address register, said first selection decoder activating a word line dependent upon said first address provided by said first address register; a plurality of switches having control inputs connected to said word lines, each of said switches being connected between a respective one of said memory cells and one of said bit lines, said switches being connected to said word line being switched to conduct with an activation of said word line; respective sets of two of said bit lines being combined to form one bit line pair, a first bit line of said bit line pair being a true bit line and a second bit line of said bit line pair being a complementary bit line; amplifier circuits, a respective one of said amplifier circuits being connected to a respective one of said bit line pairs; a second selection decoder connecting said test logic to said amplifier circuits, said second selection decoder being connected to said second address register for selecting said bit line pair; said test logic being connected to said first selection decoder, said test logic writing into one of said memory cells connected to a complementary one of said bit lines a logical data item having a different physical value than a data item written into another of said memory cells connected to said true bit line; a repair unit being connected to said test logic and having an address register storing addresses therein at least of said spare word lines, said repair unit being connected to said first selection decoder and diverting, through a readdressing of an access of said first selection decoder to a defective one of said word lines, to one of the addresses, stored in said address register, of a spare one of said spare word lines; and said test logic taking into consideration an address of said spare word line during the writing and reading of the test data in the presence of a readdressing to one of said spare word lines, said address of said spare word line having information regarding connection of said spare word line to one of said true bit line and said complementary bit line.