Patent ID: 7577047
Filing Date: 2009-08-18
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a delay time selecting portion configured to receive an internal read/write command and output the internal read/write command with no substantial delay as a final read/write command when an additive latency is not “0”, and output a delayed read/write command generated by delaying the internal read/write command for a predetermined time as the final read/write command when an additive latency is “0” ; a decoder configured to decode an address applied from an external portion with the read/write command to output a decoded address; and a selecting portion configured to receive the decoded address to select a memory cell of a memory cell array in response to the final read/write command, wherein the internal read/write command is generated by delaying an external read/write command for as long as the additive latency.