Patent ID: 8271922
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A system for clock optimization to achieve timing signoff in an electronic circuit, comprising: a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort said at least some clock cells according to breadth in an order from a broader breadth to a narrower breadth, wherein breadth of a clock cell of said at least some clock cells is a number of data paths of circuit elements driven by said clock cell of said clock network; a slack analyzer associated with said clock cell identifier/sorter and configured to process said at least some clock cell in said order by identifying flops in said data paths that are downstream of said at least some clock cells and determining a worst setup and hold timing slack thereof; and a clock cell delay adjuster associated with said slack analyzer and configured to adjust delays of said at least some clock cells subject to said worst setup and hold timing slack.