Patent ID: 6211074
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method for forming a silicide layer and a cap layer in a semiconductor device, the method comprising:forming a polysilicon floating gate on an underlying layer;depositing an interpoly dielectric layer over the floating gate;forming a polysilicon control gate over the interpoly dielectric layer;depositing a silicide layer on the polysilicon control gate at a first deposition temperature;depositing a cap layer on the silicide layer at a second deposition temperature, wherein a temperature difference between the first deposition temperature and the second deposition temperature is less than about 250.degree. C., thereby significantly reducing cracking in the silicide layer, wherein the step of depositing the cap layer includes forming polysilicon on the silicide layer, and wherein the step of forming polysilicon includes forming amorphous polysilicon using low temperature oxide (LTO) techniques wherein the second deposition temperature is less than about 500.degree. C.