Patent ID: 6088293
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A memory circuit for operating synchronously with a system clock signal, comprising:a memory array having a plurality of banks, each bank addressable in response to a bank address signal, each bank arranged in rows and columns of memory cells;a plurality of sense amplifiers, each sense amplifier coupled to a respective column of memory cells, each sense amplifier coupled to a data lead by a respective select transistor;a plurality of column decode circuits, each column decode circuit having a plurality of input terminals and at least one output terminal, the output terminal coupled to a control gate of at least one of the select transistors;a plurality of first predecode circuits, each first predecode circuit having a plurality of input terminals and at least one output terminal, each input terminal coupled to receive a respective first address signal; anda plurality of groups of second predecode circuits, each group corresponding to a respective bank, each second predecode circuit having a memory element, a plurality of input terminals and at least one output terminal, at least one second predecode circuit input terminal coupled to at least one first predecode circuit output terminal, at least another second predecode circuit input terminal coupled to receive the bank address signal, the second predecode circuit output terminal coupled to an input terminal of at least one of the column decode circuits, the second predecode circuit arranged to store a second address signal in the memory element in response to the bank address signal.