Patent ID: 6571365
Filing Date: 2003-05-27
Classification: G01R

Abstract:
An initial stage of a multi-stage algorithmic pattern generator, which is comprised of: multiple sets of input registers which store respective addresses; an operational circuit, coupled to said input registers, which receives a series of commands and in response performs selectable arithmetic operations on said addresses; and, a limit means which stores a respective pair of address limits for each register set; characterized in thatfor each register set, one corresponding control flip-flop is provided; a control circuit is provided which puts the control flip-flop for a particular register set in a predetermined state, when an address in any input register from said particular register set is modified, by a first command in said series, to any one address limit in said pair of address limits for said particular register set; and, a gating means is provided which responds, when a second command in said series modifies an address in any input register from said particular register set, by a) passing onto an output, the modified address only if said control flip-flop for said particular register set is not in said predetermined state, and otherwise b) passing onto said output, the address limit in said pair of address limits for said particular register set which is not said one address limit.