Patent ID: 7493531
Filing Date: 2009-02-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory array including a plurality of memory cells, each of said memory cells being in need of a refresh operation for retention of data; a circuit for writing preset data in predetermined plural memory cells, referred to as monitor cells, provided in said memory array; a circuit for performing control for reading data from said plural monitor cells, in which said preset data have been written, with the lapse of time equal to or shorter than a refresh period; and a circuit for comparing the data read from said monitor cell with said preset data to measure an error count or an error rate and for variably controlling the refresh period based on a measured result of said error count or the error rate, wherein preset data are written in a plurality of said monitor cells before or after the refreshing of said memory array; and data are read from said monitor cells after lapse of a predetermined time equal to or shorter than said refresh period; wherein said semiconductor memory device further comprises: a circuit for comparing said read data with said predetermined data to check the presence or absence of an error; a counter for counting said error; and a decision circuit for deciding, based on an output of said counter, whether the refresh period is to be elongated, shortened or maintained, wherein said decision circuit includes: a set value storage circuit for holding an upper limit value and a lower limit value of an error; and a comparator circuit outputting a keep-signal for maintaining the refresh period when the sum of said error counts for said monitor cells is intermediate between said upper and lower limit values; said comparator circuit outputting an up-signal for increasing said refresh period when the sum of said error counts exceeds said upper limit value, said comparator circuit outputting a down-signal for performing control to lower said refresh period when the sum of said error count is lower than said lower limit value, wherein said set value storage circuit includes: a non-volatile storage circuit for holding each of an upper limit value and a lower limit value; a counter for counting a test signal entered thereto; and a selector for selecting outputs of said counter and the non-volatile storage circuit; said selector outputting the value of said non-volatile storage circuit at the time of resetting.