Patent ID: 6466589
Filing Date: 2002-10-15
Classification: H04J,H04L

Abstract:
Anti-meta trap (AMT) circuitry for use with digital data processing circuitry to ensure that digital bit data arriving at the digital data processing circuitry is not sampled at transition state of the bit data, comprising:an input data port for receiving the digital bit data; an input clock port for receiving a global signal by which a local clocking signal CLK is generated; at least four registers electrically coupled to the input data port, the sampling operations of which are each controlled by one of: signal CLK, and sampling signals CLKt, CLKB, and CLKBt; wherein sampling of each data input bit by signal CLK generates a sampled signal SA, by signal CLKt generates a sampled signal SSA, by signal CLKB generates a sampled signal SB, and by signal CLKBt generates a sampled signal SSB; at least first and second dual-input exclusive OR circuits, the first dual-input exclusive OR circuit coupled to the outputs of the registers which generated sampling signals SA and SSA, respectively, and the second dual-input exclusive OR circuit coupled to the outputs of the registers which generated sampling signals SB and SSB, respectively; and an SR flip flop, wherein an output port of the first dual-input exclusive OR circuit is coupled to a set input port of the SR flip flop, an output of the second dual-input exclusive OR circuit is coupled to a reset input port of the SR flip flop, such that an output of the SR flip flop controls the selection of an AMT output data signal which is 1) equivalent to sampled signal SA when signal SA is determined to be equivalent to signal SSA, 2) equivalent to sampled signal SB when signal SB is determined to be equivalent to signal SSB and SA is not equal to SSA.