Patent ID: 7949984
Filing Date: 2011-05-24
Classification: G06F

Abstract:
1. A method of designing a three-dimensional integrated circuit, comprising: designating, in a computer, a plurality of partition lines dividing two-dimensional layout data of a circuit to be formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, each of the plurality of layout block data including data of a semiconductor circuit; generating, in the computer, reversed layout block data reversing of one of two layout block data adjacent to each other among the plurality of layout block data by reversing the one of the layout data symmetrically with respect to a specified partition line among the plurality of partition lines; arranging, in the computer, the reversed layout block data and the other of the two block layout data to form two layers vertically stacked assuming with the semiconductor substrate interposed therebetween; selecting, in the computer, at least one pair of interconnects included in a the two layout block data of the circuit, ranging over the two layers, and mutually and functionally relating, with respect to at least one of time delay, interconnect length and block configuration; and re-arranging, in the computer, the at least one pair of interconnects selected using a via connecting an upper one and an under one of the interconnects.