Patent ID: 9035471
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A semiconductor die comprising: i) an integrated circuit formed on one surface of a piece of semiconductor wafer; ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit; iii) a routing layer formed on said semiconductor wafer, said routing layer comprising a layer of dielectric material; iv) a plurality of under-bump metallizations (UBMs) formed atop said routing layer, each for attaching a respective one of a plurality of solder bumps; and v) a plurality of conductive traces, each extending from one of said I/O pads to a contact point for a corresponding one of said UBMs and electrically interconnecting said one of said I/O pads to said corresponding one of said UBMs; wherein said routing layer comprises one or more stress-buffering areas, each circumscribing a UBM and larger than a bump pad in contact with said UBM, each stress-buffering area comprising at least one of said conductive traces passing beneath one of said UBMs without electrically contacting one of said UBMs, wherein at least one of said stress-buffering areas is between 30% and 100% occupied by said conductive traces.