Patent ID: 7953959
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. A processor which decodes plural instructions and executes the decoded plural instructions in parallel, said processor comprising: an instruction buffer which holds a group of instructions executable in parallel; an instruction decoder that simultaneously decodes at least a portion of the group of instructions; and an instruction issuance controller that detects, based on a number of functional units, whether a factor obstructing simultaneous execution of the group of instructions exists in the group of instructions, and that supplies the group of instructions to said instruction decoder by controlling said instruction buffer so that a subset of the group of instructions are sequentially supplied when the factor obstructing simultaneous execution of the group of instructions exists and each of the group of instructions are simultaneously supplied when the factor obstructing simultaneous execution of the group of instructions does not exist, the functional units executing predetermined instructions included in the group of instructions, wherein said instruction issuance controller sequentially supplies, one-at-a-time, instructions from the group of instructions that correspond to respective values of a counter, when the subset of the group of instructions are sequentially supplied, the counter having, as a largest value, a largest number of instructions simultaneously decodable by said instruction decoder.