Patent ID: 7243273
Filing Date: 2007-07-10
Classification: G11C

Abstract:
1. A memory testing apparatus for testing a plurality of areas of memory cells of a first memory device and a second memory device, comprising: a waveform-shaping module configured to generate a plurality of test signals according to a plurality of address signals and to output each of the plurality of test signals to one of the memory devices; a comparing module configured to compare expected values corresponding to the test signals with output signals from corresponding memory devices of the first memory device and the second memory device in response to the plurality often signals, and to output a plurality of comparison results; an address-compressing module configured to generate compressed addresses for the plurality of comparison results; and an error catch memory configured to record outputted comparison results for both the first memory device and the second memory device in a corresponding plurality of consecutive divisions of the error catch memory according to a corresponding plurality of the compressed addresses for the first memory device and the second memory device, each of the outputted comparison results being stored as a single bit; wherein the memory testing apparatus is configured to test all areas of the plurality of areas and not to test all memory cells in a given area when any comparison result is indicative of a failed memory cell in that area.