Patent ID: 8737392
Filing Date: 2014-05-27
Classification: H04L

Abstract:
1. A processor, comprising: a plurality of processor tiles, each tile comprising a processor core with processor cores of the tiles arranged in a two-dimensional array of rows and columns of processor cores, with a top row of processor cores connected to input/output ports that couple to corresponding input/output ports of a peripheral device; and an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions in which an ordering of dimensions for routing data is configurable, with the interconnection network having a first dimension and a second dimension, and the interconnection network is selectable between at least two configurations, the first configuration routing data along the first dimension before routing the data along the second dimension, the second configuration routing data along the second dimension before routing the data along the first dimension, and when there are more data being sent from the peripheral device to the processor cores, the interconnection network is configured to route data along a column direction followed by routing the data along a row direction and when there are more data being sent from the processor cores to the peripheral device, the interconnection network is configured to route data along a row direction followed by routing the data along a column direction.