Patent ID: 6021476
Filing Date: 2000-02-01
Classification: G06F

Abstract:
A data processing apparatus for controlling access to a memory having a plurality of memory locations for storing data values, each memory location having a corresponding address, the apparatus comprising:address range storage for storing information identifying address ranges for a plurality of logical regions within said memory;attribute storage for storing, for each logical region, attributes used to control access to memory locations within said logical region;address comparator logic for comparing an address issued by a processor corresponding to one of said memory locations with the address ranges for said plurality of logical regions, and, if one or more of the logical regions contain said address, for generating a signal indicating those logical regions containing said address;attribute determination logic, responsive to the signal generated by the address comparator logic, for applying predetermined priority criteria to determine which logical region containing said address has the highest priority, and to output the attributes in the attribute storage corresponding to that highest priority region for use in controlling access to the memory location specified by the address; wherein one of said logical regions being a background region covering the entire memory and having the lowest priority of said logical regions, whereby if the address issued by the processor corresponds to a memory location that is not within any of the other logical regions, then the attribute determination logic is arranged to output the attributes associated with the background region.