Patent ID: 6707496
Filing Date: 2004-03-16
Classification: G11C,H04N

Abstract:
A reading structure including an analog delay line for a MOS image sensor having a pixel array formed from a plurality of individual pixels organized as rows and columns, the reading structure comprising:a first common signal line coupled to a plurality of columns of the pixel array for receiving pixel signals from selected pixels in the columns; a first delay line coupled to the first common signal line for receiving and storing the pixel signals; the first delay line comprising: an input line coupled to the first common signal line; an output line coupled to a second common signal line; a first set of write switches coupled to the input line, the first set of write switches being coupled in parallel and having at least one switch for each of the columns coupled to said first common signal line; a first set of storage capacitors, the first set of storage capacitors having at least one capacitor associated with each of said write switches, the write switches operating in sequence so as to write one of each of the pixel signals from a row of pixels in sequence into one each of said capacitors of said first set of storage capacitors; and a first set of read switches for selectively reading out the pixel signals from the first set of storage capacitors onto the output line; and a second delay line coupled to the first common signal line for receiving and storing the pixel signals; first and second primary write switches for coupling the inputs of the first and second delay lines, respectively, to the first common signal line; and first and second primary read switches for coupling the outputs of the first and second delays lines, respectively, to the second common signal line.