Patent ID: 6683340
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A split-gate flash memory, comprising:a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and having an outer side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on and in contact with the first junction region between two adjacent first spacers, wherein the first spacer insulates the floating gate from the conductive line; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the outer side wall of the first spacer; a word line formed on the second gate insulating layer, and having an inner side wall opposite the spacer side wall and an outer vertical side wall, the word line having a uniform width; a second spacer formed on the outer vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as that of the first junction region; an interlayer insulator formed over the first spacer, word line, and second spacer, and having a contact hole, the contact hole formed on a portion of the second junction region; and a second conductive line formed on the interlayer insulator and contacting the second junction region through the contact hole.