Patent ID: 8981330
Filing Date: 2015-03-17
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: an array of contacts having top surfaces; a patterned insulating layer over the array of contacts, the patterned insulating layer including sidewall features aligned with and directly overlying the top surfaces of a plurality of contacts in the array; a plurality of bottom electrodes, the bottom electrodes including respective sidewall electrode layers on lower portions of the sidewall features contacting respective top surfaces of the contacts in the plurality of contacts, the bottom electrodes having electrode top surfaces; a first insulating fill material disposed adjacent to the sidewall electrode layers with the bottom electrodes between the first insulating fill material and the patterned insulating layer; a second insulating fill material, formed as a separate element from the first insulating fill material and directly overlying the first insulating fill material, disposed adjacent to upper portions of the sidewall features; the first insulating fill material and the second insulating fill material having substantially the same widths between two adjacent sidewall features of the patterned insulating layer; and a plurality of memory elements comprising a confined layer of memory material between the upper portions of the sidewall features and the second insulating fill material, the memory elements in contact with the electrode top surfaces of the plurality of bottom electrodes and a portion of each memory element in the plurality of memory elements is in contact with two adjacent bottom electrodes of the plurality of bottom electrodes.