Patent ID: 6708323
Filing Date: 2004-03-16
Classification: G03F

Abstract:
A computer implemented method for, during a circuit design stage, verifying pattern data of a designed circuit according to given design rules, said pattern data including a plurality of feature data, said method comprising:if there is any feature data not meeting said given design rules, outputting contents of this feature data as an error; if there is inputted first error information indicating that said error is not problematical in view of characteristics of said circuit, then outputting said first error information with said pattern data; during a mask data generating stage, processing for obtaining mask data for manufacturing a mask from the pattern data including the feature data, the processing comprising verifying said feature data processed according to given mask-making rules, where the mask data and mask-making rules are specific to a given exposure system; if any feature data not meeting said given mask-making rules exists, automatically judging whether or not contents of this feature data corresponds to said first error information; and if the contents of the feature data is judged to correspond to said first error information, then if said first error information indicates not being problematic, automatically judging that said feature data not meeting said given mask-making rules is not problematic.