Patent ID: 6331796
Filing Date: 2001-12-18
Classification: H03K

Abstract:
A semiconductor integrated circuit device comprising:a pass-transistor logic circuit having at least one n-type MOS transistor forming a logic circuit to supply a logic output signal; anda load circuit having a CMOS inverter including a p-type MOS transistor forming the CMOS inverter and an n-type MOS transistor forming the CMOS inverter which are connected in series between a first power source and a second power source, said p-type MOS transistor forming the COMS inverter and said n-type MOS transistor forming the CMOS inverter having gate terminals supplied with said logic output signal forming the input of said CMOS inverter, said p-type MOS transistor forming the CMOS inverter and said n-type MOS transistor having a common connected point from which a load output signal is output and which forms the output of said CMOS inverter, the threshold voltage value Vtn of said n-type MOS transistor forming the CMOS inverter being substantially equal to the threshold voltage value Vtn of said n-type MOS transistor forming the logic circuit, and said p-type MOS transistor forming the CMOS inverter having the threshold voltage value whose absolute value .vertline.Vtp.vertline. is larger than the threshold voltages Vtn of the n-type MOS transistor forming the logic circuit and the n-type MOS transistor forming the CMOS inverter; andwherein said load circuit further comprises a feedback mechanism including a p-type MOS transistor for feedback purposes having a source terminal connected to said first power source, a gate terminal connected to the output of the CMOS inverter and a drain terminal connected to the input of the CMOS inverter;wherein said feedback mechanism does not function when said pass-transistor logic circuit is in its operative mode, but supplies said first power source to the input of the CMOS inverter when said pass-transistor logic circuit is in its non-operative mode and the logic output signal is high level.