Patent ID: 7670890
Filing Date: 2010-03-02
Classification: H01L

Abstract:
1. A method of forming a p type junction field effect transistor (PJFET) and an n type junction field effect transistor (NJFET) in a semiconductor substrate, comprising: forming a first n type buried layer (NBL1) in the substrate; forming a first p type buried layer (PBL1) in the substrate, but laterally spaced from the NBL1; forming a first n type epitaxial layer (NEPI1) over the substrate; forming a second p type buried layer (PBL2) over the PBL1 in the NEPI1; forming one or more DEEPNX regions over the NBL1 in the NEPI1; forming a second n type epitaxial layer (NEPI2) over the NEPI1; forming a p type surface shield near an upper surface of the NEPI2, where the p type surface shield resides over at least some of the PBL2; forming an n type channel of the NJFET in the NEPI2, where the n type channel resides over at least some of the PBL2; forming a p type bottom gate (BG) near a lower surface of the NEPI2, where the p type BG resides over at least some of the PBL2; forming an n type surface shield near an upper surface of the NEPI2, where the n type surface shield resides over at least some of the NBL1; forming a p type channel of the PJFET in the NEPI2, where the p type channel resides over at least some of the NBL1; forming one or more isolation areas that isolate the PJFET from the NJFET at least by being formed between the NBL1 and the PBL1; forming one or more n type back gate contact regions in the NEPI2 down to the one or more DEEPNX regions; forming one or more p type back gate contact regions in the NEPI2 down to the PBL2; forming a layer of silicide block material (SBLK) over the NEPI2; patterning the SBLK to expose areas of the NEPI2 where gate, source and drain regions are to be formed; forming an n type gate region in the p type channel of the PJFET, and n type source and drain regions in the n type channel of the NJFET; forming p type source and drain regions in the p type channel of the PJFET, and a p type gate region in the n type channel of the NJFET; siliciding the gate, source and drain regions in the p type channel of the PJFET and in the n type channel of the NJFET; forming a layer of dielectric material over the silicided gate, source and drain regions and over the NEPI2; forming conductive contacts extending down through the layer of dielectric material to the silicided gate, source and drain regions in the p type channel of the PJFET and in the n type channel of the NJFET; and forming a field plate over at least one of the conductive contacts extending down to one of the gate, source and drain regions of at least one of the PJFET and the NJFET, where the field plate also extends over at least some of at least one other of the gate, source and drain regions of the at least one of the PJFET and the NJFET.