Patent ID: 8089145
Filing Date: 2012-01-03
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads disposed in spaced relation to the die pad, each of the first leads defining a land; a plurality of second leads disposed in spaced relation to the die pad, each of the second leads defining a land; a plurality of third leads disposed in spaced relation to the die pad; a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second and third leads; a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the semiconductor die and the first, second and third leads, the package body including a plurality of openings formed in the bottom surface thereof, each of the openings extending to a respective one of the lands of the first and second leads; and a plurality of conductive elements disposed within each of the openings, each of the conductive elements being electrically connected to a respective one of the lands and protruding from the bottom surface of the package body, the conductive elements attached to the first leads being separated from corresponding ones of the conductive elements attached to the second leads by at least one groove which is formed in the bottom surface and extends therebetween.