Patent ID: 6657896
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including electrically rewritable nonvolative memory cells arranged therein; a plurality of latch circuits which temporarily hold data read out from the memory cell array; a first circuit configured to generate a first current which varies in proportion to â€œ1â€  or â€œ0â€  of binary logical data of one end of the plurality of latch circuits; a second circuit configured to generate a predetermined second current; a current control circuit connected to the first and second circuits, and configured to determine absolute values of the first current and the second current; and a third circuit configured to compare the first current and the second current, wherein the number of â€œ1â€  or â€œ0â€  of binary logical data of the one end of the plurality of latch circuit is detected based on a result of comparison between the first current and the second current.