Patent ID: 6235593
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method of fabrication of a self aligned contact (SAC) using thin interlevel dielectric spacers comprising the steps of:a) forming spaced isolation regions in a substrate; said substrate having a self aligned contact area and a borderless contact area;b) forming a gate dielectric layer on said substrate;c) forming a conductive layer over said gate dielectric layer;d) forming a cap layer over said conductive layer; said cap layer having a bottom;e) patterning said cap layer, said conductive layer and said gate dielectric layer to form spaced gate structures on said substrate; implanting ions into said substrate adjacent to said gate structures to form LDD regions in said substrate; depositing a liner layer over said substrate and said gate structure;f) forming an interlevel dielectric layer over said substrate and gate structures;g) etching said interlevel dielectric layer and said cap layer forming a contact hole that exposes said LDD region between said gate structures; and that removes a section of said liner layer on said cap layer leaving remaining portions of said liner layer, and removes a portion of said cap layer; said contact hole having sidewalls of said interlevel dielectric layer; said contact hole have an upper opening above the top of said conductive layer; and a lower opening below the bottom of said cap layer; the remaining portion of said liner layer on the sidewalls of said gate structure is a first liner spacer;h) forming an interlevel dielectric spacer layer over said interlevel dielectric layer, the sidewalls of said contact hole and on said LDD region;i) anisotropically etching said interlevel dielectric spacer layer forming a top spacer on the sidewalls of said upper opening and a bottom spacer on said lower opening; said bottom spacer is on said first liner spacer; andj) forming a contact plug filling said contact hole and electrically contacting said LDD region.