Patent ID: 6041341
Filing Date: 2000-03-21
Classification: G06F

Abstract:
A method of adding operands comprising the steps:inputting a first m bit operand into m least significant first inputs of an n bit adder, where n is greater than m;inputting a second m bit operand into m least significant second inputs of the n bit adder;inputting a first (n-m) bit operand into the (n-m) most significant first inputs of the n bit adder, wherein each bit of the first (n-m) bit operand represents logical zero;inputting a second (n-m) bit operand into the most significant (n-m) second inputs of the n bit adder, wherein each bit of the second (n-m) bit operand represents logical one;inputting a carry in bit into a carry input of the adder;wherein the first m bit operand, second m bit operand, first (n-m) bit operand, the second (n-m) bit operand, and the carry in bit are all inputted into the n bit adder in parallel;generating a set of n carry out bits;generating an n bit output operand, and;wherein the least significant m bits of the n bit output operand and the most significant carry out bit represent a result of adding the first m bit operand, the second m bit operand, and the carry in bit.