Patent ID: 6742113
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A microprocessor having an exception, interrupt, and trap (EIT) processing function for branching a program processing sequence to an EIT vector area for executing an EIT process program when an EIT process is initiated, said microprocessor being connected to an external memory having an EIT vector area containing programs for a plurality of EIT processes, said microprocessor comprising:an internal memory for storing first data in a first area of the internal memory and second data in a second area of the internal memory, said first data being identical to data in a first portion of the EIT vector area of the external memory and said second data being identical to data in a second portion of the EIT vector area of the external memory; a determining circuit for determining whether an EIT process initiated during process sequence execution is a first EIT process, a second EIT process or a third EIT process among the plurality of EIT processes; and a branch destination changer for setting a process sequence branch destination to the EIT vector area stored in the external memory when the determining circuit determines the initiated EIT process to be the first EIT process, setting the process sequence branch destination to the first area of the internal memory when the determining circuit determines the initiated EIT process to be the second EIT process, and setting the process sequence branch destination to the second area of the internal memory when the determining circuit determines the initiated EIT process to be the third EIT process, wherein the branch destination changer includes: a first register for storing a first upper address specifying the first area of the internal memory; a second register for storing a second upper address specifying the second area of the internal memory; a first selector connected to the first and second registers, for selecting one of the first upper address, the second upper address and a third upper address specifying the external memory, the first selector outputting the third upper address when the determining circuit determines the initiated EIT process to be the first EIT process, outputting the first upper address when the determining circuit determines the initiated EIT process to be the second EIT process, and outputting the second upper address when the determining circuit determines the initiated EIT process to be the third EIT process; a plurality of registers for storing lower addresses respectively corresponding to the plurality of EIT processes; and a second selector for selecting the plurality of registers and output the lower address stored in the selected register, wherein the process sequence branch destination is specified by the upper address output from the first selector and the lower address output from the second selector.