Patent ID: 8954754
Filing Date: 2015-02-10
Classification: G06F,H04L

Abstract:
1. A processor, comprising: an instruction decoder to receive a first instruction to process a SHA-1 hash algorithm, the first instruction having a first operand to store a SHA-1 state, a second operand to store a plurality of messages, and a third operand to specify a hash function; and an execution unit coupled to the instruction decoder, in response to the first instruction, to perform a plurality of rounds of the SHA-1 hash algorithm on the SHA-1 state specified in the first operand and the plurality of messages specified in the second operand, using the hash function specified in the third operand, wherein the instruction decoder receives a second instruction, and wherein in response to the second instruction, the execution unit performs a first part of message scheduling operations based on a plurality of first previous messages specified by the second instruction.