Patent ID: 8725989
Filing Date: 2014-05-13
Classification: G06F

Abstract:
1. A processor comprising: a scalar register file; a single instruction multiple data (SIMD) register file; an execution unit to perform a function call from a main program to a function that is to operate on at least one SIMD operand, wherein the execution unit is to pass only scalar values to the function, and input values to the function including the at least one SIMD operand are to be renamed from input registers expressed in code of the function to registers of the SIMD register file; an input output register mask to be programmed by the main program and to store a value corresponding to an identity of registers of the SIMD register file to be used in the function; an input output rename table to store a plurality of entries, wherein the plurality of entries are to be generated responsive to the value of the input output register mask, the input output rename table to be indexed by the input or output registers and each indexed entry is to identify a corresponding register of the SIMD register file to be used in the function; and a virtual input output register mask to be programmed by the function and to store a value corresponding to an identity of virtual registers of the SIMD register file to be used by a second function called by the function, wherein the input output rename table is to provide a mapping between virtual register numbers used by the second function to register numbers of the SIMD register file.