Patent ID: 9141550
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A computer system for prefetching data on a chip, the system comprising: a parent core located on the chip, the parent core configured to selectively execute a plurality of applications, one of the plurality of applications being a specific application; and at least one scout core located on the chip, the system configured to perform a method comprising: saving a prefetch code start address by the parent core, the prefetch code start address indicating where a prefetch code is stored, and the prefetch code specifically configured for monitoring the parent core based on the specific application being executed, wherein the parent core saves the prefetch code start address based on a task swap occurring within the parent core; sending a broadcast interrupt signal by the parent core to the at least one scout core, the broadcast interrupt signal being sent based on the prefetch code start address being saved; and monitoring the parent core by the at least one scout core, the at least one scout core executing the prefetch code to monitor the parent core, the executing of the prefetch code based on receiving the broadcast interrupt signal.