Patent ID: 6366514
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A memory refresh structure, comprising:an original clock generator for periodically generating an original clock signal; a first clock generator for periodically generating a first clock signal; a memory array composed by a plurality of memory cells which are grouped into a plurality of original memory segments; an original segment pointer generator for generating, according to the original clock signal, an original pointer to cyclically select, in a predetermined order, one of the original memory segments and to trigger the refreshing of the memory cells in the selected original memory segment; and a first segment pointer generator for one-to-one tagging of the original memory segments as first memory segments and generating, according to the first clock signal, a first pointer to select, in a predetermined order, one of the first memory segments, and to trigger the refreshing of the memory cells in the selected first memory segment; wherein an original refresh time interval, defined as the interval of time between refreshes triggered by the original pointer for each of the memory cells in the original memory segments, is longer than a first refresh time interval, defined as the interval of time between refreshes triggered by the first pointer for each of the memory cells in the first memory segments.