Patent ID: 6329844
Filing Date: 2001-12-11
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a first p-type MOS transistor whose source is connected to an electric power-supply, whose gate is connected to a first node, and whose drain is connected to a second node;a second p-type MOS transistor whose source is connected to said second node, whose gate is connected to a first input terminal, and whose drain is connected to a first output terminal;a first n-type MOS transistor whose source is con-nected to ground, whose gate is connected to a fifth node, and whose drain is connected to a third node;a second n-type MOS transistor whose source is connected to said third node, whose gate is connected to said first input terminal, and whose drain is connected to said first output terminal; anda logic circuit connected to receive as inputs said first output terminal and a second input terminal, said logic circuit having a first output connected to drive said first node and a second output connected to drive said fifth node.