Patent ID: 6717070
Filing Date: 2004-04-06
Classification: H05K

Abstract:
A printed wiring board, comprising:an insulating layer having a first surface, and a second surface located on an opposite side of said first surface; first to third circuit patterns arranged apart from one another on said first surface, said first to third circuit patterns being formed by etching metal foil deposited on said first surface, said metal foil being plated after the etching, wherein said first circuit pattern is a line through which an electric currently flows; a plurality of fourth circuit patterns formed on said second surface, said fourth circuit patterns being formed by etching metal foil deposited on said second surface, said metal foil being plated after the etching; a via formed on said insulating layer, said via having one end opened on said first surface of said insulating layer and surrounded by said second circuit pattern on said first surface, and another end closed by a circuit pattern of said plurality of fourth circuit patterns formed on said second surface of said insulating layer; a first plating layer having (1) a first portion that covers an inner surface of said via and a circuit pattern of said fourth circuit patterns that closes said another end of said via and which is exposed within said via, (2) a second portion covering a part of said second circuit pattern on said first surface, said second portion surrounding said one end of said via and connected to said first portion, and (3) a third portion that covers a part of said first circuit pattern formed on said first surface such that the first circuit pattern has a part covered by the third portion and a part exposed on the first surface, wherein the first to third portions are simultaneously processed; and a second plating layer laminated on said first plating layer and electrically connecting said second circuit pattern formed on said first surface with said circuit pattern of the plurality of said fourth circuit patterns that closes said another end of said via, wherein a part of the second plating layer that covers the third portion forms a thick portion in cooperation with the third portion, said thick portion having an increased thickness on a part of said first circuit pattern formed on said first surface and being shorter than said first circuit pattern, wherein a current capacity in said first circuit pattern is increased in said thick portion.