Patent ID: 6329255
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method for making self-aligned bit-lines on a semiconductor wafer, the semiconductor wafer comprising a first dielectric layer, the first dielectric layer comprising a plurality of node contact holes and bit-line contact holes, the method comprising:forming a first conducting layer over the surface of the semiconductor wafer, the first conducting layer filling each node contact hole;forming a protective layer and a first photoresist layer over the first conducting layer;performing a first lithographic process to transfer node contact patterns to the first photoresist layer, each node contact pattern located above a corresponding node contact hole;etching the protective layer and the first conducting layer, using the first photoresist layer as a hard mask, down to the first dielectric layer to form each node contact and bit-line contact;removing the first photoresist layer;forming a spacer around each node contact;forming a second dielectric layer over the surface of the substrate;forming a second photoresist layer over the second dielectric layer;performing a second lithographic process to transfer bit-line contact patterns to the second photoresist layer;etching the second dielectric layer down to the first dielectric layer and the surface of each bit-line contact, using the pattern of the second photoresist layer as a hard mask, so as to form a trench for each bit-line contact in the second dielectric layer;removing the second photoresist layer;forming a second conducting layer over the surface of the semiconductor wafer, the second conducting layer filling each trench;performing an etching back process to remove the second conducting layer from the top of the second dielectric layer, and to partially remove the second conducting layer from each trench down to a certain depth, so as to form each bit-line; andforming a third dielectric layer over the surface of the semiconductor wafer to fill each bit-line trench.