Patent ID: 6858924
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A semiconductor device comprising an internal circuit area receiving therein a plurality of input/output (I/O) pads arranged in an array and a peripheral area surrounding said internal circuit area, said internal circuit area receiving therein a plurality of internal I/O modules, each of said I/O modules including said I/O pads and a plurality of I/O buffers each corresponding to one of said I/O pads, and at least one internal test line for supplying a common test signal to said I/O buffers, wherein said internal test line includes: an out-module test line extending outside an area of said internal I/O module and formed as a common layer with said I/O pads; a first in-module test line extending within said area of said internal I/O module and formed as said common layer; and a second in-module test line extending within said area of said internal I/O module and connected between said first in-module test line and said I/O buffers.