Patent ID: 6487127
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A circuit configuration for reading and writing binary information at a memory cell field arranged in a matrix of rows and columns of memory cells each connected to a word line allocated to a row and a bit line allocated to a column of the memory cells, comprising:write/read circuits each connected to access a respective memory cell via a word line and a bit line; each of said write/read circuits containing a gate circuit controllable by a column selection signal, and a latch flipflop having a current supply and at least one data terminal connected between an allocated bit line and a data line via said gate circuit; a switching device connected to said current supply of said latch flipflops, said switching device, subsequently to an excitation of any word line, interrupting the current supply to said latch flipflops in the write/read circuits that are controllable by the column selection signal, from an instant no earlier than a time at which the respective latch flipflop assumes a state indicating an information content of the accessed memory cell and, at the latest, within an active interval of the relevant column selection signal.