Patent ID: 7667231
Filing Date: 2010-02-23
Classification: G01R,H01L

Abstract:
1. A semiconductor wafer comprising a plurality of dice, comprising: a) at least a first die of said plurality of dice comprising its own conductive trace; and, b) a fixed voltage node of an on wafer test circuit coupled to said conductive trace, said on-wafer test circuit to support testing of said at least a first die during an on-wafer test sequence, said fixed voltage node to provide a fixed voltage to said at least a first die during said on-wafer test sequence, said at least a first die's conductive trace having a narrowed region in at least one section of said conductive trace such that said narrowed region has a smaller width than another region of said conductive trace that neighbors said narrowed region, said width of said narrowed region being greater than or substantially equal to a width of a transistor gate node within said at least a first die, said narrowed region located at a same layer as said transistor gate node.