Patent ID: 6725247
Filing Date: 2004-04-20
Classification: H03H

Abstract:
An integrated circuit comprising:a two-dimensional pyramid filter architecture of an order 2Nâˆ’1, where N is a positive integer greater than five; said two dimensional pyramid filter architecture of order 2Nâˆ’1, in operation, capable of producing, on respective clock cycles, at least the following: pyramid filtered output signals corresponding to output signals produced by fourteen one-dimensional pyramid filters of order 2Nâˆ’1; and pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(Nâˆ’1)âˆ’1] using signal sample matrices of order [2(Nâˆ’1)âˆ’1]; wherein the respective output signals in said two dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.