Patent ID: 8434036
Filing Date: 2013-04-30
Classification: G06F

Abstract:
1. An arithmetic-program conversion apparatus comprising: a program storage section storing an arithmetic program describing a circuit to be designed by a logical expression including a plurality of input variables, operators, and an output variables; if the logical expression having three input variables or more is stored in the program storage section, an intermediate-variable generation section generating an intermediate variable to be used for converting the logical expression into a plurality of binomial expressions wherein each binomal expression includes two input variables and one output variable; if the intermediate variable is generated by the intermediate-variable generation section, an expression conversion section converting the logical expression into a plurality of binomial expressions including a binomial expression for obtaining the intermediate variable and a binomial expression for obtaining the output variable from the intermediate variable; if a plurality of binomial expressions are generated by the converting process of the expression conversion section, an expression update section updating the logical expression originally stored in the program storage section by the plurality of binomial expressions; a bit-width determination section determining bit widths of the output variable, the input variables, and the intermediate variable of the logical expression stored in the program storage section; and a bit-width storage section storing the bit width of the output variable, the bit width of the input variables, and the bit width of the intermediate variable.