Patent ID: 9047946
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A read circuit reading data from a non-volatile memory array including a variable resistance memory cell, the read circuit comprising: a current load circuit configured to supply a load current from a power source to a first input and a second input, which are coupled to the non-volatile memory array; a first discharge circuit configured to discharge potential of the first and second inputs to a ground level by control with a first discharge signal; an equalization circuit configured to short-circuit the first and second inputs by control with equalization signal to equalize the potential of the first and second inputs; a differential circuit configured to receive the first and second inputs as differential inputs, and to output a first read output and a second read output as differential outputs; and a second discharge circuit configured to discharge potential of the first and second read outputs to the ground level by control with a second discharge signal.