Patent ID: 9189384
Filing Date: 2015-11-17
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a storage medium including a plurality of nonvolatile memory devices and configured to store data; and a memory controller including a buffer memory and configured to control the plurality of nonvolatile memory devices, wherein the memory controller manages a life of each of the nonvolatile memory devices based on whether a program-erase number of each memory block of each nonvolatile memory device reaches a reference value, wherein when the program-erase number of each memory block of a nonvolatile memory device reaches the reference value, addresses transferred to the nonvolatile memory device during a write operation where data are sequentially stored in at least two memory blocks of the nonvolatile memory device are partially discontinuous, and wherein when the program-erase number of each memory block of each nonvolatile memory device reaches the reference value, the memory controller controls each nonvolatile memory device such that at least two word lines located at both edges of each memory block are faded out or the memory controller controls each nonvolatile memory device such that odd or even word lines of word lines of each memory block are faded out.