Patent ID: 9200956
Filing Date: 2015-12-01
Classification: G01J,H01L,H04N

Abstract:
1. A readout transistor circuit for a pixel, comprising: a sense node of a back-illuminated CMOS imager pixel; a reset transistor in signal communication with the sense node; a source follower transistor in signal communication with the sense node; a row select transistor in signal communication with the sense node; a switching transistor in signal communication with the sense node, the switching transistor connected to a source terminal of the reset transistor; and a capacitor connected between a source terminal of the switching transistor and ground, wherein the switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e−) ratio and a high voltage-per-charge (V/e−) to enable low noise performance of the sense node.