Patent ID: 6372664
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method for forming upon a substrate employed within a microelectronics fabrication a dielectric layer comprising:providing a substrate; forming upon the substrate a series of lines which constitute a patterned microelectronics layer; forming over the substrate a first conformal dielectric layer having a thickness of from about 500 to 1200 Ã¥; the first conformal dielectric layer formed employing a PECVD method using: a silane gas flow rate from about 100 to 150 sccm; a nitrous oxide gas flow rate from about 1000 to 1500 sccm; a power of from about 250 to 300 watts; a temperature of about 400Â° C.; a total pressure of from about 2 to 2.5 Torr; and an electrode separation of from about 0.4 to 0.45 inches; forming over the first dielectric layer a second dielectric layer having a thickness of from about 2000 to 6000 Ã¥; the second dielectric layer formed employing an APCVD method with ozone/TEOS gases using: an ozone gas flow rate from about 4500 to 5500 sccm a TEOS gas flow rate from about 250 to 300 mg/min; a helium carrier gas flow rate from about 3500 to 4500 sccm; a total pressure of from about 400 to 500 Torr; and an electrode separation of from about 0.2 to 0.25 inches; and forming over the substrate a third non-conformal dielectric layer having a thickness of from about 5000 to 9000 Ã¥; the third non-conformal dielectric layer formed employing the method of high-density plasma chemical vapor deposition (HDP-CVD) using: a silane source gas flow rate from about 50 to 80 sccm; an O2 oxidizing gas flow rate from about 90 to 120 sccm; an argon gas flow rate from about 110 to 130 sccm; a temperature of about 400Â° C.; a total pressure of from about 6 to 9 Torr; and an RF power of from about 1000 to 1500 watts source power, from about 3000 to 3500 watts side power, and from about 2000 to 3000 bias power.