Patent ID: 6383887
Filing Date: 2002-05-07
Classification: H01L,Y10S

Abstract:
A method of forming a monolithic integrated circuit comprising:fabricating integrated circuitry over a portion of a semiconductor substrate, the integrated circuitry comprising elements including transistors, capacitors and resistive elements, the fabrication of at least one of the capacitors comprising: forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon and including unexposed undoped silicon in contact with the node location; substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon, wherein forming a mass of silicon material over a node location comprises: forming an insulative layer over the portion of the semiconductor substrate; forming an opening through the insulative layer to expose a node location; forming a layer of undoped silicon within the opening and in contact with the node location; filling the opening with a core of doped silicon; and etching the insulative layer to expose a portion of the undoped silicon.