Patent ID: 6732132
Filing Date: 2004-05-04
Classification: G06F

Abstract:
In a digital signal processor including an arithmetic operation unit, at least one internal register connected to said arithmetic operation unit, and at least one external register, said arithmetic operation unit carrying out arithmetic processing by receiving data stored in said at least one internal register to carry out an arithmetic operation using said at least one internal register, and receiving data stored in said at least one external register to carry out an arithmetic operation using said at least one external register,the improvement comprising: a path commonly used for transfer of said data stored in said at least one internal register for said arithmetic operation using said at least one internal register and said data stored in said at least one external register for said arithmetic operation using said at least one external register; and a variable delay device interposed in said path; wherein based on changeover of said delay time of said variable delay device, said arithmetic operation unit carries out said arithmetic processing in a predetermined constant time period irrespective of whether said arithmetic processing is said arithmetic operation using said at least one internal register or said arithmetic operation using said at least one external register.