Patent ID: 7260005
Filing Date: 2007-08-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells; a plurality of sense amplifiers coupled to the memory cells; a plurality of signal lines, each of the signal lines being coupled to an output of at least one of the sense amplifiers; a plurality of isolating circuits, each of the isolating circuits being associated with one of the signal lines and isolating that signal line from the output of the sense amplifier to which it is coupled during an evaluating phase in which a datum stored in one of the memory cells is evaluated by that sense amplifier; and a precharging circuit for precharging the signal lines; wherein the plurality of signal lines comprises at least a first group of the signal lines and a second group of the signal lines, arranged such that coupling capacitances between the signal lines of the first group and the signal lines of the second group are substantially negligible, and the precharging circuit precharges the signal lines of the first group to a first voltage level and precharges the signal lines of the second group to a second voltage level, which is different than the first voltage level.