Patent ID: 7017134
Filing Date: 2006-03-21
Classification: G06F,H01L

Abstract:
1. An automatic floor-planning method comprising: extracting a register and a logic operation cell in a semiconductor integrated-circuit unit to be designed; extracting a first register set that is assumed to input a signal to the logic operation cell directly or via another logic operation cell and a second register set that is assumed to receive a signal from the logic operation cell directly or via the other logic operation cell; creating a set of the logic operation cells as a cluster cell, based on extracting the first register set and the second register set, wherein the creating includes creating a set of the logic operation cells common to the first register set and the second register set as one cluster cell; determining layout of the cluster cell and the register such that the logic operation cells in the cluster cell are arranged closely; selecting a logic level block, for which a floor plan is performed, from among arbitrary logic level blocks that are formed by a set of the register and the logic operation cells in the semiconductor integrated-circuit unit; and determining an arrangement and a wiring area, based on the selecting, such that the arrangement and the wiring area of the logic level block selected includes as many cells as possible that belong to the logic level block.