Patent ID: 6247166
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A computer implemented method for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits comprising the steps of:(a) receiving initial user selections for a hierarchical macro to be created; said initial user selections including a command list of multiple leaf cell build commands; responsive to said received initial user selections, automatically performing the steps of:(b) initializing X and Y placer pointers;(c) obtaining a next build command from the command list and identifying a command type;(d) identifying a next leaf cell build command in a leaf cell group;(e) identifying a user selected schematic or physical view, and reading a corresponding leaf cell view for the user selected schematic or physical view; said leaf cell view represented by a symbol;(f) obtaining X and Y sizes for the leaf cell view;(g) orienting and placing the leaf cell; including the steps of providing connections to adjacent leaf cells by abutting leaf cells together;(h) calculating next X and Y placer pointers; and(i) repeating steps (d)-(h) until a last leaf cell build command in the leaf cell group is found;(j) returning to step (c) for obtaining a next build command from the command list and identifying a command type;(k) for the user selected schematic view, obtaining each unconnected pin from all symbols along the perimeter of the placed leaf cells, and connecting said obtained pins to schematic pins of same name and type;(l) condensing said schematic pins by removing bussing from single bit busses and combining bussed single pins into multiple bit bus pins; and(m) creating a symbol view; and (n) moving said combined bus pins to different sides and adjusting pin spacing of said moved pins responsive to received user selections.