Patent ID: 6350705
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A wafer scale package, comprising:a semiconductor wafer, including chip images separated by a kerf area and having a topmost passivating layer through which pass connecting studs; on said topmost passivating layer, a planarizing layer; on the planarizing layer, a redistribution network connected to said studs; on said planarizing layer, a body of silicone elastomer having an upper surface, said body of silicone elastomer being able to absorb stress due to thermal mismatch between said semiconductor wafer and said body of silicone elastomer; embedded within said silicone elastomer body, a plurality of metal posts, each having an upper end and a lower end, said metal posts being of a diameter and height and of a material such that they can bend to absorb stress due to said thermal mismatch; said redistribution network being in contact with, and fixed to, said lower ends, the metal posts passing vertically through said body of silicone elastomer from the redistribution network; each said upper end being in contact with, and fixed to, a metal pad that lies on said upper surface; and on each of said metal pads, a solder bump that does not overlap said upper end, being separated therefrom by a finite distance and thereby isolating the solder bumps from stresses due to rigidity of the metal posts.