Patent ID: 8779520
Filing Date: 2014-07-15
Classification: G11C,H01L

Abstract:
1. An erasable programmable single-poly nonvolatile memory, comprising: a substrate structure; a floating gate transistor comprising a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a P-well region, a n-type source/drain region connected to an erase line voltage and a first n-type region formed between the n-type source/drain region and the P-well region; wherein the P-well region comprises: a first p-type region formed under a surface of the substrate structure and contacted to a first n-type region; a plurality of second p-type regions; and a third p-type region formed under the first p-type region; wherein, the first p-type region and the third p-type regions are located between the second p-type regions; and wherein the first n-type region is a double diffused drain region, the N-well region and the P-well region are formed in the substrate structure, the gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.