Patent ID: 9165901
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor chip including a field effect transistor and having a first main surface over which a source electrode and a gate electrode of the field effect transistor are formed and a second main surface opposite the first main surface over which a drain electrode of the field effect transistor is formed; a metal-made support board having a top surface over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces the top surface of the metal made support board and a bottom surface opposite the top surface; a gate lead electrically connected to the gate electrode of the semiconductor chip via a gate wire; a source lead electrically connected to the source electrode of the semiconductor chip via a plurality of sources wires; and a sealing body sealing the semiconductor chip, the gate wire, the plurality of source wires, and a part of each of the gate and source leads, and wherein, in a plan view, the semiconductor chip has a quadrangular shape having a first chip side, a second chip side opposite the first chip side, a third chip side that intersects with the first and second chip sides, and a fourth chip side opposite the third chip side, wherein, in the plan view, the gate and source leads are disposed to be more proximate to the third chip side than each of the first, second, and fourth chip sides of the semiconductor chip, wherein, in the plan view, the gate electrode is disposed at a corner portion defined by the first and fourth chip sides of the semiconductor chip, wherein, in the plan view, the gate electrode is disposed to be more proximate to the fourth chip side than a respective connecting portion between each of the plurality of source wires and the source electrode in a first direction in which the first chip side extends, wherein, in the plane view, the gate electrode has a first gate side and a second gate side opposite the first gate side wherein, in the plan view, the first and second gate sides respectively face the first and second chip sides, wherein, in the plan view and in a second direction that is perpendicular to the first direction, the first gate side is located between the first chip side and the second gate side, and the second gate side is located between the first gate side and the second chip side, wherein the plurality of source wires includes a first source wire that is most proximate to the gate wire among the plurality of source wires, and wherein, in the plan view, the second gate side of the gate electrode is located in a range of a width in the second direction of an end portion of the first source wire of the respective connecting portion between the first source wire and the source electrode.