Patent ID: 6468862
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method for fabricating a floating gate, the method comprising:forming a tunneling dielectric layer on a semiconductor substrate; forming a first conductive layer; patterning the first conductive layer, the tunneling dielectric layer and the substrate to form a trench, whereby the first conductive layer is patterned to form a conductive structure; forming an insulating layer over the substrate, wherein the insulating layer fills the trench; removing a portion of the insulating layer to form a raised shallow trench isolation (STI) structure, wherein a portion of sidewalls of the conductive structure is also exposed; forming a dielectric layer over the substrate; etching back the dielectric layer to form a spacer structure on the exposed portion of the sidewalls of the conductive structure; removing a portion of the conductive structure to a predetermined depth to further expose a sidewall of the spacer structure; forming a conformal second conductive layer over a topographic surface of the substrate, wherein the second conductive layer has contact with the conductive structure; and patterning the second conductive layer, whereby the second conductive layer and the conductive structure serve together as a floating gate.