Patent ID: 6693476
Filing Date: 2004-02-17
Classification: H03K

Abstract:
A differential latch comprises:sample transistor section operably coupled to sample, when coupled to a supply voltage, a differential input signal to produce a sampled differential input signal; hold transistor section operably coupled to latch, when coupled to the supply voltage, the sampled differential input signal thereby producing a latched differential signal; first gating circuit operable to couple the sample transistor section to the supply voltage in accordance with a first clocking logic operation and a second clocking logic operation, wherein the first clocking logic operation is based on a negative leg and a positive leg of a differential clock signal, and wherein the second clocking logic operation is based on the negative leg and the positive leg of the differential clock signal; and second gating circuit operable to couple the hold transistor section to the supply voltage in accordance with a third clocking logic operation and a fourth clocking logic operation, wherein the third clocking logic operation is based on the negative leg and the positive leg of the differential clock signal, and wherein the fourth clocking logic operation is based on the negative leg and the positive leg of the differential clock signal.