Patent ID: 7190632
Filing Date: 2007-03-13
Classification: G11C

Abstract:
1. A semiconductor memory device which receives and outputs data in synchronization with a reference clock signal, comprising: a memory cell array; a first global column selection line and a second global column selection line via which a first global column selection signal and a second global column selection signal are respectively transmitted to select a column of the memory cell array, the first and second global column selection signals having a first frequency lower than the reference clock signal frequency, wherein the first global column selection signal is out of phase with the second global column selection signal; a pair of column selection gates connected between a pair of bit lines and a pair of input/output lines, wherein gate terminals of the column selection gates are connected to a local column selection line; and a logic operation unit performing a logic operation on the first and second global column selection signals and outputting a local column selection signal, the local column selection signal having a second frequency higher than the first frequency, wherein the local column selection signal is applied to the gate terminals of the column selection gates via the local column selection line.