Patent ID: 6028336
Filing Date: 2000-02-22
Classification: H01L

Abstract:
In a flash EEPROM formed on a semiconductor substrate with a plurality of adjacent rows of memory cells, individual ones of said rows comprising:a plurality of floating gates, one floating gate per memory cell, having two opposing side walls,an elongated control gate having its length extending along the row in a position over the floating gates in a manner to establish a capacitive coupling therebetween, andat least one elongated erase gate having its length extending along one side of the row in a manner to establish a capacitive coupling with the floating gates thereof through a tunnel dielectric therebetween,wherein said tunnel dielectric is provided on one of said two floating gate side walls; a spacer is provided on another of said two floating gate side walls; and said spacer isolates said another floating gate side wall from an erase gate of an immediately adjacent one of said rows.