Patent ID: 6249533
Filing Date: 2001-06-19
Classification: G01R

Abstract:
A pattern generator comprising:address generating means (VGC) for generating a pattern address;control signal generating means (Cfor generating a control signal;address converting means for converting a pattern address from said address generating means into at least first and second address signals on the basis of a control signal from said control signal generating means, each of the address signals being composed of a plurality of bits;m memory means (m being an integral multiple of the number n of pins of a semiconductor device under test) each having predetermined pattern data previously stored therein and responsive to said first address signal supplied thereto to generate corresponding pattern data;n sequence registers responsive to said second address signal supplied thereto to generate data of a preset sequence; andn select means each selecting one of said memory means depending upon the preset sequence data outputted from said sequence registers, and applying to corresponding one of pins of said semiconductor device under test a test pattern based on pattern data stored in the selected memory means.