Patent ID: 6389528
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A processor arranged to execute instructions from a predetermined set of instructions of which at least one is formed of an operation section and an operand section, wherein the set includes a control instruction having an operand section that includes control signals controlling operation of the processor, the processor comprising:a plurality of operating blocks having operation control inputs; and a control unit including: an instruction input for receiving the instructions of the predetermined set; control outputs connected to the operation control inputs; a switch unit coupled to the instruction input by first and second paths and to the control outputs for selectively connecting one of the paths to the control outputs; and an instruction interpreter coupled between the instruction input and the switch unit along the second path separate from the first path, the instruction interpreter being structured to interpret the instructions received from the instruction input and, upon receiving one of the instructions other than the control instruction, convert the instruction to a control signal that is transfered through the switch unit and control outputs to the plurality of operating blocks, and upon receiving the control instruction, cause the switch unit to transfer the operand section of the control instruction from the first path through the control outputs to the plurality of operating blocks.