Patent ID: 6788612
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A memory means for simultaneous memory operations, comprising:a) a partitioning means for subdividing a memory into a plurality of sectors containing a plurality of memory cells, b) a word line means, a source line means, a sub bit line means and a main bit line means for conditioning cells of said memory for memory operations, c) a sector decoder means for coupling said main bit lines to said sub bit lines in said sector, d) a multiple input and output means for said sector decoder to couple a plurality of sub bit lines within said sector to a plurality of said main bit lines, e) said sector decoder means drives a first set of selector pates to couple main bit lines to a first set of sub bit lines for a write operation and said selector decoder means drives a second set of selector gates to couple main bit lines to a second set of sub bit lines for a read operation to perform a first memory operation in a first sector while performing a second memory operation in a second sector.