Patent ID: 9087819
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. Semiconductor package comprising: a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface, wherein grooves are formed around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip, wherein grooves are formed such that inner surfaces formed by the grooves only comprise the dielectric layer, and each of the grooves has a width that is greater at a bottom than a top; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves, wherein the bumps are projected more upward on the center portions than on the edge portions.