Patent ID: 6237123
Filing Date: 2001-05-22
Classification: G01R,G06F,G11C

Abstract:
Apparatus for scheduling the self-testing of a plurality of electronic devices, each of said plurality of electronic devices having self-test circuitry and means for indicating when its self-test has been completed, a plurality of resource controllers controlling said plurality of electronic devices, comprising:a plurality of resource controller sets, each of said plurality of resource controller sets including at least one resource controller, wherein each said resource controller controls at least one of said electronic devices to cause said self-test circuitry thereof to test;for at least a first of said plurality of resource controller sets, a first digital token passing circuit adapted for initiating processing of each of said resource controllers in said first set in parallel;each of said resource controllers in said first set having means for receiving the indication that its at least one electronic device has completed execution of said self-test circuitry and, after receiving such notification, sending a self-test complete signal to a second digital token passing circuit; andsaid second digital token passing circuit analyzing each said self-test complete signal from each said resource controller in said first set and sending a begin self-test signal to a second set of said plurality of resource controller sets when each of said electronic devices controlled by said first set has indicated that it has completed execution of said self-test circuitry by sending self-test complete signals.