Patent ID: 6287921
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of performing threshold voltage adjustment for MOS transistors, wherein said threshold voltage adjustment is performed by means of P-type ion implantation, comprising the steps of:a. forming a first oxide layer and a layer of hard mask on a silicon substrate wherein the layer of hard mask comprises a nitride or oxynitride layer;b. forming shallow trenches and active regions by using photolithography and anisotropic etching steps;c. removing part of said layer of hard mask laterally and vertically so that part of the nitride oxynitride layer at an edge of the active region is removed wherein a part of the silicon substrate is exposed;d. performing a first ion implantation including the edge of the active region for threshold voltage adjustment by using P-type ion implantation;e. completing shallow trench isolations; andf. performing a second ion implantation, which includes said edge of the active region previously exposed to ion implantation so that said edge of the active region has a much higher dopant concentration than other portions of said active regions, for threshold voltage adjustment by using P-type ion implantation.