Patent ID: 6316964
Filing Date: 2001-11-13
Classification: H03K

Abstract:
A method for controlling an interface output circuit, said interface output circuit operating in a disabled state and an enabled state, said method comprising the steps of:utilizing a connection point between first and second transistors connected in series to each other as a first output terminal and a connection point between third and fourth transistors connected in series to each other as a second output terminal, wherein said first connection point is connected through resistors to said second connection point and said first and second transistors are connected in parallel to said third and fourth transistors;connecting a first current source to said first and third transistors;connecting a second current source to said second and fourth transistors;connecting a terminating power supply source to a node between said resistors;switching said first to fourth transistors simultaneously to ON during a disabled state of said interface output circuit, to thereby cause said first and second output terminals to be in a high impedance state; andswitching said first and fourth transistors OFF when said interface output circuit is switched to said enabled state.