Patent ID: 6202166
Filing Date: 2001-03-13
Classification: G06F,Y02D

Abstract:
A state machine with a dynamic clock gating function, comprising:a next state logic for outputting a next state;a plurality of flip-flops, of which each data input terminal is electrically coupled to the output terminal of the next state logic and each data output terminal is electrically coupled to the input terminal of the next state logic, for providing a current state;a plurality of OR gates, of which each first input terminal receives an external clock signal and each output terminal is electrically coupled to the clock input terminal of a corresponding flip-flop; anda gating clock control logic, of which the input terminal is electrically coupled to the data output terminals of the flip-flops and the output terminal is electrically coupled to the second input terminals of the OR gates, for judging whether to gate the clock signal of the flip-flops based on the current state and the next state.