Patent ID: 7929574
Filing Date: 2011-04-19
Classification: H04J

Abstract:
1. A clock distribution mechanism for circuit emulation applications, the clock distribution mechanism comprising: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks, generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks, and outputs the normalized frequency; a clock source selector that receives a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normalizer, selects the normalized frequency output from among the plurality of input clock sources, and transmits the selected normalized frequency to a node, wherein the selected normalized frequency is used throughout the clock distribution mechanism.