Patent ID: 6809575
Filing Date: 2004-10-26
Classification: G05F

Abstract:
A current-reference circuit comprising:a CMOS differential amplifier having first output node comprising a drain of a first n-channel MOS transistor and a second output node comprising a drain of a second n-channel MOS transistor; a first p-channel MOS transistor having a source coupled to a supply potential, a gate coupled to said second output node, and a drain; a first PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a first resistor and to a gate of said second n-channel MOS transistor, and a collector and a base both coupled to ground; a second PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a second resistor in series with a third resistor, and a collector and a base both coupled to ground, a gate of said first n-channel MOS transistor coupled to a common node between said second and third resistors; and a third n-channel MOS transistor having a drain coupled to said drain of said first p-channel MOS transistor, a source coupled to ground through a fourth resistor, and a gate coupled to a fixed reference potential.