Patent ID: 7364944
Filing Date: 2008-04-29
Classification: H01L

Abstract:
1. A fabrication method of a thermally enhanced semiconductor package, comprising the steps of: preparing a wafer comprising a plurality of chips each having an active surface and an opposite inactive surface, the active surface formed with a plurality of bond pads thereon; forming a conductive bump on each of the bond pads of the chips; singulating the wafer to separate apart the plurality of chips each having a plurality of the conductive bumps formed thereon; providing a heat sink module plate comprising a plurality of heat sinks, and attaching the chips to a surface of the heat sink module plate, wherein the inactive surface of at least one of the chips is mounted on each of the heat sinks, and the heat sink has a surface area larger than that of the corresponding chip; fabricating an encapsulation body for encapsulating the heat sink module plate, the chips, and the conductive bumps, and allowing a plurality of surfaces, other than that for attaching the chips, of the heat sink module plate and ends of the conductive bumps to be exposed to outside of the encapsulation body; forming a plurality of conductive traces on the encapsulation body and electrically connecting the conductive traces to the exposed ends of the conductive bumps; applying a solder mask layer over the conductive traces and forming a plurality of openings through the solder mask layer for exposing predetermined portions of the conductive traces; forming a solder ball on each of the exposed portions of the conductive traces; and cutting the encapsulation body and the heat sink module plate to separate apart the plurality of heat sinks and thereby form a plurality of semiconductor packages each having the individual heat sink.