Patent ID: 7685222
Filing Date: 2010-03-23
Classification: G06F

Abstract:
1. A method of executing a multiplication within an electronic circuit, the electronic circuit configured for performing the steps comprising: (a) creating a Y-adder power of two shift table having a multiplicand input of a desired bit width coupled to at least one shifter column and at least one column of adders, with rows of right shifters extending from the adder columns, wherein coefficients are equated to the output contribution of each said shifter or adder in proportion to the multiplicand input; (b) receiving a multiplier value of a desired bit width to which said multiplicand input values are to be multiplied by the electronic circuit; (c) locating a coefficient associated with a shift-add path in said table to successively approach the received multiplier value; (d) storing the shift and add path for said coefficient in a memory; (e) repeating execution of steps (c) and (d) until a desired level of accuracy has been obtained in approaching the received multiplier value; and (f) combining the stored shift and add paths from memory to form a multiplication engine in which said multiplicand value is multiplied by said multiplier value to generate an output product.