Patent ID: 7223645
Filing Date: 2007-05-29
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps in the following order: (a) preparing a semiconductor substrate having current input/output regions; (b) forming an insulating layer on the semiconductor substrate, (c) forming a resist laminate on the insulating layer; (d) forming an upper opening through an upper region of the resist laminate, the upper opening having a laterally broadening space in a middle portion of the resist laminate; (e) forming a lower opening through a lower region of the resist laminate, the lower opening communicating the upper opening, having a limited size along a current direction, and having generally vertical side walls; (f) etching the insulating layer exposed in the lower opening to form a gate electrode opening exposing the semiconductor substrate; (g) performing a heat treatment of the resist laminate to move the side walls of the lower opening so that at least one of opposite ends of the lower region of the resist laminate at the lower opening is retarded from a corresponding end of the insulating layer and that the lower opening of the resist laminate has a forward taper shape upwardly and monotonically increasing a size of the lower opening along the current direction; and (h) filling a gate electrode stem in the gate electrode opening and the lower opening and forming a head in the upper opening, the head having an expanded size along the current direction.