Patent ID: 9001546
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A static random access memory (SRAM) device comprising: a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells and a word line disposed thereon, each word line being connected to the plurality of memory cells disposed on its memory array layer, wherein the number of memory cells in a layer corresponds to a predetermined memory page size; a layer decoder circuit disposed on each memory array layer, each layer decoder circuit being configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer; a word line driver circuit disposed on each memory array layer, each word line driver circuit being configured to drive the word line disposed on its memory array layer; and a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple a memory cell in each memory array layer.