Patent ID: 7920438
Filing Date: 2011-04-05
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory array including a plurality of static memory cells, each of the plurality of static memory cells being supplied with a first voltage as an operating voltage; a peripheral circuit controlling the memory array and supplied with a second voltage as an operating voltage; a threshold voltage detecting circuit having a first circuit outputting a first potential that varies according to a threshold voltage of a MOS transistor, a first reference potential generator including first and second resistive elements coupled between a second potential and a third potential lower than the second potential in series and outputting a first reference potential from a connection node of the first and second resistive elements, and a first comparator receiving the first potential and the first reference potential and outputting a first signal that indicates whether the first potential is higher than the first reference potential or not; and a power circuit generating the first voltage according to the first signal, wherein the first voltage is different from the second voltage, and wherein each of the plurality of static memory cells comprises a plurality of PMOS, and wherein the first voltage is supplied to a source of the plurality of PMOS.