Patent ID: 7139348
Filing Date: 2006-11-21
Classification: H03L,H04L

Abstract:
1. A distributed clock circuit for distributed high speed data, comprising: a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked; and one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal; wherein the master DLL circuit includes a clock DLL and at least one data DLL, and wherein the slave DLL circuit includes at least one data DLL; and wherein the clock DLL includes: a clock signal input; a clock variable delay unit (VDU) having a first input coupled to the clock signal input, and a delayed clock signal output; a data VDU having an input coupled to the clock signal input; a phase detector having a first input coupled to the delayed clock signal output, and a second input coupled to an output of the data VDU; a filter/control circuit having an input coupled to an output of the phase detector, and a first output connected to a second input of the clock VDU; a lock circuit having an input coupled to a second output of the filter/control circuit, and a clock delay control signal output.