Patent ID: 6038184
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A semiconductor memory device fabricated on a semiconductor chip, comprising:a plurality of addressable memory cells for storing data bits,an addressing system for selecting accessible memory cells from said plurality of addressable memory cells,a bit line system connected to said plurality of addressable memory cells for supplying first data bits to and from the selected accessible memory cells,a sense amplifier system connected to said bit line system for amplifying said first data bits on said bit line system,a plurality of temporary data storage circuits selectively coupled to said sense amplifier system at intervals for storing second data bits which comprise some portion of said first data bits at each time said addressable memory cells are selected,an interface connectable to said plurality of temporary data storage circuits for serially propagating said first data bits between said plurality of temporary data storage circuits and a data port,a controller for sequentially connecting said plurality of temporary data storage circuits to said interface, andan internal timing generator connected to said controller for providing a starting timing of the serial data propagation of said first data bits, an end point of said serial data propagation as well as activation timings and deactivation timings to said addressing system and said sense amplifier system without any external signal and including a counter for counting clock pulses to generate output signals and a decoder producing timing signals from said output signals for providing said activation timings and said deactivation timings.