Patent ID: 8730248
Filing Date: 2014-05-20
Classification: G06F,G06T

Abstract:
1. A multi-graphics processor system comprising: a main processor; a first graphics processor, which is connected to the main processor via an input/output interface; a second graphics processor, which is connected to the first graphics processor via an external connection interface; a relay interface provided in the first graphics processor, which is used when the main processor communicates with the second graphics processor via the external connection interface; and an arbiter included in the first graphics processor that receives data from the main processor, the data including a destination address of either the first graphics processor or the second graphics processor, wherein the arbiter distributes the data received from the main processor in a time-sharing manner such that data with a destination address of the first graphics processor is allocated to be communicated between the main processor and a processor core within the first graphics processor to be processed only by the first graphics processor, and data with a destination address of the second graphics processor is allocated to be communicated between the main processor and the relay interface to be processed only by the second graphics processor, wherein the first graphics processor and second graphics processor process data in parallel, and wherein the main processor is operable to communicate with the second graphics processor via the relay interface provided in the first graphics processor, after receiving a signal indicating the timing of data communication, the signal being transmitted from the relay interface.