Patent ID: 6510510
Filing Date: 2003-01-21
Classification: G06F,Y02D

Abstract:
A computation block for performing digital signal computations, comprising:a register file for storage of operands and results of said digital signal computations; first and second computation units for executing said digital signal computations using said operands and producing said results; one or more operand buses each coupled between an operand output of said register file and an operand input of said first and second computation units; and one or more result buses each coupled to a result output of said first and second computation units, to an intermediate result input of said first and second computation units and to a result input of said register file, wherein an intermediate result of a digital signal computation may be transferred directly from the result output of one of said computation units to the intermediate result inputs of one or both of said first and second computation units for use in a subsequent computation without first transferring the intermediate result to said register file, wherein each of said computation units comprises a first latch having inputs coupled to each of said operand buses and each of said result buses, a first multiplexer having inputs coupled to said first latch for selecting a first operand from one of said operand buses or one of said result buses in response to a first control signal, a second latch having inputs coupled to each of said operand buses and each said result buses, a second multiplexer having inputs coupled to said second latch for selecting a second operand from one of said operand buses or one of said result buses in response to a second control signal, a computation circuit for receiving said first and second operands and executing said digital signal computation, and an output latch having an input coupled to said computation circuit and an output coupled to one or more of said result buses.