Patent ID: 8386230
Filing Date: 2013-02-26
Classification: G06F

Abstract:
1. A method, comprising: generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration; wherein the first configuration further comprises a logic cone configured to receive the first intermediate signal, to receive a plurality of scan inputs, and to generate a scan output based on the first intermediate signal and the plurality of scan inputs; modifying the first behavioral model to generate a second behavioral model, the second behavioral model describing the physical circuit in a second configuration; generating a testability model based on the second behavioral model, the testability model comprising a first structural representation, based on the first logic structure; determining, based on the testability model, whether the first logic structure causes a first coverage problem; and in the event the first logic structure causes a first coverage problem, modifying the testability model to include an inversion structure;