Patent ID: 6675269
Filing Date: 2004-01-06
Classification: G06F,G11C,Y02D

Abstract:
A semiconductor device comprising:a memory controller receiving commands from a CPU, and controlling a memory, wherein said memory controller has a first mode and a second mode, wherein said memory comprises a plurality of word lines, data lines, and memory cells, wherein said memory is controlled to precharge after a read access in said first mode, wherein said memory is controlled to receive a next access command without a precharge operation after a read access in said second mode, wherein said memory controller has a circuit comparing one address inputted and the address previous to said one address to control the mode for access commands corresponding to addresses inputted after said one address, wherein after a first number of successive times a different word line is selected, said memory controller changes said second mode to said first mode, and wherein said circuit controls sad first number.