Patent ID: 8188779
Filing Date: 2012-05-29
Classification: H03K

Abstract:
1. A duty control buffer circuit comprising: a first differential circuit that differentially receives input signals and generates first differential output signals comprising a non-inverting output signal and an inverting output signal, the first differential output signals making a transition responsive to a transition of the input signals, the first differential output signals having a predetermined magnitude relationship between a time of at least one of falling and rising transitions of the non-inverting output signal thereof and a time of the one of falling and rising transitions of the inverting output signal thereof; a second differential circuit that differentially receives the input signals in common with the first differential circuit and generates second differential output signals comprising a non-inverting output signal and an inverting output signal, the second differential output signals making a transition responsive to a transition of the input signals, the second differential output signals having a magnitude relationship between a time of the one of falling and rising transitions of the non-inverting output signal thereof and a time of the one of falling and rising transitions of the inverting output signal thereof, the magnitude relationship of the second differential output signals being opposite to the magnitude relationship of the first differential output signals; first and second latch circuits that respectively receive the outputs of the first and second transistors and have outputs thereof cross-connected to the outputs of the second and first transistors; third and fourth latch circuits that respectively receive the outputs of the third and fourth transistors and have outputs thereof cross-connected to the outputs of the fourth and third transistors; ninth and tenth transistors respectively connected to the first and second constant current sources, the ninth and tenth transistors forming a differential pair that differentially receives first and second control signals, the ninth and tenth transistors respectively forming the first and third current sources; a first resistor connected between a connection node of the first constant current source and the ninth transistor and a connection node of the second constant current source and the tenth transistor; eleventh and twelfth transistors respectively connected to the third and fourth constant current sources, the eleventh and twelfth transistors forming a differential pair that differentially receive the first and second control signals, the eleventh and twelfth transistors forming the second and fourth current sources; and a second resistor connected between a connection node of the third constant current source and the eleventh transistor and a connection node of the fourth constant current source and the twelfth transistor being connected, a signal obtained by combining the non-inverting output signals of the first and second differential output signals and a signal obtained by combining the inverting output signals of the first and second differential output signals being produced respectively at first and second output terminals of the duty control buffer circuit, wherein the first differential circuit comprises: wherein the second differential circuit comprises: the second differential pair including third and fourth transistors having current driving capabilities with a predetermined ratio therebetween, the second and fourth transistors having control terminals connected in common to a first input terminal of the duty control buffer circuit, the first and third transistors having control terminals connected in common to a second input terminal of the duty control buffer circuit, outputs of the second and fourth transistors being connected in common to the first output terminal, outputs of the first and third transistors being connected in common to the second output terminal, wherein: