Patent ID: 6295244
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A semiconductor memory device, comprising:n memory cell array blocks;k sense amplifiers of n groups for respectively amplifying k pairs of output data output from each of the n memory cell array blocks and for respectively outputting the amplified k pairs of output data to main data lines, in response to a sense amplifier control signal;k main buffers for, in response to a main buffer control signal, respectively resetting the k pairs of main data lines, and, when each of the pairs of data of the k pairs of main data lines achieve complementary levels, for respectively generating k pairs of data each of which has complementary levels, said k pairs of data being reset after a lapse of predetermined time;k data output buffers for respectively receiving and buffering said k pairs of data generated from said k main buffers, in response to k data output buffer control signals, each of said k data output buffer control signals being generated responsive to a respective condition of a corresponding one of said k pairs of data by which data of said corresponding one of said k pairs of data have reached complementary levels;k data output buffer control signal generating means for generating said k data output buffer control signals, each of said data output buffer control signals being collectively enabled in response to a common control signal and being independently disabled after a lapse of predetermined time from the point of time at which each of said pairs of data output from said k main buffers achieve the complementary levels; anda controller for generating said sense amplifier control signal, said main buffer control signal and said data output buffer control signals which are in pulse shape, in response to a clock signal, chip select signal and read command which are externally applied thereto.