Patent ID: 6384650
Filing Date: 2002-05-07
Classification: H03L

Abstract:
A digital phase locked loop (PLL) circuit, which provides a first loop circuit based on a stationary phase difference multiplied by a first constant multiplier and a second loop circuits based on the stationary phase difference multiplied by the first constant multiplier and a second constant multiplier, the first and second loop circuits being constructed to set an input frequency equivalent to an output frequency equivalent by a feedback operation, and in which in case that a clock source to be synchronized is lost, a clock frequency being synchronized is memorized and held, the digital PLL circuit comprising:a third loop circuit which compares said output frequency with a predetermined constant frequency and uses the compared result for the feedback operation at said first and second loop circuits, said third loop circuit, comprising: a fixed frequency oscillator which outputs a signal having the predetermined constant frequency; a calculating means for calculating a difference between said frequency of said signal outputted from said fixed frequency oscillator and said output frequency; a memorizing means for memorizing said difference calculated at said calculating means; a comparing means for comparing a difference between said frequency of said signal outputted from said fixed frequency oscillator and a current output frequency with said difference memorized in said memorizing means; and a voltage controlled oscillator (VCO) which outputs a signal having a frequency based on the compared result at said comparing means, wherein: control is performed so that said difference between said frequency of said signal outputted from said fixed frequency oscillator and said current output frequency, and said difference memorized in said memorizing means are made to be equal.