Patent ID: 7000210
Filing Date: 2006-02-14
Classification: G06F

Abstract:
1. A computer-implemented method of mapping a plurality of configurable logic blocks (CLBs) in a programmable logic device (PLD), the method comprising: initializing a performance constraint; generating an initial mapping of the CLBs in the PLD; and applying a simulated annealing algorithm to the initial mapping to generate a final mapping of the CLBs in the PLD, wherein the simulated annealing algorithm comprising: generating a first modified mapping of the CLBs in the PLD; characterizing circuit performance of the first modified mapping; comparing the circuit performance of the first modified mapping to the performance constraint to determine whether to accept of reject the first modified mapping; modifying the performance constraint; generating a second modified mapping of the CLBs in the PLD; characterizing circuit performance of the second modified mapping; and comparing the circuit performance of the second modified mapping to the modified performance constraint to determine whether to accept of reject the second modified mapping.