Patent ID: 8514232
Filing Date: 2013-08-20
Classification: G06F,G06T

Abstract:
1. A circuit arrangement, comprising: a shared memory within which is stored a copy of a shared state used in connection with rendering an image; a plurality of processing cores coupled to one another in a network on chip configuration by a packet-based on-chip network, the plurality of processing cores defining a plurality of parallel threads of execution, and each processing core including a cache memory within which is stored a locally cached copy of the shared state; and a multithreaded rendering software pipeline hosted by at least a subset of the plurality of processing cores, the multithreaded rendering software pipeline including a plurality of stages configured to perform work in connection with rendering an image in a buffer; wherein the multithreaded rendering software pipeline is further configured to propagate changes to the shared state to the plurality of processing cores by streaming change packets to stages in the multithreaded rendering software pipeline to cause each processing core to update its locally cached copy of the shared state without attempting to access the copy of the shared state in the shared memory, wherein the multithreaded rendering software pipeline is further configured to, in response to a first change made to a first locally cached copy of the shared state associated with a first processing core, propagate the first change to second and third processing cores to cause the second and third processing cores to respectively modify state data in second and third locally cached copies of the shared state respectively associated with the second and third processing cores to incorporate the first change into the second and third locally cached copies of the shared state such that an accesses to the second and third locally cached copies of the shared state that occur after the first change is propagated access the modified state data.