Patent ID: 7664930
Filing Date: 2010-02-16
Classification: G06F

Abstract:
1. A computer-implemented method comprising: identifying a type in a data processing instruction by a main processor, the type indicating one of coprocessors attached to the main processor for executing a coprocessor instruction embedded in the data processing instruction; executing the coprocessor instruction conditionally when a conditional flag of the main processor matches a condition associated with the coprocessor instruction; decoding the coprocessor instruction by the coprocessor, the coprocessor instruction that specifies executing by the coprocessor the add-subtract operation when the operation type includes the add-subtract operation to generate a first result by adding the first real component to the second imaginary component and to generate a second result by subtracting the second real component from the first imaginary component; saturating the first and second results when saturating operations are enabled; and storing the first result and the second result in a first destination register.