Patent ID: 6944753
Filing Date: 2005-09-13
Classification: G06F

Abstract:
1. A method for use in a computer system having an integer execution unit (FXU) having an Instruction Decode and Dispatch Unit (I-Unit) of a central processor (CP) of the computer system and in which said integer execution unit contains an arithmetic and logical unit (ALU) which is capable of performing arithmetic functions including binary addition, subtraction, and logical operations such as logical and, logical or, and logical exclusive or, wherein said logical operations for operands which feed the ALU are bit maskable to select which bits of the operands participate in the logical operation, comprising the steps of: allowing a partial instruction to be executing during the instruction dispatch cycle of the computer system by providing said integer execution unit (FXU) with a predetermination cycle pipeline stage created to accommodate a timing critical function used for excecution of an instruction, and overlapping said predetermination cycle pipeline stage (E-1 stage) with a dispatch cycle of the Instruction Decode and Dispatch Unit (I-Unit) of said integer execution unit (FXU) of a central processor (CP) of the computer system before an instruction is dispatched.