Patent ID: 8384448
Filing Date: 2013-02-26
Classification: H03L

Abstract:
1. A DLL (Delay Locked Loop) circuit comprising: a duty ratio correction unit configured to correct duty ratios of first and second delay clocks to generate first and second correction clocks; a duty ratio detection unit configured to detect duty ratios of the first and second correction clocks, thereby generating first and second detection signals; a voltage comparison unit configured to compare levels of the first and second detection signals, thereby generating a first fine control signal; an operation mode setting unit configured to generate a locking completion signal and a second fine control signal; and a switching unit configured to transmit one of the first fine control signal and the second fine control signal to a delay control unit according to whether or not the locking completion signal is enabled, wherein the first clock is generated from a first delay line which receives a first reference clock and is controlled by the first fine control signal to delay the first reference clock, and the second clock is generated from a second delay line which receives a second reference clock and is controlled by output of the switching unit to delay the second reference clock.