Patent ID: 7609538
Filing Date: 2009-10-27
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit comprising: a plurality of bit line pairs, wherein each bit line pair includes a first bit line and a second bit line, wherein the first bit line and the second bit line within each bit line pair are aligned adjacent to each other; a plurality of word lines, wherein each word line is associated with the bit lines such that an array is formed by the bit lines and the associated word lines; a first interconnect layer and a second interconnect layer, wherein each of the bit lines is associated with both the first and second interconnect layers; a plurality of memory cells, wherein each of the plurality of memory cells is associated with every other bit line along each word line; and a plurality of amplifiers, wherein each of the plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.