Patent ID: 6256768
Filing Date: 2001-07-03
Classification: G06F

Abstract:
A method for processing a logic design defining an integrated circuit (IC) as a multiple level hierarchy of components formed by a plurality of cells, the method comprising the steps of:a. processing said logic design to generate one of either a flat or a loose IC layout wherein cells of components of the IC are assigned to separate positions within an IC substrate;b. analyzing said IC layout and the logic design to identify positions within said substrate to which cells forming each component of said hierarchy were assigned at step a; andc. determining from the positions identified at step b, a shape and position of each of a plurality of areas of said layout, wherein each component of said multiple-level hierarchy corresponds to at least one area of said plurality of areas, and wherein each area of said plurality of areas has a perimeter sized and shaped to encompass those cells which are both included in the area's corresponding component and which are contiguous to one another within said layout.