Patent ID: 8143125
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method of forming a trench-gate FET structure, the method comprising: forming a plurality of trenches extending into a semiconductor region; forming a gate dielectric layer extending continuously along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches; forming a gate electrode inside each trench; forming well regions of a second conductivity type ill the semiconductor region; forming source regions of the first conductivity type in upper portions of the well regions; after forming the source regions, forming a concave-shaped salicide layer comprising at least one of cobalt or nickel over the gate electrode inside each trench abutting portions of the gate dielectric layer, wherein the gate dielectric layer prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between the adjacent trenches; forming a dielectric layer over the concave-shaped salicide layer in each trench; and forming an interconnect layer over the dielectric layer, the dielectric layer isolating the interconnect layer from the concave-shaped salicide layer and portions of the gate dielectric layer isolating the interconnect layer from the mesa surfaces between the adjacent trenches.