Patent ID: 6205521
Filing Date: 2001-03-20
Classification: G06F,Y02D

Abstract:
A cache system comprising:a cache memory, the cache memory arranged in blocks of cache lines, with each such block including a plurality of cache lines;wherein the cache memory additionally comprises:a plurality of valid bits, with a valid bit associated with each cache line, the valid bit indicating whether the data in the associated cache line is active;a plurality of dirty bits, with a dirty bit associated with each of the cache lines, the dirty bit indicating whether the data in the associated cache line has been rewritten;a flush inclusion map, the flush inclusion map having a corresponding block flush inclusion bit for each block of cache lines, andwherein the block flush inclusion bit for a given block is set whenever any of the valid bits in the block is set; anda cache flush controller, connected to control a cache flush operation, the cache flush controller reading the state of the block flush inclusion bits, and executing a cache flush operation only for blocks in which the associated block flush inclusion bit is set, and while executing the cache flush operation, the cache flush controller reading the state of the dirty bits in the associated block to determine individual cache lines to be flushed, such that the only dirty bits read during the cache flush operation are those dirty bits associated with the cache lines in those blocks for which the corresponding block flush inclusion bit is set.