Patent ID: 6552625
Filing Date: 2003-04-22
Classification: G05B,H02P

Abstract:
A pulse width modulation generator for a processor comprising:fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on at least two of the plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals; and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.