Patent ID: 6064100
Filing Date: 2000-05-16
Classification: H01L,Y10S

Abstract:
A ROM product having a silicon controlled rectifier structure, comprising:a substrate having a planar surface and a first insulating layer on the planar surface;a plurality of bit lines on the surface of the first insulating layer and extending in a first direction, and each of the bit lines including a heavily doped first type impurity layer, a lightly doped second type impurity layer, and a lightly doped first type impurity layer, which are sequentially stacked on the first insulating layer;a second insulating layer on the first insulating layer between the bit lines and having a height equal to that of the bit lines;a plurality of first contact windows in the bit lines to expose the corresponding heavily doped first type impurity layer;a plurality of spacers on sidewalls of the first contact windows;a plurality of first type diffusion regions in the corresponding heavily doped first type impurity layer about within the first contact window, and in the corresponding lightly doped first type impurity layer at a desired location;a first conducting layer filling each of the first contact windows;a plurality of second type diffusion regions in the corresponding lightly doped first type impurity layer;a third insulating layer over the corresponding lightly doped first type impurity layer, the second insulating layer, and the corresponding first conducting layer;a plurality of second contact windows in the third insulating layer to expose the corresponding first conducting layer, the first type diffusion regions and selected ones of the second type diffusion regions;a plurality of triggering word line electrodes located in the second contact windows above the first type diffusion regions and covering part of the third insulating layer;a common electrode filling the second contact windows above the corresponding first conducting layer and covering part of the third insulating layer; anda plurality of bit line electrodes located above the surface of the third insulating layer, and filling the second contact windows above the exposed second type diffusion regions, the bit line electrodes being generally parallel to and separate from each other and extending in a second direction, the first direction and the second direction crossing each other at an angle, the bit lines and the bit line electrodes crossing each other to form a plurality of memory units, wherein the selected ones of the second type diffusion regions, having a second contact window, form ON state memory units, and others of the second type diffusion regions, without a second contact window, form OFF state memory units.