Patent ID: 7165254
Filing Date: 2007-01-16
Classification: G06F

Abstract:
1. A processor system made to carry out a plurality of threads, each having one or more instructions, in parallel through the use of one or more arithmetic units, comprising: a multithread control unit to selectively switch among said threads to be executed in said one or more arithmetic units; a loop predicting unit to predict a loop of an instruction string on the basis of a processing history of a branch instruction in said thread; and a loop detecting unit to detect, when said loop predicting unit predicts said loop, a fixed-point-mode load instruction for writing data in a fixed-point register in said instruction string, and to detect an occurrence of said loop by detecting a spin-loop when the number of times of continuous occurrence of the same fixed-point-mode load instruction, which is in a continuing condition, exceeds a predetermined value, when said loop detecting unit detects said loop, said multithread control unit switching from said thread, which is in execution in said arithmetic unit, to a different thread.