Patent ID: 8136066
Filing Date: 2012-03-13
Classification: G06F,Y02P

Abstract:
1. An apparatus for performing critical area analysis on an integrated circuit design having redundant and non-redundant elements, the apparatus comprising: means for generating a graphical data symbol representation of the integrated circuit design; means for identifying any redundant elements of the integrated circuit in the graphical data symbol representation with unique identifiers; and means for analyzing the graphical data symbol representation for undesired open-causing defects in wires and/or vias for the non-redundant elements, wherein the apparatus treats redundant and non-redundant elements differently during yield estimations in performing the critical area analysis, and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and wherein the generating comprises generating graphical design data (GDD) shapes for performing the critical area analysis for short defects and opens, wherein the critical area analysis for short defects uses the GDD and performs the critical area analysis for both the redundant and the non-redundant elements of the integrated circuit design, and wherein the critical area analysis for the opens uses the GDD and performs the critical area analysis for only the non-redundant elements of the integrated circuit design.