Patent ID: 8008698
Filing Date: 2011-08-30
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate including a plurality of active regions, wherein each of the active regions extends in a first direction parallel with respect to a surface of the semiconductor substrate; a plurality of pillars extending from respective active regions in a direction perpendicular with respect to the surface of the semiconductor substrate with each of the pillars including a respective channel region on a sidewall thereof; a plurality of impurity regions formed in respective active regions, wherein each of the impurity regions is disposed directly between a pair of the pillars and in a straight line with the pair of the pillars in the first direction; a plurality of gate insulating layers surrounding respective sidewalls of the plurality of pillars; a plurality of word lines extending in a second direction parallel with respect to the surface of the semiconductor substrate wherein the first and second directions are different and wherein respective ones of the word lines surround sidewalls of respective ones of the plurality of pillars so that the gate insulating layers are between the word lines and the pillars; a plurality of contact plugs electrically connected to respective ones of the impurity regions and spaced apart from the word lines; and a plurality of bit lines electrically connected to respective ones of the impurity regions through respective ones of the contact plugs wherein the plurality of bit lines extend in the first direction.