Patent ID: 8484594
Filing Date: 2013-07-09
Classification: G06F

Abstract:
1. A method for routing-based pin placement, the method being implemented by a non-transitory computing device including a processing unit and memory having executable instructions stored thereon, which, when executed cause the processing unit to execute the method, the method comprising: generating a logical description of a macro of a partitioned circuit, the logical description being received at a routing tool coupled to the computing device and including connectivity information of the macro and a physical outline of the macro; instructing the routing tool to generate an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information such that the abstracted shape conforms to dimensions of the macro; freeing the routing tool to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net; and instructing the routing tool to identify a location where the routed net crosses the physical outline of the macro as a chosen location for the pin.