Patent ID: 8065651
Filing Date: 2011-11-22
Classification: G01R

Abstract:
1. An method for testing a circuit, the method comprising: configuring, by computer, a first design-for-test (DFT) core to perform a test on a first module of the circuit, by: configuring a first series of flip-flops to receive an input bit stream associated with the compressed test vector, wherein an output of a first flip-flop in the first series of flip-flops is coupled to a first test input in the set of test inputs; configuring a second series of flip-flops to generate a first output bit stream associated with the compressed response vector, wherein a first response output in the set of response outputs is coupled to an input of a first flip flop in the second series of flip flops; and configuring a first set of multiplexers to interface the outputs of the first series of flip-flops with the set of test inputs of the first DFT core, wherein the first set of multiplexers are used to input the compressed test vector into the test inputs of the first DFT core in a forward direction or in a backward direction.