Patent ID: 7326998
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. An integrated circuit comprising at least one I/O logic circuit and at least one electrostatic discharge (ESD) protection device formed in a substrate having a first conductivity type, said logic circuit and said ESD protection device each comprising: a gate on the substrate and insulated therefrom, first and second heavily doped regions having a second conductivity type located in the substrate on opposite sides of the gate and forming source and drain regions; and first and second lightly doped drain (LDD) regions having a second conductivity type located in the substrate on opposite sides of the gate and extending from one of the heavily doped regions toward the other heavily doped region; wherein said ESD protection circuit further comprises a region of first conductivity type located under a portion of the LDD regions of the ESD protection device but not under any portion of the first and second LDD regions of the I/O logic circuit, said region of first conductivity type forming a P-N junction with an adjacent source/drain region under no more than approximately 50% of the width of the LDD regions.