Patent ID: 6199177
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A semiconductor memory comprising:a primary array;a first set of non-volatile elements for storing at least a portion of an address of a defective cell of the primary array;a redundant array having a redundant row;data path circuitry coupled to the primary and redundant arrays for writing data thereto and reading data therefrom;a second set of non-volatile elements for storing a block repair configuration;routing circuitry coupled to the second set of non-volatile elements to be configured by the block repair configuration to output a selected ratio of received row address bits to received column address bits; andcomparison circuitry coupled to the first set of non-volatile elements, the redundant array, the data path circuitry, and the routing circuitry for comparing the row and column address bits output by the routing circuitry with the stored portion of the defective cell address and, when a match occurs, for implementing a block repair of the defective cell by activating the redundant row in the redundant array and directing the data path circuitry to write data to or read data from the activated redundant row instead of the primary array.