Patent ID: 7032190
Filing Date: 2006-04-18
Classification: G06F,H01L

Abstract:
1. A representation of a macro for an integrated circuit layout comprising: a plurality of diffusion regions; a metal layer connected to said diffusion regions; and at least one interconnection layer above said metal layer, wherein (i) said diffusion regions and said metal layer form a plurality of sub-circuit cells of a first module, (ii) said at least one interconnection layer connects at least two of said sub-circuit cells in accordance with said macro to complete said first module having a predefined functionality, and (iii) said sub-circuit cells include at least one reusable circuit cell configured with a plurality of signal terminals such that when said predefined functionality of said module is not used in a custom design, said reusable circuit cell is connected to at least one second module through said terminals by said at least one interconnection layer in said custom design.