Patent ID: 6657255
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A trench DMOS transistor device comprising:a substrate of a first conductivity type, said substrate acting as a common drain region for said device; an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate; a trench extending into said epitaxial layer from an upper surface of said epitaxial layer; an insulating layer lining at least a portion of said trench; a conductive region within said trench adjacent said insulating layer; a body region of a second conductivity type provided within an upper portion of said epiraxial layer and adjacent said trench; a source region of said first conductivity type within an upper portion of said body region and adjacent said trench; a low resistivity deep region extending into said device from an upper surface of said epitaxial layer, said low resistivity deep region acting to provide electrical contact with said substrate; and a metallic drain contact adjacent an upper surface of said deep region, a metallic source contact adjacent an upper surface of said source region, and a metallic gate contact adjacent an upper surface of said conductive region in a termination region remote from said source region.