Patent ID: 7420840
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: an N-type insulated-gate field-effect transistor including a gate electrode that is provided on a P-well in a semiconductor substrate, a source and a drain that are provided in the P-well and spaced apart from each other such that the gate electrode is interposed between the source and the drain, and a first insulating layer that is provided to extend from over the source and the drain to over the gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor; and a P-type insulated-gate field-effect transistor including a gate electrode that is provided on an N-well in the semiconductor substrate, a source and a drain that are provided in the N-well and spaced apart from each other such that the gate electrode is interposed between the source and the drain, and a second insulating layer that is provided to extend from over the source and the drain to over the gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.