Patent ID: 7939369
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A method of making 3D integrated circuits, comprising the steps of: obtaining a first semiconductor structure comprising a first semiconductor wafer, a front end of the line (FEOL) wiring on the first semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer; obtaining a second semiconductor structure comprising a second semiconductor wafer, a front end of the line (FEOL) wiring on the second semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer; aligning the first semiconductor structure with the second semiconductor structure such that the metallic layers of the first and second semiconductor structures face each other; and contacting and bonding the metallic layers of the first and second semiconductor structures to each other, wherein the bonded metallic layers form an electrically isolated layer.