Patent ID: 7663908
Filing Date: 2010-02-16
Classification: G11C

Abstract:
1. A DRAM circuit comprising: at least one memory cell comprising a capacitor coupled to a transistor; and at least one sense amplifier comprising a pre-charge circuit and a back-to-back inverter, the back-to-back inverter having at least one PMOS transistor and at least one NMOS transistor, wherein a source of the at least one NMOS transistor is coupled to a first voltage source set at ground and a source of the at least one PMOS transistor is coupled to first and second MOS transistors, the first MOS transistor configured to connect the source of the PMOS transistor to a second voltage source having a voltage that is a common supply voltage of the DRAM circuit and is higher than ground, the second MOS transistor configured to connect the source of the PMOS transistor to a third voltage source set at a higher voltage than the voltage of the second voltage source, wherein the first and second MOS transistors are configured to maintain the transistors of the back-to-back inverter in an off state during normal operation of the DRAM circuit by decoupling the source of the PMOS transistor from the second and third voltage sources.