Patent ID: 6184735
Filing Date: 2001-02-06
Classification: H03K

Abstract:
A variable delay circuit comprising:a variable delay part having n (.gtoreq.2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through said delay element, and an OR gate for outputting an output of the selected delay element or said input signal; andcontrol means for selecting at least one of said plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of said delay elements,wherein assuming that a variable width of a delay time is Span, a resolution being Res, and absolute and relative errors being da and dr, respectively, then, a designed delay time value D.sub.k of the delay element of a number k (1.ltoreq.k.ltoreq.n) delay part meets the following conditions:D.sub.1 =Span/(1-da)/2D.sub.2 =(Span/(1-da)/2).times.(1+dr)/2when k.gtoreq.3, ##EQU10## D.sub.n.times.(1+da).times.(1+dr)<Res.