Patent ID: 7830205
Filing Date: 2010-11-09
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated apparatus comprising: a first fuse block including a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged, wherein the second plurality of fuses comprises fewer fuses than the first plurality of fuses; and a second fuse block including a second up fuse block where a third plurality of fuses are arranged, wherein the third plurality of fuses comprises the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, wherein the fourth plurality of fuses comprises the same number of fuses as the first plurality of fuses, wherein the first up fuse block is opposite to the second up fuse block and the first down fuse block is opposite to the second down fuse block.