Patent ID: 7192847
Filing Date: 2007-03-20
Classification: H01L

Abstract:
1. A method of forming a wafer level stack package, comprising: providing a first wafer having a first surface and opposing second surface and having a plurality of base chips thereon; providing a second substrate, the second substrate having a first surface and opposing second surface and a plurality of chips wherein the chips of the second substrate is matched with respect to the position and size of the base chips of the first wafer; selectively binding a portion of the first surface of the first wafer to a portion of the first surface of the second substrate by using a plurality of adhesives to form, a selectively adhered first wafer wherein a distance between the first surface of the first wafer and the first surface of the second substrate is equal to a thickness of the adhesives; forming a plurality of independent chip sets, wherein each of the independent chip sets comprises the base chip and the corresponding chip of the second substrate, an order of steps of forming the independent chip sets comprise: a first cutting at the second surface of the first wafer of the selectively adhered first wafer, wherein a depth of the first cutting is greater than a thickness of the first wafer but smaller than the total thickness of the first wafer and the adhesive; and a second cutting at the second surface of the second substrate of the selectively adhered first wafer to form the independent chip sets, wherein a depth of the second cutting is greater than the thickness of the second substrate but smaller than the total thickness of the second substrate and the adhesive; and packaging the independent chip sets.