Patent ID: 6828669
Filing Date: 2004-12-07
Classification: H01L,H05K,Y02P,Y10S,Y10T

Abstract:
A multilayer interconnection substrate comprising:an uppermost interconnection layer having a plurality of terminal pads formed at positions corresponding to a plurality of external connection terminals provided on a semiconductor element which is to be mounted on said multilayer interconnection substrate; a metal column formed on each of said terminal pads by metal-plating, and having a top surface; a resin film covering a side surface of said metal column, and having a top surface; and an insulating layer formed on said uppermost interconnection layer of the same material as the resin film so that a gap is formed between the insulating layer and an outer peripheral surface of said resin film, wherein an upper end surface of each metal column is at the same height as an upper surface of the insulating layer, the top surface of the metal column and the top surface of the resin film covering the side surface of the metal column are formed at the same level of height; and the top surface of the metal column is surrounded by and exposed on the resin film so that the top surface of the resin film metal column forms a pad for connection with a semi-conductor element.