Patent ID: 6751765
Filing Date: 2004-06-15
Classification: G01R

Abstract:
A method for LBIST testing an integrated circuit comprising:generating a plurality of multi-bit test patterns; dividing each of said multi-bit test patterns by a plurality of test pattern partitions such that each of said multi-bit test patterns includes a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than said first number; applying said first number of bits to said integrated circuit and generating a first signature; comparing said first signature to a first reference signature to detect a failure in said integrated circuit; applying said second number of bits to said integrated circuit and generating a second signature; comparing said second signature to a second reference signature to detect a failure in said integrated circuit; generating a unique identifier upon the detection of a failure in said integrated circuit; storing said unique identifier along with a corresponding failure signature; and comparing said failure signature to a reference failure signature to detect failures having a common source.