Patent ID: 6906577
Filing Date: 2005-06-14
Classification: H02M

Abstract:
1. A boosting circuit, comprising: a first capacitor connected between a first node and a second node; a second capacitor connected between a third node and a fourth node; a third capacitor connected between a first boosted voltage output node and a third power source; a fourth capacitor connected between a second boosted voltage output node and the third power source; a first switch which selectively connects or disconnects a fourth power source and the first node in response to a logic state of a first control signal; a second switch which selectively connects or disconnects the fourth power source and the third node in response to a logic state of a second control signal; a third switch which selectively connects or disconnects the third power source and the third node in response to a logic state of a third control signal; a fourth switch which selectively connects or disconnects the first node and the first boosted voltage output node in response to a logic state of a fourth control signal; a fifth switch which selectively connects or disconnects the first node and a first power source in response to a logic state of a fifth control signal; a sixth switch which selectively connects or disconnects the first node and the third node in response to a logic state of a sixth control signal; a seventh switch which selectively connects or disconnects the third node and the first boosted voltage output node in response to a logic state of a seventh control signal; an eighth switch which selectively connects or disconnects the second node and the first power source in response to a logic state of an eighth control signal; a ninth switch which selectively connects or disconnects the second node and the third power source in response to a logic state of a ninth control signal; a tenth switch which selectively connects or disconnects the fourth node and the first power source in response to a logic state of a tenth control signal; an eleventh switch which selectively connects or disconnects the fourth node and the third power source in response to a logic state of an eleventh control signal; a twelfth switch which selectively connects or disconnects the fourth node and a second power source in response to a logic state of a twelfth control signal; a thirteenth switch which selectively connects or disconnects the fourth node and the second boosted voltage output node in response to a logic state of a thirteenth control signal; and a fourteenth switch which selectively connects or disconnects the second node and the second boosted voltage output node in response to a logic state of a fourteenth control signal.