Patent ID: 7326595
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A method of redesigning a semiconductor integrated circuit, which includes a first functional block, a second functional block, a metal interconnection layer, and a signal line disposed in the metal interconnection layer for transmitting a signal from the first functional block to the second functional block and which is fabricated with the aid of a predetermined mask defining the metal interconnection layer, to invert the signal carried on the signal line, said method comprising: providing a p-channel metal-oxide-semiconductor (PMOS) circuit disposed between the first functional block and the second functional block, the PMOS circuit having a source terminal, a gate terminal, and a drain terminal, the drain terminal extending to said metal interconnection layer at a point separated by a first space from said signal line, and the gate terminal also extending to said metal interconnection layer; providing an n-channel metal-oxide-semiconductor (NMOS) circuit disposed between the first functional block and the second functional block, the NMOS circuit having a source terminal, a gate terminal, and a drain terminal, the drain terminal extending to said metal interconnection layer at a point separated by a second space from said signal line, and the gate terminal also extending to said metal interconnection layer; modifying the predetermined mask so as to cause an intermediate part of the signal line to be removed, thereby dividing the signal line into a first part receiving the signal from the first functional block and a second part transmitting the signal to the second functional block; and modifying the mask so as to cause the drain terminals of the PMOS circuit and the NMOS circuit to be connected to the second part of the signal line.