Patent ID: 8415189
Filing Date: 2013-04-09
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising: providing an integrated circuit substrate including a pixel region and a logic region; etching a plurality of spaced apart isolation trenches in the integrated circuit substrate of the pixel region, the trenches including trench walls; forming a sacrificial layer including an impurity therein on at least some of the trench walls; diffusing at least some of the impurity from the sacrificial layer into the trench walls to form an impurity layer in the substrate adjacent the trench walls; removing at least some of the sacrificial layer; and etching the integrated circuit substrate of the logic region to form a plurality of logic isolation trenches, the logic isolation trenches including logic trench walls; wherein at least some of the trench walls in the logic region are free of the impurity layer.