Patent ID: 6395597
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A method of forming a memory cell, comprising the steps of:providing a semiconductor substrates; forming a vertical transistor over the substrate, wherein the vertical transistor has first, second, and third conductive regions, and wherein said vertical transistor is formed by defining a first set of trenches in said first, second, and third conductive regions and said semiconductor substrate, and defining a second set of trenches in said first, second, and third conductive regions and said semiconductor substrate which is orthogonal to said first set of trenches; providing a trench capacitor in one of said trenches to one side of the vertical transistor and in connection with the first conductive region of the vertical transistor; forming a word line gating the second conductive region of the vertical transistor; and forming a bit line in connection with the third conductive region of the vertical transistor.