Patent ID: 8401137
Filing Date: 2013-03-19
Classification: G01R,H04L

Abstract:
1. Jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, comprising: a clock recovery circuit configured to recover a recovered clock signal from said digital test signal; a synchronisation circuit configured to generate a synchronised system clock signal from said recovered clock signal; a sinusoid generator configured to generate a sinusoid signal from said synchronised system clock signal; and a sampling analog to digital converter configured to sample said sinusoid signal by said recovered clock signal to provide sinusoid samples, further comprising: a numerically controlled oscillator configured to produce sine values and cosine values in response to receiving said synchronised system clock signal; a first multiplier configured to produce a first product of said sinusoid samples and said sine values; a second multiplier configured to produce a second product of said sinusoid samples and said cosine values; and a co-ordinate rotation device configured to receive said first product via a first low pass filter and to receive said second product via a second low pass filter, and to produce a phase signal that is indicative of jitter phase.