Patent ID: 7639547
Filing Date: 2009-12-29
Classification: G11C

Abstract:
1. A semiconductor memory device including a memory cell array, the semiconductor memory device comprising: a reference voltage generating unit configured to output a reference voltage in response to an external voltage; an internal reference voltage generating unit configured to convert the reference voltage into a plurality of internal reference voltages, and to output the plurality of internal reference voltages, wherein a level of each of the plurality of internal reference voltages is separately dependent on a test Mode Register Set (TEST_MRS) signal; and an internal supply voltage generating unit configured to convert the plurality of internal reference voltages into a plurality of internal supply voltages, and to output the plurality of internal supply voltages, wherein a first internal reference voltage of the plurality of internal reference voltages is used to generate a first internal supply voltage of the plurality of internal supply voltages, and a second internal reference voltage of the plurality of internal reference voltages is used to generate a second internal supply voltage of the plurality of internal supply voltages.