Patent ID: 6121086
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate on which there are provided a plurality of memory cells each comprising a memory cell selection transistor and an information storage capacity element connected thereto in series, comprising the steps of:(a) forming a first region having an isolated rectangular plan shape on the semiconductor substrate;(b) forming a word line extending in a direction crossing the first region, on the semiconductor substrate;(c) forming a pair of semiconductor regions for a source and drain of the memory cell selection transistor, in the first region, with a channel region directly under the word line inserted;(d) forming a first interlayer insulating film for covering the memory cell selection transistor formed through the steps of (a) to (c);(e) forming a wiring groove for a bit line and a contact hole for a bit line being a part of the wiring groove for the bit line, extending in a direction two-dimensionally crossing the extending direction of the wiring groove for the bit line, integrally connected to the wiring groove for the bit line in a region two-dimensionally overlapping one of the semiconductor regions of the memory cell selection transistor and contacting to one of the semiconductor regions of the memory cell selection transistor;(f) burying a conductive member into the wiring groove for the bit line and the contact hole for the bit line, thereby to form the bit line constructed by integrally forming a wiring portion in the wiring groove for the bit line and a contact portion in the contact hole for the bit line; and(g) forming the information storage capacity element electrically connected to the other semiconductor region of the memory cell selection transistor above the bit line.