Patent ID: 6145106
Filing Date: 2000-11-07
Classification: G01R

Abstract:
A method for fast static compacting a test set for sequential circuits with finite output states by removing subsequences of test vectors from a vector test set comprising(a) relaxing the output states of said sequential circuits;(b) identifying, in response to said step of relaxing a candidate subsequence of test vectors from said vector test set for removal;(c) temporarily removing said candidate identified subsequence of test vectors from said vector test set;(d) performing fault simulation on remaining test vectors from said vector test set;(e) examining, in response to said step of performing fault simulation results against a set of removal criteria;(f) permanently removing, in response to said step of examining said temporarily removed candidate subsequence if said set of removal criteria is met;(g) replacing, in response to said step of examining said temporarily removed candidate subsequence if said set of removal criteria is not met; and(h) repeating steps (a) through (g) until all candidate subsequences of test vectors have been identified.