Patent ID: 7716611
Filing Date: 2010-05-11
Classification: G06F

Abstract:
1. A method of reducing a circuit listing, comprising: analyzing with a logic injection computing unit at least a portion of a circuit listing stored in a computer readable memory to identify occurrences of a predefined structure, the predefined structure made up of a plurality of circuit components; for each identified occurrence of the predefined structure, creating with the logic injection computing unit an injection data object corresponding to the plurality of components, and substituting the injection data object into the at least a portion of the circuit listing for the plurality of components; and comparing the portion of the circuit listing with a corresponding second circuit listing, where one of the circuit listing and second circuit listing is an original schematic for the plurality of circuit components, and the other of the circuit listing and the second circuit listing is a layout design based on the original schematic, wherein each injection data object includes at least one repeat information data object containing information common to multiple occurrences of the predefined structure, and a specific information data object containing information specific to the corresponding occurrence of the predefined structure.