Patent ID: 7064051
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method comprising: forming gate line structures extending in one direction on a semiconductor substrate having non-straight type active regions; covering the gate line structures with an interlayer insulating layer; forming a photo-resist layer on the interlayer insulating layer; exposing and developing the photo-resist layer with a photo-mask having bar type patterns to form a photo-resist pattern, the bar type patterns extending at right angles to the gate line structures, the length of the bar type patterns from 3 times the pitch of the gate line structures to 4 times the pitch of the gate line structures; etching the interlayer insulating layer using the photo-resist pattern as an etching mask to form contact holes exposing source/drain regions of the non-straight type active regions; and filling the contact holes with a conductive material to form contact pads.