Patent ID: 7288724
Filing Date: 2007-10-30
Classification: H01L,H05K,Y10T

Abstract:
1. A multilayer wiring substrate in which a first wiring substrate and a second wiring substrate electrically connected to said first wiring substrate are stacked on each other, wherein said first wiring substrate is a double-side copper-clad stack; said second wiring substrate is partially stacked exclusively over a predetermined region of said first wiring substrate; further including: an adhesive layer for adhering said first wiring substrate and said second wiring substrate, between said first wiring substrate and said second wiring substrate comprised of an insulating resin with one or more conducting inter-layer connections formed therein, and wherein a surface on said first wiring substrate on which said second wiring substrate is stacked is leveled by depositing a layer of an insulating material in regions in which a conductor pattern is not formed in order to provide for a substantially flat build-up surface for said second wiring substrate: and further wherein said second wiring substrate is comprised of one or more layers of photosensitive resin material, with conductor patterns formed therein, and wherein a lower surface of said second substrate contains a plurality of conductor lands for interfacing with a wiring of said first substrate, and an upper surface of said second substrate contains a plurality of conductor lands formed at a higher pitch than those formed on said lower surface.