Patent ID: 6707704
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory device comprising at least three memory cell blocks arranged in a word line direction, each of the at least three memory cell blocks comprising a plurality of memory cells arranged in a bit line direction, each of the plurality of memory cells comprising a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor,wherein each of the at least three memory cell blocks comprises: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line, the read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells, and the sub-bit lines of two memory cell blocks among the at least three memory cell blocks are connected to each other via a sub-bit line coupling switch.