Patent ID: 7768316
Filing Date: 2010-08-03
Classification: G11C

Abstract:
1. A decoder circuit that decodes an (m+n)-bit address signal that includes an m-bit address signal portion and an n-bit address signal portion, the decoder circuit comprising: a first decoder section that decodes the m-bit address signal portion; and a second decoder section that decodes the n-bit address signal portion, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion, an output enable signal that has a pulse width shorter than a logical time length of the (m+n)-bit address signal being input to the second AND operation circuit section, and the output enable signal being input to the fourth AND operation circuit section.