Patent ID: 6646920
Filing Date: 2003-11-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines; a plurality of bit lines; a memory cell array including a plurality of memory cells, each formed of a MIS transistor, disposed at intersections of said word lines and said bit lines, threshold voltages of said MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof, and the floating gates of said MIS transistors being simultaneously discharged to collectively erase said memory cells; a first row decoder for applying a normal voltage to a selected word line to select memory cells connected to said selected word line, when reading data; and a second row decoder for applying a predetermined source voltage to sources of the memory cells connected to said selected word line, and applying an unselected state establishing voltage to the sources of memory cells, including those overerased by said collective erasing, connected to unselected word lines, when reading data.