Patent ID: 9030904
Filing Date: 2015-05-12
Classification: G06F,G11C

Abstract:
1. A memory device comprising: a plurality of memory blocks; a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number; a storage circuit configured to store additional refresh information; and a refresh control unit configured to control the first number of memory blocks to be refreshed when the additional refresh information is activated, and to control the second number of memory blocks to be refreshed when the additional refresh information is deactivated whenever a refresh command is executed in which the second mode is set by the setting circuit, wherein, activation and deactivation of the additional refresh information is determined by a data retention time of the memory device.