Patent ID: 8577717
Filing Date: 2013-11-05
Classification: G06Q

Abstract:
1. A method for predicting cost benefits of an integrated circuit chip design shrink, the method comprising: calculating, by a business assessment computer, an original yield result based on a design layout of the integrated circuit chip using a yield simulator executed on the business assessment computer; populating original layout information into a database in computer readable storage, the database comprising information of different shrink rules of the integrated circuit chip for a plurality of design shrinks, each design shrink generated by an application of a different technology shrink factor to the design layout, each different technology shrink factor being defined from a first dimension to a second dimension, the different shrink rules being organized in a plurality of shrink tables each having a plurality of critical area values corresponding to different critical dimension bins, wherein the plurality of shrink tables includes a first shrink table associated with the design layout and a plurality of second shrink tables each associated with a respective one of the plurality of design shrinks; calculating, by the business assessment computer, a plurality of shrunk yield results for the plurality of design shrinks based on the design layout, the different shrink rules, and a process parameter using a shrinkable regression-model calculator executed on the business assessment computer; and determining, by the business assessment computer, a cost benefit across the plurality of design shrinks based on the original yield result and the shrunk yield results, wherein the cost benefit includes a predicted cost savings over a defined time period.