Patent ID: 6651038
Filing Date: 2003-11-18
Classification: G01R,G06F

Abstract:
A simulation testbench comprising:a circuit under test; a plurality of test models including at least one of a driver which selectively applies stimuli to the circuit under test, and a monitor which observes responses to the stimuli from the circuit under test; a controller for the plurality of test models, said controller having an instruction source including a list of commands which control the plurality of test models; a model control bus over which the commands are routed to the plurality of test models from the instruction source; bus interfaces associated with each of the plurality of test models, each of said bus interfaces linking its associated test model to the model control bus, wherein each bus interface includes a test model control which signals its associated test model to begin an operation in accordance with an accepted command, and receives signals indicative of its associated test model completing the operation; and, a sequencer which addresses one command at a time from the list such that it is put out on the model control bus.