Patent ID: 6594181
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A method of reading a double-bit core cell of a memory device, the double-bit core cell having two bits stored as voltage thresholds therein, the first bit being the normal bit and the second bit being the complementary bit; the memory device having two double-bit reference cells associated with the double-bit core cell, each of the double-bit reference cells having a first and second reference bit stored as a predetermined reference threshold; the method comprising the steps of:reading the normal bit threshold of the core cell; reading the first reference bit predetermined threshold of each of the double-bit reference cells; comparing the core cell normal bit threshold to the first reference bit threshold of each of the two reference cells simultaneously; reading the complementary bit threshold of the core cell; reading the second reference bit threshold of each of the double-bit reference cells; comparing the core cell complementary bit threshold to each of the second reference bit thresholds of each of the two reference cells simultaneously; wherein based on the comparisons the binary value of the bits of the double-bit core cell are determined.