Patent ID: 6806140
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method of fabricating a semiconductor memory device, comprising:forming trench regions filled with an insulating material at predetermined intervals, the trench regions being buried in a semiconductor substrate such that they are adjacent to the surface of the semiconductor substrate; forming a bit line between adjacent trench regions in the semiconductor substrate; sequentially forming a first insulation layer, a conductive layer for a word line and a mask layer of an insulating material over the resulting structure including the bit line; forming a word line having the mask layer on its top surface overlying the trench regions; forming a second insulation layer on the sidewall of the exposed word line; exposing a portion of the surface of the bit line adjacent to the sidewall of the word line where the word line and the bit line intersect; forming a first source/drain region material layer on the exposed bit line; forming a body region material layer on the semiconductor substrate including the first source drain region material layer such that the body region material layer has a predetermined height from the mask layer on the word line; etching a portion of the body region material layer to form a body region on the first source/drain region material layer; and forming a second source/drain material layer on the body region.