Patent ID: 6977202
Filing Date: 2005-12-20
Classification: H01L

Abstract:
1. A method of making a semiconductor memory device that has a substrate, memory cells on the substrate that each has a floating gate, a control gate, a first insulating layer between the substrate and the floating gate and an intergate insulating layer between the floating and control gates, and a logic circuit with a logic gate separated from the substrate by a second insulating layer, the method comprising the steps of: for the memory cells, sequentially laminating on the substrate a first layer that will form the first insulating layer, a second layer that will form the floating gate, a third layer that will form the intergate insulating layer, and a fourth layer that will form the control gate, to form a memory cell lamination; for the logic circuit, sequentially laminating on the substrate a fifth layer that will form the second insulating layer, a sixth layer that will form the logic gate, and a protection layer, to form a logic circuit lamination; in one lithography step, applying a mask layer to the fourth layer of the memory cell lamination and to the protection layer of the logic circuit lamination; and first patterning the fourth layer of the memory cell lamination using the mask layer and protecting the sixth layer of the logic circuit lamination with the protection layer during patterning of the fourth layer; and second patterning the second and third layers of the memory cell lamination and the protection layer and the sixth layer of the logic circuit lamination using the mask layer.