Patent ID: 7547571
Filing Date: 2009-06-16
Classification: H01L

Abstract:
1. A packaging method of a light-sensing semiconductor device, comprising the steps of: providing a light-sensing wafer having multiple light-sensing chips, wherein each said light-sensing chip has a light-sensing region and a non-light-sensing region positioned along a perimeter of said each light-sensing chip; forming a buffer layer of a predetermined thickness on said light-sensing wafer; etching a plurality of trenches in said buffer layer substantially in alignment with said non-light-sensing regions of neighboring light-sensing chips, each trench having a bottom of predetermined dimensions positioned at a predetermined depth, said depth being smaller than said predetermined thickness of said buffer layer; removing portions of said buffer layer above said light-sensing regions through the entire said predetermined thickness thereof, and removing respective portions of said buffer layer between said bottom of said each trench and said light-sensing wafer to form channels of cross-sectional dimensions smaller than said predetermined dimensions of said bottom of said each trench, thereby forming a plurality of pairs of spacer walls on a respective areas corresponding to non-light sensing regions of neighboring light-sensing chips, in each pair thereof, said spacer walls being separated by respective one of said channels, wherein said each pair of spacer walls has a common one of said plurality of trenches positioned at tops of said pair of spacer walls, and wherein said common trench defines a receiving cavity at the tops of said spacer walls in each said pair thereof; applying an adhesive in said receiving cavity at the tops of said spacer walls; and affixing a light transparent cover to said tops of said spacer walls via said adhesive, wherein at least one of said light-sensing regions, said space walls and said light transparent cover form at least one airtight space, and wherein said adhesive is substantially localized within said receiving cavity and said channel between said spacer walls in each said pair thereof.