Patent ID: 8859370
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A method for forming an impurity region of a vertical transistor, comprising: preparing a semiconductor substrate having a first region and a second region; forming a first mask pattern on the semiconductor substrate; forming an impurity ion junction region on the semiconductor substrate by performing an ion implantation process using the first mask pattern; forming a material layer on the semiconductor substrate in which the impurity ion junction region is formed by using a material which is substantially equal to a material of the semiconductor substrate; forming a second mask pattern on the material layer, wherein the second mask pattern has an opening exposing a portion of the material layer covering the second region, wherein the second mask pattern is formed by an exposure process in such a state that a photomask used to form the first mask pattern is shifted in a horizontal direction; and forming the trench by etching the second region using the second mask pattern as an etching mask, wherein the etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.