Patent ID: 6735139
Filing Date: 2004-05-11
Classification: G11C

Abstract:
A memory system having asynchronous SRAM functionality comprising:a DRAM array; a first portion adapted to receive external memory commands and to detect external address transitions in order to perform read and write operations on said DRAM array asynchronously; a second portion adapted to selectively interrupt said external memory commands in order to perform refresh operations on said DRAM array, and to selectively interrupt write operations in progress on said DRAM array; and a third portion adapted to perform read, write, refresh and retire operations on said DRAM array, and including a write data buffer for registering unwritten write data when a write operation is interrupted, and an address buffer for registering an address signal corresponding to said unwritten write data, wherein the third portion selectively retires said unwritten write data to said DRAM array after a refresh operation is completed.