Patent ID: 6965973
Filing Date: 2005-11-15
Classification: G06F,Y10S

Abstract:
1. A node comprising: a memory controller configured to couple to a memory and having a plurality of coherency blocks, wherein the node permits coherent access to the plurality of coherency blocks by other nodes; a directory configured to track a state, in the other nodes, of at most a first number of the plurality of coherency blocks, the first number less than a total number of the plurality of coherency blocks, wherein the directory includes a plurality of entries, each entry configured to track the state of one coherency block; a control circuit coupled to the directory, wherein, in response to an access by one of the other nodes to a first coherency block that is a miss in the directory, the control circuit is configured to select a first entry of the plurality of entries to track the state of the first coherency block, and wherein, if the first entry is currently tracking the state of a second coherency block, the node is configured to cause the second coherency block to be invalidated in the other nodes; and a probe buffer configured to store probes that are sent to each other node storing a copy of the second coherency block to invalidate the second coherency block, in which a particular probe remains in the probe buffer until responses to the particular probe have been received by the node.