Patent ID: 6788591
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A control circuit for a memory array device having one or more memory storage cells associated therewith, comprising:a true bit-line and a complementary bit-line coupled to the one or more memory storage cells; a sense amplifier coupled to said true and complementary bit-lines, said sense amplifier configured to amplify a small voltage difference between said true bit-line and said complementary bit-line to a full level signal at predetermined high and low logic voltage levels; and a bit-switch pair for selectively coupling said bit-lines and said sense amplifier to fan-in circuitry, said bit-switch pair further configured so as to couple said fan-in circuitry to said true and complementary bit-lines prior to the activation of a word-line associated with a selected cell for a write operation thereto, thereby commencing said write operation to said selected cell prior to the completion of time associated with signal development on said true and complementary bit-lines.