Patent ID: 8479155
Filing Date: 2013-07-02
Classification: G06F

Abstract:
1. A system for programming an application configured for execution on a multi-core computing device, comprising: a processor; a memory; a hypergraph template library, stored in the memory and executable by the processor, comprising: a plurality of hypergraphs that are located in a top level of a programming code, the top level configured to provide a single pointer to the plurality of data structures; and a plurality of bulk data areas forming at least a portion of the application configured for execution on the multi-core computing device, the plurality of hypergraphs including: a plurality of pointers such that the multi-core computing device that runs the application accesses a second processor, the second processor including cache memory and main memory, the application capturing the plurality of pointers in the cache memory and capturing a plurality of data structures in the main memory; and a basic hypergraph that comprises a hyperedge table, a tentacle table, a vertex table and a backpointer table.