Patent ID: 7482860
Filing Date: 2009-01-27
Classification: H03K

Abstract:
1. An electronic circuit, comprising a signal conductor a power supply reference conductor and a switching circuit coupled between the signal conductor and the power supply reference conductor, the switching circuit comprising: a substrate arrangement coupled to the power supply reference conductor; a first MOS transistor realized on said substrate arrangement with a source, a drain and a gate, the source being coupled to the power supply reference conductor the first MOS transistor having a first conductivity type; a second MOS transistor realized on said substrate arrangement with a source, a drain and a gate, the source being coupled to the drain of the first MOS transistor the drain being coupled to the signal conductor the second MOS transistor having a second conductivity type opposite the first conductivity type; a control circuit with outputs coupled to the gate of the first MOS transistor and the gate and source of the second MOS transistor the control circuit being arranged to switch between an “on” state and an “off” state, in which the control circuit controls the gate source voltages of the first and second MOS transistors to make channels of the first and second MOS transistors conductive and not to make the channels of these first and second MOS transistors conductive respectively; wherein each of the first and second MOS transistors have source-drain diodes in anti-series so that said first and second MOS transistors have a respective maximum breakdown voltage at drain voltages in mutually opposite directions relative to a substrate voltage, wherein the control circuit comprises: a power supply input for supplying a power supply voltage with a first polarity relative to the power supply reference conductor the first conductivity type being such that the channel of the first MOS transistor becomes conductive when a voltage at its gate has a second polarity, opposite the first polarity relative to its source; a pump circuit fed with the power supply voltage and arranged to generate the gate voltage of the first MOS transistor with the second polarity relative to the power supply reference conductor in the “on” state.