Patent ID: 6867619
Filing Date: 2005-03-15
Classification: G11C

Abstract:
1. A shift registercomprising: a first switch having input node, control node and an output node connecting to a control node of a second switch and one terminal of a storage element, the second switch having an output node connecting to an output node of a third switch to form a first stage circuit and an output node thereof; an input signal generated on the input node of the first switch and a first clock signal generated on the control node, the second switch having another input node receiving a second clock signal, the third switch having a control node receiving a third clock signal; and a fourth switch connecting to the output node of the first stage circuit, the fourth switch having an output node connecting to a control node of a fifth switch and one terminal of a second storage element, the fifth switch having an output node connecting to an output node of a sixth switch to form a output node of the second stage circuit; the fifth switch having another input node receiving the first clock signal, and the sixth switch having a control node receiving the third clock signal; wherein the first stage circuit and the second stage circuit are controlled by the first clock signal, the second clock signal, and the third clock signal to achieve shift transfer of the input signal.