Patent ID: 7519862
Filing Date: 2009-04-14
Classification: G01R,G06F,G11C

Abstract:
1. A method for testing and debugging an embedded device under test, the method comprising: loading, from within a built-in self-test (BIST) module, an instruction into a parameterized shift register of said BIST module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test, wherein said parameterized shift register comprises a plurality of formatted portions for simultaneously handling a BIST command, a counter value, a first address and a second address; determining, within said BIST module, an identity of the loaded instruction; and generating, within said BIST module, a plurality of test signals corresponding to said determined identity of said loaded instruction, each of said generated plurality of test signals causing control and execution of the testing and debugging of a corresponding one of each of said plurality of embedded memory modules comprising the embedded device under test.