Patent ID: 6205462
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A Multiply-Accumulate circuit comprising:(a) an exponent adder circuit having:a first multi-bit output;first and second multi-bit inputs for receiving as input first and second exponents of first and second operands, respectively, to be added by said exponent adder circuit, said adding of said first exponent and said second exponent by said exponent adder circuit producing a control exponent sum at said first multi-bit output, said first and second operands being both in a combined data format, said combined data format prescribing a mantissa and an exponent for both integer and floating point operands, said first and second operands having first and second mantissas, respectively, said exponent adder circuit monitoring said first exponent at said first multi-bit input and determining if said first operand is an integer, and in response to said first operand being an integer, substituting said first exponent in said adding by said exponent adder circuit with a substitute exponent, said substitute exponent being related to the number of bits of said first mantissa;(b) a mantissa multiplier circuit having third and fourth multi-bit inputs for receiving as input first and second mantissas of said first and second operands, respectively, and a second multi-bit output, said mantissa multiplier circuit multiplying said first mantissa and said second mantissa to produce a mantissa product at said second multi-bit output; and(c) a shifter having fifth and sixth multi-bit inputs and a third multi-bit output, said fifth multi-bit input being connected to said first multi-bit output, said sixth multi-bit input being connected to said second multi-bit output, said shifter shifting said mantissa product according to said control exponent sum to produce a shifted number at said third multi-bit output, said shifted number being in a pre-defined fixed point format.