Patent ID: 6161188
Filing Date: 2000-12-12
Classification: G06F

Abstract:
A microprocessor having a configurable core-to-bus clock ratio, the configurable core-to-bus clock ratio determining a first frequency of a core clock signal within the microprocessor, the core clock signal being derived from a bus clock signal operating at a second frequency that is provided to the microprocessor from an external source, the microprocessor comprising:a fuse, configured to provide a permanent state that prescribes the configurable core-to-bus clock ratio; andbuffer/control logic, coupled to said fuse, configured to accept said permanent state and to direct the microprocessor to either set the configurable core-to-bus clock ratio according to the states of a plurality of clock ratio signals or to ignore said states and to set the configurable clock ratio to a fixed multiple of the second frequency.