Patent ID: 8159026
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A semiconductor lateral device having three outer terminals formed on a substrate of first conductivity type with current in conduction state comprising of flows of two types of majorities simultaneously in their own drift region, said device consists of a highest voltage region and a lowest voltage region with said substrate being zero voltage and a surface voltage-sustaining region between said highest voltage region and said lowest voltage region; wherein said surface voltage-sustaining region has at least three layers, a positive integral number of order of said layers is set starting from a layer contacted to said substrate up to the top of semiconductor surface, layers of odd numbers are semiconductor of second conductivity type and serve as drift regions of majorities of second conductivity; layers of even number numbers are semiconductor regions of a first conductivity type and serve as drift regions of majorities of first conductivity type; said highest voltage region is a semiconductor region of second conductivity type and contacted directly to said first layer of said surface voltage-sustaining region, an electrode of highest voltage is formed on the top of said highest voltage region and serves as an outer terminal of highest voltage; said highest voltage region can have a first active device region of majorities of first conductivity type, where a semiconductor region of first conductivity type serving as source region of majorities of first conductivity type is formed inside said highest voltage region, and a part of said source region of first active device region is contacted directly to said electrode of highest voltage; said first active device region of majorities of first conductivity type has a first control terminal for controlling majorities of first conductivity type flow to said layers of even number of said surface voltage-sustaining region; said lowest voltage region is a semiconductor region of first conductivity type, an electrode of lowest voltage is formed on the top of said lowest voltage region and serves as an outer terminal of lowest voltage; said lowest voltage region can have a second active device region of second conductivity type, where a semiconductor region of second conductivity type serving as source region of majorities of second conductivity type is formed inside said lowest voltage region, and a part of said second active device region is contacted directly to said electrode of lowest voltage; said second active device region of second conductivity type has a second control terminal for controlling majorities of second conductivity type flow to said layers of odd number of said surface voltage-sustaining region; said surface voltage-sustaining region has at least an inner terminal; when said inner terminal is located inside a layer of semiconductor of first conductivity type close to second active device region, said inner terminal connected directly or indirectly to second control terminal, then, second control terminal, is not an outer terminal; when said inner terminal is located inside a layer of semiconductor of second conductivity type close to first active device region, said inner terminal connected directly or indirectly to first control terminal, then, first control terminal, is not an outer terminal; said semiconductor lateral device is formed by integrating different kinds of sub-devices, each sub-device has its own highest voltage region and lowest voltage region and surface voltage-sustaining region; each kind of sub-device includes an inner terminal and/or or an outer terminal; the highest reverse bias voltage is sustained between said highest voltage region and the bottom of the substrate, said highest voltage region has an average density of doping of second conductivity type not smaller than D when said semiconductor region of first conductivity type is p-type and said majorities of first conductivity type are holes and said semiconductor region of second conductivity type is n-type and said majorities of second conductivity type are electrons, said highest reverse voltage to said substrate of zero voltage is a positive value; when said semiconductor region of first conductivity type is n-type and said majorities of first conductivity type are electrons and said semiconductor region of second conductivity type is p-type and said majorities of second conductivity type are holes, said highest reverse voltage to said substrate of zero voltage is a negative value.