Patent ID: 8094754
Filing Date: 2012-01-10
Classification: H03L,H04L

Abstract:
1. In a clock and data recovery (CDR) device frequency synthesizer, a method for holding the frequency of a non-synchronous communication signal, the method comprising: using a phase detector (PHD) to acquire the phase of a non-synchronous first communication signal having a first frequency; in response to acquiring the phase of the first frequency, dividing a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency; saving the frequency ratio value in a tangible memory medium; in response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, retrieving the frequency ratio value from memory; using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, generating a second synthesized signal with the first frequency; and, in response to using the PFD to generate the second synthesized signal with the first frequency, using a rotational frequency detector (RFD) to generate the second synthesized signal having an output frequency equal to second frequency.