Patent ID: 6559850
Filing Date: 2003-05-06
Classification: G06F,G09G

Abstract:
A device, comprising:a memory controller configured to access a system memory to obtain data in response to a plurality of Advanced Graphics Port (AGP) pipelined read requests; an AGP interface configured to provide an interface to an AGP bus and to receive the plurality of AGP pipelined read requests from a requesting AGP device in a first order and return a data response to the requesting AGP device for each of the plurality of AGP pipelined read requests in a second order different from the first order, wherein each said data response comprises the data obtained by the memory controller from the system memory for the corresponding AGP pipelined read request; and a transaction ID unit configured to associate a transaction ID with each said data response, wherein the transaction ID for each said data response is returned to the requesting AGP device.