Patent ID: 6534414
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A complementary metal-oxide semiconductor (CMOS) dual-gate semiconductor fabrication method comprising:providing a polysilicon layer of a first type over a first region of a semiconductor substrate; providing a polysilicon layer of a second type over a second region of the semiconductor substrate; depositing a metallic layer overlying the polysilicon layers in the first and second regions; depositing an anti-reflective layer overlying the metallic layer in the first and second regions; selectively etching the anti-reflective layer; forming a first photoresist pattern overlying the anti-reflective layer in the first region; first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; forming a second photoresist pattern overlying the anti-reflective layer in the second region; and second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region.