Patent ID: 7620954
Filing Date: 2009-11-17
Classification: G06F

Abstract:
1. A distributed multiprocessing computer system, which includes a plurality of processors, each coupled to an associated memory module, wherein each of the associated memory modules stores data that is shared between said processors, said system comprising: a Home processor that includes a memory block and a directory for said memory block in the associated memory module; an Owner processor that includes a cache memory, and wherein said Owner processor obtains an exclusive copy of said memory block, and stores said exclusive copy of said memory block in said cache memory; wherein said Owner processor begins write operations on said memory block and then displaces the exclusive copy of said memory block from said cache memory prior to completing the write operations on said memory block, and in response to displacing said memory block prior to completing the write operations said Owner processor returns said displaced copy of said memory block to said Home processor with a signal indicating that said Owner processor remains a sharer of said memory block; and wherein said Owner processor includes a register in which an address is stored representing a memory block obtained in response to a lock instruction, compares an address of any displaced data with the address stored in said register, and asserts a shared message if the address of any displaced data matches the address stored in said register.