Patent ID: 7877655
Filing Date: 2011-01-25
Classification: G01R

Abstract:
1. A method for testing an integrated circuit comprising a step of performing a test case with at least one logic built-in self-test (LBIST) engine on the integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme, wherein: the LBIST engine is partially formed by the storage elements and the logic circuits provided for functional purposes, at least one scan chain is formed by selected ones of the storage elements, keeping the non-selected storage elements to be used for the LBIST engine or a portion thereof in a testing mode, said at least one scan chain being driven by a test pattern, wherein the LBIST tests a subset of the logic circuits corresponding to the selected storage elements of said at least one scan chain, and wherein when in the testing mode, the LBIST engine runs with scan clocks enabled providing an LBIST test function, the same storage elements that form the LBIST engine being reused to create a new logical function when the integrated circuit is not in the testing mode and functional clocks are running, said new logical function being independent of said LBIST test function.