Patent ID: 6172398
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A vertical DMOS transistor cell formed in a semiconductor substrate of a first conductivity type with a top surface and a bottom surface, said DMOS transistor cell comprising:a trenched gate having a polysilicon filling a trench opened from said top surface disposed substantially in a middle portion of said transistor cell;a source region of said first conductivity type surrounding said trenched gate near said top surface of said substrate;a body region of a second conductivity type surrounding said trenched gate encompassing said source region;said body region further includes a body-dopant redistribution-compensation region disposed immediately below said source region for providing a delta-incremented body dopant concentration near a channel region along said trenched gate immediately below said source region and having a substantially same width as said source region for adjusting a threshold voltage of said vertical DMOS transistor cell.