Patent ID: 9189057
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. An apparatus for optimizing performance and power consumption of a multi-core processor, comprising: a main controller; a multi-core processor including a plurality of cores, said multi-core processor being coupled to a clock source configured to provide a reference input clock frequency to said plurality of cores in said multi-core processor, each of said cores of said plurality of cores having a specification core frequency preset for said multi-core processor, and each of said cores of said plurality of cores being connected to separate supply voltage sources, each of the separate supply voltage sources being connected, in parallel, to said main controller and a voltage level-translating communication transceiver to allow individual adjustment of the separate supply voltage sources, by said main controller, for each of said cores of said plurality of cores; said supply voltage sources, wherein said plurality of cores has a respective operational core frequency that is proportional to said supply voltage provided by said respective supply voltage source; and said main controller coupled to said plurality of cores, said main controller being configured to adjust said supply voltage provided by said supply voltage source connected to said respective core to increase the supply voltage of an underperforming core of the multi-core processor in order to increase said reference input clock frequency provided to said respective core and to decrease the supply voltage of an overperforming core of the multi-core processor in order to decrease an increased power consumption resulting from the increase, wherein adjustment of either said supply voltage provided and said respective input clock frequency provided to said respective core optimizes a respective core performance and a respective core power consumption by said respective core, and wherein said main controller dynamically adjusts said supply voltage provided by said supply voltage source to said plurality of cores in real-time.