Patent ID: 8053361
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method for forming a semiconductor device comprising: providing a substrate prepared with a dielectric layer formed thereon; reducing an initial height H forming the first upper etch stop layer on the dielectric layer, the first upper etch stop layer comprising a first material; patterning the dielectric layer and first upper etch stop layer to form an interconnect opening; filling the interconnect opening with a conductive material to form the interconnect, the interconnect and first upper etch stop layer having coplanar top surfaces; and forming a second upper etch stop layer over the coplanar top surfaces and directly contacting the coplanar top surfaces, wherein the second upper etch stop layer comprises a second material similar to the first material to provide sufficient adhesion with the first material to reduce diffusion of the conductive material.