Patent ID: 7383422
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. A processor having a plurality of registers and a plurality of operation units, which executes a very long instruction word including (i) a register specifying field which specifies at least one of said registers, (ii) a plurality of instruction operational codes which respectively specify operations using said operation units, and (iii) a register allocation information field including register allocation information which indicates a corresponding relationship between the at least one of said registers specified by said register specifying field and each instruction operational code which uses the at least one of said registers specified by said register specifying field, said processor comprising: an output port which outputs a value stored in the at least one of said registers specified by said register specifying field; and an input selection control unit operable to select the value output from said output port and output the selected value to at least one of said operation units according to the corresponding relationship indicated by said register allocation information; wherein said register allocation information field is a different field of the very long instruction word than said register specifying field, such that said register specifying field does not include said register allocation information; wherein said register specifying field is independent from the instruction operational codes, such that said register specifying field does not include any of the instruction operational codes; wherein said register specifying field specifies all of the registers of the processor used by the very long instruction word; and wherein said processor executes, using the selected value output by said input selection control unit, the operations specified by the instruction operational codes.