Patent ID: 7080240
Filing Date: 2006-07-18
Classification: G06F

Abstract:
1. A data processor apparatus comprising: a first instruction storing means holding a series of instructions to be executed reiteratively; a second instruction storing means temporarily holding the series of instructions; an instruction executing section executing the series of instructions; a start address register storing a start address of the series of instructions; an end address register storing an end address of the series of instructions, and a repeat count register storing a required number of execution repeats of said series of instructions, wherein said second instruction storing means is capable of holding a predetermined number of instructions, wherein said start and end addresses are loaded into the start and end address registers, respectively, by a specific instruction or instructions, wherein a number of instructions constituting the series of instructions is calculated based on the difference between said start address and said end address, wherein when the number of instructions constituting the series of instructions is less than the predetermined number, said second instruction storing means starts to store therein the series of instructions after the calculation of the number of instructions constituting the series of instructions, and said instruction executing section reads and executes the series of instructions from said second instruction storing means, wherein when the number of instructions constituting the series of instructions is greater than the predetermined number, said instruction executing section reads and executes the series of instructions from said first instruction storing means, and wherein said instruction executing section executes the series of instructions a number of times equal to the required number of execution repeats stored in said repeat count register.