Patent ID: 7250346
Filing Date: 2007-07-31
Classification: H01L

Abstract:
1. A method of forming a dual gate oxide layer, comprising: sequentially forming a first insulation layer and a second insulation layer on a semiconductor substrate; sequentially etching the second insulation layer, the first insulation layer and a portion of the semiconductor substrate to form a trench for defining first and second active regions on the semiconductor substrate; filling the trench with a device isolation layer; planarizing the device isolation layer and the second insulation layer so that the second insulation layer formed on the first insulation layer remains by a determined thickness; removing the remaining second insulation layer; etching the first insulation layer and the device isolation layer such that an uppermost part of the device isolation layer is positioned below an upper surface of the semiconductor substrate that includes the first and second active regions; forming a first thermal oxide layer for use as a gate oxide layer on an upper surface of the first and second active regions and in a sidewall of a non-filled trench; removing the first thermal oxide layer provided with the first active region; and forming a second thermal oxide layer for use as a gate oxide layer on an upper surface of the first active region and a non-filled trench sidewall of the first active region, the second thermal oxide layer having a thickness thinner than the first thermal oxide layer.