Patent ID: 6407611
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method of providing compensation of integrated circuit design parameters, comprising the steps of:biasing a first MOSFET with a first known current; biasing a second MOSFET with a second known current; wherein said second known current is a multiple of said first known current; determining &Dgr;VGS of said first and second MOSFETs, wherein said &Dgr;VGS is inversely proportional to the transconductance of said first MOSFET; determining a relationship between said transconductance and a circuit performance parameter, thereby establishing a relationship between said &Dgr;VGS and said circuit performance parameter; implementing process compensation, wherein said &Dgr;VGS is compared to a known reference voltage; and latching an output of said process compensation step into digital decoding logic, thereby deriving a process compensation current.