Patent ID: 8664721
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A field effect transistor (FET) comprising: source/drain silicide regions located in a silicon layer; source/drain segregated interfacial layers located in between the source/drain silicide regions and the silicon layer; a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate segregated interfacial layer located on the gate oxide layer, and a gate silicide located on the gate segregated interfacial layer; highly doped source/drain regions located in the silicon layer, wherein the source/drain silicide regions are located in the highly doped source/drain regions, and the source/drain segregated interfacial layers are located in between the source/drain silicide regions and the highly doped source/drain regions; and wherein the source/drain segregated interfacial layers and the gate segregated interfacial layer comprise segregated dopants.