Patent ID: 6452423
Filing Date: 2002-09-17
Classification: H03K

Abstract:
A circuit for avoiding a contentious condition, comprising:a transmission gate multiplexer having n transmission gates where n is more than one, each of said n transmission gates coupled respectively to n select lines and the ith transmission gate being a polarity-modified transmission gate that is active at a logic state opposite the logic state at which all other transmission gates are active; n NAND gates coupled respectively to each of said n select lines, the ith NAND gate coupled to the ith select line corresponding to said ith transmission gate; n flip-flops coupled respectively to a first input of said n NAND gates, the ith flip-flop coupled at its non-inverting output to said ith NAND gate and the remaining flip-flops coupled respectively at their inverting outputs to the remaining NAND gates; and a control input coupled to a second input on each of said n NAND gates.