Patent ID: 8194690
Filing Date: 2012-06-05
Classification: H04L

Abstract:
1. A method for processing packets in a system that comprises a plurality of interconnected processor cores, the method comprising: receiving packets into a plurality of queues; associating at least some nodes at a first level in a hierarchy of nodes with respective ones of the plurality of queues, and associating at least some of the nodes at a second level in the hierarchy with respective rates of transfer; mapping a first set of nodes at the first level in the hierarchy to a plurality of processor cores based on at least one rate associated with a node at the second level in the hierarchy, with a first subset of nodes in the first set being mapped to a first group of processor cores and a second subset of nodes in the first set being mapped to a second group of processor cores, and with a first processor core in the first group being responsible for a first function for the nodes in the first subset, a second processor core in the first group being responsible for a second, different function for the nodes in the first subset, a first processor core in the second group being responsible for the first function for the nodes in the second subset, and a second processor core in the second group being responsible for the second, different function for the nodes in the second subset; and processing the packets in processor cores including the mapped processor cores according to the hierarchy.