Patent ID: 7545001
Filing Date: 2009-06-09
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an isolation region located in a substrate; an NMOS device located partially over a surface of the substrate; and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface; an etch stop layer on the substrate overlying the NMOS device and the PMOS device; and wherein a first one of the NMOS and PMOS devices includes a gate and a first source/drain regions, wherein the first source/drain regions are recessed and disposed entirely below the surface of the substrate and wherein the first source/drain regions are recessed such that the etch stop layer overlying the gate and the first source/drain regions extends below an interface of the gate and the surface; and wherein a second one of the NMOS and PMOS devices includes second source/drain regions at least partially extending above the surface of the substrate, and wherein the etch stop layer imparts a first strain within the first source/drain region and a second strain within the second source/drain region, the first and second strain being different in magnitude.