Patent ID: 7075332
Filing Date: 2006-07-11
Classification: H03K

Abstract:
1. A six-input look-up table architecture comprising: sixty-four memory cells adapted to store sixty-four corresponding data values; a 64:1 multiplexer having input terminals coupled to receive the sixty-four data values from the sixty-four memory cells; six input lines providing six input signals and coupled to corresponding control terminals of the 64:1 multiplexer, wherein the 64:1 multiplexer is configured to asynchronously read any one of the sixty-four data values as an output value in response to the six input signals; sixty-four write control circuits, each coupled to a corresponding one of the sixty-four memory cells, and each coupled to receive a write data value; a first write address decoder coupled to receive a first subset of the six input signals, and in response, provide a first set of write select signals to the sixty-four write control circuits; and a second write address decoder coupled to receive a second subset of the six input signals and a write clock signal, and in response, provide a plurality of decoded write clock signals to the sixty-four write control circuits.