Patent ID: 8324925
Filing Date: 2012-12-04
Classification: H03K

Abstract:
1. An output buffer circuit comprising: one or more inverters; a delay circuit for delaying an input signal for a specific time; one or more buffers; means for transmitting a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages; and means for making a preemphasis amount variable, wherein the buffer, which controls the ON resistance thereof as a variable resistor, includes a P-type transistor and an N-type transistor that are connected between a high-potential power source and a low-potential power source; the P-type transistor and the N-type transistor operate complementarily to each other, with the assistance of a signal applied to the input terminal thereof; transistors configured to serve as variable resistors are connected between the P-type transistor and the N-type transistor; and respective resistance-adjustment variable voltages are applied to gate pins of the transistors serving as the variable resistors, and by adjusting the variable voltages, the ON resistance of the buffer is adjusted.