Patent ID: 6842373
Filing Date: 2005-01-11
Classification: G11C

Abstract:
1. A command decoder for use in a semiconductor memory device, comprising: a control circuit configured to operate in either a first mode or a second mode responsive to a control signal; a read signal generating circuit for generating a read signal that transits from a first state to a second state in response to a transition from the second state to the first state of a clock signal when an inverted chip selecting signal has the first state and an inverted row address strobe signal has the second state during a transition from the first state to the second state of the clock signal when the control circuit is in the first mode; a write signal generating circuit for generating a write signal that transits from the first state to the second state in response to a transition from the second state to the first state of the clock signal when the inverted chip selecting signal has the first state and the inverted row address strobe signal has the first state during a transition from the first state to the second state of the clock signal when the control circuit is in the first mode; a first switching circuit for transferring an inverted column address strobe signal and an inverted write enable signal when the control circuit is in the second mode; and a first decoding circuit for generating internal command signals by decoding the inverted chip selecting signal and the read and write signals when the control circuit is in the first mode and by decoding the inverted chip selecting signal, the inverted row address strobe signal, the inverted column address strobe signal, and the inverted write enable signal when the control circuit is in the second mode.