Patent ID: 6670662
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A semiconductor memory component, having memory cells, logic regions and dummy structures with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with a conductive material, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with a conductive material, in the lower oxide layer and the upper oxide layer, in which component between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures, wherein in the contact hole there is a structure, the composition of which corresponds to that of the structure of the lower electrode of the capacitor and of the contact hole, as a result of a plug of material, which is of the same thickness as the lower electrode, being arranged in the contact hole in the region of the upper oxide layer, and as a result of a further plug, which corresponds to the material filling the contact hole, being provided in the lower region of the contact hole inside the lower oxide layer.