Patent ID: 6044391
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A method for generating a sticky-bit of a multiplication operation of first and second operands comprising:receiving a first sixteen bits of said first operand by an input port of a first sixteen-bit encoder wherein said first sixteen-bit encoder includes first, second, third, fourth and fifth output terminals;receiving a second sixteen bits of said first operand by an input port of a second sixteen-bit encoder wherein said second sixteen-bit encoder includes first, second, third, fourth and fifth output terminals;receiving a third sixteen bits of said first operand by an input port of a third sixteen-bit encoder wherein said third sixteen-bit encoder includes first, second, third, fourth and fifth output terminals;receiving a last four bits of said first operand by an input port of a four-bit encoder wherein said four-bit encoder includes first, second, and third output terminals;receiving a signal on a first input lead of a first multiplexer from said first output terminal of said first sixteen-bit encoder;receiving a signal on a second input lead of said first multiplexer from said first output terminal of said second sixteen-bit encoder;receiving a signal on a third input lead of said first multiplexer from said first output terminal of said third sixteen-bit encoder;receiving a signal on a fourth input lead of a first multiplexer from said first output terminal of said four-bit encoder wherein said first multiplexer includes an output line;receiving a signal on a first input lead of a second multiplexer from said second output terminal of said first sixteen-bit encoder;receiving a signal on a second input lead of said second multiplexer from said second output terminal of said second sixteen-bit encoder;receiving a signal on a third input lead of said second multiplexer from said second output terminal of said third sixteen-bit encoder;receiving a signal on a fourth input lead of a first multiplexer from said second output terminal of said four-bit encoder wherein said second multiplexer includes an output line;receiving a signal on an input terminal of an inverter from said third output terminal of said four-bit encoder;receiving a signal on a first input lead of a third multiplexer from said third output terminal of said first sixteen-bit encoder;receiving a signal on a second input lead of said third multiplexer from said third output terminal of said second sixteen-bit encoder;receiving a signal on a third input lead of said third multiplexer from said third output terminal of said third sixteen-bit encoder;receiving a signal on a fourth input lead of a first multiplexer from an output terminal of said inverter wherein said third multiplexer includes an output line;receiving a signal on a first input lead of a fourth multiplexer from said fourth output terminal of said first sixteen-bit encoder;receiving a signal on a second input lead of said fourth multiplexer from said fourth output terminal of said second sixteen-bit encoder;receiving a signal on a third input lead of said fourth multiplexer from said fourth output terminal of said third sixteen-bit encoder wherein said fourth multiplexer includes an output line;receiving a signal on a first input lead of a three-bit encoder from said fifth output terminal of said first sixteen-bit encoder;receiving a signal on a second input lead of said three-bit encoder from said fifth output terminal of said second sixteen-bit encoder;receiving a signal on a third input lead of said three-bit encoder from said fifth output terminal of said third sixteen-bit encoder;receiving on first output select terminals of said first, second, third, and fourth multiplexers a signal from a first output lead of said three-bit encoder;receiving on second output select terminals of said first, second, third, and fourth multiplexers a signal from a second output lead of said three-bit encoder;wherein a first encoded value of a number of trailing zeros in the first operand is generated on said output lines of said first, second, third, and fourth multiplexers, and said first and second output leads of said three-bit encoder;receiving said second operand on an input port of a second encoder having a plurality of output lines wherein, in response to said second operand, said second encoder generates, on said plurality of output lines, a second encoded value of a number of trailing zeros in the second operand;receiving said first encoded value by a first input port of an adder circuit;receiving said second encoded value by a second input port of said adder circuit, wherein said adder circuit generates a sum of said first and second encoded values, compares said sum to a predetermined constant, and generates said sticky-bit.