Patent ID: 6205459
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A digital signal processor comprising:an arithmetic operation unit having an output bit width of N;a bus of bit width M that transfers data to be processed by said arithmetic operation unit and results of arithmetic processing by said arithmetic operation unit, wherein M<N;at least one accumulator that holds said results of said arithmetic processing by said arithmetic operation unit and delivers said results to said bus, wherein said at least one accumulator has a bit storage capacity N; anda bypass device that delivers said results to said bus by bypassing said at least one accumulator, wherein said bypass device comprises a delay element that delays delivery of said results of said arithmetic processing by said arithmetic operation unit to said bus, said delay element delivering said results to said bus at a same timing that said results are delivered by way of said at least one accumulator, and wherein said delay element has a bit storage capacity M.