Patent ID: 8471577
Filing Date: 2013-06-25
Classification: G01R,H01L

Abstract:
1. A method of topside only dual-side testing of an electronic assembly comprising: providing said electronic assembly comprising a singulated through substrate via (TSV) die flip chip attached to a die support comprising a multilayer (ML) package substrate, wherein said TSV die has a die area and a plurality of TSVs that extend from its frontside to contactable TSV tips on its bottomside, wherein said TSVs on said frontside of said TSV die are coupled to embedded topside substrate pads on a top surface of said ML package substrate below said die area, and wherein said die support includes lateral coupling paths between at least a portion of said embedded topside substrate pads and lateral topside pads positioned on a topside surface of said die support lateral to said die area; contacting said contactable TSV tips with a first plurality of probes, interfaced to an automatic test system, to provide a first topside connection to said TSVs; contacting said lateral topside pads with a second plurality of probes, interfaced to the automatic test system, to provide a second topside connection, dual-side testing, by the automatic test system, across said electronic assembly using said first and said second topside connections; and obtaining, by the automatic test system, at least one test parameter.