Patent ID: 9135107
Filing Date: 2015-09-15
Classification: G06F

Abstract:
1. A memory control device comprising: a CPU; an electrically-rewritable non-volatile memory that records therein first information having undergone an error-correction coding process and second information not having undergone an error-correction coding process; a first switch device that detects an address output from the CPU, and switches between a first path that connects an address bus to the memory so that the CPU can read first information recorded in the memory and a second path that connects the address bus to the memory so that the second information recorded in the memory can be erased, written, and read; a decoder that performs error correction on the first information recorded in the memory, removes a redundant bit from corrected information, and decodes information before undergoing an error-correction coding process; and a second switch device that detects an address output from the CPU, and switches between a third path that connects the decoder to a data bus so that information decoded by the decoder is transmitted to the data bus of the CPU and a fourth path that connects the memory to the data bus so that the second information recorded in the memory can be erased, written, and read, and the first switch device and the second switch device are separate devices.