Patent ID: 6192409
Filing Date: 2001-02-20
Classification: H04L

Abstract:
An X.25 network connection for X.25 protocol communications used in a full electronic switching system, comprising:,microprocessor (MPU) means for controlling internal circuits of said X.25 network connection in accordance with serving as one of a master and a slave relative to a main bus for interconnecting said internal circuits;switching system interface circuit means provided with a controller for serving as one of a master and a slave relative to said main bus so as to convert X.25 packet data from an X.25 network into IPC (Inter Process Communication) format data for transfer to said switching system;a plurality of X.25 network interface circuits, each provided with a controller serving as one of a master and a slave relative to said main bus so as to convert the IPC format data into the X.25 packet data for transfer to said X.25 network;packet memory means for temporarily storing the IPC format data from said switching system interface circuit means and said X.25 packet data from said X.25 network interface circuits under the control of said MPU means and said controllers of said X.25 network interface circuits;system memory means for storing a system control program and application programs thereof, and for storing data from said packet memory means for said MPU means to analyze said IPC format data and said X.25 format packet data; andbus control circuit means for controlling input and output directions of data and addresses of said internal circuits while preventing collision of the data and addresses through said main bus;wherein said packet memory means comprises:a packet memory for temporarily storing the IPC format data from said switching system interface circuit means and the X.25 format packet data from said X.25 network interface circuits;a packet address buffer for buffering addresses generated by said MPU means and said controllers of the X.25 network interface circuits to access said packet memory and to control said X.25 network interface circuits;a packet data buffer for buffering data transferred from said controllers of the X.25 network interface circuits to said packet memory; anda data buffer for buffering data generated by said MPU means so as to access said packet memory.