Patent ID: 6537877
Filing Date: 2003-03-25
Classification: G11C,H01L

Abstract:
A method of producing a semiconductor memory device comprising a plurality of memory cells each including two inverters which comprises drive transistors having a first conductivity type and load transistors having a second conductivity type connected in series between a first power voltage supply line for supplying a first power voltage and a second power voltage supply line for supplying a second power voltage and having gates connected in common and which have inputs and outputs connected cross-wise, said method comprising a step of forming first and second interconnections for interconnecting the inputs and outputs of the two inverters:said interconnections forming step comprising: successively forming over the entire surface a conductive film for forming node interconnections and a film having an etching rate slower than the conductive film; producing the film with the slower etching rate by using the pattern of the first interconnections to form an etching mask layer; and producing the conductive film by using the pattern of the second interconnections to form the first and second node interconnections by using the resultant etching mask layer to thereby protect the portions of the conductive film directly underneath.