Patent ID: 6215150
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A semiconductor device comprising a drain region, a channel region and a source region all vertically formed in a region of a silicon substrate which is encircled by an element isolation film formed vertically in the silicon substrate; wherein a drain (or source) electrode and a gate electrode are led out from said drain (or source) region to a surface of said silicon substrate, and wherein said gate electrode is electrically isolated from channel region and said drain by a gate-insulating film, while said drain (or source) electrode is electrically isolated by an interlayer insulating film(s) and wherein the drain electrode, channel electrode and source electrode are arranged such that one of the electrodes is disposed at a center and surrounded by another electrode, and the device includes a plurality of element isolation films, each radially extending from the electrode disposed at the center to an outer electrode so as to form a plurality of transistors each partitioned by said element isolation films.