Patent ID: 9214237
Filing Date: 2015-12-15
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series, the nonvolatile memory cells including dummy cells which are not used for data storage provided at the both ends of the memory string and memory cells for data storage which are capable of storing multi-bit data provided between the dummy cells in the memory string; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block, the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a certain pre-program voltage to the memory cells for data storage in the NAND cell units, and by applying a voltage different from the certain pre-program voltage to the dummy cells in the NAND cell units, wherein the certain pre-program voltage is applied to word lines connected to the control gate electrodes of the memory cells for data storage, and the voltage different from the certain pre-program voltage is applied to dummy word lines connected to the control gate electrodes of the dummy cells.