Patent ID: 7724056
Filing Date: 2010-05-25
Classification: G06F,H03K

Abstract:
1. A semiconductor integrated circuit device comprising: a processor core operating in synchronism with a first clock and including a first critical path which is active while the first clock is at an “H” level and a second critical path which is active while the first clock is at an “L” level; a first clock generating section controlling a duty of an externally input second clock to generate the first clock; and a control section detecting a first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time occurring on the first critical path and a second phase difference between the first clock and a fourth clock obtained by delaying the first clock by a delay time occurring on the second critical path, the control section instructing the first clock generating section to control the duty so as to minimize a difference between the first phase difference and the second phase difference.