Patent ID: 8289054
Filing Date: 2012-10-16
Classification: H03F

Abstract:
1. A high voltage (HV) differential pair implemented in a low voltage process, comprising: a differential pair of PMOS transistors having their gates coupled to a pair of differential input voltages; a HV current source coupled to a common source node of the differential pair; wherein the HV current source comprises a first plurality of stacked PMOS transistors and a first voltage divider in series with a first diode; a first and second plurality of stacked transistors coupled to the outputs of the differential pair; and a HV current sink coupled to the common source node of the differential pair; wherein the HV current sink comprises a first plurality of stacked NMOS transistors and a second voltage divider in series with a second diode; wherein the second voltage divider generates a plurality of voltages, and each of the plurality of generated voltages is coupled to a respective gate of the first and second pluralities of stacked transistors.