Patent ID: 7493451
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A processor comprising: a prefetch unit configured to concurrently maintain a plurality of separate, active prefetch streams, wherein each of the plurality of prefetch streams is either software initiated via execution by the processor of a dedicated prefetch instruction that is defined in the instruction set architecture implemented by the processor to cause a prefetch operation or hardware initiated via detection of a data cache miss by one or more load/store memory operations, and wherein a first prefetch stream of the plurality of prefetch streams is allocable to a software initiated prefetch in a first instance, and wherein the first prefetch stream is allocable as a hardware initiated stream in a second instance; and a data cache coupled to the prefetch unit, wherein the prefetch unit is configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache, wherein each of the plurality of prefetch streams corresponds to a plurality of prefetch requests.