Patent ID: 9047939
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A method for operating a circuit having a plurality of resistive memory devices, the method comprising: providing an enable signal on a first global word line coupled to at least a first selector device and to a second selector device; coupling a first source line to a first plurality of resistive memory devices from the plurality of resistive memory devices with the first selector device in response to the enable signal on the first global word line; coupling the first source line to a second plurality of resistive memory devices from the plurality of resistive memory devices with the second selector device in response to the enable signal on the first global word line; coupling the first source line to ground; receiving a first address associated with the first plurality of resistive memory devices to read; coupling a sense amp unit to the first plurality of resistive memory devices via a first plurality of bit lines in response to the first address; applying with the sense amp unit, a read voltage to the first plurality of resistive memory devices wherein each resistive memory device from the first plurality of resistive memory devices provides an output signal in response to a respective resistive state thereof, in response to the read voltage and in response to the ground; and sensing with the sense amp unit, in parallel, the output signal provided by each resistive memory device in the first plurality of resistive memory devices to determine a respective state for each resistive memory device in the first plurality resistive memory devices.