Patent ID: 7774533
Filing Date: 2010-08-10
Classification: G06F,H05K

Abstract:
1. A system having a memory device comprising: connector pins including data pins, a command pin, and a power signal pin; a first register that stores own operation mode information of the memory device, the own operation mode information including bus width information which indicates one of first and second operation modes such that, in the first operation mode, the system receives data using one of the data pins and, in the second mode, the system receives data using four of the data pins; a controller that outputs the operation mode information to one of the connector pins in response to a first command; and a second register that stores operation voltage information concerning an operation voltage of the system; wherein said controller provides the operation voltage information to the command pin to transmit the operation voltage information in response to a second command, and wherein said controller sets the operation mode of the system into one of the first and second operation modes stored in the first register in response to a third command received via a command pin.