Patent ID: 7173388
Filing Date: 2007-02-06
Classification: H02P

Abstract:
1. A drive control device for a brushless motor comprising: a rectifying circuit with an input connected to a power source and an output connected to one terminal of each of a first and a second inductors of the brushless motor; a regulating circuit with an input connected to the output of the rectifying circuit; a drive control circuit with an input connected to an output of the regulating circuit and an output connected to the other terminal of each of the first and the second inductor; and a protection circuit connected between the output of the rectifying circuit and ground, wherein the drive control circuit includes a first and a second integrated chips, a first and a second complementary metal oxide semiconductors (CMOS), a first, a second, a third, a fourth, a fifth and a sixth resistors and a first, a second and a third capacitors, the first resistor has one terminal connected to the output of the rectifying circuit and the other terminal connected to a first pin of the first integrated chip, the second resistor is connected between a third pin of the first integrated chip and the ground in series, the first integrated chip has a second and a fourth pins connected to two input pins of the second integrated chip, respectively, the second integrated chip has a Vcc pin connected to the output of the regulating circuit and a GND pin directly connected to the ground, the first capacitor is connected between a CT pin of the second integrated chip and the ground in series, the fourth resistor is connected between the first output pin of the second integrated chip and a gate of the first CMOS in series, the fifth resistor and the second capacitor connected in parallel are connected between the gate of the first CMOS and ground in series, a drain of the first CMOS is connected to the other terminal of the first inductor, and a source of the first CMOS is connected to the ground, the third resistor is connected between the second output pin of the second integrated chip and a gate of the second CMOS in series, the sixth resistor and the first capacitor connected in parallel are connected between the gate of the second CMOS and the ground in series, a drain of the second CMOS is connected to the other terminal of the second inductor, and a source of the second CMOS is connected to the ground.