Patent ID: 6867499
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. An electronic component comprising: an electronic device package formed from an integral silicon wafer having a recess, the recess including a single conductive region, the wafer and the conductive region conductively coupled so as to be at substantially the same electrical potential; a bare die electronic device having a top, a bottom, sides, and a plurality of terminals, including a non-terminal, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, and wherein the non-top terminal is electrically coupled to the conductive region by the conductive bonding material; and a dielectric material disposed so as to form a planar surface over the recess that is level with or higher than the top of the device, the dielectric material filling the recess not occupied by the device and conductive bonding material.