Patent ID: 6309919
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method for fabricating a vertical transistor, comprising the steps of:providing a substrate having a surface;forming a semiconductor layer on the substrate to be of a first conductivity type, a top surface of the semiconductor layer being opposite a bottom surface of the layer opposed to the substrate;implanting the semiconductor layer to form a heavily doped region such that a boundary of the heavily doped region is spaced from the top surface of the semiconductor layer, the heavily doped region formed to be of a second conductivity type;after the step of forming the heavily doped region, opening a trench in the semiconductor layer from the top surface of the semiconductor layer at least to the boundary of the heavily doped region;responsive to said step of opening a trench, defining a channel region in the semiconductor layer, the channel region being of the first conductivity type opposite said second conductivity type;forming a gate dielectric layer on sidewalls of said trench;forming a conductive gate in the trench to be adjacent the gate dielectric layer;implanting a source connector region in the semiconductor layer to be of the second conductivity type and to extend from the top surface of the semiconductor layer to the boundary of the heavily doped region, the source connector region disposed remotely from the channel region; andforming a drain region to be of the second conductivity type and to be at the surface of the semiconductor layer and spaced from the boundary of the heavily doped region and the source connector region, the drain region disposed insulatively adjacent the conductive gate and disposed to adjoin the channel region.