Patent ID: 6085413
Filing Date: 2000-07-11
Classification: H01L,H05K,Y10T

Abstract:
A method of fabricating a monolithic multilayer electrical interconnection device, comprising the steps of:depositing an insulating undercoat layer over a substrate of conducting material, said insulating undercoat layer including a void;depositing a first conducting layer including conductive traces over said substrate by thermal spraying a conductive material through a first mask having a first pattern;depositing a first insulating layer over said first conducting layer by thermal spraying an insulative material through a second mask having a second pattern such that selected regions of said first conducting layer are not covered by said first insulating layer; anddepositing a second conducting layer over said first insulating layer and said first conducting layer by thermal spraying through a third mask having a third pattern such that said second conducting layer includes at least one of said selected regions;wherein at least one conducting layer connects with said substrate through said void;whereby said selected regions provide interconnects between conducting layers through direct metallurgical bonding.