Patent ID: 6856529
Filing Date: 2005-02-15
Classification: G11C

Abstract:
1. A content addressable memory (CAM) device, comprising: a plurality of CAM arrays, each having a plurality of CAM cells; a plurality of first priority encoders, each one of said first priority encoders being coupled to a respective one of said plurality of CAM arrays; at least one subsequent priority encoder coupled to said plurality of first priority encoders, said subsequent priority encoder receiving outputs from said plurality of first priority encoders and selecting one of said outputs; and a control circuit coupled to said plurality of CAM arrays, said plurality of first priority encoders, and said at least one subsequent priority encoder, wherein said control circuit operates said plurality of CAM arrays so that at least a first one of said plurality of CAM arrays is operated in accordance with a first clock domain and at least a second one of said plurality of CAM arrays is operated in accordance with a second different clock domain.