Patent ID: 6490192
Filing Date: 2002-12-03
Classification: G11C

Abstract:
A magnetoresistive memory, comprising:a common word line voltage source outputting a common word line voltage; bit lines; word lines crossing said bit lines; a memory cell array having a multiplicity of memory cells with cell resistors connected to said bit lines and said word lines, said memory cell array further having a multiplicity of reference cells with reference cell resistors connected to said bit lines and said word lines, said memory cell array configured such that for testing a respective cell resistor in each case two of said reference cell resistors nearest said respective cell resistor and said reference cell are simultaneously connected to the common word line voltage, a respective bit line connected to said respective cell resistor is connected to the common word line voltage through said respective cell resistor and correspondingly at a same time two of said bit lines each respectively connected to one of said two reference cell resistors are connected to the word line voltage through said two reference cell resistors; a first feedback amplifier together with said two reference cell resistors forming a summing amplifier having an output; a second feedback amplifier together with said respective cell resistor forming an amplifier having an output and an equivalent gain as said summing amplifier; and a comparator having a first input connected to said output of said summing amplifier and a second input connected to said output of said amplifier, said comparator having an output supplying an evaluation signal dependent on said respective cell resistor.