Patent ID: 7330385
Filing Date: 2008-02-12
Classification: G11C

Abstract:
1. An integrated semiconductor memory device that adapts evaluation performance of sense amplifiers, the device comprising: an output terminal to output a data item; a plurality of memory cells, each memory cell being configured to have a cell voltage depending on a memory state; a plurality of bit line pairs, each bit line pair comprising a first bit line and a second bit line; a plurality of sense amplifiers, each sense amplifier being configured to evaluate the cell voltage of one of the memory cells, wherein: a first controllable voltage generator to generate a first precharging voltage; and a second controllable voltage generator to generate a second precharging voltage, wherein a level of the first precharging voltage differs from a level of the second precharging voltage; wherein the first precharging voltage is supplied to the bit lines of the first bit line pair, and the second precharging voltage is supplied to the bit lines of the second bit line pair.