Patent ID: 6917561
Filing Date: 2005-07-12
Classification: G11C

Abstract:
1. A memory controller for aligning write data and a clock strobe signal provided to a memory device, the memory controller comprising: a local clock input providing a local clock signal; a delay line coupled to the local clock input and providing as an output a delayed local clock signal; a first latch circuit receiving data to be written to the memory device as an input and having an output coupled to a data input of the memory device, the first latch circuit being clocked by a first one of the local clock signal and the delayed local clock signal and providing in response the write data to the data input of the memory device; and a clock strobe generating circuit which is clocked by a second one of the local clock signal and the delayed local clock signal, the clock strobe generating circuit having an output coupled to a clock strobe input of the memory device and providing the clock strobe signal to the memory device.