Patent ID: 6434582
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A cosine computation device comprising:an input bus comprising a plurality of input lines, wherein the input bus is configured to receive an input value; a logical processing unit coupled to the input bus, wherein the logical processing unit includes a first plurality of gates coupled to the input bus, wherein each gate of the first plurality of gates couples to two or more of the input lines, wherein the logical processing unit comprises N output buses, wherein at least one of said output buses includes (a) at least one output line which is coupled to an output of one of said first plurality of gates and (b) at least one output line which is coupled to one of the input lines of the input bus, wherein N is greater than or equal to two; an addition unit coupled to the N output buses of the logical processing unit, wherein the addition unit is configured to perform an addition of N binary numbers corresponding to the N output buses and generate a resultant number which corresponds to a cosine of the input value.