Patent ID: 8228111
Filing Date: 2012-07-24
Classification: H03F

Abstract:
1. A circuit, comprising: an H-bridge arrangement of field effect transistors comprising: a first bias network comprising a first resistive element, a second resistive element and a first switching element, the first resistive element being coupled between the power supply node and a third terminal of the first high-side transistor, the second resistive element being coupled between the third terminal of the first high-side transistor and a first terminal of the first switching element, and a second terminal of the first switching element being coupled to the ground node, the first switching element capable of selectively providing a DC path from the first terminal of the first switching element to the ground node and substantially no DC path from the first terminal of the first switching element to the ground node, and the first switching element being different from the first low-side transistor and from the second low-side transistor; and a second bias network comprising a third resistive element, a fourth resistive element and second switching element, the third resistive element being coupled between the power supply node and a third terminal of the second high-side transistor, the fourth resistive element being coupled between the third terminal of the second high-side transistor and a first terminal of the second switching element, and a second terminal of the first switching element being coupled to the ground node, the second switching element capable of selectively providing a DC path from the first terminal of the second switching element to the ground node and substantially no DC path from the first terminal of the second switching element to the ground node, and the second switching element being different from the first low-side transistor and from the second low-side transistor, the third terminal of the first switching element being coupled to a first control signal source, the first control signal source being capable of selectively switching the first switching element off so that there is substantially no DC path through the first switching element from the first terminal of the first switching element to the ground node.