Patent ID: 6492734
Filing Date: 2002-12-10
Classification: H01L,Y10S

Abstract:
A semiconductor device, comprising:a semiconductor substrate including a plurality of semiconductor elements; a first insulating layer formed above said semiconductor substrate, said first insulating layer having a surface; a damascene wiring depression formed in said surface of said first insulating layer beginning at said surface, said depression having a first width; an aligning groove formed in said surface of said first insulating layer beginning at said surface, said aligning groove having a second width larger than said first width; a damascene wiring formed by filling a substance in said damascene wiring depression, an aligning wiring pattern formed of a wiring layer same as said damascene wiring, in said aligning groove, said aligning wiring pattern having a first stepped surface, a surface wiring pattern formed on a surface of said first insulating layer, said surface wiring pattern being connected to said damascene wiring; and a first aligning surface wiring pattern formed of a wiring layer same as said surface wiring pattern on said aligning wiring pattern, said first aligning surface wiring pattern having a second stepped surface above the first stepped surface.