Patent ID: 6413813
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method for producing a DRAM structure, comprising:forming a plurality of transistors on a silicon wafer substrate; depositing an insulating layer; forming a plurality of bitline contacts in the insulating layer; depositing a lower-plate; depositing an oxide; removing the oxide and the planar part of the lower-plate covering the insulating layer; removing the oxide outside each bitline contact and leaving the oxide inside of each bitline contact to provide an oxide plug; depositing a high dielectric constant substance; depositing an upper-plate to form a planar surface; removing a portion of the upper-plate above each oxide plug to form a plurality of openings in the upper-plate, each opening being broader than the respective bitline contact at an upper portion of the lower-plate adjacent to the bitline contact so as to electrically isolate the bitline contacts from the upper-plate; and removing the oxide plug from each bitline contact.