Patent ID: 6069391
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A semiconductor device including a circuit configuration formed on a semiconductor substrate, comprising:a boosting circuit for boosting an external power supply voltage to a plus voltage VH and a minus voltage VL; anda detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage VH and the minus voltage VL boosted by said boosting circuit are respectfully connected to said resistor to detect a potential at a prescribed point of said resistor so as to verify whether or not said boosting circuit has generated a desired potential, wherein:the semiconductor substrate is of a first conductivity type, further comprising:a well region having the first conductivity type formed in said substrate, said well region having a lower surface and a side, and another well region having a second conductivity type formed in said substrate and surrounding said lower surface and said side of the first-conductivity-type well region, andsaid impurity diffused layer constituting said resistor is formed to have the second conductivity type within said well region having the first conductivity type, wherein:the plus boosted potential VH supplied by said boosting circuit is connected to one end of the impurity diffused layer of said resistor, and the minus boosted potential VL is connected to the other end of the impurity diffused layer of said resistor; andsaid device is characterized that when said detecting circuit operates,a fixed potential Va is applied to said well region having the first conductivity type, a fixed potential Vb is applied to said well region having the second conductivity type, and a fixed potential Vc is applied to said semiconductor substrate, andsaid fixed potentials Va, Vb, and Vc are set so that at the respective junctions between said impurity diffused layer of said resistor and said well region having the first conductivity type, between said well regions having the first and second conductivity types, and between said well region having the second conductivity type and said semiconductor substrate, the potential difference between each of said regions forming a respective junction is equal to or lower than the forward and reverse junction withstand voltages.