Patent ID: 6762099
Filing Date: 2004-07-13
Classification: H01L,Y10S

Abstract:
A two-stage method for fabricating buried strap out-diffusions of vertical transistors, comprising the steps of:providing a semiconductor substrate having thereon a deep trench; depositing a first conductive layer at bottom of the deep trench; forming a collar oxide layer on sidewalls of the deep trench; depositing a second conductive layer atop the first conductive layer within the deep trench; selectively etching back the collar oxide layer; depositing a third conductive layer having a first thickness atop the second conductive layer; depositing a trench top oxide (TTO) layer having a second thickness on the third conductive layer; forming a spacer on each sidewall of the deep trench; etching away a portion of the TTO oxide layer to form a recess underneath the spacer, the recess exposing the semiconductor substrate in the deep trench; performing a diffusion process to dope dopants into the exposed semiconductor substrate by way of the recess so as to form a first doped region; stripping the spacer; and performing a thermal process to out-diffuse dopants in the second conductive layer to the semiconductor substrate through the third conductive layer so as to form a second doped region that merges with the first doped region, wherein the first doped region and the second doped region constitute a buried strap out-diffusion.