Patent ID: 7167971
Filing Date: 2007-01-23
Classification: G06F

Abstract:
1. A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, wherein the co-processor has been configured to implement an instruction set comprising one or more co-processor instructions, the method comprising the steps of: issuing a co-processor instruction to the co-processor; determining whether the instruction is mapped to the co-processor instruction set; for an instruction not mapped to the co-processor instruction set, evaluating the need for reconfiguring the co-processor; reconfiguring the instruction set of the co-processor when the evaluation indicates said reconfiguring the co-processor is needed; and executing the instruction, wherein said reconfiguring the instruction set of the co-processor comprises the steps of: raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the unmapped instruction, adding the unmapped instruction to the co-processor instruction set, if there is enough space for said instruction, and clearing the stall signal.