Patent ID: 9021332
Filing Date: 2015-04-28
Classification: G06F,G11C,H03M

Abstract:
1. An apparatus comprising: a circuit configured to receive a codeword from a memory, wherein (i) the memory is nonvolatile and (ii) the codeword has one or more errors; and one or more processors configured to generate read data by a soft-decision decode of the codeword, wherein (A) the soft-decision decode uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the soft-decision decode to converge using the first procedure and (iii) a third procedure in response to another failure of the soft-decision decode to converge using the second procedure and (B) at least one of (i) the second procedure adjusts the codeword with an inter-cell interference cancellation technique and (ii) the third procedure dampens the parameters used in the soft-decision decode.