Patent ID: 6339343
Filing Date: 2002-01-15
Classification: G11C

Abstract:
A semiconductor circuit, comprising:an input/output pad for at least one of input and output of data; a data input buffer for receiving data from the input/output pad; a data output buffer for output of the data to the input/output pad; and, a controller that provides a control signal to control the data input and output buffers such that only one of the data input buffer and the data output buffer is enabled during a prescribed operation, wherein the data input buffer comprises, a first transistor having first and second electrodes and a control electrode, and second, third and fourth transistors, each having first and second electrodes and a control electrode, wherein the first and second electrodes of the second and third transistors, respectively, are commonly coupled to the first electrode of the first transistor, wherein the first and second electrodes of the third and fourth transistors, respectively, are commonly coupled, and wherein the control electrode of the first and fourth transistors is coupled to the input/output pad to receive the data, and the control electrode of the second and third transistors is coupled for receiving the control signal.