Patent ID: 6751137
Filing Date: 2004-06-15
Classification: G11C

Abstract:
A column repair circuit in a non-volatile ferroelectric memory having main columns and redundancy columns, comprising:a data input/output buffer part for data input/output between the non-volatile ferroelectric memory and an external circuit; a failed column coding part for controlling the main columns and the redundancy columns and connected in response to a failed column address signal to one of main input/output lines in the input/output buffer part and redundancy input/output lines; a repair column adjusting circuit part including a plurality of logical circuits and a plurality of switch blocks, wherein the plurality of logical circuits providing a plurality of redundancy mode control signals in response to a plurality of failed column address enabling signals and a mode control signal, and the plurality of switch blocks selectively connecting a main input/output line and an input/output line of the data input/output buffer part; a data bus amplifying part for amplifying data between the main input/output lines and the main columns to control read/write operation; and a redundancy data bus amplifying part for amplifying data between the redundancy input/output lines and the redundancy columns in response to the redundancy mode control signal.