Patent ID: 8962390
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method for manufacturing a chip packaging structure, comprising: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; removing a part of the adhesion layer to form at least one through hole in the adhesion layer, so that an upper surface of the conductive trace layer is partly exposed through the through hole; disposing at least one metal bump in the through hole to be in contact with the conductive trace layer after the formation of the through hole; placing a chip on the adhesion layer to be in contact with the metal bump being disposed in the through hole; electrically connecting the chip to the conductive trace layer through the metal bump in the through hole; placing a transfer element on top of the chip; electrically connecting the chip and the transfer element; utilizing an encapsulation to encapsulate the chip, the adhesion layer, the conductive trace layer and the transfer element; and removing the entire protection layer.