Patent ID: 7791210
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A semiconductor integrated circuit (IC) package comprising: a substrate having a first surface and a second surface located on each side of a core portion with the core portion including a stripline having a signal plane and a pair of reference planes each arranged on different layers of the substrate core, the pair of reference planes including a power plane, and a ground plane each defined by a planar layer of conductive material arranged such that the signal plane is positioned between the pair of reference planes of the stripline, the signal plane having an electrical signal trace extending a first length across the signal plane and arranged in between the pair of reference planes such that one of the reference planes extends contiguously above a substantial portion of the first length of the signal trace and such that another of the reference planes extends contiguously under a substantial portion of the first length of the signal trace enabling the plurality of electrical signal traces to be shielded by the ground plane and the power plane of the stripline; an integrated circuit die mounted to a first surface of the substrate; and a discrete non-active electrical component mounted on the first surface of the substrate so that the integrated circuit die is electrically connected with the discrete non-active electrical component through the electrical signal trace of the package and wherein the discrete non-active electrical component is also electrically connected with an I/O (input/output) solder ball arranged on the second surface of the substrate said connection facilitated by a conductive via that passes through the core portion of the substrate.