Patent ID: 6812103
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device including a gate electrode stack and doped source and drain regions disposed on each side of a channel region located under the gate electrode stack over a substrate, comprising:etching the doped source and drain regions to create recessed regions in the substrate adjacent to, and recessed with respect to the gate electrode stack and the channel region, and to expose sidewalls in the doped source and drain regions; forming an oxide layer over the exposed sidewalls in the doped source and drain regions and over the recessed regions in the substrate; and removing the formed oxide layer to expose the substrate in the recessed regions of the source and drain regions and to leave a portion of the formed oxide layer on the exposed sidewalls of the source and drain to form a dielectric spacer and to surround a channel region between the source and drain regions.