Patent ID: 6483141
Filing Date: 2002-11-19
Classification: H01L

Abstract:
Semiconductor memory device comprising,a semiconductor substrate provided with an impurity diffusion layer in a prescribed place in the surface region; a first insulator layer provided on the semiconductor substrate; a second insulator layer formed on top of the first insulator layer, said second insulator layer being of a different material than the first insulator layer; a contact hole provided in the first and second insulator layers in a position on the impurity diffusion layer; a contact plug that buries the contact hole and that is provided projecting upward above the first and second insulator layers and in contact with the second insulator layer, the contact plug having a top surface; a memory capacitor lower electrode that is provided on the second insulator layer and connected to the contact plug, at least a portion of said memory capacitor lower electrode is in direct contact with said contact plug top surface; a capacitor dielectric film provided on the surface of the lower electrode; and a memory capacitor upper electrode provided on the capacitor dielectric film.