Patent ID: 7924592
Filing Date: 2011-04-12
Classification: G11C,H01L

Abstract:
1. A semiconductor package comprising: a package substrate having a plurality of first and second connection terminals; a first semiconductor chip comprising an input/output circuit for sending and receiving signals to and from an outside of the semiconductor package; a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip comprising a memory cell region for storing data; a plurality of first through vias formed through the first semiconductor chip, the first through vias connecting the input/output circuit to the plurality of first connection terminals; a plurality of second through vias formed through the second semiconductor chip, the second through vias connecting the memory cell region to the input/output circuit; a plurality of third through vias formed through the first semiconductor chip, connected to the second connection terminals; and a plurality of fourth through vias formed through the second semiconductor chip, the fourth through vias being connected to the third through vias for providing a power signal and a ground signal to at least the second semiconductor chip, wherein the plurality of third through vias are dedicated to at least the second semiconductor chip and not electrically connected to the remainder of the first semiconductor chip to provide the power signal and the ground signal to the first semiconductor chip.