Patent ID: 9099364
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A MPS-C2 semiconductor device comprising: a chip having an active surface and a plurality of bonding pads on the active surface; a wafer-level packaging layer formed on the active surface, wherein the bonding pads are reentrant from the wafer-level packaging layer; a patterned UBM layer including a plurality of UBM pads and at least a first UBM island, wherein the UBM pads are respectively disposed on the bonding pads and the first UBM island is disposed on the wafer-level packaging layer far away from the bonding pads, wherein a first island area of the first UBM island is at least four times greater than the unit area of the UBM pads on the corresponding bonding pads; a plurality of I/O pillars disposed on the corresponding UBM pads in a one-to-one relationship, wherein each I/O pillar has a first top jointing surface; and a plurality of first supporting pillars disposed on the first UBM island in a many-to-one relationship, wherein there are two or more first supporting pillars disposed on each first UBM island, and each first supporting pillar has a second top jointing surface, wherein a second unit footprint of the first supporting pillars on the first UBM island is smaller than a first unit footprint of the I/O pillars on the UBM pads to compensate the jointing height difference between the second top jointing surfaces and the first top jointing surfaces.