Patent ID: 8247305
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A method of forming a capacitor structure for a dynamic random access memory integrated circuit, the method comprising: providing a semiconductor substrate; forming a pad oxide layer overlying the semiconductor substrate; forming a nitride layer overlying the pad oxide layer; forming an interlayer dielectric layer overlying the nitride layer; forming a polysilicon mask layer overlying the interlayer dielectric layer; patterning the polysilicon mask layer to form an opening therein for a trench structure; applying a first reactive ion etching process to form a first trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer; maintaining the first reactive ion etching process to etch through a portion of the nitride layer and through a portion of the pad oxide layer; ceasing the first reactive ion etching process when a surface region of the semiconductor substrate has been exposed; forming an oxide layer overlying the surface region of the semiconductor substrate to protect the surface region of the semiconductor substrate; removing the patterned polysilicon mask layer while protecting the surface region of the semiconductor substrate using the oxide layer; applying a second reactive ion etching process to continue to form a second trench region by removing the oxide layer and removing a portion of the semiconductor substrate to a predetermined depth in the semiconductor substrate; forming a lower electrode plate overlying at least a portion of the first trench region and the entire second trench region; forming a dielectric layer overlying the lower electrode plate; and forming an upper electrode plate to complete the capacitor structure.