Patent ID: 6580655
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A pre-charge circuit for a memory device having a sense amplifier shared between a right bank during row operations to the right bank and a left bank during row operations to the left bank, the pre-charge circuit comprising:a right bank isolation transistor pair connected between the sense amplifier and the right bank; a left bank isolation transistor pair connected between the sense amplifier and the left bank; a right bank isolation control line having an on state for turning on the right bank isolation transistor pair to connect the sense amplifier to the right bank, and an off state for turning off the right bank isolation transistor pair to disconnect the sense amplifier from the right bank; a left bank isolation control line having an on state for turning on the left bank isolation transistor pair to connect the sense amplifier to the left bank, and an off state for turning off the left bank isolation transistor pair to disconnect the sense amplifier from the left bank; and a flip-flop switchable between a right bank state and a left bank state, the flip-flop including: a right bank isolation output connected to the right bank isolation control line, the right bank isolation output being in the on state and turning on the right bank isolation transistor pair when the flip-flop is in the right bank state and the right bank isolation output being in the off state and turning off the right bank isolation transistor pair when the flip-flop is in the left bank state; and a left bank isolation output connected to the left bank isolation control line, the left bank isolation output being in the on state and turning on the left bank isolation transistor pair when the flip-flop is in the left bank state and the left bank isolation output being in the off state and turning off the left bank isolation transistor pair when the flip-flop is in the right bank state; the memory device switching the flip-flop to the right bank state prior to right bank row operations and to the left bank state prior to left bank row operations, the flip-flop remaining in the right bank state to pre-charge the sense amplifier from the right bank after right bank row operations and remaining in the left bank state to pro-charge the sense amplifier from the left bank after left bank row operations, wherein the flip-flop maintains the state of said isolation transistor pairs while said left and right banks select signals are low, allowing pre-charging the bit lines in the absence of the bank select signals.