Patent ID: 8751723
Filing Date: 2014-06-10
Classification: G06F,G09G

Abstract:
1. A memory access control device which includes a memory that stores data and controls access to said memory, comprising: a plurality of groups of said memory; a control unit that divides and stores said data in different memory areas of said plurality of groups of the memory distinguished based on one or more predetermined bits of an access address to said plurality of groups of the memory; wherein said data stored in said different memory areas of said plurality of groups of the memory arc accessed simultaneously in the same clock cycle of access to said memory, wherein the one or more predetermined bits of said access address to said plurality of groups of the memory are controlled independently for each of said groups, and wherein the part of the access address to said plurality of groups of the memory other than said one or more predetermined bits controlled independently for each of said groups is common for said plurality of groups, wherein said data comprises two-dimensional unit data; and an access mode selection unit configured to select at least two modes from: a mode to access two horizontally consecutive unit data at a time, a mode to access two vertically consecutive unit data at a time, and a mode to access two unit data on vertically alternate lines at a time.