Patent ID: 8913615
Filing Date: 2014-12-16
Classification: H04L

Abstract:
1. A shared network interface controller (NIC) within the memory maps of a plurality of operating system domains (OSDs), for interfacing the plurality of operating system domains to a network, the controller comprising: a bus interface, for interfacing the controller to the plurality of operating system domains via a load store-bus, such that the shared network interface controller is within the memory maps of the plurality of operating system domains; transceiver logic, for interfacing the controller to the network; a processor configured to control transfer of data packets between the bus interface and the transceiver logic; packet replication logic, coupled to said bus interface, for detecting whether packets received via the bus interface from a first one of the plurality of operating system domains is destined for a second one of the plurality of operating system domains, and if said packets are destined for said second one of the plurality of operating system domains, said logic causing said packets to be transferred to said second one of the plurality of operating system domains; and control status registers, wherein each control status register is within a memory map of one or more of the operating system domains interfaced to the bus interface, wherein the shared network interface controller includes the control status registers for each of the plurality of operating system domains, and wherein the load store-bus comprises a PCI-Express bus.