Patent ID: 7350018
Filing Date: 2008-03-25
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: at least one primary memory of a type required to be refreshed and having a plurality of memory locations; a secondary memory of a type not required to be refreshed, the secondary memory coupled to the at least one primary memory; and control logic coupled to the at least one primary memory and the secondary memory, the control logic operable to refresh each of the plurality of memory locations of the at least one primary memory one at a time, the control logic operable to write data to the secondary memory when the data is directed to a first location of the plurality of memory locations of the at least one primary memory during a time the first location is being refreshed, and the control logic further operable to transfer the data that was directed to the first location of the at least one primary memory from the secondary memory to the first location of the at least one primary memory after the first location of the at least one primary memory has been refreshed.