Patent ID: 6345005
Filing Date: 2002-02-05
Classification: G11C

Abstract:
An integrated circuit comprising:a D flip-flop receiving m-bit write data and a clock signal, causing the m-bit data latched by the clock signal to branch to n individual signal lines and outputting the resultant (mÃ—n)-bit data; and a plurality of memory circuits provided with a plurality of memory blocks including a recovery memory block and configured to input and output (x+1)-bit data simultaneously; and a write control circuit receiving, m-bit parallel, the (mÃ—n)-bit data output from the D flip-flop, receiving a q-bit data selection signal and writing, in accordance with a binary value indicated by the q-bit data selection signal, the output data from the D flip flop to the plurality of memory circuits in units of integral multiplex of (x+1) bits in a total of 2q operations, where m, n, x, and q indicate positive integers, (x+1)>m and n>2q.