Patent ID: 7737472
Filing Date: 2010-06-15
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a circuit block including a plurality of standard cell rows arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction, wherein each of the standard cell rows includes an N well and a P region extending in the horizontal direction and adjacent to each other in the vertical direction, each of the standard cells has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region, in the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row, the first and second standard cell rows share the P region, and the second and third standard cell rows share the N well, in at least one of the standard cell rows, a distance from a PMOS transistor located at least one end thereof to an end closer to the PMOS transistor in the horizontal direction of the N well is greater than or equal to a shared-N well width which is a width in the vertical direction of the N well shared by the second and third standard cell rows.