Patent ID: 6456165
Filing Date: 2002-09-24
Classification: H03L

Abstract:
A phase-locked loop (PLL) device comprising:a main charge pump,; a phase error control charge pump that is only active when a phase error of said PLL device exceeds a user-defined value; a user-defined circuit coupled to said phase error control charge pump for determining a phase error of said PLL device and activating said phase error control charge pump when said phase error exceeds said user-defined value; a phase comparator, coupled to said main charge pump, said auxiliary charge pump, and said user-defined circuit, for providing a fist and second pulse, wherein said phase error is determined based on said first and second pulse; a filter, coupled to said phase error control charge pump and said main charge pump, said phase error control charge pump removing charge from said filter only when said phase error exceeds a user-defined value; and an oscillator, coupled to said filter and said auxiliary charge pump, for outputting an output signal; wherein said user-defined circuit receives an input signal of said PLL circuit and said output signal from said oscillator for creating user-settable pulse width, wherein said user-defined circuit includes: a first delay circuit, coupled to said input signal; a second delay circuit, coupled to said output signal; a first XOR gate, coupled to said first delay circuit and receiving said first pulse from said phase comparator; a second XOR gate, coupled to said second delay circuit and receiving said second pulse from said phase comparator; a first AND gate, coupled to said first XOR gate and receiving said fist pulse; and a second AND gate, coupled to said second XOR gate and receiving said second pulse; wherein outputs of said first and second AND gate are inputted into said phase error control charge pump.