Patent ID: 9025965
Filing Date: 2015-05-05
Classification: H03L

Abstract:
1. A digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digital controlled oscillator (DCO), comprising: a DCO gain estimator to calculate a frequency gain of the DCO; and a DLF compensator to adjust a loop filter coefficient of the DLF, wherein the digital phase locked loop has a constant jitter characteristic even when an operating condition varies according to a phase, voltage, temperature (PVT) change, and the DCO is designed to have only a single variable that affects a frequency gain according to the PVT change, wherein the DCO is in a structure in which a plurality of delay cell modules are connected in series and each of the delay cell modules is configured to connect delay cells, having the same input node and having a different delay time, in parallel to each other and add up the delay cells and then transfer an addition result to a delay cell module of a subsequent end.