Patent ID: 7581131
Filing Date: 2009-08-25
Classification: G06F

Abstract:
1. A method for balancing clock trees in a multi-voltage synchronous digital environment, comprising: generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain, the first mirrored clock signal generated in the second voltage domain using an original clock signal; generating a second source clock signal in the second voltage domain based on a second mirrored clock signal in the first voltage domain, the second mirrored clock signal generated in the first voltage domain using the original clock signal; generating a first feedback signal based on the first source clock signal; generating a second feedback signal based on the second source clock signal; and adjusting at least one of a first delay and a second delay based on the first and second feedback signals, the first delay associated with the first source clock signal and the second delay associated with the second source clock signal.