Patent ID: 6444539
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method for producing at least one shallow trench isolation, said method comprising the steps of:(a) providing a semiconductor substrate member having a barrier oxide layer; (b) forming at least one pair of spaced apart first dielectric pads on said barrier oxide layer; (c) forming a silicon layer over said first dielectric pads and over said barrier oxide layer in regions between said first dielectric pads, said regions between said first dielectric pads comprising regions for forming said at least one shallow trench isolation; (d) forming a polysilicon layer over said silicon layer, said polysilicon layer forming a first U-shaped notch in said region delineated for forming said at least one shallow trench isolation and providing a first buffer region comprising an oxide and a polysilicon material adjacent said at least one pair of spaced apart first dielectric pads; (e) forming, by a polysilicon etching process, a wider, second U-shaped notch in said region delineated for forming said at least one shallow trench isolation, said second U-shaped notch having sloped sidewalls that form a second buffer region comprising tapering amounts of an oxide and a polysilicon material; and (f) forming a V-shaped isolation trench region into said semiconductor substrate member, said V-shaped isolation trench region being formed by etching the polysilicon material comprising sidewalls of said second U-shaped notch, by etching through said barrier oxide and into said semiconductor substrate member a predetermined depth.