Patent ID: 8934299
Filing Date: 2015-01-13
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor device comprising: a first wiring configured to supply a high power source potential and a low power source potential; a second wiring configured to supply the high power source potential; a third wiring configured to supply the high power source potential and the low power source potential; a first n-channel transistor, one of a source and a drain of which is electrically connected to the first wiring; a second n-channel transistor, a gate of which is electrically connected to the second wiring, one of a source and a drain of which is electrically connected to the third wiring, and the other of the source and the drain of which is electrically connected to a gate of the first n-channel transistor; and a node which is electrically connected to the other of the source and the drain of the first n-channel transistor, wherein the node is brought into a floating state by turning off the first n-channel transistor.