Patent ID: 7477546
Filing Date: 2009-01-13
Classification: G11C,H01L

Abstract:
1. A non-volatile memory system comprising: an array of non-volatile memory cells arranged in one or more rows and columns, wherein each of the non-volatile memory cells includes an access transistor having source/drain regions of a first conductivity type and a capacitor structure having a diffusion region of a second conductivity type, opposite the first conductivity type, wherein the access transistor and capacitor structure share a common floating gate, and wherein the access transistors in each row are fabricated in a dedicated well region of the second conductivity type; a first set of control lines, wherein each of the control lines in the first set is coupled to the source of each access transistor in a corresponding column; and a second set of control lines, wherein each of the control lines in the second set is coupled to the drain of each access transistor in a corresponding column.