Patent ID: 8937837
Filing Date: 2015-01-20
Classification: G11C

Abstract:
1. A method of erasing non-volatile storage system, comprising: creating a voltage differential between a bit line and a sense amplifier connected to the bit line as part of an erase process for a plurality of non-volatile memory elements in communication with the bit line, the sense amplifier includes a clamping device and a shield device, the clamping device is used as a voltage clamp for the bit line during a sensing operation, the shield device is positioned between the clamping device and the bit line, the shield device shields the sense amplifier from high bit line voltages, the sense amplifier further includes a node between the clamping device and the shield device; prior to creating the voltage differential between the bit line and the sense amplifier, and as part of the erase process, turning on the clamping device to allow charge to be communicated across the clamping device in order to charge up the node; subsequent to starting the creating of the voltage differential between the bit line and the sense amplifier, actively turning off the clamping device to prevent additional charge to be communicated across the clamping device to the node while the voltage differential between the bit line and the sense amplifier continues to persist; turning on the shield device to allow a portion of a charge on the bit line to be communicated across the shield device to charge up the node, thereby partially counteracting the voltage differential between the bit line and the sense amplifier; and erasing the plurality of non-volatile memory elements connected to the bit line while the node remains charged, as part of the erase process.