Patent ID: 9184095
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A method, comprising: forming a metal-containing electrode material layer so as to line sidewall and bottom surfaces of a gate opening formed in a gate electrode structure of a transistor of a semiconductor device; after forming said metal-containing electrode material layer, forming a contact opening so as to expose a contact area of at least one of a drain region and a source region of said transistor and a sidewall surface of a sidewall spacer positioned adjacent to said gate electrode structure, wherein forming said contact opening comprises selectively removing a portion of a first interlayer dielectric material with respect to at least said sidewall surface of said sidewall spacer, said contact opening being self-aligned with respect to at least said sidewall surface of said sidewall spacer; completely filling said contact opening and said gate opening with a contact metal during a same material deposition step, wherein said contact metal completely filling said contact opening and said gate opening is deposited on and in direct contact with said exposed contact area and said exposed sidewall surface of said sidewall spacer; removing excess material of said conductive material so as to form at least one contact bar, wherein said contact bar is self-aligned with respect to said sidewall spacer element; and forming a second interlayer dielectric material above said first interlayer dielectric material and said contact bar.