Patent ID: 6344675
Filing Date: 2002-02-05
Classification: H01L

Abstract:
An SOI-MOS field effect transistor comprising:a silicon substrate; a buried insulation layer provided on said silicon substrate; a silicon layer provided on said buried insulation layer so that said silicon layer is electrically isolated from said silicon substrate, said silicon layer having source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions, and said source region having a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region; a gate insulation film extending over said body portion and over inside portions of said source and drain regions in the vicinity of said body portion; a gate electrode on said gate insulation film so that said gate electrode is positioned over said body portion; a first side wall insulation film provided on a first side wall of said gate electrode and in the vicinity of said source region; a second side wall insulation film formed on a second side wall of said gate electrode and in the vicinity of said drain region; an inter-layer insulator extending over said silicon layers and said gate electrode wall as well as over said first and second side wall insulation films; a source contact layer provided in said inter-layer insulator and said source contact layer having a bottom portion which is in contact with said first low resistive region of said source region and also having a top portion which is connected to a first interconnection extending over said inter-layer insulator; and a drain contact layer provided in said inter-layer insulator and said drain contact layer having a bottom portion which is in contact with said second low resistive region of said drain region and also having a top portion which is connected to a second interconnection extending over said inter-layer insulator, wherein a distance of an inside edge portion of said first low resistive region from a first interface between said source region and said body portion is shorter than a distance of an inside portion of said second low resistive region from a second interface between said drain region and said body portion.