Patent ID: 7120043
Filing Date: 2006-10-10
Classification: G11C

Abstract:
1. A nonvolatile ferroelectric memory device comprising: a plurality of cell array blocks each comprising a dummy main bit line and a cell array having a hierarchical bit line architecture where a sensing voltage of a main bit line is induced depending on a sensing voltage of cell data transmitted to a sub bit line; a sensing voltage pull-up regulating unit configured to compare a voltage of the dummy main bit line with a sensing level, and to generate a sensing voltage pull-up signal for regulating pull-up voltages of the dummy main bit line and the main bit line, so as to set a pull-up voltage of the main bit line to a predetermined sensing level when a sensing operation starts; a plurality of sense amplifiers for sensing the cell data by comparing the sensing voltage of the main bit line with the sensing level when data are sensed to sense the cell data; a main amplifier unit for amplifying data sensed in the plurality of sense amplifiers and outputting the sensed data to a data buffer; and a data bus for connecting the plurality of sense amplifiers to the main amplifier unit and transmitting read or written data.