Patent ID: 6067651
Filing Date: 2000-05-23
Classification: G01R

Abstract:
A method for generating a compacted set of test sequences for testing an integrated circuit having a scan register containing a plurality of bits defining test inputs for the integrated circuit, the method comprising the steps of:(a) defining a list of faults for the integrated circuit;(b) generating a first test sequence that defines values for those inputs necessary to detect a target fault selected from the list of faults;(c) adding the first test sequence to a list of test sequences and marking the selected fault as detected;(d) generating an additional test sequence which defines values for those inputs necessary to detect a target fault selected from the list of faults, and other than one marked as detected;(e) determining whether the additional test sequence may be compacted with any test sequence in the list of test sequences, and if so, compacting the additional test sequence with a test sequence in the set of test sequences, and if not, adding the additional test sequence to the set of test sequences; and(f) repeating steps (d) through (e) until a compacted condition is reached.