Patent ID: 8289777
Filing Date: 2012-10-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells, each memory cell including a selection transistor and a memory transistor, the memory transistor coupled to the selection transistor and having a control gate; a plurality of selection gate lines coupled to a gate of the selection transistor of the plurality of memory cells; a plurality of control gate lines coupled to the control gate of the memory transistor of the plurality of memory cells; a plurality of source lines coupled to a source of the memory transistor of the plurality of memory cells; and a plurality of bit lines that intersect the plurality of selection gate lines and are coupled to the selection transistor of the plurality of memory cells, wherein a drain current flows from the source line in the memory transistor in a programming operation and the drain current flows to the source line in the memory transistor in a read operation.