Patent ID: 7477170
Filing Date: 2009-01-13
Classification: H03H

Abstract:
1. A sample rate converter system comprising: a numerically controlled oscillator (NCO) register for receiving a clock input at the desired output rate; a first summing circuit, responsive to a first factor to decrement said NCO register contents; a comparator for indicating when said decremented NCO register contents are at zero or below; and in response to the said decremented NCO register contents not being zero or below, presenting said decremented NCO register contents to the input of the said NCO register; a second summing circuit responsive to said decremented NCO register contents being zero or below to increment said decremented NCO register contents by a second factor and present it to the input of said NCO register; and a processor configured, in response to said decremented NCO register contents being zero or below, to fetch samples and interpolate them to produce a resultant sample value at the output rate, and in response to said contents not being zero or below to interpolate the previous sample to produce a resultant sample value.