Patent ID: 7655521
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor memory device, the method comprising: providing a semiconductor substrate having a cell region and a peripheral region, wherein the peripheral region includes a low voltage NMOS transistor (LVN) region and a high voltage NMOS transistor (HVN) region; forming a first insulating layer and a pad layer over the semiconductor substrate; removing the pad layer and the first insulating layer formed in the HVN region; forming a second insulating layer on the HVN region; removing the pad layer and the first insulating layer formed in the cell region; forming a tunnel insulating layer, a first charge trap layer, and an isolation mask layer over the semiconductor substrate of the cell region and the peripheral region; etching portions of the isolation mask layer, the first charge trap layer, the tunnel insulating layer, the pad layer, the second insulating layer and the semiconductor substrate to form trenches; forming an isolation layer to fill the trenches; exposing the first charge trap layer by removing the isolation mask layer formed in the cell region; forming a second charge trap layer on the exposed first charge trap layer and the isolation layer; and forming a blocking layer and a control gate over the semiconductor substrate in which the second charge trap layer is formed.