Patent ID: 6614494
Filing Date: 2003-09-02
Classification: G02F

Abstract:
An integrated thin film transistor substrate comprising:an insulated substrate; a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on said insulated substrate, each of said accumulated bus lines extending parallel to and between a pair of said gate bus lines; a plurality of auxiliary capacitance electrodes extending from said accumulated capacitance bus lines; a first insulated film provided on said gate and accumulated capacitance bus lines and said auxiliary capacitance electrodes; a plurality of thin film transistors, each of said gate bus lines electrically connecting at least two of said thin film transistors; a plurality of parallel drain bus lines provided substantially perpendicular to said gate and accumulated capacitance bus lines on said first insulated film, each of said drain bus lines electrically connecting at least two of said thin film transistors; a second insulated film provided on said thin film transistors and said drain bus lines, said second insulated film having an opening over each of said thin film transistors; a plurality of pixel electrodes provided on said second insulated film, each of said pixel electrodes being electrically connected to a corresponding one of said transistors via said opening; and at least one conductive layer formed on said second insulated film at first and second crossing regions where said drain bus lines cross said gate and said accumulated capacitance bus lines respectively.