Patent ID: 6831325
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A non-volatile memory transistor capable of storing two binary bits comprising:a semiconductor substrate having an active region with spaced apart source and drain regions in the active region; a first insulative layer disposed over the substrate; a polysilicon gate disposed over the insulative layer, the polysilicon gate having sidewalls; a pair of polysilicon upright spacers acting as charge storage regions spaced apart on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide; a second insulative layer covering the upright spacers and the polysilicon gate, thereby allowing the spacers to be electrically floating structures; a conductive layer over the second insulative layer and contacting the polysilicon gate through an opening in the second insulative layer, the conductive layer having a voltage supply associated therewith, thereby allowing the polysilicon gate to serve as a control gate; and timing means for applying voltage alternately to one of the source and drain regions and then the other whereby each of the upright spacers may be independently read or written in cooperation with the voltage applied to the conductive layer.