Patent ID: 8264028
Filing Date: 2012-09-11
Classification: G11C,H01L

Abstract:
1. A bandgap engineered, dielectric charge trapping non-volatile memory device, comprising: a semiconductor substrate including a channel region; a gate; and a data storage structure between the channel region and the gate, the data storage structure comprising a charge trapping layer which traps charge to establish a threshold voltage, and a multilayer tunneling dielectric structure between the channel region and the charge trapping layer, and an insulating layer between the charge trapping layer and the gate, the multilayer tunneling dielectric structure and the insulating layer being configured to enable hole tunneling from the channel region into the charge trapping layer and suppressing electron injection from the gate into the charge trapping layer in presence of an electric field across the data storage structure in an operating mode to lower the threshold voltage, and to enable electron tunneling from the channel region and blocking hole tunneling from the gate into the charge trapping layer in presence of an electric field across the data storage structure in an operating mode to raise the threshold voltage.