Patent ID: 6930339
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A ferroelectric memory comprising: a mounting base composed of any one of semiconductor, glasses, and plastics; a memory cell array disposed on the mounting base and layered as a memory cell array chip and including first signal electrodes and second signal electrodes which are disposed facing and perpendicular to each other, and a ferroelectric layer which is disposed between the first signal electrode and the second signal electrode, wherein regions of intersection between said first signal electrodes and said second signal electrodes that include said ferroelectric layer are in the form of a matrix for employment as memory cells; a peripheral circuit disposed on the mounting base and layered as a peripheral circuit chip and including MOS transistors for selecting the memory cells; wherein, in said memory cell array chip, said first signal electrodes undergo expitaxial growth on a (100) Si single crystal substrate via a buffer layer, the buffer layer including either a metal oxide MO (M=Mg, Ca, Sr, Ba) or a titanium nitride (TiN) having a NaCl structure; the first signal electrodes include either a conductive oxide having a perovskite structure (100)-oriented in a pseudo-cubic system or a metal platinum Pt that is (100)-oriented in a pseudo-cubic system; and said ferroelectric layer undergoes epitaxial growth on said first signal electrode, and the peripheral circuit and the memory cell array are formed on separate chips.