Patent ID: 6466221
Filing Date: 2002-10-15
Classification: G06F,G06T,G09G,G11C

Abstract:
A processing device connectable to a memory device with a mode register, comprising:a circuit; a setting circuit; and an interface circuit, wherein said circuit is capable of generating an access address for accessing said memory device and generating information for setting to said mode register in said memory device, wherein said interface circuit is capable of connecting to said memory device, controls outputting of a clock signal and address signals corresponding to said access address and inputting/outputting of control signals including a row address strobe signal and a column address strobe signal and data signals, wherein said setting circuit is capable of controlling setting of said information to said mode register in said memory device, wherein said circuit is capable of generating first information as said information when said processing device is in a first status, and wherein said interface circuit outputs a first state of said row address strobe signal, said first state of said column address strobe signal and said first information via said address signals in synchronism with said clock signal.