Patent ID: 6268281
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method of fabrication of an integrated circuit device comprising:providing a semiconductor substrate;depositing an interpoly oxide laminated layer overlying said semiconductor substrate wherein said interpoly oxide laminated layer comprises a first layer, a second layer, and a third layer and wherein said first layer, said second layer, and said third layer are not planarized after said depositing;etching a contact hole through said interpoly oxide laminated layer to the surface of said semiconductor substrate;depositing a polysilicon layer overlying said interpoly oxide laminated layer and completely filling said contact hole;polishing away said polysilicon layer to define only polysilicon remaining in said contact hole and thereby also polishing said interpoly oxide laminated layer sufficiently to flatten the top surface of said interpoly oxide laminated layer; andcompleting said fabrication of said integrated circuit device.