Patent ID: 7138311
Filing Date: 2006-11-21
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: providing a semiconductor substrate; forming a first well and a second well both of a first conductivity type in the semiconductor substrate, the first and second wells being discrete and spaced apart from each other; forming a punch-through stopper area in said first well; and forming a source area and a drain area in each of the first and second wells, wherein the first well has the source and drain areas formed over the punch-through stopper area to form a first lateral MOS transistor, the punch-through stopper area offering a punch-through voltage resistance between the source area and the drain area thereof, and wherein the second well has the respective source and drain areas forming a semiconductor element that does not require a punch-through stopper area in part or all of the area thereof, wherein the semiconductor element is a second lateral MOS transistor having a lower threshold voltage than the first lateral MOS transistor, and wherein the first and second lateral MOS transistors each include a channel area formed between the respective source and drain region areas, and the length of the channel area of the first lateral MOS transistor is smaller than the length of the channel area of the second lateral MOS transistor.