Patent ID: 6145055
Filing Date: 2000-11-07
Classification: G06F,G11C

Abstract:
A cache memory which employs plural-way set associative system and replaces data of a way specified by an algorithm for updating data based on previous reference record, comprising:reference history storage areas which are provided for each entry commonly to each way and updated according to said algorithm, indicate the previous reference record, and are referred to at the time of replacement so as to indicate a way in which the data is to be replaced; andrewrite inhibit flags which are provided corresponding to said reference history storage areas to inhibit rewrite of said reference history storage areas, wherein when a fault entry is found in the initial state at the time of power-on, a reference history storage area corresponding to the fault entry is rewritten by an instruction from outside so as not to instruct a way of the fault entry, a rewrite inhibit flag corresponding to the rewritten reference history storage area is set and when the reference history storage area corresponding to the fault entry is updated, it is controlled that the reference history storage area is not rewritten so as to instruct the way of the fault entry.