Patent ID: 6614814
Filing Date: 2003-09-02
Classification: H04L

Abstract:
A multiplexed signal demultiplexing device comprising;a reference clock pulse generating circuit for outputting a reference clock pulse having a predetermined reference frequency, a counting circuit for counting by synchronizing with the reference clock pulse outputted from the reference clock pulse generating circuit, and for outputting a count value obtained by counting, a multiplexing circuit for multiplexing one signal selected from a predetermined signal and the count value outputted from the counting circuit in order to generate a multiplexed one signal, a demultiplexing circuit for demultiplexing the multiplexed one signal generated by the multiplexing circuit in order to generate a demultiplexed signal, an arranging circuit for arranging the demultiplexed signal generated by the demultiplexing circuit, and an array controlling circuit for detecting the values of bits which are set at the bottoms of demultiplexed signals generated by demultiplexing multiplexed count values outputted from the multiplexing circuit in order in which the arranging circuit arranges the demultiplexed signals generated by demultiplexing the multiplexed count values, and for changing an array of the demultiplexed signal generated by demultiplexing the multiplexed count value with the demultiplexing circuit on the basis of a change of the detected values of bits which are set at the bottoms of the demultiplexed signals.