Patent ID: 6370138
Filing Date: 2002-04-09
Classification: H04L

Abstract:
In an asynchronous transfer mode (ATM) switching system for performing a frame relay service, including an ATM local switch (ALS), an ATM switch interface apparatus, 16 frame relay interface apparatuses (FRIA) for performing a channelized/unchannelized 4 DSI/E1 interface, a Q.922 core function, a frame-to-ATM cell conversion function, a network management hierarchy protocol process, an OAM and PVC state management function, and a frame relay/ATM interworking core function, a frame relay clock distribution apparatus (FCDA) for receiving a system clock from the ALS and generating a clock used for the ATM switch interface apparatus and the FRIA, a local link interface apparatus (LLIA) for providing a link interface function between the ATM switches, and a call connection control processor (CCCP) for performing a call processing function, the improvement comprising the ATM switch interface apparatus for frame relay network interworking comprising:an up stream cell flow interface comprising an up stream cell transmission request signal, a FIFO read enable signal, a read clock, and a 16 bit data bus; a first buffer connected to said upstream cell flow interface for receiving a cell inputted through the up stream cell flow interface and decreasing an effect of an external noise with respect to the cell inputted through the up stream cell flow interface; a cell bus receiving controller (CBRC) connected to a content address memory (CAM), a usage parameter control FIFO (UPC FIFO), and a processor, said CBRC including a data register for storing the cell inputted through the first buffer and a control register for enabling the processor to perform a registration, deletion and inquiry of a connection identifier, the CBRC performing an up stream cell transmission request signal checking operation and generating a FIFO read enable signal; a UPC connected to the UPC FIFO, the processor and UPC memories for checking a user cell traffic with respect to the cell stored in the UPC FIFO and storing a control data and a statistic data in the UPC memories; a user cell FIFO (UFIFO) connected to the UPC for storing a user cell passed through the UPC; an IPC cell transmitting FIFO (ITFIFO) connected to the processor for storing an IPC cell and an OAM cell transmitted via the processor to the ALS; a control signal generator connected to the ITFIFO for controlling ALL5 cell segmentation for storing the IPC cell and OAM cell into the ITFIFO and generating a chip selection signal of a 4 Mbyte data memory; a second buffer for receiving an FRIA state management message inputted via an IPC bus and controlling a data bus; the processor processing a state management message inputted from the second buffer and storing the IPC cell and the OAM cell transmitted to the ALS into a segmentation packet memory (SPM); the SPM comprising 128 Kbyte and a segmentation control memory (SCM) comprising 128 Kbyte connected to the ALL5 cell segmentation; a cell multiplexer connected to the UFIFO and ITFIFO for reading the cell stored in the UFIFO and ITFIFO, performing a cell head conversion using a connection identifier of the cell head when more than one cell from the UFIFO and ITFIFO is stored, generating a head error control (HEC) with respect to a first 7 bytes of the cell, creating an odd parity bit and transmitting the cell to the LLIA in synchronization with a 23.4747 MHz clock signal; a cell head conversion table (HCT) connected to said cell multiplexer and including a 32 Kbyte DPRAM for storing a head conversion table transmitted from the processor, the cell multiplexer receiving the head table conversion for performing the head conversion; a switch link transmitting and receiving unit (LTRI) connected to the cell multiplexer for receiving the cell from the multiplexer, generating an odd parity bit, and checking the odd parity bit against a received parity bit via a head error control (HEC) code generation and checking and converting a parallel data with respect to the cell inputted from the cell multiplexer into a serial data, and transmitting the thusly converted serial data to the LLIA of the ALS through a ground-shielded cable, the LTRI being connected to a cell demultiplexer for receiving serial data from the LLIA, converting the serial data received from the LLIA into a parallel data, generating an odd parity bit and transmitting the parallel data to the cell demultiplexer; the cell demultiplexer receiving the cell from the LTRI, identifying a user cell and an IPC cell, transmitting one of the user cell to the FRIA or the IPC cell and the OAM cell to the IRFIFO; an AAL5 reassembling unit having 128 Kbyte reassembling packet memories (RPM), and 128 Kbyte reassembling control memories (RCM) and connected to the cell demultiplexer for reassembling the cell stored in the IRFIFO in the form of the AAL5; a third buffer for controlling a 16 bit data bus transmitted from the cell demultiplexer; and a clock receiver connected to the LTRI, the CBRC, the cell multiplexer and the FCDA interface for receiving a clock signal of an ECL level from the FCDA interface and transmitting the received clock to each of the LTRI, the CBRC and the cell multiplexer.