Patent ID: 6654898
Filing Date: 2003-11-25
Classification: G06F,Y02D

Abstract:
An integrated circuit chip having internal functional circuitry, said integrated circuit chip receiving an external clock, a reset signal and a clock stop signal, said integrated circuit chip comprising:a clock control circuit, said clock control circuit receives the reset signal and the clock stop signal and produces a clock control signal; a phase lock loop circuit, said phase lock loop receives the external clock and produces a generated clock based on the external clock; a multiplexer operatively connected to said phase lock loop circuit, said multiplexer receives the external clock and the generated clock, and said multiplexer outputs at an output terminal one of the external clock and the generated clock as a selected clock based on the clock control signal; and a clock stopper operatively connected to the output terminal of said multiplexer, said clock stopper operates to permit or block passage of the selected clock to the internal functional circuitry of said integrated circuit chip.