Patent ID: 6011280
Filing Date: 2000-01-04
Classification: H01L

Abstract:
A semiconductor power device comprising:a semiconductor substrate of a first conductivity type;an epitaxial layer on the substrate and having an interior region and a peripheral region surrounding the interior region so as to be between the interior region and a die edge of the semiconductor power device, the epitaxial layer having an opposite conductivity type to the first conductivity type;a semiconductor layer overlying and electrically insulated from the epitaxial layer;a first metallization electrically-contacting the semiconductor layer;a plurality of active cells in the interior region of the epitaxial layer, each of the active cells having a collector/anode terminal, an emitter/cathode terminal, a gate terminal and a base, the gate terminal being formed by the semiconductor layer, the base being formed by the epitaxial layer;an edge termination structure in the peripheral region of the epitaxial layer so as to be near the die edge of the semiconductor power device and surround the interior region of the epitaxial layer, the edge termination structure comprising:a first well of the first conductivity type underlying the semiconductor layer and completely surrounding the interior region of the epitaxial layer;a dielectric layer between a portion of the semiconductor layer and a portion of the first well so as to form a gate terminal of the edge termination structure;a second well of the opposite conductivity completely surrounding the first well, the second well being electrically insulated from the semiconductor layer; anda second metallization contacting the second well and being electrically insulated from the semiconductor layer;wherein the first well is spaced at least 250 .mu.m from the second well and the second well is spaced at least 100 .mu.m from the die edge of the semiconductor power device.