Patent ID: 6759268
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A semiconductor device manufacturing method, comprising:forming an initial conductor layer, comprising a wiring pattern, on an upper surface of an insulative base substrate; mounting an initial semiconductor element on said initial conductor layer; forming an initial insulating layer on said base substrate and said initial conductor layer so as to concurrently cover said initial semiconductor element and said initial conductor layer; forming via holes in said initial insulating layer, extending to said initial conductor layer on said base substrate; forming a further conductor layer, comprising a wiring pattern, on said initial insulating layer inclusive of inner walls of said via holes; mounting a further semiconductor element on the further conductor layer; forming a further insulating layer so as to concurrently cover the further semiconductor element and the further conductor layer; forming, on a bottom surface of said base substrate, external connection terminals electrically connected through the base substrate with the wiring pattern of the initial conductive layer.