Patent ID: 6593557
Filing Date: 2003-07-15
Classification: H01L,H04N

Abstract:
A pixel addressing system to address at least four lines of pixels in an array of pixels, the pixel addressing system comprising:a gate line including a first segment and a second segment; a plurality of spurs extending from a first side of the first segment of the gate line to couple to pixels in a first line of pixels in the array of pixels; a plurality of spurs extending from a second side of the first segment of the gate line to address pixels in a second line of pixels in the array of pixels; a plurality of spurs extending from the first side of the second segment of the gate line to couple to pixels in a third line of pixels in the array of pixels; and, a plurality of spurs extending from the second side of the second segment of the gate line to couple to pixels in a fourth line of pixels in the array of pixels.