Patent ID: 6074958
Filing Date: 2000-06-13
Classification: H01L

Abstract:
An integrated circuit device fabrication method, comprising the following steps;(a) forming a silicon nitride film over a major surface of a wafer; which major surface has a gate structure including a gate electrode and a gate protecting insulation covering side and upper surfaces of the gate electrode, and an isolation region including a recess region and an isolating insulation therein;(b) forming a silicon oxide film over the silicon nitride film;(c) forming a patterned masking film over the silicon oxide film;(d) forming a hole in the silicon oxide film by dry-etching the silicon oxide film using the nitride film as an etching stopper with a cyclic perfluorocarbon gas with three or more carbon atoms under the condition that the patterned masking film exists over the silicon oxide film and an inert gas component occupies no less than 50% of a first gas ambiance around the wafer, thereby exposing the silicon nitride film at the bottom of the hole; and then(e) removing the silicon nitride film at the bottom of the hole by etching the silicon nitride film, thereby exposing the major surface of the wafer at the bottom of the hole between the gate structure and the isolation region.