Patent ID: 8969922
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a first device region, a second device region, a third device region, a region between the first and second device regions, and a shallow trench isolation (STI) feature between the second and third device regions; a first device of a first type disposed in the first device region, the first device of the first type including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features; a second device of the first type disposed in the second device region, the second device of the first type including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features; a third device of a second type disposed in the third device region, the third device of the second type including a third gate structure, third gate spacers formed on the sidewalls of the third gate structure, and third source and drain features; a contact etch stop layer (CESL) disposed on the first, second, third gate spacers, and on the STI feature between the second and third device regions; a silicide layer disposed on the source and drain features of the first source and drain features, the second source and drain features, and the third source and drain features; an interconnect structure disposed on the silicide layer over the third source and drain features, the interconnect structure being in direct contact with the CESL disposed on the third gate spacers; and a common interconnect structure disposed on the first and second source and drain features, the common interconnect structure traversing the region between the first and second device regions and in electrical contact with the first and second source and drain features and in contact with the CESL disposed on the first and second gate spacers, wherein a top surface of the first gate structure, a top surface of the second gate structure, and a top surface of the CESL are in a common plane.