Patent ID: 7735040
Filing Date: 2010-06-08
Classification: G06F

Abstract:
1. A method for designing a cell layout of a semiconductor integrated circuit, comprising the steps of: inputting information from information files storing the information, the information including a floor plan of the semiconductor integrated circuit with a logic circuit, arranged cells and a cell layout-prohibited area which have been predetermined based on the floor plan, priority cells constrained by the circuit performance of the logic circuit which are a group of cells chosen from a plurality of cells whose arrangement order is determined in consideration of a data flow in the logic circuit and which are other than the arranged cells, general cells other than the arranged cells and the priority cells, and a limit of a cell layout width which determines a layout range of the priority cells; extracting cells which have been already arranged in a direction in which the priority cell is to be arranged, or a cell layout-prohibited area; arranging the priority cell in a layout area determined by the limit of the cell layout width using a first algorithm, avoiding the extracted arranged cell or cell layout-prohibited area; arranging the general cells using a second algorithm after completion of the arrangement of the priority cells; and outputting a layout result of each of the priority cells and the general cells; wherein, when any one cell chosen from the priority cells is referred to as a first priority cell and a cell connected with the first priority cell as a second priority cell, the first algorithm performs a cell layout so that at least a part of one side of the first priority cell is in contact with at least a part of one side of the second priority cell; and the second algorithm performs compaction so that a cell density of an area where the general cells are arranged is high.