Patent ID: 7366873
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A computerized method comprising: providing a first vector of addressing values; providing a second vector of operand values; storing a first sequence of values to a sequence of addressed locations within a constrained area of memory, wherein each location's address is based at least in part on a corresponding one of the addressing values; reading back from the sequence of addressed locations values resulting from the storing of the first sequence to obtain a second sequence of values; comparing the first sequence of values to the second sequence of values to generate a bit vector representing compares and miscompares; compressing the second vector of operand values using the bit vector; using the first vector of addressing values as masked by the bit vector, loading a third vector register with elements from memory; performing an arithmetic-logical operation using values from the third vector register and the compressed second vector of operand values to generate a result vector; and using the first vector of addressing values as masked by the bit vector, storing the result vector to memory.