Patent ID: 7928562
Filing Date: 2011-04-19
Classification: H01L

Abstract:
1. An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment, comprising: a substrate installed within the computing environment; a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, which is normal to a plane of the substrate; a set of one or more second components to perform operations of the computing environment, each of which is stacked onto the first component in the stacking direction such that the first component is at least partially interposed between the substrate and the one or more second components along the stacking direction, and each of which is segmented with respect to one another to form a vacated region; a thermal interface material (TIM) disposed on exposed surfaces of the first and second components; and a lid, including a protrusion, coupled to the substrate to overlay the first and second components along the stacking direction such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.