Patent ID: 6178207
Filing Date: 2001-01-23
Classification: G01S,H04L

Abstract:
An apparatus for processing data messages under control of a host processor, the apparatus having a receive data path through which received messages are processed, and having a transmit data path through which transmit messages are processed independently from the received messages, such that messages in a first data protocol and a second data protocol can be processed by the receive data path and the transmit data path, the apparatus comprising:a downconverter that receives sample data of data messages at an intermediate frequency;a first protocol demodulator that receives sample data from the downconverter and processes the received messages according to the first data protocol;a second protocol demodulator that receives sample data from the downconverter and processes the received messages according to the second data protocol; anda processor interface through which the apparatus exchanges data with the host processor;wherein the second protocol demodulator includes a digital correlator comprising a matched filter that further includes a vector summer that sums sample data values to form a reference vector and then compares a current sample data value comprising a signal vector to the reference vector such that a signal vector that is in phase with the reference vector is added to the reference vector to produce a new reference vector value, and a signal vector that is out of phase with the reference vector is inverted before being added to the reference vector.