Patent ID: 6711602
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A data processing apparatus operating in response to predetermined instructions comprising:a first data source; a second data source; a first multiplier circuit connected to said first data source and said second data source, said first multiplier circuit forming a first product of an instruction selected portion of said first data source and an instruction selected portion of said second data source; a first shifter connected to said first multiplier circuit forming a first shifted output of said first product having an instruction specified shift amount; a second multiplier circuit connected to said first data source and said second data source, said second multiplier circuit forming a second product of an instruction selected portion of said first data source and an instruction selected portion of said second data source; a second shifter connected to said second multiplier circuit forming a second shifted output of said second product having an instruction specified shift amount; and an arithmetic circuit connected to said first shifter and to said second shifter forming an instruction selected arithmetic combination of said first shifted product applied to most significant bits and said second shifted product applied to least significant bits.