Patent ID: 6321369
Filing Date: 2001-11-20
Classification: G01R,G06F,G06Q,Y10S

Abstract:
A method for compiling a base design and a variation of an electronic design, the method comprising:providing a graphical user interface;providing a base design, said base design including one or more data files including assignment data;creating a variation design by applying at least one variation assignment to a group of logic functions not provided in the assignment data of said base design, wherein the variation assignment to the group of logic functions specifies at least one of a style, logic option, clique assignment, position requirement, timing requirement, family, device, speed grade and global default parameter;using said graphical user interface to display, for compilation, a list of designs including the base design and the variation design;with the aid of said graphical user interface, selecting for compilation the base design and the variation design;compiling both said base design and said variation design; andoutputting the compiled base design to a first file designated for said compiled base design and outputting the compiled variation design to a second file designated for said compiled variation design.