Patent ID: 8179155
Filing Date: 2012-05-15
Classification: G01R

Abstract:
1. A layout structure of electronic elements, comprising: M*N electronic elements in a form of a matrix; a first test pad group disposed on a first side of said matrix, and all electronic elements in the same linear section of said matrix electrically connected to a corresponding test pad in said first test pad group; a second test pad group disposed on a second side of said matrix, and all electronic elements in the same linear section of said matrix electrically connected to a corresponding test pad in said second test pad group; a third test pad group disposed on a third side of said matrix, and all electronic elements in the same linear section of said matrix electrically connected to a corresponding test pad in said third test pad group; and a fourth test pad group disposed on a fourth side of said matrix, and all electronic elements in the same linear section of said matrix electrically connected to a corresponding test pad in said fourth test pad group.