Patent ID: 6399399
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory having an array of memory cells, each memory cell including a memory cell transistor electrically connected to a capacitor, comprising the steps of:forming a memory cell transistor on a semiconductor substrate followed by forming a first interlayer insulation film over a surface resulting after forming the memory cell transistor; forming a groove for making the capacitor at a predetermined location in the first interlayer insulation film; forming a lower electrode film over a surface resulting from forming the groove; applying and processing a resist material so as to leave a resist film in the groove; removing excess portions of the lower electrode film so as to leave the lower electrode film in the groove; selectively forming a first metal film on the lower electrode film after applying and processing the resist material; and forming a capacitor insulation film and an upper electrode film over a surface resulting from removing excess portions of the lower electrode film.