Patent ID: 6351787
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A storage apparatus to be coupled with a system bus for receiving a write request accompanied with a plurality of sector data through said system bus from an information processing system, wherein each of said plurality of sector data is comprised of 512 bytes, comprising:an interface unit to be coupled to said system bus; a plurality of nonvolatile flash semiconductor memories each of which includes a plurality of memory blocks of erase units erasable by flash erase operations; and a controller, coupled to said interface unit and said plurality of nonvolatile flash semiconductor memories, which carries out write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories in response to said write request, wherein each of said plurality of nonvolatile flash semiconductor memories has a flash data bus width of a first predetermined bit number for inputting data to be written into each nonvolatile flash semiconductor memory, wherein said interface unit has a system data bus width of a second predetermined bit number which includes a product number of multiplying said first predetermined bit number by a number of said plurality of nonvolatile flash semiconductor memories, and wherein said write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories are carried out simultaneously in response to said write request.