Patent ID: 6818936
Filing Date: 2004-11-16
Classification: H01L

Abstract:
An EEPROM cell having a Metal-Insulator-Metal (MIM) coupling capacitor as a control gate comprising:an interlevel dielectric (ILD) layer over a substrate, said ILD layer having an opening reaching the substrate; a tunneling dielectric formed at the bottom of said opening over said substrate; a floating gate over said ILD layer, including over said opening and reaching underlying said tunneling dielectric; a first metal layer over said ILD reaching underlying said floating gate through a via hole; an intermetal dielectric (IMD) layer over said first metal layer; an opening having inside walls in said IMD layer reaching said first metal layer; a capacitor dielectric layer covering said first metal layer and said inside walls of said opening in said IMD layer; and a second metal layer covering said capacitor dielectric layer in said hole, thus forming said MIM coupling capacitor of said EEPROM cell.