Patent ID: 6342419
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method for fabricating a capacitor in a DRAM cell, said method comprising the steps of:providing a semiconductor substrate, which is formed therein with isolation regions, source/drain regions, and word lines having first spacers and first capping layers on tops of said word lines; forming landing pads on said source/drain regions, said first spacers, said first capping layers of said word lines, each one of said landing pads being separated by an isolating layer, said isolating layer being on a portion of said first capping layers; forming a first dielectric layer on said landing pads and said isolating layer; forming bit lines on said first dielectric layer, each said bit line having a second capping layer on a top and second spacers on sidewalls; forming a second dielectric layer on resulting surfaces, said second dielectric layer having a substantial higher etching rate than to that of said first dielectric layer by at least one etchant; patterning said second dielectric layer through first dielectric layer to expose portions of said landing pads using line masks, said second capping layer and said second spacers as etching masks, each of said line masks being substantially perpendicular to said bit lines and a space interval between any two said line masks which are adjoin, having a smaller width than each said landing pad, so that said space interval is within said landing pads; etching portions of said second dielectric layer to expand openings of said second dielectric layer using an etchant having a substantially higher etching rate to said second dielectric layer than to said first dielectric layer; forming a capacitor storage node of said DRAM cell on resulting regions; refilled a photoresist layer on all recessed region; performing a planarization process using said second nitride capping layer as a stopping layer; and removing said photoresist layer.