Patent ID: 6522171
Filing Date: 2003-02-18
Classification: H03K

Abstract:
A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprising:a connection to at lent one upper power rail; a conuection to a lower power rail; a precharge node; an output node adapted to be charged to the potential of one of the at least one upper power rails after a precharge signal is received at the precharge node; a latch on the output node to maintain the potential at the output node; at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail; a device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail and wherein the device coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage comprises an NFET transistor coupled between the lower power rail and the output node which, upon receipt of the standby signal, maintains the potential of the output node at the potential of the lower power rail.