Patent ID: 6313678
Filing Date: 2001-11-06
Classification: H03K,H04L

Abstract:
An edge rate controller circuit for controlling an output driver comprising:a first transistor coupled to an output control node of said output driver and having a control terminal coupled to receive an input signal;a second transistor coupled to the output control node and having a control terminal coupled to receive said input signal;a third transistor coupled to the first transistor;a fourth transistor coupled in parallel with the third transistor;a first transmission gate coupled between a control terminal of the third transistor and a control terminal of the fourth transistor for providing an edge rate control signal;a fifth transistor coupled to the second transistor;a sixth transistor coupled in parallel with the fifth transistor; anda second transmission gate coupled between a control terminal of the fifth transistor and a control terminal of the sixth transistor for providing said edge rate control signal.