Patent ID: 8884361
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a power MISFET in a first region of a semiconductor substrate and having a gate electrode over the gate, electrically coupled to the gate, comprised of a second conductor whose resistivity is lower than that of the first conductor, and having a gate finger portion; a source electrode over the source, electrically coupled to the source, comprised of the second conductor, and having a plurality of regions; a drain electrode over the drain and electrically coupled to the drain of the power MISFET; a gate bump electrode over the gate electrode and electrically coupled to the gate of the power MISFET; a plurality of source bump electrodes over each of the respective plurality of regions of the source electrode; a gate lead over the gate bump electrode and electrically coupled to the gate bump electrode; a source lead over the source bump electrodes and electrically coupled to the plurality of source bump electrodes; a drain lead over the drain electrode and electrically coupled to the drain electrode; and a resin body sealing the semiconductor substrate, wherein the gate electrode and the source electrode are formed in a same conductive layer, and wherein the gate finger portion of the gate electrode is located between two adjacent regions of the plurality of regions of the source electrode.