Patent ID: 8455320
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A method for manufacturing an inverted field-effect-transistor (iT-FET) semiconductor device comprising a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate having a vertical current conducting channel between said source and said drain controlled by a vertical sidewall gate disposed on sidewalls of a trench and a source-body short structure extending downwardly from a bottom surface of said trench for electrically shorting a body region in said substrate to a source disposed on under a bottom of said trench wherein the method comprising: applying a first mask for opening a shallow-and-wide trench in the semiconductor substrate followed by carrying out a plurality processing steps of sidewall tilt implanting, conformal insulation depositions, anisotropic etching to form sidewall spacers, selective etching to form the sidewall gate and a deep and narrow trench and carrying out trench bottom implants to form bottom body and source regions and source/body dopant contact regions, followed by filling the trench and covering the top surface with insulation and passivation layers; applying a gate/drain contact opening mask as a second mask to etch the insulation and passivation layer to open gate and drain contact openings; and depositing a contact metal on top and applying a third mask for patterning the contact metal into a drain contact metal and a gate contact metal with the source terminal on the bottom of the semiconductor substrate.