Patent ID: 8049198
Filing Date: 2011-11-01
Classification: H01L

Abstract:
1. A phase change memory device comprising: an interlayer dielectric formed on a semiconductor substrate; lower electrodes respectively formed within the interlayer dielectric in a plurality of phase change cell regions of the semiconductor substrate; a first insulation layer formed on the interlayer dielectric including the lower electrodes and having holes for exposing the respective lower electrodes, wherein the holes are aligned in a cell arrangement direction; heaters formed on surfaces of the respective holes and contacting the lower electrodes, wherein the heater has a first side and a second side that is opposite to the first side; a second insulation layer formed to fill the holes in which the heaters are formed; a mask pattern formed on the first and second insulation layers including the heaters, the mask pattern having openings which selectively expose center portions of the first side of the respective heaters and which are arranged to have a constant pitch among the respective heaters, wherein the openings are arranged to expose the heaters in a direction perpendicular to the cell arrangement direction, and wherein the mask pattern covers whole portions of the respective heaters entirely except for only the center portion of the first side; a phase change layer formed over the mask pattern including on the exposed center portions of the first side of the heaters and the first and second insulation layers; and upper electrodes formed directly on the phase change layer.