Patent ID: 7847367
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. An integrated circuit device comprising: an integrated circuit substrate; a first gate pattern on the substrate; a non-conductive barrier layer pattern on the first gate pattern, the barrier layer pattern having openings at selected locations therein extending to the first gate pattern, wherein the barrier layer pattern comprises a plurality of sub-barrier layer patterns that are separated from one another to define the openings in the barrier layer pattern and wherein a portion of the first gate pattern is exposed by at least one of spaces between the sub-barrier layer patterns; and a second gate pattern on the barrier layer pattern and extending into the opening in the barrier layer pattern to electrically connect the second gate pattern to the first gate pattern, wherein the second gate pattern comprises a tungsten silicide layer, a combination of tungsten silicide and tungsten nitride, or a combination of tungsten, tungsten nitride and tungsten silicide.