Patent ID: 7624252
Filing Date: 2009-11-24
Classification: G06F

Abstract:
1. A processing device comprising: a plurality of input buffer units which are provided in correspondence with a plurality of data series and store input data to output the input data as data to be processed; a processing unit which changes an arithmetic processing function by establishing a connection relation of internal components according to connection information to execute desired arithmetic processing on the data to be processed and output processed data; a plurality of output buffer units which are provided in correspondence with said data series and store the processed data to output the processed data as output data; and a control unit which, in each processing cycle, determines the components of said processing unit to be assigned to an operation, which is indicated by instruction information corresponding to the data series, when the operation is executable, shifts a processing cycle in which the operation is to be executed to a subsequent processing cycle upon satisfying a data output timing from said output buffer unit when the operation is not executable due to lack of the components of said processing unit, and outputs an assignment of the components of said processing unit as the connection information.