Patent ID: 6514817
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each said deep trench capacitor construction having a collar construction and a conductor construction, comprising steps of:(a) defining a mask by forming a mask layer on said semiconductor substrate having said deep trench capacitor constructions; (b) performing a first etching process with respect to said specific region uncovered by said mask so as to form a first depth trench, said first etching process having a relatively high selectivity ratio of said conductor construction relative to said mask; and (c) performing a second etching process with respect to said first depth trench so as to form a second depth trench, said second etching process having a selectivity ratio of said conductor construction relative to said collar construction substantially close to 1.