Patent ID: 8907835
Filing Date: 2014-12-09
Classification: H03M,H04N

Abstract:
1. An A/D conversion circuit comprising: a delay circuit that includes a plurality of delay units having a first pulse input terminal, a pulse output terminal, and an analog signal input terminal, wherein each first pulse input terminal of the plurality of delay units is connected to one of the pulse output terminals corresponding to the plurality of delay units, and a pulse output signal input to the first pulse input terminal is delayed in accordance with an analog signal input to the analog signal input terminal and output from the pulse output terminal, and one of the plurality of delay units has a second pulse input terminal to which a pulse signal is input from outside; a state variation detection circuit that successively compares pulse output signals from two continuous delay units the plurality of delay units and that, when the states are different between the two pulse output signals, outputs a state variation detection signal; and an encoding signal latch circuit that latches the encoding signal when an encoding signal having a state in accordance with a delay unit that has output the pulse output signal to the state variation detecting circuit is input and the state variation detection signal is input.