Patent ID: 7589375
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A non-volatile memory device, comprising: a semiconductor substrate including a cell array region and a peripheral circuit region; a first cell unit on the semiconductor substrate in the cell array region; a cell insulating layer on the first cell unit; a first active body layer in the cell insulating layer and over the first cell unit; a second cell unit on the first active body layer; a peripheral transistor on the semiconductor substrate in the peripheral circuit region, the peripheral transistor having a gate pattern and source/drain regions; a metal silicide layer on the gate pattern and/or on the source/drain regions of the peripheral transistor; a peripheral insulating layer on the metal silicide layer and the peripheral transistor; and an etching protection layer between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.