Patent ID: 8325506
Filing Date: 2012-12-04
Classification: G11C,H04L

Abstract:
1. A semiconductor device for comparing data in a content-addressable memory, comprising: a semiconductor-on-insulator (SeOI) substrate; a memory cell formed in the SeOI substrate, the memory cell including a first transistor and a second transistor, each of the transistors having a front control gate and a back control gate that can be controlled to block the associated transistor, the transistors being configured so that, in order to store a data bit (BIT) and the complement of the data bit (˜BIT), with one of the transistors passing and the other blocked; and a comparison circuit configured to operate the transistors in read mode by applying to both front control gates a nominal read voltage, to control the back control gates so as to block the passing transistor if a proposed bit (DATA) and the stored bit (BIT) correspond, and to detect a current on a source line linked to the source of each of the transistors, wherein the presence or absence of such a current indicates whether the proposed bit (DATA) and the stored bit (BIT) are identical or not.