Patent ID: 6753193
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method of fabricating a ferroelectric memory device comprising the steps of:forming first and second switching elements on a semiconductor substrate; forming an interlayer insulating layer covering the first and second switching elements; forming first and second contact plugs in the interlayer insulating layer, the first and second contact plugs being coupled to the first and second switching elements, respectively; forming, on the interlayer insulating layer, capacitors where a lower electrode coupled to the first contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode are sequentially stacked; forming an insulating layer covering the capacitor, the second contact plug, and the interlayer insulating layer; and forming, in the insulating layer, an interconnection for connecting the second contact plug to the upper electrode.