Patent ID: 8921229
Filing Date: 2014-12-30
Classification: C09G,C09K,H01L

Abstract:
1. A method of polishing surfaces of copper wiring of an ultra large scale integrated circuit, the method comprising: a) preparing a polishing solution consisting essentially of: between 35 and 80 w. % of a nano SiO b) polishing using the polishing solution under following conditions: wherein the active agent is selected from the group consisting of an FA/O surfactant, O π -7((C 10 H 21 —C 6 H 4 —O—CH 2 CH 2 O) 7 —H), O π -10((C 10 —H 21 —C 6 H 4 —O—CH 2 CH 2 O) 10 —H), O−20(C 12-18 H 25-37 —C 6 H 4 —O—CH 2 CH 2 O) 70 —H), or JFC.