Patent ID: 8604556
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a recess pattern by selectively etching a substrate; forming a gate dielectric layer by filling the recess pattern on the substrate; forming a groove by selectively etching the gate dielectric layer, wherein a bottom surface of the groove is higher than the highest surface of the substrate; forming a polysilicon electrode filling the groove; forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and forming a gate pattern by etching the electrode metal layer and the gate dielectric layer, wherein the recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery, wherein the gate dielectric layer below the edge portion of the gate pattern has a lower protruding area completely filling the recess pattern both in the length direction and the width direction of a channel.