Patent ID: 8418175
Filing Date: 2013-04-09
Classification: G06F

Abstract:
1. A data processing apparatus, comprising: processing circuitry configured to execute hypervisor software to support the execution of multiple virtual machines on the processing circuitry; a memory system configured to store data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request; the processing circuitry being configured to execute in a secure domain when executing the hypervisor software, the secure memory being accessible from the secure domain, and the processing circuitry being configured to execute in a non-secure domain when executing any of the multiple virtual machines, as a default position the secure memory not being accessible from the non-secure domain; address translation circuitry, responsive to an access request issued by a current virtual machine executing on the processing circuitry and specifying a virtual address, to perform an address translation process to identify a physical address in said memory system containing data seeking to be accessed by the current virtual machine, and to cause to be issued to the memory system a modified access request specifying the physical address; and a storage configured to store a trusted virtual machine identifier managed by the hypervisor software, the hypervisor software being arranged to set the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory; in response to the access request issued by the current virtual machine, if the trusted virtual machine identifier is not set, the address translation circuitry is configured to maintain said default position by causing the modified access request to be issued as a non-secure access request specifying a physical address within the non-secure memory, but if the trusted virtual machine identifier is set, the address translation circuitry is configured to overcome the default position by causing the modified access request to be issued as said secure access request able to specify a physical address within the secure memory while the processing circuitry continues to execute in said non-secure domain.