Patent ID: 6114917
Filing Date: 2000-09-05
Classification: H03L

Abstract:
An analog PLL circuit, comprising:a voltage controlling oscillator configured to change frequency in accordance with voltage;a phase comparator configured to output a signal corresponding to a frequency deviation and a phase deviation of a signal corresponding to an output of said voltage controlling oscillator and a signal corresponding to a standard input signal;a charge pump configured to output a voltage corresponding to an amount and a direction of the phase deviation based on the signal output by said phase comparator;a low pass filter configured to eliminate a high-frequency component included in the voltage output by said charge pump;a ring oscillator provided inside said voltage controlling oscillator and having a delay circuit configured to change a delay amount, an oscillating frequency of said ring oscillator being controlled variably based on said delay amount;a delay amount control section provided inside said voltage controlling oscillator and configured to set the delay amount of said delay circuit;an initial delay amount setting circuit configured to set an initial delay amount of said delay circuit by said delay amount control section during a reset period; andan oscillation controlling circuit configured to allow oscillating operation of said ring oscillator to begin at a point when a rising edge or a falling edge of said standard input signal is firstly inputted after the reset period finishes, said oscillating control circuit having a flip-flop with a clock terminal to which said standard input signal is inputted, and being configured to allow oscillating operation to begin at the point when the rising edge or the falling edge of said standard input signal is inputted to said clock terminal after the reset period finishes;wherein the oscillating frequency of said voltage controlling oscillator is controlled in accordance with an output of said low pass filter.