Patent ID: 7790606
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A method of forming an interconnect structure for a semiconductor device, comprising: (a) depositing a first dielectric layer; (b) patterning the first dielectric layer to form via holes in the first dielectric layer; (c) filling the via holes with a filler material, wherein the filler material comprises an organic material that is selectively etchable with respect to the material of the first dielectric layer, and wherein the filler material has a decomposition temperature higher than 350° C.; (d) depositing a second dielectric layer over the first dielectric layer which is selectively etchable with respect to the filler material, wherein said deposition of the second dielectric layer is carried out at a temperature below 350° C.; (e) patterning the second dielectric layer to form trenches defining interconnections provided by the interconnect structure in the second dielectric layer; (f) removing filler material exposed by the trenches from the via holes; and (g) depositing electrically conductive material to fill the trenches and via holes.