Patent ID: 7188219
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A memory hub controller for controlling access to a system memory, comprising: a memory request queue storing at least one memory request received through an input port, the memory request queue being operable to issue from an output port each memory request stored in the memory request queue responsive to a flow control signal; a response queue coupled to receive through an input port read responses containing each read data and a read status signal identifying read requests corresponding to the read data, the response queue further being coupled to receive through the input port write responses each having a write status signal identifying write requests that have been serviced, the response queue being operable to couple at least the read data from each read response signal to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and a buffer management unit coupled to receive the read status signals and the write status signals from the response queue, the buffer management unit having a read buffer monitor circuit to determine from the read status signals a number of outstanding read requests issued by the memory request queue and having a write buffer monitor circuit to determine from the write status signals a number of outstanding write requests issued by the memory request queue, the buffer management unit further having a flow control circuit coupled to the read and write buffer monitor circuits to generate a flow control signal provided to the memory request queue controlling issuance of read and write requests to the memory modules based on the numbers of outstanding read and write requests, respectively, issued by the memory request queue.