Patent ID: 8194491
Filing Date: 2012-06-05
Classification: G11C

Abstract:
1. A power-up circuit for a semiconductor memory device, comprising: an external supply voltage potential detector configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value; a first internal supply voltage potential detector configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value; a second internal supply voltage potential detector configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively; and a logic circuit configured to receive the third detection signal and to generate a power-up signal.