Patent ID: 8914581
Filing Date: 2014-12-16
Classification: G06F

Abstract:
1. A machine-implemented method in a cache system of a memory controller of a network processor in a network element to avoid caching data identified by physical memory addresses that have not been accessed frequently in a recent period of time, the method comprising the steps of: receiving a request for reading data from a memory location within a main memory identified by a physical memory address; in response to the request, accessing a cache memory based on the physical memory address to determine whether the cache memory contains the data being requested, wherein entries in the cache memory are to store cache lines that have a size spanning a set of one or more physical memory addresses and that are aligned on cache line boundaries; incrementing, in a filter array comprising a plurality of entries that each include a value, the value of a first entry, by one count, wherein each of the plurality of entries is currently associated with one or more recently accessed physical memory addresses, wherein each of the plurality of entries can store a value larger than one, and wherein the first entry is associated with the physical memory address; returning the data associated with the request from the cache memory without accessing the memory location of the main memory if there is a cache hit; and in response to a cache miss, performing the following steps: decrementing, upon an occurrence of a predetermined number of processing cycles, the value of each of the plurality of entries of the filter array by one count, such that the value of each of the plurality of entries represents a number of accesses of corresponding physical memory locations wherein each value decays by one count upon a set period of time represented by the predetermined number of processing cycles.