Patent ID: 7960984
Filing Date: 2011-06-14
Classification: G01R,H01L

Abstract:
1. A semiconductor device including stacked chips, each stacked chip comprising: a test circuit configured to output a test control signal, an interface control signal, and a selection control signal in response to a test enable signal; a selection signal generator configured to output a selection signal in response to the selection control signal; an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal; at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal and in response to the selection signal; at least one test pad configured to receive the selected test signal; at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally; and an interface configured to receive the plurality of test signals from the internal circuit and to one of drive and output the test signals and prevent the test signals from being output in response to the interface control signal.