Patent ID: 6353562
Filing Date: 2002-03-05
Classification: G11C

Abstract:
An integrated semiconductor memory, comprising:memory cells which are combined to form addressable normal units; further memory cells which are combined to form at least one redundant unit for replacing one of said addressable normal units; an address bus to which an address can be applied and having connection points; a redundancy circuit connected to said address bus and storing the address for one of said addressable normal units which is to be replaced by said redundant unit, said redundancy circuit having inputs and compares the address on said address bus with a stored address, and said redundancy circuit selecting said redundant unit if a match is established between the stored address and the address on said address bus; and a processing unit having a first input connected to one of said connection points of said address bus, a second input receiving a test signal, and an output connected to one of said inputs of said redundancy circuit, said processing unit modifying an address signal only for a defined state of the test signal.