Patent ID: 6815333
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of forming trenches and vias in a dielectric stack comprising the steps of:(a) providing a substrate; (b) applying the dielectric stack to the substrate wherein the dielectric stack comprises a top portion in which trenches will be formed and a bottom portion in which vias will be formed and an etch stop layer between the top and bottom portions wherein the dielectric constant of each of the top portion and the bottom portion is less than 3.0; (c) applying a first mask layer which acts as a stop during the polishing step and which has etch selectivity relative to the top portion of the dielectric stack and has etch characteristics similar those of the etch stop layer; (d) applying a second mask layer which has etch selectivity relative to the first mask layer and has etch characteristics similar to those of the top portion of the dielectric stack; (e) applying a third mask layer which has etch selectivity relative to the second mask layer and having etch characteristics similar to those for the first mask layer, (f) patterning the first mask layer in accordance with a trench pattern; (g) patterning the etch stop layer with via pattern; (h) etching the trench pattern into the top portion of the dielectric stack to form at least one trench and the via pattern into the bottom portion of the dielectric stack to form at least one via; (i) depositing a metal in the vias and trenches; (j) polishing away excess metal wherein the first mask layer serves as a polishing stop; wherein only three mask layers are used and at least a substantial portion of the third mask layer is removed during patterning of either the first mask layer or the etch stop layer and wherein at least a substantial portion of the second mask layer is removed during etching of the dielectric stack and wherein all the layers are applied via solvent coating.