Patent ID: 6472234
Filing Date: 2002-10-29
Classification: G01R,H01L

Abstract:
A failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads, first solder balls formed on said pads, an interposer substrate formed on said first semiconductor balls and second solder balls formed on said interposer substrate, comprising the steps of:removing said second solder balls and said interposer substrate from said semiconductor device; removing said first solder balls from said semiconductor device to expose said pads on a surface of said semiconductor chip, after said second solder balls and said interposer substrate are removed; mounting said semiconductor device on a package, after said first solder balls are removed and said pads exposed; performing a wire bonding operation on said pads of said semiconductor chip and on bonding pads of said package to connect bonding wires therebetween; and performing a test operation upon said semiconductor chip by mounting said package on a tester.