Patent ID: 6275950
Filing Date: 2001-08-14
Classification: G06F

Abstract:
An adjustable PCI asychronous clock device having a plurality of PCI slots, which device selectively delays a PCI clock signal in order to match a computer signal of a system chip set with a clock signal of a chip set of a PCI add-on card, which comprises:an I/O port for generating a control signal;a plurality of multiplexers having a plurality of control signals on control lines of which are selectively controlled by the I/O port and a output of which is connected to each of the PCI slots; andtime delay means for delaying the PCI clock signal, having a plurality of delay units, output of the time delay means being connected to each of the PCI slots;output of I/O port being set by a firmware so that each of the PCI slots selects one of the delay units, the PCI clock signal associated with each of the PCI slots is delayed by the delay unit in order to regulate the clock signal of the chip set on the PCI add-on card to be synchronous to the computer signals of the system chip set, so that the add-on cards match the PCI slots.