Patent ID: 7521806
Filing Date: 2009-04-21
Classification: H01L

Abstract:
1. A system comprising: a first chip having first semiconductor devices and first electrical connections thereon; a second chip having second semiconductor devices and second electrical connections thereon; and a third chip having third semiconductor devices and third electrical connections thereon, wherein at least one of the first, second, or third electrical connections comprise a post portion that is rigid, and at least another one of the first, second, or third electrical connections comprise a malleable metal portion that is malleable compared to the post portion, wherein the post portions are configured to penetrate into the corresponding malleable metal portions to form malleable and rigid connection, and wherein the third chip is disposed at an elevation above the first and second chips, and is separated from the first and second chips by a non-conductive planarizing layer deposited on the first and second chips, and wherein the third chip is coupled to the first and second chips such that at least some of the third electrical connections are coupled to at least some of the first electrical connections and at least one or more others of the third electrical connections are coupled to some of the second electrical connections through joints formed by the post portions and the corresponding malleable metal portions.