Patent ID: 8330251
Filing Date: 2012-12-11
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a first capacitor comprising a first feature, the first capacitor having a first area in a given layer of a metallization level, the first feature being disposed at least partially in the given layer, the first feature having a plurality of fingers each having a first portion extending longitudinally in a first direction, each of the fingers having a second portion co-planar in a plan view perspective with the first portion extending from the first portion in a second direction that is non co-linear with the first direction; a second capacitor comprising a second feature, the second capacitor having a second area in the given layer of the metallization level, the second being disposed at least partially in the given layer, and the first and second capacitors being electrically matched, the first capacitor and the second capacitor being symmetrical about a central axis from the plan view perspective; and a common electrode feature that is common to the first and second capacitors, the common electrode feature being at least partially located in the given layer, the common electrode feature having a plurality of common electrode fingers each comprising a first portion extending longitudinally in a third direction and a second portion co-planar in the plan view perspective with the first portion extending from the first portion longitudinally in a fourth direction that is non co-linear with the third direction; wherein a first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.