Patent ID: 6313681
Filing Date: 2001-11-06
Classification: G01R,H03H,H03K

Abstract:
A variable delay circuit comprising:an input terminal;a positive logic variable delay circuit for delaying a leading edge of the signal inputted through said input terminal;a negative logic variable delay circuit for delaying a trailing edge of the signal inputted through said input terminal; andan extracting circuit for extracting only the edges delayed in accordance with a set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuitwherein said positive logic variable delay circuit includesdelay time increasing means for making more than the set time, the delay time of an edge, varying from a low level to a high level, of the signal inputted through said input terminal, whilesaid negative logic variable delay circuit includesdelay time decreasing means for making less than the set time, the delay time of an edge, varying from a high level to a low level, of the signal inputted through said input terminal.