Patent ID: 6760254
Filing Date: 2004-07-06
Classification: G11C

Abstract:
A semiconductor memory circuit comprising:a plurality of memory cell blocks arranged in a first direction, each of the memory cell blocks including a plurality of memory cells arranged in a matrix form, the plurality of memory cells being of MOS structure and being electrically data rewritable; a plurality of bit lines formed of a plurality of first wiring layers, a plurality of sub data lines formed of a plurality of second wiring layers, the plurality of sub data lines extending in the first direction on the plurality of memory cell blocks and being connected to the plurality of memory cell blocks; a first bank region including at least the plurality of memory cell blocks and the plurality of sub data lines; at least one of second bank region arranged in a second direction perpendicular to the first direction, the second bank region having the same structure as the first bank region; a plurality of data read lines formed of third wiring layers and arranged on the first and second bank regions, the plurality of data read lines configured so that data are read by way of the plurality of data lines from the plurality of memory cells of a bank region of the first and second bank regions selected in a first operation mode; a plurality of first amplifier circuits connected to the plurality of data read lines; a plurality of auto data lines extending in the second direction on a region out of the plurality of memory cell blocks of the first and second bank regions, the plurality of auto data lines configured so that data are read in a second operation mode by way of the plurality of sub data lines from the plurality of memory cells; a plurality of second amplifier circuits connected to the plurality of auto data read lines; a plurality of switch circuits provided in correspondence to the plurality of memory cell blocks of the first and second bank regions, the plurality of switch circuits configured to switch the plurality of sub data lines of the first and second bank regions and the plurality of data read lines between a connection state and a non-connection state in correspondence to the first and second operation modes, wherein data in the plurality of memory cells of the second bank region are readable from the plurality of first amplifier circuits, even when data in the plurality of memory cells of the first bank region is being read from the plurality of second amplifier circuits.