Patent ID: 6130129
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A method for fabrication flash memories with high control-gate-to-floating-gate coupling ratio comprising the following steps:(a) forming a stacked multi-layer on a substrate, said stacked multi-layer comprising, in said order away from said substrate, a tunnel oxide layer, a poly-1 layer, a dielectric layer, and a thin poly layer;(b) using a photolithography technique and a silicon etching procedure to etch said stacked multilayer and said substrate so as to form a towering structure surrounded by by a recessed region in said substrate;(c) forming a field oxide layer (FOX) which fills said recessed region and covers said stacked multilayer;(d) planarizing said field oxide layer by applying a chemical-mechanical polishing (CMP) procedure, using said thin poly layer as a CMP stop;(e) applying an oxide etchback procedure to said field oxide layer to reveal a portion of said poly-1 layer;(f) forming a poly-2 layer on top of said field oxide and said stacked multilayer wherein said poly-2 layer is merged with said poly-1 layer through said revealed portion of said poly-1 layer;(g) applying an anisotropic etching procedure to remove said dielectric layer, said thin poly layer, and a portion of said poly-2 layer on top thereof, wherein an elevated height due to said dielectric layer and said thin poly layer causes a pair of poly sidewall spacers to remain which are attached to said poly-1 layer to jointly form a floating gate;(h) forming an oxide/nitride/oxide (ONO) layer covering said floating gates; and(i) forming a poly-3 layer on top of said substrate covering both said floating gates and said field oxide layer to form a control gate.