Patent ID: 8634254
Filing Date: 2014-01-21
Classification: G11C

Abstract:
1. A single polycrystalline silicon electrically erasable and programmable floating gate memory device, comprising: a one-pass NMOS transistor having a drain connected to a bit line and a gate connected to a word line; a floating gate NMOS storage transistor having a single polycrystalline (single-poly) floating gate, a drain connected a source of said one-pass NMOS transistor and a source connected to a source line; a first polycrystalline-Insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor, said first PIP or MIM capacitor having a first plate connected to said single-poly floating gate and a second plate connected to a first voltage source node; and a second PIP or MIM capacitor having a first plate connected to said single-poly floating gate and a second plate connected to a second voltage source node, said second PIP or MIM capacitor being a tunneling capacitor for said floating gate NMOS storage transistor; wherein said one-pass NMOS transistor and said floating gate NMOS storage transistor are formed in a triple P-well on a deep N-well, said first PIP or MIM capacitor is a coupling capacitor for coupling a substantial portion of a voltage level applied to said first voltage source node to said single-poly floating gate with a coupling ratio greater than 90%, said floating gate NMOS storage transistor has cell capacitance Ccell, said first PIP or MIM capacitor has capacitance CA which is greater than Ccell, and said second PIP or MIM capacitor has capacitance CB, and a ratio defined by (CA+Ccell)/CB is greater than 10.