Patent ID: 7984270
Filing Date: 2011-07-19
Classification: G06F

Abstract:
1. A method of scheduling execution of an instruction in a processor having at least one cascaded delayed execution pipeline unit having four or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; determining if at least one arithmetic instruction is in the issue group, and if so, scheduling the at least one arithmetic instruction in one of the four or more execution pipelines based upon a first prioritization scheme; determining if there is an issue conflict for one of the four or more execution pipelines, the issue conflict corresponding to multiple arithmetic instructions being prioritized to the same pipeline; resolving the issue conflict by implementing a second prioritization scheme by scheduling all but one of the at least one arithmetic instruction causing the issue conflict in a different execution pipeline, wherein the second prioritization scheme is based on a stall delayed penalty; and scheduling execution of the issue group of instructions in the cascaded delayed execution pipeline unit; wherein the first prioritization scheme prioritizes the arithmetic instruction dealing with multiple long operations in a following dependency chain as having a highest priority, the arithmetic instruction with one long operation in a following dependency chain as having a second highest priority, the arithmetic instruction dealing with multiple ALU operations in a following dependency chain as having a third highest priority, the arithmetic instruction having an end of chain condition as having a fourth highest priority, and the arithmetic instruction being an independent instruction with no dependency as having a lowest priority.