Patent ID: 6229384
Filing Date: 2001-05-08
Classification: G05F

Abstract:
A semiconductor integrated circuit comprising:a voltage regulating transistor consisting of a depletion-type N channel FET including a current path having one end to which a first voltage is supplied, and an other end connected to an internal circuit; anda control circuit for generating a gate voltage for said voltage regulating transistor, said control circuit supplying the gate voltage to a gate of said voltage regulating transistor, said voltage regulating transistor generating a second voltage lower than the first voltage used in said internal circuit, from said first voltage,wherein said control circuit further comprises:a detection circuit for detecting a threshold voltage of said voltage regulating transistor;a first current-voltage converting circuit for converting a current corresponding to the threshold voltage detected by said detection circuit, into a voltage;a differential amplifying circuit having an input end to which a reference voltage is supplied, and an other input end to which an output voltage of said first current-voltage converting circuit is supplied; anda second current-voltage converting circuit connected between an output end of said differential amplifying circuit and the other input end thereof, for rendering said differential amplifying circuit to operate as an inverse amplifying circuit, said differential amplifying circuit outputting a voltage obtained by compensating the threshold voltage, from the output end thereof.