Patent ID: 6438830
Filing Date: 2002-08-27
Classification: H01L,H05K,Y10T

Abstract:
A method for making a plastic pin grid array comprising a circuitized laminate carrier having a top surface and a bottom surface, a centrally disposed dielectric material, and at least one transverse through-hole which defines an inner-surface with a corresponding at least one solid pin inserted therein and having a gold surface, the process including the steps of:disposing a layer of gold on said inner surface of said at least one through-hole in said circuitized laminate carrier, inserting at least one solid pin blank having a gold surface into said at least one through-hole, deforming said at least one solid pin blank to form at least one pin with a gold surface which directly contacts substantially throughout said inner surface said layer of gold disposed on said inner surface of said at least one through-hole, said laminate carrier further including at least one conductor of a metal plane disposed in said dielectric material, wherein said at least one conductor is electrically connected to said gold on said inner surface of said at least one through-hole.