Patent ID: 7608908
Filing Date: 2009-10-27
Classification: H01L

Abstract:
1. An integrated electronic circuit (IC) embodying an isolation wall, comprising: a semiconductor (SC) substrate of a first conductivity type and substrate doping concentration; a further semiconductor (SC) layer overlying the substrate and having an upper surface, wherein the further SC layer comprises a first region of the first conductivity type and a first doping concentration less than the substrate doping concentration overlying the substrate, a second region of a second, opposite, conductivity type and a second doping concentration overlying the first region, a third region of the second conductivity type and third doping concentration higher than the second doping concentration overlying the second region, and a fourth region of the second conductivity type and fourth dopant concentration less than the third doping concentration overlying the third region and extending substantially to at least a part of the upper surface; and a dielectric lined isolation trench extending from the upper surface through the fourth, third, second and part of the first regions toward the substrate.