Patent ID: 6823032
Filing Date: 2004-11-23
Classification: H03L,H04J,H04L

Abstract:
A telecommunication device including a clock generation unit (2) having an input (10) for a reference clock (fR), including an electrical circuit arrangement which has a phase-locked loop (4) for converting the reference clock (fR) into a working clock, wherein the circuit arrangement has circuit portions (16a, 16b; 20a, 20b) provided for different reference clocks (fR) and one of the circuit portions (16a, 16b; 20a, 20b) can be selected, and wherein the circuit portions (20a, 20b) include each a divider module (20a, 20b) integrated especially with the phase-locked loop (4) for converting the reference clock (fR) assigned to the circuit portion (20a; 20b) into a plurality of working clocks, and the divider modules (20a, 20b) are arranged so that several of the working clocks that can be generated by them are substantially the same.