Patent ID: 6255183
Filing Date: 2001-07-03
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device with a MOS transistor, said method comprising:forming a gate dielectric and a gate electrode on a surface of a silicon substrate, the gate dielectric and the gate electrode having sidewalls aligned with each other;exposing the surface of the substrate next to the gate electrode;forming a layer of semiconductor material consisting of Si.sub.1-x Ge.sub.x with 0.1<x<0.6, on the sidewalls of the gate dielectric and the gate electrode, the layer of semiconductor material extending to the surface of the substrate;implanting ions with the gate electrode and the layer of semiconductor material acting as a maskcarrying out a heat treatment so as to form a source zone and a drain zone through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material; consisting of Si.sub.1-x Ge.sub.x, with 0.1<x<0.6; and,after the heat treatment, selectively etching away the layer of semiconductor material consisting of Si.sub.1-x Ge.sub.x, with 0.1<x<0.6 to expose the sidewalls and the surface of the substrate.