Patent ID: 6794280
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method of fabricating a non-volatile memory, comprising the steps of:providing a substrate; forming a longitudinal strip of stacked layer over the substrate, wherein the longitudinal strip is a stack that includes a gate dielectric layer, a conductive layer and a cap layer; forming a buried bit line in the substrate on each side of the longitudinal strip; patterning the longitudinal strip to form a plurality of stacked blocks; forming a dielectric layer over the substrate, wherein the dielectric layer exposes the cap layers of the stacked blocks; removing the cap layers of some of the stacked blocks to form a plurality of first opening exposing a portion of the conductive layer of the stacked blocks; and forming a word line over the dielectric layer and filling the first openings to connect the portion of the conductive layer exposed by the first opening of the stacked blocks in the same row serially to form a plurality of coding memory cells, wherein the coding memory cells having the word line connecting to the conductive layer of the stacked blocks are in a first data state and the coding memory cells having the word line connecting to the cap layers of the stacked blocks are in a second data state.