Patent ID: 8102187
Filing Date: 2012-01-24
Classification: G11C

Abstract:
1. A method for calibrating an integrated circuit (IC) comprising at least one programmable digital logic cell, said programmable digital logic cell providing a plurality of different accessible circuit configurations or comprising a voltage level controller, comprising: measuring at least one electrical performance parameter that can affect a processing speed of said programmable digital logic cell or at least one parameter that can affect said electrical performance parameter to obtain calibration data using a reference device, and programming said programmable digital logic cell to select a first of said plurality of different circuit configurations or a voltage level output by said voltage level controller based on said calibration data, wherein said programming changes said processing speed of said programmable digital logic cell, wherein said measuring and said programming are performed during wafer probing of a wafer comprising said IC and a plurality of other ICs, and wherein said wafer includes said reference device.