Patent ID: 7186593
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: forming a window layer on an integrated circuit substrate that defines a fuse region such that the window layer is formed at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device; forming a conductive layer pattern and a buffer pattern on the integrated circuit substrate between the integrated circuit substrate and the window layer, the buffer pattern being between portions of the conductive layer pattern on the integrated circuit substrate; and forming a fuse pattern between the buffer pattern and the window layer; wherein forming the buffer pattern comprises: forming a first buffer pattern; forming a first insulation layer between the first buffer pattern and the fuse pattern, the fuse being formed on the first insulation layer; forming a second buffer pattern between the first buffer pattern and the integrated circuit substrate; and forming a second insulation layer between the second buffer pattern and the first buffer pattern, the conductive layer pattern and the first buffer pattern being formed on the second insulation layer.