Patent ID: 6198679
Filing Date: 2001-03-06
Classification: G11C

Abstract:
Semiconductor memory device comprising a memory array composed of plural memory cells arranged at positions where plural bit line pairs cross plural word lines, plural sense amplifiers electrically connected to the plural bit line pairs, respectively, for determining the potential difference between the bit line pairs, input/output line pairs that are used to transfer the data read from the memory cells and the data to be written into the memory cells, plural first switch circuits that electrically connect the plural sense amplifiers to the input/output line pairs, respectively, a timing control signal generator for generating a timing control signal, a row decoder circuit that activates one of the plural word lines corresponding to a row address signal, and a column decoder circuit that provides a column select signal for selecting a first switch circuit from the plural first switch circuits corresponding to the timing control signal and a column address signal; said timing control signal generator generating a timing control signal during a data write operation, having a pulse width that it is shorter than the pulse width of a timing control signal during a data read operation; during a data write operation, the width of the pulse used to activate the column select signal is shorter than the width of the pulse used to activate the column select signal during a data read operation.