Patent ID: 6282124
Filing Date: 2001-08-28
Classification: G11C,H01L

Abstract:
A method of erasing an array or part of an array of nonvolatile memory cells, said cells comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of the drain region with a thin dielectric layer therebetween and extending over a portion of said channel, further referred to as the floating-gate channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and further comprising a program gate capacitively coupled through a dielectric layer to said floating gate, said array or said part of an array comprising a number of rows of said cells, wherein said control gates of said cells on the same row are connected to a common wordline, and said program gates of said cells are connected to a common program line, the method comprising the steps of:applying a first negative voltage of about -7V or below to at least one of said program lines and to at least one of said wordlines thereby coupling a negative voltage to said floating gates of said cells that share both said wordline and said program line; andapplying an on-chip generated voltage higher than the supply voltage to said common substrate of said cells to thereby cause a tunneling current of electrons to flow from said floating gates of said cells towards said drain regions of said cells while achieving simultaneous erasure of said memory cells sharing both said wordline and said program line without the need for high negative voltages.