Patent ID: 7730288
Filing Date: 2010-06-01
Classification: G06F

Abstract:
1. A method of executing instructions in a processor, the method comprising: receiving a first load instruction and a second load instruction; issuing the first load instruction and the second load instruction to a cascaded delayed execution pipeline unit having at least a first execution pipeline and a second execution pipeline, wherein the second execution pipeline executes an instruction in a common issue group in a delayed manner relative to another instruction in the common issue group executed in the first execution pipeline; accessing a cache by executing the first load instruction and the second load instruction, wherein a delay between execution of the first load instruction and the second load instruction allows the cache to complete the access with the first load instruction before beginning the access with the second load instruction; and wherein the first load instruction and the second load instruction are decoded and scheduled for execution after the first load instruction and the second load instruction are fetched from a level two cache and before the first load instruction and the second load instruction are placed in a level one cache.