Patent ID: 7587560
Filing Date: 2009-09-08
Classification: G06F,G11C

Abstract:
1. A method of operating a controller for a memory device, the method comprising: receiving a first command at a first latch of the controller from a first processor external to the memory device; sending the first command from the first latch to a second latch of the controller upon receiving a second command at the first latch from a command user interface of the memory device; sending the first command from the second latch to a first gate of the controller during a first clock phase of the controller; sending the first command from the first gate to a second gate of the controller in response to receiving a control signal at the first gate from a second processor of the controller, wherein the second processor generates the control signal in response to the second processor executing an instruction of an algorithm of the second processor; sending the first command from the second gate to a third latch of the controller during a second clock phase of the controller; sending the first command from the third latch to the second processor; and resetting the third latch.