Patent ID: 7467336
Filing Date: 2008-12-16
Classification: G01R,H04L

Abstract:
1. A measurement circuit, comprising: a windowed comparator operative to receive an input signal and generate an output signal having a first value when the input signal is within a desired voltage region; a sampling device, coupled to the windowed comparator, operative to sample the output signal and generate a sampled signal at desired time intervals, the sampled signal having a first logical value when the sampled signal is within the desired voltage region; an event array counter, coupled to the sampling device, operative to generate a count value signal representing the number of sampled inputs within one or more desired time offsets and the desired voltage region; a trigger processing circuit, coupled to the event array counter, operative to generate a bit offset signal that controls the counting of the event array counter in response to a test pattern signal; and a measurement circuit, wherein the desired time interval is determined by a programmable clock signal, and wherein the trigger processing circuit further includes at least one clock counter and a first signal comparator, the clock counter generating the bit offset signal in response to the programmable clock signal.