Patent ID: 7362628
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a defective cell block; a normal cell block adjacent to the defective cell block; a first redundant cell block; a second redundant cell block, each of the first redundant cell block, the second redundant cell block, the defective cell block, and the normal cell block including a separate plurality of memory cells organized into a plurality of rows and a plurality of columns, all of the memory cells in the defective cell block being replaced by memory cells in the first redundant cell block, at least some of the memory cells in the normal cell block being replaced by memory cells in the second redundant cell block; a programmable circuit for storing a complete address of the defective cell block; a first address generator for generating, from the stored address of the defective cell block and an input address signal selecting the defective cell block, a first redundant address signal selecting the first redundant cell block; a second address generator for generating, from the stored address of the defective cell block and an input address signal selecting the normal cell block adjacent to the defective cell block, a second redundant address signal selecting the second redundant cell block; and a decoding circuit for decoding the first and second redundant address signals to generate signals selecting memory cells in the first and second redundant cell blocks, wherein the second address generator comprises: the decoding circuit combines the upper enable signal with the upper comparison output.