Patent ID: 8745559
Filing Date: 2014-06-03
Classification: G06F

Abstract:
1. A method, comprising: a) creating a technology file adapted for use by an electronic design automation tool, the technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process; b) creating a netlist based on the technology file, the netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of the at least one die; c) simulating a performance of the integrated circuit based on the netlist; d) adjusting, using a processor, the conductors in the metal layer of the at least one die based on the simulation to reduce the at least one of the capacitive or the inductive couplings due to misalignment attributable to the multi-patterning process; e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings; and f) storing a data file representing a model of the integrated circuit in a non-transient computer readable storage medium.