Patent ID: 7432206
Filing Date: 2008-10-07
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a structure on an integrated circuit, comprising: forming a first layer of material having a top surface; forming a second layer of material over the top surface of the first layer; applying an etch mask over the second layer, the etch mask defining a pattern for a first structure to be formed from the first layer of material; etching the second layer of material and the first layer of material according to the etch mask, leaving the first structure in the first layer of material having a first width, and a portion of the second layer of material over the first structure; trimming the etch mask to formed a trimmed etch mask, the trimmed etch mask defining a more narrow pattern for a second structure to be formed from the second layer of material over the first structure; and etching the second layer of material according to the more narrow etch mask to form the second structure, the second structure having a second width that is less than the first width, and being self-centered over the first structure.