Patent ID: 8441111
Filing Date: 2013-05-14
Classification: H01L

Abstract:
1. A microelectronic package, comprising: a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, the apertures having first and second parallel axes extending in directions of the lengths of the respective apertures, the second surface having a central region disposed between the first and second axes; first and second microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, each microelectronic element having memory storage array function; a plurality of terminals exposed at the second surface in the central region thereof, the terminals configured for connecting the microelectronic package to at least one component external to the package; and leads electrically connected between the contacts of each microelectronic element and the terminals, each lead having a portion aligned with at least one of the apertures, wherein the terminals are configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements.