Patent ID: 6545531
Filing Date: 2003-04-08
Classification: G11C

Abstract:
A power voltage driver circuit for a low power operation mode in a semiconductor memory device, comprising:a constant voltage generating unit for generating a first constant voltage and a second constant voltage; a clock input buffer unit using an internal step-down voltage as a power source; a control unit for receiving an operation control signal indicating the low power operation mode; a voltage comparing unit controlled in response to the output signal from the control unit, for stopping the operation in the low power operation mode, and receiving the first and second constant voltages in the other operation modes, and generating a signal by comparing and amplifying the first and second constant voltages with a reference voltage; and a driver unit controlled in response to the output signal from the control unit and the output signal from the voltage comparing unit, for generating the internal step-down voltage by using a first external power voltage in the other operation modes, and by using a second external power voltage in the low power operation mode.