Patent ID: 6812042
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method for fabricating a ferroelectric memory device, comprising the steps of:a) forming an interfacial insulation layer on a semiconductor substrate; b) forming a stack pattern of a lower electrode and a hard mask on the interfacial insulation layer; c) forming an isolating insulation layer on an entire surface having the stack pattern; d) planarizing an isolating insulation layer until exposing a surface of the hard mask; e) removing the hard mask by using a liquid chemical; f) forming a ferroelectric layer on an entire surface having the lower electrode exposed after the hard mask is removed; g) forming an oxygen vacancy compensation layer on the ferroelectric layer; h) forming a conductive layer for an upper electrode on the oxygen vacancy compensation layer; and i) patterning the conductive layer and the oxygen vacancy compensation layer consecutively.