Patent ID: 7022572
Filing Date: 2006-04-04
Classification: B82Y,G11C

Abstract:
1. A method for manufacturing an integrated circuit memory device comprising: providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region; and providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line; wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and wherein the first selected Y-line pulse substantially falls within the selected X-line pulse.