Patent ID: 8656237
Filing Date: 2014-02-18
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a substrate of semiconductor material; B. functional core circuitry formed on the substrate, the functional core circuitry including functional flip-flops; C. a stimulus input lead; D. first and second scan paths formed on the substrate, each scan path having a stimulus input, connections with the functional core circuitry for communicating test patterns to and from the functional core circuitry, and a response output, each scan path including functional flip-flops of the functional core circuitry that, in a test mode, are connected in series, and the stimulus input of the first scan path being coupled to the stimulus input lead; and E. first multiplexer circuitry having a first input coupled to the stimulus input lead, a second input connected to the response output of the first scan path, a control input, and an output connected to the stimulus input of the second scan path.