Patent ID: 6807645
Filing Date: 2004-10-19
Classification: G01R

Abstract:
Apparatus for implementing enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures comprising:a plurality of sequential channels under test; a plurality of first multiplexers; a respective one of said plurality of first multiplexers coupled between adjacent sequential channels; each of said first multiplexers selectively receiving a first data input in a first scan mode with said sequential channels configured in a common scan path and a second data input in a second scan mode with each said sequential channels configured in a separate scan path responsive to a first control signal; a second multiplexer, coupled between a test data output of a last sequential channel and said first data input of a first sequential channel; said second multiplexer selectively receiving said test data output of said last sequential channel and an external test data input responsive to a recirculate control signal; a first multiple input signature register (MISR), said first multiple input signature register including multiple MISR inputs coupled to a respective one of said plurality of sequential channels under test; a blocker function coupled between said first multiple input signature register and said plurality of sequential channels under test; said blocker function configured for blocking all MISR inputs except for a single MISR input receiving said test data output of said last sequential channel responsive to said recirculate control signal; and a second MISR shadow register coupled to said first multiple input signature register.