Patent ID: 6337173
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method for fabricating a capacitor electrode on a semiconductor substrate on which a transistor having a diffusion region is formed, comprising the steps of:forming a first insulating layer over the semiconductor substrate; patterning the first insulating layer to expose a portion of the diffusion region as a window; forming a first conducting layer over the semiconductor substrate and filling in the window; forming a second insulating layer over the first conducting layer; forming a photoresist layer over the second insulating layer; patterning the photoresist layer through an interfering exposure step using a holography technology; etching anisotropically the second insulating layer using the patterned photoresist layer as a mask, thereby forming a plurality of openings in which the first conducting layer is exposed; etching anisotropically the first conducting layer using the second insulating layer as a mask; removing the photoresist layer and the second insulating layer, thereby leaving the first conducting layer as a lower capacitor electrode; forming a dielectric layer over the lower capacitor electrode; and forming a second conducting layer over the dielectric layer as an upper capacitor electrode.