Patent ID: 6822483
Filing Date: 2004-11-23
Classification: G01R

Abstract:
A bang-bang phase detector circuit, comprising:a data signal line; a clock signal line; a delay cell having an input coupled to the data signal line; a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line; the first double flip-flop including a first flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second flip-flop having a data input coupled to an output of the first flip-flop and a clock input coupled to the clock signal line; a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line; a NOR circuit having a first input coupled to an output of the second flip-flop of the first double flip-flop and a second input coupled to an output of the second double flip-flop; a lag output signal line coupled to an output of the NOR circuit; and a lead output signal line coupled to the output of the second double flip-flop.