Patent ID: 6333868
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells on a semiconductor substrate, wherein said memory cell array includes a differential amplifier circuit serving as data input/output terminals of said memory cell array when data is written in or read from a selected memory cell;a plurality of input/output pads, provided on said semiconductor substrate, for writing data to said memory cells and reading data from said memory cells; anda data bus that connects said differential amplifier and said input/output pads, wherein said data bus includes a plurality of write data lines dedicated for writing data to said memory cells and a plurality of read data lines dedicated for reading data from said memory cells, wherein said plurality of write data lines have mutually parallel portions and said plurality of read data lines have mutually parallel portions, wherein at least said parallel portions of said write data lines are arranged alternately with said read data lines in an arrangement direction of said parallel portions on said semiconductor substrate, and wherein said write data lines are held at a predetermined potential level when data is read and said read data lines are held at the predetermined potential level when writing data, to respectively function as shielded lines.