Patent ID: 7457998
Filing Date: 2008-11-25
Classification: G01R

Abstract:
1. An apparatus for scan testing of a semiconductor device, the apparatus comprising: a master latch having a data input, a data output, and a control input, the control input being coupled to a clock signal, the master latch to store data in response to the clock signal; a scan latch having a data input, a data output, and a first control input, the data input of the scan latch being coupled to the data output of the master latch, the scan latch to receive and to store data from the master latch in response to a scan enable signal indicating a scan mode; and a functional latch having a data input, a data output, and a first control input, the data input of the functional latch being coupled to the data output of the master latch, the functional latch to receive and to store data from the master latch in response to the scan enable signal indicating a functional mode.