Patent ID: 7494858
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method comprising: forming an insulator on a substrate; forming a gate on the insulator; forming a plurality of sidewall spacers on the lateral surfaces of the gate; and etching, with a wet etch, a source region and a drain region in the substrate, the wet etch substantially selective to a crystallographic plane in the substrate; forming, with the wet etch, a facet in the {010} crystallographic plane of the substrate in the source region and a facet in the {010} crystallographic plane of the substrate in the drain region, the {010} facets extending laterally beneath the gate into the substrate region directly under the gate. forming, with the wet etch, a facet in the {111} crystallographic plane of the substrate in the source region and a facet in the {111} crystallographic plane of the substrate in the drain region.