Patent ID: 8661293
Filing Date: 2014-02-25
Classification: G06F

Abstract:
1. A method for testing a computer system, the method comprising: testing the computer system, by a sequencer, using test modules arranged in a first sequence, wherein each of the test modules is for testing at least a portion of the computer system; generating an interrupt by a test module, wherein the interrupt is generated in response to encountering an error during testing, or in response to the test module requiring an operator to complete a particular portion of testing; responsive to the interrupt generated by the test module in the modules, determining if the operator is available to respond to the interrupt; responsive to determining that the operator is available to respond to the interrupt, arranging, by the sequencer, the test modules into a second sequence based on a first policy; and responsive to determining that the operator is unavailable to respond to the interrupt, arranging, by the sequencer, the test modules into a third sequence based on a second policy.