Patent ID: 6989305
Filing Date: 2006-01-24
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor device comprising a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method of manufacturing a semiconductor device comprising the steps of: (a) forming a gate insulation layer above a semiconductor layer; (b) forming a first conductive layer above the gate insulation layer; (c) forming a stopper layer above the first conductive layer; (d) patterning the stopper layer and the first conductive layer, to form a stack of layers formed of that stopper layer and that first conductive layer; (e) forming a first insulation layer at least over the semiconductor layer and both side surfaces of the first conductive layer; (f) forming a second conductive layer over an entire surface of the memory region, and forming a first control gate in the form of a side wall on each of two opposed side surfaces of the first conductive layer, with the first insulation layer interposed with respect to the semiconductor layer, by anisotropic etching of the second conductive layer; (g) removing oxide films from a surface of the first control gate; (h) using the first control gate as a mask to remove part of the first insulating layer, and defining part of the remaining first insulating layer under the removed portion as a second insulating layer; (i) forming a third conductive layer over the entire surface of the memory region; (j) forming a second control gate on a side surface of the first control gate, with the second insulation layer interposed with respect to the semiconductor layer, by anisotropic etching of the third conductive layer; (k) forming an impurity layer to be a source region or a drain region within the semiconductor layer; (l) forming a third insulation layer over the entire surface of the memory region then removing the third insulation layer to expose at least part of the stopper layer; and (m) removing the stopper layer, then forming a fourth conductive layer and patterning the fourth conductive layer to form a word line.