Patent ID: 7446581
Filing Date: 2008-11-04
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: an inverter that inverts and outputs first output data; a first pull-up circuit which takes in, as a pull-up control signal, input data input in synchronization with a clock signal and, when the pull-up control signal takes one value, pulls up the first output data input to the inverter, the first pull-up circuit including a first gate circuit and a first p-channel MOS transistor, the input data being supplied to a gate of the first p-channel MOS transistor via the first gate circuit; a first pull-down circuit which takes in, as a pull-down control signal, the input data input in synchronization with the clock signal and, when the pull-down control signal takes a second value, pulls down the first output data input to the inverter, the first pull-down circuit including a second gate circuit and a first n-channel MOS transistor, the input data being supplied to a gate of the first n-channel MOS transistor via the second gate circuit; a first feedback circuit formed of a first path including a second p-channel MOS transistor, the first path feeding back a first feedback signal corresponding to the first output data to the gate of the first p-channel MOS transistor included in the first pull-up circuit; and a second feedback circuit formed of a second path including a second n-channel MOS transistor, the second path being separate from the first path, the second path feeding back a second feedback signal corresponding to the first output data to the gate of the first n-channel MOS transistor included in the first pull-down circuit, wherein a power supply voltage is supplied to a first end of a current path of the first p-channel MOS transistor, a reference voltage is supplied to a first end of a current path of the first n-channel MOS transistor, and a second end of the current path of the first p-channel MOS transistor is directly connected to a second end of the current path of the first n-channel MOS transistor, wherein the first gate circuit, the second gate circuit, the first feedback circuit, and the second feedback circuit are supplied with clock signals used for controlling an operation-enabled state and an operation-disabled state: