Patent ID: 7730470
Filing Date: 2010-06-01
Classification: G06F

Abstract:
1. A system, comprising: a processor; and memory coupled to the processor, wherein the memory comprises program instructions executable by the processor to implement a code analyzer configured to: analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address, wherein the memory address is calculated during the execution from values stored in one or more registers of the execution engine, wherein the instruction stream specifies an instruction timestamp for each of a plurality of instructions in the instruction stream, wherein said analyze comprises: for each register modifying instruction in the instruction stream that stores a value into a register of the one or more registers, update a register timestamp associated with the register to indicate the earliest instruction timestamp at which the value could have been computed during the execution of the instruction stream; and identify one or more specific registers whose values are used to calculate the memory address referenced by the given memory reference instruction; wherein the earliest point in time is indicated by the latest resister timestamp among the resister timestamps of the one or more specific resisters when the given memory reference instruction is executed; and generate an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.