Patent ID: 7710773
Filing Date: 2010-05-04
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array comprising a plurality of upper and lower memory strings, each of the plurality of upper and lower memory strings having electrically erasable and programmable memory cells serially connected, each of the plurality of upper and lower memory strings having a plurality of odd-state memory cells storing therein an odd number of threshold voltage states and at least one even-state memory cell storing therein at least one even number of threshold voltage states; a plurality of bit lines, each of the plurality of bit lines connected to one end of a corresponding one string of the plurality of upper memory strings through corresponding upper string select transistors and to one end of a corresponding one string of the plurality of lower memory strings through corresponding lower string select transistors; a common source line, the common source line connected the other end of the plurality of upper and lower memory strings through corresponding ground select transistors of the plurality of upper and lower memory strings; and a plurality of word lines which are connected to respective cells in the plurality of upper and lower memory strings wherein reading and programming a bit of data from the odd-state memory cells is performed by enabling more than one word line to be selected.