Patent ID: 6899602
Filing Date: 2005-05-31
Classification: B24B,B24D,Y10S

Abstract:
1. A method of polishing a patterned semiconductor substrate including the step of polishing the semiconductor substrate with a porous polishing pad, the porous polishing pad having a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer, the non-fibrous polishing layer having a polishing surface with a pore count of at least 500 pores per mm 2 and the pore count (per mm 2 ) decreases below the polishing layer and a surface roughness Ra between 0.01 and 3 μm and maintaining the polishing surface with the pore count of at least 500 pores per mm 2 for at least 50 patterned wafers.