Patent ID: 7856075
Filing Date: 2010-12-21
Classification: H03L

Abstract:
1. A clock supply circuit comprising: an averaging unit that inverse-quantizes digital signals, averages the digital signals over a certain period of time, and sequentially outputs the averaged digital signals; a PLL circuit that includes a divider and a voltage-controlled oscillator, the voltage-controlled oscillator outputting an output signal to the outside, the output signal having a frequency in phase synchronization with an input signal in accordance with a dividing rate of the divider; an output frequency value storing unit that stores a digital signal obtained by sampling and quantizing the frequency of the output signal of the PLL circuit, the digital signal being sequentially stored in chronological order; an error detecting unit that detects a frequency error in the input signal to be input to the PLL circuit; and a signal switching unit that sequentially inputs a signal, instead of the input signal, to the PLL circuit after the error detecting unit detects a frequency error in the input signal, the signal having a frequency inverse-quantized in accordance with the dividing rate of the divider, the signal being output from the averaging unit, wherein the averaged digital signals are selected instead of input signals when frequency errors are found in the input signals, and wherein the averaging unit performs an averaging operation to absorb an error in terms of time with respect to the frequency of each digital signal at the time of storage of the digital signal into the output frequency value storing unit.