Patent ID: 9007857
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A domino SRAM (static random access memory), comprising: a local bit line; a global bit line; an SRAM cell coupled to the global bit line through the local bit line and configured to store one of a first logical value or a second logical value; precharge logic configured to precharge the global bit line to a non-zero precharge voltage for a period prior to a non-read operation and configured to charge the global bit line to a boosted voltage that is greater than the precharge voltage for a period prior to a read operation; discharge logic configured to maintain the global bit line at the boosted voltage for the read operation when reading the first logical value stored on the SRAM cell and configured to discharge the global bit line to a discharge voltage that is less than the precharge voltage for the read operation when reading the second logical value stored on the SRAM cell; and sense logic configured to output the first logical value when the global bit line is at the boosted voltage and configured to output the second logical value when the global bit line is at the discharge voltage.