Patent ID: 8966140
Filing Date: 2015-02-24
Classification: H04L

Abstract:
1. A data transfer apparatus comprising: a plurality of input ports, each of the plurality of input ports including: an input buffer configured to store input data, each piece of the input data including destination information indicating a destination of the each piece of the input data, a first buffer monitoring unit configured to monitor a first usage rate of the input buffer, the first usage rate being a ratio of a portion of the input buffer, which is currently used by the stored input data, to a total storage capacity of the input buffer, and a first frequency control unit configured to control a first operating frequency of the input buffer on the basis of the first usage rate; a plurality of output ports, each of the plurality of output ports including: an output buffer configured to store output data, a second buffer monitoring unit configured to monitor a second usage rate of the output buffer, the second usage rate being a ratio of a portion of the output buffer, which is currently used by the stored output data, to a total storage capacity of the output buffer, and a second frequency control unit configured to control a second operating frequency of the output buffer on the basis of the second usage rate; and a switch unit provided between the plurality of input ports and the plurality of output ports and configured to supply a piece of the input data, as a piece of the output data, to the output port corresponding to the destination of the piece of the input data on the basis of the destination information of the piece of the input data, wherein the first and second frequency control units are each configured to include a gate circuit that is inserted in a supply path of a clock signal; and the first and second operating frequencies are reduced based on the first and second usage rates, respectively, by controlling the gate circuit so that clock pulses are cut off or passed through to a circuit area including the input or output buffer, beyond the gate circuit.