Patent ID: 8832388
Filing Date: 2014-09-09
Classification: G06F

Abstract:
1. A system comprising: a plurality of compute nodes including a writing compute node and multiple reading compute nodes, the multiple reading compute nodes including a first reading compute node having a first local cache and a second reading compute node having a second local cache; a shared globally addressable memory configured to enable access to shared data by the plurality of compute nodes; and a memory interface configured to: process memory requests sent to the shared globally addressable memory from the plurality of compute nodes, allocate a read-only memory location in the shared globally addressable memory and write read-only data provided by the writing compute node to the read-only memory location in the shared globally addressable memory, map the read-only data in the globally addressable shared memory as read-only for subsequent accesses by the multiple reading compute nodes while allowing the writing compute node to perform an update on the read-only data in the read-only memory location, provide the multiple reading compute nodes with a first notification that the read-only data is going to be updated and thus unreadable, and provide the multiple reading compute nodes with a second notification after the update that the read-only data is readable, wherein the first reading compute node is configured to cache the read-only data in the first local cache and the second reading compute node is configured to cache the read-only data in the second local cache.