Patent ID: 8006152
Filing Date: 2011-08-23
Classification: G01R

Abstract:
1. A method, comprising: generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs); identifying a first plurality of faults detected by a first MISR of the plurality of MISRs; identifying a second plurality of faults detected by a second MISR of the plurality of MISRs; in the event the first plurality of faults detected by the first MISR does not include any of the second plurality of faults detected by the second MISR and the second plurality of faults detected by the second MISR does not include any of the first plurality of faults detected by the first MISR, coupling the first MISR and the second MISR as an independent MISR pair; applying the test pattern to the DUT to generate a scan chain output; capturing, by the independent MISR pair, the scan chain output to generate a test signature; and comparing the test signature with a known good signature.