Patent ID: 6544853
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A process of fabricating a PMOSFET to affect reduction of negative bias temperature stress in the formed p-type metal oxide semiconductor structure, comprising:a) forming a poly Si gate in a substrate; b) forming a spacer on a sidewall of the gate; c) forming a source/drain extension beside the gate oxide in the substrate; d) implanting F2 between the poly Si gate and said source drain extension at a sufficiently large tilted angle and in amounts of from about 5e12 to about 1e14/cm2 to affect reduction of negative bias temperature stress compared to an equivalent fluorine dose B/BF2 implantation; and e) forming a second spacer on the sidewall of said spacer in step b) and above said source/drain extension.