Patent ID: 7489553
Filing Date: 2009-02-10
Classification: G11C

Abstract:
1. A nonvolatile memory, comprising: an array of memory cells accessible by bit lines and word lines; a group of sensing circuits for sensing conduction currents in a corresponding group of memory cells in parallel wherein individual memory cells of the group as accessible by associated bit lines and a common word line; a word line voltage supply for precharging the common word line to a selected demarcation threshold voltage level relative to which the sensing is to be performed, the demarcation threshold voltage level being one among a set of multiple threshold voltage levels; a bit line voltage supply for precharging the associated bit line substantially to a predetermined voltage level; a set of control signals for controlling the group of sensing circuits to sense the group of memory cells in parallel relative to the selected demarcation threshold voltage; and a bit-line grounding circuit for each sensing circuit to ground the associated bit line responsive to both a sense result of said each sensing circuit and a control signal for enabling bit-line lockout during sensing.