Patent ID: 6770532
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A method for fabricating a memory unit with T-shaped gate for a PMOS, comprising:providing a semiconductor substrate, with a dielectric layer and a patterned hard mask layer with an opening are formed thereon, wherein the opening exposes the dielectric layer; forming a doped spacer on a sidewall of the opening; annealing the doped spacer to form a lightly doped area in the semiconductor substrate; removing the doped spacer and the dielectric in the opening; forming an insulating spacer on the sidewall of the opening; forming a gate dielectric layer on the surface of the opening and the semiconductor substrate and a conducting layer in the opening; removing the patterned hard mask layer; and forming an ion doped area on a side of the lightly doped area in the semiconductor substrate.