Patent ID: 7087528
Filing Date: 2006-08-08
Classification: H01L

Abstract:
1. A method of forming shallow trench isolations in the fabrication of an integrated circuit device comprising: growing a pad oxide layer overlying a semiconductor substrate; depositing a polysilicon layer overlying said pad oxide layer; depositing a nitride layer overlying said polysilicon layer; etching trenches through said nitride layer, said polysilicon layer, and said pad oxide layer into said semiconductor substrate; filling said trenches with an oxide layer wherein said oxide layer extends above a top surface of said nitride layer; etching away said oxide layer except where it overlies said trenches; thereafter first polishing away said oxide layer and a portion of said nitride layer using a first slurry having low selectivity of oxide to nitride and having low-defect properties; removing said nitride layer; and thereafter second polishing away said oxide layer and a portion of said polysilicon layer using a second slurry having high selectivity of oxide to polysilicon to complete formation of said shallow trench isolations in said fabrication of said integrated circuit device.