Patent ID: 8912606
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A method for forming an integrated circuit, comprising: etching a plurality of trenches into a silicon substrate and filling the trenches with a first insulating material to delineate a plurality of spaced-apart silicon fins having a longitudinal axis; forming gate structures overlying said plurality of fins, each of said gate structures extending in a gate width direction that is transverse to said longitudinal axis of said plurality of fins; removing said first insulating material for forming recess trenches between said gate structures and for exposing at least sidewall portions of said spaced-apart silicon fins such that said recess trenches have a depth corresponding to a first height; forming protruding portions of semiconductor material on the exposed sidewall portions of said fins, wherein said protruding portions of semiconductor material comprise an outermost protruded surface and at least one tapered portion, wherein said at least one tapered portion is positioned between said outermost protruded surface and one of said gate structures, said at least one tapered portion being formed such that it has a width that increases with increasing distance from said gate structure, wherein said width of said at least one tapered portion is measured in a plane parallel to said gate width direction; and filling said recess trenches with a second insulating material up to at least said first height.