Patent ID: 6489796
Filing Date: 2002-12-03
Classification: G11C

Abstract:
A semiconductor device, comprising:a voltage detecting portion detecting a potential at a first node supplied with a boosted potential; a clock signal generation circuit generating an source clock signal in accordance with an output from said voltage detecting portion; and a boosting portion boosting an externally applied external power supply potential in accordance with said source clock signal for applying said boosted potential to said first node, said boosting portion including: a precharge circuit precharging a second node to a prescribed potential, a boost circuit boosting a potential at said second node in accordance with said source clock signal, a first field effect transistor of a first conductivity type connected between said first and second nodes, a first drive circuit driving a gate potential of said first field effect transistor in accordance with said source clock signal, a second field effect transistor of a second conductivity type connected between said first and second nodes, and a second drive circuit driving a gate potential of said second field effect transistor in accordance with said source clock signal.