Patent ID: 7405592
Filing Date: 2008-07-29
Classification: H03K

Abstract:
1. A system, comprising: a circuit card comprising an integrated circuit capable of communicating in accordance with a plurality of different communication protocols, the circuit card configured to be coupled to a bus, said integrated circuit further including decoder circuitry configured to switch a plurality of switches to generate at least one output signal, said output signal having a first amplitude and a second amplitude, said decoder circuitry further configured to control a conduction state of each of said plurality of switches to include a first conduction state and a second conduction state, said decoder circuitry being further configured to determine a total number of switch transitions between said first conduction state and said second conduction state for a plurality of switches, said decoder circuitry further configured to reduce the number of switch transitions between binary states of at least one said switch when said output signal goes from said first amplitude to said second amplitude, said decoder circuitry further configured to determine a number of switches that may be left unswitched between said first conduction state and said second conduction state.