Patent ID: 7205188
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A process for the production of high-speed vertical npn-bipolar transistors and complementary MOS-transistors on a chip with implementation of all technological process steps for the production of a vertical structure of a collector, base and emitter in an active region of the npn-bipolar transistors and for lateral structuring of the collector, base and emitter regions prior to production of the wells or the gate insulating layer for the MOS-transistors, wherein finished structures of the npn-bipolar transistors are provided prior to production of the gate insulating layer for the MOS-transistors with a protective layer which during implementation of the technological process steps for production of the MOS-transistors prevents the conversion of silicon into silicon oxide within the finished structures of the npn-bipolar transistors.