Patent ID: 6041148
Filing Date: 2000-03-21
Classification: G06F,G06T

Abstract:
A data extraction system comprising:at least one data storage memory for storing data formatted into a plurality of data samples, each of said plurality of data samples having multiple bits;a data extraction processor, for receiving said data from said data storage memory one processor word at a time, wherein a processor word includes at least two of said data samples, for simultaneously processing said at least two of said data samples in each said processor word, and for generating at least one result record containing information extracted from said data samples in at least one said processor word, said data extraction processor comprising a segmentation processor including:a label computation engine, coupled to said data flow controller, for simultaneously receiving said data samples in each said processor word, for identifying transitions between said data samples and generating transition bit signals for each potential transition, and for computing a label code for each said potential transition using said transition bit signals;a label row FIFO shifter, coupled to said label computation engine, for receiving and storing said label code for each said potential transition;a neighborhood computation unit, coupled to said label computation engine and to said label row FIFO shifter, for receiving current row labels from said label computation engine and previous row labels from said label row FIFO shifter, and for computing connecting relationships to segments in a previous row;a segment processor controller, coupled to said data flow controller, for providing a current segment length; anda segment record generator, coupled to said label computation engine, said segment processor controller and said neighborhood computation unit, for receiving said current row labels, said current segment length, and information about said connecting relationships, and for generating at least one segment record for each transition event; anda data flow controller, coupled between said at least one data storage memory and said data extraction processor, for controlling the flow of processor words into said data extraction processor and the flow of said result records out of said data extraction processor.