Patent ID: 8040435
Filing Date: 2011-10-18
Classification: H04N

Abstract:
1. A synchronization detecting apparatus comprising: a counter counting to a pre-determined counter value in response to a clock signal; an error detector generating an error, which is a difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal; an a line length generator generating a current line length based on the pre-determined counter value and a compensated error, where the compensated error is obtained by automatic compensation of the error, wherein the synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal, wherein the error detector outputs the error obtained by taking a difference between the current counter value and a corrected line length that is a sum of the previous line length and a predetermined offset, and outputs an integral part and a decimal part of the corrected line length as a next synchronization start signal and offset, respectively.