Patent ID: 6542422
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged in a matrix; at least one redundant memory cell column for being substituted for a memory cell column having a defective memory cell among a plurality of memory cell columns for the sake of saving; an address conversion circuit receiving an address signal of L bits (where L is an integer of 2 or more) for selecting said plurality of memory cell columns to apply a prescribed conversion operation to a part-bit having at least one bit among said L bits when necessary; a defect address conversion circuit receiving a defect address signal of L bits, stored in advance, and corresponding to the memory cell column having said defective memory cell to apply an inverse conversion operation, exercised by inverting a relationship between an input and output in said prescribed conversion operation applied by said address conversion circuit, to said part-bit of said defect address signal; an address comparison circuit comparing said address signal before passage through said address conversion circuit and said defect address signal after passage through said defect address conversion circuit with each other; and a select circuit getting access to one of a memory cell column corresponding to said address signal after passage through said address conversion circuit and said redundant memory cell column according to a result of comparison in said address comparison circuit.