Patent ID: 6013549
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A method for manufacturing a DRAM cell capacitor, comprising the steps of:forming a field oxide layer over a semiconductor substrate to define active and inactive regions;forming a pad electrode over the active region;forming an interlayer insulating layer over the pad electrode and the field oxide layer;forming a contact hole in the interlayer insulating layer to expose the pad electrode;forming a conductive layer over interlayer insulating layer and filling up the contact hole;forming a photoresist pattern over the conductive layer to define a capacitor bottom electrode;simultaneously etching an upper portion of the conductive layer using the photoresist pattern as a mask, and forming a polymer on sidewalls of the photoresist pattern to etch the upper portion of the conductive layer and to thereby angle a top edge of the conductive layer;etching a remaining portion of the conductive layer using a combination of the photoresist pattern and the polymer as a mask until an upper surface of the interlayer insulating layer is exposed, to thereby form the capacitor bottom electrode having a top surface, one or more sidewalls, and the top edge formed between the top surface and the one or more sidewalls;removing the photoresist pattern and the polymer;forming an HSG silicon layer on the capacitor bottom electrode in order that the capacitor bottom electrode has a rugged surface, wherein the HSG silicon layer is formed only on the top surface and the one or more sidewalls of the capacitor bottom electrode;forming a capacitor dielectric layer over the capacitor bottom electrode; andforming a capacitor top electrode over the capacitor dielectric layer.