Patent ID: 6232805
Filing Date: 2001-05-15
Classification: H03F,H03K

Abstract:
A buffer circuit arrangement having voltage clamping capabilities, said buffer circuit comprising:first and second power supply rails;an input MOS transistor having a gate for receiving an input signal to be buffered;a current source connected intermediate a source of the input MOS transistor and the first power supply rail;a first clamping MOS transistor having a gate for receiving a first clamping voltage and a source coupled to a source of the input MOS transistor;a second clamping MOS transistor defining a drain-source current path connected in series with a drain-source current path of the input MOS transistor, with the second clamping MOS transistor having a gate for receiving a second clamping voltage; andsubsequent signal processing circuitry having an input coupled to an output of the buffer circuit, wherein the output of the buffer circuit is at a buffer circuit location other than a node intermediate the input MOS transistor and the second power supply rail and other than a node intermediate the first clamping transistor and the second power supply rail.