Patent ID: 7528425
Filing Date: 2009-05-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory having a multitude of memory cells, said semiconductor memory having a substrate, at least one wordline and a first and a second line, wherein each memory cell of said multitude of memory cells comprises: a first doping region disposed in said substrate; a second doping region disposed in said substrate; a channel region disposed in said substrate between said first doping region and said second doping region; a charge-trapping layer stack disposed over said substrate, said charge-trapping layer stack continuously covering said channel region, a portion of said first doping region and a portion of said second doping region; a conductive layer disposed over said charge-trapping layer stack, wherein said conductive layer is electrically floating; and a dielectric layer disposed on a top surface of said conductive layer and on sidewalls of said conductive layer; said first line extending along a first direction and coupled to said first doping region; said second line extending along said first direction and coupled to said second doping region; and said at least one wordline extending along a second direction and being disposed over said dielectric layer; wherein said charge-trapping layer stack is formed as a continuous layer laterally extending beyond said memory cell, said conductive layer disposed on a portion of said charge-trapping layer stack, said portion of said charge-trapping layer stack covering said channel region and said portion of said first doping region and said portion of said second doping region, said dielectric layer being disposed on said top surface and said sidewalls of said conductive layer and on other portions of said charge-trapping layer stack, said other portions being located between conductive layers of memory cells adjacent to one another.