Patent ID: 6770535
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A process for a semiconductor integrated circuit device where a plurality of memory cells which have field effect transistors formed in a semiconductor substrate and capacitor elements connected to the source and drain regions of said field effect transistors are provided, comprising the steps of:(a) forming trenches of which the radius of curvature of the bottom corners is larger than 10 nm in a first semiconductor region of said semiconductor substrate; (b) forming a first gate insulating film through a deposition method inside of said trenches; (c) forming gate electrodes within said trenches and placing said gate electrodes on said first gate insulating film; and (d) forming a second semiconductor region and a third semiconductor region in said first semiconductor region such that said second and said third semiconductor regions have a depth shallower than that of said first semiconductor region and that of said trenches, wherein said second and said third semiconductor regions serve as source and drain regions of said field effect transistor such that a channel forming region thereof is effected at the bottom surface of said trench and two side surfaces of said trench between said second semiconductor region and said third semiconductor region.