Patent ID: 6545519
Filing Date: 2003-04-08
Classification: H03K

Abstract:
Latch circuitry, operable in cycles responsive to at least one timing signal, wherein during such a cycle the latch circuitry captures data at a latch input and holds data at a latch output, the latch circuitry comprising:a first input stage for sampling a first input signal on a first latch input node responsive to a first timing signal, and generating a signal on an intermediate node in the latch circuitry; a second input stage for sampling a second input signal on a second latch input node responsive to a second timing signal, and generating a signal on the intermediate node; and an output stage for generating an output signal on an output node of the latch circuitry responsive to the signal on the intermediate node and a third timing signal, wherein the first input signal has a maximum voltage level and at least one stage of the latch circuitry is operable to effectively shift the voltage level so that the output signal has a higher maximum voltage level than that of the first input signal.