Patent ID: 6574169
Filing Date: 2003-06-03
Classification: G01R

Abstract:
A delay test system for an LSI including an electronic circuit which is selectively operable in a normal mode and a test mode and which has a circuit to be tested and a plurality of flip-flop circuits each of which is serially connected to each other via said circuit to be tested to perform a delay test for said electronic circuit, comprising, in combination:a first clock input terminal which is connected to said plurality of flip-flop circuits and said electronic circuit to input a normal mode clock signal generated in the normal mode; and a second clock input terminal which is connected to said flip-flop circuits and a normal circuit to input a test clock signal; the test mode being carried out in synchronism with a first edge timing of the normal mode clock signal and a second edge timing of the test clock signal while the normal mode is carried out by the use of the normal mode clock signal with the test clock signal kept inactive.