Patent ID: 6104229
Filing Date: 2000-08-15
Classification: H03K

Abstract:
An input buffer circuit for an integrated circuit having a first voltage supply for providing a first supply voltage and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the input buffer circuit comprising:an input terminal;an output terminal; a first p-channel field effect transistor (FET) having a source region coupled to the first voltage supply, a drain region coupled to the output terminal, and a gate electrode coupled to the input terminal;a bias circuit coupled to the drain region of the first p-channel FET, the bias circuit maintaining a voltage at the drain region of the first p-channel FET which is greater than the second supply voltage when a logic high voltage is applied to the input terminal, wherein the bias circuit comprises:a first n-channel FET having a drain region connected to the drain region of the first p-channel FET, a source region connected to the second voltage supply, and a gate electrode; anda second n-channel FET having a source region connected to the gate electrode of the first n-channel FET, a drain region connected to the first voltage supply, and a gate electrode coupled to the input terminal.