Patent ID: 9153241
Filing Date: 2015-10-06
Classification: G10L,G11B,H04Q

Abstract:
1. A signal processing apparatus, comprising: a processor; and a non-transitory memory having stored thereon executable instructions, which when executed by the processor, cause the processor to perform: coding an input signal on a per frame basis; inserting a header in each frame at a regular interval within a coded signal, the coded signal being generated in said coding and being represented by a sequence of frames, and the header indicating management information of the coded signal; determining a frame in which the header is to be inserted, independent of the frames in which the header is inserted in said inserting; and singly inserting the header in the frame determined in said determining, wherein the header, which is inserted in said inserting and said singly inserting, indicates management information of auxiliary data for enlarging channels of the coded signal for reproduction, and wherein the header, which is inserted in said inserting and said singly inserting, (i) indicates the management information of auxiliary data for enlarging channels of the coded signal for reproduction and (ii) includes coding mode information indicating a coding method for coding Inter-channel Intensity Differences.