Patent ID: 7028161
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. A superscalar processing system for executing instructions, wherein the instructions have a prescribed program order, comprising: an instruction fetch unit that concurrently fetches a plurality of instructions from an instruction store; a register file that stores register data corresponding to said plurality of instructions, said register file comprising an integer register file and a floating point register file; a plurality of functional units, said plurality of functional units including an integer functional unit and a floating point functional unit; a register file output bus that concurrently transfers said register data from said register file to said plurality of functional units, said plurality of functional units executing said plurality of instructions regardless of the prescribed program order to generate integer results and floating point results; and an output bus that concurrently distributes said integer results and said floating point results, wherein said output bus distributes at least one of said integer results to said floating point register file and at least one of said floating point results to said integer register file.