Patent ID: 9159716
Filing Date: 2015-10-13
Classification: G06F,H01L

Abstract:
1. A stacked chip layout comprising: a central processing chip having a first area; a first active circuit block over the central processing chip, the first active circuit block having a second area less than the first area; a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block, and a center of the second active circuit block is displaced with respect to a center of the first active circuit block in a first direction parallel to a top surface of the central processing chip; and a third active circuit block over the second active circuit block, the third active circuit block having a fourth area less than the first area, wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first active circuit block and the second active circuit block, and a center of the third active circuit block is displaced with respect to the center of the first active block in a second direction parallel to the top surface of the central processing chip and perpendicular to the first direction.