Patent ID: 7605642
Filing Date: 2009-10-20
Classification: G05F

Abstract:
1. Apparatus comprising: a power supply providing Vss and Vdd; a reference voltage source coupled to Vss and Vdd for generating a reference voltage signal (NBIAS); and a startup circuit coupled to Vss and Vdd and coupled to the reference voltage source to generate a startup signal applied to the reference voltage source to initiate operation of the reference voltage source, wherein the startup circuit is configured to consume no static current once the reference voltage source reaches its normal operating state, and wherein the startup circuit is configured to never generate a stress voltage in any of its transistors, wherein the startup circuit comprises: a fence capacitor (C a first pmos transistor (M a second pmos transistor (M a third pmos transistor (M wherein at least one of the first, second and third PMOS transistors has a maximum gate-source voltage (“stress voltage”) less than Vdd-Vss.