Patent ID: 8996840
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. An I/O controller for a processing unit, wherein the I/O controller is coupled to the processing unit and to a memory, the I/O controller comprising: an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator configured to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator configured to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher configured to forward address translation prefetch information from a data packet received at the I/O link interface to the address translation unit, wherein the prefetcher is configured to forward a Requestor ID (RID) and a virtual address as the address translation prefetch information from the data packet received at the I/O link interface; wherein the address translator is configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory, and wherein the address translation unit further includes a request translation unit configured to translate the Requestor ID (RID) into a RID translation entry (RTE) including a translation table base address for translating at least a part of the virtual address into a translation control entry (TCE) index.