Patent ID: 8785275
Filing Date: 2014-07-22
Classification: G11C,H01L

Abstract:
1. A method of fabricating an electronic device, comprising: forming one or more masking layers on a semiconducting surface of a substrate; forming a plurality of fin-type projections in said semiconducting surface based on said one or more masking layers; forming a plurality of dielectric isolation features based on said one or more masking layers; processing said masking layers and said plurality of fin-type projections to provide an inverted T-shaped cross-section for said plurality of fin-type projections comprising a distal extension portion and a proximal base portion, wherein said plurality of dielectric isolation features have a height being greater that a height of said proximal base portion of said plurality of fin-type projections; forming a plurality of dielectric layers on said distal extension portion, wherein a portion of said plurality of dielectric layers substantially fill a region that extends between a portion of a sidewall of said distal extension portion of said plurality of fin-type projections and a sidewall of said plurality of dielectric isolation features and that extends between said height of said proximal base portion and said height of said plurality of dielectric isolation features; and forming a plurality of gate layers on said plurality of dielectric isolation features and said plurality of dielectric layers.