Patent ID: 9128914
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A semiconductor integrated interface circuit, comprising: a plurality of processing parts which respectively process data appearing on a plurality of bus lines; a receiving part for receiving packets; a distributing part for distributing the received packets in accordance with destinations contained in the received packets; a plurality of accumulating parts for accumulating the packets provided from the distributing part; a plurality of relaying parts for converting the packets accumulated in the accumulating parts into data, and relaying the converted data to said processing parts in response to a relay permission command assigned thereto; and an output controlling part for supplying the relay permission command to a corresponding one of said relaying parts when the distributed packet is determined as a relay permission packet based on packet identification information contained in the distributed packet from said distributing part; wherein said processing parts respectively generate communication data used for debugging, in accordance with the relayed data from the corresponding relaying parts, and output said communication data to a succeeding stage with a debugging function; wherein the plurality of bus lines includes a first inner bus line and a second inner bus line; said distributing part distributes the relay permission packet to the first inner bus line; said output controlling part supplies the relay permission command to accumulating parts connected to the second inner bus line; and a processing part of the plurality of processing parts receives readout data from a bus line of the plurality of bus lines, and transmits the received readout data to the outside as communication data according to a communication protocol.