Patent ID: 7885098
Filing Date: 2011-02-08
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory, comprising: a phase-change memory cell which is programmable at least between a set state and a reset state and which includes a selection element to selectively connect the phase-change memory cell to a sense node; a boosting circuit which receives an internal supply voltage and generates a boosted voltage having a voltage level which is greater than a voltage level of the internal supply voltage; a pre-charge circuit which is driven by the boosted voltage to pre-charge the sense node so that the voltage of the sense node is the boosted voltage before a sensing interval; a biasing circuit which is driven by the boosted voltage to bias the sense node; and a sense amplifier which senses a voltage of the sense node during the sensing interval, wherein the sense amplifier includes a power supply terminal driven by the boosted voltage and an input terminal connected to the sense node, wherein, during the sensing interval, a sensing margin at the sense node between the set state and the reset state is defined by a difference between the boosted voltage and a voltage across the selection element of the phase-change memory cell.