Patent ID: 9111072
Filing Date: 2015-08-18
Classification: G06F

Abstract:
1. A method for generating and executing anti-reverse engineering logic comprising: receiving, by a computing device, at least two sets of input values, wherein at least one of the at least two sets of input values is a non-empty set; executing, by the computing device, one or more functions corresponding to both a combination of the at least two sets of input values and a set of states of the computing device, wherein the one or more functions correspond to a logic to be protected; generating, by the computing device, a set of output values corresponding to both the executed one or more functions and the set of states of the computing device; and outputting, by the computing device, the set of output values, whereby when the set of output values is later used as one of the at least two sets of input values, the method executes the same one or more functions, and whereby an alteration of the set of states of the computing device results in the method executing one or more different functions.