Patent ID: 6526501
Filing Date: 2003-02-25
Classification: G06F

Abstract:
An adapter for assisting debugging of a microprocessor on a single integrated circuit chip, the integrated circuit chip comprising an on-chip CPU with a plurality of registers, a communication bus providing a parallel communication path between the CPU and a first memory local to the CPU, and an external communication port connected to the bus on the integrated circuit chip, the external communication port having an internal connection to the bus of an internal parallel signal format and an external connection to the adapter of a first external format less parallel than the internal parallel format, the adapter comprising:a first communication unit for connection to the external communication port with the first external format; a second communication unit for connection to an external computer with a second external format having a higher latency than the first external format; a second memory local to the adapter; and a processing unit local to the adapter and operable: (a) in a first mode to translate between the first external format and the second external format to allow the external computer to communicate directly with the external communication port; (b) in a second mode to connect the second communication unit to the second memory to allow the external computer to access the second memory; and (c) in a third mode to execute instructions stored in the second memory to transmit data via the first communication unit to the external communication port.