Patent ID: 6154830
Filing Date: 2000-11-28
Classification: G06F

Abstract:
A microprocessor including at least two instruction execution units for decoding and executing instruction codes read from an externally provided common instruction memory, comprising:a first instruction execution unit for supplying an address to said instruction memory and for decoding and executing an instruction code read from said instruction memory in accordance with said address;an instruction cache for storing plural instruction codes read from said instruction memory;a second instruction execution unit for supplying an address to said instruction cache and for decoding and executing an instruction code read from said instruction cache in accordance with said address; anda cache controller for determining whether or not the instruction code specified by said address supplied from said second instruction execution unit to said instruction cache is present in said instruction cache, and when the instruction code is not present, for controlling said second instruction execution unit to suspend decoding and execution of the instruction code and controlling said first instruction execution unit to supplement an instruction block including the instruction code from said instruction memory to said instruction cache.