Patent ID: 8117519
Filing Date: 2012-02-14
Classification: G06F,G11C

Abstract:
1. An error correction circuit coupled to a plurality of memory cells in a memory device, comprising: an error correcting code (“ECC”) generator coupled to the memory cells, the ECC generator operable to recognize data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common, the ECC generator further operable to generate a respective correction code in the first direction for each data bit string in the first direction and generate a respective correction code in the second direction for each data bit string in the second direction; and an ECC controller coupled to the memory cells and the ECC generator, the ECC controller operable to identify each data bit string in the first direction having more than one data bit in error based on the respective correction code in the first direction and identify each data bit string in the second direction having more than one data bit in error based on the respective correction code in the second direction, the ECC controller further operable to cause the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed from a respective existing value to a respective new value different than the respective existing value, and wherein the ECC controller is further operable to determine whether or not at least one of the data bits is still in error after each of the shared data bits has been changed to the respective new value.