Patent ID: 6463529
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A processor-based system comprising:a first bus; a system memory to store information; a processing unit coupled to the first bus, the processing unit including a processor, a cache memory associated with the processor to store a duplicate of a portion of the information, a cache controller to control the cache memory, a numerical processor associated with the processor, a reset input node and a partial-reset input node, wherein the processing unit is reset in response to a system reset signal being asserted at the reset input node and wherein only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at the partial-reset input node; a second bus; bus interface circuitry coupled between the first bus and the second bus; video circuitry coupled for access by the processor through the first bus; a hard disk drive coupled for access by the processor through the first bus; a speaker driver coupled for access by the processor through the first bus; a speaker coupled to the speaker driver; a keyboard controller coupled for access by the processor through the first bus; and a keyboard coupled to the keyboard controller.