Patent ID: 6479377
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of forming an electrical interconnect in a semiconductor device comprising:providing a substrate having two or more transistors with active areas therebetween, the transistors having gate regions wherein the gate regions are not exposed; creating an insulating layer overlying the transistors and the active areas; forming a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area; forming a dielectric material spacer within the contact plug/interconnect opening thereby forming two contact holes; removing insulating material overlying one or more of the active areas including the first active area such that the active areas are exposed; exposing a portion of the gate region of the first transistor; and depositing interconnect material within the contact plug/interconnect opening on the exposed portion of the gate region of the first transistor and the first active area thereby electrically connecting the first transistor to the first active area.