Patent ID: 6281730
Filing Date: 2001-08-28
Classification: H03K

Abstract:
An apparatus for providing an output signal with a controlled slew rate comprising:a signal node having an associated node capacitance and configured to alternately receive first and second output signal currents and in accordance therewith convey an output signal voltage;alternately active first and second complementary node driver circuits coupled to the signal node, each configured to receive said output signal voltage and corresponding first and second input signals, and in accordance therewith, to alternately provide said first and second output signal currents, the first and second node drivers alternately sourcing and sinking first and second output signal currents,wherein the first output signal current has a first constant value when said output signal voltage is within a first predetermined voltage range, and a first non-constant value when said output signal voltage is outside the first predetermined voltage range, andwherein the second output signal current has a second constant value when said output signal voltage is within a second predetermined voltage range, and a second non-constant value when said output signal voltage is outside the second predetermined voltage range;first and second current conveying circuits coupled to the first and second node driver circuits to provide constant input currents as said first and second input signals to the node driver circuit when the output signal voltage is within the first and second predetermined voltage ranges; andfirst and second buffer circuits coupled to the first and second node driver circuits, the first and second buffer circuit being configured to receive first and second digital input signals having first and second digital states, whereinwhen the first and second digital input signals are in said first digital state the first buffer circuit couples first said current conveying circuit to the first node driver circuit and the second buffer circuit couples a first bias voltage to the second node driver circuit to deactivate the second node driver, andwhen the first and second digital input signals are in said second digital state the second buffer circuit couples said second current conveying circuit to the second node driver circuit and the first buffer couples a second bias voltage to the first node driver circuit to deactivate the first node driver circuit.