Patent ID: 6727597
Filing Date: 2004-04-27
Classification: H01L

Abstract:
An integrated circuit comprising:a first plurality of wire bond pads arranged along a horizontal axis comprising power connections, ground connections, and I/O connections; and a plurality of C4 (controlled collapse chip connection) pads arranged in a grid array where a nearest adjoining C4 pad is located diagonally, at least one of said C4 pads being electrically coupled to at least one of said wire bond pads, said C4 pads including a plurality of power connections that are divided into a first set of vertical rows to form a plurality of power buses, ground connections, and I/O connections a second plurality of wire bond pads arranged along a vertical axis comprising power connections, ground connections, and I/O connections and wherein each grid of said C4 pads is defined by the intersection of one of said first wire bond pads and one of said second wire bond pads.