Patent ID: 8713383
Filing Date: 2014-04-29
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode, wherein the test mode control unit controls the one of the first data pads to a stuck state after a read operation is finished, wherein the test mode control unit comprises: