Patent ID: 6930380
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip having a main surface; an internal circuit which is formed on the main surface of the semiconductor chip; an interface circuit which is formed on the main surface of the semiconductor chip and includes a plurality of I/O cells which are arranged to surround the internal circuit in plane; a plurality of bonding pads which are formed on the main surface of the semiconductor chip, are arranged between the interface circuit and sides of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads; power source wiring which is formed on the main surface of the semiconductor chip, is connected to the first and second power source bonding pads in common, and supplies an operational potential to the plurality of I/O cells; a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads; a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first power source bonding pads with second power source bonding pads and a plurality of third bonding wires for connecting a plurality of signal bonding pads with the plurality of signal leads; and a sealing body which seats the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.