Patent ID: 6306733
Filing Date: 2001-10-23
Classification: H01L,Y10S,Y10T

Abstract:
A process for the preparation of a silicon wafer comprising a front surface having an epitaxial layer deposited thereon, a back surface, a central plane between the front and back surfaces, a front surface layer which comprises the region of the wafer between the front surface and a distance, D, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and front surface layer, the bulk region further comprising a concentration of oxygen precipitates, wherein the process comprises:subjecting the wafer to a heat-treatment to form crystal lattice vacancies in the front surface and bulk layers;controlling the cooling rate of the heat-treated wafer to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer and the difference in the concentration of vacancies in the front surface and bulk layers being such that a thermal treatment at a temperature in excess of 750.degree. C., is capable of forming in the wafer a denuded zone in the front surface layer and oxygen clusters or precipitates in the bulk zone with the concentration of the oxygen clusters or precipitates in the bulk layer being primarily dependant upon the concentration of vacancies;subjecting the silicon wafer, to an oxygen precipitation heat treatment to cause the nucleation and growth of oxygen precipitates in the bulk layer, to a size sufficient to stabilize the oxygen precipitates such that they are incapable of being dissolved at temperatures not in excess of 1150.degree. C., with the oxygen precipitate concentration profile being formed according to the vacancy concentration profile such that a denuded zone is formed in the front surface layer; and,depositing an epitaxial layer on at least one surface of the oxygen precipitate stabilized wafer.