Patent ID: 6330697
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A defect leakage screen test apparatus for regulating a p-well voltage of a semiconductor memory device, comprising:a tester adapted to provide initial program load logic signals; and,a semiconductor memory device having logic circuitry comprising:an initial program load decoding logic circuit, adapted to decode input signals and decoding output signals, for decoding said initial program load logic signals such that, when one of said input signals is active, a reference voltage generator circuit is turned on, and a second multiplexor stage within the initial program load voltage reference multiplexor circuit is switched on;said reference voltage generator circuit comprising a voltage divider circuit for creating a reference voltage by generating a voltage level between an internal voltage and a ground voltage;said initial program load voltage reference multiplexor circuit adapted to multiplex different voltage levels from said reference voltage generator circuit, said multiplexor comprising a first multiplexor stage and said second multiplexor stage;a p-well voltage feed-back circuit detecting a back-bias voltage of said semiconductor memory device, and voltage dividing the detected back-bias voltage with a voltage divider circuit;a voltage pump activated to increase said back-bias voltage when said back-bias voltage decreases with respect to said reference voltage; anda differential amplifier circuit comparing said detected back-bias voltage to said reference voltage, and controlling activation of said voltage pump.