Patent ID: 7178126
Filing Date: 2007-02-13
Classification: G06F,H01L,Y02P

Abstract:
1. A method of laying out an integrated circuit having a semiconductor substrate and metal interconnecting lines disposed above the semiconductor substrate, the metal interconnecting lines including a core ring with a first power line and a first around line, the first power line and the first ground line being mutually adjacent, core ring supplying power to circuits surrounded by the core ring, the method comprising: routing a plurality of the metal interconnecting lines across the core ring, for use as input-output (I/O) signal lines; identifying a part of the core ring crossed by comparatively few of the I/O signal lines; laying out at least one metal-oxide-semiconductor (MOS) capacitor unit below said part of the core ring, the MOS capacitor unit having an active area disposed in the semiconductor substrate and an insulated gate electrode disposed on the semiconductor substrate, at least part of the insulated gate electrode being disposed above part of the active area; laying out first contacts connecting the active area to one of the first power line and the first ground line, and; laying out second contacts connecting the insulated gate electrode to another one of the first power line and the first around line.