Patent ID: 6207533
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method for forming an integrated circuit comprising the steps of:providing a substrate;forming a patterned trench mask overlying the substrate;etching the substrate to form a trench in the substrate;forming a first dielectric layer overlying the substrate, wherein the first dielectric layer overlies the patterned trench mask and lies within the trench;forming a patterned masking layer overlying the first dielectric layer;using the patterned masking layer to etch a portion of the first dielectric layer;removing the patterned masking layer;forming an intermediate polishing layer overlying the first dielectric layer, after the patterned masking layer has been removed;forming a second dielectric layer overlying the intermediate polishing layer;polishing the second dielectric layer to expose a portion of the intermediate polishing layer, and to determine a polish rate for the second dielectric layer;using the polish rate for the second dielectric layer to determine a polish time for the first dielectric layer; andpolishing the first dielectric layer for the polish time to expose the patterned trench mask.