Patent ID: 6252819
Filing Date: 2001-06-26
Classification: G11C

Abstract:
A reduced line select decoder for selecting a bit line pair from a pair of bit line pairs to perfrom a read or write operation on the selected bit line pair comprising:a pair of bit line select signals for selecting a bit line pair, the pair of bit line select signals coupled to the bit lines via P-type and N-type transfer device pairs, each transfer device having a controlled current path and a control terminal, the controlled current path of each P-type transfer device coupled between a bit line pair and a sense amplifier, the controlled current path of each N-type transfer device coupled between a bit line pair and a write buffer,wherein the sense amplifier is coupled to receive a sense amplifier control signal to activate a read operation on the selected bit line via a coupled P-type transfer device, and providing a read data output from the sense amplifier associated with the selected bit line,wherein the write buffer is coupled to receive a write control signal to activate a write operation on the selected bit line via a coupled N-type transfer device.