Patent ID: 6249862
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A reorder buffer for performing dependency checking in a microprocessor, comprising:an instruction storage, wherein said instruction storage is configured to store information regarding a plurality of instructions;an instruction control unit, wherein said instruction control unit is coupled to said instruction storage;a dependency table, wherein said dependency table is coupled to said instruction storage, wherein said dependency table includes a plurality of dependency entries, wherein each of said plurality of dependency entries is assigned to a different one of a plurality of registers, wherein each of said plurality of dependency entries identifies one of said plurality of instructions represented in said instruction storage, and wherein said one of said plurality of instructions is the most recent instruction in program order to update one of said plurality of registers; anda dependency control unit, wherein said dependency control unit is coupled to said dependency table, wherein said dependency control unit is configured to detect dependencies between said set of concurrently decoded instructions and said plurality of instructions represented in said instruction storage, and wherein said dependency control unit uses one of said plurality of dependency entries to resolve dependencies between said set of concurrently decoded instructions and said plurality of instructions represented in said instruction storage.