Patent ID: 8125054
Filing Date: 2012-02-28
Classification: H01L

Abstract:
1. A semiconductor device for wafer level chip scale packaging comprising: a die having a top surface, and an outer edge in the shape of a rectangle, the die having a functional circuit area that does not extend into the corners of the die; a first scribe seal formed around a perimeter of the functional circuit area, wherein the first scribe seal comprises a set of at least two barrier walls, the set comprising at least one continuous barrier wall, and the set further comprising at least one discontinuous barrier wall comprising an array of metal vias interconnecting electrically conductive layers; a second scribe seal formed between the first scribe seal and the outer edge of the die and following the outer edge into the corners of the die, the second scribe seal comprising a set of at least two barrier walls, the set comprising at least one continuous barrier wall adjacent the outer edge of the die, and the set further comprising at least one discontinuous barrier wall comprising an array of metal vias interconnecting electrically conductive layers; and a first package insulating layer formed on the top surface of the die and having an outer edge, the first package insulating layer substantially covering the functional circuit area.