Patent ID: 7855926
Filing Date: 2010-12-21
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells; a pair of bit lines connected to the memory cells; a bit line sense amplifier for amplifying voltages of first data output from the pair of bit lines and for transmitting the first data to a pair of local input/output lines; a local sense amplifier for amplifying second data output from the local input/output lines and for transmitting the second data to a pair of global input/output lines in response to a local sense control signal; a data sense amplifier for amplifying third data output from the pair of data input/output lines connected to the global input/output lines and for outputting the third data from the semiconductor memory device in response to a sensing enable signal; a multiplexer in a data path between the local sense amplifier and the data sense amplifier, responsive to a multiplexer control signal to connect the local input/output lines to the global input/output lines; and a controller for activating the local sense control signal within a predetermined duration in response to a first signal and a second signal, the controller comprising a pulse generator generating a first pulse signal activated for a predetermined duration in response to the first signal, and a local sense control signal generator activating the local sense control signal when both the first pulse signal and the second signal are activated, and deactivating the local sense control signal when the second signal is deactivated.