Patent ID: 9141473
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. An apparatus, comprising: a first N-bit error processing subsystem coupled to a first memory array, the first error processing subsystem configured to perform first error processing on a first portion of a K-bit word carried on a K-bit data bus, the first portion of the K-bit word stored in the first memory array; a second N-bit error processing subsystem coupled to a second memory array, the second N-bit error processing subsystem configured to perform, in parallel to the first error processing of the first N-bit error processing subsystem, second error processing on a second portion of the K-bit word, the second portion of the K-bit word stored in the second memory array; an error circuit being connected to the first N-bit error processing subsystem and the second N-bit error processing subsystem, the error circuit configured to produce an error signal when either the first N-bit error processing subsystem or the second N-bit error processing subsystem detects an error, the error signal indicating that a memory error has occurred to the K-bit word; and a first N+M bit bus coupled to the first memory array and to the first N-bit error processing subsystem, wherein the first memory array and the second memory array are portions of a spin-transfer torque random access memory (STT-RAM) device, wherein at least one of the first or second N-bit error processing subsystem is configured to add M bits of parity information to N bits of the K-bit word using a specified error correction scheme and store resulting N+M bits of data in a corresponding memory array during a memory write operation, and wherein the first N-bit error processing subsystem comprises: an encoder circuit connected to a K-bit data bus, the encoder circuit being configured to receive N bits of the K-bit word and generate the M bits of parity information for the N bits of the K-bit word; an error detection circuit connected to the first memory array, the error detection circuit configured to detect an error in the N bits of the K-bit word based at least in part on the M bits of parity information and the error correction scheme and generate one or more syndrome bits indicating the detected error; an error correction circuit connected to the error detection circuit, the error correction circuit configured to correct the detected error using the one or more syndrome bits; and a write back switch coupled to the first N+M bit bus that is coupled to the first memory array, wherein a first input of the write back switch is coupled to a first internal N+M bit bus that is coupled to an output of the encoder circuit, and wherein a second input of the write back switch is coupled to a second internal N+M bit bus that is coupled to an output of the error correction circuit, wherein: the encoder circuit and the error correction circuit are connected to the first memory array through the write back switch, the write back switch operable to select, based on a signal from the error detection circuit, one of an output from the encoder circuit or an output from the error correction circuit to write to the first memory array, wherein the signal indicates that the error has been detected.