Patent ID: 7071761
Filing Date: 2006-07-04
Classification: H03K

Abstract:
1. A circuit for reducing propagation delay, comprising: a logic circuit including a p-type transistor and an n-type transistor, wherein a drain of the p-type transistor is coupled to a drain of the n-type transistor, and wherein the logic circuit is coupled between a low power supply and a high power supply; and a voltage offset circuit that is arranged to provide a first voltage to a gate of the p-type transistor, and further arranged to provide a second voltage to a gate of the n-type transistor such that the second voltage is positively offset relative to the first voltage, wherein the positive offset is less than the difference between the high power supply and the low power supply; and a current source that is operable to provide a first current, wherein the voltage offset circuit includes a resistor, and wherein the voltage offset circuit is operable to provide the first and second voltages such that the logic circuit performs as if the difference between the high power supply and the low power supply was approximately VDD+I