Patent ID: 6600689
Filing Date: 2003-07-29
Classification: G11C,H01L

Abstract:
A semiconductor memory device, comprising:a memory cell region including a plurality of main banks, each having memory cells, main digit lines, main virtual ground lines, subordinate digit lines, and subordinate virtual ground lines; a main digit line selector circuit being connected to said main digit lines for selecting at least one of said main digit lines; a main virtual ground selector circuit being connected to said main virtual ground lines for selecting at least one of said main virtual ground lines; a reference cell region including a plurality of reference banks, each having reference memory cells, reference digit lines, reference virtual ground lines, subordinate reference digit lines and subordinate reference virtual ground lines; a reference digit line selector circuit being connected to said reference digit lines for selecting at least one of said reference digit lines; a reference virtual ground selector circuit being connected to said reference virtual ground lines for selecting at least one of said reference virtual ground lines; a bank selecting circuit connected to said subordinate digit lines and said reference subordinate digit lines for selecting at least one of said subordinate digit lines and connecting said at least one subordinate digit line to said main digit line, and further selecting at least one of said subordinate reference digit lines and connecting said at least one subordinate reference digit line to said reference digit line; and a ground selecting circuit connected to said subordinate main virtual ground lines and said subordinate reference virtual ground lines for selecting at least one of said subordinate main virtual ground lines and connecting said at least one subordinate main virtual ground line to said main virtual ground line, and further selecting at least one of said subordinate reference virtual ground lines and connecting said at least one subordinate reference virtual ground line to said reference virtual ground line, wherein said reference cell region has substantially the same interconnection routine as said memory cell region, and wherein said reference cell region includes adjacent first and second subordinate regions, said first subordinate region having even number banks having ON-bit cells and odd number banks having OFF-bit cells, and said second subordinate region having even number banks having OFF-bit cells and odd number banks having ON-bit cells.