Patent ID: 6826105
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A refresh-free ultra-low power pseudo DRAM (Dynamic Random Access Memory) for performing a 1-bit read, 1-bit write, and a non-read and non-write operation according to the clock that controls a DRAM, the clock containing a first signal selected from a first read signal, a first write signal and a non-read and non-write signal, the refresh-free ultra-low power pseudo DRAM comprising:an interface circuit, which generates a second read signal, a second write signal, and a second non-read and non-write signal in response to the first signal selected from the first read signal, the first write signal, and the first non-read and non-write signal, respectively; and an SRAM (Static Random Access Memory) memory cell, which is coupled with the interface circuit for performing the 1-bit read operation, the 1-bit write operation, and the non-read and non-write operation according to the second read signal, the second write signal, and the second non-read and non-write signal, respectively.