Patent ID: 7006400
Filing Date: 2006-02-28
Classification: G11C

Abstract:
1. A content addressable memory (CAM) comprising: a CAM array that stores a plurality of data values, and outputs a first signal and a second signal when a match is found between a data value stored in the CAM array and a search value, the first signal indicating that the match was found, the second signal including location information of where the match was found, the CAM array including a plurality of CAM banks that store the plurality of data values; a plurality of word lines connected to the CAM array, the plurality of word lines having logic states; a plurality of bit lines connected to the CAM array, the plurality of bit lines having logic states, each CAM bank contacting the word lines and the bit lines; a state machine that controls the logic states placed on the word lines and the bit lines to control the CAM array; a plurality of power switches connected between the plurality of CAM banks and a power source, a power switch passing power to a CAM bank when turned on, and removing power from the CAM bank when turned off; and a plurality of power lines connected to the power switches and the state machine, the power lines having logic states, the state machine determining which CAM bank can respond to the logic states placed on the word and bit lines by controlling the logic states placed on the power lines that turn on and off the CAM banks.