Patent ID: 6027959
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of forming a field-effect transistor within a semiconductor wafer, comprising:sequentially forming an oxide layer, a polysilicon layer, an anti-reflective layer, and a resist layer on an upper surface of a semiconductor substrate;patterning the resist layer and anti-reflective layer to define dimensions of a gate;using the patterned resist layer and anti-reflective layer to form the gate on the semiconductor substrate with a gate oxide therebetween, and to expose the upper surface of the semiconductor substrate on opposing sides of the gate;removing the patterned resist layer;performing a first implantation of ions into the exposed upper surface of the semiconductor substrate on the opposing sides of the gate using the patterned anti-reflective layer, the gate and the gate oxide as a mask to form lightly doped source/drain regions;depositing a first dielectric layer over the patterned anti-reflective layer and the exposed upper surface of the semiconductor substrate on the opposing sides of the gate;etching the first dielectric layer using a first plasma to remove the first dielectric layer located over the patterned anti-reflective layer and a portion of the patterned anti-reflective layer, to form first spacers on the opposing sides of the gate, and to expose the upper surface of the semiconductor substrate adjacent the first spacers;performing a second implantation of ions into the exposed upper surface of the semiconductor substrate adjacent the first spacers using the remaining patterned anti-reflective layer, the gate, the gate oxide and the first spacers as a mask to form source/drain regions in a portion of the lightly doped source/drain regions;depositing a second dielectric layer, comprising silicon nitride, over the remaining patterned anti-reflective layer, the first spacers and the exposed upper surface of the semiconductor substrate adjacent the first spacers; andetching the second dielectric layer using a second plasma to remove the second dielectric layer located over the patterned anti-reflective layer and the remaining patterned anti-reflective layer, to form second spacers on the first spacers, and to expose the upper surface of the semiconductor substrate adjacent the second spacers.