Patent ID: 7398482
Filing Date: 2008-07-08
Classification: G06F

Abstract:
1. A method for providing a variable and scalable modular multiprocessor design for providing custom designed chips while avoiding redesign of modules comprising the design, said method comprising: generating a multiprocessor chip design comprised of one or more processing unit (PU) modules and a plurality of assisting processing unit (APU) modules wherein said one or more PU modules control said APU modules and wherein said one or more PU modules and APU modules are designed in accordance with one or more rules establishing common parameters wherein at least one dimension of said one or more PU modules and APU modules is defined in said rules as a standard; selecting said one or more PU modules and APU modules to be removed and/or added from said multiprocessor chip design; and configuring said multiprocessor chip design comprised of said selected one or more PU modules and APU modules and a clock and power mesh positioned on each of said one or more PU modules and said APU modules wherein said design further comprises locating module bus connections in a same relative position for each of said one or more PU modules and APU modules requiring bus connections and a performance monitor bus connected to each of said one or more PU modules and APU modules.