Patent ID: 6336208
Filing Date: 2002-01-01
Classification: G06F

Abstract:
A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array, comprising:selectively collapsing into a first single node, a node and its predecessor nodes as a function of delay factors associated with the plurality of sizes of lookup tables and a maximum of delay factors associated with the predecessor nodes; selecting one of the sizes of lookup tables to implement the first single node if an associated cut-size of the first single node is less than or equal to the number of inputs to the one size; selectively collapsing into a second single node a node and its predecessor nodes as a function of the delay factors and the maximum delay factor increased by a selected value if a lookup table size was not selected for the first single node; and selecting one of the sizes of lookup tables to implement the second single node if an associated cut-size of the second single node is less than or equal to the number of inputs to the one size.