Patent ID: 8909979
Filing Date: 2014-12-09
Classification: G06F

Abstract:
1. A computer system for implementing fault tolerance, comprising: a first CPU; a second CPU; a first CPU interconnect device that comprises a first quick path interconnect (QPI) interface and a first serial deserial (SerDes) interface that are connected to each other; and a second CPU interconnect device that comprises a second QPI interface and a second SerDes interface that are connected to each other; wherein: wherein the computer system is configured to monitor the link state of any one of the first connection link, the second connection link and the third connection link, transmit the link state through the fourth data channel between the first CPU interconnect device and the second CPU interconnect device, recover any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.