Patent ID: 7921395
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A method for laying out decoupling cells, wherein the method is executed by a decoupling cell layout apparatus having stored in a storage device cell position information representing the position of a decoupling cell that is to be added to layout data for a semiconductor integrated circuit including a plurality of paths, the method comprising: extracting, by the decoupling cell layout apparatus, from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the plurality of paths serving as a target path; converting, by the decoupling cell layout apparatus, the extracted timing margin to a noise tolerance amount; comparing, by the decoupling cell layout apparatus, the noise tolerance amount and a power supply noise amount of the target path; and determining, by the decoupling cell layout apparatus, whether a decoupling cell must be additionally laid out in the target path based on the comparison result.