Patent ID: 6236230
Filing Date: 2001-05-22
Classification: H03K

Abstract:
A product-term allocation architecture for a programmable device, comprising:a plurality of logic gate sections, wherein:a first one of said logic gate sections comprises a first plurality of fixed logic gates, each of said first plurality of fixed logic gates having m product term inputs, m being an integer of at least one;a second one of said logic gate sections comprises a second plurality of fixed logic gates, each of said second plurality of fixed logic gates having n product term inputs, n being an integer of at least two and being different from m; andsaid plurality of logic gate sections are configured to provide p outputs, p being an integer equal to or greater than the total number of said fixed logic gates and less than the total number of fixed logic gate inputs; anda routable, programmable OR-type array receiving said p outputs, configured to generate a plurality of array outputs.