Patent ID: 8214593
Filing Date: 2012-07-03
Classification: G06F

Abstract:
1. A serial interface cache controller, applied to a micro-controller system that reads data from an external memory through a serial interface read controller, then stores the data into an internal cache memory, and controls a micro-controller to read the internal cache memory, wherein a micro-controller read-out address of the micro-controller is A bits, the serial interface cache controller comprising: an address tag row register, for storing L rows of address tags, wherein each of the rows of address tags comprises an M-bits block tag for recording an address block of T-bytes data stored in the internal cache memory, and an N-bits valid area tag for recording valid bit sectors in the address block, M is an integer smaller than A, and each of the valid bit sectors has a size of T/N bytes; a comparison control unit, for reading the L rows of address tags in the address tag row register and the micro-controller read-out address of the micro-controller, comparing data of the M-bits block tags with [A−1,M] bit data of the micro-controller read-out address, comparing data of the N-bits valid area tags with [M−1,K] bit data of the micro-controller read-out address, and outputting a comparison signal, an internal cache memory read-out address and an external memory read-out address, wherein N is 2 to the K a finite state machine, for controlling the micro-controller to read the data from the internal cache memory according to the internal cache memory read-out address, and reading the data from the external memory to the internal cache memory according to the external memory read-out address, wherein when the [A−1,M] bit data of the micro-controller read-out address does not match any data in the M-bits block tags, or when the [A−1,M] bit data of the micro-controller read-out address matches the data of the M-bits block tag in one of the address tag but the data of the N-bits valid area tag in the address tag does not have the [M−1,K] bit data of the micro-controller read-out address, the comparison control unit reads the data from the external memory to the internal cache memory by the external memory read out address, wherein the data read from the external memory at each time is smaller than T bytes; wherein, when J wherein, when the [A−1,M] bit data of the micro-controller read-out address matches one of data in the M-bits block tags of one of the L rows of address tags, the Q wherein when the [A−1,M] bit data of the micro-controller read-out address does not match any data in the M-bits block tags, the comparison control unit updates the [A−1,M] bit data of the micro-controller read-out address into the M-bits block tag of one of the L rows of address tags.