Patent ID: 6514810
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method for forming a buried channel PMOS transistor in an integrated circuit, comprising:providing a semiconductor substrate; simultaneously forming a n-well region and a third well region in said semiconductor substrate by implanting first n-type dopants into said substrate; forming a p-well region in said semiconductor substrate by implanting first p-type dopants into said semiconductor substrate wherein said third well region is simultaneously implanted with said first p-type dopants; forming a dielectric layer over said semiconductor substrate; forming a gate layer over said dielectric layer; implanting said gate layer with second n-type dopants such that a first region of said gate layer over said p-well region and a second region of said gate layer over said third well region are both doped n-type, forming a gate electrode over said third well region by etching said gate layer; and implanting said gate electrode and said third well region with second p-type dopants wherein an output MOS transistor is simultaneously implanted with said second p-type dopants.