Patent ID: 6801093
Filing Date: 2004-10-05
Classification: H03L

Abstract:
A frequency synchronous apparatus for outputting a synchronous clock, comprising:a switch which selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal; a frequency division circuit which divides a frequency of the synchronous clock; a phase comparison circuit which detects a phase difference between an output clock from said frequency division circuit and an output clock from said switch, and outputs a phase difference value; a frequency adjustment and calculation circuit which performs synchronous control so as to adjust the phase difference value output from said phase comparison circuit to 0, and outputs a synchronous control value; a memory which holds the synchronous control value output from said frequency adjustment and calculation circuit at least when the highly stable clock is output in accordance with the mode switching signal, said memory further holding at least two synchronous control values output from said frequency adjustment and calculation circuit when a frequency of the highly stable clock is set to a predetermined higher frequency and to a predetermined lower frequency; a conversion circuit which converts the synchronus control value output from said frequency adjustment and calculation circuit into a control voltage value; and a voltage-controlled oscillator which outputs a synchronous clock on the basis of the control voltage value.