Patent ID: 6218886
Filing Date: 2001-04-17
Classification: G05F,H01L,H03K

Abstract:
Circuit (DC) for compensating the fluctuations of the value of an output quantity (fu) in a CMOS integrated device (OS) comprising P transistors and N transistors, in which the value of such output quantity (fu) depends on the value of a control quantity (Ici) according to a given transfer function and may exhibit, for a given value of the control quantity (Ici), fluctuations due to fluctuations of the characteristics of the manufacturing process of said transistors and to the operating temperature variations, the circuit (DC) being characterised in that it comprises:means (CP) for generating a first compensation signal that depends on quality indexes of the manufacturing processes of the P and the N transistors in said integrated device (OS), which indexes are determined in a calibration phase of the device, and that is representative, according to an inverse transfer function of said given transfer function, of a deviation of the output quantity value from the desired value due to the deviation of said quality indexes from a typical value;means (CT) for generating a second compensation signal representative, according to said inverse transfer function, of a deviation of the output quantity from the desired value due to the deviation of the operating temperature from a typical value; andmeans (S1, S2) for simultaneously applying said compensation signals to the control quantity so as to generate into said control quantity such variations as to restore the value of the output quantity to the desired value.