Patent ID: 7675785
Filing Date: 2010-03-09
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device including a memory cell to store data with a first transistor and a capacitor, and a word driver to control the first transistor with a second transistor and a third transistor connected in series, comprising: a substrate area formed of a semiconductor of a first conductivity type; a first isolation area formed of a semiconductor of a second conductivity type in an upper layer of the substrate area; a first well area where the first transistor is placed, formed of a semiconductor of the first conductivity type in an upper layer of the first isolation area; a second well area where the second transistor is placed, formed of a semiconductor of the first conductivity type in the upper layer of the first isolation area; a third well area where the third transistor is placed, formed of a semiconductor of the second conductivity type in the upper layer of the first isolation area; and a second isolation area formed of a semiconductor of the second conductivity type in the upper layer of the first isolation area, wherein the second well area, the third well area and the second isolation area are formed between two of the first well area, the second isolation area is formed between the second well area and one of the first well area, and the third well area is formed between the second well area and another one of the first well area.