Patent ID: 6912151
Filing Date: 2005-06-28
Classification: G11C

Abstract:
1. A memory device comprising: a data transfer element adapted to facilitate a read operation or a write operation involving a storage node of the memory cell; and a first negative differential resistance (NDR) element coupled to said data transfer element, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and a second NDR element coupled to said first NDR element, said data transfer element, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential; said data transfer element, said first NDR element and said second NDR element are located within a single common well situated in a silicon based substrate, said single common well being doped with a first type of dopant that is opposite to a second type of dopant used in said silicon based substrate; wherein said single common well is biased so as to float a body region of said data transfer element, said first NDR element and said second NDR element.