Patent ID: 6399999
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; an epitaxial layer formed on said substrate; a device isolation region formed with a surrounding frame pattern in said epitaxial layer; an emitter diffusion layer and a collector diffusion layer which are formed in the surface area of said epitaxial layer in said device isolation region, a frame pattern of said collector diffusion layer being laid out in a fashion to surround said emitter diffusion layer; an insulating layer formed on said epitaxial layer; an emitter electrode wiring layer that is led from said emitter diffusion layer through a first contact hole opened in said insulating layer; a collector electrode wiring layer that is led from said collector diffusion layer through a second contact hole opened in said insulating layer; and a control wiring layer which is laid down under said emitter electrode wiring layer, and which is applied a voltage according to a reverse bias voltage to be applied to said collector diffusion region.