Patent ID: 9122494
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A method for code size reduction executed by a processor, comprising the steps of: a) determining basic blocks in an intermediate representation module; b) grouping ones of the basic blocks having duplicate code into groups; c) providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes of number i, wherein i is an integer greater than 0; d) determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; e) removing duplicates in one of the groups of the module to obtain a module having one processed group; f) determining a weighted size of the module having one processed group, wherein the weighted size of the module having one processed group is determined by summing weighted sizes of the basic blocks of the module having one processed group, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks of the module having one processed group and the corresponding weighting values; and g) comparing the weighted size of the module to the weighted size of the module having one processed group.