Patent ID: 6792483
Filing Date: 2004-09-14
Classification: G06F

Abstract:
An apparatus comprising:a processor handling an I/O request in an I/O operation; main storage controlled by said processor for storing data; one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation; a summary register for registering I/O requests for service by any one or more of said devices; a dispatcher for polling said summary register to determine if an I/O request is outstanding, if the polling determines an I/O request is outstanding, the I/O request is serviced and the summary register is reset; a target delay register having a target delay value set to a predetermined value; a program in said dispatcher calculating a delay value responsive to the workload of the processor in handling I/O requests, if the calculated delay value is greater than expected, setting the target delay value to a minimum value; and an adapter connected between said device and said processor driving an interrupt of said processor if the target delay value time period is exceeded between registering and resetting an I/O requests.