Patent ID: 6577008
Filing Date: 2003-06-10
Classification: H01L,Y10T

Abstract:
An integrated circuit comprising:a semiconductor die having a first surface and a first plurality of wire bond pads disposed about the first surface; a redistribution layer disposed upon the first surface, the redistribution layer having a plurality of conductive redistribution traces, at least some of which having first ends in electrical communication with the first wire bond pads; a second plurality of wire bond pads patterned with at least some of the redistribution traces; an insulation layer disposed atop the redistribution layer, the insulation layer having first openings therethrough to first positions along the redistribution traces and second openings therethrough to the second wire bond pads; a plurality of solder bumps disposed through the first openings to the first positions along the redistribution traces; and a plurality of bond wires bonded through the second openings to the second wire bond pads.