Patent ID: 6258663
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method for forming dynamic random access memory (DRAM) storage node comprising the steps of:providing a pre-processed semiconductor wafer having an oxide layer deposited on top, said oxide layer having a thickness substantially the same as the height of the storage mode to be built,forming a node contact of a first diameter by a first mask and a first etching process to expose a semiconductor substrate,filling said node contact by a resist material or an anti-reflective coating material,etching said wafer by a chemical that has low selectivity towards oxide and high selectivity towards said resist or anti-reflective coating material to form a node tub of a second diameter by a second mask in a second etching process to a depth smaller than the thickness of the oxide layer, said second diameter being larger than said first diameter, anddepositing and etching-back polysilicon and dielectric layers forming said storage node.