Patent ID: 6130167
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A method of forming a via hole, in an insulator layer, on a semiconductor substrate, comprising the steps of:providing a metal structure, located on a first insulator layer;depositing a second insulator layer on said metal structure, and on the regions of said first insulator layer, not covered by said metal structure;forming a photoresist shape, on the top surface of said second insulator layer, with an opening in said photoresist shape exposing an area of said second insulator layer that overlays a portion of underlying, said metal structure;performing a dry etching procedure to the area of said second insulator layer, exposed in the opening in said photoresist shape, creating said via hole, in said second insulator layer, with said via hole exposing a portion of the top surface of said metal structure, and exposing a side of said metal structure;performing a dry plasma stripping procedure to remove a top portion of said photoresist shape;performing a H.sub.2 O/N.sub.2 plasma treatment to create a metal oxide layer on said side of said metal structure, exposed in said via hole;performing a wet stripping procedure, to remove a bottom portion of said photoresist shape; andforming an upper level metal structure, in said via hole, contacting said top surface of, and said side of, said metal structure.