Patent ID: 7767531
Filing Date: 2010-08-03
Classification: H01L

Abstract:
1. A method of forming a transistor, the method comprising: forming a device isolation layer in a semiconductor substrate to define at least one active region; forming two channel portion holes in the at least one active region that extend downward from a main surface of the semiconductor substrate; forming a channel region in the at least one active region between the channel portion holes, the channel region in contact with the two channel portion holes; forming first gate patterns at the active region such that the first gate patterns respectively and sufficiently fill the channel portion holes and extend upward and downward from the main surface of the semiconductor substrate, the first gate patterns crossing the at least one active region; forming second gate patterns disposed on the device isolation layer; and forming shallow impurity regions in the at least one active region between the gate patterns, the shallow impurity regions in contact with the main surface of the semiconductor substrate, one of the shallow impurity regions in contact with the channel region, wherein a lowermost portion of the channel region is above a bottom surface of the channel portion holes, and wherein the channel region is only between the first gate patterns.