Patent ID: 6600440
Filing Date: 2003-07-29
Classification: H03M

Abstract:
An apparatus for producing digital output signals from an analog input signal in a pipelined stage that includes a sample mode and a hold mode, the apparatus comprising:a first capacitor circuit that is coupled to the analog input signal during the sample mode such that the first capacitor circuit is charged by the analog input signal; a second capacitor circuit that is coupled to the analog input signal during the sample mode such that the second capacitor circuit is charged by the analog input signal; a third capacitor circuit that is coupled to a circuit ground potential during the sample mode such that the third capacitor is discharged; a comparator circuit that is coupled to the analog input signal, and first and second sampling reference signals that are pre-selected to minimize transition height errors, the comparator circuit providing an output code in response to the analog input signal and the first and second sampling reference signals, wherein the output code correspond to one of at least three operating regions for the analog input signal during the sample mode; an amplifier circuit that is coupled to the first, second, and third capacitance circuits during the hold mode; a first selection circuit that is arranged to couple a selected one of the first, second, and third capacitance circuits between an input and an output of the amplifier circuit in response to the output code during the hold mode; and a second selection circuit that is arranged to couple the other of the capacitor circuits between a respective hold reference signal and the input of the amplifier circuit, wherein the hold reference signals and the selected capacitor are determined by the output code, and the output of the amplifier circuit during the hold mode corresponds to a residue signal in a pipelined converter.