Patent ID: 8339405
Filing Date: 2012-12-25
Classification: G06T

Abstract:
1. A programmable data processing circuit comprising: a memory circuit having a plurality of memory banks and a memory port; a data port; a controllable switching circuit, coupled between the memory port and the data port, for providing a controllable coupling between respective data value positions of the data port and data value positions of the memory port dependent on a control signal; a parameter storage circuit for storing a plurality of parameter value sets, each comprising at least one parameter value, each parameter value set at least partly determining an assignment of data value positions of the data port to data value positions of the memory port; an instruction execution control circuit coupled to the switching circuit and the parameter storage circuit, the instruction execution control circuit comprising a parameter set controlled circuit, a single switch control generation circuit, and an address generation circuit having, for each of the memory banks, a dedicated output; and an instruction set of the instruction execution control circuit including an instruction that comprises an indication of a selected parameter value set, the instruction execution control circuit being configured to respond to the instruction by retrieving the selected parameter value set from the parameter storage circuit, to have the single switch control generation circuit control the switching circuit according to the assignment determined using the selected parameter value set, and to have the address generation circuit generate addresses for each of the memory banks dependent on the signals from parameter set controlled circuit.