Patent ID: 8691658
Filing Date: 2014-04-08
Classification: G01L,H01L

Abstract:
1. A method of aligning an electronic CMOS structure with respect to a buried structure in a bonded and thinned-back stack of semiconductor wafers comprising the steps of: forming at least one alignment mark at an edge portion of a semiconductor wafer in a process of fabricating the buried structure prior to burying it, the structure provided on a front side a semiconductor wafer; bonding a cover wafer such that at least one thinned portion that is defined by a recessed edge at a bond side of the cover wafer is provided at a position corresponding to the at least one alignment mark, whereby the cover wafer bonding results in a burying of the buried structures, thinning the resulting wafer stack to a certain degree with respect to the cover wafer, making visible the at least one alignment mark; and using the alignment mark for aligning masks in fabricating the electronic CMOS structure on the surface of the thinned cover wafer.