Patent ID: 6187625
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method of fabricating a crown capacitor, comprising:providing a semiconductor substrate having a transistor, comprising at least one diffused region, formed thereon and overlaid by a first insulating layer;forming bit lines in the first insulating layer, wherein the first insulating layer isolates the bit lines and the substrate;forming a first masking layer over the first insulating layer;forming a second insulating layer over the first masking layer;patterning the second insulating layer, the first masking layer and the first insulating layer to form a contact hole which exposes the diffused region;conformally forming a second masking layer on the surface of the second insulating layer and extending to the sidewalls and the bottom of the contact hole;etching back the second masking layer to form masking spacers on the sidewalls of the contact hole to prevent the bit lines from being damaged and shorting;removing the second insulating layer;conformally forming a first conductive layer over the first masking layer and extending to the surface of the masking spacers and the bottom of the contact hole;forming a third insulating layer over the first conductive layer, wherein the third insulating layer fills the contact hole;patterning the third insulating layer and the first conductive layer to the first masking layer leaving portions of the third insulating layer with vertical sidewalls over the contact hole;forming a second conductive layer over the third insulating layer and the first masking layer;etching back the second conductive layer to form conductive spacers on the sidewalls of the third insulating layer;removing the third insulating layer to expose the conductive spacers and the first conductive layer as a bottom electrode;forming a capacitor dielectric layer on the bottom electrode; andforming a top electrode over the capacitor dielectric layer.