Patent ID: 8751864
Filing Date: 2014-06-10
Classification: G06F

Abstract:
1. A system comprising: a first processor; a second processor; a first memory controller to couple the first processor to a first portion of a system memory formed of at least one memory module; and a second memory controller to couple the second processor to a second portion of the system memory, wherein the first memory controller is to cause a migration of information stored in the first portion of the system memory to the second portion of the system memory and update a redundant memory aperture storage of the first memory controller to indicate an amount of the information migrated from the first portion of the system memory to the second portion of the system memory, the first memory controller further to determine whether an error incurred during a memory access request of an operating system (OS)-controlled thread to the first portion of the system memory occurred in a region of the first portion of the system memory that has been migrated to the second portion of the system memory and if so forward the memory access request to the second memory controller to retry the memory access request to the second portion of the system memory, otherwise signal an uncorrectable memory error.