Patent ID: 6590196
Filing Date: 2003-07-08
Classification: H04N

Abstract:
An integrated active pixel photosensor in which each pixel includes a photosensitive component and only two transistors, said photosensor including a matrix array of pixels, said matrix array comprising:a plurality of pixels arranged in columns and rows, first and second pluralities of column lines respectively arranged in the said columns; a different one of each of said pluralities connected to the pixels of corresponding column, each of said pixels being associated to a first column line and a second column line, a plurality of row lines respectively arranged in said rows and connected one each to the pixels of a corresponding row, said photosensor further comprising logic control devices external to said matrix array for establishing a repetitive connection sequence for said column and row lines, said sequence including, for each pixel of said matrix array, a reset to initial state phase, a luminance information acquisition phase, and a phase of reading said luminance information, each of said pixels comprising: a photosensitive component having a first terminal and a second terminal, a first transistor having a gate and a source-drain path, said gate of said first transistor being connected to said first column line associated with said pixel, said source-drain path of said first transistor being connected between one of said first and second terminals of said photosensitive element and to said second column line associated to said pixel, and a second transistor having a gate and a source-drain path, said gate of said second transistor being connected to said one of said first and second terminals, said source-drain path of said second transistor being connected between said second column line and one of said plurality of row lines belonging to the row of pixels wherein said pixel is located, the other one of said first and second terminals of said photosensitive element being connected to a reference potential, wherein, in each pixel and in accordance with said predetermined sequence, said logic control devices: in said reset to initial state phase, connect said first column line to a first logic level to activate said first transistor and connect said second column line to a power supply potential of a first polarity to discharge said photosensitive component, during which reset to initial state phase said one of said row lines is floating, in said acquisition phase, connect first column lines to a second logic level opposite said first logic level to deactivate said first transistor, during which acquisition phase said second column line and said one of said row lines are floating, and in said read phase, maintain said first column line at said second logic level, to connect said second column line to a power supply potential of a second polarity opposite said first polarity and connect said one of said row lines to a useful signal output of said matrix array.