Patent ID: 7502896
Filing Date: 2009-03-10
Classification: G06F

Abstract:
1. A system for maintaining the integrity of data transfers in shared memory configuration comprising: a plurality of devices for reading or writing data; a memory interface connected to said plurality of devices; and a shared memory connected to said memory interface for storing said data; wherein said memory interface comprises: an arbitration logic for prioritizing the access of said plurality of devices to said shared memory; a control block connected to said arbitration logic for facilitating the buffering of data while the access of said shared memory is restricted; and a plurality of buffers connected to said control block for temporarily storing data wherein the memory interface is operable in a multi-portion mode responsive to a control signal from at least one of the plurality of devices, the memory interface operable during the multi-portion mode to sequentially buffer in the plurality of buffers N−1 portions of a block of data to be transferred from one of a plurality of devices to the shared memory, the block of data including N portions, and after buffering the N−1 portions, the memory interface being further operable to transfer the Nth portion directly into the shared memory and to thereafter transfer the N−1 portions to the shared memory.