Patent ID: 7777271
Filing Date: 2010-08-17
Classification: H01L

Abstract:
1. An electrically erasable programmable read only memory cell comprising a program gate, a control gate, a select gate, and a floating gate, the memory cell configured to erase data in said memory cell using a channel erase procedure, said memory cell further comprising: an erase capacitor coupled to said floating gate of said memory cell, wherein said erase capacitor is configured to couple a positive voltage bias to said floating gate during said channel erase procedure, said erase capacitor comprising a P-type metal oxide semiconductor transistor having a source, a drain, and an N-well tied together and having a gate coupled to said floating gate of said memory cell, wherein said floating gate includes (1) a square portion, (2) a first rectangular portion coupled to said square portion and extending transversely over said control gate, and (3) a second rectangular portion coupled to said square portion and extending transversely over said erase capacitor, a long dimension of the first rectangular portion substantially perpendicular to a long dimension of the second rectangular portion, and wherein at least a portion of said select gate extends over said first rectangular portion of said floating gate and is at approximately a same level as said program gate.