Patent ID: 8531056
Filing Date: 2013-09-10
Classification: G05F

Abstract:
1. An apparatus comprising: a plurality of power supply terminals; an output terminal; a supply node; a plurality of switches, wherein each switch is directly coupled to at least one of the power supply terminals, and wherein each switch is directly coupled to the supply node, and wherein each switch is controlled by at least one of a plurality of control signals; a plurality of power transistors, wherein each power transistor has a body electrode, a first passive electrode, a second passive electrode, and a control electrode, and wherein each power transistor is directly coupled to the supply node at its body electrode, and wherein the first passive electrode of each power transistor is directly coupled to at least one of the power supply terminals, and wherein the second passive electrode of each power transistor is directly coupled to the output terminal; a plurality of buffers, wherein each buffer is directly coupled to the control electrode of at least one of the power transistors; and an amplifier that is directly coupled to each buffer.