Patent ID: 7760007
Filing Date: 2010-07-20
Classification: H03K

Abstract:
1. A CMOS analog switch circuit, comprising: a first terminal and a second terminal; an NMOS switch transistor coupled between the first and second terminals of the CMOS switch circuit, the NMOS switch transistor having a gate terminal that is configured to control a current flow through the NMOS switch transistor between the first and second terminals in response to a first control signal, the NMOS switch transistor further including a body terminal for providing a body bias to the NMOS switch transistor; a PMOS switch transistor coupled between the first and second terminals of the CMOS switch circuit, the PMOS switch transistor having a gate terminal that is configured to control a current flow through the PMOS switch transistor between the first and second terminals in response to a second control signal, the PMOS switch transistor further including a body terminal for providing a body bias to the PMOS switch transistor; a first native transistor having a gate terminal coupled to the first terminal of the CMOS switch circuit and a source terminal coupled to the body terminal of the PMOS switch transistor, the first native transistor being characterized by a substantially 0V threshold voltage; a second native transistor having a gate terminal coupled to the second terminal of the CMOS switch circuit and a source terminal coupled to the body terminal of the PMOS switch transistor, the second native transistor being characterized by a substantially 0V threshold voltage; and a current bias circuit having first and second transistors in series between a second power supply terminal and the coupled source terminals of the first and the second native transistors, whereby the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.