Patent ID: 6606687
Filing Date: 2003-08-12
Classification: G06F

Abstract:
A digital system comprising a processor coupled to main memory and a cache memory with dirty bits and having control circuitry for performing a hardware clean function, the control circuitry comprising:high circuitry for storing a highest address representative of a highest cache location having dirty data, wherein the high circuitry is operable to compare a pending address of each access to the cache that sets a dirty bit and to update the highest address if the pending address is higher than the current highest address; low circuitry for storing a lowest address representative of a lowest cache location having dirty data, wherein the low circuitry is operable to compare the pending address of each access to the cache that sets a dirty bit and to update the lowest address if the pending address is lower than the current lowest address; control logic circuitry for writing information from the cache to corresponding main memory locations for each dirty cache location in a range between the lowest address and the highest address in response to a clean function command; and wherein the control logic circuitry is responsive to the detection of an interrupt to halt the clean function, and to then resume the clean function at a later time.