Patent ID: 8018788
Filing Date: 2011-09-13
Classification: G11C

Abstract:
1. A static memory device, comprising: a bit cell connected to an internal voltage line; and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein: the power supply control circuit is configured to supply a power supply voltage level to the internal voltage line, the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group, wherein the mode control signal group includes a write assist signal and a sleep mode signal, and the power supply control circuit includes a NAND gate configured to receive the write assist signal and the sleep mode signal, a first PMOS transistor including a source connected to the power supply voltage, a drain connected to the internal voltage line, and a gate configured to receive an output signal from the NAND gate, and a second PMOS transistor including a source connected to the power supply voltage, a gate connected to the internal voltage line, and a drain connected to the internal voltage line.