Patent ID: 6445001
Filing Date: 2002-09-03
Classification: H01L,Y10T

Abstract:
A semiconductor device comprising:a semiconductor substrate; an input/output terminal array formed on said semiconductor substrate in a two-dimensional array fashion, said input/output terminal array having a plurality of input/output terminals evenly formed on an inner region on said semiconductor substrate; a peripheral region formed on said semiconductor substrate, said peripheral region having a plurality of testing terminals equal in number to the number of the input/output terminals; a first metal wiring layer for connecting each of said input/output terminals to a dedicated one of said testing terminals located from said input/output terminal; and input/output circuits arranged along sides of said semiconductor substrate on the peripheral region of said semiconductor substrate, said plurality of testing terminals being respectively arranged between said input/output circuits and the sides of said semiconductor substrate; wherein said testing terminals and said input/output terminals are formed of a second metal wiring layer, said input/output terminals are arranged at a place inner to that of said input/output circuits on the semiconductor substrate, and each of said plurality of input/output terminals includes a barrier layer formed over said second metal wiring layer to have a top surface higher than that of each testing terminal, and a bump formed on said barrier layer.