Patent ID: 9093298
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprising semiconductor material extending to a top surface of said substrate; forming field oxide in said substrate; forming a gate of a first gate structure over said semiconductor material proximate to said field oxide; forming a gate of a second gate structure over said field oxide so as not to overlap said semiconductor material adjacent to said field oxide; forming an epitaxy hard mask over said second gate structure so as to expose a portion of said semiconductor material between said first gate structure and said second gate structure, so that said epitaxy hard mask overlaps a top surface of said semiconductor material adjacent to said field oxide between said first gate structure and said second gate structure; removing said semiconductor material in a source/drain region between said first gate structure and said second gate structure exposed by said epitaxy hard mask to form a source/drain cavity; forming a silicon-germanium source/drain region in said source/drain cavity, so that a top edge of said silicon-germanium source/drain region at a sidewall of said field oxide does not extend more than one third of a depth of said silicon-germanium source/drain region from a top surface of said semiconductor material; forming dielectric spacers adjacent to lateral surfaces of said gate of said second gate structure so that said dielectric spacers extend onto said silicon-germanium source/drain region; forming metal silicide on said silicon-germanium source/drain region; and forming a contact between said first gate structure and said second gate structure, such that at least half of a bottom of said contact directly contacts said metal silicide on said silicon-germanium source/drain region.