Patent ID: 8788562
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. For use in an integrated circuit having a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of a first number of multipliers, a method of performing a multiplication operation of a second size larger than said first size, said method comprising: decomposing said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size; performing a multiplication operation of a first one of said different sizes using said first number of multipliers in a first one of said units; performing a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes using one of said multipliers in a second one of said units; performing a plurality of multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes, using, for each respective one of said multiplication operations of said third one of said different sizes, a respective subset of said multipliers in a third one of said units; aligning outputs of said plurality of multiplication operations of said third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes; and adding results of said multiplication operations of said first, second and third ones of said different sizes.