Patent ID: 6479860
Filing Date: 2002-11-12
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device including: memory cells each having first and second access MOS (Metal Oxide Semiconductor) transistors, first and second driver MOS transistors, and first and second load MOS transistors;a first gate forming a gate of said first driver MOS transistor and a gate of said first load transistor; a first conductive layer, formed on said first gate with a first insulating layer interposing therebetween, and forming a capacitance between said first gate and said first conductive layer; a second gate forming a gate of said second driver MOS transistor and a gate of said second load MOS transistor; a second conductive layer, formed on said second gate with a second insulating layer interposing therebetween, and forming a capacitance between said second gate and said second conductive layer; a first local interconnect connecting said first gate and said second conductive layer therebetween; and a second local interconnect connecting said second gate and said first conductive layer therebetween, wherein said first gate has a first portion on which said first conductive layer is not formed and said first portion extends onto a drain of said second load MOS transistor; said second gate has a second portion on which said second conductive layer is not formed and said second portion extends onto a drain of said first load MOS transistor; said first local interconnect is electrically connected to said first portion and said second conductive layer through a first contact hole reaching said first portion and said second conductive layer; and said second local interconnect is electrically connected to said second portion and said first conductive layer through a second contact hole reaching said second portion and said first conductive layer.