Patent ID: 6407590
Filing Date: 2002-06-18
Classification: H03F

Abstract:
A differential receiver circuit comprising:a current source; a differential pair coupled to the current source; a first transistor coupled to a first branch of the differential pair; a second transistor coupled to a second branch of the differential pair, the first and second transistors are cross coupled; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in parallel with the first and third transistors; a sixth transistor coupled in parallel with the second and fourth transistors; a seventh transistor coupled between a control node of the fifth transistor and the first branch of the differential pair; and an eighth transistor coupled between a control node of the sixth transistor and the second branch of the differential pair, wherein the current source is a PMOS transistor, the differential pair has two PMOS transistors, the first, second, third, fourth, fifth, and sixth transistors are NMOS transistors, and the seventh and eighth transistors are PMOS transistors.