Patent ID: 6061673
Filing Date: 2000-05-09
Classification: G06N

Abstract:
Learning method in a binary system comprising the steps of:Providing any of an OR, AND, NOR, NAND, and EXOR gates as a first binary gate and a second binary gate, respectively,providing a learning network, comprised of an input layer consisting of plural binary input terminals, a connecting layer, first binary gate layers consisting of plural logic elements of the same kind, second binary gate layers consisting of plural logic elements of the same kind, and output layers, in which signals are not coupled in each layer but are coupled only in one direction among the layers from the input layers to the output layers;selecting one connection of said first gate to said second gate from a direct connection, a connection through an inverter, a connection to said second gate always input with binary 1, and a connection to said second gate always input with binary 0, andreducing or eliminating an error in the output layer between an actual signal and a teacher's signal when the first and second gates are connected to perform learning,providing a pseudo-neuron Q, defined as follows, between either of said first binary gate or input data and said second binary gate, selecting the connection between them in accordance with the value of said pseudo-neuron Q, and defining said pseudo-neuron Q, as Q=f(WX,.theta.) in whichf is the threshold function, a sigmoid function or a partial linear function;X is the input signal to the pseudo-neuron Q;W is the weight between the input and a pseudo-neuron Q; and.theta. is the threshold of the pseudo-neuron Q.