Patent ID: 8983012
Filing Date: 2015-03-17
Classification: H04L

Abstract:
1. A receive timing manager comprising: a data node; an edge detection logic coupled to the data node; a data selection logic coupled to the edge detection logic; a plurality of data flip-flops each having an input node, a clock node and an output node; and a multiplexer coupled to the data flip-flops and the data selection logic, wherein the edge detection logic comprises: a plurality of first NAND gates each having a first input node, a second input node and an output node wherein the first input node is coupled to an inverse node of the output node of one of the synchronizers, the second input node is coupled to the output node of the next synchronizer; a plurality of second NAND gates each having a first input node, a second input node and an output node wherein the first input node is coupled to an inverse node of output node of one of the synchronizer, the second input node is coupled to the output node of a previous synchronizer; a plurality of rising-edge registers each is coupled to output nodes of a group of neighboring first NAND gates and each rising-edge register is coupled in series; and a plurality of falling-edge registers each is coupled to output nodes of a group of neighboring second NAND gates and each falling-edge register is coupled in series.