Patent ID: 6754786
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A memory control circuit for controlling a memory bus and a memory connected to said memory bus, comprising:a plurality of buffers which temporarily store at least either of data to be transferred to said memory or data transferred from said memory; a plurality of counters having count values respectively, the count values corresponding to numbers of pieces of data stored in said plurality of buffers respectively; a plurality of data transfer circuits which perform data transfer between said memory and said plurality of buffers using said memory bus; and a bus arbiter including a state machine which has a plurality of states associated with said plurality of data transfer circuits respectively and sets one of the plurality of states as a current state, transition of the current state of said state machine taking place in accordance with a predetermined transition condition; wherein (1) each of said plurality of data transfer circuits transmits a request signal demanding start of the data transfer to said bus arbiter on the basis of at least one of the count values of said plurality of counters, (2) if said data transfer circuit associated with the current state of said state machine transmits the request signal to said bus arbiter, said bus arbiter transmits an acknowledge signal granting start of the data transfer to said data transfer circuit associated with the current state of said state machine, (3) each of said plurality of data transfer circuits starts the data transfer at receipt of the acknowledge signal from said bus arbiter in response to the request signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of said plurality of counters, (4) when said data transfer circuit associated with the current state of said state machine either does not transmit the request signal or has stopped the data transfer being executed, said bus arbiter does not transmit the acknowledge signal to said data transfer circuit associated with the current state of said state machine, and transition of the current state of said state machine to a renewed current state takes place in accordance with the predetermined transition condition, and (5) said operations (1) to (4) are repeated.