Patent ID: 6414886
Filing Date: 2002-07-02
Classification: G11C

Abstract:
An integrated memory, comprising:deactivation lines; and memory blocks including a first memory block and a second memory block, each of said memory blocks containing: row lines; column lines intersecting said row lines at intersection point; memory cells disposed at said intersection points of said column lines and said row lines; at least one redundancy row line for replacing and intersection a respective one of said row lines; a deactivation unit for deactivating said first memory block and having an input and an output, said input connected to one of said deactivation lines; and a deactivation decoder having an output end connected to said deactivation lines assigned to said second memory block, if one of said row lines of said first memory block of said memory blocks is replaced by said redundancy row line of said second memory block of said memory blocks, said deactivation decoder deactivates said first memory block through a corresponding one of said deactivation lines.