Patent ID: 9153689
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A device defined in a semiconductor layer having a top surface, a bottom surface and a width therebetween, said device comprising: a semiconductor portion defining a first end, a second end, and a semiconductor slit portion between said first end and said second end, wherein said first end, said second end and said slit portion each define side walls on opposite sides of said first end, said second end and said slit portion, and further wherein said first end defines an end wall between said side walls of said first end and said second end defines an end wall between said side walls of said second end, wherein the cross sectional shape of said side walls and said end walls in a plane parallel to said top and bottom surfaces is an arc; a first gate connected to said semiconductor portion at one side wall of said slit portion, said first gate defining side walls on opposite sides thereof, a connecting wall where said first gate portion connects to said semiconductor portion, and a contact wall opposite said connecting wall, wherein the cross-sectional shape of said side walls, said connecting wall and said contact wall of said first gate in a plane parallel to said top and bottom surfaces is an arc; a second gate connected to said semiconductor portion at a side wall of said slit portion opposite said first gate, said second gate defining side walls on opposite sides thereof, a connecting wall where said second gate connects to said semiconductor portion, and a contact wall opposite said connecting wall, wherein the cross-sectional shape of said side walls, said connecting wall and said contact wall of said second gate in a plane parallel to said top and bottom surfaces of said device is an arc; a first contact connected to said end wall of said first end of said semiconductor portion, said first contact having an outer wall, wherein the cross sectional shape of said outer wall of said first contact in a plane parallel to said top and bottom surfaces is a circle; and a second contact connected to said end wall of said second end of said semiconductor portion, said second contact having an outer wall, wherein the cross sectional shape of said outer wall of said second contact in a plane parallel to said top and bottom surfaces is a circle; wherein all walls of said semiconductor portion, said first gate, said second gate and said outer walls of said first and second contacts extend from said top surface to said bottom surface.