Patent ID: 6981128
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. A method for preventing load/store collisions between multiple threads in an SMT system with a plurality of load/store units comprising the steps of: coupling a first address for a first load word (LW) request to a first load/store unit (LSU) for a first thread to circuitry comprising a store reorder queue (SRQ) for a second thread in a second LSU; comparing said first address of said first LW request to addresses of atomic store Quadword (SQW) in said SRQ for said second thread; determining if first and second words making up an atomic SQW corresponding to said first address have been committed to storage if there is a match in said comparing step; and rejecting said first LW request from said first address if there is a match in said comparing step and both of said first and second words have not been committed to storage.