Patent ID: 6700152
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor integrated device comprising:a DRAM having a word line, a bit line, a plurality of memory cells In which each memory cell Is comprised of a storage capacitor and a MOS transistor, and a peripheral circuit to control said memory cells; a logical circuit; and a plurality of wiring layers separated from one another by a plurality of insulating layers Interposed between said wiring layers, wherein said storage capacitor is comprised of a metal storage node, a metal plate electrode and an dielectric film interposed between said storage node and said plate electrode and is formed in the uppermost layer of said plurality of wiring layers, and said MOS transistor is comprised of a gate electrode connected to said word line and two diffusion layers of which one diffusion layer is connected to said bit line and another diffusion layer is connected to said storage node of said storage capacitor through a plurality of contact plugs respectively formed individually in contact holes formed in each of said plurality of insulating layers separating said storage node from said another diffusion layer, end wherein a metal wire of said logical circuit and said plate electrode of said storage capacitor of said memory cell are formed on the same uppermost layer of said plurality of wiring layers.