Patent ID: 6405350
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A crosstalk error reducing system comprising:logical/library inputting means for inputting information including: 1.) logical connection information between a plurality of blocks making up a circuit, 2.) physical information of a block placing results and/or inter-block connection wiring results, 3.) delay library information comprising parameters for calculating said block's internal delay and/or wiring delay required for delay analysis, and 4.) library information for crosstalk analysis comprising parameters for calculating crosstalk magnitude required for crosstalk analysis; path delay limit value inputting means for inputting path delay time limit values, wherein the time limit values comprises minimum delay time limitation and/or maximum delay time limitation, prescribing a target performance of the circuit; crosstalk magnitude limit value inputting means for inputting a crosstalk magnitude limit value of a net for assuring normal circuit operation; path delay analysis means for performing delay analysis on at least one path; net switching timing detection means for finding, from a results of the delay analysis the time during which net switching is likely to occur, by determining a minimum/maximum time between a clock input time and a signal propagation to a net; timing overlap detection means for detecting, for all or part of the net, referred to as a â€œnet under detectionâ€ , an overlap of the switching timing between the net under detection and a net having a wire that neighbors the wire of the net under detection, referred to as â€œneighboring netâ€ ; crosstalk analysis means for calculating, using the library information for crosstalk analysis, crosstalk magnitude to the net under detection from the neighboring net having timing overlap as detected by the timing overlap detection means thus detecting the net subjected to the crosstalk error; delay gate inserting means for inserting at least one delay gate, into the net subject to crosstalk as detected by the crosstalk analysis means or into a net on a path which belongs to the neighboring net which has a timing overlap with the net under detection so as to eliminate the timing overlap, said delay gate thus satisfies the delay time limitations of the neighboring net for reducing the crosstalk error; delay gate placing means for placing the delay gate, inserted either into the neighboring net or into the net on the path which belongs the neighboring net, at a position on the route of the real wiring result of the net or at a near-by possible placing position, wherein the position reduces the crosstalk error with the net under detection; incremental wiring means for re-wiring the net divided by the insertion and placement of the delay gate wherein the incremental wiring means also rewires other nets affected by the insertion and placement of the delay gate; outputting means for outputting a placing wiring results; and control means for controlling all of said means.