Patent ID: 6721853
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A data processing system comprising:a node interconnect; a plurality of nodes interconnected by the node interconnect for transfer of data for processing in the plurality of nodes; each node including one or more processors, each processor having at least one associated cache memory; each node serving as a home node for portions of data stored therein and transferring segments of that data to another node for processing in that other node as a remote node; at least one cache memory in the remote node deallocating cached data received from a home node; wherein said cache memory, responsive to a determination to deallocate the data, issues a cache deallocate address transaction only within said remote node, said cache deallocate address transaction inquiring whether each processor within the remote node has further need for the deallocated data; the remote node including inclusivity indicators that indicate whether data from other nodes is cached within the remote node, wherein at least one of the cache memories updates said inclusivity indicators in response to receipt of responses to said cache deallocate address transaction to identify at least one cache in which the deallocated data is invalid; and the remote node, responsive to said inclusivity indicators indicating that no processor within the remote node has further need of the deallocated data, notifying the home node, via the node interconnect, of deallocation of the deallocated data by all cache memories within the remote node, said notifying being performed without the remote node receiving, via the node interconnect, a transaction from another node specifically identifying said deallocated data.