Patent ID: 6172522
Filing Date: 2001-01-09
Classification: H03K

Abstract:
A digital circuit for pulling an output node up or down in a controlled fashion, said digital circuit comprising:a first PFET having a source, a drain, and a gate;a first resistor with one end connected to said drain of said first PFET;a second PFET having a source connected to a second end of said first resistor, a drain connected to said output node, and a gate;a first NFET having a drain connected to said source of said first PFET, a source connected to said output node, and a gate;a second NFET having a drain connected to said output node, a source, and a gate;a second resistor with one end connected to said source of said second NFET and the other end connected to a ground terminal;a third PFET having a source connected to said output node, a drain connected to said ground terminal and a gate; andmeans for simultaneously activating said gates of said NFET's and PFET's to pull up and pull down said output node.