Patent ID: 6525548
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A check pattern for a semiconductor device, the check pattern comprising:a first group of a predetermined number of via openings to be checked, a second group of via openings, a third group of via openings, and a fourth group of via openings, each group interconnecting first and second conductor layers to define one side of four sides of a Wheatstone bridge circuit, the second, third and fourth groups having the same number of via openings, each having the same diameter so that the total of opening areas of the via openings of each of the second, third and fourth groups is common, the total of opening areas of the via openings of each of the second, third and fourth groups being deviated by a predetermined amount, in one direction, from a predetermined total of opening areas of the predetermined number of via openings, each being formed as designed and having a desired diameter, whereby, current passing through the Wheatstone circuit changes in direction when the diameter of each of the via openings to be checked is different from the desired diameter such that the total of opening areas of the via openings to be checked is deviated beyond the predetermined amount, in the same direction, from the predetermined total of opening areas of the via openings, each being formed as designed and having the desired diameter.