Patent ID: 6204703
Filing Date: 2001-03-20
Classification: H03K

Abstract:
A power on reset circuit for generating a power on reset signal to set logic elements to a desired initialization state during power-up, comprising:a latch circuit having first and second input terminals and an output terminal that outputs the power on reset signal; anda latch controller connected to the first and second input terminals and having a first threshold voltage, and a second threshold voltage higher than the first threshold voltage,said latch controller setting said latch circuit to an initialization state when a power supply voltage is less than the first threshold voltage during power-up so that the power on reset signal goes to a logically activated state, andsaid latch controller resetting said latch circuit when the power supply voltage is higher than the second threshold voltage so that the power on reset signal goes to a logically deactivated state,a voltage difference between the first and second threshold voltages being greater than an oscillation of the power supply voltage level during power-up.