Patent ID: 8705288
Filing Date: 2014-04-22
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a first cell unit including a first memory cell; a second cell unit including a second memory cell; a first bit line connected to one end of the first cell unit; a second bit line connected to one end of the second cell unit; a source line connected to the other ends of the first and second cell units; a cell-source driver setting the source line on a fixed potential in a programming; a data latch circuit temporary storing program data; a hookup circuit connecting one of the first and second bit lines to the data latch circuit, and connecting the other one of the first and second bit lines to the source line, in the programming; a level detection circuit detecting a potential level of the source line; and a control circuit determining a completion of a charge of the first and second bit lines when the potential level of the source line is larger than a threshold value, and making a charge time of the first and second bit lines variable, in the programming.