Patent ID: 8878274
Filing Date: 2014-11-04
Classification: G11C,H01L,Y10S

Abstract:
1. An integrated circuit memory device, comprising: a multi-resistive memory array; a circuit connected to the multi-resistive memory array, the circuit to provide a substantially stable voltage to the multi-resistive memory array, the circuit including a capacitor with a layer of conductive material including at least a first portion and a second portion arranged in an interleaved pattern to provide a maximum amount of capacitance per area, and a layer of insulation material disposed at least between the first and second portions; a first reference layer arranged above the first and second portions and a second reference layer arranged below the first and second portions, wherein the first reference layer and the second reference layer contribute to the capacitance of the capacitor and are in electrical contact with one of the first portion or the second portion; and a sensor device connected to the multi-resistive memory array to read information from the multi-resistive memory array.