Patent ID: 8638625
Filing Date: 2014-01-28
Classification: G11C

Abstract:
1. A device comprising: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a redundant bit line, and a plurality of memory cells arranged at intersections of the word lines and the bit lines and intersections of the word lines and the redundant bit line, respectively; a row decoder that selects one of the word lines included in one of the memory mats based on a row address; a column decoder that selects one of the bit lines included in the selected memory mat based on a column address; a column relief circuit that selects the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address; and a determination circuit that activates the column relief circuit when the row address is supplied to the row decoder in response to a first command, and inactivates the column relief circuit when the row address is supplied to the row decoder in response to a second command.