Patent ID: 6501123
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A non-volatile memory structure having a high gate coupling ratio, comprising:a substrate, a pair of isolation layers embedded within the substrate; a pair of tunnel oxide layers on an upper surface of the substrate between the isolation layers; a buried source/drain region in the substrate between the isolation layer and the tunnel oxide layer, a first dielectric layer over the substrate covering the buried source/drain region and having an opening above each tunnel oxide layer; a pair of floating gates each comprising a first polysilicon layer and a second polysilicon layer, wherein the first polysilicon layer is located within the opening and the second polysilicon is located over the first polysilicon layer, and wherein the first polysilicon layer and the second polysilicon layer are electrically connected; a second dielectric layer over each floating gate surface; and a control gate over the second dielectric layer.