Patent ID: 7945719
Filing Date: 2011-05-17
Classification: H04L

Abstract:
1. An apparatus comprising: a first clock source in a manageability engine (ME) space having an input/output (I/O) ME partition to generate a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device, the device having a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data, the first and second data each forming a packet being one of a posted packet, a completion packet, and a non-posted packet, the first and second frequencies being independent of each other and bounded within first and second frequency ranges, respectively, the I/O ME partition managing input/output resources which are shared between a processor interface space of a processor and the ME space in a secure manner, the I/O ME partition being a part of an ME having a memory controller (MC) ME partition and the I/O ME partition; and a queue structure coupled to the first clock source to store packets used in a credit-based flow control policy, the queue structure having a first queue to store receive posted and completion packets and a second queue to store receive non-posted packets.