Patent ID: 8930760
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A method, in a data processing system, for validating cache coherency within a processor, the method comprising: generating, by a processor, a self-modifying branch test pattern for execution by one or more processors that is under validation testing; selecting, by the processor, an execution pattern from a set of execution patterns thereby forming a selected execution pattern; loading, by the processor, the selected execution pattern into a condition register; executing the self-modifying branch test pattern by: for each node in a set of nodes: comparing, by the processor, values output during execution of the self-modifying branch test pattern based on the selected execution pattern in the condition register to a set of expected results; responsive to a match of the comparison of the values output during execution of the self-modifying branch test pattern based on the selected execution pattern in the condition register to the set of expected results, repeating, by the processor, the execution of the self-modifying branch test pattern for each execution pattern in the set of execution patterns; and responsive to a match of each comparison of the values output during each execution of the self-modifying branch test pattern to the set of expected results, validating, by the processor, the cache coherency.