Patent ID: 6389557
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A system for debugging a data processing device, comprising:an internal clock generating circuit responsive to an external clock signal for producing an internal clock signal supplied to internal circuitry of said data processing device, a freezing circuit responsive to a stop signal for fixing said internal clock signal in an off state to freeze operation of said internal circuitry, a bypass circuit responsive to a bypass clock signal supplied from a logic device external with respect to said data processing device for controlling said internal clock signal in accordance with said bypass clock signal in a debug mode, and a bypass mode control circuit responsive to a bypass mode control signal supplied from said external logic device, wherein said internal clock signal is controlled in accordance with said bypass clock signal when said bypass mode control signal is in a first state to enable operation in the debug mode, and said internal clock signal is controlled in accordance with said external clock signal when said bypass mode control signal is in a second state.