Patent ID: 7238969
Filing Date: 2007-07-03
Classification: H01L

Abstract:
1. A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit, comprising: a first area in which one or more devices are constructed for functioning as a silicon controlled rectifier; a second area in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event; and a third area in which at least one diode is provided for clamping an ESD voltage during the ESD event, wherein the first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event, and at least one device in the second area includes a grounded-gate NMOS transistor.