Patent ID: 7444498
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A method for speculatively executing instructions in a microprocessor which commits results of non speculative instructions to at least one architected facility, said method comprising the steps of: determining the occurrence of a stall condition during execution of instructions; speculatively executing speculative instructions during said stall condition across multiple pipeline stages within said microprocessor; determining the validity of speculative data utilized during said speculative execution; retrieving valid data for use by said non speculative instructions upon removal of said stall condition, wherein determining the validity of speculative data utilized during said speculative execution comprises forwarding validity bits along with the instructions through a pipeline of the microprocessor via a first forwarding path associated with the pipeline of the microprocessor; and forwarding dependency on load values along a second forwarding path associated with the pipeline for the speculative instructions, wherein the dependency on load values have at least one dependency on load bit that determines at which one of the multiple pipeline stages the data retrieved by a load instruction is determined to be valid or invalid, and wherein a pipeline stage at which data retrieved by the load instruction is determined to be valid or invalid is any one of the multiple pipeline stages.