Patent ID: 6946700
Filing Date: 2005-09-20
Classification: H01L

Abstract:
1. An integrated circuit memory cell comprising: a substrate; a trench capacitor formed in said substrate and having a conductive area and a capacitor dielectric between the conductive area and said substrate; a vertically stacked transistor comprising first, second and third stacked conductivity regions over said substrate, the second stacked conductivity region being of a first conductivity type, and the first and third stacked conductivity regions being of a second conductivity type, wherein the second stacked conductivity region is between said first and third stacked conductivity regions, said vertically stacked transistor having a first vertical side and a second vertical side, wherein one of the first and second vertical sides of the vertically stacked transistor at said first stacked conductivity region is in contact with the conductive area of said trench capacitor; a word line positioned to gate the second stacked conductivity region of said transistor; and a bit line in contact with said third stacked conductivity region.