Patent ID: 7392331
Filing Date: 2008-06-24
Classification: G06F

Abstract:
1. In a memory system having a plurality of memory modules each of which contains a memory hub connected to a plurality of memory devices, a system in at least one memory hub for receiving data packets through a first upstream link from a downstream memory module and the memory devices connected to the memory hub and for transmitting the received data packets through a second upstream link to either an upstream memory module or a controller, the system comprising: an upstream reception port coupled to the first upstream link and operable to receive data packets from the downstream memory module; a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets; a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port; an upstream transmission port coupled to the second upstream link, the second upstream link being isolated from the first upstream link; a bypass multiplexer for selectively coupling the upstream transmission port to each of a core logic circuit, the temporary storage, and the bypass bus; and a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to each of the core logic circuit, the bypass bus, and the temporary storage.