Patent ID: 6070257
Filing Date: 2000-05-30
Classification: G01R

Abstract:
An input interface circuit having a testing function mode, an input signal being applied to said input interface circuit timed with an external clock signal, the input interface circuit comprising:a first transistor of a first conduction type having a control electrode and a pair of current conducting electrodes through which electric current flows when the first transistor is conductive, wherein an input signal to the input interface circuit is to be applied to said control electrode of the first transistor;a second transistor of said first conduction type having a control electrode and a pair of current conducting electrodes through which electric current flows when the second transistor is conductive, wherein a reference signal is to be applied to said control electrode of the second transistor;a first integrating capacitor connected in series to said pair of said current conducting electrodes of said first transistor, said input signal being integrated by said first integrating capacitor;a second integrating capacitor connected in series to said pair of said current conducting electrodes of said second transistor, said reference signal being integrated by said second integrating capacitor;a third transistor of a second conduction type having a control electrode and a pair of current conducting electrodes through which electric current flows when the third transistor is conductive, one of said pair of current conducting electrodes being connected to a junction between said first transistor and said first integrating capacitor, wherein a first test signal is to be applied to said control electrode of the third transistor and a second test signal is to be applied to the other of said said pair of current conducting electrodes of the third transistor in a testing function mode, said junction between said first transistor and said first integrating capacitor serving to provide an output corresponding to an integration of said input signal to the input interface circuit;a fourth transistor of the second conduction type having a control electrode and a pair of current conducting electrodes through which electric current flows when the fourth transistor is conductive, one of said pair of current conducting electrodes being connected to a junction between said second transistor and said second integrating capacitor, wherein a third test signal is to be applied to said control electrode of the fourth transistor and a fourth test signal is to be applied to the other of said said pair of current conducting electrodes of the third transistor in the testing function mode, said junction between said second transistor and said second integrating capacitor serving to provide an output corresponding to an integration of said reference signal; anda discharge path circuit connected to said junction between between said first transistor and said first integrating capacitor and to said junction between said second transistor and said second integrating capacitor, said first and second integrating capacitors being controllably discharged through said discharge path circuit.