Patent ID: 6052789
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A computer system, including a central processing unit and a main memory system, said computer system comprising:a battery for powering said computer system;a battery monitoring circuit for measuring a level of charge in said battery, said battery monitoring circuit providing a first control signal when said charge measured falls below a predetermined level;a logic circuit, coupled to receive said first control signal, for providing a second control signal; anda cache memory for said main memory system, said cache memory including a cache controller coupled to receive said second control signal, said cache controller initially operating said cache memory as a ""write-back cache"", said cache controller providing, in response to said second control signal, an interrupt signal to said central processing unit, thereby causing said central processing unit to execute a service routine in response to said interrupt signal, said service routine causing said central processing unit to provide a third control signal to said cache controller, whereupon said cache controller either disables said cache memory or operates said cache memory as a write-through cache, in response to said third control signal.