Patent ID: 7319614
Filing Date: 2008-01-15
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a plurality of memory cell blocks arranged in matrix form, each of said memory cell blocks having a plurality of memory cells connected in series, each memory cell consisting of a transistor having a drain, a source, a floating gate and a control gate; a plurality of selecting transistors, each connected in series to one end of each of said memory cell blocks, for selecting said memory cell block; row lines each connected to the control gates of the memory cells arranged in the same row of the memory cells; and means for programming data to the memory cells by simultaneously injecting electrons to the floating gates of targeted memory cells, which require injection of electrons, of the memory cells connected to the same row line by applying a program voltage to the corresponding row line, wherein the electron injection and a checking of the amount of electrons injected in the floating gate are repeatedly performed in sequence during the programming, if a result of the checking shows that there is a memory cell of insufficient electron injection, the program voltage higher than the preceding program voltage is applied to the corresponding row line when the program voltage is repeatedly applied; wherein when the program voltage higher than the preceding program voltage is applied to the corresponding row line, drain voltages to be applied to the drains of the memory cells of insufficient electron injection are controlled to perform an electron injection at the same time on the floating gates of the memory cells of insufficient electron injection, and drain voltages to be applied to the drains of the memory cells of sufficient electron injection are controlled not to perform an electron injection to the floating gates of the memory cells of sufficient electron injection.