Patent ID: 6492714
Filing Date: 2002-12-10
Classification: H01L,H05K

Abstract:
A semiconductor device comprising:at least two substrates, each substrate having upper, lower, and end faces, said upper and lower faces being opposed to each other and said end faces being transverse to said upper and lower faces, said two substrates being spaced apart so that said end faces of said substrates are opposed to and spaced from each other by a space between said end faces; first and second integrated circuit packages, each of said first and second integrated circuit packages having a package body and plural leads extending from said package body, said first and second integrated circuit packages being respectively disposed in the space, said first integrated circuit package protruding from the space toward said upper faces of said substrates and said second integrated circuit package protruding from the space toward said lower faces of said substrates; plural external connection terminals located on said upper and lower faces of said substrates, said external connection terminals including a first group of external connection terminals located along sides of said first and second integrated circuit packages, centers of each pair of adjacent connection terminals of said first group of external connection terminals being separated by an interval 2P1; and a second group of external connection terminals located along sides of said first and second integrated circuit packages and farther from said first and second integrated circuit packages than said first group of external connection terminals, centers of each pair of adjacent connection terminals of said second group of external connection terminals being separated by the interval 2P1, centers of each pair of adjacent connection terminals of the first and second groups of external connection terminals being separated by an interval 1.41P1, external connection terminals of said first group of external connection terminals and of said second group of external connection terminals being arranged in an alternating, staggered pattern with alternating leads of said first and second integrated circuit packages respectively connected to the external terminals of said first group of external connection terminals, and alternating leads of said first and second integrated circuit packages not connected to said first group of external terminals being respectively connected to said external terminals of said second group of external connection terminals; and external connection bumps connected to said external connection terminals and disposed on at least one of said upper and lower faces of said substrates, wherein each of said external connection terminals is directly opposite a corresponding lead of said first and second integrated circuit packages to which the respective external connection terminal is electrically connected.