Patent ID: 8438578
Filing Date: 2013-05-07
Classification: G06F,H04L

Abstract:
1. A network on chip (‘NOC’) comprising: IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller for controlling communication between an IP block and memory; each network interface controller for controlling inter-IP block communications through said routers; each IP block adapted to the NOC by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator configured to administer at least some data communications traffic to and from the at least one IP block, wherein the I/O accelerator further comprises: an aggregation of sequential and non-sequential logic configured to function in response to a single opcode executed on a thread of execution on a processor in the at least one IP block that comprises the I/O accelerator to receive a plurality of messages through the inbox in accordance with an application pipeline protocol, convert data from the messages from message format to I/O format, and perform multiple store operations of the converted data.