Patent ID: 6407953
Filing Date: 2002-06-18
Classification: G11C

Abstract:
In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of:providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, to ascertain at least one characteristic of the test memory cells; and using the at least one ascertained characteristic of the test memory cells to predict whether related memory cells in the array will program correctly.