Patent ID: 7214965
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A thin film transistor (TFT) array panel comprising: an insulating substrate; gate lines formed on the insulating substrate; a gate insulating layer formed on the gate lines; a plurality of semiconductor layers formed on the gate insulating layer; data lines formed on the semiconductor layers and having a plurality of source electrodes; drain electrodes extending parallel with and adjacent to the data lines; conductive layers directly connected to respective drain electrodes and overlapping an adjacent first gate line, the respective drain electrodes extending from the first gate line toward a second gate line and extending parallel and adjacent to a respective data line that intersects the first and second gate lines; an insulating layer formed on or above the semiconductor layers, the data lines, the drain electrodes, and the conductive layers; and pixel electrodes formed on the insulating layer and electrically connected to the conductive layers through a contact hole, wherein the pixel electrodes cover both the data lines and the drain electrodes.