Patent ID: 6621327
Filing Date: 2003-09-16
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a pMOS transistor supplied with a first power supply voltage at a source electrode of said pMOS transistor; an nMOS transistor supplied with a second power supply voltage at a source electrode of said nMOS transistor, the second power supply voltage being lower than said first power supply voltage; a first switch circuit for setting substrate voltages of said pMOS and nMOS transistors to values between said first and second power supply voltages during operation periods of said pMOS and nMOS transistors, respectively; a second switch circuit for setting substrate voltages of said pMOS and nMOS transistors to said first and second power supply voltages during non-operation periods of said pMOS and nMOS transistors, respectively; and a third switch circuit for temporarily supplying a voltage to the substrate of said pMOS transistor when said non-operation periods start, the voltage being higher than said first power supply voltage.