Patent ID: 6335903
Filing Date: 2002-01-01
Classification: G06F

Abstract:
A memory system comprising:a memory unit accessed by sequential designation of row address and column address; a memory access request generator for issuing a memory access request to said memory unit; and a memory controller for controlling said memory unit in accordance with the memory access request issued from said memory access request generator, wherein said memory controller includes: a row address buffer for storing a row address, extracted from the memory access request issued from said memory access request generator, avoiding registration of the same row address into different positions; a pointer register for storing a pointer to a registration entry in said row address buffer holding said row address; a correspondence detection circuit for comparing a previously stored pointer with a newly stored pointer in said pointer register and detecting whether or not row addresses of plural memory access requests correspond with each other; and a memory unit control circuit for continuously issuing memory access requests with row addresses corresponding to each other to said memory unit.