Patent ID: 6400231
Filing Date: 2002-06-04
Classification: H03B,H03J,H03K

Abstract:
An oscillator comprising:a resonator having first and second terminals; first and second capacitor banks coupled to said first and second terminals, respectively, said first and second capacitor banks each comprising a plurality of capacitors coupled to said resonator through respective switching devices that may be selectively enabled; circuitry for selectively enabling said switching devices to couple a desired set of said capacitors to said resonator, including circuitry for generating a clock signal having a programmable duty cycle to enable at least one of said switching devices during a first phase of the clock signal and disable said at least one switching device during a second phase of the clock signal; and a clock slicer coupled to said resonator for generating a synchronization signal responsive to the signal across said resonator, wherein said clock slicer generates said synchronization signal at the maximum amplitude of said signal across said resonator and further wherein said circuitry for generating a clock signal having a programmable duty cycle is responsive to the synchronization signal to cause said enabling and disabling of said at least one switching device to occur synchronously with said signal across said resonator to avoid amplitude modulation.