Patent ID: 7034565
Filing Date: 2006-04-25
Classification: G11C

Abstract:
1. An on-die termination (“ODT”) circuit for use in a synchronous memory device, the ODT circuit comprising: a termination voltage port for receiving a termination voltage; a data input/output (“I/O”) port; a first termination resistor, one end of which is connected to the data I/O port; a switch that selectively connects the other end of the first termination resistor to the termination voltage port in response to a termination enable signal; and a termination enable signal generating circuit for generating the termination enable signal in response to a signal which indicates a valid section of input data or indicates that the present period is not a read period during write operations of the synchronous memory device, and for generating the termination enable signal in response to a signal output from a mode register set (“MRS”).