Patent ID: 6100123
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of forming a pillar CMOS FET device comprising the steps of:forming abutting N and P wells in a silicon substrate;forming N.sup.+ and P.sup.+ diffusions in said P well and N well in said substrate, respectively;growing a single undivided unitary pillar of epitaxial silicon on said substrate, which pillar has a base end at said substrate and which pillar has opposite sides, one of which sides overlaps said N well and the other one of which sides overlays said P well;said pillar terminating at a distal end;forming an N well on the side of the pillar overlying the N well in the substrate and a P well on the side of the pillar overlying the P well on the substrate and abutting the N well in the pillar;forming a P.sup.+ diffusion in the N well in the pillar adjacent the distal end and an N.sup.+ diffusion in the P well in the pillar adjacent the distal end;maintaining said pillar as a single undivided unitary structure;forming gate insulators over said opposite sides of said pillar, andforming gate electrodes over said gate insulators.