Patent ID: 6165899
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device having a dual damascene structure, comprising the steps of:forming a first insulating film on a semiconductor substrate having a device region at a surface thereof;forming a first photoresist on said first insulating film;forming a pattern for a contact hole in said first photoresist by using an exposure method;etching said first insulating film by using said first photoresist as a mask to form said contact hole for providing said device region with electrical conduction;removing said first photoresist;forming an organic insulating film on said first insulating film and in said contact hole;forming a second insulating film on said organic insulating film that is on said first insulating film and in said contact hole;forming a second photoresist on said second insulating film;forming a pattern for wiring trench in said second photoresist by using an exposure method;etching said second insulating film by using said second photoresist as a mask;etching said organic insulating film by using said second insulating film as a mask to form a wiring trench so as to leave a portion of said organic insulating film on said first insulating film; andembedding a conductive layer in said contact hole and said wiring trench.