Patent ID: 7426706
Filing Date: 2008-09-16
Classification: G06F

Abstract:
1. A computer-implemented method of configuring a wiring layout in an integrated circuit design, comprising: analyzing at least a portion of the wiring layout in the integrated circuit design, the wiring layout portion having a signal wire and one or more ground wires defined by multiple physical parameters; and adjusting one or more of the physical parameters in order to create non-negligible inductance effects in the wiring layout portion that are calculated to produce a desired time delay for signal propagation on the signal wire of the wiring layout portion, wherein the act of analyzing comprises calculating an rlc relationship between the signal wire and the one or more ground wires that produces the desired time delay for signal propagation, where r corresponds to a loop resistance per unit length of the signal wire, l corresponds to a loop inductance per unit length of the signal wire, and c corresponds to a total capacitance per unit length of the signal wire, and wherein the act of adjusting comprises changing a physical parameter of the wiring layout portion so that the wiring layout portion exhibits the rlc relationship.