Patent ID: 6903988
Filing Date: 2005-06-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a cell array consisting of a number of memory cells; a bit line sense amplifier connected to the memory cell through a bit line, for sensing data of the memory cell; a bit line equalization circuit for equalizing the bit line sense amplifier with the same voltage level; a sense amplifier I/O line electrically connected to the bit line according to a column signal; a sense amplifier I/O line equalization circuit for equalizing the sense amplifier I/O line with the same voltage level; a local I/O line electrically connected to the sense amplifier I/O line according to a row matrix signal; a local I/O line equalization circuit for equalizing the local I/O line with the same voltage level; and an I/O sense amplifier connected to the local I/O line, for sensing and outputting the data sensed through the bit line sense amplifier, wherein the bit line and the sense amplifier I/O line are equally precharged with voltages that are independently supplied through different supply lines by the bit line equalization circuit and the sense amplifier I/O line equalization circuit that are operated by an inverse signal of the row matrix signal.