Patent ID: 6321284
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A data processing system,one or more processor modules, each module having a processor for executing a program;a plurality of memories which are respectively mapped onto a plurality of areas defined in a memory space;a plurality of buses disposed between said one or more processor modules and said plurality of memories, each bus allowing said one or more processor modules to make access to at least one of said plurality of memories;a bus arbiter which accepts an access request from one of said processor modules for access to one of said memories, checks availability of each of said plurality of buses that lies between the requesting processor and the requested memory, and grants the access request when one of said buses is found by said checking to be available for the requesting processor to reach the requested memory;a module monitor, coupled to said one or more processor modules and said bus arbiter, to monitor whether each of said one or more processor modules is present or absent; anda disabling unit which disables the operation of said bus arbiter when said module monitor has found that only one of said one or more processor modules is present in the data processing system.