Patent ID: 7830986
Filing Date: 2010-11-09
Classification: H03L,Y10S

Abstract:
1. A phase locked loop (PLL), comprising: a phase detector coupled to receive first and second signals and adapted to provide an error signal indicative of a phase error between the first and second signals, the phase detector having a decoder coupled to receive first, second and third phase indication signals derived from the first signal being sampled by at least a first phase of the second signal and a second phase of the second signal to provide an incremental phase error and an accumulator adapted to accumulate the incremental phase error between the first and second signals, the incremental phase error being accumulated synchronously with the second signal, wherein the error signal is based upon the accumulated phase error; a loop filter coupled to receive the error signal and adapted to provide a control signal in response to the error signal; and an oscillator coupled to receive the control signal and adapted to adjust a phase of the second signal to be substantially equal to a phase of the first signal in response to the control signal.