Patent ID: 6822489
Filing Date: 2004-11-23
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:an FET having a gate terminal configured to input a controlled signal with a predetermined frequency and a drain terminal configured to output a signal corresponding to said controlled signal; an inductor element provided between a source terminal of said FET and a ground terminal, said inductor element having an inductance value selected in accordance with the predetermined frequency of said controlled signal and forming a series resonance circuit with a reactance component of a gate-to-source impedance when a drain voltage of said FET is lower than a source voltage thereof; and a second capacitor element provided between the gate terminal and the source terminal of said FET, wherein when a drain voltage of said FET is lower than a source voltage thereof, a series resonance circuit is formed of the reactance component of the gate-to-source impedance and said inductor element, and the inductance value of said inductor element is set in accordance with said predetermined frequency of said controlled signal, and a capacitance value of said second capacitor element is set so that a parasitic resistance component of said FET apparently decreases when the drain voltage of said FET is lower than the source voltage thereof.