Patent ID: 7271014
Filing Date: 2007-09-18
Classification: G01R

Abstract:
1. A fabrication method of semiconductor integrated circuit device comprising the steps of: (a) preparing for a semiconductor wafer in which a plurality of chip regions are segmented, a semiconductor integrated circuit is formed over each region among a plurality of chip regions, and a plurality of first electrodes for electrical connection with said semiconductor integrated circuit are formed over a principal surface; (b) preparing for a first board provided with a plurality of contact terminals for contact with the first electrodes, a second board mounted over said first board to form a plurality of wiring layers for electrical connections with the contact terminals, and a probe card mounted over a principal surface of said second board, provided with a plurality of electronic components to form a first circuit for electrical connection with a tester, and connected electrically with said first and second boards through a plurality of first wires; and (c) conducting electrical inspection of said semiconductor integrated circuit by coming end points of the contact terminals into contact with the first electrodes, (i) a third region electrically connected to the ground potential; (ii) a fourth region which surrounds said third region and to which a plurality of third wires for electrically connecting said first board with second board are connected; and (iii) a fifth region which surrounds said fourth region and to which a connecting means for electrically connecting said probe card with said tester is connected; and