Patent ID: 6707286
Filing Date: 2004-03-16
Classification: G05F

Abstract:
An enhanced output impedance current mirror comprising the following:a current source (I) having a first terminal connected to a high voltage source; a first nMOSFET(M1) having a source terminal that is connected to a low voltage source; a second nMOSFET (M2) having a source terminal that is connected to a drain terminal of the first nMOSFET(M1); a first pMOSFET (M3) having a gate terminal connected to the source terminal of the second nMOSFET (M2), having a source terminal connected to a second terminal of the current source (I), and having a drain terminal that is connected to a gate terminal of the second nMOSFET (M2); a second pMOSFET (M4) having a source terminal connected to the second terminal of the current source (I); a third nMOSFET (M5) having a gate terminal connected to a drain terminal of the second pMOSFET (M4), and having a drain terminal connected to the drain terminal of the first pMOSFET (M3); a fourth nMOSFET (M6) having a gate terminal connected to the gate terminal of the third nMOSFET (M5), having a drain terminal connected to the drain terminal of the second pMOSFET (M4), and having a source terminal connected to a gate terminal of the second pMOSFET (M4); a fifth nMOSFET (M7) having a gate terminal connect to the gate terminal of the third nMOSFET (M5), having a drain terminal connected to the source terminal of the third nMOSFET (M5), and having a source terminal connected to the low voltage source; and a sixth nMOSFET (M8) having a gate terminal connected to the gate terminal of the third nMOSFET (M5), having a drain terminal connected to the source terminal of the fourth nMOSFET (M6), and having a source terminal connected to the low voltage source.