Patent ID: 7772127
Filing Date: 2010-08-10
Classification: H01L

Abstract:
1. A method for reducing surface roughness in a semiconductor heterostructure that includes a substrate, a buffer layer and a top layer, which method comprises: providing the substrate with at least a surface layer having a first in-plane lattice parameter that corresponds to the lattice parameter value of the substrate material in a relaxed state; providing the buffer layer with a second in-plane lattice parameter and providing the buffer layer upon the surface layer of the substrate, the buffer layer having a surface that contains peaks and valleys; growing an additional layer upon the buffer layer, the additional layer having a third in-plane lattice parameter that corresponds to the lattice parameter value of the additional layer material in a relaxed state; and providing the top layer upon the additional layer, the top layer having a lattice parameter that corresponds to the lattice parameter value of the top layer material in a relaxed state, wherein the top layer and the additional layer are both in a strained state after being provided upon the additional layer and the buffer layer, respectively, and the third in-plane lattice parameter of the additional layer has a value in between those of the first and second lattice parameters to increase growth speed of the additional layer in the valleys compared to on the peaks of the surface of the buffer layer to thereby improve the surface roughness of the additional layer, and in turn, that of the top layer of the semiconductor heterostructure, wherein the thickness of each of the additional layer and of the top layer is less than the critical thickness above which defects occur.