Patent ID: 8624643
Filing Date: 2014-01-07
Classification: H03L

Abstract:
1. A semiconductor memory apparatus, comprising: a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock and output a comparison result signal; a delay circuit configured to delay the reference clock by a predetermined time based on the comparison result signal of the phase comparator to thereby generate rising and falling delayed clocks; a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases when receiving the comparison result signal; a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio; and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.