Patent ID: 6507074
Filing Date: 2003-01-14
Classification: H01L

Abstract:
An ESD protection device for semiconductor circuitry in a semiconductor substrate, comprising:first and second heavily doped active areas formed in the substrate as a source and a drain of a lateral CMOS transistor; a third heavily doped area formed in the substrate and separated from the first active area; a first well resistor between and at least partially under the first active area and the heavily doped third area and conductively coupled thereto, the first well resistor having a higher sheet resistance than the first active area and the third area; a first conductive layer disposed over the third area and electrically coupled thereto; a fourth heavily doped area formed in the substrate and separated from the second active area; a second well resistor formed in the substrate between and at least partially under the second active area and the fourth heavily doped area and conductively coupled thereto, the second well resistor having a higher sheet resistance than the second active area and the fourth area and disposed substantially in a straight line with the first well resistor; a second conductive layer disposed over the fourth area and conductively coupled thereto; a third conductive layer disposed over the fourth area and conductively coupled thereto; a first insulative layer disposed between the third heavily doped area and the first conductive layer; and a first plurality of contacts electrically connecting the first conductive layer to the third area, wherein the first and second active areas are covered with a silicide.