Patent ID: 6198334
Filing Date: 2001-03-06
Classification: H03K

Abstract:
A CMOS circuit comprising:a first PMOS transistor;a second PMOS transistor;a first NMOS transistor;a second NMOS transistor;a drain of said second PMOS transistor and a drain of said second NMOS transistor being each connected with a common output terminal,a source of said second PMOS transistor being connected with a drain of said first PMOS transistor.a source of said first PMOS transistor being connected with a power supply voltage,a source of said second NMOS transistor being connected with a drain of said first NMOS transistor,a source of said first NMOS transistor being grounded, andmeans for causing switching speeds or switching timings of said first PMOS transistor and said first NMOS transistor to differ from switching speeds or switching timings of said second PMOS transistor and said second NMOS transistor, respectively,wherein said means causes switching speeds or switching timings of said second PMOS transistor and said second NMOS transistor to be delayed relative to switching speeds or switching timings of said first PMOS transistor and said first NMOS transistor, respectively, andwherein said means causes channel resistances of said second PMOS transistor and said second NMOS transistor to be greater than channel resistances of said first PMOS transistor and said first NMOS transistor, respectively.