Patent ID: 6642130
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method for fabricating a highly integrated transistor, comprising the steps of:forming a well region having a first conductive type on a silicon substrate; forming an isolation oxide layer on a desired region of a surface of the silicon substrate; forming a first pad oxide layer on the surface of the silicon substrate; forming a LDD (low doped drain) region and a source/drain region on an active region of the silicon substrate, wherein said LDD region and said source/drain region having a second conductive type; forming a pad nitride layer on the first pad oxide layer; forming a trench through sequential etching desired parts of the pad nitride layer, the first pad oxide layer, the source/drain region, and the LDD region to expose side surfaces of the source/drain region and the LDD region; forming a second pad oxide layer along the exposed side surfaces of the source/drain region, the LDD region and on a bottom of the trench; removing a portion of the second pad oxide layer formed at the bottom of the trench and portions of the LDD region and the upper pan of the well region; forming a gate in the trench; forming an interlayer insulating layer on the surface of the silicon substrate including the gate; etching the interlayer insulating layer to form contact holes; and forming a source electrode, a drain electrode, and a gate electrode, each of which is electrically connected with the source/drain region and the gate.