Patent ID: 6097643
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A semiconductor storage apparatus comprising:a plurality of memory-cells arranged in an array and composed of regular memory-cell blocks and redundant memory-cell blocks;a regular DQ line shared by physically adjacent columns for each of a plurality of memory cells in each of the regular memory-cell blocks, and a redundant DQ line shared by physically adjacent columns for each of a plurality of memory cells in each of the redundant memory-cell blocks, the plural memory-cell groups being grouped into at least two groups sharing said each DQ line;means for storing the addresses of columns in which the defects have been generated in the regular memory-cell blocks when at least two defects were detected in data lines of a plurality of regular memory cell-blocks;means for grouping the redundant memory-cell blocks into groups in accordance with the changed groups corresponding to the addresses of the defective column in the data lines in the regular memory-cell blocks which share the DQ lines; andmeans for substituting the changed grouping portions of the redundant memory-cell blocks for the corresponding regular memory-cell blocks in which includes the defect.