Patent ID: 6548346
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method of forming a DRAM, comprising:providing a substrate having a transfer transistor, the transfer transistor including a gate electrode having a protective layer formed on an upper surface and a sidewall of the gate electrode, a first source/drain region and a second source/drain region; forming a first dielectric layer over the transistor; forming a self-aligned contact via by etching the first dielectric layer while using the protective layer as a mask to protect the gate electrode, the self-aligned via exposing at least a portion of the first source/drain region and at least a portion of the protective layer formed on the upper surface of the gate electrode; depositing a first conductive layer within the self-aligned contact via and over the protective layer, the first conductive layer being electrically connected with the first source/drain region; providing a sacrificial layer over the first conductive layer; patterning the sacrificial layer to form a sacrificial structure having sidewalls; forming spacers on the sidewalls of the sacrificial structure; removing the sacrificial structure; and etching, in a first anisotropic etching process, the first conductive layer using the spacers as a mask after the sacrificial structure is removed to form a vertically extending conductive structure electrically connected to the first source/drain region.