Patent ID: 6735667
Filing Date: 2004-05-11
Classification: G09G,G11C,H04B

Abstract:
A synchronous data system comprising:A. a processor that includes an address port, the address port including a certain number of plural address terminals sending parallel address signals to external the processor, the address signals occurring in plural groups separated in time, the address signals indicating an address of a random location in memory; and B. a synchronous dynamic random access memory device including: i. a single chip integrated circuit; ii. a dynamic random access memory array formed on the chip, the array including plural array data leads carrying parallel data signals to and from the array and parallel array address leads carrying parallel address signals to the array, one data signal representing one data bit and one address signal representing one address bit, the array being organized in plural addressable locations with each location containing one data word of plural data bits and each location being randomly addressable by the address signals for writing and reading of one word of data bits from the array data leads to each addressed location; iii. a first clock signal terminal formed on the chip for receiving a first clock signal formed of rising and falling edges regularly spaced in time, the first clock signal being continuous during operation of the device; iv. a second clock signal terminal formed on the chip for receiving a second clock signal formed of rising and falling edges regularly spaced in time, the second clock signal being continuous during operation of the device; v. an address port formed on the chip, the address port including plural address terminals coupled to the plural address terminals of the processor and receiving parallel address signals from the processor, the received address signals occurring in plural groups separated in time and being received while the first and second clock terminals receive the first and second continuous clock signals, the address terminals being coupled to the array address leads and the received address signals indicating an address of a random location in the array, the address port including a control data buffer connected to the plural address terminals, the control data buffer receiving address control data signals from the address terminals for controlling the parallel address signals carried to the array; vi. plural data terminals formed on the chip for sending and receiving parallel data signals, each set of parallel data signals representing one data word; vii. an input data port formed on the chip and coupling the plural data terminals with the array data leads, the input data port receiving the parallel data signals synchronous with the first continuous clock signal for writing the data signals in the array at the random location indicated by the received address signals; and viii. an output data port formed on the chip and coupling the array data leads with the plural data terminals, the output data port sending the parallel data signals synchronous with the second continuous clock signal for reading the data signals from the array at the random location indicated by the received address signals.