Patent ID: 6501693
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory device having a test mode and a normal mode as operation modes, comprising:a memory array including a plurality of memory cells arranged in a matrix; a plurality of word lines for selecting a row of said memory cells; a row decoding circuit for activating a word line corresponding to an address signal out of said plurality of word lines in accordance with a word line activating signal; a plurality of bit line pairs provided in correspondence with columns of said memory cells; a sense amplifier circuit for amplifying data held in said plurality of memory cells read on said plurality of bit line pairs in accordance with a sense amplifier activating signal; and a timing control circuit for outputting said word line activating signal and said sense amplifier activating signal in accordance with an external control signal in said normal mode, making a phase relation between said word line activating signal and said sense amplifier activating signal different from that in said normal mode and outputting the resultant phase relation in accordance with a timing test signal supplied from the outside in said test mode.