Patent ID: 8446175
Filing Date: 2013-05-21
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semiconductor substrate; field oxide located at a top surface of said substrate, said field oxide having a plurality of openings which expose said substrate; an n-well located in said substrate, such that a plurality of said openings in said field oxide are located in said n-well; a p-well located in said substrate, such that a plurality of said openings in said field oxide are located in said p-well; a layer of gate dielectric material located at said top surface of said substrate in said openings in said field oxide; a plurality of gate elements located on said layer of gate dielectric material; a plurality of n-type source/drain (NSD) regions located in said substrate in said openings in said field oxide in said p-well; a plurality of p-type source/drain (PSD) regions located in said substrate in said openings in said field oxide in said n-well; a pre-metal dielectric (PMD) layer located over said field oxide, said gate elements, said NSD regions and said PSD regions; a plurality of contacts located in said PMD layer, said contacts making electrical connection to said gate elements, said NSD regions and said PSD regions; a plurality of metal interconnects located over said PMD layer, said metal interconnects making electrical connection to said contacts; an area containing logic gates, including: a logic-cell-compatible decoupling capacitor located adjacent to said area containing logic gates, said logic-cell-compatible decoupling capacitor including;