Patent ID: 6219758
Filing Date: 2001-04-17
Classification: G06F

Abstract:
A computer system comprising:a central processor having a pipeline for processing data and a prefetching mechanism for fetching lines of data from a hierarchical memory system storing lines of data to be used in said central processor's pipeline and having a mechanism for rescinding delayed requests for data to be fetched from said hierarchical memory system,said hierarchical memory system having at least a first level of cache memory and a storage subsystem, including main memory,said central processor using logical addresses which are absolute and virtual addresses to access data, and often using virtual addresses for requests for data to be fetched from said storage subsystem,said hierarchical memory system using absolute addresses to access data, and including as a part of the first level of the cache memory a translator with translation logic that translates virtual and real addresses to absolute addresses, and whereinsaid central processor sends requests for data to said hierarchical memory system via the first level cache, and when requested data are not resident in the first level of cache the request for data is delayed and is forwarded to a lower level of said hierarchical memory, and when results in cancellation of any process during a delayed request that sends back an exception for rescinding outstanding line fetches and for canceling translations of data prefetched from said memory which are not needed for future processing, wherein a cancellation request is sent to storage subsystem and to said translation, and either the storage subsystem and translator may honor the request for recision or not honor the request for recision, and while said delayed request may be rescinded by said central processor, it is only honored after the central processor has reached an interruptible stage in its pipeline logic at which point an exception for rescinding outstanding line fetches and for canceling translations of data prefetched from said memory which are not needed for future processing is forced clearing all the wait states while the central processor ignores the exception for rescinding outstanding line fetches and for canceling translations of data prefetched from said memory which are not needed for future processing and until the last interruptable state is reached a request for recision is ignored and the delayed request is completed.