Patent ID: 7818538
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A serial decoder comprising: an address input; a plurality of word line outputs; and a plurality of shift register stages; wherein respective ones of the shift register stages are connected to a previous and a next one of the shift register stages so that data shifts through said shift register stages in a circular fashion; wherein, at half of the plurality of the shift register stages, the contents of the previous shift register stage for respective ones of the shift register stages of the half of the plurality of shift register stages are configured to be gated using the address input; wherein, at the other half of the plurality of the shift register stages, the contents of the previous shift register stage for respective ones of the shift register stages of the other half of the plurality of the shift register stages are configured to be gated using the inverse of said address input; and wherein a respective word line output is configured to be driven by a respective shift register stage.