Patent ID: 6323034
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A process for manufacturing a thin film transistor, comprising:(a) providing a transparent insulating substrate and depositing thereon a first layer of chromium;(b) patterning and etching said first layer of chromium to form a gate electrode having a width;(c) depositing a layer of gate insulation over said gate electrode and the substrate;(d) depositing a layer of undoped amorphous silicon over said layer of gate insulation;(e) depositing a layer of N+ amorphous silicon over said layer of undoped amorphous silicon,(f) depositing a second layer of chromium over said N+ layer of amorphous silicon;(g) patterning and etching the second chromium layer, the N+ amorphous silicon layer, and the undoped amorphous silicon layer to form a channel pedestal having a width;(h) forming insulating spacers on all vertical surfaces of said channel pedestal,steps (g) and (h) further comprising:forming the channel pedestal using a mask of photoresist,removing the photoresist;growing a dielectric layer on all exposed surfaces of the channel pedestal;selectively removing all exposed chromium compounds, and, optionally, removing all exposed chromium;(i) depositing a layer of second level metal over the channel pedestal and the layer of gate insulation;(j) patterning and etching said layer of second level metal to form source and drain electrodes, symmetrically disposed over said channel pedestal and separated from one another by a gap; and(k) using the source and drain electrodes as a mask, etching the N+ amorphous silicon layer down to the level of the undoped amorphous silicon layer.