Patent ID: 8552530
Filing Date: 2013-10-08
Classification: H01L

Abstract:
1. A vertical transient voltage suppressor for ESD protection, comprising: a conductivity type substrate, having highly doping concentration and being a first type; a first lightly doped region, arranged on the conductivity type substrate and being a second type; a first heavily doped region, completely formed within the first lightly doped region and being the first type; a second heavily doped region, completely formed within the first lightly doped region and being the first type; a first deep heavily doped region, being the first type, arranged on the conductivity type substrate, neighboring the first lightly doped region, and coupled to the first heavily doped region; and a first pin, connected to the second heavily doped region, wherein the first pin is connected to a circuit terminal to be protected; a second pin, connected to the conductivity type substrate, wherein the second pin is connected to a ground terminal; wherein the first type and the second type are opposite.