Patent ID: 8055978
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. A buffer memory comprising: a memory cell array having a plurality of word lines, each of the plurality of word lines electrically connected to a plurality of memory cells storing first data; a flag cell array having a plurality of flag cells, each of the plurality of flag cells electrically connected to each of the word lines and storing information that indicates whether error correction of the first data has been performed; and an error correction block performing error correction on the first data output from the memory cell array in response to a command received through a host interface and a first flag data output from the flag cell array, wherein the error correction block comprises: a flag sense amplifier for receiving and amplifying the first flag data output from the flag cell array and for outputting amplified first flag data; a controller for receiving the amplified first flag data in response to the command received through the host interface, generating an error correction enable signal and a wait signal based on received first flag data and outputting one of the wait signal to the host interface and the first data to the host interface; and an error correction logic for performing the error correction of the first data in response to the error correction enable signal and for outputting a result of the error correction to the controller.