Patent ID: 8559253
Filing Date: 2013-10-15
Classification: G11C

Abstract:
1. A variable-resistance memory device comprising: a memory-cell array employing a plurality of memory cells and a plurality of common lines, the plurality of common lines each respectively connected to a predetermined number of bit lines, each of the plurality of memory cells including a storage element having a resistance varying in accordance with the direction of a voltage applied to said storage element and including an access transistor connected in series to said storage element between one of the bit lines and one of the source lines; and a voltage supplying circuit for setting a read voltage used for reading out said resistance of said storage element on a selected bit line connected to said memory cell serving as a read object in an operation to supply said read voltage to said selected bit line by electrically pre-charging a common line of said plurality of common lines and the selected bit line, said selected bit line being coupled to said common line, and discharging pre-charge voltage of said selected bit line to share charge with unselected bit lines of the predetermined number of bit lines connected to the common line.