Patent ID: 6794945
Filing Date: 2004-09-21
Classification: H03L,H04L

Abstract:
A system for generating de-serializing timing signals for a serial bit stream word of M bits including data and framing bits, the system comprising:a voltage controlled oscillator with a number of outputs equal to M, wherein the outputs are equally offset from each other in phase over the period of about M bits, wherein each phase in succession about matches the corresponding successive bits in the bit stream, a phase detector arranged to receive the serial bit stream word and a phase output from the voltage controlled oscillator, wherein the phase detector compares the serial bit stream word to the voltage controlled oscillator phase output, a control signal output from the phase detector, wherein the control signal indicates whether the voltage control oscillator phase output must go faster or slower, and wherein the voltage controlled oscillator output, in response to the control signal, becomes phase locked to the serial bit stream word, a reset signal input to the phase detector, wherein when the reset signal is true the control signal is disabled and when the rest signal is false the control signal is enabled, circuitry receiving a combination of voltage controlled oscillator phase outputs and logically forming the reset signal therefrom, wherein the reset signal is false for the last of the M bits to the beginning of the second of the M bits, thereby defining a time window where the control signal is active.