Patent ID: 9191196
Filing Date: 2015-11-17
Classification: H04L

Abstract:
1. A server computer comprising: a server-participant communication module configured to receive: an evaluation module configured to evaluate an arithmetic circuit based on the first concealed input and the second concealed input, and to generate a concealed output; and a processing device configured to execute the server-participant communication module and the evaluation module, wherein the server-participant communication module is further configured to send the concealed output to the first participant module and the second participant module, wherein the evaluation module is further configured to perform multiple multiplication operations using the multiple first components of the first concealed input, the multiple second components of the second concealed input, and a modifier factor provided by the first participant module or the second participant module, and wherein actual values of the first concealed input, the second concealed input, and the concealed output are not revealed to the server computer.