Patent ID: 6240484
Filing Date: 2001-05-29
Classification: G06F

Abstract:
A cache for temporarily storing information for use by a functional unit of a processor, the functional unit of the processor operating using logical addresses, the processor accessing a device external to the processor using physical addresses, the processor translating between logical addresses, linear addresses and the physical addresses, the cache comprising:a store array having a plurality of lines for temporarily storing information; anda linear tag array having a plurality of linear address tag locations for storing a corresponding plurality of linear address tags, said plurality of linear address tag locations corresponding to said plurality of lines of said store array, each linear address tag location storing a linear address tag indicating a linear address of the information stored in a corresponding line of said store array;a translation lookaside buffer having a plurality of linear tag value locations and a corresponding plurality of physical address locations, each of said plurality of linear tag value locations storing a linear tag value indicating a linear address and each of said corresponding plurality of physical address locations storing a corresponding physical address, said corresponding physical address being a translation of said linear address.