Patent ID: 6744677
Filing Date: 2004-06-01
Classification: G11C,H01L

Abstract:
A method of erasing data in an EEPROM using a single power supply, including a memory cell array having a plurality of memory cells, each memory cell comprising a storage transistor including a substrate having a first conductivity type and provided therein with a source and a drain each of a second conductivity type, a floating gate disposed over the substrate and a control gate disposed over the floating gate, said method comprising steps of:applying a first voltage higher than both a supply voltage based on the single power supply and a ground voltage to the control gate of the storage transistor of each of selected memory cells; applying a second voltage lower than both the supply voltage and the ground voltage to at least one of the source and drain of the storage transistor of each of the selected memory cells while the first voltage is applied to the control gate, whereby electrons are injected into the floating gate when both the first and second voltages are applied; and applying said ground voltage to at least one of the source and drain of the storage transistor of a non-selected memory cell, whereby the data in said selected memory cells are erased simultaneously.