Patent ID: 8994100
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer; source and drain regions of a first conductivity type that are provided separately from each other in the semiconductor layer; a source offset region of the first conductivity type that is formed to contact the source region of the semiconductor layer via a first well region of the first conductivity type, with a lower concentration than those of the source region and the drain region; a drain offset region of the first conductivity type that is formed to contact the drain region of the semiconductor layer via a second well region of the first conductivity type while being separated from the source offset region, with a lower concentration than those of the source region and the drain region; a groove portion provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view; a gate insulating film that covers a side and a bottom of the groove portion; a gate electrode that is provided only within the groove portion in a plan view and contacts the gate insulating film; and an embedded region of a second conductivity type opposite the first conductivity type that is located deeper than the source region and the drain region, wherein the source region is surrounded by the source offset region in a plan view, and the drain region is surrounded by the drain offset region in a plan view.