Patent ID: 7847349
Filing Date: 2010-12-07
Classification: G06F

Abstract:
1. A circuit for generating updated Fast Fourier Transform (FFT) coefficients with a butterfly, the circuit comprising: a set of storage registers storing a twiddle factor, a first A coefficient and a first B coefficient for a current stage, wherein the twiddle factor, the first A coefficient, and the first B coefficient are complex-valued; a set of multipliers configured to combine the twiddle factor and the first B coefficient to provide an updated product register value, wherein the product register value is stored in a product register of the set of storage registers; and a set of combiners configured to derive a first pair of updated FFT coefficients for a subsequent stage with add/subtract operations based on the first A coefficient, first B coefficient, and the product register value, wherein the set of storage registers stores one or more subsequent A coefficients and one or more subsequent B coefficients corresponding to the twiddle factor, and the set of multipliers and the set of combiners are further configured so as to provide one or more subsequent updated FFT coefficients, wherein the circuit is configured to provide each pair of FFT coefficients in one clock cycle.