Patent ID: 6989575
Filing Date: 2006-01-24
Classification: B82Y,H01L

Abstract:
1. An array of microelectronic elements comprising: a substrate of semiconductor material; a lower layer of dielectric material disposed with a lower surface in contact with said substrate and an upper surface in spaced adjacency thereto; a pattern of mutually electrically isolated conducting regions disposed within said lower layer of dielectric material, said conducting regions extending to said upper surface of said lower layer; an upper layer of dielectric material disposed with a lower surface thereof in contact with and bonded to said upper surface of said lower layer; a plurality of nodes of semiconductor material disposed within said upper layer of dielectric material, each of said nodes being in electrical contact with only one of said conducting regions at said upper surface of said lower layer; and a bonding promoting layer formed on said lower layer of dielectric material, said bonding promoting layer bonding said lower surface of said upper layer of dielectric material to said upper surface of said lower layer, wherein each conducting region comprises: