Patent ID: 6362039
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method of forming a silicide interconnect layer and an integrated resistor in an integrated circuit, the method comprising:depositing a polysilicon layer over a first insulating layer; doping the polysilicon layer with a first amount of a dopant having a first conductivity type; depositing a second insulating layer over the polysilicon layer to cover a shielded polysilicon region and define an exposed polysilicon region not covered by the second insulating layer; after depositing the second insulating layer doping the exposed polysilicon region with a dopant of a second amount having an opposite conductivity type to the first conductivity type; depositing a refractory metal layer over the entire exposed polysilicon region; and forming the silicide over the entire exposed polysilicon region and leaving at least an unreacted portion of the exposed polysilicon region underlying the silicide to form the integrated resistor.