Patent ID: 6751741
Filing Date: 2004-06-15
Classification: G06F,Y02D

Abstract:
A power management apparatus used for a computer system which performs a CPU throttling operation of falsely reducing an operating frequency of a central processing unit (CPU), the power management apparatus comprising:an event detecting section to detect an event in said system; an activity detecting section to determine whether said system is in one of a busy state or an idle state, by checking whether there is activity in said system when said event detecting section detects said event; and a clock control section to start said CPU throttling operation when said system is in the busy state and to stop said CPU throttling operation when said system is in the idle state, wherein said clock control section includes a stop grant executing section, a stop clock executing section, and a CPU throttling executing section; said stop grant executing section causing said system to be in a stop grant state when said system is in the busy state; said stop clock executing section causing said system to be in a stop clock state when said system is in the idle state; and said CPU throttling executing section starting said CPU throttling operation when said system returns from the stop grant state and stopping said CPU throttling operation when said system returns from the stop clock state by a system timer, wherein said CPU throttling executing section starts said CPU throttling operation when said system returns from the stop grant state and when said system returns from the stop clock state due to an event other than said system timer, and stops said CPU throttling operation when said system returns from the stop clock state by said system timer.