Patent ID: 9190916
Filing Date: 2015-11-17
Classification: H02M

Abstract:
1. A control circuit of a DC/DC converter including a transformer having a primary winding and an auxiliary winding provided at a primary side and a secondary winding provided at a secondary side, a switching transistor connected to the primary winding, and a detection resistor provided on a path of the switching transistor, the control circuit comprising: a pulse modulator configured to generate a pulse signal having a duty cycle adjusted such that an output voltage of the DC/DC converter approaches a target value, based on a detection voltage across the detection resistor and a feedback voltage depending on the output voltage of the DC/DC converter; and a driver configured to switch the switching transistor based on the pulse signal, wherein the pulse modulator includes: an off signal generator configured to generate an off signal asserted depending on the feedback voltage and the detection voltage; and an on signal generator asserted depending on a voltage of one end of the auxiliary winding, wherein the pulse modulator is configured to generate the pulse signal which is shifted to an on level corresponding to turning-on of the switching transistor when the on signal is asserted and is shifted to an off level corresponding to turning-off of the switching transistor when the off signal is asserted, and wherein the on signal generator includes: a bottom detection comparator configured to compare the voltage of the one end of the auxiliary winding with a predetermined threshold voltage and generate a bottom detection signal asserted when the voltage of the one end of the auxiliary winding becomes lower than the threshold voltage; a first time-out circuit configured to generate a first time-out signal asserted when the bottom detection signal is not asserted during a first time-out period; a second time-out circuit configured to generate a second time-out signal asserted when the bottom detection signal is not asserted during a predetermined second time-out period shorter than the first time-out period; and a logic part configured to generate the on signal based on the bottom detection signal, the first time-out signal and the second time-out signal.