Patent ID: 7639058
Filing Date: 2009-12-29
Classification: G06F,H04L

Abstract:
1. A clock signal generation circuit comprising: a first counter circuit configured to generate a first reset signal by using a synchronizing signal and to count the number of rising edges of a first reference clock signal in accordance with the first reset signal; a second counter circuit configured to generate a second reset signal by using the counted number in the first counter circuit and to count the number of the rising edges of the first reference clock signal in accordance with the second reset signal wherein the second counter circuit is connected to the first counter circuit; a first divider circuit configured to generate a second reference clock signal by dividing a frequency of the first reference clock signal in accordance with the first reset signal wherein the first divider circuit is connected to the first counter circuit; a reset signal generation circuit configured to output one of the first reset signal and the second reset signal as a third reset signal wherein the reset signal generation circuit is connected to the first counter circuit and the second counter circuit; and a second divider circuit configured to generate a clock signal by dividing a frequency of the second reference clock signal in accordance with the third reset signal wherein the second divider circuit connected to the first divider circuit and the reset signal generation circuit.