Patent ID: 6427202
Filing Date: 2002-07-30
Classification: G06F

Abstract:
A microcontroller having an instruction set composed of two or more instruction subsets, each of said instruction subsets having a specific functionality, each of said instruction subsets constructed and arranged to be either enabled or disabled to provide selected functionality for said microcontroller, said microcontroller comprising:program memory, said program memory constructed and arranged to contain at least one coded instruction; a decoder connected to said program memory, said decoder constructed and arranged to decode said coded instruction fetched from said program memory into a decoded instruction; and an instruction enabler, said instruction enabler constructed and arranged to receive said decoded instruction from said decoder, said instruction enabler further constructed and arranged to determine if said received decoded instruction is present in an enabled instruction subset, said instruction enabler further constructed and arranged to enable execution of said received decoded instruction if said received decoded instruction is included in an enabled instruction subset.