Patent ID: 6127843
Filing Date: 2000-10-03
Classification: H03K

Abstract:
A field programmable gate array device comprising:(a) a first plurality, P1 of repeated logic units wherein:(a.1) each said logic unit is user-configurable to receive and process at least a second plurality, P2 of input logic bits and to responsively produce result data having at least a third plurality, P3 of output logic bits,(a.2) said logic units are distributed among a plurality of horizontal rows, with each row of the plurality of rows having a fourth plurality, P4 of said logic units;(a.3) said logic units are further distributed among a plurality of vertical columns, with each column of the plurality of columns having a fifth plurality, P5 of said logic units;(b) a sixth plurality, P6 of horizontal interconnect channels (HIC's) correspondingly distributed adjacent to said horizontal rows of logic units, wherein:(b.1) each said horizontal interconnect channel (HIC) includes at least P3 interconnect lines, and(b.2) each said horizontal row of P4 logic units is configurably couplable to a corresponding one of the P6 HIC's at least for receiving input logic bits from the corresponding HIC or at least for outputting result data to the corresponding HIC;(b.3) each said logic unit can internally process its respective second plurality of input logic bits without using said horizontal interconnect channels or other general interconnect for such internal processing; and(c) an embedded memory subsystem, wherein said embedded memory subsystem includes:(c.1) a seventh plurality, P7 of independently-usable memory blocks, and wherein:(c.1a) each said memory block is embedded within one of said rows of logic units and is configurably couplable to the corresponding HIC of said row for transferring storage data by way of the corresponding HIC of that row of P4 logic units; and(c.1b) plural ones of said memory blocks are arranged to define one or more columns of embedded memory within said field programmable gate array device with each such column having an eighth plurality, P8 of said memory blocks.