Patent ID: 9160290
Filing Date: 2015-10-13
Classification: H03F

Abstract:
1. A Class D power amplifier for driving a load between first and second output nodes, comprising: a first output half-bridge circuit comprising first, highside, and second, lowside, transistors in series between power rails, with the first output node between the first and second transistors; a second output half-bridge circuit comprising third, highside, and fourth, lowside, transistors in series between power rails, with the second output node between the third and fourth transistors; a first controller circuit of the first output half-bridge circuit for generating gate drive signals for the highside and lowside transistors in the first output half-bridge circuit; and a second controller circuit of the second output half-bridge circuit for generating the gate drive signals for the highside and lowside transistors in the second output half-bridge circuit, wherein the first and second controller circuits are adapted to: derive an amplifier hold signal in response to an overcurrent state being detected in one output half-bridge circuit and an output state of one of the half-bridge circuits, and to prevent switching of the other output half-bridge circuits based on the hold signal.