Patent ID: 8347040
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A system comprising: an interconnect; a plurality of agents coupled to the interconnect, wherein each agent of the plurality of agents comprises a level 1 (L1) cache; a level 2 (L2) cache coupled to the interconnect and shared among the plurality of agents; and at least one memory controller coupled to the interconnect and configured to couple to a memory, wherein the L2 cache and the plurality of agents are configured to snoop on the interconnect to maintain cache coherency between the memory, the L2 cache, and the L1 cache, and wherein the L2 cache is configured to invalidate a first cache block supplied by the L2 cache to the L1 cache in an exclusive state, wherein the L2 cache is configured to invalidate the first cache block in the L2 cache in response to providing the first cache block to the L1 cache in the exclusive state and the first cache block was in the exclusive state in the L2 cache immediately prior to invalidation, and wherein an exclusive block is unmodified with respect to corresponding data stored in the memory, and wherein the L1 cache is configured to write a second cache block to the L2 cache in response to evicting the second cache block in the exclusive state, and wherein the L2 cache is configured to respond to any read snoop hit in the L2 cache in any L2 cache state, independent of a response from other agents of the plurality of agents, by supplying data.