Patent ID: 6768173
Filing Date: 2004-07-27
Classification: H01L

Abstract:
A method for making an integrated circuit with a high voltage NMOS transistor comprising:implanting and diffusing a first concentration of N-type dopant into a P-type semiconductor substrate to form an N-type buried layer; implanting a second concentration of P-type dopant into the N-type buried layer; growing a P-type epitaxial layer over the P-type substrate, wherein P-type dopant of the second concentration diffuse into the epitaxial layer farther than N-type dopant of the first concentration to form a P-type up-retro well in the epitaxial layer; and implanting and diffusing N-type dopant into the epitaxial layer above the up-retro well to form a source region and a drain region for the NMOS transistor.