Patent ID: 7763987
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate including first regions and a second region, wherein the first regions are arranged along a row extending along a row direction; a buried mask comprising a first trim opening arranged above the first regions and a second trim opening arranged above the second region; a top mask comprising first template openings, each template opening being arranged above a respective first region, and a second template opening arranged above the second region; first contacts extending between an upper edge of the top mask and the first regions, wherein each first contact passes through a corresponding first template opening and the first trim opening and is in contact with the buried mask on two opposing sides of the buried mask and is further in contact with the top mask on two opposing sides of the top mask; and a second contact extending between an upper edge of the top mask and the second region, wherein the second contact passes through the second template opening and the second trim opening and is in contact with the buried mask on two opposing sides of the buried mask and is further in contact with the top mask on two opposing sides of the top mask.