Patent ID: 7197053
Filing Date: 2007-03-27
Classification: H04J

Abstract:
1. A serializer circuit comprising: a first programmable delay element having a first input for a first input data signal, a first output, and at least one control input for a first number of control signals, said first programmable delay element being configured to generate, at said first output, a first delayed data signal representing said first input data signal delayed by a first delay amount determined by said first number of control signals; a second programmable delay element having a second input, for a second input data signal, a second output, and at least one control input for a second number of control signals, said second programmable delay element being configured to generate, at said second output, a second delayed data signal representing said second input data signal delayed by a second delay amount determined by said second number of control signals; and an output signal selector having a third input for a first selectable signal based on said first delayed data signal, a fourth input for a second selectable signal based on said second delayed data signal, and a third output, said output signal selector being configured to select, in response to a select signal having a frequency of F cycles/second, said first selectable signal or said second selectable signal for use as a serialized output signal at said third output; wherein said first input data signal and said second input data signal each convey data at a rate of F bits/second; said second input data signal is delayed relative to said first input data signal; and said serialized output signal conveys data at a rate of 2F bits/second.