Patent ID: 6826111
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A method comprising:provisioning a semiconductor memory device having at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions, each of the memory cells being assigned a physical address corresponding to the physical position of the memory cell in the memory cell array and an electrical address corresponding to the electrical addressing of the memory cell in the memory cell array; inputting of a physical address of a memory cell of the memory cell array that is to be addressed into an address input device of the semiconductor memory device; decoding of the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device; outputting of the electrical address to the memory cell array in order to address the memory cell to be addressed; inputting data that to be written to the memory cell, to be addressed, and have two logic data states into a data input device of the semiconductor memory device; decoding of the input data by a data decoder device of the semiconductor device in such a way that in the event of data inputting of the first logic data state, such a decoded data state is generated which is assigned to a predetermined first physical memory state of the memory cell to be addressed, and in the event of data inputting of the second logic data state, such a decoded data state is generated which is assigned to a predetermined second physical memory state of the memory cell to be addressed; and outputting of the decoded data state to the memory cell array in order to bring the memory cell to be addressed into the respective physical memory state.