Patent ID: 6359806
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A memory device comprising:a memory array including a plurality of nonvolatile memory cells arranged in a matrix fashion, each of said nonvolatile memory cells having a control gate and a floating gate and having a threshold voltage corresponding to data held therein; and an error correcting circuit which receives data read from a plurality of memory cells in said memory array and which generates syndromes to indicate whether the read-out data includes any error and to correct said any error included in the read-out data, wherein said read-out data are sent in a predetermined block from said memory array to said error correcting circuit while being externally output simultaneously, wherein said error correcting circuit externally outputs, either upon completion of the data output or immediately thereafter, an error status signal indicating whether any error is included in said read-out data, and wherein upon detection of any error in said read-out data of said predetermined block from said memory array, said error correcting circuit corrects said error.