Patent ID: 6044121
Filing Date: 2000-03-28
Classification: G06F

Abstract:
An apparatus for receiving data from a parallel data bus which transfers the data at a bus clock rate, the parallel data bus comprising a plurality of data lines, a data signal transfer on the parallel data bus being preceded by a start-of-cell delimiter consisting of a predetermined sequence of pulses transferred at the bus clock rate on each of the data lines, the apparatus comprising:sampling logic for sampling the data signal on each of the data lines at a sampling rate which is higher than the bus rate;a sample register which, for each of the data lines on the bus, stores a plurality of samples of the respective data signal, the number of samples stored being large enough to store at least some of the pulses constituting the respective start-of-cell delimiter, the sample register outputting the stored samples synchronous with a local clock operating at the bus clock rate;start-of-cell detection logic which, for each of the data lines on the bus, determines that a start-of-cell delimiter is output by the respective sample register; andcenter selection logic responsive to the start-of-cell detection logic which, for each of the data lines on the bus, determines which one of the samples output by the sample register represents an approximate center sample of one of the pulses of the start-of-cell delimiter for that data line, the center selection logic outputting the approximate center sample determined for each of the data lines on the bus.