Patent ID: 7936582
Filing Date: 2011-05-03
Classification: G11C

Abstract:
1. An integrated circuit comprising: an E-fuse cell memory array including a plurality of E-fuses; a plurality of E-fuse sense circuits; wherein each E-fuse sense circuit is coupled to a subset of the plurality of E-fuses, and each E-fuse sense circuit is configured to produce a read voltage according to a fuse resistance of a selected one of the subset of the plurality of E-fuses during a read operation; a plurality of reference cells disposed along a perimeter edge of the E-fuse memory cell array; wherein each reference cell includes a reference sense circuit corresponding to one of the plurality of E-fuse sense circuits, and each reference sense circuit is configured to produce a reference voltage according to a reference resistance of an on-chip reference resistor during the read operation, each reference sense circuit replicating the corresponding E-fuse sense circuit; and a plurality of comparators, each comparator coupled to one of the plurality of the E-fuse sense circuits and to one of the reference sense circuits and configured to produce a bit value according to a difference between the read voltage and the reference voltage.