Patent ID: 8982642
Filing Date: 2015-03-17
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory comprising: a three-dimensional (3D) memory cell array including a substrate and a memory block, the memory block including an array of memory cell strings extending vertically over the substrate, wherein the memory block includes first and second sub-blocks stacked over the substrate such that the first sub-block includes a first sub-set of memory cells of each memory cell string and the second sub-block includes a second sub-set of memory cells of each memory cell string; an address decoder connected with the memory cell array via a plurality of word lines; and a voltage generator configured to generate an erase voltage supplied to the substrate during an erase operation of a selected sub-block among the first and second sub-blocks, wherein the address decoder is configured to supply a selection word line voltage to word lines connected with the selected sub-block among the first and second sub-blocks, to supply a non-selection word line voltage to word lines connected with an unselected sub-block among the first and second sub-blocks during a first delay time from a point of time when the erase voltage is supplied, and to float the word lines connected with the unselected sub-block after supplying the non-selection word line voltage.