Patent ID: 9034704
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method for forming a memory device, said method comprising: forming a first plurality of semiconductor nanowires tethered between first and second landing pads and suspended over a substrate; forming a first gate electrode extending across said first plurality of semiconductor nanowires, each of said first plurality of semiconductor nanowires being surrounded by said first gate electrode, said semiconductor nanowires of said first plurality thereby being gate-all-around (GAA) semiconductor nanowires; forming a first, a second, and a third field effect transistor (FET), with said first gate electrode, each of said first, second and third FETs including at least one of said first plurality of semiconductor nanowires; forming a source/drain contact for each of said first, second, and third FETs, each of said source/drain contacts being elevated over said first and second landing pads and said first gate electrode relative to said substrate; forming a second plurality of semiconductor nanowires tethered between third and fourth landing pads and suspended over said substrate, one of said third and fourth landing pads being aligned with said first gate electrode; forming a second gate electrode extending across said second plurality of semiconductor nanowires, said second gate electrode being aligned with one of said first and second landing pads of said first plurality of semiconductor nanowires, each of said second plurality of semiconductor nanowires being surrounded by said second gate electrode, said semiconductor nanowires of said second plurality thereby being GAA semiconductor nanowires; forming a fourth, a fifth, and a sixth field effect transistor (FET), with said second gate electrode, each of said fourth, fifth and sixth FETs including at least one of said second plurality of semiconductor nanowires; forming a source/drain contact for each of said fourth, fifth, and sixth FETs, each of said source/drain contacts being elevated over said third and fourth landing pads and said second gate electrode relative to said substrate; coupling said first gate electrode to said aligned one of said third and fourth landing pads of said second plurality of semiconductor nanowires; coupling said second gate electrode to said aligned one of said first and second landing pads of said first plurality of semiconductor nanowires; forming a gate contact on each of said first and second gate electrodes, each of said gate contacts being elevated over said source/drain contacts relative to said substrate; connecting said source/drain contact of said first FET to a bitline connection; connecting said source/drain contacts of said second and fifth FETs to ground connections; connecting said source/drain contacts of said third and fourth FETs to operating voltage connections; connecting said source/drain contact of said sixth FET to a bitline bar connection; and connecting said gate contacts of said first and second gate electrodes to a word line connection.