Patent ID: 6159773
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A process for forming a stress release contacting system in an integrated circuit, comprising the sequential steps of:(a) providing a silicon wafer containing a completed integrated circuit and having an upper surface on which are contact pads connected to said integrated circuit;(b) forming first metal posts, attached one-on-one to the contact pads and extending vertically upwards from the contact pads;(c) placing a leveling plate on said metal posts;(d) through application of force to said leveling plate at an elevated temperature, causing the posts to tilt at an angle relative to said wafer upper surface and to point in a direction;(e) filling all empty space between the leveling plate and the wafer surface with an elastomer while leaving all ends of the posts uncovered;(f) removing the leveling plate;(g) forming second metal posts that attach one-on-one to said uncovered ends;(h placing a leveling plate on said metal posts;(i) through application of force to said leveling plate at an elevated temperature, causing the posts to tilt at said angle relative to said wafer upper surface and to point in a direction that is orthogonal to the direction of the most recently formed posts;(j) repeating steps (e) through (i) a number of times;(k) filling all empty space between the leveling plate and the wafer surface with an elastomer while leaving all ends of the posts uncovered;(l) removing the leveling plate;(m) forming pads of underlayer barrier metal over all uncovered ends of said posts; and(n) forming solder balls that extend upwards and are attached to the underlayer barrier metal pads.