Patent ID: 6992919
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. A three-dimensional circuit comprising a plurality of stacked levels on a substrate, each level comprising a plurality of all-metal circuit components arranged in two dimensions, the plurality of circuit components on at least one of the levels comprising a plurality of memory cells, each memory cell comprising a multi-layer structure exhibiting magnetoresistance, each multi-layer structure comprising a plurality of magnetic layers at least one of which is operable to magnetically store a bit of information, a plurality of access lines integrated with the plurality of magnetic layers and configured such that the bits of information may be accessed using selected ones of the plurality of access lines and a magnetoresistive effect, and at least one keeper layer, wherein the magnetic layers, the access lines, and the at least one keeper layer associated with each multi-layer structure form a substantially closed flux structure, the circuit further comprising an interconnect for providing interconnections between the circuit components on different ones of the plurality of levels.