Patent ID: 7359247
Filing Date: 2008-04-15
Classification: G11C

Abstract:
1. A read-out circuit in a semiconductor memory device for reading out multilevel data stored in a memory cell to be read that is selected from a memory cell array arranged with a plurality of memory cells capable of storing multilevel data with three or more levels, the read-out circuit comprising: a read-out voltage generator circuit which converts a memory cell current flowing through the selected memory cell into a read-out voltage; a reference voltage generator circuit which sequentially selects one of reference memory cells each memory state of which is intermediately assigned between two adjacent data levels of the multilevel data ordered by the memory cell current and which converts a reference current flowing through the reference memory cell into a reference voltage; and a sense circuit that amplifies a change in the read-out voltage or a difference between the read-out voltage and the reference voltage for each selection of the reference memory cells, wherein the reference voltage generator circuit includes a reference loading circuit that supplies the reference memory cell with the reference current, wherein a current supply capability of the reference loading circuit is selectively determined in response to a change in the selection of the reference memory cell so as to suppress a change in the reference voltage derived from a change in the reference current, the read-out voltage generator circuit includes a main loading circuit that supplies the selected memory cell with the memory cell current, wherein a current supply capability of the main loading circuit is selectively determined in response to a change in the selection of the reference memory cell so as to increase or decrease in proportion to the current supply capability of the reference loading circuit.