Patent ID: 9202761
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A manufacturing method for a semiconductor integrated circuit device comprising: (a) preparing a semiconductor wafer having a thickness in a first direction and having a semiconductor wafer top surface and an opposing semiconductor wafer bottom surface in the first direction, a first insulator layer disposed on the semiconductor wafer top surface, and a semiconductor layer disposed on the first insulator layer; (b) removing the semiconductor layer and the first insulator layer of a second MISFET formation region so as to keep the semiconductor layer and the first insulator layer of a first MISFET formation region, wherein the first MISFET formation region includes the semiconductor wafer top surface and the second MISFET formation region includes the semiconductor wafer top surface; (c) forming a second insulator layer on the semiconductor wafer top surface of the second MISFET formation region after the step (b); (d) removing the second insulator layer after the step (c); (e) forming a device isolation region in the semiconductor wafer top surface after the step (d); (f) forming a gate electrode film over the semiconductor layer in the first MISFET formation region and over the semiconductor wafer top surface in the second MISFET formation region after the step (e); (g) patterning the gate electrode film thereby to form a first gate electrode of a first MISFET in the first MISFET formation region, and to form a second gate electrode of a second MISFET in the second MISFET formation region; (h) forming an interlayer insulative film to cover the first and second gate electrodes after the step (g); and (i) executing a CMP treatment on the interlayer insulative film to expose a top face of the first gate electrode and not to expose a top face of the second gate electrode after the step (h), wherein, after the step (g), a height in the first direction, directly below the first gate electrode, from the semiconductor wafer bottom surface to the semiconductor wafer top surface of the first MISFET formation region is higher than a height in the first direction, directly below the second gate electrode, from the semiconductor wafer bottom surface to the semiconductor wafer top surface of the second MISFET formation region, wherein, after the step (i), a height in the first direction from the semiconductor wafer bottom surface to the first gate electrode top face of the first MISFET formation region is higher than a height in the first direction from the semiconductor wafer bottom surface to a second gate electrode top face of the second MISFET formation region, wherein, a periphery of the first MISFET formation region and the second MISFET formation region is defined by the device isolation region, and wherein, the step (c) includes forming the second insulator layer on an upper surface of the semiconductor layer of the first MISFET formation region.