Patent ID: 9034703
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method of forming a semiconductor device comprising: providing a gate structure on a channel portion of semiconductor substrate that is present between a source region and a drain region of the semiconductor substrate, wherein the gate structure includes a gate sidewall spacer that is adjacent to a gate dielectric comprising a horizontal portion and two vertical portions, and a gate conductor of the gate structure; forming an interlevel dielectric layer over the source region and the drain region, wherein an upper surface of the interlevel dielectric layer is coplanar with an upper surface of the gate structure; recessing the upper surface of the gate conductor relative to the interlevel dielectric layer, wherein a recessed surface of the gate conductor is vertically offset and located beneath a topmost surface of the two vertical portions of the gate dielectric; forming a multi-layered cap on the recessed surface of the gate structure and contacting a sidewall surface of each vertical portion of the gate dielectric, wherein at least one layer of the multi-layered cap is comprised of a high-k dielectric material; and etching via openings to at least one of the source region and the drain region, wherein at least the high-k dielectric material protects a sidewall of the gate conductor from being exposed by the etching of the via openings.