Patent ID: 8461052
Filing Date: 2013-06-11
Classification: H01J,H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: preparing a wafer having a silicon layer on which a mask having a plurality of openings is located, the plurality of openings having M different widths, where M is a positive integer more than one; placing the wafer in a chamber; and forming a plurality of trenches simultaneously in the silicon layer of the wafer through the mask, the plurality of trenches having M different widths defined by the plurality of openings of the mask, wherein the forming of the plurality of trenches includes alternately and repeatedly performing a passivation step and an etching step, the passivation step includes depositing a polymer passivation layer on a side wall and a bottom of the plurality of trenches by converting gas introduced in the chamber into plasma, the etching step includes removing the passivation layer on the bottom of the plurality of trenches until the silicon layer is exposed to the bottom and applying reactive ion etching to the exposed silicon layer to increase a depth of the plurality of trenches, the etching step further includes setting incident ion energy for the reactive ion etching to a predetermined energy value when the passivation layer on the bottom of the trench having the Nth smallest width is removed, where N is a positive integer less than M, and the energy value allows the etching amount of the silicon layer at the bottom of the trench having the Nth smallest width to be equal to or greater than the etching amount of the silicon layer at the bottom of the trench having the (N+1)th smallest width within a remaining time of the present etching step.