Patent ID: 7943469
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a gate dielectric layer above a substrate; forming a gate electrode above said gate dielectric layer; forming a pair of tip extensions on either side of said gate electrode and in said substrate, wherein said pair of tip extensions defines a channel region in said substrate; forming a pair of gate isolation spacers on either side of said gate electrode and above said pair of tip extensions; removing a portion of said substrate on either side of said pair of gate isolation spacers to form a pair of etched-out regions in said substrate; forming a first portion of a pair of source/drain regions in said pair of etched-out regions; and forming a second portion of said pair of source/drain regions in said pair of etched-out regions directly above said first portion to form an interface between said second portion and said first portion, wherein the lattice constants of said first and said second portions are different from the lattice constant of said channel region, wherein said pair of source/drain regions imparts a strain to said channel region, wherein said channel region imparts a strain to said pair of source/drain regions, wherein the concentration of charge-carrier dopant impurity atoms of said second portion at said interface is greater than the concentration of charge-carrier dopant impurity atoms of said first portion at said interface by a factor of at least two, wherein said channel region has a first conductivity type, wherein said pair of source/drain regions has a second conductivity type, and wherein said first conductivity type is different from said second conductivity type.