Patent ID: 6065122
Filing Date: 2000-05-16
Classification: G06F,Y02D

Abstract:
A bridge logic unit, comprising:a programmable interrupt controller receiving at least one interrupt request signal; anda power management logic unit coupled to said programmable interrupt controller and capable of asserting a SLEEPREQ signal that causes a CPU clock to be turned off when SLEEPREQ is asserted;said power management logic unit comprising a first programmable CPU stop clock register including modulation bits by which the SLEEPREQ signal is dynamically modulated so that the SLEEPREQ signal is asserted only for a programmed number of cycles of a clock signal and a second programmable CPU stop clock register including modulation bits by which the SLEEPREQ signal is dynamically modulated so that the SLEEPREQ signal is asserted only for a programmed number of cycles of said clock signal when said SLEEPREQ signal is not being modulated by said first programmable CPU stop clock register, said programmed number of cycles defined by the value of said modulation bits of each of said stop clock registers.