Patent ID: 6818090
Filing Date: 2004-11-16
Classification: H01L,H05K,Y02P,Y10T

Abstract:
A semiconductor device in chip format, comprising:a chip; electrical connection pads disposed on said chip; a first passivation layer disposed on said chip such that said electrical connection pads are free of said first passivation layer on at least one surface; interconnects running on said first passivation layer and in each case leading from said electrical connection pads to base regions; a second passivation layer disposed on said interconnects and on said first passivation layer, said second passivation layer having openings formed therein leading to said base regions; at least one insulating layer disposed on said interconnects and on said second passivation layer, said at least one insulating layer having a layer thickness, said at least one insulating layer having openings formed therein leading to said base regions; cylinders of a conductive material with an elasticity, disposed in each of said openings; small balls disposed on said cylinders of said conductive material in a region of a free end of each of said openings, said small balls having an elasticity and being metallic at least on an outside; said at least one insulating layer being at least four times thicker than said first passivation layer; and said thickness of said insulating layer, said elasticity of said conductive material, and said elasticity of said small balls being selected for obtaining a desired level of comparatively good mechanical decoupling from a printed circuit board upon the semiconductor component being soldered onto the printed circuit board.