Patent ID: 6195744
Filing Date: 2001-02-27
Classification: G06F

Abstract:
A processor comprising:a plurality of execution units; anda scheduler coupled to the execution units, the scheduler comprising:a sequence of rows of entries, the sequence of rows beginning with a top row and ending with a bottom row, wherein each row contains a plurality of entries, each entry includes memory fields for storage of information describing an operation associated with the entry, and the memory fields of the entries of each row except the bottom row are coupled to the memory fields of the entries in a next row of the sequence to permit shifting of information from one row to the next in the sequence;logic which scans the entries to select operations for issue to the execution units for execution;logic which provides information from the entries to the execution units for execution of the issued operations; andlogic which stores results from execution of previously issued operations in the entries associated with the previously issued operations.