Patent ID: 8471320
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A memory array layout, comprising, a substrate; an active region array disposed on the substrate and having a plurality of active regions arranged along a first direction and a second direction, wherein the active regions along the second direction are arranged alternatively and parts of sides of the two adjacent active regions are partially overlapped along the second direction; a plurality of first doped regions, wherein each of the first doped regions is disposed in a middle region within each of the active regions; a plurality of second doped regions, wherein the second doped regions are disposed in distal end regions within each of the active regions; a plurality of recessed gate structures disposed between the middle regions and the distal end regions of the active regions in the substrate; a plurality of word lines disposed between the middle regions and the distal end regions of the active regions, wherein each of the word lines along a third direction perpendicular to the first direction is electrically connected to the respective recessed gate structure; a plurality of digit lines disposed above the word lines, wherein each of the digit lines along the first direction is electrically connected to the respective first doped region in the active region; and a plurality of capacitors disposed above the second doped regions wherein each capacitor is electrically connected to the respective second doped region via a self-aligned contact plug, wherein the self-aligned contact plug is between the respective two adjacent digit lines and the respective two adjacent word lines.