Patent ID: 6639276
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A power semiconductor device comprising:a substrate of a first conductivity type; an epitaxial layer of a first conductivity type formed on a surface of said substrate; a plurality of lightly doped base regions of a second conductivity type formed to a first predetermined depth in said epitaxial layer, said base regions being spaced from one another; common conduction regions disposed between said base regions; a plurality of highly doped source regions of the first conductivity type formed in said lightly doped base regions; invertible channel regions disposed between said source regions and said common conduction regions; deep implanted junctions of said second conductivity type formed in said epitaxial layer under said base regions extending between said first predetermined depth to a second predetermined depth; gate electrodes formed over said invertible channels, said gate electrodes being insulated from said invertible channels by an insulation layer; and thick insulation spacers disposed over at least a portion of said common conduction regions.