Patent ID: 7852974
Filing Date: 2010-12-14
Classification: G01R,G06F,H04B,H04J,H04L

Abstract:
1. A device comprising; A. a clock input lead, B. a mode input lead, C. a data input lead, D. a data output lead, E. first communication circuitry having a data input coupled to the data input lead, a clock input coupled to the clock input lead, a mode input coupled to the mode input lead and a data output coupled to the data output lead, the first circuitry operating according to a first protocol that includes an idle state and a communication state with the states changing in response to steady state mode input signals at the time of changing clock input signals; and F. second circuitry having a clock signal input coupled with the mode input lead, and a mode input signal coupled to the clock input lead, the second circuitry operating according to a second protocol that is different from the first protocol.