Patent ID: 6101198
Filing Date: 2000-08-08
Classification: H04Q

Abstract:
A processor-based apparatus for performing a time slot interchange completely therewithin, comprising:a processor having an input serial port, an output serial port, a memory, and a program control unit to control the processor based on stored instructions and external commands;wherein the memory of the processor is configured to create two input buffers, an even input buffer and an odd input buffer, into which an input serial data stream received through the input serial port can be buffered to allow one of the input buffers to be emptied while the other of the input buffers is being filled;wherein the memory of the processor is also utilized to create an output buffer from which an output serial data stream can be generated and supplied out of the processor through the output serial data port;wherein the program control unit of the processor controls the memory to transfer data between the input buffers and the output buffer in fashion which remaps the data in the input buffer into data in the output buffer to perform a time slot interchange, wherein the program control unit of the processor includes two connection arrays, a connection array for the even input buffer and a connection array for the odd input buffer, wherein the connection arrays have connection data stored therewithin that the program control unit utilizes to remap the data from given slots in the input buffers into given slots in the output buffer, wherein the data is read in one of sequential or non-sequential fashion from the input buffers and the data is written in the other of sequential or non-sequential fashion to the output buffer.