Patent ID: 6747974
Filing Date: 2004-06-08
Classification: H04L

Abstract:
A switching apparatus comprising:an input packet processing circuit which determines whether an input including packet includes an included packet and which performs, for an including packet which includes said included packet, demultiplexing processing of said included packet, header processing for a header of said included packet, and mapping processing for mapping a respective demultiplexed included packet associated with a switching including packet for switching processing, a switch for performing switching processing of said switching including packet and a switching including packet which does not include said included packet, and an output packet processing circuit which determines whether a switching including packet which is switched and outputted from said switch includes an included packet and which performs, for a switching including packet which includes said included packet, demultiplexing processing of said included packet and re-mapping processing for mapping said demultiplexed included packet in an including packet that is different from a switching including packet, wherein said input packet processing circuit comprising an included packet filling means wherein, at the time of said mapping processing, a number of included packets corresponding to a length of said switching including packets and a length of the associated included packets is mapped in one switching including packet as long as the header information thereof can be shared in common.