Patent ID: 9009540
Filing Date: 2015-04-14
Classification: G06F,G11C

Abstract:
1. A memory subsystem comprising: a memory device to store data and execute memory device commands to access and manage the data; a memory controller coupled to the memory device via a data bus and via a command bus, the memory controller to drive the command bus with memory device commands; and a buffer coupled to the command bus, the buffer including logic to detect that the at least a portion of the command bus is in a state where the memory controller has not driven the at least a portion with a valid executable memory device command, generate a signal pattern in response to detecting the state, the signal pattern generated based on the detected state, and inject the signal pattern on the command bus through a multiplexer to drive the at least a portion of the command bus with the signal pattern, the multiplexer having an output coupled to the command bus, a first input coupled to the memory controller and a second input coupled to the buffer, the multiplexer to select between memory device commands generated by the memory controller and signal patterns generated by the buffer.