Patent ID: 6620685
Filing Date: 2003-09-16
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor memory device, comprising the steps of:forming a gate electrode on a silicon substrate, the silicon substrate being divided into a cell area and a peripheral area, and the gate electrode having a gate and a gate spacer being covered with the gate; forming a first inter-layer dielectric layer (ILD1) on the silicon substrate having the gate electrode; forming a cell pad poly between the gate electrodes in the cell area; forming a direct contact plug (DC) on the cell pad poly in the cell area, and a first landing stud on the gate in the peripheral area; forming a bit line on the DC in the cell area and a second landing stud on the first landing stud, the bit line being covered with a bit line isolation layer; forming a second inter-layer dielectric layer (ILD2) on the ILD1 having the bit line to cover the bit line isolation layer; forming a silicon nitride layer on the ILD2; patterning the silicon nitride layer; etching out a portion of the ILD2 in the cell area using the patterned silicon nitride layer and the bit line isolation layer as etching blocking layers until the cell pad poly is exposed, and simultaneously etching out a portion of the ILD2 and a portion of the ILD1 in the peripheral area using the patterned silicon nitride layer; and simultaneously forming a plurality of buried contact plugs in the cell area and a first metal contact plug in the peripheral area by filling electrically conducting material to the etching portions of the ILD1 and ILD2.