Patent ID: 6108802
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A method for detecting faults in a memory-based FIFO having n words of memory, each of said n words of memory addressed by one of a plurality of addresses, a read address register for addressing one of said plurality of addresses at a time to be read from, a write address register for addressing one of said plurality of addresses at a time to be written to, and said write address register and said read address register having a bit width of M, where n and M are integers, said method comprising the steps of:executing a check reset step a plurality of times equal to each successive integer value of i, from i equal to 0 to (M-1), said check reset step including(a) a reset operation,(b) a sequence of a write operation of a first binary value followed by a read operation of said first binary value executed at successive ones of said plurality of addresses to an address equal to the value of 2.sup.i -1,(c) a reset operation,(d) a write operation of said first binary value executed at successive ones of said plurality of addresses to said address equal to the value of n-2,(e) a write operation of said first binary value, and(f) a write operation of said first binary value.