Patent ID: 6806579
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:providing a workpiece; disposing a first insulating layer over the workpiece; patterning the first insulating layer with a conductive line pattern; filling the conductive line pattern with conductive material to form at least one conductive line within the first insulating layer, the conductive line including a top surface and at least one sidewall with an outside surface; disposing a second insulating layer over the first insulating layer and the at least one conductive line; removing a portion of the second insulating layer to expose at least a portion of the top surface of the conductive line; removing a portion of the first insulating layer to expose at least a top portion of said outside surface of the at least one sidewall of the conductive line, wherein removing a portion of the second insulating layer and removing a portion of the first insulating layer forms a via opening wholly within the insulating layers; and filling the via opening with conductive material to form a via, wherein the via makes contact with at least a portion of the top surface of the conductive line and at least a top portion of said outside surface of the at least one sidewall of the conductive line.