Patent ID: 8571031
Filing Date: 2013-10-29
Classification: H04L

Abstract:
1. A packet switch, comprising: a multi-ported switch datapath; a plurality of ingress ports for receiving incoming data frames; ingress interconnection circuitry configured to selectively connect each of the ingress ports to the switch datapath; a plurality of egress ports for transmitting outgoing data frames; egress interconnection circuitry configured to selectively connect each of the egress ports to the switch datapath; control circuitry configured to control operation of the ingress and egress interconnection circuitry and the switch datapath to facilitate writing the incoming data frames to the switch datapath and reading the outgoing data frames from the switch datapath; and frame processing pipeline circuitry configured to determine forwarding behavior for and modifications to apply to each of the incoming frames with reference to incoming header data associated with the incoming data frames, and to generate outgoing header data for association with the outgoing data frames, the frame processing pipeline circuitry comprising: the programmable structure to generate a first operand in response to selection of the first profile, including: the programmable structure to perform with the first operand a first operation according to the operation field of the first profile, and the programmable structure to transform data in the data fields channel based on a result of the operation and according to the output field of the first profile.