Patent ID: 6310806
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns;a spare cell array including spare cells, said spare cells being to be replaced with defective memory cells in said memory cell array;a memory circuit for storing the addresses of said defective memory cells;an address buffer for outputting addresses for selecting said memory cells;a decoder for selecting a memory cell in said memory cell array according to the address signal outputted from said address buffer and which includes a select circuit for said memory cells and a control circuit for deactivating said select circuit according to the address signal for said defective memory cell;a spare decoder for selecting a spare cell in said spare array; anda switch circuit which is connected between said spare decoder and said address buffer and which enables only the defective address supplied from said address buffer to pass through according to the address of the defective memory cell outputted from said memory circuit when a power supply is turned on.