Patent ID: 6327198
Filing Date: 2001-12-04
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged correspondingly to rows of said plurality of memory cells and a plurality of bit lines arranged correspondingly to columns of said plurality of memory cells;a test mode setting circuit serially setting a plurality of test modes in accordance with an external signal; anda memory control circuit writing a checker pattern to said memory cell array in accordance with an output from said test mode setting circuit, said memory control circuit including:a row control circuit bringing even-numbered word lines/odd-numbered word lines of said plurality of word lines into a selection/non-selection state in accordance with corresponding one of said plurality of test modes; anda column control circuit setting a voltage of said plurality of bit lines for supplying it to said plurality of bit lines in accordance with said corresponding one of said plurality of test modes.