Patent ID: 7755925
Filing Date: 2010-07-13
Classification: G11C

Abstract:
1. A static random access memory, comprising: a row driver selecting a first word line or a second word line according to an address signal; a column driver providing data to a first bit line and a second bit line, wherein the data received by the first bit line is opposite to that of the second bit line; a first P-type transistor comprising a first electrode receiving a first voltage; a second P-type transistor comprising a first electrode receiving the first voltage; a first N-type transistor comprising a gate coupled to a gate of the first P-type transistor and a second electrode of the second P-type transistor, a first electrode coupled to a second electrode of the first P-type transistor, a second electrode coupled to a point, and a substrate receiving a second voltage; a second N-type transistor comprising a gate coupled to a gate of the second P-type transistor and the second electrode of the first P-type transistor, a first electrode coupled to the second electrode of the second P-type transistor, a second electrode coupled to the point, and a substrate receiving the second voltage; a third N-type transistor comprising a gate coupled to the first word line, a first electrode coupled to the first bit line, a second electrode coupled to the second electrode of the first P-type transistor, and a substrate receiving the second voltage; a fourth N-type transistor comprising a gate coupled to the first word line, a first electrode coupled to the second bit line, a second electrode coupled to the second electrode of the second P-type transistor, and a substrate receiving the second voltage; a third P-type transistor comprising a first electrode receiving the first voltage; a fourth P-type transistor comprising a first electrode receiving the first voltage; a fifth N-type transistor comprising a gate coupled to a gate of the third P-type transistor and a second electrode of the fourth P-type transistor, a first electrode coupled to a second electrode of the third P-type transistor, a second electrode coupled to the point, and a substrate receiving the second voltage; a sixth N-type transistor comprising a gate coupled to a gate of the fourth P-type transistor and the second electrode of the third P-type transistor, a first electrode coupled to the second electrode of the fourth P-type transistor, a second electrode coupled to the point, and a substrate receiving the second voltage; a seventh N-type transistor comprising a gate coupled to the second word line, a first electrode coupled to the first bit line, a second electrode coupled to the second electrode of the third P-type transistor, and a substrate receiving the second voltage; a eighth N-type transistor comprising a gate coupled to the second word line, a first electrode coupled to the second bit line, a second electrode coupled to the second electrode of the fourth P-type transistor, and a substrate receiving the second voltage; a control unit controlling a voltage of the point, wherein in a normal mode, the voltage of the point is equal to the second voltage, and in a stand-by mode, the voltage of the point exceeds the second voltage, wherein the control unit comprises: a ninth N-type transistor comprising a first electrode coupled to the point and a second electrode receiving the second voltage; a tenth N-type transistor comprising a gate coupled to the point, a first electrode coupled to the point, and a second electrode receiving the second voltage; and a controller coupled to a gate of the ninth N-type transistor, wherein in normal mode, the ninth N-type transistor is turned on by the controller such that the voltage of the point is equal to the second voltage, in stand-by mode, the ninth N-type transistor is turned off by the controller such that the voltage of the point exceeds the second voltage; and a processing module activating the controller according to the address signal.