Patent ID: 6654274
Filing Date: 2003-11-25
Classification: G11C

Abstract:
A ferroelectric memory device, comprising:a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells; a plurality of main bitlines disposed along a first direction corresponding to the sub-cell array blocks in column units; a plurality of sub-bitlines disposed along the first direction in a one-to-one correspondence to the sub-cell array blocks; a plurality of pairs of sub-bitline pull down signal application lines and sub-bitline enable switch signal application lines disposed along a second direction perpendicular to the first direction, each pair corresponding to the sub-cell array block for applying a sub-bitline enable switch signal and a sub-bitline pull down signal; and, a plurality of switching control blocks, each corresponding to the sub-cell array block for one of enabling the sub-bitlines selectively in response to the sub-bitline enable switch signal and pulling down the sub-bitlines in response to the sub-bitline pull down signal.