Patent ID: 6667913
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having memory cells; a phase adjustment circuit for delaying an external clock signal by a predetermined time to generate an adjusted clock signal; a phase comparator for comparing phases of said external clock signal and said adjusted clock signal, and for outputting a phase adjustment signal to adjust a delay time of said phase adjustment circuit in accordance with the comparison result; a data output circuit for outputting read data from said memory cell array to a data terminal in synchronization with said adjusted clock signal; and a data input circuit for receiving write data written to said memory cell array in synchronization with said adjusted clock signal, said write data also being supplied to said data terminal, wherein said phase adjustment circuit generates said adjusted clock signal leading said external clock signal in phase, while said phase comparator is detecting a coincidence in phase.