Patent ID: 7400034
Filing Date: 2008-07-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device formed on a semiconductor substrate comprising: a plurality of first memory arrays formed in a first region, each of the plurality of first memory arrays having a plurality of first word lines, a plurality of first bit lines across the plurality of first word lines, and a plurality of memory cells arranged at predetermined intersections of the plurality of first word lines and the plurality of first bit lines; a plurality of second memory arrays formed in a second region, each of the plurality of second memory arrays having a plurality of second word lines, a plurality of second bit lines across the plurality of second word lines, and a plurality of second memory cells arranged at predetermined intersections of the plurality of second word lines and the plurality of second bit lines; a plurality of data input/output pads formed in a third region; and a plurality of output circuits coupled to the plurality of data input/output pads and formed in the third region, wherein the first region, the third region, and the second region are sequentially arranged in a first direction, wherein the plurality of data input/output pads are arranged between a center axis of the first direction of the semiconductor substrate and the first region, wherein no data input/output pads are arranged between the center axis of the first direction of the semiconductor substrate and the second region, wherein each of the plurality of output circuits has a first transistor whose source is coupled to a first voltage line and whose drain is coupled to a corresponding one of the plurality of data input/output pads and a second transistor whose source is coupled to a second voltage line and whose drain is coupled to the corresponding one of the plurality of data input/output pads, wherein the first transistors are arranged between the plurality of data input/output pads and the first region, and wherein the second transistors are arranged between the plurality of data input/output pads and the second region.