Patent ID: 8334719
Filing Date: 2012-12-18
Classification: H01L,H03K

Abstract:
1. A semiconductor device comprising: first to ninth insulated gate transistors; a capacitor; a buffer circuit; a first wiring to which a first high power supply potential is supplied; a second wiring to which a second high power supply potential is supplied; a third wiring to which a first low power supply potential is supplied; and a fourth wiring to which a second low power supply potential is supplied, wherein a gate of the first insulated gate transistor is electrically connected to an input terminal, a first terminal of the first insulated gate transistor is electrically connected to the third wiring, and a second terminal of the first insulated gate transistor is electrically connected to a first terminal of the second insulated gate transistor, wherein a gate of the second insulated gate transistor is electrically connected to a first terminal of the seventh insulated gate transistor and a first terminal of the eighth insulated gate transistor; and a second terminal of the second insulated gate transistor is electrically connected to a first terminal of the third insulated gate transistor, a first terminal of the fourth insulated gate transistor, and a gate of the sixth insulated gate transistor, wherein a gate of the third insulated gate transistor is electrically connected to the first wiring, and a second terminal of the third insulated gate transistor is electrically connected to the second wiring, wherein a gate of the fourth insulated gate transistor is electrically connected to a first terminal of the fifth insulated gate transistor, a first terminal of the sixth insulated gate transistor, a first electrode of the capacitor, a gate of the eighth insulated gate transistor, and a gate of the ninth insulated gate transistor through the buffer circuit; and a second terminal of the fourth insulated gate transistor is electrically connected to the third wiring, wherein a gate of the fifth insulated gate transistor is electrically connected to the first wiring, and a second terminal of the fifth insulated gate transistor is electrically connected to the second wiring, wherein a second terminal of the sixth insulated gate transistor is electrically connected to the third wiring, wherein a gate of the seventh insulated gate transistor is electrically connected to the first wiring, and a second terminal of the seventh insulated gate transistor is electrically connected to the second wiring, wherein a second terminal of the eighth insulated gate transistor is electrically connected to the third wiring, wherein a first terminal of the ninth insulated gate transistor is electrically connected to an output terminal, and a second terminal of the ninth insulated gate transistor is electrically connected to the fourth wiring, wherein a second electrode of the capacitor is electrically connected to the third wiring, wherein the first to ninth insulated gate transistors each have a semiconductor layer formed using an oxide semiconductor, and wherein a potential of a node at which the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, and the gate of the eighth insulated gate transistor are electrically connected is supplied to the gate of the ninth insulated gate transistor through the buffer circuit.