Patent ID: 9129991
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit die, the method comprising: providing a semiconductor substrate; forming a first semiconducting layer of a first conductivity type on a first side of the semiconductor substrate; forming a vertical MOSFET by: forming a second semiconducting layer of a second conductivity type on a second side of the semiconductor substrate such that the first and second semiconducting layers are separated by the substrate; forming a gate trench in the second semiconducting layer, lining said gate trench with a dielectric layer and filling the lined gate trench with a gate electrode material; and forming a semiconducting region of a first conductivity type in the second semiconducting layer adjacent to said gate trench; forming a plurality of trenches through said second semiconducting layer, a first one of said trenches delimiting said vertical MOSFET; filling the first one of said trenches with an electrically insulating material; lining at least one further one of said trenches with an electrically insulating material and filling said lined further one of said trenches with a conductive material, thereby defining a vertical capacitor having the first semiconducting layer as a first plate and the conductive material as a second plate, wherein the region of the first conductivity type in the second semiconducting layer adjacent the gate trench is a source of the vertical MOSFET and the first semiconducting region is a drain of the vertical MOSFET; and electrically isolating the second plate of the vertical capacitor from the source.