Patent ID: 7240203
Filing Date: 2007-07-03
Classification: G06F,H04L

Abstract:
1. A computer implemented method comprising: calling a single macro instruction operation from a first processor, the single macro instruction operation representing a plurality of primitive security operations, the single macro instruction operation selected from a group of macro operations including a first key exchange macro operation, a second key exchange macro operation, a finish macro operation, and a server full handshake macro operation, wherein the first key exchange macro operation represents a plurality of primitive security operations including a decrypt operation, a group of modular arithmetic operations, and seventy-eight hash operations, the second key exchange operation macro represents a plurality of primitive security operations including one decrypt operation, a group of modular arithmetic operations, and twenty-two hash operations, the finish operation macro represents a plurality of primitive security operations including one decrypt operation, an encrypt operation, and twelve hash operations, and the server full handshake operation macro represents a plurality of primitive security operations including a decrypt operation, two encrypt operations, a set of modular arithmetic operations, and thirty-five hash operations; executing the plurality of primitive security operations at a second processor in response to receiving the single macro instruction operation from the first processor, the second processor having a plurality of execution units that each can perform the single macro instruction operation, wherein a single execution unit of said plurality of execution units performs the plurality of primitive security operations that correspond to the single macro instruction; generating a set of data from executing the plurality of primitive security operations at the second processor; and establishing a secure session between a first network element and a second network element using the set of data, wherein the first network element includes the first processor and the second processor.