Patent ID: 6292391
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A high-voltage isolating circuit for controlling the discharge of high-voltage in a memory array, comprising:a line connected to individual memory cells of said memory array, said line having both a high-voltage portion and a low-voltage portion, such that said line is capable of providing a high-voltage and a low-voltage to said memory cells; andan isolation transistor having a first source/drain terminal coupled with said high-voltage portion of said line and an opposing source/drain terminal coupled with said low-voltage portion of said line, wherein the substrate of said transistor is coupled with said high-voltage portion of said line, such that the voltage potential of said line can be maintained within a certain voltage range when said low-voltage portion of said line is at a first voltage potential, and wherein said high-voltage portion of said line can be discharged when said low-voltage portion of said line is at a second voltage potential, thereby preventing latch-up of said transistor.