Patent ID: 6856342
Filing Date: 2005-02-15
Classification: H04N

Abstract:
1. A high speed video photography system for photographing a projectile comprising: a video camera having a gate input and positioned to view passage of said projectile; a sensor providing a sensor signal on detection of the passage of said projectile; and a control circuit joined to said sensor and to said video camera gate input, said control circuit providing a control signal to said video camera gate input to activate said video camera a predetermined time after said sensor provides said sensor signal to said control circuit wherein said control circuit comprises: a sensor conditioning circuit joined to said sensor and providing a trigger in signal output; a first latch joined to said sensor conditioning circuit and providing a latched trigger in signal output; a first oscillator providing a first timing signal; a first AND gate joined to receive said latched trigger in signal from said first latch and said first timing signal from said first oscillator, said first AND gate providing a latched timing signal when said latched trigger in signal is asserted; a first counter joined to receive said latched timing signal from said first AND gate and providing a first counter output; a first delay generation logic circuit joined to receive said first counter output and preselected delay count, said first delay generation logic circuit providing an asserted first delay logic signal when said first counter output exceeds said preselected delay count; a second latch joined to said first delay generation logic circuit and receiving said asserted first delay logic signal and providing a latched first delay signal; a second AND gate joined to said first oscillator and receiving said first timing signal and said second latch and receiving said latched first delay signal, said second AND gate providing a second latched timing signal when said latched first delay signal is asserted; a second counter joined to receive said second latched timing signal from said second AND gate and providing a second counter output; a second delay generation logic circuit joined to receive said second counter output and second preselected delay count, said second delay generation logic circuit providing an asserted second delay logic signal when said second counter output exceeds said second preselected delay count; a third latch joined to said second delay generation logic circuit and receiving said asserted second delay logic signal and providing a latched second delay signal; an exclusive OR gate joined to said second latch and receiving said latched first delay signal and joined to said third latch and receiving said latched second delay signal, said exclusive OR gate providing an asserted trigger out signal when only one of latched first delay and latched second delay signals is asserted; a second oscillator providing a second timing signal; a third AND gate joined to said exclusive OR gate output to receive said exclusive OR trigger out signal and joined to said second oscillator to output said second timing signal when said exclusive OR trigger out signal is asserted; and a buffer joined to said third AND gate, receiving said second timing signal and providing a buffered control signal to said video camera gate input.