Patent ID: 6643726
Filing Date: 2003-11-04
Classification: G06F

Abstract:
An integrated computing system comprises:at least one processor formed on a substrate, wherein the processor operates at a processor rate; a global bus operably coupled to the at least one processor, wherein the global bus is formed on the substrate, and wherein the global bus supports transactions at a rate that is equal to or greater than the processor rate; device gateway operably coupled to the global bus, wherein the device gateway is formed on the substrate, wherein the device gateway provides an interface for at least one device to the global bus; and memory gateway operably coupled to the global bus, wherein the memory gateway is formed on the substrate, and wherein the memory gateway provides an interface between the global bus and memory and wherein the at least one processor, the memory gateway, and the device gateway each include a bus arbitrator to distributively arbitrate access to the global bus, and the bus arbitrators are synchronous to the processor rate.