Patent ID: 6249892
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A circuit structure for testing functions of a microprocessor having an instruction fetch unit, an instruction decoder, a main memory, and an instruction execution unit, comprising:a test control register for providing test instructions to the instruction decoder of the microprocessor;a first multiplexer for selecting either the test instructions from the test control register or instructions from the instruction fetch unit;a linear feedback shift register for providing test operand to the instruction execution unit of the microprocessor, the test operand being random data for operating the instruction execution unit multiple times per instruction from the test control register;a second multiplexer for selecting either the test operand from the linear feedback shift register or operand from the main memory;a multi-input feedback shift register for receiving results from the instruction execution unit of the microprocessor in a compressed form of data; anda controller for providing the test instruction to the test control register and the linear feedback shift register, and evaluating an output signature of the multi-input feedback shift register.