Patent ID: 7464320
Filing Date: 2008-12-09
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device which operates in synchronization with a clock signal comprising: a memory cell array in which a plurality of memory cells are arranged; a plurality of bit lines connected to the plurality of memory cells; an input circuit to which data is input; a code generation circuit which codes data and generates an error correction code; a read data bus to which the data that has been read out from the memory cells is supplied; a write data bus to which the data that has been coded by the code generation circuit is supplied; a plurality of read column selection lines which are designated by a column address and connects the read data bus to the bit lines; a plurality of write column selection lines which are designated by a column address and connects the write data bus to the bit lines; a syndrome generation circuit which generates a syndrome from the data that has been read out from the memory cells to the read data bus; and a correction circuit which decodes the syndrome that has been generated by the syndrome generation circuit and performs an error correction, wherein a read and write operations are performed in the same cycle of the clock signal, the read operation allowing the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines, and the write operation allowing the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines, and in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.