Patent ID: 8675739
Filing Date: 2014-03-18
Classification: G06F,H04N

Abstract:
1. A multi-core processor device comprising: a video decoder module comprising a plurality of function modules for repeatedly performing a video decoding operation; a memory to store an input bitstream and to load the function modules; and a multi-core processor comprising a plurality of cores, each core dedicated to performing one or more function modules from among the plurality of function modules, the cores including at least a first core and a second core, wherein, in response to the first core finishing one or more respective function modules dedicated thereto during a respective video decoding operation, the second core allocates part of a remaining task of one or more other function modules dedicated to the second core, to the first core, to reduce an idle time of the first core during the respective video decoding operation, and wherein, if the first core becomes idle, the first core transmits a signal to the second core indicating that the first core is idle.