Patent ID: 7009869
Filing Date: 2006-03-07
Classification: G11C,H01L

Abstract:
1. A dynamic memory cell, comprising: a storage capacitor; a first selection transistor; and a second selection transistor; wherein depending on a selection signal, a first electrode of the storage capacitor is connected to a first bit line via the first selection transistor and a second electrode of the storage capacitor is connected to a second bit line via the second selection transistor; wherein the first and second selection transistors are vertically disposed on opposite sides of the storage capacitor, respectively; wherein the storage capacitor comprises an inner region defining the first electrode, an outer region defining the second electrode and an insulation layer disposed between the regions to electrically isolate the regions from one another; wherein the first selection transistor is connected to the inner region and the second selection transistor is connected to the outer region; and wherein, when the selection transistors is activated, a charge of the inner region is applied to the first bit line and a charge of the outer region is applied to the second bit line.