Patent ID: 6787422
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method of forming a silicon-on-insulator device in the fabrication of integrated circuits comprising:providing a silicon layer overlying an oxide layer on a silicon semiconductor substrate; etching a first trench into said silicon layer wherein said first trench extends partially through said silicon layer and does not extend to underlying said oxide layer and wherein no implant is made underlying said first trench; filling said first trench with an insulating layer; etching second trenches into said silicon layer wherein said second trenches extend fully through said silicon layer to underlying said oxide layer and wherein said second trenches separate active areas of said semiconductor substrate and wherein said first trench lies within each of said active areas; filling said second trenches with an insulating layer; thereafter forming gate electrodes and associated source and drain regions in and on said silicon layer between said second trenches; depositing an interlevel dielectric layer underlying said gate electrodes; opening first contact openings through said interlevel dielectric layer to underlying said source and drain regions and opening a second contact opening through said interlevel dielectric layer wherein said second contact opening contacts both said first trench and one of said second trenches; and filling said first and second contact openings with a conducting layer to complete formation of said silicon-on-insulator device in said fabrication of integrated circuits.