Patent ID: 6314496
Filing Date: 2001-11-06
Classification: G06F

Abstract:
A processor system, comprising:a main memory configured to store data;an external system, coupled to the main memory and configured to generate a command relating to data stored in the main memory;a processor or a plurality of processors, each processor coupled to the external system and including:at least one memory cache;a system port configured to receive the command, the command having an address part identifying data stored in the at least one cache which is associated with the data stored in the main memory and a next coherence state part indicating a next state of the data in the cache; andan execution unit for executing the command to change the coherence state of the data in the cache according to the next coherence state part of the command and wherein the execution unit operates according to internal acknowledge rules, said rules controlling the extent to which each processor uses external acknowledgment to check coherency of internal and external cache memories.