Patent ID: 7193884
Filing Date: 2007-03-20
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells each having a MOS transistor and a capacitor, in which a gate of said MOS transistor is a selection terminal, one of source and drain of said MOS transistor is an I/O terminal, and the other of the source and drain is connected to a storage node of said capacitor; a plurality of word lines respectively connected to said selection terminals of said plurality of memory cells; complementary bit lines respectively connected to said I/O terminals of said plurality of memory cells; sense amplifiers connected to said complementary bit lines and each amplifying a voltage difference between corresponding one of said complementary bit lines to latch the amplified voltage; and means which, after one of said plurality of word lines is activated and at the time when said sense amplifier is activated, one of said complementary bit lines is amplified to a first voltage, and the other complementary bit line is amplified to a second voltage lower than said first voltage, reduces the voltage of the complementary bit line amplified to said first voltage to a third voltage lower than said first voltage at a first time and then deactivates said one of word lines.