Patent ID: 6529031
Filing Date: 2003-03-04
Classification: G11C,H01L

Abstract:
An integrated circuit configuration for testing transistors, comprising:a first multiplicity of pads, a first further pad, a second further pad, and a third further pad; a multiplicity of transistors to be tested, said transistors each having a control connection and a controlled path between a first connection and a second connection, and said transistors being arranged in a first row and in a second row; each of said transistors in said first row being arranged between two respective pads of said first multiplicity of pads, and said connections of said controlled path through said transistors being connected to said two pads, and said control connections of said transistors in said first row being connected to said first further pad; said first connections of said controlled path through said transistors in said second row being each connected to a respective one of said pads, the second connections of said controlled path through said transistors in said second row being jointly connected to said second further pad, and said control connections of said transistors in said second row being jointly connected to said third further pad.