Patent ID: 6830966
Filing Date: 2004-12-14
Classification: H01L,Y10S

Abstract:
A method of forming a device for dissipating electrostatic discharge in an integrated circuit comprising:providing a semiconductor substrate; providing a p-region in said semiconductor substrate; forming a source n-well and drain n-well in said p-region wherein said p-region, said source n-well, and said drain n-well have a peak in concentration at a depth of between 0.5 and 1.5 &mgr;m; providing a gate oxide overlying said p-region in the space between said source n-well and said drain n-well; forming an n+ source region and an n+ drain region within a top portion of said source n-well and said drain n-well, respectively; forming a lightly doped source region and a lightly doped drain region within said source n-well and said drain n-well, respectively and adjacent to said source n-well and said drain n-well, respectively; forming a gate electrode overlying said gate oxide and not overlapping said source n-well and said drain n-well; forming conductive contacts to said n+ source region and said n+ drain region; and electrically connecting said gate electrode and said conductive contact to said n+ source thereby completing fabrication of said device for dissipating electrostatic discharge.