Patent ID: 6671075
Filing Date: 2003-12-30
Classification: H03F

Abstract:
An offset voltage cancellation circuit, which removes a difference between direct-current voltage element included in first and second differential input signals, and generates a differential signal including first and second output signals, comprising:a first peak detector which includes a first capacitor for storing the peak level of said first input signal, which outputs a voltage corresponding to a charge stored in said first capacitor as a first peak voltage, and which discharges said charge stored in said first capacitor in response to a reset signal; a second peak detector which includes a second capacitor for storing the peak level of said second input signal, which outputs a voltage corresponding to a charge stored in said second capacitor as a second peak voltage, and which discharges said charge stored in said second capacitor in response to said reset signal; a first adder which adds said first input signal to said second peak voltage to generate said first output signal; a second adder which adds said second input signal to said first peak voltage to generate said second output signal; and a peak level reset unit which outputs said reset signal, the reset signal corresponding to a potential difference between said first and second output signals.