Patent ID: 6311284
Filing Date: 2001-10-30
Classification: G06F

Abstract:
A method for coordinating access to at least one data register between a peripheral device and a host system, the at least one data register being within a statistics module having an independent clock, the method including the steps of:A. asserting a first valid signal from the peripheral device, when a taken signal from said statistics module is not asserted, to indicate that the peripheral device has new statistical data for updating said at least one data register within said statistics module, said first valid signal being synchronized to a peripheral device clock within said peripheral device;B. asserting a second valid signal synchronized to said independent clock at the statistics module from said first valid signal being asserted in said step A;C. accepting said new statistical data by said statistics module from said peripheral device when said second valid signal has been asserted in said step B;D. asserting said taken signal at said statistics module after said new statistical data has been substantially received by said statistics module from said peripheral device, said taken signal being synchronized to said independent clock within said statistic module; andE. deasserting said first valid signal synchronized to said peripheral device clock at said peripheral device after said taken signal is asserted in said step D, to indicate that said peripheral device is free to return to a foreground task.