Patent ID: 8866119
Filing Date: 2014-10-21
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a selection element layer; a nanomaterial aggregate layer stacked on the selection element layer, the nanomaterial aggregate layer having a plurality of micro conductive bodies aggregated with an interposed gap, the plurality of micro conductive bodies being disposed throughout a whole of the nanomaterial aggregate layer; and a fine particle having at least a surface made of silicon oxynitride, the selection element layer and the nanomaterial aggregate layer being a portion of a pillar extending in a thickness direction, the fine particle being dispersed between the plurality of micro conductive bodies of the nanomaterial aggregate layer, the fine particle being dispersed within an outer circumferential portion of the pillar, and the fine particle not being dispersed within a central portion of the pillar inside of the outer circumferential portion of the pillar, and the nanomaterial aggregate layer extending throughout the outer circumferential portion of the pillar and the central portion of the pillar.