Patent ID: 7532250
Filing Date: 2009-05-12
Classification: H03L

Abstract:
1. A clock generation circuit comprising: a first ADC for converting a video signal on which a sync signal is superimposed or a sync signal, which is inputted through a first video signal input terminal, into a digital signal, and outputting the digital signal; a second ADC for converting a video signal inputted through a second video signal input terminal into a digital signal, and outputting the digital signal; a horizontal sync signal separation circuit for receiving the video signal or sync signal that is digitized by the first ADC, and separating the horizontal sync signal from the signal; a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the first ADC; a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information; a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information; a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; a multiple phase output PLL for multiplying the output of the DAC to supply a clock to the first ADC, and simultaneously, outputting an intermediate phase among the multiple phases; and a clock selection circuit for selecting one of the multiple phase clocks outputted from the multiple phase output PLL, and supplying the second ADC with the selected clock.