Patent ID: 8738996
Filing Date: 2014-05-27
Classification: G06F,G11C

Abstract:
1. A system comprising: a flash memory; an encoder configured to (i) receive data, and (ii) encode the data based on an error correction code; a first interface configured to (i) write the encoded data to a plurality of memory cells in the flash memory, and (ii) read the encoded data back from the plurality of memory cells; a decoder configured to (i) decode the encoded data read back from the plurality of memory cells, and (ii) based on the decoded data, determine a number of decoding errors for the plurality of memory cells; and a controller configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the plurality of memory cells, wherein the first threshold is less than a maximum number of errors correctable by the error correction code for the plurality of memory cells.