Patent ID: 6345372
Filing Date: 2002-02-05
Classification: G11C

Abstract:
A method for checking contact connections of a writable and readable integrated electronic circuit connected to an address bus and a data bus, the method which comprises:A) writing, in at least a first sequence of write steps, address bit test patterns step-by-step to an address bus, and writing data bit test patterns on a data bus into a writable and readable integrated electronic circuit; B) writing, in at least a first sequence of read steps, the address bit test patterns again step-by-step to the address bus, and reading associated data bit patterns on the data bus from the writable and readable integrated electronic circuit; C) comparing, in at least a first sequence of test steps, the associated data bit patterns with the data bit test patterns and, in the event of discrepancies, localizing a faulty line on one of the address bus and the data bus; and D) selecting the address bit test patterns and the data bit test patterns such that, i) in a respective first step in one of the first sequence of write steps and read steps, bits in the address bit test pattern have a first, matching binary value, ii) in the first step of the first sequence of write steps, bits in the data bit test pattern have a second, matching binary value, and iii) for each following step in one of a respective sequence of write steps and read steps, starting with one of a lowest-value bit and a highest-value bit in one of the address bit test pattern and the data bit test pattern, a respective adjacent bit is assigned a respective complementary binary value with respect to a preceding step, until, iv) in a final step in one of the respective sequence of write steps and read steps, all bits in one of the address bit test pattern and the data bit test pattern, have a binary value complementary to the first, matching binary value and the second, matching binary value, respectively.