Patent ID: 6477087
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory transistor having a charge storage portion and having a threshold voltage affected by an amount of charge stored in the charge storage portion; a bit line connected to said memory transistor at one terminal; a source line connected to said memory transistor at another terminal; a word line connected to said memory transistor at a gate electrode; a row decoder configured to supply a write voltage and a verify voltage to the word line; a data circuit, including a flip-flop, configured to store a write control data by the flip-flop, verify a voltage level of said bit line by one of the invertors, and then latch a verified data by the flip-flop in order to use the verified data as a modified write control data; a transfer gate connected between said bit line and said data circuit and configured to connect said bit line and said data circuit when verifying the voltage level of the bit line; a precharge circuit connected to said bit line and configured to charge up the bit line to a predetermined potential level, the predetermined potential level being decreased if the threshold voltage of the memory transistor is lower than a voltage level of the word line; and a voltage regulator connected to said bit line and configured to change the voltage level of the bit line according to the write control data stored before verifying.