Patent ID: 9054821
Filing Date: 2015-06-09
Classification: H03L,H04L

Abstract:
1. A frequency locking apparatus, adapted to a transmission interface without a quartz oscillator, and comprising: a phase-locked loop, receiving a radio frequency signal, and locking a phase and a frequency of the radio frequency signal to generate a recovery clock signal and a received data; a local clock generator, generating a local clock signal; a data buffer unit, coupled to the phase-locked loop and the local clock generator, writing the received data into an elastic buffer in the data buffer unit according to a frequency of the recovery clock signal, and reading the received data from the elastic buffer according to a frequency of the local clock signal; a control unit, coupled to the data buffer unit and the local clock generator, wherein the control unit reads a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to a relationship between the write-in address and the read-out address, wherein the control unit comprises a calibration mode, wherein when the control unit is in the calibration mode, the control unit a. determines whether the radio frequency signal is received, and activates accessing of the elastic buffer when the radio frequency signal is received; b. determines whether the elastic buffer is full or empty when a first timing value is smaller than a value X, and increases a digital value in the control signal when the elastic buffer is full, and decreases the digital value in the control signal when the elastic buffer is empty; c. determines whether a multiplication of a second timing value and a period of the recovery clock signal reaches a spread spectrum clock period, and resets the first timing value and repeats the step b when the multiplication of the second timing value and the period of the recovery clock signal does not reach the spread spectrum clock period; and d. stores the digital value and resets the second timing value to zero when the multiplication of the second timing value and the period of the recovery clock signal reaches the spread spectrum clock period.