Patent ID: 7394705
Filing Date: 2008-07-01
Classification: G11C

Abstract:
1. A memory device comprising: a first voltage source generating a first voltage; a second voltage source external to the memory device and generating a second voltage that is different from the first voltage; a first switching circuit internal to the memory device, said first switching circuit having a first input, which is operatively coupled to the first voltage source and having a second input which is coupled to the second voltage source, said first switching circuit having an output and being configured to route at least one of the first and second voltages to a voltage divider, coupled to said output of said first switching circuit, in response to a first control signal; a voltage divider circuit, internal to the memory device and which is coupled to an output of the first switching circuit, said voltage divider dividing a voltage selected by the first switching circuit into a plurality of voltage levels; a second switching circuit, internal to the memory device, which selects one of the multiple voltage levels outputted from the divider; and a decoder, which generates a second control signal which controls the second switching circuit; wherein the first switching circuit is controlled by a code signal of a mode register set (MRS) or an extended mode register set (EMRS).