Patent ID: 6408345
Filing Date: 2002-06-18
Classification: G06F

Abstract:
A data processing system comprising:a central processing unit executing program instructions to manipulate data; at least one level one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit; a level two unified cache connected to said level one instruction cache and said level one data cache for supply of instructions to said level one instruction cache and data to said level one data cache; a directly addressable memory; a direct memory access unit connected to said directly addressable memory and adapted for connection to an external memory; and a superscalar memory transfer controller connected to said level one instruction cache, said level one data cache, said level two unified cache, said directly addressable memory and said direct memory access unit, said superscalar memory transfer controller operable in memory cycles and capable of scheduling plural non-interfering memory movements to and from said level two unified cache and said directly addressable memory each memory cycle in accordance with a predetermined priority of operation.