Patent ID: 7437633
Filing Date: 2008-10-14
Classification: G01R

Abstract:
1. A system for testing duty cycle at an input/output node of an integrated circuit, comprising: a first digital clock module having a first clock signal and a second clock signal as respective outputs, the second clock signal having a phase shifted approximately 180° from a phase of the first clock signal; an output buffer having a timing signal as an output, the timing signal responsive to the first clock signal and the second clock signal; a second digital clock module having a sampling signal as an output and a phase adjust signal as an input; a register having a data input to receive the timing signal, a clock input to receive the sampling signal, and a sampled test signal as an output; a control logic having the sampled test signal as an input and a phase adjust signal as an output, the phase adjust signal configured to shift the phase of the sampling signal, the control logic configured to provide duty cycle information, the duty cycle information being associated with the sampled test signal and a phase shift which the sampling signal undergoes responsive to the phase adjust signal; the sampling signal being phase shifted in opposite directions responsive to the phase adjust signal to determine respective level changes in the sampled test signal, the respective level changes being associated with respective phase indicators, the phase indicators being the duty cycle information; wherein the duty cycle of the test signal is determinable responsive to the duty cycle information; a drive adjust circuit having a duty cycle adjust enable signal and the duty cycle information as inputs, and a drive adjust signal as an output; the drive adjust circuit configured to provide the drive adjust signal responsive to the duty cycle adjust enable signal and the duty cycle information, wherein the drive adjust signal provides information associated with at least one set of drive transistors selected from a group consisting of n-type drive transistors and p-type drive transistors for obtaining a duty cycle indicated by the duty cycle adjust enable signal; a reference voltage circuit having the drive adjust signal as an input; the reference voltage circuit configured to provide a first reference voltage as an output using one or more of either the n-type drive transistors or the p-type drive transistors responsive to the drive adjust signal; and the first reference voltage being provided to either an n-type well or a p-type well of an output buffer to provide a first body bias voltage of the output buffer.