Patent ID: 6587804
Filing Date: 2003-07-01
Classification: G11C

Abstract:
A method of calibrating a data path of a digital device comprising:a) capturing a first predetermined number of bits of a repeating calibration pattern received on said data path during a first capture period corresponding to a first predetermined number of ticks of a clock signal; b) predicting a second predetermined number of bits of said repeating calibration pattern to be received on said data path from said first predetermined number of bits; c) capturing a third predetermined number of bits of said repeating calibration pattern during a second capture period corresponding to said first predetermined number of ticks of said clock signal; d) comparing said predicted second predetermined number of bits with said captured third predetermined number of bits during a compare period corresponding to a second number of ticks of said clock signal; e) using the results of said comparison to adjust the relative timing of said received calibration pattern and said clock signal; and f) repeating steps â€œaâ€  through â€œeâ€  a plurality of times wherein for at least a first number of said times said second number of ticks equals a first number of ticks and for at least a second number of times said second number of ticks does not equal said first number of ticks.