Patent ID: 8924614
Filing Date: 2014-12-30
Classification: G06F,Y02D

Abstract:
1. A host controller apparatus comprising: an event controller configured to output occurred event information to a system memory; and an interruption controller configured to output an interrupt signal to a processor executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory; wherein the event controller is configured to output the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the processor, wherein the interruption controller comprises an interrupt signal output timer configured to indicate a timing to output the interrupt signal, and the event controller comprises an event buffer configured to accumulate the occurred event information, and to output event information accumulated in the event buffer to the system memory in synchronization with the timing to output the interrupt signal from the interrupt signal output timer, wherein the event controller is configured to output the event information that are accumulated to the system memory when a predetermined number of pieces of event information are accumulated in the event buffer.