Patent ID: 6108770
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A method of scheduling program instructions for execution in a computer processor, comprising:fetching instructions from an instruction memory and holding them, certain fetched instructions being load instructions (loads) and causing load operations, and other fetched instructions being store instructions (stores) and causing store operations;executing the fetched instructions out of program order;detecting a load/store order violation wherein a load executes prior to a store on whose data the load depends, and upon such detection:erasing the effect of and re-executing the load and its dependent instructions, andassociating the load with the store on whose data the load depends by adding the store to an existing store set associated with the load, and if no such store set exists,creating a store set for the load, andadding the store to the store set; andon a subsequent issuance of the load, delaying its execution until any store associated with a previously-fetched instruction which has been associated with the load, has executed.