Patent ID: 6789137
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A semiconductor memory device for operating selectively in a normal operation mode for periodically performing writing and reading of data, and in a slow operation mode for periodically performing writing and reading of said data at a lower speed than that in said normal operation mode, comprising:a plurality of memory cells for storing the data; a signal select circuit for selecting either a first signal received from an I/O terminal used only in said normal operation mode or a second signal received from an I/O terminal used in both of said slow and normal operation modes; and a peripheral circuit for performing the writing and/or reading of said data into and/or from said plurality of memory cells in said slow operation mode by using said second signal when said signal select circuit selects said second signal, and performing the writing and/or reading of said data into and/or from said plurality of memory cells in said normal operation mode by using said first signal when said signal select circuit selects said first signal, wherein said signal select circuit selects said first signal in said normal operation mode, and selects said second signal in said slow operation mode.