Patent ID: 7518394
Filing Date: 2009-04-14
Classification: H03K

Abstract:
1. In an integrated circuit device, a process monitor vehicle, comprising: a plurality of shift register bits coupled in series; a logic gate coupled to receive an enable signal and an output signal from a last shift register bit of the plurality of shift register bits and coupled to provide an input signal to a first shift register bit of the plurality of shift register bits, wherein each shift register bit includes, a memory cell block adapted to latch the input signal; a first inverter coupled to receive the latched input signal from the memory cell block and adapted to provide the latched input signal as an output signal in response to a programmable drive current; and a write driver coupled to a power supply reference of the first inverter, wherein the write driver is adapted to conduct a programmable magnitude of current from the power supply reference of the first inverter to set the programmable drive current, wherein the memory cell block comprises: