Patent ID: 7529114
Filing Date: 2009-05-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a bit line which is provided above the semiconductor substrate and runs in a first direction; a source line which is provided above the semiconductor substrate and runs in the first direction; an active area which is provided in the semiconductor substrate and extends in the first direction; a first selection transistor and a second selection transistor which are formed on the active area and share a source region electrically connected to the source line; a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line; and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line, wherein the source line includes a first interconnection portion and a second interconnection portion which run in the first direction and are adjacent to the bit line in a second direction perpendicular to the first direction, and a third interconnection portion which connects the first interconnection portion to the second interconnection portion and is electrically connected to the source region.