Patent ID: 6621755
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A system comprising:a processor; and at least one synchronous random access memory (SRAM) device comprising: a plurality of memory array blocks each configured to store data; a write driver located locally with respect to the plurality of memory array blocks and configured to receive data on an input line and to drive the data into one or more of the plurality of memory array blocks on one or more data lines coupled between the write driver and the plurality of memory array blocks; and at least one logical device configured to provide a block select signal to each of the plurality of memory array blocks such that each of the plurality of memory array blocks may receive data from the write driver simultaneously; wherein the at least one logical device is configured to receive a testmode signal, wherein enabling the testmode signal provides write access to each of the plurality of memory array blocks simultaneously; and wherein the testmode signal is enabled during burn-in testing of the SRAM device.