Patent ID: 6356488
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A bias level generation circuit in a flash memory device, comprising:a first inverter for inverting an enable signal; a first switching element switched depending on an output signal from said first inverter; a charge pump for generating a pump-out voltage needed to generate a bias level depending on a power supply applied via said first switching element and in response to said enable signal; a bias switch circuit for preventing oscillation of said pump-out voltage in order to generate a bias level for use in a programming or a programming verification of a cell depending on a program signal, wherein an input of said bias switch circuit is connected to an output of said charge pump; and a regulator for making a voltage generated in said bias switch to have a bias level suitable for programming or programming verification of the cell, by setting a specific path current depending on said program signal, wherein an input of said regulator is connected to an output of said bias switch circuit.