Patent ID: 6040603
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A transistor formed in a semiconductor substrate having improved FSD protection comprising:a gate structure formed atop of said semiconductor substrate, said gate structure comprised of a conducting layer formed atop a thin gate oxide layer;sidewall spacers formed on the sidewalls of said gate structure;lightly doped source and drain regions formed in said semiconductor substrate and substantially underneath said sidewall spacers;a source region formed in said semiconductor substrate and adjacent to one of said sidewall spacers;a drain region formed in said semiconductor substrate and adjacent to a second one of said sidewall spacers:a first ESD implant formed underneath said source region and said drain region, said first ESD implant having the same impurity type as said source region and said drain region;wherein said source region, said drain region, and said lightly doped drain regions are within said first ESD implant; anda second ESD implant formed underneath said first ESD implant, said second ESD implant having an impurity type opposite to that of said first ESD implant, said second ESD implant also being spaced apart vertically from said first ESD implant.