Patent ID: 6486508
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A non-volatile semiconductor memory device comprising:a first conductivity type of a semiconductor substrate having separately formed active areas and field areas formed with field insulating layers to isolate the active areas; a first gate insulating layer formed at respective substrate of the active areas; floating gates arranged at a predetermined interval on the first gate insulating layer; oxide layers respectively formed at the upper surface of the floating gates; a second gate insulating layer to be used as a tunneling insulating layer formed at lateral surfaces of the floating gates; control gates, each of which overlaps a pair of floating gates out of the floating gates; a second conductivity type of source areas formed at the active area, a part of which is overlapped with the same part of the floating gates, and at a part of the neighboring active area; and a second conductivity type of buried diffusion areas formed at the substrate of a part of the field area for preventing neighboring source areas of the same source line, out of source areas, from being isolated by the field insulating layer, and for making them electrically connected.