Patent ID: 6291843
Filing Date: 2001-09-18
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device comprising more than one unit assembly wherein first and second main source lines are disposed respectively on both sides of a main bit line and first and second sub-source lines connected respectively to said first and second main source lines and first and second sub-bit lines connected to said main bit line are provided and wherein two groups of memory cells consisting one group having two or more memory cells connected in parallel between said first sub-source line and said first sub-bit line and the other group having two or more memory cells connected in parallel between said second sub-source line and said second sub-bit line are disposed in a manner that an isolated area is located between these two groups of memory cells,whereby each of said first and second bit lines is elongated along the direction of the bit line and in the reverse direction and is connected to said main bit line through first and second bit select transistors each being independently controllable.