Patent ID: 8198144
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A method of forming a pillar structure for a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric layer overlying the surface region of the semiconductor substrate; forming a first wiring structure overlying the first dielectric layer, the first wiring structure comprising at least a first conductor material; forming a second dielectric material overlying the first wiring structure; forming a planarized second dielectric layer surface, exposing a first wiring structure surface; forming a bottom metallic barrier material overlying the second dielectric layer surface including the first wiring structure surface, the bottom metallic barrier forming a metal-to-metal contact with the first wiring structure; depositing a contact material overlying the bottom metal barrier material; depositing a switching material overlying the contact material; depositing a conductive material overlying the switching material; depositing a top barrier material overlying the conductive material; performing a patterning and etching process to form a plurality of pillar structures from at least the bottom metallic barrier material, the contact material, the switching material, the conductive material, and the top barrier material; depositing a third dielectric material overlying at least the plurality of pillar structures, the third dielectric material having a non-planer surface region; planarizing the third dielectric material, exposing a surface region of the pillar structure, the surface region of the pillar structure including a surface region of the top barrier material, and forming a top wiring structure overlying at least the exposed surface region of the pillar structure, the top wiring structure comprising at least a second conductor material.