Patent ID: 9076546
Filing Date: 2015-07-07
Classification: G11C

Abstract:
1. A nonvolatile semiconductor storage device, comprising: a nonvolatile memory cell array, having a plurality of memory cells connected to global bit lines; a page buffer circuit, having a first latch circuit temporarily storing data read from and written to the nonvolatile memory cell array by a predetermined page unit; a second latch circuit, temporarily storing data input from and output to an external circuit; and a control circuit, controlling data reading and writing of the nonvolatile memory cell array, wherein the nonvolatile memory cell array is divided into a first cell array and a second cell array, the page buffer circuit is arranged between the first cell array and the second cell array, and the second latch circuit is arranged by the outside edge section of the first cell array; the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array; the control circuit controls data writing to the first cell array or the second cell array by transmitting the writing data to the page buffer circuit from the second latch circuit via the global bit line of the first cell array, after the writing data from the external circuit is latched in the second latch circuit, for data writing; and the control circuit controls outputting the data read from the first cell array or the second cell array to the external circuit by transmitting data to the second latch circuit from the page buffer circuit via the global bit line of the first cell array, for data reading.