Patent ID: 6208547
Filing Date: 2001-03-27
Classification: G11C,H01L

Abstract:
A memory circuit/logic circuit integrated device comprising:a logic circuit chip formed on a first major surface of a first semiconductor substrate, said logic circuit chip including a plurality of first input/output pads for electrically interfacing with the exterior of said logic circuit chip;a memory chip separated from a second semiconductor substrate having a plurality of memory circuits separably spaced on a second major surface, said memory chip includingat least one said memory circuit,an insulator layer provided on the surface of said memory chip, andan interface wiring layer provided under said insulator layer and capable of being provided in common for a plurality of said memory circuits, said interface wiring layer having a plurality of second input/output pads each provided on a position corresponding to an opening part of said insulator layer for electrically interfacing with the exterior of said memory chip; anda plurality of connect members connecting said plurality of first input/output pads to corresponding said second input/output pads with said first major surface of said logic circuit chip faced to said second major surface of said memory chip.