Patent ID: 6040218
Filing Date: 2000-03-21
Classification: G11C,H01L

Abstract:
A method of forming an array of non-volatile random access memory (NVRAM) cells comprising the steps of:a) etching a plurality of trenches in a semiconductor layer;b) forming a source gate line of a first conductive material in said trenches;c) forming sidewalls of said first conductive material above said source gate line along the sidewalls of said trenches;d) forming a plate of a second conductive material between said first conductive material sidewalls;e) plugging said trenches above said plate with said first conductive material;f) forming perpendicular to said trenches a plurality of second trenches, said second trenches dividing said trenches such that semiconductor pillars are formed, said first conductive material sidewalls are divided into floating gates adjacent said semiconductor pillars and said first conductive material plugging said trenches is divided into word line plugs adjacent said semiconductor pillars.