Patent ID: 6813657
Filing Date: 2004-11-02
Classification: G10L

Abstract:
An apparatus for processing a bit stream that is coded in a plurality of frames, the apparatus comprising:a circular buffer for storing a transmitted bit stream without separately storing header and data in each of the frames included in the transmitted bit stream; a first register for storing a first value indicating a first read point of the bit stream stored in the circular buffer; a first backup register for backing up the first value stored in the first register; a second register for storing a second value indicating the number of bits to be read from the circular buffer; a third register for storing a third value indicative of the number of bits to be ignored from the first read point; a second backup register for backing up the third value stored in the third register; an adder for adding the second value stored in the second register and the third value stored in the third register; and a controller responsive to the adder to determine the number of bits to be shifted to read desired data from the circular buffer without any restriction on the location of the desired data in the frames.