Patent ID: 6153916
Filing Date: 2000-11-28
Classification: H01L

Abstract:
An MOS transistor with high output voltage endurance comprising:a semiconductor substrate provided with a weak doping of a first conductivity type;drain and source conduction areas formed in a surface of the substrate, the conduction areas being provided with a heavy to excessive doping and being of a second conductivity type opposite the first conductivity type;a gate oxide layer applied on the surface of the substrate under a gate and between the conduction areas, the gate oxide layer having a source-side edge adjacent the source conduction area and a drain-side edge spaced from the drain conduction area;a doping area of the second conductivity type extending into the surface of the substrate from the drain conduction area to below the gate and spaced from the source conduction area, a surface concentration of the doping area in an area adjacent the drain conduction area being higher than in a region below the gate; andan intrinsic zone arranged in the surface of the substrate within the doping area below the drain-side edge of the gate oxide layer,the doping area comprising a first partial area adjacent the drain conduction area, a size of the first partial area along a lateral direction between the conduction areas being considerably larger than a penetrating depth of outdiffusion of the first partial area into the substrate, and at least one second partial area arranged between the first partial area and the source conduction area, a size of the at least second partial area along the lateral direction and a distance of the at least one partial area to the first partial area being smaller than a penetrating depth of outdiffusion of the at least one second partial area into the substrate,the first and second partial areas being ion implanted and merging into each other on the surface of the substrate by outdiffusion to thus form the doping area having a doping concentration gradient.