Patent ID: 8762647
Filing Date: 2014-06-24
Classification: G06F,Y02D

Abstract:
1. A multicore processor system comprising: a memory including a memory region; and a multicore processor including: the memory region permits: the multicore processor comprises a kernel unit that makes transition of the memory region between the first state and the second state and between the second state and the third state, the kernel unit writes back the first cache corresponding to the first state to the second cache when the kernel unit makes a transition of the memory region from the first state to the second state, and writes back the second cache corresponding to the second state to the memory region when the kernel unit makes a transition of the memory region from the second state to the third state, and the address translation unit maps a plurality of virtual addresses to a physical address of the memory region for each state of the memory region, and each one of the processor cores uses a virtual address among the virtual addresses according to the state of the memory region.