Patent ID: 9043662
Filing Date: 2015-05-26
Classification: G01R,G11C

Abstract:
1. A method for providing multi-mode high speed on-chip test data generation and on-chip data comparison to provide self-diagnostics testing of multiple data bits of a double data rate (DDR) physical interface, comprising the operations of: selecting a first mode of the multi-mode to enable an on-chip bypass connection using a self-check loopback test logic, generating a set of on-chip test data values using a first linear feedback shift register (LSFR), wherein the set of test data values comprise at least two bits of data; generating a set of on-chip expected data values, being a family of signal data, using a second LSFR, wherein the set of expected data values correspond to the set of test data values; providing the set of test data values to an output data path of the chip; looping back the set of test data values from the output data path of the chip to an input data path of the chip via the on-chip bypass connection; receiving the set of test data values from the output data path and providing them to an on-chip loopback error check element via read capture flip-flops that provides an expected value output and an expected value output; comparing the received set of test values with the set of expected data values; determining a state of operation of the DDR physical interface by comparing the set of test data values and the set of expected data values, where if the set of test data values and the set of expected values match, the state is operational, and if the set of test data values and the set of expected values do not match, the state is in error and the check element determines where the differences between the set of test data values and the set of expected values occur by providing an expected value on an expected value output line and an actual value on an actual value line thereby determining one or more logic errors in one or more of output logic, input logic, and read capture element; and, providing an output in response to the state detected, wherein the method further provides for the testing of entire families of signals simultaneously.