Patent ID: 6018814
Filing Date: 2000-01-25
Classification: G01R

Abstract:
A single instruction-stream multiple data-stream (SIMD) semiconductor tester digital system for testing a device under test (DUT) having a plurality of contact points for accessing circuitry inside the DUT, comprising:a global instruction broadcast subsystem regulated by a system clock signal oscillating at a system clock rate, said global instruction broadcast subsystem including:a system controller for providing a first sequence of instructions, anda global instruction broadcast network, coupled to said system controller, for broadcasting said first sequence of instructions at said system clock rate; anda timing generator module coupled to said global instruction broadcast subsystem for producing event sequences for the plurality of contact points of the DUT, wherein said timing generator module is associated with a respective contact point of the DUT, said timing generator module being implemented on a single chip and including:a local clock generating circuit, responsive to said system clock signal, for generating a local clock signal for regulating said timing generator module, wherein said local clock signal oscillates at a rate higher than said system clock rate,a cache element for storing said first sequence of instructions provided by said global instruction broadcast subsystem, anda cache controller responsive to said global instruction broadcast subsystem for providing addresses and control signals to said cache element for the purposes of storing selected instructions in said cache element and for retrieving selected instruction sequences from said cache element for local re-broadcast within said timing generator module.