Patent ID: 8461643
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A flash memory cell stack comprising; a semiconductor substrate; a control electrode provided in a vertical pillar shape on a surface of the semiconductor substrate; an insulating film provided between the control electrode and the semiconductor substrate; a gate stack provided on a side surface of the control electrode; a plurality of first insulating films provided as layers on a side surface of the gate stack; a plurality of second doping semiconductor areas provided as layers on the side surface of the gate stack; and a first doping semiconductor area provided on side surfaces of the first insulating films and the second doping semiconductor areas, wherein the first insulating films and the second doping semiconductor areas are alternately provided on the side surface of the gate stack, and wherein the first doping semiconductor area and the second doping semiconductor area are doped with opposite types of impurities.