Patent ID: 8566759
Filing Date: 2013-10-22
Classification: G01R,H01L

Abstract:
1. A design process for comprising, manufacturing, or testing an integrated circuit, the integrated circuit comprising: a conductive structure surrounding a circuit device arranged on a substrate; and at least one feed through device associated with the conductive structure and providing signals to the device, wherein the substrate comprises one of a silicon substrate and a wafer; the conductive structure comprises a bottom arranged within the substrate; the conductive structure comprises a box comprising a cover, sidewalls, and the bottom; the cover comprises a layer of metal above the substrate; the bottom comprises a doped region of the substrate; the sidewalls are partially within the substrate and extend out of and above the substrate; the sidewalls comprise a doped portion of the substrate and at least one via; the conductive structure is an on-chip shielding structure; the at least one via of the sidewalls comprises a plurality of vias arranged one on top of another in a plurality of wiring levels over the substrate; and one of the plurality of vias is formed on the doped portion of the substrate.