Patent ID: 6771537
Filing Date: 2004-08-03
Classification: G11C

Abstract:
A non-volatile semiconductor memory device for making it possible to store four-value information in each of electrically erasable and writable non-volatile memory cells by controlling said memory cell to an erase state, a first write state, a second write state or a third write state each having a different threshold voltage, comprising:a write control circuit for setting said nonvolatile memory cell to the erase state, and controlling each of a first write operation for selectively setting said non-volatile memory cell under the erase state to the first write state, a second write operation for selectively setting said non-volatile memory cell to the second write state after said first write operation and a third write operation for selectively setting said non-volatile memory cell to the third write state after said second write operation, in a data rewrite operation of said non-volatile memory cell; a write data conversion circuit for generating one-bit write information deciding whether or not said non-volatile memory cell is brought into the first write state by said first write operation, one-bit write information deciding whether or not said non-volatile memory cell is brought into said second write state by said second write operation and one-bit information deciding whether or not said non-volatile memory cell is brought into the third write state by said third write operation, from two-bit write data given from outside, and a data latch circuit for latching the corresponding write information generated by said write data conversion circuit for each of said first to third write operations by said write control circuit, and selecting whether or not said memory cell is brought into the corresponding write state for each of said first to third write operations.