Patent ID: 6366231
Filing Date: 2002-04-02
Classification: H03M

Abstract:
An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits, said analog to digital conversion circuit comprising:an operational amplifier having an inverting terminal for receiving said analog input signal and further having an output terminal; an integrating capacitor connected between said inverting terminal and said output terminal of said operational amplifier, said integrating capacitor storing a charge proportional to an integral of said analog input signal; a charge subtracting circuit selectively coupled to said inverting terminal and said output terminal of said operational amplifier, said charge subtracting circuit removing a first predetermined charge from said integrating capacitor when an output charge of said operational amplifier is substantially equal to a second predetermined charge level, said first predetermined charge being removed from said integrating capacitor a number of times wherein removal of said first predetermined charge from said integrating capacitor said number of times allows said integral of said analog input signal to be larger than a maximum charge capable of being stored by said integrating capacitor; a digital logic circuit connected to said charge subtracting circuit, said digital logic circuit tracking said number of times that said first predetermined charge is removed from said integrating capacitor by said charge subtracting circuit, and said digital logic circuit providing at least one bit of said plurality of binary output bits; a residue quantizing circuit connected to said integrating capacitor and said output of said operational amplifier, said residue quantizing circuit determining a residual charge in said integrating capacitor, said residual charge being substantially equal to the stored charge in said integrating capacitor after said first predetermined charge has been removed from said integrating capacitor said number of times, and said residue quantizing circuit providing at least one additional bit of said plurality of binary output bits corresponding to said residual charge; and a low pass filter circuit selectively coupled to said output terminal of said operational amplifier, said low pass filter connected to said output terminal when said number of times said first predetermined charge is removed from said integrating capacitor is less than a predetermined number.