Patent ID: 6091892
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A method for programming a programmable logic device to implement a logic function, the programmable logic device including a function block having an AND array for generating a plurality of product term elements, a plurality of macrocells and a product term allocator, the method comprising the steps of:dividing the logic function into a set of equations, each equation including one or more product terms which are mappable into the product term elements of the function block;mapping a locked equation of the equation set by assigning the locked equation to a first group of product term elements, and by generating programming data for controlling the product term allocator, wherein the product term allocator is connected between the AND array and the plurality of macrocells and is programmable to route a selected product term element signal to any of the plurality of macrocells, wherein each macrocell has an OR gate programmably connected to the product term elements from the AND array through the product term allocator, and wherein product term element signals generated by the first group of product term elements are routed by the product term allocator to a first macrocell in response to the programming data;mapping non-locked equations of the equation set by assigning each non-locked equation to a second group of product term elements, and by modifying the programming data such that product term element signals generated by the second group of product term elements assigned to each non-locked equation are respectively routed to an associated second macrocell in response to the programming data;shuffling locations of the mapped equations to eliminate placement constraint violations by adjusting the programming data;creating a bit map whose contents are defined by the placement arrangement produced after the step of shuffling, the placement arrangement including said adjusted programming data; andtransmitting the bit map to the programmable logic device such that the programmable logic device is programmed to implement the logic function in accordance with the bit map.