Patent ID: 9006814
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first insulating layer on a substrate; a first semiconductor layer on the first insulating layer; a second semiconductor layer disposed on the first semiconductor layer and in contact with the first semiconductor layer; an upper gate electrode on the second semiconductor layer, wherein the first and second semiconductor layers include carbon element, and a carbon concentration of the first semiconductor layer is greater than a carbon concentration of the second semiconductor layer; a lower gate electrode disposed between the first insulating layer and the first semiconductor layer; and a second insulating layer disposed between the lower gate electrode and the first semiconductor layer, wherein the lower gate electrode includes: a third semiconductor layer disposed between the first insulating layer and the second insulating layer, and a fourth semiconductor layer disposed between the third semiconductor layer and the second insulating layer, and wherein a carbon concentration of the third semiconductor layer is greater than a carbon concentration of the fourth semiconductor layer.