Patent ID: 6170031
Filing Date: 2001-01-02
Classification: G06F

Abstract:
An interface apparatus, within a storage system, for controlling the transfer of sectors of data between a host processor and a buffer within the storage system in response to a READ and WRITE command issued by the host processor, said apparatus comprising: a Byte Count state machine, an Update Task File state machine, a Read State Machine comprising means for automating a READ DMA command and a means for automating a READ DMA MULTIPLE command from said host processor; and at least a first state and a second state wherein said Read State Machine requires only one state time between the transfer of each sector during a READ DMA MULTIPLE command such that said Read State Machine transistions between said first and second state until all sectors in a block have been transferred including transferring a first sector in said first state, transistioning to said second state on a first clock cycle, decrementing a Block Count register and loading a Byte Count register in said second state, and returning to said first state on a second clock cycle to transfer a second sector; and a Write State Machine comprising means for automating a WRITE DMA command, a multiplicity of autowrite DMA commands, and a WRITE DMA MULTIPLE command; and at least a third state and a fourth state wherein said Write State Machine requires only one state time between the transfer of each sector during a WRITE DMA MULTIPLE command such that said Write State Machine transistions between said third state and fourth states until all sectors in a block have been transferred including transferring a third sector in said third state, transistioning to said fourth state a third clock cycle, decrementing said Block Count register and loading siad Byte Count register in said fourth state, and returning to said third state on a fourth clock cycle to transfer a fourth sector.