Patent ID: 8013850
Filing Date: 2011-09-06
Classification: G09G

Abstract:
1. A driving circuit of an electrooptic device, comprising: a plurality of scanning lines; a plurality of data lines; first and second capacitor lines corresponding to each of the plurality of scanning lines; a common electrode; pixels corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, the pixels each including: a pixel switching element connected at one end to a data line corresponding to the element itself, and brought into conduction when a scanning line corresponding to the element itself is selected; a pixel capacitor disposed between the pixel switching element and the common electrode; and a storage capacitor disposed between one end of the pixel capacitor and one of the first and second capacitor lines corresponding to the scanning line; a scanning-line driving circuit that selects the scanning lines in a predetermined order; a capacitor-line driving circuit, when the one scanning line is selected, shifts the voltage of a first capacitor line corresponding to one scanning line to one of higher and lower levels from a predetermined voltage by a predetermined value, and holds the predetermined voltage after a scanning line apart from the one scanning line by a predetermined number of lines is selected until the one scanning line is selected again; and when the one scanning line is selected, shifts the voltage of a second capacitor line corresponding to the one scanning line to the other one of higher and lower levels from the predetermined voltage by the predetermined value, and holds the predetermined voltage after a scanning line apart from the one scanning line by a predetermined number of lines is selected until the one scanning line is selected again; a data-line driving circuit that applies a data signal to pixels corresponding to a selected scanning line via a data line, the data signal having a voltage corresponding to the gray level of the pixels corresponding to the selected scanning line, wherein when the one scanning line is selected, the capacitor- line driving circuit connects the first capacitor line corresponding to the one scanning line to one of a first feed line that feeds a first capacitance signal and a second feed line that feeds a second capacitance signal; connects the second capacitor line corresponding to the one scanning line to the other one of the first feed line and the second feed line; and connects the first capacitor line and the second capacitor line to a third feed line after a scanning line apart from the one scanning line by a predetermined number of lines is selected until the one scanning line is selected again, wherein the capacitor-line driving circuit comprises: first to sixth transistors corresponding to each row, wherein the gate electrode of the first transistor corresponding to each of the first and second capacitor lines is connected to a scanning line corresponding to the one scanning line, and the source electrode of the first transistor is connected to one of the first and second feed lines; the gate electrode of the second transistor is connected to the scanning line corresponding to the one scanning line, and the source electrode of the second transistor is connected to the other one of the first and second feed lines; the source electrodes of the third and fourth transistors are connected to the third feed line; the gate electrode of the fifth transistor is connected to the scanning line corresponding to the one capacitor line, and the source electrode of the fifth transistor is connected to an off-voltage feed line that feeds off-voltage for turning off the third and fourth transistors; the gate electrode of the sixth transistor is connected to a scanning line apart from the scanning line corresponding to the one capacitor line by a predetermined lines, and the source electrode of the sixth transistor is connected to an on-voltage feed line that feeds on-voltage for turning on the third and fourth transistors; and the drain electrodes of the first and third transistors are connected to the first capacitor line corresponding to the line, the drain electrodes of the second and fourth transistors are connected to the second capacitor line corresponding to the line, and the drain electrodes of the fifth and sixth transistors are connected to the gate electrodes of the third and fourth transistors.