Patent ID: 8248833
Filing Date: 2012-08-21
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines; and a plurality of memory cells arranged in matrix, provided at intersecting portions of the plurality of word lines and the plurality of bit lines, wherein each of the plurality of memory cells includes a PIN diode and an anti-fuse, wherein an anode of the PIN diode is electrically connected to one of the plurality of bit lines, wherein a cathode of the PIN diode is electrically connected to a first terminal of the anti-fuse, wherein a second terminal of the anti-fuse is electrically connected to one of the plurality of word lines, wherein the anti-fuse includes a silicon layer and an insulating layer which are interposed between a pair of electrodes, wherein a current direction in the PIN diode is parallel to a surface of a substrate.