Patent ID: 6300928
Filing Date: 2001-10-09
Classification: G09G,G11C

Abstract:
A scanning circuit comprising a plurality of cascaded scanning stages, each of the scanning stages having an input terminal and an output terminal, the scanning circuit including means for generating phase delayed scanning signals and means for receiving an input signal, the scanning stages comprising:output circuitry comprising a push-pull amplifier including a pull-up transistor and a pull-down transistor having respective conduction paths connected in series with the output terminal, the pull-up transistor having a control electrode and the pull-down transistor having a control electrode, the push-pull amplifier having a supply terminal for receiving one of the phase delayed scanning signals;input circuitry responsive to a scanning pulse applied to the input terminal for generating first and second control signals that are respectively coupled to the control electrodes of the pull-up transistor and a pull-down transistor for conditioning the push-pull amplifier to provide output scanning pulses; andmeans responsive to a signal at the output terminal for raising a voltage of the first control signal to be applied to the control electrode of the pull-up transistor.