Patent ID: 8866283
Filing Date: 2014-10-21
Classification: H01L,Y10T

Abstract:
1. A chip package structure, comprising: a) a chip having a plurality of first contact pads comprising ground pads for operation at substantially a same potential, and a plurality of second contact pads comprising switch pads for operation at variable potentials, and power pads for operation at substantially a same potential; b) a lead frame having a plurality of pins for external connection to said package structure, wherein said chip is disposed on said lead frame; c) a plurality of first bonding wires comprising ground bonding wires and being configured to connect said first contact pads directly to said lead frame without connecting to one of said plurality of pins; and d) a plurality of second bonding wires comprising switch signal bonding wires and being configured to connect said second contact pads to said plurality of pins on said lead frame, wherein other bonding wires connected to said power pads on said chip comprise power bonding wires.