Patent ID: 8797822
Filing Date: 2014-08-05
Classification: G06F,G11C,H01L

Abstract:
1. A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals, the method comprising: determining an operating mode for the plurality of DRAM devices; providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode; and possibly activated if the operating mode is determined to be a physical rank address mode; and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.