Patent ID: 6838322
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A method for forming a double-gated transistor, comprising the steps of: forming an insulative layer over a substrate; forming an amorphous silicon layer over said insulative layer for producing a polysilicon layer; forming a silicon germanium seed layer associated with said amorphous silicon layer for controlling silicon grain growth in producing said polysilicon layer; forming said polysilicon layer using an annealing step applied to said amorphous silicon layer, said annealing step comprising the step of controlling said silicon grain growth using said silicon germanium seed layer; and forming a source, a drain, and a channel from said polysilicon layer, said channel comprising a double-sided vertical fin structure; and forming a gate in association with said channel and around said double-sided vertical fin structure for forming said polysilicon double-gated transistor.