Patent ID: 7563627
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array substrate comprising: forming gate lines and data lines that cross each other on a lower substrate, a gate insulating film located between the gate lines and data lines, a thin film transistor formed at crossing of the gate lines and data lines, a lower gate pad electrode connected to the gate lines, and a lower data pad electrode; forming a passivation film on the substrate provided with the gate insulating film; forming a photo-resist pattern on the substrate provided with the passivation film; forming a first hole passing through a portion of the passivation film and through a portion of the gate insulating film using the photo-resist pattern, wherein a remaining part of the gate insulating film is left on the lower gate pad electrode; then removing the photo-resist pattern; then forming a second hole exposing the lower gate pad electrode by a dry etching; and forming a transparent electrode pattern through the second hole including an upper gate pad electrode connected to the exposed lower gate pad electrode, wherein forming the second hole is done through the remaining part of the gate insulating film.