Patent ID: 9214435
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A method for implementing three-dimensional integration (3Di) of functional components of a circuit comprising: forming landing pads of upper and lower layers such that each of the landing pads includes a respective protective coating and such that a thickness of each protective coating is greater than the protective coating of any landing pad disposed on a lower layer in a stack and smaller than the protective layer of any landing pad disposed on a higher layer in the stack; aligning an upper layer over an adjacent, lower layer during bonding of the upper and lower layers such that a landing pad disposed on the upper layer is offset from a landing pad disposed on the lower layer; etching through the upper and lower layers to form a via hole in the layers and to expose the landing pads; and filling the via hole with a conductive material to form a via that couples the landing pads of the upper and lower layers.