Patent ID: 6115290
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A memory device comprising:a nonvolatile memory cell;a bit line coupled to the nonvolatile memory cell; andcircuitry coupled to the nonvolatile memory cell and the bit line, the circuitry configured to reset the bit line to a lower predetermined state for an amount of time in response to a transition of an input address signal;wherein the circuitry comprises an address transition detection (ATD) circuit configured to receive the input address signal and generate a pulse signal; and a reset circuit coupled to the ATD circuit, the bit line, and nonvolatile memory cell, the reset circuit configured to reset the bit line to the lower predetermined state in response to the pulse signal; andwherein the reset circuit comprises a first transistor having a first terminal coupled to the bit line, a second terminal coupled to a power supply terminal, a third terminal coupled to the ATD circuit, the first transistor driving the bit line to the lower predetermined state in response to the pulse signal, a second transistor having a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the bit line, and a third terminal coupled to the third terminal of the first transistor.