Patent ID: 8468419
Filing Date: 2013-06-18
Classification: G06F,G11C,H03M

Abstract:
1. A memory circuit, comprising: a memory including a plurality of primary memory elements; an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the at least one primary memory element; at least one spare memory element; and a control circuit operative to replace at least one of the plurality of primary memory elements with the at least one spare memory element as a function of results generated by the error correction circuit; wherein the control circuit is further operative to indicate a given one of the memory elements as defective based at least in part on data read from a first portion of the given memory element, error correction information read from a second portion of the given memory element, and predicted error correction information determined for the data read from the first portion of the given memory element.