Patent ID: 8169030
Filing Date: 2012-05-01
Classification: H01L

Abstract:
1. A semiconductor memory device comprising a static memory cell composed of four MOS transistors arranged on a substrate, wherein the four MOS transistors function as first and second PMOS access transistors for supplying a charge to hold memory cell data and accessing the memory, and as a first and a second NMOS driver transistors for driving memory nodes to read memory cell data, wherein the first and second PMOS access transistors comprises a P-type first diffusion layer, a first columnar semiconductor layer and a P-type second diffusion layer arranged vertically in tiers in an ascending order on the substrate, the first columnar semiconductor layer being formed around its side with a gate, and wherein the first and second NMOS driver transistors comprises an N-type third diffusion layer, a second columnar semiconductor layer and an N-type forth diffusion layer arranged vertically in tiers in an ascending order on the substrate, the columnar semiconductor layer being formed around its side with a gate; the first PMOS access transistor and first NMOS driver transistor adjoin each other; the second PMOS access transistor and second NMOS driver transistor adjoin each other; a first well giving a potential to the substrate and common to multiple memory cells is formed in the substrate; the P-type first diffusion layer formed at the bottom of the first PMOS access transistor and the N-type first diffusion layer formed at the bottom of the first NMOS driver transistor are connected to each other via a first silicide layer formed on their surfaces; the mutually connected P-type first diffusion layer and N-type first diffusion layer function as a first memory node for holding data stored in the memory cell; a first anti-leak diffusion layer having the conductivity type opposite to the first well is formed between the first N-type diffusion layer or the P-type first diffusion layer and first well in order to prevent leak between the N-type first diffusion layer or the P-type first diffusion layer and first well, wherein the first anti-leak diffusion layer has a bottom shallower than an element separator; the first anti-leak diffusion layer is directly connected to the P-type first diffusion layer or the first N-type diffusion layer; a P-type second diffusion layer formed at the bottom of the second PMOS access transistor and an N-type second diffusion layer formed at the bottom of the second NMOS driver transistor are connected to each other via a second silicide layer formed on their surfaces; the mutually connected P-type second diffusion layer and N-type second diffusion layer function as a second memory node for holding data stored in the memory cell; a second anti-leak diffusion layer having the conductivity type opposite to the first well is formed between the N-type second diffusion layer or the P-type second diffusion layer and first well in order to prevent leak between the N-type second diffusion layer or the P-type second diffusion layer and first well, wherein the second anti-leak diffusion layer has a bottom shallower than an element separator; and the second anti-leak diffusion layer is directly connected to the P-type second diffusion layer or the N-type second diffusion layer.