Patent ID: 6496130
Filing Date: 2002-12-17
Classification: H03M

Abstract:
An active matrix type display device comprising:at least a source signal line driving circuit; at least a gate signal line driving circuit; a pixel portion including a plurality of pixels; each of the plurality of pixels including at least a pixel thin film transistor; a plurality of source signal lines; each of the plurality of source signal lines connected to the source signal line driving circuit and a source region of the pixel thin film transistor; a plurality of gate signal lines; each of the plurality of gate signal lines connected to the gate signal line driving circuit and a gate electrode of the pixel thin film transistor; a shift register circuit in the source signal line driving circuit; a first latch circuit in the source signal line driving circuit; a second latch circuit in the source signal line driving circuit; a D/A conversion circuit in the source signal line driving circuit; said D/A conversion circuit comprising: n resistors A0, A1, . . . Anâˆ’1, n resistors B0, B1, . . . , Bnâˆ’1, a power-supply voltage line L and a power-supply voltage line H being maintained at potentials different from each other, n switches SWa0, SWa1, . . . , SWanâˆ’1, n switches SWb0, SWb1, . . . , SWbnâˆ’1, and an output line, wherein resistance values of the n resistors A0, A1, Anâˆ’1 are R, 2R, . . . , 2nâˆ’1R, respectively, wherein n stands for a natural number of 1 or greater, and R stands for a positive number, respectively, wherein resistance values of the n resistors B0, B1, . . . , Bnâˆ’1 are R, 2R, . . . , 2nâˆ’1R, respectively, wherein both ends of each of the n resistors A0, A1, . . . Anâˆ’1 are connected to one end of each of the n switches SWa0, SWa1, . . . , SWanâˆ’1 and to the output line, wherein an end of each of the n switches SWa0, SWa1, . . . , SWanâˆ’1 which is not connected to each of the n resistors A0, A1, . . . Anâˆ’1 is connected to the power-supply voltage line L, wherein both ends of each of the n resistors B0, B1, . . . , Bnâˆ’1 are connected to one end of each of the n switches SWb0, SWb1, . . . , SWbnâˆ’1 and to the output line, wherein an end of each of the n switches SWb0, SWb1, . . . , SWbnâˆ’1 which is not connected to each of the n resistors B0, B1, . . . , Bnâˆ’1 is connected to the power-supply voltage line H, wherein the n switches SWa0, SWa1, . . . , SWanâˆ’1 and the n switches SWb0, SWb1, . . . , SWbnâˆ’1 are controlled by n-bit digital signals inputted from the outside, wherein inverted signals of the n-bit digital signals which are inputted to the n switches SWa0, SWa1, . . . , SWanâˆ’1 are respectively inputted to the n switches SWb0, SWb1, . . . , SWbnâˆ’1, and wherein an analog gradation voltage signal is outputted from said output line, wherein each of the switches SWa0, SWa1, . . . , SWanâˆ’1 includes a first thin film transistor, wherein each of the switches SWb0, SWb1, . . . , SWbnâˆ’1 includes a second thin film transistor.