Patent ID: 6828654
Filing Date: 2004-12-07
Classification: H01L,H03L

Abstract:
A phase locked loop circuit with dual gate dielectric thicknesses, comprising:an oscillator to output a reference clock signal; a reference frequency divider to receive and divide the reference clock signal, and output a reference signal; a comparison frequency divider to receive a control voltage signal and output a comparison signal; a phase comparator to receive the reference signal and the comparison signal, wherein said phase comparator compares the reference signal with the comparison signal and outputs a frequency difference signal and a phase difference signal; a charge pump to receive the frequency difference and the phase difference signals and output a charge pump signal; a low-pass filter to receive the charge pump signal and output a low pass filter signal; and a voltage controlled oscillator to receive the low pass filter signal and output the control voltage signal, wherein said oscillator, said reference frequency divider, said comparison frequency divider, said phase comparator, said charge pump, and said voltage controlled oscillator comprise devices having thin gate oxide layers; wherein said low-pass filter comprises a capacitor formed by an N-type substrate; a P-type region within said N-type substrate; a thick oxide layer formed over said P-type region; a P+ gate electrode formed over said thick oxide layer and coupled to a first voltage supply line; and P+ pick-up terminals within said P-type region adjacent the said gate electrode and coupled to a second voltage supply line; and wherein said thick oxide layer of said capacitor reduces leakage current such that a gate-to-substrate voltage of said capacitor is maintained, thereby maintaining a stable control voltage for the phase locked loop circuit.