Patent ID: 6649481
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method of fabricating a semiconductor device structure having major portions of heavily-doped source and drain regions resided on a trench-isolation region using highly-conductive semiconductor layers, the method comprising the steps of:providing a semiconductor substrate; forming a shallow-trench-isolation (STI) structure for said semiconductor device structure having a gate-dielectric layer formed on a surface of a retrograde-well over said semiconductor substrate and a highly-conductive gate layer deposited over said gate-dielectric layer and a planarized capping-oxide layer and a planarized trench field-oxide layer, and said planarized capping-oxide layer being formed along a sidewall of said planarized trench field-oxide layer; depositing a masking dielectric layer over said highly-conductive gate layer; defining a gate region and a gate interconnection of said semiconductor device structure using a patterned masking photoresist PR3; removing selectively said masking dielectric layer and said highly-conductive gate layer using anisotropic dry etching to form said gate region and said gate interconnection of said semiconductor device structure, followed by stripping said patterned masking photoresist PR3; implanting doping impurities in a self-aligned manner into said retrograde-well using a patterned masking photoresist PR4 to form lightly-doped source and drain regions or heavily-doped source and drain regions and then stripping said patterned masking photoresist PR4; forming dielectric spacers on sidewalls of said gate region and said gate interconnection by depositing a conformable dielectric layer followed by etching back said conformable dielectric layer; performing pocket or halo-implant using a patterned masking photoresist PR5 to form punch-through stops in said retrograde-well over said semiconductor substrate using large-tilt-angle implantation and then stripping said patterned masking photoresist PR5; removing said gate-dielectric layers and said planarized capping-oxide layers outside of said dielectric spacers and simultaneously etching said planarized trench field-oxide layer to a depth approximately equal to or larger than a junction depth of said lightly-doped source and drain regions or said heavily-doped source and drain regions in a self-aligned manner by using said masking dielectric layer over said gate region, said gate interconnection and said dielectric spacers as a hard etching mask; depositing a conductive semiconductor film over a formed structure to a level higher than a top level of said masking dielectric layer; planarizing said conductive semiconductor film using chemical-mechanical polishing (CMP) and using said masking dielectric layer as a polishing stop; patterning planarized conductive semiconductor films to define said heavily-doped source and drain regions made of said conductive semiconductor film using a patterned masking photoresist PR6 followed by selectively removing said conductive semiconductor film and then stripping said patterned masking photoresist PR6; etching back formed conductive semiconductor films in a self-aligned manner to a depth approximately equal to a top level of said gate-dielectric layer; implanting doping impurities in a self-aligned manner to form said heavily-doped source and drain regions in semiconductor surface regions of said retrograde-well and to dope remained conductive semiconductor films using a patterned masking, photoresist PR7 and then stripping said patterned masking photoresist PR7; depositing a refractory metal film over a formed structure surface followed by annealing in a nitrogen ambient to perform self-aligned silicidation of said remained conductive semiconductor films; removing refractory metal-nitride film using a wet-chemical solution; depositing an interlayer dielectric film and planarizing said interlayer dielectric film; patterning planarized interlayer dielectric film using a patterned masking photoresist PR8 to form contact holes on said heavily-doped source and drain regions in said trench-isolation region and etching said contact holes followed by stripping said patterned masking photoresist PR8; depositing a barrier-metal layer over a formed structure surface and then depositing a plug-metal film to fill up said contact holes; planarizing a formed structure surface by removing said barrier-metal layer and said plug-metal film over a surface of said planarized interlayer dielectric film; depositing a first-level interconnection metal film over a planarized structure surface; and patterning said first-level interconnection metal film by using a patterned masking photoresist PR9 and then selectively removing said first-level interconnection metal film followed by stripping said patterned masking photoresist PR9.