Patent ID: 6041168
Filing Date: 2000-03-21
Classification: G01R,G06F

Abstract:
A delay verification apparatus for verifying delay of a circuit including a plurality of nodes, said delay verification apparatus comprising:tracing means for respectively calculating, for each node of said circuit, a first delay time from each node to a starting point within said circuit and a second delay time from each node to an ending point within said circuit based on contents of a circuit model; andlimit inspecting means, to produce a modified circuit model to be verified, for following steps of:a first deleting operation of deleting a node from the contents of a circuit model, said node having a sum of the first delay time and the second delay time which is less than a first predetermined value;a second deleting operation of deleting a node from the contents of the circuit model, said node having a sum of the first delay time and the second delay time which is greater than a second predetermined value; anda third deleting operation of deleting a node from the contents of the circuit model, said node having a sum of the first delay time and the second delay time which is less than the first predetermined value and greater than the second predetermined value, the second predetermined value being less than the first predetermined value.