Patent ID: 7103832
Filing Date: 2006-09-05
Classification: H03M

Abstract:
1. A cyclic redundancy check circuit, comprising: a W-bit packet data slice latch having outputs; a multiple level XOR subtree having inputs and outputs, each level comprising one or more XOR subtrees, each output of said packet data slice latch coupled to an input of said multiple level XOR subtree, each lower level XOR subtree of said multiple level XOR subtree coupled to a higher level XOR subtree of said multiple level XOR subtree through an intervening latch level; a remainder XOR subtree having inputs and outputs; a combinational XOR subtree having inputs and outputs, the outputs of said remainder XOR subtree and the outputs of said multiple level XOR subtree coupled to the inputs of said combinational XOR subtree; and an M-bit current CRC result latch having inputs and outputs, the output of said combinational XOR subtree coupled to the inputs of said current CRC result latch and the outputs of said M-bit current CRC result latch coupled to the inputs of said remainder XOR subtree.