Patent ID: 8716089
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising: forming a thermally grown oxygen-containing layer over a semiconductor layer in the NVM region and the logic region; forming a polysilicon layer over the thermally grown oxygen-containing layer; patterning the polysilicon layer and thermally grown oxygen-containing layer in the logic region to form a dummy gate and dummy gate dielectric in the logic region; patterning the polysilicon layer and thermally grown oxygen-containing layer to form a select gate and a gate dielectric in the NVM region; forming a first dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the first dielectric layer surrounds the select gate and gate dielectric in the NVM region and surrounds the dummy gate and dummy gate dielectric in the logic region; removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region; forming a charge storage layer over the semiconductor layer and select gate in the NVM region, and over the first dielectric layer and the dummy gate in the logic region; removing the charge storage layer from the logic region; removing the dummy gate and dummy gate dielectric in the logic region which results in an opening in the logic region; forming a second dielectric layer over the charge storage layer in the NVM region and over the first dielectric layer and within the opening in the logic region; forming a gate layer over the second dielectric layer in the NVM region and over the second dielectric layer and in the opening in the logic region; removing a top portion of the gate layer in the NVM region and the logic region, wherein a remaining portion of the gate layer in the opening forms a logic gate in the logic region; and patterning a remaining portion of the gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate, wherein a top surface of the control gate is substantially coplanar with a top surface of the logic gate.