Patent ID: 8050102
Filing Date: 2011-11-01
Classification: G11C

Abstract:
1. A memory device, comprising: an array of memory cells; a plurality of access lines in communication with the array of memory cells; and a plurality of buses selectively coupled to an access line driver for supplying control signals to the access line driver; wherein circuitry for accessing the array of memory cells is configured to select one of the plurality of buses to supply control signals to the access line driver during an access operation based at least on a relationship of at least one of the access lines relative to a target access line; and wherein the circuitry for accessing the array of memory cells is further configured to select a potential from a plurality of potentials of which the access line driver is coupled to receive, in response to the supplied control signals of the selected one of the plurality of buses, to drive at least one of the access lines during the access operation.