Patent ID: 7023751
Filing Date: 2006-04-04
Classification: G11C

Abstract:
1. A memory array, comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor; a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective colunm of memory cells; a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells; a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier being operable to couple a first voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a first logic level, and being operable to couple a second voltage to the digit line to which the sense amplifier is coupled responsive to sensing a voltage level on the digit line corresponding to a second logic level, the first voltage being a positive supply voltage and the second voltage being a positive supply voltage having a magnitude that is significantly less than the magnitude of the first voltage; and a voltage regulator coupled to the respective sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor and being operable to supply the first and second voltages to the sense amplifier, the second voltage being supplied using the at least one bipolar transistor.