Patent ID: 6744646
Filing Date: 2004-06-01
Classification: G05F

Abstract:
A voltage level rising regulator, for converting a low voltage signal to a high voltage signal, wherein the low voltage signal is between a low level and a high level of the low voltage signal, and the high voltage level is between a low level and a high level of the high voltage signal, the voltage level rising regulator comprising:a first NMOS transistor, having a drain, a gate and a source, and the low voltage signal being applied to the drain of the first NMOS transistor; an inverter, having an input terminal and an output terminal, and the low voltage signal being applied to the input terminal of the inverter; a second NMOS transistor, having a drain, a gate and a source, and the drain of the second NMOS transistor being coupled to the output terminal of the inverter; a first PMOS transistor, having a drain, a gate and a source, wherein the gate of the first PMOS transistor is connected to the source of the first NMOS transistor and the low level of the high voltage signal is inputted to the source of the first PMOS transistor; a second PMOS transistor, having a drain, a gate and a source, wherein the drain of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the high level of the high voltage signal is inputted to the source of the second PMOS transistor; a third PMOS transistor, having a drain, a gate and a source, wherein the source is biased, the drain of the third PMOS transistor is connected to source of the first NMOS transistor, and the source of the third PMOS transistor is connected to the drain of the second PMOS transistor; a fourth PMOS transistor, having a drain, a gate and a source, wherein the gate of the fourth PMOS transistor is connected to the source of the second NMOS transistor, the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the low level of the high voltage signal is inputted to the source of the fourth PMOS transistor; a fifth PMOS transistor, having a drain, a gate and a source, wherein the drain of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor and the gate of the fifth PMOS transistor is connected to the drain of the first PMOS transistor, and the high level of the high voltage signal is inputted to the source of the fifth PMOS transistor; a sixth PMOS transistor, having a drain, a gate and a source, wherein the source is biased, the drain of the sixth PMOS transistor is connected to the source of the second NMOS transistor, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor; and an output end, connected to the drain of the fourth PMOS transistor.