Patent ID: 7791971
Filing Date: 2010-09-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first cell array including cells ( a second cell array including cells ( a third cell array including cells ( (M+1) pairs of bit lines, each of which is provided to connect (N+1) cells arrayed in a column direction in the first cell array; (N+1) word lines, each of which is provided to connect (M+1) cells arrayed in a row direction in the first cell array; (N+1) row decoders, each of which is connected to an end of a corresponding one of the word lines; and a first replica circuit adjusting sense timing of the second cell array, the first replica circuit being provided between the row decoders and the second cell array and having: a first dummy array including dummy cells (D, a dummy word line to which the dummy cells (D, a dummy row decoder connected to an end of the dummy word line; a first dummy local bit line and first dummy global bit line to which the dummy cells ( a second replica circuit adjusting sense timing of the third cell array, the second replica circuit being provided between the second cell array and the third cell array and having: a second dummy array including dummy cells (D,J) to (D,M) arrayed in the row direction and dummy cells ( a second dummy local bit line and second dummy global bit line to which the dummy cells (