Patent ID: 6689676
Filing Date: 2004-02-10
Classification: H01L

Abstract:
A method for forming a semiconductor device structure in a semiconductor layer, comprising:forming a first region and a second region of opposite conductivity type in the semiconductor layer, the first region and the second region being electrically isolated by an isolation region; forming a control electrode dielectric overlying the first region and the second region; forming a silicon-containing layer overlying and in contact with the control electrode dielectric; patterning a mask layer to overlie a selective portion of the silicon-containing layer; depositing a first metal layer overlying the silicon-containing layer and the mask layer; annealing the semiconductor device structure to form a first control electrode silicide by chemical reaction between the first metal layer and those portions of the silicon-containing layer not underlying the mask layer; removing remaining portions of the first metal layer that did not chemically react with the silicon-containing layer; removing the mask layer; depositing a second metal layer overlying the first control electrode silicide and the silicon-containing layer; annealing the semiconductor device structure to form a second control electrode silicide by chemical reaction between the second metal layer and the silicon-containing layer; removing remaining portions of the second metal layer that did not chemically react with the silicon-containing layer; forming a conducting layer overlying the first control electrode silicide and the second control electrode silicide; patterning the conducting layer, the first control electrode silicide and the second control electrode to form a first control electrode stack and a second control electrode stack having differing metal silicide content.