Patent ID: 7230302
Filing Date: 2007-06-12
Classification: H01L

Abstract:
1. A transistor having a gate located over a channel region recessed into a semiconductor substrate, comprising: a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent to but not surrounded by said lightly doped region within said semiconductor substrate; an oppositely doped well located under and within said channel region; a doped region, located between said heavily doped region of said source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said source/drain; another source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region; and another doped region, located between said heavily doped region of said another source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain; and an oppositely doped buried layer under said doped region and said another doped region.