Patent ID: 8547765
Filing Date: 2013-10-01
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cells connected to a word line; a plurality of sense amplifiers each assigned to an associated one of the memory cells; and a control circuit that activates the sense amplifiers in response to selection of the word line, wherein in response to a request for writing of data to any one of the memory cells, a driving performance of the plurality of sense amplifiers is temporarily reduced, wherein the control circuit includes a drive transistor that supplies an operating voltage to the sense amplifiers, wherein the control circuit is configured to supply a first voltage to a control electrode of the driver transistor in response to selection of the word line, and is configured to supply a second voltage that is different from the first voltage to the control electrode of the driver transistor in response to the request for writing of data to any of the memory cells, wherein both of the first and second voltages bring the driver transistor into an on state, and the operating voltage that is supplied when the second voltage is supplied to the control electrode is lower than the operating voltage that is supplied when the voltage is supplied to the control electrode.