Patent ID: 6707822
Filing Date: 2004-03-16
Classification: H04L

Abstract:
A digital subscriber line (DSL) transceiver for a plurality of DSL sessions, said DSL transceiver comprising:an asynchronous transfer mode (ATM) accelerator interfacing a plurality of ATM channels for each of said plurality of DSL sessions, said ATM accelerator operative to convert a first analog signal to a first bit stream, said ATM accelerator operative to convert a second bit stream, said ATM accelerator operative to convert a second bit stream to a second analog signal; a frame memory bi-directionally coupled to said ATM accelerator, said frame memory operative to receive a bit stream and store said bit stream as a frame of data; a framer/coder/interleaver (FCI) bi-directionally coupled to said frame memory, said FCI operative to perform a data operation on said frame of data; an interleave/de-interleave memory (IDIM) bi-directionally coupled to said FCI, said IDIM operative to receive said frame of data and store said frame of data; and a digital signal processing (DSP) core for performing a processing task, said DSP core bi-directionally coupled to said ATM accelerator, said frame memory and said IDIM, wherein said DSP core includes a means to generate a periodic signal, wherein, responsive to said periodic signal, said transceiver performs a transmit process sequentially for a first subset of said plurality of DSL sessions and performs a receive process sequentially for a second subset of said plurality of DSL sessions.