Patent ID: 6777266
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method for manufacturing a dual-chip integrated circuit package, comprising the steps of:preparing a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second rows of leads; mounting a first integrated circuit chip onto the support members of the leadframe, the first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; the first integrated circuit chip being mounted onto the support members in such a manner that the front side thereof faces the support members and the bonding pads on the first integrated circuit chip are separated from any of the support members; performing a first wire-bonding process to connect a plurality of bonding wires between the bonding pads on the first integrated circuit chip and the first leads of the leadframe; mounting a second integrated circuit chip in a back-to-back manner to the first integrated circuit chip; the second integrated circuit chip having a front side and a back side, with the front side thereof being formed with a plurality of bonding pads; the second integrated circuit chip being attached onto the first integrated circuit chip in such a manner that the back side of the second integrated circuit chip is attached to the back side of the first integrated circuit chip and the bonding pads on the second integrated circuit chip are aligned to at least one of the support members; performing a second wire-bonding process to connect a plurality of bonding wires between the bonding pads on the second integrated circuit chip and the second leads of the leadframe; and performing an encapsulation process to form an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe.