Patent ID: 6498527
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A voltage generation circuit having a capacitor and generating a prescribed voltage through a node connected to a first terminal of said capacitor, comprising:an n-channel transistor having one of a source terminal and a drain terminal connected to said node with the other one of said source terminal and said drain terminal defining an output terminal outputting said prescribed voltage; and a p-channel transistor having one of a source terminal and a drain terminal connected to said node with the other one of said source terminal and said drain terminal defining a reference potential terminal, wherein gate terminals of said n-channel transistor and said p-channel transistor are connected in common, wherein one of two clock signals inverted in phase to each other is applied to a second terminal of said capacitor while the other one of said two clock signals is applied to said gate terminals connected in common without going through a capacitor, and wherein said voltage generation circuit is formed on a P-type semiconductor substrate having a triple well structure, said n-channel transistor includes a MOSFET formed on a P-type well to which said output terminal is connected for obtaining its back gate potential, said p-channel transistor includes a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and said capacitor includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to said node.