Patent ID: 7602616
Filing Date: 2009-10-13
Classification: H01R,H05K

Abstract:
1. An apparatus comprising: a first socket having first N sets of front side bus (FSB) contacts to house a first package having first 2N dice, each of the first 2N dice having M cores, N and M being positive integers; a first chipset having 2N FSB signal groups coupled to the first socket to interface to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups, the first chipset comprising: a second socket having second N sets of FSB contacts to house a second package having second 2N dice, each of the second 2N dice having K cores, K being a positive integer, the second socket being coupled to the first chipset to interface the second package to the first chipset via the second N sets of FSB contacts using second N FSB signal groups of the 2N FSB signal groups.