Patent ID: 6442740
Filing Date: 2002-08-27
Classification: G06F

Abstract:
A clock signal analysis device comprising:first memory means for storing circuit connection information including transistor information and net information, said transistor information comprising logical gates including clock buffers and said net information comprising parasitic resistances and parasitic capacities of wires among transistors to be used during analysis for delay/skew values in clock signal propagation paths in a semiconductor integrated circuit; second memory means for storing transistor characteristic information to be used during a simulation for circuit operation of said semiconductor integrated circuit; third memory means for storing control information to be used for controlling an execution of said analysis of delay/skew values; pre-processing means for inputting said circuit connection information stored in said first memory means, said transistor characteristic information stored in said second memory means, said control information stored in said third memory means, and for editing said circuit connection information, said transistor characteristic information, and said control information; simulation execution means for inputting said edited information transferred from said pre-processing means and for executing said simulation of circuit operation of said semiconductor integrated circuit by using a circuit simulator and a switch level simulator; and after-processing means for inputting simulation results transferred from said simulation execution means, and for calculating a delay value of each clock signal terminal node from each clock signal input node, a skew value as a difference between delay values of clock signal terminal nodes, a rising time of said clock signal, and a falling time of said clock signal, and for transferring said calculated delay values, said skew values, said rising time, and said falling time as simulation analysis results in order to display said simulation analysis results on display means, wherein said pre-processing means edits said circuit connection information into an usable state for said simulation, and said after-processing means displays said simulation analysis results executed by said simulation means on a two-dimensional distribution map through said display means.