Patent ID: 6058469
Filing Date: 2000-05-02
Classification: G06F

Abstract:
A dynamically reconfigurable computer within a reprogrammable logic device, the dynamically reconfigurable computer comprising:an architecture description memory having an output, for storing architecture description signals that characterize an architecture of the reconfigurable computer, the architecture description signals comprising an interrupt response signal that specifies a manner in which the dynamically reconfigurable computer responds to an interrupt;an instruction state sequencer having an input, for controlling execution of an instruction by the reconfigurable computer; andan interrupt state machine having a first input, a second input, and an output, for generating a transition control signal that specifies when during the instruction execution cycle a transition to an interrupt service state is allowed, the input of the interrupt state machine coupled to the output of the architecture description memory, the output of the interrupt state machine coupled to the input of the instruction state sequencer.