Patent ID: 7439134
Filing Date: 2008-10-21
Classification: H01L

Abstract:
1. A method comprising: providing a substrate having a first region for formation of at least one nonvolatile memory cell transistor, a second region that is electrically separated from the first region and a third region that is electrically separated from the first and second regions, the second region being for formation of at least one transistor of higher voltage capability than at least one transistor of the third region; forming a layer of transistor gate dielectric overlying the second region; forming a tunnel dielectric layer overlying the first region, the second region and the third region; forming a first polysilicon layer overlying the tunnel dielectric layer and the layer of transistor gate dielectric; patterning the first polysilicon layer to form at least one memory cell gate overlying the first region; depositing a multiple layer dielectric overlying the first polysilicon layer and exposed portions of the tunnel dielectric layer, the multiple layer dielectric having at least one layer that stores electrical charge; using a same mask in a same etch removal step to form one or more control electrodes in the second region from the first polysilicon layer while substantially removing the first polysilicon layer overlying the third region; and completing formation of the at least one nonvolatile memory cell in the first region, the at least one transistor in the second region and the at least one transistor in the third region, the at least one transistor in the second region having a thicker control electrode oxide than the at least one transistor in the third region to permit the higher voltage capability.