Patent ID: 6915412
Filing Date: 2005-07-05
Classification: G06F

Abstract:
1. A microprocessor, comprising: prefetch control logic that fetches a plurality of instruction sets from an instruction store, wherein each of said plurality of instruction sets comprises a plurality of instructions; a prefetch buffer that stores said plurality of instruction sets fetched by said prefetch control logic; a branch decoder that decodes said plurality of instruction sets stored by said prefetch buffer; a first in first out (FIFO) buffer that receives and stores said plurality of instruction sets decoded by said branch decoder; buffer control logic that serially transfers each of said plurality of instruction sets from a top portion of said FIFO buffer to a bottom portion of said FIFO buffer; and an execution unit adapted to execute instructions from one or more instruction sets stored in said bottom portion of said FIFO buffer, said execution unit concurrently executing more than one instruction from said one or more instruction sets stored in said bottom portion of said FIFO buffer and executing at least one instruction from said one or more instruction sets stored in said bottom portion of said FIFO buffer out of a predefined program order; wherein said execution unit generates a control signal when all of the instructions in one of said one or more instruction sets from said bottom portion of said FIFO buffer have completed, and wherein, in response to said control signal, said buffer control logic transfers another instruction set from said plurality of instruction sets into said bottom portion of said FIFO buffer.