Patent ID: 6044426
Filing Date: 2000-03-28
Classification: G06F,G11C,Y02D

Abstract:
A memory system having a plurality of memory devices, the memory system comprises:a bus having a plurality of signal lines coupled to the plurality of memory devices, the bus provides a transaction request to the plurality of memory devices, wherein the transaction request includes identification information;a controller, coupled to the bus, wherein the controller generates the transaction request;a first memory device including:a memory array which includes a plurality of memory cells;a programmable register to store a first memory identification value to identify the first memory device on the bus;interface circuitry, coupled to the bus, to receive a transaction request;comparison circuitry, coupled to the programmable register and the interface circuitry of the first memory, to determine whether the identification information in the transaction request corresponds to the first memory identification value wherein when the identification information corresponds to the first memory identification value, the first memory device responds to the transaction request; anda second memory device including:a memory array which includes a plurality of memory cells;a programmable register to store a second memory identification value which identifies the second memory device on the bus;interface circuitry, coupled to the bus, to receive the transaction request;comparison circuitry, coupled to the programmable register and the interface circuitry of the second memory device, to determine whether the identification information in the transaction request corresponds to the second memory identification value wherein when the identification information corresponds to the second memory identification value, the second memory device responds to the transaction request.