Patent ID: 6081456
Filing Date: 2000-06-27
Classification: G11C,H01L

Abstract:
A bit line control circuit comprising:a plurality of first-level pass transistors coupled to receive a first set of bit lines from a memory array, wherein each bit line in the first set of bit lines is coupled to one and only one of the first-level pass transistors;a second set of bit lines coupled to the first-level pass transistors;a plurality of second-level pass transistors coupled to the second set of bit lines, wherein each bit line in the second set of bit lines is coupled to a parallel-connected pair of the second level pass transistors;a third set of bit lines coupled to the second-level pass transistors; anda plurality of voltage control circuits coupled to the third set of bit lines, wherein the voltage control circuits apply voltages to the third set of bit lines to perform read, write and erase operations in the memory array.