Patent ID: 6859384
Filing Date: 2005-02-22
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory array in which a plurality of memory cells are arranged in a matrix, wherein said memory array includes a plurality of first and second bit lines provided to correspond to memory cell columns, respectively, and a plurality of first and second word lines provided to correspond to memory cell rows, respectively; said semiconductor memory device further comprising: a plurality of first sense amplifiers connected to at least one of said plurality of first bit lines in a region adjacent to said memory array in a row direction, respectively; and a plurality of second sense amplifiers connected to at least one of said plurality of second bit lines in a region opposite to said plurality of first sense amplifiers across said memory array, respectively; and wherein each of said plurality of memory cells has a first transistor connected between a corresponding one of said plurality of first bit lines and a storage node, a second transistor connected between a corresponding one of said plurality of second bit lines and said storage node, and a capacitor connected to said storage node to hold charges as data; said first and second sense amplifiers are provided to correspond to every two adjacent memory cell columns, respectively, the first bit line corresponding to one of said two adjacent memory cell columns and the second bit line corresponding to the other of said two adjacent memory cell columns are arranged between said two adjacent memory cell columns, each of said first sense amplifiers is connected to two out of said plurality of first bit lines that correspond to said two adjacent memory cell columns, and each of said second sense amplifiers is connected to two out of said plurality of second bit lines that correspond to said two adjacent memory cell columns.