Patent ID: 7531419
Filing Date: 2009-05-12
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device including a capacitor, the capacitor comprising a first electrode, a dielectric film formed over the first electrode, and a second electrode formed over the dielectric film, the method comprising the steps of: (a) forming a plurality of lower wiring layers over a semiconductor substrate; (b) forming an insulating film over the lower wiring layers; (c) forming a first via hole and a second via hole in the insulating film; (d) forming an electrode trench larger in planar area than the second via hole in the insulating film so that the electrode trench is connected to the second via hole; (e) forming a first conductive film over the insulating film including an interior of the electrode trench, the first via hole, and the second via hole; (f) removing the first conductive film present outside the electrode trench using a chemical mechanical polishing method, allowing the first conductive film to remain in the interior of the electrode trench, the first via hole, and the second via hole, to form the first electrode in the interior of the electrode trench and the second via hole, and to form the first plug in an interior of the first via hole; (g) forming the dielectric film over the insulating film including an upper portion of the first electrode and forming a second conductive film over the dielectric film; (h) dry-etching the second conductive film and the dielectric film at the same time with use of a photoresist film as a mask, thereby allowing the dielectric film having an area larger than that of the first electrode to remain over the first electrode, and forming the second electrode over the dielectric film, wherein the second electrode comprises the second conductive film and has an area larger than that of the first electrode; (i) removing the photoresist film; and (j) forming a plurality of upper wiring layers over the insulating film, the first plug, and the second electrode, wherein one of the upper wiring layers is connected to the first plug, and wherein the other of the upper wiring layers is connected to the second electrode.