Patent ID: 7328396
Filing Date: 2008-02-05
Classification: H03M

Abstract:
1. A circuit, comprising: multiple packet data slice latches each having W-bits where W is a positive integer, each packet data slice latch having inputs and outputs, said packet data slice latches connected in series from a first to a last packet data slice latch, outputs of a previous packet data slice latch connected to inputs of an immediately subsequent packet data slice latch; a data partition comprising multiple data XOR subtree levels and having data latches between said data XOR subtree levels, said data partition having inputs and outputs, said outputs of each packet data slice latch connected to corresponding inputs of said data partition; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between said remainder XOR subtree levels, said remainder partition having inputs and outputs; a combinatorial XOR tree having inputs and outputs, the outputs of said remainder partition and the outputs of said data partition connected to corresponding inputs of said combinatorial XOR tree; and a current cyclic redundancy check (CRC) remainder latch having M-bits where M is a positive integer and having inputs and outputs the outputs of said combinatorial XOR tree connected to corresponding inputs of said current CRC remainder latch and the outputs of said current CRC remainder latch connected to corresponding inputs of said remainder partition.