Patent ID: 7957206
Filing Date: 2011-06-07
Classification: G11C

Abstract:
1. An integrated circuit device comprising: a memory cell array including: memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, the electrically floating body transistor associated with a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line; sense amplifier circuitry having an input which is electrically coupled to the bit line to receive a signal which is responsive to the current conducted on the bit line by the electrically floating body transistor of the selected memory cell and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof; current regulation circuitry, electrically coupled to the bit line, to sink or source at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation; and sensing circuitry, coupled between the bit line and the current regulation circuitry, to responsively couple the current regulation circuitry to the bit line during only the portion of the read operation.