Patent ID: 8014218
Filing Date: 2011-09-06
Classification: G11C

Abstract:
1. A device, comprising: a first amplifier stage having an input signal applied thereto; wherein the first amplifier stage includes an isolation capacitor and a capacitor shunt switch connected across the isolation capacitor in parallel and having the input signal applied thereto and wherein an output of the isolation capacitor and the capacitor shunt switch connect at a signal node, wherein the first amplifier stage further includes a gated inverter, with respect to power and ground terminals, that connects to the signal node and an inverter shunt switch that connects between the signal node and an output of the inverter; wherein the input signal is on a bitline from a DRAM array of memory cells, and wherein the first amplifier stage comprises a sense amplifier for the DRAM array of memory cells; and a write back switch that connects to an output of the first amplifier stage and that provides an output that connects to the bitline, wherein when the write back switch is selectively closed a reinforcing voltage value is applied to the bitline, and wherein the capacitor shunt switch is also selectively closed when the write back switch is selectively closed.