Patent ID: 8755227
Filing Date: 2014-06-17
Classification: G11C,H01L

Abstract:
1. A NAND flash memory unit, comprising: a string of memory cells connected in series; two source/drain (S/D) regions coupled to two terminals of the string of memory cells; at least one select transistor coupled between a terminal of the string and one of the two S/D regions, for selecting the string of memory cells; and at least one erase transistor coupled between the at least one select transistor and the one of the two S/D regions, for reducing Vt-shift of the at least one select transistor, wherein a plurality of gates of the memory cells are coupled to a first voltage source, a gate of the at least one select transistor coupled to a second voltage source, and a gate of the at least one erase transistor coupled to a third voltage source, wherein the first voltage source and the second voltage source are different from each other.