Patent ID: 6281529
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A semiconductor device including a plurality of cell areas laid out along a periphery of said semiconductor device, with a plurality of transistors being formed in each cell area, said semiconductor device comprising:at least three transistor groups formed from said plurality of transistors in each cell area and arranged in a direction perpendicular to a circumferential direction of said semiconductor device, and each of said at least three transistor groups being connected to one of a high-potential power supply and a low-potential power supply, wherein said at least three transistor groups include PMOS transistor groups and NMOS transistor groups that are alternately located; andan interconnection line connecting said at least three transistor groups to each other and being common to said at least three transistor groups, said interconnection line further connecting said at least three transistor groups to an external pad, and said at least three transistor groups being arranged in parallel with each other and wherein said at least three transistor groups are arranged such that alternate transistor groups in the direction perpendicular to the circumferential direction are of different types, wherein said MOS transistors have drains, respectively, and wherein said common intereconnection line is connected to the drains of said MOS transistors.