Patent ID: 8125815
Filing Date: 2012-02-28
Classification: G11C

Abstract:
1. A read-only memory bit cell that has two memory storage bit configurations, a logic level 1 configuration and a logic level 0 configuration, comprising in combination: a PMOS transistor having the source thereof maintained at a voltage V an NMOS transistor having the source thereof maintained at a voltage V wherein, when said read-only memory bit cell is configured in said logic level 1 configuration, the drain of said PMOS transistor is in electrical contact with a bit line and the drain of said NMOS transistor is unconnected and is, accordingly, not in electrical contact with said bit line such that when said PMOS transistor receives a voltage corresponding to a logic 0 on the gate thereof, said bit line is pulled up to a voltage corresponding to a logic level 1; wherein, when said read-only memory bit cell is configured in said logic level 0 configuration, the drain of said PMOS transistor is unconnected and is, accordingly, not in electrical contact with said bit line and the drain of said NMOS transistor is in electrical contact with said bit line such that when said NMOS transistor receives a voltage corresponding to a logic level 1 on the gate thereof, said bit line is discharged to a voltage corresponding to a logic level 0; and wherein said read-only memory bit cell includes only said PMOS transistor and said NMOS transistor.