Patent ID: 7245516
Filing Date: 2007-07-17
Classification: G06F

Abstract:
1. A layout method of an integrated circuit for reading data of a plurality of functional cells from a cell library stored in a storage device to place the functional cells on an integrated circuit in order to realize a circuit configuration stored in a storage device as an integrated circuit, comprising: a first step of reading data of a functional cell required for realizing the circuit configuration stored in said storage device from said cell library; a second step of calculating a value of decoupling capacitance required for the functional cell whose data are read from said cell library at said first step; a third step of creating a virtual cell which has the functional cell whose data are read from said cell library at said first step, and a decoupling capacitance placing area required for placing the decoupling capacitance whose value is calculated at said second step; a fourth step of repeating said first through third steps until data of all functional cells required for realizing the circuit configuration stored in said storage device are read from said cell library; a fifth step of placing all of the virtual cells created at said third step on the integrated circuit; and a sixth step of placing the decoupling capacitance in the decoupling capacitance placing area of each of all virtual cells placed on the integrated circuit at said fifth step.