Patent ID: 8159070
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening; a first metal post on said first contact point, wherein said first metal post comprises a third metal layer on said first contact point and a copper layer having a thickness between 3 and 100 micrometers on said third metal layer; a second metal post on said second contact point, wherein a pitch between said first and second metal posts is between 25 and 100 micrometers; and a second metallization structure on a top surface of said first metal post and on a top surface of second metal post, wherein said second metallization structure comprises a tin-containing layer over said first and second metal posts.