Patent ID: 6081021
Filing Date: 2000-06-27
Classification: H01L

Abstract:
An integrated circuit apparatus including a first device and a second device, the first device comprising:a first conductive interconnect;a first interlevel dielectric disposed upon the first conductive interconnect and having an upper surface and a first opening extending through the first interlevel dielectric to the first conductive interconnect, the first opening defined by sidewalls and a bottom;an insulating layer coating the bottom of the first opening;a first conductor disposed upon the insulating layer filling the first opening wherein the first conductor is planarized to the upper surface of the first interlevel dielectric;a second interlevel dielectric disposed upon the first interlevel dielectric and upon the first conductor, the second interlevel dielectric having a second opening extending through the second interlevel dielectric to the first conductor in the first opening;a second conductor filling the second opening; andthe second device comprising:a second conductive interconnect wherein the first interlevel dielectric is disposed upon the second conductive interconnect and has a third opening extending through the first interlevel dielectric to the second conductive interconnect, the third opening having sidewalls, a bottom, a third opening width, and a third opening depth; anda trench in the first interlevel dielectric corresponding to the third opening having a width greater than the third opening width and a depth less than the third opening depth wherein the trench and the third opening are filled with the first conductor planarized to the upper surface of the first interlevel dielectric.