Patent ID: 6043436
Filing Date: 2000-03-28
Classification: H01L

Abstract:
An integrated circuit chip comprising:a substrate;positioned on said substrate, a plurality of contiguous layers M0, M1, M2, M3, M4, M5, and M6 placed one on top of the other, each of said plurality of said layers comprising a plurality of uniformly parallel lines, characterized in thatsaid uniformly parallel lines in each of said layers are rotated with respect to said plurality of uniformly parallel lines in a first one of said layers by an angle a.sub.1, said angle a.sub.1 varying between at least two of said layers, wherein the value of said angle a.sub.1 is determined by said layer's distance from said first layer, and whereinsaid layer M5 is rotated 45.degree. compared with said layer M6, said layer M4 is rotated 90.degree. compared with said layer M5, said layer M3 is rotated 135.degree. compared with said layer M4, said layer M2 is rotated 90.degree. compared with said layer M3, said layer M1 is rotated 90.degree. compared with said layer M2, and said layer M0 is rotated 90.degree. compared with said layer M1.