Patent ID: 9143152
Filing Date: 2015-09-22
Classification: H03M,H04N

Abstract:
1. An analog-to-digital (AD) conversion circuit comprising: a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with passage of time, the comparison unit being configured to compare voltages of the analog signal and the reference signal, the comparison unit being configured to output a first comparison signal at a first timing at which the voltages of the analog signal and the reference signal have a predetermined relationship; a signal generation unit configured to output a second comparison signal for switching a logic state at a second timing at which a predetermined time has elapsed from the first timing, the signal generation unit being configured to output a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit configured to output an enable signal at least between a timing relating to a comparison start of the comparison unit and the second timing; a clock generation unit configured to output first to n a latch unit that includes first to n a count unit configured to perform a count operation based on a signal from the output terminal of the n each of first to (n−k) each of (n−k+1) each of the first to n