Patent ID: 8765579
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A processing method for a semiconductor wafer having a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on a front side of said semiconductor wafer and a peripheral marginal area surrounding said device area, said processing method comprising: a protective tape attaching step of attaching a protective tape to the front side of said semiconductor wafer; a grinding step of grinding the back side of said semiconductor wafer in a central area corresponding to said device area to thereby form a circular recess and an annular projection surrounding said circular recess after performing said protective tape attaching step; a chip stacked wafer forming step of providing a plurality of semiconductor device chips on a bottom surface of said circular recess of said semiconductor wafer at the positions respectively corresponding to said semiconductor devices of said semiconductor wafer in a condition where the device surface of each semiconductor device chip comes into contact with the bottom surface of said circular recess and filling a filler into said circular recess until reaching a depth corresponding to a finished thickness of each semiconductor device chip to thereby form a chip stacked wafer after performing said grinding step; a thickness reducing step of grinding the back side of said chip stacked wafer to thereby reduce the thickness of each semiconductor device chip to said finished thickness after performing said chip stacked wafer forming step; and a through electrode forming step of forming a through electrode in each semiconductor device of said semiconductor wafer after performing said thickness reducing step.