Patent ID: 6067271
Filing Date: 2000-05-23
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of banks ranged in a y-direction each comprising:a plurality of sub-arrays arranged in matrix;a global I/O (Input/Output) line pairs extending in the y-direction traversing the banks and each shared by a certain number of columns of the sub-arrays;a plurality of read/write amplifiers, each being connected with one of the global I/O-line pairs;local I/O-line pairs extending in an x-direction perpendicular to the y-direction and each traversing sub-arrays of each row of the certain number of columns;column-selection lines extending in the y-direction traversing the sub-arrays of columns of each of the banks for transmitting column-selection signals for selecting bit-line pairs to be connected to the local I/O-line pairs;I/O switch lines for transmitting a column-activating signal for connecting the global I/O-line pairs to the local I/O-line pairs of a row of the sub-arrays to be accessed;a row-activating signal for activating the row of the sub-arrays to be accessed; andAND logic, the AND logic having as inputs the column-activating signal and the row-activating signal, an output of the AND logic providing a signal controlling connection of the local I/O-line pairs to the global I/O line pairs;wherein each of the I/O switch lines extends along with a respective one of the global I/O-line pairs in each of the banks.