Patent ID: 8492221
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for fabricating a power semiconductor device, comprising: providing a substrate of a first conductivity type; forming a semiconductor layer of a second conductivity type on the substrate; forming a hard mask pattern on the semiconductor layer, the hard mask pattern having at least an opening exposing a portion of the semiconductor layer; performing a first etching, via the opening, to form a first recess in the semiconductor layer, wherein the first recess has a depth that is smaller than a thickness of the semiconductor layer; performing a first ion implantation process to vertically implant first dopants into a bottom of the first recess via the opening, thereby forming a first doping region wherein the first doping region is located within the semiconductor layer; and performing a second etching to etch through the first doping region, thereby forming a second recess extending through the first doping region, wherein a PN junction is formed between the first doping region and the semiconductor layer along a sidewall of the second recess.