Patent ID: 8921792
Filing Date: 2014-12-30
Classification: G01J,H01L

Abstract:
1. A method for manufacturing a vertically stacked thermopile comprising: providing a semiconductor substrate; etching a first cavity in the semiconductor substrate; depositing, in the first cavity, a plurality of vertically ascending planar layers alternating between first and second layers, said first layers being formed from a semiconductor material having a positive seebeck coefficient and said second layers being formed from a semiconductor material having a negative seebeck coefficient, said stack further including a plurality of insulating layers between said first and second layers; depositing a first plurality of metal contacts creating a series connection between the first and second semiconductor layers, at least one of said plurality of metal contacts extending from the first layer to the second layer in the vertically upward direction; depositing a first insulation layer over the plurality of vertically ascending planar layers and the first plurality of metal contacts, wherein at least a portion of the first plurality of metal layers is not covered by the first insulation layer; depositing a second plurality of metal contacts on the first insulation layer, wherein at least a portion of the second plurality of metal contacts connects to the at least a portion of the first plurality of metal layers that is not covered by the first insulation layer; etching a portion of the first insulation layer, a portion of the plurality of vertically ascending planar layers, and a portion of the plurality of insulating layers to form a thermopile strip; depositing a second insulation layer on the second plurality of metal contacts, the first insulation layer, and the thermopile strip, wherein at least a portion of the second plurality of metal contacts is not covered by the second insulation layer; depositing an absorptive material on at least a portion of the semiconductor substrate and at least a portion of the thermopile strip; and etching a second cavity in the semiconductor substrate, wherein the second cavity is positioned below the absorptive material and at least a portion of the thermopile strip.