Patent ID: 6094668
Filing Date: 2000-07-25
Classification: G06F,H03M

Abstract:
A microprocessor, comprising:an execution unit coupled to receive a first pair of floating point input values, wherein the execution unit comprises:a close data path configured to perform a first effective subtract operation on said first pair of floating point input values assuming said first pair of floating point input values have an absolute exponent difference less than or equal to one, wherein said close data path comprises:a first arithmetic unit configured to generate a first difference value and a second difference value, wherein said first difference value is equal to a difference of mantissa portions of said first pair of floating point input values, and wherein said second difference value is equal to said first difference value plus one;a first multiplexer unit coupled to receive said first output value and said second output value, wherein said first multiplexer unit is configured to select either said first output value or said second output value as a preliminary subtraction result according to a close path selection signal;a logic unit configured to calculate a guard bit, a sticky bit, and a round bit based on said first pair of floating point input values; anda first selection unit configured to generate said close path selection signal using one or more of the following: the guard bit, the sticky bit, the round bit, and a least significant bit and a next-to-least significant bit from at least one of said first and second difference values.