Patent ID: 6562645
Filing Date: 2003-05-13
Classification: G02F

Abstract:
A method of fabricating FFS-LCD comprising the steps of:forming a gate bus line and a common electrode line on a lower substrate in parallel with each other; forming a gate insulating layer on the lower substrate; forming a counter electrode on the gate insulating layer to overlap with a predetermined part of the common electrode line; depositing a metal layer on the resulting lower substrate and then selectively patterning the metal layer, thereby forming a source region, a drain region and a contacting part connecting the counter electrode to the exposed common electrode line; depositing a protective layer on the lower substrate obtained after formation of the source, the drain and the contacting part; selectively etching the protective layer to expose a predetermined part of the drain; and forming a pixel electrode on the protective layer to form a field with the counter electrode, the pixel electrode being in contact with the drain.