Patent ID: 6429478
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A semiconductor memory device comprising:(a) a semiconductor substrate on which a circuit is formed; (b) a first interlayer insulating film formed on said semiconductor substrate; (c) a plurality of bit lines formed on said first interlayer insulating film, a contact hole being formed through said first interlayer insulating film between adjacent bit lines such that said contact hole reaches said semiconductor substrate; (d) a second interlayer insulating film formed on said first interlayer insulating film such that said second interlayer film covers said bit lines therewith; (e) a first electrically conductive layer buried in said contact hole, a recess being formed through said second interlayer insulating film between adjacent bit lines such that said recess reaches said first electrically conductive layer; (f) a second electrically conductive layer covering a bottom and an inner sidewall of said recess therewith such that said second electrically conductive layer is electrically isolated from said bit lines; and (g) an insulating film covering upper and side surfaces of said bit lines therewith, said insulating film formed around a first bit line and said insulating film formed around a second bit line adjacent to said first bit line both partially defining a part of said inner sidewall of said recess, said bottom of said recess being extensive between said insulating films.