Patent ID: 8574991
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A method, comprising: performing a non-zero tilt angle implantation process to form at least one of asymmetric counter doped regions and asymmetric shallow extension regions of drain and source regions of a transistor in a semiconductor region, said semiconductor region having a gate electrode formed thereabove; after forming said at least one of asymmetric counter doped regions and asymmetric extension regions, asymmetrically forming a spacer element on sidewalls of said gate electrode, wherein asymmetrically forming said spacer element comprises depositing a spacer material, covering said spacer material at one of a drain side and a source side of said transistor by an implantation mask, implanting an implantation species so as to modify an etch behavior of an exposed portion of said spacer material and etching said spacer material after removing said implantation mask; and forming deep drain and source areas of said drain and source regions using said asymmetrically formed spacer element.