Patent ID: 6583491
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A microelectronic fabrication comprising:a substrate; a first dielectric layer formed over the substrate, the first dielectric layer having formed exposed therein a pair of patterned first conductor layers such that a series of upper surfaces of the first dielectric layer and the pair of patterned first conductor layers is planar; a multilayer patterned dielectric layer formed over the first dielectric layer, the multilayer patterned dielectric layer having a capacitor structure formed interposed between a pair of dielectric layers within the multilayer dielectric layer, the capacitor structure being registered with respect to a first one of the pair of patterned conductor layers, the multilayer patterned dielectric layer having a first via interposed between the capacitor structure and the first one of the pair of patterned conductor layers and a second via formed completely through the multilayer dielectric layer to access a second of the pair of patterned conductor layers; and a first conductor contact stud layer formed within the first via and a single layer second conductor stud layer formed within the second via.