Patent ID: 6177721
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A chip stack type semiconductor package comprising:a lower chip having a center pad formation surface defined at a bottom thereof;an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof,both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip;leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip opposite to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip, to enclose opposite sides of the upper and lower chips;conductive connection members for electrical connection of the inner lead portions of the leads with the center pads of the lower chip and the upper chip;a molded body for encapsulating entire structure except the outer lead portions; and,solder balls, external power source connection terminals, attached to bottoms of the outer lead portions.