Patent ID: 8331147
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner, a first physical page being configured by a first bit of a plurality of the memory cells selected by one of the first lines, and a second physical page being configured by a second bit of the plurality of the memory cells selected by the one of the first lines, the second bit being different from the first bit; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches, wherein, during a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored, and when, of the plurality of unit data included in one of the write data, a certain one of the unit data is assumed to be a first unit data, the unit data inputted into the column selection unit following said first unit data is assumed to be a second unit data, and the unit data inputted into the column selection unit after the second unit data is assumed to be a third unit data, the first unit data is stored in the first physical page, the second unit data is stored in the second physical page, and the third unit data is stored in the first physical page.