Patent ID: 6104234
Filing Date: 2000-08-15
Classification: G05F

Abstract:
A substrate voltage generation circuit for a semiconductor memory device, the circuit comprising:a substrate voltage detector for detecting a substrate voltage VBB;a first inverter for inverting an output from said substrate voltage detector;a second inverter for inverting an output from said first inverter;an oscillator for oscillating in response to an output voltage from said second inverter; anda substrate voltage generator driven by an oscillation frequency from said oscillator for applying a substrate voltage to said substrate voltage detector;a substrate voltage generator driven by an oscillation frequency from said oscillator for applying a substrate voltage to said substrate voltage detector;said first inverter having a plurality of transistors, channels in said transistors being configured with ratios of width to length, respectively, that collectively produce a threshold voltage for said first inverter that varies substantially in accordance with a variation .DELTA.VCC of a supply voltage VCC so as to minimize variations in said substrate voltage VBB relative to .DELTA.VCC.