Patent ID: 6638843
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A method for forming a gate structure for a semiconductor device, comprising:forming an opening using a directional etching process in an insulating layer over a semiconductor substrate; growing a gate oxide at the bottom of said opening; forming a conductive gate comprising polysilicon in said opening on said gate oxide, said conductive gate having a thickness within the range of approximately 500 to 1500 Angstroms; forming a silicide layer in said opening on said conductive gate by a salicide method, said silicide layer having a thickness within the range of approximately 200 to 500 Angstroms, said salicide method comprising: depositing a refractory metal capable of forming a silicide over said polysilicon gate; annealing said refractory metal such that refractory metal in contact with said polysilicon is converted to a conductive silicide; and selectively etching to remove refractory metal not converted to conductive silicide; forming an etch protective cap within said opening over a top surface of said silicide layer, said cap being sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure; subsequently etching away said insulating layer; and forming an insulating spacer on side walls of said gate structure.