Patent ID: 6392461
Filing Date: 2002-05-21
Classification: H03K,H04B

Abstract:
A clock modulator comprising:a delay circuit having delay elements of plural stages which are connected in series with each other from a first stage to a final stage, wherein each of the delay elements outputs an output pulse delayed from an input pulse by a phase delay time &tgr;; and a selection circuit sequentially selecting the output pulse outputted from each of the delay elements of the plural stages; wherein with respect to a fundamental clock pulse inputted to the delay element of the first stage, a phase variation amount of the output pulse from the delay element of the first stage and a phase variation amount of the output pulse from the delay element of the final stage are near Â±45Â° when a phase of the output pulse from the delay element at a center position of the delay elements of the plural stages is made a reference.