Patent ID: 6384434
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A master-slice semiconductor device in which a lot of transistors are formed on a semiconductor substrate, transistors selected from the lot of transistors being connected by wiring, the master-slice semiconductor device comprising:an input/output cell region disposed in a peripheral part of the semiconductor device; and an internal cell region disposed inside the input/output cell region, wherein a plurality of output cells are disposed in the input/output cell region; wherein an output terminal and a plurality of transistors are disposed in each of the output cells, with at least on transistor selected from the plurality of transistors being connected to the output terminal; wherein each of the plurality of transistors comprises: a gate electrode formed on the semiconductor substrate through a gate-insulating film; and two diffusion regions formed at the semiconductor substrate on both sides of the gate electrode; and wherein one of the diffusion regions of at least one of the plurality of transistors is divided into a plurality of divisional diffusion regions in a direction of the width of the gate electrode.