Patent ID: 6420752
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a multi-layer structure disposed on an active region on said semiconductor substrate, said multi-layer structure having a top passivation layer and sidewalls; a sidewall spacer disposed over said sidewalls and around said multi-layer structure; a source region and a drain region disposed on said active region adjacent said sidewall spacer; a liner oxide layer over said semiconductor substrate, including said multi-layer structure, said source region and said drain region, in contact with said sidewall spacer, said source region and said drain region, wherein boron and phosphorus are absent from said liner oxide layer; a dielectric layer disposed over said liner oxide layer, wherein said dielectric layer includes a material selected from a group consisting of boron, phosphorus, and a combination thereof; and a contact extending through the dielectric layer and the liner oxide layer in contact with the top passivation layer and the sidewall spacers.