Patent ID: 6847058
Filing Date: 2005-01-25
Classification: H01L

Abstract:
1. A semiconductor device having a plurality of polygonal cells connected in parallel over a main surface of a semiconductor substrate, the semiconductor device comprising: the semiconductor substrate of a first conductive type; a MOS gate comprising a gate insulating film formed selectively over the main surface of the semiconductor substrate, a gate electrode formed over the gate insulating film, and an insulating film which covers the gate electrode and the gate insulating film; a source contact hole formed in a region not being covered with the insulating film, of the semiconductor substrate; a base region of a second conductive type formed over the main surface of the semiconductor substrate, superimposed over the source contact hole and extending to below the MOS gate; a source region of a first conductive type formed over the main surface of the semiconductor substrate, extending to below the MOS gate from an inside portion of the source contact hole and forming a channel between it and an outer peripheral edge of the base region; and a source electrode formed over the source contact hole and the MOS gate and connected electrically to the source region and the base region, wherein the gate insulating film, the gate electrode and the insulating film are of a mesh structure for forming the cells over the main surface of the semiconductor substrate, and the regions where the gate insulating film, the gate electrode and the insulating film are not formed are polygonal in shape, the polygons being arranged in a quadrangular array such that centers of four adjacent polygons arranged in order longitudinally and transversely over the main surface of the semiconductor substrate are positioned respectively at vertices of a quadrangle, wherein the source region is not present below the gate electrode at each corner of each said polygon, the source region is offset by a predetermined distance from the gate electrode, and wherein in the source region extending along each side of each said polygon, the width b of the source region extending over both inside and outside of a side of the source contact hole is longer than the width a of an inner end of the source region exposed to the source contact hole and extending along said side of the contact hole, and the width c of an outer end of the source region which confronts the gate electrode is longer than the width a of the inner end of the source region.