Patent ID: 8716802
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A semiconductor device structure, comprising: a substrate, comprising a resistor region, a metal-oxide-semiconductor (MOS) transistor region, and an electrostatic discharge (ESD) protection device region; a resistor, disposed on the substrate within the resistor region, the resistor comprising a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate; a first gate structure, disposed on the substrate within the MOS transistor region, the first gate structure comprising the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate, wherein the height of the resistor and the height of the first gate structure are equivalent and a second gate structure disposed on the substrate within the ESD protection device region, the second gate structure comprising the first dielectric layer, the metal layer, the second dielectric layer, and the semiconductor layer sequentially stacked on the substrate, wherein the second dielectric layer is disposed on a portion of the metal layer, and the semiconductor layer is disposed on the second dielectric layer and the metal layer.