Patent ID: 6188258
Filing Date: 2001-02-13
Classification: H03L,H04N

Abstract:
Clock generating circuitry comprising:first frequency multiplying means for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for outputting the frequency-multiplied clock as a first clock signal, said first frequency multiplying means having a first oscillator means for oscillating at a first frequency;frequency dividing means for dividing the frequency of the frequency-multiplied clock output by said first frequency multiplying means by 227, and for outputting the frequency-divided clock; andsecond frequency multiplying means for multiplying the frequency of the frequency-divided clock from said frequency dividing means by 128, and for outputting the frequency-multiplied clock as a second clock signal, said second frequency multiplying means having a second oscillator means for oscillating at a second frequency which is less than said first frequency.