Patent ID: 9069652
Filing Date: 2015-06-30
Classification: G06F,G11C

Abstract:
1. An integrated level shifting latch circuit for receiving an input signal in a first voltage domain and generating an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting latch circuit comprising: data retention circuitry operating in said second voltage domain and configured to operate in a transparent phase where a data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is retained irrespective of any change in the input signal during the latching phase, and that retained data value forms said output signal; control circuitry configured to receive a clock signal and to control the data retention circuitry to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal; writing circuitry configured during the transparent phase to write said data value into said data retention circuitry by controlling a voltage of at least one internal node of the data retention circuitry dependent on the input signal; and contention mitigation circuitry configured to receive said input signal and, during said transparent phase, to reduce a voltage drop across at least one component within the data retention circuitry, thereby assisting said writing circuitry in altering the voltage of said at least one internal node during the transparent phase.