Patent ID: 6469949
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A fuse latch array system for storing fuse data for column redundancy applications for an embedded DRAM (eDRAM) system, the fuse latch array system comprising:a plurality of fuse latch elements arranged in an array and having a plurality of bitlines traversing there through; an data input line coupled to at least one of the plurality of fuse latch elements for inputting fuse data to the fuse latch array for storage therein; a plurality of data connection lines each connecting adjacent fuse latch elements of the plurality of fuse latch elements for passage of fuse data there between; and at least one clock signal line for inputting at least one clock signal to the fuse latch array for shifting fuse data within adjacent fuse latch elements via the plurality of data connection lines and within each of the plurality of fuse latch elements.