Patent ID: 7601599
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating film pattern above a semiconductor substrate, said first insulating film including at least a first portion with a first width, a second portion with a third width, and a third portion with a fifth width, the second portion being separated from said first portion by a first space with a second width, and the third portion being separated from said second portion by a second space with a fourth width; selectively forming a first impurity diffusion layer in a portion of said semiconductor substrate located at least below said first space by conducting ion implantation of impurities into said semiconductor substrate by using at least said first insulating film pattern as a mask, said first impurity diffusion layer self-aligned with said first insulating film pattern and having a width defined by said second width; selectively forming a second impurity diffusion layer below said second space, said second impurity diffusion layer being self-aligned with said first insulating film pattern and having a width defined by said fourth width; defining a channel region below said second portion, said channel region having a channel length defined by said third width by conducting said ion implantation of impurities; forming a gate electrode above said semiconductor substrate, said gate electrode including a functional portion and nonfunctional portions, the functional portion having a first edge defined by an edge of said first portion and a second edge defined by an edge of said third portion, the functional portion being overlapped with said first impurity diffusion layer in a self alignment fashion and being continuously formed on a gate insulating film, and the nonfunctional portions being located above and separated from said gate insulating film through said first portion and said third portion, respectively; selectively forming (a) a third impurity diffusion layer that is at least continuously formed below said first portion and in contact with an edge of said first impurity diffusion layer and (b) a fourth impurity diffusion layer that is at least continuously formed below said third portion and in contact with said second impurity diffusion layer, by implanting impurity ions into said semiconductor substrate, after said gate electrode is formed, by penetrating said impurity ions into said first portion and said third portion in an oblique direction by using said gate electrode as a mask while said semiconductor substrate is rotated; and eliminating said second portion, wherein said gate electrode is continuously formed out from said first edge and said second edge of said functional portion, and wherein said second impurity diffusion layer formation step and said channel region definition step are performed at the same time as said first impurity division layer is formed by conducting said ion implantation of impurities.