Patent ID: 7391240
Filing Date: 2008-06-24
Classification: H03K

Abstract:
1. A clock anomaly detection circuit comprising: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monitoring clock that is synchronized with the target clock, and to measure an H level time with and an L level time width; a second time width measurement unit configured to obtain values of the divided target clock using falling edges of the monitoring clock, and to measure an H level time with and an L level time width; and an anomaly determination unit configured to determine that the target clock is abnormal when an anomaly is detected in the H level time width or the L level time width measured in the first time width measurement unit and when an anomaly is detected in the H level time width or the L level time width measured in the second time width measurement unit.