Patent ID: 6337832
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock signal, comprising:a memory cell array including a plurality of memory cells arranged in a matrix; a control circuit controlling an operation of said synchronous semiconductor memory device; a first internal synchronizing signal generation circuit providing a first internal clock signal in synchronization with said external clock signal and of a frequency higher than the frequency of said external clock signal; a second internal synchronizing signal generation circuit providing a second internal clock signal in synchronization with said external clock signal; an address signal input circuit receiving said address signal in synchronization with said second internal clock signal; a control signal input circuit receiving said control signal in synchronization with said second internal clock signal; a memory cell select circuit selecting said memory cell according to said address signal; a plurality of data input/output nodes to which write data to said memory cell array or readout data from said memory cell array are applied; and an interface circuit provided between memory cells selected by said memory cell select circuit and said data input/output nodes to output said readout data, said interface circuit receiving said readout data from said memory cell array in synchronization with said second internal clock signal in a first operation mode, and receiving said readout data from said memory cell array in synchronization with said first internal clock signal in a second operation mode.