Patent ID: 8020055
Filing Date: 2011-09-13
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a substrate; a flash memory array fabricated on the substrate; a plurality of bond pads fabricated on the substrate; a plurality of boundary scan cells fabricated on the substrate each in electronic communication with an associated one of the bond pads, wherein each boundary scan cell of the plurality of boundary scan cells is configured to transmit test data to the associated bond pad so as to test an electrical connection between the associated bond pad and the flash memory array; and a scanning element associated with at least one of the plurality of boundary scan cells, wherein the scanning element and a comparator are configured to verify the contents of the memory cells; wherein the integrated circuit is configured to store test data within the memory array, retrieve the test data as result data at the pins, and indicate a connectivity error within the flash memory array if result data from a path through the flash memory array does not correspond to the test data.