Patent ID: 6813754
Filing Date: 2004-11-02
Classification: G06F

Abstract:
A method of mapping a plurality of circuit elements onto a plurality of configurable logic blocks (CLBs) in a programmable logic device (PLD), comprising:generating a mapping of the circuit elements to the GLBs in the PLD; selecting a critical path in the PLD corresponding to the mapping, wherein: the critical path comprises a first node in a first GLB in the PLD; and the first CLB further comprises one or more other nodes; and changing node assignment of the first node from a current location to a different location without changing node assignment of at least one other node in the first CLB, wherein: the change in node assignment results in a change of circuit performance; the different location falls within an area adjacent to the current location; the first node is a terminal node; and the area is a circle centered at a connecting node having a radius corresponding to a distance measure between the terminal and connecting nodes.