Patent ID: 8125064
Filing Date: 2012-02-28
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a generally quadrangular substrate defining a central die mounting area and at least four peripheral edge segments, the substrate comprising a patterned metal layer and an insulation layer formed on at least a portion of the patterned metal layer, the substrate defining a plurality of holes which are segregated into at least four sets, the holes of each set being located between the central die mounting area and a respective one of the peripheral edge segments such that the holes of the sets are generally arranged in a pattern of concentric rings which at least partially circumvent the central die mounting area; a plurality of lands disposed within respective ones of the holes of the substrate; at least one semiconductor die mounted to the substrate: at least one electrical coupling member electrically connecting the semiconductor die to at least one of the lands; and an encapsulant covering at least the semiconductor die and the electrical coupling member.