Patent ID: 6470486
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A technology selection process in an electronic design automation system, comprising the steps of:partitioning an original circuit design into a set of corresponding logic trees; ordering said set of corresponding logic trees into an ordered linear list such that each tree-T that drives another ordered tree precedes said other ordered tree, and such that each ordered tree that drives said tree-T precedes said tree-T; sweeping forward in said ordered linear list while computing a set of Pareto-optimal load/arrival curves for each of a plurality of net nodes that match a technology-library element; and sweeping backward in said ordered linear list while using said set of Pareto-optimal load/arrival curves for each of said net nodes and a capacitive load to select a best one of said technology-library elements with a shortest signal arrival time; wherein, only net nodes that correspond to a gate input are considered, and any capacitive loads are predetermined.