Patent ID: 6768341
Filing Date: 2004-07-27
Classification: G06F

Abstract:
A computer system comprising:a high speed processing device, a low speed processing device, and a synchronizing interface device coupled between said high and said low speed processing devices, said synchronizing interface device including a read/write assembly coupled between said high and said low speed processing devices, and a delay counting assembly coupled between said high and said low speed processing devices and said read/write assembly for suitably communicating between said high and said low speed processing devices, and said synchronizing interface device including an AND gate having a first input coupled to said high speed processing device, and having a second input, and having an output coupled to said low speed processing device, and said synchronizing interface device including an OR gate having an output coupled to said second input of said AND gate, a first input coupled to said delay counting assembly, and a second input coupled to said high speed processing device.