Patent ID: 6420251
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method for fabricating an integrated circuit comprising the steps of:providing a first dielectric material layer; depositing a first conductive material layer onto said first dielectric material layer; patterning said first conductive material layer by removing preselected portions of said first conductive material layer thereby exposing portions of said first dielectric material layer and creating a first conductive pattern from said first conductive material layer; depositing a non-planarizing second dielectric material layer comprising silicon dioxide over said first conductive pattern and exposed portion of said first dielectric material layer; depositing a benzocyclobutene planarizing material layer over said non-planarizing second dielectric material layer forming a substantially planar top surface; and, etching away substantially all of said planarizing material layer and portions of said non-planarizing second dielectric material layer using a mixture of CHF3 and CF4 compounds and oxygen in a reactive ion etcher so that said substantially planar top surface is maintained during etching until only a preselected amount of said second dielectric material covers said first conductive pattern and said top surface of said second dielectric material is substantially planar.