Patent ID: 7227920
Filing Date: 2007-06-05
Classification: H03K,H03L,H04L

Abstract:
1. A circuit for controlling a duty cycle and jitter of a clock signal, comprising: an input node for receiving the clock signal; a plurality of serially connected delay elements coupled to the input node, said plurality of delay elements creating a delayed clock signal; a phase detector having a first input coupled to said clock signal and a second input coupled to an output of said plurality of delay elements for receiving a delayed clock signal therefrom, said phase detector operating so as to generate an error signal that is indicative of a phase difference between said clock signal and said delayed clock signal, said error signal being coupled to at least a first one of said delay elements for controlling said at least one delay element for minimizing the phase difference between said clock signal and said delayed clock signal; a first divider circuit having an input coupled to said clock signal; a second divider circuit having an input coupled to an output of said first one of said plurality of delay elements for receiving the delayed clock signal therefrom; a gate having inputs coupled to outputs of said first and second divider circuits and an output; and an output node coupled to the output of the gate far outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is controlled so as to provide a predetermined processed clock signal duty cycle.