Patent ID: 6706592
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of forming an array of semiconductor memory cells, comprising the steps of:forming a plurality of spaced apart isolation regions on the substrate of a first conductivity type which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; forming a plurality of spaced apart blocks of conductive material in each of the active regions, wherein each of the conductive material blocks is disposed over and insulated from the substrate; forming a plurality of spaced apart first trenches in a first material in each of the active regions, wherein the conductive material blocks are disposed in the first trenches; etching away a top portion of the conductive material block in each of the first trenches to form sloping portions of the conductive material block therein that terminate in edges extending along sidewalls of the first trenches; removing the first material; forming a plurality of control gates of conductive material each disposed adjacent to and insulated from one of the conductive material blocks; and forming a plurality of spaced apart first and second regions in the substrate in each of the active regions that have a second conductivity type, with channel regions of the substrate defined between the first and second regions, wherein each of the control gates is disposed over and insulated from a portion of one of the channel regions.