Patent ID: 6511857
Filing Date: 2003-01-28
Classification: G01R

Abstract:
A method of manufacturing a semiconductor apparatus comprising:a device forming process for forming a multiplicity of devices on a wafer; a probing test process for applying a probing test to the wafer (a subject to be tested) on which said multiplicity of devices are formed; and a burn-in test process for applying a burn-in test to the wafer on which said multiplicity of devices are formed or a chip thereof (a subject to be tested), wherein in said probing test process and/or said burn-in test process, a conductive projection is provided on a main surface, and there is included a process for pressing said projection of a test structure in which said projection and a pad provided on a surface opposite to said main surface are electrically connected to a desired position of said subject to be tested, and wherein said main surface is a main surface of a substrate, and said substrate has a first portion and a second portion which is thinner than said first portion, said conductive projection being placed in an area of said second portion, and said second poltion is deformed when pressing said projection.