Patent ID: 6604161
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A computer system comprising:one or more Peripheral Component Interconnect (PCI) devices for generating interrupts; an interrupt line for conveying the interrupts generated by the PCI devices; a bridge device, coupled to the interrupt line, for receiving a first interrupt from the PCI devices via the interrupt line, wherein, when the bridge device receives the first interrupt, the bridge device generates a first interrupt write packet; and one or more microprocessors communicatively coupled to the bridge device, wherein the one or more microprocessors includes a first microprocessor, wherein the first microprocessor receives the interrupt write packet from the bridge device and initiates an interrupt routine associated with the first interrupt; and wherein the bridge device generates a second interrupt write packet if an interrupt exists on the interrupt line upon completion of the interrupt routine associated with the first interrupt.