Patent ID: 7414905
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: a memory to be tested that substitutes a memory cell to be written on and read out with a redundancy memory cell when the address of the memory cell to be written on and read out matches a defective memory cell address; a nonvolatile memory element that stores the defective memory cell address detected by testing the memory, and supplies the defective memory cell address to the memory; a readout circuit that reads out the defective memory cell address from the nonvolatile memory element; an address retention circuit that retains the defective memory cell address read out by the readout circuit; an address generation circuit that selectively generates, based on the defective memory cell address retained in the address retention circuit, an address of the memory cell substituted by the redundancy memory cell; and a control circuit that selectively tests the redundancy memory cell, based on the address generated by the address generation circuit, by performing a retest on whether the substitution is successful or not.