Patent ID: 8230257
Filing Date: 2012-07-24
Classification: G06F,G11C

Abstract:
1. A solid-state memory device comprising: a primary power source configured and arranged to provide primary power; a secondary power source configured and arranged to provide secondary power; a secondary switch that includes a transistor located between the secondary power source and an operating power circuit for the solid-state memory device, the secondary switch configured and arranged to enable the transistor in response to a secondary enable signal; a power controller configured and arranged to provide the primary power to the operating power circuit and, in response to problems with the primary power source, provide the secondary power to an operating power circuit by enabling the secondary switch; a solid-state memory circuit configured and arranged to use power from the operating power circuit as a primary source of power when accessing stored data and to retain data in the absence of power being provided by the operating power circuit; a memory controller configured and arranged to facilitate the access to the stored data and, in response to problems with the primary power source, complete pending writes to the solid-state memory circuit; and a timing circuit configured and arranged to substantially delay full enablement of the secondary switch by operating the transistor in a linear mode to partially enable the switch over a delay time period.