Patent ID: 6472274
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method for forming a MOSFET device, comprising the steps of:a) depositing a masking layer over a planar surface of a silicon substrate; b) patterning and etching through said masking layer into said silicon substrate to form first and second trenches defining a MOSFET device active area; c) selectively etching back said masking material to expose regions of un-etched silicon at border regions of said MOSFET device active area, said border regions defining MOSFET device channel edges; d) selectively doping said exposed border regions to form drain and source portions each including a respective MOSFET channel edge; e) filling said trench with an electrically insulating material and removing remaining masking layer; f) forming a MOSFET gate on and in un-etched areas of said MOSFET device active area, wherein a said MOSFET device exhibits reduced or eliminated threshold leakage current in low-voltage applications.