Patent ID: 7797728
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A computer system comprising: a central processing unit (CPU) having: a first thread having first associated thread identification (ID); and a second thread having second associated thread ID; and a chipset coupled to receive access requests, from the CPU, to access requested resources, the chipset to examine a thread ID included with each of the access requests to determine which thread is requesting access to the requested resources, wherein the first thread is an unrestricted thread that is provided full access to data and the second thread is a restricted thread that is provided limited access to data, wherein at least one of the first or second threads is to provide a respective processor function to implement an operating system, wherein the chipset is to operate in a plurality of modes comprising: said each of the access requests to be first transferred to the unrestricted thread to determine whether a request is to be passed to the restricted thread or the first thread and the second thread to operate independently to prevent the restricted thread from muting the unrestricted thread; and a thread checker to examine the thread ID and determine whether the corresponding thread is to access the requested resources.