Patent ID: 6653951
Filing Date: 2003-11-25
Classification: H03M

Abstract:
A circuit for protecting the minimum run length in RLL code, the circuit operating in before, turning, and after states of an EFM signal to protect the minimum run length in RLL code, the circuit comprising:three state processors, each of which including a decision bit, an invalid bit, a metric bit, and a path bit array, and operating according the three states of before, turning and after, respectively; a metric computing unit for computing metrics of the EFM signal with respect to the three states of before, turning and after; a timing control unit for generating control signals that are transferred to the three state processors and the metric computing unit according to the EFM signal; and an operation unit for controlling the decision bit, the invalid bit, the metric bit, and the path bit array of the state processors, and generating correct output signals according to the control signals from the timing control unit and the metrics of the three states from the metric computing unit.