Patent ID: 7582528
Filing Date: 2009-09-01
Classification: H01L

Abstract:
1. A method of fabricating a flash memory device, the method comprising: forming an interlayer dielectric layer over a semiconductor substrate, wherein the semiconductor substrate comprises a cell region and a peripheral region; etching the interlayer dielectric layer to form first contact holes, wherein the first contact holes expose junction regions of the cell region; forming a first contact plug within each first contact hole; etching a top surface of the interlayer dielectric layer such that portions of the first contact plugs having the largest width are exposed; etching the interlayer dielectric layer to form a second contact hole, wherein the second contact hole exposes a junction region of the peripheral region; forming a second metal layer over the first contact plugs and the interlayer dielectric layer such that the second contact hole is gap-filled; and forming a second contact plug within the second contact hole by removing the second metal layer and the exposed portions of the first contact plugs over the interlayer dielectric layer.