Patent ID: 6674314
Filing Date: 2004-01-06
Classification: H03K,H03L

Abstract:
An interpolating circuit, receiving first and second signals, for generating an output signal having a phase corresponding to a value obtained by dividing a phase difference between the first and second signals in accordance with a preset interior division ratio, said interpolating circuit comprising a waveform synthesis unit and a bias control unit;said waveform synthesis unit including: a first switch element inserted between a node connected to an output terminal from which the output signal is delivered, and a first power supply; means for placing said first switch element in an ON state when the first and second signals are both a first logic value; a first series circuit composed by serial connection of a first current source and a second switch element placed in the ON state when the first signal is a second logic value; and a second series circuit composed by serial connection of a second current source and a third switch element placed in the ON state when the second signal is the second logic value; said first series circuit and said second series circuit being connected in parallel with each other between the node connected to the output terminal and a second power supply; said bias control unit setting current values flowing through the first and second current sources of said waveform synthesis unit respectively to values conforming to the interior division ratio.