Patent ID: 7605421
Filing Date: 2009-10-20
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory element comprising: a semiconductor region of a first conductivity type that is formed in a plate-like form on a semiconductor substrate; a first insulating film that is formed on a first side face of the semiconductor region; a first charge accumulating layer that is formed on a face of the first insulating film opposite from the semiconductor region; a second insulating film that is formed on a second side face of the semiconductor region, and has a different equivalent oxide thickness from the first insulating film, the second side face being the opposite side from the first side face; a second charge accumulating layer that is formed on a face of the second insulating film opposite from the semiconductor region; a third insulating film that is provided so as to cover the first and second charge accumulating layers; a control gate electrode that is provided so as to cover the third insulating film; a channel region that is formed in a portion of the semiconductor region covered with the control gate electrode; and source/drain regions of a second conductivity type that are formed in portions of the semiconductor region on both sides of the channel region, the semiconductor region having a thickness smaller than twice the maximum thickness of a depletion layer determined by impurity concentration in the semiconductor region.