Patent ID: 6085077
Filing Date: 2000-07-04
Classification: H03H,H04B

Abstract:
A hardware efficient digital channelized receiver comprising:frequency converter means connected to a radio frequency input signal source for converting said input signals to signals of a lower intermediate frequency;analog-to-digital converter means coupled to said frequency converter means for converting said lower intermediate frequency signals into digital signals;decimating means coupled to said analog-to-digital converter means for reducing the processing speed requirements of each said digital signal by a factor M;digital filter bank means for performing an inverse discrete Fourier transform containing K number of polyphase bandpass filters coupled to said decimating means for generating a plurality of polyphased digital channel signals from said digital signals;means, including a plurality of exponential operator-inclusive modulators coupled to individual channel outputs of said K number of polyphase bandpass filters for translating said channelized digital signals from bandpass frequencies to baseband frequencies of selected limited frequency spectrum;converter means coupled to said digital filter bank means for converting said plurality of polyphased digital channel signals into phase component signals and magnitude component signals;signal detection logic means having inputs coupled to said converter means magnitude component signals for sampling signal amplitude;digital instantaneous frequency measurement means coupled to said signal detection logic means for processing said converter means phase component signals to instantaneous frequency signals; andarbitration means coupled to output signals of said digital instantaneous frequency measurement means for segregating valid from invalid signals therefrom, said segregation being based on location of a signal within or without of a channel.