Patent ID: 9059267
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a III-V compound semiconductor-containing heterostructure above a substrate, wherein the III-V compound semiconductor-containing heterostructure comprises a buffer layer above the substrate, a channel layer above and in contact with the buffer layer, a barrier layer above and in contact with the channel layer, and an etch stop layer above and in contact with the barrier layer; gate spacers on an uppermost surface of the etch stop layer; raised source-drain (RSD) regions on the uppermost surface of the etch stop layer, wherein the RSD regions are adjacent to and contacting the gate spacers; a dielectric layer on the uppermost surface of the RSD regions, wherein the dielectric layer is adjacent to and contacting the gate spacers, and wherein an uppermost surface of the dielectric layer is higher than an uppermost surface of the gate spacers; and a T-shaped gate structure above the uppermost surface of the channel layer and adjacent to the gate spacers, wherein the T-shaped gate structure comprises: