Patent ID: 6072212
Filing Date: 2000-06-06
Classification: H01L

Abstract:
An array of nonvolatile memory cells on a substrate of first conductivity-type, said array comprising:a first diffused region of second conductivity-type in said substrate, said first diffused region including the sources, and the connections between sources, of all of said memory cells in said array;a second diffused region of first conductivity-type, said second diffused region in said first diffused region, said second diffused region including the channel of at least one of the memory cells of said array;floating gates and control gates of said memory cells over, and insulated from, a junction of said first diffused region and said second diffused region; anda third diffused region of said second conductivity-type, at least one said third diffused region in said substrate located at one edge of a said floating gate and a said control gate, said third diffused region isolated in said second diffusion to form the drain of a said memory cell.