Patent ID: 6235650
Filing Date: 2001-05-22
Classification: C23C,H01L

Abstract:
A method for the passivation and protection of a semiconductor integrated circuit device comprising the steps of:forming a silicon oxide layer on a semiconductor substrate containing elements and devices;forming a conductive pattern interconnecting said elements and said devices and said semiconductor substrate;depositing a barrier layer of silicon oxynitride on said interconnection pattern and said elements and said devices by means of a plasma-enhanced chemical vapor deposition process further comprising:forming a gas mixture of nitrous oxide and a silicon-containing gas with a flow rate of nitrous oxide greater then 600 standard cubic centimeters per minute and a nitrous oxide:silicon-containing gas flow rate ratio of greater than 20:1, and;sustaining an electrical plasma in the said gas mixture employing dual power sources to deposit said layer of silicon oxynitride;depositing a final protective silicon oxide layer over said silicon oxynitride barrier layer.