Patent ID: 7673194
Filing Date: 2010-03-02
Classification: G01R,G06F

Abstract:
1. An apparatus configured to generate a power-on-reset using a power-on-reset signal line, said apparatus comprising: a power-on-reset circuit having an input and an output; an oscillator circuit having an input and an output, said input coupled to said output of said power-on-reset circuit; at least one memory test device having a data input, an output, a set input, a reset input, a row-control signal line, and a column-control signal line, one of said set input and said reset input of each said at least one memory test device coupled to said output of said power-on-reset circuit, said row-control signal line and said column-control signal line coupled to said output of said oscillator circuit; and a buffer having an input and an output, said input coupled to said output of said memory test device and said output coupled to said power-on-reset signal line.