Patent ID: 7646643
Filing Date: 2010-01-12
Classification: G11C,H01L

Abstract:
1. An integrated circuit comprising: first and second pads adapted to be charged by charge carriers during manufacture of the integrated circuit; a reference nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate of the reference nonvolatile memory cell is coupled to the first pad; a charging protection device coupled to the control gate of the reference memory cell and adapted to limit the gate voltage of the control gate of the reference nonvolatile memory cell induced by the charge carriers during the manufacture of the integrated circuit; and a charging monitor nonvolatile memory cell comprising a floating gate and a control gate, wherein the control gate of the charging monitor nonvolatile memory cell is coupled to the second pad but not to a charging protection device adapted to limit the gate voltage of the control gate of the charging monitor memory cell, wherein the reference nonvolatile memory cell whiled charged exhibits a first threshold voltage, the charging monitor nonvolatile memory cell while charged exhibits a second threshold voltage, and the memory cells are adapted to enable the first and second threshold voltages to be compared to each other as a measurement of potential damage sustained by the integrated circuit in response to the charge carriers.