Patent ID: 6249450
Filing Date: 2001-06-19
Classification: G06F,G11C

Abstract:
In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of executing a cache load cycle, comprising the steps of:receiving a row address not corresponding to data stored in any of said cache cells;coupling said bit lines to said sense lines;activating a word line corresponding to said row address;transferring data from memory cells coupled to said word line via said bit lines to said sense lines;amplifying the data on said sense lines;coupling said column data lines to said sense lines;transferring the data on said sense lines via said column data lines to said cache cells; andreceiving at least one column address and transferring data between said column data lines and said data bus, thereby completing said cache load cycle.