Patent ID: 7517789
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A structure formation method, comprising: providing (a) a dielectric layer including a dielectric layer top surface that defines a reference direction essentially perpendicular to the dielectric layer top surface, and (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; forming a bump limiting metallurgy (BLM) film on the electrically conductive bond pad and the dielectric layer top surface; forming a patterned support/interface layer on the BLM film, wherein the patterned support/interface layer comprises a hole directly above the electrically conductive bond pad such that the BLM film is exposed to a surrounding ambient through the hole; forming an electrically conductive solder bump in the hole and in direct physical contact with the BLM film, wherein the electrically conductive solder bump has a top point at a level higher than a top surface of the patterned support/interface layer; and using the electrically conductive solder bump as a blocking mask to etch the patterned support/interface layer and then the BLM film stopping at the dielectric layer so as to form a support/interface region from the patterned support/interface layer, wherein the support/interface region is in direct physical contact with the electrically conductive solder bump.