Patent ID: 7761832
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. In a computing device, a method for optimizing the timing-driven placement of one or more movable elements of a circuit in a physical synthesis flow, the method comprising: identifying and selecting at least one movable element within a subcircuit based on at least one selection criteria; generating a delay pyramid for each net in the subcircuit; generating a required arrival time (RAT) surface for each net in the subcircuit; generating a slack pyramid for each net in the subcircuit; generating a worst-case slack region based on a plurality of slack pyramids in the subcircuit; mapping the worst-case slack region on a placement region; determining a set of coordinates representing an optimal location of the at least one movable element in the placement region based on the mapping of the worst-case slack region; and outputting, by said computing device, the determined set of coordinates representing the optimal location of the at least one movable element.