Patent ID: 7687305
Filing Date: 2010-03-30
Classification: H01L,Y02E

Abstract:
1. A method comprising: forming an interlayer dielectric layer including a pad over a semiconductor substrate formed with a pixel; sequentially forming a color filter and a planarization layer over the interlayer dielectric layer; forming a first dielectric layer over the planarization layer; forming a microlens array mask over the first dielectric layer; forming a seed microlens array by etching the first dielectric layer using the microlens array mask as an etching mask; forming a microlens array by depositing a second dielectric layer over the seed microlens array and in spaces between neighboring seed microlenses; and then exposing the pad, wherein etching the first dielectric layer is performed in a chamber using a source power of between 600 to 1400 W at 27 MHz and a bias power of between 0 to 500 W at 2 MHz.