Patent ID: 6501181
Filing Date: 2002-12-31
Classification: H01L,H01P,H05K

Abstract:
An arrangement in a multilayered electronic circuit for radio frequency applications, said circuit comprising a number of substrate layers, wherein a first planar conductor (504) is formed on a first substrate layer among said plurality of substrate layers; said circuit further comprising a first via hole, formed in said first substrate layer or in a substrate layer adjacent to said first substrate layer on the side of the first planar conductor, said first via hole being filled with a conductive material constituting a first via segment (513), where the capacitive coupling between the first via segment (513) in said first via hole and said first planar conductor (504) is intended to be within a predetermined range characterised in that a compensating planar conductor (511) is situated between said first via hole segment (513) and said first planar conductor (504) on the same side of the same substrate layer as said first planar conductor (504), said first (504) and said compensating (511) planar conductors being non-intersecting; and that said first (504) and said compensating (511) planar conductors are interconnected by a conductive material (512) disposed in a compensating via hole, which is formed in the same substrate layer as said first via hole.