Patent ID: 6598194
Filing Date: 2003-07-22
Classification: G01R

Abstract:
In a method for testing integrated circuits having associated position designations, the improvement comprising:a. introducing a predetermined set of input vectors as test input into the integrated circuits, b. sensing output from the integrated circuits in response to the predetermined set of input vectors, c. recording the output from the integrated circuits in a wafer map, referenced by the position designations, d. selecting the output from at least a subset of the integrated circuits, e. mathematically manipulating the output of the selected subset of integrated circuits to produce a reference value, f. individually comparing the output for each of the integrated circuits in the selected subset to the reference value, g. identifying graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount, and h. assigning a classification to the graded integrated circuits.