Patent ID: 7329578
Filing Date: 2008-02-12
Classification: H01L

Abstract:
1. In a flash memory process, forming a floating gate comprising: forming a gate dielectric layer overlying a semiconductor substrate; forming a first gate conductive layer overlying said gate dielectric layer; forming a photoresist layer overlying said first gate conductive layer, wherein said photoresist layer has a pattern opening corresponding to an area where a floating gate will be defined; removing at least part of said first gate conductive layer through said pattern opening to form a trench in said first gate conductive layer without exposing said gate dielectric layer; removing said photoresist layer; forming an oxide layer overlying said first gate conductive layer to fill said trench; partially removing said oxide layer till said oxide layer remaining in said trench is substantially leveled off with said first gate conductive layer, forming a trench-filled oxide layer; and removing portions of said first polysilicon layer not covered by said trench-filled oxide layer and leaving portions of the first polysilicon layer that are not covered by said trench filled oxide layer, and thereby said first gate conductive layer covered by said trench-filled oxide layer functioning as a floating gate with a tip.