Patent ID: 8558281
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer over the buffer layer and a barrier layer over the channel layer, the method comprising: forming a gate, the gate comprising silicon; forming first sidewalls on either side and adjacent to the gate, the first sidewalls comprising a first material; selectively etching into the buffer layer to form a mesa for the field effect transistor; depositing a material layer over the mesa; planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface; depositing metal on the planzarized surface; annealing to form the gate into a metal silicided gate; and selectively etching to remove excess non-silicided metal.