Patent ID: 8017445
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A method of packaging a semiconductor device in a package, the method comprising: mounting a die on which the semiconductor device is fabricated to a die paddle of a leadframe, wherein the die paddle is offset above a plane formed by the leadframe and the die is mounted on a top portion of the die paddle facing away from the plane formed by the leadframe; and encapsulating the die on the die paddle in a first volume of molding compound above the leadframe and the die and a second volume of molding compound below the leadframe, a first volume of molding compound above the leadframe and the die and a second volume of molding compound below the leadframe, wherein the first volume of molding and the second volume of molding compound are substantially equal to substantially eliminate warpage stress on the package caused by coefficient of thermal expansion (CTE) mismatch between the device, the package, and the molding compound.