Patent ID: 6016064
Filing Date: 2000-01-18
Classification: H03K

Abstract:
An interpolating circuit comprising:a parallel-connected element having a plurality of MOS transistors of a first conductivity type, one of the terminals of said transistors being connected to a first power supply, the other terminal of said transistors being connected to an output terminal, and the gates of said transistors being connected to mutually different input terminals, respectively, and,a first series-connected element having a plurality of MOS transistor of a second conductivity type, one of the terminals of said transistors being connected to a second power supply, the other terminals of said transistor being connected to said output terminal, and the gates of said transistors being connected respectively to said input terminals,one or more separate series-connected elements each having a plurality of MOS transistor, one of the ends of which is connected to said first power supply, the other ends of which is connected to the above-noted output terminal, and the gates of each one of said MOS transistors is connected respectively to the above-noted input terminals.