Patent ID: 8799750
Filing Date: 2014-08-05
Classification: G06F,H03M

Abstract:
1. A system comprising: a first integrated circuit having a local memory, an address generator receiving interleaver settings and generating WRITE addresses according to first interleaver settings and READ addresses according to second interleaver settings, a physical controller, and a WRITE controller; and a second integrated circuit having memory supporting burst WRITE operations and burst READ operations, the physical controller of the first integrated circuit writing data from the first integrated circuit to the WRITE addresses for memory locations of the second integrated circuit as a WRITE burst of data according to write address sets in a write address sequence, and reading data from the second integrated circuit to the first integrated circuit as a READ burst of data according to read address sets in a read address sequence, at least one datum from the READ burst of data being stored in the local memory at an address provided by the WRITE controller according to the interleaver settings; wherein the WRITE addresses comprise duplicate memory locations which are available to be written as a part of each WRITE burst to enable the WRITE burst of data, and a selected memory location of a pair of duplicate memory locations associated with the same memory address of the write address sequence for different time sequences is written with second data associated with a second time sequence during the WRITE burst of data according to the write address sequence, and first data associated with a first time sequence is stored in the other memory location of the pair of duplicate memory locations, wherein the second data associated with the second time sequence is read before the first data associated with the first time sequence according to a read address sequence which is different than the write address sequence.