Patent ID: 8325549
Filing Date: 2012-12-04
Classification: G11C

Abstract:
1. A global to local bit line interface circuit for domino static random access memory (SRAM) devices, the circuit comprising: a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write control logic configured to control precharging of the complementary global write bit lines independently with respect to precharging of the complementary global read bit lines, wherein the write control logic comprises a pair of parallel NOR gates configured to precharge the complementary global write bit lines in a standby mode of operation and in a read mode of operation, and wherein a pulse width of write data on the complementary global write bit lines is determined only by a global column select signal.