Patent ID: 6720627
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A CMOS-type semiconductor device comprising:an NMOSFET having n-type source and drain regions and a PMOSFET having p-type source and drain regions of the PMOSFET, wherein the NMOSFET and the PMOSFET each have a gate electrode provided with sidewall spacers of an insulating film on both sidewalls, the n-type source and drain regions include first diffusion layer regions on both sides of a channel region, and second diffusion layer regions located on the outside of the first diffusion layer regions, the p-type source and drain regions include third diffusion layer regions on both sides of a channel region and fourth diffusion layer regions located on the outside of the third diffusion layer regions, the second diffusion layer regions have a greater junction depth than the fourth diffusion layer regions, and each of the sidewall spacers has a lateral thickness of at least about 0.7, multiplied by the junction depth of a corresponding second or fourth diffusion layer region.