Patent ID: 6189128
Filing Date: 2001-02-13
Classification: G01R

Abstract:
A design for testability method comprising:extracting paths that can be appropriated as scan paths from a multiplicity of paths that connect specific circuit elements in a preliminarily-designed register transfer level circuit;for each of said extracted paths that include at least one multiplexer as one of said circuit elements, forming a first candidate scan path by connecting control elements to each said multiplexer and calculating an area occupied by said first candidate scan path;for each of said extracted paths that include registers as said circuit elements, forming a second candidate scan path by replacing each of said registers with a scan element and calculating an area occupied by said second candidate scan path;for each of said extracted paths, selecting from said first candidate scan path and said second candidate scan path the candidate scan path having the smaller occupied area; andfor each of said extracted paths, forming a scan path based on the selected result.