Patent ID: 7986037
Filing Date: 2011-07-26
Classification: H01L,H05K,Y02P

Abstract:
1. A semiconductor device comprising: a semiconductor chip having at least a power terminal and a ground terminal; a semiconductor package having a first terminal and a second terminal and being electrically connected to the power terminal and the ground terminal, respectively; a third terminal, a fourth terminal, a fifth terminal and a sixth terminal being connected to a printed circuit board; a plurality of first power feed routes being connected between the first terminal and the third terminal, and between the first terminal and the fourth terminal, respectively; and a plurality of second power feed routes being connected between the second terminal and the fifth terminal, and between the second terminal and the sixth terminal, respectively, wherein the semiconductor package is provided on the printed circuit board and a power supply layer for electrical connection to the power terminal and a ground layer for electrical connection to the ground terminal are disposed in at least one of inside layers of the printed circuit board and a decoupling capacitor is mounted on the surface of the printed circuit board, wherein further on a surface of the printed circuit board provided with a plurality of first VIA electrodes connected with the power supply layer by way of VIA, a plurality of second VIA electrodes connected with the ground layer by way of VIA, a first interconnection connected with the first VIA electrode, a second interconnection connected with the second VIA electrode, a first capacitor interconnecting electrode connecting to the first interconnection and mounting on an opposite side of the printed circuit board with respect to the first VIA electrode, a second capacitor interconnecting electrode connecting to the second interconnection, and mounting on an opposite side of the printed circuit board with respect to the second VIA electrode, and the decoupling capacitor being connected to the first capacitor interconnecting electrode and the second capacitor interconnecting electrode, respectively, and wherein the first capacitor interconnecting electrode and the second capacitor interconnecting electrode provide a high resistance area comprised of a high resistance material and a low resistance area comprised of a low resistance material, the high resistance area of the first capacitor interconnecting electrode and the high resistance area of the second capacitor interconnecting electrode are disposed on inner sides of the first interconnection and the second interconnection, respectively so as to be disposed face to face on the surface of the printed circuit board, the low resistance area of the first capacitor interconnecting electrode and the low resistance area of the second capacitor interconnecting electrode are disposed on an outer side of the first interconnection and the second interconnection.