Patent ID: 7383394
Filing Date: 2008-06-03
Classification: G06F

Abstract:
1. An apparatus in a microprocessor for selectively retiring a prefetched cache line into a cache memory of the microprocessor, comprising: a prefetch buffer, for storing the prefetched cache line, said prefetched cache line having an associated index value, wherein said index value is a portion of a memory address of said prefetched cache line; a counter, coupled to said prefetch buffer, for storing a count of accesses to a replacement candidate line in the cache, wherein said replacement candidate cache line is stored in a location within the cache specified by said index value of said prefetched cache line stored in said prefetch buffer; and control logic, coupled to said counter, for selectively retiring the prefetched cache line to said location within the cache specified by said index value of said prefetched cache line stored in said prefetch buffer based on said count in said counter.