Patent ID: 8338254
Filing Date: 2012-12-25
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a buried insulating film on a semiconductor substrate and spaced apart first and second active regions vertically extending into the buried insulating film; forming an interlayer insulating film on the first and second active regions and on the buried insulating film; forming an upper interconnection in the interlayer insulating film, a gate electrode extending from the upper interconnection into a region between the spaced apart first and second active regions and a protective film pattern covering at least a top surface of the upper interconnection, the protective film pattern being formed to be self aligned with the upper interconnection and to have a width greater than that of the upper interconnection; and forming first and second buried contact holes exposing top surfaces of the first and second active regions by anisotropically etching the interlayer insulating film using the protective film pattern as an etch-stop film.