Patent ID: 8990759
Filing Date: 2015-03-24
Classification: G01R,H01L

Abstract:
1. A method for evaluating fabrication of at least a portion of a wafer, the method comprising: (a) independently detecting and activating a plurality of test structures distributed at a plurality of locations on the portion of the wafer; the plurality of test structures being formed during a first fabrication process to establish electrical connectivity for a first set of elements which include the plurality of test structures, each test structure being activated and then detected without electrical or physical connectivity to any circuit elements that are part of a design of the product wafer; wherein independent detecting and activating is performed immediately after the first fabrication process; (b) programmatically correlating, with use of one or more computers, an output of one or more of the plurality of test structures to a specified performance parameter that is indicative of an attribute that results from performance of at least one or more fabrication processes for the wafer.