Patent ID: 8249171
Filing Date: 2012-08-21
Classification: H04L,H04N

Abstract:
1. A data synchronizer having an input that receives an input stream of asynchronous digital data in packets and an output that receives an output stream of synchronous data in packets, wherein each packet having a length and valid data bits asserted during valid periods, the data synchronizer comprising: a first memory unit and a second memory unit, wherein the first and second memory units each have a data input, a data output, a write clock input- and a read clock input, and wherein each of the first and second memory units receive a write clock signal at its write clock input; a first switch that switches the input of the data synchronizer in alternating manner between the data inputs of the first and second memory units; a second switch that switches the output of the data synchronizer in alternating manner between the data outputs of the first and second memory units; a packet counter having an input that is coupled to the input of data synchronizer, wherein the packet counter counts a number of write clock cycles in a received packet and provides an output frequency code word representing an average data rate of the received valid data during the reception of the received packet; a digital frequency synthesizer having an input that receives the frequency code word and that provides a read clock signal directly to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read; and a controller that is responsive to the packet counter, wherein the controller controls the switching of the first and second switches such that the first and second switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.