Patent ID: 6376351
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of fabrication a gate with a wide top comprising the steps of:a) providing a substrate; providing a gate dielectric layer, a gate electrode and spacers over a substrate; providing source and drain regions adjacent said gate electrodes; providing source and drain silicide regions over said source and drain regions and a gate silicide region over said gate electrode; b) forming a stop layer over said substrate, said source and drain silicide regions, said gate silicide region and said spacers; c) forming a first interlevel dielectric layer over said stop layer; d) polishing said first interlevel dielectric layer using said stop layer and said gate silicide region as a polish stop and polishing said stop layer to expose said gate silicide region; e) forming a polish stop layer over said first interlevel dielectric layer and said gate silicide region; f) forming a second interlevel dielectric layer over said polish stop layer; g) forming a contact trench through at least said second interlevel dielectric layer, said polish stop layer, and said first interlevel dielectric layer, and said stop layer to expose said source and drain silicide regions; h) forming a wide gate trench top opening through said second interlevel dielectric layer and said polish stop layer to expose said gate silicide region; i) depositing a conductive material to fill said wide gate trench top opening to form a wide gate top and to fill said contact trench to form a contact plug contacting said source and drain silicide regions; and j) forming a first metal layer over said second interlevel dielectric layer; said first metal layer contacting said contact plugs and said wide gate top.