Patent ID: 6202185
Filing Date: 2001-03-13
Classification: G01R

Abstract:
An electronic circuit comprising:a plurality of register circuits, each including an input gate configured to selectively pass a data signal applied to that register, a master stage configured to store a data signal passed by the input gate of that register, an interstage gate configured to selectively pass a data signal stored by the master stage of that register, and a slave stage configured to store a data signal passed by the interstage gate of that register;a plurality of inter-register gates, each of which is operatively arranged to selectively pass a data signal stored by the master stage of an associated respective first one of the registers to the master stage of an associated respective second one of the registers for storage by the master stage of that second one of the registers so that the master stages of all of the registers and the inter-register gates are connected in a single series of alternating master stages and inter-register gates;normal mode circuitry configured to alternately enable the input gates and the interstage gates and to disable the inter-register gates; andscan mode circuitry configured to disable the input gates and the interstage gates and to alternately enable alternate ones of the inter-register gates in the series.