Patent ID: 7181710
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. A method of estimating a cell delay for an integrated circuit design comprising steps of: (a) selecting a range of values for cell ramptime and load; (b) selecting a range of values for an additional cell parameter; (c) arranging the values for cell ramptime, load, and the additional cell parameter in a lookup table; (d) calculating a cell delay as a function of each combination of the cell ramptime, load, and the additional cell parameter for the lookup table; (e) searching the values for cell ramptime, load, and the additional cell parameter in the lookup table for a cell delay that most closely corresponds to the values of cell ramptime, load, and the additional cell parameter for a specific cell in an integrated circuit design; (f) interpolating between only two cell delays that most closely correspond to the values of cell ramptime, load, and the additional cell parameter; and (g) successively weighting the values of cell ramptime, load, and the additional cell parameter to generate an estimated cell delay for the specific cell.