Patent ID: 6720200
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A fabrication process of a field effect transistor comprising the steps of:forming a hetero junction semiconductor crystal having a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer; forming a two stage recess structure by selective etching of said first GaAs layer and said second GaAs layer with respect to said first AlGaAs layer and said second AlGaAs layer for removing said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; performing etching in a transverse direction with respect to said first GaAs layer by performing excessive etching after reaching to said first AlGaAs layer in said selective etching with respect to said first GaAs layer, without etching said first AlGaAs layer; and forming a gate electrode on said first AlGaAs layer so as to define a gap between said first GaAs layer and said gate electrode, whereby said gate electrode does not contact with said first GaAs layer.