Patent ID: 7544567
Filing Date: 2009-06-09
Classification: H01L

Abstract:
1. A method of manufacturing a flash memory device, comprising: providing a semiconductor substrate comprising a cell region and a peri region, the cell region including a memory cell region and a Drain Select Line/Source Select Line (DSL/SSL) region, the peri region including a high voltage region and a low voltage region; forming a first oxide layer and a buffer poly layer over the surface of the semiconductor substrate except for the memory cell region of the cell region; forming a second oxide layer, a nitride layer and a third oxide layer over the surface of the first oxide layer and the memory cell region of the cell region; exposing the poly buffer layer by etching specific regions of the third oxide layer, the nitride layer and the second oxide layer in the peri region and in the DSL/SSL region of the cell region; forming a conductive layer so that the conductive layer is electrically connected to the poly buffer layer; selectively etching the third oxide layer, the nitride layer and the second oxide layer to form a gate in the memory cell region of the cell region; and selectively etching the buffer poly layer to form a gate in the DSL/SSL region of the cell region and a gate in the high voltage region and the low voltage region of the peri region.