Patent ID: 8035226
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate; a bond pad disposed over said substrate; a dielectric layer disposed over the substrate and the bond pad, the dielectric layer having an opening therein over the bond pad; a first stress relief layer disposed over the dielectric layer, the first stress relief layer having a second opening therein over the bond pad; a redistribution layer (RDL) disposed over the dielectric layer and the bond pad through the first opening and the second opening; an under bump metallization (UBM) layer disposed over the RDL; and a second stress relief layer disposed over at least a portion of the first stress relief layer, over at least a portion of the RDL, and over at least a portion of the UBM, the second stress relief layer having a third opening therein over the UBM; and a solder ball disposed over the UBM layer through the third opening, the solder ball including: