Patent ID: 6647507
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A method comprising:allowing a processor to execute instructions for improving a timing margin in a first integrated circuit (IC) die under test, wherein the execution (a) instructs the first IC die to set a relative phase of receive and reference clock signals at the first IC die, from a plurality of discrete, receive phase values, (b) instructs the first IC die to set a relative phase of transmit and reference clock signals at the first IC die, from a plurality of discrete, transmit phase values, (c) instructs the first IC die to drive a sequence of outgoing data symbols according to the transmit clock and receive a sequence of incoming data symbols according to the receive clock, at the relative phase settings of (a) and (b), and compares the outgoing symbols to the incoming symbols, and then (d) repeats (a)-(c) for other combinations of said plurality of transmit and receive phase values, and then (e) sets the relative phases, to values which are closest to yielding a balanced timing margin as determined from the results of the comparisons.