Patent ID: 6044027
Filing Date: 2000-03-28
Classification: G11C,H03K

Abstract:
A method of delaying a digital signal having first or second logic levels, the method comprising:providing a capacitor;providing a first transistor coupled between a first power supply voltage and the capacitor;rendering the first transistor conductive responsive to a first logic level of the digital signal, the first transistor, when conductive, conducting a charging current to the capacitor to charge the capacitor toward the first supply voltage;providing a second transistor coupled between a second power supply voltage and the capacitor;rendering the second transistor conductive responsive to a second logic level of the digital signal, the second transistor, when conductive, conducting a discharging current from the capacitor to discharge the capacitor toward the second supply voltage;adjusting the magnitude of the charging current as a function of the magnitude of the first supply voltage;adjusting the magnitude of the discharging current as a function of the magnitude of the second supply voltage; andproviding a delayed digital signal having one logic level responsive to the capacitor charging to a first predetermined voltage and another logic level responsive to the capacitor discharging to a second predetermined voltage.