Patent ID: 7373584
Filing Date: 2008-05-13
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a memory array having a data area in which data is stored and a check code area in which a check code for error detection/correction of said data is stored; a refresh control means which controls a refresh operation of said memory array in a data holding state using a predetermined period; an operation means which executes an encoding operation for generating said check code using a bit string in said data area as a processing unit for said encoding operation, and executes a decoding operation for performing said error detection/correction of said data using said check code; an encode control means for controlling an encode process in which, in a change to said data holding state, in a first direction and a second direction orthogonal to each other in said memory array, a first code generated by said operation means on the basis of said bit string in said first direction and a second code generated by said operation means on the basis of said bit string in said second direction are written in said check code area in a distinguishable manner; and a decode control means for controlling a decode process in which, at the end of said data holding state, a first bit error correction based on said first code in said first direction and a second bit error correction based on said second code in said second direction are alternately performed by said operation means, and said first bit error correction and said second bit error correction are performed at least twice respectively.