Patent ID: 6734065
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method for fabricating a non-volatile memory device on a semiconductor substrate having a cell array area and a peripheral circuit area, the method comprising:forming an isolation layer on the semiconductor substrate to define a first active region in the cell array area and define second and third active regions in the peripheral circuit area; sequentially forming a tunnel oxide layer, a silicon nitride layer and a top oxide layer on the resultant structure having the isolation layer; patterning the top oxide layer, the silicon nitride layer and the tunnel oxide layer to form a cell gate insulation layer having a tunnel oxide layer pattern, a silicon nitride layer pattern and a top oxide layer pattern, which are sequentially stacked on a first area of the first active region and expose a second area of the first active region, the second active region and the third active region; forming a first gate insulation layer on the exposed second area of the first active region, the exposed second active region and the exposed third active region; patterning the first gate insulation layer to expose the second area of the first active region and the second active region; and forming a second gate insulation layer on the exposed second area of the first active region and the exposed second region, the second gate insulation layer having a thickness less than equivalent oxide thickness of the cell gate insulation layer.