Patent ID: 6964922
Filing Date: 2005-11-15
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device comprising: forming an interlevel dielectric film on an integrated circuit substrate, the integrated circuit substrate including a conductive portion thereof, wherein the interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate and wherein the interlevel dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate; forming a first metal layer using chemical vapor deposition (CVD) in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate wherein the first metal layer comprises aluminum; after preferentially forming the first metal layer in the contact hole, forming a second metal layer using chemical vapor deposition (CVD) on the surface of the interlevel dielectric film opposite the integrated circuit substrate and in the trench wherein the second metal layer comprises aluminum; after forming the second metal layer, forming a third metal layer using physical vapor deposition (PVD) on the second metal layer so that portions of the second metal layer in the trench are between the first and third metal layers wherein the third metal layer comprises aluminum; and reflowing the third metal layer.