Patent ID: 7368350
Filing Date: 2008-05-06
Classification: H01L

Abstract:
1. A method for fabricating nonvolatile memory cells, the method comprising: providing a semiconductor wafer, said semiconductor wafer comprising a semi-conductive substrate having a surface; depositing a structured charge-trapping layer over the surface of said semiconductor wafer; depositing a plurality of gate lines over said structured charge-trapping layer; forming a plurality of buried bit lines between said gate lines, wherein each of said buried bit lines is embedded in said semi-conductive substrate; depositing a first insulating layer within the region between said plurality of gate lines and said structured charge-trapping layer; etching said first insulating layer to form first contact holes, said first contact holes extending from the surface of said first insulating layer to the surface of said buried bit lines; depositing an insulating liner on the sidewalls of said first contact holes; depositing a contact fill material within said first contact hole, said contact fill material filling said first contact holes from the surface of said buried bit lines up to a predetermined height within said first contact holes; depositing a further insulating liner on a top side of the contact fill material; depositing a second insulating layer over the surface of said semiconductor wafer; etching said second insulating layer and said further insulating liner to form second contact holes, said second contact holes extending from the surface of said second insulating layer to the surface of said contact fill material; and forming a contact plug by filling said second contact holes with a conductive material.