Patent ID: 8341579
Filing Date: 2012-12-25
Classification: G01R,G06F

Abstract:
1. A method of analyzing an operation of a semiconductor integrated circuit, comprising: extracting, by using a computer, respective inductances, resistances, and capacitances of a semiconductor substrate, a package, and said semiconductor integrated circuit, from said semiconductor integrated circuit mounted on said semiconductor substrate via said package; generating, by using said computer, individual networks of the extracted inductance, resistance, and capacitance with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; generating, by using said computer, an integrated network by integrating all of said individual networks generated; inserting, by using said computer, a test noise pattern to an arbitrary position as a noise source in said integrated network generated, and performing an operation simulation of said semiconductor integrated circuit, using said integrated network with said test noise pattern being inserted as said noise source; analyzing, by using said computer, a result of said operation simulation performed, and detecting a false operation occurring due to said noise source; performing, by using said computer, said operation simulation with a new test noise pattern being inserted as another noise source when said false operation is not detected in said operation simulation; applying, by using said computer, said test noise pattern corresponding to said noise source as an exogenous noise from outside said semiconductor integrated circuit, when said false operation detected is caused by said noise source; and carrying out, by using said computer, a device analysis through an actual operation of said semiconductor integrated circuit to which said exogenous noise applied, thereby checking the conformity of the results of the analysis through said operation simulation with said actual operation by said semiconductor integrated circuit.