Patent ID: 9224679
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A wafer level chip scale (WLCS) package device comprising: a semiconductor chip having a plurality of bonding pads formed on a front surface of the semiconductor chip, each of the plurality of bonding pads having a respective metal interconnecting structure of a plurality of metal interconnecting structures formed thereon; a bottom metal layer covering a back surface of the semiconductor chip opposite the front surface of the semiconductor chip; a thick bottom metal attached to the bottom metal layer through a conductive bonding layer, said thick bottom metal having a thick central portion and a thin portion extending away from the thick central portion; a top package layer covering the front surface of the semiconductor chip and surrounding a sidewall of each of the plurality of metal interconnecting structures; and a package body surrounding at least a bottom portion of a sidewall of the semiconductor chip and a sidewall of the thick bottom metal.