Patent ID: 6013537
Filing Date: 2000-01-11
Classification: G01R,H01S

Abstract:
A method comprising the steps of:providing a wafer;forming an electrical device within said wafer;said electrical device having:a top layer forming an upper device surface, said top layer having a first top surface and a second top surface;a first electrode making contact with said first top surface;a first device contact making electrical contact with said first electrode;a bottom layer forming a lower device surface, said bottom layer having a first bottom surface and a second bottom surface, said first bottom surface being attached to said second top surface;a second electrode making contact with said first bottom surface;a substrate attached to said second bottom surface;a second device contact making electrical contact with said substrate;attaching a conductive plate to a portion of said first top surface;forming a third device contact in electrical contact with said conductive plate; andforming a semi-insulated region in said top layer between said portion and said first bottom surface.