Patent ID: 6502187
Filing Date: 2002-12-31
Classification: G06F

Abstract:
The pipelined computer, comprising:an instruction division unit which divides a variable-length data-handling instruction into a predetermined number of fixed-length data-handling instructions; an execution unit which executes said fixed-length data-handling instructions, received from said instruction division unit, in a sequence of generation during the division; wherein said instruction division unit adds a derivation flag and a sequence flag to each of said fixed-length data-handling instructions as an extension tag, the derivation flag indicating that the instruction is generated by the division, the sequence flag indicating the sequence of the instruction during the division, which further comprises: a redundant instruction detection unit which checks the instruction issued to said execution unit and, upon detecting through said extension tag that the instruction is the fixed-length data-handling instruction generated by the division and that a number of the fixed-length data-handling instructions required to process the data length handled by the original variable-length data-handling instruction have been executed, outputs said extension tag as a bubble extension tag.