Patent ID: 8921944
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; at least two metal-oxide semiconductor (MOS) transistors disposed in the substrate, wherein the MOS transistor comprises a gate structure and a source/drain disposed in the substrate adjacent to two sides of the gate structure; at least one stress plug disposed between two MOS transistors, and the stress plug is not electrically connected to the source/drain; a shallow trench isolation (STI) disposed in the substrate and between two MOS transistors, wherein the STI comprises a stress material, and the MOS transistors adjacent to two sides of the STI are transistors of the same conductivity type; and at least one conductive plug disposed on the substrate to connect the source/drain, wherein the stress plug surrounds and extends parallel to the gate structure, but not in direct contact with the gate structure, and the conductive plug is disposed between the gate structure and the stress plug.