Patent ID: 7705639
Filing Date: 2010-04-27
Classification: H04L

Abstract:
1. An automatic frequency correction component, wherein a phase signal input to the automatic frequency correction component is converted to a frequency correction signal output, the circuit comprising: a clock generator circuit configured to convert a received clock signal into a plurality of internal clock signals that operate at a fraction of the rate of the clock signal and are skewed uniformly in time, each of the internal clock signals being separated by a fixed clock time interval, and where a sum of the fixed clock time intervals equals the cycle time interval of the clock generator; a plurality of sample and hold elements, each receiving one of the plurality of internal clock signals and the phase signal, where the phase signal is sampled responsive to each internal clock signal, to obtain a corresponding plurality of sampled phase signals; a plurality of delay elements, where each delay element stores one of the plurality of sampled phase signals responsive to a corresponding one of the internal clock signals in order to output a corresponding one of a plurality of delayed phase signals; a plurality of accumulators, where each accumulator is configured to receive one of the delayed phase signals and a corresponding one of the sampled phase signals and compute a difference responsive thereto in order to output a corresponding one of a plurality of phase difference signals; an intermediate averaging component configured to receive the plurality of phase difference signals and generate an intermediate average of the phase difference signals responsive to the received clock signal; a threshold detector configured to receive the phase difference signals, generate a difference between multiple phase difference signals responsive to the clock signal, and compare the difference between multiple phase difference signals to a first threshold in order to detect a series of substantially equal consecutive phase differences and activate a detect signal responsive thereto; and an output filter configured to receive the intermediate average of the phase difference signals and filter the intermediate average responsive to the detect signal in order to generate the frequency correction signal.