Patent ID: 6388470
Filing Date: 2002-05-14
Classification: H03K

Abstract:
A high voltage output CMOS thin oxide gate signal driver system comprising:an output CMOS device adapted to transmit a high voltage signal; a bias voltage range limiter coupled to said output CMOS device, said bias voltage range limiter adapted to confine a gate degradation repression bias voltage signal within a range that results in an acceptable voltage differential from a gate of said output CMOS device to a source and drain of said output CMOS device that is within electric field stress tolerance limitations of said output CMOS device; a pull down component coupled to said output CMOS device, said pulldown component adapted to pull a signal down; a bias voltage level driver coupled to said output CMOS device; said bias voltage level driver adapted to actively drive said gate degradation repression bias voltage signal to an acceptable level that results in a voltage differential from the gate of said output CMOS device to the source and drain of said output CMOS device that is within electric field stress tolerance limitations of said output CMOS device; and a high voltage input component coupled to said bias voltage level driver, said high voltage input component configured as an input receiver adapted to provide a feedback signal to said bias voltage level driver.