Patent ID: 9099419
Filing Date: 2015-08-04
Classification: G01R,H01L

Abstract:
1. A test method, comprising: providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell, wherein a potential of the at least one additional electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, the at least one second terminal electrode region, and the at least one gate electrode.