Patent ID: 8288771
Filing Date: 2012-10-16
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a plurality of gate lines formed on the substrate; a plurality of common electrodes having a transparent conductive layer on the substrate; a gate insulating layer covering the gate lines and the common electrodes; a plurality of semiconductor layers formed on the gate insulating layer; a plurality of data lines including a plurality of source electrodes, formed on the semiconductor layer and the gate insulating layer; a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer; and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes, wherein the transparent conductive layer comprises indium tin oxide nitride (ITON) or indium zinc oxide nitride (IZON) or amorphous indium tin oxide nitride (a-ITON).