Patent ID: 6027964
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of making an IGFET with a selectively doped gate in combination with a protected resistor, the method comprising:providing a semiconductor substrate with an active region and a resistor region;forming a gate over the active region;forming a diffused resistor in the resistor region;forming an insulating layer over the active region and the resistor region;forming a masking layer over the insulating layer, wherein the masking layer includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate;applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate, wherein an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor; andforming a source and a drain in the active region, including at least partially doping the source and the drain during a doping step that provides more doping for the first portion of the gate than for the second portion of the gate after forming the masking layer.