Patent ID: 6598191
Filing Date: 2003-07-22
Classification: G01R

Abstract:
An apparatus for verifying the functional behavior of a digital system, the digital system including a first series of interconnected registers clocked by a first clock and a second series of interconnected registers clocked by a second clock, wherein an asynchronous boundary is formed at a coupling between the first series of interconnected registers and the second series of interconnected registers, the apparatus comprising:a delay register coupled to an output of a predetermined register which is predetermined from a group of registers including the last register of the first group of interconnected registers and all registers from the second group of interconnected registers, wherein the delay register is clocked by the same clock as the predetermined register; a multiplexer, including: at least two multiplexer inputs coupled to the output of the predetermined register and an output of the delay register, a multiplexer output coupled to an input of a next register in the second series of interconnected registers, a multiplexer input selector, and a selector coupled to the multiplexer input selector for selecting which of the at least two multiplexer inputs to pass through to the multiplexer output.