Patent ID: 6153467
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of fabricating buried bit line flash EEPROM with a trench floating gate, comprising the steps of:forming a pad oxide layer on a silicon substrate;forming a first polysilicon layer with conductivity type impurities on said pad oxide layer;oxidizing said first polysilicon layer so as to form an oxide layer on said pad oxide and driving said conductivity type impurities through said pad oxide layer so as to form a conductive silicon layer with said conductivity type impurities therein, which is beneath said pad oxide layer;coating a patterned mask on said oxide layer to define a plurality of buried bit line regions;forming a plurality of trenches come down into said silicon substrate using said patterned mask as a mask and defined said buried bit lines by utilizing said conductive silicon layer;removing said patterned mask;forming a gate dielectric layer on said plurality of trenches and form forming a silicon layer to refill said plurality of trenches;performing a planarization process to a resultant surface to form a plain surface using said gate dielectric layer as an etching stopping layer;forming an interpoly dielectric layer on a resultant surfaces; andforming a polysilicon layer on said interpoly dielectric layer to define word lines.