Patent ID: 9141362
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. A hardware apparatus comprising: a processor having a binary translator to perform binary translation of a code having a source binary program order, wherein one or more store instructions of the binary translated code are to be issued in a different order from the source binary program order of the one or more store instructions of the code, and wherein the one or more store instructions of the binary translated code are to be retired in the source binary program order, wherein each store instruction has a store offset indicator to indicate the source binary program order, and the code comprises one or more commit instructions, wherein each commit instruction has a count, and wherein each store instruction is only visible externally if the store offset indicator of the store instruction is smaller or equal to the count of an executed commit instruction, the binary translator, in response to the executed commit instruction, to subtract the store offset indictor of each store instruction by the count when the store offset indicator is bigger than the count; and the binary translator, in response to the executed commit instruction, to subtract the load offset indictor of each load instruction by the count when the load offset indicator is bigger than the count.