Patent ID: 6480436
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A semiconductor memory comprisinga plurality of electrically programmable, non-volatile memory cells connected to one another by row lines and by column lines to form a matrix of memory cells; a charge pump connected to said matrix of memory cells; a plurality of controllable connection elements, with each controllable connection element being connected between an output of said charge pump and a respective column line; control means for selectively activating said plurality of controllable connection elements; a first element equivalent to a controllable connection element and being connected to the output of said charge pump; a second element equivalent to a memory cell in a biased condition and being connected in series with said first element and a common voltage reference; and a regulator connected between said second element and an input of said charge pump for regulating an output voltage therefrom based upon a voltage between terminals of said second element.