Patent ID: 7172970
Filing Date: 2007-02-06
Classification: H01L

Abstract:
1. A polish method for semiconductor device planarization, said method comprising: providing a substrate having a first layer thereon and a second layer which is a single layer by a deposition process on said first layer, wherein said first layer and said second layer are not made of same material; performing a first chemical mechanical polishing process to decrease a thickness difference value between a highest point and a lowest point of said second layer to a first predetermined thickness difference value without polishing said first layer; and performing a second chemical mechanical polishing process to further decrease said first predetermined thickness difference value to a second predetermined thickness difference value and to expose said first layer, wherein said second chemical mechanical polishing process has a polish selectivity between said first layer and said second layer higher than a polish selectivity between said first layer and said second layer of said first chemical mechanical polishing process.