Patent ID: 6037818
Filing Date: 2000-03-14
Classification: G01R,H03K

Abstract:
A delay circuit for producing a delay timing which is longer than one cycle time of a reference clock while resolution of the delay timing is smaller than said one cycle time of said reference clock, comprising:a coarse delay circuit for producing a borrow signal having a delay time which is an integer multiple of one cycle time of a clock signal supplied thereto;a divider for dividing a frequency of said reference clock to produce said clock signal supplied to said coarse delay circuit;a flip-flop circuit which is supplied with said reference clock for delaying an incoming signal by one time period of said reference clock;a re-timing circuit for receiving an output signal from said flip-flop circuit and producing a coarse delay signal in synchronism with said reference clock;a decoder for receiving said borrow signal from said coarse delay circuit and selectively providing said borrow signal to either said flip-flop circuit or said re-timing circuit; anda fine delay circuit for adding a fine delay time which is smaller than said one cycle time of said reference clock to said coarse delay signal from said re-timing circuit.