Patent ID: 7477564
Filing Date: 2009-01-13
Classification: G11C

Abstract:
1. A microcomputer configured in a single chip, comprising: a plurality of memories with redundancy memory elements having reserve memory elements; a fuse cell storing configuration information for controlling switching of memory elements in the plurality of memories; a shift register corresponding to each of the memory elements, with said shift register receiving and retaining the configuration information of the corresponding memory element from the fuse cell; and a control circuit controlling operations of each of the shift registers, wherein the shift register includes: a shift portion, which receives data of the configuration information and transfers the data to another shift register; and, a latch portion which retains the data to be inputted to the shift portion, wherein the control circuit controls whether or not the data inputted to the shift portion of the shift register is to be retained in the latch portion; and wherein the control circuit is formed on a chip of the microcomputer and provides for a plurality of modules activated by causing power to be supplied from an independent power source, respectively, and controls whether or not the data inputted to the shift portion of the shift register in the module is to be retained in the latch portion in response to turning on and off of one of the modules.