Patent ID: 8108588
Filing Date: 2012-01-31
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a random-access flash cell array that includes an executable flash device portion configured for random-access; a serial-access flash cell array that includes a non-executable flash device portion configured for serial-access, wherein the random-access flash cell array and the serial-access flash cell array are both fabricated on a common die using insulating floating gate technology; first circuitry for managing the executable flash device portion; and second circuitry for managing the non-executable flash device portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation in the non-executable flash device portion simultaneously with a processor executing code in the executable flash device portion; wherein the first circuitry and the second circuitry are all located on the common die; and wherein the second circuitry occupies a smaller area per cell on the common die than the first circuitry occupies per cell on the common die.