Patent ID: 6381186
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A random access memory comprising:a memory cell having a transfer N-channel MOS transistor and a storing element for storing data which is connected to said transfer N-channel MOS transistor; a word line connected to a gate of said transfer N-channel MOS transistor of said memory cell; a word line driving voltage source, to which power voltage is input for raising the power voltage to generate a word line driving voltage, said word line driving voltage source being a voltage raising circuit for outputting a steady-level voltage as the word line driving voltage; an address circuit for generating first internal address signals for selecting a first number of said word lines in accordance with externally input address signals, in a normal operation mode; a control circuit responsive to a voltage stress test control signal for generating second internal address signals for selecting a second number of said word lines in a voltage stress test mode, the second number being greater than the first number; a word line selecting circuit, connected to said word line driving voltage source, for decoding the first and second internal address signals, said word line selecting circuit including a precharge circuit and a discharge circuit serially connected between a first node and a ground potential node and outputting a word line selecting signal via a series-connection node connecting said precharge circuit and said discharge circuit, the word line selecting signal having a voltage which varies between a first voltage and a second voltage; and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, said word line driving circuit being provided in correspondence with said word line and having a P-channel MOS transistor which has a source connected to said first node having the word line driving voltage, a drain connected to said word line and a gate to which the word line selecting signal is applied, wherein said word line driving voltage source outputs the steady-level voltage during a first period in which said precharge circuit precharges said series-connection node and during a second period in which said word line driving circuit drives said corresponding word line.