Patent ID: 6535075
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A tunable on-chip capacity circuit for a semiconductor chip mounted on a substrate and including a plurality of power supply decoupling capacitors (Ci) which are connected to a power supply network including a first power line having a first voltage level and a second power line having a second voltage level, and containing parasitic on-chip capacities (CP) and off-chip path impedance comprising inductance (LMC) and resistance (RMC) and an off-chip capacity (CM) generating power supply voltage noise during a highly synchronous on-chip switching activity, the device comprising:a plurality of on-chip switching means each assigned to one of the power supply decoupling capacitors for activating the capacitor by connecting it to one of the power supply lines in a first switching position and for deactivating the capacitor by disconnecting it from the power supply line in a second switching position; on-chip means connected to said first and second power supply lines for detecting a circuit specific load/unload frequency of the on-chip power supply network; and on chip control means responsive to said detecting for increasing or decreasing the total on-chip capacity (CSD) of the power supply decoupling capacitors by selectively operating said switching means.