Patent ID: 6748407
Filing Date: 2004-06-08
Classification: G06F

Abstract:
A direct digital synthesizer comprising:a phase accumulator for cumulatively computing phase data according to a reference clock and frequency data that are entered; a phase-amplitude converter for converting most significant m bits of the phase data supplied by said phase accumulator into an amplitude value; and a variable delay circuit operable to delay the output signal of said phase-amplitude converter according to a phase compensation quantity obtained from the value of least significant bits of said phase data, without said most significant m bits, and said frequency data; wherein said phase accumulator is provided with an adder, which receives said frequency data at one of its inputs and its own output at the other input, for adding them in synchronism with said reference clock; wherein said variable delay circuit delays the output signal of said phase-amplitude converter according to the product of multiplication of the reciprocal of the frequency of said reference clock by the quotient of the division of the least significant bits of said phase data, without the most significant m bits, by said frequency data; wherein a digital-to-analog converter is arranged on the signal input side of said variable delay circuit; and wherein said time constant circuit comprises: a resistor whose input is the output signal of a digital-to-analog converter for analog conversion of the output of said phase-amplitude converter, and a variable capacity element which is connected between the output of this resistor and the ground and whose capacitance varies according to said analog compensation control signal.