Patent ID: 7329571
Filing Date: 2008-02-12
Classification: H01L

Abstract:
1. A method, comprising: forming a first gate electrode of a first transistor of a first type and a second gate electrode of a second transistor of a second type; forming a strained semiconductor layer in a recess formed adjacent to said second gate electrode; forming a first sidewall spacer structure at said first gate electrode and a second sidewall spacer structure at said second gate electrode, said first and second sidewall spacer structures having a first type of stress; forming a first contact etch stop layer above said first transistor, said first contact etch stop layer having said first type of stress; and forming a second contact etch stop layer above said second transistor, said second contact etch stop layer having a second type of stress other than said first type, wherein forming said second contact etch stop layer comprises selecting a magnitude of said second type of stress so as to at least compensate for said first type of stress in said second sidewall spacer structure.