Patent ID: 6356119
Filing Date: 2002-03-12
Classification: G06F,G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a first node; a second node; an input node; an output node; a first signal path from said input node to said output node; a second signal path from said input node to said output node; and first to third stages each of which includes a PMOS transistor and a NMOS transistor serially connected to the PMOS transistor, source-drain paths of both the PMOS transistor and the NMOS transistor being between said first node and said second node; wherein said first signal path includes said first stage and said second signal path includes said first to third stages; and wherein absolute values of threshold voltages of a PMOS transistor and an NMOS transistor of at least one of the second and the third stages are higher than absolute values of threshold voltages of the PMOS transistor and the NMOS transistor of the first stage.