Patent ID: 6654284
Filing Date: 2003-11-25
Classification: G11C,H01L

Abstract:
A pseudo-dynamic operating method for a channel write/erase flash memory cell, a word line voltage VWL, a source line voltage VSL, and a bit line voltage VBL being applied, respectively, to control gate, source terminal, and drain terminal of the flash memory cell, wherein an N well, a deep P well and an N substrate are positioned in order under the flash memory cell, and a well voltage VP is applied to the deep P well, and wherein the N well and the deep P well constitute a parasitic capacitor during programming the flash memory cell, the pseudo-dynamic operating method comprising:charging the drain terminal and the parasitic capacitor to a level of the bit line voltage VBL when initiating a program mode; and utilizing the charged parasitic capacitor to eject electrons from a floating gate of the flash memory cell to the drain terminal during the program mode.