Patent ID: 8368195
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A semiconductor device comprising a plurality of stacked semiconductor chips each having a major surface and a plurality of electrodes including through-via electrodes and external connecting electrodes, the electrodes provided in the semiconductor chips being connected by solder to form connections, thereby providing electric conduction between the semiconductor chips, wherein said semiconductor device is configured so that said major surfaces of said semiconductor chips are substantially parallel to one another, wherein a recess is formed in at least one surface of the through-via electrode in each of the connections of the interconnected semiconductor chips, wherein the through-via electrodes are each a hollow through-via electrode having a hollow portion, and wherein the recess comprises a tapered portion formed co-axially with the through-via electrode, and wherein the solder is provided in the interior thereof with a core formed of a material higher in melting point than the solder, the core being adapted to engage in the tapered portion to permit, during melting of the solder between the semiconductor chips, control of the connection height between said semiconductor chips and alignment of said semiconductor chips while said solder is in a melted state to prevent tilting of the major surfaces of the semiconductor chips relative to one another.