Patent ID: 7185250
Filing Date: 2007-02-27
Classification: G01R

Abstract:
1. A test access port formed in an integrated circuit on a substrate, comprising: A. a test access port controller having a test mode select input, a test clock input, and control outputs; B. a multiplexer having a test data output, a first input, and a second input; C. data registers having control inputs connected to the control outputs of the controller, a test data input and a test data output, the test data output being connected to the first input of the multiplexer; D. an instruction register having control inputs connected to the control outputs of the controller, a test data input and a test data output, the instruction register being connected between the second input of the multiplexer and the test data input of the data register; and E. a scan cell separate from the instruction register connected in series with the instruction register between the second input of the multiplexer and the test data input of the data register, the scan cell having a control input connected to the control inputs of the instruction register.