Patent ID: 6210175
Filing Date: 2001-04-03
Classification: H01L,H01R,H05K

Abstract:
A circuit board capable of accepting a semiconductor integrated circuit device, said integrated circuit device having a plurality of splayed terminations arranged for surface mounting of the semiconductor integrated circuit device, the circuit board comprising:a. a mounting position on a first side of the circuit board for a first one of said semiconductor integrated circuit devices permitting fusion bonding of the semiconductor integrated circuit device for purposes of attachment to the circuit board;b. a socket mounted on a second, opposite side of the circuit board and including a plurality of vertically oriented electrical connectors, the socket capable of accepting at least one additional semiconductor integrated circuit device in an inverted position whereby the splayed terminations extend outwardly and in a generally upward direction from a body portion of said additional semiconductor integrated circuit device, the splaved terminations being in ohmic contact with the electrical connectors when the additional semiconductor integrated circuit device is mounted in the socket, the electrical connectors including a surface material sufficiently soft so as to deform upon engagement with the splayed terminations, thereby facilitating ohmic contact, the socket in vertical alignment with the first one of the semiconductor integrated circuit devices, whereby said vertical alignment provides commonality of a plurality of circuit connections between the first one of the semiconductor integrated circuit devices and said additional integrated circuit device in the socket; andc. the socket including at least two sidewalls extending in a vertical direction, said electrical connectors being formed in an inside surface of said sidewalls, said sidewalls having a plurality of partitions separating said electrical connectors and extending in a vertical direction and inwardly toward the additional semiconductor integrated circuit device, thereby providing a guide for the splayed terminations of the additional semiconductor integrated circuit device.