Patent ID: 8751817
Filing Date: 2014-06-10
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a ROM (Read Only Memory) having a validity verification program stored therein; an auxiliary storage device including a plurality of storage areas having a plurality of target verification data stored therein; an execution unit configured to perform a validity verification process on the plural target verification data in accordance with the validity verification program; wherein an order of priority is assigned to the plural target verification data, wherein the plural storage areas have addresses that is recognizable by the execution unit, wherein the execution unit is configured to determine validity of each of the plural target verification data based on the order of priority until one of the plural target verification data is determined to be valid, wherein the plural target verification data includes superordinate target verification data and subordinate target verification data having the order of priority that is lower than the order of priority of the superordinate target verification data, wherein the subordinate target verification data does not include a target verification data having the highest order of priority among the plural target verification data, wherein the auxiliary storage device is configured to have a recovery program of the superordinate target verification data stored in at least one of the subordinate target verification data, wherein the ROM and the execution unit constitute a configuration of a SoC (System-on-a-Chip) or a configuration of a ASIC (Application Specific Integrated Circuit).