Patent ID: 8481990
Filing Date: 2013-07-09
Classification: H01L

Abstract:
1. A nonvolatile memory element comprising: a substrate; a lower electrode layer formed on said substrate; a first variable resistance layer formed on said lower electrode layer and comprising a metal oxide; a second variable resistance layer formed on said first variable resistance layer and comprising a metal oxide having smaller oxygen deficiency than oxygen deficiency of said first variable resistance layer; an upper electrode layer formed on said second variable resistance layer; an interlayer insulating layer formed to cover at least side surfaces of said lower electrode layer, said first variable resistance layer, and said second variable resistance layer; a stress buffering region layer for buffering a stress on said upper electrode layer, said stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of said upper electrode layer and having a stress smaller than a stress of an insulating layer used as said interlayer insulating layer; a contact extending to said upper electrode layer; and a wiring pattern connected to said contact, and said stress buffering region layer is an insulating layer having porous structure.