Patent ID: 6297105
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method of forming asymmetric source/drain for a DRAM cell, comprising the steps of:providing a substrate having a gate structure formed thereon;forming a first mask layer on the substrate, wherein the first mask layer exposes one side of the gate structure;proceeding a first ion-implanting process to form a first doped region on the side of the gate structure exposed;removing the first mask layer;forming a second mask layer on the substrate, wherein the second mask layer exposes another side of the gate structure;proceeding a second ion-implanting process to form a second doped region on the side of the gate structure exposed by the second mask layer to form a bit line contact region with an abrupt junction;removing the second mask layer;proceeding a high temperature rapid thermal process;forming a spacer on opposite sides of the gate structure; andforming a SAC doped region below said first doped region to form a node contact region with a graded junction.