Patent ID: 7221592
Filing Date: 2007-05-22
Classification: G11C

Abstract:
1. A method for programming a multiple level NAND non-volatile memory device comprising a plurality of rows coupled to wordlines and a plurality of columns, each coupled to a bitline, the method comprising: programming a first cell, coupled to a selected wordline and a selected bitline, with a first state having a highest threshold voltage distribution of a plurality of states each having a different threshold voltage distribution; and programming remaining cells that are coupled to the selected wordline in a decreasing order of threshold voltage distributions wherein the selected wordline is biased with a programming voltage and unselected wordlines of the plurality of wordlines are biased at a constant predetermined voltage that is less than the programming voltage and greater than 0V, the selected bitline is biased at 0V, and unselected bitlines are biased at an inhibit voltage.