Patent ID: 9086890
Filing Date: 2015-07-21
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a division unit including a normalization circuit and a plurality of divide engines, wherein the normalization circuit is configured to normalize a set of operands of a divide instruction, and wherein each divide engine is configured to operate on a respective normalized set of operands in parallel with one or more others of the plurality of divide engines, and wherein each respective normalized set of operands is received from the normalization circuit and is associated with a respective divide instruction; and a scheduler unit configured to dispatch instructions to a plurality of execution units including the division unit, wherein the scheduler unit is configured to dispatch a divide instruction to the division unit in response to receiving a first indication that the division unit has completed operation on a previously dispatched divide instruction, wherein the first indication is indicative that one of the plurality of divide engines is available to receive another divide instruction.