Patent ID: 6675319
Filing Date: 2004-01-06
Classification: G11C

Abstract:
A memory chip, module, or subsystem assembly comprising:(a) a plurality of assembly memory bus lines for address, data, and control signals; (b) a first group of at least one primary memory sub-assemblies, each having a plurality of sub-assembly memory bus lines and a plurality of sub-assembly memory cells partitioned into a plurality of sub-assembly memory blocks each containing at least one memory cells; (c) a second group of at least one supporting memory sub-assemblies, each having a plurality of sub-assembly memory bus lines and a plurality of sub-assembly memory cells partitioned into a plurality of sub-assembly memory blocks each containing at least one memory cells; (d) a memory status unit containing a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, programmable storage cells controlled by internal or external control signals, or a combination of the above items; (e) a memory access control unit which includes a data routing unit; wherein the primary memory sub-assemblies contain at least one sub-assembly that has one or more defective memory cells; wherein the supporting memory sub-assemblies also contain at least one sub-assembly that has one or more defective memory cells; wherein, for at least one memory access to a memory address, the memory access control unit assigns at least a first assembly data bit to a first sub-assembly data bit in the first group of memory sub-assemblies and at least a second assembly data bit to a second sub-assembly data bit in the second group of memory sub-assemblies, at the appropriate memory timing cycles, according to the memory access address; wherein the memory status unit contains information for the memory access control unit to determine the data bit assignments.