Patent ID: 6959058
Filing Date: 2005-10-25
Classification: H04L

Abstract:
1. A data recovery apparatus, comprising: a phase locked loop (PLL) for generating a plurality of phase clock signals each having a different delay time with respect to a clock signal; an oversampler for M times oversampling serial input data in response to the plurality of phase clock signals and outputting a plurality of data bits in parallel, wherein M is an integer; a level transition detector for receiving the parallel data bits output from the oversampler, detecting logic level transitions between successive bits of the parallel data bits and generating a detection result as one of M transition signals; a transition accumulator for accumulating a number of times each one of the M transition signals is generated and outputting a transition accumulation signal corresponding to the transition signal whose generation frequency is highest, the transition accumulation signal comprising one of M transition accumulation signals, wherein the transition accumulator comprises a reset signal generator for performing a logical combination of the M transition accumulation signals and generating an accumulation reset signal for resetting the transition accumulator in response to the logical combination result; a state selector for generating a state signal in response to the transition accumulation signal output from the transition accumulator, wherein the state signal is used for selecting corresponding data bits among the parallel data bits output from the oversampler; and a data selector for receiving the parallel data bits, utilizing the state signal to select from the parallel data bits those data bits having sampling positions corresponding to the state signal, and outputting the selected data bits in parallel.