Patent ID: 8238132
Filing Date: 2012-08-07
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array having a plurality of memory cells arranged in arrays; a plurality of bit lines configured in columns of the memory cells; a plurality of word lines configured in rows of the memory cells; a plate line having one of a configuration in which first electrodes of the plurality of memory cells are included in the plate line and a configuration in which the first electrodes are connected to the plate line; a column switch configured to connect a selected bit line and a data access line; and a pre-charge portion configured to perform a pre-charge operation to pre-charge a non-selected bit line not selected by the column switch to a potential of the plate line, wherein each of the plurality of memory cells includes a memory element including a memory layer sandwiched between the first electrode and a second electrode and having a resistance value that varies with an application of a voltage between the first electrode having one of a configuration to be included in the plate line and a configuration to be connected to the plate line and the second electrode, and an access transistor connected between the second electrode and one of the plurality of bit lines provided in a corresponding column and having a gate connected to one of the plurality of word lines provided in a corresponding row.