Patent ID: 6639846
Filing Date: 2003-10-28
Classification: G11C

Abstract:
A memory circuit configuration, comprising:word lines disposed in a column form; bit lines disposed in a row form; sense amplifiers; and a multiplicity of memory cells, each of said memory cells including a single transistor and a storage capacitor; said memory cells being connected to and activated by said word lines, said bit lines connecting said memory cells to said sense amplifiers, upon activating a respective word line of said word lines, at least one of said bit lines being a first bit line and being associated with a respective memory cell of said memory cells, electrically connecting said respective memory cell to a respective first sense amplifier of said sense amplifiers for reading-out a datum, a second sense amplifier of said sense amplifiers during the reading-out on said first bit line putting an adjacent one of said bit lines being a second bit line adjacent to said first bit line actively at a precharge potential; said second bit line being associated with said second sense amplifier of said sense amplifiers, said second amplifier being disposed in a different activation array at an opposite side of a field of bit lines with respect to said first sense amplifier; one side of each of said sense amplifiers being associated with a pair of said bit lines, a bit line of a second of said sense amplifiers being disposed between a pair of bit lines of first of said sense amplifiers.