Patent ID: 8835996
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. An integrated circuit configuration, comprising: a substrate; a diffusion region formed in the substrate, wherein the diffusion region comprises a channel region, a source region and a drain region; a gate structure formed over the substrate and spanned across the diffusion region; an extension conductor structure formed over the substrate and contacted with the diffusion region, wherein a portion of the extension conductor structure is directly in contact with a surface of the substrate, and another portion of the extension conductor structure extends externally to a first position along the surface of the substrate, wherein the first position is outside the diffusion region, and an extending direction of the extension conductor structure from the diffusion region to the first position is different from an extending direction from the source region to the drain region; a dielectric layer formed over the substrate, the gate structure and the extension conductor structure; a contact structure penetrating through the dielectric layer to be contacted with the first position of the extension conductor structure; and a metal conductor line formed on the dielectric layer and contacted with the contact structure.