Patent ID: 6788092
Filing Date: 2004-09-07
Classification: G01R

Abstract:
In combination,an IC package having a plurality of first contact pads and a plurality of first conductors connecting selected ones of said first contact pads to define a first circuit portion; and a test board having a plurality of second contact pads and a plurality of second conductors connecting selected ones of the second contact pads to define a second circuit portion, the test board further comprising a plurality of pairs of test pads, each of the test pads being connected to one of said second contact pads; wherein, when the IC package is mounted on the test board by a plurality of solder bumps each being disposed between and soldered to one of the first contact pads and one of the second contact pads. the first and second circuit portions are connected to define a conductive path that passes through all of the solder bumps which are connected in series in said conductive path by said first and second contact pads and conductors, and a closed circuit is formed from a segment of said conductive path when each of said pairs of test pads is probed, said closed circuit including a number of said second contact pads all of which are physically arranged along a single straight line; and wherein said conductive path includes two spiral sections extending around a central area of the test board, an end of one of said spiral sections is connected to an end of the other spiral section by one of said second conductors, the other ends of said spirals sections are connected to two major test pads so that the entire conductive path belong to a closed circuit when said major test pads are probed.