Patent ID: 9209310
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having an insulating surface; a gate electrode layer over the substrate having the insulating surface; a gate insulating layer over the gate electrode layer; a source electrode layer and a drain electrode layer over the gate insulating layer; and an oxide semiconductor layer over the source electrode layer and the drain electrode layer, wherein the source electrode layer and the drain electrode layer are formed with a stack comprising a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are in contact with the oxide semiconductor layer, wherein the first metal layer is formed using a metal layer of a metal element selected from Se and Te, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination, wherein the first metal layer is between the oxide semiconductor layer and the second metal layer, wherein the second metal layer is between the first metal layer and the gate insulating layer, wherein the second metal layer is formed using a metal layer of a metal element selected from Al, Ti, Mo, and W, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination, wherein a first edge of the first metal layer is aligned with an edge of the oxide semiconductor layer, and wherein the oxide semiconductor layer is not in contact with a top surface of the second metal layer.