Patent ID: 7170812
Filing Date: 2007-01-30
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including data bit memory cells, arranged in rows and columns, storing a plurality of data, each of said data bit memory cells having a data storage unit storing and holding data, and a readout port unit reading out data from said data storage unit, and said memory cell array further including flag bit memory cells, arranged in each row, storing inverted information of storage data of said data bit memory cell, a plurality of readout word lines, arranged in a row direction of said memory cell array, connected, in each row, to a readout port of said data bit memory cell and said flag bit memory cell, a plurality of readout bit lines, arranged in a column direction of said memory cell array, connected, in each column, to a readout port of said data bit memory cell, a data input circuit writing a data indicating that data in a row of said data bit memory cell is an inverted data, to the row of said flag bit memory cell, and writing an inverted data in the row of data input signal, to the row of said data bit memory cell, when the amount of current flowing in said data bit memory cell in the reading operation of said data input signal of one of logic values written in said data bit memory cell is greater than that of said data input signal of the other of logic values, and when the number of one of logic values is greater than the number of the other of logic values in the row of said data input signal, a data output circuit reading out an inverted data in a row of said data bit memory cell, when data of said flag bit memory cell is the data indicating an inversion of the data in the row.