Patent ID: 7526056
Filing Date: 2009-04-28
Classification: H03L

Abstract:
1. In a delay locked loop circuit that includes a delay line configured to receive a clock signal and pass the clock signal through an adjustable number of delay elements, a phase detector circuit configured to sample a phase of a clock signal at an output terminal of the delay line and received at a feedback clock input of the phase detector and the clock signal received at a reference input of the phase detector, the phase detector configured to generate a first signal when the phase of the clock signal at the feedback clock input of the phase detector is not approximately equal to the phase of the reference clock signal at a reference input of the phase detector and the variance is in a first direction, wherein the phase detector is further configured to generate a second signal when the phase of the clock signal at the feedback clock input of the phase detector is not approximately equal to the phase of the reference clock signal at the reference input of the phase detector and the variance is in a second direction that is opposite the first direction, a method for adjusting the number of delay elements through which the clock signal passes in the delay line, the method comprising the following: when operating in an operational mode after pseudo-lock, when operating in a reset mode before pseudo-lock, an act of allowing signals from the phase detector to adjust the number of delay elements through which the clock signal passes in the delay line without waiting for the predetermined number of multiple consecutive first signals or for the predetermined number of multiple consecutive second signals.