Patent ID: 7350048
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. A memory subsystem comprising: a host configured to initiate memory accesses; a plurality of memory modules; and a plurality of router nodes; wherein the host is coupled to a first router node of the plurality of router nodes by a channel comprising a southbound link and a northbound link; and wherein each of the plurality of router nodes is configured to be coupled to a subsequent one of the plurality of router nodes through a first southbound link and a first northbound link; and wherein each of the plurality of nodes further includes an interface configured to be coupled to one of said memory modules or a router node in a next level of a hierarchy of levels; wherein said host is configured to initialize each of the plurality of nodes to correspond to a particular level and position within the hierarchy of levels; wherein subsequent to initializing each of the nodes and during system operation, in performing a memory access to one of said plurality of memory modules, the host is configured to: