Patent ID: 6161206
Filing Date: 2000-12-12
Classification: G01R,G06F

Abstract:
A test pattern generator for a semiconductor integrated circuit tester, comprising:a first read/write memory for receiving and storing test pattern data in a plurality of blocks, said first read/write memory including DRAM,a second read/write memory for storing checking data in a plurality of units, said second read/write memory including SRAM and each unit of checking data stored in the second read/write memory bearing a predetermined relationship to a corresponding block received by the first read/write memory,at least one sequencer for addressing the first read/write memory for reading the blocks of test pattern data in a predetermined order and addressing the second read/write memory for reading the units of checking data from the second read/write memory, anda validating means for receiving a block of test pattern data read from the first read/write memory and the corresponding unit of checking data read from the second read/write memory and providing an output which indicates whether the unit of checking data is in said predetermined relationship with the block.