Patent ID: 7388407
Filing Date: 2008-06-17
Classification: H03L

Abstract:
1. A variable delay buffer comprising: a buffer circuit configured to receive an input clock signal and to generate a slew-rate limited buffer output signal with approximately linear rising edges and a first phase delay with respect to the input clock signal; a multiplier circuit configured to receive a first control signal associated with a first offset voltage for approximately canceling the first phase delay and to generate a second offset voltage by scaling the first offset voltage by a delay factor; and a summing circuit configured to adjust a zero-crossing of the slew-rate limited buffer output signal to generate an output clock signal with a second phase delay with respect to the input clock signal, wherein the zero-crossing of the slew-rate limited buffer output signal is adjusted by adding the second offset voltage to the slew-rated limited buffer output signal and the second phase delay is variable by adjusting the delay factor to vary the second offset voltage.