Patent ID: 6448831
Filing Date: 2002-09-10
Classification: H03K

Abstract:
A TSPC-1 flip-flop circuit comprisingan input stage having a first input node and a first output node, said input stage precharging said first output node to a first supply voltage during a first part of a clock period and selectively discharging said first output node to a second supply voltage in response to data signals applied in a second part of said clock period, a middle stage having a second output node, said middle stage inverting signals at said first output node during said second part of said clock period for application to said second output node, and an output stage comprising a first device connected between said first supply voltage and a first intermediate node, said first device selectively assuming a conducting state in response to signals at said second output node, a second device connected between said first intermediate node and a third output node, said second device selectively assuming a conducting state in response to a transition from said second part of a clock period to said first part of a succeeding clock period, a third device connected between said third output node and a second intermediate node, said third device selectively assuming a conducting state in response to signals on said first output node, and a fourth device connected between said second intermediate node and said second supply voltage, said fourth device selectively assuming a conducting state in response to signals at said second output node, a correction circuit for substantially eliminating glitches at said third output node resulting from charge accumulated at said first intermediate node by connection of said first supply voltage to said first intermediate node prior to said second device assuming said conducting state.