Patent ID: 7317633
Filing Date: 2008-01-08
Classification: G11C,H01L

Abstract:
1. A method for protecting NROM devices from charge damage during process steps, the method comprising: providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor (T 1 ) and an NMOS transistor (T 4 ), the PMOS transistors (T 1 ) sharing a common deep N well and the NMOS transistors (T 4 ) connected to a P well, providing an N+ tap connected to said N well and connecting the N+ tap to a positive voltage clamping device; and connecting all the P wells together to a common P+ taps, connecting the P+ tap to a negative voltage clamping device; wherein during process steps, the negative and positive voltage clamping devices direct leakage current to a ground potential: providing antenna structure and at least one access transistor for protection during top-level metal formation, and wherein said antenna structure comprises a dummy word line connected to a word line driver.