Patent ID: 6432773
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of fabricating a memory cell of a semiconductor device, comprising the steps of:(a) depositing a first conductive layer having a top surface and a side surface; and (b) forming an ONO film adjacent to the top surface and the side surface of said first conductive layer, said step of forming the ONO film comprising the steps of: (i) depositing a first SiO2 layer; (ii) depositing a first Si3N4 layer on the first SiO2 layer; (iii) depositing a second SiO2 layer on the first Si3N4 layer; (iv) depositing a first protective photoresist layer on a portion of the second SiO2 layer; (v) anisotropically etching away at least the portion of the second SiO2 layer and a portion of the first conductive layer not covered by the first protective photoresist layer; (vi) removing the first protective photoresist layer; (vii) thermally growing a third SiO2 layer on the side surface of the first conductive layer; (viii) depositing a second Si3N4 layer on the second and third SiO2 layers; (ix) depositing a fourth SiO2 layer on the second Si3N4 layer; and (x) anisotropically etching the fourth SiO2 layer so as to leave a portion of said fourth SiO2 layer on a side surface of the second Si3N4 layer.