Patent ID: 6573192
Filing Date: 2003-06-03
Classification: H01L

Abstract:
In a method for forming two gate oxide layers having different thicknesses on a surface of a CMOS or MOSFET semiconductor body, the improvement of avoiding resist residue on the surface of the gate oxide upon regrowth and avoiding the narrow processing window caused by using low energy implantations for advance designs that use about 0.18 &mgr;m design rules, comprising:a) thermally oxidizing the surface of the semiconductor body to form a silicon oxide layer thereon; b) providing a patterned photoresist layer over a first portion of the silicon oxide layer to protect same from plasma effects; c) subjecting a portion of silicon oxide not covered by the patterned photoresist layer to a plasma highly selective to silicon oxide, said plasma comprising HBr, O2, and He, said HBr having a flow rate of 50 sccm, said O2 having a flow rate of 3 sccm, and said He having a flow rate of 100 sccm; d) removing the patterned photoresist layer and cleaning the surface of said silicon oxide layer with a silicon cleaning solution; e) subjecting the silicon oxide layer to an etchant to remove portions not covered by the patterned photoresist and partially etching a portion of the first silicon oxide layer protected from the plasma by said removed patterned photoresist layer; and f) thermally oxidizing the semiconductor body to simultaneously form a regrown second silicon oxide layer on the exposed portion of the semiconductor surface to increase the thickness of the portion of the first silicon oxide layer protected by the patterned photoresist layer and form a second silicon oxide layer thinner than the first silicon oxide layer.