Patent ID: 6028465
Filing Date: 2000-02-22
Classification: H01L

Abstract:
Electrostatic protection circuitry for a MOS integrated circuit semiconductor device, said device having active and passive integrated components thereon for executing various electronic functions, and having input and output connections for inputting and outputting signals and power to and from said device, comprising:a first tier coupled to an input pad of the MOS integrated circuit semiconductor device and comprising at least a first diode coupled to an external ground line and a second diode coupled to an external power supply voltage line and serially connected to the first diode at a first node, said first and second diodes providing a first shunt for an ESD charge on the input pad between the external ground line and the external power supply voltage line;a first low impedance resistive element coupled to the first tier at the first node to provide a first additional ESD charge shunt in the event the first tier does not entirely shunt the ESD charge;a second tier coupled to the first low impedance resistive element and comprising a third diode serially connected at a second node to a first bi-directional capacitive element between the external ground line and the external power supply voltage line, said third diode and said first capacitive element for providing a second shunt for the ESD charge between the external ground line and the external power supply voltage line; andan output tier coupled to the second tier between the external ground line and the external power supply voltage line and coupled to a buffer of the MOS integrated circuit semiconductor device.