Patent ID: 8126087
Filing Date: 2012-02-28
Classification: H03M,H04L

Abstract:
1. A DC offset correction circuit, comprising: a DC offset detector generating a detection voltage based on a result of a comparison of a first reference voltage and a voltage difference between signals input to the DC offset detector; a comparator comparing a second reference voltage and the detection voltage and a third reference voltage and the detection voltage and outputting first and second comparison signals, respectively, as a result of the comparisons; and an up/down counter performing an up or a down count operation in response to one of the first or second comparison signals and, as a result of the up or down count operation, outputting a signal that causes at least one control signal for canceling a DC offset in a signal input to a receiver to be generated, wherein the comparator comprises: a first comparator comparing the detection voltage and the second reference voltage and outputting the first comparison signal; and a second comparator comparing the detection voltage and the third reference voltage and outputting the second comparison signal, and wherein the comparator increases a first pulse width of the first comparison signal to a first logic level of the first comparison signal during a first time in which the detection voltage reaches the second reference voltage and increases a second pulse width of the second comparison signal to a first logic level of the second comparison signal during a second time in which the detection voltage reaches the third reference voltage.