Patent ID: 8018066
Filing Date: 2011-09-13
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a wiring substrate including a core substrate having first and second surfaces opposed to each other, and first and second build-up substrates on the first and second surfaces of the core substrate, respectively; a semiconductor chip comprising a substrate which has third and fourth surfaces opposite to each other, and semiconductor elements on the third surface, a multilayer structure on the third surface, and pad electrodes on the multilayer structure, the multilayer structure including a wiring layer, a silicon oxide layer, and an interlayer insulating film, and the interlayer insulating film having an electrical constant lower that that of the silicon oxide film the semiconductor chip being on the first build-up substrate such that the third surface of the substrate faces the first build-up substrate and the semiconductor elements are electrically connected with the second wiring layers via first bump electrodes between the pad electrodes of the semiconductor chip and the first build-up substrate; a resin layer between the semiconductor chip and the first build-up substrate and between the first bump electrodes; and second bump electrodes on the second build-up substrate and electrically connected with the third wiring layers of the second build-up substrate, wherein diameters of the second and third through holes of the first and second build-up substrates are smaller than diameters of the first through holes of the core substrate, the first insulating layer of the core substrate, and the second and third insulating layers of the first and second build-up substrates, contain glass cloths, respectively, and a thickness of the glass cloths in each of the first and second build-up substrates is smaller than a thickness of the glass cloths in the core substrate.