Patent ID: 6975665
Filing Date: 2005-12-13
Classification: H04B

Abstract:
1. An ultra wide bandwidth timing generator, comprising: a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit; and a phase accumulator circuit coupled to the low frequency control generation circuit and configured to provide a phase-ramp control signal to the low frequency control generation circuit for fine tuning of the agile timing signal in frequency; wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals; the low frequency control generation circuit generates a plurality of low frequency control signals; and the modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals.