Patent ID: 6100737
Filing Date: 2000-08-08
Classification: H04L

Abstract:
A scanner circuit for digital signals with a high data rate, comprising:a scanner stage having a first input supplied with a digital data signal and a second input supplied with an auxiliary timing signal, said scanner stage scanning said digital data signal dependent on said auxiliary timing signal and emitting a digital scanned signal at an output of the scanner stage;an edge discriminator having a first input connected to the output of the scanner stage and being supplied at said first input with said digital scanned signal, and having a second input supplied with said auxiliary timing signal, said edge discriminator generating a control pulse directly upon each occurrence of at least one of each positive edge and each negative edge of said digital scanned signal;a digital oscillator having a first input supplied with said control pulse from said edge discriminator, and having a second supplied input with said auxiliary timing signal, said digital oscillator generating a data timing signal dependent on said control signal and said auxiliary timing signal; anda timing adjustment stage having a first input connected to an output of said edge discriminator, and having a second input supplied with said data timing signal from said digital oscillator, said timing adjustment stage scanning a signal at the output of said edge discriminator, dependent on said data timing signal, and generating a final output signal.