Patent ID: 6324653
Filing Date: 2001-11-27
Classification: G06F,H03K

Abstract:
An integrated circuit comprising at least one microprocessor driven by an internal clock signal and at least one internal peripheral circuit, each internal peripheral circuit being activated selectively by at least one microprocessor to perform an operation,wherein said integrated circuit further comprises means for matching the period of said internal clock signal to the operating time of the activated internal peripheral circuit, andthe means for matching comprise:means, in each internal peripheral circuit, for performing a second operation in parallel to said operation controlled by the microprocessor, the time of said second operation being equal to or slightly greater than the time of the operation controlled by the microprocessor,a clock signal generation circuit to generate a primary clock signal that takes the form of a series of pulses dictating a processing speed on the microprocessor, anda circuit for the conversion of the primary clock signal to eliminate the pulses of said primary clock signal during said second operation in order to match the period of said internal clock signal to the operating time of the activated internal peripheral circuit, said conversion circuit delivering the internal clock signal.