Patent ID: 6747484
Filing Date: 2004-06-08
Classification: H03F,H03G

Abstract:
A limiter circuit, comprising:a rectification circuit coupled to an input of the limiter circuit, such rectification circuit producing a voltage having a predetermined average level, such level being a function of an input signal fed to the input of the limiter circuit; a voltage divider circuit coupled to the rectification circuit for producing an output voltage having a level proportional to the input signal; an enhancement mode field effect transistor having a gate electrode fed by the output voltage produced by the voltage divider circuit, such transistor having drain and source electrodes, one of such source and drain electrodes being coupled to an output of the limiter circuit and the other one of the source and drain electrodes being coupled to a reference potential; and a transmission line coupled between the input of the limiter and the output of the limiter circuit, such transmission line having an electrical length n&lgr;/4, where &lgr; is the nominal operating wavelength of the limiter circuit and n is an odd integer.