Patent ID: 9029859
Filing Date: 2015-05-12
Classification: G02F,H01L

Abstract:
1. A display device comprising: a first transistor comprising a first semiconductor layer including a first channel formation region and a second channel formation region; a second transistor comprising a second semiconductor layer; a first wiring electrically connected to one of a source and a drain of the first transistor; a second wiring electrically connected to one of a source and a drain of the second transistor; a third wiring including a first region; a first electrode including a second region that overlaps with at least a part of the first semiconductor layer; and a first pixel electrode electrically connected to the other of the source and the drain of the first transistor, wherein the first electrode is electrically connected to the other of the source and the drain of the second transistor, wherein the first region and at least a part of the second semiconductor layer overlap with each other, wherein the first region is capable of being a gate of the second transistor, wherein the second region is capable of being a gate of the first transistor, wherein the gate of the first transistor is electrically connected to the other of the source and the drain of the second transistor, wherein a longitudinal direction of the first wiring intersects with a longitudinal direction of the third wiring, wherein a longitudinal direction of the second wiring intersects with the longitudinal direction of the third wiring, wherein a longitudinal direction of the first pixel electrode intersects with the longitudinal direction of the third wiring, wherein a channel width direction of the first transistor intersects with the longitudinal direction of the third wiring, wherein a channel width of the first channel formation region is longer than a channel length of the first channel formation region, wherein the first semiconductor layer includes a region between the first channel formation region and the second channel formation region, wherein a longitudinal direction of the region intersects with the longitudinal direction of the third wiring, wherein the first wiring includes a third region, wherein at least a part of the first electrode and at least a part of the first semiconductor layer overlap with each other in a fourth region, and wherein the third region and the fourth region overlap with each other.