Patent ID: 6816421
Filing Date: 2004-11-09
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a first nonvolatile memory cell and a second nonvolatile memory cell, each of the nonvolatile memory cells holding data; first and second bit lines which are connected correspondingly to the first and second nonvolatile memory cells; first and second column selection transistors connected correspondingly to the first and second bit lines; a first column resetting and bit line testing transistor a drain of which is connected to a first node to which the first and second column selection transistors are commonly connected; a sense amplifier which is selectively connected to the first node and senses and amplifies a cell data appeared on the first node; and a control circuit which controls to turn the first column resetting and bit line testing transistor on to reset an electric potential of the first node, after data of one of the first and second nonvolatile memory cells selected by turning one of the first and second column selection transistors on has been sensed by the sense amplifier in a first time duration, and controls to electrically separate the sense amplifier from the first node while the first and second column selection transistors and the first column resetting and bit line testing transistor are turned on simultaneously in a second time duration.