Patent ID: 6243305
Filing Date: 2001-06-05
Classification: G11C

Abstract:
Redundant circuitry for a memory device including a memory cell array having a plurality of memory row/column lines, each memory row/column line being initially mapped to a distinct address value, the redundant circuitry comprising:programmable circuitry for indicating a first address value corresponding to a first memory row/column line associated with a defect, and a second address corresponding to a second memory row/column line associated with a defect; andshifter circuitry, responsive to the programmable circuitry, for remapping the first address value and address values which are greater than the first address value each to a distinct memory row/column line in the memory cell array initially mapped to another address value relative to the corresponding remapped address value, and remapping at least one third address value which is greater than the second address value to a memory row/column line initially mapped to an address value which was higher relative to the third address value.