Patent ID: 6448640
Filing Date: 2002-09-10
Classification: H01L,H05K

Abstract:
A chip assembly, comprising:a ball array layout on a substrate, the ball array layout comprising: a plurality of buffer traces each having a perimeter; and a plurality of ball pads arranged in columns and in rows that are perpendicular to the columns, each column and row being upon the substrate, wherein at least one of said plurality of ball pads is the terminus of a respective electrically conductive trace, and having an approximate center that is: about equally spaced from adjacent ball pads in the respective column and in the respective row; and aligned with the other ball pads in the respective column and the other ball pads in the respective row; wherein: the columns include a first column and a second column; each ball pad in the first column has a perimeter that is parallel to the perimeter of a first length of one said plurality of buffer traces; and at least one ball pad in the second column is adjacent to a second length of the perimeter of at least one buffer trace; and a semiconductive-material-comprising chip attached to said substrate.