Patent ID: 6034905
Filing Date: 2000-03-07
Classification: G01R,G11C

Abstract:
An apparatus for testing a semiconductor memory device, comprising:a signal generating unit for generating an input signal to a semiconductor memory device under test, an address signal for designating an address of a memory cell of said semiconductor memory device under test to which the input signal is supplied, an expected value signal for indicating an expected value of an output obtained when inputting the input signal to said memory cell of the address in said semiconductor memory device under test, and an address signal having an address space which is set based on according to classification of memory cells;a judging unit for judging whether said memory cell of the address in said semiconductor memory device under test is good or defective by comparing the output signal outputted by said semiconductor memory device under test with the expected value signal in accordance with the input of the input signal to said memory cell of the above address, and generating a judgement signal about a result of the judgement; anda defect analyzing memory unit including a defect analyzing memory for storing the judgement signal in a predetermined address corresponding to an address space of said memory cell.