Patent ID: 6437790
Filing Date: 2002-08-20
Classification: G06F

Abstract:
An image processing system comprising:a memory circuit which stores image data; and a processing circuit which effects data processing operation with respect to first image data and second image data both read out from said memory circuit, wherein said first image data corresponds to a first area of a display area and said second image data corresponds to a second area of said display area, said first image data is allocated within a first address area starting from a first arbitrary position in said first address area, said first address area having a start address at a first word boundary, and said second image data is allocated within a second address area starting from a second arbitrary position in said second address area, said second address area having a start address at a second word boundary, wherein said processing circuit includes a memory access circuit which accesses by a first data read operation data of said first address area from said memory circuit by successive accesses including a first access which is carried out from said first word boundary to a next word boundary immediately succeeding said first word boundary and a second access which is carried out from said next word boundary to a further next word boundary immediately succeeding said next word boundary, said first word boundary and said next word boundary define an access operation of a word unit of predetermined fixed-length data from said memory circuit, said predetermined fixed-length data being aligned with said word boundaries, wherein said memory access circuit accesses by a second data read operation data of said second address area from said memory circuit by other successive accesses including a first access which is carried out from said second word boundary to a next word boundary immediately succeeding said second word boundary and a second access which is carried out from said next word boundary to a further next word boundary immediately succeeding said next word boundary, said second word boundary and said next word boundary define an access operation of a word unit of said predetermined fixed-length data from said memory circuit, wherein said processing circuit receives each of said first address area including said first image data and said second address area including said second image data from said memory circuit, and aligns said first arbitrary position of said first image data with said second arbitrary position of said second image data, and wherein said processing circuit executes a logic processing operation on said first image data aligned with said second image data, and said second image data, and transfers said operated on image data to said memory access circuit for writing said operated on image data to said second start address of said second address area at which said data of said second address area including at least a part of said second image data was read by said memory access circuit.