Patent ID: 6662173
Filing Date: 2003-12-09
Classification: G06F,Y10S

Abstract:
An apparatus for partitioning a cache memory, comprising:a cache memory having a plurality of addressable blocks; first and second components coupled to said cache memory to access said cache memory; a register coupled to said cache memory to store a first mask value and a second mask value, wherein access to addressable blocks of said cache memory is controlled based on said first mask value; a processor coupled to said cache memory, wherein said first component includes execution of instructions by said processor from a first thread and said second component includes execution of instructions by said processor from a second thread; wherein an eviction array is provided indicating a least recently used addressable block of said cache memory; wherein said first mask value is an auxiliary mask value and said auxiliary mask value represents which of the addressable blocks of said cache memory are available for eviction; and wherein the second mask value selects which bits of said eviction array are used in controlling which of the addressable blocks of said cache memory are available for eviction.