Patent ID: 6194928
Filing Date: 2001-02-27
Classification: H03K,H03L

Abstract:
An integrated circuit, comprising:a delay unit having an input for receiving an input signal, an output for outputting an output signal delayed with respect to the input signal, and a signal path between said input and said output;said delay unit having first delay elements each having a first delay time and second delay elements each having a second delay time greater than the first delay time;a control unit connected to said delay unit for adjusting a delay of said delay unit, said control unit adjusting the delay of said delay unit by establishing a number of said first and said second delay elements in series in the signal path between said input and said output of said delay unit;said control unit, first, incrementally increasing or reducing a number of said second delay elements in the signal path, and thereby altering an actual value of the delay in a direction towards a setpoint value of the delay until the setpoint value is exceeded;said control unit, subsequently, incrementally reducing or increasing, respectively, a number of said first delay elements in the signal path, and thereby altering the actual value of the delay in a direction towards the setpoint value until the setpoint value once more crossed;said control unit, in response to subsequent changes in one of the setpoint value and the actual value of the delay, incrementally altering the number of said first delay elements in the signal path, while keeping the number of said second delay elements in the signal path constant; andwherein a sum of the first delay times of all of said first delay elements is at least three times greater than the second delay time.