Patent ID: 7688127
Filing Date: 2010-03-30
Classification: G06F,Y02D

Abstract:
1. A method for generating an output clock signal having an output cycle, the method comprises: adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter then the sleep cycle; counting short cycles and sleep cycles; and generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the output clock signal; wherein the generating comprises activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.