Patent ID: 8004910
Filing Date: 2011-08-23
Classification: G11C

Abstract:
1. A data transfer system comprising: a plurality of system components, each of the system components being a circuit block or a device; and a memory shared and used by the system components, wherein the memory comprises a plurality of memory areas, each of the memory areas holding data corresponding to a plurality of memory addresses, and a memory control circuit outputting the memory addresses and the data held corresponding to the memory addresses in synchronization with a clock, each of the system components comprises a decoder decoding a memory address outputted by the memory control circuit so as to determine whether said memory address corresponds to one of the memory addresses that are assigned in advance to the system component, and a register receiving the data outputted by the memory control circuit in synchronization with the clock depending on a result of the decoding by the decoder, and the memory control circuit starts the outputting of the memory addresses and the data in response to at least part of the data held in the memory areas being rewritten.