Patent ID: 8617951
Filing Date: 2013-12-31
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, said method comprising: forming a conductive layer for a floating gate above a semiconductor layer, a gate insulating film being interposed between the conductive layer and the semiconductor layer; forming a sacrificial layer having an opening on the conductive layer; removing a portion of the conductive layer by etching using the sacrificial layer as a mask to form an exposed portion of the conductive layer, the exposed portion of the conductive layer having a sloped-shaped portion at a lateral end of the exposed portion, the sloped-shaped portion having a tip portion; forming a first spacer on the exposed portion of the conductive layer and the opening of the sacrificial layer; forming a second spacer on the first spacer, the second spacer having an etching rate lower than that of the first spacer; selectively removing the conductive layer by using the first and the second spacers as a mask; removing the vertical side portions of the first spacer to expose the sloped-shaped portion of the conductive layer; forming a tunnel insulative film on the sloped-shaped portion of the conductive layer; forming a flat portion on the exposed portion of the conductive layer other than on the tip portion of the conductive layer; forming a second diffusion layer on the semiconductor layer at a position corresponding to the opening; forming a plug over the second diffusion layer; siliciding an upper portion of the plug, wherein the first spacer includes a first silicon oxide material and the second spacer includes a second silicon oxide material, wherein an etching rate of the second silicon oxide material is less than an etching rate of the first silicon oxide material; forming a control gate that is insulated from the conductive layer by the tunnel insulative film; disposing a first silicide layer on a surface of the control gate; forming a side wall insulative film on a side surface of the control gate; forming an active region in the semiconductor layer adjacent a side of the side wall insulative film; disposing a second silicide layer on the active region; wherein, following the forming of the first spacer, the forming of the second spacer on the first spacer is performed, wherein following the forming of the second spacer on the first spacer, an etching of the first spacer and the second spacer is performed, and wherein the etching of the first spacer and the second spacer comprises a single etching; and wherein a film thickness of the second spacer above the flat portion of the conductive layer is greater than a film thickness of the first spacer above the flat portion of the conductive layer.