Patent ID: 6294936
Filing Date: 2001-09-25
Classification: H03C,H03K,H03L

Abstract:
A clock generator phase-locked loop, comprising:a reference frequency source for providing a reference frequency;a phase comparator for producing a control signal based on a periodic comparison of a phase difference between respective signals provided to a first input and a second input of the phase comparator, the reference frequency being operatively coupled to the first input;a voltage-controlled oscillator for generating an output frequency based on the control signal provided by the phase comparator;a feedback divider which receives and divides the output frequency to provide a divider output which is operatively coupled to the second input of the phase comparator; anda modulation circuit for injecting a dither signal into the control signal provided by the phase comparator to modulate the output frequency, a period of the dither signal being equal to or an integer fraction of a phase comparison period of the phase comparator.