Patent ID: 7978014
Filing Date: 2011-07-12
Classification: H03L

Abstract:
1. A fast-locking digital PLL frequency synthesizer, comprising: a loop filter with an automatically-adjusted loop gain, for generating a control signal, and automatically adjusting loop parameters according to a PLL locking procedure; a controllable oscillator, coupled to said loop filter, for generating a corresponding oscillating frequency according to said control signal; a feedback phase integration circuit, coupled to said controllable oscillator, for estimating a phase information of said controllable oscillator; a reference phase integration circuit, for generating a reference phase information; and a phase detector, coupled to said loop filter, said feedback phase integration circuit, and said reference phase integration circuit, for comparing the error between the phase of said controllable oscillator and said reference phase; wherein said locking procedure is categorized into a first stage and a second stage respectively, and wherein when said locking procedure is at the first stage, said locking procedure comprises the steps of: a locking state control circuit generates a control signal for setting a adjustable magnification device on a forward-path to be a predetermined magnification; setting the adjustable magnification device on a integral-path to be zero; and changing its state to be the second stage when the output of said phase detector is within a predetermined range.