Patent ID: 7888214
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A method of fabrication of a semiconductor device comprising: providing a substrate having a PMOS region and a NMOS region; providing a PMOS transistor in the PMOS region and a NMOS transistor in the NMOS region, wherein forming a stress layer having a first stress over the substrate, the stress layer covering the PMOS region and the NMOS region; forming a dielectric layer over the stress layer; forming PMOS S/D contact holes having a PMOS S/D contact layout design through the stress layer in the PMOS region to expose portions of the PMOS S/D regions and NMOS S/D contact holes having a NMOS S/D contact layout design through the stress layer in the NMOS region to expose portions of the NMOS S/D regions, wherein forming contact plugs in the PMOS contact holes and the NMOS contact holes.