Patent ID: 6317810
Filing Date: 2001-11-13
Classification: G06F

Abstract:
A central processing unit (CPU) of a computer, comprising:a data cache, internal to the CPU, for storing data specified by an address request, the data cache having an input port;a prefetch cache, internal to the CPU, coupled to a processing unit of the CPU in parallel with said data cache such that a first input port of the prefetch cache and the input port of the data cache receive a first address request from the processing unit in parallel, said prefetch cache generating a prefetch cache hit signal in response to said first address request; andan external memory controller circuit, internal to the CPU, responsive to said prefetch cache hit signal, for retrieving and loading into said prefetch cache data specified by a prefetch address derived from said address request;wherein:said prefetch cache further comprises a second input port for receiving a second address request from the processing unit; andsaid first and second address requests are simultaneously processed by said prefetch cache.