Patent ID: 8045667
Filing Date: 2011-10-25
Classification: H03K,H03M,H04L

Abstract:
1. A deserializer comprising: a first register configured to load an external sync data packet and a serial data packet sequentially in response to a recovery clock signal; a sync detector outputting a sync detect signal based on whether the sync data packet is synchronized with the recovery clock signal; a lost bit storage unit detecting a data bit of the sync data packet or the serial data packet corresponding to an activation point of the sync detect signal from the sync detector and outputting the detected data bit as a lost bit; a second register configured to load the serial data packet from the first register; a packet combiner combining the lost bit and the serial data packet from the second register in response to the sync detect signal; and a third register outputting the data packets from the packet combiner in parallel, wherein the first register is configured to load the sync data packet and the serial data packet in response to rising/falling edges of one cycle of the recovery clock signal in units of data bits, and the first register comprises: a first flip-flop group including a plurality of flip-flops connected in cascade and storing odd-numbered data bits of the sync data packet in response to a rising edge of the recovery clock signal; and a second flip-flop group including a plurality of flip-flops connected in cascade and storing even numbered data bits of the sync data packet in response to a falling edge of the recovery clock signal, and wherein the first register is configured to load a first to last data bits of the sync data packet if the first data bit of the sync data packet is synchronized with the rising edge of the recovery clock signal, and the first register is configured to load the second data bit of the sync data packet to a first data bit of the serial data packet if the first data bit of the sync data packet is synchronized with the falling edge of the recovery clock signal.