Patent ID: 7999590
Filing Date: 2011-08-16
Classification: H03K

Abstract:
1. A flip-flop comprising: a pulse generator, the pulse generator including a latch configured to latch input data with a high level equal to a third level lower than the second level and output output data with a high level that is converted into the second level in response to the pulse signal, wherein the receiving portion includes a NAND gate configured to receives the input clock signal and performs a NAND operation on a feedback signal and the input clock signal, and to outputs an operation result, and the generating portion includes an inverter configured to invert a signal received from the NAND gate and outputs the pulse signal, and includes a PMOS transistor and a NMOS transistor connected in series between a first supply voltage having the first level and a ground voltage, in which the input clock signal and the pulse signal are applied to gates of the PMOS transistor and the NMOS transistor, respectively.