Patent ID: 6535446
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A boost circuit for boosting an output node voltage comprising:a first transistor having a current path coupled between a first node and a second node, and a gate coupled to a third node; a second transistor having a current path coupled between a fourth node and the third node, and a gate coupled to the output node; a third transistor having a current path coupled between the third node and ground, and a gate coupled to a fifth node; a fourth transistor having a current path coupled between a sixth node and a seventh node, and a gate coupled to the output node; a fifth transistor having a current path coupled between the seventh node and ground, and a gate coupled to the fifth node; a first capacitor coupled between the second node and the output node; and a second capacitor coupled between the third node and the seventh node, wherein the first, fourth, fifth, and sixth nodes receive control signals.