Patent ID: 6356481
Filing Date: 2002-03-12
Classification: G11C

Abstract:
A row decoder for a nonvolatile memory comprised of a plurality of word lines, said row decoder comprising a first reference line set at a first operating potential switchable at least between a first reference potential and a programming potential higher than said first reference potential, a second reference line set at a second operating potential switchable at least between a second reference potential lower than said first reference potential and an erase potential lower than said second reference potential, and a third reference line set at a third operating potential equal, at least in preset operating conditions, to said first reference potential, and, for each one of said word lines, a respective biasing circuit receiving on an input a row selection signal switchable between said third operating potential and said second reference potential and supplying at an output a biasing signal for the respective word line switchable between said first and said second operating potentials; each said biasing circuit comprising an output driver circuit connected between said first and said second reference lines and supplying on an output said biasing signal, wherein each said biasing circuit further comprises a level translator circuit connected between said second and said third reference lines, receiving on an input said row selection signal and supplying on an output a control signal for said driver circuit switchable between said first and said second operating potentials.