Patent ID: 8761916
Filing Date: 2014-06-24
Classification: G10L,H04Q

Abstract:
1. A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein the DSP is adapted to: receive an N-sample data frame comprising digital samples corresponding to an audio signal; and perform tone detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the tone detection comprises: for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (b) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel; and for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (c) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel, wherein V