Patent ID: 7900017
Filing Date: 2011-03-01
Classification: G06F

Abstract:
1. A computer system comprising: a memory to store a plurality of page tables and a plurality of remap tables; a processor, including partitioning logic and a first translation lookaside buffer, the partitioning logic to partition the memory by dividing the memory into a plurality of contiguous regions and allocating each one of the plurality of contiguous regions to each one of a plurality of virtual machines, the first translation lookaside buffer to cache page table entries from the plurality of page tables; an input/output device; and a chipset, coupled to the processor and the input/output device, including a second translation lookaside buffer to cache remap table entries from the plurality of remap tables, the second translation lookaside buffer and the plurality of remap tables to circumvent the partitioning by remapping memory addresses from the processor and the input/output device at page level granularity, where page size is less than region size.