Patent ID: 6125431
Filing Date: 2000-09-26
Classification: G06F

Abstract:
A single-chip microcomputer having input terminals and output terminals, in combination with an external ROM having input terminals that are connected to the output terminals of the single-chip microcomputer and having output terminals that are connected to the input terminals of the single-chip microcomputer,wherein the external ROM stores instruction data; andwherein the single-chip microcomputer comprises:an internal ROM which stores instruction data;an internal/external switching signal generation circuit for generating an internal/external switching signal having a first digital level or a second digital level;means for reading instruction data out of the internal and external ROMs;a selector to select either instruction data that has been read out of the internal ROM or instruction data that has been read out of the external ROM according to the level of the internal/external switching signal;an instruction register to receive the instruction data selected by the selector, the selected instruction data being fetched into the instruction register by a fetch control signal; andmeans for emitting the fetch control signal to the instruction register at a timing which depends on the level of the internal/external switching signal, the means for emitting comprising a data fetch signal generation circuit which generates a data fetch signal, means connected to one of the output terminals of the single-chip microcomputer for generating a further signal, and means responsive to the internal/external switching signal for passing either the data fetch signal or the further signal to the instruction register as the fetch control signal.