Patent ID: 6228716
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method of making a flash memory MOS transistor comprising:providing a substrate;forming a first dielectric layer over said substrate;etching one or more openings in said first dielectric layer, wherein said openings define the locations of flash memory MOS transistors;depositing a material layer over said substrate to fill said openings;patterning said material layer to define source and drain regions adjacent to a remaining portion of said material layer;doping said source and drain regions with dopants;depositing a second dielectric layer over said source and drain regions;removing said remaining portion of said material layer to define channel regions in said substrate, wherein said channel regions are disposed between said source and drain regions;forming a tunneling dielectric layer over said channel regions;depositing a first conductive layer over said tunneling dielectric layer;everywhere removing said first conductive layer except over said channel regions;forming a third dielectric layer over said first conductive layer;etching contact openings over said source and drain regions;forming contacts over said third dielectric layer in said channel region, and in said contact openings.