Patent ID: 8341566
Filing Date: 2012-12-25
Classification: G06F

Abstract:
1. A method of a digital processor for generating and evaluating a table model for circuit simulation in N dimensions, the method comprising the steps of: (a) employing, by said circuit simulation, at least one mathematical expression for describing a device and using an unstructured N-dimensional grid by said table model for effecting approximations of said expression and to establish boundaries of the N-dimension utilizing a function domain; (b) performing, via the digital processor, an accuracy partitioning operation to establish a plurality of accuracy partitions; said at least one mathematical expression being satisfied within each respective accuracy partition of said plurality of accuracy partitions within a predetermined error criteria; (c) performing a continuity partitioning operation to establish a set of continuity partitions; said set of continuity partitions ensuring continuity of solutions of said at least one mathematical expression across N-dimension boundaries separating respective adjacent accuracy partitions of said plurality of accuracy partitions; (d) performing a N-dimensional grid refining operation to configure said set of continuity partitions to assure monotonic solutions of said at least one mathematical expression in said set of continuity partitions; and (e) if a continuity partition of said set of continuity partitions is altered pursuant to said N-dimensional grid refining operation, returning to step (c), else proceeding to next step.