Patent ID: 7861116
Filing Date: 2010-12-28
Classification: G06F

Abstract:
1. A method comprising: accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, wherein each portion of the circuit comprises at least one logic gate, and each of the plurality of user-selected properties includes an identifier for the at least one logic gate and a value of an input to the logic gate, and at least one of the plurality of user-selected properties identifies a logic gate receiving an input from another logic gate of the circuit; accepting a plurality of user-selected erroneous outputs, each of which corresponds to one of the plurality of user-selected set of properties; executing a simulation of the circuit for each of the plurality of user-selected properties; detecting in the output for the simulation at least one of the plurality of user-selected erroneous outputs of the portions of the circuit for the corresponding one of the plurality of user-selected properties; displaying to a user the output for the simulation of the circuit for each of the plurality of user-selected properties if the number of detected erroneous outputs is greater than a predetermined threshold; and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties.