Patent ID: 7511341
Filing Date: 2009-03-31
Classification: H01L

Abstract:
1. A transistor comprising: a semiconductor substrate; a buried oxide layer formed within said substrate; a trench isolation region formed within said substrate; a source region; a drain region; a channel region; passivated trap site regions comprising trap sites of at least said buried oxide layer and said channel region, said passivated trap site regions formed by (a) applying different voltages to said source region and said drain region to electrically stress and thereby remove a first passivating species from said trap sites, and (b) after removing said first passivating species from said trap sites, passivating said trap sites with a second passivating species; and a transistor gate formed over said channel region, wherein, due to steps (a) and (b), a percentage of said trap sites passivated by said second passivating species near said drain region is greater than a percentage of said trap sites passivated by said second passivating species near said source region.