Patent ID: 8997031
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A timing delay characterization method performed by at least one processor, said method comprising: dividing a signal path between an input terminal and an output terminal of a semiconductor circuit into an input stage, a processing stage, and an output stage, the input stage coupled to the input terminal, the output stage coupled to the output terminal, and the processing stage coupled in series between the input stage and the output stage; performing a simulation of an operation of the input stage at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage; performing a simulation of an operation of the processing stage to obtain an intrinsic timing delay associated with the processing stage, wherein the intrinsic timing delay is obtained separately from the extrinsic input timing delays; performing a simulation of an operation of the output stage at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage; and generating or populating a timing delay date store based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.