Patent ID: 6470439
Filing Date: 2002-10-22
Classification: G06F,H04L

Abstract:
A FIFO memory control circuit, comprising:a write address circuit for generating a write address which is an operation address; a read address circuit for generating a read address which is another operation address; a memory which receives a write permission signal, a read permission signal, a write clock signal, and a read clock signal and which has a memory capacity of a predetermined number of words, wherein, while the write permission signal is asserted, data is written into an address in the memory designated by the write address in synchronization with the write clock signal, and while the read permission signal is asserted, data is read from an address in the memory designated by the read address in synchronization with the read clock signal; a first count control enable signal generation circuit for generating a first count control enable signal based on a first clock signal and a least significant bit of a said operation address corresponding to a second clock signal, the first clock signal being one of the write clock signal and the read clock signal which has the higher frequency, and the second clock signal being one of the write clock signal and the read clock signal which has the lower frequency; and an up-down counter which has a count value and receives a count-up enable signal, a count-down enable signal, and the first clock signal, wherein while the count-up enable signal is asserted, the count value is incremented in synchronization with the first clock signal, and while the count-down enable signal is asserted, the count value is decremented in synchronization with the first clock signal, wherein the first count control enable signal is one of the count-up enable signal and the count-down enable signal.