Patent ID: 6838323
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A method of manufacturing a non-aligned MOSFET transistor for ESD protection comprising the steps: providing a substrate having a source diffusion region and a drain diffusion region; implanting a first resistor well implant as a source diffusion into said source diffusion region; implanting a second resistor well implant as a drain diffusion into said drain diffusion region, thereby forming a channel region that connects said first and second resistor well implants; forming a non-self aligned gate over said first and second resistor well implants therein forming a first overlap region of said non-self aligned gate over said first resistor well implant and a second overlap region of said non-self aligned gate over said second resistor well implant; exposing a portion of each said first resistor well implant and said second resistor well implant; and implanting lightly doped implants only into upper portions of each said exposed portions of said first resistor well implant as said source diffusion and said second resistor well implant as said drain diffusion such that said lightly doped implants reside entirely within said first and second resistor well implants, wherein said second overlap region extends over said second resistor well implant to a different extent than said first overlap region extends over said first resistor well implant to form a variable capacitance between said gate and said second resistor well implant.