Patent ID: 6427200
Filing Date: 2002-07-30
Classification: G06F

Abstract:
A multiple changeable addressing mapping circuit for converting an input logic address of a field array in a data array into an output physical address, the circuit comprising:at least an address mapper for processing the conversion between the input logical address and the output physical address, wherein the address mapper comprises: a base shift register for recording a starting physical address of the field array to be mapped; a logical base register for recording a starting logical address of the field array to be mapped; a field length register for recording the length of a field; a recording length register for recording the length of the array; a subtracter for subtracting a logical base address stored in the logical base register from the input logic address; a division/remainder generator for dividing output value of the subtracter by a field length stored in the field length register; a multiplier for multiplying the array length of the record length register by a quotient of the division/remainder generator; and an adder for adding a starting physical address stored in the base shift register, a remainder of the division/remainder generator and an output value of the multiplier together to have an output physical address; a mapper selector for selecting an address mapper to output physical address; and a control and interface circuit for setting the base shift register, logical base register, field length register and recording length register, and controlling the address mapper and mapper selector.