Patent ID: 7098691
Filing Date: 2006-08-29
Classification: G01R,H01L,H03K

Abstract:
1. A semiconductor device comprising: a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up tablet; said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer; a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer; a customizable clock distribution structure, wherein said customizable clock distribution structure is customized by said custom via layer; and a customizable trimmer cell to fine tune said clock distribution structure, wherein said customizable trimmer cell is customized by said custom via layer.