Patent ID: 6233700
Filing Date: 2001-05-15
Classification: G06F

Abstract:
In a system comprising:a central processing unit;a storage device connected to said central processing unit;a cache memory connected to said central processing unit and having an accessing speed higher than that of said storage device;a set of a plurality of cache pages provided in said cache memory; andan LRU table provided in said cache memory and constituted by a plurality of entries adapted for controlling said cache pages; wherein said LRU table is divided into a protection area and an examination area;a method for management of a cache page comprising the steps of:(a) that in case of a cache failure, a cache failure entry is stored in said examination area and, on occurrence of overflow of said examination area with entries, an entry at an LRU position of said examination area is extracted and driven out of said cache memory, while the cache failure entry is added to an MRU position of said examination area;(b) that in case of a cache hit in said protection area, the cache hit entry is extracted and moved to an MRU position in said protection area and, on occurrence of overflow of said protection area with entries, an entry at an LRU position of said protection area is moved to an MRU position of said examination area; and(c) that in case of a cache hit in said protection area, entries in said protection area are interchanged in sequence so that the cache hit entry will assume an MRU position in said protection area;wherein the improvement resides in:(d) that the most recent accessing time point of each entry is stored and held from one entry to another;(e) that, if cache failure has occurred when the central processing unit accesses said cache memory for data writing or data reading into/out of said storage device, the stored time point for an entry at the LRU position of said protection area and that for an entry at the LRU position of said examination area are compared to each other;(f) that, if the former time point is earlier, the entry at the LRU position in said protection area is moved to the MRU position in said examination area to reduce the size of said protection area, the cache failure entry is added to the MRU position in said examination area, and an entry at the LRU position in said examination area is driven out of the cache memory; and(g) that, if the latter time point is earlier, an entry at the LRU position in said examination area is extracted and driven out of the cache memory and, in its place, the cache failure entry is added to the MRU position in said examination area.