Patent ID: 9035630
Filing Date: 2015-05-19
Classification: G05F

Abstract:
1. A method to achieve leakage current compensation for an ultra low power LDO regulator without impacting topology of LDO regulation loop and loop compensation scheme, comprising the following steps: (1) providing a LDO regulator and a PTAT type sink current generator; (2) deploying the PTAT type sink current generator on a same silicon and same chip as the LDO regulator, wherein the PTAT type sink current generator comprises a port for a bias current and a port for a control voltage, wherein said control voltage is configured to switch off via a switch all transistors that might cause power consumption while the junction temperature is below a threshold; and (3) providing sink current by the PTAT type sink current generator as required to compensate leakage current of LDO pass transistor, wherein the sink current and leakage current depend upon common junction temperature of both LDO and sink current generator and wherein the output voltage of the LDO is independent of leakage current.