Patent ID: 7019580
Filing Date: 2006-03-28
Classification: H03F

Abstract:
1. A composite NMOS device having a source connection, a drain connection and a gate connection for conducting an operating current comprising: a first NMOS device having a source, a drain and a gate; a second NMOS device having a source, a drain and a gate; the source of the second NMOS device being connected to the drain of the first NMOS device; the gates of the first and second NMOS devices being coupled together through a bias control, the bias control providing a different bias to the gates of the first and second NMOS devices; the gate of the first NMOS device being coupled to the gate connection, the drain of the second NMOS device being coupled to the drain connection and the source of the first transistor being coupled to the source connection; the second NMOS device having a lower threshold voltage than the first NMOS transistor.