Patent ID: 9203460
Filing Date: 2015-12-01
Classification: H03F,H04B

Abstract:
1. A transceiver, comprising: a voltage controlled oscillator to generate a first sinusoidal signal and a second sinusoidal signal having a 90° (λ/4) phase delay with respect to the first sinusoidal signal; a mixer to receive the first and second sinusoidal signals; a first buffer to receive the first sinusoidal signal, the first buffer to convert the first sinusoidal signal to a first rectangular wave signal; a second buffer to receive the second sinusoidal signal, the second buffer to convert the second sinusoidal signal to a second rectangular wave signal; a logic circuit to receive the first and second rectangular wave signals, the logic circuit to perform logical operation processing on the first and second rectangular wave signals to generate a logic signal with a duty cycle of 25% which contains 25% high level intervals and 75% low level intervals; and an power amplifier to receive the logic signal, the power amplifier to perform amplification operation based on the logic signal; wherein the power amplifier includes a filter circuit, a first transistor, and an output matching circuit, the output matching circuit has a first inductor and a first capacitor, the first inductor has one end connected to a higher voltage source and the other end connected to one end of the first capacitor, the first capacitor has the other end connected to one end of the filter circuit, and the first transistor is provided between the other end of the first inductor and a lower voltage source, the first transistor has a gate receiving the logic signal, the first transistor outputs an amplified signal.