Patent ID: 7764099
Filing Date: 2010-07-27
Classification: H03L

Abstract:
1. A semiconductor integrated circuit device comprising: a DLL circuit that receives an external clock from an input terminal thereof and produces an internal clock at an output terminal thereof in synchronism with the external clock, the DLL circuit operating on a power supply voltage applied thereto; a voltage comparator circuit configured to compare a first voltage related to the power supply voltage with a reference voltage, the voltage comparator circuit producing a comparison result signal that takes a first logic level when the first voltage is smaller than the reference voltage, and a second logic level when the first voltage is equal to or larger than the reference voltage; a reset node supplied with a reset signal; and a hold circuit coupled to the voltage comparator circuit and the reset node to receive the comparison result signal and the reset signal, the hold circuit resetting the DLL circuit in response to the reset signal to bring the DLL circuit from an active state to an initial state and releasing the DLL circuit in response to the second logic level of the comparison signal to bring the DLL circuit from the initial state to the active state.