Patent ID: 6772251
Filing Date: 2004-08-03
Classification: G06F,H04L

Abstract:
A communication system comprising:a) a single system clock line; b) a single serial data line, operable for bi-directional data transfer; and c) a first device and a second device, operable to perform bit interleaved communication with each other, said devices coupled to said system clock line and said single serial data line, wherein said bi-directional data transfer comprises of simultaneous bit interleaved transfer between said first and second devices, and wherein each of said devices further comprises: an output enabler, coupled to said data line, operable for controlling bit interleaved data transmission and reception; a clock divider, coupled to said system clock line, operable for regulating said receiving and transferring of data; and a shift register, coupled to said clock divider and said output enabler, operable for receiving bit interleaved data and transferring byte data to and from a memory area.