Patent ID: 6467004
Filing Date: 2002-10-15
Classification: G06F

Abstract:
A multi-processor having M microprocessors and a repeater integrally fabricated on a semiconductor chip, comprising:M signal transmission buses on the semiconductor chip assigned to M microprocessors (M being a positive integer); N (&gE;1) signal transmission pipeline stages for signal transmission between each of the M microprocessors and the repeater including a pipeline latch wherein N is given by N&gE;tx/(Tâˆ’(tk+tl+ts)), wherein T is a pipeline cycle time, tk is a clock skew, tl is a delay time of the pipeline latch, and tx is a total wiring delay time of said signal transmission buses; and 2 N (N&gE;1) signal transmission pipeline stages for signal transmission between two of said M microprocessors.