Patent ID: 6284578
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method of fabricating an IC device on a substrate comprising a plurality of MOS transistors and a plurality of other IC components, said transistors each having a raised source electrode, a raised drain electrode and dual gate electrodes, said transistors and said other IC components interconnected by way of a plurality of self-aligned contact windows, said method comprising the steps of:forming on said substrate a plurality of isolation regions to separate a plurality of active regions;doping said substrate with a dopant to form a plurality of doped wells in said substrate;forming a first gate structure on one of said active regions and a second gate structure on one of said isolation regions adjacent to said active region, said first gate structure and said second gate structure each comprising a gate electrode layer of a first conductor material and a first dielectric layer, said second gate structure having a larger surface area than said first gate structure;forming a second dielectric layer on the portions of said substrate other than those portions covered by said first and second gate structures;forming a mask layer on said second gate structure and on the portions of said second dielectric layer other than those portions of said second dielectric layer adjacent to said first gate structure;removing the portions of said second dielectric layer adjacent to said first gate structure to form a plurality of trenches next to said first gate structure;removing said mask layer;depositing a second conductor material in said trenches to form a plurality of conductor columns;removing said first dielectric layers of said first and second gate structures;doping said gate electrode layers of said first and second gate structures with a second dopant to form said dual gate electrodes;forming said raised source electrode and said raised drain electrode;forming a plurality of self-aligned silicide layers on said conductor columns and said gate electrode layers;forming a third dielectric layer on top of said gate electrode layers to cover said gate electrode layer of said first gate structure entirely and said gate electrode layer of said second gate structure partially and to form said plurality of self-aligned contact windows; andinterconnecting said conductor columns and said second gate electrode layer to other said transistors and said other IC components by way of said plurality of self-aligned contact windows.