Patent ID: 6490208
Filing Date: 2002-12-03
Classification: G11C

Abstract:
A column redundancy circuit for a semiconductor memory device, comprising:a plurality of DQ region units including a memory cell array unit having a plurality of cells arranged in cell banks and sharing a local data bus and a global data bus, a column decoder unit for generating a column decoding signal for selecting one of the cells, a write driver unit for driving data input through a global I/O line to the global data bus, and a read sense amp unit for amplifying data inputted through the global data bus, and transmitting the data to the global I/O line; and a repair region unit provided at one side of the DQ region units capable of substituting for regular cells regions of any memory cell bank, and including a repair cell array unit having a plurality of repair cells sharing the local data bus and the global data bus, N (an integer) column decoder units for generating a column decoding signal for selecting one of the repair cells, N write driver units for driving data input through the global I/O line to a repair global data bus, N read sense amp units for amplifying data inputted through the repair global data bus, and transmitting the data to the global I/O line, N DQ selection fuse box units for programming information of the DQ region unit having a defect cell among the plurality of DQ region units, and N multiplexer and demultiplexer units for switching one write driver unit among the N write driver units, one read sense amp unit among the N read sense amp units, and the global I/O line according to output signals from the DQ selection fuse box units.