Patent ID: 6470414
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A bank selector circuit for a simultaneous operation non-volatile memory device with a flexible bank partition architecture, comprising:(a) a bank selector encoder, comprising: (i) a partition indicator circuit comprising a plurality of partition boundary indicator terminals capable of designating a partition of memory into an upper memory bank and a lower memory bank at a memory partition boundary selected from a plurality of predetermined partition boundaries; (ii) a ROM array comprising a plurality of ROM cells arranged in a plurality of columns and rows, each row of the ROM cells coupled to a respective one of the partition boundary indicator terminals; (iii) a plurality of inverters arranged in a plurality of columns, each column of the inverters coupled to a respective one of the columns of the ROM cells; and (iv) a plurality of bank selector code outputs, coupled to the respective columns of the inverters, capable of outputting a plurality of code bits of a bank selector code; (b) a plurality of memory address inputs capable of receiving a plurality of memory address bits of a memory address; (c) a logic bit P determining circuit coupled to receive a first plurality of the code bits from a first plurality of the bank selector code outputs, the logic bit P determining circuit comprising: (i) a plurality of PMOS transistors arranged in a plurality of columns, each column of the PMOS transistors having a first current path terminal capable of receiving a DC common voltage and a second current path terminal opposite the first current path terminal, the PMOS transistors comprising a first plurality of gates coupled to a first plurality of the memory address inputs and a second plurality of gates coupled to the first plurality of the bank selector code outputs; (ii) a plurality of NMOS transistors arranged in a plurality of columns, each column of the NMOS transistors having a first current path terminal capable of being grounded and a second current path terminal opposite the first current path terminal, the NMOS transistors comprising a first plurality of gates coupled to the first plurality of the memory address inputs and a second plurality of gates coupled to the first plurality of the bank selector code outputs; and (iii) a logic bit P output connected to the second current path terminals of the columns of the PMOS and NMOS transistors; (d) a logic bit Q determining circuit coupled to receive a second plurality of the code bits from a second plurality of the bank selector code outputs, the logic bit Q determining circuit comprising: (i) a plurality of PMOS transistors arranged in a plurality of columns, each column of the PMOS transistors having a first current path terminal capable of receiving a DC common voltage and a second current path terminal opposite the first current path terminal, the PMOS transistors comprising a first plurality of gates coupled to the first plurality of the memory address inputs and a second plurality of gates coupled to the second plurality of the bank selector code outputs; (ii) a plurality of NMOS transistors arranged in a plurality of columns, each column of the NMOS transistors having a first current path terminal capable of being grounded and a second current path terminal opposite the first current path terminal, the NMOS transistors comprising a first plurality of gates coupled to the first plurality of the memory address inputs and a second plurality of gates coupled to the second plurality of the bank selector code outputs; and (iii) a logic bit Q output connected to the second current path terminals of the columns of the PMOS and NMOS transistors; (e) a logic bit O determining circuit coupled to receive a third one of the code bits from a third one of the bank selector code outputs, the logic bit O determining circuit comprising: (i) a plurality of PMOS transistors, comprising a first plurality of gates coupled to a second plurality of the memory address inputs and a second gate coupled to the third bank selector code output; and (ii) a plurality of NMOS transistors, comprising a first plurality of gates coupled to the second plurality of the memory address inputs and a second gate coupled to the third bank selector code output, some of the PMOS transistors and some of the NMOS transistors having current path terminals connected together forming a logic bit O output; and (f) an output logic circuit coupled to the logic bit O, P and Q outputs of the logic bit O, P and Q determining circuits, respectively, the output logic circuit having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.