Patent ID: 7884026
Filing Date: 2011-02-08
Classification: H01L

Abstract:
1. A method of fabricating a dual damascene structure on a semiconductor wafer, the semiconductor wafer sequentially comprising a substrate, a conductive layer, a dielectric layer comprising a via hole, a hard mask comprising a trench pattern larger than the via hole in bird's eye view, and a sacrificial layer disposed on the hard mask, the dielectric layer, and the via hole so as to completely cover the hard mask comprising the trench pattern, the dielectric layer and the via hole, the method being performed in an etching chamber and comprising at least two sequential steps of: performing a first etching process, the first etching process using an oxygen based plasma gas to etch a part of the sacrificial layer and expose the hard mask, the dielectric layer, and a part of the via hole; performing a second etching process, the second etching process using a tetrafluoromethane (CF performing a third etching process, the third etching process using an oxygen based plasma gas to remove the sacrificial layer to expose the conductive layer through the via hole.