Patent ID: 6190964
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating a stacked capacitor, which comprises the following steps:providing a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed in the substrate;forming a stack of alternating first conductive layers of the first conductivity type and second conductive layers of the second conductivity type, with respective insulation layers interposed therebetween, on the semiconductor substrate;selectively etching the second conductive layers at a first edge region of the stack and undercutting the second conductive layers with respect to the first conductive layers to form undercuts;forming insulation bridges at the undercuts to provide continuous insulation of the second conductive layers towards the first edge region;forming a first spacer of a conductive material at the first edge region of the stack, and connecting the first spacer to the semiconductor substrate and to the first conductive layers;selectively etching the second conductive layers at a second edge region of the stack and undercutting the second conductive layers with respect to the first conductive layers to form undercuts;forming an etching stop layer at the undercuts;etching the first conductive layers at the second edge region of the stack and undercutting the first conductive layers with respect to the second conductive layers to form second undercuts;removing the etching stop layer;forming insulation bridges at the second undercuts for providing continuous insulation of the first conductive layers towards the second edge region; andforming a second spacer of a conductive material at the second edge region of the stack, and connecting the second spacer to the well and to the second conductive layers.