Patent ID: 7692177
Filing Date: 2010-04-06
Classification: C23C,H01L,Y10T

Abstract:
1. A memory element comprising: an insulating layer formed over a semiconductor substrate; a first electrode layer formed over said insulating layer; a dielectric layer formed over said first electrode layer; a first chalcogenide glass layer formed over said dielectric layer; a first metal-containing layer formed over at least a portion of said first chalcogenide glass layer; a second chalcogenide glass layer formed over at least a portion of said first metal-containing layer; a second metal-containing layer formed over at least a portion of said second chalcogenide glass layer; and a second electrode layer formed over at least a portion of said second metal-containing layer, wherein said first and second electrode layers of the memory element are in electrical communication with each other, wherein said first metal-containing layer comprises a metal that diffuses into said first chalcogenide glass layer to enable the memory element to switch from a first resistance state to a second resistance state when a voltage potential is applied across the first electrode layer and the second electrode layer, and wherein said second metal-containing layer comprises a metal that diffuses into said second chalcogenide glass layer to enable the memory element to switch from the first resistance state to the second resistance state when a voltage potential is applied across the first electrode layer and the second electrode layer.