Patent ID: 7039143
Filing Date: 2006-05-02
Classification: H03K

Abstract:
1. A circuit for determining a time difference between edges of a first digital signal and of a second digital signal, the circuit comprising: a first input for receiving a first signal; a plurality of basic elements connected in succession and in series, each one of said plurality of basic elements having an input, a control input, and a storage unit with an output, said plurality of basic elements including a first basic element having an input connected to said first input for receiving the first signal, said input of each one of said plurality of basic elements, except that of said first basic element, connected to said output of a respective preceding one of said plurality of basic elements; a second input for receiving a second signal, said second input connected to said control input of each one of said plurality of basic elements; each one of said plurality of basic elements, except for said first basic element, configured such that if the second signal has a first level, said storage unit will store a signal level that is already stored in said storage unit of an immediately preceding one of said plurality of basic elements, and if the second signal has a second level, said storage element will retain a previously stored signal level; and a plurality of comparator units having outputs, each one of said plurality of comparator units receiving the signal level stored by said storage elements of two adjacent ones of said plurality of basic elements, each one of said plurality of comparator units supplying a different event signal at said output thereof when two identical signal levels are received from said storage elements of two adjacent ones of said plurality of basic elements than when two different signal levels are received.