Patent ID: 7725687
Filing Date: 2010-05-25
Classification: G06F

Abstract:
1. A data processing apparatus operating in response to a sequence of instructions comprising: a data register file including a plurality of data registers storing data; a functional unit having at least one data input and a data output, said functional unit operable to perform an instruction specified data operation upon data received at said at least one data input generating result data at said data output; a forwarding register having an input connected to said data output of said functional unit receiving said result data, and an output; a bypass detection unit comparing an instruction specified destination register within said register file of just completing instruction with an instruction specified input operand of an instruction just beginning execution, said comparator generating a comparison signal indicating whether register bypass is needed; a multiplexer having a first input connected to said data register file for receiving data read from an instruction specified input operand register of said plurality of data registers, a second input connected to said output of said forwarding register for receiving data read from said forwarding register and an output connected to a first data input of said at least one data input of said functional unit, said multiplexer connected to said bypass detection unit and operable said data register file is connected to said output of said forwarding register and selectively operable to either write said data read from said forwarding register into said instruction specified destination register in response to a kill bit within said instruction having a first digital state or not write said data read from said forwarding register into said instruction specified destination register in response to a kill bit within said instruction having a second digital state opposite to said first digital state.