Patent ID: 7763925
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first inter-layer dielectric film formed on a semiconductor substrate; a first electrode pattern formed on the first inter-layer dielectric film; a first capacitor region where the first inter-layer dielectric film is etched in self-alignment to the first electrode pattern; a first metal-insulator-metal (MIM) capacitor conformably formed on a sidewall of the first electrode pattern and the surface of the first capacitor region to form a first hollow region; a second electrode pattern filling the first hollow region to have sidewalls opposite to the sidewalls of the first electrode pattern; a first interconnection layer formed on the same level with the first electrode pattern; a second inter-layer dielectric film covering the first electrode pattern, the second electrode pattern, and the first interconnection layer; a second interconnection layer formed on the second inter-layer dielectric film; a third electrode pattern formed on the same level with the second interconnection layer; a second capacitor region where the second inter-layer dielectric film is etched in self-alignment to the third electrode pattern; a second MIM capacitor conformably formed on a sidewall of the third electrode pattern and the surface of the second capacitor region to define a second hollow region; and a fourth electrode pattern filling the second hollow region to have a sidewall opposite to a sidewall of the third electrode pattern.