Patent ID: 6658561
Filing Date: 2003-12-02
Classification: G06F

Abstract:
A hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction, each of said execution steps corresponding to a micro-instruction select among a plurality of micro-instructions; said device comprising:decision blocks being each associated with a specific instruction of said set of programmable instructions, only one decision block being selected by said determined instruction in order to define which are the micro-instructions to be processed for executing said determined instruction; activation blocks respectively associated with said decision blocks for running one or several specific micro-instructions, only the activation block associated with said selected decision block being activated to run said specific micro-instructions; and a micro-instruction selection block connected to each one of said activation blocks for selecting said specific micro-instructions among said plurality of micro-instructions in answer to the contents of said operand field of said determined instruction.