Patent ID: 6370634
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A computing system containing the switch (2) and N processor units (1-1 . . . 1-N) the second informational output (11) and the third informational input (8); the first control outputs (19-1) and address outputs (20) of the i-th processor unit (1-i) (i=1 . . . N) are connected correspondingly with the i-th input (54-i) of the first group of control inputs and with the i-th input (55-i) of the group of the switch address inputs; the first (21-1) and the second (21-2) informational outputs of the i-th processor unit (1-i) are connected with the corresponding i-th input (57-i) of the group of the switch informational inputs; the first informational (13), address (17-1), control (18-1) and the second informational (14), address (17-2), control (18-2) inputs of the i-th processor unit (1-i) are connected with the first (6) and second (7) informational inputs of the system; the first control input (9) of the system is connected with the control input (53) of the switch (2) and with the third control input (18-3) of the i-th processor unit (1-i); the control output (58) of the switch (2) is connected with the fourth control input (18-4) of the i-th processor unit (1-i); the third informational output (21-3) of the i-th processor unit (1-i) is connected with the first informational output (10) of the system; the computer system is characterized by the fact that there are introduced the auxiliary switch (3), N modules (4-1 . . . 4-N) of associative memory and the buffering block (5); the first control (30-1-i), first informational (30-2-i), second control (30-3-i) and second informational (30-4-i) outputs of the i-th group of exchange outputs of the auxiliary switch (3) are connected correspondingly with the fifth control (18-5), third informational (15), sixth control (18-6) and fourth informational (16) inputs of the i-th processor unit(1-i); the first group of control outputs (28-1 . . . 28-N) of the auxiliary switch (3) is connected with the first group of control inputs (32-1 . . . 32-N) of the buffering block (5); the second group of control outputs (29-1 . . . 29-N) of the auxiliary switch (3) is connected with the second group of control inputs (33-1 . . . 33-N) of the buffering block (5); the control input (22) of the auxiliary switch (3) and the control input (31) of the buffering block (5) and the first control input 46 of each module (4-1 . . . 4-N) of associative memory are connected with the control input (9) of the system; the i-th inputs of the first (23-1 . . . 23-N) and second (24-1 . . . 24-N) groups of control inputs of the auxiliary switch (3) are connected correspondingly with the second (19-2) and third (19-3) control outputs of the i-th processor unit (1-i); the seventh (18-7) and eighth (18-8) control inputs of the i-th processor unit are connected correspondingly with the i-th outputs of the first (39-1 . . . 39-N) and second (40-1 . . . 40-N) groups control outputs of the buffering block (5); the third group of control outputs (41-1 . . . 41-N) and the first group of the informational outputs (42-1 . . . 42-N) of the buffering block are connected correspondingly with the third group of control inputs (25-1 . . . 25-N) and the first group of informational inputs (27-1-1 . . . 27-1-N) of the auxiliary switch (3); the second group of informational outputs (43-1 . . . 43-N) of the buffering block is connected with the second informational output (11) of the system; the fourth group of control inputs (26-1 . . . 26-N) of the auxiliary switch (3) is connected with the fourth group of control outputs (44-1 . . . 44-N) of the buffering block (5); the i-th input of the first group of the informational inputs (34-1 . . . 34-N) of the buffering block is connected with the fourth (21-4) and fifth (21-5) informational outputs of the i-th processor unit (1-i); the fourth control output (19-4) of i-th processor unit is connected with the i-th input of the third group of control inputs (35-1 . . . 35-N) of the buffering block (5); the third group of informational outputs (45-1 . . . 45-N) of the buffering block is connected with the second group of informational inputs (27-2-1 . . . 27-2-N) of the auxiliary switch(3); the first control output (50) of the i-th module (4-i) of associative memory is connected with the i-th input of the second group of control inputs (56-1 . . . 56-N) of the switch (2); the i-th output of the group of informational outputs (59-1 . . . 59-N) of the switch is connected with the informational input (48) of the i-th module (4-i) of the associative memory; the informational (51) and the second control (52) outputs of the i-th module of the associative memory are connected with the i-th inputs of the second group of informational inputs (36-1 . . . 36-N) and the fourth group of control inputs (37-1 . . . 37-N) of the buffering block (5); the third group of informational inputs (38-1 . . . 38-N) of the buffering block is connected with the third informational input (8) of the system; and, the i-th output of the group of control outputs (60-1 . . . 60-N) of the switch (2) is connected with the second control input (49) of the i-th module (4-i) of the associative memory.