Patent ID: 8788908
Filing Date: 2014-07-22
Classification: G06F,G11C

Abstract:
1. A data storage device comprising: a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region; and a memory controller including a buffer memory and configured to control the multi-bit memory device, wherein the memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, wherein the memory controller is further configured to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region, and wherein the memory controller is further configured to generate parity data based upon the data stored to the first memory region, and to store the parity data in the first memory region, the parity data being copied from the first memory region to the second memory region via the main program operation.