Patent ID: 6037211
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a contact in a semiconductor integrated circuit with a self-aligned landing plug, said method comprising:forming gate structures with first sidewall spacers on a substrate and source/drain regions in said substrate, wherein said source/drain regions are adjacent to said gate structure;forming a first dielectric layer on said substrate to cover said gate structures and said source/drain regions;forming conductive hard masks on said first dielectric layer, wherein each said conductive hard mask is aligned to each said gate structure;etching said first dielectric layer by using said conductive hard masks as etching masks to remove a portion of said first dielectric layer to form trenches on said first dielectric layer, wherein portions of said trenches are aligned to said source/drain regions;forming conductive spacers on sidewalls of said trenches and on sidewalls of said conductive hard masks;selectively etching said first dielectric layer by using said conductive hard masks and said conductive spacers as etching masks to expose said first sidewall spacers and the source/drain regions for forming first contact holes on said substrate, wherein an etching rate of said first dielectric layer is higher than that of said sidewall spacers and said conductive hard masks;forming conductive landing plugs in said first contact holes;removing said conductive hard masks, a portion of said conductive spacers and a portion of conductive landing plugs above the etched first dielectric layer, wherein the etched conductive spacers serve as a portion of said conductive landing plugs;forming a second dielectric layer on said conductive landing plugs and the etched first dielectric layer;etching said second dielectric layer to form a second contact hole for exposing a portion of an upper surface of a selected conductive landing plug of said conductive landing plugs;forming a bit line structure on said second dielectric layer to electrically connect said selected conductive landing plug via said second contact hole;forming a third dielectric layer to cover said second dielectric layer and said bit line structure;etching said third dielectric layer to form third contact holes in said third dielectric layer for exposing a portion of said conductive landing plugs other than said selected conductive landing plug; andforming capacitor nodes on said third dielectric layer connecting to said portion of said conductive landing plugs through said third contact holes.