Patent ID: 6236697
Filing Date: 2001-05-22
Classification: H03L,H04L

Abstract:
A clock recovery circuit that recovers a clock from an input data signal that is received at a first frequency or at a second frequency, in response to a mode signal that indicates whether the first or second frequency is received, the clock recovery circuit comprising:a first phase locked loop that generates a control signal in response to a reference clock;a pulse generating and delaying circuit that is responsive to the input data signal and to the mode signal, to generate from the input data signal pulses of predetermined width that is no more than half the period of the input data and that are delayed by a predetermined delay, at least one of the predetermined width that is no more than half the period of the input data and the predetermined delay being a function of the mode signal; anda second phase locked loop that is responsive to the control signal and to the pulse generating circuit, to generate a clock signal from the input data signal.