Patent ID: 8614129
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A method of fabricating a power semiconductor device, comprising: providing a conductive substrate; growing a III-nitride transition layer over a major surface of said substrate by growing at least a first III-nitride layer using a first growth method selected from the group consisting of MBE, HVPE, and MOCVD, and at least a second III-nitride layer over said at least first III-nitride layer using a second growth method selected from said group, said second growth method being distinct and different from said first growth method, and at least a third III-nitride layer over said second III-nitride layer; growing a plurality of said first, second, and third III-nitride layers in an arrangement where a sequence of said first, second, and third III-nitride layers does not repeat; and forming an active semiconductor region on said transition layer, said active semiconductor region including a thick III-nitride semiconductor layer, wherein said first and second III-nitride layers each act to transition lattice mismatch and differences in the thermal expansion characteristics between said conductive substrate and said thick III-nitride semiconductor layer.