Patent ID: 7694245
Filing Date: 2010-04-06
Classification: G06F,H01L

Abstract:
1. A method for designing a semiconductor package, the semiconductor package comprising a semiconductor chip and an adjustment target, the method comprising carrying out the following steps in a computer: calculating a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain; calculating a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level: in consideration of power integrity for the semiconductor chip, selecting inferior one of the first and the second target variables as a main target variable; and comparing the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.