Patent ID: 9143276
Filing Date: 2015-09-22
Classification: H03M,H04L

Abstract:
1. A nested CRC code generation method for data transmission error control, comprising: (1) segmenting data to be computed by a data segmenting module, further comprising: (1.1) initializing the data in the data segmenting module to 0, and determining the maximum number of data segments to be N according to the number of calculating channels N, where N is a positive integer; (1.2) generating N+1 pointers (P (1.3) assigning fixed values to the pointers (P (1.4) initializing the values of the pointers (p (1.5) filling the data to be computed into the data segmenting module and changing the values of the pointers (p (1.6) segmenting the data to be computed into m data segments by the data segmenting module and sending the value of m to a channel selector and a reverse channel selector; (1.7) transmitting W bits of each of the data segments to each of the m computing channels respectively in each clock cycle via the values of the pointers (p (1.8) checking if the values of the pointers (p (2) allocating an appropriate CRC code computing channel to each of the data segments to be computed, further comprising: (2.1) generating a channel selecting table for the channel selector for generating a Qth nested CRC code for the data to be computed of different data types, so as to allocate a corresponding computing channel to each of the data input channels in each of the nested computing processes of the data to be computed of different data types, where Q is a positive integer; (2.2) turning on switches connecting m outputs of the data segmenting module ( (2.3) connecting each of the selected m data inputs of the channel selector to a corresponding computing channel according to the channel selecting table; (3) computing a CRC sub-code for each of the data segments to be computed by the corresponding computing channel, further comprising: (3.1) allocating each of generating polynomials (g (3.2) realizing computing W bits in parallel in each of the computing channels by logic circuits or looking up remainder tables according to the generating polynomials; (3.3) setting an initial value for each of the computing channels according to the generating polynomials, where each computing channel is usually initialized to all 0s or 1s; and (3.4) generating m CRC sub-codes by computing a CRC sub-code for the input data segment of each of the computing channels; (4) sorting the computed CRC sub-codes of the computing channels, further comprising: (4.1) using a same channel selecting table as the channel selector for the reverse channel selector; (4.2) turning on the switches for connecting m CRC sub-code registers ( (4.3) connecting each of m data outputs of the reverse channel selector to an output of the corresponding computing channel according to the channel selecting table; and (4.4) storing each of the CRC sub-codes computed by the computing channels into a corresponding CRC sub-code register by the corresponding computing channel according to the selecting result of the reverse channel selector to generate a new data string (CRC (5) checking if another multi-channel computing process is required, and returning to step (1) using the computed CRC sub-codes in step (4) as the new data to be computed if yes, otherwise proceeding to step (6), further comprising: (5.1) decreasing a nesting frequency of a CRC code Q by 1; and (5.2) checking if Q equals 0, and proceeding to step (6) if yes, otherwise returning to step (1) using the sorted CRC sub-codes in step (4) as the new data to be computed; and (6) computing a final Qth nested CRC code by a (N+1)th computing channel, further comprising: (6.1) allocating the generating polynomial g (6.2) realizing computing W bits in parallel in the (N+1)th computing channel by logical circuits or looking up a remainder table according to the generating polynomial; (6.3) setting an initial value for the (N+1)th computing channel, where the initial value of the (N+1)th computing channel is usually set to 0 or 1; and (6.4) generating a final Qth nested CRC code by a last CRC code computing process with sorted Qth computed CRC sub-codes by the (N+1)th computing channels.