Patent ID: 7168070
Filing Date: 2007-01-23
Classification: G06F

Abstract:
1. A method for cache management in a shared memory multiprocessor environment to inhibit the occurrence of store misses during transfer of a store stream from a first cache to a second cache, the store stream including a plurality of cache lines having updated store elements, the method comprising the steps of: identifying a store stream for potential miss conditioning in a loop of an application code; performing a cost analysis for calculating a threshold value for further consideration of the identified store stream for miss conditioning; selecting the identified store stream for miss conditioning based on an accepted value for the threshold value; and conditioning the selected store stream for miss inhibition by inserting a reset instruction in a corresponding loop of the selected store stream, the reset instruction for clearing at least one cache line in the second cache in advance of a store operation of the selected store stream; wherein the reset instruction causes the environment to override an imposed store condition of a prefetch operation such that a previous version of the updated store elements is resident in the second cache in order to complete the store operation.