Patent ID: 7179750
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. A method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, the method comprising: forming a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a different dielectric material from that of the first dielectric layer; selectively removing a portion of the second dielectric layer so as to selectively expose a portion of the first dielectric layer under the second dielectric layer; selectively removing a portion of the exposed first dielectric layer so as to selectively expose a portion of the semiconductor substrate under the exposed first dielectric layer; and forming a third dielectric layer having a thickness that is thinner than that of the first dielectric layer on the exposed semiconductor substrate, to form a gate dielectric layer including a thick portion formed of the first dielectric layer and remaining second dielectric layer, a medium-thickness portion formed of the exposed first dielectric layer, and a thin portion formed of the third dielectric layer.