Patent ID: 6707708
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A memory comprising:a word line; a first bit line; a second bit line; and a memory cell comprising cross-coupled inverters comprising first and second nodes to store an information state represented by complementary voltages at the first and second nodes; a first nMOSFET comprising a gate connected to the word line and to provide a low impedance path between the first bit line and the first node only if ON; a second nMOSFET comprising a gate connected to the word line and to provide a low impedance path between the second bit line and the second node only if ON; a third nMOSFET comprising a gate connected to ground and to conduct leakage current between the second node and the first bit line; and a fourth nMOSFET comprising a gate connected to ground and to conduct leakage current between the first node and the second bit line.