Patent ID: 8161263
Filing Date: 2012-04-17
Classification: G06F

Abstract:
1. A processor, comprising: a first address translation engine configured to determine a first memory address of a pointer associated with a data prefetch instruction, wherein the first memory address corresponds to an address to which the pointer points; a prefetch engine coupled to the first address translation engine, wherein the prefetch engine is configured to fetch a first data block that includes content of a memory at the first memory address; and a second address translation engine coupled to the prefetch engine, wherein the second address translation engine is configured to determine a second memory address based solely on the content of the memory at the first memory address, and wherein the prefetch engine is also configured to fetch a second data block that includes desired data at the second memory address, where the data prefetch instruction includes an indirect address field that identifies whether an effective address associated with the data prefetch instruction is a pointer for the desired data that is to be prefetched or whether the effective address corresponds to an address for the desired data.