Patent ID: 6539529
Filing Date: 2003-03-25
Classification: G06F

Abstract:
An integrated circuit designing method comprising the steps of:designating where a plurality of circuit blocks are to be placed on a circuit area of a substrate, input layout data being used to designate said placement of said plurality of circuit blocks, said circuit area being a portion of said substrate where a circuit is to be placed; allocating a plurality of delay adjusting circuits to a plurality of regions of said circuit area, said plurality of regions being all portions of said circuit area that are unoccupied by said plurality of circuit blocks, said plurality of regions being one of a path region and a non-path region, said path region being a portion of said circuit area where a wire pattern of a plurality of wiring patterns will be designated for passage, said path region accommodating a first delay adjusting circuit of said plurality of delay adjusting circuits, said non-path region being another portion of said circuit area where none of said plurality of wiring patterns will be designated for passage, said non-path region accommodating another delay adjusting circuit of said plurality of delay adjusting circuits, said another delay adjusting circuit being separate and distinct from said first delay adjusting circuit; designating said wire pattern for passage, said wire pattern connecting one of said plurality of circuit blocks to another of said plurality of circuit blocks; calculating a performance requirement for said wiring pattern; designating said first delay adjusting circuit for placement in said path region when said wiring pattern fails to meet said performance requirement; placing said first delay adjusting circuit in said path region, said performance requirement being met when said first delay adjusting circuit placed at said path region is connected to said wiring pattern; modifying an input net list to generate a modified net list, said input net list defining said wiring pattern, said wiring pattern providing the connection between one of said plurality of circuit blocks and another of said plurality of circuit blocks, said modified net list defining the connection between said first delay adjusting circuit and said wiring pattern; modifying said input layout data to generate modified layout data, all of said plurality of delay adjusting circuits that are unconnected to any of said plurality of wiring patterns being eliminated from said modified layout data; generating said plurality of wiring patterns from said modified layout data and from said modified net list.