Patent ID: 8787368
Filing Date: 2014-07-22
Classification: G06F,H04L

Abstract:
1. A processor, comprising: a crossbar switch configured to connect source ports to destination ports; a command scheduler configured to schedule at least two command packets from the source ports to the destination ports during a clock cycle; the command scheduler having a first picker configured to select a command packet during the clock cycle; and the command scheduler having a second picker different from the first picker, the second picker configured to select another command packet during the clock cycle, wherein the second picker is dependent on the first picker for source port selection from the source ports, wherein the first picker selects from a first group of source ports and the second picker selects from a second group of source ports during the clock cycle, wherein the first picker selects from the second group of source ports and the second picker selects from the first group of source ports in the next clock cycle, and wherein the second picker command packet selection is cancelled upon a destination port collision with the first picker command packet selection.