Patent ID: 8181148
Filing Date: 2012-05-15
Classification: G06F

Abstract:
1. A method for chip design, comprising: generating a functional representation of a cone in element comprising at least one input; generating a functional representation of a standard application specific integrated circuit (ASIC) library directly coupled to an output of the cone in element; generating a functional representation of a special purpose flexible logic block (FLB) library directly coupled to the output of the cone in element, the special purpose FLB library comprising at least one FLB initially wired to perform a functioning logic of a normal ASIC gate, and to comprise additional at least one of inputs and outputs for alteration of the functioning logic; generating a functional representation of a selector device directly coupled to an output of the standard ASIC library and an output of the special purpose FLB library, and for selecting at least one of the output of the standard ASIC library and the output of the special purpose FLB library; generating a functional representation of a cone out element directly coupled to an output of the selector device, and comprising at least one output; receiving a first netlist; receiving a subsequent netlist composed of engineering logic changes; identifying the engineering logic changes made since the first netlist; and replacing at least one of the engineering logic changes with the at least one FLB by selecting the output of the special purpose FLB library, wherein the method is embodied on a computer-readable storage memory device executed by a computer and used for fabricating an integrated circuit chip.