Patent ID: 7863957
Filing Date: 2011-01-04
Classification: H03K

Abstract:
1. A duty cycle correction circuit, comprising: a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal; a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal; a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals, wherein the control signals are digital signals having multiple bits, and the clock delay unit is configured to delay the rising clock signal and the falling clock signal with variation according to logical values of the control signals in order that the delayed rising clock signal and the delayed falling clock signal have a phase difference by as much as one-half of a period.