Patent ID: 6021061
Filing Date: 2000-02-01
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array comprising a plurality of memory cells arranged in a matrix format of rows and columns;a plurality of row lines arranged to correspond to said rows, respectively, for selecting said memory cells along said rows;a plurality of column lines arranged to correspond to said columns, respectively, for selecting said memory cells along said columns;a row-selection mechanism connected to said row lines for selecting said row lines, based on address signals;a column-selection mechanism connected to said column lines for selecting said column lines, based on address signals; anda circuit section for writing and reading data into and from memory cells in said memory cell array, selected in sequence by means of cooperation of said row- and column-selection mechanisms,wherein at least one of said row- and column-selection mechanisms comprises a core circuit array and a control circuit array arranged adjacent to said core circuit array,said core circuit array comprises an m-number of core circuit units which are substantially equivalent to each other, and each of which consists of an n-number of core circuits forming decoders, respectively,said control circuit array comprises an m-number of control circuit units which are substantially equivalent to each other, and are connected to said core circuit units by interconnection wiring lines, respectively, andsaid core circuit units and said control circuit units are arranged in a first direction with first and second pitches, respectively, which differ from each other.