Patent ID: 6567927
Filing Date: 2003-05-20
Classification: G06F

Abstract:
A supercomputer comprising a plurality of logic units, said plurality of logic units being configured to tolerate an amount F of errors in simultaneous manner as to time and being capable of operating under the instructions of the Byzantine algorithm, at least one of said plurality of logic units comprising:(a) a plurality of inputs (+0, +1, +2, +3) for the in-reading of data into registers (SR1 to SR10) of a set of registers; (b) a plurality of outputs (+1, +2, +3) for out-reading of data from the registers (SR1 to SR10); (c) each output (+1, +2, +3) being connectable with an input (+1, +2, +3) of a further logic unit (BSL); and (d) the registers (SR1 to SR10) being connected with the last-mentioned inputs (+1, +2, +3) and with outputs (+1, +2, +3) in such a manner that each register (SR1 to SR10) is capable of in-reading and out-reading, independently of the position of the logic unit (BSL) within the assembly, by means of a position invariant, relative identification.