Patent ID: 6469699
Filing Date: 2002-10-22
Classification: G09G

Abstract:
A sample and hold circuit comprising:a common substrate; a sample and hold pulse generation circuit formed on said common substrate for generating a plurality of sample and hold pulses for sampling and holding a video signal, wherein a phase of said plurality of sample and hold pulses is shifted successively by a period of a master clock; a PLL circuit for generating said master clock in synchronism with a comparison reference signal provided externally and for generating a horizontal start pulse for use as a reference to determine a horizontal position of a displayed picture based on said video signal by dividing said master clock, wherein said PLL circuit is formed on said common substrate so that unwanted radiation is reduced regardless of a high frequency of said master clock; and a plurality of sample and hold units formed on said common substrate and having as inputs said video signal and said plurality of sample and hold pulses.