Patent ID: 7930464
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A multiprocessor system comprising: at least two processors, each processor having at least one processing core; at least two memory controllers, each communicatively coupled to one of the at least two processors, to facilitate transactions between a memory and the at least two processors; at least one hub for input/output devices; at least one bridge to send and receive transactions between the at least one hub for input/output devices and the at least two processors; and at least two crossbars, each communicatively coupled to one of the at least two processors, to route the transactions between the at least one hub for input/output devices and the at least two processors; wherein the at least two crossbars are each communicatively coupled to one of the at least two memory controllers to route transactions between the at least one hub for input/output devices and the memory.