Patent ID: 6262478
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A multilevel electronic interconnect structure comprising:a) at least two layers of aluminum conductors supported on a base and disposed on and separated by a non-aluminum oxide dielectric material;b) a layer of an adhesion metal on said dielectric material, beneath each said conductor;c) a layer of a barrier metal selected from the group consisting of tantalum, niobium, hafnium, titanium, and zirconium disposed between each said adhesion metal layer and each said conductor;d) filled aluminum vias at least about 3 microns thick interconnecting adjacent layers of conductors, said filled aluminum vias being surrounded by said non-aluminum oxide dielectric material;e) a layer of said barrier metal beneath each said via, disposed between said via and an interconnected conductor; andf) an external surface remote from the base, said external surface being constructed and arranged for receipt thereon of at least one integrated circuit chip,the electronic interconnect structure serving as means for interconnecting the at least one integrated circuit chip.