Patent ID: 6838724
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A transistor array, comprising: vertical FET transistors each formed of vertical and laterally parallel sections of active webs of semiconductor formed into a depth of a substrate; said vertical FET transistors having a channel region surrounded by gate strips, forming a gate electrode and running along said sections of active webs, and forming word lines for a memory cell array of semiconductor memory cells assigned to the transistor array; word line contacts electrically connecting at least some of said word lines to metal tracks of a metal plane superimposed on the transistor array; an insulation in a deep trench, passing into the depth of said active web, insulating said word line contacts from other elements, the deep trenches being formed with a substantially identical structure as deep trenches otherwise forming storage capacitors in the memory cell array, except for a buried strap connecting said active web in the memory cell array to polysilicon in the depth of the substrate and that is omitted in the deep trenches of the word line contacts.