Patent ID: 6310822
Filing Date: 2001-10-30
Classification: G06F,G11C,H03K,H04L

Abstract:
A clock synchronizer circuit to provide an internal clock signal for an integrated circuit that is synchronized to an external system clock signal, such that said internal clock signal is aligned with and has minimal skew from said external system clock signal, whereby said clock synchronizer circuit is comprising:a plurality of serially connected delaying means to receive said external system clock signal and delay said external system clock signal by an incremental period of delay;a plurality of frequency divider means, whereby a first frequency divider means receives said external system clock signal and divides a frequency of said external system clock signal by a dividing factor and each remaining frequency divider means is connected to an output of one of the serially connected delaying means to divide a delayed external system clock signal by said dividing factor providing a plurality of divided external system clock signals;a plurality of clock synchronization delay means, whereby each clock synchronization delay means is connected to one of the plurality of frequency divider means to synchronized each divided external system clock signal to the external system clock signal; anda logical combining means to combine the synchronize, divided external system clock signals to form said internal clock signal.