Patent ID: 9042173
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A memory in an integrated circuit, comprising: a plurality of memory cells arranged in rows and columns in a plurality of sector portions, the memory cells in each column within a sector portion coupled to a bit line associated with that column; row decoder circuitry for selecting a row of memory cells responsive to a row portion of an address; a plurality of column select circuits grouped in pairs, each column select circuit associated with one of a plurality of groups of adjacent columns and for selecting one of the columns in its group responsive to a column address portion of the address, each pair of column select circuits associated with groups of columns disposed near one another; a plurality of sense amplifiers, each sense amplifier having first and second inputs, each sense amplifier associated with a pair of column select circuits; a plurality of global bit lines, each global bit line associated with a single column of memory cells; and local/global bit line switch circuitry for coupling local bit lines of columns of a sector portion selected by a portion of the address to corresponding global bit lines; wherein the memory cells in each column within each sector portion are coupled to a local bit line associated with that column and that sector portion; and wherein the pairs of column select circuits operate to select a column by one of the plurality of column select circuits in the pair coupling the global bit line associated with the selected one of the columns in its group to an input of its associated sense amplifier.