Patent ID: 8098255
Filing Date: 2012-01-17
Classification: G06F,G06T

Abstract:
1. In a graphics system including a main processor; a graphics processing system including a command processor, a texture unit and a pixel engine for generating graphics images on a display in cooperation with said main processor; an audio processor; a video interface; an input/output interface; and a main memory, a memory controller comprising: a plurality of main memory read queues each operatively coupled to a respective read requester, said plurality of main memory read queues including a first main memory read queue which is operatively coupled to receive read requests from said command processor, a second main memory read queue which is operatively coupled to receive read requests from said texture unit, a third main memory read queue which is operatively coupled to receive read requests from said audio processor, a fourth main memory read queue which is operatively coupled to receive read requests from said input/output interface, and a fifth main memory read queue which is operatively coupled to receive read requests from said video interface; a plurality of main memory write queues each operatively coupled to a respective write requester, said plurality of main memory write queues including a first main memory write queue which is operatively coupled to receive write requests from said pixel engine, a second main memory write queue which is operatively coupled to receive write requests from said audio processor and a third main memory write queue which is operatively coupled to receive write requests from said input/output interface; a global write queue coupled to said plurality of main memory write queues for storing write requests for main memory access transferred thereto from said plurality of main memory write queues; and a control circuit for controlling the transfer of write requests to said global write queue, wherein said control circuit is operable to control the transfer of write requests from said plurality of main memory write queues to said global write queue to reduce the frequency of switching from main memory write operations to main memory read operations, wherein said control circuit further comprises an arbitration circuit for arbitrating access to said main memory from among said main processor, said plurality of main memory read queues and said global write queue.