Patent ID: 7016931
Filing Date: 2006-03-21
Classification: G06F

Abstract:
1. A comparator for comparing two N-bit binary numbers, comprising: a block of N circuits for detecting equality/difference between homologous bits of the two numbers, the circuits being arranged in decreasing order of significance, that is of weight, of the bits compared, and each circuit outputting a first, logic-level 1 and electrically-positive signal on a correspondingly arranged continuity/disconnection line, if the bits compared are identical, and a logic-level 1 and electrically-positive signal on a correspondingly arranged decision line if the bits compared are different, a matrix-like structure of n-channel transistors arranged to form 4 columns of N rows of transistors, arranged in an order corresponding to that of the detector circuits and of the corresponding continuity and decision lines, the transistors of a first and of a second of the columns being connected in series with one another in order, the respective first transistors in order, of the of the first and second columns having their respective drains connected to a first node and to a second node, respectively, at least one of the nodes constituting an output node, the respective last transistors in order, of the first and second columns having their respective sources connected to respective input terminals so as to receive a positive or zero voltage signal according to the comparison function to be performed, the transistors arranged in order in the third column having their drains connected, respectively and in order, to the first node and to the intermediate nodes between the transistors of the first column, in sequence, the transistors arranged in order in the fourth column having their drains connected, respectively and in order, to the second node and to the intermediate nodes between the transistors of the second column, in sequence, the gates of the transistors of the first and second columns being connected in the order of the transistors, to a correspondingly arranged continuity line, the gates of the transistors of the third and fourth columns being connected, in the order of the transistors, to a correspondingly arranged decision line, the sources of the transistors arranged in order in the third and fourth columns being biased in order, in dependence on the comparison function to be performed, by one and by the other, respectively, of a pair of signals belonging to a set of pairs of signals selected from at least the following sets: the set of pairs of signals representative of the bits, in decreasing order of significance, of one of the binary numbers compared, and of their negated forms, the set constituted by a positive voltage signal applied to the sources of the transistors of one of the two columns and by a zero voltage signal applied to the sources of the transistors of the other column, and a signal supply and regeneration block connected to a source of a positive voltage Vcc which, in response to a zero-level voltage signal imparted by the matrix to the first node, imparts the positive voltage Vcc to the second node and, in response to a zero-level voltage signal imparted by the matrix to the second node, imparts the positive voltage Vcc to the first node.