Patent ID: 8423843
Filing Date: 2013-04-16
Classification: G01R,G06F

Abstract:
1. A method for optimizing power consumption of scan groups of a system-on-chip (SOC) circuit during testing of the SOC circuit, the method comprising: generating one or more scan groups using at least a register-transfer level (RTL) design description of the SOC circuit and a circuit library corresponding the SOC circuit; establishing an activity factor (AF) for each of said one or more scan groups; instantiating a clock frequency value for each clock domain in each of said one or more scan groups; establishing a peripheral interaction factor (PIF) for each of said one or more scan groups; performing a power simulation for each of said one or more scan groups; generating a report for each of said one or more scan groups containing at least power consumption data of the one or more scan groups obtained in response to the power simulation for the one or more scan groups; and optimizing the testing of the SOC by grouping said one or more scan groups into a plurality of test groups based on the power consumption data of the one or more scan groups as provided in the report and at least one of a tester's power capability, desired test time, and test cost on the tester.