Patent ID: 6281090
Filing Date: 2001-08-28
Classification: H01C,H01L,H05K

Abstract:
A method of forming a resistor between two metallic circuit traces, which circuit traces have a volume resistivity less than about 5.times.10.sup.-6 ohm-cm, and which circuit traces are upon and separated by an insulative substrate, which insulative substrate has a volume resistivity greater than about 1.times.10.sup.9 ohm-cm, which method comprises plating a resistive material, which resistive material has a volume resistivity of from about 500 to 1.times.10.sup.-4 ohm-cm, onto an area of the insulative substrate between the circuit traces such that the resistive material connects the circuit traces and wherein the area of the insulative substrate between the circuit traces has been treated with a process selected from the group consisting of chemical etching, plasma etching, laser normalization, vapor blasting, sanding, shot blasting and sand blasting prior to plating the resistive material thereon.