Patent ID: 6436853
Filing Date: 2002-08-20
Classification: B81C,G01P,H01L,H03H

Abstract:
A microstructure for simultaneously micropackaging a plurality of microelectronic devices, the microstructure comprising:a first substrate wafer; a first array of microdevices mounted on the first substrate wafer; a second substrate wafer; a corresponding second array of micropackages defining a predetermined volume and an open aperture along at least one side, the micropackages mounted on the second substrate wafer, the micropackages being aligned such that the second array matches the first array; a corresponding array of microheaters, each said microheater mounted on a respective one of the micropackages of the second array along a predetermined peripheral boundary line area; electrically conductive interconnection lines electrically interconnected between the microheaters of the second array on the second substrate, wherein the second substrate is connectible with the first substrate such that each microdevice in the first array is covered by one of the micropackages in the second array, and such that the corresponding array of microheaters is interposed between the first array of devices and the second array of micropackages; and a localized high-temperature bond interposed between the first substrate and the second substrate to enclose the predetermined volume therebetween.