Patent ID: 6117711
Filing Date: 2000-09-12
Classification: B82Y,H01L,Y10S

Abstract:
A method for manufacturing single-electron-tunneling CMOS transistors on a semiconductor substrate, said method comprising the steps of:forming a plurality of isolations on said semiconductor substrate;forming a pad oxide on said semiconductor substrate;performing an ion implantation to dope dopants into said semiconductor substrate using said plurality of isolations as a mask, thereby forming an oxygen amorphized region in said semiconductor substrate, said oxygen amorphized region keeping a distance from a surface of said oxygen amorphized region;performing a thermal anneal to convert said oxygen amorphized region into a buried oxide, thereby forming localized silicon islands between said pad oxide and said buried oxide;performing a thermal oxidation to increase a thickness of said pad oxide and narrow a thickness of said localized silicon islands, thereby forming silicon wires between said pad oxide and said buried oxide;removing said pad oxide; andforming said single-electron-tunneling CMOS transistors on said silicon wires.