Patent ID: 8045664
Filing Date: 2011-10-25
Classification: H03L,H04L

Abstract:
1. A clock/data recovery device for recovering a clock signal and data based on an input digital signal, comprising: a sampler for receiving an input of a clock signal CK and a clock signal CKX, which have a same cycle T(n), and also receiving the input digital signal, setting a signal to which an offset (−Voff) has been applied to the input digital signal as a first signal, setting a signal to which an offset (+Voff) has been applied to the input digital signal as a second signal, and in each n a detector for, in each period T(n), receiving an input of the digital value DA(n), digital value DB(n), digital value DXA(n) and digital value DXB(n) outputted from the sampler, determining a digital value D(n) and a digital value DX(n−1) by setting “D(n)=DA(n)” and “DX(n−1)=DXA(n−1)” in a case where a value D(n−1) is HIGH level and setting “D(n)=DB(n)” and “DX(n−1) =DXB(n−1)” in a case where the digital value D(n−1) is LOW level, and detecting a phase relationship between the clock signal CK and the input digital signal based on the digital value D(n−1), digital value DX(n−1) and digital value D(n);