Patent ID: 7326622
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. A method of manufacturing a metal-oxide semiconductor (MOS) transistor device, comprising: providing a semiconductor substrate having a main surface; forming a gate dielectric layer on the main surface; forming a gate electrode on the gate dielectric layer, wherein the gate electrode has vertical sidewalls and a top surface; forming a liner on the vertical sidewalls of the gate electrode; wherein the liner is made of silicon oxide; forming a silicon nitride spacer on the liner; ion implanting the main surface using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface; removing the silicon nitride spacer; and forming a cap layer that borders the liner, wherein the cap layer has a specific stress status: wherein the MOS transistor device is an NMOS transistor device and wherein the cap layer is tensile-stressed.