Patent ID: 8592923
Filing Date: 2013-11-26
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a first well region of a first conductivity type over a substrate; a second well region of a second conductivity type opposite the first conductivity type over the substrate; a cushion region laterally spacing the first well region apart from the second well region, wherein the cushion region comprises impurities from the first and the second well regions, wherein the cushion region has a width between about 0.3 μm and about 3 μm, and wherein the first and the second well regions and the cushion region extend from a top surface of the substrate into the substrate; an insulation region extending from a top surface of the first well region into the first well region; a gate dielectric directly over the first and the second well regions and a portion of the insulation region, the gate dielectric comprising silicon carbide; a gate electrode on the gate dielectric; and a third well region of the second conductivity type adjacent to the first well region.