Patent ID: 6080644
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method of making an epitaxial layer on a silicon substrate having in a major surface thereof a P+ field layer region in a substantial portion of the major surface, comprising:(a) loading the substrate in a reactor and providing a. carrier gas therein;(b) performing a low temperature bake cycle on the substrate at a temperature of approximately 850.degree. C.;(c) further heating the substrate while providing N+ dopant gas in the carrier gas;(d) performing a high temperature bake cycle on the substrate in the presence of N+ dopant gas;(e) depositing a first intrinsic epitaxial cap layer on the substrate;(f) performing a first high temperature gas purge cycle;(g) depositing a second intrinsic epitaxial cap layer on the first intrinsic epitaxial cap layer;(h) performing a second high temperature gas purge cycle; and(i) depositing an N- epitaxial layer having a thickness substantially greater than the thickness of either of the first and second intrinsic cap layers on the second intrinsic epitaxial cap layer.