Patent ID: 9171846
Filing Date: 2015-10-27
Classification: G11C,H01L,Y10T

Abstract:
1. A memory architecture comprising: a memory component located on a single chip in a mobile computer device, wherein the memory component comprises one of the single chip, a die on the chip, and a module on the chip, and the memory component further comprises a first memory segment located on the single chip which is assigned a first memory grade, the first memory grade being a performance measure based on a re-grading of the first memory segment measured post-manufacturing that reflects manufacturing process variations in the first memory segment, and a second memory segment located on the single chip which is assigned a second memory grade, the second memory grade being a performance measure based on a re-grading of the second memory segment measured post-manufacturing that reflects manufacturing process variations in the second memory segment, wherein the first memory grade is different than the second memory grade; and an external controller that associates each memory segment with a respective memory grade based on the re-grading and selectively changes a mode of operation of the memory component by activating a set of memory segments having the first memory grade to achieve a first mode of operation and by activating a second set of memory segments having the second memory grade to achieve a second mode of operation, wherein the first memory segment and the second memory segment are stacked in a through-silicon via (TSV) configuration.