Patent ID: 8621138
Filing Date: 2013-12-31
Classification: G06F,G11C

Abstract:
1. A method including performing the following steps by a storage controller in a system wherein the storage controller is operatively coupled to a flash memory module: for each flash port of a plurality of flash ports, each flash port corresponding to a flash group of the flash memory module, each flash port comprising an associated processor, setting a repeat count register to a predetermined value if the flash port is in sleep mode such that the processor associated with the flash port wakes up before a transfer operation associated with the flash port is complete; upon wake up of a first processor of a first flash port of the plurality of flash ports, prior to the transfer operation completing, in accordance with the predetermined value set in the repeat count register: repeating the above steps until the first state information or the second state information indicates that the operations required by the corresponding data structure is are completed, at which point a pointer to that data structure is removed from the corresponding queue and the method continues for the other data structure until its state information indicates that the operations required by it are completed, at which point a pointer to that data structure is removed from the corresponding queue.