Patent ID: 9153606
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A method of manufacturing an array substrate, comprising: a first patterning process of forming a first metal layer comprising a gate line and a gate electrode of a thin film transistor (TFT) on a substrate; a second patterning process of forming a first insulating layer to cover the first metal layer and the substrate and sequentially forming a semiconductor layer, an ohmic contact layer, a second metal layer that comprises a data line and a source electrode and a drain electrode of the TFT, and an etch-blocking pattern on the first insulating layer, wherein a lamination of the semiconductor layer and the ohmic contact layer constitutes an active layer of the TFT, and the data line is connected to the source electrode; and a third patterning process of forming a second insulating layer to cover the semiconductor layer, the ohmic contact layer, and the second metal layer, and forming, through a lifting-off process, a pixel electrode connected to the drain electrode of the TFT; wherein the etch-blocking pattern is formed in a peripheral area of the pixel electrode within an overlapping region between the pixel electrode and the first metal layer, and the etch-blocking pattern is interposed between the active layer and the pixel electrode.