Patent ID: 6077776
Filing Date: 2000-06-20
Classification: H01L,Y10S

Abstract:
A method of forming a polysilicon line on a wafer in the fabrication of an integrated circuit comprising:providing a dielectric layer over the surface of a semiconductor substrate;depositing a polysilicon layer overlying said dielectric layer;depositing a hard mask layer overlying said polysilicon layer and patterning said hard mask layer;thereafter cleaning said wafer whereby surfaces of said wafer are hydrophillic and whereby moisture and impurities form volatile defects on said surfaces of said hard mask layer and said polysilicon layer after said cleaning;thereafter heat treating said wafer whereby said volatile defects are removed; andthereafter etching away said polysilicon layer where it is not covered by said hard mask to complete formation of said polysilicon line on said wafer in the fabrication of said integrated circuit.