Patent ID: 6862693
Filing Date: 2005-03-01
Classification: G06F

Abstract:
1. A method for providing fault-tolerance by using redundant processors, comprising: receiving a plurality of store operations from a plurality of redundant processors running the same code in lockstep; comparing the plurality of store operations to determine if the plurality of store operations are identical, thereby indicating that the plurality of redundant processors are operating correctly; if the plurality of store operations are not identical, indicating an error condition; if the plurality of store operations are identical, receiving a plurality of invalidation messages from the plurality of redundant processors; wherein the plurality of invalidation messages indicate that a specific cache line should be invalidated in other caches in the computer system; combining the plurality of invalidation messages into a combined invalidation message; and communicating the combined invalidation message to the other processors in the computer system, but not to the plurality of redundant processors.