Patent ID: 8458390
Filing Date: 2013-06-04
Classification: G06F,H04L

Abstract:
1. A system for communicating a packet, the system comprising: means for converting a packet into cells within an input/output interface, each cell specifying a destination physical address corresponding to a first physical partition of a physically-partitionable symmetric multiprocessor; means for transferring each cell through a switch in accordance with the destination address; means for forming the cells into a reconstructed packet within the first physical partition; wherein the physically-partitionable symmetric multiprocessor is programmable as a selected one of a first configuration comprising one physical partition and a second configuration comprising a plurality of physical partitions; wherein the packet has a destination logical address and the destination physical address of each cell corresponding to the packet is based at least in part on the destination logical address of the packet; wherein the forming of the cells into a reconstructed packet comprises data transfers according to a direct memory access protocol; and wherein the input/output interface comprises at least one of a network interface and a storage interface.