Patent ID: 6605509
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A method for forming a floating gate structure of a flash memory, said method comprising:providing a substrate; forming a first conductive layer and a second conductive layer sequentially on said substrate; forming a first dielectric layer on said second conductive layer; forming a first hard mask layer and a second hard mask layer sequentially on said first dielectric layer; transferring a floating gate pattern into said second hard mask layer to expose said first hard mask layer; etching said first hard mask layer to form a pattern and expose said first dielectric layer; conformally forming a second dielectric layer over said second hard mask layer and said pattern; etching back said second dielectric layer to form a spacer and expose said first dielectric layer; etching said first dielectric layer to expose said second conductive layer; and removing said spacer, said second hard mask layer, said first hard mask layer and said first dielectric layer.