Patent ID: 6044123
Filing Date: 2000-03-28
Classification: H03L,H04L

Abstract:
A phase-locked loop comprising:a first multiplexer for selecting one of a first clock signal or a second clock signal as a selected signal;a detector coupled to the first multiplexer for generating a detection signal based on the selected signal;a controlled oscillator coupled to the detector for generating an output signal based on the detection signal;a signal modification device coupled to the controlled oscillator for modifying the output signal according to a function;a second multiplexer coupled to the controlled oscillator and to the signal modification device for receiving the output signal from the controlled oscillator and the modified output signal from the signal modification device; anda control device coupled to the signal modification device for controlling the function, coupled to the first multiplexer for controlling the first multiplexer to select the first clock signal as a preferred signal when the first clock signal is available and to select the second clock signal when the first clock signal is unavailable, and coupled to the second multiplexer for controlling the second multiplexer to select the output signal when the first clock signal is available and to select the modified output signal when the first clock signal is unavailable.