Patent ID: 6065070
Filing Date: 2000-05-16
Classification: G06F

Abstract:
A method of optimizing a data transfer from an N-byte wide memory system within a data processing system using a bus master controller and an M-byte wide transmit buffer, wherein the data is organized in data frames, each data frame is comprised of data buffers, and each data buffer having an associated descriptor block including a memory system address pointer field for holding an address pointer, a length field for holding a length value, a status field for holding a status value, and a command field for holding a command value, the method comprising the steps of:initializing first and second latched storage registers capable of holding the least significant bits of the address pointer and the length value, which together indicate the alignment of the start and end of the data buffer relative to N-byte wide boundaries within the memory system, to zero;initializing a third latched storage register capable of holding an intermediate value used to calculate the byte arrangement for transferring an individual data buffer into the transmit buffer;loading the descriptor block values including the address pointer to the next data buffer to be transferred, the length value of the next data buffer to be transferred, the status value of the next data buffer to be transferred, and the command value of the next data buffer to be transferred, into the bus master controller from the memory system;loading and latching the first, second, and third latched storage registers in response to loading the descriptor block values;calculating a steer value based upon the values stored in the latched storage registers;steering N bytes of the data buffer into Accumulator registers;calculating a clocking value based on the transfer of the N bytes of data into the Accumulator registers to determine when the Accumulator registers contain the proper arrangement of the current N bytes of the data buffer;writing the current N bytes of the data buffer into the transmit buffer from the Accumulator registers;transferring any remaining bytes of the data buffer by repeating the steps of steering, calculating a clocking value, and writing until all bytes of the data buffer have been transferred into the transmit buffer;repeating the steps of initializing the third latched storage register, loading descriptor block values, loading and latching the first, second, and third latched storage registers, calculating a steer value, steering, calculating a clocking value, writing, and transferring until all data buffers of the current data frame have been transferred into the transmit buffer;writing one or more place holder bytes into the transmit buffer after the end of the transferred data frame to insure that the next data frame to be written will start on a M-byte wide boundary in the transmit buffer; andwriting a value into the status field of the descriptor block of the last data buffer of the transferred data frame to indicate that the frame has been transferred.