Patent ID: 6649526
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method for implanting and coding a read-only memory with automatic alignment at four corners for being used in a mask memory; the read-only memory comprising a substrate, bit lines on said substrate; a gate oxide layer on said substrate; and a spaced-striped first polysilicon layer on said gate oxide layer; comprising the steps of:forming a spacing layer on said gate oxide layer; depositing a second polysilicon layer overlying said spacing layer and said spaced-striped first polysilicon layer; etching a part of said second polysilicon layer and said spaced-striped first polysilicon layer to expose said gate oxide layer so that the second polysilicon layer becomes a striped second polysilicon layer; forming an isolating layer on said etched portion of the spaced-striped first polysilicon layer and said etched portion of the striped second polysilicon layer; and defining code areas by using the striped second polysilicon layer as a mask for performing the process of implantation and coding.