Patent ID: 6931091
Filing Date: 2005-08-16
Classification: H03K

Abstract:
1. A gray code counter for generating a gray code having N bits comprising: a first toggle flip-flop stage including first and second latches; N−1 cascaded toggle flip-flop stages each including third and fourth latches; wherein each of the latches has a clock input, a complementary clock input, a data D input, a Q output and a complementary Q output; wherein, in the first stage, the clock input of the first latch and the complementary clock input of the second latch are for receiving an external clock signal, the complementary clock input of the first latch and the clock input of the second latch are for receiving a complement of the external clock signal, the D input of the first latch is coupled to the complementary Q output of the second latch, and the Q output of the first latch is coupled to the D input of the second latch; wherein, in each of the N−1 stages, the D input of the third latch is coupled to the complementary Q output of the fourth latch, the Q output of the third latch is coupled to the D input of the fourth latch, the Q output of the fourth latch is coupled to the clock input of the third latch and the complementary clock input of the fourth latch of a successive N−1 wherein, for the first of the cascaded N−1 stages, the clock input of the third latch and the complementary clock input of the fourth latch are connected to the Q output of the second latch, and the complementary clock input of the third latch and the clock input of the fourth latch are connected to the complementary Q output of the second latch; and wherein the Q outputs of the third latches of each of the successive N−1