Patent ID: 6781869
Filing Date: 2004-08-24
Classification: G11C,H01L

Abstract:
A semiconductor memory with a plurality of full CMOS-type of memory cells arranged in an array, each memory cell comprising:a first load transistor and a first driver transistor connected in series between a power supply voltage line and a ground voltage line, and having a gate connected to a same line in common; a second load transistor and a second driver transistor connected in series between the power supply voltage line and the ground voltage line, and having a gate connected to a same line in common; a first cell node which connects an active region of said first load transistor to an active region of said first driver transistor, and connects with each gate of said second load transistor and said second driver transistor; a second cell node which connects an active region of said second load transistor to an active region of said second driver transistor, and connects with each gate of said first load transistor and said first driver transistor; a first access transistor connected between said first cell node and a first bit line, and having a gate connected to a word line; a second access transistor connected between said second cell node and a second bit line in conjugate with said first bit line, and having a gate connected to a the word line; an insulating film and a conductive film directly formed on said first and second cell nodes for constituting a charge capacitor element with said first and second cell nodes, so that said insulating film is held between the first and second cell nodes and the conductive film, covering both said first and second cell nodes in common.