Patent ID: 6324092
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A random access memory cell, comprising:a first transistor having a first control gate, a floating gate, a first substrate, a data read terminal and an earth terminal, wherein the first transistor is switched on when a voltage greater than a first threshold voltage is applied, the first control gate is connected to a control signal line, the data read terminal is connected to a data read line, the earth terminal is connected to a ground, the floating gate is located between a portion of the first substrate and a portion of the first control gate; anda second transistor having a second control gate, a second substrate, a data write terminal and a data transmission terminal, wherein the second transistor is switched on when a voltage greater than a second threshold voltage is applied, the second control gate is connected to the control signal line, the data write terminal is connected to a data write line and the data transmission terminal is connected to the floating gate;wherein the second threshold voltage is greater than the first threshold voltage, the control signal line needs to provide a write control voltage to write data into the memory cell and a read control voltage to read data out of the memory cell, the write control voltage is greater than or equal to the second threshold voltage while the read control voltage is smaller than the second threshold voltage but greater than or equal to the first threshold voltage.