Patent ID: 6346438
Filing Date: 2002-02-12
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device, comprising:a) forming, on one major surface of a substrate, a gate structure selected from the group consisting of a first gate structure comprising a dummy gate wiring layer and a dummy gate electrode, and a second gate structure comprising a gate wiring layer and a gate electrode, each of the gate wiring layer and the gate electrode being provided with an insulating film at least on a bottom surface thereof, and a device isolation insulating film having a first groove, such that said dummy gate electrode or said gate electrode divides said first groove, and such that an upper surface level of said gate structure is not higher than an upper level of said device isolation insulating film; and b) forming source and drain electrodes in the first groove by use of film forming and flattening, wherein said dummy gate wiring layer or said gate wiring layer is formed on the device isolation insulating film, connected to said dummy gate electrode or said gate electrode, and crossing said first groove.