Patent ID: 6105113
Filing Date: 2000-08-15
Classification: G06F

Abstract:
A system for updating virtual memory address-to-physical memory address translations for a computer system, comprising:a central processing unit;a cache memory coupled to said central processing unit;a translational look-aside buffer (TLB) table coupled to the central processing unit, said TLB table having:a page table entry field for storing a list of page table entries, each page table entry identifying a page of physical memory that stores a virtual memory page,a virtual memory address tag field for storing a list of virtual memory address tags, each virtual memory address tag associating a virtual memory address with each page table entry in said page table entry field, anda page table entry address tag field for storing a list of page table entry address tags, each page table entry address tag associating a page table entry address with each page table entry in said page table entry field; anda TLB controller that updates said TLB table without broadcast instructions by an operating system, said TLB controller having:a snooping controller that snoops a cache-memory interconnect for page table entry addresses and for an indication that a page table entry in said cache memory has changed,a search engine that searches said page table entry address tag in said TLB table for a snooped page table entry address when said snooping controller detects that a page table entry has changed, andan updating module that updates a page table entry in said TLB table that is associated with the snooped page table entry address.