Patent ID: 6243791
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A memory system, the system comprising:a main memory adapted to store data;a cache controller coupled to the main memory, the cache controller being adapted to receive a data access request for a selected data set, the data access request having a corresponding access type indicator; anda cache coupled to the cache controller and adapted to store data, where an access time for the cache is less than an access time for the main memory, and wherein the cache includes:a plurality of heterogeneous cache sets each adapted to store data and including first and second cache sets having different characteristics from one another,a control input for receiving the access type indicator for the data access request from the cache controller, where the access type indicator can have a value corresponding to the first cache set and another value corresponding to the second cache set, andcontrol circuitry for checking each one of the plurality of cache sets for a cache hit regardless of the value of the access type indicator.