Patent ID: 8373443
Filing Date: 2013-02-12
Classification: H01L,H03K

Abstract:
1. A logic circuit comprising: a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode; a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; a first terminal electrically connected to the second gate electrode of the second transistor; and a second terminal electrically connected to a portion where the second transistor is connected to the first transistor, wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor; wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor, wherein the first transistor comprises: wherein the second transistor comprises: wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode.