Patent ID: 6436741
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising a logic circuit, and a plurality of first storage circuits and a second storage circuit acting as a storage circuit capable of constituting an optional logic for the semiconductor integrated circuit device; said second storage circuit including a memory array capable of reading and writing data from a memory cell specified by an address signal; an address decoder to decode the address signal and to generate a signal to select a memory cell in the memory array; a feedback path to feed back data read from the memory array to an input side of the address decoder; a switch matrix capable of switching an input address signal or a signal fed back through the feedback path so as to supply the switched signal to the address decoder; and a memory to store control information of each switch in the switch matrix; comprising the steps of:constituting, on said second storage circuit, a test circuit to check said first storage circuits and/or said logic circuit; testing said first storage circuits and/or the logic circuit by the test circuit; and reconstituting said second storage circuit after the test for said first storage circuits and/or the logic circuit is completed.