Patent ID: 8963329
Filing Date: 2015-02-24
Classification: G11C,H01L,H05K

Abstract:
1. A semiconductor device comprising: first to n-th (n is an integer equal to or greater than 2) memories; a controller that designates addresses of the n number of memories; a multi-layer wiring board having lines formed thereon, the lines connecting the controller with the memories; and a solder ball group including a plurality of solder balls arranged in an array, and connecting the controller with the lines of the multi-layer wiring board, wherein a plurality of address lines formed on the multi-layer wiring board includes a plurality of first address lines formed of a first wiring layer of the multi-layer wiring board, the plurality of address lines formed on the multi-layer wiring board includes a plurality of second address lines formed of a second wiring layer of the multi-layer wiring board, the first wiring layer being at a different level from the second wiring layer, and in each of the first and second wiring layers, each of the first and second address lines from the solder balls of the solder ball group is routed in order from the first memory to the n-th memory, wherein in the solder ball group, all of solder balls connected to the first address lines are arranged on an outer peripheral side of the controller relative to all of solder balls connected to the second address lines in planar view.