Patent ID: 6236693
Filing Date: 2001-05-22
Classification: G06F,H04L

Abstract:
A delay matched clock and data generator having data retiming element and a clock retiming element, each retiming element having the functionality of a two-input multiplexer and being connected and operated such that a level on an output(s) is controlled from data control inputs and a timing of transitions on the output(s) is controlled from timing control inputs, the data control inputs of each retiming element corresponding to data input(s) of the two-input multiplexer, and the timing control inputs of each retiming element corresponding to select input(s) of the two-input multiplexer, wherein a clock signal(s) is connected to the timing control inputs of the retiming elements, a data signal(s) is connected to a first data control input of the data retiming element, a delayed data signal(s) is connected to a second data control input of the data retiming element, and timing control signals are connected to the data control inputs of the clock retiming element.