Patent ID: 7734975
Filing Date: 2010-06-08
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising: a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit, wherein while said device circuit built-in self test circuit is executing the built-in self test of said device circuit, said logic built-in self test circuit is set in a low power consumption mode, said pattern generator maintains a data holding state immediately before said logic built-in self test circuit is set in the low power consumption mode, generates a fixed value in place of the pattern, and inputs the fixed value to said logic circuit, and said pattern compactor maintains a data holding state immediately before said logic built-in self test circuit is set in the low power consumption mode and stops a compaction operation.