Patent ID: 7279872
Filing Date: 2007-10-09
Classification: H02M

Abstract:
1. A circuit for processing a supply voltage with a voltage peak to obtain an output voltage with reduced or eliminated voltage peaks, comprising: a first capacitance between a first node and a second node, wherein an input voltage can be generated between the first node and the second node due to the supply voltage; a second capacitance between a third node and a fourth node, wherein the output voltage can be tapped between the third node and the fourth node, wherein the first capacitance has a smaller capacitance value than the second capacitance; a controllable resistor between the first node and the third node; and a control device for controlling the controllable resistor, wherein the control device is formed to control the controllable resistor in a first case, where the input voltage is smaller than a predetermined input voltage set value, such that the controllable resistor has a first high resistance, to control the controllable resistor in a second case, where the input voltage is equal to or higher than the predetermined input voltage set value, and where the output voltage is smaller than a predetermined output voltage set value such that the controllable resistor has a second, lower resistance, so that a charge acceptance of the first capacitance is at least reduced and more charge flows into the second capacitance than in the case where the controllable resistor has the high resistance, and to control the controllable resistor in a third case, where the output voltage at the second capacitance is equal to or higher than the predetermined output voltage set value, such that the same has a third low resistance so that the first capacitance and the second capacitance are substantially connected in parallel, wherein the first resistance is higher than the second resistance, and wherein the second resistance is higher than the third resistance.