Patent ID: 7983067
Filing Date: 2011-07-19
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of first bit lines; a plurality of plate lines formed corresponding to the word lines; a plurality of second bit lines formed corresponding to the first bit lines; a plurality of first ferroelectric capacitors each including a ferroelectric film between two electrodes; a plurality of cell transistors formed corresponding to the first ferroelectric capacitors, and each including a gate coupled to a respective of the word lines; a plurality of second ferroelectric capacitors each including a ferroelectric film between two electrodes; and a sense amplifier configured to detect data stored in a selected one of the first ferroelectric capacitors through a respective of the first bit lines or data stored in selected one of the second ferroelectric capacitors through a respective of the second bit lines, or to write data into the selected one of the first ferroelectric capacitors or the selected one of the second ferroelectric capacitors; wherein the first ferroelectric capacitors and the respective cell transistors connect between the respective first bit lines and the respective plate lines in series, and the second ferroelectric capacitors connect between the respective second bit lines and the respective word lines.