Patent ID: 6560691
Filing Date: 2003-05-06
Classification: G06F

Abstract:
A modulus address generator circuit that calculates the next address to access from a current address and an address shift within a circular buffer having a given length, the modulus address generator circuit comprising:a first register that stores the value of the current address of the circular buffer; a second register that stores the value of the length of the circular buffer; a third register that stores the value of the address shift; a priority encoder that is connected to the second register and generates a mask value from an index table that establishes a correspondence between the value of the length of the circular buffer and the mask value; a separator circuit that is connected to the priority encoder and the first register, the separator circuit calculating the value of an offset address and the value of a base address from the mask value and the value of the current address; a first adder that is connected to the separator circuit and the third register to calculate the value of an absolute offset address from the value of the offset address and the value of the address shift; a complementary operator that is connected to the second register to perform a complementary operation applied to the value of the length of the circular buffer; a length selector that is connected to the complementary operator, the second register, and the third register to select either the value of the length of the circular buffer or the value of the complementary length of the circular buffer delivered by the complementary operator; a second adder that is connected to the length selector and the first adder to calculate the value of a wrapped offset address from the value of the absolute offset address calculated by the first adder and the value of the length selected by the length selector; a first logical gate that is connected to the second adder to invert a sign bit of the value of the wrapped offset address; a sign selector that is connected to the third register, the first logical gate, and the first adder, the sign selector selecting either the value of the sign bit of the absolute offset address or the value of the inverted sign bit of the wrapped offset address, depending on the value of the sign bit of the address shift, to generate a wrap-around flag; an address selector that is connected to the first adder, the second adder, and the sign selector, the address selector outputting the value of an offset second address according to the value of the wrap-around flag; and a second logical gate that is connected to the address selector and the separator circuit to calculate the value of the next address to access within the circular buffer from an OR boolean operation applied to the value of the offset second address and the value of the base address.