Patent ID: 6165895
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A fabrication method of an interconnect comprising the steps of:providing a substrate with a conductive layer, an anti-reflection layer and a cover layer sequentially formed on the substrate;removing a portion of the cover layer and the anti-reflection layer to form a via opening;forming a conductive plug in the via opening;removing the cover layer;forming a photoresist layer with a specific pattern on the conductive plug and the anti-reflection layer;conducting anisotropic etching to form an opening and a conductive lining structures, with the photoresist layer and the conductive plug serving as etching masks;removing the photoresist layer;forming a first dielectric layer to fill the opening;forming a conformal isolation layer on the substrate; andconducting a planarization procedure to expose the conductive plug.