Patent ID: 6395642
Filing Date: 2002-05-28
Classification: C25D

Abstract:
A method to improve copper process integration comprising the steps of:providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon; forming an inter-level dielectric layer over said substrate; patterning and etching said inter-level dielectric layer to form a damascene trench with inside walls therein; performing physical or chemical vapor deposition of a diffusion barrier layer over said substrate including over said inside walls of said damascene trench; forming a metal seed layer over said substrate including over said diffusion barrier layer; performing oxide reduction over said metal seed layer, wherein said performing said oxide reduction on said seed layer is accomplished by using NH3 plasma cleaning, or H2/N2 thermal reduction process; forming a metal layer over said substrate including over said metal seed layer; and removing excess metal layer from said substrate.