Patent ID: 6022804
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A manufacturing method of a semiconductor device comprising:a step of forming an insulating film on a semiconductor substrate;a step of forming on said insulating film, a lower-layer metal wiring having a lower-layer cutout portion formed therein at a predetermined position, said lower-layer cutout portion having a wall surface and being formed by severing said lower-layer metal wiring whereby said lower-layer metal wiring is electrically separated by said lower-layer cutout portion;a step of forming a first inter-layer insulating film covering said lower-layer metal wiring;a step of forming on said first inter-layer insulating film, an intermediate-layer metal wiring having an intermediate-layer cutout portion formed therein at a position above said lower-layer cutout portion, said intermediate-layer cutout portion having a wall surface, being formed by removing a portion of said intermediate-layer metal wiring, and being smaller than said lower-layer cutout portion;a step of forming a second inter-layer insulating film covering said intermediate-layer metal wiring;a step of forming an upper-layer metal wiring on said second inter-layer insulating film;a step of forming a through hole extending in a direction perpendicular to a surface of said semiconductor substrate so as to penetrate said insulating film, said 1st inter-layer insulating film, said intermediate-layer cutout portion and said second inter-layer film, wherein said wall surface of said lower-layer cutout portion is not exposed to said through hole, while said wall surface of said intermediate-layer cutout portion is exposed to said through hole; anda step of forming a contact comprising a conductive material for filling said through hole, wherein said contact electrically contacts said semiconductor substrate and said exposed wall surface of said intermediate-layer cutout portion.