Patent ID: 6593795
Filing Date: 2003-07-15
Classification: H03K

Abstract:
A semiconductor device including a first level shift circuit, the first level shift circuit comprising:a first output node; a first power supply node to which a first power voltage is applied; a second power supply node to which a second power voltage, lower than the first power voltage is applied; a first MOS transistor coupled between the first output node and the first power supply node, the first MOS transistor electrically connecting the first power supply node with the first output node in response to a first control signal; and a first logic circuit coupled between the first power supply node and the second power supply node, the first logic circuit for outputting the first control signal to a gate electrode of the first MOS transistor in response to an application of both a data signal and an enable signal wherein the data signal and the enable signal each have a respective logic level, the logic level of the data signal being independent of the logic level of the enable signal, the logic level of the data signal being either a first logic level or a second logic level, the logic level of the enable signal being either the first logic level or the second logic level, wherein irrespective of the logic level the data signal, the first level shift circuit sets the first output node in response to the first logic level of the enable signal to a predetermined electric potential that is independent of the logic level the data signal.