Patent ID: 8053324
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming gate electrodes on semiconductor wafers; forming source/drain extensions adjacent the gate electrodes; placing portions of the semiconductor wafers in top and bottom regions of a deposition furnace subsequent to forming the source/drain extensions; achieving a pre-deposition temperature of the deposition furnace, wherein a heated temperature at the bottom region is about equal to a heated temperature at the top region; adjusting the pre-deposition temperature such that the heated temperature at the bottom region is higher than the heated temperature at the top region for a first time duration; changing the adjusted pre-deposition temperature to a deposition temperature, wherein the heated temperature at the bottom region is lower than the heated temperature at the top region for a second time duration; depositing a gate spacer layer over the gate electrodes at the deposition temperature; changing the deposition temperature to a post-deposition temperature, wherein the heated temperature at the bottom region is higher than the heated temperature at the top region for a third time duration; and forming deep source/drains adjacent the gate electrodes subsequent to changing the deposition temperature to the post-deposition temperature.