Patent ID: 9025389
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. A method for erasing a first sub-block of a plurality of sub-blocks included in a block of a non-volatile memory device, wherein the first sub-block includes at least one word line, comprising: applying an erase voltage to a substrate; applying a third voltage lower than the erase voltage to the at least one word line of the first sub-block; applying a first voltage to at least one adjacent word line adjacent to the at least one word line of the first sub-block; and applying a second voltage that is in the range of approximately 90% to 100% of the erase voltage to other word lines, wherein the first voltage has a level between the third voltage and the second voltage, and the erasing of the first sub-block is performed when the number of erase-program cycles is equal to or greater than a set number.