Patent ID: 6509778
Filing Date: 2003-01-21
Classification: G01R

Abstract:
A programmable impedance control circuit for controlling the impedance of a driver circuit comprising:at least two sets of impedance devices, a first set comprising p-type field effect transistors (PFET) and a second set comprising n-type field effect transistors (NFET); at least two primary counters operatively connected to said sets of impedance devices and to a clock signal, said primary counters comprising a PFET primary counter and an NFET primary counter, said primary counters selectively activating individual ones of said impedance devices to vary the overall impedance of said driver circuit; and at least two test counters comprising a PFET test counter and an NFET test counter operatively connected to said clock signal, wherein said test counter verifies an operation of said primary counter during manufacturing testing of said driver circuit.