Patent ID: 8932921
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device comprising: providing a semiconductor substrate having a first region and a second region; forming a high k dielectric layer on the semiconductor substrate; forming a first crystalline metal feature with a first orientation on the high k dielectric layer in the first region, wherein the first orientation is {100}; forming a second crystalline metal feature with a second orientation on the high k dielectric layer in the second region, wherein the second orientation is {111}; forming a first source and first drain in the semiconductor substrate in the first region, wherein the first source and first drain include n-type dopant and wherein the first crystalline pure metal feature is interposed between the first source and first drain; and forming a second source and second drain in the semiconductor substrate in the second region, wherein the second source and second drain include p-type dopant and wherein the second crystalline metal feature is interposed between the second source and second drain, wherein the first crystalline metal feature and second crystalline metal feature each includes ruthenium (Ru).