Patent ID: 6437549
Filing Date: 2002-08-20
Classification: H02J,H02M,Y02B

Abstract:
An apparatus, comprising:upper and lower switching circuits, the upper and lower switching circuits capable of alternate activation and deactivation during a first mode of operation to provide outgoing current flow during a first mode of operation, wherein the upper and lower switching circuits respectively comprise first and second transistors, the second transistor having a control terminal coupled to a control logic circuit and being responsive to the control logic circuit to activate and deactivate; a comparator coupled to the lower switching circuit, the comparator being coupled to compare a first voltage, associated with the lower switching circuit, with a second voltage, and to generate a signal if the first voltage is different from the second voltage; the control logic circuit coupled to receive the signal from the comparator and to trigger deactivation of the lower switching circuit to prevent subsequent incoming current flow during a second mode of operation; and a third transistor having a control terminal coupled to the control logic circuit, a first terminal coupled to a first terminal of the second transistor, and a third terminal coupled to an input of the comparator to provide the first voltage to the comparator.