Patent ID: 7582548
Filing Date: 2009-09-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a first gate line, first dummy gates spaced a predetermined interval from a first side of the first gate line, and second dummy gates spaced a predetermined interval from a second side of the first gate line on a semiconductor substrate; forming a thin insulating layer on the first gate line, the first dummy gates, and the second dummy gates; forming a second gate line of a spacer shape on the thin insulating layer on the sidewalls of the first gate line; forming a second gate pad of a spacer shape connected with the second gate line at the first side of the first gate line, wherein the second gate pad fills gaps between the first dummy gates; forming a third gate pad of spacer shape connected with the second gate line at the second side of the first gate line, wherein the third gate pad fills gaps between the second dummy gates; and forming a first contact electrode vertically connected with the first gate line, a second contact electrode vertically connected with one or more of the first dummy gates and the second gate pad, and a third contact electrode vertically connected with one or more of the second dummy gates and the third gate pad.