Patent ID: 7518182
Filing Date: 2009-04-14
Classification: H01L,Y10S

Abstract:
1. An integrated circuit structure comprising: a substrate; a vertically stacked transistor having first, second and third stacked conductive regions formed within the substrate, the second region being of a first conductivity type, and the first and third regions being of a second conductivity type, wherein the second region resides between the first and third regions, the vertically stacked transistor having a first vertical side and a second vertical side; a first bit line and a second bit line located below said transistor and below a surface of the substrate, the first bit line and the second bit line extending in a first direction, the first bit line and the second bit line extending fully below the first conductive region and in contact with the first conductive region; and a conductive line positioned on the first vertical side of the transistor to form a gate of the vertically stacked transistor, the conductive line extending over both the first bit line and the second bit line and in a second direction which is orthogonal to the first direction.