Patent ID: 8429337
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. An apparatus for controlling NAND flash memory, the apparatus comprising: a register unit storing a start address of a macro-command to be executed, wherein macro-commands are described in a command script, and wherein each macro-command comprises a plurality of micro-commands in an array for controlling a unit operation of NAND flash memory; a command fetch unit, if a start address of the macro-command to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command to be executed and sequentially reading the plurality of micro-commands from the start address of the macro-command to be executed; a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation.