Patent ID: 6452858
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of word lines; a plurality of data lines intersecting with said plurality of word lines; a plurality of memory cells installed at desired cross points of said plurality of data lines and said plurality of word lines; and a plurality of word drivers installed to correspond to each of said plurality of word lines; and each of the plurality of word drivers having: a first MOSFET of a first conduction type supplied with a first voltage at one of the source and the drain; a first MOSFET of a second conduction type supplied with a second voltage at one of the source and the drain; a second MOSFET of said second conduction type supplied with said second voltage at one of the source and the drain; a third MOSFET of said second conduction type supplied with a third voltage to one of the source and the drain; and a fourth MOSFET of said second conduction type connected at one of the source and the drain with the remaining one of the source and the drain of said third MOSFET of said second conduction type, wherein each of said plurality of word drivers outputs any one voltage selected from among said first voltage, said second voltage or said third voltage to a corresponding word line.