Patent ID: 6408365
Filing Date: 2002-06-18
Classification: G06F

Abstract:
A multiprocessor system having a plurality of nodes interconnected by an interconnection network, each of said nodes comprising:a main memory for storing data; a cache memory for storing part of the data stored in the main memory in either one of the nodes, said cache memory being accessible faster than said main memory; cache state storage means for storing a state of the data stored in said cache memory; main memory state storage means for storing information of nodes having cache memories which store data corresponding to the data stored in said main memory, and a state of coherency of the data stored in said main memory; a processor for issuing access requests to access data; first coherency controlling means for sending the access request from said processor to a node having said main memory which stores data corresponding to said access request according to an access request from said processor and the state of the data stored in said cache state storage means; second coherency controlling means for making coherency requests to cause nodes represented by the information stored in said main memory state storage means to effect a process to maintain coherency of the data according to an access request from said first coherency controlling means in either one of said nodes and the state of the data stored in said main memory state storage means; third coherency controlling means for effecting a process to maintain coherency of the data in said cache memory and sending a first reply with respect to a completion of the process to maintain coherency to a node having said main memory whose stored data is subjected to the process to maintain coherency according to a coherency request from said second coherency controlling means in either one of said nodes and the state of the data stored in said cache state storage means; fourth coherency controlling means for effecting a process to maintain coherency of the data in said main memory and sending a second reply with respect to the completion of the process to maintain coherency to the node having said processor which has made said access request according to the first reply sent from said third coherency controlling means in either one of said nodes and the state of the data stored in said main memory state storage means of said node; and fifth coherency controlling means for effecting a process to maintain coherency of the data in said cache memory and sending a third reply with respect to a completion of the process to maintain coherency to said processor according to a second reply sent from said fourth coherency controlling means in either one of said nodes and the state of the data stored in said cache state storage means.