Patent ID: 7524714
Filing Date: 2009-04-28
Classification: H01L

Abstract:
1. A method comprising: forming a gate insulating layer and a conductive layer over a semiconductor substrate; forming a first portion of the conductive layer in a gate region to have a first thickness and a second portion of the conductive layer not in the gate region to have a second thickness, the first thickness being greater than the second thickness; implanting impurity ions into a surface of the semiconductor substrate to form a lightly doped drain region overlapping the first portion of the conductive layer; forming a gate electrode by selectively etching the sidewalls of the first portion and the gate insulating layer such that the lightly doped drain region does not overlap the first portion of the conductive layer; forming insulating layer sidewalls at both sides of the gate electrode; and forming source/drain regions in portions of the semiconductor substrate located at both sides of the gate electrode.