Patent ID: 8847637
Filing Date: 2014-09-30
Classification: H03K

Abstract:
1. A multi-modulus frequency divider, comprising: a time-interleaved multi-clock generator configured to generate a plurality of time-interleaved clock signals from a received clock signal; a plurality of bit counters each having an input in communication with the time-interleaved multi-clock generator to receive a respective one of the time-interleaved clock signals, each of the bit counters having an output to provide a counter output signal; a multiplexer having a plurality of multiplexer inputs each in communication with the output of a respective one of the bit counters, the multiplexer having a multiplexer output; and a multiplexer selection module in communication with the multiplexer and generating a selection signal based on a divider ratio, the selection signal controlling which one of the counter output signals at the multiplexer inputs is provided to the multiplexer output.