Patent ID: 8975940
Filing Date: 2015-03-10
Classification: H03K,H03L

Abstract:
1. A semiconductor device comprising: a first signal line coupled to a first external terminal; a second signal line coupled to a second external terminal; a third signal line; a power transistor disposed between the first signal line and the second signal line, a gate electrode of the power transistor being coupled to the third signal line; a clamp circuit disposed between the first signal line and the third signal line to clamp a voltage between the first signal line and the third signal line; a first resistive element disposed between the third signal line and the second signal line; and a monitoring section that monitors a gate voltage of the power transistor, wherein the clamp circuit is configured so to change a clamp voltage, wherein the monitoring section decreases the clamp voltage of the clamp circuit when the gate voltage exceeds a predefined threshold value, wherein the clamp circuit includes a plurality of series-coupled diodes, the monitoring section decreases the clamp voltage of the clamp circuit by forming a current path in parallel with one or more of the diodes, wherein the clamp circuit further includes a switch element coupled across the one or more of the diodes, and the monitoring section forms the current path by turning on the switch element, wherein the monitoring section includes a first transistor having a gate electrode coupled to the third signal line, a voltage generation section that is coupled at one end to a source electrode of the first transistor and coupled at the other end to the second signal line to generate a voltage across both ends thereof in accordance with an input current, and a load element, one end of which is disposed between a drain electrode of the first transistor and the first signal line, and wherein an on/off operation of the switch element is controlled in accordance with the potential difference across the load element.