Patent ID: 6599813
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A method for forming shallow trench isolation on a silicon-on-insulator (SOI) substrate for isolating device areas on said SOI substrate, wherein said SOI substrate comprises a silicon layer on top of a buried oxide layer, the method comprising the steps of:forming a gate oxide layer on said silicon layer; depositing a first polysilicon layer on said gate oxide layer; depositing a polish stop layer on said first polysilicon layer; forming a plurality of trenches, wherein said trenches have a depth extending through said polish stop layer, said first polysilicon layer, said gate oxide layer, and said silicon layer; conformally depositing a silicon oxide layer in said trenches and on said polish stop layer; removing a first portion of said silicon oxide layer by chemical mechanical polishing, such that the top surface of said silicon oxide layer in said trenches is polished down to the same height as the top surface of said polish stop layer; removing a second portion of said silicon oxide layer by etching, such that the top surface of said silicon oxide layer is etched down to a height below the top surface of said polish stop layer and above the top surface of said first polysilicon layer; removing said polish stop layer; depositing a second polysilicon layer on said silicon oxide layer and said first polysilicon layer; and forming a polysilicon gate comprised of said first and second polysilicon layers by photolithography masking and etching said first and second polysilicon layers.