Patent ID: 6397169
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A method for the placement of cells of a logic integrated circuit comprising the steps of:a) generating a netlist mapped to an area using a selected semiconductor technology, said netlist comprising a plurality of interconnected cells and associated nets, wherein each of said nets consists of the interconnect wires driven by its associated cell; b) assigning a unit weight to each of said nets and establishing a convergence criterion; c) performing a rough placement of said cells in accordance with the weights to produce an initial spacing between said cells; d) evaluating the wire length associated with a net at the current cell spacing and adjusting the weights, said adjustment being determined from the synthesis library capacitance related parameters associated with said semiconductor technology; e) performing a placement of the cells in accordance with the assigned weights f) repeating steps d) through e) for a predetermined number of times; g) effecting changes to the netlist; h) modifying said spacing; i) defining partitions; j) repeating steps d) through i) until said convergence criterion is met; k) estimating timing parameters based upon node capacitances; and l) performing a place and route process.