Patent ID: 7752617
Filing Date: 2010-07-06
Classification: G06F

Abstract:
1. An apparatus for updating an embedded code image in a host bus adapter performing high speed data transfer between a host system and a storage system, comprising a processor, a main memory, and a temporary memory, the main memory and the temporary memory storing Microcode Reconstruct and Boot (MRB) format code images, and the apparatus further comprising: the processor executing executable code stored on the main memory occupied by and used by an old code image comprising a first MRB format header, the executable code comprising: a loader stored in the main memory and loading a new code image comprising a second MRB format header into the temporary memory; a branch module stored in the main memory causing the processor to execute a bootstrap module within the new code image; the bootstrap module accessing an old code image version number pointed to by the first MRB format header and a new code image version number pointed to by the second MRB format header; the bootstrap module identifying: the bootstrap module further: a copy module copying the new code image into the main memory space occupied by the old code image.