Patent ID: 6875693
Filing Date: 2005-04-05
Classification: H01L

Abstract:
1. A method for forming a robust copper interconnect structure having increased resistance to void failure, the method comprising: a) providing a substrate having a conductive layer formed thereon, the conductive layer comprising a copper-containing material and having an insulating layer formed thereon, the insulating layer having an opening that exposes a portion of the underlying conductive layer at the bottom of the opening; b) forming a barrier layer on the substrate so that the barrier layer is formed on the insulating layer and on the exposed portion of the conductive layer in the opening; c) removing a portion of the barrier layer at the bottom of the opening to expose the underlying conductive layer by anisotropically etching the barrier layer to expose the conductive layer at the bottom of the opening; and d) forming a conductive plug with a copper-containing material in the opening such that the bottom of the plug is in contact with the exposed conductive layer.