Patent ID: 6812515
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A semiconductor non-volatile memory cell comprising:a first insulating layer over a substrate region; a floating gate comprising a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer, the first polysilicon layer having a predetermined doping concentration and the second polysilicon layer having a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers; a second insulating layer over and in contact with the second polysilicon layer; and a control gate comprising a third polysilicon layer over and in contact with the second insulating layer and a fourth polysilicon layer over and in contact with the third polysilicon layer, the fourth polysilicon layer having a predetermined doping concentration and the third polysilicon layer having a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.