Patent ID: 6389522
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A signal control circuit for outputting, to a subsidiary processing circuit, control signals for controlling input and output of bus signals with respect to the subsidiary processing circuit, the bus signals being transferred via a bus between the subsidiary processing circuit and a main processing circuit, the signal control circuit comprising:a comparing portion that compares at least a bit in at least a predetermined portion of a present bus signal, which is transferred between a main processing circuit and a subsidiary processing circuit at a present timing with corresponding at least a bit in at least a predetermined portion of a preceding bus signal, which is transferred between the main processing circuit and the subsidiary processing circuit at a preceding timing, the comparing portion outputting a delay request signal when the compared result shows that a predetermined difference occurs between the present bus signal and the preceding bus signal; and an output control portion that outputs, to the subsidiary processing circuit, a control signal for controlling input and output of the present bus signal, the output control portion outputting the control signal at a predetermined timing when the compared result shows that the predetermined difference does not occur between the present bus signal and the preceding bus signal, the output control portion delaying the timing of output of the control signal from the predetermined timing when the output control portion receives the delay request signal indicative of the compared result that the predetermined difference occurs between the present bus signal and the preceding bus signal, thereby preventing the input and output of the present bus signal from being influenced from noise that occurs when the bus signal changes from the preceding bus signal into the present bus signal while occurring the predetermined difference.