Patent ID: 6826067
Filing Date: 2004-11-30
Classification: G11C,H01L

Abstract:
A stacked memory device, comprising:a first memory chip having a plurality of control terminals, a plurality of address terminals and two data input/output terminals; and a second memory chip having a plurality of control terminals, a plurality of address terminals and two data input/output terminals, wherein the control terminals of the first memory chip are electrically coupled to the control terminals of the second memory chip correspondingly to serve as control terminals of the stacked memory, the address terminals of the first memory chip are electrically coupled to the address terminals of the second memory chip correspondingly to serve as address terminals of the stacked memory, and the two data input/output terminals of the first memory chip and second memory chip construct four data input/output terminals of the stacked memory, such that the stacked memory accesses data in the first and second memory chip simultaneously according to an access command.