Patent ID: 7508639
Filing Date: 2009-03-24
Classification: H01L

Abstract:
1. An input/output device with robustness of ESD protection, comprising an input/output pad; a first NMOS transistor, comprising a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad; a second NMOS transistor, comprising a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver receiving an output enable signal and an intermediate output signal and comprising a first logic circuit and a level shifter; and an ESD detector coupled to the first pre-driver, wherein when an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current, wherein the first logic circuit is controlled by the output enable signal and the intermediate output signal to generate a control signal when the output enable signal is activated, and wherein the level shifter shifts the voltage level of the control signal.