Patent ID: 6284609
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A Method of fabricating an integrated circuit device comprising:providing an active area in a semiconductor substrate separated from other active areas by isolation regions;forming a dielectric layer overlying said semiconductor substrate and said isolation regions;patterning and etching away said dielectric layer in two distinct areas and within said active area to form two openings to said semiconductor substrate;growing a doped silicon region to fill each of said openings wherein said doped silicon regions form raised source and drain regions;etching away said dielectric layer in said active area between said doped silicon regions forming a gate opening to said semiconductor substrate;conformally growing a gate oxide layer within said gate opening and overlying said dielectric layer and said doped silicon regions;depositing a conducting layer overlying said gate oxide layer and filling said gate opening;planarizing said conducting layer to complete formation of a gate electrode;thermally diffusing dopant atoms from each of said doped silicon regions into said substrate underlying said doped silicon regions to form lightly doped regions; anddepositing an interlevel dielectric layer overlying said gate electrode completing fabrication of said integrated circuit device.