Patent ID: 8548773
Filing Date: 2013-10-01
Classification: G01R

Abstract:
1. A voltage controlled delay line (VCDL) for use in an apparatus for measuring the maximum speed of a chip with automated testing equipment comprising: (a) a first input configured to receive a reference clock signal; (b) a first output configured to output an output clock signal; (c) a second input configured to receive a phase error signal, the phase error signal representing a phase delay between the reference clock signal and the output clock signal; (d) a register having a delay code stored therein, the VCDL being configured to generate the output clock signal by applying the delay code stored in the register to the reference clock signal to delay the reference clock signal, the delay code being adjusted according to the phase error signal until the phase delay is equal to a predetermined value; and (e) a second output coupled to an interface configured to read the delay code from the register of the VCDL and output the delay code to the automated testing equipment when the phase delay is equal to the predetermined value, the outputted delay code corresponding to the maximum speed of the chip.