Patent ID: 6105125
Filing Date: 2000-08-15
Classification: G06F

Abstract:
An apparatus including a decoder for decoding an instruction in a processor having an instruction set and for providing a microcode to a sequencer, the apparatus comprising:a buffer for storing an instruction and associated operands to be decoded;an extraction circuit for reading portions of the instruction from the buffer;at least one read-only memory storing instruction decode tables, the at least one read-only memory coupled to the extraction circuit to receive the portions of the instruction and in response generate a plurality of output signals including a microcode output signal, an information bits output signal, and an output signal indicating an existence of an addressing mode specifier; anda selection circuit includingdata inputs coupled to the microcode output signal of the at least one read-only memory,control inputs coupled to the information bits output signal of the at least one read-only memory, anda selected output coupled to a sequencer.