Patent ID: 6779148
Filing Date: 2004-08-17
Classification: G06F,H03M

Abstract:
A main memory controller connected to a processor through a processor bus, connected to an I/O unit through an I/O bus, and designed to control writing or reading of a main memory, said main memory controller comprising:a first error detection circuit for detecting an error in data on said processor bus; a second error detection circuit for detecting an error in data on said I/O bus: an encoder circuit for producing check bits using object data to be written, which is transferred over one of said processor bus and I/O bus and written in said main memory, and fault information bits which, when one of said first and second error detection circuit detects an uncorrectable error in the object data, enable identification of a detection circuit which detects the uncorrectable error, and for producing a word composed of the object data to be written and the check bits as a word to be written in said main memory; a decoder circuit for producing a syndrome for data read from said main memory under an assumption that the unwritten fault information bits were all zero, and detecting and correcting an error in the object data according to a bit pattern of the syndrome; and a fault information detection table for detecting whether the syndrome produced by said decoder circuit exhibits a specific bit pattern so as to identify the source of an uncorrectable error having occurred before encoding is performed by said encoder circuit.