Patent ID: 7861055
Filing Date: 2010-12-28
Classification: G06F,Y02D

Abstract:
1. A method for configuring memory, the method comprising: monitoring a cache hit rate of a processor; dynamically configuring one or more of a plurality of memory banks integrated within a chip to operate as fast on-chip memory based on said monitoring and based on one or more of a determined start address, a determined end address, and a corresponding one or more of a plurality of fast memory configuration bits; dynamically configuring a remainder of said plurality of memory banks to operate as on-chip level 2 cache memory based on said monitoring, wherein said one or more of said plurality of memory banks configured to operate as fast on-chip memory and said remainder of said plurality of memory banks configured to operate as on-chip level 2 cache memory are accessed via a common address line; comparing at least a portion of a memory address to one or both of said determined start address and said determined end address; selecting a plurality of tag addresses based on a set portion of said memory address; comparing each of said plurality of tag addresses to a tag portion of said memory address; selecting one or more memory locations within said one or more of said plurality of memory banks or within said remainder of said plurality of memory banks based on one or more of: outputting data from said selected one or more memory locations to a bus.