Patent ID: 6021473
Filing Date: 2000-02-01
Classification: G06F

Abstract:
A computer apparatus for maintaining coherency for data transactions of a processor and plurality of bus devices, the computer apparatus comprising:a central processing unit (CPU);a shared memory coupled to and accessible by said CPU;at least a bus device for receiving data items from said CPU over a device bus and for accessing said shared memory over said device bus;bridge circuit coupled between said CPU and said device bus for providing said data items from said CPU to said device bus, said bridge circuit including:a host slave for receiving a write command and said data items from said CPU for determining whether said data item is to be written to said shared memory or to said bus device;a write buffer coupled to said host slave for temporarily storing data items from said CPU before sending said data items to said bus device;a status bit location associated with said write buffer and being coupled to said host slave for storing a status bit, wherein the host slave sets the status bit to indicate that the write buffer is storing a data item, the status bit being cleared when the write buffer is flushed;a bridge master coupled to receive said data item and said associated status bit from said write buffer and said status bit location, respectively, said bridge master being adapted to send said data item from the write buffer to said bus device through said device bus;plurality of dirty bit locations which correspond to each data location within said write buffer, coupled to said host slave for storing a dirty bit, said dirty bit being set when said CPU writes a second data item to said shared memory after having written a first data item to said write buffer, wherein only selective of said second data item in said write buffer is flushed to said device bus in response to said dirty bit when said bus device requests access to said shared memory;an arbiter circuit coupled to a bridge slave for arbitrating bus access requests from said plurality of bus devices and said CPU; anda four-input logical-OR gate coupled between said plurality of dirty bit locations and said bridge slave for providing a signal to said bridge slave indicating when any one or more of dirty bits are set, whereinsaid bridge slave coupled to said plurality of dirty bit locations to receive said dirty bit, the bridge slave for receiving an indication if any dirty bits are set such that when said bus device requests access to said shared memory, said bridge slave informs said bus device to retry said request if any of said dirty bits are set.