Patent ID: 6163851
Filing Date: 2000-12-19
Classification: G06F

Abstract:
A data processor that has a normal operation mode in which it operates in a normal rate, and a power saving mode in which it saves consumed power, and that operates in response to a system clock signal generated by a system clock oscillator in the normal operation mode, said data processor comprising:a peripheral circuit;an alternative clock generator for generating an alternative clock signal used instead of said system clock signal;a clock switching circuit for supplying said peripheral circuit with the alternative clock signal generated by said alternative clock generator in said power saving mode, and with the system clock signal generated by said system clock oscillator in said normal operation mode; andan alternative clock generation controller for controlling generation of the alternative clock signal by said alternative clock generator in said power saving mode,wherein said power saving mode is a sleep mode in which generation of said system clock signal is halted and wherein said alternative clock generation controller comprises a feedback loop controlling circuit which starts generation of the alternative clock signal by said alternative clock generator in the sleep mode by enabling a feedback loop of said alternative clock generator in response to a trigger signal indicative of a start of a processing of said peripheral circuit, and which halts the generation of the alternative clock signal by disabling the feedback loop of said alternative clock generator when one of releasing of said sleep mode and completion of the operation of the peripheral circuit by the peripheral circuit has occurred.