Patent ID: 9213600
Filing Date: 2015-12-15
Classification: G06F,G11C,H03M

Abstract:
1. An apparatus comprising: one or more error-correction decoders; a buffer configured to store data to be decoded by the one or more error-correction decoders; at least one direct memory access (DMA) engine coupling the buffer and the one or more error-correction decoders; and at least one processor enabled to send messages to the at least one DMA engine, wherein the messages are configured to deliver DMA control information and corresponding datapath control information, the data is read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information, and the one or more error-correction decoders are enabled to decode the data read from the buffer according to the corresponding datapath control information.