Patent ID: 6598149
Filing Date: 2003-07-22
Classification: G06F

Abstract:
An apparatus comprising:a plurality of registers to operate on data of a first mode when operating in a first state and to operate on data of a second mode when operating in a second state; a tag bit for each said register, in which each tag bit denotes if its corresponding register contains data when operating in the first state, but in which the tag bits of all of said registers are expected to be placed into a same state when operating in the second state; a tag status bit to identify if said tag bits are not all placed to the same state when transitioning from the first state to the second state; a control circuit coupled to said tag bit and said tag status bit to generate a substitute condition satisfying the expected placement of said tag bits to have all the same state when said tag status bit indicates an inconsistency between actual bit values of said tag bits and the expected same state for said tag bits; and said control circuit to remove the substitute condition once all of said tag bits are made consistent to the expected same state.