Patent ID: 6790732
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of forming a self-aligned dual gate transistor device, comprising:providing a substrate comprising an insulator layer over a substrate material and semiconductive layer over at least a portion of the insulator layer, the insulator layer comprising an insulative material; forming a first gate structure over the semiconductive layer, the first gate structure comprising an insulative cap and opposing insulative sidewall spacers; forming a pair of alignment structures at least partially through the insulator layer, one of the alignment structures being received against one of the insulative sidewall spacers of the first gate structure, another of the alignment structures being received against another of the insulative sidewall spacers of the first gate structure; and removing insulative material of the insulator layer between the alignment structures and thereafter forming a second gate structure between the alignment structures opposingly self-aligned to the first gate structure and operatively proximate the semiconductive layer.