Patent ID: 6760259
Filing Date: 2004-07-06
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a first basic memory block having a plurality of memory cells arranged in a matrix and having a first storage capacity corresponding to a unit of collective erasure, said collective erasure not allowed in a partial region of said first basic memory block, said partial region of said first basic memory block having a second storage capacity smaller than said first storage capacity; a plurality of second basic memory blocks provided independent of said first basic memory block, each having a plurality of memory cells arranged in a matrix and each having said second storage capacity, a total storage capacity of said plurality of second basic memory blocks being equal to said first storage capacity; and an erasure control circuit switching, in accordance with a switching signal, between a first operation of erasing one of said plurality of second basic memory blocks in accordance with an erasure command, and a second operation of erasing said plurality of second basic memory blocks collectively in accordance with said erasure command.