Patent ID: 7363563
Filing Date: 2008-04-22
Classification: H04L

Abstract:
1. A built-in self test (BIST) circuit for a data transceiver, the BIST circuit comprising: a clock synthesis unit (CSU) having a first clock signal as an output; a parallel-in, serial-out (PISO) circuit configured to receive parallel data and to generate serial data, where a data rate of the serial data corresponds to a serial clock frequency provided to the PISO circuit via a clock signal input; a multiplexer having at least a first input, a second input, and an output, where the first input is coupled to the first clock signal from the clock synthesis unit (CSU), where the second input is coupled to a second clock signal from an asynchronous clock source, where the output of the multiplexer is coupled to the clock signal input of the PISO circuit, where the multiplexer provides the first input to the clock signal input of the PISO circuit when the data transceiver is in a normal mode and provides the second input to the clock signal input of the PISO circuit when the data transceiver is in a test mode.