Patent ID: 8093116
Filing Date: 2012-01-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: providing a semiconductor substrate; forming a high-k dielectric layer over the substrate; forming a semiconductor layer over the high-k dielectric layer; removing a portion of the semiconductor layer such that the semiconductor layer in a first region has a first thickness and the semiconductor layer in a second region has a second thickness less than the first thickness; forming a hard mask layer over the semiconductor layer; patterning the hard mask layer, semiconductor layer, and high-k dielectric layer to form a first gate structure in the first region and a second gate structure in the second region; forming an interlayer dielectric (ILD) over the first and second gate structures; performing a first chemical mechanical polishing (CMP) on the ILD that substantially stops at the semiconductor layer of the first gate structure; removing the semiconductor layer from the first gate structure thereby forming a first trench, wherein the hard mask layer of the second gate structure protects the semiconductor layer of the second gate structure; forming a first metal layer to fill in the first trench; removing the hard mask layer and semiconductor layer from the second gate structure thereby forming a second trench; and forming a second metal layer to fill in the second trench.