Patent ID: 7804132
Filing Date: 2010-09-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: an SOI substrate having a semiconductor substrate, a buried oxide film formed on said semiconductor substrate, and an SOI layer having a first conductivity type; and at least one MOS transistor provided on said SOI layer, wherein said at least one MOS transistor comprises: a source region and a drain region having a second conductivity type and selectively provided in a surface of said SOI layer; a body region having a first conductivity type and corresponding to said SOI layer sandwiched between said source region and said drain region; a gate electrode provided on said body region; and a plurality of semiconductor regions having a first conductivity type and provided in a surface of said source region in a vicinity of said gate electrode so as to be spaced and aligned along said gate electrode and electrically connected to said body region, wherein an active region comprising said source region, said drain region, and said body region is surrounded by a full isolation insulation film penetrating said SOI layer and reaching said buried oxide film, and said plurality of semiconductor regions are arranged such that a first distance between an end of said semiconductor regions and a nearest edge of said active region becomes half of a second distance between said semiconductor regions.