Patent ID: 6243794
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A data-processing system with cc-NUMA architecture comprising a plurality of nodes each constituted by at least one processor intercommunicating with a DRAM-technology local memory by a local bus, the nodes intercommunicating by remote interface bridges and at least one intercommunication ring,the at least one processor of each node having access to a system memory space defined by memory addresses each of which identifies a block of data and one byte within the block, wherein access time by said at least one processor to said system memory is substantially greater than access time to said DRAM-technology local memory by said at least one processor,and further wherein each node comprises:a unit for configuring a second portion of the DRAM-technology local memory as a remote cache of the node for caching remote system memory, wherein said unit uniquely maps a first portion of the system memory space, which is different for each node, onto a first portion of the DRAM-technology local memory, and maps the second portion of the system memory space which is uniquely mapped onto a portion of the DRAM-technology local memory of all of the other nodes onto said second portion of the DRAM-technology local memory, anda SRAM-technology memory for storing labels each associated with a block of data stored in said second portion of DRAM-technology local memory and each comprising an index identifying the block and bits indicating a coherence state of the block so that said second portion of DRAM-technology local memory in each node constitutes a remote cache of the node for caching said remote system memory.