Patent ID: 6803306
Filing Date: 2004-10-12
Classification: H01L,Y10S

Abstract:
A metal-insulator-metal capacitor process, comprising:forming a first dielectric layer on a substrate; forming a first metal layer in the first dielectric layer; forming a stop layer on the first dielectric layer; forming a second dielectric layer on the stop layer; forming a first patterned mask layer on the second dielectric layer; performing an etching process, using the first patterned mask layer as an etching mask, so that a first opening and a second opening are formed in the second dielectric layer, thereby exposing portions of the stop layer above a first region and a second region of the first metal layer, respectively; forming a second patterned mask layer on the second dielectric layer and a part of the stop layer; performing a further etching process, using the second patterned mask layer as a further etching mask, to etch the stop layer below the second opening and to partially etch a third opening adjacent the second opening in the second dielectric layer without exposing the stop layer thereunder; and forming a second metal layer over the substrate so as to fill the first, second and third openings; wherein a metal-insulator-metal (MIM) capacitor is formed by the first region of the first metal layer, the stop layer and the filled first opening, and the filled second opening forms a via between the first and second metal layers, and the first and second metal layers include copper.