Patent ID: 9054739
Filing Date: 2015-06-09
Classification: H03M

Abstract:
1. An error correction device comprising: a plurality of first calculators each of which is provided for each of a plurality of variable nodes to which a plurality of pieces of 1-bit data coded on the basis of a low density parity check matrix and is configured to calculate a first message representing a probability that a value of the data input to the variable node is 1; a plurality of second calculators each of which is provided for each of a plurality of check nodes connected to the variable nodes in connecting states according to the low density parity check matrix and is configured to calculate a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the respective two or more variable nodes connected to the check node; a plurality of estimators each of which is provided for each of the variable nodes and is configured to estimate a true value of the data input to the variable node to generate an estimated value by using the first messages and the second messages; and an inverter configured to invert the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.