Patent ID: 9076880
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. An asymmetric high-voltage JFET comprising: a semiconductor substrate with an upper surface; a deep well of a first type of conductivity in the semiconductor substrate; a further well, which is arranged on the upper surface of the semiconductor substrate in the deep well and which has a second type of conductivity opposite to the first type of conductivity; a shallow well, which is arranged on the upper surface of the semiconductor substrate in the further well and which has the first type of conductivity; a first contact region for source arranged in the further well and a second contact region for drain arranged in the further well; a third contact region for gate arranged between the first contact region and the second contact region in the shallow well; and a plurality of spatially separated partial regions of the third contact region, the plurality of spatially separated partial regions being separated by one or more isolation regions, wherein a first distance between the first contact region and the third contact region is smaller than a second distance between the second contact region and the third contact region, and wherein within the further well there is an electric connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.