Patent ID: 6366525
Filing Date: 2002-04-02
Classification: G11C

Abstract:
A semiconductor memory of the dynamic random access type, comprising:memory cells combined in addressable units of bit lines and word lines; said memory cells disposed in at least four matrix memory cell arrays in a memory field, said memory cell arrays having outer edge areas and said memory field having an edge area; each of said memory cell arrays having two sides, each of said sides disposed opposite one side of another of said memory cell arrays; row decoders each assigned to a respective one of said memory cell arrays for selection of one of said word lines in said memory cell array, and column decoders each assigned to a respective one of said memory cell arrays for selection of one of said bit lines in said memory cell array; said column decoders each disposed at said outer edge area of said assigned memory cell array and at said edge area of said memory field; a row selection signal line for transmission of a row selection signal, said row selection signal line connected to said row decoders in said at least four memory cell arrays for selection of one of said word lines; said row selection signal line and said row decoders disposed between respective opposite sides of said memory cell arrays; and said column decoders for selection of one of said bit lines in said assigned memory cell arrays connected to said row selection signal line for transmission of a column selection signal.