Patent ID: 7202705
Filing Date: 2007-04-10
Classification: H03K

Abstract:
1. A dynamic logic circuit comprising: a dynamic logic tree formed from one or more transistors coupled between a summing node and a first power supply rail corresponding to a first logical state, and wherein gates of said transistors are coupled to one or more logical input signals; a precharge circuit connected to said summing node and a second power supply rail for setting said summing node to a precharge voltage level corresponding to a second logical state opposite from said first logical state, said precharge circuit having an input coupled to a precharge clock signal, whereby said summing node is held in said second logical state while said precharge clock signal is asserted; an inverter having an input coupled to said summing node and an inverter output providing an output signal of said dynamic logic circuit; an inverter foot device coupled between said first power supply rail and a power supply rail of said inverter, whereby conduction through said inverter to said first power supply rail is disabled in response to assertion of a power control signal coupled to an input of said inverter foot device; and a control logic for providing said power control signal and said precharge clock signal, wherein said power control signal is deasserted a predetermined time after deassertion of said precharge clock signal and asserted a second predetermined time after said assertion of said precharge clock signal, whereby current leakage into said inverter is reduced when said power control signal is asserted.