Patent ID: 6477598
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A controller for a digital memory partitioned into a plurality of banks, the memory divided into addresses that are accessed by row access strobe (RAS) and column access strobe (CAS) signals, the controller comprising:a plurality of transaction processor state machines, each of which having an input and an output; a plurality of bank state machines, each of which having an input and an output, the output of each of the plurality of bank state machines coupled to the input of each of the plurality of transaction processor state machines, each of the plurality of bank state machines configured to provide a signal indicating whether it is idle to each of the plurality of transaction state machines; a command arbitor with an input and an output, the command arbitor input coupled to the output of each of the plurality of transaction processor state machines and the output of each of the plurality of bank state machines, the command arbitor output coupled to the input of each of the plurality of transaction processor state machines and to the input of each of the plurality of bank state machines; wherein each of the plurality of transaction processor state machines is configured to issue RAS and CAS commands to the arbitor; each of the plurality of bank state machines is configured to issue bank precharge commands to the arbitor; and the arbitor is configured to arbitrate between at least RAS, CAS and bank precharge requests received from transaction processor state machines and bank state machines to generate a winning command, which the arbitor is configured to output.