Patent ID: 6815770
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A metal-oxide-semiconductor (MOS) transistor structure having reduced sheet resistance in the source/drain extensions, comprising:a gate electrode formed on a semiconductor substrate; a gate insulating layer formed between the gate electrode and the semiconductor substrate; a spacer disposed on each sidewall of the gate electrode; a lightly doped source/drain (S/D) extension formed in the semiconductor substrate under the spacer, the lightly doped S/D extension comprising a raised epitaxial layer bordering bottom of the spacer; wherein the spacer consists of an offset spacer, a liner and a silicon nitride spacer, and wherein the liner directly overlies the epitaxial layer; a heavily doped S/D region formed in the semiconductor substrate next to an outer edge of the spacer; and a silicide layer formed on the heavily doped S/D region.