Patent ID: 7724567
Filing Date: 2010-05-25
Classification: G06F,G11C

Abstract:
1. A memory device comprising: a memory word comprising a plurality of thyristor storage elements, each thyristor storage element comprising a first current electrode to receive a corresponding data bit of a data word during a write cycle, a second current electrode, and a control electrode; and a control module to place each respective thyristor storage element into a programmed state based upon a corresponding signal level during a write cycle, where the programmed state can be a conductive state or a non-conductive state, and during a refresh mode the control module is to refresh each thyristor storage element of the memory word at the conductive state by providing a high-signal level to the first current electrode of each conductive thyristor while a first low-signal level is provided to the second current electrode of each thyristor at the conductive state.