Patent ID: 6027971
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of forming an integrated circuit memory device, comprising the steps of:patterning a field oxide isolation region at a face of a semiconductor substrate to define an active region therein;forming a gate electrode of a memory device on the active region;forming a word line on the field oxide isolation region and on the gate electrode;forming a first protection layer on an upper surface of the word line;implanting source and drain region dopants of first conductivity type into the active region, using the first protection layer as an implant mask; thenetching the field oxide isolation region to expose the face of the substrate, using the first protection layer as an etching mask; andimplanting dopants of first conductivity type into the exposed face of the substrate to define a common source region therein which is electrically coupled to the memory device, using the first protection layer as an implant mask.