Patent ID: 8245103
Filing Date: 2012-08-14
Classification: H03M

Abstract:
1. An arithmetic circuit of concatenated codes used for a coding circuit or a decoding circuit, comprising: an arithmetic section to perform an arithmetic operation for coding or decoding; a first to a τth (τ is an integer of 2 or more) registers; and an address control section to specify an address of a register to which an arithmetic operation result of the arithmetic section is written among the first to the τth registers, wherein the address control section performs an address control for each frame, in which a first address is changed to switch a writing destination of the arithmetic operation result for a top segment of a frame sequentially and circularly to the first to the τth registers for respective frames, and an address control for each segment, in which a second address is changed to switch a writing destination of the arithmetic operation result for each segment in the frame sequentially and circularly from the register indicated by the first address for the top segment of the frame, in a direction from the τth register to the first register for respective segments, wherein the arithmetic operation result of the arithmetic section is written in the first to the τth registers for the respective segments in accordance with the second address.