Patent ID: 7345938
Filing Date: 2008-03-18
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first memory cell array including a plurality of first word lines, a plurality of first bit lines, and a plurality of first memory cells at intersections of the plurality of first word lines and the plurality of first bit lines; a second memory cell array including a plurality of second word lines, a plurality of second bit lines, and a plurality of second memory cells at intersections of the plurality of second word lines and the plurality of second bit lines; a plurality of first sense amplifiers arranged in a direction parallel to the plurality of first word lines and coupled to the plurality of first bit lines; a plurality of second sense amplifiers arranged in a direction parallel to the plurality of second word lines and coupled to the plurality of second bit lines; a first wiring line coupled to first power supply nodes of the plurality of first sense amplifiers commonly; a second wiring line coupled to second power supply nodes of the plurality of first sense amplifiers commonly; a first switch coupled between the first wiring line and a first power line supplied a first voltage; a plurality of second switches coupled between the first wiring line and a second power line supplied a second voltage larger than the first voltage; a plurality of third switches coupled between the second wiring line and a third power line supplied a third voltage smaller than the first voltage; and a fourth switch coupled between the first wiring line and the second wiring line, wherein the first and fourth switches are provided between a first area including the plurality of first sense amplifiers and a second area including the plurality of second sense amplifiers, and wherein the plurality of second switches are provided along the first power line and the plurality of third switches are provided along the second power line.