Patent ID: 6332191
Filing Date: 2001-12-18
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache coupled to receive a first fetch address corresponding to two or more instructions terminated by a branch instruction, wherein the first fetch address locates an initial one of the two or more instructions in memory, and wherein the instruction cache is configured to store a plurality of instructions; anda branch prediction unit coupled to receive the first fetch address, the branch prediction unit comprising a storage storing branch prediction information corresponding only to branch instructions, wherein the storage is configured to output first branch prediction information in response to the first fetch address, and wherein the branch prediction unit is configured to generate a first branch prediction for the branch instruction terminating the two or more instructions located by the first fetch address responsive to the first branch prediction information, wherein the brancih prediction unit further comprises logic coupled to receive the first branch prediction and a second branch prediction corresponding to the first fetch address, and wherein the logic is configured to signal that the two or more instructions are to be cancelled if the first branch prediction disagrees with the second branch prediction.