Patent ID: 6456551
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A synchronous semiconductor memory device comprising:a plurality of main data lines, each main data line coupled between one of a plurality of block sense amplifier arrays and one of a plurality of data output buffers, and each of said main data lines configured to prefetch a plurality of cell data segments from a plurality of memory cells corresponding to an input/output port and transmit the data segments to a corresponding data output buffer; and a pass/latch part coupled to a plurality of corresponding block sense amplifiers within a corresponding block sense amplifier array, said pass/latch part configured to receive the plurality of cell data segments from the corresponding block sense amplifiers in parallel in response to a plurality of control signals applied to the pass/latch part, and said pass/latch part further configured to transmit the cell data segments to a corresponding main data line in series.