Patent ID: 8954825
Filing Date: 2015-02-10
Classification: G06F,G11C,H03M

Abstract:
1. An apparatus comprising: first memory cells; a first access line configured to access the first memory cells; second memory cells; a second access line configured to access the second memory cells; and a controller used to cause data to be stored in a first memory portion of the first memory cells, to cause additional data to be stored in a first memory portion of the second memory cells, to cause at least a portion of an error correction code associated with the additional data to be stored in a second memory portion of the second memory cells, to cause a first portion of an error correction code associated with the data to be stored in a second memory portion of the first memory cells, and to cause a second portion of the error correction code associated with the data to be stored in a third memory portion of the second memory cells, wherein the controller is configured to cause the at least a portion of the error correction code associated with second data to be stored in the second memory portion of the second memory cells concurrently with storing of the second portion of the error correction code associated with the data in the third memory portion of the second memory cells.