Patent ID: 6085313
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A computer processor system for executing floating point instructions having an operation code for an instruction having more than four bytes comprisinga floating point processor with a processor cache and having a separate adder for performing X-B-D addressing, including base, extended and displacement B-X-D addressing, and associated gating circuitry for general purpose register (GPR) access in a critical path determining a cycle time of the processor system and also having instruction registers for instructions of specific format for processing floating point operations,said separate adder being enabled for executing floating point instructions register indexed from storage instructions in an RX (register indexed from storage) format having an operation code field of 8 bits as said RX format's initial field and having an R1, X2, B2 and D2 fields in said instruction format following said operation code field for a first Operand Register (R1) field, a second Operand Index Register (X2) field, a second Operand Base Register (B2) field, and a second Operand Displacement Amount (D2) field respectively,and wherein said instruction register is enabled to decode an instruction with processor decode logic after loading an instruction text into the instruction register for performing instruction decode logic, and wherein said separate adder for executing floating point instructions is also enabled for processing register indexed extended instructions after said register indexed extended instructions have been loaded for an instruction text into the instruction register to perform instruction decode logic in which said register indexed extended instruction is in an RXE format having an operation code field as said RXE format's initial field of 8 bits and having R1, X2, B2 and D2 fields following said operation code field and register indexed extensions of the operation code placed after the R1, X2, B2 and D2 fieldswhere instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor decode logic to determine from an initial 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and wherein register indexed extensions of the operation code for said register indexed extended instructions are placed in an instruction beyond the first four bytes of the instruction format, whereby the operation codes are assigned for the processor in such a way that after the processor decode logic determines from the first 8 bits of the operation code alone the exact format of the instruction, and that an instruction being decoded is an RXE format instruction, the processor decode logic gates correct information to said separate adder, andin which instructions are processed in a six cycle pipeline, in which prior to a first cycle of the six cycle pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation; while during a second cycle of the six cycle pipeline the address add of B+X+Displacement is performed and sent to the processor's cache, and during a third and fourth cycles of the six cycle pipeline the cache is respectively accessed and data is returned, and during a fifth cycle of the six cycle pipeline execution of the fetched instruction occurs with the result putaway in a sixth cycle of the six cycle pipeline.