Patent ID: 6871102
Filing Date: 2005-03-22
Classification: G06F

Abstract:
1. An apparatus for verifying a memory coherency of a duplication processor having a symmetrical structure comprising: an active processor in which a standby memory read command (SMRC) is generated and transmitted by hardware and then a read data of a standby memory which has been inputted corresponding to the SMRC is image-buffered to verify a memory coherency; and a standby processor in which the SMRC transmitted from the active processor is analyzed and a read command of a standby memory is outputted, and then data read from the standby memory is transmitted to the active processor, wherein the active processor comprises: a standby memory image buffer (SMIB) for temporarily storing a read data of the standby memory; a CPU for generating the SMRC; a first memory controller for storing the read data of the standby memory in the SMIB; a first processor bus controller for applying the read data of the standby memory to the first memory controller; and a first duplication processor for informing the standby processor of a registered SMRC when the SMRC is registered by the CPU, and outputting a command done signal to the CPU when the reading operation of the standby memory is completed.