Patent ID: 6269439
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A micro processor comprising:a means for storing instructions;a means for fetching an instruction from the instruction storing means;a means for decoding the fetched instruction;a means for executing the decoded instruction to produce an executed result;a memory;a means for accessing the memory;a means for writing the executed result from the accessed memory; anda means for pipeline processing the operations in the instruction fetching means, the instruction decoding means, the instruction executing means, the memory accessing means, and the writing means,the instruction fetching means includinga program counter successively designating addresses in the instruction storing means,an address storage portion for exclusively storing a branch destination address included in the branch instruction, said address storage portion being separate and distinct from said program counter,an instruction storage portion having a plurality of simultaneously accessible bank regions in which instructions are stored, a fetch portion simultaneously fetching a first instruction stored at a first address in the instruction storing means, the first address designated by the program counter, and a second instruction stored at a second address in the instruction storing means, the second address designated by the address stored in the address storage portion when the decoded instruction is the branch instruction, anda selection portion for selecting one of the simultaneously fetched first and second instructions in response to the determination of the branch condition in the branch instruction and outputting said one of the simultaneously fetched first and second instructions to the instruction decoding means.