Patent ID: 8736329
Filing Date: 2014-05-27
Classification: G06F,H03K

Abstract:
1. A duty cycle module comprising: a first programmable delay to receive an input clock signal and output a first delayed clock signal; an inverter to receive the input clock signal and output an inverted clock signal; a second programmable delay to receive the inverted clock signal and output a second delayed clock signal; a latch to combine the first delayed clock signal and the second delayed clock signal and generate a corrected clock signal; a first timing circuit to measure a first pulse width of the corrected clock signal and output a first measurement; a second timing circuit to measure a second pulse width of the corrected clock signal and output a second measurement; a first comparator to output an UP control signal if the first measurement is greater than the second measurement at a desired time; a second comparator to output a DOWN control signal if the second measurement is greater than the first measurement at the desired time; and a duty cycle controller to receive at least one of the UP control signal and the DOWN control signal and adjust a setting of one of the first programmable delay and the second programmable delay based on the received at least one control signal in order to adjust a duty cycle of the corrected clock signal.