Patent ID: 7107399
Filing Date: 2006-09-12
Classification: G06F,G11C

Abstract:
1. In a memory structure having a plurality of ordered memory levels, and forward and return paths for interconnecting said memory levels and a processor, each said memory level having a controller in said return path for receiving responses from an immediately higher one of said levels, if any, and for transmitting responses to an immediately lower one of said levels, except for the controller of the lowest one of said levels which transmits responses instead to said processor, each said controller having a buffer, a method of transferring requests from said processor on said forward path and responses to said requests on said return path to said processor, said method comprising the steps of: transmitting each request from said processor to each of said levels; if a request at any one of said levels is a read request addressed to the memory of said one level, then transmitting a response to said read request on said return path along with up to one other response from said buffer of said controller of said one level; if a request at said any one of said levels is a write request addressed to the memory of said one level, then transmitting up to two responses from said buffer of said controller of said one level on said return path; if a request at said any one of said levels is addressed to one of said levels higher than said one level, then transmitting up to two responses from said buffer of said controller of said one level on said return path; and if a request at said any one of said levels is addressed to one of said levels lower than said one level, then transmitting up to one response from said buffer of said controller of said one level on said return path.