Patent ID: 7413946
Filing Date: 2008-08-19
Classification: H01L

Abstract:
1. A method of forming a CMOS device comprising: forming a plurality of first type wells in a substrate; forming a plurality of second type wells in said substrate; providing a first mask over said substrate overlying at least one of said second type wells wherein said second type wells masked by said first mask define standard voltage threshold first type regions and said second type wells not masked by said first mask define low voltage threshold first type regions; doping said substrate with a first voltage threshold implant such that said low voltage threshold first type regions and said second type wells are exposed to said first voltage threshold implant; removing said first mask from said substrate; providing a second mask over said substrate overlying at least one of said first type wells wherein said first type wells masked by said second mask define standard voltage threshold second type regions and said first well types not masked by said second mask define low voltage threshold second type regions; doping said substrate with a second voltage threshold implant such that said low voltage threshold second type regions and said first type wells are exposed to said first voltage threshold implant; forming at least one polysilicon gate over each of said first and second type wells; providing a third mask overlying each polysilicon gate formed over said second type wells; doping said polysilicon gates over each of said first type wells with a first gate conductor dopant; removing said third mask; providing a fourth mask overlying each polysilicon gate formed over said first type wells; and doping said polysilicon gates over each of said second type wells with a second gate conductor dopant.