Patent ID: 8932948
Filing Date: 2015-01-13
Classification: G11C,H01L

Abstract:
1. A method of forming a NAND flash memory integrated circuit comprising: forming a first polysilicon layer overlying a gate dielectric layer; forming a first dielectric layer overlying the first polysilicon layer; forming a second polysilicon layer overlying the first dielectric layer; removing the second polysilicon layer in an array area using the first dielectric layer as an etch stop, while maintaining the second polysilicon layer in a peripheral area; depositing a second dielectric layer and a third polysilicon layer to replace the second polysilicon layer in the array area; forming a floating gate in the array area from a portion of the first polysilicon layer and a portion of the third polysilicon layer connected through a portion of the second dielectric layer; and forming a transistor gate in the peripheral area from a portion of the first polysilicon layer and a portion of the second polysilicon layer connected through a portion of the first dielectric layer.