Patent ID: 6401181
Filing Date: 2002-06-04
Classification: G06F,Y10S

Abstract:
A computing system having a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, said system comprising:a plurality of memory blocks in said real memory system for storing said data, a physical memory storage for storing the data of the real memory blocks, each said real memory block partitioned into one or more sectors, each comprising contiguous bytes of said physical memory; an index table structure in said physical memory storage having entries for associating a real address with zero or more sectors of said physical memory, each index table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, said table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by said processor; a control device associated with said physical memory for dynamically allocating sectors in a memory block and further calculating an offset of said real address in said memory block for indexing into an allocated sector for data read and data write operations thereto, said control device implementing a free list structure having address pointers for pointing to unallocated sectors to be allocated and maintaining a top entry pointer for pointing to a sector address corresponding to a next sector in said list to be allocated; and, a cache memory comprising a portion of said free list structure and including a first entry corresponding to a sector address pointed to by said top entry pointer and a last entry, wherein, upon determination that a sector corresponding to said last entry stored in said cache has been allocated, said control device filling said cache memory by loading contents of new unallocated sector address pointers into said cache, and setting said top entry pointer to a first entry in said cache.