Patent ID: 8664101
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A method of manufacturing a vertical memory device, comprising: forming a first insulating interlayer on a substrate including a first region and a second region, the first insulating interlayer having a top surface, a height of which is greater at least a portion in the first region than in a second region; sequentially forming a first planarization stop layer and a second insulating interlayer on the first insulating interlayer; planarizing the second insulating interlayer until a portion of the first planarization stop layer is exposed; removing portions of the first planarization stop layer and the first and second insulating interlayers in the second region to expose a surface of the substrate; forming a lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern, the first insulation layer patterns and the first sacrificial layer patterns being alternately and repeatedly formed on the exposed surface of the substrate, the second planarization stop layer pattern being formed on an outermost first insulation layer pattern; forming a third insulating interlayer pattern in a space between the lower mold structure and the first insulating interlayer on the substrate; and forming an upper mold structure on the lower mold structure.