Patent ID: 6393530
Filing Date: 2002-05-21
Classification: G06F

Abstract:
A paging system for a multi-processor system, comprising:a system having: a system address, and system resources addressable within said system address space; a plurality of processing nodes, each of said processing nodes having: a processor with a defined addressable local memory space, local resources addressable by said processor within said local memory space, an interface for interfacing with said system, and a paging device for paging a portion of said local address space to said system address space through said interface, with the unpaged portion of said local address space reserved for said local resources and not addressable from said system, and wherein said paged to portion of said system address space is only addressable by the one of said paging devices associated therewith, such that none of the other of said processors in the other of said nodes has access thereto, said paging device operable to generate an address in said system address space; wherein said local resources include addressable local memory such that said addressable local memory is addressable within said unpaged portion of said local address space and occupies a unique address within said local address space.