Patent ID: 6448137
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method of forming an Nitride read only memory (NROM) embedded with mixed-signal circuits on a semiconductor substrate, the surface of the semiconductor substrate divided into at least a memory area and a periphery area, the periphery area comprising a plurality of active areas isolated by an isolation layer, the method comprising:forming a bottom electrode layer of a capacitor on the isolation layer in the periphery area; performing an oxide-nitride-oxide (ONO) process to form an ONO dielectric layer comprising a top oxide layer, a silicon nitride layer and a bottom oxide layer on the surface of the semiconductor substrate that covers the surface of the bottom electrode of the capacitor; performing a first lithography process to form a patterned first photoresist layer on the surface of the ONO dielectric layer, the first photoresist layer defining a plurality of bit line patterns in the memory area and covering the periphery area; performing a first anisotropic etching process to etch the ONO dielectric layer not covered by the first photoresist layer; performing a first ion implantation process to form a plurality of buried bit lines in the semiconductor substrate not covered by the first photoresist layer in the memory area; removing the first photoresist layer; performing a second photolithography process to form a patterned second photoresist layer on the surface of the semiconductor substrate, the second photoresist layer defining ion implantation well regions in the periphery area and covering regions atop the bottom electrode of the capacitor and all of the memory area; performing a second anisotropic etching process to etch the ONO dielectric layer not covered by the second photoresist layer in the periphery area; performing a second ion implantation process, utilizing the second photoresist layer as a mask, to form at least one ion well in the semiconductor substrate not covered by the second photoresist layer in the periphery area; removing the second photoresist layer; performing a wet etching process to etch and clean the surface of the active area in the periphery area; peforming at least one oxidation process to form at least one gate oxide layer with a specific thickness on the active area in the periphery area and form a thermal oxide layer atop each of the buried bit lines in the memory area; forming a polysilicon layer on the semiconductor substrate; performing a third photolithography process to form a patterned third photoresist layer on the polysilicon layer, the third photoresist layer defining a gate pattern, a pattern of a top electrode of the capacitor and a resistor pattern in the periphery area, and a word line pattern in the memory area; performing a third anisotropic etching process to remove the polysilicon layer not covered by the third photoresist layer and form at least a gate, the top electrode of the capacitor and a resistor in the periphery area, and a word line in the memory area; and removing the third photoresist layer.