Patent ID: 6773994
Filing Date: 2004-08-10
Classification: H01L

Abstract:
An integrated circuit structure comprising:a semiconductor layer having a major surface formed along a plane; a first and a second spaced-apart doped region formed in the surface; an isolation region disposed overlying and between said first and said second regions for electrically insulating said first and said second regions; a plurality of layers overlying said isolation region, including a first and a second trench therein, wherein said first and said second trenches extend through said isolation region; a third doped region formed in said first trench over said first doped region, and of a different conductivity type than said first doped region; a fourth doped region formed in said second trench over said second doped region, and of a different conductivity type than said second doped region; a first oxide layer proximate said third doped region; and a second oxide layer proximate said fourth doped region.