Patent ID: 6838903
Filing Date: 2005-01-04
Classification: H03K

Abstract:
1. Circuitry in a field programmable gate array wherein said field programmable gate array includes a logic block having a plurality of clusters wherein each of said plurality of clusters includes a plurality of logic devices wherein at least one of said plurality of logic devices has an input and an output, said circuitry comprising: a first set of plurality of interconnect conductors entering said logic block from a first side and forming a programmable intersection with said input and said output of said at least one of said plurality of logic devices in each of said plurality of clusters; a second set of plurality of interconnect conductors entering said logic block from a second direction and forming a first intersection with a set of at least one interconnect conductor of said first set of said plurality of interconnect conductors and forming a second intersection with a second set of a second at least one interconnect conductor of said first set of said plurality of interconnect conductors; and an interconnect conductor splitting extension disposed between said first intersection and said second intersection formed by said second set of said plurality of interconnect conductors.