Patent ID: 6173368
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A microprocessor for coupling to an external read/write memory having an addressable storage space for storing data including non-cacheable data, said microprocessor comprising:a non-cacheable data storage circuit for storing a portion of said data which comprises non-cacheable data recalled from the external read/write memory;a non-cacheable address storage circuit for storing an address corresponding to said non-cacheable data stored in said non-cacheable data storage circuit;a class storage circuit for storing a class identifier corresponding to said non-cacheable data stored in said non-cacheable data storage circuit;an input for receiving a class signal indicating a class for a corresponding subset of non-cacheable data;an input for receiving a terminate signal indicating expiration of a lifespan of non-cacheable data corresponding to said class signal;an indicator for indicating a lifespan of said non-cacheable data in said non-cacheable data storage circuit is expired in response to assertions of said terminate signal and said class signal matching said class identifier; anda control circuit connected to said non-cacheable address storage circuit, said non-cacheable address storage circuit, said indicator and a read address of a central processing unit for comparing said read address to said non-cacheable address and generating a hit signal permitting said central processing unit to read from said non-cacheable data storage circuit upon an address match if said indicator indicates said non-cacheable data in said non-cacheable data storage circuit is not expired.