Patent ID: 8112560
Filing Date: 2012-02-07
Classification: G06F

Abstract:
1. A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations, said plurality of data sources and data destinations communicating with said direct memory access controller via a plurality of channels, said direct memory access controller further communicating with a memory, and a processor which are external to said controller, said memory configured to store two sets of control data for each of said plurality of channels and for said processor, said direct memory access controller comprising: means for receiving a data transfer request from at least one of said plurality of channels and from said processor; means for accessing at least one set of corresponding control data stored in said memory; means for performing at least a portion of said data transfer requested in dependence upon said accessed control data; an indicator store for each of said plurality of channels and processor, said indicator store comprising an indicator bit indicating which of said two sets of control data is to be accessed, said direct memory access controller configured to toggle said indicator bit following completion of at least a portion of said data transfer controlled by said one set of control data; and a register, said register configured to store a base address relating to storage of said control data such that each set of control data is configured to be accessed in dependence upon said base address.