Patent ID: 6011718
Filing Date: 2000-01-04
Classification: G11C

Abstract:
An electrically erasable and programmable memory cell formed at a face of a semiconductor layer having a first conductivity type, comprising:a channel region of said semiconductor layer formed to be of said first conductivity type and adjoining said face, source and drain regions formed at said face to be of a second conductivity type opposite said first conductivity type, said channel region spacing said source region from said drain region;a conductive floating gate for controlling the conductance of said channel region, said floating gate insulatively spaced from said channel region by a first gate insulator layer; anda conductive control gate insulatively spaced from said floating gate by a second insulating layer, said second insulating layer being substantially thinner than said first insulating layer so as to permit Fowler-Nordheim tunneling of electrons from said control gate to said floating gate.