Patent ID: 6403468
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method for forming an embedded metal wiring comprising the steps in sequence of:patterning a dielectric film overlying a semiconductor substrate for forming a wiring trench having a first depth; forming a barrier metal film on said dielectric film, said barrier metal film having a thickness smaller than said first depth; forming a conductive metal film on said barrier metal film while filling said wiring trench with said conductive metal; CMP polishing said conductive metal film by use of a first polishing liquid including an oxidizing agent having a volume concentration of 1.4% or more with respect to said polishing liquid, wherein said conductive metal film is oxidized by said oxidizing agent to a more easily polished material, to expose said barrier metal film on a region other than said wiring trench; and CMP polishing said exposed barrier metal film by use of a second polishing liquid including an oxidizing agent having a volume concentration of 0.6 or less with respect to said polishing liquid to leave said barrier metal film and said conductive metal film in said wiring trench.