Patent ID: 6330591
Filing Date: 2001-12-11
Classification: G06F

Abstract:
A computer system, comprising:a first central processing unit (CPU) operably coupled to access a first cluster cache via a first cluster cache controller, wherein the first cluster cache is coupled to a first I/O subsystem through a path not including a first system bus coupled between the first CPU and the first cluster cache;a second central processing unit (CPU) operably coupled to access a second cluster cache via a second cluster cache controller, wherein the second cluster cache is coupled to a second I/O subsystem through a path not including a second system bus coupled between the second CPU and the second cluster cache;a differential serial line, adapted to transfer data between the first and second cluster cache controllers; anda directory, operably coupled to the first and second cluster cache controllers via the differential serial line, and providing information on whether a most recent version of data requested by either CPU is present in either cluster cache.