Patent ID: 8730747
Filing Date: 2014-05-20
Classification: G11C

Abstract:
1. A semiconductor device including a semiconductor memory circuit, which has a clock input terminal to which a clock signal is supplied and a first input terminal for communication to which a data signal is supplied, and a mode switching circuit comprising: a data comparison circuit which detects that data signals having phases that are reversed from each other have been supplied to the first input terminal and a second input terminal; a first decoder circuit which detects that a first data signal of the data signals has been received and outputs a detection signal in combination with a detection signal of the data comparison circuit; a second decoder circuit which detects that a second data signal of the data signals has been received and outputs a detection signal in combination with the detection signal of the data comparison circuit and the detection signal of the first decoder circuit; and a circuit which outputs a switching signal for shifting to a test mode upon receipt of the detection signals from the first decoder circuit and the second decoder circuit.