Patent ID: 6111801
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A method for testing wordline and related circuitry of a memory array, the memory array including a plurality of memory cells arranged in a plurality of rows, each of the plurality of rows having a respective wordline connected to respective ones of the plurality of memory cells, the related circuitry including a decode circuit connected to a first end of each of the respective wordlines for activating at least one of the respective wordlines based upon a corresponding address signal that is decoded by the decode circuit, the method comprising the steps of:applying an address signal to the decode circuit so as to activate a corresponding one of the respective wordlines; andmonitoring a second end of the corresponding one of the respective wordlines so as to determine if the corresponding one of the respective wordlines has been activated and thereby determine if the entire length of the corresponding one of the respective wordlines and the related circuitry are operating in a proper manner.