Patent ID: 7496779
Filing Date: 2009-02-24
Classification: G06F

Abstract:
1. A circuit for indicating the location of a leading edge of a bus clock, the circuit comprising: a clock ratio controller configured to generate a clock_ratio signal indicating the ratio of the frequency of a processor clock to the frequency of a bus clock and a valid_ratio signal indicating whether or not the clock_ratio signal is 1:1, the frequency of the processor clock being an integer multiple of the frequency of the bus clock; a previous edge detector for detecting a leading edge of a previous bus clock cycle, the previous edge detector configured to receive the valid_ratio signal, the bus clock, and the processor clock at a leaf of a clock tree, the previous edge detector further configured to generate a previous_edge signal according to the received valid_ratio signal, bus clock, and processor clock; combinational logic configured to receive the clock_ratio signal, the combinational logic further configured to generate a new_clock_count signal according to the received clock_ratio signal; a clock counter configured to receive the processor clock, the previous_edge signal, the valid_ratio signal, and the new_clock_count signal, the clock counter further configured to generate a clk_count signal according to the received processor clock, previous_edge signal, valid_ratio signal, and new_clock_count signal; and a flag generating circuit configured to process the clk_count signal and generate a clk_edge_flag signal indicative of the location of the leading edge of the next bus clock cycle.