Patent ID: 8396915
Filing Date: 2013-03-12
Classification: G06F,G06T

Abstract:
1. A processor comprising: a plurality of registers to store 64-bit packed data operands; a cache; a decoder coupled with the cache to decode a multiply and add instruction, the multiply and add instruction to have a 32-bit instruction format, the multiply and add instruction to have a first field to indicate a first register of the plurality of registers that is to store a first 64-bit packed data operand that is to have a first four signed 16-bit integer data elements A1, A2, A3, and A4, and the multiply and add instruction to have a second field to indicate a second register of the plurality of registers that is to store a second 64-bit packed data operand that is to have a second four signed 16-bit integer data elements B1, B2, B3, and B4; and an execution unit coupled with the decoder and the plurality of registers, the execution unit operable, in response to the multiply and add instruction, to store a 64-bit destination operand in a third register of the plurality of registers that is to be indicated by a third field of the multiply and add instruction, the 64-bit destination operand to include two 32-bit integer data elements, a first data element of the destination operand to include A1*B1+A2*B2, and a second data element of the destination operand to include A3*B3+A4*B4, wherein the processor comprises a general-purpose central processing unit (CPU), and wherein the processor has a reduced instruction set computing (RISC) architecture.