Patent ID: 6545506
Filing Date: 2003-04-08
Classification: H03K

Abstract:
A CMOS output circuit comprising:a. a pad terminal; b. a pull-up transistor having a source-to-drain path and a gate, the source-to-drain path of the pull up transistor at a first end to a power supply terminal and connected at a second end to a pad terminal; c. a pull-down transistor having a source-to-drain path and a gate, the source-to-drain path of pull-down transistor connected at a first end to a ground terminal, the gate of the pull-down transistor connected to a pull-down control signal; d. a pass transistor having a source-to-drain path and a gate, the source-to-drain path of pass transistor connected in series between the second end of the pull-up transistor and the second end of the pull-down transistor, the gate of the pass transistor connected to the power supply terminal; e. a floating well bias circuit comprising i. first, second, and third transistors each having a source-to-drain path and a gate, the source-to-drain paths of the first and second transistors being each connected at a first end to the power supply terminal, a second end of the source-to-drain paths of the first and second transistors, a first end of the source-to-drain path of the third transistor, and the wells of the first, and second, and third transistors each being connected to a floating well bias circuit output node coupled to the well of the pull-up transistor; ii. the gate of third transistor connected to the power supply terminal, and the gate of second transistor connected to the pad terminal; and iii. a second end of the source-to-drain path of the third transistor connected to the gate of the first transistor and the gate of pull-up transistor; f. a data-input inverter circuit comprising i. fourth transistor having a source-to-drain path and a gate, the source-to-drain path of the fourth transistor at a first end connected to a power supply terminal and connected at a second end to a data inverter output node; ii. fifth transistor having a source-to-drain path and a gate, the source-to-drain path of fifth transistor connected at a first end to ground terminal and connected at a second end to a data inverter output node; and iii, the gates of the fourth and fifth transistors being each connected to a positive data control signal; and g. a pull-up gate control circuit comprising i. sixth and seventh transistors each having a source-to-drain path and a gate, the source-to-drain paths of the sixth and seventh transistors being each connected at a first end to the power supply terminal, the gate of the sixth transistor connected to the positive data control signal; ii. eighth, ninth, tenth, and eleventh transistors each having a source-to-drain path and a gate, the source-to-drain paths of the eighth, ninth, tenth, and eleventh transistors being each connected at a first end to a pull-up gate control circuit output node, the gate of the eleventh transistor connected to the power supply terminal; iii. the source-to-drain path of the eighth transistor connected at a second end to the second end of the source-to-drain path of the sixth transistor; the source-to-drain paths of the seventh and tenth transistors being each connected at a second end to the gate of the ninth transistor, the gates of the seventh and tenth transistors being each connected to the data inverter output node coupled to the source-to-drain path of the eleventh transistor at a second end; iv. the source-to-drain path of the ninth transistor connected at a second end to the pad terminal coupled to the gate of the eighth transistor, the gate of the pull-up transistor connected to the pull-up gate control circuit output node; and v. the wells of sixth and eighth transistors each connected to the floating well bias circuit output node coupled to the well of the ninth transistor.