Patent ID: 6777143
Filing Date: 2004-08-17
Classification: G03F

Abstract:
A method to pattern a photoresist layer in the manufacture of an integrated circuit device wherein said integrated circuit device comprises a plurality of fields, said method comprising:depositing a photoresist layer overlying a wafer; loading a first mask and a second mask in a mask stage of an exposure apparatus wherein said mask stage maintains a fixed relative position between said first mask and said second mask; aligning said first mask and said second mask to said wafer; indexing said wafer such that said first mask overlies a starting said field; thereafter performing a first exposure pass on said wafer by repeatedly performing the steps of: scanning said field using said first mask; and stepping said wafer such that said first mask overlies a next said field yet unexposed by said first mask; â€ƒuntil all said fields in said wafer have been exposed by said first mask; thereafter indexing said wafer such that said second mask overlies said starting field; thereafter performing a second exposure pass on said wafer by repeatedly performing the steps of: scanning said field using said second mask; and stepping said wafer such that said second mask overlies a next said field yet unexposed by said second mask; â€ƒuntil all said fields in said wafer have been exposed by said second mask; and developing said photoresist layer to thereby complete said patterning in the manufacture of said integrated circuit device.