Patent ID: 9064596
Filing Date: 2015-06-23
Classification: G11C

Abstract:
1. A semiconductor device comprising: a shift register comprising a plurality of stages, each of the plurality of stages comprising a flipflop, wherein in each of the plurality of stages, the flipflop comprises a first memory circuit, a second memory circuit and a third memory circuit, wherein in each of the plurality of stages, the second memory circuit is configured to save data of the first memory circuit, write data of the first memory circuit to the third memory circuit and write data of the third memory circuit to the first memory circuit, wherein the third memory circuit of each of stages other than a last stage among the plurality of stages is configured to transfer the data to the third memory circuit of a next stage, and wherein in each of the plurality of stages, each of the second memory circuit and the third memory circuit is configured to hold data in a period during which power supply to the flipflop is stopped.