Patent ID: 6221747
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method of fabricating a conductive plug with a low junction resistance, comprising the steps of:preparing a semiconductor substrate at least comprising a conductive region;forming an insulating layer over the substrate;forming a contact opening at a specified location in the insulating layer to expose a part of the conductive region, wherein a native oxide layer is formed on the exposed conductive region;performing a preliminary doping process to dope a selected dopant into the native oxide layer through the contact opening so as to form a doped region in the exposed area of the substrate; andperforming a depositing process to deposit polysilicon into the contact opening, over the insulating layer, and over the doped native oxide layer to form the intended conductive plug, the deposition process being performed at a high-temperature that can cause the dopant atoms in the doped region to diffuse.