Patent ID: 7838982
Filing Date: 2010-11-23
Classification: H01L,H05K

Abstract:
1. A semiconductor package comprising: A multilayer wiring substrate formed with a plurality of insulating layers and a plurality of wiring layers alternately stacked each other where a portion of the outermost insulating layer is projected outwardly from the multilayer wiring substrate to form a projected bump; a first terminal formed with a metal layer on a first surface of the multilayer wiring substrate where the projected bump is not formed; and a second terminal formed with a metal layer that covers substantially the whole surface of the projected bump on a second surface defined by the outermost insulating layer; wherein a via hole is provided in the outermost insulating layer where the projected bump is formed extending the via hole to the metal layer of the second terminal; and a conductor via is formed within the via hole of the projected bump thereby electrically connecting the metal layer of the second terminal to the metal layer of the first terminal via the plurality of wiring layers; wherein the metal layer covering the surface of the projected bump is made of any selected one of the combinations of metals including, from the surface side, Au/Ni/Cu, Au/Pd/Ni/Cu and Au/Pd/Ni/Pd/Cu, thereby Cu of the metal layer is in contact with an insulating surface of projected bump and also is connected with the conductor via formed within the via hole of the projected bump.