Patent ID: 7263565
Filing Date: 2007-08-28
Classification: G06F

Abstract:
1. A bus system comprising: a bus to which a plurality of bus masters are each connected; and an address monitor unit including: a table which is shared among said plurality of bus masters and stores therein access right information that has been preset in correspondence to a subject-of-access and associated address information; a first decoder capable of decoding subject-of-access information received via said bus; a second decoder capable of decoding address information inputted via said bus; a detecting circuit capable of detecting the access right information specified by an output of said first decoder and an output of said second decoder; and a judging circuit capable of outputting judgment information on the presence or absence of the access right to said bus based on a detection output of said detecting circuit, wherein the address monitor unit is adapted to determine, by referencing said table, the presence or absence of an access right for each bus master based on the subject-of-access information and address information outputted from said bus master, and wherein said address monitor unit allows routing for transferring a packet which can be transferred via said bus to a target hardware item uniquely determined by a destination address of said packet.