Patent ID: 7173853
Filing Date: 2007-02-06
Classification: G11C,H01L

Abstract:
1. A memory system comprising: a first nonvolatile semiconductor memory and a second nonvolatile semiconductor memory each including a memory cell array containing a plurality of nonvolatile memory cells, each of the plurality of nonvolatile memory cells having a source region and a drain region disposed in a surface region of a semiconductor substrate in a mutually spaced-apart relationship, a gate insulating film extended on at least a channel region, a floating gate formed on the gate insulation film, an intermediate insulating film formed on the floating gate, and a control gate formed on the intermediate insulating film, and each of the plurality of nonvolatile memory cells being capable of setting one of a program state and an erase state by transferring an electric charge according to a tunnel mechanism between the surface region and the floating gate; a first data bus to which program data is provided from outside of the memory system; a first control bus to which a first program signal is provided from outside of the memory system; an interface part coupled to both the first control bus and the first data bus; a second data bus provided in common to the first and second nonvolatile semiconductor memories, and coupled to both the interface part and the first and second nonvolatile semiconductor memories, the second data bus being capable of transmitting transmission data, corresponding to the program data, from the interface part; and a second control bus coupled to the first and second nonvolatile semiconductor memories and to the interface part, the second control bus being capable of transmitting a second program signal corresponding to the first program signal, wherein the second program signal controls the first and second nonvolatile semiconductor memories in which the setting of the program state to a corresponding memory cell is performed by a program operation of programming data corresponding to the transmission data, and wherein the program operation of the first nonvolatile semiconductor memory is overlapped with at least one of (i) a receive operation of the second nonvolatile semiconductor memory, including receiving of the transmission data from the second data bus and (ii) the program operation of the second nonvolatile semiconductor memory.