Patent ID: 6136680
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method of forming an interconnect, comprising the steps of:providing a semiconductor structure having an exposed first metal contact;forming a dielectric layer having a predetermined thickness over said semiconductor structure;forming a fluorinated silica glass layer having a predetermined thickness over said dielectric layer;forming a trench within said fluorinated silica glass layer and said dielectric layer exposing said first metal contact, said trench having a predetermined width;forming a second metal layer filling said trench and blanket filling said fluorinated silica glass layer, said second metal layer having a predetermined thickness over said fluorinated silica glass layer;planarizing said second metal layer on said upper surface of said fluorinated silica glass layer, exposing said upper surface of said fluorinated silica glass layer and forming a planarized second metal filled trench;processing said fluorinated silica glass layer and said planarized second metal filled trench whereby any formed Si--OH bonds and second metal oxide are removed; andforming a dielectric cap layer having a predetermined thickness over said processed fluorinated silica glass layer and said planarized second metal filled trench.