Patent ID: 6748411
Filing Date: 2004-06-08
Classification: G06F

Abstract:
An adder comprising:a first adder for receiving as inputs a plurality of operands k in number, k being an integer at least three, and kâˆ’1 carry-in inputs, the first adder providing as outputs a sum that is the sum of the k operands and the kâˆ’1 carry-in inputs, and kâˆ’1 carry-out outputs; a plurality of 2kâˆ’1âˆ’1 carry-select adders, each of the carry-select adders receiving a plurality of operands k in number, each of the carry-select adders having kâˆ’1 predetermined carry-in inputs, each of the carry-select adders providing as outputs a sum that is the sum of the k operands and the respective predetermined carry-in inputs; a multiplexer for receiving as inputs the sum outputs from the carry-select adders, the multiplexer receiving a select input to select one of the inputs of the multiplexer as an output of the multiplexer; a code converter for receiving as inputs a mode select input and the kâˆ’1 carry-out outputs from the first adder, the code converter causing the first adder and the carry-select adders to operate as a split adder when the mode select input takes on a first state, and the code converter causing the first adder and the carry-select adders to operate as a hierarchical carry-select adder when the mode select input takes on a second state.