Patent ID: 9128864
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A memory controller that controls a non-volatile memory, comprising: an encoding unit that calculates a first parity from a first user data by a first error correction encoding process using a first generator polynomial, calculates a second parity from a second user data by the first error correction encoding process using the first generator polynomial, and calculates a third parity from the first user data, the first parity, the second user data, and the second parity by a second error correction encoding process using a second generator polynomial; a memory interface unit that controls the non-volatile memory to write the first user data, the first parity, the second user data, the second parity, and the third parity to the non-volatile memory; and a decoding unit that performs an error correction decoding process using the first user data, the first parity, the second user data, the second parity, and the third parity, wherein when a correcting capability of the first parity is A (A is an integer of 1 or larger) bits and a correcting capability of the third parity is B (B is an integer of 1 or larger) bits, the error correction decoding process that uses the first parity, the second parity, and the third parity has at least A+B bits of correcting capability for the first user data, the second user data, the first parity, the second parity, and the third parity.