Patent ID: 6812567
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A semiconductor package, comprising:a board having an upper surface, a lower surface and an aperture; a plurality of solder bump pads formed on the lower surface of the board; a plurality of board pads formed on the lower surface of the board; a plurality of distribution patterns for electrically connecting the solder bump pads to the board pads; a plurality of contact pads formed on the upper surface of the board, and electrically connected to the solder bump pads; at least one chip having a plurality of bonding pads, disposed in the aperture; a plurality of bonding wires electrically connecting the bonding pads to the board pads, at least one end of the bonding wires being bonded to the bonding pads or the board pads by wedge bonding; an encapsulation part provided on the lower surface of the board for encapsulating the at least one chip, the plurality of bonding wires and the plurality of board pads; and a plurality of solder bumps formed on the plurality of solder bump pads.