Patent ID: 6556497
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A refresh controller for use in a dynamic random access memory (â€œDRAMâ€ ) having a full density mode and a reduced density mode, the refresh controller comprising:an oscillator generating a first periodic clock signal; a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal; a first selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and to apply the second periodic clock signal to the output terminal in the reduced density mode; a counter having a clock input terminal coupled to the output terminal of the first selector circuit, the counter having first and second stages the first of which increments at a faster rate than the second; and a second selector circuit coupled the first and second stages of the counter, the second selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode.