Patent ID: 8854082
Filing Date: 2014-10-07
Classification: H03K

Abstract:
1. A deglitcher circuit comprising: a first multiplexer operable to receive an input signal and load a first value in a memory when said input signal is high, and load a second value in said memory when said input signal is low, wherein said loaded value is stored in said memory responsive to a clock signal; a first comparator operable to compare said stored memory value to an upper threshold value and output a first comparator signal; a second comparator operable to compare said stored memory value to a lower threshold value and output a second comparator signal; and a flip-flop operable to set when said first comparator signal is a first state and reset when said second comparator signal is a second state; wherein said first value is an incrementation of said stored memory value when said first comparator signal is a third state, and said second value is a decrementation of said stored memory value when said second comparator signal is a fourth state.