Patent ID: 7842568
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A method of manufacturing a lateral power semiconductor device, consisting of: providing a substrate; forming an oxide layer over the substrate for reducing minority carrier storage in the substrate; forming a silicon layer having a first conductivity type directly on the oxide layer; forming a well region having the first conductivity type in the silicon layer; forming a source region having a second conductivity type, drain region having the second conductivity type, gate region, and channel region having the first conductivity type in the well region, the channel region being disposed below the gate region between the source region and drain region; forming a first region having the first conductivity type on a surface of the lateral power semiconductor device adjacent to the source region, wherein a body diode is formed between the first region and drain region; and forming a second region having the first conductivity type in the well region below the source region and first region; wherein the oxide layer confines the minority carrier charge from the body diode to a depth of less than 20 micrometers from the surface of the lateral power semiconductor device.