Patent ID: 6072543
Filing Date: 2000-06-06
Classification: H04N

Abstract:
A priority order processing circuit for a Motion Picture Experts Group (MPEG) system comprising:a video buffer verifier writing controller for generating a writing request signal when a situation exists for storing data in an external memory;a video buffer verifier reading controller for generating a reading request signal when a situation exists for reading data stored in said external memory;a display controller for generating a display request signal in response to recovered data received therein;a motion compensation reading controller for generating a motion compensation reading request signal when motion compensation for the data stored in said external memory is requested;a motion compensation writing controller for generating a motion compensation writing request signal when storing motion compensated data in said external memory is requested; anda priority order controller for determining a priority order for the request signals generated by said video buffer verifier writing controller, said video buffer verifier reading controller, said display controller, said motion compensation reading controller and said motion compensation writing controller, and generating a service code for executing a data processing service based on the determined priority order.