Patent ID: 6425107
Filing Date: 2002-07-23
Classification: G06T,H03M

Abstract:
Encoding apparatus for converting a plurality of input values to a corresponding plurality of run length limited codes, wherein each of said input values comprises a plurality of bits, said encoding apparatus comprising:a map for mapping said plurality of input values into said corresponding plurality of run length limited codes, wherein each one of said corresponding plurality of run length limited codes is either DC balanced or imbalanced in the same direction by the same magnitude, said map being indexed by said plurality of input values and operative to produce a single one of said run length limited codes as a map output in response to the input of each one of said plurality of input values, wherein a single bit within a predetermined bit position of each one of said plurality of input values comprises a imbalance indicator bit having a first imbalance state or a second imbalance state, said run length limited codes being stored within said map such that each of said plurality of run length limited codes are imbalanced for input values having said imbalance indicator bit of said first imbalance state and balanced for input values having said imbalance indicator bit of said second imbalance state.