Patent ID: 7195963
Filing Date: 2007-03-27
Classification: H01L

Abstract:
1. A method of forming a transistor, the method comprising: forming a first layer including silicon carbon over a material including silicon germanium; forming a layer including silicon over the first layer including silicon carbon; forming a gate over the layer including silicon; forming a gate dielectric between the gate and the layer including silicon; and removing the material including silicon germanium below the gate after the forming the gate; filling a material in a location from which the material including silicon germanium was removed; forming a second recess in the material in the location; and epitaxially growing semiconductor material, wherein the epitaxially growing includes growing semiconductor material in the second recess; wherein the first layer including silicon carbon functions as a barrier to germanium diffusion from the material including silicon germanium to the gate dielectric; and wherein the transistor includes a source/drain region, wherein at least a portion of the source/drain region is located in the semiconductor material epitaxially grown.