Patent ID: 6799291
Filing Date: 2004-09-28
Classification: G11C

Abstract:
A method for detecting a failure in a dynamic random access memory (DRAM) array, wherein said memory array has a plurality of cells organized in a plurality of rows and columns, said method comprising:reading a content of a first row of cells during a first refresh cycle; saving said content of said first row of cells in a register; generating a first complement of said content and writing said first complement back to said first row of cells during a first refresh cycle write-back operation; setting a refresh flag bit in a refresh address counter; reading said first complement from said first row of cells during a subsequent refresh cycle and generating a second complement of said first complement; writing back said second complement to said first row of cells during said subsequent refresh cycle writeback operation; comparing said content of said first row of cells with said second complement; and generating a control signal, in response to said content not being equal to said second complement, to indicate a failed memory array.