Patent ID: 6515936
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A method of controlling the operation of a memory device which includes an array of memory cells and a system bus interface which includes a tag bus interface and a data bus interface, said method comprising the following steps:transferring a load control register command to the memory device over the tag bus interface together with control register data over the data bus interface; storing the control register data in a control register block of the memory device; transferring a memory address to the memory device over the data bus interface together with a memory address command over the tag bus interface; setting a magnitude of a program operation voltage based upon the control register data stored in the control register block; performing a memory operation on the memory array at a memory array address which corresponds to the memory address transferred over the data bus interface by application of the program operation voltage to the array, with the memory operation including a memory program operation and a memory read operation.