Patent ID: 6404254
Filing Date: 2002-06-11
Classification: H03K

Abstract:
A latch circuit in a semiconductor integrated circuit having an active mode and a standby mode, based on a first control signal, said latch circuit comprising:a first inverter circuit for receiving an input signal; a first conductivity type MOSFET having a first threshold and having a first terminal connected to a first power supply and a second terminal connected to said first inverter circuit; a second conductivity type MOSFET having a second threshold higher than said first threshold and having a first terminal connected to a second power supply having a lower voltage than said first power supply and a second terminal connected to said first inverter circuit; an information hold loop for receiving an output from said first inverter circuit and holding information in said standby mode, said information hold loop comprising second and third inverter circuits, each having a first power terminal connected to said first power supply and a second power terminal connected to said second power supply; and a control signal generating circuit for receiving a clock signal and said first control signal, and for outputting a second control signal which is input to said first conductivity type MOSFET and a third control signal which is input to said second conductivity type MOSFET, wherein a high level voltage amplitude of said first control signal is higher than high level voltage amplitudes of said first power supply and said second power supply, wherein said semiconductor integrated circuit is in active mode when said first control signal has a first voltage amplitude and is in standby mode when said first control signal has a second voltage amplitude which is different from said first voltage amplitude, and wherein in said active mode, said first control signal comprises a clock signal and in said standby mode, said first control signal comprises a signal for creating an information hold condition.