Patent ID: 7737561
Filing Date: 2010-06-15
Classification: B82Y,G03F,H01L

Abstract:
1. A microprocessor comprising: electrical interconnections having an RC delay comprising ultra low dielectric constant materials providing a circuit speed, said electrical interconnections comprise; a dual damascene interconnect structure, comprising: a patterned multilayer of dielectrics on a substrate, comprising: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over said first porous low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between said metal via and line conductors and said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric layer, and said second thin non-porous via level low-k dielectric layer, wherein said second thin non-porous via level low-k dielectric layer has a composition that is covalently bonded with said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric layer, and said etch stop layer.