Patent ID: 9129856
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A method for concurrently fabricating a memory region with a logic region on a common substrate, said method comprising: forming a lower dielectric segment in each of said memory and logic regions over said common substrate in a stacking direction; forming a polysilicon layer over said lower dielectric segment in said stacking direction in each of said memory and logic regions; etching said polysilicon layer to form a polysilicon segment in said memory region and a sacrificial polysilicon segment in said logic region; forming a first spacer in said logic region and a second spacer in said memory region, said first spacer being adjacent to said sacrificial polysilicon segment in a first direction that is perpendicular to said stacking direction, and said second spacer being adjacent to said polysilicon segment in said first direction; removing said lower dielectric segment and said sacrificial polysilicon segment from said logic region; forming a first high-k segment in said logic region over said common substrate in said stacking direction and adjacent to said first spacer in said first direction; forming a second high-k segment in said memory region over said polysilicon segment in said stacking direction and adjacent to said second spacer in said first direction; forming a first metal segment over said first high-k segment in said logic region in said stacking direction; and forming a second metal segment over said second high-k segment in said memory region in said stacking direction.