Patent ID: 6452230
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A high voltage MOSgated device of low on-resistance comprising, in combination; a thin flat chip of silicon having a main body layer of one conductivity type and having relatively high concentration and a junction-receiving layer of said one conductivity type and of a relatively lower concentration disposed atop said main body layer; a plurality of spaced base diffusions of the other conductivity type formed in the upper surface of said junction receiving layer and a plurality of source regions of said one conductivity type formed in respective ones of said base diffusions to define invertable channel regions laterally spaced from one another by a vertical conduction channel region in said junction receiving layer; and a MOSgate structure disposed above each of said invertible channels and responsive to a suitable MOSgate input signal; a plurality of spaced thin trenches extending vertically from the top of said junction receiving layer for at least a major portion of the thickness of said junction receiving layer; a first main contact disposed above the top surface of said junction receiving layer and in contact with said source and base diffusions and said trenches; a second main contact formed on the bottom of said main body layer; said trenches defining between them vertical depletable vertical conduction regions in said junction receiving layer for the length of said trenches; each of said trenches being filled with a semi-insulating, non-injecting material which is relatively incapable of carrier injection into the junction receiving layer.