Patent ID: 6545507
Filing Date: 2003-04-08
Classification: H03L,H04L

Abstract:
A system for producing recovered clock and data signals for serial data communications operations, comprising:a 1st logic system operable to receive a decoded single ended serial data stream, and a plurality of clock phases, which are evenly spaced and offset between successive phases derived from the local clock signal, wherein the 1st logic system is configured to detect whether a transition of the data stream took place corresponding with one of the plurality of clock phases and independent of an event caused by metastability, to generate one of a corresponding plurality of data transition detections based upon the serial data stream, and the plurality of clock phases; a 2nd logic system operable to receive a plurality of data transition detections, a plurality of clock phases, and a plurality of previous clock phase selections, to determine which phases corresponded to a data stream transition, to compare the new data transition to a last phase selection transition, and to generate a plurality of phase determinations based upon the comparisons; a 3rd logic system operable to receive the plurality of phase determinations, to apply amplification, hysteresis and feedback, and to generate a plurality of processed phase selections based upon the plurality of phase determinations, and an elimination of metastable conditions and multiple phase selections; and a phase selection logic operable receive the plurality of clock phase signals, and to receive and to use the plurality of processed phase selections to make a best phase selection which is used to securely latch and recover the clock and data signals, whereby the recovered clock and data signals are free of metastable conditions and multiple phase selections, and independent of jitter and wander.