Patent ID: 7225306
Filing Date: 2007-05-29
Classification: H03M

Abstract:
1. A method of generating an address sequence, the method comprising: decomposing a Forney's (P,D,m) interleaver with delays f(i)=(im mod P)D, 0≦i<P, into a concatenation of a multiplexed interleaver with period P and delays f generating A+1 multiplexed interleaver addresses, wherein A is the average delay of the (P,D,m) interleaver and equals (P−1)D/2; generating 2P block interleaver addresses; generating at least one two-dimensional address array from the multiplexed interleaver addresses and the block interleaver addresse; and controlling read and write addresses associated with a sole RAM in response to the at least one two-dimensional address array such that symbols are written into and read from the sole RAM according to a periodic sequence defined by the two-dimensional address array.