Patent ID: 7489581
Filing Date: 2009-02-10
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines corresponding to the rows of memory cells, each of the word lines being connected to memory cells of a corresponding one of the rows; a plurality of bit line pairs corresponding to the columns of memory cells, each of the bit line pairs being connected to memory cells of a corresponding one of the columns; a plurality of high-data retaining supply line pairs corresponding to the columns of memory cells; a plurality of write circuits each of which drives a corresponding one of bit lines of the plurality of bit line pairs; and a plurality of high-data retaining supply circuits each connected to a corresponding one of high-data retaining supply lines of the plurality of high-data retaining supply line pairs, wherein each of the plurality of memory cells include a selected one of the high-data retaining supply circuits receives a signal determined according to an input data signal and address signal without the intervention of any of the bit lines which constitute the bit line pairs to drive one of the high-data retaining supply lines connected to the selected high-data retaining supply circuit such that the driven high-data retaining supply line has a potential corresponding to the received signal.