Patent ID: 6873053
Filing Date: 2005-03-29
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a gate oxide film provided over the semiconductor substrate; a gate electrode formed on the gate oxide film; a source/drain region formed in the semiconductor substrate and disposed adjacent to the gate electrode; a lower layer wiring connected to the source/drain region with contact; an interlayer insulating film covering the lower layer wiring; a via hole formed in an interlayer insulating film; and an upper layer wiring, disposed over the interlayer insulating film and connected to the lower layer wiring through the via hole, wherein the upper layer wiring and the lower layer wiring are arranged directly under a pad portion and in areas other than under the pad portion, and wherein no hole connecting the upper layer wiring and the lower layer wiring is formed directly under the pad portion.