Patent ID: 6041014
Filing Date: 2000-03-21
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a nonvolatile memory cell;a word line connected to said nonvolatile memory cell;a decoder to which an address signal is input;a word line driver having a first node, a second node, an output node, a first P-channel transistor and a first N-channel transistor, a first terminal of said first P-channel transistor being connected to said first node, a second terminal of said first P-channel transistor being connected to said output node, a substrate terminal of said first P-channel transistor being connected to said first node, a substrate terminal of said first N-channel transistor being connected to said second node, and said output node supplying a first predetermined potential to said word line;a second N-channel transistor having a gate terminal to which a second predetermined potential is applied, a first terminal of said second N-channel transistor being connected to said decoder and a second terminal of said second N-channel transistor being connected to a gate terminal of said first P-channel transistor; anda second P-channel transistor having a gate terminal connected to which a predetermined signal is applied, a first terminal of said second P-channel transistor being connected to a gate terminal of said first P channel transistor, a second terminal of said second P-channel transistor being connected to a substrate terminal of said second P-channel transistor,wherein in an erase mode a negative potential is applied to said second node of said word line driver, and a voltage greater than the negative potential is applied to both said first node of said word line driver and the second terminal of said second P-channel transistor.