Patent ID: 6631012
Filing Date: 2003-10-07
Classification: G06K

Abstract:
A method for generating and outputting a bitstream corresponding to a 2D-barcode having I first sequences of modules and J second sequences of said modules substantially orthogonal to said first sequences, each of said modules having a one-to-one correspondence with a bit in a binary data array and comprising X first sequences of pixels substantially parallel to said first sequences of said modules and Y second sequences of said pixels substantially parallel to said second sequences of said modules, said method comprising the steps of:a) generating a bit map corresponding to an initial first sequence of said modules and comprising binary pixel values P(x,y), where for each module in said initial first sequence; a1) all P(x,y) equal 0 if said corresponding data bits are not asserted; and otherwise a2) for first pixel sequences P(1) through P(Xâˆ’H), where H is in the range 0 to Xâˆ’1, all P(x,y), equal 1; a3) for first pixel sequences P(Xâˆ’H+1) through P(X), all P(x,y) in second pixel sequences P(1) through P(Yâˆ’V), where V is in the range 0 to Yâˆ’1, equal 1 if a corresponding data bit for an adjacent module in a next first sequence equals 1, and otherwise equal 0; and a4) for first pixel sequences P(Xâˆ’H+1) through P(X), all P(x,y) in second pixel sequences P(Yâˆ’V+1) through P(Y) equal 0 if said corresponding data bit for an adjacent module in said next first sequence equals 0, or if said corresponding data bit for a diagonally adjacent module in said next first sequence equals 0; and b) outputting said bit map as a bitstream by: b1) for each module in said initial first module sequence setting all P(x,y) in said second pixel sequences P(Yâˆ’V+1) through P(Y)=0 if a data bit corresponding to a next module in said initial first sequence=0; b2) for each module in said initial first module sequence outputting an initial first pixel sequence; b3) repeating step b2 for each remaining first pixel sequence; and c) repeating steps a and b for each remaining first module sequence; where d) H and V are not both equal to 0.