Patent ID: 6798015
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns,wherein each of the nonvolatile memory devices includes: a word gate formed over a semiconductor layer with a gate insulating layer interposed in between; an impurity layer formed in the semiconductor layer to form one of a source region and a drain region; and control gates in the shape of sidewalls formed along both side surfaces of the word gate, wherein each of the control gates includes a first control gate and a second control gate adjacent to each other, wherein a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film is disposed between the first control gate and the semiconductor layer, and a side insulating layer is disposed between the first control gate and the word gate; wherein a second insulating layer formed of a silicon oxide film is disposed between the second control gate and the semiconductor layer, and wherein the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.