Patent ID: 6016284
Filing Date: 2000-01-18
Classification: G11C

Abstract:
An address transition detector for a memory device, comprising:a detection circuit for detecting a change in an address signal which specifies an address of one of a plurality of memory cells and producing a detection signal;a first logic gate having a first input terminal and a second input terminal and an output terminal;a transistor having a gate which receives the detection signal from said detection circuit and terminals connected to a given potential and the first input terminal of said first logic gate, respectively;an inverter having an input terminal connected to the output terminal of said first logic gate and an output terminal connected to the first input terminal of said first logic gate;a first delay circuit connected to the output terminal of the first logic gate for delaying a rising edge of a signal output from the output terminal of the first logic gate; anda second delay circuit connected to said first delay circuit for delaying a falling edge of the delayed signal from said first delay circuit and for delivering a shaped signal to the second input terminal of said the first logic gate.