Patent ID: 6771547
Filing Date: 2004-08-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of data-erasable memory cells including drain and source regions and gate electrodes, for storing data, said plurality of data-erasable memory cells being formed in a well region; a first voltage output circuit supplied with a first voltage, for outputting a second voltage obtained by boosting the first voltage; a second voltage output circuit coupled with the first voltage output circuit, for generating a third voltage whose voltage value is smaller than a value of the second voltage at a data program time; a row decoder circuit coupled with the second voltage output circuit, for supplying the third voltage to a selected one or the gate electrodes at a data program time; and a first switch circuit coupled with the first voltage output circuit, for supplying the second voltage to the well region at a data erase time.