Patent ID: 8627243
Filing Date: 2014-01-07
Classification: G01B,G01N,G06F,G16Z,H01L

Abstract:
1. A method, comprising: receiving layout data for an IC design to be manufactured on a semiconductor wafer with patterned conductors formed in an electrochemical plating (ECP) process; extracting layout data from the received layout data corresponding to at least one metal layer; determining from the extracted layout data a layout effects factor for each of a plurality of unit grid areas covering the semiconductor wafer, the layout effects factor corresponding to one selected from a line edge density and a pattern density for the at least one metal layer in the unit grid area; determining from the extracted layout data a global effects factor corresponding to a global pattern density for the at least one metal layer over a total area of the semiconductor wafer; determining from the extracted layout data a local effects factor for each of the unit grid areas, the local effects factor corresponding to a local pattern density for the at least one metal layer over an area of the semiconductor wafer within a local grid area larger than, and surrounding, the corresponding unit grid area; using a computing device, performing an ECP simulation configured to predict post-ECP plating hump heights in the at least one metal layer for each one of the unit grid areas, the ECP simulation using at least one of the global effects factor and the local effects factor as inputs, and using the layout effects factor as an input; and outputting a predicted post-ECP hump data map for the semiconductor wafer from the ECP simulation.