Patent ID: 8464117
Filing Date: 2013-06-11
Classification: G01R

Abstract:
1. In an integrated circuit having a plurality of clock domains, a system for generating a plurality of time staggered internal clock signals for scan testing the integrated circuit, the system comprising: one or more registers clocked by a single test clock signal, wherein the one or more registers are loaded with one or more codewords, and wherein the number of the registers equals two to the power of the number of the clock domains; a decoder, connected to the one or more registers, for providing one or more clock gate control signals, wherein the one or more clock gate control signals are based on one or more data bits of the one or more code words; and a plurality of clock gating cells connected to the decoder, for providing the plurality of time-staggered internal clock signals, wherein each clock gating cell operates based on a respective one of the clock gate control signals, and wherein each clock gating cell receives the single test clock signal.