Patent ID: 8443328
Filing Date: 2013-05-14
Classification: G06F

Abstract:
1. A method for recursive hierarchical static timing analysis, comprising: accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form by using a computer system; accessing constraints for the lower-level block; performing static timing analysis on the lower-level block; accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form; accessing constraints for the upper-level block; performing static timing analysis on the upper-level block while incorporating results from the static timing analysis on the lower-level block; performing recursive static timing analysis on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block; performing design rule checking in conjunction with static timing analysis on both the lower-level block and the upper-level block; and reporting violations of design rule checking criteria or static timing analysis criteria for both the lower-level block and the upper-level block.