Patent ID: 6701425
Filing Date: 2004-03-02
Classification: G06F

Abstract:
A computer system having a memory the memory including two separately accessible memory banks, each bank storing half a word at each word address, a plurality of parallel execution pipelines and a memory access controller, said access controller providing a plurality of queues including store address queues holding addresses for store operations to be effected in the memory, store data queues holding a plurality of data for storing in the memory at locations identified by the store address queues, and load address storage holding addresses for load operations to be effected from the memory, said access controller, including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits that indicate which byte positions at each word address are to be accessed and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits, the comparator further comprising a plurality of comparator devices, two of which effect comparison of addresses in respective memory banks, each of said two comparator devices having first inputs for comparing the bank word addresses for a pair of load and store addresses and second inputs for comparing respective byte enable bits of a pair of load and store addresses.