Patent ID: 7003650
Filing Date: 2006-02-21
Classification: G06F

Abstract:
1. A method of resolving an output dependence problem with regard to the requirement to ensure a precise exception in an explicit parallelism architecture processor comprising a set of different latency executive units, a register file with a set of write ports to write the results of the operations execution and a bypass to transfer the results of the operations execution to the following operations as operands before the real write into the register file, the method comprising: ensuring a correct write order of the operations results into the register file with a WAW hazard available by: aligning the execution time of a set of short latency instructions to the longest latency from the set and writing their results into the register file only after checking for the absence of precise exception, which restores the issue order of results write into the register file of said instructions and makes it possible to implement precise exception for this type of instructions; canceling the write into the register file for long and undefined latency type operations, which are already being executed in the executive units, and which addresses of the result write into the register file coincide with the write addresses of operations coming to the executive units, in this case the write inhibition is performed only after checking for the absence of precise exception in the operations coming to the executive units is finished; ensuring a correct use through the bypass of the results of operations in the following operations as operands with the WAW hazard available by: inhibiting the issue through the bypass of the results of all operations, which are already being executed in the executive units, which write addresses into the register file coincide with the write addresses of operations coming to the executive units, in this case the inhibition is performed as soon as the operations with the same result addresses come to the executive units; ensuring access through the bypass to the results of the short latency operations in all additional stages introduced to align the execution time.