Patent ID: 7512572
Filing Date: 2009-03-31
Classification: G11C

Abstract:
1. A memory configuration for use in a computer system, the memory comprising: a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; and wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; and wherein each address decoder identifier has an equal number of bits set to the first selectable state and the means to receive an input address is configured to receive addresses containing a predetermined number of bits set to the first selectable state.