Patent ID: 7042260
Filing Date: 2006-05-09
Classification: G06F,G11C,H03L

Abstract:
1. A phase-lock loop generating an output clock signal responsive to an input clock signal, comprising: a phase detector having a first input receiving the input clock signal and a second input receiving the output clock signal, the phase detector generating a phase error signal at an output that is indicative of a relationship between the phase of the input clock signal and the phase of the output clock signal; a voltage controlled ring oscillator having an input coupled to the output of the phase detector, the voltage controlled oscillator generating a clock signal at an output that has a frequency corresponding to the phase error signal, the ring oscillator comprising a plurality of delay elements that are coupled to each other in a ring in an unstable relationship, each of the delay elements having a respective delay control terminal that controls the signal propagation delay through the delay element, the delay control terminal of each of the delay elements being coupled to the output of the phase detector so that the signal propagation delay of each of the delay elements corresponds to the phase error signal, each of the delay elements generating a respective phase of the clock signal generated by the voltage controlled oscillator; and a frequency multiplier having an input coupled to receive the clock signal from the output of the voltage controlled oscillator, the frequency multiplier generating the output clock signal at an output having a frequency that is a multiple of the frequency of the clock signal received from the output of the voltage controlled oscillator, the output of the frequency multiplier being coupled to the second input of the phase detector, the frequency multiplier comprising a clock serializer coupled to receive each of the phases of the clock signal from the respective delay elements, the clock serializer being operable to transition the output clock signal on each transition of any of the phases of the clock signal from the respective delay elements.