Patent ID: 8145963
Filing Date: 2012-03-27
Classification: G01R

Abstract:
1. A semiconductor integrated circuit device, comprising: a first clock domain in which a plurality of first flip-flops are provided on a data path, and which is configured to operate with a first clock; a second clock domain in which a plurality of second flip-flops are provided on a data path, and which is configured to operate with a second clock of a lower frequency than a frequency of the first clock; a first test clock supplying section configured to supply a test clock based on the first clock to all of the first flip-flops at a time of a delay fault test; and a second test clock supplying section configured to supply, at the time of the delay fault test, a test clock based on the first clock to a third flip-flop to which data from the first clock domain is input among the plurality of second flip-flops, and not to supply the test clock to a plurality of fourth flip-flops excluding the third flip-flop among the plurality of second flip-flops.