Patent ID: 9158539
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A microprocessor, comprising: a multiply unit; at least one general-purpose-register arranged to store and provide a number of destination bits to said multiply unit; a control unit adapted to provide at least a multiply-high instruction and a multiply-high-and-accumulate instruction to said multiply unit wherein said multiply unit further is wherein said multiply-high-and-accumulate operation comprises generating said result operand using a sum of an intermediate result operand generated from a multiply-high operation using said at least first and second source operands and a concatenation of a preceding destination portion previously stored in said at least one general-purpose-register and a corresponding preceding precision-enhancement portion previously stored in said at least one cache entry, the microprocessor further comprising a plurality of general-purpose-registers, each having a register identifier, wherein said control unit is adapted to provide a destination identifier matching one of said register identifiers to said multiply unit, said multiply unit adapted to store said destination portion in said general-purpose-register identified by said destination identifier, wherein said register-extension cache comprises a plurality of said cache entries, each identified using a cache entry identifier corresponding to one of said register identifiers and wherein said multiply unit is adapted to generate said result operand using said destination portion and a precision enhancement portion provided by a cache entry having said cache entry identifier matching said destination identifier.