Patent ID: 7266791
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A high level synthesis device, comprising: a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level at an arbitrary clock cycle, with a general-purpose programming language, wherein the cycle accurate model generation section generates the cycle accurate model based on (i) operation information on the plurality of components, (ii) connection information which represents at least one of a connection between a component and another component among the plurality of components and a connection between one of the plurality of components and the controller, and (iii) controller information which represents a state transition of the controller, and the cycle accurate model generation section generates component state calculation expressions for calculating states of the plurality of components and a controller state calculation expression for calculating a state of the controller with the general-purpose programming language based on the operation information, the connection information, and the controller information.