Patent ID: 8922007
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a circuit substrate including a substrate pad; a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad; and a connection pattern electrically connecting the circuit substrate with the semiconductor chip, wherein the semiconductor chip comprises a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip, at least one first via electrically connecting the chip pad to the first circuit patterns, a second circuit pattern disposed parallel to the top surface of the semiconductor chip, and a second via connected to the second region of the chip pad to electrically connect the second circuit pattern to the chip pad, and wherein each of the first circuit patterns and the second circuit pattern are physically separated from each other, and wherein the chip pad comprises a first region in contact with the connection pattern and a second region arranged outside the first region, and the first via is connected to the second region of the chip pad.