Patent ID: 6429480
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A semiconductor device in which nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate, comprising:(a) a first conductive layer which is formed on said semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape; (b) a first interlevel insulating film which is formed on said semiconductor substrate so as to cover said field effect transistor, and has a first opening for exposing a surface of said first conductive layer; (c) a second conductive layer which is formed on said first conductive layer inside the first opening, and patterned into a predetermined shape; (d) a control gate electrode of said nonvolatile memory cell which is formed on said second conductive layer via an internal insulating film patterned into a predetermined shape; and (e) an interconnection layer electrically connected to a source/drain region of said field effect transistor via a contact hole formed in said first interlevel insulating film; wherein said first and second conductive layers constitute said floating gate electrode, and said first conductive layer has a planar shape which can be patterned at the same time as a gate electrode of said field effect transistor; and wherein said semiconductor device further comprises a second interlevel insulating film which has a trench communicating with the contact hole and is formed on said first interlevel insulating film, said second interlevel insulating film has a second opening for exposing a surface of said internal insulating film, said control gate electrode is buried in the second opening, and said interconnection layer is buried in the trench.