Patent ID: 6521969
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; electrical active device regions formed in the semiconductor substrate; and an isolating region made of a trench-type isolating oxide film, of which surface is abraded by a CMP method, wherein: a plurality of types of dummy patterns having various areas, including first dummy patterns having relatively small areas of the same size and second dummy patterns having relatively large areas of a size larger than the size of the relatively small areas, being active regions of a dummy surrounded by the trench-type isolating oxide film patterns, are located in the isolating region so that the trench-type isolating oxide film pattern does not exceed a predetermined width; the dummy patterns are regularly arranged by setting an area in response to a positional relationship between the dummy patterns and patterns of the electrical active device regions; the first dummy patterns having relatively small areas are arranged around the entire periphery of at least one of the electrical active device patterns; and the second dummy patterns having the relatively large areas are arranged around the first dummy patterns having the relatively small areas.