Patent ID: 8041881
Filing Date: 2011-10-18
Classification: G06F,G11C,Y02D

Abstract:
1. A memory apparatus for use with a host system, the memory apparatus comprising: a plurality of memory circuits; one or more first components of a first type, each of the one or more first components being electrically couplable to the host system; and one or more second components of a second type different from the first type, each of the one or more second components being electrically couplable to the host system, the first and second components being operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one of the plurality of memory circuits, wherein each memory circuit of the plurality of memory circuits is electrically coupled to at least one of the one or more first components of the first type and to at least one of the one or more second components of the second type, where the one or more first components and the one or more second components are further operable to identify at least one of the plurality of memory circuits that is not being accessed and to perform a power-saving operation on the at least one of the plurality of memory circuits identified as not being accessed.