Patent ID: 8378483
Filing Date: 2013-02-19
Classification: H01L

Abstract:
1. A fabrication process of a multi-chip package comprising the steps of: providing an incomplete substrate and a substrate block, wherein one sidewall of the incomplete substrate has a first spliced portion and one sidewall of the substrate block has a second spliced portion, and the dimension of the incomplete substrate is larger than the one of the substrate block; disposing at least a memory chip on the incomplete substrate; disposing a controller chip on the substrate block; fitting the substrate block in the incomplete substrate as a complete substrate by connecting the second spliced portion of the substrate block with the first spliced portion of the incomplete substrate after the disposition of the memory chip on the incomplete substrate and after the disposition of the controller chip on the substrate block; and forming an encapsulant on the incomplete substrate, wherein the encapsulant is further formed on the substrate block to encapsulate the memory chip and the controller chip together.