Patent ID: 6427194
Filing Date: 2002-07-30
Classification: G06F,G06T,G09G,H04N

Abstract:
A portion of an electronic system for coupling to a memory and a display device, the portion of the electronic system comprising:a first bus communicatively linked to the memory to allow access for the display device, subject to a display device access control, through the first bus to the memory without also requiring a second bus to access the memory; a decoder communicatively linked to the first bus for receiving compressed images and displaying decoded images on the display device and to access the memory, subject to a decoder access control, through the first bus without also requiring a second bus to access the memory, the memory storing at least one previously decoded image used to decode a current image, the memory being a region of a main memory of the electronic system; and an arbiter wherein the arbiter is communicatively linked to the display device for the display device access control, the arbiter communicatively linked to the decoder for the decoder access control, the arbiter configured to control access to the memory for the display device and the decoder.