Patent ID: 8854101
Filing Date: 2014-10-07
Classification: G06F,H03K,H03L

Abstract:
1. An adaptive clock generating apparatus comprising: a fixed frequency divider that receives a reference clock, and outputs a clock signal having a period corresponding to an integer multiple of the period of the reference clock; a replica that receives the clock signal output by the fixed frequency divider, and outputs a clock signal that is delayed as long as critical path delay of a synchronous circuit; a counter that receives an enable signal and a reset signal, which are generated based on the signals output by the fixed frequency divider and the replica, further receives the reference clock as its clock signal, and counts the number of cycles of the reference clock while the counter is enabled; and a variable frequency divider that, based on the number of cycles of the reference clock, generates a clock signal having a period corresponding to an integer multiple of the number of cycles of the reference clock, the integer being greater by 1 than the number of cycles of the reference clock, wherein the adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of the synchronous circuit.