Patent ID: 6721223
Filing Date: 2004-04-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array having a plurality of memory cells; refresh circuitry for refreshing storage data of a memory cell in said memory array; a register circuit for storing data setting at least one of a refresh period and a refresh region of said memory array, said register circuit storing externally applied refresh specifying data in response to an externally applied register set instruction signal; and refresh execution control circuitry for generating, in refresh execution, a refresh address specifying a memory cell to be refreshed in said memory array, and supplying said refresh address to and activating said refresh circuitry, according to data stored in said register circuit, wherein said refresh specifying data comprises region specifying data specifying a refresh target region of said memory array to be refreshed, and said refresh execution control circuitry includes: a counter for generating a counter address in a refresh operation mode of performing the refresh; and a circuit for modifying the counter address in accordance with the region specifying data to change the counter address into an address in said refresh target region to generate said refresh address.