Patent ID: 6647511
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A reconfigurable datapath operable to alternatively perform various debug functions, comprising:a first set of register bitcells that form a reference register bitcell unit; a second set of register bitcells that form a mask register bitcell unit; wherein each of said register bitcells has a half adder, a register input multiplexer for selecting between a number of inputs, at least one said input being a counter input from said half adder and at least one input being a write input, and a flip flop for storing a selected one of said inputs, and wherein said half adder receives a carry chain input and the output of said flip-flop; and a set of comparator bitcells that form a comparator bitcell unit, each of said comparator bitcells having NOR logic for receiving a bus input and a mask input, and XOR logic that receives the output of said NOR gate and a signal from said reference register unit and provides a compare result signal.