Patent ID: 7824969
Filing Date: 2010-11-02
Classification: B82Y,H01L

Abstract:
1. A method of forming a tunneling fin field effect transistor comprising: disposing a pad oxide layer and a silicon nitride mask layer on a silicon on insulator layer; the silicon on insulator layer comprising a silicon wafer, a buried oxide layer and a silicon on insulator layer; the silicon on insulator layer comprising a P+ type or N+ type doped silicon on insulator; etching a fin; the fin comprising the silicon on insulator layer, the pad oxide layer and the silicon nitride mask layer; disposing a high dielectric constant layer and an electrically conducting layer on the fin; reactively ion etching the electrically conducting layer to form a gate electrode; disposing an oxide offset spacer on the gate electrode; ion implanting a N+ dopant or a P+ dopant in the fin; the ion implanting being conducted at an angle of about 45 to about 80 degrees, with respect to a longitudinal axis of the wafer; the ion implanting creating a source region and a drain region in the fin; the ion implanting also creating a N-doped or a P-doped region in the gate electrode; disposing a nitride spacer on the gate electrode; and disposing a nickel silicide layer on the wafer to form an electrical short between N+ and P+ doped regions; and forming a tunneling device on the buried oxide layer; the tunneling device comprising an N+ doped region and the P+ type doped silicon on insulator.