Patent ID: 8817914
Filing Date: 2014-08-26
Classification: G11C,H03K

Abstract:
1. A receiver circuit, comprising: a receiving stage coupled to a first supply voltage and an input signal, operative to generate a first intermediate signal from the input signal based on the first supply voltage; a compensation stage coupled to a second supply voltage and the first intermediate signal, operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage; and an outputting stage coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal, wherein a voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle, wherein the compensation stage comprises: wherein the detection circuit comprises: wherein the increment/decrement detection circuit comprises: wherein the ADC comprises: