Patent ID: 8064262
Filing Date: 2011-11-22
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first data storage region comprising a non-volatile main data storage region; a second data storage region comprising a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region, wherein the non-volatile reference region comprises a first memory cell and a second memory cell that are both connected to a word line, the first memory cell stores a first logic value and has a first threshold voltage setting, the second memory cell stores a second logic value and has a second threshold voltage setting that is less than the first threshold voltage setting, a reference voltage value is determined between the first and second threshold voltage settings; and a control unit coupled to the first and second data storage regions, wherein every time the control unit erases collectively data stored in the first and second data storage regions, the control unit determines a stress information related to the second data storage region by writing data to the second data storage region, next the control unit determines a stress condition corresponding to the first data storage region based on the stress information, and next the control unit uses the stress condition to verify a threshold voltage of the first data storage region.