Patent ID: 6501119
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A semiconductor memory device comprising a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor, comprising:a substrate, a transistor formed on said substrate, a first insulating film formed on said substrate covering said transistor, a storage node contact hole formed in said first insulating film and reaching a source and drain region of said transistor, a storage node contact plug buried in said storage node contact hole, a storage node electrode formed connected to said storage node contact plug, a second insulating film formed above said first insulating film in the gap portion of said storage node electrodes, a capacitor insulating film formed above said storage node electrode, and a plate electrode formed above said capacitor insulating film, said storage node electrode and said storage node contact plug being formed connected at least at part of the top surface and side surface of said storage node contact plug, and said storage node electrode and said second insulating film being formed in contact at least at part of the top surface and the side surface of said second insulating film.