Patent ID: 6388486
Filing Date: 2002-05-14
Classification: H03K

Abstract:
An output signal pad cell driver circuit of an integrated circuit for controlling the slew rate of a digital logic output signal delivered from an output pad of the integrated circuit in relation to a load connected to the output pad, the output signal occurring in response to an input digital logic signal to said driver circuit, said driver circuit comprises:a first timing circuit for generating a first predetermined plurality of first trigger signals which occur in a first sequence at sequentially spaced time intervals with respect to one another; a second timing circuit for generating a second predetermined plurality of second trigger signals which occur in a second sequence at sequentially spaced time intervals with respect to one another in the first and second sequences, respectively; the first and second predetermined pluralities of trigger signals being equal in number; the first trigger signals of the first sequence and the second trigger signals of the second sequence correlating to one another; the time intervals between the first trigger signals in the first sequence being different from the time intervals between the second trigger signals in the second sequence; the first timing circuit responds to the input signal to initiate the generation of the first plurality of first trigger signals; the second timing circuit responds to the output signal under influence of the load connected to the output pad to initiate the generation of the second plurality of second trigger signals; a plurality of logic gates, the plurality of logic gates equal in number to the number of first and second trigger signals in the first and second sequences, respectively; each logic gate receiving the correlated first and second trigger signals and supplying a selected one of the correlated first and second trigger signals which occupies a predetermined temporal relationship to the other trigger signal received at each logic gate; and a switching circuit comprising a plurality of drive switches connected to the output pad, each drive switch connected to a different logic gate to receive the selected one of the first and second trigger signals, the selected one of the trigger signals applied from each logic gate controlling the conductivity of each drive switch to establish the slew rate of the output signal.