Patent ID: 7064040
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method of fabricating a static random access memory (SRAM), comprising steps of: (a) forming a gate electrode of an n-channel MISFET over an element forming region of a first semiconductor region of p-type conductivity formed in a semiconductor body, and a gate electrode of a p-channel MISFET over an element forming region of a second semiconductor region of n-type conductivity formed in said semiconductor body, wherein each of said element forming regions is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method; (b) after said step (a), implanting ions in said first semiconductor region to form a lightly doped drain; (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes; (d) after said step (c), implanting ions in said first semiconductor region to form a fourth semiconductor region of n-type conductivity; (e) after said step (c), implanting ions in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and (f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region, wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region, wherein a depth of said fifth semiconductor region is greater than a depth of said fourth semiconductor region, wherein said gate electrode of said n-channel MISFET is N-type gate electrode, and wherein said gate electrode of said p-channel MISFET is P-type gate electrode.