Patent ID: 8826097
Filing Date: 2014-09-02
Classification: G06F,H03M

Abstract:
1. A data processing apparatus comprising: a processor core having a fetch unit, a decode unit, and an issue unit, said processor core configured to perform data processing operations in response to a sequence of program instructions including a data scrub program instruction; a storage unit configured to store data values for access by said processor core when performing said data processing operations, wherein redundant error control data is stored in association with said data values, said redundant error control data enabling identification of an error in said data values; and a data scrubbing unit configured to perform a data scrubbing process on at least a subset of said data values, said data scrubbing process comprising determining with reference to said redundant error control data if said error is present in said subset of data values and, where possible, correcting said error with reference to said redundant error control data, wherein said data scrubbing unit is configured to receive a scrub transaction issued within said processor core, and said data scrubbing unit is configured to perform said data scrubbing process upon receipt of said scrub transaction, and wherein said processor core is configured to issue said scrub transaction to said storage unit in response to said data scrub program instruction in said sequence of program instructions decoded by said decode unit of said processor core.