Patent ID: 7069306
Filing Date: 2006-06-27
Classification: G06F

Abstract:
1. A method for managing memory in a multiprocessor system, comprising: defining a plurality of processor coherence domains within a system coherence domain of a multiprocessor system, the processor coherence domains each including a plurality of processors and a processor memory; providing shared access to data in the processor memory of each processor coherence domain only to elements of the multiprocessor system within the processor coherence domain; providing non-shared access to data in the processor memory of each processor coherence domain to elements of the multiprocessor system within and outside of the processor coherence domain; defining a plurality of partition coherence domains within the system coherence domain of the multiprocessor system, each partition coherence domain including at least one processor coherence domain, a router node, and a peer input/output node, each partition coherence domain providing memory coherence for its respective processor coherence domain, router node, and peer input/output node.