Patent ID: 8643815
Filing Date: 2014-02-04
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a substrate; a plurality of gate lines; a plurality of data lines crossing the gate lines; a transistor electrically connected to a first gate line and a first data line; a pixel electrode electrically connected to the transistor, the pixel electrode disposed on the substrate; a first common electrode insulated from the pixel electrode, overlapped with the pixel electrode, and disposed on the pixel electrode such that the pixel electrode is disposed between the first common electrode and the substrate; a second common electrode adjacent to the first common electrode such that the first data line is disposed between the first and second common electrodes; and a connecting portion electrically connecting the first and second common electrodes to each other, wherein the first common electrode has at least two slits overlapped with the pixel electrode, wherein the pixel electrode forms a continuous plane between adjacent slits of the first common electrode, and wherein the connecting portion overlaps with at least a portion of the first data line, and is formed from a same layer as the first and second common electrodes.