Patent ID: 6511887
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A method for fabricating dual gate oxides on the same integrated circuit chip comprising the steps of:providing a semiconductor substrate having logic device areas and memory device areas surrounded and electrically isolated by field oxide regions; removing a first native oxide from said logic and memory device areas; depositing a blanket silicon nitride (Si3N4) layer on said substrate; patterning said Si3N4 layer leaving portions over said logic device areas and exposing surface of said memory device areas; removing a second native oxide from said memory device areas; oxidizing surface of said substrate to form a gate oxide on said memory device areas and concurrently to convert said Si3N4 layer to a nitrogen-rich silicon oxide layer on said logic device areas; depositing and patterning a polysilicon layer to form FET gate electrodes.