Patent ID: 7996650
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A microprocessor configured to perform a speculative tablewalk, comprising: a translation lookaside buffer (TLB), configured to indicate that a physical page address of a page of memory that a memory access instruction is attempting to access is missing in the TLB; and a tablewalk engine, configured to: wherein to determine whether at least one of the predetermined set of conditions exists, the tablewalk engine is configured to at least determine whether the memory page whose physical page address is missing in the TLB is a global page; wherein to determine whether the memory page whose physical page address is missing in the TLB is a global page, the tablewalk engine is configured to at least determine whether the memory page whose physical page address is missing in the TLB is of a type for which the microprocessor will not invalidate an entry in the TLB for the memory page when the microprocessor performs a task switch.