Patent ID: 7536611
Filing Date: 2009-05-19
Classification: G11C

Abstract:
1. A method of performing built-in self repair of memories comprising: loading a value into an on-chip counter through a test pattern during production testing, where the value represents an amount of redundant elements which are allowed for a repair; testing the memories a first time; generating a repair solution; identifying memories which require a number of redundant elements for repair which exceeds the value that has been loaded into the on-chip counter; using the repair solution to repair a first set of damaged memories while not repairing and instead flagging a second set of damaged memories, wherein each of the memories in the second set have been identified as requiring a number of redundant elements to be used for the repair, where the number exceeds the value which has been loaded into the on-chip counter; making an on-chip assessment to test the memories a second time; and using the repair solution to repair damaged memories which were not previously flagged.