Patent ID: 7973398
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. An embedded chip package structure, comprising: a supporting board with at least one protruding section; at least a first semiconductor chip having a plurality of electrode pads and mounted on a surface of the protruding section of the supporting board, wherein the surface of the protruding section is flat and free of any cavity; at least a second semiconductor chip having a plurality of electrode pads mounted on a region of the supporting board except the protruding section, wherein the first and second semiconductor chips are slightly different in thickness, and the height of the protruding section of the supporting board can be varied according to the thicknesses of the first and second semiconductor chips so as to keep electrically connecting surfaces of the first and second semiconductor chips flush with each other; a dielectric layer formed on the supporting board and the first semiconductor chip and being in contact with the supporting board, the protruding section and the first and second semiconductor chips, wherein the dielectric layer covers the protruding section; and a circuit layer formed on the dielectric layer, wherein the circuit layer is electrically connected to the electrode pads of the first and second semiconductor chips through a plurality of conducting structures formed inside the dielectric layer.