Patent ID: 7821813
Filing Date: 2010-10-26
Classification: B82Y,G11C,H01L,Y10S

Abstract:
1. A memory device comprising: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode in a first direction parallel to a top surface of the substrate; a second electrode formed over the first electrode to partially overlap the first electrode in a direction perpendicular to the substrate; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes so as to electrically insulate the first electrode from the second electrode in a first state wherein if the first and second nanowires do not electrically contact each other, and wherein the first and second nanowires are capable of contacting each other in a second state such that the first and second electrodes are electrically connected to each other.