Patent ID: 6174822
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:sequentially forming a lower electrode, a dielectric film, and an upper electrode on a supporting substrate having an integrated circuit, thereby forming a capacitor;forming a first interlayer insulating film so as to cover the capacitor;forming a first contact hole in the first interlayer insulating film;selectively forming a first interconnect in the first contact hole and on a prescribed area of the first interlayer insulating film so as to be electrically connected to the integrated circuit and the capacitor;forming a second interlayer insulating layer consisting of a singular second interlayer insulating film of thermal ozone TEOS so as to cover the first interconnect;subjecting the first interconnect to a first thermal treatment;forming a second contact hole in the second interlayer insulating film;selectively forming a second interconnect in the second contact hole and on a prescribed area of the second interlayer insulating film so as to be electrically connected to the first interconnect;subjecting the second interconnect to a second thermal treatment; andforming a passivation layer so as to cover the second interconnect.