Patent ID: 7050955
Filing Date: 2006-05-23
Classification: G06T

Abstract:
1. A processor-readable medium comprising code representing instructions to cause a processor to: analyze a first scene graph having a plurality of interconnected nodes, the first scene graph being associated with a first scene; analyze a second scene graph having a plurality of interconnected nodes, the second scene graph being associated with a second scene; associate, using a neutral scene graph, each node from the plurality of interconnected nodes of the first scene graph with a node from the plurality of interconnected nodes of the second scene graph independent of any connections between the plurality of interconnected nodes of the first scene graph and any connections between the plurality of interconnected nodes of the second scene graph; update information associated with the first scene graph at a first update rate; and update information associated with the second scene graph at a second update rate, the second update rate being substantially higher than the first update rate, the code representing instructions to cause a processor to update the information associated with the second scene graph being configured to cause the processor to update the information associated with the second scene graph via a separate thread from the code representing instructions to cause a processor to update the information associated with the first scene graph.