Patent ID: 6636576
Filing Date: 2003-10-21
Classification: H03L

Abstract:
A method for reducing the settling time in PLL circuits which have a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage for controlling a voltage-controlled oscillator provided by means of a varactor, comprising:determining the dependency of the control voltage of said voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current of said digital-analog converter, wherein said law of variation of the output current of said digital-analog converter is nonlinear, such that the voltage obtained from the output current of said digital-analog converter, added to an output voltage of said filter, is such as to keep said filter voltage constant, in order to reduce the settling time of said PLL circuit when changing a selected channel.