Patent ID: 7263003
Filing Date: 2007-08-28
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: first memory cells each of which has a first MOS transistor including a floating gate and a control gate, and a second MOS transistor having a drain connected to a source of the first MOS transistor; a first cell array in which the first memory cells are arranged in a matrix; second memory cells each of which has a third MOS transistor including a floating gate and a control gate, and a fourth MOS transistor having a drain connected to a source of the third MOS transistor; a second cell array which includes the second memory cells; a memory cell array which includes the first cell array and the second cell array; first bit lines each of which electrically connects commonly the drains of the first MOS transistors in a same column in the first cell array; second bit lines each of which electrically connects commonly the drains of the third MOS transistors in a same column in the second cell array; a first precharge circuit which precharges the first bit lines in a read operation; a sense amplifier which amplifies the data read from the first memory cells in the read operation; a read control circuit which precharges and discharges the second bit lines in the read operation and, on the basis of the time required to precharge and discharge the second bit lines, controls the first precharge circuit and the sense amplifier; and word lines each of which connects commonly the control gates of the first and third MOS transistors in a same row in the memory cell array; a well region in which the first memory cells and the second memory cells are formed; a first row decoder which applies a voltage to the word lines and the well region in a write operation and an erase operation; and write circuits which are provided so as to correspond to the first bit lines and the second bit lines and which hold write data.