Patent ID: 9147457
Filing Date: 2015-09-29
Classification: G11C

Abstract:
1. A memory apparatus comprising: a first reference cell in a first array of reference cells, the first reference cell including a first reference magnetic tunnel junction (MTJ) coupled to a first reference bit line, the first reference MTJ having a parallel magnetic orientation; a second reference cell in a second array of reference cells, the second reference cell including a second reference MTJ coupled to a second reference bit line, the second reference MTJ having the parallel magnetic orientation; a third reference cell in a third array of reference cells, the third reference cell including a third reference MTJ coupled to a third reference bit line, the third reference MTJ having the parallel magnetic orientation; a word line coupled to the first reference cell, the second reference cell and the third reference cell; and programmable switching circuitry configured to simultaneously couple the first reference bit line, the second reference bit line and the third reference bit line to a merged reference node to generate a merged reference level on the merged reference node or to selectively de-couple the first reference bit line from the merged reference node and to simultaneously couple the second reference bit line and the third reference bit line to the merged reference node to generate the merged reference level on the merged reference node.