Patent ID: 6781431
Filing Date: 2004-08-24
Classification: H02M,H03K

Abstract:
A clock generating circuit generating a clock signal comprising:a ring oscillator including an odd number of first inverters connected in a ring configuration, being activated to generate a clock signal when an activating signal is at a first level, while being deactivated to cease generation of said clock signal when said activating signal is at a second level; and a latch circuit, connected to an output node of said ring oscillator, and holding a level of the output node of said ring oscillator in response to transition of said activating signal from said first level to said second level, wherein the output node of said ring oscillator is an internal node in the ring configuration and the level of the output node of the ring oscillator is driven to one of a high level and a low level in accordance with the timing of the activating signal driven to the second level from the first level.