Patent ID: 7535981
Filing Date: 2009-05-19
Classification: G06F

Abstract:
1. A clock generation circuit for generating an output clock signal having a frequency freq between a frequency fref/A of a first divided clock signal and a frequency fref/(A+1) of a second divided clock signal on the basis of the first divided clock signal obtained by dividing a reference clock signal having a frequency fref by A and the second divided clock signal obtained by dividing the reference clock signal by (A+1), said clock generation circuit comprising: dividing means for selectively generating the first divided clock signal and the second divided clock signal and for outputting a selected divided clock signal as the output clock signal; and correction means for controlling said dividing means so as: if C<D, repeating C times the process of generating the second divided clock signal once and generating the first divided clock signal (Q−1) times; and if C>D, repeating D times the process of generating the first divided clock signal once and generating the second divided clock signal (Q−1) times, where A, B, and C are natural numbers satisfying the following formula (1): where D=B−C, Q is the quotient of B/C for C<D, and Q is the quotient of B/D for C>D.