Patent ID: 6181618
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A dynamic type RAM comprising:a memory cell array portion having pairs of bit lines, a plurality of word lines and a plurality of memory cells connected to the pairs of bit lines and the word lines, for electrically storing data, and a sense amplifier portion for detecting data from the bit lines through transfer gates and amplifying the data thus detected,wherein each of the pairs of bit lines extend in a column direction, and in said each pair of bit lines, a voltage amplitude of a signal to be applied to those parts of the bit lines which are connected to the memory cell array portion is different from a voltage amplitude of a signal to be applied to those parts of the bits lines which are connected to the sense amplifier portion, and a precharge voltage to be applied to those parts of the bit lines which are connected to the memory cell array portion is different from a precharge voltage to be applied to those parts of the bit lines which are connected to the sense amplifier portion.