Patent ID: 6064607
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A semiconductor memory device comprising:a decoder generating an address predecode signal of a plurality of bits in response to an address signal;a plurality of address predecode signal lines corresponding to the plurality of bits of said address predecode signal, each address predecode signal line transmitting a signal of a corresponding bit of said address predecode signal; anda plurality of program circuits corresponding to a plurality of redundancy circuits, each program circuit being programmable of a defective address, and rendering a corresponding redundancy circuit active when an input address predecode signal matches the programmed defective address, each of said program circuits includinga plurality of transistors, corresponding to said plurality of address predecode signal lines,a determination node from which a signal is generated to determine whether to render said corresponding redundancy circuit active or not, anda plurality of fuses corresponding to said plurality of transistors, each fuse being connected between said determination node and a corresponding transistor, whereinfirst plurality of transistors corresponding to each of said address predecode signal lines in a first program circuit are each located adjacent to a respective transistor of a second plurality of transistors included in a second program circuit;said semiconductor memory device further comprising;a plurality of supply lines corresponding to said plurality of address predecode signal lines, each supply line common to a transistor of the first program circuit and a transistor of the second program circuit located adjacent to each other, and connected between a corresponding address predecode signal line and gates of the transistors of the first and second program circuits located adjacent to each other.