Patent ID: 6198317
Filing Date: 2001-03-06
Classification: H03K

Abstract:
A circuit for N times frequency multiplication and 50% duty cycle equalization of an input clock signal, comprising:an edge detector circuit, for receiving said input clock signal at a frequency fin, and for outputting a one shot pulse signal for each transition cycle of said input clock signal, said one shot pulse signals comprising a pulse train at a frequency equal to fin, with a duty cycle less than 50%,a quantity N-1 first-stage duty cycle control buffers, where N is an integer>=2, said first-stage duty cycle control buffers for simultaneously receiving said one shot pulse train from said edge detector circuit and for individually adjusting said one shot pulse train to the preset duty cycle values of said first-stage duty cycle control buffers,wherein said preset duty cycle values are 1/N, 2/N,...,N-1/N, respectively,a rising and falling edge detector, for receiving an output signal from said first-stage duty cycle control buffer having a duty cycle equal to 1/N, said rising and falling edge detector outputting a one shot pulse signal for each transition edge of said 1/N duty cycle signal, such that said one shot pulse signals outputted from said rising and falling edge detector occur at a frequency 2fin, equal to twice that of the input signal frequency fin,a quantity N-2 falling edge detectors, when N>2 , each said falling edge detector for receiving an output signal from its corresponding said first-stage duty cycle control buffer having a duty cycle equal to 2/N,...,N-1/N, respectively, wherein each said falling edge detector outputs a one shot pulse signal for each transition cycle of said 2/N,...,N-1/N input signals, such that said one shot pulse signals outputted from said falling edge detectors occur at a frequency fin, equal to that of said input signal frequency,an OR gate, for receiving said output signal from said rising and falling edge detector, and, when N>2 , for also receiving said output signals from said N-2 falling edge detectors, said OR gate for outputting a pulse train comprising all said edge detected signals, such that said OR gate output signal frequency is equal to N times said input frequency fin,a second-stage 50% duty cycle control buffer, for receiving said OR gate output signal at frequency N times fin, and for adjusting said OR gate output signal to a 50% duty cycle, at frequency N times fin.