Patent ID: 8217712
Filing Date: 2012-07-10
Classification: G05F

Abstract:
1. A semiconductor device comprising: a word line; a first bit line; a second bit line; at least one memory cell which is coupled between the word line and the first bit line, and which comprises a memory cell transistor; a sense amplifier circuit comprising: a replica transistor which is a replicate of the first transistor, and which comprises a third substrate, a firth gate and a firth source-drain path; a voltage generating circuit which generates a substrate bias voltage and supplying the substrate bias voltage in common to the first substrate of the first transistor, the second substrate of the second transistor, and the third substrate of the replica transistor; a monitor circuit which monitors a level of the substrate bias voltage; and a control circuit which is coupled to the replica transistor and the monitor circuit, and which controls the voltage generating circuit in response to an output of the monitor circuit and a replica voltage across the fifth source-drain path of the replica transistor.