Patent ID: 6423622
Filing Date: 2002-07-23
Classification: H01L,H05K,Y10T

Abstract:
A method of making a multilayer substrate for use in forming a lead-bond type chip package comprising the steps ofproviding an interlayer circuit board in which conductor circuits have been formed, the interlayer circuit board having a dielectric layer formed thereon and a slot defined therein; providing a first copper foil with one surface coated by a etch-resistant layer; laminating on one surface of the interlayer circuit board the first copper foil, and the other surface of the interlayer circuit board a second copper foil in a manner that the etch-resistant coated surface of the first copper foil is in contact with the dielectric layer on the interlayer circuit board; selectively etching the copper foils laminated on the interlayer circuit board so as to form fine holes at predetermined positions thereof; applying laser beams to the dielectric layer of the interlayer circuit board exposed from the fine holes of the copper foils so as to form via holes and expose parts of the conductor circuits of the interlayer circuit board; forming through-holes; plating a metal layer to electrically connect the conductor circuits of the interlayer circuit board and the copper foils; selectively etching the first copper foil and the plated metal layer thereon to form a plurality of leads adapted for electrically connecting to a semiconductor chip wherein each of the leads has at least a portion across the slot of the interlayer circuit board, and selectively etching the second copper foil and the plated metal layer thereon to form a predetermined configuration and expose the slot of the interlayer circuit board; stripping the etch-resistant on the first copper foil exposed within the slot of the interlayer circuit board; forming a solder mask on the patterned surfaces of the multilayer substrate in a manner that areas on the leads for electrically connecting to a semiconductor chip and solder pads for making external electrical connection are exposed from the solder mask; and forming a metal coating on the solder pads and the exposed portions of the leads.