Patent ID: 7947603
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. A chemical mechanical polishing process for manufacturing a semiconductor device, comprising the steps of: forming a conductive layer over a first dielectric layer formed over a semiconductor substrate; patterning said conductive layer to form a patterned conductive layer with multiple first openings; forming at least one second dielectric layer to cover said patterned conductive layer and to fill said multiple first openings, said at least one dielectric layer having a first thickness; polishing said at least one second dielectric layer to form a planar surface; forming at least one cap layer with a second thickness over said planar surface to adjust an overall thickness to a predetermined thickness, wherein the overall thickness comprises thinknesses of the at least one second dielectric layer and the at least one cap layer; patterning said at least one cap layer and said at least one second dielectric layer to form multiple second openings; and forming conductive vias in said multiple second openings.