Patent ID: 6813713
Filing Date: 2004-11-02
Classification: G06F,Y02D

Abstract:
A data processing apparatus comprising:a program memory which stores an operation program comprised of a variety of instructions; an external input terminal fed with a variety of data and a variety of signals from the outside; a clock input terminal fed with a clock signal from the outside; a data processing circuit for executing a variety of data processing in synchronization with the clock signal fed through said clock input terminal from the outside in accordance with a variety of data fed through said external input terminal from the outside and the operation program stored in said program memory; an input monitor circuit for monitoring the variety of data and the variety of signals fed through said external input terminal from the outside to execute a predetermined counter-operation upon determining that the data or signals are improper; an operation control circuit for controlling operations involved in temporarily stopping and restarting said input monitor circuit and said data processing circuit; a clock counter circuit for counting the clock signal fed through said clock input terminal from the outside when said operation control circuit temporarily stops said input monitor circuit and said data processing circuit; and a monitor start circuit for restarting said input monitor circuit temporarily stopped by said operation control circuit when a count number of said clock counter circuit reaches a predetermined number.