Patent ID: 9160459
Filing Date: 2015-10-13
Classification: H04B

Abstract:
1. An equalization signal processor, comprising: an equalization filter configured to receive digital signals by coherent receiving systems; a coefficient controller configured to control coefficients defining characteristics of the equalization filter; a significant coefficient holding unit configured to hold significant coefficients of significant values among initial values of the coefficients; a significant coefficient positioning unit configured to determine a significant coefficient position, a position of the significant coefficients in the initial values, so that equalization characteristics of the equalization filter may be optimized; and a significant coefficient setting unit configured to allocate the significant coefficients to the significant coefficient position; wherein: the significant coefficient positioning unit-includes a signal quality monitor; the signal quality monitor detects signal quality of output from the equalization filter; the significant coefficient positioning unit determines the significant coefficient position on the basis of the signal quality; the significant coefficient positioning unit further includes a coefficient initializing unit; the coefficient initializing unit determines whether or not the coefficients have fallen into a local optimum solution on the basis of the output of the signal quality monitor, and if it is determined that the coefficients have fallen into a local optimum solution, sends a notification about it to the coefficient controller; and the coefficient controller, in receiving the notification, sets the coefficients again and performs an adaptive control again keeping the optimum significant coefficient position held.