Patent ID: 7482270
Filing Date: 2009-01-27
Classification: H01L,Y10S

Abstract:
1. A method of forming fully and uniformly silicided gate conductors on a semiconductor device, comprising the steps of: providing a semiconductor device comprising a silicon substrate and one or more gate stacks formed on the silicon substrate, said one or more gate stacks each further comprising a gate conductor overlying a thin gate dielectric, said thin gate dielectric spacing the gate conductor away from a corresponding channel region defined in the silicon substrate; disposing a layer of a self-assembling diblock copolymer overlying the one or more gate conductors, said diblock copolymer is a PS-PMMA block copolymer; annealing the diblock copolymer layer to cause it to organize itself into a repeating pattern of nanometer-scale polymer structures; developing the diblock copolymer layer to form a repeating pattern of nanometer-scale openings therein; selectively etching, using the developed copolymer layer as an etching template, to form nanometer-scale perforations extending into the one or more gate conductors, then depositing a silicide-forming metal over the one or more gate conductors, the selectively etching step including a reactive ion etch (RIE); selecting the silicide-forming metal from the group consisting of Ni, Ti, Pt, Co, Ta and alloys of said metals; saliciding to convert said one or more gate conductors to silicide, the one or more gate conductors are polysilicon prior to silicidation; wherein said step of saliciding is accomplished by means of a high-temperature rapid thermal anneal (RTA); and disposing a hardmask layer overlying the one or more gate conductors prior to disposing the diblock copolymer layer.