Patent ID: 7265051
Filing Date: 2007-09-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device comprising: preparing a substrate including a cell area and a peripheral circuit area; forming transistors on the substrate including the cell area and the peripheral circuit area, each transistor having a gate electrode structure including a gate electrode, a gate electrode capping pattern formed on the gate electrode, and sidewall spacers formed at sidewalls of the gate electrode and the gate electrode capping pattern, and having a source region and a drain region; forming a first interlevel dielectric layer over an entire surface of the substrate including the transistors; etching the first interlevel dielectric layer to simultaneously form a bit line contact hole in the cell area and a metal wiring contact hole in the peripheral circuit area; and filling the bit line contact hole and the metal wiring contact hole with a conductive material, to simultaneously form a bit line connector connected to a drain region of at least one of the transistors formed in the cell area and a metal contact connector connected to a drain region or a gate electrode of at least one of the transistors formed in the peripheral circuit area, wherein after said filling to form the bit line connector and the metal contact connector, further comprising: