Patent ID: 7703057
Filing Date: 2010-04-20
Classification: G06F

Abstract:
1. A method for converting a capacitor network of an electronic circuit having floating nets and non-floating nets with mutual capacitances into a reduced capacitor matrix to represent the capacitor network in a computer storage device, comprising: associating each of a first plurality of mutual capacitances with two of a plurality of non-floating nets in a first matrix C associating each of a second plurality of mutual capacitances with one of the plurality of non-floating nets and one of a plurality of floating nets in a second matrix C associating each of a third plurality of mutual capacitances in the electronic circuit with two of the plurality of floating nets in a third matrix C determining leading diagonal entries of a reduced capacitor matrix C_red for the electronic circuit using a computer, wherein reduced matrix C_red=first matrix C for each of the plurality of non-floating nets in the electronic circuit, associating a ground capacitance in the electronic circuit with a non-floating net in the electronic circuit that is substantially equal to an associated leading diagonal entry and to a determined self-capacitance of the non-floating net.