Patent ID: 6996739
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. An apparatus, comprising: a functional unit configured to perform an operation on one or more block operands; an accumulator memory comprising a first memory bank having a first interface and a second memory bank having a second interface, wherein the first and second interfaces are independent of each other; and a control unit configured to receive a first command to perform the operation on a first operand identified by an address of the accumulator memory and to store a first result of the operation to the same address; wherein in response to receiving the first command, the control unit is configured to cause the first memory bank to output the first operand to the functional unit via the first interface and to cause the second memory bank to store the first result generated by the functional unit via the second interface; wherein the functional unit is configured to perform the operation on two operands, wherein the second operand is provided by a source other than the first and second memory banks, wherein the source of the second operand and the accumulator memory each comprise a same type and speed of single-ported memory.