Patent ID: 6609227
Filing Date: 2003-08-19
Classification: G06F,Y10S

Abstract:
An Integrated Circuit (IC) Schematic design method having a set of Schematic design programs and an initial Schematic database of data describing a Schematic for an IC, said IC Schematic design method comprising the steps of:(a) organizing said set of Schematic design programs as executable programs states; (b) coupling said executable program states with a program scheduler; (c) executing, in parallel, selected Logic program states from said set of Schematic programs states; (d) executing a checking program state, said checking program state operable to detennine if changes to said Schematic database data are related to a logic functionality of said IC; (e) completing said selected Logic program states and starting additional Logic program states unless stopped by said program scheduler; (f) determining if all program states in said set of program states have completed successfully; (g) correcting said Schematic database data by said designer if all programs have not completed successfully; and (h) repeating said method steps from step (c-g) in response to one or more designer control inputs, wherein said designer control inputs comprise a start program scheduler, a stop program scheduler, set Audit Mode, and set Non-Audit Mode.