Patent ID: 8711635
Filing Date: 2014-04-29
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell string comprising memory cells connected in series; a bit line electrically connected to one end of the memory cell string; a source line electrically connected to the other end of the memory cell string; a control circuit configured to perform a plurality of write operations, each write operation followed by a verify operation for checking a threshold voltage of a memory cell after data is written to the memory cell in the write operation, the verify operation including a first verify process and a second verify process, the control circuit being configured to determine whether a threshold voltage of a memory cell is equal to or higher than a first verify voltage in the first verify process, the control circuit being configured to determine whether the threshold voltage of the memory cell is equal to or higher than a second verify voltage higher than the first verify voltage in the second verify process; and a voltage setting circuit connected to the bit line through a transistor and configured to set a charging voltage for the bit line in the verify operation and to make the charging voltage in the second verify process higher than the charging voltage in the first verify process.