Patent ID: 8395218
Filing Date: 2013-03-12
Classification: B82Y,H01L

Abstract:
1. A gate-all-around type semiconductor device comprising: a source layer and a drain layer disposed at a predetermined distance apart from each other in a first direction on a semiconductor substrate; a nanowire channel connecting the source layer and the drain layer; a gate electrode extending in a second direction substantially perpendicular to the first direction, wherein the gate electrode has a height in a third direction substantially perpendicular to the first and second directions and partially surrounds the nanowire channel; and an insulation layer pattern between the gate electrode and the source/drain layers on the semiconductor substrate to separate the gate electrode from the source/drain layers in the first direction, the insulation layer pattern covering the nanowire channel and a portion of the gate electrode, wherein the insulation layer pattern surrounds the nanowire channel at both sides of the gate electrode.