Patent ID: 6304961
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A computer system comprising:an instruction cache for storing a plurality of processor instructions, the instruction cache includingan instruction array for storing the plurality of processor instructions;an instruction class array for storing an instruction class for each of the plurality of processor instructions; anda predictive annotation array for storing at least one prediction indicator for each of the plurality of processor instructions, wherein the instruction cache selectively refers to the predictive annotative array based upon the instruction class;a next address fetch array for storing at least one next fetch address, each next fetch address associated with at least one of the processor instructions stored in the instruction array and indicating a location of a processor instruction to be fetched;a next fetch address register, coupled to the instruction cache, for receiving a next fetch address associated with each processor instruction previously fetched from the instruction cache; anda fetch unit, coupled to the instruction cache and the next fetch address register, for fetching a processor instruction stored at a location indicated by each next fetch address received at the next fetch address register.