Patent ID: 7667473
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a die having a plurality of solder bumps formed on an active surface thereof; a substrate; a plurality of conductive post structures mounted on a top surface of the substrate, each aligned to make electrical contact with a corresponding solder bump, wherein the conductive post structures are flexible to absorb lateral forces exerted upon the solder bumps, wherein each conductive post structure comprises: a conductive post mounted to the substrate, the conductive post comprising a first layer of a material to which the solder bumps do not bond extending upward from the substrate; and a second layer comprising a plating layer attached to a top surface of the conductive post and extending upward from the first layer to and in electrical contact with the corresponding solder bump, wherein sides of the first layer are not covered by the second layer comprising the plating layer; and a lid attached to the substrate by a bonding material, wherein the lid encapsulates the die.