Patent ID: 6483150
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; an element separation insulating film formed on a surface of said semiconductor substrate and defining first and second active regions; a first MISFET formed in the first active region and having a gate insulating film, a gate electrode, a source region, a drain region and a side wall spacer, the drain region of said first MISFET having a lightly doped drain structure with a low concentration region and a high concentration region, the low concentration region contacting the gate electrode as viewed along a substrate normal direction, and the side wall spacer conformingly covering a side wall of the gate electrode and a surface of the low concentration region in the drain region; a second MISFET formed in the second active region and having a gate insulating film, a gate electrode, a source region, a drain region and a side wall spacer, the side wall spacer of said second MISFET covering a side wall of the gate electrode and extending to surfaces of the source and drain regions; and an interlayer insulating film covering said first MISFET and second MISFET and being made of material having an etching resistance different from an etching resistance of the side wall spacers of said first MISFET and second MISFET.