Patent ID: 7500059
Filing Date: 2009-03-03
Classification: G06F

Abstract:
1. An storage system comprising: a plurality of central processing units (CPUs) configured to issue I/O commands; a disk apparatus configured to be accessed by said CPUs via an internal bus; a disk cache configured to cache at least a part of data stored in said disk apparatus, said disk cache being connected to said disk apparatus; and an I/O processor configured to receive said I/O commands and to issue disk I/O commands to said disk apparatus and said disk cache, said I/O processor being connected to said internal bus such that said CPUs access said disk apparatus and said disk cache optionally via said I/O processor, wherein each of said CPUs is configured to issue a request to said I/O processor to configure a partial area of said disk cache as a communication buffer for transferring data among said CPUs without saving said data in said disk apparatus, wherein said I/O processor is configured to configure said partial area of said disk cache only as said communication buffer, after receiving the request to configure said partial area, wherein each of said CPUs is configured to write data into said communication buffer for another one of said CPUs to fetch; said communication buffer is a message queue comprising a plurality of slots; said slots are used sequentially in a round-robin manner, starting from the first one of said slots; and by storing a position of one of said slots, which has been just used, a position of the following one of said slots, which is to be subjected to next-availability verification, is determined univocally at a communication time.