Patent ID: 6323692
Filing Date: 2001-11-27
Classification: H03D,H03K,H03L

Abstract:
A phase comparator comprising:a first latch connected to receive a reference signal, the reference signal having a first and a second logical state, and the first latch outputting a first control signal for a correction signal generator, the first control signal having a first and a second logical state;a second latch connected to receive a monitor signal, the monitor signal having a first and a second logical state, and the second latch outputting a second control signal for the correction signal generator, the second control signal having a first and a second logical state, the first and second control signals indicative of relative phase of the reference signal and the monitor signal; anda reset circuit for resetting the first and second latches when both of the following conditions are met:a) a logical OR operation performed by the reset circuit indicates that one of the reference signal is in the first logical state or the first control signal is in the first logical state; andb) a logical OR operation performed by the reset circuit indicates that one of the monitor signal is in the first logical state or the second control signal is in the first logical state.