Patent ID: 6482728
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method for fabricating a floating gate in a non-volatile memory device, the method comprising:forming a conductive layer having upper and lower portions over a substrate with field regions formed therein; forming a hard mask layer over the conductive layer; forming a photoresist pattern over the hard mask layer; etching the hard mask layer to form a hard mask pattern, using the photoresist pattern as an etching mask; slope-etching the upper portion of the conductive layer, leaving the lower portion of the conductive layer un-etched, using the photoresist pattern as an etching mask; and vertically etching the slope-etched upper portion of the conductive layer and concurrently slope-etching the lower portion of the conductive layer, using the hard mask pattern as an etching mask.