Patent ID: 6639243
Filing Date: 2003-10-28
Classification: H01L,Y10S

Abstract:
A DRAM cell, comprising:a first monocrystalline silicon substrate; an electrically conductive region extending through the first monocrystalline silicon substrate; a DRAM capacitor under the first monocrystalline substrate; the DRAM capacitor comprising an electrically conductive storage node electrically connected with the electrically conductive region; the DRAM capacitor comprising a dielectric material and an electrically conductive cell plate spaced from the electrically conductive storage node by at least the dielectric material; a second monocrystalline silicon substrate beneath the DRAM capacitor and joined to the electrically conductive cell plate through an oxide bonding region; and a DRAM transistor gate over the first monocrystalline silicon substrate; the transistor gate being comprised by a transistor device which includes a source/drain region electrically connected to the DRAM capacitor electrically conductive storage node through the electrically conductive region.