Patent ID: 6404666
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A read only memory comprising:a plurality of word lines arranged in a first direction, one of said word lines activated in response to an address signal; a plurality of sense lines arranged in a second direction so that said word lines and said sense lines are intersected, one of said sense lines selected in response to a selection signal; a reference sense line arranged in the second direction so that said word lines and said reference sense line are intersected; a plurality of memory cells storing data therein arranged at intersections between said word lines and said sense lines, wherein one of said memory cells connected the activated one of said word lines and the selected one of said sense lines is selected; a plurality of reference memory cells arranged at intersections between said word lines and said reference sense line; a sense amplifier for comparing currents flowing on the selected one of said sense lines and on said reference sense line so that the data stored in said selected one of said memory cells is detected; and a correction current supply circuit operatively coupled to said sense lines and said reference sense line, said correction current supply circuit generating a correction current approximately corresponding to a leak current flowing through said memory cells connected to the selected one of said sense lines and providing the correction current to said sense lines and said reference sense line.