Patent ID: 6967138
Filing Date: 2005-11-22
Classification: H01L,H05K

Abstract:
1. A process for manufacturing a substrate with an embedded capacitor comprising the steps of: providing a substrate base having a surface; forming a first metal wiring layer on the surface of the substrate base, the first metal wiring layer including a lower electrode pad and plurality of traces; forming a dielectric layer on the surface of the substrate base; forming a hole in the dielectric layer to expose the lower electrode pad; filling a medium material into the hole of the dielectric layer, wherein the medium material is fully fitted into the hole of the dielectric layer and slightly protrudes from the dielectric layer in the filling step of the dielectric constant material; grinding the medium material until a top surface of the medium material is coplanar with the top surface of the dielectric material, wherein the thickness of the dielectric material is not changed; and forming a second metal wiring layer on the dielectric layer, the second metal wiring layer including an upper electrode pad, the upper electrode pad covering the top surface of the medium material and being parallel to the lower electrode pad so as to form an embedded capacitor.