Patent ID: 8416116
Filing Date: 2013-04-09
Classification: H03M

Abstract:
1. A successive approximation analog-to-digital converter, comprising: a positive and a negative input terminals; a capacitor array having at least one capacitor with a first and a second terminals, and a plurality of bits, counting from a most significant bit (MSB) to a least significant bit (LSB), wherein each of the plurality of bits electrically connects with the at least one capacitor, the first terminal electrically connects with one of the positive input terminal and the negative input terminal, and the second terminal switchably connects with a first and a second reference voltage sources to selectively receive one of a first reference voltage and a second reference voltage; a first comparator receiving an adjustable third reference voltage and electrically connected to the positive input terminal, wherein the second terminal of each the at least one capacitor is configured to be switched when the voltage on the positive terminal is larger than a third reference voltage; and a second comparator receiving the third reference voltage and electrically connected to the negative input terminal, wherein the second terminal of the at least one capacitor is configured to be switched when the voltage on the negative terminal is less than a negative value of the third reference voltage.