Patent ID: 7956410
Filing Date: 2011-06-07
Classification: H01L

Abstract:
1. A trench DMOS transistor having overvoltage protection, comprising: a substrate having a first conductivity type; an epitaxial layer grown on said substrate; a body region disposed within said epitaxial layer having a second conductivity type, comprising a plurality of first-type function trenched gates, at least one second-type function trenched gate and at least two third-type function trenched gates extending through said body region and into said epitaxial layer; a doped polysilicon layer filled in said first, second and third-type function trenched gates over a gate oxide served as said first, second and third type function trenched gates; wherein said second-type function trench gate with said doped polysilicon layer having gate trenched contact filled with metal plug connecting to gate metal; wherein said third-type function trench gate is disposed in a manner directly and symmetrically underneath the ESD trenched contact areas of anode and cathode in a ESD protection diode as a buffer layer; a source region of said first conductivity type encompassed entirely within said body region disposed in the active area adjacent to at least one side of said first-type function trenches gates; an insulating layer lining over said first, second and third-type function trenches gates and overlying said body region and said source region; wherein said ESD protection diode comprises multiple back to back polysilicon Zener diodes disposed on top of said insulating layer wherein said anode and cathode areas have ESD trenched contacts filled with said metal plug, having trench width of said trenched contacts not greater than that of said third-type function trench gates; and a source-body trenched contact formed between two adjacent said first-type function trenches filled with said metal plug having a heavily doped region surrounding said source-body trenched contact below said source region with a same doping type as said body region; wherein said heavily doped region is disposed in a manner spaced apart from said epitaxial layer under said ESD protection diode.