Patent ID: 7826298
Filing Date: 2010-11-02
Classification: G11C

Abstract:
1. A semiconductor memory device driven by first and second power supply voltages during a normal operation, said second power voltage supplied to the semiconductor memory device being shut off during standby, the semiconductor memory device comprising: a memory cell driven by said first power supply voltage and storing data, a write/read circuit driven by said second power supply voltage and writing data into and reading data from said memory cell, and a pair of bit lines connected to said memory cell, said write/read circuit including a P-channel MOS transistor having a back gate receiving said first power supply voltage, having a source receiving said second power supply voltage, and having a drain connected to said memory cell, wherein said write/read circuit includes a decoder activating said memory cell during a write operation, and a write circuit setting any one bit line in said pair of bit lines to said second power supply voltage and setting the other bit line to a ground voltage in accordance with a write data signal, and writing said write data signal into said memory cell activated by said decoder, and said write circuit includes said P-channel MOS transistor provided to correspond to each of the bit lines and having the drain connected to said memory cell via the corresponding bit line.