Patent ID: 6047004
Filing Date: 2000-04-04
Classification: H04L,H04N

Abstract:
A synchronizing device for receiving an input data signal in which a first data signal formed of unit packets each having a sequence of P(.gtoreq.2) pieces of L(.gtoreq.1)-bit-long first unit data is assigned in a sequence of m(.gtoreq.1)-bit-long second unit data to form a second data signal, and for reconfiguring said first data signal from said input data signal and outputting the same, comprising:a shift register having a plurality of buffers, said plurality of buffers each having a storage capacity of m bits and successively holding said second unit data forming said input data signal;a pattern data extracting portion for extracting L-bit-long data from the data held in said shift register in correspondence with first to K(.gtoreq.1)th patterns in which said first unit data is sequentially assigned in said second data signal to obtain first to Kth extraction data;a first comparator portion for comparing each of said first to Kth extraction data with a synchronizing code as an indicator of a head word of a packet;a pattern selecting portion for selecting and outputting one of said first to Kth extraction data as an extraction signal;a state transition control portion for controlling the selecting operation of said pattern selecting portion depending on whether said state transition control portion in a synchronous state or an asynchronous state; anda synchronization determining portion for determining whether said state transition control portion in said synchronous state or said asynchronous state;wherein said state transition control portion comprises,a mode shifting portion for causing said pattern selecting portion to cyclically and sequentially select said first to Kth extraction data so that continuous L-bit-unit data are sequentially extracted from said input data signal, anda mode changing portion for, only in the asynchronous state, every time the comparison in said first comparator portion shows that only a kth (1.ltoreq.k.ltoreq.K) extraction data coincides with said synchronizing code, causing the sequential selection of the extraction data instructed by said mode shifting portion to said pattern selecting portion to be changed to a sequential selection in which the kth extraction signal corresponding to the kth pattern is set as a candidate for said head word and the extraction data are selected starting from the kth extraction data, andsaid synchronization determining portion comprises,a processing number generating portion capable of cyclically counting P integers as processing numbers in synchronization with output of said extraction signal,a second comparator portion for comparing said extraction signal with said synchronizing code, anda state determining portion for determining whether to make a transition between said synchronous state and said asynchronous state on the basis of said processing number and a result of the comparison in said second comparator portion,wherein, in said asynchronous state, when the comparison in said second comparator portion repeatedly provides agreement between said extraction signal corresponding to said candidate and said synchronizing code at a first certain frequency or more, said state determining portion determines to shift to said synchronous state and sets said candidate providing the agreement as a definite head word, and in said synchronous state, when the comparison in said second comparator portion repeatedly provides disagreement between said extraction signal corresponding to said definite head word and said synchronizing code at a second certain frequency or more, said state determining portion determines to shift to said asynchronous state, and said state determining portion determines whether said extraction signal corresponds to said candidate or said definite head word on a basis of said processing number.