Patent ID: 8539400
Filing Date: 2013-09-17
Classification: G06F

Abstract:
1. A method, in a data processing system comprising at least one hardware-implemented processor and at least one memory, for generating a logic design of an integrated circuit device, comprising: receiving, in the data processing system, an initial logic design representation of the integrated circuit device; identifying, by the data processing system, one or more areas of the initial logic design representation where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures; replacing, by the data processing system, logic elements in the one or more areas of the initial logic design representation with multiplexer tree structures to generate a modified logic design representation; outputting, by the data processing system, the modified logic design representation to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation; identifying and marking control lines in one of the initial logic design representation or the modified logic design representation; identifying and marking multiplexer tree roots in one of the initial logic design representation or the modified logic design representation; and performing re-synthesis of portions of the modified logic design representation corresponding to the marked control lines and multiplexer roots, wherein identifying and marking control lines comprises: selecting a logic gate in one of the initial logic design representation or the modified logic design representation; analyzing the nets of the selected logic gate to generate a state table for the selected logic gate; determining, based on the state table for the selected logic gate, whether the selected logic gate is a potential decoder; and marking nets corresponding to the selected logic gate as control lines in response to a determination that the selected logic gate is a potential decoder.