Patent ID: 7249335
Filing Date: 2007-07-24
Classification: G06F

Abstract:
1. A method of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) technique, the method comprising: analyzing logic placement in the design; generating a list of placement patterns as a result of analyzing the logic placement, the list of placement patterns including a list of nets associated with each placement pattern; wherein each net includes a source and one or more loads, and each net associated with a placement pattern has placement of the source relative to placement of the loads identical to each other net associated with the placement pattern; sorting the list of placement patterns in an order determined by a number of nets associated with each placement pattern; routing the nets associated with each placement pattern, in order from a placement pattern having a largest number of nets to a placement pattern having a smaller number of nets, to produce a fully routed design; generating a configuration bitstream for fully routed design; and compressing the configuration bitstream using the MFW technique, wherein the routing includes, in response to a placement pattern having more than two associated nets, determining whether more than two nets associated with the placement pattern are routable with one selected routing template, wherein a routing template specifies relative routing resources that represent a pattern of a possible route for all the nets associated with the placement pattern, and in response to determining that more than two nets associated with the routing pattern are routable with the one selected routing pattern, routing the more than two nets consistent with the one selected routing template.