Patent ID: 6735119
Filing Date: 2004-05-11
Classification: G11C

Abstract:
A nonvolatile semiconductor memory which is provided with a plurality of memory elements each having a control gate and a floating gate such that data is stored by electron injection to the floating gate and electron emission from the floating gate, comprising:an electric current detecting circuit configured for detecting a drain current supplied to a drain of each of the memory elements; and a voltage control circuit configured for controlling, in accordance with the drain current detected by the electric current detecting circuit, a control gate voltage supplied to the control gate of each of the memory elements, wherein the voltage control circuit includes a reference potential generating circuit configured for generating a first internal potential in response to an output of the electric current detecting circuit and an amplifier circuit for outputting, via a second internal potential, a third internal potential to an output node of the voltage control circuit in accordance with the first internal potential in response to a first supply potential; wherein the amplifier circuit includes a reference potential input portion configured for outputting the second internal potential in response to the first internal potential and a drive portion configured for driving the third internal potential of the output node in response to the second internal potential; wherein the reference potential input portion includes a first field effect transistor in which a source is connected to the first internal potential and a drain and a gate are connected to the second internal potential and a first current source which is provided between a first internal node subjected to a predetermined supply potential and the first field effect transistor so as to supply a first bias current to the first field effect transistor; and wherein the drive portion includes a second field effect transistor in which a gate is connected to the gate of the first field effect transistor and which is provided on a path connecting a second internal node subjected to the predetermined supply potential and the output node.