Patent ID: 6597740
Filing Date: 2003-07-22
Classification: H04N

Abstract:
A variable-length encoding and decoding apparatus comprising:a register which stores a bit stream of video compression information from an external apparatus; a first shift register which shifts a signal to the high-order direction by n bytes per a machine cycle; first selection means for selecting a vacant section of a successive predetermined bit number in a predetermined section from the least significant bit of the first shift register, and successively storing a signal of the first register from the high-order side of the vacant section of the first shift register; a second shift register which shifts the signal to the high-order direction by the optional bit number per a machine cycle; second selection means for selecting a vacant section of the successive predetermined bit number in a predetermined section from the least significant bit of the second shift register, and successively storing a signal of the second shift register from the high-order side of the vacant section of the second shift register; third selection means for selecting a signal of the successive predetermined bit number in the second shift register; variable-length encoding and decoding means for performing decoding and simultaneously outputting code length information which shows a code length of a variable-length code in the case where a signal selected by the third selection means is a variable-length code and can be decoded; fourth selection means for selecting a signal of the successive predetermined bit number from the first shift register, outputting the same while decoding processing of the variable-length code is being performed by the variable-length encoding and decoding means, and outputting a signal input from the third selection means when the decoding processing is completed; synchronizing word detecting means having first code detecting means for comparing the signal of the first shift register selected by the fourth selection means with a specific bit pattern to perform coincidence detection, and second code detecting means for comparing the signal of the second shift register selected by the fourth selection means with the specific bit pattern to perform coincidence detection; specific bit pattern position information management means which, when a signal of the specific bit pattern in the first shift register is detected by the first code detecting means and a signal of the most significant bit of the specific bit code is moved to the second shift register, at this point of time, sets head bit position information of the specific bit pattern in the second shift register at that timing, and, when shift processing is generated in the second shift register, updates the head bit position information in accordance with the shift amount; overlap detecting means which judges whether or not an overlap is generated between the variable-length code and the specific bit pattern in the second shift register, on the basis of code length information of the variable-length code from the variable-length encoding and decoding means and the head bit position information of the specific bit pattern from the specific bit pattern position information management means and, when the overlap is detected, outputs an overlap notifying signal.