Patent ID: 8652963
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit device on a silicon substrate having source and drain regions, comprising: depositing a gap fill layer over said source and drain regions; etching wide and narrow contact trenches through said gap fill layer to expose surfaces of said source and drain regions; depositing a layer of metal over said wide and said narrow contact trenches; forming an amorphous alloy layer comprising silicon intermixed with said metal at the interface of said metal layer and said silicon substrate, said amorphous alloy layer having a substantially uniform thickness in said wide and said narrow contact trenches; removing unreacted metal from said substrate surface prior to annealing; and thereafter annealing said substrate at a predetermined elevated temperature range for a predetermined period of time to convert at least a portion of said amorphous alloy layer into a thin silicide layer.