Patent ID: 7023016
Filing Date: 2006-04-04
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line formed on the substrate and including lower and upper films; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts and including lower and upper films; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and a portion of the gate insulating layer adjacent thereto and an opening exposing a first portion of the semiconductor layer; a pixel electrode formed on the passivation layer and contacting the lower film of the drain electrode through the first contact hole; and a columnar spacer formed on the exposed portion of the exposed first portion of the semiconductor layer.