Patent ID: 6847073
Filing Date: 2005-01-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a MOS transistor formed on a semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate such that the interlayer insulating film covers the MOS transistor; a contact plug formed in the interlayer insulating film and connected to an impurity diffusion layer of the MOS transistor; a capacitor lower electrode formed on the contact plug; a ferroelectric film formed on the capacitor lower electrode; and two capacitor upper electrodes formed on the capacitor lower electrode with the ferroelectric film interposed therebetween, a contact area between the contact plug and the capacitor lower electrode being greater than a contact area between each of the two capacitor upper electrodes and the ferroelectric film, and at least a part of a gate electrode of the MOS transistor being located just below a region of the contact plug, which region is in contact with the capacitor lower electrode.