Patent ID: 6295590
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A semiconductor memory apparatus, comprising:a memory portion storing a program;a terminal for external connection;a three-state buffer, one end of said three-state buffer is connected to said memory portion so that said three-state buffer can receive program data from said memory portion, and another end of said three-state buffer is connected to said terminal for external connection, said three-state buffer being capable of taking a high-impedance state in addition to two-value states of high-level and low-level;a key memory for storing key data;an input register, connected to said terminal for external connection, for storing a key release signal received via said terminal when said three-state buffer is in the high-impedance state;an RS flip-flop connected to said three-state buffer, for turning said three-state buffer into the high-impedance state to disconnect said memory portion from said terminal under a reset state and for canceling the high-impedance state under a set state;a power-on reset circuit for resetting said RS flip-flop when a power is turned on; anda comparator for comparing an output from said key memory and an output from said input register to set said RS flip-flop when the two outputs coincide.