Patent ID: 6577159
Filing Date: 2003-06-10
Classification: G06F

Abstract:
A programmable logic device, operating in one of two modes, one of said modes being called C mode, the other of said modes being called D mode, said device comprising:(a) a plurality of input channels, (b) a mode selection means of choosing C or D mode based on a subset of said plurality of input channels, (c) a plurality of output channels, (d) an internal storage memory, viewed conceptually as a lookup table organized in rows and columns, the number of said rows being 2 raised to the power of the number of gold input channels/2, the number of said columns being the same as the number of said output channels, (e) a writing means of modifying the contents of said storage memory based on said mode and a subset of said plurality of input channels, (f) a reading means of selecting some set of bits from said storage memory based on said mode and on the values of a subset of said plurality of input channels, (g) a detecting means of detecting certain bit patterns in said storage memory, (h) a setting means of setting a first subset of said output channels based on said mode, on said set of bits, and on said bit patterns, and (i) a setting means of, when said mode is D mode, setting a second subset of said output channels, disjoint from said first subset of output channels, based on a subset of said plurality of input channels, and on said bit patterns, whereby said programmable logic device can set certain output channels by using said storage memory as a lookup table, and can set certain other output channels by bypassing said storage memory and directly using certain inputs to set said other output channel values.