Patent ID: 6622198
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A method for loading a FIFO comprising:providing N logical locations; providing N+1 latch stages; and providing N+1 load pointer signals, wherein two load pointer signals are contemporaneously enabled during a FIFO load operations: wherein a first latch stage receives an active first load pointer signal causing the first latch stage to transparently receive input data; concurrently a second latch stage receives a second load pointer signal causing the second latch stage to transparently receive input data; in response to a FIFO load command, the first load pointer signal goes inactive, latching data into the first latch stage, the second load pointer signal remains active, and a transparent path for input data to the second latch stage is maintained; substantially simultaneously with loading the first latch stage, a third load pointer signal goes active causing a third latch stage to transparently receive input data; and following the execution of the load command, the first latch stage contains latched data, while the load pointer signals for the second and third latch stages are active allowing a transparent path for input data to both the second and third latch stages.