Patent ID: 8153521
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A method of manufacturing a wafer-level stack package, comprising: forming rewirings in at least one of a plurality of semiconductor chips, the rewirings being connected to pairs of power/ground pads of each of the semiconductor chips; stacking the semiconductor chips on one another; forming first through-holes that penetrate the power/ground pads and signal pads formed between the pairs of power/ground pads of the stacked semiconductor chips, respectively; forming a second through-hole that penetrates the stacked semiconductor chips, the second through-hole being connected to the rewirings; filling the first through-holes with a conductive material to form first connection members; and filling the second through-hole with a conductive material to form a conductive pillar, to thereby form a second connection member including the conductive pillar and the rewirings.