Patent ID: 6490673
Filing Date: 2002-12-03
Classification: G06F

Abstract:
A processor that processes a plurality of instructions in one cycle, comprising:A) a register; B) instruction fetching means for fetching the plurality of instructions that include at least a first instruction and a second instruction from an external program, the first instruction including a first access indication for accessing a first area, which is at least part of an area in the register, the second instruction including a second access indication for accessing a second area, which is at least part of the area in the register, wherein when the first area is a whole of the register, the second area is the part of the register, when the second area is the whole of the register, the first area is the part of the register, and at least one of the first and second access indications is for storing data in at least the part of the register; C) decoding means for decoding each of the fetched instructions and outputting at least decoded information on the register and on areas in the register in one cycle, the decoded information including at least information on the register and on the first and second areas; and D) access means for accessing the first and second areas according to the decoded information in one cycle.