Patent ID: 6201749
Filing Date: 2001-03-13
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory cell regions each being constituted by a particular memory cell;a plurality of word lines for selecting memory cells;a word line drive circuit for activating, based on an address signal input from outside said semiconductor memory, one of said plurality of word lines to which a memory cell designated by said address signal is connected;a bit line connected to the memory cell selected by the word line activated for reading data out of said memory cell in a form of a voltage change;a sense amplifier for amplifying a potential difference between two adjoining bit lines forming a bit line pair to thereby output two data voltages respectively corresponding to said two bit lines;a sense amplifier precharge circuit for charging, before said sense amplifier starts amplifying the potential difference, a power supply line and a ground line, which feed a voltage to said sense amplifier, to a preselected voltage; anda drive circuit for feeding to a gate of a first n-channel MOS transistor and a gate of a second n-channel MOS transistor included in said sense amplifier precharge circuit a control signal of a preselected high-level voltage from a third n-channel MOS transistor, wherein said first and second n-channel MOS transistors feed a precharge current output from a precharge power supply to said power supply line and said ground line, respectively.