Patent ID: 7530003
Filing Date: 2009-05-05
Classification: H03M

Abstract:
1. A system for processing data, the system comprising: a maximum transition run or timing-varying maximum transition run (hereinafter MTR) encoder configured to encode input data sequence from a hard disk controller into an MTR coded sequence which satisfies a j-constraint; an error correction code (ECC) encoder configured to generate ECC check bits for the MTR coded sequence; and a bit-level interleaving and substitution module configured to interleave the generated ECC check bits into the MTR coded sequence by stuffing the generated ECC check bits at boundaries of MTR coded blocks of the MTR coded sequence, to determine if a violation of the j-constraint has occurred at the boundaries of the MTR coded blocks, and to perform substitution of bits at a boundary of the MTR coded blocks to maintain the j-constraint if a violation of the j-constraint has occurred at the boundary; wherein the j-constraint is satisfied when a long string of consecutive ones and zeros are removed.