Patent ID: 7526742
Filing Date: 2009-04-28
Classification: G06F

Abstract:
1. A test environment for performing verification on a parameterizable circuit design comprising: a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization; a hardware verification language shell configured to randomly generate signals which indicate one of said instances and provide the signals to said test harness, wherein said test harness selects one of said instances according to the signals; a software construct communicatively linked with said first and second instances, wherein said software construct selectively passes output from one of said first or second instances to said hardware verification language shell according to a signal received by said software construct from said hardware verification language shell; and a plurality of transactors, wherein each of said instances is associated with one of said plurality of transactors, wherein said plurality of transactors convey signals from said hardware verification language shell to said first and second instances.