Patent ID: 6833735
Filing Date: 2004-12-21
Classification: H03K

Abstract:
A complementary metal oxide semiconductor (CMOS) low-power high speed logic circuit for processing input data signals that change at pre-defined times, said logic circuit comprising a chain of logic gates comprising:a pulsed domino logic first stage having one or more logic signal inputs for processing selected ones of said input data signals, a logic output, and a timing input for receiving a clocking pulse, said clocking pulse conditioning said logic signal inputs for evaluation; and a sequence of series-connected skewed static logic gates connected to said logic output of said pulsed domino logic first stage, each of said skewed static logic gates having a first logic input connected to the preceding logic gate in said chain and having zero or more additional logic inputs for processing selected ones of said input data signals, wherein said sequence of series-connected skewed static logic gates exhibit alternating fast rise and fast fall times from gate to gate in said sequence.