Patent ID: 6031405
Filing Date: 2000-02-29
Classification: H01L,H03K

Abstract:
An electrostatic discharge protection circuit to be positioned at an IC pad for preventing an internal circuit within an integrated circuit from ESD damage, the electrostatic discharge protection circuit comprising: a lateral silicon-controlled rectifier circuit coupled between said IC pad and a grounding node to provide electrostatic discharge through an ESD path; andan ON/OFF controller arranged in said conduction path; said ON/OFF controller disconnecting said ESD path during normal operation, said ON/OFF controller including:a PMOS transistor having a source and a drain connected to a cathode of said silicon-controlled rectifier and said grounding node, respectively;a resistor connected between a gate of said transistorand a powering node; anda capacitor connected between said gate of said transistor and said grounding node.