Patent ID: 8716085
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method of fabricating a high-voltage semiconductor device, the method comprising: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; substantially filling each groove with a charge compensation plug of the first conductivity type; and forming a plurality of wells of the second conductivity type in the semiconductor layer such that each well forms a PN junction with a corresponding charge compensation plug and with two pillars adjacent to the corresponding charge compensation plug and contacts a corresponding charge compensation layer on opposing sidewalls of the two pillars.