Patent ID: 7183158
Filing Date: 2007-02-27
Classification: H01L,Y10S

Abstract:
1. A method for fabricating nonvolatile memory device, comprising: providing a substrate, having at least a memory cell region and a periphery circuit region; forming a first bottom dielectric layer over the memory cell region, and a second bottom dielectric layer over the periphery circuit region, a thickness of the second bottom dielectric layer is greater than a thickness of the first bottom dielectric layer; forming a charge trapping layer over the substrate; forming a top dielectric layer over the charge trapping layer; forming a conductive layer over the top dielectric layer; forming a patterned mask layer over the conductive layer; removing portions of the conductive layer, the top dielectric layer, the charge trapping layer, the first bottom dielectric layer, the second bottom dielectric layer and the substrate using the patterned mask layer as a mask, to form a first gate electrode structure at the memory cell region and a second gate electrode structure at the periphery circuit region and a plurality of trenches in the substrate; filing an insulation layer into the trench; and removing the patterned mask layer and a portion of the insulation layer until the conductive layer is exposed, so as to form the device isolation structure; and forming source/drain regions adjacent to the first gate electrode structure and the second gate electrode structure.