Patent ID: 6790707
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method of preparing a sample of a semiconductor structure for adhesion testing, comprising:a) providing a first semiconductor structure comprising at least one layer of additive material overlying a first crystalline semiconductor substrate, wherein said at least one layer of additive material is different from said crystalline substrate; b) providing a second semiconductor structure comprising a second crystalline semiconductor substrate, wherein said second semiconductor substrate is the same material as said first semiconductor substrate; c) providing an adhesive on an exposed surface of said at least one layer of additive material; d) aligning said first semiconductor structure and said second semiconductor structure crystalline lattice structures, with an exposed surface of said at least one layer of additive material in contact with an exposed surface of said second semiconductor structure, with a layer of said adhesive between said additive material layer and said second semiconductor structure; e) curing said adhesive, to bond said exposed surface of said at least one layer of additive material to said exposed surface of said second semiconductor structure, whereby a bonded sandwich structure is formed; f) making at least one scribe extending across an edge portion of an exposed upper surface of said first crystalline semiconductor substrate, and downward across an exposed side surface of said first crystalline semiconductor substrate, an exposed side surface of said at least one layer of additive material, and at least a portion of an exposed side surface of said second crystalline semiconductor substrate; and g) breaking said bonded sandwich structure along a crystalline lattice structure direction to form at least one test specimen.