Patent ID: 6667217
Filing Date: 2003-12-23
Classification: H01F,H01L

Abstract:
A method of integrating the fabrication of a thick, damascene type copper inductor structure completely inlaid in a dielectric layer, and of complimentary metal oxide semiconductor, (CMOS), devices, on a semiconductor substrate, comprising the steps of:providing a CMOS device region, on a first region of said semiconductor substrate, to be used for said CMOS devices, and providing an inductor region, in a second region of said semiconductor substrate, to be used for said thick, copper inductor structure; forming a first intermetal dielectric, (IMD), layer; forming openings in said first IMD layer to expose underlying conductive regions in said CMOS device region, and to expose underlying conductive regions in said inductor region; forming a first sub-metal structure, on said first IMD layer, in said CMOS device region, with said first sub-metal structure contacting said underlying conductive regions, in said openings in said first IMD layer, and forming a second sub-metal structure, on said first IMD layer, in said inductor region; depositing a second IMD layer; forming a first photoresist shape, on said second IMD layer, with an opening in said first photoresist shape exposing a portion of the top surface of said second IMD layer, in said inductor region; removing the region of said second IMD layer, exposed in said opening in said first photoresist shape, creating an inductor opening in said second IMD layer, exposing a portion of the top surface of said second sub-metal structure; using a second photoresist shape as a mask to create damascene type openings in said second IMD layer, exposing portions of the top surface of said first sub-metal structure in said CMOS device region, with said second photoresist shape completely covering the portion of top surface of said second sub-metal structure exposed in said inductor opening; removing said second photoresist shape and performing a post photoresist wet clean procedure; forming a titanium nitride layer on top surface of said second sub-metal structure; forming a thin copper layer via chemical vapor deposition (CVD), or via physical vapor deposition (PVD) procedures, on said titanium nitride layer; depositing a thick copper layer via electro-chemical deposition (ECD) procedures, completely filling said inductor opening, in said inductor region, and completely filling said damascene type openings, in said CMOS device region; and removing regions of said thick copper layer from the top surface of said second IMD layer to form copper interconnect structures, in said damascene type openings, overlying and contacting said first sub-metal structure, in said CMOS region, and forming said thick, damascene type copper inductor structure, in said inductor opening, overlying and contacting, said second sub-metal structure, in said inductor region.