Patent ID: 7969230
Filing Date: 2011-06-28
Classification: H02M

Abstract:
1. A voltage generating circuit comprising: a power supply input node; an output terminal node; and a multi-stage charge pump booster circuit disposed between the power supply input node and the output terminal node, wherein the multi-stage charge pump booster circuit includes plural charge transfer switches connected in series between the power supply input node and the output terminal node, forming two or more lines of charge transfer circuits that are operated by clock signals that are out of phase with each other, the multi-stage charge pump booster circuit further including capacitors connected on one end to nodes of the charge transfer circuits and driven on another end by the out-of-phase clock signals, wherein the charge transfer circuits include a first control unit, a second control unit, and a voltage comparison output unit, the first control unit including a charge transfer switch comprising a NMOS transistor configured to transfer a charge from the power supply input node to each of the capacitors in a first-stage, the second control unit including a charge transfer switch comprising an NMOS transistor configured to transfer a charge from a predetermined one of the capacitors in the first stage to the capacitor in a next stage, the second control unit further including a switch unit configured to selectively supply a signal from a node of the previous stage or a subsequent stage to the gate terminal of the charge transfer switch of the second control unit, depending on the phase of the clock signal, and the voltage comparison output unit including a charge transfer switch comprising a PMOS transistor configured to transfer a charge from each of the capacitors in a final stage to the output node, the switching unit of the second control unit includes a first switch element and a second switch element connected in series for each of a first and charge transfer circuit and a second charge transfer circuit, wherein, in the first charge transfer circuit, the NMOS transistor of the second control unit is connected at a gate terminal thereof to a node between the first and the second switch elements, at a source terminal thereof and a substrate terminal to an input-side node of the first charge transfer circuit via which a charge is transferred from the capacitor in the previous stage, and at a drain terminal thereof to an output side node of the first charge transfer circuit via which a charge is transferred to the capacitor in the subsequent stage, wherein, in the second charge transfer circuit, the NMOS transistor of the second control unit is connected at a gate terminal thereof to a node between the first and the second switch elements, at a source terminal thereof and a substrate terminal to an input-side node of the second charge transfer circuit via which a charge is transferred from the capacitor in the previous stage, and at a drain terminal thereof to an output side node of the second charge transfer circuit via which a charge is transferred to the capacitor in the subsequent stage, wherein, in the first charge transfer circuit, the first switch element of the switch unit of the second control unit is connected to the input-side node of the first charge transfer circuit, and the second switch element of the switch unit is connected to the output side node of the second charge transfer circuit, and wherein, in the second charge transfer circuit, the first switch element of the switch unit of the second control unit is connected to the input-side node of the second charge transfer circuit, and the second switch element of the switch unit is connected to the output side node of the first charge transfer circuit, wherein the first switch element comprises a switch NMOS transistor and the second switch element comprises a switch PMOS transistor, wherein, in the first charge transfer circuit, the switch NMOS transistor for the first switch element is connected at a source terminal thereof and a substrate terminal to the input-side node of the first charge transfer circuit, at a gate terminal thereof to the input-side node of the second charge transfer circuit, and at a drain terminal thereof to a drain terminal of the PMOS transistor forming the second switch, the PMOS transistor forming the second switch element is connected at a source terminal thereof and a substrate terminal to the output side node of the second charge transfer circuit, and at a gate terminal thereof to the output side node of the first charge transfer circuit, and wherein, in the second charge transfer circuit, the switch NMOS transistor for the first switch element is connected at a source terminal thereof and a substrate terminal to the input-side node of the second charge transfer circuit, at a gate terminal thereof to the input-side node of the first charge transfer circuit, and at a drain terminal thereof to the drain terminal of the PMOS transistor forming the second switch, and the PMOS transistor forming the second switch is connected at a source terminal thereof and a substrate terminal to the output side node of the first charge transfer circuit, and at a gate terminal thereof to the output side node of the second charge transfer circuit.