Patent ID: 6172421
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A semiconductor device, said device comprising:(a) a semiconductor substrate;(b) at least one trench formed in said semiconductor substrate, each of said at least one trench having a floor surface and a plurality of wall surfaces;(c) a barrier material layer coated on said floor surface and said plurality of wall surfaces, said barrier material layer being a barrier material selected from the group consisting of tantalum, tantalum nitride, and titanium nitride;(d) at least one copper interconnect disposed over said barrier material layer, said at least one copper interconnect having an upper surface and a lower surface, said lower surface being disposed adjacent lo said barrier material layer; and(e) a copper titanide protective intermetallic layer formed on said upper surface of said copper interconnect by annealing in an inert atmosphere, andwhereby said barrier material layer and said copper titanide protective intermetallic layer prevent oxidation of said copper interconnect.