Patent ID: 6943719
Filing Date: 2005-09-13
Classification: H03M

Abstract:
1. A signal processing circuit comprising: an analog integrated circuit having a first input terminal that receives a first-level analog signal during a first active period of a first switching signal and a second input terminal that receives a time varying reference signal, the first input terminal being coupled to a data line to receive a second-level analog signal corresponding to image charges of an image input element during a second active period of the first switching signal; an inverter circuit that inverts and amplifies an output of said analog integrated circuit in response to an activated enable signal; and an output circuit that generates a digital word indicative of a time period defined by a start signal and an end signal corresponding to a transition of an output of said inverter circuit, wherein the enable signal is deactivated between an end point of the first active period and an end point of the second active period of the first switching signal.