Patent ID: 8316242
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. An electronic circuit made in integrated form, comprising: a first data storage RAM; a second RAM in which a key is stored, said data being encrypted by implementation of said key; a processing unit configured to perform a deleting operation in the first RAM; an access terminal connected to the processing unit and receiving a first power supply signal provided by a first power supply source external to the electronic circuit; and a second power supply source integrated to the electronic circuit and configured to provide a second power supply signal to the processing unit, the processing unit being configured to detect that an unauthorized access attempt is occurring based on comparison of the first and second power supply signals and to delete said key while the processing unit is powered by the second power supply source, wherein the processing unit comprises MOS transistors, wherein the second power supply source corresponds to stray capacitances of the MOS transistors, and wherein the storage capacity of the second RAM is smaller than the storage capacity of the first RAM.