Patent ID: 8065546
Filing Date: 2011-11-22
Classification: G06F,H05B,Y02B,Y02D

Abstract:
1. An electronic device having a low power sleep mode, comprising: circuits capable of being placed in a sleep mode; input-output (I/O) capable of being placed in the sleep mode, the I/O coupled to the circuits; sleep/wake-up logic for controlling when the circuits and the I/O are in the sleep mode or in an operational mode; a frequency differentiator having an output coupled to the circuits, the output presenting output values representative of frequencies at an input of the frequency differentiator; an external frequency source connection adapted for coupling to an external frequency source and coupled to the input of the frequency differentiator; wherein the frequency differentiator output is at a first output value when the external frequency source is at a first frequency, and the frequency differentiator output is at a second output value when the external frequency source is at a second frequency; and a watchdog timer coupled to the sleep/wake-up logic, wherein the watchdog timer periodically causes the sleep/wake-up logic to wake up the circuits and the I/O from the sleep mode to the operational mode for a certain time so that the circuits can sample the output values from the frequency differentiator, wherein when a present output value sample is different than a prior output value sample, then the circuits and the I/O will remain in the operational mode.