Patent ID: 6526525
Filing Date: 2003-02-25
Classification: G06F

Abstract:
A PCI debugging device for debugging a system with a PCI interface, wherein the PCI interface includes a request signal, a grant signal and a target ready signal, and the system has a debug mode such that current grant signal is retained as long as the request signal is activated, the PCI debugging device comprises of:a switching circuit for setting a wait-to-debug signal; a system data display circuit coupled to the PCI interface for displaying data on the PCI interface and sending an instantaneous command signal out; a decoding comparator circuit coupled to the switching circuit and the system data display circuit for decoding the instantaneous command signal and comparing with the wait-to-debug command signal, and then generating an identical command signal; and a latch circuit with reset capability coupled to the decode comparator circuit for latching the identical command signal and activating the request signal.