Patent ID: 6255221
Filing Date: 2001-07-03
Classification: H01L,Y10S

Abstract:
A method for etching dielectric layers in a high density plasma etcher, comprising:providing a wafer having a dielectric layer disposed over transistor devices, the transistor devices including transistor gate oxides and gate electrodes, and diffusion regions;forming a photoresist mask over the dielectric layer in order to define at least one contact via hole over one of the diffusion regions;inserting the wafer into the high density plasma etcher;ascertaining an etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;setting up gas flow conditions, temperature conditions and pressure conditions within the high density plasma etcher;selecting a duty cycle of a pulse application of a TCP source of the high density plasma etcher;pulse applying the TCP power source;scaling a peak power of the pulse application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source, wherein the scaling is designed to vary the peak power of the pulse application of the TCP source inversely to the duty cycle; andapplying an RF bias to a bottom electrode of the high density plasma etcher;wherein the pulse applying of the TCP power source is configured to etch through the dielectric layer to define the at least one contact via hole over one of the diffusion regions while substantially reducing damage to the transistor gate oxides of the transistor devices.