Patent ID: 8660170
Filing Date: 2014-02-25
Classification: H03M

Abstract:
1. A circuit for correcting the quadrature phase error between the in-phase and quadrature sampling clocks in a quadrature bandpass-sampling receiver comprising: a quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) configured to a sampling clock generator configured to generate an in-phase sampling clock, having an in-phase sampling clock frequency; a ninety-degree phase shifter configured to a discrete Fourier transform (DFT) block configured to an integrator configured to a symbol clock generator configured to generate a symbol clock, having a symbol clock frequency; an in-phase/quadrature (I/Q) mismatch calculator configured to a test tone generator configured to generate a first multiplier configured to multiply the in-phase test tone with the in-phase sampling clock to generate an up-converted in-phase test tone; a second multiplier configured to multiply the quadrature test tone with the quadrature sampling clock to generate an up-converted quadrature test tone; a first digital-to-analog (D/A) converter configured to receive the up-converted in-phase test tone to generate a in-phase analog test tone; and a second D/A converter configured to receive the up-converted quadrature test tone to generate a quadrature analog test tone; wherein