Patent ID: 9036397
Filing Date: 2015-05-19
Classification: G11C,H01L

Abstract:
1. A resistive memory array, comprising: a plurality of resistive memory units arranged in rows and columns, wherein each of the resistive memory units comprises a first memory cell, and a second memory cell disposed under and electrically connected in series with the first memory cell, wherein each of the resistive memory units includes: a first solid electrolyte, being a part of the first memory cell; a second solid electrolyte, being a part of the second memory cell; and an oxidizable electrode, formed between the first solid electrolyte and the second solid electrolyte, wherein the first solid electrolyte and the second solid electrolyte are made of a transition metal oxide or a material containing at least one chalcogenide element; a plurality of word lines, wherein each of the word lines is coupled to the first memory cells of a row of the resistive memory units; and a plurality of bit lines, wherein each of the bit lines is coupled to the second memory cells of a column of the resistive memory units.