Patent ID: 6845557
Filing Date: 2005-01-25
Classification: H01L,H05K,Y10T

Abstract:
1. A method for producing an electronic package possessing controlled impedance characteristics, said method comprising the steps of: providing a first substrate consisting of a dielectric material; applying a first conductive layer on at least one surface of said substrate, said first conductive layer having a first thickness; plating a second conductive layer on said first conductive layer, said second conductive layer having a thickness greater than the thickness of said first conductive layer; reducing the thickness of said second conductive layer to form a thickness which in combination with the first thickness of said first conductive layer is less than the initial thickness of said second conductive layer; laminating a second dielectric substrate to said first substrate so as to cause said conductive layers to comprise an innerlayer intermediate said laminated substrate; drilling holes into said laminate substrate, and plated conductive material in said holes, said holes comprising selectively plated through holes, deep blind holes and buried holes forming vias in said laminated substrates; and filling at least some of said holes with a dielectric material or solder to prevent thinning of the plated conductive material in said holes during external etching and thinning of conductive material on external surfaces of said laminated substrates.