Patent ID: 6737710
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A microelectronic structure comprising:a substrate; a gate electrode formed over the substrate and defining an underlying channel region in the substrate, said gate electrode having a barrier layer formed on a sidewall of the gate electrode to prohibit the silicidation of the sidewall; a source/drain extension formed in the substrate adjacent the gate electrode and encroaching laterally into the underlying channel region a first distance, the source/drain extension having a first silicide layer formed therein, the first silicide encroaching laterally into the underlying channel region a second distance less than the first distance; and a source/drain region formed in the substrate adjacent the source/drain extension and having an activated doped region with a second silicide layer disposed therein, both the activated doped region and the second suicide layer are aligned with a spacer disposed along sidewalls of the gate electrode such that both the activated doped region and the second silicide layer encroach laterally into the underlying channel region a third distance due to alignment with the spacer disposed along the sidewalls, the third distance less than the second distance, said source/drain extension having less dopant concentration than the activated doped region.