Patent ID: 7180341
Filing Date: 2007-02-20
Classification: H03K

Abstract:
1. A variable division method characterized by comprising: the signal processing step of forming a clock signal before division by inverting/without inverting an input clock signal applied to an input terminal in accordance with a level of a signal applied to a control terminal, dividing the clock signal before division by a predetermined frequency division number on the basis of a change point, which corresponds to a change point in one direction of the input clock signal, in a clock pulse having a pulse width larger than a predetermined pulse width in the clock signal before division, and outputting the frequency-divided signal as an output clock signal from an output terminal; the step of connecting/disconnecting, in accordance with an external control signal, a feedback path which is formed between the output terminal and control terminal and functions as a path of a signal to be returned to the control terminal; and the delay step of making a delay time during which a signal applied to the input terminal is returned to the control terminal through the feedback path larger than a pulse width of the input clock signal.