Patent ID: 6137320
Filing Date: 2000-10-24
Classification: G11C

Abstract:
An input receiver circuit comprising:a first N channel MOS transistor having a gate supplied with an activation signal and a source connected to a ground potential;a second N channel MOS transistor having a gate supplied with said activation signal and a source connected to the ground potential;a third N channel MOS transistor having a gate supplied with a first signal and a source connected to a drain of said first N channel MOS transistor;a fourth N channel MOS transistor having a gate supplied with a second signal and a source connected to a drain of said second N channel MOS transistor;a node;a fifth N channel MOS transistor having a source connected to the source of said third N channel MOS transistor, a drain connected to a drain of said third N channel MOS transistor, and a gate connected to said node;a sixth N channel MOS transistor having a source connected to the source of said fourth N channel MOS transistor, a drain connected to a drain of said fourth N channel MOS transistor, and a gate connected to said node;a first P channel MOS transistor having a source supplied with a power source voltage, a drain connected to the drain of said third N channel MOS transistor, and a gate connected to said node; anda second P channel MOS transistor having a source supplied with the power source voltage, a drain connected to the drain of said fourth N channel MOS transistor, and a gate connected to said node, the second P channel MOS transistor outputting a drain voltage as an output signal.