Patent ID: 7999367
Filing Date: 2011-08-16
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a buffer chip comprising a plurality of base bond pads receiving externally provided write data and providing read data, wherein the buffer chip comprises a plurality of base through silicon vias (TSVs) respectively connected to the plurality of base bond pads, and a plurality of solder balls respectively connecting the plurality of base TSVs to a substrate mounting the device; a first memory chip comprising first bond pads and being seated in a central portion of a first interposer chip, the first interposer chip being larger in area than the first memory chip and comprising second bond pads respectively connecting the first bond pads of the first memory chip, and a plurality of TSVs formed proximate at least one edge of the first interposer chip; a second memory chip comprising first bond pads and being seated in a central portion of a second interposer chip, the second interposer chip being larger in area than the second memory chip and comprising second bond pads respectively connecting the first bond pads of the second memory chip, and a plurality of TSVs formed proximate at least one edge of the second interposer chip and respectively connected via vertical connection elements to the plurality of TSVs in the first interposer chip, wherein the first interposer is stacked on the second interposer and the plurality of TSVs in the second interposer chip are respectively connected to the plurality of base bond pads, the first and second memory chips are memory core chips, and the buffer chip is an interface chip comprising: