Patent ID: 6081858
Filing Date: 2000-06-27
Classification: H03K

Abstract:
A waveform signal regulating circuit comprising:a sample-and-hold circuit receiving as input a transaction activity waveform signal;a latch coupled to the sample-and-hold circuit, the latch generating a regulated waveform signal at an output;wherein the sample-and-hold circuit detecting whether there is an on-going transaction activity, if there is an on-going transaction activity, the sample-and-hold detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a first state in the regulated waveform signal for at least N clock cycles thereby controlling a pulse width, if there is no on-going transaction activity, the sample-and-hold circuit detecting whether a pulse is occurring in the regulated waveform signal, if a pulse is not occurring in the regulated waveform signal, the sample-and-hold circuit signaling the latch to assert a second state in the regulated waveform signal for at least M clock cycles thereby controlling a gap between two pulses;wherein the sample-and-hold circuit comprises a first counter coupled to the latch, the first counter monitoring a first count in response to the regulated waveform signal, the first counter generating a signal having the first state while the first count is less than the value N, the first counter generating the signal having a second state when the first count reaches the value N; a second counter coupled to the latch, the second counter monitoring a second count in response to a complementary of the regulated waveform signal, the second counter generating a signal having the first state while the second count is less than the value M, the second counter generating the signal having the second state when the second count reaches the value M; and a switching circuit receiving as inputs the waveform signal and the signals generated by the first and second counters, the switching circuit outputting first and second output signals generated by the first and second counters, the first and second output signals from the switching circuit provided as inputs to the latch; wherein the first and second counters start the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are HIGH, the first and second counters reset the first and second counts when the regulated waveform signal and the complementary of the regulated waveform signal are LOW; and wherein the switching circuit comprises an AND-gate receiving as inputs the waveform signal and an invert of the signal generated by the second counter, the AND-gate providing as output the first output signal of the switching circuit; and a NOR-gate receiving as inputs the waveform signal and the signal generated by the first counter, the NOR-gate providing as output the second output signal of the switching circuit.