Patent ID: 8874881
Filing Date: 2014-10-28
Classification: G06F

Abstract:
1. A method comprising: performing by a first subcircuitry a multi-byte non-branch instruction that includes determining, by a first portion of the first subcircuitry, a first sign extended value of a first immediate field associated with a multi-byte non-branch instruction using first subcircuitry, wherein the first portion of the first subcircuitry is operable to only perform sign extension; and performing by the first subcircuitry a multi-byte branch instruction, the branch instruction having a different multi-byte alignment from the non-branch instruction, by determining, by said first portion of the first subcircuitry, a second sign extended value of a second immediate field associated with the multi-byte branch instruction and calculating a target address by adding the second sign extended value of the second immediate field to a program counter value, wherein the multi-byte branch instruction is performed without first performing a multiplication with the second immediate field, wherein the first subcircuitry is used to determine the second sign extended value and calculate the target address even if the target address contains a byte aligned instruction or a multi-byte aligned instruction, and wherein determining the first sign extended value and determining the second sign extended value are both performed using the same first portion of the first subcircuitry.