Patent ID: 6724667
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A data memory for storing data, comprising:a) a memory cell array, which comprises a large number of memory cells, each of which can be addressed by means of a memory cell select transistor connected to a word line and to a bit line and which have a storage capacity for storing one data bit, b) the memory cell array containing redundant memory cells, which are provided in order to replace memory cells which have been produced wrongly, by means of readdressing, and having c) read amplifiers, which are in each case provided for the signal amplification of a data bit read from an addressed memory cell via an associated bit line and are supplied with a buffered supply voltage, d) select transistors of the redundant memory cells which have not been readdressed being turned on in order that storage capacity of the redundant memory cells is connected to the associated bit lines for additionally buffering the supply voltage for the read amplifiers.