Patent ID: 6713793
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A semiconductor device comprising:a compound semiconductor substrate having a first surface and a second sure, the compound semiconductor substrate being electrically isotropic in two mutually orthogonal directions; first, second, and third active regions on the first surface of the substrate, the first and second active regions being separated by a first insulating region and the second and third active regions being separated by a second insulating region; a first semiconductor element including first, second, and third channel regions serially connected, adjacent channel regions having width directions essentially perpendicular to each other, a first source electrode and a first drain electrode, adjacent to the first, second, and third channel regions and opposing each other with the first, second, and third channel regions therebetween, and in ohmic contact with the first second, and third active regions, and a first gate electrode disposed on the first, second, and third channel regions and along the first source electrode and the first drain electrode, and bent at first and second bending positions; and a second semiconductor element on the first, second, and third active regions adjacent to the first semiconductor element, including fourth, fifth, and sixth channel regions serially connected, adjacent channel regions having width directions essentially perpendicular to each other, the fourth, fifth, and sixth channel regions being adjacent to the first, second, and third channel regions, respectively, with one of the first source electrode and the first drain electrode therebetween, a second source electrode and a second drain electrode in ohmic contact with the first, second, and third active regions, one of the second source electrode and the second drain electrode and opposing the first drain electrode or the first source electrode across the fourth, fifth, and sixth channel regions, and a second gate electrode on the fourth, fifth, and sixth channel regions and along one of the second source electrode and the second drain electrode, and bent at third and fourth bending positions, wherein the first insulating region is under the fist and third bending positions of the first and second gate electrodes, and the second insulating region is under the second and fourth bending positions of the first and second gate electrodes.