Patent ID: 6697040
Filing Date: 2004-02-24
Classification: G02F,G09G,H05K

Abstract:
A liquid crystal display device comprising:a liquid crystal panel formed by bonding a first substrate to a second substrate, said first substrate has a plurality of drain lines, a plurality of gate lines intersecting said plurality of drain lines, and a plurality of pixels each having a switching element controlled by one of said plurality of gate lines and receiving one of gray scale voltage signals from one of said plurality of drain lines, and said second substrate has color filters; a plurality of drain drivers arranged in an extending direction of said plurality of gate lines, for applying said gray scale voltage signals to said plurality of pixels so arranged as to correspond to predetermined groups of said plurality of drain lines on the basis of display data signals; a plurality of gate drivers arranged in an extending direction of said plurality of drain lines, for applying scanning voltage signals to said plurality of pixels arranged along said plurality of drain lines; a timing converter for generating said display data signals and a pixel clock signal on the basis of a display signal and a timing signal inputted from outside; lines directly formed on said first substrate, for serially transferring in series said display data signals, said gray scale voltage signals and said pixel clock signal to and between said plurality of drain drivers, wherein each of said plurality of drain drivers acquires said display data signals inputted thereto in response to said pixel clock signals, and includes gate circuits disposed on output sides of said display data signals and on an output side of said pixel clock signal thereof, said gate circuits inhibit the transfer of said display data signals and said pixel clock signal to display data lines and to a pixel clock line of another of a following stage while one of said plurality of drain drivers including said gate circuits acquires said display data signals, and start the transfer of said display data signal and said pixel clock signal to the following stage when acquisition of said display data signals by said one of said plurality of drain drivers is finished.