Patent ID: 7439603
Filing Date: 2008-10-21
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: at least two deep trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, wherein the deep trench isolation layers comprise sidewalls having vertical profiles; a first conductive type well arranged between the at least two deep trench isolation layers to have a second depth smaller than the first depth and a width equal to the width of the deep trench isolation layers; a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between; an ONO layer on the channel region of the semiconductor substrate and on the at least two deep trench isolation layers, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer; and a wordline conductor layer on the ONO layer.