Patent ID: 7885131
Filing Date: 2011-02-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory array including a plurality of memory cells and a reference cell each of which has a memory element that stores data based on change in resistance value; a plurality of read circuits configured to read respective data of a plurality of selected cells that are selected from said plurality of memory cells; and a first current-voltage conversion circuit provided at a subsequent stage of a decoder relating to selection of said plurality of selected cells and configured to output a reference voltage corresponding to a reference current flowing through said reference cell, wherein said first current-voltage conversion circuit distributes said reference voltage to said plurality of read circuits in common, wherein each of said plurality of read circuits includes: a second current-voltage conversion circuit provided at a subsequent stage of said decoder and configured to output a sense voltage corresponding to a sense current flowing through a coupled one of said plurality of selected cells; a voltage comparison unit configured to compare said sense voltage with said reference voltage; a first switch circuit provided between said first current-voltage conversion circuit and said voltage comparison unit, the first switch circuit controlling connection between said first current-voltage conversion circuit and said voltage comparison unit by switching on or off; and a second switch circuit provided between said second current-voltage conversion circuit and said voltage comparison unit, said second switch circuit controlling connection between said second current-voltage conversion circuit and said voltage comparison unit by switching on or off.