Patent ID: 8487477
Filing Date: 2013-07-16
Classification: H02J

Abstract:
1. A system comprising: a communication bus; and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing configuration in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output voltage, and a respective output current according to at least the generated respective output voltage, wherein each POL regulator has a respective phase in the current sharing configuration, wherein each POL regulator is configured to transmit and receive information over the bus according to a bus communication protocol corresponding to the bus; wherein each POL regulator of the plurality of POL regulators is configured to: during the output voltage ramp period, modulate a duty cycle of a gate signal controlling a low-side field effect transistor (GL) of the output stage of the POL regulator.