Patent ID: 7120221
Filing Date: 2006-10-10
Classification: G11C

Abstract:
1. A shift register having a plurality of stages for shifting an input start pulse using first and second driving voltages and first and second clock signals to apply the shifted start pulse as each output signal and a next stage start pulse, each of the plurality of stages comprising: an output buffer for applying the first clock signal to an output line under control of a first node and for applying the second driving voltage to the output line under control of second and third nodes; a first node controller for controlling the first node using the start pulse and an output signal of the next stage; a second node controller for selectively applying a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals; a third node controller for applying the voltage at the fourth node and the second driving voltage to the third node that is opposite to the second node under control of the first and second clock signals; and a fourth node controller for controlling the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.