Patent ID: 6600345
Filing Date: 2003-07-29
Classification: G06F,H03K,H04L

Abstract:
A clock selection circuit, the circuit switching between a plurality of possible clocks, a switch made from an existing clock to a new frequency clock in synchronization with both existing and new frequency clocks, the clock selection circuit comprising:a first clock input to receive the existing clock as input; a new frequency clock input to receive the new frequency clock; first synchronization logic associated with the first clock input to enable/disable output of the existing clock, said first synchronization comprises a first set of one or more cascaded flip-flops, each of the flip-flops clocked by the existing clock signal; second synchronization logic associated with the new frequency clock to enable/disable output of the new frequency clock, said second synchronization comprises a second set of one or more cascaded flip-flops, each of the flip-flops clocked by the second clock signal; wherein the first synchronization and second synchronization logic cooperating to disable output of the existing clock synchronously to the existing clock and to enable output of the new frequency clock synchronously to the new frequency clock; and a power control logic to control clocking of the first and second sets of flip-flops such that the first and second sets of flip-flops are not clocked unless the first clock is being disabled and the new clock is being enabled.