Patent ID: 8719593
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A secure processing device comprising: an external memory storing encrypted data; and at least one processor cooperating with said external memory and comprising a processing unit, an address bus coupled to said processing unit, a keystream cache coupled to said address bus, a summer coupled to said keystream cache, and an encryption engine coupled to said address bus and having a key input thereto to generate a plurality of keystreams; said processing unit configured to generate a plurality of address requests for the encrypted data in said external memory, said address bus configured to provide in parallel the plurality of address requests to said keystream cache and said encryption engine, each address request comprising a keystream index value and a tag value; said keystream cache configured to cache the plurality of keystreams based upon an encryption key; said summer configured to generate decrypted plaintext based upon the cached plurality of keystreams and the encrypted data requested from said external memory; and said processing unit configured to predict a plurality of future address requests, and generate a sequential range of keystream data for a plurality of addresses based upon the cached plurality of keystreams.