Patent ID: 6521539
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method for forming a patterned microelectronic layer comprising:providing a substrate; the substrate being a first lower microelectronic layer; forming over the first lower microelectronic layer a multi-layer stack layer comprising: a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant; forming an encapsulating layer upon the first lower microelectronic layer, encapsulating the first lower microelectronic layer and at least a portion of the second intermediate patterned microelectronic layer, while leaving exposed at least a portion of the third upper microelectronic layer; etching selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated within the encapsulating layer; and stripping, while employing a second etch method which employs a second etchant, the encapsulating layer from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer encapsulated by the encapsulating layer.