Patent ID: 6253314
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A computer-implemented data processing method for a microcomputer having a flag register, comprising the steps of:loading a first instruction code belonging to a first instruction subset, the first instruction code specifying an operation on an operand of a first size;loading a second instruction code belonging to a second instruction subset, said second instruction code comprising a common prefix code appended to the first instruction code belonging to the first instruction subset as one of a higher order and lower order portion of the second instruction code, said second instruction code belonging to the second instruction subset specifying the operation on another operand of a second size, other than the first size; andexecuting the first instruction code belonging to the first instruction subset or the second instruction code belonging to the second instruction subset to perform the operation upon an operand of the first size or the second size selectively based upon a content of the flag register and presence or absence of the common prefix code.