Patent ID: 8549630
Filing Date: 2013-10-01
Classification: G06F

Abstract:
1. A method for protecting a bus architecture connected to a CPU from a Trojan attack of a master device and a slave device comprising the steps of: (a) securing a conventional address decoder, where the conventional address decoder receives an address signal from the master device and outputs a requested slave select signal to a requested slave device, and where the requested slave device generates a slave response signal, the conventional address decoder being secured by: (b) securing a conventional bus arbiter, where the conventional bus arbiter receives a lock signal from the master device, the lock signal having a lock signal active time, the conventional bus arbiter being secured by: (c) securing a bus matrix, the bus matrix receiving a wait request signal from the slave device having a slave ID, the wait request signal having a wait request active time, the bus matrix being secured by: