Patent ID: 6646324
Filing Date: 2003-11-11
Classification: H01L,Y02P

Abstract:
An apparatus comprising:an insulated gate FET having a gate electrode; the insulated gate FET having a channel disposed beneath the gate electrode; the insulated gate FET having a source doped region adjacent to the channel and electrically coupled to the channel; the insulated gate FET having a drain doped region adjacent to the channel and laterally opposite the source doped region, the drain doped region electrically coupled to the channel; the insulated gate FET having a resistor doped region adjacent to the drain doped region, away from the gate electrode and separated from the drain doped region a distance suitable to linearize the voltage transfer curve of the insulated gate FET, the resistor doped region, the drain doped region and the source doped region formed in a common processing step; the insulated gate FET having a source contact area disposed adjacent to the source doped region away from the gate electrode and electrically coupled to the source doped region; the insulated gate FET having an unlinearized drain contact area disposed between the drain doped region and the resistor doped region and electrically coupled to the drain doped region and to the resistor doped region; and the insulated gate FET having a linearized drain contact area disposed adjacent to the resistor doped region away from the gate electrode and electrically coupled to the resistor doped region.