Patent ID: 6251733
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A manufacturing method of a semiconductor device having a CMOS structure including a complementary n-channel semiconductor device and p-channel semiconductor device, comprising the steps of:forming first impurity regions in a channel forming region of the n-channel semiconductor device and second impurity regions in a channel forming region of the p-channel semiconductor device artificially and locally in a direction approximately parallel with a channel direction;subjecting the n-channel semiconductor device to first means for strengthening a narrow channel effect and subjecting the p-channel semiconductor device to second means for strengthening a short channel effect so as to calculate absolute values of threshold voltages of the n-channel and p-channel semiconductor devices to be approximately equal to each other;wherein the first means is for intentionally narrowing an interval between the first impurity regions; andwherein the second means is for making an interval between the second impurity regions wider than the interval between the first impurity regions.