Patent ID: 6570419
Filing Date: 2003-05-27
Classification: H03K,H03L,H04L

Abstract:
A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock,wherein said clock recovery circuit comprises: an input standard node, to which said external clock is coupled, for supplying a first standard clock; a plurality of first delay circuits, whose initial stage is coupled to said input standard node, for supplying a plurality of reference clocks differing in phase from each other; and a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said first standard clock and detecting the reference clock closest in phase to said first standard clock, and a latch circuit for holding information on said predetermined number of delay stages, wherein said plurality of first delay circuits supply said internal clock correspondingly to said predetermined number of delay stages detected by said control circuit.