Patent ID: 6304939
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A mechanism for cache-line replacement within a cache memory having redundant cache lines, said mechanism comprising:a token for indicating a candidate cache line for cache-line replacement;a plurality of token registers connected in a ring configuration, wherein one of said plurality of token registers contains said token, wherein each of said plurality of token registers is associated with a cache line of said cache memory having redundant cache lines;a plurality of allocation-indicating circuits, wherein each of said plurality of allocation-indicating circuits is associated with one of said plurality of token registers, wherein each of said plurality of allocation-indicating circuits is for indicating whether or not a line-allocation procedure is in progress at an associated cache line;a plurality of bypass circuits, wherein each of said plurality of bypass circuits is associated with one of said plurality of token registers, wherein each of said plurality of bypass circuits is for relocating said token to an adjacent one of said plurality of token circuits in response to said indication from said allocation-indicating circuits; andmeans for replacing a cache line within said cache memory in response to a location of said token.