Patent ID: 6691206
Filing Date: 2004-02-10
Classification: G05B,G06F,G11C,H04N,Y02D

Abstract:
A method of interfacing a host processor bus to a computation engine having a micro-programable memory-centric controller (MCC) and an array of computation memory, the processor bus being coupled to a host processor and to main memory, and the method comprising the steps of:providing a predetermined series of MCC microcode instructions executable by the MCC; storing the MCC microcode instructions in a memory accessible to the MCC; receiving an instruction on the host processor bus; decoding the received instruction on in the MCC to detect an instruction executable on the computation engine; only if the decoded instruction has a corresponding operation executable on the computation engine, selecting a start address within the series of MCC microcode instructions for carrying out the decoded instruction; and executing the series of MCC microcode instructions in the MCC beginning at the selected start address so as to carry out the corresponding operation in the computation engine without using host processor cycles.