Patent ID: 8809174
Filing Date: 2014-08-19
Classification: B82Y,H01L,Y10S

Abstract:
1. A method for forming a field effect transistor comprising: forming a dielectric layer on a semiconductor substrate of a first type; forming a Si layer on said dielectric layer; forming a mask over said Si layer; etching said Si layer and said dielectric layer through said mask to form a sacrificial gate dielectric and a sacrificial Si gate electrode having gate sidewalls on opposite sides of said sacrificial gate dielectric and said sacrificial Si gate electrode; forming a first spacer on said gate sidewalls; implanting ions using said gate electrode and said first spacer as a mask to form a halo, source and drain extensions of a second type in said semiconductor substrate; forming a second spacer on said gate sidewalls; implanting ions using said gate electrode, said first spacer and said second spacer as a mask to form a source and drain of a second type in said semiconductor substrate; annealing said semiconductor substrate to activate said implanted ions; forming a dielectric layer having a first thickness above said substrate at least a height of said sacrificial Si gate electrode; planarizing said dielectric layer down to said sacrificial Si gate electrode; removing said sacrificial gate dielectric and said sacrificial Si gate electrode to form a gate opening; forming a gate dielectric in said gate opening; forming an organic planarization layer over said dielectric layer, said organic planarization layer filling said gate opening; forming a layer of photo resist over said organic planarization layer; forming openings above said source and drain in said layer of photo resist and said layer of organic planarization layer exposing said dielectric layer; forming source and drain openings in said dielectric layer to expose said source and drain; removing said layer of photo resist and said layer of organic planarization layer; forming a layer of metal in said openings in said dielectric layer over said exposed source and drain; annealing said exposed source and drain to form a metal silicide at said source and drain; removing unreacted metal of said layer of metal; forming a first layer of metal in said gate opening, source opening and drain opening having a first work function; forming a second layer of metal over said first layer of metal filling said gate opening, source opening and drain opening; and polishing said second layer of metal and said first layer of metal and down to said dielectric layer to form spaced apart gate, source and drain contacts.