Patent ID: 7979675
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A microprocessor, comprising: a register, configured to store a state; a fetch unit, coupled to said register, configured to fetch instructions of a program, the program including a first instruction followed non-immediately by a second instruction, wherein the first instruction instructs the microprocessor to update the state in the register, wherein the second instruction is a conditional branch instruction that specifies a branch condition based on the state in the register, wherein the fetch unit is configured to dispatch the first instruction for execution but to refrain from dispatching the second instruction for execution; and execution units, configured to receive the first instruction from the fetch unit and responsively update the state in the register; wherein the fetch unit is configured to non-selectively correctly resolve the conditional branch instruction based on the state in the register when the execution units have updated the state in the register, and configured to non-selectively refrain from sending the conditional branch instruction to the execution units to be resolved regardless of whether the execution units have updated the state in the register.