Patent ID: 6922195
Filing Date: 2005-07-26
Classification: G09G

Abstract:
1. An image processing apparatus comprising: a memory circuit storing an input data in response to a write address and outputting an output data in response to a read address; a one-line judging circuit receiving a horizontal synchronization signal and a sampling clock signal, the one-line judging circuit comparing a number of pixels sampled within one line of the horizontal synchronization signal with a predetermined number so as to output a comparison signal and a difference signal representing a difference between the sampled number of pixels and a predetermined number; a write control circuit coupled to the memory circuit and the one-line judging circuit, the write control circuit generating the write address in response to the sampling clock signal and the comparison signal and a read control signal in response to the comparison signal; and a read control circuit coupled to the memory circuit, the write control circuit and the one-line judging circuit, the read control circuit generating the read address in response to the write address, the read control signal and the difference signal.