Patent ID: 7492853
Filing Date: 2009-02-17
Classification: G11C

Abstract:
1. A shift register comprising: a clock terminal and an output terminal; a first transistor configured to supply a clock signal input to said clock, terminal to said output terminal; and second and third transistors both configured to discharge said output terminal, wherein said first, second and third transistors have their control electrodes connected to first, second and third nodes, respectively, said shift register further comprising: a fourth transistor connected between a first control terminal to which a predetermined first control signal is input and said second node; a fifth transistor connected between a second control terminal to which a predetermined second control signal is input and said third node; and a driving circuit configured to alternately drive said second and third transistors on the basis of said first and second control signals, wherein said fourth and fifth transistors each have one main electrode connected to a control electrode of each other in a crossed manner.