Patent ID: 6462373
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device in which a plurality of memory cells are arranged in an array-like configuration to constitute a cell array having a plurality of device isolation regions buried by an insulation material in trenches formed in a semiconductor substrate, and a plurality of device forming regions each of which is divided with the device isolation regions, and in which each of the memory cells includes a floating gate formed via a first gate insulation film on the device forming region, and a control gate formed on the floating gate via a second gate insulation film,wherein at least a portion of the floating gate sandwiched with the device isolation regions has a lower end contacting with a surface of the semiconductor substrate via the first gate insulation film with a width larger than that of an upper end of the sandwiched portion, and the device isolation regions each has a width of 0.25 &mgr;m or less.