Patent ID: 7818545
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. An information processing unit, comprising: an instruction processing section that decodes instruction and issues a processing instruction; an arithmetic unit that carries out operation in accordance with arithmetic instruction issued as said processing instruction from the instruction processing section; an arithmetic register that holds an operation result by the arithmetic unit; store ports that hold a store instruction, which is issued from said instruction processing section as said processing instruction for storing the operation result held in said arithmetic register in a predetermined storage area; store data buffers that temporarily hold said operation result issued as store data from said arithmetic register; wherein said instruction processing section is configured, when said arithmetic register holding said operation result is determined, irrespective of an issuance state of the store instruction to said store ports to cause the operation result to be issued from said arithmetic register to said store data buffers as said store data, in response to the store instruction so that issuance of the store instruction to said store ports and issuance of the store data to said store data buffers are performed out-of-order, and said store ports are configured to hold a store data hold flag, which is set to ON when said store data corresponding to said store instruction are held in said store data buffers, a reset section that sets said store data hold flag to OFF at a point of time when said store instruction is held by said store ports in order to ensure, that when said store data is to be issued to said store data buffers after said store instruction is issued to said store ports, that said store data buffers have not yet retained said store data at a point of time when said store instruction is held by said store ports; and a restraint section that, when said store data are held in said store data buffers before said store instruction is held in said store ports, restrains said reset section from setting said store data hold flag to OFF at a point of time when said store instruction is held in said store ports to maintain said store data hold flag to ON in order to perform the issuing of said store instruction to said ports and the issuing of said store data to said store data buffers in an out-of-order manner; an align section that aligns said operation result issued from said arithmetic register as said store data, in which said instruction processing section is configured, when said instruction processing section causes said operation result stored in said arithmetic register to be issued to said store data buffers to said store data buffers as said store data, to issue an align information necessary for aligning along with the operation result and a usable/unusable information indicating whether the align information is used by said align section; and an align information selection section that selects said align information used in said align section from said align information issued along with said store data and said align information included in said store instruction based on said usable/unusable information, wherein, when causing said operation result stored in said arithmetic register to be issued to said store data buffers as said store data after issuing said store instruction to said store ports, said instruction processing section sets said usable/unusable information to unusable, and when causing said operation result stored in said arithmetic register to be issued to said store data buffers as said store data before issuing said store instruction to said store ports, said instruction processing section sets said usable/unusable information to usable.