Patent ID: 9053281
Filing Date: 2015-06-09
Classification: G06F

Abstract:
1. A computer-implemented method for clock tree synthesis in an electronic design automation (EDA) tool, the computer-implemented method comprising: upon receiving a circuit design in which clock tree synthesis is to be performed, constructing, by using a processor, a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree, wherein each upper-level clock tree is optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew, and wherein optimizing each upper-level clock tree includes optimizing at least one of: a topology of said each upper-level clock tree, buffers in said each upper-level clock tree, routing of said each upper-level clock tree, and a wire width used in said each upper-level clock tree; and for each leaf of each upper-level clock tree, constructing a lower-level clock tree, wherein the lower-level clock tree distributes a clock signal from said each leaf of said each upper-level clock tree to a set of clock sinks, wherein the lower-level clock tree is optimized to reduce latency, power consumption, and/or area, and wherein optimizing the lower-level clock tree includes optimizing at least one of: a topology of the lower-level clock tree, buffers in the lower-level clock tree, routing of the lower-level clock tree, and a wire width used in the lower-level clock tree.