Patent ID: 6489852
Filing Date: 2002-12-03
Classification: H03L,H04J

Abstract:
A phased lock loop (PLL) circuit for locking onto either a primary input reference clock signal or a backup input reference clock signal, the PLL circuit comprising:a switch for selecting a reference signal from one of the primary input reference clock signal or the backup input reference clock signal; a phase detector coupled to the reference signal and a feedback signal for discriminating the phase difference between the reference signal and the feedback signal and for generating a corresponding phase pulse output; an integrator coupled to the phase pulse output for generating a phase voltage; a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal; a feedback circuit including a counter coupled to the local oscillator signal for generating the feedback signal; a slew controlled frame aligner coupled to the local oscillator signal and the counter for controlling the slew rate of the phase deviation in the feedback signal; and a pair of control inputs coupled between the slew controlled frame aligner and the counter, wherein one of the control inputs is an add pulse input to the counter and the other control input is a subtract pulse input to the counter.