Patent ID: 7692960
Filing Date: 2010-04-06
Classification: G11C

Abstract:
1. A method for improving an over erasing effect of a charge-trapping memory cell in a charge-trapping memory structure, the charge-trapping memory cell having a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line, the charge-trapping memory structure comprising a first switch and a second switch, the first switch having a first terminal coupled to the first bit line, the second switch having a first terminal coupled to the second bit line, the method comprising the steps of: erasing the charge-trapping memory cell by turning on the first switch and the second switch; and when the erased charge-trapping memory cell is to be read for verification, employing an equalization transistor, having a first terminal coupled to a second terminal of the first switch and a second terminal coupled to a second terminal of the second switch, to electrically connect the first bit line to the second bit line and make a voltage level of the first bit line equal a voltage level of the second bit line such that a voltage level of the first terminal of the transistor equals a voltage level of the second terminal of the transistor to correctly verify the erased charge-trapping memory cell.