Patent ID: 6236602
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A reconfigurable memory comprising:M bit lines, where M>1;a plurality of row lines;an array of memory storage cells, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said bit lines in response to a row control signal on one of said row lines;a row select circuit for generating said row control signal on one of said row lines in response to a row address being coupled to said row select circuit, said row select circuit comprising a memory for storing a mapping of said row addresses to said row lines, said mapping determining which of said row lines is selected for each possible value of said row address; anda controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to that row line that causes that defective storage cell to couple a data value to one of said bit lines.