Patent ID: 6990507
Filing Date: 2006-01-24
Classification: G06F

Abstract:
1. A circuit for generating a parity check for an increment function on an operand, said circuit comprising: a plurality of cells arranged in a row, each cell capable of receiving from an operand input at least one pair of bits from the operand and connected sequentially to one another by way of a disable connection and a parity inversion connection; and a logic circuit in each cell that sends a disable signal over the disable connection to disable the logic circuit in each subsequent cell in the plurality of cells when there is no carry predicted from an increment to be performed on the at least one pair of bits from the operand and sends a parity inversion signal over the parity inversion connection when the at least one pair of bits from the operand indicates that incrementing the at least one pair of bits from operand would change the parity of the operand.