Patent ID: 8725900
Filing Date: 2014-05-13
Classification: G06F,H04L

Abstract:
1. A processing pipeline having a plurality of processing stages, the processing pipeline comprising: a first processing stage circuit configured to a second processing stage circuit subsequent to the first processing stage circuit, the second processing stage circuit configured to a register configured to store i) the length of the data packet as a length n and ii) a position of the data packet within the data block with respect to the dummy header portion and the dummy tail portion as an offset m, wherein m corresponds to a length of the dummy header portion, wherein the register is configured to, to modify the additional information to reflect the data added to the at least one of the dummy header portion and the dummy tail portion, store the length of the data packet as a length n+q+p, wherein a corresponds to a length of data added to the dummy tail portion and p corresponds to a length of data added to the dummy header portion, and store the position of the data packet within the data block with respect to the dummy header portion and the dummy tail portion as an offset m−p.