Patent ID: 8184471
Filing Date: 2012-05-22
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first memory cell block including a first plurality of word lines, a first plurality of bit lines, and a first plurality of memory cells formed on a substrate, the first plurality of memory cells being located at respective intersections of a word line of the first plurality of word lines and a bit line of the first plurality of bit lines; a second memory cell block, adjacent to the first memory cell block, including a second plurality of word lines, a second plurality of bit lines, and a second plurality of memory cells formed on the substrate, the second plurality of memory cells being located at respective intersections of a word line of the second plurality of word lines and a bit line of the second plurality of bit lines; and a first sense amplifier, positioned between the first and second memory cell blocks and connected to the first plurality of memory cells by a first one of the first plurality of bit lines and connected to the second plurality of memory cells by a first one of the second plurality of bit lines, configured to sense data stored in each of the first plurality of memory cells and in each of the second plurality of memory cells, wherein each memory cell among the first plurality of memory cells includes a data storage capacitor having a first capacitance value, wherein each memory cell among the second plurality of memory cells includes a data storage capacitor having a second capacitance value, wherein the first capacitance value is substantially greater than the second capacitance value, wherein each data storage capacitor of the first plurality of memory cells comprises: