Patent ID: 6255870
Filing Date: 2001-07-03
Classification: H03L

Abstract:
An apparatus for compensating a locking error in a high speed memory device using a DLL, comprising:a division means for dividing a buffered external clock signal into a plurality of divided clock signals having respective pulse widths, wherein the plurality of the divided clock signals include a first clock signal, a second clock signal corresponding to an inverted first clock signal, and a third clock signal having a low level width twice as wide as that of the second clock signal;a selection means for selecting one of the second clock signal and the third clock signal in response to a first control signal;a delay means for delaying the first clock signal and gradually increasing a time delay in response to a second control signal;a means for receiving and delaying the delayed first clock signal according to a modeling of a delay value to generate a fourth clock signal, wherein the modeling of the delay value corresponds to a delay time from a clock buffer for buffering the external clock signal to an output unit for outputting an internal data;an initial clock control means for generating the first control signal, wherein the first control signal is allowed to select the second clock signal by the selection means in case when a rising edge of the fourth clock signal is disposed within a low level width of the second clock signal, and wherein the first control signal is allowed to select the third clock signal by the selection means in case when a rising edge of the fourth clock signal is disposed outside a low level width of the second clock signal; anda phase comparison means for comparing the fourth clock signal and an output signal of the selection means to generate the second control signal.