Patent ID: 6606686
Filing Date: 2003-08-12
Classification: G06F

Abstract:
A data processing apparatus comprising:a central processing unit for executing instructions manipulating data; and a memory connected to said central processing unit, configured as a predetermined number of cache entries organized in a predetermined number of 2N sets serving as proxy for N address bits and a predetermined number of ways for each set and selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory, said memory including tag bits for each cache entry, an address comparator for each cache entry having a first input connected to said corresponding tag bits and a second input receiving an address to which access is sought, said address comparator indicating whether said tag bits matches a predetermined number of most significant bits of said address, and control logic coupled to said address comparator for inhibiting indication that said tag bits matches said predetermined number of address bits if said corresponding way is configured as directly addressable memory.