Patent ID: 7434119
Filing Date: 2008-10-07
Classification: G11C

Abstract:
1. Apparatus for processing data, said apparatus being operable in an operational mode and a self-test mode, said apparatus comprising: at least one memory having a plurality of memory cells arranged according to a physical configuration, wherein physical locations in said at least one memory of said plurality of memory cells are selected by respective memory addresses; a self-test controller operable in said self-test mode to generate in response to a self-test instruction a sequence of generated memory addresses for performing respective memory-access operations in accordance with at least one memory test algorithm having an associated memory cell physical access pattern; and a programmable remapper, responsive to programmable mapping selection data, for remapping said sequence of generated memory addresses to a sequence of remapped memory addresses for selecting memory cells in said at least one memory, wherein said memory cells are accessed in accordance with said associated memory cell physical access pattern.