Patent ID: 6151251
Filing Date: 2000-11-21
Classification: G05F,H01L

Abstract:
A biasing device for a memory cell having a substrate bias terminal associated therewith, said biasing device comprising:a sub-threshold circuitry blockstructured to supply an appropriate current during a standby phase of the device, the sub-threshold circuitry block including a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal; and a bias circuit connected between the supply voltage reference and a ground voltage reference and connected to the control terminal of the restore transistor to drive the restore transistor with a current of limited value; anda feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and including a bias transistor having a control terminal; a stabilization transistor connecting the control terminal of the bias transistor to the ground voltage reference and having a control terminal connected to an output node; and a first regulation transistor connected between the supply voltage reference and the ground voltage reference and having a control terminal connected to a control terminal of the stabilization transistor, said stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.