Patent ID: 6651023
Filing Date: 2003-11-18
Classification: G01R

Abstract:
A semiconductor test apparatus comprising:an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal from the outside or the inside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.