Patent ID: 8982645
Filing Date: 2015-03-17
Classification: G11C

Abstract:
1. A semiconductor comprising: a memory cell array including a plurality of memory cells; a first amplifier producing, when activated, at an output node thereof a first data signal related to data stored in a selected first one of the memory cells; a first data line; a first transistor provided between the output node of the first amplifier and the first data line, and turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line; a first signal line; a second amplifier coupled to the first data line and amplifying, when activated, the first data signal, the second amplifier being further coupled to the first signal line and activated in response to a first activation signal that is transferred through the first signal line; and a second transistor coupled to the first signal line and turned ON in response to the first selection signal to produce the first activation signal to the first signal line.