Patent ID: 6479341
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A method of fabricating a DRAM device, on a semiconductor substrate, with a Capacitor Over Metal, (COM), stacked capacitor structure, comprising the steps of:providing a first transfer gate transistor, comprised of polysilicon gate structures, on a gate insulator layer, with a first source and drain region in said semiconductor substrate, in an area not covered by said polysilicon gate structures; providing a second source and drain region in said semiconductor substrate, for a second transfer gate transistor; forming contact plugs, in contact holes in a first insulator layer, with the contact plugs placed between said polysilicon gate structures of said first transfer gate transistor, and with said contact plugs, contacting said first source and drain region, of said first transfer gate transistor; forming short, first level metal studs, in shallow via holes, created in a second insulator layer, with said short, first level metal studs contacting the top surface of said contact plugs; forming a tall, first level metal stud, in a deep via hole, created in said second insulator layer, and in said first insulator layer, with said tall, first level metal stud contacting said second source and drain region, of said second transfer gate transistor; forming a metal bit line structure, contacting the top surface of a first, short, first level metal stud; forming a metal plug contacting the top surface of a second, short first level metal stud; forming a first level metal interconnect structure, contacting the top surface of said tall, first level metal stud; forming a second level metal stud in a via hole created in a third insulator layer, with said second level metal stud contacting the top surface of said first level interconnect structure; forming a third level metal stud in a via hole created in a fourth insulator layer, and in said third insulator layer, with said third level metal stud contacting the top surface of said metal plug; and forming said COM, stacked capacitor structure, on the top surface of said fourth insulator layer, and with said COM, stacked capacitor structure contacting the top surface of said third level metal stud.