Patent ID: 6415384
Filing Date: 2002-07-02
Classification: G06F

Abstract:
A computer-implemented method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the step of parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded system; (b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the tasks graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the tasks graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, to generate a current version of the embedded system; and (c) a reconfiguration phase, following the synthesis phase, comprising the step of generating a reconfigurable version of the embedded system by merging at least two programmable PEs of the current version of the embedded system into a composite reconfigurable programmable PE having at least two modes of operation.