Patent ID: 9013456
Filing Date: 2015-04-21
Classification: G09G,G11C

Abstract:
1. A scan driver comprising a plurality of scan driving blocks, each scan driving block including a sequential input terminal, a first clock signal input terminal, a second clock signal input terminal, an inverse-output input terminal, and a signal output terminal; the plurality of scan driving blocks comprises: a first scan driving block receiving one of a frame start signal and an output signal of an adjacent scan driving block through the sequential input terminal of the first scan driving block, receiving a first clock signal through the first clock signal input terminal of the first scan driving block, and receiving a second clock signal having an inverse-phase voltage level of the first clock signal through the second clock signal input terminal of the first scan driving block so as to output a first output signal to the signal output terminal of the first scan driving block; and a second scan driving block receiving the first output signal of the first scan driving block through the sequential input terminal of the second scan driving block, receiving the second clock signal through the first clock signal input terminal of the second scan driving block, and receiving the first clock signal through the second clock signal input terminal of the second scan driving block so as to output a second output signal to the signal output terminal of the second scan driving block, the second output signal of the second scan driving block transmitted to the inverse-output input terminal of the first scan driving block; each scan driving block including: a first transistor transmitting a signal applied to the second clock signal input terminal to the signal output terminal of said each scan driving block; a second transistor transmitting a power source voltage of a logic high level to the signal output terminal of said each scan driving block; a third transistor transmitting a power source voltage of a logic low level for turning on the second transistor; a fourth transistor transmitting the power source voltage of logic high level for turning off the second transistor; and a fifth transistor transmitting a signal applied to the sequential input terminal of said each scan driving block to the gate electrode of the first transistor.