Patent ID: 7786017
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, the method comprising: depositing an inter-level dielectric layer over a CMOS device, the CMOS device including an NMOS device and a PMOS device; depositing a first photoresist over the inter-level dielectric layer; patterning a first opening in the first photoresist, and patterning a second opening in the first photoresist; etching the first photoresist and the inter-level dielectric layer under conditions causing inverse reactive ion etching lag, the etching including forming a first inter-level dielectric opening and a second inter-level dielectric opening corresponding to the first opening in the first photoresist and the second opening in the first photoresist, respectively; removing the first photoresist; depositing a first organic planarizing layer (OPL) over the inter-level dielectric layer, the depositing of the first OPL including filling the first inter-level dielectric opening and the second inter-level dielectric opening; depositing a second photoresist over the first OPL; patterning an opening in the second photoresist, the opening in the second photoresist located within the filled second inter-level dielectric opening; etching the second photoresist, the OPL, and the inter-level dielectric layer to form a third inter-level dielectric opening; and forming a contact in each of the first inter-level dielectric opening, the second inter-level dielectric opening, and the third inter-level dielectric opening.