Patent ID: 7897483
Filing Date: 2011-03-01
Classification: H01L

Abstract:
1. A method for manufacturing a plurality of semiconductor integrated circuits, comprising the steps of: adding an ion to a single crystal semiconductor substrate to form an embrittlement layer at a predetermined depth from a surface of the single crystal semiconductor substrate; providing a supporting substrate; forming an insulating layer over one of the single crystal semiconductor substrate and the supporting substrate; performing heat treatment for generating a crack in the embrittlement layer and separating the single crystal semiconductor substrate at the embrittlement layer in a state where the single crystal semiconductor substrate and the supporting substrate overlap with each other with the insulating layer interposed therebetween so as to form a single crystal semiconductor layer over the supporting substrate from the single crystal semiconductor substrate; forming a plurality of semiconductor element layers including the single crystal semiconductor layer over the supporting substrate; reducing a thickness of the supporting substrate; forming a groove between the plurality of semiconductor element layers in the supporting substrate; forming a resin layer over the supporting substrate in which the groove is formed; and cutting the supporting substrate and the resin layer in the groove.