Patent ID: 6240329
Filing Date: 2001-05-29
Classification: G01R

Abstract:
In a semiconductor wafer manufacturing system, an automated method of determining defects in wafers by analyzing their electrical parameters, comprising the steps of:making a plurality of measurements on each of a plurality of wafers;producing computed measurements based on said plurality of measurements;recording said plurality of measurements and said computed measurements as stored metrics;for each wafer, selecting a rule defining a wafer failure mode, said rule including (i) a first electrical parameter and a first off-target limit, (ii) a second electrical parameter and a second off-target limit, and (iii) a boolean logic connector;making a wafer pass/fail determination of said each wafer based on a selected rule, including:(i) constructing a first text string comprising said first off-target limit and a stored metric corresponding to said first parameter;(ii) constructing a second text string comprising said second off-target limit and a stored metric corresponding to said second parameter;(iii) constructing a third text string comprising said first text string followed by said boolean logic connector followed by said second text string; and(iv) interpreting said third text string to obtain a wafer off-target determination, said pass/fail determination being based on said wafer off-target determination; andreporting said wafer failure mode for said each wafer resulting in a positive determination of a wafer failure.