Patent ID: 7423339
Filing Date: 2008-09-09
Classification: G11C,H01L,Y10T

Abstract:
1. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input device, the output device, and the memory device, one of the input device, the output device, the memory device, and processor device comprising: a base having a surface having a first plurality of flip-chip pads solely thereon and a second plurality of wire-bondable pads solely thereon, the first plurality of flip-chip pads connected to the second plurality of wire-bondable pads; a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon, at least one flip-chip bump of the plurality of flip-chip bumps connected to at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base; a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface attached to the back-side surface of the first integrated circuit die and the front-side surface having a plurality of bond pads thereon; and at least one wire connection between at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least one wire-bondable pad of the second plurality of wire-bondable pads on the surface of the base.