Patent ID: 6207985
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a first bit line; anda first memory cell includinga first storage capacitor, anda first pass transistor formed within a semiconductor mesa, the semiconductor mesa extending in length direction and a width direction and being coupled between the first bit line and the first storage capacitor, the first pass transistor including,a source region coupled to the first bit line, the first source region having a source width in the width direction,a first drain region coupled to the first storage capacitor, the first drain region having a drain width in the width direction,a first channel region disposed between the source region and the first drain region in the length direction, the first channel region having a first channel width along the width direction, the first channel width being less than the source region width, the first channel region having at least one generally horizontal first channel top surface, and at least one generally vertical first channel first side surface, anda first control gate disposed adjacent to the first channel top surface and first channel first side surface, and separated therefrom by a first gate insulating layer.