Patent ID: 6069514
Filing Date: 2000-05-30
Classification: G06F,H03K,H03L

Abstract:
A system for distributing clock signals to a plurality of locations on a chip such that each of the plurality of locations receives a local clock signal which is substantially synchronized with local clock signals received at other locations, the system comprising:(a) a ring of control structures, one per location, wherein each control structure in the ring is associated with a previous control structure in the ring and a next control structure in the ring, each control structure comprising:(1) an input;(2) an output; and(3) a clock distribution node at which the control structure outputs its local clock signal; and(b) a plurality of signal lines, wherein a signal line carries a signal from the output of one control structure to the input of the one control structure's next control structure, the signal line and the control structure having a combined signal delay substantially equal to a combined signal delay of each of the control structures and their output signal lines.