Patent ID: 6777762
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A Mask ROM, comprising:a substrates; a plurality of gates on the substrate; a gate oxide layer between the gates and the substrate; a plurality of buried bit lines in the substrate between the gates; an insulator on the buried bit lines and between the gates; a plurality of word lines over the substrate perpendicular to the buried bit lines, wherein each word line is located over a row of gates and the insulator; and a coding layer between the word lines and the gates, wherein a gate, the substrate, the gate oxide layer under the gate, and the coding layer on the gate constitute a memory cell, and the coding layer on the gate of a memory cell serves as a coding region of the memory cell; and the coding regions of some memory cells are implanted with coding ions and are in a logic state of 1 (or 0), and the coding regions of other memory cells are not implanted with coding ions and are in a logic state of 0 (or 1).