Patent ID: 7863071
Filing Date: 2011-01-04
Classification: B81C

Abstract:
1. A method for fabricating a combined micro-electro-mechanical systems (MEMS) device and integrated circuit (IC) on a silicon-on-insulator (SOI) wafer comprising: providing the SOI wafer comprising an SOI device layer over an SOI buried oxide layer; forming at least one deposition layer over the SOI device layer; forming at least one electronic component of the IC using the SOI device layer and the at least one deposition layer; etching through all of the at least one deposition layer to create a MEMS device section on the SOI device layer; after the etching through all of the at least one deposition layer, applying a hard mask to a surface of the SOI wafer; applying imprint material over the hard mask to the MEMS device section; imprinting a MEMS device pattern in the imprint material using a stamp; and dry etching the MEMS device pattern through the imprint material and through the hard mask down to the SOI device layer.