Patent ID: 7590012
Filing Date: 2009-09-15
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a plurality of memory cell rows each of which includes a plurality of memory cells provided at intersections between a bit line and a word line, memory cells in each of said memory cell rows being connected by the bit line; a write amplifier; and a selecting circuit that selectively connects one of said memory cell rows to said write amplifier via a bit line by a block-select activating signal; wherein said selecting circuit includes a first MOS transistor having a first end connected to said write amplifier, a second end connected to the bit line, and a control end, so as to be controlled in such a manner that if said write amplifier outputs a voltage level on a power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the voltage on the power-supply side and exceeding the voltage level is applied to the control end.