Patent ID: 7184356
Filing Date: 2007-02-27
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer lines disposed in parallel with each other to intersect said data select lines, and electrically rewritable non-volatile memory cells laid out at cross portions between said data select lines and data transfer lines; a data select line driver for driving said data select lines of said memory cell array; a sense amplifier circuit connected to said data transfer lines of said memory cell array, for performing data read of memory cells selected by one of said data select lines: and a control circuit used for timing control of data read of said memory cell array, for outputting at least two types of timing signals, wherein said device has a data write mode for writing data into selected memory cells, said data write mode including a verify-read operation for verifying a write state.