Patent ID: 6134637
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A memory comprising:a memory array, partitioned into N (N=2.sup.n, n is an integer; N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells of the array having a same row address commonly designated in the divisional memory areas being accessed simultaneously;a serial access memory (SAM) array partitioned into M (M=2.sup.m, m is an integer greater than or equal to 2; M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with respect to said memory array, each of said divisional SAM areas corresponding with at least one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas, said serial access memory being accessed in an arbitrary sequential order using boundary points for initiating a serial transfer cycle; anda data transfer unit to transfer data between one divisional memory area of said memory array and one of said divisional SAM areas of said serial access memory array.