Patent ID: 8499215
Filing Date: 2013-07-30
Classification: G11C

Abstract:
1. A multi-level cell (MLC) memory device, comprising: ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses, according to the encoded bit stream, to the ‘a’ number of m-bit MLC memory cells in order to write the encoded bit stream in the ‘a’ number of m-bit MLC memory cells; wherein ‘a’ and ‘m’ are integers greater than or equal to 2, wherein ‘k’ and ‘n’ are integers greater than or equal to 1, wherein ‘n’ is greater than ‘k’, and wherein n=a*m=k+1.