Patent ID: 6097200
Filing Date: 2000-08-01
Classification: G01R

Abstract:
Semiconductor reliability test system for testing a plurality of DUTs comprising, in combination: a board of a generally planar configuration, with the board having a first face, with the board having a plurality of provisions for removably receiving DUTs, with the DUTs extending beyond the face to an extent, with the provisions located within an area on the face of the board; and an oven having a cavity for removably receiving the board having DUTs received thereon, with the oven including a heat transfer element having a large thermal mass and having an area corresponding to the area of the provisions when the board is received in the cavity, with the heat transfer element having a uniform spacing from the provisions when the board is received in the cavity and being in close and uniform proximity to the extent of the DUTs received on the board.