Patent ID: 6181603
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory cell array which includes a plurality of memory cells, each having a floating gate,wherein a threshold level of each memory cell depends on a value of electric charge in said floating gate of said memory cell,wherein said threshold level of each memory cell is placed on one of three states including an erased state, a first state, and a second state to store at least three-value information in said memory cell, said first state being located between said erased state and said second state;an input terminal which receives write information data to be stored in said memory cell array; anda writing circuit which performs a first write operation and a second write operation after said first write operation, based on a data signal which controls said threshold levels of said memory cells so as to store said write information data,wherein said first write operation includes applying a plurality of pulses including a first beginning pulse and a first ending pulse, an amplitude of said pulses are increasing during said first write operation, and said first beginning pulse being applied to memory cells whose threshold level should be changed to store said three-value information,wherein said second write operation includes applying a plurality of pulses including a second beginning pulse and a second ending pulse, an amplitude of said pulses are increasing during said second operation, andwherein an amplitude of said first ending pulse is large than that of said first beginning pulse, an amplitude of said second ending pulse is larger than that of said second beginning pulse, and an amplitude of said first ending pulse is larger than that of said second beginning pulse.