Patent ID: 8103898
Filing Date: 2012-01-24
Classification: G06F,H04L,Y02D

Abstract:
1. An apparatus comprising a receiver circuit which comprises: a clock tree configured to provide a plurality of phases of the same clock signal such that one or more of the phases are different from the other phases; a plurality of data input latches configured to receive a data group comprising a plurality of data elements such that the data elements are received at two or more different points in time; and a group latch block, wherein the group latch block is configured to receive the data elements from the plurality of data input latches, wherein the clock tree comprises a linear line, wherein the linear line comprises a plurality of nodes from which the plurality of phases are provided, wherein the receiver circuit further comprises a plurality of data lines, each of the data lines being configured to transfer a respective one of the data elements from a respective one of the data input latches to the group latch block, wherein the plurality of data lines have a length different from one another such that one or more of the data elements experience different delays from the other data elements between the data input latches and the group latch block.