Patent ID: 6734072
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) device, on a semiconductor substrate, comprising the steps of:forming a composite insulator shape on a portion of a top surface of said semiconductor substrate; forming a source/drain extension (SDE) region in an area of said semiconductor substrate not covered by said composite insulator shape; forming insulator spacers on sides of said composite insulator shape; forming a heavily doped source/drain region in an area of said semiconductor substrate not covered by said composite insulator shape or by said insulator spacers; forming a planarized dielectric layer on portions of said semiconductor substrate not covered by said composite insulator shape or by said insulator spacers; removing said composite insulator shape resulting in an opening exposing a portion of a top surface of said semiconductor substrate; forming a gate insulator layer on said portion of said semiconductor substrate exposed in said opening, wherein said gate insulator layer is obtained via a multiple spike rapid thermal oxidation (RTO) procedure featuring a first step comprised of multiple cycles, each performed in an ambient comprised with either O2, NO, and N2O, or in a mixture of O2, NO, or N2O, with each cycle performed at a temperature between about 600 to 850Â° C., for a time between about 1 to 50 sec, and with each cycle performed at a pressure between about 0.01 to 200 torr, and featuring a second step performed in a desired ambient, at a temperature between about 950 to 1500Â° C., for a time between about 50 to 1000 millisecond, at a pressure between about 0.01 to 200 torr; and forming a conductive gate structure in said opening, overlying said gate insulator layer.