Patent ID: 6803263
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of fabricating a thin film transistor (TFT) with self-aligned structure, comprising:providing a substrate, with a semiconductor layer and gate insulation layer formed in sequence thereon; forming a conductive layer on the gate insulation layer; defining the conductive layer to form a gate conductive layer and a dummy conductive layer, wherein the dummy conductive layer is on both sides of the gate conductive layer and is provided with a gap therebetween; performing a first ion implantation process via the gap to form a lightly doped region on the semiconductor layer thereunder; forming a sacrificial layer to fill the gap; removing the dummy conductive layer; and performing a second ion implantation process to form a heavily doped source/drain region on the semiconductor layer with the gate conductive layer and the sacrificial layer used as a mask.