Patent ID: 6762106
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:(a) pre-cleaning a substrate including a single crystalline underlying layer having a composition represented by Si1-x3-y3Gex3Cy3 (where 0&lE;x3<1, 0&lE;y3<1) and an insulating layer; (b) forming, after the step (a), a buffer layer having a composition represented by Si1-x2-y2Gex2Cy2 (where 0&lE;x2<1, 0&lE;y2<1) on the underlying layer while depositing a first polycrystalline semiconductor layer having substantially the same composition as the buffer layer on the insulating layer; and (c) forming, after the step (b), a semiconductor layer having a composition represented by Si1-x1-y1Gex1Cy1 (where 0wherein a relation represented by the inequality of 1-x2-y2>1-x1-y1 holds between both the compositions of the semiconductor layer and the buffer layer.