Patent ID: 8143663
Filing Date: 2012-03-27
Classification: G11C,H01L

Abstract:
1. A non-volatile memory device, comprising: a substrate; a tunnel insulation layer formed on the substrate; a floating gate formed on the tunnel insulation layer; a dielectric layer directly contacting a top surface and a sidewall of the floating gate, the dielectric layer being a continuous layer having a substantially uniform thickness; a selection gate covering a sidewall of the dielectric layer, the selection gate having a height that is substantially equal to a height of a portion of the dielectric layer formed on the top surface of the floating gate; a spacer formed along a predetermined portion of the selection gate; a first metal silicide layer directly formed along a top corner of the selection gate, the first metal silicide layer being formed along a portion of the selection gate along which the spacer is not formed; a source region and a drain region formed in the substrate, the source region and the drain region being respectively exposed at one side of the floating gate and one side of the selection gate; an insulation layer contacting an outer surface of the dielectric layer; and a source contact formed over the source region.