Patent ID: 6124634
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A chip scale package for a semiconductor die, comprising:at least one semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof;a passivation layer disposed on at least said active side of said at least one semiconductor die; anda discrete preformed blank made of the same semiconductor material as said at least one semiconductor die is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active side of said at least one semiconductor die and including apertures preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured thereto by said bondable surface with a bonding material to form a laminate comprising said at least one semiconductor die, said passivation layer, and said discrete preformed blank bonded together.