Patent ID: 8946007
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure comprising: forming a gate stack comprising a gate dielectric, a gate electrode, and a gate cap dielectric on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, said SOI substrate further comprising a bottom semiconductor layer having a first semiconductor material and a buried insulator layer; forming a source trench and a drain trench through said top semiconductor layer, said buried insulator layer, and a portion of said bottom semiconductor layer, said source trench and said drain trench abutting said gate stack; forming a source region and a drain region by depositing at least a second semiconductor material that is different from said first semiconductor material in said source trench and said drain trench, wherein said source region has a surface in contact with a portion of said bottom semiconductor layer in said source trench, and wherein said drain region has a surface in contact with another portion of said bottom semiconductor layer in said drain trench; removing said bottom semiconductor layer selective to each of said second semiconductor material and said buried insulator layer to expose said surface of said source region, said surface of said drain region, and a horizontal surface of a remaining portion of said buried insulator layer; forming a dielectric spacer on each of sidewalls of said source region and said drain region, wherein said dielectric spacer contacts said horizontal surface of said remaining portion of said buried insulator layer; depositing a conductive material layer directly on said horizontal surface of said remaining portion of said buried insulator layer, a surface of each dielectric spacer, said surface of said source region, and said surface of said drain region; planarizing said conductive material layer to expose said surface of said source region and said surface of said drain region; and vertically recessing said planarized conductive material layer such that a topmost surface of a remaining portion of said conductive material layer is below said surface of said source region and said surface of said drain region, wherein said remaining portion of said conductive material layer constitutes a back gate electrode contacting said horizontal surface of said remaining portion of said buried insulator layer.