Patent ID: 6070263
Filing Date: 2000-05-30
Classification: H03M

Abstract:
A circuit for use in a Viterbi decoder to decode an input signal in dependence on metric values representing branch metrics between different states in a predetermined coding trellis to derive a maximum likelihood path, the circuit comprising:first and second selection register means for receiving and producing a selected value froma first metric value representative of the trellis path to a first state at a first time, anda second metric value representative of the trellis path to a second state at the first time;third selection register means for receiving and producing a selected value froma first branch metric value representing the branch from the first state to a third state at a second time following the first time, anda second branch metric value representing the branch from the second state to the third state at the second time;fourth selection register means for receiving and producing a selected value froma third branch metric value representing the branch from the first state to a fourth state at the second time, anda fourth branch metric value representing the branch from the second state to the fourth state at the second time;first comparator means for receiving and comparinga first difference metric value representative of the difference between the metric to the first state at the first time and the metric to the second state at the first time, anda first difference branch metric value representative of the difference between the branch metric from the second state to the third state at the second time and the branch metric from the first state to the third state at the second time,the first comparator means being coupled to the first selection register means for selecting an input thereof in dependence on the first comparator means' comparison and being coupled to the third selection register means for selecting an input thereof in dependence on the first comparator means' comparison;second comparator means for receiving and comparingthe difference metric value, and a second difference branch metric value representative of the difference between the branch metric from the second state to the fourth state at the second time and the branch metric from the first state to the fourth state at the second time;the second comparator means being coupled to the second selection register means for selecting an input thereof in dependence on the second comparator means' comparison and being coupled to the fourth selection register means for selecting an input thereof in dependence on the second comparator means' comparison;first addition means for receiving and adding the selected value from the first selection register means and the selected value from the third selection register means to produce a value representative of the path metric to the third state at the second time; andsecond addition means for receiving and adding the selected value from the second selection register means and the selected value from the fourth selection register means to produce a value representative of the path metric to the fourth state at the second time.