Patent ID: 7309653
Filing Date: 2007-12-18
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, comprising: providing a substrate; depositing a first dielectric layer on the substrate, wherein the first dielectric layer comprises a material having a dielectric constant in a range of 1.4 to 2.7; depositing a first hard mask on the first dielectric layer; forming an at least one first feature within the first dielectric layer and the first hard mask; depositing a first conformal liner over a top surface of the first hard mask and within the at least one first feature, wherein the first conformal liner occupies more than at least 2% of a volume of the at least one first feature; removing a portion of the first conformal liner that was deposited over the top surface of the first hard mask and within the at least one feature, wherein the first conformal liner that remains after said removing said portion of the first conformal liner is performed is not on the top surface of the first hard mask and is in direct physical contact with the substrate, the first dielectric layer, and the first hard mask; depositing a first conductive material over the first conformal liner; planarizing a surface of the device to remove excess first conductive material; depositing a capping layer over the surface of the first conductive material following planarizing the surface of the device; depositing a second dielectric layer on the capping layer, wherein the second dielectric layer comprises a low k dielectric material; depositing a second hard mask on the second dielectric layer; forming an at least one second feature within the second dielectric layer and the second hard mask; depositing a second conformal liner over the second hard mask and within the at least one second feature, wherein the second conformal liner occupies at least 50% of a volume of the at least one second feature; depositing a second conductive material over the second conformal liner; and planarizing a surface of the device to remove excess second conductive material which results in a planar surface of the first conductive material and a planar surface of the second conductive material, wherein the first conductive material and the second conductive material comprise copper, and wherein the capping layer comprises a continuously distributed capping material that prevents diffusion of copper from the first conductive material in the at least one first feature to the second dielectric layer and from the second conductive material in the at least one second feature to the second dielectric layer, wherein one feature of the at least one first feature is denoted as feature A, wherein one feature of the at least one second feature is denoted as feature B, and wherein the continuously distributed capping material is in direct mechanical contact with: