Patent ID: 8195993
Filing Date: 2012-06-05
Classification: G01R,G11C

Abstract:
1. A semiconductor integrated device comprising: a plurality of memory cell arrays arranged with a plurality of electrically reprogrammable memory cells; a control circuit which controls operation of a latch circuit of a plurality of latch circuits that are arranged corresponding to a number of bits of test parameter data provided from an external tester; a data input/output circuit which transfers externally input data to said latch circuit of said plurality of latch circuits; and a selection circuit which is connected with said control circuit, one end of said latch circuit being connected to said control circuit and said data input/output circuit, an input of said latch circuit being connected to an output of said selection circuit, and an output of said latch circuit being connected to an input of said selection circuit so that the output of said latch circuit is fed back to said selection circuit, said latch circuit latching said test parameter data, which is provided from said external tester via said selection circuit, said latch circuit latching said test parameter data, and which is programmed to said plurality of memory cell arrays and read out from said plurality of memory cell arrays by a data program/read circuit, said control circuit generating an internal control signal which activates said selection circuit at a timing at which a fixed value data of said test parameter data is changed, and transferring said internal control signal to said selection circuit, and said selection circuit receiving said internal control signal and controlling so that said fixed value data of said test parameter data is changed by selecting one or more latch circuit of said plurality of latch circuits.