Patent ID: 6011751
Filing Date: 2000-01-04
Classification: G11C

Abstract:
A burst address counter comprising:first to fourth decoder circuits for decoding address signals;first to fourth multiplexer circuits having first to third input terminals to receive the decoded address signals output from said first to fourth decoder circuits at the first input terminals, respectively, and selectively output one of input signals input to the first to third input terminals on the basis of a control signal;first to fourth register circuits for storing output signals representing a burst address and output from said first to fourth multiplexer circuits, respectively;a first interconnection used in linear and interleave modes of single data rate scheme and connected to input the output signal stored in said first register circuit to the second input terminal of said fourth multiplexer circuit and the output signals stored in said second to fourth register circuits to the second input terminals of said first to third multiplexer circuits, respectively; anda second interconnection used in the interleave mode of single data rate scheme and connected to input the output signals stored in said first to third register circuits to the third input terminals of said second to fourth multiplexer circuits, respectively, and the output signal stored in said fourth register circuit to the third input terminal of said first multiplexer circuit.