Patent ID: 8185879
Filing Date: 2012-05-22
Classification: G06F

Abstract:
1. A tracing system, stored in a non-transitory computer readable medium, for a multi-tasking embedded pipelined processor having a processor core for executing instructions and trace generation logic that is operative to periodically generate trace synchronization information, the tracing system comprising: a trace tap point located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed; a compression module, located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed and coupled to the trace tap point via a first lead, wherein the compression module compresses immediately available data received from the first lead; and a load order determination module, located at a position in the pipeline of the pipelined processor after which instructions can no longer be killed and coupled to the trace tap point via a second lead, for tracing immediately available load data from cache memory received from the second lead, wherein the load order determination module includes an input node to receive deferred load data from memory and an output node connected to a load data compression module.