Patent ID: 6538514
Filing Date: 2003-03-25
Classification: H03F

Abstract:
An output stage for a Class-G Amplifier comprising:a first current mirror (18) having an input (IIN) driven by a first half cycle of an input signal provided to an input of the of the Class-G amplifier, and having an output (IOUT(Cmâˆ’)); a second current mirror (20) having an input (IIN) driven by a second half cycle of an input cycle provided to the input of the Class-G amplifier, and having an output (IOUT(Cm+)); series connected diodes (14) connected between the outputs of the first and second current mirrors (18,20); a pair of emitter follower transistors (32,34) having common emitters forming an output (output) of the amplifier, a first one of the pair of emitter follower transistors (32) having a base connected to the output (IOUT(Cmâˆ’) of the first current mirror (18) and a collector forming a node p, and a second one of the pair of emitter follower transistors (34) having a base connected to the output (IOUT(Cmâˆ’)) of the second current mirror (20) and a collector forming a node m; a first voltage source (26) having a negative terminal connected to the output of the amplifier, and having a positive terminal; a second voltage source (28) having a positive terminal connected to the output of the amplifier, and having a negative terminal; a first low voltage control diode (38) having a first terminal connected to a first low voltage power supply terminal (Vsp1), and a second terminal connected to the node p; a first high voltage control transistor (30) having a collector-emitter path connecting the node p to the first high power supply terminal (Vsph), and having a base connected to the positive terminal of the first voltage source (26); a second low voltage control diode (40) having a first terminal connected to a second low voltage power supply terminal (Vsm1), and having a second terminal connected to the node m; a second high voltage control transistor (36) having a collector-emitter path connecting the node m to the second high power supply terminal (Vsmh), and having a base connected to the negative terminal of the second voltage source (28); a first compensation capacitor (82) having a first terminal connected to the input of the first current mirror (18) and a second terminal connected to the node p; and a second compensation capacitor (84) having a first terminal connected to the input of the second current mirror (20) and a second terminal connected to the mode m.