Patent ID: 7316949
Filing Date: 2008-01-08
Classification: H01L,Y10S

Abstract:
1. A process comprising: forming an n-type and a p-type transistor upon a semiconductor substrate, the n-type and p-type transistors comprising n-type and p-type polysilicon gates, respectively; forming an interlayer dielectric layer on a top of the n-type and p-type transistors; removing an interlayer dielectric (ILDO) layer from the top of the n-type and p-type polysilicon gates; etching the n-type polysilicon gate to form a first trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the first trench; depositing n-type metal into the first trench; removing excess n-type gate material to expose a top of the n-type metal gate and the p-type polysilicon gate; etching the p-type polysilicon gate to form a second trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on a bottom of the second trench; depositing a p-type metal gate within the second trench; and removing excess p-type gate material to expose the top of the n-type metal gate and the p-type metal gate.