Patent ID: 7977739
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A semiconductor device having a power MISFET, comprising: (a) a semiconductor substrate with a device main surface; (b) an active region of the power MISFET arranged over the device main surface; (c) a gate contact region of the power MISFET arranged over the device main surface; (d) a trench provided across the active region and the gate contact region of the device main surface of the semiconductor substrate; (e) a gate insulating film formed at the inner surface of the trench; and (f) a gate electrode embedded in the trench via the gate insulating film, the gate electrode having an upper portion with a top surface directly over said trench, the top surface being higher than the device main surface; (g) an interlayer insulating film formed over the active region and the gate contact region and having a first opening over the active region and a second opening over the gate contact region; and (h) a first conductive film portion and a second conductive film portion formed over the interlayer insulating film, wherein the first conductive film portion is electrically connected to a top surface of the active region through the first opening, the second conductive film portion is electrically connected to a first portion of the top surface of the gate electrode in the gate contact region through the second opening, and a second portion of the top surface of the gate electrode in the active region is substantially at the same height as a third portion of the top surface of the gate electrode in the gate contact region.