Patent ID: 8447896
Filing Date: 2013-05-21
Classification: G06F

Abstract:
1. A host system comprising: a system memory configured to store a host driver and first to fourth descriptors; a CPU configured to access the system memory; and said host controller configured to control data transfer between the system memory and the device, to load the first descriptor stored in the system memory, and including a set of a plurality of pointers indicating the second descriptors, each of the third descriptors forming the second descriptors, and including a command number, a command operation mode, and an argument as information necessary to issue a command to the device, and a block length and the number of blocks as information necessary for data transfer, and each of the fourth descriptors forming the second descriptors, and including information indicating addresses and sizes of a plurality of data arranged in the system memory, and the DMA unit configured (1) to set contents of the third descriptor to the register set, and issues commands to the device, (2) to transfer data between the system memory and the device via the host controller in accordance with contents of the fourth descriptors, (3) to repeat (1) and (2) to complete an execution of all the third and the fourth descriptors indicating a plurality of the pointers in the first descriptor, and (4) to generate an interrupt signal according to an attribute of the third and fourth descriptors, wherein the host controller, after accessing all the plurality of pointers in the first descriptor, is configured to generate an interrupt signal indicating data transfer has been completed, and wherein the system memory stores a host driver, and the host driver has a function of forming a descriptor including transfer information, designating only start of the DMA unit, and recognizing completion of the DMA data transfer or detection of a data transfer error by interrupt.