Patent ID: 8361858
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method, comprising: forming a mask layer above a first silicon-containing crystalline semiconductor region and a second silicon-containing crystalline semiconductor region, said first and second silicon-containing crystalline semiconductor regions being laterally separated by an isolation region; removing said mask layer selectively from above said first silicon-containing crystalline semiconductor region while maintaining said mask layer above said second silicon-containing crystalline semiconductor region; etching said first silicon-containing crystalline semiconductor region to reduce a height difference between the first silicon-containing crystalline semiconductor region and the isolation region; forming a threshold adjusting semiconductor alloy selectively on said first silicon-containing crystalline semiconductor region of reduced thickness; forming a first gate electrode structure of a first transistor above said threshold adjusting semiconductor alloy; and forming a second gate electrode structure of a second transistor above said second silicon-containing crystalline semiconductor region.