Patent ID: 6928012
Filing Date: 2005-08-09
Classification: G11C

Abstract:
1. A bitline equalization system for pre charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising: a first equalization circuit connected between a first position along the bitline and a corresponding first position along the complementary bitline, including a second equalization circuit connected between a second position along the bitline and a corresponding second position along the complementary bitline, the second equalization circuit including a fourth transistor having a fourth gate connected to a second equalization line, a fourth source connected to the second position alone the bitline, and a fourth drain connected to the corresponding second position on the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.