Patent ID: 7287203
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A method of testing a RAM block embedded in an integrated circuit, the method including: providing a scan circuit including a RAM block, a plurality of first flip-flops each sending a read address to the RAM block, a plurality of second flip-flops each sending a write address to the RAM block, a plurality of third flip-flops each sending an enable signal to the RAM block, a plurality of fourth flip-flops, and a multiplexer receiving an output from the RAM block, the first, second, third and fourth flip-flops being connected in series, performing an internal scan test by loading serial data into the first, second, third and fourth flip-flops, observing data captured by at least the fourth flip-flops, an output of each fourth flip-flop bypassing the RAM block and being received by the multiplexer, and controlling signals output by the multiplexer, and performing a RAM scan test by the combination of loading serial data into the first, second, third, and fourth flip-flops of the RAM block, triggering a RAM write cycle to latch data in the second, third and fourth flip-flops to the RAM block, triggering a RAM read cycle with data of the first flip-flops being latched by the RAM block and data of a specified read address being output from the RAM block and received by the multiplexer and by the fourth flip-flops, and outputting the data of the specified read address from the fourth flip-flops.