Patent ID: 6549596
Filing Date: 2003-04-15
Classification: H04L

Abstract:
A phase aligner in the form of an all-digital control loop and comprising:a digital delay line having an input coupled to an incoming data stream and outputting a delayed data stream, said digital delay line comprising a plurality of delay cells arranged in at least one cascade with each cell being individually configurable to produce a selectable propagation delay as a function of a logic state of a respective digital control signal; a digital phase detector discriminating on a phase lead or lag between a clock signal and the delayed data stream from said digital delay line; a digital state machine defining a loop filter coupled to an output of said digital phase detector for checking oscillatory behavior of the control loop; a digital delay line control circuit regulating the delay introduced by said digital delay line, said digital delay line control circuit comprising a shift register including a plurality of latches equal to a number of delay cells, each latch having an output tap controlling a respective delay cell; and a digital output circuit receiving the delayed data stream from said digital delay line and outputting a logic bitstream of information congruent with information content of the incoming data stream.