Patent ID: 6713393
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of forming a nanometer-gate MOSFET device, comprising the steps of:providing a semiconductor substrate of a first conductivity type; forming a shallow-trench-isolation (STI) structure on said semiconductor substrate having an active region isolated by an isolation region, wherein said active region has a first conductive layer being formed over a gate-dielectric layer and said isolation region is filled with a first raised field-oxide layer; forming a second masking dielectric layer over said STI structure having a flat surface formed by said first raised filed-oxide layers and said first conductive layer; patterning a gate region to form a gate structure using a masking photoresist step by removing said second masking dielectric layer, etching said first raised field-oxide layers to a depth equal to a thickness of said first conductive layer to form second raised field-oxide layers, removing said first conductive layer, and removing said gate-dielectric layer and simultaneously etching said second raised field-oxide layers to form third raised field-oxide layers; forming a buffer-oxide layer over said gate structure, said third raised field-oxide layers, and exposed semiconductor surfaces; forming lightly-doped source and drain diffusion regions of a second conductivity type by implanting doping impurities across said buffer-oxide layers into said semiconductor substrate in a self-aligned manner; forming a first sidewall dielectric spacer over each sidewall of said buffer-oxide layers and on said buffer-oxide layers; forming heavily-doped source and drain diffusion regions of said second conductivity type by implanting doping impurities across said buffer-oxide layers into said semiconductor substrate in a self-aligned manner; forming a second sidewall dielectric spacer over each sidewall of said first sidewall dielectric spacers and on said buffer-oxide layers; etching back said first and second sidewall dielectric spacers to a thickness of said buffer-oxide layers and removing simultaneously said buffer-oxide layers over said second masking dielectric layer in said gate region and over said third raised field-oxide layers and said heavily-doped source/drain diffusion regions outside of said gate region; forming a metal-disilicide layer over each of said heavily-doped source/drain diffusion regions outside of said second sidewall dielectric spacers by using a well-known self-aligned silicidation process; forming a planarized thick-oxide layer over each side portion of said gate region; removing selectively said second masking dielectric layer in said gate region; forming a pair of second conductive sidewall spacers over each inner sidewall of said buffer-oxide layers and on a portion of said first conductive layer and said first raised field-oxide layers in said gate region; forming an implant region in said semiconductor substrate by implanting doping impurities across said first conductive layer and said gate-dielectric layer between the pair of second conductive sidewall spacers in a self-aligned manner; and forming a planarized third conductive layer over said first conductive layer and said first raised field-oxide layers between the pair of second conductive sidewall spacers to form a conductive-gate structure for said nanometer-gate MOSFET device.