Patent ID: 8418091
Filing Date: 2013-04-09
Classification: G06F,H01L

Abstract:
1. A computer-implemented method of camouflaging an application specific integrated circuit (ASIC) wherein the ASIC comprises interconnected functional logic performing a logical function, the method comprising the steps of: generating, using the computer, a logical description of the interconnected functional logic for performing a logical function, the logical description comprising a plurality of interconnected logic cells, each logic cell including an input and an output, generating, using the computer, a logical description of a functionally inert camouflage element including at least one filler cell; generating, using the computer, a camouflaged logical description of the interconnected functional logic by incorporating the generated logical description of the functionally inert camouflage element into the generated logical description of the interconnected functional logic without affecting the logical function wherein the functionally inert camouflage element comprises the at least one filler cell communicatively coupled to a logical input or logical output of at least one of the interconnected logic cells; and generating, using the computer, a camouflaged ASIC design from the camouflaged logical description.