Patent ID: 7558106
Filing Date: 2009-07-07
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cells arranged in rows and columns, and each storing data written in response to application of first and second data write magnetic fields; a plurality of write word lines provided corresponding to said rows for passing, in a predetermined direction, a first data write current producing said first data write magnetic field in a selected row, respectively; a plurality of first bit lines provided corresponding to said columns, respectively; and a data write circuit for passing, in a direction in accordance with a write data, a second data write current producing said second data write magnetic field through a portion, corresponding to a selected memory cell, of selected one of said first bit lines corresponding to a selected column, wherein said data write circuit includes a plurality of bit line drive portions provided for each of said columns, and arranged corresponding to a first node corresponding to one end portion of the corresponding first bit line, a second node corresponding to the other end portion of the corresponding first bit line and an at least one intermediate node of the corresponding first bit line, respectively, and two bit line drive portions among said plurality of bit line drive portions in said selected column and located on opposite sides of said selected memory cell set the corresponding nodes of the selected first bit line to one and the other of first and second voltages corresponding to said write data.