Patent ID: 8877648
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: forming a substrate comprising a semiconductor active layer on an underlying sacrificial layer; forming a multi-layer electrical interconnect network comprising a plurality of interlayer dielectric layers, on the substrate; selectively etching through the plurality of interlayer dielectric layers to expose an upper surface of the semiconductor active layer; encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the exposed upper surface of the semiconductor active layer; selectively etching through the inorganic capping layer and the semiconductor active layer to expose the sacrificial layer; and then removing the sacrificial layer from the substrate to thereby suspend the semiconductor active layer from the substrate, wherein said encapsulating is preceded by roughening an upper surface of the semiconductor active layer.