Patent ID: 7547940
Filing Date: 2009-06-16
Classification: H01L

Abstract:
1. A non-volatile memory device, comprising: an EEPROM transistor in a first portion of a semiconductor substrate, said EEPROM transistor comprising a control gate electrode; an access transistor in a second portion of the semiconductor substrate that extends adjacent a first side of the first portion of the semiconductor substrate, said access transistor having a first source/drain terminal electrically connected to a first source/drain terminal of said EEPROM transistor and an active region that forms a first P-N junction in the second portion of the semiconductor substrate; and an erase transistor in a third portion of the semiconductor substrate that extends adjacent a second side of the first portion of the semiconductor substrate, said erase transistor having a first source/drain terminal electrically connected to a second source/drain terminal of said access transistor and an active region that forms a second P-N junction in the third portion of the semiconductor substrate; wherein the first portion of the semiconductor substrate extends between the first and second P-N junctions; and wherein the second and third portions of the semiconductor substrate extend on diametrically opposite sides of the control gate electrode.