Patent ID: 7636877
Filing Date: 2009-12-22
Classification: G01R,G11C

Abstract:
1. A test apparatus that tests a device under test comprising: a pattern memory that stores data to be outputted to the device under test; a device judgment section that judges whether the device under test passes or fails based on an output signal outputted from the device under test; a number of data information storage section that stores the number of data information based on the number of logic H data included in an input data to be stored in the pattern memory; a counter that receives output data outputted from the pattern memory to the device under test and counts the number of logic H data included in the output data; a pattern memory judgment section that judges that the data stored in the pattern memory is correct when the number of data information of the input data stored in the number of data information storage section is corresponding to the number of logic H data counted by the counter and outputs a signal according to this judgment result; and a count selecting section that receives the input data and the output data, selects the input data and provides the same to the counter when the input data is written to the pattern memory, causes the counter to acquire the number of data information of the input data, and selects the output data and provides the same to the counter when the pattern memory outputs the output data, wherein the number of data information storage section stores the number of data information of the input data acquired by the counter.