Patent ID: 6559494
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a memory cell portion formed on the substrate, comprising: a plurality of first active regions having a first impurity concentration, formed in a surface of the substrate within the memory cell portion; a plurality of first gate electrodes, each first gate electrode comprising: a dielectric layer formed on the substrate; a gate conductive layer formed on the gate dielectric layer; and a silicon oxide layer formed on each gate conductive layer; a silicon nitride film formed over the substrate, wherein the silicon nitride film overlies the first active regions and the silicon oxide layer on each gate conductive layer and contacts side surfaces of each silicon oxide layer and gate conductive layer, the silicon nitride film overlying the entirety of the first active regions at least in a direction in which two neighboring first gate electrodes and a first active region therebetween are arranged; an interlayer dielectric formed over the substrate including to cover the silicon nitride film; and a plurality of first local interconnections extending to the first active regions through the interlayer dielectric and the silicon nitride film; and a peripheral circuit portion formed on the substrate, comprising: a plurality of second active regions having a second impurity concentration, formed in the surface of the substrate; a plurality of second gate electrodes, each having an upper surface and comprising: a dielectric layer formed on the substrate; and a gate conductive layer formed on the gate dielectric layer; a plurality of silicon nitride sidewall spacers contacting side surfaces of each second gate electrode; the interlayer dielectric formed over the substrate to cover the second active regions, the second gate electrodes, and the silicon nitride sidewall spacers; a plurality of second local interconnections extending to the second active regions through the interlayer dielectric; and a plurality of third local interconnections extending to the second gate electrodes through the interlayer dielectric, wherein the silicon nitride film does not overly the upper surface of the plurality of second gate electrodes.