Patent ID: 7875550
Filing Date: 2011-01-25
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, said method comprising: forming, on a semiconductor substrate, a first gate electrode and a second gate electrode positioned laterally relative to said first gate electrode; forming a first sidewall spacer adjacent to said first gate electrode and a second sidewall spacer adjacent to said second gate electrode such that said first sidewall spacer and said second sidewall spacer are separated by a gap; forming a silicide region on said semiconductor substrate within said gap and extending laterally from said first sidewall spacer to said second sidewall spacer; forming a sacrificial section on said silicide region, said sacrificial section extending laterally from said first sidewall spacer to said second sidewall spacer and filling said gap such that side edges of said sacrificial section follow contours of said first sidewall spacer and said second sidewall spacer and a top surface of said sacrificial section is approximately level with top surfaces of said first gate electrode and said second gate electrode; forming a dielectric layer above said first gate electrode, said first sidewall spacer, said sacrificial section, said second sidewall spacer and said second gate electrode; forming a contact hole through said dielectric layer to said sacrificial section; selectively removing said sacrificial section to form a cavity and expose said silicide region, said first sidewall spacer and said second sidewall spacer; and depositing a conductive material into said cavity and said contact hole so as to form a contact comprising: