Patent ID: 8595529
Filing Date: 2013-11-26
Classification: G06F,Y02D

Abstract:
1. A method for implementing a low power state in a first processor of a multi-processor computing device, comprising: registering a set of indication filtering criteria on a second processor of the multi-processor computing device, wherein the set of indication filtering criteria identifies a communications control service on the second processor, and wherein the indication filtering criteria comprise indications that should be sent to the first processor when the first processor is in the low power state; informing the second processor that the first processor is in the low power state; establishing an event indication generated by the communications control service on the second processor; determining whether the event indication matches an indication in the registered set of indication filtering criteria; and sending the event indication from the second processor to the first processor in response to determining that the event indication matches an indication in the registered set of indication filtering criteria.