Patent ID: 6237075
Filing Date: 2001-05-22
Classification: G06F

Abstract:
A sequence generator comprising:a. a memory having a plurality of uniquely addressable memory locations, address inputs for selecting any one of said memory locations and data outputs providing data stored in an addressed memory location;b. latch circuitry providing a latched output of a latch input upon receiving a clock signal, at least part of said data output coupled to said latch input and at least part of said latched output coupled to said address inputs; andc. a portion of said data from any one memory location latched at said latched output representing at least part of an address for an immediately succeeding one of said memory locations to be addressed and a sequence of bits wherein continuous clocking of the latch circuitry provides at least part of an address for the immediately succeeding memory location and a sequence of bits formed from a portion of said latched outputs.