Patent ID: 8035170
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; device regions formed on the semiconductor substrate, the device regions having a length direction in a predetermined direction; a plurality of transistors having gate electrodes, respectively, the gate electrodes extending in a direction approximately perpendicular to the predetermined direction, the plurality of transistors having a source/drain region and a channel region having a channel direction approximately parallel to the predetermined direction in the device region; a plurality of SRAM cells disposed in an array, each of the plurality of SRAM cells including the plurality of transistors; and a dummy region made of the substantially same material as that of the device regions, the dummy region being formed between outermost device regions of the SRAM cells adjacent to each other in the direction approximately perpendicular to the predetermined direction, the dummy region having a length direction approximately parallel to the predetermined direction, wherein each SRAM cell includes a plurality of transfer transistors, a plurality of driver transistors, and a plurality of load transistors; in each SRAM cell, two of the load transistors are disposed on an inner side of the SRAM cell, and two of the transfer transistors and two of the driver transistors are both disposed on outer sides of the SRAM cell; gate electrodes of one of the load transistors and one of the driver transistors in each SRAM cell are commonly connected to an end of another load transistor in the SRAM cell; gate electrodes of the transfer transistors, which are respectively included in the SRAM cells adjacent to each other, are connected to each other; and gate contacts connecting the gate electrodes of the transfer transistors to wirings thereabove are disposed above the dummy region.