Patent ID: 8184651
Filing Date: 2012-05-22
Classification: H04L

Abstract:
1. An integrated circuit for processing 10 Gigabit Ethernet (10 GbE) signals comprising: programmable logic device (PLD) circuitry, wherein the PLD circuitry comprises PLD fabric that includes an array of blocks of programmable logic and programmable interconnection resources; 10 GbE physical coding layer (PCS) circuitry programmed into the programmable logic device fabric; 10 GbE transceiver circuitry implemented in dedicated circuitry that receives a 64-bit parallel data signal from the programmable logic device circuitry and generates a serial 10 GbE data signal from the parallel data signal, wherein the dedicated circuitry is distinct from the programmable logic device (PLD) circuitry; and interface circuitry that interconnects a portion of the programmable logic device circuitry with the transceiver.