Patent ID: 7683662
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A logic gate for implementing complex logic within a memory array, comprising: a logic gate output node; a first input circuitry, wherein an output node is coupled to the first input circuitry, and wherein the first input circuitry receives a first storage cell signal, a second storage cell signal, and a first external signal; wherein the first input circuitry comprises: a second input circuitry, wherein the output node is coupled to the second input second input circuitry, wherein the second input circuitry receives the first storage cell signal, the second storage cell signal, and a second external signal, and wherein the same first storage cell signal and the same second storage cell signal are received by both the first input circuitry and the second input circuitry; wherein the second input circuitry comprises: an output drive circuitry, wherein the output drive circuitry is coupled to the output node and the logic gate output node, wherein the first input circuitry and second input circuitry are operable to receive at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at their respective input circuitry; and wherein the logic gate performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal.