Patent ID: 8278159
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A method of fabricating a thin film transistor (TFT), comprising: placing a semiconductor layer having an edge portion on a substrate; placing a gate insulating layer on the substrate having the semiconductor layer; forming a first pattern on the gate insulating layer to expose the edge portion of the semiconductor layer; performing a first impurity implantation process on the edge portion of the semiconductor layer using the first pattern as a mask to form an edge region; removing the first pattern and placing a gate electrode on the gate insulating layer; forming a second pattern on the substrate to cover at least the edge region; performing a second impurity implantation process on the semiconductor layer using the second pattern as a mask to form source and drain regions on respective sides of a channel region in the semiconductor layer; removing the second pattern and placing an interlayer insulating layer on the substrate having the gate electrode; etching the gate insulating layer and the interlayer insulating layer to form a contact hole exposing a portion of the source region and a portion of the edge region; and placing a conductive layer on the substrate and then patterning the conductive layer to form an interconnection portion that connects the exposed portion of the edge region and the exposed portion of the source region.