Patent ID: 9024793
Filing Date: 2015-05-05
Classification: G04F,H03K,H03M

Abstract:
1. An oversampling time-to-digital converter, comprising: an input pulse generation circuit configured to generate two pulse signals from two input signals such that a time difference between respective start edges of the two pulse signals is equal to a time difference between respective edges of the two input signals and respective end edges of the two pulse signals match each other; a reference pulse generation circuit configured to generate two pulse signals from a reference clock signal such that a time difference between respective start edges of the two pulse signals is equal to a cycle of the reference clock signal and respective end edges of the two pulse signals match each other; a swap circuit configured to receive the two pulse signals output from the reference pulse generation circuit and to swap the received two pulse signals in accordance with a control signal to output the pulse signals; a multiplexer configured to receive the two pulse signals output from the input pulse generation circuit and the two pulse signals output from the swap circuit and to selectively output the two pulse signals output from the input pulse generation circuit or the swap circuit; a time-to-current conversion circuit configured to output two pulse currents in accordance with respective pulse widths of the two pulse signals output from the multiplexer; a current mirror circuit configured such that one of the two pulse currents is connected to an input terminal of the current mirror circuit and the other of the two pulse currents is connected to an output terminal of the current mirror circuit; an integration circuit configured to integrate a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit; and a comparison circuit configured to compare an output signal of the integration circuit to a threshold voltage, wherein an output signal of the comparison circuit is given as the control signal to the swap circuit.