Patent ID: 9064977
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method for fabricating stacked microelectronic packages, comprising: bonding upper and lower package layers in a stacked relationship, each package layer including a molded package layer body, a microelectronic device embedded within the molded package layer body, and package edge conductors electrically coupled to the microelectronic device and extending to at least one sidewall of the package layer; after bonding the upper and lower package layers, applying a flowable conductive material on sidewalls of the upper and lower package layers and contacting the package edge conductors; and removing selected portions of the flowable conductive material to define, at least in part, a plurality of sidewall conductors electrically coupled to the package edge conductors and electrically interconnecting the microelectronic devices within the upper and lower package layers wherein removing comprises forming openings extending vertically through the flowable conducive material to electrically isolate adjacent ones of the sidewall conductors interconnecting the microelectronic devices within the upper and lower package layers.