Patent ID: 6985823
Filing Date: 2006-01-10
Classification: H04B

Abstract:
1. A system for determining a jitter tolerance of an optoelectronic device, comprising: a generation circuit configured to generate a first sequence of bits and to transmit said first sequence of bits to a delay circuit configured to individually transmit each of said bits in said first sequence of bits to said opto-electronic device, each bit of said first sequence of bits subject to a delay prior to being transmitted to said opto-electronic device; and comparison circuitry configured to receive a second sequence of bits from said optoelectronic device, said second sequence of bits being derived by said opto-electronic device from said first sequence of bits; wherein said comparison circuitry compares said second sequence of bits to said first sequence of bits and wherein said jitter tolerance of said opto-electronic device is determined by reference to said comparison.