Patent ID: 8916419
Filing Date: 2014-12-23
Classification: H01L

Abstract:
1. A semiconductor package assembly process, comprising: applying an adhesive material to a substrate having one or more dies attached thereon, the substrate having an upper surface, at least one die of the one or more dies having a top surface, the upper surface of the substrate being offset from the top surface of the at least one die of the one or more dies, and the adhesive being applied on a periphery of the upper surface of the substrate; applying a thermal interface material (TIM) on the top surface of the at least one die of the one or more dies; and positioning a lid over the at least one die of the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier, to encapsulate the at least one die of the one or more dies; wherein the adhesive material and the TIM are concurrently forced out of a dispenser to apply the adhesive material on the periphery of the upper surface of the substrate and to apply the TIM on the top surface of the at least one die of the one or more dies.