Patent ID: 7245332
Filing Date: 2007-07-17
Classification: G02F,H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate wire on an insulating substrate, the gate wire including gate lines, and first and second gate electrodes connected to the gate lines and spaced apart from each other by a predetermined distance forming a gate insulating layer; forming first and second semiconductor layers; forming a data wire, the data wire including first and second data lines intersecting the gate lines to define pixel areas and spaced apart from each other by a predetermined distance, first and second source electrodes branched from the first and the second data lines, and first and second drain electrodes respectively facing the first and the second source electrodes; forming a passivation layer with at least one contact hole; and forming a pixel electrode connected to the first and the second drain electrodes, wherein the first drain electrode and the second drain electrode are connected to each other and connected to the pixel electrode through the at least one contact hole.