Patent ID: 9183329
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method for simulating and re-simulating behavior of a circuit comprising at least one high-level circuit module and at least one low-level circuit module, wherein each high-level circuit module is represented by a high-level design model and each low-level circuit module is represented by a low-level design model, wherein the low-level circuit module has a plurality of output driving port signals capable of outputting data from the low-level circuit module and a plurality of input receiving port signals capable of inputting data to the low-level circuit module, the method comprising the steps of: a. compiling each high-level design model into a corresponding high-level executable model for simulating behavior of the at least one high-level circuit module and compiling each low-level design model into a corresponding low-level executable model for simulating behavior of the at least one low-level circuit module; b. generating a first replay engine for a first low-level circuit module of the at least one low-level circuit module according to the output driving port signals of the first low-level circuit module, wherein the first replay engine for the first low-level circuit module is generated without using any simulated data and without using any emulated data; c. performing an initial simulation of circuit behavior, comprising executing the high-level executable models and the low-level executable models and recording data representing behavior of the output driving port signals of the first low-level circuit module in response to the input receiving port signals of the first low-level circuit module; and d. performing a replay simulation of circuit behavior, comprising executing the high-level executable models, the first replay engine to replace the low-level executable model corresponding to the first low-level circuit module, and the low-level executable models which are not replaced, wherein the first replay engine simulates behavior of the output driving port signals of the first low-level circuit module in response to the data recorded during the initial simulation that represents the behavior of the output driving port signals of the first low-level circuit module.