Patent ID: 6444527
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method of operating a transistor formed on a semiconductor substrate, the transistor having a heavily doped drain region directly overlain by a lightly doped body region which is directly overlain by a heavily doped source region, with a P-N junction formed between the drain region and the body region and between the body region and the source region and a gate electrode extending through the source region into the body region, the method comprising the acts of:inducing a blocking state of the transistor by fully depleting the body region under an applied drain-source voltage and zero applied gate electrode to source region voltage, the body region having a uniform doping concentration and the gate electrode doped to have a conductivity type the same as a conductivity type of the body region, and opposite a conductivity type of the source region and the drain region; and inducing an on-state of the transistor, the gate electrode to source region voltage being greater than a predetermined threshold voltage of the transistor, thereby providing conduction through the body region due to an inversion adjacent the gate electrode in the body region, the source region overlying all of the body region and thereby the body region is electrically floating, and not in electrical contact with any structures except the source region and the semiconductor substrate; wherein a leakage current between the drain region and the source region in the blocking state is limited by a gate electrode-enhanced depletion barrier.