Patent ID: 8578071
Filing Date: 2013-11-05
Classification: G06F

Abstract:
1. An information processing apparatus comprising: a plurality of processors configured to form a pipeline; a plurality of communication units configured to transfer communication data between a processor in an upstream stage of the pipeline and a processor in a downstream stage and to temporarily store the communication data output from the processor in the upstream stage to the processor in the downstream stage into an internal FIFO buffer; and a memory configured to be accessible from each of the processors and each of the communication units, wherein each of the processors includes a generation unit configured to output, when sending a command to the processor in the downstream stage, communication data including an address of data which exists on the memory and was used for generation of the command, and identification information indicating whether the command exists at the address within the memory, wherein each of the communication units includes: a DMA control unit configured to control a DMA access to the memory; an input unit configured to execute input processing of analyzing the identification information in the communication data input from the processor in the upstream stage and, if it is determined that the command in the communication data does not exist in the memory, deleting the address from the communication data, and, if it is determined that the command in the communication data exists in the memory, deleting the command from the communication data and sending the communication data without the address or the command to the DMA control unit to transfer the communication data to the memory; and an output control unit configured to execute output processing of, when an empty space occurs in the buffer, acquiring the communication data DMA-transferred to the memory from the memory by the DMA control unit, analyzing the acquired identification information in the communication data, and, if it is determined that a command is contained in the communication data, outputting the command in the communication data to the buffer and, if it is determined that an address is contained in the communication data, acquiring the command from the memory by the DMA control unit using the address in the communication data to output the acquired command to the buffer; wherein the input control unit is configured to execute processing of, when an empty space exists in the buffer, sending data input from the processor in the upstream stage by deleting the address from the communication data to the output control unit and, when no empty space exists in the buffer, sending identification information indicating DMA-transfer of the communication data to the memory, to the output control unit as well as the input processing, and wherein the output control unit is configured to analyze, when receiving data from the input control unit, the identification information in the data and, if the identification information is not identification information indicating the DMA-transfer of the communication data to the memory, when an empty space is generated in the buffer, to output the command in the data to the buffer and, if the identification information is identification information indicating the DMA-transfer of the communication data to the memory, to execute the output processing.