Patent ID: 8847646
Filing Date: 2014-09-30
Classification: G11C

Abstract:
1. A semiconductor integrated circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, the semiconductor integrated circuit comprises: a first data clock adjusting circuit that outputs a first clock signal to an outside of the semiconductor integrated circuit via the first terminal; a first phase controlling circuit that is capable of controlling a phase of the first clock signal output from the first data clock adjusting circuit and superposing a jitter on the first clock signal; a second data clock adjusting circuit that receives the first clock signal from the outside of the semiconductor integrated circuit via the second terminal and outputs a second clock signal; a second phase controlling circuit that controls a phase of the second clock signal output from the second data clock adjusting circuit; a data generating circuit that generates a test data signal in a test operation; a first data input/output circuit that outputs the test data signal to the outside of the semiconductor integrated circuit via the third terminal in synchronization with the first clock signal in the test operation; a second data input/output circuit that strobes the test data signal input thereto from the outside of the semiconductor integrated circuit via the fourth terminal in synchronization with the second clock signal in the test operation; a cycle adjusting circuit that is capable of, in the test operation, latching the test data signal generated by the data generating circuit and adjusting a cycle in which the latched test data signal is output; a data comparing circuit that compares data of the test data signal output from the cycle adjusting circuit and data of the test data signal strobed by the second data input/output circuit and detects an error bit; a counter that counts the number of error bits detected by the data comparing circuit; and a result outputting circuit that outputs an analysis result based on the number of the error bits counted by the counter.