Patent ID: 6199091
Filing Date: 2001-03-06
Classification: G06F

Abstract:
An N-stage carry skip adder, said N being an integer of 3 or more, comprising:a plurality of ripple adders, wherein at least one part of said plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group, and if a group includes a plurality of ripple adders, a carry signal is transferred between ripple adders in said group;a circuit for calculating C=C2+F*C1, wherein said C1 denotes a carry signal from said one group to said one upper group, and said F denotes a signal indicating whether or not outputs of all adders in said one upper group are 1s, and said C2 denotes a carry signal associated with the most upper ripple adder in said one upper group, andwherein if a group includes three or more ripple adders, said three or more ripple adders are organized into a plurality of groups at N-2 levels;a circuit for calculating C2.sub.1 =C4+F2.sub.0 *C3.sub.0 ; anda circuit for calculating C2.sub.n+1 =C2.sub.n +F2.sub.n *C3.sub.n, wherein 1.ltoreq.n.ltoreq.N-2, and C2.sub.N-1 =C2, and said C3.sub.0 denotes a carry signal transferred to said most upper ripple adder from a ripple adder in a group at a level 1 to which said most upper ripple adder belongs, and said level 1 is the lowest level, and said C3.sub.n (1.ltoreq.n.ltoreq.N-2) denotes a carry signal transferred to a group at a level n to which said most upper ripple adder belongs from an adjacent group at said level n, and said C4 denotes a carry signal of said most upper ripple adder, and said F2.sub.0 denotes a signal indicating whether or not outputs of all adders in said most upper ripple adder are 1s, and said F2.sub.n denotes a signal indicating whether or not outputs of all adders upper than a ripple adder associated with a circuit outputting said C3.sub.n and up, to said most upper ripple adder are 1s.