Patent ID: 6920526
Filing Date: 2005-07-19
Classification: G06F

Abstract:
1. A dual bank FIFO memory buffer, comprising: a first bank of memory elements operable to buffer memory data; a second bank of memory elements operable to buffer memory data; write control address logic operable to store selected memory data in memory elements with selected addresses; a first write pointer associated with the first bank of memory elements, the first write pointer operable to allow received data to be written to the first bank of memory elements when a second write pointer is in a null state; a second write pointer associated with the second bank of memory elements, the second write pointer operable to allow received data to be written to the second bank of memory elements when the first write pointer is in a null state; write control timing logic operable to selectively grant write access to the banks of memory elements at predetermined times by enabling the first and second write pointers at times dependent on received strobe signal preamble timing; read control logic operable to read data stored in the first and second banks; a first port connecting the dual bank FIFO memory buffer to a memory; and a second port connecting the dual bank FIFO memory buffer to a memory controller.