Patent ID: 7526395
Filing Date: 2009-04-28
Classification: G01R

Abstract:
1. A logic analyzer, comprising: a clock channel, wherein said clock channel receives a signal under test from a probe connected to a circuit under test, and provides a clock signal at an output; a plurality of associated data channels, wherein each data channel receives said signal under test from said probe connected to said circuit under test, and provides a logic signal at an output; said clock channel including a clock channel digitizer that receives said signal under test and digitizes said signal under test to produce a series of multi-bit clock samples; and each of said data channels including a data channel digitizer that receives said signal under test and digitizes said signal under test to produce a series of multi-bit data samples; a clock channel interpolator receiving said multi-bit clock samples and resampling said multi-bit clock samples prior to storage in a deep memory; and each of said data channels including a data channel interpolator receiving said multi-bit data samples and re-sampling said multi-bit data samples in accordance with said re-sampled multi-bit clock samples to determine logic level of said signal under test at precise times prior to storage of a signal indicative of said logic levels in said deep memory.