Patent ID: 6618294
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A method of performing an erase operation on a flash memory block comprising:pre-charging flash memory cells arranged in rows in the block to a predetermined level; applying at least one first stage erase pulse to the block; verifying if each memory cell is erased by row after each first stage erase pulse is applied to the block; counting a first number of pulses applied to the block, wherein the first number of pulses applied to the block is the number of pulses used to verify a majority of rows in the block have been erased; calculating a second number based on a fraction of the first number, wherein the second number is a maximum number of additional second stage erase pulses that may be applied to the block to try and erase the memory cells in the rows not yet verified as being erased; applying at least one second stage erase pulse to the block; verifying if each memory cell is erased by row after each second stage erase pulse is applied to the block; and completing erase of the block when either the second number of second stage erase pulses have been applied to the block or all the rows have been verified as being erased.