Patent ID: 8951857
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising the steps of: in a main implantation, implanting ions into a wafer to form source/drain junctions of first transistors in a first portion in a first predetermined region of the wafer and source/drain junctions of second transistors in a second portion of a second predetermined region of the wafer; and in an additional implantation, additionally implanting ions into only source/drain junctions of the first transistors to compensate for a difference in threshold voltage of the first transistors and threshold voltage of the second transistors, wherein the source/drain junctions of the first transistors in the first portion is implanted by the main implantation and the additional implantation, wherein the source/drain junctions of the second transistors in the second portion is implanted by only the main implantation and is not implanted by the additional implantation.