Patent ID: 6326253
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method for fabricating a semiconductor device comprising a MIS transistor and a bipolar transistor, the bipolar transistor including: an emitter diffused layer of a second conductivity type; and a collector diffused layer of the first conductivity type,the method comprising the steps of:(a) providing an isolating region on a semiconductor substrate to divide a region where the bipolar transistor is to be formed from a region where the MIS transistor is to be formed, and to divide a region of the semiconductor substrate, where the bipolar transistor is to be formed, into an active region and a collector-forming region;(b) after the step (a), forming a gate insulating film on the semiconductor substrate;(c) after the step (b), retaining the gate insulating film only in the entire region where the MIS transistor is formed by removing the gate insulating film on the region where the bipolar transistor is formed;(d) after the step (c), forming an amorphous semiconductor film, containing a dopant of the second conductivity type, over the semiconductor substrate, whereby the gate insulating film is formed in the entire region where the MIS transistor is formed, and chemical oxide film is removed from the surfaces of the collector-forming region and active region;(e) forming an upper insulating film over the entire surface of the semiconductor film;(f) patterning the upper insulating film and the semiconductor film to form a base electrode of the semiconductor film over the active region, the base electrode having an opening for emitter electrode and an outer edge positioned in the isolating region, and at the same time forming the gate electrode made of the semiconductor film on the region where the MIS transistor is formed.