Patent ID: 9165612
Filing Date: 2015-10-20
Classification: G11C

Abstract:
1. A memory comprising: a first cell block comprising a plurality of first word line groups each having two or more first word lines, and one or more first redundancy word line groups each having two or more first redundancy word lines and corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups each having two or more second word lines, and one or more second redundancy word line groups each having two or more second redundancy word lines and corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section, wherein, in the first cell block, the first word lines are sequentially disposed, and the first redundancy word lines are sequentially disposed after a last-disposed first word line; and in the second cell block, the second word lines are sequentially disposed, and the second redundancy word lines are sequentially disposed after a last-disposed second word line.