Patent ID: 6242300
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method for forming an embedded DRAM device with a mixed mode capacitor in the logic, comprising the steps of:a. providing a semiconductor structure having a logic area and a memory area; said logic area and said memory area being separated by an isolation structure; said logic area having thereon a second isolation structure;b. forming a first dielectric layer over said semiconductor structure, and forming a first polysilicon layer on said first dielectric layer;c. patterning said first polysilicon layer and said first dielectric layer to form an opening over said memory area;d. forming an implant mask over said first polysilicon layer; said implant mask having an opening over said second isolation structure;e. implanting impurity ions into said first polysilicon layer through said opening in said implant mask;f. removing said implant mask;g. forming a second dielectric layer over said semiconductor structure and said first polysilicon layer;h. forming a second polysilicon layer on said second dielectric layer; forming a silicide layer on said second polysilicon layer; and forming a hard mask layer on said silicide layer;i. patterning said second polysilicon layer; said silicide layer; and said hard mask layer to define a top electrode for a mixed mode capacitor over said second isolation structure in said logic area and gates in said memory area; andj. patterning said second dielectric layer to form a capacitor dielectric and patterning said first polysilicon layer to define gate structures and bottom electrode for a mixed-mode capacitor in said logic area.