Patent ID: 6222265
Filing Date: 2001-04-24
Classification: H01L,H05K,Y10S,Y10T

Abstract:
A semiconductor assembly, comprising:a base substrate having a first surface including a plurality of bond pads;a first stacked substrate having a first surface and a second surface, at least one of said first surface and second surface of said first stacked substrate including a plurality of bond pads;a first semiconductor die disposed on said first surface of said first stacked substrate, said first semiconductor die having an active surface, a second surface, and a plurality of bond pads located on the active surface;a second semiconductor die having a first surface facing said first surface of said base substrate, said first surface having a plurality of bond pads located thereon, said second semiconductor die disposed on said second surface of said first stacked substrate;at least one first intercoupler connecting said at least one of said plurality bond pads of said first surface of said first stacked substrate and said plurality of bond pads on said second surface of said first stacked substrate, and at least one of said plurality of bond pads of said first semiconductor die;at least one second intercoupler connecting said base substrate and said first stacked substrate, said at least one second intercoupler positioning said first stacked substrate substantially parallel to said base substrate;a second stacked substrate having a first surface including a plurality of bond pads and having a second surface including a plurality of bond pads;at third semiconductor die disposed on said first surface of said second stacked substrate, said third semiconductor die having a plurality of bond pads located thereon;a fourth semiconductor die disposed on said second surface of said second stacked substrate, said fourth semiconductor die having a plurality of bond pads located thereon;at least one fourth intercoupler connecting said at least one of said plurality of bond pads on the first surface of said second stacked substrate and said plurality of bond pads of said second surface of said second stacked substrate, and at least one of said plurality of bond pads of said fourth semiconductor die; andat least one fifth intercoupler connecting said second stacked substrate and one of said first surface of said first stacked substrate, said second surface of said first stacked substrate, and said first surface of said base substrate, said at least one fifth intercoupler separating one of said second stacked substrate from said first surface of said first stacked substrate, said second surface of said first stacked substrate, or said first surface of said base substrate.