Patent ID: 8022475
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A transistor comprising: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; and a buried layer formed between the semiconductor substrate and the semiconductor layer, wherein the transistor is configured to allow an electric current to flow through the transistor in a direction of stacking of a stack of the semiconductor substrate, the buried layer and the semiconductor layer, the buried layer comprises a first impurity-doped layer having a first peak impurity concentration of a first impurity and a second impurity-doped layer having a second peak impurity concentration of a second impurity, the second peak impurity concentration is lower than the first peak impurity concentration, and the second impurity-doped layer overlaps the first impurity-doped layer, extends further into the semiconductor layer than the first impurity-doped layer and extends further into the semiconductor substrate than the first impurity-doped layer.