Patent ID: 8928379
Filing Date: 2015-01-06
Classification: G01R,H03K,H03M

Abstract:
1. A minimal power latch circuit, comprising: a first latch and a second latch, said first latch having an input at which to receive a comparator signal C, an input at which to receive a code value signal D, and an input at which to receive a signal Q said second latch having an input at which to receive said comparator signal C, an input at which to receive said code value signal D, and an input at which to receive said signal Q said first latch and said second latch constructed to operate according to a pair of equations in which a first latch equation is given by said comparator signal C representing a comparison as a function of time of a signal to be measured and a monotonically varying reference signal; said code value signal D representing a time increment measured from a start of said monotonically varying reference signal; and a selected one of said signal Q