Patent ID: 6486032
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A method for fabricating control gate and floating gate of a flash memory cell, comprising:providing a semiconductor substrate; forming a field insulating layer on the surface of the semiconductor substrate to define an active area; forming a first insulating layer on the substrate within the active area; forming a first conductive layer on the first insulating layer; forming a masking layer on the first conductive layer; removing part of the first masking layer to define a first opening and to expose the surface of the first conductive layer; forming a first gate insulating layer on the exposed surface of the first conductive layer by oxidation; removing part of the first masking layer to expose the surface of the first conductive layer; forming a sacrificial layer on the first conductive layer to cover the first gate insulating layer; removing the sacrificial layer between the neighboring first gate insulating layers within the active area to define a second opening and to expose surfaces of the first conductive layer and part of the first gate insulating layer; using the remaining sacrificial layer and the first gate insulating layer as a hard mask to remove the first conductive layer and the first insulating layer within the second opening to form another opening and to expose the surface of the substrate, wherein the opening together with the second opening form a third opening; forming a second insulating layer on surface of the remaining sacrificial layer to fill the third opening; using the remaining sacrificial layer as a stop layer to remove the second insulating layer remaining on the surface of the sacrificial layer without removing the part within the third opening, which forms an isolating plug; removing the remaining sacrificial layer to expose the remaining first conductive layer and a partial surface of the first gate insulating layer; using the first gate insulating layer and the insulating plug as hard mask to remove the first conductive layer and the first insulating layer not covered by the first gate isolating layer and the isolating plug, wherein the remaining first conductive layer forms a floating gate and the remaining first insulating layer forms the second gate insulating layer; forming a third insulating layer on surface of the substrate to cover the surface of the first gate insulating layer, the surface and sidewalls of the insulating plug and the sidewalls of the floating gate and the second gate insulating layer; forming a second conductive layer on the surface of the third insulating layer; and using the isolating plug as a stop layer to remove part of the second conductive layer and the third insulating layer to expose the surface of the top part of the insulating plug and surface of the substrate, wherein the remaining second conductive layer forms a control gate and the remaining third insulating layer forms a tunneling oxide.