Patent ID: 7154141
Filing Date: 2006-12-26
Classification: G11C,H01L

Abstract:
1. A flash memory, comprising: a plurality of memory cells, each memory cell having a single transistor having a single control gate, a single floating gate, a single drain and a single source, said plurality of memory cells arranged in an N-row by M-column array, where N and M are integers greater than or equal to one; N word lines, each word line connecting together the control gates of the transistors in a common and corresponding row; M bit lines, each bit line connecting together the drains of transistors in a common and corresponding column; wherein first and second memory cells of the plurality of memory cells are programmed by applying a first voltage to the respective control gates of the first and second memory cells, applying a second voltage to the respective sources of the first and second memory cells and grounding the respective drains of the first and second memory cells, wherein the sources of the first and second memory cells are coupled to a common node, wherein the sources of a plurality of memory cells are connected together to a common node, wherein each of the sources of the memory cells includes a first doped region of a first conductivity type and a second doped region of the first conductivity type to provide a graded profile that is less abrupt than the drain wherein the control gate is applied with a first voltage of 8.5 volts or less and the source region is applied with a second voltage of 4.5 volts or less to program the non-volatile device.