Patent ID: 6061765
Filing Date: 2000-05-09
Classification: G06F

Abstract:
A computer system, comprising:A) a first central processing unit, including a cache and a victim data buffer coupled to said cache, for storing victim data evicted from said cache, said victim data buffer and said cache comprising a cache subsystem;B) system control logic coupled with said central processing unit, said central processing unit issuing a command to said system control logic to write said victim data back to a main memory;C) a first flag associated with said victim data buffer, said first flag indicative of a first portion of a release condition of said victim data buffer when an address comparison has been performed by said central processing unit for data targeted by pending probe messages stored at a top of a probe queue coupled to said central processing unit and said targeted data has been sent to said system control logic for transfer to a second central processing unit;D) a second flag associated with said victim data buffer, said second flag indicative of a second portion of said release condition when said victim data is transferred from said cache to said victim data buffer and when an address comparison has been performed for data targeted by probe messages that have passed a serialization point of said computer system prior to a time when a command for writing said victim data passed said serialization point.