Patent ID: 7117277
Filing Date: 2006-10-03
Classification: G06F

Abstract:
1. A method of modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block, the bus interconnect block providing a plurality of connections via which one or more master devices may access one or more slave devices, each connection comprising one or more paths, each path having one or more path portions separated by storage elements, each storage element, during a particular clock cycle, for outputting a stored value of a signal while a new value of that signal is stored in that storage element, the method comprising the steps of: a) selecting one or more candidate paths from said paths; b) for each candidate path, applying predetermined criteria to determine whether modification of the number of storage elements in said path will assist in meeting the requirement for said chosen characteristic; and c) modifying the number of storage elements in each candidate path for which it is determined at said step (b) that modification will assist in meeting the requirement for said chosen characteristic.