Patent ID: 9094185
Filing Date: 2015-07-28
Classification: H03L

Abstract:
1. A digital phase locked loop, comprising: a phase acquisition module configured to output a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference; a phase offset write module configured to convert a phase offset commanded from an external source into a phase offset correction value expressed with respect to said internal phase reference; a phase offset controller for summing said phase offset correction values from said phase offset write module to produce a second phase value; an adder for adding said second phase value to said first phase value to produce a third phase value; a digital controlled oscillator (DCO) configured to output a fourth phase value expressed with respect to said internal phase reference; a phase detector for outputting a fifth phase value representing the difference between said third and fourth phase values; a loop filter configured to derive a frequency offset for said DCO based on said fifth phase value; and an output module configured to generate one or more output clocks from said fourth phase value.