Patent ID: 6518175
Filing Date: 2003-02-11
Classification: H01L,Y10S

Abstract:
A method of fabricating reduced feature size in an integrated circuit, the integrated circuit including a patterned photoresist layer provided over a substrate, the patterned photoresist layer being patterned with radiation at a lithographic wavelength and in accordance with a pattern on a mask or reticle, the method comprising the steps of:providing an electron beam to at least one area of an aperture included in the patterned photoresist layer, the aperture having sidewalls and a width; transforming the sidewalls in response to the electron beam, thereby creating shrink areas, wherein the electron beam at least partially liquefies or plasticizes molecules on the sidewalls to form the shrink areas; and forming a feature in the substrate in accordance with the transformed sidewalls of the aperture.