Patent ID: 7366005
Filing Date: 2008-04-29
Classification: G09G,G11C

Abstract:
1. A ferroelectric memory device comprising: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward another end thereof, in a second direction, which is a direction substantially opposite to the first direction; a plurality of second memory cells, which are connected to the second bit line and store predetermined data; a sense amplifier, which is connected to the one end of the first bit line and the one end of the second bit line, and which amplifies data which have been stored at the first memory cells and the second memory cells; a latch circuit, which is connected to the other end of the first bit line, and which latches data that the sense amplifier has amplified; a data bus, which transfers data which are to be stored at the first memory cells and the second memory cells; and a first switch, which is connected to the other end of the second bit line and which switches between connecting and not connecting the second bit line with the data bus.