Patent ID: 7247905
Filing Date: 2007-07-24
Classification: H01L

Abstract:
1. A memory array comprising: at least one first-type memory device, each of said at least one first-type memory device comprising a first transistor, a first underlying capacitor, a first buried strap, and a first collar region with a first vertical length which is substantially constant throughout the periphery of said first collar region, wherein said first buried strap is located at a first depth and is positioned on said first collar region and is in electrical contact with both said first transistor and said first underlying capacitor; and at least one second-type memory device, each of said at least one second-type memory device comprising a second transistor, a second underlying capacitor, an offset buried strap, and a second collar region with a second vertical length which is substantially constant throughout the periphery of said second collar region, wherein said offset buried strap is located at a second depth that is different from said first depth and is positioned on said second collar region and is in electrical contact with both said second transistor and said second underlying capacitor, and said second vertical length is equal to said first vertical length.