Patent ID: 6768686
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A read/write amplifier for a DRAM memory cell, which, for evaluation of the information content of at least one DRAM memory cell, is connected or can be connected to a plurality of bit lines and to a plurality of reference bit lines, which in each case form a bit line pair, having a number of components for assessment, amplification and forwarding of voltage signals read from the bit lines and reference bit lines, in which case the read/write amplifier has a first read/write amplifier element and a second read/write amplifier element separate therefrom and in that the individual amplifier elements are divided between the two read/write amplifier elements, wherein the first read/write amplifier element is located at a first end of the bit line pairs and the second read/write amplifier element is located at a second end of the bit line pairs, and wherein the bit line pairs are activated or can be activated with the read/write amplifier.