Patent ID: 6353574
Filing Date: 2002-03-05
Classification: G11C

Abstract:
A semiconductor memory device for outputting data at a high speed, comprising:global input/output (I/O) lines; complementary global I/O lines; and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and said complementary global I/O lines to store the data, said pipe register comprising: a data detecting means, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating means for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage means for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting means.