Patent ID: 6656802
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate (1) including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source (S) and drain (D) electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein:the gate recess and the gate are manufactured according to predetermined respective gate recess width value (Wri) and gate length value (LGo) in order that the access region, defined between the gate (G) and the edge (31) of the gate recess (A4), has an access region width (2&Dgr;o), derived from said predetermined respective values (Wri, LGo), which is sufficiently small to permit the transistor of functioning according to saturation current characteristics that have substantially continuous slopes, wherein only one photo-resist layer is used in forming the gate recess and the gate to the respective gate recess width value (Wri) and gate length value (LGo), the access region width (2&Dgr;o) being between 0.07 &mgr;m and 0.12 &mgr;m.