Patent ID: 9166832
Filing Date: 2015-10-20
Classification: H04L

Abstract:
1. A receiver circuit for a data link, the receiver circuit comprising: a linear equalizer for receiving an input data signal and outputting a linearly-equalized signal; a slicer circuit for receiving the linearly-equalized signal and outputting a quantized signal; a feedback filter having multiple taps for receiving the quantized signal and outputting a feedback signal; a summation node for adding the feedback signal to the linearly-equalized signal; and adaptation circuitry for adapting tap weights of the feedback filter with variable update resolution, wherein the adaptation circuitry operates in a coarse resolution mode followed by a fine resolution mode, wherein the fine resolution mode has a smaller step size than the coarse resolution mode for adapting the tap weights of the feedback filter, and wherein the adaptation circuitry uses a convergence detection criterion comprising a maximum step variation being greater than a threshold step variation to switch from the coarse resolution mode to the fine resolution mode.