Patent ID: 6274910
Filing Date: 2001-08-14
Classification: H01L

Abstract:
An ESD protection circuit fabricated on a semiconductor block on an insulating layer overlying a supporting substrate, said ESD protection circuit comprising:a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in said semiconductor block, where said first N-type doped region is more heavily doped than said second N-type doped region and first P-type doped region is more lightly doped than said second p-type doped region; anda stacked structure including a dielectric layer and a conductive layer sequentially overlying said first P-type doped region and said second N-type doped region;wherein said first N-type doped region and said second P-type doped region are respectively coupled to a relatively low voltage and a relatively high voltage during operation.