Patent ID: 8988941
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A three dimensional charge-storage memory formed in multiple physical levels disposed above a substrate comprising: a plurality of NAND strings that extend in a direction that is perpendicular to a surface of a substrate, each of the plurality of NAND strings having a select transistor at each end; a plurality of select lines that are connected to gates of the select transistors to selectively connect the plurality of strings to conductive lines; resolving circuits that are configured to resolve a threshold voltage of a sample select transistor; and charge-changing circuits that are configured to apply conditions to the sample select transistor that are sufficient to change an amount of charge located in the sample select transistor and thereby change the threshold voltage of the sample select transistor to within a desired threshold voltage range that is confirmed by the resolving circuits, the charge-changing circuits further configured to subsequently apply the conditions to other select transistors without confirming by the resolving circuits that the other select transistors have threshold voltages within the desired threshold voltage range.