Patent ID: 6812768
Filing Date: 2004-11-02
Classification: G09G,H03K

Abstract:
An input circuit which receives first and second signals at its inputs and outputs an output signal having a level different from the first and second signals, comprising:a first transistor whose output current is controlled by the level of the first signal; second and third transistors whose output currents are controlled by the level of the second signal; a first current mirror circuit which receives a current output of the first transistor at its input and includes a first switch; a second switch which receives a current output of the second transistor at its input; and a second current mirror circuit which receives an output of the second switch at its input, wherein the first current mirror circuit performs its normal operation when the first switch is turned on, and is constructed so that a period during which the first current mirror circuit outputs a current occurs when the first switch is turned off, wherein the second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit, wherein a current output of the third transistor and a current output of the first current mirror circuit are connected and outputted as the output signal, and wherein the first and second switches are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.