Patent ID: 8555123
Filing Date: 2013-10-08
Classification: G06F

Abstract:
1. A test device for the SoC test architecture, comprising: m cores, wherein m is an integer, and i is an integer between 1 and m−1, wherein test outputs of a first core are serial-connected to test inputs of a second core, and test outputs of an i a test input port, wherein the test input port is serial-connected to test inputs of the first core of the m cores; a test output port, wherein the test output port is serial-connected to test outputs of an m a register, comprising m bits corresponding to the m cores; and m user defined logics, each connected to a corresponding bit of the register and a corresponding one of the m cores, receiving a plurality of test control signals, receiving the corresponding bit of the register to change values of test control signals and outputting the changed test control signals, wherein the changed test control signals of each of the m user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated; wherein in each of the m cores which are selected to change the test instructions by the changed test control signals, the test instruction is shifted from the test input to a wrapper instruction register; wherein in each of the m cores which are not selected to change the test instructions by the changed test control signals, test data is shifted from the test input to the test output through a bypass register.