Patent ID: 6477596
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A bus cycle controlling method which, when write or read access is made following a previous access of a first device in a current bus cycle in a successive access operation for a second device, considers an output disable time of the first device being accessed in the current bus cycle, to delay activation of a following bus cycle for the following write or read access, when such delay is necessary to avoid data conflicts between data of the previous access and read or write data of the following read or write access caused by a long output disable time, the delay in activating the following bus cycle being accomplished by inserting a preset number of necessary idle state according to the output disable time of said first device, and to prohibit insertion of said number of necessary idle state when no data conflict occurs, wherein the bus cycle controlling method does not insert an idle state during successive accesses when the first and second devices are the same single device.