Patent ID: 8294209
Filing Date: 2012-10-23
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of active pillars protruding from a semiconductor substrate, the plurality of pillars being arranged in a plurality of columns; a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode; a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode; a first body region in the active pillar adjacent to the first gate electrode; a second body region in the active pillar adjacent to the second gate electrode; a first source/drain region in the active pillar between the first body region and the semiconductor substrate; a second source/drain region in the active pillar between the second body region and the first body region; a third source/drain region in the active pillar, the second body region being between the second and third source/drain regions; and an insulating line having flat faces contacting the first gate electrode and the second gate electrode, the insulating line extending continuously between adjacent columns of the active pillars.