Patent ID: 6515920
Filing Date: 2003-02-04
Classification: G11C

Abstract:
A semiconductor data storing circuit device, comprising:a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns; a data input/output circuit which is arranged in the memory core to be used in a normal operation of the memory cell array and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array; and a checking circuit which is arranged in the memory core to be used in a test operation performed in manufacturing of the memory cell array and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array on condition that the second predetermined number of columns differs from the first predetermined number of columns.