Patent ID: 6346366
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A method for making a guard ring on a merged DRAM integrated circuit comprising the steps of:providing a semiconductor substrate having logic regions and memory regions having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas that includes a gate oxide on said device areas; depositing an amorphous silicon layer on said substrate; patterning said amorphous silicon layer to leave a blanket portion over said logic regions and removing portions over said memory regions; depositing a stacked film on said substrate; forming a first photoresist etch mask for etching FET gate electrodes in said stacked film over said memory regions, and concurrently forming portions of said first photoresist mask extending over edges of said amorphous silicon layer for etching guard rings; plasma etching to form said FET gate electrodes and concurrently forming said guard rings in said stacked film over said edges, whereby said guard rings are sufficiently wide to prevent peeling of said guard rings; forming a second photoresist etch mask and plasma etching to form gate electrodes in said amorphous silicon layer over said logic regions; depositing a conformal insulating layer and etching back to form sidewall spacers on said FET gate electrodes formed in said amorphous silicon and in said stacked film, and to concurrently form sidewall spacers on said guard rings.