Patent ID: 6376348
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A process for forming a reliable polycide gate conductive layer with decreased thickness and lower sheet resistance over a portion of a silicon substrate comprising:a) depositing over the portion of the substrate a layer of polysilicon that is doped with dopants to a concentration greater than the concentration that would produce a metal-rich interface with a superposed layer of a metal silicide; b) annealing the substrate at a temperature and for a time sufficient to outdiffuse dopants from the polysilicon layer to provide a top surface layer in which the dopant concentration is reduced below a concentration that would form a metal-rich interface layer with a superposed layer of a metal silicide; and c) depositing a metal silicide layer over said top surface of the polysilicon layer in a manner to avoid formation of a metal-rich interface between the polysilicon layer and the metal silicide layer; said annealing is performed at a temperature higher than the temperature at which the polysilicon layer is deposited, and at a pressure lower than the pressure at which the polysilicon layer is deposited.