Patent ID: 6282100
Filing Date: 2001-08-28
Classification: H01L

Abstract:
An IC package comprising:a. a first printed wiring board (first PWB) having an upper surface and a lower surface, and an array of first PWB wire bonding pads on said upper surface,b. a semiconductor intermediate interconnection substrate (IIS) comprising:i. a semiconductor substrate having an upper surface, a lower planar surface, and a center region on said upper surface,ii. an array of IIS interconnection sites in said center region of said upper surface,iii. an array of IIS wire bonding pads surrounding said center region of said upper surface,iv. metallization runners interconnecting said array of IIS interconnection sites to said array of IIS wire bonding pads,c. means for die bonding said lower planar surface of said IIS to the upper surface of said first PWB,d. a single silicon IC chip attached to said IIS and having an array of IC chip interconnection sites on a surface thereof, said array of IC chip interconnection sites bonded to said array of IIS interconnection sites, ande. means for wire bonding said array of IIS wire bonding pads to said array of first PWB wire bonding pads.