Patent ID: 8949680
Filing Date: 2015-02-03
Classification: G01R

Abstract:
1. A data receiver device operative in either of a test mode and a normal mode, the data receiver device comprising: a logic unit configured to detect a current operational mode of the data receiver device, the logic unit configured during the test mode to generate a test pattern signal, receive a test result signal, and compare the test pattern signal with the test result signal to perform a test, the test pattern signal and the test result signal are respective parallel signals; a system frequency control circuit configured during the test mode to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal; an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal through an output pin; and an input terminal configured to serially receive an input signal at an input pin, to recover a data signal and a data clock signal from the input signal based on the output signal, to deserialize the data signal based on the data clock signal, and during the test mode to output the test result signal to the logic unit responsive to the deserialized data signal.