Patent ID: 6442642
Filing Date: 2002-08-27
Classification: G06F,Y02D

Abstract:
An electronic bridge apparatus for providing a first electronic device attached to a high-data throughput bus and a second electronic device attached to a lower-speed peripheral bus, the electronic bridge apparatus comprises:an input bus circuit for receiving a plurality of input bus signals from the high-data throughput bus, the plurality of input bus signals comprise a multi-bit system data bus and a multi-bit system address bus; an input control signal circuit for receiving a plurality of input control signals from the high-data throughput bus, the plurality of input control signals comprises a continuous input BCLK clock signal; an output bus circuit for generating a plurality of output bus signals onto the lower-speed peripheral bus, the plurality of output bus signals comprise a multi-bit peripheral data bus and a multi-bit peripheral address bus; an output size signal circuit for generating one or more output size signals for indicating the number of bits being used for a data transfer over the multi-bit peripheral data bus; an output control signal circuit for generating a plurality of output control signals onto the lower-speed peripheral bus, the plurality of output control signals comprise, a PWRITE write control signal for indicating whether a write operation is occurring, a continuous PCLK clock signal having a rising edge and a falling edge for controlling the transfer of data over the lower-speed peripheral bus, and one or more PSELx signals for indicating the particular cycle of the PCLK signal in which data is to be transferred over the lower-speed peripheral bus; and wherein data is transferred into the second electronic device over the multi-bit peripheral data bus on the rising edge of the PCLK signal during a clock cycle when the PSELx signal is in an active state and the PWRITE signal is in an active state.