Patent ID: 6555015
Filing Date: 2003-04-29
Classification: H05K

Abstract:
A method of manufacturing a printed circuit board having at least two conductor patterns and reducing interfacial shear stresses, comprising:providing a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness, and a bottom layer forming a second major surface opposed to the first major surface, each of the layers comprised of a material etchable in a respective given etchant; disposing a first etch resist on the first surface corresponding to a reverse image of a first conductor pattern; disposing a second etch resist on the second surface corresponding to a reverse image of a second conductor pattern; etching the first and second surfaces in each said respective given etchant to form said first and second conductor patterns; removing the first and second etch resists; securing a compliant adhesive layer comprising a low modulus material to the second surface so that the bottom layer becomes embedded in one major surface of the adhesive layer; securing the other major surface of the adhesive layer to one major surface of a base; and selectively etching the middle layer in said given etchant to isolate selected portions of the first and second surfaces and define interconnect regions therebetween having a height equal to said predetermined thickness; wherein selecting the low modulus material and selecting the thickness of the middle layer are reducing interfacial shear stresses.