Patent ID: 7346884
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. An Integrated Circuit (IC) comprising a transistor embedded silicon based substrate and an interconnect structure including at least three metal layers for power routing purposes and transistor interconnection purposes, the IC having at least one power consuming entity having at least one VDD port for electrical connection to a power net of an IC power supply net and at least one GND port for electrical connection to a ground net of said IC power supply net, said at least one power consuming entity being graphically representable as an exempt area on an IC floorplan of the IC, at least one of said power net and said ground net being constituted by a Sea-of-Supply (SoS) net exclusively occupying a single metal layer of said interconnect structure, and being the logical complement of all the exempt areas bounded by a SoS net boundary itself bounded by the boundary of the IC floorplan.