Patent ID: 6314549
Filing Date: 2001-11-06
Classification: G06F,H03K

Abstract:
A method for reducing the power consumed by a programmable logic array (PLA), comprising the steps of:(a) dividing an original PLA into a plurality of sub-PLA's, wherein each of said sub-PLA's having a plurality of input lines receiving an input data for operating by a logic array to generate a plurality of outputs to a plurality of output lines;(b) providing sub-PLA input means in each sub-PLA for receiving a plurality of sub-PLA input signals, each sub-PLA having a plurality of input lines;(c) providing sub-PLA output means for providing a plurality of sub-PLA output signals;(d) using programmable logic connections in each sub-PLA to define a logic relationship between each of said sub-PLA input signals and each of said sub-PLA output signals;(e) providing sub-PLA input signal storage means and output signal storage means for storing respectively existing sub-PLA input and output signals;(f) providing sub-PLA activity control means for comparing each of said plurality of sub-PLA input signals with each of corresponding existing sub-PLA input signals for turning on a power input of said sub-PLA only when at least one of said plurality of sub-PLA input signals is not identical to each of said corresponding existing sub-PLA input signals;(g) for each of said input lines comparing said logic array in said sub-PLA to find a sub-set of the sub-PLA inputs having identical logic array as shared minterm logic (SML) for identifying said input lines a ""shared minterm inputs"" (SMI) having identical logic array; and(h) simplifying said sub-PLA by disconnecting each of said input lines to said SMI and providing a logic circuit to calculate a value of said SML in a sub-PLA activity control means to replace said input lines disconnected from said sub-PLA.