Patent ID: 6249149
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A logic array block of a programmable logic device, comprising:a clock generation circuit includinga clock generation circuit input node to receive a clock signal,an enable signal input node to receive an enable signal,a clock generation circuit output node, anda digital logic circuit connected between said clock generation circuit input node, said enable signal input node, and said clock generation circuit output node, said digital logic circuit selectively generating an enabled clock signal on said clock generation circuit output node by logically combining said clock signal and said enable signal, wherein said digital logic circuit is configured to initiate said enabled clock signal only after said enable signal has been asserted during a previous clock state of said clock signal; anda set of logic elements, each of said logic elements including a logic element clock input node connected to said clock generation circuit output node such that each logic element of said set of logic elements receives said enabled clock signal from said clock generation circuit.