Patent ID: 6192004
Filing Date: 2001-02-20
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit comprising:a plurality of memory cells for storing data;a clock pulse generator for generating a plurality of clock pulses having different phases during one cycle of a reference clock signal supplied from the exterior;a timing setting circuit for setting a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of said reference clock signal and for outputting latency information according to the set latency;an output controlling pulse switching circuit for respectively outputting said clock pulses as predetermined output controlling pulses in accordance with said latency information; anda data outputting circuit for sequentially and respectively converting parallel data read from said memory cells into serial data and respectively outputting the converted serial data, in synchronization with said output controlling pulses during a predetermined period according to said set latency.