Patent ID: 8593899
Filing Date: 2013-11-26
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of core chips stacked with one another, each of the core chips being configured to receive row and column commands at different timings and each of the core chips including a layer address generating circuit storing a chip address and a row access holding circuit, the chip address being unique among the core chips, wherein in a first operation mode each of the core chips is configured to be controlled such that the row command is executed when the chip address is coincident with a layer address supplied together with the row command, that the row access holding circuit stores a hit information when the row command is executed and that the column command is executed in response to the hit information, and wherein in a second operation mode each of the core chips is configured to be controlled such that the row command is executed when the chip address is coincident with the layer address supplied together with the row command and that the column command is executed when the chip address is coincident with an additional layer address supplied together with the column command.