Patent ID: 9098336
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware thread according to priority rank the priority rank being established in advance for each of the plurality of hardware threads; a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and an execution pipeline that executes an instruction output from the first selector, wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads; further comprising a second scheduler that specifies execution of at least one hardware thread selected in a fixed manner among the plurality of hardware threads in a predetermined first execution period, and outputs a second thread selection signal specifying execution of an arbitrary hardware thread in a second execution period other than the first execution period and a real-time bit signal indicating one of the first execution period and the second execution period.