Patent ID: 6363453
Filing Date: 2002-03-26
Classification: G06F

Abstract:
General purpose parallel computer comprising a plurality of processors (SPU), a plurality of main memory units (M) and a plurality of memory buses (C-BUS), each memory bus comprising at least a data bus (DATA-B), an address bus (ADRS-B) and a control bus (CNTL-B), and each memory bus (C-BUS) on which a single process at a time is executed, is connected at least to a main memory unit (M) and to a processor (SPU) which is redundantly replicated on said memory bus (C-BUS);said computer being characterized in that: each processor (SPU) is reciprocally coupled in a pair to another processor (SPU) belonging to a different memory bus (C-BUS) directly through a pair interconnection (P-P), the two processors sharing at least a group of respective register banks (REG-F) and mutually exchanging context data in response to the execution of pair communication instructions so as to form a single biprocessor unit (DPU); each said memory bus (C-BUS) is linked to a migration structure (A-S) which is directly connected to all the processors (SPU) sharing said memory bus (C-BUS), so as to allow process migration from processor to processor; only one processor (SPU) per memory bus (C-BUS) is active at a time therefore assuming the state of master of said memory bus (C-BUS), all other (SPU) lying inactive in a state slave of the memory bus (C-BUS) but allowing the master-active processor to perform read and write operation on their own register banks (REG-F); in response to migration instructions, a processor (SPU) in the active state transfers process context and control to an inactive-slave destination processor (SPU) of the same memory bus (C-BUS), which becomes the new master-active processor of said memory bus (C-BUS) and restarts computation according to the contents of its register bank (REG-F).