Patent ID: 6279144
Filing Date: 2001-08-21
Classification: G01R,Y10S

Abstract:
A memory array cell comprising:a pair of cross-coupled inverters forming a first latch for storing data, said first latch having an input and an output, wherein the output is connected to a read bit line;true and complement write word and bit line inputs to the first latch;a first set of pass gates connected between the true and complement write word and bit line inputs via gates and the input of said first latch, said first set of pass gates being responsive to a first clock via a second pass gate;a pair of cross-coupled inverters forming a second latch of a Level Sensitive Scan Design (LSSD), said second latch having output connected to an LSSD output for design verification;said second pass gate connected between the output of the first set of pass gates and the input of said first latch, said second pass gate being responsive to said first clock; anda third pass gate connected between the output of said first latch and an input of said second latch, said third pass gate being responsive to a second clock, wherein said first and second clocks being responsive to a black boxing process for incremental verification.