Patent ID: 8069385
Filing Date: 2011-11-29
Classification: G11C

Abstract:
1. A test data controller built into an integrated circuit for testing an array of memory cells of the integrated circuit, comprising: an interface for receiving expected result data for a test; the interface further for receiving address information and control information for writing and reading the expected result data respectively to and from a tile of the array of memory cells and result memory; a data path circuit coupled to the array of memory cells and coupled to the tile; the data path circuit configured to read the expected result data stored in the tile and configured to read the expected result data stored in the result memory; the data path circuit further configured for bit-to-associated bit comparisons of the expected result data read from the tile with the expected result data read from the result memory; the data path circuit coupled to first failure memory and coupled to second failure memory; the data path circuit configured to write a first type of failure indication to the first failure memory responsive to a data 0 being read from the result memory and a data 1 being read from the tile for a bit-to-associated bit comparison failure; and the data path circuit further configured to write a second type of failure indication to the second failure memory responsive to a data 1 being read from the result memory and a data 0 being read from the tile for the bit-to-associated bit comparison.