Patent ID: 7115445
Filing Date: 2006-10-03
Classification: H01L,Y10T

Abstract:
1. A method of fabricating a semiconductor package, comprising the steps of: a) providing a leadframe which includes: b) etching the leadframe such that each of the leads includes a half etched portion which is formed in the lower lead surface, extends to the inner lead end, and defines a generally planar etched lead surface which is disposed in opposed relation to the upper lead surface and extends in generally co-planar relation to the top surface of the die paddle; c) attaching a semiconductor chip to the top surface of the die paddle; d) electrically connecting the semiconductor chip to at least one of the leads; and e) at least partially encapsulating the leadframe and the semiconductor chip with an encapsulation material such that at least a portion of the lower lead surface of each of the leads is exposed in the encapsulation material.