Patent ID: 6175852
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A binary adder for adding a first multiple-bit number to a second multiple-bit number, comprising:a plurality of rows of carry-lookahead circuits, wherein one of said plurality of rows of carry-lookahead circuits includes a plurality of eight-bit group generate circuits and a plurality of eight-bit group propagate circuits, wherein each of said eight-bit group generate circuits generates a generate signal for a corresponding bit location of said multiple-bit numbers, wherein each of said eight-bit group propagate circuits generates a propagate signal for a corresponding bit location of said multiple-bit numbers;a half-sum module for generating a half-sum signal; anda sum/carry module coupled to said half-sum module and to said plurality of rows of carry-lookahead circuits, wherein said sum/carry module generates a sum signal utilizing said half-sum signal, said generate signals, and said propagate signals.