Patent ID: 8749289
Filing Date: 2014-06-10
Classification: G06F,H03B,H03K

Abstract:
1. A clock generation apparatus, comprising: a plurality of stages arranged in a ring with an output terminal of each stage coupled to an input terminal of a next stage at an output node, each stage configured to receive complementary input clock signals at respective first and second clock terminals and to receive a prior output signal from a prior stage at the input terminal and produce an output signal at the output terminal that is an inverted and delayed version of the prior output signal, wherein individual stages are gated to pass an inverted version of the prior output signal from the prior stage as the output signal at the output terminal responsive to the complementary input clock signals; and a plurality of latch structures, each latch structure being configured to cause an output signal at a respective output node to be the inverse of another output signal at a respective other output node; wherein the output signals at each output node have different phases.