Patent ID: 8102288
Filing Date: 2012-01-24
Classification: H03M

Abstract:
1. A circuit that converts parallel data into serial data to output the serial data, the circuit comprising: a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the first data rate of the reference input clock; a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data when the second parallel data is selected; a serial data generation unit that performs a process of generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock when the second parallel data is selected, and a process of generating second serial data by performing a serial conversion on the expanded data based on the reference input clock when the first parallel data is selected; and a data output port that outputs the first serial data or the second serial data.