Patent ID: 6295229
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A method of operating a memory array, wherein the method includes selectively programming the memory array that includes a first memory cell to be programmed and a second memory cell that is not to be programmed, the selectively programming comprising:providing a memory array including the first and second memory cells, wherein:each of the first and second memory cells includes:a source region, a drain/source region, and a drain region;a floating gate overlying portions of the source region and the drain/source region;a control gate overlying the floating gate and portions of the source region and the drain/source region; anda select gate overlying portions of the drain/source region and the drain region; andthe drain regions of the first and second memory cells are electrically connected to each other;placing the drain regions of the first and second memory cells at a first potential having a first polarity;placing the source regions of the first and second memory cells at a second potential of approximately zero volts;placing the control gate of the first memory cell at a third potential having a second polarity that is opposite the first polarity;placing the select gate of the first memory cell at a fourth potential having the first polarity, wherein the fourth potential is no higher than approximately eight volts;placing the control gate of the second memory cell at a fifth potential having an absolute value less than the first potential; andplacing the select gate of the second memory cell at a sixth potential having an absolute value less than the first potential.