Patent ID: 6566193
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of producing a memory cell of a semiconductor memory, which comprises the following steps:providing a substrate; forming a first trench in the substrate; depositing a capacitor dielectric in the trench; depositing a conductive trench fill in the trench; sinking the conductive trench fill into the trench; depositing a first insulating layer on the conductive trench fill in the trench; overgrowing the first insulating layer epitaxially with an epitaxial layer, proceeding from the substrate; forming a second trench in the epitaxial layer, the second trench extending through the first insulating layer to the conductive trench fill, and thereby removing a part of the substrate to the conductive trench fill, and forming a ridge from the epitaxial layer; etching the first insulating layer, thereby undercutting the epitaxial layer; depositing and sinking a contact layer, whereby the contact layer remains in an undercut region beneath the epitaxial layer; depositing and sinking a second insulating layer in the second trench; forming a gate oxide at the ridge; forming lateral margin ridges as a gate on the gate oxide; incorporating dopant into the ridge, thereby forming a doped region; forming a bit line on the doped region; forming a word line over the bit line; and forming a word line contact for electrically connecting the gate to the word line.