Patent ID: 6404022
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A field effect transistor device, comprising:a plurality of gate regions and a corresponding plurality of drain regions configured to form a plurality of gate-drain pairs including a first set of gate-drain pairs having relatively high threshold turn-on voltages and a second set of gate-drain pairs having threshold turn-on voltages lower than the threshold turn-on voltages of the first set; a gate bond pad; an electrical connection between the gate bond pad and each of the plurality of gate regions, the electrical connection configured such that a current path between the gate bond pad and gate regions in the first set is shorter than a current path between the gate bond pad and gate regions in the second set; a drain bond pad; an electrical connection between the drain bond pad and the plurality of drain regions, the electrical connection configured such that a current path between the drain bond pad and drain regions in the first set is shorter than a current path between the drain bond pad and drain regions in the second set; and a source operatively associated with the plurality of gate-drain pairs.