Patent ID: 8309459
Filing Date: 2012-11-13
Classification: H01L

Abstract:
1. A semiconductor process, comprising: providing a substrate in an etching apparatus, wherein a plurality of first conductive patterns, a barrier layer and a patterned insulating layer are formed on the substrate, a plurality of first openings is formed between the first conductive patterns, the barrier layer covers surfaces of the first conductive patterns and the first openings, the patterned insulating layer is formed on the first conductive patterns and has a plurality of second openings, the second openings expose the barrier layer disposed on top corners of the first conductive patterns, and each second opening is connected to a corresponding first opening; depositing a first polymer layer and a second polymer layer on the barrier layer, wherein the first polymer layer is disposed on the top corners of the first conductive patterns, the second polymer layer is disposed on bottom portions of the first openings, and a thickness of the first polymer layer is larger than a thickness of the second polymer layer; and performing an etching process to remove the second polymer layer and the barrier layer disposed on the bottom portions of the first openings.