Patent ID: 8564704
Filing Date: 2013-10-22
Classification: H04N

Abstract:
1. A solid-state imaging device comprising: photodiodes: charge-voltage converting circuits provided after the photodiodes; first pre-holding circuits provided after the charge-voltage converting circuits; a first transimpedance amplifier which is provided after the first pre-holding circuits and has a capacitor between input and output terminals thereof, the first transimpedance amplifier including: a first amplifier having: a non-inverting input terminal receiving a reference voltage value, an inverting input terminal receiving the voltage values held and output by the first pre-holding circuits, and an output terminal, a capacitor connected between the inverting input terminal and the output terminal of the first amplifier, and a resistor connected between the inverting input terminal and the output terminal of the first amplifier; and a peak holding circuit provided after the first transimpedance amplifier, wherein the peak holding circuit inputs voltage values output from the first transimpedance amplifier, hold a peak voltage value of the input voltage values, and outputs a voltage value corresponding to the held peak voltage value, and second pre-holding circuits provided in parallel to the first pre-holding circuits after the charge-voltage converting circuits; a second transimpedance amplifier which is provided after the second pre-holding circuits and has a capacitor between input and output terminals thereof, the second transimpedance amplifier including: a second amplifier having: a non-inverting input terminal receiving a reference voltage value, an inverting input terminal receiving the voltage values held and output by the second pre-holding circuits, and an output terminal, a capacitor connected between the inverting input terminal and the output terminal of the second amplifier, and a resistor connected between the inverting input terminal and the output terminal of the second amplifier; and a subtracting circuit which is interposed between the output terminal of the first transimpedance amplifier and the output terminal of the second transimpedance amplifier, and the peak holding circuit.