Patent ID: 7135905
Filing Date: 2006-11-14
Classification: H03K,H03L,H04L

Abstract:
1. A clock and data recovery system comprising: a start of packet detector for detecting the start of a preamble of an incoming data stream; a gain control logic module coupled to the start of packet detector, wherein the gain control logic module is configured to determine a gain value; a phase interpolator for generating a recovered clock signal; a sampling module coupled to the phase interpolator, the sampling module including logic for sampling a data stream using the recovered clock signal; a phase detector coupled to the sampling module, wherein the phase detector generates a phase adjustment signal; a gain adjust module coupled to the phase detector, the gain control logic module, and a phase accumulator, wherein the gain adjust module applies the gain value received from the gain control logic module to the phase adjustment signal; and the phase accumulator coupled to the gain adjust module and the phase interpolator.