Patent ID: 6025646
Filing Date: 2000-02-15
Classification: H01L

Abstract:
An insulating gate type semiconductor device comprising:(a) a semiconductor region defining a cell region and a field region, said cell region including a drain region, a base region formed at a surface of said drain region, and a source region formed at a surface of said base region, a first recess being formed throughout said source region and reaching an intermediate depth of said base region;(b) a gate insulating film partially covering an exposed surface of said source region therewith, entirely covering an exposed surface of said base region, and partially covering an exposed surface of said drain region therewith;(c) a gate electrode formed on said gate insulating film;(d) a field insulating film formed on said semiconductor region in said field region;(e) a first gate wiring layer formed on said field insulating film in electrical connection with said gate electrode, said first gate wiring layer being formed with a second recess;(f) a source electrode in electrical isolation from said gate electrode, but in electrical connection with both an inner surface of said first recess and a part of a surface of said base region; and(g) a second gate wiring layer in electrical connection with both an inner surface of said second recess and a part of a surface of said first gate wiring layer.