Patent ID: 6762987
Filing Date: 2004-07-13
Classification: G11B

Abstract:
A circuit arrangement including means for determining a slicer level from incoming slicer levels and a slicer for slicing the incoming, signal levels on the basis of the slicer level thus determined, characterized in that the means for determining a slicer level include a first and a second register circuit, which registered circuits are connected to an output of a discriminator circuit, which discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and it to apply an incoming signal level to the second register circuit if the incoming signal level is lower than set discrimination level, which first and second register circuit are each adapted to determine a register mean value of the least two different incoming signal levels consecutively applied to the register circuit, and there is a mean-value circuit for supplying a signal having a level which is a mean value of the register mean values determined by the first and seconds register circuit, which supplied signal represents both the set discrimination level and the slicer level, wherein the mean-value circuit has a feed-back that forms an input to the discriminator circuit.