Patent ID: 7026690
Filing Date: 2006-04-11
Classification: H01L,Y10S

Abstract:
1. A memory device comprising: a crystalline layer separated from a substrate by an insulative material; the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium; a field effect transistor having a transistor gate and a pair of source/drain regions; a bipolar transistor having a collector region, emitter region and base region; the collector region and emitter region both being elevationally above the transistor gate; the base region electrically connecting with one of the source/drain regions of the field effect transistor; and wherein the field effect transistor is over the crystalline layer and has an active region extending into the crystalline layer; at least a portion of the source/drain regions is comprised by the active region within the crystalline layer; the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium.