Patent ID: 6040222
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A method for fabricating an electrostatic discharge (ESD) protection device, which is simultaneously formed while an internal circuit is formed, wherein an isolation structure is formed on a semiconductor substrate to define a device region and a protection circuit region, a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor are respectively formed on the device region and the protective circuit region, in which the first MOS transistor comprises a first gate structure and a first interchangeable source/drain region with a first lightly doped drain (LDD) structure, and the second MOS transistor comprises a second gate and a second interchangeable source/drain with a second lightly doped drain (LDD) structure, of which the second interchangeable source/drain region is doped with a first-type dopant, the method comprising:performing a self-aligned silicide (Salicide) process over the substrate;removing a spacer of the second MOS transistor at the protection circuit region so as to expose a portion of the second interchangeable source/drain region in the substrate, wherein the spacer is on each sidewall of the second gate of the second MOS transistor; andimplanting a second-type dopant into the exposed portion of the second interchangeable source/drain region to form a second-type dopant region so as to form a diode structure.