Patent ID: 8719741
Filing Date: 2014-05-06
Classification: G06F,Y02D

Abstract:
1. A method for inserting a guarding logic into a circuit, comprising: inputting, by a computer, a gate net list generated using a gated clock method, wherein the gated clock method controls a clock in all flip flops in the circuit; exploring, by the computer, a circuit in a tree structure upstream starting from a data input terminal of one of the flip flops as a starting point, for every flip flop within the gate net list; finding, by the computer, a portion in which a downstream combination circuit does not stop switching only according to a gated clock design, by checking a relation between a driver gate and a load gate from a view of each gate found in the tree structure to find a boundary between a first combination circuit and a second combination circuit, wherein an output terminal of the first combination circuit is connected only to a clock domain that controls the one of the flip flops as the starting point, and an output terminal of the second combination circuit is connected to clock domains including a clock domain that controls the one of the flip flops as the starting point; and in a front stage of the first combination circuit that corresponds to the boundary, inserting, by the computer, a guarding logic in which an Enable control line of the gated clock of the one of the flip flops as the starting point is input to the guarding logic.