Patent ID: 6383920
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A process for enclosing a via in a semiconductor device, the process comprising the steps of:forming a dielectric layer over a first metal layer, wherein the dielectric layer has a thickness; forming a via in the dielectric layer, wherein the via has a depth at least equal to the thickness of the dielectric layer, thereby defining a sidewall of the dielectric layer and exposing a portion of the first metal layer; conformally depositing a first metal liner in the via, wherein the first metal liner includes a bottom portion deposited over said exposed portion of the first metal layer and a sidewall portion deposited over said sidewall of the dielectric layer; forming at least one trench in the dielectric layer adjacent to the first metal liner, wherein the trench has a depth less than the thickness of the dielectric layer, thereby defining a trench bottom and a trench sidewall and exposing an upper portion of said sidewall portion of the first metal liner; conformally depositing a second metal liner in the trench, wherein at least a portion of the second metal liner is deposited over the trench bottom and the trench sidewall; and depositing a second metal layer over the first metal liner and the second metal liner, wherein the second metal layer substantially fills the via and the trench.