Patent ID: 7916531
Filing Date: 2011-03-29
Classification: G11C

Abstract:
1. A memory element, comprising: a first MOSFET and a second MOSFET each including a dielectric material having a dielectric constant of about 3.9 to about 25, a first one of (a) a source, and (b) a drain of said first MOSFET and of said second MOSFET being coupled to a common reference voltage, and the second one of (a) said source and (b) said drain of said first MOSFET being coupled to a gate of said second MOSFET; and control logic coupled to said MOSFETs, said control logic selectively coupling the second one of (a) said source and (b) said drain of said second MOSFET to a gate of said first MOSFET; wherein the control logic is adapted to: