Patent ID: 6828612
Filing Date: 2004-12-07
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device comprising:a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit-line pair; a sense amplifier connected to said bit-line pair and amplifying a potential of said bit-line pair: a data-line pair for transmitting the potential of said bit-line pair; and a switch circuit between said bit-line pair and said data-line pair, wherein one of said bit-line pair is connected to said first dynamic memory cell and the other of said bit-line pair is connected to said second dynamic memory cell, and wherein said switch circuit includes a pair of transistors each having a gate connected to said bit-line pair and a source-drain path connected to said data-line pair.