Patent ID: 6374384
Filing Date: 2002-04-16
Classification: H03M

Abstract:
A Reed-Solomon error-correcting circuit that receives a transmitted packet encoded with a Reed-Solomon code, decodes a received packet with a Reed-Solomon code, and outputs the decoded packet, said Reed-Solomon error-correcting circuit comprising:a memory operable to input and delay the received packet to output a delayed packet; a syndrome generating circuit operable to input the received packet to output a syndrome; and an error-correcting circuit operable to input the delayed packet and the syndrome to output the decoded packet; said error-correcting circuit comprising: an error-locator-polynomial/error-evaluator-polynomial calculating circuit operable to input the syndrome and output an error-locator-polynomial and an error-evaluator-polynomial; and a correcting circuit operable to input the delayed packet, the error-locator-polynomial, and the error-evaluator-polynomial, obtain errors contained in the delayed packet from the error-locator polynomial and the error-evaluator-polynomial, remove errors from the delayed packet, and output the decoded packet; said error-locator-polynomial/error-evaluator-polynomial calculating circuit having a plurality of shift registers and a Galois-field operations circuit to which a final stage output of each shift register is input; said syndrome generating circuit and said error-correcting circuit operable to perform parallel operation by pipelined processing for each packet; and said error-correcting circuit operable to operate in synchronization with a clock with a period of 1/N the period of the received symbol clock, where N&gE;1, and N is an integer.