Patent ID: 9223728
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. An apparatus for servicing a globally broadcast interrupt signal in a multi-threaded computer, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of: indicating, by an interrupt controller, in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller, each local interrupt status location corresponding to a particular thread; determining, by a thread, that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller; and in response to determining that the local interrupt status location indicates that the globally broadcast interrupt signal has been received by the interrupt controller, processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked, each entry in the global interrupt status bit queue corresponding to a queued global interrupt, wherein processing one or more entries in the global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked includes: