Patent ID: 6816397
Filing Date: 2004-11-09
Classification: G11C

Abstract:
An integrated circuit memory, comprising:a plurality of primary sense amplifiers coupled to provide read and write access to a multiplicity of storage cells; a plurality of second sense amplifiers; a plurality of pairs of input/output data lines (IODLs), each said input output data line (IODL) pair coupled to a primary sense amplifier of said plurality of primary sense amplifiers, and each said IODL pair adapted to carry first complementary signals representing a storage bit; a plurality of pairs of bi-directional primary data lines (BPDLs), each said bi-directional primary data line (BPDL) pair coupled to a second sense amplifier of said plurality of second sense amplifiers, and each said BPDL pair adapted to carry second complementary signals representing a storage bit; and a plurality of local buffers each adapted to transfer by converting, in accordance with read control input, said first complementary signals carried by said IODLs to said second complementary signals carried by said BPDLs, and to transfer by converting, in accordance with write control input, said send complementary signals carried by said BPDLs to said first complementary signals carried by said IODLs.