Patent ID: 6438068
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A non-volatile memory device comprising:an array of non-volatile memory cells arranged in banks of rows and columns; address connections to receive address signals; a chip select (CS#) connection to receive a chip select signal; a row address strobe (RAS#) connection to receive a row address strobe; a column address strobe (CAS#) connection to receive a column address strobe; a write enable (WE#) connection to receive a write enable signal; and control circuitry to perform a burst read operation of memory cells in a first block of the array, the control circuitry interrupts the burst read operation in response to a burst terminate command or an active terminate command, the burst terminate command is defined as the chip select is active, the row address strobe is inactive, the column address strobe is inactive, and the write enable signal is active, the active terminate is defined as the chip select is active, the row address strobe is active, the column address strobe is inactive, the write enable signal is active, and the address signals identify the first block.