Patent ID: 8601193
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A method comprising: selecting an event within a processor core; configuring a multiplexer in front of each of a number of counters to route the event to the counter; assigning a number of counters for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters comprises a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field; configuring the number of counters to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts; setting a bit in a trigger status register corresponding to a particular interrupt thread identification and to a particular processor identification of a particular counter in response to the performance counter identifying a trigger condition; and freezing all counters having the same particular interrupt thread identification field and the same particular processor identification field as the bit in the trigger status register, while leaving other counters unaffected in response to being enabled to freeze all counters.