Patent ID: 6915388
Filing Date: 2005-07-05
Classification: G06F

Abstract:
1. A multiprocessor computer system comprising: a plurality of processor nodes; a memory, wherein the memory includes a plurality of lines and a cache coherence directory structure, wherein the plurality of lines includes a first line and wherein the cache coherence directory structure includes a plurality of directory structure entries; and an interconnect network connecting the plurality of processor nodes to the memory; wherein each directory structure entry includes processor pointer information indicating the processor nodes that have cached copies of the first line, wherein the processor pointer information includes a plurality n of bit vectors, where n is an integer greater than one; wherein the n bit vectors define a matrix having a number of locations equal to the product of the number of bits in each of the n bit vectors, wherein the number of locations is at least equal to the number of processor nodes and wherein each of the processor nodes is mapped to a corresponding one of the locations wherein the locations corresponding to the processor nodes are dispersed in the matrix in an at least partially noncontiguous manner.