Patent ID: 9117526
Filing Date: 2015-08-25
Classification: G11C,H01L

Abstract:
1. A memory comprising: a doped substrate well; a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well; a series arrangement including a plurality of memory cells, the series arrangement coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad, wherein the source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors; a supply line connected to the set of interlayer connectors; a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and circuitry coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.