Patent ID: 8819354
Filing Date: 2014-08-26
Classification: G06F

Abstract:
1. An apparatus comprising: a first circuit configured to read data from and write data to an external memory device connected to a plurality of input/output (I/O) pins of said apparatus, said first circuit comprising a plurality of data path circuits, each data path circuit configured to (i) present a data strobe output signal to the external memory device via a respective one of said plurality of input/output (I/O) pins, (ii) receive a data strobe input signal from said external memory device via said respective one of said I/O pins, and (iii) gate a read data path in response to a respective gating control signal; and a second circuit comprising a plurality of feedback circuits, each feedback circuit corresponding to a respective one of said plurality of data path circuits and configured to (i) present a feedback control signal to a respective external load circuit connected to a respective load output pin of said apparatus, (ii) receive a feedback of said feedback control signal from said respective external load circuit through a respective load input pin of said apparatus, and (iii) generate the respective gating control signal for the respective data path circuit in response to the feedback received via the respective load input pin, wherein said respective external load circuit is configured to match a load of said external memory device connected to said plurality of input/output pins and said feedback circuits compensate for signal flight time variations between said apparatus and said external memory device.