Patent ID: 6327318
Filing Date: 2001-12-04
Classification: H03L

Abstract:
A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising a plurality of fine delay elements and a coarse delay line comprising a plurality of coarse delay elements, said main delay line being controlled by a controller, said delay compensation circuit comprising:(a) a coarse delay element,(b) an adjustable fine delay adapted for modeling said coarse delay element,(c) a counter for controlling the delay of the adjustable fine delay to a value which is substantially the same as the delay of said modelled coarse delay element to obtain a fine delay count,(d) a circuit for applying a representation of the system clock to the delay compensation circuit, and(e) a circuit for applying said fine delay count from the counter to the controller of said main delay line for adjusting the delay of the fine delay line of the main delay line to a value which is the same as that of said modelled coarse delay element,in which the delay compensation circuit is comprised of a pair of delay paths each for receiving the representation of the system clock in parallel,an output of each of the delay paths being coupled to an input of a phase detector,a first delay path of said pair of delay paths including said fine delay elements, a second delay path of said pair of delay paths including said modelled coarse delay element, the number of fine delay elements required to provide a delay which is equal to that of said second delay path being determined by said delay compensation circuit, said modelled coarse delay element being similar to each coarse delay element of the main delay line, the counter controlling the delay of the first delay path, and the output of the phase detector being coupled to said counter, in which said second delay path includes a series circuit of a coarse delay element and a fine delay element.