Patent ID: 6704919
Filing Date: 2004-03-09
Classification: G06F,H05K

Abstract:
A printed circuit board wiring structure verification system comprising:a unit for identifying a high speed IC incorporated in said board on the basis of a rise time of a signal of said high speed IC; an optimum capacitance value computing unit for computing an optimum capacitance value for a bulk capacitor; a comparison unit for comparing at least a capacitance value tentatively given to said bulk capacitance with said optimum capacitance value; means for determining if there is a difference larger than a predetermined value between a tentative design value and an optimum value; an optimum position computing unit for computing an optimum position for said bulk capacitor; and a means for determining if a proposed position of the bulk capacitor is separated by a distance larger than a predetermined value from the optimum position; and a means for identifying if the interconnect distance between said bulk capacitor and said high speed IC of the tentative design exceeds the predetermined value.