Patent ID: 6034400
Filing Date: 2000-03-07
Classification: H01L

Abstract:
An MOS integrated circuit device formed on a semiconductor chip and having an improved electrostatic discharge protection capability, comprising:high and low voltage rails for bringing externally-supplied power to circuitry within the chip;input bonding pads for communicating input signals to the chip from external sources;clamping circuitry connected to input bonding pads for clamping the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads;a receiver circuit coupled to each input bonding pad, each receiver circuit having a receiver input node, a receiver output node and overvoltage-sensitive MOS circuitry between the input and output nodes; anda conductor connecting each input bonding pad to its receiver circuit, the conductor having a length greater than the distance between the input bonding pad and the receiver input node, said conductor having an inductance of about 0.3 nanohenry,wherein said conductor comprises a first layer of metal strips interconnected with a second layer of metal strips, the first and second layers being disposed at different levels to define a multi-level inductor on the semiconductor chip.