Patent ID: 8296703
Filing Date: 2012-10-23
Classification: G06F,G11C

Abstract:
1. A method of characterizing defects in state-retention logic, comprising: specifying a circuit that includes an arrangement of circuit elements, wherein specifying a defect that corresponds to an incorrect functioning of the state-retention cell in a state-retention operation of the circuit; using a computer for determining one or more pattern faults for detecting the defect in the state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control, wherein the one or more pattern faults include required circuit-element values for activating the defect in the state-retention operation of the circuit and propagation circuit-element values for detecting a presence or absence of the defect in the state-retention operation of the circuit; and saving one or more values for the one or more pattern faults.