Patent ID: 6828229
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of forming an interconnection line in a semiconductor device comprising:forming a first etching stopper on a lower conductive layer which is formed on a semiconductor substrate; forming a first interlayer insulating layer on the first etching stopper; forming a second etching stopper on the first interlayer insulating layer; forming a second interlayer insulating layer over the second etching stopper; etching the second interlayer insulating layer, the second etching stopper and the first interlayer insulating layer sequentially using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer; forming a protective layer to protect a portion of the first etching stopper exposed at the bottom of the via hole, the protective layer filling the via hole and extending across the via hole; etching the protective layer such that the protective layer remains only in the bottom of the via hole; after etching the protective layer such that the protective layer remains only in the bottom of the via hole, forming an etching mask on the second interlayer insulating layer; etching a portion of the second interlayer insulating layer adjacent to the via hole using the second etching stopper as an etching stopping point and the etching mask to form a trench connected to the via hole; removing the protective layer; removing the portion of the first etching stopper positioned at the bottom of the via hole; and forming an upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer.