Patent ID: 6362091
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method of forming a semiconductor device that has a dual damascene interconnect comprising:forming on a substrate a first insulating layer, which includes a carbon doped oxide; forming a second insulating layer on the surface of the first insulating layer, wherein the second insulating layer is under compressive stress and provides superior mechanical strength, when compared to the mechanical strength of the first insulating layer; forming a third insulating layer, which includes a carbon doped oxide, on the surface of the second insulating layer; forming a fourth insulating layer on the surface of the third insulating layer, wherein the fourth insulating layer is under compressive stress and provides superior mechanical strength, when compared to the mechanical strength of the third insulating layer; etching a via through the first, second, third and fourth insulating layers; forming a trench on top of the via and on top of the fourth insulating layer; and then filling the via and trench with a conductive material.