Patent ID: 8912041
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A method for forming an interconnect structure, comprising: providing a plurality of conductive features in a semiconductor substrate; forming a dielectric material layer over the conductive features; forming an oxygen-rich oxide layer over the dielectric material layer; patterning the dielectric material layer and the oxygen-rich oxide layer to form a plurality of vias in the semiconductor substrate, wherein each of the plurality of vias is substantially aligned with a respective one of the plurality of conductive features; forming a barrier layer in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich oxide layer exposed; forming a copper alloy layer on the barrier layer and on the exposed portion of the oxygen-rich oxide layer, wherein the copper alloy layer fills the plurality of vias; and annealing the semiconductor substrate to segregate metal oxide to the surface of the copper alloy layer to form a metal-oxide etch stop layer.