Patent ID: 6107859
Filing Date: 2000-08-22
Classification: H03F

Abstract:
A buffer circuit, comprising:a pair of input nodes and an output node, wherein voltages applied to the input nodes and a voltage produced upon the output node all differ in the same direction from a voltage upon an intermediate node;a first conductive path connected from one input node of the pair of input nodes to the output node, wherein the intermediate node is within the first conductive path between the one input node and the output node;a second conductive path connected from another input node of the pair of input nodes to the output node, wherein the intermediate node is also within the second conductive path between the another input node of the pair of input nodes and the output node;a pair of input transistors having gate conductors coupled to the respective pair of input nodes, such that one respective input transistor of the pair of input transistors is within each of the first and second conductive paths;a first resistor coupled within the first or second conductive path between the intermediate node and one transistor of the pair of input transistors; anda diode coupled within the first and second conductive paths between the intermediate node and the output node.