Patent ID: 9222965
Filing Date: 2015-12-29
Classification: G01R,H01L

Abstract:
1. A method for testing a microelectronic substrate, comprising; positioning a first translator in a first region proximate to a microelectronic substrate, the microelectronic substrate having a first major surface and a second major surface facing away from the first major surface, the microelectronic substrate having electrically conductive through-substrate vias extending through the substrate, a first region extending outwardly from the first major surface of the microelectronic substrate and a second region extending outwardly from the second major surface; releasably fixing the first translator relative to the microelectronic substrate at the first region; releasably fixing a second translator relative to the microelectronic substrate at the second region while the first translator is fixed relative to the microelectronic substrate at the first region; electrically accessing a through-substrate via of the microelectronic substrate with the first translator while the first translator is positioned in the first region; and electrically accessing the through-substrate via of the microelectronic substrate with the second translator while both the first and second translators are releasably fixed relative to the microelectronic substrate, wherein the via is a first via, and the first via is part of a first die, and wherein the method further comprises simulating stacked dies by: