Patent ID: 8300752
Filing Date: 2012-10-30
Classification: H04L

Abstract:
1. A structure for performing cross-chip communication with mesochronous clocks, comprising: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; a control that influences a delay associated with the data delay line and the remote clock delay line; a delay register that holds a current value upon which the delay is based; a first delay structure in the data delay line that applies the delay to a data signal; and a second delay structure in the remote clock delay line that applies the delay to a remote clock signal, wherein the data signal and the remote clock signal are aligned and generated together at a remote location of a chip, wherein the control comprises a state machine; the state machine receives the current value of the delay register and the at least one value of the state of the delayed remote clock signal and generates a new value for the delay register; the delay register provides the current value as input to each of the first delay structure, the second delay structure, and the control; and the control dynamically adjusts the current value to align the delayed remote clock signal with a local clock signal of a local clock in a local domain, such that the delayed data signal is valid for use by the local domain.