Patent ID: 7908310
Filing Date: 2011-03-15
Classification: G06G

Abstract:
1. A multiplier-divider having error offset function including a multiplier input terminal, a first divisor input terminal, a second divisor input terminal and a third divisor input terminal to receive respectively a first multiplier signal, a first divisor signal, a second divisor signal and a third divisor signal, and an output terminal to output process results, the multiplier-divider comprising: a first differential converter to receive and divide the first divisor signal and output a plurality sets of divisor conversion signals; a second differential converter to receive the first multiplier signal and output at least one multiplier conversion signal; a pulse generator to receive one of the divisor conversion signals to generate a first pulse signal and a second pulse signal that are output respectively through a first pulse output end and a second pulse output end; a first division unit to receive another one of the divisor conversion signals, the first pulse signal and the second divisor signal and perform processing to generate a first quotient signal; a second division unit to receive yet another one of the divisor conversion signals, the second pulse signal and the third divisor signal and perform processing to generate a second quotient signal; a first multiplication unit to receive the multiplier conversion signal, the first pulse signal and the first quotient signal and perform processing to generate a first product signal; a third differential converter to receive the first product signal and output at least one product conversion signal; and a second multiplication unit to receive the product conversion signal, the second pulse signal and the second quotient signal and perform processing to generate an output signal; wherein the divisor conversion signals generated by the first differential converter during the processing form a division error after two times of division processing, the multiplier conversion signal generated by the second differential converter and the product conversion signal generated by the third differential converter go through respectively one multiplication processing to form a multiplication error, a product error generated by the second multiplication unit resulting from the second differential converter and the third differential converter offsets the division error generated by the first differential converter such that the errors are offset in the output signal.