Patent ID: 6744139
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate; a gate structure selectively formed on said semiconductor substrate and having a layered structure in which a gate electrode and an insulation film are stacked one above the other in order from said semiconductor substrate side; an active region formed in a main surface of said semiconductor substrate; a stopper film covering a whole surface of said gate structure and formed on said active region; a first interlayer insulation film formed on said stopper film; a first contact hole extending from an upper surface of said first interlayer insulation film to said active region; a metal material buried in said first contact hole; a metal wiring layer formed on said first interlayer insulation film to be connected to said metal material; a second interlayer insulation film formed on said first interlayer insulation film to cover said metal wiring layer; a second contact hole extending from an upper surface of said second interlayer insulation film through said first interlayer insulation film, said stopper film and said insulation film to said gate electrode of said gate structure; and a third contact hole extending from the upper surface of said second interlayer insulation film to said metal wiring layer, said third contact hole being shallower than said second contact hole, wherein an etch rate of a film in forming said second and third contact holes is larger than that of said metal wiring layer.