Patent ID: 7390729
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a transistor having a gate structure and a source/drain region on a substrate, wherein the gate structure comprises a gate conductor layer, a gate dielectric layer and a spacer, the gate dielectric layer is disposed between the gate conductor layer and the substrate, and the spacer is disposed on the side wall of the gate conductor layer; forming a metal layer on the substrate; performing a first annealing step, such that the metal layer reacts with the surface of the gate conductor layer and the surface of the source/drain region to form a metal silicide layer on the surface of the gate conductor layer and the surface of the source/drain region; selectively removing the metal layer that is not reacted; performing a second annealing step; performing a surface treatment step between the step of selectively removing the metal layer that is not reacted and the second annealing step to selectively form a protection layer on the metal silicide layer, wherein the material of the protection layer is different from that of the spacer; using the protection layer as a mask, partially removing the spacer so as to reduce a width of the spacer, such that a space exists between the spacer and the metal silicide layer; and forming a stress layer on the substrate, so as to cover the spacer, the protection layer and the space.