Patent ID: 7279738
Filing Date: 2007-10-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: an oxide layer adjacent a substrate; a polysilicon layer disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate; a planarized PSG (phosphorus silicate glass) layer disposed outwardly from the polysilicon layer; a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer; a dielectric layer in the capacitor channel disposed outwardly from the polysilicon layer; a tungsten plug operable to substantially fill the capacitor channel; a first TEOS (tetraethylorthosilicate) layer disposed outwardly from the polysilicon layer and disposed inwardly from the planarized PSG layer; and a second TEOS layer disposed outwardly from the planarized PSG layer and disposed inwardly from the dielectric layer.