Patent ID: 6158018
Filing Date: 2000-12-05
Classification: G06F

Abstract:
An Integrated Circuit (IC) device comprising, in combination:an IC including an embedded Digital Signal Processor (DSP), an embedded Random Access Memory (RAM), and an embedded Read Only Memory (ROM) having at least one portion thereof which is flawed;patching circuitry embedded in said IC, the patching circuitry including a plurality of patch modules, each patch module arranged to receive as input signals a current DSP program address and respective break addresses and arranged to generate an output signal at an output terminal when the current program address matches the respective break address, wherein each break address corresponds to a separate flawed portion of said embedded ROM, the patching circuitry further including a patch priority circuit coupled to output terminals of the patch modules, the priority circuit configured and arranged to selectively enable the patch modules one after another in a priority order.