Patent ID: 6518631
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A transistor device formed on a semiconductor substrate having active regions defined by isolation trenches, the device comprising:a gate defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate wherein the source and the drain include main source and drain regions and source and drain extension regions; a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed in the main source and drain regions and wherein the multi-thickness silicide layer which is formed on polysilicon regions of the main source and drain regions is thicker than the portion of the silicide layer which is formed on main junction regions of main source and drain regions; and a plurality of spacers used in the formation of the device.