Patent ID: 6018794
Filing Date: 2000-01-25
Classification: G11C

Abstract:
A data processing circuit, comprising:a plurality of components arranged to be responsive to a command signal to generate substantially simultaneously a plurality of first output signals, each output signal representing variable data bits;a timed circuit arranged to receive the plurality of first output signals and to generate second output signals for use in subsequent data processing operations, the information content of the second output signals being dependent on the variable data bits represented by the plurality of first output signals;a subset of the components being arranged to generate respective ones of said plurality of first output signals representing variable data bits that are coded so as to cause at least one of the second output signals generated by the timed circuit to transition from its state prior to the generation of the plurality of first output signals; andcontrol circuitry, responsive to the state transition of said at least one of the second output signals to generate a timing signal used to control the operation of said timed circuit.