Patent ID: 8592817
Filing Date: 2013-11-26
Classification: H01L

Abstract:
1. A metal oxide TFT with reduced interelectrode capacitance comprising: a transparent substrate having a front surface and a rear surface; an opaque gate metal positioned on the front surface of the substrate and defining a gate area for a TFT; a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area; a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric; a layer of etch stop material positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal, the layer of the etch stop material defining a channel area in the layer of metal oxide semiconductor material; and conductive material patterned on the portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material to form source and drain areas on opposed sides of the channel area.