Patent ID: 6128297
Filing Date: 2000-10-03
Classification: H04L

Abstract:
A packet switching system comprising a switching device, wherein said switching device comprises:a main memory for buffering packets arriving by auxiliary lines;a main memory controller for generating addresses to store the packets in the main memory and for controlling write and read operations of the packets; anda demultiplexer controlled by said main memory controller, for transporting the packets by trunk lines,characterized in that said main memory controller comprisesan address memory for producing an address for a write operation,a respective buffer assigned to each said trunk line, for buffering the addresses produced by the address memory, anda decoding device,wherein the decoding device includes means for selecting a buffer for storing an address in dependence on a destination of a packet, means for selecting a buffer for producing an address intended to be read from said main memory, and means for accordingly controlling said demultiplexer.