Patent ID: 6405185
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A processor array comprising:a plurality of processing elements (PEs) arranged in a multidimensional array, the PEs each comprising a plurality of input/output (I/O) ports, each of the I/O ports for transmitting and receiving data; the PEs each coupled to four adjacent ones of the plurality of PES each at one of said plurality of I/O ports, and wherein each PE along an edge of the array is wraparound coupled to another PE of the plurality of PEs along a nonadjacent edge of the array, said four adjacent ones of the PEs are designated as north, south, east and west PEs; wherein the PEs are coupled in a folded mesh such that pairs of the PEs share said plurality of input/output ports, a PE designated PEij shares the input/output ports with a PE designated PEji, where column and row subscripts i and j, respectively, are nonequal positive integers, PEs with iPEs with i>j are designated bottom PEs, PEs with i=j are designated diagonal PEs, and wherein the diagonal PEs are each coupled to two adjacent ones of the PEs each at one of said plurality of I/O ports, and each diagonal PE at a corner of the array is wraparound coupled to a nondiagonal PE at another corner of the array.