Patent ID: 6643183
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first and a second node which have a potential difference equal to or higher than a supply voltage between them and are connected to each other via a parasitic capacitance; a first switch circuit which is connected between said first and second nodes, wherein the first switch circuit short-circuits said first and second nodes, and wherein said first switch circuit includes: (a) an n-channel first transistor one end of whose current path is connected to said first node, (b) an n-channel second transistor one end of whose current path is connected to said second node, and (c) a p-channel third transistor both ends of whose current path are connected to the respective other ends of the current paths of said first and second transistors; a second switch circuit which is connected between said first node and ground, wherein the second switch circuit is turned on after said first switch circuit has been turned on; a third switch circuit which is connected between said second node and ground, wherein the third switch circuit is turned on after said first switch circuit has been turned on; and a control circuit configured to control said first switch circuit, said control circuit turning on said first switch circuit after an erase operation.