Patent ID: 9099027
Filing Date: 2015-08-04
Classification: G09G

Abstract:
1. A display panel driving device for use with a display panel having a plurality of signal lines and a plurality of scan lines, with a plurality of pixel units being formed at crossing portions of the signal lines and scan lines, said display panel driving device comprising: a signal line driver that applies, on the basis of an input image signal, a pixel driving voltage to each of said signal lines, wherein said signal lines are grouped into a plurality of signal line groups, said signal line driver includes a plurality of driver chips, which are associated with the plurality of signal line groups respectively, and the driver chips are connected in cascade through a clock line; each said driver chip includes a pixel driving voltage generation unit and a clock transmission unit, the pixel driving voltage generation unit applies the pixel driving voltage to each of those signal lines which belong to the associated signal line group at a timing corresponding to a clock signal supplied via said clock line, and the clock transmission unit transmits the clock signal supplied via said clock line to a subsequent one of said driver chips via said clock line; and said clock transmission unit includes a ½ frequency division circuit, a delay circuit and an Exclusive NOR gate such that the ½ frequency division circuit generates a frequency-divided clock signal by half-dividing a cycle of said clock signal supplied, the delay circuit generates a delayed frequency-divided clock signal by delaying the frequency-divided clock signal by a predetermined delay time, and the Exclusive NOR gate generates a shaped clock signal having a first level and a second level, the shaped clock signal has the first level in a period when a logic level of said delayed frequency-divided clock signal is equal to a logic level of said frequency-divided clock signal, the shaped clock signal has the second level in a period when the logic levels are different, and the Exclusive NOR gate transmits the shaped clock signal having the first and second levels to said subsequent driver chip via said clock line, said shaped clock signal being shaped to the same waveform as said clock signal introduced to the ½ frequency division circuit, wherein the delay circuit includes a plurality of inverters that are connected in series and each of the inverters includes a pair of first FETs have a first conductivity type channel, with a drain of one of the first FETs being connected to a source of the other first FET at a first connection point, gates of the first FETs being connected together at an input point, a first potential being applied to a source of said one of the first FETs, and a drain of said other first FET being connected to an output point, a pair of second FETs having a second conductivity type channel, with a drain of one of the second FETs being connected to a source of the other second FET at a second connection point, gates of the second FETs being connected together at said input point, a second potential being applied to a source of said one of the second FETs, and a drain of said other second FET being connected to said output point, a first additional FET that applies said second potential to said first connection point when said output point is at said second potential, a second additional FET that applies said first potential to said second connection point when said output point is at said first potential, a third additional FET that is always in an on condition and applies said second potential to said first additional FET, a fourth additional FET that is always in an on condition and applies said first potential to said second additional FET, a fifth additional FET whose drain is connected to a gate of said third additional FET, with said first potential being applied to a source of the fifth additional FET, a sixth additional FET whose gate and drain are both connected to a gate of said fifth additional FET, with said second potential being applied to a source of the sixth additional FET, a seventh additional FET whose drain is connected to a gate of said fourth additional FET, with said second potential being applied to a source of the seventh additional FET, and an eighth additional FET whose gate and drain are both connected to a gate of said seventh additional FET, with said first potential being applied to a source of the eighth additional FET.