Patent ID: 6378118
Filing Date: 2002-04-23
Classification: G11C,H01L

Abstract:
A large scale semiconductor integrated circuit, implemented on a chip, comprising:a microprocessor (MPU) disposed substantially in a central area of a chip; a dynamic random access memory (DRAM) cache memory including at least one DRAM macro block, having a plurality of memory cells arranged in a matrix, which is located near a corresponding side of said MPU, each of said at least one DRAM macro block having a peripheral circuit that includes a memory redundancy function implemented by a plurality of fuses, wherein said plurality of fuses occupies a plurality of areas of said chip; a plurality of bonding pads disposed near edges of said chip; a plurality of overlying interconnect lines including at least a pair of source lines connected between said MPU and said plurality of bonding pads, wherein said plurality of overlying interconnect lines circumvents said plurality of areas occupied by said plurality of fuses; and a plurality of underlying interconnect lines disposed beneath said plurality of overlying interconnect lines and extending in directions substantially parallel to rows and columns of said matrix of said plurality of memory cells, said plurality of underlying interconnect lines including at least a pair of source lines connected to said at least a pair of overlying source lines and to said at least one DRAM macro block.