Patent ID: 7349251
Filing Date: 2008-03-25
Classification: G11C,H01L

Abstract:
1. An integrated memory circuit arrangement comprising: a plurality of memory cells arranged in a matrix where the memory cells are arranged in rows and columns, each memory cell including at least one transistor; word lines coupled to control electrodes of the transistors of memory cells of a row of the matrix; bit lines coupled to electrodes of the transistors of memory cells of a column of the matrix; a single switching element per column, the single switching element configured to connect two local bit lines of a common column without the need of any additional switching elements; a collective line in the row direction of the matrix where at least one further switching element per column enables the production and disconnection of an electrically conductive connection of the collective line to a respective bit line, the collective line having the same potential in all of the operating modes; a first bit line of the two local bit lines being electrically conductively connected to the single switching element, the first bit line being formed from a doped region of a semiconductor substrate; and a second bit line of the two local bit lines being electrically conductively connected to the single switching element, the second bit line of the two local bit lines comprising a metallic line.