Patent ID: 7180132
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. An HV PMOS device, comprising: a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type opposite said first polarity type; at least one pair of field oxide regions disposed on a surface of the substrate and at least partially over the HV well; at least one pair of insulated gates on the substrate between each pair of field oxide regions, said gates having inner edges facing each other and outer edges facing corresponding one of the field oxide regions; stacked hetero-doping rims disposed in the HV well and in self-alignment with the outer edges of the gates; a buffer region of the first polarity type formed in the HV well between and in self-alignment with the inner edges of the gates; a drift region of the second polarity type formed in the buffer region between and in self-alignment with the inner edges of the gates; a drain region of the second polarity type formed within said drift and buffer regions; and source tap regions formed proximate said field oxide regions.