Patent ID: 7523426
Filing Date: 2009-04-21
Classification: G06F

Abstract:
1. A system comprising: a clock structure analysis tool configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit by (1) combining a plurality of circuit devices in said complex clock structure into a representative device in said simplified clock structure, (2) combining a plurality of logic blocks in said complex clock structure into a representative block in said simplified clock structure and (3) combining a plurality of signal interfaces between said circuit devices and said logic blocks into a representative interface in said simplified clock structure, wherein (A) each of said circuit devices (i) is of a single device type, (ii) receives said clock signal as an input and (iii) comprises one or more of said signal interfaces and (B) said representative device (i) is of said single device type, (ii) receives said clock signal as said input and (iii) comprises said representative interface; a static timing analysis tool configured to generate a plurality of results for a plurality of intermediate signals in said simplified clock structure in response to a static timing analysis of said design, wherein at least one of said intermediate signals is altered by said clock signal; and a waveform tool configured to generate a first representation in a graphical user interface format of said intermediate signals and said results, wherein said first representation is viewable by a user.