Patent ID: 7518850
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method for providing a composite capacitive circuit assembly, comprising: forming a metal-oxide-silicon capacitor at a bottom of a front end-of-line of a semiconductor chip by disposing a plurality of source, gate and drain regions within an overall horizontal length dimension of the metal-oxide-silicon capacitor; the plurality of metal-oxide-silicon capacitor gate regions each having a common horizontal length, the common horizontal lengths of the plurality of gate regions defining an effective horizontal width dimension of the metal-oxide-silicon capacitor; the effective horizontal width dimension and the overall horizontal length dimension defining an effective horizontal footprint area of the metal-oxide-silicon capacitor on the semiconductor chip; forming a vertical-native capacitor with a plurality horizontal metal layers in a back end-of-line of the semiconductor chip and vertically above the metal-oxide-silicon capacitor within the metal-oxide-silicon capacitor horizontal footprint area, each of the vertical-native capacitor horizontal metal layers comprising a plurality of parallel positive plates alternating with a plurality of parallel negative plates; forming a metal-insulator-metal capacitor in the back end-of-line of the semiconductor chip and vertically above the metal-oxide-silicon capacitor and the vertical-native capacitor and within the metal-oxide-silicon capacitor horizontal footprint area, the metal-insulator-metal capacitor having a top negative plate horizontally spaced over a parallel bottom positive plate; electrically connecting each of the vertical-native capacitor parallel positive plates, the metal-insulator-metal capacitor bottom positive plate, and the plurality of metal-oxide-silicon capacitor drains and sources with a first port; electrically connecting each of the vertical-native capacitor parallel negative plates, the metal-insulator-metal capacitor top negative plate and the plurality of metal-oxide-silicon capacitor gates with a second port; and the metal-insulator-metal capacitor, the vertical-native capacitor and the metal-oxide-silicon capacitor defining a composite capacitance density value between the first port and the second port, the composite capacitance density value about twice a capacitance density value of the metal-oxide-silicon capacitor.