Patent ID: 9111990
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a first surface and a second surface facing the first surface; a plurality of first semiconductor layers of a first conductive type provided in the semiconductor substrate of the second surface side, the first semiconductor layers extending in a first direction, the first semiconductor layers arranged in a second direction orthogonal to the first direction, each of the first semiconductor layers surrounded by a gate layer, a gate insulating film interposed between each of the first semiconductor layers and the gate layer; a plurality of second semiconductor layers of the first conductive type provided between the first semiconductor layers adjacent to each other in the second direction, the second semiconductor layers having a depth smaller than a depth of the first semiconductor layers in a direction toward the first surface from the second surface; a plurality of third semiconductor layers of the first conductive type provided in the semiconductor substrate of the second surface side, each of the third semiconductor layers arranged at ends of the first direction of each of the first semiconductor layers, each of the third semiconductor layers surrounded by the gate layer, the gate insulating film interposed between each of the third semiconductor layers and the gate layer, a depth of the third semiconductor layers being substantially equal to the depth of the first semiconductor layers in the direction toward the first surface from the second surface; a fourth semiconductor layer of a second conductive type provided in the semiconductor substrate at the second surface side of the second semiconductor layers; a sixth semiconductor layer of the first conductive type provided in the semiconductor substrate at the first surface side of the first semiconductor layers; a seventh semiconductor layer of the second conductive type provided between the first, second, and third semiconductor layers and the sixth semiconductor layer; an emitter electrode electrically connected to the third and fourth semiconductor layers; and a collector electrode electrically connected to the sixth semiconductor layer.