Patent ID: 6864156
Filing Date: 2005-03-08
Classification: H01L

Abstract:
1. A method, comprising: (a) attaching a supporting structure to a face side of a device wafer, a transistor being disposed on the face side of the device wafer, the transistor comprising a gate, a source region of a first conductivity type and a drain region of the first conductivity type, the source and drain regions extending into a well region of a second conductivity type opposite the first conductivity type, the device wafer also having a planar back side surface, a layer of the device wafer being disposed between the source and drain regions and the back side surface of the device wafer; (b) processing the back side surface and thereby removing the layer of the device wafer such that a portion of the well region is exposed; and (c) forming a well electrode that is electrically coupled to the well region so that the well electrode is disposed directly underneath the gate.