Patent ID: 6836019
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; an interlevel dielectric (LD) layer formed on the semiconductor substrate; a first contact stud formed in the ILD layer, the first contact stud having a first width of an entrance portion adjacent an upper surface of the ILD layer larger than a second width of a contacting portion adjacent the semiconductor substrate; a second contact stud formed in the ILD layer at a position proximal to the first contact stud and electrically isolated from the first contact stud; and a landing pad formed on the ILD layer to contact an upper surface of the second contact stud, having a width larger than that of the second contact stud, the landing pad being localized to a region directly above the upper surface of the second contact stud and being electrically isolated from horizontally adjacent conductive structures.