Patent ID: 7926002
Filing Date: 2011-04-12
Classification: G03F

Abstract:
1. A computer-implemented method of modifying integrated circuit layout design data, comprising: A. identifying a layout design, the layout design representing at least a portion of an integrated circuit design; B. implementing a resolution enhancement process having a first set of parameter values on the layout design, wherein an altered layout design is generated; C. checking for errors within the altered layout design, wherein one or more errors is detected; D. forming a re-correction region around at least one of the one or more detected errors, wherein the re-correction region designates a sub-portion of the altered layout design; E. identifying a second set of parameter values, wherein the second set of parameter values is different than the first set of parameter values; F. implementing an optical proximity correction process having the second set of parameter values on the sub-portion of the altered layout design designated by the re-correction region, wherein an altered sub-portion of the layout design is generated; G. stitching the altered sub-portion of the layout design into the altered layout design, wherein a modified layout design is generated; and H. saving the modified layout design to a memory storage location.