Patent ID: 6928129
Filing Date: 2005-08-09
Classification: H03C,H03L

Abstract:
1. A phase locked loop circuit comprising: a frequency divider for frequency-dividing an output signal to generate frequency-divided pulses; an oscillator for generating said output signal under control to an oscillation frequency by a control voltage obtained from a signal corresponding to a phase difference between said frequency-divided pulses and a reference frequency signal; and a controller for performing such a control that plural kinds of frequency dividing rate are switched to be given to said frequency divider having a predetermined number of said frequency divided pulses, and at a boundary of switching the plural kinds of frequency dividing rate, the plural kinds of frequency dividing rate are given co-existentially to said frequency divider, and further for switching the co-existent plural kinds of the frequency-dividing rate, the next frequency dividing rate is given before a first appearance of a frequency peak in a transitional characteristic of the frequency of the clock signal outputted from the phase locked loop circuit caused by previous setting the frequency-dividing rate, wherein said controller calculates the frequency dividing rate of said frequency divider on the basis of a first signal “I”, a second signal “H” and a third signal “V” to generate a frequency dividing rate control signal in accordance with a frequency dividing time period of said output signal and supply said frequency dividing rate control signal to said frequency divider, where said first signal “I” represents a counted value of said frequency-divided pulses, and said second signal “M” represents the number of outputs of said frequency divided pulses corresponding to said frequency dividing time period, and said third signal “V” represents the number of appearance of a combination of first and second frequency dividing rates, and where said first frequency dividing rate is allocated to a first half time period of a first time period corresponding to a rising time period or a falling time period of said frequency modulation waveform, and said second frequency dividing rate is allocated to a second half time period of said first time period, and said first and second frequency dividing rates alternately appear for every frequency dividing time periods at a boundary between said first half time period and said second half time period.