Patent ID: 7212587
Filing Date: 2007-05-01
Classification: H03F,H03M,H04L

Abstract:
1. Apparatus for reducing a DC offset in a signal path of a conversion system comprising: a front end circuit for providing an input signal; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the output signal from the amplifier system and providing a first bit quantizer signal; a digital DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer signal from the sigma delta modulator and arranged to reduce a DC offset in said signal path; a digital to analog converter coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to an input of the amplifier system, wherein the digital DC adapt circuit and the digital to analog converter form a feedback path originating from a first bit from the multi bit sigma delta modulator to an input of the amplifier system; and a serial peripheral interface coupled to the digital DC adapt circuit to provide an input signal to the digital to analogue converter for a known gain setting.