Patent ID: 7268831
Filing Date: 2007-09-11
Classification: H04N

Abstract:
1. A television receiver for receiving and processing television signals, apparatus comprising: a controller assembly comprising an inter-integrated circuit bus having a clock signal path and a data signal path, a processor, coupled to said clock and data paths, an IIC bus expander coupled to said processor via said clock and data paths, and a buffer coupled to an output of said IIC bus expander; a front-end assembly comprising a tuner having a down converter coupled to a phase-lock loop, said phase-lock loop coupled to an output of said buffer, at least one demodulator for demodulating said television signals, coupled to said down-converter, such that said phase-lock loop is operatively coupled to said processor via said inter-integrated circuit bus only when said processor is communicating with said phase-lock loop; and at least one video and audio processor for processing said modulated television signals to produce audio and video signals.