Patent ID: 6828842
Filing Date: 2004-12-07
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit device comprising:a first input terminal for receiving a high potential side power source; a second input terminal for receiving a low potential side power source; an internal circuit, including a first terminal for receiving a power source for internal circuit which is lower than voltage of said high potential side power source, to be operated by receiving said power source thereof; and a first clamp circuit and a second clamp circuit respectively for clamping unwanted level voltages, wherein said first and second clams circuits are connected in series between said first input terminal and said second input terminal and an intermediate node between said first clamp circuit and said second clamp circuit is connected to said first terminal, and wherein said internal circuit comprises: logic circuits formed of thin film transistors coupled with said power source for internal circuit; and capacitors for noise reduction provided between said power source for internal circuit and said low potential side power source.