Patent ID: 6166562
Filing Date: 2000-12-26
Classification: H02M,Y02B

Abstract:
A semiconductor integrated circuit device provided with a voltage converter circuit which comprises:a buffer circuit including:a P-channel MOS transistor having a source connected to a first supply voltage; andan N-channel MOS transistor having a source connected to a second supply voltage and a drain connected to a drain of said P-channel MOS transistor, an output voltage of the buffer circuit being outputted from a common-connected drain terminals of said two MOS transistors;a duty ratio control circuit including:a counter for outputting a first n-bit signal by repeatedly counting up numbers from 0 to (2.sup.n -1) one by one in synchronism with a first clock signal; anda comparator circuit for comparing the first n-bit signal with a second n-bit signal applied from the outside, and for outputting a first control signal to a gate of said P-channel MOS transistor and a second control signal to said N-channel MOS transistor; anda smoothing circuit for smoothing the output voltage of said buffer circuit, a voltage smoothed by said smoothing circuit being outputted as an output of the voltage converter circuit.