Patent ID: 6104628
Filing Date: 2000-08-15
Classification: G06F,G11C,H01L

Abstract:
An integrated-circuit device comprising:a rectangular circuit board having side edges parallel to x and y directions perpendicular to each other;a first cache memory comprising a circuit cell having side edges parallel to the x and y directions and having a length in the x direction corresponding to column addresses and a length in the y direction corresponding to row addresses, said first cache memory being disposed on an end portion of said circuit board in the y direction;a second cache memory comprising a circuit cell having side edges parallel to the x and y directions and having a length in the x direction corresponding to column addresses and a length in the y direction corresponding to row addresses, said first cache memory being disposed on an opposite end portion of said circuit board in the y direction remote from said first cache memory on said circuit board;a microprocessor comprising a circuit cell having side edges parallel to the x and y directions and disposed on an end portion of said circuit board in the x direction, said microprocessor being positioned in an area between said first cache memory and said second cache memory; anda tag memory comprising a circuit cell having side edges parallel to the x and y directions and having a length in the x direction corresponding to column addresses and a length in the y direction corresponding to row addresses, said tag memory being disposed on an opposite end portion of said circuit board in the x direction remote from said microprocessor, said tag memory being positioned in the area between said first cache memory and said second cache memory, said tag memory having row addresses converted to column addresses;said lengths in the x direction of said circuit board, said first cache memory, and said second cache memory being essentially equal to each other;said length in the x direction of said circuit board being essentially equal to the sum of the lengths in the x direction of said microprocessor and said tag memory;said lengths in the y direction of said microprocessor and said tag memory essentially equal to each other;said length in the y direction of said microprocessor being essentially equal to the sum of the lengths in the y direction of said microprocessor, said first cache memory, and said second cache memory.