Patent ID: 6469939
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A method for programing a flash memory device having an array of multiple flash memory cells formed in rows and columns with a flash memory cell located at each intersection of a column and a row, and each flash memory cell having a control gate and a floating gate formed over a substrate, and each flash memory cell having a source and a drain formed in the substrate, wherein each of the drains of the flash memory cells in a column are coupled together as a common bit line terminal, and wherein each of the sources of the flash memory cells in a column are coupled together as a common source terminal, and wherein each of the substrates of the flash memory cells in a column are coupled together as a common substrate terminal, the method comprising the steps of:selecting a flash memory cell of the array of multiple flash memory cells to be programmed; applying a control gate programming voltage to the control gate of the selected flash memory cell; applying a bit line programming voltage to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected; coupling a source resistor to the common source terminal to which the source of the selected flash memory cell is connected; and applying a substrate programming voltage that is a negative voltage to the substrate of the selected flash memory cell, wherein said negative substrate programming voltage is applied simultaneously with said source resistor being coupled to said common source terminal to maintain programming speed with reduced VDS (drain to source voltage) of said selected flash memory cell from coupling of said source resistor to said common source terminal.