Patent ID: 8799744
Filing Date: 2014-08-05
Classification: G06F,G11C,H04L

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array having a plurality of memory cells for storing data; an ECC (Error Check and Correction) processing circuit configured to receive read data from the memory cells, the ECC processing circuit configured to output, in the case where an error is detected in the read data, the error-corrected read data and a first parity flag indicating that the read data has been error-corrected, and further configured to output, in the case where an error is not detected in the read data, the read data without correcting the error and a second parity flag indicating that the read data has not been error-corrected; a data buffer configured to store the read data and the parity flags outputted from the ECC processing circuit; a first input/output pin configured to output the read data outputted from the data buffer; and a second input/output pin configured to output the first or second parity flag outputted from the data buffer, wherein the ECC processing circuit is configured to output the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.