Patent ID: 9110716
Filing Date: 2015-08-18
Classification: G06F,Y02D

Abstract:
1. A method, comprising: detecting a power-on reset event in an information handling system; requesting, by a first central processing unit (CPU), configuration information including thread scheduling information in response to the power-on reset event in the information handling system; communicating first thread scheduling information in response to the request, the first thread scheduling information identifying processor cores in a sequential format, wherein each of a first plurality of processor cores of the first CPU assigned a program thread prior to one of a second plurality of processor cores of a second CPU being assigned a program thread; communicating second thread scheduling information in response to the request, the second thread scheduling information identifying that one of the first plurality of processor cores of the first CPU is assigned a program thread and one of the second plurality of processor cores of the second CPU is assigned a program thread prior to a second one of the first plurality of processor cores of the first CPU being assigned a program thread; placing the second CPU in a low-power mode in response to each of the second plurality of processor cores of the second CPU not having any threads scheduled for execution; communicating third thread scheduling information to reduce a number of the first processor cores executing threads in the first CPU, and to improve a performance of the first CPU by the first CPU providing more resources to the first processor cores in the first CPU that are executing threads; and retaining, during the low-power mode, state information in each of the first plurality of processor cores in order to resume operations when the first central processing unit is returned to a normal mode.