Patent ID: 8460981
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A method of creating differential stress in a plurality of contacts in an integrated circuit (IC) chip, the method comprising: providing a substrate including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), the PFET and NFET each including a source/drain region; forming a silicide layer over the PFET and the NFET; depositing at least one nitride layer over the substrate; depositing a dielectric layer over the at least one nitride layer; etching a PFET contact trench through the dielectric layer down to the at least one nitride layer on the PFET; etching an NFET contact trench through the dielectric layer down to the at least one nitride layer on the NFET; opening the at least one nitride layer in the PFET contact trench; further etching the PFET contact trench through the silicide layer into the source/drain region of the PFET; depositing a layer of silicon germanium (SiGe) into the PFET contact trench, wherein an upper surface of the SiGe layer is coplanar with an upper surface of the silicide layer; filling the PFET contact trench to form a PFET contact; and filling the NFET contact trench to form a NFET contact.