Patent ID: 9188638
Filing Date: 2015-11-17
Classification: G01R

Abstract:
1. An integrated circuit chip comprising: system circuitry configured to perform a function, the system circuitry comprising a plurality of sub-circuits configured to perform the function by performing concurrent actions; debugging circuitry configured to detect one or more errors in the system circuitry's performance of the function, the debugging circuitry comprising variability circuitry; wherein the debugging circuitry is configured to functionally test the system circuitry by: at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying a delay to occurrences of a particular action of the concurrent actions by intercepting or delaying a communication through system circuitry; and recording one or more errors.