Patent ID: 9064744
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising a logic area and an embedded dynamic random access memory (eDRAM), the method comprising: providing a semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer, at least the first semiconducting layer is intrinsic or comprising a dopant of low concentration; forming deep trenches in the SOI substrate for a plurality of capacitors in the eDRAM area; growing a semiconductor epitaxial film comprising a further dopant of high concentration on sidewalls and bottoms of the first semiconductor layer of the deep trenches in the SOI; implanting an additional further dopant of a same type as the further dopant using an angled ion implant into the semiconductor epitaxial film on the sidewalls and bottoms of the deep trenches; thermally infusing the implanted additional further dopant and the further dopant of high concentration into regions adjacent to sidewalls and bottoms of the deep trenches in the first semiconductor layer to provide the regions of high dopant concentration in the first semiconductor layer around the deep trenches; and removing the semiconductor epitaxial film from the sidewalls and the bottoms of the deep trenches by selective etching.