Patent ID: 8420951
Filing Date: 2013-04-16
Classification: H01L,Y10T

Abstract:
1. A package structure formed by: providing a metal substrate, the metal substrate having a first surface, a second surface, and a side surface connecting the first surface and the second surface, the first surface and the second surface being opposite to each other, wherein a seed layer covering the first surface, the second surface, and the side surface is located on the metal substrate; forming a patterned circuit layer on a portion of the seed layer located on the first surface of the metal substrate; forming a first patterned dry film layer on the other portion of the seed layer located on the first surface of the metal substrate; electroplating a surface treatment layer on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask; removing the first patterned dry film layer; performing a chip bonding process to electrically connect a chip to the surface treatment layer; forming an encapsulant on the metal substrate, the encapsulant encapsulating the chip, the surface treatment layer, and the patterned circuit layer; and removing the metal substrate and the seed layer to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer, the package structure comprising: the patterned circuit layer; the chip electrically connected to the patterned circuit layer; and the encapsulant encapsulating the chip and the patterned circuit layer and exposing the lower surface of the patterned circuit layer.