Patent ID: 6914460
Filing Date: 2005-07-05
Classification: G06F,H03K

Abstract:
1. A system comprising a clock doubler circuit, the clock doubler circuit comprising: an input clock terminal; an output clock terminal; a first counter circuit having a clock terminal coupled to the input clock terminal and a plurality of output terminals; a divide-by-two register having a plurality of data input terminals coupled to the output terminals of the first counter circuit, a clock terminal coupled to the input clock terminal, and a plurality of output terminals; a second counter circuit having a clock terminal coupled to receive a clock update signal from the first counter circuit, a plurality of data input terminals coupled to the output terminals of the divide-by-two register, and a plurality of output terminals; and an output clock generator having a plurality of input terminals coupled to the output terminals of the second counter circuit and an output terminal coupled to the output clock terminal of the clock doubler circuit.