Patent ID: 6914852
Filing Date: 2005-07-05
Classification: G11C

Abstract:
1. A synchronizing clock signal generator for generating an output synchronizing clock signal, comprising: a clock generator having an input clock signal terminal to which an input clock signal is provided and generating therefrom first and second clock signals having first and second frequencies, respectively, the clock generator further having first and second output clock signal terminals at which the first and second clock signals are provided; a first delay-locked loop having an input clock signal terminal coupled to the first output clock signal terminal and further having an output terminal at which a first synchronizing clock signal is provided, the first synchronizing clock signal generated by the first delay-locked loop from the first clock signal; a second delay-locked loop having an input clock signal terminal coupled to the second output clock signal terminal and further having an output terminal at which a second synchronizing clock signal is provided, the second synchronizing clock signal generated by the second delay-locked loop from the second clock signal; and a selection circuit having first and second input terminals coupled to the output terminals of the first and second delay-locked loops and having an output clock signal terminal to which the first or second input terminal is coupled to provide the first or second synchronizing clock signal, respectively, as the output synchronizing clock signal, the selection circuit further having a selection terminal for receiving a selection signal on which selection of the first or second synchronizing clock signal is based.