Patent ID: 7010787
Filing Date: 2006-03-07
Classification: G06F

Abstract:
1. A program conversion apparatus for converting a given source program into a program for a multi-thread processor including a plurality of program counters and a plurality of thread execution apparatus, said plurality of thread execution apparatus being operable to fetch, decode and execute a plurality of instructions of threads simultaneously in accordance with said plurality of program counters such that is possible to execute, after a thread is created, the thread in a control speculative mode wherein a change having had an effect on a register set can be cancelled later, and to execute the thread in a data-dependent speculative mode wherein, when, after a self thread loads a value from a memory location, a parent thread by which the self thread has been created stores a value into the same memory location, at least a processing result of the self thread after the load is abandoned and the processing is re-executed, said multi-thread processor having an instruction set with which it can be executed by a single machine instruction or a combination of several machine instructions for a thread being executed by any of said thread execution apparatus to create a new thread of the control speculative mode, to end, if a designated condition is satisfied, the self thread and clear the control speculative mode of a thread of the control speculative mode created by the self thread, to abandon the created thread of the control speculative mode, to give, when a thread created by the self thread performs load from a memory location of a designated address, an instruction in advance to temporarily block the operation, to clear the load temporary blocking instruction to the designated memory address, for the thread being executed by the thread execution apparatus to create a new thread of the data-dependent speculative mode and to clear the data-dependent speculative mode of the thread of the data-dependent speculative mode created by the self thread, said program conversion apparatus comprising: a register allocation trial section for trying register allocation prior to parallelization to estimate a register allocation situation of variables and intermediate terms of an intermediate program; a fork spot determination section for determining based on a result of the register allocation trial by said register allocation trial section whether or not a conditional branch portion of the intermediate program should be converted into a parallel code for which a thread creation instruction is used and determining a parallelization execution method with the parallel code; an instruction reordering section for converting the conditional branch portion in the intermediate program into a parallel code for which the thread creation instruction is used based on a result of the determination by said fork spot determination section and referring to the result of the register allocation trial to insert an instruction for assuring a data-dependence relationship between threads through a memory into positions before and after the thread creation instruction and reorder the instructions before and after the thread creation instruction so that thread creation may be performed in an early stage; and a register allocation section for performing definite register allocation so that, regarding whether or not a physical register is allocated to the parallelized and reordered instruction sequence, the same allocation result as that upon the register allocating trial may be obtained.