Patent ID: 6559002
Filing Date: 2003-05-06
Classification: H01L,Y10S

Abstract:
In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising:a) providing a semiconductor substrate having a collar region and an adjacent region below said collar region, said collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on said region below said collar; c) depositing a layer of a-Si on said SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.