Patent ID: 8190853
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. A calculator comprising: a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table; a micro TLB that stores therein part of the page table stored in the main TLB; a page-size detecting unit that, when an address translation pair stored in the main TLB is read and is registered in the micro TLB, detects a page size of the read address translation pair; a number-of-bit determining unit that chops the read address translation pair to reduce the page size detected by the page-size detecting unit to a predetermined page size by attaching a part of offset bits, in accordance with the page size detected by the page-size detecting unit, to a page address, the offset bits and the page address being included in the read address translation pair, wherein the number of predetermined page sizes is less than the number of page sizes detected by the page-size detecting unit, and determines the number of bits of a virtual address to be added to an absolute address included in the chopped address translation pair; a registering unit that adds the virtual address with respect to the number of bits determined by the number-of-bit determining unit and adds chop information indicating that the address translation pair is chopped to the predetermined size to the chopped address translation pair to register in the micro TLB; an address searching unit that, when receiving an address translation request from the virtual address into the physical address from a processor, determines a search target bit of the address translation request for searching address translation pairs registered in the micro TLB from the chop information of the address translation pair registered in the micro TLB by the registering unit, and searches the micro TLB for an address translation pair in which a virtual address indicated by the determined search target bit and a context included in the address translation request are registered in a correlated manner; and an address responding unit that, when the address translation pair in which the virtual address indicated by the search target bit and the context included in the address translation request are registered in a correlated manner is found from the micro TLB by the address searching unit, calculates an absolute address from the address translation pair and responds to the processor, and, when the address translation pair is not found by the address searching unit, sends the address translation request to the main TLB.