Patent ID: 8575757
Filing Date: 2013-11-05
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of insulating layers stacked with one another, each insulating layer having a thorough hole, conductive wiring, and glass cloths; a semiconductor chip comprising a silicon substrate having a third surface and a fourth surface opposite to the third surface, semiconductor elements on the third surface, a silicon oxide film covering the semiconductor elements, an interlayer insulating film over the silicon oxide film, pad electrodes over the interlayer insulating film, and internal wiring layers electrically connecting the semiconductor elements with the pad electrodes, the interlayer insulating film having an electrical constant lower than that of the silicon oxide film, the semiconductor chip being mounted on the wiring substrate via first bump electrodes such that the third surface of the silicon substrate faces the first surface of the wiring substrate and the pad electrodes of the semiconductor chip are electrically connected with the conductive wiring of a first one of the plurality of insulating layers via the first bump electrodes; a resin layer between the semiconductor chip and the first one of insulating substrates and between the first bump electrodes; and second bump electrodes being on the second surface of the wiring substrate, and being electrically connected with conductive wiring of a second one of the plurality of insulating layers.