Patent ID: 6417540
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A non-volatile semiconductor memory device, comprising:a semiconductor substrate having a recess pattern on a surface thereof, a field oxide region formed in the recess pattern, and on the surface on the semiconductor substrate, a gate-electrode structure comprising a first insulator layer, a floating gate-electrode layer, a second insulating layer and a control gate-electrode layer which are deposited after the formation of the field oxide region, wherein an embedded layer is deposited over the whole surface of the gate-electrode structure including the control gate-electrode layer, and the embedded layer is embedded in a groove formed within the field oxide region, characterized by that a width (w) at a bottom of the groove is adjusted to be at most twice larger than a distance (t) between the lowest level of the surface of the embedded layer in the groove and each end of the bottom of the groove.