Patent ID: 9164836
Filing Date: 2015-10-20
Classification: G06F,G11C

Abstract:
1. A method comprising: determining a current program/erase cycle count for one or more memory cells of a non-volatile memory array; comparing the current program/erase cycle to a first target program/erase cycle count; and implementing one or more cycling endurance extending schemes based on whether the current program/erase cycle count exceeds the first target program/erase cycle count or based on whether a failure trigger associated with the one or more memory cells has been reached, the one or more cycling endurance extending schemes to include at least one of a gradual read window expansion that includes incrementally extending a read window for reading the one or more memory cells by adjusting an erase threshold voltage to cause the read window to have a larger threshold voltage range to read all programmed values from the one or more memory cells, a gradual read window shift that includes incrementally shifting the read window for reading one or more memory cells by raising the erase threshold voltage and lowering a program threshold to cause the read window to shift while maintaining a threshold voltage range to read all programmed values from the one or more memory cells, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.