Patent ID: 8278701
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A nonvolatile memory device provided with at least a first gate lamination structure and a second gate lamination structure wherein the first gate lamination structure comprises a first channel region formed on a semiconductor substrate, a first insulating film including a charge storage layer and a first conductive body, the second gate lamination structure comprises a second channel region formed abutting with the first gate lamination structure a second insulating film free of a charge storage layer and a second conductive body, and effective work function of the second gate lamination structure is higher than the effective work function of the first gate lamination structure, wherein withstanding voltage of the second gate lamination structure is more than the withstanding voltage of the first lamination structure, wherein at least an interface between a conductive body and the second insulating film in the second conductive body is made of silicon doped with p-type impurity, at least an interface between a conductive body and the first insulating film in the first conductive body is made of silicon doped with n-type impurity, the second insulating film is made of silicon oxide or silicon oxynitride and the first insulating film comprises a first and a second layers seeing from a channel region side, said first layer being made of silicon oxide or silicon oxynitride and said second layer being made of either one of silicon nitride and silicon oxynitride.