Patent ID: 6639278
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate serving as a drain region of one conductive type; a first high resistance drift layer of one conductive type provided on a surface of said semiconductor substrate; second to (n+1)th high resistance drift layers of one conductive type provided on said first high resistance drift layer (wherein n is an integer of 1 or more); a base region of other conductive type provided on a surface layer of said (n+1)th high resistance drift layer; a source region of one conductive type provided on a surface layer of said base region; a first high resistance buried layer of other conductive type provided on a surface layer of said first high resistance drift layer and a bottom layer of said second high resistance drift layer at a position right under said base region; second to nth high resistance buried layers of other conductive type respectively provided on surface layers of said second to nth high resistance drift layers and bottom layers of said third to (n+1)th high resistance drift layers at a position right under said base region; a gate electrode provided on said base region held between said (n+1)th high resistance drift layer and said source region via a gate oxide film; a source electrode in ohmic contact with said source region over said base region and said source region; and a drain electrode provided on the other surface of said semiconductor substrate; wherein a thickness of said first high resistance drift layer being established in such a manner that a depletion layer formed within said first high resistance drift layer reaches through said drain region, when a voltage lower than a sharing voltage shared by said first high resistance drift layer out of a predetermined withstand voltage between said source electrode and said drain electrode is applied to a PN junction between said first high resistance buried layer and said first high resistance drift layer.