Patent ID: 6534874
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A semiconductor device comprising a first semiconductor chip having outer electrodes and inner electrodes, and a second semiconductor chip having inner electrodes, said second semiconductor chip being stacked on said first semiconductor chip with a space provided therebetween, and said inner electrodes being electrically connected to each other, wherein through holes are provided in said inner electrodes of said second semiconductor chip, electrodes capable of being plated by electroless plating are formed on the inner walls of said through holes while being insulated from other electrodes, said second semiconductor chip is secured with an adhesive to said first semiconductor chip at portions other than said outer electrodes and said inner electrodes of said first semiconductor chip so that said inner electrodes of said first semiconductor chip are aligned with said inner electrodes of said second semiconductor chip, and said inner electrodes of said second semiconductor chip and said electrodes on said inner walls of said through holes are electrically connected to said inner electrodes of said first semiconductor chip by continuously extending metals having the same composition, and the diameter of said through hole in said inner electrode of said second semiconductor chip is made smaller than one half of the space between said first semiconductor chip and said second semiconductor chip.