Patent ID: 6785773
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A method of verifying cache coherence in a multi-node data processing system, comprising:identifying transaction pairs in an activity trace generated by simulating the data processing system, wherein the transaction pairs include: a foreign node transaction (FNT) representing a transaction originating from a processor on a system bus of a first node of the data processing system and referencing a memory location associated with a second node; and, a home node transaction (HNT) representing a transaction resulting from the FNT that occurs on a system bus of the second node; merging each of the transaction pairs to form a corresponding merged transaction (MT) wherein the merged transaction includes attributes of the FNT and the HNT; and creating a modified activity trace by replacing each of the transaction pairs with its corresponding merged transaction, whereby the modified activity trace is suitable for cache coherence verification by a coherence checker.