Patent ID: 6653958
Filing Date: 2003-11-25
Classification: H03M

Abstract:
A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels and including a digital-to-analog converter in a feedback loop, comprising:a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values Ci, where i is a positive integer from 1 to N; and a calibration phase in which the correction values Ci are calculated from values of the output of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels; wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels Xm, XM, and Xi, where i is from 1 to Nâˆ’2; wherein during a period P1i, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the sigma-delta analog-to-digital converter are processed digitally; wherein the calibration phase is executed Nâˆ’2 times, retaining the levels Xm and XM, and taking successively for the level Xi, the Nâˆ’2 levels other than the levels Xm and XM; and wherein the correction values Ci of the Nâˆ’2 levels other than Xm and XM are calculated using a sum of the processed values, the Nâˆ’2 correction values Ci being adapted to modify the Nâˆ’2 levels other than Xm and XM during the normal operation phase.