Patent ID: 8120098
Filing Date: 2012-02-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a pair of main surfaces; a first semiconductor region of a first conductivity type positioned adjacent to one of the main surfaces of the semiconductor substrate and located within the semiconductor substrate; a second semiconductor region of a second conductivity type provided adjacent to the first semiconductor region and having a carrier concentration lower than a carrier concentration of the first semiconductor region; a third semiconductor region of the second conductivity type provided adjacent to the second semiconductor region and having a carrier concentration lower than the carrier concentration of the second semiconductor region; a plurality of MOS type trench gates extended from one of the main surfaces of the semiconductor substrate into the third semiconductor region to have at least two sorts of different intervals; a fourth semiconductor region of the first conductivity type provided between the MOS type trench gates having a narrow adjacent interval and having a carrier concentration higher than the carrier concentration of the third semiconductor region; a fifth semiconductor region of the second conductivity type provided between the MOS type trench gates having the narrow adjacent interval, located within the fourth semiconductor region to be adjacent to the MOS type trench gates, and having a carrier concentration higher than the carrier concentration of the fourth semiconductor region; a sixth semiconductor region of the first conductivity type located between the MOS type trench gates having an adjacent interval larger than the narrow interval and having a carrier concentration higher than the carrier concentration of the third semiconductor region; a first electrode located between the MOS type trench gates having the narrow adjacent interval to be contacted with the fourth and fifth semiconductor regions; and a second electrode contacted with the first semiconductor region, wherein the sixth semiconductor region extends from one main surface of the semiconductor substrate into the third semiconductor region and is exposed at a part of the one main surface, the third semiconductor region is exposed at the part of the one main surface, between the sixth semiconductor region and the trench gate, and includes a part which extends from the part of the one main surface into the semiconductor substrate, and the sixth semiconductor region and the trench gate are isolated by the part of the third semiconductor region.