Patent ID: 6025743
Filing Date: 2000-02-15
Classification: H03L,Y10S

Abstract:
A phase locked loop (PLL) circuit comprising:an oscillator that oscillates at a frequency corresponding to a control input signal;a phase comparator that detects a phase difference between an oscillation signal of said oscillator and an input frequency signal and produces an error signal; anda forcible pull-in circuit that adds said error signal and a forcible pull-in signal to obtain said control input signal during an attempt period of a pull-in operation, wherein said forcible pull-in circuit comprises:a reference value generator that supplies a reference value determining a frequency step of the oscillation signal of said oscillator, anda computing circuit that computes a magnitude for said forcible pull-in signal based on said reference value,wherein said computing circuit sets said magnitude for said forcible pull-in signal at an integer multiple of said reference value, and increases said magnitude for said forcible pull-in signal stepwise while changing a polarity of said forcible pull-in signal from one of positive and negative polarities to the other polarity every attempt period of a pull-in operation.