Patent ID: 7554371
Filing Date: 2009-06-30
Classification: H03L

Abstract:
1. A delay locked loop for generating an internal clock signal locked to an external clock signal, the delay locked loop comprising: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; at least two variable delay units, which are cascade-connected to each other, to delay the external clock signal and output the delayed external clock signal to at least two respective output lines which are separated from each other in response to the control signal; and a selecting circuit for receiving at least three inputs, the at least three inputs including the selection signal and the at least two output lines, wherein the selecting circuit selects a signal on one of the at least two output lines, and provides the selected signal as the internal clock signal in response to the selection signal, wherein the selecting circuit includes,