Patent ID: 6645825
Filing Date: 2003-11-11
Classification: H01L

Abstract:
A method of fabricating a planarized structure on a semiconductor substrate, wherein an insulating material is embedded in a trench formed in the semiconductor substrate, the method comprising the steps of:providing a semiconductor substrate having a layer of silicon nitride formed thereon and at least one trench formed through the layer of silicon nitride and into the semiconductor substrate; depositing a layer of insulating material onto said layer of silicon nitride and into said at least one trench formed through the layer of silicon nitride and into the semiconductor substrate; chemical-mechanical polishing the layer of insulating material by a first CMP step comprising chemical-mechanical polishing until exposure of said silicon nitride layer is detected by an endpoint detecting device; selecting an overpolish thickness based on the percentage of substrate area occupied by said trench; and chemical-mechanical polishing the layer of insulating material by a second CMP step which removes said overpolish thickness based on the percentage of substrate area occupied by said trench.