Patent ID: 6753560
Filing Date: 2004-06-22
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:an MFMIS transistor including a first field effect transistor and a ferroelectric capacitor formed on or above said first field effect transistor with a gate electrode of said first field effect transistor working as or being electrically connected to a lower electrode of said ferroelectric capacitor, an upper electrode of said ferroelectric capacitor working as a control gate and said first field effect transistor having a first well region; and a second field effect transistor having a second well region that is isolated from said first well region of said first field effect transistor, wherein said first well region of said first field effect transistor is electrically connected to a source region of said second field effect transistor, and said gate electrode of said first field effect transistor is electrically connected to a drain region of said second field effect transistor.