Patent ID: 9214541
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a gate stack located on a semiconductor substrate, wherein said gate stack comprises, from top to bottom, a U-shaped work function metal portion, a U-shaped barrier metal portion and a gate conductor portion; a planarization dielectric layer laterally surrounding said gate stack, wherein a top surface of said gate stack is recessed relative to a top surface of said planarization dielectric layer; and an etch stop layer contiguously located on said recessed top surface of said gate stack and said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate stack and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion.