Patent ID: 8390038
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A device, comprising: an upper plate comprising one or more electrically conductive layers, said upper plate having a top surface, a bottom surface and sidewalls; a dielectric block comprising one or more dielectric layers said dielectric block having a top surface, a bottom surface and sidewalls, said top surface of said dielectric block in physical contact with said bottom surface of said upper plate; a lower plate comprising one or more electrically conductive layers, said lower plate having a top surface, a bottom surface and sidewalls, said top surface of said lower plate in physical contact with said bottom surface of dielectric block; a spreader plate comprising one or more electrically conductive layers, said spreader plate having a top surface, a bottom surface and sidewalls, a top surface of said spreader plate in physical and electrical contact with all of said bottom surface of said lower plate; a dual-damascene upper wire, said dual-damascene upper wire comprising a first wire region and multiple and integral first via regions, said first wire region and said integral first via regions formed in a same first interlevel dielectric layer, said first via regions in physical and electrical contact with said top surface of said upper plate, regions of said same first interlevel dielectric layer intervening between said via portions and between a bottom surface of said wire region between said via regions; two or more dual-damascene lower wires, each of said two or more dual-damascene lower wires having a second wire region and an integral second via region, the second wire regions and the integral second via regions formed in a same second interlevel dielectric layer, the second wire regions in physical and electrical contact with said bottom surface of said spreader plate; and wherein said upper plate, said dielectric block and said lower plate are formed in and abut sidewalls of a same trench in an intermediate dielectric layer, said trench between said first interlevel dielectric layer and said second interlevel dielectric layer, said trench extending from a top surface of said dielectric layer to a bottom surface of said intermediate dielectric layer.