Patent ID: 6784023
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method of fabricating a multi-level stack of semiconductor substrate elements, each semiconductor substrate element of the substrate elements including integrated circuitry, comprising:providing a first semiconductor substrate element having a first side including integrated circuitry thereon and having a back side in a first wafer having a periphery having a portion thereof including a flat; providing a second semiconductor substrate element having a first side including integrated circuitry thereon and having a back side in a second wafer having a periphery having a portion thereof including a flat; providing a heat sink element for the multi-level stack between the first and second semiconductor substrate elements; stacking the first semiconductor substrate element and the second semiconductor substrate element in a superimposed relationship having the back side of the first semiconductor substrate element facing the back side of the second semiconductor substrate element having the periphery of the first semiconductor substrate element substantially aligned with the periphery of the second semiconductor substrate element, the first semiconductor substrate element and the second semiconductor substrate element for locating a portion of the integrated circuitry on the first semiconductor substrate element vertically spaced from a portion of the integrated circuitry on the second semiconductor substrate element for vertical alignment of the first semiconductor substrate element and the second semiconductor substrate element; and severing from the multi-stack stack traversely at least one dice pair comprising a die from the first semiconductor substrate element and a second die from the second semiconductor substrate element; and adhesively attaching the first semiconductor substrate element and the second semiconductor substrate element.