Patent ID: 7549081
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. A method of allocating functionality to processor elements in a processor array, wherein the processor array comprises a plurality of processor elements arranged in an array of rows and columns, the processor elements being interconnected by buses running between the rows and columns and by switches located at the intersections of the buses, wherein, in operation of said processor array, data is transferred during time slots between processor elements over horizontal buses running between the rows of processor elements and over vertical buses running between the columns of processor elements, the method comprising: identifying one row as a redundant row to which no functionality is initially allocated, such that, in the event that a first processor element is found to be faulty, functionality can be removed from the row that contains said first processing element, and can be allocated instead to the redundant row; and when allocating functionality to the processor elements, such that data is scheduled to be transferred during a first time slot from a first processor element in a first row to a second processor element in a second row, which is different from the first row, via one of said switches without using any vertical bus, reserving said time slot for said scheduled data transfer on a segment of a vertical bus that would be used in the event of a reallocation of functionality following a determination that either said first processor element or said second processor element was faulty.