Patent ID: 7962829
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. A logic operation parity prediction circuit, which predicts a parity of an execution result of a logic operation on a pair of input operands, comprising: a first parity inversion condition computation circuit, which computes the parity inversion condition for AND logic operations for said pair of input operands; a second parity inversion condition computation circuit, which computes the parity inversion condition for OR logic operations for said pair of input operands; a selector, which selects the parity inversion condition of said first parity inversion condition computation circuit or of said second parity inversion condition computation circuit, according to a logic operation instruction; a parity prediction circuit, which performs EOR operations on parity bits of said pair of input operands; a correction signal generation circuit, which performs EOR operations on one of the input operands and generates a correction signal; and a correction circuit, which uses said correction signal and said parity inversion condition of said selector to correct the parity prediction signal of said parity prediction circuit, and outputs a predicted parity according to said logic operation instruction.