Patent ID: 7855969
Filing Date: 2010-12-21
Classification: G01R

Abstract:
1. A method for providing visibility of intermediate signals of a high speed SERDES core, comprising: providing a plurality of test points of the high speed SERDES core; selecting desirable test points from the plurality of test points further including selecting a first test point for having a raw receive signal to appear at a first pin on a chip and a second test point for having Dynamic Feedback Equalization (DFE) processed signal to appear at a second pin on the chip, the first and second test points located on the high speed SERDES core; tapping signals at the plurality of test points further including buffering the tapped signals in the high speed SERDES core; running the buffered signals at the desirable test points through a programmable analog MUX to dynamically select a desirable signal which gates out through a corresponding pin; and directing the multiplexed signals to a restricted number of debug port pins to control required pin count.