Patent ID: 9214943
Filing Date: 2015-12-15
Classification: H03K

Abstract:
1. A fractional frequency divider for dividing a digital input clock signal by a fraction m/n, wherein a divided output signal has m pulses for every n pulses of the input signal, the fractional frequency divider comprising: a counter for counting input clock signal pulses, wherein the counter comprises a first counter module that is a down-counter initially loaded with the value 2n/m−1 and arranged to decrement by 2 with every input clock pulse; a clock gating module including a first clock gating cell for receiving the input clock signal; a second clock gating cell for receiving an inverted version of the input clock signal, wherein the first and second clock gating cells are arranged to enable a pulse of the input clock signal and a pulse of the inverted version of the input clock signal to pass to respective outputs thereof when an output of the counter reaches a preset value; and a combiner for combining the outputs of the first and second clock gates.