Patent ID: 6137721
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A memory device comprising:a row of memory cells, each memory cell including:a memory transistor having a source and a drain of a first conductivity type, a channel region defined between the source and drain, a floating gate insulatively formed over the channel and an adjacent region, a layer of interpoly dielectric formed on the floating gate formed over the adjacent region, and an upper plate formed on the interpoly dielectric over the adjacent region; andan access transistor having a source and a drain of a second conductivity type, and a gate, the drain of the access transistor being connected to the drain of the memory transistor;a page line connected to the source of each memory transistor in the row;an erase line connected to the upper plate of each memory transistor;a well line connected to set a potential on the channel region of each memory transistor;a plurality of enable lines connected to the access transistors in the row of memory cells so that each enable line is connected to the gate of an access transistor; anda plurality of sense lines connected to the memory cells so that each sense line is connected to a memory cell.