Patent ID: 6521959
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:a transistor active region comprising a predetermined region of the semiconductor layer; at least one body contact active region spaced apart from the transistor active region, the body contact active region including a portion of the semiconductor layer; a semiconductor residue layer disposed over the entire surface of the buried insulating layer between the transistor active region and the body contact active region, the semiconductor residue layer being thinner than the semiconductor layer; a partial trench isolation layer surrounding upper sidewalls of the transistor active region and the body contact active region, the partial trench isolation layer being disposed on the semiconductor residue layer; a full trench isolation layer interposed between the partial trench isolation layer and the transistor active region, the full trench isolation layer being in contact with the buried insulating layer; a body extension of the first conductivity type extended from a predetermined sidewall of the semiconductor residue layer toward the transistor active region, the body extension electrically connecting the transistor active region to the semiconductor residue layer and being covered with the partial trench isolation layer; and an insulated gate pattern crossing over the transistor active region, the insulated gate pattern being overlapped with the body extension.