Patent ID: 6092172
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A data processor, comprising:a central processing unit;a first translation lookaside buffer in which a part of address translation information for translating a virtual address treated by said central processing unit to a physical address is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to a virtual page number outputted by said central processing unit;a second translation lookaside buffer in which address translation information regarding an instruction address out of the address translation information possessed by said first translation lookaside buffer is stored and which associatively retrieves, from the address translation information, a physical page number corresponding to the virtual page number that is outputted by said central processing unit upon instruction fetching said second translation lookaside buffer being coupled to said first translation buffer; anda buffer control circuit which, when associative retrieval with respect to a virtual page number in said second translation lookaside buffer results in a retrieval miss, a virtual page number concerned with the retrieval miss is applied to said first translation lookaside buffer for an associative retrieval therein and the address translation information for said associative retrieval in said first translation lookaside buffer with respect to said virtual page number concerned with the retrieval miss is supplied to said second translation lookaside buffer.