Patent ID: 6463560
Filing Date: 2002-10-08
Classification: G01R

Abstract:
A method for implementing a BIST scheme in an integrated circuit for testing RTL controller data paths in the integrated circuit, comprising the steps of:extracting a state table from a controller netlist of a controller circuit within the integrated circuit; selecting untested RTL elements from an RTL circuit in the integrated circuit; extracting test control and data flow (TCDF) information for the selected RTL elements from the extracted state table, controller netlist and a data path of the circuit; performing a symbolic testability analysis of the extracted test control and data flow information to derive a test environment; identifying a controller input sequence for the derived test environment; modifying an existing controller input sequence of the integrated circuit with the identified controller input sequence; synthesizing a BIST controller from the modified controller input sequence; and modifying the integrated circuit with a BIST architecture having the synthesized BIST controller and the controller input sequence for testing of the integrated circuit.