Patent ID: 9171935
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A FinFET semiconductor device fabrication process comprising: forming a plurality of FinFET fins upon a semiconductor substrate; forming a first dielectric layer upon the semiconductor substrate, an upper surface of the first dielectric layer being coplanar with upper surfaces of the FinFET fins; forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins; revealing first segments of the FinFET fins by removing first portions of the first dielectric layer covering the FinFET fins in source-drain regions adjacent to respective dummy gates; subsequent to revealing first segments of the FinFET fins, removing the dummy gates, and; subsequent to the removal of the dummy gates, revealing second segments of the FinFET fins by removing second portions of the first dielectric layer covering the FinFET fins in channel regions.