Patent ID: 7994620
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A stacked semiconductor device, comprising: a circuit base having an element mounting part and a connection part; a first semiconductor element bonded on the element mounting part of the circuit base; a second semiconductor element bonded on the first semiconductor element via an adhesive layer with a thickness of 50 μm or more, wherein the adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less and greater than zero ppm; an electrode pad formed on the first semiconductor element and electrically connected to the connection part via a bonding wire, the electrode pad projecting from an upper face of the first semiconductor element, and an upper end of the electrode pad being in the adhesive layer; and a sealing resin formed on the circuit base to seal the first and second semiconductor elements together with the bonding wire, wherein a tensile stress acting on the first or second semiconductor element due to the adhesive layer during a thermal cycle test is 300 MPa or less and greater than zero MPa.