Patent ID: 8390075
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: an one-time-programmable (OTP) cell including an OTP gate, a fuse electrode, a first high-density impurity region that overlaps with the fuse electrode and a first gate insulating layer between the fuse electrode and the first high-density impurity region; and an electrically erasable programmable read-only memory (EEPROM) cell including a memory transistor having a first gate, a selection transistor having a second gate, a second high-density impurity region that overlaps with the first gate and the second gate and a second gate insulating layer between the first gate and the second high-density impurity region, wherein the first gate insulating layer has a thickness in the range from 1.5 nm to 4 nm, and the second gate insulating layer has a thickness in the range from 6 nm to 8 nm.