Patent ID: 6725438
Filing Date: 2004-04-20
Classification: G06F

Abstract:
An automated method for designing an initial integrated circuit layout with a computer, based upon an electronic circuit description and by using a cell library containing cells that each have an associated relative delay value, comprising the steps of:(a) selecting a plurality of cells from the cell library that are intended to be coupled to each other with a plurality of wires and that can be used to implement a digital circuit based on the electronic circuit description input to the computer; and (b) determining, using a portion of a computer program that contains a sequence of instructions, an initial intended area of each of the selected plurality of cells, the initial intended area of at least some of the selected plurality of cells being determined using the associated relative delay values of the some selected cells and initial intended lengths of some of the wires coupled to each of said some selected cells in order to meet predetermined timing constraints associated with each of said some cells that are coupled to another cell.