Patent ID: 8166088
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A processor for implementing fast Fourier transform, comprising: a fast Fourier transform (FFT) processor unit for operating a radix-2 a first butterfly-III unit for operating a radix-2 a second butterfly-III unit serial coupled to the first butterfly-III unit by a second complex number multiplier, for operating a radix-2 a second butterfly-I unit, which is coupled to the first butterfly-III units via a first complex number multiplier, for receiving 2 a first butterfly-I unit, for receiving 2 a coefficient generator for generating and transmitting a plurality of twiddle factors to the first and second complex number multipliers; a multiplexer having a control terminal, a output terminal and two input terminals, wherein one input terminal is coupled to the output of the first butterfly-I unit, another input terminal receives 2 a bit-reverse circuit, which is coupled to the output of the second butterfly-III unit, for rearranging the output data of the first fast Fourier transform processor; wherein: each of the first and second butterfly-I units has a feedback path formed between of a feedback input and a feedback output thereof; the first butterfly-I unit has a 128-word feedback register coupled between the feedback input and the feedback output thereof; and the second butterfly-I unit has a 64-word feedback register coupled between the feedback input and the feedback output thereof.