Patent ID: 6340614
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A method of forming a DRAM cell with a capacitor directly over a transistor having a recessed-gate, the method comprising:a. forming isolation regions in a semiconductor substrate; b. forming a heavily-doped region in said semiconductor substrate; c. forming a first dielectric layer and a second dielectric layer on said semiconductor substrate; d. forming a trench in said semiconductor substrate by an anisotropic etching process and also forming source/drain regions of said transistor, wherein said trench is prepared for fabricating said recessed-gate; e. forming first spacers with dopant source material on sidewalls of said trench; f. forming a gate dielectric layer within said trench; g. forming a first plug on said gate dielectric layer as a gate plug; h. forming an isolation film on said first plug; i. forming source/drain extensions of said transistor; j. forming a second plug on said isolation film, wherein a top surface of said second plug has the same level with a top surface of said second dielectric layer; k. removing said second dielectric layer; l. forming second spacers on sidewalls of said first spacers; m. forming third spacers on sidewalls of said second spacers, wherein said third spacers is composed of conductive material; n. removing said second spacers and upper portions of said first spacers; and o. forming said capacitor on said second plug and said third spacers.