Patent ID: 6288573
Filing Date: 2001-09-11
Classification: G11C,H03K

Abstract:
A semiconductor device comprising:a first power supply node for receiving a first power supply potential;a second power supply node for receiving a second power supply potential lower than said first power supply potential; anda first logic circuit coupled between said first and second power supply nodes, operating in an operation mode to receive at least one signal and issue a result of a predetermined first logical operation to a first output node, and operating in a standby mode to hold the result of said first logical operation existing at the time of transition from said operation mode to said standby mode,said first logic circuit including:a first logical operation unit arranged between first and second internal nodes, and issuing the result of said first logical operation in accordance with said signal,said first logical operation unit including:a first internal circuit coupled between said first internal node and said first output node for connecting said first internal node to said first output node in accordance with said signal, anda second internal circuit coupled between said second internal node and said first output node for connecting said second internal node to said first output node in accordance with said signal, said first logic circuit further including:a first connection circuit coupled between said first internal node and said first power supply node for connecting said first internal node to said first power supply node during said operation mode and when said first internal circuit connects said first internal node to said first output node, said first connection circuit receiving said signal and a first control signal activated in said operation mode, anda second connection circuit coupled between said second internal node and said second power supply node for connecting said second internal node to said second power supply node during said operation mode and when said second internal circuit connects said second internal node to said first output node, said second connection circuit receiving said signal and a second control signal formed of a complementary signal of said first control signal,wherein a value of a leak current of said first correction circuit in the disconnection state is smaller than a value of a leak current of said first internal circuit in the disconnected state, anda value of a leak current of said second connection circuit in the disconnected state is smaller than a value of a leak current of said second internal circuit in the disconnected state.