Patent ID: 8259895
Filing Date: 2012-09-04
Classification: G11C

Abstract:
1. A shift register, comprising: first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node, a second input node and an output node, wherein the plurality of shift register stages is grouped into L sections such that each section comprises a corresponding number of consecutive shift register stages, L being a positive integer greater than three, wherein each section has at least two consecutive shift register stages, wherein the first and second input nodes of each shift register stage in each odd section are electrically and respectively coupled to two control signal bus lines of the first, second, third and fourth control signal bus lines for receiving corresponding two control signals of the first, second, third and fourth control signals, Bi