Patent ID: 7115509
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A method of fabricating a source interconnect to a memory cell, comprising: forming a layer of dielectric material overlying a gate stack, a source region and a drain region of the memory cell; forming a first mask layer overlying the layer of dielectric material; patterning the first mask layer to expose a portion of the layer of dielectric material over at least the source region; removing a portion of the exposed portion of the layer of dielectric material to form a trench shaped region and expose the source region; removing the first mask layer; forming a layer of polysilicon overlying the layer of dielectric material and trench shaped region to be in contact with the exposed source region; forming a second mask layer overlying the layer of polysilicon; patterning the second mask layer to expose a portion of the layer of polysilicon over at least the trench shaped region, wherein patterning the first and second mask layers further comprises patterning the first and second mask layers with the same pattern; implanting ions in the exposed portion of the layer of polysilicon, thereby forming an implanted portion of the layer of polysilicon and an non-implanted portion of the layer of polysilicon; removing the second mask layer; and selectively etching the layer of polysilicon to preferentially remove the non-implanted portion, thereby forming the source interconnect in the trench shaped region.