Patent ID: 6584027
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory cell array having a plurality of memory cells and a plurality of bit lines for transmitting data to said memory cells, respectively; a plurality of sense amplifier arrays each including a plurality of sense amplifiers for amplifying respective data on said bit tines; a first sense amplifier control circuit for generating a first activating signal to be supplied to said sense amplifiers in all of said sense amplifier arrays simultaneously; and a plurality of second sense amplifier control circuits for generating second activating signals having different activating timings from each other and being supplied to said sense amplifier arrays, respectively, wherein said sense amplifiers each include: a latch for amplifying and holding data on corresponding bit line of said bit lines in response to the activation of said first activating signal; an amplifying transistor configured separately from said latch, for amplifying a voltage level of said bit line received at a gate of said amplifying transistor upon receiving the activation of one of said second activating signals at a source of said amplifying transistor; and a first column switch for connecting the drain of said amplifying transistor to a read data bus line in response to the activation of a column selecting signal.