Patent ID: 6449712
Filing Date: 2002-09-10
Classification: G06F

Abstract:
A processor element operable to execute N-bit instructions, including an N-bit branch instruction, or M-bit instructions, including an M-bit branch instruction, where M and N are integers, and M is less than N, the processor element executing the M-bit instructions according to the steps of:indicating in the M-bit branch instruction a target address of an M-bit target instruction and an M-bit delay slot instruction immediately following the M-bit branch instruction in a sequence of M-bit instructions; emulating the M-bit branch instruction with a sequence of N-bit instructions that includes a prepare target instruction for loading a target register with the target address and the N-bit branch instruction; using the target address with the N-bit branch to complete execution of the M-bit branch instruction; and emulating the delay slot instruction with a sequence of one or more N-bit instructions that are executed before execution of the N-bit instructions that emulate the M-bit target instruction.