Patent ID: 6191000
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A shallow trench isolation (STI) method used in a semiconductor wafer, the surface of the semiconductor wafer comprising a plurality of active regions and a plurality of shallow trenches for electrically isolating the active regions, the surface of the semiconductor wafer further comprising one alignment region having at least one recess of predetermined pattern in it, the method comprising the following steps:forming an insulation layer on the surface of the semiconductor wafer that completely fills the trenches and the recess in the alignment region;etching the insulation layer on the active regions and alignment region to a predetermined thickness;defining at least one working area on the surface of the semiconductor wafer which comprises a plurality of active regions, and etching the insulation layer on the working area and the alignment region to reduce the thickness of the insulation layer on the working area and to completely remove the insulation layer on the alignment region; andperforming a chemical mechanical polishing process to horizontally remove the insulation layer on the surfaces of the active regions and to approximately level the surfaces of the insulation layer in the trenches with the surfaces of the active regions.