Patent ID: 7024651
Filing Date: 2006-04-04
Classification: H03K

Abstract:
1. A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA, said method comprising the steps of: designating in a bus macro at least one row of bus lines as a routing resource between at least first and second design areas of the FPGA; creating a first routing configuration from the bus macro for a first design for controlling a routing of signals over said designated at least one row of bus lines from said first design area to said second design area of the FPGA, said first design including said first routing configuration; creating a second routing configuration from the bus macro for a second design for controlling a routing of signals over said designated at least one row of bus lines from said second design area to said first design area of the FPGA, said second design including said second routing configuration; embedding the bus macro into respective top level design programs of the first design and the second design, respectively; compiling the top level design programs of the first and second designs to render corresponding first and second bit stream files for partially reconfiguring the FPGA therewith, wherein the compiling of the top level design program of the first design is independent of the compiling of the top level design program of the second design; partially reconfiguring the FPGA in the first design area with the first bit stream file corresponding to the top level design program for the first design; and partially reconfiguring the FPGA in the second design area with the second bit stream file corresponding to the top level design program for the second design.