Patent ID: 6799249
Filing Date: 2004-09-28
Classification: G06F

Abstract:
In a data processing system having a first instruction processor directly coupled to a system controller dedicated only to and accessible only by said first instruction processor wherein said system controller contains an internal cache memory within said system controller wherein said internal cache memory has an instruction interface and an operand interface and wherein said first processor makes a first plurality of instruction memory access requests of said internal cache memory via said instruction interface and wherein a second plurality of said instruction memory access requests of said internal cache memory via said instruction interface result in a third plurality of cache misses and wherein said first instruction processor makes a fourth plurality of operand memory access requests of said internal cache memory via said operand interface and wherein a fifth plurality of said operand memory access requests of said internal cache memory via said operand interface result in a sixth plurality of cache misses, the improvement comprising:a. a first queue directly coupled to said instruction interface for queuing said third plurality of cache misses and a second queue directly coupled to said operand interface for queuing said sixth plurality of cache misses.