Patent ID: 6063662
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A method for fabricating a semiconductor device including a metal silicide layer having a reduced potential for cracking, the method comprising the sequential steps of:forming, within a semiconductor substrate, at least two isolating regions, separated by an isolated region;forming a floating gate layer over the substrate;forming a dielectric layer on the floating gate layer and on at least a portion of each of the two isolating regions;forming a control gate layer having a first predetermined thickness on at least a portion of the dielectric layer and at least partially located directly over at least a portion of the floating gate layer, wherein the step of forming the control gate layer comprises a non-continuous deposition process comprising:forming a first, lower portion of the control gate layer on at least a portion of the dielectric layer and at least partially located directly over at least a portion of the floating gate layer, the first, lower portion having a preselected thickness;allowing the first, lower portion to cool down for a predetermined period of time, thereby increasing the flow and/or coverage of a second, upper portion of the control gate layer deposited thereon in a following step; andforming the second, upper portion of the control gate layer over the first, lower portion of the control gate layer, the second, upper portion having a preselected thickness substantially equal to that of the first, upper portion;removing part of the second, upper portion of the control gate layer to achieve a predetermined second thickness of the control gate layer which is less than the predetermined first thickness and sufficient to remove any depressions in the surface thereof and reduce cracking of a silicide layer formed to overlie the control gate layer in a subsequent step;forming the silicide layer on at least a portion of the reduced thickness control gate layer; andpatterning the silicide and control gate layer to form a control gate arrangement.