Patent ID: 8843728
Filing Date: 2014-09-23
Classification: G06F

Abstract:
1. A processor comprising: first instruction logic to execute instructions; a first accelerator coupled to the first instruction logic via a first interconnect, the first accelerator to perform at least one operation on data received from the first instruction logic, the first accelerator comprising a heterogeneous resource with respect to the first instruction logic; and communication logic to enable inter-sequencer communication between the first instruction logic and the first accelerator according to an extension to a native communication protocol, wherein responsive to receipt of an authentication message from the first accelerator via the first interconnect, the first instruction logic is to map an accelerator identifier to a sequencer identifier to be used during execution of a sequencer-aware instruction by the first instruction logic and to enable communication with the first accelerator along the first interconnect, the authentication message responsive to generation of an assertion signal on a second interconnect corresponding to a non-native interconnect, by the first instruction logic, and the first instruction logic to select the first accelerator to obtain a lock on the second interconnect, receive a registration message from the selected accelerator, and register the selected accelerator responsive to the registration message, wherein the first accelerator is to compete with at least another accelerator for the lock.