Patent ID: 7173939
Filing Date: 2007-02-06
Classification: H04J,H04L

Abstract:
1. A synchronous transfer module (STM) mapping circuit that performs a mapping process for storing data in transmission frames while distributing the data in byte units to prescribed logical channels, comprising: a packet length detection circuit for receiving a plurality of byte data that have been parallel-expanded to M signals that contain pad bytes and generating byte effectiveness information that indicates whether each item of the byte data is effective data or said pad bytes; routing circuits for generating routing information for rearranging each of said byte data in a prescribed order while using said byte effectiveness information to eliminate said pad bytes; packet filter circuits for taking in each item of packet data for each logical channel in accordance with channel number signals that indicate which logical channel said packet data belong to; M×M switches for rearranging packet data of each of said logical channels in a prescribed order while eliminating said pad bytes in accordance with said routing information; and packet memories for holding, for each of said logical channels, packet data that have been rearranged by said M×M switches; where k is a positive integer and M=2