Patent ID: 8728889
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming a conductive structure including a plurality of insulating interlayer patterns and a plurality of conductive patterns alternately and repeatedly laminated on a substrate, wherein each of the plurality of conductive patterns includes a pad region; forming an upper insulating interlayer on the conductive structure; forming a hard mask pattern on the insulating interlayer, the hard mask pattern including a plurality of holes, each of the plurality of holes being aligned to the pad region, respectively; forming first contact holes by etching the upper insulating interlayer and an uppermost insulating layer pattern of the insulating interlayer patterns using the hard mask pattern until upper surfaces of a first group of the plurality of conductive patterns are exposed; forming first buffer conductive patterns selectively on the upper surfaces; forming second contact holes by etching the upper insulating interlayer using the hard mask patterns and the first buffer conductive patterns until an upper surface of a lowermost conductive pattern is exposed, wherein the first buffer conductive patterns protect the first group of the conductive patterns; and forming the contact plugs by filling a conductive material in the first and the second contact holes.