Patent ID: 6707723
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A circuit for a synchronous semiconductor memory device, comprising:a first delay unit to receive a strobe signal and delay the strobe signal to provide a delayed strobe signal; a fetch circuit to fetch data from an input data signal to generate a first input data signal; the fetch circuit to perform the fetch responsive to the delayed strobe signal; a detection unit to detect a relative phase difference between the strobe signal and a clock signal; a second delay unit to receive the delayed strobe signal and further delay the delayed strobe signal to generate a second delayed strobe signal; the second delay unit operable to adjust a duration of the further delay dependent on the relative phase difference detected by the detection unit; and a data input synchronization unit to fetch data from the first input data signal to generate a second data signal; the data input synchronization unit to perform the fetch responsive to the further delayed strobe signal.