Patent ID: 6594720
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A data processing system comprising:a data processor adapted so that it may be coupled to a PC card; a read only memory (ROM); a dynamic random access memory (DRAM); a first PC card connector connectable to a PC card; and an external bus coupled to the data processor, the ROM, the DRAM, and the first PC card connector; wherein the data processor accesses the external bus based on a physical address in an address space, wherein the address space is divided into a plurality of areas assigned fixedly to the ROM, the DRAM and the PC card; and wherein the data processor comprises: a central processing unit, wherein the central processing unit outputs an internal logical address; and a memory management unit coupled to the central processing unit, wherein the memory management unit outputs a physical address applicable to the external bus based on the internal logical address.