Patent ID: 6463549
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A device for patching code residing on a ROM module, the device is adapted to be coupled to a processor, to an address bus and to an instruction bus, the device comprising:a patch detect logic comprising a RAM module, adapted to store M fields, wherein each of the M fields is one bit long, each field indicating a validity of a content of a GROUP of at least two memory words of said ROM module, wherein said patch detect logic is adapted to receive at least a portion of an ADDRESS of a requested memory portion within the ROM module, said ADDRESS being provided on said address bus and to select accordingly a selected field out of said M fields, M>1; and a patch translation logic, adapted to receive the selected field and to either (a) provide a content of the requested memory portion the processor, if the selected field indicates that the requested memory portion is a part of a GROUP having a valid content; (b) provide to the processor a patched code from a patch memory module accessed by the patch translation logic, if the selected field indicates that the requested memory portion is a part of a GROUP having a non valid content, wherein each memory word of the RAM module is adapted to store a plurality of fields out of the M fields, and wherein the patch detect logic further comprises of a word selection logic, for receiving a content of a selected memory word, the selected memory word stores the selected field, and for providing the selected field.