Patent ID: 6016549
Filing Date: 2000-01-18
Classification: G06F

Abstract:
A peripheral unit, which is adapted to be coupled to a computer system, comprising:an MPU;a sequencer circuit coupled to said MPU, wherein said MPU and said sequencer circuit are each configured to be selectively activated to perform a specific function and subsequently deactivated upon the completion of said specific function, and wherein said sequencer circuit comprises a first sequencer circuit configured to control data transfers and a second sequencer circuit configured to control data transfers; anda clock generating circuit coupled to said MPU and said sequencer circuit, wherein said clock generating circuit is configured to provide said MPU, when activated, a first clock signal, and to provide said first sequencer circuit, when activated, a second clock signal, and to provide said second sequencer circuit, when activated, a third clock signal, and, wherein said clock generating circuit is further configured to halt said first clock signal to said MPU when said MPU is deactivated, to halt said second clock signal to said first sequencer circuit when said first sequencer circuit is deactivated, and to halt said third clock signal to said second sequencer circuit when said second sequencer circuit is deactivated.