Patent ID: 8423692
Filing Date: 2013-04-16
Classification: G11B

Abstract:
1. A non-transitory computer useable medium encoded with a computer program product and useable with programmable computer processor to read information from an information storage medium using an asynchronous read channel assembly wherein said asynchronous read channel assembly comprises a data cache and a data storage device controller, comprising: computer readable program code which causes said programmable computer processor to generate over a time interval an analog waveform comprising said information; computer readable program code which causes said programmable computer processor to provide throughout said time interval said analog waveform to an analog to digital converter disposed in said asynchronous read channel assembly wherein said analog to digital converter is interconnected with a finite impulse response filter by a first communication link comprising a test port, and wherein said test port is interconnected with said data cache by a second communication link, and wherein said data cache is interconnected by a third communication link with a microprocessor interface comprising a plurality of registers, wherein each of said plurality of registers comprises a different register setting; computer readable program code which causes said programmable computer processor to provide one or more first operating parameters to said read channel assembly; computer readable program code which causes said programmable computer processor to generate a digital signal throughout a first portion of said time interval from said analog waveform using said one or more first operating parameters; computer readable program code which causes said programmable computer processor to retrieve an error correction rate threshold; computer readable program code which causes said programmable computer processor to error correct said digital signal during said first portion of said time interval at an actual error correction rate; computer readable program code which causes said programmable computer processor to determine if said actual error correction rate is greater than said error correction rate threshold; computer readable program code which, if said actual error correction rate is not greater than said error correction rate threshold, causes said programmable computer processor to continue to generate said digital signal throughout said time interval using said one or more first operating parameters; computer readable program code which, if said actual error correction rate is greater than said error correction rate threshold, causes said programmable computer processor to capture said digital signal using said test port and said register settings and store said digital signal in said data cache during said first portion of said time interval; computer readable program code which causes said programmable computer processor to read said digital signal from said cache during said first portion of said time interval; computer readable program code which causes said programmable computer processor to generate one or more second operating parameters during said first portion of said time interval; computer readable program code which causes said programmable computer processor to provide said one or more second operating parameters to said read channel assembly during said first portion of said time interval; computer readable program code which causes said programmable computer processor to generate said digital signal using said one or more second operating parameters during a second portion of said time interval.