Patent ID: 6084433
Filing Date: 2000-07-04
Classification: G06F,H03K

Abstract:
A high speed SCSI input receiver, comprising:a high-level input buffer having a first switching threshold voltage, the high-level input buffer connected to receive an input signal and to produce an output in response thereto;a low-level input buffer having a second switching threshold voltage, lower than the first switching threshold voltage, the low-level input buffer connected to receive the input signal and to produce an output signal in response thereto;a high-level threshold setting master circuit, defining a high-level control voltage, the high-level control voltage biasing the high-level input buffer so as to maintain the first switching threshold voltage of the high-level input buffer at a substantially constant value without regard to temperature and process parameter variations;a low-level threshold setting master circuit, defining a low-level control voltage, the low-level control voltage biasing the low-level input buffer so as to maintain the second switching threshold voltage of the low-level input buffer at a substantially constant value without regard to temperature and process parameter variations;logic circuitry connected to receive the output signals from the high-level input buffer and the low-level input buffer, the logic circuitry defining an output such that the output does not switch from a low level to a high level unless the input has exceeded the second switching threshold, and such that the output does not switch from a high level to a low level unless the input has dropped below the first switching threshold;an input inverter including a p-channel transistor and an n-channel transistor coupled together at their common drain terminals to define an output node, their respective input terminals coupled together in common and connected to receive the input signal;a p-channel current source transistor connected between a power supply and the input inverter's output node;an n-channel current source transistor connected between the input inverter's output node and ground potential; andwherein the p-channel and n-channel current source transistors have gate terminals coupled together in common and connected to receive the high-level control voltage, the high level control voltage biasing the current source transistors to thereby adaptively adjust the first switching threshold voltage.