Patent ID: 6556593
Filing Date: 2003-04-29
Classification: G11B,H04J,Y10S

Abstract:
Interconnection apparatus for high-speed signals organized in synchronous frames, said high-speed signals including a plurality of low-speed data signals as tributary signals, said interconnection apparatus comprising:a plurality of parallel processing modules (9-T, 9-R; 66-1, . . . 66-4) with first interfaces (5,6; 12-1 . . . 12-4; 12-i-T, 12-i-R) and second interfaces (7,8; 16-1 . . . 16-4; 16-i-T, 16-i-R), each of said plurality of parallel processing modules provided for manipulating portions of said tributary signals in parallel with the manipulating of other portions of said tributary signals by other of said plurality of parallel processing modules, and configurable multiplexing/demultiplexing means (14, 34, 38, 40, 42) enabling each said plurality of parallel processing module (66-i) to access any portion of an arbitrarily preselected tributary signal in said high-speed signals and providing said accessed portion to at least one of said plurality of parallel processing modules without disassembling and demultiplexing said signals; wherein the configurable multiplexing/demultiplexing means (14; 34, 38, 40, 42) includes a pipeline arrangement (20, 22-1 . . . 22-4; 24-1 . . . 24-4, 26; 32, 36; 58, 62, 70) for sequentially transferring a high-speed signal along the plurality of parallel processing modules (66-i) and for selectively transferring tributary signals into and out of the first interfaces (12-i) of said plurality of parallel processing modules, according to configuration information (29; 50; 74) provided to control means (28-1 . . . 28-4; 30-1 . . . 30-4; 46; 72) for said multiplexing/demultiplexing means.