Patent ID: 6784033
Filing Date: 2004-08-31
Classification: C23C,H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device having at least a gate electrode, a gate insulating film on the gate electrode, an amorphous semiconductor layer on the gate insulating film and a pair of n+ type semiconductor layers formed on the amorphous semiconductor layer, said method comprising the steps of:placing a substrate having said gate electrode formed thereon in a reaction chamber; introducing a film forming gas into said reaction chamber; forming said gate insulating film on sais gate electrode by exciting said film forming gas in said reaction chamber; introducing a cleaning gas into said reaction chamber after the formation of said gate insulating film; etching an unnecessary layer formed on an inside of said reaction chamber by exciting said cleaning gas; forming said pair of n+ type semiconductor layers on said amorphous semiconductor layer; and forming source and drain electrodes on said pair of n+ type semiconductor layers, wherein an inner edge and an outer edge of said pair of n+ type semiconductor layers are coextensive with an inner edge and an outer edge of said source and drain electrodes.