Patent ID: 6162997
Filing Date: 2000-12-19
Classification: H01L,H05K

Abstract:
A multilayer circuit board and chip carrier assembly for a chip carrier having a high density array of electrical pads arrayed in a grid pattern that optimizes wiring density, said assembly comprising;a chip carrier having a high density array of electrical pads arrayed in a grid pattern;a multilayer electrically insulating substrate having upper, lower and internal surfaces;a plurality of electrical contacts on said upper surface for connecting to the chip carrier electrical pads, wherein said plurality of electrical contacts form a first set of electrical contacts and a second set of electrical contacts and said first set of electrical contacts and said second set of electrical contacts further form an upper surface grid pattern area, said upper surface grid pattern area correlating to the chip carrier electrical pad grid pattern;a plurality of primary through holes in a primary pattern within said upper surface grid pattern area through said substrate extending from said upper surface to a third set of electrical contacts on said lower surface of said substrate, said third set of contacts electrically connected to said primary through holes and further defining a lower surface grid pattern area, wherein the lower surface grid pattern area is beneath and coextensive with said upper surface grid pattern area, and wherein the average spacing between the lower surface grid pattern area contacts is greater than the spacing between the upper surface grid pattern area contacts;a plurality of secondary through holes in a secondary pattern through said substrate, said secondary pattern located outside said upper and lower surface grid pattern areas, said secondary through holes extending from one surface of said substrate to another surface on said substrate;a fourth set of electrical contacts on said lower surface of said substrate connected to said secondary through holes, said fourth set of electrical contacts located outside the lower surface grid pattern area, wherein the third set of connections and the fourth set of connections together define a dispersal pattern area, said dispersal pattern area larger than the chip carrier electrical pad grid pattern area;wherein the first set of said electrical contacts is connected to said primary through holes and the second set of said electrical contacts is connected to said secondary through holes on a surface of said substrate, wherein each contact of said first set of upper surface electrical contacts is electrically connected to a contact from said third set of lower surface electrical contacts, wherein each contact of said third set of lower surface electrical contacts is directly beneath the contact of said first set of upper surface electrical contacts connected to it; andwherein the secondary through holes are connected to said fourth set of electrical contacts by wiring on one of said upper, lower or internal surfaces of said substrate, thereby electrically connecting each contact of said fourth set of lower surface electrical contacts to a contact from said second set of upper surface electrical contacts, wherein each contact of said fourth set of lower surface electrical contacts is offset and not directly beneath a second set upper surface electrical contact connected to it by the secondary through holes.