Patent ID: 7814276
Filing Date: 2010-10-12
Classification: G06F

Abstract:
1. A data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm; wherein the data cache memory is partitioned into at least a plurality of large cache-size blocks and a plurality of small cache-size blocks, wherein the cache algorithm comprises steps of: (a) determining whether the host writes data larger than or equal to a threshold number of sectors; (b) determining whether a cache hit occurs in the large cache-size blocks; and (c) writing data to the small cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit does not occur in the large cache-size blocks, otherwise writing data to the large cache-size blocks.