Patent ID: 6124818
Filing Date: 2000-09-26
Classification: H03M

Abstract:
A pipelined analog to digital converter (ADC) circuit for converting an analog input signal to a digital output signal having most significant bits (MSBs) and least significant bits (LSBs), said ADC circuit comprising:a first stage coupled to receive said analog input signal comprising:a first CDAC and associated control that convert a portion of said analog input signal corresponding to said (MSBs) from analog to digital; anda first buffer with associated transfer function coupled to said first CDAC for outputting a first stage residue signal corresponding to said LSBs; anda second stage coupled to said first stage to receive said first stage residue signal comprising:a second CDAC and associated control that convert said first stage residue signal to said LSBs; anda second buffer with associated transfer function coupled to said second CDAC, wherein said second buffer has matched transfer function as said first buffer.