Patent ID: 6337589
Filing Date: 2002-01-08
Classification: G11C,H03L

Abstract:
A system for generating an internal clock signal in response to an external clock signal, comprising:a phase adjustment circuit responsive to said external clock signal and said internal clock signal for producing a phase adjustment signal representing a difference between the phase of said external clock signal and the phase of said internal clock signal; a frequency adjustment circuit responsive to said external clock signal and said internal clock signal for producing a frequency adjustment signal representing a difference between the frequency of said external clock signal and the frequency of said internal clock signal; a control value calculator responsive to said phase adjustment signal and said frequency adjustment signal for producing a resulting control signal; and a signal-controlled oscillator responsive to said resulting control signal for producing said internal clock signal at an internal clock frequency deviating in response to said resulting control signal; wherein said frequency adjustment circuit comprises a frequency detector responsive to said external clock signal and said internal clock signal for producing an instantaneous value of a frequency error signal indicating a difference between instantaneous frequencies of the internal clock signal and the external clock signal, and an accumulator coupled to said frequency detector for accumulating instantaneous values of the frequency error signal over a preset time period to produce an accumulated signal indicating an average value of the frequency difference for the preset time period.