Patent ID: 9170914
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. An interface monitoring apparatus for an interface port that connects a peripheral device to an interface chip by at least one first data line comprising: a capacitor arranged between the interface chip and the interface port and configured to capacitively couple the first data line to the interface chip, a first monitoring circuit coupled to the first data line at a node arranged between the capacitor and the interface port and configured to monitor at least one device-end termination of the first data line and provide a first control signal in the event of identifying that a termination for the first data line is not present, a first deactivation circuit that permanently stops data traffic via the first data line of the interface port until the interface monitoring apparatus is reset when the first control signal has been provided by the first monitoring circuit, and a first voltage divider, a second voltage divider and a comparator, wherein 1) the first voltage divider connects between a supply voltage potential and a reference potential and provides, at a first internal node, a reference voltage, 2) the second voltage divider connects between the supply voltage potential and the node of the data line arranged between the capacitor and the interface port and provides, at a second internal node, a voltage level dependent on the output impedance of the at least one first data line, and 3) the comparator compares the reference voltage provided by the first voltage divider with the voltage level provided by the second voltage divider to detect a current flowing through the second voltage divider from the supply voltage potential to the device-end termination to determine the output impedance of the at least one first data line.