Patent ID: 7518243
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A semiconductor device with a multilayer interconnection structure comprising: a semiconductor substrate; a plurality of metal wiring layers provided on the semiconductor substrate and electrically insulated from upper and lower metal wiring layers by an interlayer insulation film; and at least one via penetrating through the interlayer insulation film and connecting a wiring of a first metal wiring layer and a wiring of a second metal wiring layer positioned above the first metal wiring layer, wherein a potential of a predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, wherein a capacitance value between the predetermined wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less, and wherein the predetermined value is 8pF.