Patent ID: 7447290
Filing Date: 2008-11-04
Classification: G11B,H03L

Abstract:
1. A phase-frequency detector for adjusting a target clock signal and an input signal to the same phase comprising: a first logic gate for receiving a first protection signal and a second protection signal, and for outputting a third protection signal; a first flip-flop electrically connected to the first logic gate, the first flip-flop for receiving the third protection signal, and for outputting the third protection signal as a first output signal when triggered by the target clock signal; a second flip-flop electrically connected to the first logic gate, the second flip-flop for receiving the third protection signal, and for outputting the third protection signal as a second output signal when triggered by the input signal; a second logic gate electrically connected to the first flip-flop and the second flip-flop, the second logic gate for receiving the first output signal and the second output signal, and for outputting a fourth protection signal; and a third logic gate electrically connected to the second logic gate, the third logic gate for receiving the third protection signal and the fourth protection signal, and for outputting a fifth protection signal; wherein a level of the fifth protection signal is used to determine whether to compare the phase of the input signal and the phase of the target clock signal.