Patent ID: 7446038
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A method for manufacturing an interlayer interconnect structure of a three-dimensional memory, the method comprising the steps of: providing a substrate comprising a memory array area, a first peripheral interconnect area in a first-direction extension to the memory array area, and a second peripheral interconnect area in a second-direction extension to the memory array area; forming lower electrode lines at a first height within the memory array area of the substrate; forming discrete line patterns at the first height within the first and second peripheral interconnect areas of the substrate; forming a plurality of memory cells at a second height within the memory array area; forming first plugs at the second height within the first and second peripheral interconnect areas and at ends of the lines within the memory array area; forming upper line patterns at a third height within the memory array area; forming discrete line patterns at the third height within the first and second interconnect areas; and forming second plugs at a fourth height within the second peripheral interconnect area.