Patent ID: 8658497
Filing Date: 2014-02-25
Classification: B82Y,H01L

Abstract:
1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising: in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first high-k gate dielectric, a metal select gate, and a first dielectric layer, wherein the metal select gate is on the first high-k dielectric, a top surface of the first dielectric layer is substantially aligned with a top surface of the metal select gate, and the first dielectric layer has a first opening in which the metal select gate is present in the first opening; in a logic region, forming over the semiconductor substrate a second high-k gate dielectric, a metal logic gate, a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the metal logic gate is on the second high-k dielectric, a top surface of the second dielectric layer is substantially aligned with a top surface of the metal logic gate, and the second dielectric layer has a second opening in which the metal logic gate is present in the second opening; forming a hard mask over the NVM region and the logic region; removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region, wherein the forming the hard mask is performed prior to the removing the first dielectric layer; forming a charge storage layer comprising metal nanocrystals over the NVM region including over the metal select gate; forming a metal layer over the charge storage layer; patterning the metal layer to form a metal control gate; and etching the charge storage layer to leave a remaining portion of the storage layer aligned to the metal control gate.