Patent ID: 7518918
Filing Date: 2009-04-14
Classification: G11C

Abstract:
1. An integrated circuit comprising: an embedded memory array having a plurality of first addressable memory locations and a second plurality of adressable memory locations mappable to the first plurality of addressable memory locations; a memory controller capable of accessing the memory array and adapted to detect a defective memory location during functional operation of the integrated circuit; a built-in self test (BIST) element adapted to receive an address corresponding to the defective memory location and generate a plurality of control signals to direct read and write access of and to the memory array, test pattern stimuli data, and address locations to be accessed; and a built-in redundancy analyzer (BIRA) capable of receiving the contents of an address corresponding to the defective memory location, comparing with an expected result from the BIST element and replacing the defective memory location utilizing a redundant memory address from the second plurality of addressable memory locations when a miscompare occurs between a received data and an expected data.