Patent ID: 8031819
Filing Date: 2011-10-04
Classification: H03K,H04L

Abstract:
1. A system for synchronizing an input signal, the system comprising: a first latching device configured to latch an input signal; a second latching device configured to latch an output signal; and a synchronizer transition element interconnected between the first latching device and the second latching device and configured to provide substantial race condition prevention and increased resolving time based on delaying an edge of the input signal without delaying a resolving edge of a metastable condition associated with the input signal, such that the resolving edge does not appear at the second latching device for both resolving to a logic 1 state and a logic 0 state; wherein the synchronizer transition element comprises a channel switching circuit configured to switch between an input channel and a complementary input channel based on a logic state transition of the latched input signal.