Patent ID: 7166828
Filing Date: 2007-01-23
Classification: H01L

Abstract:
1. A solid-state image sensing device comprising: an image sensing region in which unit pixels are arranged in a matrix, each of the unit pixels comprising a photodiode formed in a surface portion of a first-conductivity-type semiconductor substrate, and including a second-conductivity-type first semiconductor layer which generates and stores signal charge by photoelectrically converting incident light, and a first-conductivity-type second semiconductor layer which is grounded, a read transistor which has a drain and source connected between the first semiconductor layer of the photodiode and a detection node, and, when a read signal is supplied to a gate, reads out the signal charge and outputs the readout signal charge to the detection node, an amplifying transistor which has a gate connected to the detection node, and a drain connected to a signal output line, and amplifies the signal charge output to the detection node to output a pixel signal to the signal output line, a reset transistor which has a second-conductivity-type third semiconductor layer connected to the detection node, and a second-conductivity-type fourth semiconductor layer connected to a discharge node, and, when a reset signal is supplied to a gate, removes signal charge present in the detection node to the second-conductivity-type third semiconductor layer, and an address transistor which has a drain connected to a source of the amplifying transistor, and a source connected to a first voltage supply line, and selects an address of the photodiode when an address signal is supplied to a gate; and the signal output line which reads out the pixel signal output from the unit pixel by the amplifying transistor, wherein the first semiconductor layer is formed in a predetermined depth of the surface portion of the semiconductor substrate, the third semiconductor layer is formed in the surface portion of the semiconductor substrate, and at least a portion of the first semiconductor layer and at least a portion of the third semiconductor layer overlap each other, with a predetermined spacing therebetween, along a direction of depth of the semiconductor substrate.