Patent ID: 6625702
Filing Date: 2003-09-23
Classification: G06F

Abstract:
A memory controller, comprising:a) a memory map storing indications of data/strobe ratios which are required to read and write memory modules coupled to said memory controller, said memory map being addressed during read and write cycles of said memory controller; b) subsets of strobe driver circuits, wherein each of said subsets receives addressed indications of data/strobe ratios during said write cycles, and wherein at least one of said subsets generates strobes in response to only a portion of said indications of data/strobe ratios; c) pluralities of strobe receiver circuits and data receiver circuits; and d) a number of multiplexers associating at least some of said strobe receiver circuits with at least some of said data receiver circuits, wherein each of said multiplexers receives addressed indications of data/strobe ratios during said read cycles, and wherein said multiplexers associate different ones of said strobe receiver circuits with said data receiver circuits in response to different indications of data/strobe ratios.