Patent ID: 6192491
Filing Date: 2001-02-20
Classification: G06F,H04L

Abstract:
A processor comprising:a first input receiving a first input data, a second input receiving a second input data, a third input receiving a third input data and a fourth input receiving a CRC instruction;a logic unit coupled to the first input, the second input, the third input and the fourth input, the logic unit including activatible CRC circuitry which is activated upon receipt of the CRC instruction and which performs a calculation of a CRC value based upon:I) the polynomial defined in the first input data;ii) the current state of the CRC calculation stored in the second input data; andiii) a third input data containing a portion of a message upon which to calculate a CRC;an output coupled to the logic unit, the output outputting the CRC value in a predefined location; andwherein the processor can be programmed to process one of many different instructions, including at least one instruction from a group comprising: a zero stuffing instruction, a zero unstuffing instruction, a partial subtraction and conditional move instruction, a partial compare and conditional move instruction and a multiple compare instruction.