Patent ID: 6279070
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A multi-step pulse generating circuit, comprising:loop counter for counting the number of repeating erase or program operation based on an output of a loop reset circuit and generating a multi-step pulse erase mode signal, the loop counter being reset by a loop reset signal when a suspense command is input during a multi-step pulse erase operation, the loop counter not being reset when the suspense command is input during a normal erase operation;timer for generating a pulse signal of appropriate intervals for respective erase modes in response to said multi-step pulse erase mode signal of said loop counter;multi-step pulse generating block for outputting a multi-step erase signal, and either a multi-step pulse erase signal or a normal erase signal, based on the multi-step pulse erase mode signal of said loop counter, said pulse signal output from said timer, an erase mode signal, and an erase reset signal; andpulse generating number counter for counting the number of toggling said pulse signal output from said timer, for generating an erase reset signal to reset said multi-step pulse generating block when a given number of counting is reached, and for storing the counting number at the time when a suspense command is input if said suspense command is input during said multi-step pulse erase mode, and for resuming said multi-step erase mode from the time when the suspense command is stored, said pulse generating number counter comprising a plurality of logic gates and a plurality of flip-flops.