Patent ID: 6064620
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A memory device for storing data therein, said memory device comprising:a first memory array having bit lines having a first plurality of memory locations;at least a second memory array also having bit lines having at least a second plurality of memory locations;a decoder coupled to said first memory array through a first memory array switch and said at least second memory array through an at least second memory array switch and coupled to receive indications of access requests to access selected memory locations of the first plurality of memory locations and the second plurality of memory locations, said decoder for selectively accessing the memory locations identified by the indications of the access requests; andbiasing circuitry coupled to said first memory array, to said at least second memory array and to said decoder, said biasing circuitry coupled to said decoder by input lines, said biasing circuitry for selectively biasing bit lines of all but at least one selected memory array of said first memory array and said at least second memory array and for selectively biasing input lines of said decoder to selectively turn off said first memory array switch and said at least second memory array switch, the at least one selected memory array containing the selected memory locations identified in the indications of the access requests received by said decoder, the at least one selected memory array remaining active responsive to the selective biasing of the at least input lines and the bit lines thereof, and the selected memory locations thereof accessible, each of said first memory array and said at least second memory array biased by said biasing circuitry being inactive and the memory locations thereof inaccessible.