Patent ID: 6194283
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method for forming a trench isolation region, comprising:etching an isolation trench into a semiconductor substrate such that a base of the trench is spaced below a surface of the substrate;depositing a spacer layer across the semiconductor substrate and into the trench, wherein the spacer layer comprises silicon nitride;isotropically etching the spacer layer to form a pair of spacer structures laterally adjacent opposed sidewall surfaces of the isolation trench such that exposed lateral surfaces of said pair of spacer structures are substantially angled such that the width of the spacers structure at the base of the isolation trench is greater than a width of the spacers structure proximate the surface of the substrate, and wherein the width of the spacers structure at a position between the base of the trench and the surface of the substrate is less than a width of the spacers structure at the base;filling the isolation trench with an isolation dielectric, wherein the spacer structures and the isolation dielectric together fill the isolation trench such that the isolation trench is substantially free of a void.