Patent ID: 7049868
Filing Date: 2006-05-23
Classification: G06F,H03L

Abstract:
1. A method of compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising steps of: (a) comparing a rising edge of a first signal associated with a first signal level with a rising edge of a second signal associated with a second signal level; (b) generating a rising edge compensation signal indicative of a phase difference between the rising edge of the first signal and the rising edge of the second signal; (c) comparing a falling edge of the first signal with a falling edge of the second signal; (d) generating a falling edge compensation signal indicative of a phase difference between the falling edge of the first signal and the falling edge of the second signal; (e) delaying the rising edge of the first signal in response to the rising edge compensation signal; and (f) delaying the falling edge of the first signal in response to the falling edge compensation signal; wherein delaying steps (e) comprises buffering the first signal with a buffer transistor and adjusting current flow through the buffer transistor, thereby controlling delay of the rising edge of the first signal through the buffer transistor.