Patent ID: 6870424
Filing Date: 2005-03-22
Classification: H03F

Abstract:
1. A low voltage differential amplifier architecture with differential input and output signals, comprising, a first stage comprising a first set of common source connected first identical NMOS transistors and parallel first identical PMOS transistors with their respective gates connected to the differential input signal, a first current source connected to the sources of the first NMOS transistors and a second current source connected to the sources of the first PMOS transistors, the drains of the first NMOS transistors are connected to sources of a set of second identical PMOS transistors, the drains of the first PMOS transistors are connected to sources of a set of second identical NMOS transistors, wherein the second identical PMOS and the second identical NMOS transistors are in a second stage, wherein each of the second identical NMOS transistors and each of the second identical PMOS transistors are symmetrical to each other, and wherein the drain of one of the second PMOS transistors is connected to the drain of one of the set of second identical NMOS transistors, thereby forming a first current path, and wherein the drain of the other of the second PMOS transistors is connected to the drain of the other of the set of second identical NMOS transistors, thereby forming a second current path, wherein the voltage signal between the commonly connected drains defines an intermediate differential output signal, a first biasing tree including a first tree PMOS transistor and a first tree NMOS transistor, with drains and gates connected to each other, the source of the first tree PMOS connected to the source of the PMOS in the second current path, wherein the first tree PMOS and the PMOS in the first current path formed a first current mirror, and the source of the first tree NMOS connected to the source of the NMOS in the second current path, wherein the first tree NMOS and the NMOS in the first current path form a second current mirror, a second biasing tree including a second tree PMOS transistor and a second tree NMOS transistor, with drains and gates connected to each other, the source of the second tree PMOS connected to the source of the PMOS in the first current path, wherein the second tree PMOS and the PMOS in the second current path form a third current mirror, and the source of the second tree NMOS connected to the source of the NMOS in the first current path, wherein the second tree NMOS and the NMOS in the second current path form a fourth current mirror, wherein all the gates of the PMOS and NMOS transistors in the first and the second current paths and in the first and second biasing trees all are connected together, a third current source connected to the source of the PMOS transistors in the first current path, a fourth current source connected to the source of the PMOS transistors in the second current path, wherein the third current source and the fourth current source are equal to each other and each is of a higher value than the second current source, a fifth current source connected to the sources of the NMOS transistors in the first current path, a sixth current source connected to the sources of the NMOS transistors in the second current path, wherein the fifth current source and the sixth current source are equal to each other and each is of a higher value than the first current source, a third differential stage with a differential input connected to the intermediate differential output, and the third differential stage providing a differential output.