Patent ID: 9076672
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; an NMOS gate disposed over the substrate, wherein the NMOS gate includes: a first high-k gate dielectric, a capping layer disposed over the first high-k gate dielectric, and an N-type work function metal disposed over the capping layer, and a polysilicon gate electrode disposed over the N-type work function metal, wherein the capping layer and the N-type work function metal are configured to collectively tune a work function of the NMOS gate; and a PMOS gate disposed over the substrate and adjacent to the NMOS gate, wherein the PMOS gate includes: a second high-k gate dielectric, and a P-type metal gate electrode disposed over the second high-k gate dielectric, wherein a portion of the P-type metal gate electrode is configured to tune a work function of the PMOS gate, wherein the P-type metal gate electrode includes: a first metal contact physically contacting the blocking layer and the fill metal.