Patent ID: 6850460
Filing Date: 2005-02-01
Classification: G11C

Abstract:
1. A high performance SRAM array local clock generator comprising in combination: a forward delay path extending from a global clock input to a local clock output in order to establish a leading edge of said local clock signal; at least one additional delay element set that can be inserted in said forward delay path in response to scan bits in order to delay the propagation of said global clock signal along said forward delay path; a trailing delay path extending from said global clock input to said local clock output in order to establish a trailing edge of said local clock signal; at least another additional delay element set that can be inserted in said trailing delay path in response to scan bits in order to delay the propagation of said global clock signal along said trailing delay path; a connection between said forward delay path and said trailing delay path that inhibits the introduction of said global clock signal into said trailing delay path by an amount that is a function of the delay introduced by said forward delay path.