Patent ID: 8189784
Filing Date: 2012-05-29
Classification: H03M,H04L,Y04S

Abstract:
1. A communication system comprising: an encoding device including an encrypting module adapted for encrypting an original signal into an encrypted signal, and an error correction encoding module coupled to said encrypting module for receiving the encrypted signal therefrom, and generating an output signal by performing error correction encoding on the encrypted signal; and a decoding device including an error correction decoding module for receiving an input signal via a transmission channel, the input signal being a result of the output signal combined with noise attributed to the transmission channel, said error correction decoding module generating a recovery signal from the input signal by performing error correction decoding on the input signal, and a decrypting module coupled to said error correction decoding module for receiving the recovery signal therefrom, and generating a decrypted signal that corresponds to the original signal by decrypting a portion of the recovery signal, wherein said encrypting module of said encoding device is adapted for receiving a plurality of bits of an encryption key in sequence from a most significant bit to a least significant bit, and encrypts the original signal into the encrypted signal according to a public key and the encryption key thus received, said encrypting module including: a computing unit adapted for receiving the original signal, the public key, and a multiplexer output signal; a controller coupled electrically to said computing unit, and adapted for receiving the bits of the encryption key in sequence from the most significant bit to the least significant bit; and a first multiplexer coupled electrically to said controller and said computing unit, adapted for receiving the original signal and a modulus signal, and controlled by said controller to output the multiplexer output signal; wherein, for each bit received by said controller and determined by said controller to be a bit other than the most significant bit, said controller controls said computing unit to perform modulus computation processing for generating the modulus signal with reference to the original signal, the public key, and the multiplexer output signal; wherein, when the bit received is a second most significant bit of the encryption key, said controller controls said first multiplexer to output one of the original signal and a predetermined signal as the multiplexer output signal according to a value of the most significant bit of the encryption key, and controls said computing unit to perform the modulus computation processing according to a first modulus computation for generating the modulus signal with reference to the multiplexer output signal and the public key; wherein, when the bit received is the second most significant bit and when a value of the second most significant bit matches a predetermined value, said controller further controls said first multiplexer to output the modulus signal generated according to the first modulus computation as the multiplexer output signal, and further controls said computing unit to perform the modulus computation processing according to a second modulus computation for generating the modulus signal with reference to the original signal, the public key, and the multiplexer output signal; wherein, when the bit received is a bit other than the most significant bit and the second most significant bit of the encryption key, said controller controls said first multiplexer to output the modulus signal as the multiplexer output signal, controls said computing unit to perform the modulus computation processing according to the first modulus computation with reference to the multiplexer output signal and the public key, and further controls said computing unit to perform the modulus computation processing according to the second modulus computation for generating the modulus signal with reference to the original signal, the public key, and the multiplexer output signal when a value of the bit matches the predetermined value and after the modulus computation processing according to the first modulus computation is completed; wherein, upon determining that the bit received is the least significant bit of the encryption key, said controller enables said computing unit to output the modulus signal as the encrypted signal upon completion of the modulus computation processing according to the first modulus computation when a value of the least significant bit does not match the predetermined value, and upon completion of the modulus computation processing according to the second modulus computation when the value of the least significant bit matches the predetermined value.