Patent ID: 6910152
Filing Date: 2005-06-21
Classification: G11C

Abstract:
1. A semiconductor memory comprising: an array including a redundant row; a first set of nonvolatile elements for storing at least a portion of an address of a defective cell of said array; data path circuitry coupled to said array for writing data thereto and reading data therefrom; a second set of nonvolatile elements for storing a block repair configuration; routing circuitry coupled to said second set of nonvolatile elements capable of being configured by a stored block repair configuration to output a selected ratio of received row address bits to received column address bits; and comparison circuitry coupled to said first set of nonvolatile elements, said data path circuitry, and said routing circuitry for comparing row and column address bits output by said routing circuitry with said stored at least a portion of said defective cell address and, when a match occurs, for implementing a block repair of said defective cell by activating said redundant row and directing said data path circuitry to write data to or read data from said activated redundant row.