Patent ID: 7222209
Filing Date: 2007-05-22
Classification: G06F

Abstract:
1. A bus system for use with addressable memory comprising: a master device; a global bus having a first end at the master device and a second end; a plurality of memory subsystems coupled to the global bus, each memory subsystem comprising: a local bus having a first end coupled to the global bus and a second end,; a local bus terminator coupled to the local bus at the second end; one or more slave devices including a last slave device at a furthest distance from the master device global bus, each slave device including an active terminator coupled to the local bus, wherein the active terminator of the last slave device is enabled; and wherein a first portion of a respective local bus, extending from first end of the local bus to a point on the local bus to which a first device is coupled, has a first characteristic impedance Z