Patent ID: 9018690
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. A memory device, comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween; a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region; a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region; and a stressor region of embedded silicon carbide formed in the substrate directly under the second portion of the channel region and the second gate, wherein no stressor region of embedded silicon carbide is formed directly under the first portion of the channel region.