Patent ID: 9042156
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array configured by arranging a plurality of memory cells, each of which includes a variable resistance element for storing information based on a variation in electrical resistance, in a row direction and a column direction, respectively, such that one ends of the memory cells of the same column are connected to a common first control line, and the other ends of the memory cells of at least the same row or the same column are connected to a common second control line; a selection circuit for selecting the memory cell to be written or read; a writing circuit for changing an electrical resistance of the variable resistance element of the selected memory cell; and a reading circuit for reading a resistance state of the variable resistance element of the selected memory cell, wherein the writing circuit is configured to execute each of a setting action in which the electrical resistance of the variable resistance element is converted to a low resistance by applying an electric current from the one end side to the other end side of the memory cell via the variable resistance element, and a resetting action in which the electrical resistance of the variable resistance element is converted to a high resistance by applying an electric current from the other end side to the one end side of the memory cell via the variable resistance element, and the reading circuit is configured to execute each of a first reading action in which the resistance state of the variable resistance element is read by applying an electric current from the one end side to the other end side of the memory cell via the variable resistance element, and a second reading action in which the resistance state of the variable resistance element is read by applying an electric current from the other end side to the one end side of the memory cell via the variable resistance element.