Patent ID: 6228684
Filing Date: 2001-05-08
Classification: G01R,H01L

Abstract:
A method of manufacturing a wafer-level package comprising the steps of:a) preparing a semiconductor wafer having at least one semiconductor chip circuit forming region each provided with a semiconductor chip circuit and a plurality of chip terminals, at least one of said chip terminals being a test chip terminal and at least one being a non-test chip terminal;b) forming a redistribution layer includingan insulating film having through holes on the semiconductor wafer andan electrically conductive film formed on said insulating film, said electrically conductive film being redistribution traces having a predetermined pattern;c) forming external connection terminals and at least one testing member on said redistribution layer, said testing member being provided at an outer region of said semiconductor chip circuit forming region and connected to said test chip terminal through said redistribution traces; andd) testing said semiconductor chip circuit using said testing member.