Patent ID: 7683490
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and a third-level wiring layer, the second-level wiring layer being between the first-level wiring layer and the third-level wiring layer; a first interconnection line formed as the first-level wiring layer and extending in a first direction; a second interconnection line formed as the second-level wiring layer and extending to cross over the first interconnection line, the second interconnection line thereby having a first portion and a second portion which are located respectively on first and second sides opposite to each other with respect to the first interconnection line, the first and second portions being distant form each other in the first direction; and a third interconnection line formed as the third-level wiring layer and extending to cross over the first interconnection line, the third interconnection line thereby having a third portion and a fourth portion which are located respectively on the first and second sides with respect to the first interconnection line: the second portion of the second interconnection line being connected through a via to the third portion of the third interconnection line on the second side with respect to the first interconnection line.