Patent ID: 6525978
Filing Date: 2003-02-25
Classification: G11C

Abstract:
A circuit configuration for evaluating an information content of a memory cell, the circuit configuration comprising:a line connected to the memory cell; an evaluation unit; a first switch-connected to said line; a second switch connected to said line; at least one current mirror circuit electrically connected to said evaluation unit through said first switch and said second switch, said current mirror circuit asymmetrically measuring at least one of a first measured value and a second measured value of the memory cell, said current mirror circuit having a first transistor with a gate terminal and connected to said line through said first switch, said current mirror circuit further having a second transistor with a gate terminal and connected to said line through said second switch; a third switch connected between said gate terminal of said first transistor and said gate terminal of said second transistor; and a capacitance connected to said gate terminal of said second transistor.