Patent ID: 6927969
Filing Date: 2005-08-09
Classification: H01L

Abstract:
1. Circuit arrangement comprising: first chips, which each contain a transistor and are arranged along a first axis on a first metallic body in a side-by-side and interspaced manner and are electrically connected to the first body, second chips, which each contain a transistor and are arranged along a second axis parallel to the first axis on a second metallic body in a side-by-side and interspaced manner and are electrically connected to the second body, wherein the second chips, with regard to a third axis perpendicular to the first axis, each being arranged opposite an area of the first body, which is located between adjacent first chips, wherein the second chips each being electrically connected to the corresponding opposite area of the first body via at least one bonding connection, wherein the first chips, with regard to the third axis each being arranged opposite an area of the second body, which is located between adjacent second chips, a third metallic body being arranged on the second body so that it is electrically insulated and having projections, each of which being arranged on one of the areas of the second body, and wherein the first chips each being electrically connected to the opposite projection of the third body via at least one bonding connection.