Patent ID: 6201817
Filing Date: 2001-03-13
Classification: H04L

Abstract:
A system providing an interface between a serial communications link and a processor, comprising:a) a transmit register and a receive register, said transmit register and receive register respectively transmitting and receiving data to and from said serial communications link;b) a system memory comprising a transmit buffer and a receive buffer, said system memory coupled to said processor;c) a receive register command processor, coupled to said receive register, for detecting the presence of a control character or characters in said incoming data stream associated with communication control condition in said stream of data from said serial communications link and identifying where in said data stream such control character or characters occurred; andd) a control state machine coupled to said system memory and said receive command processor, said control state machine responsive to said receive register command processor to coordinate the transfer of blocks of data in said incoming data stream from said receive register to said receive buffer in said system memory, said control state machine further comprising a means for monitoring the status of said receive buffer;1) wherein said control state machine issues a first signal to said processor to initiate retrieval of data in said receive buffer and processing of said data in said receive buffer when said receive buffer is filled to a predetermined amount, and2) wherein said control state machine issues another signal to said processor indicating the location in said receive buffer where said control character or characters associated with said communication control condition is located,whereby the efficiency of transfer of data from said serial communication link and said processor may be improved.