Patent ID: 6018755
Filing Date: 2000-01-25
Classification: H03H

Abstract:
A method for implementing an N-tap filter on a processor, the method comprising the steps of:loading a plurality, L.sub.2, of input registers with successive ones of a sequence of input values;repeating N/L.sub.2 times the step of:repeating L.sub.1 times L.sub.1 .gtoreq.L.sub.2) the steps of:accumulating in a respective one of a plurality, L.sub.1, of output registers, an inner product of a partial vector of filter coefficients represented in a plurality, L.sub.2, of coefficient registers and a partial vector of the input values represented in the L.sub.2 input registers; andloading one of the L.sub.2 input registers with a next successive one of the sequence of input values, thereby replacing an earliest one of the sequence of input values with the next successive one of the sequence of input values; andstoring result values accumulated in the L.sub.1 output registers.