Patent ID: 8987078
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of forming a semiconductor device comprising: forming a gate structure on a channel portion of a semiconductor substrate, wherein a source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate; forming an interlevel dielectric layer over the gate structure; forming an opening to at least one of the source region and the drain region through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region, wherein said forming of the opening comprises forming an etch mask over the dielectric layer including initial openings having a first width, etching the interlevel dielectric layer with an anisotropic etch that is selective to the exposed portion of the semiconductor substrate, and increasing the width of the initial openings to a second width to provide the openings to at least one of the source region and the drain region; forming a metal semiconductor alloy contact on the exposed surface of the semiconductor substrate; forming at least one dielectric sidewall spacer on sidewalls of the opening overlying a portion of the metal semiconductor alloy region; and forming an interconnect within the opening in direct contact with the metal semiconductor alloy contact.