Patent ID: 6504745
Filing Date: 2003-01-07
Classification: G11C,H01L

Abstract:
A method for organizing M single-bit erasable programmable read-only memory (EPROM) cells into N blocks, where M is a multiplication-product of N by I by J. and N, I and J are positive integers, the method comprising steps of:(a) dividing said M single-bit EPROM memory cells into N blocks where each of said block includes {J(j)Ã—I} single-bit memory cells, and where j=1, 2, 3, . . . , N, and said positive integer I representing a bit length of a stored data; (b) arranging said single-bit EPROM memory cells in each of said blocks into a J(j)-by-I two dimensional array and by connecting every I single EPROM memory cells with a first level bit line in a first bit-line direction and every J(j) single-bit EPROM memory cells by a first level word line wherein each said first level word lines and said first level bit lines intersect at one of said single-bit EPROM memory cells; (c) connecting each of said I first level bit lines in each of said blocks to a corresponding multiple-block first level bit-lines, i. e. , multiple-block bit-line-i where i=1, 2, 3, . . . I, wherein said multiple-block first-level bit lines being arranged in a second bit-line direction different from said first-bit line direction and each being connected to a corresponding first level sense-amplifier-i where i32 1, 2, 3, . . . I; and (d) applying a block select signal to activate one of said J(j) first level word lines in one of said blocks, i. e. , block-n where n is a positive integer ranging from 1 to N, and employing said I sense amplifiers for detecting memory-cell signals from each of said first level I bit lines of said block n for reading data therefrom whereby said N blocks sharing said I sense amplifiers.