Patent ID: 7738259
Filing Date: 2010-06-15
Classification: H05K,Y02P

Abstract:
1. A printed wiring board (PWB) for mounting a high performance integrated circuit, comprising: on a top side of said PWB, a modified via array with BGA columns and BGA row of ball connection pads; a modified vias array of plated through hole (PTH) vias, with each via column Col(n) arranged between two respective BGA columns c(n) and c(n+1) and each via row R(k) arranged between two respective BGA rows r(k) and r(k−1), wherein 2m vias of said via column Col(i) placed in successive via rows R(j) to R(j+2m−1) of said modified vias array are depopulated to obtain a free space on the back side of said PWB, wherein 2m corresponding vias in a via column Col(i+1) adjacent to said via column Col(i) and placed in said successive via rows R(j) to R(j+2m−1) of said vias array are shared vias, wherein n≧1, k≧2, 2≦i<n and j<k, and wherein a first shared via in said via column Col(i+1) and said via row R(j) provides a power contact to a first associated ball contact pad in said via column c(i+1) and said via row r(j) and to a second associated ball contact pad in said via column c(i+2) and said via row r(j).