Patent ID: 6643727
Filing Date: 2003-11-04
Classification: H04L

Abstract:
A logically partitioned data process system in which I/O bus errors are isolated, comprising:a system bus; a processing unit coupled to the system bus; a memory unit coupled to the system bus; a host bridge coupled to the system bus; a first and a second terminal bridge coupled to the host bridge through a first bus; a first input/output adapter coupled to the first terminal bridge through a second bus, a second input/output adapter coupled to the second terminal bridge through a third bus; each terminal bridge prevents errors from each of the input/output adapters from affecting other components within the data processing system; wherein each of the first and second input/output adapters is assigned to one of a plurality of logical partitions within the data processing system; and wherein the first terminal bridge, responsive to receipt of a first error type from the first input/output adapter of a type which can be reported directly to the input/output adapter for handling, does not place the first input/output adapter into a stopped state and does not prevent the input/output adapter from responding to Load and Store operations or performing direct memory access operations.