Patent ID: 6499135
Filing Date: 2002-12-24
Classification: G06F

Abstract:
A method for designing grounded fill in an integrated circuit, said integrated circuit having multiple metal layers, the method employing a computer-aided design (CAD) system having a fixed amount of memory, the method comprising:(a) finding the eligible fill areas for each metal layer; (b) storing the eligible fill area data for each metal layer in an overflow memory; (c) finding ground contact areas for each metal layer; (d) storing the ground contact area data for each metal layer in an overflow memory; (e) temporarily storing the eligible fill area data for a selected metal layer and the ground contact area data for the metal layers adjacent to said selected metal layer in said fixed amount of memory; (f) fitting a fill pattern to an eligible fill area in said selected metal layer, said fill pattern composed of at least one element; (g) checking said adjacent metal layers for a ground contact for grounding said element of the fill pattern; (h) locating a conductive via between said element of the fill pattern and a ground contact in an adjacent layer; and (i) repeating steps (e) through (h) for each metal layer.