Patent ID: 8311222
Filing Date: 2012-11-13
Classification: H04L

Abstract:
1. A system comprising a module, and the module comprising: a linear feedback shift register (LFSR) to output a first pseudo-random sequence of digital values based on a first key value stored in a first key register; and a permutator circuit to receive successive groups of bits and receive the first pseudo-random sequence of digital values, and, for each group of said successive groups, to: the bit permutation is a permutation on N elements; each group of said successive groups is N bits in length; each of the digital values of said first pseudo-random sequence is M bits in length; M is greater than or equal to log the LFSR is to generate a second pseudo-random sequence of internal values each of length L bits; L is larger than M; each digital value of said first pseudo-random sequence is obtained by taking M bits from a respective one of the internal values of the second pseudo-random sequence; the LSFR is to generate the second pseudo-random sequence of internal values so that the second pseudo-random sequence of internal values is periodic with period 2