Patent ID: 7301202
Filing Date: 2007-11-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate of a first conduction type serving as a common drain of a plurality of power MISFET cells; a middle semiconductor layer of said first conduction type formed on said semiconductor substrate; a plurality of pillar semiconductor regions of said first conduction type formed into strips on said middle semiconductor layer, and a plurality of pillar semiconductor regions of a second conduction type formed into strips on said middle semiconductor layer, each having both sides sandwiched between said pillar semiconductor regions of said first conduction type; a source diffusion layer of said first conduction type formed above said pillar semiconductor region of said second conduction type; a gate insulator film formed over a region sandwiched between said source diffusion layer and said pillar semiconductor region of said first conduction type; a gate electrode formed on said gate insulator film, wherein the middle semiconductor layer has a lower impurity concentration than that of said semiconductor substrate, and has a higher impurity concentration than those of said pillar semiconductor regions of said first conduction type.