Patent ID: 7999708
Filing Date: 2011-08-16
Classification: G06F,H03L,H04B,H04J,H04L

Abstract:
1. A time-interleaved analog-to-digital converter (ADC) comprising: a plurality of ADC units, each ADC unit configured to sample an analog input signal according to a respective clock signal and generate a digital output signal; a multiplexor coupled to receive the digital output signals from respective ones of the plurality of ADC units, wherein the multiplexor is configured to selectively output each of the respective digital output signals from the ADC units in a sequence; a control circuit configured to receive a digital signal indicative of a timing mismatch between at least two of the respective digital output signals from the ADC units and further configured to generate an analog control signal as a function of the timing mismatch; and a clock generator configured to generate the respective clock signals for the ADC units and further configured to receive the analog control signal and adjust at least one of the respective clock signals based, at least in part, on the analog control signal to reduce the timing mismatch.