Patent ID: 8095742
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A microcomputer comprising: a first CPU capable of processing a predetermined task; a first bus coupled with the first CPU; a first memory accessed by the first CPU through the first bus and used as a local memory of the first CPU; a second CPU capable of processing a predetermined task; a second bus coupled with the second CPU; and a second memory accessed by the second CPU through the second bus and used as a local memory of the second CPU, wherein the first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding thereto, wherein the microprocessor further comprises an address translation circuit configured to translate an address output from the second CPU so that access to the first memory by the task becomes access to the second memory when a task so programmed that the task has a data area in the first memory is transferred to the second memory and executed by the second CPU, and wherein the address translation circuit includes