Patent ID: 6113648
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method for protecting a first transistor in a gate array from gate charging, said gate array implementing a logic function, said method comprising:a) creating a base array having at least one free transistor and said first transistor, said free transistor not employed to implement said logic function; said first transistor and free transistor each having a gate electrode, said free transistor having a drain electrode;b) forming contacts in the gate electrode of the free transistor, the gate electrode and the drain electrode of the target transistor; andc) coupling said gate electrode of said first transistor to the drain electrode of said free transistor and connecting the gate electrode of the free transistor to a first reference voltage to turn the free transistor off wherein the free transistor is at least one of a NMOS transistor and a PMOS transistor.