Patent ID: 6791363
Filing Date: 2004-09-14
Classification: G06F,H03K

Abstract:
An apparatus comprising:first timing circuitry; at least one stage of logic circuitry; and second timing circuitry, wherein the first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry, the second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry, and the edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.