Patent ID: 6931562
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. A method of transferring data from circuitry disposed in a higher frequency clock domain to circuitry disposed in a lower frequency clock domain, said higher frequency clock domain operating with a first clock signal and said lower frequency clock domain operating with a second clock signal, comprising: latching said data in a first latch to generate a first latched data output, said first latch operating in response to a first modified clock signal that is synthesized based on a plurality of intermediary clock signals that are generated at least in part from said first clock signal; providing said first latched data output to a second latch disposed in said lower frequency clock domain, wherein said second latch is gated by a second modified clock signal synthesized at least in part from said second clock signal, said second latch operating to generate a second latched data output; and providing said second latched data output to a register clocked by said second clock signal for generating a synchronized data output operable to be supplied to said circuitry disposed in said lower frequency clock domain.