Patent ID: 8971090
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of first lines disposed on a substrate; a plurality of second lines disposed intersecting the first lines; a memory cell array including memory cells, each of the memory cells disposed at each of intersections of the first lines and the second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell disposed at the intersection of the selected first line and the selected second line is applied with a first potential difference required in an operation of the selected memory cell, the control circuit being configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation and in a case there are a plurality of the selected memory cells of which resistance state of their respective variable resistors is not changed after a certain application of the voltage to the selected memory cells, the selected memory cells to which the first potential difference was applied simultaneously in the certain application of the voltage are divided into a plurality of groups to which the first potential difference can be applied simultaneously next after the certain application of the voltage.