Patent ID: 6253312
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A microprocessor for executing a load macro instruction, the load macro instruction directing the microprocessor to load two single-precision operands into two floating point registers, the microprocessor comprising:translation logic, configured to receive the load macro instruction, the load macro instruction prescribing an address, and to decode the load macro instruction into a double load micro instruction, wherein said double load micro instruction directs the microprocessor to retrieve the two single-precision operands from said address and to load the two single-precision operands into the two floating point registers;data logic, coupled to said translation logic, configured to receive and execute said double load micro instruction, and to retrieve the two single-precision operands from said address; andwrite back logic, coupled to said data logic, configured to load the two single-precision operands into the two floating point registers during a single write cycle.