Patent ID: 6888246
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first interconnect and a second interconnect over a semiconductor device substrate; a passivation layer over the first interconnect and the second interconnect and laterally adjacent the first interconnect and the second interconnect; openings through the passivation layer, wherein a first opening exposes a portion of the first interconnect and a second opening exposes a portion of the second interconnect; a stress buffer feature only over all portions of the passivation layer that are laterally adjacent the first interconnect and the second interconnect; a conductive layer overlying all of the first interconnect, the stress buffer feature and the second interconnect, the continuous conductive layer electrically connecting the first interconnect and the second interconnect; a continuous conductive structure over all of the conductive layer, wherein the continuous conductive structure is electrically coupled to the first interconnect through the first opening and the second interconnect through the second opening; and a wirebond connected to an exposed surface of the continuous conductive structure for making electrical contact to the semiconductor device.