Patent ID: 6825525
Filing Date: 2004-11-30
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a first transistor including a first source region, a first drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the first source region and the first drain region, and a first gate electrode for controlling potential of the first channel region; and a second transistor including a second source region, a second drain region, a second channel region of a semiconductor material connecting the second source region and the second drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity, wherein the second source region of the second transistor is connected to a source line, one end of the first source region or the first drain region of the first transistor is connected to the charge storage region of the second transistor, and the other end of the first source region or the first drain region of the first transistor is connected to a date line, wherein the first channel region is formed on an insulating film, said first channel region being on a level corresponding to upper surfaces of the first source region and the first drain region of the first transistor, and wherein said first gate electrode extends over said first channel region and over the upper surfaces of the first source region and the first drain region of the first transistor.