Patent ID: 6614711
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A decoder for addressing a non-volatile memory device, comprising:a row decoder having a NAND gate that receives input signals and produces a processed signal, the row decoder further having a first n-channel transistor having a gate receiving a multiplexed signal, a source receiving the processed signal, and a drain that outputs a decoded signal when the multiplexed signal is at a high level, and a second n-channel transistor having a gate receiving the inverse of the multiplexed signal and a source coupled to the drain of the first n-channel transistor to pull the decoded signal to a voltage supply when the multiplexed signal is at a low level; a driver that receives the decoded signal to drive a word line; a limiter that couples the word line to a negative voltage supply, the limiter limiting the current supplied to the word line by the negative voltage supply so as to inhibit a flow of charge from the negative voltage supply; and a transfer mechanism coupled to the driver and the limiter for decoupling the driver from the word line to enable the negative voltage supply to charge the word line.