Patent ID: 8736325
Filing Date: 2014-05-27
Classification: H03L

Abstract:
1. A system for wide frequency range clock generation, comprising: a phase lock loop (PLL) configured to generate a signal having a frequency; at least one fractional-N divider, wherein a first one of the at least one fractional-N divider is coupled to the PLL, and the at least one fractional-N divider is configured to divide the frequency of the signal; and a multiplexer, coupled to the PLL and the at least one fractional-N divider, configured to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal; wherein the at least one fractional-N divider comprises a divide-by-1/α divider; and wherein α is equal to (f