Patent ID: 7825495
Filing Date: 2010-11-02
Classification: H01L

Abstract:
1. A semiconductor chip structure comprising: a semiconductor chip; a first insulation layer on the semiconductor chip, the first insulation layer having a plurality of first grooves, which have an upper width and a lower width greater than the upper width, at an upper surface portion of the first insulation layer; a redistribution layer partially on the first insulation layer, the redistribution layer having a plurality of first protrusions, which have an upper width and a lower width less than the upper width, at a lower surface portion of the redistribution layer to be interlocked with the plurality of first grooves; a second insulation layer on the redistribution layer and the first insulation layer, the second insulation layer having a plurality of second protrusions, which have an upper width and a lower width less than the upper width, at a lower surface portion of the second insulation layer to be interlocked with the plurality of first grooves, and a plurality of second grooves, which have an upper width and a lower width greater than the upper width at an upper surface portion of the second insulation layer; and an adhesive layer on the second insulation layer, the adhesive layer having a plurality of third protrusions, which have an upper width and a lower width less than the upper width, interlocked with the plurality of second grooves.