Patent ID: 8181144
Filing Date: 2012-05-15
Classification: G06F

Abstract:
1. A computer-implemented method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of: performing cell library timing characterization for the at least one cell in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively, the first and second temperatures corresponding to first and second process, voltage and temperature (PVT) corners, respectively, in the cell library; for each instance of the at least one cell in the circuit, determining at least one of a third temperature at which cell delay is maximum and a fourth temperature at which cell delay is minimum, the third and fourth temperatures being between the first and second temperatures; performing cell library timing characterization for the at least one cell in the circuit using at least one of the third and fourth temperatures; calculating a cell delay for the at least one cell, the cell delay calculation being a function of at least one of the third and fourth temperatures for each instance of the at least one cell in the circuit; and incorporating the cell delay calculation into the timing characterization for the at least one cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of the timing characterization, wherein the steps are performed at least in part by a processor.