Patent ID: 8614435
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A fabrication process for a nanoelectronic device, comprising: depositing graphene as the channel material on a substrate to form a channel, wherein the substrate is selected from silicon carbide, silicon dioxide, aluminum oxide, or a combination thereof; depositing a source metal contact and a drain metal contact on the channel material, wherein the source metal contact and the drain metal contact are on opposing ends of the channel material; patterning the graphene by: depositing a layer of polyhydroxystyrene derivative on top of and touching the channel material, on top of and touching the source metal contact, and on top of and touching the drain metal contact; causing the layer of polyhydroxystyrene derivative previously deposited to remain on top of and touching each of the channel material, the source metal contact, and the drain metal contact throughout completion of the nanoelectronic device; depositing a top gate oxide on the polyhydroxystyrene derivative; and depositing a top gate metal on the top gate oxide.