Patent ID: 8539158
Filing Date: 2013-09-17
Classification: G06F

Abstract:
1. A method for merging data, in a computer system having a hierarchy of caches, the hierarchy of caches consisting of one or more L1 caches associated with a corresponding processor, a shared L2 cache and main storage, the one or more L1 caches configured to hold a subset of shared L2 cache data, the method comprising: receiving a request from an input/output (I/O) device to merge I/O data with memory data; based on determining that the memory data does not exist in the shared L2 cache, loading the memory data to the shared L2 cache; directly obtaining a line of the memory data from the shared L2 cache without involving the one or more L1 caches and without using a memory controller; merging the line of the memory data with the I/O data in a merge buffer; and storing the merged data from the merge buffer directly in the shared L2 cache.