Patent ID: 6434206
Filing Date: 2002-08-13
Classification: H03L

Abstract:
A phase locked loop circuit for generating an output signal in response to an input signal, comprising:a phase detector for detecting a phase error between the input signal and the output signal and outputting a pump up signal and a pump down signal based on the phase error; a charge pump coupled to said phase detector for generating a charge pump signal in response to the pump up and the pump down signals; a loop filter coupled to said charge pump for filtering out high-frequency components from the charge pump signal to generate a filtered signal, said loop filter having an input terminal and an output terminal; boost-up means coupled to the output terminal of said loop filter for charging the input terminal of said loop filter in response to the filtered signal, to expedite the filtered signal reaching a predetermined common mode voltage level; and a voltage-controlled oscillator coupled to the output terminal of said loop filter and said phase detector, for generating the output signal in response to the filtered signal.