Patent ID: 6300200
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of fabricating a ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, said buried bit lines being oriented in a first direction, a gate oxide layer above the substrate and word lines formed above said gate oxide layer, said word lines being oriented in a second direction, which comprises the steps of:forming a dielectric layer over said word lines and said gate oxide layer;forming a first photoresist layer over said dielectric layer;selectively exposing said first photoresist layer to develop a first opening area over said photoresist layer, said first opening area centered between said adjacent bit lines;etching said dielectric layer through said first opening area;stripping said first photoresist layer;forming a second photoresist layer over said dielectric layer;selectively exposing said second photoresist layer to develop a second opening area over said second photoresist layer to define a pattern of code ion implantation;ion implanting a code implant dopant through said second opening area down into said substrate; andstripping said second photoresist layer.