Patent ID: 6839821
Filing Date: 2005-01-04
Classification: G11C

Abstract:
1. A method of reading from a nonvolatile memory array comprising the steps of: receiving a first address identifying a first location within the nonvolatile memory array wherein a first data is to be read, the nonvolatile memory array being coupled to a first page register and a second page register, the first and second page registers for buffering data that is to be read from the nonvolatile memory array; receiving a second address identifying a second location within the nonvolatile memory array wherein a second data is to be read; latching said first and second addresses in a set of address latches, coupled to the nonvolatile memory array, said set of address latches having at least a first address latch for receiving said first address and a second address latch for receiving said second address for addressing the nonvolatile memory array; operating said page registers and said address latches using a state machine; decoding said received first and second addresses; while receiving the second address, reading the first location of the nonvolatile memory array; storing the read first location in the first page register; reading the second location of the nonvolatile memory array; while reading the second location, receiving a third address for identifying a third location within the nonvolatile memory array where a third data is to be read, thereby creating a pipe-lining effect so as to expedite the performance of read operations of the nonvolatile memory array; and checking the number of read operations to be performed, and if a predetermined number of read operations has not been performed, continuing to the step of receiving a first address.