Patent ID: 6015734
Filing Date: 2000-01-18
Classification: H01L

Abstract:
A method for fabricating stacked capacitors for memory devices comprising the steps of:providing a semiconductor substrate having device areas with semiconductor devices;forming a planar first insulating layer over said device areas on said substrate;depositing a blanket etch-stop layer on said first insulating layer;depositing a second insulating layer on said etch-stop layer;selectively etching first openings for capacitor node contacts in said second insulating layer, said etch-stop layer, and said first insulating layer to said device areas;depositing a conductively doped first polysilicon layer to fill said first openings, and etching back said first polysilicon layer to form polysilicon plugs that are recessed below the surface of said second insulating layer and above said etch-stop layer;depositing a third insulating layer;selectively etching second openings, over and wider than said first openings, in said third and said second insulating layers to the top surface of said etch-stop layer and to said polysilicon plugs;depositing a conformal second polysilicon layer over and in said second openings and contacting said polysilicon plugs;polishing back said second polysilicon layer to said third insulating layer to form bottom electrodes in said second openings;isotropically etching said third and said second insulating layers selectively to said etch-stop layer to leave free-standing said bottom electrodes, while said polysilicon plugs that abut said etch-stop layer prevent said etching from eroding said first insulating layer when said second openings are misaligned to said first openings;depositing an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a third polysilicon layer to form top electrodes and completing said stacked capacitors.