Patent ID: 7078773
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A double-gate field effect transistor (DGFET) comprising: a doped back-plane region having thermal oxide isolation regions located adjacent to said doped back-plane and atop a portion of the doped back-plane; a back-gate dielectric stack including at least a bottom back-gate nitride located atop a surface portion of said doped back-plane region not containing said thermal oxide isolation regions; a Si-containing layer having edges located atop said back-gate dielectric stack, each of said Si-containing edges including a source/drain region, wherein said edges of the Si-containing layer are essentially free of sidewall oxide; a front gate dielectric located atop portions of said Si-containing layer; a front gate located atop said front gate dielectric; and Si-containing regions located adjacent to said front gate and over said thermal oxide isolation regions, said Si-containing regions are in contact with said source/drain regions, wherein said thermal oxide regions are aligned to a vertical edge of the front gate and are not connected to each other in a region beneath said front gate.