Patent ID: 7239189
Filing Date: 2007-07-03
Classification: H03K,H03L

Abstract:
1. A clock generating circuit comprising: a first delay circuit array for delay measurement having a plurality of delay circuits, said first delay circuit array receiving an input signal and outputting a signal from a delay circuit at a position to which the applied input signal has traveled following a prescribed delay time; and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction opposite a direction of signal propagation in said first delay circuit array; wherein on the basis of the signal output from the delay circuit at the position where the delay has been detected in said first delay circuit array, an output terminal of a delay circuit in said second delay circuit array that corresponds to the position where the delay has been detected in said first delay circuit array is fed back to an input terminal of the delay circuit to thereby construct a closed-loop oscillator circuit, an oscillation output signal being extracted from said oscillator circuit at an output terminal of said second delay circuit array.