Patent ID: 6125157
Filing Date: 2000-09-26
Classification: G06F,G11C,H03K,H03L,H04L

Abstract:
A method for generating an output clock with a predetermined phase relationship with an input clock, the method comprising the steps of:selecting a pair of adjacent phase vectors from a set of phase vectors, each vector separated in time from an adjacent vector by a unit delay;generating the output clock using an interpolator that receives the selected pair of phase vectors;delaying the output clock from the interpolator by a delay equal to a multiple of the unit delay to produce a feedback clock;adjusting the selection of a pair of adjacent phase vectors received by the interpolator so that the phase of the input clock lies between the selected pair of phase vectors;detecting the difference in phase between the input clock and the feedback clock;interpolating between the selected pair of adjacent phase vectors using the interpolator so that the feedback clock is in phase with the input clock based on the detected phase difference between the input clock and the feedback clock; andwherein the output clock from the interpolator has the predetermined phase relationship with the input clock when the feedback clock is in phase with the input clock, the predetermined phase relationship being a multiple of the unit delay.