Patent ID: 7112866
Filing Date: 2006-09-26
Classification: H01L

Abstract:
1. A multilevel interconnect structure, comprising: a semiconductor surface that has been provided with metal points of electrical contact, there-over having been created a low k compound layer of inter metal dielectric comprising: (1) a first layer of dielectric deposited on said semiconductor surface, said first layer of dielectric comprising a first network of trenches filled with air; (2) a second layer of dielectric deposited on and in contact with said first layer of dielectric, said second layer of dielectric comprising a second network of trenches filled with air, said second network of trenches beings in contact with and intersecting with said first network of trenches to form an interconnected network of trenches filled with air; and (3) a layer of oxide deposited over said second layer of dielectric, said layer of oxide comprising: (i) a first layer of oxide having openings created there-through, said openings being aligned with the intersections between said first and second network of trenches, enabling creation of said first and second network of trenches; and (ii) a second layer of oxide, said second layer of oxide closing the openings in the first layer of oxide.