Patent ID: 6188345
Filing Date: 2001-02-13
Classification: H03M

Abstract:
A sigma-delta A/D converter, comprising:a plurality of sample-hold circuits coupled to receive an analog input signal, each responsive to a respective one of a plurality of phase clocks to sample and hold a corresponding sample of the analog input signal;a plurality of circuit stages arranged in a sequence, each circuit stage associated with one of the plurality of sample-hold circuits, a first one of the plurality of circuit stages comprising:a summer having a first input receiving a data signal from a first one of the plurality of sample-hold circuits, a second input receiving an initial prior sum signal, and a negative input receiving an initial prior quantized sum signal, for producing a sum signal at a summer output; anda quantizer coupled to the summer output for quantizing the sum signal into a quantized sum signal;and wherein each of the other of the plurality of circuit stages comprise:a summer having a first input receiving a data signal from a corresponding sample-hold circuit, a second input receiving a prior sum signal from the summer output of the prior circuit stage in the sequence, and a negative input receiving a prior quantized sum signal from the quantizer of the prior circuit stage in the sequence, for producing a sum signal at a summer output; anda quantizer coupled to the summer output for quantizing the sum signal into a quantized sum signal.