Patent ID: 8076729
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A method for forming a dual gate electrode of a semiconductor device, comprising the steps of: forming a first polysilicon layer over the entire surface of a semiconductor substrate; forming a first photoresist pattern on the first polysilicon layer so as to close a first region, the first region being one of a PMOS and an NMOS region; leaving the first polysilicon layer only in the first region by removing an exposed portion of the first polysilicon layer by etching using the first photoresist pattern; removing the first photoresist pattern; forming a second polysilicon layer over the entire surface of the first polysilicon layer and semiconductor substrate; wherein the second polysilicon layer is directly contact with the first polysilicon layer; forming a second photoresist pattern on the second polysilicon layer so as to close the first region and so as to close and define a second region different from the first region; leaving the first and second polysilicon layers in a stack in the first region and leaving the second polysilicon layer in the second region by removing an exposed portion of the second polysilicon layer until the semiconductor substrate is exposed by etching using the second photoresist pattern; and removing the second photoresist pattern; wherein the first region is formed in a two-layer structure which includes the first polysilicon layer and the second polysilicon layer, and wherein the second region is formed in a single layer structure which includes the second polysilicon layer.