Patent ID: 7493448
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A method of controlling hit determination of a shared cache memory in a multiprocessor system that includes a plurality of processors, said shared cache memory being a multiple-way set-associative cache memory that contains a directory and a data array, said multiprocessor system being partitioned such that said plurality of processors each operate as independent systems, the method comprising: allocating ways of said shared cache memory to respective partitions of said multiprocessor system, said shared cache memory not including an indication of said partitions, wherein said multiprocessor system allocates a region dedicated to respective partitions and a region common to said partitions; and determining hits of only said ways that have been allocated to said partition, by, after determining one set, selecting either the region dedicated to respective partitions or the region common to said partitions from the ways in said set, said determined set being unchanged even when the selection of a partition is changed each time the cache is accessed.