Patent ID: 6444571
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A process for fabricating a semiconductor device, comprising the steps of:a) forming at least one lower metal line over a semiconductor substrate; b) covering said lower metal line with an inter-level insulating layer wherein said semiconductor substrate is heated to a temperature that is less than or equal to a first temperature, wherein said inter-level insulating layer is deposited at the first temperature; c) forming at least one via-hole in said inter-level insulating layer; d) performing out an outgassing process wherein said semiconductor substrate is heated to a second temperature that is equal to or less than said first temperature; and e) forming at least one upper metal line penetrating into said via-hole and formed of a conductive material selected from the group consisting of aluminum and aluminum alloys wherein said at least one upper metal line is formed in a vacuum deposition at a temperature that is lower than said first temperature.