Patent ID: 8759910
Filing Date: 2014-06-24
Classification: H01L

Abstract:
1. A semiconductor power device comprising: a plurality of transistor cells disposed in an active area near a top surface of an epitaxial layer of a first conductivity type grown on a semiconductor substrate of said first conductivity type wherein each of said transistor cells is surrounded by trenched gates, said trenched gates being surrounded by source regions of said first conductivity type encompassed in body regions of a second conductivity type and extending into said epitaxial layer; multiple trenched floating gates disposed in a termination area without having said source regions, surrounding said active area and each of said trenched floating gates having a floating voltage wherein said trenched floating gates are penetrating through said body regions and extending into said epitaxial layer; at least one wider trenched gate in a gate contact area, having a greater trench width than said trenched gates and electrically connecting said trenched gates in said active area to a gate metal; a HDP (High-Density Plasma) oxide layer padded with a thermal oxide layer formed on bottom surfaces of said trenched gates, said at least one wider trenched gate and said trenched floating gates and top surface of said mesa areas between two adjacent of said trenched gate; and a plurality of trenched source-body contact structures penetrating through a contact interlayer, said HDP oxide layer, said thermal oxide layer and said source regions, and extending into said body regions in said transistor cells in said active area, each of said trenched source-body contact structures being filled with a contact metal plug for electrically connecting said source region and said body region to a source metal.