Patent ID: 8856578
Filing Date: 2014-10-07
Classification: H03K,H03L,H04L

Abstract:
1. An integrated circuit device, comprising: a plurality of signal lines configured to transmit a plurality of signals respectively; a plurality of buffer circuits provided corresponding to the plurality of signal lines respectively and configured to receive the plurality of signals transmitted by the plurality of signal lines respectively; a plurality of delay circuits provided in respective stages preceding the plurality of buffer circuits and configured to delay the plurality of signals, respectively; a monitoring circuit configured to detect a number of signal changes, the number of signal changes corresponding to a number of the signal lines in which changes of the signals occur during a monitoring period; and a delay adjustment circuit configured to decide a first plural types of delay amounts as the delay amounts for the plurality of delay circuits when the number of signal changes detected by the monitoring circuit is a first plural number, and to decide a second plural types of delay amounts, where the second plural types is greater than the first plural types, as the delay amounts for the plurality of delay circuits when the number of signal changes is a second plural number greater than the first plural number, and to set the delay amounts in the plurality of delay circuits, respectively.