Patent ID: 6461913
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method for fabricating semiconductor memory device, comprising the steps of:providing a semiconductor substrate, forming a gate electrode on the semiconductor substrate, and forming a plurality of source/drain junctions in the semiconductor substrate; forming an interlayer insulating layer over the semiconductor substrate; etching the interlayer insulating layer to form a contact hole; forming a plug with a diffusion barrier and a conducting layer in the contact hole, and forming the conducting layer with a material capable of flowing current when the conducting layer is oxidized; forming a seed layer on the conducting layer; forming a glue layer on the seed layer; forming a sacrificial layer on the glue layer; etching the sacrificial layer and the glue layer to form an opening defining a region of the lower electrode; forming a lower electrode on the seed layer in the opening; removing the sacrificial layer and the seed layer; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.