Patent ID: 7109801
Filing Date: 2006-09-19
Classification: H03F

Abstract:
1. A power amplifier having low gate oxide stress, the power amplifier comprises: input transistor having an input, a first node, and a second node, wherein the second node of the input transistor is coupled to a supply voltage return and the input of the input transistor operably coupled to receive an outbound radio frequency (RF) signal; output transistor having an input, a first node, and a second node, wherein the first node of the output transistor is coupled to provide an output of the power amplifier, the second node of the output transistor is coupled to the first node of the input transistor; and circuitry operably coupled to provide an enabling bias voltage to the input of the input transistor and to the input of the output transistor during a transmit mode and to provide a disabling bias voltage to the input of the input transistor and to the input of the output transistor during a power down mode, wherein the disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.