Patent ID: 9082659
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A method of manufacturing a vertical type semiconductor device comprising: forming a mold layer by repeatedly stacking sacrificial layers and insulating layers on a substrate; forming a pillar structure penetrating the mold layer and protruding in a first direction which is a vertical direction relative to an upper surface of the substrate, the pillar structure including a semiconductor pattern and a channel pattern, an oxidation target layer being included at an exterior surface of the pillar structure; selectively removing the sacrificial layers to expose the oxidation target layer; removing a portion of the oxidation target layer to form oxidation target layer patterns making contact with the insulating interlayers and having a smaller height than the insulating interlayers in the first direction; oxidizing the surface of the oxidation target layer patterns to form first insulating layer structures including an oxide, the first insulating layer structures including a first portion having a relatively smaller height and making contact with the pillar structure and the insulating interlayer horizontally extended in the side direction of the first portion; and forming first word line structures at a gap portion between the first insulating layer structures, the first word line structures being horizontally extended while surrounding the pillar structure at a portion facing the channel pattern and including a blocking dielectric layer pattern and a metal pattern, a height of the first word line structure at a portion making contact with the pillar structure being enlarged.