Patent ID: 6407007
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method for forming a thick insulator layer on an underlying, spin on glass, (SOG), layer, with said SOG layer featuring a planar, smooth top surface topography, on a semiconductor substrate, comprising the steps of:forming metal interconnect structures, on an underlying first insulator layer; depositing a second insulator layer on said metal interconnect structures, and in the spaces between said metal interconnect structures; applying said SOG layer, on said second insulator layer completely filling the spaces between said metal interconnect structures, and resulting in said SOG layer featuring said planar, smooth top surface topography; baking of said SOG layer; curing of said SOG layer; performing a plasma treatment, in a nitrogen containing ambient,for a time between about 20 to 60 sec, resulting in said SOG layer comprised with a planar, roughened top surface topography; and depositing said thick insulator layer, comprised of silicon nitride at a thickness between about 8000 to 12000 Angstroms, on plasma treated, said planar, roughened top surface topography, of said SOG layer.