Patent ID: 6539049
Filing Date: 2003-03-25
Classification: H04B

Abstract:
An integrated circuit device for maintaining time synchronous with a CDMA network time, comprising:a clock generator having a primary input for coupling to a primary reference frequency source, and an output, the output producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n) in a primary mode, and a secondary digital transceiver clock signal having a frequency of chiprate in a secondary mode; a chiprate divider having an input coupled to the output of the clock generator and an output producing a primary mode enable signal having a frequency of chiprate when in a primary mode; a long PN generator having a clock input and an enable input, the clock input being coupled to the output of the clock generator; a short PN generator having a clock input and an enable input, the clock input being coupled to the output of the clock generator; a first multiplexer having a first input coupled to the output of the chiprate divider, a second input coupled to an output providing a secondary mode enable signal, a control input, and an output coupled to the enable input of the long PN generator and to the enable input of the short PN generator; and a controller having a multiplexer control output coupled to the control input of the first multiplexer, the controller producing a first control signal at the control output for producing the primary mode enable signal at the output of the first multiplexer in a primary mode, the controller producing a second control signal at the control output for producing the secondary mode enable signal at the output of the first multiplexer in a secondary mode.