Patent ID: 6649982
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate doped with a first type of dopant having a top surface providing an interface on which an epitaxial semiconductor layer is formed with the epitaxial layer being counterdoped with an opposite type of dopant, and the epitaxial layer having an upper surface, dielectric, Shallow Trench Isolation (STI) structures formed in the epitaxial layer extending downwardly from the upper surface with the STI structures separating the epitaxial layer into a shallow collector plug area, an emitter/base bipolar region in said epitaxial layer located between a pair of STI structures with the emitter/base bipolar region being lightly doped with the first type of dopant, an NMOS area between a second pair of STi structures, and a PMOS area between a third pair of STI structures with a gap between bottoms of the STI structures and the top surface of the substrate, a buried region for a bipolar transistor formed in the substrate and in the epitaxial semiconductor layer solely at the bottom of the emitter/bipolar region, deep below the upper surface of the epitaxial layer, straddling the interface, and reaching across through the gap in the epitaxial semiconductor layer below an STI) structure, the buried region being counterdoped with the opposite type of dopant, an emitter region formed at the surface of the epitaxial layer in the emitter/base bipolar region being counterdoped with the opposite type of dopant, a base region formed at the surface of the epitaxial layer in the emitter/base bipolar region juxtaposed with the emitter region, the base region being doped with the first type of dopant, a collector plug formed extending through the shallow collector plug area from the upper surface of the epitaxial layer down through the epitaxial layer and through the top surface of the substrate into contact with the buried region, the collector plug being counterdoped with the opposite type of dopant, a thin silicon oxide layer superjacent to the (STI) structures on the top surface of the epitaxial semiconductor layer, a conductive polysilicon layer superjacent to the thin silicon oxide layer, bipolar dopant formed in a portion of the conductive polysilicon bipolar layer over the emitter/base bipolar region of the substrate, dopant having been driven from the polysilicon bipolar layer into the substrate including the thin oxide layer in the bipolar region in the emitter/base bipolar area in the substrate, and doped source/drain regions formed in the NMOS and PMOS areas of the epitaxial semiconductor layer.