Patent ID: 9099343
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; a first doped region and a second doped region provided spaced apart from each other on the substrate; a storage node contact plug in contact with the first doped region; a bitline electrically connected to the second doped region; a bitline node contact plug disposed between the bit line and the second doped region; and a spacer interposed between the bit line and the storage node contact plug and between the bitline node contact plug and the storage node contact plug, wherein the spacer comprises: an etch stop pattern disposed between the storage node contact plug and the bitline node contact plug to be in contact with at least the storage node contact plug; and a first sub-spacer disposed between the storage node contact plug and the bit line to be in contact with the storage node contact plug and the etch stop pattern.