Patent ID: 9147647
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a die pad including an upper surface and a lower surface opposite to the upper surface; a semiconductor chip including a main surface and a back surface opposite to the main surface so that a plurality of electrode pads are formed on the main surface and being mounted on the die pad so that the back surface is opposite to the upper surface of the die pad; a plurality of leads arranged to be aligned on a side of the die pad; a first wire electrically connecting between a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads; and a second wire having a diameter thicker than a diameter of the first wire and electrically connecting between a second electrode pad among the plurality of electrode pads of the semiconductor chip and a second lead among the plurality of leads, wherein each of the plurality of leads includes a wire joint part at a distal end on the side of the die pad, wherein the wire joint part of each of the plurality of leads includes a first region including a most outer surface on which a first plating is applied and a second region including a most outer surface on which a second plating different from the first plating is applied, wherein the second region in the wire joint part is arranged on the side of the die pad, and the first region is arranged at a position distant from the die pad which is farther than the second region, and wherein the first plating and the second plating are stacked in the first region.