Patent ID: 6278287
Filing Date: 2001-08-21
Classification: G11C,H01L,H03K

Abstract:
An SEU signal blocking and dissipation subcircuit comprised of:(a) a blocking subciruit using transistors that are entirely of type PMOS which are all contained within a single n-well, said blocking subcircuit having one external source node which is connected to the n-well and sources of one or more of the subcircuit's transistors, one external drain node which is connected to one or more drains of the subcircuit's transistors, and a set of external gate nodes connected to the subcircuit's transistor gates and having bias applied to the external gate nodes such that whenever any circuit connected to the blocking subcircuit's external source node is in an SEU sensitive state, the current path(s) through the blocking subcircuit from the external source node to the external drain node will be in a high impedance (off) state; and(b) a shunt subcircuit connected between the blocking subcircuit's external source node and another circuit node which has a static bias potential with respect to the blocking subcircuit's external drain node the magnitude of which is less than 40% of the potential from the supply voltage to ground and said shunt subcircuit having a current capability which is less than 50% of any low impedance circuit path from the blocking subcircuit's external drain node to the negative circuit power supply or ground.