Patent ID: 6333890
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A memory device having a plurality of banks each including a plurality of memory cells, for reading or writing data from or into memory cells, said memory device comprising:a plurality of banks, each of said plurality of banks including a plurality of memory cells and a global data bus through which said data is read out of or written into the memory cells;a plurality of common data buses shared by said plurality of banks, the number of said common data buses being less than the number of said banks; anda plurality of switching circuits provided for each of said plurality of banks, for feeding or receiving data of each of said plurality of banks to or from said plurality of common data buses, one of said plurality of switching circuits being provided between each global data bus and the plurality of common data buses for selectively connecting each global data bus with one of the plurality of common data buses; whereinread or write operations of data of said plurality of banks are made by cyclically switching said switching circuits so that the global data buses of selected banks are connected to each of the plurality of common data buses in a cyclic fashion.