Patent ID: 6246113
Filing Date: 2001-06-12
Classification: H01L

Abstract:
An IC package architecture with ESD protection, said IC package including more than 100 package pins wherein at least 5 of which are no-connect pins, said IC package further including a lead frame having a die pad for mounting an IC chip thereon and a plurality of package pins wherein said at least 5 no-connect pins are grouped into at least one separate unit, each unit consisting of one single no-connect pin or a number of consecutively arranged no-connect pins, said IC package architecture comprising:an input pin which is connected via a bonding wire to the bonding pad which is connected to an ESD protection circuit;a power pin or a conductive tongue arranged proximate to a first side of each no-connect pin unit, said conductive tongue being extended from said die pad along the first side of the no-connect pin unit; anda power pin or a conductive tongue arranged proximate to a second side of each no-connect pin unit, said conductive tongue being extended from said die pad along the second side of the no-connect pin unit.