Patent ID: 6774430
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate including an active region of first conductive type; a gate insulating layer formed on said active region, said gate insulating layer including a thin central section of about 3 nm thickness and thick end sections on both sides thereof; a floating gate electrode formed on said gate insulating layer; an inter-electrode insulating layer formed on said floating gate electrode; a control gate electrode formed on said inter-electrode insulating layer; a pair of source/drain regions of second conductive type respectively extending in said active region from respective regions outside of said floating gate electrode respectively below said thick end sections, said source/drain regions being apart from said thin central section, wherein said source/drain regions, comprises: extension regions extended below said thick end sections; and source/drain contact regions respectively formed on both outside regions respectively of said extension regions, said source/drain contact regions having a junction depth exceeding a junction depth of said extension regions.