Patent ID: 7804122
Filing Date: 2010-09-28
Classification: H01L

Abstract:
1. A non-volatile memory, comprising: a substrate, having two openings; a stacked gate structure, disposed on the substrate between the two openings, wherein the stacked gate structure comprises a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer sequentially stacked on the substrate; a liner, disposed on a bottom of each of the two openings and a portion of a sidewall of each of the two openings, wherein a top surface of the liner is lower than that of the substrate; a second conductive layer, disposed on the liner at the bottom of each of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner; and a third conductive layer, disposed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is higher than a top surface of the substrate and lower than that of the first dielectric layer.