Patent ID: 6424579
Filing Date: 2002-07-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to said plurality of rows, and a plurality of bit line pairs provided corresponding to said plurality of columns; a data input/output line pair provided common to said plurality of bit line pairs; a plurality of column select gates provided corresponding to said plurality of bit line pairs, each column select gate connected between a corresponding bit line pair and said data input/output line pair; a plurality of sense amplifiers provided corresponding to said plurality of bit line pairs, each sense amplifier being driven by a first internal power supply potential to amplify potential difference generated between a corresponding bit line pair in response to a corresponding memory cell rendered active; a row select circuit selecting a word line out of said plurality of word lines according to a row address signal to drive the selected word line to a select level and render active each corresponding memory cell; a column select circuit driven by a second internal power supply potential to select a bit line pair out of said plurality of bit line pairs according to a column address signal to render conductive the column select gate corresponding to said selected bit line pair; a data input/output circuit connected to said data input/output line pair to write/read data of a memory cell rendered active by said row select circuit via a bit line pair selected by said column select circuit; a first potential generation circuit generating and providing to said plurality of sense amplifiers said first internal power supply potential according to an external power supply potential; a second potential generation circuit generating and providing to said column select circuit said second internal power supply potential according to said external power supply potential, at least one of said first and second potential generation circuits having a speed of response with respect to change in an output potential therefrom controllable; and a control circuit controlling said speed of response with respect to change in the output potential of at least one of said first and second potential generation circuits according to an external control signal.