Patent ID: 6237105
Filing Date: 2001-05-22
Classification: A61N,G06F

Abstract:
A clock circuit for providing a main clock signal having periodic logic state transitions to an associated circuit which performs actions in response to said logic state transitions of said main clock signal and provides completion signals indicating completion of said actions performed in response to a preceding logic state transition of said main clock signal, wherein said clock circuit comprises:a main clock output means for providing said main clock signal to said associated circuit;a clock signal input means for receiving an input clock signal having periodic logic state transitions;completion signal input means for receiving said completion signals from said associated circuit;means responsive to occurrence of a logic state transition of said input clock signal for causing a logic state transition of said main clock signal, said responsive means further comprising logic means responsive to receipt of a said completion signal indicating completion of actions performed in response to a preceding logic state transition of said main clock signal, for delaying said transition of said logic state of said main clock signal until receipt of said completion signal.