Patent ID: 8649475
Filing Date: 2014-02-11
Classification: G06F,G11C,H03L,H04L,Y02D

Abstract:
1. A memory device, comprising: clock-receiving circuitry to receive a global clock signal; phase-adjusting circuitry coupled to the clock-receiving circuitry; and data-receiving circuitry to operate in a standby mode, a partial-rate mode, or an active mode; wherein in the standby mode, power supplied to the data-receiving circuitry and the phase-adjusting circuitry is substantially removed; wherein in the partial-rate mode, the data-receiving circuitry receives a data bit transmitted repeatedly over more than one interval based on the global clock signal, wherein a respective interval corresponds to a transmission time of a data bit in the active mode, and the phase-adjusting circuitry adjusts a phase of the global clock signal based on received data to produce a local phase-adjusted clock signal; and wherein in the active mode, the data-receiving circuitry receives a data bit transmitted in one interval based on the local phase-adjusted clock signal.