Patent ID: 6498750
Filing Date: 2002-12-24
Classification: G11C

Abstract:
A boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory comprising at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity, wherein:the plurality of asymmetrical blocks is divided into at least one virtual block, each of the at least one virtual block being comprised of a plural number of asymmetrical block; the boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or the at least one virtual block, and when erasing data stored in each of the at least one virtual block, the second address signal is counted so as to address each asymmetrical block comprising the virtual block.