Patent ID: 6070216
Filing Date: 2000-05-30
Classification: G06F

Abstract:
A serial I/O incorporated semiconductor device comprising:a plurality of transmitting pins for outputting serial transmit data;a plurality of receiving pins for inputting serial received data;a CPU;a transmitting unit comprising a transmission shift register for outputting written transmit data from said transmitting pins, a transmission completion detection circuit for detecting normal completion of transmission of the transmit data, a transmission completion flag set to have a predetermined value by said transmission completion circuit that has detected normal completion of transmission of transmit data and a transmission channel selection register for selecting said transmitting pin to output transmit data, wherein when said transmission completion flag is set to the predetermined value, said transmitting unit supplies the value to said CPU; anda receiving unit comprising a receiving shift register for writing received data inputted to said receiving pins therein, a reception completion detection circuit for detecting normal completion of reception of received data, a reception completion flag set to have a predetermined value by said reception completion detection circuit that has detected normal completion of reception of received data, a receiving error detection circuit for detecting unusual receiving of received data, a receiving error flag set to have a predetermined value by said receiving error detection circuit that has detected unusual receiving of received data, a receiving channel detection circuit for detecting said receiving pins that have received data, a receiving channel flag set to have a predetermined value by said receiving channel detection circuit that has detected said receiving pins that have received data, a plural channels reception detection circuit for detecting that received data is inputted to the plurality of receiving pins by searching a value of said receiving channel flag, and a plural channels receiving flag set to have a predetermined value by said plural channels reception detection circuit which has detected that received data has been inputted to the plurality of receiving pins, wherein when any one of said reception completion flag, said receiving error flag, and said plural channels receiving flag is set to the predetermined value, said receiving unit supplies the value to said CPU as a reception interrupt signal.