Patent ID: 8258621
Filing Date: 2012-09-04
Classification: H01L,Y10S

Abstract:
1. A semiconductor chip including memory cells, the semiconductor chip comprising: semiconductor substrate; a lower conductive layer including a gate electrode interconnect layer and a diffusion layer of the semiconductor substrate; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer, wherein one of the memory cells comprises; a first inverter including a first transistor having a first conductivity type; a second inverter including a second transistor having the first conductivity type, an output of the second inverter connecting to an input of the first inverter and an input of the second inverter connecting to an output of the first inverter; a first electrical connection between one end of the first transistor made of the lower conductive layer and a first line made of the upper conductive layer, the first electrical connection connecting to the output of the first inverter; and a second electrical connection between one end of the second transistor made of the lower conductive layer and a second line made of the upper conductive layer, the second electrical connection connecting to the output of the second inverter, wherein the first electrical connection comprises: a first connection plug extending from an immediately above position of the one end of the first transistor; a second connection plug disposed at a shift position from the immediately above position of the one end of the first transistor to recede from the second electrical connection; and a first intermediate line made of an intermediate connection layer for electrically connecting the first and the second connection plugs.