Patent ID: 6313516
Filing Date: 2001-11-06
Classification: H01L

Abstract:
Polysilicon resistors on a semiconductor substrate comprised of:field oxide regions on surface of said substrate surrounding and electrically isolating device areas;a gate oxide on said device areas;a first polysilicon layer and a refractory metal silicide layer that are patterned to form FET gate electrodes over said device areas and that form local interconnections over said field oxide that include bottom plates for capacitors;insulating sidewall spacers and source/drain contact areas adjacent to said FET gate electrodes;a thin first insulating layer as an interpolysilicon oxide that is used as an interelectrode dielectric layer for said capacitors;a doped second polysilicon layer with an upper undoped third polysilicon layer patterned to form resistors and top plates for said capacitors;a second insulating layer that electrically insulates said devices, said resistors, and said capacitors;contact openings for said resistors in said second insulating layer and extending through said undoped third polysilicon layer to said doped second polysilicon layer;electrically conducting plugs in said contact openings; anda patterned metal layer that forms the next level of interconnections and that contact said conducting plugs to form said resistors having said interconnections.