Patent ID: 6738918
Filing Date: 2004-05-18
Classification: G06F,G11C

Abstract:
A high-speed data transfer synchronizing system comprising:a memory device which receives a clock signal and which operates in synchronism with said clock signal; a controller which generates and supplies said clock signal to said memory device, and transfers/receives data to/from said memory device; and a timing control circuit which controls an input/output timing of the data transferred/received between said memory device and controller, wherein, before the data is transferred/received between said memory device and controller, said timing control circuit (a) causes a data pattern pre-stored in the memory device to be output in synchronism with the clock signal, and controls either operation timing of the input timing or output timing so as to allow the controller to correctly read-in the data pattern in synchronism with the clock signal; (b) causes a predetermined data pattern to be output from the controller, and causes the predetermined data pattern to be read in the memory device in synchronism with the clock signal; (c) causes the predetermined data pattern written in the memory device to be output from the memory device and to be read in the controller, (d) controls other operation timing of the input timing and output timing until the predetermined pattern read in the controller agrees with the predetermined data pattern written in the memory device, thereby controlling the input/output timing of the data.