Patent ID: 6620031
Filing Date: 2003-09-16
Classification: B24B,B24D

Abstract:
A method for optimizing the planarizing length of a polishing pad, comprising:a) forming a substantially constant network of islands and trenches into a first side of a polishing pad, wherein said trenches are formed to a pre-determined distance apart; b) fitting said polishing pad to a chemical-mechanical polishing system; c) planarizing a surface layer of a semiconductor wafer with said first side of said polishing pad; d) observing said planarized wafer surface layer; e) uniformly decreasing said distance between said trenches on said first side of said polishing pad if said wafer surface layer is planarized to an amount outside of a set target polishing range; and f) repeating b through e until said wafer surface layer is planarized to an amount within said set target polishing range.