Patent ID: 7902059
Filing Date: 2011-03-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a pattern on a substrate, the pattern having an opening that exposes a portion of the substrate; forming a first preliminary polysilicon layer on the pattern and on the exposed portion of the substrate to substantially fill the opening, a first deposition irregularity in the first preliminary polysilicon layer; forming a first polysilicon layer by partially etching the first preliminary polysilicon layer until the first deposition irregularity in the first preliminary polysilicon layer is exposed; and forming a second polysilicon layer on the first polysilicon layer and on the pattern to substantially fill a recess caused by an exposure of the first deposition irregularity, a second deposition irregularity in the second preliminary polysilicon layer; and partially etching the second preliminary polysilicon layer to expose the second deposition irregularity in the second preliminary polysilicon layer.