Patent ID: 7071062
Filing Date: 2006-07-04
Classification: H01L

Abstract:
1. A manufacturing process for an integrated device comprising a MOS transistor and a Schottky diode, said process comprising: forming a plurality of body region stripes of a first conductivity type inside a semiconductor material substrate of a second conductivity type, said body region stripes being adjacent and parallel to each other; forming a plurality of elementary structures parallel to each other, each one of which comprises a silicon oxide layer placed over a portion of said substrate which is between two adjacent body region stripes, a polysilicon layer being superimposed over said silicon oxide layer; forming source regions of the second conductivity type inside at least one of said plurality of adjacent body region stripes and in an adjacent way to a first zone of said elementary structures for forming elementary cells of said MOS transistor, said elementary structures and said body regions stripes extending longitudinally in a transversal way to the formation of the channel in said elementary cells of the MOS transistor; depositing a dielectric layer over and around said elementary structures; depositing a first metal layer over said substrate for contacting the source regions; forming a second metal layer under said substrate; and masking the silicon oxide layer and the superimposed polysilicon layer of at least one elementary structure in at least a second zone of said elementary structure, wherein said first metal layer is deposited for contacting the underlying substrate portion of said at least a second zone to form the Schottky diode.