Patent ID: 7560971
Filing Date: 2009-07-14
Classification: H03K

Abstract:
1. A level shift circuit comprising: a first transistor having a gate, a source, and a drain, wherein the gate is coupled to a first input, the source is coupled to a first voltage supply, and the drain is coupled to a first output; a second transistor having a gate, a source, and a drain, wherein the gate is coupled to a second input, the source is coupled to the first voltage supply, and the drain is coupled to a second output, and wherein the second input has an inverted logic state of the first input; a third transistor having a gate, a source, and a drain, wherein the gate is coupled to the second output and the drain is coupled to the first output; a fourth transistor having a gate, a source, and a drain, wherein the gate is coupled to the first output, the source is coupled to a second voltage supply, and the drain is coupled to the second output; and a first control circuit comprising: