Patent ID: 6973009
Filing Date: 2005-12-06
Classification: G11C

Abstract:
1. A method of switching modes of a memory system in which a normal mode and a synchronous mode are switchable, comprising: supplying a clock signal, a first control signal and a second control signal to the memory system; setting the mode to be the normal mode in a case in which the second control signal is of a first level, and setting the mode to be the synchronous mode in a case in which the second control signal is of a second level, when the first control signal transits; fetching in an address signal regardless of the clock signal when the mode is set to be the normal mode; designating an address of a memory cell in a memory cell array after the address signal is asserted; inputting/outputting data regardless of the clock signal after the address of the memory cell in the memory cell array is designated in the normal mode; designating the address of the memory cell in the memory cell array in response to at least one of a rising edge and a falling edge of the clock signal; and obtaining a plurality of output data output from the memory cell array in synchronism with the clock signal after the address signal is asserted, output of the data beginning after a number of clock cycles (latency N, N being a positive integer ≧2) of the clock signals, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output in the synchronous mode.