Patent ID: 6047357
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A cache memory system for use with a computer system comprising:a plurality of caches, each cache including a plurality of addressable storage locations for storing data and said plurality of caches arranged in a hierarchical fashion and said plurality of caches adhering to a subset rule;means for comparing a portion of tag bits of an entry stored in a first one of said plurality of caches with address bits asserted on a bus, said portion of tag bits being associated with ones of said address bits needed to index a location in a second one of said plurality of caches; andmeans responsive to said comparing means for determining a most recent version of a data item stored in said first one of said plurality of caches during a lookup of said first one of said plurality of caches without a lookup of said second one of said plurality of caches;means, responsive to said determining means for placing said most recent version of said data item in a main memory before replacing said data item with another data item.