Patent ID: 7939446
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A process to fabricate an effective very low dielectric constant interconnect structure comprising: a) depositing on a substrate a layer comprising at least one dielectric layer lying between interconnects; b) depositing on said at least one dielectric layer at least one layer comprising a cap layer; c) depositing layers comprising a sacrificial organic layer, low temperature oxide layer, ARC layer and a sacrificial first lithographic resist layer in that order on said cap layer; d) applying on said sacrificial first lithographic resist layer a mask comprising a blockout mask with lines that project into an area between and that do not overlie said interconnects, and lithographically developing said sacrificial first lithographic resist layer through said blockout mask to form a pattern of said lines in said sacrificial first lithographic resist layer; e) shrinking the dimension of said pattern of lines by etching wherein said etching comprises isotropic etching; f) applying a planarizing layer that extends between and above said pattern of lines to obtain a planarizing layer with said pattern of lines, and reducing the thickness of said planarizing layer with said pattern of lines to expose said pattern of lines as a reversed tone pattern in the planarizing layer and thereby form a trench pattern in the planarizing layer; g) selectively etching said photoresist through said trench pattern in said planarizing layer as a mask; h) transferring said trench pattern through said ARC layer, low temperature oxide layer, sacrificial organic layer, and said cap layer, and onto said at least one dielectric layer to form a trench corresponding to said trench pattern and to form a cap layer having perforations; i) forming an airgap comprising extracting said at least one dielectric layer between said interconnects, said extracting being conducted through said cap layer having perforations and said trench, said airgap extending from a point in said trench in the region of said cap layer having perforations to a region between said interconnects; j) depositing a layer comprising at least a second dielectric layer on said cap layer having perforations that extend into and coats the surface of said airgap; and k) pinching-off said cap layer having perforations with said second dielectric layer to provide a pinched-off airgap.