Patent ID: 6760249
Filing Date: 2004-07-06
Classification: G11C

Abstract:
A memory cell, comprising:a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor and a first capacitor, a gate of the first storage transistor and the first capacitor for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor and a second capacitor, a gate of the second storage transistor and the second capacitor for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a match line; a match unit, coupled to the first bit line, the second bit line, the first storage transistor and the second storage transistor, wherein during the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the second bit line receiving a comparing data bit and the first bit line receiving a complement of the comparing data bit, if the complement of the comparing data bit from the first bit line is not logically equal to the storage data bit, or if the comparing data bit from the second bit line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.