Patent ID: 6253302
Filing Date: 2001-06-26
Classification: G06F

Abstract:
An apparatus comprising:a bus interface to receive a set of address lines;comparator circuitry coupled to the bus interface to receive a set including all bits corresponding to the set of address lines and to determine an address represented by bits on the address lines to determine an address space, from a plurality of address spaces, to which the address corresponds, wherein addresses in a first address space require bits from all address lines to represent addresses therein and addresses in other address spaces of the plurality of address spaces are represented by bits from a subset of the address lines; anda parity checking circuit coupled to receive the address and to check parity for the address, wherein parity checking is performed only on the set of address lines used to represent the address if the address is within a supported address space, and a subset of the set of address lines if the address is outside the supported address space.