Patent ID: 6847229
Filing Date: 2005-01-25
Classification: H03K

Abstract:
1. A configurable logic element (CLE) for a programmable logic device (PLD), the CLE comprising: a plurality of data input terminals comprising first, second, and third sets of data input terminals; a programmable multiplexer having first and second sets of input terminals coupled respectively to the first and second sets of data input terminals, and further having output terminals; a read decoder having input terminals coupled to the third set of data input terminals and further having output terminals; a memory array having a plurality of input terminals coupled to the plurality of data input terminals, a plurality of address terminals coupled to the output terminals of the read decoder, and a plurality of output terminals; and an output multiplexer having a plurality of input terminals coupled to the output terminals of the memory array, a plurality of control terminals coupled to the output terminals of the programmable multiplexer, and a first output terminal.