Patent ID: 7493498
Filing Date: 2009-02-17
Classification: G06F

Abstract:
1. A processor adapted for coupling to a memory, the processor being capable of operating at one of a plurality of input/output (I/O) privilege levels, the processor comprising: an execution unit configured to execute I/O instructions; a memory management unit (MMU) configured to store data in the memory; and a bus interface unit (BIU) coupled to receive an input/output (I/O) port number and a security context identification (SCID) value, wherein the I/O port number indicates a number of an input/output (I/O) port referenced by an I/O instruction, wherein the SCID value indicates a security context level of a memory location including the I/O instruction and one of a plurality of input/output (I/O) permission bitmaps stored within the memory, and wherein the SCID value is determined independently of the I/O instruction stored in the memory location, wherein the BIU is configured to use, in response to receiving an enable signal indicating that the I/O instruction is at least as privileged as an operative I/O privilege level being used by the processor, the SCID value and the I/O port number to access the input/output (I/O) permission bitmap indicated by the SCID value to obtain a permission bit corresponding to the I/O port, and to produce an output signal dependent upon a value of the permission bit; and wherein the execution unit is coupled to receive the output signal and configured to execute the I/O instruction dependent upon the output signal.