Patent ID: 7272066
Filing Date: 2007-09-18
Classification: G11C

Abstract:
1. A dynamic random access memory device, comprising: an array of memory cells arranged in rows and columns, at least some of the rows containing at least one memory cell that may be unable to retain data bits during refresh; an address decoder receiving row addresses and colunm addresses, the address decoder being operable to activate a row of memory cells corresponding to each received row address and to select a memory cell in a colunm of memory cells corresponding to each received column address; a read data path operable to couple read data from a selected memory cell to in an activated row to a data bus terminal; a write data path operable to couple write data from the data bus terminal to a selected memory cell to in an activated row; a refresh counter operable to increment to generate refresh row addresses during a refresh cycle; a plurality of row address registers each storing a respective subsets of bits of row addresses identifying a row of memory cells containing at least one memory cell that is unable to retain data bits during the refresh cycle; a row address comparator coupled to the row address registers and the refresh counter, the row address comparator being operable to compare each of the stored subsets of bits with corresponding bits of each refresh row address as each refresh row address is generated; and control logic coupled to the array of memory cells and the row address comparator, the control logic being operable in the event of a match between one of the generated refresh row addresses and one of the stored subsets of bits to cause the row of memory cells to be refreshed that corresponds to the row address from which the matching subset of bits were obtained.