Patent ID: 6247119
Filing Date: 2001-06-12
Classification: G06F

Abstract:
An integrated circuit, comprising:a plurality of external connection pins;a processor which executes instructions from an instruction sequence, said processor including an instruction execution pipeline having a plurality of successive stages which correspond to respective successive phases of instruction execution, said pipeline being operative to move instructions of the instruction sequence successively through said stages so that, at each of a plurality of successive points in time, each said stage corresponds to a respective phase of execution of a respective instruction, said stages of said pipeline including a first stage, and including a second stage immediately successive to said first stage; anda flattener register having an output which is coupled to a selected one of said external connection pins, and having an input which is coupled to a signal of said pipeline associated with said first stage, said integrated circuit being operative to cause said register to be loaded from said input based on an instruction being moved from said first stage to said second stage, wherein when that instruction is in said second stage said register maintains the state which the signal had when that instruction was in said first stage wherein a selector having a control input, having first and second inputs, and having an output, said first input of said selector being coupled to said output of said register, said second input of said selector being coupled to a signal of said pipeline, and said output of said selector being coupled to said selected one of said external connection pins, said control input of said selector being coupled to one of said external connection pins other than said selected one of said external connection pins.