Patent ID: 7266016
Filing Date: 2007-09-04
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having memory cells arranged in a matrix form, a clamp circuit connected between one-side ends of first and second bit lines which are adjacent in the memory cell array and first and second wirings to which first and second bias voltages are applied and configured to set potentials of the first and second bit lines, a data cache connected to the other ends of the first and second bit lines in the memory cell array, first and second switching elements which selectively divide the first and second bit lines into plural portions, and a control circuit configured to control the data cache, clamp circuit and first and second switching elements, the control circuit charges part of one of the first and second bit lines to which a memory cell of an address to be written is connected and which is divided by a corresponding one of the first and second switching elements by use of one of the clamp circuit and data cache and discharges and shields the other bit lines by use of the clamp circuit.