Patent ID: 8219756
Filing Date: 2012-07-10
Classification: G06F,Y02D

Abstract:
1. A system, comprising: an L1 instruction cache, wherein the L1 instruction cache includes a plurality of lines of data, wherein each line of data includes one or more instructions; and a tagless hit instruction cache, wherein the tagless hit instruction cache stores a subset of the lines of data in the L1 instruction cache, wherein each line of data stored in the tagless hit instruction cache is stored with respective dynamically adjustable metadata indicative of whether a next instruction is guaranteed to reside in the tagless hit instruction cache, the metadata comprising first metadata indicative of whether a target instruction for a transfer of control instruction is guaranteed to reside in the tagless hit instruction cache and second metadata indicative of whether a next sequential line of data is guaranteed to reside in the tagless hit instruction cache, wherein an instruction fetcher is arranged to have direct access to the L1 instruction cache and the tagless hit instruction cache, and wherein the tagless hit instruction cache is arranged to have direct access to the L1 instruction cache, and wherein upon each actual miss that occurs when an instruction is fetched by the instruction fetcher from the L1 instruction cache but not already stored in the tagless hit instruction cache, a current line of data associated with the fetched instruction is stored in the tagless hit instruction cache.