Patent ID: 6321361
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A process for detecting errors in a high-speed serial-parallel communication port (10.sup.0) between a parallel bus (L2CB, C2LB) and a serial link of an integrated circuit, the communication port (10.sup.0) comprising a sending part (40) and a receiving part (41), the sending part having at least one buffer (TDBUF) for data to be transmitted issuing from the parallel bus, the receiving part (41) having at least one buffer (RDBUF) for data to be received, whereas the sending part (40) inserts each message or data set into a frame of control characters that convey information on the messages in question, and codes the characters of the messages at the bit level, and the receiving part (41) performs a complete verification of the messages before the message is written into the receiving buffer or buffers (RDBUF), characterized in that the buffers of the sending (40) and receiving (41) parts (TDBUF, RDBUF) of communication port (10.sup.0) are equal in number and are used synchronously and cyclically, the process comprising:a first step for on-the-fly consistency checking of messages at the level of coding of the messages into bits,a second step for on-the-fly consistency checking of a character stream constituting the messages,a third step for on-the-fly checking that the buffers of the sending (40) (TDBUF) and receiving (41) (RDBUF) parts are being used synchronously and cyclically, anda fourth step for on-the-fly checking of message data by calculating a cyclic redundancy check (CRC) code on all the data of each message to be transmitted.