Patent ID: 8796836
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A semiconductor device package, comprising: an interposer substrate comprising a dielectric member, a plurality of terminals proximate and extending along at least one peripheral edge thereof on one side thereof and an array of lands proximate and extending along a same at least one peripheral edge on an opposing side of the interposer substrate, terminals of the plurality of terminals being respectively electrically connected to lands of the land array through conductive via structures extending through the dielectric member, the interposer substrate further comprising a two-dimensional array of pads substantially centrally located on the opposing side of the interposer substrate, and wherein the terminals of the plurality of terminals that are respectively electrically connected to lands of the array of lands are respectively electrically connected to pads of the two-dimensional pad array; at least one electrical component mechanically and electrically connected to the interposer substrate through pads of the two-dimensional pad array; at least one semiconductor die mounted by a back side thereof to the one side of the interposer substrate, the at least one semiconductor die comprising a plurality of bond pads on an active surface opposite the back side thereof, the plurality of bond pads proximate and extending along at least one peripheral edge thereof adjacent the at least one peripheral edge of the interposer substrate, bond pads of the plurality of bond pads being respectively electrically connected to the plurality of terminals; an encapsulant structure disposed over the at least one semiconductor die and the one side of the interposer substrate; and a lead frame comprising a plurality of lead fingers having inner ends respectively disposed over lands of the land array on the opposing side of the interposer substrate and mechanically and electrically connected to respective lands of the land array thereunder.