Patent ID: 8929500
Filing Date: 2015-01-06
Classification: H03L,H04L

Abstract:
1. A method of clock-data recovery with out-of-lock detection, comprising: receiving a received data signal corresponding to data transmitted with an embedded clock; performing frequency and phase acquisition cycles to generate, from the received data signal, a recovered clock signal corresponding in frequency and phase to the embedded clock; generating, from the received data signal and the recovered clock signal, a recovered data signal with positive and negative edges retimed by a predetermined amount relative to corresponding positive and negative edges of the received data signal; sampling the recovered data signal with positive and negative edges of the received data signal, and generating an edge detection signal indicating for at least some of the samples whether a corresponding edge of the recovered data signal is detected; and signaling an out-of-lock condition if the edge detection signal indicates failure to detect a predetermined number of edges of the recovered data signal.