Patent ID: 8253462
Filing Date: 2012-08-28
Classification: H03K

Abstract:
1. A duty cycle correction method, comprising the steps of: (A) detecting a first relative delay time of a first input signal relative to a second input signal and a second relative delay time of the second input signal relative to the first input signal, wherein the first input signal and the second input signal are a pair of differential signals, the first relative delay time and the second relative delay time respectively correspond to a high-level period of the first and second input signals and a low-level period of the first and second input signals, and a sum of the first relative delay time and the second relative delay time is equal to a cycle of the first input signal and the second input signal; (B) generating a feedback control signal by accumulating time errors of the high-level period of the first and second input signals, and the low-level period of the first and second input signals; (C) the feedback control signal adjusting the first relative delay time and the second relative delay time for equating the first relative delay time to the second relative delay time; and (D) after step (C), generating an output signal with a duty ratio of 1:1 by synthesizing two rising or falling signals with the same time intervals into just one path.