Patent ID: 6078536
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A packet type integrated circuit memory device having a plurality of pins and a memory array, wherein the packet type integrated circuit memory device operates in a direct test mode, wherein data is stored in and retrieved from the memory array in response to direct test mode packets that include data, address and control information applied to the pins of the packet type integrated circuit memory device in the direct test mode, the packet type integrated circuit memory device comprising:a plurality of first pins, selected from the plurality of pins on the packet type integrated circuit memory device, assigned to a plurality of internal data signals in the packet type integrated circuit memory device that provide the data information from the direct test mode packet to the memory array in direct test mode; anda plurality of second pins, selected from the plurality of pins on the packet type integrated circuit memory device, assigned to a plurality of internal address signals in the packet type integrated circuit memory device that provide the address information from the direct test mode packet to the memory array in direct test mode, wherein none of the pins included in plurality of first pins are included in the plurality second of pins.