Patent ID: 7101755
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. A method for processing a semiconductor device comprises: providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate; stripping the pad nitride; depositing an array top oxide layer over the semiconductor device; planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area; forming a wordline stack comprising a polysilicon-layer, a gate conductor and an insulator-formed sequentially on the array top oxide; and etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.