Patent ID: 9214473
Filing Date: 2015-12-15
Classification: G02F,G09G,H01L

Abstract:
1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor and a fourth transistor; wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein a gate of the first transistor is electrically connected to the first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the third transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein a gate of the third transistor is electrically connected to a third wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring, wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor, and wherein at least one of a ratio of a channel width to a channel length of the second transistor and a ratio of a channel width to a channel length of the third transistor is higher than a ratio of a channel width to a channel length of the first transistor.