Patent ID: 7124170
Filing Date: 2006-10-17
Classification: G06F,G06Q,H04L

Abstract:
1. A secure processing unit comprising: an internal memory unit; a processor; tamper detection and response logic; an interface to external systems or components; one or more buses for connecting the internal memory unit, the processor, the tamper detection and response logic, and the interface to external systems and components; a memory management unit; a level-one page table, the level-one page table including a plurality of level-one page table entries, wherein the level-one page table entries each correspond to at least one level-two page table, and wherein the level-one page table entries each contain a predefined attribute, the predefined attribute being operable to indicate to the memory management unit whether entries in a corresponding level-two page table may designate certain predefined memory regions; a plurality of processor security registers; access control data, the access control data being operable to indicate whether access to predefined memory regions is restricted to certain software components or processor modes, wherein the access control data are stored in a critical address register, the critical address register comprising one of the processor security registers; and a tamper-resistant housing.