Patent ID: 8700886
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A processor comprising: memory circuitry; and processing circuitry coupled to the memory circuitry and configured to retrieve operation codes from the memory circuitry and to decode said operation codes to produce corresponding instructions for execution by the processing circuitry; wherein the processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given one of the instructions, that same instruction thereby being produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded; wherein the first and second operation codes each correspond only to the given one of the instructions; and wherein the given one of the instructions corresponds to a set of one or more signals associated with one or more execution operations in the processor.