Patent ID: 6356157
Filing Date: 2002-03-12
Classification: H03L

Abstract:
A Phase Locked Loop circuit, comprising:a first phase comparator for detecting the phase difference between a feedback signal and an input reference signal, and outputting a first compare signal including a first phase lead detection signal and a first phase lag detection signal, said first phase lead and said first phase lag detection signals indicating when said phase difference is not within a dead zone of said first comparator; a second phase comparator for detecting the phase difference between said feedback signal and said reference signal, and outputting a second compare signal including a second phase lead detection signal and a second phase lag detection signal, said second phase lead and second phase lag detection signals indicating a when said phase difference is not within a dead zone that is wider than said dead zone of said first phase comparator; a supplier, receiving said first and second compare signals, that judges that said phase difference is large when both of said first and second comparators recognize that said phase difference is not within a dead zone of said first and second comparators, and that judges that said phase difference is small when said first comparator recognizes that said phase difference is not within a dead zone of said first comparator and said second comparator recognizes that said phase difference is within a dead zone of said second comparator; an output signal generator for generating an output signal, for outputting said output signal to said first and second phase comparator as said feedback signal, and for modifying the phase of said output signal in accordance with the judgment of said supplier wherein said supplier supplies either a positive current or a negative current in accordance with the polarity of said phase difference and connects at least one of a power line and a ground line to a current output terminal; wherein said power line and said current output terminal are connected via a first impedance when said first phase lead detection signal and said second phase lead detection signal are inputted and are connected via a second impedance, higher than said first impedance, when only said first phase lead detection signal is inputted; and wherein said ground line and said current output terminal are connected via a third impedance when said first phase lag detection signal and said second phase lag detection signal are inputted, and via a fourth impedance, higher than said third impedance, when only said second phase lag detection signal is inputted, wherein said supplier comprises: a first transistor, wherein a control electrode inputs said first phase lead detection signal, a main electrode of the one side is connected to said power line, and a main electrode of the other side is connected to said current output terminal by way of a first resistor; a second transistor, wherein a control electrode inputs said first phase lag detection signal, a main electrode of the one side is connected to said ground line, and a main electrode of the other side is connected to said current output terminal by way of a second resistor; a third transistor, wherein a control electrode inputs said second phase lead detection signal, a main electrode of the one side is connected to said power line, and a main electrode of the other side is connected to said current output terminal by way of a third resistor; and a fourth transistor, wherein a control electrode inputs said second phase lag detection signal, a main electrode of the one side is connected to said ground line, and a main electrode of the other side is connected to said current output terminal by way of a fourth resistor.