Patent ID: 7492653
Filing Date: 2009-02-17
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a global I/O line for transferring data between an external circuit and a local I/O line; an I/O sense amplifier for controlling a data transmission between the local I/O line and the global I/O line; and an I/O sense amplifier control unit for controlling the I/O sense amplifier in response to a test mode signal in order to test the semiconductor memory device, independent of the data outputted from a memory cell, wherein the I/O sense amplifier control unit includes: an I/O sense amplifier driving signal generating unit for producing an I/O sense amplifier driving signal in response to an internal read signal and a bank select signal; and an I/O sense amplifier driving signal control unit for controlling the I/O sense amplifier driving signal in response to the test mode signal.