Patent ID: 9164951
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A multiprocessor system comprising: one or a plurality of main processors and a plurality of sub-processors which execute a command issued; and an execution control circuit which conducts execution control of each said plurality of sub-processors, wherein said execution control circuit comprising a control bus output unit which outputs said command to each any of said plurality of sub-processors, a status bus input unit which inputs a status notification indicative of a processing state of a command issued to each said plurality of sub-processors from each said plurality of sub-processors, a determination circuit which determines whether or not said status notification that is input from a sub-processor to which a first command is issued among said plurality of sub-processors and that is indicative of a processing state of said first command has one-to-one dependency with a second command to be issued next on an operation sequence, a status accelerator which issues said second command to said control bus output unit when the state notification is determined to have said dependency, a status FIFO control unit which stores said status notification when determination is made that said dependency fails to exist, and an execution control processor which executes predetermined analysis by using said status notification stored to issue a third command to said control bus output unit.