Patent ID: 6936891
Filing Date: 2005-08-30
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory device comprising: a substrate; a plurality of first gate electrodes extending parallel to one another along a first direction in a memory cell array area on the substrate and a plurality of second gate electrodes extending parallel to one another along a second direction in said memory cell array area intersecting said first direction; and a plurality of diffusion regions, each provided in a substrate surface of each of a plurality of areas, herein termed divisions, which are demarcated by said plural first gate electrodes and by said plural second gate electrodes in said memory cell area in a matrix configuration; wherein each cell, in said memory cell array, having said first gate electrode and said second gate electrode as a gate structure includes an insulating film provided below said gate electrodes, said insulating film having two storage nodes, being spaced apart in association with the diffusion regions of two of said divisions lying on both sides of said gate electrodes; and wherein each division having four sides defined by said two neighboring first gate electrodes and by said two neighboring second gate electrodes, and each cell having four storage nodes having a total storage capacity of independently accessible four bits.