Patent ID: 7400016
Filing Date: 2008-07-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a surface; a gate electrode as formed over the surface of said semiconductor substrate with a gate dielectric film sandwiched there between; a pair of source and drain diffusion layers formed in said semiconductor substrate to oppose each other with a channel region laterally interposed there between at a location immediately beneath said gate electrode; a first impurity doped layer of a first conductivity type formed in said channel region between the source/drain diffusion layers; a second impurity doped layer of a second conductivity type formed under said first impurity doped layer and the source and drain diffusion layers; and a third impurity doped layer of the first conductivity type formed under said second impurity doped layer, wherein said first impurity doped layer is equal to or less in junction depth than said source/drain diffusion layers, and wherein said second impurity doped layer is determined in impurity concentration and thickness causing a depth of its junction with said third impurity doped layer to be greater than a junction depth of said source/drain diffusion layers while permitting said second impurity doped layer to be fully depleted due to a built-in potential creatable between said first and third impurity doped layers, and wherein said source/drain diffusion layers each comprise a low resistivity region and an extension region being formed to extend from this low resistivity region toward said channel region and being lower in impurity concentration and shallower in depth than said low resistivity region, said low resistivity region having a bottom surface residing within said second impurity doped layer.