Patent ID: 6324496
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A computer-implemented method for testing a hierarchical state machine that models flow of control within a real system, comprising the steps of:(I) providing the hierarchical state machine for the real system; and(II) performing model checking on the hierarchical state machine, wherein the real system is a circuit or a computer program and the model checking is applied to the hierarchical state machine without first flattening the hierarchical state machine, wherein the hierarchical state machine is a finite state machine comprising a plurality of states, wherein at least two of the states are multiple instances of a single state machine and the model checking comprises comparison of the hierarchical state machine against at least one correctness requirement to determine whether the hierarchical state machine satisfies the at least one correctness requirement, wherein, during the model checking, each state machine having multiple instances in the hierarchical state machine is analyzed fewer times than its number of instances in the hierarchical state machine using cyclic temporal logic relation.