Patent ID: 7238962
Filing Date: 2007-07-03
Classification: G01R,H01L

Abstract:
1. A semiconductor chip comprising: a plurality of outer edges; a peripheral area located adjacent to the outer edges; and a main circuit area located within the confines of the peripheral area, the main circuit area including integrated circuits, wherein the peripheral area includes chip pads connected to the integrated circuits, a plurality of test pads electrically connected to the integrated circuits for testing electrical properties of the integrated circuits, the respective chip pads and test pads being arranged in first and second pairs of rows at substantially uniform intervals, the first pair of rows being arranged substantially parallel to each other and the second pair of rows being arranged substantially parallel to each other, the first pair of rows being arranged substantially perpendicular to the second pair of rows, the chip pads being arranged in each of the rows adjacent the main circuit area of the semiconductor chip, and the test pads being located within each of the rows of chip pads, and the test pads being substantially the same dimensional size as the chip pads.