Patent ID: 7971171
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. An electromigration analysis method implemented by a computer system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration, comprising: providing at least one interconnect between a driver cell and one or more load cells; applying same extracted netlist data for an electromigration analysis and at least one of the following: a noise analysis and a timing analysis; modeling the driver cell by the computer system by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting by the computer system at least a slew rate of a driver voltage signal and at least one of the following: noise information and timing information from the noise analysis and the timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.