Patent ID: 6614264
Filing Date: 2003-09-02
Classification: H03K

Abstract:
A method of cascading a chain of modified full-rail differential logic circuits comprising:providing a first supply voltage; providing a second supply voltage; providing a first modified full-rail differential logic circuit by the method of: providing a first modified full-rail differential logic circuit out terminal; providing a first modified full-rail differential logic circuit outBar terminal; providing a first modified full-rail differential logic circuit first node; coupling said first modified full-rail differential logic circuit first node to said first supply voltage; providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode; coupling said first modified full-rail differential logic circuit first node to said first transistor first flow electrode; coupling said first transistor second flow electrode to said first modified full-rail differential logic circuit out terminal; providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode; coupling said first modified full-rail differential logic circuit first node to said second transistor first flow electrode; coupling said second transistor second flow electrode to said first modified full-rail differential logic circuit outBar terminal; providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode; coupling said first transistor control electrode to said third transistor first flow electrode and said first modified full-rail differential logic circuit outBar terminal; coupling said second transistor control electrode to said third transistor second flow electrode and said first modified full-rail differential logic circuit out terminal; providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; coupling said fourth transistor first flow electrode to said first modified full-rail differential logic circuit first node; coupling said fourth transistor second flow electrode to said first modified full-rail differential logic circuit out terminal; providing a first clock signal; coupling said fourth transistor control electrode to said first clock signal; providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; coupling said fifth transistor first flow electrode to said first modified full-rail differential logic circuit first node; coupling said fifth transistor second flow electrode to said first modified full-rail differential logic circuit outBar terminal; coupling said fifth transistor control electrode to said first clock signal; providing a second clock signal; coupling a first modified full-rail differential logic circuit sense amplifier circuit between said first modified full-rail differential logic circuit out terminal and said first modified full-rail differential logic circuit outBar terminal, said first modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to said second clock signal; providing a logic block, said logic block comprising: at least one logic block input terminal; a logic block out terminal; and a logic block outBar terminal; coupling said logic block out terminal to said first modified full-rail differential logic circuit out terminal; coupling said logic block outBar terminal to said first modified full-rail differential logic circuit outBar terminal; providing a second modified full-rail differential logic circuit by the method of: providing a second modified full-rail differential logic circuit out terminal; providing a second modified full-rail differential logic circuit outBar terminal; providing a second modified full-rail differential logic circuit first node; coupling said second modified full-rail differential logic circuit first node to said first supply voltage; providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode; coupling said second modified full-rail differential logic circuit first node to said first transistor first flow electrode; coupling said first transistor second flow electrode to said second modified full-rail differential logic circuit out terminal; providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode; coupling said second modified full-rail differential logic circuit first node to said second transistor first flow electrode; coupling said second transistor second flow electrode to said second modified full-rail differential logic circuit outBar terminal; providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode; coupling said first transistor control electrode to said third transistor first flow electrode and said second modified full-rail differential logic circuit outBar terminal; coupling said second transistor control electrode to said third transistor second flow electrode and said second modified full-rail differential logic circuit out terminal; providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; coupling said fourth transistor first flow electrode to said second modified full-rail differential logic circuit first node; coupling said fourth transistor second flow electrode to said second modified full-rail differential logic circuit out terminal; coupling said fourth transistor control electrode to said second clock signal; providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; coupling said fifth transistor first flow electrode to said second modified full-rail differential logic circuit first node; coupling said fifth transistor second flow electrode to said second modified full-rail differential logic circuit outBar terminal; coupling said fifth transistor control electrode to said second clock signal; providing a third clock signal; coupling a second modified full-rail differential logic circuit sense amplifier circuit between said second modified full-rail differential logic circuit out terminal and said second modified full-rail differential logic circuit outBar terminal, said second modified full-rail differential logic circuit sense amplifier circuit having an input terminal; coupling said second modified full-rail differential logic circuit sense amplifier circuit input terminal to said third clock signal; providing a logic block, said logic block comprising: at least one logic block input terminal; a logic block out terminal; and a logic block outBar terminal; coupling said logic block out terminal to said second modified full-rail differential logic circuit out terminal; coupling said logic block outBar terminal to said second modified full-rail differential logic circuit outBar terminal; delaying said second clock signal with respect to said first clock signal by a predetermined delay time; and delaying said third clock signal with respect to said second clock signal by a predetermined delay time.