Patent ID: 8381012
Filing Date: 2013-02-19
Classification: G06F

Abstract:
1. A method of fault-tolerant clocking comprising the steps of: generating, by a first process controller, a first digital data value; receiving the first digital data value, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating a first output clock signal of a predetermined frequency by the master clock synthesizer circuit by converting the first digital data value to the first output clock signal at a conversion rate determined by the first clock signal; receiving the first output clock signal of the master clock synthesizer circuit and a second clock signal in a slave clock synthesizer circuit; generating a second output clock signal by the slave clock synthesizer circuit in response to the first output clock signal of the master clock synthesizer circuit and the second clock signal; and transmitting the second output clock signal of the slave clock synthesizer circuit to the master clock synthesizer circuit as the first input reference signal.