Patent ID: 9190141
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A data entry valid circuit for performing a reset operation on a plurality of static random access memory (SRAM) bitcells in a SRAM, comprising: a power collapsing circuit configured to collapse power supplied by a power supply to a plurality of SRAM bitcells in a SRAM from an operational power level to a collapsed power level lower than the operational power level in response to receiving a reset input; and a biasing circuit configured to apply a voltage or current bias to the plurality of SRAM bitcells in response to receiving the reset input; the power collapsing circuit further configured to restore the power supplied by the power supply to the plurality of SRAM bitcells from the collapsed power level to the operational power level while the voltage or current bias is applied by the biasing circuit to the plurality of SRAM bitcells to cause the plurality of SRAM bitcells to reset to a desired state.