Patent ID: 6048765
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A method of fabricating buried bit line flash EEPROM with a trench floating gate on a silicon substrate comprising the steps of:forming a first dielectric layer on said silicon substrate;forming a second dielectric layer with a first conductivity type dopant on said first dielectric layer;forming an antireflection layer on said second dielectric layer;coating a patterned mask on said antireflection layer to define a plurality of buried bit line regions;forming a plurality trenches using said patterned mask as a mask;removing said patterned mask;performing an oxidation process to grow an oxynitride layer on said trenches and form buried bit line;forming a silicon layer to refill said plurality of trenches;performing a planarization process to said first silicon layer to form a plain surface using said antireflection layer as an etching stopping layer;forming a stacked ONO layer as an interpoly dielectric layer; andforming a polysilicon layer on said stacked ONO layer to define word lines.