Patent ID: 8368447
Filing Date: 2013-02-05
Classification: H03L

Abstract:
1. A delay lock loop circuit, for generating a locked signal, comprising: a phase detector, for receiving a clock signal and the locked signal, and generating a phase detecting result by detecting a phase difference between the clock signal and the locked signal; a first voltage controlled delay chain, coupled to the phase detector, for receiving the clock signal and a first control signal, and generating a first delayed signal by delaying the clock signal according to the first control signal; a second voltage controlled delay chain, coupled to the phase detector, for receiving the clock signal and a second control signal, and generating a second delayed signal by delaying the clock signal according to the second control signal; a charge pump, coupled to the phase detector, the first and the second voltage controlled delay chains, for receiving the phase detecting result and generating the first and the second control signals according to the phase detecting result; and a duty cycle detection pump, coupled to the charge pump and the first and the second voltage controlled delay chains, for receiving the first and the second delayed signals and controlling a voltage level of the second control signal according to the first and the second delayed signals.