Patent ID: 9122839
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A method comprising: identifying a plurality of first standard cells having first devices within a description of a part of a layout of an integrated circuit (IC) that satisfies a first specification value, wherein the IC is patterned using a set of masks; identifying timing paths that connect respective groups of first standard cells within the plurality of standard cells; selecting a subset of the timing paths including a subset of the plurality of first standard cells; and generating data for forming an additional mask, wherein a modified IC that satisfies a second specification value is to be patterned using the set of masks and the additional mask, and the additional mask changes a process step performed using one of the set of masks to form the second devices in place of the first devices in the subset of the plurality of first standard cells, wherein a computer is used to perform at least one of the steps of identifying a plurality of first standard cells, identifying timing paths, selecting or generating.