Patent ID: 7464198
Filing Date: 2008-12-09
Classification: G06F

Abstract:
1. A method for programming a DMA controller of a system on a chip, the system on a chip including a central processing unit, a memory management unit for translating virtual addresses into physical addresses according to a translation table which also contains the size of each page, a hardware contiguity checking module for checking contiguity, an address bus, a data bus, and the DMA controller, the DMA controller being programmable by applying, to at least one of the data bus and the address bus, programming elements comprising a source physical address, a destination physical address and a size for the data to be transferred, each user program being linked to a virtual address space and a physical memory space, organized in pages, and each address including high-order bits indicating a page associated with the address, the method comprising the steps of: in response to dedicated instructions of a user program that deliver size information and a programming virtual address, which is a source virtual address or a destination virtual address, supplying, from the central processing unit, a transfer size to the hardware contiguity checking module and the programming virtual address to the memory management unit and the hardware contiguity checking module; translating, by the memory management unit, the programming virtual address into a corresponding programming physical address; supplying, from the memory management unit, the corresponding programming physical address to the hardware contiguity checking module; determining, by the hardware contiguity checking module, a first discontinuity as a function of the transfer size supplied by the central processing unit and the corresponding programming physical address supplied by the memory management unit and stored in the translation table; determining, by the hardware contiguity checking module, at least a first sub-block formed by a memory sub-space without discontinuity identified by a start physical address equal to the programming physical address and an end physical address equal to the physical address immediately preceding the first discontinuity in a part of the physical memory space corresponding, according to the translation table, to the part of the virtual address space beginning at the programming virtual address and of a size equal to the size information delivered by the user program; defining at least a DMA transfer size for the DMA controller as a function of at least the first sub-block; and delivering programming elements including the DMA transfer size to the DMA controller by applying the programming elements to at least one of the address bus and the data bus, the DMA transfer size being coupled from the hardware contiguity checking module to the data bus, wherein the hardware contiguity checking module is coupled between the central processing unit and the memory management unit.