Patent ID: 7848161
Filing Date: 2010-12-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising memory cell arrays arranged at least in a row direction, the memory cell arrays each including a plurality of memory cells arranged in a row direction and a column direction, the memory cells each having a variable resistance element for storing information by a change of an electric resistance, a plurality of data lines extending in the row direction, and a plurality of bit lines extending in the column direction, in which one end of the variable resistance element of each of the memory cells in the same row is connected to a common data line, and the other end of the variable resistance element of each of the memory cells in the same column is connected to a common bit line, wherein a plurality of main data lines for supplying a predetermined data line voltage to each of the corresponding data lines of the memory cell arrays arranged in the row direction extend in the row direction, the main data lines are connected to the corresponding data lines through respective data line selection transistors in the memory cell array, and the number of the data lines of the memory cell array is equal to the maximum number of the memory cells to be programmed simultaneously in one programming action.