Patent ID: 8867300
Filing Date: 2014-10-21
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more); a page selection circuit configured to select a row in the block array as a page to be selected; and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page, wherein each of the memory blocks comprising: a memory cell array having a plurality of memory cells; a row selection circuit configured to select a row of the memory cell array; and a column selection circuit configured to select a column of the memory cell array, wherein when a row-specifying command and a row address are given, a group of memory cells of a specific row corresponding to the given row address is selected for each of the n number of memory blocks aligned in the column direction in the block array, when a column-specifying command and a column address are given, a group of memory cells of a specific column corresponding to the given column address is selected for each of the m number of memory blocks aligned in the row direction in the block array, and when the page selection circuit is given a per-page read or write command and the corresponding page address, the page selection circuit simultaneously selects a plurality of memory cells separated from one another in a page indicated by the given page address among a group of memory cells selected by a row-specifying command, a row address, a column-specifying command and a column address that are given just before the per-page read or write command and the corresponding page address.