Patent ID: 6803658
Filing Date: 2004-10-12
Classification: H01L,H05K

Abstract:
A wiring substrate having a main surface, a back surface, and a plurality of top-flattened solder bumps projecting from the main surface, said substrate comprising:a core substrate; a solid layer formed on the core substrate and partially covering the core substrate; at least one resin dielectric layer formed on the solid layer and the core substrate; a plurality of pads formed on the resin dielectric layer and exposed at the main surface of the wiring substrate, the pads including first pads located within a region above the solid layer and second pads located outside of said region; and first top-flattened solder bumps formed on the corresponding first pads and including a top face having a diameter, second top-flattened solder bumps formed on the corresponding second pads and including a top face having a diameter, the diameter of the top face of each of the first top-flattened solder bumps being substantially equal to the diameter of the top face of each of the second top-flattened solder bumps.