Patent ID: 6891271
Filing Date: 2005-05-10
Classification: H01L

Abstract:
1. A semiconductor device comprising a memory region in which non-volatile memory devices are arranged in a matrix of rows and columns to form a memory cell array, wherein: each of the non-volatile memory devices has a word gate formed over a semiconductor layer with a first gate insulating layer interposed, an impurity layer formed in the semiconductor layer to form a source region or a drain region, and sidewall-shaped first and second control gates formed on the opposite sides of the word gate; each of the first and second control gate faces the semiconductor layer with a second gate insulating layer interposed, and also faces the word gate with a side insulating layer interposed; the first and second control gates extend in a first direction; the first and second control gates adjacent to each other in a second direction intersecting the first direction with the impurity layer interposed are connected to a common contact section; the common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer; the second contact conductive layer is continuous with the first and second control gates and disposed inside the first contact conductive layer; and the third contact conductive layer is disposed over the first and second contact conductive layers.