Patent ID: 8344759
Filing Date: 2013-01-01
Classification: G11C,H03K

Abstract:
1. A track and hold circuit, comprising; a first switch device including a first MOS transistor, the first MOS transistor having a gate terminal, an input terminal, and an output terminal, the gate terminal being configured to receive a control voltage; a capacitive hold device electrically coupled to the output terminal of the first MOS transistor; and a track-voltage generating device coupled to the first switch device, the track-voltage generating device being configured to generate the control voltage based on a signal on the input terminal of the first MOS transistor and to supply the control voltage to the gate terminal of the first MOS transistor during track phases, the control voltage providing a channel charge to the first MOS transistor that is the same for each track phase, the track-voltage generating device including a second MOS transistor having a drain terminal and a source terminal that are shorted together, the second MOS transistor being configured to be charged with a predetermined electrical charge during a hold phase and to generate the control voltage during the track phases by redistributing a predetermined fraction of the predetermined charge to the first MOS transistor.