Patent ID: 6373737
Filing Date: 2002-04-16
Classification: G06F,G11C

Abstract:
A content addressable memory, comprising:a random access memory, organized as a plurality of rows having a preselected number of bits, each row selectable by a row address; a counter for sequentially generating row addresses to be presented to the random access memory; a register for storing an input value to be compared to the rows of said memory, said register having a number of bits equal to the number of bits in each random access memory row; a single comparator for comparing, in sequence, each selected row with the value stored in said register, wherein said comparator compares a row and the value stored in said register in a single step, and for generating a signal indicative of whether a match occurs; and means connected to said comparator for storing the row addresses generated by the counter for each row which causes a signal indicative of a match to be generated.