Patent ID: 7079966
Filing Date: 2006-07-18
Classification: G01N,H01L

Abstract:
1. A method of qualifying a process tool comprising steps of: (a) finding a plurality of pre-scan defect locations on a surface of a semiconductor wafer; (b) subjecting the semiconductor wafer to processing by a process tool after step (a); (c) finding a plurality of post-scan defect locations on the surface of the semiconductor wafer after step (b); (d) calculating which defects were added by the process tool from the pre-scan defect locations and the post-scan defect locations; (e) displaying a scatter plot of a point representative of a total number of defects added by the process tool to the semiconductor wafer; and (f) selecting the point on the scatter plot to initiate a display of one of a pre-test wafer map, a post-test wafer map, and an added defect map of defects added by the process tool to the semiconductor wafer.