Patent ID: 6636165
Filing Date: 2003-10-21
Classification: H03H

Abstract:
A device for converting an input digital signal sequence (Sin) with an input sampling rate (fin) into an output digital signal sequence (Sout) with an output sampling rate (fout), comprising:an estimator which estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and estimates a set point phase (&PHgr;set,k) of the output signal sequence (Sout) in observation intervals being variable in observation length; a controlling system which is connected to the estimator and compares an actual phase (&PHgr;actual,k) of the output signal sequence (Sout) with the set point phase (&PHgr;set,k) of the output signal sequence (Sout) and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and a deviation (&Dgr;&PHgr;k) of the actual phase (&PHgr;actual,k) from the set point phase (&PHgr;set,k); and an interpolator which interpolates the input signal sequence (Sin) for generating the output signal sequence (Sout) at sampling times (tâ€²1, tâ€²2, . . . , tâ€²6), the sampling times (tâ€²1, tâ€²2, . . . , tâ€²6) having a position in time being predetermined by the control signal (RTC,k).