Patent ID: 9155202
Filing Date: 2015-10-06
Classification: G11C,H01L,H05K,Y10T

Abstract:
1. A layout for a printed circuit, comprising: a first layout consisting essentially of a first plurality of features, each of the first plurality of features being orthogonal or parallel to every other feature in the first plurality of features, the first plurality of features comprising (i) first print-compatible shape features and (ii) first and second subsets of features; and a second layout consisting essentially of a second plurality of features, each of the second plurality of features being orthogonal or parallel to every other feature in the first and second plurality of features, the second plurality of features comprising (i) second print-compatible shape features, (ii) a first subset that crosses over the first subset of the first plurality of features, and (iii) a second subset that crosses over the second subset of the first plurality of features.