Patent ID: 6204715
Filing Date: 2001-03-20
Classification: H03F

Abstract:
A signal amplifying circuit comprising:a first capacitor having a first end adapted for connection to a signal source and a second opposite end;a field effect transistor (FET) having a gate connected to said second end of said first capacitor, one of a drain and a source adapted for connection to a reference potential and an opposite one of said drain and a source defining a circuit output; anda first diode having a cathode connected to said gate and an anode connected to said one of a drain and a source adapted for connection to a reference potential, said first capacitor and said first diode establishing a positive bias at said gate of said FET with respect to said reference potential when an input signal at said first end of said first capacitor is negative with respect to said reference potential to thereby prevent clipping of an output signal provided by said FET at said circuit output.