Patent ID: 7554848
Filing Date: 2009-06-30
Classification: G11C

Abstract:
1. A method of programming a selected memory cell of a non-volatile memory, the memory comprising a plurality of memory cells formed upon a substrate and arranged into a plurality of columns connected along respective bit lines each comprising a number of said memory cells connected in series between a drain side select transistor through which the memory cells are connected to a corresponding bit line and a source side select transistor, whereby the memory cells form a corresponding number of rows with the memory cells of each row are connected along the same word line, and wherein the columns are subdivided into a plurality of distinct subsets, the method comprising: selecting a memory cell for programming, where the selected memory cell belongs to a first of the subsets; setting a first voltage level on the corresponding bit line of the selected memory cell; biasing the source side and drain side select transistors of the subsets, wherein the source side select transistors in the first subset are biased with a different control gate voltage than the source side select transistors in the other subsets; subsequent to setting the voltage level on the corresponding bit line of the selected memory cell and while applying said biasing, applying a programming pulse on the corresponding word line of the selected memory cell.