Patent ID: 6156611
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method of fabricating a vertical FET with sidewall gate electrode comprising the steps of:providing a doped semiconductor substrate with a semiconductor drift layer formed thereon and a semiconductor contact layer formed on the semiconductor drift layer;etching through the semiconductor contact layer into the semiconductor drift layer to form a plurality of parallel, spaced apart elongated mesas, each mesa having an end and an upper surface and each adjacent pair of mesas defining therebetween an elongated trench with substantially vertical sidewalls and a bottom, and defining a gate feed region adjacent the ends of the mesas;conformally depositing a conductive layer over the plurality of mesas and the trenches, including the sidewalls and the bottoms of the trenches;depositing a layer of resist over the conductive layer;removing a portion of the resist to expose portions of the conductive layer on the upper surface of the mesas and the sidewalls and the bottoms of the trenches;anisotropically etching the conductive layer to remove the exposed portions of the conductive layer on the upper surface of the mesas and the bottoms of the trenches so as to leave portions of the conductive layer on the sidewalls of the trenches;removing remaining portions of the resist in the gate feed region;depositing conductive material on the upper surfaces of the mesas and in the gate feed region, and depositing conductive material to connect the portions of the conductive layer on the sidewalls of the trenches to portions of the conductive material in the gate feed region; anddepositing conductive material on a reverse side of the substrate.