Patent ID: 7099010
Filing Date: 2006-08-29
Classification: G01B,G03F,H01L

Abstract:
1. A structure for estimating an overlay accuracy in forming successive material layers on a substrate during the course of manufacture of integrated circuit devices, the structure comprising: a substrate comprised of a semiconductor material having formed thereon a plurality of first and second regions, wherein the first region and the second region differ from each other in at least one of type of material and surface topology, the first and the second regions arranged to form a periodic pattern having a predefined first periodicity along a first direction and along a second direction; and a plurality of third regions, each of which overlies one of said second regions so as to exhibit a predefined second periodicity, with a pitch that is substantially equal to a pitch of said periodic pattern, along the first and the second directions, wherein the size of the first, the second and the third regions is selected so that each third region lies within the respective second region for a given maximum overlay inaccuracy.