Patent ID: 8495543
Filing Date: 2013-07-23
Classification: G06F,H03K

Abstract:
1. A computer-implemented method for designing an asynchronous circuit, the method comprising: using a computer system to generate a design for the asynchronous circuit that operates with a full-buffer, 4-phase handshaking protocol based on an asynchronous circuit template that includes a plurality of asynchronous pipeline stages, wherein each stage comprises (i) a data path including one or more dual-rail logic cells, each cell configured and arranged to receive and convey a token and having a true rail and a false rail, and (ii) a control path including a controller configured and arranged to control the one or more dual-rail logic cells and to communicate with other controllers via a handshaking protocol, wherein each pipeline stage contains dual-rail logic and the pipeline control supports a full-buffer 4-phase protocol with N levels of dual-rail logic, wherein N>1, and wherein the initial N−1 levels of dual-rail logic are configured to evaluate earlier than the last level of dual-rail logic and further comprising designing the circuit template to use a pre-charged completion unit to detect the validity of the dual-rail logic.