Patent ID: 8536925
Filing Date: 2013-09-17
Classification: H03K

Abstract:
1. A voltage translator circuit, comprising: an input stage adapted for receiving an input signal referenced to a first voltage supply; a latch adapted for connection to a second voltage supply and operative to at least temporarily store a logic state of the input signal; a voltage clamp coupled between the input stage and the latch, the voltage clamp being operative to set a maximum voltage across the latch to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level, the voltage translator circuit generating a first output signal at a junction between the latch and the voltage clamp, the voltage translator circuit generating a second output signal at a junction between the voltage clamp and the input stage; and at least first and second output buffers, the first output buffer being operative to receive the first output signal and to generate a first buffered output signal indicative thereof, the second output buffer being operative to receive the second output signal and to generate a second buffered output signal indicative thereof, the first buffered output signal being referenced to the second voltage supply of the voltage translator circuit and to a first bias voltage, the second buffered output signal being referenced to a voltage return of the voltage translator circuit and to a second bias voltage; and wherein the first buffered output signal swings between the second voltage supply of the voltage translator circuit and the first bias voltage, and the second buffered output signal swings between the voltage return of the voltage translator circuit and the second bias voltage.