Patent ID: 8754691
Filing Date: 2014-06-17
Classification: G06F,H03K

Abstract:
1. A method comprising: monitoring a variable global clock signal pulse width; determining whether the variable global clock signal pulse width is within a local evaluation signal pulse width threshold; adjusting the variable global clock signal pulse width to be within the local evaluation signal pulse width threshold if the variable global clock signal pulse width is not within the local evaluation signal pulse width threshold; and producing a first local clock signal from the variable global clock signal by a local clock buffer adapted to receive a variable global clock signal; limiting the first local clock signal pulse width with a pulse width logic control circuit in operable communication with the local clock buffer to be less than the variable global clock signal pulse width during a slow mode; and expanding the first local clock signal pulse width with the pulse width logic control circuit to be greater than the variable global clock signal pulse width during a fast mode, wherein the limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.