Patent ID: 7254062
Filing Date: 2007-08-07
Classification: G11C

Abstract:
1. A bit-line selection circuit for a memory device comprising: a decoding line including a regulated voltage node receiving a regulated voltage and a programming voltage node providing a programming voltage for a cell in the memory device, said decoding line comprising at least one input transistor connected to the regulated voltage node and being controlled by an enable/disable signal; a dummy line identical to said decoding line and being controlled by the enable/disable signal; an equalization circuit connected between said decoding and dummy lines for setting a current in said dummy line equal to a current in said decoding line; and a regulating circuit for regulating the programming voltage generated at the programming voltage node of said decoding line by compensating for differences between the programming voltage and a reference voltage, said regulating circuit having a first input for receiving the reference voltage, a second input for receiving a sensed voltage on the programming voltage node in said dummy line, and an output for providing the enable/disable signal.