Patent ID: 6848090
Filing Date: 2005-01-25
Classification: G06F

Abstract:
1. A method for abstracting a precharged latch, comprising: accessing a logic level representation of a structure, said logic level representation comprising a data node, and a clock node for receiving a clock signal, said clock signal having multiple phases; deriving a first resultant cofactor based upon said logic level representation and a first phase of said clock signal; determining whether said first resultant cofactor indicates: (1) a first node of said logic level representation experiencing a precharge; and (2) a second node of said logic level representation maintaining a previous logic value; in response to an affirmative determination, concluding that said second node is a precharged latch candidate; deriving a second resultant cofactor based upon said logic level representation and a second phase of said clock signal; determining whether said second resultant cofactor is devoid of a feedback loop; and in response to an affirmative determination, abstracting said structure as a precharged latch.