Patent ID: 6933226
Filing Date: 2005-08-23
Classification: H01L

Abstract:
1. A method of forming gates in a semiconductor device having a non-linear top profile, the method comprising the steps of: forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device; depositing a dummy gate polysilicon layer on the dummy gate insulating layer; depositing a hard mask layer on the dummy polysilicon layer; patterning the hard mask layer into a mask pattern; forming a plurality of dummy gates by patterning the dummy gate polysilicon layer and the dummy gate insulating layer using the mask pattern as an etch barrier, forming a spacer at each of the two sidewalls of each of the dummy gate; depositing an insulating interlayer on the resultant structure after forming the spacers; performing a non-linear planarization by performing chemical mechanical polishing (CMP) process to polish away the insulating interlayer formed above the mask patterns and the mask patterns, exposing the patterned dummy gate polysilicon layer of each dummy gate, forming a damascene structure by removing the patterned dummy gate polysilicon and insulating layers using the insulating interlayer as another etch barrier; and depositing a gate insulating layer and a gate metal layer on the entire surface of the semiconductor substrate having the damascene structure.