Patent ID: 7238569
Filing Date: 2007-07-03
Classification: H01L

Abstract:
1. A method of fabricating an array source line structure in a wafer of a NAND flash memory, comprising: forming a first dielectric layer and a charge trapping layer of a multi-layer dielectric-charge trapping-dielectric stack over a substrate and an STI of the wafer; implanting an ion species in an array source line region, to unite the array source line structure to a source/drain region; forming a second dielectric layer over the charge trapping layer of the multi-layer dielectric-charge trapping-dielectric stack, and forming a high-dielectric material layer over the second dielectric layer; removing the high-dielectric material layer and the multi-layer dielectric-charge trapping-dielectric stack in the array source line region, thereby defining a local interconnect opening in the multi-layer dielectric-charge trapping-dielectric stack and the high-dielectric material layer in the array source line region of the wafer; forming a polysilicon layer over the wafer, thereby filling the local interconnect opening with polysilicon; selectively removing the polysilicon layer and the high-dielectric material layer, thereby concurrently defining wordline and select drain gate structures in bitline contact regions, and select source gate structures and source line structures in source line regions of the wafer; and implanting an ion species through the openings in the polysilicon layer and the high dielectric material layer to form the source/drain regions in the bitline contact regions and the source line regions of the wafer, wherein the source line structure formed in the source line region of the wafer is united with the source/drain regions of the select source gate structures.