Patent ID: 9111599
Filing Date: 2015-08-18
Classification: G11C

Abstract:
1. A memory device, comprising: a training circuit; a data strobe transmission path comprising: a plurality of data transmission paths each comprising: a plurality of data latching circuits each connected to outputs of the adjustable delay circuit of one of the data transmission paths and the tree circuit; a phase detection circuit connected to the outputs of the adjustable delay circuit of at least one of the data transmission paths and the tree circuit; and wherein when the memory device is under a training mode, a training process is performed on at least one of the data transmission paths such that the training circuit is activated to generate a training clock signal to both of the first input path and the second input path and further to the tree circuit and the adjustable delay circuit to generate a first clock signal and a second clock signal respectively, wherein the phase detection circuit detects a phase difference between the first clock signal and the second clock signal to adjust a delay time of the adjustable delay circuit until the first clock signal and the second clock signal are in phase; wherein when the memory device is under an operation mode, the training circuit is deactivated such that the first input path receives an external data strobe signal to generate a data strobe signal to the tree circuit and the second input path receives an external data signal to generate a data signal to the adjustable delay circuit, wherein each of the data latching circuits receives a treed data strobe signal from the tree circuit to latch a delayed data signal received from the adjustable delay circuit of one of the data transmission paths.