Patent ID: 7853840
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles wherein, during the test operation, a first external address is received during first and second clock cycles of a clock signal, and the internal address generating circuit outputs a first internal address and a first internal command in a third clock cycle of the clock signal, the first internal address and the first internal command respectively corresponding to the first external address and a first external command, a second external address is consecutively received after the first external address and a second external command is received two clock cycles from that of the first external command,