Patent ID: 6209049
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A data processing system comprising:a data processing unit that switches a process data input mode for each prescribed area in a total address space between a first mode, in which data is input at a first number of bits, and a second mode, in which data is input at the first number of bits by performing a plurality of inputs at a second number of bits smaller than the first number of bits;at least one storage device, each storage device outputting process data at the second number of bits; andan address data converter that converts address data for the at least one storage device,wherein the data processing unit comprises: address data output means for outputting address data for selecting an external device having a prescribed area allocated in the total address space; storage device number determination means for determining number of storage devices and outputting results of determination; and process data input means for inputting process data from the at least one storage device, using either a first address area by the first mode or a second address area by the second mode, based on the results of determination,wherein the address data converter comprises: address data extraction means for extracting address data and outputting the address data to the at least one storage device based on whether the address data from the data processing unit corresponds to the first address area or the second address area so that the process data is output from the at least one storage device either on the first number of bits basis or the second number of bits basis; and selecting means for outputting signals based on the address data to select the at least one storage device, andwherein the at least one storage device is connected to at least one connection device that connects to the address data extraction means via an address data line and the data processing unit via a process data line.