Patent ID: 8200954
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A method for configuring an electronic device during a power-on sequence, comprising: sampling a boot pin state multiple times with use of a multi-stage sampling logic having a first switch, a second switch, a third switch, and a fourth switch, the sampling comprising: a) presetting the third and fourth switch, wherein the third switch selects between two voltage levels; b) sampling a first sample of the boot pin state, wherein the boot pin is sampled with: c) storing a first value corresponding to the first sampled boot pin state, d) connecting the pull-up resistor or the pull-down resistor to the boot pin, through closing the first switch or the second switch, respectively, after the first sampling of the boot pin state and before a second sampling of the boot pin state and e) transitioning the fourth switch between a connection and a non-connection to a staging resistor after the first sampling of the boot pin state and before a second sampling of the boot pin state, f) sampling the second sample of the boot pin state after the connecting of the pull-up resistor or the pull-down resistor and the transitioning of the fourth switch, g) storing a second value corresponding to the second boot pin state, wherein the stored values comprise one of four different states for a single boot pin in a boot code selection logic.