Patent ID: 6521498
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method of manufacturing a vertical power transistor trench-gate semiconductor device having a plurality of transistor cells, each transistor cell being surrounded by a trench-gate structure comprising a trench extending into a semiconductor body with gate material in the trench and a gate insulating layer between the trench and the gate material, and each transistor cell having an annular source region adjacent an upper part of the trench-gate structure and separated from a drain region by a channel-accommodating body region adjacent the trench-gate structure, wherein the method includes forming the source regions so as to be self-aligned to the trench-gate structures, characterised in that the method includes the steps of:(a) forming on a surface of the semiconductor body a first mask of a first material with first windows, each said first window having a mid-point path coincident with a mid-point path of the location of a said trench; (b) providing in each first window a U-shaped section layer of an insulating second material, the layers of second material being provided after the trench-gate structures are formed, each layer of second material having upright portions on the side walls of the first window and a base portion which provides a gate insulating overlayer on the gate material of a said trench-gate structure; (c) removing the first mask and then forming spacers, each spacer having a vertical surface which is aligned with the location of a surface of a said upright portion of the layer of second material and each spacer having a horizontal base surface; (d) using the spacers to form the annular source regions with the lateral extent of the source regions from the trench-gate structures being determined by the lateral extent of the base surface of the spacers; and (e) providing a source electrode to contact the source regions and the body regions adjacent the source regions.