Patent ID: 7667220
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A memory structure having multiple memory layers, comprising: a first bit line; a first diode electrically coupled to the first bit line; a first memory layer structure having a first electrode, a second electrode, and a metal oxide element embedded within the first electrode and in contact with the second electrode, the first electrode of the first memory layer structure electrically coupled to the first diode; a second bit line which includes the second electrode in the first memory layer structure; a second diode electrically coupled to the second bit line; a second memory layer structure, overlying the first memory layer structure, having a first electrode, a second electrode, and a metal oxide element embedded within the first electrode and in contact with the second electrode, the first electrode of the second memory layer structure electrically coupled to the second diode; and a third bit line which includes the second electrode in the second memory layer structure.