Patent ID: 6351169
Filing Date: 2002-02-26
Classification: G06F,G11C,H03L,Y10S

Abstract:
An internal clock signal generating circuit for generating an internal clock signal synchronized in phase with an externally applied external clock signal, comprising:a phase difference detecting circuit for detecting a phase difference between said external clock signal and said internal clock signal; a first delay circuit for selectively delaying said external clock signal by changing a first delay amount applied to said external clock signal by a first time width according to the detected phase difference; and a second delay circuit for selectively delaying the delayed external clock signal from said first delay circuit by changing a second delay amount applied to said delayed external clock signal by a second time width greater than the first time width according to said detected phase difference to output as said internal clock signal, said second delay amount being fixed after the phase difference detecting has started; wherein said phase difference detecting circuit detects that said external clock signal and said internal clock signal are phase-locked and outputs a phase lock signal, and said second delay circuit includes: a plurality of fixed delay circuits serially coupled to each other, one of said plurality of fixed delay circuits connected to and receiving the delayed external clock signal from said first delay circuit, each of said plurality of fixed delay circuits delaying a signal input therein by a time period that is equivalent to said second time width for output; and a select circuit for selecting either the output of said first delay circuit or one of the respective outputs of said plurality of fixed delay circuits for output as said internal clock signal, and responsive to said phase lock signal for holding a state in which said either one of the outputs is selected at the time of reception of said phase lock signal.