Patent ID: 6954377
Filing Date: 2005-10-11
Classification: G11C

Abstract:
1. A non-volatile differential dynamic random access memory (DRAM) cell comprising: a first MOS transistor having a first current carrying terminal coupled to a first node, a second current carrying terminal coupled to a first bitline associated with the non-volatile differential DRAM cell, and a gate terminal coupled to a first terminal of the non-volatile DRAM cell; and a first non-volatile device associated with the first MOS transistor and comprising: a first substrate region coupled to a second terminal of the non-volatile differential DRAM cell; a source region formed in the first substrate region and coupled to the first node; a drain region formed in the first substrate region and separated from the source region by a first channel region; said drain region being coupled to a third terminal of the non-volatile differential DRAM cell; a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer; said first gate coupled to a fourth terminal of the non-volatile differential DRAM cell; and a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer; wherein said first portion of the first channel region and said second portion of the channel do not overlap and wherein said second gate is coupled to a fifth terminal of the non-volatile differential DRAM cell, said first non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof; a second MOS transistor having a first current carrying terminal coupled to the second node, a second current carrying terminal coupled to a second bitline associated with the non-volatile differential DRAM cell, and a gate terminal coupled to the first terminal of the non-volatile differential DRAM cell; and a second non-volatile device associated with the second MOS transistor and comprising: a second substrate region coupled to the second terminal of the non-volatile differential DRAM cell; a source region formed in the second substrate region and coupled to the second node; a drain region formed in the second substrate region and separated from the source region of the second substrate region by a second channel region; said drain region of the second substrate region being coupled to the third terminal of the non-volatile differential DRAM cell; a first gate overlaying a first portion of the second channel region and separated therefrom via a first insulating layer and coupled to the fourth terminal of the non-volatile differential DRAM cell; and a second gate overlaying a second portion of the second channel region and separated therefrom via a second insulating layer; wherein said first portion of the second channel region and said second portion of the second channel region do not overlap and wherein said second gate overlaying the second portion of the second channel region is coupled to the fifth terminal of the non-volatile differential DRAM cell, said second non-volatile device being adapted so as not to include a floating gate disposed between said first and second gates thereof.