Patent ID: 6085308
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A data processor, comprising:(a) a program part including an incrementation register for containing addresses;(b) a program memory having instruction data stored therein connected to said incrementation register for receiving addresses therefrom to identify data to be accessed from said program memory;(c) a local random access memory;(d) a decoding part for receiving instruction data from said program memory for execution of a respective instruction in multiple cycles, said decoding part including a decoder for generating the address of a register used in the instruction and/or a random access memory address, said decoder being effective to receive interrupt signals, data, and set-up signals in a monitoring function to facilitate synchronization of the data processor with another processor coupled to said data processor to facilitate synchronization of the data processor with another processor coupled to said data processor;(e) a data part comprising first and second multiplexers, an arithmetic and logic unit connected to the outputs of said first and second multiplexers, and a bank of registers connected to the inputs of said first and second multiplexers;(f) said program memory providing first instruction data from the address designated by said incrementation register to said decoding part and the first instruction data being decoded during a first of said multiple cycles, said program memory providing second instruction data from the address designated by said incrementation register to said decoding part and the second instruction data being decoded during the first cycle of a second multiple-cycle sequence coincident with the execution of the first instruction by said data part during a subsequent cycle of the first multiple cycle sequence; and(g) further comprising a condition monitoring block connected between the decoder of said decoding part and said bank of registers, the condition monitoring block receiving information from a selected register of said bank of registers and from the condition field of an instruction to be executed.