Patent ID: 6236696
Filing Date: 2001-05-22
Classification: H03L,H04L

Abstract:
A digital PLL circuit, comprising:a sampler for sampling a burst data signal depending on N phase clock signals to produce N phase sampled data signals;an edge phase detector for detecting edge information based on the N phase sampled data signals in synchronization with a reference signal;a duty selector for detecting duty information based on a bit count value produced by counting bits having a predetermined value of the predetermined number of bits of the N phase sampled data signals and a ratio of the bit count value to the predetermined number as the duty information;a selector for selecting an optimal sampled data signal from the N phase sampled data signals depending on a selected selection pattern determined by an edge count value, the edge information and the duty information; anda retiming section for retiming the sampled data signal selected in synchronization with the reference signal.