Patent ID: 6768358
Filing Date: 2004-07-27
Classification: G06F,H03L,H04W,Y02D,Y10S

Abstract:
A frequency multiplier comprising:a comparator to receive an input clock signal having a first frequency and a feedback signal, the comparator providing an error signal indicative of a difference in a first property between the input clock signal and the feedback signal; a signal generator, coupled to the comparator, to provide an output clock signal having a second frequency, the signal generator adjusting a second property of the output clock signal based on the error signal to reduce the difference in the first property between the input clock signal and the feedback signal; a feedback loop having a divider to provide the feedback signal to the comparator, based on the output clock signal, the feedback loop having an associated first interval of time to reduce the difference in the first property such that the first property of the input clock signal and the first property of the feedback signal are substantially the same; and means for providing an operative signal, based on the output clock signal, during the first interval of time, the means including at least a portion of the divider coupled to the output clock signal to reduce the second frequency below a target frequency of the output clock signal.