Patent ID: 7142941
Filing Date: 2006-11-28
Classification: G03F

Abstract:
1. A computer-implemented method, comprising: simulating the formation of a wafer feature having a plurality of characteristics which deviate from specification by changing one or more process parameter values within a lithographic process simulation module; matching the plurality of characteristics of the simulated wafer feature with a corresponding plurality of deviant characteristics of a wafer feature fabricated by a lithography process, wherein the matched characteristics comprise critical dimensions and overlay variations of the simulated and fabricated wafer features; identifying a first set of process parameters used to generate the simulated wafer feature that respectively have values substantially equal to a second corresponding set of process parameters used to fabricate the wafer feature by the lithography process, wherein the values of at least one process parameter of the first and second sets are within specification; and citing the values of the first and second sets of process parameters as potential causes of specification deviations within wafers fabricated from the lithography process.