Patent ID: 6041013
Filing Date: 2000-03-21
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a main control block having an address signal terminal, a clock signal terminal, a command signal terminal and a power supply terminal as external terminals and including an address signal generating section for receiving an external address signal fed to the address signal terminal to generate an internal address signals, a command signal generating section for receiving an external command signal fed to the command signal terminal to generate an internal command signal, a clock signal generating section for receiving an external clock signal fed to the clock signal terminal to generate an internal clock signal and an internal power supply generating section for receiving an external supply potential fed to the power supply terminal to generate an internal supply potential; andat least one memory block, each memory block having a data input/output terminal and a power supply terminal for data input/output, a plurality of memory cells for storing data, a data input/output section for sending data to and receiving data from the data input/output terminal in response to the internal command signal and in synchronism with the internal clock signal, the data input/output section being driven by the source power for data input/output fed to the power supply terminal for data input/output, and a memory control section for writing data in a specific one of the plurality of memory cells and reading data from a specific one of the plurality of memory cells in response to the internal address signal and in synchronism with the internal clock signal, the memory control section being driven by the internal power supply potential.