Patent ID: 6310485
Filing Date: 2001-10-30
Classification: G01R

Abstract:
A burn-in stress test mode circuit of an integrated circuit device, comprising:a diode stack comprised of a plurality of diodes , wherein the plurality of diodes are serially connected with a first diode of the plurality of diodes connected to a first supply voltage;a first transistor having a gate connected to the first supply voltage;a second transistor having a gate controlled by a power-on reset signal; anda first logic element having an input terminal and an output terminal, wherein a node is defined by the electrical connection of the input terminal of the first logic element, a second diode of the plurality of diodes of the diode stack, a second source/drain of the first transistor, and a second source/drain of the second transistor;wherein when the first supply voltage of the integrated circuit device exceeds a predetermined voltage level equal to a diode forward bias voltage drop of the diode stack plus a voltage trip point of the first logic element, the integrated circuit device enters a burn-in mode.