Patent ID: 6518812
Filing Date: 2003-02-11
Classification: H03H

Abstract:
A composite delay line, comprising:a multiplexer having a first and a second input; a first delay line having an input, an output and first control means for controlling delay, wherein the output is connected to the first input of the multiplexer and wherein the first delay line is a binary weighted delay line; a second delay line having an input, an output and second control means for controlling delay, wherein the output is connected to the second input of the multiplexer, and the second delay line is a linear discrete delay line; control logic connected to the first control means for selecting a delay through the first delay line; control logic connected to the second control means for selecting a delay through the second delay line, wherein the delays available through the first delay line are different than the delays available through the second delay line; and control logic connected to the multiplexer for selecting between the output of the first delay line and the output of the second delay line.