Patent ID: 7149142
Filing Date: 2006-12-12
Classification: G11C

Abstract:
1. A method, comprising: controlling standby power consumption in a memory array that includes a plurality of volatile memory cells as well as a voltage limiting component and a current limiting component between the volatile memory cells and a ground voltage potential; isolating one or more rows of memory cells in the memory array from the ground voltage potential to control power consumption in a standby mode by having the current limiting component stop passing current in the standby mode; controlling a floating ground voltage potential sensed by each memory cell when in the standby mode by configuring the voltage limiting component to conduct when the floating ground voltage potential is larger than a threshold voltage of the voltage limiting component in order to reduce leakage current but reliably maintain stored contents of the volatile memory cells; and internally raising the floating ground voltage potential higher than a voltage biasing the bulk of the transistors in a volatile memory cell by coupling the floating ground voltage potential to the voltage limiting component.