Patent ID: 6480869
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A random-number generating circuit comprising:a plurality of shift registers of clock synchronization type being cascaded so as to generate a random-number of predetermined bit number with parallel outputs of said plurality of shift registers; a circuit that obtains a sum of serial outputs of two or more of said plurality of shift registers to input the obtained sum to an input terminal of the first stage shift register; a clock generating circuit that generates a clock signal to input the clock signal to each shift register; an external data input means that inputs external bit data of a predetermined number of bits to one or more of said plurality of shift registers; and a plurality of adders arranged within one or more of said plurality of shift registers, each adder adding corresponding one bit of the input external bit data to corresponding one bit of bit data being shifted within corresponding shift register, thereby the random-number including a plurality of bit data added by said plurality of adders, and wherein each shift register is comprised of one or more flip-flop circuits of clock synchronization type the number of which is equal to the number of parallel output bits of each shift register, and wherein each flip-flop circuit provides with a first element for making an output data HIGH upon turning an electric power on and a second element for making an output data LOW upon turning the electric power on, said second element having a derivability same to that of said first element.