Patent ID: 8234540
Filing Date: 2012-07-31
Classification: G06F,H03M

Abstract:
1. A communication interface device comprising: high-speed sampling logic to capture high-speed data from a high-speed bus using a high-speed sampling clock; static bit communication (SBC) sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock, wherein the SBC sampling clock is slower than the high-speed sampling clock; an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples; and command decoding logic to decode the received SBC command, wherein the high-speed bus is one of an upstream bus and a downstream bus to communicate with a second communication interface device, and the high-speed sampling clock is received via one of upstream clock lanes and downstream clock lanes, and wherein the upstream bus includes 13 upstream data lanes and 2 upstream spare lanes, the downstream bus includes 13 downstream data lanes and 2 downstream spare lanes, the upstream clock lanes include an upstream clock and an upstream spare clock, and the downstream clock lanes include a downstream clock and a downstream spare clock.