Patent ID: 7269046
Filing Date: 2007-09-11
Classification: G11C

Abstract:
1. A floating-gate transistor array comprising: a first transistor having a first source, a first drain, and a first floating gate; a second transistor having a second source, a second drain, and a second floating gate; a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the first floating gate of first transistor; a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the second floating gate of the second transistor; a first row programming switch having a first output, wherein the first output of the first row programming switch is coupled to the second terminal of the first capacitor and the second terminal of the second capacitor; a third transistor having a third source, a third drain, and a third floating gate; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third floating gate of the third transistor; a second row programming switch having a first output, wherein the first output of the second row programming switch is coupled to the second terminal of the third capacitor; a first column programming switch having a first output, wherein the first output of the first column programming switch is coupled to the first drain of the first transistor and the third drain of the third transistor; and a second column programming switch having a first output, wherein the first output of the second column programming switch is coupled to the second drain of the second transistor.