Patent ID: 7069406
Filing Date: 2006-06-27
Classification: G06F,G11C

Abstract:
1. A synchronous memory circuit comprising: an address bus for receiving an address; at least two memory blocks each of which is capable to be accessed at said address; and a data bus for receiving data items for transfer to or from the memory blocks, wherein in two consecutive clock cycles at least a first and a second write data items corresponding to a first write burst operation are capable of being transferred sequentially to the memory circuit via the data bus and at least a first and second read data items corresponding to a first read burst operation are capable of being provided sequentially by the memory circuit via the data bus, and wherein the data bus is capable of receiving data corresponding to the write burst operation and providing data corresponding to the read burst operation with no dead cycles therebetween; and further including an output circuit for receiving the at least first and second read data items from respective at least two memory blocks in the first read burst operation and allowing the first read data item to be provided on the data bus half a clock cycle after the first read burst operation is initiated, and allowing the second read data item to be provided on the data bus one clock cycle after the first read burst operation is initiated; and at least two registers for providing both a burst address received at the address bus and at least one read/write control signal received at least one input terminal of the memory circuit to the at least two memory blocks sequentially in one clock cycle.