Patent ID: 6657124
Filing Date: 2003-12-02
Classification: H01L,H05K,Y02P

Abstract:
A semiconductor packaging structure comprising:an electrically mechanically stressed substrate having a top surface and a bottom said surface; a region of stress concentrations and a region of electrical dummy within substrate; a semiconductor die mounted on said top surface; means, attached on said top surface for electrically contacting selected areas on said die; a first plurality of solder joints mounted on said die surface, integral with said top surface and projecting downwardly, therefrom, positioned so as to underlie said region of electrical dummy; a second plurality of solder joints mounted on said die surface, integral with said top surface and projecting downwardly, therefrom, having a lower melting point than said first plurality of solder joints and arranged as a ball grid array over said die surface, excepting locations occupied by said first plurality of solder joints, said region of stress concentrations comprising said second plurality of solder joints; and selected areas on the surface of said top surface that is attached to said die surface, said selected areas comprising cured solder paste and being positioned in one-to-one correspondence with the totality of solder joints on said die surface.