Patent ID: 8861292
Filing Date: 2014-10-14
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array that includes a plurality of word lines, a plurality of redundant word lines, a plurality of bit lines and a plurality of redundant bit lines, the memory cell array can be accessed by supplying a row address and a column address; a row fuse circuit that stores addresses of a plurality of defective word lines included in the word lines; a column fuse circuit that stores addresses of a plurality of defective bit lines included in the bit lines; a row decoder that selects one of the word lines based on the row address when the row address does not match the addresses output from the row fuse circuit, and selects one of the redundant word lines when the row address matches one of the addresses output from the row fuse circuit; and a column decoder that selects one of the bit lines based on the column address when the column address does not match the addresses output from the column fuse circuit, and selects one of the redundant bit lines when the column address matches one of the addresses output from the column fuse circuit, wherein the memory cell array has a substantially rectangular shape having short sides in an extension direction of the word lines and the redundant word lines and having long sides in an extension direction of the bit lines and the redundant bit lines, the row decoder, the row fuse circuit and the column fuse circuit are arranged along one of the long sides of the memory cell array, and are laid out in a direction of the short sides of the memory cell array, and the column decoder is arranged along one of the short sides of the memory cell array.