Patent ID: 9223717
Filing Date: 2015-12-29
Classification: G06F,Y02D

Abstract:
1. A method of reducing data communication burden for cache coherence protocols in a multiprocessor system having multiple processors associated with cache memory holding lines of data that may be individually invalidated, the method comprising the steps at each processor of: (a) delaying the transmission of cache line invalidation messages to other caches while collecting cache line invalidation messages related to different addresses in memory according to common regions of memory; (b) combining the collected cache line invalidation messages in a compressed form while preserving the information of each collected invalidation message, the compressed form preserving the information of each invalidation message in that compressed form so that each of the invalidation messages including the multiple different addresses in memory could be reconstructed from the compressed collected invalidation message; and (c) transmitting the combined compressed invalidation messages instead of the cache line invalidation messages related to different addresses.