Patent ID: 7000162
Filing Date: 2006-02-14
Classification: G01R,H01L

Abstract:
1. An integrated circuit for performing stress testing, comprising: a first power rail connected to a first latch and a first circuit, said first power rail powered when a first clock signal is in an (A) state and de-powered when said first clock signal is in a (1−A) state where A is equal to 0 or 1, said first power rail supplied from a first power supply; a second power rail connected to a second latch, said second power rail powered when a second clock signal is in a (B) state and de-powered when said second clock signal is in a (1−B) state, where B is equal to 0 or 1, said second power rail supplied from a second power supply; said first circuit coupled between an output of said first latch and an input of said second latch; and said first clock signal high whenever said second clock signal is low, said first clock signal low whenever said second clock signal is high, low states of said first clock signal not overlapping high states of said second clock signal and low states of said second clock signal not overlapping high states of said first clock signal.