Patent ID: 8976603
Filing Date: 2015-03-10
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory blocks, one of the memory blocks including a first group and a second group, the first group including a first unit and a second unit, the first group electrically connected to a first bit line, the second group electrically connected to a second bit line, the first unit including a first memory cell and a second memory cell, the second unit including a third memory cell and a fourth memory cell; a first line electrically connected to one end of the first unit; a second line electrically connected to one end of the second unit; a third line electrically connected to gates of the first memory cell and the third memory cell; a fourth line electrically connected to gates of the second memory cell and the fourth memory cell; and a controller configured to perform an erase operation on the condition that a first voltage is applied to the first line, a second voltage is applied to the second line, a third voltage is applied to the third line, a fourth voltage is applied to the fourth line, the second voltage is higher than the first voltage, and the fourth voltage is higher than the third voltage.