Patent ID: 6365943
Filing Date: 2002-04-02
Classification: H01L,Y10S

Abstract:
An integrated circuit comprising:a first silicon gate structure dielectrically spaced above a first silicon base layer and laterally between a first pair of silicon source/drain structures, wherein an upper surface of said first silicon gate structure is coplanar with upper surfaces of said first pair of silicon source/drain structures; a second silicon gate structure dielectrically spaced above a second silicon base layer and laterally between a second pair of silicon source/drain structures, wherein an upper surface of said second silicon gate structure is coplanar with upper surfaces of said second pair of silicon source/drain structures, and wherein said second silicon base layer is spaced above said first silicon base layer; a first pair of dielectric spacer structures laterally disposed between said first silicon gate structure and said first pair of silicon source/drain structures, wherein upper surfaces of said first pair of dielectric spacer structures are coplanar with said upper surfaces of said first pair of silicon source/drain structures; a second pair of dielectric spacer structures laterally disposed between said second silicon gate structure and said second pair of silicon source/drain structures, wherein upper surfaces of said second pair of dielectric spacer structures are coplanar with said upper surfaces of said second pair of silicon source/drain structures; and an insulating layer disposed above said first silicon gate structure and below said second silicon base layer, such that a lower surface of said insulating layer is adjacent an upper surface of said first silicon gate structure, and an upper surface of said insulating layer is adjacent a lower surface of said second silicon base layer.