Patent ID: 6127228
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method for forming a buried bit line, comprising the steps of:providing a silicon-on-insulator substrate, wherein the substrate includes a silicon base layer, a first insulation layer over the silicon base and an epitaxial silicon layer over the first insulation layer;forming a shallow trench isolation (STI) layer in the epitaxial silicon layer, wherein a lower surface of the STI layer contacts the first insulation layer;forming a patterned bit line mask layer over the epitaxial silicon layer, wherein the mask layer exposes a portion of an upper surface of the STI layer;forming a trench that passes through the STI layer and runs deep into the first insulation layer, while using the patterned bit line mask layer as an etching mask;forming a buried bit line inside the trench, wherein the top surface of the buried bit line is at a level between the upper and the lower surfaces of the STI layer;forming a second insulation layer above the buried bit line, wherein the second insulation layer completely fills the trench;removing the patterned bit line mask layer;forming a plurality of word lines and a plurality of source/drain regions above the substrate and in the epitaxial silicon layer;forming a third insulation layer above the substrate, wherein the third insulation layer fills a space between neighboring word lines;performing a self-aligned contact process to form a bit line contact opening between neighboring word lines, wherein the bit line contact opening exposes a portion of the buried bit line and a portion of the source/drain region; andforming a bit line contact inside the bit line contact opening, wherein the bit line contact is electrically connected to the buried bit line and the source/drain region.