Patent ID: 6150847
Filing Date: 2000-11-21
Classification: G06F,H03K

Abstract:
A device for generating a variable duty cycle clock, comprising:a frequency divider for dividing an input clock to obtain a divided clock;a plurality of first delay elements connected in series, for sequentially delaying the divided clock for a first delay time to obtain a plurality of first delay clocks;a plurality of second delay elements connected in series and corresponding to the first delay elements, for sequentially delaying the divided clock for a second delay time to obtain a plurality of second delay clocks, wherein the second delay time is in a variable proportion to the first delay time;a selector for comparing the divided clock and the first delay clocks to obtain a plurality of state signals for selecting a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks; anda logic circuit for XORing the divided clock and the second selected clock to obtain the variable duty cycle clock.