Patent ID: 9059020
Filing Date: 2015-06-16
Classification: G06F,H01L

Abstract:
1. A circuit for implementing an enhanced transistor topology enabling enhanced current capability comprising: a fin field effect transistor (FinFET); said FinFET formed on a semiconductor substrate; said FinFET having in-line source and drain regions formed without a dog-bone shape and a gate region formed on a gate dielectric with first and second gate extensions extending past opposing sides of said in-line source and drain regions; a first field effect transistor (FET) formed in said semiconductor substrate beside and under said FinFET and a second FET formed in said semiconductor substrate beside and under said FinFET; each of said first FET and said second FET having buried source and drain diffusions formed in said semiconductor substrate on the opposing sides of said in-line source and drain regions with angled implants used to dope said buried source and drain diffusions and FinFET; and said first and second gate extensions of said FinFET providing a gate of said first FET and said second FET.