Patent ID: 6448149
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method of fabricating Shallow Trench Isolation (STI) structures for a semiconductor device, comprising:forming an active mask layer on a semiconductor substrate; etching the semiconductor substrate to form a plurality of trenches therein, using said active mask layer as an etch mask; depositing an oxide layer by High Density Plasma Chemical Vapor Deposition (HDP-CVD) over said active mask layer so as to fill said trenches to a thickness greater than the depth of said trenches and less than the sum of said depth and the thickness of said active mask layer; depositing a capping oxide layer over said HDP-CVD oxide layer by means of plasma source of Tetra-Ethyl-Ortho-Silicate (TEOS); and polishing said capping oxide layer and HDP-CVD oxide layer so as to expose said active mask layer.