Patent ID: 7746690
Filing Date: 2010-06-29
Classification: G11C

Abstract:
1. A memory comprising: a plurality of word lines; first transistors, the respective gate electrodes of which are connected to respective said plurality of word lines for entering an ON-state through selection of corresponding said word line; a plurality of memory cells including diodes having cathodes connected to the source or drain regions of said first transistors respectively; and a data determination portion connected to the drain or source regions of said first transistors for determining data read from selected said memory cell, wherein said plurality of word lines connected with said first transistors respectively are classified into a plurality of word line groups each including a prescribed number of said word lines, said memory further comprises first signal lines linking the drain or source regions of said first transistors and said data determination portion with each other, and said first signal lines are arranged at least one by one for said plurality of word line groups respectively.