Patent ID: 6472944
Filing Date: 2002-10-29
Classification: H03K

Abstract:
A voltage-controlled oscillator comprising:a plurality of basic cells; and a center frequency adjustment circuit that outputs a control signal for setting a delay time for each of said plurality of basic cells; each of said basic cells comprising: first and second cell input terminals; first and second cell output terminals from which signals that have been received from said first and second cell input terminals are outputted in non-inverted form; a first delay circuit for delaying signals received from said first and second cell input terminals by a delay time that is set based on the control signal outputted from said center frequency adjustment circuit; a second delay circuit for delaying output signals of said first delay circuit by a delay time that is set independently of said first delay circuit based on the control signal outputted from said center frequency adjustment circuit; and an adder circuit that adds said output signals of said first delay circuit and output signals from said second delay circuit at a proportion that is based on an additional proportion coefficient that is controlled from outside and outputs a result of addition; wherein, in each of said basic cells, said result of addition is applied to said first and second cell output terminals; and the basic cells are connected in a series such that said first and second cell output terminals of a preceding-stage basic cell are connected to said first and second cell input terminals, respectively, of the next-stage basic cell, and said first and second cell output terminals of the last-stage basic cell are connected to the second and first cell input terminals, respectively, of the first-stage basic cell such that logic is reversed; wherein said center frequency adjustment circuit comprises a plurality of delay time adjustment circuits each having first and second control signal generation circuits; each of said control signal generation circuits comprises: a plurality of switches that are connected to each other in parallel; a plurality of constant-current power supplies that are each serially connected to one of said plurality of switches and that output different currents; a current mirror circuit that is connected to sides of said plurality of switches that are not connected to said constant-current power supplies, said current mirror circuit comprising: a reference current terminal for outputting a current that is set by said plurality of switches and said plurality of constant-current power supplies, and a current output terminal for outputting a current of a same value as the current that is outputted from the reference current terminal; and a MOS (Metal-Oxide-Semiconductor) transistor having a drain connected to the current output terminal of said current mirror circuit, a source connected to a power-supply voltage, and a gate connected to each of said plurality of basic cells, said drain and gate of said MOS transistor being connected together.