Patent ID: 8148219
Filing Date: 2012-04-03
Classification: H01L,H03L

Abstract:
1. A method for implementing a phase locked loop (PLL) circuit, comprising: forming an oscillator from one or more devices having a first thin oxide layer to output a reference clock signal; forming a reference frequency divider from one or more devices having a second thin oxide layer to receive and divide the reference clock signal and output a reference signal; forming a comparison frequency divider from one or more devices having a third thin oxide layer to receive a control voltage signal and output a comparison signal; forming a phase comparator from one or more devices having a fourth thin oxide layer to receive the reference signal and the comparison signal, wherein the phase comparator compares the reference signal with the comparison signal and outputs a frequency difference signal and a phase difference signal; forming a charge pump from one or more devices having a fifth thin oxide layer to receive the frequency difference and the phase difference signals and output a charge pump signal; forming a low-pass filter with one or more capacitors having a thick oxide layer to receive the charge pump signal and output a low pass filter signal, wherein the thick oxide layer is thicker than the first thin oxide layer, and wherein the one or more capacitors are metal-oxide-semiconductor (MOS)-based capacitors; and forming a voltage controlled oscillator from one or more devices having a sixth thin oxide layer to receive the low pass filter signal and output the control voltage signal.