Patent ID: 6647404
Filing Date: 2003-11-11
Classification: G06F

Abstract:
An array multiplier having inputs A and B and output O;where B is a multiplicand; where input A is a bit vector {An . . . Am+1, Am, Amâˆ’1 . . . A0}; the multiplier comprising: a plurality of booth encoder circuits each receiving a pair of bits of vector A and a third input, and generating a booth encoded value, one of said plurality of booth encoder circuits having inputs Am and Am+1, the booth encoder circuits generating a booth encoded value; a multiplexor having an output bit Vm, said multiplexor having a control input S, said control input S being true only during a predetermined cycle of a multiply operation, said multiplexor having inputs C, said control input S, inputs C and bit Am of vector A coupled such that Vm,=S&C|!S&Am, wherein Vm is coupled as the third input of the booth encoder having inputs Am, and Am+1 and another of the plurality of booth encoder circuits receives the Am+2 and Am+3 pair of bits of vector A and third input Am+1; a plurality of partial product generators wherein the booth encoded value and input B are used to generate a plurality of partial products; and an adder tree wherein output O is computed by summing the partial products.