Patent ID: 6097622
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A ferroelectric memory comprising:a memory cell composed by a MOSFET and a ferroelectric capacitor;a word line connected to said memory cell;a plate line connected to said memory cell;a row decoder having a first inverter, whose output is coupled to said word line; anda plate line select circuit having a second inverter and an output coupled to said plate line;wherein one of:a capacitance of said MOSFET is smaller than a capacitance of said capacitor;a first product of a ratio of a length to a width of a gate in an NMOS transistor included in said first inverter and a gate capacitance of the MOSFET is approximately equal to a second product of a ratio of a length to a width of a gate in an NMOS transistor included in said second inverter and a capacitance of said capacitor; anda third product of a ratio of a length to a width of a gate in a PMOS transistor included in said first inverter and a gate capacitance of the MOSFET is approximately equal to a fourth product of a ratio of a length to a width of a gate in a PMOS transistor included in said second inverter and a capacitance of said capacitor.