Patent ID: 6278290
Filing Date: 2001-08-21
Classification: H03K

Abstract:
A method of operating a programmable logic device at device power-up, the programmable logic device including a plurality of configuration memory cells, a plurality of interconnect wires, a plurality of pass transistors connected to the plurality of interconnect wires and controlled by the plurality of configuration memory cells, and a plurality of buffers, each buffer having an input terminal connected to a first interconnect wire, and a pull-up device for pulling up the input terminal of an associated buffer when a high voltage is applied to the input terminal, wherein the method comprises:transmitting a high voltage signal to the input terminals of all of the plurality of buffers when the programmable logic device is in one of a power-up mode and a standby mode, thereby turning on the pull-up devices of all of the plurality of buffers such that the high voltage signal is simultaneously transmitted onto all of the interconnect wires;writing configuration data to the configuration memory cells such that a group of the plurality of pass transistors is turned off, wherein a group of said plurality of interconnect wires connected to the group of pass transistors remain pulled up by the pull-up devices of an associated group of said plurality of buffers; andafter writing the configuration data, changing the mode of the programmable logic device such that the programmable logic device is no longer in the one of the power-up mode and the standby mode.