Patent ID: 6117689
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of fabricating an integrated circuit, said method comprising: forming an array of microelectronic structures, wherein said forming of each of said microelectronic structures comprisesforming a barrier layer on an oxidizable layerl, whereinsaid oxidizable layer and said barrier layer form a plug in an opening in an interlayer dielectric formed on a semiconductor substrate, whereinsaid plug is recessed below a top surface of said interlayer dielectric;depositing a single crystal oxygen stable layer on said barrier layer, wherein said depositing of said oxygen stable layer comprisesforming a train nucleus of said oxygen stable layer on a top surface of said barrier layer;forming grain nuclei on said top surface of said interlayer dielectric;depositing photoresist on said microelectronic structure;planarizing said photoresist down to said top surface of said interlayer dielectric;removing said grain nuclei from said top surface of said interlayer dielectric with a reactive ion etch; andremoving remaining portions of said photoresist from said opening; anddepositing a high-dielectric-constant material layer on said oxygen stable layer,whereby said single crystal oxygen stable layer prevents oxidation of said barrier layer and said oxidizable layer.