Patent ID: 6632718
Filing Date: 2003-10-14
Classification: H01L

Abstract:
A method for fabricating an integrated circuit, comprising the steps of:forming a plurally of gate electrodes over a semiconductor body; forming an etch stopping layer over said gate electrodes and said semiconductor body; forming disposable spacers comprising germanium separated from edges of said gate electrodes by said etch stopping layer; forming a first mask layer over said semiconductor body exposing a first region of said semiconductor body and covering a second region of said semiconductor body; implanting first source/drain regions in said first region using said first mask layer and at least one of said disposable spacers as an implant mask; removing said at least one of said disposable spacers; implanting first drain extension regions in said semiconductor body using said first mask layer as an implant mask after removing said at least one of said disposable spacers; and removing said first mask layer.