Patent ID: 7549109
Filing Date: 2009-06-16
Classification: G06F,G11C

Abstract:
1. A memory circuit, comprising: a dual port memory circuit that includes: a memory plane including a first module and a second module, each composed of an array of memory cells arranged in rows and columns, each row of said memory plane allowing to store a page of words, each word of said page being identified by an address organized according to a hierarchical division defined by (@MSB, row address, column address), with @MSB identifying a particular module among said modules; a first address bus and a second address bus; a first data bus and a second data bus used for reading and for writing in said modules respectively; first and second multiplexers each having a first input and a second input connected to said first and second address buses respectively and also having an output; first and second row decoders each having an input connected to the output of a respective one of said multiplexers in order to receive a row address; a first column decoder having an input connected to the output of said first multiplexer in order to receive a column address, said first column decoder having an output connected to said first data bus; a second column decoder having an input connected to the output of said first multiplexer in order to receive a column address, said second column decoder having an input connected to said second data bus; a third column decoder having an input connected to the output of said second multiplexer in order to receive a column address, said third column decoder having an output connected to said first data bus; a fourth column decoder having an input connected to the output of said second multiplexer in order to receive a column address, said fourth column decoder having an input connected to said second data bus; first and second control circuits for controlling the first and second multiplexers, respectively, allowing each multiplexer to select one of both address buses according to the following logic: if @MSB of said first address bus is equal to the address of said module corresponding to said multiplexer and a read/write control is present on said first bus, then the multiplexer outputs the row and column addresses and said read/write control of said first bus; otherwise, if @MSB of said second address bus is equal to the address of said module corresponding to said multiplexer and a read/write control is present on said second bus, then the multiplexer outputs the row and column addresses of said second bus; and if the @MSB on one of the first and second address buses does equal the address of the first and second modules, then each multiplexer outputs inactive read/write controls.