Patent ID: 6018258
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A clock divider comprising:(a) a divisor circuit coupled for receiving a first clock signal having a first prescribed period and responsive to an input divisor value (DIV) and a plurality of control signals, said divisor circuit generating an output signal indicative of the input divisor value;(b) a control circuit coupled to said divisor circuit for receiving the output signal such that said control circuit generates a second clock signal having a first logic state for a first prescribed length of time and a second state for a second prescribed length of time, wherein the second clock signal has a second prescribed period substantially equal to the input divisor value times the first prescribed period of the first clock signal; andan output circuit coupled to said control circuit, said output circuit adjusting a transition of the second clock signal from the first state to the second state and outputting a third clock signal.