Patent ID: 8022544
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A chip structure comprising: a silicon substrate; a MOS device in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first circuit layer and a second circuit layer over said first circuit layer; a dielectric layer between said first and second circuit layers; a metal interconnect over said silicon substrate; a passivation layer over said silicon substrate, said metallization structure and said dielectric layer, wherein an opening in said passivation layer is over a contact point of said metal interconnect, and said contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; a patterned metal layer on said polymer layer and said contact point, wherein said patterned metal layer is connected to said contact point through said opening, wherein said patterned metal layer comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer on said gold seed layer; and a metal bump on said patterned metal layer, wherein said metal bump is connected to said contact point through said patterned metal layer, wherein said metal bump comprises an electroplated gold bump directly on said electroplated gold layer, wherein said electroplated gold bump is not vertically over said contact point, wherein said electroplated gold bump has a thickness between 7 and 30 micrometers.