Patent ID: 6271094
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:(a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;(c) forming an oxide layer on said nitride layer in said gate hole;(d) etching said oxide layer and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing said substrate, wherein the pad oxide layer is tapered by said etching;(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;(f) filling said gate hole with gate conductor;(g) removing said nitride layer exposing portions of said high-k, high-temperature metal oxide; and(h) completing fabrication of said MOSFET device.