Patent ID: 7008850
Filing Date: 2006-03-07
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device that includes a high-breakdown-voltage transistor, a low-voltage-drive transistor, and a MNOS type memory transistor, the method comprising: (a) forming a first mask layer above a high-breakdown-voltage transistor forming region in which the high-breakdown-voltage transistor is formed, a low-voltage-drive transistor forming region in which the low-voltage-drive transistor is formed, and a MNOS type memory transistor forming region in which the MNOS type memory transistor is formed of a semiconductor layer; (b) forming a second mask layer above the first mask layer; (c) selectively removing portions of the first mask layer and the second mask layer above a first gate insulation layer forming region of the high-breakdown-voltage transistor; (d) after step c), forming a first insulation layer on the high-breakdown-voltage transistor forming region by a thermal oxidation method with the first mask layer and the second mask layer as a mask; (e) removing portions of the second mask layer remaining above the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region; (f) removing only the portion of the first mask layer formed above the MNOS type memory transistor forming region; (g) after steps (a)–(f), forming a multilayer film above the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region, the multilayer film being formed with at least a silicon oxide layer and a silicon nitride layer; (h) after step (g), simultaneously removing portions of the multilayer film formed above the high-breakdown-voltage transistor forming region and the low-voltage-drive transistor forming region; (i) after step (h), removing only the portion of the first mask layer remaining above the low-voltage-drive transistor forming region; (j) forming a second gate insulation layer on the low-voltage-drive transistor forming region; (k) simultaneously forming a gate electrode above each of the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region; and (l) forming a source-drain region in each of the high-breakdown-voltage transistor forming region, the low-voltage-drive transistor forming region, and the MNOS type memory transistor forming region.