Patent ID: 6114210
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises:forming a dielectric layer on a surface of a semiconductor substrate;forming a conductive layer on the dielectric layer;patterning to form a gate electrode, having side surfaces, on the surface of the semiconductor substrate with a gate dielectric layer therebetween;ion implanting a first N-type impurity at a first angle with respect to a line perpendicular to the surface of the semiconductor substrate, at a first implantation dosage and at a first implantation energy to form a first N-type impurity lightly doped drain (N-LDD) implant having a first impurity concentration;ion implanting a second N-type impurity at a second angle with respect to a line perpendicular to the surface of the semiconductor substrate less than the first angle, at a second implantation dosage greater than the first implantation dosage and at a second implantation energy less than the first implantation energy to form a second N-LDD implant having a second impurity concentration greater than the first impurity concentration; andactivation annealing to form:a first low concentration N-LDD region extending under the gate electrode from a side surface thereof; anda second high concentration N-LDD region forming a graded junction with the first low concentration N-LDD implant.