Patent ID: 6130467
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate or epitaxial layer formed in the substrate;a trench, formed in the substrate or epitaxial layer, having side surfaces intersecting a main surface of the substrate or epitaxial layer at edges;a thermally grown oxide liner in the trench and on the edges;a pad oxide layer on the main surface having one end in contact with the oxide liner and another end having a side surface, the pad oxide layer covering a first portion of the main surface having a varied crystallographic orientation and proximal to the trench edges;an insulating material filling the trench and extending above the trench to form a step between the insulating material and the pad oxide layer, the step defined by a substantially vertical side surface of the insulating material, wherein the substantially vertical side surface of the insulating material has a height of 500 .ANG. to about 1250 .ANG.;a protective sidewall spacer on the side surface of the insulating material and extending on the pad oxide layer, wherein the protective sidewall spacer has a width of about 500 .ANG. to about 1000 .ANG.; anda thin gate oxide layer on only a second portion of the main surface having a single crystallographic orientation.