Patent ID: 6605525
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks comprising the steps of:providing a wafer that is pre-processed with a plurality of IC dies formed on a top surface, each of said plurality of IC dies being spaced-apart from its immediately adjacent IC dies by a distance that is at least a width of a scribe line, each of said plurality of IC dies further having a multiplicity of input/output pads formed on top; depositing a first metal layer on said top surface of the wafer; depositing a photoresist layer of at least 20 &mgr;m thickness on said first metal layer; forming a plurality of trench openings separating said plurality of IC dies and a plurality of via openings with each on one of said multiplicity of input/output pads exposing said first metal layer; depositing a second metal into and filling said plurality of trench openings forming a plurality of metal lines and said plurality of via openings forming a plurality of metal vias; removing said photoresist layer and said first metal layer not covered by said plurality of metal vias; and depositing an elastomeric material on top of said wafer filling cavities formed between said plurality of metal lines forming said multiplicity of elastomeric blocks.