Patent ID: 8846469
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of: providing a base; forming at least two gate trenches in the base; forming a first dielectric layer to line the inner surfaces of the gate trenches; forming a first polysilicon structure in the gate trenches lining with the first dielectric layer; forming an interlayer dielectric structure on the first polysilicon structure to define at least a source trench; forming the source trench between the two neighboring gate trenches; forming a second dielectric layer to line the inner surfaces of the source trench; forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer; forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region; forming a source region between the gate trenches; removing a portion of the second dielectric layer to expose the source region and the body region; and filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region, wherein the step of forming the source trench comprises: wherein prior to the formation of the spacer, further comprising the step of forming a heavily doped region in the body region by using the interlayer dielectric structure as an implantation mask.