Patent ID: 8370706
Filing Date: 2013-02-05
Classification: H03M,H04L

Abstract:
1. A device comprising: a plurality of input lines, the input lines carrying data; an error correction code (ECC) circuit coupled to the plurality of input lines, the ECC circuit supplying a plurality of codewords in series, the plurality of codewords being generated by the ECC circuit based on the data, each of the plurality of codewords including error correction information and a portion of the data; a serial-to-parallel circuit configured to receive each of the plurality of codewords in series, and supply a first plurality of data units in parallel, each of the first plurality of data units including information from a corresponding one of the plurality of codewords; an interleaver circuit configured to receive the first plurality of data units in parallel and output a second plurality of data units in parallel, each of the second plurality of data units including bits from different ones of the first plurality of data units; a parallel-to-serial circuit to receive the second plurality of data units in parallel from the interleaver circuit, to serialize the second plurality of data units, and to output the serialized second plurality of data units on a plurality of output data lines; where the serial-to-parallel circuit includes: a plurality of delay elements; a rotator circuit to receive data streams, corresponding to the plurality of serial codewords, delayed by the plurality of delay elements, the rotator circuit switching the received data streams to various ones of a plurality of rotator outputs, corresponding to each of the first plurality of data units in parallel; and a plurality of register circuits connected to receive the plurality of rotator outputs, store a bit received from one of the rotator outputs, and output another bit that was previously received from the rotator circuit.