Patent ID: 7537991
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A method of fabricating a salicided MOS device and a one-sided salicided MOS device, comprising: providing a semiconductor substrate having a first region serving as a peripheral region and a second region serving as a DRAM region, wherein the first region of the substrate is used for the salicided MOS device, and the second region of the substrate is used for the one-sided salicided MOS device; forming a first MOS device on the substrate in the first region and a second MOS device on the substrate in the second region, wherein the first MOS device has a first gate structure formed on the substrate, first and second doped regions formed in the substrate and a first spacer and a second spacer formed on each sidewall of the first gate structure, and the second MOS device has a second gate structure formed on the substrate, third and fourth doped regions formed in the substrate and a third and a fourth spacer formed on each sidewall of the second gate structure; forming a capacitor electrically coupled to the fourth doped region in the second region; forming a conformal insulation layer on the first MOS device, the second MOS device and the substrate; forming an organic layer on the conformal insulation layer; performing anisotropic etching to remove part of the organic layer until the conformal insulation layer on the top surface of the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate; removing the insulation layer on the top surface of the first gate structure and the second gate structure; removing the remaining organic layer; removing the conformal insulation layer on the first, second, and third doped regions and on the first, second, and third spacers; and forming a silicide layer on the first gate structure, the first doped region, the second doped region, the second gate structure and the third doped region.