Patent ID: 7502914
Filing Date: 2009-03-10
Classification: G06F

Abstract:
1. A processor comprising: one or more execution resources configured to execute instruction operations, wherein the execution resources comprise hardware circuitry configured to perform at least part of the execution of instruction operations; and a scheduler coupled to the execution resources and configured to maintain an ancestor tracking vector (ATV) corresponding to each given instruction operation in a memory circuit in the scheduler, wherein the ATV identifies instruction operations which can cause the given instruction operation to replay, wherein a replayed instruction operation is reexecuted without being refetched, and wherein the scheduler is configured to set the ATV of each given instruction operation to a null value in the memory circuit in response to the given instruction operation being dispatched to the scheduler, and wherein the scheduler is configured to modify the ATV of the given instruction operation dynamically to insert ATVs corresponding to instruction operations which resolve source operands of the given instruction operation responsive to destination tags of the instruction operations that resolve the source operands, wherein the destination tags are broadcast by the execution resources during execution of the instruction operations that resolve the source operands, and wherein the scheduler is configured to modify the ATV of the given instruction operation to remove ATV tokens assigned to instruction operations for which a replay status is determined, wherein the ATV tokens of the instruction operations are removed independent of whether or not the replay status indicates replay.