Patent ID: 8853040
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A method of forming a transistor device, the method comprising: forming a first patterned gate structure over an extremely thin silicon-on-insulator (ETSOI) semiconductor substrate corresponding to a first polarity type transistor region, and forming a second patterned gate structure over the ETSOI semiconductor substrate corresponding to a second polarity type transistor region, the ETSOI semiconductor substrate having a thickness on the order of about 10 nanometers (nm) or less; forming a first vertical sidewall spacer adjacent the first patterned gate structure; forming a second vertical sidewall spacer adjacent the second patterned gate structure; forming a first type vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the first vertical sidewall spacer, wherein the first type RSD structure abuts the first vertical sidewall spacer and produces a compressive strain on a channel region of the ETSOI semiconductor substrate below the first patterned gate structure; and forming a second type vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the second vertical sidewall spacer, wherein the second type RSD structure abuts the second vertical sidewall spacer and produces a tensile strain on a channel region of the ETSOI semiconductor substrate below the second patterned gate structure.