Patent ID: 6807124
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A memory device comprising:a plurality of memory cells for storing information, said plurality of memory cells divided into a plurality of local blocks, and said plurality of local blocks each including a same number of said memory cells; and a plurality of AND circuits provided in correspondence with said plurality of memory cells, wherein, in writing of said information to one of said memory cells, or in reading of said information from one of said memory cells, one of said plurality of local blocks is specified, and one of the same number of memory cells is specified in each said local block in a common manner, and thereby only said one memory cell in said one local block is activated, and one of said plurality of local blocks and one of said same number of said memory cells are specified by generating a block select signal for selecting one of said plurality of local blocks and an in-block memory cell select signal for selecting one of said same number of memory cells in a common manner among said plurality of local blocks, and logically operating said two select signals in each of said plurality of corresponding AND circuits.