Patent ID: 6552357
Filing Date: 2003-04-22
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate; a memory cell array formed in said semiconductor substrate, said memory cell array including bit lines and word lines crossing each other and memory cells arranged at intersections of the bit lines and the word lines and each having a transistor and a capacitor, said capacitor being formed on an interlayer insulation film that covers both said transistor and bit-line precharge circuits, and including a first electrode electrically connected through the interlayer insulation film to an impurity diffusion layer of the transistor and serving as a storage node, a capacitor insulation film formed on the first electrode, and a second electrode arranged on the capacitor insulation film; bit-line precharge circuits formed in said semiconductor substrate, to precharge the bit lines; and a plate electrode serving as the second electrode of each capacitor of the memory cells, extending from an area where the memory cell array is formed to an area where the bit-line precharge circuits are formed, and applying a power supply potential to said bit-line precharge circuits, said plate electrode being electrically connected to an impurity diffusion layer through a contact hole in the area where the bit-line precharge circuits are formed, said impurity diffusion layer serving as the power supply terminal of the bit-line precharge circuits, and said contact hole being formed through both the capacitor insulation film and the interlayer insulation film.