Patent ID: 6819616
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A method of buffering data for an integrated circuit memory device, the method comprising:converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits; providing the first even and odd data bits from the first and second conversion output nodes at first and second latch output nodes during a first period of time; providing the second even and odd data bits from the first and second conversion output nodes at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping; latching the first even and odd data bits at first and second buffer output nodes responsive to providing the first even and odd data bits at the first and second latch output nodes; and latching the second even and odd data bits at the first and second buffer output nodes responsive to providing the second even and odd data bits at the third and fourth latch output nodes.