Patent ID: 8072050
Filing Date: 2011-12-06
Classification: H01L

Abstract:
1. A semiconductor package comprising: a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being disposed in spaced relation to the die pad; a plurality of second leads, at least some of which include a downset formed therein, the second leads being disposed in spaced relation to the die pad; a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second leads; at least one passive component electrically connected to and extending between adjacent portions of the leadframe; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads, the semiconductor die and the passive component such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.