Patent ID: 6190957
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor apparatus comprising the steps of:forming, on a surface of a semiconductor substrate, an MIS transistor including a drian region and a source region each formed of an impurity diffusion region;forming a first insulation film on said semiconductor sustrate having said MIS transistor formed thereon;forming, in said first insulation film, first contact holes for exposing said drain region and said source region;embedding, in said first contact holes by a CVD method, a bit line contact plug having a lower end which is in contact with one of said drain region and said source region of said MIS transistor and a capacitor cntact plug having a lower end which is in contact with other one of said drain region and said source region of said MIS transistor;forming, above said first insulation film in which said bit line contact plug amd said capacitor contact plug are embedded, a ferroelectric capacitor having a lower eletrode, an interelctrode ferroelectric film and an upper elctrode;forming, above said first insulation film having said ferroelectric capacitor formed thereabove, a second insulation film;selectivity forming second contact holes in said second insulation film;forming, on said second insulation film and in said second contact holes, a capacitor electric wire for establishing a connection between said upper electrode of said ferroelectric capacitor and a top end of said capacitor contact plug, and a bit line contact plug electric wire connected to a top surface of said bit line contact plug;forming a third insulation film on said second insulation film including said capacitor electric wire and said bit line contact plug electric wire;forming a via hole in a portion corresponding to a portion above said bit line contact plug eletric wire of said third insulation film; andreflowing at least one material selected from the group consisting of Al, AlCu, AlCuSi and Cu to embed said via hole therewith, for forming a bit line on said third insulation film and in said via hole and then patterning the material to form a bit line on said third insulation film, after the step of forming said ferroelectric capacitor.