Patent ID: 6731526
Filing Date: 2004-05-04
Classification: G11C

Abstract:
A content addressable memory cell array comprising:a first memory cell array; a second memory cell array, each of the first and second memory cell arrays including a plurality of content addressable memory cells arranged in rows and columns, a plurality of search line pairs respectively connected to ones of the content addressable memory cells arranged in the columns, a plurality of match lines respectively connected to ones of the content addressable memory cells arranged in the rows, and a plurality of precharge circuits respectively connected to the match lines, each precharging the match line connected thereto, each of the content addressable memory cells including a coincidence comparison circuit comparing data stored in each of the content addressable memory cells with data on the search line pairs connected to each of the content addressable memory cells and providing a comparison result of coincidence or non-coincidence for the match line connected to each of the content addressable memory cells after being precharged; a plurality of storage circuits storing the comparison results on the match lines of the first memory cell array, respectively; and a plurality of control circuits provided correspondingly to the storage circuits and controlling the precharge circuits of the second memory cell array, each preventing the precharge circuit to be controlled from precharging the match line connected to the precharge circuit to be controlled when the corresponding storage circuit stores the comparison result of the non-coincidence.