Patent ID: 6874049
Filing Date: 2005-03-29
Classification: G06F

Abstract:
1. In a digital system of the type having at least first and second processors and at least one shared resource accessible to the processors via a system bus, the bus allowing only one bus transaction in any one clock cycle, a hardware semaphore circuit coupled to said system bus and configured to monitor shared resource accesses by said processors, the hardware semaphore circuit comprising: a semaphore cell coupled to the first and second processors via the system bus and configured to have a first state and a second state, the first state indicating that the shared resource is available for access and the second state indicating that the shared source is unavailable for access, and configured to be in the second state after being read by any processor and to change back to the first state after the shared resource is again made available for access; and an interrupt generation circuit coupled to the first and second processors via the system bus and coupled to an output of the semaphore cell, and configured to generate a semaphore interrupt signal to any processor requesting access to the shared resource whenever the semaphore cell changes from the second state back to the first state, the interrupt generation circuit comprising: