Patent ID: 7027332
Filing Date: 2006-04-11
Classification: G11C

Abstract:
1. A memory I/O driving circuit, suitable for use to drive multiple memory cards or multiple I/O in a memory card, the memory I/O driving circuit comprising: a register, receiving a new-coming data and a delayed clock, and exporting a current-existing data, wherein the delayed clock has a delay with respect to a clock; a pre-detecting circuit, receiving the current-existing data, the new-coming data, and a pre-enable signal and exporting an output signal, wherein the current-existing data is compared with the new-coming data, and the output signal indicates a disable state if the two data are the same, otherwise the output signal indicates an enable state, wherein the pre-enable signal is also used to enable or disable the pre-detecting circuit; an output driving circuit, receiving the current-existing data and an enabling signal, and exporting a first output signal; and a pre-driving circuit, receiving the output signal of the pre-detecting circuit, the new-coming data, and an enable control signal, and exporting a second output signal, wherein the first output signal and the second output signal are sent to a common node.