Patent ID: 6757349
Filing Date: 2004-06-29
Classification: H03L

Abstract:
A lock detection circuit for detecting whether a phase of a compared signal is locked with that of a reference signal based on first and second phase difference signals, wherein the first phase difference signal corresponds to the reference signal having a reference frequency obtained by frequency-demultiplying an oscillation signal having a predetermined frequency and the second phase difference signal corresponds to the compared signal having a preset frequency obtained by frequency-demultiplying a frequency signal of a voltage control oscillator, and wherein the first and second phase difference signals include a first information indicative of a phase difference between the reference signal and the compared signal and second information indicating of the signal which leads in phase, wherein one of the first and second phase difference signals, which leads in phase, is inverted faster than another one of the first and second phase difference signals, and then the both of the first and second phase difference signals are recovered substantially simultaneously after a predetermined time is elapsed, the lock detection circuit comprising:a clock generating unit for receiving the first and the second phase difference signals and generating a detecting clock signal in synchronism with the first and second phase difference signals, based on the first and second phase difference signals; and a lock detecting unit for receiving the first and the second phase difference signals and the detecting clock signal, and detecting whether or not the phase of the compared signal is locked with the phase of the reference signal based on the first and the second phase difference signals in synchronism with the detecting clock signal, and generating a lock detecting signal, wherein the lock detecting unit includes a status detecting circuit for receiving the detecting clock signal and generating a status signal based on the first and second phase difference signals in synchronism with the detecting clock signal.