Patent ID: 8261227
Filing Date: 2012-09-04
Classification: G06F

Abstract:
1. A computer-implemented method, the method comprising: obtaining a circuit design, the circuit design is responsive to input signals, the circuit design defines connections between combinational elements, memory elements, and input signals; selecting one or more combinational logic input signals of the circuit design; identifying at least one cut-off point in the circuit design with respect to the selected combinational logic input signals, wherein said identifying is performed by using a computer, wherein value of the cut-off point is defined as a combinational function of a set of combinational logic input signals, the set of combinational logic input signals does not comprise any of the selected combinational logic input signals, wherein said identifying comprises identifying the at least one cut-off point from a selected connection of the circuit design wherein said identifying comprises traversing the connections of the circuit design to identify the at least one cut-off point, wherein said traversing begins in the selected connection, wherein said traversing stops at combinational logic input signals, wherein combinational logic input signals are input signals and output signals of memory elements; wherein said traversing comprises: approximating the circuit design by defining an approximated circuit design, wherein the approximated circuit design is retained in a storage device, wherein in the approximated circuit design the at least one cut-off point is defined as a value of a new input signal.