Patent ID: 7622952
Filing Date: 2009-11-24
Classification: G06F,H03K

Abstract:
1. An integrated circuit device comprising: core circuitry having an outer periphery; a plurality of IO circuits disposed outside of said outer periphery, said IO circuits being grouped in a multiplicity of groups, each of which groups includes a respective subplurality of adjacent ones of said IO circuits; and clock signal routing circuitry disposed between said outer periphery and each of said groups, said routing circuitry including, in association with each of said groups, (1) a plurality of first conductors, each of which extends past all of the IO circuits in the associated group, and each of which receives a respective one of a plurality of clock signals from the core circuitry, (2) a plurality of second conductors, each of which extends across all of the first conductors to a respective one of the IO circuits in the associated group, and (3) a mask-programmable via option at each intersection between a first conductor and a second conductor.