Patent ID: 6505305
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A computer system comprising:a bus subsystem for transferring digital information; a processing unit for processing the digital information; a mass storage device for storing the digital information and cooperatively coupled to the bus subsystem to transmit and receive the digital information; a memory module array having multiple memory modules, each of the memory modules having multiple memory blocks for storing the digital information transmitted or received by the mass storage device; a memory controller for controlling transfer, between the bus subsystem, the processing unit and the memory module array, of the digital information transmitted or received by the mass storage device; and a memory fail-over subsystem cooperatively coupled to fail-over individual memory blocks, and the digital information stored therein, of one or more of the memory modules; and an error monitoring circuitry cooperatively coupled to transmit error data to the memory controller, wherein the memory fail-over subsystem fails-over an individual memory block when the error data for the individual memory block exceeds a permissible threshold, and accesses to remaining memory blocks in the same memory module as the failed-over memory block are satisfied by the remaining memory blocks in the same memory module.