Patent ID: 6072776
Filing Date: 2000-06-06
Classification: H04L,H04Q

Abstract:
A fault self-supervising system of a cell processor in an ATM network, including an arithmetic circuit serving as a supervising object in the cell processor, said arithmetic circuit outputting a supervising information signal CHK, made by processing an input cell, said supervising information signal indicating an operating condition of said arithmetic circuit, said fault self-supervising system comprising:connection supervising section for supervising a main signal cell flow and setting connection information having a desired combination of a virtual path identifier (VPI) and a virtual channel identifier (VCI) and detecting a cell as insertion of a supervising cell;supervising result expected value generation section for making a supervising information pattern as a supervising expected value based on said connection information and outputting the supervising expected value;supervising cell generation section for overwriting the supervising cell having a set combination of VPI and VCI based on the supervising expected value from said supervising result expected value generation section;supervising cell application section for overwriting the supervising cell from said supervising cell generation section on said cell for inserting the supervising cell in the main signal cell flow in a stage preceding said arithmetic circuit;supervising cell termination section for removing said supervising cell from the main signal cell flow and outputting said main signal cell flow having a cell pattern before being overwritten by said supervising cell application section, said supervising cell termination section being disposed in a stage subsequent to said arithmetic circuit;supervising result comparison and collation section for detecting a fault of said arithmetic circuit by comparing and collating said supervising information signal CHK from said arithmetic circuit with said supervising expected value from said supervising result expected value generation section, said supervising result comparison and collation section being disposed subsequent to said arithmetic circuit.