Patent ID: 6704895
Filing Date: 2004-03-09
Classification: G01R,G06F

Abstract:
An integrated circuit comprising:A. microprocessor circuitry including input leads, output leads, and internal logic, the internal logic including an arithmetic and logic unit and an accumulator; and B. a test access port connected to a test mode select signal, a test clock signal, a test reset signal, a test data in signal, and a test data out signal, the test access port including: i. a tap controller connected to the test mode select signal, the test clock signal and the test reset signal; ii. an instruction register connected to the test data in signal, the test data out signal, and the tap controller; iii. a boundary scan register connected to the test data in signal, the test data out signal and the instruction register, the boundary scan register including a boundary scan serial scan path of registers connected to the input leads and output leads of the microprocessor circuitry; iv. a bypass register connected to the test data in signal, the test data out signal and the instruction register; and v. an emulation register connected to the test data in signal, the test data out signal and the instruction register, the emulation register including an emulation serial scan path of registers connected to the internal logic of the microprocessor circuitry and separate from the boundary scan serial scan path of registers.