Patent ID: 6536027
Filing Date: 2003-03-18
Classification: G06F

Abstract:
A process for extending a metal wire for a feature in an integrated circuit cell, comprising steps of:a) defining a grid for a metal layer of the cell, the grid having a plurality of grid elements each having x and y coordinates; b) assigning one of a first, second and third designators to each grid element, the first designator being assigned to grid elements representing the metal wire being extended, the second designator being assigned to grid elements representing blockages to extension of the metal wire, and the third designator being assigned to grid elements that represent neither the metal wire being extended nor blockages to the extension of the wire metal; c) identifying grid elements having the third designation as grid elements that are neighbors to grid elements having the second designation; and d) defining a path through grid elements having the third designation, which are not neighbors to grid elements having the second designation, between a boundary of the cell and grid elements having the first designation.