Patent ID: 6528842
Filing Date: 2003-03-04
Classification: G11C,H01L

Abstract:
An electrically erasable, programmable read-only memory cell, comprising:a first insulated gate metal-oxide semiconductor having a source region and a drain region in a substrate, and further having an insulated gate deposited in a first oxide layer above the substrate; a first conductive plate located above the insulated gate, the first conductive plate being electrically isolated in its own oxide layer; a second conductive plate located above the first conductive plate and being electrically isolated therefrom and from the insulated gate in its own oxide layer such that the first and second conductive plates form a capacitor having a capacitance substantially greater than an inherent capacitance between the insulated gate and the substrate so as to define a capacitance ratio; commutating means for electrically commutating the first conductive plate with the insulated gate so as to form a floating gate; and, electrical contact means for charging the capacitor.