Patent ID: 7884472
Filing Date: 2011-02-08
Classification: B23K,B41M,H01L

Abstract:
1. A semiconductor package primarily comprising: a substrate having a top surface and a bottom surface and including a circuit and a solder mask on the bottom surface, wherein the bottom surface includes a circuit-free zone, and the solder mask covers the circuit and the circuit-free zone; a chip disposed on the top surface of the substrate; a substrate ID code consisting of a plurality of first laser marks located on the bottom surface of the substrate away from the circuit; an encapsulant formed on the top surface of the substrate to encapsulate the chip; and a product code consisting of a plurality of second laser marks inscribed in the encapsulant on the top surface; wherein the encapsulant is further partially formed on the bottom surface of the substrate, wherein the substrate ID code is inscribed in the portion of the encapsulant on the bottom surface.