Patent ID: 7145803
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: plural word lines; plural drain lines; plural source lines; a memory array including plural memory cells formed from a field effect transistor having a gate, a drain, a source and a floating gate, said gate of each of said plural memory cells being connected to any of said plural word lines, said drain of each of said plural memory cells being connected to any of said plural drain lines, said source of each of said plural memory cells being connected to any of said plural source lines; a data write circuit which receives a first control signal and write data and supplies a source drive voltage to said source line when data is written into said memory cell; a write control circuit which receives a second control signal supplied later than said first control signal and supplies a drain drive voltage based on said second control signal to said drain line when data is written into said memory cell; and a word line drive circuit which receives an address signal and said second control signal, and supplies a word line drive voltage based on said second control signal to said word line selected according to said address signal; wherein said write control circuit outputs said drain drive voltage at a high level for data write via said drain line to said memory cell selected by said word line drive circuit when a data write operation is commanded by said second control signal, and outputs said drain drive voltage at a low level when a data write operation is not commanded by said control signal, and said data write circuit generates a write voltage corresponding to a logical value of data to be written into said selected memory cell based on said drain drive voltage outputted from said write control circuit, and supplies said write voltage as said source drive voltage via said source line to said selected memory cell when a data write operation is commanded by said first control signal.