Patent ID: 6603361
Filing Date: 2003-08-05
Classification: E05Y,G11B,H03L

Abstract:
A circuit that synchronizes an output clock signal to a second clock signal, comprising:a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal; wherein the frequency locked loop circuit includes a frequency discriminator and a controlled signal generator; and wherein the controlled signal generator includes a down counter that provides the output clock signal and a saturated up/down counter, the saturated up/down counter receiving a signal from the frequency discriminator and providing a signal to the down counter.