Patent ID: 7230336
Filing Date: 2007-06-12
Classification: H01L

Abstract:
1. An electronic structure, comprising: a semiconductor substrate; a first layer on and in direct mechanical contact with the semiconductor substrate, wherein the first layer includes a plurality of electrically conducting regions, wherein the electrically conductive regions each consist of an electrically conductive material selected from the group consisting of tungsten and silicon, and wherein the electrically conducting regions are separated by insulative regions, wherein each insulative region comprises an insulative material, wherein a bottom surface of each electrically conductive region is coplanar with a bottom surface of the first layer, and wherein a top surface of each electrically conductive region is coplanar with a top surface of the first layer; a dual damascene copper interconnect wiring level having a plurality of damascene copper wires within one or more corresponding damascene contact vias wherein each damascene copper wire is in electrically conductive contact with a corresponding conducting region of the electrically conducting regions; an etch stop layer above the first layer, wherein the etch stop layer comprises etch stop regions, wherein the etch stop regions are mechanically separated from each other by the damascene contact via, wherein each etch stop region has a first bounding surface such that said first bounding surfaces are mutually coplanar and in direct mechanical contact with the electrically conductive material of the first layer, and wherein the etch stop layer includes an etch stop insulative material; a first insulator region of an insulator layer on a first portion of the etch stop layer and contacting a first surface of the damascene copper interconnect, wherein the first insulator region includes an electrically insulative material; a second insulator region of the insulator layer on a second portion of the etch stop layer and contacting a second surface of the damascene copper interconnect, wherein the second insulator region includes the electrically insulative material; and a third insulator region on a third portion of the etch stop layer and disposed between the damascene copper interconnect and the third portion of the etch stop layer, wherein the third insulator region includes the electrically insulative material, wherein the damascene copper interconnect wiring level comprises a dual damascene copper interconnect, and wherein the dual damascene copper interconnect comprises: