Patent ID: 8988954
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A memory device comprising: an array of memory cells arranged as a plurality of rows and columns, each row of memory cells being coupled to an associated read word line, each column of memory cells forming at least one column group, and the memory cells of each column group being coupled to an associated read bit line; word line driver circuitry configured, during a read operation, to issue an asserted read word line pulse signal on the read word line coupled to an addressed row of the array so as to activate the memory cells within that addressed row whilst the read word line pulse signal is asserted; precharge circuitry configured, prior to the read operation, to precharge each read bit line to a first voltage level; during the read operation the voltage on the read bit line associated with any column group containing one of the activated memory cells being arranged to transition towards a second voltage level if a data value stored in that activated memory cell has a first value; sense amplifier circuitry connected to the associated read bit line of each column group, and configured for each activated memory cell to determine that that activated memory cell stores said first value if the voltage on the associated read bit line transitions to a trip voltage level between said first and said second voltage levels whilst the read word line pulse signal is asserted, and to determine that that activated memory cell stores a second value if the voltage on the associated read bit line does not transition to said trip voltage level whilst the read word line pulse signal is asserted; bit line keeper circuitry coupled to each read bit line and responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level; and keeper pulse signal generation circuitry configured to assert the keeper pulse signal at a selected time after the read word line pulse signal is asserted, the selected time being selected such that if an activated memory cell stores said first value, the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted, and such that if an activated memory cell stores said second value, leakage current within the memory cells of the column group coupled to the associated read bit line will not have caused the voltage on the associated read bit line to have transitioned to the trip voltage level before the keeper pulse signal is asserted.