Patent ID: 6421770
Filing Date: 2002-07-16
Classification: G06F

Abstract:
A buffer memory configuration, comprising:a data transmitter, a data receiver, and a buffer memory connected for data communication signal lines between said data transmitter and said data receiver; said buffer memory including a memory for data buffering, an address/data bus connected to said memory, and a memory management unit controlling reading from and writing to said memory via said address/data bus; said memory being mapable onto an address space exactly half as large as said memory, a first half of said memory defining a first memory page and a second half of said memory defining a second memory page, each address in the address space being assigned a respective memory location on each of said memory pages; and said memory management unit generating a significant bit assigning in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page.