Patent ID: 6091095
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A semiconductor storage comprising:a plurality of memory cells;a pair of bit lines connected to said plural memory cells and which are formed on a semiconductor substrate;a first impurity layer of the first conductive type connected to one of said pair of bit lines and which is formed in said semiconductor substrate;a second impurity layer of the first conductive type connected to the other of said pair of bit lines and which is formed in said semiconductor substrate;a third impurity layer of the first conductive type formed in said semiconductor substrate;a fourth impurity layer of the first conductive type formed in said semiconductor substrate;a fifth impurity layer of the first conductive type to which a predetermined potential is applied and which is formed in said semiconductor substrate;a sixth impurity layer of the first conductive type to which said predetermined potential is applied and which is formed in said semiconductor substrate;a first conductive layer formed over said semiconductor substrate between said first impurity layer and said third impurity layer and which is connected to the other of said pair of bit lines;a second conductive layer which is formed over said semiconductor substrate between said second impurity layer and said fourth impurity layer and which is connected to one of said pair of bit lines;a third conductive layer formed over said semiconductor substrate between said third impurity layer and said fifth impurity layer and to which a sense amplifier actuating signal is applied; anda fourth conductive layer formed over said semiconductor substrate between said fourth impurity layer and said sixth impurity layer and to which said sense amplifier actuating signal is applied.