Patent ID: 6930924
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells; a first switch circuit; and a control circuit, wherein each of said plurality of memory cells has a control terminal, a first terminal and a second terminal, a channel between said first terminal and said second terminal, and an electron storage area between said control terminal and said channel, wherein said control terminal of a first memory cell of said plurality of memory cells couples to a first word line, wherein said first terminal of said first memory cell is coupled to a first bit line of said plurality of bit lines and said second terminal of said memory cell is coupled to a first signal line, wherein said first bit line is coupled to a first sense amplifier via said first switch circuit, and wherein in a writing operation for writing data to said first memory cell, said control circuit controls charging of a first voltage to said first signal line, turning a switch of said first switch circuit to ON for connecting said first bit line to said first terminal of said first memory cell, coupling said first bit line to a ground level voltage, and then supplying a write voltage to said first word line coupled to said control terminal of said first memory cell.