Patent ID: 8947945
Filing Date: 2015-02-03
Classification: G06K,G11C

Abstract:
1. A memory card, comprising: a first surface; a second surface opposite to the first surface; a first group of conductive pins set on the first surface; a second group of conductive pins set on the second surface; a buffer connected to the first group of conductive pins through a first channel and connected to the second group of conductive pins through a second channel; a NAND gate comprising a first input connected to a ground pin of the first group of conductive pins, a second input, and an output connected to the buffer; an inverter connected between a ground pin of the second group of conductive pins and the second input of the NAND gate; a storage medium connected to the buffer; and a control chip connected between the buffer and the storage medium, to control data transmission between the buffer and the storage medium; wherein an order of pins of the first group of conductive pins located on the first surface from left to right is same with an order of pins of the second group of conductive pins located on the second surface from left to right; the output of the NAND gate is connected to an enable pin of the buffer; when the enable pin of the buffer receives a high level signal outputted from the NAND gate, the first channel is turned on, and data is transmitted between the buffer and the first group of conductive pins; when the enable pin of the buffer receives a low level signal outputted from the NAND gate, the second channel is turned on, and data is transmitted between the buffer and the second group of conductive pins.