Patent ID: 8018030
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a chip; and a low dielectric constant film having a relative dielectric constant of less than 3.5 and a plurality of seal rings, each of the seal rings forming a moisture blocking wall in closed loop form in a plan view, wherein each of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a corner of the chip, one of the seal rings is an outermost seal ring in the moisture blocking wall formed by the plurality of said seal rings, each of the seal rings comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length length wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the outermost seal ring from the center of the chip, wherein a passivation film covers said low dielectric constant film, said seal ring and said sacrifice pattern and includes a planar portion and a ridged portion, and wherein the planar portion of said passivation film is formed above said sacrifice pattern and the ridged portion of said passivation film covers a top of each of said seal rings and a part of a side wall of each of said seal rings.