Patent ID: 6775761
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A superscalar processor configured to execute, out of a program order, one or more instructions from a group of instructions comprising:a superscalar register renaming circuit configured to associate unique addresses with each instruction from the group of instructions, wherein the superscalar register renaming circuit is also configured to associate respective unique addresses with more than one instruction from the group of instructions approximately simultaneously; a plurality of functional units configured to execute instructions from the group of instructions out of the program order; a buffer configured to store execution results of instructions from the group of instructions, wherein the unique address associated with each instruction indicates a static location in the buffer where an execution result for each instruction is to be stored; an array including a plurality of array locations referenced to provide execution results of instructions that have been retired; a retirement control block configured to determine whether instructions from the group of instructions that are executed can be retired; and an instruction retirement unit configured to retire approximately simultaneously a group of instructions that can be retired by approximately simultaneously associating an execution result of each instruction in the group of instructions that can be retired to array locations in the register array, wherein the execution result of each instruction in the group of instructions that can be retired are respectively stored in static locations in the buffer.