Patent ID: 6166419
Filing Date: 2000-12-26
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:a semiconductor substrate;a first element separation insulating film formed on said semiconductor substrate to define a first element region;a low withstand voltage MOS transistor formed in said first element region, said low withstand voltage MOS transistor having a first gate electrode coupled with a first power voltage;a second element separation insulating film formed on said semiconductor substrate to define a second element region, the second element separation insulating film having a thickness greater than a thickness of the first element separation insulating film; anda high withstand voltage MOS transistor formed in said second element region, said high withstand voltage MOS transistor having a second gate electrode coupled with a second power voltage higher than said first power voltage, a thickness of said second gate electrode being greater than a thickness of said first gate electrode.