Patent ID: 6309933
Filing Date: 2001-10-30
Classification: H01L

Abstract:
A method of fabricating a semiconductor transistor device, comprising the steps of:providing a semiconductor structure having an upper silicon layer, with a pad dielectric layer thereover;depositing and patterning a lower SiN layer over said pad dielectric layer to define a lower gate area;etching said pad dielectric layer and said upper silicon layer within said lower gate area to form a lower gate trench having a predetermined width;forming a lower gate portion within said lower gate trench;forming an upper oxide layer over said lower SiN layer;forming an upper SiN layer over said upper oxide layer;etching said upper SiN layer to define an upper gate trench having a predetermined width greater than said lower gate trench predetermined width;forming an upper gate portion within said upper gate trench; wherein said lower and upper gate portions form a T-shaped gate;removing said etched upper SiN, upper oxide, and lower SiN layers to expose said T-shaped gate extending above said pad dielectric layer;forming an uppermost oxide layer over said exposed T-shaped gate;forming SiN sidewall spacers adjacent the exposed vertical side walls of said lower polysilicon gate portion; andforming silicide regions over said source/drain regions.