Patent ID: 9164920
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A processor comprising: multiple processing cores; and memory management logic coupled to the multiple processing cores, the memory management logic to translate a guest virtual address to a first guest physical address and to translate the first guest physical address to a first host physical address in response to a memory access request including the guest virtual address, the memory management logic comprising: a first translation table base register to store a base address of a first multilevel translation table, the first multilevel translation table to provide a mapping of guest virtual addresses to guest physical addresses; a second translation table base address register to store a base address of a second multilevel translation table, the second multilevel translation table to provide a mapping of guest physical addresses to host physical addresses; address translation logic coupled to the first translation table base register and to the second translation table base register, the address translation logic to access the second multilevel translation table to translate guest physical addresses formed during a walk of the first multilevel translation table to host physical addresses; and access logic to enable use of the second multilevel translation table and to prevent contents of a page in memory from being executed based on a permission bit field of a page table entry, the permission bit field to indicate whether the contents of the page may be executed.