Patent ID: 8797081
Filing Date: 2014-08-05
Classification: H03K,H03L

Abstract:
1. A circuit comprising: an FPGA, which comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; a digitally controlled oscillator, which outputs a clocking signal for said FPGA, wherein: the FLL-circuit is designed in order to register a first number of clock signals from said digitally controlled oscillator during a second number of periods of the reference clock; the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of said digitally controlled oscillator; the frequency of the digitally controlled oscillator is controlled via at least one resistance value, on which the feedback signal acts; the resistance value is adjustable via a series of individual resistors, which, for the reduction of the resistance, can be selectively bypassed with respect to ground, at least in part; the series of the resistors that can be selectively bypassed account for, not more than 10% of the total value of the resistance; the series of resistors that can be bypassed comprises at least 10 individual resistors; and the frequency of the digitally controlled oscillator is, due to the feedback signal, not variable by more than 5%.