Patent ID: 6319750
Filing Date: 2001-11-20
Classification: H01L,H05K

Abstract:
A layout method for a semiconductor package substrate, comprising:(1) defining a plurality of package sites on the substrate, each neighboring pair of package sites being delimited by a singulation line;(2) defining at least one die-mounting area within each of the package sites;(3) within each package site, defining at least one row of via lands alongside the singulation line, with the opposite row of via lands within the neighboring package site across the singulation line being substantially aligned crosswise in line;(4) interconnecting all the via lands alongside the singulation line to a common plating bus, which includes:(i) a plurality of crosswise segments, each of which serves to interconnect one crosswise-opposite pair of the via lands across the singulation line; and(ii) a plurality of diagonal segments, each of which serves to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line.