Patent ID: 7096403
Filing Date: 2006-08-22
Classification: H03M

Abstract:
1. An iterative concatenated code decoding circuit, employing a concatenated code concatenating an outer code and an inner code, in which a coding ratio of each of said inner code and said outer code is respectively represented by (code-word length redundancy check length)/(code-word length), said inner code having a higher coding ratio than said outer code, said decoding circuit comprising: an inner decoder for decoding said inner code having a high coding ratio; and an outer decoder for decoding said outer code having a low coding ratio, wherein: said inner decoder and said outer decoder are disposed at multiple stages and said outer decoder comprises a circuit configuration different than a circuit configuration of said inner decoder to locate and correct errors, said concatenated code comprises a BCH (Bose-Chaudhuri-Hocciuenghem) code containing a Reed-Solomon code, said outer decoder employs a read-only memory to acciuire an inner code modification syndrome coefficient indicating a variation between a syndrome coefficient for output data of said inner decoder at a former stage and a syndrome coefficient for input data of said inner decoder at a latter stage when errors are corrected, and the inner decoders at a second and ensuing stages make the decoding on a basis of a result of adding a syndrome coefficient of the inner decoder at the former stage and said inner code modification syndrome coefficient calculated by the outer decoder at the former stage.