Patent ID: 7985667
Filing Date: 2011-07-26
Classification: G11C,H01L

Abstract:
1. A method for patterning a semiconductor device, comprising: forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate; forming an upper electrode conductive layer used as a first hard mask over the stack structure; forming a second hard mask layer over the upper electrode conductive layer; selectively etching the second hard mask layer to form a second hard mask pattern; etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode; etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier; and disposing a buffer layer between the upper electrode conductive layer and the second hard mask before forming of the second hard mask layer.