Patent ID: 6094371
Filing Date: 2000-07-25
Classification: G11C

Abstract:
A ferroelectric memory device comprising ferroelectric memory cell array in rows and columns, each ferroelectric memory cell of a part of said memory cell array including:a ferroelectric capacitor having first and second plate electrodes, said second plate electrode being connected to a plate line;a transfer gate having a control input and a current pass, said current pass being connected between a bit line and said first plate electrode; anda coupling capacitor connected between said first plate electrode and a common line,wherein said bit line is common to memory cells in the same column, said plate line is common to memory cells in the same row, and said common line is common to memory cells in the same row,wherein said ferroelectric memory device further comprising:a first erase switch having a control input and a current pass, said current pass thereof being connected between said plate line and a conductor at a first potential, said first erase switch being turned on in response to an erase signal; anda second erase switch having a control input and a current pass, said current pass thereof being connected between said common line and a conductor at a second potential, said second erase switch being turned on in response to said erase signal.