Patent ID: 7133484
Filing Date: 2006-11-07
Classification: H03K,H03L

Abstract:
1. A clock generator comprising: a phase-locked loop which generates a plurality of oscillating clock signals of a first frequency, each of which mutually has a constant phase difference averagely distributed over a clock cycle of 360 degrees; and a sampling circuit coupled to said phase-locked loop and comprising at lease one stage of sampler comprising at least one sampling unit, each of said sampling unit receives two oscillating clock signals of an input frequency and one selection signal of said input frequency with a phase being an average of the phases of said two oscillating clock signals of said input frequency, and samples said two oscillating clock signals of said input frequency according to said selection signal to generate a clock signal of a frequency as twice as said input frequency, for providing for the sampler of next stage as either an input signal or a selection signal for a sampling unit thereof, so as to generate a clock signal of a frequency being 2