Patent ID: 6178125
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:(a) a regular memory cell region, including(a-1) a plurality of regular memory cell groups each including a plurality of regular memory cells;(b) a main address decoder provided corresponding to said regular memory cell region and selecting one of said regular memory cell groups in response to an address signal;(c) a spare memory cell region, said spare memory cell region including(c-1) a plurality of spare memory cell groups each including a plurality of spare memory cells and usable in place of said regular memory cell groups by substitution;(d) a spare address decoder provided corresponding to said spare memory cell region and selecting one of said spare memory cell groups in response to a spare address signal;(e) a substitution control circuit holding a substitution address data corresponding to a substitution address of said regular memory cell group to be substituted by said spare memory cell group, inactivating said main address decoder and supplying said spare address signal as an output when said address signal matches with said substitution address, said substitution control circuit including,(e-1) a plurality of address setting portions provided corresponding to said plurality of spare memory cell groups, respectively, and holding said substitution address data, and(e-2) a setting portion select circuit selecting one of said plurality of address setting portions according to a setting portion select signal,said setting portion select circuit having a holding circuit holding in a non-volatile manner, information that substitution operation of substituting said regular memory cell group with said spare memory cell group has been performed and determining an order of priority of use of said plurality of address setting portions corresponding to said setting portion select signal according to the information held by said holding circuit.