Patent ID: 6194270
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A process for manufacturing an electrically programmable non-volatile memory device including a first MOSFET and an electrically programmable non-volatile memory cell having a floating-gate MOS transistor and a second MOSFET capable of sustaining gate voltages higher than sustainable by the first MOSFET, said process comprising:forming a first gate oxide layer for the floating-gate MOS transistor, a second gate oxide layer for the first MOSFET, and a third gate oxide layer for the second MOSFET, the first gate oxide layer including a tunnel oxide region;forming over a surface of a semiconductor material a first layer of oxide;selectively removing the first layer of oxide from a region of said surface dedicated to the first MOSFET, but not from regions dedicated to the floating-gate MOS transistor or the second MOSFET;forming a second layer of oxide over the first layer of oxide and over said region dedicated to the first MOSFET;removing the first and the second layer of oxide only from the tunnel oxide region of the floating-gate MOS transistor; andforming over the second layer of oxide and over said tunnel region oxide for the floating-gate MOS transistor a tunnel oxide layer,wherein said third gate oxide layer and said first oxide later, except in the tunnel oxide region, are formed by the superposition of the first layer of oxide, the second layer of oxide and the tunnel oxide layer, said second gate oxide layer being formed by the superposition of the second layer of oxide and the tunnel oxide later.