Patent ID: 8614507
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: lower interconnection patterns that are connected to a plurality of drain nodes on a substrate, wherein each of the lower interconnection patterns has a respective center point; and upper interconnection patterns that are connected to the lower interconnection patterns, wherein each of the upper interconnection patterns has a respective center point, wherein the center points of the upper interconnection patterns are arranged at positions where an absolute value of (n−m) is an even number among coordinate sets given by (n*L wherein the center points of the lower interconnection patterns are arranged at positions where the absolute value of (n−m) is an odd number among the coordinate sets given by (n*L wherein n and m are natural numbers, wherein L wherein * represents a multiplication operation, wherein each lower interconnect pattern is in electrical contact with at least two of the drain nodes.