Patent ID: 8441839
Filing Date: 2013-05-14
Classification: G11C,H01L

Abstract:
1. A cross point variable resistance nonvolatile memory device comprising: a substrate; a memory cell array formed on said substrate and having a plurality of memory cells each of which includes a variable resistance element and a bidirectional current steering element, said variable resistance element reversibly changing between at least two states including a low resistance state and a high resistance state by application of voltages of different polarities, and said current steering element being connected in series with said variable resistance element and having nonlinear current-voltage characteristics, a plurality of global bit lines each of which is provided for a different one of said plurality of vertical array planes; a plurality of first bit line selection switch elements each of which is provided for a different one of said plurality of vertical array planes, and has one end connected to the first via; a plurality of second bit line selection switch elements each of which is provided for a different one of said plurality of vertical array planes, and has one end connected to the second via; a plurality of bidirectional current limiting circuits each of which is provided for a different one of said plurality of vertical array planes, said bidirectional current limiting circuit being positioned between a global bit line corresponding to said vertical array plane and each of an other end of a first bit line selection switch element corresponding to said vertical array plane and an other end of a second bit line selection switch element corresponding to said vertical array plane, and limiting each bidirectional current flowing between said global bit line and each of said first bit line selection switch element and said second bit line selection switch element; a current limiting control circuit that controls said bidirectional current limiting circuit; a global bit line decoder and driver that supplies a signal for selecting a memory cell and writing or reading said memory cell, to any of said plurality of global bit lines; a word line decoder and driver that supplies a signal for selecting said memory cell and writing or reading said memory cell, to any of said plurality of word lines; a write circuit that writes data to said memory cell selected by said global bit line decoder and driver and said word line decoder and driver; a read circuit that reads data from said memory cell selected by said global bit line decoder and driver and said word line decoder and driver; and a control circuit that controls said global bit line decoder and driver, said word line decoder and driver, said write circuit, and said read circuit, wherein said bidirectional current limiting circuit includes an N-type current limiting element and a P-type current limiting element that are connected in parallel with each other, said N-type current limiting element including an NMOS transistor, and said P-type current limiting element including a PMOS transistor, and when changing said selected memory cell to the low resistance state, said current limiting control circuit activates one current limiting element, from among said N-type current limiting element and said P-type current limiting element, that is more capable of limiting an amount of current flowing in said selected memory cell.