Patent ID: 6724249
Filing Date: 2004-04-20
Classification: H03F

Abstract:
A circuit to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels, comprising:means to convert the input signal into ideal PDM (Pulse Density Modulated) output pulses; means to generate a â€œpulse polarityâ€  and a digital â€œpulse length selectâ€  signal, where said pulse length select signal represents multiple pulse-area values; means to define a set of output pulse area reference values, one for each step of said multi-level output; a length-of-pulse-integrator to determine the pulse stop time, based on the pulse start time (clock), on said digital â€œpulse length selectâ€  signal and based on said output pulse area reference values; a pulse generator providing the multi-level output pulses to said power driver, using said pulse start and pulse stop signals; means for a Class-D power driver to drive voltage into an output load, controlled by said power driver control pulses; and means for an output load as the amplifier output's target.