Patent ID: 7986573
Filing Date: 2011-07-26
Classification: G11C

Abstract:
1. A storage system, comprising: a memory array comprising a set of storage elements and an associated set of word lines, including a selected word line, the set of storage elements includes first and second storage elements in communication with the selected word line; first and second bit lines associated with the first and second storage elements, respectively; and one or more control circuits, the one or more control circuits, to perform an iteration of a multiple-iteration programming operation: (a) connect a power supply at an initial level to the first bit line to pre-charge a voltage of the first bit line to the initial level, the initial level prevents programming of the first storage element, while pre-charging the second bit line to a level which provides a slow programming mode for the second storage element, and (b) subsequently: (i) connect a power supply at a stepped up level to the first bit line while floating the second bit line, a difference between the stepped up level and the initial level of the first bit line causes capacitive coupling to the second bit line which raises a voltage of the second bit line, thereby slowing programming of the second storage element, and (ii) apply a program pulse to the selected word line when the voltage of the second bit line is coupled higher.