Patent ID: 6625630
Filing Date: 2003-09-23
Classification: G06F

Abstract:
A digital signal processor (DSP) comprising:at least two multipliers wherein each multiplier is operative to receive either of a real and an imaginary first data value and either of a real and an imaginary coefficient value and multiply said data and coefficient values to provide a multiplication result; at least two three-input arithmetic logic units (ALU) wherein each ALU is operative to receive each of said multiplication results from said multipliers and either of a real and an imaginary second data value and perform any of addition and subtraction upon each of said multiplication results and said second data value to provide a Fast Fourier Transform (FFT) calculation result; at least two first-cycle registers wherein each first-cycle register is operative to receive said FFT calculation result from one of said ALUs calculated during a first processing cycle of two consecutive processing cycles; at least two second-cycle registers wherein each second-cycle register is operative to receive said FFT calculation result from one of said ALUs calculated during a second processing cycle of said two consecutive processing cycles; and multiplexing apparatus operative to selectably retrieve and forward for storage in memory said FFT calculation results from one of said first-cycle registers and one of said second-cycle registers during a first memory-write cycle of two consecutive memory write cycles and said FFT calculation results from the other of said first-cycle registers and the other of said second-cycle registers during a second memory-write cycle of said two consecutive memory write cycles.