Patent ID: 6865645
Filing Date: 2005-03-08
Classification: G06F

Abstract:
1. A method of supporting programs that include instructions that modify subsequent instructions in a processor system with a storage controller and a central processing unit including an execution unit, an instruction unit, and a plurality of caches including separate instruction cache and operand cache, the method comprising: subjecting said instruction cache and said operand cache of said central processing unit to a cache coherency protocol with interlocks on cache block access including; allowing shared read access by said instruction cache and said operand cache to a cache block if said cache block has read only status in said instruction cache and said operand cache; allowing read and write access by said operand cache and preventing access by said instruction cache to said cache block if said cache block has exclusive status in said operand cache; and interlocking access to said cache block by said operand cache with exclusive status in said operand cache if said cache block has read-only status in said instruction cache; interfacing said cache coherency protocol with a processor system cache coherency protocol employed by said storage controller, wherein said cache coherency protocol operates in cooperation with existing cache handling requirements; buffering cache block addresses in a register-file in said instruction cache corresponding to fetched unexecuted instructions in an instruction buffer in said instruction unit; when data is required to be stored or updated, evaluating a cache block's status for a desired storage address in said operand cache and transmitting a request for exclusive status to said storage controller and transmitting a cross interrogate signal to said instruction cache; allowing an operand store once exclusive status is obtained front said storage controller and a response from said cross interrogate signal; discarding and refetching data in said instruction cache if an associated cache block in said instruction cache matches said desired storage address; when instruction fetch is requested, providing said instruction cache read-only status for a requested cache block; discarding and refetching data in said instruction buffer and re-buffering cache locations in said register if an instruction stream of said execution unit changes; discarding data in said instruction buffer and discarding said cache locations in said register if said execution unit completes execution of fetched instructions; wherein said instruction cache responds to said cross interrogate signal by: generating a response to said cross interrogate signal and a hit signal indicative of an address match if said desired storage address matches an associated cache block in said instruction cache and if a location of said associated cache block matches any valid entry in said register, otherwise responding with a no bit signal; and invalidating said associated cache block in said instruction cache if said desired storage address matches.