Patent ID: 8962455
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a gate trench in a substrate; forming a gate insulating layer on bottom and side surfaces of the gate trench; forming a gate barrier material layer and a gate electrode material layer on bottom and side surfaces of the gate insulating layer and a top surface of the substrate; removing the gate barrier material layer and the gate electrode material layer from the substrate to form a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the top surface of the substrate within the gate trench; removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth; removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth; and forming a gate capping layer to cover the gate barrier layer and the gate electrode and fill the gate trench.