Patent ID: 6127229
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A process for fabricating an electrically erasable and programmable read only memory integrated circuit device having a split gate memory cell comprising:providing a silicon substrate having spaced and parallel recessed oxide regions that isolate component regions, the oxide regions projecting above the top surface of said substrate,forming a thin gate oxide layer on the top surface of said silicon substrate,depositing a first conformal layer of polysilicon over said thin oxide layer and projecting oxide regions,chemical-mechanical polishing the top surface of the substrate to remove the projections of polysilicon over the field oxide regions,depositing a layer of silicon nitride over the resultant planar surface of said layer of polysilicon,forming elongated openings in the silicon nitride layer that are perpendicular to said field oxide regions that define the position of the floating gates,oxidizing the exposed polysilicon through said openings in the silicon nitride layer down to at least the top surfaces of said field oxide regions, thereby forming floating gate regions beneath a silicon oxide layer,removing the silicon nitride layer,removing the polysilicon layer using the silicon oxide layer over the floating gates as an etch barrier,oxiding the edge surfaces of the polysilicon floating gates,depositing a second polysilicon layer on the surface of the substrate,forming elongated word lines that are parallel and in close proximity to said floating gates from said second polysilicon layer,forming a source line in the substrate that is parallel to the word line and is spaced from said floating gates, and drain regions spaced from said source line, andforming a gate electrode on the surface of the substrate that overlies the floating gates and is perpendicular to said word lines.