Patent ID: 8483000
Filing Date: 2013-07-09
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array; a first memory control unit; a first word driver; a first input/output circuit unit; a second memory control unit; a second word driver; and a second input/output circuit unit, wherein the memory cell array includes: first word lines coupled to the first word driver; first complementary bit lines coupled to the first input/output circuit unit; second word lines coupled to the second word driver; second complementary bit lines coupled to the second input/output circuit unit; a plurality of memory cells coupled to the first complementary bit lines, the first word lines, the second complementary bit lines, and the second word lines; a first replica word line coupled to the first word driver; a first replica bit line coupled to the first input/output circuit unit; a second replica word line coupled to the second word driver; a second replica bit line coupled to the second input/output circuit unit; and a plurality of replica cells coupled to the first replica bit lines, the first replica word lines, the second replica bit lines, and the second word lines; wherein the first replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the first complementary bit lines in half are coupled, and wherein the second replica bit line has a wiring structure that parallel lines having length obtained by cutting an inversion bit line and a non-inversion bit line of the second complementary bit lines in half are coupled.