Patent ID: 6681272
Filing Date: 2004-01-20
Classification: G06F,H04J

Abstract:
An elastic store with programmable phase delay comprising:a static phase offset circuit having a first input to accept a reference clock having a first frequency and a first phase, a second input to receive a phase delay control signal, and an output to provide a read (RD) clock having a second frequency and a third phase, the RD clock being phase delayed with respect to a write (WR) clock having the second frequency and a second phase, said static phase offset circuit varying the third phase of the RD clock in response to the phase delay control signal; a first in/first out (FIFO) circuit having a first input to receive input data, a second input to accept the WR clock, a third input to accept the RD clock, and an output to provide the input data at the FIFO output, delayed by a first delay corresponding to the difference of the second phase of the WR clock and the third phase of the RD clock, whereby the input data is delayed in response to the WR clock and the RD clock; a phase bias circuit having a first input to accept a null-phased reference compare signal having the first frequency and a fourth phase, which is phase-locked to the RD clock, said phase bias circuit having a second input to accept the phase delay control signal, and an output to, provide a phase-biased reference compare signal having the first frequency and the first phase; and a first clock synthesizer unit (CSU) having a first input operatively connected to the output of said phase bias circuit to receive the phase-biased reference compare signal, said first CSU having an output operatively connected to the third input of said FIFO circuit to provide the RD clock, said first CSU varying the third phase of the RD clock in response to the phase delay control signal.