Patent ID: 7647539
Filing Date: 2010-01-12
Classification: G06F

Abstract:
1. A computer-implemented method comprising: simultaneously executing a first test pattern on a first processor and a second test pattern on a second processor, resulting in a first test pattern execution round; after the first test pattern execution round, computing a first hardware register error detection check value; comparing the first hardware register error detection check value to a simulation register error detection check value; after the comparing, simultaneously re-executing the first test pattern on the first processor and re-executing the second test pattern on the second processor, resulting in a second test pattern execution round; after the second test pattern execution round, computing a second hardware register error detection check value; comparing the second hardware register error detection check value to the simulation register error detection check value; and setting an error flag if the first hardware register error detection check value or the second hardware register error detection check value do not match the simulation register error detection check value based upon the comparison.