Patent ID: 8868397
Filing Date: 2014-10-21
Classification: G06F

Abstract:
1. A modeling tool used for verifying System on a Chip (SoC) sub components and stored on a non-transitory machine-readable medium for a computing system, comprising: a transactor configured to translate a behavior of one or more subcomponents between two or more different levels of abstraction derived from a same electronic system design under verification based upon an applied sequence of test patterns and expected test results from a same instance of a testbench executable program, where the transactor is also configured to convert stimulus responses sent from the the one or more sub-components of the electronic system design under verification from a first level of abstraction that the electronic system design under verification possesses to a second level of abstraction that the testbench executable program is at, where the transactor is configured to apply the sequence of test patterns and expected test results from the testbench executable program to the sub-components of the electronic system design under verification at the first level of abstraction; a timing module configured to generate correlation measurements of timing approximation between the different levels of abstraction of the sub-components so that the timing approximation between the different levels of abstraction is accurate between the different levels of abstraction for each cycle of operation of same sub-components of the electronic system design under verification; and a functional correlation module configured to establish a functional correlation between the different levels of abstraction of the sub-components, where the functional correlation includes analysis of the behavior of the sub-components to applied stimulus from the testbench executable program, including 1) whether an expected logic value occurred, 2) whether an expected blocking of a signal occurred, and 3) any combination of these two, and where the correlation of measurements of timing approximation includes analysis of recorded timing data between the two or more levels of abstraction of the sub-components, wherein the applied sequence of the test patterns and expected test results from testbench executable program are applied in parallel to the subcomponents at the different levels of abstraction in order to make the correlation of measurements of timing approximation between the different levels of abstraction of the sub-components, and wherein the testbench executable program, the transactor, the timing module and the functional correlation module are stored and executed on the non-transitory machine readable medium.