Patent ID: 7852309
Filing Date: 2010-12-14
Classification: G09G

Abstract:
1. A scan driver comprising: a first sampler for sampling an input signal in synchronization with an inverted clock signal; a second sampler for sampling an output signal of the first sampler in synchronization with a clock signal; a third sampler for sampling an output signal of the second sampler in synchronization with the inverted clock signal; an OR gate for performing a logical OR operation on the output signal of the first sampler and the output signal of the second sampler to generate a first scan signal; and a NAND gate for performing a NAND operation on the output signal of the second sampler and an output signal of the third sampler to generate a second scan signal, wherein the first sampler, the second sampler, the third sampler, the OR gate, and the NAND gate include transistors of a first conductivity type.