Patent ID: 7496731
Filing Date: 2009-02-24
Classification: G06F

Abstract:
1. A method, comprising: providing a processor comprising M independent vector register files and M address registers, wherein each address register of the M address registers is associated with a corresponding one of the M vector register files, and wherein each vector register file is independently addressable through its associated address register pointing to one of the N registers of said vector register file; and distributing a matrix of L data elements in M independent vector register files comprised by a processor resulting in the M vector register files collectively storing the matrix, each data element having B binary bits, said matrix having N rows and M columns, said L=N*M, each column having K subcolumns, said N≧2, said M≧2, said K≧2, said N=K*M, said B≧1, each row of said N rows being addressable, each subcolumn of said K subcolumns being addressable, wherein each of the M vector register files includes an array of N registers, wherein each of the N*M registers of the M vector register files is storing a data element of the L data elements, wherein the data elements of each subcolumn are stored in different vector register files, wherein the data elements of each row are stored in different vector register files.