Patent ID: 8555011
Filing Date: 2013-10-08
Classification: G11C

Abstract:
1. A method comprising: shifting a memory address of a memory array, a first write-enable value, and a first write data stored in a first input stage to a first delay stage, wherein the first delay stage is configured to store the memory address, first write-enable value, and the first write data; shifting the memory address, a second write-enable value, and a second write data stored in a second input stage to a second delay stage, wherein the second delay stage is configured to store the memory address, second write-enable value, and the second write data; selecting the memory address from the second input stage and asserting a read enable signal at the memory array; and clearing the second write-enable value from a control delay element in the second delay stage to assert a write disable signal at the memory array, the write disable signal conditionally blocking the second write data from accessing the memory array.