Patent ID: 9012261
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method for forming a plurality of thin film transistors on a substrate in a combinatorial manner, the method comprising: providing the substrate, wherein the substrate comprises a plurality of site-isolated regions; depositing a gate electrode layer above each of the site-isolated regions; patterning each of the gate electrode layers; depositing a gate dielectric layer above each gate electrode layer; patterning the gate dielectric layer deposited above each gate electrode layer; depositing a metal-based semiconductor material layer above each gate dielectric layer; patterning the metal-based semiconductor material layer deposited above each gate dielectric layer; depositing an etch stop layer above each metal-based semiconductor material layer; patterning the etch stop layer deposited above each metal-based semiconductor material layer; depositing a source/drain layer above each etch stop layer; patterning the source/drain layer deposited above each etch stop layer; depositing a passivation layer above each source/drain layer; and patterning the passivation layer deposited above each source/drain layer; wherein at least one of depositing the gate electrode layer, patterning the gate electrode layer, depositing the gate dielectric layer, patterning the gate dielectric layer, depositing the metal-based semiconductor material layer, patterning the metal-based semiconductor material layer, depositing the etch stop layer, patterning the etch stop layer, depositing the source/drain layer, patterning the source/drain layer, depositing the passivation layer, or patterning the passivation layer is varied in a combinatorial manner between at least two of the plurality of site-isolated regions.