Patent ID: 6787408
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A method for forming an electrical insulating layer on bit lines of the flash memory, the method comprising the steps of:providing a semiconductor substrate having a plurality of gate stacks wherein each of said gate stacks comprises a conductive layer, a mask layer and a cap layer, and a plurality of spacing are located between said gate stacks; forming a dielectric layer on said gate stacks to fills into said spacing wherein said dielectric layer is higher than said cap layer; forming a planarized layer on said dielectric layer to generate a planar surface; performing a first etching step to totally remove said dielectric layer on said cap layer and simultaneously forming a spacing dielectric layer on said spacing; performing a second etching step to remove said cap layer wherein the etching rate of said dielectric layer is less than that of said mask layer so that said spacing dielectric layer has a round top and slant sides to prevent a thin film from stress concentration; and removing said mask layer and then remaining said spacing dielectric layer to form said electrical insulating layer.