Patent ID: 9105355
Filing Date: 2015-08-11
Classification: G11C

Abstract:
1. A memory cell array, comprising: a bit line; a complementary bit line; a first operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a first operation voltage; a second operation voltage supply circuit, electrically coupled to the bit line and the complementary bit line, configured to provide a second operation voltage; a first memory cell, electrically coupled to the bit line and the complementary bit line, configured to receive the first operation voltage; and a second memory cell, electrically coupled to the bit line and the complementary bit line, configured to receive the second operation voltage; wherein the first and second memory cells are located in a same column in the memory cell array; wherein the first and second operation voltage supply circuits both comprise: a node for generating the first or the second operation voltage; a first N-type transistor configured to have one source/drain thereof electrically coupled to a first source voltage and another source/drain thereof electrically coupled to the node; a second N-type transistor configured to have one source/drain thereof electrically coupled to the first source voltage and another source/drain thereof electrically coupled to the node; a first P-type transistor configured to have one source/drain thereof electrically coupled to the node and a gate thereof electrically coupled to a gate of the second N-type transistor; a second P-type transistor configured to have one source/drain thereof electrically coupled to another source/drain of the first P-type transistor, another source/drain thereof electrically coupled to the first source voltage, and a gate thereof electrically coupled to a gate of the first N-type transistor; a first inverter configured to have an input terminal thereof electrically coupled to the bit line and an output terminal thereof electrically coupled to a gate of the second P-type transistor; and a second inverter configured to have an input terminal thereof electrically coupled to the complementary bit line and an output terminal thereof electrically coupled to a gate of the first P-type transistor; wherein the first operation voltage or the second operation voltage at the node is equal to or smaller than the first source voltage.