Patent ID: 6940316
Filing Date: 2005-09-06
Classification: H03K

Abstract:
1. A comparator circuit comprising: a differential amplification circuit including a differential pair transistor for inputting a signal as an object of comparison, and a current mirror load circuit; a latch circuit including inversion amplifiers that are configured so that an input of one amplifier becomes an input of other amplifier so as to amplify a differential output signal outputted from said current mirror load circuit in accordance with a magnitude relation of said signal as the object of comparison; an equalization transistor for equalizing a signal of said differential amplification circuit; a delay circuit for generating a signal to delay a control signal to be inputted in a control electrode of said equalization transistor; and a control transistor for inputting an output signal of said delay circuit in the control electrode as a control signal to make said latch circuit into an active status and a non-active status.