Patent ID: 7587014
Filing Date: 2009-09-08
Classification: H04L

Abstract:
1. A digital frequency/phase recovery circuit for generating a sampling clock according to a frequency and a phase of an input signal, comprising: a comparator with hysteresis for receiving the input signal to generate a comparison signal, wherein the comparison signal is set to state “High” when the level of the input signal is higher than a high reference voltage, and the comparison signal is set to state “Low” when the level of the input signal is lower than a low reference voltage; a counter for receiving the comparison signal, calculating the number of pulses of the comparison signal in one period relating to a counting clock, and outputting a pulse value, wherein the frequency of the counting clock being higher than that of the comparison signal; a frequency determiner for receiving the pulse value, calculating the frequency of the input signal according to the pulse value, and generating a frequency value; a multi-phase clock generator for receiving the frequency value and generating multi-phase reference clocks with identical frequency and distinct phases according to the frequency value; a transition detector for receiving the comparison signal and generating a transition signal, wherein the transition signal is enabled for a preset period as the comparison signal is changing from a high level to a low level or from the low level to the high level; a phase adjuster for receiving the transition signal and the sampling clock and generating a phase selection signal according to the phase relationship between the sampling clock and the transition signal; and a multiplexer for receiving the multi-phase reference clocks and selecting one reference clock as the sampling clock according to the phase selection signal.