Patent ID: 6278159
Filing Date: 2001-08-21
Classification: H01L,Y10S

Abstract:
A structure for protecting the gate oxide of integrated devices from damage arising from the manufacturing process, comprising:a substrate of a first conductivity type housing a well of a second conductivity type and a first conductivity level;a zener diode formed in said well and including one first conductive region having said second conductivity type and a second conductivity level, higher than said first conductivity level, and a second conductive region of said first conductivity type, adjacent to said first conductive region and forming, with said first conductive region, said zener diode;a conductive material layer overlying said gate oxide layer to be protected and connected to said first conductive region;a third conductive region of said second conductivity type and said second conductivity level, said third conductive region extending in an area of said well remote from said first conductive region and second conductive region;an electrically insulating region covering said substrate, and a first metal region extending above said electrically insulating region, said first metal region having a portion crossing said electrically insulating region and in direct electrical contact with said third conductive region, said first metal region being connected to a gate region of a MOS transistor element; anda fourth conductive region extending in said substrate outside said well, and a second metal region extending above and insulated from said substrate, said fourth conductive region having said first conductivity type and a conductivity level higher than said substrate, and said second metal region electrically connecting said second conductive region and fourth conductive region.