Patent ID: 7001804
Filing Date: 2006-02-21
Classification: H01L

Abstract:
1. A method of producing active semiconductor regions in an SOI wafer, comprising the steps: a) providing an SOI wafer including an active layer of active semiconductor material on an insulating layer; b) covering at least a selected area of said active layer with a protective layer; c) in said selected area, forming a trench to penetrate through said protective layer and into said active layer, while leaving first active semiconductor regions of said active semiconductor material of said active layer remaining beside said trench; d) covering at least a partial surface area of said trench with a first oxide layer; e) after said step d), forming spacers within said trench directly or indirectly on said first oxide layer at sides of said trench; f) filling said trench between said spacers with a second oxide layer; g) forming seed openings through portions of said first oxide layer lying under said spacers by removing said spacers and removing said portions of said first oxide layer to form said seed openings extending to said active semiconductor material of said active layer; h) epitaxially growing epitaxial semiconductor material regions within said trench beginning and progressing from said seed openings to areas displaced from said seed openings; i) again opening said seed openings by removing portions of said epitaxial semiconductor material regions in and leading to said seed openings; j) leaving portions of said epitaxial semiconductor material regions remaining, to form thereof second active semiconductor regions within said trench; and k) after said step i), providing an insulating intermediate material to close and insulate said seed openings; wherein said first active semiconductor regions have a first thickness in a direction perpendicular to a plane of said insulating layer, said second active semiconductor regions have a second thickness in said direction that is smaller than said first thickness, and said second active semiconductor regions are completely laterally and vertically dielectrically insulated from said first active semiconductor regions.