Patent ID: 6154865
Filing Date: 2000-11-28
Classification: G01R

Abstract:
An instruction processor (20) for responding to each input instruction of a sequence of input instructions by changing a value of an output address (ADDR), the instruction processor comprising:stack means (32) for saving a return address when signaled to do so by an input PUSH signal and for discarding a saved return address when signaled to do so by an input POP signal, andprocessing means (24, 26, 29, 30) for responding to at least one of said instructions (TEMP) by changing said output address from a current value to a value of a return address previously saved by said stack means, by generating a new return address, by signaling said stack means via said POP signal to discard the previously saved return address, and by signaling said stack means via said PUSH signal to save said new return address.