Patent ID: 8585842
Filing Date: 2013-11-19
Classification: B32B,C04B,H01L,H05K

Abstract:
1. A method for manufacturing a multilayer ceramic substrate, the method comprising the steps of: preparing a first low-temperature co-fired ceramic material and a second low-temperature co-fired ceramic material, and a sintering-resistant ceramic powder that is substantially not sintered under a condition for sintering the first and the second low-temperature co-fired ceramic material; forming a composite sheet including a first ceramic green layer containing the first low-temperature co-fired ceramic material and a shrinkage-retardant layer containing the sintering-resistant ceramic powder; forming a resistor pattern and/or a conductor pattern on the first ceramic green layer of the composite sheet by an ink jet method using a resistor ink and/or a conductor ink; stacking a plurality of second ceramic green layers containing the second low-temperature co-fired ceramic material with the composite sheet having the resistor pattern and/or the conductor pattern such that the shrinkage-retardant layer of the composite sheet defines an outermost layer, thus forming a multilayer composite including an unfired multilayer ceramic substrate and the shrinkage-retardant layer disposed at at least one main surface of the unfired multilayer ceramic substrate; firing the multilayer composite under the condition for sintering the first and the second low-temperature co-fired ceramic material, thereby producing a sintered multilayer ceramic substrate; and removing the shrinkage-retardant layer to obtain the multilayer ceramic substrate; wherein the first ceramic green layer has a voidage in a range of about 30% to about 60%; the shrinkage-retardant layer has a voidage in a range of about 10% to about 50%; the voidage of the shrinkage-retardant layer is less than the voidage of the first ceramic green layer; and each of the resistor pattern and/or the conductor pattern has a line fineness after the firing step of about 135 or less, where the line fineness is defined as an index of an average width of each of the resistor pattern and/or the conductor pattern with respect to an intended width of each of the resistor pattern and/or the conductor pattern that is defined as 100.