Patent ID: 6989303
Filing Date: 2006-01-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory integrated circuit comprising: forming a plurality of first gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate; forming a first-layer gate electrode material film not doped with impurities on said first gate insulating films; selectively etching said semiconductor substrate covered with said first-layer gate electrode material film to form device isolation grooves, and burying said device isolation grooves with a device isolation insulating film; forming a barrier film on said device isolation insulating film and said first-layer gate electrode material film maintained in self-alignment in regions surrounded by said device isolation insulating film to prevent diffusion of impurities; selectively removing said barrier film from above said cell array region; forming a second-layer gate electrode material film doped with impurity on said cell array region and said peripheral circuit region; selectively etching said second-layer gate electrode material film to remove said second-layer gate electrode material film from above said device isolation insulation film within said cell array region, and removing said second-layer gate electrode material film from said peripheral circuit region; selectively forming a second gate insulating film on said second-layer gate electrode material film in said cell array region; forming a third-layer gate electrode material film not doped with impurities on said second gate insulating film in said cell array region and on said peripheral circuit region from which said barrier film has been removed; selectively etching third-layer gate electrode material films to form control gates in said cell array region and gate electrodes in said peripheral circuit region; and forming source and drain diffusion layers and lowering the resistance of said gate electrodes by introducing impurities into said memory cell region and said peripheral circuit region under a plurality of different conditions.