Patent ID: 6400614
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A transmission device for controlling transmission of digital signals, comprising:a memory for storing an input signal; write address generating means for generating a write address for writing in said memory; read address generating means for generating a read address for reading from said memory; phase state monitoring means for monitoring a transition from a steady phase state in which writing/reading in/from said memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided; and reset signal output means, responsive to detection of the coincident phase state or the unstable phase state, for outputting a reset signal to said write address generating means and said read address generating means such that a phase relation between the write and read addresses is brought to an optimum phase relation.