Patent ID: 6226556
Filing Date: 2001-05-01
Classification: G06F,H02J

Abstract:
An apparatus comprising:a power supply;an energy reservoir, coupled to the power supply, for receiving energy from the power supply and for supplying voltage when a power failure occurs;a processor, coupled to the power supply and to the energy reservoir; wherein as a result of power failures the processor enters a predetermined mode;a memory, coupled to the processor, for storing a status of the processor;a power failure sensor, coupled to the power supply, for sensing when the supply voltage is below or above a first level;a power failure recovery controller, coupled to the power supply, the energy reservoir, the power failure sensor, and to the processor; wherein the power failure recovery controller notifies the processor when the supply voltage is below the first level and when the supply voltage raises above the first level, wherein after the processor enters a predetermined state, the power failure recovery controller reduces power consumption of the apparatus;a plurality of further processors and a plurality of further memories; and wherein each processor is coupled to one of the memories, for storing and reading the processor statuses; anda clock generator, coupled to the power failure recover controller, to the plurality of processors, and to the plurality of memories, wherein most of all of the plurality of processors and memories are built from cells, wherein a cell average power dissipation P is proportional to the cell operating frequency F by the power of k, k>0, and wherein the power failure recovery controller reduces the power consumption of the apparatus by disabling the clock generator.