Patent ID: 6667641
Filing Date: 2003-12-23
Classification: H03K,H03L

Abstract:
A programmable logic integrated circuit comprising:a programmable interconnect structure including rows of horizontal conductors and columns of vertical conductors; a phase detector circuit receiving a reference clock signal; a charge pump circuit coupled to the phase detector circuit; a voltage controlled oscillator, coupled to the charge pump and programmably coupled to the logic array blocks, wherein the voltage controlled oscillator generates a plurality of voltage controlled oscillator outputs; and a first multiplexer coupled to the voltage controlled oscillator, wherein the multiplexer selects one of the voltage controlled oscillator outputs as a first clock output, wherein the voltage controlled oscillator comprises second, third and fourth multiplexer an input of the second multiplexer coupled to an output of the third multiplexer, an input of the third multiplexer coupled to an output of the fourth multiplexer, and an input of the fourth multiplexer coupled to an output of the third multiplexer.