Patent ID: 8165257
Filing Date: 2012-04-24
Classification: H04L

Abstract:
1. A method of clock compensation for one or more lanes of a serial data channel transferred through one or more corresponding first-in, first-out (FIFO) buffers, comprising the steps of: determining, for each FIFO buffer, a state of the FIFO buffer corresponding to a relative buffer occupancy of the FIFO buffer; aligning portions of data in the one or more lanes in the corresponding FIFOs; generating, for each lane, a recovered clock signal from the portions of data in the corresponding FIFO; dividing, for each FIFO buffer, the aligned portion of data in a corresponding lane into current aligned data and look-ahead data; determining, for each FIFO buffer, a location of a clock compensation pattern in the aligned portion of data from the look-ahead data; generating, for each FIFO buffer, a clock compensation indicator based on the recovered clock and the state of the FIFO buffer; selecting one FIFO buffer based on the corresponding state of the FIFO buffer and at least one clock compensation indicator; and adjusting the aligned portion of data in each FIFO buffer by the steps of: