Patent ID: 7989707
Filing Date: 2011-08-02
Classification: H01L,H05K,Y10T

Abstract:
1. A chip embedded substrate, comprising: a first substrate on which a first wiring is formed and a semiconductor chip is mounted so as to be connected to the first wiring; and a second substrate on which a second wiring is formed, the second substrate being joined with the first substrate; wherein a first connection layer that is connected to the first wiring and exposed from a solder resist layer formed in the first substrate and a second connection layer that is connected to the second wiring and exposed from a solder resist layer formed in the second substrate are electrically connected with each other by an electrical connection member, wherein the semiconductor chip and the electrical connection member are encapsulated by an insulation layer between the first substrate and the second substrate, and the first substrate and the second substrate are adhered by the insulation layer, wherein the first substrate has an electrically conductive layer provided in an entire inner layer of the first substrate when seen from above, wherein an electrically conductive layer provided in the second substrate is electrically connected to the electrical connection member connected to the first substrate, and wherein the semiconductor chip mounted on the first substrate is electrically shielded by the electrically conductive layer provided in the first substrate, the electrically conductive layer provided in the second substrate, and the electrical connection member.