Patent ID: 9190418
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a plurality of gate structures on a top semiconductor layer of a semiconductor-on-insulator (SOT) substrate; forming trenches in the top semiconductor layer between the gate structures, the trenches extending through a portion of the top semiconductor layer; forming sacrificial spacers on sidewalls of the gate structures and the trenches, the sacrificial spacers shielding portions of the top semiconductor layer underneath the sacrificial spacers; introducing dopants into un-shielded portions of the top semiconductor layer underneath the trenches to form doped regions in the top semiconductor layer, the doped regions contacting a buried insulator layer of the SOI substrate; removing the sacrificial spacers to expose undoped portions of the top semiconductor layer beneath the trenches; and forming doped epitaxial semiconductor regions in the trenches.