Patent ID: 6900125
Filing Date: 2005-05-31
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a lower interconnect on a semiconductor substrate; forming an dielectric film on said lower interconnect; performing selective etching on said dielectric film to form a via hole that reaches the proximity of said lower interconnect; forming an anti-reflection coating at a bottom portion of said via hole; forming a resist layer over the substrate so as to substantially fill a space remaining on said anti-reflection coating in said via hole; forming an opening in said resist layer; performing selective etching on said dielectric film utilizing said resist layer as a mask to form an interconnect trench for connection with said via hole; removing said resist layer and said anti-reflection coating in said via hole to have an upper surface of said lower interconnect exposed; and substantially filling said via hole and said interconnect trench with a metal layer; wherein said anti-reflection coating is formed to have its thickness at a central portion of said via hole thinner than a distance between the upper surface of said lower interconnect and a bottom portion of said interconnect trench in said forming said anti-reflection coating.