Patent ID: 6469552
Filing Date: 2002-10-22
Classification: H03K

Abstract:
A power on reset circuit incorporated in a semiconductor device and generating a reset signal for resetting said semiconductor device when power is turned on, comprising:an inverter driving said reset signal to an activated level in response to reception of a power supply potential and a reference potential, and driving said reset signal to an inactivated level in response to a potential of an input node of the inverter exceeding a predetermined threshold potential; a first transistor of a first conductivity type having a first electrode receiving said reference potential and a second electrode connected to the input node of said inverter, and rendered conductive in response to said reset signal attaining the activated level; a second transistor of a second conductivity type having a first electrode receiving said power supply potential, a second electrode connected to the input node of said inverter and an input electrode receiving said reference potential; a first resistance element connected in series with said second transistor between the line of said power supply potential and the input node of said inverter and having a resistance value that is sufficiently larger than a conductive resistance value of said second transistor; and a second resistance element connected in series with said first transistor between the line of said reference potential and the input node of said inverter and having a resistance value that is sufficiently larger than a conductive resistance value of said first transistor, wherein said first and second resistance elements are formed of the same material and are each formed of a diffusion resistance layer or a polycrystalline silicon layer.