Patent ID: 6028412
Filing Date: 2000-02-22
Classification: A61M,H02P,H03B

Abstract:
A method of generating a clock signal having a desired frequency comprising the step of generating a pulse each time a stored accumulator value is found to be greater than or equal to a stored trigger value, wherein in a first loop the stored accumulator value is iteratively incremented by a first iterative value until the stored accumulator value is greater than or equal to the stored trigger value and subsequently in a second loop the stored accumulator value is decremented by a second iterative value until the stored accumulator value is less than the stored trigger value, and wherein during each iteration of the first loop, a current frequency of the clock signal is compared to a desired frequency value and if the two values are different, the first iterative value is corrected at a predetermined rate over one or more subsequent iterations until the frequency of the generated clock signal corresponds to the detected value of the desired frequency.