Patent ID: 6023092
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A resistor positioned on a semiconductor wafer comprising:a silicon substrate containing dopants in it as a first-type semiconductor which is either an n-type or p-type semiconductor;a first doped layer formed by implanting ions in a predetermined area on the silicon substrate and functioning as a resistor layer, the first doped layer being a second-type semiconductor which is either an n-type or p-type semiconductor but different from the first-type semiconductor, the first doped layer forming a first pn-junction at its interface with the silicon substrate to prevent electrical leakage;a second doped layer formed by implanting ions in a predetermined area of the first doped layer, the second doped layer being the first-type semiconductor and forming a second pn-junction at its interface with the first doped layer to prevent electrical leakage;a dielectric layer formed on the silicon substrate and positioned above the first and the second doped layers;a passivation layer positioned on the dielectric layer having a plurality of charges at fixed positions; anda conducting layer positioned between the dielectric layer and the passivation layer above the intersections between the surface of the dielectric layer and the first pn-junction and between the surface of the dielectric layer and the second pn-junction for preventing an electric field generated by the charges of the passivation layer from reducing the breakdown voltages of the first and second pn-junctions at their intersections with the surface of the dielectric layer.