Patent ID: 6813205
Filing Date: 2004-11-02
Classification: G11C,H01F

Abstract:
A pre-charge and sense out circuit of a differential type ROM for sensing logic data stored in a memory cell of the ROM, the memory cell being capable of connecting to one of a first bit line and a second bit line for providing digital signals to the first bit line or the second bit line, the pre-charge and sense out circuit comprising:a pre-charge module electrically connected to the first and the second bit lines for pre-charging the first and the second bit lines; a selecting module electrically connected to the first bit line, the second bit line, a first data line, and a second data line, for transmitting signals on the first bit line to the first data line and signals on the second bit line to the second data line according to a first control signal; a charge sharing module electrically connected to the first and the second data lines for pre-charging the first and the second data lines, and for sharing electrical charges stored in the charge sharing module with the first and the second data lines according to a second control signal; and a sensing module electrically connected to the first and the second data lines for sensing signals on the first and the second data lines to generate an output signal.