Patent ID: 6538954
Filing Date: 2003-03-25
Classification: G11C

Abstract:
A memory device comprising:(a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line, and (b-2) a write control line provided in corresponding relation to said write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of said word line groups and one of said bit line groups, each of said memory cells including (c-1) a storage cell including a first storage node, and (c-2) a first switch connected between said write data bit line of said one of said bit line groups corresponding thereto and said first storage node, said first switch being conducting only when both of said write word line of said one of said word line groups corresponding thereto and said write control line are active, wherein said write control line is active when an associated one of said bit line groups which includes said write control line is selected, and is inactive when said associated one of said bit line groups is not selected.