Patent ID: 8433971
Filing Date: 2013-04-30
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: an LDPC (Low Density Parity Check) encoder circuitry to employ a plurality of configurations of a superimposed LDPC matrix respectively to encode respective pluralities of information bits thereby generating a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein: a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix within each of the plurality of configurations; and wherein: when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC encoder circuitry to employ a first generator matrix to encode a first respective plurality of information bits thereby generating a first of the plurality of LDPC coded signals; and when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC encoder circuitry to employ a second generator matrix to encode a second respective plurality of information bits thereby generating a second of the plurality of LDPC coded signals.