Patent ID: 6028358
Filing Date: 2000-02-22
Classification: H01L,H05K

Abstract:
A semiconductor device package comprises a multilayer laminated substrate comprising a metallic base substrate around a semiconductor chip, an insulation layer and a metallic film layer having a configuration formed in a predeterminedly designed wiring pattern, and wherein at least one continuity checking terminal is provided at a portion of said metallic base substrate in said multi-layer laminated substrate and opposite to a part of said wiring pattern, said continuity checking terminal being separated from said metallic base substrate and also being electrically insulated from said metallic base substrate, further wherein at least one solder ball is provided on a surface of said wiring pattern which is a reverse side of a surface thereof being opposite to said metallic base substrate, and at a point on said wiring pattern opposite to a point at which said continuity checking terminal is provided.