Patent ID: 6781187
Filing Date: 2004-08-24
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cell shaving two nonvolatile memory elements and being controlled by one word gate and two control gates, wherein the memory cell array region includes: a plurality of control gate lines which connects in the first direction the control gates in each column of the memory cells disposed in the first direction; and sub control gate lines extending in the first direction in an upper layer of the control gate lines, the number of the sub control gate lines being half the number of the control gate lines, wherein each of the sub control gate lines is connected to adjacent two of the control gate lines in adjacent two of the memory cells in the second direction; wherein each two of the control gate lines have a wide spacing region having a large line-to-line width, a common connection region in which the two lines are connected in common in one line, and a narrow spacing region having a small line-to-line width; and wherein the wide spacing regions are disposed on both sides of the common connection region in the second direction.