Patent ID: 6014508
Filing Date: 2000-01-11
Classification: G06F

Abstract:
A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net comprising a plurality of nodes to be interconnected while ensuring that the interconnected nodes meet system requirements that include physical, electrical and noise constraints, wherein the system requirements are expressed by wiring rules, the method comprising the steps of:a) building a trace structure comprising:i) a plurality of rule nodes, each of the rule nodes comprising at least one rule node constraint;ii) a plurality of net node lists associated with the rule nodes, each of the net node lists comprising net nodes having first attributes that meet the rule node constraints; andiii) a plurality of rule connections, each of the rule connections comprising connection constraints to be imposed on a pair of the rule nodes;b) successively linking each of the rule nodes to each of the rule connections until all the rule nodes have been linked, thereby forming the net; andc) matching the rule connection constraints to second attributes associated with the pair of rules nodes, wherein:when the matching is successful, the rule connection constraints are imposed on the pair of rule nodes;when the matching is successful and the net node list of at least one pair of the rule nodes is empty, at least one cluster point is added to the net; andwhen the matching is unsuccessful, the connection between the linked rule nodes is flagged as violating the wiring rules.