Patent ID: 7720900
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. A method of processing an instruction in an arithmetic logic unit, the instruction indicating a plurality of operands (A, B) including an addend (C), said method comprising: receiving, by an arithmetic logic unit, input operands A, B and C, said arithmetic logic unit including a hardware structure for executing an instruction for calculating A×B+C; performing a multiplication of A and B operands in a Multiplier block to obtain an intermediate product including partial sum results and partial carry results; aligning in parallel operation, the C addend to the intermediate product and generating the aligned addend; inputting said partial sum and carry expression results and the aligned addend to a carry-save adder block that generates an explicit value of the result in carry-save form in a double wide format; and, generating, from said carry-save form result, an extended result in a carry-propagate adder that produces an explicit extended result in a double wide format; and, preventing normalization of said explicit extended result by suppressing left-alignment of said explicit extended result, whereby input operands for a subsequent A×B+C operation remain right-aligned.