Patent ID: 7445978
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A method of fabrication of a semiconductor device comprising: providing a substrate having a first region and a second region; providing a first transistor in said first region having a first gate with exposed first gate sidewalls, first source/drain regions adjacent to said first gate, and a first channel region under said first gate; providing a second transistor in said second region having a second gate, second spacers over second gate sidewalls of said second gate, second source/drain regions adjacent to said second spacers, and a second channel region under said second gate; and forming a stress dielectric layer having a first stress over the first and second transistors, the stress dielectric layer contacting the exposed first gate sidewalls, the stress dielectric layer remains over the first and second transistors, wherein the second transistor is less affected by the stress dielectric layer than the first transistor.