Patent ID: 6844781
Filing Date: 2005-01-18
Classification: H03F

Abstract:
1. A circuit comprising a dual differential-input amplifier that comprising the following: a first PMOSFET having a source terminal coupled to a high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal; a second PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal; a third PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to the gate terminal of the second PMOSFET, and having a gate terminal coupled to the drain terminal of the third PMOSFET; a fourth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the fourth PMOSFET; a fifth PMOSFET having a source terminal, coupled to the high voltage source, having a drain terminal, and having a gate terminal coupled to the gate terminal of the fourth PMOSFET; a sixth PMOSFET having a source terminal coupled to the high voltage source, having a drain terminal coupled to an output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the gate terminal of the first PMOSFET; a first NMOSFET having a source terminal coupled to a low voltage source, having a drain terminal coupled to the drain terminal of the first PMOSFET, and having a gate terminal coupled to the drain terminal of the second PMOSFET; a second NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the second NMOSFET and to the drain terminal of the second PMOSFET; a third NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal, and having a gate terminal coupled to the drain terminal of the third NMOSFET and to the drain terminal of the fifth PMOSFET; a fourth NMOSFET having a source terminal coupled to the low voltage source, having a drain terminal coupled to the output terminal of the dual differential-input amplifier, and having a gate terminal coupled to the drain terminal of the fifth PMOSFET; a fifth NMOSFET having a source terminal coupled to a current sink, having a drain terminal coupled to the drain terminal of the third PMOSFET, and having a gate terminal coupled to a first input terminal of the dual differential-input amplifier; a sixth NMOSFET having a source terminal coupled to the current sink, having a drain terminal coupled to the drain terminal of the fourth PMOSFET, and having a gate terminal coupled to a second input terminal of the dual differential-input amplifier; a seventh PMOSFET having a source terminal coupled to a current source that provides a current of approximately equal magnitude to a current drawn by the current sink, having a drain terminal coupled to the drain terminal of the second NMOSFET, and having a gate terminal coupled to the second input terminal of the dual differential-input amplifier; and an eighth PMOSFET having a source terminal coupled to the current source, having a drain terminal coupled to the drain terminal of the third NMOSFET, and having a gate terminal coupled to the first input terminal of the dual differential-input amplifier.