Patent ID: 7406113
Filing Date: 2008-07-29
Classification: G01S,H03H,H04B

Abstract:
1. A semiconductor integrated circuit for processing a plurality of received broadcast signals, the broadcast signals being of a type each having a different respective digital code, the semiconductor integrated circuit comprising: a digital sampler; a sample reducer; and a plurality of correlators being arranged to be operable in two modes wherein: in an acquisition mode: in a track mode: wherein for the acquisition mode, the sample reducer includes an adder to add the groups of N bits, wherein in the acquisition mode, the adder is adapted to provide a digital output representative of a value of a sum of the N bits, and wherein in the acquisition mode, the adder is adapted to provide an output having a first logic state if the sum of the N bits is greater than a given value and an output having a second logic state opposite to said first logic state if the sum of N bits is less than the given value.