Patent ID: 8436409
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A semiconductor device comprising a vertical MOS transistor having upper and lower conductive layers at upper and lower parts thereof in a normal direction of a semiconductor substrate, the vertical MOS transistor comprising: a first semiconductor pillar comprising a first upper pillar having a first width and a first lower pillar having a second width larger than the first width and an upper surface around the first upper pillar on a main surface of the semiconductor substrate; a first insulation film that is provided on a side surface to at least a part of the upper surface of the first lower pillar; a second insulation film that is provided on a side surface of at least a part of the first upper pillar, and a third insulation film provided on the second insulation film and upwardly extended beyond an upper surface of the first semiconductor pillar, wherein the side surface of the first semiconductor pillar is continuously covered with the first and second insulation films.