Patent ID: 7576593
Filing Date: 2009-08-18
Classification: H02M

Abstract:
1. A two-phase charge pump circuit without the body effect that receives a first input signal and a second input signal of opposite phases, the charge pump circuit comprising: a first voltage dropping stage, which includes a first NMOS discharge transistor and a third NMOS discharge transistor, each of which having a body, a gate, a first terminal, and a second terminal, the body of the first NMOS discharge transistor being connected to two switches, the first terminal and the second terminal of the first NMOS discharge transistor being connected respectively to a first control node and an input node, the first terminal and the second terminal of the third NMOS discharge transistor being connected respectively to the first control node and the input node, the gate of the third NMOS discharge transistor is connected to the second control node, and the body of the third NMOS discharge transistor is connected to the body of the first NMOS discharge transistor; a second voltage dropping stage, which includes a second NMOS discharge transistor and a fourth NMOS discharge transistor, each of which having a body, a gate, a first terminal, and a second terminal, the body of the second NMOS discharge transistor being connected to two switches, the first terminal and the second terminal of the second NMOS discharge transistor being connected respectively to a second control node and the input node, the first terminal and the second terminal of the fourth NMOS discharge transistor being connected respectively to the second control node and the input node, the gate of the fourth NMOS discharge transistor is connected to the first control node, and the body of the fourth NMOS discharge transistor is connected to the body of the second NMOS discharge transistor; an input stage, which includes two NMOS discharge transistors connected in series with their connecting node being the input node, the body of each NMOS discharge transistor being connected to two switches with one end of the fifth NMOS discharge transistor connected to a third control node and one end of the sixth NMOS discharge transistor connected to a fourth control node; and a negative-voltage generator, which includes two NMOS output transistors, the body of each of the NMOS output transistors being connected to two switches with one end of the first NMOS output transistor connected to the third control node and one end of the second NMOS output transistor being connected to the fourth control node, and the other ends of the two NMOS output transistors being connected to an output node; wherein the first input signal and the second input signal are provided to the first voltage dropping stage and the second voltage dropping stage, respectively, the two switches of the first voltage dropping stage, the two switches of the second voltage dropping stage, and the four switches of the input stage are controlled by the voltage on the first control node or the second control node so that the bodies of the first/third NMOS discharge transistor and the second/fourth NMOS discharge transistors are constantly switched to a lower voltage level.