Patent ID: 8993425
Filing Date: 2015-03-31
Classification: H01L,Y10S

Abstract:
1. A method of forming an integrated circuit, comprising: forming a first nitride layer over a gate stack supported by a substrate; implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate; etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation; implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain; removing the first asymmetric nitride spacer using a wet etching process; and forming a second nitride layer over the gate stack and implanting germanium ions in the second nitride layer in the direction forming the acute angle with the top surface of the substrate.