Patent ID: 9026823
Filing Date: 2015-05-05
Classification: G06F,Y02D

Abstract:
1. A data processing device, comprising: a central processing unit operating in accordance with a user program; a register which can be set by a user; a non-volatile memory; and a first clock circuit for supplying a first clock to said central processing unit and said non-volatile memory, said central processing unit setting said register which of a first mode, a second mode, and a third mode said data processing device is to operate in accordance with said user program, and said first mode allowing operation within a first range in which an external supply voltage is relatively high, and said second mode allowing operation within a second range in which said external supply voltage includes said first range and a relatively low voltage range, and an upper limit of a frequency of said first clock in said second mode being lower than an upper limit of a frequency of said first clock in said first mode, and said third mode being a low electric power consumption operation mode, and a frequency of said first clock in said third mode being lower than the frequency of said first clock in said first mode and the frequency of said first clock in said second mode.