Patent ID: 6571106
Filing Date: 2003-05-27
Classification: G06F

Abstract:
A digital system, comprising:an internal circuit; an interface circuit connected to the internal circuit, the interface circuit having a first input for receiving a first signal from a remote source, a second input for receiving a third signal that is received from the remote source, and an output for sending a second signal to a remote destination in response to the first signal; wherein the interface circuit is operable to immediately set the second signal to a first state in a glitchless manner in response to a signal edge in the first signal; wherein the interface circuit is further operable to set the second signal to a second state in a glitchless manner in response to the internal circuit; wherein the interface circuit is further operable to selectively set the second signal to the first state in response to either a rising edge in the first signal or a falling edge in the first signal as selected by the third signal; wherein the interface circuit comprises a first flip-flop and a second flip-flop connected to receive the first signal as a clock input, such that a first flip flop is responsive to a rising edge on the first signal and the second flip-flop is responsive to a falling edge on the first signal; and wherein the interface circuit further comprises a state machine connected to the internal circuit, the first input and the second input and having a plurality of state outputs; and wherein the state machine is operable to generate a plurality of gray code states such that only one output of the plurality of outputs changes on each state change.