Patent ID: 6107666
Filing Date: 2000-08-22
Classification: G11C,H01L

Abstract:
A high density ROM device, comprising:a substrate; andat least one memory array, including:a first insulating layer located over a surface of the substrate,plural bit lines located over the first insulating layer and extending in a first direction, said bit lines being spaced from one another at essentially equal intervals;a second insulating layer formed over the plural bit lines,at least one via formed in the second insulating layer and exposing a portion of the bit lines, andplural word lines located over the second insulating layer and extending in a second direction that crosses the first direction to form an angle, said word lines being spaced from one another at essentially equal intervals; andwherein some of the word lines are connected to the bit lines using the via and some of the word lines are isolated from the bit lines using the second insulating layer.