Patent ID: 6306680
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method of fabricating a power semiconductor device package comprising:providing at least one power semiconductor device having an active major surface and an opposite major surface, with contact pads on the active major surface and a terminal contact on the opposite major surface;providing a dielectric film having first and second sides, the dielectric film comprising a polymeric film;forming holes through the dielectric film;bonding the active major surface of the at least one power semiconductor device to the second side of the dielectric film, with the contact pads in alignment with the holes;molding a dielectric encapsulant around the at least one semiconductor device on the second side of the dielectric film; andforming a patterned electrically conductive layer on the first side of the dielectric film, portions of the patterned electrically conductive layer extending through the holes as vias into electrical contact with the device contact pads.