Patent ID: 6764908
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising steps of:(a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming a CMOS device comprising at least one pair of PMOS and NMOS transistors in at least one pair of adjacent active device areas on or within said tensilely strained lattice semiconductor layer; wherein the drive current of said PMOS transistor is maximized by reducing the thickness of said tensilely strained lattice semiconductor layer of the respective active device area from an initial thickness to a final thickness, and the drive current of said NMOS transistor is maximized by increasing the thickness of said tensilely strained lattice semiconductor layer of the respective active device area from an initial thickness to a final thickness or by maintaining the thickness of said tensilely strained lattice semiconductor layer of the respective active device area at said initial thickness.