Patent ID: 6735730
Filing Date: 2004-05-11
Classification: G01R

Abstract:
An integrated circuit having a design for testability comprising:a data path section for carrying out a data processing, including combinatorial circuit elements each being assigned with a test plan having a plurality of phases for a test operation, each of the phases being constituted by a control vector sequence; a controller section generating a control signal for controlling data flow of the data path section in a normal operation; a test controller section generating the test plan to be supplied to the data path section for testing each of the combinatorial circuit elements of the data path section when the test operation is carried out; and a switching unit for switching a signal to be supplied to the data path section between the control signal generated by the controller section and the test plan generated by the test controller section, wherein the control vector sequence constituting each of the phases of the test plan is comprised of one control vector.