Patent ID: 8793644
Filing Date: 2014-07-29
Classification: G06F

Abstract:
1. A method of using a computer system to display a timing path within a network on chip (NoC) in a graphical user interface (GUI), the method comprising: exporting a register transfer language (RTL) model of the NoC to a tool; receiving a report from the tool, the report including data to preserve the identity of a first signal and a second signal that is connected to the first signal by a timing path; mapping the first signal to a first unit of the NoC; mapping the second signal to a second unit of the NoC; displaying the first unit, the second unit, and at least one line representing the timing path between the first unit and the second unit within the GUI; mapping to a plurality of units the first unit, the second unit, and names of intermediate signals in the timing path; displaying an order of units in the plurality of units traversed by the intermediate signals in the timing path; displaying using a first color a first path between units in the order of units where a cumulative time in the timing path is before expiration of a timing budget; and displaying using a second color a second path between units in the order of units where a cumulative time in the timing path is beyond the timing budget.