Patent ID: 6495879
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A ferroelectric memory device comprising:a plurality of memory cells arranged in an array of memory cells each having a cell transistor and a ferroelectric capacitor formed on a semiconductor substrate; a peripheral circuit; an interconnection structure for connecting said cell transistor, said ferroelectric capacitor and said peripheral circuit to store data in each of said memory cells, said ferroelectric capacitor including a bottom electrode, a ferroelectric film and a top electrode, said interconnection structure including a first interconnect layer in contact with said top electrode; an interlayer dielectric film formed on said first interconnect layer; an insulator film overlying said interlayer dielectric film and including at least one of SiNx and SiOxNy; and a protective layer disposed between said interlayer dielectric film and said insulator film, said protective layer including at least one of Ir, IrO2, Ru, RuO2, and having a higher modulus of elasticity than said interconnect layer.