Patent ID: 8995162
Filing Date: 2015-03-31
Classification: G11C

Abstract:
1. A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit comprising a first PMOS transistor ( 401 ), a second PMOS transistor ( 402 ), a third PMOS transistor ( 403 ), a fourth PMOS transistor ( 404 ), a fifth PMOS transistor ( 405 ), and a sixth PMOS transistor ( 406 ), wherein said first PMOS transistor ( 401 ) and said second PMOS transistor ( 402 ) are pull-up transistors; a source of said first PMOS transistor ( 401 ) is coupled to a voltage VDD, a gate of said first PMOS transistor ( 401 ) is coupled to an reverse storage node (QN4), and a drain of said first PMOS transistor ( 401 ) is coupled to a storage node (Q4); and a source of said second PMOS transistor ( 402 ) is coupled to the voltage VDD, a gate of said second PMOS transistor ( 402 ) is coupled to the storage node (Q4), and a drain of said second PMOS transistor ( 402 ) is coupled to the reverse storage node (QN4); said third PMOS transistor ( 403 ) and said fourth PMOS transistor ( 404 ) are read-out access transistors; a source of said third PMOS transistor ( 403 ) is coupled to a read selecting word line ( 410 ), a gate of said third PMOS transistor ( 403 ) is coupled to the storage node (Q4), and a drain of said third PMOS transistor ( 403 ) is coupled to a first read-out bit line ( 411 ); and a source of said fourth PMOS transistor ( 404 ) is coupled to the read selecting word line ( 410 ), a gate of said fourth PMOS transistor ( 404 ) is coupled to the reverse storage node (QN4), and a drain of said fourth PMOS transistor ( 404 ) is coupled to a second read-out bit line ( 412 ); and said fifth PMOS transistor ( 405 ) and said sixth PMOS transistor ( 406 ) are write-in access transistors; a source of said fifth PMOS transistor ( 405 ) is coupled to the storage node (Q4), a gate of said fifth PMOS transistor ( 405 ) is coupled to a write selecting word line ( 407 ), and a drain of said fifth PMOS transistor ( 405 ) is coupled to a first write-in bit line ( 408 ); and a source of said sixth PMOS transistor ( 406 ) is coupled to the reverse storage node (QN4), a gate of said sixth PMOS transistor ( 406 ) is coupled to the write selecting word line ( 407 ), and a drain of said sixth PMOS transistor ( 406 ) is coupled to a second write-in bit line ( 409 ).