Patent ID: 7333516
Filing Date: 2008-02-19
Classification: H04L

Abstract:
1. An interface for synchronous data transfer from a first domain clocked at by a first clock at a first frequency to a second domain clocked by a second clock at a slower frequency, comprising: a first latch for receiving data from the first domain when the first latch is selected; a second latch for receiving data from the first domain when the second latch is selected; and a third latch for transferring data from said first latch or said second latch to the second domain when the second domain is clocked by a clock pulse of the second clock, said third latch being selectively toggled to receive data from said first latch or said second latch in response to a negative edge of the clock pulse clocking the second domain; wherein the first and second latches are clocked by the first clock at the first clock frequency; and wherein the first clock clocking the first domain and the second clock clocking the second domain are both derived from a single primary clock and generate clock pulses that repeat in a ratioed, systematic pattern framed by a secondary synch pulse also generated as a function of the same primary clock.