Patent ID: 6253297
Filing Date: 2001-06-26
Classification: G06F

Abstract:
A memory controller circuit for coupling to a memory having a plurality of banks and rows, comprising:circuitry for receiving signals representative of requests to access the memory, wherein a first signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory and wherein a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory;determining circuitry for determining whether the second address is directed to a same one of the plurality of rows as the first address, the determining circuitry includes circuitry for indicating state information of the memory said circuitry comprising a plurality of address registers, wherein each of the plurality of address registers stores an address of an active row corresponding to a different one of the plurality of banks in the memory;circuitry for issuing control signals to the memory in response to receiving signals representative of requests to access the memory, the control signals causing a first memory access to occur in response to the first request and causing a second memory access to occur in response to the second request; andwherein in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.