Patent ID: 8027422
Filing Date: 2011-09-27
Classification: H04L

Abstract:
1. A symbol timing recovery circuit for recovering a symbol timing of an input signal, comprising: a sampling unit for sampling the input signal using a first clock; an interpolation unit for generating interpolation data of the input signal by performing interpolation using sampled data obtained by the sampling unit; a decimation unit for decimating the interpolation data obtained by the interpolation unit using a second clock; a phase comparator for detecting a phase error of an output signal of the decimation unit; a loop filter for smoothing the output signal of the phase comparator; a numerically controlled oscillator for generating an oscillation signal with a frequency in accordance with an output of the loop filter; an interpolation control unit for controlling an operation of the interpolation unit in accordance with the oscillation signal; and a clock control unit for generating the second clock form the first clock in accordance with the oscillation signal, wherein the numerically controlled oscillator generates the oscillation signal by cumulatively adding an output value of the loop filter and subtracting a certain value and the output value of the loop filter from the added value when the added value exceeds a threshold.