Patent ID: 7084681
Filing Date: 2006-08-01
Classification: H03D

Abstract:
1. A circuit comprising: an edge counter that counts rising edges and falling edges of a first clock signal; and a lock state machine having a lock state, a wait for lock state and a no lock state, wherein the lock state machine passes to the lock state when the first clock signal locks to a second clock signal in the wait-for-lock state, wherein the lock state machine passes to the no-lock state when the first clock signal is no longer locked to the second clock signal in the lock state, wherein the lock state machine passes to the wait for lock state when a valid cycle of the second clock signal occurs in the no-lock state, and wherein the valid cycle occurs when the edge counter counts a single rising edge and a single falling edge of the first clock signal during a cycle period of the second clock signal; wherein each of a number of consecutive valid cycles has a cycle period, further comprising: a cycle counter that counts the number of consecutive valid cycles of the second clock signal during which a single rising edge and a single falling edge of the first clock signal occur during each of the cycle periods of the consecutive valid cycles of the second clock signal.