Patent ID: 6557085
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A circuit configuration for handling access contentions in a memory with N mutually independent, simultaneously addressable I/O ports, comprising:at least one contention identification circuit for identifying an access contention between a plurality of said I/O ports to a given memory cell of said memory; at least one contention inhibit circuit connected to said contention identification circuit, said contention inhibit circuit constructed for receiving status signals of said contention identification circuit, and in an event of an access contention between a plurality of said I/O ports to the given memory cell, generating output signals enabling one of said plurality of said I/O ports involved in said access contention and inhibiting all other ones of said plurality of said I/O ports involved in said access contention; and N(Nâˆ’1)/2 signal lines connecting said contention identification circuit to said contention inhibit circuit, said contention identification circuit generating said status signals on said signal lines, said status signals defining which ones of said I/O ports are involved in said access contention; said contention identification circuit including N(Nâˆ’1)/2 multiple input EXOR gates for generating said status signals as a logic combination of addresses of said N I/O ports; and said contention inhibit circuit constructed for prioritizing said I/O ports in accordance with an importance thereof defined by a prioritization algorithm.