Patent ID: 8320187
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, the memory cell storing data of multi-levels corresponding to a plurality of threshold values, a row control circuit configured to control the rows of the memory cell array; a column control circuit configured to control the columns of the memory cell array; a latch circuit configured to temporarily hold external data and a result of verify; a bit scan circuit configured to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify; a processing unit configured to perform an operation process based on a scan result of the bit scan circuit; and a control circuit configured to control operations of the row and column control circuits to write the external data to the memory cells connected to a selected word line and control an operation of writing the external data according to a first mode in which a first voltage used for an upper-data writing is calculated during a lower-data writing and a second mode in which a write voltage based on setting information is set; wherein the bit scan circuit scans the number of to-be-written memory cells before starting the external data writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes in which the writing is performed based on a result of comparison.