Patent ID: 6084453
Filing Date: 2000-07-04
Classification: H03K

Abstract:
A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of (1/2.sup.K).times.100%, where K is a natural number, said circuit comprising:a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal;a cycle measuring circuit for measuring a cycle of the first clock pulse signal, which is approximately m times a unit time, the cycle measuring circuit having a plurality of first delay elements connected in cascade;a number converting circuit for multiplying m by 1/2.sup.K ;a time converting circuit for generating a second pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2.sup.K times the unit time, the time converting circuit having a plurality of second delay elements connected in cascade, each of said second delay elements corresponding to two or more first delay elements; anda logic circuit for generating the second clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal.