Patent ID: 6593190
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A method for manufacturing a non-volatile memory device, the method comprising the steps of:forming field areas and active areas on a semiconductor substrate such that the active areas are spaced by the field areas and extend in a first direction while being repeatedly arranged in a second direction that is orthogonal to the first direction; forming a plurality of word lines, string select lines and ground select lines on the semiconductor substrate with the active areas, wherein the word lines extend in the second direction while being repeatedly arranged in the first direction, wherein the string select lines are adjacent to a first word line among the word lines and extend in the second direction, and wherein the ground select lines are adjacent to a last word line among the word lines and extend in the second direction; forming a first insulating interlayer on the word lines, the string select lines, the ground select lines and the semiconductor substrate; etching the first insulating interlayer to form a first opening which partially exposes the active area formed between the ground select lines and extends in the first direction, and to form a second opening which partially exposes the active areas formed between the string select lines and extends in the second direction; forming a common source line in the first opening and a pad line in the second opening; forming a hard mask layer pattern on the common source line, the pad line, and the first insulating interlayer, the hard mask pattern being patterned in a same size as the active area; forming a bit line contact pad by slantingly etching the pad line using the hard mask layer pattern such that a sidewall of the bit line contact pad comprises a negative slope in the first direction and a positive slope in the second direction; forming a second insulating interlayer on the bit line contact pad and the first insulating interlayer; and forming a bit line contact hole for exposing the bit line contact pad by etching the second insulating interlayer.