Patent ID: 7054194
Filing Date: 2006-05-30
Classification: G11C

Abstract:
1. A non-volatile static random access memory (SRAM) cell, comprising: an SRAM unit, which receives a 1-bit datum, temporarily stores the 1-bit datum, and transmits the 1-bit datum for normal operations; and a non-volatile memory unit, which connects to the SRAM unit for storing the 1-bit datum in the SRAM unit before power is turned off (storage operation), keeping the 1-bit datum (storage operation), recovering the 1-bit datum back to the SRAM unit once the power supply is resumed (recovery operation), and erasing the 1-bit after the recovery operation is completed (erase operation), the non-volatile memory unit further including two split-gate transistors, each of the split-gate transistors including a control gate, a source and a drain, the control gates of the split-gate transistors being connected, the sources of the split-gate transistors being connected and having a same voltage level, the drains of the split-gate transistors storing the 1-bit datum in the SRAM unit; wherein a voltage on the control gates of the split-gate transistors is higher than that a voltage on the sources of the split-gate transistors during the storage operation.