Patent ID: 6429066
Filing Date: 2002-08-06
Classification: H01L,Y10S

Abstract:
A method for forming a capacitor element, comprising the steps of:(a) providing a semiconductor substrate having a surface; (b) forming a well region of a first conductivity type in the surface of the substrate; (c) forming a dielectric film on the surface of the substrate; (d) forming a polycrystalline silicon gate conductor of the first conductivity type on the dielectric film over the well region of the substrate; (e) forming a first pair of first conductivity type impurity diffusion regions, said gate conductor lying over a portion of the substrate between the first pair of first conductivity type impurity diffusion regions; (f) depositing a hybrid resist on the substrate and the gate conductor; (g) exposing the hybrid resist through a mask; (h) developing the hybrid resist; (i) removing portions of the hybrid resist; (j) forming a plurality of gate edges in the hybrid resist; (k) forming a plurality of implants at the gate edges; and (l) forming a second pair of first conductivity type impurity diffusion regions, each of said second pair of first conductivity type impurity diffusion regions being located between the gate conductor and a respective one of the first pair of first conductivity type impurity diffusion regions.