Patent ID: 9190989
Filing Date: 2015-11-17
Classification: G05F,G06F,H03K,Y02D

Abstract:
1. A method of power management of an integrated circuit, wherein the integrated circuit comprises a main domain and a low power domain, and is capable of operating in a full power mode of operation in which both the main domain and low power domain are active and a low power mode of operation in which the main domain is inactive and the low power domain is active, the method comprising: operating the integrated circuit in the full power mode under the control of a central controller; receiving a first instruction to switch from the full power mode to the low power mode; switching control of the low power domain from the central controller to a low power mode controller; gating the main domain so that the main domain is inactive; and receiving a second instruction to revert to the full power mode and subsequently controlling the main domain with the central controller and continuing to control the low power domain with the low power mode controller.