Patent ID: 7161520
Filing Date: 2007-01-09
Classification: H03M

Abstract:
1. An analog to digital converter comprising: an input switch array configured to, during a first time interval, sample a first input signal to a first input capacitor and a second input signal to a second input capacitor, said input switch array further configured to, during a third time interval, sample said first input signal to said second input capacitor and said second input signal to said first input capacitor; an integrator having a first and second integration capacitor; a cross switch array coupled between said input switch array and said integrator, said cross switch array configured to, during a second time interval, transfer charges sampled during said first time interval from said first input capacitor to said first integration capacitor and charges sampled during said first time interval from said second input capacitor to said second integration capacitor, said cross switch array further configured to, during a fourth time interval, transfer charges sampled during said third time interval from said first input capacitor to said second integration capacitor and charges sampled during said third time interval from second input capacitor to said first integration capacitor, wherein said fourth time interval is after said third time interval, said third time interval is after said second time interval, said second time interval is after said first time interval and said first, second, third, and fourth time intervals are non-overlapping; and a one-bit digital to analog converter responsive to an output of said integrator to provide a feedback analog signal.