Patent ID: 8138792
Filing Date: 2012-03-20
Classification: G09G

Abstract:
1. A gate drive circuit comprising: a shift register including a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals; a clock wiring extended along the first direction, the clock wiring electrically connected to a plurality of clock connecting wirings extended in a second direction crossing the first direction to deliver a clock signal to the stages; and a start wiring including a first wiring extended along the first direction and a second wiring connected to the first wiring and extended along the first direction to cross with the clock connecting wirings so as to deliver a vertical start signal to a first stage among the stages, wherein capacitors are formed where the second wiring of the start wiring crosses the clock connecting wirings, and static electricity applied to the start wiring is dispersed through the capacitors to decrease energy of static electricity applied to the shift register.