Patent ID: 6208280
Filing Date: 2001-03-27
Classification: H03M

Abstract:
An apparatus which converts a pulse-width modulation (PWM) signal to an analog voltage signal, the PWM signal comprising a series of cycles each having a first and a second level and a duty cycle expressed as a percentage of time the PWM signal is at the first level over each cycle, the analog voltage signal having a magnitude indicative of the duty cycle, the apparatus comprising:a current source which supplies electrical charge at a controllable rate;a ramp capacitor which, during selected, successively occurring cycles of the PWM signal, alternatively receives electrical charge from the current source and discharges previously received electrical charge;a first sampling capacitor which receives electrical charge from the ramp capacitor to output a feedback voltage to adjust the rate of electrical charge supplied by the current source; anda second sampling capacitor which receives electrical charge from the ramp capacitor to output the analog voltage.