Patent ID: 6303424
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A fabrication method for a dynamic random access memory device, the method comprising the steps of:forming a pad oxide layer and a nitride layer on a substrate;forming a plurality of shallow trenches in the substrate and defining an active region;forming a liner oxide layer to cover inner walls of the shallow trenches;forming a first barrier layer to cover the substrate;forming a bit line in some of the shallow trenches;filling some of the shallow trenches with an insulation layer where the bit line is not formed to form shallow trench isolation structures;removing the nitride layer;removing a portion of the pad oxide layer at a periphery of the shallow trenches to form a bit-line contact, wherein the bit-line contact extends into the active region and reveals a portion of the bit line;forming an elevated feature in the bit-line contact, in which the elevated feature is connected to the bit line and covers a part of the active region where a source region is to be formed; andforming a transistor in the active region, wherein the transistor comprises the source region and a drain region, and the source region is extended to a bottom of the elevated feature and is connected to the elevated feature.