Patent ID: 6456103
Filing Date: 2002-09-24
Classification: G01R,G06F

Abstract:
An apparatus for testing an integrated circuit device under test (DUT) by transmitting a first sequence of test signals to the DUT causing a first logic circuit implemented by the DUT to undergo a sequence of state changes during a test, said DUT having a first power input terminal for receiving a first current, wherein said DUT increases its demand for said first current during state changes and decreases its demand for said first current between state changes, the apparatus comprising:an integrated circuit (IC) tester for generating said first sequence of test signals and for generating a similar second sequence of test signals that precedes said first sequence of test signals; a reference IC similar to said DUT and having a second power input terminal similar to said first power input terminal of said DUT; a main power supply connected to said first power input terminal of said DUT for supplying a second current as input thereto; an auxiliary power supply connected to said second power input terminal of said reference IC; first means for conveying said first sequence of test signals from said tester to said DUT and for conveying said second test signal to said reference IC, wherein said DUT begins a state change of said sequence of state changes with a first delay after said reference IC begins a similar state change; and second means for monitoring a supply voltage appearing at said second power input terminal of said reference IC and for supplying with a second delay a third current into said first power input terminal of said DUT of magnitude determined in accordance with said variation of said supply voltage.