Patent ID: 6107660
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A vertical thin film transistor formed on a substrate, the vertical thin film transistor comprising:a conductive pad formed on said substrate;a first isolation layer formed on said conductive pad and said substrate;a gate patterned on said first isolation layer, wherein said gate is partially overlap with said conductive pad;a second isolation layer formed on said first isolation layer and said gate, wherein said second isolation layer, said first isolation layer and said gate includes an opening through therein;a gate oxide formed on a side-wall of said opening;a first doped region located at a lower portion of said opening;an undoped polysilicon formed in said opening and on said first doped region;a conductive structure formed on said opening and contacting said undoped polysilicon to act as a second doped region; anda third isolation layer formed on said conductive structure and said second isolation layer; whereinsaid first, second and third isolation layers includes a first contact hole through therein, saidsecond and said third isolation layers including a second contact hole through therein, saidthird isolation layer including a third opening through therein.