Patent ID: 6071785
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:(a) forming a first insulating film on a semiconductor substrate;(b) forming gate electrodes on said first insulating film, said gate electrodes having a two-layered structure including a first conductive film and a second insulating film lying over said first conductive film;(c) forming a diffusion layer around said gate electrodes;(d) forming an insulating sidewall film around a sidewall of said gate electrodes;(e) covering a resultant with a third insulating film;(f) forming a contact hole between said gate electrodes in self-aligning fashion;(g) covering a resultant with a second conductive film layer;(h) covering a resultant with a fourth insulating film;(i) planarizing said fourth insulating film;(j) isotropically etching said planarized fourth insulating film to expose a plurality of portions of said second conductive film layer;(k) covering a resultant with a third conductive film layer so that said third conductive film layer is in electrical contact with the exposed portions of the second conductive film layer; and(l) etching said third conductive film layer, said fourth insulating film and said second conductive film layer in a selective area to form a ground wiring layer having parallel conduction paths through the second and third conductive film layers, said parallel conduction paths being separated by the fourth insulating film.