Patent ID: 9130556
Filing Date: 2015-09-08
Classification: H03K

Abstract:
1. A semiconductor device comprising: a data terminal; a first power supply line supplying a first potential; a second power supply line supplying a second potential different from the first potential; a first buffer circuit coupled between the first power supply line and the data terminal; a second buffer circuit coupled between the second power supply line and the data terminal; a first control circuit generating first and second internal data signals that are complementary to each other; a level shifter generating third and fourth internal data signals that are complementary to each other by changing amplitude values of the first and second internal data signals; and an adjustment circuit to synthesize an inverted signal of the first internal data signal with the second internal data signal, and to synthesize an inverted signal of the second internal data signal with the first internal data signal, wherein the first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.