Patent ID: 8610650
Filing Date: 2013-12-17
Classification: G09G

Abstract:
1. A circuit, realizing a flat panel display capable to display images, comprising: an image storage and processing block for storing and processing said images to be displayed; a display and timing controller block controlling said display operation; an image pixel matrix containing a multitude of row- and column- line arranged pixel elements; one or more controlled row driver blocks; one or more controlled column driver blocks; and a pixel display operation for displaying said pixel elements employing an advanced multi-line addressing operation applied to a row and/or column drive activated pixel element display operation, whereby said advanced multi-line addressing operation comprises during every operating sequence lossless decomposition of image pixel data by analyzing image pixel data from multiple lines for common contents by image pixel data comparison using only pixel data calculation algorithms for said lossless decomposition operation of image pixel data which are requiring only one single pass through said image pixel data within one image frame period, thereby separating common parts of said image pixel data into a multi-line data domain and residual parts of the image pixel data into a single line data domain thus allowing for a display of these two data domains in separately activated pixel element display operations, wherein the lossless decomposition is performed by maximizing multi-line data in the multi-line data domain and minimizing single-line data in the single-line data domain within one image frame period.