Patent ID: 6417048
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A method for fabricating a flash memory with recessed floating gates, comprising the steps of:(a) providing a semiconductor substrate, on which a pad oxide layer and a first dielectric layer are formed in turn; (b) patterning said first dielectric layer by anisotropic etching, so as to form a plurality of trenches for recessed floating gates; (c) implanting ions into said semiconductor substrate, so as to define a plurality of bit line regions; (d) filling said plurality of trenches for recessed floating gates by depositing a second dielectric layer, which is to be planarized by chemical mechanical polishing (CMP); (e) removing said first dielectric layer; (f) forming a plurality of trenches by etching by using said second dielectric layer as an etching mask; (g) forming a tunnel dielectric layer on the top surface of said semiconductor substrate and said plurality of trenches; and (h) filling said plurality of trenches by depositing a first conductive layer, which is to be planarized by chemical mechanical polishing (CMP), so as to form recessed floating gates.