Patent ID: 9214552
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A method, comprising: forming a gate stack over a substrate; forming a spacer adjoining a sidewall of the gate stack; forming a first recess in the substrate aligned to the spacer; selectively etching a lower portion of the spacer relative to an upper portion of the spacer to form a second recess in the lower portion of the spacer; and forming a strain feature in the second recess, wherein the step of selectively etching the lower portion of the spacer relative to the upper portion of the spacer comprises: depositing a dummy layer over the gate stack and the spacer, and lining the first recess; partially etching the dummy layer such that the dummy layer is removed from the lower portion of the spacer but partially remains over the upper portion of the spacer and partially remains over the gate stack; and exposing the lower portion of the spacer to an etch process.