Patent ID: 6170078
Filing Date: 2001-01-02
Classification: G01R

Abstract:
A method for fault simulation testing of circuits, the method comprising the steps of: (a) providing a dynamically alterable behavioral model code of a circuit to be tested, said code able to perform a plurality of unique testing functions each simulating unique faults internal to said circuit wherein the behavioral model comprises at least one simulated fault bus line for receiving code input from a fault simulation tool, said simulated fault bus line not part of the circuit to be tested nor receptive of input from the circuit to be tested; (b) applying fault simulation test data directly to the behavioral model through the simulated fault bus; (c) altering the behavioral model responsive to said fault simulation test data to perform at least one of said unique testing functions, wherein each unique testing function is enabled to test said circuit responsive to said fault simulation test data on said simulated fault bus: and (d) recording the behavior of the behavioral model.