Patent ID: 6794921
Filing Date: 2004-09-21
Classification: H03K

Abstract:
A clamp circuit integrated in a semiconductor integrated circuit with an input terminal and configured to clamp a voltage inputted to the input terminal of the semiconductor integrated circuit, said clamp circuit comprising:a first transistor having a gate, a source, a drain connected to the gate and a conductivity type, said first transistor being configured to shift a target clamp voltage applied on the source by a gate-source voltage to output the shifted target clamp voltage, said gate-source voltage representing a voltage between the gate and the source of the first transistor; a buffer circuit having an output terminal and connected to the first transistor, said buffer circuit being configured to input the shifted target clamp voltage outputted from the first transistor and output a reference voltage according to the inputted shifted voltage; and a second transistor having a gate, a source, a drain and a conductivity type which is the same as the conductivity type of the first transistor, said gate being connected to the output terminal of the buffer circuit, said source being connected to the input terminal.