Patent ID: 6016005
Filing Date: 2000-01-18
Classification: H01L,H05K

Abstract:
A multilayer circuit assembly, comprising:a number of sintered sheets formed of a dielectric material, each of said sintered sheets having opposed major surfaces and a periphery, said each of said sintered sheets being formed with a selected density of registration holes and via;a number of electrically conductive patterns each deposited onto a major surface of one of said sintered sheets;said sintered sheets being vertically stacked on top of one another to form a stack, said via within said sintered sheets being filled with an electrically conductive material and at least some of said via in said each sintered sheet being positioned in electrical contact with said electrically conductive patterns deposited on adjacent sintered sheets within said stack of sintered sheets, said stack having an exterior surface defined by a first major surface of the uppermost sintered sheet in said stack, a second major surface of the lowermost sintered sheet in said stack and the combined peripheries of said individual sintered sheets extending between said first and second major surfaces;a sealing material applied to said exterior surface of said stack to substantially isolate said electrically conductive patterns from contamination.