Patent ID: 8946826
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of cell arrays arranged sequentially in a first direction, each of the plurality of cell arrays including a plurality of gates extending in the first direction and arranged in a second direction orthogonal to the first direction, wherein each of the plurality of cell arrays includes a first conductive type well region extending in the second direction and formed below the plurality of gates, wherein a first cell array of the plurality of cell arrays includes: wherein a second cell array of the plurality of cell arrays adjacent to the first cell array in the first direction includes three gates of the plurality of gates, each of the three gates is opposed to at least one of the first, second and third adjacent gates of the first cell array in the first direction, and wherein the first, second, and third adjacent gates of the first cell array are dummy gates, and the first adjacent gate overlaps a portion of the first well potential supply region.