Patent ID: 7589006
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising: forming a plurality of gate lines on a substrate; forming a gate spacer on the gate lines; forming a first cell spacer on the gate spacer; forming an insulation layer over the first cell spacer; etching the insulation layer to form a contact hole opening top portions of the first gate spacer and bottom portions of the first gate spacer between the neighboring gate lines; forming a second cell spacer on a resultant structure obtained after etching the insulation layer; forming a buffer layer on the second cell spacer; and etching the buffer layer, the second cell spacer and the first cell spacer to expose the surface of the substrate between the gate lines, wherein the first cell spacer is conformally formed on the gate spacer, gate lines and the substrate, and the second cell spacer is formed thinner on the surface of the substrate and sidewalls of the gate spacer than on the top surface of the gate spacer.