Patent ID: 6230304
Filing Date: 2001-05-08
Classification: G06F

Abstract:
An automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and upon a selected plurality of cells from a cell library, comprising the steps of:(a) assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells;(b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information;(c) performing track routing which sets the position of each of the global routes;(d) performing detailed placement.such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and(e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.