Patent ID: 8537629
Filing Date: 2013-09-17
Classification: G11C

Abstract:
1. A method of testing bitlines in a non-volatile memory device, the non-volatile memory device comprising a memory cell array and a plurality of bitlines crossing the memory cell array, the bitlines each having a first end and a second end, the bitlines being divided into a first group and a second group, the testing method comprising the steps of: supplying a supply voltage to the first group of bitlines from the first end of the bitlines to perform a charging process, and applying a ground voltage to the second group of bitlines; shutting down the charging process which is otherwise performed on the first group of bitlines, and applying the ground voltage to the bitlines from the second end thereof to perform a discharging process; identifying a status of each of the bitlines in the first group based on a voltage level of the first group of bitlines, wherein, if the voltage level of one of the bitlines in the first group is identified not the ground voltage, it will be determined that the bitline has an open-circuit defect; applying the supply voltage to the second group of bitlines from the second end of the bitlines to perform the charging process, and applying the ground voltage to the first group of bitlines from the first end of the bitlines to perform the discharging process; shutting down the discharging process which is otherwise performed on the first group of bitlines; and identifying the status of each of the bitlines in the first group based on a voltage level of the first group of bitlines, wherein, if the voltage level of the bitlines is identified not the ground voltage, it will be determined that the bitlines have developed a short circuit with the adjacent bitlines and have a short-circuit defect.