Patent ID: 6151658
Filing Date: 2000-11-21
Classification: G06F

Abstract:
A buffer coupled to an input bus on which address/data pairs and read requests are received, the buffer temporarily storing the address/data pairs and then writing the stored address/data pairs to an output bus, the buffer comprising:a dual-ported random access memory configured as a circular queue, First-In-First-Out (FIFO) buffer having a plurality of ranks for storing address/data pairs received from the input bus, the ranks having address locations associated therewith, each address/data pair having an address portion and a data portion;a write pointer to provide an available write address location at which a new address/data pair received from the input bus can be stored;a read pointer to provide an available read address location from which a stored address/data pair can be written to the output bus;a matching circuit to compare the address portion of a new address/data pair and an address portion of a read request received on the input bus to all stored address portions, the match circuit providing a hit indication comprising a matched address location if the received address portion matches one of the stored address portions;a write switch to direct the new address/data pair to a write address location in the FIFO buffer, the write address location corresponding to the matched address location in response to the hit indication, else corresponding to the available write address location, wherein, if directed to the matched address location, the data portion of the new address/data pair is combined with the stored data portion at the matched address location;a read switch to provide a read address location in the FIFO buffer from which to read the stored address/data pair, the read address location corresponding to the matched address location in response to the hit indication and the receipt of a read request, else corresponding to the available read address location; anda latch circuit to hold the stored address/data pair read from the read address location before writing the stored address/data pair to the output bus to prevent stalling of storage of a new address/data pair when the read address location is the same as the write address location.