Patent ID: 9189274
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. An apparatus for predicting performance attributable to parallelization of hardware acceleration devices, comprising: a processor coupled to a memory; a setting unit configured to divide a time it takes to perform a task into a plurality of task stages and a plurality of processing stages and to set one of a parallelization index and a target performance; an operation unit configured to calculate a time it takes to perform each of the plurality of task stages and the plurality of processing stages, and to calculate at least one of a ratio of a target parallelization stage in the task and a speed improvement value using the calculated times; and a prediction unit configured to calculate an expected performance value or a parallelization index using at least one of the calculated times it takes to perform the plurality of task stages and the plurality of processing stages, the calculated ratio of the target parallelization stage, the calculated speed improvement value, and the set target performance, wherein the setting unit provisions a number of hardware acceleration devices using the parallelization index to achieve the expected performance value or using the parallelization index to achieve the set target performance.