Patent ID: 8847396
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: receiving a precursor, the precursor including: depositing a decomposable polymer layer (DPL) in the space between the conductive features on the precursor; annealing the DPL to form an ordered periodic pattern of different types of polymer nanostructures between the conductive features; performing a first selective etch to decompose a first type of the polymer nanostructures to form a trench and a template with the ordered repeating periodic pattern of the trench and a second type of polymer nanostructures between conductive features; filling in the trench with a dielectric layer to form a dielectric block; and performing a second selectively etching to decompose the second type of polymer nanostructures to form a dielectric matrix of nano-air gaps and the dielectric block between constructive features.