Patent ID: 6853382
Filing Date: 2005-02-08
Classification: G06F,G06T,G09G

Abstract:
1. A graphics subsystem, comprising: a graphics memory; a graphics memory access bus connected to said graphics memory; a plurality of graphics processing units, each graphics processing unit issuing memory requests, each individual memory request having an associated data transfer size; and a memory controller connected between said graphics memory access bus and said plurality of graphics processing units, said memory controller providing a non-partitioned view of said graphics memory to said plurality of graphics processing units, while dividing said graphics memory access bus into individual bus partitions, each of which is a fraction of the graphics memory access bus size, said memory controller partitioning information within said graphics memory into independently accessible memory partitions, said memory controller routing data between said independently accessible memory partitions and said plurality of graphics processing units via said individual bus partitions, said memory controller determining which memory requests are to be serviced in particular clock cycles via one or more of said independently accessible memory partitions and said memory bus partitions; wherein said memory controller identifies memory requests requiring a subset of said independently accessible memory partitions and determines if another memory request can be serviced in parallel via another subset of said independently accessible memory partitions to improve throughput.