Patent ID: 6710390
Filing Date: 2004-03-23
Classification: H01L,Y10S

Abstract:
A DRAM array comprising:a first node location, a second node location and a third node location associated with a semiconductor substrate, the second node location disposed between the first and third node locations; a first transistor gate configured to electrically couple the first node location to the second node location; a second transistor gate configured to electrically couple the second node location to the third node location; an electrically insulative layer over the node locations and having a horizontally extending uppermost surface; a first storage node and a second storage node, each extending through the electrically insulative layer, the first and second storage nodes electrically coupling to the first node location and the third node location, respectively, each of the first storage node and the second storage node, in cross-sectional view, comprising: an upper surface elevationally above the horizontally extending uppermost surface of the electrically insulative layer, the upper surface essentially parallel to the horizontally extending uppermost surface of the electrically insulative layer; and an outer lateral surface continuously extending elevationally downward from the upper surface along a first vertical axis perpendicular to the horizontally extending uppermost surface, the outer lateral surface comprising an upper portion disposed elevationally above the horizontally extending uppermost surface, the upper portion having a doped rugged polysilicon-comprising surface, the outer lateral surface further comprising a lower portion contiguous with the upper portion, the lower portion disposed elevationally below the horizontally extending uppermost surface and having a doped non-rugged-polysilicon-comprising surface, the array further comprising: a conductive contact extending through the electrically insulative layer to the second node location, the conductive contact comprising an upper portion having a rugged polysilicon outer surface above the horizontally extending uppermost surface and a lower portion having a non-rugged-doped-polysilicon outer surface below the horizontally extending uppermost surface; a first dielectric layer and a second dielectric layer, proximate the first storage node and the second storage node, respectively; a first cell plate layer and a second cell plate layer, proximate the first dielectric layer and the second dielectric layer, respectively; the first cell plate layer, first dielectric layer and first storage node together defining a first capacitor and the second cell plate layer, second dielectric layer and second storage node together defining a second capacitor; and a bitline electrically connected to the conductive contact; the conductive contact and first capacitor together defining a first DRAM cell configured to be electrically coupled to the bitline; the conductive contact and second capacitor together defining a second DRAM cell configured to be electrically coupled to the bitline, wherein the bitline is formed atop a second electrically insulative layer formed above the first and second DRAM cells.