Patent ID: 9082865
Filing Date: 2015-07-14
Classification: G11C,H01L

Abstract:
1. A split-gate type nonvolatile memory device comprising: a semiconductor substrate having a first conductivity type; a deep well having a second conductivity type in the semiconductor substrate; a pocket well having the first conductivity type in the deep well, wherein the pocket well is isolated from the substrate by the deep well; a source line region having the second conductivity type in the pocket well; an erase gate on the source line region; and a first floating gate and a first control gate stacked sequentially on the pocket well on a first side of the erase gate; a first bit line region having the second conductivity type in the pocket well, wherein the first bit line region is spaced apart from the source line region; a first select gate on the pocket well between the first bit line region and the source line region, wherein the first select gate is adjacent to the first bit line region, wherein the first floating gate and the first control gate are between the first select gate and the erase gate; a second floating gate and a second control gate stacked sequentially on the pocket well on a second side of the erase gate; a second bit line region having the second conductivity type in the pocket well, wherein the second bit line region is spaced apart from the source line region; and a second select gate on the pocket well between the second bit line region and the source line region and adjacent to the second bit line region, wherein the second floating gate and the second control gate are between the second select gate and the erase gate.