Patent ID: 8004487
Filing Date: 2011-08-23
Classification: G09G

Abstract:
1. A display device comprising: a display panel including a plurality of video lines; a plurality of data drivers that transmit a video voltage to each of the video lines; and a display control circuit that controls or drives the plurality of data drivers, wherein: a data driver includes: an internal control signal production circuit that groups the plurality of video lines into a plurality of blocks, and produces first internal control signals and second internal control signals which are used to make the transmission timings of video voltages onto video lines, which belong to the blocks, different from one another among the blocks; a first latch circuit that sequentially latches display data items which express one display line and which are received successively externally; a second latch circuit that latches the display data items which have been latched into the first latch circuit; a third latch circuit that latches the display data items, which have been latched into the second latch circuit and are associated with the respective blocks, at timings which are different from one another among the blocks; and a decoder that converts the display data items, which have been latched into the third latch circuit, into video voltages; the second latch circuit latches the display data items, which have been latched into the first latch circuit, at timings that are different from one another among the blocks; before the first latch circuit latches succeeding display data items associated with the blocks, the second latch circuit latches display data items that have already been latched into the first latch circuit; and before the second latch circuit latches succeeding display data items from the first latch circuit, the third latch circuit latches display data items that have already been latched into the second latch circuit; the first latch circuit latches display data items responsively to fetch signals; the second latch circuit latches display data items, which have been latched into the first latch circuit, responsively to first internal control signals produced by the internal control signal production circuit; the third latch circuit latches display data items, which have been latched into the second latch circuit, responsively to second internal control signals produced by the internal control signal production circuit; the first internal control signals are signals that are synchronous with whichever one of the fetch signals, responsively to which the last display data among display data items associated with the blocks is latched, and the second internal control signals, responsively to which the display data items associated with the blocks are latched, that are invalidated last.