Patent ID: 7709956
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A semiconductor wafer comprising: a plurality of conductive regions; an isolation structure that touches the plurality of conductive regions, the isolation structure having a top surface; a number of seed structures that touches the isolation structure, and extends down from the top surface of the isolation structure into the isolation structure, the number of seed structures each having a bottom surface, the bottom surface of each seed structure lying substantially in a common horizontal plane; and a number of conductive structures that touches the number of seed structures, and extends down from the top surface of the isolation structure into the isolation structure, the number of conductive structures including a plurality of first conductive structures and a plurality of second conductive structures, the plurality of first conductive structures having top surfaces that lie substantially in a first common plane, the plurality of second conductive structures having top surfaces that lie substantially in a second common plane that lies above the first common plane, each conductive structure being substantially only copper.