Patent ID: 7709898
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A semiconductor protection circuit provided on a semiconductor substrate for protecting a semiconductor device including an interconnect from charge entering said interconnect during fabrication of said semiconductor device, comprising: a first metal interconnect connected to said interconnect and disposed on an upper layer than said interconnect; a forward diode having an input port connected to said interconnect; a backward diode that has an output port connected to said interconnect and is connected to said forward diode in parallel; an N-channel MIS transistor whose drain is connected to an output port of said forward diode, whose source is connected to said semiconductor substrate and whose gate electrode is grounded through a second metal interconnect disposed on an upper layer than said first metal interconnect; a P-channel MIS transistor whose drain is connected to an input port of said backward diode and whose source is connected to said semiconductor substrate; a first antenna connected to the gate electrode of said N-channel MIS transistor and disposed on the same interconnect layer as at least a part of said first metal interconnect; and a second antenna connected to a gate electrode of said P-channel MIS transistor and disposed on the same interconnect layer as at least a part of said first metal interconnect.