Patent ID: 8618649
Filing Date: 2013-12-31
Classification: H01L,H05K

Abstract:
1. A package for a semiconductor device having electrical terminals, the package comprising: a substrate including at least one semiconductor device; a first dielectric layer selectively printed on at least a portion of the semiconductor device comprising first recesses aligned with a plurality of the electrical terminals; a conductive material printed in the first recesses forming contact members on the semiconductor device; a second dielectric layer selectively printed on at least a portion of the first dielectric layer comprising second recesses aligned with a plurality of the first recesses; a conductive material printed in at least a portion of the second recesses comprising a circuit geometry; a third dielectric layer selectively printed on at least a portion of the second dielectric layer comprising third recesses aligned with a portion of the circuit geometry; a conductive material printed in the third recesses comprising a plurality of exposed terminals that are offset from, and electrically coupled to the electric terminals on the semiconductor device by the circuit geometry; and a compliant material deposited in recesses in one or more of the first, second or third dielectric layers adjacent to a plurality of the exposed terminals to permit the exposed terminals to move within the dielectric layers relative to the substrate.