Patent ID: 6537873
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A process for fabricating an integrated circuit comprising a semiconductor substrate supporting a memory cell of the DRAM type comprising an access transistor and a storage capacitor, wherein:a) an initial single-crystal substrate having locally a capacitive trench containing a polycrystalline fill material emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice is prepared; b) the initial substrate is recessed at the trench; c) the single-crystal lattice of the substrate around the periphery of the recess and the emergent part of the polycrystalline material for filling the trench are amorphized locally and so as to be self-aligned with respect to the trench; d) a layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained in the previous step; e) the structure obtained in the previous step is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate; and f) an upper substrate layer, in and on which the access transistor is made, is grown by epitaxy, the capacitive trench forming the storage capacitor being in contact with one of the source and drain regions of the transistor.