Patent ID: 6618799
Filing Date: 2003-09-09
Classification: G06F

Abstract:
A processing node configured to perform selective address translation, said node comprising:a first processor; a first local memory, wherein a first address space and a second address space are mapped to said first local memory; and a first system interface; wherein data which is local to said node is assigned an address in said first address space and data which is not local to said node is assigned an address in said second address space, and wherein addresses within each of said first address space and said second address space are mapped to local physical addresses of said node; wherein said system interface is configured to: convert a local physical address of a transaction initiated by said first processor to a global address prior to initiating a global transaction corresponding to said transaction, in response to detecting that said local physical address corresponds to said second address space; and initiate said global transaction without converting said local physical address to a global address, in response to detecting that said local physical address corresponds to said first address space.