Patent ID: 6479862
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A semiconductor structure comprising:a trapping layer located proximate to a transistor channel, which transistor channel is capable of carrying a current that varies continuously from a first current value associated with a conducting condition for said transistor channel, to a second current value associated with a non-conducting condition for said transistor channel, said second current value being substantially less than said first current value; and a plurality of carrier trapping sites located within said trapping layer, said carrier trapping sites being configured for trapping carriers that are electrically biased by an electrical control field to move from said transistor channel into said trapping layer; wherein said trapping sites have a concentration and arrangement within said trapping layer so that a density of carriers in said transistor channel available for carrying said current is increased or decreased by correspondingly dynamically increasing or decreasing a number of carriers stored by said trapping sites.