Patent ID: 6028447
Filing Date: 2000-02-22
Classification: H03K

Abstract:
A field-programmable gate array comprising a plurality of programmable cells, wherein:a first subset of the plurality of programmable cells are logic cells;a second subset of the plurality of programmable cells are input/output (I/O) cells;at least one of the plurality of programmable cells comprises one or more cell output nodes and an output node circuit for each of the cell output nodes;at least one output node circuit comprises:(a) an internal output data node;(b) an output buffer having (1) a data-in port connected directly to the output data node, (2) a tri-state port, and (3) a data-out port, and adapted to receive (i) an output data signal at the data-in port directly from the output data node and (ii) a tri-state signal at the tri-state port and to generate an output signal at the data-out port for the cell output node; and(c) a mux having two mux input ports, one of which is connected directly to the output data node, and a mux output port connected directly to the tri-state port of the output buffer and adapted to receive (i) the output data signal directly from the output data node and (ii) the tri-state signal at the two mux input ports and to generate at the mux output port a signal to be transmitted directly to the tri-state port of the output buffer to provide a dedicated path for the output data signal to be transmitted from the output data node to the tri-state port without passing through any other intervening logic in order to configure the output node circuit in an open-drain drive mode.