Patent ID: 6147631
Filing Date: 2000-11-14
Classification: H03M

Abstract:
An input sampling circuit comprising:main input sampling structure comprising:an integrator having a positive input terminal and a negative input terminal;a first capacitor; anda first plurality of switches for selectively connecting the first capacitor to a common mode voltage, the negative input terminal, a first input signal line, a first reference line, and a second reference line; anda first replica input sampling structure coupled to the main input sampling structure, the first replica input sampling structure comprising:a first buffer connected to the first input signal line, the first buffer reducing the signal dependent current from the first input signal thereby reducing gain error;a second capacitor; anda second plurality of switches for selectively connecting the second capacitor to the common mode voltage, the first buffer, and the first and second reference lines such that a signal-dependent current that is drawn from the reference signal lines is cancelled in the main input sampler.