Patent ID: 6162660
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method for fabricating a semiconductor chip package, comprising the steps of:bringing a region of solder, mounted on a chip contact pad of a semiconductor integrated circuit chip, into contact with a carrier contact pad of a chip carrier substrate, which solder region has a composition which includes at least a first component and a second component and which carrier contact pad includes a pad region having a composition which includes at least a third component;forming a region of material at and/or adjacent to the interface between said solder region and said carrier contact pad, which material region has a composition which includes at least said second component and said third component, while using said solder region and said carrier contact pad as sources of said second component and said third component, said material region having a melting temperature which is lower than that of said solder region and of said carrier contact pad;disassociating said region of material; anddiffusing at least said third component of said material region into said solder region via solid state diffusion.