Patent ID: 8508968
Filing Date: 2013-08-13
Classification: G11C,H01L

Abstract:
1. A semiconductor apparatus comprising: a plurality of logic semiconductor chips each including a processor; a memory semiconductor chip stacked in a layer above or below the plurality of logic semiconductor chips; and a plurality of penetration-electrodes, wherein a penetration-electrode among the plurality of the penetration-electrodes, for use in establishing communication between the memory semiconductor chip and the plurality of the logic semiconductor chips, is disposed in such a way as to be in a band-like form and in a central region in each of the plurality of logic semiconductor chips and the memory semiconductor chip, and wherein penetration-electrodes among the plurality of the penetration-electrodes, for use in establishing communication among the plurality of the logic semiconductor chips, are disposed in a dispersed fashion inside a region of each of the plurality of the logic semiconductor chips.