Patent ID: 9048335
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: receiving a substrate, the substrate having a first region, a second region, and a third region defined thereupon; forming a first interfacial layer over the first region, the second region, and the third region; etching the first interfacial layer to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region, wherein the etching of the first interfacial layer defines a first gate stack having a first gate stack height within the third region, wherein the first gate stack includes: forming, after the etching of the first interfacial layer, a second interfacial layer over at least a portion of the second region; etching the second interfacial layer to define a second gate stack within the second region, wherein the second gate stack has the first gate stack height and includes: forming, after the etching of the second interfacial layer, a third interfacial layer on the substrate over at least a portion of the first region to define a third gate stack within the first region the third gate stack within the first region has the first gate stack height, and wherein the third gate stack includes: wherein the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.