Patent ID: 8749535
Filing Date: 2014-06-10
Classification: G09G

Abstract:
1. A display driver integrated circuit comprising: a plurality of driver circuits, wherein each driver circuit in the plurality of driver circuits respectively provides output data; a clock bus having a multi-drop connection to the plurality of driver circuits; a resistive termination circuit coupled to the clock bus; and a timing controller providing a first clock signal to the plurality of driver circuits via the multi-drop connection of the clock bus, and providing a respective differential data signal to each driver circuit via a respective point-to-point connection, wherein each driver circuit comprises a clock regenerator receiving the first clock signal and generating a third clock signal, and wherein each driver circuit comprises: a de-skew circuit receiving the respective differential data signal and the third clock signal and generating a de-skewed data signal and a fourth clock signal; and a de-serializer circuit receiving the de-skewed data signal and the fourth clock signal and generating the output data and a corresponding fifth clock signal.