Patent ID: 8271979
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. A storage system operative with a higher-level device to receive a plurality of input/output (I/O) requests from said device, comprising: a plurality of microprocessors, including a plurality of first microprocessors and a plurality of second microprocessors; a plurality of storage devices, which read and write data according to I/O task processing regarding the I/O requests; cache memory, which temporarily stores data exchanged with the higher-level device and with said plurality of storage devices; wherein the first microprocessors execute I/O task processing regarding the I/O requests and control communication with the higher-level device and with said cache memory; wherein the second microprocessors control communication with said storage devices and with said cache memory, wherein, in case that one of the I/O requests is a write request, one of the first microprocessors which executes I/O task processing regarding the write request assigns a part of the I/O task processing regarding the write request to an assignee microprocessor which is one of the first microprocessors, if a load thereof is equal to or greater than the predetermined value, wherein, in case that one of the I/O requests is a read request, one of the first microprocessors, which executes I/O task processing regarding the read request, assigns a part of the I/O task processing regarding the read request to an assignee microprocessor, which is one of the second microprocessors, if a load thereof is equal to or greater than the predetermined value, wherein when said first microprocessors assigns a part of the I/O task processing regarding a write request to the assignee microprocessor, the first microprocessor accumulates data according to said write request in a buffer, and the first microprocessor writes data stored in said buffer to said cache memory, wherein, when said first microprocessor does not assign said write I/O task portion, said first microprocessor secures a cache area in said cache memory, writes data to said secured cache area, and thereafter unlocks said secured cache area; said write I/O task portion comprises cache control processing, comprising the securing of said cache area, and the unlocking of said secured cache area; and when said first microprocessor assigns a write I/O task portion to said assignee microprocessor which is one of the first microprocessors, said first processor accumulates data according to said write request in a buffer and issues a prescribed request to said assignee microprocessor; said assignee microprocessor, in response to the prescribed request, secures said cache area in said cache memory, writes data stored in said buffer to said secured cache memory, unlocks said secured cache area, and returns a completion report; and said first microprocessor, in response to the completion report, transmits status to said higher-level device.