Patent ID: 6271106
Filing Date: 2001-08-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor component comprising:providing a substrate;disposing a first layer over the substrate;disposing an etch stop layer over the first layer;disposing a sacrificial layer over the etch stop layer;patterning the sacrificial layer, the etch stop layer, and the first layer to form a gate stack comprising a portion of the first layer, a portion of the etch stop layer, and a portion of the sacrificial layer;disposing a dielectric layer over the substrate and the gate stack;exposing the portion of the sacrificial layer after disposing the dielectric layer;removing the portion of the sacrificial layer to create a via in the dielectric layer;disposing a barrier layer on the first layer in the via wherein the barrier layer does not extend onto sidewalls of the via;disposing a conductor layer onto the barrier layer; anddisposing a metal layer onto the conductor layer.