Patent ID: 9171999
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A thin film transistor array panel, comprising: a gate line disposed on a substrate; a gate insulating layer disposed on the gate line; a semiconductor layer disposed on the gate insulating layer; and a data line and a drain electrode disposed on the semiconductor layer, wherein: the data line and the drain electrode each comprise a lower layer and an upper layer, the lower layer comprising a first portion that protrudes outside an edge of the upper layer, the first portion comprising an upper surface that is parallel to an upper surface of the substrate and not covered by the upper layer; the semiconductor layer comprises a second portion that protrudes outside an edge of the lower layer, the second portion comprising an upper surface that is parallel to an upper surface of the substrate and not covered by the lower layer; the lower layer comprises one of titanium, tantalum, molybdenum, and alloys thereof; and the first portion and the second portion protrude from the same side of the upper layer.