Patent ID: 6473865
Filing Date: 2002-10-29
Classification: G06F,Y02D

Abstract:
A clock control circuit, comprising:a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a forward pulse by propagating said forward pulse, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a rearward pulse by propagating said rearward pulse, a control device to propagate said rearward pulse by said rearward-pulse delay line in a number of stages corresponding to the number of stages where said forward pulse was propagated by said forward-pulse delay line, a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and an electric power consumption control device to control electric power consumption of said rearward-pulse delay circuits, corresponding to the detected result of said forward-pulse detecting device.