Patent ID: 6088821
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A logic circuit verification device for a semiconductor integrated circuit, comprising:a synchronous circuit extracting unit for reading connection information among respective elements of the semiconductor integrated circuit described in a hardware description language and for extracting connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion from said connection information;a circuit information library for registering a pair of the connection information of the synchronous circuit portion and the connection information of the asynchronous circuit portion;said connection information of the synchronous circuit portion being logically equivalent to the connection information of the asynchronous circuit portion,a logic gate expansion processing unit for converting the connection information of the asynchronous circuit portion extracted by said synchronous circuit extracting unit into the connection information of the synchronous circuit portion read from said circuit information library and paired with said connection information of the asynchronous circuit portion;a cycle based simulation/static timing verification unit which, based on the connection information of the synchronous circuit portion which has been converted by said logic gate expansion processing unit and the connection information of the synchronous circuit portion extracted by said synchronous circuit extracting unit, executes verification of a logic circuit through a cycle based simulation method or a static timing verification method with respect to the synchronous circuits corresponding to said two pieces of the connection information; anda logic circuit simulation unit for executing verification of a logic circuit in accordance with an event-driven system with respect to the connection information of the asynchronous circuit which has not been converted into the connection information of the synchronous circuit by said logic gate expansion processing unit.