Patent ID: 6055183
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A method to erase a flash EEPROM cell, which is comprised of a control gate, a floating gate, a source, a drain, and a tunneling oxide disposed upon a semiconductor substrate, to prevent a write/erase threshold voltage closure and damage from high field stress in said tunneling oxide after repeatedly writing and erasing said flash EEPROM cell, comprising the steps of:a) applying a relatively high positive voltage pulse to the source of said EEPROM cell;b) simultaneously applying a ground reference voltage to the drain and to the semiconductor substrate; andc) simultaneously applying a relatively large negative voltage pulse to said control gate;wherein erasing the flash EEPROM cell causes a parasitic bipolar transistor inherent in said flash EEPROM cell to begin to conduct and go into a snap back condition, thus reducing excess field stress in said tunneling oxide, while removing charges from the floating gate.