Patent ID: 9142002
Filing Date: 2015-09-22
Classification: G06T

Abstract:
1. A graphic processor device implemented on a field programmable gate array circuitry, comprising: a pipeline formatter that sets graphic commands and vertex data into structures; a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein an output of the rasterizer is a stream of fragments that become pixels; a frame buffer operator that receives the stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer memory that is external to the graphic processor device, wherein the frame buffer operator also blends at least one of the plurality of fragments with a fragment that is already stored in the external frame buffer memory; a frame buffer manager that is in bidirectional communication with and controls the external frame buffer memory, wherein the external frame buffer memory includes a front buffer which is used for receiving graphics from the graphic processor device and a back buffer which is used for transmitting graphics from the graphic processor device; and an output processor configured to retrieve the plurality of fragments from the frame buffer manager and transmit a plurality of pixels according to a predefined resolution.