Patent ID: 8627008
Filing Date: 2014-01-07
Classification: G06F

Abstract:
1. An apparatus for memory access prediction comprising: a plurality of processors; a plurality of private memory caches associated with the processors such that there is at least one private memory cache associated with each processor; a physical memory; and a plurality of saturation counters associated with the processors such that there is at least one saturation counter associated with each processor, each of the saturation counters having an indicator bit for predicting whether a data item may be found by just a cache snoop or by accessing the physical memory in parallel with the cache snoop; wherein responsive to a cache miss in one of the private memory caches associated with one of the processors for a data item, the cache snoop and access to the physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined value (one (1) or zero (0)) whereas just the cache snoop is initiated if the indicator bit is a second predetermined value (zero (0) or one (1)) wherein the cache snoop is to each of the plurality of private memory caches other than the one of the private memory caches.