Patent ID: 6112288
Filing Date: 2000-08-29
Classification: G06F,Y10S

Abstract:
A pipeline processing system including a pipeline comprising:a) a plurality of accelerator chips coupled in series, a first and last one of said accelerator chips for coupling to an interface logic, wherein each of said accelerator chips includes:(i) an instruction processor;(ii) a plurality of pipeline processor segments coupled in series, each of said pipeline processor segments including:1) a plurality of pipeline processors coupled in series, each of said pipeline processors having an output and having as one input an output from a preceding pipeline processor, and, as a set of second inputs, a corresponding set of outputs from said instruction processor;2) a result processor having an output, and having as one input, an output from a prior result processor, and, as a second input, the output from a predetermined one of said plurality of pipeline processors.