Patent ID: 6252263
Filing Date: 2001-06-26
Classification: G11C,H01L

Abstract:
A layout structure for a semiconductor memory device, comprising:a semiconductor substrate of first conductivity type having a main surface;a plurality of memory cell array regions arranged in a row on the main surface of the semiconductor substrate;a plurality of bit line equalization regions formed on the main surface of the semiconductor substrate lateral to and spaced apart from the plurality of memory cell array regions, such that each one of the plurality of bit line equalization regions defines a column perpendicular to the row;a word line drive region disposed in the row between adjacent memory cell array regions and between columns defined by adjacent bit line equalization regions;an impurity region of second conductivity type formed parallel to the row and between the plurality of cell array regions and the plurality of bit line equalization regions on the main surface of the semiconductor substrate, the impurity region of second conductivity type being electrically coupled to the plurality of bit line equalization regions;a metal line extending over the impurity region of second conductivity type and supplying a bit line equalization voltage to the impurity region of second conductivity type; anda contact that electrically couples the metal line to the impurity region of second conductivity types and that is disposed lateral to the word line drive region in a columnar direction, so that no contacts are formed directly between the plurality of memory cell array regions and the plurality of bit line equalization regions in the columnar direction.