Patent ID: 8993392
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A method of forming an integrated circuit including PFETs, NFETs, and at least one vertically stacked, planar junction Zener diode, comprising: providing a substrate of a first conductivity type; forming a first gate electrode structure over a well of a second conductivity type, the well disposed in the substrate; forming a second gate electrode structure over the substrate in an area outside the well; forming recesses in the well adjacent to the first gate electrode structure, and simultaneously forming at least one recess in the substrate in an area outside the well; epitaxially growing first source/drain (S/D) terminals in the recesses adjacent to the first gate electrode structure, and simultaneously epitaxially growing a first planar diode junction in the recess outside the well; and epitaxially growing second S/D terminals adjacent to the second gate electrode structure, and simultaneously epitaxially growing a second planar diode junction over at least a portion of the first planar diode junction; wherein the second S/D terminals are raised S/D terminals.