Patent ID: 9099199
Filing Date: 2015-08-04
Classification: G11C

Abstract:
1. A memory cell, comprising: a first data node, a first complementary data node, a second data node, and a second complementary data node; a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch aligned as a first column of devices along a first direction; a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch aligned as a second column of devices along the first direction; and a first pull-up transistor and a second pull-up transistor aligned as a third column of devices along the first direction, the first pull-up transistor, the first pull-down transistor, and the third pull-down transistor being connected as a first inverter, the first inverter having a first output terminal, the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor being connected as a second inverter, the second inverter having a second output terminal, the first inverter and the second inverter being cross-coupled, and the first switch, the second switch, the third switch, and the fourth switch being arranged to respectively couple: