Patent ID: 6611462
Filing Date: 2003-08-26
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:a non-volatile memory; a data latch portion having [mÃ—n] latches, holding input write data in [mÃ—n] bits length, and outputting the write data to the non-volatile memory in batch; and a data fetch control portion for generating a data fetch pulse for fetching the write data into each latch of the n separate parts based on a logical value of the least significant address of write addresses in one write cycle of a write command of writing the write data into the non-volatile memory in â€œx m modeâ€ , wherein the data fetch control portion repeats a write data fetch command n times when the write command is input in the write cycle of the write command, and inputs the write data of [mÃ—n] bits in length to the data latch portion for each m bits in â€œx m modeâ€ , and the data latch portion outputs the write data of [mÃ—n] bits in length to the non-volatile memory in batch.