Patent ID: 8391085
Filing Date: 2013-03-05
Classification: G11C

Abstract:
1. A device comprising: a first memory area including a first memory cell array, a plurality of first sense amplifiers, and a plurality of first sub-amplifiers; at least one control line connected in common to the first sub-amplifiers, each of the first sub-amplifiers being activated in response to an active level of the control line, the control line being extended up to outside of the first memory area; and a sub-amplifier control circuit disposed outside the first memory area to be connected to the control line, the sub-amplifier control circuit receiving a set of control data to bring the control line to the active level, wherein the first memory area further includes first and second regions arranged in line in a first direction, each of the first and second regions includes first and second parts arranged in line in a second direction perpendicular to the first direction, the first memory cell array includes a first set of memory cells disposed in the first part of the first region and a second set of memory cells disposed in the first part of the second region, the first sense amplifiers includes a first set of sense amplifiers disposed in the second part of the first region and a second set of sense amplifiers disposed in the second part of the second region, the first memory area further includes a third region between the first and second regions, the third region includes third and fourth parts arranged in line in the second direction, the first sub-amplifiers are disposed in the third part of the third region.