Patent ID: 6573798
Filing Date: 2003-06-03
Classification: H03L

Abstract:
A PLL system comprising:phase comparison means for comparing a phase of an input horizontal sync signal with a phase of a comparison signal; variable-capacity charge pump means for outputting a charge pump signal in accordance with a phase error signal output from said phase comparison means; filter means for converting the charge pump signal from said charge pump means into a voltage control signal; a voltage-controlled oscillator for changing an oscillation frequency in accordance with the voltage control signal output from said filter means; frequency division means for performing 1/N frequency division of a frequency signal output from said voltage-controlled oscillator in accordance with a control signal; CRT drive means for performing deflection processing in a CRT on the basis of an output from said frequency division means and outputting, to said phase comparison means, said comparison signal based on a reference signal for a display system which is generated by CRT deflection processing; and arithmetic means for calculating said control signal to be output to said frequency division means from the horizontal sync signal and wherein said arithmetic means output a charge pump setting signal, wherein said variable-capacity charge pump means varies its capacity based upon said charge pump setting signal so as to compensate for a variation in PLL loop gain.