Patent ID: 7688648
Filing Date: 2010-03-30
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a memory cell which includes a floating gate MOS transistor having a charge trap region; and a memory string which includes a memory cell array configuring a NAND series connection, a first select transistor connecting to one side of the memory cell array, and a second select transistor connecting to the other side, where the first select transistor is connected to a local bit line; and a first dynamic circuit serving as a local sense amp connecting to the memory string, wherein the first dynamic circuit includes a pre-charge transistor for pre-charging the local bit line through a read transistor, a local amplify transistor for reading an amplify node connecting to the read transistor, where the local amplify transistor is serially connected to a local select transistor, a write transistor for connecting the local bit line to a write bit line; and a second dynamic circuit serving as a segment sense amp connecting to the local select transistor through a segment bit line, wherein the second dynamic circuit is composed of a reset transistor for resetting the segment bit line, a segment amplify transistor for reading the segment bit line where the segment amplify transistor is serially connected to a segment select transistor connecting to a global bit line; and a first tri-state inverter serving as an amplify circuit of a global sense amp connecting to the global bit line, wherein the global sense amp includes a read circuit, a data transfer circuit, a returning buffer and a write circuit; and the read circuit includes the first tri-state inverter for reading the global bit line and a pre-set transistor for pre-setting the global bit line; and the data transfer circuit includes a second tri-state inverter for bypassing a write data and a read inverter for reading a common node which is connected to the first tri-state inverter and the second tri-state inverter; and the write circuit receives the write data and drives the write bit line; and the returning buffer receives a read output from the read inverter through a returning read path; and a buffered data path connecting to the global sense amp, wherein the buffered data path is composed of a forwarding write line connecting to the second tri-state inverter, a forwarding read line connecting to the read inverter, and a returning read line connecting to the returning buffer; and an output latch circuit receiving and storing an output from the returning read line; and a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.