Patent ID: 7823093
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A system for reducing subexpressions in structural design representations, said system comprising: means for receiving an initial design, wherein said initial design represents an electronic circuit containing an AND gate of said system; means for selecting a first simplification mode for said initial design from a set of applicable simplification modes; means for performing a simplification of said initial design according to said first simplification mode to generate a reduced design, wherein said first simplification mode is an AND/OR simplification mode; means for determining whether a size of said reduced design is less than a size of said initial design; means, in response to determining that said size of said reduced design is less than a said size of said initial design, for replacing said initial design with said reduced design; means, responsive to determining that said size of said reduced design is not less than a said size of said initial design, for selecting a second simplification mode for said initial design from a set of applicable simplification modes; and means, responsive to determining that said size of said reduced design is not less than a said size of said initial design, for performing a simplification of said initial design according to said second simplification mode to generate a reduced design, when said means for performing a simplification of said initial design according to said second simplification mode to generate a reduced design further comprises, means, in response to determining that said reduced design does not meet a size parameter, for performing a simplification of said initial design according to said second simplification mode to generate a reduced design.