Patent ID: 8326083
Filing Date: 2012-12-04
Classification: G06F,G06T,G09G

Abstract:
1. An image processing circuit comprising: a image memory that stores the location and pixel value of each pixel that composes a plurality of graphical images disposed in an arrangement; a calculation unit that calculates a difference between a target location representative of a target to which the graphical images are to be aligned in binary image data in which the pixel value at each location is expressed as a binary value that includes 0 and an initial location representative of an initial point in the graphical images for aligning to the binary image data; a pixel value output unit that outputs pixel values resulting from shifting the pixel values stored in the image memory by an amount equivalent to the difference calculated by the calculation unit; a first multiplier that multiplies the pixel value at each location output by the pixel value output unit with the pixel value at each location included in the binary image data, for each of the corresponding pixel locations; an inverter that inverts the pixel value at each location in the binary image data; a second multiplier that multiplies the pixel values at each location in the binary image data or the pixel values at each location included in background image data that is to be the background of an image based on the binary image data with the pixel values inverted by the inverter, for each of the corresponding pixel locations; and an adder that adds the result of the multiplication performed by the first multiplier with the result of the multiplication performed by the second multiplier for each of the corresponding pixel locations and outputs the result of the adding as output image data.