Patent ID: 6794199
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A method for fabricating a ferroelectric memory including a plurality of ferroelectric capacitors, each of which has a lower electrode, a capacitor dielectric film of a ferroelectric film and an upper electrode successively formed on an interlayer insulating film on a semiconductor substrate, said plurality of ferroelectric capacitors being arranged along a bit line direction and a word line direction, comprising the steps of:forming said lower electrodes of said plurality of ferroelectric capacitors on said interlayer insulating film; depositing a first insulating hydrogen barrier film on said interlayer insulating film and said lower electrodes and planarizing said first insulating hydrogen barrier film, whereby filling said first insulating hydrogen barrier film between said lower electrodes of some ferroelectric capacitors, among said plurality of ferroelectric capacitors, that are arranged along one direction out of said word line direction and said bit line direction; forming, on said lower electrodes of said some ferroelectric capacitors arranged along said one direction and on said first insulating hydrogen barrier film, said capacitor dielectric film as a common capacitor dielectric film commonly used by said some ferroelectric capacitors arranged along said one direction; forming, on said common capacitor dielectric film, said upper electrode as a common upper electrode commonly used by said some ferroelectric capacitors arranged along said one direction; and forming, on said common upper electrode, a second insulating hydrogen barrier film covering said common upper electrode.