Patent ID: 7752512
Filing Date: 2010-07-06
Classification: G01R,G11C

Abstract:
1. A semiconductor integrated circuit comprising: a first circuit including a first scan chain and a second scan chain each including a plurality of flip-flops and configured to perform a scan path test; a second circuit configured to receive a signal from said first circuit in a normal operation mode through a first flip-flop being one of said plurality of flip-flops included in said first scan chain and a signal path which couples said first flip-flop with said second circuit; and a third circuit configured to exchange signals with said second circuit through said first flip-flop and said signal path without an intervention of a second flip-flop being one of said plurality of flip-flops included in said second scan chain when said third circuit tests said second circuit; and a third circuit configured to exchange signals with said second circuit through said first flip-flop and said signal path without an intervention of a second flip-flop being one of said plurality of flip-flops included in said second scan chain when said third circuit tests said second circuit, wherein said second scan chain performs said scan path test when said third circuit exchanges signals with said second circuit through said first flip-flop and said signal path without an intervention of said second flip-flop.