Patent ID: 6035383
Filing Date: 2000-03-07
Classification: G06F

Abstract:
Apparatus for processing data, said apparatus comprising:(i) a memory;(ii) a processor core for initiating a memory access request that is subject to subsequent confirmation in response to a confirm signal that indicates that said memory access request has completed such that no further variable response will result from said memory access request;(iii) a confirm signal generator for determining within a confirm signal delay period which confirm signal should be generated, said processor core being responsive to a confirm signal indicating a non-completed memory access request to recover said data processing apparatus to a state that is uncorrupted by said non-completed memory access request;(iv) a result prediction circuit responsive to one or more variable signals indicative of characteristics of said memory access request for determining within a result prediction delay period, which finishes before said confirm signal delay period, a prediction as to in which of a plurality of ways said memory access request will complete and for generating a result prediction signal, said processor core being responsive to said result prediction signal to prepare a predicted next memory access request for execution if said confirm signal indicates completion of said memory access request.