Patent ID: 7382641
Filing Date: 2008-06-03
Classification: G11C

Abstract:
1. A non-volatile ferroelectric memory device comprising: a plurality of cell array blocks each having a hierarchical bit line architecture including a plurality of main bit lines and a plurality of sub bit lines, wherein a voltage of a sub bit line induced by cell data is converted into current so that a sensing voltage of a main bit line is induced, the plurality of cell array blocks including main bit line groups each corresponding to a plurality of unit cells for storing differential data; a plurality of lines connected one by one to the plurality of main bit lines; a plurality of sense amplifier units connected one by one to the plurality of main bit lines through the plurality of lines, for sensing and amplifying the differential data outputted from the main bit line groups in a sensing operation; a plurality of local data buses, corresponding one by one to the plurality of sense amplifier units, for transferring the differential data outputted from the plurality of sense amplifier units and transmitting the differential data inputted to the plurality of sense amplifier units; and a global data bus, shared by the plurality of local data buses, for transferring the differential data, wherein the plurality of sense amplifier units, respectively, comprises: a main bit line sensing load unit for controlling a sensing load of the main bit line groups in response to a load signal; a sense amplifier switch unit, being turned on in read mode in response to a sense amplifier switch signal, for transferring the sensing voltage induced on the main bit line groups; a data latch unit, being activated in response to a sensing control signal, for sensing the sensing voltage on the main bit line groups which is transferred through the sense amplifier switch unit to latch the differential data; a write driving unit, being activated in response to a write control signal in write mode or restore mode, for transferring the differential data stored in the data latch unit to the main bit line groups; and a write selection unit for transferring the differential data applied from the plurality of local data buses to the data latch unit in response to a column selection signal; and a read selection unit for transferring the differential data stored in the data latch unit to the plurality of local data buses in response to the column selection signal.