Patent ID: 6780702
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A manufacturing method of a device for reducing parasitic capacitance on the laminated structure of an InP/InGaAs double heterojunction bipolar transistor (DHBT) comprising:a first process of alternately laminating a first and a second sub-collector InGaAs layers/a base InGaAs layer/an emitter InGaAs layer and an etch stop InP layer/a collector InP layer/a first and a second emitter InP layers on an InP substrate by an epitaxy method; a second process of depositing an emitter metal layer thereon and thereafter etching said emitter InGaAs layer and said first and second emitter InP layers in sequence, for a base metal to be self-alignable, to expose the upper surface of said base InGaAs layer; a third process of defining a photo resistor (PR) thereon for protecting the emitter region and thereafter etching said base InGaAs layer; a fourth process of etching said collector InP layer with using said base InGaAs layer as a mask to expose the upper surface of said second sub-collector InGaAs layer; a fifth process of selectively side-etching said second sub-collector InGaAs layer to expose the bottom surface of said collector InP layer where a void region is formed; a sixth process of performing an anisotropic selective etching on the bottom surface of said collector InP layer, which contributes to parasitic capacitance, with using said second sub-collector InGaAs layer as a mask and on the surface of said etch stop InP layer simultaneously to expose the upper surface of said first sub-collector InGaAs layer; and a seventh process of eliminating said photo resistor (PR) and thereafter depositing a metal layer to form a base- and a collector-metal layers.