Patent ID: 6069815
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A semiconductor memory having a memory cell array of memory cells arranged in rows and columns, comprising:a master bit line pair in each column, comprising first and second master bit lines with portions of the first and second master bit lines being vertically spaced from one another, and the first and second master bit lines twisting with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line, said vertical direction being perpendicular to a major surface of the memory cell array, the first and second master bit lines remaining substantially parallel in vertical planes;a plurality of local bit line pairs in each column coupled to memory cells, with at least one of the local bit lines operatively coupled to a master bit line anda hierarchical word line configuration comprising a plurality of master word lines, each associated with at least one row, at least one sub-master word line operatively coupled to each said word line, and a plurality of local word lines coupled to said memory cells and operatively coupled to the sub-master word line.