Patent ID: 6614258
Filing Date: 2003-09-02
Classification: H03K

Abstract:
A field-programmable dynamic logic array (FPDLA) comprising:an array of at least one dynamic programmable module (DPM), the at least one DPM comprises a cascaded combination of at least one dynamic PLA (DPLA), the at least one DPLA having an output and an input; and at least one micro clock, wherein each of the at least one DPM is controlled by the at least one micro clock, wherein at least one output of the at least one DPM is coupled to at least one input of at least one chronologically next DPM, and wherein the at least one DPM is controlled by its micro clock and the at least one chronologically next DPM is controlled by a second micro clock, the second micro clock is asserted after a sufficient time for the at least one output of the at least one DPM to become valid at the at least one input of the at least one chronologically next DPM.