Patent ID: 6804163
Filing Date: 2004-10-12
Classification: G11C

Abstract:
A semiconductor memory device having a reduced chip size comprising:local input/output (I/O) lines, global I/O lines, and a memory core, said memory core being coupled between a bit line and a complementary bit line, said memory core including a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A, wherein first and second transistors for connecting said local I/O lines to said global I/O lines are installed in a space between adjacent bit lines, and wherein the PMOS S/A driving circuit and the NMOS S/A driving circuit are installed in a space between adjacent bit lines.