Patent ID: 6544881
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A method of forming a stacked local interconnect in a semiconductor substrate having a plurality of electrical features formed thereon, at least one electrical feature of said plurality being an electrical contact located on a surface of said semiconductor substrate, having at least one etch stop layer on at least a portion of said surface of said semiconductor substrate, and having a passivation layer covering at least a portion of said at least one etch stop layer and covering at least a portion of said electrical contact, said method comprising:forming a first local interconnect; depositing a layer of resist over at least a portion of said at least one etch stop layer; patterning said layer of resist; providing a self-aligned contact etching process; etching through at least a portion of said passivation layer using said self-aligned contact etching process; exposing a portion of said electrical contact using said etching through said at least a portion of said passivation layer; forming a second local interconnect electrically connecting a first group of electrical features included within said plurality of electrical features; electrically connecting said second local interconnect to said first local interconnect during said forming thereof; and forming a third local interconnect electrically connected to said first local interconnect and at least one electrical feature of said plurality of electrical features.