Patent ID: 6675183
Filing Date: 2004-01-06
Classification: H03H,H04N

Abstract:
A semiconductor integrated circuit device on a semiconductor chip, comprising:a filter circuit which digitally filters a data string in which data of a plurality of data string element in which transmission frequency of one data string element is different from that of the other data string elements are multiplexed, wherein the filter includes: a delay line having (f1/f2)Ã—(Nâˆ’1) D flip-flops, wherein f1 is transmission frequency of the data string, f2 is transmission frequency of least among the data string elements in the data string and N is a number of taps; selector circuits which select one from two or more taps other than a center tap among a plurality of taps in the delay line; multipliers which multiply first data outputted from the selector circuits and second data outputted from the center tap by respective coefficients; and an adder which adds outputs of the multipliers, wherein the delay line is operated with the transmission frequency of the data string, and wherein the selector circuits process the plurality of data string elements in a time division manner by switching the taps coupled to the multipliers so that the interval between the taps is f1/f3 of the D flip-flops based on the center taps, where f3 is transmission frequency of the data string element outputted from the center tap at the time selected by the selectors.