Patent ID: 7028121
Filing Date: 2006-04-11
Classification: G06F

Abstract:
1. An arbitration parameter generating circuit comprising: a counter which receives a request signal generated in order for a master block to occupy a system bus and a grant signal generated in order for an arbitrator to allow the master block to occupy the system bus, up-counts when the request signal is at a first logic level, down-counts when the grant signal is at the first logic level, and is reset in response to a predetermined short term reference time signal; a short term arbitration parameter storage unit which receives and stores the counted signal as the short term arbitration parameter until the counter is reset in response to the short term reference time signal; a short term reference time measurement unit which generates the short term reference time signal in response to a clock signal whenever the short term reference time is over, in which the short term reference time indicates a time period for which the short term arbitration parameter is stored in the short term arbitration parameter storage unit; a long term arbitration parameter control unit which continuously accumulates the short term arbitration parameter outputted from the short term arbitration parameter storage unit, outputs the accumulated short term arbitration parameter as a long term arbitration parameter, and is reset in response to a long term reference time signal; and a long term reference time measurement unit which generates a long term reference time signal in response to the short term reference time signal whenever the long term reference time is over.