Patent ID: 6346454
Filing Date: 2002-02-12
Classification: H01L

Abstract:
A method of making an integrated circuit device including an interconnect structure and a capacitor, the interconnect structure comprising a metal line and a metal contact, and the capacitor comprising upper and lower metal, electrodes, the method comprising the steps of:forming a dielectric layer adjacent a semiconductor substrate; simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the dielectric layer; forming a mask over the second opening; selectively depositing a first metal conductive layer to fill the first opening; removing the mask from the second opening; depositing a lower metal layer to at least line the second opening and to form the lower metal electrode of the capacitor; forming a capacitor dielectric layer on the lower metal layer to form the capacitor dielectric of the capacitor; depositing an upper metal layer on the capacitor dielectric layer to form part of the upper metal electrode of the capacitor; depositing a second conductive layer to fill a remaining portion of the second opening and form part of the upper metal electrode of the capacitor; and planarizing an upper surface of the integrated circuit device.