Patent ID: 6145063
Filing Date: 2000-11-07
Classification: G06F,Y02D

Abstract:
A memory system comprising:a memory consisting of a plurality of banks each of which is made up of a plurality of segments, each of the segments being divided to correspond to a plurality of sub word lines which are provided to one main word line, and being independently accessible respectively, the memory being accessed in an interleaving manner;a status table having at least a same number of entries as the plurality of banks of the memory, accessed destination information such as comprising: bank Number, row address, segment address in access in the memory indicating an accessed destination and status information indicating access state of the accessed destination being stored in respective entries; andan access queue for receiving an access address of the memory, then extracting accessed destination information from the access address, and then controlling access to the memory based on extracted accessed destination information and information stored in the status table;wherein the access queue compares the accessed destination information with information stored in the status table to decide their coincidence, and if the same bank as that specified by the extracted accessed destination information is stored in the status table and is now being accessed, then refers to access states stored in the status table in correspondence to the accessed destination information contained in the access to the bank and then controls the access to the memory based on the access states and the information of the row address and the segment address of the accessed destination.