Patent ID: 6051507
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method of fabricating a capacitor with high capacitance, comprising:forming a dielectric layer having a contact window to expose an active region in a semiconductor substrate;forming a conductive layer on the dielectric layer to fill the contact window;forming an insulating layer on the conductive layer;patterning the insulating layer and the conductive layer, so that a portion of the dielectric layer is exposed;forming a hemispherical grained-Si (HSG-Si) layer over the substrate to cover the insulating layer, exposed sidewalls of the conductive layer and the exposed portion of the dielectric layer, wherein the HSF-Si layer comprises a plurality of gaps form between hemispherical silicon grains;performing an anisotropic overetching process to remove the HSG-Si layer, wherein a portion of the HSG-Si layer on the sidewalls of the conductive layer remains, and a plurality of trenches are formed in a top portion of the conductive layer since the insulating layer is first etched from the gaps of the HSG-Si layer and then the insulating layer functions as a trench mask on the conductive layer for forming the plurality of trenches; andremoving the insulating layer to expose the conductive layer to form a storage node of the capacitor.