Patent ID: 6512695
Filing Date: 2003-01-28
Classification: H01L

Abstract:
An electronic system, comprising:a memory; a processor coupled to the memory; and wherein the processor includes at least one programmable logic array including: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes: a horizontal substrate, wherein the substrate includes a source region, a drain region, and a channel region separating the source and the drain region; a vertical floating gate located above a first portion of the channel region adjacent to the source region and separated from the channel region by a first oxide thickness; and a vertical control gate located above a second portion of the channel region adjacent to the drain region and separated from the channel region by a second oxide thickness.