Patent ID: 8201035
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A testing system for detecting memory faults of a memory, the memory comprising a first and a second memory cell, the testing system comprising: a module data end, for receiving a testing data; a first writing pattern selection unit, coupled between the module data end and the first memory cell, for inverting the testing data according to a first pattern selection signal to generate a first writing pattern selection testing data, and transmitting the first writing pattern selection testing data to the first memory cell for storage; a second writing pattern selection unit, coupled between the module data end and the second memory cell, for inverting the testing data according to a second pattern selection signal to generate a second writing pattern selection testing data, and transmitting the second writing pattern selection testing data to the second memory cell for storage; a data pattern selection circuit, coupled between the first and second writing pattern selection units, for generating the first and the second pattern selection signals; a first reading pattern selection unit, coupled between the module data end and the first memory cell, for inverting data read from the first memory cell to generate a first reading pattern selection testing data, according to the first pattern selection signal; a second reading pattern selection unit, coupled between the module data end and the second memory cell, for inverting data read from the second memory cell to generate a second reading pattern selection testing data, according to the second pattern selection signal; and a data comparison circuit, for determining if the first or the second memory cells is damaged, the data comparison circuit comprising: wherein when the first and the second reading pattern selection testing data are not matched, the enabling signal represents disable for disabling the buffer, the reading determining data is of tri-state, and the testing system determines the first or the second memory cell to be damaged.