Patent ID: 9141742
Filing Date: 2015-09-22
Classification: G06F

Abstract:
1. In an electronic design automation (EDA) tool in a computer, a method for performing a priori corner and mode reduction based on a set of library cells, wherein the set of library cells includes delay information for each cell for a plurality of corners and a plurality of modes, wherein different modes correspond to different portions of a circuit design in which timing constraints need to be satisfied, the method comprising: identifying, by the EDA tool in the computer, for at least one corner, a portion of the circuit design that is common across a set of modes; replacing, by the EDA tool in the computer, the set of modes with a single mode for optimizing the portion of the circuit design that is common across the set of modes; creating, by the EDA tool in the computer, a synthetic corner in which a cell delay for each library cell in the set of library cells corresponds to a maximum delay over multiple temperature corners; and optimizing, by the EDA tool in the computer, the circuit design using the synthetic corner.