Patent ID: 7394823
Filing Date: 2008-07-01
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of memories; a plurality of systems, each of the plurality of systems including at least one processor, a cache, interface circuits for receiving and sending data, a bridge and a memory controller, in which the memory controller is coupled to a respective one of the plurality of memories and each of the plurality of systems is coupled to at least one other one of the plurality of systems for bi-directional data transfer between the plurality of systems, wherein each of the plurality of systems further comprises one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses, the plurality of systems including at least one system to bi-directionally receive and transmit packets to and from a network; and a switch interface circuit, wherein at least one system is coupled to the switch interface circuit separate from the interconnection of the plurality of systems, wherein the switch interface circuit is configured to interface the apparatus to a switch fabric, and wherein the switch interface circuit is coupled to bi-directionally receive and transmit packets between the at least one system coupled to the switch interface circuit and the switch fabric.