Patent ID: 7599219
Filing Date: 2009-10-06
Classification: G11C

Abstract:
1. An integrated circuit device, comprising: at least a first non-volatile memory device having at least a first array of nonvolatile memory cells therein, said first non-volatile memory device configured to program a row of non-volatile memory cells in the first array by repeatedly verifying the threshold voltages of a plurality of non-volatile memory cells in the row being programmed in parallel, using a plurality of memory verify operations that are interleaved in time relative to operations to increase threshold voltages of the plurality of non-volatile memory cells; wherein the plurality of memory verify operations include a first sequence of memory verify operations that are performed during corresponding first verify time intervals having equivalent durations; and wherein the first sequence of memory verify operations are followed by a second sequence of memory verify operations that are performed during corresponding second verify time intervals having equivalent durations greater than the durations of the first verify time intervals.