Patent ID: 8044912
Filing Date: 2011-10-25
Classification: G09G

Abstract:
1. A semiconductor device comprising: an address generator configured to output a plurality of addresses in response to a first number of most significant bits of a current pixel value including a first selection bit and a second number of most significant bits of a previous pixel value including a second selection bit; an output unit configured to determine correction parameters, which respectively correspond to the plurality of addresses, in response to the plurality of addresses, to select an index pattern from a plurality of index patterns in response to the first selection bit and the second selection bit, and to arrange the determined correction parameters into the selected index pattern to output arranged correction parameters; a ratio generator configured to calculate a distance ratio between the correction parameters in response to a first number of least significant bits of the current pixel value and a second number of least significant bits of the previous pixel value; and a bilinear interpolator configured to perform bilinear interpolation based on the correction parameters and the distance ratio output from the ratio generator to generate a correction value for the current pixel value, wherein the index pattern is a pattern that can be generated according to positions of the determined correction parameters in a look-up table including the plurality of indexes.