Patent ID: 6593609
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A semiconductor device comprising:a plurality of access transistors and memory capacitors connected to drains of said plurality of access transistors in a memory cell region; and a plurality of logic transistors in a logic region; said each logic transistor including: a first silicide film on a source and a drain; a gate electrode on a gate insulation film; a second suicide film on said gate electrode; a sidewall formed from a first film and proximate said gate electrode; and an encircling insulation film formed from a second film and encircling said sidewall; and said each access transistor including: a gate electrode on a gate insulation film; a third silicide film on said gate electrode; and a laminated insulation film on a source and a drain of said each access transistor; wherein said laminated insulation film is composed of a first layer and a second layer laminated on said first layer and a top surface; a top surface of said laminated insulation film is positioned at substantially the same height as a middle of a thickness of said third silicide film, said first layer is formed from said first film, which is also used to form said sidewall of said each logic transistor, said second layer is formed from said second film, which is also used to form said encircling insulation film.