Patent ID: 6150201
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method of forming a top gated thin film field effect transistor comprising:forming a thin film transistor layer over a substrate, the layer comprising first and second source/drain areas separated by an intervening channel region having a channel length;forming a conductive layer of material over the thin film transistor layer;removing conductive layer portions sufficient to define a pair of source/drain blocks over the thin film transistor layer, said blocks having inwardly facing sidewalls defining a spacing dimension therebetween, the channel length being less than the spacing dimension;forming a top gate over the substrate; andwherein the channel length is defined by a pair of spaced-apart channel region sidewalls, and wherein the removing of the conductive layer portions comprises forming one of the blocks' sidewalls to be generally aligned with one of the channel region sidewalls.