Patent ID: 6013552
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A method of manufacturing a split-gate flash memory cell comprising source and drain diffusion regions (6 and 9), a floating gate insulation film (2), a floating gate electrode (3), a control gate insulation film (4), and a control gate electrode (10), said method comprising:a first step of successively forming said floating gate insulation film (2) and said floating gate electrode (3) on a selected area of a semiconductor substrate (1);a second step of forming said control gate insulation film (4) on said floating gate electrode (3) and on a remaining area of said semiconductor substrate (1), said control gate insulation film (4) having a side wall part brought into contact with a side wall of said floating gate electrode (3);a third step of carrying out ion-implantation of a first dopant to form said source diffusion region (6) on a first part of said remaining area of the semiconductor substrate (1);a fourth step of forming a sidewall electrode (8) brought into contact with said sidewall part of the control gate insulation film (4);a fifth step of carrying out ion-implantation of a second dopant to form, on a second part of said remaining area of the semiconductor substrate (1), said drain diffusion region (9) self-aligned with respect to said sidewall electrode (8); anda sixth step of forming said control gate electrode (10) on said control gate insulation film (4) and on said sidewall electrode (8).