Patent ID: 8610470
Filing Date: 2013-12-17
Classification: H01L,H03K

Abstract:
1. A semiconductor integrated circuit, comprising: a first node coupled between a first potential node and a second potential node, the first potential node having a first potential and the second potential node having a second potential, the second potential being lower than the first potential; a first voltage-dividing circuit arranged between the first potential node and the first node; and a second voltage-dividing circuit arranged between the first node and the second potential node, the first voltage-dividing circuit comprising a first p-channel transistor and a second p-channel transistor, the first and second p-channel transistors being coupled in series between the first potential node and the first node and both having one end, another end, and a gate terminal, the one end of the first p-channel transistor being coupled to the first potential node, the another end of the first p-channel transistor being coupled to the one end of the second p-channel transistor, and the gate terminal of the first p-channel transistor being coupled to a second node, the another end of the second p-channel transistor being coupled to the first node and the gate terminal of the second p-channel transistor being applied with a first intermediate range potential having a potential between the first potential and the second potential, the second voltage-dividing circuit comprising a first n-channel transistor and a second n-channel transistor, the first and second n-channel transistors being coupled in series between the first node and the second potential node and both having one end, another end, and a gate terminal, the one end of the first n-channel transistor being coupled to the second potential node, the another end of the first n-channel transistor being coupled to the one end of the second n-channel transistor, and the gate terminal of the first n-channel transistor being coupled to the second node, the another end of the second n-channel transistor being coupled to the first node and the gate terminal of the second n-channel transistor being applied with the first intermediate range potential, wherein the first intermediate range potential is different from a potential of the first node.