Patent ID: 9223585
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A data processing device comprising: a first number of first processors that initialize the data processing device based on a first or a second boot program for initialization of first buses after power-on, the first number being one or more; the first buses, connected with the first processors respectively, that require initialization based on the first or the second boot program before use; a chip set that includes: a second number of first memories that store the first boot program respectively, the second number being one or more and being the first number or less; and a memory controller that reads out the first boot program stored in the first memories; the first number of second buses, arranged between the memory controller and the first processors to provide the first boot program read out by the memory controller to the first processors, that do not require initialization based on the first boot program before use, wherein the chip set further includes a boot control unit that performs at least one of: controlling activation timing of the first processors; controlling reboot timing of the first processors; and controlling access to the second buses, and the data processing device further comprising: a nonvolatile second memory that stores the second boot program for initialization of the first buses after power-on; and a third bus, arranged between the second memory and one of the first processors to provide the second boot program stored in the second memory to said first processor, that does not require initialization before use by said first processor based on the second boot program, wherein the boot control unit selects either one of the first boot program stored in the first memories or the second boot program stored in the second memory so that said first processor executes either one of the first boot program or the second boot program upon activation.