Patent ID: 6598112
Filing Date: 2003-07-22
Classification: G06F,G11C

Abstract:
A method for executing an integrated circuit (IC) test program, said IC test program comprising main program instructions including at least one subroutine calling instruction and at least one called subroutine, the method comprising the steps of:partitioning said at least one called subroutine into first and second subroutine portions, loading said main program instructions into a primary memory, said main program instructions including said at least one said calling instruction, loading said first portion at a location in said primary memory contiguous with said calling instruction, inserting a memory transfer access instruction after said first portion, loading a remainder of said main program instructions into said primary memory, fetching and executing instructions from said primary memory, executing said calling instruction from said primary memory, said calling instruction causing said second portion of said called subroutine to be loaded into a tertiary memory FIFO element from a secondary memory, executing said first portion from said primary memory, executing said memory transfer access instruction to initiate the steps of fetching and executing said second portion of said called subroutine from said tertiary memory FIFO element, executing a return instruction in said second portion of said called subroutine, and resuming fetching and executing said main program instructions from said primary memory.