Patent ID: 7271013
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate having active circuitry; a plurality of layers of interconnect over the substrate; a final layer of interconnect over the plurality of layers of interconnect having a plurality of final layer pads around a perimeter of the substrate and having a plurality of interconnect lines; a layer of passivation over the final layer of interconnect having a plurality openings, wherein each of the plurality of openings corresponds to a final layer pad of the plurality of final layer pads and each of the plurality of openings is over the final layer pad to which it corresponds; and a plurality of bond pads, wherein each bond pad of the plurality of bond pads corresponds to an opening of the plurality of openings, each bond pad is over the opening to which it corresponds, each bond pad has a first region and a second region, wherein the first region of each bond pad is closer to the perimeter of the substrate than the second region of each bond pad, and wherein first regions of adjacent bond pads alternate between probe regions and wire bond regions, and wherein the probe regions of each of the plurality of bond pads are formed entirely over the layer of passivation.