Patent ID: 6493275
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A semiconductor integrated circuit device integrating a plurality of MIS (Metal Insulator Semiconductor) transistors each having its source and drain provided in a respective region of a semiconductor substrate that is surrounded by a substrate region, and its gate provided on a region of the semiconductor substrate that is located between the source and drain, whereinthe plurality of MIS transistors include at least one of a P-channel modulation MIS transistor and an N-channel modulation MIS transistor, a modulation substrate bias Vb varying with a prescribed amplitude within such a range that causes no latch-up is applied to the P-channel modulation MIS transistor, and a modulation substrate bias Vbâ€² varying with a prescribed amplitude within such a range that causes no latch-up is applied to the N-channel modulation MIS transistor.