Patent ID: 7836258
Filing Date: 2010-11-16
Classification: G06F,G06T

Abstract:
1. A method of invalidating data in a memory cache, the method comprising: creating a first memory directory entry corresponding to a first portion of the memory cache and a second memory directory entry corresponding to a second portion of the memory cache, wherein the memory directory entries provide effective address to real address translation for the data in the memory cache; prior to the reception of a distributed time base signal, setting a first bit in the first memory directory entry to indicate the first memory directory entry will be invalid upon the reception of the distributed time base signal; generating the distributed time base signal; setting a second bit in the first and second memory directory entries in response to the distributed time base signal; receiving a request for memory address translation for the first portion of the memory cache; and determining the first memory directory entry is invalid by examining the first bit and the second bit in the first memory directory entry.