Patent ID: 6187651
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method of forming a trench isolation region, comprising the steps of:forming a trench in a semiconductor substrate;lining a sidewall of the trench with a first electrically insulating layer;forming a stress-relief layer on the first electrically insulating layer;filling the trench with a second electrically insulating layer;planarizing the second electrically insulating layer; thenetching the stress-relief layer to define a recess that extends below a surface of the semiconductor substrate and between the second electrically insulating layer and a portion of the first electrically insulating layer lining the sidewall of the trench;forming a third electrically insulating layer that extends on the planarized second electrically insulating layer and extends into the recess; andsimultaneously etching back the third electrically insulating layer and the planarized second electrically insulating layer to define an isolation region.