Patent ID: 7190155
Filing Date: 2007-03-13
Classification: G01R

Abstract:
1. A test apparatus for testing a device-under-test, comprising: a reference clock source for generating reference clock for controlling operations of said device-under-test; a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is equal to the frequency of said reference clock and having a phase difference from said reference clock corresponding to said phase adjusting signal; a timing comparator for obtaining a value of an output signal outputted from said device-under-test based on said regenerated clock; a first phase comparing section for outputting said phase adjusting signal that converges said phase difference into a reference phase difference set in advance to said clock regenerating circuit based on the comparison result of the phases of said output signal and said regenerated clock; and a storage section for sequentially storing said phase adjusting signals outputted from said first phase comparing section.