Patent ID: 7800916
Filing Date: 2010-09-21
Classification: H01L,H05K,Y10T

Abstract:
1. A circuitized substrate assembly comprising: a first circuitized substrate including at least one thin dielectric layer and at least one conductive layer, said conductive layer including a first plurality of conductive members; a first semiconductor device including a plurality of conductive sites thereon, selected ones of said conductive sites being soldered to corresponding ones of said first plurality of said conductive members of said conductive layer of said first circuitized substrate; a second circuitized substrate including at least one thin dielectric layer and at least one conductive layer, said at least one conductive layer of said second circuitized substrate including a second plurality of conductive members; a second semiconductor device including a plurality of conductive sites thereon, elected ones of said conductive sites of said second semiconductor device being electrically coupled to corresponding ones of said second plurality of said conductive members of said conductive layer of said second circuitized substrate; and at least one dielectric layer being positioned substantially between said first and second circuitized substrates, said first and second circuitized substrates being bonded together to form said circuitized substrate assembly, said first and second semiconductor chips being internally positioned within said assembly in a substantially stacked orientation; wherein each of said conductive members of said first and second plurality of conductive members is sculpted.