Patent ID: 6434053
Filing Date: 2002-08-13
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a channel forming region comprised of a first conductivity type semiconductor, source and drain regions comprised of a second conductivity type semiconductor sandwiching the channel forming region between them, a gate insulating film provided on said channel forming region, a gate electrode provided on said gate insulating film, and a charge storing means which is formed in said gate insulating film dispersed in the plane facing said channel forming region and in the direction of thickness and is injected with hot electrons at the time of operation from said source and drain regions, wherein a memory transistor comprises said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode has a gate length shorter than or equal to the gate length when a region retaining hot electrons from one of said source and drain regions is merged or partially merged in the gate insulating film with a region retraining hot electrons from the other of said source and drain regions when hot electrons are injected from both said source and drain regions.