Patent ID: 7496870
Filing Date: 2009-02-24
Classification: G06F

Abstract:
1. A method of selecting cells in an integrated circuit design suitable for use in logic restructuring of an original design, wherein the original design includes a set of parameters, the method comprising: (a) forming a restructuring set having restructuring cells including at least an initial cell, wherein the restructuring set is adapted to accept additional cells identified as restructuring cells; (b) forming a candidate set adapted to include candidate cells, wherein each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set, (c) removing a selected candidate cell from the candidate set; (d) for each restructuring cell connected to the selected candidate cell, identifying a corresponding cell pair parameter for a cell pair formed by that restructuring cell and the selected candidate cell; (e) if the cell pair parameter is included in the set of parameters, then placing the removed, selected candidate cell into the restructuring set as an identified restructuring cell and placing at least one cell that is connected to the removed, selected candidate cell into the candidate set; (f) repeating steps (c) through (e) for other candidate cells in the candidate set; and (g) returning a completed restructuring set.