Patent ID: 6791878
Filing Date: 2004-09-14
Classification: G11C

Abstract:
A word line decoder in a NAND type flash memory device, for decoding a word line select signal by which a given memory cell is selected, comprising:a row decoder for receiving an address of the given memory cell to produce a signal informing that the given memory cell is selected or not selected; control unit for outputting a positive voltage if the signal informing that the given memory cell was selected from the row decoder is received and for outputting a negative voltage if the signal informing the given memory cell was not selected is received; and a driving unit having NMOS transistors for outputting the negative voltage from sources of the NMOS transistors to drains of the NMOS transistors if the positive voltage outputted from the control unit is applied to gates of the NMOS transistors, and for prohibiting the negative voltage inputted to the sources of the NMOS transistors from being outputted to the drains of the NMOS transistors if the negative voltage outputted from the control unit is applied to the gates of the NMOS transistors, wherein the negative voltage inputted to the sources of the NMOS transistors is applied to a P well of the NMOS transistors.