Patent ID: 9104426
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A processor comprising: a plurality of registers to store data; an instruction decoder to decode a first instruction word that is to include a first plurality of at least three instructions, wherein the first instruction word is part of an instruction set architecture having instruction words with a variable instruction length; and at least three groups of execution units coupled with the instruction decoder and the plurality of registers, wherein each of the at least three groups of execution units is to correspond to a different instruction of the at least three instructions of the first instruction word, wherein each instruction of the at least three instructions of the first instruction word is only able to control an execution unit in the corresponding group of execution units, and wherein only one execution unit in each of the at least three groups of execution units is to be controlled by the different corresponding instructions of the at least three instructions of the first instruction word.