Patent ID: 8228704
Filing Date: 2012-07-24
Classification: G11C,H01L,H03L

Abstract:
1. A semiconductor chip package comprising at least two semiconductor chips having a stacked configuration, the semiconductor chips including at least one DLL path for a sharing of a DLL clock signal generated by any one of the semiconductor chip, wherein each of the semiconductor chips includes a DLL circuit and a switching circuit for enabling or disabling of the DLL circuit, only one DLL circuit provided on any one of the semiconductor chips is in an enable state, and a remainder of DLL circuits on other semiconductor chips are in a disable state, and wherein the DLL circuit provided in each of the semiconductor chips comprises: a main delay chain unit including a plurality of main delay cells, for delaying an external clock signal, and outputting a first clock signal; an interpolation unit for outputting a second clock signal obtained by interpolating the first clock signal; a switching unit for performing a switching of the DLL path and a switching for an enable or disable of the DLL circuit, and outputting the second clock signal or the DLL clock signal in response; a delay selection unit for selecting a delay compensation of the second clock signal or the DLL clock signal output from the switching unit, and generating a third clock signal; a replica path unit configured to have a same delay condition as an actual clock path, the replica path unit receiving the third clock signal, delaying it by a given time according to a delay condition, and outputting a fourth clock signal; and a phase detecting unit for comparing phases of the fourth clock signal and the external clock signal, outputting a detection signal corresponding to the comparison result, and controlling a delay amount of the first clock signal output from the main delay chain unit.