Patent ID: 9151800
Filing Date: 2015-10-06
Classification: G01R

Abstract:
1. A system for testing a chip comprising: a first plurality of scannable latches on a first scan channel, the first plurality of scannable latches configured to apply first input data to logic circuits on the chip and further configured to receive first output data from the to logic circuits on the chip; a second plurality of scannable latches on a second scan channel, the second plurality of scannable latches configured to apply second input data to the logic circuits on the chip and further configured to receive second output data from the logic circuits on the chip; a first XOR on the first scan channel, the first XOR on the first scan channel configured to hash output data from the first plurality of scannable latches; a first XOR on the second scan channel, the first XOR on the second scan channel configured to hash output data from the second plurality of scannable latches; a second XOR on the first scan channel, the second XOR on the first scan channel configured to hash output from the first XOR on the first scan channel; a rotator configured to receive output data from the second XOR on the first scan channel and further configured to create adjustment data for transmittal to the second scan channel; and a second XOR on the second channel, the second XOR on the second scan channel configured to hash the adjustment data and output data from the first XOR on the first scan channel.