Patent ID: 9083357
Filing Date: 2015-07-14
Classification: H03L,H04L

Abstract:
1. A frequency locking system for locking a clock frequency in a clock and data recovery (CDR) circuit without crystal oscillator, comprising: a first low-pass filter, a first swing detector, a second low-pass filter, a second swing detector, a comparator, a charge pump, a voltage-controlled oscillator, a code pattern conversion generator and a capacitor; wherein an input terminal of said first low-pass filter is inputted with reference data information; an output terminal of said first low-pass filter is connected to an input terminal of said first swing detector; an output terminal of said first swing detector is connected to a non-inverting input terminal of said comparator; an output terminal of said comparator is connected to an input terminal of said charge pump; an output terminal of said charge pump is connected to a first terminal of said capacitor; a second terminal of said capacitor is grounded; said first terminal of said capacitor is also connected to an input terminal of said voltage-controlled oscillator; an output terminal of said voltage-controlled oscillator is connected to an input terminal of said code pattern conversion generator; an output terminal of said code pattern conversion generator is connected to an input terminal of said second low-pass filter; an output terminal of said second low-pass filter is connected to an input terminal of said second swing detector; an output terminal of said second swing detector is connected to an inverting input terminal of said comparator; said first swing detector detects an amplitude of said reference data information which is filtered by said first low-pass filter to generate a first detection result, and then inputs said first detection result into said non-inverting input terminal of said comparator; said code pattern conversion generator converts a clock information which is generated by said voltage-controlled oscillator into a code pattern correspondently to said reference data information, and inputs said converted clock information into said second low-pass filter; said second swing detector detects an amplitude of said clock information which is filtered by said second low-pass filter to generate a second detection result, and inputs said second detection result into said inverting input terminal of said comparator; said comparator compares said amplitudes of said two inputted informations to generate a comparison result, and controls said charge pump to charge/discharge said capacitor according to said comparison result; and, said voltage-controlled oscillator adjusts a frequency of said clock information outputted thereby according to voltages of two ends of said capacitor.