Patent ID: 6987309
Filing Date: 2006-01-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a first conductivity type well area formed in a surface area of the semiconductor substrate; a plurality of element isolation areas formed in the well area; a second conductivity type semiconductor layer formed in a first area of the well area which is isolated by the element isolation areas, the second conductivity type semiconductor layer configuring a first electrode of a capacitor; a first conductivity type semiconductor layer formed in a second area of the well area which is isolated by the element isolation areas, the first conductivity type semiconductor layer configuring a second electrode of the capacitor; and a first conductivity type low resistance area having a resistive value lower than that of the well area, which is in contact with the element isolation areas, and is not in contact with a depletion layer of a junction portion between the second conductivity type semiconductor layer and the well area, and is not in contact with a depletion layer of a junction portion between the first conductivity type semiconductor layer and the well area, wherein the low resistance area is in contact with a base portion of the well area and connects said first and second areas.