Patent ID: 9213563
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A method for implementing a jump instruction, comprising: interpreting, by a processor, a first non-native instruction to generate a first instruction code after an initial scheduling of the first non-native instruction for execution; storing, by the processor, the first instruction code and an address of a target instruction code pointed to by the first instruction code, wherein the address corresponds to an address in a shadow memory; determining, by the processor, if a second instruction code is available at the shadow memory address of the target instruction code pointed to by the first instruction code; compiling, by the processor, during a subsequent scheduling of the first non-native instruction for execution, and without reinterpreting the first non-native instruction during the subsequent scheduling, at least the first instruction code and the second instruction code, both retrieved from the shadow memory, as a group to generate a native instruction path when it is determined that the second instruction code is available in the shadow memory; and defining a maximum number of target instruction codes for the first instruction code; and compiling no more than the maximum number of target instruction codes with the first instruction code to generate the native instruction path.