Patent ID: 8476706
Filing Date: 2013-07-02
Classification: H01L

Abstract:
1. A semiconductor structure comprising a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) located on a substrate, wherein said PFET comprises a first silicon portion and a layer stack of a first silicon carbon alloy layer and a silicon germanium alloy layer, a combination of said first silicon portion and said layer stack includes a first source region, a first drain region, and a first body region, and said layer stack is in contact with a first gate dielectric that is in contact with a first gate electrode, and wherein said NFET comprises a second silicon portion and a second silicon carbon alloy layer, a combination of said second silicon portion and said second silicon carbon alloy layer includes a second source region, a second drain region, and a second body region, and said second silicon carbon alloy layer is in contact with a second gate dielectric that is in contact with a second gate electrode, and wherein said first gate dielectric and said second gate dielectric have a same composition and a same thickness.