Patent ID: 6750080
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A process for manufacturing a semiconductor device, comprising the steps of:preparing a first semiconductor chip and a second semiconductor chip, each of which is formed in a square shape when viewed in plan, and each of which is formed with a plurality of electrodes on a side of a first latus of a front surface of front and rear surfaces thereof and along the first latus; bonding and fixing the first and second semiconductor chips to each other in a state where the rear surfaces of the respective semiconductor chips are faced to each other with no supporting leads therebetween so that the first latus of said first semiconductor chip and the first latus of said second semiconductor chip lie on opposite sides, such that said bonded and fixed first and second semiconductor chips are entirely supported by supporting leads bonded and fixed onto the from surface of the first semiconductor chip, and where positions of said respective semiconductor chips are staggered relatively to each other in a direction orthogonal to a direction of arraying the electrodes; and electrically connecting said electrodes of said first semiconductor chip and first leads arranged outside said first latus of said first semiconductor chip, by pieces of conductive wire, so that said pieces of conductive wire have a peak height that is greater than a peak thickness of the supporting leads bonded and fixed onto the front surface of the first semiconductor chip, and electrically connecting said electrodes of said second semiconductor chip and second leads arranged outside said first latus of said second semiconductor chip, by pieces of conductive wire, wherein said first and second leads, respectively electrically connected to said electrodes of said first and second semiconductor chips in said electrically connecting step, are entirely disposed outside of the first latus of one of said first and second semiconductor chips and a second latus of the other of said first and second semiconductor chips, so that none of said first and second leads is on said front surface of either of said first and second semiconductor chips, and wherein said first and second semiconductor chips are not mirror inversion correspondents of each other.