Patent ID: 7746708
Filing Date: 2010-06-29
Classification: G11C

Abstract:
1. A system on a chip comprising: a plurality of nonvolatile latch circuits to hold a logic state of latch data, wherein each of the plurality of nonvolatile latch circuits comprise: a nonvolatile latch unit adapted and configured to amplify and store a voltage level of an input signal in a nonvolatile ferroelectric capacitor in response to storage control signals while a clock is activated; a latch transition detecting unit adapted and configured to detect transition of an output signal from the nonvolatile latch unit to output a latch transition detecting signal when the output signal from the nonvolatile latch unit transitions; and a latch control unit adapted and configured to store data in the nonvolatile latch unit in response to the latch transition detecting signal and a power-on reset signal and output the storage control signals for restoring the latch data.