Patent ID: 6434076
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A semiconductor static random access memory (SRAM) system including one or more memory arrays, said system comprising;a power management device associated with each memory array, each power management device comprising a first switching device for connecting an external Power source to a memory array during normal SRAM device operation and responsive to a low power mode signal for disconnecting said external power source from said memory array during a low power mode of operation; said power management device further comprising a second switching device for connecting said external power source to a local power source associated with each respective memory array, and, a refresh control device for independently controlling each said second switch device for selectively connecting and disconnecting said external power source to said local power source associated with a respective memory array for refreshing said associated local power source during said low power mode of operation, whereby power consumption in said SRAM device is reduced during said low power mode.