Patent ID: 6833747
Filing Date: 2004-12-21
Classification: H03K

Abstract:
A level translator circuit for use between a lower voltage potential circuit and a higher voltage potential circuit; the translator circuit comprising:first transistor coupled to the lower voltage potential circuit; a bootstrap mechanism coupled to the first transistor; a second transistor coupled to the first transistor, a higher voltage potential and the higher voltage potential circuit; a third transistor coupled to the higher voltage potential circuit, the higher voltage potential and the second transistor; and a fourth transistor coupled to the higher voltage potential circuit, and to a ground potential, wherein the bootstrap mechanism allows for the dynamic modulation of the first transistor to maximize translation speed and minimize power consumption; wherein the bootstrap mechanism comprises: a fifth transistor coupled to a lower voltage potential and the lower voltage potential circuit; and a capacitative mechanism coupled to the lower voltage potential circuit and to the gate of the first transistor; and wherein the level translator circuit further comprises: a sixth transistor coupled to the bootstrap mechanism, and a transistor stack coupled to the bootstrap mechanism, the higher voltage potential circuit, and the lower voltage potential circuit, and the ground potential.