Patent ID: 7977180
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method for fabricating a MOS device, the method comprising the steps of: providing a silicon substrate having a P-well region; depositing a polycrystalline silicon gate electrode layer overlying the P-well region of the silicon substrate; implanting P-type dopant ions into the polycrystalline silicon gate electrode layer to form a P-type implanted region; forming a first polycrystalline silicon gate electrode overlying the P-well region of the silicon substrate; etching recesses into the P-well region of the silicon substrate using the first polycrystalline silicon gate electrode as an etch mask, wherein the step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide; and forming a tensile stress-inducing material within the recesses.