Patent ID: 6590424
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A latchless dynamic asynchronous digital pipeline circuit for processing data in an environment comprising:a first processing stage comprising: a first function block enabled to enter a first precharge phase and a first evaluate phase in response to a first precharge control signal, and having a first data input for receiving the data for processing from the environment and a first data output for receiving the data processed by the first function block upon completion of the first evaluate phase; a first completion generator responsive to the first precharge control signal and a first request signal from the environment and which asserts a first environment precharge control signal; a first delay element which applies a delay to the environment precharge control signal to produce a second request signal; a second processing stage comprising: a second function block enabled to enter a second precharge phase and a second evaluate phase in response to a second precharge control signal, and having a second data input for receiving the data for processing from the first data output and a second data output for receiving the data processed by the second function block upon completion of the second evaluate phase; a second completion generator responsive to the second precharge control signal and the second request signal and which asserts the first precharge control signal; a second delay element which applies a delay to the first precharge control signal to produce a third request signal.