Patent ID: 7428249
Filing Date: 2008-09-23
Classification: H04J

Abstract:
1. A bit Interleaved Parity-8 (BIP-8) computation system comprising: a frame error check value computation block receiving first frame data from a frame processor, for computing new first frame BIP-8 values; storage means receiving second frame data from the frame processor for storing old first frame BIP-8 values, wherein the old first frame BIP-8 value is transmitted within the second frame; and a comparator circuit receiving data from the BIP-8 computation block, from the storage means and from a critical time signaling circuit, for comparing the new first frame BIP-8 values with the old first frame BIP-8 values, wherein the critical time signalling circuit sends an enabling signal to the comparator, for enabling the comparison operation according to a predetermined comparison timing schedule.