Patent ID: 8782496
Filing Date: 2014-07-15
Classification: G06F,G11C,H03M

Abstract:
1. A memory controller comprising: a first memory section configured to store threshold decision information of data read from a NAND type flash memory section when frame-unit data coded using a low density parity code is decoded through partial parallel processing based on a check matrix comprising a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted; an LLR conversion section configured to convert the threshold decision information to a logarithmic likelihood ratio; a second memory section configured to store probability information calculated during iteration processing that repeatedly performs column processing and row processing based on the logarithmic likelihood ratio in an iteration unit equal to or smaller than a size of the block; and a control section configured to transfer the probability information stored in the second memory section to the first memory section every time the iteration processing in the iteration unit is completed.