Patent ID: 6285403
Filing Date: 2001-09-04
Classification: H04L,H04N

Abstract:
A data slice circuit to perform a data slice operation on an input video signal, comprising:a top peak detector to detect a top peak of an input video signal to generate a top peak detection signal;a bottom peak detector to detect a bottom peak of said input video signal to generate a bottom peak detection signal;a composite synchronous signal separation circuit to separate a composite synchronous signal from said input video signal;a clock run-in window circuit to generate a first control signal for a clock run-in interval based upon said composite synchronous signal;a sampling/holding circuit to sample an intermediate value between said top peak detection signal and said bottom peak detection signal in response to said first control signal of a first state, and holding the sampled intermediate value to generate a reference voltage in response to said first control signal of a second state;a control signal generator to receive said composite synchronous signal and, in response, generate a second control signal indicating a line on which data of the input video signal is being carried; anda comparator circuit to compare said input video signal with said reference signal in response to said second control signal;whereby the data slice circuit performs the data slice operation at the line on which the data is carried.