Patent ID: 6262924
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell part including a plurality of main cell arrays and a plurality of parity cell arrays;a row decoder, including a plurality of row decoder circuits, decoding a row address of an input address and outputting from said memory cell part data and parity data specified by the row address;a column decoder, including a plurality of column decoder circuits, decoding a column address of the input address and outputting data and parity data specified by the column address out of the data and the parity data output from said memory cell part;a defective output storage circuit storing an address region including a defective main cell and outputting data indicating a defective bit; anda redundant circuit correcting and outputting the output data of the main cell array including the defect out of the data output from said column decoder, based on the parity data and the output data of said defective output storage circuit,each word line driven by the row decoder circuit not traversing a plurality of main cell arrays.