Patent ID: 6310521
Filing Date: 2001-10-30
Classification: H03L,H04L,Y10S

Abstract:
An apparatus comprising:a first circuit configured to generate one or more first control signals having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said first data rate;a second circuit configured to generate one or more second control signals having said first data rate in response to (i) said input signal and (ii) said clock signal; anda first logic circuit configured to generate said clock signal in response to (i) said one or more first control signals, (ii) said one or more second control signals and (iii) a third control signal, wherein one of said first control signals and said second control signals comprises a pump-up signal and another one of said first control signals and said second control signals comprises a pump-down signal.