Patent ID: 6114721
Filing Date: 2000-09-05
Classification: H01L,Y10S

Abstract:
A dynamic random access memory device, comprising:a plurality of memory cells;a plurality of bit lines disposed in a bit line layer;a plurality of word lines respectively associated with the plurality of memory cells and disposed in a word line layer; andeach memory cell being located along a respectively associated said bit line and comprising:a storage capacitor,a transfer transistor which electrically connects the storage capacitor to the respectively associated bit line in response to a select signal applied thereto via the respectively associated word line,the storage capacitor comprising a storage electrode disposed in a storage electrode layer, the storage electrode layer being electrically conductive and thicker than each of the respective thicknesses of the word line and bit line layers, a dielectric film on the storage electrode, and an opposed electrode on the dielectric film, the bit line layer being lower than the storage electrode layer,said transfer transistor comprising first and second impurity diffused regions, the second impurity diffused region being electrically connected to said storage electrode,said respectively associated bit line having a portion making an electrical connection with the first impurity diffused region at a connecting position thereon, andsaid respectively associated word line crossing said respectively associated bit line and extending between the first and second impurity diffused regions;an associated bit line of one transfer transistor being paired with and spaced from an adjacent bit line respectively associated with an adjacent transfer transistor, the paired bit lines having corresponding portions making respective electrical connections with the corresponding first impurity diffused regions of the one and the adjacent transfer transistors at respective connecting positions thereon;the respective connecting positions of the one and the adjacent transfer transistors being spaced apart in a direction in which the paired bit lines commonly extend; andthe one and the adjacent transfer transistors being located so that two word lines extend between the respective connecting positions thereof.