Patent ID: 6281134
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method for combining logic circuit and capacitor circuit, comprising:providing a semiconductor wafer, wherein said semiconductor wafer has a first dielectric layer and a first contact formed in said semiconductor wafer;forming a first metal layer over said first contact of a logic circuit area, and over a portion of a capacitor circuit area;forming a second dielectric layer onto on said first metal layer and said first dielectric layer;forming a second metal layer over a portion of said first metal layer of the capacitor circuit area and abutting on a portion of said second dielectric layer;forming a third dielectric layer on said second metal layer and said second dielectric layer;forming a fourth dielectric on said third dielectric layer;forming a fifth dielectric layer on said fourth dielectric layer;sequentially etching said fifth dielectric layer, said fourth dielectric layer, said third dielectric layer and said second dielectric layer, whereby forming a second contact which is located on a portion of said first metal layer of the capacitor area, a third contact located on said second metal layer, and a fourth contact which is located on said first metal layer over said first contact;etching said fifth dielectric layer, whereby said second contact, said third contact, said fourth contact inside said fifth dielectric layer is bigger than said second contact, said third contact and said fourth contact inside said third dielectric layer;forming a barrier layer on side walls and bottom of said second contact, said third contact and said fourth contact;forming an inter-metal line into said second contact, said third contact and said fourth contact;planazing said inter-metal line; andforming outer connection line, whereby combining said logic circuit and said capacitor circuit.