Patent ID: 6403417
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method for simultaneously fabricating a landing via and a strip contact of an embedded memory, the method comprising:providing a semiconductor wafer with both a memory array region and a periphery circuit region defined on the surface of the silicon substrate of the semiconductor wafer; forming a first dielectric layer, an undoped polysilicon layer, and a second dielectric layer, respectively, on the surface of the semiconductor wafer; implanting the undoped polysilicon layer in the memory array region so as to change the undoped polysilicon layer above the memory array region to a doped polysilicon layer; removing the second dielectric layer in the memory array region and etching the doped polysilicon layer to a predetermined depth; forming a silicide layer, a protection layer, and a first photoresist layer, respectively, on the surface of the semiconductor wafer; defining a pattern of a plurality of gates in the first photoresist layer in the memory array region, using the pattern of the first photoresist layer as a hard mask to etch the protection layer, the silicide layer, and the doped polysilicon layer located in the memory array region down to the surface of the first dielectric layer, as well as in-situ etching of the protection layer and the silicide layer located in the periphery circuit region down to the surface of the second dielectric layer; forming a lightly doped drain (LDD) adjacent to each gate in the memory array region; removing the first photoresist layer and the second dielectric layer in the periphery circuit region; forming a second photoresist layer on the surface of the semiconductor wafer; defining a pattern of a plurality of gates in the second photoresist layer in the periphery circuit region; using the pattern of the second photoresist layer as a hard mask to etch the undoped polysilicon layer in the periphery circuit region down to the surface of the first dielectric layer so as to form each gate in the periphery circuit region; forming a lightly doped drain (LDD) adjacent to each gate in the periphery circuit region; removing the second photoresist layer; forming a silicon nitride on the surface of the semiconductor and covering each surface of the gate; removing portions of silicon nitride in the periphery circuit region, to form a spacer on either side of the gate in the periphery circuit region; forming a third dielectric layer and a third photoresist layer on the surface of semiconductor wafer, respectively; defining a pattern of the landing via and the strip contact in the third photoresist layer; using the pattern of the third photoresist layer as a hard mask to etch the third dielectric layer, to form a landing via hole in the third dielectric layer in the memory array region, and in-situ to form a strip contact hole in the third dielectric layer in the periphery circuit region; and filling each landing via hole and strip contact hole with a conductive layer, so as to form in-situ each landing via and strip contact.