Patent ID: 8866707
Filing Date: 2014-10-21
Classification: G09G

Abstract:
1. A display device having a plurality of display elements comprising: a plurality of pixel electrodes over a substrate; a plurality of pixel driving elements including a first pixel driving element, each of the pixel driving elements having a first transistor, a second transistor, a third transistor, a first inverter and a second inverter; a first line electrically connected to a gate electrode of the first transistor and a gate electrode of the third transistor in the first pixel driving element; a second line electrically connected to one of a source electrode and a drain electrode of the first transistor in the first pixel driving element; a third line parallel to the first line; and a fourth line connected to the first inverter and the second inverter in the first pixel driving element, wherein one of a source electrode and a drain electrode of the third transistor in the first pixel driving element is electrically connected to an output terminal of the second inverter in the first pixel driving element, wherein the output terminal of the second inverter in the first pixel driving element is electrically connected to a gate electrode of the second transistor in the first pixel driving element, wherein the other of the source electrode and the drain electrode of the third transistor in the first pixel driving element is electrically connected to an input terminal of the first inverter in the first pixel driving element, wherein a connection between the output terminal of the second inverter in the first pixel driving element and the input terminal of the first inverter in the first pixel driving element is configured to be controlled by the third transistor in the first pixel driving element, wherein an output terminal of the first inverter in the first pixel driving element is electrically connected to an input terminal of the second inverter in the first pixel driving element, wherein the other of the source electrode and the drain electrode of the first transistor in the first pixel driving element is directly connected to the input terminal of the first inverter in the first pixel driving element, wherein one of a source electrode and a drain electrode of the second transistor in the first pixel driving element is electrically connected to one of the pixel electrodes, wherein first signals having two levels are alternately applied to the third line, wherein the potential of the one of the pixel electrodes is controlled by the first signals and controlled by an output signal of the second inverter in the first pixel driving element, wherein each of the plurality of pixel driving elements further includes a fourth transistor and a fifth transistor, wherein the other of the source electrode and the drain electrode of the second transistor in the first pixel driving element is electrically connected to the fourth line, wherein one of a source electrode and a drain electrode of the fourth transistor in the first pixel driving element is electrically connected to the output terminal of the second inverter in the first pixel driving element, wherein a gate electrode of the fourth transistor in the first pixel driving element is electrically connected to the third line, wherein one of a source electrode and a drain electrode of the fifth transistor in the first pixel driving element is electrically connected to the fourth line, wherein a gate electrode of the fifth transistor in the first pixel driving element is electrically connected to the third line, wherein the other of the source electrode and the drain electrode of the fourth transistor in the first pixel driving element is electrically connected to the gate electrode of the second transistor in the first pixel driving element, and wherein the other of the source electrode and the drain electrode of the fifth transistor in the first pixel driving element is electrically connected to the gate electrode of the second transistor in the first pixel driving element.