Patent ID: 7705372
Filing Date: 2010-04-27
Classification: H01L

Abstract:
1. A memory device comprising: a substrate; a first word line structure on the substrate, the first word line structure extending in a first direction; a bit line over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction; and a second word line structure over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction, wherein the bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.