Patent ID: 6800511
Filing Date: 2004-10-05
Classification: B82Y,H01L,Y10S

Abstract:
A method of fabricating a semiconductor device with negative differential conductance or transconductance, comprising:a first step of etching a single crystal silicon layer of an SOI substrate consisting sequentially of a silicon support, a buried oxide film and the single crystal silicon layer so as to form source and drain regions which are spaced apart from each other and a channel region which is connected with the source and drain regions and has a fine line width; a second step of implanting impurity ions into the source, channel, and drain regions with their density being higher than the effective density of states at which electrons or holes can exist so that the channel is doped with the impurity ions; a third step of forming a first insulation film on the source, channel and drain regions and the buried oxide film, and etching the first insulation film so as to form sidewall spacers on side surfaces of the source, channel and drain regions and then forming a second insulation film on the exposed silicon surface including the source, channel and drain regions so as to form a gate insulation film on the channel region; a fourth step of depositing a gate material on the entire surface including the second insulation film and forming a gate having a fine line width in a direction normal to the channel region by etching the deposited gate material; and a fifth step of implanting impurity ions, having opposite polarity to that of the impurity ions implanted in the second step, into the source and drain regions.