Patent ID: 6188211
Filing Date: 2001-02-13
Classification: G05F

Abstract:
A voltage regulator circuit, comprising:an error amplifier, having a first input receiving a reference voltage and having a second input, for generating a voltage at an output responsive to a difference in the voltages at its first and second inputs;a source follower transistor having a gate coupled to the output of the error amplifier, having a drain connected to an input voltage, and having a source;a current source, coupled between the source of the source follower transistor and a reference bias voltage;an output leg, comprising an output MOS transistor having a source-drain path coupled between the input voltage and an output node, and having a gate coupled to the source of the source follower transistor;a mirror leg, comprising a mirror MOS transistor having a source-drain path coupled on one side to the input voltage, and having a gate coupled to the source of the source follower transistor;a negative feedback circuit coupled to the output node and to the second input of the error amplifier, for providing feedback to the error amplifier based upon the voltage at the output node;a first positive feedback transistor having a conduction path connected in parallel with the current source, having a control electrode coupled to the mirror leg;a delay network, coupled to the control electrode of the first positive feedback transistor, for delaying the response of the control electrode of the first positive feedback transistor; anda second positive feedback transistor, having a conduction path connected in parallel with the current source, and having a control electrode coupled to the mirror leg, the second positive feedback transistor having a faster response than the first positive feedback transistor.