Patent ID: 7783859
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A method for managing memory of a processing system comprising at least one processor, the method comprising: detecting, through the use of the at least one processor, a change in a page table including a plurality of page table entries, where each of the plurality of page table entries includes information for translating a virtual address to a corresponding physical address, memory page size for a corresponding virtual address page, and access permission information for the corresponding virtual address page; responding to the detection by identifying contiguous page table entries having substantially the same access permission information; analyzing, through the use of the at least one processor, the identified contiguous page table entries to determine whether a change of the memory page size for any of the identified contiguous page table entries is warranted; updating the memory page size information for at least one of the identified contiguous page table entries with new memory page size information if the analysis of the identified contiguous page table entries determines that a change of the memory page size of any of the identified contiguous page table entries is warranted, where the new memory page size information corresponds to a largest memory page size to which any of the identified contiguous page table entries may be mapped; and updating, through the use of the at least one processor, one or more entries of the translation lookaside buffer corresponding to at least one of the identified contiguous page table entries, if any, with the new memory page size information.