Patent ID: 7565589
Filing Date: 2009-07-21
Classification: G01R

Abstract:
1. A semiconductor integrated circuit, comprising: a first external terminal which inputs a test signal; a second external terminal which inputs a clock signal; a self-test circuit which conducts a self-test based on the clock signal which is input through the second external terminal; a third external terminal which outputs, to the outside, a test judgment signal which is output from the self-test circuit; an external output control circuit which controls output of the test judgment signal from the third external terminal on the basis of the test signal which is input through the first external terminal and a test completion signal which is output from the self-test circuit; and a clock signal input control circuit which controls input, to the self-test circuit, of the clock signal which is input through the second external terminal, on the basis of the test judgment signal and the test completion signal.