Patent ID: 8601422
Filing Date: 2013-12-03
Classification: G06F

Abstract:
1. A computer implemented method for creating a layout of an electrical design, comprising: receiving design information for a schematic of the electrical design for simulation; generating one or more routing components, wherein the routing components define physical routing topology and physical routing constraints for the schematic, and wherein the physical routing topology and physical routing constraints are based at least in part upon an order of pin connections in the schematic; generating, using a processor, layout routing topology information and layout routing constraint information from the physical routing topology and physical routing constraints defined by the routing components, wherein the act of generating comprises generating layout routing constraints to be used in implementing a physical layout in conformance with the constraints; generating the physical layout using the layout routing topology information and layout routing constraint information, such that the layout routing topology information and layout routing constraint information ensure that the routing topology of the physical layout is visually in-sync with the order of pin connections of the schematic; and displaying the layout routing topology information and layout routing constraint information on a display device or storing the layout routing topology information and layout routing constraint information in a configured data structure on a non-transitory computer readable medium.