Patent ID: 7517767
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method of forming a conductive stud contacting a semiconductor device having a gate region, the method comprising: forming a protective layer covering said semiconductor device and at least substantially not covering sidewalls of said gate region of said semiconductor device; forming one or more spacers adjacent to said gate region of said semiconductor device, said spacers covering a first portion of said protective layer; removing a second portion of said protective layer not being covered by said spacers to expose source/drain areas of said semiconductor device; forming source/drain regions at said exposed source/drain areas; creating said protected area self-aligned to and covered by said first portion of said protective layer; removing said spacers covering said first portion of said protective layer; siliciding exposed areas of said source/drain regions to form said contact area of said semiconductor device, said contact area being a silicided contact area, and siliciding a top and said sidewalls of said gate region; selectively etching an opening down through said protective layer reaching a contact area of said semiconductor device, said opening being away from a protected area of said semiconductor device, and filling said opening with a conductive material to form said conductive stud.