Patent ID: 8136065
Filing Date: 2012-03-13
Classification: G06F

Abstract:
1. An integrated prototyping system (IPS) for a user to verify and validate an electronic system design (ESD) with design data provided as a plurality of hierarchical design elements HDEs each having its corresponding test bench and said HDEs further interacting with one another according to a pre-defined functional validation specification, said IPS comprising: a) a reprogrammable logic device (RPLD) having: b) an electronic design automation (EDA) simulator for reading the design data, simulating and then verifying, while receiving and outputting corresponding streams of exchanging vectors, selected members of said HDEs in conjunction with their test benches, said EDA simulator further comprising a simulator interface for controlling said EDA simulator's execution; and c) an IPS controller bridging the RPLD and the EDA simulator respectively through the RPLD-interface and the simulator interface, said IPS controller further comprising an IPS executive for progressively verifying and validating the design data by: