Patent ID: 6833327
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising:forming an electrically conductive film comprising a single layer or a plurality of layers over a semiconductor film; forming a hard mask layer over said electrically conductive film; forming a resist mask over said hard mask layer; etching said hard mask layer using said resist mask and forming a hard mask pattern whose edge is located inside of said resist mask; etching said electrically conductive film using said resist mask to form an electrically conductive film in a first shape; etching said electrically conductive film in said first shape using said hard mask pattern to form a gate electrode having an exposed portion is thinner than a portion covered by said hard mask pattern; and forming a channel formation region, first impurity regions sandwiching said channel formation region, and a second impurity region whose impurity concentration is lower than said first impurity region, which has been provided between said channel formation region and one of said first impurity regions, wherein said exposed portion of said gate electrode overlaps with said second impurity region.