Patent ID: 7193894
Filing Date: 2007-03-20
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus comprising: a control circuit; a plurality of terminals including a clock terminal, a command terminal and other terminal; a clock generator; a data buffer; a command buffer; and a plurality of nonvolatile memory cells, wherein said clock terminal receives a clock signal, wherein said clock generator is controlled by said control circuit for generating a second clock signal, wherein said command terminal couples to said command buffer and receives commands which comprise a read command and a program command, wherein said data buffer is used for receiving data from outside and outputting data to outside, wherein said control circuit reads out operation steps from a program memory for controlling an operation of said received command by executing said operation steps. wherein in an operation in response to said read command, said control circuit controls, based on operation steps corresponding to said read command, reading data from ones of said nonvolatile memory cells, stores read data to said data buffer, and outputting said read data stored in said data buffer via said other terminal except said command terminal in response to said clock signal, wherein in an operation in response to said program command received from said command terminal, said control circuit controls, based on operation steps corresponding to said program command, receiving data via said other terminal except said command terminal in response to clock signal, stores received data to said data buffer and writing said received data to ones of said nonvolatile memory cells, and wherein said data writing to ones of said nonvolatile memory cells is performed using said second clock signal.