Patent ID: 6740933
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A semiconductor device, comprising:a trench region disposed at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate, the trench region defining an active region; and an isolation structure filling an inside of the trench region, wherein the trench region comprises a deep trench region and a shallow trench region, the deep trench region existing where the upper silicon layer is removed to expose the buried insulating layer, the shallow trench region existing at an outside of the deep trench region, wherein the isolation structure includes a trench oxide layer, a trench liner, and an insulating layer pattern, the trench oxide layer and the trench liner sequentially covering a bottom and a sidewall of the shallow trench region, the insulating layer pattern filling the inside of the trench region covered with the trench oxide layer and the trench liner.