Patent ID: 8178973
Filing Date: 2012-05-15
Classification: H01L,Y10T

Abstract:
1. A thin film transistor substrate comprising: a plurality of gate lines formed on a substrate, and a plurality of data lines formed perpendicular to the gate lines between the gate lines and a gate insulating film to define pixel regions; a plurality of thin film transistors formed at regions where the gate lines and the data lines cross respectively, and a plurality of pixel electrodes formed at the pixel regions connected to the thin film transistors respectively, wherein one of the gate lines and the data lines is constructed of a copper wire; wherein another one of the gate lines and the data lines is not constructed of the copper wire; wherein the copper wire includes a barrier layer formed on an underlying structure and a copper conductive layer on the barrier layer, wherein the barrier layer includes at least one of a Cu wherein x and y are positive numerals; wherein the barrier layer is comprised of a first barrier layer and a second barrier layer; wherein the first barrier layer is formed between the underlying structure and the second barrier layer; wherein the second barrier layer is formed between the first barrier layer and the copper conductive layer; wherein the first barrier layer is a CuO wherein the second barrier layer is a Cu wherein a thickness of the first barrier layer is between about 50 to about 1000 Å; wherein the one of the gate lines and the data lines constructed of the copper wire has no overlying separate capping layer; wherein the other one of the gate lines and the data lines not constructed of the copper wire has an overlying separate capping layer.