Patent ID: 6022783
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A semiconductor processing method of forming an NMOS field effect transistor comprising the following steps:forming a patterned gate over a semiconductor substrate;after forming the gate, forming a mesa of semiconductive material beneath the patterned gate, the substrate defining a semiconductive substrate floor and the mesa comprising opposing, substantially vertical wall sections rising upwardly from the floor; andforming a pair of opposing LDD regions within the mesa wall sections and substrate floor, the respective LDD regions having a first portion running along one of the mesa wall sections and a second portion running along the semiconductor substrate floor, the first and second portions of the respective LDD regions being interconnected to form respective elongated and angled LDD regions extending from the mesa into the bulk semiconductor substrate; the step of forming the pair of opposing LDD regions comprising:depositing a layer of phosphosilicate glass over the mesa wall sections and substrate floor, the layer of phosphosilicate glass lying conformally over the mesa wall sections and substrate floor; andsubjecting the substrate to conditions effective to out-diffuse phosphorus from the phosphosilicate glass layer into the mesa wall sections and the substrate floor.