Patent ID: 6776399
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A power a miconductor package, comprisinga substrate having an insulating body, and upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges, the edges of the substrate defining the boundaries of the package; a power MOSFET semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which source and gate metalized surfaces are disposed and a bottom surface defining a drain; at least one drain conductive pad disposed directly on the substrate; a least one source conductive pad disposed directly on the upper surface only at the second side edge of the substrate; at least one gate pad disposed directly on the upper surface at the second side edge; a plurality of wire bonds extending from the source metalized surface to the source conductive pad, at least one wire bond extending from the gate metalized surface to the gate conductive pad; a plurality of spaced conductors disposed on the lower surface of the substrate; and a plurality of vias, each via extending between a conductive pad on the upper surface; to a respective conductor on the lower surface, wherein each conductive pad is electrically connected to at least one conductor through a respective via.