Patent ID: 7906396
Filing Date: 2011-03-15
Classification: H01L

Abstract:
1. A method of fabricating a flash memory, comprising: providing a substrate comprising a cell region and a periphery region, wherein a plurality of isolation structures is formed on the substrate, and a first dielectric layer and a floating gate are sequentially formed on the substrate between the isolation structures; forming a mask layer on the substrate, the mask layer covering the isolation structures in the periphery region and the isolation structure in the cell region and adjacent to the periphery region; removing a portion of the isolation structures in the cell region by using the mask layer as a mask, so that a first height difference is present between surfaces of the isolation structures in the periphery region and a surface of the first dielectric layer, the first height difference is present between a surface of the isolation structure in the cell region and adjacent to the periphery region and the surface of the first dielectric layer, and a second height difference is present between surfaces of the other isolation structures in the cell region and the surface of the first dielectric layer, wherein the first height difference is greater than the second height difference and the surfaces of the isolation structures are higher than the surface of the first dielectric layer; removing the mask layer; forming an inter-gate dielectric layer on the substrate; removing the inter-gate dielectric layer and the floating gates in the periphery region; and forming a conductive layer on the substrate.