Patent ID: 8927407
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method, comprising: forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, each of said gate electrodes comprising a gate cap layer positioned above said sacrificial gate electrode; performing at least one etching process to define a self-aligned contact opening between said plurality of spaced-apart sacrificial gate electrodes; removing said gate cap layers to thereby expose an upper surface of each of said sacrificial gate electrodes; after removing said gate cap layers, and while said upper surface of each of said sacrificial gate electrodes is exposed, depositing at least one layer of conductive material on said exposed upper surfaces of said sacrificial gate electrode structures and in said self-aligned contact opening; and removing portions of said at least one layer of conductive material that are positioned outside of said self-aligned contact opening and above said upper surface of each of said sacrificial gate electrodes to thereby define at least a portion of a self-aligned contact positioned in said self-aligned contact opening.