Patent ID: 6341241
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A defect analysis method of a device which includes an integrated circuit formed on each of a plurality of chips on a wafer through a plurality of processes, said defect analysis method comprising the steps of:(a) after each of at least one process out of said plurality of processes, detecting a new defect due to said at least one process and occurring in a new area of said wafer other than an area of a defect occurring at a previous process and its vicinity; (b) after said plurality of processes are completed, making one of defective and non-defective judgment on said integrated circuit on each of said plurality of chips; (c) judging a presence or absence of said new defect satisfying a predetermined identifying condition in each of said plurality of chips, for each of said at least one process; (d) classifying said plurality of chips into four groups including non-defective chip with no said new defect, defective chip with no said new defect, non-defective chip with said new defect an defective chip with said new defect on a basis of a combination of the judgment of said step (b) and the judgment of said step (c), for each of said at least one process; and (e) calculating a number of new defective chips considered to be caused only by said new defect of said at least one process, on basis of the classification of said step (d).