Patent ID: 6611020
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A non-volatile memory cell structure on a silicon substrate having an existing topography, comprising;a gate oxide region layer on and conforming to the existing topography of the substrate; an isolation layer formed on sidewall spacers surrounding the gate oxide region layer, the isolation layer having a top surface, wherein the isolation layer further includes a masking layer of silicon nitride which serves as an etch stop; an opening extending from the top surface of the isolation layer to the gate oxide region and defined by walls interior to the isolation layer; a conductive bottom plate layer on and conforming to the top surface of the isolation layer, the interior walls of the isolation layer, and the gate oxide region; a dielectric layer on and conforming to the conductive bottom plate layer; and a conductive top plate layer on and conforming to the dielectric layer.