Patent ID: 6820109
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A computing system comprising:a plurality of full adders, wherein each of the plurality of full adders comprising three inputs for receiving a bit-wise inversion of a portion of a first data, a portion of a second data, and a portion of a third data, respectively, and wherein each of the plurality of full adders adding its respective bit-wise inversion of a portion of the first data, portion of the second data, and portion of the third data, to provide a sum data at a sum output and a carry data at a carry output; and the sum output of a first of the plurality of full adders being electrically coupled to a first input and the carry output of a second of the plurality of full adders being electrically coupled to a second input of one of: 1) an exclusive-OR logic module having an output electrically coupled to an AND logic module that has an equal output, and 2) an exclusive-NOR logic module having an output electrically coupled to a NOR logic module that has an equal output, and wherein the equal output providing a signal that indicates whether the first data equals the sum of the second data and third data.