Patent ID: 7161840
Filing Date: 2007-01-09
Classification: G11C

Abstract:
1. In a flash memory device, which includes a tunnel oxide layer, a floating gate, a first block oxide layer, a second block oxide layer having an energy band gap higher than that of the first block oxide layer, and a control gate sequentially stacked on a semiconductor substrate, an erase method in the flash memory device, comprising the steps of: applying an electric field to a structure between the control gate and the semiconductor substrate by applying negative and positive voltages to the control gate and the semiconductor substrate, respectively; and weakening an intensity of the electric field applied to the tunnel oxide layer according to a progress of an erase time, and simultaneously, strengthening a relative intensity of the electric field applied to the first and second block oxide layers to control a slope of the energy band gap of the first block oxide layer, the second block oxide layer, and the tunnel oxide layer to constantly maintain a prescribed quantity of electrons on a conduction band of the floating gate.