Patent ID: 6665769
Filing Date: 2003-12-16
Classification: G11C

Abstract:
In a method of programming an N-bit memory array, whose cells are individually programmable by programming bits that exhibit a predetermined logic state using the bit pattern of an arbitrary N-bit first byte, in such a manner that no more than K cells are simultaneously programmed, the steps of:generating a first N-bit auxiliary programming byte which replicates the bit pattern of the first byte up to the Kth programming bit, and otherwise exhibits bits whose logic state is different from that of the programming bits; applying the bit pattern of the first auxiliary byte to the respective cells of the array; generating a second N-bit auxiliary programming byte which replicates the bit pattern of the first byte starting with the first bit position after the Kth programming bit and continuing to the Kth additional programming bit (if any), and otherwise exhibits bits whose logic state is different from that of the programming bits; and applying the bit pattern of the second auxiliary byte to the respective cells of the array.