Patent ID: 6168989
Filing Date: 2001-01-02
Classification: H01L

Abstract:
An improved process for fabricating an array of crown-shaped capacitors on a dynamic random access memory (DRAM) device comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding device areas, said device areas having semiconductor devices; depositing a first insulating layer over said device areas and said field oxide areas; planarizing said first insulating layer; depositing a polycide layer over said first insulating layer and patterning to form bit lines having contacts through said first insulating layer to said device areas; forming a planar second insulating layer over said bit lines; depositing a first etch-stop layer on said second insulating layer; depositing a disposable layer on said first etch-stop layer; etching contact openings in said disposable layer, said first etch-stop layer and in said second and said first insulating layers to said device areas for capacitor node contacts; depositing a doped polysilicon layer sufficiently thick to fill said contact openings; etching back said polysilicon layer to said disposable layer to form capacitor node contact plugs in said contact openings; selectively removing said disposable layer to said first etch-stop layer, and leaving portions of said node contact plugs extending above said first etch-stop layer a distance equal to the thickness of said disposable layer; depositing a blanket conformal second etch-stop layer over said node contact plugs; depositing a third insulating layer; etching openings in said third insulating layer for capacitors aligned over said node contact plugs and removing said second etch-stop layer to expose top surface of said node contact plugs while forming sidewall spacers on said node contact plugs; depositing a conformal first conducting layer and polishing back to form capacitor bottom electrodes in said openings; forming an interelectrode dielectric layer on said bottom electrodes; depositing and patterning a second conducting layer to form capacitor top electrodes, thereby completing said array of crown-shaped capacitors.