Patent ID: 7644223
Filing Date: 2010-01-05
Classification: G06F,G11C

Abstract:
1. A programmable system, comprising: a processor for generating at least a first address and a program read enable (PRE) signal; a memory for storing data, addresses, and computer codes; a first comparator circuit configured to assert at least a first control signal in response to the first address matching one of a plurality of first predetermined addresses stored therein, and to de-assert the first control signal when the matching between the first address and one of the first predetermined addresses is not present; a second comparator circuit configured to assert a second control signal in response to: (i) an assertion of the PRE signal; (ii) an assertion of a signal generated by AND-logic-operation of the PRE signal and at least one delayed assertion of the first control signal; and (iii) a second address matching the first address and an intermediate address produced by adding a predetermined number to the first address, and to de-assert the second control signal when either the matching between the second address and the intermediate address is not present or the PRE signal is disabled by the processor, wherein the assertion of a signal generated by AND-logic-operation of the PRE signal and at least one delayed assertion of the first control signal is also asserted in response to a feedback of a delayed version of the second control signal; and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a second predetermined address corresponding to the first address in response to the assertion of the second control signal, wherein the processor is responsible for reading the predetermined instruction data and the second predetermined address.