Patent ID: 6784686
Filing Date: 2004-08-31
Classification: G01R

Abstract:
A semiconductor testing device that is incorporated in chip in which a semiconductor device that is a target for test is incorporated, comprising:a pattern generator that generates and outputs a test pattern for testing the semiconductor device and incorporated in the chip; a stay time counting unit that starts counting a first count value that shows a stay time of a program in a first subroutine in synchronism with a predetermined first clock signal, when the pattern generator has output a test pattern that shows that the program shifts to the first subroutine, and outputs return instruction data when the first count value reaches a predetermined first value; a call waiting time counting unit that starts counting a second count value that shows a second subroutine call waiting time in synchronism with a predetermined second clock signal, and outputs call instruction data when the second count value reaches a predetermined second value; and a control unit that controls a program counter value so that the program returns from the first subroutine to a call originating routine, upon receiving the return instruction data from the stay time counting unit and when the pattern generator has output a test pattern that shows the program returns from the first subroutine to the call originating routine, and controls the program counter value so that the program shifts to the second subroutine, upon receiving the call instruction data from the call waiting time counting unit and also when the pattern generator has output a test pattern that shows that the program shifts to the second subroutine.