Patent ID: 7993990
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure comprising: providing a semiconductor-on-insulator substrate including a base semiconductor layer having a first crystallographic orientation, a buried dielectric layer located on an upper surface of the base semiconductor layer, and a semiconductor-on-insulator surface semiconductor layer having a second crystallographic orientation located on an upper surface of said buried dielectric layer, wherein said second crystallographic orientation is different from said first crystallographic orientation; forming a patterned hard mask having at least one opening on an upper surface of said semiconductor-on-insulator surface semiconductor layer; etching exposed portions of the semiconductor-on-insulator surface semiconductor layer and the buried dielectric layer within said at least one opening and not protected by the patterned hard mask, stopping atop the upper surface of the base semiconductor layer; forming a spacer within the at least one opening, wherein a base of the spacer is located on an exposed surface of said base semiconductor layer and a vertical wall of said spacer is located on exposed wall portions of at least the etched semiconductor-on-insulator surface semiconductor layer and the etched buried dielectric layer; forming an epitaxial surface semiconductor layer having the first crystallographic orientation on remaining exposed surfaces of the base semiconductor layer, atop said spacer and atop said patterned hard mask; removing portions of the epitaxial surface semiconductor layer, portions of the spacer and the patterned hard mask to provide a planarized substrate having said semiconductor-on-insulator surface semiconductor layer of said second crystallographic orientation separated from the epitaxial surface semiconductor layer by remaining portions of the spacer, wherein the epitaxial surface semiconductor layer has a first edge having a first defect and an adjoining second edge absent a defect; and forming within the epitaxial surface semiconductor layer a first field effect device having a first gate and a second field effect device having a second gate, the first gate being perpendicular to the first edge and the second gate being perpendicular to the second edge.