Patent ID: 6794941
Filing Date: 2004-09-21
Classification: H03F,H03G

Abstract:
A gain-controlled amplifier with a fixed minimum gain, comprising:an output load (4) across which a variable gain output signal is provided; a first gain-control output transistor (21) with its output connected to drive the output load (4) and an input to receive a first gain-control signal (16); a second gain-control output transistor (22) with its output connected in parallel with first gain-control output transistor (21) to drive the output load (4) and an input to receive a second gain-control signal (17); a third gain-control output transistor (23) with its output connected in shunt with the output load (4) and an input to receive said second gain-control signal (17); and an output-transistor signal input connected in parallel with all three of the first, second, and third gain-control output transistors (21-22); wherein, said first and second gain-control signals (16-17) when varied relative to one another will balance the contributions of amplified output signals to the output load (4) by the first and second gain-control output transistors (21-22) and an output-load shunting effect of the third gain-control output transistor (23); wherein, a minimum amplifier gain is determined by the combination of the output load (4) driven by the second gain-control output transistor (22) and shunted by the third gain-control output transistor (23); and wherein, a maximum amplifier gain is determined by the combination of the output load (4) driven by the first gain-control output transistor (21).