Patent ID: 7024442
Filing Date: 2006-04-04
Classification: G06F

Abstract:
1. A processing apparatus comprising: a memory capable of storing data; a butterfly arithmetic unit for performing butterfly computation processes; and a bit-reversed order shuffle processing unit for writing results obtained by the butterfly computation processes performed by said butterfly arithmetic unit at addresses in said memory after bit-reversed order shuffle instead of writing the results at addresses in said memory in processing order, wherein data written by said bit-reversed order shuffle processing unit are discrete fast Fourier transform results and wherein said processing apparatus further comprises a complex conjugate data transforming unit for transforming input real data into complex data, and an output reconstruction arithmetic unit for reading out the data written in said memory by said bit-reversed order shuffle processing unit and performing an output reconstruction computation process, wherein said butterfly arithmetic unit performs a butterfly computation process for the complex conjugate data, and output reconstruction computation process results obtained by said output reconstruction arithmetic unit are real discrete Fourier transform results.