Patent ID: 6853040
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A method for fabricating a MOS transistor comprising: forming a buried layer of a second conductivity type and a base layer of a first conductivity type on a semiconductor substrate of the first conductivity type; growing a semiconductor layer on the semiconductor substrate; forming a sink region of the second conductivity type in a portion of the semiconductor layer; forming a first well of the first conductivity type in a portion of the semiconductor layer overlying the buried layer and a first isolation region of the first conductivity type in a portion of the semiconductor layer overlying the base layer; forming a second well of the second conductivity type in a portion of the semiconductor layer; forming a device isolating oxide layer on the semiconductor layer, wherein the sink region is disposed under the device isolating oxide layer; forming a gate oxide layer and a gate electrode on the semiconductor layer; and forming source and drain regions in the first and second wells, respectively.