Patent ID: 8558725
Filing Date: 2013-10-15
Classification: H03M

Abstract:
1. An analog to digital converter (ADC) apparatus comprising: a clock signal generator, for generating a clock signal; a first ADC coupled to the clock signal generator, the first ADC converting an input signal to provide a first digital signal; a second ADC coupled to the clock signal generator, the second ADC converting the input signal to provide a second digital signal; wherein the input signal has an unused spectral portion that lies within a Nyquist zone of the first and second ADCs; a first digital filter, for filtering the first digital signal, to provide a first filtered signal, with the first digital filter having a frequency response that attenuates components of the first digital signal that aliased as a result of the first ADC; a second digital filter, for filtering the second digital signal, to provide a second filtered signal, the second digital filter having a frequency response that attenuates components of the second digital signal that are aliased as a result of the second ADC; an error measurement block coupled to receive the first and second filtered signals, the error measurement block producing an error measurement signal based on the first and second filtered signals; an adaptive processor coupled to receive the error signal, the adaptive processor estimating at least one of offset, gain, and sample-time error between the first and second ADCs based on the error measurement signal, the adaptive processor feeding back a correction signal corresponding to the estimated error to correct one of offset, gain, and sample-time error of at least one of the first and second ADCs; and a multiplexer, for interleaving the first and second digital signals to form a digital representation of the input signal.