Patent ID: 6780779
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising the steps of:successively depositing a first metal film and a first interlayer insulating film on an insulating film formed on a semiconductor substrate; forming a first mask pattern for masking first metal interconnect forming areas on said first interlayer insulating film, and etching said first interlayer insulating film and said first metal film by using said first mask pattern, whereby forming openings in said first interlayer insulating film and forming first metal interconnects from said first metal film; filling a second interlayer insulating film made from a different material from said first interlayer insulating film in an interval in said first metal interconnects and in said openings of said first interlayer insulating film; depositing a sacrifice film of an insulating material on said first interlayer insulating film and said second interlayer insulating film; forming a second mask pattern for masking second metal interconnect forming areas on said sacrifice film, and etching said sacrifice film by using said second mask pattern, whereby forming interconnect patterns from said sacrifice film; filling a third interlayer insulating film in an interval in said interconnect patterns; and forming a third mask pattern having via openings corresponding to via hole forming areas on said interconnect patterns and said third interlayer insulating film, and etching said interconnect patterns and said first interlayer insulating film by using said third mask pattern under etching conditions that an etching rate for said interconnect patterns is higher than an etching rate for said third interlayer insulating film and that an etching rate for said first interlayer insulating film is higher than an etching rate for said second interlayer insulating film, whereby forming via holes for exposing said first metal interconnects in said second interlayer insulating film.