Patent ID: 6406946
Filing Date: 2002-06-18
Classification: G02F,H01L

Abstract:
A method for fabricating a thin film transistor matrix device comprising:a first step of forming on a transparent insulating substrate: a plurality of gate bus lines for commonly connecting gates of thin film transistors, alternating ones of said plurality of gate bus lines being divided into either a group of odd numbered gate bus lines or a group of even numbered gate bus lines; a plurality of first outside terminals opposed to ends of the gate bus lines; and a first gate connection line for commonly connecting the gate bus lines of a selected one of the odd and the even numbered groups of gate bus lines; a second step of forming a first insulating film on the entire surface; a third step of forming on the first insulating film a plurality of drain bus lines for commonly connecting drains of the thin film transistors, alternating ones of said plurality of drain bus lines being divided into either a group of odd numbered drain bus lines or a group of even numbered drain bus lines; a plurality of second outside terminals opposed to ends of the drain bus lines, and a first drain connection line for commonly connecting the drain bus lines of a selected one of the odd and the even numbered groups of drain bus lines; a fourth step of forming a second insulating film on the entire surface; and a fifth step of forming on the second insulating film: a plurality of picture element electrodes; a second gate connection line for commonly connecting the gate bus lines of a selected other of the odd and the even numbered groups of gate bus lines; and a second drain connection line for commonly connecting the drain bus lines of a selected other of the odd and the even numbered groups of drain bus lines.