Patent ID: 9153624
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A solid state memory cell, comprising: a switching medium having a first surface and a second surface, wherein the switching medium is formed to have a thickness; a first electrode layer adjacent to the first surface of the switching medium, comprising a source of ions that are at least in part mobile within the switching medium; a second electrode layer located proximate to the second surface of the switching medium on an opposite side of the switching medium to the first electrode layer; and a first conductive layer disposed between the switching medium and the second electrode layer; and a second conductive layer disposed between the switching medium and the first electrode layer; wherein the switching medium includes a conductive path, at least a portion of which comprises a filament having a targeted filament width, that is configured to form between the first electrode layer and the second electrode layer in response to an electric signal; wherein the conductive path comprises a first region with a radius that is related to the targeted filament width in a ratio within a range of about 0.2 to about 0.5; wherein the thickness of the switching medium is related to the radius in a ratio from a range of approximately 1:2.44 to approximately 1:5; and wherein the thickness of the switching medium is determined in response to the targeted filament width.