Patent ID: 8928154
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first die; a second die stacked on the first die; first data input/output (I/O) pads disposed on a first peripheral portion of the first die, the first data I/O pads configured to input/output data I/O signals; second data I/O pads disposed on a second peripheral portion of the second die, the second data I/O pads configured to input/output data I/O signals, first command/address (C/A) pads disposed on a third peripheral portion of the first die, the first C/A pads configured to input/output C/A signals; and second C/A pads disposed on a fourth peripheral portion of the second die, the second C/A pads configured to input/output C/A signals, wherein, in a plan view, the first peripheral portion is disposed at an opposite side to the second peripheral portion, the third peripheral portion is disposed at a same side with the fourth peripheral portion, the first peripheral portion does not overlap the second peripheral portion, and the third peripheral portion overlaps at least a portion of the fourth peripheral portion.