Patent ID: 9153563
Filing Date: 2015-10-06
Classification: H01L,H02M,H03K

Abstract:
1. An electronic device, comprising: (a) a wiring board having a first surface, a first electrode formed on the first surface, a second electrode formed on the first surface, a third electrode formed on the first surface, a first external terminal electrically connected with the first electrode, a second external terminal electrically connected with the second electrode, a third external terminal electrically connected with the third electrode, and a second surface opposite to the first surface; and (b) first and second semiconductor devices each including first and second semiconductor chips, a first external connection terminal electrically connected with the first and second semiconductor chips, a second external connection terminal electrically connected with the first and second semiconductor chips, a third external connection terminal electrically connected with the first semiconductor chip, and a sealing body in which the first and second semiconductor chips are sealed, wherein the first surface of the wiring board has a pair of longer sides, and first and second shorter sides as a pair of shorter sides intersecting the pair of longer sides, wherein the first external terminal is provided beside either one of the pair of shorter sides, wherein the second external terminal is provided beside either one of the pair of shorter sides, wherein the third external terminal is provided beside either one of the pair of shorter sides, wherein the first shorter side is provided with at least one of the first, second, and third external terminals, wherein the second shorter side is provided with at least one of the first, second, and third external terminals other than the external terminal provided at the first shorter side, wherein a first insulated gate bipolar transistor including an emitter electrode, a collector electrode, and a gate electrode is formed in the first semiconductor chip, wherein the second semiconductor chip is formed with a diode including an anode electrode, and a cathode electrode, wherein the first external connection terminal is electrically connected with the emitter electrode of the first semiconductor chip and the anode electrode of the second semiconductor chip, wherein the second external connection terminal is electrically connected with the collector electrode of the first semiconductor chip and the cathode electrode of the second semiconductor chip, wherein the third external connection terminal is electrically connected with the gate electrode of the first semiconductor chip, wherein the sealing body has an upper surface, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface, and a second side surface located between the upper surface and the lower surface and facing to the first side surface, wherein the first external connection terminal is placed beside the first side surface of the sealing body, wherein the second external connection terminal is placed on the lower surface of the sealing body, wherein the third external connection terminal is placed beside the second side surface of the sealing body, wherein the first semiconductor device is mounted over the first surface of the wiring board such that the first external connection terminal of the first semiconductor device is electrically connected with the third electrode of the wiring board, and such that the second external connection terminal of the first semiconductor device is electrically connected with the second electrode of the wiring board, wherein the second semiconductor device is mounted over the first surface of the wiring board such that the first external connection terminal of the second semiconductor device is electrically connected with the second electrode of the wiring board, and such that the second external connection terminal of the second semiconductor device is electrically connected with the first electrode of the wiring board, and wherein the second semiconductor device is mounted over the first surface of the wiring board such that, in plan view, an orientation of the second semiconductor device intersects an orientation of the first semiconductor device.