Patent ID: 8245174
Filing Date: 2012-08-14
Classification: G06F

Abstract:
1. A method comprising: (a) receiving an identification of a plurality of cells to be included in a layer of an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other; (b) using a computer to identify first routing paths to connect each of the pairs of cells for which 1-D routing is possible, using one-dimensional (1-D) routing between cells within those pairs of cells, said 1-D routing including either, but not both of, horizontal lines of the layer of the IC layout, to be formed using a first mask, or vertical lines of the same layer to be formed using a second mask; (c) using the computer to select second routing paths from a predetermined set of two-dimensional (2-D) routing patterns to connect only pairs of cells which cannot be connected by 1-D routing; and (d) outputting the first and second routing paths to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.