Patent ID: 7863930
Filing Date: 2011-01-04
Classification: H03K

Abstract:
1. A programmable device, comprising: a plurality of processing tiles each including a core logic unit that performs a calculation indicated by circuit information, and a configuration memory that stores the circuit information to be set in the core logic unit; a power supply unit operable to supply power to the core logic unit and the configuration memory in each of the plurality of processing tiles; and a control unit operable to, for each of the plurality of processing tiles, (i) when a processing tile is to be in a wait state, with use of the configuration memory included in the processing tile, save data related to an internal state of the core logic unit in the processing tile, and cut off a power supply route to the core logic unit that is separate from a power supply route to the configuration memory, and (ii) when the processing tile is to be in a used state, after connecting the power supply route to the core logic unit, restore the data related to the internal state to the core logic unit, wherein the control unit, when cutting off the power supply route to the core logic unit, does not cut off the power supply route to the configuration memory.