Patent ID: 9183905
Filing Date: 2015-11-10
Classification: G11C

Abstract:
1. A delay circuit comprising: a first first-conductive type transistor configured to receive an input signal at a gate; a second first-conductive type transistor connected in series to the first first-conductive type transistor, a gate potential of the second first-conductive type transistor being set so as to adjust a charge amount carried between a source and a drain; a first second-conductive type transistor connected in series to the second first-conductive type transistor and configured to receive the input signal at a gate; a second second-conductive type transistor connected in series to the first second-conductive type transistor and configured to receive a source potential of the second first-conductive type transistor at a gate; and a third second-conductive type transistor connected in parallel with the second second-conductive type transistor and configured to receive the input signal at a gate.