Patent ID: 6492857
Filing Date: 2002-12-10
Classification: H03K

Abstract:
A transition NAND gate comprising:two or more input nodes; an output node; circuitry responsive to the two or more input nodes; the circuitry being capable of transitioning from a most recent current state to a state that is not a current state; the output node storing the current state of the circuitry, wherein the circuitry comprises: a supply-side FET for each input terminal,the gate of each supply-side FET being connected to a respective input terminal, the supply-side FETs being connected in series, the series-connected supply-side FETs having a supply end and an output end; a ground-side FET for each input terminal,the gate of each ground-side FET being connected to a respective input terminal, the ground-side FETs being connected in series, the series-connected ground-side FETs having a ground end and an output end; the output end of the series-connected supply-side FETs being connected to the output end of the series connected ground-side FETs to form an output terminal, wherein said circuitry comprises a state machine.