Patent ID: 8890546
Filing Date: 2014-11-18
Classification: G01D

Abstract:
1. An apparatus for digitising an impedance, comprising; a first impedance element having a first impedance that varies with a property to be measured; a second impedance element having a second impedance; a drive signal generator configured to apply a first alternating drive signal to the first impedance element and a second alternating drive signal to the second impedance element; and an analogue-to-digital converter (ADC) configured to receive and digitise a resultant signal, the resultant signal comprising a combination of signals produced by the application of the first and second alternating drive signals to the first and second impedance elements, wherein the first alternating drive signal is phase shifted relative to the second alternating drive signal such that the resultant signal received and sampled by the analogue-to-digital converter sequentially relates to the sum of, and the difference between, the first and second impedances, wherein the apparatus comprises a signal separator that receives sample values from the ADC and provides a sum channel and a difference channel, the sum channel comprising a series of values relating to the sum of the first and second impedances and the difference channel comprising a series of values relating to the difference between the first and second impedances, and wherein the apparatus further comprises a divider, the divider dividing values in the difference channel by values in the sum channel to thereby produce a stream of output values, and the output values relating to the ratio of the difference between the first and second impedances and the sum of the first and second impedances.