Patent ID: 7802058
Filing Date: 2010-09-21
Classification: G06F

Abstract:
1. A method for performing cache coherency in a computer system, comprising: selecting a first one of a plurality of coherency protocols for a first memory transaction; performing cache coherency for the first memory transaction on caches in the computer system by applying a first set of cache states to cached data in accordance with the first one of the plurality of coherency protocols selected for the first memory transaction; selecting a second one of a plurality of coherency protocols for a second memory transaction, the second one of the plurality of coherency protocols selected for the second memory transaction being different than the first one of the plurality of coherency protocols selected for the first memory transaction; performing cache coherency for the second memory transaction on caches in the computer system by applying a second set of cache states to cached data in accordance with the second one of the plurality of coherency protocols selected for the second memory transaction; wherein selection among the plurality of cache coherency protocols is performed on a dynamic basis for each separate memory transaction to be processed.