Patent ID: 9054939
Filing Date: 2015-06-09
Classification: G09G,H04L

Abstract:
1. A method of processing data, comprising: dividing, at a transmitter, data into 3-bit units; generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal; transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal; and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal, wherein generating the first and second clock embedded data signals comprises, pulse-amplitude-modulating, at a polarity signal generating part, the first and second bits of the units to generate first and second signals, respectively; and receiving, at a clock information inputting part, the first and second signals from the polarity signal generating part, reversing polarities of the first and second signals in response to the clock signal and embedding the clock signal in the first and second signals where the polarity reversal occurs to convert the first and second signals to first and second dock embedded signals, respectively, wherein the first and second bits of the units are each pulse-amplitude modulated by four levels, wherein generating the third data signal comprises pulse-amplitude modulating the third bits of the units to generate a third signal, wherein the third bits of the units are pulse-amplitude modulated by two levels, wherein pulse-amplitude-modulating the first and second bits comprises, generating the first signal having a first positive polarity level voltage and a second positive polarity level voltage with respect to a first reference voltage and the second signal having a first negative polarity level voltage and a second negative polarity level voltage with respect to a second reference voltage, wherein pulse-amplitude-modulating the third bits comprises, pulse-amplitude-modulating the third bits to a first level voltage and a second level voltage with respect to a third reference voltage, the third reference voltage being different from each of the first and second reference voltages.