Patent ID: 8268691
Filing Date: 2012-09-18
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, the method comprising: forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode, the first dielectric having upper portions overlying the sidewalls of the gate electrode and lower portions adjacent a bottom portion of the gate electrode, the at least one dielectric layer forming an etch stop layer; depositing a spacer dielectric layer over the at least one dielectric layer; anisotropically etching the spacer dielectric layer to remove horizontal portions of the spacer dielectric using the at least one dielectric layer as an etch stop and forming gate sidewall spacers on opposing sidewalls of the gate electrode; patterning an opening in the at least one dielectric layer overlying the first doped region, the opening spaced from at least one of the gate sidewall spacers by a spacing distance, the lower portions of the at least one dielectric layer extending laterally and parallel to a planar top surface of the substrate from the bottom portion of the gate electrode over the portion of the first doped region by a distance corresponding to the spacing distance; and forming a second doped region substantially within the opening in the portion of the first doped region adjacent the one of the gate sidewall spacers and spaced apart from the one of the gate sidewall spacers by at least the spacing distance.