Patent ID: 6258682
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of making ultra shallow junction MOSFET, said method comprising the steps of:providing a semiconductor substrate having source/drain regions and poly-gate region formed thereon;depositing an IMP silicon layer on said source/drain regions and a polysilicon layer on said polygate region using ion-metal plasma directional;performing a first ion implantation to entire areas;performing a thermal oxidation process to form an IMP oxide layer on said source/drain regions and said polysilicon layer by partially oxidizing said IMP silicon layer, said polysilicon layer;forming a dielectric layer on entire areas;performing an anisotropic etching so as to form sidewall spacers on said poly-gate and to do IMP oxide layer removal;performing a second ion implantation through said IMP silicon into said source/drain regions;forming metal layer on entire areas;performing a thermal annealing process so as to form a metal silicide layer on surfaces of said source/drain regions and said polygate region; andremoving unreactive metal layer.