Patent ID: 6518825
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a main circuit which includes a PMOS transistor having a source-drain channel between a first operating-potential point and a second operating-potential point lower than the first operating-potential point and a NMOS transistor having a source-drain channel between said first operating-potential point and said second operating-potential point and connected in series to said PMOS transistor; a changeover circuit which generates a changing signal; a substrate bias control circuit which includes a substrate potential generator to generate a first substrate potential lower than the first operating potential and a second substrate potential higher than the second operating potential; and a switching circuit which includes a first switching element provided between said first operating-potential point and a substrate-potential supplying point of said PMOS transistor and a second switching element provided between said second operating-potential point and a substrate-potential supplying point of the NMOS transistor; wherein said substrate bias control circuit responds to the changing signal to control the switching circuit; and (i) in the case that said changing signal is in a first state, said first and second switching elements are turned on, the substrate of said PMOS transistor is supplied with first operating potential from said first operating-potential point and the substrate of said NMOS transistor is supplied with second operating potential from said second operating-potential point, and (ii) in the case that the changing signal is in a second state, said first and second switching elements are turned off, said substrate potential generator supplies said first substrate potential which is forward bias to the substrate of said PMOS transistor and said second substrate potential which is forward bias to the substrate of said NMOS transistor.