Patent ID: 6252426
Filing Date: 2001-06-26
Classification: H03K

Abstract:
A logic circuit having an output comprising:a first transistor with a first polarity having a source, a drain and a gate, the source of the first transistor is coupled to a power supply voltage, the drain of the first transistor is coupled to the output of the logic circuit, and the gate of the first transistor is coupled to a first input signal;a second transistor with the first polarity having a source, a drain and a gate, the source of the second transistor is coupled to the power supply voltage, the drain of the second transistor is coupled to the output of the logic circuit, and the gate of the second transistor is coupled to a second input signal;a third transistor with a second polarity having a source, a drain and a gate, the source of the third transistor is coupled to a third input signal, the drain of the third transistor is coupled to the output of the logic circuit, and the gate of the third transistor is coupled to the first input signal; andthe logic circuit not having a fourth transistor with a source, a drain and a gate, with the source coupled to the complement of the first input signal, the drain coupled to the output of the logic circuit, and the gate coupled to the second input signal.