Patent ID: 8111494
Filing Date: 2012-02-07
Classification: G11C

Abstract:
1. A memristor-protection integrated circuit, comprising: a first current-bias circuit, said first current-bias circuit configured to be coupled to a first rail of a power supply; a second current-bias circuit, said second current-bias circuit configured to be coupled to a second rail of said power supply; an inverter, said inverter coupled to said first current-bias circuit and coupled to said second current-bias circuit, and said inverter configured to couple at least one memristor to at least one of said first current-bias circuit and said second current-bias circuit in response to an input signal applied to said inverter; and a current limiter, said current limiter coupled to said first current-bias circuit and coupled to said second current-bias circuit, said current limiter configured to limit current flowing through said memristor.