Patent ID: 6590423
Filing Date: 2003-07-08
Classification: H03K

Abstract:
A storage element comprising:a combinational logic element (708, 716; 804, 812) having a storage node (706; 814) as input and having an output (714; 810) on which is produced an output signal OUT; a transistor (712; 808) having a clock (704; 802) input for reception of a low-voltage swing clock, an input for receiving an input signal IN and an output connected to said storage node (706; 814); and a pullup/pulldown means (702; 816) having an input for application of a supply voltage (VDD; GND) and having an output connected to said storage node (706; 814) for pulling said storage node (706; 814) to said supply voltage (VDD; GND); wherein said low-voltage swing clock has a voltage swing at least 10% smaller than the voltage swing of a normal logic signal, whereby, in spite of the reduced amplitude of the clock signal, said storage node is pulled to said supply voltage (VDD, GND) by said pullup/pulldown means, and whereby the clock power consumption of said storage element is reduced compared to a storage element using a full voltage swing clock.