Patent ID: 8264873
Filing Date: 2012-09-11
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory circuit coupled to a memory cell array, the non-volatile semiconductor memory circuit comprising: a control signal generation unit configured to provide a control signal in response to a read command or a write command; and a sensing block configured to include a sensing reference voltage providing section receiving a reference voltage, generate a second sensing reference voltage by transmitting the reference voltage when the control signal is enabled, or a first sensing reference voltage which is lower than the reference voltage when the control signal is disabled, selectively provide one of the reference voltage as a first sensing reference voltage and the reference voltage as a second sensing reference voltage to the sense amplifier, wherein the first and second sensing reference voltages are used to read data of the memory cell array, and the sensing block comprises a sensing reference voltage providing section configured to provide the first sensing reference voltage during a normal read operation and the second sensing reference voltage during a verify read operation.