Patent ID: 6489829
Filing Date: 2002-12-03
Classification: H03K

Abstract:
A circuit arrangement comprising:a power source comprising a power terminal and a ground terminal; a power MOSFET including a gate, a first terminal, a second terminal, and a first threshold voltage, wherein the first terminal of said power MOSFET is coupled to one of said power terminal and said ground terminal of said power source; a load coupled to said second terminal of said power MOSFET; a control circuit comprising at least a first input, a second input, and a third input, and at least a first output, a second output, and a third output, wherein the first input of said control circuit is coupled to an enable signal, said control circuit adapted to control the drive force applied to said gate of said power MOSFET to control a turn-on of said power MOSFET and to limit a rush current through said power MOSFET; a sense circuit comprising at least an input, a first output, and a second output, wherein the input of said sense circuit is coupled to said gate of said power MOSFET, the first output of said sense circuit is coupled to said second input of said control circuit, and the second output of said sense circuit is coupled to said third input of said control circuit, said sense circuit adapted to sense when said power MOSFET has been enhanced by a first level and by a second level; an off circuit comprising an input and an output, wherein said input of said off circuit is coupled to said third output of said control circuit and said output of said off circuit is coupled to said gate of said power MOSFET, said off circuit adapted to turn said power MOSFET off when necessary; a first drive circuit comprising an input and an output, wherein the input of said first drive circuit is coupled to said first output of said control circuit and the output of said first drive circuit is coupled to the gate of said power MOSFET, said first drive circuit adapted to adjust the voltage applied to said gate of said power MOSFET at a first rate; a second drive circuit comprising an output coupled to the gate of said power MOSFET, said second drive circuit adapted to adjust the voltage applied to said gate of said power MOSFET at a second rate that is less than said first rate; and a third drive circuit comprising an input and an output, wherein the input of said third drive circuit is coupled to said second output of said control circuit and the output of said third drive circuit is coupled to the gate of said power MOSFET, said third drive circuit adapted to adjust the voltage applied to said gate of said power MOSFET to a maximum level allowable by said power source at a third rate that is greater than said second rate.