Patent ID: 7647472
Filing Date: 2010-01-12
Classification: H04L

Abstract:
1. An integrated circuit comprising: a single chip having components including a plurality of data stream inputs that receive streams of data and/or data stream outputs that transmit streams of data; a plurality of data stream processors that process the received data streams and/or the data streams to be transmitted, each data stream processor being directly coupled to a data stream input of the plurality of the data stream inputs and/or a data stream output of the plurality of the data stream outputs; and a plurality of writeable local memories, each writable local memory being local to a given data stream processor of the plurality of data stream processors, the writeable local memories belonging in a global address space which is addressable by any of the data stream processors via a global bus, an aggregator that aggregates certain of the data stream processors so that the aggregated data stream processors are each coupled to a given data stream input or given data stream output and cooperate in processing the data stream received in the given data stream input or to be transmitted by the given data stream output, the aggregator including configurable interconnections between the aggregated data stream processors, a configurable, operation coordinator that coordinates operation of the aggregated data stream processors; and a configurator that specifies the configurable interconnections and the configurable operation coordinator as required for each of the certain data stream processors to be coupled to given data stream input or the given data stream output, the configurator configuring the certain of the data stream processors to cooperate either in a receive aggregation mode or in a transmit aggregation mode, the receive aggregation mode being a mode wherein each of the certain data stream processors receives the entire data stream received in the given data stream input, and the transmit aggregation mode being a mode wherein each of the certain data stream processors provides part of the data stream to be transmitted by the given data stream output.