Patent ID: 6172402
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A transistor formed on a semiconductor substrate, comprising:an active region;a trench isolation region surrounding the active region the trench isolation region comprising a trench filled with a dielectric, the trench having a substantially flat bottom and substantially vertical sidewalls;a channel formed in a top portion of the active region;a source formed in a top portion of the active region and residing adjacent a first end of the channel;a drain formed in a top portion of the active region and residing adjacent a second end of the channel;an implanted insulative layer formed in the semiconductor substrate;wherein a first portion of the implanted insulative layer resides below the channel, the source and the drain to form an insulative punchthrough layer that extends fully across the active region;wherein a second portion of the implanted insulative layer resides below the filled dielectric of the trench isolation region and extends fully across the bottom of the trench;wherein the implanted insulative layer resides at a first depth in the substrate across the trench isolation region and at a second depth in the substrate across the active region, wherein the first depth is greater than the second depth;a gate oxide formed above the channel; anda gate conductor formed above the gate oxide.