Patent ID: 6165820
Filing Date: 2000-12-26
Classification: H01L,H05K

Abstract:
A package for a semiconductor chip having at least one semiconductor device, wherein a first surface of the chip is bonded to a base, the base being attached to a frame, and the frame attached to a lid to enclose the chip, the chip having at least one contact pad on its second surface, characterized in that:the lid comprises a rigid, planar, insulating substrate having a conductive pattern at least on a first surface facing the chip, the conductive pattern of the lid being electrically connected to the chip through soft, ductile, metal protuberances between the chip and the lid, the number of protuberances connected to a contact pad being sufficient to minimize the contact resistance and the power lost as heat (I.sup.2 R) between the chip and the lid, and minimize the current density on the surface of the chip.