Patent ID: 6319774
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for forming a non volatile memory on a silicon substrate having an existing topography, comprising:forming a field oxide in a surface of the substrate to separate an active area from an adjacent active area;forming a planarized isolation layer on the existing topography of the substrate, wherein the planarized isolation layer includes a top surface, and wherein forming the planarized isolation layer includes forming a first masking layer over and upon the existing topography of the substrate and depositing a second masking layer of isolation material on the first masking layer;removing a portion of the planarized isolation layer to form a substantially cylindrical opening having walls extending from the top surface of the planarized isolation layer to the field oxide, wherein removing a portion of the planarized isolation layer includes removing portions of the second masking layer using the first masking layer as an etch stop, and next removing portions of the first masking layer, wherein removing portions of the first masking layer includes exposing the substrate and at least a portion of the field oxide;forming a gate oxide region layer on and conforming to the existing topography of the substrate;forming a conductive bottom plate layer on and conforming to the top surface of the planarized isolation layer, each and every surface of the substantially cylindrical walls of the planarized isolation layer, the portion of the field oxide and the gate oxide region layer;selectively removing a portion of the conductive bottom plate layer from the second masking layer of isolation material only at a location directly on the top of the planarized isolation layer, which is, adjacent to the substantially cylindrical opening such that the portion of the field oxide, the gate oxide region layer and the walls of the substantially cylindrical opening are completely covered by the conductive bottom plate layer;forming a dielectric layer on and conforming to the conductive bottom plate layer and on and conforming to the second masking layer of isolation material where the portion of the conductive bottom plate layer has been selectively removed, wherein the conductive bottom plate layer remains conforming to the substantially cylindrical walls of the isolation layer; andforming a conductive top plate layer on and conforming to the dielectric layer.