Patent ID: 7032165
Filing Date: 2006-04-18
Classification: H03M

Abstract:
1. A device for implementing a function of add-compare-select type in an error correction code decoder, comprising: a first adder for adding, for a first branch, a branch metric value, an intermediate value of former state metric, and an offset value of former state metric, thus forming a first value of present state metric; a second adder for adding, for a second branch, a branch metric value, an intermediate value of former state metric, and an offset value of former state metric, thus forming a second value of present state metric; a comparator, coupled to the first and second adders, for selecting a highest value from among the first and second values of present state metrics; a first storage means for storing the selected value of present state metric; means for determining a digital offset value of present state metric comprised of a single bit, based on the first and second values of present state metrics; and a second storage means for storing the offset value of present state metric.