Patent ID: 7151297
Filing Date: 2006-12-19
Classification: H01L

Abstract:
1. An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; a third semiconductor layer of the first conductivity type on the second semiconductor lever; trenches formed through the third semiconductor layer down to the second semiconductor layer to divide the third semiconductor layer into at least into relatively narrow semiconductor regions and relatively wide semiconductor regions; fourth semiconductor layers of the second conductivity type selectively formed at least in the surface portions of the relatively narrow semiconductor regions; a control electrode formed in each of the trenches with an insulator film interposed between the control electrodes in the trenches; a first main electrode on the third and fourth semiconductor layers with an interlayer insulator film interposed between the first main electrode and the third and fourth semiconductor layers, the first main electrode being in contact with the third semiconductor layer and the fourth semiconductor layers through the interlayer insulator film in the relatively narrow semiconductor region; and the first main electrode being connected electrically to the third semiconductor layer via resistance of 50 mΩ or higher in the relatively wide semiconductor regions, and a second main electrode connected electrically to the first semiconductor layer, wherein the resistance comprises the sheet resistance of an impurity layer in the relatively wide semiconductor region, and the impurity layer is connected electrically to the first main electrode via contact holes formed locally through the interlayer insulator film.