Patent ID: 6608348
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A semiconductor device comprising a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction,wherein each of the nonvolatile semiconductor memory devices is capable of carrying a cell current and includes: a semiconductor substrate; a floating gate having a major axis disposed on the semiconductor substrate through a first insulating layer which is capable of functioning as a gate insulating layer interposed therebetween; a second insulating layer disposed on the floating gate; a third insulating layer which is formed in contact with at least part of the floating gate and is capable of functioning as a tunnel insulating layer; a control gate which is isolated from the floating gate by the third insulating layer and extends in the row direction; and impurity diffusion layers which are formed in the semiconductor substrate, forming a source region and a drain region, wherein the nonvolatile semiconductor memory devices which are adjacent to each other in the row direction are isolated by element isolations region extending in the column direction, and wherein one of angles formed where a major axis direction of the floating gates in a planar configuration of the memory cell array intersects the column direction is an acute angle, whereby the cell currents may be increased without enlarging the memory cell array.