Patent ID: 8940608
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit comprising: providing a semiconductor substrate having an upper surface formed by a drift region of a first doping type, a first region of the first doping type formed in the drift region, a third region of the opposite doping type, a second region of the first doping type formed in the third region, an isolation region formed in the third region adjacent the second region, and a temporary gate structure between the drift region and the second region; applying a layer of photoresist to the upper surface formed by the first region, the second region, the drift region, and the third region; etching the layer of photoresist to form a mask covering the upper surface formed by the drift region and the third region; performing a source/drain ion implantation into the first region and the second region, wherein the mask prevents the upper surface formed by the drift region and the upper surface formed by the third region from receiving the source/drain ion implantation; removing the mask and exposing the upper surface formed by the drift region and the third region; after removing the mask, removing the temporary gate structure and defining a gate trench; forming a replacement gate structure in the gate trench; depositing an insulating dielectric layer over the replacement gate structure and semiconductor substrate; forming trenches in the insulating dielectric layer to expose the first region and the second region; and siliciding the exposed regions.