Patent ID: 6427192
Filing Date: 2002-07-30
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configure to receive and store instruction bytes; a branch target array coupled to said instruction cache and configured to store branch target information corresponding to said stored instruction bytes; and a victim branch prediction cache coupled to said branch target array, wherein said branch target array is configured to output said stored branch target information to said victim branch prediction cache in response to said corresponding instruction bytes being overwritten in said institution cache, and wherein said victim branch prediction cache is configured to store said branch target information received from said branch target array and convey said stored branch target information hack to said branch target array in response to said corresponding instruction bytes once again being stored in said instruction cache, and wherein said branch target information comprises at least an address tag, two or more branch target addresses, two or more taken/not bits, and strength information for each branch target address.