Patent ID: 7876439
Filing Date: 2011-01-25
Classification: G03F

Abstract:
1. A method of determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level of a wafer using a target thereon comprising: creating a first target pattern on a lithographic field containing an integrated circuit pattern, the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center, located solely at corners of a geometric shape and at a same first distance from the first target pattern center; creating a second target pattern on a different lithographic field containing an integrated circuit pattern, the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center, located solely at corners of a geometric shape and at a same second distance from the second target pattern center, the second target pattern center intended to be at the same location as the first target pattern center, the second distance being the same or different than the first distance and the sub-patterns of the second target pattern being substantially non-overlapping with the sub-patterns of the first target pattern; determining the center of each of the sub-patterns; using the center of each of the sub-patterns, determining the center of the first target pattern and the center of the second target pattern; and measuring positioning error between the lithographic fields by comparing locations of the first target pattern center and the second target pattern center.