Patent ID: 6124165
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method for making fuses for Dynamic Random Access Memory (DRAM) circuits comprising the steps of:providing a semiconductor substrate having devices in device areas surrounded by a field oxide isolation, said devices formed in part from a patterned first polycide layer;forming a planar first insulating layer on said substrate over said devices;depositing a second polycide layer and a cap layer on said first insulating layer;patterning said cap layer and said second polycide layer to form bit lines in memory cell areas of said DRAMs, and to form local interconnections having portions for fuses, and forming sidewall spacers on sidewalls of said patterned second polycide layer;depositing a second insulating layer over said patterned second polycide layer, and planarizing said second insulating layer;etching contact openings in said second insulating layer over said bit lines and in said first insulating layer to said substrate for self-aligned node capacitors in said memory cell areas;depositing a doped polysilicon layer on said second insulating layer and in said contact openings; p1 patterning said polysilicon layer to form self-aligned node contacts in said contact openings and forming said node capacitors, one on each of said node contacts;depositing a third insulating layer over said second insulating layer and said node capacitors, and planarizing said third insulating layer;depositing a first metal layer and an anti-reflective coating (ARC) layer;patterning said ARC layer and said first metal layer to form electrical interconnections;depositing a fourth insulating layer;etching via holes in said fourth insulating layer to said ARC layer on said patterned first metal layer, and concurrently etching wider fuse window openings over portions of said second polycide layer used for said fuses, said fuse window openings etched in said fourth and partially into said third insulating layers, while said ARC layer prevents overetching of said first metal layer;depositing an adhesion layer, and depositing a refractory metal layer and etching back to form refractory metal plugs in said via holes while removing said refractory metal in said fuse window openings;depositing a second metal layer and patterning to form metal interconnections including metal bonding pads, said patterning removing said second metal in said fuse window openings, and further etching said third insulating layer over said fuses in said fuse window openings;depositing a passivation layer over said substrate;using a single photoresist mask and anisotropic etching to etch said passivation layer to said second metal layer to form openings for said bonding pads and etching in said fuse window openings to said third insulating layer;etching selectively said third insulating layer and said second insulating layer to said cap layer on said second polycide layer to complete said fuse window openings to said fuses.