Patent ID: 6167544
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A method of testing refresh timing of a dynamic memory device connected to a high reference voltage source and a low reference voltage source and including at least one memory cell, at least one bit line selectively connected to the memory cell, at least one word line connected to the memory cell and a bootstrap circuit connected to the word line for providing a voltage thereon in excess of the high reference voltage source during a write operation, said method comprising the steps of:writing data into the memory cell of the dynamic memory;waiting a predetermined period of time;reading the data stored in the memory cell; andcomparing the data written into the memory cell with the data read from the memory cell;said step of writing data into the memory cell includes the step of driving the word line to a voltage level less than the bootstrap circuit driven voltage level in excess of the high reference voltage source.