Patent ID: 9041076
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method for fabrication of a gate structure in a semiconductor device, said method comprising steps of: forming a patterned gate stack on a substrate, said patterned gate stack comprising: forming gate spacers on vertical sidewalls of the gate stack; forming source and drain regions on opposite sides of the gate spacers; removing the cap layer; encapsulating top and sidewalls of the gate stack with nitride; planarizing the nitride encapsulation using an organic planarizing layer, thus protecting the source and drain regions; removing a top portion of the nitride encapsulation; removing the top portion of the gate stack; removing a remaining portion of the nitride encapsulation and the organic planarizing layer; and performing silicidation over the source and drain regions and the bottom portion of the gate stack.