Patent ID: 6028001
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of fabricating a contact hole to an integrated circuit substrate comprising the steps of:forming an interlayer dielectric layer on the integrated circuit substrate;forming a first layer on the interlayer dielectric layer, opposite the integrated circuit substrate;forming a second layer on the first layer, opposite the interlayer dielectric layer;forming a photoresist pattern on the second layer, opposite the first layer, the photoresist pattern including a first opening therein;etching the second layer through the first opening to define a sidewall therein while concurrently forming a polymer on the sidewall of the second layer during the etching step, so as to form a second opening in the second layer that is smaller than the first opening;obliquely etching the first layer through the second opening to form a third opening that is smaller than the second opening; andvertically etching the interlayer dielectric layer to form the contact hole to the integrated circuit substrate.