Patent ID: 6566914
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A circuit comprising:a sense amplifier having (1) an input matched differential field effect transistor (FET) pair coupled between a power supply node and a power return node, each FET of the input pair having gate, drain, source, and bulk regions, each FET having a channel length on the order of 0.18 microns and less, (2) first and second output nodes whose voltages are to be driven in opposite directions by the input pair, each output node to provide a voltage swing between the supply and return nodes, (3) a reset circuit coupled to selectively equalize the first and second output nodes, and (4) switching field effect transistor coupled in series with a common source node of the pair; and one of a logic gate and a flip flop, having an input coupled to receive the voltage swing, wherein the bulk and source regions of each FET of the input pair in the sense amplifier are shorted so that a bulk-source junction of each FET is zero biased to improve Vt mismatch in the input differential pair.