Patent ID: 7016215
Filing Date: 2006-03-21
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a normal memory cell array in which a plurality of normal memory cells each comprising a ferroelectric capacitor are arranged; a normal word line which is connected to the normal memory cells of the normal memory cell array; a normal word line driver which selectively drives the normal word line; a normal plate line which is connected to the normal memory cells of the normal memory cell array; a spare memory cell array in which a plurality of spare memory cells each comprising a ferroelectric capacitor are arranged, the spare memory cells being used as a substitution of a faulty normal memory cell of the normal memory cell array; a spare word line which is connected to the spare memory cells of the spare cell array; a spare word line driver which selectively drives the spare word line; a spare plate line which is connected to the spare memory cells of the spare memory cell array; an address input circuit to which an address signal for selectively specifying the memory cells is inputted; and a judging circuit which compares an address inputted in the address input circuit with a faulty address previously stored and generates an output signal for selecting one of the normal word line driver and spare word line driver according to a result of the comparison, wherein the normal word line driver and spare word line driver are simultaneously selected by an output signal of the address input circuit to start driving the normal word line and spare word line, after the start of the driving of the normal word line and spare word line and before the normal plate line or spare plate line is driven, the normal word line driver and spare word line driver are selected by the output signal of the judging circuit to stop the driving of one of the normal word line and spare word line, return the potential of the one of the normal word line and spare word line to its respective inactivation level, and continue the other of the driving of the normal word line and spare word line, each of the normal memory cells comprises a cell transistor whose gate is connected to a corresponding one of the normal word lines and the ferroelectric capacitor connected to one terminal of the cell transistor, each of the spare memory cells comprises a cell transistor whose gate is connected to a corresponding spare word line and the ferroelectric capacitor connected to one terminal of the cell transistor, a bit line is connected to one terminals of the normal memory cell and spare memory cell, a normal plate line is connected to the other terminal of the normal memory cell, a spare plate line is connected to the other terminal of the spare memory cell, the normal word line driver and spare word line driver start to drive the normal word line and spare word line, the normal plate line and spare plate line are selectively driven after the start of the driving, the normal plate line and spare plate line being connected to the normal memory cell and spare memory cell to which the normal and spare word lines and spare word lines are connected, the normal word line and spare word line are started to be driven by the normal word line driver and spare word line driver so that a potential of the normal word line and spare word line changes toward an activation level, the driving of one of the normal word line and spare word line caused by the normal word line driver and spare word line driver is stopped and the driving of the other of the normal word line and spare word line is continued, before the potential of the normal word line and spare word line reaches the activation level, the normal word line driver comprises a first logic circuit which carries out a logic operation of a pulse signal A outputted from the address input circuit and an output signal F outputted from the judging circuit, and a second logic circuit to which a plurality of normal word line selecting signals and an output signal of the first logic circuit are inputted, and from which an output signal having the same logic level as that of the output signal of the first logic circuit is outputted, the spare word line driver has the same configuration as that of the word line driver and comprises a first logic circuit which carries out a logic operation of a pulse signal A′ outputted from the address input circuit and an output signal F′ outputted from the judging circuit, and a second logic circuit to which a plurality of spare word line selecting signals and an output signal of the first logic circuit are inputted, and from which a signal having the same logic level as that of the output signal of the first logic circuit is outputted, the input signals A′ and F′ corresponding to the input signals A and F inputted to the normal word line driver, respectively, and the plurality of spare word line selecting signals corresponding to the plurality of word line selecting signals inputted to the normal word line driver, and a width of the pulse signal A outputted from the address input circuit is shorter than a rise time of the output signals of the second logic circuits of the normal word line driver and the spare word line driver.