Patent ID: 7302524
Filing Date: 2007-11-27
Classification: G06F

Abstract:
1. An apparatus for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache, comprising: at least one instruction register, the at least one instruction register having a thread ID indicator; an address generator having a cache index indicator and a plurality of cache index bits; a cache memory; a selector for selecting between the thread ID indicator and the cache index indicator, the selector outputting an upper index indicator, and at least one cache miss counter, the at least one cache miss counter counting cache misses, wherein the at least one cache miss counter controls the selector; and wherein when the thread ID indicator is selected by the selector, the thread ID indicator is output to the upper index indicator, and the upper index indicator is concatenated with the plurality of cache index bits to form an address for retrieving an entry from the cache memory.