Patent ID: 6115321
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A memory circuit for operating synchronously with a system clock signal, comprising:an array of memory cells arranged in rows and columns;a first group of columns;a second group of columns, exclusive of the first group of columns;a third group of columns including columns from the first and second groups;a fourth group of columns including columns from the first and second groups, exclusive of the third group of columns; anda logic circuit coupled to receive a mode control signal, a first column address signal and a second column address signal, the logic circuit arranged to produce a first group of column address signals corresponding to the first group of columns at a first time and a second group of column address signals corresponding to the second group of columns at a second time in response to a first logic state of the mode control signal, the second column address signal, and a first and a second logic state of the first column address signal,the logic circuit arranged to produce a third group of column address signals corresponding to the third group of columns at a third time, and a fourth group of column address signals corresponding to the fourth group of columns at a fourth time in response to a second logic state of the mode control signal and the first and second column address signal.