Patent ID: 7342838
Filing Date: 2008-03-11
Classification: G06F

Abstract:
1. Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface comprising: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal, wherein the phase relationship is based upon the state of the internal PLD clock at a first rising edge in the DQS signal following a preamble signal; a first buffer to detect the DQS signal from a DQS pad; and a second buffer to detect the preamble from the DQS pad.