Patent ID: 6906360
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. An integrated circuit having complementary metal oxide semiconductor (CMOS) transistors including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each said NFET and said PFET having a channel region disposed in a single-crystal layer of a first semiconductor, wherein a stress is applied at a first magnitude to a channel region of said PFET but not to a channel region of said NFET by a layer of a second semiconductor which is lattice-mismatched to said first semiconductor, said layer of said second semiconductor being formed in source and drain regions of said PFET a first distance from said channel region of said PFET, and said layer of said second semiconductor further being formed in source and drain regions of said NFET at a second distance from said channel region of said NFET, said second distance being greater than said first distance.