Patent ID: 7002377
Filing Date: 2006-02-21
Classification: G01R,H03K

Abstract:
1. A clock signal detection circuit, comprising: a first circuit generating an output signal of predetermined potential in accordance with a first level of a clock signal, and setting an output terminal to a high impedance state in accordance with a second level of the clock signal; an impedance element that is disposed between the output terminal of the first circuit and a potential source having a potential that is different from the predetermined potential, and that maintains the output signal above a first threshold when the output terminal is in the high impedance state for less than a first period; and a second circuit generating a clock signal detection result that is a first state when the output signal is above the first threshold and is a second state when the output signal is below the first threshold, wherein the output signal decreases below the first threshold when the output terminal is in the high impedance state for greater than or equal to the first period.