Patent ID: 6101596
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A data processing apparatus, comprising:a plurality of memories which store data;a processor which has registers for storing data, and which outputs an address and a register number for reading data from said memories;at least two data buses connected to said memories; anda memory controller which controls said memories, wherein said memory controller comprises:a plurality of buffers provided for said at least two data buses for storing a plurality of register numbers output from said processor,a first selector which selects one of data transmitted on said at least two data buses, anda second selector which selects a register number corresponding to said data selected by said first selector,wherein, based on said address output from said processor, said memory controller reads data from memories, and outputs to said processor said data selected by said first selector and said register number selected by said second selector, to be stored in one of said registers of said processor corresponding to said register number.