Patent ID: 6990016
Filing Date: 2006-01-24
Classification: G11C

Abstract:
1. A method of making a memory cell circuit comprising the steps of: forming a transfer field effect transistor (FET) in a first region of a substrate so as to be connected in series between a data line and a storage node; and forming a first negative differential resistance (NDR) FET in a second region of said substrate so as to be connected in series between a first voltage potential and said storage node; and forming a second negative differential resistance (NDR) FET in a third region of said substrate so as to be connected in series between said storage node and a second voltage potential; and wherein said transfer FET and at least one of said first NDR FET or said second NDR FET share a common source/drain region, which common source/drain region operates as said storage node; further wherein the transfer FET, said first NDR FET and said second NDR FET are formed in a common substrate.