Patent ID: 7287122
Filing Date: 2007-10-23
Classification: G06F

Abstract:
1. A method of managing a cache structure of a multiprocessor computer system having a plurality of cache lines distributed among multiple cache ways wherein affinity sets of the cache ways are associated with respective processors, comprising: detecting a read operation from a requesting processor for a given cache line; updating a line location set corresponding to the given cache line to indicate which of the cache ways contain the given cache line; instructing retrieval of the given cache line from a first cache way that is closest to the requesting processor and contains the given cache line; transmitting the given cache line to the requesting processor from the first cache way; concurrently with said transmitting, incrementing an access counter associated with the requesting processor for the given cache line to yield an incremented access count value; determining that the first cache way is in a first affinity set remote from the requesting processor; comparing the incremented access count value to a pre-established threshold to establish that the incremented access count value exceeds the pre-established threshold; determining a minimum access count value for all cache ways in a second affinity set proximate to the requesting processor; comparing the incremented access count value to the minimum access count value to establish that the incremented access count value exceeds the minimum access count value; and replicating the given cache line in a second cache way of the second affinity set wherein the second cache way contains a different cache line corresponding to the minimum access count value.