Patent ID: 7975093
Filing Date: 2011-07-05
Classification: G06F

Abstract:
1. An electronic circuit with a cache system comprising: a single-ported cache data memory; a first slot tag SRAM(Static Random Access Memory) and a second slot tag SRAM; a first slot address calculation logic circuit for calculating a first address for control of storing, in the single-ported cache data memory, first slot data for a first issue slot; a first slot tag arbiter that receives the first address from said first slot address calculation logic circuit for controlling access to the first slot tag SRAM; a second slot address calculation logic circuit for calculating a second store address for control of storing in, or loading from, the single-ported cache data memory, second slot data for a second issue slot; a second slot tag arbiter that receives the second address from said second slot address calculation logic circuit for controlling access to the second slot tag SAM; a cache write buffer configured for buffering the first slot data, and for buffering the second slot data in case of the storing of the second slot data in the single-ported cache data memory, and comprising: a first buffer input for receiving the first slot data; a second buffer input for receiving the second slot data; a buffer output for supply of the buffered first slot data and the buffered second slot data to the single-ported cache data memory.