Patent ID: 6080661
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for making reliable conductive vias in a semiconductor device that is fabricated over a semiconductor wafer, the semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, an oxide material is configured to cover a top surface of the polysilicon gate electrodes of the transistor devices, a silicon nitride layer is disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer, the method comprising:depositing a silicon nitride layer over the dielectric layer;etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired;pattering a photoresist mask over the silicon nitride layer, the photoresist mask having a plurality of windows defining all contacts to both selected ones of the diffusion regions and selected ones of the polysilicon gate electrodes, wherein some of the plurality of windows are defined over the nitride windows; andperforming a series of dielectric and silicon nitride etch operations to substantially simultaneously form via holes down to selected polysilicon gate electrodes and selected diffusion regions.