Patent ID: 6064223
Filing Date: 2000-05-16
Classification: H03K

Abstract:
A circuit, comprising:a subcircuit;a first switchable path coupled between a first power supply node and the subcircuit, the first switchable path having a first control input terminal;a second switchable path coupled between the subcircuit and a second power supply node, the second switchable path having a second control input terminal;wherein the first control input terminal is configured to receive a signal having a voltage that ranges between the voltage of the second power supply node and a voltage higher than the first power supply node, and the second control input terminal is configured to receive a signal having a voltage that ranges between a voltage lower than that of the second power supply node and the voltage of the first power supply node; andwherein the first switchable path comprises a PFET and the second switchable path comprises an NFET, and wherein the voltage that is higher than the first power supply voltage is approximately equal to the voltage required to drive the PFET into accumulation, and the voltage that is lower than the second power supply voltage is approximately equal to the voltage required to drive the NFET into accumulation.