Patent ID: 8842803
Filing Date: 2014-09-23
Classification: G09G,G11C

Abstract:
1. A shift register comprising a plurality of stages for sequentially generating outputs thereof, wherein each of the stages comprises: a set node; a reset node; a node controller controlling voltages at the set node and reset node in response to a carry pulse from an upstream stage and a carry pulse from a downstream stage; a carry output unit being controlled by the voltage at the set node and outputting the carry pulse to drive at least one of the downstream stage and the upstream stage; and a scan output unit being controlled by the voltages at the set node and the reset node, and outputting a scan pulse to drive a gate line, wherein the node controller of each of the stages comprises: a first switching device controlled by the carry pulse from the upstream stage and connected between a charging voltage line and the set node; a second switching device controlled by the carry pulse from the downstream stage and connected between the set node and a discharging voltage line; a third switching device controlled by the voltage at the reset node and connected between the set node and the discharging voltage line; and an inverter controlling the voltage at the reset node in response to the voltage at the set node, wherein each of the outputs generated from the stages comprises the carry pulse and the scan pulse, the carry pulse and the scan pulse being paired to correspond to each other, and wherein the paired carry pulse and scan pulse have different durations.