Patent ID: 6326273
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method for fabricating a gate structure for a field effect transistor on a semiconductor substrate, the method including the steps of:A. depositing a blocking layer on a top surface of said semiconductor substrate;B. etching a vertical opening in said blocking layer, said vertical opening having at least one sidewall of said blocking layer and having a bottom wall of said top surface of said semiconductor substrate;C. forming a respective spacer on each of said at least one sidewall of said vertical opening,wherein said respective spacer is substantially triangular in shape such that said respective spacer has a gradually smaller width toward the top of said vertical opening from the bottom of said vertical opening to form a trapezoidal opening having at least one sidewall of said respective spacer and a bottom wall of said top surface of said semiconductor substrate;D. filling said trapezoidal opening with a dielectric material that contacts said top surface of said semiconductor substrate at said bottom wall of said trapezoidal opening; andE. etching said dielectric material at a top portion of said trapezoidal opening with said dielectric material remaining at a bottom portion of said trapezoidal opening to form a gate dielectric of said field effect transistor, said gate dielectric having a trapezoidal shape with a larger width toward the top from the bottom of said gate dielectric, said bottom of said gate dielectric contacting said top surface of said semiconductor substrate;wherein said dielectric material remains to cover said semiconductor substrate at said bottom portion of said trapezoidal opening after said step E.