Patent ID: 6138257
Filing Date: 2000-10-24
Classification: G01R,G11C

Abstract:
An IC testing apparatus comprising:a main tester unit that tests an IC device for presence of a defect for each of a plurality of addresses thereof under predetermined test conditions and stores test results for individual ones of the addresses into a first memory;a curing analysis processing section that cures each of the addresses of the IC device determined as defective on the basis of the test results for the individual addresses stored in said first memory; anda defect analysis section that acquires, from said main tester unit, the test results for the individual addresses along with test condition data indicative of said predetermined test conditions to store the test results, the individual addresses, and the test condition data into a second memory, and analyzes a specific cause of a defect in the IC device on the basis of the test results for the individual addresses and the test condition data stored in said second memory.