Patent ID: 6781151
Filing Date: 2004-08-24
Classification: G01R,G05B

Abstract:
An integrated circuit testable serpentine staircase for an integrated circuit comprising a plurality of interconnect layers, said staircase comprising:a first power bus having a first axis; a second power bus parallel to said first axis; an input signal trace on a first layer disposed between said first power bus and said second power bus; a series of successive layers wherein each layer comprises an elongate first bus power trace extending substantially perpendicular from said first axis and electrically connected to said first power bus, an elongate second bus power trace extending substantially perpendicular from said first axis and electrically connected to said second power bus, and a signal trace disposed between said first power trace and said second power trace at a predetermined distance from said first power trace to said signal trace and at said predetermined distance from said second power trace to said signal trace, wherein said signal trace from one layer is connected to the signal trace of the next layer by a via, wherein said via does not have any other traces above said via, wherein at least a portion of said signal traces has no other traces above said signal trace, said signal traces adapted to be electrically connected to said input signal trace on said first layer, said signal traces further adapted to be electrically connected to each of said layers in succession from said first layer to an upper layer; and a plurality of test pads located on the top layer adaptable to probing wherein each of said test pads is electrically connected to said signal traces on each of said layers.