Patent ID: 8402328
Filing Date: 2013-03-19
Classification: G01R,G06F

Abstract:
1. An apparatus adapted for soft-error resilience in an integrated circuit or a system comprising a system circuit which includes at least a first latch, a shadow circuit which includes at least a second latch, and an output joining circuit which includes at least one of the following elements: a transmission gate, a C-element, an XOR gate, an error detection circuit, or a third circuit coupled to a majority voter; at least a data input signal and at least a system clock driving both the system circuit and the shadow circuit; the shadow circuit including at least a duplicate of the system circuit; the apparatus further comprising a slow-speed snapshot circuit in the shadow circuit for performing a functional testing using slow-speed snapshot by capturing the data input signal from the system circuit into the shadow circuit selectively at the system clock frequency or at a reduced shift clock frequency or at a reduced shift clock frequency, and then shifting out at least the captured data signal at the reduced shift clock frequency (called slow-speed) when the system clock is still running.