Patent ID: 6303455
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method for manufacturing a capacitor, which is suitable for a substrate with a memory cell region and a peripheral circuit region, wherein the memory cell region has an isolation structure therein, comprising the steps of:forming a gate oxide layer over the substrate apart from the isolation structure in the memory cell region;forming a first polysilicon layer over the substrate;forming a dielectric layer on the first polysilicon layer;forming a second polysilicon layer on the dielectric layer;patterning the second polysilicon layer, wherein the residual second polysilicon layer is above the isolation structure;patterning the dielectric layer by using the residual second polysilicon layer as a mask;patterning the first polysilicon layer and the gate oxide layer to form respectively a bottom electrode of the capacitor above the isolation structure and a polysilicon gate in the peripheral circuit region, wherein a width of the bottom electrode is larger than that of the residual second polysilicon layer;forming spacers on sidewalls of the polysilicon gate, the residual second polysilicon layer and the bottom electrode, wherein a portion of a top surface of the bottom electrode is exposed; andforming a first suicide layer and a second silicide layer on the bottom electrode and the polysilicon gate, respectively.