Patent ID: 6081452
Filing Date: 2000-06-27
Classification: G11C

Abstract:
A semiconductor storage device comprising:a memory cell array having nonvolatile memory cells in which control gates and drains of a plurality of memory cell transistors each having a floating gate are connected to word lines and bit lines arranged in a matrix form;a row decoder circuit which selects between the word lines of the memory cell array;a column decoder circuit which selects between the bit lines of the memory cell array;a sense amplifier which outputs a detection signal upon detecting an event that an inputted voltage or current has exceeded a reference value;a common bit line connected to an input terminal of the sense amplifier;a switching circuit which receives a verify selection signal and connects the bit lines of the memory cell array to the common bit line according to the verify selection signal; anda pre-charging circuit which pre-charges the common bit line with a specified voltage.