Patent ID: 8176463
Filing Date: 2012-05-08
Classification: G06F,Y02P

Abstract:
1. A method of designing a circuit, comprising: specifying a plurality of layout styles for devices, wherein each layout style includes values that specify geometrical constraints for arranging devices and one or more correlation coefficients for statistical simulation parameters that characterize device-matching corresponding to the geometrical constraints; specifying a schematic for the circuit, wherein the schematic includes devices, connections between devices, and electrical parameters that specify electrical properties of the devices; determining a layout for the circuit from the schematic by specifying sizes of the devices and an arrangement of the devices, wherein determining the layout includes using a computer to select layout styles for one or more devices in the circuit schematic; and evaluating one or more performance metrics for the layout by using the computer to simulate circuit performance with device models that are statistically correlated according to the specified layout styles.