Patent ID: 8824183
Filing Date: 2014-09-02
Classification: G11C,H01L

Abstract:
1. A memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate, the memory further comprising: a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes; a plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line pillars and the word lines adjacent the crossings thereof; a plurality of global conductive lines in the y-direction; a row of pillar select devices in the x-direction below a selected row of bit line pillar in the x-direction arranged to switch the selected row of bit line pillars to corresponding global conductive lines in the y-direction; and wherein: each pillar select device is a transistor above the semiconductor substrate and vertically aligned to a corresponding bit line pillar in the selected row of hit line pillars in the z-direction; and wherein: said plurality of parallel planes stacked in the z-direction has a top surface and a bottom surface; and a word line in a plane is accessed from the top surface via a conductive riser column connected to the word line.