Patent ID: 7436923
Filing Date: 2008-10-14
Classification: G09G,G11C,H03K

Abstract:
1. A shift register circuit comprising: first and second input terminals and an output terminal; first and second voltage-signal terminals each receiving a predetermined voltage signal; first and second clock terminals each receiving a clock signal with a different phase from the one inputted to the other; a first transistor supplying a first clock signal inputted to said first clock terminal, to said output terminal; a second transistor discharging said output terminal; a third transistor having a control electrode connected to said first input terminal and supplying a first voltage signal inputted to said first voltage-signal terminal, to a first node connected to a control electrode of said first transistor; a fourth transistor having a control electrode connected to said second input terminal and supplying a second voltage signal inputted to said second voltage-signal terminal, to said first node; a first pull-down circuit discharging said first node in response to activation of said first clock signal; and a second pull-down circuit discharging said first node in response to activation of a second clock signal inputted to said second clock terminal, discharge of said first node by said first and second pull-down circuits is performed during a period when said first node is not charged, and it is not performed during a period when said first node is charged.