Patent ID: 6384437
Filing Date: 2002-05-07
Classification: H01L

Abstract:
Dynamic random access memory (DRAM) cells on and in an epitaxial silicon layer over an insulating layer on a semiconductor substrate comprised of:a shallow trench isolation around device areas having recesses over and aligned to said device areas; said insulating layer on said substrate in said recesses, each of said recesses having an opening in said insulating layer to said substrate; an epitaxial layer in each of said recesses extending from said opening and laterally over said insulating layer; a gate oxide on said epitaxial layer in each of said recesses; FET gate electrodes on said gate oxide and over said openings in said insulating layer, and including lightly doped source/drain areas and source/drain contact areas in said epitaxial layer adjacent to said gate electrodes; capacitor node contacts to said source/drain contact areas in said epitaxial layer over said insulating layer; bit line contacts in said epitaxial layer over said insulating layer; capacitors over and contacting said capacitor node contacts, and bit lines over and contacting said bit line contacts.