Patent ID: 8332607
Filing Date: 2012-12-11
Classification: G06F,Y02D

Abstract:
1. A non-volatile memory storage device, comprising: a non-volatile memory having a plurality of memories; and a controller coupled to the plurality of memories of the non-volatile memory, comprising: a plurality of control circuits each being configured to generate a request to update chip-enable (CE) signals for the plurality of memories of the non-volatile memory, wherein each of the chip-enable (CE) signals is sent to at least one of the plurality of memories of the non-volatile memory for enabling the at least one of the memories of the non-volatile memory; and an arbitration circuit coupled with the plurality of control circuits and configured to determine when the requests transmitted from the plurality of control circuits are acknowledged by interleaving the timing of acknowledge signals sent to the plurality of control circuits; wherein the plurality of control circuits update the CE signals for the plurality of memories of the non-volatile memory when receiving the acknowledge signals.