Patent ID: 7263154
Filing Date: 2007-08-28
Classification: G11B,H03L

Abstract:
1. A method for enabling fast clock phase locking in a phase-locked loop, the phase-locked loop including a phase detector for receiving an input digital signal associated with a rewritable digital versatile disc and an input phase-locking clock signal, and a voltage controlled oscillator that generates an oscillator output, said method comprising the steps of: (a) in response to the oscillator output, obtaining multiple sampling points of the input digital signal, wherein temporally adjacent ones of the sampling points are spaced apart from each other by an interval; (b) comparing logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal; and (c) providing an adjusted input phase-locking clock signal for replacing a current input phase-locking clock signal to the phase detector, the adjusted input phase-locking clock signal corresponding to one of the sampling points in the temporally adjacent pair that was detected to have the logic level transition occurring in the interval of the temporally adjacent pair.