Patent ID: 7099199
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus comprising: a plurality of memories; and a processing unit, wherein each of said memories has a terminal used for data input and for data output, said terminal of each of said memories are coupled to each other by a bus, wherein one of said memories is a nonvolatile memory and is capable of being specified a plurality of operations from said processing unit, wherein said nonvolatile memory operates an erase operation for erasing data stored therein, said erase operation is included in said operations specified from said processing unit, and said nonvolatile memory is capable of freeing said terminal during said erase operation, wherein said erase operation includes a threshold voltage moving operation and a verify operation, wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in said nonvolatile memory is moved to within a threshold voltage distribution indicative of an erase level, wherein said verify operation determines whether the threshold voltage movement of said memory cell to within said threshold voltage distribution is completed, wherein said nonvolatile memory repeats said erase operation when the threshold voltage movement of said memory cell to within said threshold voltage distribution is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase level, and wherein said processing unit is capable of accessing other ones of said memories via said bus during a time said erase operation is being performed in said nonvolatile memory.