Patent ID: 6175257
Filing Date: 2001-01-16
Classification: G06F,H04L

Abstract:
An integrated circuit comprising:a first clock circuit for providing a first clock signal;a second clock circuit for providing a second clock signal, said second clock circuit being independent of said first clock circuit;a master circuit having a clock input for receiving the first clock signal, and an output for providing a control signal activated during an active edge of the first clock signal;a slave circuit having a control input, and a clock input for receiving the second clock signal;a first register having a clock input for receiving the second clock signal, a data input for storing the control signal during an active edge of the second clock signal, and an output connected to the control input of said slave circuit; anda second register having a clock input for receiving the first clock signal, a data input connected to the output of said first register for storing the control signal during an active edge of the first clock signal, and an output.