Patent ID: 6044446
Filing Date: 2000-03-28
Classification: G06F

Abstract:
In a multi-processor shared memory system with each processor having a private cache, an improved system for maintaining coherency between the caches comprising:a query bus coupling the processors for transmitting query bus transactions when a virtual address referencing a page in memory is generated by a first one of said processors;an address translation system, coupled to said first one of said processors, including table entries translating a virtual address to a physical address, with each table entry including an unshared bit which is set to indicate that a page addressed by a physical address has not been shared by a plurality of processors; anda querying system, coupled to said processors and said query bus, for generating query transactions on said query bus when reference to a particular page indicated by a particular virtual address is made by the first processor and the particular page is not located in the private cache of the first processor unless the unshared bit in the table entry corresponding to the particular virtual address is set.