Patent ID: 8575742
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a generally planar die pad defining multiple peripheral edge segments; a plurality of power bars arranged to at least partially circumvent the die pad in spaced relation thereto; a plurality of first leads disposed in spaced relation to the power bars and the die pad, the first leads being positioned inwardly of the power bars between the power bars and the die pad, with at least some of the first leads being electrically isolated from the die pad; a plurality of second leads disposed in spaced relation to and positioned outwardly of the power bars, each of the second leads including first and second downsets formed therein in spaced relation to each other; a plurality of third leads disposed in spaced relation to and positioned outwardly of the power bars, at least some of the third leads including a downset formed therein; a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second and third leads, and to at least one of the power bars; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads, the power bars, and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die pad, the first leads and the second leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the third leads protrude from at least one of the side surfaces of the package body.