Patent ID: 7919793
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting said plurality of standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with said metallic wiring layer and arranged on a periphery of said plurality of standard cells, wherein each of the gate electrodes of said plurality of standard cells and said plurality of reserve cells has a gate pad section and two gate finger sections extending from said gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of said plurality of reserve cells in a direction orthogonal to said predetermined direction is equal to or more than a sum total value of three times a minimum line width in said metallic wiring layer and twice a minimum separation distance.