Patent ID: 6260135
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A parallel processing unit comprising:a plurality of execution blocks for executing a plurality of instructions in parallel, each execution block being capable of receiving an instruction in a sequence;a dispatch unit for dispatching an instruction with source information to said execution blocks when that instruction is ready to be executed, said source information includes:source data to be processed; andregister identification of resultant data to identify a register that said resultant data is stored;a plurality of registers connected to said dispatch unit, for storing the source data and outputting the source data to said dispatch unit; anda data forwarding path connecting said execution blocks and said dispatch unit, for bypassing said registers;wherein said dispatch unit comprises:a source information holder having:a first register identification storing unit for storing a register identification of source data;a second register identification storing unit for storing a register identification of resultant data;a source data storing unit for storing said source data; andan execution block number storing unit for storing an execution block identification;an address selector connected to said execution block number storing unit and said plurality of execution blocks, wherein said address selector inputs a plurality of resultant data addresses from said execution blocks and outputs one of said resultant data addresses based on said execution block identification; anda comparator connected to said source data storing unit and said address selector, wherein said comparator compares source register identification stored in said source data storing unit with selected resultant data addresses,wherein said dispatch unit writes data from said execution block corresponding to said execution block identification to said source data storing unit.