Patent ID: 7170960
Filing Date: 2007-01-30
Classification: H03K,H03L,H04L

Abstract:
1. A clock recovery circuit, comprising: a Josephson transmission line forming an oscillator loop and having a length of 2T, where T is equal to one clock period; first and second data inputs spaced apart from one another on the oscillator loop by a distance of T for injecting at least one data pulse onto the oscillator loop; a pulse generator for injecting an initial pulse onto the oscillator loop that circulates as a clock pulse and is output as periodic clock signals; first and second output taps spaced apart from one another on the oscillator loop for receiving the clock pulse and the data pulse in the oscillator loop; and a clock output tap for outputting the clock pulse as the periodic clock signals; wherein when the data pulse is input into the oscillator loop, a clock phase is instantaneously reset.