Patent ID: 8224883
Filing Date: 2012-07-17
Classification: G06F

Abstract:
1. A processor circuit adapted to execute a packed half-word addition and subtraction operation upon a pair of selected operands, the processor circuit comprising: an arithmetic logic unit (ALU) having adder circuitry configurable to be selectively split into two half-word adders, each half-word adder being independently selectable to perform either an addition or subtraction operation upon operands received at respective operand inputs to said half-word adders, the ALU having access to a register file having a set of selectable registers with top and bottom half-word storage locations, the half-word adders of the ALU having outputs selectively coupled to respective top and bottom half-word storage locations of an instruction-designated destination register in the register file; and a set of multiplexers coupled between the register file and the operand inputs of the half-word adders of the ALU, the set of multiplexers being configured to select, in response to instruction-determined control signals, a first operand input from a designated top or bottom half-word of a designated first source register of the register file and a second operand input from a designated top or bottom half-word of a designated second source register of the register file, the designated second source register not necessarily the same as the designated first source register; wherein the set of multiplexers includes a first set of multiplexers responsive to a top or bottom control signal for selection between top and bottom half-word operands from the designated first and second source registers; and wherein the set of multiplexers further comprises a second set of multiplexers responsive to a half-word/full-word control signal for selection between half-word and full-word operands from the designated first and second source registers.