Patent ID: 6153513
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of fabricating a self-aligned capacitor of a DRAM cell, wherein a landing pad is formed on a semiconductor substrate, the method comprising the steps of:forming a first insulating layer on the landing pad and the semiconductor substrate;patterning and removing part of the first insulating layer to expose the semiconductor substrate;forming and patterning a bit line after the landing pad is formed on the semiconductor substrate and a second insulating layer on the first insulating layer and the semiconductor substrate;forming and patterning a third insulating layer on the first insulating layer and the second insulating layer, wherein a via hole is formed in the third insulating layer to expose the landing pad;forming and etching back a fourth insulating layer to form spacers on the sidewalls of the via hole; andforming a conductive layer in the via hole to form a bottom electrode of a capacitor.