Patent ID: 7903070
Filing Date: 2011-03-08
Classification: G09G

Abstract:
1. An apparatus for driving a liquid crystal display device comprising: a display area which includes a plurality of liquid crystal cells in portions defined by a plurality of gate and data lines; a gate driver which supplies overlapped gate pulses to the adjacent gate lines; a data driver which supplies a data voltage to the data line in synchronization with the gate pulse; and a timing controller which controls an overlapped section of the gate pulses supplied to the adjacent gate lines using a plurality of gate shift clocks, wherein the overlapped section of the gate pulse supplied to the adjacent gate lines is less than the half width of each gate pulse when the polarities of the data voltages supplied to the adjacent liquid crystal cells corresponding to the adjacent gate lines are inversion, wherein the timing controller includes a clock signal generator which generates the plurality of gate shift clocks shifted in sequence and overlapped by less than the half of one horizontal period between the adjacent gate shift clocks, wherein the clock signal generator includes: a reference clock generator which generates a plurality of reference clocks shifted in sequence and overlapped by the half of the one horizontal period between the adjacent reference clocks, wherein each of the plurality of reference clocks has the same pulse width as the one horizontal period; a width modulation signal generator which generates a plurality of width modulation signals to control the overlapped section of the gate pulses, wherein each of the plurality of width modulation signals corresponds to each reference clock and overlaps a first period of the corresponding reference clock; and a logic operation unit which generates the plurality of gate shift clocks by a logic operation of the reference clock and the width modulation signal, wherein each of the plurality of gate shift clocks corresponds to each reference clock and overlaps a second period of the corresponding reference clock, wherein the second period is subtracting the first period from a pulse width of the corresponding reference clock.