Patent ID: 9025716
Filing Date: 2015-05-05
Classification: H04L

Abstract:
1. An inter-integrated circuit slave interface, comprising: a data line; and a clock line, the clock line having a first input buffer and the data line having a second input buffer and an output buffer, the data line for transmission of a data input signal and a data output signal, and the clock line for the transmission of a clock signal, wherein the clock line has a first delay element, and the data line has a second delay element and a third delay element, the first delay element being configured to delay an ascending flank of the clock signal by a first time and a descending flank of the clock signal by a second time, the second delay element being configured to delay an ascending flank of the data input signal by a third time and a descending flank of the data input signal by a fourth time, and the third delay element being configured to delay an ascending flank of the data output signal by a fifth time and a descending flank of the data output signal by a sixth time.