Patent ID: 6594609
Filing Date: 2003-07-15
Classification: G01R

Abstract:
An apparatus in a semiconductor test system for generating test vectors for a normal test of semiconductor devices and scan vectors for a scan test of semiconductor devices, comprising:an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from a predetermined reference point with use of N data bits in parallel, thereby defining one test vector, wherein the N data bits are divided into two fields of the timing data, one for defining an integer multiple of a reference clock, and another for defining a fraction of the reference clock; an event generator for generating an event with use of the timing data and the event type data from the event memory where each event is used as a test vector or a scan vector; and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors, the mode change circuit detecting the scan mode when the event type data from the event memory indicating a predetermined word; wherein each bit of the N data bits in the event memory defines each scan vector, and the N data bits read from the event memory in parallel are converted to a serial form by said mode change circuit and are provided to the event generator, thereby producing 2N scan vectors at each access of the event memory.