Patent ID: 7307871
Filing Date: 2007-12-11
Classification: G11C

Abstract:
1. A method of fabricating an SRAM cell having pair of cross-coupled inverters, the method comprising: preparing a coat of layer of silicide material on a selective portion of a first gate structure of a first and second MOS transistors included in a first inverter, wherein the selective portion of the first gate structure includes a gate of the second MOS transistor and a selective portion of a gate of the first MOS transistor; preparing a coat of a layer of silicide material on a selective portion of a second gate structure of the third and fourth MOS transistors, wherein the selective portion of the second gate structure includes a gate of the fourth MOS transistor and a selective portion of a gate of the third MOS transistor; connecting a remaining portion of the gate of the first MOS transistor that is substantially void of the silicide material to a drain of a third MOS transistor and a drain of a fourth MOS transistor included in a second inverter, wherein the remaining portion that is substantially void of the silicide material is disposed above a shallow trench isolation (STI) region near an edge of the gate of the first MOS transistor; and connecting a portion of the gate of the third MOS transistor that is substantially void of the silicide material to a drain of the first MOS transistor and drain of the second MOS transistor, wherein the remaining portion of the gate of the third MOS transistor that is substantially void of the silicide material is disposed above a shallow trench isolation (STI) region near an edge of the gate of the third MOS transistor.