Patent ID: 9069598
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A computer program product comprising a memory storing program instructions for execution by a computer system, wherein the program instructions are program instructions of a hypervisor for managing multiple logical partitions executing within a processor core, wherein the program instructions comprise: program instructions of an interrupt handler to, responsive to a trap interrupt generated upon access to a register containing hardware-thread specific information, transform the hardware thread-specific information in the register to reflect an exclusive use of the processor core by a given logical partition by generating a logical register value that is different than an actual value in the register; and program instructions of the interrupt handler to replace a return value for the access to the register containing hardware thread-specific information with the logical register value, wherein the hardware thread-specific information is a value dependent on a logical hardware thread number of a particular hardware thread assigned to the given logical partition and specified by the access to the register, and wherein the program instructions of the interrupt handler that transform the hardware thread-specific information in the register comprise program instructions for generating an actual hardware thread number from the logical hardware thread number and retrieving the hardware thread-specific information for the particular hardware thread using the actual hardware thread number, wherein the program instructions that replace the return value replace the return value with the retrieved hardware thread-specific information, wherein the hardware thread-specific information is the hardware thread number of the hardware thread performing the access, and wherein the program instructions for generating subtract a base thread number for the given logical partition to generate the actual hardware thread number.