Patent ID: 7917733
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. An instruction code compression method for reducing a number of instruction codes in a computer, the computer including an operation circuit that sequentially decodes and executes instruction codes composed of an upper bit group including operational codes, and a lower bit group including operands and having a same number of bits as the upper bit group, wherein reuse flags are provided in the lower bit group, and wherein, when 2N+1 (N is an integer of 1 or more) instruction codes having a same upper bit group continues in a series of instruction codes, respective reuse flags of the lower bit group of a 2n-th (n is an integer of 1 or more and N or less) instruction code and a (2n+1)-th instruction code in the series of instruction codes are set, and the lower bit groups of the 2n-th and (2n+1)-th instruction codes are integrated into one compressed instruction code.