Patent ID: 7643533
Filing Date: 2010-01-05
Classification: G01S,H04B,H04L

Abstract:
1. An ultra wide bandwidth timing generator, comprising: a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; and a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit, wherein the high frequency clock generation circuit generates a plurality of high frequency clock signals, the low frequency control generation circuit generates a plurality of low frequency control signals, and the modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals, wherein the high frequency clock generation circuit is configured to receive at least one of