Patent ID: 6762102
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, the method comprising the steps of:(a) forming a gate dielectric layer; (b) forming a first conductive layer having a specified pattern on the gate dielectric layer; (c) forming sidewall spacers on side walls of the first conductive layer; (d) depositing an insulation layer that covers the first conductive layer and the sidewall spacers; (e) planarizing the insulation layer until an upper surface of the first conductive layer is exposed; (f) removing a part of the first conductive layer in a manner so that the gate dielectric layer is not exposed, to thereby form a recessed section in the first conductive layer; and (g) filling a second conductive layer in the recessed section to form a gate electrode that includes at least the first conductive layer and the second conductive layer.