Patent ID: 6713333
Filing Date: 2004-03-30
Classification: H01L,Y10S

Abstract:
A method for fabricating a MOSFET comprising the steps of:forming a first insulation layer over a semiconductor substrate; selectively forming a trench in said first insulation layer to define a part of said semiconductor substrate as a gate formation region, said gate formation region having a central portion and end portions sandwiching said central portion; injecting oxidation enhancing impurities into said end portions of said gate formation region while suppressing injection of said oxidation enhancing impurities into said central portion of said gate formation region; forming a second insulation layer on said gate formation region, said second insulation layer thereby having a first part on said central portion of said gate formation region and second parts on said end portions of said gate forming region which are larger in thickness than said first part; forming a gate electrode on said second insulation layer; and forming source and drain regions by using said gate electrode as a mask so that each of said source and drain regions is formed in contact with an associated one of said end parts of said second insulation layer.