Patent ID: 7095885
Filing Date: 2006-08-22
Classification: G06T

Abstract:
1. A method for measuring the registration between at least two integrated circuit layers, one residing over the other, said method comprising: generating a top-down image of a field of said at least two integrated circuit layers, each of said layers having a respective visible feature in said image; digitizing said image and processing said digitized image to determine a relative location of said visible feature of one of said layers, relative to said visible feature of the other of said layers; determining a location of a first feature reference point in said visible feature of one of said layers, and a location of a second feature reference point in said visible feature of the other of said layers, to indicate a relative location, wherein at least one of said visible features is a non-metrological structure on said one of said integrated circuit layers; and determining if said relative location is within stored acceptable design limits for said integrated circuit layers by comparing said relative location to said stored acceptable design limits.