Patent ID: 6310800
Filing Date: 2001-10-30
Classification: G11C,H01L

Abstract:
A non-volatile semiconductor memory device comprising, on a semiconductor substrate, a plurality of memory cells arranged in a matrix, a plurality of word lines extending in a row direction, a plurality of source lines extending in the row direction, and a plurality of bit lines extending in a column direction,wherein a plurality of memory cells belonging to a certain row are connected to a first source line among the plurality of source lines,a plurality of memory cells belonging to a row adjacent to the certain row are connected to a second source line among the plurality of source lines, andthe first source line is electrically independent from the second source line, the non-volatile semiconductor memory device further comprising:means for applying a first voltage having a polarity reverse-biased with respect to the semiconductor substrate to a bit line to which a selected memory cell of the plurality of memory cells belongs;means for applying a second voltage having the same polarity as the first voltage to a word line to which the selected memory cell belongs;means for applying a third voltage having the same polarity as the first voltage to all of the source lines to which memory cells other than the selected memory cell belong; andmeans for applying an electric potential of the semiconductor substrate to the source line to which the selected memory cell belongs, thereby putting the threshold voltages of the memory cells other than the selected memory cell into an enhancement state.