Patent ID: 7777523
Filing Date: 2010-08-17
Classification: H03K

Abstract:
1. A flip-flop, comprising: a data input line carrying a logical value represented by a first voltage range, the first voltage range between a reference voltage and a first power supply rail; a data complement line connected to the data input line through an inverter, wherein the inverter is connected to the first power supply rail; first and second transistors, the first transistor connected to the data input line and the second transistor connected to the data complement line; first and second pre-charge nodes, the first pre-charge node connected to the first transistor and the second pre-charge node connected to the second transistor; a first keeper transistor connected to the first transistor, wherein the ratio of the width of the first transistor to the width of the keeper transistor is between 8 to 1 and 4 to 1; a clock line operable to trigger a capture of the logical value carried by the data input to form a captured logical value; and a data output line carrying the captured logical value represented by a second voltage range, the second voltage range between the reference voltage and a second power supply rail, wherein the capture of the logical value includes a discharge of one of the first and second pre-charge nodes by a path to ground through one of the first and second transistors by one of the data input and data complement lines; wherein the second power supply rail is greater than the first power supply rail.