Patent ID: 6281831
Filing Date: 2001-08-28
Classification: H03M

Abstract:
An analog to digital converter for generating a digital data of a plurality of bits from a most significant bit (MSB) to a least significant bit (LSB) in response to an analog input voltage comprising:(a) a plurality of thresholding circuits corresponding to said bits of said digital data, each said thresholding circuit comprising an odd number of inverters serially connected from a first stage to a last stage, said first stage inverter of each said thresholding circuit having a threshold equal to a weight of said corresponding bit;(b) a plurality of weighting circuits connected to inputs of thresholding circuits of bits other than said MSB, each said weighting circuit receiving said analog input voltage and one or more outputs from said thresholding circuits corresponding to higher bits than said bit corresponding to said weighting circuit, said analog input voltage being weighted by a weight corresponding to said bit of said thresholding circuit, each said output being weighted by a ratio of a weight corresponding to bit of said weighting circuit; and(c) said inverters of said first stage and said last stage having different thresholds.