Patent ID: 6204144
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method of forming a metal capacitor with two metal electrodes on a substrate of a semiconductor wafer, the semiconductor wafer comprising a gate area for a gate electrode, a source/drain area for a source/drain electrode, and a capacitor area for the metal capacitor, the method comprising the following steps:(a) forming a first insulating layer to cover the substrate;(b) patterning the first insulating layer to form at least a contact hole to expose the source/drain area;(c) conformably forming a barrier metal layer on the surface of the contact hole and the first insulating layer;(d) forming a metal plug in the contact hole;(e) forming a dielectric layer on the surface of the metal plug and the barrier metal layer;(f) patterning the dielectric layer for exposing predetermined areas of the barrier metal layer to form a dielectric plate with an area larger than that of the capacitor area;(g) forming a metal layer on the surface of the dielectric plate, the metal plug and the barrier metal;(h) patterning the metal layer to expose a predetermined area of the surface of the dielectric plate and predetermined areas of the surface of the first insulating layer to separately form a top electrode plate on the surface of the dielectric plate inside the capacitor area, a bottom electrode plate composed of the barrier metal layer under the dielectric plate, and a metal line; and(i) forming a second insulating layer for isolating the top electrode plate, the bottom electrode plate and the metal line.