Patent ID: 6262607
Filing Date: 2001-07-17
Classification: H03K

Abstract:
An output buffer circuit comprising:an input terminal;an inverter having an input connected to the input terminal;an output unit having a CMOS configuration; anda correction unit, arranged between a said input terminal and said output unit, for temporarily decreasing a signal output to said output unit when an input signal at said input terminal rises from a relatively low first potential level to a relatively high second potential level and for temporarily raising the signal output to said output unit when the input signal at said input terminal falls from the relatively high second potential level to the relatively low first potential level, said correction unit includinga selector circuit having a first input connected to said input terminal, a second input connected to an output of said inverter, an output terminal connected to an input of said output unit, and a control terminal receiving a control signal for controlling a signal output by said selector circuit at the output of said selector circuit;an exclusive OR circuit connected at a first input to the output of said inverter, a first delay circuit receiving a signal output by said exclusive OR circuit and connected at an output to the control terminal of said selector circuit; anda second delay circuit connected between the output of said inverter and a second input of said exclusive OR circuit.