Patent ID: 6878591
Filing Date: 2005-04-12
Classification: H01L

Abstract:
1. A method of making an electrically erasable programmable memory cell, the method comprising the steps of: forming a first layer of polysilicon disposed over and insulated from a semiconductor substrate of a first conductivity type; forming a block of insulation material over the first polysilicon layer which leaves portions of the first polysilicon layer exposed; removing the exposed portions of the first polysilicon layer to form a floating gate underneath the block of insulation material; forming a block of polysilicon that is disposed over and insulated from the substrate and is disposed adjacent to and insulated from the floating gate, wherein the formation of the polysilicon block includes a planarization etch for planarizing an upper surface of the polysilicon block using an upper surface of the insulation material block as a planarization etch stop; and forming spaced apart first and second regions in the substrate that have a second conductivity type, with a channel region defined in the substrate between the first and second regions.