Patent ID: 6028613
Filing Date: 2000-02-22
Classification: G06F,G06T

Abstract:
A system for rendering graphics primitives during a burst write cycle operation, the system comprising:a system bus for communicating data and instructions and generating burst write cycles;a host processor coupled to the system bus for generating graphics primitive address requests to the system bus;a system memory coupled to the system bus for storing a display list of parameters responsive to the graphics primitives;a graphics subsystem coupled to the system bus for processing the graphics primitives address requests generated by the host processor, the graphics subsystem including decode logic, the decode logic having therein a command register and a register file for storing parameter values at sequential addresses in the register file, wherein an addresses stored in the register file are sequentially stored without reference to the physical graphics primitive address values generated by the host processor; anda display unit coupled to the graphics subsystem for displaying the graphics primitives corresponding to the addresses generated by the host processor.