Patent ID: 7996652
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A processor architecture, comprising: a plurality of elements arranged in an array comprising rows and columns; a plurality of first bus pairs, each first bus pair being located between different adjacent rows of the array and including a respective first bus running in a first direction and a respective second bus running in a second direction opposite to the first direction; and a plurality of second bus pairs, each second bus pair being located between different adjacent columns of the array and including a respective third bus running in a third direction and a respective fourth bus running in a fourth direction opposite to the third direction, the third and fourth buses intersecting the first and second buses; wherein each element of the array, which is not at an edge row of the array, is configured so as to be able to receive data from a respective first bus of said bus pairs and from a respective second bus of a different one of said bus pairs, and is configured so as to be able to transfer data to said respective first bus of one of said bus pairs and to said respective second bus of said different one of said bus pairs and further comprising a plurality of switch matrices, each switch matrix being located at an intersection of one of said first bus pairs and one of said second bus pairs, configured to have inputs for each of said first, second, third and fourth buses and outputs for each of said first, second, third and fourth buses and switch elements for switchably connecting said inputs to said outputs.