Patent ID: 7363606
Filing Date: 2008-04-22
Classification: G06F

Abstract:
1. A method for inserting flip-flop (flop) in an interconnect (net) between logic blocks of an integrated circuit design to ensure that a cycle time constraint for the net is satisfied, comprising: inserting a flop at an initial placement at a node along a signal path of the net such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net; and optimizing the initial placement of the flop by moving the flop from the initial placement to an optimal placement at a downstream node such that a delay difference, of a downstream delay minus an upstream delay, relative to the optimal placement is not greater than a number zero, wherein the optimal placement of the flop is derived by moving the flop downstream from the initial placement to one or more preliminary optimal placements at one or more nodes located downstream from the initial placement of the flop and upstream from the optimal placement of the flop, wherein at each preliminary optimal placement determining whether each delay difference relative to each preliminary optimal placement is not greater than number zero, and if a delay difference relative to a preliminary optimal placement at a node is greater than a number zero, moving the flop to a next preliminary optimal placement at an adjacent downstream node, else identifying the node to be the optimal placement of the flop.