Patent ID: 6278755
Filing Date: 2001-08-21
Classification: H04L

Abstract:
A bit synchronization circuit comprising:clock generating means for generating a plurality of clocks having respective different phases from a reference clock;clock selecting means for alternatively selecting one of said plurality of clocks based on an extracted phase value indicative of either one of said phases;latch means for latching input data with the clock selected by said clock selecting means;edge detecting means for detecting an edge of said input data;storage means for storing accumulated edges detected by said edge detecting means as phase information;jitter range detecting means for detecting positive and negative ends of a jitter range from the phase information accumulatively stored by said storage means;center phase calculating means for calculating a central phase of an eye pattern from the positive and negative ends of the jitter range which have been detected by said jitter range detecting means; andextracted phase value updating means for updating said extracted phase value depending on a result of comparison of the central phase of the eye pattern calculated by said center phase calculating means and said extracted phase value at the, time the central phase of the eye pattern is calculated.