Patent ID: 6044455
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A central processing unit for performing a pipeline process by dividing a sequence including reading, decoding and executing an instruction into different stages, comprising:a plurality of registers;an arithmetic and logic unit for performing a computation using an operand for an instruction to be executed,an adder dedicated to address calculation provided separately from said arithmetic and logic unit so as to calculate an address of said operand;a first data route electrically connected at least between at least one of said plurality of registers and said adder for transferring data stored in a specific one of said plurality of registers to said adder;a second data route electrically connected at least between an immediate address que and said adder for transferring an immediate address of the instruction to be executed set in said immediate address que to said adder;a predecoder for determining whether said address of said operand for said instruction can be calculated by adding said immediate address to the data stored in said specific register, wherein when said predecoder yields an affirmative answer, the data stored in said specific register is transferred to said adder via said first data route, and said immediate address is transferred to said adder via said second data route, so as to cause said adder to calculate said address based on the data and said immediate address transferred to said adder.