Patent ID: 8375265
Filing Date: 2013-02-12
Classification: G01R

Abstract:
1. A non-transitory computer readable medium carrying one or more sequences of instructions for causing a digital processing system to facilitate testing of an integrated circuit, wherein execution of said one or more sequences of instructions by one or more processors contained in said digital processing system for testing said integrated circuit causes said digital processing system to perform the actions of: disabling a phase-locked loop (PLL) clock connected to distributed clock dividers; shifting a first set of test data from an on-chip test control circuit into scan chains; generating delay fault testing (DFT) code from the on-chip test control circuit; transmitting the DFT code to the distributed clock dividers; enabling the PLL clock to the distributed clock dividers; generating launch pulses in the distributed clock dividers that are selected by the DFT code wherein the launch pulses are sent to test circuits in clock domains that contain the selected distributed clock dividers; generating capture pulses in the distributed clock dividers that are selected by the DFT code wherein the capture pulses are sent to test circuits in clock domains that contain the selected distributed clock dividers; capturing a second set of test data in scan chains; disabling the PLL clock to the distributed clock dividers; shifting the second set of test data from the scan chains to the on-chip test control circuit.