Patent ID: 7188041
Filing Date: 2007-03-06
Classification: G01R,G06F

Abstract:
1. A system configured to verify a device under test comprised of hardware description language logic, said system comprising: a test case of a testbench executing within a master thread; a generator executing within a sub-thread of the master thread, wherein said generator is configured to create test vectors to be provided to the device under test; at least one additional module executing within at least one additional sub-thread of the master thread, wherein said at least one additional module interacts with the device under test and indicates behavior of the device under test resulting from application of the test vectors; and a command queue configured to store a plurality of commands registered by the master thread, wherein said generator obtains individual ones of the plurality of commands from said command queue for execution, wherein said generator creates the test vectors to be provided to the device under test responsive to execution of individual ones of the plurality of commands from the command queue, wherein said generator modifies the content of said command queue during execution of at least one of the plurality of commands.