Patent ID: 8327218
Filing Date: 2012-12-04
Classification: G06F,G11C

Abstract:
1. A storage device comprising: memory cells array, comprising a plurality of memory cells, said memory cells divided into a plurality of memory pages, at least two of said memory pages stored by a same group of memory cells; and at least two error correction modules, providing a plurality of Error Correction Code (ECC) with different error correction capability for data on said memory pages of said same group of memory cells; wherein one of said error correction modules provides long-bit ECC for Least Significant Bit (LSB) pages in the same group of memory cells; wherein one of said error correction modules provides short-bit ECC for Most Significant Bit (MSB) pages in the same group of memory cells; and wherein one of said error correction modules provides long-bit ECC for data on said memory pages which are distributed between the lowest voltage and next lower voltage of said memory cell.