Patent ID: 8718216
Filing Date: 2014-05-06
Classification: H03L,H04L

Abstract:
1. An apparatus for generating a phase indicator signal used in Delay-Locked Loop (DLL) and Phase-Locked Loop (PLL) circuits comprising: a digital phase detector comprising: a first digital system and a second digital system receiving a clock signal and a reference clock signal, the first digital system includes a first digital sense amplifier and the second digital system includes a second digital sense amplifier; and a cross-coupling unit cross-coupling at least one respective output signal of the first digital sense amplifier system to at least one respective input of the second digital sense amplifier system and cross-coupling at least one respective output signal of the second digital sense amplifier system to at least one respective input of the first digital sense amplifier system; wherein the first digital sense amplifier system and the second digital sense amplifier system operating near zero phase offset and generating the phase indicator signal, said phase indicator signal of a logical one or a logical zero respectively to identify the clock signal as leading or lagging the reference clock signal.