Patent ID: 7799697
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A patterning method in a semiconductor manufacturing process comprising: providing a base with a target layer and a lining layer sequentially formed on top of the base; patterning the lining layer to form a periodic array of rectangular blocks distributed on the target layer in a plurality of columns and a plurality of rows of said rectangular blocks, wherein a first pitch is defined between any two adjacent rectangular blocks in each of said plurality of columns and in each of said plurality of rows, and wherein neighboring of said plurality of columns and neighboring of said plurality of rows are spaced apart a distance smaller than said first pitch; forming a sidewall spacer surrounding each of the plurality of rectangular blocks in contiguous contact with sidewalls thereof, wherein the target layer is partially exposed within said sidewall spacer; forming a filling layer to substantially completely cover the target layer exposed within said sidewall spacer; removing the sidewall spacer, thereby forming a plurality of filling features disposed on said target layer between neighboring rectangular blocks in each of said plurality of rows thereof, wherein each of said plurality of filling features is separated said distance from each of said plurality of rectangular blocks adjacent thereto; and using the filling layer and the plurality of rectangular blocks as a hard mask to partially remove the target layer therebetween.