Patent ID: 6119226
Filing Date: 2000-09-12
Classification: G06F,G11C

Abstract:
A semiconductor memory device, comprising:a memory array having rows and columns of memory cells;a first block including a set of rows of the memory array for storage of data located in one of a top and a bottom of an address space; anddecoders for a memory access request for the data in the first block, said memory access request in one of an address protocol of a first type in which the first block includes high order address bits at the top of the address space, and a second type in which the first block includes high order address bits at the bottom of the address space, and said decoders including logic to invert the high order address bits in response to a mode control signal, and outputting output signals for selecting a row of the memory array in the first block in response to the memory access request in the first type and the second type address protocol.