Patent ID: 7302460
Filing Date: 2007-11-27
Classification: G06F

Abstract:
1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB's) connected by a PLD routing architecture, wherein at least one LAB is configured in different modes of operations to determine a compression of a plurality of N-bit numbers, the one LAB comprising: a plurality of look-up table (LUT) logic cells, each look-up table (LUT) logic cell configured to input three operand signals at three respective inputs of that look-up table (LUT) logic cell and to output two signals at two respective outputs of that look-up table logic cell (LUT) that are a sum and carry signal resulting from adding the three operand input signals; input lines configured to receive input signals from the PLD routing architecture that represent the plurality of N-bit numbers and output lines configured to provide output signals to the PLD routing architecture that represent the compression of the plurality of N-bit numbers; LAB internal routing logic, not part of the routing architecture of the PLD, connecting the LUT logic cells such that the LUT logic cells collectively process the input signals, received at the input lines, that represent the N-bit numbers to generate the output signals, provided at the output lines, that represent the sum of the N-bit numbers; and a register on the outputs and multiplexor and control bits internally to switch between different modes of operations, wherein the LUT logic cells are organized into slices, each of the slices performing arithmetic on a bit position of the operand signals, each slice including two of the plurality of LUT logic cells organized in a cascaded arrangement, the first logic cell in each slice performing processing of three lines receiving a first one of the bits of the N-bit numbers, and the second logic cell in each slice performing processing of three line receiving a second one of the bits of the N-bit numbers.