Patent ID: 7888243
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device in which a parallel p-n layer with first conductivity type semiconductor layers and second conductivity type semiconductor layers being alternately joined is provided on a first conductivity type low resistance semiconductor layer and a part of the parallel p-n layer is provided over an active region in which a current flows in a turned-on state and a part of the parallel p-n layer is provided over an inactive region around the active region, the method comprising: carrying out epitaxial growth of a first conductivity type semiconductor layer on the first conductivity type low resistance semiconductor layer; depositing an insulator film on the surface of the epitaxially grown first conductivity type semiconductor layer; carrying out patterning of the insulator film to form a mask for forming trenches; by using the patterned insulator film as a mask, forming a plurality of trenches in a region to become an active region in the first conductivity type semiconductor layer and along with this, forming a plurality of trenches in a part of a region to become an inactive region in the first conductivity type semiconductor layer, the trenches being formed with a spacing different from that of the trenches formed in the region to become the active region; carrying out epitaxial growth of a second conductivity type semiconductor layer in each of the trenches formed in the first conductivity type semiconductor layer to fill trenches with the second conductivity type semiconductor layers to a level equal to or higher than the level of the surface of the insulator film used as the mask for forming the trenches; and polishing the parallel p-n layer comprising the first conductivity type semiconductor layers and the second conductivity type semiconductor layers filling the trenches to planarize the surface of the parallel p-n layer.