Patent ID: 6320413
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A level conversion circuit for converting a negative ECL level to a positive CMOS level, comprising:a level conversion circuit input terminal for inputting said negative ECL level;a level shifter, one end of which is connected to said input terminal;a load for said level shifter, one end of which is connected to said level shifter and the other end of which is connected to a positive power supply; anda positive ECL-CMOS level converter, which compares a voltage that is level shifted by said level shifter with a reference voltage and converts to a CMOS level,wherein said level shifter comprises an nMOS transistor with a shorted gate electrode and drain electrode, and said load comprises a pMOS transistor, a gate electrode of which is connected to ground, and a source electrode of which is connected to said positive power supply.