Patent ID: 7683462
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A chip package structure, comprising: a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface; a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising: a die pad to which the back surface of the chip is adhered; and a plurality of leads surrounding the die pad, wherein the die pad is separate from the plurality of the leads with at least one gap there-between; a photoresist layer partially covering the lower surface of the lead frame but having only one opening to expose one of the at least one gap; a plurality of bonding wires electrically connected to the plurality of the chip bonding pads and to the plurality of the leads, respectively; an upper encapsulant encapsulating the chip, the plurality of the bonding wires, and the upper surface of the lead frame; and a lower encapsulant filled only in the only one opening.