Patent ID: 6404664
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A method for constructing a twisted bit line structure in an integrated memory circuit, comprising:forming parallel and adjacent first and second bit line traces in a first conductive level over a substrate by passing light through a phase shift reticle to selectively expose a photosensitive layer deposited over said substrate, wherein said first and second bit line traces comprise a discontinuity at approximately the same location along the length of each of the respective first and second bit line traces to separate each trace into at least two bit line segments; forming in a second conductive level over said substrate a first connection between a first segment of said first bit line trace and a first segment of said second bit line trace; and forming in said second conductive level a second connection between a second segment of said first bit line trace and a second segment of said second bit line trace.