Patent ID: 6080607
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for manufacturing a transistor having a low leakage current, suitable for a substrate, comprising:forming a semiconductor layer on said substrate;forming a first deposition-shielding layer on said semiconductor layer wherein said first deposition-shielding layer is a silicon nitride layer;forming a gate with a second deposition-shielding layer thereon, on said first deposition-shielding layer;performing a first ion-implanting to form a lightly-doped drain/source in said semiconductor layer on both sides of said gate, respectively;forming spacers on the vertical sides of said gate by using a selective deposition process during which no spacers are deposited on said first deposition-shielding layer and said second deposition-shielding layer wherein said selective deposition process is completed by using a selective liquid-phase deposition method;removing the part of said first deposition-shielding layer which is located on both sides of said spacers;performing a second ion-implanting to form a drain/source in said semiconductor layer on both sides of said spacers.