Patent ID: 7509112
Filing Date: 2009-03-24
Classification: H03D

Abstract:
1. An image rejection mixer comprising: a first hybrid coupler adapted to receive an input radio frequency (RF) signal and to produce a first RF signal and a second RF signal, the second RF signal being in quadrature compared to the first RF signal; a first traveling-wave single-ended mixer adapted to mix the first RF signal and a local oscillator (LO) signal to produce a first intermediate frequency (IF) signal; a second traveling-wave single-ended mixer adapted to mix the second RF signal and the local oscillator signal to produce a second IF signal; and a second hybrid coupler adapted to combine the first IF signal and the second IF signal to produce at least one of an upper sideband of the IF signals and a lower sideband of the IF signals; such that the first traveling-wave single-ended mixer further comprises: a least two switching devices each switching device having a first current terminal, a second current terminal, and a gate terminal, and said switching devices connected in parallel; wherein each switching device provides a first parasitic capacitance between its first current terminal and its gate terminal and a second parasitic capacitance between its first current terminal and its second terminal; a gate matching circuit including a plurality of gate inductors, serially connected to each other, each gate inductor connected to at least one gate terminal such that inductance of said gate inductors electrically combine with the first parasitic capacitance to present a first input impedance; and a drain matching circuit including a plurality of drain inductors, serially connected to each other, each drain inductor connected to at least one second current terminal such that inductance of said drain inductors electrically combine with the second parasitic capacitance to present a second input impedance; such that the second traveling-wave single-ended mixer further comprises: a least two switching devices each switching device having a first current terminal, a second current terminal, and a gate terminal, and said switching devices connected in parallel; wherein each switching device provides a first parasitic capacitance between its first current terminal and its gate terminal and a second parasitic capacitance between its first current terminal and its second terminal; a gate matching circuit including a plurality of gate inductors, serially connected to each other, each gate inductor connected to at least one gate terminal such that inductance of said gate inductors electrically combine with the first parasitic capacitance to present a first input impedance; and a drain matching circuit including a plurality of drain inductors, serially connected to each other, each drain inductor connected to at least one second current terminal such that inductance of said drain inductors electrically combine with the second parasitic capacitance to present a second input impendence.