Patent ID: 6137349
Filing Date: 2000-10-24
Classification: H03H

Abstract:
A filter combination circuit for performing a sampling rate conversion of an input data sequence (d1) into an output data sequence, comprising:an input low-pass filter (1) receiving said input data sequence (d1) for outputting a first data sequence (d4) in response to a digitization clock frequency of a clock signal (f1), said input low-pass filter having an attenuation characteristic (tp1) of at least one first attenuation value (a1) substantially corresponding to between one-half and 1.5 times digitization clock frequency (f1);a time-invariant interpolation filter (2) responsive to said first data sequence (d4) of said input low-pass filter and said digitization clock frequency (fi) for increasing a number of samples from that of the input data sequence (d1) by an integral factor to provide a second data sequence (d5), and having an attenuation characteristic (tp2) comprising at least one second attenuation value (a2) substantially corresponding to the frequency of the digitization clock (f1) and at least one third attenuation value (a3) substantially corresponding to the between one-half and 1.5 times the frequency of the digitization clock; anda time-varying interpolation filter (3) for interpolating said second data sequence (d5) provided at an output of the time-invariant interpolation filter (2), in response to said clock signal for suppressing signal components at twice the frequency of the digitization clock (f1) to provide said output data sequence, said time-varying filter having an attenuation characteristic (tp3) of at least one fourth attenuation value (a4) substantially corresponding to twice the frequency of the clock signal (f1);wherein, said input low pass filter (1), time-invariant interpolation filter (2) and time-variant interpolation filter (3) are coupled in series.