Patent ID: 6236117
Filing Date: 2001-05-22
Classification: H01L,Y10S

Abstract:
A semiconductor device, comprising:a first memory cell, said first memory cell being one of a plurality of memory cells arranged in a matrix;a first ground line formed on said first memory cell;two word lines provided in a single layer on said first memory cell;a first low resistance shunt interconnection formed on said first ground line having a first interlayer insulating film therebetween, wherein said first shunt interconnection is one of a plurality of shunt interconnections, each of said plurality of shunt interconnections provided corresponding to at least two of said plurality of memory cells arranged adjacent to each other in a direction substantially orthogonal to the direction in which said first ground line extends, and each of said plurality of shunt interconnections arranged on only one of said at least two corresponding memory cells; anda first shunt connection region formed in a region two-dimensionally overlapping said first memory cell for electrically connecting said first ground line and said first shunt interconnection.