Patent ID: 8841777
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A bonded structure comprising a vertical stack containing, from bottom to top, at least: a first semiconductor substrate; a first interconnect-level structure; a first planar dielectric layer; a layer complementarily filled with metal semiconductor alloy portions and vertical stacks of dielectric material portions, each of said vertical stacks of dielectric material portions including a first dielectric material portion and a second dielectric material portion that contact each other within a same interface plane that is common across all of said vertical stacks; a second planar dielectric layer; a second interconnect-level structure; and a second semiconductor substrate, wherein an entire top surface of one of said metal semiconductor alloy portions is in physical contact with a dielectric surface of said second planar dielectric layer, an entire bottom surface of said one of said metal semiconductor alloy portions is in physical contact with a dielectric surface of said first planar dielectric layer, and entire sidewall surfaces of said one of said metal semiconductor alloy portions are in physical contact with surfaces of said vertical stacks of dielectric material portions.