Patent ID: 8941629
Filing Date: 2015-01-27
Classification: G09G

Abstract:
1. A scan driver for a display device, the scan driver comprising: clock selectors that output either a first clock or a second clock obtained by inverting the first clock in accordance with logic value of a selection signal, the first clock having a logic high period followed by a logic low period within one horizontal time, the horizontal time corresponding to a duration during which a scan signal is asserted for display of an image on the display device; and shift registers that generate pulse signals for driving sub-pixels of the display device in a given row, based on either the first clock or the second clock supplied from the clock selectors together with first to N-th start pulses of different phases where N is an integer equal to or greater than 4, one or more of the shift registers generating at least a first pulse signal for the given row based on a first start pulse responsive to the first clock and generating a second pulse signal for the given row offset by ½ horizontal time from the first pulse signal based on a second start pulse responsive to the second clock, the first pulse signal being asserted during a light-emitting period of the sub-pixels and the second pulse signal not being asserted during the light-emitting period of the sub-pixels.