Patent ID: 6356599
Filing Date: 2002-03-12
Classification: H03J,H04L,H04M,H04W

Abstract:
An Automatic Frequency Control (AFC) device in a dual-mode terminal, comprising:a first IF (Intermediate Frequency) generator having a first frequency oscillator, for generating a first IF by mixing a first input signal with a first oscillation frequency; a first analog-to-digital (A/D) converter for receiving a first quantization step value, allocating quantization bits to obtain a first linear characteristic, and then converting the first IF to first digital data, wherein the first A/D converter comprises a first maximum amplitude detector for detecting the maximum amplitude value of the first IF, a first quantization gain controller for receiving the first quantization step value and generating a first quantization gain control signal, and a first quantization bit allocator for allocating the quantization bits to the maximum amplitude by using the first quantization gain control signal; a second IF generator having a second frequency oscillator, for generating a second IF by mixing a second input signal with a second oscillation frequency; a second A/D converter for receiving a second quantization step value, allocating quantization bits to obtain a second linear characteristic, and then converting the second IF to second digital data, wherein the second A/D converter comprises a second maximum amplitude detector for detecting the maximum amplitude value of the second IF, a second quantization gain controller for receiving the second quantization step value and generating a second quantization gain control signal, and a second quantization bit_allocator for allocating the quantization bits to the maximum amplitude by using the second quantization gain control signal; an automatic frequency controller for receiving one of the first and second digital data by the first and second input signals and automatically controlling the frequency of a main clock based on one of the first and second linear characteristics in accordance with the one of the first and second input signals; and a frequency multiplier for multiplying a signal of said main clock and applying the multiplied clock signal to said first and second frequency oscillators.