Patent ID: 7139956
Filing Date: 2006-11-21
Classification: G11C

Abstract:
1. A method for performing a test on a semiconductor integrated circuit device, which comprises a test target circuit including a plurality of nodes and terminals, the method comprising: performing a first fault simulation on the test target circuit to obtain a first undetected fault list, in which faults not detected by the first fault simulation are listed, the first undetected fault list including a correlation of each undetected fault with the nodes and terminals, and a type of each undetected fault; with reference to the first undetected fault list, extracting observation point candidates selected from the nodes and terminals, and observation point information including a type of each undetected fault at the observation point candidates, and sorting out the observation point candidates to obtain first observation points, such that the first observation points do not include less effective observation points in terms of insertion thereof for a test; performing a second fault simulation to confirm an effect of inserting the first observation points, and obtain a second undetected fault list, by using the first observation points, first circuit connection information at a gate level, and first test patterns to perform substantially normal functional operation; with reference to the second undetected fault list, deleting less effective observation points in terms of insertion thereof for a test, from the first observation points, to obtain second observation points; and connecting a test circuit to observation points finally determined, the test circuit being configured to compress data at observation points to a signature and read out the signature.