Patent ID: 6304887
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A system for processing data in digital signal processing applications employing fast Fourier transforms (FFT's), the system processing N data points through Y processing stages using Z execution units, each execution unit having a plurality of I/O ports including A and B ports, and including an addressable memory unit for each A and B port on each execution unit, including memory units A(1) through A(Z) operatively connected to the A ports of execution units P(1) through P(Z), respectively, and including memory units B(1) through B(Z) operatively connected to the B ports of execution units P(1) through P(Z), respectively, and wherein data is processed through the Y processing stages by moving data in parallel in selectable sequences used in mixed radix FFT operations through each execution unit P(q) between memory units A(q) and B(q), and in which at the start of the processing of the data the N data points are distributed between memory units connected to one of the ports of the execution units, either A(1) through A(Z) if distributed to the memory units connected to the A ports of the execution units or B(1) through B(Z) if distributed to the memory units connected to the B ports of the execution units, each memory unit receiving N/Z data points, and each execution unit P(1) through P(Z) processing a block of N/Z data points through the Y processing stages, the processing occurring in parallel, the system for processing data comprising:a first address generator AG-A operatively connected to memory units A(1) through A(Z) for supplying a series of selected address sequences used in mixed-radix FFT operations, the series of selected address sequences being supplied for Y processing stages to memory units A(1) through A(Z);a second address generator AG-B operatively connected to memory units B(1) through B(Z) for supplying a series of selected address sequences used in mixed-radix FFT operations, the series of selected address sequences being supplied for Y processing stages to-memory units B(1) through B(Z); andfor each of the Y processing stages, address generator AG-A supplies the same address sequence to all A(1) through A(Z) memory units, and address generator AG-B supplies the same address sequence to all B(1) through B(Z) memory units, whereby the N data points are processed in Z parallel streams through the Z execution units.