Patent ID: 6560679
Filing Date: 2003-05-06
Classification: G06F,Y02D

Abstract:
A digital data processing system comprising:a digital data processor; a main memory, responsive to a main memory address from said processor, for storing instructions and data to be processed by said processor, said main memory address including a set field and a tag field; a cache memory including a data RAM and a tag RAM, said data RAM storing a frequently accessed portion of the instructions and data stored in said main memory, said tag RAM storing tags for accesses to said data RAM and generating cache hit/miss signals by comparing the tag field with the tags stored in said tag RAM; and a controller which stores state information on access type, operation mode and cache hit/miss associated with a first access to said tag RAM, and controls a second access to said tag RAM sequentially following the first access, based on the state information and a portion of a main memory address for the second access, the portion including a least significant bit of the set field.