Patent ID: 7898058
Filing Date: 2011-03-01
Classification: H01L,Y10T

Abstract:
1. A chip package comprising: a first polymer layer; a first die between a first portion of said first polymer layer and a second portion of said first polymer layer, wherein said first die has a top surface substantially coplanar with a top surface of said first polymer layer; a second polymer layer on said top surface of said first die and on said top surface of said first polymer layer; a circuit metal layer on said second polymer layer, over said top surface of said first die and over said top surface of said first polymer layer, wherein there is no metal layer between said circuit metal layer and said top surface of said first polymer layer, wherein said circuit metal layer is connected to a first metal pad of said first die through a first opening in said second polymer layer, wherein said circuit metal layer comprises a portion as a part of a capacitor; and a third polymer layer on said circuit metal layer, on said second polymer layer, over said top surface of said first die and over said top surface of said first polymer layer.