Patent ID: 6868374
Filing Date: 2005-03-15
Classification: G06F

Abstract:
1. A method for performing power distribution analysis for I/O circuits in an integrated circuit (IC) design, said I/O circuits having defined placement locations within a power distribution network of said design, comprising the steps of: a) calculating maximum and average currents for each of said I/O circuits, and an average logic current demand per node; b) creating a resistance model of said power distribution network comprising nodes and resistors corresponding to points on buses of said network and resistivities corresponding to said points; c) indexing each of said I/O circuit currents and said average logic current demand per node to the node in said model closest to the corresponding I/O circuit location; d) solving the resistance an current source model resulting from step (c) for voltages at the nodes; and e) outputting the results.