Patent ID: 8212322
Filing Date: 2012-07-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having at least a first and a second nFET region, and at least a first and a second pFET region, wherein the first and second pFET regions comprise crystalline silicon germanium, and wherein the crystalline silicon germanium in the second pFET region is configured to have a reduced germanium fraction; at least one logic nFET on the substrate over the first nFET region; at least one logic pFET on the substrate over the first pFET region; at least one SRAM nFET on the substrate over the second nFET region; and at least one SRAM pFET on the substrate over the second pFET region, wherein each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer, wherein the logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, and wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.