Patent ID: 7308557
Filing Date: 2007-12-11
Classification: G06F

Abstract:
1. A method for invalidating entries within a translation control entry (TCE) cache within a host bridge, wherein said host bridge is coupled between a plurality of processors and a plurality of adaptors, said method comprising: detecting a modification to a TCE in a TCE table located within a system memory, wherein said TCE is identified within said TCE table via a TCE fetch address formed by combining high-order bits of a Peripheral Component Interconnect (PCI) address with a TCE address within a TCE address register, wherein a system memory address for a PCI device associated with said TCE is formed by combining a subset of address bits from said TCE with low-order bits of said PCI address; in response to a detection of a modified TCE in said TCE table, sending a memory mapped input/output (MMIO) Store to a TCE invalidate register to specify an address of said modified TCE; utilizing data within said TCE invalidate register to generate a command for invalidating an entry in said TCE cache containing an unmodified copy of said modified TCE in said TCE table; and invalidating said entry in said TCE cache.