Patent ID: 8519771
Filing Date: 2013-08-27
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a single ended driver coupled to receive an input signal, the single ended driver comprising a first n-type metal-oxide-semiconductor (NMOS) transistor and a first p-type metal-oxide-semiconductor (PMOS) transistor; and an input pass gate coupled to the single ended driver, the input pass gate being configured as a PMOS pass gate coupled in parallel with the first NMOS transistor, wherein in a low voltage mode the first NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to a receiver; and wherein in a high voltage mode the PMOS pass gate is disabled, and the first NMOS transistor and the first PMOS transistor form a second pass gate for transmitting the input signal to the receiver.