Patent ID: 6709562
Filing Date: 2004-03-23
Classification: C25D,H01L

Abstract:
A process for fabricating an interconnect structure on an electronic device with void-free seamless submicron conductors comprising the steps of:forming an insulating material on a substrate, lithographically defining and forming recesses for submicron lines and/or submicron vias in said insulating material in which interconnection conductor material will be deposited, forming a conductive layer on said insulating material serving as a plating base, depositing by a damascene process said conductor material in a seamless and void-free manner by electroplating from a bath containing additives, said bath additives causing the plating rate to increase with depth along the sidewall of a recess, thereby preventing the formation of a seam or void in a conductor in said recesses, and said conductor material comprising copper and planarizing the resulting structure to accomplish electrical isolation of individual seamless and void-free lines and/or seamless and void-free vias.