Patent ID: 8892859
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. An integrated circuit device, comprising: a central processing unit (CPU) that is configured to perform a reset operation in response to detecting that a first signal is asserted at an input pin; a counter circuit, configured to operate independently from the CPU and not to reset a count of the counter circuit upon the reset operation of the CPU, that is coupled to the input pin and that is configured to count clock cycles whenever the first signal is asserted on the input pin, and to update a count value stored in a factory reset register based on the counted clock cycles; and a factory reset module, configured to operate independently from the CPU, that compares the stored count value to a threshold value, and that causes the CPU to perform a factory reset operation, that is different from the reset operation, in response to the stored count value meeting or exceeding the threshold.