Patent ID: 8671327
Filing Date: 2014-03-11
Classification: G06F,G11C

Abstract:
1. A method of storing a plurality of bits in at least one memory cell, comprising: (a) providing, in accordance with a respective initial value of a physical parameter of each of the at least one memory cell, an adaptive mapping of the bits to physical parameter ranges for storing the bits in the at least one memory cell, by steps including encoding the bits as a codeword by partitioning the bits into a plurality of subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string; and (b) for each of the at least one memory cells, if according to the adaptive mapping it is determined that the respective initial value of the physical parameter of the at least one memory cell is to be adjusted to enable the plurality of bits to be stored in the at least one memory cell: adjusting the respective initial value of the physical parameter of the each memory cell in accordance with the adaptive mapping.