Patent ID: 6230293
Filing Date: 2001-05-08
Classification: G01R

Abstract:
A method for quality and reliability assurance testing of integrated circuits (ICs), comprising the steps of:measuring the quiescent current I.sub.ddq of a sample of ICs from a lot of ICs at two different voltages;determining the differential quiescent current .DELTA.I.sub.ddq of the ICs by subtracting the value of the quiescent current measured at the first voltage from the value of the quiescent current measured at the second voltage;identifying those sample ICs having differential quiescent current .DELTA.I.sub.ddq readings falling outside of a first predetermined range of acceptable measurement as potentially defective ICs;burning-in each one of the sample ICs;testing the functionality of the burned-in sample of ICs; andidentifying those sample ICs having post burn-in functionality readings falling outside of a second predetermined range of acceptable measurement as defective ICs, wherein if the ICs identified as defective by the differential quiescent current measurements are the same ICs identified as defective by the post burn-in functionality testing, then the second voltage is an effective screening voltage for the entire lot of ICs.