Patent ID: 8861364
Filing Date: 2014-10-14
Classification: H04L

Abstract:
1. An integrated circuit (IC), comprising: a link controller; and a plurality of queue controllers in communication with the link controller, each queue controller of the plurality of queue controllers operable to be coupled to a corresponding external dedicated buffer, wherein each external dedicated buffer resides in a remote transmitter of data that is external to the IC, and wherein each queue controller of the plurality of queue controllers is operable to: monitor and detect a buffer full level for the corresponding external dedicated buffer, transmit a signal indicating one of the buffer full condition or buffer below full condition associated with the corresponding external dedicated buffer to the link controller, and wherein the link controller is operable to: receive, from a first queue controller, the signal indicating the buffer full condition associated with a first external dedicated buffer, transmit a priority flow control signal to discontinue sending data to the first external dedicated buffer based on the received signal from the first queue controller, communicate to the first queue controller a second signal interpreted by the first queue controller as indicating completion of the transmission of the priority flow control signal, receive, from the first queue controller, a pause time associated with the first external dedicated buffer, the pause time indicating a time period that the link controller waits before rechecking a buffer level.