Patent ID: 7467320
Filing Date: 2008-12-16
Classification: G06F

Abstract:
1. An apparatus comprising: a first clock signal generator to output a first clock signal; a second clock signal generator to output a second clock signal and coupled to receive the first clock signal and an enable signal, the second clock signal generator includes a clock source to output a first reference clock signal, and the second clock signal generator to output a first error value that indicates a frequency difference between the first clock signal and the first reference clock signal, the second clock signal generator includes a third clock signal generator coupled to receive the first clock signal, the third clock signal generator includes a clock source to output a second reference clock signal and, the third clock generator to output a second error value that indicates a frequency difference between the second reference clock signal and the first clock signal; and a fail detect circuit to detect a failure in the first clock signal generator, output the enable signal and determine which of the first and second clock signals is oscillating at a frequency nearest the frequency of the third clock signal.