Patent ID: 6580411
Filing Date: 2003-06-17
Classification: G09G,H03K

Abstract:
A latch circuit which receives a pulse signal and a clock signal as inputs and outputs the pulse signal in synchronization with the clock signal, wherein one of the clock signal and the pulse signal has an amplitude smaller than the amplitude of the pulse signal outputted from the latch circuit, the latch circuit comprising:a first p-type transistor and a second p-type transistor, having source electrodes connected to the power potential and gate electrodes connected to drain electrodes of the counterparts; a first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a drain electrode connected to a ground potential and a gate electrode connected to the drain electrode of the second p-type transistor; a second n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the first p-type transistor; a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor and a gate electrode that receives the pulse signal as an input; a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input; a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode that receives an inverted signal of the pulse signal as an input; and a sixth n-type transistor having a source electrode connected to the drain electrode of the fifth n-type transistor, a drain electrode connected to the ground potential and a gate electrode that receives the clock signal as an input, whereby the pulse signal is outputted from the drain electrode of the second p-type transistor, and the inverted signal of the pulse signal is outputted from the drain electrode of the first p-type transistor.