Patent ID: 7979629
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A serial peripheral interface (SPI) memory module using address cache comprising: a serial/parallel converter, for receiving a reference clock signal and a chip select signal from a system chip, receiving a control command signal, a address signal and a data signal transmitted in serial via a plurality of signal lines from the system chip, and outputting a control command, an address bus signal and a data bus signal; a flash memory array, for storing the data bus signal; an address register, for storing an access address according to the address bus signal; an address accumulator for accumulating the access address stored in the address register and storing the accumulated access address back to the address register after the SPI memory module completes access; and a flash memory controller for receiving the control command and the access address stored in the address register to control the access to the flash memory array, wherein the flash memory controller either transmits data from the flash memory array to the serial/parallel converter or stores data from the serial/parallel converter to the flash memory array; wherein while the control command signal received by the serial/parallel converter is a standard command, the serial/parallel converter stores a portion of bits subsequent to the control command signal into the address register and then the flash memory controller starts to access the data; and while the control command signal received by the serial/parallel converter is a specific command, the flash memory controller starts to access data.