Patent ID: 6247111
Filing Date: 2001-06-12
Classification: G01R,G06F

Abstract:
A system comprising:A. a device having address leads and data leads, the device producing data signals on the data leads in a first time after occurrence of address signals received on the address leads;B. a microprocessor having address leads sending address signals and having data leads at least receiving data signals, the microprocessor being capable of receiving data signals on the data leads in a second time after the occurrence of address signals on the address leads, the second time being less than the first time, and the microprocessor including a wait state register connected to the data leads to receive data signals from the data leads, the first register containing a first number indicating a first number of wait states to be inserted between the occurrence of the address signals on the microprocessor address leads and the second time to result in a third time that is greater than the first time; andD. address leads connecting the address leads of the device to the address leads of the microprocessor and data leads connecting the data leads of the device to the data leads of the microprocessor.