Patent ID: 6141630
Filing Date: 2000-10-31
Classification: G01R,G06F

Abstract:
An automated simulated electronics design verification system for electronic design automation, comprising:a design database for storing a hardware design coding language representing a circuit design;a coverage database that contains a map of each state and transition arc represented within said circuit design;a test bench that includes a simulated electronics design converted from said hardware design coding language representing a circuit design in the design database, and including an output-log database, and providing for stimulation of said simulated electronics design with a test-frame of test vectors, wherein an output data results and is compiled in the output-log database;a coverage analysis tool for monitoring said output data, and for identifying to the test bench any portions of said simulated electronics design that remain to be tested;a comparator for comparing an output data from said simulated electronics design with at least one of a reference data and a constraint data, and for generating an anomaly report; anda test generator for sending said test-frame of test vectors to the test bench, and connected to receive design database and coverage database information, and for correlating any basic blocks and transition arcs exercised by said test-frame of test vectors with said anomaly report for localizing and identifying any defective ones of said basic blocks and transition arcs;wherein, the test bench exercises portions of said simulated electronics design as directed by the coverage analysis tool.