Patent ID: 9053776
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. An integrated circuit chip, comprising: a selection code transfer bus configured to transfer selection codes; a setting data transfer bus configured to transfer setting data; a first line configured to transfer a first set signal; a second line configured to transfer a second set signal; a plurality of first decoders configured to generate a plurality of first input enable signals, respectively, in response to the selection codes and a first set signal; a plurality of first register sets configured to correspond to the plurality of first decoders, respectively, and to receive the setting data when the first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and to store the received setting data; a plurality of second decoders configured to generate a plurality of second input enable signals, respectively, in response to the selection codes and the second set signal; a plurality of second register sets configured to correspond to the plurality of second decoders, respectively, and to receive the setting data when the second input enable signals generated from the plurality of second decoders corresponding to the second register sets, respectively, are enabled, and to store the received setting data; a reception circuit configured to receive a plurality of signals externally; and an encoding circuit configured to generate the selection codes, the setting data, the first set signal, and the second set signal by using the plurality of signals received through the reception circuit.