Patent ID: 8664707
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a lower interconnection on a substrate; at least one upper interconnection disposed on the lower interconnection; at least one gate structure disposed between the upper interconnection and the lower interconnection, the gate structure comprising a plurality of gate lines vertically stacked and each of the gate lines having a wiring portion substantially parallel to an upper surface of the substrate and a contact portion extending from the wiring portion along a direction penetrating the upper surface of the substrate; at least one semiconductor pattern connecting the upper and lower interconnections; and a mold insulation layer on the substrate, a sidewall of the mold insulation layer having a plurality of undercut regions vertically spaced apart from each other, wherein each of the plurality of gate lines is in respective ones of the plurality of undercut regions, and the semiconductor pattern conformally covers the sidewall of the mold insulation layer.