Patent ID: 6790685
Filing Date: 2004-09-14
Classification: H01L

Abstract:
Method of forming a test pattern comprising:forming first and second junction regions having a symmetrical structure on both sides of field oxide layer formed on a semiconductor substrate; forming third and fourth junction regions having a asymmetrical structure on front and rear portions of said field oxide layer; forming a test pattern having first and second projection portions on said semiconductor substrate, in which both side portions of said test pattern are overlapped with said first and second junction regions and said first and second projection portions which are formed on front and rear portions of said test pattern are overlapped with said third and fourth junction regions; forming an inter insulating layer on a resulting structure after forming said test pattern; patterning said inter insulating layer to expose a portion of said first to fourth junction regions; forming current supply lines connected to said first and second junction regions, respectively; and forming voltage measuring lines connected to said third and fourth junction regions, respectively.