Patent ID: 6088253
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of data pads;a plurality of first stage circuits;a plurality of data latch circuits; andan internal clock signal generating circuit;wherein data that is introduced to said data pads is fed via said first stage circuits to said data latch circuits, said data latch circuits latching said data on a rising edge and on a falling edge of a clock signal generated by said internal clock signal generating circuit,said plurality of data pads are arranged in a straight line so as to form a data pad row,said data latch circuits are disposed in a region surrounded between a second straight line which is perpendicular to a first straight line that passes over said data pad row and which also passes one end of said plurality of data pads and a third straight line, which is parallel to said second straight line and which passes another end of said plurality of data pads,the length of interconnections between each of said plurality of data latch circuits and said internal clock signal generating circuit is made the same,the wiring length from said first stages to said data latch circuits is made the same as the length of the wiring from said internal clock signal generating circuit to each of said data latch circuits, andsaid first stage circuits, data latch circuits, and the internal clock signal generating circuit are operated by a voltage that has been dropped from an external power supply.