Patent ID: 6570802
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A semiconductor memory device comprisinga memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit, wherein: the semiconductor memory device has a first refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal input externally and a refresh address generated from the first internal address generation circuit that operates in response to the periodic pulse signal input externally, and a second refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and a refresh address generated from the second internal address generation circuit, and different memory regions are refreshed in the first refresh mode versus the second refresh mode.