Patent ID: 6576528
Filing Date: 2003-06-10
Classification: C23C,H01L

Abstract:
A method of manufacturing a capacitor of semiconductor memory devices comprising:providing a semiconductor substrate in which a MOS transistor is formed; forming, on the semiconductor substrate, an interlevel insulating layer having a contact hole exposing a selected portion of a junction region of the MOS transistor; forming a lower electrode on the interlevel insulating layer to contact with the exposed junction region; depositing an amorphous TaxOyNz layer as a dielectric layer on the lower electrode; crystallizing the amorphous TaxOyNz layer; and forming an upper electrode on the crystalline TaxOyNz layer, wherein the total of x, y and z in the TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3; wherein the step of depositing the amorphous TaxOyNz layer further comprises supplying reactant gases Ta chemical vapor obtained from a precursor, O2 gas and NH3 gas into a low pressure chemical vapor deposition chamber (LPCVD) at pressure of 0.1 to 100 Torr at temperature of 300 to 600Â° C. and inducing a surface chemical reaction between the reactant gases; and wherein the O2 gas is supplied at 50 to 150 sccm and NH3 is supplied at 30 to 70 sccm.