Patent ID: 6222772
Filing Date: 2001-04-24
Classification: G11C

Abstract:
A method of operating a nonvolatile integrated circuit memory device, comprising the steps of:performing a first erase operation on a first sector of memory cells;verifying whether a first memory cell at a current address in the first sector is sufficiently erased in response to the first erase operation and updating a failure count of a number of memory cells in the first sector that have failed to become sufficiently erased if the first memory cell has not become sufficiently erased in response to the first erase operation;determining whether the failure count has reached a maximum number of erase failures greater than one;determining whether a maximum number of erase operations have been performed on the first sector of memory cells if and only if the failure count has reached the maximum number of erase failures; andresetting the failure count and performing a second erase operation on the first sector of memory cells if a maximum number of erase operations have not been performed on the first sector of memory cells.