Patent ID: 8400815
Filing Date: 2013-03-19
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of first lines and second lines intersecting each other, and a plurality of memory cells connected at intersections of the plurality of first lines and second lines respectively; and a first line control circuit and a second line control circuit configured to select the first lines and the second lines respectively to supply a voltage or current necessary for a resetting operation or a setting operation on the memory cells, the first line control circuit including a plurality of unselecting voltage generating circuits each configured to generate an unselecting voltage of a different value, and a switching circuit configured to select a certain one of the unselecting voltages from the plurality of unselecting voltages corresponding to a distance between unselected ones of the first lines and the second line control circuit and supply the selected unselecting voltage to the unselected first lines.