Patent ID: 9082624
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a signal conductor layer comprising: a first signal track having a design width on the signal conductor layer defined by a first mask and processed to a first physical width; a second signal track having the design width on the signal conductor layer defined by a second mask and processed to a second physical width, wherein the first signal track is adjacent to the second signal track and physical widths defined by a single mask more closely track than physical widths defined by separate masks; and a repeater structure to achieve a timing tolerance standard adapted to repower a first signal on a first conductor in the first signal track and transfer the first signal to a second conductor in the second signal track, and to repower a second signal on a third conductor in the second signal track and transfer the second signal to a fourth conductor in the first signal track.