Patent ID: 6147511
Filing Date: 2000-11-14
Classification: H03K

Abstract:
A circuit to implement an overvoltage-tolerant integrated circuit comprising:a pull-up device coupled between a first supply voltage and an I/O pad; anda body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node;a second clamping device coupled between the I/O pad and the first node; anda third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.