Patent ID: 9048865
Filing Date: 2015-06-02
Classification: H03F,H03M,H04L

Abstract:
1. An apparatus for combining sub-rate outputs of a polyphase parallel processor into a single output, comprising: a plurality of input lines for accepting sub-rate samples of an underlying full-rate input signal, the underlying full-rate input signal comprising a sequence of samples at a sampling rate or, correspondingly, said samples separated in time by a sampling period; a plurality of delay elements coupled to the input lines; and a signal combiner having inputs that are coupled to outputs of said delay elements and also having an output, wherein the sub-rate samples on each of the plurality of said input lines are a sequence of values representing a different subsampling phase of the underlying full-rate input signal, wherein said delay elements introduce different time-offsets in increments that are integer multiples of the sampling period of the underlying full-rate input signal, wherein the signal combiner performs a summing operation, and wherein said delay elements and said signal combiner together produce a filter response that includes a lowpass function having a bandwidth smaller than the sampling frequency of the underlying full-rate input signal.