Patent ID: 8711598
Filing Date: 2014-04-29
Classification: G11C

Abstract:
1. A memory cell, comprising: a first P-type transistor configured to have a first source/drain thereof electrically coupled to a first voltage; a second P-type transistor configured to have a first source/drain thereof electrically coupled to the first voltage; a first N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the first P-type transistor, a second source/drain thereof electrically coupled to a second voltage, and a gate thereof electrically coupled to the gate of the first P-type transistor; a second N-type transistor configured to have a first source/drain thereof electrically coupled to a second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and a gate thereof electrically coupled to the gate of the second P-type transistor; a third N-type transistor configured to have a first source/drain thereof electrically coupled to a write word line, a second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to a first write bit line; and a fourth N-type transistor configured to have a first source/drain thereof electrically coupled to the write word line, a second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and a gate thereof electrically coupled to a second write bit line.