Patent ID: 7890737
Filing Date: 2011-02-15
Classification: G06F

Abstract:
1. A microcomputer for functioning according to a plurality of operation modes comprising; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter so as to output a mode signal, wherein the mode signal represents one of the operation modes; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU is capable of accessing to the input data buffer when the mode signal represents a test mode, wherein in the test mode, test instruction data is capable of being inputted from an external circuit.