Patent ID: 6218200
Filing Date: 2001-04-17
Classification: G03F,H01L

Abstract:
A method for measuring overlay error in a photolithography process, the method comprising:growing a first layer;printing a first circuit pattern on said first layer using a first photomask;printing a first registration pattern on said first layer using said first photomask;etching said first layer;growing a second layer on said first layer;printing a second circuit pattern on said second layer using a second photomask;printing a second registration pattern on said second layer using said second photomask;etching said second layer;growing a third layer on at least one of said first and second layers;printing a third circuit pattern on said third layer using a third photomask; andprinting a third registration pattern on said third layer using said third photomask,wherein said first, second and third registration patterns form an overlay mark that defines overlay errors in a first direction between said first and third layers and in a second direction between said second and third layers.