Patent ID: 8315089
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. A phase change memory device comprising: a cell array including a phase change resistor configured to read/write data; a sense amplifier configured to compare a reference voltage with a sensing voltage received from the cell array; a write driving unit configured to supply a driving voltage corresponding to write data to the cell array wherein the sense amplifier is connected to a global bit line through a global column switching unit; a reference level selecting unit configured to select a read reference voltage in a read mode so as to output the reference voltage, to select a set reference voltage when a input data is a set data and select a reset reference voltage when a input data is a reset data in a write verifying mode so as to output the reference voltage; and a comparing unit configured to compare the input data with output data of the sense amplifier so as to output a driving enable signal for controlling the write driving unit; wherein the sense amplifier includes: a sensing current voltage converting unit configured to convert a sensing current received from a bit line of the cell array into the sensing voltage; an amplifier configured to compare and amplify the sensing voltage and the reference voltage; and a latch unit configured to latch an output signal of the amplifier.