Patent ID: 6809374
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A nonvolatile memory device, comprising:a first impurity region and a second impurity region each formed in a substrate; a channel region between the first and second impurity regions; a word gate formed above the channel region; a first gate insulation layer between the word gate and the channel region; a first control gate formed to one side of the word gate; a first side insulation layer between the first control gate and the word gate; a second control gate formed to another side of the word gate; a second side insulation layer between the second control gate and the word gate; a second gate insulation layer having a first charge trapping region formed between the substrate and the first control gate; and a third gate insulation layer having a second charge trapping region formed between the substrate and second control gate; wherein the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and the first control gate is lower within a first range in a gate length direction adjacent the first side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.