Patent ID: 9122838
Filing Date: 2015-09-01
Classification: G03F,G06F

Abstract:
1. A method of decomposing a layout for triple-pattern lithography, said method comprising: generating a conflict graph from a layout for a layer of a semiconductor device, said conflict graph including a plurality of nodes, each said node representing a polygon of said layout, and a plurality of links, each connecting two said nodes, each said link corresponding to a distance between adjacent polygons being less than a minimum separation distance using a single photomask; and converting said conflict graph to a simplified conflict graph, said converting including removing nodes that are connected to two or fewer links, from said conflict graph, wherein said converting further comprises separating portions of said conflict graph that are connected by only a single loop, wherein at least one of said generating and converting is carried out by a computer, wherein the computer outputs mask assignment data based on the simplified conflict graph indicating whether the layout can be decomposed for triple pattern lithography, and the mask assignment data are used to fabricate at least one photomask for patterning the layer of the semiconductor device.