Patent ID: 8995165
Filing Date: 2015-03-31
Classification: G11C,H01L

Abstract:
1. A program and erase method of a resistive memory cell comprising a unipolar type RRAM and a MOS transistor serially connected with the RRAM as a switch and the MOS transistor is fabricated over a partial depletion SOI substrate, comprising: grounding a source terminal of the MOS transistor and connecting a gate of the MOS transistor to a word line; electrically connecting a metal layer at one end of the unipolar type RRAM to a drain terminal of the MOS transistor, and connecting a metal layer at the other end to a bit line; when performing a program operation, applying a high voltage of 1V˜2V to the word line to turn on the MOS transistor, and then applying a high voltage of 5V˜7V to the bit line to induce a floating effect of the MOS transistor, so that the unipolar type RRAM reaches a program voltage to perform the program operation; and when performing an erase operation, applying a high voltage level of 2V˜3V to the word line to turn on the MOS transistor, and applying a high voltage level of 4V˜6V to the bit line to induce a floating body effect of the MOS transistor, so that the unipolar type RRAM reaches an erase voltage to perform the erase operation.