Patent ID: 6818503
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device, the method which comprises:forming a CMOS structure in at least one region selected from the group consisting of a semiconductor substrate region, a passivation region, a surface region of the semiconductor substrate region and a surface region of the passivation region; forming a capacitor configuration in at least one region selected from the group consisting of the semiconductor substrate region, the passivation region, the surface region of the semiconductor substrate region and the surface region of the passivation region such that the capacitor configuration includes a plurality of capacitor devices serving as storage elements; providing at least first and second contact regions for contacting the capacitor devices to the CMOS structure; forming a first electrode device as a bottom electrode device, a second electrode device as a top electrode device and a dielectric between the first electrode device and the second electrode device for each of the capacitor devices; and forming at least some of the first and second contact regions with respective elevated regions in the passivation region such that the elevated regions are elevated above the surface region of the passivation region.