Patent ID: 6785629
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A method for testing an integrated circuit containing FeRAM cells, comprising:performing sensing operations that respectively compare reference voltages to a bit line voltage, wherein performing the sensing operations generates a result signal representing a series of values with each value distinguishing whether a comparison of a corresponding one of the reference voltages to the bit line voltage had a first result or a second result; generating a first data value identifying a first limit for a range of the reference voltages in which the sensing operations provided inconsistent results; and generating a second data value identifying a second limit for the range of the reference voltages in which the sensing operations provided the inconsistent results, wherein generating the first data value comprises: applying a data signal to a storage element, the data signal indicating which of the reference voltages corresponds to a current value of the result signal; precharging a line connected to the storage element, wherein precharging is performed only once before a first plurality of the sensing operations, and wherein precharging the line activates an enable signal that enables the storage element to set a stored value equal to a current value of the data signal; activating a drive circuit in response to the values of the result signal corresponding to the first plurality of the sensing operations, wherein the drive circuit when activated pulls the line to a state where the enable signal is deactivated, the storage element being disabled from changing the stored value while the enable signal is deactivated; and providing as the first data value, the stored value in the storage element after the first plurality of sensing operations.