Patent ID: 8713288
Filing Date: 2014-04-29
Classification: G06F

Abstract:
1. A storage system comprising: a plurality of storage devices that are configured to provide a plurality of logical volumes; and a controller, which receives from an external device an input/output request that specifies any of the plurality of logical volumes and processes the input/output request, wherein the controller comprises a first interface for communicating with the external device, a second interface for communicating with the storage devices, and a memory, the memory being respectively coupled to the first interface and the second interface, and a plurality of microprocessors, each of the plurality of microprocessors being respectively coupled to the first interface, the second interface, and the memory, wherein each of the plurality of microprocessors is configured to execute synchronous processing and asynchronous processing, wherein execution of the synchronous processing is triggered by the input/output request from the external device, and the asynchronous processing is processing other than the synchronous processing, wherein each of the plurality of microprocessors is configured to execute the synchronous processing up to a preset upper limit value, and is configured to execute the asynchronous processing when the synchronous processing is not executed, wherein upper limit value management information for correspondingly managing a first upper limit value and a second upper limit value for each of a plurality of prescribed modes is stored in a memory area that is used by the respective microprocessors, wherein the first upper limit value refers to an upper limit value of the number of times that synchronous processing with respect to the first interface may be executed from among the synchronous processing, wherein the second upper limit value refers to an upper limit value of the number of times that synchronous processing and asynchronous processing with respect to the second interface may be executed from among the synchronous processing and the asynchronous processing, wherein in a first mode, which is included in the plurality of modes, the first upper limit value is set higher than the second upper limit value, wherein in a second mode, which is included in the plurality of modes, the second upper limit value is set higher than the first upper limit value, wherein in a third mode, which is included in the plurality of modes, the first upper limit value and the second upper limit value are set equal to each other, wherein any one mode of the first mode, the second mode, or the third mode is set for each of the microprocessors, wherein which of the first mode, the second mode, or the third mode is to be set in each of the microprocessors is determined at a prescribed cycle based on a utilization rate of each of the microprocessors and an amount of unwritten data, which is stored only in the memory and has not been written to the storage device, wherein when the utilization rate is less than a prescribed utilization rate, the first mode is set, wherein when the utilization rate is equal to or larger than the prescribed utilization rate, and the amount of the unwritten data is equal to or larger than a prescribed data amount, the second mode is set, and wherein when the utilization rate is equal to or larger than the prescribed utilization rate, and the amount of the unwritten data is less than the prescribed data amount, the third mode is set.