Patent ID: 7125791
Filing Date: 2006-10-24
Classification: H01L

Abstract:
1. A method for forming a via interconnection structure, the method comprising: forming a first inter-level dielectric (ILD) over a substrate; forming a first trench in the first ILD; filling the first trench with conductive material to form a first conductive line; forming a via etch stop layer (ESL) over the first ILD and the first conductive line; forming a via ILD on the via ESL; forming a trench ESL on the via ILD; forming a trench ILD on the trench ESL; etching a via opening through the trench ILD, trench ESL, via ILD and stopping at the via ESL; etching a second trench through the trench ILD and stopping at the trench ESL; etching the trench ESL to form a substantially round bottom corner of the second trench; etching the exposed via ESL; wherein the second trench has at least one bottom round corner with a substantially rounded portion having a horizontal width greater than about one fifth the total width of the second trench and a height greater than about one fourth the total height of the second trench; and filling the via and the second trench with conductive material.