Patent ID: 6058263
Filing Date: 2000-05-02
Classification: G06F

Abstract:
A development system comprising:a single-chip component interface having a plurality of sets of configurable and externally accessible signal lines;a plurality of peripheral modules that are external to the single-chip component interface, each of the peripheral modules being connected to a respective unique set of the plurality of sets of configurable and externally-accessible signal lines, the peripheral modules also being connected in common to a common set of the configurable and externally-accessible signal lines;a CPU module, wherein the CPU module has connections to all of the sets of configurable and externally-accessible signal lines;the single-chip component interface having internal hardware interfaces corresponding to respective peripheral modules, the internal hardware interfaces being accessible only within the single-chip component interface, wherein the internal hardware interfaces are selected from a plurality of pre-defined internal hardware interfaces for general kinds of computer components;the single-chip component interface further including interconnection logic between the internal hardware interfaces;the single-chip component interface further including component-specific hardware interfaces for configuring the plurality of sets of configurable signal lines to which the peripheral modules are connected, the component-specific hardware interfaces connecting the peripheral modules to the internal hardware interfaces;the component-specific hardware interfaces being designed individually for the different peripheral modules to interface the peripheral modules to the internal hardware interfaces;wherein a CPU on the CPU module can be connected to any lines of the sets of the plurality of sets to control such interface lines in place of the single-chip component interface.