Patent ID: 6750504
Filing Date: 2004-06-15
Classification: G11C,H01L

Abstract:
A low voltage single-poly flash memory array comprising:a deep ion well of a first conductivity type; a first ion well of the first conductivity type formed on the deep ion well; a second ion well of a second conductivity type formed on the deep ion well and being in contact with the first ion well; a sector of memory cells comprising a plurality of memory cells, and each memory cell comprising: a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well; a gate located on the charge storage layer; a source of the second conductivity type located in the second ion well and being in contact with the charge storage layer; an ion doped region of the first conductivity type formed under and surrounding the source and at least a portion of a bottom of the first insulating layer; and a drain of the second conductivity type located in the second ion well and being in contact with the ion doped region and the charge storage layer; a selection bit line device having a first end, a second end, and a gate end for controlling the corresponding sector of memory cells, wherein the first end and the second end of the selection bit line device are formed within the first ion well, and the gate end is formed on the first ion well; an isolating region formed between the selection bit line device and the corresponding sector of memory cells; a main bit line electrically connected to the first end of the selection bit line device; and a sub-bit line electrically connected to the second end of the selection bit line device and memory cells of the corresponding sector of memory cells.