Patent ID: 8735944
Filing Date: 2014-05-27
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a gate electrode level region having at least seven adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the at least seven adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type, wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a third transistor of the first transistor type and a gate electrode of a second transistor of the second transistor type, wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the second transistor type, wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein the second transistor of the first transistor type and the third transistor of the second transistor type are located on opposite sides of the third gate level feature in the second direction, wherein the third transistor of the first transistor type is electrically connected to the fourth transistor of the first transistor type in a serial manner through a diffusion region shared by the third and fourth transistors of the first transistor type, and wherein the gate electrode of the third transistor of the second transistor type is positioned between the gate electrodes of the second and fourth transistors of the second transistor type in the second direction.