Patent ID: 8954779
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. A timer module connectable to an external arithmetic unit, comprising: a status register; an input, wherein output signals of the timer module are fed back into the input; a multi-channel sequence which checks the fed-back output signals for predefined signal characteristics including at least one of a signal length, a signal level, and a signal period; means for generating at least one activity signal for a process within the timer module, wherein the activity signal is output by the multi-channel sequencer when the check of the predefined signal characteristics is carried out; and means for (i) entering an activity status into a status register in the event of a determined activity, and (ii) allowing the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit, wherein the activity status entered into the status register remains until reset by the external arithmetic unit.