Patent ID: 6457157
Filing Date: 2002-09-24
Classification: G06F,H01L

Abstract:
An apparatus for laying out input/output (I/O) pairs, each comprising an I/O cell and a pad, on an integrated circuit die, said apparatus comprising:a processor for executing stored program instruction steps; and a memory connected to the processor for storing the program instruction steps, wherein the program instruction steps include steps to: (1) obtain plural I/O pairs, wherein each I/O pair includes layout information for an I/O cell, a pad and a connection between the I/O cell and the pad; (2) obtain cell, pad and connection information for each of a first I/O pair and a second I/O pair; (3) determine a minimum spacing criterion which specifies a minimum distance between the first I/O pair and the second I/O pair, wherein the minimum spacing criterion is based on the cell, pad and connection information for each of the first I/O pair and the second I/O pair; and (4) layout the first I/O pair and the second I/O pair so as to satisfy the minimum spacing criterion.