Patent ID: 6507862
Filing Date: 2003-01-14
Classification: G06F

Abstract:
A method of operating a processor comprising:running one or more program applications concurrently; executing a plurality of execution threads in a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications; switching the execution threads in the multiple-thread pipeline including: freezing an active state in the pipeline; activating a previously idle thread in the pipeline while holding the state of the newly frozen thread in the pipeline; and subsequently resuming execution of the frozen thread at the precise state of the frozen thread immediately prior to the thread switch; wherein the multiple-thread pipeline includes a plurality of pulse-based high-speed flip-flops, the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.