Patent ID: 6505149
Filing Date: 2003-01-07
Classification: G06F,H04L

Abstract:
A method for verifying a source-synchronous communication interface of a device, said method comprising the steps of:providing a software model of a first device having a source-synchronous communication interface, wherein said source-synchronous communication interface includes an applied clock line, a request line, an echo clock line, and a response line; providing a software model of a second device capable of communicating with said first device via said source-synchronous communication interface; simulating a sending of a request from said first device model to said second device model via said request line along with an applied clock signal on said applied clock line; receiving a response from said second device model to said first device model via said data line after various delays between said applied clock signal on said applied clock line and an echo clock signal on said echo clock line; and verifying whether or not said response received by said first device model is correct.