Patent ID: 7851898
Filing Date: 2010-12-14
Classification: G11C,H01L

Abstract:
1. A semiconductor package constructed by mounting, on a front surface of a package substrate, at least one memory chip and a logic chip for controlling the at least one memory chip, wherein: the package substrate has four layers and a rear surface, a first pin is provided on the rear surface of the package substrate and electrically connected to the logic chip, a second pin is provided on the rear surface of the package substrate for transmitting a test signal and transmitting a logic signal, the logic chip includes a selector circuit which is configured to switch, in response to a test mode select signal, a signal path from a normal operation mode to a test mode which enables access from the second pin to a memory control signal to the at least one memory chip, the second pin transmits the test signal when the selector is in a test mode and transmits the logic signal when the selector circuit is in a normal operation mode, and power supply wiring for the logic chip and power supply wiring for the at least one memory chip are allocated to either the third layer of the package substrate or the third layer and next lower layer of the package substrate in the package substrate including at least four wiring layers, said allocated power supply wiring for the logic chip supplying electric power thereto by being connected from a power supply pin for the logic chip to thereto via the allocated power supply wiring for the logic chip, said allocated power supply wiring for the at least one memory chip supplying electric power to each thereof by being connected from power supply pins for the at least one memory chip to each thereof via the allocated power supply wiring for the at least one memory chip.