Patent ID: 6413824
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of fabricating an integrated circuit, comprising the steps of:forming a plurality of isolation structures in a semiconductor body; forming a plurality of gate structures over said semiconductor body; forming a first masking layer exposing the first type of low voltage transistor and masking the second type of low voltage transistor and the higher voltage transistor prior to forming the first drain extension regions; forming first drain extension regions in a first type of low voltage transistor; removing the second masking layer after forming the first drain extension regions; forming pocket regions in said first type of low voltage transistor; forming a second masking layer exposing tile higher voltage transistor and the second type of low voltage transistor and masking the first type of low voltage transistor prior to forming the second drain extension regions; simultaneously forming second drain extension regions in a higher voltage transistor and in at least a drain side of a second type of low voltage transistor; and removing the second masking layer after forming the second drain extension regions.