Patent ID: 7408814
Filing Date: 2008-08-05
Classification: G11C

Abstract:
1. A memory device, comprising: a memory core comprising an array of memory cells, sense amplifier circuitry to sense data from the array, a latch to latch sensed data, and an address transition detector and read timer to generate a sense amplifier latch signal when data is addressed and sensed from the array; an output buffer to provide data to an output; and a data path circuit between the memory core and the output buffer along which data is propagated from the array of memory cells to the output, the data path circuit having a first path for data, comprising a first data path driver and a data latch in series; and a second path for a data latch enable signal, comprising a second data path driver identical to the first data path driver and logic to enable a first filtered configuration or a second non-filtered configuration.