Patent ID: 7230861
Filing Date: 2007-06-12
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising a plurality of memory units, a logic circuit connected to said plurality of memory units and a plurality of scan flip-flops for carrying out a scan test on said logic circuit; a first operation mode for carrying out a test on said memory units, and a second operation mode for accessing to said memory units from said logic circuit being defined; a first data shift circuit having a plurality of stages of registers corresponding to said plurality of memory units, for inputting testing input data to a register in a first stage among said plurality of stages and shifting the same to registers in the subsequent stages in said first operation mode; and a first selection circuit for selecting said testing input data, shifted and outputted from said respective registers in the corresponding stages in said first operation mode, and selecting data output from said logic circuit in said second operation mode, to determine the data input to the memory units, the respective registers of said first data shift circuit being formed by said scan flip-flops.