Patent ID: 7755089
Filing Date: 2010-07-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a p-type first semiconductor region formed on the semiconductor substrate; an n-type second semiconductor region formed on the semiconductor substrate so as to be insulated from the first semiconductor region; an n-channel MOS transistor formed on the first semiconductor region; and a p-channel MOS transistor formed on the second semiconductor region, the n-channel MOS transistor including: a first pair of source/drain regions formed opposite to each other on the first semiconductor region; a first gate insulating film formed from a single layer of an amorphous insulating film containing at least La, and formed in direct contact with the first semiconductor region interposed between the first pair of source/drain regions; and a first gate electrode formed in direct contact with the first gate insulating film, the p-channel MOS transistor including: a second pair of source/drain regions formed opposite to each other on the second semiconductor region; a second gate insulating film having a stacked structure formed of a silicon oxide film and a second film thereon formed from the amorphous insulating film, the silicon oxide film being formed on the second semiconductor region interposed between the second pair of source/drain regions; and a second gate electrode formed in direct contact with the second film of the second gate insulating film.