Patent ID: 7119435
Filing Date: 2006-10-10
Classification: H01L,Y10S

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a gate structure including a gate insulating layer and a gate electrode that are successively formed on the semiconductor substrate; a first insulating layer formed on a top and a first and a second side of the gate structure; a second insulating layer formed on the substrate and spaced apart from the first insulating layer; a lightly doped source/drain region formed in the surface portions of the substrate between the gate structure and the second insulating layer; a source/drain extension layer formed on the lightly doped source/drain regions; a heavily doped source/drain region formed on the second insulating layer and in contact with the source/drain extension layer; and a gate spacer disposed between the heavily doped source/drain region and the gate structure, the gate spacer including an insulating material, a maximum width of the gate spacer substantially the same as a width of the source/drain extension layer.