Patent ID: 8952442
Filing Date: 2015-02-10
Classification: G11C,H01L

Abstract:
1. A method comprising: forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other; etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess; implanting a top surface layer and a side surface layer of the second active region to form an implantation region, wherein the side surface layer of the second active region extends from the sidewall of the second active region into the second active region; oxidizing an upper portion of the top surface layer and an upper portion of the side surface layer to form a capacitor insulator; and forming a floating gate extending over the first active region and the second active region, wherein the floating gate comprises a portion extending into the recess.