Patent ID: 7492011
Filing Date: 2009-02-17
Classification: H01L

Abstract:
1. A semiconductor device including ESD protective circuits for enhancing a tolerance to an electrostatic discharge breakdown, comprising: a substrate of a first conductive type, a first region forming a plurality of first ESD protective circuits in a finger structure, and a second region forming a plurality of second ESD protective circuits in the finger structure, wherein each of the first ESD protective circuits includes: a first transistor having a first gate electrode, and a first drain electrode including a first diffusion region of a second conductive type, and a first ballast resistance including a second diffusion region of the second conductive type connected to the first diffusion region in a direction apart from the first gate electrode, with an impurity concentration lower than the concentration of the first diffusion region, and each of the second ESD protective circuits includes: a second transistor having a second gate electrode, and a second drain electrode including a third diffusion region of the second conductive type, having dielectric strength of a gate oxide lower than that of the first transistor, and a second ballast resistance including a fourth diffusion region of the second conductive type connected to the third diffusion region in a direction apart from the second gate electrode, with the impurity concentration higher than the concentration of the second diffusion region.