Patent ID: 9087952
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. An integrated photonic semiconductor structure comprising: a substrate; a photonic device located on the substrate; a CMOS device located on the substrate and electrically isolated from the photonic device; and a multi-layer stack including a first silicon nitride layer having a first stress property, an oxide layer having a stress property, and a second silicon nitride layer having a second stress property, the multi-layer stack encapsulating the photonic device, wherein the first silicon nitride layer is located over an active region of the photonic device and in direct contact with opposing sidewalls of the active region, the oxide layer is located over the first silicon nitride layer, and the second silicon nitride layer is located over the oxide layer, the first silicon nitride layer, the oxide layer, and the second silicon nitride layer comprise graded stress properties such that the oxide layer includes a larger stress than the first silicon nitride layer and the second silicon nitride layer has a larger stress than the oxide layer.