Patent ID: 7099416
Filing Date: 2006-08-29
Classification: G09G,H04J,H04L

Abstract:
1. A receiver that receives high rate bit stream data, the receiver comprising: a plurality of data buffers, each of which couples to a transmission path carrying a respective high rate serial bit stream, wherein each of the plurality of data buffers includes: an input that receives the respective high rate serial bit stream; buffering circuitry that buffers the respective high rate serial bit stream; and an output that produces a buffered representation of the respective high rate serial bit stream; a clock buffer that receives and buffers a clock signal corresponding to the high rate bit stream data and includes: an input that receives the clock signal; buffering circuitry that buffers the clock signal; and an output that produces a buffered representation of the clock signal; and clock termination circuitry coupled to a transmission path that carries the clock signal, wherein the clock termination circuitry applies a terminating impedance to the transmission path that carries the clock signal during a first operating condition, and wherein the clock termination circuitry applies a high impedance to the transmission path that carries the clock signal during a second operating condition.