Patent ID: 6448835
Filing Date: 2002-09-10
Classification: G06F,H03L

Abstract:
A circuit for providing a gated output timing signal, said circuit comprising:a timing signal input providing a timing signal; a complementary timing signal input providing a complementary timing signal; gating logic that gates a timing signal from said signal input, wherein said gating logic includes a gating signal input, wherein said gating logic comprises: a first combinatorial logic block coupled to said timing signal input that generates a first gated timing signal; and a second combinatorial logic block coupled to said complementary timing signal input that generates a second gated timing signal; and circuit means for providing a gate signal to said gating logic, wherein said circuit means provides a full-cycle path for said gate signal to said gating signal input, said circuit means for providing a gate signal to said gating logic including a pair of serially coupled shift register latches, wherein each of said pair of shift register latches includes a first latch control input receiving said timing signal from said timing signal input and a second latch control input receiving said complementary timing signal from said complementary timing signal input, said pair of shift register latches generating a first gate signal for gating said first combinatorial logic block and a second gate signal for gating said second combinatorial logic block.