Patent ID: 6530013
Filing Date: 2003-03-04
Classification: G06F

Abstract:
An instruction control apparatus comprising:address unit holding an address from which to fetch an instruction word, and for updating said address; storage unit holding said fetched instruction word; a fetch control circuit, prior to instruction execution in an execution stage, fetching one or more instruction words into said storage unit in accordance with the address indicated by said address unit; a selection circuit selecting a portion of an instruction sequence held in said storage unit, starting from the beginning of the next instruction word to be loaded into said execution stage, pointed to by a pointer, and extending until reaching a maximum length of instructions that can be loaded into said execution stage, and which, from within said selected portion, selects a plurality of instructions to be loaded into said execution stage, based on a minimum instruction length unit and on the length of each of said instructions; and a plurality of loading ports holding the instructions selected by said selection circuit.