Patent ID: 8972828
Filing Date: 2015-03-03
Classification: H03M

Abstract:
1. A method of providing for error mitigation in a chip for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method comprising: grouping in the chip a pre-selected number of high speed interconnect protocol words to form a protection frame; adding in the chip at least one additional error protection bit to each word in said grouped words; adding in the chip a synchronization bit to each word; and sending the words over a serial interface, wherein the synchronization bit in a first word in each frame provides for synchronization of said protection frame; and wherein the at least one additional error protection bit in each word of the protection frame is used collectively with the other additional error protection bits as a single error correction code that provides for detecting and correcting a single bit error in the protection frame.