Patent ID: 7227808
Filing Date: 2007-06-05
Classification: G11C

Abstract:
1. A memory device having a plurality of data paths for receiving data, wherein the data paths comprise a plurality of data storage units adapted to store data, including: a first stage of data storage units adapted to asynchronously store the data; and at least one second stage of data storage units adapted to synchronously store the data output from the first stage of data storage units, wherein the first stage of data storage units are adapted to store data in response to a latch clock signal, and wherein the second stage of data storage units are adapted to store the data output from the first data storage units in response to a reference clock signal, and wherein the latch clock signal comprises a plurality of sub latch clock signals each corresponding to one of the plurality of data paths, wherein each sub latch clock signal is obtained by delaying the reference clock signal, and wherein each sub latch clock signal is generated at a different time according to a propagation delay time of the data input in the corresponding data path.