Patent ID: 8659140
Filing Date: 2014-02-25
Classification: G11C,H01L

Abstract:
1. A microelectronic package, comprising: a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function; a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface facing the element contacts of the microelectronic element and joined to the element contacts; and a plurality of terminals on the second surface of the substrate configured for connecting the microelectronic package with at least one component external to the microelectronic package, the terminals electrically connected with the substrate contacts and including first terminals arranged at positions within first and second parallel grids, each grid disposed on a respective side of an axis, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, the terminals including second terminals arranged at positions within third and fourth parallel grids and configured to carry second information, the second information being other than the information carried by the first terminals, the second information including data signals, wherein the first and second grids separate the third and fourth grids from one another, the first terminals having signal assignments, wherein the signal assignments of the first terminals in the first grid are symmetric about the axis with the signal assignments of the first terminals in the second grid, such that of the first terminals of the first grid that are configured to carry address information, each of such first terminals is configured to carry the same address information as a corresponding one of the first terminals of the second grid at a position symmetric about the axis with respect to such first terminal.