Patent ID: 7467243
Filing Date: 2008-12-16
Classification: G06F,H04L

Abstract:
1. An advanced processor having a plurality of processor cores connected to a plurality of fast messaging ring components, the fast messaging ring components comprising: a ring input coupled to an insertion queue and a receive queue, and a multiplexer; the multiplexer having a first input coupled to the ring input by way of the insertion queue and configured to provide a ring output; a transmit queue coupled to a second input of the multiplexer; a plurality of receive buffers coupled to the receive queue; a plurality of transmit buffers coupled to the transmit queue; and a plurality of registers; said fast messaging ring components being connected together in a ring configuration; in which each processor core is connected to its own individual fast messaging ring component, and in which each processor core is not always required to participate in exchanging messages on said fast messaging ring component when said fast messaging ring is transmitting messages between a prior ring component and a next ring component.