Patent ID: 8659009
Filing Date: 2014-02-25
Classification: B82Y,H01L

Abstract:
1. An electronic device comprising: a graphene layer comprising first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction; a local first gate region, separated from the graphene nanoconstriction by a first gate dielectric, the local first gate region configured to be capacitively coupled to gate electrical conduction in the graphene nanoconstriction; a transistor, including the first and second terminal regions and the local first gate region, the first gate dielectric including a first layer of hydrogen silsesquioxane (HSQ) and a second layer including a dielectric material grown directly on the first layer by atomic layer deposition; and a second gate region, separated from the graphene nanoconstriction by a second gate dielectric, the second gate region configured to be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction.