Patent ID: 8232635
Filing Date: 2012-07-31
Classification: H01L

Abstract:
1. A hermetically sealed semiconductor package comprising: a power semiconductor die including at least a first power electrode, a control electrode and a second power electrode disposed opposite said first power electrode; a substrate having a thermally conductive but electrically insulating body, at least one conductive pad on a first surface of said thermally conductive but electrically insulating body connected by a conductive adhesive body to said first power electrode, and at least another conductive pad on said first surface connected by another conductive adhesive body to said control electrode; at least a first external terminal and a second external terminal each being electrically connected to a respective one of said conductive pads through a respective conductive filled via inside said substrate; a thermally conductive but electrically insulating surround hermetically connected to said substrate and surrounding said power semiconductor die; another substrate having a thermally conductive but electrically insulating body, and having a third conductive pad electrically connected to said second power electrode by a third conductive adhesive body, said another substrate being hermetically attached to said surround; a third surface mountable terminal electrically connected to said third conductive pad through a conductive filled via inside said another substrate and disposed opposite said first and second external terminals; said substrate, said another substrate, and said surround creating a hermetically sealed space providing double-sided cooling in both the vertical and lateral directions around said power semiconductor die, and wherein said first external terminal, said second external terminal, and said third surface mountable terminal are outside said hermetically sealed space.