Patent ID: 6159793
Filing Date: 2000-12-12
Classification: H01L,Y10S

Abstract:
A method of fabricating a stacked capacitor, comprising steps of:providing a substrate;forming a first dielectric layer on the substrate;forming a contact in the first dielectric layer;forming a doped polysilicon layer to fill the contact;forming an insulating layer to cover the first dielectric layer;forming an opening in the insulating layer to expose the contact;forming a crown shaped amorphous silicon layer to cover the opening;forming a plurality of hemispherical grains (HSG) polysilicon on an exposed surface of the crown shaped amorphous silicon layer;forming a first metal layer as a lower electrode of the capacitor, the first metal layer is formed from the HSG polysilicon and the crown shaped amorphous silicon layer by a selective metal deposition;forming a second dielectric layer to cover the first metal layer; andforming a second metal layer to cover the second dielectric layer, wherein the second metal layer as an upper electrode of the capacitor.