Patent ID: 7869248
Filing Date: 2011-01-11
Classification: G11C

Abstract:
1. A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: R first sub-decoders that communicate with R memory sub-arrays of said memory array, respectively, where R is an integer greater than 1, wherein R isolation circuits each having (i) first ends that communicate with said R first sub-decoders, respectively, and (ii) second ends, wherein said second ends of a first of said R isolation circuits communicate with corresponding said second ends of (R-1) or said R isolation circuits; a second sub-decoder that communicates with one of said R first sub-decoders via said second ends of said R isolation circuits; and a sensing circuit that (i) communicates with said second sub-decoder and (ii) senses a state of one of said memory cells located within one of said R memory sub-arrays via said second ends.