Patent ID: 6130851
Filing Date: 2000-10-10
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a first pad for receiving a first potential voltage from outside of said device and supplying the first potential voltage;a second pad for receiving a second potential voltage from outside of said device and supplying the second potential voltage;a redundant fuse having a first terminal connected to the first pad and a second terminal connected to the second pad, said redundant fuse being made of a material broken by an electric current flowing therethrough when the first and second potential voltage are applied to said first and second pads;a detector circuit connected to one of the first and second terminals of said redundant fuse for outputting a detecting signal in response to a potential applied thereto from the one of the first and second terminals of said redundant fuse;a selector circuit for selectively transferring input data to either a normally-used memory cell or a redundant memory cell in response to the detecting signal; anda control circuit for supplying a third potential voltage to the other of first and second terminals of said redundant fuse in response to a redundancy cut enable signal.