Patent ID: 6727542
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A semiconductor memory device comprising:an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate; a plurality of MOS transistors, comprising source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area; a bit line, formed on the plurality of MOS transistors and electrically connected to the MOS transistor; a stack-shaped capacitor, comprising a first electrode, a dielectric layer, and a second electrode, the bit line and the MOS transistors in the cell area being disposed beneath the stack-shaped capacitor; a guard-ring pattern, interposed between the cell area and the peripheral circuit area, surrounding the cell area and being spaced apart from the peripheral circuit area; and a contact fill for a plate electrode formed in the guard-ring pattern and in contact with the second electrode, the second electrode being formed on the internal sidewall and the bottom of the guard-ring pattern.