Patent ID: 6678819
Filing Date: 2004-01-13
Classification: G06F

Abstract:
Pipeline microprocessor (MP1, MP2) comprising:a program counter (PC), means (DEC1, DEC2, DEC3) to decode a set of instructions of the microprocessor, means (FIG. 1 PREDEC, FIG. 2 DEC3) to decode a conditional jump instruction (JMPc) that are designed to deliver an address selection signal (SEL), laid out in a first pipeline stage (ST1) and connected to a second output (S2) of a computation unit (ALU), a computation unit (ALU) laid out in a second pipeline stage (ST2) neighboring the first pipeline stage (ST1), comprising a first output (S1) to deliver a result and a second output (S2) to deliver status bits (C, N, P, Z) of the result, a circuit (SPC) for the incrementation of the program counter (PC), comprising means (MUX, ADD) for the delivery, as a function of said address selection signal (SEL), of a read address of an immediately following instruction or a jump address determined by the contents (VAL) of a conditional jump instruction (JMPc), the first and second pipeline stages (ST1, ST2) each comprising a first sector (ST11, ST21) and a second sector (ST12, ST22), the first sector (ST11, ST21) of each stage (ST1, ST2) being active only during a first clock half-cycle (H1) and the second sector (ST12, ST22) of each stage (ST1. ST2) being active only during a second clock half-cycle (H2), the computation unit (ALU) is laid out in the first sector (ST21) of the second pipeline stage (ST2), the circuit (SPC) for the incrementation of the program counter (PC) is laid out in the second sector (ST12) of the first pipeline stage (ST1), the address selection signal (SEL) is applied to the circuit (SPC) for the incrementation of the program counter during the first clock half-cycle (H1).