Patent ID: 8361852
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method of manufacturing a transistor, the method comprising: forming a silicon germanium channel layer on a portion of a single crystalline silicon substrate; forming a first gate structure and a second gate structure, each of the first and second gate structures including a gate oxide layer pattern, a conductive layer pattern and a polysilicon layer pattern on the single crystalline silicon substrate and the silicon germanium channel layer; forming a first impurity region by doping n-type impurities into the single crystalline silicon substrate at both sides of the first gate structure; forming a second impurity region by doping p-type impurities into the silicon germanium channel layer at both sides of the second gate structure; and forming a silicon nitride layer on a surface of the single crystalline silicon substrate, the silicon germanium channel layer and the first and second gate structures, the silicon nitride layer operable to remove dangling bonds at an inner portion and/or a surface portion of the silicon germanium channel layer via a depositing gas that includes a reacting gas, an atmosphere gas and a hydrogen gas, and wherein the silicon nitride layer is operable to apply a tensile stress.