Patent ID: 8415973
Filing Date: 2013-04-09
Classification: H03K

Abstract:
1. An integrated circuit (“IC”) comprising: a plurality of configurable nodes arranged in an array having a plurality of rows and a plurality of columns, the plurality of configurable nodes comprising a first group of configurable nodes aligned along a first direction and a second group of configurable nodes aligned along a second direction, wherein the first direction and second direction intersect at a particular location; a set of nested direct offset connections comprising (i) a first direct offset connection that connects a first node from the first group of configurable nodes with a second node from the second group of configurable nodes, and (ii) a second direct offset connection that connects a third node from the first group of configurable nodes with a fourth node from the second group of configurable nodes, wherein a distance between the third node and the particular location in the first direction is greater than a distance between the first node and the particular location in the first direction, wherein a distance between the fourth node and the particular location in the second direction is greater than a distance between the second node and the particular location in the second direction.