Patent ID: 7965555
Filing Date: 2011-06-21
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a NAND string, in which a plurality of memory cells are connected in series and first and second select gate transistors are disposed on the both ends for coupling them to a bit line and a source line, respectively; a plurality of word lines coupled to the respective control gates of the memory cells; and first and second select gate lines coupled to the gates of the first and second select gate transistors, respectively, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side of the selected word line is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side of the selected word line are applied with a third read pass voltage higher than the first read voltage.