Patent ID: 7060570
Filing Date: 2006-06-13
Classification: H01L,Y10S

Abstract:
1. A method of fabricating multiple sets of field effect transistors, comprising: forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate, the etch stop layer and the insulative capping layer each being insulative and of different compositions; patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate; forming and anisotropically etching an insulative spacer forming layer over the first set of conductive gate constructions effective to form insulative spacers, the etch stop layer restricting etching of the insulative capping layer during the anisotropically etching, the anisotropically etching forming the spacers to have elevationally outermost surfaces which are elevationally lower than elevationally outermost surfaces of the etch stop layer and which are elevationally higher than elevationally innermost surfaces of the etch stop layer; after forming the insulative spacers, forming and planarizing a dielectric material over the first set of gate constructions; and after forming and planarizing the dielectric material, patterning and etching the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate.