Patent ID: 6912702
Filing Date: 2005-06-28
Classification: G06F

Abstract:
1. A method of generating a scalable cell model for an integrated circuit cell comprising the steps of: a) accessing a technology library comprising a plurality of cell groups each cell group comprising a plurality of discrete cells that share a common logic function but are of different cell sizes, each discrete cell having a corresponding output load-based non-linear delay model; b) generating a metric for a selected cell group that measures a cell characteristic over all discrete cells of said selected cell group; c) generating, based on said metric, a cell cluster for said selected cell group by selecting a subset of discrete cells of said selected cell group that are similar in terms of said cell characteristic; d) generating a gain-based delay model for said scalable cell model based on output load-based non-linear delay models of said discrete cells of said cell cluster, said gain-based delay model receiving an input gain value and providing, based thereon, an output delay value; and e) storing said gain-based delay model within a computer memory.