Patent ID: 6385126
Filing Date: 2002-05-07
Classification: G06F,G11C,H03L

Abstract:
A clock synchronization circuit for synchronizing an external clock signal with an internal clock signal, the circuit being connected to a clock buffer adapted to output the internal clock signal, the circuit comprising:a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween; and a second loop adapted to delay the plurality of reference clock signals, select a signal from among the plurality of delayed reference clock signals, provide the selected signal to the clock buffer, detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal, generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages, so as to synchronize the internal clock signal with the external clock signal.