Patent ID: 8243865
Filing Date: 2012-08-14
Classification: H03M

Abstract:
1. A data processing apparatus comprising: a binarization unit binarizing input data based on a threshold voltage and configured to output only a binary output from a single connection point between a drain of a PMOS transistor and a drain of a NMOS transistor; a capture unit capturing data from the binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit, implemented via a processor, controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit and configured to output only a single control signal directly into a gate of another PMOS transistor of the binarization unit, wherein a drain current value of the another PMOS transistor is varied in accordance with a change of the single control signal, wherein the duty cycle detection unit is configured to detect the duty cycle of the binary output from an average value of the binary output and pulse values when the binary output is at a high (H) level and at a low (L) level.