Patent ID: 6198171
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A thermally enhanced quad flat non-lead package of semiconductor comprising:a chip, having an active surface and a corresponding back surface wherein the active surface comprises a plurality of bonding pads;a die pad, having a first surface and a corresponding second surface wherein the area of the die pad is smaller than the area of the chip, and the die pad has the first surface bonded to the active surface of the chip while those bonding pads on the active surface of the chip are exposed;a plurality of leads, disposed at the periphery of the die pad, and having a first surface and a corresponding second surface wherein the second surface appears a stepped structure which make each of the leads have a relatively thin wire-bonding protruded zone, and the second surface of the die pad and the second surface of the lead are coplaner;a plurality of bonding wires, electrically connected to those bonding pads and to the wire-bonding protruded zone of the second surface of those leads respectively; anda molding compound, encapsulating the chip, the die pad, the first surface of those leads, the wire-bonding protruded zone, and those bonding wires but leaving the second surface of the die pad exposed in order to form a package structure, and the package structure comprises a first side and a second side wherein the molding compound exposes at least the portion excluding the wire-bonding protruded zone on the second surface of those leads at the second side of the package structure.