Patent ID: 6166979
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix in which memory cells in one row are connected by a common word line and memory cells in one column are connected by a common bit line; anda plurality of sense circuits for detecting and amplifying a potential of said bit line and for holding data corresponding to the potential of said bit line,wherein each of said sense circuits includes:a first sense amplifier connected to a bit line through a first MOS transistor;a second sense amplifier connected to said bit line through a second MOS transistor;a first bus line to which an output terminal of said first sense amplifier is connected through at least one first column gate; anda second bus line to which an output terminal of said second amplifier is connected through at least one second column gate.