Patent ID: 6246612
Filing Date: 2001-06-12
Classification: G11C,H01L,Y10S

Abstract:
A method of erasing a nonvolatile memory cell in a chip, said cell comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, further referred to as the floating-gate channel, a control gate extending over another portion of the channel region, further referred to as the control-gate channel, and an additional program gate capacitively coupled through a dielectric layer to said floating gate, said method comprising the steps of:applying a first negative voltage to the program gate; thereby coupling a second negative voltage to said floating gate; andapplying a third positive voltage to the control gate; to thereby establish a high electric field across the dielectric between the control gate and the floating gate, and to thereby cause a tunneling current to flow from the floating gate towards the control gate.