Patent ID: 6256722
Filing Date: 2001-07-03
Classification: G06F,H04L

Abstract:
A data processing system comprising;(A) a plurality of nodes;(B) a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information; and(C) at least one processing node including(a) a processor,(b) a printed circuit board,(c) a memory partitioned into a plurality of sections, a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory, and(d) a local bus connecting said processor, said block sharable memory, and said printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board,(e) the printed circuit board having(i) a sensor for sensing when data is transferred into said directly sharable memory,(ii) a queuing device for queuing said sensed data,(iii) a serializer for serializing said queued data,(iv) a transmitter for transmitting said serialized data onto said serial data bus to a next successive processing node,(v) a receiver for receiving serialized data from a preceding processing node, and(vi) a deserializer for deserializing said received serialized data into parallel data.