Patent ID: 6169436
Filing Date: 2001-01-02
Classification: H03K

Abstract:
A delay circuit for providing an output signal that has a delay with respect to an input signal, the delay being adjustable as a function of a delay instruction, said delay circuit comprising: a primary circuit that receives the input signal and outputs first and second intermediate signals, there being a fixed delay between the first and second intermediate signals; a combination circuit that receives the first and second intermediate signals and outputs a combination signal; and a shaping circuit that receives the combination signal and outputs the output signal based on a threshold level, wherein the combination circuit includes: a control input that receives a control variable representing the delay instruction; a capacitor connected between a common line and a first supply potential; and first and second circuit modules that charge and discharge the capacitor through the common line, the first circuit module being controlled by the first intermediate signal and the second circuit module being controlled by the second intermediate signal, the common line providing the combination signal, wherein each of the circuit modules includes a charging circuit and a discharging circuit, each of the discharging circuit having a switch for selectively coupling the common line to the first supply potential through one variable resistor and one non-variable resistor that are connected in parallel, each of the charging circuits having a switch for selectively coupling the common line to a second supply potential through one variable resistor and one non-variable resistor that are connected in parallel, wherein the non-variable resistor is independent of the control variable received on the control input and the non-variable resistor causes each of the first and the second circuit modules to contribute current so as to form the output signal which is linear over a time period provided by the delay instruction, the switches of the charging and discharging circuits being controlled by the first and second intermediate signals from the primary circuit.