Patent ID: 8724722
Filing Date: 2014-05-13
Classification: H04L

Abstract:
1. An apparatus comprising: a radio frequency (RF) interface; and a processor configured to process downlink information such that a downlink data processing latency of said apparatus is determined by an amount of time involved in (i) processing the downlink information and mapping complex-valued modulation symbols for a single orthogonal frequency division multiplexed (OFDM) symbol onto resource elements of a respective antenna port and (ii) generating a complex-valued time-domain OFDM signal for the respective antenna port from the single OFDM symbol mapped onto the resource elements of the respective antenna port for presentation to the RF interface, wherein a processing chain of said processor is configured to process each OFDM symbol individually by scrambling coded bits in one or more code words to be transmitted on a physical channel, generating the complex-valued modulation symbols based upon the scrambled coded bits, mapping the complex-valued modulation symbols onto a transmission layer, precoding the complex-valued modulation symbols on the transmission layer for transmission on the respective antenna port, and mapping the precoded complex-valued modulation symbols onto the resource elements of the respective antenna port.