Patent ID: 8673783
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate; performing a chemical mechanical polishing (CMP) process to planarize the metal conductor, a barrier layer comprising silicon nitride (Si cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process; rinsing the cleaned metal conductor and dielectric layer with an alcohol; drying the rinsed metal conductor and dielectric layer in an inert gas environment, wherein the IC wafer is provided through a first front opening unified pod (FOUP) of a CMP tool, the CMP process is performed in a CMP unit of the CMP tool, the cleaning and rinsing is performed in a cleaning unit of the CMP tool, and the drying is performed in a drying unit of the CMP tool; and transferring the dried wafer for further processing through a second FOUP of the CMP tool operating in an inert gas environment, wherein the second FOUP is operably coupled to the drying unit.