Patent ID: 6691200
Filing Date: 2004-02-10
Classification: G06F

Abstract:
A multi-port bus bridge comprising:a plurality of at least three port-sections coupled together, each port-section comprising: a bus interface for coupling to an external bus, wherein each port-section has a bus interface for coupling to a different external bus; a first data first-in-first-out (FIFO) for storing data words from a port-section acting as a first source port, the first data FIFO outputting the data words to the bus interface for transmission of the data words to the external bus; a second data first-in-first-out (FIFO) for storing data words from another port-section acting as a second source port, the second data FIFO outputting the data words to the bus interface for transmission of the data words to the external bus; a posted-write address FIFO, coupled to receive addresses from both the first and second source ports for posted-write bus transactions, the posted-write address FIFO outputting an address to the bus interface that is transmitted during a posted-write bus transaction to the external bus with data words from the first data FIFO when the address was received from the first source port, and data words from the second data FIFO when the address was received from the second source port; a request address FIFO, coupled to receive addresses from both the first and second source ports for request bus transactions, the request address FIFO outputting an address to the bus interface that is transmitted during a request bus transaction to the external bus; a completion address FIFO, coupled to receive addresses from both the first and second source ports for completion bus transactions, the completion address FIFO outputting an address to the bus interface that is transmitted during a completion bus transaction to the external bus; and an address multiplexer, coupled to the posted-write address FIFO, the request address FIFO, and to the completion address FIFO, for delaying the address from the second source port when addresses of a same type from both the first and second source ports are received concurrently, the address multiplexer for merging addresses from the first and second source ports into the posted-write address FIFO, the request address FIFO, and to the completion address FIFO, whereby the posted-write address FIFO, the request address FIFO, and to the completion address FIFO each store addresses from both the first and second source ports, but the first data FIFO stores data words from only the first source port while the second data FIFO stores data words from only the second source port.