Patent ID: 6599774
Filing Date: 2003-07-29
Classification: H01L

Abstract:
A method for making an electronic component comprising an assembly of a plurality of electrically connected stacked integrated circuit chips and an interconnection substrate, wherein peripheral conductive pads on a top chip of the stacked assembly are electrically connected to corresponding pads on the surface of the interconnection substrate by solder connections between their corresponding pairs of pads the method comprising the steps of:providing an integrated circuit chip electrically connected stacked assembly containing a plurality of chips having a top chip and a bottom chip wherein the top chip of the assembly has a larger width and length and a larger surface area than other chips in the assembly and contains peripheral pads which are electrically connected to corresponding pads on the surface of an interconnection substrate by a plurality of solder connections forming a space between the pad containing surface of the top chip and the pad containing surface of the substrate with the other chips of the stacked assembly being enclosed in a cavity in the substrate, the cavity having an open area smaller than the surface area of the top chip and an open area larger than the other chips, which cavity accommodates and encloses the bottom chip and other chips of the assembly other than the top chip; providing a fluid encapsulant; and supplying the encapsulant to the cavity through a through opening in the substrate extending from a surface of the substrate and communicating with the cavity and sealing the cavity and encapsulating the solder connections between the stacked chips and the space between the top chip and the interconnection substrate with the encapsulant.