Patent ID: 7379347
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. A memory device comprising: a memory array comprising a plurality of memory cells; a plurality of word lines and a plurality of bit lines via which the plurality of memory cells are accessed; write driver circuitry responsive to a write request to write data into at least one memory cell during a programming interval by altering voltage on at least one of said bit lines connected to said at least one memory cell whilst one of said word lines connected to said at least one memory cell is selected, to cause a value indicative of the data to be stored in said at least one memory cell; at a start of the programming interval said at least one bit line being at a first voltage, and the write driver circuitry comprising first coupling circuitry responsive to the write request to couple said at least one bit line to a second voltage to cause the voltage on said at least one bit line to transition towards said second voltage, said first and second voltages representing the operating voltages of said memory cells; and said write driver circuitry further comprising additional coupling circuitry triggered at a predetermined time during said programming interval to cause said at least one bit line to transition beyond said second voltage towards a third voltage.