Patent ID: 8247816
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: a gate line including a gate electrode; a data line intersecting the gate line and including a source electrode; a drain electrode that is disposed apart from the source electrode and comprises first and second portions electrically connected to each other, wherein the first portion is a portion overlapping the gate electrode and the second portion is a portion overlapping the gate electrode, and the first and the second portions are spaced apart from each other and are extended substantially parallel to each other; a semiconductor layer connected to the source electrode and the drain electrode; a passivation layer formed on the gate line, the data line, the drain electrode, and the semiconductor layer; and a pixel electrode connected to the drain electrode, wherein the source electrode comprises first and second concave portions that are connected to each other and opened toward opposite directions against each other, the first and second portions of the drain electrode are separated by the source electrode, and the first and second concave portions enclose first and second portions of the drain electrode, respectively, and the first and second concave portions form an “S” shape.