Patent ID: 9047092
Filing Date: 2015-06-02
Classification: G06F

Abstract:
1. Apparatus for processing data in response program instructions having a program execution order, said apparatus comprising: issue queue circuitry configured to store a queue of program instructions to be issued for execution; and load store circuitry configured to perform data access operations in response to data access instructions issued from said issue queue circuitry; wherein said load store circuitry comprises a plurality of access slot circuits, each access slot circuit configured to perform an access operation corresponding to a data access instruction issued from said issue queue circuitry; said issue queue circuitry is configured to permit issue of data access instructions to said load store circuitry to be performed by respective different ones of said plurality of access slot circuits in an order different from said program execution order such that a bypassing data access instruction is issued to said load store circuitry before a bypassed data access instruction is issued to said load store circuitry, said bypassed data access instruction having a position before said bypassing data access instruction within said program execution order and said bypassing data access instruction having a potential dependency upon said bypassed data access instruction; said load store circuitry is configured to manage hazards due to potential dependency between a bypassing data access instruction and a bypassed data access instruction; and further comprising dependency tracking circuitry configured to track a freeable number of said plurality of access slot circuits including access slot circuits that are not performing access operations for bypassing data access instructions having a potential dependency upon one or more bypassed data access instructions and already free access slot circuits; wherein said issue control circuitry is coupled to said dependency tracking circuitry and is configured to prevent issue of any further bypassing data access instruction to said load store circuitry unless said freeable number is equal to or exceeds a minimum number, wherein said freeable number is a sum of any access slot circuits not performing access operations and any access slot circuits that are performing access operations for data access instruction that are not bypassing data access instructions.