Patent ID: 7542367
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a write voltage source capable of applying a write voltage; an antifuse connected to said write voltage source and having one end supplied with said write voltage; a first transistor having one end connected to the other end of said antifuse; a first transistor controller configured to provide a first gate signal to the gate of said first transistor to controllably turn on/off said first transistor; a second transistor having one end connected to the other end of said first transistor and having the other end grounded; a second transistor controller configured to provide a second gate signal to the gate of said second transistor to controllably turn on/off said second transistor; a sense node having one end connected to the other end of said first transistor; a sense amp connected to said sense node and configured to compare the potential on said sense node with a reference potential; and a potential difference controller configured to accumulate charge on said sense node to control the potential difference placed between both ends of said antifuse.