Patent ID: 7003622
Filing Date: 2006-02-21
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a regular RAM having a plurality of memory cells arranged in an array with a first row number and a second column number, such that each row is selectable from said first row number according to a regular row address signal, while each column is selectable from said second column number according to a regular column address signal; a redundant RAM having a plurality of memory cells arranged in an array with a third row number and a fourth column number, such that said plurality of memory cells is selectable instead of the defective memory cell of said regular RAM; a conversion circuit for converting said regular row address signal into a redundant column address signal for making a column selection at said redundant RAM, or converting said regular column address signal into a redundant row address signal for making a row selection at said redundant RAM, such that an address selection is changeable from a first memory cell area of said regular RAM including said defective memory cell and having a fifth row number and a sixth column number to a second memory cell area of said redundant RAM and having a seventh row number and an eighth column number different from said fifth row number and said sixth column number respectively.