Patent ID: 6535438
Filing Date: 2003-03-18
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells, each of which is assigned in advance a unique address; at least one spare memory cell for replacing defective memory cells among said plurality of memory cells; a decoder for selecting one memory cell of said plurality of memory cells according to an externally supplied address signal; at least one programming circuit for storing addresses corresponding to defective memory cells and for rendering said decoder inactive and selecting one of the at least one spare memory cell in response to the externally supplied address signal representing one of the addresses stored in the at least one programming circuit; a write/read circuit for performing a write/read operation of data signals on a memory cell selected by said decoder or one of the at least one spare memory cell selected by said programming circuit; and a first determination circuit for generating an output signal indicating availability to replace a defective memory cell with the at least one spare memory cell.