Patent ID: 9087928
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of manufacture of a semiconductor device including a memory cell, said method including steps of forming an opening in a semiconductor layer formed on a buried insulator, forming a storage node through said opening, depositing an insulator layer over said storage node to prevent crystal lattice dislocations propagating from the storage node, wherein a surface of said insulator layer is formed substantially coplanar with said buried insulator, forming a monocrystalline semiconductor layer by lateral epitaxial growth from edges of said semiconductor layer over said insulator layer, etching said monocrystalline semiconductor layer to remove any remaining crystal lattice dislocation resulting from said lateral epitaxial growth, forming an isolation structure in a volume created by said etching step, and forming a transistor structure on a remaining portion of said semiconductor layer and a planarized extension region of said semiconductor layer.