Patent ID: 7649605
Filing Date: 2010-01-19
Classification: G02F,G06F

Abstract:
1. An array substrate comprising: a substrate a plurality of gate lines extending in a first direction on the substrate; a common electrode formed on the substrate in each pixel; a first insulation layer covering the gate lines and the common electrode, the first insulation layer having a first common contact hole exposing the common electrode; a plurality of data lines formed on the first insulation layer, the data lines extending in a second direction substantially perpendicular to the first direction; a plurality of thin-film transistors electrically connected to the gate lines and the data lines; a common voltage line formed on the first insulation layer, the common voltage line extending in the second direction substantially parallel with the data lines and having a common voltage connection portion; a second insulation layer covering the data lines and the common voltage line, the second insulation layer having a second common contact hole exposing the common voltage connection portion; a pixel electrode formed on the second insulation layer, the pixel electrode electrically connected to the thin-film transistor; and a connection electrode formed on the second insulation layer, the connection electrode being electrically insulated from the pixel electrode, wherein the connection electrode is electrically connected to the common electrode through the first common contact hole, and is electrically connected to the common voltage connection portion through the second common contact hole, so that the common electrode is electrically connected to the common voltage line, wherein the connection electrode is disposed adjacent the first common contact hole and the second common contact hole.