Patent ID: 9029201
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, the method comprising: preparing a semiconductor-on-insulator wafer for processing, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate; forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region; bonding a handle wafer to a top side of said semiconductor-on-insulator wafer; after bonding said handle wafer to said semiconductor-on-insulator wafer, removing said substrate from a backside of said semiconductor-on-insulator wafer; forming an excavated insulator region in said insulator layer from a back side of said semiconductor-on-insulator layer, said excavated insulator region exposing a portion of said active device; and depositing an electrically insulating thermal dissipation layer on said excavated insulator region; wherein said excavated insulator region defines a remaining section of insulator material that is laterally coextensive with said channel region of said active device.