Patent ID: 6253350
Filing Date: 2001-06-26
Classification: G01R

Abstract:
A method for detecting faults within dual-rail complementary logic circuits, said method comprising the steps of:coupling the outputs of a dual-rail complementary logic circuit to an associated complementary fault detection circuit within an integrated circuit said associated complementary fault detection circuit comprising;a first inverter having an output connected to a gate of a first transistor and an input of a third inverter, wherein said first transistor includes a source coupled to an output of said complementary logic circuit;a second inverter having an output coupled to a gate of a second transistor and an input of a fourth inverter, wherein said second transistor includes a drain coupled to ground and a source coupled to a drain of said first transistor;said third inverter having an output connected to a gate of a third transistor, wherein said third transistor includes a source coupled to said output of said complementary logic circuit;said fourth inverter having an output coupled to a gate of a fourth transistor, wherein said fourth transistor includes a drain coupled to ground and a source coupled to a drain of said third transistor; anddetecting the presence of a non-complementary logic signal at an output of said associated complementary fault detection circuit, in response to providing an input signal at an input of said dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of said associated complementary fault detection circuit indicates the presence of a fault within said associated dual-rail complementary logic circuit.