Patent ID: 7945826
Filing Date: 2011-05-17
Classification: G06F,G11C

Abstract:
1. A test apparatus for testing a memory under test accessed in page-units and having a storage region that can be disabled in block-units that contain defects, each block including a plurality of pages, the test apparatus comprising: a bad block memory that stores a plurality of pieces of fail information in association with the blocks of the memory under test, each piece of fail information indicating whether there is a defect in the corresponding block; a data writing section that writes a test data sequence to a page under test of the memory under test; a data reading section that reads the test data sequence written to the page under test; a comparing section that compares the read data sequence to the written data sequence; a fail detecting section that detects whether there is a defect corresponding to each of a plurality of predetermined fail conditions serving as conditions for determining whether there is a defect in the page under test, and outputs the detection result as a fail signal; and an updating section that updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to fail conditions allocated in advance to the plurality of pieces of fail information associated with the block including the page under test.