Patent ID: 9136852
Filing Date: 2015-09-15
Classification: H03M

Abstract:
1. Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law, wherein the logarithmic ADDA comprises multi-sub-ADDAs, wherein at least one sub-ADDA comprises a stage-potential processing device, wherein the stage-potential processing device at stage λ comprising: a stage-potential generating module at stage λ which comprises a resistor chain for generating reference potential points and a potential stage determining circuit, wherein let Q=2 a stage-potential extracting module, wherein, for the sub-ADDA at stage λ, although it can be determined that which of the reference potential points V wherein the stage-potential V wherein the stage-potential V firstly, the correspondence between V secondly, V wherein the threshold switch comprises a lossy switch and a lossless switch, wherein the lossless switch comprises a voltage follower switch which functions as a signal switch for transmitting or blocking signals, wherein the voltage follower switch comprises two modules, a module of a voltage follower and a module of a power source switch; the power source switch is an electronic device provided on a power source loop of the follower; connection and disconnection of the power source loop of the follower are controlled by the power source switch through the control characters, so as to control connection and disconnection of a signal loop of the follower.