Patent ID: 7834442
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A chip package comprising: a substrate; a chip having a bottom surface, a top surface opposite said bottom surface and sidewalls, wherein said bottom surface is connected to said substrate; a lid above said top surface of said chip, said lid and said substrate each comprising outer edges extending laterally beyond said chip; a cured sealant connecting said outer edges of said lid to said outer edges of said substrate; and a metal thermal interface layer between and adhered to said lid and said top surface of said chip, said metal thermal interface layer comprising one of a metal foil and a metal alloy foil, having a predetermined minimum thickness and being registered to said top surface of said chip without extending vertically along said sidewalls of said chip, at least one of said chip being angled relative to said substrate such that said chip and said substrate are non-parallel, said substrate being warped such that said substrate is non-planar, and said chip being warped such that said chip is non-planar, at least one of said sealant and said metal thermal interface layer having a non-uniform thickness, and said sealant having a cure temperature that is less than a reflow temperature of said one of said metal foil and said metal alloy foil.