Patent ID: 8732425
Filing Date: 2014-05-20
Classification: G06F,Y02D

Abstract:
1. An electronic apparatus, comprising: a Double Data Rate (DDR) memory; a memory controller to generate a control signal for controlling operations of the DDR memory; and a transmission line arranged so as to transmit the control signal from the memory controller to the memory; wherein a waveform of the control signal transmitted from the memory controller to the DDR memory includes an overshoot portion and an undershoot portion due to the omission of the terminating resistor, wherein a portion of the transmission line disposed between the memory controller and the DDR memory has a predetermined length which is selected such that a waveform level of the waveform of the control signal including the overshoot portion, transmitted from the memory controller to the DDR memory, does not exceed a predefined upper voltage level, wherein no terminating voltage, or terminating resister connected thereto, is applied to the portion of the transmission line disposed between the memory controller and the DDR memory, and wherein the memory controller shortens a duty cycle of the control signal to prevent a timing of the control signal from being slower due to the omission of the terminating voltage.