Patent ID: 8099557
Filing Date: 2012-01-17
Classification: G06F

Abstract:
1. An apparatus comprising: at least a first processor and a second processor; a first cache coupled to the first processor, wherein the first cache is private to the first processor; and a second cache coupled to the first cache, wherein the second cache is shared by at least the first processor and the second processor; wherein the first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction, and wherein, responsive to a hit on a first cache block in the first cache by the address, the first cache is configured to transmit the first cache block to the second cache, and wherein the second cache is configured to retain the first cache block responsive to its transmission in response to the first instruction, and wherein the first cache is configured to invalidate the first cache block in the first cache for at least one cache state in the first cache, and wherein the first cache and the second cache are configured not to transmit the first cache block to a home memory location for the first cache block responsive to the first instruction, and wherein the first processor is further configured to execute a second instruction having a different definition than the first instruction in an instruction set architecture implemented by the first processor, and wherein the first processor is configured to form a second address responsive to one or more operands of the second instruction and wherein, responsive to a hit on a second cache block in the first cache by the second address, the first cache is configured to transmit the second cache block to the second cache, and wherein the second cache is configured to retain the second cache block responsive to its transmission in response to the second instruction, and wherein the first cache is configured to invalidate the second cache block in the first cache for at least one cache state in the first cache, and wherein the second cache is configured to transmit the second cache block to a home memory location for the second cache block in addition to retaining the second cache block responsive to the second instruction.