Patent ID: 6208176
Filing Date: 2001-03-27
Classification: G01D,G01R

Abstract:
An adaptive driver circuit for driving a semiconductor magnetoresistive device, said adaptive driver circuit comprising:a first transistor having a first base, first emitter and first collector;a second transistor having a second base, second emitter and second collector, wherein said first and second bases are mutually connected, and wherein said first transistor is matched to said second transistor;a first semiconductor magnetoresistive device having a first end and a second end, said first end thereof being connected to said first collector;a shunt connected between said first base and said first collector;a first resistor having a first end and a second end, said first end thereof being connected to said second collector, wherein said second end of said second resistance is connected to said second end of said first semiconductor magnetoresistive device;wherein a current through said first semiconductor magnetoresistive device is mirrored as an equivalent current through said first resistor;a third transistor having a third base, third emitter and third collector;a fourth transistor having a fourth base, fourth emitter and fourth collector, wherein said first, second, third and fourth emitters are mutually connected, wherein said third and fourth bases are mutually connected, and wherein said third transistor is matched to said fourth transistor;a second semiconductor magnetoresistive device having a first end and a second end, said first end thereof being connected to said third collector;a shunt connected between said third base and said third collector;a second resistor having a first end and a second end, said first end thereof being connected to said fourth collector, wherein said second end of said second resistor is connected to said second end of said second semiconductor magnetoresistive device;wherein a current through said second semiconductor magnetoresistive device is mirrored as an equivalent current through said second resistor; andwherein voltage outputs are provided, respectively, at said first end of said first and second resistors.