Patent ID: 6617896
Filing Date: 2003-09-09
Classification: H03K

Abstract:
A complementary signal generation circuit comprising:a complementary signal generator for generating an antiphase signal from an input signal, input at a signal input terminal, and outputting said antiphase signal from a first internal signal terminal, and for generating an in-phase signal from said input signal and outputting said in-phase signal from a second internal signal terminal; a flip-flop, including a first, first-conductive field-effect transistor, the source of which is connected to a first power source, a second, first-conductive field-effect transistor, the source of which is connected to said first power source, a first, second-conductive field-effect transistor, the source of which is connected to a second power source and the drain of which is connected to the drain of said first, first-conductive field-effect transistor and the gate of said second, first-conductive field-effect transistor, and a second, second-conductive field-effect transistor, the source of which is connected to said second power source and the drain of which is connected to the drain of said second, first-conductive field-effect transistor and the gate of said first, first-conductive field-effect transistor; a first RC series circuit including a first transfer gate including a second-conductive field-effect transistor, the source of which is connected to a first node, the gate of which is connected to said first power source and the drain of which is connected to a second node, and a capacitor connected to said first node; a second RC series circuit including a second transfer gate including a second-conductive field-effect transistor, the source of which is connected to a third node, the gate of which is connected to said first power source and the drain of which is connected to a fourth node, and a capacitor connected to said third node; an in-phase signal output terminal for outputting an in-phase signal to the outside; and an antiphase signal output terminal for outputting an antiphase signal to the outside, wherein said first internal signal is connected to the gate of said first, second-conductive field-effect transistor and said second node, said second internal signal terminal is connected to the gate of said second, second-conductive field-effect transistor and said fourth node, the drain of said first, second-conductive field-effect transistor is connected to said in-phase output terminal, and the drain of said second, second-conductive field-effect transistor is connected to said antiphase signal output terminal.