Patent ID: 8438505
Filing Date: 2013-05-07
Classification: G06F,Y02P

Abstract:
1. A method, comprising: providing a layout pattern having a first polygon; generating a first contour by using a computer, wherein the first contour represents the layout pattern after the layout pattern has been subjected to a first manufacturing process; generating a second polygon that approximates a geometry of the first contour; extracting an electrical parameter from the second polygon; building a pattern library using the second polygon and the electrical parameter; after building the pattern library, providing a circuit layout having a third polygon; after providing the circuit layout, generating a second contour by using the computer, wherein the second contour represents the circuit layout after the circuit layout has been subjected to second a manufacturing process; after generating the second contour, generating a fourth polygon that approximates a geometry of the second contour; and after generating the fourth polygon, determining an electrical characteristic of the circuit layout based on comparing the fourth polygon and the second polygon.