Patent ID: 7320049
Filing Date: 2008-01-15
Classification: G06F,G11C

Abstract:
1. Mode detection circuitry for initiating a memory access operation in a memory device receiving memory address signals and control signals, the detection circuitry comprising: a first mode detection circuit configured to receive the memory address signals and the control signals, the first mode detection circuit configured to generate a first mode detection signal in response to receiving the first combination of control signals and the memory address signals; a second mode detection circuit configured to receive the control signals and a clock signal, the second mode detection circuit configured to generate a second mode detection signal in response to receiving the second combination of control signals and an active clock signal; a refresh timer coupled to the first and second mode detection circuits and configured to wait a time delay after receiving a first occurrence of the first mode detection signal and to generate the first mode activation signal following expiration of the time delay only when the second mode detection signal and a second occurrence of the first mode detection signal are not received during the time delay, the refresh timer further configured to reset the time delay when the second occurrence of the first mode detection signal is received during the time delay; and an output circuit coupled to the refresh timer and the second mode detection circuit and configured to provide an activation signal to initiate a memory access operation in response to receipt of the first mode activation signal or the second mode detection signal.