Patent ID: 7343454
Filing Date: 2008-03-11
Classification: G06F

Abstract:
1. A system for ensuring triangle ordering of messages in a computer system, comprising: a plurality of caches comprising a first cache, a second cache and a third cache; a message-passing interconnect connecting the plurality of caches; a triangle ordering mechanism maintained for the first cache, the second cache and the third cache, wherein the first cache sends a first message to the second cache and the third cache, and the second cache sends a second message to the third cache, and wherein the triangle ordering mechanism ensures that the third cache receives and processes the first message before receiving and processing the second message, if the second cache receives and processes the first message before sending the second message; and a plurality of sequencing classes, the plurality of sequencing classes comprising a first sequencing class, the first sequencing class comprising the first message and the second message, wherein the triangle ordering mechanism comprises a first CT (current timestamp) maintained in the first cache, the first CT indicating a sequence number for the first message if the first message is the next message of the first sequencing class to be sent from the first cache, wherein the triangle ordering mechanism comprises a first LRTR (last received timestamp record) maintained in the second cache, the first LRTR comprising a first LRT (last received timestamp) for the first cache, the first LRT indicating the sequence number of the last received and processed message of the first sequencing class from the first cache, and wherein the triangle ordering mechanism comprises a second LRTR maintained in the third cache, the second LRTR comprising a second LRT for the first cache, the second LRT indicating the sequence number of the last received and processed message of the first sequencing class from the first cache.