Patent ID: 6011565
Filing Date: 2000-01-04
Classification: G06F

Abstract:
A non-stalled cache system, coupled to a memory module adapted to store a plurality of memory blocks, the system comprising:a cache module, coupled to the memory module, adapted to store a first memory block of the plurality of memory blocks;an address module adapted to receive a first pixel identifier of a plurality of pixel identifiers and adapted to determine whether the first pixel identifier corresponds to the first memory block stored within the cache module; anda controller module, coupled to the cache module and the address module, adapted to respond to the first pixel identifier corresponding to the first memory block by synchronizing the non-stalled transmission from the cache module of a first texel within the first memory block and the non-stalled storage of a second memory block of the plurality of memory blocks from the memory module in the cache module; said first texel corresponding to the first pixel identifier.