Patent ID: 6055182
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, and a junction-field-effect transistor of a first conductivity type for current control, wherein(A-1) one source/drain region of the first transistor is connected to a predetermined potential,(A-2) the other source/drain region of the first transistor has a common region with one source/drain region of the junction-field-effect transistor,(A-3) a gate region of the first transistor is connected to a first memory-cell-selecting line,(B-1) one source/drain region of the second transistor is connected to a second memory-cell-selecting line,(B-2) the other source/drain region of the second transistor has a common region with a channel forming region of the first transistor and with a first gate region of the junction-field-effect transistor,(B-3) a gate region of the second transistor is connected to the first memory-cell-selecting line,(C-1) a second gate region of the junction-field-effect transistor faces the first gate region thereof through a channel region thereof, the channel region thereof being an extended region of the other source/drain region of the first transistor, and(C-2) the other source/drain region of the junction-field-effect transistor is positioned in the extended region of the other source/drain region of the first transistor via the channel region.