Patent ID: 8994635
Filing Date: 2015-03-31
Classification: G09G,H01L

Abstract:
1. An image display device comprising: a substrate including pixel circuits arranged in a matrix of pixel circuit rows and pixel circuit columns for performing display control for pixels, each of the pixel circuits including a first thin film transistor, a storage capacitor, a second thin film transistor and an organic light emitting diode element; and a plurality of scanning signal lines wired in one of the pixel circuit rows, which one pixel circuit row includes a plurality of said pixel circuits, wherein: the storage capacitor of each of the pixel circuits has one end connected to a data signal line via the first thin film transistor of the pixel circuit and another end connected to a gate electrode of the second thin film transistor of the pixel circuit, a source electrode of the second thin film transistor is connected to a power supply line, one end of the organic light emitting diode element is connected to the second thin film transistor and another end of the organic light emitting diode is connected to a common ground electrode, the first thin film transistor of a first one of the pixel circuits in the one pixel circuit row is connected to one of the plurality of scanning signal lines wired in the one pixel circuit row while the first thin film transistor of a second one of the pixel circuits in the one pixel circuit row is connected to a different one of the plurality of scanning signal lines wired in the one pixel circuit row, and two reset signal lines are arranged in said one of the pixel circuit rows, wherein the first one of the pixel circuits in the one pixel circuit row is connected to one of the two reset signal lines, and the second one of the pixel circuits in the one pixel circuit row is connected to the other one of the two reset signal lines, wherein the plurality of scanning signal lines and the two reset signal lines are configured and arranged relative to first and second one of the pixel circuits to reduce transmission delay of signals on the scanning signals lines and the reset signal lines to the first and second one of the pixel circuits.