Patent ID: 6841465
Filing Date: 2005-01-11
Classification: G03F,H01L,Y10S

Abstract:
1. A method of forming a dual damascene pattern in a semiconductor device, comprising the steps of: providing a semiconductor substrate in which an interlayer insulating film is formed and a trench of a given pattern is formed in the interlayer insulating film; forming a photoresist pattern in which a via hole region is defined, in the trench; forming a high polymer solution coating film containing a crosslinkable agent or a radical generator, on the entire structure; reacting to the crosslinkable agent or the radical generator with polymer of the photoresist pattern by means of a baking process so that an etching tolerance property is increased, thereby forming a hardened photoresist pattern; removing the high polymer solution coating film; and forming a via hole in the interlayer insulating film by an etching process, wherein the photoresist pattern is thinly formed relatively as much as the etching tolerance property is increased by the hardened photoresist pattern to form said dual damascene pattern.