Patent ID: 6583056
Filing Date: 2003-06-24
Classification: H01L

Abstract:
A method for fabricating a storage electrode of a semiconductor memory device, the method comprising:i) preparing a wafer having a first insulating layer formed with a buried contact plug; ii) forming an etching stop layer on the first insulating layer formed with the buried contact plug; iii) forming a second insulating layer on the etching stop layer; iv) implanting an impurity into the second insulating layer; v) forming a third insulating layer on the second insulating layer; vi) forming a photoresist pattern for defining a capacitor forming area on the third insulating layer; vii) forming an opening by anisotropically and sequentially etching the third insulating layer, the second insulating layer and the etching stop layer by using the photoresist pattern as an etching mask until an upper surface of the buried contact plug is exposed; viii) removing the photoresist pattern; ix) cleaning a resulting structure such that the second insulating layer exposed through the opening is isotropically etched; x) depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness; xi) removing the polysilicon deposited on an upper surface of the third insulating layer; and xii) removing remaining third and second insulating layers.