Patent ID: 7181704
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. A method of designing an integrated circuit, comprising the steps of: interpreting high-level flow data from a command line, constraint files, and environment variables to create a data model; wherein the data model includes a plurality of partial netlists of a design; augmenting the data model with a plurality of directives allowing for flow independent tasks; wherein each of the plurality of directives controls selection of one or more tasks, and at least one of the directives is an guiding implementation directive; associating one or more of the plurality of directives with one or more of the plurality partial netlists, wherein each partial netlist forms a container; creating a list of tasks based upon the plurality of directives associated with the partial netlist; wherein each partial netlist that has one or more associated directives has a respective list of one or more tasks, and the list of tasks created for the guiding implementation directive includes a first task that determines whether signal names match between a current version of the partial netlist and a previous version of the partial netlist and a second task that assigns for a matching signal, an implementation of the matching signal from the previous version of the partial netlist to an implementation of the current version of the partial netlist; and associating a set of tasks that operate on logic represented by the partial netlist.