Patent ID: 6628490
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A circuit arrangement for protecting the input of an integrated circuit particularly suitable for analog signals, more specifically a CMOS circuit, against overvoltages, said circuit arrangement (100) comprising:at least two input terminals (10; 20) and at least one protection stage (S) in which each input terminal (10; 20) is connected to a power supply voltage (US) by a respective protection diode (12; 22), particularly a semiconductor diode, and to a reference potential (UR) by a respective protection diode (16; 26), particularly a semiconductor diode, characterized in that at least a further diode (14, 18; 24; 28) is arranged in series with each protection diode (12, 16; 22, 26), and the protection stage (S) precedes at least a filter stage (F), particularly at least a high-frequency filter stage.