Patent ID: 6850108
Filing Date: 2005-02-01
Classification: H03K

Abstract:
1. An input buffer, comprising: a single pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and having a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting at an output terminal a signal applied to the input pad; a buffer having an input terminal coupled directly and exclusively to the output terminal of the transmission transistor, the buffer generating an input signal by buffering the signal transmitted by the transmission transistor; and a controller generating the voltage of the signal applied to the input pad as the control voltage and the floating well voltage when a high voltage is applied to the input pad, and generating the ground voltage as the control voltage and the power supply voltage as the floating well voltage in the case where a voltage less than the high voltage is applied to the input pad.