Patent ID: 8151241
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. An impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port, comprising: calculating a first set of impedances at a predetermined frequency for the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, wherein the first set of impedances comprises a self-impedance of the observation I/O port and mutual impedances of the observation I/O port with respect to other I/O ports; calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source, wherein the second set of impedances comprises a self-impedance of the observation I/O port and mutual impedances of the observation I/O port with respect to other I/O ports; comparing the first set of impedances to the second set of impedances; and adjusting the impedance of the power network or the impedance of the carrier according to the comparison result.