Patent ID: 6016281
Filing Date: 2000-01-18
Classification: G11C,H01L

Abstract:
A memory system comprising:a memory array of cells arranged in M rows and N columns, each row having a row conductor and each column having a column conductor, with a cell being formed at the intersection of a row conductor and a column conductor, and each cell including a transistor and a storage capacitor, each transistor having first and second electrodes defining the ends of a main conduction path and a gate electrode, with each transistor having its gate electrode connected to its corresponding row conductor, one end of its conduction path connected to its corresponding column conductor and the other end of its conduction path connected to its storage capacitor; andselect circuit, said select circuit selectively applying a turn-off voltage to selected row conductors for turning off conduction in the main conduction paths of the transistors whose gate electrodes are connected to the selected row conductors, and selectively applying an increased turn-off voltage to selected row conductors.