Patent ID: 7583553
Filing Date: 2009-09-01
Classification: G11C

Abstract:
1. A semiconductor memory that needs refresh operation, the memory comprising: a temperature detection section for detecting temperature of the semiconductor memory; a cycle change control section for sending a cycle change signal for changing a refresh cycle at the time of the temperature of the semiconductor memory becoming a predetermined cycle change temperature; a refresh timing signal generation section for generating a refresh timing signal and for changing a cycle of the refresh timing signal in response to the cycle change signal; a signal generation circuit for generating a signal for generating the refresh timing signal; a first setting circuit for designating a level of the signal generated in a case of the temperature of the semiconductor memory being lower than or equal to the cycle change temperature; a second setting circuit for designating a level of the signal generated in a case of the temperature of the semiconductor memory being higher than the cycle change temperature; wherein each of the first setting circuit and the second setting circuit includes a plurality of fuses and designates the level of the signal according to a position of a fuse cut out of the plurality of fuses; and if the signal has temperature dependence by which the level of the signal increases with a rise in the temperature of the semiconductor memory, fuses of same positions out of the plurality of fuses in the first setting circuit and the second setting circuit are cut.