Patent ID: 6167048
Filing Date: 2000-12-26
Classification: H04J,H04L

Abstract:
A method of clock recovery from a fast packet switched asynchronous network at a near end wherein a time stamp is transmitted at a far end over a network that has variable delay, comprising the steps of:maintaining an input counter at a sending device at said far end, said input counter having a value dependent on an input clock;periodically transmitting at said far end a sample value x.sub.i of said input counter over said network to a receiving device at said near end;receiving at said near end said value x.sub.i of said input counter;maintaining a local counter at said receiving device, said local counter having a sample value y.sub.i dependent on a local clock;comparing the received sample value x.sub.i with the sample value y.sub.i of said local counter to derive a difference representing an error sample e.sub.i ;deriving the minimum value Emin.sub.j of a block of said error samples e.sub.j ; andadjusting the local clock frequency f.sub.j such that the average of Emin.sub.j remains close to zero.