Patent ID: 8788887
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a memory comprising a plurality of memory locations identified by corresponding memory addresses; processing circuitry configured to perform processing operations in response to instructions; and trace circuitry configured to generate a stream of trace data elements indicative of said processing operations performed by said processing circuitry and to output said stream of trace data elements; wherein: said trace circuitry comprises a plurality of reference address registers configured to store a plurality of reference addresses; and said trace circuitry is responsive to said processing circuitry processing an instruction for performing a processing operation associated with an associated memory address to select one of said plurality of reference address registers as a selected reference address register and to generate and output a trace data element indicating: (i) first information indicative of which of said plurality of reference address registers is said selected reference address register; and (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register; wherein said trace circuitry is configured, after generating said trace data element, to perform a reference address updating operation for selectively updating the reference address of at least one of said plurality of reference address registers in dependence on said associated memory address, and wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register of said plurality of reference address registers.