Patent ID: 7019572
Filing Date: 2006-03-28
Classification: H03L

Abstract:
1. A system implemented in a phase-locked loop (PLL) circuit, comprising; a charge pump configured to receive up and down signals and to maintain a voltage at an output of the charge pump based on the up and down signals; control circuitry coupled to the charge pump and configured to provide the up and down signals to the charge pump in either a first mode or a second mode; wherein in the first mode, the control circuitry is configured to pass through signals received from a phase frequency detector as the up and down signals; wherein in the second mode, the control circuitry is configured to override at least one of the signals received from the phase frequency detector to drive a voltage at an output of the charge pump to a selectable test voltage; wherein the control circuitry is configured to receive one or more control signals and to enter one of the first and second modes based upon the control signals; wherein the control signals include a test signal, an initialization signal, an up control signal and a down control signal; wherein the control circuitry is configured to alternately enter the first and second modes based on the test and initialization signals; and wherein the test voltage is selectable from a plurality of possible voltages based on the up control signal and the down control signal.