Patent ID: 6043533
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A semiconductor substrate having lightly doped drain regions formed by a method comprising the steps of:providing a semiconductor substrate having a p-well region and an n-well region;forming a patterned gate oxide and gate electrode on each of the p-well region and the n-well region;masking one of either the p-well region or the n-well region with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed;implanting ions to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region such that said implantation in the n-well is on the order of 0.1 .mu.m or less; andimplanting ions to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step.