Patent ID: 6529549
Filing Date: 2003-03-04
Classification: H04L

Abstract:
An equalizer based symbol timing loop for use in a receiver, comprising:a linear equalizer for removing inter-symbol interference; a phase detector coupled to the linear equalizer for identifying a center tap of the linear equalizer, capturing the center tap at a the beginning and end of a measurement period, multiplying the captured value of the center tap at the beginning of the measurement period by the conjugate of the captured value of the center tap at the end of the measurement period, and calculating the arc tangent of the multiplication result; a loop filter coupled to the phase detector for multiplying the arc tangent result by a scalar and adding the scalar-multiplied result to a frequency difference estimate; a coefficient generator coupled to the loop filter for determining an interpolation phase for a given sample stream based on the frequency difference estimate and generating interpolator coefficients based on the interpolation phase; and a timing interpolator filter coupled to the coefficient generator for receiving the interpolator coefficients and modifying the sample stream to match a transmitter's symbol rate.