Patent ID: 6740578
Filing Date: 2004-05-25
Classification: G01R,H01L,H05K

Abstract:
A method of fabricating discrete interconnections for receiving portions of substantially spherical interconnection elements of a semiconductor device, comprising:providing a semiconductor substrate; forming a dielectric layer over a portion of the semiconductor substrate; forming a lower conductive trace over a portion of the dielectric layer; forming a lower passivation layer over and in contact with the lower conductive trace and at least a portion of the dielectric layer; etching a column via in the lower passivation layer to expose a portion of the lower conductive trace; forming a conductive column in the column via; forming an upper conductive trace over a portion of the lower passivation layer; forming an upper passivation layer over the conductive column and over and in contact with the upper conductive trace and at least a portion of the lower passivation layer; etching a first via in the upper passivation layer to expose the conductive column; etching a second via in the upper passivation layer to expose a portion of the upper conductive trace; forming a metal layer over the upper passivation layer and into the first via and into the second via; removing the metal layer surrounding the first via to define a first discrete interconnection contacting the lower conductive trace through the conductive column; and removing the metal layer surrounding the second via to define a second discrete interconnection contacting the upper conductive trace.