Patent ID: 6477170
Filing Date: 2002-11-05
Classification: H04L

Abstract:
An interface for transferring information between a first system operating within a first clock regime and a second system operating within a second clock regime different from the first clock regime, the interface comprising:a first pipeline section connected to the first system; a second pipeline section connected to the second system; a first system state machine operating in accordance with the first clock regime to transfer information between the first system and the second pipeline section through the first pipeline section; a second system state machine operating in accordance with the second clock regime to transfer information between the second system and the first pipeline section through the second pipeline section; wherein the first system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the second system prior to continuing operation, and the second system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the first system prior to continuing operation.