Patent ID: 6750496
Filing Date: 2004-06-15
Classification: G03F,H01L,Y10S

Abstract:
A semiconductor integrated circuit device comprising:a plurality of first regions formed over a semiconductor substrate; a first insulative film deposited on said semiconductor substrate; a first hole pattern formed over said first insulative film and electrically connected to each of said plurality of first regions; a wiring provided on said first insulative film to pass through an adjacent gap between the first hole patterns and intersect relative to said plurality of first regions; a second insulative film for covering said wiring; and a second hole pattern provided in said second insulative film to be connected to said first hole pattern and not to be connected to said wiring, wherein said first region is an active region in which a memory cell selection field effect transistor of a DRAM is formed, and said wiring is a data line, and said first and second hole patterns are constituent members for electrically connecting an information storage capacitance element and said memory cell selection field effect transistor, wherein said data line passes through a center of said active region in such a state that the data line is aslant disposed with respect to said active region, and said data line is electrically connected to a semiconductor region formed in a center of said active region, said semiconductor region being for a source/drain of said memory cell selection field effect transistor, and wherein said second hole pattern is disposed such that even if a position thereof is deviated, a connection between said first and second hole patterns is kept and an insulative state between said second hole pattern and said wiring is kept, and a pair of second patterns disposed to put said wiring therebetween are disposed to be displaced separately from said wiring put between the pair of second hole patterns.