Patent ID: 9123412
Filing Date: 2015-09-01
Classification: G11C

Abstract:
1. A resistance change memory comprising: a first memory cell including a resistance change element; a first inverter including a first input terminal, a first output terminal, and first and second voltage terminals; a second inverter having a second input terminal, a second output terminal, and third and fourth voltage terminals, the second input terminal being connected to the first output terminal, the second output terminal being connected to the first input terminal; a first MOS transistor being connected to the first output terminal, the first MOS transistor having a gate supplied with a first signal; a second MOS transistor being connected to the second output terminal, the second MOS transistor having a gate supplied with the first signal; a third MOS transistor being connected to the first voltage terminal; a fourth MOS transistor being connected to the third voltage terminal; a fifth MOS transistor being connected between the first voltage terminal and the first memory cell, the fifth MOS transistor having a gate supplied with a second signal; a sixth MOS transistor being connected to the third voltage terminal, the sixth MOS transistor having a gate supplied with the second signal; and a controller that outputs the first and second signals, the controller turning on the first and second MOS transistors by using the first signal, after turning off the fifth and sixth MOS transistors by using the second signal.