Patent ID: 8346883
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A method of effecting hardware acceleration of broadcast operations in a parallel computer, the parallel computer comprising a plurality of compute nodes organized for collective operations via a data communications network, each compute node having a receive buffer, the method comprising: establishing a network topology for the data communications network; selecting, in dependence upon the network topology, a schedule for a broadcast operation; depositing, by a root node of the topology, broadcast data in a target node's receive buffer, including performing a DMA operation with a well-known memory location for the target node's receive buffer; depositing, by the root node in a memory region designated for storing broadcast data length for the target node, a length of the broadcast data, including performing a DMA operation with a well-known memory location of the broadcast data length memory region; and triggering, by the root node, the target node to perform a next DMA operation, including depositing, in a memory region designated for receiving injection instructions for the target node, an instruction to inject the broadcast data into the receive buffer of a subsequent target node.