Patent ID: 7398361
Filing Date: 2008-07-08
Classification: G06F

Abstract:
1. An interface unit configured to interface a processor core to an interconnect, the interface unit comprising: an address buffer comprising a plurality of address buffer entries, the address buffer is configured to store addresses of processor core requests generated by the processor core and addresses of snoop requests received from the interconnect; a control unit coupled to the address buffer, the control unit configured to maintain a plurality of queues, with at least a first queue of the plurality of queues dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests; the control unit is further configured to respond to a first snoop request received by the interface unit from the interconnect, to allocate a first address buffer entry of the plurality of address buffer entries to store the first snoop request, and the control unit stores a first pointer to the first address buffer entry in the first queue; the control unit is responsive to a first processor core request received by the interface unit from the processor core and to allocate a second address buffer entry of the plurality of address buffer entries to store the first processor core request, and the control unit is configured to store a second pointer to the second address buffer entry in the second queue; and, the control unit reads the first pointer from the first queue to use as an index to the address buffer to read or write the first address buffer entry, and the control unit reads the second pointer from the second queue to use as an index to the address buffer to read or write the second address buffer entry.