Patent ID: 6185664
Filing Date: 2001-02-06
Classification: G06F,G11C

Abstract:
A method for providing more than one clock cycle of memory latency for accesses to a synchronously accessed memory, comprising:delaying a clock signal in a memory controller by passing the clock signal through a delay element within the memory controller to produce a delayed clock signal;wherein the clock signal is coupled to a clocked interface of the synchronously accessed memory;receiving data to be written into the synchronously accessed memory at an input register in the memory controller;latching the data at the input register using the delayed clock signal;applying a write address from the memory controller to the synchronously accessed memory; andapplying a control signal from the memory controller to the synchronously accessed memory to command the synchronously accessed memory to perform a write operation;wherein the delayed clock signal is delayed relative to the clock signal at the input register so that the data is latched by a preceding cycle of the delayed clock signal into the input register and is recorded by a cycle of the clock signal at the write address in the synchronously accessed memory.