Patent ID: 8400828
Filing Date: 2013-03-19
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix and a peripheral circuit, a first active region and a second active region defined by isolation regions in a memory cell array region, extending in a first direction, a first gate insulating film and a second gate insulating film on the first active region, a third gate insulating film and a fourth gate insulating film on the second active region, a first floating gate above the first gate insulating film, a third floating gate above the third gate insulating film, a first gate electrode above the first floating gate, a second gate electrode above the second gate insulating film, a third gate electrode above the third floating gate, a fourth gate electrode above the fourth gate insulating film, a first sidewall spacer on a sidewall of the first gate electrode, a second sidewall spacer on a sidewall of the second gate electrode, a third sidewall spacer on a sidewall of the third gate electrode, a fourth sidewall spacer on a sidewall of the fourth gate electrode, a first source region on one side of the first gate electrode and a first drain region on the other side of the first gate electrode in the first active region, a second source region on one side of the second gate electrode and a second drain region on the other side of the second gate electrode in the first active region, a third source region on one side of the third gate electrode and a third drain region on the other side of the third gate electrode in the second active region, a fourth source region on one side of the fourth gate electrode and a fourth drain region on the other side of the fourth gate electrode in the second active region, a first memory cell transistor including the first gate insulating film, the first floating gate, the first gate electrode, the first sidewall spacer, the first source region and the first drain region, a first selecting transistor including the second gate insulating film, the second gate electrode, the second sidewall spacer, the second source region and the second drain region, a second memory cell transistor including the third gate insulating film, the third floating gate, the third gate electrode, the third sidewall spacer, the third source region and the third drain region, a second selecting transistor including the fourth gate insulating film, the fourth gate electrode, the fourth sidewall spacer, the fourth source region and the fourth drain region, an interlayer insulating film having a planarized surface above the first gate electrode, the second gate electrode, the third gate electrode, the fourth gate electrode, the first sidewall spacer and the second sidewall spacer, the third sidewall spacer and the fourth sidewall spacer, a first plug in the interlayer insulating film above the first drain region, the second plug in the interlayer insulating film above the second source region, a third plug in the interlayer insulating film above the third drain region and a fourth plug in the interlayer insulating film above the fourth source region, a bit line commonly connecting to the first plug and the third plug, extending in a second direction perpendicular to the first direction, a source line commonly connecting to the second plug and the fourth plug, extending in the second direction, a third active region, a fourth active region, a fifth active region and sixth active region defined by isolation regions in a peripheral circuit region, a fifth gate insulating film on the third active region, a sixth gate insulating film on the fourth active region, a seventh gate insulating film on the fifth active region and a eighth gate insulating film on the sixth active region, a fifth gate electrode above the fifth gate insulating film, a sixth gate electrode above the sixth gate insulating film, a seventh gate electrode above the seventh gate insulating film, an eighth gate electrode above the eighth gate insulating film, a fifth sidewall spacer on a sidewall of the fifth gate electrode, a sixth sidewall spacer on a sidewall of the sixth gate electrode, a seventh sidewall spacer on a sidewall of the seventh gate electrode, an eighth sidewall spacer on a sidewall of the eighth gate electrode, a fifth source region on one side of the fifth gate electrode and a fifth drain region on the other side of the fifth gate electrode, a sixth source region on one side of the sixth gate electrode and a sixth drain region on the other side of the sixth gate electrode, a seventh source region on one side of the seventh gate electrode and a seventh drain region on the other side of the seventh gate electrode, an eighth source region on one side of the eighth gate electrode and an eighth drain region on the other side of the eighth gate electrode, a fifth transistor including the fifth gate insulating film, the fifth gate electrode, the fifth sidewall spacer, the fifth source region and the fifth drain region, a sixth transistor including the sixth gate insulating film, the sixth gate electrode, the sixth sidewall spacer, the sixth source region and the sixth drain region, a seventh transistor including the seventh gate insulating film, the seventh gate electrode, the seventh sidewall spacer, the seventh source region and the seventh drain region, an eighth transistor including the eighth gate insulating film, the eighth gate electrode, the eighth sidewall spacer, the eighth source region and the seventh drain region, a column decoder including the fifth transistor, connecting to the bit line, a first row decoder including the sixth transistor, connecting to the first gate electrode and the third gate electrode, a second row decoder including the seventh transistor, connecting to the second gate electrode and the fourth gate electrode, a third row decoder including the eighth transistor, connecting to the source line, wherein the first gate electrode and the third gate electrode are formed with a first conductor of one extending in the second direction, the second gate electrode and the fourth gate electrode are formed with a second conductor of one extending in the second direction, the first source region and the second drain region are the same region, the third source region and the fourth drain region are the same region, the first memory cell transistor is connected in series to the first selecting transistor, the second memory cell transistor is connected in series to the second selecting transistor, a thickness of the fifth gate insulating film is thinner than either a thickness of the sixth gate insulating film or a thickness of the eighth gate insulating film, a thickness of the seventh gate insulating film is thinner than either a thickness of the sixth gate insulating film or a thickness of the eighth gate insulating film.