Patent ID: 6226671
Filing Date: 2001-05-01
Classification: G06F

Abstract:
A computer system comprising:a plurality of processing nodes;a hierarchical bus system comprising a plurality of address partitions; anda shared memory system comprising a plurality of physical memory locations wherein said plurality of physical memory location are either located in a node of said plurality of processing nodes, distributed in equal proportions among nodes of said plurality of processing nodes, or distributed in unequal proportions among at least two nodes of said plurality of processing nodes, wherein:said physical memory locations of said shared memory system are mapped to said plurality of address partitions of said hierarchy bus system, whereby each of said plurality of physical memory locations of said shared memory system are addressed by a plurality of address aliases, and wherein properties of said address partitions dictate whether a transaction in a transaction originating node of said plurality of nodes is visible to the remaining nodes of said plurality of nodes.