Patent ID: 6721813
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A computer system, comprising:a processing subsystem including a plurality of processing nodes interconnected via coherent communication links, wherein the plurality of processing nodes includes a first processing node and a second processing node, and wherein the first processing node comprises a host bridge; a memory coupled to the second processing node; an input/output (I/O) node coupled to the first processing node via a non-coherent communication link, wherein the I/O node is configured to dispatch a first write transaction to store data within the memory, wherein the first write transaction is a posted write transaction, wherein the first write transaction is conveyed within a posted command virtual channel of the I/O subsystem, and wherein the posted command virtual channel is separate from a non-posted command virtual channel of the I/O subsystem; wherein the host bridge is configured to dispatch a second write transaction within the processing subsystem in response to the first write transaction, and wherein the second write transaction is directed to the second processing node; wherein the second processing node is configured to respond to the second write transaction by dispatching a target done response directed to the host bridge.