Patent ID: 7002397
Filing Date: 2006-02-21
Classification: H01L,H03K

Abstract:
1. A semiconductor integrated circuit including a plurality of operation modes, comprising: a plurality of circuit blocks, each comprising a plurality of P channel MOS transistors, and a plurality of N channel MOS transistors, wherein said plurality of circuit blocks include a first circuit block and a second circuit block, wherein said operation modes include a first mode and a second mode, wherein said N channel MOS transistors included in said first circuit block are provided a bias voltage higher than a ground voltage in said first mode, and are provided a bias voltage lower than said ground voltage in said second mode, wherein said P channel MOS transistors included in said first circuit block are provided a bias voltage lower than a power supply voltage in said first mode, and are provided a bias voltage higher than said power supply voltage in said second mode, wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage lower than said ground voltage in said second mode, wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage higher than said power supply voltage in said second mode, wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage equal to said ground voltage in said first mode, and wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage equal to said power supply voltage in said first mode.