Patent ID: 8492822
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for manufacturing an LC circuit, comprising: forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer; forming a dielectric layer pattern storing electric charges on the first conductive layer pattern; forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern; forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug; and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched as a metal interconnection type layer and functions as an inductor, the third conductive layer pattern being etched in a planar spiral pattern so that the third conductive layer pattern covers the second conductive layer pattern in a vertical direction.