Patent ID: 6380021
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing a semiconductor substrate wafer wherein there is at least one NMOS active area and at least one PMOS active area; providing a NMOS gate electrode in said NMOS area and a PMOS gate electrode in said PMOS area; implanting p-type pocket implants in said NMOS area; implanting n-type source/drain extensions in said NMOS area; implanting n-type pocket implants in said PMOS area; thereafter annealing said wafer whereby said n-type source/drain extensions are driven in; thereafter implanting p-type source/drain extensions in said PMOS area wherein said p-type source/drain implants are not subjected to an annealing step; forming spacers on sidewalls of said NMOS gate electrode and said PMOS gate electrode; and forming source/drain regions in said NMOS and said PMOS areas wherein said source/drain regions are self-aligned to said spacers to complete formation of said integrated circuit device.