Patent ID: 8000951
Filing Date: 2011-08-16
Classification: G06F

Abstract:
1. A timing analysis method comprising: storing simulation information for each block when performing circuit analysis by partitioning a circuit into blocks; identifying a path that needs analysis and obtaining a SPICE deck generation target node; performing a static timing analysis; determining whether said obtained SPICE deck generation target node is located on a path that is analyzed by said static timing analysis; generating a SPICE deck by interconnecting said blocks, for said path that needs analysis, by using a result of said static timing analysis and using simulation conditions for said each block, when said obtained SPICE deck generation target node is located on said analyzed path; performing a SPICE simulation based on said generated SPICE deck; causing a result of the simulation performed using said generated SPICE deck to be reflected in said static timing analysis, by substituting the result of said static timing analysis by the result of said SPICE simulation; and performing said static timing analysis once again, wherein in identifying said path, if a circuit that matches a template is found, back-tracing is performed starting from a designated terminal of the circuit that matches said template, and a node passed through during said back-tracing is taken as said SPICE deck generation target node, and said back-tracing is performed in a direction going from a drain terminal of a transistor to a source terminal or a gate terminal thereof.