Patent ID: 7046573
Filing Date: 2006-05-16
Classification: G11C

Abstract:
1. A semiconductor integrated circuit, comprising: a central processing unit; a memory including instructions and data; a clock generator for generating a plurality of clock signals; and a bus coupled to said central processing unit and said memory, wherein said semiconductor integrated circuit has a plurality of operation states including an active state and a standby state, wherein said semiconductor integrated circuit is instructed as to a transition of the operation state from said active state to said standby state, when said central processing unit executes a predetermined instruction, wherein said central processing unit can access said memory and said clock generator provides a clock signal to said central processing unit, in said active state, wherein said central processing unit stops an operation and said clock generator stops generating said clock signals, in said standby state, wherein said memory has voltage generation circuits for bit lines and source lines with which memory cells are connected, and wherein said voltage generation circuits make the potential of said bit lines and the potential of said source lines equal to each other in response to an instruction to transition from said active state to said standby state, and produce a potential difference between said bit lines and said source lines in response to an instruction to transition from said standby state to said active state.