Patent ID: 7248534
Filing Date: 2007-07-24
Classification: G11C

Abstract:
1. A semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks, in which data is read or written by the local block, and in which each local block has a write error protection circuit for preventing a write error from occurring in the case of data being written into a memory cell, the write error protection circuit including: a first transistor to an input terminal of which an auxiliary common bit line for reading data from or writing data into a local block included in each column is connected, to a first output terminal of which a main connection line of a memory cell included in the local block is connected, and to a second output terminal of which power supply is connected; and a second transistor to an input terminal of which a main common bit line for reading data from or writing data into a local block included in each column is connected, to a first output terminal of which an auxiliary connection line of a memory cell included in the local block is connected, and to a second output terminal of which the power supply is connected.