Patent ID: 8510700
Filing Date: 2013-08-13
Classification: G06F,H01L,H03K

Abstract:
1. A computer-implemented method of camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells that together perform one or more logical functions, the method comprising the steps of: identifying, using the computer, at least one gap between the plurality of interconnected functional logic cells having no functional logic therein; placing, using the computer, one filler cell or combination of filler cells into the identified gap, wherein at least one of the filler cells has a physical design layout similar to but different from at least one of the functional logical cells; and defining, using the computer, a routing of the placed one filler cell or combination of filler cells; wherein the filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the routed one or more filler cells together perform at least one camouflage logical function reproducing at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.