Patent ID: 6700149
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A circuit configuration for forming an MOS capacitor with a low voltage dependence, comprising:interconnected terminals; a first MOS transistor having a drain terminal and a source terminal; and a second MOS transistor having a drain terminal and a source terminal; said drain terminal of said first MOS transistor being connected to said source terminal of said first MOS transistor; said drain terminal of said second MOS transistor being connected to said source terminal of said second MOS transistor; said first MOS transistor being a short-channel transistor having a channel length not greater that 1 &mgr;m; said second MOS transistor being a short-channel transistor having a channel length not greater that 1 &mgr;m; said first MOS transistor and said second MOS transistor being operated in depletion; said first MOS transistor having a given channel type, a bulk terminal, and a gate; said second MOS transistor having the given channel type, a bulk terminal, and a gate; said first MOS transistor being connected to said second MOS transistor in a manner selected from the group consisting of a first manner and a second manner; in said first manner, said bulk terminal of said first MOS transistor and said bulk terminal of said second MOS transistor defining said interconnected terminals and being connected together; in said second manner, said gate of said first MOS transistor and said gate of said second MOS transistor defining said interconnected terminals and being connected together; said first MOS transistor and said second MOS transistor being reverse-connected in series; said first MOS transistor having a depletion region being widened by a first potential difference; said second MOS transistor having a depletion region being widened by a second potential difference; the first potential difference being connected between said interconnected terminals and said drain terminal of said first MOS transistor; and the second potential difference being connected between said interconnected terminals and said drain terminal of said second MOS transistor.