Patent ID: 8107365
Filing Date: 2012-01-31
Classification: H04L,Y02D

Abstract:
1. An apparatus comprising: a buffer, included in a first physical layer device (PHY), with the buffer adapted to receive data from a non-compliant host media access control device (MAC when the first PHY is in an Energy Efficient Ethernet low power idle (LPI) state, where the non-compliant host MAC is not compliant with Energy Efficient Ethernet and where the non-compliant host MAC does not respond to the assertion of a flow-control signal until a fixed latency response interval has expired; and a control circuit, included in the first PHY, adapted to control the first PHY to respond to data sent from the non-compliant host MAC to the PHY when the first PHY is in the LPI state by asserting the flow-control signal, with the flow-control signal signaling the non-compliant host MAC to pause data transmission for a first pause period, with the control circuit further adapted to write data transmitted from the non-compliant host MAC into the buffer while the non-compliant host MAC transmits data during the latency response period and to transition the first PHY from the LPI state to an active state during a wake up period, and with the control circuit further adapted to control the first PHY to transmit data from the buffer to a link partner subsequent to completion of the wake up period and before the completion of the first pause period and to transmit data received at the first PHY from the non-compliant host MAC to the link partner after completion of the pause period.