Patent ID: 9040351
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method of manufacturing a stack package, the method comprising: forming a lower package comprising a lower package substrate, a first lower land disposed on a top surface of the lower package substrate, a lower inter-package connector disposed on the first lower land, and a lower semiconductor chip disposed on the top surface of the lower package substrate; forming an upper package comprising an upper package substrate, a first upper land disposed on a bottom surface of the upper package substrate, an upper inter-package connector disposed on the first upper land, and an upper semiconductor chip disposed on a top surface of the upper package substrate; providing an intermediate inter-package connector disposed on at least one of the lower inter-package connector and the upper inter-package connector; providing a fastening element between the lower package and the upper package; performing a first annealing to cure the fastening element; and performing a second annealing to integrate the lower inter-package connector, the intermediate inter-package connector, and the upper inter-package connector, wherein at least one of the first annealing and the second annealing removes at least one of an alcohol or a solvent from the intermediate inter-package connector to decrease a volume thereof.