Patent ID: 7813141
Filing Date: 2010-10-12
Classification: H05K,Y10T

Abstract:
1. A capacitive/resistive device, comprising: a first metallic foil; a second metallic foil; a dielectric layer disposed over the first metallic foil; a resistive layer disposed on the second metallic foil and adjacent to the dielectric layer, said resistive layer being disposed between said second metallic foil and said dielectric layer; a first capacitor electrode formed from the first metallic foil; a second capacitor electrode and a conductive trace formed from the second metallic foil, the conductive trace being spaced from the second capacitor electrode, wherein the first capacitor electrode, the second capacitor electrode, and the dielectric layer form a capacitor with the dielectric layer disposed between the first and second capacitor electrodes; a resistor element formed from the resistive layer, wherein the resistor element extends between and is in contact with the conductive trace and the second capacitor electrode so as to form a resistor element in series with the capacitor; and wherein the first capacitor electrode and the second capacitor electrode are formed by selective imaging and etching the first and second metallic foils, respectively, to form a specific value of capacitance, and wherein the resistor element is formed by selectively imaging and etching the resistance layer independent of the capacitor electrodes to form a specific value of resistance, the specific values of capacitance and resistance selected so as to achieve a specific circuit impedance; and wherein the capacitor and the resistor are embedded within at least two printed wiring board dielectric laminate layers.