Patent ID: 6483168
Filing Date: 2002-11-19
Classification: H01L,H03F

Abstract:
An integrated circuit configured to assert a first potential at a first node and a second potential at a second node in response to an input signal, wherein each of the first potential and the second potential changes in response to changes in the input signal, said circuit comprising:a substrate of semiconductor material of a first polarity; a vertical bipolar transistor having a base, an emitter, and a collector, wherein the collector is a portion of the substrate, a first tub of semiconductor material having the first polarity comprises the emitter, the first tub is formed in a second tub of semiconductor material comprising the base, and the second tub is formed in the substrate and has a second polarity opposite to the first polarity; and a resistor formed over the vertical bipolar transistor in a position at least partially overlying the first tub.