Patent ID: 8084800
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: (a) a semiconductor substrate; (b) an element isolation region formed over the semiconductor substrate; (c) a capacitor element formed over the element isolation region, the capacitor element (c) including: wherein the entire lower electrode and the entire upper electrode are formed over the element isolation region, wherein the length of the upper electrode in a first direction is larger than that of the lower electrode in the first direction, the length of the upper electrode in a second direction intersecting the first direction is smaller than that of the lower electrode in the second direction, the capacitor element is formed in a region where the upper electrode and the lower electrode overlap each other planarly, (d) a first side wall formed over a side face of at-he stepped portion of the upper electrode in the first direction, (e) a first insulating film formed so as to cover the first side wall, wherein the length of the first insulating film in a first direction is larger than that of the first side wall in the first direction, (f) a plurality of first metal silicide films formed over a surface of the upper electrode, wherein each of the plurality of first metal silicide films is spaced apart from the stepped portion by the first side wall and the first insulating film, and (g) a first plug coupled electrically to the upper electrode, wherein the first plug is formed in a region of the upper electrode where the upper electrode does not overlap the lower electrode planarly.