Patent ID: 8582711
Filing Date: 2013-11-12
Classification: G06F,H04J,H04L

Abstract:
1. A clock change device comprising: a serial-parallel conversion unit which converts serial data synchronized to a first clock into parallel data; a detection unit which detects the head of the parallel data; a data storing unit which latches the parallel data from the serial-parallel conversion unit with a latch timing that occurs once per every number of clock cycles of a second clock; a parallel-serial conversion unit which converts the parallel data stored in the data storing unit into the serial data synchronized to the second clock; and a timing adjusting unit which, each time a packet of serial data synchronized to the first clock is received, performs a timing adjustment to adjust the latch timing during the period from the receipt of the serial data to the latch timing of the head of the parallel data, so that the latch timing occurs a time after occurrence of a conversion timing of the serial-parallel conversion unit.