Patent ID: 6365475
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A method of forming a Metal Oxide Semiconductor (MOS) transistor with a Super Steep Retrograde (SSR) channel doping distribution on a substrate of a semiconductor wafer, the method comprising:forming a gate of the MOS transistor on the substrate; forming a source and a drain of the MOS transistor in the substrate; and performing an ion implantation process to simultaneously form a first doped region, a second doped region and a third doped region; wherein the first doped region is positioned under the gate and overlaps with the channel of the MOS transistor to form the Super Steep Retrograde channel doping distribution, the second doped region is positioned in a portion of the substrate under the source, the third doped region is positioned in a portion of the substrate under the drain, the second doped region and the third doped region are used to reduce the junction capacitance (Cj) between the substrate and the source and reduce the junction capacitance between the substrate and the drain, and the first doped region, the second doped region, the third doped region, the source, and the drain are all a first conductivity-type semiconductor.