Patent ID: 6825115
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising sequentially:forming a gate electrode over a main surface of a substrate with a gate dielectric layer therebetween, the gate electrode having an upper surface and side surfaces; forming shallow source/drain extensions in the substrates; forming dielectric sidewall spacers on the side surfaces of the gate electrode; forming first metal silicide layers on the main surface of the substrate adjacent the dielectric sidewall spacers and a second metal silicide layer on the upper surface of the gate electrode; and forming deep source/drain implants in the substrate under the first metal silicide layers by: forming preamorphized regions extending to a first depth from the main surface of the substrate to below the first metal silicide layers; and ion implanting to form the deep source/drain implants overlapping the preamorphized regions and extending to a second depth from the main surface of the substrate to below the first metal silicide layers.