Patent ID: 6269429
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A microcomputer comprising:a central processing unit;an interrupt request generation circuit for generating an interrupt processing request;a processing request control unit for controlling two processing requests in response to the interrupt processing request on a basis of a first interrupt mode for performing interrupt processing using a program stored in a program memory and a second interrupt mode for performing interrupt processing without using the program stored in said program memory; anda flash memory serving as an electrically programmable erasable read-only memory,wherein processing of writing/deleting data in/from said flash memory is performed in the second interrupt mode,wherein said central processing unit comprises a program counter for designating an address of said program memory at which an instruction to be executed is stored, an execution control unit for executing the instruction read out from said program memory, and a program status word register for storing an operation state of said execution control unit, when the processing request based on the first interrupt mode is generated, said central processing unit stops execution of the program, saves contents of said program counter and said program status word register, and reads out the program from said program memory to execute interrupt processing based on the first interrupt mode, and when the processing request based on the second interrupt mode is generated, the central processing unit interrupts execution of the program, maintains the states of said program counter and said program status word register without saving the contents thereof, and executes interrupt processing based on the second interrupt mode without using an instruction stored in said program memory.