Patent ID: 6259281
Filing Date: 2001-07-10
Classification: H03M

Abstract:
An analog sampling circuit for sampling an analog input signal at intervals of time precisely defined by a master clock signal, the analog sampling circuit comprising:N track-and-hold circuits each including a clock signal input, where N is an integer greater than unity; anda clock signal generator, including:a clock window signal generator, comprising:an input connected to receive the master clock signal, andN outputs,the clock window signal generator deriving clock window signals from the master clock signal and feeding one of the clock window signals to each of the outputs, the clock window signals having imprecisely-timed edges,N gate circuits, each generating a sub-sampling clock signal with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the one of the clock window signals, and comprising:a first input connected to one of the outputs of the clock window signal generator;a second input connected to receive the master clock signal; andan output connected to the clock signal input of one of the track-and-hold circuits.