Patent ID: 6631504
Filing Date: 2003-10-07
Classification: G01R

Abstract:
A hierarchical test control network for a chip design, comprising:a plurality of test control circuit blocks in a hierarchical structure having a plurality of hierarchical levels, said test control circuit blocks comprising a top-level test control circuit block having a chip access port (CAP) controller; and a plurality of lower-level test control circuit blocks, one or more of said lower-level test control circuit blocks at each of said hierarchical levels, at least one of said lower-level test control circuit blocks connected to said top-level test control circuit block, each of said lower-level test control circuit blocks comprising a socket access port (SAP) controller; wherein test operation is transferred downward and upwards within said hierarchical structure by communicating from each test control circuit block to the test control circuit block at the immediately higher or immediately lower hierarchical level in said hierarchical structure.