Patent ID: 9183105
Filing Date: 2015-11-10
Classification: G01R,G06F

Abstract:
1. A computerized system comprising: a processing module including a processor allowing the processing module to receive a plurality of scan operations associated with a plurality of segments of a system under test and to generate therefrom, through the processor, input test data configured to be applied to the system under test via a test access port; and a scheduler including a second processor and a memory storing a circuit model of the system under test, the circuit model defining the plurality of segments of the system under test, the scheduler adapted to scan the circuit model stored in memory and provide the processing module with scheduling for the plurality of scan operations based on the circuit model stored in the memory; wherein the circuit model includes, stored in the memory, at least one attribute providing enhancing information for at least one segment of the plurality of segments, the scheduler scanning the circuit model and processing the at least one attribute to dynamically modify the scheduling provided to the processing module based on the at least one attribute for the at least one segment.