Patent ID: 8816734
Filing Date: 2014-08-26
Classification: H03H,H03L

Abstract:
1. A clock generation circuit comprising: a delay line configured to delay an input clock and generate a delayed clock; a delay modeling block configured to delay the delayed clock by a modeled delay value, and generate a feedback clock; a phase detection block configured to compare phases of the input clock and the feedback clock and generate phase information, and to quantize a phase difference between the input clock and the feedback clock to generate phase codes; a multi-update signal generation block configured to generate a multi-update signal in response to the phase codes, wherein the multi-update signal generation block generates pulses of the multi-update signal by the number of times corresponding to a value of the phase codes; and a delay line control block configured to change a delay amount of the delay line in response to the multi-update signal and the phase information.