Patent ID: 6617631
Filing Date: 2003-09-09
Classification: H01L

Abstract:
An array of capacitors on a dynamic random access memory (DRAM) device comprised of:a semiconductor substrate having field oxide areas surrounding device areas and said device areas having semiconductor devices; a planar first insulating layer over said device areas and said field oxide areas; an array of polysilicon bit-line contact plugs and an array of capacitor node contact plugs in said first insulating layer to said device areas; a second insulating layer over said first insulating layer and over said polysilicon bit-line contact plugs and said capacitor node contact plugs, said second insulating layer with second openings to said bit-line contact plugs for bit lines; a patterned polycide layer over said second insulating layer for said bit lines in said second openings to said bit-line contact plugs; a planar third insulating layer over said bit lines; an etch-stop layer on said third insulating layer; polysilicon plugs extending through said etch-stop layer and said third and said second insulating layers to said capacitor node contact plugs; a fourth insulating layer composed of a low-dielectric-constant material having an array of recesses aligned over said capacitor node contact plugs and capacitors in said recesses, said capacitors having bottom electrodes formed from a first conducting layer, an interelectrode dielectric layer on said bottom electrodes, and a second conducting layer to form capacitor top electrodes, wherein said low-dielectric material between said capacitors reduces the parasitic capacitance between said capacitors.