Patent ID: 8659462
Filing Date: 2014-02-25
Classification: H03M

Abstract:
1. A successive approximation register analog-to-digital converter comprising: a sample-and-hold amplifier that samples and holds an externally input analog voltage; a comparator that compares a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, wherein n is an integer no less than 1; a successive approximation register logic circuit that sequentially generates a digital signal from a most significant bit to a least significant bit in response to the comparison signal; a digital-to-analog converter that converts the sequentially generated digital signal into the analog signal and providing the analog signal to the comparator; and an output register for holding the sequentially generated digital signal from the most significant bit to the least significant bit to generate an n-bit digital signal; wherein, upon externally receiving a start signal, the successive approximation register logic circuit generates a digital signal of a most significant bit having a one-bit phase delay compared with the start signal.