Patent ID: 7353340
Filing Date: 2008-04-01
Classification: G06F

Abstract:
1. A node comprising: at least one processor core configured to generate an address to access a memory location, wherein the address maps to a first coherence plane of a plurality of coherence planes, wherein coherence activity is performed within each of the plurality of coherence planes independent of other ones of the plurality of coherence planes, and wherein the address is included in an address space, and wherein a mapping of the address space across the plurality of coherence planes is independent of a physical location of the memory in a distributed system memory, and wherein the address space includes respective addresses that are mapped to each of the plurality of coherence planes; and a plurality of coherence units, wherein each of the plurality of coherence units corresponds to a respective coherence plane of the plurality of coherence planes and is configured to manage coherency for the node and for the respective coherence plane, the plurality of coherence units operating independent of each other, and wherein a first coherence unit of the plurality of coherence units corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.