Patent ID: 7154309
Filing Date: 2006-12-26
Classification: H03K

Abstract:
1. An integrated circuit comprising: a controller configured for outputting configuration signals for one of a first voltage mode and a second voltage mode, the first voltage mode corresponding to outputting an output signal at a first voltage range and a first frequency, the second voltage mode corresponding to outputting the output signal at a second voltage range and a second frequency, the first voltage range greater than the second voltage range and the second frequency substantially higher than the first frequency; and a dual mode output driver configured for selectively outputting the output signal at one of the first voltage mode and the second voltage mode in response to the configuration signals, the dual mode output driver including: a voltage source configured for outputting one of a first reference voltage for the first voltage range and a second reference voltage for the second voltage range in response to a first of the configuration signals, a high-voltage pull-up transistor coupled to the voltage source and an output node for the output signal, the high-voltage pull-up transistor configured for controlling a voltage rise of the output signal according to the first voltage mode in response to a second of the configuration signals, a high-voltage pull-down transistor coupled to the output node and configured for controlling a voltage drop of the output signal according to the first voltage range in response to a third of the configuration signals, a low-voltage pull-up transistor, coupled to the voltage source, and configured for controlling a voltage rise of the output signal according to the second voltage mode in response to a first gate signal generated based on a fourth of the configuration signals, a low-voltage pull-down transistor, coupled to a base reference voltage and the high-voltage pull-down transistor at a connecting node, and configured for controlling a voltage drop of the output signal according to the second voltage mode in response to a second gate signal generated based on a fifth of the configuration signals, and protection circuitry configured for protecting the low-voltage pull-up transistor and the low-voltage pull-down transistor from encountering an overvoltage condition during operation of the dual mode output driver in the first voltage mode.