Patent ID: 7590015
Filing Date: 2009-09-15
Classification: G11C

Abstract:
1. An integrated circuit device comprising: at least one memory block that includes memory cells and a redundant cell; an information storage block in which an address of a defective cell of the at least one memory block is programmed and stored as a defective address, the defective cell being replaced by the redundant cell; and a switch control circuit that switches access to the defective cell to access to the redundant cell, a row address of the defective cell being stored in the information storage block as the defective address, the switch control circuit including a first coincidence detection circuit and a second coincidence detection circuit, the first coincidence detection circuit receiving a first row address of a first access and the defective address from the information storage block, detecting whether or not the first row address coincides with the defective address, and activating a first switching signal when the first row address coincides with the defective address, the first access being an access from an electro-optical device, the second coincidence detection circuit receiving a second row address of a second access and the defective address from the information storage block, detecting whether or not the second row address coincides with the defective address, and activating a second switching signal when the second row address coincides with the defective address, the second access being an access from a host.