Patent ID: 6476634
Filing Date: 2002-11-05
Classification: G06F

Abstract:
An ALU circuit implemented in a Programmable Logic Device (PLD), the ALU circuit comprising:first and second data input terminals providing first and second data input signals, respectively; first and second operator input terminals providing first and second operator input signals, respectively; a carry-in input terminal; a carry-out output terminal; a result output terminal; a function generator coupled to the first and second data input terminals and the first and second operator input terminals, the function generator being configured to provide: an XOR function of the first and second data input signals and the first operator input signal, the XOR function providing an XOR output signal; a first multiplexer function of the first and second data input signals, providing a result of a first logical function to a first multiplexer output signal when the first operator input signal is high and providing a result of a second logical function to the first multiplexer output signal when the first operator input signal is low, the first and second logical functions each being functions of at least one of the first and second data input signals; and a second multiplexer function of the XOR output signal and the first multiplexer output signal, providing the XOR output signal to a function generator output terminal when the second operator input signal is high and providing the first multiplexer output signal to the function generator output terminal when the second operator input signal is low; an AND gate coupled to the first data input terminal and the second operator input terminal and having an AND output terminal; a carry multiplexer having a zero data input terminal coupled to the AND output terminal, a one data input terminal coupled to the carry-in terminal, an output terminal coupled to the carry-out terminal, and a select input terminal coupled to the function generator output terminal; and an XOR circuit having a first input terminal coupled to the function generator output terminal, a second input terminal coupled to the carry-in terminal, and an output terminal coupled to the result output terminal.