Patent ID: 6350993
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A layered structure for forming p-channel field effect transistors comprising:a single crystalline substrate, a first layer of relaxed Si1âˆ’xGex formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si1âˆ’xGex formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of undoped Si1âˆ’xGex formed epitaxially on said third layer, a fifth layer of Ge formed epitaxially on said fourth layer whereby said fifth layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a sixth layer of Si1âˆ’wGew formed epitaxially on said fifth layer where the Ge fraction w is in the range from 0.5 to <1.0 and where wâˆ’x >0.2 whereby said sixth layer is under compressive strain, and a seventh layer of Si1âˆ’xGex formed epitaxially on said sixth layer.