Patent ID: 8196075
Filing Date: 2012-06-05
Classification: G06F

Abstract:
1. A method of creating an input/output (I/O) model, comprising: determining a set of logical I/O pins of an unplaced and unrouted circuit design; determining pin placement of one or more of the logical I/O pins of the unplaced and unrouted circuit design on device pins of a target device; determining a respective I/O pin profile for each of the logical I/O pins; inputting a plurality of I/O pin models available for the device pins of the target device, each I/O pin model specifying a different respective set of one or more pin parameter values for simulation of I/O behavior of an I/O pin; selecting an I/O pin model from the plurality of I/O pin models for each of the logical I/O pins based on pin parameter values of the I/O pin model matching the respective I/O pin profile; wherein selecting an I/O in model from the plurality of I/O in models for each placed logical I/O pin includes: locating an I/O pin model from the plurality of I/O models having an I/O pin profile matching the determined I/O pin profile of the placed logical I/O pin; and creating an association between the placed logical I/O pin and the located I/O pin model; generating, by a programmed processor, an I/O model including each selected I/O pin model within the I/O model; inputting a generic package parasitic document specifying at least partial package parasitic information for the target device; selecting at least a portion of the package parasitic information for one or more selected I/O pin models within a particular package parasitic document; and storing the I/O model and particular package parasitic document in a non-transitory processor readable storage medium.