Patent ID: 8592860
Filing Date: 2013-11-26
Classification: H01L

Abstract:
1. An apparatus comprising: a semiconductor substrate comprising a first p-well and a second p-well adjacent the first p-well, wherein the first and second p-wells are separated by an n-type region; a first n-type active area over the first p-well, the first n-type active area electrically connected to a cathode of a first high reverse blocking voltage (HRBV) device; a first p-type active area over the second p-well, the first p-type active area electrically connected to an anode of the first HRBV device, wherein the first n-type active area, the first p-well and the n-type region are configured to operate as an emitter, a base, and a collector of a NPN bipolar transistor, respectively, and wherein the second p-well, the n-type region, and the first p-well are configured to operate as an emitter, a base, and a collector of a PNP bipolar transistor, respectively, the NPN bipolar transistor defining a forward trigger voltage of the first HRBV device and the PNP bipolar transistor defining a reverse breakdown voltage of the first HRBV device; and a first protection circuit electrically connected between a first pad and a second pad, wherein the first protection circuit comprises the first HRBV device, wherein the first protection circuit is configured to activate to provide protection against a transient electrical event received between the first and second pads when the transient electrical event has a first voltage polarity, and wherein the first HRBV device is configured to prevent the first protection circuit from activating when the transient electrical event has a second voltage polarity opposite the first voltage polarity.