Patent ID: 6617205
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory device, comprising steps of:respectively forming a first field-effect transistor in a memory cell area of a semiconductor substrate and a second field-effect transistor in a peripheral circuit area of the semiconductor substrate respectively provided with a low-resistance diffused region a conductive type of which is reverse to that of the semiconductor substrate, a gate dielectric film and a gate electrode; forming a conductor film electrically connected to said diffused region of the first field-effect transistor through first plural dielectric films after forming the first plural dielectric films covering the memory cell area and the peripheral circuit area; forming a first dielectric film over the first plural dielectric films; forming a first wiring layer electrically connected to said diffused region of the second field-effect transistor on the first dielectric film, through the first plural dielectric films and the first dielectric film; forming a second dielectric film over the first dielectric film; forming a concave by removing a predetermined portion of the second dielectric film and the first dielectric film in the memory cell area and exposing an upper portion of the conductor film; and forming at least a storage electrode, a capacitor dielectric film and a plate electrode on an inner face of said concave.