Patent ID: 8719650
Filing Date: 2014-05-06
Classification: G01R

Abstract:
1. A self-diagnosis system comprising: a test circuit including first and second diagnosis controllers which determine normality of a test target circuit by using an execution result of a test pattern in the test target circuit; a test circuit determination unit which determines normality of the test circuit by comparing a normality determination result of the test target circuit output from the first diagnosis controller with a normality determination result of the test target circuit output from the second diagnosis controller; and a first delay circuit which delays a timing for the second diagnosis controller to acquire an expectation value from a memory, with respect to a timing for the first diagnosis controller to acquire the expectation value obtained when the test pattern stored in the memory is executed, wherein the test circuit includes a memory which stores an expectation value, and the first and second diagnosis controllers include a memory control unit which controls reading the expectation value from the memory and generation of a control signal, and the first and second diagnosis controllers determine the normality of the test target circuit by comparing the execution result of a test pattern with the expectation value read out from the memory, in response to the control signal.