Patent ID: 8943287
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A multi-core processor system, comprising: a) a plurality of cores, each core comprising; b) a memory system, comprising: c) a common access bus for interconnecting said plurality of cores and said memory system, wherein said core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value, wherein each core processor memory access comprises an individual cache line memory access, and wherein each core processor rate limiter utilizes a token bucket process, said token bucket process including a) waiting until a core memory access count is reached following an initialization setting, wherein event counters in each core processor rate limiter are set to a predetermined value; b) determining a memory access envelope eligibility time (ET) when the core memory access count is reached; and c) waiting until said ET is reached.