Patent ID: 6483714
Filing Date: 2002-11-19
Classification: H01L,H05K

Abstract:
A multilayered wiring board comprising:(a) a first insulating layer having a mounting region for mounting a semiconductor device formed substantially centrally on a surface thereof; (b) an upper conductor layer formed on the other surface of the first insulating layer and underneath the mounting region; (c) a second insulating layer formed to have a surface facing the other surface of the first insulating layer and the upper conductor layer; (d) a line conductor layer comprising a plurality of line conductors, the line conductor layer being formed on the other surface of the second insulating layer and underneath the mounting region; (e) a first through conductor array, passing through the first and second insulating layers, for electrically connecting the semiconductor device to the line conductors of the line conductor layer; (f) a third insulating layer formed to have one surface facing the other surface of the second insulating layer and the line conductor layer; (g) a lower conductor layer formed on the other surface of the third insulating layer and underneath the mounting region, the lower conductor layer forming a stripline section together with the upper conductor layer and the line conductor layer; (h) a first wiring layer interposed between the other surface of the first insulating layer and the one surface of the third insulating layer, the first wiring layer having a plurality of first parallel conductor arrays, each of the first parallel conductor arrays being formed in one of a plurality of split regions formed around the stripline section, the split regions being separated by two to four straight lines intersecting at a point within the mounting region so that interior angles &thgr;11, &thgr;12; &thgr;1, &thgr;2; &thgr;3, &thgr;4; &thgr;5 to &thgr;7; &thgr;81 to &thgr;84 are approximately equal, and each of the first parallel conductor arrays being oriented in a direction parallel to a direction directed toward the point of intersection; (i) a second wiring layer formed on the other surface of the third insulating layer, the second wiring layer having a plurality of second parallel conductor arrays, each of the second parallel conductor arrays being formed in one of the split regions, and the second parallel conductor arrays being oriented orthogonal to the first parallel conductor arrays in the respective split regions; and (j) a second through conductor array, passing through the third insulating layer, for electrically interconnecting the first and second wiring layers, the second through conductor array forming a parallel conductor section, together with the first and second wiring layers.