Patent ID: 7636906
Filing Date: 2009-12-22
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit, comprising a hard macro, a plurality of logic cells and a plurality of wirings, wherein: said hard macro includes a hard macro main body, and a plurality of pins connected to said hard macro main body; each of said plurality of wirings is connected to one of said plurality of pins and to one of said plurality of logic cells; said plurality of pins include at least three first-type pins and at least three second-type pins; said first-type pins, each of which is adjacent to one of said first-type pins, are arranged along a first direction; said second-type pins, each of which is adjacent to one of said second-type pins, are arranged along a second direction; said first direction is oblique to said second direction on a plane; wherein: said plurality of wirings include first-type wirings and second-type wirings; each of said first-type wirings is arranged along a third direction; each of said second-type wirings is arranged along a fourth direction; said third direction is oblique to said fourth direction on the plane; each of said first-type wirings is connected to one of said first-type pins; and each of said second-type wirings is connected to one of said second-type pins.