Patent ID: 6895523
Filing Date: 2005-05-17
Classification: H03K

Abstract:
1. A pulse signal generating circuit for generating a specific pulse signal from a clock signal having a fixed cycle, comprising: an edge detector configured to detect rising and trailing edges of the clock signal; a first delay signal generator, including at least one first delay circuit having a first delay value, the first delay signal generator being configured to generate at least one first delay signal whose first delayed edge is delayed by the first delay value in relation to the rising edge of the clock signal; a second delay signal generator including at least one second delay circuit having a second delay value, the second delay signal generator being configured to generate at least one second delay signal whose second delayed edge is delayed by the second delay value in relation to the trailing edge of the clock signal; and a logic unit configured to generate a pulse signal by performing logic operations on the first and second delay signals.