Patent ID: 7402886
Filing Date: 2008-07-22
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate; a first portion of a layer formed above said substrate; a second portion of said layer formed above said substrate; and a trench isolation region formed in said substrate between said first and second portions of said layer, said trench isolation region including a first trench portion and a second trench portion, said first trench portion including two sidewalls, said second trench portion is at least partially filled with a grown dielectric; a first sidewall spacer coupled to a first sidewall of said first trench portion; a second sidewall spacer coupled to a second sidewall of said first trench portion; said first portion of said layer includes two sidewalls; said second portion of said layer includes two sidewalls; said integrated circuit includes a third sidewall spacer formed on a sidewall of said first portion of said layer and a fourth sidewall spacer formed on a sidewall of said second portion of said layer, said third sidewall spacer is adjacent to said fourth sidewall spacer; said first sidewall spacer is further coupled to said third sidewall spacer; and said second sidewall spacer is further coupled to said fourth sidewall spacer.