Patent ID: 8456944
Filing Date: 2013-06-04
Classification: G11C

Abstract:
1. A decoder circuit of a semiconductor storage device, comprising: a word line selection circuit that includes voltage application MOS transistors corresponding to each of a plurality of word lines that apply a normal voltage in a predetermined normal operation to the word lines corresponding to memory cells selected among a plurality of memory cells positioned at a portion where the plurality of word lines intersect a plurality of bit lines, and that applies a high voltage higher than the normal voltage in a predetermined high voltage operation to the word lines; and a level shift circuit that outputs to the voltage application MOS transistors at least one of the normal voltage and a ground voltage lower than the normal voltage according to a selection state of the word lines in the normal operation, and that outputs to the voltage application MOS transistor at least one of the normal voltage and the high voltage according to a selection state of the word lines in the high voltage operation, wherein the voltage application MOS transistors of the word line selection circuit include PMOS transistors, wherein the word line selection circuit includes a control PMOS transistor that controls output of a voltage applied to the voltage application MOS transistors, the control PMOS transistor including a source to which the normal voltage is input when the word line selection circuit performs the normal operation and to which the high voltage is input when the word line selection circuit performs the high voltage operation, and a drain connected to a source of each of the voltage application MOS transistors, and wherein the level shift circuit includes