Patent ID: 7023094
Filing Date: 2006-04-04
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, comprising: an orthogonal wire having a first minimum wire width, which is formed in a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to said first minimum wire width, which is formed in a second wiring layer which differs from said first wiring layer and extending in a diagonal direction in relation to said orthogonal wire; and a via having a size which is no greater than said first or second minimum wire width, which is formed at point at which said orthogonal wire and said diagonal wire overlap so as to connect said orthogonal wire and said diagonal wire, wherein one of said diagonal wire and said orthogonal wire includes an enlarged wire width region in a position at which said via is formed, the wire width of said enlarged wire width region being enlarged beyond said first or second minimum wire width.