Patent ID: 6723609
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of fabricating a metal-oxide semiconductor transistor (MOS transistor) on a substrate comprising:sequentially forming a gate oxide layer and a gate on the substrate; performing a first ion implantation process to form a first doped region in the substrate; sequentially forming a liner layer, a dielectric layer and a sacrificial layer on the substrate; performing a first etching process to simultaneously form an arc-shaped spacer on either side of the gate and remove portions of the dielectric layer and the sacrificial layer atop the gate by utilizing the liner layer as a first stop layer; performing a second etching process to remove portions of the sacrificial layer within the arc-shaped spacer by utilizes the dielectric layer as a second stop layer, and constructing a L-shaped spacer on either side of the gate; performing a third etching process to remove portions of the liner layer not covered by the L-shaped spacer; performing a second ion implantation process to form a second doped region with a gradient profile in portions of the substrate adjacent to either side of the L-shaped spacer; and performing a self-aligned silicide (salicide) process to form a silicide layer on the gate and on exposed portions of the substrate surface above the second doped region.