Patent ID: 6157052
Filing Date: 2000-12-05
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:first and second memory cell array regions arranged along a first direction;a peripheral circuit region including a predetermined area provided between said first and second memory cell array regions, the predetermined area including a first transistor of a first conductivity type formed on a first region and a second transistor of a second conductivity type formed on a second region, the first and second regions being arranged along a second direction crossing the first direction;a local wire connected to drains of the first and second transistors and formed by a first metal wiring layer;first and second wires disposed extending along the first direction and on the first and second regions respectively, and formed by a second metal wiring layer stacked on the first metal wiring layer with an insulation layer laid therebetween; anda plurality of upper wires disposed extending along the second direction and formed by a third metal wiring layer stacked on the second metal wiring layer.