Patent ID: 8318561
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a plurality of floating gate electrodes on a tunnel insulating film formed on a semiconductor substrate; filling a gap between side surfaces of the floating gate electrodes opposing each other with an element isolation insulating film; removing part of the element isolation insulating film to partially expose the side surfaces of the floating gate electrodes; reducing a width, in a channel width direction, of an upper portion of each of the floating gate electrodes by etching part of the upper portion of each of the floating gate electrodes from the exposed side surfaces, thereby the upper portion being narrower than a lower portion of the floating gate electrode, in the channel width direction; forming an interelectrode insulating film on the floating gate electrodes, part of the interelectrode insulating film being formed on side surfaces of the upper portions of the floating gate electrodes; and forming a control gate electrode on the floating gate electrodes, the control gate electrode being partially buried between the floating gate electrodes opposing each other.