Patent ID: 8958229
Filing Date: 2015-02-17
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device, comprising: a plurality of variable resistive elements formed on a substrate; a plurality of bit lines formed on the variable resistive elements, the bit lines being extended in a first direction and separated from each other by a first pitch; a plurality of cell word lines formed on the bit lines, the cell word lines being extended in a second direction and separated from each other by a second pitch; and a plurality of circuit word lines formed on the bit lines, the circuit word lines being extended only in the first direction and separated from each other by a third pitch, wherein the third pitch of the circuit word lines is larger than the first pitch of the bit lines; wherein the substrate includes a cell array region and a peripheral circuit region, the bit lines including first through nth bit lines arranged in order, the circuit word line including first through nth circuit word lines that correspond to the first through the nth bit lines, and the bit lines and the circuit word lines being electrically connected at the peripheral circuit region; wherein the peripheral circuit region includes a first peripheral circuit region formed on one side of the cell array region and a second peripheral circuit region formed on another side of the cell array region, at least some of the first through the nth circuit word lines being disposed on the first peripheral circuit region, and some of remaining first through nth circuit word lines being disposed on the second peripheral circuit region, wherein n is an integer greater than or equal to 2.