Patent ID: 6154862
Filing Date: 2000-11-28
Classification: G01R,G06F,G11C

Abstract:
A failure analysis memory for memory testing apparatus wherein: in a test mode for each of steps of testing a memory under stepwise varied test conditions through utilization of test data, an address and expectation data generated by a pattern generator, said test data is written in said memory under test at said address, data read out therefrom is compared by a logic comparator with said expectation data, the comparison result is written in said failure analysis memory at the corresponding address to analyze a failure of said memory under test, said failure analysis memory being masked at an address corresponding to that of said memory under test that has failed in the previous test; and in a remove mode, mask data is newly created for said failure analysis memory in preparation for writing therein the comparison result in the next test, said failure analysis memory comprising:a failure data storage part, anda mask data storage part;wherein said failure data storage part comprises: a failure data memory having a data input terminal supplied with a predetermined logical level; and a first memory control part which effect control so that, in said test mode, a write enable signal is generated in accordance with said comparison result and said predetermined logical level is written as failure data in said failure data memory at the corresponding address and that, in said remove mode, said failure data is read out from said failure data memory; andwherein said mask data storage part comprises: a mask data memory having a data input terminal supplied with a predetermined logical level; and a second memory control part which effects control so that, in said test mode, mask data is read out of said mask data memory at an address corresponding to said address from said pattern generator and is provided as an inhibit signal to said logic comparator to inhibit it from making a logical comparison at that address and that, in said remove mode, said failure data read out from said failure data memory is applied as a write enable signal to said mask data memory to write therein said logical level as mask data at the corresponding address.