Patent ID: 6236695
Filing Date: 2001-05-22
Classification: H03K,H04L

Abstract:
Output buffer circuitry fabricated on a common integrated circuit comprising:an output buffer with a controllable delay time for delaying a data signal;a reference output buffer comprising,a flip-flop circuit,a delay tuning buffer coupled to receive an output from the flip-flop circuit,a phase detector circuit coupled to receive an output from the delay tuning buffer,a fixed delay electrically located between the delay tuning buffer and the phase detector, the fixed delay comprising an external wire connected to first and second external connections of the integrated circuit, anda state machine coupled to an output of the phase detector; anda synchronous delay circuit coupled to the reference output buffer, the synchronous delay circuit provides a reference clock signal to the reference output buffer, the reference clock signal calibrates the delay time of both the reference output buffer and the output buffer to a predetermined delay time.