Patent ID: 6781875
Filing Date: 2004-08-24
Classification: G11C,H01L

Abstract:
A semiconductor memory device including a memory cell array having a plurality of memory cells, each of the memory cells comprising:a first MISFET including a first source region formed in a semiconductor layer, a first drain region which is formed in the semiconductor layer and which is apart from the first source region, and a first gate electrode formed on the semiconductor layer between the first source region and the first drain region, wherein the semiconductor layer between the first source region and the first drain region is a floating body in a floating state; and a second MISFET including a second source region formed in the semiconductor layer, a second drain region which is formed in the semiconductor layer and which is apart from the second source region, and a second gate electrode formed on the semiconductor layer between the second source region and the second drain region, wherein the semiconductor layer between the second source region and the second drain region is the floating body shared with the first MISFET.