Patent ID: 7746705
Filing Date: 2010-06-29
Classification: G11C

Abstract:
1. A memory device, comprising: a subset of memory cells in a sector in the memory device, wherein each memory cell of the subset of memory cells is configured to store one or more bits of data therein; and an optimization component that facilitates selection of memory cells to be in the subset of memory cells based at least in part on a respective location of at least a first memory cell with respect to other memory cells in the sector to facilitate an erase of at least a portion of the memory cells, comprising the first memory cell, in the sector, the subset of memory cells comprising the first memory cell, a second memory cell and a third memory cell, the optimization component selects the first memory cell associated with a first word line for erase and facilitates application of an erase voltage to the first word line and thereby the first memory cell, and selects the second memory cell adjacent to the first memory cell and associated with a second word line adjacent to the first word line, and selects the third memory cell adjacent to the first memory cell and associated with a third word line adjacent to the first word line, wherein a specified voltage is applied to the second word line and the third word line to facilitate application of a voltage bias corresponding to the erase voltage to the second memory cell and the third memory cell substantially simultaneously with the application of the voltage to the first memory cell to facilitate reduction in fringing effect associated with the first memory cell during the erase.