Patent ID: 6549598
Filing Date: 2003-04-15
Classification: H03D,H04L

Abstract:
A clock signal extraction circuit, comprising:an input terminal for receiving serial data having time periods each being an integer multiple of a fundamental time period of a clock signal to be reproduced; a delay element for providing a predetermined delay time to the serial data from the input terminal; a voltage controlled oscillator whose oscillation frequency is regulated by a control signal voltage for producing the clock signal; means for latching the serial data at the timing of the output signal of the voltage controlled oscillator; a phase comparator for comparing the serial data from the delay element and the latched serial data from the latching means and generating a detection signal representing a phase difference therebetween; and means for feed-backing the detection signal to the voltage controlled oscillator as the control signal voltage to minimize the phase difference detected by the phase comparator; wherein said predetermined delay time by said delay element is adjusted so that timings of the serial data from the delay element and the latched serial data from the latching means are equivalent to one another; and wherein said phase comparator detects the phase difference by comparing edges of the time periods in the serial data, thereby increasing a phase detection gain.