Patent ID: 7872930
Filing Date: 2011-01-18
Classification: G11C

Abstract:
1. A method for testing a memory device comprising: setting a supply voltage for the memory device at a first supply voltage level; writing test data to the memory device at the first supply voltage level in response to setting the supply voltage; decreasing the supply voltage for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data; accessing the test data from the memory device at the second supply voltage level, without identifying the test data, in response to decreasing the supply voltage; increasing the supply voltage for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data; reading the test data from the memory device at the third supply voltage level in response to increasing the supply voltage; and comparing the test data written to the memory device at the first supply voltage level to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.