Patent ID: 6492838
Filing Date: 2002-12-10
Classification: H03K

Abstract:
A dynamic circuit, comprising:a precharge transistor having an output connected to a precharge node for charging said precharge node during a precharge state; a DNG FET transistor connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state; and a logic section comprising a plurality of pull-down transistors that are connected in parallel, wherein each pull-down transistor of said plurality of pull-down transistors is connected to said precharge node and to said DNG node for discharging the precharge node during the evaluate state if so dictated by logical function inputs to the plurality of pull-down transistors, and each of said plurality of pull-down transistors has a precharge leakage current, a floating body voltage, and an input threshold level that is affected inversely by the body voltage; wherein the DNG FET has an associated DNG precharge leakage current that is greater than the sum of the respective precharge leakage currents from said plurality of pull-down transistors for lowering the voltage at the DNG node during the evaluate state thereby lowering each respective floating body voltage of said plurality of pull-down transistors.