Patent ID: 8441859
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. A flash memory device, comprising: a memory cell array comprising a plurality of memory cells arranged in rows connected to corresponding wordlines, and columns connected to corresponding bitlines, wherein each row of memory cells is configured to store multiple pages of data through the corresponding wordline; a voltage generation circuit configured to generate a program voltage to be applied to a selected wordline among the wordlines connected to the plurality of memory cells; and a program voltage controller configured to detect a program characteristic of selected memory cells connected to the selected wordline during programming of a first page of data in the selected memory cells, and to control a start level of a program voltage to be applied to the selected memory cells in a program operation used to store a second page of data, wherein the voltage generation circuit generates the program voltage based on a program code received from the program voltage controller, and wherein during programming of the first page of data, the program voltage controller stores the program code with a modified value corresponding to the voltage applied to the selected memory cells in a program loop where a first off-cell is detected.