Patent ID: 6115279
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate having a main surface;a memory array portion in said main surface, in which a plurality of memory cells are arranged in row direction and in column direction;bit lines each extending in said column direction and each of said bit lines connected to said memory cells;word lines each extending in said row direction and each of said word lines connected to said memory cells;a first peripheral circuit portion having a plurality of MOSFETs and said first peripheral circuit portion arranged adjacent to said memory array portion in said row direction;an external terminal formed on said main surface of said semiconductor substrate, and a predetermined voltage is supplied to said external terminal from outside of said semiconductor memory device;a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage supply lines,wherein said first and second voltage supply lines are connected to each other at the intersection of said first and second voltage supply lines,wherein one of said first and second voltage supply lines is connected to said external terminal, andwherein said predetermined voltage is supplied to said MOSFETs in said first peripheral circuit portion from said external terminal via said first and second voltage supply lines.