Patent ID: 7505351
Filing Date: 2009-03-17
Classification: G11C

Abstract:
1. A data output circuit for a semiconductor memory apparatus, the data output circuit comprising: a plurality of pads, respective ones of the pads being configured to be used exclusively in one of at least two kinds of unit data output modes or used commonly in all of the at least two kinds of unit data output modes; a plurality of data lines configured to transmit data from a plurality of memory banks to outside of the memory banks; and a data output control unit configured to output data from a data line among the plurality of data lines, according to at least one control signal, to respective signal lines corresponding to the pads used in a currently set unit data, wherein the data output control unit includes: a first control signal generating unit that is configured to generate a first control signal according to a command recognition signal that is enabled when a row address and a read command are input; and a data selecting unit that is configured to select data from the data line according to the first control signal or a second control signal, and output the data to the signal line corresponding to the pad used in the currently selected unit data output mode among the plurality of pads.