Patent ID: 6842370
Filing Date: 2005-01-11
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along columns of pillars; a number of first transmission lines coupled to the first source/drain region of each transistor along columns of the memory array; and a number of word lines formed parallel to the trenches along the rows of the memory array and coupled to the gate of each transistor; a number of second transmission lines coupled to the second source/drain region of each transistor along columns of the memory array; wherein at least one of the multiple bit cell transistors is adapted to have a charge programmed in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the first source/drain region a second voltage threshold region (Vt2) adjacent to the second source/drain region which vary depending on in which direction the transistor is operated; and wherein the first and second source/drain regions of the transistor share both the first and second source/drain regions respectively from another of the vertical multiple bit cells.