Patent ID: 8208311
Filing Date: 2012-06-26
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising a plurality of electrically data rewritable non-volatile semiconductor memory cells; a memory cell array in which the memory cells or memory cell units are arranged in matrix, the memory cell unit including at least one of the memory cells; a word line connected to a portion of the memory cells; a write circuit configured to perform write step operation for a selected memory cell included in the memory cells, a write voltage being applied to the word line connected to the selected memory cell in the write step operation; and a write verify circuit configured to perform write verify operation for the selected memory cell, a write verify voltage being applied to the word line connected to the selected memory cell in the write verify operation; wherein at least one write step operation and at least one write verify operation are repeated before completion of writing data into the selected memory cell, and more than one bit data is capable of being written into the memory cell and being stored in the memory cell; wherein when a first data is written into a first selected memory cell, first step and second step of first write verify operation are performed for the first selected memory cell between (n-th) write step operation and (n+1-th) write step operation (n is a natural number), the second step of the first write verify operation is performed after the first step of the first write verify operation, a first write verify voltage and a second write verify voltage are respectively applied to the word line connected to the first selected memory cell in the first step and the second step of the first write verify operation, the first write verify voltage is lower than the second write verify voltage; wherein when a second data is written into a second selected memory cell, first step and second step of second write verify operation are performed for the second selected memory cell between (n-th) write step operation and (n+1-th) write step operation (n is a natural number), the second step of the second write verify operation is performed after the first step of the second write verify operation, a third write verify voltage and a fourth write verify voltage are respectively applied to the word line connected to the second selected memory cell in the first step and the second step of the second write verify operation, the third write verify voltage is lower than the fourth write verify voltage; and wherein the second write verify voltage is lower than the third write verify voltage, difference between the second write verify voltage and the third write verify voltage is larger than difference between the first write verify voltage and the second write verify voltage, and the first data is different from the second data.