Patent ID: 6603266
Filing Date: 2003-08-05
Classification: H01J

Abstract:
A matrix addressable plasma flat-panel display comprising:a first transparent substrate; a plurality of linear display electrodes deposited in parallel rows across a surface of said first substrate; a dielectric layer of insulating film deposited upon said surface of said first substrate, said insulating film covering said display electrodes; at least one electrically conductive surface pad located upon the surface of said dielectric layer of insulating film in association with a corresponding display electrode, said conductive surface pad covering only a portion of said corresponding display electrode and cooperating with said display electrode to form a capacitor, said capacitor operative to store electrical charge whereby the efficiency of the plasma flat-panel display is improved; an electron emissive surface coating covering at least a portion of said insulating film and said display electrodes; a second substrate which is hermetically sealed to said first substrate, said second substrate having a plurality of micro-voids formed in a surface thereof which is adjacent to said first substrate, said micro-voids cooperating with said first substrate to define a plurality of sub-pixels which form rows parallel to said display electrodes and columns which are perpendicular to said display electrodes; a gas filling said micro-voids; a plurality of address electrodes incorporated within said second substrate, each of said address electrodes corresponding to one column of said sub-pixels; and a phosphor material deposited within each micro-void and associated with said address electrodes.