Patent ID: 8183688
Filing Date: 2012-05-22
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a module board including an upper surface, a plurality of first bonding leads formed on the upper surface, a plurality of second bonding leads formed on the upper surface, a plurality of substrate wirings electrically connecting the first bonding leads with the second bonding leads, and a lower surface opposite to the upper surface; a first memory chip including a first front surface, a plurality of first bonding pads formed on the first front surface, and a first rear surface opposite to the first front surface, and mounted over the upper surface of the module board such that the first rear surface of the first memory chip faces to the upper surface of the module board; a data processor chip including a main surface, a plurality of bonding pads formed on the main surface, and a back surface opposite to the main surface, and mounted over the upper surface of the module board such that the back surface of the data processor chip faces to the upper surface of the module board, and arranged next to the first memory chip in a plan view; a plurality of first wires electrically connecting the bonding pads of the data processor chip with the first bonding leads of the module board, respectively; a plurality of second wires electrically connecting the first bonding pads of the first memory chip with corresponding second bonding leads of the module board, respectively; a resin sealing the first memory chip, the data processor chip, the first wires and the second wires; and a plurality of ball electrodes formed over the lower surface of the module board; wherein the first bonding leads include inside bonding leads arranged between the data processor chip and the first memory chip in the plan view, and outside bonding leads arranged between the inside bonding leads and the first memory chip in the plan view; wherein the first front surface in the plan view of the first memory chip is quadrangular having a first side; wherein the first bonding pads of the first memory chip include a plurality of first data system bonding pads arranged along the first side, and a plurality of first data strobe bonding pads; wherein the main surface in the plan view of the data processor chip is quadrangular having a second side; wherein the bonding pads of the data processor chip include a plurality of data system bonding pads arranged along the second side, a plurality of data strobe bonding pads arranged along the second side, a plurality of power supply bonding pads arranged along the second side, and a plurality of ground bonding pads arranged along the second side; wherein the first memory chip is mounted over the upper surface of the module board such that the first side faces to the second side in the plan view; wherein the data system bonding pads of the data processor chip are electrically connected with the first data system bonding pads of the first memory chip via a plurality of data system wires of the first wires, some of the outside bonding leads, a plurality of first substrate wirings of the substrate wirings, and some of the second bonding leads, respectively; wherein the data strobe bonding pads of the data processor chip are electrically connected with the first data strobe bonding pads of the first memory chip via a plurality of data strobe wires of the first wires, some of the inside bonding leads, a plurality of second substrate wirings of the substrate wirings, and some of the second bonding leads, respectively; wherein the first substrate wirings are formed on one of the upper surface and the lower surface; and wherein the second substrate wirings are formed on other of the upper surface and the lower surface.