Patent ID: 6590254
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell region where a plurality of memory elements is formed, said memory element having a floating gate formed of a first conductive film, an insulation film formed on said floating gate, and a control gate formed of a second conductive film on said insulation film; a peripheral circuit region having a transistor with its gate electrode formed of said second conductive film for controlling said memory elements; an element isolating insulation film formed between said memory cell region and said peripheral circuit region; and a groove formed at a surface of said element isolating insulation film, said groove being formed in said element isolating insulation film in a boundary region between said memory cell region and said peripheral circuit region, said boundary region being defined as the region between a first side edge of the control gate in the memory cell region and a second side edge of the gate electrode in the peripheral circuit region, said groove formed at the second side edge of the boundary region.