Patent ID: 8719487
Filing Date: 2014-05-06
Classification: G11C,H03K

Abstract:
1. A data system, comprising: a Read Only Memory (ROM) writer comprising a Central Processing Unit (CPU), first control devices, and first memory, wherein the ROM writer is configured to provide data; and a plurality of memory socket assemblies (MSAs), each MSA having a socket configured to mechanically mount and thereby electrically connect a memory link architecture (MLA), wherein each MSA comprises a respective second memory and a respective second control device connected to one of the first control devices, each MSA being configured to control a first transfer of the data received from the ROM writer to the second memory and to control a second transfer of the data from the second memory to the MLA, wherein the first transfer of the data from the ROM writer to the second memory via the second control device occurs before the MLA is mounted into the socket of the MSA.