Patent ID: 6300891
Filing Date: 2001-10-09
Classification: H03M

Abstract:
A D/A conversion apparatus comprising:a decoder for converting a digital input value into n m-valued signals each corresponding to the amplitude level of the digital input value (where m is an integer not smaller than 3, and n is an integer not smaller than 2, the m value being 0,1, 2, . . . m-1);n m-valued D/A converters for converting the n m-valued signals output from the decoder into analog signals at the same phase; andan analog adder for summing the outputs of the n m-valued D/A converters, and wherein:the decoder maps the digital input value to the n m-valued signals a ""1"" at a time in a cyclic fashion progressing from one signal to the next so that the sum of the n m-valued signals becomes equal to the digital input value.