Patent ID: 6770523
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit wafer comprising:depositing a chemical-mechanical polishing stop layer on a semiconductor wafer; processing a first photoresist layer over the chemical-mechanical polishing stop layer to form a patterned first photoresist layer; processing to form a patterned chemical-mechanical polishing stop layer on the semiconductor wafer and to form a shallow trench in the semiconductor wafer using the patterned first photoresist layer; depositing a shallow trench isolation material on the chemical-mechanical polishing stop layer and in the shallow trench; processing a second photoresist layer to form a patterned second photoresist layer over the shallow trench isolation material and leaving uncovered shallow trench isolation material; treating the uncovered shallow trench isolation material using the patterned second photoresist layer to form a chemical-mechanical polishing stop treated area; and chemical-mechanical polishing the shallow trench isolation material to be co-planar with the patterned chemical-mechanical polishing stop layer and the chemical-mechanical polishing stop treated area.