Patent ID: 6049816
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A processor accessing an external program memory and external data memory through one port, comprising:a program selection unit for carrying one of a program from an internal memory and an external program memory onto a program bus in accordance with an external program request signal and an external memory preparation signal;an instruction fetch unit for fetching the program carried on the program bus in accordance with a program wait signal and a data wait signal and outputting an instruction;an instruction decoding unit for decoding an instruction from the instruction fetch unit;a control signal generation unit for fetching a decoding signal from the instruction decoding unit, outputting a control signal, and stopping a fetching operation of the decoding signal when the program wait signal or data wait signal is activated;a program counter for accessing a program memory in accordance with a control signal from the control signal generation unit;a memory accessing unit for judging whether an internal memory is accessed or an external memory is accessed in accordance with a program address from the program counter and a data address stored in the memory access unit, accessing an internal memory RAM when the internal memory is accessed, generating an external program request signal and external data request signal when the external memory is judged to be accessed, accessing the external program memory and external data memory, and disabling a request signal of the memory when the external memory ready signal is a high level;a data selection unit for carrying, on the data bus, one of the data from the RAM and a data from the external data memory in accordance with an external memory ready signal and external data request signal;a wait signal generation unit for enabling the program wait signal and data wait signal for temporarily stopping an internal pipeline operation when the external program request signal and external data request signal from the memory access unit are activated, disabling the program wait signal and data wait signal when the external memory ready signal becomes a high level, and normally maintaining the stopped pipeline operation; andan arithmetic operation unit for computing an internal or external output data based on an external or internal program in accordance with a control signal from the control signal generation unit.