Patent ID: 7616657
Filing Date: 2009-11-10
Classification: H03K,H04L

Abstract:
1. Serial data receiver circuitry on a programmable logic device comprising: a plurality of first channels of receiver circuitry, each of which is adapted to receive a serial data signal having a serial bit rate up to a first, relatively low, maximum bit rate, wherein each of the plurality of first channels includes a first clock data recovery circuit; a second channel of receiver circuitry that is adapted to receive a serial data signal having a serial bit rate up to a second, relatively high, maximum bit rate, wherein the second channel includes a second clock data recovery circuit different from the first clock data recovery circuit; clock multiplier circuitry including a plurality of first phase-locked loop circuits, each of which can supply clock signals suitable for use by any of the channels that is operating at a bit rate up to the first maximum bit rate but not significantly above the first maximum bit rate to the second maximum bit rate; a second phase-locked loop circuit that can supply clock signals suitable for use by any of the channels that is operating at a bit rate up to the second maximum bit rate; circuitry for distributing the clock signals supplied by the first and second phase-locked loop circuits to all of the first channels including each of the first clock data recovery circuits in the first channels; and circuitry that is dedicated to conveying the clock signals supplied by the second phase-locked loop circuit to the second channel.