Patent ID: 8458625
Filing Date: 2013-06-04
Classification: G03F

Abstract:
1. A method for modifying a chip design layout, said method comprising steps of: marking, in a chip design layout, regions of potential lithographic hot spots associated with an instance of a design shape with marker layers; adding multiplicate shapes to said instance of said design shape in said marker layers in said chip design layout; performing lithographic simulations for each marker layer in said chip design layout by running an optical correction program having multiplicate layer handling capability, wherein each of said multiplicate shapes is successively employed to perform lithographic simulations for said instance of said design shape in said marker layers; calculating a lithographic performance metric for each of said lithographic simulations; generating a modified chip design layout by selecting, for each marker layer, a multiplicate shape that satisfies at least one predefined selection criterion for said lithographic performance metric; and storing data representing said modified chip design layout in a non-transitory machine readable storage medium by encoding said data therein, wherein at least one of said steps among said step of marking, said step of adding, said step of performing, said step of calculating, and said step of generating is performed employing at least one computing means that is configured to run at least one automated program for performing said at least one of said steps.