Patent ID: 8631223
Filing Date: 2014-01-14
Classification: G06F

Abstract:
1. A method of data processing in a processor having a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, each of the first and second level register files including a plurality of physical registers, said method comprising: prior to execution of a particular transactional code section, placing one or more non-speculative register values in the first level register file; in response to processing one or more instructions in the transactional code section to generate as an execution result one or more speculative register values that are each assigned a respective register identifier that collides with that of one of the one or more non-speculative register values, moving one or more non-speculative register values from the first level register file to the second level register file on a register-by-register basis as needed to resolve collisions rather than en masse and placing the one or more speculative register values in the first level register file; in response to unsuccessful termination of the transactional code section, designating the one or more speculative register values in the first level register file as invalid, such that the one or more non-speculative register values moved to the second level register file belong to a working value set; and in response to successful termination of the transactional code section, designating the one or more speculative register values in the first level register file as non-speculative.