Patent ID: 7424579
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A processor chip, comprising: multiple programmable units integrated in the processor chip, wherein at least some of the multiple programmable units integrated in the processor chip comprise multi-threaded programmable units having multiple program counters corresponding to multiple threads of program execution; a random access memory controller integrated in the processor chip to couple to an off-chip random access memory, the random access memory controller coupled to the multiple programmable units integrated in the processor chip, the random access memory controller comprising logic to enqueue entries for memory reference requests received from the multiple programmable units into one of multiple queues and select from the enqueued entries to initiate a memory access operation of the off-chip random access memory, wherein the random access memory controller logic to select from the enqueued entries comprises logic to select from the enqueued entries in an order that differs from the order in which the memory reference requests are received from the multiple programmable units.