Patent ID: 6531742
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A CMOS device, comprising:an insulating film formed on a substrate; first and second sapphire patterns formed on the insulating film at fixed intervals; first and second semiconductor layers formed on the first and second sapphire patterns; isolating structures formed at outer edges of said first and second semiconductor layers, respectively; first and second trenches formed down to predetermined depths within the first and second semiconductor layers; sidewall spacer structures formed at both sides of the first and second trenches; a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures; first and second gate electrodes formed in the first and second trenches, respectively, on the gate insulating film; first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrode; and second conductivity type impurity regions formed in the second semiconductor layer on both sides of the second gate electrode.