Patent ID: 7149874
Filing Date: 2006-12-12
Classification: G06F

Abstract:
1. A memory module, comprising: a plurality of memory devices; and a memory hub, comprising: a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the plurality of memory devices, the memory device interface coupling memory requests to the memory devices and generating a status signal indicating whether or not at least one of the memory requests is being serviced; a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit generating and coupling a portion of each of the memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced; and a sequencer coupled to the link interface and the memory device interface, the sequencer generating and coupling memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is being serviced and generating and coupling the remaining portion of each of the memory requests not handled by the bypass circuit from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.