Patent ID: 6330201
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A circuitry for supplying data from a write amplifier through a write bus line pair to a digit line pair for writing said data into a memory cell and for reading out said data from said memory cell to supply said data from said digit line pair to a read out bus line pair, said circuitry comprising:a pair of switching devices for selectively connecting said write bus line pair and said read out bus line pair to said digit line pair;a first balancing device providing a first connection between lines of said write bus line pair to balance said write bus line pair by making equal a voltage level on each of the lines of said write bus line pair; anda controller connected to said first balancing device for sending a balancing signal to said first balancing device to start said balance operation at a timing immediately before said pair of switching device connect said write bus line pair to said digit line pair and balancing said write bus line pair by utilizing a period during which a signal of said data is transmitted from an input line pair of said write amplifier to said write bus line pair.