Patent ID: 7636870
Filing Date: 2009-12-22
Classification: G06F

Abstract:
1. A semiconductor integrated circuit device, comprising: a plurality of subsystems, a first one of said plurality of subsystems including a first processor, a second one of said plurality of subsystem including a second processor, and a third one of said first, second and third processors executing programs respectively in response to a first request; a debug control unit that includes a break detecting unit, said debug control unit stopping program execution in said first processor when said break detecting unit detects that program execution in said first processor satisfies a predetermined break condition; and a system debug control unit issuing a second request for stopping program execution in response to the detection result of said break detecting unit, wherein said second processor stops program execution in response to said second request, and wherein said third processor executes its program without responding to said second request when said second processor stops program execution in response to said second request.