Patent ID: 6194233
Filing Date: 2001-02-27
Classification: H01L

Abstract:
In a process for designing integrated circuits, a method for preventing electrostatic charges from damaging a gate of a transistor comprising:determining the routing of metallic conductors for said integrated circuit in a first metalization layer of said integrated circuit;determining for each metallic conductor formed in said metalization layer connected to a gate of a transistor the ratio of metallic area to gate connection area;identifying each metallic conductor having a ratio of metallic area to a gate connection area which exceeds a threshold value;tracing each identified metallic conductor for a location above said identified metallic conductor which is free of metallic conductors;breaking said identified metallic conductors at said location whereby a split conductor having spaced apart ends is created; andcreating first and second vias in an insulation layer which separates said identified metallic conductors and a second adjacent metalization level, and connecting said ends through said vias following creation of said second adjacent metalization layer, whereby said gates are protected from excessive charge build up prior to connecting said ends of said metallic conductors.