Patent ID: 7653795
Filing Date: 2010-01-26
Classification: G06F,G11C

Abstract:
1. A method of accessing data in a pipelined data processing apparatus in which the operating conditions of the pipelined data processing apparatus are such that metastable signals may occur on at least the boundaries of the pipelined stages, the method comprising the steps of: receiving an indication that an instruction is being fetched for processing by the pipelined data processing apparatus; generating a memory access prediction signal, the memory access prediction signal having a value indicative of whether or not the instruction being fetched for processing is likely to cause a read access from a memory; generating for the fetched instruction a predicted memory access control value from the memory access prediction signal, the predicted memory access control value being generated to achieve and maintain a valid logic level for at least a sampling period thereby preventing any metastability in the predicted memory access control value; and controlling initiation of a read access from the memory in dependence upon the memory access control value; wherein the step of generating the predicted memory access control value comprises the steps of: passing the memory access prediction signal through a pair of latches, each latch being clocked to coincide with the passing of the instruction between subsequent boundaries of the pipelined stages.