Patent ID: 6194272
Filing Date: 2001-02-27
Classification: H01L,Y10S

Abstract:
A method of forming, a non-volatile memory cell comprising:(a) forming a first dielectric layer on a surface of a semiconductor substrate, the semiconductor substrate having a substrate conductivity type;(b) forming a first conductive layer on the first dielectric layer;(c) patterning the first conductive layer and first dielectric layer to form a first gate structure separated from the semiconductor substrate by the first dielectric layer, and to form an exposed portion of the surface of the semiconductor substrate;(d) forming a second dielectric layer on a sidewall of the first gate structure and on the exposed portion of the surface of the semiconductor substrate;(e) forming a second conductive layer on the second dielectric layer;(f) patterning the second conductive layer to form a first spacer and a second spacer, the first spacer and the second spacer being separated from the first gate structure by the second dielectric layer;(g) removing the second spacer;(h) forming a first region in the substrate proximate to an opposite sidewall of the first gate structure and a second region in the substrate proximate to an edge of the first spacer, the first region and the second region having a conductivity type opposite to the substrate conductivity type; and (i) forming a pocket region in the semiconductor substrate, the pocket region being proximate to and substantially underlying the second gate structure and proximate to the second region, the pocket region having the substrate conductivity type.