Patent ID: 7830295
Filing Date: 2010-11-09
Classification: H03K,H03M

Abstract:
1. An analog-to-digital converter comprising: a first capacitor, a second capacitor, and a third capacitor each configured to sample an analog input voltage in cooperation with a first switching circuit, a second switching circuit, and a third switching circuit, respectively; a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage for the first capacitor, the second capacitor, and the third capacitor, respectively, and to apply the first reference voltage, the second reference voltage, and the third reference voltage to first terminals of the first capacitor, the second capacitor, and the third capacitor, respectively; a comparator between the analog input voltage and the first reference voltage, the second reference voltage, and the third reference voltage configured to compare a voltage at second terminals of the first capacitor, the second capacitor, and the third capacitor with a predetermined value; a charging timing controller configured to control the reference voltage generator to apply two reference voltages in order to obtain an analog-to-digital converted value at an (N+1)th most significant bit to the first terminal of two of the first capacitor, the second capacitor, and the third capacitor before an analog-to-digital converted value at an Nth most significant bit is determined, where N is an integer that is larger than or equal to one; and a comparing timing controller configured to control the comparator to determine an analog-to-digital converted value at the (N+1)th most significant bit by controlling the comparator to compare a voltage at the second terminals of the first capacitor, the second capacitor, and the third capacitor with the first terminal applied with a reference voltage according to the analog-to-digital converted value at the Nth most significant bit with a predetermined value after the analog-to-digital converted value at the Nth most significant bit is determined.