Patent ID: 6825064
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A fabrication method of a multi-chip semiconductor package, comprising the steps of:preparing a substrate having an upper surface and a lower surface opposed to the upper surface; mounting at least a first chip on the upper surface of the substrate; applying a non-conductive material over predetermined area on the first chip and the upper surface of the substrate; mounting at least a second chip on the non-conductive material, wherein the second chip is formed with at least a suspending portion free of interference in position with the first chip, and the non-conductive material having a chip contact portion formed on an upper surface of the first chip and at least a substrate contact portion formed on the upper surface of the substrate, the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported directly on the substrate contact portion of the non-conductive material; and forming an encapsulant on the upper surface of the substrate for encapsulating the first and second chips.