Patent ID: 8629498
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A power semiconductor device comprising: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of said semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of said drift layer; a second well region of the second conductivity type formed in a part of the surface layer of said drift layer at a distance from said first well region, said second well region having a smaller area than that of said first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of said first well region, said low-resistance region formed integrally or discretely so as to cover a region extending to most of said surface layer of said first well region and having a higher impurity concentration than that of said first well region; a gate insulating film formed on and in contact with surfaces of said first well region and said low-resistance region; and a gate electrode formed on and in contact with a surface of said gate insulating film; and a source electrode pad; a well contact hole connecting said first well region to said source electrode pad; and a source contact hole connecting said second well region to said source electrode pad, wherein in a region under said well contact hole, said source electrode pad and said low-resistance region are in contact with one another, a contact region having a higher impurity concentration than that of said low-resistance region is provided under said well contact hole.