Patent ID: 7910424
Filing Date: 2011-03-22
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor memory comprising: forming a tunnel insulating film for a memory cell transistor, a first gate insulating film for a low-voltage transistor, and a second gate insulating film for a high-voltage transistor on a semiconductor substrate; forming a first semiconductor film having a first conductivity type, which becomes a floating gate electrode of the memory cell transistor and a part of gate electrodes of the low-voltage transistor and the high-voltage transistor, on the tunnel insulating film, the first gate insulating film, and the second gate insulating film; forming a first insulating film, as an inter-layer insulating film for the memory cell transistor, on the first semiconductor film; removing the first insulating film on the first semiconductor film in areas in which gate electrodes of the low-voltage transistor and the high-voltage transistor are positioned, so as to expose the first semiconductor film; forming a second semiconductor film having a first impurity of the first conductivity type, which becomes a control gate electrode of the memory cell transistor and a part of gate electrodes of the low-voltage transistor and the high-voltage transistor, on the exposed first semiconductor film, and the first insulating film; delineating the floating gate electrode and the control gate electrode of the memory cell transistor, and the gate electrodes of the low-voltage transistor and the high-voltage transistor; and implanting a second impurity of a second conductivity type using the gate electrodes of the low-voltage transistor and the high-voltage transistor as a mask, so as to form source and drain regions having the second conductivity type in the semiconductor substrate, wherein an amount of the second impurity in the second semiconductor film is lower than that of the first impurity in the second semiconductor film.