Patent ID: 7435683
Filing Date: 2008-10-14
Classification: H01L,Y10S

Abstract:
1. A method of fabricating a multi-gate transistor, comprising: depositing a first dielectric layer for a spacer on a top surface and side surfaces of a gate and a body; planarizing the first dielectric layer and exposing the top surface of the gate; eroding the first dielectric layer to reduce the thickness of the first dielectric layer over the body and to expose the side surfaces of the gate; depositing a second dielectric layer for a spacer cap on the first dielectric layer and the side surfaces of the gate; eroding the second dielectric layer to expose the top surface of the gate and to form the spacer cap on a portion of the first dielectric layer and adjacent to the side surfaces of the gate; and eroding the first dielectric layer to expose the top surface and the side surface of the body.