Patent ID: 8928113
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A semiconductor word line decoder device comprising: a plurality of word line decoder device cells including multiple patterned metal-metal interconnect layers including at least a lower patterned metal-metal interconnect layer, a middle patterned metal-metal interconnect layer and an upper patterned metal-metal interconnect layer; and a pair of transistors spaced apart from one another and having respective gates coupled by a polysilicon lead and further coupled by a metal lead of one of said lower patterned metal-metal interconnect layer and said middle patterned metal-metal interconnect layer and a further pair of transistors spaced apart from one another and having respective further gates coupled by a further polysilicon lead, wherein said metal lead further couples said further gates, said metal lead, said polysilicon lead and said further polysilicon lead are parallel to one another, and said pair of transistors are disposed in different word line decoder device cells of said plurality of word line decoder device cells and said further pair of transistors are disposed in different word line decoder device cells of said plurality of word line decoder device cells.