Patent ID: 6699753
Filing Date: 2004-03-02
Classification: H01L,Y10S

Abstract:
A method of fabricating a contact-less array of non-volatile memory cells in a silicon substrate, the method comprising:(A) forming over the substrate a plurality of pairs of stacks of first and second layer polysilicon along a row, the first layer being insulated from the substrate, and the second layer being insulated from the first layer; (B) forming in the substrate a drain region between the two stacks in each pair of polysilicon stacks, each drain region being self-aligned to the edges of the two stacks between which the drain region is formed; (C) forming side-wall spacers adjacent to edges of each polysilicon stack; (D) forming in the substrate a source region between each of two adjacent pairs of polysilicon stacks, each source region being self-aligned to the side-wall spacers; (E) forming a composite layer of, in the order from bottom to top, HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B); (F) planarizing the surface area of the array after step (D) using an insulating material; (G) selectively removing the insulating material from over the row of cells after step (F) thereby creating a trench directly over the row of cells; and (H) converting the ONP composite layer to ONO composite layer after step (G).