Patent ID: 8811104
Filing Date: 2014-08-19
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a real memory cell; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a replica circuit including a plurality of replica units connected in series, each of the plurality of replica units including a dummy word line, a dummy bit line, and a plurality of dummy memory cells connected in parallel between the dummy word line and the dummy bit line, each of the plurality of replica units configured to read data from the plurality of dummy memory cells by activating the dummy word line and to output the data to the dummy bit line, wherein the dummy word line of a first one of the plurality of replica units is activated in response to data which is output to the dummy bit line of a second one of the plurality of replica units of a prior stage prior to the first one of the plurality of replica units; and an operation control circuit configured to activate a dummy access signal to activate the dummy word line of one of the plurality of replica units of a first stage in response to a read command, and to activate the sense amplifier enable signal in response to data output to the dummy bit line of one of the plurality of replica units of a last stage.