Patent ID: 8299833
Filing Date: 2012-10-30
Classification: H03K

Abstract:
1. A programmable clock control circuit, the circuit comprising: a base block configured to control operation of the programmable clock control circuit, the base block being coupled to a clock signal and having an output; a chop block configured to control the width of an output clock signal of the programmable clock control circuit and having a chop block output; a pulse width variation block coupled between the chop block and the base block, the pulse width variation block receiving the chop block output and providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths; a launch clock delay block coupled to the output of the base block to delay the output of the base block and having a clock signal output; a scan clock delay block coupled to the output of the base block to delay the output of the base block and having a scan clock output; and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.