Patent ID: 8766700
Filing Date: 2014-07-01
Classification: H03K

Abstract:
1. A sampled CMOS switch for connection between input and output nodes, comprising: first and second MOS devices in series between said input and output nodes, said first and second MOS devices being activated by a sample signal; and a pair of extended drain MOS devices connected in a “T” configuration between said input and output nodes, said pair of extended drain MOS devices being activated by an inverted sample signal; wherein said first and second MOS devices are NMOS devices having high threshold voltages and said pair of extended drain MOS devices are low-voltage DEPMOS devices; wherein said DEPMOS devices are a part of a feedback circuit further comprising: a third NMOS device and a fourth NMOS device connected between an analog voltage source and a reference potential, said third NMOS device being controlled by a signal on the input node, and a drain of said fourth NMOS device being connected to gates of said DEPMOS devices; a fifth NMOS device, a sixth NMOS device, and a current source connected in series between a supply voltage and the reference potential, a gate of said sixth NMOS device being connected to a gate of said fourth NMOS device and to a drain of said fifth NMOS device, and a gate of said fifth NMOS device being connected to said output node; and a switch to switchably connect the analog voltage source to a drain of the sixth NMOS device in accordance with a phase of the inverted sample signal, wherein the inverted sample signal is mirrored to the gates of said pair of DEPMOS devices.