Patent ID: 6441430
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A semiconductor memory device comprising:a plurality of floating gates formed on a semiconductor substrate; an interlayer insulating film formed on the floating gates; and a control gate formed on the interlayer insulating film; wherein at least first and second of the floating gates each comprise a lower floating gate whose sidewalls are substantially vertical relative to the surface of the semiconductor substrate and an upper floating gate formed on the lower gate and in a shape so that opposing sidewall portions of the upper floating gate are concave with respect to the gate interior and the opposing sidewall portions gradually widen towards a top of the upper floating gate, and an insulating film having first and second lower sidewall portions substantially vertical relative to the surface of the semiconductor substrate and upper sidewall portions gradually narrowed towards a top of the insulating film in respective correspondence with the shapes of the lower and upper floating gates.