Patent ID: 8114696
Filing Date: 2012-02-14
Classification: H01L

Abstract:
1. A method, comprising: disposing a well of a first conductivity type on a substrate of the first conductivity type; disposing a first impurity region of a drive transistor in the well; forming a first gate electrode of a second conductivity type for the drive transistor such that the first gate electrode is connected to the first impurity region; forming a second gate electrode of the second conductivity type for a select transistor such that the second gate electrode is formed in parallel to the first gate electrode; and disposing a second impurity region of the second conductivity type in the substrate such that the second impurity region is coupled to the second gate electrode and an output node of a unit pixel, wherein a width of the well disposed under the second impurity region is in a range from approximately −0.1 μm to approximately −0.33 μm.