Patent ID: 8498165
Filing Date: 2013-07-30
Classification: G11C

Abstract:
1. A data outputting method of a memory circuit, comprising: providing the memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data, wherein the data buffers are arranged in an order that is DQ[0], DQ[8], DQ[1], DQ[9], DQ[2], DQ[10], DQ[3], DQ[11], DQ[4], DQ[12], DQ[5], DQ[13], DQ[6], DQ[14], DQ[7]and DQ[15], a zeroth through eleventh metal lines are used to connect the data buffers, the 2k selecting one of a dual data outputting mode and a quadruple data outputting mode by a mode selector; if the quadruple data outputting mode is selected: when a clock signal triggers the 16 data buffers DQ[0]˜DQ[15], outputting the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9]; and when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], transferring the batch of the data stored in the data buffer DQ[2n +2]to be stored in the data buffer DQ[2n], and transferring the batch of the data stored in the data buffer DQ[2n +3] to be stored in the data buffer DQ[2n +1], for n is an integer from 0 through 2, and from 4 through 6.