Patent ID: 7711882
Filing Date: 2010-05-04
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a processing unit for processing data; a plurality of registers; and a data stack; said processing unit being responsive to each of a plurality of interrupt signals to carry out a corresponding interrupt routine; wherein on receipt of an interrupt signal, said processing unit is configured to begin an interrupt entry stacking process comprising storing on said data stack a plurality of data values indicative of a state of said processing unit stored in said plurality of registers; wherein on completion of an interrupt routine, said processing unit is configured to begin an interrupt exit unstacking process comprising returning said plurality of data values from said data stack to said plurality of registers; wherein in response to a further higher priority interrupt signal received whilst performing either said interrupt entry stacking process or said interrupt exit unstacking process, said processing unit is configured to abandon said interrupt entry stacking process or said interrupt exit unstacking process, and to begin a further interrupt entry stacking process comprising storing on said data stack a further plurality of data values stored in said plurality of registers.