Patent ID: 6496425
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A memory array, comprising:at least one memory block having columns of memory cells, each column memory cells being coupled to a local bit line; at least one primary grouping of memory cells, comprising a primary sensing device coupled to a first primary global bit line and a second primary global bit line, wherein each primary global bit line is coupled to at least two local bit lines of each memory block; at least one redundant grouping of memory cells, comprising a redundant sensing device coupled to a first redundant global bit line and a second redundant global bit line, wherein each redundant global bit line is coupled to at least two local bit lines of each memory block; and a comparator coupled to the at least one primary grouping of memory cells and the at least one redundant grouping of memory cells for selectively accessing one of the redundant groupings of memory cells when an address applied to the memory array corresponds to a memory cell in a known defective primary grouping of memory cells.