Patent ID: 9142567
Filing Date: 2015-09-22
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: (a1) a first transistor coupled between a first potential and a first node; (a2) a second transistor coupled between the first node and a second potential lower than the first potential; (a3) a third transistor coupled between the first potential and a second node; (a4) a fourth transistor coupled between the second node and the second potential; (b1) a first active region which is surrounded by an element isolation region and in which the first transistor is located; (b2) a second active region which is surrounded by the element isolation region and in which the second transistor is located; (c) an insulating layer placed below the first active region and the second active region; (d1) a first semiconductor region placed below the first active region via the insulating layer and surrounded by the element isolation region; (d2) a second semiconductor region placed below the second active region via the insulating layer and surrounded by the element isolation region; (e1) a third semiconductor region placed below the first semiconductor region and at least partially extending to a position deeper than the element isolation region; and (e2) a fourth semiconductor region which is placed below the second semiconductor region and at least partially extending to a position deeper than the element isolation region; wherein the first semiconductor region is coupled to the gate electrode of the first transistor; wherein the second semiconductor region is coupled to the gate electrode of the second transistor; wherein the third semiconductor region is a region having a conductivity type opposite to that of the first semiconductor region and coupled to the second potential, and wherein the fourth semiconductor region is a region having a conductivity type opposite to the second semiconductor region and coupled to the first potential.