Patent ID: 6194301
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A process for fabricating an integrated circuit device having a first transistor and a second transistor, comprising:providing a semiconductor substrate;forming a well within the semiconductor substrate;forming a first gate oxide layer on the semiconductor substrate;depositing a first gate conductor layer on the first gate oxide layer;depositing a gate cap dielectric layer on the first gate conductor layer;patterning the first gate oxide layer, first gate conductor layer, and gate cap dielectric layer to form first gate electrodes;forming source/drain areas adjacent to and self-aligned with the first gate electrodes;depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate;etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes;depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate;chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes;stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate;forming a second gate oxide at the selected region of the semiconductor substrate;depositing a second gate conductor on the second gate oxide;forming a salicide at an upper portion of the second gate conductor, whereby a second gate electrode is formed;depositing a second interlevel dielectric layer over the first and second gate electrodes and first level dielectric layer; andforming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions.