Patent ID: 8571158
Filing Date: 2013-10-29
Classification: H03L,H04L

Abstract:
1. A data transceiving system for generating a reference clock signal, comprising: a voltage controlled oscillator, for generating the reference clock signal; a phase lock loop (PLL) unit, coupled to the voltage controlled oscillator, for increasing a clock frequency of the reference clock signal to generate a PLL clock signal; and a data receiver, coupled to the PLL unit and the voltage controlled oscillator, for receiving an input data stream and the PLL clock signal so as to output a voltage adjusting signal to the voltage controlled oscillator, wherein the data receiver comprises: a frequency detector, for receiving the input data stream and comparing a clock frequency of the PLL clock signal with a base frequency of the clock signal of the input data stream, so as to generate a frequency adjusting signal; a clock and data recovery circuit, for receiving the input data stream and the PLL clock signal, and transforming the input data stream into a retimed data stream by using the PLL clock signal as a reference clock; a SOF decoder, for finding a start-of-frame (SOF) of each of a plurality of frames in the retimed data stream, so as to generate SOF signals; and a frequency lock controller, for receiving the frequency adjusting signal and the PLL clock signal and accordingly generating the voltage adjusting signal, or receiving the SOF signals generated by the SOF decoder and the PLL clock signal, counting the SOF signals by using the PLL clock signal, and accordingly generating the voltage adjusting signal, wherein the voltage controlled oscillator adjusts the clock frequency of the reference clock signal according to the voltage adjusting signal, so as to lock the clock frequency of the PLL clock signal generated by the PLL unit to the base frequency of the clock signal of the input data stream, wherein when the SOF is not detected, the frequency lock controller receives the frequency adjusting signal and the clock signal and accordingly generates the voltage adjusting signal, so as to determine whether to increase or reduce the clock frequency of the reference clock signal, and when the SOF is detected by the SOF decoder, the frequency lock controller counts a number of the SOF of the plurality of frames in the retimed data stream, which is transformed from the input data stream, to determine whether to increase or reduce the clock frequency of the reference clock signal.