Patent ID: 6424190
Filing Date: 2002-07-23
Classification: G06F,H03K,H03L

Abstract:
A transition delay matching circuit comprising:(a) a first frequency dividing means for implementing frequency division on a first clock signal, said first frequency dividing means producing a first divided clock signal; (b) a second frequency dividing means for implementing frequency division on a second clock signal, said second frequency dividing means producing a second divided clock signal, wherein said second clock signal is substantially 180 degrees out of phase with said first clock signal; and (c) amplitude limiting means for limiting a divided clock steady state voltage differential between said first divided clock signal and said second divided clock signal, wherein said first divided clock signal is substantially in phase with said first clock signal, wherein said second divided clock signal is substantially in phase with said second clock signal, wherein said amplitude limiting means causes said divided clock steady state voltage differential to be substantially equal to a voltage differential between said first clock signal and said second clock signal immediately prior to a transition of said first clock signal from one steady state value to another steady state value, so that said first divided clock signal and said second divided clock signal more quickly transition to steady state values.