Patent ID: 7328332
Filing Date: 2008-02-05
Classification: G06F

Abstract:
1. A processor having a pipeline and operable to process a plurality of instructions including branch instructions, said processor comprising: a fetch pipeline having branch prediction circuitry to provide an indication of a taken branch or a not taken branch and store and supply respective predicted taken target addresses for some or all of said branch instructions in said plurality of branch instructions; an execution pipeline having a branch execution circuit; and storage elements and control logic operable to establish a first-in-first-out (FIFO) circuit with a write pointer and a read pointer, wherein said control logic is coupled to said branch prediction circuitry to receive said indication of taken or not taken; wherein said control logic is responsive, to said indication indicating that a given branch instruction in the plurality of instructions is predicted to be a taken branch, to write a predicted taken target address, corresponding to said given branch instruction, to a said storage element identified by the write pointer and the predicted taken target address remaining stationary therein and so that said storage elements of said FIFO circuit do not store predicted not taken branches, said control logic operable to read a predicted taken target address from a storage element identified by the read pointer to said branch execution unit without said read predicted taken target address passing through a plurality of pipestages between said branch prediction circuitry and said branch execution circuit.