Patent ID: 6881670
Filing Date: 2005-04-19
Classification: H01L

Abstract:
1. A process for fabricating metal interconnects, comprising the steps of: providing a substrate having a dielectric layer and a silicon-containing mask layer over the dielectric layer; patterning the dielectric layer to form an opening using the silicon-containing mask layer as an etching mask; forming a metallic glue layer over the silicon-containing mask layer and interior surfaces of the opening; forming a metallic layer over the substrate to fill the opening and cover the metallic glue layer; performing a thermal treatment so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer; removing a portion of the metallic layer using the metal silicide layer as an stopping layer so that the metal silicide layer is exposed; performing a cleaning process to remove the metallic silicide layer; and removing the silicon-containing mask layer so that the dielectric layer is exposed.