Patent ID: 7485508
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure comprising: providing a semiconductor-on-insulator (SOI) substrate with a carrier substrate, a buried insulator layer, and a first semiconductor layer; forming at least one first type MOSFET on said first semiconductor layer; forming a first stress liner directly on said at least one first type MOSFET, wherein said first stress liner applies a first stress to a first channel of said at least one first type MOSFET; forming a first middle-of-line (MOL) dielectric layer on said at least one first type MOSFET; bonding a handle wafer on said first MOL dielectric layer; removing a lower portion of said carrier substrate and exposing a second semiconductor layer; forming at least one second type MOSFET on said second semiconductor layer, wherein said at least one first type MOSFET and said at least one second type MOSFET are at least one p-type MOSFET and at least one n-type MOSFET, respectively, or said at least one first type MOSFET and said at least one second type MOSFET are at least one n-type MOSFET and at least one p-type MOSFET; and forming a second stress liner directly on said at least one second type MOSFET, wherein said second stress liner applies a second stress to a second channel of said at least one second type MOSFET, wherein said first stress and said second stress are a compressive stress and a tensile stress, respectively, or a tensile stress and a compressive stress, respectively.