Patent ID: 8228107
Filing Date: 2012-07-24
Classification: G06F,H03L

Abstract:
1. A clock signal balancing circuit for synchronizing a first clock signal with a second clock signal, the clock signal balancing circuit comprising: a buffer gain controlling circuit for comparing the first clock signal with the second clock signal and accordingly generating a buffer gain; and a variable gain buffering circuit coupled to the buffer gain controlling circuit, wherein the variable gain buffering circuit receives a third clock signal, adjusts a timing of the third clock signal accord to an amplitude of the buffer gain, and outputs the adjusted third clock signal; wherein the first clock signal is received by a first register, and the second clock signal is received by a second register; wherein data processed by the first register is related to data processed by the second register; wherein the data processed by the first register is directly transmitted to the second register or transmitted through a combinational logic circuit to the second register.