Patent ID: 7187694
Filing Date: 2007-03-06
Classification: H04L

Abstract:
1. A packet parser comprising: logic circuitry adapted to receive a first portion of a control information disposed in a packet being parsed and to transition from a first state to a second state if the first portion of the control information matches a first criteria associated with the first state; logic circuitry adapted to receive a second portion of the control information disposed in the packet and to transition from the second state to a third state if the second portion of the control information matches a second criteria associated with the second state; logic circuitry adapted to receive a third portion of the control information disposed in the packet and to transition from the first state to the third state if the first portion of the control information disposed in the packet matches a third criteria associated with the first state; an offset register that is incremented if a transition from the first state to any of the second and third states is made; logic circuitry adapted to transition from the first state to a default state if the first portion of the control information disposed in the packet does not match any one of the criteria associated with the first state; logic circuitry adapted to transition from said default state to a fourth state; a processor adapted to execute at least one instruction at one or more of the first, second, third, fourth and default states; wherein said processor is adapted to set a flag at one or more of the first, second, third, fourth and default states; a memory coupled to the processor and adapted to store records associated with each parsing state and records associated with each transition originating from each parsing state; and a plurality of comparators each coupled to the memory and each adapted to receive a record associated with a different one of the transitions originating from each parsing state.