Patent ID: 6591343
Filing Date: 2003-07-08
Classification: G06F

Abstract:
An apparatus in a pipeline microprocessor for predecoding macro instructions, the apparatus comprising:an instruction cache, configured to store instruction bytes, said instruction cache comprising a plurality of cache ways, said instruction cache comprising a plurality of tag arrays, each of said plurality of tag arrays coupled to a corresponding cache way, and storing tags within, wherein specific tags within said each of said plurality of tag arrays denote specific physical page addresses associated with corresponding cache lines within said cache ways; predecode logic, coupled to said instruction cache, configured to predecode instruction bytes retrieved from each of said plurality of cache ways, wherein said each of said plurality of cache ways comprises cache lines, and wherein said instruction bytes are stored within said cache lines, and wherein low-order bits of a requested linear address are provided to said each of said plurality of cache ways to indicate said instruction bytes, and wherein said low-order bits are provided to said plurality of tag arrays to retrieve a corresponding plurality of indexed tags, each of said plurality of tags being retrieved from a corresponding each of said plurality of tag arrays; way selection logic, coupled to said predecode logic, configured to provide for translation a set of said instruction bytes and associated predecode data entities that correspond to one of said each of said plurality of cache ways; a translation lookaside buffer, coupled to said way selection logic, configured to translate upper address bits of said requested linear address into a requested physical page address; and tag compare logic, coupled to said translation lookaside buffer, configured to compare said requested physical page address with said corresponding plurality of tags, and configured to select one of said plurality of tags that matches said requested physical page address, thereby denoting said one of said each of said plurality of cache ways, wherein said tag compare logic directs said way selection logic to provide said set of said instruction bytes and said associated predecode data entities for translation; wherein said predecode logic predecodes said instruction bytes while said translation lookaside buffer converts said upper address bits of said requested linear address into said requested physical page address.