Patent ID: 8064241
Filing Date: 2011-11-22
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a plurality of memory cells each having a capacitor capable of storing an electric charge corresponding to a logic of data; bit lines coupled to each of the memory cells; a voltage detection circuit being provided corresponding to a pair of the bit lines from which complementary data are read, and outputting a detection signal when an amount of charges read to one of the pair of the bit lines reaches a predetermined amount when the memory cells are accessed; a timing generator having a plurality of cascade-coupled delay circuits, outputting timing signals from each of the delay circuits, and outputting a sense amplifier activation signal in response to one of the timing signals; and a sense amplifier determining logics of data read to the bit lines from the memory cells in synchronization with the sense amplifier activation signal, wherein the timing generator comprises a mask circuit masking an output of the sense amplifier activation signal until the detection signal is output, and a delay circuit in a next stage of one of the delay circuits outputting the one of the timing signals operates upon reception of the sense amplifier activation signal.