Patent ID: 6782498
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A semiconductor memory device operating in response to a plurality of command control signals and an address signal including a plurality of address bits, comprising:a memory cell array including a plurality of memory cells arranged as a matrix; a plurality of external command terminals externally receiving said plurality of command control signals; a plurality of external address terminals externally receiving said plurality of address bits; a self test circuit operating at a time of test execution and supplying said plurality of command control signals and said plurality of address bits based on a predetermined test pattern; a first input switching circuit for supplying a plurality of internal command control signals according to (1) said plurality of command control signals received from said plurality of external command terminals, or (2) the plurality of command control signals received from said self test circuit; a second input switching circuit for supplying an internal address signal having a plurality of internal address bits according to (1) said plurality of address bits received from said plurality of external address terminals, or (2) the plurality of address bits received from said self test circuit; a test mode circuit determining an operation state of said self test circuit according to said plurality of internal command control signals and said internal address signal; and a control circuit controlling outputs of said first and second input switching circuits according to said operation state of said self test circuit, said control circuit controlling an operation for said memory cell array according to said plurality of internal command control signals and said internal address signal.