Patent ID: 6530014
Filing Date: 2003-03-04
Classification: G06F

Abstract:
A microprocessor including two MAC processors, an input of each MAC processor being cross-connected to the input of the other MAC processor, each MAC processor having a multiplier connected to an adder, said adders being connected to an accumulator having a plurality of registers, an output of the multiplier of one MAC processor being cross-connected to the input of the adder of the other MAC processor, said microprocessor having a reduced set of architected instructions in which the architected instructions for controlling said multipliers and adders are comprised of:only two single two-input accumulate statements associated with a particular one of said two MAC processors; only four dual two-input accumulate statements, each of said dual two-input accumulate statements being restricted to acting on predefined pairs of accumulator registers; only four three-input accumulate statements; only one single-product statement; and only four dual-product statements, no two of which form a symmetric pair.