Patent ID: 9170901
Filing Date: 2015-10-27
Classification: G01R,G06F

Abstract:
1. A method for testing a device under test having an embedded logic analyzer and input circuitry, one or more outputs of the input circuitry being coupled to one or more inputs of the embedded logic analyzer, the method comprising: receiving an identification of at least one signal appearing in the device under test and provided to the input circuitry, for display during a test or debug session of the device under test; translating the identified at least one signal into one or more signals associated with the embedded logic analyzer based at least in part upon information relating to the device under test, the embedded logic analyzer and the input circuitry, the one or more signals being different from the at least one signal appearing in the device under test; receiving, by a computing device, samples of the one or more signals from the embedded logic analyzer, the embedded logic analyzer sampling the one or more signals during the test or debug session; reconstructing, by the computing device, the identified at least one signal based upon the sampled one or more signals received from the embedded logic analyzer; and displaying the reconstructed at least one signal to the user.