Patent ID: 6018479
Filing Date: 2000-01-25
Classification: G11C

Abstract:
A high voltage generating circuit for semiconductor memory device having a memory cell array, and a row decoder, a column decoder and a Y-access portion for operating the memory cell array, the circuit comprising:a first clock generator for generating first and second clock signals CLK1 and CLK1a during read and standby mode and program and erasure mode;a first pump for outputting a constant high voltage from the first clock signal of the first clock generator during read and standby mode, or generating first and second pumping voltages during program and erasure mode;a first voltage adjustment portion for outputting a row decoder operation signal from the constant high voltage of the first pump during read and standby mode and maintaining high voltage during program and erasure mode;second and third clock generators for generating third and fourth clock signals CLK2 and CLK3, respectively, during program and erasure mode;a second pump for outputting a third pumping voltage from the third clock signal of the second clock generator and the first and second pumping voltages of the first pump during program and erasure mode;a third pump for outputting a fourth pumping voltage from the fourth clock signal CLK3 of the third clock generator during program and erasure mode;a second voltage adjustment portion for controlling the operation of the first, second and third clock generators by inputting the third and fourth pumping voltages during program and erasure mode, and outputting each operation voltage of the row decoder, the column decoder and the Y-access portion; anda voltage generator for outputting a constant high voltage to the first voltage adjustment portion during program and erasure mode.