Patent ID: 6775344
Filing Date: 2004-08-10
Classification: G11B,H03L,H04L

Abstract:
A dropout resistant phase-locked loop for synchronizing a received data signal with a read clock comprising:a phase detector in communication with the received data signal and the read clock, the phase detector operative to output a phase difference signal indicating phase difference between the received data signal and the read clock when a disable signal is not asserted and indicating zero phase difference between the data signal and the read clock when the disable signal is asserted; a loop error controller operative to input the phase difference signal and output a filtered phase difference signal, the loop error controller operative to set phase-locked loop dynamic performance; a voltage controlled oscillator operative to input the filtered phase difference signal and output the read clock; and a comparison system for generating the disable signal based on at least one data signal quality indication, the comparison system operative to assert the disable signal when the at least one data signal quality indication falls outside of at least one threshold level and deassert the disable signal otherwise; whereby the effect of data signal dropout is reduced by having the voltage controlled oscillator generate constant frequency and minimize phase shift during periods when the at least one data signal quality indication falls outside of the at least one threshold level.