Patent ID: 6323088
Filing Date: 2001-11-27
Classification: G11C,H01L

Abstract:
A method of forming a memory cell comprising the steps of:forming a first floating gate region on a silicon substrate;forming a second floating gate region on said silicon substrate; said second floating gate region being adjacent to and electrically isolated from said first floating gate region;forming a sidewall insulator on at least one of said first and second floating gate regions;forming an insulating layer over said first and second floating gate regions;forming a control gate region over said insulating layer and over said first and second floating gate regions;forming active doped regions in said substrate such that said first and second floating gate regions are located at least in part between said active doped regions; andforming electrical interconnects with said active doped and control gate regions, at least one of the electrical interconnects to an active doped region also connecting with said sidewall insulator.