Patent ID: 6982896
Filing Date: 2006-01-03
Classification: G11C

Abstract:
1. A nonvolatile ferroelectric memory device having a multi-bit control function, comprising: a plurality of cell array blocks for outputting a plurality of different cell data sensing voltages induced to a main bitline in a reference timing strobe interval, wherein each of the plurality of cell array blocks comprises a nonvolatile ferroelectric memory; a timing data register array unit for comparing the plurality of cell data sensing voltages with a plurality of preset sensing critical voltages to output comparison results corresponding to a plurality of bit data, and for converting a plurality of inputted bit data or the plurality of cell data sensing voltages into analog reference level signals; and a common data bus unit, connected in common to the plurality of cell array blocks, for controlling data exchange between the plurality of cell array blocks and the timing data register array unit.