Patent ID: 7336086
Filing Date: 2008-02-26
Classification: H01L

Abstract:
1. An apparatus for measuring bias of a silicon area comprising: a first plurality of polysilicon shapes, wherein each polysilicon shape of the first plurality of polysilicon shapes is formed having a bridging vertex positioned near the silicon area; a second plurality of polysilicon shapes, wherein each polysilicon shape of the second plurality of polysilicon shapes is formed having a bridging vertex positioned near the silicon area and positioned generally opposed to the first plurality of polysilicon shapes; and wherein each plurality of polysilicon shapes may be used to detect a first quantity of electrical shorts when bias is not present and may be used to detect a second quantity of electrical shorts when a bias is present, the second quantity of shorts differing from the first quantity of shorts; and wherein a bridging vertex is a portion of a particular polysilicon shape on a semiconductor chip, the portion having an angle, as seen from a top view, acute enough to prevent a sidewall spacer being formed on a vertical surface of the particular polysilicon shape at the bridging vertex during a step of processing the semiconductor chip having the plurality of polysilicon shapes, including the particular polysilicon shape, and the silicon area, thereby allowing silicide to form on the vertical surface of the particular polysilicon shape at the bridging vertex in a silicide step performed during processing of the semiconductor chip.