Patent ID: 6404685
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A circuit for equilibrating a bitline and a plateline of a dynamic plate sensing memory device, comprising:a first switching device having first and second terminals defining a conduction path therebetween, wherein the first terminal of the first switching device is connected to the plateline and the second terminal of the first switching device is connected to a first power rail; an on-pitch circuit having a first terminal connected to a first portion of the bitline and a second terminal connected to a second portion of the bitline, wherein the on-pitch circuit includes: a second switching device having first and second terminals defining a conduction path therebetween, wherein the first terminal of the second switching device is connected to the second portion of the bitline; and an inverter circuit having a first terminal connected to the first portion of the bitline and a second terminal connected to the second terminal of the second switching device; and a third switching device having first and second terminals defining a conduction path therebetween, wherein the first terminal of the third switching device is connected to the second portion of the bitline and the second terminal of the third switching device is connected to the plateline.