Patent ID: 9123891
Filing Date: 2015-09-01
Classification: G11C,H01L

Abstract:
1. A process comprising: forming an island in a semiconductive film to include an island first height; reducing the island first height to an island second height, wherein the island second height is defined by a first wall and a second wall in the semiconductive film; wherein forming the first and the second wall includes: forming a patterned nitride film above the semiconductive film, wherein the semiconductive film is an n-doped semiconductive material above a p-doped semiconductor material; etching the semiconductive film to expose the p-doped semiconductive material; wherein the etching exposes the first wall and second walls of the island second height to form a recess; filling adjacent the island with a shallow-trench isolation (STI); forming a metal diode plug above and within the island second height, wherein the metal diode plug also contacts the first wall and the second wall; forming an electrode above and on the metal diode plug; and coupling the electrode to a variable-resistance material memory (VRMM) cell.