Patent ID: 8400381
Filing Date: 2013-03-19
Classification: G09G,H03K

Abstract:
1. An analog output buffer circuit comprising: a first transistor having a source coupled to a first node, a drain coupled to a second node, and a gate coupled to a third node; a second transistor coupled between the second node and the third node such that the first transistor is diode-coupled when the second transistor is on, the second transistor having a gate coupled to a first control line to receive a first control signal; a third transistor having a source coupled to a data line and configured to receive a data signal from the data line, a drain directly coupled to the first node, and a gate coupled to the first control line; a fourth transistor having a source coupled to the second node, a drain coupled to an output terminal, and a gate coupled to a second control line to receive a second control signal different from the first control signal; a fifth transistor having a source coupled to the first node, a drain coupled to a first power supply, and a gate coupled to the second control line; and a capacitor coupled between the third node and the first power supply and configured to receive the data signal through the first transistor.