Patent ID: 7030508
Filing Date: 2006-04-18
Classification: H01L,H05K,Y10S

Abstract:
1. A substrate for a semiconductor package comprising: an insulative layer having an approximately planar surface and a predetermined thickness; a die attachment region formed on the surface of the insulative layer; a plurality of electrically conductive patterns which are positioned on the surface of the insulative layer outward of the die attachment region, wherein each of the electrically conductive patterns includes a respective one of a plurality of bond fingers; a solder mask on the surface of the substrate, wherein the solder mask includes a plurality of openings, and an internal area of each of the bond fingers is individually exposed through a respective one of the openings; and at least one reference mark formed on the surface of the insulative layer outward of the die attachment region that allows for a state of a solder mask shift to be checked, the at least one reference mark comprising a reference pattern overlaid by one of the openings of the solder mask through which a subportion only of the reference pattern is exposed, the position of the respective opening relative to the underlying reference pattern determining the solder mask shift, wherein the reference pattern of the at least one reference mark is composed of a first region and a second region, which have a substantially oblong rectangular shape in a plan view and are connected at a substantially right angle; the solder mask opening of the at least one reference mark is also composed of a first region and a second region, which have a substantially oblong rectangular shape in a plan view and are connected at a substantially right angle; the first regions of the reference pattern and the solder mask opening cross each other perpendicularly near centers of the first regions of the reference pattern and the solder mask opening; and the second regions of the reference pattern and the solder mask opening also cross each other perpendicularly near centers of the second regions of the reference pattern and the solder mask opening.