Patent ID: 7486530
Filing Date: 2009-02-03
Classification: G06F,G11C

Abstract:
1. A memory device, comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of sense amplifiers coupled to the memory array; a data cache coupled to the plurality of sense amplifiers; and a data comparison circuit coupled between the data cache and the plurality of sense amplifiers, wherein the data comparison circuit contains a plurality of bit comparators, each of the plurality of bit comparators having an output directly coupled to a common error signal line, and where each bit comparator of the plurality of bit comparators is adapted to compare a first data value held in a sense amplifier of the plurality of sense amplifiers with a second data value held in the data cache and express a data match or data mismatch signal from an output of a bit comparator directly on the common error signal line, wherein the data comparison circuit further comprises: wherein each bit comparator further comprises: