Patent ID: 6251727
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A process for making self-aligned split-gate non-volatile memory cell, comprising the steps of:(a) forming a tunnel oxide layer, a poly-1 layer, and a nitride layer on a silicon substrate;(b) forming a nitride photoresist and using said nitride photoresist to etch said nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness region, wherein said low thickness region contains a first portion corresponding to an area intended to become floating gate and a second portion corresponding to an area intended to become cell drain;(c) forming a poly-1 photoresist and using said poly-1 photoresist to etch through said first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of said high thickness region adjacent to said first portion of said low thickness region is also etched to a reduced thickness;(d) poly-oxidizing said exposed poly-1 layer to form a poly-oxide layer;(e) forming a cell drain photoresist and using said cell drain photoresist to etch through said second portion of said low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch, wherein a portion of said high thickness region adjacent to said second portion of said low thickness region is also etched to a reduced thickness during said nitride etch;(f) performing drain implantation to form cell drain, followed by removing said nitride layer;(g) using the poly-oxide layer as a hard mask to etch said poly-1 layer;(h) forming a sidewall spacer on the sidewall of said poly-1 layer;(i) depositing a poly-2 layer covering said substrate;(j) forming a poly-2 photoresist and using said poly-2 photoresist to etch the poly-2 layer; and(k) forming a cell source photoresist and using said cell source photoresist to perform a cell source implantation.