Patent ID: 7555084
Filing Date: 2009-06-30
Classification: G01R

Abstract:
1. An apparatus comprising: a first digital synchronous system configured to be coupled to first clock signal having a first clock signal frequency and an input signal, and to provide a first output signal; a second digital synchronous system, substantially identical to said first digital synchronous system, wherein said second digital synchronous system is configured to receive a second clock signal having a second clock signal frequency, that is an integer fraction of the first clock signal frequency, and the input signal, and is configured to provide a second output signal; a third digital synchronous system, substantially identical to said first digital synchronous system, wherein said third digital synchronous system is configured to receive a third clock signal having a third clock signal frequency, that is substantially the same as the second clock signal frequency, and the input signal, is configured to provide a third output signal; and comparison and selection logic configured to be coupled to said first, second and third output signals to determine if a fault has occurred in the computation of said first output signal and configured to select a system output signal based on whether or not a fault has occurred.