Patent ID: 7574586
Filing Date: 2009-08-11
Classification: G06F

Abstract:
1. A system, comprising: a processor adapted to execute software code comprising branch instructions; and a trace logic coupled to the processor being operable to trace execution of a sequence of software instructions and adapted to generate a branch packet comprising a consecutives sequence of branch bits for representing whether corresponding branch instructions in the sequence of software instructions occurring between two trace synchronization points were taken or not taken, wherein an assigned branch bits in the consecutive sequence of branch bits is a valid branch bit having a value that indicates whether the corresponding branch instruction was taken or not taken and an unassigned branch but in the consecutive sequence of branch bits is an invalid branch bit; and wherein the trace logic further operable to store a selected value in one or more unassigned branch bits in the consecutive sequence of branch bits to indicate that the one or more unassigned branch bits are invalid when a trace synchronization point is issued before all branch bits in the branch packet are assigned, wherein the selected value indicating an invalid bit is selected to be a different value than a most significant valid branch bit; and port circuitry coupled to the trace logic being operable to output the branch packet to a test host processor.