Patent ID: 7054214
Filing Date: 2006-05-30
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory array including a plurality of memory cells for storing either one of first information and second information, the plurality of memory cells being arranged at points of intersection between a plurality of word lines and a plurality of data lines; a dummy memory array including a plurality of first dummy cells for storing the first information and a plurality of second dummy cells for storing the second information, the plurality of first and second dummy cells being coupled to a dummy data line; first and second switch circuits coupled to the plurality of data lines; and third and fourth switch circuits coupled to the dummy data line; wherein when the first or second information is written into at least one of the plurality of memory cells, the first and second switch circuits make a current path through the first and second switch circuits and one of the plurality of data lines, wherein when the first or second information is written into at least one of the plurality of first and second dummy cells, the third and fourth switch circuits make a current path through the third and fourth switch circuits and the dummy data line; and wherein each of said plurality of cells, said plurality of first dummy cells, and said plurality of second dummy cells has a magnetic tunnel junction element.