Patent ID: 6650582
Filing Date: 2003-11-18
Classification: G11C

Abstract:
A semiconductor memory device having a data bit width settable selectively to a first bit width and a second bit width wider than said first bit width, comprising:first data terminals of the first bit width used in both of a mode of said first bit width and a mode of said second bit width; first main data lines, having said first bit width, disposed corresponding to said first data terminals, a correspondence relationship between said first main data lines and said first data terminals being the same between the mode of said first bit width and the mode of said second bit width; one or more second data terminals, non-used in the mode of said first bit width, having a bit width equal to a difference between the first and second bit widths; and one or more second main data lines, disposed corresponding to said one or more second data terminals, having a bit width equal to a bit width of said one or more second data terminals.