Patent ID: 6300196
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of fabricating a gate over a substrate, which comprises a first dielectric layer having a first opening formed thereon, a gate dielectric layer formed in the first opening, a lower portion of a floating gate formed on the gate dielectric layer, a source/drain region formed in the substrate beside the lower portion of the floating gate, comprising:forming a first conductive layer on the first dielectric layer and on the lower portion of the floating gate to completely fill the first opening;patterning the first conductive layer to form a second opening in the first conductive layer, wherein the second opening is above the first opening and does not expose the first dielectric layer, and the second opening has a tapered sidewall and a predetermined depth;forming a mask layer to cover the first conductive layer and fill the second opening;removing the mask layer outside the second opening to expose the first conductive layer, wherein a portion of the mask layer is removed to leave a first etching mask layer in the second opening;performing a first anisotropic etching process using the first etching mask layer as a mask to etch the first conductive layer, wherein an upper portion of the floating gate is formed, and the first dielectric layer is exposed; andremoving the first etching mask layer.