Patent ID: 8487683
Filing Date: 2013-07-16
Classification: H03K

Abstract:
1. A circuit for generating multi-phase, non-overlapping clock signals from an input clock signal, comprising: a shift register that receives the input clock signal and generates first and second clock signals by dividing the input clock signal; first and second circuit modules connected to the shift register, wherein the first circuit module receives the first clock signal and a first feedback signal, and generates a first interim signal, and the second circuit module receives the second clock signal and a second feedback signal, and generates a second interim signal, wherein the first and second interim signals are non-overlapping by at least a predetermined minimum time difference; a multiplexer, connected to the first and second circuit modules, for receiving the first and second interim signals and generating an output signal; a first delay circuit, connected to the multiplexer, for receiving the output signal and generating a first delay signal by delaying the output signal by a first predetermined time; a second delay circuit, connected to the first delay circuit, for receiving the first delay signal and generating a second delay signal by delaying the first delay signal by a second predetermined time; a first de-multiplexer, connected to the second delay circuit, for receiving the second delay signal and generating the first and the second feedback signals; a second de-multiplexer, connected to the first delay circuit, for receiving the first delay signal and generating a first set of multi-phase, non-overlapping clock signals; and a frequency divider, connected between an output terminal of the first delay circuit and a select input of the first de-multiplexer, for generating a first de-multiplexer select signal.