Patent ID: 6353619
Filing Date: 2002-03-05
Classification: H04L

Abstract:
A circuit for an interconnect node in a packet-switching network, said circuit comprising:a processor; a first interface block comprising logic for interfacing said processor to other components within said circuit, said other components comprising: a second interface block comprising logic for interfacing said circuit to an external Ethernet interface and an external memory; a third interface block comprising logic for interfacing said circuit to an external DSL interface; a memory access block comprising logic for receiving packets of data from the external Ethernet interface and moving said data packets to the external memory, transmitting packets of data from the external memory to the external DSL interface, receiving packets of data from the external DSL interface and moving said data packets to the external memory, and transmitting packets of data from the external memory to the external Ethernet interface; and an internal memory block comprising memory and arbitration logic to prevent reading and writing to an address during a single clock cycle.