Patent ID: 8219964
Filing Date: 2012-07-10
Classification: G03F,H01L

Abstract:
1. A method of designing an electrical test pattern comprising the steps of: providing a chip design comprising a chip layout of a first layer of features to be printed; using a computer in identifying a critical site in said chip layout; identifying at least one electrical test feature of said chip layout adjacent said critical site, said at least one electrical test feature having at least one electrical characteristic that will be significantly modified if a printing failure occurs at said critical site; defining a region of influence (ROI) around said critical site such that printing of said critical site will not be influenced more than a predetermined critical site tolerance by the absence of features outside said ROI; defining at least one feed line electrically connected to said at least one electrical test feature to enable testing of said at least one electrical characteristic; defining a trim region outside of said ROI such that the absence any feature of said chip layout located outside of said trim region will not substantially, within a predetermined ROI tolerance, affect the printed dimensions of any feature within said ROI; and deleting all features, other than said at least one feed line and said at least one electrical test feature, located outside of said trim region to form a customized electrical test pattern.