Patent ID: 9111965
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor layer; forming a first mask of a charge storing material and a second mask of a charge storing material on the first insulating film, the first mask including a first portion, a second portion, and a third portion extending in a first direction from the first portion to the second portion and connecting the first portion and the second portion, the third portion having a width in a second direction perpendicular to the first direction, and the second mask having a width in a third direction that is wider than the width of the third portion in the second direction, the first mask and the second mask being formed of the same material; forming a first semiconductor region having a protruded shape and a second semiconductor region having a protruded shape on the semiconductor layer by patterning the first insulating film and the semiconductor layer using the first mask and the second mask, the first semiconductor region including a fourth portion, a fifth portion, and a sixth portion connecting the fourth portion and the fifth portion, and the second semiconductor region having a width in the third direction that is wider than a width of the sixth portion in the second direction; forming an element isolation insulating film between the first semiconductor region and the second semiconductor region; performing selective etching so that the third portion of the first mask is removed but the second mask is left by using an etching rate difference between the third portion of the first mask and the second mask; forming and patterning a second insulating film and a gate electrode material film, thereby forming a gate insulating film and a first gate electrode at least on a top surface of the sixth portion in the first semiconductor region, and forming a tunnel insulating film, a charge storage film, a block insulating film, and a second gate electrode on the second semiconductor region; and implanting an impurity into the first semiconductor region and the second semiconductor region using the first gate electrode and the second gate electrode as masks, thereby forming first source and drain regions in the fourth portion and the fifth portion of the first semiconductor region, and forming second source and drain regions in the second semiconductor region in a fourth direction perpendicular to the third direction.