Patent ID: 7290027
Filing Date: 2007-10-30
Classification: G06F

Abstract:
1. A microprocessor including an adder circuit for determining the sum of two operands, the adder comprising: a set of PGK circuits configured to generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands; at least one tier of group circuits configured to receive the propagate, generate, and kill bits from a plurality of the PGK circuits and to produce, in response thereto, a set of group propagate, generate, and kill values; a carry generation circuit configured to receive a carry-in bit and the outputs of at least one of the group circuits and further configured to generate a carry-out bit representing the carry-out of the corresponding group; and a select circuit configured to select between a first sum and a second sum responsive to the carry-out bit wherein at least one of the PGK circuits, group circuits, and carry circuits includes at least one complementary metal oxide semiconductor transmission gate; wherein the complementary metal oxide semiconductor transmission circuit comprises a PMOS transistor and an NMOS transistor, wherein a first source/drain terminal of the PMOS transistor is connected to a first source/drain terminal of the NMOS transistor and wherein a second source/drain terminal of the PMOS transistor is connected to a second source/drain terminal of the NMOS transistor; and wherein a gate terminal of the PMOS transistor is driven by a first signal and a gate terminal of the NMOS transistor is driven by the logical complement of the first signal.