Patent ID: 7057225
Filing Date: 2006-06-06
Classification: H01L,Y10T

Abstract:
1. An integrated circuit comprising: a semiconductor die; a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, each of the plurality of memory cells including at least one container-configured capacitor having a storage node including a roughened outer surface in a substantially vertical dimension with respect to the semiconductor die for storing electrical charge to define a logic level, each of the plurality of memory cells coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor; and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells; wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.