Patent ID: 6771096
Filing Date: 2004-08-03
Classification: G01R,H03D,H03L

Abstract:
A detector, comprising:a first input conductor coupled to a first latch and adapted to receive a reference clock signal; a second input conductor coupled to a second latch and adapted to receive a feedback clock signal; a first input conductor coupled to the second latch, wherein the first output conductor is adapted to receive a pump down signal that transitions to a logic high voltage if a leading edge of the feedback clock signal precedes a leading edge of the reference clock signal; a second output conductor coupled to the first latch, wherein the second output conductor is adapted to receive a pump up signal after the pump down signal is received by the first output conductor; a logic gate having no more than two inputs and one output, wherein the inputs of the logic gate are coupled to reset inputs of the first and second latches, wherein the output of the logic gate is coupled to reset inputs of the first and second latches, and wherein the logic gate is adapted to forestall transition of the pump down signal to a logic low voltage until after a transition of the pump up signal reaches a steady state logic high voltage value for each cycle of the reference clock signal; and a reset path extending between the output nodes and reset inputs of the first and second latches, wherein the reset path comprises no delay elements other than the logic gate.