Patent ID: 9111811
Filing Date: 2015-08-18
Classification: G09G,H01L

Abstract:
1. An analog memory cell circuit for a low temperature polycrystalline silicon thin film transistor liquid crystal display (LTPS TFT-LCD), the circuit comprises: a first transistor, the first transistor having a first jack of the first transistor, a second jack of the first transistor and a control jack of the first transistor; a second transistor, the second transistor having a first jack of the second transistor, a second jack of the second transistor and a control jack of the second transistor, the first jack of the second transistor being connected to a second power source; a third transistor, the third transistor having a first jack of the third transistor, a second jack of the third transistor and a control jack of the third transistor, the second jack of the third transistor being connected to a reference power source, the first jack of the third transistor being connected to the control jack of the first transistor, the control jack of the third transistor is connected to a third scan signal; a fourth transistor, the fourth transistor having a first jack of the fourth transistor, a second jack of the fourth transistor and a control jack of the fourth transistor, the first jack of the fourth transistor being connected to the control jack of the second transistor, the second jack of the fourth transistor being connected to the reference power source, the control jack of the fourth transistor being connected to the control jack of the third transistor, the control jack of the fourth transistor being connected to the third scan signal; a fifth transistor, the fifth transistor having a first jack of the fifth transistor, a second jack of the fifth transistor and a control jack of the fifth transistor, the first jack of the fifth transistor being connected to the second jack of the first transistor, the second jack of the fifth transistor being connected to a output jack, the control jack of the fifth transistor receiving the third scan signal; a sixth transistor, the sixth transistor having a first jack of the sixth transistor, a second jack of the sixth transistor and a control jack of the sixth transistor, the first jack of the sixth transistor being connected to the second jack of the sixth transistor, the second jack of the sixth transistor being connected to the output jack, the control jack of the sixth transistor receiving the third scan signal; a seventh transistor, the seventh transistor having a first jack of the seventh transistor, a second jack of the seventh transistor and a control jack of the seventh transistor, the control jack of the seventh transistor receiving a first scan signal, the first jack of the seventh transistor being connected to the first jack of the first transistor; and a eighth transistor, the eighth transistor having a first jack of the eighth transistor, a second jack of the eighth transistor and a control jack of the eighth transistor, the second jack of the eighth transistor being connected to the first jack of the first transistor, the first jack of the eighth transistor being connected to a first power source, the control jack of the eighth transistor being connected to a second scan signal; a ninth transistor, the ninth transistor having a first jack of the ninth transistor, a second jack of the ninth transistor and a control jack of the ninth transistor, the first jack of the ninth transistor is connected to an image data, the second jack of the ninth transistor is connected to the second jack of the first transistor and the first jack of the fifth transistor, the control jack of the ninth transistor receiving the first scan signal; a first capacitor, the first capacitor having a first jack of the first capacitor and a second jack of the first capacitor, the first jack of the first capacitor being connected to the control jack of the first transistor, the first jack of the third transistor and the second jack of the seventh transistor, the second jack of the first capacitor being connected to the first jack of the fourth transistor and the control jack of the second transistor; wherein, the first transistor, the fourth transistor, the sixth transistor, the seventh transistor and the ninth transistor comprise a N-type thin film transistor (NTFT), the second transistor, the third transistor, the fifth transistor, and the eighth transistor comprised a P-type thin film transistor (PTFT), the analog memory cell circuit having a plurality of operation periods, in the plurality of operation period, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor being controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal being output in an opposite to the output jack, wherein the analog memory cell circuit comprises a first operation period, a second operation period, a third operation period and a fourth operation period, in the first operation period, the first scan signal, the second scan signal and the third scan signal are set to turn the fourth transistor, the fifth transistor, the seventh transistor, the eighth transistor and the ninth transistor on, and turn the third transistor and the sixth transistor off, in the second operation period, the second scan signal is set to turn the seventh transistor off, in the third operation period, the first scan signal is set to turn the eighth transistor and the ninth transistor off, the second scan signal is set to turn the seventh transistor off, in the fourth operation period, the third scan signal is set to turn the fourth transistor, the fifth transistor off, and turn the third transistor on.