Patent ID: 9147680
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit, the method comprising: providing a bulk dielectric layer overlying a semiconductor substrate, the bulk dielectric layer having a first trench and a second trench; forming a gate dielectric layer in the first trench and the second trench; forming a first barrier layer overlying the gate dielectric layer; forming a work function material layer within the first trench and the second trench; recessing the work function material layer and the first barrier layer in the first trench and the second trench, wherein the work function material layer and the first barrier layer form a chamfered surface relative to and below the top planar surface of the bulk dielectric laver; recessing the gate dielectric layer in the first trench and the second trench; depositing a conductive gate electrode material such that it fills the first trench and the second trench; and recessing the conductive gate electrode material in the first trench and the second trench.