Patent ID: 6026505
Filing Date: 2000-02-15
Classification: G11C

Abstract:
An array built in self test (ABIST) system disposed on a single semiconductor chip comprising:a memory array having a plurality of column lines and a plurality of row lines and at least one redundant column line and at least one redundant row line with cells coupled to the lines at intersections thereof,first identifying means coupled to said memory array for identifying a given number of faulty cells along each of said column lines,first register means disposed on said semiconductor chip having a number of registers equal to the number of redundant column lines,second means coupled to said first identifying means for storing address signals of each of the column lines having said given number of faulty cells in said first register means, if a given number of faulty cells in one of the column lines is identified,third identifying means coupled to said memory array for identifying a faulty cell along each of said row lines while masking the faulty cells having address signals of said column lines stored in said first register means,second register means disposed on said semiconductor chip having a number of registers equal to the number of redundant row lines,fourth means coupled to said third identifying means for storing address signals of each of the row lines having a faulty cell in said second register means,fifth means coupled to said second register means for producing a given signal indicating that said second register means is filled to capacity,sixth means responsive to said given signal for storing column line address signals of a faulty cell identified by said third identifying means in said first register means, if said first register means is not full, andmeans coupled to said first and second register means for substituting said redundant column and row lines for the column and row lines having address signals stored in said first and second register means.