Patent ID: 9018694
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. An integrated circuit device having a plurality of multi-gate structures, comprising: a plurality of first gates for a plurality of multi-gate structures for an integrated circuit device; and a plurality of second gates for the plurality of multi-gate structures; wherein the plurality of multi-gate structures comprise at least one hundred or more multi-gate structures; wherein overall gate lengths for the plurality of multi-gate structures vary by 10 percent or less; wherein the multi-gate structures comprise multi-gate structures for multi-gate non-volatile memory (NVM) cells; wherein the multi-gate NVM cells comprise split-gate NVM cells and each of the multi-gate structures comprises a select gate and a control gate; wherein the overall gate lengths comprise combined gate lengths for the select gates and the control gates without including any gate overlaps; wherein the overall gate length of the select gate and the control gate for each NVM cell is 280 to 320 nanometers; and wherein an overlap of the control gate and the select gate for each NVM cell is 40 to 60 nanometers.