Patent ID: 6349398
Filing Date: 2002-02-19
Classification: G01R

Abstract:
A self-testing procedure for a logic part having a first portion of core logic testable using a first self-testing procedure and having a second portion of core logic testable using a second self-testing procedure and not testable using the first self-testing procedure, said procedure comprising the steps of:initializing the first portion of core logic part with a first test value; initializing the second portion of core logic part with a first test value; executing the test using the first self-testing procedure on the first portion and using the second self-testing procedure on the second portion; summing the test results from the first portion of core logic and the second portion of core logic such that test results are kept in the chip logic and become new test operands in succeeding clocks; and checking the output of the summer to determine whether the logic part is good.