Patent ID: 8298882
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A method for fabricating a circuit structure, comprising: defining portions for NFET devices and for PFET devices on a Si principal surface of a substrate; depositing onto said portions a SiGe layer using blanket epitaxial growth; blanket disposing a first sequence of layers over said SiGe layer, wherein said first sequence of layers has one layer in direct contact with said SiGe layer and said one layer in direct contact with said SiGe layer is of a dielectric material, wherein said first sequence of layers comprise a first high-k dielectric and a first metal; incorporating said first sequence of layers into both said NFET devices and said PFET devices, wherein said first high-k dielectric is being included into first gate dielectrics and said first metal is being included into first gatestacks; for said NFET devices but not for said PFET devices, removing said first gatestack, said first gate dielectric, and removing said SiGe layer from regions that were directly thereunder said first gate dielectrics; and deploying a second sequence of layers comprising a second high-k dielectric and a second metal, wherein for said NFET devices forming a second gate dielectric and a second gatestack.