Patent ID: 9030029
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A chip package comprising: a substrate having a first surface at a first height and a second surface at a second height, said first height different from said second height, said substrate having opposing sidewalls between said first surface and said second surface of said substrate, in which said opposing sidewalls and said first surface of said substrate define an opening in said substrate; only one singulated die positioned in said opening in said substrate, said singulated die having a first surface opposite said first surface of said substrate and a second surface opposite said first surface of said singulated die; an adhesive material joining said first surface of said substrate and said second surface of said only one die, wherein said adhesive material comprises an adhesive tape joining said first surface of said substrate and said second surface of said only one die; a first insulating layer coupled to said only one die, coupled to said substrate and across an edge of said only one die, wherein said first insulating layer comprises a first portion vertically over said only one die and a second portion not vertically over said only one die, wherein said first insulating layer is not integrated with said adhesive material; a patterned circuit layer over said first insulating layer, said first horizontal level, said only one die and said substrate and across said edge, wherein said patterned circuit layer is connected to said only one die through a first opening in said first insulating layer; a passive device over said first horizontal level and said first insulating layer, wherein said passive device comprises an inductor; and a second insulating layer over said passive device.