Patent ID: 6858500
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device comprising at least one trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench, a first drain region positioned under a bottom surface of the trench, first source regions positioned on both sides of the trench, an extended drain region positioned between the first drain region and the first source regions, a first drain electrode connected electrically to the first drain region, and first source electrodes connected electrically to the respective first source regions, and at least one planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate, a second drain region and a second source region that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode, a second drain electrode connected electrically to the second drain region, and a second source electrode connected electrically to the second source region, the manufacturing method comprising: forming the trench in the semiconductor substrate; forming the extended drain region; forming the first gate oxide film and the second gate oxide film; forming first gate electrodes and the second gate electrode; forming the first drain region, first source regions, the second drain region, and the second source region; laying an interlayer insulating film over the surface of the semiconductor substrate; etching the interlayer insulating film to expose the first drain region under the bottom surface of the trench; filling the inside of the trench with a polysilicon layer that is in contact with the first drain region; laying a passivation film over the surface of the semiconductor substrate; etching the passivation film and the interlayer insulating film to expose the polysilicon layer, the first source regions, the second drain region, and the second source region; and laying a metal layer on the passivation film and patterning the metal layer to form the first drain electrode, first source electrodes, the second drain electrode, and the second source electrode that are in contact with the polysilicon layer, the first source regions, the second drain region, and the second source region, respectively.