Patent ID: 6995554
Filing Date: 2006-02-07
Classification: H03L

Abstract:
1. A delay-locked loop (DLL) of an integrated circuit (IC) comprising: a selector having a reference clock input, a test clock input and an output, the selector being configured to select between the reference clock input and the test clock input and to provide the selected input on the selector output, a reference clock being delivered to the reference clock input and a test clock being delivered to the test clock input, the test clock being generated external to the IC; a phase comparator having a first input and a second input, the first input of the phase comparator receiving the selector output, the second input of the phase comparator receiving a feedback clock, wherein when the reference clock input of the selector is selected, the phase comparator compares a phase of the feedback clock with a phase of the reference clock to determine a phase difference between the phase of the reference clock and the phase of the feedback clock, and wherein when the test clock input of the selector is selected, the phase comparator compares a phase of the test clock with the phase of the feedback clock to determine a phase difference between the phase of the test clock and the phase of the reference clock; and a variable delay element, the variable delay element receiving the reference clock and the phase difference determined by the phase comparator as inputs, the variable delay element delays the reference clock by an amount that depends on the determined phase difference.