Patent ID: 6542963
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A method of performing arithmetic operation using a cache structure having a TAG register and a cache data memory, the method comprising the steps of:storing in the TAG register a plurality of known operands, each having a corresponding resultant derived from an arithmetic operation, the resultant being stored in a corresponding location in the cache data memory; inputting a new operand on which the arithmetic operation is to be performed to the TAG register; comparing the new operand to the plurality of the known operands; determining if the new operand matches any of the known operands and if there is a match, outputting from the cache data memory the known resultant corresponding to the known operand that matched the new operand; if there is no match in the determining step, determining if there are partial matches between the known operands and the new operand; selecting the known operand having the MSBs matching the MSBs of the new operand; accessing from the cache data memory the resultant corresponding to the known operand having the most matched MSBs; determining a first portion of the accessed resultant derived from the matched MSBs of the known operand; masking a second portion of the accessed resultant which is other than the first portion; and providing as a first partial resultant the masked resultant.