Patent ID: 6643762
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A computer system for processing instructions of a computer program, comprising:a plurality of registers; a plurality of connections corresponding respectively with said registers; at least one pipeline configured to process and execute said instructions; a scoreboard coupled to said plurality of connections and to said at least one pipeline, said scoreboard having a plurality of bits corresponding respectively with said plurality of registers, said scoreboard configured to transmit each of said bits across a different one of said connections, each of said bits indicative of whether a pending write to a corresponding one of said registers exists; decoding circuitry configured to decode at least one encoded register identifier associated with at least one of said instructions into a decoded register identifier, said decoded register identifier having a plurality of bits corresponding respectively with said plurality of registers and identifying at least one of said registers; and hazard detection circuitry coupled to each of said plurality of connections, said hazard detection circuitry configured to compare each of said transmitted bits to a respective one of said bits of said decoded register identifier and to detect data hazards based on comparisons of said transmitted bits to said decoded register identifier bits, wherein said decoding circuitry comprises a decoder configured to receive, from said at least one pipeline, said encoded register identifier and to decode said encoded register identifier into said decoded register identifier, said decoder further configured to transmit said decoded register identifier to said hazard detection circuitry and to said scoreboard.