Patent ID: 9160360
Filing Date: 2015-10-13
Classification: H03M

Abstract:
1. A multiplying digital-to-analog converter, generating an analog output in accordance with digital input bits, comprising: an operational amplifier; and a first switched-capacitor network and a second switched capacitor network sharing the operational amplifier, wherein: the first switched-capacitor network samples an analog signal when the first switched-capacitor network is disconnected from the operational amplifier; the first switched-capacitor network is coupled to the operational amplifier for sampled signal amplification based on the digital input bits when the second switched-capacitor network is disconnected from the operational amplifier; the second switched-capacitor network samples the analog signal when the second switched-capacitor network is disconnected from the operational amplifier; the second switched-capacitor network is coupled to the operational amplifier for sampled signal amplification based on the digital input bits when the first switched-capacitor network is disconnected from the operational amplifier; the operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier; and the operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier.