Patent ID: 6847228
Filing Date: 2005-01-25
Classification: G06F,H03K

Abstract:
1. A configurable logic block (CLB) slice comprising: a first function generator having a first set of input terminals; a first multiplexer having a plurality of input terminals coupled to a plurality of the first set of input terminals; a second function generator having a second set of input terminals; a second multiplexer having a plurality of input terminals coupled to a plurality of the second set of input terminals; a carry input terminal for receiving a carry input signal from outside of the CLB slice; a carry output terminal for providing a carry output signal, which is propagated out of the CLB slice; a third multiplexer configured to receive more than two input signals, including the carry input signal, a first input signal from the first multiplexer, and a second input signal from the second multiplexer, the third multiplexer having an output terminal coupled to the carry output terminal; and a decoder circuit configured to receive a plurality of control signals within the CLB slice, and in response, generate a plurality of routing control signals for controlling the configuration of the third multiplexer, wherein the third multiplexer provides the only path between the carry input terminal and the carry output terminal.