Patent ID: 8094590
Filing Date: 2012-01-10
Classification: G06F,H04L,Y04S

Abstract:
1. A cross link multiplexer bus, comprising: a plurality of multiplexers; and a plurality of interconnects coupled between adjacent pairs of multiplexers from among the plurality of multiplexers; wherein a first multiplexer from among the plurality of multiplexers is configured to convey a signal toward a second multiplexer from among the plurality of multiplexers in a first direction by a first set of interconnects from among the plurality of interconnects coupled to a third multiplexer from among the plurality of multiplexers and the first multiplexer is configured to convey the signal toward the second multiplexer in a second direction by a second set of interconnects from among the plurality of interconnects coupled other than to the third multiplexer; wherein the plurality of multiplexers are configured to delay conveyance of a first bit of the signal by a gate delay time; wherein the plurality of interconnects are configured to delay conveyance of a second bit of the signal by a path delay time; and wherein the gate delay time and the path delay time are set so that the first bit remains substantially synchronized with the second bit.