Patent ID: 8946856
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. An integrated circuit device, comprising: a silicon substrate; analog circuitry formed on the silicon substrate; a digital core formed on the silicon substrate separate from the analog circuitry, the digital core including at least one area of active digital circuitry; one or more decoupling cell rows formed on the silicon substrate within the at least one area of active digital circuitry, each of the one or more decoupling cell rows including at least one p-type doped well or n-type doped well; one or more metal-oxide-semiconductor (MOS) decoupling capacitors formed within the at least one p-type doped well or n-type doped well of each of the one or more decoupling cell rows; multiple standard cell rows formed on the silicon substrate within the digital core and oriented in a parallel relationship to the one or more decoupling cell rows such that one or more of the decoupling cell rows are disposed between adjacent rows of the multiple standard cell rows, each of the multiple standard cell rows including a p-type doped well and an n-type doped well; and where the at least one p-type doped well or n-type doped well of each of the one or more decoupling cell rows extends across an entire height of the decoupling cell row and into each of the adjacent row of the multiple standard cell rows such that the p-type doped well or n-type doped well of the decoupling cell row also forms the p-type doped well or n-type doped well of each of the adjacent standard cell rows.