Patent ID: 6104223
Filing Date: 2000-08-15
Classification: H03H

Abstract:
An apparatus for phase shifting a periodic reference signal T.sub.0 to produce an output signal T.sub.OUT with a phase shift that is a function of a value of input first control data N, wherein said function is adjustably determined by input function control data, the apparatus comprising:a programmable phase shifter for phase shifting said periodic reference signal T.sub.0 with a phase shift controlled by a value of second control data (F,G) provided as input thereto, thereby to produce T.sub.OUT ; anda programmable data converter, receiving said first control data N and said function control data, for providing said second control data (F,G) to said programmable phase shifter, wherein a value of said second control data (F,G) is an adjustable function of said value of said first control data N, said function being adjusted in accordance with said function control data,wherein said programmable phase shifter comprises:a tapped delay line for receiving and delaying said periodic reference signal T.sub.0 to produce a plurality of tap signals TAP each delayed from T.sub.0 by a differing amount,a multiplexer for receiving said tap signals TAP, selecting in response to a first portion F of said second control data (F,G) one of said TAP signals and providing it as an output selected tap signal T.sub.S, anda programmable delay circuit for receiving and delaying said selected tap signal T.sub.S with a delay time determined by a second portion G of said second control data (F,G) to produce said output signal T.sub.OUT,wherein said programmable data converter comprises:a random access memory addressed by a first portion NH of said first control data N for storing delay correction data B and for reading out stored delay correction data B when addressed by said first portion NH of said first control data N,means for delivering said first portion NH of said first control data N to said multiplexer as said first portion F of said second control data (F,G),scaling means for receiving a second portion NL of said first control data N and for producing output delay control data wherein said delay control data A is proportionately larger than said second portion NL of said first control data N, andan adder for adding said delay control data A produced by said scaling means to delay correction data B read out of said random access memory to produce said second portion G of said second control data (F,G).