Patent ID: 7149135
Filing Date: 2006-12-12
Classification: G11C

Abstract:
1. A multi chip package type memory system comprising: a plurality of volatile memory chips, each of which including a volatile memory cell region configured to store a data and a redundant memory cell region configured to be used to replace a defect in the volatile memory cell region, the redundant memory cell region including a redundant memory cell, a non-volatile memory chip including a non-volatile memory cell region, the non-volatile memory chip configured to output a first redundant information that is an information based on whether the volatile memory cell region has the defect in the volatile memory chip or not, and an internal line commonly connected to the plurality of volatile memory chips and the non-volatile memory chip, the internal line configured to transmit the first redundant information from the non-volatile memory chip to the plurality of volatile memory chips, the first redundant information including 1) a chip select/release information that indicates which the plurality of volatile memory chips should be selected, 2) a defect address information that indicates an address of a defect memory cell to be replaced, and 3) a redundant address information that indicates an address of the redundant memory cell to replace the defect memory cell, and the internal line configured to transmit at least one of a data, an address signal, and a control signal from/to an outside circuit.