Patent ID: 6384772
Filing Date: 2002-05-07
Classification: G01S,H03L

Abstract:
A circuit for phase locking a frequency offset between a first oscillator (400) and a second oscillator (402) with a desired offset signal from a reference oscillator 404, the circuit comprising:a first mixer (410) having a first input coupled to an output of the first oscillator (400), a second input coupled to an output of the second oscillator (402), and having an output; a first phase shifter (414) having an input coupled to the output of the second oscillator (402), and having an output; a second mixer (408) having a first input coupled to the output of the first oscillator (400), a second input coupled to the output of the first phase shifter (414), and having an output; a first filter (420) having an input coupled to the output of the first mixer (410), and having an output; a second filter (418) having an input coupled to the output of the second mixer (408), and having an output; a first multiplier (422) having a first input coupled to the output of the second filter (418), a second input coupled to an output of the reference oscillator (404), and having an output; a second phase shifter (426) having a first input coupled to the output of the reference oscillator (404), and having an output; a second multiplier (424) having a first input coupled to the output of the first filter (420), a second input coupled to the output of the second phase shifter (426), and having an output; and a subtractor (428) having a first input coupled to the output of the first multiplier (422), a second input coupled to the output of the second multiplier (424), and having an output coupled to a frequency control input of the second oscillator (402), the output of the subtractor providing a signal composed of a signal from the output of the first multiplier (422) subtracted from a signal from the output of the second multiplier (424).