Patent ID: 6727179
Filing Date: 2004-04-27
Classification: H01L,Y10S

Abstract:
A process for creating an integrated circuit stage including patterns, in which a first group of the patterns have widths above a threshold and a second group of the patterns have widths below the threshold, comprising:depositing a layer of pattern material on a substrate, depositing a first mask on the layer of pattern material, then depositing an upper layer on the first mask, depositing a first resin which is exposed and developed subsisting only on first patterns still to be formed; etching the upper layer where the upper layer is visible; removing the first resin; depositing a second resin, which is exposed and developed subsisting on second patterns still to be formed; etching the first mask where the first mask is visible; etching the layer of pattern material, thus forming the first and second patterns, where the layer of pattern material is visible; removing the second resin; etching the first mask where the first mask is visible after etching the upper layer; depositing a second mask after removing the first resin; and etching the second mask where the second mask is visible after depositing, exposing, and developing the second resin.