Patent ID: 8278717
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device, the method comprising: forming isolation layers on a surface of a semiconductor substrate to separate the substrate into active areas, the isolation layers and the active areas being arranged along a predetermined direction parallel to the surface of the semiconductor substrate; forming diffusion layers on surfaces of the active areas; forming a stress liner on upper surfaces of the diffusion layers, the stress liner being formed of a material having a lattice constant smaller than a lattice constant of a material forming the semiconductor substrate; forming gate structures of cell transistors and of first and second select transistors arranged to sandwich the cell transistors, on the semiconductor substrate before the stress liner is formed; burying insulators between the cell transistors and between the cell transistors and the select transistors before the stress liner is formed, a compression stress of the insulators to the material forming the substrate being smaller than a compression stress of the stress liner to the material forming the substrate; and annealing the diffusion layers after the stress liner is formed.