Patent ID: 6172530
Filing Date: 2001-01-09
Classification: G11C

Abstract:
A decoder for generating N output signals, the decoder comprising:a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals, in a precharge phase said precharged gate structure being arranged to output said N intermediate signals at a first logic value, and in an evaluate phase said precharged gate structure being arranged to maintain a first intermediate signal at said first logic value, and to cause all other intermediate signals to transition to a second logic value;self-timed logic for receiving the N intermediate signals, and for generating said N output signals, the self-timed logic being arranged, during said precharge phase, to generate said N output signals at said second logic value, and during said evaluate phase to cause a first output signal corresponding to said first intermediate signal to transition to said first logic value;said self-timed logic being arranged to generate each output signal from the corresponding intermediate signal as qualified by a predetermined other intermediate signal, such that the transition of said first output signal to said first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to said second logic value.