Patent ID: 8830766
Filing Date: 2014-09-09
Classification: G11C

Abstract:
1. A circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset, comprising: a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell; a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal; a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal; and a push-pull logic formed by a NMOS and a PMOS in series to generate an output of the circuit, wherein, in a read cycle, with an initial state of the global sense amplifier enable signal LOW, the transition detect signal HIGH and the first and inverted output signals LOW, the first PMOS driver pulls the inverted output signal HIGH, and a cross-coupled NMOS device maintains the first output signal LOW, wherein the read detect detects the transition of the inverted output to the HIGH state that drives the transition detect signal LOW and in turn drives the sense amplifier OFF and then precharges the internal nodes of the sense amplifier and the bitlines for the next read cycle.