Patent ID: 6510486
Filing Date: 2003-01-21
Classification: G06F,G11C

Abstract:
A circuit for reading and writing data to a number of memories comprising:a plurality of receiving devices each receiving: (i) one or more fixed width digital words and (ii) a write timing signal, at least one of said plurality of receiving devices presenting an output in an order defined by said write timing signal; first counter circuit configured to provide said write timing signal changing to a different value on each cycle of a first clock; a plurality of memory devices for storing information, wherein each of said memory devices is configured to (i) receive an input from said plurality of receiving devices in an order defined by said write timing signal and (ii) present an output in an order defined by a read timing signal; second counter circuit configured to provide for said read timing signal changing to a different value on each cycle of a second clock input; and a plurality of output devices receiving said memory device outputs and said read timing signal, at least one of said output devices forms a multiple-width word by presenting one of said output(s) of said receiving devices when said read timing signal is present.