Patent ID: 6862702
Filing Date: 2005-03-01
Classification: G11C

Abstract:
1. An address counter in combination with a test unit for addressing and f or testing synchronous high-frequency digital circuits, for generating column and row addresses at an operating frequency of the digital circuit, the address counter comprising: a number n of offset registers for storing n address offset values, said off set registers each having an output; a selection and combination circuit connected to said outputs of said offset registers and serving for controllable selection of the address offset values stored in said offset registers and generation of high-frequency output addresses for the digital circuit to be tested; and a control circuit connected to and controlling said selection and combination circuit, said control circuit receiving a number m of low-frequency input signals from the test unit and generating therefrom n high-frequency control signals for driving said selection and combination circuit to select in correspondence to said m low-frequency input signals the address offset values as output addresses from said offset registers, the address counter generating said output addresses with a high frequency determined by a ratio of the number m of said input signals to the number n of said control signals required for selection of said offset registers.