Patent ID: 6021478
Filing Date: 2000-02-01
Classification: G11C

Abstract:
A method of operating a microprocessor and memory, including the steps of:coupling the microprocessor to the memory using a bus, the memory including a memory address counter;initiating communication between the microprocessor and the memory;determining a first condition of address phase enable and determining a second condition of output enable activated;if both said first condition and said second condition are met, then initiating a burst of memory transfer from the memory to the microprocessor;establishing a plurality of system clock cycles;consecutively activating the condition of output enable for more than one system clock cycle;having a burst sequence wherein the memory continues to read and latch data on the bus by advancing to the next address in the memory address counter until the burst sequence is suspended or terminated;suspending said burst sequence when the output enable is deactivated and a next address phase has not been requested from the microprocessor until the condition of output enable is reactivated; andterminating said burst sequence when the microprocessor desires another address phase, said another address phase being indicated by a chip enable signal.