Patent ID: 7309977
Filing Date: 2007-12-18
Classification: H02M,Y02B

Abstract:
1. A method for adaptively compensating for the offset and delay of a comparator in a switching regulator to thereby achieve a more optimal on/off timing of a synchronous switch that is controlled by the comparator in a feedback control loop, the method comprising the Steps of: sampling at least one a node in the output of the switching regulator and generating at least one sampled error signal; at least in part based on said sampled error signal value, determining if the current comparator offset is too high or too low relative to a target switching regulator output value; at least in part based on said offset determination, accordingly generating a compensated feedback error signal that is based at least in part on the sampled error signal; and applying said compensated feedback error signal to an input of the comparator to have the effect of a comparator offset adjustment signal, wherein said compensated feedback error signal is operable as a feedback input to the comparator to result in more optimal timing of the on and off times of the synchronous switch to improve convergence towards the target switching regulator output value and thereby lower the next sampled error signal value.