Patent ID: 6140949
Filing Date: 2000-10-31
Classification: H03M

Abstract:
A method for trimming a pipelined gain stage in a pipeline analog-to-digital converter, comprising the steps of:providing a gain tuning element for the gain stage to allow the gain thereof to be trimmed in accordance with an input trim value;measuring the integrated non-linearity (INL) of the analog-to-digital converter by sweeping the input thereof between two predetermined values such that at least one comparator transition in the gain stage occurs;measuring the magnitude of the at least one INL transition in the measured INL, which transition corresponds to the comparator transition, and which magnitude has a predetermined relationship to the gain error of the gain stage;determining the gain error of the gain stage from both the measured INL transition and the predetermined relationship between the magnitude of the measured INL transition and the associated gain error; andtrimming the gain of the gain stage with the gain tuning element by generating the input trim value therefor corresponding to the determined gain error.