Patent ID: 7372098
Filing Date: 2008-05-13
Classification: G11C,H01L

Abstract:
1. A floating gate transistor comprising: source and drain regions located in a transistor body region, the source and drain regions are laterally spaced apart to form a channel therebetween; a floating gate electrically isolated from and located vertically above the channel; a control gate isolated from and located vertically above the floating gate; and a bi-polar junction located in the transistor body comprising a base region having a doping level higher than a doping level of the transistor body and an oppositely doped emitter region disposed below the base region, to form a vertical electric field during a write operation in response to at least one of a negative bias applied to the emitter region and a reference bias applied to the base region, such that electrons are accelerated in the vertical electric field and injected onto the floating gate.