Patent ID: 6124817
Filing Date: 2000-09-26
Classification: H03M

Abstract:
A DAC with noise equalized, placed between a voltage source and ground, driven by a bias device, receiving digital signals and a BLANK signal, comprising:a thermal code decoder, processing with said digital signals and said BLANK signal, having a plurality of outputs;a plurality of D-type flip-flops, processing said plurality outputs of said thermal code decoder;a plurality of preprocessors, each receiving the output of one corresponding D-type flip-flop and outputing a signal and an inverted signal of said signal; anda plurality of current sources, each receiving corresponding said signal and said inverted signal, each current source comprising:a first PMOS transistor, having a source connected to said voltage source, a gate connected to said bias device, and a drain;a second PMOS transistor, having a source connected to said drain of said first PMOS transistor, a gate receiving said signal, and a drain;a third PMOS transistor, having a source connected to said drain of said first PMOS transistor, a gate receiving said inverted signal, and a drain connected to said ground; anda fourth PMQS transistor, having a source connected to said drain of said second PMOS transistor, a gate receiving said BLANK signal, a drain acting as the output of said DAC when said BLANK is high and said third PMOS transistor is off.