Patent ID: 7101766
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device comprising: forming a vertical gate pattern on a semiconductor substrate; sequentially forming an insulating layer and a sacrificial layer on the semiconductor substrate having the vertical gate pattern, the sacrificial layer being formed of a material having an etch selectivity with respect to the insulating layer; etching the sacrificial layer to form a sacrificial spacer; etching the insulating layer until at least an upper surface of the vertical gate pattern is exposed, to form an L-shaped spacer, the L-shaped spacer including a vertical portion located between sidewalls of the vertical gate pattern and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer; selectively etching a part of the vertical portion of the L-shaped spacer, to form an empty space between upper sidewalls of the vertical gate pattern and the sacrificial spacer; forming a horizontal gate pattern formed of a conductive layer to fill at least the empty space, to provide a T-shaped gate composed of the vertical gate pattern and the horizontal gate pattern; and removing the sacrificial spacer.