Patent ID: 7873926
Filing Date: 2011-01-18
Classification: G06F

Abstract:
1. A method for analyzing timing of an integrated circuit using a static statistical timing analysis (SSTA) tool, the method comprising: computing a timing graph from a netlist using the SSTA tool, the timing graph having a plurality of nodes and a plurality of edges connecting the nodes; in response to forward propagating a first set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool an arrival time of the first set of probabilistic distributions at each of the nodes; in response to backward propagating a second set of probabilistic distributions in the timing graph, statistically calculating with the SSTA tool a required arrival time of the second set of probabilistic distributions at each of the nodes; identifying with the SSTA tool a statistically worst slack for a node in the timing graph from the arrival times and the required arrival times either through a slack calculation based upon the arrival times and the required arrival times or through required arrival time calculations; determining one or more of the slacks of the edges arriving at the node in the timing graph with a parameter sensitivity that exceeds a user-defined limit; equating a proxy worst slack to the slack of the edge that produces a worst projected slack: and generating a timing report with the SSTA tool that replaces the statistically worst slack with the proxy worst slack for at least one of the edges arriving at the node in the timing graph at which the statistically worst slack is identified during backward propagation.