Patent ID: 6295721
Filing Date: 2001-10-02
Classification: H01L,Y10T

Abstract:
A process for forming a fuse structure, comprising:providing a partially completed integrated circuit having a first dielectric upper surface in which are embedded, and exposed, first and second dual damascene connectors, each having a width and each having an inner edge and an outer edge, said inner edges being separated by a gap having a length;depositing a layer of chromium on said upper surface, including the exposed dual damascene connectors;depositing a layer of aluminum over the layer of chromium;patterning and etching the aluminum and chromium layers to form a fusible stripe, having said width, that extends no further than said outer edges and that overlaps the first inner edge by a first amount and the second inner edge by a second amount that may be different from the first amount, thereby controlling conductance of heat between the stripe and said first and second dual damascene connectors; anddepositing a second dielectric layer over the first dielectric surface, including said stripe.