Patent ID: 6097661
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A pointer circuit with a predetermined number of outputs and for selecting one output such that the one output alone is in a determined one logical state of two logically distinguishable states, while all other outputs are in the other logical state and are not selected, and for changing the one logical state from the one output to an output immediately adjacent to this output in response to inputting a clock signal, so that after this change the immediately adjacent output is in the one logical state and is the selected output, while all other outputs, are in the other logical state and are not selected, comprising:a plurality of static memories, each of said static memories having first and second memory terminals, the plurality of static memories being respectively associated with the number of outputs, each of said memories respectively having the first and second memory terminals complementary to one another, such that the terminals are always in first and second stored logical states that are different from one another;a respective static memory of said plurality of static memories having a predetermined memory terminal connected with a respective output that is associated with the respective static memory;a shift circuit connected with the predetermined memory terminal of each memory for producing a logical state at the predetermined memory terminal of a memory and for changing the logical state from the predetermined memory terminal of a first memory to a predetermined memory terminal of a second memory immediately adjacent to the first memory by inputting at least one clock signal, which simultaneously effect the change such that the predetermined memory terminal of one respective memory is in one of the first and second logical states, and such that the predetermined memory terminals of all other memories are in the other of the first and second logical states.