Patent ID: 7892906
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method for making a fully silicided gate electrode of a NMOS transistor and a fully silicided gate electrode of a PMOS transistor on a semiconductor wafer, comprising: forming said NMOS transistor and said PMOS transistor on said semiconductor wafer, said NMOS transistor and said PMOS transistor having an undoped polysilicon gate electrode and a hardmask over said undoped polysilicon gate electrode; forming a layer of insulating material over said semiconductor wafer; removing said hardmasks and a portion of said layer of insulating material; forming a layer of silicidation metal over said semiconductor wafer; performing a first silicide anneal to change said undoped polysilicon gate electrodes into partially silicided gate electrodes; removing unreacted portions of said silicidation metal layer; forming a first patterned photoresist layer to protect said partially silicided gate electrode of said NMOS transistor; implanting dopants of a first type into said partially silicided gate electrode of said PMOS transistor; removing said first patterned photoresist layer; forming a second patterned photoresist layer to protect said partially silicided gate electrode of said PMOS transistor; implanting dopants of a second type into said partially silicided gate electrode of said NMOS transistor; removing said second patterned photoresist layer; and performing a second silicide anneal to change said doped partially silicided gate electrodes into fully silicided gate electrodes.