Patent ID: 6950909
Filing Date: 2005-09-27
Classification: G06F

Abstract:
1. In a data processing system comprising a multi-sectored cache having sectored arrays of cache lines and associated cache directories and a cache controller that includes a plurality of queues for write access to cache lines within sectored arrays, a system for serializing overlapping write access to said arrays to enable accurate directory updates, said system comprising logic for: issuing a write access request from a first queue for access to a first block of a cache line; asserting a last in line signal identifying said first queue as a last sequential queue to request access to said cache line; determining whether a second queue has an outstanding write access request for a second block of said cache line; responsive to a determination that there are no outstanding write access requests for said cache line, proceeding with a write to said cache line and a corresponding entry of the associated cache directory utilizing current directory information; and responsive to a determination that the second queue has an outstanding write access requests for said cache line: