Patent ID: 6078078
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A transistor, comprising:a substrate having an active area and a channel in the active area having a substantially flat bottom and upwardly sloping walls;a gate dielectric layer positioned in the channel and having a bottom portion having a first thickness, a first leg projecting obliquely upwardly from the bottom portion and having a second thickness, a second leg protecting obliquely upwardly from the bottom portion and having a third thickness, the second and third thicknesses being larger than the first thickness, the bottom portion and the first and second legs defining a V-shaped cross-section;a gate electrode positioned on the gate dielectric layer;a first source/drain region positioned in the substrate; anda second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer.