Patent ID: 6072727
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A dynamic sense amplifier, particularly for semiconductor memory devices of the EPROM, EEPROM and Flash-EEPROM types, which comprises:a virtual ground sense circuit having a pair of input nodes and a pair of output nodes;an equilibration device structured to accept an equilibration signal and equalize voltages at said output nodes in response to the equilibration signal;respective reference and matrix circuit legs associated with said output nodes and coupled to the respective input nodes of the virtual ground sense circuit; anda clamping circuit structured to alternately couple the reference and matrix circuit legs to a ground voltage or to couple the reference and matrix circuit legs, respectively, to a reference and a memory cell, in response to a clamp signal;wherein said clamp signal is changed prior to the equilibration signal being changed such that the virtual ground sense circuit is coupled to the reference and to the memory cell at its input nodes for a period of time while the output nodes are equalized.