Patent ID: 7516171
Filing Date: 2009-04-07
Classification: G06F

Abstract:
1. An arithmetic unit comprising: a memory for storing data; an arithmetic logic unit for executing a predetermined arithmetic operation with respect to the data from the memory to provide first output data, the data being grouped into one of several patterns; a register for temporarily storing the data read from the memory, and providing the temporarily stored data as second output data; and a combining circuit for receiving the first output data from the arithmetic logic unit and the second output data from the register, and outputting combined data which is provided by replacing a part of the second output data with a part of the first output data based on the pattern of the data from the memory, wherein when the part of the second output data is replaced with the part of the first output data, the combining circuit shifts a position of data to be replaced in the second output data by a predetermined number of bits every time an operation process is executed.