Patent ID: 6586319
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:forming an insulation film on a compound semiconductor layer; forming an opening in said insulation film so as to expose a part of said compound semiconductor layer; forming a gate electrode of a refractory metal compound on said insulation film such that said gate electrode contacts with said compound semiconductor layer at said contact hole; and removing said insulation film by a wet etching process; said wet etching process being conducted by an etchant to which both of said gate electrode and said compound semiconductor layer show a resistance; wherein said compound semiconductor layer comprises a group III-V compound semiconductor material that contains P as a group V element, said insulation film is selected from SiO2 and SiON, said gate electrode is selected from a group consisting of WN, TiW and TiWN, and wherein said etchant is a buffered HF solution, and wherein said step of forming said opening is conducted such that a lateral size of said opening increases continuously from a bottom surface to a top surface of said insulation film.