Patent ID: 7188190
Filing Date: 2007-03-06
Classification: H04L

Abstract:
1. A packet data processing apparatus for processing a packet received from a network by a processor, comprising: a packet data access part, which has a plurality of registers and a plurality of selectors arranged in series, shifting the received packet through the plurality of registers toward an outlet in synchronization with a clock, wherein: the processor processes the received packet while the received packet is being-shifted through the plurality of registers, independently of an instruction order for processing the received packet; the processor and the packet data access part are directly connected by a read data line and a write data line; the processor reads out or writes data from or to the packet data access part by synchronizing the cycle time of the processor by the read data line and the write data line; and each of the plurality of registers of the packet data access part is connected to a neighbor register via one of the plurality of selectors which selects write data from between the processor via the write data line and the neighbor register, so as to enable the processor to process the received packet, instead of fully shifting the received packet through the entire series of registers.