Patent ID: 6406945
Filing Date: 2002-06-18
Classification: H01L,Y10S

Abstract:
A method for forming a transistor gate dielectric, comprising the steps of:a. forming a dummy layer over a semiconductor structure, and patterning said dummy layer to form a gate opening; wherein the bottom of said gate opening is the top surface of said semiconductor structure; b. forming a high-K dielectric layer on the bottom and sidewalls of said dummy dielectric layer, and forming a low-K dielectric layer on said high-K dielectric layer; c. forming spacers on the sidewalls of said gate opening; d. etching said low-K dielectric layer where it is not covered by said spacers; e. removing said spacers; and f. forming a gate electrode on and/or over said high-K dielectric layer and said low-K dielectric layer in said gate opening.