Patent ID: 7057237
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. A method of forming multiple spacer widths on a substrate, comprising: providing a substrate with isolation regions and a plurality of transistor regions including first, second, and third transistor regions comprised of a dielectric layer on said substrate between said isolation regions; forming a first gate electrode on said dielectric layer in said first transistor region, a second gate electrode on said dielectric layer in said second transistor region, and a third gate electrode on said dielectric layer in said third transistor region, said first gate electrode having a greater thickness than said second gate electrode and said second gate electrode having a greater thickness than said third gate electrode; forming an oxide layer on the substrate and on the gate electrodes in said plurality of transistor regions; and etching said oxide layer to form spacers with a first width adjacent to said first gate electrode, spacers having a second width less than said first width adjacent to said second gate electrode, and spacers having a third width less than said second width adjacent to said third gate electrode.