Patent ID: 8158481
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor structure comprising: forming a first gate stack upon a first region of a semiconductor substrate, the first gate stack comprising an upper first gate material layer; forming a material stack of a second gate dielectric and a second metal gate material layer upon the first gate stack and a laterally adjacent second region of the semiconductor substrate, wherein said second gate dielectric contacts a top surface and a sidewall surface of the upper first gate material layer and a semiconductor surface in the laterally adjacent second region; removing a portion of the material stack located above the top surface of the upper first gate material layer, while not removing another portion of the material stack contacting the semiconductor surface; forming a second silicon gate material layer over the second metal gate material layer and an exposed portion of the first gate material layer; forming a planarizing layer upon the second silicon gate material layer; and simultaneously etching non-selectively the planarizing layer and the second silicon gate material layer, while a vertical portion of said material stack is present on the sidewall surface of the upper first gate material layer, to form a second gate stack laterally adjacent the first gate stack and approximating the height of the first gate stack.