Patent ID: 8569838
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. An integrated circuit formed at a semiconducting surface of a body, comprising: at least one active area at the semiconducting surface; a plurality of electrodes formed at a gate level in the integrated circuit, each electrode extending for a length in a common direction with others of the plurality of electrodes, each electrode having a width at about a critical dimension for the integrated circuit, the critical dimension corresponding to a minimum photolithographically patterned feature size for the integrated circuit, the plurality of electrodes disposed relative to one another at a substantially constant pitch within a preselected range; an isolation dielectric structure disposed at the surface, and defining the boundary of the at least one active area; and the at least one interconnect, formed at the gate level in the integrated circuit, and disposed over the isolation dielectric structure, the at least one interconnect having a width at about the critical dimension for the integrated circuit, the at least one interconnect having a portion disposed at a location overlying the isolation dielectric structure that has a length extending in a direction substantially perpendicular to the common direction of the plurality of electrodes; wherein the plurality of electrodes and the the at least one interconnect are formed by a process comprising the steps of: