Patent ID: 6642148
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of forming a graded junction for a device on a semiconductor substrate, the method comprising the steps of:forming a dielectric layer overlying a surface of the semiconductor substrate; forming a first masking pattern overlying the dielectric layer overlying the surface of the semiconductor substrate, the first masking pattern having a first opening associated with a first region of the semiconductor substrate, wherein the first opening has a first lateral dimension: doping the semiconductor substrate with a first dopant of a first conductivity type, wherein the first masking pattern is used as a doping mask to form a first dopant region in the semiconductor substrate; swelling the first masking pattern to decrease the first lateral dimension of the first opening to a second lateral dimension, wherein the second lateral dimension is smaller than the first lateral dimension, and wherein the swelled doping mask overlies one or more portions of the first dopant region; and doping the semiconductor substrate with a second dopant of a second conductivity type, wherein the swelled first masking pattern is used as a doping mask to form a second dopant region in the semiconductor substrate, wherein the second dopant region defines a buried bitline region, the method further comprising the steps of: selectively etching the dielectric layer overlying the first dopant region prior to swelling the first masking pattern; removing the first masking pattern after doping the semiconductor substrate with the second dopant; and oxidizing the semiconductor substrate to form a bitline oxide region overlying the first region.