Patent ID: 6351423
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a global data bus for transmitting data of plurality of bits in parallel; a memory array having a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs, arranged corresponding to the columns of the memory cells in said memory array, each having the memory cells arranged on a corresponding column connected thereto; a local data bus of the plurality of bits arranged between said global data bus and said memory array for coupling selected bit line pairs out of said plurality of bit line pairs, and internal data write circuitry coupled between said global bus and said local data bus, for writing data, in parallel, into selected memory cells in said memory array through said local data bus and selected bit line pairs in accordance with the data on said global data bus, said internal data write circuitry including data mask circuit for inhibiting data writing into at least one memory cell out of said selected memory cells on the respective selected bit line pairs in accordance with a data mask designating signal designating a memory cell to be masked of data writing.