Patent ID: 6745319
Filing Date: 2004-06-01
Classification: G06F

Abstract:
A digital system comprising a microprocessor having an instruction execution pipeline with a plurality of pipeline phases, wherein the microprocessor comprises:program fetch circuitry operable during a first portion of the plurality of pipeline phases to fetch instructions; instruction decode circuitry connected to receive fetched instructions from the program fetch circuitry, the instruction decode circuitry operable during a second portion of the plurality of pipeline phases to decode fetched instructions; and at least a first functional unit connected to receive control signals from the instruction decode circuitry, the functional unit operable to perform a third portion of the plurality of pipeline phases, the third portion being execution phases, wherein the first functional unit comprises: swizzle circuitry connected to receive a source operand and having destination operand outputs for providing a destination operand in response to control signals from the instruction decode circuitry, wherein the swizzle circuitry is operable to form a swizzled result on the destination operand outputs by interleaving individual bits from a first portion of the source operand with individual bits from a second portion of the source operand wherein each bit of the source operand occupies a position in the destination operand; and wherein the first functional unit is operable to provide the swizzled result in response to a single instruction of a first type.