Patent ID: 8625354
Filing Date: 2014-01-07
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array configured to comprise a plurality of memory cells; a voltage generator configured to supply a program voltage, a sub-verification voltage, or a target verification voltage to the memory cells selected during a program operation, the target verification voltage being the lowest acceptable voltage in a target threshold distribution, the sub-verification voltage being lower than the target verification voltage; page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with the sub-verification voltage and latch second data according to results from comparing the threshold voltages of the memory cells with the target verification voltage; a sub-pass check circuit configured to output a sub-pass signal in response to the first data outputted from the page buffers; a main pass check circuit configured to output a main pass signal in response to the second data outputted from the page buffers; and a control circuit configured to control whether or not the voltage generator supplies the sub-verification voltage and the target verification voltage in response to the sub-pass signal and the main pass signal, wherein the sub-verification voltage is supplied and the target verification voltage is not supplied in response to the sub pass signal which is a first level, and the sub-verification voltage is not supplied and the target verification voltage is supplied in response to the sub pass signal which is a second level.