Patent ID: 9196569
Filing Date: 2015-11-24
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a gate electrode formed on a substrate; a first insulation layer formed on the gate electrode; a first conductive layer formed on the first insulation layer; a source electrode or drain electrode formed on the first conductive layer; a second insulation layer formed on the source electrode or drain electrode; and a second conductive layer formed on the second insulation layer, wherein the second insulation layer is formed with a bonding pad via through which the second conductive layer is electrically connected to the first conductive layer, wherein the second conductive layer is separated from the source electrode or drain electrode by the second insulation layer and does not contact with the source electrode or drain electrode, and wherein the source electrode or drain electrode has a longitudinal direction and a lateral direction, and the source electrode or drain electrode is transversely cut off by the bonding pad via at a position of the source electrode or drain electrode in the longitudinal direction, such that the source electrode or drain electrode is divided into separate segments.