Patent ID: 8108814
Filing Date: 2012-01-31
Classification: G06F,Y02P

Abstract:
1. A computer-readable, non-transitory storage medium storing a dummy metal insertion processing program for causing a computer to execute a procedure, said procedure comprising: optimizing an origin position of a dummy pattern template representing an arrangement pattern of dummy metal by preliminarily superposing and arranging said dummy pattern template, onto a layout area defined by layout data of a semiconductor circuit, while changing said origin position of said dummy pattern template; and upon detecting that it is confirmed that a result of a timing verification processing has no problem, superposing and arranging said dummy pattern template onto said layout area defined by said layout data at the optimized origin position of said dummy pattern template, to generate second layout data after inserting said dummy metal, wherein said preliminarily superposing and arranging comprises calculating variations of a wiring capacity and a wiring resistance, for each wiring, in a case where said origin position of said dummy pattern template was optimized, wherein said calculating said variations comprises, for each sub-area in said layout area defined by said layout data, calculating a variation of said wiring capacity for each wiring segment, from a length of said wiring segment in said sub-area, a distance between said wiring segment and a nearest dummy metal piece and data representing a relation among said length, said distance and said variation of said wiring capacity.