Patent ID: 6335901
Filing Date: 2002-01-01
Classification: G11C

Abstract:
A semiconductor device comprising:an internal circuit; a signal generation circuit which produces a selection signal; and a clock input circuit including a first clock signal output circuit which receives a first clock signal and outputs a second clock signal which is a delayed version of said first clock signal with a first delay time and a second clock signal output circuit which receives said first clock signal and outputs a third clock signal which is a delayed version of said first clock signal with a second delay time; wherein said internal circuit is operable based on said second clock signal in case that said selection signal is in a first state, wherein said internal circuit is operable based on said third clock signal in case that said selection signal is in a second state, wherein said first delay time is controlled to vary correspondingly with the variation in frequency of said first clock signal, and said second delay time is controlled to be fixed correspondingly with the variation in frequency of said first clock signal, and wherein power is not supplied to said first clock signal output circuit in case that said selection signal is in said second state so that said first clock signal output circuit is not activated.