Patent ID: 7098969
Filing Date: 2006-08-29
Classification: G02F,H01L

Abstract:
1. A TFT array substrate comprising: a plurality of gate lines formed on an insulative substrate, each of the gate lines including a gate electrode, a semiconductor layer formed on the gate electrodes with a gate insulating film interposed in between, a plurality of source lines, each of the source lines including a source electrode connected to the semiconductor layer, a plurality of drain electrodes, each of the drain electrodes connected to the semiconductor layer, a thin-film transistor formed by the source electrode and the drain electrode, the source electrode and the drain electrode being connected to the semiconductor layer, and a pixel electrode having a pixel line connected to the drain electrode, and overlapping with the semiconductor layer, wherein the width of a crossing portion of the semiconductor layer that crosses an edge line of the gate electrode is made smaller than the width of the drain electrode that is equal to a channel width of the thin-film transistor, and the width of a crossing portion of the pixel line that crosses the edge line of the gate electrode is also made smaller than the width of the drain electrode.