Patent ID: 7605473
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: a substrate having a memory region and a well contact region; an isolation layer on the substrate that defines an active region of the substrate; a gate insulating layer on the substrate, the gate insulating layer defining an opening therein, the opening exposing at least a portion of the well contact region of the substrate and acting as a charge pathway for charges generated during a subsequent etch of the isolation layer; a first conductive layer pattern on the gate insulating layer, the first conductive layer pattern having at least a portion of a side surface thereof exposed; a dielectric layer pattern on the first conductive layer pattern; and a second conductive layer pattern on the dielectric layer pattern, the first conductive layer pattern, the dielectric layer pattern and the second conductive layer pattern providing stacked gate electrodes on the memory region and the well contact region of the substrate.