Patent ID: 6046943
Filing Date: 2000-04-04
Classification: G06F,G11C

Abstract:
An output circuit having reduced switching, comprising:N data output terminals;an output enable terminal receiving an output enable signal, the output enable signal having an output enable potential and an output disable potential;N internal data output terminals;N driver circuits, each coupled to a one of the N data output terminals, one of the N internal data output terminals, and the output enable terminal, each driver circuit receiving an internal data output signal from its respective internal data output terminal and transmitting an output signal to its respective data output terminals when the output enable signal has the output enable potential;N next data terminals receiving N next data signals;a voter circuit coupled to the N internal data outputs and the N next data signals, the voter circuit producing a voter output having a first logic level and a second logic level, the voter circuit producing the second logic level when more than half of the N internal data outputs differ in logic level with the N next data signals;a voter latch circuit coupled to the voter output, the voter latch circuit latching the voter output and producing a voter latch output, the voter latch output having an invert potential and a non-invert potential; andN data switching circuits, each of the N data switching circuits being coupled between a one of the N next data terminals and a one of the N internal data output terminals, the N data switching circuits passing the N next data signals to the N internal data output terminals when the voter latch output is at the non-invert potential and passing inverted N next data signals to the N internal data output terminals when the voter latch output is at the non-invert potential.