Patent ID: 6078516
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A memory device comprising:a ferroelectric memory cell block;a data input terminal;an input/output latch buffer connected to both said ferroelectric memory cell block and said data input terminal;detecting means for detecting a request for writing of data;writing period forming means for forming, in response to a request for writing of data, a plurality of writing periods to repeat writing of data a predetermined number of times; andcontrol means for controlling said input/output latch buffer to write data to said memory cell block during the plurality of writing periods formed by said writing period forming means,wherein said writing period forming means includesa pulse generating circuit,a counter for counting output pulses of said pulse generating circuit, said counter using, as a target count, a value equal to the predetermined number of times that writing of data is repeated, anda writing period forming circuit for forming a writing period every time said counter counts.