Patent ID: 7436344
Filing Date: 2008-10-14
Classification: H03M

Abstract:
1. A pipeline A/D converter having a first mode and a second mode and comprising multiple stages connected by pipelines, at least one of said stages comprising: an amplifier, a first pair of a first capacitor and a second capacitor, and a second pair of a third capacitor and a fourth capacitor, wherein in said first mode, said amplifier amplifies an analog input signal at the amplification factor corresponding to the capacitance of said first pair of capacitors and outputs an amplified signal, and in said second mode, said amplifier amplifies said analog input signal at the amplification factor corresponding to the capacitance of only said second pair of capacitors or the capacitance of said first and second pairs of capacitors and outputs an amplified signal, and wherein at least one of said stages comprises: an amplifier; a first pair of a first capacitor and a second capacitor connected in series, at least said first capacitor being charged with the charge corresponding to said analog input signal in a first period, the charges stored in said first capacitor and said second capacitor being redistributed in a second period while current flowing is prevented at the connection point of said first capacitor and said second capacitor, the connection point of said first capacitor and said second capacitor being connected to the input terminal of said amplifier, and one terminal of said second capacitor, not connected to said first capacitor, being connected to the output terminal of said amplifier; and a second pair of a third capacitor and a fourth capacitor connected in series, at least said third capacitor being charged with the charge corresponding to said analog input signal in said first period, the charges stored in said third capacitor and said fourth capacitor being redistributed in said second period while current flowing is prevented at the connection point of said third capacitor and said fourth capacitor, the connection point of said third capacitor and said fourth capacitor being connected to an input terminal of said amplifier, and one terminal of said fourth capacitor, not connected to said third capacitor, being connected to an output terminal of said amplifier.