Patent ID: 7500041
Filing Date: 2009-03-03
Classification: G06F

Abstract:
1. A graphics system, comprising: a graphics processing unit having a first mode of operation in which said graphics processing unit is operable as an individual graphics processing unit and a second mode of operation in which said graphics processing unit is operable as part of a set of graphics processing units in which each respective graphics processing unit processes graphics data in parallel; a bus interface disposed in said graphics processing unit, said bus interface supporting a set of serial data lanes; and said bus interface including a mode controller in which for said first mode of operation said set of serial data lanes is operated as a single bus and for said second mode of operation a first subset of said serial data lanes is managed as one bus and a second subset of said serial data lanes is managed as a private bus for peer-to-peer communication with another graphics processing unit; said graphics processing unit in said second mode of operation having at least two data paths for directing traffic to said another graphics processing unit including a first data path via said private bus and a second data path via said one bus through a chipset to said another graphics processing unit; said graphics processing unit configured to direct traffic to said another graphics processing unit to avoid sending traffic over said private bus that has a semantic order in which an interpretation of data is critically dependent on an order of the data such that said private bus is utilized to send data in which the order that the data is received is not critical.