Patent ID: 6847252
Filing Date: 2005-01-25
Classification: H03K

Abstract:
1. A semiconductor integrated circuit device comprising: a first circuit comprising a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, a delay monitor circuit comprising a third MOS transistor of the first conductivity type and a fourth MOS transistor of the second conductivity type, and outputting a delay signal, a first comparator comparing the delay signal with a clock signal and outputting a first control signal and a second control signal, a well bias voltage generator outputting a first well bias voltage to the first MOS transistor and the third MOS transistor and outputting a second well bias voltage to the second MOS transistor and the fourth MOS transistor, and a compensation circuit comprising a fifth MOS transistor of the first conductivity type and a sixth MOS transistor of the second conductivity type, and outputting a difference signal, the difference signal based on the difference between a threshold voltage of the fifth MOS transistor and a threshold voltage of the sixth MOS transistor, wherein the well bias voltage generator outputs the first well bias voltage controlled by the first control signal and outputs the second well bias voltage controlled by the second control signal adjusted by the difference signal.