Patent ID: 6624029
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A method of fabricating a self-aligned non-volatile memory cell on a semiconductor substrate, said method comprising the steps of:forming a first insulating layer over said substrate; forming a main floating gate region on said first insulating layer; modifying a first portion of said first insulating layer next to a side of said main floating gate region to form a thin insulating region, said thin insulating region being thinner than a second portion of said first insulating layer under said main floating gate region; forming a small sidewall spacer over said thin insulating region; forming a second insulating layer over said first insulating layer and over said small sidewall spacer; removing a portion of said second insulating layer and said thin insulating region over said main floating gate region to expose a surface on top of said main floating gate region; forming a thin connecting layer over and in physical contact with both said small sidewall spacer and said main floating gate region, said thin connecting layer contacting said main floating gate region via said surface, whereby said small sidewall spacer is electrically connected to said main floating gate region, and whereby said main floating gate region, said small sidewall spacer and said thin connecting layer form a floating gate of said non-volatile memory cell; forming a third insulating layer over at least said floating gate; and forming a control gate over said second insulating layer and above at least said floating gate.