Patent ID: 6374395
Filing Date: 2002-04-16
Classification: G06F

Abstract:
A method of creating a core macrocell library of semiconductor device cells whereby said semiconductor device macrocells are free of notch errors, comprising the steps of:providing a first database that contains generic macrocell layout data; providing a second database that functions as temporary data repository during the process of the invention whereby said second database temporarily contains all data that relate to the process of the invention; reading generic macrocell layout data from said first database onto said second database thereby forming a generic circuit using said generic macrocell layout data and a generic alignment grid; determining valid locations where via interconnects are to be provided for metal-1 layout that is contained within said generic macrocell layout data whereby a valid location is represented by original metal-1 data; creating a test via device whereby said test via device is to be used for successive testing at valid locations where via interconnects are to be provided whereby said test via is represented by test via data; â€œdroppingâ€  said test via over an identified valid location thereby establishing a test via site; identifying notch errors for this latter test via site; creating, for locations where a notch error is identified, a shape that has the same geometric surface configuration as the surface area of said identified notch error thereby creating notch error data; merging said original metal-1 data with said test via data with said notch error data thereby creating corrected metal-1 data and thereby making said original metal-1 data and said test via device data and said notch error data redundant; deleting said original metal-1 data and said test via device data and said notch error data from said second database thereby retaining corrected metal-1 data on said second database; placing the corrected metal-1 data on said core macrocell library for further customer use; and repeating the above steps starting with reading generic macrocell layout data from said first database into said second database and ending with placing the corrected metal-1 data on said core macrocell library said repetition to be continued up to the point where all generic macrocell layout data that are contained in said first database have been read from said first database.