Patent ID: 6052028
Filing Date: 2000-04-18
Classification: H03F

Abstract:
A buffer circuit which comprises:(a) an input terminal;(b) a pair of complementary input transistors, each having a control electrode coupled to said input terminal;(c) a pair of serially connected complementary output transistors, each having a control electrode coupled to the emitter of a different one of said input transistors;(d) an output terminal coupled to the junction of said output transistors;(e) transient sensing means responsive to sensing of one of a positive or negative transient to inject a current to only a particular one of said input transistors determined by the direction of said transient which includes a first sensing transistor of the same conductivity type and a first resistor and coupled in series with one of said input transistors and a second sensing transistor of the same conductivity type and a second resistor coupled in series with the other of said input transistors; and(f) a mirror circuit mirroring each of said combinations of sensing transistor and associated resistor coupled across the control electrode and the electron collecting electrode of a different one of said output transistors.