Patent ID: 6381686
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A parallel processor comprising:a plurality of processor elements, each including an internal memory storing one or more sub-pages and performing using data stored in the internal memory; a first data bus connected to the plurality of processor elements; a second data bus connected in an external memory; and a shared memory connected to both the first and second buses; the shared memory including: a storage means having a plurality of sub-banks storing the sub-pages, a control means for controlling data transfer between the internal memory of the processor elements and the storage means through the first bus and data transfer between the storage means and the external memory through the second bus, and an access request management means for receiving as input an access request which generates a page fault to the storage means from the processor elements, storing another access request when another access request is input during the data transfer due to the access request between the shared memory and the external memory through the second bus, and causing the control means to execute the stored other access request when the stored other access request does not generate a page fault.