Patent ID: 8803783
Filing Date: 2014-08-12
Classification: G09G,G11C

Abstract:
1. A bidirectional shift register, comprising: a shift register portion including unit register circuits each of which has an output terminal for outputting a pulse and which are cascaded in m stages, where m is an integer which is equal to or larger than 6, for outputting the pulse from a column of the output terminals in a shift order which is one of a forward direction and a reverse direction; a clock signal generating portion for supplying n-phase clock pulses, where n is an integer which is equal to or larger than 3, to the stages of the shift register portion in sequence in the forward direction in forward shift operation of the shift register portion and in the reverse direction in backward shift operation; and a trigger signal generating portion for generating a forward direction trigger signal at a start of forward shift and generating a reverse direction trigger signal at a start of backward shift, the cascaded unit register circuits including main stages that are unit register circuits in which a load to be driven is connected to the output terminal and dummy stages that are unit register circuits in which a load to be driven is not connected to the output terminal, the main stages forming a successive column and the dummy stages being connected at a top before the column of the main stages and at a bottom after the column of the main stages in the cascade, when αf, αb, βf, and βb are natural numbers which satisfy both αf<βb<n and αb<βf<n, the unit register circuit in a k-th stage, where k is an integer which satisfies including: an output circuit for outputting an output pulse P each of the main stages including both the forward direction reset terminal and the reverse direction reset terminal, a number of the top dummy stages provided being βb, each of the top dummy stages including only the forward direction reset terminal as the reset terminal, a number of the bottom dummy stages provided being βf, each of the bottom dummy stages including only the reverse direction reset terminal as the reset terminal, the forward direction trigger signal instead of the output pulse P the reverse direction trigger signal instead of the output pulse P the unit register circuit in each of (αf+1)th to N-th stages includes a forward direction initialization circuit for, when the forward direction trigger signal is input, applying the first potential to the node, the potential of the reference point of the unit register circuit being set to the second potential correspondingly to the forward direction trigger signal at the start of forward shift, and the unit register circuit in each of first to (N−αb)th stages includes a reverse direction initialization circuit for, when the reverse direction trigger signal is input, applying the first potential to the node, the potential of the reference point of the unit register circuit being set to the second potential correspondingly to the reverse direction trigger signal at the start of reverse shift.