Patent ID: 8698316
Filing Date: 2014-04-15
Classification: B81B,H01L

Abstract:
1. A chip package, comprising: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads, wherein an upper conducting pad of the conducting pads has at least an opening or a trench, wherein the at least an opening or a trench exposes a lower conducting pad of the conducting pads.