Patent ID: 6321299
Filing Date: 2001-11-20
Classification: G06F,Y02D

Abstract:
A method of operating a computing system comprising a cache memory having a predetermined number of cache lines, comprising the steps of:first, for a plurality of write addresses, writing data to the cache memory at a location corresponding to each of the plurality of write addresses; andsecond, cleaning a selected number of lines in the cache memory in response to a context switch by the computing system;wherein for each of the selected number of lines the cleaning step comprises:evaluating a dirty indicator corresponding to data in the line; andcopying data from the line to another memory if the dirty indicator indicates the data in the line is dirty; andwherein the selected number of lines cleaned is less than the predetermined number of cache lines and further comprising the steps of:storing a value in an address indicator; andin response to each of the plurality of write addresses, setting the value equal to the write address if the write address is greater than what is stored in the address indicator, wherein the value in the address indicator represents a final value upon completing the plurality of write addresses; andwherein the selected number of lines is responsive to the final value.