Patent ID: 7719921
Filing Date: 2010-05-18
Classification: G11C,H03L

Abstract:
1. A semiconductor memory device having a duty detection circuit, the duty detection circuit comprising: first and second discharge transistors that operate in response to first and second control signals; first and second charge transistors that operate in response to third and fourth control signals; a first detection line connected to a contact node between the first discharge transistor and the first charge transistor; a second detection line connected to a contact node between the second discharge transistor and the second charge transistor; a comparator circuit that detects a potential difference between the first and second detection lines; a first gate circuit that can activate the first control signal when an internal clock signal being at a high level during every n cycles (where n is a power of 2) of an internal clock signal; a second gate circuit that can activate the second control signal when the internal clock signal being at a low level during every n cycles of the internal clock signal; a third gate circuit that can activate the third control signal when the internal clock signal being at the low level during every n cycles of the internal clock signal; a fourth gate circuit that can activate the fourth control signal when the internal clock signal being at the high level during every n cycles of the internal clock signal; a first delay circuit that delays one of the first and second control signals; and a second delay circuit that delays one of the third and fourth control signals.