Patent ID: 7488638
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. Method for fabricating a voltage-stable PMOSFET semiconductor structure proceeding from a P-doped semiconductor substrate, having the following steps of: applying a mask to the P-doped semiconductor substrate for definition of a window delimited by a peripheral edge, producing an N-doped well in the P-doped semiconductor substrate by means of high-voltage ion implantation, energy of the ion implantation being dimensioned in such a way that a P-doped inner zone remains at a surface of the semiconductor substrate and an edge zone of the N-doped well reaches as far as the surface of the semiconductor substrate, and producing a P-doped source region, a P-doped drain region and an N-doped channel region between the P-doped source region and the P-doped drain region in the remaining P-doped inner zone of the N-doped well, the source region, the drain region and the channel region being arranged in such a way that the remaining P-doped inner zone of the well remains as a drift zone between the channel region and the drain region, wherein after production of the N-doped well, the N-doped channel region is produced in the P-doped inner zone, wherein an insulator layer is applied to the N-doped channel region and a gate electrode is applied on the insulator layer, wherein a gate connection is applied to the gate electrode, wherein a source/bulk connection is applied to the P-doped source region and to a region of the N-doped channel region which adjoins the P-doped source region, and wherein an N+-doped transition zone is produced prior to the application of the source/bulk connection in the region of the N-doped channel region which adjoins the P-doped source region.