Patent ID: 6822300
Filing Date: 2004-11-23
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a first well of a first conductive type; second and third wells of a second conductive type, formed on both sides of said first well; first and second access MOS (metal oxide semiconductor) transistors of the first conductive type, each formed on one of said second or third well respectively; first and second driver MOS transistors of the second conductive type, formed on said first well; a word line connected to each of the gates of said first and second access MOS transistors, and extending in the direction along which said first, second and third wells are aligned; and first and second bit lines connected to the sources of said first and second access MOS transistors, respectively, and extending in the direction perpendicular to the direction along which said first, second and third wells are aligned, wherein first and second diffusion regions of the first conductive type for forming the sources/drains of said first and second access MOS transistors, and third and fourth diffusion regions, of the second conductive type for forming the sources/drains of said first and second driver MOS transistors, extend in the same direction, and the gates of said first and second access MOS transistors and the gates of said first and second driver MOS transistors extend in the same direction.