Patent ID: 6136660
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method of forming a memory cell comprising the steps of:forming spaced apart source and drain regions of a transistor at a top surface of a silicon body;forming a dielectric coating over the top surface of the silicon body;forming a contact hole with essentially vertical side walls in a portion of the dielectric coating overlying one of the source and drain regions that is to serve as a storage node of the cell;filling the contact hole with a conductor to form a conductive plug;forming a conductive barrier layer over the conductive plug;patterning a dielectric layer portion over the conductive barrier layer;forming a first conductive layer over at least sidewalls of the dielectric layer portion, the first conductive layer forming vertically disposed conductive portions connecting to the conductive barrier layer, the first conductive layer serving as an inner plate of a storage capacitor;forming a dielectric layer over the first conductive layer and top of the dielectric layer portion; andforming a second conductive layer over the dielectric layer for serving as an outer plate of the storage capacitor.