Patent ID: 7544980
Filing Date: 2009-06-09
Classification: B82Y,G11C,H01L

Abstract:
1. A memory device, comprising: a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region; a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall; charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; and a control gate structure having a first portion adjacent to the first portion of the charge storage material of the first location; wherein the control gate structure includes a portion located directly over a portion of the select gate structure.