Patent ID: 6037215
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating an integrated circuit memory device comprising the steps of:forming a plurality of memory cell transistors and a plurality of peripheral circuit transistors in a cell array region and in a peripheral circuit region, respectively, of an integrated circuit substrate;forming a bit line on the integrated circuit substrate, the bit line being electrically connected to at least one of the memory cell transistors;forming a first capping layer on the bit line;forming a first interlayer dielectric film on the integrated circuit substrate, including on the cell array region and on the peripheral circuit region, the first interlayer dielectric film exposing the first capping layer on the bit line;forming a second capping layer on the first capping layer and on the first interlayer dielectric film;forming a first contact hole in the cell array region and a second contact hole in the peripheral circuit region;simultaneously placing conductive material in the first and second contact holes, such that the conductive material in the first contact hole electrically contacts a memory cell transistor in the cell array region and the conductive material in the second contact hole electrically contacts a peripheral circuit transistor in the peripheral circuit region;forming a wiring layer on the second capping layer, electrically connected to the conductive material in the second contact hole;forming a second interlayer dielectric film on the wiring layer;forming a capacitor storage electrode on the conductive material on the first contact hole;forming a capacitor dielectric film on the capacitor storage electrode; andforming a capacitor plate electrode on the capacitor dielectric film.