Patent ID: 7670950
Filing Date: 2010-03-02
Classification: C25D,H01L

Abstract:
1. A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate, and a bottom, the method comprising: immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 5 microns and 300 microns, a depth dimension between 50 microns and 250 microns, and an aspect ratio greater than about 0.3:1, the deposition composition comprising: supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.