Patent ID: 7228514
Filing Date: 2007-06-05
Classification: G06F

Abstract:
1. A circuit design method comprising: automatically estimating interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout, the automatically estimating interconnect segments including automatically generating pin locations for a plurality of pins to be employed with the at least some circuit components of the circuit layout, the interconnect segments to interconnect the plurality of pins, and employing a route estimator to estimate lengths of the interconnect segments based on the generated pin locations of the plurality of pins without laying out the interconnect segments therebetween; and employing the estimated interconnect segment lengths and interconnect attributes derived from a schematic of the circuit in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout without layout the interconnect segments therebetween, wherein the interconnect attributes define certain electrical and physical properties of at least some of the interconnect segments to be employed.