Patent ID: 6380047
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a plurality of trenches formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises:forming a pad oxide layer on a main surface of the substrate or epitaxial layer; forming a polish stop layer having an upper surface on the pad oxide layer, forming a relatively large trench having side surfaces; depositing a first layer of an insulating material to fill the relatively large trench and cover the polish stop layer, whereby the first layer of the insulating material has a step in its upper surface above the relatively large trench; providing a planarization mask on the first layer of the insulating material above the step; etching to remove substantially all of the first layer of the insulating material above the polish stop layer; removing the planarization mask; performing a first polish to planarize such that an upper surface of the first layer of the insulating material is substantially flush with the upper surface of the polish stop layer; forming a relatively small trench, the relatively small trench having a width at the main surface less than a width at the main surface of the relatively large trench; forming a peripheral trench surrounding the relatively large trench and abutting the side surfaces of the relatively large trench, the peripheral trench having a width at the main surface less than the width at the main surface of the relatively large trench; thermally growing an oxide layer lining the relatively small trench and the peripheral trench; depositing a second layer of the insulating material to fill the relatively small trench and the peripheral trench and cover the polish stop layer; performing a second polish to planarize such that an upper surface of the second layer of the insulating material is substantially flush with the upper surface of the polish stop layer.