Patent ID: 7200692
Filing Date: 2007-04-03
Classification: G06F

Abstract:
1. A system comprising: a Packet Voice Data Module (PVDM) having a set of bi-directional data inputs/outputs configured as an interface between a master device coupled to a DMA engine and a slave device having a set of addressable registers including egress mailbox registers, ingress mailbox registers, and indirect access address registers, with the interface comprising; a set of master address inputs configured to couple to PVDM to the DMA engine, with the master address for-transmitting address data from the DMA engine to the slave; a master data strobe input configured to couple the PVDM to the DMA engine, with the master data strobe for strobing data; a master read/write signal input configured to couple the PVDM to the DMA engine, with master read/write signal for indicating whether data is to be read from or written to the slave; a set of slave select signal inputs configured to couple the PVDM to the DMA engine, with slave select signals for selecting one of a plurality of slaves; a slave wait signal output configured to couple the PVDM to the DMA engine, with the slave wait signal asserted by a slave to delay a data transfer; a slave reset signal input configured to couple the PVDM to the DMA engine, with the slave reset signal resetting the slave when asserted; a clock signal line output configured to couple the PVDM to the DMA engine and to receive a clock signal; and a clock signal line input configured to couple the PVDM to the DMA engine and to receive a clock input signal.