Patent ID: 6300171
Filing Date: 2001-10-09
Classification: H01L

Abstract:
Method of manufacturing an edge structure for a high voltage semiconductor device, comprising: a first step of forming a first semiconductor layer of a first conductivity type; a second step of forming a first mask over the top surface of said first semiconductor layer; a third step of removing portions of said first mask in order to form at least one opening in it; a fourth step of introducing dopant of a second conductivity type in said first semiconductor layer through said at least one opening; a fifth step of completely removing said first mask and forming a second semiconductor layer of the first conductivity type over said first semiconductor layer; a sixth step of diffusing the dopant implanted in said first semiconductor layer in order to form a doped region of the second conductivity type in said first and second semiconductor layers; and repeating at least one time the second step up to the sixth step in order to form a final edge structure comprising a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, said columns being inserted in said number of superimposed semiconductor layers and formed by superimposition of said doped regions subsequently implanted through the mask openings, wherein each mask for forming said column of doped regions has an additional opening in respect to the preceding mask, said additional opening being properly distanced from the preceding opening in order to form an additional column, the column near said high voltage semiconductor device being deeper than the column farther from said high voltage semiconductor device.