Patent ID: 6516432
Filing Date: 2003-02-04
Classification: G01R

Abstract:
An apparatus for performing AC scan chain built-in self test and diagnostics of an integrated circuit, comprising:a reconfigurable linear feedback shift register (LFSR) having an input and a plurality of output lines, the LFSR generating a bit pattern; a plurality of scan chains having a plurality of latches, the scan chains interconnected to the LFSR, each scan chain serially receiving at a respective input the bit pattern output by the LFSR, and each scan chain propagating the bit pattern from the respective input to a respective output of each scan chain; a multiple input signature register (MISR), the MISR receiving the bit patterns output by the respective scan chains; the MISR generating a signature in accordance with the bit patterns input from the scan chains; a comparison circuit for comparing the signature with an expected signature based upon the pattern input to the plurality of scan chains, wherein when the signature is equal to the expected signature, the scan chains are functioning correctly; and a controller for reconfiguring the LFSR to vary the bit patterns output by the LFSR and for varying a timing sequence of operation of the LFSR, the plurality of scan chains, the MISR, and the comparison circuit.