Patent ID: 6057227
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A method for forming a damascene structure on a semiconductor substrate having semiconductor devices formed thereon comprising:a) depositing a layer of non-stoichiometric oxide over said semiconductor substrate;b) planarizing said layer of non-stoichiometric oxide;c) depositing a layer of stoichiometric oxide over said layer of non-stoichiometric oxide;d) masking and etching said layer of stoichiometric oxide and said layer of non-stoichiometric oxide with a non-selective etch process so as to etch said layer of non-stoichiometric oxide and so as to etch said layer of stoichiometric oxide so as to form openings within said layer of non-stoichiometric oxide and within said layer of stoichiometric oxide;e) masking and etching said semiconductor substrate with a selective etch process so as to selectively etch portions of said layer of stoichiometric oxide so as to form a plurality of trenches within said layer of stoichiometric oxide, said layer of non-stoichiometric oxide forming an etch stop so as to form trenches having a uniform depth, said step of masking and etching said semiconductor substrate with a selective etch immediately following step d);f) depositing a layer of metal over said semiconductor substrate such that a portion of said layer of metal overlies said layer of stoichiometric oxide and such that said layer of metal is deposited within said openings within said layer of non-stoichiometric oxide and within said plurality of trenches; andg) polishing said semiconductor substrate so as to remove that portion of said layer of metal that overlies said layer of stoichiometric oxide so as to form interconnects within said trenches and so as to form contacts within said openings in said layer of non-stoichiometric oxide such that said contacts selectively electrically couple said interconnects to said semiconductor devices.