Patent ID: 6303433
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of fabricating a capacitor for a dynamic random access memory, comprising:forming a transistor on a substrate, wherein the transistor comprises a gate on the substrate and a source/drain region in the substrate;forming a first dielectric layer on the substrate to cover the transistor;forming a second dielectric layer and a third dielectric layer over the first dielectric layer;etching the first dielectric layer, the second dielectric layer, and the third dielectric layer to form a contact opening which exposes a portion of the source/drain region;forming a conductive layer to completely fill the contact opening and electrically coupled with the source/drain region;forming a fourth dielectric layer on the third dielectric layer to cover the conductive layer;removing the third dielectric layer and the fourth dielectric layer to form a storage node opening, which exposes a portion of the second dielectric layer and a portion of the conductive layer;forming a bottom electrode in the storage node opening to completely cover an exposed conductive layer and an exposed second dielectric layer;removing the third dielectric layer and the fourth dielectric layer until the second dielectric layer is exposed; andforming a capacitor dielectric layer and a top electrode over the bottom electrode, wherein the exposed conductive layer provides support for the bottom electrode and is completely in contact with the bottom electrode.