Patent ID: 6621120
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A semiconductor device comprising:a base layer formed by an n-type semiconductor substrate having resistivity uniform in a thickness direction; a p-type channel diffusion region, an n-type emitter diffusion region, an emitter electrode, a gate-insulating film, and a gate electrode formed in one principal surface region of said substrate; a p-type collector layer and a collector electrode formed in a second principal surface region of said substrate; and an n-type impurity diffusion layer having an impurity concentration higher than an impurity concentration in said base layer and being provided between said collector layer and said base layer, wherein a thickness of said impurity diffusion layer defined by Xfsâˆ’Xj is in a range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is a position at which said impurity concentration of said impurity diffusion layer equals twice said impurity concentration of said base layer and Xj is a position of a junction between said impurity diffusion layer and said collector layer; wherein a voltage at which said base layer completely depletes lies in a range from 0.45 to 0.7 times a blocking voltage of said semiconductor device.