Patent ID: 7733130
Filing Date: 2010-06-08
Classification: G06F,H04L

Abstract:
1. A data communications system comprising: a source clock signal; a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency; a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is less than the first frequency; and circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched; wherein said data is only latched when said pulse is asserted and on a given edge of the first clock signal, and wherein said circuitry is configured to generate said pulse such that said given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal; circuitry configured to generate an additional pulse, wherein when said pulse is asserted and said additional pulse is not asserted, said data is always latched on a same edge of the first clock signal, either a positive edge or a negative edge.