Patent ID: 7969008
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a circuit portion formed on said semiconductor substrate and including a plurality of semiconductor elements; insulating lamination formed above said semiconductor substrate and covering said circuit portion; multilevel wiring structure formed in said insulating lamination and including wiring patterns and via conductors; and pad electrode structure formed above said semiconductor substrate and connected to said multilevel wiring structure, said pad electrode structure including pad wiring patterns in a plurality of levels and pad via conductors interconnecting said pad wiring patterns, at least said pad wiring pattern in an uppermost level including a pad pattern and a sealing pattern surrounding said pad pattern in a loop shape with some distance from said pad pattern, at least one of the pad wiring patterns in a level other than the uppermost level having a continuous extended pad pattern of a size overlapping said sealing pattern, said pad via conductors including a plurality of columnar via conductors disposed in an area overlapping said pad pattern and a loop-shaped wall portion disposed in an area overlapping said sealing pattern, said pad pattern of said pad wiring pattern or said extended pad pattern and said columnar via conductors constituting a laminated bonding pad, and said extended pad pattern, said sealing pattern and said loop-shaped wall portion surrounding said laminated bonding pad to form a cup-shaped moisture resistant structure having a function of shielding moisture and hydrogen.