Patent ID: 7586149
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A circuit device including vertical transistors, the circuit device comprising: a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate electrodes in the peripheral circuit region and extending between the gate electrodes to commonly interconnect the gate electrodes in the peripheral circuit region, thereby configuring a peripheral circuit; signal lines electrically connected to upper surfaces of the channel pillars or to at least one of the local interconnection lines; and interconnection contacts electrically connecting the local interconnection line to the buried bitline of a different row from that of the commonly-connected gate electrodes or electrically connecting the local interconnection lines to the signal lines, thereby configuring the peripheral circuit.