Patent ID: 6016541
Filing Date: 2000-01-18
Classification: G06F

Abstract:
An instruction controlling system for performing out-of-order instruction control, comprising:register registering data used for executing an instruction;instruction register outputting a logical address of said register, which is used for executing the instruction;decoding unit decoding the logical address output from said instruction register;register update buffer temporarily storing the data to be registered to said register;update table registering an address in said register update buffer, to which data for updating said register is registered, and an update reservation instructing bit indicating whether or not an update operation of contents of a corresponding address in said register according to the data registered to said register update buffer, is reserved, in correspondence with the address in said register; andreservation station registering the address in said register, the address in said register update buffer, and the update reservation instructing bit by making a correspondence between them, assigning priorities for executing corresponding instructions to entries corresponding to contents of each registration, and transmitting an address of data to be processed to said register update buffer, if the update operation of contents of said register is reserved, wherein:when the instruction is executed, the update reservation instructing bit in said update table, which corresponds to the address output from said instruction register, is referenced;an arithmetic operation is performed by using the data registered to said register if said register is updated; andthe arithmetic operation is performed by using the data registered to said register update buffer if the update operation of said register is reserved.