Patent ID: 8604533
Filing Date: 2013-12-10
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a memory cell transistor which has a floating gate formed over a semiconductor substrate via a tunnel insulating film, a control gate formed over the floating gate via an insulating film, and a source and a drain formed in the semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate formed over the semiconductor substrate via a gate insulating film, and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the N-type first impurity diffusion layer, and an N-type third impurity diffusion layer which is formed in the N-type second impurity diffusion layer and is shallower than the N-type second impurity diffusion layer, wherein the end of the N-type first impurity diffusion layer on a side of which the floating gate is formed being positioned between an end portion of the N-type second impurity diffusion layer on the side of which the floating gate is formed and the channel area, and an impurity concentration of the N-type second impurity diffusion layer is lower than the impurity concentration of the third impurity diffusion layer.