Patent ID: 8238501
Filing Date: 2012-08-07
Classification: H03L,H04L,H04Q

Abstract:
1. A burst-mode clock and data recovery circuit using phase selecting technology, comprising: a phase-locked loop circuit for providing a plurality of fixed clock signals, each of which comprises a clock phase; an oversampling phase selecting circuit, coupled to the phase-locked loop circuit, for using the clock signals to detect a data edge of received data signal by counting a number of times that the data edge of the data signal falls between two of the fixed clock signals, and selecting the clock phase to be locked according to the position of the data edge, wherein the oversampling phase selecting circuit comprises: a delay-locked loop circuit, coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, for comparing a data phase of the data signal with the clock phase to be locked so as to control the data phase of the data signal to be delayed for a delay time period until the data phase is locked to the clock phase.