Patent ID: 6058156
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A shift register device comprising:a bit data input line along which bit data is to be shifted from an input terminal toward an output terminal;a plurality of data hold circuits connected and arranged in series along said bit data input line between said input terminal and said output terminal; anda clock signal input line connected individually to each of said plurality of data hold circuits for providing an input clock signal successively to said each of said plurality of data hold circuits;said each of said plurality of data hold circuits including a flip-flop circuit and a latch circuit directly connected in series in the named order;each of said plurality of data hold circuits further including a time-delay circuit having an input and an output designed and adapted to delay an operating timing of said flip-flop circuit with respect to an operating timing of said latch circuit, wherein said flip-flop circuit and said latch circuit are respectively enabled on alternate half-cycles of said clock input signal.