Patent ID: 9042391
Filing Date: 2015-05-26
Classification: G06F,H04L

Abstract:
1. An information processing device comprising: a memory; a plurality of processors that issue a memory access request to the memory; a router group that is provided with a first router connected to the memory and a second router forming a transfer path between the first router and the processors, and transmits the memory access request issued from the processors to the memory; and an address protection unit that is connected to the first router and examines the memory access request packet input to the first router to detect a violated memory access, wherein each of the processors is provided with a processor core that generates the memory access request for the memory, a cache memory, and a packet generator that generates and sends a packet for making a pseudo memory access request in a case where the memory access request of the processor core hits the cache memory, and wherein when receiving the packet for making the pseudo memory access request, the first router transmits the received pseudo memory access packet to the address protection unit.