Patent ID: 8155261
Filing Date: 2012-04-10
Classification: G11C

Abstract:
1. A shift register comprising: a first thin film transistor, of which a gate is connected to a first node that serves as a pull-up node, a source is connected to a clock signal terminal, and a drain is connected to an the output terminal at current stage; a second thin film transistor, of which a gate is connected to a second node that serves as a pull-down node, a source is connected to the output terminal at current stage, and a drain is connected to a low level signal terminal; a third thin film transistor, of which a gate is connected to the first node, a source is connected to the low level signal terminal, and a drain is connected to the second node; a fourth thin film transistor, of which a gate is connected to the second node, a source is connected to the low level signal terminal, and a drain is connected to the first node; a first capacitor connected between the clock signal terminal and the second node, for changing the second node into high level when the clock signal terminal is at high level; a discharging module connected between the clock signal terminal and the output terminal at current stage, for causing the output terminal at current stage to discharge to the clock signal terminal when the output terminal at current stage is at high level and the clock signal terminal is at low level; and a compensation module connected between the first node and the low level signal terminal, for providing compensation and compensation protection for the first node, so as to change the second node into high level or low level correspondingly, according to the high level or low level of the clock signal.