Patent ID: 6191983
Filing Date: 2001-02-20
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising: a plurality of memory cells which are disposed two-dimensionally in the word line and bit line directions in a memory cell array, said plurality of memory cells are composed of a large number of normal memory cells and a small number of redundant memory cells; and peripheral circuits having word drivers and sense amplifiers on the outside of said memory cell array which are capable of switching an operation to said redundant memory cell when said normal memory cell is defective,wherein said redundant memory cells are disposed approximately at the center in said word line and bit line directions, a layout unit of said word drivers and sense amplifiers connected to said redundant memory cell is substantially equal to what layouts for the redundant memory cell and for the normal memory cell are combined and is substantially equal to the layout unit of said normal memory cell and a control input of said word driver or said sense amplifier is replaced among those for the normal and redundant ones.