Patent ID: 6542346
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A high-voltage tolerance electrostatic discharge (ESD) protection circuit connected to a pad of an integrated circuit, comprising:a voltage-sharing circuit connected between the pad and a power rail for generating a reference voltage not higher than the voltage of the pad; and a semiconductor controlling rectifier (SCR) coupled to the voltage-sharing circuit, comprising: a first n-type MOS transistor, wherein the first n-type MOS transistor further comprises a gate coupled to the reference voltage to improve the triggering of the semiconductor controlling rectifier during an ESD event, a p-type substrate; an n-type well disposed on the p-type substrate to form a PN junction, wherein the first n-type MOS Transistor further comprises a source/drain disposed on the PN junction; a p-type doped region disposed in the n-type well; an n-type contact region disposed in the n-type well, connected to both the p-type doped region and the pad; an n-type doped region disposed on the p-type substrate; a p-type contact region disposed on the p-type substrate, connected to both the n-type doped region and the power rail; and a second n-type MOS transistor connected in series with the first n-type MOS transistor, disposed on the surface of the substrate between the first n-type MOS transistor and the n-type doped region.