Patent ID: 6741193
Filing Date: 2004-05-25
Classification: H03M

Abstract:
A parallel in serial out circuit for converting 2r data bits (r is a natural number) applied thereto in parallel into a corresponding serial data, comprising:first to (r+1)-th latch means wherein the s-th (1&lE;s&lE;r+1) latch means comprises 2r+1+s flip-flops; first to r-th selector means respectively provided between adjacent two of said first to (r+1) th latch means; wherein the t-th latch means (1&lE;t&lE;r) is provided such as to latch 2r+1+t data bits in synchronism with a clock signal of 2t+2Ã—100 MHz, and the (r+1)-th latch means is provided to latch a single data bit in synchronism with a clock signal of 2r+1âˆ’2Ã—100 MHz, and wherein the u-th selector means (1&lE;u&lE;r) is provided with 2râˆ’u selectors each of which receives two different data bits outputted from the u-th latch means and generates sequentially the received two different data bits in synchronism with a clock signal of 2uâˆ’2Ã—100 MHz.