Patent ID: 6362047
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method for manufacturing a memory point including a control gate and a floating gate above an insulator including a sufficiently thin area to enable a tunnel effect between an underlying semiconductor substrate and the floating gate, including the steps of:delimiting at the surface of the substrate an active region by field insulation areas; forming a first insulating layer; opening a window in the first insulating layer to partially expose the entire width of the active region and a portion of the insulating areas; forming a second very thin insulating layer by thermal oxidation; depositing a first conductive material; forming a third insulating layer; and depositing a second conductive material, further including the step of etching the second conductive material, the third insulating layer, the first conductive material and the second and first insulating layers according to a same contour to expose the active region and the insulation areas in the vicinity of the border regions between the active region and the insulation areas.