Patent ID: 6152073
Filing Date: 2000-11-28
Classification: H01J,H01L

Abstract:
An assembly for the manufacture of highly integrated circuits on a semiconductor substrate, comprising:a wafer of semiconductor material, said wafer having coated front and back sides, said front side having an outer edge region;a process chamber having a seating surface for said wafer and a ring diaphragm disposed in said outer edge region of said front side of said wafer;said wafer and said ring diaphragm defining a first portion of said process chamber in which said front side of said wafer is subjected to a neutral gas, and a second portion of said process chamber in which said back side of said wafer is etched by subjecting said back side to reactive particles produced in a plasma; andan indirect limit stop for holding said ring diaphragm and said wafer in a completely contact free manner relative to each other on said front side of said wafer.