Patent ID: 6855601
Filing Date: 2005-02-15
Classification: H01L

Abstract:
1. A method of manufacturing a trench-gate semiconductor device having source and drain regions which are separated by a channel-accommodating region adjacent to the trench-gate, including the following sequence of steps: (a) providing at a surface of a semiconductor body a masking pattern having therein a window that is used for self-aligning a gate trench and parts of the gate formed in the subsequent steps (b) to (d); (b) etching the trench into the semiconductor body within the window, and forming a dielectric layer at the walls of the trench to provide a gate dielectric for capacitively coupling the gate to the channel-accommodating region, (c) depositing and then etching back semiconductor gate material to provide a semiconductor gate part on the dielectric layer in the trench without protruding above the masking pattern at the window, and (d) then providing at the window a thickness of metal silicide material at the top of the semiconductor gate part sufficient to form a silicide upstanding part of the gate having a top and sidewalls that protrude upward above the level of the body surface, the gate dielectric at least adjacent to the channel-accommodating region being protected from the metal silicide material by at least the semiconductor part of the gate and by the protrusion of its silicide part above the level of the body surface.