Patent ID: 8058161
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A method for fabricating a recessed STI wide transistor, comprising: providing a substrate with active regions of a first conductivity type, forming a first oxide layer on the substrate; forming a nitride layer on the first oxide layer; employing a photolithographic process to pattern and etch the first oxide and nitride layers to create isolation trenches extending in a first direction; filling the isolation trenches partially by providing insulative material in a bottom portion of the isolation trenches; thereby establishing recessed isolation trenches defining active area pillars therebetween; forming at least one conducting serpentine gate structure including a gate electrode on a gate dielectric; the gate structure running in a second direction transverse to the first direction and thereby defining source/drain regions in the active area pillars on opposing sides of the gate structure; and the gate dielectric being a substantially non-charge trapping dielectric that consists of a single layer dielectric film ; and implanting dopant of a second conductivity type to form source/drains in the source/drain regions; wherein the recessed isolation trenches have trench space lengths and trench recess depths; and wherein two times the trench recess depths is greater than the trench space lengths.