Patent ID: 6343364
Filing Date: 2002-01-29
Classification: G06F,G06K,H04L

Abstract:
A method for generating a local clock signal in a device using Universal Serial Bus downstream signals DP and DM, comprising;a) receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals; b) counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal; c) dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal; and d) generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T.