Patent ID: 7916821
Filing Date: 2011-03-29
Classification: H03L,H04L

Abstract:
1. A synchronizing circuit, comprising: a first phase detector configured to generate at least one first control signal related to a first phase comparison of a first edge, in a first direction, of a clock signal and a first edge, in the first direction, of a modified clock signal; a first delay circuit configured to use a first delay magnitude related to the at least one first control signal to generate an intermediate clock signal as a delayed version of the clock signal; a second phase detector configured to generate at least one second control signal related to a second phase comparison of a second edge, in a direction opposite to the first direction, of the clock signal and a second edge, in a direction opposite to the first direction, of the modified clock signal; a second delay circuit configured to use a second delay magnitude related to the at least one second control signal to generate the second edge of an inverse of the modified clock signal as a delayed version of the second edge of an inverse of the intermediate clock signal; and a third delay circuit configured to delay the intermediate clock signal by a third delay magnitude, wherein the third delay magnitude corresponds to a value that lies between a value of the first delay magnitude and a value of the second delay magnitude.