Patent ID: 7732911
Filing Date: 2010-06-08
Classification: H01L,H05K

Abstract:
1. A semiconductor packaging substrate comprising: a dielectric layer including a plurality of packaging units and a plurality of electrostatic dissipation regions defined on a surface of the dielectric layer; a plurality of leads formed in each packaging unit on the dielectric layer; a plurality of first electrostatic guiding traces and a plurality of second electrostatic guiding traces both formed in the electrostatic dissipation regions and attached to the surface of the dielectric layer, wherein at least a first electrostatic guiding trace and at least a second electrostatic guiding trace disposed in each electrostatic dissipation region are separated in equal line spacing and electrically isolated, and the first electrostatic guiding trace is electrically connected to some of the leads; and a solder mask formed on the dielectric layer to partially cover the leads but expose the first electrostatic guiding traces and the second electrostatic guiding traces, wherein the electrostatic dissipation regions are disposed between each two adjacent packaging units and completely exposed from the solder mask.