Patent ID: 7478203
Filing Date: 2009-01-13
Classification: G06F

Abstract:
1. A method for reducing off-chip bandwidth requirements for a processor, comprising: maintaining a dirty bit for a line of an on-chip cache; storing new data in an on-chip new data buffer; reading old data from a location in the line of the on-chip cache of said processor in preparation of writing new data from the on-chip new data buffer to the location in the line of the on-chip cache; determining whether new data bytes in the new data and associated old data bytes in the old data are different; writing the new data bytes to the line of the on-chip cache; marking each new data byte in the new data, which is different from the associated old data byte, to identify said each new data byte wherein said marking is in addition to maintaining the dirty bit for the line of the on-chip cache; and writing only the marked new data bytes to an off-chip store when updating the off-chip store.