Patent ID: 8817525
Filing Date: 2014-08-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in at least one of a row direction and a column direction, each of the plurality of memory cells having a variable resistance element including a first electrode and a second electrode and a selection transistor, one of the first electrode and the second electrode of the variable resistance element being connected to one of input and output terminals of the selection transistor, the variable resistance element further including a variable resistor between the first electrode and the second electrode, the variable resistor including metal oxide, such that an electrical resistance between the first electrode and the second electrode changes in accordance with application of an electrical stress between the first electrode and the second electrode, thereby storing information in the semiconductor memory device; and a control circuit configured to control a reset operation and a set operation, the reset operation being an operation of applying a reset voltage pulse having a first polarity to ends of a memory cell among the memory cells to convert an electrical resistance between the first electrode and the second electrode of the variable resistance element of the memory cell to a high resistance in a high-resistance range, the set operation being an operation of applying a set voltage pulse having a second polarity opposite to the first polarity to ends of a memory cell among the memory cells to convert an electrical resistance between the first electrode and the second electrode of the variable resistance element of the memory cell to a low resistance in a low-resistance range, wherein the control circuit is configured to, in the set operation, apply a certain voltage to a control terminal of the selection transistor of the memory cell to limit an upper limit of a set current flowing between the first electrode and the second electrode to a low electric current, and perform control, while limiting the upper limit of the set current to the low electric current, to apply the set voltage pulse to the plurality of memory cells for a longer time than a time during which the reset voltage pulse is applied in the reset operation.