Patent ID: 7510954
Filing Date: 2009-03-31
Classification: G11C,H01L

Abstract:
1. A method of fabricating a memory array comprising: forming a plurality of local data/bit lines in a surface of a substrate; forming a mask layer on the surface of the substrate; forming openings in the mask layer so as to be aligned generally with corresponding local data/bit lines; depositing sidewall material in the openings of the mask layer; directionally etching the sidewall material so as to form sidewall structures arranged against inner surfaces of the openings and defining a generally centrally arranged hole in the sidewall structures; forming a plug structure in the holes; performing a directional etch with the plug structures as masking structures so as to define a plurality of pillars extending generally vertically from the surface of the substrate and substantially conforming to the contour and position of the plug structures; forming gate structures about the pillars such that the gate structures substantially completely encompass corresponding pillars; and forming global data/bit lines extending across the pillars.