Patent ID: 6238958
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method for manufacturing a transistor in integrated circuits, comprising:providing a substrate;forming an insulating layer on said substrate;forming a conductor layer on said insulating layer;forming a patterned photoresist layer on said conductor layer;using said patterned photoresist layer as a mask to etch said conductor layer, said conductor layer having a sidewall;removing said patterned photoresist layer;forming a liner layer on said sidewall of said conductor layer;introducing first ions to form a lightly doped drain region on and in said substrate by using said liner layer and the etched conductor layer as a mask;forming a spacer on said liner layer;introducing second ions into said lightly doped drain region to form a source/drain region by using said spacer, said liner layer and said etched conductor layer as a mask;removing said spacer;forming an epi-silicon layer on said lightly doped drain region, said source/drain region and top surface of said conductor layer; andtreating said epi-silicon layer with a salicidation process to form a salicide layer.