Patent ID: 8112736
Filing Date: 2012-02-07
Classification: G01R,G06F,Y02P

Abstract:
1. A method of designing an integrated circuit (IC) in a wafer, the method comprising: simultaneously supplying power to each of a first stack having a plurality of first inputs coupled to a plurality of devices under test (DUTs) located within the wafer and a second stack having a plurality of second inputs coupled to a plurality of reference devices located within the wafer; wherein each of the first stack and the second stack comprises a first-type device and at least two second-type devices; wherein the first-type device is one of a p-channel device or an n-channel device; wherein each second-type device is the other of the p-channel device or the n-channel device; during said simultaneously supplying, comparing a first output from said DUTs and a second output from said reference device; re-designing an existing IC design, based on at least an output resulting from said comparing; and outputting a new IC design resulting from said re-designing.