Patent ID: 8044723
Filing Date: 2011-10-25
Classification: H03L

Abstract:
1. An apparatus for wireless communication, comprising: a phase-locked loop (PLL) used to generate an oscillator signal for a frequency channel selected from among a first frequency channel and a second frequency channel, each frequency channel being associated with a set of PLL settings for at least one parameter in addition to overall divider ratio, the multiple frequency channels being associated with at least two different sets of PLL settings, and the PLL operating based on the set of PLL settings for the selected frequency channel; and a memory comprising the at least two different sets of PLL settings comprising a first set of PLL settings resulting in lower spur levels at the first frequency channel than a second set of PLL settings, the second set of PLL settings resulting in lower spur levels at the second channel frequency than the first set of PLL settings, wherein the memory stores a table of the PLL settings for the multiple frequency channels, the PLL settings comprising PLL loop bandwidth settings, frequency equation settings, frequency division scheme settings, low side or high side injection settings, overall divider ratio settings, and VCO biasing settings.