Patent ID: 7537994
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: providing a semiconductor material; defining a line across the semiconductor material, the line having a narrow region between wide regions, the line having a pair of opposing sides; forming a pair of trenches along opposing sides of the line; forming protective material along sidewalls of the trenches to narrow the trenches; isotropically etching the semiconductor material through the trenches to merge the trenches under the narrow region without merge the trenches under the wide regions; forming gate dielectric along the narrow region of the line; forming electrically conductive gate material within the trenches and under the narrow region; conductively-doping the wide regions of the line of the semiconductor material to form a pair of source/drain regions; such pair of source/drain regions being spaced from one another by a channel region comprised by the narrow region of the line of the semiconductor material; wherein the narrow portion of the line has an outer periphery; and wherein the gate material is a transistor gate entirely surrounding the outer periphery of the narrow portion of the line.