Patent ID: 6275446
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A clock generator, comprising:an input buffer for receiving an external clock signal; anda one-shot circuit coupled to the input buffer for providing output pulses in response to the external clock signal, wherein the one-shot circuit comprises a delay circuit having at least one delay element and at least one associated bypass;wherein the one-shot circuit generates a first logic level in response to a completion of an output pulse and presents the first logic level to an input of the delay circuit, further wherein the first logic level activates the at least one associated bypass and is passed to an output of the delay circuit substantially without delay; andwherein the one-shot circuit generates a second logic level in response to a beginning of an output pulse and presents the second logic level to the input of the delay circuit, further wherein the second logic level deactivates the at least one associated bypass and is passed to the output of the delay circuit at a time delta substantially equal to a predetermined delay time of the at least one delay element.