Patent ID: 7994843
Filing Date: 2011-08-09
Classification: H02M,H03K,H03M

Abstract:
1. A boost circuit configured to receive a bitstream signal, to boost the amplitude of the bitstream signal thus received, and to output the bitstream signal thus boosted, the boost circuit comprising: a first clock booster configured to receive a clock signal, and to boost the amplitude of the clock signal thus received; a second clock booster configured to receive an inverted clock signal, and to boost the amplitude of the inverted clock signal; a switch configured to receive output signals of the first and second clock boosters, and to select one signal that is high level from among the output signals thus received; a first capacitor coupled to an output terminal of the switch; and a level shifter configured to level-shift the high level of the bitstream signal to the voltage level that occurs at the first capacitor.