Patent ID: 7168013
Filing Date: 2007-01-23
Classification: G11C

Abstract:
1. A method of performing a pre-program cycle of an erase operation on a flash memory having a row-to-row short in a primary array and a plurality of redundant rows to replace the rows shorted together, comprising: pre-programming the redundant rows; setting the row address to the first address of the primary array; pre-programming each row in the primary array incrementally until a row address matches a row address replaced by a redundant row; reading an error code that indicates a row-to-row short; disabling a redundant circuit that redirects address requests from the shorted rows to the redundant rows; activating the shorted rows together; pre-programming the shorted rows simultaneously; incrementing the row address to skip over the following shorted row; and pre-programming the remaining rows in the primary array.