Patent ID: 7626267
Filing Date: 2009-12-01
Classification: G03F,H01L

Abstract:
1. A semiconductor integrated circuit device comprising: trenches formed in a semiconductor substrate and defining an active region and dummy regions not functioning as an element; element isolation insulating films filled in the trenches, wherein the dummy regions are regularly arranged at a scribing area; wiring lines formed over the semiconductor substrate; dummy interconnections formed by the same level layer as the wiring lines, wherein the dummy interconnections are regularly arranged at the scribing area; a first interlayer insulating film formed over the wiring lines and over the dummy interconnections such that the surface of the first interlayer insulating film is flat; an external terminal formed the over first interlayer insulating film; a passivation film formed over the external terminal and over the first interlayer insulating film and having an opening over the external terminal; a bump electrode formed over the passivation film and electrically connected to the external terminal through the opening; and first interconnections formed the over first interlayer insulating film and formed by the same level layer as the external terminal, wherein the passivation film is formed over the external terminal and over the first interconnections such that the bump electrode is formed over the first interconnections.