Patent ID: 7719915
Filing Date: 2010-05-18
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including dynamic memory cells; a refresh request circuit generating an internal refresh request in a predetermined cycle; a chip enable terminal receiving a chip enable signal which is made valid when said memory cell array is accessed; an address valid terminal receiving an address valid signal indicating that an address signal indicating a memory cell to be accessed is supplied; a terminal which receives the address signal when the address valid signal has a valid level, and receives a data signal to be written into a memory cell when the address valid signal has an invalid level; an access detection circuit detecting an external access request when both said chip enable signal and said address valid signal have a valid level; and an arbiter determining which of said external access request and said internal refresh request is given priority, disabling reception of said internal refresh request in response to the detection by said access detection circuit, and enabling the reception of said internal refresh request in response to completion of a read operation or a write operation corresponding to the received chip enable signal and address valid signal.