Patent ID: 6765404
Filing Date: 2004-07-20
Classification: G01R,G05F,G11C

Abstract:
An integrated circuit, comprising:an array of memory cells formed on a substrate; and a circuit for setting a substrate voltage level, the circuit comprising: a first n-channel MOSFET having a first gate, a first drain, and a first source, wherein the first gate is coupled to the first drain and the first gate is coupled to a voltage reference level; a second n-channel MOSFET having a second gate, a second drain, and a second source, wherein the second gate is coupled to the second drain and the second gate is coupled to the first source; a third n-channel MOSFET having a third gate, a third drain, and a third source, wherein the third gate is coupled to the third drain and the third drain is coupled to the second source; a fourth n-channel MOSFET having a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate is coupled to be controlled by a first control voltage and the fourth drain is coupled to the third drain, and the fourth source is coupled to the third source; a fifth n-channel MOSFET having a fifth gate, a fifth drain, and a fifth source, wherein the fifth gate is coupled to the third gate and the fifth drain is coupled to the third source and the fifth source is coupled to the substrate; and a sixth n-channel MOSFET having a sixth gate, a sixth drain, and a sixth source, wherein the sixth drain is coupled to the fifth drain and the sixth source is coupled to the fifth source and the sixth gate is coupled to be controlled by a second control voltage.