Patent ID: 6073156
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A circuit comprising:(a) a multiplier comprising:a first and second input value terminal configured to respectively receive first and second signed input bit groups representing respective first and second signed values; anda sum and carry output terminal configured to carry respective sum and carry bit groups representing, in redundant form, a product of the first and second signed values;(b) a sign determining circuit configured generate a sign bit representing a sign of the product;(c) an extension unit comprising:a sum, sign, and carry input terminal configured to respectively receive a sum most significant bit, the sign bit, and a carry most significant bit;an extension output terminal configured to carry a replacement bit and an extension bit, the replacement bit having a same weight as the sum most significant bit, the extension unit structured such that the replacement bit has one binary state only if just one of the sum most significant bit and the carry most significant bit is a binary one, the extension unit structured such that the extension bit has one binary state only if the sign bit is a binary zero and the sum most significant bit and the carry most significant bit are the same.