Patent ID: 8518774
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A method of fabricating semiconductor memory cells comprising: forming a plurality of substantially parallel doped semiconductor active area lines in a first direction on and substantially parallel to a surface of a substrate, each active area line of the plurality having a first predefined width and separated from a neighboring active area line by a first predefined gap; forming a plurality of substantially parallel word lines in a second direction substantially perpendicular to the first direction above and substantially parallel to the surface of the substrate, each word line of the plurality having a second predefined width and separated from a neighboring word line by a second predefined gap; defining active areas in the active area lines for gate, source, and drain regions of each of a plurality of transistors formed by the active area lines and the word lines, wherein the active areas for gate regions are formed at spatially separated intersections of the active area lines and the word lines, wherein the active areas for source and drain regions are formed at spatially separated intersections of the active area lines and the second predefined gaps between neighboring word lines to provide substantially square contact areas for the active areas for source and drain regions, wherein the active areas for gate regions form channel regions in the active area lines, and wherein the active areas for gate regions are separated from respective word lines by insulative regions the thicknesses of which may be adjusted to optimize operation of the memory cells; and layering polycide and insulative regions on the word lines.