Patent ID: 6470484
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A method for including functionally extraneous cells on an integrated circuit die without significant adverse impact to logically functional cells of the integrated circuit comprising:defining the description of a first functionally extraneous cell for a layout tool so an initial area map of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell and so an output of the first functionally extraneous cell is defined at an intermediate hierarchical level as being connected to signal ground; and altering the description of the first functionally extraneous cell so that the output of the first functionally extraneous cell is defined at the intermediate hierarchical level as being disconnected from signal ground and so that the layout tool produces a second area map of the die that functionally couples said first functionally extraneous cell to said second functionally extraneous cell whereby the position of the second functionally extraneous cell with respect to a logically functional cell does not change between the first and second layouts.