Patent ID: 7738566
Filing Date: 2010-06-15
Classification: H04L

Abstract:
1. Circuit arrangement for use in a data transmission system, the circuit arrangement comprising: at least one input stage being connected downstream of at least one bus system, in particular of at least one C[ontroller]A[rea]N[etwork] bus system, the input stage comprising at least one resistive ladder for dividing the input signals, wherein the resistive ladder comprises two parallel resistor branches; and at least one amplifier stage connected downstream of the input stage, characterized in that the voltage range of the amplifier stage is limited to a defined maximum voltage, in particular to the supply voltage, wherein the input stage further comprises a divided bus system connected downstream of the resistive ladder, characterized in that the resistive ladder comprises at least six resistors determining the recessive level of the high branch of the bus system as well as the low branch of the bus system, in particular with the high branch of the divided bus system being connected between the first resistor and the second resistor, the high branch of the bus system being connected between the second resistor and the third resistor, the low branch of the divided bus system being connected between the fourth resistor and the fifth resistor, the low branch of the bus system being connected between the fifth resistor and the sixth resistor, the first resistor and the fourth resistor being connected on ground potential, and the third resistor and the sixth resistor being connected on supply voltage.