Patent ID: 6795357
Filing Date: 2004-09-21
Classification: G11C

Abstract:
A method of detecting a charge stored on a source charge storage region of a selected dual bit dielectric memory cell within an array of dual bit dielectric memory cells, the array comprising a plurality of parallel bit lines forming a source and a drain for each cell and a plurality of parallel word lines forming a gate for each cell, the method comprising:applying a source voltage to a first bit line that forms a source junction with a channel region of the selected memory cell, the channel region being to the right of the first bit line; applying a positive drain voltage to a second bit line that forms a drain junction with the channel region, the second bit line positioned to the right of the first bit line and separated from the first bit line by only the channel region; applying a positive read voltage to a selected one of the word lines, the selected one of the word lines being the word line that forms a gate of the selected memory cell; the read voltage being a positive voltage greater than the source voltage;applying a bias voltage to non-selected word lines, the non-selected word lines being the word lines other than the selected one of the word lines, the bias voltage being a negative voltage; and detecting current flow at the second bit line.