Patent ID: 6420233
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A method for fabricating a split gate field effect transistor comprising:providing a semiconductor substrate; forming upon the semiconductor substrate a gate dielectric layer; forming upon the gate dielectric layer a doped polysilicon floating gate electrode, the doped polysilicon floating gate electrode having a higher dopant concentration in a central annular portion of the doped polysilicon floating gate electrode than in a peripheral annular portion of the doped polysilicon floating gate electrode; forming over the doped polysilicon floating gate electrode an inter-gate electrode dielectric layer; forming over the inter-gate dielectric layer and covering at least a portion of the doped polysilicon floating gate electrode a control gate electrode; and forming into the semiconductor substrate a pair of source/drain regions which define within the semiconductor substrate a floating gate electrode channel with respect to the polysilicon floating gate electrode and an adjoining control gate electrode channel with respect to the control gate electrode.