Patent ID: 6996737
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. A method of delaying the counting of a number of occurrences of each of a plurality of events occurring in a processor complex having at least one processor until the disposition of an event has been determined, comprising the steps of: providing at least one array of memory storage for storing count information for each of the plurality of events; providing a plurality of separately addressable groups of memory addresses in each of the at least one array of memory storage; providing at least one counter associated with each array of memory storage; said at least one processor generating a plurality of counter parameters for each of the plurality of events, said counter parameters uniquely identifying each of the plurality of events, specifying a counter operation, and specifying one of the at least one counter for the operation; providing a means for altering the disposition of an event, said means enabled to modify said parameters; disposing a first event with the means for altering to create a first event disposition; the means for altering modifying or not modifying the parameters responsive to the first event disposition; and subsequently selecting an at least one counter and performing a counter operation on the selected counter responsive to the parameters.