Patent ID: 7855910
Filing Date: 2010-12-21
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a plurality of word lines; a plurality of bit lines; a plurality of plate lines corresponding to the plurality of bit lines on a one-to-one basis; a plurality of transistors; a plurality of electric elements corresponding to the plurality of transistors on a one-to-one basis; a word line driver for driving the plurality of word lines; and a bit line/plate line driver for driving the plurality of bit lines and the plurality of plate lines, wherein each of the plurality of transistors and one of the electric elements corresponding to the transistor are connected in series between any one of the plurality of bit lines and one of the plate lines corresponding to the bit line, each of the plurality of transistors is connected between one of the bit lines corresponding to the transistor and one of the electric elements corresponding to the transistor, the transistor having a gate connected to any one of the plurality of word lines, each of the plurality of electric elements includes the variable-resistance film includes Fe