Patent ID: 9105527
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A method for forming a plurality of devices on a substrate in a combinatorial manner, the method comprising: providing the substrate, wherein the substrate comprises a plurality of site-isolated regions, and wherein each site-isolated region further comprises one or more gate electrodes formed therein; depositing a gate dielectric layer above a surface of each site-isolated region; patterning the gate dielectric layer deposited above the surface of each site-isolated region; depositing a metal-based semiconductor layer above each gate dielectric layer, wherein the metal-based semiconductor layer comprises [X][Y]ZO, wherein [X] and [Y] each comprises one of Al, Ba, C, Ca, Cr, Cu, Fe, K, Mg, Mn, Mo, Na, Ni, Si, Sn, Sr, Ti, V, W, Zn, or Zr; patterning the metal-based semiconductor layer deposited above each gate dielectric layer; depositing an etch stop layer above each metal-based semiconductor layer; patterning the etch stop layer deposited above each metal-based semiconductor layer; depositing a source/drain layer above each etch stop layer; and patterning the source/drain layer deposited above each etch stop layer, wherein the patterning the metal-based semiconductor layer is varied in the combinatorial manner between at least two of the plurality of site-isolated regions.