Patent ID: 8022682
Filing Date: 2011-09-20
Classification: H02M,Y10S

Abstract:
1. A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage comprising high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit comprising: a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal; a resistor having a first terminal connected to a source of the high switch and a second terminal connected to a drain of the high switch and the common node; wherein a small current source pre-charges the output capacitor before a start of a PWM oscillation; wherein the first error amplifier turns ON the level switch when a voltage at the common node reaches the target output voltage.