Patent ID: 7856346
Filing Date: 2010-12-21
Classification: G06F

Abstract:
1. A method of testing a design of a data processing circuit having a plurality of bus masters connected via a shared bus to at least one bus slave, said method comprising the steps of: emulating by simulation with computer software a first bus master issuing a first bus access request to make a data transfer via said shared bus to a bus slave being emulated by simulation with computer software; emulating by simulation with computer software a second bus master issuing a second bus access request to make a data transfer via said shared bus to said bus slave; detecting if said first bus master has blocked access to said bus slave prior to said second emulating step, wherein, if said first bus master being emulated has blocked access to said bus slave, then refusing said second bus access request and, if said first bus master being emulated has not blocked access to said bus slave, then granting said second bus access request; and generating test results indicative of expected operation of said data processing circuit design in dependence upon whether said second bus access request was refused or was granted.