Patent ID: 6207980
Filing Date: 2001-03-27
Classification: H01L

Abstract:
In a semiconductor device having a plurality of pads and a plurality of I/O buffers, a method of laying out inter-I/O-pad wirings between the pads and the I/O buffers comprising steps of:arranging the plurality of I/O buffers in an I/O frame, wherein the plurality of I/O buffers includes a two pin I/O buffer having two I/O terminals that corresponds to two of the plurality of pads;arranging the plurality of pads in a pad region near the I/O frame;arranging the two I/O terminals that correspond to the two pads in the two pin I/O buffer, wherein each of the I/O terminals includes a generally horizontal terminal extending in the width direction of the two pin I/O buffer near the end of the two pin I/O buffer opposed to the pads and a vertical terminal extending in the lengthwise direction of the I/O buffer; andforming two inter-I/O-pad wirings extending toward and contacting the two pads, respectively, from one of the horizontal terminals and the vertical terminals thereof in accordance with a spacing of the two pads, respectively.