Patent ID: 6133762
Filing Date: 2000-10-17
Classification: H03K

Abstract:
A logic circuit family formed of metal oxide semiconductor field effect transistors comprising:a first supply voltage;a second supply voltage;an output node producing an output of said logic circuit;a plurality of logic circuits, each logic circuit includinga first series connection between said first supply voltage and said output node consisting ofa source-drain path of an N-channel transistor having a first threshold voltage, said N-channel transistor having a gate receiving a first logic input signal, said N-channel transistor not shared with other logic circuits of said plurality of logic circuits,a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a second threshold voltage lower than said first threshold voltage, said pull-down network receiving at least one second logic input signal which determines whether said pull-down conditional conduction path conducts or does not conduct; anda second series connection between said second supply voltage and said output node consisting ofa source-drain path of a P-channel transistor having said first threshold voltage, said P-channel transistor having a gate receiving an inverse of said first logic input signal, said P-channel transistor not shared with other logic circuits of said plurality of logic circuits,a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having said second threshold voltage, said pull-up network receiving at least one third logic input signal which determines whether said pull-up conditional conduction path conducts or does not conduct, said second and third logic input signals selected such that pull-down conditional conduction path and pull-up conditional conduction path do not conduct simultaneously.