Patent ID: 7235995
Filing Date: 2007-06-26
Classification: G01R

Abstract:
1. A test apparatus that tests a device under test, comprising: a main memory having an expectation pattern storing region storing an expectation pattern sequence to be sequentially compared with a plurality of output patterns sequentially output from a terminal of the device under test; a test pattern outputting unit for sequentially inputting a plurality of test patterns into the device under test; a capture unit for sequentially acquiring the output patterns into an output pattern storing region on said main memory in a first period of a cycle in an acquisition process; a memory reading unit for reading an output pattern sequence consisting of the plurality of acquired output patterns and the expectation pattern sequence from said main memory in a second cycle period of a cycle, when the acquisition process acquiring the output patterns into the output pattern storing region has been terminated; an expectation comparing unit for comparing the read expectation pattern sequence and the output pattern sequence in said second cycle period of a cycle; and a cycle period switching unit for setting said first period and second period in a way that said second period is larger than said first period.