Patent ID: 8283713
Filing Date: 2012-10-09
Classification: H01L

Abstract:
1. An electronic device, comprising: an active layer located over a substrate, the active layer including a logic circuit and an eDRAM cell; a first dielectric layer located on the active layer and a second dielectric layer located on the first dielectric layer; a first metallization level located on the first dielectric layer, the first metallization level including first logic interconnect lines on the first dielectric layer and a capacitor on the first dielectric layer, wherein the first logic interconnect lines are connected to the logic circuit through first logic contacts passing through the first dielectric layer and first and second metal capacitor plates of the capacitor are separately connected to the eDRAM cell through capacitor contacts passing through the first dielectric layer; and a second metallization level located on the second dielectric layer, the second metallization level including second logic interconnect lines on the second dielectric layer, wherein the second logic interconnect lines are connected to the logic circuit through second logic contacts passing though the second dielectric layer, and a bit line on the second dielectric layer that is connected to the eDRAM cell.