Patent ID: 7588948
Filing Date: 2009-09-15
Classification: H01L

Abstract:
1. A test structure for verifying an isolation trench etching in an SOI wafer, wherein the test structure in the SOI device comprises, after etching of isolation trenches, a row of islands, each of which is surrounded by a trench, said trenches having increasing trench width from one island to a next island and including a certain trench width of another isolation trench of an active circuit away from the test structure; wherein a portion of the surrounding trench (a,b) of each island shares a common portion with the surrounding trench of the adjacent island; wherein the respective common portion—except for an island having a broadest (e) or a narrowest (a) isolation trench—has the width of the adjacent surrounding trench having a next larger or a next smaller measure of width in the row.