Patent ID: 6060940
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A CMOS output stage, comprising:a complementary transistor pair including a first MOS power transistor and a second MOS power transistor each having a drain terminal, the pair connected between a power supply line and a ground, an output of the stage being formed at the drain terminals of the first and second transistors;a circuit connected to a gate terminal of the first MOS power transistor for setting a quiescent current of the output stage, the circuit including:a reference source having a reference current and including a reference transistor; anda current mirror;an additional MOS transistor connected to the current mirror; anda resistor connected between the additional MOS transistor and the ground,wherein the quiescent current is set by a channel geometry ratio of the second MOS power transistor and the reference transistor multiplied by the reference current, the second MOS power transistor being of the N-channel type.