Patent ID: 6074887
Filing Date: 2000-06-13
Classification: H01J,H01L

Abstract:
A method for fabricating a MOSFET-controlled FEA, which comprises the steps of:forming a first and a second n+-doped silicon layers over a p-type silicon substrate by diffusion of n+ ions;forming a buffer oxide layer over the first and the second n+-doped silicon layers and the p-type substrate by dry oxidation;depositing a silicon nitride layer over the buffer oxide layer by LPCVD and patterning the nitride film by RIE into a disc on the first n+-doped silicon layer;implanting boron ions over a selected region of the oxide layer that is spaced away from the first n+-doped silicon layer but located adjacent to the second n+-doped silicon layer to form a doped channel;oxidizing the buffer oxide layer to form a gate oxide layer except for the portion beneath the nitride disc;removing the nitride disc by acid and etching the buffer oxide layer beneath the nitride disc by RIE;isotropically etching the exposed portion of the first n+-doped silicon layer by RIE to form gate holes;depositing a metal perpendicularly over the silicon substrate to form a gate layer;depositing a parting material at a grazing angle to the gate layer to form a parting layer and depositing molybdenum perpendicularly with respect to the surface of the parting layer to form emitter tips;removing the parting layer selectively;patterning the gate layer into gate electrodes of the FEA and a gate electrode of the MOSFET.