Patent ID: 6778445
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A nonvolatile memory device comprising:a plurality of memory cell blocks that are selectively accessed, said memory cell blocks each including a plurality of memory cells arranged in a matrix and each having an electric resistance varying according to storage data written in nonvolatile manner by a data write current and a plurality of bit lines respectively provided correspondingly to memory cell columns; a plurality of row selection circuits respectively provided correspondingly to said plurality of memory cell blocks, said row selection circuits each selecting memory cell rows in a corresponding memory cell block; and peripheral circuitry for writing and reading data of multiple bits in parallel, said data being input/output to/from a data node, into and from at least a part of memory cells in the selected memory cell row, through at least a part of said plurality of bit lines in a selected memory cell block which is one of said plurality of memory cell blocks, said peripheral circuitry transmitting said data of multiple bits in the direction of said memory cell columns.