Patent ID: 6489646
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A DRAM device with buried trench capacitors, comprising:a semiconductor substrate with a first conductivity; a plurality of access transistors on said semiconductor substrate, each said access transistor with a second conductivity opposite to the first conductivity and having a conductive gate connected to a word line, a source region connected to a bit line, and a drain region; a plurality of trench isolation region in said semiconductor substrate and under said access transistors, wherein two said access transistors sharing one said source region are isolated between two pairs of neighboring trench isolation regions; a pair of neighboring buried trench capacitors under the pair of said neighboring trench isolation regions, each of said neighboring buried trench capacitors being aligned with one of the pair of said neighboring trench isolation regions, and a buried conductive strap with the second conductivity formed therebetween, said buried conductive strap being electrically coupled to said drain region of one of said two access transistors sharing one said source region, wherein each of said neighboring buried trench capacitors includes an oxide layer along an upper portion of the inner sidewall of said buried trench capacitor below said buried conductive strap, each said oxide layer opposite to each other within the pair of said neighboring buried trench capacitors, a dielectric layer along the other portion of the inner peripheral area of each said buried trench capacitor except for the upper portion covered by said oxide layer, a conductive layer with the second conductivity filled in each said buried trench capacitor between said buried conductive strap and said dielectric layer for serving as a first electrode of said buried trench capacitor electrically coupled to said drain region of said access transistor via said buried conductive strap, a diffusion region with the second conductivity around the surrounding of each said buried trench capacitor in said semiconductor substrate except for the portion of said semiconductor substrate covered by said oxide layer, the respective diffusion region of the pair of said neighboring buried trench capacitors being adjacent to each other, and an inversion layer on the interface between said dielectric layer and said semiconductor substrate and adjacent to said diffusion region, both of said diffusion region and said inversion layer serving as a second electrode of said buried trench capacitor; and a well with the second conductivity electrically coupled with each said diffusion region.