Patent ID: 8354873
Filing Date: 2013-01-15
Classification: H03K

Abstract:
1. A transmission gate, comprising: a PMOS transistor including a gate and a drain that receives an input voltage, and a source that outputs the input voltage; an NMOS transistor including a gate and a drain that receives the input voltage, and a source that outputs the input voltage; wherein a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage are the same for both the PMOS transistor and the NMOS transistor; a first level shifter for generating a first voltage from the input voltage; and a second level shifter for generating a second voltage from the input voltage, wherein the PMOS transistor is turned ON when the first voltage, obtained by subtracting a first predetermined voltage from the input voltage, is input to the gate of the PMOS transistor and the NMOS transistor is turned ON when a second voltage, obtained by adding a second predetermined voltage to the input voltage, is input to the gate of the NMOS transistor, wherein the first predetermined voltage is the sum of a first level shifter PMOS transistor threshold voltage and an overdrive voltage, and the second predetermined voltage is the sum of a second level shifter NMOS transistor threshold voltage and the overdrive voltage.