Patent ID: 6182187
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A computer system, comprising:a bus;a microprocessor for asserting cycles on said bus;a system ROM coupled to said bus for storing boot code including primary boot code for execution by said microprocessor upon power up of the computer system, other boot code and other system code, said system ROM comprising:a flash EPROM coupled to said bus and having an enable input, said flash EPROM for storing said other boot code and said other system code; anda ROM coupled to said bus and having an enable input, said ROM for storing said primary boot code; anda selector coupled to said microprocessor, said system ROM and said bus, said selector providing a first signal at an enabling value to said enable input of said ROM and a second signal at a disabling value to said enable input of said flash EPROM when a cycle is executed to said primary boot code and said selector providing a disabling value on said first signal and an enabling value on said second signal when a cycle is executed to said other boot code or said other system code.