Patent ID: 8952943
Filing Date: 2015-02-10
Classification: G09G

Abstract:
1. A scan driving apparatus comprising a plurality of sequentially arranged scan driving blocks, each of the scan driving blocks comprising: a first node configured to receive a first clock signal input to a first clock signal input terminal; a second node configured to receive an input signal according to a second clock signal input to a second clock signal input terminal; a first transistor having a gate electrode coupled to the first node, a first electrode configured to receive a power source voltage from a power source, and a second electrode coupled to an output terminal; a second transistor having a gate electrode coupled to the second node, a first electrode coupled to a third clock signal input terminal for receiving a third clock signal, and a second electrode coupled to the output terminal; a fifth transistor including a gate electrode configured to receive the input signal and a first electrode coupled to the first clock signal input terminal; and a sixth transistor coupled in series with the fifth transistor and including a gate electrode coupled to the second clock signal input terminal, a first electrode coupled to a second electrode of the fifth transistor, and a second electrode coupled to the first node, wherein each of the plurality of scan driving blocks is configured to receive the first, second, and third clock signals as corresponding three clock signals among four clock signals sequentially shifted by a first period, the four clock signals further comprising a fourth clock signal, and to output the third clock signal in synchronization with the input signal.