Patent ID: 6376297
Filing Date: 2002-04-23
Classification: G11C,H01L

Abstract:
A method of fabricating an SRAM memory cell comprising the steps of:providing a substrate assembly having at least one semiconductor layer; forming a first semiconductor structure within said at least one semiconductor layer; coupling said first semiconductor structure to a first voltage input through a first contact formed within said semiconductor structure; forming a first pull-up transistor in said first semiconductor stricture, said first pull-up transistor comprising a first gate, a first source and a first drain; coupling said first source to said first semiconductor structure through a second contact formed within the semiconductor structure so as to couple said first source to said first voltage input through a combined parasitic resistance of said semiconductor structure; configuring said first source of said first pull-up transistor, said first semiconductor structure, and said semiconductor layer to form a first parasitic bi-polar transistor including a base; coupling said base of said first bi-polar transistor to said second contact through a first component of said combined parasitic resistance and to said first contact through a second component of said combined parasitic resistance, wherein said first and second components of said combined parasitic resistance are connected in series; arranging said first pull-up transistor such that said first drain is positioned between said first source and said second contact along a surface of said semiconductor structure; forming a first pull-down transistor in said at least one semiconductor layer, said first pull-down transistor comprising a second gate coupled to said first gate, a second source coupled to a second voltage input, and a second drain coupled to said first drain.