Patent ID: 7095116
Filing Date: 2006-08-22
Classification: H01L

Abstract:
1. A semiconductor wafer having an active surface, comprising: a plurality of dice, each die having a plurality of contact pads formed on the active surface of the wafer; a passivation layer disposed on said active surface, said passivation layer having a plurality of passivation layer vias formed therethrough and associated with at least a portion of said plurality of contact pads; a resilient layer disposed on said passivation layer, said resilient layer having a plurality of resilient layer vias formed therethrough, wherein all sidewalls of at least some of said plurality of resilient layer vias are fully tapered from the top to the bottom of said resilient layer at substantially non-vertical angle relative to the active surface of said wafer, and wherein at least a portion of said plurality of passivation layer vias define a perimeter that completely encloses the perimeter of a corresponding resilient layer via; a plurality of under bump metallization stacks, each under bump metallization stack including a nickel-vanadium layer and a copper layer, wherein the nickel-vanadium layer is directly atop and in substantial contact with an associated contact pad and the copper layer is directly atop and in substantial contact with the nickel-vanadium layer, said under bump metallization stack being arranged such that at least some portion of the under bump metallization stack overlies a portion of said resilient layer; and a plurality of solder bumps, each solder bump being formed on an associated under bump metallization stack.