Patent ID: 7714424
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A stacked semiconductor chip module comprising: a first substrate of insulating material having a first and second major surface, said first substrate being formed with: external connection terminals arranged on said second major surface; a first semiconductor chip secured on an inner area of said first major surface; first connection points arranged on an outer area of said first major surface; first conduction lines electrically connecting said first connection points with the corresponding external connection terminals, respectively; and second conduction lines formed on said first major surface so as to electrically connect said first connection points with corresponding electrodes formed on said first semiconductor chip, respectively; a second substrate of insulating material closely spacedly stacked on said first substrate, said second substrate being formed with: a second semiconductor chip secured on an inner area of a major surface of the second substrate; second connection points arranged on an outer area of said major surface of the second substrate; and third conduction lines formed on said major surface of the second substrate so as to electrically connect said second connection points with corresponding electrodes formed on said second semiconductor chip, respectively; and interconnection members disposed between said first and second substrates so as to electrically connect the first and second substrates so as to electrically connects the first connection points with the corresponding second connection points, respectively, wherein electrical signals applied to said external connection terminals are transmitted through the corresponding first conduction lines to the corresponding first connection points, respectively, wherein the electrical signals are diverged at said first connection points, one of which are transmitted to said first semiconductor chip via said second conduction lines, another of which are transmitted to said second semiconductor chip via said interconnection members, said second connection points and said third conduction lines, respectively, wherein at each signal path a path between the first connection point and the end portion of the second conduction line which is connected to the corresponding electrode on the first semiconductor chip has an electric length substantially equal to that of a path between the second connection point and that end portion of the third conduction line which is connected to the corresponding electrode on the second semiconductor chip.