Patent ID: 8139387
Filing Date: 2012-03-20
Classification: G11C,H01L

Abstract:
1. An erasing method of a nonvolatile memory device including a first nonvolatile memory including a first substrate having first and second impurity regions of a first type, and a first channel region and a first gate stacked structure disposed on the first channel region; and a second nonvolatile memory including a second substrate having first and second impurity regions of a second type, different from the first type, and a second channel region and a second gate stacked structure disposed on the second channel region, the first and second nonvolatile memories having a complementary relationship, upper surfaces of the first and second nonvolatile memories being contiguous, the method comprising: applying a voltage difference to first and second impurity regions of at least one of the first and second nonvolatile memories such that there is an electric potential difference therebetween; and erasing data written in the at least one of the first and second nonvolatile memories by applying an erase voltage to a corresponding gate stacked structure in the at least one of the first and second nonvolatile memories, wherein applying the voltage difference includes applying a first voltage difference between the first and second impurity regions of the second type such that there is a first electric potential difference therebetween, and erasing data includes erasing data written in the second nonvolatile memory by applying a first erase voltage to the second gate stacked structure.