Patent ID: 6218282
Filing Date: 2001-04-17
Classification: H01L,Y10T

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a substrate with active regions;forming an interconnection system comprising:a first patterned metal layer, over the substrate, having metal features electrically connected to the active regions by contacts;a plurality of patterned metal layers over the first patterned metal layer terminating with an upper most patterned metal layer, each patterned metal layer having metal features electrically connected to metal features of different patterned metal layers by vias; andan inter-layer dielectric between each of the plurality of patterned metal layers;removing the inter-layer dielectrics; anddepositing tungsten (W) to form a liner directly on the metal features and vias by chemical vapor deposition leaving substantially continuous air gaps throughout the interconnection system.