Patent ID: 8411309
Filing Date: 2013-04-02
Classification: H04L

Abstract:
1. An integrated circuit comprising: a plurality of IP (Intellectual Property) cores; and a plurality of intermediary circuits that are each connected to one IP core among the plurality of IP cores, and that relay, using an NoC (Network On Chip) scheme, packets which are transmitted/received between the IP cores, wherein the plurality of intermediary circuits are connected to each other, and wherein each of the plurality of intermediary circuits replaces, when the intermediary circuit has received a plurality of flow-control packets which are each transmitted from one IP core to another IP core in order to notify the other IP core of free-space information of a data buffer which the one IP core has, in a case where destinations of the plurality of flow-control packets are the same IP core, the plurality of flow-control packets with one flow-control packet including the free-space information included in the individual flow-control packets, and transmits the one flow-control packet to the IP core which is the destination.