Patent ID: 6128720
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A data processing system, comprising:a first memory for storing a first group of instructions and a first group of data;a first control unit, including a multiplexer means, coupled to the first memory, for fetching first instructions and first data from the first memory;said first instructions each including a tag portion which determines how the instruction is to be executed at a processor, a topology configuration value, and an opcode portion;said first data including a first unit of data and a second unit of data;a plurality of first processor elements coupled to the first control unit by means of a first data bus and a first instruction bus, each of the processor elements having a unique identity value enabling a unique one of more than two interpretations of said instructions depending on the identity value of a processor element;each of the first processor elements including an instruction decode coupled to the first instruction bus, for processing said unique identity value thereof with said tag portion of a particular one of the first instructions received on the instruction bus to determine how the instruction is to be executed at the processor;each of the first processor elements further including a general purpose register file coupled to the first data bus and coupled to the instruction decode therein, for selectively buffering either said first unit of data or said second unit of data received on the first data bus in response to said instruction decode thereof determining how said particular instruction is to be executed at the processor;each of the first processor elements further including an arithmetic element coupled to the first data bus and coupled to the instruction decode therein, for performing custom execution of said particular one of the first instructions in response to said instruction decode thereof determining how said particular instruction is to be executed at the processor;said multiplexer means receiving said topology configuration value in said first instructions, for selectively broadcasting said first instructions to selected combinations of said first processor elements in response to said topology configuration value;each of the first processor elements further including a mode register coupled to said first instruction bus, for receiving said topology configuration value in said first instructions;each of the first processor elements further including an interconnection switch coupled to an interprocessor link and to said mode register thereof, for selectively interconnecting a first one of said processor elements to another one of said processor elements in response to said topology configuration value in said first instructions;said plurality of first processors being arranged into a first folded mesh or alternately into a second folded mesh, in response to said topology configuration value in said first instructions, andmeans in each respective processing element for executing the instruction to send result data in a customized direction to another one of said processor elements in the array, in response to said instruction decode thereof determining how said particular instruction is to be executed at the processor.