Patent ID: 8015230
Filing Date: 2011-09-06
Classification: G06F

Abstract:
1. A zero determiner for an adder, comprising: a plurality of logic circuits, wherein each logic circuit corresponds to a respective bit position of a result of the adder, and wherein a first logic circuit of the plurality of logic circuits corresponds to a least significant bit of the result and comprises: wherein each remaining logic circuit of the plurality of logic circuits comprises: a second XOR logic gate and a second XNOR logic gate coupled to receive a respective bit from the respective bit position of each operand and generate a second XOR result and a second XNOR result, a second OR logic gate and a NOR logic gate coupled to receive a respective less significant bit adjacent to the respective bit position of each operand and generate a second OR result and a NOR result, a third AND logic gate coupled to receive the second XOR result and the second OR result and generate a third AND result, a fourth AND logic gate coupled to receive the second XNOR result and the NOR result and generate a fourth AND result, and a third OR logic gate coupled to receive the third and fourth AND results and generate a second output signal; and wherein each first and second output signal is indicative of whether a zero result occurs in the respective bit position of the result responsive only to inputs that the logic circuit is coupled to receive as recited previously; and a second logic circuit coupled to receive the output signals from the plurality of logic circuits and configured to generate a zero sum signal indicative, when asserted, that a zero result occurs for the adder, and wherein the second logic circuit is configured to assert the zero sum signal responsive to each of the output signals indicating zero.