Patent ID: 6437990
Filing Date: 2002-08-20
Classification: H01L,H05K

Abstract:
An IC BGA package comprising:a. a first printed wiring board (first PWB) having an upper surface and a lower surface, a first array of BGA bond pads on the upper surface, and a second array of BGA bond pads on the upper surface, the second array of BGA bond pads spaced from the first array of BGA bond pads, and the BGA bond pads having a thickness B1, b. a second printed wiring board (second PWB) having an upper surface and a lower surface, and comprising: i. a first array of BGA bond pads with thickness B2 on the lower surface, ii. a second array of BGA bond pads with thickness B2 on the lower surface, the second array of BGA bond pads spaced from the first array of BGA bond pads, thereby forming a BGA gap therebetween, iii. an IC chip attached to the upper surface of the second PWB, iv. an array of IC chip wire bond pads on the IC chip, v. a first array of upper surface PWB wire bond pads on the upper surface of the second PWB at least partially surrounding the IC chip, vi. a second array of upper surface PWB wire bond pads on the upper surface of the second PWB at least partially surrounding the IC chip, vii. a third array of upper surface PWB wire bond pads on the upper surface of the second PWB at least partially surrounding the IC chip, viii. an array of solder bump pads on the lower surface of the second PWB, the solder bump pads having a thickness U1, ix. a first plurality of wire bonds interconnecting the first array of IC chip wire bond pads and the first array of upper surface PWB bond pads, x. a second plurality of wire bonds interconnecting the second array of IC chip wire bond pads and the second array of upper surface PWB bond pads, xi. a third plurality of third wire bonds interconnecting the third array of IC chip wire bond pads and the third array of upper surface PWB bond pads, xii. a first plurality of BGA interconnection vias through the second PWB, xiii. a second plurality of BGA interconnection vias through the second PWB, xiv. a plurality of chip interconnection vias through the second PWB, xv. first upper surface metallization means for interconnecting the first plurality of BGA interconnection vias and the first array of upper surface PWB wire bond pads, xvi. second upper surface metallization means for interconnecting the second plurality of BGA interconnection vias and the second array of upper surface PWB wire bond pads, xvii. third upper surface metallization means for interconnecting the chip interconnection vias and the third array of upper surface PWB wire bond pads, xviii. first lower surface metallization means for interconnecting the plurality of chip interconnection vias with the solder bump pads, xix. at least two IC chips each having a thickness less than T, and each having an array of solder bump pads having a thickness U2, c. a first array of BGA solder balls bonding the first array of BGA bond pads on the first PWB to the first array of BGA bond pads on the second PWB, and a second array of BGA solder balls bonding the second array of BGA bond pads on the first PWB to the second array of BGA bond pads on the second PWB, the first array of BGA solder balls and the second array of BGA solder balls having a height H, d. an array of solder bumps with height M bonding the array of solder bump pads on the IC chip to the array of solder bump pads on the lower surface of the second PWB, with U1, U2, M, T, B1, B2, and H related by: H+B1+B2&gE;T+M+U1+U2.