Patent ID: 6686780
Filing Date: 2004-02-03
Classification: H03K

Abstract:
A frequency divider comprising:a plurality of serially-connected data storage units which temporarily hold data input based, on control by an input control signal, wherein data output from each storage unit is input into an immediately subsequent storage unit; a clock inversion circuit which is supplied with an output of a final data storage unit of said plurality of data storage units and a clock signal of original oscillation, which inverts logic of the clock signal at a change of the output of said final data storage unit to produce a logic inverted clock signal, and which supplies the logic inverted clock signal to odd-numbered data storage units and even-numbered data storage units of said plurality of data storage units in a complementary manner as the input control signal; and an inversion-delay circuit comprising a delay processing circuit which delays the output of the said final data storage unit for a predetermined time, a delay selection circuit for selecting one of (i) the output of said final data storage unit delayed by said delay processing circuit and (ii) the output of said final data storage unit, and an inverter receiving and inverting the signal selected by said delay selection circuit and inputting the signal inverted to a data input of a first data storage unit of said plurality of data storage units, wherein said inversion-delay circuit selectively outputs the clock signal (i) by N and (ii) divided by Nâˆ’2, where N is an odd integer and at least 3.