Patent ID: 6088267
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:an array of memory cells arranged in a matrix of rows and columns;a plurality of word lines commonly connected to gates of said memory cells arranged in a row direction of said array; anda row decoder circuit including a logic circuit and a word line driver circuit connected to first and second potential nodes, said logic circuit decoding a select signal, and said word line driver circuit applying to a selected word line a negative voltage supplied to said second potential node during an erase mode and a positive voltage supplied to said first potential node during a write node,wherein during the erase mode, said row decoder circuit selects said word line connected to a memory cell to be erased in accordance with the select signal decoded by said logic circuit, applies the negative voltage to the selected word line via a N-channel transistor included in said word line driver circuit, and applies to said first potential node a potential less than the positive voltage.