Patent ID: 6202129
Filing Date: 2001-03-13
Classification: G06F

Abstract:
A computer system having cache memory management, the computer system comprising:a main memory;a processor coupled to said main memory, said processor to execute instructions to process non-temporal data and temporal data;at least one cache memory coupled to said processor, said at least one cache memory having at least two cache ways, each of said at least two cache ways comprising a plurality of sets of data stored in said at least one cache memory, each of said plurality of sets of data having a first bit and a second bit in said at least one cache memory, said first bit of each of said plurality of sets of data to indicate whether one of said at least two cache ways in the associated set of data contains said non-temporal data that can be replaced first, said non-temporal data being infrequently used by the processor, said second bit indicative of an order of data entry in a corresponding way; andwherein said processor accesses data from one of said main memory or said at least one cache memory.