Patent ID: 8749291
Filing Date: 2014-06-10
Classification: G09G

Abstract:
1. A semiconductor integrated circuit comprising: a substrate on which semiconductor circuit elements are formed; an output terminal formed on the substrate, the output terminal being connected to an external load; an internal signal line formed on the substrate, the internal signal line connecting the output terminal to an internal node; a voltage generator formed on the substrate, for generating a voltage and supplying the voltage to the internal node for output through the internal signal line and the output terminal to the external load; a voltage attenuating element formed on the substrate and connected to the internal signal line, for attenuating voltage swings on the internal signal line; a voltage limiting circuit formed on the substrate and connected to the internal node, for limiting the voltage at the internal node to a predetermined range if, after attenuation of the voltage swings by the voltage attenuating element, the voltage at the internal node exceeds the predetermined range; a first power supply node for receiving a first power supply voltage; a second power supply node for receiving a second power supply voltage higher than the first power supply voltage; and a third power supply node for receiving the first power supply voltage, wherein the voltage attenuating element includes a well formed in the substrate, the well being electrically connected in series with the internal signal line, the voltage limiting circuit is electrically connected to the first power supply node and the second power supply node and the predetermined range extends from the first power supply voltage to the second power supply voltage, and the third power supply node is electrically connected to the substrate at such a distance from the well that the substrate produces at a predetermined electrical resistance between the third power supply node and the well.