Patent ID: 6303421
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of manufacturing a CMOS sensor, comprising the steps of:providing a substrate having a first conductive type, wherein the first conductive substrate comprises an isolation region and an active region;forming a gate structure on the active region;forming a lightly doped drain region having a second conductive type in the substrate exposed by the gate structure and the isolation region;forming a spacer on the sidewall of the gate structure;forming a heavily doped region having a second conductive type in the substrate exposed by the gate structure, the spacer and the isolation region, wherein the lightly doped drain region and the heavily doped region constitute a source/drain region;forming a patterned photoresist over the substrate to expose a portion of the source/drain region between the spacer and the isolation region;forming a first doped region having the second conductive type across a portion of the source/drain region and extending from the surface of the substrate into the substrate;forming a second doped region having the first conductive type to wrap the first doped region and to isolate the first doped region from the isolation region;forming a third doped region having the second conductive type between the first doped region and the second doped region, wherein a portion of the second doped region is compensated by the first and the third doped regions;forming a fourth doped region having the first conductive type under the second doped region; andremoving the patterned photoresist.