Patent ID: 8107303
Filing Date: 2012-01-31
Classification: G11C

Abstract:
1. A semiconductor device comprising: a first control circuit; a second control circuit; a transistor, the transistor being a p-type transistor, a gate of the transistor being electrically connected to the first control circuit through a first word line, and one of a source and a drain of the transistor being electrically connected to the second control circuit through a bit line, and a memory element, a first terminal of the memory element being electrically connected to the other of the source and the drain of the transistor, and a second terminal of the memory element being electrically connected to the first control circuit through a second word line, wherein: the first control circuit is configured to supply a first potential to the gate of the transistor through the first word line, the second control circuit is configured to supply a second potential to the one of the source and the drain of the transistor through the bit line, the first control circuit is configured to supply a third potential to the second terminal of the memory element through the second word line, the third potential at a time of data writing is negative potential, and a potential difference between the second potential and the third potential at the time of data writing is larger than a withstand voltage of the transistor.