Patent ID: 8259505
Filing Date: 2012-09-04
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: one or more reference cell transistors; one or more memory cell transistors; and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and said another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors, wherein the current source circuit further includes two or more additional field effect transistors having two or more gates thereof connected to the gates of the three or more field effect transistors, and some of the two or more additional field effect transistors are selected in response to a code applied to the nonvolatile memory device from an external source, currents flowing through the selected some of the two or more additional field effect transistors being combined with the currents flowing through the two or more field effect transistors to flow through the one or more reference cell transistors.