Patent ID: 6774495
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A solder terminal structure, comprising:a plurality of electrode pads exposed through an insulating layer on a surface of a semiconductor device chip; an adhesion metal layer formed on the electrode pads and on the insulating layer adjacent to the electrode pad, wherein the adhesion metal layer comprises Al or Al alloy material: a thermal diffusion barrier formed on the adhesion metal layer, wherein the thermal diffusion barrier comprises a TiW or Ti alloy material; a solder bonding layer formed on the thermal diffusion barrier, wherein the solder bonding layer is comprises a NiV material; and a solder bump formed on the solder bonding layer, wherein the thermal diffusion barrier does not substantially reach with either the electrode pad, the solder bump during a solder reflow process or a high-temperature semiconductor reliability test.