Patent ID: 8321729
Filing Date: 2012-11-27
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: A. logic circuitry having a first pattern of logic stimulus inputs and a second pattern of logic response outputs; B. a scan in lead and a scan out lead; and C. a scan path of serially connected scan cells, the scan path having an input connected to the scan in lead, an output connected to the scan out lead, a third pattern of scan stimulus parallel outputs connected from the scan cells to the first pattern of logic stimulus inputs, and a fourth pattern of scan response parallel inputs connected to the scan cells from the second pattern of logic response outputs to carry a known stimulus and response test pattern in the scan path to and from the logic circuitry, the scan path being divided into segments of scan cells, each segment having a scan input connected to the scan in lead, a separate scan enable input, a separate scan clock input, a separate scan output, stimulus parallel outputs, response parallel inputs, and a tristate output buffer selectively coupling the separate scan output with the scan out lead, and each segment maintaining the third pattern of stimulus parallel outputs connected to the first pattern of logic stimulus inputs and the fourth pattern of response parallel inputs connected to the second pattern of logic stimulus outputs; and D. decode logic circuitry having a scan clock input, a scan enable input, at least one binary control input, and, for each segment, a separate scan clock output and a separate scan enable output.