Patent ID: 7282958
Filing Date: 2007-10-16
Classification: H03K

Abstract:
1. A multiplex (MUX) circuit, comprising: a first buffer unit for receiving an inverted version of a first input signal to generate a first buffer unit output signal; a first switch for transmitting the first buffer unit output signal in response to a selection signal; a first inverter for receiving the first input signal to generate a first inverter output signal; a second switch for transmitting the first inverter output signal in response to the selection signal; a second inverter for receiving a second input signal to generate a second inverter output signal; a third switch for transmitting the second inverter output signal in response to the selection signal; a third inverter receiving the first inverter output signal from the second switch and the second inverter output signal from the third switch to generate a third inverter output signal; a second buffer unit for receiving an inverted version of the second input signal to generate a second buffer unit output signal; and a fourth switch for transmitting the second buffer unit output signal in response to the selection signal, wherein the first buffer unit output signal, third inverter output signal and second buffer unit output signal are combined at an output of the third inverter as a MUX circuit output signal.