Patent ID: 9012281
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a substrate including a first region having a first gate electrode and a first source/drain region disposed adjacent the first gate electrode, and a second region having a second gate electrode and a second source/drain region disposed adjacent the second gate electrode; forming an etch stop layer on the first and second source/drain regions of the first and second regions; forming an interlayer insulating film on the etch stop layer; etching the interlayer insulating film to expose portions of the etch stop layer in the first and second regions; forming a resist layer on the second region; etching the etch stop layer and an underlying portion of the first source/drain region in the first region using the resist layer as a mask to form a first contact hole having a first depth in the first source/drain region; concurrently forming a first silicide region in the first contact hole and a sacrificial silicide region on the etch stop layer in the second region; forming a second contact hole having a second depth different from the first depth in the second source/drain region by removing the sacrificial silicide region, a portion of the etch stop layer, and an underlying portion of the first source/drain region in the second region; and forming a second silicide region in the second contact hole.