Patent ID: 6265739
Filing Date: 2001-07-24
Classification: G11C,H01L,Y10S

Abstract:
A non-volatile semiconductor memory device comprising:a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a semiconductor substrate in which data is programmed and erased by charging and discharging the charge storing layer;a plurality of select transistors each connected to a corresponding one of the memory cell units; andfirst and second transistors each for controlling a voltage to be applied to at least one of the memory cells and the select transistor connected thereto, the first transistor having a first gate insulating film, and the second transistor having a second gate insulating film with a different thickness from the first gate insulating film,wherein a gate insulating film incorporated in the memory cell, a gate insulating film incorporated in the select transistor and the first gate insulating film are formed of substantially the same film.