Patent ID: 6353879
Filing Date: 2002-03-05
Classification: G06F

Abstract:
Apparatus for data processing, said apparatus comprising:(i) a memory for storing data at mapped addresses within said memory; (ii) a processor core for requesting a memory access to a virtual address within said memory; (iii) an address translation circuit for performing a translation of said virtual address to a mapped address in accordance with a current address mapping prediction, wherein said address translation circuit has a translation mode which replaces a bit field within said virtual address with a bit field specified by said address mapping prediction, and a transparent mode in which said bit field within said virtual address is passed unaltered; (iv) a memory accessing circuit for accessing data from said memory using said mapped address; and (v) a mapping validity circuit for determining if said translation is valid for use in said memory access; wherein (vi) said mapping validity circuit does not determine if said translation is valid until after said memory accessing circuit has commenced said memory access; and further comprising (vii) an abort circuit for aborting said memory access if said translation is invalid; and (viii) a restart circuit for restarting said memory access with a valid translation of said virtual address to a valid mapped address, wherein said mapping validity circuit compares for equality said bit field within said virtual address of a current memory access with a predetermined bit field to produce an equality result and, if said equality result differs from that of a predicted result, swaps between said translation mode and said transparent mode.