Patent ID: 9012272
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method for manufacturing a MOSFET, comprising: providing an SOI wafer comprising a semiconductor substrate, a first buried insulating layer, a first semiconductor layer, a second buried insulating layer and a second semiconductor layer from bottom to top; forming a back gate in the first semiconductor layer; forming source/drain regions in the second semiconductor layer; forming a gate on the second semiconductor layer; and providing electrical connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoin the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions, and wherein the electric connections to the source/drain regions comprise conductive vias in contact with the source/drain regions, and one of the first back gate regins shares a common conductive via with one of the source/drain region.