Patent ID: 7183156
Filing Date: 2007-02-27
Classification: H01L

Abstract:
1. A method for fabricating a transistor structure, comprising: providing a gate dielectric layer on at least a portion of a surface of a semiconductor substrate; applying a base layer of a conductive material to the gate dielectric layer; patterning the base layer so as to produce a base portion of a gate conductor structure; providing a first side wall oxide on a first side wall of the base portion and a second side wall oxide on a second side wall of the base portion, wherein the first and second side walls are substantially vertical with respect to the substrate surface, and wherein the second side wall opposes the first side wall; applying a conformal mask layer from a mask material having an etching resistance that can be altered by dopant implantation; altering the etching resistance of portions of the conformal mask layer by an α-oblique implantation on the first side wall and/or in the gate dielectric layer; selectively causing unaltered portions of the conformal mask layer to recede with respect to the altered portions of the conformal mask layer to produce a mask that covers at least the second side wall but not said first side wall; and growing the first side wall oxide and the second side wall oxide from conductive material of the base portion by an oxidation process that is controlled asymmetrically by said mask to produce the first side wall oxide and the second side wall oxide such that the first side wall oxide has a greater layer thickness than the second side wall oxide.