Patent ID: 6557151
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A method of performing a distributed static timing analysis of a network of logic circuits comprising interconnected predecessor nodes and successor nodes, wherein predecessor nodes provide signals characterized by timing values to successor nodes, said method comprising the steps of:partitioning said network into a plurality of partitions, each partition comprising a subset of said predecessor and successor nodes; executing a separate timing analysis process for each of said partitions, each of said processes executing substantially in parallel; and issuing, to at least a first of said processes corresponding to a first partition containing a successor node, a first request for timing information for said successor node, wherein said first request initiates a depth-first search (DFS) on predecessor nodes of said successor node to respond to said first request, said DFS recursively executing on each of said predecessor and successor nodes only once for said first request, and wherein computation and propagation of timing values are performed subsequently to said DFS.