Patent ID: 8198930
Filing Date: 2012-06-12
Classification: G06F,H03H,H03K

Abstract:
1. An integrated circuit comprising, a first chain of clock buffers, wherein each clock buffer in the first chain receives a first supply voltage from a first voltage source, wherein a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers; and a second chain of clock buffers coupled in series with the first chain of clock buffers, wherein each clock buffer in the second chain is coupled to the first voltage source through coupling circuitry between the first voltage source and the second chain of clock buffers, such that the change in the first supply voltage causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.