Patent ID: 6965986
Filing Date: 2005-11-15
Classification: G06F

Abstract:
1. Apparatus for implementing two-tiered thread state multithreading support with a high clock rate comprising: a first tier thread state storage for storing a limited number of runnable thread register states; said limited number being less than a threshold value; next thread selection logic coupled between said first tier thread state storage and a currently executing processor state for picking a next thread to run on a processor from said limited number of runnable thread register states; a second tier thread storage facility for storing a second number of thread states; said second number of thread states being greater than said limited number of runnable thread register states; a runnable thread selection logic coupled between said first tier thread state storage and said second tier thread storage facility for exchanging thread states between said first tier limited number of runnable thread register states and said second tier thread storage facility; said runnable thread selection logic identifies a processor stall condition; evaluates a status of all threads; and checks for an optimum set of threads occupying said runnable thread register states.