Patent ID: 9015352
Filing Date: 2015-04-21
Classification: G06F,Y02D

Abstract:
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising: a functional unit configured to perform a digital operation; one or more multiplexers coupled to the memory bus; a configurable data path configurably coupled to the one or more multiplexers and the functional unit, the configurable data path configured in response to a first configuration information to provide a data path configuration by configuring interconnections between the one or more multiplexers and the functional unit; wherein the one or more multiplexers are coupled to the memory bus and the configurable data path, each of the one or more multiplexers configured in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration.