Patent ID: 7405974
Filing Date: 2008-07-29
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory array of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held; a page buffer circuit connected to a main bus via a first port and to an internal bus via a second port, containing multiple page planes; an access control circuit operating either in a user mode or in a memory control mode as determined by a control signal, enabling access to the page planes over the main bus when in the user mode and over the internal bus when in the memory control mode; an interface circuit connected to the main bus and the page buffer circuit, generating the control signal to assign the page planes to the user mode and the memory control mode in accordance with a command received over the main bus; and a memory control circuit controlling at least write operation to the memory array, connected to the page buffer circuit over the internal bus and accessing the page buffer circuit in the memory control mode.