Patent ID: 6421266
Filing Date: 2002-07-16
Classification: G11C

Abstract:
A sense-amplifier block for a memory device having a bi-level architecture memory array and first, second and third conductive layers, the sense-amplifier block comprising:N digit line pairs coupled to and passing through and out of the sense-amplifier block: M sense-amplifier circuits disposed in a first region and coupled to the N digit line pairs through first and second conductive layers, M being no more than N-1, each of the M sense-amplifier circuits coupled to no more than one of the N digit line pairs; X digit line pairs coupled to and passing through and out of the sense-amplifier block; Y sense-amplifier circuits disposed in a second region and coupled to the X digit line pairs through the first and second conductive layers, Y being no more than X-1, each of the Y sense-amplifier circuits coupled to no more than one of the X digit line pairs; N-M of the N digit line pairs being electrically isolated from the M sense-amplifier circuits and respectively coupled to the Y sense-amplifier circuits through a third conductive layer isolated from the first and second conductive layers; and X-Y of the X digit line pairs being electrically isolated from the Y sense-amplifier circuits and respectively coupled to the M sense-amplifier circuits through the third conductive layer.