Patent ID: 6426530
Filing Date: 2002-07-30
Classification: H01L,Y10S

Abstract:
A latch comprising two pairs of directly coupled vertical Field Effect Transistor (FETs), the drains of each said FET in one said pair being connected to drains of opposite conduction type FETs in the other, said two pairs forming cross coupled invertors, each said pair of directly coupled FETs comprising:a first stack of layered, epitaxially grown silicon, said first stack having a channel layer of a first conduction type between a pair of conducting terminal layers of a second conduction type, a second stack of layered, epitaxially grown silicon, said second stack having a channel layer of said second conduction type between a pair of conducting terminal layers of said first conduction type, a gate oxide layer of SiO2 separating said first and second stacks, and one of said conducting terminal layers of each of said first and said second stacks being at least as thick as the sum of the thickness of the channel layer and the thickness of the other of said conducting terminal layers of said second and first stacks, each said channel layer of each said stack having a surface facing said thicker conducting terminal layer of the other said stack and separated therefrom by said gate oxide so that said thicker conducting terminal layer of each said epitaxial stack is the gate of one FET of said pair of FETs.