Patent ID: 6477556
Filing Date: 2002-11-05
Classification: G06F,G06Q,H04L

Abstract:
An operation apparatus for calculating a remainder R of data Z having Bz bits divided by data I represented by a following equation: I=&Sum;N=0N=Nmax&it;â€ƒ&it;AN&it;QMN(M is a number of bits of a basic operational unit; N is a natural number being one of 0 through Nmax, A0 is a value whose absolute value is smaller than a value represented by the basic operational unit of M bits; each of A1 through ANmaxâˆ’1 is +1, 0, or âˆ’1; ANmax is +1, or âˆ’1; and Q is a natural number equal to or more than 2) the operation apparatus comprising:(1) a data Zl storing region for storing data Zl of lower MÃ—Nmax bits of the data Z; (2) a data Zh storing region for storing data Zh of higher (Bzâˆ’MÃ—Nmax) bits of the data Z; (3) a data AN storing region for storing the data AN; and (4) an addition/subtraction unit for calculating the remainder R by determining an operation between addition and subtraction based on positive/negative of the data AN, and operating addition/subtraction of data stored in at least a part of the data Zl storing region and data stored in at least a part of the data Zh storing region.