Patent ID: 6161119
Filing Date: 2000-12-12
Classification: G06F

Abstract:
A scaling multiplier circuit for producing an 8-bit scaled product of two 8-bit numbers, comprising:a multiplier circuit that produces a 16-bit product of the two 8-bit numbers, the 16-bit product having bits referred to herein as bits m(15:0);a carry calculation circuit that produces a first carryout bit from a sum of a first number consisting of bits m(6:0), a second number consisting of bits m(14:8), and a third number consisting of bit m(7);a logic circuit that produces intermediate carryout bits from a sum of bit m(7), bit m(15), the first carryout bit, and a constant bit having a value of ""1"";an adder circuit that produces the scaled product by summing the intermediate carryout bits and a fourth number consisting of bits m(15:8).