Patent ID: 7183615
Filing Date: 2007-02-27
Classification: G11C,H01L,Y10T

Abstract:
1. A semiconductor memory having a memory cell matrix including a plurality of memory cell transistors serially arranged along row- and column-directions, the memory cell matrix comprising: a plurality of device isolation films having flat top surfaces, running along the column-direction, each of the device isolation films arranged alternately between the memory cell transistors aligned along the row-direction, a pair of edges of each of the top surfaces are respectively beveled obliquely so as to provide a pair of nonparallel slanting surfaces, establishing a regular-mesa shape of the device isolation films in a cross sectional view cut along the row-direction; a plurality of first conductive layers arranged along the row and column-directions, a group of the first conductive layers arranged along the column-direction are assigned to a corresponding cell column, adjacent cell columns are isolated from each other by the device isolation film, top surfaces of the first conductive layers lie at a lower level than the top surfaces of the device isolation films; an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so as to implement a level top on each of the device isolation films so that the inter-electrode dielectric can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns, relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films; and a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.