Patent ID: 7596772
Filing Date: 2009-09-29
Classification: G06F

Abstract:
1. A method for setup/hold time characterization for an analog IP including flip-flops of at least first and second levels, the method comprising steps of: inputting parameters by an input module, wherein the parameters comprise characterizations of input pin of the analog IP, clock pin connected to the flip-flops and destination block of the analog IP; extracting, by a path extraction module, critical paths from the analog IP for setup/hold time simulation; wherein the step of extracting critical paths includes a step of extracting data paths from the input pin of data pins to the flip-flop of the first level and extracting clock paths from the clock pin to the flip-flop of the first level; building, by a building module, a subcircuit subset (SCSS); merging, by a merge module, the extracted critical paths to the SCSS for generating a merged SCSS; generating a setup/hold time testbench according to the merged SCSS and running the setup/hold time testbench by a testbench generation and running module; and generating liberty libraries, by a library generation module, according to a result of running the setup/hold time testbench.