Patent ID: 8194817
Filing Date: 2012-06-05
Classification: G09G,G11C

Abstract:
1. A shift register circuit comprising: an input terminal, an output terminal, and a clock terminal; a first transistor for supplying said output terminal with a clock signal inputted to said clock terminal; a second transistor for charging a first node connected to a control electrode of said first transistor in response to activation of an input signal inputted to said input terminal; a third transistor for discharging said first node; an inverter supplied with a power supply of active level, using a second node connected to a control electrode of said third transistor as an output end; and a first unidirectional element for discharging a third node connected to an input end of said inverter when said power supply is inactive, said first unidirectional element being turned off when said power supply is active, wherein said inverter includes a load element for charging said second node when said power supply is active.