Patent ID: 7809971
Filing Date: 2010-10-05
Classification: G06F

Abstract:
1. A clock distribution circuit in a semiconductor integrated circuit that has a first sequential circuit which operates in accordance with a first clock signal distributed through a first branch node on a first clock distribution network, a second sequential circuit which operates in accordance with a second clock signal distributed through a second branch node on a second clock distribution network, and a data transfer path provided between said first sequential circuit and said second sequential circuit, comprising: a first PLL circuit configured to receive a first feedback clock signal that is said first clock signal branched at said first branch node, and to output said first clock signal to said first clock distribution network based on said first feedback clock signal and a first reference clock signal; and a second PLL circuit configured to receive a second feedback clock signal that is said second clock signal branched at said second branch node, and to output said second clock signal to said second clock distribution network based on said second feedback clock signal and a second reference clock signal, wherein a branch node is provided at least one of between an output of said first PLL circuit and said first branch node on said first clock distribution network and between an output of said second PLL circuit and said second branch node on said second clock distribution network, wherein said first branch node is closest to said first sequential circuit among a plurality of branch nodes on a first path from said first PLL circuit to said first sequential circuit.