Patent ID: 6717875
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array comprising a plurality of cells; a plurality of sense amplifiers coupled to respective bit lines and respective bit-bar lines of respective cells in the plurality of cells, each of the plurality of sense amplifiers having a first terminal and a second terminal; a control signal generating circuit, driven by a plurality of signals for sensing the cells of the memory cell array, to generate first-third control signals; first switching means, driven by the first control signal, for supplying the first terminals of the plurality of sense amplifiers with a power supply voltage. second switching means, driven by the second control signal, for supplying the second terminals of the plurality of sense amplifiers with a ground voltage; a charge recycling circuit, driven by a power-up signal and the third control signal, to supply the first terminals of the plurality of sense amplifiers with electric charges of a first given potential and to supply the second terminals of the plurality of sense amplifiers with electric charges of a second given potential, or to store the electric charges of the first terminals and to store electric charges of the second terminals, depending on operation of the plurality of sense amplifiers.