Patent ID: 6316956
Filing Date: 2001-11-13
Classification: H02J,H03K

Abstract:
A fault-tolerant integrated power circuit, comprising:a. a plurality of power transistors, each having a power source, each power source electrically coupled to a common source line, a power gate and a power drain, each power drain electrically coupled to a common drain line, the plurality of power transistors capable of driving a power current from the source line to the drain line;b. a first plurality of control transistors, each of the first plurality of control transistors having a first source, a first gate and a first drain, the first drain of each of the first plurality of control transistors being electrically coupled to a corresponding power gate of a different one of the power transistors;c. a first transistor control circuit that generates a first control signal, the first control signal being electrically coupled to each first gate of the first plurality of control transistors;d. at least a second plurality of control transistors each of the second plurality of control transistors having a second source, a second gate and a second drain, the second drain of each of the second plurality of control transistors being electrically coupled to a corresponding power gate of a different one of the power transistors;e. a second transistor control circuit that generates a second control signal, the second control signal being electrically coupled to each second gate of the second plurality of control transistors; andf. a plurality of current sources, each current source being electrically coupled to a different power gate of the plurality of power transistors so as to draw current in a predetermined direction relative the power gate; wherein the first transistor control circuit is spaced apart from the second transistor control circuit on the integrated circuit chip.