Patent ID: 6546461
Filing Date: 2003-04-08
Classification: G06F,G11C

Abstract:
A buffer memory device, comprising:a first quad-port cache memory device; a second quad-port cache memory device; an input bus electrically coupled to a first unidirectional input port of said first quad-port cache memory device and a first unidirectional input port of said second quad-port cache memory device; a first embedded memory array having a write port and a read port electrically coupled to a second unidirectional output port and third unidirectional input port of said first quad-port cache memory device, respectively; a second embedded memory array having a write port and a read port electrically coupled to a second unidirectional output port and a third unidirectional input port of said second quad-port cache memory device, respectively; and an output bus electrically coupled to a fourth unidirectional output port of said first quad-port cache memory and a fourth unidirectional output port of said second quad-port cache memory.