Patent ID: 6486506
Filing Date: 2002-11-26
Classification: H01L

Abstract:
An integrated circuit including a plurality of transistors, each of the transistors having a gate stack including a floating gate, the transistors being at least partially covered by a triple layered capping layer and an interlevel dielectric, wherein the triple layered capping layer includes a bottom buffer layer, a middle insulative layer, and a highly transparent layer, wherein a contact extends through the capping layer and the interlevel dielectric between adjacent gate stacks of the plurality of transistors and the configuration of the triple layered capping layer and the contact makes the integrated circuit resistant to charge gain or charge loss associated with the gate stacks, wherein only the bottom buffer layer extends continuously from a level below a top surface of the floating gate conductor to a top surface of the gate stack in a cross-sectional view through the contact and the first gate stack.