Patent ID: 6219279
Filing Date: 2001-04-17
Classification: G11C

Abstract:
In an array of floating gate transistor memory cells having bit lines individually connected to a column of said cells and word lines individually connected to a row of said cells, a program driving circuit connectable to individual ones of the bit lines to provide, in response to an active programming signal, a programming current to a cell connected thereto that is addressed by a proper voltage on its word line, comprising:a first transistor connected between the bit line and a programming voltage supply, said first transistor having a source connected with the programming voltage supply and a gate whose voltage controls a level of conduction through said first transistor,a reference current supply, anda second transistor connected to the reference current supply and the first transistor in a manner, when the programming signal is active, to mirror a controlled current through the second transistor to the first transistor, thereby to limit a maximum value of the bit line current during programming of an addressed cell connected to the bit line.