Patent ID: 6606743
Filing Date: 2003-08-12
Classification: G06F

Abstract:
A computer system providing accelerated processing of stack oriented interpretive language instructions, said system comprising:a native processing unit for executing native language instructions; a translator for translating the interpretive language instructions to native language instructions, for generating address values associated with selected ones of said native language instructions, and for establishing a correlation between each of said address values and a corresponding core operation; a dedicated processing accelerator core communicatively coupled with said processing unit, responsive to address values received from said processing unit, and operative to perform core operations, said core including, a dedicated hardware stack cache memory device having a plurality of memory address locations addressable by said address values, said locations for storing operand data upon which said core operations are to be performed, core control logic responsive to said address values and read/write control signals provided by said native processing unit, operative to control writing and reading of said operand data to and from said cache memory device, and being further operative to determine core operations corresponding with said address values based solely on said correlation established by said translator, and an arithmetic logic unit communicatively coupled with said core control logic for receiving said operand data from corresponding ones of said address locations of said cache memory device, and being operative to perform core operations on said operand data, each of said core operations being specified solely by said address values.