Patent ID: 6813199
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:first to fourth normal memory cell groups each including a plurality of normal memory cells; first and second spare memory cells each for being substituted for a defective memory cell among said plurality of normal memory cells; a first select circuit holding address assignment information in a non-volatile manner, selecting two normal memory cell groups among said first to fourth normal memory cell groups determined on the basis of said address assignment information together with said first spare memory cell in response to a first address value given as an input address, and selecting the other two normal memory cell groups among said first to fourth normal memory cell groups determined on the basis of said address assignment information together with said second spare memory cell in response to a second address value given as said input address; and a second select circuit holding replacement information in a non-volatile manner, selecting said first spare memory cell on the basis of said replacement information instead of a first defective memory cell among normal memory cells selected according to said first address value, and selecting said second spare memory cell on the basis of said replacement information instead of a second defective memory cell among normal memory cells selected according to said second address value.