Patent ID: 7956664
Filing Date: 2011-06-07
Classification: G06F,H04L

Abstract:
1. A method of controlling a digital system having a plurality of clock domains, each clock domain having a respective local network and a respective capacitive load discrete from the local network and the capacitive load of any other one of the plurality of clock domains, the method comprising the steps of: distributing a reference clock via a global clock distribution network coupled to each of the plurality of clock domains; generating a local resonant clock waveform from the reference clock via a clock generator in a first clock domain of the plurality of clock domains; resonating the capacitive load of the first clock domain with the local resonant clock waveform via an inductor in the first clock domain independently of the capacitive load of any other one of the plurality of clock domains for resonant distribution of the local resonant clock waveform via the respective local network of the first clock domain; and adjusting a programmable delay element disposed on a path carrying the reference clock to the first clock domain or a second clock domain of the plurality of clock domains; wherein the adjusting step comprises responding to a control signal directed to controlling the programmable delay element to manage a relative clock phase difference between the first and second clock domains.