Patent ID: 6272063
Filing Date: 2001-08-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first core section including a plurality of memory cell arrays and a plurality of sense amplifiers, said first core section having a rectangular shape with a long side and a short side;a second core section including a plurality of memory cell arrays and a plurality of sense amplifiers, said second core section having a rectangular shape with a long side and a short side, the long side of said second core section facing the long side of said first core section;a third core section including a plurality of memory cell arrays and a plurality of sense amplifiers, said third core section having a rectangular shape with a long side and a short side, the short side of said third core section facing the short side of said first core section;a fourth core section including a plurality of memory cell arrays and a plurality of sense amplifiers, said fourth core section having a rectangular shape with a long side and a short side, the long side of said fourth core section facing the long side of said third core section;an input circuit for inputting first and second activation signals;a first control signal line coupled between said first core section and said fourth core section to activate said first core section and said fourth core section in accordance with said first activation signal; anda second control signal line coupled between said second core section and said third core section to activate said second core section and said third core section in accordance with said second activation signal.