Patent ID: 7292484
Filing Date: 2007-11-06
Classification: G11C

Abstract:
1. A memory circuit, comprising: a reference voltage circuit comprising: a fourth transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving the first bias voltage, and a second current electrode, wherein the fourth transistor is of the first conductivity type; a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode for receiving the second bias voltage, and a second current electrode, wherein the fifth transistor is of the second conductivity type; a first memory cell having a first terminal coupled to the second current electrode of the fifth transistor and a second terminal coupled to the second power supply terminal; a sixth transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving the first bias voltage, and a second current electrode, wherein the sixth transistor is of the first conductivity type; a seventh transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode for receiving the second bias voltage, and a second current electrode, wherein the seventh transistor is of the second conductivity type; a second memory cell having a first terminal coupled to the second current electrode of the seventh transistor and a second terminal coupled to the second power supply terminal; a first comparator having a first input coupled to the second current electrode of the first transistor, a second input coupled to the second current electrode of the fourth transistor, and an output corresponding to a signal representative of a logic state of the first memory cell; and a second comparator having a first input coupled to the second current electrode of the first transistor, a second input coupled to the second current electrode of the sixth transistor, and an output corresponding to a signal representative of a logic state of the second memory cell.