Patent ID: 7646667
Filing Date: 2010-01-12
Classification: G06F,G11C

Abstract:
1. A memory system, comprising: an array of re-programmable non-volatile memory cells divided into a plurality of sub-arrays of memory cells, the sub-arrays being divided into a plurality of blocks that individually contain a minimum number of memory cells that are erasable together, a first group of the blocks storing user data and a second group of one or more of the blocks storing records of physical characteristics of the first group of blocks or their operation, a controller memory separate from the array of floating gate memory cells in which at least some of the records from the second group of blocks are temporarily stored, said controller memory being characterized by operating faster than the array of re-programmable non-volatile memory cells, an external data interface; and a controller adapted to (1) communicate user data between the interface and the first group of blocks with the use of those of the records in the controller memory from the second group of blocks that correspond to those of the first group of blocks with which user data are communicated, and (2) write user data received through the interface into more than one of the blocks of memory cells of the first group of blocks in more than one sub-array at a time.