Patent ID: 6521495
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method for fabricating a non-volatile memory device, comprising:forming isolation layers on a semiconductor substrate to define active regions; forming floating gate layers on the active regions while a tunneling insulating layer is interposed therebetween; forming common source regions in a column direction, each crossing the floating gate layers so as to divide each of the floating gate layers and the isolation layers into two parts; forming intergate dielectric layers and control gate layers on the divided floating gate layers; patterning the control gate layers, the intergate dielectric layers and the divided floating gate layers to complete control gates, intergate dielectric layers and floating gates, wherein each control gate is parallel to one of the common source regions and overlaps a pair of the floating gates adjacent in a column direction, and wherein the pair of the floating gates centers around one of the common source regions; and forming bit lines connected to drain regions adjacent to the floating gates.