Patent ID: 8471611
Filing Date: 2013-06-25
Classification: H03L,H04L

Abstract:
1. A phase-locked loop (PLL) for maintaining, a phase relationship between an output signal and an input signal, the PLL comprising: a multi-modulus divider (MMD) configured to reduce a frequency of the output signal by a fractional division factor to provide a comparison signal; a modulator configured to increment an accumulator value after a cycle of the comparison signal and control the MMD based on the accumulator value to alternately reduce the frequency of the output signal by at least two integer division factors to provide the comparison signal; a delay line configured to delay the comparison signal based on the accumulator value to provide an adjusted comparison signal; and a bang-bang phase detector (BBPD) configured to detect a difference in phase between the input signal and the adjusted comparison signal to adjust a phase of the output signal to maintain the phase relationship.