Patent ID: 7276404
Filing Date: 2007-10-02
Classification: G11C,H01L,Y10S

Abstract:
1. A method of forming an SRAM cell having gate patterns vertically stacked on a cell array region, the method comprising: forming a device isolation layer in a semiconductor substrate of the cell array region, the isolation layer being formed to isolate at least one lower active region; sequentially forming two lower cell gate patterns on the lower active region, and a buried interlayer insulating layer covering the lower cell patterns; sequentially forming a sacrificial layer pad between the lower cell gate patterns passing the buried interlayer insulating layer, and a body pattern on the buried interlayer insulating layer, the body pattern being formed to extend from one of the lower cell gate patterns and overlap the sacrificial layer pad, and concurrently, to confine an upper active region; forming upper cell gate patterns facing each other on the upper active region, the upper cell gate patterns being formed to overlap the lower cell gate patterns respectively; forming a semiconductor buffer layer on the buried interlayer insulating layer to conformally cover the upper gate patterns; forming pad holes confined by the buried interlayer insulating layer together with the semiconductor buffer layer, thereby exposing the semiconductor substrate and the device isolation layer respectively; and forming a landing pad and a node pattern fully filling the pad holes respectively, wherein the pad hole exposing the device isolation layer is formed to expose one of the upper cell gate patterns and the underneath lower cell gate pattern, and the pad hole exposing the semiconductor substrate is formed to remove the sacrificial layer pad, and expose the remaining upper cell gate pattern and the body pattern.