Patent ID: 7158404
Filing Date: 2007-01-02
Classification: G11C

Abstract:
1. A memory cell for a first bit line, a second bit line, a word line and a power voltage, the memory cell comprising: a first PMOS transistor comprising a first gate, a first drain, and a first source coupled to the power voltage; a first NMOS transistor comprising a second gate coupled to the first gate, a second drain coupled to the first drain, and a second source coupled to a ground voltage, wherein the connection point of the first drain and the second drain is a first terminal; a second PMOS transistor comprising a third gate coupled to the first terminal, a third drain coupled to the first gate, and a third source coupled to the power voltage; a second NMOS transistor comprising a fourth gate coupled to the first terminal, a fourth drain coupled to the third drain, and a fourth source coupled to the ground voltage, wherein the connection point of the third drain and the fourth drain is a second terminal; a first switch coupled between the first bit line and the first terminal, switched according to a voltage level of the word line; a second switch coupled between the second bit line and the second terminal, switched according to the voltage level of the word line; and a latch circuit having a power terminal directly connected to the power voltage, and coupled between the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal.