Patent ID: 6637009
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A method of optimizing a logic circuit that includes a plurality of flip-flops, the method comprising the steps of:determining in advance target delay values, said target delay values being limit values of delay times of all signal paths between the external input terminals and output terminals; modifying said logic circuit to a hierarchical structure, said hierarchical structure composed of circuits, said circuits in total comprising a schematic of said logic circuit, wherein each individual circuit constitutes a path of said logic circuit in which there axe no paths that do not pass through a flip-flop, and further wherein each individual circuit has as its beginning and/or end: an input terminal of one of said plurality of flip-flops, the external input terminals of said logic circuit, or the external output terminals of said logic circuit; and optimizing each of said individual circuits such that said delay times are less than or equal to said target delay values.