Patent ID: 6715042
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A system comprising:a first processor configured to decode a digital signal from a digital signal source; a second processor configured to provide control signals to the first processor; and an expansion unit having a first port coupled to the first processor and a second port coupled to the second processor wherein the expansion unit is configured to communicate data and instructions between a memory device and the first and second processors, the expansion unit including: a state generator comprising circuitry for selecting one of the first and second ports for receiving a memory device access grant in response to at least one request from a corresponding one of the first and second processor, the circuitry including circuitry for selecting the one of the first and second ports according to a selected arbitration protocol, and wherein a duration of the memory device access grant comprises one of a preselected number of accesses and a preselected timeslice; and logic for selecting the one of the preselected number of accesses and the preselected timeslice for determining the duration of the memory device access grant, and an amplifier for amplifying a decoded digital signal from the first processor.