Patent ID: 6356970
Filing Date: 2002-03-12
Classification: G06F

Abstract:
A system comprising a processor, an ASIC which generates at least N interrupt requests to be serviced by said processor, a memory accessible by said processor and containing at respective address locations therein individual interrupt services routines to be executed by said processor in servicing respective ones of said interrupt requests, and a processor bus connected to said processor, said ASIC and said memory, said system further comprising:an ICSR connected to receive said N interrupt requests and having N flags corresponding to respective ones of said N interrupt requests and reflecting pending status of respective ones of said N interrupt requests, said flags being associated with respective numbers according to a priority ranking of said interrupt requests; a look-up table containing, by said respective numbers, vectors corresponding to said respective address locations, said look-up table having a look-up table input and a look-up table output providing a vector corresponding to a number received at said look-up table input; an ICVR connected to said look-up table output and readable by said processor, whereby said ICVR contains a vector provided at said look-up table output; a controller having a controller input connected to said ICSR and a controller output specifying the respective number of the highest priority pending flag in said ICSR, said output being coupled to said look-up table input, said controller further including logic circuitry which changes the status of a pending flag in said ICSR upon said processor reading the corresponding vector in said ICVR, whereby the contents of said ICVR is updated to reflect the current highest priority pending interrupt request.