Patent ID: 8959289
Filing Date: 2015-02-17
Classification: G06F

Abstract:
1. A method of data processing in a data processing system including a processor core supported by upper and lower level caches, the method comprising: the processor core executing a deallocate instruction at completion of processing of a dataset including a target cache line and a plurality of other cache lines to promote eviction of the dataset from the lower level cache; in response to executing the deallocate instruction in the processor core, sending a deallocation request from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line; in response to receipt of the deallocation request at the lower level cache, determining if the target address hits in the lower level cache; and in response to determining that the target address hits in the lower level cache, retaining the target cache line in a data array of the lower level cache and updating a replacement order field in a directory of the lower level cache such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss in a congruence class including the target cache line.