Patent ID: 7822926
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. Apparatus for processing data comprising: a cache memory having a plurality of cache rows each of said cache rows configured to store a cache line of data values; a memory partitioning unit which partitions memory into a plurality of regions of memory; a cache controller, coupled to said cache memory and responsive to a cache miss, configured to trigger a line fill operation to store data values into said cache rows, wherein said cache controller is responsive to a cache line size specifier associated with at least one region of memory to vary a number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier, wherein at least one of said cache rows is configured by said cache line size specifier to form a variable number of portions, each of said portions storing one or more of said data values, wherein each of said portions of said at least one of said cache rows has an associated cache tag for storing address information identifying a memory location corresponding to said one or more data values stored in a corresponding portion of said at least one of said cache rows.