Patent ID: 6373305
Filing Date: 2002-04-16
Classification: H03L,H04L

Abstract:
A digital phase lock loop (PLL) employing cumulative phase error correction, said PLL having an internal PLL clock and comprising:a data signal input at which an incoming data signal is received, said data signal comprising successive pulses having a characteristics pulse edge rate, said internal PLL clock having a clock rate about M times said pulse edge rate to define M successive samples of each one of said successive pulses; a state machine having an internal cyclic count of modulus M incremented in synchronism with said internal PLL clock, corresponding to M successive samples of each one of said successive pulses, said state machine having a control input for advancing or retarding said internal cyclic count, said internal cyclic count including: (a) a predetermined center count value tending to coincide with center regions of said successive pulses, and (b) a predetermined edge count value offset from said center count value by approximately one half of one pulse width of said successive pulses and tending to coincide with edges of the successive pulses; sampling logic connected to receive said data signal and having a sampling control input connected to an output of said state machine, said sampling logic for selecting a current one of said M successive samples whenever said internal count reaches the predetermined center count value; an edge detector; an error detector for sampling said internal count from said state machine in synchronism with aid edge detector whereby to sense a phase error between a time of occurrence of a current one of said successive edges and the time of occurrence of said edge count value of said internal count; a cumulative phase error register; an adder having a first input connected to receive said phase error from said error detector, a second input connected to an output of said cumulative phase error register, and an adder output connected to an input of said cumulative phase error register, whereby to store in said cumulative phase error register a cumulative phase error of phase error summed over successive edges of said data signal; a correction circuit responsive upon accumulation of a predetermined number N of phase errors for applying a correction signal corresponding to said cumulative phase error to said control input of said state machine; and residual error logic for computing from said predetermined number N and from said cumulative phase error a residual phase error remaining after application of a correction signal to said control input of said state machine; and reset logic for resetting said cumulative phase error register to a current value of said residual phase error whenever said correction output signal is applied to said state machine, whereby successive cumulative phase errors are computed and corresponding corrections made to said internal count periodically.