Patent ID: 7940599
Filing Date: 2011-05-10
Classification: G11C

Abstract:
1. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising: a first storage module comprising a first storage node; a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline; a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline; and a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode; a reference node to provide a precharge signal; a fourth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the first bit line, and a control electrode; a fifth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the second bit line, and a control electrode; and a control module coupled to the control electrode of the fifth transistor and operable, in response to a dummy access of the first storage module at the second transistor, to deactivate the fifth transistor during the dummy access of the first bit cell.