Patent ID: 7650468
Filing Date: 2010-01-19
Classification: G06F,G10H

Abstract:
1. A data processor, comprising: a CPU configured to control an entire system; a DSP configured to perform preset processing, to have at least two bus cycles in a unit of one data access, and to use a selectable number of the bus cycles in the unit of one data access; and an external memory configured to be accessed by the DSP and to be accessed through the DSP by the CPU, wherein a data word length accessed by the DSP at the external memory is variable, and the DSP includes wherein when the DSP accesses the external memory using a maximum number of the bus cycles in a unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is placed in a wait state until a subsequent unit of data access commences, and when the DSP does not access the external memory using the maximum number of the bus cycles in said unit of data access wherein the DSP actually accesses the external memory, access from the CPU to the external memory is constantly allowed during said unit of data access.