Patent ID: 6396754
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A semiconductor memory device having memory cells connected to a plurality of word lines and a plurality of bit lines, comprising:a row address strobe (RAS) signal delay unit that delays a row address strobe (RAS) signal for a period of time and outputs the delayed RAS signal; a sense amplifier control signal generator that generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, the first and second sense amplifier control signals being enabled concurrently and at respectively different times depending on an operation mode of the semiconductor memory device; plurality of first sense amplifiers that sense and amplify potential of a (2Nâˆ’1)th bit line pair of the semiconductor memory device responsive to the first sense amplifier control signal, wherein N is a natural number equal to or greater than 1; and a plurality of second sense amplifiers that sense and amplify potential of a 2Nth bit line pair of the semiconductor memory device responsive to the second sense amplifier control signal, wherein during a test mode, the first and second sense amplifier control signals are enabled at the respectively different times, so that the first and second sense amplifiers are activated at different times.