Patent ID: 9059315
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of forming a semiconductor device comprising: forming a first high-k dielectric layer above a semiconductor substrate having a pFET region and an nFET region; forming a first sacrificial layer above a portion of the first high-k dielectric layer only in the pFET region, another portion of the first high-k dielectric layer remaining exposed in the nFET region; forming a pFET work-function metal layer above and in direct contact with only the first sacrificial layer; forming a second sacrificial layer above and in direct contact with only the pFET work-function metal layer; forming an nFET work-function metal layer above and in direct contact with the portion of the first high-k dielectric layer only in the nFET region, above and in direct contact with the second sacrificial layer in the pFET region, and along a sidewall of each of the first sacrificial layer, the pFET work function metal layer, and the second sacrificial layer; forming a pFET gate dielectric layer in the pFET region from the portion of the first high-k dielectric layer in the pFET region by annealing the pFET work function metal layer and the portion of the first high-k dielectric layer in the pFET region; and forming an nFET gate dielectric layer in the nFET region from the portion of the first high-k dielectric layer in the nFET region by annealing the nFET work function metal layer and the portion of the first high-k dielectric layer in the nFET region.