Patent ID: 7310396
Filing Date: 2007-12-18
Classification: G06F,H04L

Abstract:
1. A method of translating input data captured at a first clock frequency into output data conveyed at a second clock frequency, the method comprising: sampling a first clock signal carrying the first clock frequency with a second clock signal carrying the second clock frequency to produce a clock sample; first registering the input data synchronously with the first clock frequency using the first clock signal to provide first registered data of a first time domain associated with the first clock signal, the first registered data being registered with a first data width; second registering the first registered data using the second clock signal to provide second registered data of a second time domain associated with the second clock signal, the second registered data being registered with the first data width; generating control signaling using the clock sample for controlled output of the second registered data; the first clock frequency being substantially less than the second clock frequency; the second registering including periods of synchronous registration of the first registered data with respect to the second clock signal responsive to the sampling and including other periods of no synchronous registration with respect to the second clock signal responsive to the sampling; and outputting the second registered data synchronously with the second clock frequency responsive to the second clock signal to provide the output data, the output data provided with a second data width less than the first data width.