Patent ID: 6444558
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method for selectively forming an antifuse in an integrated circuit, comprising:forming a first conductive island of the antifuse and a second conductive island of the antifuse on an insulator, wherein the insulator is supported by a semiconductor substrate and insulates the first conductive island and the second conductive island from the semiconductor substrate; forming a refractory metal silicide layer on the first and second conductive islands; forming a bottom conductor layer on the refractory metal silicide layer of the first conductive island; forming a programming layer on the bottom conductor layer; and forming a top conductor layer on the programming layer, wherein the top conductor layer overlies at least a portion of the second conductive island, wherein the refractory metal silicide layer on the first conductive island of the antifuse is adapted to function as an etch stop for a first electrical contact to the bottom conductor layer of the antifuse through the first conductive island and the refractory metal silicide layer on the first conductive island, and wherein the refractory metal silicide layer on the second conductive island of the antifuse is adapted to function as an etch stop for a second electrical contact to the top conductor layer of the antifuse.