Patent ID: 7277980
Filing Date: 2007-10-02
Classification: G06F,Y02D

Abstract:
1. A non-volatile memory device, comprising: a single array of non-volatile memory cells having a plurality of rows and columns arranged in erase blocks, wherein each erase block contains two or more erase sub-blocks; wherein each erase block comprises a plurality of rows of the memory array that cross all of the array columns, and where each erase sub-block comprises a plurality of rows of the memory array that cross only a selected number of the array columns; wherein the non-volatile memory device is adapted to selectively erase either an erase block of the array or a single erase sub-block of an erase block of the array; and wherein each erase block comprises rows having contiguous memory cell location addresses, and each erase sub-block comprises rows having non-contiguous memory cell location addresses.