Patent ID: 6759318
Filing Date: 2004-07-06
Classification: H01L,H05K

Abstract:
A method for improving an IC substrate manufacturing process with bump pitch less than 180 um, comprising the steps of:(a) providing a substrate formed with a first metal layer and a plurality of through holes, said first metal layer and said plurality of through holes being plated with a first metal plated layer; (b) forming an inner layer circuit by patterning and etching said first metal layer and said first metal plated layer; (c) black-oxiding said inner layer circuit; (d) covering and filling said inner layer circuit and said plurality of through holes with a first dielectric layer; (e) covering said first dielectric layer with a second metal layer; (f) forming a plurality of first micro vias through said second metal layer and said first dielectric layer; (g) plating said second metal layer and said plurality of first micro vias with a second metal plated layer; (h) filling said plurality of first micro vias with plating filled copper, etching and forming a circuit layer above said plurality of first micro vias and said second metal plated layer, said circuit layer including a plurality of bump pads on a bump-pad side of said substrate and a plurality of ball pads on a ball-pad side of said substrate; (i) forming a second dielectric layer on said bump-pad side for covering said plurality of bump pads, and a solder resist layer on said ball-pad side for covering said plurality of ball pads; (j) forming a plurality of second micro vias by CCD alignment laser drilling on said second dielectric layer for exposing said plurality of bump pads; (k) filling up said plurality of second micro vias with plating filled metal to a surface level for providing enlarged bump pads and translating passive components and fiducial marks to said surface level; (l) providing flexible and adjustable bump pads to meet wafer side bump size; and (m) providing flexible final finishing.