Patent ID: 7818656
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A circuit comprising: a first combinatorial circuit configured to implement a combinatorial function f, wherein the first combinatorial circuit is configured to receive inputs x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t), and to output y[1](t), . . . , y[n](t), wherein the combinatorial function f determines outputs y[1](t), . . . , y[n](t) such that outputs y[1](t), . . . , y[n](t) are indicative of a bit-by-bit comparison of inputs x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t); a controllable register, comprising: a second combinatorial circuit configured to implement a combinatorial function g, wherein the second combinatorial circuit is configured to receive binary states z[1](t), . . . , z[n](t), and output a value u(t), wherein the combinatorial function g determines output u(t) as a function of binary states z[1](t), . . . , z[n](t).