Patent ID: 7733999
Filing Date: 2010-06-08
Classification: H03L,H04J

Abstract:
1. A system for providing timing recovery of a digital clock for a digital transmission comprising: a phase smoothing circuit, wherein the phase smoothing circuit redistributes timing discontinuities caused by the removal of overhead bytes, pointer justification bytes, stuff bytes, or other phase discontinuities in a signal, into a series of smaller and more frequent phase discontinuities in order to remove low frequency components in the power spectrum of the signal, and a clock gapping circuit, wherein the clock gapping circuit outputs a timing pulse train with an average frequency equal to a desired output clock frequency, and wherein the clock gapping circuit utilizes analog proportional/differential control with feedback, and wherein the timing pulse train is achieved by inhibiting timing pulses on a system clock based on a ratio that is proportional to an average output frequency relative to the system clock, and wherein a plurality of controlled clock gapping circuits are cascaded in a series such that a highest gain controlled clock gapping circuit is first in the series followed by a one or more lower gain controlled clock gapping stages, and wherein a plurality of controlled clock gapping circuits are cascaded in series such that the system is a three-stage implementation, wherein stage