Patent ID: 6060927
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A data storage device, comprising:a first latch that receives a clock signal and a data signal and produces a first output signal, wherein the first output signal is an inverted logical value of the data signal when the clock signal is low level, wherein the first latch consists of,a first pull-up element controlled by the clock signal, anda first pull-down element controlled by the data signal, wherein the first pull-down element is coupled at a first node in series with the first pull-up element between first and second prescribed voltages;a second latch that receives the first output signal and the clock signal and produces a second output signal, wherein the second output signal is high level when the clock signal is low level; anda third latch that receives the second output signal and the clock signal and produces a third output signal, wherein the third output signal is an inverted logical value of the second output signal when the clock signal is high level.