Patent ID: 8350330
Filing Date: 2013-01-08
Classification: B44C,B44F,C03C,C09D,C25D

Abstract:
1. An integrated circuit structure comprising: a target diffusion region comprising: a first stress-blocking dummy diffusion region adjacent to, and spaced apart from, the first edge, wherein no dummy diffusion regions are located between the first edge and the first stress-blocking dummy diffusion region, and wherein the first stress-blocking dummy diffusion region has a first lengthwise dimension substantially not smaller than the first length; and a second stress-blocking dummy diffusion region adjacent to, and spaced apart from, the second edge, wherein no dummy diffusion regions are located between the second edge and the second stress-blocking dummy diffusion region, wherein the second stress-blocking dummy diffusion region has a second lengthwise dimension substantially not smaller than the second length, and wherein the first and the second lengthwise dimensions are in perpendicular directions.