Patent ID: 6806535
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A non-volatile memory structure, comprising:a substrate; a buried bit line within the substrate; a plurality of first stacked blocks on the substrate, wherein each first stacked block is a stack having a cap layer, a conductive layer and a gate dielectric layer; a plurality of second stacked blocks on the substrate, wherein each second stacked block is a stack having a conductive layer and a gate dielectric layer; a dielectric layer over the substrate for isolating the first stacked blocks and the second stacked blocks; and a word line over the dielectric layer for connecting stacked blocks in the same row serially to form a plurality of coding memory cells, wherein the coding memory cells having a first stacked block is in a first data state and the coding memory cells having a second stacked block is in a second data state.