Patent ID: 7532069
Filing Date: 2009-05-12
Classification: H03F

Abstract:
1. A pipeline A/D converter, comprising: a sample-and-hold unit which converts an inputted continuous-time analog signal into a discrete-time analog signal; and an A/D converter unit which converts the discrete-time analog signal into a plurality of quantized values, the A/D converter unit having a plurality of A/D conversion stages connected in series, the A/D conversion stage converts an inputted analog signal into the quantized value, wherein at least one of the sample-and-hold unit and the A/D conversion stage has a differential amplifying circuit which includes: an input stage including a pair of differential input terminals and a pair of differential output nodes outputting differential currents according to differential voltages inputted to the pair of differential input terminals; a first intermediate stage including a first transistor and a first amplifying circuit, the first transistor having a source to which one of the pair of differential output nodes and an input side of the first amplifying circuit are connected, a gate to which an output side of the first amplifying circuit is connected, and a drain being a negative-side current output node; a second intermediate stage including a second transistor and a second amplifying circuit, the second transistor having a source to which another of the pair of differential output nodes and an input side of the second amplifying circuit are connected, a gate to which an output side of the second amplifying circuit is connected, and a drain being a positive-side current output node; and an output stage using the negative-side current output node and the positive-side current output node as a pair of differential input nodes and including a pair of differential output terminals outputting differential voltages according to differential currents inputted to the pair of differential input nodes, wherein the first amplifying circuit includes: wherein the second amplifying circuit includes: wherein a drain of the sixth transistor is connected to the drain of the eighth transistor, and a drain of the tenth transistor is connected to the drain of the fourth transistor; wherein a ratio between a total of gate widths converted per unit gate length of the fourth and the tenth transistor and a gate width converted per unit gate length of the fifth transistor is nearly proportional to a current ratio between the first current source circuit and the second current source circuit, the gate width converted per unit gate length of the fourth transistor being equal to or more than the gate width converted per unit gate length of the tenth transistor; and wherein a ratio between a total of gate widths converted per unit gate length of the eighth and the sixth transistor and a gate width converted per unit gate length of the ninth transistor is nearly proportional to a current ratio between the third current source circuit and the fourth current source circuit, the gate width converted per unit gate length of the eighth transistor being equal to or more than the gate width converted per unit gate length of the sixth transistor.