Patent ID: 6987704
Filing Date: 2006-01-17
Classification: G11C

Abstract:
1. A synchronous memory device receiving data in synchronization with a clock signal, the data being inputted in response to a write command, the synchronous memory device comprising: a data alignment means for aligning in parallel a plurality of data sequentially inputted through one data input pin as many as the number of prefetched data to generate a plurality of aligned data; a global I/O line driving means for receiving the plurality of aligned data and outputting the even data or the odd data to a memory core area in response to a data input strobe signal; a data input strobe signal generating means for buffering the clock signal to output the data input strobe signal; and a data input strobe signal control means for generating a data input strobe control signal used to allow the data input strobe signal generating means to output the data input strobe signal only at a period when an operation corresponding to the write command is carried out.