Patent ID: 9021311
Filing Date: 2015-04-28
Classification: G06F

Abstract:
1. A processing system comprising: a first interconnect of a first data processor to communicate information between a portion of the first data processor and a first memory; a first debug module, of the first data processor, coupled to the first interconnect, the first debug module comprising: a first data trace filter module coupled to the first trace buffer to filter out data trace information stored at the first trace buffer that does not meet a second data trace criteria; a second interconnect of a second data processor to communicate information between portions of the second data processor a second memory; and a second debug module, of the second data processor, coupled to the second interconnect, the second debug module comprising: a second data trace filter module coupled to the second trace buffer to filter out data trace information stored at the second trace buffer that does not meet a fourth data trace criteria.