Patent ID: 6020773
Filing Date: 2000-02-01
Classification: H03K,H03L

Abstract:
A clock signal generator comprising:a pre-phase converter including a plurality of cascaded pre-delay circuits, and an initial pre-delay circuit of said plurality of pre-delay circuits receiving a clock signal, said plurality of pre-delay circuits producing pre-delay clock signals; anda main phase converter including a plurality of main delay circuit sequences, each of said main delay circuit sequences including a plurality of cascaded main delay circuits, each of said main delay circuit sequences receiving one of said pre-delay clock signals, and said main delay circuits in said plurality of main delay circuit sequences producing main phase clock signals, wherein delay of said pre-delay circuits differs from delay of said main delay circuits, and the main phase clock signals differ in phase from each other, wherein said main phase converter comprises:a sub-delay circuit sequence including a plurality of cascaded sub-delay circuits, the sub-delay circuits including an initial sub-delay circuit receiving a sub-clock signal;a sub-phase comparator receiving two sub-delay clock signals output from said plurality of sub-delay circuits, and outputting a sub-phase compared signal corresponding to a phase difference between the two sub-delay clock signals; anda first charge pump for storing a first charge in response to the sub-phase compared signal; anda control circuit for controlling a delay of said sub-delay circuits and a delay of said main delay circuits in response to an integral of the first charge.