Patent ID: 6339553
Filing Date: 2002-01-15
Classification: G11C,H03K,H03L

Abstract:
A clock generating circuit generating an internal clock signal synchronized with an external clock signal, comprising:a first input buffer circuit generating a first internal signal according to voltage levels of said external clock signal and an inverted external clock signal; a first delay circuit adding a delay control time to said first internal signal; a phase difference control circuit setting said delay control time in accordance with phase difference between said first internal signal and an output signal of said first delay circuit; a second input buffer circuit generating a second internal signal having phase inverted from that of said first internal signal, according to voltage levels of said external clock signal and said inverted external clock signal; a second delay circuit adding said delay control time set commonly to said first delay circuit, to said second internal signal under control of said phase difference control circuit; and a signal generating circuit generating said internal clock signal in response to output signals of said first and second delay circuits.