Patent ID: 6362028
Filing Date: 2002-03-26
Classification: G02F

Abstract:
A method for fabricating TET array with reduced masks comprising the steps of:providing a substantially transparent ceramic panel, sputter depositing a first metal layer on said ceramic panel, forming a plurality of gate buslines on said ceramic panel with a first mask, depositing sequentially a gate nitride layer, an intrinsic amorphous silicon layer and an n+ doped amorphous silicon layer on top of said plurality of gate buslines, sputter depositing a metal mask layer for a source/drain metal on said n+ doped amorphous silicon layer, patterning and forming a TFT island and source/drain data lines simultaneous by a second mask, sputter depositing a second metal layer on top of said metal mask layer, patterning TFT channel and a storage capacitor by a third mask, etching a plurality of back channels, depositing a passivation layer and patterning said layer by a fourth mask, and sputter depositing a substantially transparent conductive electrode layer on top of said passivation layer and patterning electrodes by a fifth mask.