Patent ID: 7537988
Filing Date: 2009-05-26
Classification: G11C,H01L

Abstract:
1. A method of fabricating a CMOS integrated circuit, comprising the steps of: providing a substrate having a semiconductor surface; forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using said surface; forming a multi-layer offset spacer stack comprising a top layer and a compositionally different bottom layer; etching said multi-layer spacer stack to leave offset spacers on sidewalls of said gate electrodes; covering transistors designed to utilize a thinner offset spacer with a first masking material; patterning transistors designed to utilize a thicker offset spacer; first implanting said transistors designed to utilize a thicker offset spacer; removing at least a portion of said top layer to leave said thinner offset spacers on said sidewalls of said gate electrodes; covering said transistors designed to utilize said thicker offset spacer with a second masking material, patterning said transistors designed to utilize said thinner offset spacer; second implanting said transistors designed to utilize said thinner offset spacer, and completing fabrication of said integrated circuit.