Patent ID: 8742486
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A memory cell comprising: a first trench formed in a semiconductor substrate having a uniform doping concentration; a second trench formed in said semiconductor substrate adjacent to said first trench, said first trench and said second trench defining a first sidewall and a second sidewall, respectively, of a channel in said semiconductor substrate between said first trench and said second trench; a first storage element formed on said first sidewall; a second storage element formed on said second sidewall; a first source/drain region formed substantially under said first trench; and a second source/drain region formed substantially under said second trench, wherein said first and second source/drain regions comprise an upper region and a lower region surrounding said upper region, wherein said first trench comprises an oxide layer extending into and substantially covering and substantially directly contacting an entire upper surface of said upper region of said first source/drain region, and wherein said channel comprises: