Patent ID: 8013394
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. An integrated circuit having a first resistor between a back-end-of-the-line (BEOL) interconnect and a front-end-of-the-line (FEOL) structure, the integrated circuit comprising: a first metal layer of the BEOL interconnect disposed above a contact layer of the FEOL structure with the first resistor disposed between the first metal layer and the contact layer, wherein the first resistor is contacted by the first metal layer and the contact layer; a second resistor disposed above the first metal layer, wherein the second resistor is connected to the first metal layer through a wiring path that traverses at least two contacts and a second metal layer of the BEOL interconnect; and a polysilicon member disposed below the contact layer, wherein the polysilicon member is contacted by the contact layer.