Patent ID: 6622230
Filing Date: 2003-09-16
Classification: G11C

Abstract:
A method of selecting a plurality of memory blocks in a memory device, each memory block having a block address, each block address comprising a string of bits, each bit having a bit location in the string, the method comprising the acts of:providing a starting address, the starting address being the block address of a memory first block; providing an ending address, the ending address being the block address of a memory second block, a multi-block first bit location comprising the most significant bit location of all the bit locations where the starting address has a different bit than the ending address, the multi-block first bit location being a bit location where the starting address has a 0 logic level and the ending address has a 1 logic level; comparing the starting address and the ending address to determine the multi-block first bit location; generating a converted memory block address where the bits in the bit locations more significant than the multi-block first bit location are the bits of the ending address at the corresponding bit location and where the bits in the bit locations less significant than, or equal in significance to, the multi-block first bit location are equal to a 1 logic level; generating a converted complementary memory block address where the bits in the bit locations more significant than the multi-block first bit location are the complements of the bits of the ending address at the corresponding bit location and where the bits in the bit locations less significant than, or equal in significance to, the multi-block first bit location are equal to a 1 logic level; pre-decoding the converted memory block address and the converted complementary memory block address to generate one or more sets of pre-decoded z-signals, each such set corresponding to one of the block addresses included in a group of block addresses comprising the starting address, the ending address and all the block addresses between the starting address and the ending address; and decoding each of the one or more sets of pre-decoded z-signals to generate one or more selecting signals that select a memory block whose block address is included in said group of block addresses.