Patent ID: 6313511
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductive substrate;a first substrate conductor region formed on or over said substrate and commonly shared by a first plurality of metal insulator semiconductor field effect transistors (""MISFETs"");a second substrate conductor region formed on or over said substrate and commonly shared by a second plurality of MISFETs;a third substrate conductor region formed on or over said substrate and commonly shared by a third plurality of MISFETs;a first power supply node having an output connected to said first substrate conductor region;a second power supply node having an output connected to said second substrate conductor region;a third power supply node having an output connected to said third substrate conductor region;wherein said first, second, and third of MISFETs are of the same conductivity type;said first substrate conductor region, said second substrate conductor region and said third substrate conductor region are electrically isolated from one another; andsaid first power supply node is lower in potential than said second power supply node, said second power supply node is lower in potential than said third power supply node, said second substrate conductor region being greater in total area than said first substrate conductor region, said second substrate conductor region being greater in total area than said third substrate conductor region.