Patent ID: 7084033
Filing Date: 2006-08-01
Classification: H01L

Abstract:
1. A method for fabricating a trench power MOSFET, comprising: forming an epitaxial layer and a mask layer on the substrate subsequently; forming a trench in the mask layer and the epitaxial layer; forming a gate oxide layer on a surface of the trench; forming a gate layer to fill the trench; removing the mask layer, so that a top surface of the gate layer is higher than that of the epitaxial layer; forming a body well region at both sides of the trench and in the epitaxial layer; forming a source region adjoined to a surface of the body well region and in the body well region; forming a spacer on sidewalls of the exposed gate layer, while a portion of the source region is exposed; removing a portion of the source region by using the spacer as a mask to form an opening, exposing a portion of the body well region, while a portion of the gate layer is removed at the same time; forming a body region below the opening and inside the body well region, and forming a metal silicide layer on surfaces of the opening and the gate layer.