Patent ID: 7941642
Filing Date: 2011-05-10
Classification: G06F

Abstract:
1. A multithreaded processor, comprising: a multithreaded instruction source configured to provide a plurality of instructions each corresponding to a respective one of a plurality of threads; a pick unit coupled to the multithreaded instruction source and configured to select in a given cycle, a first divide instruction corresponding to one thread in a first thread group of the plurality of threads and a second divide instruction corresponding to another thread in a second thread group of the plurality of threads based upon a thread selection algorithm, wherein the first divide instruction and the second divide instruction are selected by the pick unit for execution such that both the first divide instruction and the second divide instruction are scheduled for execution at a divider during a same cycle; a functional unit including the divider coupled to the pick unit and configured to execute the first divide instruction and the second divide instruction; a decode unit coupled to the functional unit, wherein the decode unit includes arbitration functionality for arbitrating between the first divide instruction and the second divide instruction for access to the divider using an indicator that is associated with the divider and that indicates which one of the first thread group and the second thread group has priority for access to the divider, wherein the arbitration functionality for arbitrating between the first divide instruction and the second divide instruction is independent of the thread selection algorithm; and a storage coupled to the divider and configured store a decoded and issued one of the first and the second divide instructions during execution of the other of the first and the second divide instructions.