Patent ID: 6973001
Filing Date: 2005-12-06
Classification: G11C,H03K

Abstract:
1. A semiconductor integrated circuit comprising: a first transistor disposed between a first node and a first power supply line, and pre-charging said first node to a first power supply voltage; a plurality of pairs of second transistors discharging electric charges at said first node which has been pre-charged to the first power supply voltage, each of the pairs of second transistors being disposed in series between said first node and a second power supply line; a timing signal delaying circuit having a plurality of delay stages connected in cascade, and generating a plurality of delayed timing signals obtained by sequentially inverting a first timing signal received at a first stage; a plurality of detection circuits operating at timings different from each other, each of which detects a voltage at said first node as a logic value; a selector selecting any one of a plurality of second timing signals depending on a detection result provided by said detection circuits, and an internal circuit operating in synchronization with a second timing signal selected by said selector, wherein gates of each of said pairs of second transistors receive one and the other of a pair of said delayed timing signals whose rising edge and falling edge are adjacent to each other, respectively, and the pair of said delayed timing signals received by each of said pairs of second transistors are different from each other.