Patent ID: 8327115
Filing Date: 2012-12-04
Classification: G06F

Abstract:
1. An apparatus, comprising: a memory storing a matrix of instructions; a pipeline comprising a decoder to decode the matrix of instructions and a matrix of execution units to execute the matrix of instructions, the matrix of instructions includes a set of instruction rows and instruction columns, each instruction within the same row across all columns is executed in parallel by a corresponding sub-set of execution units of the matrix of execution units and instructions dependent upon source instructions of an instruction row are in a subsequent instruction row of the matrix of instructions; a first sub-set of execution units corresponding to a row of the instruction matrix computes and forwards first data results to a second sub-set of execution units of a subsequent row of the matrix of execution units in a single clock cycle and without pipeline buffering; the second sub-set of execution units separately receives, from the matrix of instructions, instructions dependent upon the first data results; the second sub-set of execution units in the same single clock cycle, and without pipeline buffering, computes and forwards second data results to a third sub-set of execution units of a subsequent row of the matrix of execution units; and the third sub-set of execution units separately receives, from the matrix of instructions, instructions dependent upon the second data results; wherein the matrix of instructions is one of a plurality of matrices of instructions; wherein the matrix of execution units is one of a plurality of matrices of execution units; and wherein the plurality of matrices of execution units is alternately operative to: