Patent ID: 8169246
Filing Date: 2012-05-01
Classification: H03K

Abstract:
1. A circuit comprising: a precharge transistor coupled between a voltage supply node and a precharge node and configured to precharge the precharge node during a first phase of a clock signal; an input circuit coupled to receive an input data signal and configured to convey, based on a state of the input data signal, a first logic state to the precharge node during a second phase of the clock signal, wherein the input circuit comprises an input transistor coupled between the precharge node and a ground node and having a gate terminal configured to receive the input data signal; and an evaluation circuit including: a pull-up transistor coupled between the supply voltage node and a transfer node and having a gate terminal coupled to the precharge node; a discharge circuit including a first discharge transistor and a second discharge transistor; a delay circuit coupled to receive the clock signal and configured to delay the clock signal by a delay time; and a pull-down transistor having a gate terminal coupled to the precharge node, wherein the pull-down transistor is coupled between the ground node and the first discharge transistor, wherein the first discharge transistor is coupled between the pull-down transistor and the second discharge transistor, and wherein the second discharge transistor is coupled between the first discharge transistor and the second pull-up transistor; wherein the first discharge transistor is configured to activate responsive to the clock signal transitioning to the second phase, wherein the second discharge transistor is configured to activate at the delay time subsequent to the to the clock signal transitioning to the second phase, wherein the evaluation circuit is configured to convey a second logic state to the transfer node responsive to at least the clock signal transitioning to the second phase.