Patent ID: 8145853
Filing Date: 2012-03-27
Classification: G06F

Abstract:
1. A semiconductor memory apparatus, comprising: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores both the data and the priority information while maintaining a corresponding relationship between the data and the priority information; a data reading portion which reads the data corresponding to the address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input portion and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses the data with a highest priority among the priority information and the data that are stored in the read data storing portion, and outputs the chosen data, while maintaining a corresponding relationship between the priority information and the data.