Patent ID: 9201781
Filing Date: 2015-12-01
Classification: G06F,G06T

Abstract:
1. A data processing apparatus for accessing data to be processed, the data being stored in a memory composed of a plurality of blocks in each of which continuous access is possible, the data processing apparatus comprising: a mapping unit configured to determine addresses according to a first arrangement and addresses according to a second arrangement, the addresses being for mapping the data to a plurality of areas defined in the memory according to the determined addresses; the memory including: a selection unit configured to select one of the arrangements that is more efficient in accessing a portion to be read of the data, based on an address range corresponding to the portion of the data, the address range differing depending on which of the arrangements is selected; and an access control unit configured to perform control such that access to the portion of the data is realized by accessing, from among the plurality of areas in the memory, the first area and the second area corresponding to the addresses determined according to the selected arrangement, the memory storing data that is same as the data to be processed in the first area and the second area corresponding to the addresses determined according to the first arrangement and the addresses determined according to the second arrangement, wherein the addresses determined according to the first arrangement and the addresses determined according to the second arrangement are different from each other in terms of relative positions with respect to boundary addresses of the blocks in each address space, wherein the data to be processed is two-dimensional image data, the first arrangement and the second arrangement map the two-dimensional image data in a two-dimensional space, an address in the X direction of a pixel of the two-dimensional image data in the second address space is offset from an address in the X direction of a pixel of the two-dimensional image data in the first address space, or an address in the Y direction of a pixel of the two-dimensional image data in the second address space is offset from as address in the Y direction of a pixel of the two-dimensional image data in the first address space, and the blocks in the memory are memory cell groups, each memory cell group being composed of cells included in the same bank and having the same row address.