Patent ID: 6577480
Filing Date: 2003-06-10
Classification: H01L,H03K

Abstract:
An ESD protection circuit for operating with a Vss line and a Vdd line comprising:a string of a plurality of diodes connected in series between the Vss line and the Vdd line; a first PMOS transistor and a first NMOS transistor connected in series between the Vss line and one end of the string of diodes, the PMOS transistor having a gate which is connected between two of the diodes of the string, and the NMOS transistor having a gate which is connected to the Vdd line; a second PMOS transistor and a second NMOS transistor connected in series between the Vss line and the Vdd line, the second PMOS transistor having a gate which is connected between the first PMOS transistor and the first NMOS transistor, and the second NMOS transistor having a gate which is connected to the Vdd line; and a clamp NMOS transistor connected between the Vss line and the Vdd line, the clamp NMOS transistor having a gate which is connect between the second PMOS transistor and the second NMOS transistor.