Patent ID: 8947968
Filing Date: 2015-02-03
Classification: G11C

Abstract:
1. A memory having a plurality of modes of operation including a normal mode and a power saving mode, the memory comprising: storage circuitry configured to store a data value; a pair of bitlines for accessing the data value stored by the storage circuitry; bittine precharge circuitry configured, during the normal mode, to selectively couple the bitlines to a precharge node to charge the bitlines to a voltage level of the precharge node and, during the power saving mode, to isolate the bitlines from the precharge node; voltage control circuitry configured to control the voltage level of the precharge node; wherein during the normal mode, the voltage control circuitry is configured to maintain the precharge node at a first voltage level and, during the power saving mode, the voltage control circuitry is configured to maintain the precharge node at a second voltage level less than the first voltage level, wherein the voltage control circuitry is coupled between the precharge node and a first node for supplying the first voltage level and, wherein the voltage control circuitry comprises voltage limiting circuitry configured during the power saving mode to provide a voltage drop between the first node and the precharge node, wherein the voltage limiting circuitry comprises a diode-connected transistor coupled between the first node and the precharge node.