Patent ID: 7440882
Filing Date: 2008-10-21
Classification: G06F

Abstract:
1. A computer implemented method for analyzing transaction level simulation data of an integrated circuit design, comprising: allocating space for a transaction fiber, said transaction fiber comprising one or more transaction blocks and one or more child fibers; plotting said transaction fiber within said allocated space; calculating a maximum number of child levels allowed to be displayed in said allocated space; and graphically displaying one or more compact representations indicating a total number of hidden child levels and relative temporal positions of hidden child blocks for a fiber, which comprises the transaction fiber or the one or more child fibers, within said allocated space when said fiber is in a collapsed state, wherein the fiber is in a collapsed state when the one or more compact representations are displayed without taking plotting space away from other fibers, and wherein the one or more compact representations correspond to an expanded representation which comprises details of at least one of the one or more child fibers that is graphically represented by at least a portion of the one or more compact representations when the at least one of the one or more child fibers is in the collapsed state.