Patent ID: 6333658
Filing Date: 2001-12-25
Classification: H03K

Abstract:
An analog synchronization circuit comprising:a first capacitor;a first current source circuit for starting charging said first capacitor in accordance with a first clock signal and stopping the charging in accordance with a second clock signal delayed from said first clock signal;a second capacitor;a second current source circuit for starting charging said second capacitor in accordance with said second clock signal; anda comparator circuit for comparing charge voltages of said first and second capacitors with each other and generating a timing signal when said charge voltages coincide with each other,said comparator circuit including,a first switch having one end supplied with said charge voltage of said first capacitor,a second switch having one end supplied with said charge voltage of said second capacitor and the other end connected to the other end of said first switch,a third capacitor having one end connected to a common node between said other ends of said first and second switches,a first amplifier circuit having an input node connected to the other end of said third capacitor and an output node from which said timing signal is output, anda third switch for controlling supply of a voltage equivalent to a threshold voltage of said first amplifier circuit to said other end of said third capacitor,wherein when said first and third switches are enabled, said second switch is controlled to be disabled, and when said second switch is enabled, said first and third switches are controlled to be disabled.