Patent ID: 6777300
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A method of forming an integrated circuit, comprising the steps of:forming a polysilicon layer over a gate dielectric over a semiconductor substrate; forming a blocking layer over said polysilicon layer; patterning and etching said polysilicon layer and said blocking layer; then, implanting an initial dose of first conductivity type dopant to form source/drain extension regions in said semiconductor substrate; then, removing said blocking layer; forming sidewall spacers adjacent said polysilicon layer after said step of implanting the initial dose; then, with said sidewall spacers present, implanting an additional dose of first conductivity type dopant, with a deeper stopping distance than said implanting an initial dose step, to form main source/drain regions in said semiconductor substrate; then, depositing a metal layer and reacting said metal layer with portions of said polysilicon layer to form a conductive silicide.