Patent ID: 6916691
Filing Date: 2005-07-12
Classification: H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate, comprising the steps of: providing a substrate; forming a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer over the substrate in sequence, wherein the first patterned metallic layer comprises a plurality of scan lines and a plurality of gates connected to the respective scan lines and the second patterned metallic layer comprises a plurality of data lines and a plurality of source/drains connected to the respective data lines; forming a patterned photoresist layer over the passivation layer, wherein the patterned photoresist layer at least covers the source/drains and its peripheral regions, part of the edges of the patterned photoresist layer has a plurality of thin-out regions with a smaller layer thickness, and each first thin-out region stretches over part of the edge of one source/drain; removing the passivation layer, the amorphous silicon layer and the dielectric layer exposed by the patterned photoresist layer using the patterned photoresist layer as an etching mask to form a plurality of staircase structure that correspond to the first thin-out regions; and forming a plurality of pixel electrodes over the substrate such that each pixel electrode at least covers one of the staircase structures and electrically connects with one of the source/drains.