Patent ID: 8307236
Filing Date: 2012-11-06
Classification: G06F

Abstract:
1. An apparatus to synchronously communicate on a bus that has an associated bus clock, the apparatus for a central processing unit (CPU) that has a CPU clock used internal to the CPU, the apparatus comprising: a control circuit coupled to receive the CPU clock and the bus clock, wherein the control circuit is configured to sample the bus clock a plurality of times per clock cycle of the CPU clock, and wherein the control circuit is configured to detect a phase difference, to a granularity of the samples, between the CPU clock and the bus clock, and wherein the control circuit is configured to detect the phase difference responsive to the samples; and a data path configured to transport data between a CPU clock domain corresponding to the CPU clock and a bus clock domain corresponding to the bus clock, the data path configured to provide at least two different timings on the transported data relative to the CPU clock, and wherein the control circuit is coupled to the data path and is configured to select one of the timings responsive to the detected phase difference, the detected phase difference determined responsive to the samples.