Patent ID: 6160733
Filing Date: 2000-12-12
Classification: G11C

Abstract:
A low voltage and low power static random access memory (SRAM) comprising:an address decoding circuit for receiving an address of said SRAM and for generating address decoding circuit output signals:a memory cell array comprising a plurality of memory cells coupled to a plurality of wordlines and to a plurality of bitline pairs, each of said bitline pairs having a first bitline line and a second bitline line:a sense amplifier circuit;an I/O circuit; anda clock chain circuit for receiving said address decoding circuit output signals and for providing a plurality of control signals and a plurality of precharge signals;wherein said control signals and said precharge signals control said address decoding circuit, said memory cell array, said sense amplifier circuit, and said I/O circuit:said sense amplifier circuit comprisesa sense amplifier precharge device for receiving a first (SAPB) of said precharge signals and for providing sense amplifier precharge device output signals; anda sense amplifier for receiving a first (SAC) of said control signals and said sense amplifier precharge device output signals, and for providing sense amplifier output signals:said sense amplifier precharge device comprises p-channel transistors for receiving said first (SPAB) precharge signal, a first logic level of said first precharge signal activates said transistors, and a second logic level of said first precharge signal deactivates said transistors; anda first of said p-channel transistors has a first source, a first drain, a first gate, and a first bulk;a second of said p-channel transistors has a second source, a second drain, a second gate, and a second bulk;a third of said p-channel transistors has a third source, a third drain, a third gate and a third bulk; andsaid first gate, said second gate, and said third gate are connected for receiving said first (SAPB) precharge signal; said first source, said third source, said first bulk, said second bulk, and said third bulk are connected to a memory voltage source; said first drain is coupled to said second source for providing a first of said sense amplifier precharge device output signals; and said second drain is coupled to said third drain for providing a second of said sense amplifier precharge device output signals.