Patent ID: 8164934
Filing Date: 2012-04-24
Classification: G11C

Abstract:
1. A content addressable memory comprising: a plurality of entries each having a plurality of content addressable memory cells; a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry; a search data bus coupled in parallel to the entries, for transferring search data in parallel to the entries; and a plurality of match amplifiers, arranged corresponding to the respective match lines, each including (i) a precharge circuit for precharging a corresponding match line to a precharge voltage level, (ii) an amplifier circuit having a first node receiving a voltage on the corresponding match line and a second node receiving a sense reference voltage produced by changing a voltage at the precharge voltage level through use of a capacitance element, comparing the voltages on the first and second nodes and producing a signal indicating a result of comparison, and (iii) an isolation gate for confining charges on the first and second nodes before activation of said amplifier circuit, wherein said precharge circuit further precharges a reference voltage line coupled to said second node via said isolation gate to the precharge voltage level, and each match amplifier further includes a capacitance element, a first transistor for precharging said capacitance element to a ground voltage level in an operation of the precharging, and a second transistor for coupling said capacitance element to said reference voltage line according to a voltage down instructing signal, said voltage down instructing signal being activated before confinement of the charges by said isolation gate.