Patent ID: 6172919
Filing Date: 2001-01-09
Classification: G11C

Abstract:
A semiconductor memory device comprising:an array of memory cells arranged in columns and rows;plural pairs of bit lines, each said pair of bit lines being provided for associated one of the columns in the array;a pair of data lines, through which data to be written into, or read out from, the array are transferred;a control signal generator for generating an internal clock signal and a read/write switching signal in response to an external clock signal and a control input;a read/write pulse width controller for generating a read/write pulse width control signal in response to the internal clock signal and the read/write swtiching signal, the read/write pulse width control signal having a pulse width variable with whether the mode of operation is reading or writing;a column decoder for selecting one of the columns in the array in response to a column address, and asserting a column-select signal associated with the selected column while the read/write pulse width control signal is activated;a plurality of column-select gates, each said column-select gate being provided for associated one of the plural pairs of bit lines and connecting the associated pair of bit lines to the pair of data lines while the associated column-select signal is asserted;equalizing means for equalizing potentials on the pair of data lines while none of the pairs of bit lines are connected to the pair of data lines; anda write amplifier for driving the pair of data lines in response to data supplied during writing,wherein the read/write pulse width controller comprises delay means, and produces a one-shot pulse, having an active pulse width determined by a delay time caused by the delay means, as the read/write pulse width control signal during reading.