Patent ID: 6427191
Filing Date: 2002-07-30
Classification: G06F

Abstract:
A cache memory, comprising:a first cache memory stage to access cache data; at least two address ports coupled to the first cache memory stage, wherein each of the at least two address ports is to receive an input for a cache address, including a first data address on one port and a second data address on another, wherein the first cache memory stage is to access a first data set and a second data set corresponding to the first data address and the second data address, respectively, on a first clock cycle of a processor clock signal, wherein the first cache memory stage is to receive a new first data set and a new second data set at a consective clock cycle of the processor clock signal; and a second cache memory stage, wherein the second cache memory stage is to receive the first data set and the second data set, is to manipulate the first data set and the second data set and to output a first manipulated data set and a second manipulated data set, respectively, to a first arithmetic logic unit (ALU) or a first register file and a second arithmetic logic unit (ALU) or a second register file, respectively, all in a second clock cycle of the processor clock signal.