Patent ID: 6584536
Filing Date: 2003-06-24
Classification: H04L

Abstract:
A circuit structure for accelerating bus transaction status register access in multi-clock systems, comprising:a first electronic data storage device, having an input functionally connected to a voltage source, an output, an enable input for accepting a first chip enable signal, a clock input functionally connected to an external system clock, and a clear input; a second electronic data storage device, having an input functionally connected to the output of the first data storage device, an output, and a clock input functionally connected to a host system clock; a first control circuit for clearing the output of the first data storage device, having an output functionally connected to the clear input of the first data storage device, a first input functionally connected to the output of the second data storage device, and a second input; a third electronic data storage device, having an input functionally connected to the output of the second data storage device, an output functionally connected to a host system and to the second input of the first control circuit, an enable input, and a clock input functionally connected to the host system clock; and a second control circuit for enabling said third electronic data storage device, having an output functionally connected to the enable input of the third data storage device, a first input functionally connected to the output of the second data storage device, a second input for accepting a write enable signal from the host system, and a third input for accepting a data-in status bit from the external system.