Patent ID: 8837235
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. A local evaluation circuit for a memory array, comprising: a first NAND gate having a first input, a second input, and an output, wherein a first local bit line of a first column of the memory array is coupled to the first input of the first NAND gate, a second local bit line of the first column is coupled to the second input of the first NAND gate, and the output of the first NAND gate is coupled to a global bit line, and wherein the first column of the memory array includes a plurality of memory cells and the first and second local bit lines are coupled to different clusters of the memory cells in the first column; a second NAND gate having a first input, a second input, and an output, wherein a third local bit line of a second column of the memory array is coupled to the first input of the second NAND gate, a fourth local bit line of the second column is coupled to the second input of the second NAND gate, and the output of the second NAND gate is coupled to the global bit line, and wherein the second column of the memory array includes a plurality of memory cells and the third and fourth local bit lines are coupled to different clusters of the memory cells in the second column; a first switch configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal; a second switch configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal; a third switch configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal; and a fourth switch configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.