Patent ID: 6829165
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a memory cell array having multiple twin memory cells arrayed at least in a row direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; a word line shared by the word gates of the multiple twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in a column direction; multiple control gate lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first control gate of the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second control gate of the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an access control circuit that regulates operations of the word line, the multiple bit lines, and the multiple control gate lines to control a reading operation of information; and a detection circuit that detects the information read via the multiple bit lines, in the non-volatile semiconductor memory device, in the case of reading information from the second non-volatile memory element of an (i)-th twin memory cell and from the first non-volatile memory element of an (i+1)-th twin memory cell in the row direction, where i is an integer of not less than 1, the access control circuit setting a reading word line-selecting voltage to the word line connecting with the word gate of the (i)-th twin memory cell and with the word gate of the (i+1)-th twin memory cell, setting a reading control gate voltage to the second control gate of the second non-volatile memory element of the (i)-th twin memory cell via an (i)-th control gate line connecting with the second control gate, and setting an override voltage to the first control gate of the first non-volatile memory element of the (i)-th twin memory cell via an (iâˆ’1)-th control gate line connecting with the first control gate, while setting an override voltage to the second control gate of the second non-volatile memory element of the (i+1)-th twin memory cell via an (i+1)-th control gate line connecting with the second control gate, the detection circuit sensing an (iâˆ’1)-th bit line connecting with the first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (iâˆ’1)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell, sensing an (i+1)-th bit line connecting with the second non-volatile memory element of the (i+1)-th twin memory cell, so as to detect an electric current running between the (i+1)-th bit line and the (i)-th bit line connecting with the first non-volatile memory element of the (i+1)-th twin memory cell, via the first non-volatile memory element of the (i+1)-th twin memory cell, thereby reading a piece of information stored in the second non-volatile memory element of the (i)-th twin memory cell together with a piece of information stored in the first non-volatile memory element of the (i+1)-th twin memory cell.