Patent ID: 6635521
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method of fabricating a CMOS device in which p- and n-type thin film transistors are formed, comprising the steps of:non-selectively doping the whole of a thin film with p-type impurities, said thin film to be an active semiconductor layer including prospective regions to form said p- and n-type thin film transistors; selectively doping only the prospective region to form said n-type thin film transistor with p-type impurities at a higher concentration than that in said step of non-selectively doping; annealing said thin film to activate the p-type impurities contained therein; forming a gate insulating film pattern on at least a portion of said prospective regions for forming said p- and n-type thin film transistors after said non-selective doping step or said selective doping step; and forming element structures in said thin film after said nonselective doping step or said selective doping step, each of said structures including a gate electrode pattern and source/drain patterns which are separated from said gate electrode pattern by said gate insulating film pattern, wherein threshold voltages of said p- and n-type thin film transistors are independently set by said step of non-selectively doping and said step of selectively doping.