Patent ID: 7633110
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. A memory cell comprising: a semiconductor substrate; an isolation region in the semiconductor substrate, wherein the isolation region includes a trench that extends into the semiconductor substrate; a sidewall implanted to a first conductivity type within sides of the trench thereby substantially circumscribing the trench, the substrate substantially circumscribing the sidewall and having a second conductivity type different than the first conductivity type; an at least semiconductive structure of a second conductivity type within the trench of the isolation region; a dielectric layer disposed on all sides within the trench between the at least semiconductive structure and the sidewall; and a gate structure directly vertically above at least a portion of the sidewall and the at least semiconductive structure, and extending laterally on the semiconductor substrate to define a channel region of the first conductivity type in the substrate horizontally adjacent to and in direct electrical contact with the sidewall, the dielectric layer electrically insulating the at least semiconductive structure from the channel region.