Patent ID: 8198174
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A method of forming interconnected air channels within semiconductor wafers comprising the steps of: processing an upper wafer to form one or more semiconductor devices and circuitry for connecting the one or more semiconductor devices in a device layer located on a front surface of the upper wafer; forming a plurality of air vias in a portion of the upper wafer and a plurality of through-silicon vias (TSVs) in another portion of the upper wafer; filling each of the plurality of air vias with a material comprising one of a conductive material or a dummy material and filling each of the plurality of TSVs with a conductive material; forming a protective structure on the air vias and a bonding pad on the TSVs; forming a stud for wafer bonding on the bonding pad located on the TSVs; removing at least a portion of the protective structure and the conductive material from inside the air vias, thereby forming a plurality of vertical air channels and an opening exposing the plurality of vertical air channels; processing a lower wafer to form one or more semiconductor devices and circuitry for connecting the one or more semiconductor devices in a device layer located on a front surface of the lower wafer; forming a bonding pad on the device layer located on a front surface of the lower wafer; depositing an insulating layer on the lower wafer, including on the bonding pad; forming an opening in the insulating layer exposing the bonding pad; aligning and bonding the upper wafer and the lower wafer to each other, thereby forming an embedded air channel interconnect network which includes the vertical air channels and a horizontal air channel which are interconnected to each other within at a bonding interface between the bonded upper wafer and lower wafer; thinning a backside of the upper wafer to expose the vertical air channels and the TSVs; and forming a passivation layer on the exposed surface of the backside of the upper wafer.