Patent ID: 8266338
Filing Date: 2012-09-11
Classification: G06F

Abstract:
1. A direct memory access (DMA) controller comprising: a transmit circuit configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a descriptor data structure in memory, wherein a given DMA descriptor that describes a DMA transfer includes data that defines a source and a target of the DMA transfer, and wherein the transmit circuit is configured to generate read operations to read data from the source to be transmitted to the target responsive to the given DMA descriptor; a data flow control circuit coupled to the transmit circuit and configured to control processing of DMA descriptors by the transmit circuit; and one or more registers coupled to the data flow control circuit, wherein the one or more registers are configured to store a set of flags, and wherein a first control descriptor is codable to specify a first flag in the set of flags, and wherein, responsive to the first control descriptor in the descriptor data structure, the data flow control circuit is configured to update the first flag to a first value specified by the first control descriptor.