Patent ID: 7774577
Filing Date: 2010-08-10
Classification: G09G,G11C

Abstract:
1. A semiconductor integrated circuit device in which circuits are integrated on a semiconductor substrate, the semiconductor integrated circuit device comprising: a memory array in which memory unit areas having a plurality of cells connected to word lines and bit lines are arranged in the form of a matrix, each of the memory units being associated to a single column address; and an input/output unit that reads, in response to a read command, a plurality of data items from a first memory unit associated to a first column address and a second memory unit associated to a second column address based on a first column address, wherein the input/output unit read a part of first plurality of data items corresponding to a first column address and a part of second plurality of data items corresponding to a second column address based on first combination information indicating a start position for reading the first memory unit area and second combination information indicating a method for reading the first memory unit area and the second memory unit area.