Patent ID: 9136325
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A device structure for reducing leakage current of semiconductor devices with a floating buried layer, comprising: a semiconductor substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (S-JTE) and a scribe street; the protected device and the S-JTE are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers; the doped trench is penetrated through the second epitaxial layer and connected to the split floating buried layer, the first epitaxial layer is located on the semiconductor substrate, a space between the split floating buried layer and the scribe street is no less than 20% of the thickness of maximum depletion layer of ideal parallel-plane abrupt junction at a specific voltage.