Patent ID: 6342409
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method of manufacturing a polycrystalline silicon thin film transistor, comprising;forming a buffer layer on a substrate; depositing on the buffer layer an impurity-doped amorphous silicon layer and patterning the impurity-doped amorphous silicon layer into source and drain regions, the source and drain regions being spaced apart from each other; forming a metal layer over the entire substrate while covering the source and drain regions; depositing an intrinsic amorphous silicon layer on the metal layer; applying a voltage to the intrinsic amorphous silicon layer to simultaneously crystallize the intrinsic amorphous silicon layer and the source and drain regions so that the intrinsic amorphous silicon layer is converted into a polycrystalline silicon layer; and patterning the polycrystalline silicon layer to form an active layer so that part of the polycrystalline silicon layer overlaps at least a portion of the source and drain regions.