Patent ID: 8566567
Filing Date: 2013-10-22
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of channels of a processor to store a plurality of state information corresponding to a plurality of instruction threads, each channel having a different priority and to specify a trigger-action mapping for a scenario associated with the channel responsive to which a yield event is to occur to transfer execution to a yield event service routine associated with the channel, and a block indicator to provide an override of the yield event, wherein if multiple yield events occur simultaneously, a highest priority channel is selected for servicing; a scenario detection unit to detect performance characteristics via interpretation of the occurrence of events within the processor, a combination of events to be determined by the plurality of state information; and a profiling unit to generate a profile of the combination of events according to a user model, and a profile method generator to translate the profile into a method, wherein user code of at least one of the plurality of instruction threads is to be modified within a managed run-time environment (MRTE) during run-time of the at least one instruction thread.