Patent ID: 7414903
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: bit lines; word selecting lines; a plurality of memory cells arranged in a matrix, one of said memory cells including a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node thereof coupled to one of the word selecting lines and a source/drain node thereof coupled to one of the bit lines, and the MIS transistor becoming conductive in response to a first state of said one of the word selecting lines and becoming nonconductive in response to a second state of said one of the word selecting lines; and a test circuit coupled to said one of the bit lines to sense a current running through the MIS transistor, said test circuit configured to indicate error in response to either a detection of presence of said current when said one of the word selecting lines is in the second state or a detection of absence of said current when said one of the word selecting lines is in the first state.