Patent ID: 6566920
Filing Date: 2003-05-20
Classification: H03L

Abstract:
A PLL (phase locked loop) comprising:a phase frequency detector detecting a phase of an input signal and outputting an up signal and a down signal; a lock detecting circuit detecting whether the PLL is locked using the up and down signals, the lock detecting circuit including a NOR gate for performing a logical NOR operation on the up signal and the down signal, and an inverter for inverting an output signal of the NOR gate; a charge pump pumping the up signal and the down signal; first and second voltage dividers respectively receiving an output signal of the charge pump; first and second switching means controlling output signals of the first and second voltage dividers, respectively, using an output signal of the lock detecting circuit and selectively outputting the output signals of the first and second voltage dividers; a capacitor connected between an output terminal connected in common to the first and second switching means and a ground voltage; and a voltage controlled oscillator feeding back a signal to the phase frequency detector based on the output signals of the first and second switching means.