Patent ID: 6240049
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A synchronous semiconductor storage device, comprising:a plurality of memory blocks into which a plurality of memory cells arranged in a matrix form have been divided every plural number of columns;word lines each activating the memory cells of an identical row in each memory block;bit lines each connected to one terminal of the memory cells of an identical column of each memory block;virtual GND lines each connected to the other terminal of the memory cells of an identical column of each memory block;a column selector that selects any one of the memory blocks on the basis of an input column address in a read operation;a sense amplifier that holds and amplifies a signal representing a level difference between a reference line and the bit line of the memory block selected by the column selector;a precharge level supply circuit that supplies a precharge level to the bit lines and the virtual GND lines of the memory blocks other than the memory block selected by the column selector; anda disconnecting circuit that, upon latching of the signal representing the level difference between the reference line and the bit line by the sense amplifier in the read operation, disconnects the bit line and the reference line from the sense amplifier until a next read operation and also disconnects the virtual GND line from the ground potential until the next read operation.