Patent ID: 9128781
Filing Date: 2015-09-08
Classification: G06F

Abstract:
1. A processor comprising: a first core to execute a first software thread; a second core to execute a second software thread; and a shared memory access monitoring and recording logic of the first core, the shared memory access monitoring and recording logic comprising: a memory access monitor logic to monitor accesses to memory by the first software thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads; a chunk generation logic coupled with the memory access monitor logic, the chunk generation logic to generate chunks to represent committed execution of the first software thread, each of the chunks to include a number of instructions of the first software thread executed and committed and a time stamp, the chunk generation logic to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic; and a chunk buffer coupled with the chunk generation logic, the chunk buffer to temporarily store the chunks until the chunks are transferred out of the processor.