Patent ID: 7516384
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A test device for a semiconductor memory device, the test device comprising: a clock frequency multiplier configured to generate an internal clock signal having a frequency higher than an external clock signal received from an external test device; a data input buffer configured to buffer test pattern data that is provided from the external test device and that is synchronized to the external clock signal, the data input buffer further configured to output the buffered test pattern data; a test data generator configured to generate test data responsive to the buffered test pattern data and one of a first control signal and a second control signal, the first control signal provided by the external test device, the second control signal generated in response to an internal setting data; and a data output buffer configured to synchronize the test data to the internal clock signal and configured to output the synchronized test data to a memory core of the semiconductor memory device.