Patent ID: 6180881
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A stackable chip carrier comprising the combination of:a base layer having opposed upper and lower surfaces and a conductive pattern disposed on at least one of the upper and lower surfaces thereof;a top layer mounted to the upper surface of the base layer and having a top layer central opening and at least one top layer aperture disposed therein;a center layer mounted to the lower surface of the base layer and having a center layer central opening and at least one center layer aperture disposed therein, the center layer aperture being generally aligned with the top layer aperture;at least one stacking aperture disposed within the carrier, the stacking aperture having an upper portion defined by the top layer aperture and a lower portion defined by the center layer aperture; andat least one conductive element disposed within the lower portion of the stacking aperture and electrically connected to the conductive pattern;the conductive element being secured within the lower portion of the stacking aperture via a quantity of conductive epoxy and sized to protrude from an exposed surface of the center layer.