Patent ID: 8923050
Filing Date: 2014-12-30
Classification: G06F,G11C,H01L

Abstract:
1. A non-volatile memory, comprising: memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a plurality of global bit lines elongated in the y-direction; and a vertical switch in line with each local bit line along the z-direction to switch one end of the local bit line to a corresponding global bit line, said vertical switch being a thin film transistor with a transistor junction in the z-direction in line with the local bit line and having a select gate, the select gate being insulated from said plurality of local bit lines and having a thickness extending along the x-direction between the local bit line and adjacent local bit lines on each side of the local bit line.