Patent ID: 6530076
Filing Date: 2003-03-04
Classification: G06F

Abstract:
A processor wherein:said processor comprising: a microcode engine capable of executing microcode instructions and comprising: a microcode instruction address counter that provides a set of microcode instruction address signals; a microcode store, comprising a microcode patch memory, wherein: the microcode store responds to the set of microcode instruction address signals, the microcode store contains a plurality of microcode instruction words containing microcode instructions for execution by the microcode engine; each of the plurality of microcode instruction words has a plurality of microcode instruction bits, and a one of the plurality of microcode instruction bits is a trace enable bit having a first state and a second state; a trace memory containing a plurality of trace words; a trace memory controller that controls writing a selected set of trace memory input signals as a set of values to the trace memory; and a circuit for routing a first set of signals to the trace controller as a first set of trace memory input signals for tracing when the microcode engine executes a microcode instruction having its trace enable bit in the first state.