Patent ID: 8943119
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A system for multiplying matrix multiplicand data by vector multiplier data, the system comprising: a memory for storing the matrix multiplicand data and a register for storing the vector multiplier data, the matrix multiplicand data having a bit width wider than the vector multiplier data; a multiplier formatter coupled to the memory for receiving the vector multiplier data and partitioning it into a plurality of vector data elements; a multiplicand formatter coupled to the memory for receiving the matrix multiplicand data and partitioning it into a plurality of matrix multiplicands; a group of multiplier strips producing partial products; a group of alignment stages, each stage including a bit-aligning multiplexer; a group of reduction stages; a final carry propagation stage for providing a result of multiplication of the matrix multiplicand data by the vector multiplier data; and wherein: the matrix multiplicand data and the vector multiplier data include floating point data having exponents and significand fields; and each reduction stage aligns n-bit partial products to 2n-bit alignment thereby producing 2n-bit aligned partial products before adding the 2n-bit aligned partial products to produce a 2n-bit partial product.