Patent ID: 8559236
Filing Date: 2013-10-15
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of blocks, each of the blocks including a plurality of memory cells; and a control unit configured to perform an erase operation to a selected block, the erase operation including a first phase, a second phase, a third phase, a fourth phase, a fifth phase, and a sixth phase, the control unit configured to perform a first operation supplying a first erase voltage to the selected block and to perform a first verify operation supplying a first verify voltage to the selected block, in the first phase, the control unit configured to perform a second operation supplying a second erase voltage to the selected block and to perform a second verify operation supplying a second verify voltage to the selected block, in the second phase after the first phase, the second erase voltage being higher than the first erase voltage, the control unit configured to perform a third operation supplying a third erase voltage to the selected block, in the third phase after the second phase, the control unit configured to interrupt the erase operation when the control unit receives a first command for interrupting the erase operation during the third operation, the third erase voltage being higher than the second erase voltage, the control unit configured to perform a third verify operation supplying a third verify voltage to the selected block when the control unit receives a second command for resuming the erase operation after the third phase, in the fourth phase after the third phase, the control unit configured to perform the a fourth operation supplying a fourth erase voltage to the selected block and to perform a fourth verify operation supplying a fourth verify voltage to the selected block, in the fifth phase after the fourth phase, the control unit configured to perform a fifth operation supplying a fifth erase voltage to the selected block and to perform a fifth verify operation supplying a fifth verify voltage to the selected block, in the sixth phase after the fifth phase, the fourth erase voltage and the fifth erase voltage being equal to or higher than the third erase voltage.