Patent ID: 8278146
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A method of manufacturing a package-on-package chip package, the method comprising: placing an integrated circuit proximate a top surface of a substrate, the substrate having a plurality of top bond pads and a plurality of bottom bond pads; forming electrical connections between the integrated circuit and a first subset of the plurality of top bond pads; encapsulating the integrated circuit in an encapsulant to form a cap on at least a portion of the top surface of the substrate, the cap having a height measured from the top surface of the substrate to a top surface of the cap above the substrate, the substrate having a second subset of the plurality of top bond pads positioned outside of a perimeter of the cap; and forming a plurality of extension features from the encapsulant on at least a portion of the top surface of the substrate, the plurality of extension features extending from the cap to a perimeter of the substrate, the plurality of extension features having a height measured from the top surface of the substrate to a top surface of the plurality of extension features above the substrate that is less than the height of the cap, the substrate having at least two top bond pads of the second subset not covered by the plurality of extension features; placing a top chip package proximate the substrate; and forming electrical connections between the top chip package and the at least two top bond pads of the second subset.