Patent ID: 6746910
Filing Date: 2004-06-08
Classification: G11C,H01L

Abstract:
A method of fabricating a self-aligned cross-point memory array, comprising:preparing a substrate, including forming supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region; depositing a barrier meal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer on the bottom electrode layer; patterning and etching to move portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench, thereby forming plural P+/N junction; patterning and etching to remove portions of the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layers; patterning and etching the top electrode layer; and completing the self-aligned cross-point memory array.