Patent ID: 8995455
Filing Date: 2015-03-31
Classification: H04L

Abstract:
1. A network device, comprising: a plurality of base-ports, where each base-port is coupled to a plurality of network links and each base-port has a plurality of sub-ports configured to operate independently as a port for sending and receiving information using one of the plurality of network links at a plurality of rates complying with a plurality of protocols; a memory storage device having a plurality of storage locations that are used to store packets received by the plurality of sub-ports; wherein the memory storage device is shared among the plurality of sub-ports such that each sub-port is provided access to one or more storage locations within a certain phase of a system clock cycle for the network device; a plurality of first stage buffers for each sub-port for staging information before the information is stored at one of the storage locations of the memory storage device; wherein a packet or a portion thereof received by a sub-port is stored at one of the storage locations when the sub-port has access to the memory device; and addresses for the memory storage locations are scrambled such that a different one of the storage locations is available to the sub-port for a next write operation in a next phase when the sub-port is given access to the memory storage device; and a second stage buffer shared among the plurality of sub-ports and used for staging information between the plurality of first stage buffers and the memory storage device when there is conflict for data at any first stage buffer of the plurality of the first stage buffers.