Patent ID: 7522463
Filing Date: 2009-04-21
Classification: G11C

Abstract:
1. A circuit, comprising: a first stage including a first portion of a first mirror configuration with a first node for receiving a cell current derived from a memory cell, a first portion of a second mirror configuration with a first output node for receiving a reference current derived from a reference cell, and a first pass gate coupled between the first node and the first output node; a second stage including a second portion of the second mirror configuration with a second node for receiving the reference current, a second portion of the first mirror configuration with a second output node for receiving the cell current, and a second pass gate coupled between the second node and the second output node; and a comparator including comparator input nodes coupled to the first and second output nodes for providing an output indicative of a state of the memory cell based on a first voltage at the first output node and a second voltage at the second output node.