Patent ID: 7434129
Filing Date: 2008-10-07
Classification: G01R,G11C

Abstract:
1. A method of generating a partial good integrated circuit, the method comprising: providing an integrated circuit having: isolating said macro-circuits from other circuits of said integrated circuit by connecting scan-in and scan-out pins dedicated to each macro-circuit of said multiplicity of macro-circuits to respective pads of said scan-in I/O pads and scan-out I/O pads; performing a first testing operation of each macro-circuit of said multiplicity of macro-circuits prior to a fuse programming operation; performing a second testing operation on each repairable circuit of said one or more repairable circuits prior to said fuse programming operation; programming fuses in said first set of fuses in order to store data indicating which macro-circuits failed said first testing operation; programming fuses in said second set of fuses in order to store data indicating which repairable circuits failed said second testing operation; for each macro-circuit of said multiplicity of macro-circuits that failed said first testing operation, permanently preventing utilization of the entire failing macro-circuit during operation of said integrated circuit based on data stored in said first set of fuses and configuring said integrated circuit to utilize only macro-circuits that passed said testing; and for each repairable circuit of said one or more repairable circuits replacing failing circuit portions of said repairable circuits with redundant good circuit portions based on data stored in said second set of fuses.