Patent ID: 6146917
Filing Date: 2000-11-14
Classification: B81C

Abstract:
A process for the micromachining, and simultaneous encapsulating of a plurality of microstructures fabricated on a single planar silicon wafer, comprising:defining a plurality of fusion bond surround areas on said planar silicon wafer;fabricating a plurality of electronically active microstructures within said fusion bond surround areas such that said fusion bond surround areas are maintained in a substantially mutual co-planar condition;providing electrical communication between electronically active portions of said microstructures and a plurality of microstructure-associated lead bond pads exterior to said fusion bond surround areas surrounding said microstructures by fabricating a plurality of conductive pathways between said microstructures and said associated bond pads through said fusion bond surround areas by doping portions of said fusion bond surround areas with a dopant material such that the conductive pathways are flush with the fusion bond surround;positioning an encapsulating wafer on said planar silicon wafer, portions of said encapsulating wafer contacting said fusion bond surround areas;directly bonding said planar and encapsulating wafers to form a bond along said fusion bond surround areas and between said wafers, such that said microstructures are located in cavities defined between surfaces on said planar silicon wafer and said encapsulating wafer.