Patent ID: 7564736
Filing Date: 2009-07-21
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a plurality of memory blocks each having memory cells and a word line connected to the memory cells; and word control circuits formed corresponding to the memory blocks, respectively, and which each activates/inactivates level of the word line, wherein each of the word control circuits includes: a word decoder activating a word control signal to a low level voltage during an access period of the corresponding memory block and inactivating the word control signal to a high level voltage during a non-access period of the corresponding memory block; a word driver having a transistor that receives the word control signal at a gate and has its output connected to the word line, and which activates the word line selected by an address during the access period and inactivates the word line during the non-access period by using the transistor; and a voltage control circuit that performs a first operation connecting a high level voltage line to supply the high level voltage for the word control signal to the word decoder to a first high voltage line to which a first high voltage is supplied during the access period of the corresponding memory block and connecting the high level voltage line to a second high voltage line to which a second high voltage lower than the first high voltage is supplied during the non-access period of the corresponding memory block.