Patent ID: 6054342
Filing Date: 2000-04-25
Classification: H01L

Abstract:
A process for making a CMOS IC including a p-type tub tie region having a p-type cap portion and an n-type pedestal portion and an n-type tub tie region having an n-type cap portion and an p-type pedestal portion, each of said cap portions having a central section and peripheral sections with the former more heavily doped than the latter, said process comprising:forming a multiplicity of separate isolating regions in the surface of a semiconductor body, the spaces between some isolating regions defining the location of PMOS or NMOS transistors and the spaces between other isolating regions defining the locations of said tub-tie regions, each of said isolating regions adjacent a tub-tie having a protrusion which extends partially over the surface of said tub-tie region, thereby defining peripheral sections of said cap portion under said protrusions and a central section therebetween,forming a first mask over the location where the central section of a p-type tub-tie region is to be formed and over the isolating regions, including the protrusions, adjacent the locations where an n-type tub-tie region is to be formed,sequentially performing a first cycle of ion implantation steps without intervening mask steps, said implantation steps including at least (1) implanting n-type dopant to a relatively shallow depth in the S/D regions of the NMOS transistors and simultaneously in the central section of the n-type tub-tie region, said protrusions preventing said n-type dopant from penetrating therethrough into said peripheral sections of said p-type tub-tie region, and (2) implanting p-type dopant to relatively larger depths through said isolating regions, including said protrusions, to form a p-type tub of the NMOS transistors and to dope p-type said peripheral portions of said p-type tub-tie region, and simultaneously to form said p-type buried pedestal portion of said n-type tub-tie region of the PMOS transistors,removing said first mask,forming a second mask over the location where the central section of an n-type tub-tie is to be formed and over the isolating regions, including the protrusions, adjacent the locations where an p-type tub-tie region is to be formed,sequentially performing a second cycle of ion implantation steps without intervening mask steps, said implantation steps including at least (3) implanting p-type dopant to a relatively shallow depth in the SID regions of the PMOS transistors and simultaneously in the central section of the p-type tub-tie region, said protrusions preventing said p-type dopant from penetrating therethrough into said peripheral sections of said n-type tub-tie region, and (4) implanting n-type dopant to relatively larger depths through said isolating regions, including said protrusions, to form an n-type tub of the PMOS transistors and to dope n-type said peripheral portions of said n-type tub-tie region, and simultaneously to form said n-type buried pedestal portion of said p-type tub-tie region of the NMOS transistors,at least a top section of each of said pedestal portions being formed so as to surround the corresponding cap portion so that a conducting path is formed between said cap portion and the corresponding tub of the said transistors.