Patent ID: 6052008
Filing Date: 2000-04-18
Classification: H03K

Abstract:
A circuit, comprising:an inverting circuit coupled to a first input signal for generating and outputting a second signal, the second signal is a complement of the first input signal;a logic circuit comprising,an output, anda first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output,a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output;a second n-channel FET having a gate electrode, the second n-channel FET operable for receiving said first signal at the gate electrode, and wherein the second n-channel FET is coupled to the output, and wherein the first signal is a dynamic input signal; anda second p-channel FET having a gate electrode, the second p-channel FET operable for receiving a clock signal at the gate electrode and coupled to the output of the first logic circuit.