Patent ID: 6828812
Filing Date: 2004-12-07
Classification: G01R,H01L,H05K

Abstract:
An apparatus for testing a semiconductor die having a plurality of pads comprising:a plate; a substrate on the plate comprising a surface and a plurality of contacts on the surface configured to electrically contact the pads; and a biasing member on the plate configured to bias the contacts and the pads together with a force; the plate, the substrate and the biasing member configured such that the die can be placed on the substrate and biased against the substrate with the contacts in electrical contact with the pads; each contact comprising a bump on the substrate having a height on the surface and a plurality of raised portions dimensioned to penetrate into a pad to a penetration depth less than a thickness of the pad, the bump dimensioned to limit further penetration of the raised portions into the pad at the force.