Patent ID: 7464295
Filing Date: 2008-12-09
Classification: G01R,G06F,G11C

Abstract:
1. A method for testing and debugging an embedded device under test, the method comprising: loading an instruction into a parameterized shift register of each of a plurality of BIST modules, each of said plurality of BIST modules coupled to respective an individual one of a plurality of embedded memory modules comprising the embedded device under test; determining an identity of each of said instruction loaded into said parameterized shift register of each of said plurality of BIST modules; generating a separate test signal from each of said plurality of BIST modules corresponding to said determined identity of said instruction loaded in said each of said plurality of BIST modules, said each one of said generated test signals causing control and execution of the testing and debugging of a corresponding one of each of said plurality of embedded memory modules comprising the embedded device under test; and loading test results from said each one of said plurality of embedded memory modules into said parameterized shift register of said each of said plurality of BIST modules coupled to said individual one of said plurality of embedded memory modules.