Patent ID: 6528848
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A semiconductor device comprising:a P type silicon substrate, a P type silicon semiconductor layer situated to one main surface of the substrate and having an impurity concentration lower than that of the substrate, a first N type region and a second N type region disposed being spaced from each other within a main surface of a semiconductor layer, a third N type region situated between the first N type region and the second N type region in the main surface of the semiconductor region, being spaced apart from the first N type region and in contact with the second N type region, and having an impurity concentration lower than that of the second N type region, a gate electrode disposed by way of a gate insulation film and situated between the first N type region and the third N type region on the main surface of the semiconductor layer to be formed with a channel, overlapping at the ends thereof on the first region and the third region respectively, and terminating on the first region and the third region respectively, a first electrode and a second electrode connected with the first region and the second region, respectively and a third electrode connected with the other main surface of the semiconductor substrate opposite to one main surface in which the distribution of the impurity concentration in the semiconductor layer situated between the first N type region and the third N type region comprises a P type distribution area increasing from the surface of the semiconductor layer to the semiconductor substrate and an N type distribution area overlapping on the P type distribution area and decreasing from the surface of the semiconductor layer to the semiconductor substrate.