Patent ID: 9053283
Filing Date: 2015-06-09
Classification: G06F,H01L

Abstract:
1. A method, comprising: defining standard cells including at least one transistor and polysilicon dummy structures formed on cell edges; forming a pre-layout netlist schematic from an input gate level netlist using the standard cells, wherein the pre-layout netlist schematic does not include the polysilicon dummy structures; using the gate level netlist, performing using a processor an automated place and route process to form a layout netlist for fabricating an integrated circuit using the standard cells; laying out the standard cells and laying out routing connections between the standard cells to form a layout for the integrated circuit, using the layout netlist; extracting from the layout for the integrated circuit a post-layout netlist schematic, the post-layout netlist schematic including a MOS device for each polysilicon dummy structure of a standard cell in the layout netlist; and while using a filter to block the MOS devices corresponding to the polysilicon dummy structures from the post-layout netlist schematic, comparing the pre-layout netlist schematic to the post-layout netlist schematic.