Patent ID: 6477080
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A method for forming a memory cell, the method comprising:forming vertical bars of semiconductor material on a surface of a semiconductor wafer, wherein the bars have vertically aligned first source/drain, body and second source/drain regions; separating out individual pillars of semiconductor material from the vertical bars to form vertical transistors, each transistor being formed from a single pillar of semiconducting material; coupling vertical transistors from adjacent bars with body regions of different conductivity types to form inverters, forming each inverter including: interconnecting the gates of the vertical transistors with a gate contact, the gate contact acting as an input of the inverter; interconnecting the first source/drain regions from the vertical transistors from adjacent bars with body regions of different conductivity types with a shunt, the shunt acting as an output of the inverter; cross-coupling the inverters to form a flip-flop; and coupling vertical, access transistors to inputs/outputs of the flip-flops.