Patent ID: 6278711
Filing Date: 2001-08-21
Classification: H04L,H04Q

Abstract:
An apparatus for manipulating ATM cells comprising:a memory array comprising a DRAM in which an entire ATM cell can be read or written, said memory array is comprised of N memory sub-arrays, where N.gtoreq.2 and is an integer, each memory sub-array having rows and columns of memory cells, with there being enough memory cells to store all the bits of an ATM cell, at least one row or column has enough memory cells to store all the bits of an ATM cell, each row is RW bits wide and is greater than or equal to the number of bits in an ATM cell, each column is CW bits wide, where CW.gtoreq.1; anda mechanism for reading or writing the entire ATM cell from or into the memory array, the reading or writing mechanism includes a row reading or writing mechanism for reading or writing the ATM cell into a row of the memory array, the reading or writing mechanism includes a mechanism for providing cells to the memory array said providing mechanism in communication with the row reading or writing mechanism, the row reading or writing mechanism includes a row decoder mechanism for decoding and selecting a row of the memory array, said row decoder mechanism in communication with said memory array the row reading or writing mechanism includes a mechanism for selecting a memory sub-array in communication with the memory array and the row decoder mechanism, the providing mechanism includes a W bus along which ATM cells travel to the memory array, said W bus connected to the selecting mechanism, the reading or writing mechanism includes a mechanism for delivering ATM cells from an ATM network to the W bus, said delivery mechanism connected with the W bus, the reading or writing mechanism includes a mechanism for transferring ATM cells from the W bus to an ATM network, said transferring mechanism connected with the W bus, the delivery mechanism includes a first mechanism for aligning the ATM cell so it is properly ordered to be written into the memory array when it is delivered to the W bus, said first mechanism in contact with the W bus, the transferring mechanism includes a second mechanism for aligning the ATM cell so it is properly ordered after it is read from the memory array and transferred from the W bus to the ATM network, said second mechanism connected with the W bus, the mechanism for selecting a sub-array includes a memory sub-array row data selector for reading or writing a memory sub-array, the memory sub-array row data selector is comprised of N pass gate switch arrays, each pass gate switch array connected to a corresponding memory sub-array of the N memory sub-arrays, to the W bus and to the row decoder mechanism, said row decoder mechanism activating the pass gate switch array connected to the memory sub-array in which the ATM cell is to be written or read.