Patent ID: 6789232
Filing Date: 2004-09-07
Classification: G06F

Abstract:
A library construction process comprising the steps of:a) constructing logic functions of a technology library corresponding to a basic cell set wherein each logic function of said basic cell set comprises at least a first predetermined number of discrete cells; b) constructing logic functions of said technology library corresponding to an extended cell set wherein each logic function of said extended cell set comprises at least a second predetermined number of discrete cells; c) determining input pin capacitances of discrete cells of a same logic function such that variances of input pin capacitance ratios do not exceed a percentage threshold and repeating step c) for each logic function of said basic and extended cell sets of said technology library; d) for discrete cells of a same logic function, geometrically distributing sizes of each discrete cell and repeating step d) for each logic function of said basic and extended cell sets of said technology library; and e) saving said technology library in a computer memory.