Patent ID: 6433711
Filing Date: 2002-08-13
Classification: H03F,H03K

Abstract:
An analog to digital converter, comprising:a comparator having an offset error, a positive receptor, a negative receptor, a positive output, and a negative output; a sequence generator operable to generate a control signal representing either a normal cycle or a swap cycle; a first cross connect coupled to the positive receptor, the negative receptor, a positive input signal, and a negative input signal, the first cross connect operable to couple the positive input signal to the positive receptor and the negative input signal to the negative receptor in response to a normal cycle control signal from the sequence generator, the first cross connect further operable to couple the positive input signal to the negative receptor and the negative input signal to the positive receptor in response to a swap cycle control signal from the sequence generator; and a second cross connect coupled to the positive receptor, the negative receptor, the positive output, and the negative output, the second cross connect operable to couple the positive receptor to the positive output and the negative receptor to the negative output in response to the normal cycle control signal, the second cross connect further operable to couple the positive receptor to the negative output and the negative receptor to the positive output in response to the swap cycle control signal.