Patent ID: 6604229
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A method of designing wiring for power sources in a semiconductor chip comprising:obtaining information necessary for determining an area of a logic-undecided functional block; determining the area of the logic-undecided functional block based on the obtained information; installing a logic-decided functional block on the semiconductor chip; determining a shape of the logic-undecided functional block, to match a space area of the semiconductor chip on which the logic-decided functional block has been installed; determining a power source terminal position of the logic-undecided functional block; installing the logic-undecided functional block in a space area on the semiconductor chip; providing a provisional wiring of power source between the logic-decided functional block and the logic-undecided functional block; and determining a width of the power source wiring by analyzing a resistor network of the provisionally-provided power source wiring, and rewiring the power source wiring based on the width.