Patent ID: 6259636
Filing Date: 2001-07-10
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array in which memory cells are aligned in a matrix and to which a two-dimensional address space is assigned;a redundant row for relieving a faulty cell existing in the memory cell array;a redundant column for relieving the faulty cell existing in said memory cell array;a row decoding circuit for decoding an external address and selecting a row of said memory cell array;a column decoding circuit for decoding said external address and selecting a column of said memory cell array;a redundant row decoder circuit;a redundant column decoder circuit; anda replacement control circuit for storing a faulty address of one of the row and the column of said memory cell array and an address space information of the stored faulty address to specify whether the faulty address is the row address or column address, and detecting coincidence between said faulty address and said external address to output a replacement control signal indicative of replacing said faulty cell with said one of redundant row and said redundant column on the basis of the address space information, whereinsaid replacement control circuit comprises a first memory unit for storing one of a row address and a column address as said faulty address, and a second memory unit for storing said address space information to identify said faulty address stored in said first memory unit as the row address or the column address; andpart of said first memory unit serves as part of said second memory unit in accordance with difference in bit number between said row address and said column address stored as said faulty address.