Patent ID: 6400608
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A flash memory device, comprising:an array of flash memory cells formed in a p-well in a semiconductor substrate and operatively arranged in rows and columns, wherein the cells in a same row each have a control gate connected to a same corresponding wordline, the cells in a same column each have a drain connected to a same corresponding bitline, and each of the cells has a source connected to a source potential; and control circuitry for verifying operation of the cells, the control circuitry performing the steps of: i) selecting at least one cell from among the cells in a same column by applying a high voltage to the bitline corresponding to the same column and to the wordline or wordlines correspondingly connected to the at least one cell to be selected and by applying a low voltage to the remaining wordlines correspondingly connected to the selected cells in the same column; ii) applying a negative voltage bias selectively to the p-well during the verify operation; iii) comparing a current through the bitline of the selected at least one cell with a current of a reference cell; and iv) verifying whether the selected at least one cell is operating properly based on the comparison.