Patent ID: 7065025
Filing Date: 2006-06-20
Classification: G11B,H03L

Abstract:
1. A phase-locked loop (PLL) circuit comprising: a first loop circuit for generating a first clock signal which is synchronized with a first reference signal, wherein the first reference signal is compared with the first clock signal to generate a first control voltage; and a second loop circuit connected to the first loop circuit for generating a second clock signal which is synchronized with a second reference signal having a frequency which is sufficiently lower than the frequency of the first reference signal, wherein the second reference signal is compared with the second clock signal to generate a second control voltage; wherein the first loop circuit includes a first voltage controlled oscillator for generating the first clock signal in accordance with the first control voltage and a first phase comparator for receiving the first reference signal and a first divisional clock signal, which is generated by dividing the first clock signal, and generating a first comparison signal in accordance with the first reference signal and the first divisional clock signal; wherein the second loop circuit includes a second voltage controlled oscillator for generating the second clock signal in accordance with the first control voltage and the second control voltage; and wherein the first phase comparator includes: a leading edge comparator connected to the first frequency divider for receiving the first reference signal and the first divisional clock signal and generating a leading edge comparison signal in accordance with the difference between the timing of the leading edge of the first reference signal and the timing of the leading edge of the first divisional clock signal; a trailing edge comparator connected to the first frequency divider for receiving the first reference signal and the first divisional clock signal and generating a trailing edge comparison signal in accordance with the difference between the timing of the trailing edge of the first reference signal and the timing of the trailing edge of the first divisional clock signal; and an adder connected to the leading edge comparator and the trailing edge comparator for generating a sum signal by adding the leading edge comparison signal and the trailing edge comparison signal.