Patent ID: 6232043
Filing Date: 2001-05-15
Classification: B24B,H01L

Abstract:
A process for shallow trench isolation, comprising:providing a silicon wafer suitable for forming integrated circuits, having an upper surface and a total area;by means of a first mask and photolithography, etching shallow trenches in said upper surface thereby forming active areas between the trenches;determining the percentage, of said active areas relative to the total area;depositing a layer of a dielectric over said wafer sufficient to overfill the trenches;by means of a second mask and photolithography, selectively etching sub-areas of the dielectric, said sub-areas being wholly within, and of lesser area than, said active areas;determining the percentage, PS, of said sub-areas relative to the total area;determining a thickness, OT, according to a formula:OT={K1.times.PA.times.(100-PS)}+K2,where K1 and K2 are slope and Y intercept, respectively, read off an experimental plot of OT versus PA.times.(100-PS); andby means of a single chemical mechanical polishing step, removing said thickness OT of the dielectric, whereby all dielectric is removed from the active areas and no dishing of dielectric inside the trenches occurs.