Patent ID: 6236596
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A flash EEPROM memory cell comprising:a substrate;a source region in the substrate at which a source voltage is applied during erasure of the flash EEPROM memory cell;a drain region in the substrate;a first oxide layer on the substrate;a floating gate on said first oxide layer, wherein said floating gate is disposed above at least a portion of the source region;a control gate on a second oxide layer, wherein said control gate is disposed above the floating gate, and wherein a control voltage is applied to said control gate during erasure of the flash EEPROM memory cell; anda back biasing connection on the substrate at which a non-zero first biasing voltage is applied during erasure of the flash EEPROM memory cell, wherein the biasing voltage is applied in proportion to the band-to-band current that is present during erasure of the flash EEPROM memory cell and wherein the first biasing voltage is greater than 0 volts and less than or equal to 0.5 volts during erasure of the flash EEPROM memory cell.