Patent ID: 8116417
Filing Date: 2012-02-14
Classification: H04L

Abstract:
1. A data reception apparatus that receives a plurality of data signals respectively transmitted via a plurality of data lines and a clock signal, the data reception apparatus comprising: a plurality of data buffer units that are respectively connected to the data lines and buffer the plurality of data signals; a clock signal buffer unit that buffers the clock signal; and a plurality of deskewing units each deskewing unit being connected to a predefined number of data buffer units of the data buffer units and compensating for jitter and skew included in the plurality of data signals respectively input to the predefined number of data buffer units by adjusting the clock signal by an amount corresponding to the jitter and skew, wherein each deskewing unit samples respective data signals using first and second edge sampling clocks and a data sampling clock to determine in which of first through third areas logic levels of received data signals transition by using results of sampling, detects an upper or lower limit of the area in which sampled data transitions according to the sampling and determines the amount corresponding to the jitter and skew, according to the detected limit, and wherein the data buffer units respectively buffers the plurality of data signals in response to the adjusted clock signal.