Patent ID: 8094670
Filing Date: 2012-01-10
Classification: H04L

Abstract:
1. A network processing apparatus, said apparatus comprising: a network processing pipeline comprising at least one processing subunit and a media access controller interface (MI) subunit for communicating with one or more media access controllers (MAC) to serve as an input point and output point for traversal of packets across an asynchronous boundary between each MAC of the one or more MACs and the network processing pipeline, wherein said MI subunit is configured to send one or two uncommitted frames to each MAC of the at least one MAC before waiting for a commit or reject status; at least one buffer for said at least one processing subunit, wherein said buffer is implemented using both a cache and a system memory; and a front end subunit for managing memory access to said cache and said system memory by said at least one processing subunit of said network processing pipeline.