Patent ID: 6525587
Filing Date: 2003-02-25
Classification: G06F

Abstract:
A semiconductor integrated circuit comprising:clock distribution circuitry receiving a first operation voltage and operating at an operation speed thereof determined by the received first operation voltage for distributing a dock signal, said dock distribution circuit including insulated gate type transistors receiving said first operation voltage at respective first conduction nodes; a plurality of latch circuits for transferring received signals in accordance with clock signals from said dock distribution circuitry; and at least one logical circuit placed corresponding to said plurality of latch circuits, for carrying out a logical process on a signal from a corresponding latch circuit to output a resultant signal, said logical circuit including insulated gate transistors of a same conductivity type as the insulated gate transistors of said clock distribution circuitry receiving a second operation voltage at respective first conduction nodes, the logic circuit having an operation speed determined in accordance with the second operational voltage, and the first and second operation voltages having voltage levels settable individually.