Patent ID: 6219824
Filing Date: 2001-04-17
Classification: G06F

Abstract:
An integrated circuit, comprising:a main functional unit operable to perform a computing function, wherein the main functional unit is further operable to fulfill an input/output (110) request;a memory coupled to the main functional unit, a programmable logic coupled to the main functional unit; anda plurality of I/O pads coupled to the programmable logic;wherein the memory is operable to store one or more of a plurality of configurations for the programmable logic, wherein the main functional unit is further operable to read the one or more of the plurality of configurations stored in the memory, wherein the main functional unit is operable to configure the programmable logic with a desired configuration of the plurality of configurations, wherein the desired configuration operates to configure the programmable logic to fulfill the 110 request, wherein each of the plurality of configurations are operable to control a transmission of data to or from one or more of said plurality of 110 pads; anda direct memory access (DMA) controller coupled to the main functional unit, wherein the DMA controller is further coupled to the memory, and wherein the DMA controller is further coupled to the programmable logic;wherein the main functional unit is further operable to program the DMA controller to fulfill the 110 request independently of the main functional unit.