Patent ID: 8205031
Filing Date: 2012-06-19
Classification: G06F

Abstract:
1. A memory management system, comprising: a memory switching controller for generating a control signal according to at least one request signal; a first memory including a normal access memory bank and at least one switching access memory bank, wherein the plurality of access memory banks are switched according to the control signal, and the normal access memory bank or the switching access memory bank is read out or written in according to the control signal; at least one secondary memory including at least one secondary data bank corresponding to the switching access memory bank; a direct memory access controller for moving the data in the secondary data bank to the switching access memory bank or writing data that are to be written into the secondary data bank via mapping the switching access memory bank according to the control signal; and a processor for issuing the request signal that comprises at least one address data and at least one data that is to be written, wherein the memory switching controller moves the data, corresponding to the address of the request signal, stored in the secondary data bank to the switching access memory bank and outputs the data stored in the switching access memory bank via the direct memory access controller when the address of the request signal is located in the secondary data bank.