Patent ID: 8344495
Filing Date: 2013-01-01
Classification: H01L

Abstract:
1. A method of manufacture of an integrated circuit packaging system comprising: providing a first substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the first substrate external layer; forming an insulation layer over the first substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect, the single interlayer conductive connector through the horizontal conductive pathway and the insulation layer; forming a second substrate external layer over the single interlayer conductive connector, the second substrate external layer having a hole exposing the horizontal conductive pathway; and connecting an integrated circuit and the horizontal conductive pathway with the integrated circuit over the second substrate external layer.