Patent ID: 9196754
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A chip package, comprising: a semiconductor chip, having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and a first opening extending toward the first surface from the second surface to expose the conductive pad, wherein the first opening has a first caliber adjacent to the first surface and a second caliber adjacent to the second surface, and the first caliber is different with the second caliber; an insulating layer disposed on the second surface, and extending to a sidewall and a bottom of the first opening, and exposing the conductive pad; a redistribution layer disposed on the insulating layer and electrically connected to the exposed conductive pad through the first opening; and a passivation layer covering the redistribution layer and partially filling the first opening to form a void between the passivation layer and the conductive pad in the first opening, wherein the passivation layer has at least one second opening exposing the redistribution layer above the second surface.