Patent ID: 6509775
Filing Date: 2003-01-21
Classification: H03K

Abstract:
A synchronous delay circuit apparatus comprising:(a) a plurality of sets of synchronous delay circuits, each set including a first delay circuit chain for delay measurement, along which input clock signals propagate, and a second delay circuit chain, connected to said first delay circuit chain, a difference being measured by said first delay circuit chain, said difference being between the delay time of a preset circuit or path for propagating and outputting clocks and the period of input clocks, said second delay circuit chain reproducing and outputting the measured time difference; (b) wherein at least one of said sets of the synchronous delay circuits, in combination with at least one delay circuit, has a measured delay quantity different from that of the other or others of the synchronous delay circuits, without causing discontinuity in clocks output from said synchronous delay circuits to said preset circuit or path even when the relative relation in the magnitudes between the delay time of the preset circuit or path and the period of said input clock is changed.