Patent ID: 6388335
Filing Date: 2002-05-14
Classification: H01L

Abstract:
An integrated circuit package formed at a wafer level, comprising:a silicon die having an area and having a plurality of bonding pads arranged on a first surface, an adhesive layer covering a substantial portion of the first surface of the die, the plurality of bonding pads remaining exposed, an interposer substrate disposed on the adhesive layer and including a plurality of metallized openings, said metallized openings forming a plurality of metallized vias, the vias being aligned with the plurality of bonding pads of the die, said interposer substrate further including a plurality of metal circuit traces for interconnecting the plurality of metallized vias, said circuit trace being recessed within the substrate, means for electrically connecting the plurality of metallized vias of the interposer substrate and the plurality of bonding pads on the die, and a plurality of I/O interconnects formed on the plurality of metallized openings of the interposer substrate to form a connection to the recessed metal traces.