Patent ID: 9012985
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device comprising: to forming a lower trench part within an epitaxial layer of a substrate; forming a first oxide layer on a surface of the lower trench part; forming a sacrificed buried layer pattern on the first oxide layer within the lower trench part; removing an exposed portion of the first oxide layer to expose a sidewall is of the lower trench part; forming a second oxide layer on the sidewall of the lower trench part and a surface of the sacrificed buried layer pattern; removing the second oxide layer, the sacrificed buried layer pattern and the first oxide layer so as to form an upper trench part on the sidewall of the lower trench part, the upper trench part having a width wider than that of the lower trench part; forming a gate insulating layer on surfaces of the lower trench part, the upper trench part and the substrate; filling the trench by depositing polysilicon on the gate insulating layer within the lower trench part and the upper trench part; forming a body region within the epitaxial layer; forming a gate within the lower trench part by etching the polysilicon; forming a source region through ion injection into a sidewall of the upper trench part; forming an interlayer insulating layer pattern on the gate insulating layer within the upper trench part; forming a contact trench to contact the source region and the body region; forming a highly-doped impurity region on the contact trench, the highly-doped impurity region having the same type of impurity as the body region and to having a higher concentration of impurity than the body region; and filling the contact trench with a metal layer.