Patent ID: 6756655
Filing Date: 2004-06-29
Classification: H01L

Abstract:
A semiconductor configuration, comprising:a semiconductor body having a main surface; an insulator layer disposed on said main surface of said semiconductor body and having an upper surface, said insulator layer having a cavity formed therein extending to said main surface of said semiconductor body; a fuse of predetermined length having a fusible part extending from said main surface of said semiconductor body toward said upper surface of said insulator layer at right angles to said main surface of said semiconductor body, said fusible part having a first end facing said semiconductor body and a second end opposite said first end; said fuse being embedded in said cavity, said cavity surrounding said fuse from said main surface of said semiconductor body toward said upper surface of said insulator layer entirely over said predetermined length of said fuse; a buried layer being disposed in said semiconductor body and contacting said first end of said fusible part; and a metallic contact being disposed at said second end of said fusible part.