Patent ID: 8599188
Filing Date: 2013-12-03
Classification: G09G

Abstract:
1. A data driver comprising: an inverter that inverts each bit of a multiple bit first data signal included in a first group of data signals to generate an inverted multiple bit first data signal; a converter that includes a first converting circuit and a second converting circuit, the first converting circuit converting a multiple bit second data signal included in a second group of the data signals to a first gamma voltage and the second converting circuit being connected to the inverter and re-inverting the inverted multiple bit first data signal to convert the re-inverted multiple bit first data signal to a second gamma voltage; and an output buffer being connected to the first and second converting circuits to store and output the first and second gamma voltage that are output from the converter, wherein the first converting circuit includes a plurality of first gamma voltage selection circuits to select the first gamma voltage in response to the second data signal, and the second converting circuit comprises a plurality of second gamma voltage selection circuits to select the second gamma voltage in response to the first data signal, wherein each of the first gamma voltage selection circuits includes a first voltage selecting part that outputs either a (2i)-th gamma voltage or a (2i-1)-th gamma voltage in response to an LSB (Least Significant Bit) of the second data signal (i is a natural number equal to or greater than 1), wherein the first voltage selecting part includes: wherein each of the second gamma voltage selection circuits includes a second voltage selecting part that outputs either a (2i)-th gamma voltage or a (2i-1)-th gamma voltage in response to an LSB (Least Significant Bit) of the inverted first data signal, the second voltage selecting part being inverted with respect to the first voltage selecting part, wherein the second voltage selecting part comprises: a first N-type transistor configured to have a control terminal receiving the LSB bit of the inverted first data signal, an input terminal receiving the (2i-1)-th gamma voltage from the (2i-1)-th gamma voltage line, and an output terminal connected to the output terminal of the second voltage selecting part.