Patent ID: 8543528
Filing Date: 2013-09-24
Classification: G06N

Abstract:
1. An apparatus, comprising: an address generator operative to receive a current state vector and a current input value, wherein the address generator is operative to generate a memory address corresponding to a transition rule in response to the current state vector and the current input value; a transition rule memory comprising a plurality of memory addresses, wherein the memory address is a location in the transition rule memory; and a rule selector; wherein the transition rule is a transition rule vector comprising a short state tag field; wherein the short state tag field comprises fewer bits than the current state vector; wherein the rule selector is operative to ensure that the short state tag field is not an error by correlating the memory address to the short state tag field since the memory address is derived from the current state vector; and wherein when the rule selector determines that there is no correlation between the memory address and the short state tag field, the rule selector is operative to recognize the error.