Patent ID: 7595824
Filing Date: 2009-09-29
Classification: H03M,H04N

Abstract:
1. A signal processor comprising: a timing generation circuit configured to generate a noise canceling period within a horizontal scanning period for a noise canceling circuit to cancel noise imposed on an analog signal stored in a pixel unit; an analog to digital conversion circuit configured to carry out analog to digital conversion of a signal resulting from noise cancellation; a first line memory configured to store a digital signal resulting from analog to digital conversion; a digital signal processor configured to process the digital signal stored in the first line memory; an output circuit configured to output a signal resulting from signal processing by the digital signal processor; a second line memory configured to store a digital signal for a shorter period than the horizontal scanning period and be disposed before the output circuit; and a control circuit configured to control the second line memory so as to cause the output circuit to output the signal stored in the second line memory during a period other than the noise canceling period in the horizontal scanning period.