Patent ID: 6538912
Filing Date: 2003-03-25
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a first memory array having a plurality of first memory cells provided at points where a first data line group including a first data line, a second data line adjacent to said first data line, a third data line adjacent to said second data line, and a fourth data line adjacent to said third data line intersect a plurality of first word lines; a second memory array having a plurality of second memory cells provided at points where a second data line group including a fifth data line, a sixth data line adjacent to said fifth data line, a seventh data line adjacent to said sixth data line, and an eighth data line adjacent to said seventh data line intersect a plurality of second word lines; and a first sense amplifier block provided between the first memory array and the second memory array and including a first sense amplifier and a second sense amplifier adjacent to each other; wherein the first sense amplifier is connected to the first data line and one data line of the second data line group so as to take an open data line arrangement, the second sense amplifier is connected to the fourth data line and another data line of the second data line group so as to take an open data line arrangement, wherein the first to eighth data line are formed on a first wiring layer and extend to a first direction, wherein the first sense amplifier block further includes first contact pads formed on the first wiring layer, extends to said first direction, and placed between the first and second sense amplifiers.