Patent ID: 6329670
Filing Date: 2001-12-11
Classification: G01R,H01L

Abstract:
A test pad fabricated in a semiconductor, the test pad comprising:a substrate;a metal layer;a first dielectric layer above the metal layer;a plug in the first dielectric layer, the plug in communication with the metal layer;an aluminum layer in communication with the plug wherein the aluminum layer is above the plug;a TiB.sub.x N.sub.y layer in communication with the aluminum layer wherein the TiB.sub.x N.sub.y layer is above the aluminum layer, the TiB.sub.x N.sub.y having an x-factor between about 0.5 and 2 and a y-factor between about 0.2 and 2; anda second dielectric layer above the TiB.sub.x N.sub.y layer wherein the second dielectric layer is etched to expose the TiB.sub.x N.sub.y layer.