Patent ID: 7602656
Filing Date: 2009-10-13
Classification: G11C

Abstract:
1. An I/O bus driving circuit comprising: an I/O bus for providing a data transmission path between a core area and a peripheral area in a semiconductor memory device; a data core connecting stage disposed at an end portion of the core area of the I/O bus; a data peripheral connecting stage disposed at an end portion of the peripheral area of the I/O bus; a bus voltage generator enabled during the data input or output period through the I/O bus to supply a driving voltage to the data core connecting stage and the data peripheral connecting stage; and a power supply controller for controlling a power supply circuit, wherein the power supply controller includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal, wherein the counter is a variable counter capable of adjusting a counting number of the input clock, and wherein the counter includes: a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal.