Patent ID: 6014054
Filing Date: 2000-01-11
Classification: H03F

Abstract:
A load driving circuit comprising:a first high potential power supply node to which a first potential is applied;a first low potential power supply node to which a second potential, lower than the first potential, is applied;a second high potential power supply node to which a third potential, different from the first potential, is applied;a second low potential power supply node to which a fourth potential, lower than the third potential, is applied;a third high potential power supply node to which a fifth potential, different from the first potential, is applied;a third low potential power supply node to which a sixth potential, lower than the fifth potential, is applied;a first input terminal to which a first input signal is applied;a second input terminal to which a second input signal is applied;first and second output terminals to which a load is to be connected;a first differential amplifier circuit including:a first differential amplifier circuit section connected to the first high potential power supply node and the first low potential power supply node, and having a non-inverting input node connected to the second input terminal, an inverting input node connected to the first input terminal, and an output node; anda first output buffer circuit connected to the second high potential power supply node and the second low potential power supply node, and having an input node connected to the output node of the first differential amplifier circuit section and an output node connected to the first output terminal; anda second differential amplifier circuit including:a second differential amplifier circuit section connected to the first high potential power supply node and the first low potential power supply potential node, and having a non-inverting input node connected to the first input terminal, an inverting input node connected to the second input terminal, and an output node; anda second output buffer circuit connected between the third high potential power supply potential node and the third low potential power supply potential node, and having an input node connected to the output node of the second differential amplifier circuit section and an output node connected to the second output terminal.