Patent ID: 6515512
Filing Date: 2003-02-04
Classification: H03K

Abstract:
A logic level re-referencing circuit, comprising:a digital input for receiving a digital input signal having logic levels referenced to a first logic environment; a non-inverting circuit referenced to a second logic environment and having an input, an output, and a non-inverting transfer characteristic between the input and the output; a capacitive element having a first node coupled to the input of the non-inverting circuit and a second node coupled to the digital input; a resistive element coupled between the input of the non-inverting circuit and the output of the non-inverting circuit; and a transient correcting circuit having a first input coupled to the first logic environment, a second input coupled to the second logic environment, and an output coupled to the input of the non-inverting circuit for substantially reducing a transient error between the first and second logic environments, wherein the logic level re-referencing circuit is constructed and arranged to respectively produce high and low logic levels referenced to the second logic environment in response to high and low logic levels referenced to the first logic environment.