Patent ID: 6768689
Filing Date: 2004-07-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of dynamic random access memory cells, each having an access transistor whose drain is connected to a bit line, whose gate is connected to one of a plurality of word lines, and whose source is connected to a capacitive element; a plurality of word line drive circuits that are connected to the plurality of word lines; and a word line voltage generator that is connected to the plurality of word line drive circuits; wherein a first power source that is supplied externally is supplied to a sense amplifier for driving the bit line, the word line voltage generator receives the first power source and a second power source that is supplied externally, generates a voltage that is by a predetermined voltage closer to a voltage of the second power source than the voltage of the first power source, and supplies the generated voltage to the plurality of word line drive circuits as a word line drive voltage.