Patent ID: 9171640
Filing Date: 2015-10-27
Classification: G09G,G11C

Abstract:
1. A shift register comprising: a first flip-flop to which a first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input; a second flip-flop to which a second clock signal which is in the first voltage state in at least part of the second period and in the second voltage state in at least part of the third period, and the fourth period is input; a third flip-flop to which a third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input; a fourth flip-flop to which a fourth clock signal which is in the second voltage state in at least part of the first period, and the second period and in the first voltage state in at least part of the fourth period is input; a first to fourth clock signal lines; a first power supply line to which a high power supply voltage is applied; and a second power supply line to which a low power supply voltage is applied, wherein each of the first to fourth flip-flops comprises: