Patent ID: 9130695
Filing Date: 2015-09-08
Classification: H04L

Abstract:
1. A 10GBASE-T circuit comprising: a physical (PHY) integrated circuit for coupling to a data transfer medium and carrying out data transfers at a PHY data rate; a primary media access control (MAC) integrated circuit to control access to the data transfer medium, the primary MAC coupled to the PHY via a bidirectional link that transfers data streams of data packets separated by inter-packet gap (IPG) frames at a MAC data rate, the primary MAC including an IPG controller to adjust an IPG interval width in response to a control signal, the adjusted IPG interval width varying the MAC data rate by a first data rate component; a secondary MAC circuit disposed between the primary MAC and the PHY, the secondary MAC circuit to generate one or more pause frames to the primary MAC to adjust the MAC data rate by a second data rate component; and rate control logic to detect the PHY data rate, and adjust the MAC data rate to the PHY data rate through a combination of the first and second data rate components, wherein changes to the PHY and MAC data rates are selectively capable at rates higher than 1 Gbps.