Patent ID: 9201992
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A method implemented as a generated-clock checker tool in a programmable computing system for checking timing definitions of generated-clocks against a register-level design for an integrated circuit, the method comprising: constructing waveform models from both user-specified timing definitions and a register-level design for each generated clock, by considering all logic paths from a master clock to each generated-clock, and keeping track of any inversions in a logic path, while ignoring any combinational logic unrelated to clock generation, and generating finite state machines to represent the waveform models; comparing, using formal methods, the two sets of constructed waveform models obtained from the timing definitions and the register-level design, by using a satisfiability checker to compare the finite state machines; and reporting, by using the programmable computing system, any discrepancies found between the two sets of waveforms.