Patent ID: 6825083
Filing Date: 2004-11-30
Classification: H01L

Abstract:
A method of semiconductor structure fabrication comprising:a) providing a semiconductor substrate 430 for the formation of an integrated circuit 400 comprising a plurality of memory devices 380, a plurality of first transistors 390, and a plurality of second transistors 480 (step 210); b) forming a tunnel oxide layer 310, a floating gate layer 320, and a dielectric layer 330 over said semiconductor substrate 430 for forming said plurality of memory devices 380 (step 220); c) masking said plurality of second transistors 480 with a mask 350 to inhibit formation of a thick gate oxide layer 360 for said plurality of first transistors 390, and reduce shallow trench isolation (STI) recess by eliminating removal of said thick gate oxide layer 360 before forming a thin gate oxide layer 410 for said plurality of second transistors 480 (step 230).