Patent ID: 8799617
Filing Date: 2014-08-05
Classification: G06F

Abstract:
1. A memory management unit comprises: a microprocessor controller unit including a program counter having a first address size; register and control logic arranged to support the microprocessor controller unit accessing physical address space via an address bus, the register and control logic comprises a register having a second address size greater than the first address size; and a multiplexer including a first input terminal to receive a value in the register of the register and control logic via an output of the register and control logic, a second input terminal to receive a value in the program counter via the address bus of the microprocessor controller unit, and an output terminal, wherein the microprocessor controller unit is arranged to further access the physical address space via a data bus, wherein the register and control logic is arranged to provide, via the output terminal of the multiplexer, an extended address bus between the microprocessor controller unit and the physical address space, wherein the multiplexer selectively provides, via the output terminal, one of the value in the program counter and the value in the register of the register and control logic, and wherein the memory management unit is characterised in that the register and control logic further comprises one or more of the group consisting of: