Patent ID: 7738477
Filing Date: 2010-06-15
Classification: H04L

Abstract:
1. A bus architecture, comprising: a central processing unit having a bus interface; a data line being a loop having two ends each connected to said central processing unit; a number of bus users each having a bus interface, said central processing unit and said bus users in each case being connected to said data line through said bus interface, said bus users being successively connected to said data line; said central processing unit having two transceiver units, wherein a first one of said transceiver units operates as a transmitter while a second one of said transceiver units operates as a receiver, and after a predetermined period of time, said first one of said transceiver units operates as a receiver while said second one of said transceiver units operates as a transmitter, one of said transceiver units in each case is connected to one of said two ends of said data line via said bus interface, said central processing unit is prepared for a clocked emission of data intended for said bus users; and said bus users each having a monitoring unit connected to an associated said bus interface, said monitoring unit configured for activating a transmit activity of said bus interface only after receiving a synchronization message, otherwise said monitoring unit blocking the transmit activity.