Patent ID: 6697916
Filing Date: 2004-02-24
Classification: G06F,Y02D

Abstract:
A digital system comprising:at least a first processor; a memory cache connected to the first processor, the memory cache operable to respond to transfer requests from the first processor; and direct memory access (DMA) circuitry connected to the memory cache, the DMA circuitry operable to transfer data between the memory cache and a selectable region of a secondary memory; and wherein the memory cache comprises; a data array arranged as a plurality of segments; a plurality of valid bits, wherein each of the plurality of segments has a corresponding valid bit within the plurality of valid bits; miss detection circuitry connected to the plurality of valid bits, the miss detection circuitry having a miss signal for indicating when a miss is detected in response to a request from the first processor; and block circuitry connected to the data array, the block circuitry operable to transfer data from a pre-selected region of the secondary memory to a first segment of the plurality of segments and to assert a first valid bit corresponding to the first segment when the miss detection circuitry detects a miss in the first segment; and wherein the block circuitry is further operable to transfer a block of data to a selected portion of segments of the plurality of segments in such a manner that a transfer to a first segment holding valid data within the selected portion of segments is inhibited.