Patent ID: 7865850
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. A method to develop a substrate noise aware floorplan for an integrated circuit design that includes first blocks that are substrate noise sources and second blocks that are sensitive to substrate noise, the method comprising: generating digital noise models that indicate respective digital noise model locations within one or more first blocks of the integrated circuit design and that indicate corresponding digital noise model values that represent digital switching induced power supply fluctuations associated with such respective digital noise model locations; producing a proposed floorplan for the integrated circuit design that specifies positions of the first and second blocks; producing a substrate noise model for the substrate on which the first and second blocks are to be disposed; defining one or more noise observation ports associated with one or more second blocks; using the floorplan to associate respective digital noise model locations within one or more respective first blocks with respective substrate locations; using the floorplan to associate respective noise observation ports with substrate locations adjacent to corresponding second blocks; performing a first simulation, using a computer, of substrate noise propagation from at least one respective first block to at least one second block that includes, performing a second functional simulation of at least one second block using noise propagated to an observation port associated with such second block as noise input for such functional simulation; and determining based upon the functional simulation whether such second block experiences a substrate noise level that is not within a noise constraint; and if such second block is determined to experiences a substrate noise level that is not within the noise constraint, then changing the floorplan to attempt to bring the substrate noise level experienced by such second block to within the noise constraint.