Patent ID: 6467048
Filing Date: 2002-10-15
Classification: G06F,G11C

Abstract:
A computer system providing automatic fail-over of information stored in memory locations having an undesired number of errors to cache-lines of a cache memory during operation of the computer system, the computer system comprising:a central processing unit; a memory controller connected to the central processing unit; a main memory comprising a plurality of memory locations having information stored therein, wherein the main memory is connected to the memory controller; memory error detection and correction logic for determining and correcting errors in the information stored in the plurality of memory locations during access of the main memory; a first cache memory comprising a plurality of first cache-lines and a plurality of first cache tag registers, each of the first cache tag registers being associated with a respective one of the first cache-lines, each of the first cache tag registers comprising an address portion, a status portion and a fail-over memory portion, wherein information is stored in at least one of the first cache-lines of the first cache memory during access of the main memory; and fail-over logic connected to the memory error detection and correction logic and first cache memory, wherein the fail-over logic sets the fail-over memory portion of the first cache tag register associated with the first cache-line storing information from at least one of the plurality of memory locations that has an undesired number of errors detected by the memory error detection and correction logic, and so long as the fail-over memory portion is set, the respective first cache-line cannot be written over during subsequent accesses of the main memory.