Patent ID: 6281059
Filing Date: 2001-08-28
Classification: H01L

Abstract:
An ESD protective transistor forming method, said method comprising the steps of:providing a semiconductor substrate having a functional region and an ESD protective region, said functional region having a functional transistor with a gate stack from a bottom thereof, a gate oxide, a polysilicon layer, a metal silicide layer, a silicon nitride cap layer and a silicon nitride spacer, said ESD having a ESD protective transistor with a gate stack from a bottom thereof, a gate oxide, a polysilicon layer, a metal silicide layer, and a silicon nitride cap layer thereon, further, a silicon nitride liner layer and a interlevel dielectric layer formed atop said functional transistor, said ESD protective transistor and a remaining portion of said semiconductor substrate;performing a first lithographic and etching process to pattern said interlevel dielectric layer so as to form contact holes for source/drain regions of said functional transistor connections;performing a second lithographic and etching process to pattern said interlevel dielectric layer so as to form contact holes for gate stacks of said functional transistor and of said ESD protective transistor as well as a drain region of said ESD protective transistor connections; andperforming an ion implant using p conductive ions into all areas of said semiconductor substrate so as to form a p-doped region in said drain region of said ESD protective transistor using said metal silicide layers of both transistors as barrier layers to prevent electrical depletion regions formed in both said polysilicon layers of both said transistors.