Patent ID: 6353349
Filing Date: 2002-03-05
Classification: H03K

Abstract:
A pulse delay circuit comprising,a pulse detector including an input for receiving a pulsed signal and an output for generating a leveled signal that transitions between a first voltage and a second voltage whenever the pulsed signal transitions from the first voltage to the second voltage; an RC delay circuit including an input coupled to the output of the pulse detector and an output for generating a delayed leveled signal that transitions between the first voltage and the second voltage whenever the leveled signal transitions between the first voltage and the second voltage, separated by a delay at least partially determined by an RC time constant associated with the RC delay circuit; and a pulsed signal generator including an input coupled to the output of the RC delay circuit and an output for generating a delayed pulsed signal containing a pulse of a predetermined width whenever the delayed leveled signal transitions from the first voltage to the second voltage and whenever the delayed leveled signal transitions from the second voltage to the first voltage.