Patent ID: 6680908
Filing Date: 2004-01-20
Classification: H04L

Abstract:
A network switch comprising a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and means including a look-up table relating address data in said packets to the transmit ports, said switch including, in respect of at least one of said transmit ports:an output buffer for storing data packets before they are forwarded from said port, said output buffer having a front interface which controls the writing of packets into said buffer and a back interface which controls the reading of packets from said buffer; and an allocation controller which includes: means responsive to data in said packets for allocating each packet destined for the said buffer into at least one of a plurality of categories; means responsive to data in said packets for allocating each packet leaving said output buffer into at least one of said plurality of categories; means for determining the size of each packet destined for the output buffer and the size of each packet leaving the output buffer for said port, each of said front and back interfaces including a respective buffer for the temporary storage of packets while they are categorised by said allocation controller; for each of said categories, an allocation register for defining a respective selected proportion of the memory space of said output buffer; for each of said categories, means for accumulating a running total of packet sizes, said total being increased by the size of each packet in the respective category and destined for said output buffer and said total being reduced by the size of each packet in the respective category and leaving said output buffer for the said port; and means for causing discard of a packet when the running total of packet sizes for packets of the same category exceeds the respective proportion of the memory space defined in the respective allocation register.