Patent ID: 6448119
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method of making a field effect transistor (FET), comprising the steps of:forming a layered structure on a semi-insulating substrate, the layered structure having a top layer of InGaAs and a penultimate layer of InAlAs directly beneath and contacting the top layer; forming a recess in the layered structure where a gate is to be formed, the recess extending through the top layer and into the penultimate layer; forming a gate base layer in the recess and directly on a top surface of the top layer beyond a periphery of the recess, the gate base layer directly contacting the top layer and the penultimate layer, the gate base layer comprising a first layer of one of InP, InGaP, AlxGa1âˆ’xAs (0&lE;x&lE;1), InxGa1âˆ’xAs (0&lE;x&lE;1), and InxAl1âˆ’xAs (0&lE;x<0.4, 0.6forming a gate electrode directly on the gate base layer and source and drain electrodes over the top layer spaced from the gate electrode.