Patent ID: 6586765
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A plasma damage test structure comprising:(a) a field oxide over an area of a first conductivity type on a silicon wafer; (b) a first oxide over a first island of a second conductivity type in a first opening in said field oxide; (c) a window of tunnel oxide in said first oxide, wherein said tunnel oxide is thinner than said first oxide; (d) a second oxide over a second island of said second conductivity type in a second opening in said field oxide; (e) a MOSFET having source and drain elements of said second conductivity type in a third opening in said field oxide, and also having a self-aligned polysilicon floating gate formed over a gate oxide in said third opening and wherein a first extension of said polysilicon floating gate passes over a region of said field oxide, terminating in a first pad over said tunnel oxide, entirely covering said window, and wherein a second extension of said polysilicon floating gate passes over another region of said field oxide terminating in a second pad, partially covering said second oxide; (f) a metal antenna structure, formed on a dielectric layer over said wafer and ohmically connected to said first island; (g) a first probe pad on said dielectric layer connected to said second island which forms a control gate; (h) second and third probe pads on said dielectric layer ohmically connected respectively to the source and drain elements of said MOSFET; and (i) an insulative layer over said wafer with a first window exposing said antenna structure.