Patent ID: 8709890
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A method of forming semiconductor structures on a semiconductor-on-insulator (SOI) substrate comprising: forming in a first region an extremely thin semiconductor-on-insulator (ETSOI) transistor on an ETSOI layer superimposed on a buried oxide (BOX) layer, said ETSOI transistor comprising a dummy gate bounded by a spacer and raised source and drain (RSD) abutting at said spacer; replacing said dummy gate by depositing a high-k dielectric followed by depositing a metal gate thereon; and forming in a second region coplanar to said ETSOI transistor, one or more capacitors having a first electrode formed by said doped RSD region of said ETSOI, a second electrode formed by said metal gate, having said high-K dielectric separating said first electrode from said second electrode; forming at least one pn junction diode by selectively recessing said ETSOI and said BOX, filling said junction diode with said metal gate forming one contact to a first terminal, wherein said metal gate contact is electrically isolated from said ETSOI and RSD by said high-K gate dielectric and spacer; forming one or more back gate contact by recessing said SOI and said BOX, and epitaxially growing back to form a planar contact; and forming one or more resistors following said replaced dummy gate, by recessing said ETSOI and said BOX layers and filing said recesses using an epitaxial growth.