Patent ID: 6972819
Filing Date: 2005-12-06
Classification: G02F

Abstract:
1. A method of manufacturing IPS-LCD by using 4-mask process, comprising: providing a substrate having a first area, a second area and a third area; forming a first metal layer on said substrate; patterning said first metal layer using a first mask to form a plurality of first metal lines, a plurality of second metal lines and a plurality of third metal lines, said first, second, and third metal lines being formed on a corresponding said first, second, and third area of said substrate; forming an insulator layer, a silicon based layer and a semiconductive layer sequentially on said substrate and said plurality of first, second and third metal lines; forming a photoresist layer on said semiconductive layer using a second mask, said photoresist layer having a plurality of openings over segments of said third metal lines, said photoresist layer having a thicker portion on said second metal lines, the proximate areas of said second metal lines, the segments of said third metal lines and a partial area of said semiconductive layer on said third area, and said photoresist layer having a thinner portion on other portions of said semiconductive layer; partially removing said semiconductor layer, said silicon based layer and said insulator layer using said photoresist layer as a mask, said third metal lines under said openings being partially exposed by a plurality of first contact holes inside said semiconductive layer, said silicon based layer and said insulator layer; ashing said photoresist layer, wherein said thinner portion of said photoresist layer is removed and the thickness of said thicker portion of said photoresist layer is reduced; partially removing said semiconductive layer and said silicon based layer using the remaining said photoresist layer as a mask, wherein a portion of said insulation layer is exposed; removing the remaining photoresist layer; forming a second metal layer on an exposed portion of said insulator layer and the remaining semiconductive layer, wherein said first contact holes are filled by said second metal layer; patterning said second metal layer using a third mask, a plurality of second contact holes being formed in said second metal layer and on each of said second and third metal lines, said first and second contact holes not overlapping; removing partial of said semiconductive layer that is exposed from said second contact holes; and forming a passivation layer on the remaining second metal layer, the exposed portion of said insulator layer and the exposed portion of said silicon based layer, wherein the thickness of the thinner portion of said photoresist layer is about thirty percent of the thickness of the thicker portion of said photoresist layer.