Patent ID: 6392920
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A method of driving a nonvolatile memory in which ferroelectric transistors each of which is formed by laminating a gate electrode via at least a first ferroelectric layer on the surface of a semiconductor substrate between a source area and a drain area formed on the semiconductor substrate are arrayed in a matrix; the gate electrode is connected to a word line, the source area is connected to a source line and the drain area is connected to a drain line; the semiconductor substrate is separated every column so that voltage is independently applied and is connected to a back gate line; and the potential of the source line and the potential of the drain line can be respectively set to floating potential or ground potential very line and column, wherein:for a selected cell, one of the source and the drain is grounded; and for an unselected cell at least on an adjacent line of the selected cell, in writing data to the selected cell, a depletion layer spreads in the channel area of a ferroelectric transistor in the unselected cell by making source/drain potential floating and keeping it a desired value and drain current is prevented from flowing.