Patent ID: 6025272
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device to decrease the incidence of failure of critical areas in the semiconductor device, the method comprising:forming at least one isolation structure to define at least one active area in a substrate;forming active elements in the at least one active area in the substrate;forming a layer of a spin-on layer of a dielectric material over exposed surfaces of the at least one active element, the at least one isolation structure and the substrate, wherein the spin-on layer of dielectric material fills any crevices;selectively removing portions of the spin-on layer of a dielectric material;forming an etch stop layer on exposed surfaces of the spin-on layer of a dielectric material, the at least one active element, and the at least one isolation structure;forming a layer of dielectric material over the etch stop layer; andselectively etching portions of the layer of dielectric material down to the etch stop layer.