Patent ID: 6338998
Filing Date: 2002-01-15
Classification: H01L

Abstract:
A method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication comprising:providing a semiconductor substrate; forming upon a first portion of the semiconductor substrate a first gate dielectric layer in turn having formed thereupon a first gate electrode, the first portion of the semiconductor substrate being separated from a second portion of the semiconductor substrate having formed thereupon a second gate dielectric layer in turn having formed thereupon upon a second gate electrode; forming within the first portion of the semiconductor substrate, and separated by the first gate electrode, a pair of first source/drain regions, where the pair of first source/drain regions comprises a pair of comparatively lightly doped regions formed closer to the first gate electrode; and a pair of comparatively heavily doped regions formed further spaced from the first gate electrode and overlapped by the pair of comparatively lightly doped regions; forming within the second portion of the semiconductor substrate and separated by the second gate electrode a pair of second source/drain regions; and forming contacting one of the pair of second source/drain regions a storage capacitor, wherein: the first gate electrode is formed prior to forming contacting the one of the second source/drain regions the storage capacitor, and both the pair of comparatively lightly doped regions and the pair of comparatively heavily doped regions within the pair of first source/drain regions are formed after forming contacting the one of the pair of second source/drain regions the storage capacitor.