Patent ID: 6818462
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method for determining an active region width for fabricating a memory device, said method comprising steps of:forming a plurality of composite capacitor structures, each of said plurality of composite capacitor structures comprising: a substrate having at least two shallow trench isolation structures formed therein and at least one active region situated between said at least two shallow trench isolation structures, said at least one active region having a predetermined width and said active region width; an insulating layer formed on said substrate; a semiconductor layer formed on said insulating layer; measuring a respective capacitance values of said each of said plurality of composite capacitor structures; plotting said respective capacitance value as a function of said respective predetermined width for said each of said plurality of composite capacitor structures, said respective capacitance value being plotted on a first axis and said respective predetermined width being plotted on a second axis, said function comprising a quasi-linear expression: extrapolating said quasi-linear expression to determine an extrapolated width; wherein said respective active region width for said each of said plurality of composite capacitor structures is determined by a difference between said respective predetermined width and said extrapolated width.