Patent ID: 6633177
Filing Date: 2003-10-14
Classification: G01R,H01L

Abstract:
A method of predicting the lifetime of a semiconductor integrated circuit, characterized by comprising:a first step of deriving, as a unit leakage current level, the amount of a B-mode stress induced leakage current flowing through each of SBD spots where a soft breakdown has occurred in multiple MOS devices included in the circuit; a second step of obtaining a critical spot number from the unit leakage current level, the critical spot number being a minimum number of SBD spots required for a total amount of B-mode stress induced leakage currents, flowing through the respective MOS devices, to exceed a predetermined reference level; and a third step of estimating, as an expected lifetime of the circuit, a time it takes for the number of SBD spots in the MOS devices to reach the critical spot number.