Patent ID: 6903979
Filing Date: 2005-06-07
Classification: G11C

Abstract:
1. A method of programming a PMOS stacked-gate memory cell, wherein the memory cell includes a p-type source region in n-type semiconductor substrate, a p-type drain region formed in the n-type semiconductor substrate material and space-apart from the p-type source region to define a substrate channel region therebetween, a conductive floating gate electrode formed over the substrate channel region and separated therefrom by gate dielectric material, and a conductive control gate electrode formed over the floating gate electrode and separated therefrom by integrate dielectric material, the programming method comprising: applying a negative voltage potential to the p-type drain region; applying a voltage potential to the control gate electrode such that electrons are attached to the floating gate electrode from the p-type drain region through the gate dielectric material; establishing a correlation between floating gate injection current and semiconductor substrate material current; monitoring the value of the semiconductor substrate material current; and utilizing the monitored value of the semiconductor substrate material current to provide a feedback correction signal to the voltage potential applied to the control gate electrode such that the semiconductor substrate material current is maximized during programming of the memory cell.