Patent ID: 6815997
Filing Date: 2004-11-09
Classification: G06G

Abstract:
A field effect transistor square multiplier for squaring an input signal, the field effect transistor square multiplier comprising:an input stage for providing a sum of the input signal and a reference signal and a difference of the reference signal and the input signal; a first field effect transistor device formed on a substrate and having a gate, a source, a drain and a channel, the gate of the first field effect transistor device connected to receive the sum of the input signal and of the reference signal; a second field effect transistor device formed on the substrate and having a gate, a source, a drain and a channel, the gate of the second field effect transistor device connected to receive the difference of the reference signal and of the input signal, the first and second field effect transistor devices having a first aspect ratio of channel width to channel length, a first gate insulation layer capacitance per unit area and a first charge carrier mobility; a third field effect transistor device formed on the substrate and having a gate, a source, a drain and a channel, the gate of the third field effect transistor device connected to receive the reference signal, the third field effect transistor device having a second aspect ratio of channel width to channel length, a second gate insulation layer capacitance per unit area and a second charge carrier mobility; and a constant current source connected to the source of the first, second and third field effect transistor devices respectively; wherein the drain of the first field effect transistor device is connected to the drain of the second field effect transistor device, and a parameter value defined as the product of aspect ratio, gate insulation layer capacitance and charge carrier mobility of the third field effect transistor device is two times the corresponding parameter value of the first and second field effect transistor devices, the field effect transistor square multiplier adapted to provide a current I1 at a common node connected to the drain of the first and second field effect transistor and a current I2 at the drain of the third field effect transistor, wherein a difference of I1 and I2 is proportional to the square of the input signal.