Patent ID: 6664811
Filing Date: 2003-12-16
Classification: H03K,H04L

Abstract:
A differential driver for transmitting signals, comprising:a main buffer arranged to drive a first input differential signal for output as a differential output signal over a differential output line; a set of secondary buffers arranged to receive second input differential signals, tristate signals, and mode signals, each secondary buffer receiving one second input differential signal, one tristate signal, and one mode signal, the secondary buffers being configured to operate in a normal slew rate or a slow slew rate, each tristate signal being configured to drive the associated secondary buffer to high impedance to turn off the associated secondary buffer when the tristate signal is asserted, wherein each secondary buffer is configured to operate in a slow slew rate in response to the associated mode signal; and control logic circuitry arranged to receive input signals and a clock signal for generating the first input differential signal, second input differential signals, tristate signals, and the mode signals such that the secondary buffers cutback the differential output signal on the differential output line when the input signals are in a steady state for more than a specified number of clock cycles, and wherein the secondary buffers are arranged to cutback the differential output signal by tristating in response to the tristate signals and by operating in the slow slew rate in response to the mode signals.