Patent ID: 8954819
Filing Date: 2015-02-10
Classification: G06F,G11B,H03M

Abstract:
1. A circuit, comprising: a decoder configured to receive first codewords and decode the first codewords based on a first error correcting code, and to receive second codewords and decode the second codewords based on a second error correcting code; an error checking module configured to error-check first sectors using a first error detecting code in the first sectors, each first sector being formed of a plurality of decoded first codewords, and to error-check second sectors using a second error detecting code in the second sectors, each second sector being formed of a plurality of decoded second codewords; and a controller configured to store in a memory, when the error checking fails for at least one first sector, the decoded first codewords and corresponding flags indicative of pass or fail of the decoding of the first codewords and to store in the memory, when the error checking of the second sectors fails for at least one second sector, the decoded second codewords based on the stored flags in the memory to combine the decoded first codewords with the decoded second codewords.