Patent ID: 6977861
Filing Date: 2005-12-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: memory cell transistors each having a floating gate electrode and a control gate electrode (WL), wherein the control gate electrode (WL) of the memory cell transistor takes a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential according to an operating state at the selection thereof, and wherein a first NMOS transistor of which the source is connected to a control (/ER) for controlling a second NMOS transistor which drives the control gate electrode (WL) to the first power supply potential (VCC), the drain is connected to the gate of the second NMOS transistor, and the gate is connected to the first power supply potential (VCC), is provided between the second NMOS transistor and the control signal (/ER), a PMOS transistor is provided in parallel with the second NMOS transistor, and the control gate electrode (WL) is driven by a transfer gate comprising the NMOS transistor and the PMOS transistor.