Patent ID: 7529273
Filing Date: 2009-05-05
Classification: G06F

Abstract:
1. A memory hub comprising: downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off hub transmission port and further operable to generate an enable signal in response to receiving the enable command from the respective off-hub transmission port; and downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub.