Patent ID: 7486543
Filing Date: 2009-02-03
Classification: G11C,H01L,Y10S

Abstract:
1. An asymmetrical SRAM device, comprising: a semiconductor substrate on which a plurality of unit cell regions are defined; a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate; a first pass transistor region extending into each of four adjacent unit cell regions in a first set of unit cell regions; and a second NMOS transistor region extending each of four adjacent unit cell regions in a second set of unit cell regions, wherein: the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions, the active regions of each unit cell region include: the second NMOS transistor has more threshold voltage control ions for high threshold voltage than the first NMOS transistor, the first pass transistor has more threshold voltage control ions for high threshold voltage than the second pass transistor, the first PMOS transistor has more threshold voltage control ions for high threshold voltage than the second PMOS transistor, the first pass transistor region includes a first common region that is common to each of the four adjacent unit cell regions in the first set, the first common region having a first level of voltage control ions, the second NMOS transistor region includes a second common region that is common to each of the four adjacent unit cell regions in the second set, the second common region having a second level of voltage control ions, a first pass transistor from each of the four adjacent unit cell regions of the first set is disposed in the first pass transistor region, and a second NMOS transistor from each of the four adjacent cell regions of the second set is disposed in the second NMOS transistor region.