Patent ID: 6930536
Filing Date: 2005-08-16
Classification: G11C,H02M

Abstract:
1. A voltage booster for receiving a first voltage at an input and providing a boosted voltage at an output, the voltage booster comprising: a first capacitor having a first terminal for receiving a first clock signal and having a second terminal; a second capacitor having a first terminal for receiving a second clock signal and having a second terminal, wherein the second clock signal is complementary to the first clock signal; a first n-channel field-effect transistor (nFET) having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second terminal of the first capacitor and the first source/drain region is coupled to receive the first voltage; a second nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the second source/drain region of the first nFET and the second terminal of the second capacitor, the first source/drain region is coupled to the first source/drain region of the first nFET, and the second source/drain region is coupled to the gate of the first nFET; a third nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to the gate of the first nFET and the second source/drain region of the second nFET, the first source/drain region is coupled to the gates of the first and third nFETs and the second source/drain region of the second nFET, and the second source/drain region is coupled to the output of the voltage booster; a fourth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive a supply voltage, the first source/drain region is coupled to the second terminal of the second capacitor and the second source/drain region is coupled to receive a control signal; and a fifth nFET having a gate, a first source/drain region and a second source/drain region, wherein the gate is coupled to receive the supply voltage, the first source/drain region is coupled to the gate of the third nFET and the second source/drain region is coupled to receive the control signal.