Patent ID: 6465734
Filing Date: 2002-10-15
Classification: H01L,Y10T

Abstract:
A resin-sealed semiconductor device, comprising:a semiconductor element having a top surface and a bottom surface with terminals formed on said bottom surface; and plural circuit portions having top surfaces and bottom surfaces with said top surfaces facing said bottom surface of said semiconductor element, wherein said plural circuit portions include, integrally formed inner terminals and outer terminals arranged two-dimensionally along a plane and electrically independent of one another, said terminals of said semiconductor element are arranged linearly along a center portion of said bottom surface thereof so as to correspond with respective of said linear terminals, said bottom surfaces of said inner terminals of said circuit portions are electrically connected to said terminals of said semiconductor element with wires, said device is completely sealed with a resin in such a manner that said bottom surfaces of said outer terminals are partially exposed, said bottom surfaces of said outer terminals are arranged linearly along said center portion of said semiconductor element so as to form plural lines of four or more, said circuit portions have leads for integrally interconnecting said inner terminals and said outer terminals, said inner terminals and said leads are thinner than said outer terminals, and said semiconductor element is mounted on said top surfaces of said circuit portions with an insulating layer disposed therebetween, wherein said bottom surfaces of said outer terminals are located at a bottom surface except for edge portions of said device configured as a chip size package (CSP).