Patent ID: 9092305
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A circuit for communicating with a memory, comprising: a sorting circuit configured and arranged to: receive a plurality of read transactions and a plurality of write transactions; sort the write transactions according to respective sizes of data to be written by the write transactions to the memory over a first serial data link; and sort the read transactions according to respective sizes of data to be read by the read transactions from the memory over a second serial data link; a selection circuit coupled to the sorting circuit and configured and arranged to select from the sorted read and write transactions, read and write transactions for transmission to the memory in an order that balances a quantity of data to be written to the memory over the first serial data link with a quantity of data to be read from the memory over the second serial data link; and a transmitter coupled to the selection circuit and configured and arranged to transmit the selected ones of the plurality of read and write transactions to the memory device on the first serial data link.