Patent ID: 6211015
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of forming a memory array, comprising:forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;forming a plurality of first source/drain regions, of a second conductivity type, each of the first source/drain regions formed proximally to an interface between the pillar and the substrate;forming a plurality of second source/drain regions, of a second conductivity type, each of the second source/drain regions formed within one of the pillars and distal to the substrate and separate from the first source/drain region;forming a plurality of third source/drain regions, of the second conductivity type, each of the third source/drain regions formed at least partially within one of the pillars and distal to the substrate and between the first and the second source/drain regions;forming a gate dielectric on at least a portion of the side surface of the pillars;forming at least one pair of vertically stacked floating gates per pillar, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;forming a plurality of control gate lines, each of the control gate lines formed substantially adjacent to at least one of the floating gates and insulated therefrom;forming an intergate dielectric, interposed between ones of the floating gates and ones of the control gate lines;forming at least one first source/drain interconnection line interconnecting ones of the first source/drain regions;forming at least one second source/drain interconnection line interconnecting one of the second source/drain regions; andforming a plurality of data lines, each data line interconnecting ones of the third source/drain regions.