Patent ID: 9158542
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A data processing device comprising an external memory that stores an instruction and data necessary for execution of the instruction and a plurality of processor units, each of the plurality of processor units comprising: cache memory that temporarily stores the instruction and the data; an instruction execution unit that reads the instruction and the data from the external memory via the cache memory and executes the instruction; an initiation detecting unit that detects an entering of a thread implemented by processing of the instruction execution unit into an exclusive control section, which is specified in advance to become a bottleneck; and a termination detecting unit that detects an exiting of the thread out of the exclusive control section, and wherein each of the plurality of processor units leaves, in the cache memory, data used in the exclusive control section when determining a replacement target of cache entries due to a fact that the memory access of the instruction execution unit results in a cache miss.