Patent ID: 8368221
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A method, comprising: forming a first dielectric layer at least laterally adjacent to a circuit element, said circuit element having a sidewall and at least partially extending being partially formed above a semiconductor region having a first contact region defined by a top surface of said semiconductor region, wherein forming said first dielectric layer comprises depositing a first dielectric material, depositing a second dielectric material on said first dielectric material above said first dielectric material, said second dielectric material at least laterally enclosing a portion of said sidewall of said circuit element, and performing a planarization process using said first dielectric material for controlling said planarization process to form a planarized surface; forming a first contact element in said first dielectric layer to connect to said first contact region, wherein forming said first contact element comprises patterning said first dielectric material by means of an etch mask formed on said planarized surface so as to create a contact opening to expose said first contact region and filling said contact opening with a metal containing material, wherein said first contact element has a first height above said first contact region corresponding to a second height of said circuit element above said active region plus a thickness of said first-sub-layer disposed above said circuit element; forming a second dielectric layer above said first dielectric layer, said second dielectric layer comprising a low-k dielectric material; patterning said second dielectric layer to contain a via opening connecting to said first contact element and a trench connecting to said via opening; and filling said via opening and said trench in a common deposition process sequence to define a metal line in said trench and a via in said via opening connecting to said first contact element.