Patent ID: 6225827
Filing Date: 2001-05-01
Classification: H03K

Abstract:
A self-timed pipelined datapath system comprising:a pipelined datapath circuit including a plurality of data processing stages, each having;a combinational circuit for processing input data; said combinational circuit having a dynamic logic circuit comprising a plurality of sequentially coupled unit dynamic logic circuits, anda register connected to the input side of said combinational circuit; andan asynchronous signal control circuit that controls each of the registers in said pipelined datapath circuit in response to a request signal;wherein each of said plurality of unit dynamic logic circuits further comprises:a logic circuit portion composed of one or more than one low-threshold MOS transistors;a first MOS transistor for a precharging or a pre-discharging operation with respect to said logic circuit to perform; anda second high-threshold MOS transistor to enable said logic circuit a discharging or a charging operation;and wherein said asynchronous signal control circuit comprises signal generating means for controlling precharging and discharging operations and/or pre-discharging and charging operations of said combinational circuit in response to said request signal.