Patent ID: 6201410
Filing Date: 2001-03-13
Classification: H03K

Abstract:
A structure for implementing a wide logic function in an FPGA configurable logic element (CLE), comprising:a first function generator having at least n input signals and an output terminal, the first function generator being configured as an n-input logic function;a second function generator having at least m input signals and an output terminal, the second function generator being configured as an m-input logic function, the m input signals being independent from the n input signals; anda multiplexer having a first input terminal coupled to the output terminal of the first function generator, a second input terminal coupled to the output terminal of the second function generator, and a select terminal coupled to the output terminal of at least one of the first and second function generators, wherein:the multiplexer passes a signal at the first input terminal when a select signal provided at the select terminal is low, andthe multiplexer passes a signal at the second input terminal when the select signal is high.