Patent ID: 6156605
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method for fabricating a DRAM device with a triple well structure, comprising:providing a semiconductor substrate of a first conductive type, the substrate having first and second well regions of a first conductivity type and a third well region of a second conductivity type, said first and second well regions being electrically isolated from each other by said third well region;forming spaced apart source/drain regions on both said first and second well regions in order that a distance between source/drain regions of one well region is less than a distance between source/drain regions of the other well region by a predefined amount; andforming a gate electrode on each of said first and second well regions between said corresponding spaced apart source/drain regions,whereby a threshold voltage is controlled by setting the distance between said source/drain regions in said first well region predefinedly differently from the corresponding distance in said second well region.