Patent ID: 6088770
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A multiprocessor having a plurality of nodes and a network for connecting the nodes, each of the nodes including at least one CPU, at least a cache and a memory, each of the nodes accessing the memories of all the nodes, at least one of the nodes comprising:a first register, in correspondence with each page of the memory of one of the nodes, for storing a first bit showing if the corresponding page has been accessed from any other node, the first bit is set when the corresponding page of the memory has been accessed from the other of the nodes; anda circuit for, when the CPU of the one node accesses the memory of the particular node, checking the first bit of the first register that corresponds to the page to be accessed by the CPU of the one node, for sending a message managing the caches to the other nodes from the one node in a case where said first bit is set, and for inhibiting the sending of the message in a case where said first bit is not set.