Patent ID: 6221759
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method for forming aligned vias under adjacent trenches to prevent voiding in a dual damascene process, the method comprising:forming a pair of adjacent first metal layer portions over a semiconductor substrate;forming an oxide layer over the adjacent first metal layer portions and the semiconductor substrate;forming an etch stop layer over the oxide layer;forming a set of adjacent trenches over the pair of adjacent first metal layer portions in the oxide layer through portions of the etch stop layer with one trench per first metal layer portion;forming a resist layer at least partially over the etch stop layer, the resist layer defining a via pattern having an enlarged via opening adapted to expose the pair of adjacent trenches; andetching a pair of aligned vias through the enlarged via opening in the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose the adjacent first metal layer portions so as to form a via under each of the adjacent trenches, the etch stop layer inhibiting the oxide layer underneath from being etched substantially, each of the vias formed under the each of the adjacent trenches being substantially of a same width as and in alignment with the associated trench above.