Patent ID: 6064740
Filing Date: 2000-05-16
Classification: G06F

Abstract:
An integrated circuit containing circuitry for performing modulo exponentiation, said integrated circuit comprising:a modulo exponentiation calculation circuit;a mode data, said mode data indicating whether said modulo exponentiation calculation circuit should operate in at least a one of a standard mode and a normalized mode;when said mode signal indicates that said modulo exponentiation calculation circuit should operate in said standard mode, said modulo exponentiation calculation circuit performs the steps of:a first step of determining whether a first bit of an exponent is a one or a zero, if said first bit is a zero then said first step is repeated with the next bit until a first one is found;a second step of performing a modulo square calculation with said first one;a third step of performing a modulo multiply calculation;a fourth step of determining whether the next bit of the exponent is a one or a zero, if the next bit is a one then a modulo square calculation is performed and then a modulo multiply calculation is performed, if the next bit is a zero than a modulo square calculation is performed;a fifth step of repeating the fourth step with each remaining bit in the exponent;when said mode signal indicates that said modulo exponentiation calculation circuit should operate in said normalized mode, said modulo exponent calculation circuit performs the steps of:(a) calculating a modulo square calculation on a first bit of said exponent;(b) calculating a modulo multiply calculation on said first bit of said exponent;(c) repeating steps (a) and (b) for each remaining bit in said exponent.