Patent ID: 7683495
Filing Date: 2010-03-23
Classification: H01L,H05K

Abstract:
1. A flip chip integrated circuit package, comprising: a substrate having opposing first and second surfaces; a solder mask layer that covers at least a portion of the first surface of the substrate, the first surface of the substrate having a first electrically conductive feature, a second electrically conductive feature, and a mounting region for a flip chip oriented integrated circuit die on the first surface of the substrate, the integrated circuit die having a plurality of solder bumps; an opening in the solder mask layer overlapping the first electrically conductive feature and the second electrically conductive feature; and an electrically conductive material; wherein the first electrically conductive feature is a portion of a first electrical signal net of the substrate, and the second electrically conductive feature is a portion of a second electrical signal net of the substrate; wherein the first electrically conductive feature is proximate to the second electrically conductive feature, and the first and second electrically conductive features are configured to be selectively electrically coupled together by application of the electrically conductive material; and wherein the electrically conductive material is on the first surface at the opening and electrically couples the first electrically conductive feature and the second electrically conductive feature, wherein a solder bump of the plurality of solder bumps is the electrically conductive material.