Patent ID: 8519874
Filing Date: 2013-08-27
Classification: H03M

Abstract:
1. A successive approximation A/D converter, comprising: a main DAC including a capacitive element group of which one electrode is coupled to a top node and is weighted with a power of 2, and a switch group by which the other electrode of the capacitive element group is coupled to an analog input terminal upon sampling, or is coupled to either a first reference voltage or a second reference voltage upon A/D conversion; a comparator which compares voltage of the top node of the main DAC with comparison reference voltage; a correction DAC which generates correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced among the capacitive element group of the main DAC, and supplies the correction voltage to the top node of the main DAC; and a control circuit which generates internal digital input for controlling the switch group of the main DAC and a correction code for controlling the correction voltage of the correction DAC, and outputs a successive approximation result by the comparator from a significant bit to an insignificant bit when the A/D conversion is performed, wherein the control circuit measures a first capacitance error and a second capacitance error of the capacitive element pair to be balanced by performing, twice complementarily, a switching control on the internal digital input corresponding to the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement based on the switching control is removed from the first capacitance error and the second capacitance error, by subtracting the first capacitance error from the second capacitance error.