Patent ID: 6649944
Filing Date: 2003-11-18
Classification: H01L

Abstract:
An I/O electrostatic discharge (ESD) protection circuit for protecting a silicon-on-insulator integrated circuit formed over an insulating layer, said ESD protection circuit comprising:an electrically conductive pad fabricated over said insulating layer; a conductor segment fabricated over said insulating layer, said conductor segment connecting said pad directly to a first node; a first voltage supply rail fabricated over said insulating layer; a second voltage supply rail fabricated over said insulating layer; a first primary diode fabricated over said insulating layer and connected between said first node and said first voltage supply rail; a second primary diode fabricated over said insulating layer and connected between said first node and said second voltage supply rail; a first plurality of diodes fabricated over said insulating layer and connected between said first node and said first voltage supply rail, said diodes being opposite to said first primary diode's direction; and a second plurality of diodes fabricated over said insulating layer and connected between said first node and said second voltage supply rail, said diodes being opposite to said second primary diode's direction.