Patent ID: 7840918
Filing Date: 2010-11-23
Classification: G06F

Abstract:
1. A method for implementing a circuit design for an integrated circuit, comprising: providing a physically implemented circuit design meeting at least one timing constraint; identifying a design block of the physically implemented circuit design having a high toggle rate pattern; selecting a particular power optimized transformation type of a plurality of power optimized transformation types; applying the particular power optimized transformation type to the design block of the physically implemented circuit design having the high toggle rate pattern; implementing a modified physically implemented circuit design after application of the particular power optimized transformation type, wherein the modified physically implemented circuit design is power optimized; determining whether or not the modified physically implemented circuit design meets the at least one timing constraint; measuring actual power consumption of the modified physically implemented circuit design; comparing the actual power consumption of the modified physically implemented circuit design to power consumption of the physically implemented circuit design; in response to the modified physically implemented circuit design not meeting the at least one timing constraint, selecting another of the plurality of power optimized transformation types as the particular power optimized transformation type, and repeating the steps of applying, implementing, determining and selecting another; and in response to the modified physically implemented circuit design meeting the at least one timing constraint and the actual power consumption of the modified physically implemented circuit design being less than the power consumption of the physically implemented circuit design, storing the modified physically implemented circuit design in a processor-readable storage device, wherein the plurality of power optimized transformation types includes at least a first transformation type that rearranges a signal having high switching activity and a second transformation type that rearranges circuits of the design block.