Patent ID: 6265281
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method used during the formation of a semiconductor device comprising the following steps:providing a semiconductor substrate assembly having a recess therein defined by first and second semiconductor sidewalls, said recess comprising a width;only partially filling said recess with a first dielectric layer which contacts said semiconductor sidewalls;subsequent to partially filling said recess with said first dielectric layer, annealing said first dielectric layer;subsequent to annealing said first dielectric layer, providing a second dielectric layer within said recess which contacts said first dielectric layer; andannealing said second dielectric layer, wherein a thickness of said first dielectric layer prior to annealing said first dielectric layer added to a thickness of said second dielectric layer prior to annealing said second dielectric layer is less than half said width of said recess, and wherein, subsequent to annealing said second dielectric layer, said annealed first and second dielectric layers fill said recess.