Patent ID: 6144601
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A semiconductor memory comprising at least a first memory cell and a second memory cell associated to a first bit line and a second bit line, respectively, which constitute a pair of bit lines precharged to a reference potential before data is read out, a sense amplifier connected to said first and second bit lines and selectively activated for comparing, when one memory cell of said first and second memory cells is selected and electrically connected to the bit line associated with the selected memory cell, a potential on said bit line connected to said selected memory cell with a potential on the bit line associated with a non-selected memory cell of said first and second memory cells, so as to output the result of comparison as a read-out data, and a reference potential setting means connected to said first and second bit lines, for selectively setting said bit line associated with said non-selected memory cell to said reference potential before said sense amplifier is activated.