Patent ID: 6242295
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A method of forming a plurality of shallow junction transistors, the method comprising the steps of:providing a substrate having a first well region and a second well region separated by an isolation area, the first well region having a first region and a first channel region, the second well region having a second region and a second channel region;forming a primary insulation layer outward of the substrate;forming a first and second gate outward of the primary insulation layer proximate the first and second channel region, respectively;removing portions of the primary insulation layer to expose the substrate proximate the first and second region, the primary insulation layer disposed between the substrate and the first and second gates remaining intact;forming a contiguous dopant layer covering the exposed portion of the substrate;introducing a first dopant into the dopant layer proximate the first region;introducing a second dopant into the dopant layer proximate the second region; andsimultaneously diffusing a portion of the first dopant in the dopant layer into the substrate proximate the first region to form a first shallow doped region anda portion of the second dopant in the dopant layer into the substrate proximate the second region of the substrate to form a second shallow doped region wherein the first shallow doped region forms, at least in part, a source and a drain for a first shallow junction transistor and the second shallow doped region forms, at least in part, a source and a drain for a second shallow junction transistor.