Patent ID: 8687409
Filing Date: 2014-04-01
Classification: G11C

Abstract:
1. A variable resistance nonvolatile memory device including: a plurality of first signal lines; a plurality of second signal lines crossing the first signal lines; and a memory cell array including a plurality of memory cells provided at cross-points of the first signal lines and the second signal lines, each of the memory cells including a variable resistance element and a current steering element which is connected to the variable resistance element in series and has two terminals, the variable resistance element having a resistance state which changes to (i) a low resistance state when a first voltage of a predetermined first polarity is applied to the variable resistance element, and (ii) a high resistance state when a second voltage of a second polarity opposite to the first polarity is applied to the variable resistance element, the low resistance state being a state in which the variable resistance element has a resistance value in a first range, and the high resistance state being a state in which the variable resistance element has a resistance value in a second range higher than the first range, the variable resistance nonvolatile memory device comprising: a write circuit which performs (i) low resistance writing by which the resistance state of the variable resistance element changes to the low resistance state, by applying, to each of the memory cells, a low resistance writing voltage via a corresponding one of the first signal lines and a corresponding one of the second signal lines, and (ii) high resistance writing by which the resistance state of the variable resistance element changes to the high resistance state, by applying, to each of the memory cells, a high resistance writing voltage via the corresponding one of the first signal lines and the corresponding one of the second signal lines, the low resistance writing voltage being a voltage of the first polarity and greater than or equal to the first voltage in absolute value, and the high resistance writing voltage being a voltage of the second polarity and greater than or equal to the second voltage in absolute value; a first selection circuit which selects one or more of the first signal lines; and a second selection circuit which selects one or more of the second signal lines, wherein the memory cells are grouped into a plurality of blocks, each of the blocks includes a plurality of memory cells, and the write circuit further performs the following: performs initial breakdown on one or more of the variable resistance elements in an initial state after the variable resistance nonvolatile memory device is manufactured, by applying an initial breakdown voltage to the one or more of the variable resistance elements via a corresponding one or more of the first signal lines and a corresponding one or more of the second signal lines, the initial breakdown being a process by which the initial state of the one or more of the variable resistance elements changes to a state in which resistance of the one or more of the variable resistance elements variable through the low resistance writing and the high resistance writing, and the initial breakdown voltage being greater than the low resistance writing voltage and the high resistance writing voltage in absolute value; applies, in the initial breakdown, the initial breakdown voltage to the one or more of the first signal lines selected by the first selection circuit and the one or more of the second signal lines selected by the second selection circuit, via the first selection circuit and the second selection circuit; and sequentially selects blocks from among the blocks in an order starting from a block farthest from at least one of the first selection circuit and the second selection circuit and finishing with a block closest to the at least one of the first selection circuit and the second selection circuit, and performs, for each of the selected blocks, the initial breakdown on each of memory cells included in the selected block.