Patent ID: 8710886
Filing Date: 2014-04-29
Classification: H03K

Abstract:
1. A semiconductor memory device, comprising: a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to a first correction signal and a second correction signal; and a clock edge detector configured to receive the first and second output clocks to generate the first and second correction signals activated in a period of an interval between a reference transition timing of the first output clock and the reference transition timing of the second output clock, wherein the clock edge detector includes: a first pulse generating unit configured to generate a first reference pulse in response to a first transition of the first output clock; a second pulse generating unit configured to generate a second reference pulse in response to the first transition of the second output clock; a first correction signal generating unit configured to generate the first correction signal having the first transition in response to the first reference pulse and a second transition in response to the second reference pulse; and a second correction signal generating unit configured to generate the second correction signal having the first transition in response to the second reference pulse and the second transition in response to the first reference pulse, wherein the duty cycle corrector includes: a duty cycle ratio detecting unit configured to generate a first correction value corresponding to a logic level of the first correction signal and a second correction value corresponding to a logic level of the second correction signal; and a duty cycle ratio correcting unit configured to correct a duty cycle ratio of the first output clock according to the first correction value, and a duty cycle ratio of the second output clock according to the second correction value, wherein the duty cycle ratio detecting unit includes: a first charge storing unit configured to accumulate electric charges corresponding to the first correction value; a second charge storing unit configured to accumulate electric charges corresponding to the second correction value; a first switching unit configured to discharge the electric charges accumulated in the first charge storing unit according to the second logic level of the first correction signal; a second switching unit configured to charge the electric charges to the first charge storing unit according to the first logic level of the first correction signal; a third switching unit configured to discharge the electric charges accumulated in the second charge storing unit according to the second logic level of the second correction signal; and a fourth switching unit configured to charge the electric charges to the second charge storing unit according to the first logic level of the second correction signal.