Patent ID: 7800236
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A method for forming a layout of a semiconductor die comprising: disposing a first integrated circuit design in a first region of the semiconductor die layout; disposing a second integrated circuit design in a second region of the semiconductor die layout, the second integrated circuit design identical to the first integrated circuit design and rotated approximately ninety degrees relative to the first integrated circuit design; disposing a third integrated circuit design in a third region of the semiconductor die layout, the third integrated circuit design identical to the first integrated circuit design and rotated approximately one hundred and eighty degrees relative to the first integrated circuit design; disposing a fourth integrated circuit design in a fourth region of the semiconductor die layout, the fourth integrated circuit design identical to the first integrated circuit design and rotated approximately two hundred and seventy degrees relative to the first integrated circuit design; and wherein the integrated circuit design layout includes an overlying power and ground mesh layer that includes a first set of v-shaped power and ground strips, a second set of v-shaped power and ground strips, a third set of v-shaped power and ground strips and a fourth set of v-shaped power and ground strips, each of the v-shaped power and ground strips in the first set of v-shaped power and ground strips, the second set of v-shaped power and ground strips, the third set of v-shaped power and ground strips and the fourth set of v-shaped power and ground strips including a central connection region, a first angled portion on one end and a second angled portion on the other end, wherein each first angled portion and second angled portion that extends over the first integrated circuit device is oriented at an angle of approximately forty five degrees relative to the layout of the first integrated circuit device, and each first angled portion and second angled portion that extends over the second integrated circuit device is oriented approximately perpendicular to each first angled portion and second angled portion that extends over the first integrated circuit device.