Patent ID: 6279073
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A configurable synchronizer for DDR-SDRAM, comprising:a strobe select module operable to receive a memory select signal and to pass strobe signals from one or more DDR-SDRAMs;one or more synchronizer circuits corresponding to data signals passed in parallel by each DDR-SDRAM as indicated by the memory select signal;wherein each synchronizer circuit includes:a rising edge latch operable to receive a rising edge data signal from the DDR-SDRAM and to latch the rising edge data signal through the rising edge latch on a rising edge of the strobe signal;a falling edge latch operable to receive a falling edge data signal from the DDR-SDRAM and to latch the falling edge data signal through the falling edge latch on a falling edge of the strobe signal;a data signal selector operable to receive a data order control signal and to forward the rising edge data signal from the rising edge latch to an intermediate output on either a rising edge of a memory clock cycle or a falling edge of a memory clock cycle followed by forwarding the falling edge data signal from the falling edge latch to the intermediate output on an opposite edge of the memory clock cycle in response to the data order control signal;an output latch operable to receive the intermediate output and to latch the intermediate output through the output latch to an output signal on each core clock cycle.