Patent ID: 7818747
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A method of performing computer system operations, comprising: concurrently executing a first thread and a second thread, wherein the second thread comprises a known shared cache miss rate; measuring a combined shared cache miss rate of the first thread and the second thread; calculating a shared cache miss rate of the first thread based on the combined shared cache miss rate and the known shared cache miss rate; identifying, in a chip multithreading processor, a plurality of hardware contexts comprising a plurality of maximum shared cache miss rates, wherein the plurality of hardware contexts is located on a single processing core; identifying a minimum shared cache miss rate from the plurality of maximum shared cache miss rates, wherein each of the plurality of maximum shared cache miss rates exceeds the shared cache miss rate of the first thread; selecting a hardware context of the plurality of hardware contexts corresponding to the minimum shared cache miss rate; and assigning the first thread to the hardware context.