Patent ID: 6177695
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A DRAM with an oxide plug in bitline contact, in which each memory cell comprises:a transistor, formed on a silicon wafer substrate;a bitline contact, having a bottom connecting the silicon wafer substrate to connect a source region of the transistor, and an inner part connecting a bitline; anda capacitor, comprising:a lower-plate, which is made with Ti or TiN, standing above the transistor and further comprising a selective hemi-sphere grain of lightly doped polysilicon;a high dielectric constant substance, which is deposited on the lower-plate; andan upper-plate, isolated from the lower-plate by the high dielectric constant substance, having a planar surface and an opening broader than the bitline contact at a top portion of the lower-plate neighboring the bitline contact, wherein the upper-plate is isolated from the bitline contact.