Patent ID: 6236241
Filing Date: 2001-05-22
Classification: G11C

Abstract:
A redundant decoder having fuse-controlled transistor comprising:a bistable circuit which outputs a pair of complementary signals;a discharging device which is turned on at an evaluating cycle to form a discharging path;a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage;a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive a pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals;a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; anda fuse device, having a fuse which is coupled to the bistable device that decides the logic values of the pair of complementary signals by whether the fuse is burnt down or not.