Patent ID: 7911854
Filing Date: 2011-03-22
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory layers arranged in multilayer, each memory layer including a cell array, said cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing said first lines, and a plurality of memory cells connected at intersections of said first lines and said second lines; a pulse generator operative to generate pulses required for data access to an access target memory cell in said plurality of memory cells; and a control means operative to control said pulse generator such that the pulse output from said pulse generator has energy in accordance with the memory layer to which said access target memory cell belongs, wherein said memory layer further comprising a current limiter operative to limit current flowing in said access target memory cell on access to said access target memory cell, and said current limiter sets a limit value of current in accordance with an address of said access target memory cell.