Patent ID: 6157238
Filing Date: 2000-12-05
Classification: G06F,H03K

Abstract:
A clock system of a semiconductor memory device comprising:an external clock source located outside the semiconductor memory device for generating an external clock signal;a controller synchronized to the external clock signal, said controller containing a master frequency amplifier and a master DLL circuit; anda multiplicity of DRAMs synchronized to the external clock signal, each of said multiplicity of DRAMs containing a frequency amplifier and a DLL circuit;wherein each of said frequency amplifiers amplify the external clock signal to thereby produce an inner clock signal whose frequency is two multiples of that of the external clock signal, each frequency amplifier including,a delay circuit coupled to said external clock source for producing a phase-delayed clock signal based on the external clock signal;a logic device coupled to said delay circuit for generating the inner clock signal based on the external clock signal and the phase-delayed clock signal;a buffer coupled to said logic device for buffering the inner clock signal and providing a buffered clock signal.