Patent ID: 9063870
Filing Date: 2015-06-23
Classification: G06F

Abstract:
1. For use in a programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, a method of performing a signed 3n-by-3n multiplication operation, said method comprising: performing a 2n-by-2n multiplication using four of said n-by-n multipliers in a first of said four-multiplier units; performing an n-by-n multiplication using one of said n-by-n multipliers in a second of said four-multiplier units; and performing first and second 2n-by-n multiplications in a third of said four-multiplier units, using two of said n-by-n multipliers for each of said 2n-by-n multiplications; wherein: in each of said multiplications, multiplicands representing n most significant bits are treated as signed operands and multiplicands representing n least significant bits are forced to be unsigned; said method further comprising: shifting a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and adding results of said multiplications from said first, second and third four-multiplier units.