Patent ID: 6308236
Filing Date: 2001-10-23
Classification: G06F

Abstract:
An interface device between a CPU bus and a local bus, the CPU bus having CPU address lines and data lines, comprising:a dynamic decoding means, coupled to the CPU address lines, for generating a HIT signal when an address value of a present CPU cycle falls within a predetermined range of a previous address value of a previous CPU cycle accessing a local-bus device;a local bus interface means, coupled to the local bus, for triggering a local bus cycle and generating an acknowledge signal when the address value of the present CPU cycle does not fall within the predetermined range of the previous address value of the previous CPU cycle, and, in response to the HIT signal, for generating a first plurality of control signals to the local bus;a First-In-First-Out data buffer, coupled to the CPU data lines and the local bus, for transmitting data within the data buffer to the local bus under the control of a second plurality of control signals;an acknowledgement generator, responsive to the HIT signal, for generating a READY signal;wherein the dynamic decoding means has a register with an output, responsive to the acknowledge signal, for storing the address value when the address value of the present CPU cycle does not fall within the predetermined range of the previous address value of the previous CPU cycle accessing the local-bus device.