Patent ID: 9158883
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A method of making a semiconductor device comprising: generating layout style information based on a layout design of the semiconductor device, the layout style information comprising information regarding whether an active edge cell of the semiconductor device and a non-edge cell of the semiconductor device adjacent to the active edge cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers is distributed in the active edge cell and the non-edge cell; generating array edge information based on the layout design and a schematic design of the semiconductor device; performing smart dummy insertion to selectively revise the layout design based on the layout style information and the array edge information; performing a design rule check on the revised layout design based on the layout style information and the array edge information, comprising determining whether a pattern density gradient at the active edge cell of the semiconductor device exceeds a threshold value; and repeating the revising the layout design step if the pattern density gradient at the active edge cell exceeds the threshold value, wherein at least one of the above operations is performed by a computer.