Patent ID: 6700446
Filing Date: 2004-03-02
Classification: H03L,Y10S

Abstract:
A phase-locked loop frequency synthesizer comprising;a reference signal generator for generating a reference signal with a reference frequency; a voltage controlled oscillator for generating an output signal having an output frequency in response to a control voltage signal received thereby; a first variable frequency divider connected to said reference signal generator for frequency dividing the reference signal on the basis of a first divisor so as to generate a divided reference signal; a second variable frequency divider connected to said voltage controlled oscillator for frequency dividing the output signal on the basis of a second divisor so as to generate a divided output signal; a first controllable synchronous frequency divider connected to said first variable frequency divider for frequency dividing the divided reference signal on the basis of a third divisor upon receiving a frequency dividing control signal so as to generate a first low frequency signal; a second controllable synchronous frequency divider connected to said second variable frequency divider for frequency dividing the divided output signal on the basis of the third divisor upon receiving the frequency dividing control signal so as to generate a second low frequency signal; a phase-frequency comparator connected to said first and second controllable synchronous frequency dividers for receiving the first and second low frequency signals therefrom, said phase-frequency comparator comparing the first and second low frequency signals and outputting an adjust signal according to a detected difference therebetween; a control voltage generating circuit connected to said voltage controlled oscillator and said phase-frequency comparator, said control voltage generating circuit supplying the control voltage signal to said voltage controlled oscillator in response to the adjust signal; a phase-locked detector connected to said phase-frequency comparator for outputting a phase-locked signal in response to the adjust signal; and a switching control logic connected to said phase-locked detector, said control voltage generating circuit, said first variable frequency divider, and said first and second controllable synchronous frequency dividers, said switching control logic being operable so as to supply the frequency dividing control signal to said first and second controllable synchronous frequency dividers with reference to the divided reference signal from said first variable frequency divider upon receiving the phase-locked signal from said phase-locked detector.