Patent ID: 6020235
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A method of constructing a storage capacitor for a DRAM cell having:a word line connected to the gate electrode of a MOSFET,a bit line connected to a first diffusion of said MOSFET, a first electrode of said capacitor connected to a reference potential,a second electrode of said capacitor connected to a second diffusion of said MOSFET, separated from said first electrode by a dielectric layer and having a cross-section in the form of at least one shell enclosing a core, which traverses diagonally from one memory cell to another memory cell, comprising the steps of:defining the MOSFET area and isolation area outside said MOSFET area,patterning said gate electrode,depositing and patterning a first oxide to isolate the gate from the second electrode of said capacitor,depositing a first polysilicon to form the lower portion of said shell,depositing and patterning a second oxide to form said core,depositing and patterning a second polysilicon to form the upper portion of said shell,depositing a third oxide to form the dielectric of said capacitor,depositing and patterning a third polysilicon to form the first electrode of said capacitor,depositing an interlayer dielectric,opening a contact window in said interlayer dielectric over said first diffusion for said bit line, anddepositing and patterning a conducting said bit line.