Patent ID: 6531358
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A method for fabricating a DRAM with capacitor under bit line (CUB) cell in an integrated circuit device comprising:providing a plurality of capacitor node contact junctions and a bit line junction in a semiconductor substrate; forming a node contact plug through a first insulating layer to each of said capacitor node contact junctions and forming a bit line contact plug to said bit line junction; depositing a second insulating layer overlying said node contact plugs and etching openings through said second insulating layer to each of said node contact plugs; conformally depositing a first conducting layer overlying said second insulating layer and within said openings; removing said first conducting layer except where said first conducting layer lies within said openings; coating a photoresist layer overlying said first conducting layer; exposing said photoresist layer and partially developing away said photoresist layer wherein said photoresist layer remains only within said openings and wherein a top surface of said photoresist layer lies 1000 to 2000 Angstroms below a top surface of said openings; thereafter etching away said first conducting layer where it is not covered by said photoresist layer whereby said first conducting layer is recessed by 1000 to 2000 Angstroms from said top surface of said openings wherein each of said first conducting layers forms a bottom plate electrode of said capacitor; thereafter removing said photoresist layer; thereafter forming a capacitor dielectric layer overlying said bottom plate electrodes and said second insulating layer; depositing a second conducting layer overlying said capacitor dialectic layer and patterning said second conducting layer and said capacitor dielectric layer to form top capacitor plates overlying each of said bottom plate electrodes to complete said capacitors; depositing a third insulating layer overlying said capacitors and etching an opening through said third and second insulating layers between said capacitors to said bit line contact plug; and filling said opening with a third conducting layer to form a bit line to complete fabrication of said DRAM with CUB cell in said integrated circuit device.