Patent ID: 6037617
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:(a) a semiconductor layer formed on an insulating substrate;said semiconductor layer having first area extending along a first direction and a second area extending along said first direction;said first and second areas being adjacent to one another;(b) a first IGFET of a first conductivity type formed in said first area of said semiconductor layer;said first IGFET having a first pair of source/drain regions;(c) a second IGFET of a second conductivity type opposite to said first conductivity type formed in said first area of said semiconductor layer;said second IGFET having a second pair of source/drain regions;one of said second pair of source/drain regions being electrically connected to one of said first pair of source/drain regions by a first interconnection diffusion region; and(d) a third IGFET of said first conductivity type formed in said second area of said semiconductor layer;said third IGFET having a third pair of source/drain regions;one of said third pair of source/drain regions being electrically connected to one of said second pair of source/drain regions by a second interconnection diffusion region.