Patent ID: 8217457
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit structure comprising; a substrate; a first well extending into the substrate from a first surface of the substrate; a shallow trench isolation region surrounding the first well and extending from the first surface of the substrate to a region in the substrate that has a resistivity that is that of a native substrate; a second well extending into the substrate from the first surface of the substrate and surrounding the shallow trench isolation region; a transistor in the first well, said transistor comprising a plurality of gate fingers and a plurality of source and drain regions wherein the gate fingers extend parallel to one another on the first surface of the substrate and the source and drain regions are in the first well between the gate fingers; and a tap for the first well that is located in the second well at the first surface of the substrate.