Patent ID: 9105606
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region, wherein the gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to the at least one gate conductor, wherein an upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer; and a multi-layered cap on the upper surface of the gate conductor, wherein the multi-layered cap includes a high-k dielectric material, wherein the multi-layered cap also includes a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer, wherein the high-k dielectric material includes a lower portion, a first lateral sidewall, and a second lateral sidewall, wherein the lower portion of the high-k dielectric material is located on an upper surface of the gate conductor, and wherein the first and second lateral sidewalls of the high-k dielectric material are spaced apart and extend vertically upward from the lower portion of the high-k dielectric material along the gate sidewall spacer in a direction away from the semiconductor substrate, wherein a first surface of the dielectric cap spacer is located in direct physical contact with the second lateral sidewall of the high-k dielectric material, and wherein a sidewall of the dielectric cap spacer located opposite to the first surface of the dielectric cap spacer has a convex curvature relative to the second lateral sidewall of the high-k dielectric material.