Patent ID: 8975642
Filing Date: 2015-03-10
Classification: H01L,Y10S

Abstract:
1. A method of forming a transistor device comprising: providing a semiconductor substrate; forming a confining layer on the semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer; after forming the confining layer on the semiconductor substrate, forming a well region by performing an ion implantation in both the confining layer and the semiconductor substrate; forming an epitaxial silicon layer on the ion implanted confining layer; forming a gate structure on the epitaxial silicon layer, wherein a portion of the epitaxial silicon layer forms an intrinsic channel region; forming a germanium-silicon carbide (GeSiC) implantation region in the epitaxial silicon layer by implanting germanium ions and carbon ions in the epitaxial silicon layer on both sides of the gate structure; and forming a source region and a drain region each including a portion of each of the GeSiC implantation region of the epitaxial silicon layer, the ion implanted confining layer, and the well region in the semiconductor substrate.