Patent ID: 6049231
Filing Date: 2000-04-11
Classification: H03K

Abstract:
A dynamic multiplexer circuit, comprising:an integer number N of data providing circuits, wherein the integer number N is greater than one and wherein each of the plurality of data providing circuits comprises:a precharge node to be precharged to a precharge voltage during a precharge phase;a conditional series discharge path connected to the precharge node and operable in response to at least one enabling input signal to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node;an inverter coupled to the precharge node and having an output for providing a second monotonic transitioning data signal, wherein the second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal;the integer number N of data select paths, wherein each of the data select paths comprises a select transistor, the select transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal;an output precharge node, wherein a drain of the select transistor in each of the data select paths is coupled to conditionally discharge the output precharge node;an output inverter having an input connected to the output precharge node; andwherein in a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the select transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.