Patent ID: 6775189
Filing Date: 2004-08-10
Classification: G11C

Abstract:
An option fuse circuit manufactured with standard CMOS manufacturing processes, comprising:a latch comprising a first node and a second node, and being used for latching signals at the first and the second nodes; a comparator comprising two input nodes and an output node, wherein the two input nodes are electrically connected to the first and the second nodes respectively, the comparator being used for inputting the signals at the first and the second nodes respectively, and outputting a comparison signal by comparing the two signals; a first logic cell for storing a non-volatile data, comprising a first word line node and a first bit line node, wherein the first word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the first bit line node being electrically connected to the first node; and a second logic cell for storing a non-volatile data, comprising a second word line node and a second bit line node, wherein the second word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the second bit line node being electrically connected to the second node; wherein the data stored in the first logic cell and the data stored in the second logic cell are complementary to each other.