Patent ID: 8951868
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A method of forming of a semiconductor device having functional gate structures with different critical dimensions, said method comprising: forming providing a plurality of sacrificial gate structures on a surface of a substrate, wherein a first set of said plurality of sacrificial gate structures contains a sacrificial spacer located on a sidewall surfaces of each sacrificial gate structure, and a second set of said plurality of sacrificial gate structures contains sacrificial gate structures having bare sidewall surfaces; providing a dielectric spacer to said first and second sets of said plurality of sacrificial gate structures, wherein each dielectric spacer provided to said first set of said plurality of sacrificial gate structures contacts a sidewall surface of said sacrificial spacer and each dielectric spacer provided to said second set of said plurality of sacrificial gate structures contacts said bare sidewall surfaces of the sacrificial gate structures; removing each sacrificial gate structure of said first set of said plurality of sacrificial gate structures and said sacrificial spacers to provide first cavities having a first width, and each sacrificial gate structure of said second set of said plurality of sacrificial gate structures to provide second cavities having a second width, wherein said second width is lesser than the first width; and forming a functional gate structure in each of said first and second gate cavities.