Patent ID: 7870473
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device comprising: a regenerator configured to generate a regenerated address on the basis of the output address from the 1-out-of-n decoder, the regenerated address equaling the input address if the conversion of the input address to the associated output address occurs without any faults, and the regenerated address not equaling the input address if the conversion of the input address generates an output address, out of the plurality of valid output addresses, which does not equal the associated output address; and a comparer configured to receive the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.