Patent ID: 6285208
Filing Date: 2001-09-04
Classification: H03K

Abstract:
A semiconductor integrated circuit comprising:a plurality of signal wiring lines;a plurality of shield wiring lines, each of which is arranged between adjacent two of said plurality of signal wiring lines;an interference preventing section connected to said plurality of shield wiring lines, for supplying to two of said plurality of shield wiring lines adjacent to a specific one of said plurality of signal wiring lines, an interference preventing signal which is switched to have a same phase as an input signal which is supplied to said specific signal wiring line, wherein said interference preventing section includes a plurality of interference preventing circuits, each of said plurality of interference preventing circuits including a gate circuit having two input terminals that receive input from two of said plurality of siganl wiring lines adjacent to said shield wiring line corresponding to said each interference preventing circuit and provides output to said shield wiring line, wherein said gate circuit includes at least one of: a NAND gate, a NOR gate, and an exclusive OR gate.