Patent ID: 8866802
Filing Date: 2014-10-21
Classification: G09G

Abstract:
1. A pixel circuit comprising: a display element part including a unit liquid crystal display element; an internal node constituting a part of the display element part, and holding a pixel data voltage applied to the display element part; a first switch circuit including a series circuit of a first transistor element and a second transistor element, having one end connected to a data signal line and another end connected to the internal node, and transferring the pixel data voltage supplied from the data signal line to the internal node through the series circuit; a second switch circuit including a third transistor element, and having one end connected to a predetermined voltage supply line and another end connected to a middle node serving as a connection point between the first and second transistor elements connected in series in the series circuit; and a control circuit including a series circuit of a fourth transistor element and a first capacitive element, holding the pixel data voltage held in the internal node at one end of the first capacitive element through the fourth transistor element, and controlling an on/off state of the third transistor element in the second switch circuit by a boost voltage applied to the other end of the first capacitive element, wherein each of the first to fourth transistor elements comprises a first terminal, a second terminal, and a control terminal controlling a connection between the first and second terminals, the control terminals of the first and second transistor elements are connected to a scanning signal line to turn on the first and second transistor elements at a time of an action to transfer the pixel data voltage to the internal node, the control terminal of the third transistor element, the second terminal of the fourth transistor element, and the one end of the first capacitive element are mutually connected to constitute an output node of the control circuit, the first terminal of the fourth transistor element is connected to the internal node, the control terminal of the fourth transistor element is connected to a first control line, and the other end of the first capacitive element is connected to a second control line for supplying the boost voltage.