Patent ID: 6969872
Filing Date: 2005-11-29
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a storage line formed over a substrate; a gate wire formed over the substrate and extending parallel to the storage line, the gate wire comprising a first gate line including a first gate electrode and a second gate line including a second gate electrode; a data wire formed over and extending perpendicular to the gate wire, the data wire comprising: a first data line including a first source electrode and a first drain electrode disposed opposite the first source electrode with respect to the first gate electrode; a second data line including a second source electrode and a second drain electrode disposed opposite the second source electrode with respect to the second gate electrode; and a data connector that connects the first data line to the second data line; a first pixel electrode connected to the first drain electrode; and a second pixel electrode connected to the second drain electrode.