Patent ID: 8643093
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first conductivity type semiconductor substrate; a first conductivity type epitaxial layer provided on the first conductivity type semiconductor substrate with a second conductivity type embedded layer interposed between the first conductivity type semiconductor substrate and the first conductivity type epitaxial layer; a first conductivity type well diffusion layer formed in a part of the first conductivity type epitaxial layer on the second conductivity type embedded layer; trenches formed to a depth that reaches from the first conductivity type well diffusion layer to the second conductivity type embedded layer, and connected to one another in one of a lattice pattern and a stripe pattern; a gate insulating film formed on each surface of the trenches; a gate electrode filling each of the trenches which is covered with the gate insulating film; a first second-conductivity type heavily doped source diffusion layer and a first conductivity type substrate-potential diffusion layer which are formed above surfaces of island-like regions, the island-like regions being other regions of the first conductivity type well diffusion layer than the trenches; contact holes aligned on the gate electrode along one side of the gate electrode; and a second second-conductivity type heavily doped source diffusion layer provided in a stepped portion, the stepped portion being provided on a surface of the first conductivity type well diffusion layer that is in contact with the one side of the gate electrode along the one side of the gate electrode, and having a face lower than a surrounding plane and having slopes as well.