Patent ID: 7450418
Filing Date: 2008-11-11
Classification: G11C,H01L

Abstract:
1. A non-volatile memory, comprising: a substrate; a plurality of memory cells, disposed over the substrate, each memory cell including: an access transistor; a memory transistor, having a charge storage structure and a gate, and the source of the memory transistor being connected to the drain of the access transistor; a first transistor, disposed on the side of the access transistor, opposite to the side connected with the memory transistor; and a second transistor, disposed on the side of the memory transistor, opposite to the side connected with the access transistor; a plurality of word lines, connected to the gates of the access transistors in the same column respectively; a plurality of bit lines, connected to the drains of the second transistors in the same column respectively; a plurality of source lines, connected to the sources of the first transistors in the same column respectively; and a plurality of gate lines, connected to the gates of the memory transistors in the same column respectively.