Patent ID: 6753227
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method of fabricating a MOS transistor comprising:forming a field oxide at a predetermined area of a semiconductor substrate that defines an active region; implanting well impurity ions into a semiconductor substrate having the active region; implanting channel impurity ions into a surface of the active region; diffusing the well impurity ions and the channel impurity ions using a rapid thermal anneal and forming a well area doped with the well impurity ions and a channel area doped with the channel impurity ions; forming a conductive layer on the semiconductor substrate having the well region and the channel region; forming a gate pattern crossing over the active region by patterning the conductive layer; curing etching damages of the semiconductor substrate generated during patterning of the conductive layer by applying a thermal process to the semiconductor substrate including the gate pattern; implanting source/drain impurity ions into the active region using the gate pattern as an implantation mask; and forming source/drain regions by diffusing the source/drain impurity ions.