Patent ID: 7179661
Filing Date: 2007-02-20
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor die, comprising: forming a first test structure on the semiconductor die, wherein at least a portion of the first test structure includes a dummy structure in a top conductive layer, wherein the dummy structure of the first test structure serves as both a dummy structure and a part of a voltage contrast structure, wherein serving as a dummy structure is defined as the dummy structure of the first test structure being part of a plurality of dummy structures that are distributed within empty spaces of the semiconductor die to facilitate an even polishing of a surface of the semiconductor die, and wherein only a portion of the dummy structures each serve as a voltage contrast structure while the other portion of dummy structures do not each serve as a voltage contrast structure; and performing voltage contrast testing on the first test structure that serves as both a dummy structure and a voltage contrast structure to detect electrical defects within the first test structure.