Patent ID: 6630700
Filing Date: 2003-10-07
Classification: H01L

Abstract:
An integrated NMOS circuit, comprising:an active stack having a plurality of isolated p-well active devices, each isolated p-well active device having a gate and a bulk; a bias stack having a plurality of diode-connected isolated p-well bias devices, each of the plurality of diode-connected isolated p-well bias devices having a gate, a source, and a bulk, the gate of each of the plurality of diode-connected isolated p-well bias devices coupled to the gate of a corresponding one of the plurality of isolated p-well active devices, the bulk of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding one of the plurality of isolated p-well active devices, the source of each of the plurality of diode-connected isolated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.