Patent ID: 6130383
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A solder ball array package combination comprising:a circuit carrying insulating substrate having opposing planar first and second sides and corners;a first metallization pattern, attached to the first side of the circuit carrying insulating substrate, that includes a plurality of bond pads, a plurality of via pads, and a plurality of electrical connections between the plurality of bond pads and the plurality of via pads;a second metallization pattern, attached to the second side of the substrate;a plurality of electrically conductive vias that penetrate through the substrate for making electrical connections between the plurality of via pads and the metallization pattern on the second side of the substrate;a semiconductor device mounted on the first side of the substrate;a protective plastic cover formed from an encapsulation material and moulded about the semiconductor device and a substantial portion of the first side of the substrate, wherein the protective plastic cover includes an outer periphery and is formed to reveal a second portion of the first side of the substrate about the perimeter of the protective plastic cover; anda substantially straight mould gate region overlying said second portion of the first side of the substrate at a corner through which encapsulation material had been received to form the protective plastic cover, wherein said mould gate region further comprises a straight interface and a mould gate tape attached by adhesive over at least a part of the first metallization pattern, said mould gate tape including an end that is spaced within the outer periphery of the protective plastic cover such that the end is covered by the protective plastic cover and extends straight without curvature portions from the end and along the circuit carrying substrate and such that it forms a weak area at the mould gate region that had enhanced the clean breaking of the encapsulation material.