Patent ID: 8625153
Filing Date: 2014-01-07
Classification: B41J

Abstract:
1. A multi-dimensional data registration integrated circuit for driving array-arrangement devices, the multi-dimensional data registration integrated circuit comprising a plurality of first hierarchy sets, each first hierarchy set comprising a plurality of second hierarchy sets, each second hierarchy set comprising a plurality of array-arrangement devices, the multi-dimensional data registration integrated circuit further comprising: a first hierarchy address selection circuit comprising a first serial-in parallel-out circuit having a plurality of parallel outputs for correspondingly selecting the plurality of first hierarchy sets; a second hierarchy address selection circuit comprising a plurality of second serial-in parallel-out circuits for correspondingly selecting the second hierarchy sets, each second serial-in parallel-out circuit connecting to a corresponding one of the plurality of parallel outputs of the first serial-in parallel-out circuit; and a data supply circuit writing a plurality of data into a designated second hierarchy set according to the scanning sequence of the second hierarchy address selection circuit.