Patent ID: 6706602
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A manufacturing method of a flash memory, comprising:providing a substrate, on which a gate structure is formed; forming a source region in the substrate at one side of the gate; forming a first spacer on the sidewall of the gate structure; forming a first conductive layer on the substrate; forming a sacrificial layer on the first conductive layer; removing portions of the sacrificial layer and the first conductive layer by a chemical mechanical polishing (CMP) method until the gate structure is exposed; performing thermal oxidation to form a mask layer on the first conductive layer and the gate structure; removing the sacrificial layer remaining on the first conductive layer; using the mask layer as a mask to etch the first conductive layer until a square second conductive layer is formed; removing the mask layer; forming a lightly doped region in the substrate at the side where the second conductive layer is formed; forming a second spacer on the sidewall of the second conductive layer; and forming a drain region in the substrate at the side of the second conductive layer.