Patent ID: 6446107
Filing Date: 2002-09-03
Classification: G06F

Abstract:
Circuitry for adding a first binary number having a plurality of bits to a second binary number having a plurality of bits to produce a third binary number having a plurality of bits and a fourth binary number having a plurality of bits and corresponding to the third binary number plus one, said circuitry comprising a plurality of stages wherein each stage includes:a first input for receiving a bit of the first binary number; a second input for receiving a bit of the second binary number having the same binary weight as the bit received at the first input; first output means for producing a bit of the third binary number and comprising exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number; and second output means for producing a bit of the fourth binary number comprising exclusive OR means for combining the first signal and a third signal to produce a bit of the fourth binary number, wherein said first and second output means produce the third and fourth binary numbers substantially simultaneously.