Patent ID: 6320789
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A method of Chisel programming in non-volatile memory by source bias, wherein while running both reading and programming operations, a substrate reading voltage, a gate reading voltage, a drain reading voltage, a source reading voltage, a substrate programming voltage, a gate programming voltage, a drain programming voltage and a source programming voltage are used, the method comprising the steps of:changing the substrate programming voltage to reduce the difference between the changed substrate programming voltage and he substrate reading voltage;changing the gate programming voltage, the drain programming voltage and the source programming voltage corresponding with the changing of the substrate programming voltage, wherein the changed substrate programming voltage, the gate programming voltage, the drain programming voltage and the source programming voltage are 0 V, 5.about.9 V, 3.8.about.6.3 V and 0.5.about.3 V, respectively; andrunning the programming operation by using the changed substrate programming voltage.