Patent ID: 7358120
Filing Date: 2008-04-15
Classification: H01L

Abstract:
1. A method of fabricating a Read Only Memory (ROM) on a silicon-on-insulator (SOI) wafer, said method comprising the steps of: a) forming a plurality of stripes oriented in a first direction in a silicon surface layer; b) undercutting ones of said plurality of stripes, cavities being formed along at least one edge of said ones; c) filling said cavities with a conductive material; d) forming a plurality of diffusions in an upper surface of said ones, said diffusions forming diodes in said upper surface; e) forming a plurality of conductive contacts, each of said plurality of conductive contacts contacting one of said diodes at said upper surface; and f) forming a plurality of conductive lines in a second direction orthogonal to said first direction, a ROM cell being located at each intersection of one of said plurality of conductive lines with one of said plurality of silicon stripes.