Patent ID: 6076145
Filing Date: 2000-06-13
Classification: G06F

Abstract:
An instruction supplying apparatus having a data memory storing instruction data and a tag memory storing first address information corresponding to the instruction data, and adapted for outputting instruction data stored in the instruction data memory corresponding to an instruction request from an instruction requesting unit, comprising:an output buffer circuit storing the instruction data output from the data memory and outputting the stored instruction data;an address buffer circuit storing information that is input corresponding to second address information included in the instruction request and that is used to access the data memory when said output buffer circuit has instruction data and a data release signal is not issued by the instruction requesting unit, and when said output buffer circuit has instruction data and information is present in said address buffer circuit; andan access circuit accessing the data memory with information stored in said address buffer circuit and enabling the data memory to output instruction data to said output buffer circuit, said access circuit accessing the data memory independently from an accessing operation for the tag memory with the second address information.