Patent ID: 7185159
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. A data processing apparatus having a secure domain and a non-secure domain, in the secure domain devices of the data processing apparatus having access to secure data which is not accessible in the non-secure domain, the data processing apparatus comprising: a device bus; a plurality of devices coupled to the device bus, each operable to issue a memory access request pertaining to either said secure domain or said non-secure domain at least one of the devices being operable in a plurality of modes, including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain; and a memory coupled to the device bus and operable to store data required by the devices, the memory comprising secure memory for storing secure data and non-secure memory for storing non-secure data; each device being operable to issue onto the device bus the memory access request when an access to an item of data in the memory is required, the memory access request issued by the device including a domain signal identifying whether the memory access request pertains to said secure domain or said non-secure domain, and the domain signal being provided for use in determining whether the access defined by the memory access request is allowed to proceed.