Patent ID: 9158623
Filing Date: 2015-10-13
Classification: G06F,G11C,H03M

Abstract:
1. A memory system comprising: a flash subsystem configured to save pages of information, the pages of information organized into blocks, each page of information including one or more codewords, each codeword having data and error correction code (ECC), each of the pages of information having an upper page of data and a lower page of data, the flash subsystem configured to save upper pages in upper page locations and to save lower pages in lower page locations, the flash subsystem including more than one flash die, a first block being in a first flash die and a second block being in a second flash die, wherein the lower page of data is saved in the first block and the upper page of data is saved in the second block, and a flash controller coupled to the flash subsystem and operable to save pages of information in the flash subsystem, the flash controller operable to save a page of information having a codeword with data and ECC, wherein the codeword is split between an upper page location and a lower page location of the flash subsystem and a lower page of data of the first block being paired with an upper page of data of the second block causes substantially concurrent reading of the lower and upper pages of data.