Patent ID: 6350654
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A method for fabricating a ROM device, the method comprising the steps of:preparing a semiconductor substrate of a first semiconductor type; partitioning the substrate into a peripheral region and a cell region; forming a plurality of STI structures at predefined locations in the substrate, including a plurality of first STI structures in the peripheral region and a plurality of second STI structures in the cell region, wherein each of the first and second STI structures includes a trench formed in the substrate and a dielectric isolation layer filled in the trench; forming a first photoresist layer to cover the entire peripheral region while exposing the entire cell region; with the first photoresist layer serving as mask, performing a first ion-implantation process on the cell region to dope an impurity element of a second semiconductor type into the unmasked regions of the substrate so as to form a plurality of buried bit lines of the second semiconductor type in the substrate, wherein each of the buried bit lines is located between one neighboring pair of the second STI structures in the cell region and is formed to a depth in the substrate that is shallower than the depth of the second STI structures; removing the dielectric isolation layers in all of the second STI structures in the cell region, leaving a plurality of empty trenches behind; removing the first photoresist layer; forming a conformal insulating layer over both the peripheral region and the cell region in such a manner that the conformal insulating layer in the cell region is formed to a substantially uniform thickness over the buried bit lines and over the sidewalls of the trenches, but not entirely filling the trenches; forming a conductive layer over the conformal insulating layer in both the peripheral region and the cell region, which fills all the remaining empty portions of the trenches in the cell region; removing selected portions of the conductive layer in such a manner that the remaining part of the conductive layer in the cell region serves as a word line and the remaining part of the same in the peripheral region serves as a gate; forming sidewall spacers on the sidewalls of the gate in the peripheral region and the word line in the cell region; forming a pair of source/drain regions in the peripheral region of the substrate, which, in association with the gate in the peripheral region, form a MOS transistor; forming a dielectric layer to cover the resulting structure; forming a conductive plug in the dielectric layer, which is electrically connected to one of the source/drain regions; forming a second photoresist layer over the dielectric layer, which is selectively removed to form an opening located directly above a selected one of the channel regions between the buried bit lines, which channel region is to be code implanted; and with the second photoresist layer serving as mask, performing a second ion-implantation process so as to dope an impurity element into the selected one of the channel regions between the buried bit lines.