Patent ID: 7002845
Filing Date: 2006-02-21
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising memory cell units arranged in an array form; a plurality of word lines formed by continuously extending gates of memory cells included in said memory cell units; a plurality of bit lines continuously extending in said memory cell array and crossing with said word lines perpendicularly; a first block in which first memory cell units each having at least one memory cell and at least one selection gate transistor are arranged; and a second block in which second memory cell units each having at least one memory cell and at least one selection gate transistor are arranged, wherein said first block is arranged on a first end portion of said memory cell array, said second block is arranged in another portion, a structure of each of said first memory cell units is different from a structure of each of said second memory cell units, and said plurality of bit lines continuously extend between said first block and said second block.