Patent ID: 7596729
Filing Date: 2009-09-29
Classification: G01R,G11C

Abstract:
1. A testing system, comprising: a signal generator operable to initially generate and output from the testing system sets of memory write command signals and sets of address signals and to output from the testing system respective sets of write data signals along with each of the sets of the memory write command signals, the signal generator further being operable to subsequently generate and output from the testing system sets of memory read command signals and sets of the address signals; a comparator coupled to the signal generator, the comparator being operable to receive each set of read data signals received by the testing system responsive to each set of the memory read command signals, the comparator being operable to compare each set of received read data signals to a corresponding set of the write data signals, the comparator being operable to output fail data signals having a first value responsive to the received set of read data signals matching the corresponding set of write data signals and having a second value responsive to the received set of read data signals not matching the corresponding set of write data signals; and a lossless fail data compressor coupled to the comparator, the fail data compressor being operable to generate from the fail data signals compressed fail data comprising at least one record of a first type containing an indication of the number of consecutive sets of address signals for which respective fail data signals have the same value, the compressed fail data further comprising at least one record of a second type containing an indication of the number of times that a sequence of records of the first type are repeated.