Patent ID: 7440884
Filing Date: 2008-10-21
Classification: G06F

Abstract:
1. An apparatus for restoring memories in a circuit design that is being debugged, the circuit design comprising a random access memory (RAM), the RAM comprising a write port having a data input and an address input, the RAM further comprising a read port and a plurality of memory locations for storing data, each of the plurality of memory locations comprising an address, comprising: a shadow read port corresponding to the write port, said shadow read port comprising an address input that receives an address from an address input of the RAM and a data output; a buffer, said buffer in communication with the address input of the RAM, said buffer also in communication with said data output of said shadow read port, said buffer having an address output and a data output; a first multiplexer feeding the address input on the write port, said first multiplexer having a first input in communication with said address output of said buffer, said first multiplexer having a second input in communication with the address input of the RAM; a second multiplexer feeding the data input on the write port, said second multiplexer having a first input in communication with said data output of said buffer, said second multiplexer having a second input in communication with the data input of the RAM; and said first multiplexer and said second multiplexer each having a select input that switches between a first mode and a second mode, wherein said shadow read port, said buffer, said first multiplexer, and said second multiplexer each are implemented via a hardware logic verification system selected from a group consisting of a processor-based emulation system and a field programmable gate array-based emulation system.