Patent ID: 7366877
Filing Date: 2008-04-29
Classification: G06F

Abstract:
1. A method for issuing instructions in a multithreaded computer processor, the method comprising the steps of: (1) receiving a set of computer instructions in an instruction issue logic, wherein each instruction of said set comprises one instruction from each of a plurality of independent instruction threads; (2) identifying as dependent instructions those received instructions that require a result from a prerequisite instruction; (3) determining a probability for each received instruction that the received instruction will complete all stages of a multi-stage instruction pipeline of the processor without causing a stall, wherein the probability for each received instruction is expressed at a percentage value; (4) selecting the received instruction of the set that is least likely to cause a stall in the multi-stage pipeline; and (5) issuing-the selected instruction into the pipeline for processing, from the instruction issue logic, when the probability for the selected instruction is above a predetermined threshold that is 50%.