Patent ID: 7519930
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. A method of calculating a model formuala for circuit simulation of a semiconductor device comprising a source, a drain, and a gate having a length L, the method comprising: calculating first parasitic resistance independent of gate voltage using actually measured data of the semiconductor device; calculating second parasitic resistance dependent on the gate voltage using IV characteristic of the semiconductor device from which the first parasitic resistance is removed; dividing the second parasitic resistance into channel resistance and third parasitic resistance generated under both ends of a gate length using plural kinds of diffusion resistance TEG in which the width W of each kind of diffusion resistance is the same as each other, but the length L of each kind of diffusion resistance is different from the other kinds of diffusion resistance; and obtaining an I-V characteristic formula for the semiconductor device using the third parasitic resistance as an independent characteristic; wherein the first parasitic resistance is equal to 2·R where R simulating the circuit of the semiconductor device using the model formula calculated by the method.