Patent ID: 7279993
Filing Date: 2007-10-09
Classification: H03L

Abstract:
1. A phase-locked loop, comprising: an oscillator that outputs an oscillator signal; a phase detector having an input that receives a signal proportional to the oscillator signal and having an output that provides a phase detector signal; a charge pump having an input that receives the phase detector signal from said phase detector; a filter coupled to said charge pump; a voltage controlled oscillator coupled to said filter and structured to produce a VCO signal; a fractional frequency divider coupled to receive the VCO signal, said fractional frequency divider being structured to send an frequency divider signal to said phase detector, said fractional frequency divider comprising a prescaler structured to divide the VCO signal by an integer number P or by an integer number P+1 and output a prescaler signal, said fractional frequency divider emitting a first signal representative of the division by P or by P+1; a digital-analog converter coupled to said charge pump, said filter, and said fractional frequency divider, the digital-analog converter having an input that receives said first signal and an output that provides a DAC signal that is aligned to said first signal; an accumulator coupled to said fractional frequency divider and with said digital-analog converter; and a synchronizing circuit coupled to said digital-analog converter and to said prescaler and structured to synchronize the DAC signal output from the digital-analog converter with the prescaler signal output from the prescaler.