Patent ID: 6658539
Filing Date: 2003-12-02
Classification: G06F

Abstract:
A method for improving performance of a multiprocessor data processing system having processor groups with shared caches, said method comprising:responsive to a snoop by a first processor within a processor group of a modification to a shared cache line in a cache of a third processor that is not within said processor group, setting a coherency state of said shared cache line within a shared cache of said processor group to a first coherency state indicating that said cache line has been modified by a processor not within said processor group and is not yet updated within said shared cache; and issuing a request for said cache line by said first processor to an interconnect (system bus) of said data processing system when said cache line is in said first coherency state; and responsive to an indication that said first processor should utilize data currently present within said shared cache, setting a coherency state of said cache line to a processor-specific second coherency state indicating that subsequent request for said cache line by said first processor should be provided super-coherent data, while a subsequent request for said cache line by a next processor in said processor group that has not yet issued a request for said cache line may be issued to the system bus of the data processing system.