Patent ID: 6446317
Filing Date: 2002-09-10
Classification: H01L,H05K,Y10T

Abstract:
A method for fabricating a hybrid capacitor within an integrated circuit package, the method comprising:fabricating a parallel plate capacitor embedded within a first layer of the package, wherein the parallel plate capacitor includes a first conductive layer, a second conductive layer, and a dielectric layer that electrically isolates the first conductive layer from the second conductive layer; and fabricating and electrically connecting a second source of capacitance to the parallel plate capacitor, wherein the second source of capacitance is formed in a second layer of the package, and is formed from a set of self-aligned via capacitors embedded within the second layer, and each of the self-aligned via capacitors includes an inner conductor electrically connected to the first conductive layer, and an outer conductor electrically connected to the second conductive layer.