Patent ID: 6815288
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of manufacturing a memory merged logic (MML) semiconductor device, the method comprising the steps of:(a) preparing a semiconductor substrate on which a memory area and a logic area are defined, and on which an isolation layer and a gate oxide layer formed on an active region defined by the isolation layer have been formed; (b) forming a gate conductive layer comprised of silicon on the memory area and the logic area; (c) lowering a height of the gate conductive layer formed on the memory area and implanting a predetermined conductive type of impurities into the lowered gate conductive layer; and (d) forming a suicide layer only on the lowered gate conductive layer on the memory area using deposition and photolithography, wherein the top surface of the silicide layer is lower than the top surface of the gate conductive layer formed on the logic area.