Patent ID: 8966282
Filing Date: 2015-02-24
Classification: G06F,G09C,H04L

Abstract:
1. Data processing apparatus comprising: a single instruction multiple data register file; and single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein said single instruction multiple data processing circuitry is configured to be controlled by a further program instruction to perform a further processing operation upon a vector data value comprising a sequence of data elements held within an input operand register of said single instruction multiple data register file to produce an output operand stored within an output operand register of said single instruction multiple data register file, said output operand having a first portion with a value dependent upon all data elements within said sequence of data elements, wherein said further program instruction is a cryptographic program instruction that operates to generate an output hash value as said output operand in dependence upon a plurality of words of data forming said vector data value.