Patent ID: 6624066
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A method of fabricating an integrated circuit comprising the steps of:providing a semiconductor body having a first and a second dielectric layer formed thereover, wherein said first dielectric layer has a via etched therein and said second dielectric layer has a trench etched therein, said trench overlying said via; using chemical vapor deposition, depositing a first barrier layer over said second dielectric layer including within said trench and said via; after depositing said first barrier layer, sputter etching to remove a portion of said first barrier layer from a bottom of said trench and from a bottom of said via, said sputter etching further pulling back upper corners of said trench and upper corners of said via; after said sputter etching, depositing a second barrier layer over said first barrier layer; and filling said trench and said via with a metal.