Patent ID: 7436706
Filing Date: 2008-10-14
Classification: G11C

Abstract:
1. An integrated circuit device comprising: a memory cell array having a plurality of memory cells wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes: wherein the body region is electrically floating; and wherein each memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; circuitry, coupled to the memory cell array, to program one or more of the memory cells, wherein the circuitry includes: wherein the temporal characteristics of the one or more control signals of the first predetermined program operation are different from the temporal characteristics of corresponding control signals of the second predetermined program operation.