Patent ID: 6650006
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A semiconductor package with stacked chips, comprising:a chip carrier; at least one first chip mounted on the chip carrier and electrically connected to the chip carrier, while the first chip has an active surface formed with an attachment area and at least one bond pad area thereon adjacent to the attachment area; at least one second chip having an active surface and an inactive surface, wherein the active surface includes at least one bond pad area for electrically connecting die second chip to the chip carrier, and the inactive surface is attached with a rigid interposer which is disposed on the attachment area of the first chip and thereby interposed between the first and second chips, the rigid interposer having a surface area at least equal to that of the second chip, while the second chip is sufficiently held in position above the first chip by the rigid interposer, making the bond pad area of the first chip exposed to outside of the rigid interposer and the second chip; and an encapsulant for encapsulating the first chip and the second chip.