Patent ID: 7433242
Filing Date: 2008-10-07
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source formed in the semiconductor layer, a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of the charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell before writing data, data is written to the memory cell after the absolute value of the threshold voltage of the memory cell was reduced.