Patent ID: 7768052
Filing Date: 2010-08-03
Classification: H01L

Abstract:
1. A device comprising: a lower electrode layer disposed on a semiconductor substrate; a capacitor dielectric disposed on said lower electrode layer; an upper electrode disposed on said capacitor dielectric, wherein said upper electrode has a lateral boundary, wherein said capacitor dielectric is disposed within an inter-electrode region, said inter-electrode region disposed within said lateral boundary between said lower electrode layer and said upper electrode, and wherein an exposed portion of said lower electrode layer lies outside said lateral boundary; a conformal layer of an insulating material disposed over said upper electrode and over said exposed portion of said lower electrode layer; an undercutting in said inter-electrode region, wherein said capacitor dielectric is absent from said undercutting and said undercutting is filled by said insulating material; and an anti-reflective layer disposed over said conformal layer of said insulating material.