Patent ID: 6742014
Filing Date: 2004-05-25
Classification: G06F

Abstract:
A method for performing binary addition with a conditional carry, the method comprising:utilizing logic circuitry to receive at least two operands, wherein each of said at least two operands comprise at least one block of bits; representing the carry in to each bit of said at least one block of bits with three signals, wherein one of said three signals (Gin) represents whether a carry in to a set of corresponding operand bits of said at least one block of bits is generated within said at least one block of bits, wherein another of said three signals (Kin) represents whether any carry in to the said at least one block of bits is killed before reaching said set of corresponding operand bits, and wherein another of said three signals (Pin) represents whether a carry in to the said at least one block of bits is propagated to said set of corresponding operand bits; and calculating the sum of said at least two operands using said Gin, Kin and Pin signals.