Patent ID: 8685788
Filing Date: 2014-04-01
Classification: B82Y,H01L

Abstract:
1. A method for manufacturing a nanowire TFET with vertical structure, comprising the following steps: providing a heavily-doped p-type semiconductor substrate; developing a ZnO gate seed crystal layer on a specific region of the substrate; developing a ZnO nanowire in water bath using the gate seed crystal layer; forming a first insulation film around the ZnO nanowire and the substrate; forming a heavily-doped polycrystalline silicon layer through deposition on the first insulation film; etching the formed polycrystalline silicon layer and the first insulation film to expose the ZnO nanowire; defining the gate electrode pattern on the formed polycrystalline silicon layer; forming a second insulation film, and etching the second insulation film to expose the top of the ZnO nanowire; forming a metal drain electrode onto the top of the exposed ZnO nanowire; forming a third insulation film, and etching the third insulation film to form a through-hole, and forming a layer of metal in the through-hole to contract the drain electrode and gate electrode.