Patent ID: 6635920
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A non-volatile semiconductor memory device comprising:a semiconductor substrate having a main surface; source regions and drain regions of memory cell transistors formed in said main surface; and gates of said memory cell transistors which are formed on said main surface via a gate isolation film and which are located between said source regions and said drain regions, the gates having floating gates and control gates; wherein said source regions include first high impurity concentration regions of a first conductive type and first low impurity concentration regions of a second conductive type; said drain regions include second high impurity concentration regions of the first conductive type and second low impurity concentration regions of a second conductive type; the impurity concentration of the first conductive type included in said first high impurity concentration regions is higher than the impurity concentration of the first conductive type included in said second high impurity concentration regions; and the impurity concentration of the second conductive type included in said first low impurity concentration regions is higher than the impurity concentration of the second conductive type included in said second low impurity concentration regions.