Patent ID: 7271097
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor protection element comprising: a first step of implanting an impurity into a semiconductor substrate to form a first region of a first impurity concentration; a second step of forming a pair of second regions having a second impurity concentration being higher than said first impurity concentration on both sides of said first region on a surface of said semiconductor substrate; and a third step of forming silicide layers being in contact with a surface of said second region; wherein, in said third step, each of said silicide layers is formed in a manner that said first region has a first surface region not covered by said silicide layers and said second region has a second surface region not covered by said silicide layers and that said first surface region is sandwiched by two said second surface regions; and wherein each of said silicide layers makes up a low resistance region having a relatively low resistance value, each of said second surface regions makes up an intermediate resistance region having an intermediate resistance value, and said first surface region makes up a high resistance region having a relatively high resistance value.