Patent ID: 6442070
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory cells each having a floating gate, wherein a threshold level of each memory cell depends on a value of electric charge in said floating gate of said memory cell, wherein said threshold level of each memory cell is placed at one of a first area and a second area; and a controller which controls to set each threshold voltage of ones of said plurality of memory cells: wherein said controller performs a first setting operation and a verifying operation, wherein said first setting operation shifts threshold voltages of said ones of said plurality of memory cells in a direction from said first area to said second area, and wherein said verifying operation detects erratic memory cells which have threshold voltages which are outside of said second area and on a side of said second area which is opposite of a middle area between the first area and the second area.