Patent ID: 6650720
Filing Date: 2003-11-18
Classification: H03L,H04L

Abstract:
A high speed data receiver comprising:a phase detector circuit coupled to receive a high speed input data signal and provide at least two analog voltage outputs; a transconductance circuit coupled to the phase detector circuit for converting the at least two analog voltage outputs into an analog output current, wherein the transconductance circuit includes a variable gain adjust circuit for adjusting a gain of the transconductance circuit in response to variations in a magnitude of the high speed input data signal; an oscillator coupled to the transconductance circuit and providing the second input signal to the phase detector in response to the analog output current; a phase frequency detector circuit coupled to receive an output of the oscillator and provide an output indicating a frequency difference between the output of the oscillator and a reference clock signal; and a charge pump circuit for providing an output signal in response to the phase frequency detector circuit, the charge pump output signal is coupled to an input of the oscillator.