Patent ID: 6092181
Filing Date: 2000-07-18
Classification: G06F

Abstract:
A superscalar microprocessor for executing instructions obtained from an instruction store, said microprocessor comprising:means for fetching a plurality of instructions from the instruction store;means, responsive to said fetching means, for buffering said plurality of instructions;means, responsive to said buffering means, for concurrently decoding and dispatching a plurality of said buffered instructions for execution; andmeans, responsive to said dispatching means, for executing said dispatched instructions out-of-order, said executing means including:a plurality of functional unit means for processing data wherein each said functional unit means processes data,register file means comprising temporary registers for temporarily storing out-of-order execution results from said functional unit means and a register array for storing results from said temporary registers; andbus means for providing plural data routing paths between said register file means and said plurality of functional unit means for concurrently supplying data to more than one of said functional unit means and thereby enabling concurrent execution of more than one of said dispatched instructions by said plurality of functional unit means.