Patent ID: 6532570
Filing Date: 2003-03-11
Classification: G01R,G06F

Abstract:
A method of designing an integrated circuit, comprising:calculating a current density for each metal lead in an nth design of an integrated circuit, the nth design of the integrated circuit comprising an nth set of metal leads; estimating a temperature distribution over a silicon die; calculating a mean time to failure for each metal lead in the first set of metal leads; wherein the mean time to failure is a function of the current density and the temperature distribution of the silicon die; calculating a reliability of each metal lead in the first set of metal leads; calculating a first reliability of the integrated circuit wherein the first set of metal leads are connected in series, wherein due to the series connection the failure of one metal lead of the nth set of metal leads causes the integrated circuit to fail, wherein calculating a first reliability of the integrated circuit is based on the mean time to failure for each set of metal leads and wherein calculating a first reliability of the integrated circuit is based on calculating a reliability of each metal lead in the first set of metal leads; and arranging the nth set of metal leads by reliability, wherein arranging the nth set of metal leads by reliability allows calculation of a number of metal leads to be redesigned.