Patent ID: 6100753
Filing Date: 2000-08-08
Classification: G05F

Abstract:
A bias stabilization circuit for an amplification transistor comprising:a constant current source comprising a first resistor and a depletion type transistor having a source, a gate, and a drain in which the drain of said depletion type transistor is connected to a supply voltage, said first resistor being connected between the source and the gate of said depletion type transistor;a level shift and feedback circuit comprising a second resistor and a third resistor connected at a connection node, and a common drain transistor having a drain connected to the supply voltage, and a gate connected to the gate of said depletion type transistor, said second and third resistors being connected between a source of said common drain transistor and a ground;a fourth resistor connected between the connection node of said second and third resistors and a gate of said amplification transistor; anda reference voltage generation transistor having a gate connected to the connection node of said second and third resistors, a drain connected to the gate of said depletion type transistor, and a source connected to the ground.