Patent ID: 6049859
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A processor element which is one of a plurality of processor elements arranged in a matrix as part of an image-processing processor, the processor element comprising:a first arithmetic logic unit having a first input for input data;a multiplier/adder unit having an input for the input data and having an output connected to a second input of the first arithmetic logic unit;a second arithmetic logic unit having an input for the input data and having an output connected to an input of the multiplier/adder unit;a local general purpose memory supplied with calculation data via a global bus and having an output connected to a second input of the second arithmetic logic unit;a register bank having outputs to supply output data, the outputs connected to inputs of at least one of the local general purpose memory, the second arithmetic logic unit and the multiplier/adder unit; anda storage unit of a distributed image section buffer having an output connected to a first input of the second arithmetic logic unit and having inputs for receipt of image data wherein the inputs are connected to neighboring storage units of respectively neighboring processor elements or connected to a pixel bus if a neighboring processing element is not present.