Patent ID: 6031775
Filing Date: 2000-02-29
Classification: G11C

Abstract:
A memory comprising:a memory array having a plurality of memory cells coupled to a plurality of bit lines, wherein data from a selected memory cell of the plurality of memory cells is associated with a bit line pair from a plurality of bit line pairs;first and second global data lines for coupling data from the memory cells to an output of the memory;a latch having a first input/output coupled to a first bit line of the bit line pair, a second input/output coupled to a second bit line of the bit line pair, a first power terminal for receiving a first voltage for powering the latch, and a second power terminal for receiving a second voltage for powering the latch, said second voltage being lower than said first voltage;a first P channel transistor having a control electrode coupled to the first input/output, a first current electrode for receiving the second power supply voltage, and a second current electrode coupled to the first global data line; anda second P channel transistor having a control electrode coupled to the second input/output, a first current electrode for receiving the second power supply voltage, and a second current electrode coupled to the second global data line.