Patent ID: 7882410
Filing Date: 2011-02-01
Classification: G01R

Abstract:
1. A method of testing an integrated circuit having a first capture clock domain with a first capture clock domain scan-chain and a first non-capture clock domain with a first non-capture clock domain scan chain; the method comprising: shifting a beginning subset of a first portion of a test vector into the first capture clock domain scan chain; shifting a beginning subset of a second portion of a test vector into the first non-capture clock domain scan chain; shifting an ending subset of the second portion of the test vector into the first non-capture clock domain scan chain, wherein the union of the beginning subset of the second portion of the test vector and the ending subset of the second portion of the test vector is equal to the second portion of the test vector; shifting an ending subset of the first portion of the test vector into the first capture clock domain scan chain, wherein the union of the beginning subset of the first portion of the test vector and the ending subset of the first portion of the test vector is equal to the first portion of the test vector, wherein the shifting an ending subset of the first portion of the test vector into the first capture clock domain scan chain occurs after the shifting an ending subset of the second portion of the test vector into the first non-capture clock domain scan chain; and clocking the first capture clock domain to generate test results in the first capture clock domain scan chain.