Patent ID: 6199153
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A computing apparatus, comprising:a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size;an address bus configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size;wherein the address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N;an encoder configured to map the address bits into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells;said encoder also configured to arrange the address bits of the address into an encoded packet so that, in short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus; anda controller for generating one or more bits indicating a probe miss;wherein: one or more of the cells of the encoded packet further includes at least one of the probe miss bits.