Patent ID: 6065107
Filing Date: 2000-05-16
Classification: G06F

Abstract:
A register cell apparatus for storing data in a pipelined processing system, said apparatus comprising:a first latch having a first data input, a feedback input, a first output, a first clock input, and a selector input, said first latch being responsive to receipt of a clocking signal on the first clock input to copy a signal on the first data input to the first output if the selector input at the time of receiving the clocking signal has a first value, said first latch being responsive to receipt of the clocking signal on the first clock input to copy a signal on the feedback data input to the first output if the selector input at the time of receiving the clocking signal has a second value;a second latch having a second data input, a second output, and a second clock input, the second input coupled to the first output, said second latch being responsive to receipt of a clocking signal on the second clock input to copy a signal on the second data input to the second output;a third latch having a third data input, a third output, a third clock input, and a inhibit input, the third data input coupled to the second output, the third output coupled to the feedback input, the third latch being responsive to receipt of a clocking signal on the third clock input to copy a signal on the third data input to the third output if the inhibit input at the time of receiving the clocking signal is free from a predetermined inhibit signal;a first clock source coupled to the first clock input to provide a first clock signal including a first plurality of clock pulses having a first frequency and a first period between adjacent ones of said clock pulses;a second clock source coupled to the second clock input to provide a second clock signal including a second plurality of clock pulses having the first frequency and the first period, said second clock signal being delayed from the first clock signal by a first delay amount less than the first period; anda third clock source coupled to the third clock input to provide a third clock signal including a third plurality of clock pulses having the first frequency and the first period, said third clock signal being delayed from the second clock signal by a second delay amount less than the first period.