Patent ID: 7546561
Filing Date: 2009-06-09
Classification: G01R

Abstract:
1. A method for determining scan chain correspondence between a reference design level and an implementation design level of an integrated circuit, comprising: defining a reference scan chain at the reference design level having reference latches and reference constraints, each of the reference latches having a reference latch logic cone, each of the reference constraints having a reference constraint logic cone with at least one reference constraint logic cone input and being associated with at least one of the reference latches wherein each of the reference latch logic cones has at least one reference latch logic cone input; defining an implementation scan chain at the implementation design level having implementation latches and at least one implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with at least one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone, wherein the determining includes