Patent ID: 8659079
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A transistor device comprising a first vertical transistor structure, wherein the first vertical transistor structure comprises: a substrate; a first dielectric layer disposed in a first trench of the substrate; a first gate disposed in the first dielectric layer, wherein the first gate defines, at both sides thereof, a first channel region and a second channel region in the substrate, wherein the first gate has a cylindrical structure, and the first channel region and the second channel region are respectively a curved channel disposed at both sides of the cylindrical structure; a first doped region disposed in the substrate, wherein the first doped region is located below the first channel region; a second doped region disposed in the substrate, wherein the second doped region is located above the first channel region; a third doped region disposed in the substrate, wherein the third doped region is located below the second channel region; and a fourth doped region disposed in the substrate, wherein the fourth doped region is located above the second channel region.