Patent ID: 8482041
Filing Date: 2013-07-09
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising the steps of: providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel; forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel completely surrounded by a first gate, and a sidewall of the first pillar body is oriented by a plurality of crystal planes, where a selected second crystal plane provides a first carrier mobility; and forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel completely surrounded by a second gate, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility, wherein the pillar shape of said first crystal plane and the pillar shape of said second crystal plane are not equivalent by a symmetry transformation.