Patent ID: 9209037
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit, the method comprising: forming a group of fin structures in a selected area of a semiconductor substrate, wherein the group includes two terminal fin structures and non-terminal fin structures; covering the group of fin structures and the semiconductor substrate with a mask; forming at least one trench in the mask to define at least one exposed terminal fin structure in the selected area; removing the at least one exposed terminal fin structure to provide the selected area with a desired number of fin structures; forming a second mask overlying the semiconductor substrate, wherein the selected area includes a first portion and a second portion that share a boundary, wherein forming the group of fin structures comprises forming a first group of fin structures in the first portion and the second portion and forming a second group of fin structures in the second portion; patterning the second mask to form a trench extending perpendicular to the first group of fin structures and the second group of fin structures and overlying the boundary, wherein the trench exposes middle portions of the first group of fin structures; and etching the middle portions of the first group of fin structures exposed by the second mask.