Patent ID: 6407604
Filing Date: 2002-06-18
Classification: H03K

Abstract:
A register circuit, comprising:a master latch; a slave latch that includes a first driver transistor disposed between a first supply node and a register output terminal; a second driver transistor disposed between a second supply node and the register output terminal; a first controllable impedance path disposed between a control terminal of the first driver transistor and an output of the master latch, the first controllable impedance having a low impedance in response to a first clock value; a second controllable impedance path disposed between a control terminal of the second driver transistor and the output of the master latch, the second controllable impedance having a low impedance in response to the first clock value; and a disable circuit that disables the first and second driver transistors when the slave latch circuit latches data from the master latch.