Patent ID: 8392664
Filing Date: 2013-03-05
Classification: G06F

Abstract:
1. A network on chip (‘NOC’) comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communications between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; and at least one IP block further comprising a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory, wherein the cache controller configured to lock segments of the cache further comprises the cache controller configured to load and lock a cache line in a segment upon the first load of the cache line by a thread owning private data and based on the thread's private data.