Patent ID: 8031158
Filing Date: 2011-10-04
Classification: G09G,G11C

Abstract:
1. A driving circuit for a flat panel display device, comprising: a generation unit for generating 4-phase form generation clocks; a drain voltage terminal and a source voltage terminal; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the 4-phase form generation clocks, one of the shift register stages including: first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the 4-phase form generation clocks; a second transistor connected to the second output terminal and the first transistor; and third to at least eighth transistors, each transistor having gate, drain and source terminals, wherein each gate line is connected to a node between the first and second transistors, wherein the one of the preceding shift register stages is the shift register stage immediately preceding said one of the shift register stage, and the one of the subsequent shift register stages is the shift register stage immediately following the next shift register stage, wherein the output signal of the one of the preceding shift register stages are outputted from a node between the first and second transistors of the one of the preceding shift register stages, wherein the output signal of one of the subsequent shift register stages are outputted from a node between the first and second transistors of the one of the subsequent shift register stages, wherein the drain terminal of the first transistor receives one of the 4-phase form generation clocks, and the source terminal of the first transistor is connected to the drain terminal of the second transistor, wherein the source terminal of the second transistor is connected to the source voltage terminal, wherein the gate terminal of the third transistor receives the output signal of the one of the preceding shift register stages, the drain terminal of the third transistor is connected to the drain voltage terminal, and the source terminal of the third transistor is connected to the drain terminals of the fourth and fifth transistors and the gate terminals of the seventh and first transistors, wherein the gate terminal of the fourth transistor receives the output signal of the one of the subsequent shift register stages, and the source terminal of the fourth transistor is connected to the source voltage terminal, wherein the gate terminal of the eighth transistor receives the output signal of the one of the preceding shift register stages, and the drain terminal of the eighth transistor is connected to the gate terminal of the fifth transistor, wherein the gate and drain terminals of the sixth transistor are connected to the drain voltage terminal, and the source of the sixth transistor is connected to the gate terminal of the fifth transistor, wherein the drain terminal of the seventh transistor is connected to the gate terminal of the fifth transistor, wherein the source terminals of the fifth and seventh transistors are connected to the source voltage terminal, wherein each of the 4-phase form generation clocks includes a high state and a low state, and the high states of two of the 4-phase form generation clocks overlap each other, wherein each of the 4-phase form generation clocks has one of a shape of two separate square waves having different pulse widths, a shape of two separated square waves having identical or equal pulse widths and a shape of a sum of indefinite sinusoidal waves having different amplitudes and periods.