Patent ID: 6079030
Filing Date: 2000-06-20
Classification: G06F

Abstract:
A computer system comprising:a processor for processing data;a copy-back cache, coupled to the processor, for storing data responsive to an access request to the processor in accordance with a data consistency maintenance protocol; anda memory subsystem, coupled to the processor and the cache via a bus, wherein the memory subsystem includes:a primary memory to which data is written and from which data is read;a buffer memory, coupled to the primary memory, for storing data read from the primary memory;control means for controlling the primary memory and the buffer memory to store pre-modified data to be modified during any interval between checkpoints in the buffer memory responsive to a transaction issued on the bus; andmeans for performing a checkpoint process by storing the context of said processor and the data in said cache in a modified state in the primary memory at checkpoints, without accessing the buffer memory.