Patent ID: 6160348
Filing Date: 2000-12-12
Classification: H01J

Abstract:
A DC plasma display panel comprising a plurality of display cells defined therein and organized in a matrix configuration, said display panel comprising:a first plate, comprising;a first substrate;a plurality of rows of cathodes extending substantially along a length of said first substrate, and comprising a plurality of holes therein spaced along said rows; anda dielectric layer covering said first substrate and said plurality of rows of cathodes, and comprising a plurality of holes therein, said holes being configured to align with the holes in said plurality of rows of cathodes; anda second plate, comprising;a second substrate;a plurality of rows of anodes extending substantially along a length of said second substrate;a plurality of barrier ribs extending substantially along a length of said second substrate, substantially parallel with said plurality of rows of anodes, wherein any two adjacent barrier ribs form a channel on said second substrate, such that said plurality of barrier ribs form a plurality of channels, and wherein at least one of said rows of anodes is positioned in at least one of said channels; andat least one phosphor layer deposited in at least one of said channels;wherein said DC plasma display panel is formed by combining said first plate with said second plate such that said barrier ribs on said second substrate of said second plate are in substantial touching proximity with said dielectric layer on said first substrate of said first plate, and wherein said channels formed by said barrier ribs and said rows of anodes on said second substrate run substantially orthogonal to said rows of cathodes on said first substrate, such that display cells are formed in said DC plasma display panel at locations proximate where said channels and said rows of anodes cross said rows of cathodes, creating said matrix of display cells.