Patent ID: 6555762
Filing Date: 2003-04-29
Classification: H01B,H01L,H05K,Y10T

Abstract:
A microelectronic package, whose circuitry has a cross-section width of between 0.7 mil and 2.0 mil, said microelectronic package comprising:a) a dielectric substrate having upper and lower lateral faces and at least one via being defined by a wall; b) electronic circuitry and features affixed to at least one of said lateral surfaces, said circuitry having a cross-sectional width of between 0.7 mil and 2.0 mil; and c) a composition comprising an interpenetrating network substantially filling said via, said network comprising a first matrix of cured thermosetting or thermoplastic material and a second matrix comprising an electrically conductive composition electrically connecting said via to said electronic circuitry.