Patent ID: 7704843
Filing Date: 2010-04-27
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a conductive structure on an active region of a semiconductor substrate that is defined by a device isolation layer on the substrate, the conductive structure including a gate pattern and source/drain regions adjacent to the gate pattern; forming a first semiconductor layer on the active region of the substrate by a selective epitaxial growth (SEG) process; forming an amorphous layer on the first semiconductor layer; forming a second semiconductor layer from a portion of the amorphous layer by a solid-phase epitaxy (SPE) process performed on the amorphous layer; and forming elevated structures on the source/drain regions of the conductive structure by removing a remaining portion of the amorphous layer from the substrate, so that the elevated structure includes the first semiconductor layer and the second semiconductor layer stacked on the first semiconductor layer.