Patent ID: 6521502
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A method of manufacturing a transistor, the method comprising in the following order:providing a gate structure; providing a deep amorphous implant; providing a shallow extension dopant implant; providing a tilted angle halo dopant implant, the tilted angle halo implant being the only halo implant step; forming a pair of spacers abutting the gate structure; providing a deep source/drain dopant implant; and annealing at a very low temperature, the annealing recrystallizing an amorphous region formed by the deep amorphous implant and activating dopants from the shallow extension dopant implant, the halo dopant implant, and the deep source/drain dopant implant via solid phase epitaxy wherein the deep amorphous implant is performed before the deep source/drain dopant implant and the deep source/drain dopant implant is performed after the tilted halo dopant implant.