Patent ID: 6563448
Filing Date: 2003-05-13
Classification: H03H,H03M

Abstract:
A digital-to-analog converter, comprising:a dual frequency divider, for dividing a system clock signal by a divisor selected from a pair of adjacent integers, to produce a sampling clock; a first sigma-delta modulator, for selecting the divisor for the dual frequency divider; a second sigma-delta modulator, for selecting an oversampling multiple from a pair of adjacent integers; a sampling latch, for sampling an input digital datastream synchronously with the sampling clock; a digital filter, having an input receiving the sampled input digital datastream and an input receiving the selected oversampling multiple in the form of a digital word, for generating a reconstructed datastream corresponding to the input digital datastream; and a digital-to-analog converter circuitry for producing an analog signal from the reconstructed datastream.