Patent ID: 6432748
Filing Date: 2002-08-13
Classification: H01L,H05K,Y10T

Abstract:
A method for fabricating a substrate for integrated circuit packages, said method comprising the steps of:(a) providing a copper plate, forming the plural conducting columns on defined areas of said copper plate by etching; (b) laminating an insulating layer and said copper plate together, said plural conducting columns are embedded into said insulating layer; (c) removing portions of said insulating layer for forming the blind vias each corresponding to said conducting columns; (d) plating the upper surface of said insulating layer with a copper layer, and said blind vias are also plated full with copper; (e) etching said copper layer on the surface of said insulating layer and said copper plate respectively for forming an upper circuit layer and a lower circuit layer; (f) covering said upper circuit layer and lower circuit layers respectively with solder mask layers.