Patent ID: 7388470
Filing Date: 2008-06-17
Classification: G06F

Abstract:
1. A comparator for comparing m-bit first data and m-bit second data, the comparator comprising: m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first data and the second data, and connecting or disconnecting the first node and the second node; a charge unit connected between the first node and a first voltage and charging the first node with the first voltage; a power connection controller disconnecting the second node and a second voltage in a first mode in response to a predetermined control signal and connecting the second node and the second voltage in a second mode, wherein the first node is charged with the first voltage in the first mode and the voltage level of the first node is output as a comparison result in the second mode; and a charge control & output unit outputting an inversion comparison result in response to an inversion control signal and the voltage level of the first node and controlling the operation of the charge unit, wherein the output inversion comparison result of the charge control & output unit is fed back to the charge unit.