Patent ID: 7667246
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A field programmable gate array (FPGA) structure of a semiconductor device includes a structure in which a plurality of gate electrode structures and sources/drains, a first group of first metal interconnections, a second group of second metal interconnections, and at least a third metal interconnection are sequentially stacked with insulating layers interposed therebetween, the structure comprising: one pair of contacts connecting one gate electrode structure and source/drain to a pair of corresponding first metal interconnections in the first group; another pair of contacts connecting another gate electrode structure and source/drain to an other pair of corresponding first metal interconnections in the first group; a first structure pattern having voltage-dependent conductivity interconnecting said one pair of contacts, said first structure pattern conducts each time a first predetermined voltage is applied to said first structure pattern; a pair of first vias connecting the other pair of corresponding first metal interconnections in the first group to a pair of corresponding second metal interconnections; a second structure pattern comprising voltage-dependent conductivity interconnecting the pair of the first vias, the second structure pattern conducts each time a second predetermined voltage is applied to said second structure pattern; and second vias connecting the first and second structure patterns to the at least a third metal interconnection.