Patent ID: 8420511
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A method for forming a transistor, comprising: providing a substrate, a semiconductor layer being formed on the substrate, the semiconductor layer and the substrate having a different crystal orientation; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, the interlayer dielectric layer being substantially flush with the dummy gate structure; removing the dummy gate structure to form an opening in the interlayer dielectric layer, the semiconductor layer being exposed at a bottom of the opening; non-crystallizing a portion of the semiconductor layer exposed in the opening to form the portion of the semiconductor layer as a channel layer, wherein a remaining portion of the semiconductor layer exposed in the opening has the different crystal orientation than the underlying substrate to produce a stress there-between and to increase a carrier mobility in the channel layer; annealing the channel layer so that the channel layer and the underlying substrate have a same crystal orientation to at least maintain the carrier mobility in the channel layer; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer.