Patent ID: 9203382
Filing Date: 2015-12-01
Classification: H03K

Abstract:
1. A method for gating a clock signal using complimentary switch logic, the method comprising: receiving a clock signal and an enable signal; pre-charging a first node and a second node to a first voltage level responsive to the clock signal and the enable signal having a second voltage level; latching, by a first latch, the first node to the second voltage level responsive to the enable signal having the first voltage level before or at a same time the clock signal having the first voltage level; latching, by a second latch, the second node to the first voltage level responsive to the enable signal having the first voltage level before or at the same time the clock signal having the first voltage level; and outputting a gated clock signal corresponding to the received clock signal if the second node has the first voltage level and the enable signal has the first voltage level while the received clock signal has the first voltage level.