Patent ID: 8972916
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. A method for checking the inter-chip connectivity of a three-dimensional (3D) integrated circuit (IC) using a computer, said method comprising: receiving a plurality of design files for a plurality of chips of the 3D IC such that each of the design files corresponds to a different chip, using the computer; generating, using the computer, a pre-simulated design file using the plurality of design files, wherein the pre-simulated design file identifies as least one signal communication between each of the plurality of chips; generating a plurality of inter-layer ports to be shared between at least two of the plurality of chips based on the pre-simulated design file, using the computer; generating a layout for each of the plurality of chips based on the design files for each of the plurality of chips; and conducting a layout versus schematic (LVS) check for each of the generated layouts by using the identified plurality of inter-layer ports.