Patent ID: 8166328
Filing Date: 2012-04-24
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a plurality of blocks, wherein the plurality of blocks comprises at least a core block, a peripheral block, and a memory unit; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal, wherein the activation signal has at least one of a high state and a low state wherein each of the plurality of blocks comprises a power supply providing the reduction power voltage based on dynamic voltage scaling, wherein the reduction power voltage for each of the plurality of blocks that has been activated by the respective activation signal with the low state drives the respective block, wherein a level of reduction power voltage for each of the plurality of blocks that has been activated by the respective activation signal with the low state are different, and wherein the normal power voltage for each of the plurality of blocks that has been activated by the respective activation signal with the high state drives the respective block.