Patent ID: 8936989
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate with an active area surrounded by an isolation structure; sequentially forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure on top of the active area; sequentially forming a composite dielectric layer and a second polysilicon layer covering the gate structure and the semiconductor substrate; defining a patterned photo-resist layer on the second polysilicon layer; patterning the second polysilicon layer and the composite dielectric layer to form an interconnect structure; forming a composite spacer surrounding the sidewalls of the gate structure and exposing the first capping layer over the first polysilicon layer in the gate structure; exposing a surface of the substrate within the active area; removing the photo-resist layer over the interconnect structure located partially on the isolation structures to expose a top surface of the patterned second polysilicon layer of the interconnect structure; performing a selective polysilicon deposition process over the exposed first capping layer, the exposed surface of the substrate within the active area, and the exposed top surface of the patterned second polysilicon layer of the interconnect structure such that forming a selective polysilicon layer is formed over and in direct contact with the exposed active area and the exposed top surface of the patterned second polysilicon layer of the interconnect structure, but the selective polysilicon layer is not formed over the exposed first capping layer over the gate structure; removing the first capping layer; defining the gate, source and drain area on the gate structure, the second polysilicon layer of the interconnect structure and the selective polysilicon layer lithographically for the proper dopant introduction; applying thermal treatment to activate and drive-in dopants to form source and drain regions within the exposed active area under the selective polysilicon layer; and forming a self-aligned silicide layer overlying the gate structure, source, drain and the interconnect structure, with the composite spacer separating the silicide layer overlying the gate structure from the silicide layer overlying the selective polysilicon layer over the source and drain regions.