Patent ID: 9218306
Filing Date: 2015-12-22
Classification: G06F,G11C

Abstract:
1. A memory sharing circuit comprising a plurality of unit processors connected to a memory, wherein each unit processor of the plurality of unit processors includes: a buffer configured to be connected to the memory via a buffering address bus and a buffering data bus; and a processor configured to be connected to the buffer for access to the memory through the buffer; wherein the plurality of unit processors are configured to allow all other processors of the plurality of unit processors to share the memory by preventing address or data bus collision; and wherein the memory sharing circuit further comprises a logic circuit unit configured to determine a logic value of a grant signal (GNT) of each processor of the plurality of unit processors and a logic value of an enable signal (EN) of each buffer of the plurality of unit processors using a signal buffered and output by the buffer.