Patent ID: 6415353
Filing Date: 2002-07-02
Classification: G06F,G11C

Abstract:
A memory device comprising:a plurality of memory cells configured in a plurality of banks, wherein the memory cells must be periodically refreshed to retain data values; a plurality of access control circuits, wherein each of the access control circuits is associated with one of the banks, each access control circuit enabling a refresh operation in its associated bank only when there is a refresh pending in the associated bank and there is no access requirement to the associated bank; a memory controller for accessing and refreshing the memory cells, wherein the memory controller controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external accesses to the memory cells; a central refresh timer for periodically asserting a refresh request signal; and daisy-chained connections extending between the access control circuits, wherein the daisy-chain connections sequentially pass the refresh request signal to the access control circuits in response to a clock signal.