Patent ID: 8976619
Filing Date: 2015-03-10
Classification: G06F,G11C

Abstract:
1. A semiconductor apparatus comprising: a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between a received external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, a sum of the first and the second delay amounts is a specific time period, a valid time period of the first control signal starts at a start of the read operation and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount that is detected by the phase detecting unit at a start of a valid time period of the second control signal generated by the generating unit.