Patent ID: 6747901
Filing Date: 2004-06-08
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory array comprising a plurality of floating-gate field-effect transistors disposed in a matrix configuration, the transistors being connected to corresponding row lines and column lines, at least one of the transistors comprising a source and a drain which are formed inside a P-type well formed inside an N-type well formed on a semiconductor substrate, a floating gate formed above a portion of the semiconductor substrate between the source and the drain with an insulating film interposed between the floating gate and said portion of the semiconductor substrate, and a control gate formed on the floating gate with another insulating film interposed therebetween; a first voltage application circuit applying a first voltage to the P-type well when an erasing pulse is applied; and a second voltage application circuit applying a second voltage to the N-type well when the erasing pulse is applied.