Patent ID: 6209061
Filing Date: 2001-03-27
Classification: G06F

Abstract:
Processing apparatus comprising the combination of:a) main memory means having a span of addresses;b) cache memory means;c) overlay memory means for providing high speed access to data values stored therein, said overlay memory means having an overlay span of addresses that falls within said span of addresses assigned to said main memory means, said overlay span of addresses remaining unchanged during execution of a program;d) processor means for operating a program to request access to data within said overlay span of addresses; ande) overlay controller means for responding to said request by accessing data from within said overlay memory means; andf) means for inhibiting transmission of any said request to said main memory means during an entire time of said execution of said program when said span of addresses is assigned to said overlay memory means, wherein data written to said overlay memory means is not written to said cache memory means.