Patent ID: 6593613
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A memory cell comprising:a trench formed in a substrate in a first direction, the trench having first and second sidewalls and a bottom surface along the first direction; a bitline located on the bottom surface of the trench, the bitline being commonly coupled to bitlines of other memory cells with a memory array; a vertical transistor having a gate located in the trench along the first trench sidewall, the gate being isolated from the bitline, a gate oxide between the gate and the first trench sidewall, a first diffusion coupling the bitline to the gate, a second diffusion located on a surface of the substrate adjacent to the gate; and a capacitor located above the substrate, the capacitor comprises a first electrode coupled to the second diffusion region by a contact, a second electrode, a dielectric layer separating the first and second electrodes, a plateline coupled to the second electrode, wherein data is written to or read from the memory cell through the plateline.