Patent ID: 8211755
Filing Date: 2012-07-03
Classification: H01L

Abstract:
1. A method for fabricating a memory array comprising: forming a first patterned set of parallel conductive lines over a substrate; forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein each of the semiconductor pillars comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer; depositing a dielectric between the plurality of semiconductor pillars; and plasma etching a deep via recess through the dielectric and through an underlying layer after the steps of forming the plurality of semiconductor pillars and depositing the dielectric, the deep via recess exposing a portion of the dielectric and the deep via recess being isolated from the second barrier layer during the plasma etching by the dielectric.