Patent ID: 6903414
Filing Date: 2005-06-07
Classification: H01L,Y10S

Abstract:
1. A semiconductor memory comprising: a semiconductor substrate having an active region and a device isolation layer for isolating the active region; a trench formed to cross the active region in a fixed width; wordlines formed along sides of the trench; gate insulating layers formed between the wordlines and the active region; a first impurity region formed in a bottom portion of the trench having no wordline passed therethrough; second impurity regions formed at surfaces of the semiconductor substrate adjacent to the trench; a first insulating layer formed on an entire surface having contact holes to the first and second impurity regions; a bitline formed in a direction vertical to the wordline and in contact with the first impurity region through the contact hole in the first insulating layer; a second insulating layer formed on an entire surface inclusive of the bitline; and, a storage node plug layers formed in contact with the second impurity region.