Patent ID: 8230198
Filing Date: 2012-07-24
Classification: G06F

Abstract:
1. A storage system comprising: a code delivery server (CDS) defined by a hardware controller; a main-system memory operatively coupled with said CDS and delivering via said CDS a program code including a software interrupt (SWI), in response to a CPU request for a command code, wherein said software interrupt is different than said command code, and wherein said main system memory is an asynchronous external resource; and a host-system processor coupled to said CDS, the host-system processor is operable to execute said program code stored in said main-system memory in response to receiving said software interrupt, wherein the CPU request is of said host-system processor of a host system; wherein said SWI causes said host-system processor to disable hardware interrupts, store all CPU registers and statuses, and jump to a reset-vector address.