Patent ID: 7512921
Filing Date: 2009-03-31
Classification: G06F

Abstract:
1. A layout method for a layout apparatus for laying out an integrated circuit, the method comprising: placing a plurality of cells at approximate positions according to circuit data; and placing the plurality of cells at specific positions according to a result of the placing of the plurality of cells at the approximate positions, wherein the placing of the plurality of cells at the specific positions further comprises: placing the plurality of cells at the specific positions; determining critical area values between two cells adjacent to one another in the plurality of cells, the two cells including two wires parallel and adjacent with each other, one of the two wires being included in one of the two cells and the other of the two wires being included in the other of the two cells, each of the critical area values being obtained by integrating a short area by a distribution probability density of a defect, the defect being a circle with a radius, the short area being an area gathering a point on which a center of a defect is positioned when the defect shorts or opens the two wires; and modifying the specific positions of the plurality of cells so as to reduce the critical area values determined, and wherein, in a case that the critical area values determined are reduced by replacing a position of first cell and a position of second cell with one another, the specific positions of the plurality of cells are modified by the replacing of the first cell and the second cell with one another.