Patent ID: 7542339
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus, comprising: a nonvolatile memory array; a plurality of terminals including a command terminal, a clock terminal and an other terminal; and a control circuit, wherein said command terminal is capable of receiving commands which include a read command and a write command, wherein said clock terminal is capable of receiving a clock signal, wherein said nonvolatile memory array includes a plurality of word lines each of which coupled to a plurality of nonvolatile memory cells, wherein in an operation in response to said read command received from said command terminal, said control circuit controls to selecting one word line, to supplying a read voltage to said one word line, to reading data from ones of said nonvolatile memory cells coupled to said one word line, and to outputting data via said other terminal except said command terminal in response to said clock signal, wherein in an operation in response to said write command received from said command terminal, said control circuit controls to receiving data via said other terminal except said command terminal in response to said clock signal, to selecting one word line, to supplying a program voltage to said one word line for writing data to a nonvolatile memory cell coupled to said one word line, to supplying a verify voltage to said one word line for checking whether said nonvolatile memory cell coupled to said one word line is completed writing data or not, and to repeating supplying said program voltage and supplying said verify voltage to said one word line until said nonvolatile memory cell coupled to said one word line is completed writing data, wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges, wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state, wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said one word line to within said threshold voltage range indicating said erase state in said operation in response to said erase command, and wherein said control circuit controls moving said threshold voltage of said nonvolatile memory cell coupled to said one word line to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.