Patent ID: 7855110
Filing Date: 2010-12-21
Classification: H01L

Abstract:
1. A method, comprising: (a) forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of said gate dielectric layer; (b) forming a source extension ion implanted region and a drain extension ion implanted region in said silicon region of said substrate on opposite sides of said gate electrode and forming a source ion implanted region and a drain ion implanted region in said silicon region of said substrate on opposite sides of said gate electrode, after (b), (c) performing a thermal activation anneal to form, from said ion implanted regions, a source and a drain separated by a channel region under said gate electrode, said source having a source extension extending under said gate electrode and said drain having a drain extension extending under said gate electrode, said source, source extension, drain and drain extension doped a first dopant type; after (c), (d) forming a source delta region contained entirely within said source, a region of said source extension intervening between said source delta region and said channel region and forming a drain delta region contained entirely within said drain, a region of said drain extension intervening between said drain delta region and said channel region, said delta source region and said delta drain region doped a second dopant type, said second dopant type opposite from said first dopant type; and wherein (d) includes: