Patent ID: 8351450
Filing Date: 2013-01-08
Classification: H04J,H04L

Abstract:
1. A rate adaptation device, comprising: one or more input/output (I/O) ports coupled to a first network operating at a first data transmission rate; a first physical coding sublayer (PCS) receiver to receive a stream of PCS blocks from the first network; a first-in-first-out (FIFO) memory; an idle symbol remover in the communication path between the PCS receiver and the FIFO memory and comprising a memory buffer separate from the FIFO memory to selectively remove, in response to a control signal from the FIFO memory, a sequence of idle symbols from a first PCS block and combine one or more non-idle PCS symbols from the first PCS block in the buffer with one or more non-idle PCS symbols selectively removed from a second PCS block to form a third PCS block; and a PCS transmitter coupled to the FIFO memory module to transmit the third PCS block to a second network operating at a second data transmission rate, wherein the control signal indicates whether the FIFO memory is almost full.