Patent ID: 8203868
Filing Date: 2012-06-19
Classification: G11C

Abstract:
1. A semiconductor memory device functioning as a memory cell array, said semiconductor memory device comprising: static memory cells arranged in row and column directions, each static memory cell including a plurality of transistors; a plurality of bit lines for accessing said static memory cells; a first well layer in which a plurality of first transistors of a plurality of said static memory cells are commonly formed, said first transistors being connected together to one of said plurality of bit lines and formed in the same column; and a second well layer in which a plurality of second transistors of said static memory cells of a same conductive type as said first transistors of said plurality of static memory cells are commonly formed, said second transistors being connected together to another one of said plurality of bit lines and formed in the same column, wherein potentials of said first and second well layers are adjusted to different values.