Patent ID: 7487490
Filing Date: 2009-02-03
Classification: G06F,Y02P

Abstract:
1. An integrated circuit design system having computer software for correcting integrated circuit design layouts and having correction for problematic shapes introduced by application of a previously applied layout process, the computer software comprising: code for receiving input layout data representing an integrated circuit design layout; code for determining whether a problematic shape has been created in the layout by application of a previously applied layout process selected from among the group of processes consisting of design rule check and Boolean processes or process compensation; code for applying a correction process to original unprocessed geometries, using the process geometries as a target; and code for outputting the corrected manipulated integrated circuit design layout; wherein the correction process involves a dissection step and a correction step, the dissection is performed on the original unprocessed geometries, and correction targets at the processed layout geometry boundary.