Patent ID: 8837221
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. A random-read NOR flash memory array comprising one or more memory sectors, each sector comprising N+1 word lines; K local sub-bit lines, which are perpendicular to the word-lines; K local sub-source lines, which are perpendicular to the word-lines; (K+1)/2 global bit lines, wherein every two sub-bit lines are decoded to form one of said global bit lines; (K+1)/2 global source lines, wherein every two sub-source lines are decoded to form one of said global source lines; and (N+1)/2×K flash memory cells, wherein each flash memory cell is a NAND-based N-channel 2T-string NOR flash memory cell device storing two bits, and wherein said cells can be coupled with appropriate bias condition in circuit for respective operation, comprising: