Patent ID: 7816943
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A programmable cycle state machine on an integrated circuit comprising: a first central processing unit (CPU); a memory interfaced with the CPU; a state machine; a first parallel data bus connecting the memory to the state machine; a second parallel data bus; a clock input coupled to the state machine and receiving a clock signal; a first control output coupled to an input/output device; a second control output coupled to the memory and is independent from said first control output; and a control input coupled from the memory to the state machine, wherein a value of the first control output is a function of the clock input, the current state of the state machine, and the control input; wherein a value of the first parallel data bus is being outputted on the second parallel data bus as a function of the clock input, the current state of the state machine, and the control input; wherein the second control output requests the next value for the first parallel data bus; and wherein the state machine is programmable through the control input.