Patent ID: 6929988
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A method for forming a semiconductor device with reduced Miller capacitance comprising the steps of: heavily doping a substrate with a first conductivity dopant to form a drain region; growing an epitaxial layer on the substrate and lightly doping the epitaxial layer with a dopant of the first conductivity; implanting the surface of the epitaxial layer with dopants of a second polarity opposite in polarity to the first conductivity dopant; covering the substrate with a trench mask having openings corresponding to desired trench regions and removing material from the exposed regions to form trenches; growing an oxide layer of a substantially constant thickness on the trench walls and floor and diffusing the second conductivity dopant to form well regions adjacent the trench sidewalls; forming over said oxide layer on said trench walls and floor upper and lower conductive layers respectively and separating the layers with a first dielectric layer; removing a portion of said upper conductive layer; and forming source regions on the surface of the epitaxial layer with dopant of the first conductivity.