Patent ID: 6809949
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A ferroelectric, non-volatile memory comprising: a plurality of pairs of parallel bit lines and a plurality of memory cells, each said memory cell associated with one of said pairs of bit lines, each said memory cell comprising: a first ferroelectric capacitor having a first electrode and a second electrode, a second ferroelectric capacitor having a first electrode and a second electrode, a first transistor having a gate, and a second transistor having a gate; wherein in each said memory cell said first transistor is connected between said first electrode of said first capacitor and one of said bit lines in said associated bit line pair, said second transistor is connected between said first electrode of said second capacitor and the other of said bit lines in said associated bit line pair; said memory further including a plurality of drive lines and a drive line transistor associated with each of said drive lines, said drive line transistor including a gate, said drive lines being parallel to said bit lines, each of said drive lines connected to the second electrode of at least one of said capacitors in at least one of said memory cells via said drive line transistor, each of said drive lines connected to two or less of said memory cells, said memory further including a word line perpendicular to said bit line pairs arid said drive lines, arid said gates of said first transistor, said second transistor and said drive line transistor connected to said word line, and whereineach of said drive lines is connected to said second electrode of said first capacitor and said second electrode of said second capacitor in two of said memory cells; and one of said two memory cells is a two-bit memory cell and the other of said two memory cells is a one-bit memory cell including a dummy capacitor, and said bit line connected to said dummy capacitor is a dummy bit line.