Patent ID: 6381191
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array including a plurality of memory array blocks each having a plurality of memory cells; local control circuits provided corresponding to the respective memory array blocks, each for controlling an operation related at least to an operation of memory cell selection in a corresponding memory array block when activated; control circuitry arranged in a location different from the plurality of memory array blocks of the memory array, receiving at least a main enable signal common to said plurality of memory array blocks and a block identifying signal identifying a memory array block among said plurality of memory array blocks, for generating a basic operation control signal for each respective memory array block and applying each basic operation control signal to a corresponding local control circuit to operate each local control circuit in accordance with a corresponding basic operation control signal, said basic operation control signal being activated in accordance with the block identifying signal identifying a corresponding memory array block, to activate a corresponding local control circuit.