Patent ID: 6051475
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A process for manufacturing a capacitor, comprising the sequential steps of:providing a first layer of polysilicon on a dielectric substrate;patterning the first layer of polysilicon to form a lower electrode;depositing a first layer of a silicide forming metal onto said lower electrode;subjecting said first metal and lower electrode to a first rapid thermal anneal whereby the metal and the polysilicon react to form a first silicide;removing all unreacted portions of the metal layer, resulting in a first structure;subjecting the first structure to a second rapid thermal anneal whereby the resistivity of the silicide is reduced;depositing a dielectric layer;patterning and etching said dielectric layer whereby it covers only the lower electrode;depositing a second polysilicon layer;patterning and etching the second polysilicon layer to form an upper electrode;depositing a second layer of a silicide forming metal onto said upper electrode, resulting in a second structure;subjecting said second structure to a third rapid thermal anneal whereby the second metal and all of the second polysilicon react to form a second silicide layer;removing all unreacted portions of the second metal layer, resulting in a third structure; andsubjecting the third structure to a fourth rapid thermal anneal whereby the density of the dielectric layer is increased.