Patent ID: 6184097
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit, comprising:providing a gate structure on a semiconductor substrate, the gate structure including a pair of sacrificial spacers, only one of the sacrificial spacers being on each side of the gate structure;providing a deep source region and a deep drain region, the gate structure being between the deep source region and the deep drain region, the deep source region and the deep drain region not including extensions;siliciding the deep source region, the deep drain region, and the gate structure;removing the sacrificial spacers from above a portion of the semiconductor substrate to leave a plurality of holes;forming an amorphous region through the holes within the portion of the semiconductor substrate and exclusive of the deep drain region and the deep source region, wherein the amorphous region is formed by ion implantation; andproviding dopants to the amorphous region, thereby forming the extensions to the deep source region and the deep drain region.