Patent ID: 6278148
Filing Date: 2001-08-21
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate;a dynamic memory having a memory cell array, the memory cell array including a plurality of data lines, a plurality of word lines, and a plurality of memory cells and each memory cell including a transistor formed on the semiconductor substrate and a capacitor formed over the semiconductor substrate and having an electrode connected to the transistor and a plate electrode, the plurality of data lines being formed in a first wiring layer over the semiconductor substrate, the plurality of word lines being formed in a second wiring layer and located over the capacitors of the plurality of memory cells, the memory cell array being formed in a four-sided region in a plan-view layout of said semiconductor substrate;a conductor formed in a portion of the semiconductor device located over the four-sided region, formed in a third wiring layer, and located over the first and second wiring layer; anda wiring formed in a fourth wiring layer located over the conductor;wherein the conductor is biased to a predetermined potential for supplying power to the plate electrodes and connected to the plate electrodes of the capacitors of the plurality of memory cells.