Patent ID: 7133303
Filing Date: 2006-11-07
Classification: G11C

Abstract:
1. A dynamic type semiconductor memory apparatus, comprising: a memory cell alley including a plurality of memory cells disposed repeatedly along row and column directions; a word line configured to selectively drive the memory cell alley based on a row address being input from an external unit; first and second memory cell groups determined by dividing the selectively driven memory cell alley based on a column address; a first bit line configured to transmit or receive first data to and from the first memory cell group; a second bit line configured to transmit or receive second data to and from the second memory cell group; first and second local data lines disposed along the row direction and adjoining the memory cell alley; a column selection unit configured to respectively connect the first and second bit lines to the first and second local data lines based on the column address; a first master data line disposed corresponding to the first local data line; a second master data line disposed corresponding to the second local data line; a local data line selecting unit configured to connect the first and second local data lines to the first and second master data lines, respectively; a data reading unit configured to read data from the memory cell alley by selecting the first or second master data line; and a data writing unit configured to write data being input from an external source by selecting the first or second master data line.