Patent ID: 7577821
Filing Date: 2009-08-18
Classification: G06F

Abstract:
1. An integrated circuit device comprising a data processing block including a first matrix and a second matrix, the first matrix and the second matrix respectively including a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units, a configuration of data flow with the plurality of types of operation units being changeable by changing a route of the wiring group for data supplying to the plurality of types of operation units, wherein one of the plurality of types of operation units is a delay type operation unit that include a data path suited to processing for delaying a transfer time of data, the wiring group of the first matrix and the wiring group of the second matrix are separated, and the integrated circuit device further comprises a plurality of the delay type operation units that are arranged along a boundary of the first matrix and the second matrix for connecting the wiring group of the first matrix and the wiring group of the second matrix via data paths included in the plurality of the delay type operation units.