Patent ID: 6360284
Filing Date: 2002-03-19
Classification: G06F

Abstract:
In a system including first and second modules in different power domains, each module including data and clock output pins coupled to drivers and including input pins for receiving clock and data signals, with at least a first clock output pin of each module coupled to a respective first clock receiving pin of the other module, a method, performed in said first module for protecting drivers from driving into a low-impedance powered-down module, said method comprising the steps of:transitioning to a NO_CLOCK state if no signal is received on said first clock receiving pin, with said output pins, including said first clock output pin, in a high-impedance off state; while in said NO_CLOCK state monitoring said first clock receiving pin on said first circuit for the presence of a clock signal asserted by the second module; if no clock signal is received, periodically driving a burst of clock signals on the first clock output pin of the first module to signal the second module that the first module is powered-up; if a clock signal is received on said first clock receiving pin, transitioning to a CLOCK_UP state; while in said CLOCK_UP state: driving all clock and data pins of said first module; after a predetermined delay to allow said second module to transition to its CLOCK_UP state, monitoring the first clock receive pin of said first module to detect the absence of a received clock signal; and if the absence of a clock signal on the clock receive pin of the first module is detected, transitioning to said NO_CLOCK state so that the first module transitions to the NO_CLOCK state when the absence of a received clock signal is detected.