Patent ID: 7414871
Filing Date: 2008-08-19
Classification: G11C

Abstract:
1. A program control circuit of a flash memory device including a plurality of MLCs that share word lines and bit lines, comprising: a controller that generates bit line masking signals and a step control signal in response to compare signals received from a verify data comparator, generates one of first to third cycle control signals and a first or second verify control signal based on the number of times that a step control signal is generated, outputs the bit line masking signals to a page buffer circuit connected to the bit lines, and outputs the step control signal to a word line voltage generator; a clock signal generator that generates one of first to third clock signals and one of inverted first to third clock signals in response to one of the first to third cycle control signals; and a voltage select circuit that outputs a program bias voltage, which is generated from the word line voltage generator, to a X-decoder connected to the word lines during one of first to third predetermined times or outputs a verify bias voltage, which is generated from the word line voltage generator, to the X-decoder during a fourth predetermined time, in