Patent ID: 7655977
Filing Date: 2010-02-02
Classification: H01L

Abstract:
1. An IGBT comprising a silicon die having a top surface and a bottom surface; said die having a P ++ substrate layer extending from said bottom surface, an N + buffer layer extending from the top of said substrate layer and an N − drift layer extending from the top of said buffer layer to said top surface; said top surface receiving a MOSgated structure and a top power electrode; a plurality of P ++ regions formed in said die and spaced apart; each of said P ++ regions connected to said top electrode; a P + termination region adjacent one of said P ++ regions and connected to said top electrode through said one of said P ++ regions; and an oxide body over said P + termination region and extending under a portion of said top electrode; said bottom surface receiving a bottom power elcctrode; said P ++ substrate having a resistivity less than about 10 ohm cm; said buffer layer having a resistivity in the range of 0.05 to 0.10 ohm cm, wherein said drift layer has a thickness in the range of 31 to 37 μm and a resistivity in the range of 14 to 18 ohm cm.