Patent ID: 7848164
Filing Date: 2010-12-07
Classification: G11C

Abstract:
1. A semiconductor memory device including a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats comprises: a plurality of normal memory blocks, each including a plurality of normal memory cells disposed adjacent one another; and at least one redundancy memory block having the same structure as each of the plurality of normal memory blocks, the at least one redundancy memory block being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for use in making a row and column repair, wherein in a row repair, the redundancy memory block is mapped so that a block address and a column address corresponding to the plurality of normal memory blocks become a row address of the redundancy memory block and a portion of a row address of the plurality of normal memory blocks becomes a column address.