Patent ID: 8493117
Filing Date: 2013-07-23
Classification: H03L

Abstract:
1. A leakage tolerant delay locked loop (DLL) circuit device, the DLL circuit device comprising: a primary loop configured to generate a feedback signal having a phase that is delayed relative to a reference signal, wherein the primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB), wherein the VCB is configured to generate a plurality of output phase signals and provide the feedback signal to the phase detector, wherein the phase detector is configured to generate and provide to the error controller, one of a first error-delay-increase signal and a first error-delay-decrease signal; and a secondary correction circuit configured to generate and provide secondary error-delay signals to the error controller, wherein the secondary correction circuit includes multiple error generators, wherein each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB, wherein the primary loop is configured to control a phase adjustment provided by the VCB to each of the output phase signals and the feedback signal, wherein the primary loop is configured to control the phase adjustment based on at least one of the first error-delay-increase signal, the first error-delay-decrease signal, and the secondary error-delay signals.