Patent ID: 6560144
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including memory cells arranged in rows and columns, each memory cell including a transistor having first and second terminals and a gate; a plurality of word lines each connecting the transistor gates of the memory cells in a respective corresponding row of said memory cell array; a plurality of bit lines each connecting the first terminals of the transistors of the memory cells in a respective corresponding column of said memory cell array; and a voltage supply circuit having a plurality of output terminals and generating a supply voltage to the plurality of word lines in accordance with a decode signal, wherein the voltage supply circuit comprises; a first level conversion circuit for receiving the decode signal, and outputting a first signal based on respective levels of a first logic high voltage and a first logic low level voltage supplied thereto; and a second level conversion circuit receiving the first signal, and outputting a second signal based on respective levels of a first voltage as a second logic high level voltage, and a second voltage as a second logic low level voltage supplied thereto, the first voltage having a positive value and the second voltage having a negative value.