Patent ID: 6157060
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A highly integrated semiconductor memory, comprising:an n-channel-EPROM cell in the form of a pillar having side walls and a base;an n.sup.+ -doped source region extending along said base of said pillar, and an n.sup.+ -doped drain region disposed on said pillar;said pillar having lateral dimensions chosen such that said pillar, in a potential-free state of the n-channel-EPROM cell, is fully depleted of free charge carriers;an n.sup.+ -doped floating gate disposed on said side walls of said pillar and enclosing said pillar;a control gate formed of p.sup.+ -doped semiconductor material, said control gate enclosing said pillar and said floating gate and being partly disposed on said side walls of said pillar; andan intermediate insulator layer between said control gate and said pillar.