Patent ID: 6433606
Filing Date: 2002-08-13
Classification: G06F,H03K

Abstract:
A clock driver circuit formed on a single semiconductor chip, the clock driver circuit comprising:an input terminal receiving a single-phase clock signal; an initial-stage clock driver circuit electrically connected to said input terminal for converting the single-phase clock signal to a positive-phase clock signal and an anti-phase clock signal; an intermediate clock driver circuit for relaying the positive-phase and anti-phase clock signals output from said initial-stage clock driver circuit; a final-stage clock driver circuit for converting the positive-phase and anti-phase clock signals received from said intermediate clock driver circuit to a single-phase clock signal; and a pair of first interconnect lines connected between said initial-stage clock driver circuit and said final-stage clock driver circuit through said intermediate clock driver circuit, one of the first interconnect lines transmitting the positive-phase clock signal, the other first interconnect line transmitting the anti-phase clock signal, said interconnect lines being placed as adjacent to each other.