Patent ID: 6809966
Filing Date: 2004-10-26
Classification: G11C,H01L

Abstract:
A method of preventing disturbance of a non-volatile semiconductor memory comprising:providing a non-volatile semiconductor memory device comprising a plurality of memory cells each of which comprises a control gate, a drain junction, a source junction, a floating gate, a word line, and a bit line; generating a first electric charge of a first parasitic capacitance from an applied control gate voltage and a floating gate voltage as a function of the first parasitic capacitance with respect to the difference between the control gate voltage and the floating gate voltage; generating a third electric charge of a third parasitic capacitance from a source voltage at the source junction and the induced floating gate voltage as a function of the third parasitic capacitance with respect to the difference between the source voltage and the floating gate voltage; generating a fourth electric charge of a fourth parasitic capacitance from a bulk substrate voltage and the induced floating gate voltage as a function of the fourth parasitic capacitance with respect to the difference between the bulk substrate voltage and the floating gate voltage; generating a second electric charge of a second parasitic capacitance from a drain voltage at the drain junction and the induced floating gate voltage as a function of the second parasitic capacitance with respect to the difference between the drain voltage and the floating gate voltage; selecting one of the control gate voltage and the drain voltage to reduce disturbance at the word line and the bit line where the floating gate voltage is determined by the capacitance of the first and second parasitic capacitors, the control gate voltage, the drain voltage and the total parasitic capacitance; and programming said non-volatile semiconductor memory by F-N tunneling or erasing by discharging electrons.