Patent ID: 6734816
Filing Date: 2004-05-11
Classification: H03M

Abstract:
A D/A converter comprising:input means for inputting a 1-bit signal and a clock signal; first delay means for delaying the 1-bit signal supplied from said input means; inverting means for inverting the clock signal supplied from said input means; first potential generating means for receiving the 1-bit signal and the clock signal supplied from said input means, for generating, when the clock signal is at a first level, one of a first reference potential and a second reference potential in response to the signal level of the 1-bit signal, and for generating, when the clock signal is at a second level, an intermediate potential between the first reference potential and the second reference potential; second potential generating means for receiving the 1-bit signal supplied from said input means and the clock signal inverted by said inverting means, for generating, when the inverted clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the 1-bit signal, and for generating, when the inverted clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential; third potential generating means for receiving the 1-bit signal delayed by said first delay means and the clock signal supplied from said input means, for generating, when the clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the delayed 1-bit signal, and for generating, when the clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential; fourth potential generating means for receiving the 1-bit signal delayed by said first delay means and the clock signal inverted by said inverting means, for generating, when the inverted clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the delayed 1-bit signal, and for generating, when the inverted clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential; and combining means for combining the potentials output from said first to fourth potential generating means.