Patent ID: 6574156
Filing Date: 2003-06-03
Classification: G11C

Abstract:
A portion of a memory for a semiconductor die having a memory comprising:a first sub-array of a portion of a memory for a semiconductor die and a second sub-array of a portion of the memory for the semiconductor die; and circuitry coupled to the first sub-array of memory and second sub-array of memory used to store row addresses of defective rows in the first sub-array of memory and second sub-array of memory and activate a redundant row in one sub-array of the first sub-array of memory and second sub-array of memory when receiving a row address matching one of the stored row addresses of defective rows while disabling a redundant row arranged in the other sub-array of the first sub-array of memory and second sub-array of memory in an order complementary to that of the activated redundant row, the circuitry comprising: a plurality of fuse banks to store the row addresses of defective rows and output a match signal in response to receiving the row address matching the one of the stored row addresses of defective rows; at least a first row decoder and at least a second row decoder connected to the respective first sub-array of memory and second sub-array of memory to activate redundant rows in the one sub-array of the first sub-array of memory and second sub-array of memory in response to receiving the match signal; and a plurality of enable fuses connected between the plurality of fuse banks and the at least a first row decoder and the at least a second row decoder to conduct the match signal to the at least a first row decoder and isolate the match signal from the at least a second row decoder to disable activation of the redundant row in the other sub-array of the first sub-array of memory and second sub-array of memory.