Patent ID: 7371642
Filing Date: 2008-05-13
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a split-channel transistor, the method comprising: incising a substrate to form a plurality of trenches, each pair of trenches defining a pillar; forming a diffusion region in an upper portion of each pillar; forming a lower diffusion region under each trench; forming a nitride storage region only on each facing side of adjacent pillars; forming an oxide dielectric on the pillars and in the trenches, under the nitride storage regions, such that an oxide dielectric, without a nitride layer, is formed on top of each pillar and on the bottom of each trench; and forming a single control gate overlying the pillars and in the plurality of trenches wherein during a programming operation of the transistor, a channel is adapted to form along the facing sides of adjacent pillars and are connected by the lower diffusion region, the lower diffusion region not being coupled to an electrical contact.