Patent ID: 6245613
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A process for forming a field effect transistor wherein said field effect transistor comprises:a semiconductor substrate comprising a first doped source region asnd a second doped drain region separated by a channel region;a conductive floating gate formed over a first portion of said channel region adjacent to said first doped source region, and recessed into said semiconductor substrate and being separated from said first portion of said channel region by a first insulation layer;and a conductive control gate formed substantially over but electrically isolated from said floating gate and formed over the entire channel region including those portions not beneath said floating gate, and wherein said floating gate has pointy edges which point towards said control gate; and wherein said process comprises:forming recess in a semiconductor substrate;forming a layer of isolation in said recess;depositing and planarizing a layer of doped polysilicon in said recessed area;oxidizing the top portion of said polysilicon and leaving a bottom portion unoxidized;defining active areas and providing shallow trench isolation;providing gate oxide layer on said substrate and above the floating gate;depositing and defining control gate and providing source and drain regions.