Patent ID: 7508700
Filing Date: 2009-03-24
Classification: H01L,Y10S

Abstract:
1. A MTJ pattern layout in a memory device, comprising: (a) a plurality of chips formed on a substrate wherein each chip has a plurality of active MTJ device blocks arranged in a certain array; (b) a first CMP assist feature formed around each active MTJ block and comprised of two dummy bands made of dummy MTJ devices with an MTJ ILD layer formed between adjacent dummy MTJ devices, and wherein an inner dummy band is separated from an outer dummy band by a dielectric spacer layer having no MTJ devices; and (c) an array of second CMP assist features formed outside said outer dummy band wherein a second CMP assist feature is comprised of a plurality of dummy MTJ devices formed within a contact pad and said contact pad is separated from the outer dummy band by a certain distance.