Patent ID: 6587905
Filing Date: 2003-07-01
Classification: G06F

Abstract:
A data bus system comprising:a first read data bus coupled to a plurality of slave devices; a second read data bus coupled to said plurality of slave devices; a first write data bus coupled to said plurality of slave devices; a plurality of master devices, said master devices operable to receive read data; send write data and receive read and write data acknowledge signals; a first read data acknowledge bus; a first write data acknowledge bus; and a bus arbiter, coupled to said plurality of master devices and said first and second read data bus, said first write data bus, said first read data acknowledge bus and said first write data acknowledge bus, said bus arbiter operable to monitor bus utilization of said first read data bus and said first write data bus, said bus arbiter granting bus access selectively to said master devices based on bus access priorities, said bus arbiter further asserting an auxiliary read signal in response to said bus utilization and bus access priorities; said bus arbiter simultaneously coupling data from a first slave device on said first read data bus and a second slave device on said second read data bus when said auxiliary read signal is asserted, wherein an acknowledge is asserted, from said second slave device using said second read-data bus, as a write data acknowledge and routed by said bus arbiter to a corresponding read data acknowledge of a master device receiving data from said second read data bus, said data from said second read data bus routed by said bus arbiter to a normal read input of said master device, wherein a bandwidth of a read operation is increased during unbalanced utilization of said first read data bus and said first write data bus.