Patent ID: 8059471
Filing Date: 2011-11-15
Classification: G11C

Abstract:
1. A nonvolatile DRAM device comprising: at least one array of non-volatile DRAM memory cells where the non-volatile DRAM memory cells are arranged in rows and columns in the at least one array, each non-volatile DRAM memory cell comprising: a plurality of complementary pairs of bit lines, each bit line connected to a drain of the floating gate pass transistor of each of the non-volatile DRAM cells of a column of the non-volatile DRAM cells; a plurality of word lines, each word line is connected to the control gate of the floating gate pass transistor of each of the non-volatile DRAM cells of each of the rows of the non-volatile DRAM cells; a row tag register in communication with the rows of the non-volatile DRAM memory cells comprising tag bits for identifying which of the rows have new data written to the capacitor; and a plurality sense amplifiers, each sense amplifier connected to one pair of complementary bit lines thus to two columns of the non-volatile DRAM memory cells for reading permanent data from the floating gate of the pass transistor of a selected non-volatile DRAM memory cell and volatile data from the cell capacitor of the non-volatile DRAM memory cells of a selected cell.