Patent ID: 7085949
Filing Date: 2006-08-01
Classification: H03L,H04L

Abstract:
1. A method for locking phase by providing a clock synchronized with an input signal, the input signal comprising a plurality of data, the method comprising: generating an estimated rate according to transitions of the input signal; processing a dithering step for updating the estimated rate by multiplying the estimated rate by a predetermined ratio; adjusting a frequency of the clock synchronized with an input signal according to the updated estimated rate in the dithering step to make the frequency of the clock correspond to the updated estimated rate; and modifying the predetermined ratio so that another dithering step may apply the modified predetermined ratio to update the estimated rate; wherein before adjusting the frequency of the clock according to the updated estimate rate in the dithering step, if a phase difference or frequency difference between the clock and the input signal exceeds a predetermined value, the frequency of the clock is adjusted according to the updated estimated rate in the dithering step.