Patent ID: 6201451
Filing Date: 2001-03-13
Classification: H04L

Abstract:
An MSK modulator comprising:a digital signal generator which generates a first digital signal corresponding to a first analog signal representing a logic value of bits of a to-be modulated digital signal in accordance with a .pi./2 radian-phase delay or advance of a carrier wave at a predetermined time, and a second digital signal corresponding to a second analog signal which is substantially about .pi./2 radians out of phase with respect to said first analog signal;a digital-to-analog converter which obtains said first and second digital signals from said digital signal generator and converts each of the first and second digital signals into first and second analog signals respectively; andan orthogonal modulator which obtains said first and second analog signals from said digital-to-analog converter, and generates an MSK (Minimum Shift Keying) modulation signal representing a sum or difference of a product of instantaneous values of said carrier wave and said first analog signal and a product of instantaneous values of said second analog signal and a signal whose phase substantially shifts about .pi./2 radians;wherein the digital signal generator further comprises:a bidirectional shift register which stores predetermined data having continuous plural bits arranged in an annulus wherein a continuous half of all of the bits of the predetermined data substantially have a logic value respectively identical with one another, and remaining bits of the predetermined data other than the continuous half of all of the bits have a logic value distinct from said logic value of the continuous half of all of the bits, and obtains said bits of the to-be-modulated digital signal so as to allow the logic values of the bits in the predetermined data to shift in a predetermined direction inherent in said logic values of said bits of the to-be-modulated digital signal; andan extraction circuit which obtains from the bidirectional shift register a value represented by first partial data substantially including the continuous half of all of the bits of said predetermined data, supplies the obtained value as a first digital signal to said digital-to-analog converter, obtains from said bidirectional shift register a value represented by second partial data which substantially includes the continuous half of all of the bits of the predetermined data and in which the continuous half of bits of the second partial data overlap with said first partial data, and supplies the obtained value as a second digital signal to said digital-to-analog converter.