Patent ID: 6393542
Filing Date: 2002-05-21
Classification: G06F

Abstract:
An electronic circuit system comprising:a semiconductor memory device that operates on the basis of a clock; and an interface circuit that permits read and write operations for data with respect to said: memory device under a control operation of said CPU, wherein said interface circuit comprises: a read data storage unit that stores read data from said semiconductor memory device; a write data storage unit that stores write data to be written in said semiconductor memo device; and an operation speed setting unit that sets a reading speed and a writing speed to predetermined speeds under the control operation of said CPU, wherein said CPU compares the read data in said read data storage unit and the write data in said write data storage unit and controls delay timing based on this comparison, wherein said CPU executes a first operation and a second operation, the first operation is to execute the read operation for a first address of said: memory device in a high reading speed set by said operation speed setting unit after executing the write operation for said first address in a low writing speed set by said operation speed setting unit, and the second operation is to execute the read operation or a second address of said: memory device in a low reading speed set by said operation speed setting unit after executing the write operation for said second address in a high writing speed set by said operation speed setting unit, said high reading speed being higher than said low speed, said high writing speed being higher than said low writing speed.