Patent ID: 7842578
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit device, the method comprising: providing a semiconductor substrate, the substrate comprising a first device region and a second device region, the first device region having a digital processing circuit and the second device region having an analog processing circuit; forming a trench isolation structure between the first device region and the second device region; forming a gate polysilicon layer overlying the first device region and the second device region; forming a silicide layer overlying the gate polysilicon layer; patterning the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region; forming a first sidewall spacer structure on the first silicided gate structure and a second sidewall spacer structure on the second silicided gate structure; forming a blocking layer overlying the second silicided gate structure and exposed portion of the second device region; forming a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure; performing a single annealing process to form an alloy material from at least the silicide material and the first silicided gate structure; maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer; and stripping the oxide blocking layer to expose the second source region and the second drain region.