Patent ID: 9184247
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A power semiconductor device comprising: a first conductive type drift layer that includes one surface and the other surface, and is divided into an active region, a connection region, and a termination region; a second conductive type semiconductor substrate that is formed on the other surface of the first conductive type drift layer; a second conductive type well layer that is formed with a predetermined depth in a thickness direction from the one surface of the first conductive type drift layer, and formed in the active region; a second conductive type first junction termination extension (JTE) layer that is formed to be in contact with one side of the second conductive type well layer; a second conductive type second JTE layer that is formed to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate; a first insulating layer that is formed to be in contact over an area from an upper portion of the second conductive type first JTE layer to an upper portion of the second conductive type second JTE layer; a poly silicon layer that is formed above the second conductive type well layer and an upper portion of the second conductive type first JTE layer and is formed to be in contact with an arbitrary area among a side surface and an upper surface of the first insulating layer; a trench that is formed to pass through the second conductive type well layer in a thickness direction from one surface of the first conductive type drift layer while including the second conductive type well layer; and a second insulating layer that is formed on the second conductive type well layer on an inner side surface of the trench and the second conductive type first JTE layer while including an inner side surface of the trench, wherein the second conductive type second JTE layer is formed longer than the second conductive type first JTE layer in the length direction of the substrate.