Patent ID: 7858472
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A non-volatile memory formed on an integrated circuit substrate, comprising: an array of memory cells formed in a first region of the substrate, circuits peripheral to the memory cell array including decoders, drivers and sense amplifiers that are formed in a second region of the substrate that does not overlap the first region, and a trench formed in the substrate between the first and second regions, the trench being at least 3000 Angstroms in depth and filled with a dielectric material, thereby to isolate the memory cell array and peripheral circuits, wherein the memory cell array comprises: a plurality of charge storage elements across a surface of the integrated circuit substrate, an individual charge storage element including a first portion having a first dimension in a first direction and a second portion having a second dimension in the first direction that is greater than the first dimension, the first portion located between the second portion and the surface of the integrated circuit substrate, the first portion and second portion joined along a plane; a plurality of slots between the second portions in the first direction, an individual slot extending below the plane to a level that is closer to the surface of the integrated circuit substrate than the plane is to the surface of the integrated circuit substrate; field dielectric material positioned between the charge storage elements in at least one direction across the array; and a plurality of control gates in the form of elongated conductive elements extending in the first direction, an elongated conductive element extending across a plurality of charge storage elements with a layer of dielectric positioned therebetween, and protrusions of the elongated conductive element extending into the plurality of slots, the protrusions providing electrical shielding between adjacent charge storage elements in said at least one direction.