Patent ID: 6438739
Filing Date: 2002-08-20
Classification: G06F

Abstract:
A high-level synthesis device for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, comprising:a process extraction section for extracting an available process from all processes described in the behavioral description in accordance with the behavioral description including a description of synchronous communications between plural asynchronous processes, the available process being a process for performing data communications through a path having no loop; a circuit synthesis section for producing partial circuits which realize respective available processes and for connecting the partial circuits with each other, in accordance with the inputted behavioral description, so as to synthesize the specific circuit; and a delay insertion section for inserting a delay circuit into a path that connects partial circuits with each other so that data communications between the partial circuits through a plurality of paths are synchronized with each other, wherein the behavioral description includes, as the description of the synchronous communications, codes which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, said process extraction section includes a data transfer graph generation section for recognizing the codes in the inputted behavioral description, and generating a data transfer graph composed of nodes which represent respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation, and said process extraction section further includes: an order assignment section for assigning order to processes on a path through which data communications are performed, by a breadth first search starting with one of the nodes; and an unavailable process search section for judging as to whether the end node is earlier in order than the starting node with regard to each directed edge described in the behavioral description, deciding that all nodes on a path passing through both of said nodes indicate unavailable processes when the end node is earlier in order than the starting node, and removing all of the nodes on said path.