Patent ID: 7080188
Filing Date: 2006-07-18
Classification: G06F

Abstract:
1. A system for an embedded disk controller, comprising: a first main processor operationally coupled to a first bus; a second processor operationally coupled to a second bus; a bridge that interfaces between the first bus and the second bus; an external bus controller (“EBC”) coupled to the first bus and operationally coupled to external devices via an external bus interface, wherein the EBC includes at least a segment descriptor register and a device range register, wherein the segment descriptor register allows embedded disk controller firmware to program timing characteristics of the external devices and the device range register enables the first main processor to access an address space in the external devices; and a history module for recording transaction information on the first bus and/or the second bus, wherein the history module includes a register map used for setting up the history module for recording transaction information on the first bus and/or the second bus, wherein the register map includes a register that stores a break point condition value, which is set by the first main processor and based on the break point condition value, the history module stops recording transaction information; stores a trigger mode field value, which when set allows the history module to continue recording a certain number of entries after a break point condition is reached; stores a read mask field value and a write mask field value, wherein if the read mask field value and the write mask field value are set then the history module stops recording read and/or write operations on the first and/or the second bus; and the register stores a masking field value so that the history module can exclude transactions involving components coupled to the first bus and/or the second bus.