Patent ID: 6301162
Filing Date: 2001-10-09
Classification: B82Y,G11C,H01L,Y10S

Abstract:
A memory integrated circuit comprising:row and column driving and addressing circuitry;a first memory array including a first plurality of memory cells formed from p-type silicon and arranged in rows and columns, the first plurality of memory cells having a first latency, the first memory array coupled to the driving circuitry and the addressing circuitry; anda second memory array including a second plurality of memory cells formed from p-type silicon and arranged in rows and columns, the second plurality of memory cells having a second latency greater than the first latency, the second memory array coupled to the driving and the addressing circuitry,wherein the memory cells in the first and second pluralities of memory cells each include a MOSFET comprising:a source coupled to a first end of a channel of semiconductor material;a drain coupled to a second end of the channel;a gate formed on a gate insulator on the channel, the gate and the gate insulator extending from the source to the drain; andone or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator formed in a pore extending into the channel.