Patent ID: 6981162
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. A computer system with a STR (suspend-to-RAM) state, comprising at least: a RAM (random access memory) controller with a controlling pin, the RAM controller being controlled by the computer system for generating a controlling signal, and wherein the controlling signal is for driving the computer system to the STR state; a logic circuit having an input pin connected to the controlling pin and a plurality of output pins, the output pins outputting at least one STR signal when the input pin is triggered by the controlling signal, the logic circuit including a plurality of serially connected logic elements, the input pin being an input of a first of the plurality of logic elements and the output pins being respective outputs of the plurality of logic elements; and at least one memory module, each of the memory modules having a first enable pin and a second enable pin for receiving the STR signals corresponding to the memory module, and wherein the memory module enters to the STR state when the first enable pin and the second enable pin are triggered by the STR signals.