Patent ID: 6127268
Filing Date: 2000-10-03
Classification: G01N,H01L

Abstract:
A process for fabricating a semiconductor device with a patterned metal layer, said process comprising the steps of:applying a layer (7) of material to an area of the surface of a semiconductor substrate;forming pattern lines (8) of material on the layer (7), the pattern lines (8) separated by a distance a, wherein the distance a <10 .mu.m;forming a noble metal layer (9) to a thickness d on the semiconductor substrate, wherein a/d>5, the layer (7) of material having substantially no propensity for adhering to the noble metal layer (9), the pattern lines (8) having a substantial propensity for adhering to the noble metal layer (9); andselectively removing the noble metal layer (9) outside the pattern lines (8) using ultrasoundwherein the ratio of the distance a between the pattern lines (8) to the thickness d of the noble metal layer (9), and the propensity of the pattern lines (8) for adhering to the noble metal layer (9), causes the noble metal layer (9) to adhere only to the pattern lines (8) and to the area of the layer (7) between the pattern lines (8).