Patent ID: 7779198
Filing Date: 2010-08-17
Classification: G06F,G11C

Abstract:
1. Apparatus for addressing a plurality of addressable memory banks of a computer system, each memory bank having a unique bank address and H address logic states, where H is an integer greater than 1, the apparatus comprising a bank select device for choosing bank selects for addressing the memory banks in an offset interleaved pattern, the bank select device comprising: a plurality of addressable locations, and a plurality of storage locations, each storage location being correlated to a respective one or more of the plurality of addressable locations and each addressable location being correlated to one of the plurality of storage locations, each storage location containing a respective bank select for addressing a respective one of the addressable memory banks, there being at least as many storage locations as there are addressable memory banks, the addressable locations and storage locations being arranged into a plurality of executable interleave patterns such that, for each interleave pattern, the bank select device being responsive to an input address to an addressable location to choose the bank select from the correlated storage location, such that successive input addresses to successive addressable locations during execution of a respective interleave pattern choose successive bank selects, the plurality of interleave patterns being offset so that bank selects are chosen to address a different set of Q memory banks during execution of different ones of the plurality of interleave patterns and execution of a complete rotation of the plurality of interleave patterns addresses all of the plurality of memory banks.