Patent ID: 8923051
Filing Date: 2014-12-30
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle, wherein a plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal, and wherein the reset signal generator comprises: an output pulse signal output unit configured to output an output pulse signal which pulses to a high level when any one of the first and second programming setup pulse signals pulses to a high level; a section control signal output unit configured to output a section control signal which is activated when the output pulse signal is activated and deactivated when the control pulse signal is activated; and a reset signal output unit configured to logically combine the first plane selection signal and the section control signal to output as the first reset signal and logically combine the second plane selection signal and the section control signal to output as the second reset signal.