Patent ID: 6775718
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A direct memory access control system for synchronous memory and input/output memory connected via a bus, comprising:a direct memory access controller for issuing a flyby transfer command ordering transfer of data via said bus between said synchronous memory and input/output memory; a memory interface for receiving said flyby transfer command and supplying a first access command to said synchronous memory; and an input/output interface for receiving said flyby transfer command and supplying a second access command to said input/output memory; wherein said input/output interface supplies a first status signal to said memory interface, said first status indicating a writable timing of said input/output memory during a first flyby transfer from said synchronous memory to said input/output memory and indicating a read data effective timing of said input/output memory during a second flyby transfer from said input/output memory to said synchronous memory; wherein said memory interface supplies a second status signal to said input/output interface, said second status signal indicating a read data effective timing of said synchronous memory during said first flyby transfer and indicating a writable timing of said synchronous memory during said second flyby transfer; and wherein until whichever timing is later of said respective timings according to said first and second status signals, said input/output interface and said memory interface maintain the writable state and the read data effective state respectively during said first flyby transfer and maintain the read data effective state and the writable state respectively during said second flyby transfer.