Patent ID: 6462366
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A ferroelectric memory transistor comprising:a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure formed of PSG having an opening having a width of L1 located about said gate region, wherein said source and drain regions are disposed outside said FE gate surround structure; lightly doped source and drain regions disposed along the upper surface of said substrate beneath said FE gate stack surround structure between said gate region and said source and drain regions, said lightly doped source and drain regions including phosphorus diffused into the silicon substrate from the PSG of the FE gate stack surround structure; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2&gE;L1+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process; a first insulating layer formed over the FE gate stack and the substrate; and a source electrode electrically connected to said source region; a gate electrode electrically connected to said FE gate stack; and a drain electrode electrically connected to said drain region.