Patent ID: 6178216
Filing Date: 2001-01-23
Classification: H04J,H04L

Abstract:
A digital PLL circuit, comprising:an acquisitor, for generating a reset signal, in response to an internal reference clock signal and to an act mode signal, for synchronizing with an external system;a phase detector, operative to be reset by the reset signal, for comparing the phase of the internal reference clock signal with that of a first clock signal, and for generating and outputting first and second window signals;a frequency synthesizer for generating a corrected clock signal by changing the division ratio of a system clock signal according to the first or the second window signal, said corrected clock signal output as a locked clock signal;an impulse noise remover for removing an impulse noise component from an external reference clock signal and for outputting said internal reference clock signal having had noise removed therefrom, to said acquisitor and said phase detector; anda divider, resetable by the reset signal for dividing the locked clock signal and supplying a plurality of divided clock signals, including the first clock signal to the phase detector.