Patent ID: 8984356
Filing Date: 2015-03-17
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead; B. logic circuitry having stimulus data inputs and response data outputs; C. first scan circuitry coupled to the logic circuitry stimulus data inputs and response data outputs and to the test data in lead, and having a first serial data output; D. second scan circuitry coupled to the logic circuitry stimulus data inputs and response data outputs and to the test data in lead, and having a second serial data output; E. controller circuitry having inputs coupled to the test clock lead and to the test mode select lead, and having state outputs indicating states that include a register clock state, a register capture state, and a register update state; F. register circuitry having an input coupled to the test data in lead, control inputs coupled to the state outputs of the controller circuitry, an output coupled to the test data out lead, and a control output; and G. connection circuitry having a control input connected to the control output of the register circuitry and being coupled to the first serial data output and to the second serial data output, the connection circuitry selectively coupling one of the first serial data output and the second serial data output to the test data out lead.