Patent ID: 6710391
Filing Date: 2004-03-23
Classification: H01L

Abstract:
An embedded DRAM memory cell, comprising:an access transistor, the access transistor comprising: a source and a drain within a substrate, and having a channel region therebetween; and a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell; the access transistor covered by a first insulating layer; a bit line contact pillar extending through the first insulating layer and contacting the drain of the access transistor, the bit line contact pillar composed of a contact conductive material; a three dimensional capacitor structure comprising: a storage plate comprising a storage contact pillar residing within a trench formed in the first insulating layer, and coupled to the source of the access transistor, and laterally spaced away from a side wall of the trench; and a capacitor dielectric layer overlaying the trench and the storage contact pillar within the trench; and a ground plate overlying the capacitor dielectric layer; a second insulating layer overlying the access transistor, and having a first opening overlying the bit line contact pillar and a second opening overlying the trench; and a conductive material within the first and second openings, respectively, wherein the conductive material within the first opening comprises a bit line contact and the conductive material within the second opening comprises the ground plate of the three dimensional capacitor structure.