Patent ID: 8143089
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method for manufacturing a memory device, comprising: providing a substrate body having contact plugs, the substrate body having a top surface; prior to forming a via, depositing a first electrode layer over the substrate body, the first electrode layer having a top surface; forming first and second dielectric layers on the substantially planar surface of the electrode layer, the second dielectric layer overlying the first dielectric layer; forming the via at a selected section in which the via extends through the first and second dielectric layers to produce first and second segments in the first and second dielectric layers, the first segment of the second dielectric layer overhanging the first segment of the first dielectric layer, the second segment of the second dielectric layer overhanging the second segment of the first dielectric layer, forming a pore in the via exposing the first electrode layer, by forming a sidewall structure within the via, the sidewall structure comprising a low conductivity material; depositing a programmable resistive memory material into the pore and contacting the first electrode layer; forming a second electrode layer over the programmable resistive memory material within the via, and on sidewalls of the via and patterning the second electrode layer to define a top electrode member in alignment with the via; and using the top electrode member as a mask, etching the first and second dielectric layers, and the first electrode layer to define a bottom electrode member aligned with the top electrode member.