Patent ID: 8063438
Filing Date: 2011-11-22
Classification: H01L

Abstract:
1. A vertical-type non-volatile memory device, comprising: an insulation layer pattern provided on a substrate, the insulation layer pattern having a linear shape that extends in a first direction on the substrate; single-crystalline semiconductor patterns provided on the substrate to make contact with a first sidewall and a second sidewall opposite to the first sidewall of the insulation layer pattern, each of the single-crystalline semiconductor patterns being separated by the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate; a tunnel oxide layer making contact with at least a portion of a sidewall of the single-crystalline semiconductor patterns, the contact portions of the tunnel oxide layer being spaced apart from one another in the vertical direction by a predetermined distance; a charge-trapping layer and a blocking dielectric layer provided on the tunnel oxide layer; control gate patterns provided on the blocking dielectric layer to face the sidewall of the single-crystalline semiconductor patterns, the control gate patterns having a linear shape, wherein a plurality of the control gate patterns are spaced apart from one another by a predetermined distance and are stacked in a multilayered structure; and a plurality of the insulation interlayer patterns provided in a gap between upper and lower layers of the control gate patterns, making contact with the sidewall of the single-crystalline semiconductor patterns, wherein the tunnel oxide layer is conformally formed on the profile of the sidewall of the single-crystalline semiconductor patterns, and upper and bottom surfaces of the insulation interlayer patterns.