Patent ID: 7230295
Filing Date: 2007-06-12
Classification: G11C,H01L

Abstract:
1. An integrated circuit comprising a nonvolatile memory cell, the integrated circuit comprising: a semiconductor substrate; a first dielectric region on the semiconductor substrate; a first conductive gate on the first dielectric region, the first conductive gate being part of the memory cell; at least two second dielectric regions on the semiconductor substrate; at least two conductive floating gates on the respective two second dielectric regions, the floating gates being part of the memory cell, the two floating gates being adjacent to respective two sidewalls of the first conductive gate; a dielectric layer comprising at least two continuous features, each feature overlying a respective one of the floating gates and also overlaying a respective one of the sidewalls of the first conductive gate; at least two second conductive gates, each second conductive gate overlying a respective one of the floating gates and a respective one of the continuous features of the dielectric layer, the respective continuous feature of the dielectric layer also separating the second conductive gate from the first conductive gate, the second conductive gates being part of the memory cell; wherein the memory cell is one of a plurality of memory cells; wherein the semiconductor substrate comprises a plurality of substrate isolation regions between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate; wherein each memory cell comprises a first dielectric region on an active area of the semiconductor substrate; wherein the first conductive gate is part of a conductive line G wherein each memory cell comprises two second dielectric regions on the semiconductor substrate, and a conductive floating gate on each of the two second dielectric regions; wherein each said continuous feature of the dielectric layer overlies one of the floating gates of the memory cells; wherein the integrated circuit comprises two conductive lines G