Patent ID: 6996700
Filing Date: 2006-02-07
Classification: G06F

Abstract:
1. A CPU comprising: an instruction register coupled to a memory; a plurality of general purpose registers, including a first register, a second register and a third register, and a program counter which has an address of instruction to be fetched from the memory to the instruction register, wherein the memory stores a plurality of instructions to be processed by said CPU, the instructions including a conditional branch instruction, an unconditional branch instruction and an add instruction, the add instruction for executing to add contents of the first register to contents of the second register and to place results of the addition in the third register. wherein the instruction register receives an arbitrary one of the conditional branch instruction, the unconditional branch instruction, the add instruction or other instructions from the memory, wherein an instruction bit length of the conditional branch instruction is the same as those of the unconditional branch instruction and the add instruction, and wherein a bit length of a displacement of the conditional branch instruction is different from a bit length of a displacement length of the unconditional branch instruction, and wherein a value of the displacement is added to the address of the program counter, and a result of the addition is stored in the program counter.