Patent ID: 6236081
Filing Date: 2001-05-22
Classification: H01L

Abstract:
An AND-type non-volatile semiconductor memory device, comprising:a plurality of memory cells formed on a main surface of a semiconductor substrate;a first floating gate of each of said memory cells formed on said main surface with a first insulating film of uniform thickness therebetween;an interlayer insulating film having a flat top surface and formed on said main surface by Chemical Vapor Deposition method to cover a side surface of said first floating gate;a second floating gate of each of said memory cells extending on said first floating gate and on said interlayer insulating film;a control gate of each of said memory cells formed on said second floating gate with a second insulating film therebetween;a memory cell array region where said memory cells are formed; anda peripheral circuit region in which a peripheral circuit controlling operation of said memory cells is formed, width of a boundary region located near a boundary between said memory cell array region and said peripheral circuit region being 1 to 1.5 times the distance between said first floating gates of said memory cells aligned in the direction in which said control gate extends.