Patent ID: 7283407
Filing Date: 2007-10-16
Classification: G11C

Abstract:
1. A semiconductor memory device having a memory cell array in which a plurality of memory cells having variable resistive elements which store information by a change of electric resistance are arranged in a row direction and a column direction, a plurality of row selection lines extended in the row direction and a plurality of column selection lines extended in the column direction are provided, each of the memory cells in the same row has one end of the variable resistive element connected to the same row selection line, and each of the memory cells in the same column has the other end of the variable resistive element connected to the same column selection line, comprising: a column readout voltage supply circuit coupled to each column selection line, which supplies a predetermined first voltage to a selected column selection line when readout is selected and supplies a predetermined second voltage which is different from the first voltage to a non-selected column selection line when the readout is not selected; a row readout voltage supply circuit coupled to each row selection line, which supplies the second voltage to each row selection line at the time of readout; a sense circuit which detects a current flowing in a selected row selection line separately from a current flowing in a non-selected row selection line to detect an electric resistance state of the selected memory cell at the time of readout; and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout, wherein the column readout voltage supply circuit supplies the second voltage to each of the non-selected column selection lines through the column voltage displacement prevention circuit at the time of readout.