Patent ID: 6122683
Filing Date: 2000-09-19
Classification: G06F

Abstract:
A data processing system comprising:a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with a serial data port of processing unit, wherein a first data value communicated on said serial data port of said processing is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit, said parallel data and address busses operable communicating with a bus device, and wherein said serial-to-parallel interface logic includes:a shift register for receiving a serial data value, said shift register having a parallel output bus;an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter; anda control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuit configures said serial-to-parallel interface logic circuit to reflect an operation to be performed.