Patent ID: 6046924
Filing Date: 2000-04-04
Classification: G11C,H01L

Abstract:
A semiconductor memory device including a memory cell array divided into a plurality of sub-cell arrays, and a sense amplifier circuit arranged between adjacent ones of the sub-cell arrays, comprising:a first one-conductivity-type well in which a first sub-cell array is formed;a second one-conductivity-type well in which a second sub-cell array adjacent to said first sub-cell array is formed; anda sense amplifier circuit formation region in which said sense amplifier circuit is formed, said region being formed between said first and second one-conductivity-type wells, and said region including a third one-conductivity-type well and a first and second opposite-conductivity-type wells arranged to sandwich the third one-conductivity-type well,wherein said third one-conductivity-type well is isolated from said first and second one-conductivity-type wells by said first and second opposite-conductivity-type wells.