Patent ID: 6358755
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of forming a ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell, the method comprising:(a) forming a first planarized dielectric layer over the integrated circuit transistor; (b) forming first and second vias in the first planarized dielectric layer to provide access to first and second source/drains of the integrated circuit transistor; (c) forming first and second metal plugs in the first and second vias, respectively; (d) forming a bottom electrode over the second metal plug; (e) forming a second planarized dielectric layer over the first planarized dielectric layer and bottom electrode; (f) forming a hole in the second dielectric layer to provide access to the bottom electrode; (g) forming a ferroelectric plug in the hole in the second dielectric layer; and (h) forming a top electrode over the second dielectric layer and ferroelectric plug.