Patent ID: 8896068
Filing Date: 2014-11-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: (A) source and drain regions and a channel forming region in a substrate; (B) a gate electrode above the channel forming region with a gate insulating film between the channel forming region and the gate electrode; (C) a silicide layer on the substrate over the source and drain regions; (D) a stress applying layer on the silicide layer; (E) a first interlayer insulating layer on the source and drain regions; (F) respective first contact portions in the first interlayer insulating layer and directly connected to the source and drain regions by extending through the stress applying layer and the silicide layer; (G) a second interlayer insulating layer on the gate electrode, the first interlayer insulating layer, and the first contact portions; (H) respective second contact portions in portions of the second interlayer insulating layer over the first contact portions so that each second contact portion extends to and contacts a respective first contact portion; (I) a third contact portion in the second interlayer insulating layer and directly connected to the gate electrode; and (J) respective wires on the second interlayer insulating layer and connected to the second contact portions and the third contact portion, wherein,