Patent ID: 8809131
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A method of fabricating a nanowire field-effect transistor (FET) device, comprising the steps of: providing a wafer; forming at least one sacrificial layer and at least one silicon layer on the wafer in a stack, wherein the sacrificial layer comprises an epitaxial crystalline material which can be etched selectively to silicon; patterning a plurality of fins in the stack by patterning the sacrificial layer and the silicon layer to form the fins; forming a plurality of dummy gates over one or more first portions of the fins which will serve as channel regions of the FET device, and wherein one or more second portions of the fins which remain exposed after the step of forming the dummy gates has been performed will serve as source and drain regions of the FET device; depositing a gap filler material surrounding the dummy gates; planarizing the gap filler material; removing the dummy gates selective to the gap filler material so as to form trenches in the gap filler material; releasing portions of the silicon layer from the fins within the trenches by removing from the fins only those portions of the sacrificial layer that were patterned to form the fins and that are present within the trenches, wherein the portions of the silicon layer released within the trenches will serve as nanowire channels of the FET device and by way of the releasing step only the nanowire channels are released from the fins; and forming a plurality of replacement gates within the trenches that surround the nanowire channels of the FET device in a gate all around configuration.