Patent ID: 6689650
Filing Date: 2004-02-10
Classification: H01L

Abstract:
A method of fabricating a thin vertical channel (FIN) metal oxide semiconductor field effect transistor (MOSFET) comprising the steps of:(a) forming at least one patterned region atop a surface of an insulating region, said at least one patterned region comprising a Si-containing layer present atop said insulating region, a pad oxide present atop said Si-containing layer and a polish stop layer present atop said oxide; (b) forming planarizing insulating region abutting each patterned region, said planarizing insulating region are formed on exposed portions of said insulating region, said planarizing region being co-planar with a top surface of said polish stop layer; (c) forming a hardmask on a portion of said at least one patterned region, said hardmask being used to define vertical channel regions in said at least one patterned region; (d) selectively removing a portion of said hardmask, said polish stop layer and said pad oxide layer so as to expose a portion of said Si-containing layer thereby forming vertical channels regions and a trough having sidewalls; (e) forming insulating spacers on the sidewalls of the trough and forming a gate region between said insulating spacers in said trough, said gate region comprising two regions of gate conductors that are separated from said vertical channel regions by agate dielectric; and (f) removing said polish stop layer and said pad oxide abutting said gate region so as to expose portions of said Si-containing layer and forming source/drain diffusion regions therein thereby providing a double-gated/double channel MOSFET device in which the gate region is self-aligned to the source/drain diffusion regions and vertical channel regions.