Patent ID: 6205067
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged in a matrix of rows and columns and each including a capacitor for storing information and an access transistor for reading the information stored in said capacitor;a plurality of word lines arranged corresponding to said rows and each connected to memory cells of a corresponding row;a plurality of pairs of bit lines arranged corresponding to said columns and each connected to memory cells of a corresponding column;bit line voltage holding means provided for each respective column, for holding each bit lines of a corresponding pair of bit lines at a predetermined voltage level when activated;a plurality of sense amplifier provided corresponding to said columns and each differentially amplifying a voltage of each bit line of a corresponding pair of bit lines when activated;bit line voltage supply means responsive to an activation of a stress acceleration mode designation signal for supplying a reference voltage as said predetermined voltage to said bit line voltage holding means, said reference voltage having a voltage level different from that in a normal mode of operation;word line selecting means responsive to the activation of said stress acceleration mode designation signal for simultaneously driving a predetermined number of, at least two, word lines of said plurality of word lines to a selected state;means responsive to said stress acceleration mode designation signal for changing a level of a cell plate voltage for the capacitor of each of the memory cells; andsense amplifier control means responsive to the activation of said stress acceleration mode designation signal for maintaining each of the sense amplifier in an inactive state.