Patent ID: 6065109
Filing Date: 2000-05-16
Classification: G06F

Abstract:
A counterflow pipeline for use in an asynchronous processor, comprising:a first pipeline for transmitting instructions in a first direction, the first pipeline having a plurality of stages;a second pipeline for transmitting results in a second direction opposite the first direction, the second pipeline having a plurality of stages, each of the second pipeline stages corresponding to a first pipeline stage and forming a counterflow pipeline stage therewith; andarbitration logic coupled between the first and second pipelines for facilitating movement of the instructions in the stages of the first pipeline and movement of the results in the stages of the second pipeline, in which instruction lines and results lines are connected to control adjacent counterflow pipeline stages using a four-phase level signaling protocol, the arbitration logic including:an instruction line;a results line;an AND gate having input terminals coupled to each of the instruction line and the the results line and having an output terminal coupled to a delay element;a first OR gate having input terminals coupled to the instruction line and the delay element; anda second OR gate having input terminals coupled to the results line and the delay element, whereby the contemporaneous presence of both an instruction and a result is maintained in a particular counterflow pipeline stage until the instruction and the result can interact with each other, and instructions and results are prevented from being simultaneously released from adjacent counterflow pipeline stages.