Patent ID: 6167509
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A method of operating a pipelined processor, said processor having a plurality of registers in a register set, and having a program counter for counting sequential addresses in memory, comprising the steps of:fetching instructions from said sequential addresses in memory using said program counter, and decoding said instructions before executing said instructions,detecting a jump instruction in the fetched instructions, said jump instruction including an opcode, a register specifier and a memory address specifier, and extracting from said register specifier of said jump instruction an identification of a first of said registers for storing a first address which is a target address of said jump instruction, and extracting from said memory address specifier of said jump instruction a second address which is a prediction of said target address; andprefetching an instruction from said second address rather than from said sequential addresses, before said jump instruction is executed and before said first address is available in said first register.