Patent ID: 9118351
Filing Date: 2015-08-25
Classification: G05B,G06F,H03M

Abstract:
1. A redundant system, comprising: a hardware-implemented master part configured to receive an input signal and generate a binary output signal; a first clock delay configured to receive the input signal and generate a delayed input signal; a first signature generator coupled to the hardware-implemented master part and configured to receive the binary output signal and generate a first output signature based thereon; a second clock delay coupled to the first signature generator and configured to receive the first output signature and generate a delayed first output signature; a checker part coupled to the first clock delay and configured to receive the delayed input signal and generate a delayed binary output signal based thereon; a second signature generator coupled to the checker part and configured to receive the delayed binary output signal and generate a delayed second output signature based thereon; and a comparator coupled to the second clock delay and the second signature generator, the comparator configured to receive the delayed first output signature and the delayed second output signature and generate an error signal, a state of the error signal based upon a comparison of the delayed first output signature with the delayed second output signature.