Patent ID: 6842765
Filing Date: 2005-01-11
Classification: G06F

Abstract:
1. A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D, each of A, B and C being a double-precision floating point number, the result D being a canonical-form extended-precision floating point number having a high order component and a low order component, each double-precision number and each of the high and low order components of an extended-precision number comprising an exponent and a mantissa, the processor operating on clock cycles and comprising the post-adder data path, the normalizer and the rounder each having a data width sufficient to represent post-adder intermediate results whereby both of the high and low order components of the correctly-rounded result D may be computed, and the data path, the multiplier, the adder, the normalizer and the rounder being arranged to permit the respective mantissas of the high order component of D and of the low order component of D to be stored to the set of result registers on sequential clock cycles of the processor, and where the processor logic control determines differential values of the exponents of A, B and C and to carry out operations in the processor, the logic control providing that a. where the exponent of C is greater than the sum of the exponents of A and B by a predetermined limit, b. where the exponent of C is within the predetermined limit of the sum of the exponents of A and B, c. where the exponent of C is less than the sum of the exponents of A and B by the predetermined limit,