Patent ID: 6351841
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A method of creating a multi-gate transistor for use in an integrated circuit layout, the method comprising:finding a location that corresponds to an edge of a gate of a single gate transistor in a layout of a circuit design; forming a narrow transistor structure comprising at least one transistor having a size smaller than that provided for by design rules of said layout; and splitting the single gate transistor into multiple gates by, inserting the narrow transistor structure over a diffusion layer and between a gate, a contact, and an edge of said diffusion layer of the single gate transistor, multiplying coordinates of the inserted narrow transistor structure by an order of magnitude sufficient to result in widths of features of the narrow transistor in single units and result in structural features of the resulting multi-gate transistor to comply with the design rules after a compaction process, and running a compactor on said layout that performs the steps of, enforcing compliance of the design rules of said layout, setting gates of the narrow transistor structure to values specified in an input file, expanding metal segments of the inserted narrow structure according to the design rules, and connecting the inserted narrow structure in parallel with the single gate transistor via the expanded metal segments; wherein: said single gate transistor, prior to insertion in said diffusion layer, is represented in a device database of components used in said layout as a transistor having a size defined in units sufficient enough to allow insertion of the narrow transistor structure without overlapping other features of the single gate transistor.