Patent ID: 7106820
Filing Date: 2006-09-12
Classification: H04L

Abstract:
1. A phase synchronizer comprising: an input shift register for receiving a sequence of bits comprising a codeword; a first syndrome computing module, operatively coupled to said input shift register, for computing first syndromes relating to a first potential phase of said codeword; a first error detection module for determining, based upon said first syndromes, a first number of errors associated with said first potential phase of said codeword; a second syndrome computing module, operatively coupled to said input shift register, for computing second syndromes relating to a second potential phase of said codeword; a second error detection module for determining, based upon said second syndromes, a second number of errors associated with said second potential phase of said codeword; and a comparator arrangement for comparing said first number of errors and said second number of errors to a threshold value, said first potential phase corresponding to a valid codeword phase when said first number of errors is less than said threshold value and said second potential phase corresponding to a valid codeword phase when said second number of errors is less than said threshold value.