Patent ID: 7424027
Filing Date: 2008-09-09
Classification: H04L

Abstract:
1. For use with network systems that employ packets having an associated priority, a head of line blockage avoidance system, comprising: m inputs, m numbering at least two, configured to receive said packets; n packet first-in-first-out buffers (FIFOs), n numbering at least two, each of said n packet FIFOs occupying a same hierarchical level and configured to receive at least one of said packets from said m inputs, said n packet FIFOs configured as m subsets of packet FIFOs, each of said packet FIFOs in each of said subsets being coupled to a different one of said m inputs; a priority summarizer configured to generate a priority summary of said packets within said m inputs and said n packet FIFOs that indicates which of said n packet FIFOs is to receive a highest priority packet from one of said m inputs, wherein each of said n packet FIFOs can receive packets of two or more differing priorities; a scheduler configured to cause packets in said n packet FIFOs to be queued for processing based on said priority summary such that packets in a packet FIFO that is to receive said highest priority packets are triggered to be processed before packets in other of said n packet FIFOs so that a lower priority packet in said n packet FIFO is scheduled for processing before a higher priority packet concurrently contained in another of said n packet FIFOs is scheduled for processing; and a destination FIFO and an output, said destination FIFO interposing said n packet FIFOs and said output, said scheduler further configured to transfer at least one of said packets from one of said m inputs toward said output only if said n packet FIFO and said destination FIFO are both available to simultaneously contain said packet.