Patent ID: 6972226
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A method for producing a charge-trapping memory cell array, the method comprising: providing a semiconductor body having a main surface; forming a layer sequence on said main surface, the layer sequence including a storage layer; etching trenches arranged parallel at a distance to one another in said semiconductor body at said main surface; filling said trenches with a dielectric material to form shallow trench isolations; implanting a dopant to form a well of a first conductivity type; forming wordline stacks running across said shallow trench isolations; removing upper parts of said shallow trench isolations in regions provided for local interconnects, thereby forming recesses and exposing lateral surfaces of said semiconductor body in said trenches above remaining lower parts of said shallow trench isolations; and forming conductive bridges in the recesses of the shallow trench isolations to fill said recesses between said lateral surfaces above said lower part of said shallow trench isolations.