Patent ID: 6049136
Filing Date: 2000-04-11
Classification: H01L

Abstract:
An integrated circuit package having a unique lead configuration comprising:a die containing an integrated circuit, the die having a plurality of leads for carrying electrical signals to and from the integrated circuit, the plurality of leads being disposed over a bottom side of the die;a multi-layer substrate having at least two signal layers, the substrate being juxtaposed against the die and having a plurality of contacts disposed along a top side to align with the leads of the die to carry the electrical signals to conductive paths within the at least two signal layers, the multi-layer substrate having a larger adjoining surface area than the die and having a plurality of leads disposed across a bottom side of the multi-layer substrate for connection with a printed circuit board, the leads on the bottom side of the die being in communication with the contacts of the top side of the multi-layer substrate by way of the conductive paths;wherein the leads of the die are disposed in the following configuration:at least two high speed rows are disposed in parallel fashion near the center of the die, the high speed rows are for carrying high frequency electrical signals;a first set of at least two low speed rows of leads disposed in parallel fashion near a first side of the die, the at least to rows of leads being symmetrically disposed in parallel relation to the at least two high speed rows and spaced apart therefrom; anda second set of at least two rows of leads disposed in parallel fashion near a second side of the die, the at least to rows of leads being symmetrically disposed in parallel relation to the at least two high speed rows and spaced apart therefrom.