Patent ID: 8878612
Filing Date: 2014-11-04
Classification: G05F,H03F

Abstract:
1. A circuit method for controlling node voltages of a current mirror comprising: receiving, by an op-amp of a bias branch, a divided voltage of a voltage divider and a voltage of a node between first and second transistors, wherein the first and second transistors are configured in series between a voltage source and a ground, and wherein the voltage divider is coupled between the voltage source and the ground; and driving, by the op-amp, a gate of the second transistor to pull the node to the divided voltage, wherein a power amplifier core is coupled to the bias branch, the power amplifier core including third and fourth transistors configured in series between the voltage source and the ground, wherein a gate of the first transistor and a gate of the third transistor are coupled, and the gate of the second transistor and a gate of the fourth transistor are coupled.