Patent ID: 6021483
Filing Date: 2000-02-01
Classification: G06F

Abstract:
A bridge system including at least a PCI interface and an interface to a secondary subsystem for interconnecting a first PCI bus system and the secondary subsystem, the bridge system having a delayed transaction mechanism for enabling a transaction source attached to the first PCI bus system to effect delayed transactions with a target in the secondary subsystem, the delayed transaction mechanism comprising:means for receiving a transaction request from a transaction source and transmitting said request to a target in the secondary subsystem;a timer register for storing a delayed transaction latency;timing logic arranged to read the timer register and to provide a timer expired signal if the time between receipt of a transaction request exceeds the delayed transaction latency;means responsive to the timer expired signal to terminate the transaction request with retry;means to receive a request completion signal from the target;and means for receiving a transaction completion request from the transaction source and in response thereto enabling the transaction source to complete the transaction if the request completion signal has been received from the target,characterised by data input means for enabling the latency in the timer register to be set to a desired value, whereby the latency may be optimised according to the timing characteristics of the transaction sources to be attached to the first PCI bus and the targets in the secondary subsystem.