Patent ID: 6769040
Filing Date: 2004-07-27
Classification: G06F

Abstract:
A method for using at least two first-in, first-out (â€œFIFOâ€ ) buffers in a pipelined bus architecture, comprising,interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between phases tracked by each of the buffers; assigning each of the at least two FIFO buffers to a phase in a transaction; wherein the act of defining a transaction correspondence comprises (a) providing an equal number of data structures for each of the at least two FIFO buffers; (b) numbering each of the data structures from one to the last data structure; and (c) ensuring that a numbered data structure in one FIFO buffer will have or has information that is transactionally-related to information that is contained or will be contained in the same numbered data structure in another of the at least two FIFO buffers.