Patent ID: 8386980
Filing Date: 2013-02-26
Classification: G06F

Abstract:
1. A method of generating a design for an I/O fabric of a target integrated circuit having a core, said core having internal core pins and the fabric having external I/O chip pins, the method being performed by a programmed computer operating as a process tool executing algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language and comprising the steps of: importing integrated circuit design data from a computer, from said design data, capturing I/O specification data for the core, cells, pins, I/O control, BSR and I/O cell chaining, and die for the target integrated circuit, validating said specification data, and from said validated specification data, generating the I/O fabric design by synthesizing, configuring and inter-connecting multiplexers in a cascaded arrangement according to constraints for signal control and timing, wherein a control matrix structure is realized for each pin on both the input and output paths for the following logic types: wherein the output path for a chip pin is sourced during the method from any number (1 . . . n) of functional or test core pins, there being different pin functional or test modes for at least some different sources and comprising the step of dynamically selecting a functional or test core pin for an output chip pin, wherein the selection for a given logic type controls an individual chip pin, a group of related chip pins or globally all chip pins; wherein control priority of functional, test, and override logic in the I/O fabric is configurable; wherein timing priority of functional, test, and override logic in the I/O fabric is configurable; and wherein: