Patent ID: 6735148
Filing Date: 2004-05-11
Classification: G11C,H03L

Abstract:
A memory device comprising:a row address circuit operable to receive row address signals applied to an external terminal and to decode the row address signals to provide a row address; a column address circuit operable to receive column address signals applied to an external terminal and to decode the column address signals to provide a column address; at least one array of memory cells operable to store data written to or read from the array at a location determined by the row address and the column address; a data path circuit operable to couple data signals corresponding to the data between the at least one array and an external data terminal; a command signal generator operable to generate a sequence of control signals corresponding to command signals applied to an external terminal; and a clock processing circuit receiving an first clock signal and generating a second clock signal, the clock processing circuit including a variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other; a delay select circuit receiving at least one delay command signal indicative of a delay of the variable delay circuit, the delay select circuit being operable to generate at least one control signal responsive to the delay command signal; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which an input clock signal is coupled between a clock input terminal and a clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal.