Patent ID: 6114946
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A combinational logic circuit for determining whether an address bit is inside or outside a range at least partially defined by a control address bit, said logic circuit comprising: combinational logic connected to an address bit line for receiving the address bit being tested and connected to a control address bit line for receiving the control address bit at least partially defining the range, said combinational logic configured to produce a signal indicating whether the address bit being tested and the control address bit at least partially defining the range are equal, and said combinational logic configured to produce a signal representing a mathematical relation between the address bit being tested and the control address bit at least partially defining the range, said mathematical relation identifying whether the address bit being tested is inside or outside the range at least partially defined by the control address bit, wherein said combinational logic which is connected to the address bit line and the control address bit line includes inverting means connected to the control address bit line for inverting the control address bit which at least partially defines the range and is carried by the control address bit line, and includes AND logic connected to the address bit line and said inverting means, said combinational logic comparing the inverted control address bit output by said inverting means and the address bit carried by said address bit line and outputting the signal indicating whether the address bit being tested is greater than or less than the inverted control address bit.