Patent ID: 7142187
Filing Date: 2006-11-28
Classification: G09G

Abstract:
1. An LCD driving scaler comprising: a register controller storing control information in a register; an analog-to-digital converter generating digital pixel data synchronized with an input pixel clock signal by converting analog pixel data input therein, and outputting a horizontal synchronization signal, a vertical synchronization signal, and the input pixel clock signal generated in response to the horizontal synchronization signal, and the vertical synchronization signal; a frame rate controller adjusting the frame rate to be compatible with a liquid crystal display (LCD) panel and outputting the digital pixel data, the horizontal synchronization signal, and the vertical synchronization signal; a pixel data scaler generating scaler output pixel data in response to the digital pixel data, the horizontal synchronization signal, and the vertical synchronization signal, the output pixel data having an adjusted frame rate by scaling the digital pixel data to be synchronized with a scaler pixel clock signal, which is compatible with the LCD panel, and outputting the horizontal synchronization signal and the vertical synchronization signal having the adjusted frame rate; a selector selectively outputting a system clock signal and the input pixel clock signal; a predivider dividing the frequency of an output signal of the selector and outputting a predivider signal; and a spread spectrum PLL generating the scaler pixel clock signal corresponding to a signal representing a phase difference between the predivider signal and a main divider signal, the horizontal synchronization signal having an adjusted frame rate, and a plurality of oscillation signals of different phases and generating the main divider signal by dividing the frequencies of the oscillation signals, which are sequentially selected in response to a decoding signal.