Patent ID: 8019924
Filing Date: 2011-09-13
Classification: G06F,Y10S

Abstract:
1. A processor-based system, comprising: a processor having a processor bus including an address bus, a control bus and a data bus; a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a memory hub controller coupled to a system memory port and adapted to provide memory command packets including information to access memory devices; a memory module having a plurality of memory devices coupled to a memory hub, the memory hub adapted to receive memory command packets and access the memory devices according to the memory command packets and further adapted to provide memory responses in response thereto; a first portion of a memory bus coupled to the system memory port and the memory hub on which the memory command packets from the memory hub controller are provided to the memory hub of the memory module and memory responses are provided to the memory hub controller; an expansion module having a processor circuit adapted to provide memory command packets including information to access the memory devices of the memory module and further adapted to process data included in the memory responses from the memory hub of the memory module, the memory module and expansion coupled to each other in series; and a second portion of the memory bus coupled to the memory hub of the memory module and the processor circuit of the expansion module on which the memory command packets from the processor circuit are provided to the memory hub of the memory module and memory responses are provided to the processor circuit.