Patent ID: 8710657
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A semiconductor package comprising: a plurality of connection pads on a surface of a semiconductor chip; a plurality of first bumps on and configured to be electrically connected to the plurality of connection pads, wherein each of the plurality of first bumps comprises a first solder ball and a first pillar between the first solder ball and one of the plurality of connection pads; a plurality of second bumps on the semiconductor chip and configured to be electrically isolated from the plurality of connection pads, wherein each of the plurality of second bumps comprises a second solder ball and a second pillar between the second solder ball and the semiconductor chip, and the second pillar comprises a solder channel configured to allow a portion of the second solder ball to extend into the solder channel; and a passivation layer extending between the plurality of second bumps and the semiconductor chip, wherein bottom surfaces of the plurality of second bumps contact the passivation layer, and the bottom surfaces of the plurality of second bumps are higher than bottom surfaces of the plurality of first bumps relative to the surface of the semiconductor chip.