Patent ID: 6306760
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method of forming a self-aligned contact hole on a semiconductor wafer, the semiconductor wafer comprising:a substrate;an array area located on the substrate comprising an array of memory cells of a dynamic random access memory(DRAM), the array of memory cells comprising a first gate electrode and a second gate electrode adjacent to the first gate electrode; anda periphery area located on the substrate comprising a control circuit of the DRAM, the control circuit comprising at least a third gate electrode;the method comprising:forming a first doped area over each of two opposite sides of each gate electrode;forming a first dielectric layer to cover the substrate and all of the gate electrodes on the surface of the substrate;forming a first photoresist layer on the surface of the first dielectric layer;performing a lithographic process to remove the first photoresist layer over the periphery area;performing a first dry etching process to remove a portion of the first dielectric layer in the periphery area, the remainder of the first dielectric layer in the periphery area forming a first spacer on a wall of each of two opposite sides of the third gate electrode;removing the first photoresist layer completely; andforming a second spacer on a wall of each of the two opposite sides of the first and second gate electrodes in the array area;wherein the first spacers are thicker than the second spacers, and the second spacers between the first and second gate electrodes are internal walls of a self-aligned contact hole between the first and second gate electrodes.