Patent ID: 6496934
Filing Date: 2002-12-17
Classification: G06F

Abstract:
A data processor comprising:a central processing unit; a bus coupled to said central processing unit; and a data transfer controller, wherein said data transfer controller comprises: an address register for setting a data transfer source address and a data destination address, a control register including a storing area for storing resource select information to designate with a plurality of bits a combination mode of the data transfer source and the data transfer destination, an address error detector section for detecting an illegal address access in which at least any one of the data transfer source address and the data transfer destination address set to said address register, when a data transfer request is generated, is in conflict with the combination mode of the data transfer source and the data transfer destination and is directed to a memory area where such an address is prohibited, and a control circuit for executing, when said illegal address access is not detected, data transfer control utilizing the information of said address register and control register and inhibiting, when said illegal address access is detected, the data transfer operation depending on said data transfer request.