Patent ID: 8927968
Filing Date: 2015-01-06
Classification: B82Y,H01L,Y10S

Abstract:
1. A semiconductor device comprising: a first buried oxide layer portion and a second buried oxide layer portion each located on an uppermost surface of a buried boron nitride layer, wherein a portion of said uppermost surface of said buried boron nitride layer between said first and second buried oxide layer portions is exposed; a first semiconductor pad located atop said first buried oxide layer portion; a second semiconductor pad located atop said second buried oxide layer portion; a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-configuration and suspended above said exposed portion of said uppermost surface of said buried boron nitride layer; a gate dielectric surrounding each semiconductor nanowire and located directly on a top surface and a bottom surface of each semiconductor nanowire; a gate surrounding each semiconductor nanowire and located directly on a surface of each gate dielectric; and a gate dielectric portion located directly on a surface of said exposed portion of said buried boron nitride layer, and in contact with a surface of said gate located beneath each semiconductor nanowire.