Patent ID: 8094496
Filing Date: 2012-01-10
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a plurality of active areas formed to extend in a first direction and separated from one another with a plurality of trench portions disposed therebetween; a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of the plurality of trench portions; a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film disposed therebetween; a plurality of first metal interconnections formed to extend in a second direction perpendicular to the first direction, arranged on a surface of the semiconductor substrate with inter-level insulating films disposed therebetween and each functioning as one of bit lines and source lines; a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which are formed to intersect with the plurality of first metal interconnections and each functioning as one of sources and drains; a plurality of second conductivity-type diffusion layer regions having an opposite conductivity type to that of the plurality of first conductivity-type diffusion layer regions and formed in the plurality of active areas to electrically isolate the plurality of first conductivity-type diffusion layer regions from one another; and a plurality of connection contacts arranged in a staggered form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.