Patent ID: 6892294
Filing Date: 2005-05-10
Classification: G06F

Abstract:
1. A method for finding a predefined plurality of instructions, if available, that are ready to be executed and that reside in an instruction reordering mechanism of a processor that can launch execution of instructions out of order via a predefined number of instruction ports, comprising the steps of: (a) providing said instruction reordering mechanism having a plurality of said instructions, each said instruction having a respective logic element for causing and preventing launching, when appropriate, of said instruction; and (b) propagating a set of signals successively through said logic elements of said instruction reordering mechanism, said set of signals responsive to instruction ports and port information, wherein an instruction identified as valid for launching is launched on a select instruction port selected from a plurality of instruction ports available to process the instruction, the select instruction port identified via propagation logic forwarded through said logic elements and wherein said propagation logic includes a next available instruction port identifier when an instruction port is available and an indication of how many instruction ports are available.