Patent ID: 6157214
Filing Date: 2000-12-05
Classification: H03K

Abstract:
A programmable logic device, comprising:a rectilinear array of logic cells pitched with first and second general cell pitches P.sub.1, P.sub.2, respectively, in first and second axial directions, respectively, of the array; andan array of wires each extending generally in the first direction between a respective pair of the cells which have a pitch of N.sub.1 .times.P.sub.1, where N.sub.1 is an integer greater than one, the wire array having a pitch in the second direction generally equal to N.sub.2 .times.P.sub.2, where N.sub.2 is an integer greater than zero;wherein pairs of the wires of the array which are adjacent in the second direction are mutually offset in the first direction.