Patent ID: 6079023
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A multi-bank memory device, comprising:a first active array voltage generator that is responsive to a reference voltage signal and generates a first active array voltage at a first voltage level on a first active power supply signal line when a first memory array bank signal applied thereto is in a first logic state, said first voltage level having a magnitude that equals a magnitude of the reference voltage signal;a standby voltage generator that is responsive to the reference voltage signal and generates a standby voltage at the first voltage level on a standby power supply signal line that is electrically connected to an output of said standby voltage generator;a first memory array bank electrically coupled to the first active power supply signal line; anda first switch that is responsive to the first memory array bank signal and closes to electrically connect the standby power supply signal line to said first memory array bank when the first memory array bank signal is in a second logic state opposite the first logic state, but does not have circuitry therein that can be used to disconnect an output of said first active array voltage generator from the first active power supply signal line.