Patent ID: 6316293
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of forming a NAND-type flash memory device, comprising the steps of:forming a floating gate region over a tunnel oxide layer on a core region of a substrate;forming an insulating layer over the floating gate region and over a select gate transistor region;performing a periphery dual oxide process, wherein performing the peripheral dual oxide process comprises the steps of:forming an oxide layer over a surface of the device;forming and patterning a mask over the oxide layer, thereby forming a plurality of openings in the mask that define a plurality of regions wherein an oxide region having a second thickness will be formed;etching the oxide layer, thereby removing the oxide layer in regions defined by the openings in the mask;removing the mask; andforming another oxide layer over the surface of the device, wherein a region previously covered by the mask has a first thickness and the plurality of regions previously etched have the second thickness, thereby forming an oxide region having the first thickness in a high voltage periphery region and an oxide region having the second thickness in a low voltage periphery region, wherein the first thickness is greater than the second thickness;forming a conductive layer over a surface of the device; andpatterning the conductive layer to form a gate over the oxide region in the low voltage periphery region and thereby to form a low voltage periphery transistor, and to form a gate over the oxide region in the high voltage periphery region and thereby to form a high voltage periphery transistor and to form a control gate over the insulating layer in the floating gate region, thereby forming a stacked gate flash memory cell in the core region and to form a gate over the insulating layer in the select gate transistor region, thereby forming a select gate transistor.