Patent ID: 6812558
Filing Date: 2004-11-02
Classification: B81B,B81C,H01L

Abstract:
A wafer scale package for electronic circuits, comprising:a base wafer having a plurality of locations each accommodating an electronic circuit, each said circuit including at least one electronic device and associated signal lines; a cover wafer having a corresponding like plurality of said locations each including at least one cavity of sufficient size to accommodate said electronic device; each said location of said cover wafer including a plurality of electrically conducting vias for establishing electrical continuity with said signal lines, at the bottom of said vias; a multilayer metallic seal surrounding each said location to provide a peripheral hermetic seal; a multilayer metallic seal surrounding each said bottom of said vias to provide a via hermetic seal; said peripheral hermetic seal being of sufficient width to enable dicing along said peripheral hermetic seal to form individual die packages, each containing a hermetically sealed said electronic circuit.