Patent ID: 8502378
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A package unit, comprising: a substrate; a first patterned circuit layer disposed on a surface of the substrate; a first conductive pillar deposited through the substrate and electrically connected to the first patterned circuit layer; an isolation layer formed on the first patterned circuit layer, wherein the isolation layer has an opening exposing a part of the first patterned circuit to form a pad; a semiconductor element disposed on the substrate, wherein the semiconductor element comprises at least one chip; an insulation layer covering the semiconductor element and the substrate; a second conductive pillar deposited through the insulation layer and electrically connected to the first conductive pillar; a third conductive pillar deposited through the insulation layer and electrically connected to the semiconductor element; a second patterned circuit layer disposed on the insulation layer and electrically connected to the second and the third conductive pillars; and a conductive bump disposed on the second patterned metal layer.