Patent ID: 6172391
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A DRAM cell arrangement, comprising:memory cells, each of the memory cells having a selection transistor structured as a vertical MOS transistor and a storage capacitor;a semiconductor structure having two sidewalls lying opposite one another;the semiconductor structure having at least a first source/drain region of two source/drain regions and a channel region of the selection transistor arranged therebelow;the first source/drain region being located at the two sidewalls of the semiconductor structure;the channel region being located adjacent a first sidewall of the two sidewalls of the semiconductor structure at which a first gate dielectric is adjacent;a gate electrode that is connected to a first word line being located at the first gate dielectric;an element that prevents formation of a channel as a channel stop zone, the element being located at a second sidewall of the two sidewalls of the semiconductor structure at a height of the channel region of the selection transistor;a second word line located next to the element that prevents the formation of a channel and outside the semiconductor structure;the first source/drain region connected to the storage capacitor; andthe second source/drain region connected to a bit line that proceeds transverse to the first word line.