Patent ID: 9184974
Filing Date: 2015-11-10
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: a plurality of in-phase multiplying cells that receive an in-phase local oscillator signal and a plurality of in-phase bits, each in-phase multiplying cell producing an output signal based on a received one of the plurality of in-phase bits; a plurality of quadrature multiplying cells that receive a quadrature local oscillator signal and a plurality of quadrature bits, each quadrature multiplying cell producing an output signal based on the received one of the plurality of quadrature bits; a first output line connected to a first set of the plurality of in-phase multiplying cells and a first set of the plurality of quadrature multiplying cells, the first output line propagating a first output signal produced from output signals of the first set of the plurality of in-phase multiplying cells and the first set of the plurality of quadrature multiplying cells; and a second output line connected to a second set of the plurality of in-phase multiplying cells and a second set of the plurality of quadrature multiplying cells, the second output line propagating a second output signal produced from output signals of the second set of the plurality of in-phase multiplying cells and the second set of the plurality of quadrature multiplying cells; wherein the plurality of in-phase multiplying cells and the plurality of quadrature multiplying cells are arranged into first and second rows, wherein each in-phase bit has a significance from most significant to least significant and a binary-weighted number of in-phase multiplying cells are connected to each in-phase bit, the binary-weighted number matching the significance of the in-phase bit, wherein each quadrature bit has a significance from most significant to least significant and a binary-weighted number of quadrature multiplying cells are connected to each quadrature bit, the binary-weighted number matching the significance of the quadrature bit, wherein an in-phase multiplying cell is connected to a least significant in-phase bit and arranged at a center of the first row, wherein a quadrature multiplying cell is connected to a least significant quadrature bit and arranged at a center of the second row, wherein an in-phase multiplying cell is connected to a most significant in-phase bit and arranged at each end of the second row, and wherein a quadrature multiplying cell is connected to a most significant quadrature bit and arranged at each end of the first row.