Patent ID: 7432159
Filing Date: 2008-10-07
Classification: H01L

Abstract:
1. A method of fabricating an EEPROM, comprising: forming mold patterns on a predetermined region of a semiconductor substrate; forming a tunnel insulation layer on a resultant structure where the mold patterns are formed; forming a tunnel spacer on sidewalls of the mold patterns to cover a top surface and a sidewall of the tunnel insulation layer; forming a gate insulation layer on the semiconductor substrate between the tunnel spacers, the gate insulation layer being thicker than the tunnel insulation layer; removing the tunnel spacers to expose the tunnel insulation layer; forming a first conductive layer on the resultant structure where the tunnel spacers have been removed; planarizing the first conductive layer down to a top surface of the mold pattern to form a first conductive pattern filling a gap region between the mold patterns; removing the exposed mold patterns; forming an intergate dielectric and a second conductive layer on the resultant structure where the mold patterns have been removed; and patterning the second conductive layer, the intergate dielectric, and the first conductive pattern to form gate electrodes of a memory transistor and a selection transistor.