Patent ID: 6185136
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A memory device, comprisinga first array of memory cells arranged in rows and columns, the first array including at least one redundant column of memory cells;a control circuit structured to provide control signals for controlling the operation of the memory device responsive to command signals received by the memory device;a data path circuit structured to couple data between the first array and an externally accessible data bus, the data path circuit including at least one pair of complimentary input/output lines;a row address decoder decoding row addresses received by the memory device and activating a row of memory cells corresponding to the row address in the first array;a plurality of column node circuits each including at least one pair of complimentary digit lines, each of the column node circuits comprising:a sense amplifier coupled between each pair of the complimentary digit lines of the column node circuit;an equilibration circuit coupled between each pair of the complimentary digit lines of the column node circuit; andan input/output circuit coupled to each pair of the complimentary digit lines of the column node circuit, the input/output circuit being structured to couple each pair of complimentary digit lines of the column node circuit to a respective pair of complimentary input/output lines responsive to a column enable signal;a column address decoder decoding column addresses received by the memory device and to generate a plurality of the column enable signals, the column address decoder generating at least one of the column enable signals responsive to each of the column addresses;a pair of first coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the first array, the first coupling switches having a conductive state determined by a respective column node disable signal;a second pair of coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the second array, the coupling switches having a conductive state determined by the respective column node disable signal; anda redundant column control circuit applying a respective column node disable signal to the first coupling switches coupled to each of the column node circuits, each of the redundant column disable signals causing the first coupling switches coupled to the respective column node circuits to be non-conductive responsive to a redundant column of memory cells being substituted for the column of memory cells to which the column node circuit is coupled.