Patent ID: 7596677
Filing Date: 2009-09-29
Classification: G06F

Abstract:
1. A system for virtualizing a processor, comprising: a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures; a Virtual Machine (VM) running guest code and having at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space, wherein at least some of the guest paging structures are mapped to the real paging structures; for each guest physical page that is mapped to the real paging structures, means for handling a connection structure between the guest physical page and a real physical address of the guest physical page; a cache of connection structures representing cached paths to the real paging structures; each path being described by guest paging structure descriptors and by tie descriptors; and each path comprising a plurality of nodes connected by the tie descriptors, wherein each guest paging structure descriptor is in a node of at least one path, wherein each guest paging structure either points to other guest paging structures or to guest physical pages, and wherein each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.