Patent ID: 6763368
Filing Date: 2004-07-13
Classification: G06F

Abstract:
An apparatus comprising:a redundant arithmetic circuit to perform an arithmetic operation on a plurality of operands, one or more of the operands received by the redundant arithmetic circuit being represented in redundant form, and said arithmetic circuit to generate a valid first result of the arithmetic operation represented in redundant form, the first result having a least significant digit and a most significant digit; a comparator circuit operatively coupled with the arithmetic circuit to receive the first result in redundant form, the comparator circuit also to receive a first expected value and to perform an equality comparison of the first result represented in redundant form to the first expected value, and to generate a second result indicating the truth of said equality comparison, the comparator circuit generating said second result independent of any propagation path to facilitate carry signal propagation from the least significant digit to the most significant digit.