Patent ID: 6717445
Filing Date: 2004-04-06
Classification: H03K

Abstract:
A circuit comprising:a signal input to receive a signal; a low-jitter buffer circuit to receive the signal input and to generate a buffer circuit output; and a voltage following circuit to receive the signal input and to generate a voltage following output, wherein the buffer circuit output and the voltage following circuit output are coupled to a circuit output node to produce a low-jitter output signal, the voltage following circuit including (1) a first amplifier, including a positive input, a negative input and an output, (2) an NMOS transistor including a gate, a source and a drain, the positive input of the first amplifier being coupled to receive the input signal, the negative input of the first amplifier being coupled to the source of the NMOS transistor, the output of the first amplifier being coupled to the gate of the NMOS transistor, the drain of the NMOS transistor being coupled to a positive supply voltage, and the source of the NMOS transistor being coupled to the circuit output node, (3) a second amplifier, including a positive input, a negative input and an output, and (4) a PMOS transistor, including a gate, a source and a drain, the positive input of the second amplifier being coupled to receive the input signal, the negative input of the second amplifier being coupled to the source of the PMOS transistor, the output of the second amplifier being coupled to the gate of the PMOS transistor, the drain of the PMOS transistor being coupled to a supply voltage less than the positive supply voltage, and the source of the PMOS transistor being coupled to the circuit output node.