Patent ID: 6990034
Filing Date: 2006-01-24
Classification: G11C

Abstract:
1. A static semiconductor memory device having a standby mode and normal operation mode as operation modes, comprising: a memory cell array having static memory cells arrayed in a matrix; a word line arranged in correspondence with each row of said memory cell array; a pair of bit lines arranged in correspondence with each column of said memory cell array; a plurality of precharge circuits which precharge said bit lines; a precharge control circuit which generates and outputs a precharge control signal which controls said precharge circuits, on the basis of an operation mode signal which is externally input to specify a period of the standby mode and a period of the normal operation mode; a word line selection circuit which controls access to the static memory cells by outputting a word line select signal which selects the word line; and an internal control signal generation circuit which outputs a normal precharge control signal which changes in synchronism with the word line select signal output from said word line selection circuit and controls precharge of said bit lines, wherein said precharge control circuit outputs, as the precharge control signal, the normal precharge control signal during the period of the normal operation modes, and wherein said word line select signal is independent of said precharge control signal.