Patent ID: 6772314
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A data processing device comprising:a CPU; a rewritable non-volatile memory including a program storage region that stores first and second programs to be executed by the CPU, and a data storage region that stores data to be accessed by the CPU; a ROM that stores a third program to be executed by the CPU; a RAM that is mapped to a first address range in an address space of the CPU; and an address decoder which is equipped with a flag register, and maps the non-volatile memory to a second address range in the address space of the CPU when the flag register is in a first state and maps the ROM to the second address range in the address space of the CPU and maps the data storage region of the non-volatile memory to a third address range in the address space of the CPU when the flag register is in a second state, wherein the first program stored in the non-volatile memory includes a routine to transfer the second program stored in the non-volatile memory to the RAM, and to branch to a head address of the second program transferred to the RAM, wherein the second program stored in the non-volatile memory includes a routine to set the flag register of the address decoder to the second state, to call the third program stored in the ROM as a sub-routine, and to set the flag register of the address decoder to the first state, and wherein the third program stored in the ROM includes a routine to write data stored in the RAM in the data storage region of the non-volatile memory that is mapped to the third address range.