Patent ID: 6400627
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A magnetic memory unit comprising:at least one magnetic resistor, a magnetized direction of the magnetic resistor representing bit information stored in the magnetic memory unit; at least one read line; a current source for providing the magnetic resistor a bias current to produce an output voltage; and a sensing circuit for sensing the output voltage, the sensing circuit comprising: a first inverter and a second inverter electrically connected in a back-to-back fashion forming a latch; an enabler for enabling the first inverter and the second inverter, causing a voltage of an input end and an output end to change in two opposite manners; a first capacitor and a second capacitor; and an equalizer electrically connected with the input end and the output end for equalizing voltages of the input end and the output end; wherein when the enabler is off, the equalizer is on, and the read line is on for pre-reading, the voltages of the input end and the output end are the same, and when the enabler is turned on, the equalizer is turned off, the read line is on, and the voltages of the input end and the output end are changed to two opposite voltages enabling sensing and recording of the bit information stored in the magnetic memory unit.