Patent ID: 6803285
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising:forming a plurality of isolation structures in the substrate, the isolation structures defining at least a low Vt NFET region, a high Vt NFET region, a high Vt PFET region, and a low Vt PFET region; patterning a first masking layer to expose at least the low Vt NFET region and the high Vt NFET region and to cover at least the high Vt PFET region and the low Vt PFET region; performing a p-well implant and a low Vtn implant into the exposed NFET regions; removing the first masking layer; patterning a second masking layer to expose at least the high Vt PFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt NFET region; performing an n-well implant and a high Vtp implant into the exposed PFET regions; removing the second masking layer; patterning a third masking layer to expose at least the high Vt NFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt PFET region; and performing a high Vtn implant into at least the exposed high Vt NFET and low Vt PFET regions.