Patent ID: 6265274
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method of forming a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, and a dielectric layer positioned on the silicon substrate, the method comprising:forming a gate on at least one region of the dielectric layer;forming a first silicon oxide layer on the semiconductor wafer, the first silicon oxide layer covering the gate;performing a first ion implantation process to form two doped areas on the silicon substrate at two opposite sides of the gate that are used as two lightly doped drains of the MOS transistor;forming a second silicon oxide layer on the semiconductor wafer, the second silicon oxide layer covering the first silicon oxide layer;forming a sacrificial layer on the second silicon oxide layer;performing a first etching process to remove the sacrificial layer on top of the gate, making portions of the gate protrude from the remaining sacrificial layer;performing a second etching process to remove the first and second silicon oxide layers on the protruding portion of the gate;removing the sacrificial layer;forming a silicon nitride layer on the semiconductor wafer, the silicon nitride layer covering the protruding portion of the gate and the remaining first and second silicon oxide layers;performing a third anisotropic etching process to remove the silicon nitride layer on top of the gate and to form a spacer surrounding the gate;performing a second ion implantation process to form two doped areas on the silicon substrate on two opposite sides of the spacer which are used as source and drain of the MOS transistor.