Patent ID: 6809601
Filing Date: 2004-10-26
Classification: H03L

Abstract:
A phase detector for a delay locked loop having a delay unit for delaying a periodic clock signal by a settable delay, comprising:a first input for the periodic clock signal, a second input for a delayed clock signal, an UP output for outputting a first pulse signal, a DOWN output for outputting a second pulse signal, and a reset device, the first and second signals respectively assuming a first level or a second level, for setting the delay unit, the first pulse signal changing to the first level with a positive edge of the clock signal and the second pulse signal changing to the first level with a positive edge of the delayed clock signal and, if the first and second pulse signals are at the first level, said reset device resets the first and second pulse signals to the second level; a blocking device connected to tap off a partly delayed clock signal at the delay unit, the partly delayed clock signal being delayed relative to the clock signal less than the delayed clock signal, said blocking device being configured to prevent a resetting of the first pulse signal for at least half a period of the clock signal if a positive edge of the partly delayed clock signal occurs while the first pulse signal is at the first level.