Patent ID: 7246257
Filing Date: 2007-07-17
Classification: G06F

Abstract:
1. A computer system, unaffected by memory module instability, comprising: at least one memory mirror unit controlling a plurality of memory modules and receiving a corresponding error control signal for control of corresponding memory modules, wherein each of the memory mirror units writes data to the corresponding memory modules during a write cycle and activates a first memory module among the memory modules, reading data during a read cycle; a memory controller enabling the error control signal upon detection of a read error in the first memory module, wherein the memory mirror unit disables the first memory module and activates a second memory module among the memory modules when the read error occurs in the first memory module; a central processing unit (CPU); and a system interruption device providing an interruption signal to the CPU to interrupt system operations and then activate the corresponding error control signal when the memory controller detects the read error; wherein each memory mirror unit comprises: a first AND gate comprising a first input terminal, a second input terminal, a third input terminal receiving a row selecting signal, a fourth input terminal, a fifth input terminal receiving a write enable signal, and a sixth input terminal receiving the error control signal; a first inverter comprising an input terminal receiving a chip control signal and an output terminal coupled to the first input terminal of the first AND gate; a second inverter comprising an input terminal receiving a first enable signal and an output terminal coupled to the second input terminal of the first AND gate; a third inverter comprising an input terminal receiving a column selecting signal and having an output terminal coupled to the fourth input terminal of the first AND gate; a second AND gate comprising a first input terminal, a second input terminal, a third input terminal receiving the row selecting signal, a fourth input terminal, a fifth input terminal receiving the write enable signal, and a sixth input terminal; a fourth inverter comprising an input terminal receiving the chip control signal and an output terminal coupled to the first input terminal of the second AND gate; a fifth inverter comprising an input terminal receiving a second enable signal and an output terminal coupled to the second input terminal of the second AND gate; a sixth inverter comprising an input terminal receiving the column selecting signal and an output terminal coupled to the fourth input terminal of the second AND gate; a seventh inverter comprising an input terminal receiving the error control signal and an output terminal coupled to the sixth input terminal of the second AND gate; a first switch comprising an output terminal, a control terminal, and an input terminal receiving the first enable signal; a second switch comprising an input terminal receiving the second enable signal, an output terminal coupled to the output terminal of the first switch and a control terminal receiving the chip enable signal; an eighth inverter comprising an input terminal receiving the chip enable signal and an output terminal coupled to the control terminal of the first switch; a first OR gate comprising a first input terminal receiving the first enable signal, a second input terminal coupled to the output terminal of the first AND gate, and an output terminal coupled to the first memory module; and a second OR gate having a first input terminal coupled to the output terminal of the first switch, a second input terminal coupled to the output terminal of the second AND gate, and an output terminal coupled to the second memory module.