Patent ID: 7930521
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A processor, comprising: a plurality of registers; a first processing block coupled to the plurality of registers through operand selection multiplexing circuitry, wherein said operand selection multiplexing circuitry comprises a first and second level of multiplexers, wherein outputs of the plurality of registers are coupled to inputs of the first level of multiplexers, and wherein outputs of the first level multiplexers are coupled to inputs of the second level of multiplexers, and wherein outputs of the second level of multiplexers are coupled to inputs of the first processing block; and a second processing block coupled to the plurality of registers through the operand selection multiplexing circuitry, wherein the first processing block and the second processing block are configured to read, at each clock cycle, from selected registers of the plurality of registers through the operand selection multiplexing circuitry.