Patent ID: 6779105
Filing Date: 2004-08-17
Classification: G06F

Abstract:
A pipeline microprocessor comprising:exactly two pipeline stages being defined by a first pipeline stage and a second pipeline stage, each of the pipeline stages including a first sector and a second sector, the first sector of the second pipeline stage being contiguous to the second sector of the first pipeline stage; means for reading instructions and means for decoding instructions of a program recorded in a memory, the means for reading and the means for decoding instructions being laid out in the first pipeline stage of the exactly two pipeline stages; a bank of registers that is laid out in a read mode in the first sector of the second pipeline stage of the exactly two pipeline stages and that is laid out in a write mode in the second sector of the second pipeline stage; and computation and data-processing means that are laid out in the first sector of the second pipeline stage, the first sector being activated only during a first half-cycle of a clock signal of the microprocessor and the second sector being activated only during a second clock half-cycle of the clock signal of the microprocessor.