Patent ID: 6295600
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A microprocessor for executing a plurality of reads, the microprocessor comprising:an instruction cache for storing instructions for the plurality of threads;an instruction decode unit coupled to the instruction cache and configured to decode said instructions for the plurality of threads;a plurality of instruction buffers coupled to the instruction decode unit, wherein each of the plurality of instruction buffers is configured to receive decoded instructions corresponding to one of the plurality of threads from the instruction decode unit, and to store said decoded instructions;a plurality of execution units configured to receive and execute said decoded instructions from a first selected one of the plurality of instruction buffers and corresponding to a first thread, wherein one of the plurality of execution units is configured to execute a first instruction which invokes a memory access, wherein the first instruction includes a thread indictor stored in a thread indicator field of the first instruction;a plurality of program address registers, wherein each of the program address registers is associated with a corresponding thread of the plurality of threads, wherein each of the program address registers is configured to store an address for the corresponding thread;thread switching logic configured to receive a cache-miss indication signal indicating a level-two cache miss associated with the memory access of the first instruction, and in response to the cache-miss indication signal, (a) to receive the thread indicator of the first instruction from said one of the plurality of execution units, (b) to select a first program address register of the plurality of program address registers which corresponds to the thread, indicator, (c) to invoke the fetching of a new thread based on the address stored in the first program address register, (d) to disable dispatch of decoded instructions from the first selected instruction buffer to the execution units, and (e) to enable dispatch of decoded instructions from a second selected instruction buffer to the execution units, wherein the second selected instruction buffer is determined by the thread indicator.