Patent ID: 8836626
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of pixels arranged in a matrix, each of the plurality of pixels being electrically connected to first to seventh wirings and comprising: wherein a cathode of the photodiode is electrically connected to the first wiring, wherein an anode of the photodiode is electrically connected to a first electrode of the first capacitor, wherein a first electrode of the second capacitor is electrically connected to the third wiring, wherein one of a source and a drain of the first transistor is electrically connected to the second wiring, wherein a gate of the first transistor is electrically connected to the sixth wiring, wherein one of a source and a drain of the second transistor is electrically connected to the fourth wiring, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the seventh wiring, wherein a gate of the third transistor is electrically connected to the fifth wiring, and wherein the data holding portion is configured by electrically connecting a second electrode of the first capacitor, a second electrode of the second capacitor, the other of the source and the drain of the first transistor, and a gate of the second transistor.