Patent ID: 6667555
Filing Date: 2003-12-23
Classification: H01L,H05K

Abstract:
A stacked multi-chip module array, comprising:a first multi-chip module (MCM) including a planar printed circuit board with circuitization patterns thereon and at least one surface mounted component attached to the patterns; a spacer and interconnecting stud attached to the first MCM and extending beyond the surface mounted component; the spacer and interconnecting stud comprising at least two dielectric laminates; thermal contacts attached to the upper and lower surfaces of the stud and connected to the circuitization pattern on the first MCM; a second MOM including at least one surface mounted component and circuitization patterns an upper and lower surfaces including contact regions; and connections joining the thermal contacts on the spacer-connector to the second MCM contacts whereby the first and second MCMs are spaced apart and signal paths are established between the first and second MCMs.