Patent ID: 8749296
Filing Date: 2014-06-10
Classification: H03K

Abstract:
1. A serially stacked shunt semiconductor on insulator (SOI) switch comprising: a plurality of field effect transistor (FET) devices, wherein each FET device of the plurality of FET devices includes a gate contact, a drain contact, and a source contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled to a second end of the chain, and wherein the gate contact of the FET device at the second end of the chain is a first gate contact; a plurality of gate biasing circuits coupled in series, wherein each one of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices, and further wherein each one of the plurality of gate biasing circuits includes a resistor; and a plurality of gate speedup circuits, wherein each one of the plurality of gate speedup circuits is coupled across a corresponding gate biasing circuit of the plurality of gate biasing circuits.