Patent ID: 8347111
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A data processing apparatus comprising: an integrated circuit having a data processor, a non-volatile memory storing at least one security code, at least one interface at a boundary of the integrated circuit via which communication with the data processor can occur, and a disabling circuit to disable the interface in response to the security code stored in the non-volatile memory having a particular value, where disabling the interface blocks access to the data processor via the interface, wherein the disabling circuit has a gate interposed between the interface and the data processor, wherein the gate is disabled by the security code having the particular value, wherein disabling the gate prevents access of the data processor via the interface, wherein the gate is enabled by the security code having a second value, wherein enabling the gate allows the data processor to be accessed via the interface, and wherein the data processor is to perform testing in response to access through the interface when the gate is enabled.