Patent ID: 7995398
Filing Date: 2011-08-09
Classification: G11C

Abstract:
1. A read circuit for sensing a conductance to ground in a bit line of a non-volatile memory cell, comprising: an input transistor receiving a binary input signal and providing, in response thereto, a control signal indicating a standby state and a sensing state; a charging transistor coupled to receive the control signal, the charging transistor charging the bit line to a bias voltage when the control signal is in the standby state and decoupling from the bit line when the control signal is in the sensing state; a current sensing circuit coupled to the bit line, wherein the current sensing circuit provides a current detection signal that changes state when a current flows to ground in the bit line greater than a predetermined value; and an output circuit having providing an output signal having a first state, when the bit line is charged, and changes to a second state when the current detection signal changes state.