Patent ID: 6211573
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A lead-on-chip structure of a semiconductor device packaged with a sealing resin, said lead-on-chip structure comprising:a semiconductor chip having two alignments of bonding pads along opposite sides of a center line on a top surface of said semiconductor chip, said center line separating said semiconductor chip into first and second side regions;first and second alignments of inner leads which extend over said first and second side regions of said semiconductor chip respectively so that said inner leads are spaced from said top surface of said semiconductor chip, and said inner leads having stitched portions positioned in inside terminal portions thereof, said stitched portions of said inner leads being positioned outside of said bonding pads, said inner leads extending substantially in parallel to each other and along a direction perpendicular to said center line of said semiconductor chip;bonding wires electrically connecting said stitched portions of said inner leads to corresponding said bonding pads of said semiconductor chip; andone inner electrically insulative adhesive tape having top and bottom surfaces with adhesion force arranged on each of the first and second side regions of the semiconductor chip, said bottom surfaces of each said inner tape being positioned outside of said bonding pads, said top surfaces of each said inner tape being adhered on bottom surfaces of said stitched portions of said inner leads,at least one outer electrically insulative double-sided adhesive tape piece separate from the inner tape arranged on each of the first and second side regions of the semiconductor chip, each said outer tape piece being positioned in the vicinity of an edge of said semiconductor chip which extends substantially in parallel to said center line,wherein over each said side region at least one of said inner leads is secured by both the inner tape and one of the at least one outer tape piece.