Patent ID: 7042038
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: a semiconductor substrate with an active region defined by an element isolation region, word lines extending in a first direction over said active region such that gate electrodes of metal insulator semiconductor field effect transistors (MISFETs) are electrically coupled to said word lines, semiconductor regions formed in said active region extending in a second direction perpendicular to the first direction such that said semiconductor regions serve as a source region or a drain region of each MISFET; a first insulating film and a second insulating film covering said active region, said word lines and said semiconductor regions; a first opening formed in said first insulating film such that said first opening is arranged between said word lines and extends, in said first direction, from a semiconductor region to said element isolation region; a second opening formed in said second insulating film under said first opening such that a diameter of said second opening in said first direction is less than that of said first opening, and such that said second opening reaches said semiconductor regions; a conductive material buried in said first opening and in said second opening; and a bit line formed on said first opening such that said bit line is electrically coupled to said conductive material and extends to cross said word lines, wherein one end portion of said first opening in said first direction is formed on said second opening and over said semiconductor region, and is not covered with said bit line, and wherein another end portion of said first opening in said first direction is formed on said second insulating film, over said element isolation region and under said bit line.