Patent ID: 6535899
Filing Date: 2003-03-18
Classification: G06F

Abstract:
An arithmetic unit comprising:an input register operable to store externally provides digital data as a P-bit digital data, by replacing former data with later data, and to output the stored P-bit digital data; an output register operable to receive digital data, to store the input digital data as a Q-bit digital data by replacing former data with later data, and to output the stored Q-bit digital data; and an output bit selector operable to receive the P-bit digital data from said input register as first input data and the Q-bit digital data from said output register as a second input data, to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with externally input control data, and to output the Q-bit digital data comprising values of selected bits to the output register, wherein said output bit selector is operable to use an integer â€œmâ€  as the control data, and wherein the output bit selector is operable to output a digital data comprising bits from an end to an m-th bit, which have values of bits in the same positions of the second input data, respectively, and bits of m+1-th bit and following, which have values of bits of the first input data being arranged from an end which is in the same position as the Most Significant Bit side or the Least Significant Bit side, respectively in order, as the Q-bit digital data when the control data is input.