Patent ID: 6535937
Filing Date: 2003-03-18
Classification: G06F

Abstract:
In a PCI bus system having at least one PCI bus, a method for verifying the passage of at least one write command and data sent at said PCI bus through said PCI bus system from an originating location coupled to said PCI bus, to a location substantially at the end of said PCI bus system with respect to said originating location, said PCI bus system transmitting write commands on a FIFO basis, comprising the steps of:subsequent to sending said at least one write command and data at said initiating PCI bus, sending, at said initiating PCI bus, a write command and data to a predetermined special end location address, said predetermined special end location address identifying said PCI bus system end location, said subsequently sent write command data comprising a predetermined special return address, said FIFO PCI bus system causing said at least one write command to precede said subsequently sent write command; receiving said subsequently sent write command and data addressed to said predetermined special end location address identifying said PCI bus system end location; and sensing said receipt and responding thereto, sending a return echo write command to said predetermined special return address, whereby said return echo write command verifies said passage of said at least one write command and data through said PCI bus system from said originating location to said location substantially at the end of said PCI bus system.