Patent ID: 9202578
Filing Date: 2015-12-01
Classification: G11C

Abstract:
1. A three-dimensional non-volatile memory device, comprising: a memory array comprising a plurality of vertical gate NAND memory cell strings formed in a plurality of different layers over a substrate and sharing a common set of word lines, comprising a first plurality of NAND memory cell strings forming a first erase block and second plurality of NAND memory cell strings forming a second erase block; a first source line structure and one or more first string select structures connected respectively on opposite ends of the first plurality of NAND memory cell strings, where the first source line structure controls erasure of the first erase block; a second source line structure and one or more second string select structures connected respectively on opposite ends of the second plurality of NAND memory cell strings, where the second source line structure controls erasure of the second erase block; and a source line selection circuit for selecting between the first source line structure and the second source line structure when erasing the first erase block or second erase block.