Patent ID: 6061270
Filing Date: 2000-05-09
Classification: G11C

Abstract:
A method for programming a non-volatile memory device having a memory cell array which includes a plurality of memory cells arranged in a matrix and first and second select transistors for selecting a memory cell, a plurality of bit lines connected to drains of the memory cells, and a plurality of word lines connected to control gates of the memory cells, the method comprising the steps of:(a) applying a first voltage for program inhibition to unselected bit lines and a second voltage to a gate of the first select transistor, unselected word lines, and a selected word line, to pass the first voltage without substantial loss;(b) applying the first voltage to the gate of the first select transistor to block a current path across a bit line;(c) applying a third voltage to the word line of a first unselected memory cell sharing the source of the memory cell on the selected word line and the word line of a second unselected memory cell sharing the drain of the memory cell on the selected word line, to decouple the first and second unselected memory cells from the other unselected memory cells, and applying a fourth voltage to the unselected word lines except for the word lines of the first and second unselected memory cells to capacitively couple the sources or drains of the first and second unselected memory cells to a voltage higher than the difference between a gate voltage and a threshold voltage, such that the channel of the selected memory cell is isolated from those of the other unselected memory cells; and(d) applying a program voltage to the selected word line.