Patent ID: 6728843
Filing Date: 2004-04-27
Classification: G06F

Abstract:
In a computer system comprising first and second processors, a system control unit having first and second finite state machines, and a main memory, a method of processing multiple coherent main memory accesses in parallel, the method comprising:transmitting from the first processor to the system control unit a first transaction; transmitting from the second processor to the system control unit a second transaction; decoding the first and second transactions to determine a first address and a second address, respectively; assigning the first and second transactions to a first finite state machine and a second finite state machine, respectively; retrieving a first data value corresponding to the first address from the main memory using the first finite state machine; and retrieving a second data value corresponding to the second address from the main memory using the second finite state machine, wherein the first and second data values are retrieved in parallel.