Patent ID: 6064113
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A semiconductor device package for housing an integrated circuit and having planar opposed upper and underside surfaces, the semiconductor device package comprising:a die area defined upon the upper surface and dimensioned to receive the integrated circuit;a first signal layer adjacent to the upper surface, comprising:a continuous electrically conductive ring surrounding the die area;a first set of bonding fingers arranged between the conductive ring and the die area; anda first set of signal traces connected to corresponding members of the first set of bonding fingers;a second signal layer adjacent to the underside surface, comprising:a set of bonding pads; anda second set of signal traces connected to corresponding members of the set of bonding pads; anda first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads.