Patent ID: 6098113
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A computer system, comprising:a system bus;a processor connected to said system bus;a first I/O interface circuit connected to said system bus;a second I/O interface circuit connected to said system bus;a first I/O bus connected to said first I/O interface circuit, wherein the first I/O bus has a first set of fixed addresses associated with said first I/O bus; anda second I/O bus connected to said second I/O interface circuit, wherein the second I/O bus has a second set of fixed addresses associated with said second I/O bus, and further wherein the first set of fixed addresses are the same as the second set of fixed addresses,wherein said first I/O interface circuit includes (1) means for identifying memory addresses and I/O addresses assigned to said first I/O bus by the computer system, and (2) means for translating addresses during accesses to the first set of fixed addresses associated with said first I/O bus from memory addresses and 1/O addresses assigned to said first I/O bus by the computer system into addresses of the first set of fixed addresses associated with said first I/O bus, andwherein said second I/O interface circuit includes (1) means for identifying memory addresses and I/O addresses assigned to said second I/O bus by the computer system, and (2) means for translating addresses during accesses to the second set of fixed addresses associated with said second I/O bus from memory addresses and I/O addresses assigned to said second I/O bus by the computer system into addresses of the second set of fixed addresses associated with said second I/O bus.