Patent ID: 8508285
Filing Date: 2013-08-13
Classification: H03H,H03K

Abstract:
1. An adaptive bias circuit for use with an analog delay line, the adaptive bias circuit comprising: an operational amplifier configured to receive a control signal and a feedback signal and further configured to generate a first bias signal based, at least in part on a comparison of the control signal and the feedback signal; a first transistor configured to receive the control signal at a gate of the first transistor; a second transistor having a gate coupled to a source/drain terminal of the second transistor, and wherein the source/drain of the second transistor is coupled to source/drain of the first transistor, and wherein the second transistor is configured to generate the feedback signal at the gate of the second transistor, wherein the gate of the second transistor is coupled to the operational amplifier to provide the feedback signal to the operational amplifier; and a control generator coupled to the operational amplifier and configured to generate the control signal, wherein the control generator comprises: