Patent ID: 9099346
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; an Inter-Layer Dielectric (ILD) material on the substrate; a first high-k dielectric layer and a first cap layer formed within an ILD trench in the ILD material; a second high-k dielectric layer and a second cap layer formed within the ILD trench; annealed doped source and drain regions in the substrate at sides of the ILD trench; a first metal gate within the ILD trench; and a second metal gate within the ILD trench adjacent the first metal gate; in which a dimension of the ILD trench includes the first and second metal gates separated by a P-type Metal Oxide Semiconductor (PMOS) work function layer of the first metal gate and an N-type Metal Oxide Semiconductor (NMOS) work function layer of the second metal gate; a first barrier metal layer around the PMOS work function layer; a second barrier metal layer around the NMOS work function layer; wherein the first high-k dielectric layer and the second high-k dielectric layer form a continuous substantially planar top surface that extends underneath the first metal gate, the first barrier metal layer, the second metal gate, and the second barrier metal layer, wherein the first cap layer and the second cap layer form a continuous substantially planar top surface that extends underneath the first metal gate, the first barrier metal layer, the second metal gate, and the second barrier metal layer, and wherein the first high-k dielectric layer, the second high-k dielectric layer, the first cap layer and the second cap layer substantially extend along sidewalls of the ILD trench.