Patent ID: 6259295
Filing Date: 2001-07-10
Classification: H03K,H03L

Abstract:
A method of selectively adding delay to clock signals generated by a clock generator that includes one or more delay elements capable of adding a delay to the generated clock signals, comprising the steps of:establishing a range of delay, from a minimum delay D.sub.MIN to a maximum delay D.sub.MAX, achievable using one of said delay elements, by at least:generating a first clock signal and adding thereto an amount of delay equal to a minimum delay achievable by one of said delay elements;generating a second clock signal and adding thereto an amount of delay equal to a maximum delay achievable by one of said delay elements; andcomparing said first clock signal and said second clock signal to determine the difference therebetween, thereby establishing said range of delay;generating one or more sub-delays D.sub.s of a size less than D.sub.MAX by at least:dividing said range into a predetermined number of subdivisions corresponding to the number of sub-delays D.sub.s to be created; andoutputting a sub-delay D.sub.s corresponding to each of said subdivisions; andadding one or more of said sub-delays D.sub.s to the generated clock signals by at least:receiving a control input indicating a total number of sub-delays D.sub.s to be added to the generated clock signals; andadding the total number of sub-delays D.sub.s to each generated clock signal.