Patent ID: 6518788
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A logic circuit design method for designing a logic circuit having a plurality of flip-flops, comprising:grouping the plurality of flip-flops into at least a first group of the plurality of the flip-flops operating based on a first clock, and a second group of the plurality of the flip-flops operating based on a second clock by tracing back a clock line of the logic circuit from at least one output terminal of the logic circuit and grouping one or more flip-flops of the logic circuit connected to the clock line from the output terminal until reaching a predetermined logic element or an input terminal of the logic circuit, as one group; structuring a scan path by setting the plurality of flip-flops, respectively, as scan flip-flops, scan terminals provided in each scan flip-flop being in sequence tandem-connected; and applying a scan flip-flop including a delay circuit controlled by the first clock delaying an output of the scan terminal to a scan flip-flop of the first group which is connected to a scan flip-flop of the second group on the scan path.