Patent ID: 6665766
Filing Date: 2003-12-16
Classification: G06F

Abstract:
A configuration interface arrangement for a programmable logic device (PLD) having a plurality of configuration pins, the configuration pins including one or more input/output data pins, a plurality of configuration control pins including a read/write control pin, and a configuration clock pin, the PLD having circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD, the configuration interface arrangement comprising:a register external to the PLD and including a plurality of memory elements respectively connected to the configuration pins of the PLD; a processor coupled to the register; a first set of routines executable on the processor and configured to read and write bit values from and to the register; and a second set of routines executable on the processor, a first one of the second set of routines configured to write data to the PLD via calls to the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the write protocol.