Patent ID: 6707720
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A nonvolatile semiconductor storage device comprising:a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting with each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates; a plurality of sub bit lines which extend in the first direction and are disposed in a plurality of block areas formed by dividing the memory cell array region in the first direction, each of the sub bit lines being connected with the first nonvolatile memory element of one of two the memory cells adjacent each other in the second direction and the second nonvolatile memory element of the other of the two memory cells; a plurality of main bit lines which are formed extending over the plurality of block areas arranged in the first direction, each of the main bit lines being connected in common to the plurality of sub bit lines respectively disposed in the block areas arranged in the first direction; a plurality of bit line selection switching elements which are respectively disposed at connection points between the main bit lines and the sub bit lines, and select connection or non-connection based on a control voltage; and a bit line selection driver which supplies the control voltage to the bit line selection switching elements, wherein the plurality of bit line selection switching elements include a first group of bit line selection switching elements and a second group of bit line selection switching elements, respectively connected with every second line among the sub bit lines arranged in the second direction, wherein the bit line selection driver include a first bit line selection driver which supplies a first control voltage to the first group of bit line selection switching elements, and a second bit line selection driver which supplies a second control voltage to the second group of bit line selection switching elements, wherein the first bit line selection driver supplies the first group of bit line selection switching elements with the first control voltage that is set to be lower than the second control voltage when data is read out of one of the first and second nonvolatile memory elements, and a bit line selection switching element connected to the sub bit line serving as a source of selected one of the memory cells is included in the first group of bit line selection switching elements, and wherein the second bit line selection driver supplies the second group of bit line selection switching elements with the second control voltage that is set to be lower than the first control voltage when data is read out of the other of the first and second nonvolatile memory elements, and a bit line selection switching element connected to the sub bit line serving as a source of selected one of the memory cells is included in the second group of bit line selection switching elements.