Patent ID: 6088807
Filing Date: 2000-07-11
Classification: G06F,Y02D

Abstract:
A programmed computer system including a processor coupled to external logic, the processor executing programmed instructions, the external logic including external interrupt logic that generates interrupts for input to the processor, comprising:(a) the processor including a plurality of subcircuits and clock generator circuitry coupled to supply clock signals to the plurality of subcircuits;(b) the plurality of subcircuits including a pipeline subcircuit to execute the programmed instructions, at least one of which is a halt instruction, and an interrupt handling subcircuit to handle interrupts generated by the external interrupt logic;(c) in response to the pipeline subcircuit executing the halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals at least to the pipeline subcircuit but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped;(d) in response to an interrupt generated by the external interrupt logic when the clock generator circuitry is not supplying clock signals to the pipeline subcircuit, the interrupt handling subcircuit causes the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.