Patent ID: 7430655
Filing Date: 2008-09-30
Classification: G06F

Abstract:
1. A method of executing a plurality of threads within a single programmable processor, the method comprising: storing a plurality of data elements in partitioned fields of at least one register having a register width, each of the data elements having an elemental width smaller than the register width; receiving an instruction stream for each one of the plurality of threads at an execution unit; and executing instructions from each instruction stream received at the execution unit in a multistage pipeline such that, at a given time, the multistage pipeline includes instructions from different ones of the instruction streams in different stages of the multistage pipeline, the instructions including a single instruction that specifies an operation to cause multiple instances of the operation to be performed, each instance of the operation to be performed using a different one of the plurality of data elements in partitioned fields of the at least one register to produce a catenated result.