Patent ID: 7743356
Filing Date: 2010-06-22
Classification: G06F,Y02P

Abstract:
1. A method of disposing a dummy pattern used for a semiconductor integrated circuit having a multilevel wiring structure, the method comprising the steps of: obtaining a first inter-wiring parasitic capacitance and a first wiring total parasitic capacitance for each wiring using wiring layout data of the semiconductor integrated circuit and initial dummy pattern layout data; creating a first inter-wiring parasitic capacitance data base based on the first inter-wiring parasitic capacitance; creating a first wiring total parasitic capacitance data base based on the first wiring total parasitic capacitance; performing a first dynamic simulation for identifying a first wiring affected by voltage noise, by using the first inter-wiring parasitic capacitance data base and a first wiring total parasitic capacitance data base; performing a first static simulation for identifying a second wiring affected by voltage noise, by using the first inter-wiring parasitic capacitance data base and the first wiring total parasitic capacitance data base; creating a first wiring information data base storing the results of the first dynamic simulation and the first static simulation, the results of the first dynamic simulation being information about the first wiring, and the results of the first static simulation being information about the second wiring; analyzing the capacitance of the first and second wirings based on the data in the first wiring information data base; performing an additional insertion of a dummy pattern near a third wiring in the initial dummy pattern, the third wiring being determined to be a wiring which may be affected by voltage noise based on the result of the analysis on the capacitance of the first and second wirings; and fabricating the semiconductor integrated circuit, the fabricating step including a step of making an exposure using a mask having a mask pattern corresponding to the initial dummy pattern.