Patent ID: 6608783
Filing Date: 2003-08-19
Classification: G11C

Abstract:
A memory, comprising:an array of rows and columns of memory cells; a plurality of sense amplifiers, each one having a true terminal and a compliment terminal; a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers; a plurality of word lines each one being connected to a corresponding one of the rows of memory cells; an address logic section coupled to column address signals fed to the bit lines and row address signals coupled to the word lines for producing invert/non-invert signals in accordance with the fed row and column address signals, a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.