Patent ID: 6396304
Filing Date: 2002-05-28
Classification: H03K

Abstract:
A programmable logic array integrated circuit device comprising:a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, and said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks; a plurality of inter-super-block circuits configured to convey signals between the super-blocks; a plurality of super-block-feeding circuits associated with each of said super-blocks and disposed adjacent the logic regions of the associated super-block; a first programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the inter-super-block circuits; and a second programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured for selective connection of said super-block-feeding circuits to the input terminals of the logic regions in the super-block with which said super-block-feeding circuits are associated, each such connection requiring only a single conductor and a single programmable logic connector.