Patent ID: 6683811
Filing Date: 2004-01-27
Classification: G11C

Abstract:
A nonvolatile memory apparatus comprising:a controller; and a plurality of memory devices, wherein each of said memory devices includes a plurality of memory cells and a plurality of word lines, each of said word lines couples to corresponding ones of said memory cells, wherein each of said memory cells has a threshold voltage within a plurality of threshold voltage ranges, one of which indicates an erase range and another indicates a program range, wherein said controller is capable of issuing a plurality of commands to said memory devices, which commands include a first program command and a second program command, wherein in an operation of said first program command, said memory device receives said first program command from said controller with a first data, selects one of said word lines and stores said first data to the memory cells coupled to said selected word line, and wherein in an operation of said second program command, said memory device receives said second program command from said controller with a second data, selects one of said word lines, brings said threshold voltage of the memory cells coupled to said selected word line to said erase range and stores said second data to said memory cells coupled to said selected word line.