Patent ID: 6373300
Filing Date: 2002-04-16
Classification: H03K

Abstract:
An integrated circuit, comprising:a first output driver connected to a first type of bus, wherein said first output driver specifies and supplies a termination impedance, said first output driver also specifies a first controlled pull-down impedance using a first plurality of pull-down transistors; and a second output driver connected to a second type of bus, said second output driver having the same electrical design as said first output driver, and wherein said second output driver specifies a pull-up impedance that is approximately equal to said termination impedance and said second output driver also specifies a second controlled pull-down impedance using a second plurality of pull-down transistors whereby said second controlled pull-down impedance is generated by shifting a plurality of impedance control signals by a multiplexer that receives a first and second versions of the plurality of impedance control signals.