Patent ID: 7459938
Filing Date: 2008-12-02
Classification: G06F,Y02D

Abstract:
1. An apparatus comprising: a power supply to provide a first voltage; a first Positive-channel Metal Oxide Semiconductor (PMOS) switch, the first PMOS switch including a source to couple to the first supply voltage; a first bias control to couple to a gate of the first PMOS switch; a first signal line; a portion of a transmitting device having an output; a second PMOS switch having a source to couple to a drain of the first PMOS switch, a gate input to couple to the output of the portion of the transmitting device, and a drain to couple to the first signal line; a first resistor to terminate the first signal line with reference to ground; a third PMOS switch, the third PMOS switch including a source to couple to the power source to receive a second supply voltage; a second bias control to couple to a gate of the third PMOS switch; a portion of a receiving device; a first active load having a source to couple to ground, a gate input to couple to the second supply voltage and a drain to couple to the portion of the receiving device; a second active load having a source to couple to ground, a gate input to couple to the second supply voltage and a drain to couple to the portion of the receiving device; a fourth PMOS switch having a source to couple to a drain of the third PMOS switch, a gate input to couple to the first signal line, and a drain to couple to the drain of the first active load; a fifth PMOS switch having a source to couple to the drain of the third PMOS switch, a gate input to couple to a reference voltage, and a drain to couple to the drain of the second active load; and a second resistor to terminate the first signal line with reference to ground, wherein the first and second resistors decouple the first supply voltage from the second supply, and wherein the second supply voltage is greater than the first supply voltage.