Patent ID: 6212123
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A method of controlling a memory system which comprises a plurality of memory devices coupled to a common system bus, with the system bus including a tag bus and a data bus, said method comprising the following steps:selecting at least one of the memory devices so the memory device will be in a device-enabled state where the memory device is capable of carrying out memory read operations on an array of memory cells of the memory device;after the selecting operation, transferring both a first memory address segment over the data bus and a first memory address command over the tag bus in a single transfer operations;transferring a second memory address segment over the data bus;transferring a second memory address command over the tag bus; andperforming a memory read operation on only those memory devices that are in the device-enabled state at an address which corresponds to the first and second memory address segments.