Patent ID: 7659749
Filing Date: 2010-02-09
Classification: G01R,G06F,H03M

Abstract:
1. A method for determining a value of a circuit metric under measurement within an integrated circuit, comprising: clocking a cascade of dynamic logic circuits having a delay sensitive to the value of the circuit metric under measurement with a pulse, wherein the active portion of the pulse commands the evaluate state of the dynamic logic circuits, and wherein a first one of the dynamic logic circuits has an input configured to cause an evaluation of the first one of the dynamic logic circuits when the pulse is active, wherein the cascade of dynamic logic circuits sequentially evaluates in response to the pulse; and subsequent to termination of the pulse, determining the value of the circuit metric under measurement from the position of a last one of the dynamic logic circuits that has evaluated during the pulse or the first one of the dynamic logic circuits that has not evaluated during the pulse.