Patent ID: 6292427
Filing Date: 2001-09-18
Classification: G11C

Abstract:
A compilable semiconductor memory circuit, comprising:a main array of memory cells organized into a plurality of memory banks and sub-banks;a tertiary sense amp/write driver (SA/WD) block associated with said main array of memory cells, said tertiary SA/WD being operable to effectuate data input and output (I/O) with respect to said compilable semiconductor memory circuit;at least one secondary SA/WD block coupled to said tertiary SA/WD block by a plurality of global I/O lines, said at least one secondary SA/WD block dividing said main array into said plurality of memory banks;a plurality of primary SA/WD blocks associated with said at least one secondary SA/WD block wherein said primary SA/WD blocks are coupled to said at least one secondary SA/WD by a plurality of regional I/O lines, said plurality of primary SA/WD blocks dividing a memory bank associated with said secondary SA/WD into said plurality of memory sub-banks, each of said primary SA/WD blocks being operable to drive bitline segments of a particular memory sub-bank associated therewith; anda plurality of local wordline (WL) decoders disposed in said main array of memory cells whereby said at least one secondary SA/WD block intersects said local WL decoders so as to create an area in said at least one secondary SA/WD block, wherein a regional control circuitry portion is capable of being placed within said area, said regional control circuitry portion being operable to control circuitry comprising said at least one secondary SA/WD block.