Patent ID: 6197635
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a core memory cell region and a peripheral circuitry region, the method comprising the following steps:(a) forming a first gate electrode stack in the memory cell region, the first gate electrode stack comprising, sequentially:a tunnel dielectric layer;a charge storage electrode layer;a dielectric layer;a control gate electrode layer; andan anti-reflective coating (ARC);(b) forming a second gate electrode stack in the peripheral circuitry region, the second gate electrode stack comprising:a dielectric layer;a gate electrode layer; andan ARC;(c) depositing a first layer of photoresist material over the core memory cell and peripheral circuitry regions;(d) forming a first photoresist mask on the second gate electrode stack;(e) etching the second gate electrode stack, while the first gate electrode stack is masked by the first layer of photoresist material, to form a gate electrode structure comprising, sequentially:a gate dielectric;a gate electrode; andan ARC;(f) removing the first photoresist mask from the periphery circuitry region and first layer of photoresist material from the core memory cell region;(g) forming a second photoresist layer over the core memory cell and peripheral circuitry regions;(h) forming a second photoresist mask on the first gate electrode stack;(i) etching the first gate electrode stack to form at least one stacked gate electrode structure comprising, sequentially:a tunnel dielectric;a charge storage electrode;an intergate electrode;a control gate electrode; andan ARC; and(j) implanting impurities,employing the second photoresist mask on the at least one stacked gate structure, to form shallow source/drain implants associated with each stacked gate electrode structure.