Patent ID: 6831485
Filing Date: 2004-12-14
Classification: H03D,H03L

Abstract:
A phase frequency detector with a narrow control pulse, comprising:two substantially equivalent phase latches of a narrow control pulse, each phase latch having a clock pulse input end and a signal output end; and a reset signal generating unit being connected to said phase latches, said reset signal generating unit deciding whether or not to generate a reset signal according to the logic values of said signal output ends and sending said reset signal to said phase latches; wherein each phase latch further comprises: a first inverter for inverting clock signals from said clock pulse input; a first NAND gate receiving clock signals from said clock pulse input and the inverted clock signals from said first inverter for generating voltage-level narrow control pulses; a P-MOS having a first end of fixed level signal of logic 1, a second end and a gate receiving said voltage-level narrow control pulses; an N-MOS having a first end connected to the second end of said P-MOS, a second end and a gate receiving said voltage-level narrow control pulses; a second NAND gate having a first end connected to the second end of said P-MOS, a second end connected to said reset signal, and an output; and a second inverter having an input connected to the output of said second NAND gate and on output connected to the second end of said N-MOS.