Patent ID: 7218640
Filing Date: 2007-05-15
Classification: H04L,H05K

Abstract:
1. A high speed serial fabric backplane comprising: a plurality of circuit boards interconnected to one another through a fabric of conductors, each circuit board containing a fabric interface chip (FIC); each FIC having a direct individual connection via a conductor of the fabric of conductors to all other FICs each FIC providing an interface between another conductor of the fabric of conductors on a fabric side and a local node on a local side, each FIC including a plurality of local ports to interface with a plurality of local nodes, and a plurality of destination specific fabric ports to interface with a plurality of conductors of the fabric of conductors, each FIC including a plurality of destination specific send queues and a plurality of receive queues to interface with the plurality of local ports and the plurality of destination specific fabric ports, a destination specific send queue interfacing with both a local port and a destination specific fabric port, a receive queue interfacing with both a local port and a destination specific fabric port, and each destination specific fabric port interfacing with multiple destination specific send queues.