Patent ID: 6757703
Filing Date: 2004-06-29
Classification: G06F

Abstract:
A method of adding each binary number of a plurality of first binary numbers to a corresponding binary number of a like plurality of second binary numbers, comprising the steps of:(a) providing an array processor that includes: (i) an array of content addressable memory (CAM) cells, and (ii) a first and second tags register, each said tags register including, for each row of said array, a respective tag register cell, each said tags register also including, for each row of said array, a respective logic unit operative to perform, within a single machine cycle, at least one logical operation on input including at least two operands selected from the group consisting of: (A) a bit stored in said respective tag register cell of said first tags register immediately prior to said single machine cycle, (B) a bit stored in said respective tag register cell of said second tags register immediately prior to said single machine cycle, and (C) if said single machine cycle is a compare cycle: an output of a compare operation on said each row; (b) storing the plurality of first binary numbers in a respective first at least one column of said array, each first binary number being stored in a respective row of said array; (c) storing the plurality of second binary numbers in a respective second at least one column of said array, each second binary number being stored in said respective row of the corresponding first binary number; and (d) for each said row: for each bit of the first binary number, stored in said each row, that has a corresponding bit in the second binary number stored in said each row: combining said each bit of the first binary number stored in said each row with said corresponding bit of the second binary number stored in said each row and with a respective carry bit, using said first and second registers and said respective logic units, thereby producing a respective sum bit, all within at most three said machine cycles; said combining being effected for all said binary numbers substantially simultaneously.