Patent ID: 7562315
Filing Date: 2009-07-14
Classification: G06F

Abstract:
1. A computer implemented method of applying voltage rules to at least some of a proposed semiconductor design layout, comprising: automatically determining whether an edge of an area of the layout is covered by a pseudo layer; automatically applying a first voltage dependent design rule to the area edge if the edge is not covered by the pseudo layer; automatically applying a second voltage dependent design rule to the area edge if the edge is covered by the pseudo layer; automatically applying the first voltage dependent design rule when less than all segments of the edge are covered by the pseudo layer; and at least one of automatically applying the first voltage dependent design rule when some segments of the edge are covered by a first pseudo layer and other segments of the edge are covered by a second pseudo layer, and automatically raising a voltage dependent design rule violation when some segments of the edge are covered by a first pseudo layer and other segments of the edge are covered by a second pseudo layer.