Patent ID: 7594130
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. A circuit for regulating a timing sequence of a computer, comprising: a pulse width modulation (PWM) chip comprising an input terminal configured for being connected to a first power supply, and an output terminal connected to a second power supply via a first resistor, the PWM chip capable of sending out a voltage regulation down power good (PWRGD_VRD) signal and three-phase voltage signals, upon a condition that the first power supply supplies power to the PWM chip; a north bridge configured for sending out a central processing unit (CPU) power good (PWRGD_CPU) signal according to the PWRGD_VRD signal; a converting circuit capable of transforming the three-phase voltage signals to a CPU core voltage (Vccp) signal; and a CPU arranged and configured for sending out a termination voltage power good (VTT_PWRGD) signal based on the PWRGD_CPU signal received from the north bridge, and receiving the Vccp signal from the converting circuit; wherein the logic level of the PWRGD_VRD signal is pulled up by the first resistor, causing the timing sequence of the PWRGD_CPU signal to advance, wherein the timing sequence of the VTT_PWRGD signal is advanced according to the PWRGD_CPU signal, and wherein the timing sequence of the VTT_PWRGD signal is in advance of the timing sequence of the Vccp signal.