Patent ID: 6028784
Filing Date: 2000-02-22
Classification: G11C,H01L

Abstract:
A ferroelectric memory device, comprising:a semiconductor substrate having a plurality of first substrate portions of a first conductivity type and a plurality of second substrate portions of a second conductivity type;a plurality of first memory cells formed in each first substrate portion and arranged into at least one column of first memory cells, each first memory cell including an access transistor of one conductivity type coupled to a ferroelectric capacitor;a plurality of second memory cells formed in each second substrate portion and arranged into at least one column of second memory cells, each second memory cell including an access transistor of another conductivity type, coupled to a ferroelectric capacitor; andthe first memory cells and second memory cells form rows of memory cells that include first memory cells adjacent to second memory cells, the first and second memory cells of like rows being commonly coupled to a word line.