Patent ID: 6806872
Filing Date: 2004-10-19
Classification: G09G,H04N

Abstract:
A video signal processing system provided between a host CPU and a monitor to update display setting data by said CPU, said video signal processing system comprising:first display setting registers mapped into an address space for temporarily holding various display setting data under the control of a write control signal, said display setting data being generated and outputted asynchronously with a vertical sync signal; a decoder for generating said write control signal associated with said first display setting registers for address access; a second display setting register into which an output from said first display setting registers is inputted for updating data held in said second display setting register in synchronization with a first control signal; a display output module for performing digital processing of a video display signal according to an output from said second display setting register; and a display setting start flag register in which a display setting start flag generated and outputted asynchronously with the vertical sync signal is set; wherein said first control signal is generated by using the vertical sync signal and an output from said display setting start flag register and a display setting end flag register is provided for notifying said host CPU of the completion of update of said second display setting register.