Patent ID: 6237130
Filing Date: 2001-05-22
Classification: G06F,G11C

Abstract:
A chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through appropriate buffers, the chip layout having, in combination, a chip surface carrying a plurality of closely packed DRAM banks, data ports, SRAM buffer banks, arbitration units and busses therefore, and along outer peripheral edges of the chip layout of which I/O connector pins are positioned; each of the DRAM banks being provided with its own transmit/receive SRAM buffer bank and positioned with respect to the buffer bank on the chip layout to allow the shortest length for communication with its buffer bank busses; half of the DRAM banks being distributed in spaced symmetrical rows in upper half of the chip layout, and other half of the DRAM banks being distributed in symmetrical rows in lower half of the chip layout; the data ports being positioned along vertical-horizontal cross arms dividing the chip surface into symmetrical quadrants, each quadrant containing a quadrant of the DRAMs; the transmit/receive SRAM buffer bank of each DRAM being located in the space between the DRAMs in each quadrant such that the buffer banks of adjacent DRAMS are adjacent to one another; an arbitration unit positioned adjacent each transmit/receive SRAM buffer bank for each DRAM and contiguous with the arbitration unit of the next DRAM, with data ports substantially symmetrically placed, and with each data port connected to each arbitration unit and each transmit/receive buffer bank; each data port being enabled to write into any DRAM bank by connections effected such that each data port is substantially symmetric with respect to the DRAM bank, arbitration unit and transmit/receive buffer banks and busses; andwith timing clocks centrally placed on the chip layout to minimize clock skew by symmetric clock distribution.