Patent ID: 6162672
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method for forming an integrated circuit memory device on an integrated circuit substrate, said method comprising the steps of:forming isolation regions on a semiconductor substrate wherein said isolation regions define a cell array region of said substrate, a core region of said substrate, and a peripheral circuit region of said substrate;forming at least one gate electrode on each of said cell array region, said core region, and said peripheral circuit region;doping exposed portions of said cell array and peripheral circuit regions of said substrate adjacent said gate electrodes with a first dopant;doping exposed portions of said core region of said substrate adjacent said gate electrode with a second dopant which is different from said first dopant;forming sidewall spacers adjacent said gate electrodes; anddoping exposed portions of said core and peripheral circuit regions of said substrate adjacent said spacers with said second dopant.