Patent ID: 6114200
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A method of fabricating a DRAM device, comprising:forming a transistor including a gate, a source/drain region and a word line on a silicon substrate;covering the transistor with an oxide layer,forming a contact opening in the oxide layer to expose a surface of the source/drain region;forming a conductive layer in the contact opening and covering the oxide layer;patterning the conductive layer to form at least one bottom electrode which is coupled with the source/drain region by way of the contact opening;forming a dielectric layer over a surface of the bottom electrode and the oxide layer;covering the dielectric layer with a top electrode;forming a titanium layer on an entire surface of the top electrode; andforming an interlevel dielectric layer on the titanium layer, whereby the titanium layer separates the top electrode from the interlevel dielectric layer so that the top electrode is free of any direct contact with the interlevel dielectric layer.