Patent ID: 8729709
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a multilayer wiring substrate having a first layer and a second layer, bonding electrodes arranged over a first main surface of the first layer, external terminals arranged over a second main surface of the second layer which faces a direction opposite a direction which the first main surface faces; and a semiconductor chip having an obverse surface over which electrode pads are arranged and a reverse surface opposite the obverse surface, the semiconductor chip being mounted over the first main surface of the multilayer wiring substrate such that the obverse surface of the semiconductor chip faces the first main surface of the multilayer wiring substrate, each of the electrode pads of the semiconductor chip is electrically connected to each of the bonding electrodes of the multilayer wiring substrate via a conductive material, wherein, in plan view, first bonding electrodes and second bonding electrodes located inside the first bonding electrodes among the bonding electrodes are arranged in a first region of the first main surface of the multilayer wiring substrate, wherein, in plan view, third bonding electrodes among the bonding electrodes are arranged in a second region located inside the first region, wherein all of the first bonding electrodes are signal bonding electrodes, wherein the second bonding electrodes include signal bonding electrodes, first power supply bonding electrodes, and first ground (GND) bonding electrodes, wherein the third bonding electrodes include second power supply bonding electrodes and second ground (GND) bonding electrodes, wherein, in plan view, each of first wirings drawn from each of the first bonding electrodes extends toward an outside of the multilayer wiring substrate, wherein, in plan view, each of second wirings drawn from each of the second bonding electrodes extends toward an inside of the multilayer wiring substrate, wherein each of the second wirings drawn from the signal bonding electrodes among the second bonding electrodes is electrically connected to a first wiring portion in a different layer from the first layer via a first through hole, wherein each of the second wirings drawn from the first power supply bonding electrodes among the second bonding electrodes is electrically connected to a second wiring portion in the different layer from the first layer via a second through hole, wherein each of the second wirings drawn from the first ground (GND) bonding electrodes among the second bonding electrodes is electrically connected to a third wiring portion in the different layer from the first layer via a third through hole, and wherein, in plan view, the first through hole is located between the first and the second regions and the first through hole is located inside the second and third through holes.