Patent ID: 6983348
Filing Date: 2006-01-03
Classification: G06F,Y02D

Abstract:
1. A method comprising: snooping a cache interconnect to detect a memory read request associated with a cached memory block cached in a first cache and cached in a second cache; asserting a first signal line indicative of a cache hit in response to snooping the cache interconnect if the cached memory block is in the first cache in an unmodified state; asserting a second signal line indicative of a cache hit in response to snooping the cache interconnect if the cached memory block is in the second cache in an unmodified state; and upon a cache hit to the first and second caches, supplying the cached memory block from the first cache or the second cache to a third cache based on a predetermined arbitration hierarchy, wherein the first cache, the second cache, and the cache interconnect are located in a single device and the single device is a multi-processor system.