Patent ID: 7312622
Filing Date: 2007-12-25
Classification: G01R

Abstract:
1. A semiconductor wafer, comprising: a reticle containing circuitry for a plurality of individual semiconductor chips separated by scribe regions, said reticle having at least one die location containing a wafer test probe landing cite to receive test signals to test at least a group of said individual semiconductor chips, said wafer test probe landing cite wired to said individual semiconductor chips through at least one of said scribe regions so that said test signals are transported through said at least one of said scribe regions, wherein, at least one test signal path that flows within one of said at least one scribe regions also includes: a first wiring element above said wafer's semiconductor substrate; a via coupled to said first element and that makes electrical contact to a conducting path that flows through said substrate beneath a scribe line; a second via that makes electrical contact to said conducting path on an opposite side of said scribe line from said via; and a second wiring element above said wafer's semiconductor substrate coupled to said second via.