Patent ID: 6258665
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method for manufacturing a non-volatile semiconductor memory device, comprising the steps of:forming a laminated structure composed by successively laminating a first gate insulation film and a first electrically conductive layer on a semiconductor substrate,selectively forming a plurality of opening portions in said laminated structure in order to define element formation regions in the semiconductor substrate,forming a plurality of element isolation layers in said plurality of opening portions, respectively,forming a second gate insulation film extending from an upper surface of each of said plurality of element isolation layers to a surface of said laminated structure,forming a second electrically conductive layer on said second gate insulation film,removing said second electrically conductive layer at least above an upper surface of said first electrically conductive layer, and at the same time, leaving said second electrically conductive layer above each of said plurality of element isolation layers, by retreating a portion of said second electrically conductive layer other than a region thereof in which a control gate is intended to be formed,retreating said second gate insulation. film by use, as a mask, of at least said second electrically conductive layer left above said plurality of element isolation layers, whereby at least said upper surface of said first electrically conductive layer is exposed, andretreating said first and said second electrically conductive layers and forming a plurality of laminated gate structures which each include a charge storage portion comprising said first electrically conductive layer, said control gate comprising said second electrically conductive layer, and said second gate insulation film which enables said charge storage portion and said control gate to capacitively couple to each other.