Patent ID: 6617635
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A DRAM comprising:a semiconductor substrate comprising a first insulative layer over the substrate and a second insulative layer over the first insulative layer, the first insulative layer having a plurality of first contact structures formed in their entirety therein, the first contact structures having a first conductivity type; a plurality of third contact structures formed in their entirety within the second insulative layer; a capacitor container structure, the container formed in its entirety with the second insulative layer; a second contact structure formed in its entirety within the first insulative layer and the second insulative layer, the second contact structure having a second conductivity type opposite the first type; a plurality of local interconnect structures overlying the second insulative layer; and a third insulative layer overlying the second insulative layer and the plurality of local interconnects, the third insulative layer having a plurality of fourth contact structures formed in their entirety therein, each fourth contact structure contacting one of the local interconnect structures, one of the second interconnect structures or the third interconnect structure.