Patent ID: 6245651
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of simultaneously defining a line interconnect and borderless contacts to diffusion coincident to said line interconnect, comprising:obtaining a semiconductor substrate including an array region having prepatterned gate stacks over which a first dielectric has been deposited to form a first level, each said gate stack having an insulating cap and insulating sidewalls comprising a material having a different etch selectivity than said first dielectric, said substrate further including monocrystalline regions underlying said prepatterned gate stacks;depositing a second dielectric over said array region to form a second level;lithographically defining and etching a line interconnect opening in said second level;continuing etching down to said monocrystalline regions to form openings in said first level which are borderless to said prepatterned gate stacks; anddepositing a conductor in said openings to form said borderless contacts to diffusion (CD) and said line interconnect.