Patent ID: 8685807
Filing Date: 2014-04-01
Classification: H01L

Abstract:
1. A method, comprising: forming a dummy gate electrode above a semiconductor substrate; forming sidewall spacers adjacent said dummy gate electrode; forming a layer of insulating material above said substrate and adjacent said sidewall spacers; performing at least one etching process to remove at least said dummy gate electrode and thereby define a space between said spacers; forming high-k layer of insulting material in said space between said spacers; forming a work function metal layer in said space between said spacers and above said high-k layer of insulating material; forming a sacrificial gate electrode material within said space defined by said spacers and above said work function metal layer; forming at least one conductive contact opening in said layer of insulating material; after forming said at least one conductive contact opening, removing said sacrificial gate electrode material to thereby define a gate electrode opening; and performing a common deposition process to fill said conductive contact opening and said gate electrode opening with a conductive fill material.