Patent ID: 6414525
Filing Date: 2002-07-02
Classification: H03K

Abstract:
An impedance matching method for a semiconductor system comprising a plurality of semiconductor chips connected to one another through a transmission path, each semiconductor chip comprising an I/O interface circuit including a push-pull output buffer having a first driving element connected between an I/O node connected to said transmission path and a first potential node and a second driving element connected between a second potential node and said I/O node, a first potential being applied to the first potential node, a second potential being applied to the second potential node,the method comprising the steps of: (a) adjusting an impedance value of the first driving element in said push-pull output buffer of each semiconductor chip; (b) setting one of said plurality of semiconductor chips to output mode for outputting a signal to said transmission path and setting the other semiconductor chips to input mode for inputting a signal from said transmission path; (c) adjusting an impedance value of the second driving element in said push-pull output buffer of one of said plurality of semiconductor chips; and (d) repeating the steps (b) and (c) for all of said plurality of semiconductor chips.