Patent ID: 9088293
Filing Date: 2015-07-21
Classification: H03M

Abstract:
1. An apparatus for calibration of an analog-to-digital converter (ADC) including a plurality of sub-ADCs comprising: a reference sub-ADC among the plurality of sub-ADCs; a calibration-signal generator configured to provide a calibration signal at an input node of each sub-ADC of the plurality of sub-ADCs; and a gain-correction path configured to generate, for each sub-ADC of the plurality of sub-ADCs, other than the reference sub-ADC, a corresponding error signal based on output signals of the sub-ADC and the reference sub-ADC, wherein each sub-ADC is configured to be calibrated based on the corresponding error signal, the ADC comprises a time-interleaved ADC that includes the plurality of sub-ADCs, and the reference sub-ADC is configured to have a lowest relative offset among the plurality of sub-ADCs.