Patent ID: 6477186
Filing Date: 2002-11-05
Classification: H04J

Abstract:
A multiplexer for converting parallel data signals of M bits (M being an integer larger than 1) into a serial data signal of M bits in synchronization with a clock signal, comprising:a signal generating circuit for generating control signals of M phases each having a period M times larger than that of said clock signal, and being shifted in phase from each other by (1/M) of said period; a first holding circuit for temporarily holding said control signals of M phases issued from said signal generating circuit, and issuing said control signals in synchronization with said clock signal; a select circuit for successively selecting said parallel data signals of M bits bit by bit in response to the control signals of M phases issued from said first holding circuit, and producing said M-bit serial data signal by passing each of the selected data signals; and a second holding circuit for temporarily holding each of the data signals issued from said select circuit, and thereafter issuing said data signal in synchronization with said clock signal.