Patent ID: 6130550
Filing Date: 2000-10-10
Classification: H03K

Abstract:
An apparatus for an integrated field programmable gate array having a core array of programmable logic circuits comprising:first and second pluralities of programmable I/O cells any one of which can be programmed to act as a data input or data output port for an integrated circuit, each I/O cell having a D.sub.o input for receiving a data output signal, an OE output enable input for receiving a signal which enables said I/O cell to drive any signal received at said D.sub.o input to an external pin and a CKE clock enable input for receiving a clock enable signal, and having a D.sub.in output at which a data input signal is presented if said I/O cell is programmed as a data input and having at least one programming signal input;means coupled to the at least one programming signal input of said first and second pluralities of programmable I/O cells for supplying one or more programming signals that define whether each said I/O cell acts as a data input or a data output or both;a first plurality of intermediary O.sub.-- line conductors;a second plurality of intermediary O.sub.-- line conductors;a plurality of intermediary I.sub.-- line conductors;first, second and third active repeater type multiplexers associated with each I/O cell in said first plurality of I/O cells and having first, second and third outputs coupled to said D.sub.o, OE and CKE inputs, respectively, of the associated I/O cell, and having a plurality of inputs each of which is connected to a selected one or more of said first plurality of O.sub.-- line conductors, said first, second and third multiplexers associated with each I/O cell in said first plurality of I/O cells having select inputs for receiving signals which control which input of each multiplexer is coupled to its output, and wherein each active repeater type multiplexer is implemented with switching transistors which are coupled to an external power supply when operational and programmed to select an input for coupling to said output of said multiplexer so as to use the large current drive and current sink capacity of the external power supply to charge or discharge parasitic capacitance loading said output of said multiplexer in accordance with the logic transitions of the input signal of the selected input to be coupled to said output;fourth, fifth and sixth active repeater type multiplexers associated with each I/O cell in said second plurality of I/O cells and having first, second and third outputs coupled to said D.sub.o, OE and CKE inputs, respectively, of the associated I/O cell, and having a plurality of inputs each of which is connected to a selected one or more of said second plurality of O.sub.-- line conductors, said fourth, fifth and sixth multiplexers associated with each I/O cell in said second plurality of I/O cells having select inputs for receiving signals which control which input of each multiplexer is coupled to its output, said fourth, fifth and sixth active repeaters having the same structure as said first, second and third multiplexers;means coupled to said select inputs of said first, second, third, fourth, fifth and sixth multiplexers for providing programmable signals to said select inputs to control which input of each multiplexer is coupled to that multiplexer's output;a first plurality of active repeaters in the form of tri-state drivers programmably coupling said D.sub.in output of each I/O cell to a selected one or more of said plurality of intermediary I.sub.-- lines;a plurality of output lines from each of a plurality of buses comprised of conductors that pass through said array of programmable logic circuits carrying output signals therefrom;a plurality of input lines in each of said plurality of buses for carrying input signals to said array of logic circuitsa second plurality of active repeaters in the form of tri-state drivers programmably coupling said plurality of output lines from said buses to selected ones of said first and second pluralities of intermediary O.sub.-- lines; anda third plurality of active repeaters in the form of tri-state drivers programmably coupling said plurality of input lines in said buses to selected ones of said plurality of intermediary I.sub.-- lines;and wherein each said active repeater is implemented with one or more switching transistors which are coupled to an external power supply when operational and programmed to be in an enabled state so as to regenerate on an output conductor an input signal appearing at an input of said active repeater by using the large current drive and current sink capacity of the external power supply to selectively charge or discharge parasitic capacitance loading said output of said active repeater in accordance with the logic transitions of the input signal so as to speed up the rise and fall times of the logic transitions created on said output conductor relative to corresponding logic transitions of the input signal, and wherein each active repeater includes programming means for controlling whether said active repeater is enabled or disabled.