Patent ID: 6658556
Filing Date: 2003-12-02
Classification: G06F

Abstract:
A processor, comprising:execution resources including a plurality of load-store units, wherein each load-store unit among said plurality of load-store units processes only those memory access instructions that access data having associated target addresses within a respective one of a plurality of disjoint subsets of an address space; data address storage; and an instruction sequencing unit, coupled to said data storage and said execution resources, that supplies instructions within said data storage to said plurality of load-store units, said instruction sequencing unit including a dispatch unit that hashes a target address indicated by a memory access instruction to determine a particular subset among said plurality of disjoint subsets of address space to which said target address belongs and that dispatches the memory access instruction for execution to a particular load-store unit among said plurality of load-store units that processes memory access instructions having target addresses belonging to said particular subset.