Patent ID: 6856270
Filing Date: 2005-02-15
Classification: G06F

Abstract:
1. A pipeline array comprising: a pipeline clock line for receiving a series of Pipeline Clock Pulses (PCP)s; a register having a register clock input, a register data input and a register data output; N Pulse Triggered Latch (PTL) stages with each PTL including N Latch Pulse Generators (LPG)s and N parallel sets of latches with a parallel set of single latches in each stage, where N is a positive integer, including at least a first PTL stage, a penultimate PTL stage, and a last PTL stage; each PTL stage including: each latch data output being connected in series to a latch data input of a successive PTL stage except that the latch data output of the last PTL stage is connected as a pipeline data output, with the latch data input of the first PTL stage being connected to the register data output; the pipeline clock line being connected to the register clock input and the pipeline clock pulse input of the LPG of the last PTL stage; and N−1 time delay units, with each of the time delay units being connected to the pulse input of an LPG except for the last PTL stage; whereby the time delay units activate the LPGs in a bucket brigade fashion.