Patent ID: 6660580
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method of manufacturing a capacitor of an integrated circuit device comprising:forming a first insulation layer on a semiconductor substrate; forming a buried contact hole in the first insulation layer; forming a buried contact plug in the buried contact hole to fill a portion of the buried contact hole; forming a diffusion barrier layer on the first insulation layer, on the buried contact plug and on an inner side surface of an upper portion of the buried contact hole above the buried contact plug, the diffusion barrier layer having a uniform thickness along a surface profile of the buried contact hole; forming a second insulation layer on the diffusion barrier layer; etching the second insulation layer and the diffusion barrier layer to form a through hole to expose a top surface of the buried contact plug and a diffusion barrier spacer on an inner side surface of the upper portion of the buried contact hole, the through hole having a diameter that is larger than that of the buried contact hole; forming a barrier layer on a bottom and a side surface of the through hole along a surface profile of the through hole; forming a lower electrode on the barrier layer; forming a dielectric layer on the lower electrode and an upper surface of the second insulation layer; heat treating the dielectric layer in an oxygen atmosphere to crystallize the dielectric layer; and forming an upper electrode on the dielectric layer.