Patent ID: 7187217
Filing Date: 2007-03-06
Classification: H03K

Abstract:
1. A trigger signal generation circuit, which generates a trigger signal which frequency-divides a reference clock signal, comprising: first through Pth (where P is an integer) sub-counters, provided in parallel, which count clock pulses up to at least a prescribed number M+1 and provided in parallel; and, a synthesis circuit, which synthesizes first through Pth output signals generated when said sub-counters count to said number M and generate said trigger signal; and wherein said sub-counters are supplied with first through Pth clock signals respectively, the first through Pth clock signals having a same period as said reference clock and phases shifted in sequence by 1/P of said reference clock period; an Nth (where N is an arbitrary number from 1 to P) sub-counter among said first through Pth sub-counters initializes at least said (N+1)th sub-counter excluding said Nth sub-counter, when said Nth sub-counter ends counting to said number M, and after said initialization, said (N+1)th sub-counter counts said number M pulses of the (N+1)th clock signal with phase lager by 1/P of the reference clock period than said Nth clock signal, and said (N+1)th sub-counter initializes the next-stage sub-counter when ends counting to said number M; and said trigger signal is generated upon each (M+1/P)th period of said reference clock signal.