Patent ID: 9224796
Filing Date: 2015-12-29
Classification: H01G,H01L

Abstract:
1. A process for producing at least one through-silicon via and at least one through-silicon capacitor in a substrate, comprising: forming, in the substrate from a first side, at least one first blind orifice intended for forming the capacitor and at least one second blind orifice intended for forming the through-silicon via; forming a first electrode region of said capacitor at least on the side walls and on the bottom wall of the first blind orifice, said forming said first electrode region including forming an initial electrically conductive layer in said first blind orifice but not in the second blind orifice; filling the first blind orifice and the second blind orifice by forming in the first orifice a multilayer comprising at least one dielectric layer and an additional electrically conductive layer on said dielectric layer, the additional electrically conductive layer forming a second electrode region of said capacitor, and by forming in the second orifice a multilayer comprising at least the additional electrically conductive layer in order to form at least one part of said through via; thinning the substrate from a second side until the first and second blind orifices are exposed and the first electrode region in the first orifice is reached and the additional electrically conductive layer in the second orifice is reached allowing the through-silicon via to be formed; and producing a first electrically conductive zone making contact with said first electrode region and a second electrically conductive zone making contact with said through-silicon via.