Patent ID: 8436408
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. An integrated circuit comprising: a circuit module having a plurality of active components coupled between a pair of supply nodes; and a capacitive decoupling module coupled to the circuit module, the capacitive decoupling module comprising a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between said supply nodes is divided across said plurality of MiM capacitors, thereby reducing voltage stress on said capacitors, wherein the plurality of MiM capacitors comprises at least first and second MiM capacitors formed in a dielectric layer disposed between a device substrate and a metal interconnect layer formed thereover, the metal interconnect layer having interconnects corresponding to said supply nodes, and wherein a bottom electrode of the first MiM capacitor is coupled to the metal interconnect layer through a first lateral conductor formed on the device substrate, and a bottom electrode of the second MiM capacitor is coupled to the metal interconnect layer through a second lateral conductor formed on the device substrate, wherein the first and second lateral conductors are insulated from one another.