Patent ID: 7793028
Filing Date: 2010-09-07
Classification: G06F,G11B,G11C

Abstract:
1. An interface that supports a signaling protocol between a first hardware component and a second hardware component, the interface comprising: a first pin to provide a write clock signal sourced from the first hardware component to the second hardware component during a write operation; a second pin to receive a read clock signal sourced from the second hardware component during a read operation; and a third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the write operation and the read operation, the first gate control signal being asserted during both the write operation and the read operation, wherein the first gate control signal is gated based on the write clock signal or the read clock signal.