Patent ID: 7509619
Filing Date: 2009-03-24
Classification: G06F

Abstract:
1. A method of creating a multi-staged circuit design from a high level language (HLL) program specifying an algorithm to be implemented as a circuit, said method comprising: generating a language independent model (LIM) from the HLL program by, at least in part, representing selected instructions of the HLL program as state resources within the LIM; determining a first and last access to each of the plurality of state resources within the LIM; identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by a first and last access to one of the plurality of state resources; including within the LIM, a stall point for each of the first accesses, wherein the stall point represents stall circuitry, wherein a last access is disposed within a body of a loop construct, said including step further comprising modifying the loop construct to execute the body one less time and adding a separate instance of the body of the loop construct, such that a stall release signal is defined by the last access within the separate instance of the body; and translating the LIM into a scheduled hardware description specifying the multi-staged circuit design specifying stall circuitry according to the stall points.