Patent ID: 6451630
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method for manufacturing a thin film transistor, comprising the steps of:forming a channel region on a surface of a substrate; depositing an insulating layer on the surface of the substrate to cover the channel region; patterning the insulating layer such that a portion of the channel region is exposed; depositing a silicon layer on the insulating layer; depositing a metal layer on the silicon layer; etching the silicon layer and the metal layer at the same time to define a source electrode, a drain electrode and a gate electrode; doping positive ions on a portion corresponding to an exposed portion of channel in a MOS circuit; depositing an intermediate insulating layer on the metal layer to cover the source electrode, the drain electrode and the gate electrode; patterning the intermediate insulating layer to form a plurality of contact holes at regions where a pixel electrode and a wire are to be formed; and depositing an electrode material on the intermediate insulating layer; and patterning the electrode material to define a pixel electrode section and a wire section.