Patent ID: 6469399
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A semiconductor package, comprising:a substrate panel extending continuously substantially throughout its entire area without interruption except for a single hole in a central region of the substrate panel, the substrate panel having an upper side and a underside communicated by the hole, the substrate panel further having a plurality of first leads formed thereon; a chip mounted to the underside of the substrate panel, the chip having a plurality of second leads formed thereon; a plurality of wires interconnecting the first leads of the substrate panel with the second leads of the chip; an upper package encapsulant formed on the upper side of the substrate panel, the upper package encapsulant being formed by means of filling molten liquid plastic material into an upper mold through an upper mold gate thereof, said upper mold being placed on the upper side of the substrate panel; and a lower package encapsulant formed on the underside of the substrate panel, the lower package encapsulant being formed by means of filling molten liquid plastic material into a lower mold through a lower mold gate thereof, said lower mold being placed on the underside of the substrate panel; wherein the upper package encapsulant and the lower package encapsulant are formed simultaneously for sealing the chip completely.