Patent ID: 6806537
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A semiconductor device comprising:an SOI substrate having a multi-layer structure including a semiconductor substrate, an insulation layer and a semiconductor layer stacked in the order named; a first insulation film formed on a main surface of said semiconductor layer; a gate electrode formed on said first insulation film; a pair of second insulation films having respective inner side surfaces in contact with side surfaces of said gate electrode and respective outer side surfaces out of contact with said side surfaces of said gate electrode, with said gate electrode disposed between said pair of second insulation films; a pair of third insulation films formed on said main surface of said semiconductor layer, with said first insulation film therebetween, and having respective inner side surfaces in contact with said outer side surfaces of said second insulation films and respective outer side surfaces out of contact with said outer side surfaces of said second insulation films, with said gate electrode and said second insulation films disposed between said pair of third insulation films; a body region formed in said semiconductor layer under said gate electrode; and a pair of source/drain regions formed in said semiconductor layer, with said body region disposed between said pair of source/drain regions, said source/drain regions having respective extensions extending from under said outer side surfaces of said second insulation films toward said body region in said main surface of said semiconductor layer, wherein a lifetime killer is formed in said main surface of said semiconductor layer, wherein said third insulation films are made of silicon nitride, and wherein said third insulation films are formed directly on said main surface of said semiconductor layer without said first insulation film therebetween.