Patent ID: 7790524
Filing Date: 2010-09-07
Classification: H01L

Abstract:
1. A method of fabricating a device structure for a non-volatile random access memory from a semiconductor layer carried on an insulating layer, the method comprising: forming first, second, and third semiconductor bodies from the semiconductor layer and with a juxtaposed relationship in which the second semiconductor body is disposed between the first and third semiconductor bodies; doping the first semiconductor body to form a source and a drain; forming a first dielectric layer between the first semiconductor body and the second semiconductor body; forming a second dielectric layer between the second semiconductor body and the third semiconductor body; after the first and second dielectric layers are formed, masking a first portion of the second semiconductor body and a first portion of the third semiconductor body; and after the first portion of the second semiconductor body and the first portion of the third semiconductor body are masked, concurrently removing a second portion of the second semiconductor body and a second portion of the third semiconductor body with a selective etching process, wherein the second semiconductor body and the third semiconductor body respectively define a floating gate electrode and a control gate electrode that cooperate to control carrier flow in a channel in the first semiconductor body between the source and the drain.