Patent ID: 7904639
Filing Date: 2011-03-08
Classification: G06F,G11C,Y02D

Abstract:
1. A system comprising: a memory system including a plurality of memory devices for storing data; a processor for managing a request for access to the memory system; and a controller for translating the request from the processor to a plurality of separatable commands of a modular structure interpretable by at least one of the plurality of memory devices, the plurality of separatable commands comprising an address identifier for the at least one of the plurality of memory devices and a command identifier representing an operation to be performed by the at least one of the plurality of memory devices, the plurality of memory devices and the controller being in a series-connection for communication, the at least one of the plurality of memory devices including at least two memory banks, the address identifier including a device address for the at least one of the plurality of memory devices and a bank address for at least one of the at least two memory banks, the controller being configured to produce the plurality of separatable commands for each of the at least two memory banks to interleave issuance of the plurality of separatable commands, so that the at least two memory banks are concurrently processing the issued plurality of separatable commands.