Patent ID: 7145810
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A multiplexer circuit for use in a memory, comprising: a multiplexer circuit output; a first bit line circuit coupled to receive a first bit line of a memory and coupled to receive a select signal, the first bit line circuit having an output coupled to the multiplexer circuit output, the first bit line circuit selectively providing, based at least partially upon the first select signal, data from the first bit line to the multiplexer circuit output; wherein the first bit line circuit comprises a first precharge control circuit, which receives a first input signal derived from a read enable signal, and generates therefrom a first precharge control signal, the first precharge control signal being timed such that it causes a first precharge circuit to stop precharging the first bit line before any word line of the memory is activated; and a second bit line circuit coupled to receive a second bit line of a memory and coupled to receive a complement of the select signal, the second bit line circuit having an output coupled to the multiplexer circuit output, the second bit line circuit selectively providing, based at least partially upon the complement of the select signal, data from the second bit line to the multiplexer circuit output; wherein the second bit line circuit comprises a second precharge control circuit, which receives a second input signal derived from the read enable signal, and generates therefrom a second precharge control signal, the second precharge control signal being timed such that it causes a second precharge circuit to stop precharging the second bit line before any word line of the memory is activated; and wherein the first and second bit line circuits operate such that data from only one of the first and second bit lines is provided to the multiplexer circuit output at any given time.