Patent ID: 9106209
Filing Date: 2015-08-11
Classification: G09G,H03K

Abstract:
1. A gate driving unit, comprising: N stage circuit units driven by receiving a start signal and first to fourth clock signals, wherein each stage circuit unit is configured to output gate signals by at least one of the first to fourth clock signals, and to receive gate signals output from an (N+3)th stage circuit unit to thus use as reset signals, each stage circuit unit including a first stage circuit sub-unit and a second stage circuit sub-unit, wherein the first stage circuit sub-unit includes a first pull-up transistor having a source connected to a first clock signal, a drain connected to a first output terminal, and a pull-down transistor having a drain connected to the first output terminal, and a source connected to a second voltage, wherein the second stage circuit sub-unit includes a second pull-up transistor having a source connected to a second clock signal, and a drain connected to a second output terminal, and a pull-down transistor having a drain connected to the second output terminal, and a source connected to the second voltage, and wherein a gate of the pull-down transistor of the first stage circuit sub-unit is directly connected to a gate of the pull-down transistor of the second stage circuit sub-unit.