Patent ID: 6115801
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A circuit for a semiconductor integrated storage device, comprising:a first enable terminal for enabling said semiconductor integrated storage device;a second enable terminal for enabling output terminals of said semiconductor integrated storage device;a first number of address terminals for inputting an external address formed of a corresponding first number of bits;a plurality of data storage elements which are addressable by an internal address formed of a second number of bits, larger than said first number of bits; andaddress storage elements having input terminals which are coupleable to said first enable terminal for storing a value corresponding to said first enable terminal in a first of said address storage elements, an output of said first address storage element forming one or more additional address bits, said internal address comprises said external address and said one or more additional address bits, said value corresponding to said first enable terminal appears on said output of said first address storage element upon a first signal transition appearing on one of said first and said second enable terminals to a disabling state, said first address storage element latching said value corresponding to said first enable terminal upon a second signal transition appearing on said second enabling terminal to an enabling state.