Patent ID: 6387744
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, comprising:forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type; introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said semiconductor substrate; introducing a second impurity in said first area by using said first mask to form a second semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said second semiconductor region; selectively introducing a third impurity in a second area within said first area to form a third semiconductor region, serving as a well region, of said second conductivity type in said second semiconductor region; selectively introducing a fourth impurity in a third area within said first area to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said second semiconductor region; forming a first MISFET on said third semiconductor region; and forming a second MISFET on said fourth semiconductor region.