Patent ID: 8705402
Filing Date: 2014-04-22
Classification: H04L

Abstract:
1. An apparatus, comprising: a data extraction circuit configured to receive an input frame and extract first data included in the input frame; buffer circuitry which is coupled to the data extraction circuit, the buffer circuitry receiving the first data from the data extraction circuit; a processor circuit coupled to the data extraction circuit and the buffer circuitry, such that the processor circuit generates justification event bits based on an amount of first data included in the input frame, the processor circuit also being configured to add justification opportunity bytes to the first data, the justification event bits indicating whether the justification opportunity bytes include a portion of the first data or null bits, such that a frequency associated with the first data is a predetermined frequency; and a multiplexer coupled to the buffer circuitry, the multiplexer being configured to multiplex the first data with second data and supply an output frame including the first data, second data, and the justification opportunity bytes, wherein the input frame is a first input frame, and the data extraction circuit is a first data extraction circuit, the apparatus further including: