Patent ID: 6452219
Filing Date: 2002-09-17
Classification: H01L,Y10S

Abstract:
An insulated gate bipolar transistor implemented in a diced semiconductor chip, the transistor comprising:a first layer made of a first conductivity type semiconductor; a second layer made of a second conductivity type semiconductor and disposed over and spanning an entire area of a first surface of the first layer; a base area made of the first conductivity type semiconductor and formed in the second layer so that a first pn junction is defined between the second layer and the base area; a source area made of the second conductivity type semiconductor, formed in the base area so that a second pn junction defined with the base area is spaced from the first pn junction, a surface of the base area between the first and second pn junctions being used for a channel area; an insulated gate electrode disposed at least over the channel area; a source electrode electrically connected to the source area; a buffer layer made of the second conductivity type semiconductor and disposed between the first and the second layers except at least at all outer edges of diced cross-sections of the chip, the buffer layer having an impurity concentration higher than that of the second layer; and a drain electrode disposed on a second surface of the first layer on an opposite side of the second layer as the first surface, so that a current flows between the drain electrode and the source electrode through the first layer and the buffer layer, wherein the first surface of the first layer contacts one of the second layer and the buffer layer to form a third pn junction extending to both edges of the diced cross-section of the chip; and wherein the third pn junction includes end portions exposed at both edges of the diced cross-section of the chip, the end portions of the third pn junction being formed by the first layer and the second layer.