Patent ID: 9184755
Filing Date: 2015-11-10
Classification: H01L,H03M

Abstract:
1. A semiconductor device comprising: a sample-and-hold circuit that samples a voltage level of an input voltage according to a sampling clock signal, outputs one of differential voltages corresponding to the voltage level of the input voltage to a first comparison line, and outputs the other of the differential voltages to a second comparison line; a comparator that outputs an output value indicating a high level or a low level according to a voltage difference between the first comparison line and the second comparison line; a digital-to-analog conversion circuit that changes voltages of the first comparison line and the second comparison line according to the output value; a successive approximation control circuit that controls the sample-and-hold circuit, the comparator, and the digital-to-analog conversion circuit according to a preset successive approximation sequence, and outputs a number of output values corresponding to the number of bits of a conversion result output value; and a switch circuit that is provided between the first comparison line and the second comparison line, a conductive state and a cut-off state of the switch circuit being switched by the successive approximation control circuit, wherein upon acquisition of the output value of all bits of the conversion result output value, the successive approximation control circuit brings the switch circuit into the conductive state, and outputs an offset determination signal for adjusting an input offset voltage of the comparator according to the output value during a period in which the switch circuit is in the conductive state, and the comparator changes the input offset voltage according to an offset control value generated according to a logic level of the offset determination signal.