Patent ID: 7373570
Filing Date: 2008-05-13
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising a first circuit block, a second circuit block and a plurality of scan separators transferring, in ordinary operation, signals between said first and second circuit blocks and isolating, in a testing operation, said first and second circuit blocks from each other, wherein each of said plurality of scan separators is provided for two of the signals transferred from said first circuit block to said second circuit block, and interconnected in cascaded stages, each of said plurality of scan separators comprising: a first selector for selecting one of the two signals output from said first circuit block in response to an input selector signal; a second selector for selecting scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes when receiving a scan control signal, said second selector being adapted for selecting an output signal of said first selector when not receiving the scan control signal; a flip flop for holding an output signal of said second selector to output the output signal in a form of scan data to outside or to one of said plurality of scan separators which follows in the cascaded stages, and for sending the output signal to said first selector as the input selector signal in response to a clock signal; and a third selector, which receives one of the two signals and the output signal of said flip flop as inputs, for selecting said one of the two signals or the output signal of said flip flop in response to an output selector signal, and for supplying the selected signal to said second circuit block.