Patent ID: 6580119
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A stacked gate field effect transistor device comprising:a semiconductor substrate having an active region defined therein; a tunneling dielectric layer formed upon the active region of the semiconductor substrate; a floating gate electrode formed upon the tunneling dielectric layer; an inter-gate electrode dielectric layer formed upon the floating gate electrode; a control gate electrode formed upon the inter-gate electrode dielectric layer; and a pair of source/drain regions formed adjacent a pair of opposite edges of the floating gate electrode, wherein the floating gate electrode is formed with a pointed edge tip at its outer sidewall; the floating gate electrode is formed with a pointed linear recess centered within its linewidth; and the pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.