Patent ID: 7852391
Filing Date: 2010-12-14
Classification: H04N

Abstract:
1. An imaging system generating increased pixel readout by compensating for failed read out circuits by employing redundant readout circuits, said system comprising: a focal plane imaging array (FPA); said FPA comprising a plurality of detector columns; a plurality of primary readout circuits (ROCs) that receive and process image data from said plurality of detector columns of said FPA, wherein number of said plurality of detector columns and number of said plurality of primary readout circuits is equal; a plurality of said redundant ROCs replacing one or more of said plurality of primary ROCs if one or more of said plurality of primary ROCs fails; at least one column steering module consisting of a plurality of column steering sub-modules, each said column steering sub-module comprising, input from said plurality of detector columns, a selected detector column output, a switch bank comprising switches directing output from said plurality of detector columns to readout circuits by said selected detector column output, a 3 to 8 decoder coupled to said switch bank by switch select lines, said 3 to 8 decoder receiving a decoder enable signal, a 3-bit latch receiving a latch enable signal from a sub-module block of horizontal address register, said 3 bit latch also receiving a 3-bit column select code; wherein said plurality of detector columns is connected to said switches of said switch bank in a staggered fashion, wherein said staggered fashion denotes grouped advancement of detector column busses connected to said column steering sub-modules, whereby any one bus of said plurality of detector columns is selectively steered to any one of seven ROCs connected to said plurality of detector columns by said switch bank of corresponding said column steering sub-module, and whereby said defective ROCs will be unused by said detector columns; wherein each said sub-module block of horizontal address register is one unit of a shift register whereby control data is loaded and then clocked through said shift register to enable each of pairs of said column steering sub-modules and said ROCs to carry out detector column readout; wherein said 3-bit latch translates a 3-bit column select code into a switch select enable signal, wherein most significant bit (MSB) of said 3-bit column select code denotes shift direction and least significant bits (LSBs) indicate shift magnitude relative to a center position, and wherein only one of said switch select lines is active at a time; at least one column steering control data bus directing data of said at least one column steering module, said at least one column steering control data bus comprising at least clock/enable code lines of said sub-module block of horizontal address register; wherein said clock/enable code lines provide a double clock cycle whereby an enable code sequence is advanced through blocks of said shift registers, thereby sequentially enabling each said column steering sub-module, so that detector column readout takes place; at least one switch select circuit controlling operation of said switches; at least one ROC diagnostic processor that assesses status of pairs of said sub-modules and said ROCs, determining non-functionality of operation of connective wiring to and operation of said ROCs indicated by non-compliant output; at least one redundant readout circuit (ROC) control processor that controls when a redundant readout circuit replaces said primary readout circuit; at least one redundant readout circuit controller wherein said redundant readout circuit controller switchably couples said image data from said FPA from said primary readout circuit to said redundant readout circuit; and an image processor receiving readouts from said rocs that are enabled, to generate an image of said increased pixel readout.