Patent ID: 6096600
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A method of forming a capacitative section of a semiconductor device comprising:forming a stacked layer structure including a lower electrode layer having a first impurity concentration provided on an underlay, a dielectric layer provided on said lower electrode layer, and an upper electrode layer comprising an impurity-doped layer having a second impurity concentration which is lower than the first impurity concentration and a metallic layer arranged in sequence on said dielectric layer; anddoping said metallic layer with a same impurity as an impurity in said impurity-doped layer prior to heat treatment of said stacked layer structure, to raise the second impurity concentration to a same level as the first impurity concentration and provide an equilibrium condition between an impurity concentration of said metallic layer and the impurity concentration of the impurity-doped layer.