Patent ID: 6859406
Filing Date: 2005-02-22
Classification: G11C

Abstract:
1. A dynamic random access memory (DRAM) having a shared sense amplifier organization concept, comprising: sense amplifiers disposed in sense amplifier strips; cell arrays subdivided into cell blocks having memory cells and bit lines connected as bit line pairs from two adjacent said cell blocks in each case to a common sense amplifier of said sense amplifiers, said sense amplifiers being disposed between said cell blocks, said bit lines having first ends and second ends connected to said sense amplifiers; and bit line switches disposed in said sense amplifier strips, disposed between said cell blocks, between in each case two adjacent said sense amplifiers, said bit line switches momentarily connecting said first ends, not connected to said sense amplifiers, of two of said bit line pairs from adjacent said cell blocks during a precharge phase of a bit line pair activated directly beforehand, the precharge phase taking place at a start of a charge equalization phase.