Patent ID: 7233270
Filing Date: 2007-06-19
Classification: H03M

Abstract:
1. A receiver comprising: a front-end circuit for receiving and processing an incoming signal to generate an analog input signal; a time-interleaved parallel analog-to-digital converter (ADC) circuit, coupled to the front-end circuit, for converting the analog input signal into a digital input signal, the time-interleaved parallel ADC circuit comprising a plurality of ADCs driven by a plurality of clock signals of different phases, respectively; an equalizing circuit, coupled to the time-interleaved parallel ADC circuit, for equalizing the digital input signal to generate a plurality of soft decision values; a decision circuit, coupled to the equalizing circuit, for generating a plurality of hard decision values according to the soft decision values; a calculating circuit, coupled to the equalizing circuit and the decision circuit, comprising: a compensation circuit, coupled to the calculating circuit, for compensating the time-interleaved parallel ADC circuit according to at least part of the two or more parallel paths of first error estimates.