Patent ID: 9087160
Filing Date: 2015-07-21
Classification: G06F,G11C,H01L,H05K

Abstract:
1. An electronic device comprising: a mounting board; a first semiconductor device mounted over the mounting board, the first semiconductor device including a first wiring substrate, a first semiconductor chip mounted over a chip mounting surface of the first wiring substrate, and a plurality of external terminals electrically connected with the first semiconductor chip and formed on a mounting face opposite to the chip mounting surface of the first wiring substrate; and a second semiconductor device mounted over the mounting board, and electrically connected with the first semiconductor device, the second semiconductor device including a second wiring substrate, a second semiconductor chip mounted over a chip mounting surface of the second wiring substrate, and a plurality of external terminals electrically connected with the first semiconductor device and formed on a mounting face opposite to the chip mounting surface of the second wiring substrate, wherein the external terminals of the first semiconductor device are formed in a plurality of rows and arranged along each edge of the mounting face of the first wiring substrate, in a plan view, wherein the external terminals of the first semiconductor device include a first external terminal group arranged at a peripheral portion side of the mounting face of the first wiring substrate, and a second external terminal group arranged further at a central portion side of the mounting face thereof than the first external terminal group, wherein an interval between the first external terminal group and the second external terminal group is larger than a diameter of each of the external terminals, wherein the first semiconductor device is mounted over the mounting board such that a first edge of edges of the mounting face of the first wiring substrate faces the second semiconductor device, wherein the external terminals of the first semiconductor device include a plurality of interface terminals connected with the second semiconductor device, wherein the interface terminals are arranged along the first edge of the mounting face of the first wiring substrate and arranged further at the first edge side of the mounting face thereof than the central portion of the mounting face thereof, wherein the interface terminals include multiplexed terminals, including a first interface terminal group, a second interface terminal group and a third interface terminal group, having different signal input/output configurations from each other, wherein the first interface terminal group, the second interface terminal group and the third interface terminal group are distributed to the first external terminal group and the second external terminal group, wherein the second interface terminal group is arranged between the first interface terminal group and a second edge crossing to one end part of the first edge, in the plan view, and wherein the third interface terminal group is arranged between the first interface terminal group and a third edge crossing to another end part of the first edge, in the plan view, wherein the first semiconductor device is a baseband processor that provides specified communication protocol control for the electronic device, wherein the second semiconductor device is an application processor that provides control other than the communication protocol control for the electronic device, and wherein each of the first interface terminal group, the second interface terminal group, and the third interface terminal group is assigned one of signal input/output configurations for an input terminal, an output terminal, and an input/output terminal without duplication.