Patent ID: 8493400
Filing Date: 2013-07-23
Classification: G06F,G06T,G11C,H04N

Abstract:
1. A memory device, comprising: a memory cell array which has a plurality of memory unit areas selected by an address, and stores two-dimensional array data in the plurality of memory unit areas; an internal address control unit which inputs an external address, and generates an internal address configured to select the memory unit area based on the external address; and a decoder which decodes the internal address to select the memory unit area, wherein the plurality of memory unit areas store data arrayed in a first direction out of the matrix of the two-dimensional array data, based on a lower bit group of the internal address, and store data arrayed in a second direction out of the matrix of the two-dimensional array data, based on an upper bit group of the internal address, and the internal address control unit comprises a lower address generation unit configured to generate the lower bit group of the internal address, an upper address generation unit configured to generate the upper bit group of the internal address, and an address generation unit control circuit configured to control the operation of the lower address generation unit and the upper address generation unit based on a scanning direction control signal configured to control a scanning direction of the two-dimensional array data, and sequentially generates internal addresses corresponding to the scanning direction of the scanning direction control signal, when the scanning direction control signal indicates the first direction, the address generation unit control circuit controls so that the lower address generation unit operates with priority to sequentially change lower addresses, when the scanning direction control signal indicates the second direction, the address generation unit control circuit controls so that the upper address generation unit operates with priority to sequentially change upper addresses, and when the scanning direction control signal indicates a diagonal direction which is different from the first and second directions, the address generation unit control circuit controls so that the lower and upper address generation units operates in parallel to sequentially change the lower and upper addresses in parallel.