Patent ID: 6317373
Filing Date: 2001-11-13
Classification: G11C

Abstract:
A semiconductor memory device having a test mode in which same data is written at the same time into selected N (N is an integer that is at least two) memory cells and in which said N memory cells are determined as being normal when logics of N bits of data read out at the same time from said N memory cells all match, comprising:N memory arrays, each including a plurality of memory cells;a write/read circuit provided corresponding to each memory array for selecting one of a plurality of memory cells belonging to a corresponding memory array according to an address signal and for performing a data write/read operation for the selected memory cell;a selecting circuit for selecting one memory array out of said N memory arrays according to a block selecting signal;a data output buffer for outputting to a data input/output terminal a signal of a level corresponding to a logic of data read by said write/read circuit from the memory array selected by said selecting circuit during a period in which an output enable signal is input and for causing said data input/output terminal to enter a high impedance state during a period in which the output enable signal is not input;a determination circuit for determining whether logics of N bits of data read by said write/read circuit from said N memory arrays all match and for outputting a signal of a first level when a match occurs and for outputting a signal of a second level when no match occurs;a first holding circuit for holding an output signal of said determination circuit;a signal generating circuit for outputting the output enable signal according to an external control signal; anda gate circuit provided between said signal generating circuit and said data output buffer for allowing the output enable signal output from said signal generating circuit to be input into said data output buffer during a normal operation and when said first holding circuit holds the signal of the first level during said test mode, and for inhibiting the output enable signal output from said signal generating circuit from being input into said data output buffer when said first holding circuit holds the signal of the second level during said test mode.