Patent ID: 8036036
Filing Date: 2011-10-11
Classification: H01L

Abstract:
1. A semiconductor device comprising: at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of the memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series; a plurality of cell gates selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates formed with a closed loop, each of the loops connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the memory cell units within one of the two adjacent memory cell blocks and connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks; and a plurality of pairs of first and second selection gates selecting the memory cell block, the plurality of cell gates located between one pair of the first and second selection gates within a corresponding block of the memory cell block, wherein each of the plurality of cell gates are arranged so that first gaps between adjacent cell gates of the cell gates at one or two lines of the loop in a first direction along which the two adjacent memory cell blocks are arranged, are wider than second gaps between adjacent cell gates of the cell gates at perpendicular lines of the loop in a second direction which is perpendicular to the first direction along which the two adjacent memory cell blocks are arranged.