Patent ID: 6269047
Filing Date: 2001-07-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a low-potential power-supply line applied with a low potential;a high-potential power-supply line applied with a high-potential;a memory cell array including a plurality of memory cells;a boosted potential generating circuit configured to generate a boosted potential higher than the high-potential;a precharge signal generating circuit configured to generate a precharge signal which sets the high-potential at a high-level;a level-shifting circuit configured to level-shift the precharge signal to a boosted precharge signal which sets the boosted potential at a high-level;a boosted potential line applied with the boosted potential;a boosted potential supplying circuit configured to supply the boosted potential from the boosted potential generating circuit to the boosted potential line;at least one word-line connected to the plurality of memory cells; anda word-line selecting circuit configured to select said at least one word-line, the word-line selecting circuit including:a decoder configured to decode a plurality of address signals which set the high-potential at a high-level, based on the boosted precharge signal, the decoder including a first P-channel insulated-gate FET having a gate receiving the boosted precharge signal, a source receiving the boosted potential and a drain electrically coupled to an output of the decoder; anda word-line driving circuit configured to drive said at least one word-line based on a potential of the output of the decoder.