Patent ID: 6097048
Filing Date: 2000-08-01
Classification: H01L

Abstract:
In a gate array logic device, a dynamic random access memory cell comprising:a first MOS transistor formed in a top surface of a semiconductor substrate, said transistor having spaced apart first and second impurity regions, each of a first conductivity type, and a gate electrode above and between said first and second impurity regions of the first conductivity type;a second MOS transistor formed in the top surface of a semiconductor substrate, said transistor having spaced apart first and second impurity regions, each of a second conductivity type, and a gate between said first and second impurity regions of the second conductivity type;a bit line connected to the first impurity region of the first conductivity type of the first MOS transistor; anda word line connected to the gate electrode of the first MOS transistor,wherein the second impurity region of the first conductivity type of the first MOS transistor is electrically connected with the gate electrode of the second MOS transistor.