Patent ID: 6791420
Filing Date: 2004-09-14
Classification: H03L,H04L

Abstract:
A phase locked loop for recovering a clock signal from a data signal, comprising:a delay locked loop having: a connection for supplying a signal to be derived from the clock signal; a connection for supplying the data signal; a nonlinear phase detector having: a first input coupled to the connection for supplying the signal; a second input coupled to the connection for supplying the data signal; and at least one output; said nonlinear phase detector producing, at said at least one output, one of: a signal able to assume one of only three states including: a first state in which a phase of the clock signal leads a phase of the data signal; a second state in which the phase of the clock signal lags the phase of the data signal; and a third state in which a phase angle of the clock signal and a phase angle of the data signal one of match and are instantaneously unknown; and a binary signal; an integrator having: an output; and an input connected to said at least one output of said phase detector; and a delay element having: a control input connected to said output of said integrator; and an output connected to one of said first and second inputs of said phase detector; a loop filter having: an output; an input connected to said output of said integrator; a proportional regulator component; and an integral regulator component; and a voltage controlled oscillator having: an input connected to said output of said loop filter; and an output at which the clock signal is to be tapped off.