Patent ID: 6018787
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A networked circuit board comprising:an address bus;a programmable array logic device, connectable to the address bus, which is programmed to output five (5) chip select signals in response to address signals on the address bus, and which is also programmed to output three (3) coded signals in response to other address signals on the address bus;a decoder connected to said programmable array logic device for decoding the coded signals into eight (8) chip select signals, the decoder introducing a time delay into the eight chip select signals relative to the five chip select signals output by the programmable array logic device, said decoder being a binary decoder;plural buffers corresponding respectively to the five chip select signals output by the programmable array logic device, the plural butters introducing a time delay into each of the five chip select signals so as substantially to compensate for the time delay introduced into the eight chip select signals by the decoder in order to make the eight chip select signals valid at the same time as the buffered five chip select signals; anda microprocessor, a network controller, an expansion socket, a dual port memory, a disk interface, a PCMCIA interface, a parallel interface, a video bus gate array, an address buffer and a data buffer, each of which is connected to the address bus and each of which is selectable in response to one of said plural chip select signals.