Patent ID: 8450221
Filing Date: 2013-05-28
Classification: H01L

Abstract:
1. A method of forming an integrated circuit (IC) including at least one MOS device on a wafer having a topside silicon comprising surface, comprising: forming a SiON gate dielectric layer on said topside silicon comprising surface; depositing a gate electrode layer on said SiON gate layer; patterning said gate electrode layer to form a gate stack, wherein exposed SiON sidewalls and exposed gate electrode sidewalls are revealed by said patterning; forming a supplemental silicon oxide layer on or along said exposed SiON sidewalls; nitriding said supplemental silicon oxide layer; after said nitriding, post nitridation annealing (PNA) to form an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness for said annealed N-enhanced SiON gate layer a N concentration at said N-enhanced SiON sidewalls is ≧ a N concentration in a bulk of said annealed N-enhanced SiON gate layer −2 atomic %, and forming a source and a drain region spaced apart from one another on opposing sides of said gate stack to define a channel region positioned under said gate stack.