Patent ID: 8878588
Filing Date: 2014-11-04
Classification: H03H

Abstract:
1. An attenuation circuit comprising; first through fourth MOS transistors, each having a source, a drain and a gate; the first MOS transistor having its source and drain coupled between an AC signal being attenuated and a first reference voltage; the second MOS transistor being coupled as a source follower to provide a voltage one V the third and fourth MOS transistors having their sources coupled through respective first and second resistors to a common node, the common node being coupled to a current source, the drains of the third and fourth MOS transistors being coupled through respective third and fourth resistors to a power supply, the gate of the third MOS transistor being coupled to the source of the second MOS transistor; the gate of the fourth MOS transistor being coupled to a bias voltage; the drain of the fourth MOS transistor being coupled to the gate of the first MOS transistor.