Patent ID: 6101568
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A bus interface unit for interfacing with a bus of a computer system, the bus interface unit having at least one input for receiving in-order transactions and combinable write transactions, said bus interface unit comprising:a random-access transaction buffer that stores informational entries for both in-order transactions and combinable write transactions, each of the informational entries including address information, data information, and mode information; andat least one pointer queue coupled to the transaction buffer, the pointer queue storing pointers to informational entries for received in-order transactions,wherein the pointers stored in the pointer queue are used to order the in-order transactions stored in the transaction buffer, andwhen the bus interface unit receives a combinable write transaction whose writing address falls within the address range of one of the combinable write transactions stored in the transaction buffer, the received combinable write transaction is merged with the stored combinable write transaction so as to store the received combinable write transaction and the stored combinable write transaction in a single informational entry.