Patent ID: 6067656
Filing Date: 2000-05-23
Classification: G06F

Abstract:
An error detection circuit, comprising:a parity encoder having a first input terminal to receive an input data signal and a first output terminal to deliver a signal representative of the parity of the input data signal;a parity comparator having a second input terminal, having a third input terminal connected to the first output terminal, and having a plurality of memory cells to store original parities of tag words, the parity comparator for comparing a first original parity of a first tag word to the parity of the input data signal in response to receiving a first match signal; anda content addressable memory array having a fourth input terminal to receive the input data signal, and a second output terminal to send the first match signal in response to at least one of the tag words matching the input data signal, the second output terminal connecting to the second input terminal;wherein said parity comparator is separate from said content addressable memory array.