Patent ID: 7426240
Filing Date: 2008-09-16
Classification: H03M,H04L,H04N

Abstract:
1. A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising: an interleaver memory operable to read-in the predetermined number of data symbols for mapping onto the OFDM carrier signals, and to read-out the data symbols for the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the carrier signals; and an address generator operable to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the carrier signals onto which the data symbol is to be mapped, the address generator comprising, a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM carriers, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds the predetermined number of carriers, wherein the predetermined number of OFDM carrier signals is substantially four thousand, the linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R