Patent ID: 9000796
Filing Date: 2015-04-07
Classification: G02F,G09G,H01L

Abstract:
1. An active matrix substrate, comprising: a substrate; a plurality of gate lines arranged on the substrate: a plurality of source lines arranged on the substrate, in a direction orthogonal to each of the plurality of gate lines; a gate short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of gate lines; a source short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of source lines; a plurality of gate line thin film transistors each provided for a corresponding one of the plurality of gate lines and each having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of gate lines, and an other of the source electrode and the drain electrode being connected to the gate short-circuit line; and a plurality of source line thin film transistors each provided for a corresponding one of the plurality of source lines and each having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of source lines, and an other of the source electrode and the drain electrode being connected to the source short-circuit line, wherein the plurality of gate line thin film transistors and the plurality of source line thin film transistors are of depletion-mode, the gate electrode of each of the plurality of source line thin film transistors is connected to the gate short-circuit line, a load thin film transistor having a source electrode and a gate electrode which are short-circuited is inserted between the gate electrode of each of the plurality of source line thin film transistors and the gate short-circuit line, the load thin film transistor being for setting an electric potential of the gate short-circuit line to an electric potential of the gate electrode of each of the plurality of source line thin film transistors, and the gate electrode of each of the plurality of gate line thin film transistor is connected to the gate electrode of each of the plurality of source line thin film transistors.