Patent ID: 7218169
Filing Date: 2007-05-15
Classification: G05F

Abstract:
1. A compensation circuit, comprising: a reference circuit including a reference NMOS device and a reference PMOS device, the reference circuit being operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device, the reference circuit being configured to provide the first and second reference signals as separate and independent outputs; and a control circuit connected to the reference circuit, the control circuit being operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.