Patent ID: 7924259
Filing Date: 2011-04-12
Classification: G09G,G11C

Abstract:
1. A shift register array comprising a plurality of shift registers, at least one shift register comprising: a first transistor comprising a gate, a first electrode, and a second electrode, wherein the gate and the first electrode of the first transistor receive an input signal; a second transistor comprising a gate, a first electrode, and a second electrode, wherein the gate of the second transistor is coupled to the second electrode of the first transistor, the second electrode of the second transistor generates an output signal, and the first electrode of the second transistor receives a first clock signal; a third transistor comprising a gate, a first electrode, and a second electrode, wherein the first electrode of the third transistor is coupled to the gate of the second transistor, the second electrode of the third transistor is coupled to a power source, and the third transistor is for pulling down a voltage level at the gate of the second transistor; and a driving circuit comprising: