Patent ID: 7171602
Filing Date: 2007-01-30
Classification: G01R

Abstract:
1. An event processing apparatus for use with an event based test system for testing a semiconductor device under test (DUT), comprising: an event memory for storing event data of each event where the event data includes timing data for each event which is formed with event count data which is an integer multiple of a clock period and event vernier data which is a fraction of the clock period; an event summing logic for accumulating the timing data and producing the accumulated timing data of an event in a parallel form; and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic; wherein the events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event; and wherein the clock period is a one cycle time length of a processing clock which is a reference clock for operating hardware of the event processing apparatus, and wherein the event summing logic produces the accumulated timing data at a plurality of outputs in the parallel form thereby enabling to produce the events at a rate of an event clock which has a frequency higher than the processing clock.