Patent ID: 6747493
Filing Date: 2004-06-08
Classification: H03K

Abstract:
A power-on reset circuit comprising:an input circuit which is initialized by the assertion of a power-on reset signal entered from outside when power supply is turned on and supplies a first signal of a first logical value at the time a detection signal is entered, a reset extending circuit which is initialized by the assertion of said power-on reset signal and, after said power-on reset signal is negated, supplies a second signal which takes on a second logical value when an external clock signal is first entered and a third logical value after the lapse of a prescribed length of time determined by counting said external clock signals after said first signal of said first logical value is entered, a detecting circuit which is initialized by the assertion of said power-on reset signal and, after said power-on reset signal is negated, caused to generate said detection signal by the input of said second signal of said second logical value from said reset extending circuit and supply it to said input circuit, and a gate circuit which supplies a reset signal of a prescribed logical value when the first signal of said first logical value is supplied from said input circuit and said second signal of said third logical value is supplied from said reset extending circuit.