Patent ID: 6388495
Filing Date: 2002-05-14
Classification: G06F,H03K

Abstract:
An active clamping and terminating circuit in a communication system connected to a bus comprising:a first MOS transistor comprised of a source, a drain, and a gate, whereby the drain of the first MOS transistor is connected to the bus; a second MOS transistor comprised of a source, a drain, and a gate, whereby the source of the second MOS transistor is connected to the bus; a first circuit stage providing a bias voltage of VTN to the gate of the first MOS transistor comprised of a third MOS transistor comprised of a source, a drain, and a gate, whereby the drain of the third MOS transistor is connected to the gate of the first MOS transistor, the source of the third MOS transistor is connected to VDD; a fourth MOS transistor comprised of a source, a drain, and a gate, whereby the gate and the source of the fourth MOS transistor is connected to the gate of the third MOS transistor; a fifth MOS transistor comprised of a source, a drain, and a gate, whereby the gate and the source of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the drain of the fifth MOS transistor is connected to ground; a first resistor with one end connected to the source of the fourth MOS transistor, the other end connected to VDD, and a second resistor with one end connected to ground and the other end connected to the drain of the third MOS transistor and the gate of the first MOS transistor; and a second circuit stage providing a bias voltage of VDDâˆ’VTP to the gate of the second MOS transistor wherein the first MOS transistor clamps and terminates voltage when voltage along the bus falls below VSS, and the second MOS transistor clamps and terminates voltage when voltage along the bus exceeds VDD.