Patent ID: 6473019
Filing Date: 2002-10-29
Classification: H03M

Abstract:
An N-level quantizer circuit, said quantizer circuit having an analog input terminal and Nâˆ’1 digital output terminals, comprising:a sampling circuit coupled to said input terminal for providing a sampled input voltage signal; at least one preamplifier stage for amplifying said sampled input voltage signal and providing a sampled input current signal; Nâˆ’1 comparator stages each having an input coupled to an output of said at least one preamplifier stage, individual ones of said Nâˆ’1 comparator stages operating to share said current signal and to compare said current signal to an associated one of Nâˆ’1 reference current signals; and Nâˆ’1 latches individual ones of which latch an output state of one of said Nâˆ’1 comparators and having an output coupled to one of said Nâˆ’1 digital output terminals of said quantizer circuit; wherein individual ones of said Nâˆ’1 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise from said Nâˆ’1 latches to others of said comparators and to said input terminal of said quantizer circuit.