Patent ID: 7107408
Filing Date: 2006-09-12
Classification: G06F

Abstract:
1. A computer system, comprising: a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture; a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller; wherein the first cache coherence controller is configured to receive a cache access request originating from the first plurality of processors and send a probe to the first plurality of processors in the first cluster before the cache access request is received by a serialization point in the second cluster and wherein the first cache coherence controller is further configured to forward the cache access request before determining if the cache access request can be completed locally.