Patent ID: 7183207
Filing Date: 2007-02-27
Classification: H01L

Abstract:
1. A CVD metallization process, comprising: loading a semiconductor substrate into a first transfer chamber; transferring the semiconductor substrate in the first transfer chamber into a first CVD process chamber attached to the first transfer chamber; forming a first metal layer comprising a barrier metal layer on the semiconductor substrate in the first CVD process chamber; transferring the semiconductor substrate having the first metal layer into a second transfer chamber separated from the first transfer chamber without breaking vacuum; transferring the semiconductor substrate in the second transfer chamber into a second CVD process chamber attached to the second transfer chamber; forming a second metal layer on the semiconductor substrate inside the second CVD process chamber; forming an impurity region in a portion of the semiconductor substrate before loading the semiconductor substrate into the first transfer chamber; forming an interlayer insulating layer on the semiconductor substrate having the impurity region, the interlayer insulating layer having a contact hole that exposes the impurity region; and forming a conformal ohmic layer comprising a titanium layer in the contact hole and on the interlayer insulating layer.