Patent ID: 7605423
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided on the major surface of the semiconductor layer and being adjacent to the first semiconductor pillar region; a first semiconductor region of the second conductivity type provided on the second semiconductor pillar region; a second semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor region; a first main electrode provided on the first semiconductor region and the second semiconductor region; an insulating film provided on the first semiconductor pillar region, the first semiconductor region, and the second semiconductor region; a control electrode provided on the insulating film; a second main electrode provided on a side opposite to the major surface of the semiconductor layer; a third semiconductor region of the first conductivity type provided on the major surface of the semiconductor layer and located on a terminal side of the first semiconductor pillar region and the second semiconductor pillar region; a fourth semiconductor region of the second conductivity type provided on the major surface of the semiconductor layer and located on the terminal side of the first semiconductor pillar region and the second semiconductor pillar region, the fourth semiconductor region being adjacent to the third semiconductor region; a high resistance semiconductor layer provided on the third semiconductor region and the fourth semiconductor region; a fifth semiconductor region of the first conductivity type provided on the high resistance semiconductor layer; and a sixth semiconductor region of the second conductivity type provided on the high resistance semiconductor layer and being adjacent to the fifth semiconductor region, an amount of dopant in at least one of the first semiconductor pillar region and the second semiconductor pillar region being gradually varied in a direction from the first main electrode to the second main electrode, the amount of dopant in the first semiconductor pillar region being smaller than the amount of dopant in the second semiconductor pillar region on the first main electrode side, and the amount of dopant in the first semiconductor pillar region being larger than the amount of dopant in the second semiconductor pillar region on the second main electrode side.