Patent ID: 7954027
Filing Date: 2011-05-31
Classification: G01R,G06F

Abstract:
1. TAP domain selection circuitry, comprising: A. update instruction circuitry having control outputs; B. first gating circuitry having an input connected to a test mode select input, TAP domain select inputs connected to the control outputs, and TAP domain test mode select outputs, each TAP domain test mode select output separately responding to a signal on the test mode select input and to signals on the TAP domain select inputs; C. second gating circuitry having inputs connected to the TAP domain test mode select outputs, and having one output; D. state machine circuitry having an input connected to the output of the second gating circuitry, a test clock input, and an enable output, the state machine placing an active signal on the enable output in response to the output of the second gating circuitry and the test clock input transitioning the state machine circuitry to one of a Shift-DR state and a Shift-IR state; and E. I/O circuitry including: i. an input buffer having an input connected to a data in/data out lead, and a data in output coupled to the update instruction circuitry; and ii. an output buffer having a data out input, an output connected to the data in/data out lead, and a control input connected to the enable output of the state machine.