Patent ID: 6055649
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A method for debugging a processor within a data processing system, the processor having a test port for transferring data into the processor, comprising the steps of:inhibiting fetching of instructions into an instruction register of the processor;loading at least a first debug instruction into the instruction register of the processor;transferring a stream of data into a first register element within the processor via the test port;detecting when a first portion of the stream of data is present in the first register element;moving the first portion of the stream data from the first register element to a first memory accessible to the processor by executing the first debug instruction in the instruction register after the step detecting the first portion;detecting when a second portion of the stream of data is present in the first register element;moving the second portion of the stream data from the first register element to a second memory location accessible to the processor by executing the same first debug instruction in the instruction register after the step detecting the second portion; andrepeating the steps of detecting and moving while the step of transferring continues until the entire stream of data is moved to a plurality of memory locations.