Patent ID: 8966155
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of block-access memory devices, wherein each of the plurality of block-access memory devices is configured to store data at one or more physical sector addresses, wherein each of the plurality of block-access memory devices comprises a plurality of pages, and wherein each of the plurality of pages comprises a plurality of physical sectors addressed by physical sector addresses; a random-access memory device storing a logical-to-physical (L2P) address translation data structure and a physical-to-logical (P2L) address translation structure, wherein the L2P address translation data structure stores information identifying every logical sector address currently in use within the plurality of block-access memory devices, and wherein the P2L address translation structure stores information individually identifying every physical sector address currently in use within the plurality of block-access memory devices; and a device manager, coupled to the block-access memory device and the random-access memory, and configured to: