Patent ID: 8724380
Filing Date: 2014-05-13
Classification: G11C

Abstract:
1. A method for detecting individual resistance states of a plurality of memory elements coupled in series in a memory device, each of the plurality of memory elements having a resistance state that can be switched from a first resistance level to a second resistance level by a write input no lower than a write threshold, the method comprising the steps of: sequentially writing each of the plurality of memory elements to the second resistance level in order of ascending write threshold; ascertaining whether the each of the plurality of memory elements has switched the resistance state thereof; concluding the each of the plurality of memory elements is in the first resistance level if the each of the plurality of memory elements has switched the resistance state thereof; and concluding the each of the plurality of memory elements is in the second resistance level if the each of the plurality of memory elements has not switched the resistance state thereof.