Patent ID: 8637931
Filing Date: 2014-01-28
Classification: H01L

Abstract:
1. A finFET device comprising: a buried oxide (BOX) layer; a plurality of fin structures located over the BOX layer, the fin structures each comprising a semiconductor layer and extending in a first direction; a gate stack located over the fin structures on the BOX layer, the gate stack extending in a second direction that is perpendicular to the first direction, the gate stack comprising a high-K dielectric layer and a metal gate; gate spacers located on vertical sidewalls of the gate stack; an epitaxial silicon (epi) layer covering the fin structures, the epi layer merging the fin structures together; source and drain regions located in the semiconductor layers of the fin structures; silicide regions abutting the source and drain regions; and dummy spacers located on vertical sidewalls of the gate spacers, the vertical sidewall of each source and drain region being aligned with a vertical sidewall of one of the dummy spacers, wherein at least one of the silicide regions includes a vertical portion located on the vertical sidewall of the source or drain region, and a horizontal portion formed above the BOX layer and extending from the vertical portion in the first direction.