Patent ID: 7728675
Filing Date: 2010-06-01
Classification: H03L,Y10S

Abstract:
1. A lock circuit for a phase lock loop, said circuit comprising: a phase frequency detection circuit operable to detect individual phases and individual frequencies of an input signal and in response thereto operable to adjust first and second phase control output signals for adjusting one or more of said individual phases and individual frequencies of said input signal; a frequency detection circuit coupled to said phase frequency detection circuit and operable to detect individual frequencies of said input signal and in response thereto operable to adjust first and second frequency control output signals for adjusting at least one of said frequencies of said input signal; a logic circuit coupled to said phase frequency detection circuit and further coupled to said frequency detection circuit and operable to output said first and second phase control output signals and said first and second frequency control output signals based on a lock status of said phase locked loop; a first charge pump coupled to said logic circuit for increasing and decreasing a first current output in response to one or both of said first and second phase control output signals from said phase frequency detection circuit and one or both of said first and second frequency control output signals from said frequency detection circuit; and a second charge pump coupled to said frequency detection circuit for increasing and decreasing a second current output in response to said frequency detection circuit, wherein said first and second frequency control output signals are relayed to the second charge pump regardless of whether the phase lock loop is in lock.