Patent ID: 8199603
Filing Date: 2012-06-12
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: an array of variable-resistance memory cells; and a write driver configured to drive a bit line in said array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array; wherein said write driver is configured to drive the bit line with a first stair-step sequence of at least two unequal bit line voltages during an operation to program the variable-resistance memory cell into a set state; wherein said write driver is configured to drive the bit line with a second stair-step sequence of at least two unequal bit line voltages during an operation to program the variable-resistance memory cell into a reset state; and wherein magnitudes of the voltages in the first stair-step sequence are equivalent to magnitudes of the voltages in the second stair-step sequence.