Patent ID: 6465837
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A scaled stack-gate non-volatile semiconductor device comprising:a stack-gate structure being formed on a semiconductor substrate having an active region isolated by field-oxides, said stack-gate structure includes a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer formed on a thin tunneling-dielectric layer; said stack-gate structure being oxidized to form a first thin poly-oxide layer over sidewalls of said control-gate layer, a second thin poly-oxide layer over sloped sidewalls of said tapered floating-gate layer, and a thicker oxide layer formed over each side portion of said active region having a graded-oxide layer formed near two gate edges; a deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region being formed in said side portion of said active region in a self-aligned manner; and a dielectric spacer being formed over sidewalls of said stack-gate structure for forming a self-aligned source/drain contact of said scaled non-volatile semiconductor memory device.