Patent ID: 6320406
Filing Date: 2001-11-20
Classification: H03K,H04L

Abstract:
An active fail-safe LVDS receiver circuit that provides a known logic level output in the absence of a differential in signal, comprising:a relatively high-speed main receiver having inputs coupled to a first and second differential input, and having an output;a window comparator also coupled to said first and second differential inputs consisting of first and second fail-safe comparators, each having a first and a second differential input, wherein the first input of said first fail-safe comparator is coupled to the second input of said fail-safe second comparator and to the second input of said main receiver and the second input of said fail-safe first comparator is coupled to the first input of said second fail-safe comparator and to the first input of said main receiver;a fail-safe activity timer coupled to the output of said main receiver;a logic gate having inputs coupled to the outputs of said first and second fail-safe comparators and to the output of said fail-safe timer; andan output buffer having inputs coupled to the output of said main receiver and to the output of said logic gate.