Patent ID: 6680992
Filing Date: 2004-01-20
Classification: H03D

Abstract:
A clock identification and reproduction circuit which synchronizes a clock signal with an input signal, comprising:a voltage controlled generator for generating said clock signal; a phase comparator for detecting a phase difference between said input signal and said clock signal to generate a phase difference signal according to the phase difference; a filter for synchronizing a phase of the clock signal of said voltage controlled generator in response to said phase difference signal, wherein said phase comparator comprises: a first D-type flip flop circuit for latching and outputting said input signal using said clock signal for latch timing; a second D-type flip-flop circuit for latching and outputting the output from said first D-type flip-flop circuit using an inversion of said clock signal for latch timing; a first logical product gate for outputting a logical product of said input signal and an inverted output from said first D-type flip-flop circuit as a comparison pulse signal; a second logical product gate for outputting a logical product of the output from said first D-type flip-flop circuit and an inverted output from said second D-type flip-flop circuit as a reference pulse signal; an adder for receiving inputs of said comparison pulse signal and said reference pulse signal to output said phase difference signal, wherein said phase comparator generates the phase difference signal when a specific pulse waveform of a pulse of said input signal changes; wherein said phase comparator comprises at least one of: a first delay circuit for delaying the inverted output of said second D-type flip-flop circuit by a first delay time before application to said second logical product gate, and a second delay circuit for delaying the output of said first D-type flip-flop circuit by a second delay time before application to said second logical product gate, thereby setting intervals of said reference pulse signal.