Patent ID: 6222218
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A memory cell comprisinga capacitor formed in a trench located in a semiconductor substrate or wafer, said capacitor including at least a temperature sensitive high dielectric constant material located between a bottom electrode and a top electrode;a MOSFET formed in said semiconductor substrate or wafer, said MOSFET comprising at least a patterned gate conductor stack, a near source/drain region located between said gate conductor stack and said capacitor, a far source/drain region located on a side of said gate conductor stack opposite said near source/drain region said capacitor and said MOSFET being connected by a buried-strap outdiffusion region laterally extending from an edge of said trench toward said gate conductor stack, said buried-strap outdiffusion region having a lateral outdiffusion of less than 50 nm;said capacitor and said source/drain regions having lateral dimensions photolithographically patterned to a minimum feature size of about 0.15 micron or smaller; andsaid memory cell characterized by a distance parameter, said parameter being the lateral distance between a near edge of said far source/drain region and a near edge of said outdiffusion region, said parameter having a value of between about 50% to greater than 75% of a lateral distance between said far gate conductor edge and said trench edge.