Patent ID: 7921148
Filing Date: 2011-04-05
Classification: G06F

Abstract:
1. A cell for an arithmetic logic unit comprising a mirror adder circuit modified to perform additional arithmetic or logic functions without additional transistors excluding input or output inverters, comprising: a first masked input a*; a second masked input b*; a third masked input ci*, wherein the third masked input ci* is a masked carry input, a mask bit k a first control input xe a first circuit comprising a first plurality of transistors, wherein inputs of the first plurality of transistors are connected to the first masked input a*, the second masked input b*, and the third masked input ci*, and the first plurality of transistors having a first output co*_n, the first output co*_n being a masked inverted carry-out bit; a second circuit comprising a second plurality of transistors, wherein inputs of the second plurality of transistors are connected to the first masked input a*, the second masked input b*, the first output co*_n, the first control input xe the second output s*_n having a first value, when the first control input xe the second output s*_n having a second value when the first control input xe the second output s*_n having a third value when the first control input xe the second output s*_n having a fourth value when the values at the first control input xe