Patent ID: 6259293
Filing Date: 2001-07-10
Classification: H03K,H03L

Abstract:
Delay circuitry comprising:phase locked loop means for comprising a phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to a phase difference between the phases of the reference clock and the another clock, for generating the another clock using at least a plurality of first delay elements connected into a loop, a time delay provided by each of the plurality of first delay elements being controlled by the control signal, and for changing the value of the control signal so that the another clock is made to be in phase with the reference clock;storage means for storing information to set a predetermined time delay; anddelay means, connected to said storage means, and including a plurality of second delay elements each of which provides an input with a time delay that is controlled by the control signal from said phase locked loop means, for determining the number of second delay elements through which an input signal is to be passed according to the information stored in said storage means, so as to provide the input signal with the predetermined time delay.