Patent ID: 6099579
Filing Date: 2000-08-08
Classification: G06F

Abstract:
An apparatus for performing an asynchronous path design review of a circuit design's HDL code, comprising:a tool that performs an exhaustive search of all circuits in said HDL code and that identifies any asynchronous behavior; said tool comprising:a signal table generation module for use during a first phase of design review, wherein said signal table generation module parses an input source file as a stream of tokens such that, as new signals are detected, said signals are added to a signal table for subsequent modification;a signal domain resolution module for use during a second phase of design review, wherein said signal domain resolution module processes said signal table in multiple passes until a cone of logic behind each signal is completely determined;a domain verification module for use during a third phase of design review, wherein said domain verification module uses a completed signal table to compare domain of feeder signals to a domain of every flip-flop using such feeder signal; anda report generation module for use during a fourth phase of design review, wherein said report generation module produces any one or more possible output formats for display.