Patent ID: 6237124
Filing Date: 2001-05-22
Classification: G01R,G06F

Abstract:
A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprising:providing a serial data stream into said FPGA from an external source;loading data from said serial data stream into said configuration SRAM in response to address signals generated by row column counters;loading data from said serial data stream into said user assignable SRAM in response to address signals generated by row and column counters;cycling data out of said configuration SRAM and said user assignable SRAM by said row and column counters;performing error checking on said data that has been cycled out of said configuration SRAM and out of said user assignable SRAM by a cyclic redundancy checking circuit; andgenerating an error signal when an error is detected by said error checking circuit.