Patent ID: 9218242
Filing Date: 2015-12-22
Classification: G06F,G11C

Abstract:
1. A method of operating a nonvolatile memory array comprising: receiving a portion of data to be stored in the nonvolatile memory array; buffering the portion of data in on-chip data latches; writing the portion of data from the on-chip data latches as Single Level Cell (SLC) data in a first block in the nonvolatile memory array while asserting a busy indicator throughout the writing; subsequently, writing the portion of data from the on-chip data latches as Multi Level Cell (MLC) data in a second block in the nonvolatile memory array; maintaining the portion of data in the on-chip data latches throughout a time that extends from the writing of the portion of data as SLC data in the first block to the writing of the portion of data as MLC data in the second block; and subsequently erasing the first block only after a post write read confirms that the second block contains data that passes a predetermined standard.