Patent ID: 8271812
Filing Date: 2012-09-18
Classification: G06F,Y02D

Abstract:
1. An integrated circuit comprising: at least one processor; one or more registers programmable to indicate one or more performance states; and a control circuit coupled to the one or more registers and the processor, wherein the control circuit is configured to detect that the processor is entering a sleep state, and wherein the control circuit is configured to change a performance state of at least one performance domain in the integrated circuit to a first performance state of the one or more performance states in response to the processor entering the sleep state, and wherein the control circuit is configured to detect that the processor is exiting the sleep state, and wherein the control circuit is configured to change the performance state of at least one performance domain in the integrated circuit to a second performance state of the one or more performance states in response to the processor exiting the sleep state, and wherein the second performance state differs from a third performance state that was in effect prior to the processor entering the sleep state.