Patent ID: 6423641
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A method for making self-aligned bit lines on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, a plurality of word lines positioned on the silicon substrate and a first dielectric layer positioned on the surface of the semiconductor wafer, the first dielectric layer covering each word line, the method comprising:performing a first etching process so as to form a plurality of bit-line contact holes in the first dielectric layer; forming a first conducting layer that fills the bit-line contact holes to form bit-line contacts, and leveling the top surface of each bit-line contact with the surface of the first dielectric layer; forming a second dielectric layer on the surface of the semiconductor wafer; performing a second etching process so as to form a plurality of node contact holes in the second and first dielectric layers; forming a second conducting layer that fills the node contact holes to form node contacts, and leveling the top surface of each node contact with the surface of the second dielectric layer; performing an etching back process to remove portions of the second dielectric layer so as to make the top surface of each node contact higher than the surface of the second dielectric layer; forming a first spacer on the walls around the top portion of each node contact that is higher than the surface of the second dielectric layer; performing a third etching process so as to form a plurality of bit-line trenches in the second and first dielectric layers, a plurality of bit-line contacts protruding from the bottom portion of each bit-line trench; forming a third conducting layer that fills each bit-line trench to form each bit line, and leveling the top surface of each bit line with the top surface of each bit-line contact; and forming a third dielectric layer on the surface of the semiconductor wafer, the third dielectric layer filling each bit-line trench.