Patent ID: 6226708
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A method of writing a plurality of data values to selected addressable locations in a plurality of non-volatile memory modules connected to a processor, the method comprising the steps of:storing a first data value in a first data latch of a first memory module of the plurality of non-volatile memory modules and an associated first address in a first address latch of the first memory module;storing a second data value in a second data latch of a second memory module of the plurality of non-volatile memory modules and an associated second address in a second control register of the second memory module;simultaneously writing the first data value from the first data latch to a first non-volatile memory array of the first memory module at the first address stored in the first address latch and writing the second data value from the second data latch to a second non-volatile memory array of the second memory at the second address stored in the second address latch; anddelaying processing by the processor for a predetermined time to allow the first data value to be written to the first non-volatile memory array and the second data value to be written into the second non-volatile memory array.