Patent ID: 7656178
Filing Date: 2010-02-02
Classification: G01R

Abstract:
1. A vernier calibration method for calibrating a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of: (a) mounting a second calibration board respectively connecting the plurality of drive channels to the plurality of input channels; (b) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels; (c) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels; (d) mounting a DUT interface board respectively connecting the plurality of input channels to the plurality of output channels; and (e) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels.