Patent ID: 9209765
Filing Date: 2015-12-08
Classification: H03F,H03K

Abstract:
1. A quick comparison circuit, comprising a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N≧2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them; each stage operational amplifier having the same structure, which comprises a first FET, a second FET, a third FET, a fourth FET, a fifth FET, a sixth FET, a seventh FET, and an eighth FET, with one of the differential signals being inputted to the gate of the first FET, the other differential signal being inputted to the gate of the second FET; the drain of the first FET being connected with the gate and the drain of the third FET respectively to output one of the differential signals that is amplified by the current stage operational amplifier, the drain of the second FET being connected with the gate and the drain of the sixth FET respectively to output the other differential signal that is amplified by the current stage operational amplifier; the sources of the first and the second FETs coupled jointly being connected with the biasing circuit, the sources of the third, the fourth, the fifth, and the sixth FETs being connected to an outer power source, the gates of the third and the fourth FETs being coupled together, the drain of the fourth FET being connected with the gate of the sixth FET, the gates of the fifth and the sixth FETs being coupled together, the source of the seventh FET, the gate and the drain of the eighth FET being connecting with the drain of the first FET respectively, and the source of the eighth FET, the gate and the drain of the seventh FET being connected with the drain of the second FET respectively.