Patent ID: 6882950
Filing Date: 2005-04-19
Classification: G01R,G06F

Abstract:
1. A method for testing a variety of circuit boards for a family of large electronic systems comprising: establishing a tester on-site with a third-party manufacturer/assembler/tester, said on-site tester having a connector mechanism for connection to each of said variety of circuit boards, translating a high-level language description file containing a high level language description of hardware for one of said variety of circuit boards into a low level vector format file, providing said low level vector format file for said one of said variety of circuit boards to said third-party manufacturer/assembler/tester, wherein said low level vector format file contains a test string for said one of said variety of circuit boards be tested, and wherein from said low level vector format test sings said third-party manufacturer/assembler/tester can establish a set of test vectors to use in performing a scan test on substantially said each one of said variety of circuit boards in said on-site tester.