Patent ID: 8243733
Filing Date: 2012-08-14
Classification: H04L

Abstract:
1. An integrated chip, comprising: two or more address tables implemented with separate memory tables configured to store addresses and network routing information, where the two or more address tables are comprised of a first address table and a second address table; connection lines connecting the first address table and the second address table to create a cascaded address table; and search logic to initiate a search of the first address table for a destination address received from a network packet, wherein if the destination address is not found, the search logic is configured to initiate a search of the second address table through the connection lines, and when the destination address is found at a memory location, causing the network packet to be routed based on the network routing information stored at the memory location; wherein the integrated chip is configured to operate in a networking switch, wherein the networking switch is configured to receive the network packet from an uplink port, and wherein the network packet is routed to one of a plurality of line card ports connected to the networking switch based on at least the search of the search logic, wherein the uplink port has a higher data rate than one of the plurality of line card ports.