Patent ID: 7281093
Filing Date: 2007-10-09
Classification: G06F

Abstract:
1. A memory apparatus for a message processing system having a set of n processing elements for processing messages, where n is an integer greater than zero, the apparatus comprising: a set of m memories for storing said messages, where m is an integer greater than zero; multiplexing logic for coupling each of said processing elements to each of said memories; control logic for driving said multiplexing logic to provide access to each of said memories among said processing elements in accordance with a gated modulo-n schedule; wherein said multiplexing logic comprises a set of m multiplexers, each of said multiplexers having an output terminal coupled to a respective memory of said set of memories, n input terminals respectively coupled to a processing element of said set of processing elements, and a select terminal; and wherein said control logic comprises a set of m control circuits, each of said control circuits having a select terminal coupled to a select terminal of a respective one of said multiplexers, a control interface coupled to each of said processing elements, and gating logic configured to gate said select terminal in response to control signals at said control interface.