Patent ID: 7675784
Filing Date: 2010-03-09
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell transistor; a bit line connected to the memory cell transistor; a sense amplifier activated by a sense enable signal and sensing a voltage of the bit line; a first dummy memory cell transistor; a first dummy bit line connected to the first dummy memory cell transistor and having a wiring load larger than a wiring load of the bit line; a first sense circuit sensing a voltage of the first dummy bit line and outputting a first sense signal; a precharge circuit charging the bit line and the first dummy bit line; a second dummy memory cell transistor; a second dummy bit line connected to the second dummy memory cell transistor and having a wiring load larger than the wiring load of the bit line; a discharge circuit discharging the bit line and the second dummy bit line; a second sense circuit sensing a voltage of the second dummy bit line and outputting a second sense signal; and a read control circuit starting a charging operation of the precharge circuit in response to a read enable signal, ending the charging operation of the precharge circuit and starting a discharging operation of the discharge circuit in response to the first sense signal of the first sense circuit, and outputting the sense enable signal in response to the second sense signal of the second sense circuit, wherein the first dummy memory cell transistor is connected to only one dummy bit line, and the second dummy memory cell transistor is connected to only one dummy bit line.