Patent ID: 8401135
Filing Date: 2013-03-19
Classification: H04L

Abstract:
1. A serial data receiver, comprising: an amplitude path including a first amplifier sub-path and a second amplifier subpath; a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path; an amplitude speculation multiplexer coupled to the first amplifier sub-path and a second amplifier sub-path and configured to select the first amplifier sub-path on receipt of a first selection signal and the second amplifier sub-path on receipt of a second selection signal; an amplitude latch coupled to an output of the amplitude speculation multiplexer; a data latch having a data output; a decision feedback equalization (DFE) logic block coupled to the amplitude speculation multiplexer and the data output and configured to generate either the first selection signal or the second selection signal based on the data output of the data latch; a clock recovery circuit operable to generate a recovered clock from a serial data signal and coupled to the amplitude latch and the data latch; and a phase rotator operable to shift a phase of the recovered clock to form a phase-rotated recovered clock; wherein the first sub-path includes a first summer and the second sub-path includes a second summer and both first and second summers are coupled to the DFE logic block; and wherein the first summer adds a first amount to the signal based on an assumption that an immediately preceding bit was a logical one and the second summer subtracts a second amount based on an assumption that the immediately preceding bit was a logical zero.