Patent ID: 6346833
Filing Date: 2002-02-12
Classification: G06F

Abstract:
A frequency multiplier circuit that outputs a signal achieved by multiplying a frequency of a reference clock, comprising:a first frequency divider that divides the frequency of said reference clock by 4, to provide a first signal having a duty ratio of approximately 50%; a second frequency divider that divides a frequency of a unit clock which is higher than the frequency of said reference clock by 2, to provide a second signal having a duty ratio of approximately 50%; an AND gate that obtains a logical AND of the first signal from said first frequency divider and the second signal from said second frequency divider; a first variable frequency divider that divides an output signal from said AND gate by n using variable frequency division data n (n is a positive integer) that is externally provided; an up-counter that counts a number of pulses Y in an output signal from said first variable frequency divider over intervals corresponding to a half cycle of the first signal from said first frequency divider; and a second variable frequency divider that divides the frequency of said unit clock by Y, by using the number of pulses Y as frequency division data, and that outputs the signal that is the frequency of said reference clock multiplied by n.