Patent ID: 7551485
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of being connected to a bit line for data read or data write; a sense amplifier circuit configured to read data of the memory cell array via the bit line; and a controller configured to control the sense amplifier circuit, the sense amplifier circuit further comprising: a clamp transistor connected between the bit line and a first node to transfer a voltage of the bit line to the first node; a first latch circuit capable of being connected to the first node to store data in a second node; a second latch circuit capable of being connected between the first node and a data line for inputting/outputting data, to store data in a third node; a first write-back circuit having a fourth node and configured to write back data stored in the second node to the first node via the fourth node, and to perform data addition/subtraction between the first node and the fourth node; and a second write-back circuit having a fifth node and configured to write back data stored in the second node to the first node via the fifth node, and to perform data addition/subtraction between the first node and the fifth node.