Patent ID: 6064229
Filing Date: 2000-05-16
Classification: H03K

Abstract:
An integrated circuit including a voltage translating buffer circuit, characterized in that said buffer circuit comprises:input, intermediate and output circuit stages, each circuit stage including first and second n-channel field effect transistors (n-FETS) connected in series;wherein,said first n-FET of said input stage having a gate terminal connected to receive a first logic voltage within a first logic voltage range;said first n-FET of said output stage having a gate terminal directly connected to a p-channel field effect transistor (p-FET) of said input stage;said output stage providing an output logic voltage at a circuit node between said second n-FET and a p-FET connected in series therewith, said output voltage being translated with respect to said first logic voltage to a second logic voltage range higher than said first range; andeach of said second n-FETS operable to drop sufficient voltage across a conducting channel thereof so as to prevent an excessive voltage drop across a conducting channel of the associated first n-FET in series therewith.