Patent ID: 6215691
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A cell structure of a ferroelectric memory device, comprising:first and second MOS transistors connected in series between two bit lines, for performing a switching operation according to an enable state of a word line, wherein each gate of the first and second MOS transistors is commonly connected to the word line;a third MOS transistor connected between a plate line and a contact point of the first MOS transistor and the second MOS transistor, for engaging with the first and second MOS transistors according to an enable state of the word line, wherein a gate of said third MOS transistor is connected to the word line; andfirst and second ferroelectric capacitors connected between the first MOS transistor and the third MOS transistor, and between the second MOS transistor and the third MOS transistor, respectively, and storing data in accordance with a switching state of the first to third MOS transistors.