Patent ID: 6661266
Filing Date: 2003-12-09
Classification: G01R

Abstract:
An integrated circuit having a built-in self test circuit for measuring error of a phase lock loop output clock signal, comprising:a short-pulse generator coupled to receive the phase lock loop output clock signal to generate a short-pulse signal having the same pulse width as the phase lock loop output clock signal; a delay chain coupled to receive the short-pulse signal, the delay chain comprising a plurality of delay elements to generate N delayed pulses from the short-pulse signal; a statistical counter coupled to receive the phase lock loop output clock signal, wherein the statistical counter generates a statistical maximum count 2&kgr;a hit-pulse generator coupled to receive the N delayed pulses to compare each of the N delayed pulses with the phase lock loop output clock signal 2k times, where k is a predetermined number and to generate a hit-pulse when both signals are high and to generate a hit count wherein the hit count is the number of hit pulses; a first comparator coupled to receive the hit count and at least one predetermined threshold value to compare the hit count for each of the N delayed pulses with the at least one predetermined threshold value; a storage unit coupled to the first comparator and the hit-pulse generator, such that when the hit count and one of the pre-determined set of threshold values are equivalent, the storage unit stores the value of N; and a processing unit coupled to the storage unit to calculate error of the phase lock loop output clock signal using each stored value of N for each corresponding predetermined threshold value.