Patent ID: 6111898
Filing Date: 2000-08-29
Classification: H04J

Abstract:
A method of performing a timing analysis of an integrated circuit which includes a multiplexer comprising:initializing the multiplexer to a first state, in which a first control signal enables a first input to be coupled as output from the multiplexer and a second control signal disables a second input from being coupled to the output;changing the multiplexer to a second state to couple the second input to the output and disable the first input from being coupled to the output, but in which an enabling edge of the second control signal changes prior to a disabling edge of the first control signal causing a transition period between the first and second states in which both inputs contend for the output; andpropagating the occurrence of the disabling edge of the first control signal in addition to noting the enabling edge of the second control signal to identify duration of the transition period.