Patent ID: 8537935
Filing Date: 2013-09-17
Classification: G01R,H03L,H04L

Abstract:
1. A clock data recovery circuit that generates a strobe signal based on a clock signal associated with input data to receive the input data, the clock data recovery circuit comprising: a variable delay circuit configured to receive a reference signal having a predetermined frequency, a delay control signal, and an initial delay set signal, and to provide a shift delay to the reference signal such that a phase of the reference signal is shifted on the basis of an initial delay, wherein the shift delay is a sum of the initial delay, which corresponds to the initial delay set signal, and a variable delay corresponding to the delay control signal; a latch circuit having a first terminal and a second terminal, the latch circuit being configured to receive the input data including bit data at said first terminal, to receive an output signal of the variable delay circuit at said second terminal, and to latch each bit data included in the input data by using the output signal of the variable delay circuit as a strobe signal; a phase comparator that matches frequencies of the clock signal and the output signal of the variable delay circuit with each other, and generates phase difference data in accordance with a phase difference between the two signals, the frequencies of which are matched with each other; a loop filter that performs filtering on the phase difference data generated by the phase comparator so as to generate the delay control signal, wherein the delay control signal is provided to the variable delay circuit; and a phase shift amount acquisition unit configured to accumulate the delay control signal so as to acquire the shift delay provided to the reference signal according to a cumulative value of the delay control signal.