Patent ID: 8401140
Filing Date: 2013-03-19
Classification: H03D,H03L

Abstract:
1. A circuit comprising: a first phase detector for detecting a first phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the first phase difference, and for issuing a first clear signal when both the rising edge of the first clock signal and the rising edge of the second clock signal have been detected, wherein the first phase detector comprises: a second phase detector for detecting a second phase difference between a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the second phase difference, and for issuing a second clear signal when both the falling edge of the first clock signal and the falling edge of the second clock signal have been detected, wherein the second phase detector comprises: combinational logic coupled to receive the first difference signal and the second difference signal, the combinational logic for preventing the second difference signal from being provided when the first difference signal is being provided by resetting both of the first and second phase detectors whenever either of the first or second phase detectors issues either the first or second clear signal, wherein the combinational logic comprises: