Patent ID: 8130563
Filing Date: 2012-03-06
Classification: G06F

Abstract:
1. A memory error signal detecting system, comprising: a signal extracting circuit receiving a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level; a flip-flop having a preset end, a clear end, and a flip-flop output end, wherein the preset end is coupled to an output end of the signal extracting circuit so that when the preset end receives the pulse signal, and a maintaining time of the pulse signal is maintained for a predetermine time, the flip-flop output end is set to a high voltage level, and the clear end receives a reset signal; a latch circuit coupled to the flip-flop output end and determining whether to output a state of the flip-flop output according to the reset signal; and a light sign coupled to the latch circuit and operating according to a state of an output end of the latch circuit.