Patent ID: 6974745
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A method of manufacturing semiconductor devices, comprising the steps of: forming a plurality of gates on a semiconductor substrate; forming one or more p+ source/drain junctions in the semiconductor substrate by implanting first ions; forming an insulation layer on an entire surface of the semiconductor substrate to coat the plurality of gates; selectively removing the insulation layer by using a first mask pattern to form a plurality of contact holes, which expose at least one source/drain junction and a conductive layer of at least one of the plurality of gates in the semiconductor substrate; removing the first mask pattern and forming a second mask pattern on the selectively removed insulation layer, the second mask pattern exposing only one or more the p+ source/drain junctions in the semiconductor substrate; implanting dopant ions again into one or more of the p+ source/drain junctions in the semiconductor substrate by using the second mask pattern as a mask; removing the second mask pattern and rapid thermal annealing the entire substrate in an activation temperature range of dopant which is implanted in the ion implantation step; and burying the contact holes with conductive material to form a bit line contact plug in each contact hole.