Patent ID: 8045360
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell that stores information based on a resistance value between an input/output terminal and a power supply terminal, or an ON current value of a cell transistor connected to the input/output terminal; a bit line connected to the input/output terminal that inputs and ouputs the information to and from the memory cell, respectively; a first field-effect transistor that works as a single-ended sense amplifier having a gate connected to the bit line that amplifies a data signal on the bit line; a second field-effect transistor connected to the bit line that controls a potential of the bit line to a first predetermined potential; a third field-effect transistor that supplies an output signal of the first field-effect transistor to a global bit line; and a global bit line sense amplifier connected to the global bit line that detects a signal on the global bit line, wherein the first predetermined potential of the bit line varies in accordance with a current flowing through the memory cell, and the first field-effect transistor flows a current in accordance with the varied potential of the bit line.