Patent ID: 7471540
Filing Date: 2008-12-30
Classification: G11C,H01L

Abstract:
1. A programmable memory cell comprising: a pass transistor having a gate, a gate dielectric underlying the gate, and n-type first and second doped regions in a P-well formed in a substrate, said n-type first and second doped regions in a spaced apart relationship to define a channel region therebetween under the gate; and a MOS data storage element having a gate, an ultra-thin dielectric underlying the gate, and a n-type first doped region in a P-well formed in the substrate, said n-type first doped region being coupled to the n-type first doped region of the pass transistor, said MOS data storage element being programmed by breaking down said ultra-thin dielectric; wherein said P-well is formed in a deep N-well.