Patent ID: 7102925
Filing Date: 2006-09-05
Classification: G11C,H01L

Abstract:
1. A flash memory device, comprising: a latch means for latching an address signal; a first switching means for selectively outputting an output signal of the latch means or its inverted signal according to a boot location select signal and its inverted signal; a first carry counter for outputting a bank read signal and a first carry output signal according to the output signal of the first switching means, a first carry input signal and a plurality of control signals; a second carry counter for outputting a bank write signal and a second carry output signal according to the output signal of the first switching means, a second carry input signal and the plurality of the control signals; a second switching means for selectively outputting the bank read signal or the bank write signal to control the operation of a first bank, according to a first bank select signal and its inverted signal; and a third switching means for selectively outputting the bank read signal or the bank write signal to control the operation of a second bank, according to a second bank select signal and its inverted signal.