Patent ID: 8694818
Filing Date: 2014-04-08
Classification: G06F

Abstract:
1. A control circuit comprising; a plurality of clock synchronization units configured to shift an input signal in response to sampling clock signals which are inputted thereto; a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal; and a plurality of clock sampling units configured to sample clock signals for sampling periods defined by signals, which are activated before the signals inputted to the plurality of clock synchronization units are activated, thereby generating the sampling clock signals, wherein the plurality of clock sampling units supplies the sampling clock signals to the plurality of clock synchronization units in response to a plurality of sampling control signals to control output periods of the sampling clock signals, wherein the plurality of clock sampling units correspond to the plurality of clock synchronization units in a one-to-one manner and comprise: