Patent ID: 6740561
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A method of manufacturing a CMOS semiconductor device including an N-channel MOS transistor and a P-channel MOS transistor, the method comprising the steps of:forming source, drain and channel regions of the N-channel MOS transistor and the P-channel MOS transistor in a semiconductor substrate; forming a gate insulating film over the channel regions; nitriding the gate insulating film; performing a thermal treatment on the CMOS device in an inert gas atmosphere after performing the step of nitriding the gate insulating film; forming a gate electrode of each of the N-channel MOS transistor and the P-channel MOS transistor on the gate insulating film; and introducing a p-type impurity into the gate electrodes such that the gate electrodes of the N-channel MOS transistor and the P-channel MOS transistor have a p-type conductivity.