Patent ID: 6791141
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A semiconductor construction, comprising:a pair of discrete stacks over the a substrate and spaced from one another by an intervening gap, the stacks comprising top surfaces and sidewall surfaces extending from the top surfaces to the substrate, wherein each of the stacks comprises: a tunnel oxide layer over the substrate; a floating gate physically against and over the tunnel oxide layer, the floating gate having an inner first portion beside the tunnel oxide layer and an outer second portion spaced from the tunnel oxide layer by the inner first portion, the inner first portion containing a concentration of conductivity-enhancing impurity which is greater than a concentration of conductivity-enhancing impurity contained by the outer second portion; a dielectric layer over the outer second portion; and a conductive line over the dielectric layer; a source/drain region within the substrate and between the stacks, wherein the intervening gap and the source/drain region have widths and the source/drain region width is less than or equal to the intervening gap width; and a first oxide layer extending along the top surfaces and sidewall surfaces of the stacks, wherein the first oxide layer is physically against the floating gate, dielectric layer and conductive line along the sidewall surfaces of the stacks.