Patent ID: 6711073
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A computer system, comprising:an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and an integrated circuit memory device a plurality of externally accessible terminals coupled to a processor bus; and an active termination circuit coupled to at least one of the externally accessible terminals, each active termination circuit comprising: a first controllable impedance device coupled between a first supply voltage and the externally accessible terminals, the impedance of the first controllable impedance device being controlled by a first impedance control signal; a second controllable impedance device coupled between a second supply voltage and the externally accessible terminals, the impedance of the second controllable impedance device being controlled by a second impedance control signal; a first control circuit coupled to provide the first impedance control signal to each first controllable impedance devices, the first control circuit comprising: a third controllable impedance device coupled between a third supply voltage and a first feedback node, the third controllable impedance device being different from the first and second controllable impedance devices, and the first feedback node being different from the external terminal, the impedance of the third controllable impedance device being controlled by the first impedance control signal; a first predetermined resistance coupled between the first feedback node and a fourth supply voltage, the third controllable impedance device and the first predetermined resistance forming a voltage divider between the third and fourth supply voltages to produce a first feedback voltage at the first feedback node; and a first comparator circuit comparing the first feedback voltage to a first reference voltage, the first comparator circuit causing the first impedance control signal to vary so that the first feedback voltage is substantially equal to the first reference voltage; and a second control circuit coupled to provide the second impedance control signal to each second controllable impedance devices, the second control circuit comprising: a second predetermined resistance coupled between a fifth supply voltage and a second feedback node, a fourth controllable impedance device coupled between the second feedback node and a sixth supply voltage, the fourth controllable impedance device being different from the first and second controllable impedance devices, and the second feedback node being different from the external terminal, the impedance of the fourth controllable impedance device being controlled by the second impedance control signal, the second predetermined resistance and the fourth controllable impedance device forming a voltage divider between the fifth and sixth supply voltages to produce a second feedback voltage at the second feedback node; and a second comparator circuit comparing the second feedback voltage to a second reference voltage, the second comparator circuit causing the second impedance control signal to vary so that the second feedback voltage is substantially equal to the second reference voltage.