Patent ID: 9117539
Filing Date: 2015-08-25
Classification: G06F,G11C

Abstract:
1. A flash memory device comprising: a memory array comprising a plurality of flash memory cells arranged in matrix structure comprising a plurality of word lines and a plurality of bit lines, the plurality of flash memory cells divided into multiple program blocks; a program voltage providing portion in communication with the plurality of flash memory cells to provide a program voltage to a selected word line in the plurality of word lines; a page buffer portion comprising a plurality of page buffers, each page buffer corresponding to one of the program blocks and in communication with bit lines in its corresponding program block to provide program data to the bit lines of the corresponding program block; and a control signal generating portion in communication with the plurality of page buffers to provide a plurality of buffer control signals in each one of a sequence of program loops to the plurality of page buffers in accordance with an incremental step pulse program method, the buffer control signals in each program loop sequentially activated with a time interval between subsequent buffer control signals, the time interval decreasing with each loop in the sequence of program loops and the program voltage provided by the program voltage providing unit increasing with each loop in the sequence of program loops.