Patent ID: 7602001
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A capacitorless one transistor DRAM cell, comprising: a pair of spaced source/drain regions received within semiconductive material; an electrically floating body region disposed between the source/drain regions within the semiconductive material; the floating body region having a base, an insulative layer being received against the base, conductively doped semiconductive material being received against the insulative layer beneath the base; a first gate spaced apart from and capacitively coupled to the body region between the source/drain regions; and a pair of opposing conductively interconnected second gates spaced and electrically isolated from the first gate, and received laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the body region laterally outward of the first gate and capacitively coupled to the body region between the pair of source/drain regions.