Patent ID: 7321251
Filing Date: 2008-01-22
Classification: H03F

Abstract:
1. A bias circuit comprising: a transistor formed in a substrate and having a gate, source, and drain; and a bias adjustment circuit having a resistance-dividing circuit for dividing a voltage supplied from a bias voltage supply line to produce a voltage applied between said gate of said transistor and a reference potential node, said bias adjustment circuit having a first resistance element connected directly between the bias voltage supply line and the gate of said transistor, and a second resistance element connected between said gate of the transistor and the reference potential node, wherein said first resistance element is diffused resistor having a resistance region comprising a doped semiconductor region, wherein said resistance region and the gate of said transistor are formed in the same substrate simultaneously in a single fabrication step and have an equal diffusion depth and impurity concentration, wherein variations in said fabrication step have an equal effect on the diffusion depth and impurity concentrations of said resistance region and the gate of said transistor, and wherein said bias circuit lowers the resistance of said first resistance element when the threshold voltage of said transistor is relatively high, and raises the resistance of said first resistance element when the threshold voltage of said transistor is relatively low.