Patent ID: 6865710
Filing Date: 2005-03-08
Classification: H03M,H04L

Abstract:
1. Butterfly processor arrangement for use in telecommunications decoding, said arrangement comprising: first and second add-compare-select modules, said modules each receiving first and second input path metrics supplied to said arrangement and wherein each said module comprises log-sum correction means coupled to compare and select components of said module and a controllable switch for selectively coupling outputs of said select component and said log-sum correction means to an output of said module; a branch metric calculator, said branch metric calculator receiving input data and extrinsic data and arranged to generate first and second output branch metrics supplied to each of said add-compare-select modules, said second output branch metric being the arithmetic inverse of the first output branch metric; and means for actuating said switch such that when said select component is output, said arrangement operates for convolutional decoding and when said log-sum correction means is output said arrangement operates for LOGMAP decoding.