Patent ID: 6025259
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming a first layer of interlayer dielectric on a surface of a semiconductor substrate that contains active semiconductor devices;forming a first via having a width W.sub.1 in the first layer of interlayer dielectric;forming a first trench having a width W.sub.2 in the first layer of interlayer dielectric wherein the first via and the first trench form a first dual damnascene structure;planarizing a surface of the first layer of interlayer dielectric and forming a first etch stop layer on the planarized surface of the first layer of interlayer dielectric;forming a second layer of interlayer dielectric on a surface of the first etch stop layer;planarizing a surface of the second layer of interlayer dielectric and forming a second etch stop layer on the planarized surface of the second layer of interlayer dielectric;forming a third layer of interlayer dielectric on a surface of the second etch stop layer;planarizing a surface of the third layer of interlayer dielectric and forming a third etch stop layer on the planarized surface of the third interlayer dielectric;forming a first layer of photoresist on a surface of the third etch stop layer and etching the first layer of photoresist with a pattern having a width dimension of W.sub.1 ;selectively etching a portion of the third etch stop layer exposed by the step of etching the first layer of photoresist, wherein the portion of the third etch stop layer is etched down to the planarized surface of the third layer of interlayer dielectric;removing the first layer of photoresist and forming a second layer of photoresist on the semiconductor device and etching the second layer of photoresist with a pattern having a width dimension of W.sub.2 exposing a portion of the third etch stop layer and a portion of the third layer of interlayer dielectric;selectively etching the portion of the third layer of interlayer dielectric down to the second etch stop layer, wherein a portion of the second etch stop layer is exposed;selectively etching the exposed portion of the second etch stop layer down to the second layer of interlayer dielectric, wherein a portion of the second layer of interlayer dielectric is exposed;selectively etching the portion of the second layer of interlayer dielectric down to the first etch stop layer, wherein a portion of the first etch stop layer is exposed; andselectively etching the exposed portion of the first etch stop layer, selectively etching the exposed portion of the second etch stop layer and selectively etching the exposed portion of the third etch stop layer.