Patent ID: 6743692
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) preparing a semiconductor substrate having a first impurity region exposed in a main surface and having, on said main surface, a gate structure including a gate electrode provided with a first insulating film on a side part thereof; (b) forming an epitaxial layer on said first impurity region so that said first insulating film lies between said epitaxial layer and said gate electrode; (c) forming a second insulating film on a side part of said gate electrode and a whole upper surface of said epitaxial layer; (d) forming an interlayer insulating film on an upper surface of a structure obtained by execution of said step (c); (e) etching said interlayer insulating film using said second insulating film as an etching stopper, thereby forming, in said interlayer insulating film, a first contact hole reaching said second insulating film provided on said epitaxial layer, said second insulating film lying between said gate electrode and said first contact hole; (f) etching said second insulating film exposed by execution of said step (e), thereby forming a second contact hole reaching said epitaxial layer in said second insulating film; and (g) forming a contact plug to fill in said first and second contact holes.