Patent ID: 7003639
Filing Date: 2006-02-21
Classification: G06F,G11C,Y02D

Abstract:
1. A memory controller for controlling a plurality of dynamic memory devices, comprising: device state logic for determining a power state for each memory device of the plurality of dynamic memory devices, including logic for setting the determined power state of at least one respective memory device to a predefined active power state, for setting the determined power state of a second respective memory device to a predefined low-power state, and for setting the determined power state of a third respective memory device to a predefined mid-power state; memory configured to store the power state of at least one memory device of the plurality of memory devices, and to further configured to store open page status information identifying each open page of at least one memory device in the predefined active power state; and command issue circuitry configured to issue power state commands to the dynamic memory devices in accordance with the power state determined by the device state logic, wherein the command issue circuitry is configured to issue a mid-power state command to the third respective memory device.