Patent ID: 7733694
Filing Date: 2010-06-08
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising: a semiconductor substrate; a plurality of semiconductor devices being formed on the semiconductor substrate; and a trench formed in the semiconductor substrate to divide adjacent semiconductor devices, wherein each of the semiconductor devices comprises: wherein a plurality of memory cells are formed on the semiconductor substrate in matrix form, wherein each memory cell is formed by a pair of the source/drain regions, the channel region, the floating gate electrode, and the control gate electrode, wherein the source/drain regions and the channel region of each memory cell form a row selection line, wherein the control gate electrode of each memory cell forms a column selection line, and the channel region being located at a junction of the row selection line and the column selection line between a pair of the source/drain regions in a first horizontal direction corresponding to the row selection line and between a pair of floating gate electrodes in a second horizontal direction corresponding to the column selection line.