Patent ID: 8880922
Filing Date: 2014-11-04
Classification: G06F,Y02D

Abstract:
1. A computer comprising: a processor having a normal mode that operates at a first frequency and a power-saving mode that operates at a second frequency that is lower than the first frequency; a power-saving control unit; a power sensor unit that measures power consumption; and a path for supplying an interrupt signal from the power sensor unit to the power-saving control unit, wherein the power sensor unit compares a power consumption upper limit value defined by the power-saving control unit with measured power consumption, and outputs the interrupt signal directly to the processor and to the power-saving control unit if the measured power consumption exceeds the power consumption upper limit value, when the interrupt signal is inputted, the power saving control unit outputs to the processor a signal that is equivalent to the interrupt signal and outputs to the power sensor unit an instruction to the power sensor unit to deactivate the interrupt signal; when the interrupt signal or the signal that is equivalent to the interrupt signal is inputted, the processor switches from the normal mode to the power-saving mode, the power sensor unit: