Patent ID: 6295581
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A memory access system comprising:a memory that includes a plurality of memory blocks,a cache memory that includes a plurality of cache locations,a cache controller operably coupled to receive client commands from a client process, wherein the cache controller generates fill commands, flush commands, and memory commands, based on the client commands;a fill processor operably coupled to process the fill commands and store a source memory block of the plurality of memory blocks into a destination cache location of the plurality of cache locations;a flush processor operably coupled to process the flush commands and store a source cache location of the plurality of cache locations into a destination memory block of the plurality of memory blocks;a memory command processor operably coupled to process the memory commands and transfer a data item to and from a cache location of the plurality of cache locations from and to the client process; and wherein the processing of the memory commands by the memory command processor is dependent upon the fill commands in the fill buffer, and independent of the flush commands in the flush buffer.