Patent ID: 6713880
Filing Date: 2004-03-30
Classification: H01L,H05K,Y02P

Abstract:
A semiconductor device comprising:a semiconductor chip having a principal surface provided with a plurality of electrode pads; an elastic layer formed on a region excluding the plurality of electrode pads on the principal surface of the semiconductor chip; a plurality of contact pads arranged two-dimensionally on the elastic layer on the principal surface of the semiconductor chip; a wiring layer electrically connected to at least one of the plurality of electrode pads and electrically connected to at least one of the plurality of contact pads, thereby establishing rewiring connection; an insulative resin layer formed on a region excluding the plurality of contact pads on the principal surface of the semiconductor chip; a protruded electrode provided on, and protruding from, each of the plurality of contact pads; and an underfill material layer provided on the insulative resin layer in such a manner that a top of the protruded electrode is exposed from the underfill material layer; wherein the top of the protruded electrode is projected and exposed from the upper surface of the underfill material layer by 1 um to 200 um.