Patent ID: 6493773
Filing Date: 2002-12-10
Classification: G06F

Abstract:
In a system comprising a data bus, first and second electronic modules connected to said bus, and a FIFO that is connected to said bus and that is located on one of said first and second electronic modules, a method of controlling data transfer between said first and second modules via said FIFO, the method comprising the steps of:pre-defining a certain value as representing non-valid FIFO data; reading a data element from a given location within the FIFO with the second module; comparing the data element read from the FIFO to the pre-defined value to determine whether the FIFO is empty; waiting to read from the given location by the second module if the data element matches the pre-defined value; providing a first READ pointer on-board to said first module; providing a second READ pointer on-board to said second module; and upon the occurrence of the first module reading data from the FIFO at a FIFO location indicated by the first READ pointer, incrementing both of the READ pointers.