Patent ID: 7346746
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A method of sharing a memory module between a plurality of processors comprising: dividing the memory module into n banks, where n=at least 2, enabling the memory module to be accessed by one or more processors simultaneously; mapping the memory module to allocate sequential addresses to alternate banks of the memory module; storing data words in the memory module, wherein data words in sequential addresses are stored in alternate banks due to the mapping of the memory module; providing a first signal path, the first signal path coupling a cache to a processor and the memory module when selected, the cache enabling the processor to fetch a plurality of data words from different banks simultaneously; dividing the bank into x blocks, where x=at least 1, wherein a block can be accessed by one of the plurality of processors at any one time; determining whether contention has occurred, wherein two or more processors are accessing the same address range at any one time, the address range coincides with at least one block; synchronizing the processors to access different banks when contention has occurred, wherein the step of synchronizing the processors comprises inserting wait states for processors with lower priorities when contention occurs; and activating the first signal path when contention has occurred.