Patent ID: 8829968
Filing Date: 2014-09-09
Classification: H01L,H03K

Abstract:
1. A semiconductor integrated circuit device comprising: a first power line; a second power line; a third power line; a fourth power line; a first virtual power line; a first MOS transistor connected between the first virtual power line and the second power line, and supplying a first operating potential from the second power line into the first virtual power line; a first controller controlling the first MOS transistor to supply the first operating potential from the second power line to the first virtual power line; a first circuit block having a plurality of first CMOS circuits connected between the first power line and the first virtual power line and supplied with a first operating voltage which is a difference between a potential of the first power line and the first operating potential; a first conversion circuit supplied with a second operating voltage which is a difference between the potential of the first power line and a potential of the second power line, and an output of the first circuit block being inputted into the first conversion circuit; a second conversion circuit supplied with a third operating voltage which is a difference between a potential of the third power line and a potential of the fourth power line, and output of the first conversion circuit being inputted in to the second conversion circuit; a second virtual power line; a second MOS transistor connected between the second virtual power line and the fourth power line, and supplying a second operating potential from the fourth power line into the second virtual power line; a second controller controlling the second MOS transistor to supply the second operating potential from the fourth power line to the second virtual power line; and a second circuit block having a plurality of second CMOS circuits connected between the third power line and the second virtual power line, and supplied with a fourth operating voltage which is a difference between a potential of the third power line and the second operating potential, wherein when the first MOS transistor supplies the first operating potential into the first virtual power line, the first controller outputs a first controlling signal in a first state to the first conversion circuit, and the first conversion circuit outputs a signal changing according to a change of the output of the first circuit block to the second conversion circuit, wherein when the first MOS transistor cuts off a supply of the first operating potential into the first virtual power line, the first controller outputs the first controlling signal in a second state to the first conversion circuit, and the first conversion circuit fixes a potential of its output to a potential of the first power line or a potential of the second power line, wherein when the second MOS transistor supplies the second operating potential into the second virtual power line, the second controller outputs a second controlling signal in a first state to the second conversion circuit, and the second conversion circuit outputs a signal changing according to a change of the output of the first circuit block to the second circuit block, and wherein when the second MOS transistor cuts off a supply of the second operating potential into the second virtual power line, the second controller outputs the second controlling signal in a second state to the second conversion circuit, and the second conversion circuit fixes a potential of its output to a potential of the third power line or a potential of the fourth power line.