Patent ID: 6546479
Filing Date: 2003-04-08
Classification: G06F

Abstract:
In a computer system including a processor having a first data bus width coupled to a memory having a second data bus width by a memory interface unit bridging the dissimilar first and second data bus widths, a method of fetching instructions comprising:a) initiating a first instruction fetch that requires N bytes, where N is an integer, and where the instruction includes an operation code; b) performing N memory transactions on the second bus to transfer N bytes from the memory to the memory interface unit, and assembling a complete instruction; c) presenting the N bytes of the instruction to the processor over the first bus in one transfer; d) determining, in the memory interface unit, whether the operation code of the instruction corresponds to a pre-defined instruction; and e) presenting, if the determination in (d) is affirmative, a first predetermined instruction to the processor over the first bus, in response to a second instruction fetch initiated sequentially to the first instruction fetch.