Patent ID: 6295223
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A random access memory device comprising:a word line arranged in a first direction;a first bit line arranged in a second direction;a memory cell positioned at an intersection of the word line and the first bit line;a second bit line arranged in the second direction;a sense amplifier coupled to the first and second bit lines for sensing and amplifying a voltage difference on the first and second bit lines; anda reference voltage supplying circuit for supplying the second bit line with a reference voltage responsive to first and second switching control signals, the reference voltage supplying circuit comprising a coupling capacitor having a first and second plates, a first switching device having a first, second, and third terminals, the first terminal being connected to the second bit line, the second terminal being connected to the first plate of the coupling capacitor, and the third terminal receiving the first switching control signal and a second switching device having a fourth, fifth, and sixth terminal, the fourth terminal being connected to the second plate of the coupling capacitor, the fifth terminal being connected to a first power node, and the sixth terminal receiving the second switching control signal, the first power node receiving a power supply voltage.