Patent ID: 8890231
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; first and second fin-type active areas arranged on the semiconductor substrate, aligned in a first direction, and extending in a second direction crossing to the first direction; a first memory cell on the first fin-type active area; and a second memory cell on the second fin-type active area, wherein the first memory cell includes a first gate insulating layer on the first fin-type active area, a first charge storage layer arranged on the first gate insulating layer and in which a width thereof in the first direction becomes narrower upward from below, a first inter-electrode insulating layer formed along a first surface of an upper portion of the first charge storage layer from a first lowest edge on one side of the first surface to extend over a top of the first charge storage layer to a second lowest edge on another side of the first surface in the first direction, and a control gate electrode arranged above the first charge storage layer via the first inter-electrode insulating layer and extending in the first direction, the second memory cell includes a second gate insulating layer on the second fin-type active area, a second charge storage layer arranged on the second gate insulating layer and in which the width thereof in the first direction becomes narrower upward from below, a second inter-electrode insulating layer formed along a second surface of an upper portion of the second charge storage layer from a third lowest edge on one side of the second surface to extend over a top of the second charge storage layer to a fourth lowest edge on another side of the second surface in the first direction, and the control gate electrode arranged above the second charge storage layer via the second inter-electrode insulating layer, the first and second inter-electrode insulating layers have a first contact portion through which both are in contact with each other in the first direction, and thicknesses of the first and second inter-electrode insulating layers in the first contact portion in a third direction perpendicular to the first and second directions are smaller than thicknesses of the first and second inter-electrode insulating layers in the third direction in top portions of the first and second charge storage layers respectively, wherein the first inter-electrode insulating layer and the second inter-electrode insulating layer are separate layers which contact each other at a point that is above the first, second, third, and fourth lowest edges, and that is below a top of the charge storage layer.