Patent ID: 6553435
Filing Date: 2003-04-22
Classification: G06F

Abstract:
A method of providing memory access, the method comprising:operating a processing core in response to a first clock signal, wherein the processing core is operable to implement primary processing functions of a processor; operating an input/output interface in response to a second clock signal which is asynchronous with the first clock signal, the input/output interface being operable to provide an interface between the processor and a device; in response to a request for a first DMA transfer: writing data to a data buffer accessible to both the processing core and the input/output interface; and providing the data from the data buffer to a destination; synchronizing transfer of control signals between the processing core and the input/output interface, and in response to a read request for a second DMA transfer, transferring the data from the data buffer to a second destination, wherein the data transferred in response to a request for the second DMA transfer was written to the data buffer for the first DMA transfer.