Patent ID: 7555737
Filing Date: 2009-06-30
Classification: G06F

Abstract:
1. An auxiliary method for circuit design performed by a computer system adapted to carry out the method, said method comprising the steps of: a) implementing a first physical design according to a first netlist to obtain a first physical layout of a circuit; b) processing the first physical layout of the circuit to obtain a first timing data; c) performing timing verification of the first netlist according to the first timing data; d) modifying the first netlist into a second netlist if the first netlist does not pass the verification, while defining a first modified portion of netlist; e) processing the first modified portion of netlist with an incremental delay calculation for calculating a timing data, and when a pin transition timing data of each cell included in the first modified portion of netlist is unknown, deriving an input transition timing data and an output effective capacitance from the timing data, deriving a solution set consisting of a plurality of solutions of the input transition timing data and the output effective capacitance by way of numerical analysis, and selecting one of the solutions according to a practical design, thereby obtaining a second timing data; f) performing timing verification of the second netlist according to the first timing data that is partially modified with the second timing data; and g) modifying the first physical design into a second physical design according to the second netlist if the second netlist passes the timing verification.