Patent ID: 7913131
Filing Date: 2011-03-22
Classification: G01R

Abstract:
1. An integrated circuit comprising: a scan chain cell having a functional path used in non-test operation between a functional input and a cell output, said functional path being controlled by a functional clock signal; and functional circuitry clocked by said functional clock signal and coupled to said cell output so as to receive an input signal to be processed by said functional circuitry; wherein said scan chain cell has: inverting circuitry coupled to said cell output to generate an inverted signal having a value opposite to said input signal; inverted value selecting circuitry coupled to said inverting circuitry and responsive to a test selecting signal to select said inverted signal as a next signal output from said cell output; and output signal holding circuitry responsive to a hold signal to hold unchanged a signal value at said cell output, wherein said scan chain cell is part of a wrapper scan chain providing test access to signal nodes within said integrated circuit that are not directly accessible from outside said integrated circuit, wherein said test selecting signal is shared by a plurality of scan chain cells within said wrapper scan chain.