Patent ID: 8598630
Filing Date: 2013-12-03
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other; a plurality of transistors formed in the first region; an alignment mark formed in the second region, the alignment mark having a plurality of active regions extending in a first direction; and a dummy gate structure formed over the alignment mark, the dummy poly gate structure having a plurality of lines extending in a second direction different from the first direction, wherein each line in the plurality of lines is divided into a further plurality of spaced parallel lines that each span across every active region in the plurality of active regions in the second direction; wherein the plurality of active regions of the alignment mark and the plurality of lines of the dummy gate structure form a checker board pattern when viewed in a third direction perpendicular to the first and second directions.