Patent ID: 7386681
Filing Date: 2008-06-10
Classification: G06F

Abstract:
1. A cache, comprising: a stall/reorder unit configured to receive snoop requests and store information about said snoop requests in a plurality of queues; a plurality of latches, wherein said plurality of latches store clock cycle information indicative of durations that information about said snoop requests reside in associated queues of said plurality of queues; an arbiter coupled to said stall/reorder unit, wherein said arbiter selects a processor request or a snoop request to be serviced, wherein if said arbiter selects said processor request, then information about said snoop request which was not selected for servicing is maintained in an associated queue of said plurality of queues for a next clock cycle; and a realignment unit coupled to said stall/reorder unit, wherein if said arbiter selects said snoop request to be serviced, then said realignment unit receives one or more counter bits associated with said selected snoop request that indicates a number of clock cycles that information about said selected snoop request resided in said associated queue of said plurality of queues; wherein if said one or more counter bits indicates that said number of clock cycles that information about said selected snoop request resided in said associated queue of said plurality of queues is less than n clock cycles, then said realignment unit stores a result for said selected snoop request in a queue for said n clock cycles minus said number of clock cycles that information about said selected snoop request resided in said associated queue of said plurality of queues, wherein n is a positive integer.