Patent ID: 6063529
Filing Date: 2000-05-16
Classification: G03F,H01L,Y10S

Abstract:
A mark for measuring an overlay accuracy between a first pattern which is one of at least three target patterns formed during manufacture of a semiconductor device and a second pattern which is another one of the target patterns and formed after the formation of the first pattern, the mark comprising:a first overlay measurement pattern consisting of a plurality of unit measurement marks with a tetragonal through hole in a central portion, wherein no two tetragonal holes are the same size, and wherein said unit measurement marks being spaced by a selected distance from each other in a non-overlapping manner; anda second overlay measurement pattern of a box-shape mark formed in the through hole of the innermost unit measurement mark of the unit measurement marks, wherein each unit mark of said first and second overlay measurement patterns respectively corresponds to said first and second patterns of said semiconductor device.