Patent ID: 7288461
Filing Date: 2007-10-30
Classification: G03F,H01L

Abstract:
1. A method for forming an interconnect, comprising: providing a substrate having a device region and an alignment region; forming a first film layer over the substrate; removing a portion of the first film layer to form a first alignment mark pattern in the alignment region; forming a first conductive layer to fill the first alignment mark pattern to form a first alignment mark; forming a second film layer over the first film layer; removing a portion of the second film layer to form a plurality of openings in the device region and to form a second alignment mark pattern in the alignment region; forming a second conductive layer to fill the openings to form a plurality of first conductive wires and to fill the second alignment mark pattern to form a second alignment mark, wherein the second alignment mark is composed of a plurality of second conductive wires, the first alignment mark is located in a first region corresponding to a second region in which the second alignment mark is located and the first alignment mark at least contain a third region directly under a space between each two adjacent second conductive wires; forming a third film layer and a hard mask layer over the second film layer sequentially; removing a portion of the hard mask layer and the third film layer to form a plurality of via openings in the hard mask layer and the third film layer in the device region; and forming a third conductive layer in the via openings.