Patent ID: 8988960
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A memory module configured to perform a read operation, the memory module comprising: a bit cell configured to store a logical value and to output the logical value via a first bit line and a second bit line; a first logic gate coupled to the first bit line; a second logic gate coupled to the second bit line; a sense amplifier configured to determine the logical value output by the bit cell based on a voltage differential between the first logic gate and the second logic gate; an aggressor driver configured to output a first negative voltage to the first logic gate and to the second logic gate during the read operation, wherein the voltage differential between the first logic gate and the second logic gate is based on the first negative voltage; a first aggressor line coupled to the aggressor driver and capacitively coupled to a column select line; and a second aggressor line coupled to the aggressor driver and capacitively coupled to the column select line.