Patent ID: 7813468
Filing Date: 2010-10-12
Classification: G06F,H03K,Y02D

Abstract:
1. A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of said plurality of bits being lower than a second part of said plurality of bits, said counter circuit comprising: a first counter adding said first part of said plurality of bits and said second value in response to said clock signal to output a third value regarding a result of adding said first and said second values; a second counter adding said second part of said plurality of bits and a fourth value indicated by a carry-out signal from said first counter in response to said clock signal; and a clock transmission control circuit coupled to said first and second counters and receiving said clock signal and said third value to control whether or not to supply said clock signal to said second counter in accordance with said received third value.