Patent ID: 9202744
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of fabricating an interconnection structure, the method comprising: forming a dielectric layer on a semiconductor substrate; patterning the dielectric layer to form a first recession region including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width; forming a guide spacer layer on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region, which is disposed in the first nest-shaped recession region and has a third width that is less than the first width; forming a self-assembling block copolymer material that fills the second recession region; annealing the self-assembling block copolymer material to form a polymer block domain having a circular pillar shape and a polymer block matrix surrounding the polymer block domain to have a cylindrical shape; removing the polymer block domain; and etching the dielectric layer using the polymer block matrix as an etch mask and forming a via cavity under the second nest-shaped recession region.