Patent ID: 8912642
Filing Date: 2014-12-16
Classification: H01L,H05K,Y10T

Abstract:
1. A coreless packaging substrate, comprising: a first dielectric layer having a first surface and an opposite second surface; a plurality of first metal bumps embedded in the first surface of the first dielectric layer, wherein each of the first metal bumps has a first end and an opposite second end, and the second end of the first metal bump is free from protruding from the first surface of the first dielectric layer and is exposed from the first surface for a semiconductor chip to be disposed on the first metal bump; a first circuit layer embedded in and exposed from the second surface of the first dielectric layer, wherein the first end of the first metal bump is embedded in the first circuit layer, and a conductive seedlayer is disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the metal bump; and a built-up structure disposed on the first circuit layer and the first dielectric layer, wherein an outmost layer of the built-up structure has a plurality of conductive pads for an external electronic device to be disposed on the conductive pads.