Patent ID: 9001582
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of memory strings each including multiple memory cells; a plurality of word lines, each connected to a different memory cell in the plurality of memory strings; a plurality of bit lines, each connected to a different memory string; and a column decoder connected to the plurality of bit lines, wherein the column decoder includes a plurality of sense amplifiers, a plurality of data latches, and a data bus connected to and shared by the sense amplifiers and the data latches, the data bus having multiple portions including first and second portions connected through a first switch, the sense amplifiers being connected to the first portion and connected to the second portion via the first portion and the first switch, and the data latches being connected to the second portion and connected to the first portion via the second portion and the first switch.