Patent ID: 7144782
Filing Date: 2006-12-05
Classification: H01L

Abstract:
1. A method of manufacturing, comprising: forming a symmetric transistor gate and an asymmetric transistor gate on a substrate, the symmetric transistor gate having first and second sides, the asymmetric transistor gate having third and fourth sides being positioned substantially perpendicularly to the first and second sides; forming a mask on the substrate with a first opening and a second opening, the first opening being sized to enable implantation of first and second halo regions beneath the symmetric transistor gate, the second opening being sized to enable implantation of a third halo region beneath the asymmetric gate proximate one but not the other of the third and fourth sides; forming the first and second halo regions of a first dosage beneath the first gate by implanting off-axis through the first opening toward the first side and then the second side; and forming the third halo region of a second dosage greater than the first dosage beneath the asymmetric transistor gate by implanting off-axis through the second opening toward the third side and then the fourth side, a portion of the mask preventing a halo region from forming proximate the one of the third and fourth sides.