Patent ID: 7115957
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A transistor formed on a substrate assembly, comprising: a raised drain structure; a raised source structure; a gate located between said source and said drain, wherein a top surface of said raised drain structure, a top surface of said raised source structure, and a top surface of said gate are positioned substantially within a common plane; a first capping layer in communication with at least a portion of said gate and said source; a first portion of a gate oxide structure in communication with at least a portion of said gate and said source; a first pocket implant junction located in said substrate assembly, said first pocket implant junction comprising a first high dose dopant implant and defining a first low-resistance path, wherein said first pocket implant junction is in communication with said source predominantly along a non-sidewall portion thereof and extends under a first portion of said gate; a second capping layer in communication with at least a portion of said gate and said drain; a second portion of said gate oxide region in communication with at least a portion of said gate and said drain; a second pocket implant junction located in said substrate assembly, said second pocket implant junction comprising a second high dose dopant implant and defining a second low-resistance path, wherein said second pocket implant junction is in communication with said drain predominantly along a non-sidewall portion thereof and extends under a second portion of said gate; a first field oxide region at least partially recessed within the substrate assembly and in communication with the raised drain structure; and a second field oxide region at least partially recessed within the substrate assembly and in communication with the raised source structure.