Patent ID: 7501680
Filing Date: 2009-03-10
Classification: B82Y,H01L,Y10S

Abstract:
1. A memory device, comprising: a source region and a drain region in a substrate, wherein the source and drain region are spaced apart from each other; a memory cell on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; and a control gate on the memory cell; wherein the memory cell includes a first tunneling oxide layer on the substrate, a second tunneling oxide layer on the first tunneling oxide layer, and a control oxide layer on the second tunneling oxide layer over the nanocrystals, further comprising an amino organic silane layer on the second tunneling oxide layer, wherein the amino organic silane layer is formed of an amino organic silane represented by Formula (1): wherein R R n is an integer from 3 to 20.