Patent ID: 7129420
Filing Date: 2006-10-31
Classification: H01L,Y10T

Abstract:
1. A semiconductor device comprising a plurality of stacked semiconductor devices, each of the stacked semiconductor devices comprising: a semiconductor chip having an integrated circuit; a conductive material that is a bump formed as a projection electrically connected to the integrated circuit; a substrate having the semiconductor chip mounted on a surface thereof, the substrate having an outline larger than the semiconductor chip; an interconnecting pattern having plurality of interconnecting lines formed on the substrate, the interconnecting pattern having a electrical connection contacting the conductive material; first terminals formed in a region outside a region of the substrate in which the semiconductor chip is mounted; and second terminals formed onto a surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals, wherein the semiconductor chip is electrically connected to the first and second terminals and the electrical connection is different from the first terminals and from the second terminals; wherein the semiconductor chips in upper and lower ones of the stacked semiconductor devices are electrically connected, wherein one of the first terminals, one of the second terminals and the electrical connection contacting the conductive material are part of one of the said interconnecting lines.