Patent ID: 6281715
Filing Date: 2001-08-28
Classification: H03K,H04L

Abstract:
A line driver circuit that provides a differential signal to an external circuit, the line driver circuit comprising:a current steering circuit;a current source coupled to the current steering circuit and configured to provide a first drive current to the current steering circuit;a pre-emphasis circuit coupled to the current steering circuit and configured to receive an input signal switching between first and second signal states, and in accordance therewith provide a second drive current during a transition time beginning when the input signal switches between first and second signal states for a first time and ending before the input signal switches between first and second signal states for a second time; andfirst and second output nodes configured to couple to an external circuit and convey third and fourth drive currents, whereinthe current steering circuit is configured to receive the input signal and in accordance therewith direct the first and second drive currents in first and second directions, respectively, to provide the third and fourth drive currents, wherein the third and fourth drive currents together form at the first and second output nodes a differential output signal, andwherein the pre-emphasis circuit includesa current sinking circuit coupled to the current steering circuit;a current sourcing circuit coupled to the current steering circuit, andwherein during the transition time the current sourcing circuit pushes the second drive current into the current steering circuit and the current sinking circuit sinks a portion of a combination of the first and second drive currents from the current steering circuit, andwherein the pre-emphasis circuit further includesa logic circuit coupled to the current sinking circuit and the current sourcing circuit; anda delay circuit coupled to the logic circuit and configured to receive the input signal and in accordance therewith generate a delayed input signal having first and second signal states, and wherein the logic circuit receives the input signal and the delayed input signal and in accordance therewith outputs a transition signal during the transition time, the transition time beginning when the input signal switches between first and second signal states and ending when the delayed input signal switches between first and second signal states.