Patent ID: 8536036
Filing Date: 2013-09-17
Classification: H01L

Abstract:
1. A method of forming complementary transistors of a semiconductor device, the method comprising: forming a doped semiconductor material above a first semiconductor region and a second semiconductor region, said doped semiconductor material having the same conductivity type above said first and second semiconductor regions, said first and second semiconductor regions having formed thereon a gate insulation layer including a high-k dielectric material and a metal-containing cap layer formed below said doped semiconductor material; forming a dielectric cap layer above said doped semiconductor material; forming a first gate electrode structure of a first transistor of a first conductivity type above said first semiconductor region and a second gate electrode structure of a second transistor having a second conductivity type different from said first conductivity type above said second semiconductor region at least from said dielectric cap layer, said doped semiconductor material, said metal-containing cap layer and said gate insulation layer; forming at least drain and source extension regions in said first and second semiconductor regions prior to removing said dielectric cap layer from said first and second gate electrode structures; and after removing said dielectric cap layers, forming a metal silicide in said drain and source regions and in said doped semiconductor material of said first and second gate electrode structures.