Patent ID: 7800878
Filing Date: 2010-09-21
Classification: H02H,H02M,H03K

Abstract:
1. A power supply control circuit comprising: a MOS-FET including a gate and a source and being connected between a DC power supply and a load circuit so that a body diode formed between the drain and the source is forward biased by the DC power supply during normal operation; a holding circuit configured including a capacitor connected between the gate and the source of the MOS-FET and a resistor for discharging the charges stored in the capacitor, the holding circuit for maintaining the ON state of the MOS-FET for a predetermined time when the power supply from the DC power supply is stopped; and a forcing-OFF circuit configured including a switching transistor connected between the gate and the source of the MOS-FET and a bias circuit for controlling the switching transistor, the bias circuit including a Zener diode forward biased by the DC power supply during normal operation and resistors connected in series between the drain and the source of the MOS-FET, the forcing-OFF circuit for turning ON the switching transistor when a drain-source voltage of the MOS-FET becomes larger than a drain-source voltage generated by a field decay surge and turning OFF the MOS-FET irrespective of the operation of the holding circuit, wherein a reverse voltage of the Zener diode is set to a value calculated from the product of a maximum resistance value when the MOS-FET is in the ON state and a peak current of the field decay surge.