Patent ID: 7640526
Filing Date: 2009-12-29
Classification: G06F

Abstract:
1. A method for instantiating a design in a programmable portion of an integrated circuit, the method comprising: obtaining a static portion of the design; reserving a portion of routing resources for static routes as associated with the static portion of the design leaving another portion of the routing resources unreserved with respect to the static routes for being available for use by dynamic portions of the design; generating first configuration information for configuration of the static portion of the design in the programmable portion of the integrated circuit, the first configuration information including first routing information for routing the static routes of the static portion of the design using the reserved portion of the routing resources reserved for the static routes; obtaining at least one modular version of the design, the at least one modular version of the design including a dynamic portion of the dynamic portions of the design; generating second configuration information for configuration of the at least one modular version of the design, the second configuration information including second routing information for routing routes of the dynamic portion of the design using the unreserved portion of the routing resources; merging the first configuration information and the second configuration information to provide third configuration information for at least partial configuration of the programmable portion; and performing the at least partial configuration of the programmable portion responsive to the third configuration information to physically transform the programmable portion from a first operational state to a second operational state; wherein bus macros information for interfacing the static portion of the design with the dynamic portions of the design is the same for both the static portion of the design and the dynamic portions of the design; wherein the dynamic portions are capable of being different from one another without having to vary the static portion of the design for coupling the dynamic portions thereto responsive to the bus macro information being the same in both the first configuration information and the second configuration information; and wherein one or more of the steps are performed by a processor.