Patent ID: 6324635
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A method for address paging emulation, the method comprises the steps of:a) producing an extended logical address in response to a memory access request, wherein the extended logical address includes a logical address and an address extension;b) determining, based on the logical address, whether an entry exists for the memory access request in a translation look aside table;c) when an entry does not exist for the memory access request in the translation look aside table, providing the extended logical address to a plurality of exception handlers;d) identifying one of the plurality of exception handlers to process the extended logical address; ande) generating, by the one of the plurality of exception handlers, a translation look aside table entry for the memory access request, wherein said one of the plurality of exception handlers determines whether the translation look aside table entry identifies reserved memory, and when the translation look aside table entry identifies the reserved memory, alters, when the memory access request is not a system special operation, the translation look aside table entry to produce a modified translation look aside table entry that is not identifying the reserved memory.