Patent ID: 6459616
Filing Date: 2002-10-01
Classification: G11C

Abstract:
An electrically erasable and programmable read only memory (EEPROM) having reduced charge pump loading during a write operation using a high voltage, comprising:a plurality of memory bit cells wherein said plurality of memory bit cells are divided into at least two groups of bit cells for reducing charge pump loading during the write operation using the high voltage, each of said at least two groups of bit cells have a common circuit connection separate from the other ones of said at least two groups of bits cells; and at least two selection circuits, each of said at least two selection circuits connected to the common circuit connection of a respective one of said at least two groups of bit cells, wherein said at least two selection circuits are adapted for selecting one of said at least two groups of bits cells when performing the write operation using the high voltage on at least one bit cell thereof, whereby the charge pump loading is reduced during the write operation using a high voltage.