Patent ID: 8141026
Filing Date: 2012-03-20
Classification: G01R

Abstract:
1. A method of examining an electrical circuit on a semiconductor die, comprising: identifying information about a potential electrical failure from a result of electrical failure analysis (EFA) of the electrical circuit, the electrical circuit including at least a start resource and an end resource; identifying a physical signal path between the start resource and the end resource using a layout design of the electrical circuit; and identifying one or more physical locations of potential manufacturing defects on the semiconductor die in accordance with the identified information about the potential electrical failure and the identified physical signal path; wherein the step of identifying a physical signal path between the start resource and the end resource comprises: identifying an end contact on the end resource; identifying a start contact on the start resource; and identifying a plurality of electrically-connected target contacts in accordance with the layout design, the target contacts establishing the physical signal path between the start resource and the end resource.