Patent ID: 6794711
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A non-volatile memory device comprising:a semiconductor substrate; a source region and a drain region formed in the substrate; an impurity region formed between the source region and the drain region, wherein the impurity region is in a floating state; a vertical structure located between the source region and the impurity region on a first area of the semiconductor substrate such that a tunneling layer, a charge trapping layer, and a blocking layer are sequentially stacked between the source region and the impurity region; a control gate insulating layer located between the source region and the impurity region, the control gate insulating layer adjacent to the vertical structure; a control gate electrode that is formed on the vertical structure and the control gate insulating layer; a gate insulating layer located between the impurity region and the drain region on the semiconductor substrate; and a gate electrode on the gate insulating layer.