Patent ID: 8373462
Filing Date: 2013-02-12
Classification: H03L

Abstract:
1. A delay lock loop, comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, for receiving the input signal, a first delayed output signal and a second delayed output signal, to selectively detect phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result, wherein the first delayed output signal and the second delayed output signal are respectively generated according to the first output signal and the second output signal; and a delay control circuit, for generating a first delay control signal and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop.