Patent ID: 6826068
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:first, second, third, fourth bit lines and a first redundant bit line; a first sense amplifier coupled to the first and second bit lines; a second sense amplifier coupled to the third and fourth bit lines; a redundant sense amplifier coupled to the first redundant bit line; a first column gate transistor having a current path a first end of which is coupled to the first bit line; a second column gate transistor having a current path a first end of which is coupled to the second bit line; a third column gate transistor having a current path a first end of which is coupled to the third bit line; a fourth column gate transistor having a current path a first end of which is coupled to the fourth bit line; a first redundant column gate transistor having a current path a first end of which is coupled to the first redundant bit line; a first column select line coupled to a gate of the first column gate transistor; a second column select line coupled to a gate of the second column gate transistor and passing through the first bit line; a third column select line coupled to a gate of the third column gate transistor and passing through the first and second bit lines; a fourth column select line coupled to a gate of the fourth column gate transistor and passing through the first, second and third bit lines; a redundant column select line coupled to a gate of the first redundant column gate transistor and passing through the first, second, third and fourth bit lines; fifth and sixth column gate transistors each having a current path a first end of which is coupled to a second end of the current pass of the first column gate transistor; seventh and eighth column gate transistors each having a current path a first end of which is coupled to a second end of the current pass of the second column gate transistor; ninth and tenth column gate transistors each having a current path a first end of which is coupled to a second end of the current pass of the third column gate transistor; eleventh and twelfth column gate transistors each having a current path a first end of which is coupled to a second end of the current pass of the fourth column gate transistor; second and third redundant column gate transistors each having a current path a first end of which is coupled to a second end of the current pass of the first redundant column gate transistor; a fifth column select line coupled to a gate of each of the fifth, seventh, ninth and eleventh column gate transistors and a gate of the second redundant column gate transistor; and a sixth column select line coupled to a gate of each of the sixth, eighth, tenth, and twelfth column gate transistors and a gate of the third redundant column gate transistor.