Patent ID: 7646069
Filing Date: 2010-01-12
Classification: H01L,Y10S

Abstract:
1. An integrated circuit read-only memory comprising: an electrically conductive word line; an electrically conductive bit line; and a first memory cell aligned with the bit line and including one storage transistor realized in a semiconductor substrate and including a source connected to a reference potential, a gate connected to the word line, and a drain connected to the bit line by a connection to provide the first memory cell with a first value, wherein the gate of the storage transistor of the first memory cell is formed on the substrate, in a form of a window having an inner contour that delimits the drain in the substrate, and an outer contour that delimits the source in the substrate; and a second memory cell aligned with the bit line and including one storage transistor realized in the semiconductor substrate and including a source connected to the reference potential, a gate connected to the word line, and a drain not connected to the bit line to provide the second memory cell with a second value, wherein the gate of the storage transistor of the second memory cell is formed on the substrate, in a form of a window having an inner contour that delimits the drain of the storage transistor of the second memory cell in the substrate, and an outer contour that delimits the source of the storage transistor of the second memory cell in the substrate.