Patent ID: 9059318
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A complementary metal-oxide semiconductor (CMOS) structure comprising: a substrate; and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate, each FET comprising, a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a first spacer formed on sidewalls of the gate electrode, the first spacer having a substantially constant thickness over the entirety of the sidewalls of the gate electrode, a channel formed directly below the gate electrode, a source stressor spaced apart, laterally, from the first spacer by at least a first distance, and a drain stressor disposed across from the source stressor relative to the gate electrode, the drain stressor spaced apart, laterally, from the first spacer by at least the first distance, wherein the first distance is larger than the thickness of the first spacer.