Patent ID: 6668449
Filing Date: 2003-12-30
Classification: B33Y,H01L,H05K,Y10T

Abstract:
A process of making a semiconductor device package, comprising:providing a substrate having a first surface and a second surface, at least one of the first and second surfaces including a plurality of conductors and including at least one semiconductor device attach site; disposing a solder mask layer on at least part of at least one of the first surface and the second surface of said substrate; providing an opening in the solder mask layer, said opening in the solder mask layer being a combination pin one indicator and alignment fiducial; providing at least one semiconductor device; aligning the at least one semiconductor device to the at least one semiconductor device attach site using said opening in the solder mask layer; aligning a severing deyice using the combination pin one indicator and alignment fiducial; and severing at least a portion of the substrate to obtain at least a portion of said semiconductor device package.