Patent ID: 8766690
Filing Date: 2014-07-01
Classification: G09G

Abstract:
1. A source driver with an automatic de-skew capability, coupled between a source driving device and a time schedule controller, is configured for receiving a data signal and a clock signal from the time controller for driving a display panel, comprising: a data signal delay module, comprising: a setup time register, having a data signal input terminal coupled to an output terminal of the clock signal variable delay circuit; a hold time register, having a clock signal input terminal coupled to an output terminal of the data signal variable delay circuit; a first signal delay unit, coupled between the output terminal of the data signal variable delay circuit and a clock signal input terminal of the setup time register, is configured to generate a second data delay signal; a second signal delay unit, coupled between the output terminal of the clock signal variable delay circuit and a data signal input terminal of the hold time register, is configured to generate a second clock delay signal; a logic circuit, coupled between the setup time register and the hold time register, is configured to generate a control signal to the signal delay module; and a data register, having a clock input terminal coupled to the clock signal variable delay circuit and a data input terminal coupled to the data signal variable delay circuit; wherein the first data delay signal is configured to sample the second clock delay signal and the second data delay signal is configured to sample the first clock delay signal.