Patent ID: 7395468
Filing Date: 2008-07-01
Classification: G01R

Abstract:
1. In scan testing of an integrated circuit with a plurality of scan paths, a method for debugging scan testing failures of the integrated circuit, comprising the steps of: (a) conducting scan tests on the plurality of scan paths; (b) identifying a bad scan path that is generating one or more errors within the plurality of scan paths, wherein all other scan paths within the plurality of scan paths are considered to be good scan paths; (c) assessing test results on the bad scan path and good scan paths; (d) masking the bad scan path to define a segment point that segments the bad scan path into two segments; (e) tracing the source of errors in the bad scan path segment following the segment point when the number of errors of an output of the bad scan path following the segment point are less than a bad path error threshold and the number of errors of outputs on each of the good scan paths are less than a good path error threshold; and (f) shifting the segment point based on an analysis of the errors generated by the bad scan path and the good scan paths and returning to step (d) when the number of errors of an output of the bad scan path are greater than a bad path error threshold or the number of errors on an output of the bad scan path do not exceed the bad scan path error threshold and the number of errors on an output of any of the good scan paths is greater than a good scan path error threshold.