Patent ID: 8698539
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A clock generation circuit for mitigating signal interferences of at least one aggressor block being operated on a first clock signal with a frequency range of at least one victim block in an Integrated Circuit (IC), the clock generation circuit comprising: a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on one or more control signals, wherein the second clock signal is of higher frequency than the first clock signal and an average frequency of the third clock signal is substantially matched to a frequency of the first clock signal and wherein one or more harmonics of the third clock signal do not interfere with the frequency range of the at least one victim block; a FIFO buffer circuit coupled with the gating circuit, configured to receive the first clock signal as a write clock and the third clock signal as a read clock, the FIFO buffer circuit comprising a read pointer clocked by the third clock signal and a write pointer clocked by the first clock signal; and a control circuit coupled with the gating circuit, the control circuit configured to generate the one or more control signals based on an occupancy level of FIFO buffer circuit and a plurality of random numbers, wherein the occupancy level of the FIFO buffer circuit is based on the read pointer and the write pointer.