Patent ID: 6504548
Filing Date: 2003-01-07
Classification: G09G,G11C

Abstract:
A semiconductor integrated device comprising on one semiconductor substrate an image processor in which logic circuits are integrated and first and second image memories each of which has image information stored therein, each of the first and second image memories having a relatively large latency of read operation and a relatively small latency of write operation, wherein:read and write operations for the first and second image memories are performed on the basis of an instruction from the image processor, and the image processor executes a non-operation instruction after an output of a write address, thereby making the latencies of read and write operations for the first and second image memories equal to each other; source data is read from the first image memory in a first period of time after a row address is taken in the first image memory; dot data is read from the second image memory in the first period of time after the row address is taken in the second image memory; and the image processor synthesizes the source data and the dot data in a second period of time to output an address signal and a control signal, thereby performing the writing into the second image memory.