Patent ID: 6727738
Filing Date: 2004-04-27
Classification: G11C,H03L

Abstract:
A delay locked loop comprising:a delay circuit for delaying a first clock to output a second clock; a detector for detecting which of said first and second clocks is advanced in a phase; and a gray code counter using a gray code, responsive to an output of said detector, for selectively generating one of a signal to increase an amount of delay of said delay circuit and a signal to decrease said amount of delay of said delay circuit; wherein said output of said detector indicates that said first clock is in advance of said second clock in a phase or said second clock is in advance of said first clock in a phase; wherein said gray code counter includes: a gray code register for storing said gray code; a binary code converter for converting said gray code into a binary code; an upward carry/downward carry generator using said binary code stored in said binary code converter, to generate an upward carry signal and a downward carry signal; and a carry multiplexer generating from said upward carry signal and said downward carry signal a carry signal corresponding to a result obtained by said detector, for updating said gray code in said gray code register.