Patent ID: 6750090
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first region, a second region with a channel region therebetween, and a control gate, the method comprising the steps of:a) forming a plurality of spaced apart isolation, regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, each of the active regions comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) etching a top portion of the first layer of conductive material to form a pair of raised opposing sharp edges in the first layer of conductive material in each of the active regions that have a length extending in the first direction; c) etching portions of the first layer of conductive material to form a plurality of discrete floating gates in each of the active regions, wherein each floating gate includes a portion of the raised opposing pair of sharp edges; e) forming a plurality of spaced apart blocks of electrically conductive material in each of the active regions, wherein each of the blocks partially overlaps with and is isolated from one of the floating gates; e) forming a plurality of first regions in the substrate, wherein in each of the active regions, each of the floating gates partially overlaps with and is isolated from one of the first regions; and f) forming a plurality of second regions in the substrate, wherein in each of the active regions each of the second regions is spaced apart from the first regions.