Patent ID: 8421158
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A chip structure comprising: a silicon substrate; a resistor in said silicon substrate, wherein said resistor comprises silicon with a dopant; a MOS device comprising a portion in said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a first dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and said first dielectric layer, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said metallization structure, and said second contact point is at a bottom of said second opening, and wherein a third opening in said passivation layer is over a third contact point of a third metal interconnect of said metallization structure, and said third contact point is at a bottom of said third opening, wherein said first contact point is connected to said third contact point through said resistor, wherein said passivation layer comprises a nitride layer; and a third metal layer over said passivation layer and on said first, second and third contact points, wherein said first contact point is connected to said second contact point through a first portion of said third metal layer, wherein said third metal layer comprises a second portion connected to said first portion of said third metal layer through, in sequence, said third contact point, said resistor and said first contact point.