Patent ID: 7221126
Filing Date: 2007-05-22
Classification: G06F,H04L

Abstract:
1. A method for providing a clock cycle margin between the phase of a first clock having a first phase relative to the phase of a second clock having a second phase such that synchronization behaves repeatedly, wherein said first clock is provided by a clock generator in a data processing system, comprising steps of: sampling said second clock with a sampling clock; detecting an edge on said second clock; and stretching said first clock with said clock generator to provide a clock cycle margin between said first phase of said first clock relative to said second phase of said second clock, wherein a falling edge of said first clock is stretched to coincide with a rising edge of said second clock and a clock margin is in the range of approximately 25% to 50% of the clock cycle margin between the two clock edges thereby providing repeatable synchronizing behavior between said first clock and said second clock, and wherein said step of stretching said first clock with said clock generator further comprises stalling said first clock for a selected number of cycles of said sampling clock, wherein said stretching of said first clock to generate the offset clock cycle margin is utilized to ensure repeatability when testing a system to determine a cause of failure.