Patent ID: 7944772
Filing Date: 2011-05-17
Classification: H03L

Abstract:
1. A semiconductor memory device, comprising: a Delay Locked Loop (DLL) for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for receiving the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a Column Address Strobe (CAS) latency.