Patent ID: 7167027
Filing Date: 2007-01-23
Classification: H03K,H03M

Abstract:
1. A latch-type level converter comprising: a first clock-input transistor, connected to a first power super line, receiving at a gate thereof a first clock; a pair of first signal-input transistors receiving at gates thereof differential input signals, wherein each of the first signal-input transistors are coupled to the first clock-input transistor; a second clock-input transistor, connected to a second power supply line, receiving at a gate thereof a second clock; a pair of second signal-input transistors receiving at gates thereof the differential input signals, wherein each of the second signal-input transistors are coupled to the second clock-input transistor; and a latch coupled to each of the first signal-input transistors and each of the second signal-input transistors, wherein: said latch holds data of the differential input signals received by said first and second pair of signal-input transistors; the first and second clocks are differential clocks; and said first and second pair of signal-input transistors are a high-voltage transistor so that said first and second pair of signal-input transistors receives the differential input signals having a voltage greater than a supply voltage which is supplied to said latch.