Patent ID: 6859848
Filing Date: 2005-02-22
Classification: G06F

Abstract:
1. A memory control circuit for arbitrating and selecting a direct memory access (DMA) control information signal received from at least one of a plurality of DMA request blocks and accessing a synchronous dynamic random access memory (SDRAM) on the basis of the selected DMA control information signal, the DMA control information signal including a DMA request signal, a data access signal, an address signal, and a designation signal that designates a burst DMA request number, said memory control circuit comprising: detecting means for detecting a number of possible sequential accesses on the basis of the address signal; comparison means for comparing the burst DMA request number with the number of possible sequential accesses; selecting means for selecting the lesser of the burst DMA request number and the number of possible sequential accesses, based on the result of the comparison made by said comparison means; and setting means for setting the number of sequential DMAs to be executed to the number selected by said selecting means.