Patent ID: 6303449
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of fabrication of an elevated source/drain (S/D) region in a device; comprising the steps of:a) forming first insulating layer over a substrate; said first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to said gate opening; spacer portions of said first insulating layer define said gate opening;b) forming a gate dielectric layer over said substrate in said gate opening;c) forming a conductive layer over said substrate; said conductive layer filling said gate opening and said source/drain (S/D) openings; said conductive layer is doped with dopants;d) planarizing said conductive layer to form a gate over said gate dielectric layer and filling said gate opening and filling said source/drain (S/D) opening to form elevated source/drain (S/D) regions; said conductive layer is planarized so that the top surface of said conductive layer is level with the top surface of said first insulating layer;e) removing said spacer portions to form spacer openings;f) forming LDD regions in said substrate in said spacer opening;g) forming a dielectric layer over said substrate filling said spacer openings; andh) forming source/drain (S/D) regions in said substrate under said elevated source/drain (S/D) regions.