Patent ID: 6316306
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for fabricating a DRAM, comprising the steps of:forming an active region and an insulating region in a semiconductor substrate;forming a pair of word lines arranged in rows adjacent to each other in the active region and the insulating region, said word lines having a spacing .lambda..sub.2 therebetween in the active region and a spacing .lambda..sub.1 therebetween in the insulating region, wherein said spacing .lambda..sub.1 is different from said spacing .lambda..sub.2 ;forming spacers on the peripheries of said word lines;forming source and drain regions in said semiconductor substrate adjacent to said word lines in said active region, said word lines in said active region and said source and drain regions forming a pair of transfer gate transistors;forming conductive plugs connected to said source and drain regions in a self-aligned manner;forming a bit line insulation layer on said pair of word lines;forming a bit line on said bit line insulation layer, said bit line being electrically connected to one of said conductive plugs connected to said source region between said pair of word lines in the active region; andforming a capacitor having an electrode electrically connected to one of said plugs connected to one of said drain regions formed in said active region between one of said word lines in the active region and one of said word lines in said insulating region.