Patent ID: 8716851
Filing Date: 2014-05-06
Classification: H01L,H05K,Y02P

Abstract:
1. A device for fabricating a laminate chip package, comprising: a package design system that provides a laminate package design for a laminate chip package having a plurality of insulator layers and a plurality of patterned conductive layers comprising a first conductive layer, a fourth conductive layer, and two intermediate conductive layers; a design analysis engine that determines transmission line characteristics of signal layers with respect to a voltage reference provided by a nearby source voltage plane and nearby ground potential plane, identifies areas with substandard transmission line characteristics, and identifies a first preferred voltage plane for the first conductive layer within a first area of the laminate package design and a second preferred voltage plane for the first conductive layer within a second area of the laminate package design, wherein the first preferred voltage plane is one of a source voltage plane or a ground plane and the second preferred voltage plane is the other of the source voltage plane and the ground plane; a reference plane adjustment engine that positions signal planes, source voltage planes, and ground planes within the plurality of conductive layers such that a path of the signal plane maintains a relatively consistent impedance from beneath the first area to beneath the second area by a balanced proximity to a conductive layer connected to the source voltage and a conductive layer connected to ground potential, without adding layers to the laminate package design, to form a mixed voltage plane package design; and a package fabrication system that fabricates the laminate chip package based on the mixed voltage plane package design.