Patent ID: 8723607
Filing Date: 2014-05-13
Classification: H03C,H03L,H04L

Abstract:
1. A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input signal to the oscillator; a delay unit for forming a first delayed version of the output signal of the oscillator; sampling means for generating a sequence of digital values representing the output signal of the oscillator at moments synchronised with a reference frequency; a difference unit for generating a feedback signal representing a difference between successive values in the sequence; and a first integrator for integrating a difference between the feedback signal and a signal of a desired output frequency; the input signal to the oscillator being dependent on an output of the first integrator, and wherein the sampling means generates the sequence of digital values as a sum of the output signal of the oscillator and the first delayed version of the output signal of the oscillator.