Patent ID: 8957719
Filing Date: 2015-02-17
Classification: G06F,H03K,H03L,H04L

Abstract:
1. A clock synchronization circuit for capturing an input data bit according to an input clock signal, and for synchronizing and outputting the input data bit, comprising: a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line; and a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal supplied through the clock line, wherein said clock buffer includes an inverter core portion and an electric current suppressing portion, said inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal, said electric current suppressing portion is configured to suppress an amount of the electric current, said electric current suppressing portion is configured to stop supplying the electric current to the clock line when a voltage on the clock line exceeds a first threshold value, and said electric current suppressing portion is configured to stop drawing the electric current from the clock line when the voltage on the clock line becomes less than a second threshold value smaller than the first threshold value.