Patent ID: 6828183
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of forming a high voltage (HV) oxide and peripheral gate for a split-gate flash memory comprising the steps of:providing a semiconductor substrate having a cell area and a peripheral area; forming a first oxide layer over said substrate; forming a floating gate transistor over said first oxide layer over said cell area; forming a second oxide layer over said floating gate transistor, said second oxide serving as a tunnel oxide; forming a first source region in said substrate for said floating gate transistor; forming a cell polysilicon layer over said cell area over said substrate including said second oxide layer; growing a third oxide layer over said substrate including over said cell polysilicon layer and over said peripheral area, said third oxide serving as said high voltage (HV) oxide; forming a peripheral polysilicon layer over said HV oxide layer over said peripheral area; forming a peripheral transistor comprising said peripheral polysilicon layer over said HV oxide layer over said peripheral area; forming a control gate in said cell polysilicon layer by etching said cell polysilicon layer over said first source region over said cell area; forming a second source region for said peripheral transistor.