Patent ID: 6922365
Filing Date: 2005-07-26
Classification: G11C

Abstract:
1. In a memory cell array having word lines, bit lines organized in pairs, and memory cells addressable via the word lines and the bit lines, each of the memory cells having a respective storage capacitor, and each of the storage capacitors being connectable to one of the bit lines of one of the bit line pairs by activation by one of the word lines; a read-out circuit, comprising: an interchanging circuit connected to each of the bit lines of one of the bit line pairs and having a first data output line, a second data output line adjacent said first data output line, a third data output line adjacent said second output line, and a fourth data output line adjacent said third output line; said interchanging circuit being configured to apply the bit lines connected to the storage capacitors to said second and third data output lines by activating the word line and to apply the bit lines not connected to the memory cells to said first and fourth data output lines; a first sense amplifier connected to said first and second data output lines; a second sense amplifier connected to said third and fourth data output lines; and a third sense amplifier connected to said second and third data output lines; said first, second, and third sense amplifiers each being configured to amplify a potential difference on said respective two connected lines.