Patent ID: 8120401
Filing Date: 2012-02-21
Classification: H03K

Abstract:
1. A pulse width modulator comprising: a multiplexer receiving as inputs, combinations of a plurality of clock signals, wherein said clock signals have a predetermined frequency and different phases, wherein said combinations are selected to provide a resolution for a pulse width modulator output, wherein said resolution is substantially equal to a time difference between said phases of said clock signals, wherein said multiplexer is addressed by a signal derived from a number of lower significant bits of a duty cycle signal of said pulse width modulator, and wherein said number of lower significant bits is sufficient to address said plurality of clock signals; an up-counter having a maximum count value; a first comparator asserting a first signal indicating whether an output of said up-counter is greater than said duty cycle signal; a second comparator asserting a second signal indicating whether said output of said up-counter is less than said duty cycle signal; a first latch receiving an output of said first comparator as a set input and an output of said second comparator as a reset input; a second latch receiving said output of said second comparator as a set input and said output of said first comparator as a reset input; an OR gate receiving an output of said multiplexer and an output of said second latch; and an AND gate receiving an output of said OR gate and a complement of an output of said first latch, wherein an output of said AND gate is said output of said pulse width modulator.