Patent ID: 6301647
Filing Date: 2001-10-09
Classification: G06F

Abstract:
An address translation device for providing physical addresses to a physically-addressable cache in an x86-compatible processor capable of operating in real mode and paging mode, said cache including a shadow translation look-aside buffer for storing copies of untranslated physical addresses and a tag sector for storing copies of physical addresses, wherein output of said shadow translation look-aside buffer is directly compared with output of said tag sector, said address translation device comprising:a tag array for storing received untranslated addresses in selected ones of N tag entries in said tag array during real mode operations and paging mode operations; anda data array for storing translated physical addresses corresponding to said untranslated addresses in selected ones of N data entries in said data array, wherein said untranslated addresses stored in said tag array during real mode operations are physical addresses equal to said corresponding translated physical addresses stored in said data array.