Patent ID: 9166159
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A semiconductor construction, comprising: spaced-apart electrical nodes supported by a semiconductor substrate, upper surfaces of the nodes forming a two-dimensional array having rows and columns, with the columns being substantially orthogonal to the rows; nodes within a common row as one another being coupled to one another through wordlines under the rows; bridging structures over the nodes and bridging pairs of nodes to one another; the bridging structures extending in a direction substantially orthogonal to the wordlines; the bridging structures comprising first electrically conductive material stacked over dielectric material; the bridging structures comprising opposing sidewall surfaces; programmable material structures along the sidewall surfaces, the programmable material structures being directly against both the first electrically conductive material and the dielectric material of the bridging structures; each programmable material structure having two opposing sides; one of said sides being directly against both the first electrically conductive material and the dielectric material of the bridging structures and the other of the opposing sides being directly against an insulative structure; the insulative structure comprising three different dielectric materials; one of said three different dielectric materials being configured as a container shape, and another of the three-different dielectric materials being entirely within said container shape; the three different dielectric materials differing in composition relative to one another; and electrically conductive bitlines of second electrically conductive material extending across the bridging structures; the electrically conductive bitlines being over and directly against the first electrically conductive material and the programmable material structures; the electrically conductive bitlines extending along columns of the two-dimensional array.