Patent ID: 6594813
Filing Date: 2003-07-15
Classification: H01L

Abstract:
A method for making a semiconductor cell having a standard architecture, the semiconductor cell is designed to be part of a library of cells that are accessible to a place and route layout tool that uses the semiconductor cell to complete a semiconductor functional circuit that is to be fabricated on a semiconductor chip, the method comprises:defining a plurality of diffusion regions that designate source and drain regions of transistors of the semiconductor cell; defining a polysilicon layout that identifies gate electrodes and interconnections of the semiconductor cell; and defining a local interconnect metallization layout that is patterned to identify a plurality of local interconnect metallization lines that are configured to substantially interconnect selected ones of the source and drain regions and gate electrodes to at least partially define the semiconductor cell, the local interconnect metallization layout is configured to be physically embodied in a material having a resistivity that is greater than that of aluminum.