Patent ID: 6792524
Filing Date: 2004-09-14
Classification: G06F

Abstract:
A processor comprising:an instruction dispatcher operable for dispatching instructions to a plurality of execution units and a branch processor, wherein the branch processor is operable for executing a branch instruction, said branch processor further comprising: a branch history table entry for predicting a path to be taken from the branch instruction as a function of a past prediction for the branch instruction; a counter value indicating an accuracy of past predictions, wherein the counter value is associated with the branch history table entry for the branch instruction indicating the accuracy of past predictions for the branch instruction, circuitry for cancelling a speculative instruction dispatch, associated with the predicted path, when the counter value exceeds a threshold value; an incrementor for increasing the counter value each time a path is incorrectly predicted for the branch instruction; a decrementor for decreasing the counter value each time a path is correctly predicted for the branch instruction; a multiplexor for selecting between the increased value from the incrementor and the decreased value from the decrementor as a function of a resolution of the branch instruction; and circuitry for storing the selected value with the branch instruction in the branch history table.