Patent ID: 8470688
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising the steps of: forming a first damaged region in a first single-crystal semiconductor substrate; bonding the first single-crystal semiconductor substrate and a substrate having an insulating surface with a bonding layer interposed therebetween; separating the first single-crystal semiconductor substrate, so that a first single-crystal semiconductor layer is left over the substrate having the insulating surface; forming a first gate insulating layer over the first single-crystal semiconductor layer; forming a gate electrode over the first gate insulating layer, wherein the gate electrode overlaps the first single-crystal semiconductor layer; forming a first interlayer insulating layer over the gate electrode; planarizing an upper surface of the first interlayer insulating layer, so that a surface of the gate electrode is exposed; forming a second gate insulating layer over the exposed surface of the gate electrode and the first interlayer insulating layer; forming a second damaged region in a second single-crystal semiconductor substrate; bonding the second single-crystal semiconductor substrate and the substrate having the insulating surface with the second gate insulating layer interposed therebetween; and separating the second single-crystal semiconductor substrate, so that a second single-crystal semiconductor layer is left over the second gate insulating layer, wherein the second single-crystal semiconductor layer overlaps the gate electrode and the first single-crystal semiconductor layer, wherein the first single-crystal semiconductor layer and the gate electrode are formed so as to form a first transistor of a complementary circuit, wherein the second single-crystal semiconductor layer and the gate electrode are formed so as to form a second transistor of the complementary circuit, and wherein the gate electrode is a common gate electrode of the first transistor and the second transistor including the second single-crystal semiconductor layer.