Patent ID: 9208887
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells, and a plurality of word lines and a plurality of bit lines; and a data writing unit that writes data to memory cells connected to a first word line among the word lines by applying a program voltage to the first word line one or more times, sets all of the bit lines to write-inhibited states, and applies an additional voltage to the first word line one or more times after data writing to all of the memory cells connected to the first word line is completed, when performing the writing with respect to a second word line different from the first word line among the word lines after performing the data writing to the memory cells connected to the first word line, the data writing unit setting all of the bit lines to write-inhibited states, and applying the additional voltage to the second word line after data writing to all of memory cells connected to the second word line is completed, wherein the data writing unit sets a value of the additional voltage to a value equal to or higher than a last value of the program voltage under existence of one of the bit lines being in a write-permitted state.