Patent ID: 7523351
Filing Date: 2009-04-21
Classification: G06F

Abstract:
1. A system for providing breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device, the system comprising: a first breakpoint generating module capable of generating a first breakpoint message for allowing operation of the first breakpoint generating module to be halted, and said first breakpoint message allowing generation of second breakpoint message which corresponds to said first breakpoint message; and a core processor operatively coupled to said first breakpoint generating module and being responsive to said second breakpoint message for allowing operation of said core processor to be halted and for generating a third breakpoint message which is associated with the halting of said core processor; and a second breakpoint generating module operatively coupled to said core processor and said second breakpoint generating module is responsive to said third breakpoint message for allowing operation of the second breakpoint generating module to be halted.