Patent ID: 8334726
Filing Date: 2012-12-18
Classification: H03L

Abstract:
1. A semiconductor integrated circuit comprising a phase-locked loop circuit including: a phase-frequency comparator; a first charge pump; a second charge pump; a loop filter; a voltage-control oscillator; and a divider, wherein the phase-frequency comparator compares a phase difference between a reference signal and a feedback signal made by an output signal of the divider, and produces first and second output signals as phase comparison output signals resulting from the comparison, wherein the first and second charge pumps operate to charge and discharge the loop filter in response to the first and second output signals from the phase-frequency comparator, respectively, wherein outputs of the first and second charge pumps are connected to the loop filter, wherein an operation mode of the PLL circuit includes a standby state in which locking is stopped, a lock response operation in which locking is started, and a steady lock operation in which the locking started by the lock response operation is continued, wherein, in the standby state of the operation mode of the PLL circuit, at least the phase-frequency comparator, the first and second charge pumps, and the divider of the PLL circuit are controlled to be in cutoff states, wherein a control signal for changing the operation mode of the PLL circuit from the standby state to the lock response operation is supplied to the PLL circuit, and wherein at least the phase-frequency comparator, the first charge pump and the divider of the PLL circuit are released from the cutoff states and start operating in response to the control signal being received at the PLL circuit.