Patent ID: 7428690
Filing Date: 2008-09-23
Classification: H04L

Abstract:
1. A packet communication apparatus used with a memory having a first storage area and a second storage area, comprising: a CPU (Central Processing Unit); a packet communication circuit that transmits and receives packets via a network; communication software executed by said CPU; the first storage area provided in said memory and controlled by said communication software; the second storage area provided in said memory and controlled by said packet communication circuit; and an operation unit that operates with said communication software to copy a transmission packet, stored in the first storage area, to a descriptor area provided in the second storage area and controlled by said packet communication circuit and, at the same time, performs checksum operation for the transmission packet, wherein said packet communication circuit outputs the transmission packet, which is written by said CPU or said operation unit into the second storage area and for which the operation is performed, to the network, wherein, when no checksum information is present in a packet in the first storage area, said operation unit writes a result of a checksum calculation in the packet stored in the second storage area to which the packet is copied as well as in the packet in the first storage area from which the packet is copied.