Patent ID: 6653732
Filing Date: 2003-11-25
Classification: H01L

Abstract:
An electronic component, comprising:a semiconductor chip having a test structure disposed thereon and at least two corner regions, one of said at least two corner regions having no adhesion regions; said test structure having a multi-layer coating including: at least one interconnect layer; a bottom insulation layer; a top insulation layer having a top side; and an intermediate planarization layer having embedded adhesion regions and a bottom side; said test structure including: a measuring through-contact; a top measuring interconnect disposed on said top side of said top insulation layer; a bottom measuring interconnect disposed on said bottom side of said planarization layer; a first measuring contact surface disposed on said top side of said top insulation layer and connected to said top measuring interconnect; a second measuring contact surface disposed on said top side of said top insulation layer and connected through said measuring through-contact to said bottom measuring interconnect; and at least one test through-contact extending through said planarization layer and electrically connected to said top measuring interconnect and to said bottom measuring interconnect.