Patent ID: 6468851
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of fabricating a dual gate electrode CMOS device, comprising the steps of:providing a wafer having an N-MOSFET region and a P-MOSFET region; forming a sacrificial gate layer/doped N+ poly-1 layer/gate insulator layer stack over the wafer; patterning the N-MOSFET sacrificial gate layer to form a once patterned sacrificial gate layer only within the N-MOSFET region, exposing the doped N+ poly-1 layer within the P-MOSFET region; forming an undoped poly-2 layer over the once patterned sacrificial gate layer and the exposed N+ poly-1 layer within the P-MOSFET region; planarizing the undoped poly-2 layer to form a planarized undoped poly-2 layer only within the P-MOSFET region; patterning: the once patterned sacrificial gate layer, the doped N+ poly-1 layer and the gate insulator layer within the N-MOSFET region to form an initial N-MOSFET gate electrode stack having exposed sidewalls; and the planarized undoped poly-2 layer, the doped N+ poly-1 layer and the gate insulator layer within the P-MOSFET region to form an initial P-MOSFET gate electrode stack having exposed sidewalls; forming sidewall spacers adjacent the exposed sidewalls of the initial N-MOSFET and P-MOSFET gate electrode stacks; forming an intermetal dielectric layer adjacent and between the initial N-MOSFET and P-MOSFET gate electrode stacks; removing the initial P-MOSFET gate electrode stack to form a P-MOSFET gate cavity exposing a portion of the wafer; forming a second P-MOSFET gate insulator layer within the P-MOSFET gate cavity over the exposed portion of the wafer; removing the upper sacrificial gate layer of the initial N-MOSFET gate electrode stack to form an N-MOSFET gate cavity; forming a metal layer over the structure, filling the remaining P-MOSFET gate cavity and the N-MOSFET gate cavity; and planarizing the metal layer to remove the excess metal from over the intermetal dielectric layer leaving planarized N-MOSFET metal gate electrode cap within N-MOSFET gate cavity to form a finalized N-MOSFET and planarized P-MOSFET metal gate within the remaining P-MOSFET gate cavity to form a finalized P-MOSFET, thus completing formation of the dual gate electrode CMOS device.