Patent ID: 6259755
Filing Date: 2001-07-10
Classification: H03L,H04L

Abstract:
A data and clock recovery phase locked loop circuit for extracting a clock signal from random input data, said data and clock recovery phase locked loop circuit comprising:delay means for delaying the random input data to produce delayed random input data;data transition detecting means for detecting transitions of the random input data to produce a window signal;phase comparing means connected to said delay means for comparing a phase of the delayed random input data with a phase of a feedback signal to produce a phase compared signal representative of a difference between the phase of the delayed random input data and the phase of a feedback signal;charge pump means connected to said phase comparing means for producing output voltage in response to the phase compared signal;filter means connected to said charge pump means for filtering the output voltage into DC voltage;a voltage controlled oscillator connected to said filter means to generate the clock signal which has a frequency depending on the DC voltage; andmultiplexer means connected to said voltage controlled oscillator, said data transition detecting means, and said phase comparing means for selecting one from a predetermined logical level and the clock signal to supply a selected signal to said phase comparing means as the feedback signal.