Patent ID: 7251176
Filing Date: 2007-07-31
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array which has a plurality of memory cells arranged in a matrix form; a plurality of bit line pairs which transfer data among the memory cells; a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers including a plurality of sense amplifier circuits, and the plurality of sense amplifier circuits being connected respectively to the plurality of bit line pairs to amplify data transferred to the bit line pairs; a plurality of common source lines, each connected to a predetermined number of sense amplifiers among the plurality of sense amplifiers in the sense amplifier bank, to supply first voltage to the sense amplifiers; and a plurality of column selection lines which select the sense amplifiers, wherein the predetermined number of sense amplifiers are connected respectively to different column selection lines.