Patent ID: 9104596
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A memory device comprising: a memory unit including a first subunit and a second subunit; a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data; and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit, wherein the first and second write data and the first and second redundant data are written through a plurality of writing steps, in each of which a part of data is written, at least one of the writing steps for writing the second write data and the second redundant data being carried out before all of the writing steps for writing the first write data and the first redundant data have been carried out, and wherein the control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out.