Patent ID: 7038266
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A microelectronic product comprising: a substrate having exposed therein a first contact region and a second contact region; a first dielectric layer formed over the substrate and a second dielectric layer formed over the first dielectric layer; a capacitor formed interposed between the first dielectric layer and the second dielectric layer, the capacitor also being sandwiched between a first conductor stud that penetrates the first dielectric layer and contacts the first contact region and a second conductor stud that penetrates the second dielectric layer; a contiguous conductor interconnect and conductor stud layer contacting the second contact region and formed into a trench defined within the second dielectric layer and a contiguous via defined within the first dielectric layer; and an etch stop layer interposed between the first dielectric layer and the second dielectric layer wherein the etch stop layer simultancously serves as a floor of the trench and passivates a sidewall of the capacitor.