Patent ID: 7526638
Filing Date: 2009-04-28
Classification: G06F

Abstract:
1. A system for hardware alteration of instructions in a microcode routine, said system comprising: a microcode engine with multiple scratch registers; an arithmetic and logic unit; a floating point unit; an instruction identification register; an instruction register; an instruction decoder unit; and an instruction memory; wherein said instruction register fetches instruction words from said instruction memory; wherein each of said instruction words comprises: an instruction opcode and multiple operands indicating first one or more source registers and a target register; wherein said first one or more source registers correspond to first one or more scratch registers of said multiple scratch registers; wherein said target register corresponds to a second scratch register of said multiple scratch registers; wherein said instruction opcode performs an arithmetic or floating point operation on said one or more source registers and writes the result in said target register; wherein said microcode engine is connected to said arithmetic and logic unit, said floating point unit, said instruction register, said instruction identification register, and said instruction decoder unit; wherein said microcode engine controls integer pipeline and floating point pipeline sequences; wherein said microcode engine interprets said instruction words and microcode entry points fed to it by said instruction decoder unit; wherein said floating point unit or said arithmetic and logic unit write new values to said instruction identification register based on results of previous operations; wherein said microcode engine alters said instruction opcode based on a value in said instruction identification register, by using combination logic; wherein said microcode engine recodes said value in said instruction identification register to one or more recoded values into third one or more scratch registers of said multiple scratch registers, by using combination logic, and said microcode engine alters said multiple operands, by logically ORing said one or more recoded values with said multiple operands, in case of in-order type processor; wherein said microcode engine alters said multiple operands by using a selector based on said value in said instruction identification register, in case of out-of-order type processor; wherein said microcode engine ensures that Read-After-Write operand dependencies are honored by said altered instruction opcode and said altered multiple operands.