Patent ID: 6140189
Filing Date: 2000-10-31
Classification: H01L,Y10S

Abstract:
In the fabrication of a MOS device for ESD protection, selected from the group consisting of NMOS and PMOS transistors, a method for forming a LOCOS transistor with a large drain to gate breakdown voltage comprising the steps of:a) forming a well of silicon including a first dopant, from which source and drain regions are subsequently formed;b) forming a localized area of oxidized silicon (LOCOS) having a length and a first thickness overlying the doped silicon well;c) depositing a thin layer of gate oxide having a second thickness overlying the doped silicon well and the LOCOS area, whereby thin and thick areas of gate oxide are provided;d) depositing, patterning, and doping with a second dopant, a layer of polysilicon overlying a portion of the LOCOS area and the adjoining area of thin oxide, to form a gate electrode having a gate electrode length, whereby a gate electrode is formed over both the thin and thick areas of gate oxide;e) using said gate electrode and said LOCOS area as a mask, light density doping (LDD), with a third dopant, areas of the silicon well to begin the formation of source and drain regions;f) depositing and patterning material having a third thickness selected from the group consisting of oxide and nitride, to form gate sidewalls; andg) using said gate sidewalls as a mask, implanting the source and drain regions with a fourth dopant to complete the formation of a source region adjoining the thin area of gate oxide, and a drain region adjoining the LOCOS area of gate oxide, whereby a transistor having a very large drain to gate breakdown voltage is formed.