Patent ID: 6327192
Filing Date: 2001-12-04
Classification: G11C

Abstract:
A memory device having address, data, and control buses, the memory device comprising:a memory-cell array including a number of memory cells arranged in rows and columns, each memory cell operable to store a bit of data;a row address decoder circuit adapted to receive a row address applied on the address bus and operable to decode the row address and activate a row of memory cells corresponding to the decoded row address;a column address decoder circuit adapted to receive a column address applied on the address bus and operable to decode the column address and access a plurality of memory cells in the activated row, the data stored in the plurality of memory cells in the activated row being defined as a block of data;a precharge circuit coupled to the memory-cell array operable, when activated, to precharge and equilibrate the memory-cell array; anda block read latch circuit operable to latch a first block of data accessed in the memory-cell array corresponding to first decoded row and column addresses, and to sequentially transfer subblocks of the first block of data onto the data bus, the memory device operable such that after the first block of data is latched in the block read latch circuit, the precharge circuit first precharges and equilibrates the memory-cell array, and the row and column decoder circuits then decode second row and column addresses such that the column address decoder circuit accesses a second block of data corresponding to the second row and column addresses, the second block of data being accessed before the block read latch circuit has completed sequentially transferring all the subblocks of the first block of data onto the data bus.