Patent ID: 8067267
Filing Date: 2011-11-29
Classification: H01L

Abstract:
1. A method making a stacked microelectronic assembly comprising: providing a first microelectronic package including a first substrate, the first substrate including a first dielectric layer, conductive posts having tips overlying said first dielectric layer at a vertical height from a surface of said first dielectric layer, and conductive traces extending along said surface of said first dielectric layer, wherein said conductive posts have bases extending in a vertical direction away from said conductive traces, said posts being formed integrally with said traces; providing a second microelectronic package including a second substrate, the second substrate including a second dielectric layer, conductive, fusible masses having apexes overlying said second dielectric layer at a vertical height from a surface of said second dielectric layer, contacts exposed at said surface of said second substrate supporting said fusible masses, and conductive traces extending from said contacts along said surface of said second dielectric layer; securing a microelectronic element to one of the surfaces of at least one of said first or second substrates such that said first and second dielectric layers extend beyond edges of said microelectronic element, said microelectronic element defining a vertical height that extends from the one of the surfaces of said at least one of said first or second substrates to which said microelectronic element is secured; and joining said conductive posts of said first substrate with said fusible masses of said second substrate, and wherein the vertical height of each said conductive post/fusible mass combination is equal to or greater than the vertical height of said microelectronic element, wherein said posts include a plurality of aligned posts which are aligned in a first row extending in a single orthogonal direction along a surface of said first substrate away from a portion of said first substrate that faces a face of said microelectronic element, said aligned posts being disposed beyond one of said edges of said microelectronic element.