Patent ID: 7602029
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A one-time programmable memory comprising: a first and a second metal oxide semiconductor (MOS) transistors disposed immediate adjacent to each other in a common doped-well region of a first conductivity type in a semiconductor substrate and sharing a single polysilicon strip on a top surface of said semiconductor substrate as a common gate thus connecting together in parallel and said semiconductor substrate further comprising doped regions of a second conductivity type near said top surface of said semiconductor substrate disposed on opposite sides of a gate transistors for functioning as common source and drain for said first and second MOS transistors; and said semiconductor substrate further-includes a doped drift region of said first conductivity type extended laterally to a boundary of said first and second MOS transistors and encompassed by said common doped well region and encompassing and surrounding said drain and source of said first MOS transistor wherein said doped drift region having a higher dopant concentration than said common doped well region of said first conductivity type for generating a different threshold voltage for said first MOS threshold than said second MOS transistor.