Patent ID: 6337267
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method for fabricating a semiconductor device comprising:forming a device isolation region on a semiconductor substrate to define an active region, the semiconductor substrate having a cell array region and a peripheral region; forming a first interlayer insulating layer on the substrate; forming a material layer pattern on the first interlayer insulating layer, the material layer pattern having a first opening portion defining a first contact hole for a storage node at the cell array region and a second opening portion defining a second contact hole for a metal interconnection at the peripheral region; forming a second interlayer insulating layer on the material layer pattern; forming a groove mask pattern on the second interlayer insulating layer, the groove mask pattern having an opening portion aligned over at least the second opening portion of the material layer pattern at the peripheral region, the opening portion of the groove mask pattern being larger than the second opening portion of the material layer pattern; using the groove mask pattern and the material layer pattern as etch stops, etching exposed portions of the second interlayer insulating layer and the first interlayer insulating layer to form interconnection openings in the peripheral region, the interconnection openings being self aligned with the second opening portions of the material layer pattern; and filling the interconnection openings in the peripheral region with a conductive material to form a metal interconnection.