Patent ID: 6410391
Filing Date: 2002-06-25
Classification: H01L

Abstract:
A method for fabricating an EEPROM memory cell having a trench capacitor, which comprises:providing a substrate having a weakly doped epitaxial layer and a more heavily doped layer disposed under the weakly doped epitaxial layer; forming a trench in the substrate, the trench having a lower region and an upper region, the lower region at least partially in the weakly doped epitaxial layer; filling the lower region of the trench with a first filling material; forming an insulation collar in the upper region of the trench; removing the first filling material from the lower region of the trench; forming a buried plate as a first capacitor plate in the lower region of the trench in the weakly doped epitaxial layer; filling the trench with a conductive second filling material to form a second capacitor plate; providing a capacitor dielectric between the conductive second filling material and the buried plate; forming a dielectric tunnel layer in the trench at an interface of a buried contact and an associated selection transistor; and forming a conductive protective layer on the dielectric tunnel layer.