Patent ID: 6566194
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:providing a semiconductor substrate having a core region and a peripheral region, wherein oxide islands are not formed in the core region; forming charge trapping layers comprising at least one dielectric layer over the core region; forming a poly layer over at least the charge trapping layers; prior to patterning the poly layer in the core region, doping the poly layer in the core region; patterning the poly layer in the core region to form word lines; masking the core region; while the core region is masked and prior to saliciding the word lines, doping the substrate to form source and drain regions adjacent gates in the peripheral region; and saliciding the word lines, wherein the source and drain regions adjacent the gates in the peripheral region are salicided at the same time as the word lines in the core region.