Patent ID: 6362117
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A method of fabricating an integrated circuit, comprising the steps of:providing a structure having a top surface and including a semiconductor substrate; forming spaced first and second sections on said top surface, said first and second sections respectively having first and second side surfaces which face each other; forming a first sidewall on said firs side surface; forming a second sidewall on said second side surface; forming a third section between said first and second sidewalls, including the steps of introducing a selected material between said first and second sidewalls, and removing any portion of said selected material which is higher than upper ends of said first and second sidewalls; wherein said steps of forming said first, second and third sections include the step of forming each of said first, second and third sections as a transistor gate structure; and including after said step of forming said third section, the steps of removing said first and second sidewalls, leaving a first opening between said first and third sections and a second opening between said second and third sections, doping regions of said structure through the first and second openings, and filling up the first and second openings with an insulating material.