Patent ID: 7948790
Filing Date: 2011-05-24
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a memory cell arranged between a first wiring and a second wiring and including a variable resistor element; and a controller operative to control a voltage applied between the first wiring and the second wiring to control a resistance value of the variable resistor element, the controller being configured to perform a first operation and a second operation, the first operation applying a first voltage between the first wiring and the second wiring to switch the variable resistor element from a first state with a resistance value that is not less than a first resistance value, to a second state with a resistance value that is not more than a second resistance value smaller than the first resistance value, the second operation applying a second voltage smaller than the first voltage between the first wiring and the second wiring to switch the variable resistor element from the second state to the first state, and in the first operation, a verify voltage being applied between the first wiring and the second wiring after application of the first voltage to read data from the memory cell and judge whether the second state is obtained or not, and based on a signal obtained through application of the verify voltage, a third voltage smaller than the first voltage being applied between the first wiring and the second wiring.