Patent ID: 8180964
Filing Date: 2012-05-15
Classification: G06F

Abstract:
1. A non-transitory computer-readable memory device storing instructions comprising: one or more instructions executed by one or more processors to cause the one or more processors to receive a model; one or more instructions executed by the one or more processors to cause the one or more processors to generate application code based on the model; one or more instructions executed by the one or more processors to cause the one or more processors to determine a first cache configuration based on the application code; one or more instructions executed by the one or more processors to cause the one or more processors to execute the application code in a first cache environment that is based on the first determined cache configuration; one or more instructions executed by the one or more processors to cause the one or more processors to output first cache performance results based on execution of the application code in the first cache environment; one or more instructions executed by the one or more processors to cause the one or more processors to determine a second cache configuration based on the first cache performance results; one or more instructions executed by the one or more processors to cause the one or more processors to execute the application code in a second cache environment that is based on the second determined cache configuration; one or more instructions executed by the one or more processors to cause the one or more processors to output second cache performance results based on execution of the application code in the second cache environment; and one or more instructions executed by the one or more processors to cause the one or more processors to select one of the first cache configuration or the second cache configuration as a selected cache configuration, based on comparing a performance of a first cache configuration trial, associated with the first cache environment and a performance a second cache configuration trial, associated with the second cache environment.