Patent ID: 8941958
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a first protection circuit comprising: a second protection circuit comprising: wherein the first protection circuit is electrically connected between the first wiring and the second wiring so that a forward bias is applied to the first nonlinear element and the third nonlinear element included in the first protection circuit when a potential of the first wiring is higher than a potential of the second wiring, wherein the second protection circuit is electrically connected between the first wiring and the third wiring so that a forward bias is applied to the second nonlinear element and the fourth nonlinear element included in the second protection circuit when the potential of the first wiring is lower than a potential of the third wiring, wherein the first nonlinear element and the second nonlinear element include silicon, wherein the third nonlinear element and the fourth nonlinear element are transistors including an oxide semiconductor in their respective channel formation regions, wherein the first nonlinear element and the second nonlinear element are transistors including silicon in their respective channel formation regions, and wherein the transistors are p-channel transistors.