Patent ID: 6771726
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A device for the regeneration of a clock signal from at least two synchronization pulses transmitted on an external serial bus in an integrated circuit including an internal oscillator for providing a reference clock signal, the device comprising:a time unit defining circuit for defining a time unit; a delay measurement circuit for providing a fine measurement, in the time unit, of a delay of the at least two synchronization pulses each with respect to a preceding pulse of the reference clock signal; reference clock signal stroke measurement circuit for measuring a number of reference clock signal strokes between the two synchronization pulses; a countdown circuit for outputting a regenerated clock signal pulse at each regeneration cycle; and a computation unit receiving the measured delay, a measurement of a time period of the reference clock signal and the measured number of clock signal strokes for computing the corresponding period and initializing the countdown circuit to output the regenerated clock signal pulse.