Patent ID: 7170130
Filing Date: 2007-01-30
Classification: H01L

Abstract:
1. A floating gate memory cell situated on a substrate, said floating gate memory cell comprising: a stacked gate structure situated on said substrate, said stacked gate structure being situated over a channel region in said substrate; a recess formed in said substrate adjacent to said stacked gate structure, said recess having a sloped sidewall, a bottom, and a depth; a source of said floating gate memory cell situated adjacent to said sloped sidewall of said recess and under said stacked gate structure; a spacer situated adjacent to said stacked gate structure and adjacent to said sloped sidewall of said recess, said spacer extending to said bottom of said recess; a mask situated over a drain side of said stacked gate structure and over a drain region of said floating gate memory cell, wherein said mask is not situated over said recess; wherein said spacer causes said source to have a reduced lateral straggle and diffusion in said channel region.