Patent ID: 6084312
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A semiconductor device having a double pad structure with a cell-portion having a certain circuit pattern on a semiconductor substrate, and a peri-portion having a plurality of pads formed around the cell-portion for the electrical contact of the certain circuit pattern with the outside circuits, the semiconductor device comprising:an intermediate insulating layer formed on the semiconductor substrate;an uppermost metallic conductive pattern formed on the intermediate insulating layer within the cell-portion;a first pad pattern formed on the intermediate insulating layer within the peri-portion;a passivation layer formed over the semiconductor substrate with a portion of the first pad pattern being exposed through the passivation layer; anda second pad pattern formed on the passivation layer including the exposed portion of the first pad pattern, a size of a pad of the second pad pattern being bigger than that of the first pad pattern, the second pad pattern extending over the passivation layer of the cell-portion.