Patent ID: 8664111
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A method of manufacturing semiconductor devices, comprising: forming a gate insulation layer including a high-k dielectric material on a substrate, the substrate including a first region and a second region; forming an etch stop layer on the gate insulation layer; forming a first metal layer on the etch stop layer; forming a first hard mask including amorphous silicon on the first metal layer in the first region; removing the first metal layer using the first hard mask as an etching mask until the etch stop layer is exposed to form a first metal layer pattern on the etch stop layer in the first region; forming a second metal layer on the first hard mask and the etch stop layer; forming a second hard mask on the second metal layer in the second region; and removing the second metal layer using the second hard mask as an etching mask until the etch stop layer is exposed to form a second metal layer pattern on the etch stop layer in the second region.