Patent ID: 6960504
Filing Date: 2005-11-01
Classification: H01L

Abstract:
1. A method for fabricating a capacitor for use in a semiconductor device, comprising the steps of: forming a stack layer sequentially deposited in an order of an inter-layer insulation layer and a first etch barrier layer on a substrate, wherein a hole exposing a partial portion of the substrate passing through the inter-layer insulation layer and the first etch barrier layer is formed; forming a storage node contact plug contacted to the partial portion of the substrate by being buried into the hole; forming a storage node insulation layer on the stack layer, the storage node insulation layer having a concave pattern of which bottom region has a wider critical dimension (CD) than that of a top region and exposing the storage node contact plug, wherein the step of forming a storage node insulation layer comprises the step of: forming a lower electrode inside of the concave pattern, the lower electrode being connected to the storage node contact plug; and forming sequentially a dielectric layer and an upper electrode on the lower electrode.