Patent ID: 6304568
Filing Date: 2001-10-16
Classification: H04L

Abstract:
An interconnection network for a multiprocessor communication system, said interconnection network comprising a plurality of nodes arranged in a predetermined topographical structure, each of said nodes comprising:a single interface connected to a corresponding single processor for receiving source message data from said processor and transmitting destination message data to said processor;a control router connected to receive control data from said interface;a first data router connected to receive and transmit message data over a first data connection with said interface;a second data router connected to receive and transmit message data over a second data connection with said interface;a control line connected to each of said control routers of each of said nodes for transferring said control data from a control router of a source node to a control router of a destination node, said control line and said control routers forming a control plane arranged in said predetermined topographical structure;a first data line connected to each of said first data routers of each of said nodes for transferring message data from a first data router of said source node to a first data router of said destination node, said first data line and said first data routers forming a first data plane arranged in said predetermined topographical structure; anda second data line connected to each of said second data routers of each of said nodes for transferring message data from a second data router of said source node to a second data router of said destination node, said second data line and said second data routers forming a second data plane arranged in said predetermined topographical structure, wherein said first and second data lines carry only message data and said control line carries only control data.