Patent ID: 7843731
Filing Date: 2010-11-30
Classification: G11C,H01L

Abstract:
1. A memory array comprising: a first selection line and a second selection line running in a first direction, wherein first and second selection transistors are alternatively connected to each of the first and second selection lines, wherein the first selection line includes an upper fist selection and a lower first selection line and the second selection line includes an upper second selection line and a lower second selection line; a plurality of word lines interposed between the upper first selection line and the lower second selection line and running in the first direction; a plurality of memory cells arranged in the first direction are connected to each of the word lines, a predetermined number of the memory cells arranged in a second direction perpendicular to the first direction form memory strings, and the first memory cells of the memory strings are connected to the selection transistors of the upper first selection line and the last memory cells are connected to the selection transistors of the lower second selection line; and a plurality of bit lines running in the second direction, wherein each of the bit lines is connected to the first and second selection transistors between the adjacent memory strings such that the first and last memory cells of each of the memory strings are connected to the adjacent bit lines.