Patent ID: 6221778
Filing Date: 2001-04-24
Classification: H01L

Abstract:
A method for fabricating a semiconductor device comprising the steps of:forming a plurality of spaced-apart gate electrodes with a capping insulator thereon on a semiconductor substrate;growing an oxide layer by a thermal oxidation process on the semiconductor substrate including the gate electrodes;forming a nitride layer on the thermal oxide layer;etching the nitride layer to form a spacer on sidewalls of the gate electrodes;depositing a CVD oxide layer;forming an etching stopper nitride layer on the CVD oxide layer;depositing a second oxide layer to fill spaces between the gate electrodes; andetching the second oxide, the etching stopper nitride, and the thermal oxide layers to form contacts exposing the semiconductor substrate between the gate electrodes, wherein the CVD oxide layer serves as a buffer layer between the semiconductor substrate and the etching stopper layer.