Patent ID: 8429379
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A microprocessor, comprising: an array of re-configurable gate logic circuits; an array of re-configurable register logic circuits; a programmable switch network having operational connections to the elements of both the array of re-configurable gate logic circuits and the array of re-configurable register logic circuits; a memory circuit block comprising a plurality of cache memory circuits and a plurality of non-volatile memory circuits; a binary code decoder circuit block that performs, at run time, decoding, re-ordering, and parsing of sequences of binary encoded Complex instruction Set Computer (CISC) type or Reduced Instruction Set Computer (RISC) type machine code instructions into newly generated sequences of binary code which are then stored in a first cache memory of the memory circuit block; a binary code converter circuit block that converts, at run time, the newly generated sequences of binary code into newly generated configuration bit map codes which are then stored in a second cache memory of the memory circuit block; a constructer circuit block that configures, at rain time, the array of re-configurable gate logic circuits and the array of re-configurable register logic circuits into at least one finite state machine through the use of the newly generated configuration bit map codes; and a memory bus controller circuit block that interfaces with an external memory bus compatible with a multiprocessor computer system, the external memory bus operable to fetch the sequences of binary encoded CISC type or RISC type machine code instructions stored in an externally shared memory and to store the sequences of binary encoded CISC type or RISC type machine code instructions in a third cache memory of the memory circuit block.