Patent ID: 6327273
Filing Date: 2001-12-04
Classification: H04J

Abstract:
A system for transparently transporting an incoming clock signal (CLK2) with a well-known frequency over a network segment of a telecommunication network, wherein a network timing reference signal is transported over the telecommunication network for synchronization purposes, said system comprising a transmitter (TX) and a receiver (RX) capable of communicating with each other over a communication channel (TL), wherein the transmitter (TX) comprises:a first input for receiving data (DATA);a second input for receiving the incoming clock signal (CLK2);a third input for receiving a transmitter clock signal (CLK1);an output;embedding circuitry (EMBED) coupled between said first input and said output, wherein the embedding circuitry (EMBED) is adapted to embed said data (DATA) in data frames (FRAME) and to output said data frames (FRAME) to said output; andphase measurement circuitry (PHASE) coupled between said second input and a fourth input for receiving a reference signal (R) derived from said transmitter clock signal, (CLK1), wherein said phase measurement circuitry (PHASE) is adapted to measure a phase difference value (P) between said incoming clock signal CLK2 and said reference signal (R) and to output said phase difference value (P) to said embedding circuitry (EMBED);wherein said embedding circuitry (EMBED) is further configured so as to embed in one of said data frames (FRAME) a deviation of said phase difference value (P) from a previously measured phase difference value, and the receiver (RX) comprises:a receiver input for receiving the data frames (FRAME);a clock input for receiving a receiver clock signal (CLK1'),a receiver output and a clock output;recovery circuitry (D-EMBED) adapted to retrieve incoming data (DATA') from said data frames (FRAME), to output said retrieved data (DATA') to said receiver output, and to recover a deviation of the phase difference value (P) from a previously recovered phase difference value out of a reserved field within said data frames (FRAME);reference signal circuitry adapted to generate a reference signal (R') from said receiver clock signal (CLK1'); anda clock generator (GEN) having a first input for receiving said phase difference value (P), a second input for receiving said reference signal (R'), and a third input for receiving said receiver clock signal (CLK1'), wherein said clock generator (GEN) is configured so as to generate a clock signal (CLK2') having a phase difference from said reference signal (R') generally equal to said phase difference value (P) number of clock cycles of said receiver clock signal (CLK1').