Patent ID: 9223967
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A microprocessor comprising: at least one instruction cache line storing at least one instruction, the at least one instruction cache line having an associated signature generator which determines a signature of instructions stored within a respective cache line; an instruction processing pipeline which performs a concurrent speculative partial execution of a plurality of instructions received from the at least one instruction cache line, having a pipeline latency comprising at least one pipeline phase between receipt of a respective instruction for processing and commitment of the respective instruction, the instruction processing pipeline being responsive to at least one control flow instruction and a signal which selectively authorizes commitment of the respective instruction; verification logic configured to verify a reference signature against the generated signature and to selectively produce the signal within the pipeline latency without stalling the instruction processing pipeline; authentication logic, associated with the instruction processing pipeline, configured to permit commitment of the at least one instruction, selectively based on the signal from the verification logic; and logic configured upon a failure of the verification logic to verify the reference signature against the generated signature, to restore a known stable state or a predefined checkpoint state without commitment of the instruction by the instruction processing pipeline.