Patent ID: 6121115
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of fabricating an integrated circuit memory device comprising the steps of:defining a memory cell area and a select transistor area of a semiconductor substrate, the memory cell area including a memory cell active area and a memory cell field area, and the select transistor area including a select transistor active area and a select transistor field area;implanting first channel stop impurity ions into the select transistor field area;forming a first field insulation layer in the memory cell field area, and a second field insulation layer in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation layer; andimplanting second channel stop impurity ions through the central portion of the first field insulation layer, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.