Patent ID: 7112857
Filing Date: 2006-09-26
Classification: H01L,Y10S

Abstract:
1. An static random access memory (SRAM) circuit comprising: at least one pull-down NMOS transistor, having a first gate electrode with a first dopant concentration, formed atop a first gate dielectric layer with a first physical gate dielectric thickness; at least one pull-up PMOS transistor, having a second electrode with a second dopant concentration, formed atop a second gate dielectric layer with a second physical gate dielectric thickness, wherein the pull-down NMOS transistor and the pull-up PMOS transistor are connected with each other for retaining data; a pass gate device for enabling the pull-down NMOS transistor and the pull-up PMOS transistor to be electrically charged, the pass gate device having a third gate electrode with a third dopant concentration formed atop a third gate dielectric layer with a third physical gate dielectric thickness, wherein the first physical gate dielectric thickness, the second physical gate dielectric thickness and the third physical gate dielectric thickness are substantially the same, the first dopant concentration is substantially greater than the second dopant concentration and the third dopant concentration by undergoing one or more additional doping processes to cause a difference of at least two angstroms in electrical gate dielectric thickness comparing to that of the pull-up PMOS transistor or the pass gate device.