Patent ID: 6430639
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A processor, comprising:a decode unit coupled to receive and decode a first one or more instructions that specify a lock, wherein said decode unit is configured to generate a lock indication in response to said first one or more instructions; a load/store unit coupled to receive said lock indication and said first one or more instructions from said decode unit, wherein said load/store unit is configured to select said first one or more instructions for execution and to transmit a first request for a locktoggle command in response thereto; and a system interface controller coupled between said load/store unit and a bus, wherein said system interface controller is configured to receive said first request for said locktoggle command from said load/store unit, and wherein said system interface controller is further configured to issue said first locktoggle command in response to receiving-said request for said first locktoggle command; wherein said load/store unit is further configured to transmit a second request for said locktoggle command in response to executing said first one or more instructions; and wherein said system interface controller is further configured to receive said second request for said locktoggle command from said load/store unit and to issue said second locktoggle command in response to receiving said second request for said locktoggle command.