Patent ID: 7847572
Filing Date: 2010-12-07
Classification: G01R,G11C

Abstract:
1. A test system that tests a device under test, comprising: a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal, wherein the test apparatus includes: the test system tests a plurality of the devices under test formed in a wafer under test, the test apparatus further includes a test substrate that is arranged facing the wafer under test and on which is formed a plurality of circuit blocks corresponding to the plurality of devices under test, and each circuit block includes the test circuit and the synchronization control section, and tests a corresponding device under test.