Patent ID: 8643115
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A method of forming a complementary metal oxide semiconductor comprising: providing a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET device region of a semiconductor structure and a plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET device region of the semiconductor substrate, wherein said providing comprises: forming a gate electrode layer atop both the plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion; and forming an nFET gate stack in the nFET device region and a pFET gate stack in the pFET device region, wherein the nFET gate stack includes, from bottom to top, the plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and a first patterned portion of the gate electrode layer and the pFET gate stack includes, from bottom to top, the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion and a second patterned portion of the gate electrode layer.