Patent ID: 6184704
Filing Date: 2001-02-06
Classification: H03K

Abstract:
A digital input circuit consisting of multiple inverter stages where the first stage is an inverter which contains a compensation means for lessening the effect of manufacturing process variations on the switching voltage level at the input of said digital input circuit, said compensation means being such that said digital input circuit is capable of operating at low voltage; said first stage is comprised of a first P-type FET transistor, a first compensating resistive device, a second N-type FET transistor and a second compensating resistive device, the input to said first stage is connected to the gates of said FET transistors, the source of said first FET device is connected to the supply voltage, said first compensating resistive device has one terminal connected to the drain of said first FET transistor and the other terminal of said first compensating resistive device is connected to the output node of said first stage, the source of said second FET device is connected to ground, said second compensating resistive device has one terminal connected to the drain of said second FET transistor and the other terminal of said second compensating resistive device is connected to the output node of said first stage.