Patent ID: 6603203
Filing Date: 2003-08-05
Classification: H01L

Abstract:
A semiconductor device comprising:a capacitive element having a bottom electrode; an interconnection structure over a semiconductor region, said interconnection structure comprising a multilevel interconnection structure which includes a primary level interconnection and at least one intermediate level interconnection which is over said primary level interconnection and under said bottom electrode, said bottom electrode being over said primary level interconnection; and a plug connection structure including: a contact plug under said primary level interconnection and over said semiconductor region, said contact plug connecting said primary level interconnection to said semiconductor region; a first via plug under said bottom electrode and over said primary level interconnection, said first via plug connecting said bottom electrode to said primary level interconnection; and a second via plug connecting said at least one intermediate level interconnection to said primary level interconnection and an additional interconnection partially in contact with at least a part of a top of said at least one intermediate level interconnection, wherein said additional interconnection has a terminal portion rigidly projecting in a downward direction, said terminal portion having a hollow and a bottom surface having a same level as a bottom of said bottom electrode, and said bottom surface being electrically connected to said at least one intermediate level interconnection.