Patent ID: 9165635
Filing Date: 2015-10-20
Classification: G06F,G11C,Y02D

Abstract:
1. A memory controlling device disposed in a computer for controlling a memory with a partial array self refresh (PASR) function in the computer, the computer operating under a normal mode and a sleep-or-standby mode, the memory comprising a plurality of memory segments, the memory controlling device comprising: a PASR configuration register, for storing a PASR configuration, the PASR configuration comprising a plurality of PASR configuration bits, and the PASR configuration bits corresponding to the memory segments respectively; an address mapper, for receiving an input address set, converting the input address set into a mapped address set, and outputting the mapped address set, wherein the mapped address set comprises at least one mapped address in a limited range or comprises a plurality of successive mapped addresses; an address decoder, coupled to the PASR configuration register and the address mapper, for receiving the mapped address set and the PASR configuration under the normal mode, updating the PASR configuration according to the mapped address set, and storing the updated PASR configuration in the PASR configuration register; and an address selector, coupled to the memory, the address mapper and the PASR configuration register, for under the normal mode, receiving the mapped address set to generate an updated address set for the accessing of the memory, for under the sleep-or-standby mode, receiving the updated PASR configuration to generate the updated address set, and for setting at least one mode register of the memory according to the updated address set, and for controlling the memory to self refresh at least one of the memory segments, which correspond to the PASR configuration, according to content of the at least one mode register; wherein the address mapper receives the input address set and an address offset, and converts the input address set into the mapped address set according to the address offset, and the memory comprises m memory banks, each of the memory banks comprises n pieces of the memory segments, m and n are positive integers, and the address mapper further comprises: