Patent ID: 6720813
Filing Date: 2004-04-13
Classification: H03K

Abstract:
A dual edge-triggered flip-flop programmably resetable independent of an input clock signal, comprising:control circuitry arranged to receive the input clock signal and a reset signal; negative edge-triggered circuitry operatively connected to the control circuitry and arranged to receive a data signal and a reset value signal, wherein the negative edge-triggered circuitry generates a first output value dependent on the control circuitry and the data signal; positive edge-triggered circuitry operatively connected to the control circuitry and arranged to receive the data signal and the reset value signal, wherein the positive edge-triggered circuitry generates a second output value dependent on the control circuitry and the data signal; and output circuitry operatively connected to the negative edge-triggered circuitry and the positive edge-triggered circuitry, wherein the output circuitry generates an output signal dependent on one selected from a group consisting of the first output value and the second output value, wherein, upon assertion of the reset signal, the output signal is set to a value of the reset value signal asynchronous of the input clock signal.