Patent ID: 7898896
Filing Date: 2011-03-01
Classification: G11C

Abstract:
1. A semiconductor device comprising a semiconductor memory section that has a write mode, a read mode and a bypass mode, wherein said semiconductor memory section includes: a memory cell array having a plurality of memory cells arranged in a predetermined direction; an input port; an output port; a plurality of read word lines respectively connected to said plurality of memory cells in said memory cell array; a plurality of write word lines respectively connected to said plurality of memory cells in said memory cell array; a decoder circuit which activates any one of said plurality of write word lines in said write mode, and activates any one of said plurality of read word lines in said read mode; an input buffer circuit which receives data inputted into said input port, and outputs the received data; a write bit line which extends from said input buffer circuit to said memory cell array, and transmits data outputted from said input buffer circuit to said memory cell array; an output buffer circuit which outputs received data to said output port; and a read bit line which extends from said memory cell array to said output buffer circuit, and transmits data from said memory cell array to said output buffer circuit, said write bit line is extended from said memory cell array to said output buffer circuit, and said output buffer circuit outputs data transmitted through said read bit line to said output port in said read mode, and outputs data transmitted through said write bit line to said output port in said bypass mode, wherein a data switch circuit which outputs data, having been inputted into said input port, based upon a control signal in said write mode, and outputs data, having been inputted into said input port, regardless of said control signal in said bypass mode; and a bit line driver circuit which receives data outputted from said data switch circuit, and outputs the received data to said write bit line, and said output buffer circuit has: a sense amplifier circuit which amplifies data transmitted through said read bit line, and outputs the amplified data; and an output selection circuit which outputs data from said sense amplifier circuit to said output port in said read mode, and outputs data transmitted through said write bit line to said output port in said bypass mode.