Patent ID: 7012335
Filing Date: 2006-03-14
Classification: H01L

Abstract:
1. A wiring of a semiconductor device comprising: a first conductive layer formed on a semiconductor substrate; a first insulation layer formed on said first conductive layer, wherein the first insulation layer has a scratch on a surface thereof after the surface is planarized by a CMP process; a second insulation layer formed on said first insulation layer to cover the scratch formed on the surface of the first insulation layer; a second conductive layer contacting said first conductive layer through a via hole formed in said first and second insulation layers, a groove formed in said second insulation layer over the via hole in contact with the via hole, and having a width wider than a width of the via hole, the groove having a depth less than the thickness of said second insulation layer; and a third conductive layer formed in the groove formed in said second insulation layer, the third conductive layer having a thickness less than the thickness of said second insulation layer.