Patent ID: 6906406
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. A package for multiple semiconductor dice, the package comprising: a die mount surface; a bond pad surface residing over the die mount surface, a first semiconductor die mounted to the die mount surface in the first generally rectangular die receiving area and a second semiconductor die mounted to the die mount surface in the second generally rectangular die receiving area; a first set of package bond pads on the bond pad surface proximate to the first portion of the cavity; and a second set of package bond pads on the bond pad surface proximate to the second portion of the cavity, wherein each of the second set of package bond pads is implemented in an electrical pathway electrically coupled to a bond pad of the second semiconductor die, wherein each package bond pad of the second set has an impedance sized for controlling the impedance of the electrical pathway in which it is implemented; a third semiconductor die located in the first generally rectangular die receiving area; wherein the third semiconductor die is mounted to the die mount surface.