Patent ID: 8598648
Filing Date: 2013-12-03
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a source line; a bit line; m (m is an integer greater than or equal to 2) signal lines; m word lines; a selection line; first to m-th memory cells connected in series between the source line and the bit line; and a selection transistor whose gate terminal is electrically connected to the selection line, wherein the first to m-th memory cells each comprise: wherein the second transistor includes an oxide semiconductor layer, wherein the source line is electrically connected to the first source terminal in the m-th memory cell through the selection transistor, wherein the bit line is electrically connected to the second drain terminal in the first memory cell and is electrically connected to the first drain terminal in the first memory cell, wherein the k-th (k is a natural number greater than or equal to 1 and less than or equal to m) signal line is electrically connected to the second gate terminal in the k-th memory cell, wherein the k-th word line is electrically connected to one terminal of the capacitor in the k-th memory cell, wherein the second drain terminal in the l-th (l is a natural number greater than or equal to 2 and less than or equal to m) memory cell is electrically connected to the first gate terminal in the (l−1)-th memory cell, the second source terminal in the (l−1)-th memory cell, and the other terminal of the capacitor in the (l−1)-th memory cell, wherein the first gate terminal in the m-th memory cell, the second source terminal, in the m-th memory cell, and the other terminal of the capacitor in the m-th memory cell are electrically connected to one another, and wherein the first drain terminal in the l-th memory cell is electrically connected to the first source terminal in the (l−1)-th memory cell.