Patent ID: 7076405
Filing Date: 2006-07-11
Classification: G06F

Abstract:
1. A method of estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of stages, comprising the steps of: calculating a first set of output signal elementary waveforms and occurrence probabilities thereof at the first stage of the logic gates by the use of signal waveforms and occurrence probabilities thereof at primary input terminals of the integrated circuit; calculating a second set of output signal elementary waveforms and occurrence probabilities thereof at the second stage of the logic gates by the use of said signal waveforms and said occurrence probabilities thereof at said primary input terminals and said first set of output signal elementary waveforms and said occurrence probabilities thereof at the first stage of the logic gates; and in the same manner calculating an n-th set (n is a natural number) of output signal elementary waveforms and occurrence probabilities thereof at the n-th stage of the logic gates by the use of said signal waveforms and said occurrence probabilities thereof at said primary input terminals and an (n-1)th set of output signal elementary waveforms and occurrence probabilities thereof at the (n-1)th stage of the logic gates, estimating power consumption and noise levels based on at least the n sets of output signal elementary waveforms and occurrence probabilities thereof, wherein types of the respective elementary waveforms, occurrence probabilities and signal correlations are calculated relating to signals located on each wiring of each stage inside of the integrated circuit and occurring within a predetermined time period.