Patent ID: 6630717
Filing Date: 2003-10-07
Classification: H03K

Abstract:
An integrated CMOS semiconductor circuit comprising:an internal circuit comprising CMOS transistors including P- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit provided with a power source that supplies power to the external circuit; and a switch portion which in the standby state of the internal circuit applies a reverse bias to the internal circuit between the source region and the substrate of one of the P- and N-channel transistors of the internal circuit via the power source of the external circuit, so that power is switched on the substrate side of the one transistor thereby raising a threshold voltage of the one transistor and reducing power consumption.