Patent ID: 6915480
Filing Date: 2005-07-05
Classification: H04L

Abstract:
1. A processor comprising: first classification circuitry configurable to determine for a given packet the processor whether the packet has one or more errors; the first classification circuitry storing the given packet in both first memory circuitry and second memory circuitry, wherein the given packet is stored in the first memory circuitry with an indication of the error determination made by the first classification circuitry; scheduling circuitry coupled to the first memory circuitry and adapted to receive therefrom the given packet and the indication of the error determination made by the first classification circuitry; second classification circuitry coupled to the scheduling circuitry, the second classification circuitry receiving the given packet from the scheduling circuitry if the error determination indication meets one or more specified criteria; and logic circuitry having inputs coupled to respective outputs of the scheduling circuitry and the second classification circuitry, the logic circuitry controlling the dispatch of the given packet from the second memory circuitry responsive to signals from the scheduling circuitry and the second classification circuitry; wherein if the error determination indication does not meet the one or more specified criteria, the given packet is dropped from the first memory circuitry and the second memory circuitry responsive to one or more signals from the scheduling circuitry.