Patent ID: 7616520
Filing Date: 2009-11-10
Classification: G09G

Abstract:
1. An integrated circuit device, comprising: a display memory that includes a plurality of RAM blocks, each of the plurality of RAM blocks including at least first and second RAM blocks; and a wordline control circuit that controls a plurality of wordlines provided in each of the first and second RAM blocks, the wordline control circuit being disposed between the first and second RAM blocks, the first and second RAM blocks being disposed along a first direction, the plurality of wordlines extending along the first direction, the wordline control circuit selecting the plurality of wordlines of the first and second RAM blocks when a plurality of data lines of a display panel are driven, and when accessed from a host, the wordline control circuit selecting the plurality of wordlines of an accessed RAM block that is one of the first and second RAM blocks, and setting the plurality of wordlines of a non-accessed RAM block that is the other of the first and second RAM blocks to an unselected state.