Patent ID: 8610217
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A field effect transistor comprising: a semiconductor layer having a top surface; an isolation structure in said semiconductor layer at said top surface; a gate structure on said top surface offset from said isolation structure, said gate structure having gate sidewalls; sidewall spacers on said top surface positioned laterally immediately adjacent to said gate sidewalls, said semiconductor layer comprising: first dielectric layers on said top surface aligned above and abutting said center portion of each of said source/drain extension regions, respectively; second dielectric layers above and abutting said first dielectric layers, respectively, each second dielectric layer extending laterally onto said top surface above said first section of a source/drain region to an outer edge of a sidewall spacer adjacent to said gate structure, and further extending laterally onto said top surface above said second section of said source/drain region; and metal silicide layers on said top surface above said second section of each of said source/drain regions, each metal silicide layer being positioned laterally immediately adjacent to a second dielectric layer.