Patent ID: 8586426
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: providing a semiconductor-on-insulator (SOT) substrate including at least, from bottom to top, a handle substrate, a buried insulator layer, and a semiconductor material layer; forming a vertical stack comprising, from bottom to top, at least a buried insulator portion and a semiconductor material portion above said handle substrate by forming at least one trench through at least said semiconductor material layer and said buried insulator layer; laterally recessing said buried insulator portion selective to said semiconductor material portion; forming a dielectric material layer directly on sidewalls of said buried insulator portion, wherein a peripheral region of said semiconductor material portion laterally enclosing a center region of said semiconductor material portion overlies a portion of said dielectric material layer and underlies another portion of said dielectric material layer; and forming at least one shallow trench isolation (STI) structure on said dielectric material layer.