Patent ID: 6985778
Filing Date: 2006-01-10
Classification: G06F

Abstract:
1. An interface device interfacing between a host processor and a NAND flash memory, the interface device comprising: a register file receiving a command from the host processor to control an operation of the NAND flash memory and an operation information to execute the command and storing the command and the operation information; an internal memory receiving and storing host data from the host processor and storing flash data extracted from the NAND flash memory and transmitted to the host processor; a flash interface portion controlling a control signal to operate the NAND flash memory, outputting the command, the operation information, or the host data, and controlling an I/O signal wire through which the Dash data is inputted to the NAND flash memory; and a finite state machine extracting the command and the operation information from the register file and controlling the internal memory and the flash Interface portion to execute the command.