Patent ID: 6670692
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A partially embedded decoupling capacitor to reduce delta-I noise for use with a semiconductor chip including a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer, the capacitor comprising:a surface planar metal pattern formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers, wherein: the surface planar metal pattern serves as an electrode of the decoupling capacitor, at least one of others of the plurality of embedded metal layers serves as another electrode of the decoupling capacitor, and the passivation layer serves as a dielectric layer of the decoupling capacitor, and the surface planar metal pattern further serves as a heat sink for dissipating heat directly from the inside of the semiconductor chip through the one of the plurality of embedded metal layers electrically connected to the surface planar metal pattern.