Patent ID: 6493789
Filing Date: 2002-12-10
Classification: G11C

Abstract:
A method of operation in a semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, wherein the method comprises:receiving a plurality of control signals which specify that the memory device perform a memory write operation and a precharge operation, wherein the precharge operation is performed automatically following the memory write operation; receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit, wherein the first mask bit indicates whether to write the first data value to the array; receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit, wherein the second mask bit indicates whether to write the second data value to the array; when the first mask bit indicates that the first data value is to be written to the array, writing the first data value to the array during the memory write operation; when the second mask bit indicates that the second data is to be written to the array, writing the second data value to the array during the memory write operation; and during the precharge operation, precharging a plurality of sense amplifiers that are used in writing the first and second data values to the array.