Patent ID: 8253257
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A layered chip package comprising a main body and wiring, wherein: the main body includes a main part and a plurality of terminals, the main part having a top surface and a bottom surface and including a plurality of layer portions that are stacked, the plurality of terminals being disposed on at least one of the top and bottom surfaces of the main part; the wiring includes a plurality of lines that are electrically connected to the plurality of terminals and pass through all the plurality of layer portions; the plurality of lines include a plurality of common lines that have a use common to all the layer portions in the main part, and a plurality of layer-dependent lines that are used by respective different layer portions; each of the plurality of layer portions includes: a semiconductor chip; a plurality of common electrodes electrically connected to the plurality of common lines; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines; the plurality of common electrodes are arranged in the same layout in all the layer portions in the main part; the selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to; and in at least one of the plurality of layer portions, the plurality of common electrodes and the selective connection electrode are electrically connected to the semiconductor chip, and the semiconductor chip is thereby electrically connected to the plurality of common lines and the layer-dependent line.