Patent ID: 6105114
Filing Date: 2000-08-15
Classification: G06F,Y02D

Abstract:
A two-dimensional array transposition circuit comprising:a memory cell array in which each element of a two-dimensional array formed of N rows and N columns can be written into a memory cell selected by a row and a column respectively specified by a row address signal and a column address signal synchronously with a clock signal and can be read synchronously with said clock signal from said memory cell, wherein data is read at one of a rising and a falling edge of a clock pulse and data is written at the other edge of the clock pulse;a row decoder for said memory cell array;a column decoder for said memory cell array; andan address translation circuit for successively generating said row address signal and said column address signal and supplying them respectively to said row decoder and said column decoder for each said two-dimensional array, whereinsaid N is 2.sup.i (i is a natural number), andsaid address translation circuit includesan N.sup.2 counter responsive to a system clock signal in synchronization with said clock signal to update an output and responsive to a reset signal to reset an output,a toggle counter receiving a prescribed bit of an output from said N.sup.2 counter and changing its state, anda two-input two-output selector receiving higher i bits and lower i bits from said N.sup.2 counter, distributing them depending on an output from said toggle counter, and supplying them to said row decoder and said column decoder.