Patent ID: 9077593
Filing Date: 2015-07-07
Classification: H03L,H04L

Abstract:
1. A receiver circuit comprising: a sampling circuit which samples an inputted data signal by a clock signal and outputs a voltage value or a current value interpolated from a voltage value or a current value which have been sampled in correspondence with an inputted interpolation code indicating an interpolation ratio; a comparator which performs comparison between the voltage value or the current value output from the sampling circuit and a threshold value; a phase detection circuit which detects a transition point of the data signal based on the output of the comparator and decides whether to advance or delay a phase; an interpolation code generation circuit which generates an interpolation code corresponding to an output of the phase detection circuit; and an adder which adds a phase offset code indicating a phase offset amount related to sampling of the data signal to the interpolation code generated by the interpolation code generation circuit, and outputs the interpolation code to which the phase offset code is added to the sampling circuit, wherein an offset corresponding to the phase offset amount is imparted to the threshold value of the comparator.