Patent ID: 6606361
Filing Date: 2003-08-12
Classification: H03K,H04L

Abstract:
A circuit for producing a single output data stream and a corresponding single clock signal, comprising:an input for receiving a single input data stream, the input data stream having data words at a first frequency; a plurality of clock inputs for receiving a plurality of corresponding clock signals, wherein each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words; an input for receiving a fast clock signal, the fast clock signal having a fast frequency greater than the first frequency; circuitry for sampling the input data stream at the fast frequency; circuitry for outputting the sampled data as the single output data stream; circuitry for outputting the single clock signal in response to the fast clock signal; wherein the fast clock signal consists of successive periods, wherein each-of the successive periods consists of a high state and a low state; and wherein the circuitry for outputting the single clock signal comprises circuitry for outputting a modified clock signal representing selected ones of the successive periods of the fast clock signal such that the modified clock signal transitions only once for each data word in the single output data stream.