Patent ID: 6060366
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A method for manufacturing a DRAM capacitor comprising the steps of:providing a substrate having a field effect transistor formed thereon, wherein the field effect transistor includes source/drain regions;forming an inter-layer dielectric over the substrate;forming a first dielectric layer over the inter-layer dielectric;patterning the first dielectric layer and the inter-layer dielectric to form a contact opening exposing one of the source/drain regions;forming a first conductive layer over the first dielectric layer and completely filling the contact opening so that the first conductive layer is electrically coupled to the exposed source/drain region;forming a photoresist layer over the first conductive layer;pattern the first conductive layer using the photoresist as a mask to expose the first dielectric layer;removing a portion of the photoresist layer to expose a strip on the periphery of the upper surface of the first conductive layer;forming a silicon oxide layer over the first dielectric layer and the conductive layer using a liquid-phase deposition method;removing the photoresist layer;removing a portion of the first conductive layer using the silicon dioxide layer as a mask to form a storage electrode of the capacitor, wherein the thickness of the storage electrode is substantially equal to the width of the strip;removing the silicon oxide layer and the first dielectric layer;forming a dielectric film over the exposed surface of the first conductive layer; andforming a second conductive layer over the dielectric film for serving as a cell electrode.