Patent ID: 6021171
Filing Date: 2000-02-01
Classification: G01D

Abstract:
A multiplexing decoder/counter circuit for monitoring quadrature position encoders comprising:a plurality of external differential receivers,a counter means,switching means connected to said differential receivers, said switching means includes a selection capability equal to a maximum number of axes monitored by said circuit,an edge detector that processes information from said external differential receivers to determine a position of each of a plurality of axes being monitored by said circuit,an axis scanning state machine,a position counter memory block,a position readback memory block,a position capture memory block,and a position compare management memory block; whereinat least one of said position counter memory block, said position readback memory block, said position capture memory block, and said position compare management memory block is an addressable memory block, a depth of said addressable memory block is equal to the maximum number of axes monitored by said circuit; and whereininformation from each of said external differential receivers is sequentially directed in said circuit by said switching means, and said axis scanning state machine at each position of said switching means simultaneously addresses at least said position counter memory block, said position readback memory block, said position capture memory block, and said position compare management memory block, a total loop frequency of a scanning sequence of said axis scanning state machine is equal to or greater than a maximum encoder frequency, such that said axis scanning state machine completes a total loop in less time than is required for encoder counts from the quadrature position encoders,at each visitation of a given memory address within said memory blocks, a state of said circuit is established, and any change in quadrature signals is recorded whereby any up or down count is accumulated to said position counter memory block,data describing said state of said circuit is then written back into said memory blocks, and said circuit advances to a succeeding memory location in said scanning sequence, thereby completing a load-count-store-advance cycle of said circuit; such thatsaid switching means enables said counter means to be rapidly shared among the plurality of axes being monitored by said circuit.