Patent ID: 7199453
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A semiconductor package comprising: a substrate at least having an upper surface, a lower surface opposed to the upper surface, and an opening formed through the upper and lower surfaces, wherein at least one first circuit layer and at least one second circuit layer are respectively formed on the upper surface and the lower surface and are electrically connected to each other; a lead frame mounted on the upper surface of the substrate and having a plurality of leads electrically connected to the first circuit layer via at least one conductive element; at least one chip having an active surface and a non-active surface, wherein the active surface of the chip is mounted on the lead frame and is electrically connected to the leads via a plurality of bonding wires formed in the opening; and an encapsulant for filling the opening and encapsulating the chip, the lead frame and the upper surface of the substrate.