Patent ID: 6392927
Filing Date: 2002-05-21
Classification: G11C,H01L

Abstract:
A cell array comprising nonvolatile memory cells having;a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said one cell in the X direction, the control gates of the cells arranged along the X direction are commonly connected along the X direction, the impurity diffusion layers of the cells arranged along the Y direction are commonly connected along the Y direction, and the split gates commonly connected along the Y direction are also commonly connected along the X direction through at least one conductive layer.