Patent ID: 6765563
Filing Date: 2004-07-20
Classification: B60R,B62H

Abstract:
A monolithic integrated circuit for use in a digital display unit, wherein said monolithic integrated circuit receives an analog display signal encoded with a plurality of images, said analog display signal comprising display data signal and associated synchronization signals, said monolithic integrated circuit generating a plurality of pixel data elements for display on a digital display screen contained in said digital display unit, said monolithic integrated circuit comprising:a clock generator circuit for generating a sampling clock synchronized with said synchronization signals; an analog to digital converter (ADC) for receiving said display data signal and sampling said display data signal according to said sampling clock to generate a plurality of sampled data elements representing an image encoded in said display data signal; and an scaler for scaling said image by processing said plurality of sampled data elements to generate a plurality of pixel data elements, wherein said plurality of pixel data elements are used to display said scaled image on said digital display screen, wherein said clock generator circuit comprises a digital phase locked loop for tracking and phase acquisition, and wherein the implementation as the digital phase locked loop enables said clock generator circuit to accurately recover said sampling clock.