Patent ID: 6480035
Filing Date: 2002-11-12
Classification: G01R,H03L

Abstract:
A phase detection circuit, comprising:a first transistor to source a first current to a first node; a second transistor, coupled to the first transistor, to source a second current to a second node, wherein the second current is mirrored from the first current; a third transistor to source a third current to the second node; a fourth transistor, coupled to the third transistor, to source a fourth current to the first node, wherein the fourth current is mirrored from the third current; a first capacitance, coupled to the first node; a fifth transistor coupled between a current sink path and a third node, wherein the fifth transistor receives a first input signal, and wherein: the current sink path is coupled to the third node in response to a first state of the first input signal; and the current sink path is isolated from the third node in response to a second state of the first input signal; a sixth transistor to couple the first capacitance to the third node in response to a second input signal, wherein: the first capacitance is charged in a first direction when the first capacitance is coupled to the current sink path; and the first capacitance is charged in a second direction when the first capacitance is isolated from the current sink path; and an output terminal coupled to the first capacitance, to indicate a quadrature phase error between the first and second input signals, wherein a voltage present at the first output terminal after a detection cycle indicates a quadrature phase difference between the first and second input signals, wherein the detection cycle includes charging the first capacitance in the first and second directions.