Patent ID: 6271686
Filing Date: 2001-08-07
Classification: H01L,H03K

Abstract:
A method of providing a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) dynamic logic circuit for implementing a logic function, said dynamic logic circuit having an output device and a shared node providing input to said output device, the method comprising:providing a plurality of stacks connected in parallel with one another and between said shared node and a common discharge potential to perform a predetermined logic function, each stack comprising a respective plurality of stacked SOI MOS devices and at least one intermediate node;providing a respective active discharging device interconnected between each said intermediate node and said common discharge potential, each said active discharging device being controlled by a corresponding input to a respective one of said stacked SOI MOS devices to discharge the corresponding intermediate node to said common discharge potential;wherein said plurality of stacks are arranged so as to eliminate any parasitic bipolar transistor current leakage path.