Patent ID: 6707403
Filing Date: 2004-03-16
Classification: H03M

Abstract:
An analog to digital converter (ADC) comprising:a first capacitor circuit from which a digital output word is derived corresponding to a sampled analog voltage from an input signal, the first capacitor circuit comprising at least two capacitor arrays of progressively increasing significance, each capacitor array being capacitively coupled to the next more significant capacitor array, a second capacitor circuit, a comparator having a first input coupled to the most significant capacitor array, and a second input coupled to the second capacitor circuit, and a first calibration circuit comprising an array of first calibrating capacitors, coupled to one of the capacitor arrays of the first capacitor circuit which is less significant than the most significant capacitor array, the first calibrating capacitors being selectively coupleable to the second input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array.