Patent ID: 6423958
Filing Date: 2002-07-23
Classification: H01L,H04N

Abstract:
A solid state imaging device comprising:a solid state imaging element including unit pixels each having a photo diode and a light signal detecting insulated gate field effect transistor arranged adjacently to the photo diode, the insulated gate field effect transistor having a high concentration buried layer provided in a well region under a gate electrode in vicinity of a source region to store light generating charges by irradiating a light to the photo diode, the solid state imaging element storing the light generating charges in the high concentration buried layer to modulate a threshold voltage and detect a light signal; a vertical scanning signal driving scanning circuit for outputting a scanning signal to a gate electrode of the light signal detecting insulated gate field effect transistor; and a signal output circuit for inputting to a first input terminal a first source potential obtained in a state the light generating charges are stored in the high concentration buried layer, and inputting to a second input terminal a second source potential obtained in a state the light generating charges are swept out from the high concentration buried layer, and then outputting a voltage in correspondence with the input first and second source potentials; wherein the signal output circuit comprises a first switched capacitor circuit which has a first memory (Lms) and a first operational amplifier circuit, a second switched capacitor circuit which has a second memory (Lmn) and a second operational amplifier circuit, and a third operational amplifier circuit, and the first source potential is stored in the first memory (Lms) and then transmitted via the first operational amplifier circuit to the third operational amplifier circuit, and the second source potential is stored in the second memory (Lmn) and then transmitted via the second operational amplifier circuit to the third operational amplifier circuit, and then the difference voltage between the first and second source potentials is output from the third operational amplifier circuit.