Patent ID: 6708320
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A method for optimizing element placement in layout design of a semiconductor device, the method comprising:generating a thermal equilibrium condition by performing a Monte-Carlo simulation at each virtual temperature while varying the virtual temperature that is a parameter for controlling a range in which a solution of element placement on a placement expression space is searched, thereby uniquely calculating a cost function value for evaluating the element placement with respect to an individual placement of elements; and searching an optimal placement solution to minimize the cost function value, wherein: the thermal equilibrium condition is generated by performing the Monte-Carlo simulation in which a placement Sjâ€² is accepted as the (j+1)th placement at a probability of w expressed by the following relationship: w=1/(exp(&Dgr;E/(kÃ—T))+1) wherein a cost function value for the jth placement Sj generated at one virtual temperature T is calculated as Ej, and a cost function value calculated for a placement Sjâ€² obtained by locally changing the placement Sj is varied by only &Dgr;E into Ej+&Dgr;E, and k denotes a normalization constant at a virtual temperature T; andin generating the thermal equilibrium condition, judgement of convergence is carried out by a distributed value of the cost function value for the placement generated at one virtual temperature T, and judgement whether the thermal equilibrium is achieved is carried out based on the results of the convergence judgment.