Patent ID: 7502976
Filing Date: 2009-03-10
Classification: G11C

Abstract:
1. An apparatus for testing an embedded memory in an integrated circuit, comprising: input logic comprising one or more memory-input paths coupled to respective memory inputs of the embedded memory, the embedded memory being memory that is not part of a scan chain; a memory built-in self-test (MBIST) controller; and a plurality of scan cells coupled between the input logic and the MBIST controller, and being selectively operable in a memory-test mode and a system mode, wherein at least a plurality of the scan cells input memory-test data from the MBIST controller and output the memory-test data into the input logic while operating in the memory-test mode, the input logic combining outputs from at least two of the scan cells to provide at least one logically combined output that is coupled to at least one of the respective memory inputs of the embedded memory.