Patent ID: 6237117
Filing Date: 2001-05-22
Classification: G01R

Abstract:
A method for testing sequential circuit designs in which an exhaustive sequence of test vectors is applied to input nodes of a simulated sequential circuit, the method comprising the steps of:applying a predetermined first value from a set of logic values to a first input node of the simulated sequential circuit; andapplying a predetermined sequence of values from the set of logic values to a second input node of the simulated sequential circuit,wherein the set of logic values includes a logic ""1"" (high) value, a logic ""0"" (low) value, and a floating state value, andwherein the predetermined sequence of values produces transitions between the logic ""1"" value and the logic ""0"" value, between the logic ""1"" value and the floating state value, and between the logic ""0"" value and the floating state value.