Patent ID: 8369476
Filing Date: 2013-02-05
Classification: G06F,H03K,H03L

Abstract:
1. A sigma-delta modulator, comprising: at least a frequency dividing circuit, receiving an input clock signal, and dividing a frequency of the input clock signal, so as to generate at least a frequency dividing clock signal; at least an accumulator, coupled to the frequency dividing circuit, receiving the frequency dividing clock signal, and accumulating a fractional part input signal in response to the frequency dividing clock signal, so as to generate a quantized output signal and an output overflow signal; at least a pulse width adjusting circuit, coupled to the accumulator, receiving the output overflow signal and the frequency dividing clock signal, and adjusting a pulse width of the output overflow signal in response to a period of the frequency dividing clock signal, so as to generate a width adjusted output overflow signal; and at least a data calculating device, coupled to the pulse width adjusting circuit, taking the width adjusted output overflow signal and an integral part input signal into an algorithmic calculation, so as to generate a control signal.