Patent ID: 6352903
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A method of forming an integrated circuit in a semiconductor substrate comprising the steps of:preparing said substrate, including forming a pad etch stop layer; forming a set of STI members defining a set of transistor areas covered by said pad etch stop, said transistor areas having reduced source and drain areas; defining a set of contact etch apertures in a resist area, said contact etch apertures covering said transistor areas and extending over a contact portion of said STI members on opposite sides of said transistor areas; etching said contact portion of said STI members to a contact pad depth in a contact pad aperture, thereby exposing vertical contact surfaces in said substrate on said opposite sides of said transistor region; depositing a layer of conductive material, thereby forming contact pads in said contact pad apertures, said contact pads being in electrical contact with said vertical contact surfaces; forming transistors in said transistor areas, said transistors having sources and drains contacting said contact pads through said vertical contact surfaces; and forming a set of interconnection members to complete said integrated circuit, at least some of said interconnection members contacting said contact pads.