Patent ID: 6271707
Filing Date: 2001-08-07
Classification: H03K

Abstract:
A level shifter comprising:an input terminal for receiving an input signal having low and high voltage states;an output terminal for providing an output signal having low and high voltage states, wherein a voltage of the high voltage state of the output signal is different than a voltage of the high voltage state of the input signal;an input stage coupled to the input terminal and generating a first internal control signal that represents an inversion of the input signal;a low state voltage translation circuit coupled to the input stage for receiving the first internal control signal and generating a bias signal when the input signal is in its low voltage state;a high state voltage translation circuit coupled to the input stage and a high power supply voltage to generate a high state control signal at a high state output node, wherein the high power supply voltage is approximately equivalent to the voltage of the high voltage state of the output signal, wherein the high state voltage translation circuit comprises a plurality of high state PMOS transistors coupled to the high power supply voltage and arranged as a voltage reducing circuit; andan output stage coupled to the low state voltage translation circuit, the high state voltage translation circuit, and the output terminal and providing the output signal comprising:a PMOS pull-up transistor connected to the high power supply voltage and coupled to the high state output node to receive the high state control signal to couple the high power supply voltage to the output terminal to pull the output signal to its high voltage state, wherein a current flowing through the PMOS pull-up transistor approximately mirrors a current flowing through the voltage reducing circuit of the high state voltage translation circuit; anda first bipolar device adapted to pull the output signal to its low voltage state.