Patent ID: 6628167
Filing Date: 2003-09-30
Classification: H03F,H03K,H03M

Abstract:
A linearized folding amplifier circuit comprising:a comparator circuit having a first state and a second state; and a switched output transconductance circuit coupled to the comparator circuit, said switched output transconductance circuit having an input transconductor portion, said input transconductor portion having a differential pair of transistors with a first resistor connected between the emitters of the pair of transistors, said differential pair being driven by a differential input signal applied at the bases of the differential pair, a first pair of output transistors having a first transistor and a second transistor, a second pair of output transistors having a third transistor and a fourth transistor, a linear transconductor portion having a third pair of output transistors having a fifth transistor and a sixth transistor and a fourth pair of output transistors having a seventh transistor and an eighth transistor, said third pair coupled to said first pair and said fourth pair coupled to said second pair, said linear transconductor portion having a fifth pair of transistors having a ninth transistor and a tenth transistor each having an emitter coupled to a second resistor, in a first state said switched output transconductance circuit generating a first differential error signal between emitters of said first and fourth transistors corresponding to the difference in the base-emitter voltages of the input pair of transistors, said first differential error signal coupled from said first and fourth transistors to said linear transconductor portion through said fifth and eighth transistors, said linear transconductor portion generating a first pair of linearized outputs in response to said first differential error signal, in a second state said switched output transconductance circuit generating a second differential error signal between emitters of said second and third transistors corresponding to the difference in the base-emitter voltages of the input pair of transistors, said second differential error signal coupled from said second and third transistors to said linear transconductor portion through said sixth and seventh transistors, said linear transconductor portion generating a second pair of linearized outputs in response to said second differential error signal.