Patent ID: 8352773
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A time aligning circuit for aligning a data transmission timing of a plurality of lanes, comprising: a plurality of buffers, respectively coupled to the plurality of lanes, wherein each buffer is used for receiving ordered sets transmitted on the corresponding lane; a plurality of delay selectors, respectively coupled to the plurality of buffers, wherein each delay selector is used for delaying an output of the ordered sets of the corresponding buffer according to a delay control signal; a plurality of adjustment symbol generators, respectively coupled to the plurality of delay selectors, wherein each adjustment symbol generator is used for outputting an adjustment symbol or for outputting the output received from the corresponding delay selector according to an adjustment control signal; and a control unit, coupled to the plurality of delay selectors and the plurality of adjustment symbols generators, for generating the delay control signal and the adjustment control signal, the control unit comprising: