Patent ID: 6185639
Filing Date: 2001-02-06
Classification: G06F

Abstract:
In a computer system having a host processor and a first plurality of peripheral devices coupled to said host processor by a second plurality of peripheral device controllers, one of said peripheral device controllers identified as a master controller, a method for reducing, over a predetermined amount of time, the number of system interrupts to said host processor comprising:for each said peripheral device controller;receiving a request for interrupt;determining if said device controller is enabled to delay processing of said requested interrupt and:(i) if said device controller is enabled to delay processing of said requested interrupt then processing said interrupt with delay, said processing with delay including a step of posting data and status transfer completion; and(ii) if said device controller is not enabled to process said requested interrupt with delay, then processing said interrupt without delay; and,determining if said device controller is enabled to post completion of the interrupt request, and:(iii) if said device controller is enabled to post completion of the interrupt request, then posting data and status transfer completion to said host processor; and(iv) if said device controller is not enabled to post completion of the interrupt request, then posting completion of the interrupt request in conventional manner.