Patent ID: 8259494
Filing Date: 2012-09-04
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells and a selection gate transistor, at least two of the plurality of memory cells being connected in series, the plurality of memory cells each being capable of storing data of at least one bit which can be electrically programmed and erased; a plurality of word lines each formed by continuously extending control gates of the memory cells; a plurality of selection gate lines formed by continuously extending gates of the selection gate transistors; a first word line unit comprising a first plurality of word lines connected to a first plurality of memory cells included in a first memory cell unit, the first plurality of word lines each being selected according to a corresponding row address; a first word line arranged on one end portion of the first word line unit, the first word line being included in the first plurality of word lines; and a first selection gate line connected to the selection gate transistor included in the first memory cell unit, the first word line being closest to the first selection gate line in the first plurality of word lines; wherein a distance between the first selection gate line and the first word line is greater than a distance between two word lines being located adjacent to each other and being included in the first plurality of word lines.