Patent ID: 6263406
Filing Date: 2001-07-17
Classification: G06F

Abstract:
An apparatus for controlling parallel processors comprising:a storage;a plurality of processors respectively having caches and commonly sharing the storage; anda plurality of storage controllers each connected between said storage and a respective one of the plurality of processors, whereinone of the plurality of processors has a start circuit for sending a start signal to one storage controller of said plurality of storage controllers that is connected to the one processor when the one processor has executed a start instruction to the rest of the processors;the one storage controller connected to the one processor has a first assurance circuit for detecting completion of sending of cache data cancel signals corresponding to a storage instruction that was issued by the one processor before the start instruction and for notifying the storage controllers connected to the rest of the processors of the detection; andthe other storage controllers connected respectively to the rest of the processors have second assurance circuits for sending start instructions to their respective processors when the second assurance circuits detect completion of the issuing of cache cancel requests to the rest of the processors in response to the notification from the one storage controller connected to the one processor.