Patent ID: 7675105
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A non-volatile memory device for 2-bit operation comprising: an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed at an interface between the charge storage layer and the gate; a tunnel dielectric layer formed at an interface between the charge storage layer and the active region; first and second source/drain regions formed at an exposed portion out of both sides of the gate in the active region; and first and second bit lines connected to the first and second source/drain regions respectively, and formed to extend in a bit line direction crossing the word line direction, wherein the active region is formed in a first zigzag pattern to extend in the word line direction in the semiconductor substrate and partially be bent repeatedly, and the gate is formed in a second zigzag pattern to extend in the word line direction on the semiconductor substrate, partially cross with the active region repeatedly, and repeatedly to be bent in symmetry with the first zigzag pattern.