Patent ID: 7521755
Filing Date: 2009-04-21
Classification: H01L

Abstract:
1. A trench semiconductor device of improved voltage withstanding capability, comprising: (a) a semiconductor substrate having a central portion and an annular peripheral portion between a pair of opposite major surfaces; (b) there being at least one cell trench formed in the central portion of the semiconductor substrate so as to extend to a predetermined depth from one of the major surfaces thereof toward the other; (c) a cell trench insulator; (d) a cell trench conductor received in the cell trench via the cell trench insulator; (e) there being a plurality of substantially annular guard trenches formed in the peripheral portion of the semiconductor substrate so as to extend to a predetermined depth from said one major surface of the semiconductor substrate toward said other, the guard trenches surrounding the cell trench; (f) a plurality of guard trench insulators; (g) a plurality of guard trench conductors received one in each guard trench via one guard trench insulator; (h) a first semiconductor region of a first conductivity type formed in the semiconductor substrate so as to surround part of the cell trench and part of each guard trench; (i) a second semiconductor region of a second conductivity type, opposite to said first conductivity type, formed in the central portion of the semiconductor substrate so as to extend from said one major surface thereof toward said other to a depth less than the depth of the cell trench, the second semiconductor region being contiguous to the first semiconductor region and surrounding part of the cell trench; (j) a plurality of guard rings of said second conductivity type formed in the peripheral portion of the semiconductor substrate in alternation with the guard trenches, the guard rings extending from said one major surface of the substrate toward said other to a depth less than the guard trenches and being contiguous to the first semiconductor region; (k) a first electrode on the semiconductor substrate electrically coupled to the second semiconductor region; (l) a second electrode on the semiconductor substrate electrically coupled to the first semiconductor region; and (m) a plurality of capacitive coupling conductors formed on the peripheral portion of the semiconductor substrate each for capacitively coupling one guard trench conductor to the next, wherein each capacitive coupling conductor is disposed opposite every two neighboring guard trench conductors via a dielectric.