Patent ID: 6753570
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A non-volatile memory device comprising:a semiconductor substrate, wherein the substrate has a pair of trenches therein; a tunnel oxide on a top substrate surface of the substrate; a pair of insulators, wherein the insulators have respective lower trench-fill portions in respective of the trenches, wherein the insulators have respective upper protruding portions protruding from the top substrate surface, and wherein the upper protruding portions have respective top insulator surfaces; a floating gate over the tunnel oxide and between the upper protruding portions, wherein the floating gate is in contact with both of the upper protruding portions; an interpoly dielectric over the floating gate, wherein the interpoly dielectric is in contact with the floating gate; and a control gate over the interpoly dielectric, wherein the control gate is in contact with the interpoly dielectric; wherein the interpoly dielectric includes upper and lower layers, with a middle layer therebetween; and wherein the middle layer includes a high-K dielectric, wherein the floating gate overlaps corner parts of the lower trench-fill portions of the insulators.