Patent ID: 8198190
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A method, comprising: defining a lateral position of an interlayer connection between a first metal layer and a second metal layer of a semiconductor device by a first mask; forming a second mask configured to define a trench in a dielectric material formed between said first and second metal layers, said trench corresponding to a metal line of said second metal layer; and forming an opening for said interlayer connection and said trench in said dielectric material in a common etch process, wherein a first dimension of the interlayer connection is substantially equal to a width of an opening in the second mask, and wherein a second dimension of the interlayer connection, substantially perpendicular to the first dimension, is determined by an overlap of an opening in the first mask and the opening in the second mask so the second dimension is less than a length of the opening in the second mask, wherein the first and second dimensions are substantially perpendicular to a third dimension corresponding to a depth of the interlayer connection through the dielectric material.