Patent ID: 8143666
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A device with amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure, the device comprising: a substrate; a dielectric layer on the substrate, the dielectric layer being associated with a first surface; one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions being associated with a second surface and including an n-type a-Si layer, a diffusion barrier layer, and a conductive layer, the n-type a-Si layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the conductive layer, the second surface consisting of n-type a-Si and being substantially co-planar with the first surface; an intrinsic (i-type) a-Si layer overlying the first surface and the second surface; a p-type a-Si layer overlying the i-type a-Si layer; an oxide-nitride-oxide (ONO) layer overlying the p-type a-Si layer; and at least one control gate overlying the ONO layer.