Patent ID: 7039768
Filing Date: 2006-05-02
Classification: G06F

Abstract:
1. An N-way set associative cache within a processor of a data processing system designed for multi-threaded operation, said cache comprising: a first effective address (EA) directory and a second EA directory, each corresponding to a respective one of a first array and a second array, said first EA directory and said second EA directory including (1) a portion of each of a plurality of effective addresses (EAs) representing EAs of a plurality of cache lines and (2) a plurality of thread valid bits associated with the EAs and each bit assigned to idebtify to which thread of a plurality of threads executing within said multi-threaded processor the EAs belong; means for forwarding an EA within a cache line read request associated with a particular thread of said plurality of threads to said first EA directory and second EA directory and to said first array and said second array; cache hit prediction logic for predicting a cache hit utilizing said EA and said portion of EAs within said first and said second EA directories; and way select logic for completing early selection of data from one array among said first array and said second array based on which EA directory contains a thread valid bit associated with said particular thread that is set.