Patent ID: 6445655
Filing Date: 2002-09-03
Classification: G11B

Abstract:
An interface circuit comprising:a first interface section; and a second interface section, the interface circuit being configured so as to enable mutual digital signal transmitting and receiving between the first interface section and the second interface section, making use of an optical, acoustic, or electromagnetic linking means, wherein for the purpose of removing a jitter component and a waveform distortion component from a digital signal, these interface sections comprise: a control driver which is supplied with a driver control signal, and by which the digital signal can be placed either in the on or the off operating state for an extremely short period of time in comparison with the duration time of one bit of the digital signal, this being done at a timing that does not include a jitter component; a receiving section which, during a period of time in which an electrical current flows in a transmission section of the first and second interface sections, performs code detection for only an extremely short period of time, with an operational timing that is the same as the control driver; an output circuit that outputs a received digital signal, this output circuit being supplied with the output signals of these receiving sections as data, and with a read clock signal having the same timing as the driver control signal; and a timing signal generator to which is supplied a base signal that serves as a synchronization reference signal for the first and second interface sections, and which generates the driver control signal that does not contain a jitter component and the read clock.