Patent ID: 7401317
Filing Date: 2008-07-15
Classification: G01R

Abstract:
1. A system for identifying physical manufacturing defects associated with an electrical circuit on a semiconductor die, comprising: one or more processors for executing programs; a storage device for storing a result of an electrical test (ET) and a layout design of the electrical circuit; and a defect identification engine executable by the one or more processors; the defect identification engine further comprising: a first set of instructions for retrieving from the storage device the result of electrical test of the electrical circuit; a second set of instructions for retrieving the layout design of the electrical circuit; and a third set of instructions for establishing logical and physical signal paths between a start resource and an end resource of the electrical circuit using the layout design, the third set of instructions further comprising: instructions for identifying an end contact on the end resource; instructions for identifying a start contact on the start resource in accordance with a hierarchical structure associated with the layout design; and instructions for identifying a plurality of electrically-connected target contacts in accordance with the layout design, the target contacts establishing a physical signal path between the start resource and the end resource.