Patent ID: 6778439
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a plurality of memory cells arranged in a plurality of rows and a plurality columns, each including a semiconductor substrate, a first insulator layer, a charge trapping layer, a second insulator layer, and a gate electrode successively stacked on a surface of the semiconductor substrate, and source and drain respectively formed on the surface of said semiconductor substrate at one side and other side of said gate electrode; a plurality of word lines respectively provided corresponding to said plurality of rows, each connected to the gate electrode of each corresponding memory cell; a plurality of bit lines respectively provided corresponding to said plurality of columns, each connected to the drain of each corresponding memory cell; a source line commonly connected to the sources of said plurality of memory cells; and a read circuit selecting any of said plurality of memory cells in accordance with an address signal and reading a data signal of the selected memory cell, said read circuit including a first word line drive circuit applying a predetermined first potential to a word line corresponding to said selected memory cell while applying a ground potential to another word line, a first bit line drive circuit applying a predetermined second potential to a bit line corresponding to said selected memory cell while applying a ground potential to other bit lines, a first source line drive circuit applying the ground potential to said source line, and a current detection circuit detecting whether or not a current flows through the bit line corresponding to said selected memory cell and outputting a data signal at a level corresponding to a detection result.