Patent ID: 6571348
Filing Date: 2003-05-27
Classification: G11C

Abstract:
An apparatus for accessing a memory structure including a main memory array and a redundant memory array comprising:a. an address bus for carrying addressing information for a current memory access operation; b. a main column pathway including a main column decoder for decoding addressing information and a main select circuit for selecting appropriate groups of memory cells within the main memory array for the current memory access operation; and c. a redundant column pathway including a redundant column decoder for decoding addressing information having a first output for providing a decoded redundant address and a second output for providing a disable signal, and further including a redundant select circuit for selecting appropriate groups of memory cells within the redundant memory array for the current memory access operation if the first output of the redundant column decoder is providing the decoded redundant address and the second output is providing the disable signal, wherein the addressing information is decoded by the redundant column decoder before the addressing information is decoded by the main column decoder.