Patent ID: 6845056
Filing Date: 2005-01-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: first and second memory blocks, each memory block including a plurality of memory cells arranged in a matrix; a sense amplifier band shared by said first and second memory block, including a plurality of sense amplifiers; an isolation gate circuit for connecting one of said first and second memory blocks to said sense amplifier band and isolating the other of said first and second memory blocks from said sense amplifier band at the time of transmitting data to and receiving data from the one of said first and second memory blocks; a control circuit for decoding an address signal, outputting first and second section signals indicative or selection of said first and second memory blocks, and outputting a trigger signal respectively indicative of timing of activating a row of either one of said first and second memory blocks in accordance with a command; and an isolation control unit for outputting a first isolation gate signal for isolating said first memory block from said sense amplifier band, and a second isolation gate signal for isolating said second memory block from said sense amplifier band, to said isolation gate circuit in accordance with the trigger signal and the first and second selection signals, said isolation control unit including a first holding circuit for latching and holding the first selection signal in accordance with the trigger signal, and a second holding circuit for latching and holding the second selection signal in accordance wih the trigger signal.