Patent ID: 7265622
Filing Date: 2007-09-04
Classification: H03F

Abstract:
1. A differential difference amplifier comprising: first and second low supply output terminals and first and second high supply output terminals, one or more of the first and second low supply output terminals and one or more of the first and second high supply output terminals being coupled to a low voltage terminal and a high voltage terminal, respectively; a first bias regulator comprising a first output terminal to supply a first bias voltage and a second output terminal to supply a second bias voltage; a second bias regulator comprising first and second output terminals; first, second, third, and fourth current control PMOS transistors each having a gate, a source, and a drain, the sources being coupled to one another and to the second high supply output terminal, the gates of the first and second current control PMOS transistors being coupled to first and second terminals of a first pair of differential input terminals, respectively, and the gates of the third and fourth current control PMOS transistors being coupled to first and second terminals of a second pair of differential input terminals, respectively; first and second load current control PMOS transistors each having a gate, a source, and a drain, the sources being coupled to the first high supply output terminal, and the gates of the first and second load current control PMOS transistors being coupled to the first output terminal of the first bias regulator; first, second, third, and fourth current control NMOS transistors each having a gate, a source, and a drain, the sources being coupled to each other and to the second low supply output terminal, the gates of the first and second current control NMOS transistors being coupled to the first and second terminals of the first pair of differential input terminals, respectively, and the gates of the third and fourth current control NMOS transistors being coupled to the first and second terminals of the second pair of differential input terminals, respectively; first and second load current control NMOS transistors each having a gate, a source, and a drain, the sources being coupled to the first low supply output terminal, and the gates being coupled to the second output terminal of the first bias regulator; first and second voltage control PMOS transistor circuits each having a gate terminal, at least one source terminal, and a drain terminal, the at least one source terminal of the first voltage control PMOS transistor circuit being coupled to the drains of the first and fourth current control PMOS transistors and to the drain of the first load current control PMOS transistor, the at least one source terminal of the second voltage control PMOS transistor circuit being coupled to the drains of the second and third current control PMOS transistors and to the drain of the second load current control PMOS transistor, the gate terminal of the first voltage control PMOS transistor circuit being coupled to the first output terminal of the second bias regulator, and the gate terminal of the second voltage control PMOS transistor circuit being coupled to the second output terminal of the second bias regulator; and first and second voltage control NMOS transistor circuits each having a gate terminal, at least one source terminal, and a drain terminal, the at least one source terminal of the first voltage control NMOS transistor circuit being coupled to the drains of the first and fourth current control NMOS transistors and to the drain of the first load current control NMOS transistor, the at least one source terminal of the second voltage control NMOS transistor circuit being coupled to the drains of the second and third current control NMOS transistors and to the drain of the second load current control NMOS transistor, the gate terminal of the first voltage control NMOS transistor circuit being coupled to the first output terminal of the second bias regulator, and the gate terminal of the second voltage control NMOS transistor circuit being coupled to the second output terminal of the second bias regulator, the drain terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit being coupled to a first terminal of a pair of differential output terminals, and the drain terminals of the first voltage control PMOS transistor circuit and the first voltage control NMOS transistor circuit being coupled to a second terminal of the pair of differential output terminals.