Patent ID: 6233187
Filing Date: 2001-05-15
Classification: G11C

Abstract:
In a semiconductor memory device that includes a plurality of memory cells, each including a transistor and a capacitor, the capacitors having a first node coupled to the corresponding transistor and a second node that can be placed at an opposite-to-cell level, the semiconductor memory device using an approximately half power source level for the opposite-to-cell level and a digit line precharge level, the semiconductor memory device comprising:a level generating means to provide the approximately half power source level as the opposite-to-cell level and the precharge level; anda plurality of shunting means to shunt the opposite-to-cell level and the precharge level, each shunting means comprises a shunt testing circuit to interrupt a connection that shunts the opposite-to-cell level and the precharze level during a test mode.