Patent ID: 7894280
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. An integrated circuit, comprising: a memory array comprising a plurality of SRAM memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality of bit lines for accessing columns of cells; said plurality of memory cells including a plurality of asymmetric cells, each of said asymmetric cells configured with a strong side including a first inverter having a strong side latch node, and a strong side pass transistor coupled to said strong side latch node, and a weak side including a second inverter cross-coupled with said first inverter having a weak side latch node and a weak side pass transistor coupled to said weak side latch node, wherein said plurality of word lines are coupled to at least one of a gate of said strong side pass transistor and a gate of said weak side pass transistor; and a read and write-back circuitry coupled between bit lines associated with said cells.