Patent ID: 7132717
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A power metal oxide semiconductor transistor layout comprising: a gate electrode with a lattice pattern on a substrate having a first area and a second area; a plurality of source regions laid in said lattice pattern; a plurality of drain regions laid in said lattice pattern, each said source region is laid to be surrounded by said drain regions; a first meshwork of conductive lead connecting said source regions on said first area; a second conductive plane connecting said drain regions on said first area and over said first meshwork of conductive lead and said first area; a third meshwork of conductive lead connecting said drain regions on said second area; and a fourth conductive plane connecting said source regions on said second area and over said third meshwork of conductive lead and said second area, said first meshwork of conductive lead connects said fourth conductive plane, and said second conductive plane connects said third meshwork of conductive lead.