Patent ID: 6255175
Filing Date: 2001-07-03
Classification: H01L,Y10S

Abstract:
A method for fabricating a field effect transistor, with minimized parasitic Miller capacitance, within an active device area of a semiconductor substrate, the method including the steps of:A. forming a gate structure on a gate dielectric on said semiconductor substrate over a portion of said active device area, said gate structure being doped with a first type of dopant;B. forming a drain extension within an exposed portion of said active device area of said semiconductor substrate on a drain side of said gate structure, said drain extension having a drain overlap that extends under said gate structure; andC. doping a sidewall of said gate structure at said drain side of said gate structure with a second type of dopant that is opposite to said first type of dopant, said second type of dopant forming a depletion region from said sidewall at said drain side of said gate structure into approximately an edge of said drain overlap that extends under said gate structure to reduce a parasitic Miller capacitance formed by said drain overlap.