Patent ID: 7681012
Filing Date: 2010-03-16
Classification: G06F

Abstract:
1. A method of handling memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor, the DSP including a memory management unit (“DSP MMU”) to manage memory access by the DSP, the DSP and the microprocessor accessing shared physical memory, the microprocessor including an interrupt handler to be activated in response to a page fault interrupt, comprising: (A) in the DSP, executing an instruction attempting to access a virtual address wherein the virtual address is invalid, and causing a page fault interrupt to be generated by the DSP MMU; (B) activating a microprocessor interrupt handler in the microprocessor in direct response to the page fault interrupt, and thereafter in the microprocessor: (1) creating a translation lookaside buffer (“TLB”) entry in the DSP MMU, the TLB entry including a valid mapping between the virtual address and a page of physical memory; (2) after creating the TLB entry, indicating to the DSP that the access by the DSP of the virtual address is completed, wherein the DSP processes the completion of the access of the virtual address.