Patent ID: 7522462
Filing Date: 2009-04-21
Classification: G11C

Abstract:
1. A sense amplifier comprising: first and second input nodes, to one of which a cell current is provided, a reference current being provided to the other; first and second output nodes, to which cell data are amplified and output, the cell data being defined by the difference between the cell current and the reference current; first and second NMOS transistors, drains thereof being coupled to the first and second output nodes, respectively, gates thereof being coupled to the second and first output nodes, respectively, sources thereof being coupled in common to a ground potential node; first and second PMOS transistors, drains thereof being coupled to the drains of the first and second NMOS transistors, respectively, sources thereof being coupled to the second and first input nodes, respectively, the first and second PMOS transistor constituting a latch with the first and second NMOS transistors; third and fourth PMOS transistors, drains thereof being coupled to the second and first input nodes, respectively, gates thereof being coupled to the second and first output nodes, respectively, sources thereof being coupled in common to a power supply node via a current source switching device; third and fourth NMOS transistors disposed between the second and first output nodes and the ground potential node, respectively, and turned on before sensing; and an equalizing transistor disposed between the first and second output nodes to equalize the first and second output nodes in potential before sensing, wherein the current source switching device is a fifth PMOS transistor, which is driven by an activation signal, the third and fourth NMOS transistors are off-driven by a sense signal generated after the activation signal, and the equalizing transistor is a fifth NMOS transistor, which is off-driven by the sense signal at the same time as the third and fourth NMOS transistors; and bit line precharging NMOS transistors disposed at the first and second input nodes, which are driven for a certain period prior to the activation signal to precharge bit lines to be coupled to the first and second input nodes; and separating NMOS transistors disposed between the first and second input node and the sense amplifier body portion, which are driven as complementary to the fifth PMOS transistors.