Patent ID: 6720208
Filing Date: 2004-04-13
Classification: H01L,H05K

Abstract:
A method of manufacturing a semiconductor package comprising the steps of:(a) providing a semiconductor chip and lead frame, said semiconductor chip including a plurality of semiconductor elements and bonding pads formed on a main surface thereof, said semiconductor chip having a first pair of opposed edges extending in a first direction and a second pair of opposed edges extending in a second direction substantially perpendicular to said first direction, said bonding pads being arranged in said first direction; said lead frame having a plurality of leads each having an inner lead and an outer lead which is continuous with said inner lead, tips of said inner leads of said plurality of leads being arranged at a space in said first direction; said semiconductor chip being provided by steps of: (1) providing a semiconductor wafer having a main surface including a plurality of chip forming areas which are compartmentalized by dicing lines, each of said plurality of chip forming areas including said plurality of semiconductor elements and said bonding pads; (2) coating said main surface of said semiconductor wafer, except for said bonding pads, with a polyimide film; (3) after step (2), cutting said semiconductor wafer by dicing, along said dicing lines, thereby to form a plurality of semiconductor chips each having said polyimide film, said semiconductor elements and said bonding pads; (b) after the step (a), attaching one of said semiconductor chips to said lead frame such that said tips of said inner leads are disposed over said polyimide film of said semiconductor chip and are adhered to said semiconductor chip by an adhesive layer between said polyimide film and said tips of said inner leads, said adhesive layer extending in said first direction and being arranged along said bonding pads; (c) after the step (b), electrically connecting said tips of said inner leads with said bonding pads by bonding wires; and (d) after the step (c), sealing said semiconductor chip with said polyimide film, said inner leads, said adhesive layer and said bonding wires with a resin member, wherein an area occupied by said adhesive layer is smaller than an area of said polyimide film, and wherein said area of said adhesive layer has a shape which is substantially rectangular, of which a length in said first direction is longer than a length in said second direction in a plane view.