Patent ID: 6642765
Filing Date: 2003-11-04
Classification: H03K

Abstract:
An apparatus comprising:flip-flop circuitry including; an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal, a clock terminal configured to provide a timing signal for reception of the input signal at the input and transmission of the output signal at the output, two on-path inverters connected serially between the input and output, the two on-path inverters being configured not to respond to the timing signal, two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signal, two transmission gate transistors respectively connected serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter, and a pair of additional transistors connected in parallel with one of the transmission gate transistors.