Patent ID: 6794750
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A semiconductor device comprising:a wiring substrate having a predetermined pattern of wiring formed on one surface, said wiring having a common wiring; a semiconductor chip disposed on the other surface of said wiring substrate, and having a common wiring layer and at least one chip electrode set comprising at least two chip electrodes connected to said common wiring layer, wherein said at least two chip electrodes are arranged from an edge of said semiconductor chip toward its inner side; said wiring substrate having at least one through-hole set comprising at least two through-holes formed in conforming relationship with said at least two chip electrodes; and at least one bump set comprising at least two pairs of bumps, each pair of which is formed in any one of said at least two through-holes of said wiring substrate and electrically connecting between said common wiring of said wiring substrate and said at least two chip electrodes, wherein said at least two pairs of bumps each comprise a first bump and a second bump integrated with each other.