Patent ID: 8188953
Filing Date: 2012-05-29
Classification: H01L,H03K

Abstract:
1. A semiconductor device which receives differential input signals, performs predetermined signal processing, and outputs differential output signals, the semiconductor device comprising: a timing control circuit which drives a liquid crystal panel which, after a luminance signal and a clock signal according to color are respectively inputted as the differential input signals, and the predetermined signal processing is carried out, outputs a drive signal to an external liquid crystal driver as a differential output signal; and a plurality of rear surface electrodes disposed in an m-row, n-column matrix form on a rear surface of the semiconductor device, m and n being integers greater than or equal to 4; wherein the rear surface electrodes for the differential input signals and the differential output signals are disposed in rows, 1, 2, m−1, and m, or in columns, 1, 2, n−1, and n; and rear surface electrodes for the differential input signals that form a pair are disposed so as to be adjacent, and the rear surface electrodes for the differential output signals that form a pair are disposed so as to be adjacent, and wherein the semiconductor device has a ball grid array structure of a leadframe type, and further comprises: a semiconductor chip on which a circuit, which performs the predetermined signal processing, is formed; and a substrate on which the semiconductor chip is mounted; and wherein the substrate includes: the plurality of rear surface electrodes arranged in matrix form on a rear surface of a surface on which the semiconductor chip is mounted; a plurality of lead electrodes connected through bonding wire to electrode pads arranged on the semiconductor chip; and via holes and wiring connecting the plurality of lead electrodes and the plurality of rear surface electrodes, and wherein, among the via holes by which the differential input signals and differential output signals are transmitted, via holes, disposed on an inner track side of rear surface electrodes of a track that is one track inside from an outermost track, are connected to rear surface electrodes of row 2 and row m−1, or of column 2 and column n−1 column.