Patent ID: 7371589
Filing Date: 2008-05-13
Classification: H01L

Abstract:
1. A method for manufacturing a ferroelectric random access memory (FeRAM) capacitor, the method comprising the steps of: a) preparing an active matrix including a semiconductor substrate, a source/drain region, FOX regions, a first ILD, a storage node contact; b) forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; c) forming a hard mask on a predetermined location of the second conductive layer; d) patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a capacitor stack having a bottom electrode, a ferroelectric layer and a top electrode, a width of the capacitor stack being larger than that of the storage node contact; e) forming a second ILD on the first ILD and the hard mask, wherein the second ILD embraces the capacitor stack; f) planarizing the second ILD till the top face of the hard mask is exposed; g) removing the hard mask to form an opening above the top electrode; and h) forming a third conductive layer over the resultant structure and patterning into a predetermined configuration, thereby obtaining a plate line of which a width is larger than that of the capacitor stack, the plate line being electrically connected to the top electrode.