Patent ID: 6759329
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method of fabricating a semiconductor chip, comprising the steps of:providing a substrate with a plurality of signal circuit macros and a electro-static discharge clamping circuit ring formed with power/ground circuit, wherein the signal circuit macros and the electro-static discharge clamping circuit ring are insulated to each other; forming a plurality of conductive layers sequentially above part of the substrate, wherein insulating layers are formed between the conductive layers; forming a plurality of bonding pads on part of the conductive layers, wherein the bonding pads are positioned in at least four rows, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row; and forming a plurality of vias in the insulating layers, wherein the outer row and the mid-outer row of the bonding pads is connected to a predetermined portion of the conductive layers above the signal circuit macros by the conductive layers and the electro-static discharge clamping circuit ring to form a first signal line, the inner row and the mid-inner row of the bonding pads is connected to the signal circuit macros by the conductive layers to form a second signal line, and the first signal line and the second signal line are insulated to each other.