Patent ID: 6339806
Filing Date: 2002-01-15
Classification: G06F

Abstract:
An electronic system, comprising:a primary I2C bus for communicating start bits, address bits, data bits, acknowledgment bits and stop bits over an SDA line of said primary I2C bus, wherein a block of data bits is followed by an acknowledgment bit and a stop bit; a plurality of secondary I2C buses; an expander having a unique I2C address, said expander having a bus port coupled to said primary I2C bus, said expander including a plurality of outputs that can be selectively activated; a controller coupled to said primary I2C bus, said controller activating a selected one of the outputs of said expander by transmitting said unique I2C address to the bus port of said expander, followed by the transmission of a predetermined block of data bits to the bus port of said expander; a bus switch having a bus input coupled to said primary I2C bus and a plurality of bus outputs, each of said plurality of secondary I2C buses being coupled to a unique one of the bus outputs of said bus switch, said bus switch also having a plurality of control inputs, said primary I2C bus being connected to a unique one of said secondary I2C buses in response to a unique one of the control inputs being activated; and a plurality of delay circuits, each one of said delay circuits being coupled between a unique one of the outputs of said expander and a unique one of the control inputs of said bus switch, each one of said delay circuits delaying the activation of the corresponding control input of said bus switch until after an acknowledgment bit and a stop bit have been communicated over said primary I2C bus.