Patent ID: 6938148
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. An apparatus for managing operations in a processor, said apparatus comprising: a plurality of addressable registers, each of said registers partitioned into plurality of data entry fields; a first comparison circuit operable to scan a like data entry field of said plurality of addressable registers and compare data in said like data entry fields to predetermined input data; a second comparison circuit operable to compare a first register address of a first register in said plurality of addressable registers to a second register address of a second register in said plurality of addressable registers, wherein said first register address corresponds to a first register that has said data in said like data entry field that matches said predetermined input data; and a dispatch circuit operable to dispatch data of a second data entry field of said second register to an operation unit in response to a decode of data in a third data entry field of said second register when said second comparison circuit indicates said second register address matches said first register address.