Patent ID: 7983362
Filing Date: 2011-07-19
Classification: G11C,H03K

Abstract:
1. A receiver architecture for a computer processor, the receiver architecture comprising: a linear receiver portion having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal, the linear receiver portion being configured to compare the DQ signal to the reference voltage, and to generate the differential output signal in response to the comparison; a sense amplifier portion coupled to the linear receiver portion, the sense amplifier portion having input nodes connected to the output nodes of the linear receiver portion, and an output node for a binary output signal having voltage characteristics compatible with the computer processor, the sense amplifier portion being configured to transform the differential output signal into the binary output signal; and a programming architecture coupled to the linear receiver portion, the programming architecture being configured to set operating characteristics of the linear receiver portion; wherein the linear receiver portion comprises: