Patent ID: 6324286
Filing Date: 2001-11-27
Classification: H04L

Abstract:
A full duplex DES processor comprising an I/O unit receiving an input to be encrypted/decrypted, an IV/key storage unit, an algorithm unit and a control unit, wherein said algorithm unit comprises:a key generation sub-unit for generating a plurality of subkeys;a crypto engine comprising:an input buffer for registering the input;an n-round DES device for encrypting/decrypting the input registered in said input buffer according to said subkeys to generate a corresponding cipher text/plain text;a cipher text buffer for storing the cipher text generated by said n-round DES device;a plain text buffer for storing the plain text generated by said n-round DES device; anda first multiplexor and a second multiplexor, said first multiplexor selectively supplying the input registered in said input buffer or an output of said second multiplexor to said n-round DES device, and said second multiplexor selectively outputting the cipher text stored in said cipher text buffer or the plain text stored in said plain text buffer;a mode selection sub-unit for processing the input to be encrypted/decrypted and the cipher text/plain text in said cipher text buffer/plain text buffer according to a selected encryption/decryption mode to obtain an encrypted/decrypted output for the next encryption/decryption; andan output multiplexor for selectively outputting the encrypted/decrypted output of said mode selection sub-unit or the cipher text/plain text of said cipher text buffer/plain text buffer according to said selected encryption/decryption mode.