Patent ID: 8045706
Filing Date: 2011-10-25
Classification: H04L

Abstract:
1. A system of implementing the secure hash algorithm (SHA-1) for completing an 81-step SHA-1 computation in exactly 81 clock cycles, said system comprising: an addressable quad-channel output memory (QCOM) having one data input channel and multiple data output channels for simultaneously retrieving multiple data elements from different memory locations referenced by an address value; a SHA-1 Logic Core coupled to the multiple data output channels of the QCOM to receive necessary data for the 81-step SHA-1 computation; and a central control unit (CCU) coupled to both said QCOM and said SHA-1 Logic Core for controlling the 81-step SHA-1 computation and allowing an external system to access the 81-step SHA-1 computation; wherein the SHA-1 Logic Core comprises: wherein the quad-channel output memory comprises: