Patent ID: 7880518
Filing Date: 2011-02-01
Classification: H03D,H03L

Abstract:
1. A circuit for static phase error measurement, comprising: a reference clock delay chain having a selectable number of delay elements, a number of which are enabled in accordance with a select length signal to delay a reference clock signal; a feedback signal delay chain having a selectable number of delay elements, a number of which are enabled in accordance with a select length signal to delay a feedback signal; a latch which tests for phase alignment between the delayed reference clock signal and the delayed feedback signal and outputs a measurement of static phase error; a NAND gate configured to output a count and take as input the output from the latch and the delayed reference signal, wherein the output of the NAND gate is coupled to a first filter and the delayed feedback signal is coupled to a second filter having a capacitance twice as great as the first filter; and a comparator which compares output signals from the first and second filters to provide the measurement.