Patent ID: 7576583
Filing Date: 2009-08-18
Classification: H03K

Abstract:
1. A single-event effect tolerant latch circuit comprising: a dual-port inverter ( a dual-port clocked inverter ( an output node connected to at least one of the two output nodes of said dual-port inverter ( said dual-port inverter ( said first inverter ( said second inverter ( each of said 1st and 3rd transistors ( each of said 2nd and 4th transistors ( a gate of said 1st transistor ( a gate of said 2nd transistor ( said 1st and 2nd transistors ( said 3rd and 4th transistors ( said first and second inverter input nodes are adapted to receive identical inputs to provide a valid output at either said first inverter output node or said second inverter output node; a third inverter ( a fourth inverter ( wherein: said third inverter ( said fourth inverter (