Patent ID: 6741510
Filing Date: 2004-05-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array, and a test circuit consecutively applying plural stresses to said memory cell array in response to a transition request to a burn-in test mode, wherein said memory cell array includes: mÃ—n (m and n are each a natural number) memory cells arranged in a matrix; m word lines extending in a row direction; and n bit line pairs extending in a column direction, said test circuit includes: a peripheral circuit writing data to said memory cell array; a select circuit selecting said m word lines; and a control circuit generating a transition signal for causing transition to said burn-in test in response to said transition request to output said transition signal to said select circuit, said select circuit, in response to said transition signal, selects/does not select said m word lines such that said plural stresses are consecutively applied to said memory cell array, and said peripheral circuit, in response to the selection of said word lines, writes a data pattern for applying said plural stresses to memory cells connected to said selected word lines while, in response to the non-selection of said word lines, writing said data pattern to said n bit line pairs.