Patent ID: 6335638
Filing Date: 2002-01-01
Classification: G06F,H03K

Abstract:
A pulsed-rive clock buffer comprising:a clock output; an input indicating when the clock output is to transition; an inverter, receiving the input, for driving a weak-gate node; a weak p-channel transistor, having a gate connected to the weak-gate node, for driving the clock output high throughout a high-going transition; a weak n-channel transistor, having a gate connected to the weak-gate node, for driving the clock output low throughout a low-going transition; a first pulse generator, responsive to the input, for generating a low-going pulse; a p-channel driver transistor, having a gate connected to the first pulse generator to receive the low-going pulse, for momentarily driving the clock output high during the high-going transition; wherein the p-channel driver transistor has a larger current drive than the weak p-channel transistor; a second pulse generator, responsive to the input, for generating a high-going pulse; and an n-channel driver transistor, having a gate connected to the second pulse generator to receive the high-going pulse, for momentarily driving the clock output low during the low-going transition; wherein the n-channel driver transistor has a larger current drive than the weak n-channel transistor; wherein the p-channel driver transistor is pulsed on after a start of the high-going transition and is pulsed off before an end of the high-going transition; wherein the n-channel driver transistor is pulsed on after a start of the low-going transition and is pulsed off before an end of the low-going transition, whereby the driver transistors are pulsed on and off during transitions but the weak transistors drive the clock output for each entire transition and whereby the driver transistors are pulsed on and off in a middle of clock transitions.