Patent ID: 6535406
Filing Date: 2003-03-18
Classification: H02M

Abstract:
A gate control device for a three-level inverter, comprising:first, second, and third d.c. terminals having first, second, and third potential levels, respectively; first, second, third, and fourth self-arc extinction elements connected in series between said first and third d.c. terminals; first and second clamp diodes connected between a node of said first and second self-arc extinction elements and a node of said third and fourth self-arc extinction elements in reverse parallel with said second and third self-arc extinction elements; fifth and sixth self-arc extinction elements connected between respective terminals of and in reverse parallel with said first and second clamp diodes, individually, in which a node of said first and second clamp diodes is connected to the second d.c. terminal; a PWM circuit that generates a first conduction control command with respect to said first and third self-arc extinction elements and a second conduction control command with respect to said second and fourth self-arc extinction elements; and a gate control circuit that generates gate signals with respect to the gates of said first, second, third, fourth, fifth, and sixth self-arc extinction elements based on the first and second conduction control commands, wherein said gate control circuit comprises: first and second inversion circuits that invert the first and second conduction control commands, individually, to produce inverted first and second conductive control commands; and a delay circuit group that generates the gate signals based on the first and second conduction control commands and the inverted first and second conduction control commands, and wherein said third and fifth self-arc extinction elements are rendered conductive at the same time, and said second and sixth self-arc extinction elements are rendered conductive at the same time.