Patent ID: 6103585
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A process of etching a vertical trench in a semiconductive wafer by reactive ion etching to form a part of a trench capacitor comprising the steps of:supporting the wafer in a plasma-etching chamber through which is flowed a gaseous mixture that includes at least one species that provides reactive ions suitable for etching and another species that serves to enhance the formation of a trench wall coating; andvarying the temperature of the wafer during the reactive ion etching process whereby there results a vertical trench whose diameter varies with increasing depth from a first diameter to a wider second diameter, then back to a diameter of essentially the first diameter, and then back to essentially the second diameter, whereby there is formed a trench of larger surface area than would result by maintaining the temperature at a substantially constant value for a fixed thermal budget.