Patent ID: 9190330
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing a substrate; providing a fin protruding upwardly from or through a surface of the substrate, the fin having a first semiconductor layer portion formed of a corresponding first semiconductive material having a respective first conductivity type; forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin that corresponds to a channel region to be formed at that enwrapped first portion; forming a first insulating material layer so as to at least cover an exposed second portion of the fin that is not enwrapped by the dummy gate, the formed first insulating material layer leaving exposed a top surface of the dummy gate; selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate while not exposing the second portion of the fin that is covered by the first insulating material layer; and introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant that is capable of imparting a second conductivity type to the semiconductive parts of the fin it is introduced into, so as to thereby form a channel region having the first conductivity type and at least two opposed channel control regions having the second conductivity type, the at least two opposed channel control regions being disposed for selectively generating charge depletion zones at and into opposed sides of the channel region for thereby selectively controlling current conduction through the channel region, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.