Patent ID: 9208113
Filing Date: 2015-12-08
Classification: G06F,Y02D

Abstract:
1. A method to process interrupts in a multiple processor system which comprises at least a first processor and a second processor and an interrupt controller which is coupled to the first processor and to the second processor and to at least one source for interrupts, the method comprising: receiving at the first processor, from the interrupt controller, a first interrupt and processing the first interrupt with an interrupt handler that is executing on the first processor while the second processor is in a low power sleep state, the processing of the first interrupt creating a runnable thread; requesting, by the first processor in response to the creation of the runnable thread, a deferred inter-processor interrupt (IPI) by sending a deferred IPI to the interrupt controller; starting a timer in the interrupt controller in response to the deferred IPI; cancelling the deferred IPI in response to determining, before the timer in the interrupt controller times out, that the first processor is available to execute the runnable thread, the cancelling including sending a cancel signal, to cancel the deferred IPI from the first processor to the interrupt controller.