Patent ID: 8884642
Filing Date: 2014-11-11
Classification: G01R,G11C

Abstract:
1. A circuit having an external test voltage, the circuit comprising: an amplifier having a first input terminal for receiving a first voltage, a second input terminal for receiving a reference voltage, a third input terminal, and an output terminal; a first P-type metal-oxide-semiconductor transistor having a first terminal for receiving the first voltage, a second terminal coupled to the output terminal of the amplifier, and a third terminal; a second P-type metal-oxide-semiconductor transistor having a first terminal for receiving the first voltage, a second terminal coupled to the output terminal of the amplifier, and a third terminal; at least one reference resistor having a first terminal coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor, and a second terminal, wherein each reference resistor has a reference output terminal; at least one test resistor having a first terminal coupled to the third terminal of the second P-type metal-oxide-semiconductor transistor, and a second terminal, wherein each test resistor has a test output terminal, and a resistance of the test resistor is equal to a resistance of a corresponding reference resistor; a first upper resistor having a first terminal coupled to the second terminal of the at least one reference resistor, and a second terminal coupled to the third input terminal of the amplifier; a second upper resistor having a first terminal directly coupled to the second terminal of one of the at least one test resistor in series, and a second terminal for receiving the external test voltage, wherein a current flowing through the at least one test resistor is equal to a current flowing through the at least one reference resistor and a voltage of the test output terminal corresponds to the external test voltage and the reference voltage according to relationships of the current flowing through the at least one test resistor being equal to the current flowing through the at least one reference resistor, the resistance of the test resistor being equal to the resistance of the corresponding reference resistor when the circuit is in a chip test period, and the current flowing through the at least one test resistor flows through the second upper resistor; and a lower resistor having a first terminal coupled to the third input terminal of the amplifier, and a second terminal coupled to ground.