Patent ID: 6399286
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A fabrication method for reducing a critical dimension of a conductive line and a space comprising the steps of:providing a substrate; forming a conductive layer on the substrate; forming a mask layer on the conductive layer; performing a first tapered etching on the mask layer till the conductive layer is exposed through a plurality of first openings, wherein the first openings are tapered off from top to bottom; forming a planarized sacrificial layer to fill the first tapered openings; performing a second tapered etching on the mask layer till the conductive layer is exposed through a plurality of second openings, wherein the second openings are tapered off from top to bottom; removing the sacrificial layer; patterning the conductive layer using the mask layer as a patterned hard mask; and removing the patterned mask layer.