Patent ID: 9184146
Filing Date: 2015-11-10
Classification: H01L,H05K

Abstract:
1. A semiconductor package comprising: a chip; a sealing body covering the chip; and a plurality of external connection terminals being electrically connected to the chip and exposed from a surface of the sealing body, the plurality of external connection terminals being arranged on a separate one of intersection points of first imaginary tines in rows and second imaginary lines in columns on the surface of the sealing body, wherein each external connection terminal is adjacent to an intersection point that is vacant of another external connection terminal in at least one direction of eight directions from each external connection terminal, the eight directions including first linear directions along a row of the rows, second linear directions along a column of the columns perpendicular to the first linear directions, and four diagonal directions defined between the first linear directions and the second linear directions, and each of the first imaginary lines and each of the second imaginary lines includes at least one of the plurality of external connection terminals except for two outer-most lines in the rows and in the columns, which do not include any of the plurality of external connection terminals.