Patent ID: 8574977
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: 1) growing an interface oxide or oxynitride layer on a semiconductor substrate after conventional LOCOS or STI dielectric isolation is completed; 2) forming a high-K gate dielectric film on the interface oxide or oxynitride layer and performing thermal annealing at about 500-1020° C. for about 4-120 seconds; 3) depositing a metal gate comprising a first TiN layer, an Al film, and a second TiN layer in sequence; 4) depositing a barrier metal layer on the metal gate; 5) depositing a polysilicon film and a hard mask on the barrier metal layer by low-pressure chemical vapor deposition and then performing photolithography and etching the hard mask; 6) removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface SiO 7) forming first spacers and performing source/drain extension region low-energy ion implantation and large-angle implantation; 8) forming second spacers and performing source/drain region ion implantation; 9) performing rapid thermal annealing in N 10) forming a NiSi film; and 11) forming contacts on the NiSi film and metalizing by alloying annealing in N