Patent ID: 7434032
Filing Date: 2008-10-07
Classification: G06F

Abstract:
1. A method of issuing instructions to be executed by a processing unit, comprising the steps of: comparing register IDs of registers specified in an instruction to be issued with one or more register IDs of registers that have pending writes, wherein the registers specified in the instruction include source and destination registers; generating an aggregate comparison result based on the comparison of the register IDs of the registers specified in the instruction to be issued; issuing the instruction for execution when the register IDs of registers specified in the instruction to be issued do not match any of the register IDs of registers that have pending writes; storing one or more register IDs of registers that have pending writes in memory when instructions that specify registers for pending writes are issued; storing in the memory, for each register ID stored in the memory, a size indicator associated with said each register ID, wherein the size indicator is an integer that reflects the number of sequential registers among the registers specified in the instruction; and removing the one or more register IDs of registers from the memory when instructions that specify said registers for pending writes are completed, wherein the step of comparing is carried out using the one or more register IDs stored in a location in the memory allocated to a thread of instructions that includes the instruction to be issued.