Patent ID: 7630242
Filing Date: 2009-12-08
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a plurality of memory blocks formed on a surface of a single well, each memory block having a plurality of memory cells that are arranged in a plurality of rows and a plurality of columns, and a word line provided corresponding to each row and connected to a gate of corresponding each memory cell; and an erase circuit conducting batch erasure of stored data for said plurality of memory cells included in a memory block to be erased out of said plurality of memory blocks, wherein a source of each memory cell of said plurality of memory blocks is connected to a predetermined node, and said erase circuit includes: a first drive circuit applying a first voltage to said well and said predetermined node; and a second drive circuit applying the output voltage of said first drive circuit to each word line of a memory block to be not erased out of said plurality of memory blocks, as well as a second voltage to each word line of the memory block to be erased, the second voltage being different said first voltage.