Patent ID: 6838366
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A method for manufacturing a MOS transistor having a gate electrode including silicide, the method comprising: successively depositing polysilicon and a buffer film on a gate dielectric layer over a silicon semiconductor substrate surrounded by an element isolation region to form a polysilicon gate electrode having the buffer film deposited on a top surface thereof, and patterning the polysilicon gate electrode; introducing an impurity to form source and drain diffusion layers using at least a region of the polysilicon gate electrode and buffer film as a mask; depositing an insulation member that covers the polysilicon gate electrode and the buffer film; forming side walls for the buffer film and the polysilicon gate electrode by anisotropically etching the insulation member; forming a first conductive film over the source and drain regions adjacent to the sidewalls on sides of the polysilicon gate electrode; conducting a first heat treatment to silicidize the first conductive film to selectively form a first silicide on the source and drain regions; depositing an insulation layer on the buffer film and on the first silicide, wherein the buffer film and the insulating layer are formed from the same material; planarizing the insulation layer to remove the buffer film on the polysilicon gate electrode and expose a top surface of the polysilicon gate electrode; forming a second conductive film to cover at least the top surface of the polysilicon gate electrode; and conducting a second heat treatment to silicidize the second conductive film to selectively form a second silicide on the polysilicon gate electrode.