Patent ID: 7913136
Filing Date: 2011-03-22
Classification: G01R

Abstract:
1. A method for performing, using instructions stored on non-transitory computer readable medium, a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits and storage elements and connected serially to a number of LBIST stumps between a pseudo-random-pattern generator and a multiple-input-signature register, wherein at least one constrained logic circuit requires constrained values as input signals and said method comprises the following steps: scanning the LBIST stumps with the pseudo-random-pattern generator, deactivating or resetting the multiple-input-signature register, performing a functional update in order to propagate legal values into those storage elements, which require constrained values, activating the multiple-input-signature register, and setting or programming a start value in a counter for activating a loop back circuit (