Patent ID: 6640315
Filing Date: 2003-10-28
Classification: G06F

Abstract:
In a microprocessor system that supports non-speculative and speculative execution of instructions, a method for performing inline recovery for a first excepting speculative instruction where execution was deferred because a first exception event was encountered during speculative execution, said method comprising the steps of:when said first exception event is encountered during speculative execution, storing information to indicate that said first exception event occurred and storing information relating to a program counter associated with said first excepting speculative instruction, for a subsequent speculative instruction that is data flow dependent upon said first excepting speculative instructions deferring execution of said subsequent speculative instruction, propagating and storing exception information for said first excepting speculative instruction in association with said subsequent speculative instruction, and for a subsequent non-speculative instruction that is data flow dependent upon said first excepting speculative instruction, performing an inline recovery process that re-executes speculatively those set of speculative instructions that are data flow dependent upon said first excepting instruction.