Patent ID: 9055249
Filing Date: 2015-06-09
Classification: H04N

Abstract:
1. A system for correcting a column line failure in an imager comprising: an array of CMOS active pixels arranged in rows and columns, wherein the array of CMOS active pixels captures color images; a pixel selection circuit that receives three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1)th column line, nth column line and (n+1)th column line, the (n−1)th column line disposed left of an nth column line, and the (n+1)th column line disposed right of the nth column line, and a pattern generator that generates a bit pattern denoting a column line failure in the three adjacent column lines based on whether the column line failure occurs in an even column or an odd column, wherein the pixel selection circuit outputs a pixel output signal from one of the three adjacent column lines, based on the bit pattern and a bit value of a first column line, wherein the pixel selection circuit shifts the pixel output signal to the left when the column line failure occurs in an even column and shifts the pixel output signal to the right when the column line failure occurs in an odd column.