Patent ID: 6420922
Filing Date: 2002-07-16
Classification: H03H,H03K,H03L

Abstract:
An electric circuit comprising a clock buffer circuit, and a delay circuit for shifting a phase of an external first clock signal passing through said clock buffer circuit, wherein said delay circuit includes:L (L&gE;1) groups of delay-time generation circuits for generating an appropriate phase difference suitable to said electric circuit between L groups of first control signals and L groups of second control signals; M (M&gE;1) groups of first array circuits having K (K&gE;1) number of types of unit-circuits, each type of unit-circuit being connected in series to the other type of unit-circuit in order to move data of each unit-circuit to the next unit-circuit in a first direction, and the unit-circuits of said first array circuits being enabled to start the propagations by the first control signals and being stopped by the second control signals; N (N&gE;1) groups of second array circuits having K (K&gE;1) number of types of unit-circuits, each type of unit-circuit being connected in series to the other type of unit-circuit in order to move data of each unit-circuit to the next unit-circuit in a second direction opposite to said first direction and to output the moved data through an output terminal, and said second array circuits being started when an input signal being supplied; and a data transfer circuit for transferring data from at least a part of the unit-circuit of said first array circuits to the unit-circuits of said second array circuits in order to determine data to be prefeteched in the unit-circuit of said second array circuits before starting the propagations passing through said second array circuits, wherein the number of types of said unit-circuits is one, and each of said unit-circuits operates as an inverter circuit, when said unit-circuits are enabled by the first and second control signals.