Patent ID: 7511997
Filing Date: 2009-03-31
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit; and a read/write circuit for reading data from the memory cell array and writing data into the memory cell array, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, a highest or a lowest level of the N physical quantity levels is defined as a base level, and a first of the cells of the pair cell is set to the base level and a second of the cells of the pair cell is set to a different level than the base level in two memory cells therein, thereby storing M-value data defined by M=2