Patent ID: 6762507
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A semiconductor chip, comprising:a plurality of bonding pads located about periphery of the semiconductor chip, the bonding pads being positioned in at least four rows along each side of the semiconductor chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row, wherein the inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads; a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, wherein each of the signal circuit macros are positioned to align to the corresponding bonding pads; and a electro-static discharge clamping circuit ring being positioned between the signal circuit macros and the inner row of the bonding pads.