Patent ID: 6643173
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a word line; a bit line pair having first and second bit lines and selected by a bit line selection signal; a power supply line; a data holding circuit holding data in first and second nodes; a first transistor with high threshold voltage connected between the first bit line and the first node and driven by a potential on the word line; a second transistor with high threshold voltage connected between the second bit line and the second node and driven by a potential on the word line; a third transistor with low threshold voltage connected between the first bit line and a third node; a fourth transistor with low threshold voltage connected between the second bit line and a fourth node; a fifth transistor with low threshold voltage connected between the third node and the power supply line and driven by data in the second node; a sixth transistor with low threshold voltage connected between the fourth node and the power supply line and driven by data in the first node; a seventh transistor with high threshold voltage connected between the power supply line and a fifth node with a specific potential and becoming turned-on in writing and turned-off in reading out; and a logical circuit making the third and fourth transistors turned-off in writing and the third and fourth transistors turned-on in reading out, based on the potential on the word line and a readout control signal or based on the potential on the word line, the readout control signal and the bit line selection signal.