Patent ID: 6798856
Filing Date: 2004-09-28
Classification: H04L

Abstract:
An automatic clock tuning method of automatically tuning a first phase of a first clock to a transmission latch for sending data to a first data bus in, a transmission side component and a second phase of a second clock to a receiving latch for receiving data from a second data bus in a receive side component, comprising the steps of:adjusting said first phase of said first clock to said transmission latch in said transmission side component; generating a data pattern for checking said first phase of a first clock in said transmission side component; switching a circuit in said transmission side component to send said data pattern through said component to send said data pattern through said transmission latch to said first data bus; adjusting said second phase of said second clock to said receiving latch in said receive side component; verifying, on the basis of said data pattern received by said receive latch from said transmission side component, as to whether or not the data transfer from said transmission side component to said receive side component is accomplished within a predetermined number of clock cycles; and adjusting said first phase of said first clock to said transmission latch and said second phase of said second clock to said receive latch according to a verification result of said data pattern so that the data transfer from said transmission side component to said receive side component is accomplished within said predetermined number of clock cycles.