Patent ID: 6622208
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A soft cache system performing the operations of:comparing tag bits of a virtual address with tag bits programmed in a plurality of register entries, each entry associated with an index to a cache line of programmable cache line size in virtual cache space, the virtual cache space location in memory space programmed by a block address portion of the virtual address and the cache line size programmed by a field in the virtual address; when the tag bits of the virtual address match the tag bits of one of the programmable register entries, selecting the index corresponding to said entry for generating a physical address; and generating the physical address using the selected index as an offset to the cache line and the block address from the virtual memory as an address to the virtual cache space; and when the tag bits of the virtual address do not match the tag bits of one of the register entries: selecting a cache line in the virtual cache space for encaching data associated with the virtual address; retrieving the data associated with the virtual address from a second area of memory using the virtual address; encaching the data retrieved from the second area of memory in the selected cache line in the virtual cache space; and updating the tag bits in the register associated with the selected cache line.