Patent ID: 8823628
Filing Date: 2014-09-02
Classification: G09G

Abstract:
1. A scan driving circuit for supplying a scan signal to a display apparatus comprising a plurality of pixels, the scan driving circuit comprising n stages for generating and outputting scan signals, respectively, wherein: the n stages are configured to sequentially output the scan signals overlapping with each other by h horizontal cycles, respectively, where each of the n stages is driven by a clock signal from among a (h+1)-phase clock signal comprising first to (h+1) h denotes a natural number less than or equal to n−1, and n is a natural number, wherein time periods in which the first clock signal and a start pulse signal are driven comprise: a first time period during which the first clock signal is at a first logic level, and the start pulse signal is maintained at the first logic level for at least h horizontal cycles and then changes to a second logic level; a second time period during which both the first clock signal and the start pulse signal are at the second logic level; a third time period during which the first clock signal is at the first logic level, and the start pulse signal is maintained at the second logic level for at least h horizontal cycles and then changes to the first logic level; a fourth time period during which the first clock signal is at the second logic level, and the start pulse signal is at the first logic level; and a fifth time period during which the start pulse signal is maintained at the first logic level, wherein the second to (h+1) the first logic level corresponds to a voltage for turning off transistors included in the n stages, and the second logic level corresponds to a voltage for turning on the transistors included in the n stages.