Patent ID: 6744288
Filing Date: 2004-06-01
Classification: H03K

Abstract:
A driver comprising:a p-channel MOS transistor having a p+ source connected to a supply voltage, a p+ drain connected to a first node, a gate, and an n-bulk connected to a second node; an n-channel MOS transistor having an n+ source connected to a ground node, an n+ drain connected to the first node, a gate, and a p-bulk connected to a p-bulk voltage; a gate signal generator that outputs a PMOS gate signal to the gate of the p-channel MOS transistor, an NMOS gate signal to the gate of the n-channel MOS transistor, and a control signal, the PMOS and NMOS gate signals being non-overlapping; a first switch connected to the control signal, and the n-bulk of the p-channel MOS transistor via the second node; a second switch connected to the ground node and the control signal; and a resistor that is connected to the n-bulk of the channel MOS transistor, a current flowing through the resistor to the ground node when the second switch is closed, and not flowing when the second switch is open.