Patent ID: 6548877
Filing Date: 2003-04-15
Classification: H01L,Y10S

Abstract:
A MOS field effect transistor comprising:a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; a gate electrode formed on the gate insulation layer; deep source/drain regions formed in upper portions of the semiconductor substrate at respective sides of the gate electrode; source/drain extension regions formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode, the source/drain extension regions being thinner than the deep source/drain regions; a first silicide layer portion having a first thickness, the first silicide layer portion formed on an upper surface of each of the deep source/drain regions; and a second silicide layer portion having a second thickness thinner than the first thickness of the first silicide layer portion, the second silicide layer portion extending from the first silicide layer portion into an upper portion of each of the source/drain extension regions.