Patent ID: 6052811
Filing Date: 2000-04-18
Classification: G01R

Abstract:
An apparatus for testing an integrated circuit, comprising:a plurality of controllable clock drivers each providing a clock signal at an output to an associated circuit block of the integrated circuit, each controllable clock driver also having an input coupled to receive a global clock signal, and a skew enable input, an active signal transmitted on the skew enable input causing the controllable clock driver to delay the clock signal provided at the output, and wherein each controllable clock driver includes a pair of inverters coupled in series between the input and the output, and a delay element coupled to the pair of inverters to delay signal propagation between the input and the output when enabled by the active signal of the skew enable input;a plurality of clocked storage devices each coupled to one of the controllable clock drivers and including a clock input, a data input and a data output; andtest circuitry that operates with a joint test action group (JTAG) compatible protocol coupled to the plurality of clocked storage devices and generating a signal that controls the plurality of controllable clock drivers.