Patent ID: 6801464
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array; a data line array connected to the memory cell array, and comprising 16 bit data lines for 16 bits constituting word data, the 16 bit data lines being arranged such that a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are alternately disposed one line by one line; a read circuit configured to perform selection of the data lines, and charge selected data lines to read data, the read circuit being arranged to select and charge all the 16 bit data lines when reading data in a word data read mode, and to select and charge one of the first and second groups when reading data in a byte data read mode; and a non-selection-side charge circuit configured to select and charge non-selected data lines, which belong to the other of the first and second groups not selected by the read circuit when reading data in the byte data read mode.