Patent ID: 6426261
Filing Date: 2002-07-30
Classification: G06F,H01L,H03K

Abstract:
A fabrication method for fabricating a logic circuit including a first logic gate having at least one first MOS transistor and interposed in a signal path determining an operating speed, said first MOS transistor having a threshold voltage lower than a predetermined voltage and operating at a high speed; andone or plural remaining logic gates other than said first logic circuit having at least one of a second MOS transistor and a third MOS transistor as a transistor having a margin for operating speed, said second MOS transistor having a medium threshold voltage equal to or greater than said predetermined voltage, and said third MOS transistor having a high threshold voltage equal to or greater than said predetermined voltage, said fabrication method comprising the steps of: (A) forming MOS device regions for forming MOS transistors having low, medium and high threshold voltages, said MOS device regions being isolated from each other; (B) implanting impurity for a low threshold into said MOS device regions for forming sai MOS transistors having the low and high threshold voltages; and (C) implanting impurity for a medium threshold into said MOS device regions for forming said MOS transistors having the medium and high threshold voltages.