Patent ID: 7567326
Filing Date: 2009-07-28
Classification: G02F

Abstract:
1. An array substrate for an in-plane switching liquid crystal display device, comprising: a gate line arranged in a transverse direction on a substrate, the gate line including a gate electrode and a gate pad at an end of the gate line, wherein the gate pad is formed of a same material and in a same layer as the gate electrode; a data line arranged in a direction substantially perpendicular to the gate line, the data line including a source electrode; a common line arranged parallel with the gate line, the common line including a plurality of common electrodes substantially parallel with the data line; a common connecting line connecting the plurality of common electrodes, wherein the common connecting line has a stairs shape such that the common connecting line has first, second and third portions each substantially parallel with the gate line, and wherein the plurality of common electrodes have different lengths by the first, second and third portions; a gate insulation layer on the substrate, the gate insulation layer having a gate pad contact hole and covering the gate line, the gate electrode, the common line and the plurality of common electrodes, wherein the gate pad is exposed via the gate pad contact hole in only the gate insulation layer; a semiconductor layer on the gate insulation layer; a plurality of pixel electrodes arranged substantially parallel with the data line; a pixel connecting line substantially parallel with the gate line and connecting the plurality of pixel electrodes to each other, the pixel connecting line overlapping the third portion of the common connecting line; a drain electrode spaced apart from the source electrode, the drain electrode directly contacting the semiconductor layer, wherein the drain electrode has the same layer as the plurality of pixel electrodes; and an alignment layer directly on and contacting the plurality of pixel electrodes, the source and drain electrodes and the gate insulating layer, whereby the alignment layer protects the pixel electrodes, the source and drain electrodes and the gate insulating layer, wherein the alignment layer the source and drain electrodes are simultaneously heat-treated.