Patent ID: 6815773
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A MOS transistor comprising:an SOI substrate having a supporting substrate, an insulating film having a thinner portion and a thicker portion provided on the supporting substrate, and a semiconductor layer having a thinner portion and a thicker portion provided on the insulating film; a channel region formed in the thicker portion of the semiconductor layer; first and second offset regions formed in the thicker portion of the semiconductor layer on opposite sides of the channel region; a drain region formed in the thinner portion of the semiconductor layer in contact with the first offset region on one side of the channel region; a source region formed in the thinner portion of the semiconductor layer in contact with the second offset region on an opposite side of the channel region; a gate insulating film formed on the semiconductor layer over the channel region, the first and second offset regions, and the source and drain regions; a gate electrode formed on the gate insulating film and positioned above the channel region; and an impurity diffusion region formed in the supporting substrate directly below the second offset region.