Patent ID: 9075724
Filing Date: 2015-07-07
Classification: G06F

Abstract:
1. A system capable of concurrently executing a plurality of threads, comprising: a processor capable of concurrently executing a plurality of threads; a memory storing data accessible by each of the plurality of threads, through a memory interface; and an incoherency detection module coupled with the processor and configured to maintain data for each outstanding global write memory transaction, detect a conflict between any of the outstanding global write memory transactions and a new read memory transaction, and responsive to detecting a conflict between a specific outstanding global write memory transaction and the new read memory transaction, to generate barrier data sequenced with respect to the specific global write memory transaction for which the conflict was detected, the barrier data comprising an identifier of the new read memory transaction, and wherein the memory interface is operable to prevent the new read memory transaction from being performed until the sequence of the specific global write memory transaction and the barrier have been processed by the memory interface.