Patent ID: 9093177
Filing Date: 2015-07-28
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of global bit lines; a plurality of sense amplifier circuits, each connected to a corresponding one of the plurality of global hit lines; a plurality of column selection lines, each connected to or disconnected from a corresponding one of the sense amplifier circuits according to column address information; and a plurality of local bit lines including a first local bit line and a second local bit line, the first local bit line being connected to or disconnected from a corresponding one of the global bit lines according to first row address information, the first row address information being different from the column address information, the second local bit line replacing the first local bit line when a defect is present in the first local bit line and being connected to or disconnected from the corresponding one of the global bit lines according to second row address information, the second row address information being different from the column address information.