Patent ID: 7404099
Filing Date: 2008-07-22
Classification: H03L

Abstract:
1. An apparatus, comprising: state logic to receive a signal to indicate that a phase-locked loop is enabled, the state logic to select a first value for a pulse width of at least one phase-frequency detector control signal based on the signal to indicate that the phase-locked loop is enabled, the state logic to select the first value for the pulse width of the phase-frequency detector control signal based on a phase difference between at least a first cycle of a reference clock and a feedback clock, the state logic to receive a frequency lock signal to indicate that the phase-locked loop has acquired frequency lock, the state logic to select a second value for the pulse width based on the frequency lock signal, and the state logic to receive a phase capture signal to indicate that the phase-locked loop has captured phase, the state logic to select a third value for the pulse width based on the phase capture signal.