Patent ID: 6425100
Filing Date: 2002-07-23
Classification: G01R

Abstract:
An electronic circuit comprising:a first test access port including a predetermined set of input and output lines adapted for controlling electronic test of the electronic circuit in accordance with a predetermined set of a plurality of test states; a plurality of testable embedded core circuits, each having a second test access port including said predetermined set of input and output lines adapted for controlling electronic test of said testable embedded core circuit in accordance with said predetermined set of a plurality of test states; a test access port controller connected to said first test access port and having an internal test state dependent upon inputs received from input lines of said predetermined set of input and output lines of said first test access port; and a programmable switch coupled to said first test access port, said second test access port of each of said plurality of testable embedded core circuit and said test access port controller, said programmable switch selectively connecting said first test access port to said second test access port of one of said plurality of testable embedded core circuit for controlling test of said embedded core circuit dependent upon said internal test state of said test access port controller.