Patent ID: 6894916
Filing Date: 2005-05-17
Classification: G11C

Abstract:
1. A non-volatile memory array, comprising: a plurality of memory cells, each of at least a portion of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the memory cell, the non-volatile storage element having a gate terminal, a first drain/source terminal and a second drain/source terminal, the non-volatile storage element comprising a ferroelectric gate field-effect transistor (FeGFET); a plurality of write lines operatively coupled to the gate terminals of corresponding non-volatile storage elements in the memory cells for selectively writing one or more memory cells in the memory array; and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing one or more memory cells in the memory array; wherein the write lines are arranged such that no two memory cells coupled to a same write line share a same word line or a same bit line, and wherein the memory array is configured so as to eliminate a need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell; wherein each of at least a portion of the memory cells is selectively operable in at least a first mode, wherein a logical state of the at least one memory cell is read, and a second mode, wherein the at least one memory cell is written to a predetermined logical state, the second mode comprising: (i) applying a first voltage to the first drain/source terminal of the FeGFET and applying a second voltage to the second drain/source terminal of the FeGFET, the first voltage and the second voltage being substantially equal to one another; and (ii) applying a third voltage to the gate terminal of the FeGFET, the third voltage having a magnitude and polarity which, when summed with the first voltage or the second voltage, results in a voltage potential at least equal to a coercive voltage V