Patent ID: 8706793
Filing Date: 2014-04-22
Classification: G06F

Abstract:
1. A multiplier circuit, comprising: a one-hot circuit having a multi-bit input and a multi-bit output; wherein the one-hot circuit is configured and arranged to output one bit having a logic one value and (2^K)−1 bits having a logic zero value, a position of the logic one bit in the multi-bit output being in response to the multi-bit input to the one-hot circuit, K being an integer greater than one; a multi-bit multiplexing circuit having first and second multi-bit inputs and a multi-bit output, the first input of the multiplexing circuit being coupled to the output of the one-hot circuit and configured to provide data from either the first multi-bit input or the second multi-bit input to the multi-bit output; and a multiply block having first and second multi-bit inputs and a multi-bit output, the first input of the multiply block being coupled to the output of the multiplexing circuit; wherein the first and second multi-bit inputs and the multi-bit output of the multiplexing circuit are each 2^K bits wide, and the first multi-bit input of the multiply block is 2^K bits wide.