Patent ID: 6432772
Filing Date: 2002-08-13
Classification: H01L,Y10S

Abstract:
A method for making a lower storage node of a capacitor on a semiconductor wafer, the method comprising:providing a semiconductor substrate, a surface of the semiconductor substrate comprising an isolation layer; performing a photo-etching-process (PEP) so as to form at least a trench reaching the surface of the semiconductor substrate through the isolation layer; performing a two-step in-situ doping deposition process so as to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer on the isolation layer and on the surface of the trench in sequence, a doping concentration for the second doped amorphous silicon (&agr;-Si) layer being lower than a doping concentration for the first doped amorphous silicon (&agr;-Si) layer; forming a dielectric layer on the surface of the semiconductor substrate, the dielectric layer filling the trench; performing a planarization process so as to remove a portion of the second doped amorphous silicon (&agr;-Si) layer, the first doped amorphous silicon (&agr;-Si) layer and the dielectric layer on the surface of the isolation layer; removing the dielectric layer and the isolation layer; and performing a hemi-spherical grain (HSG) process so as to form a rough surface having a plurality of hemi-spherical grains on the surface of the second doped amorphous silicon (&agr;-Si) layer inside the trench; wherein no hemi-spherical grains are formed on the surface of the first doped amorphous silicon layer to shrink the spacing with other devices.