Patent ID: 7761688
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A multi-thread processor for processing a plurality of threads comprising: operative stages including a Fetch Address Stage, a Program Access Stage, a Decode Stage, a First Execution Stage, a Second Execution Stage, and a Memory Access Stage; a Thread ID generator producing a thread identifier which alternates between a first and second value on successive even and odd clock cycles; a plurality of register sets, one said register set associated with each said thread value, each said register set comprising a plurality of registers; an n-way register set controller coupled to said plurality of register sets and simultaneously handling multiple read or write requests associated with one or more of said thread values; said Fetch Address Stage generating a Program Memory Address associated with said first thread identifier during said even clock cycles and said second thread identifier during said odd clock cycles; said Program Access Stage for receiving Program Memory Data associated with said Program Memory Addresses and forwarding said Program Memory Data and said Program Memory Addresses associated with a second thread during said even clock cycles and said Program Memory Data and said Program Memory Addresses associated with said first thread identifier during said odd clock cycles; said Decode Stage converting said Program Memory Data into instructions, said Decode Stage coupled to said n-way register set controller, said instructions associated with said first thread identifier forwarded during said even clock cycles and said instructions associated with said second thread identifier during said odd clock cycles; said First Execution Stage for handling a multiply class of instruction received from said Decode Stage and generating a multiply result associated with a second thread identifier during said even clock cycles and a multiply result associated with said first thread identifier during said odd clock cycles; said Second Execution Stage for handling an Arithmetic Logical Unit class of instructions received from said Decode Stage, said Second Execution Stage also coupled to said n-way register set controller, said Second Execution Stage generating a result associated with said first thread identifier during said even clock cycles and a result associated with said second thread identifier during said odd clock cycles; said Memory Access Stage for handling reading and writing of external memory, said Memory Access Stage optionally reading or writing data associated with said second thread identifier during said even clock cycles and data associated with said first thread identifier during said odd clock cycles; a Write Back Stage coupled to said n-way register set controller for writing data to said register set; said n-way register controller allowing simultaneous access to said plurality of register sets by at least two of said Decode Stage, said First Execution Stage, and said Write Back Stage; where: such that said result for each stage associated with a first thread are delivered to a subsequent stage operative on said first thread in a subsequent cycle, and results for each stage associated with a second thread are delivered to a subsequent stage operative on said second thread on a subsequent cycle.