Patent ID: 7929339
Filing Date: 2011-04-19
Classification: G11C

Abstract:
1. A phase change memory device comprising: a plurality of word lines arranged in a row direction; a plurality of bit lines arranged in a column direction; a reference bit line arranged in the column direction; a cell array block comprising a plurality of phase change resistance cells formed at the intersection of one of the word lines and one of the bit lines, wherein the cell array block is configured to output a data current; a reference cell array block comprising a plurality of reference cells each of which is formed at the intersection of one of the word lines and the reference bit line, wherein the reference cell array block is configured to output a reference current; a clamp voltage generating unit configured to output a clamp voltage in response to a clamp enable signal; a reference voltage generating unit connected to the reference bit line and receiving the clamp voltage, wherein the reference voltage generating unit is configured to generate a reference voltage corresponding to the reference current in response to the clamp voltage; and a sense amplifier connected to the bit lines to receive the data current and performing amplification in response to the clamp voltage and the reference voltage.