Patent ID: 6898137
Filing Date: 2005-05-24
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of normal memory cells arranged in a matrix; a plurality of first bit lines arranged in correspondence with a column of said normal memory cells, each pair of bit lines being connected to the normal memory-cells in a corresponding column; a plurality of second bit lines respectively complementary to said plurality of first bit lines and arranged in correspondence with a column of said normal memory cells; a plurality of normal word lines arranged in correspondence with a row of said normal memory cells, each normal word line being connected to the normal memory cell in a corresponding row; a reference voltage generating circuit providing equal amounts of charge to and receiving equal amounts of charge from said plurality of first bit lines and said plurality of second bit lines, respectively, to generate a reference voltage, before any one normal word line, of said plurality of normal word lines, is selected; and a sense amplifier differentially amplifying potential difference between said first bit line and second bit line, based on the reference voltage.