Patent ID: 6795049
Filing Date: 2004-09-21
Classification: G09G

Abstract:
An electric circuit comprising:a plurality of wires provided in an image pick-up region of a substrate; a plurality of image pick-up elements respectively connected to the plurality of wires; a dummy wire provided in a dummy element region of the substrate; a dummy element connected to the dummy wire so that a parasitic capacitance at a respective one of the plurality of wires is equal to that at the dummy wire; anc a shift register connected to the plurality of wires provided in the image pick-up element region and the dummy wire provided in the dummy element region, at least one stage of the shift register including: a first transistor having a first control terminal, the first transistor being turned ON by a predetermined level signal supplied to the first control terminal from a frontal stage, and outputting the predetermined level signal or a constant voltage signal from a first end of a first current path of the first transistor; a second transistor having a second control terminal, the first transistor being turned ON according to a voltage applied to a wire between the second control terminal and second end of the first current path of the first transistor, and outputting an output signal from a first end of a second current path of the second transistor while a first or second signal supplied to a second end of the second current path of the second transistor is externally defined as the output signal; a load that outputs a power voltage to be externally supplied; a third transistor having a third control terminal, the third transistor being turned ON according to a voltage applied to a wire between the third control terminal and the second end of the first current path of the first transistor, and resetting the power voltage output from the load to a first end of a third current path of the third transistor, the power voltage from the load being displaced with a predetermined level voltage from the second end of the third current path of the third transistor; and a fourth transistor having a fourth control terminal, the fourth transistor being turned ON according to a voltage applied to a wire between the fourth control terminal and the load, a first of a fourth current path of the fourth transistor being connected to the first end of the second current path of the second transistor, and outputting a reference voltage from the first end of the fourth current path via a second end of the fourth current path.