Patent ID: 8927364
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, the method comprising the steps of: providing a bulk substrate layer; forming shallow trench isolation regions in a substrate to isolate active regions for forming a first FET region and a second FET region; forming a hard mask over said second FET region; recessing the bulk substrate layer in said first FET region; depositing a layer of silicon germanium (SiGe) in the recess of said first FET region; depositing a layer of silicon on top of said SiGe layer in the recess of said first FET region; forming a first gate dielectric layer on said first FET region and a first gate conductor formed atop of said first gate dielectric layer on said first FET region to form a first gate electrode structure; recessing the shallow trench isolation regions surrounding first FET region to the bottom of the layer of SiGe in the recess of the first FET region; removing the layer of SiGe in the recess of the first FET region, which creates a first air gap; filling said first air gap with an insulator layer comprising either stressed oxide or stressed nitride, wherein the insulator layer is either tensile stressed or compressive stressed; filling said recessed shallow trench isolation regions surrounding said first FET region with an oxide, such that an enhanced strain is applied to the first FET region; removing the hard mask from the second FET region; forming a second hard mask or a soft mask over the first FET region, wherein the first FET region includes the formed gate electrode structure and the gate conductor; recessing the bulk substrate layer in said second FET region; depositing a SiGe layer in the recess of the second FET region and depositing a silicon layer on top of said SiGe layer in the recess of the second FET region; forming a second gate dielectric layer on said second FET region and a second gate conductor formed atop of said second gate dielectric layer on the second FET device to form a second gate electrode structure; recessing said shallow trench isolation regions surrounding said second FET region to the bottom of the layer of SiGe in the recess of the second FET region; removing said layer of SiGe in the recess of the second FET region, which creates a second air gap; filling the recessed shallow trench isolation regions surrounding said second FET region with an oxide, such that an enhanced strain is applied to the second FET region; and removing the hard mask layer from the first FET region.