Patent ID: 8952441
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of the semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate; first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively; and first to n-th select transistors connected in series to the first to n-th memory cells respectively, wherein the first to n-th memory cells comprise a first gate structure including a first insulating layer, a floating gate electrode with a first conductive layer, a second insulating layer, and a control gate electrode with a second conductive layer, in order thereof from the surfaces of the first to n-th semiconductor layers in the third direction, the first to n-th select transistors comprise a second gate structure including the first insulating layer, and a select gate electrode with the first conductive layer, in order thereof from the surfaces of the first to n-th semiconductor layers in the third direction, the first conductive layers of the floating gate electrodes of the first to n-th memory cells are independent of one another, the second conductive layers of the control gate electrodes of the first to n-th memory cells are connected to one another in the first direction, and the first conductive layers of the select gate electrodes of the first to n-th select transistors are connected to one another in the first direction.