Patent ID: 6556042
Filing Date: 2003-04-29
Classification: H03K

Abstract:
A configurable logic block (CLB) in a Field Programmable Gate Array (FPGA), the FPGA comprising a general interconnect structure and a plurality of the CLBs, the CLB comprising:a function generator having a plurality of data input terminals; first and second bypass input multiplexers each having a plurality of input terminals coupled to the general interconnect structure and each further having an output terminal coupled to bypass the function generator data input terminals; and a first data input multiplexer coupled between the general interconnect structure and a first one of the data input terminals of the function generator, the first data input multiplexer comprising: a plurality of data input terminals coupled to the general interconnect structure; a decoder circuit having a plurality of input terminals coupled to the output terminals of the first and second bypass multiplexers and further having a plurality of output terminals; and a second stage multiplexer having a plurality of select terminals coupled to the output terminals of the decoder circuit, a plurality of data input terminals coupled to the data input terminals of the first data input multiplexer, and an output terminal coupled to a first one of the data input terminals of the function generator.