Patent ID: 6990597
Filing Date: 2006-01-24
Classification: G06F,H03K,H03L,H04L

Abstract:
1. A clock generation circuit comprising: first to Nth inversion circuits in which an output of each previous-stage Kth (1≦K≦N−1) inversion circuit is connected to an input of the corresponding next-stage (K+1)th inversion circuit and an output of the Nth inversion circuit is connected by a feedback line to an input of the first inversion circuit; and first to Nth buffer circuits having inputs connected to outputs of the first to Nth inversion circuits, wherein the first to Nth inversion circuits are disposed along a first line that is parallel to the feedback line; wherein the first to Nth buffer circuits are disposed along a second line that is parallel to the feedback line but different from the first line; and wherein the feedback line is disposed in a region between a region in which the first to Nth inversion circuits are disposed and a region in which the first to Nth buffer circuits are disposed.