Patent ID: 7706172
Filing Date: 2010-04-27
Classification: H01L

Abstract:
1. A SRAM memory cell comprising two inverters and a plurality of switches, the SRAM cell being manufactured in a technology offering N/P shunt capabilities, the inputs of the inverters being connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of said switches, said switches being controlled by a signal word line (WLa, WLb), each inverter comprising a first transistor (MN 0 , MN 1 ) of a first conductivity type and a second transistor (MP 0 , MP 1 ) of a second conductivity type, and each switch comprising at least a third transistor (MN 4 , MN 5 ) of the first conductivity type, characterized in that the two transistors (MP 0 , MP 1 ) of the second conductivity type in the inverters are arranged in two opposite end regions of the memory cell, respectively.