Patent ID: 6076147
Filing Date: 2000-06-13
Classification: G06F

Abstract:
In a processor system having a plurality of processors, a non-inclusive cache system, comprising:an external cache;a plurality of on-chip caches each having a set of tags associated therewith, each of said plurality of processors having associated therewith at least one of said plurality of on-chip caches, and at least one of the on-chip caches including data which is absent from said external cache;a pipelined snoop bus, ported to the set of tags of each of said plurality of on-chip caches, which transmits snoop addresses to said plurality of on-chip caches; anda system interface unit which in response to a received snoop request scans said external cache for an address matching a snoop address of the received snoop request, and applies the snoop address of the received snoop request to said pipelined snoop bus for transmission to said plurality of on-chip caches.