Patent ID: 7428678
Filing Date: 2008-09-23
Classification: G01R

Abstract:
1. An integrated circuit capable of operating in a normal mode and a test mode, the integrated circuit being configured for normal operation when in the normal mode and for scan test in the test mode, the integrated comprising: a serial link interface configured to allow the integrated circuit to communicate over a serial bus, the serial link interface being employed to send and receive serial data in the normal mode and in the test mode; a scan chain configured for scan testing, the scan chain having a serial input node for serially accepting input scan data, a serial output node for serially outputting output scan data, and parallel connections to a core logic circuit of the integrated circuit; a scan control circuit configured to serially shift the input scan data to the input node of the scan chain and to serially shift out the output scan data from the serial output node of the scan chain; and a data router configured to route the input scan data from the serial link interface to the scan control circuit in the test mode, the data router being configured to transfer data between the serial link interface and the core logic circuit without going through the scan chain in the normal mode.