Patent ID: 7348228
Filing Date: 2008-03-25
Classification: H01L

Abstract:
1. A method of forming a junction field effect transistor (JFET), comprising: forming a first buried layer of a first electrical conductivity type in a semiconductor substrate; forming a second buried layer of a second electrical conductivity type over the first buried layer; forming an epitaxial layer over the surface of the substrate, were forming the epitaxial layer causes the first buried layer and the second buried layer to migrate up toward the surface of the epitaxial layer, where the second buried layer gets closer to the surface of the epitaxial layer than the first buried layer; forming first well regions having the first electrical conductivity type in the epitaxial layer; forming second well regions having the second electrical conductivity type in the epitaxial layer, the second well regions being formed adjacent to the first well regions; driving at least some of the first well regions down to at least the second buried layer; driving the second well regions down to the second buried layer; forming a gate region in a first well region that is situated over the second buried layer; forming a source region in a second well region adjacent to the first well region wherein the gate region is formed; and forming a drain region in a second well region adjacent to the first well region wherein the gate region is formed, where the first well region wherein the gate region is formed acts as a plug to force current that flows between the source and drain regions to flow in the second well region wherein the source region is formed, the second well region wherein the drain region is formed and the second buried layer, where the second buried layer thereby serves as a channel region.