Patent ID: 6797615
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, by which methoda first wiring layer with conductor tracks is formed on a surface of a semiconductor body, wherein a number of the conductor tracks have a width w and a number of the conductor tracks have a width greater than w, wherein plates are formed in the first wiring layer provided on the surface between neighboring conductor tracks that are separated through a space having a width larger than w, said plates being formed by a number of mutually parallel strips having a width w, after which a first insulating layer is formed on and between the conductor tracks of the first wiring layer by means of a process in which the thickness of the insulating layerformed is dependent on the width of the subjacent conductor tracks, whereupon a capping layer is deposited on the first insulating layer and said capping layer is planarized by means of a polishing treatment, characterized in that the conductor tracks of the first wiring layer having a width greater than w are formed by a number of mutually parallel strips having a width w, which strips are locally interconnected.