Patent ID: 7034386
Filing Date: 2006-04-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a wiring layer including a first wiring, and said wiring layer having a first surface and a second surface opposing to said first surface, and said wiring layer having a solder resist layer provided on an exposed portion on said second surface; an IC chip having an electrode on a front surface and mounted on said first surface to be electrically connected to said first wiring via said electrode by flip-chip bonding; a conductive post provided on said first surface to be electrically connected to said first wiring; insulating resin filling a space between said IC chip and said conductive post to form an upper surface opposite to said first surface and to expose a rear surface of said IC chip and an end surface of said conductive post; wherein: said rear surface and said end surface and said upper surface form a substantially flat and continuous surface.