Patent ID: 8861247
Filing Date: 2014-10-14
Classification: G11C,H01L

Abstract:
1. A method for biasing a direct injection semiconductor memory device comprising the steps of: applying a first voltage potential to a first N-doped region of the device via a bit line; applying a second voltage potential to a second N-doped region of the device via a source line; applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region of the device that is electrically floating and disposed between the first N-doped region and the second N-doped region, wherein the first N-doped region, the body region, and the second N-doped region form a bipolar transistor; and applying a fourth voltage potential to a P-type substrate of the device via a carrier injection line, wherein the second N-doped region is formed directly on the P-type substrate.