Patent ID: 7599462
Filing Date: 2009-10-06
Classification: H03L

Abstract:
1. A circuit for providing a low-jitter clock output synchronized to a timing reference having jitter, said circuit comprising: a numerically-controlled analog oscillator for providing said clock output and having an input for receiving a rational numeric representation of a ratio between a frequency of said clock output and a frequency of a stable clock for controlling said frequency of said clock output; a counter for dividing a frequency of one of said clock output or said stable clock; a digital phase-frequency detector for generating a representation of an on-going phase-frequency difference between said timing reference and an output of said counter; a digital loop filter for filtering said representation of said on-going phase-frequency difference to provide said rational numeric representation to said numerically-controlled analog oscillator; and a control circuit having a synchronization input for receiving a synchronization event signal, wherein said control circuit has an output coupled to said digital phase-frequency detector for resetting an accumulated phase error of said digital phase-frequency detector in response to said synchronization event signal.