Patent ID: 6716694
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device including a memory region including a non-volatile memory transistor with a split gate structure, and a capacitor region including a capacitor, the method for manufacturing a semiconductor device comprising the steps of:(a) forming, in the memory region, a gate insulation layer, a floating gate, and a selective oxide insulation layer on a semiconductor substrate, which comprise a portion of the non-volatile memory transistor; (b) forming, in the capacitor region, a lower electrode that comprises a portion of the capacitor on an insulation layer formed on the semiconductor substrate; (c) successively depositing in layers a first silicon oxide layer and a protection layer, and then removing, in the capacitor region, the first silicon oxide layer and the protection layer deposited over the lower electrode; (d) forming, in the capacitor region, an insulation layer by thermally oxidizing an upper surface section of the lower electrode; (e) depositing a silicon nitride layer, and then removing the protection layer and the silicon nitride layer in the memory region, and patterning the silicon nitride layer in the capacitor region; (f) forming an intermediate insulation layer and a control gate that comprise a portion of the non-volatile memory transistor, and forming a dielectric layer and an upper electrode that comprise a portion of the capacitor, wherein the control gate and upper electrode are formed by forming and then patterning a conduction layer, wherein the intermediate insulation layer is formed by patterning the first silicon oxide layer, and wherein the dielectric layer is formed between the upper electrode and the lower electrode; and (g) forming an impurity diffusion layer by introducing an impurity in a specified region in the semiconductor substrate.