Patent ID: 8427214
Filing Date: 2013-04-23
Classification: H03K

Abstract:
1. A master-slave flip-flop circuit for receiving an input signal and for generating an output signal, said master-slave flip-flop circuit being controlled by a clock signal having a first phase and a second phase, having a normal mode of operation and a retention mode of operation and comprising: a master stage configured to receive during said normal mode said input signal during said first phase of said clock signal and to store at a master node during said second phase of said clock signal a master signal with a value dependent upon said input signal; control circuitry coupled to said master node and to a slave node and configured to isolate said slave node from said master node during said first phase of said clock signal and to drive said slave node during said second phase of said clock signal to have a slave signal with a value dependent upon said master signal, said output signal having a value dependent upon said slave signal; a slave stage configured to receive during said normal mode said slave signal during said second phase of said clock signal and to store said slave signal at said slave node during said first phase of said clock signal; and retention circuitry coupled to said slave stage and configured to maintain said output signal during said retention mode, wherein said retention circuitry is configured such that: (i) during said retention mode and said first phase of said clock signal, said retention circuitry drives said slave node so as to maintain said output signal via a first path; and (ii) during said retention mode and said second phase of said clock signal, said retention circuitry drives said slave node so as to maintain said output signal via a second path passing through said master node and said control circuitry that drives said slave node during said normal mode, said second path being different from said first path.