Patent ID: 6385697
Filing Date: 2002-05-07
Classification: G06F

Abstract:
A cache system for decreasing the number of access of a data processing unit to external memory comprising:full-set associative cash memory capable of preserving cache lines of high cache hit rates, in which when a first tag extracted from input address data matched one of first tags which have been stored in valid cache lines of the full-set associative cash memory, data which has been stored in a valid cache line corresponding to the matched first tag is read by the data processing unit as cache data; non-full-set associative cash memory which is provided to the cache system so as to be coupled with the full-set associative cash memory and to execute tag comparison for the judgment on the cache hit simultaneously with the full-set associative cash memory, in which when a second tag extracted from the input address data matched a second tag which has been stored in a valid cache line of the non-full-set associative cash memory corresponding to an index extracted from the input address data, data which has been stored in the valid cache line corresponding to the matched second tag is read by the data processing unit as cache data; cache hit count storage means each of which is provided corresponding to each of the cache lines of the full-set associative cash memory for storing a cache hit count value concerning the number of cache hits which occurred to the cache line; and a cache hit count management means for counting the number of cache hits in each cache line of the full-set associative cash memory and thereby managing and updating the cache hit count values which are stored in the cache hit count storage means, wherein: if miss hits occurred to both the full-set associative cash memory and the non-full-set associative cash memory when the non-full-set associative cash memory has no invalid cache line corresponding to the index and the full-set associative cash memory has one or more invalid cache lines, data which has been stored in a valid cache line of the non-full-set associative cash memory corresponding to the index to which the miss hit occurred is transferred to one of the invalid cache lines of the full-set associative cash memory, and data fetched from the external memory due to the miss hits is written into the cache line of the non-full-set associative cash memory from which data has been transferred to the full-set associative cash memory, if miss hits occurred to both the full-set associative cash memory and the non-full-set associative cash memory when the non-full-set associative cash memory has no invalid cache line corresponding to the index and the full-set associative cash memory is full of valid cache lines, data which has been stored in a valid cache line of the non-full-set associative cash memory corresponding to the index to which the miss hit occurred is transferred to one of valid cache lines of the full-set associative cash memory having the smallest cache hit count value, and data fetched from the external memory due to the miss hits is written into the cache line of the non-full-set associative cash memory from which data has been transferred to the full-set associative cash memory, and if miss hits occurred to both the full-set associative cash memory and the non-full-set associative cash memory when the non-full-set associative cash memory has an invalid cache line corresponding to the index, data fetched from the external memory due to the miss hits is written into an invalid cache line of the non-full-set associative cash memory corresponding to the index.