Patent ID: 7296259
Filing Date: 2007-11-13
Classification: G06F

Abstract:
1. A method of implementing a software breakpoint in a processor system having at least one processor coupled to a main memory, and an instruction cache associated with the processor, a breakpoint code being insertable at a particular location in the instruction cache, the method comprising the steps of: setting a control indicator associated with the particular location to a first state which allows the breakpoint code to be returned to the processor from the instruction cache in response to a first fetch request directed to a corresponding address of the particular location; subsequently setting the control indicator associated with the particular location to a second state which directs that a second fetch request to the corresponding address of the particular location be serviced from the main memory; changing the control indicator state back to the first state after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address of the particular location will be serviced from the main memory; and utilizing the breakpoint code to debug software instructions running on the processor system.