Patent ID: 9105347
Filing Date: 2015-08-11
Classification: G09G,G11C

Abstract:
1. A shift register, comprising: a signal input unit configured for receiving an input signal and providing the input signal on an output terminal of the signal input unit; a signal output unit configured for receiving a clock signal and controlling whether outputting the received clock signal on an output terminal of the signal output unit according to the input signal provided by the signal input unit; and a plurality of stable modules, each of the stable modules including a pull-down control circuit and a pull-down circuit; each of the stable modules electrically coupled to the output terminal of the signal input unit, the output terminal of the signal output unit, and a default potential; each of the stable modules receiving a corresponding operation signal and enabled in a duty of the corresponding operation signal, such that both the output terminals of the signal input unit and the signal output unit are electrically coupled to the default potential when the input signal is disabled; wherein before one of the stable modules is disabled, another of the stable modules has already been enabled, a Mth raising edge of the Nth operation signal is earlier than a Mth falling edge of the (N−1)th operation signal, and a Mth falling edge of the Nth operation signal is later than a (M+1)th rising edge of the (N−1)th operation signal, M and N are integers.