Patent ID: 6223208
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A computer processor functionally connected to an operating system, comprising(a) at least one register set having a plurality of registers to store a state of at least one thread;(b) at least one memory unit to store data and instructions associated with at least one of said threads;(c) at least one register/storage unit connected to one of said register sets and to at least one of said memory units to transfer the state of one of said threads between one of said memory units and one of said register sets when one of said register/storage units is not otherwise explicitly assigned to transfer data between one of said register sets and one of said memory units;(d) an instruction control register functionally connected to each of said register/storage units and functionally connected to one of said memories, said instruction control register to transfer instructions to each of said register/storage units in which at least one of said instructions to be transferred to one of said register/storage units need not be executed in a next clock cycle of said processor, and so is marked as being an idle instruction; and(d) a context switch unit functionally connected to each of said register/storage units to transfer a context switch instruction to one of said register/storage units wherein said context switch unit comprises(i) at least one thread status register;(ii) at least one counter; and(iii) at least one address registerwherein a status of a first thread to be switched is stored in one of said thread status registers, and an address of said first thread is located in said address register and the size of said first thread is indicated by said at least one counter, andsaid context switch register receives a signal indicating said instruction control register received said idle instruction and in response thereto said context switch register transfers said context switch instruction to one of said register/storage units and in response to said context switch instruction, one of said register/storage units transfers said state of said first thread between one of said memory units and one of said register sets.