Patent ID: 6708268
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A microcontroller comprising:a central processing unit; a data memory having a linearized address space coupled with said central processing unit being divided into n banks; said central processing unit comprising: a bank select unit which either accesses one of said banks or accesses a virtual bank, whereby said virtual bank combines partial memory space of two banks of said data memory and wherein said selected bank forms a register file; an arithmetic logic unit coupled with said register file; a plurality of special function registers being mapped to one of said banks in said data memory, wherein one of said special function registers is a working register being coupled with said arithmetic logic unit; a program counter register within said central processing unit, said program counter mapped in said data memory; and a working register within said central processing unit being coupled with said arithmetic logic unit, said working register mapped in said data memory; wherein said microcontroller having an instruction set for controlling said arithmetic logic unit and wherein at least one instruction comprises a bit indicating whether said bank select unit accesses one of said banks or said virtual bank.