Patent ID: 8648399
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. An integrated circuit comprising: a semiconductor portion having a substantially planar upper surface, the semiconductor portion comprising: an N-type layer; a lightly doped layer disposed over the N-type layer; a P-type region extending into the lightly doped layer from the upper surface; and a plurality of N-type regions extending from the upper surface and into the P-type region, wherein each of the N-type regions has a peripheral boundary at the upper surface, wherein said each N-type region forms a central hole such that the P-type region extends up to the upper surface through the hole in said each N-type region, wherein the central hole is the only hole in said each N-type region, and wherein the N-type regions are disposed in an array; a first metal electrode that extends over at least a central portion of each of the N-type regions and also extends over the central hole in said each N-type region thereby making contact with the P-type region at the upper surface of the semiconductor portion in said central hole and thereby also making contact with said each N-type region at the upper surface of the semiconductor portion; a second metal electrode that surrounds the peripheral boundary of each of the N-type regions, wherein the second metal electrode contacts the P-type region around the peripheral boundary of each of the N-type regions; and a third metal electrode that is disposed on an opposite side of the lightly doped layer from the first and second metal electrodes.