Patent ID: 6395596
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A method of fabricating a metal oxide semiconductor (MOS) transistor in an embedded memory, the method comprising:providing a semiconductor wafer with a defined memory array area and a periphery circuits area on the surface of a silicon substrate on the semiconductor wafer; forming a first dielectric layer, an undoped polysilicon layer, and a second dielectric layer on the surface of the semiconductor wafer, respectively; performing a first ion implantation process on the undoped polysilicon layer in the memory array area to transform the undoped polysilicon layer in the memory array are to a doped polysilicon layer; performing an etching process to completely remove the second dielectric layer in the memory array area; forming a silicide layer, a protective layer, and a first photoresist layer, respectively, on the surface of the semiconductor wafer; performing a first PEP to define a plurality of gate patterns in the first photoresist layer in the memory array area; etching the protective layer, the silicide layer, and the doped polysilicon layer in the memory array area down to the surface of the first dielectric layer using the patterns of the first photoresist layer as a hard mask, and etching in-situ the protective layer and the silicide layer in the periphery circuits area down to the surface of the second dielectric layer; performing a second ion implantation process to form lightly doped drains (LDD) of each MOS transistor in the memory array area; removing the first photoresist layer and the second dielectric layer in the periphery circuits area; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second PEP to define a plurality of gate patterns in the second photoresist layer in the periphery circuits area; etching the undoped polysilicon layer in the periphery circuits area down to the surface of the first dielectric layer using the second photoresist layer as a hard mask, to form a gate in each MOS transistor in the periphery circuits area; performing a third ion implantation process to form LDDs in each MOS transistor in the periphery circuits area; removing the second photoresist layer; forming both a silicon nitride layer and a compensated silicon oxide layer on the surface of the semiconductor wafer, respectively, and covering the surface of each gate; removing portions of both the silicon nitride layer and the compensated silicon oxide layer in the periphery circuits area using an etching process, to form a spacer on either side of each gate in the periphery circuits area; and performing a fourth ion implantation process to form a source and drain in each MOS transistor in the periphery circuits area, and simultaneously doping the undoped polysilicon layer in each gate in the MOS transistor in the periphery circuits area.