Patent ID: 6133600
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A memory device, comprising:a plurality of storage cells coupled to form an array, each cell including:an access transistor with a gate coupled to a word line and a first terminal coupled to a bit line; anda capacitor coupled to a second terminal of the access transistor, wherein the capacitor includes a cell plate separated from a first plate by a dielectric layer, the first plate comprising a trunk extending outwardly from the terminal, a dome formed outwardly from the trunk that has a surface area that is greater than a planar projection of the layer on a surface of the substrate and a plurality of fins extending in layers from the trunk, wherein the plurality of fins include dome-shaped outgrowths on the end of the fins opposite the trunk;row addressing circuitry coupled to row lines for selecting a row for a storage cell; andcolumn addressing circuitry coupled to column lines for selecting a column for the selected storage cell.