Patent ID: 7240082
Filing Date: 2007-07-03
Classification: G06F

Abstract:
1. A method for improving processing efficiency of pipeline architecture with a processor, the processor having: a first functional unit for executing a calculation task; a second functional unit for executing another calculation task; and a control unit electrically connected to the first and the second functional units for generating a plurality of control signals to control the first and the second functional units; the method comprising: (a) executing a first calculation task with the first functional unit or the second functional unit; (b) determining an executing time period of a second calculation task with the control unit according to the functional unit executing the first calculation task, an executing time period of the first calculation task, and whether the second calculation task depends upon a result of the first calculation task; and (c) executing the second calculation task with the first functional unit according to the executing time period of the second calculation task determined in step (b); wherein when a calculation task executed by the second functional unit requires more instruction cycles than that of the first functional unit, the control signals control the first and the second functional units to execute the first calculation task within a first time period and a second time period, and to execute the second calculation task within the second time period and a third time period sequentially, the method further comprises: