Patent ID: 8929149
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell block including a plurality of memory cells; a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells; a fail bit counter configured to generate a fail count by counting the number of memory cells not erased in an erase operation among the memory cells; and a controller configured to control the peripheral circuit section to perform a first erase voltage applying operation using a first erase voltage obtained by increasing the erase voltage when the fail count generated by the fail bit counter is smaller than a previous fail count as a result of comparing the fail count with the previous fail count, and perform a second erase voltage applying operation using a second erase voltage obtained by decreasing the erase voltage and a new erase verification operation when the fail count is greater than or equal to the previous fail count. wherein the controller re-performs the second erase voltage applying operation by using a new second erase voltage obtained by decreasing the second erase voltage when it is determined that the new erase verification operation is failed.