Patent ID: 7995622
Filing Date: 2011-08-09
Classification: G06F

Abstract:
1. A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining said FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting said FIFO depth B into a programmable Look Up Table (LUT); (D) obtaining a phase detector error signal; (E) scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of: {a ratio of an input symbol rate to a reference clock; and a damping factor configured to compensate for latency of a frequency lock loop (FLL)}; (F) adding said scaled error factor to a nominal phase step to obtain a phase update; (F1) computing said nominal phase step by using a nominal symbol rate, a modulation index, and a reference frequency; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from said FIFO under control of an output FIFO address control register at said smoothed symbol rate.