Patent ID: 6618462
Filing Date: 2003-09-09
Classification: G06F

Abstract:
A system for dividing clock frequencies, comprising:a reference clock configured to generate a reference clock signal having a reference clock frequency; a multi-phase clock generator configured to generate a finite number of clock signals from the reference clock signal, wherein each of the finite number of clock signals has the same frequency, wherein each of the finite number of clock signals is offset from each of the other finite number of clock signals by a phase offset, wherein the phase offset between adjacent clocks within the finite number of clocks is the same; a real number divisor comprising an integer portion and a decimal portion, wherein the decimal portion comprises a remainder portion having a finite degree of precision and an error portion, wherein the finite degree of precision of the remainder portion is proportional to the finite number of clock signals; an error accumulator configured to accumulate an error term, wherein the accumulated error represents a part of the real number that is not reflected in the finite number of clock signals; and a glitch-free multiplexer configured to receive the finite number of clock signals, wherein the glitch-free multiplexer is further configured to receive a clock select signal, wherein the glitch-free multiplexer is further configured to select a clock signal from the finite number of clock signals in response to the received clock select signal, wherein the glitch-free multiplexer is further configured to output the selected clock signal, wherein the clock select signal is a function of the integer portion of the real number, wherein the clock select signal is further a function of the remainder portion of the real number, wherein the clock select signal is further a function of the accumulated error.