Patent ID: 6763504
Filing Date: 2004-07-13
Classification: G06F

Abstract:
A method for reducing the size of RC parasitics in an interconnect network of an integrated circuit (IC), the IC being formed as a collection of transistors, each having its terminals interconnected by nets, each of the nets being modeled by nodes and elements, the elements being modeled as resistors (R) and capacitors (C), the nodes being attached to transistor terminals are labeled as boundary nodes while the remaining nodes are labeled as internal nodes, the method comprising the steps of:a) selecting a net from the collection of nets; b) reducing the size of the interconnect network of the selected net by eliminating the internal nodes having a time-constant below a predetermined threshold and a fill-in count contained within a pre-specified limit, c) iteratively shorting a resistor connected to a boundary node, wherein the accumulated delay error at the boundary node after shorting is less than a fraction of the predetermined threshold; d) updating the values of the resistors adjoining the shorted resistor, wherein no additional delay error is generated in the remaining nodes due to shorting the resistor; and repeating steps c) and d) until no boundary nodes are found in the selected interconnect network with the accumulated delay errors meeting the predetermined threshold.