Patent ID: 7782691
Filing Date: 2010-08-24
Classification: G11C

Abstract:
1. A static random access memory with write-through capability, comprising: a. a memory cell configured to store a bit of data; b. an enable signal configured to enable writing a value from an input into the memory cell and to enable reading a value from the memory cell onto a dot line; c. a write-through circuit configured to allow a value being written into the memory cell to be read at the dot line in a single clock cycle; d. a precharge circuit configured to precharge the dot line to a predetermined value when the dot line is not being accessed; and e. a logic device configured to recharge the dot line when a current state of the memory cell and a current value of the input causes the dot line to discharge prematurely and when the current state of the input corresponds to a state in which the dot line should be charged.