Patent ID: 6486934
Filing Date: 2002-11-26
Classification: G02F

Abstract:
In a method for manufacturing a fringe field switching mode liquid crystal display device including a pixel electrode and a counter electrode formed on a rear substrate to generate a fringe field in a liquid crystal cell; a thin film transistor consisting of a gate electrode, a source electrode, a drain electrode and a channel, and applying a picture signal between the pixel electrode and the counter electrode; and a gate pad formed at the edge of the rear substrate, a method for manufacturing a fringe field switching mode liquid crystal display device, comprising the steps of:sequentially stacking a transparent conductive layer for a counter electrode and an opaque metal layer for a gate bus line on the surface of the rear substrate; forming a gate bus line connected to the gate electrode, a counter electrode region for forming the counter electrode, and a gate pad region for forming the gate pad, by pattering the transparent conductive layer for the counter electrode and the opaque metal layer for the gate bus line in an identical shape; sequentially stacking a gate insulating layer, an amorphous silicon layer and a doped amorphous silicon layer on the rear substrate where the gate bus line and the counter electrode region have been formed; forming an active region overlapped with the whole region of the gate bus line, by patterning the gate insulating layer, the amorphous silicon layer and the doped amorphous silicon layer in an identical shape; forming the counter electrode and the gate pad, by removing the opaque metal layer for the gate bus line in the counter electrode region and gate pad region; depositing an electrode insulating layer on the rear substrate where the active region, counter electrode and gate pad have been formed; opening a part of the active region and the gate pad, by patterning the electrode insulating layer; depositing a transparent conductive layer for a pixel electrode and an opaque metal layer for a data bus line on the rear substrate where the active region and gate pad region have been opened; forming a data bus line crossing the gate bus line, a source electrode and a drain electrode respectively electrically connected to the active region, the channel of the thin film transistor being positioned therebetween, a pixel electrode region for forming the pixel electrode to be overlapped with the counter electrode, and a contact portion of the gate pad, by patterning the transparent conductive layer for the pixel electrode and the opaque metal layer for the data bus line in an identical shape; depositing a protective layer on the rear substrate where the data bus line, source electrode, drain electrode, pixel electrode region and gate pad have been formed; opening the pixel electrode region and the contact portion of the gate pad, by pattering the deposited protective film; and forming the pixel electrode by removing the opaque metal layer for the data bus line in the opened pixel electrode region.