Patent ID: 8046546
Filing Date: 2011-10-25
Classification: G06F,G11C

Abstract:
1. A memory subsystem for use in a device, comprising: volatile memory; nonvolatile memory; a first volatile memory interface to directly interface to volatile memory control, data, and address busses of the device; a second volatile memory interface to directly interface to control, data, and address busses of the volatile memory; the memory subsystem configured to present an exclusively volatile memory interface to the device; logic to pass signals unchanged between the first volatile memory interface to the second volatile memory interface; logic to make available to the device at least one first portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure, including unmodified areas in the first portion; and logic to make available to the device at least one second portion of the volatile memory that can be modified by the device but that will not be backed up to the nonvolatile memory in the event of device power failure; and logic to enable the device to configure the first and second portions.