Patent ID: 6725357
Filing Date: 2004-04-20
Classification: G06F

Abstract:
A system comprising:a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive one or more instructions, said first-in-first-out memory including at least a first memory array to store said one or more instructions and to output said one or more instructions from said first-in-first-out memory such that said one or more instructions are available to at least one of said first and second execution units at a first time; memory store circuitry to store at least one instruction of said one or more instructions and to provide said at least one instruction to said third execution unit; and connection circuitry connecting said memory store circuitry to said first-in-first-out memory to provide said at least one instruction to said memory store circuitry in parallel to said one or more instructions being provided to said at least first memory array, wherein said at least one instruction is available to said third execution unit at substantially the same time as said first time.