Patent ID: 9219078
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A method for semiconductor fabrication, comprising: providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region and at least one Silicon (Si) channel region, the substrate including a plurality of regions including a first region and a second region; and forming gate structures for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region, and the second PFET, the first NFET and the second NFET being formed on the Si channel region, wherein the gate structure for the first NFET includes a gate electrode material having a first work function having a quartergap work function and comprising at least titanium and nitrogen, and the gate structures for the first PFET, second NFET and second PFET include a gate electrode material having a second work function having a midgap work function such that multi-threshold voltage devices are provided, wherein the gate electrode material having the first work function is not present in the gate structures for the first PFET, second NFET and second PFET, and the gate electrode material having the second work function is not present in the gate structure for the first NFET.