Patent ID: 7979777
Filing Date: 2011-07-12
Classification: H03M

Abstract:
1. A decoder comprising: an acquisition unit configured to acquire first respective likelihoods of data bits and second respective likelihoods of parity bits, the data bits and the parity bits included in code data obtained by LDPC-encoding the data bits with a low density parity check matrix; a detecting unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods; a forming unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities; an updating unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix; a discriminating unit configured to execute hard decision of the likelihoods updated by the updating unit; and a checking unit configured to execute parity check of a discrimination result of the discriminating unit, to obtain the code data.