Patent ID: 7106119
Filing Date: 2006-09-12
Classification: G06F,H03K

Abstract:
1. A circuit for the temporary interruption of an input sync signal having a plurality of leading edges and a plurality of trailing edges, comprising: a first divider that receives said input sync signal and supplies a first signal made up of said sync signal divided by two starting from a leading edge; a second divider that receives said inverse input sync signal and supplies a second signal made up of said sync signal divided by two starting from a trailing edge; an exclusive OR circuit that receives said first signal and said second signal and that supplies an output sync signal; a stop circuit for said first and said second divider; an asynchronous command signal of said stop circuit for the temporary interruption of said output sync signal; and wherein said first divider and said second divider each comprise a flip flop of the D type; and further wherein when said asynchronous command signal is placed at a low level, each flip flop has its inverse output connected to its input and to an input of said exclusive OR circuit, and when said asynchronous command signal is placed at a high level, each flip flop has a non-inverse output connected to its input and an inverse output connected to an input of said exclusive OR circuit.