Patent ID: 6580644
Filing Date: 2003-06-17
Classification: G11C

Abstract:
A flash memory device comprising:an array including a plurality of wordlines, a plurality of bitlines, and a plurality of nonvolatile memory cells located at intersections of the wordlines and bitlines; a column selecting circuit coupled to the array, the column selecting circuit for selecting a part of the bitlines; a row selecting circuit coupled to the array, the row selecting circuit for selecting one of the wordlines and providing a wordline voltage to the selected one; at least one reference cell for generating a reference current in response to a reference wordline voltage; a write control circuit for generating a test verify enable signal and a high voltage enable signal in response to receiving a test command directing the memory device to operate in a test operation mode; a verify control circuit for generating a test verify signal in response to the test command when the test verify enable signal is enabled; a high voltage generating circuit for generating a high voltage signal in response to receiving the high voltage enable signal; a first voltage regulator for receiving the high voltage signal and generating the reference wordline voltage in response to the test verify signal; a second voltage regulator for receiving the high voltage signal and generating the wordline voltage in response to the test verify signal; a sense amplifier circuit for determining whether an amount of a cell current flowing through an erased memory cell selected by the column selecting circuit and the row selecting circuit is larger than an amount of the reference current; and a pass/fail checking circuit for generating a pass/fail signal in response to an output of the sense amplifier circuit, wherein the test verify signal is disabled by the pass/fail signal indicating that the amount of the cell current is larger than the amount of the reference current; and wherein the wordline and reference wordline voltages generated for the test operation mode are higher than those generated for an erase verify operation mode.