Patent ID: 7607165
Filing Date: 2009-10-20
Classification: G06F

Abstract:
1. Automatic computing machinery having logic embodied thereon for performing a method of modular reduction processing of a number which is represented by a sequence of digits, comprising: providing a modular reduction processor; receiving a number x, wherein number x is provided in radix b form and is represented by sequence of 2k digits such that {x processing x, via the modular reduction processor, wherein x is processed least significant digit first and in digits in increasing order of significance thereafter, wherein processing x comprises: dividing x by b multiplying q dividing q multiplying q reducing the product of q reducing x modulo b subtracting r determining which of the following is true: r is non-negative and r r is non-negative and r r is non-negative and r r is negative and r r is negative and r r is negative and r wherein if r is non-negative and r wherein if r is non-negative and r wherein if r is non-negative and r wherein if r is negative and r wherein if r is negative and r wherein if r is negative and r