Patent ID: 6157265
Filing Date: 2000-12-05
Classification: G06F,H03K

Abstract:
A programmable multi-scheme clocking circuit implemented within an integrated circuit, the clocking circuit comprising:a plurality of clock sources having predetermined characteristics, the plurality of clock sources comprise:an internal oscillator, the internal oscillator digitally programmable to provide a range of frequencies and configured further to halt operation upon receiving a halt signal;a crystal clock circuit;an RC clock circuit; andan external clock interface circuit to receive and buffer an external clock signal;a multiplexer coupled to the plurality of clock sources, the multiplexer receives a set of control signals and provides one of the clock signals from the clock sources as an output clock signal; anda control circuit operatively coupled to the plurality of clock sources and the multiplexer, the control circuit includes a control register having control data to selectively enable one of the plurality of clock sources and provides the multiplexer with the set of control signals,wherein the control register comprises non-volatile memory (""NVM"") to store and to provide the set of control signals generated by the control data in accordance to a user-defined mode.