Patent ID: 9196492
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a gate bus line which couples gate fingers of a plurality of FETs and gate pads comprising: forming a metal layer on a semiconductor layer; forming a first mask layer on the metal layer, the first mask layer not covering a first pattern for a first portion the gate bus line; forming a plated layer within the first pattern for the first portion of the gate bus line on the metal layer with use of the first mask layer as a mask; forming a second mask layer which covers a second pattern for a second portion of the gate bus line on the metal layer while exposing the plated layer, the second mask layer having a width, in a first direction orthogonal to a second direction in which the gate bus line extends, smaller than a width in the first direction of the plated layer formed within the first pattern for the first portion of the gate bus line, the second portion of the gate bus line being connected to the first portion of the gate bus line in the second direction; and etching the metal layer with use of the plated layer and the second mask layer as a mask so that the metal layer beneath the second mask layer becomes the second portion of the gate bus line, the second portion of the gate bus line having a smaller width in the first direction than the first portion of the gate bus line, wherein the second portion of the gate bus line is located between the gate pads.