Patent ID: 7402871
Filing Date: 2008-07-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a cell region and a peripheral region; a lower interlayer insulating layer disposed on the semiconductor substrate; a buffer pad disposed on the lower interlayer insulating layer in the cell region; a capacitor having a storage node electrode disposed on the buffer pad, a plate electrode covering the storage node electrode, and a capacitor dielectric interposed between the storage node electrode and the plate electrode; a lower resistor disposed on the lower interlayer insulating layer in the peripheral region; an upper resistor disposed on the lower resistor to expose both ends of the lower resistor; an inter-resistor insulating layer interposed at least between the lower resistor and the upper resistor; an upper interlayer insulating layer disposed on the lower interlayer insulating layer to cover the capacitor, the lower resistor, and the upper resistor; and a resistor interconnection line, disposed on the upper interlayer insulating layer, contacting a resistor contact plug penetrating the upper interlayer insulating layer and being electrically connected to a first end of the lower resistor and a first end of the upper resistor.