Patent ID: 9143315
Filing Date: 2015-09-22
Classification: G06F,H03J,H03L,H04L

Abstract:
1. A method for synchronizing a frequency change between two clock domains, comprising: receiving receive and transmit reference frequencies from a phase-locked loop circuit; receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit through a delay circuit; obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains; calculating updated detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes to enable updates from a clock source to be sent directly to a synchronizer to manage changes in frequency between the transmit and receive clock domains; transmitting a transmit clock reference frequency to a transmit phase-locked loop circuit to generate the transmit reference frequency; and transmitting a receive clock reference frequency to a receive phase-locked loop circuit to generate the receive reference frequency, and wherein the phase-locked loop circuit comprises one of the transmit phase-locked loop circuit and the receive phase-locked loop circuit.