Patent ID: 6917227
Filing Date: 2005-07-12
Classification: H03K

Abstract:
1. A high frequency gate driver, comprising: a first transistor and a second transistor provided in a half-bridge configuration; an output node provided between the first and second transistors; a first delay circuit coupled to a first control terminal of the first transistor to provide a first delay period for a first gate drive signal being applied to the first control terminal, the first delay circuit provided on a direct signal path to the first control terminal of the first transistor; and a second delay circuit coupled to a second control terminal of the second transistor to provide a second delay period for a second gate drive signal being applied to the second control terminal, wherein the first delay period is different from the second delay period, wherein each of the first and second delay circuits is configured to operate without the use of a feedback signal, and wherein the first and second delay circuits provides one of the first and second transistors to be in a non-conducting state before placing the other in a conducting state, wherein the second delay circuit is provided on a direct signal path to the second control terminal of the second transistor, so that an output of the second delay circuit is applied directly to the second control terminal of the second transistor, wherein the first control signal is associated with a first clock signal, the change of a conductive state of the first transistor being actuated by the first control signal at a period corresponding to the first clock signal, wherein an output of the first delay circuit is applied directly to the first control terminal of the first transistor.