Patent ID: 6268769
Filing Date: 2001-07-31
Classification: H03F

Abstract:
An operational amplifier, comprising:a differential amplifier stage having a pair of differential amplifier circuits operable to receive positive and negative input signals and produce two outputs;a current mirror stage having a pair of current mirror circuits connected to a respective one of the outputs of the differential amplifier stage, the current mirror circuits producing a common output from an output terminal thereof;a buffer circuit having a first set of input transistors connected to the output terminal of the current mirror circuits, respectively, and a second set of input transistors connected to the output terminal of the current mirror circuits, respectively, and the first and second sets of transistors receiving input from the common output of the current mirror stage, each of the first set of input transistors and each of the second set of input transistors includes a control terminal, a first output terminal, and a second output terminal, the respective control terminals and first output terminals of the first set of input transistors are coupled together, the respective control terminals and first output terminals of the second set of input transistors are coupled together, and first and second series coupled output transistors connected from a first voltage potential to a lower voltage potential, the first and second series coupled output transistors each including a control terminal and forming a common output node, the respective first output terminals of the second set of input transistors being connected to the control terminal of the first output transistor, at least one of the second output terminals of the second set of input transistors being connected to the lower voltage potential, at least one of the second output terminals of the second set of input transistors being connected to the common output node, and the respective first output terminals of the first set of input transistors being connected to the control terminal of the second output transistor, at least one of the respective second output terminals of the first set of input transistors being connected to the upper voltage potential, and at least one of the respective second output terminals of the first set of input transistors being connected to the common output node.