Patent ID: 6340624
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A method of forming a circuitry isolation region within a semiconductive wafer comprising:masking an active area region over a semiconductive wafer, the active area region being provided with an impurity doping of a first conductivity type; providing an impurity of a second conductivity type within the semiconductive wafer proximate the masked active area region, the providing forming an outer wafer region proximate the masked active area region which is doped with the impurity of the second conductivity type; substantially selectively etching second conductivity type provided semiconductive wafer material of the outer wafer region relative to first conductivity type provided semiconductive wafer material to form a trench proximate the active area region which exposes first conductivity type semiconductive wafer material within the trench through the outer wafer region, said first conductivity type semiconductive wafer material not being exposed at the start of said etching; and forming electrically insulating material within the trench.