Patent ID: 7702972
Filing Date: 2010-04-20
Classification: G11C

Abstract:
1. A computer chip comprising: a plurality of chip functional elements, including: a group of protected SRAM macros; one or more spare SRAM macros; a plurality of control buses connected to subgroups of the protected SRAM macros; a plurality of store bus lanes connected to subgroups of said group of protected SRAM macros; a plurality of fetch bus lanes that are supplied by the read data out from said subgroups of the protected SRAMs; steering controls for steering any controls coupled to any of the protected SRAM macros to any of the spare SRAM macros; a steering store means of steering any of the store bus lanes connected to any of the protected SRAM macros to any of said spare SRAM macros, and a steering read means of steering read data from any of the spare SRAM macros to any of the fetch data bus lanes that are supplied by the read data out of any of the protected SRAM macros, whereby any of the protected SRAM macros are enabled to be replaced by any of the spare SRAM macros for continued full chip function of said functional elements despite any loss of one or more SRAM macros.