Patent ID: 6724670
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A shared redundancy memory circuit comprising:a main memory portion comprising a plurality of addresses, each of the plurality of addresses comprising a plurality of address bits and each of the plurality of addresses corresponding to a first memory segment and a second memory segment; a redundant memory portion configured to replace one or more addresses in the main memory portion; a plurality of redundancy fuses, each of the plurality of redundancy fuses corresponding to one of the plurality of address bits and configured to provide access to the redundant memory portion through the plurality of addresses corresponding to the first memory segment and the second memory segment, and wherein each of the plurality of redundancy fuses is coupled to each of the first memory segment and the second memory segment; and a plurality of logical devices configured to detect the state of each of the plurality of redundancy fuses corresponding to each of the plurality of address bits.