Patent ID: 6226222
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A read only memory comprising:a master signal source, the master signal being generated when an address signal is changed;a clock signal source, the clock signal having constantly oscillated pulse periods;a sense amplifier operated by a plurality of sense amplifier control signals;a latch circuit coupled to an output of the sense amplifier; anda sense amplifier control circuit comprising:a first circuit for generating a first of the sense amplifier control signals;a second circuit for generating a second of the sense amplifier control signals, the second sense amplifier control signal being generated in response to latency information signal corresponding to the pulse period of the clock signal in a specific frequency condition;a third circuit for generating a latch control signal which is applied to the latch circuit, the latch control signal being generated in response to a latency counting signal in the specific frequency condition; anda fourth circuit for generating a third of the sense amplifier control signals, the third control signal being activated in response to the master signal and is disabled in response to the latch control signal.