Patent ID: 6944808
Filing Date: 2005-09-13
Classification: G01R

Abstract:
1. A method of evaluating a system-on-a-chip IC (SoC), comprising the following steps of: building two or more metal layers to establish a pad frame and internal circuit nodes for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby creating core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core; testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC received through the chip I/O pads; testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the core I/O pads; and finding a location of a fault when the fault is detected either when testing the SoC chip as a whole or when testing each core.