Patent ID: 8832403
Filing Date: 2014-09-09
Classification: G06F,G11C

Abstract:
1. A multiprocessor system adapted to carry out parallel threads of instructions and comprising: a plurality of processors and a memory device coupled to the processors; a plurality of messaging units for issuing and queuing memory access requests associated with the memory device; and a central synchronization controller communicating synchronization control information to or from the messaging units via point to point communication rather than via a bus, the synchronization control information including independently operable instructions which comprises: a first instruction and a second instruction; one or more of the plurality of processors issuing memory write commands; the central synchronization controller issuing the first instruction after the issuance of the memory write commands, wherein before the issuance of the first instruction, the issued memory write commands are not visible to all the plurality of processors, wherein after the issuance of the first instruction, the issued memory write commands are visible to all the plurality of processors; and the central synchronization controller issuing the second instruction which enables a data location update of the memory device and a guard (flag) location update of the memory device to be performed at separate times by the one or more of the plurality of processors.