Patent ID: 6689658
Filing Date: 2004-02-10
Classification: H01L

Abstract:
A method of fabricating a stack-gate flash memory array on a semiconductor substrate comprising:forming a shallow-trench-isolation (STI) structure on said semiconductor substrate having a plurality of parallel STI lines formed alternately and a plurality of parallel active-region lines formed therebetween, wherein each of said plurality of parallel active-region lines has a major first conductive layer being formed on a thin tunneling dielectric layer and each of said plurality of parallel STI lines has two extended second conductive layers being formed on each of a plurality of planarized field-oxides (FOX); wherein said major first conductive layer is electrically connected with two neighboring extended second conductive layers to form a self-aligned integrated floating-gate layer; forming sequentially an intergate dielectric layer, a third conductive layer, and a second masking dielectric layer over said STI structure; patterning a plurality of parallel word lines perpendicular to said plurality of parallel STI lines followed by sequentially removing said second masking dielectric layer, said third conductive layer, said intergate dielectric layer, and etching said self-aligned integrated floating-gate layer to a thickness of said extended second conductive layer, wherein said extended second conductive layers over each of said plurality of planarized field-oxides outside of said plurality of parallel word lines are removed and said major first conductive layer is partially etched to have a remained first conductive layer over each of said plurality of parallel active-region lines outside of said plurality of parallel word lines; implanting doping impurities having a dopant type opposite to that of said semiconductor substrate across said remained first conductive layer and said thin tunneling dielectric layers in a self-aligned manner into said semiconductor substrate along said plurality of parallel active-region lines to form a plurality of first symmetrical common-source/drain diffusion regions; etching back anisotropically said plurality of planarized field-oxides along designated common-bus lines to a depth approximately equal to a thickness of said remained first conductive layer and then removing anisotropically said remained first conductive layers in a self-aligned manner; forming second dielectric spacers over sidewalls of said plurality of parallel word lines and simultaneously forming third dielectric spacers over sidewalls of said plurality of planarized field-oxides; removing said thin tunneling dielectric layers over said semiconductor substrate along said plurality of parallel active-region lines and simultaneously etching said plurality of planarized field-oxides along said plurality of parallel STI lines in a self-aligned manner to form a plurality of flat beds along said designated common-bus lines and to expose a plurality of common-source/drain contact holes; forming a fourth conductive layer over each of said plurality of flat beds as a self-registered common-bus line and over each of said plurality of common-source/drain contact holes as a self-registered common-source/drain landing island, wherein said fourth conductive layer is implanted with a high dose of doping impurities having a dopant type opposite to that of said semiconductor substrate to act as a self-aligned dopant diffusion source for forming a plurality of shallow heavily-doped common-source/drain diffusion regions within said plurality of first symmetrical common-source/drain diffusion regions; and forming a self-aligned silicide layer over each of said plurality of self-registered common-bus lines and each of said plurality of self-registered source/drain landing islands.