Patent ID: 7763915
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A three-dimensional integrated CMOS circuit formed in a hybrid substrate with superposed bottom and top levels, comprising: a plurality of n-MOS transistors formed, at the bottom level, in a silicon semi-conducting layer having a (100) orientation, and a plurality of p-MOS transistors formed, at the top level, in a germanium semi-conducting layer having a (110) orientation, wherein an axis passing through a drain and a source of the n-MOS transistor of the plurality of n-MOS transistors is perpendicular to an associated axis passing through a drain and a source of an associated p-MOS transistor of the plurality of p-MOS transistors so as to form at least one overlapping zone in which an interconnection of the n-MOS transistor and the associated p-MOS transistor is formed, and wherein the at least one overlapping zone is an overlap between the silicon semi-conducting layer and the germanium semi-conducting layer.