Patent ID: 8912064
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A method for forming an impurity region of a vertical transistor, comprising: forming a preliminary trench by etching the semiconductor substrate; forming an impurity ion junction region in the semiconductor substrate by performing an ion implantation process on the semiconductor substrate exposed by the preliminary trench; forming a material layer and filling the material layer in the preliminary trench by using a material which is substantially equal to a material of the semiconductor substrate; and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed, wherein the etching for forming the trench is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region, and wherein the forming of the material layer is performed by an epitaxial growth process.