Patent ID: 7446395
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: an NFET device having a spacer; a PFET device having a spacer; an isolation separating the NFET and the PFET devices; a protective layer over only a selected one of the NFET device and the PFET device; a first silicon nitride liner over the protective layer; a second silicon nitride liner over the other one of the NFET device and the PFET device; and a first silicide layer adjacent the selected one of the NFET device and the PFET device and a second silicide layer adjacent the other one of the NFET device and the PFET device, wherein a thickness of the first and second silicide layers is substantially the same in an area outside of the spacers.