Patent ID: 6804162
Filing Date: 2004-10-12
Classification: G06F,G11C

Abstract:
A circuit arrangement for providing read-modify-write memory, the circuit arrangement comprising:a memory having at least one read-or-write bank and further comprising a read-modify-write bank electrically coupled to the at least one read-or-write bank; and control circuitry adapted for using at most one access to each said at least one read-or-write bank for each read-modify-write access to the memory during a single memory access cycle; wherein the circuit arrangement is adapted to use at most one access to each said at least one read-or-write bank and only one access to the read-modify-write bank for each read-modify-write access to the memory; and wherein the read-modify-write bank has a cycle time that is smaller than the sum of the read cycle time and write cycle time of a slowest read-or-write bank in the memory arrangement, wherein the circuit arrangement is adapted to effect a read-modify-write cycle time that is smaller than the sum of the slowest read-or-write bank's read cycle time and write cycle time.