Patent ID: 6038173
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A read circuit for a non-volatile memory of the type comprising a matrix of memory cells, the read circuit being connected, firstly, to said memory cells by at least one bit line and, secondly, to a reference cell by a reference line, the read circuit comprising:precharging means to precharge the bit line and the reference line, said precharging means comprisinginterrupt means to interrupt precharging of the bit line and the reference line when a potential of the bit and reference lines reaches a boundary value,a comparison circuit for comparing the precharging potential of the bit line and reference line with the boundary value, the comparison circuit delivering a comparison signal and comprisinga first N type transistor having a drain connected to a supply terminal of the read circuit, a gate connected to the bit line, and a source connected to a current source, anda second N type transistor having a gate connected to the source of the first transistor and a source connected to ground, and a drain delivering the comparison signal,precharging transistors to precharge the bit line and reference line, andcontrol means for controlling the precharging transistors responsive to the comparison signal and a precharging signal with a constant period.