Patent ID: 6351413
Filing Date: 2002-02-26
Classification: G11C

Abstract:
A nonvolatile memory device, comprising a memory array including a plurality of cells grouped into sectors and arranged on sector rows and columns, each of the sectors being a smallest portion of the memory array that is individually erasable, wherein said memory array has an own width and an own height, and each sector has an own width and an own height, the device further comprising:a global row decoder and a global column decoder; a plurality of global word lines, extending substantially along the entire width of said memory array from said global row decoder; a plurality of global bit lines extending along a plurality of sectors, in a height direction of said memory array from said global column decoder; a plurality of local row decoders respectively associated with the sectors such that each sector is uniquely associated with a respective one of the local row decoders; a plurality of local column decoders respectively associated with the sectors such that each sector is uniquely associated with a respective one of the local row decoders; wherein each of the sectors includes a plurality of local word lines extending substantially along the entire width of the sector from the local row decoder associated with the sector; and a plurality of local bit lines extending substantially along the entire height of the sector from the local bit decoder associated with the sector; and each global word line being connected to a plurality of the local word lines that are aligned with each other; and each global bit line being connected to a plurality of the local bit lines that are aligned with each other.