Patent ID: 6473342
Filing Date: 2002-10-29
Classification: G11C,H01L

Abstract:
A method of operating a split gate type of non-volatile memory cell including:a substrate; first and second regions formed separatedly right and left on the substrate; a first insulating layer formed on top of and between the first and second regions on the substrate; a floating gate formed on the first insulating layer on top of a predetermined portion of the second region and between the first and second regions; a second insulating layer formed on top of and side of the floating gate; and a control gate formed on a predetermined portion on top of the first and second insulating layer, the method comprising the steps of: performing an erasing operation by respectively applying a first voltage to the first and second regions, a high voltage to the control gate and a negative voltage lower than the first voltage to the substrate; performing a programming operation by respectively applying the first voltage to the first region, a second voltage to the control gate and the negative voltage to the substrate; and performing a reading operation by respectively applying the first voltage to the second region, a read voltage to the first region, a reference voltage to the control gate and the first voltage to the substrate.