Patent ID: 7381602
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure, comprising: providing a substrate comprising a first transistor element and a second transistor element; forming a first stressed layer over said first transistor element; forming a first dielectric layer over said first transistor element but not over said second transistor element; forming a second stressed layer over said second transistor element after formation of said first dielectric layer, wherein said second stressed layer does not cover said first transistor element; forming a second dielectric layer over said substrate after formation of said second stressed layer; and planarizing said first dielectric layer and said second dielectric layer, wherein a portion of said second dielectric layer located over said first transistor element is removed during said planarization; wherein at least one of said first stressed layer and said second stressed layer has a predetermined tensile intrinsic stress of at least about 900 MPa, and formation of said at least one of said first stressed layer and said second stressed layer comprises performing a plasma enhanced chemical vapor deposition process in a reactor vessel, said plasma enhanced chemical vapor deposition process comprising: