Patent ID: 6166556
Filing Date: 2000-12-26
Classification: G01R,H01L

Abstract:
A method for testing integrated circuitry of a semiconductor device comprising the steps of:providing a semiconductor die having integrated circuitry coupled to a bond pad and a test pad formed on a surface of the semiconductor die that are electrically connected to each other;providing a test substrate having a solder bump for making electrical and physical connection to the test pad of the semiconductor die;bringing the solder bump on the test substrate in contact with the test pad on the semiconductor die;testing the integrated circuitry of the semiconductor die by transmitting electrical signals thereto via the solder bump of the test substrate in contact with the test pad;separating the test substrate from the semiconductor die while the solder bump is in a liquidus state; andattaching a wire bond to the bond pad for electrically accessing the integrated circuitry.