Patent ID: 7709904
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A thin film transistor substrate comprising: an insulating substrate; a first thin film transistor formed above said insulating substrate, wherein said first thin film transistor comprises a first active layer formed above said insulating substrate, a first gate insulating film formed on said first active layer, and a first gate electrode formed on said first gate insulating film; and a second thin film transistor formed above said insulating substrate, wherein said second thin film transistor comprises a second active layer formed above said insulating substrate, a second gate insulating film formed on said second active layer, and a second gate electrode formed on said second gate insulating film, wherein said second gate insulating film comprises said first gate insulating film and a gate cover film formed above said first gate insulating film, wherein said second active layer has at least two impurity doping regions which overlap said second gate electrode, wherein said first active layer has at least two impurity doping regions formed in a self aligning manner with respect to said first gate electrode, wherein said second thin film transistor further comprises a third gate electrode, wherein a gate length of said third gate electrode is shorter than a gate length of said second gate electrode, wherein said third gate electrode is formed between said second active layer and said second gate electrode and on the first gate insulating film, wherein said impurity doping regions formed in a self aligning manner are formed so as to overlap said first gate electrode by 0.1 μm or less, and wherein said second active layer comprises a first channel region disposed directly below said second gate electrode, a second channel region disposed directly below said third gate electrode and wherein one of said impurity doping regions overlapping said second gate electrode is disposed between said first and second channel regions and has a portion not directly below either said second gate electrode or said third gate electrode.