Patent ID: 6821879
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A method of forming an interconnect for a semiconductor on a substrate using a dual damascene process, comprising:forming a first layer of silicon oxide on the substrate; and forming a trench in the first layer of silicon oxide in which to form an encapsulated copper diffusion barrier, the formation of the copper diffusion barrier comprising: forming a first layer comprised of one of at least a doped amorphous silicon and polysilicon on the trench surface; forming a first layer of palladium on the first layer of the one of at least the doped amorphous silicon and polysilicon; forming a first layer comprised of one of at least a cobalt phosphorus, an alloy of cobalt/nickel phosphorus and nickel phosphorus on the first layer of palladium; and forming a metal conductor on the first layer comprised of one of at least a cobalt phosphorus, an alloy of cobalt/nickel phosphorus or nickel phosphorous; encapsulating the metal conductor with a second subsequent layer of the one of at least the cobalt phosphorus, alloy of cobalt/nickel phosphorus or nickel phosphorous layer, followed by a second layer of palladium; and forming a second layer of silicon oxide on the first layer of silicon oxide and the encapsulated copper diffusion barrier.