Patent ID: 7032142
Filing Date: 2006-04-18
Classification: G06F,G11C

Abstract:
1. A memory circuit, having: a real cell array for storing data; a parity or error correction code (ECC) generating circuit for generating a parity bit or an ECC from data of said real cell array; a parity or ECC cell array for storing said parity bit or ECC; a refresh control circuit, which generates an internal refresh request signal at a predetermined cycle, sequentially refreshes the real cell array in accordance with a refresh address, and, when an internal refresh request and a read request coincide, prioritizes a refresh operation for the real cell array; a data recovery section, which, in accordance with the parity bit or ECC read out from said parity or ECC cell array, recovers data read out from the real cell array for which the refresh operation has been prioritized; an output circuit for outputting data from said real cell array via said data recovery section; and a test control circuit, which, at a first test mode, prohibits a refresh operation for said real cell array to thereby output data read out from said real cell array, and, at a second test mode, controls said output circuit so as to output data read out from said parity or ECC cell array.