Patent ID: 8816333
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A FET device comprising: a substrate; a carbon-based material on the substrate; source and drain region electrodes on a surface of the carbon-based material, spaced apart from one another so as to permit a gate electrode to be placed therebetween; an ultra thin silicon nucleation layer having a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of a dielectric layer on the surface of the carbon-based material; the dielectric layer over the ultra thin silicon nucleation layer; and the gate electrode over the dielectric layer between the source and drain region electrodes, wherein the ultra thin silicon nucleation layer is discontinuous and does not fully cover the surface of the carbon-based material on which the dielectric layer is present yet serves as a nucleation center for the dielectric layer on the surface of the carbon-based material such that a continuous layer of the dielectric layer is present over a discontinuous layer of the ultra thin silicon nucleation layer on the surface of the carbon-based material between the source and drain electrodes.