Patent ID: 8093653
Filing Date: 2012-01-10
Classification: H01L

Abstract:
1. A fabrication method of a trench metal oxide semiconductor transistor comprising: forming an epitaxial layer of a first conductivity type over a silicon substrate; forming a plurality of first trenches in the epitaxial layer; blanket implanting impurities of the first conductivity type into the epitaxial layer; forming a polysilicon pattern filling the first trench and covering a predetermined range of the epitaxial layer surrounding the first trenches by using lithography and etching process through a polysilicon mask; implanting impurities of a second conductivity type into the epitaxial layer through the polysilicon pattern; driving in the impurities implanted in the epitaxial layer to form a well with the second conductivity type; implanting impurities of the first conductivity type into the well through the polysilicon pattern to form a plurality of first doped regions; driving in the impurities implanted in the first doped regions to form a plurality of source regions adjacent to the first trenches respectively; removing a portion of the polysilicon pattern located above an upper surface of the epitaxial layer to leave a plurality of polysilicon gates in the first trenches; depositing a dielectric layer and forming a contact window therein to expose the source regions; and depositing a metal layer over the dielectric layer to cover the exposed source regions.