Patent ID: 6870754
Filing Date: 2005-03-22
Classification: G11C

Abstract:
1. A ferroelectric memory comprising: a memory cell block including ferroelectric memory cells arranged in the form of m rows×n columns where m and n are natural numbers, each of said ferroelectric memory cells outputting a memory value from a data terminal thereof when reading potentials are applied to a first selective terminal and a second selective terminal; a plurality of bit lines each commonly connected to the data terminals of a plurality of said ferroelectric memory cells; a plurality of first selective lines each commonly connected to the first selective terminals of a plurality of said ferroelectric memory cells; and a plurality of second selective lines each commonly connected to the second selective terminals of a plurality of said ferroelectric memory cells, wherein said first selective lines and said second selective lines are provided so that the number of the ferroelectric memory cells connected to a same first selective line and a same second selective line is j, where j is a factor of m, wherein said first selective lines are n number of plate lines provided for the respective columns so that each plate line is connected to the first selective terminals of all of the ferroelectric memory cells in a corresponding column, and said second selective lines are n number of word lines provided over a plurality of columns so that each word line is connected to the second selective terminals of j number of the ferroelectric memory cells in the corresponding column, wherein said word lines comprise