Patent ID: 7504286
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A method for fabricating a memory device, the method comprising the steps of: providing a semiconductor substrate comprising: a first well region of a first conductivity type, a second well region of the first conductivity type, a first gate structure overlying the first well region and a second gate structure overlying the second well region; providing an ion implantation mask overlying the first gate structure and the second gate structure and which exposes portions of the first well region and the second well region; implanting dopant ions having a second conductivity type into the exposed portions of the first well region and the second well region to form: a drain region and a source/base region in the semiconductor substrate adjacent the first gate structure, and a cathode region in the semiconductor substrate adjacent the second gate structure; conformally depositing an insulating material layer overlying exposed portions of the semiconductor substrate; providing photosensitive material over a portion of the insulating material layer which overlies a portion of the second well region, wherein the photosensitive material exposes portions of the insulating material layer; and anisotropically etching the exposed portions of the insulating material layer to provide: