Patent ID: 6569732
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of fabricating a buried stack capacitor structure on a semiconductor substrate, comprising the steps of:forming a composite insulator layer on said semiconductor substrate; forming shallow trench shapes in said composite insulator layer and in a top portion of said semiconductor substrate; filling said shallow trench shapes with an insulator layer, resulting in a shallow trench isolation (STI) regions; growing a pad silicon dioxide layer on portions of said semiconductor substrate not occupied by said STI regions; forming an implanted well region in portions of said semiconductor substrate not occupied by said STI regions; depositing a silicon nitride layer; depositing a silicon oxide layer; performing a chemical mechanical polishing procedure exposing regions of said silicon nitride layer located on top surface of said STI regions and resulting in a planar top surface topography, comprised of portions of said silicon oxide layer on portions of said silicon nitride layer, both located overlying said pad silicon dioxide layer in regions between silicon nitride covered STI regions; removing portions of said silicon nitride layer from top surface of said STI regions; performing a dry etch patterning procedure to remove a top portion of said insulator layer from a peripheral area of an STI region, and to remove an area of said silicon oxide layer located adjacent to said peripheral area of said STI region, exposing a region of said silicon nitride layer, resulting in definition of an initial self-aligned opening, removing exposed regions of said silicon nitride layer and underlying region of said pad silicon dioxide layer, resulting in a final self-aligned opening in which a bottom portion of a peripheral region of said STI region, and a portion of said semiconductor substrate located adjacent to said peripheral area of said STI region, is exposed; forming a storage node structure in said final self-aligned opening; forming a capacitor dielectric layer on said storage node structure; and forming an upper plate structure resulting in said buried stacked capacitor structure comprised of said upper plate structure, said capacitor dielectric layer, and said storage node structure.