Patent ID: 7666747
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A process for manufacturing a semiconductor device, comprising: forming a field effect transistor in a device area of a surface of a semiconductor substrate and forming a discharge high-concentration impurity region in a grid area of the surface of the semiconductor substrate; forming an intermediate insulating film over the semiconductor substrate; forming a wiring pattern using a dry etching method, the wiring pattern connected to a gate electrode of the field effect transistor through a first contact hole provided in the intermediate insulating film placed over the device area and connected to the discharge high-concentration impurity region through a second contact hole provided in the intermediate insulating film placed over the grid area; and cutting the semiconductor substrate at a boundary between the device area and the grid area, to remove the grid area of the semiconductor substrate from the device area of the semiconductor substrate, wherein said forming a wiring pattern further includes