Patent ID: 6625684
Filing Date: 2003-09-23
Classification: G01R,G06F

Abstract:
An application specific integrated circuit including:a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a respective block bus, an interface block including a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output, a register coupled to the output of said first addressable multiplexer, and a second addressable multiplexer for selecting between data provided by the output of said first addressable multiplexer and data in said register, said second addressable multiplexer having an output, means for receiving externally supplied address words and applying different portions thereof to said first addressable multiplexer and said respective addressable multiplexer, and a decoder responsive to said address words for controlling said second addressable multiplexer.