Patent ID: 7349273
Filing Date: 2008-03-25
Classification: G11C,H01L

Abstract:
1. A method of applying a test voltage to each of a plurality of circuit wells fabricated in a semiconductor substrate of an integrated circuit and isolated from each other, the method comprising: applying a test voltage to the integrated circuit through an externally accessible terminal; coupling the externally accessible terminal to one of the circuit wells while isolating the externally accessible terminal from the other circuit wells, the act of coupling the externally accessible terminal to one of the circuit wells comprising; providing first and second transistors fabricated in respective wells of the substrate for each of the circuit wells, the first and second transistors having first source-drain regions interconnecting to each other and second source-drain regions coupled to the wells in which they are fabricated; coupling the first and second transistors for each of the circuit wells between the externally accessible terminal and the respective circuit well; applying signals to gate electrodes of the first and second transistors for the one circuit well that causes the first and second transistors to turn on; and applying signals to gate electrodes of the first and second transistors for the other circuit wells that causes the first and second transistors to turn off.