Patent ID: 8053779
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A thin film transistor panel comprising: a substrate having a TFT region and a capacitor region on a surface of the substrate; an active layer formed on the TFT region of the substrate, the active layer including a source region and a drain region; a gate insulation layer formed on the TFT region and on the capacitor region of the substrate; a gate electrode formed on the gate insulation layer over the active layer; a TFT interlayer insulation layer formed in the TFT region, the TFT interlayer insulation layer formed on the gate electrode and on the TFT region; a source electrode formed on the TFT interlayer insulation layer, the source electrode being connected to the source region; a drain electrode formed on the TFT interlayer insulation layer, the drain electrode being connected to the drain region; a capacitor lower electrode formed on the gate insulation layer of the capacitor region; a capacitor interlayer insulation layer formed on the capacitor lower electrode, the capacitor interlayer insulation layer including a first capacitor insulation layer pattern formed on the capacitor lower electrode, the first capacitor insulation layer pattern not being formed on the gate electrode; and a capacitor upper electrode formed on the capacitor interlayer insulation layer.