Patent ID: 8305323
Filing Date: 2012-11-06
Classification: G09G,G11C

Abstract:
1. A display apparatus comprising: a timing controller which outputs image data, a first output enable signal, a second output enable signal, a clock generating signal, a gate control signal and a data control signal, wherein the second output enable signal has a phase later than a phase of the first output enable signal; a clock generator which generates a first clock signal and a second clock signal based on the first output enable signal, the second output enable signal and the clock generating signal, wherein the first output enable signal determines a high period of the first clock signal, and the second output enable signal determines a high period of the second clock signal; a gate driver which sequentially outputs gate signals in response to the first clock signal, the second clock signal, and the gate control signal, wherein each of the gate signals is generated at a high state during a horizontal scanning period; a data driver which converts the image data into data signals in response to the data control signal, wherein a polarity of the data signals is inverted every horizontal scanning period; and a display panel comprising: a plurality of gate lines which sequentially receives the gate signals; a plurality of data lines which receives the data signals; and a plurality of pixels connected to the plurality of gate lines and to the plurality of data lines and which receives the data signal in response to the gate signals to display an image, wherein the gate signals transition to a low state before the polarity of the data signals is inverted; wherein the first clock signal rises to a high level in response to a rising edge of the first output enable signal and falls to a low level in response to a rising edge of the second output enable signal, and wherein the second clock signal rises to a high level in response to a rising edge of the second output enable signal and falls to a low level in response to a rising edge of the first output enable signal.