Patent ID: 8330886
Filing Date: 2012-12-11
Classification: G02F

Abstract:
1. A thin film transistor array substrate, comprising: a plurality of scan lines and a plurality of data lines disposed on a substrate to define a plurality of pixel areas; a plurality of pixel electrodes, each of the pixel areas being disposed with one of the pixel electrodes; a plurality of thin film transistors, each of the thin film transistor being disposed on one of the scan lines and each of the thin film transistors comprising a gate electrode being a portion of the one of the scan lines; a source electrode disposed over the gate electrode and electrically connected to one of the data lines; a first drain electrode disposed over the gate electrode corresponding to the source electrode and partially overlapping with one of the pixel electrodes located at a first side of the one of the scan lines, wherein a portion of the first drain electrode is contacted to the pixel electrode located at the first side through a contact hole; a second drain electrode disposed over the same gate electrode corresponding to the same source electrode and partially overlapping with and not contacted to another one of the pixel electrodes located at a second side of the one of the scan lines, wherein the first side and the second side are located at two opposite sides across the one of the scan lines; and an insulation layer disposed on the substrate and covering the thin film transistor, wherein the insulation layer has a contact hole and the first drain electrode is electrically connected to the one of the pixel electrodes located at the first side of the one of the scan lines through the contact hole; and the second drain electrode is electrically insulated with the pixel electrodes and the data lines by the insulation layer before repairing.