Patent ID: 7080194
Filing Date: 2006-07-18
Classification: G06F

Abstract:
1. A system for arbitrating memory access requests, said system including: an arbiter; a DRAM; and at least two clients, wherein the arbiter is coupled between the clients and the DRAM, the clients are configured to assert to the arbiter read and write commands for the DRAM, and the arbiter is operable to pass through to the DRAM selected ones of the commands, wherein the arbiter is configured to enter a first state upon passing a current command to the DRAM, the arbiter in the first state is configured to respond to assertion of each set of the commands that includes at least one command of the same read/write type as the current command by passing through to the DRAM a command in the set of the same read/write type as the current command, and the arbiter in the first state is configured to enter a wait state having duration that does not exceed a predetermined duration in response to assertion of a homogeneous set of at least one of the commands, wherein the homogeneous set includes no command of the same read/write type as the current command, the arbiter in the wait state prevents pass-through to the DRAM of any command that is not of the same read/write type as the current command, and the arbiter in the wait state responds to assertion of a set of the commands that includes at least one command of the same read/write type as the current command by passing through to the DRAM a command in the set of the same read/write type as the current command.