Patent ID: 6974999
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A semiconductor device comprising, on a semiconductor substrate, a peripheral circuit having a transistor and a cell array having a plurality of memory cells, wherein said transistor of said peripheral circuit includes: a first gate electrode; a side wall formed on a side surface of said first gate electrode; and a source-drain region formed in said semiconductor substrate and having a low impurity concentration region provided so as to sandwich said gate electrode and a high impurity concentration region provided outside said low impurity concentration region so as to sandwich said gate electrode, wherein a width of said side wall is smaller than a space between said first gate electrode and said high impurity concentration region, a contact is formed on an upper surface of said source-drain region, and said memory cell of said cell array includes: a second gate electrode; and a hard mask formed on an upper surface of said second gate electrode, and said hard mask is formed in only a region of said upper surface of said second gate electrode other than a region in which a contact is to be formed.