Patent ID: 6333874
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A semiconductor memory device having a normal mode and a standby mode, the device comprising:an array of memory cells arranged in columns and rows;a plurality of word lines, each being associated with one of the rows;a plurality of bit lines, each being associated with one of the columns;a plurality of access transistors, each being provided for an associated one of the memory cells, connected between a data retention node of the associated memory cell and one of the bit lines that is associated with the memory cell, and receives, at its gate, a voltage on one of the word lines that is associated with the memory cell; andpotential difference generating means for generating a negative potential difference between the gate and source of one of the access transistors while the device is in the standby mode, the access transistor being connected to a data retention node storing logical-one-level or logical-zero-level data thereon.