Patent ID: 6653685
Filing Date: 2003-11-25
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a plurality of nonvolatile memory cells, each including, a memory gate electrode formed over a first semiconductor region with first and second gate insulating films interposed therebetween; first and second switch gate electrodes formed over the first semiconductor region lying on both sides of the memory gate electrode with a third interlayer insulating film interposed therebetween; and first and second signal electrodes each used a source or drain electrode, which are formed in the first semiconductor region lying in the neighborhood below the respective first and second switch gate electrodes; wherein the memory gate electrode and the first and second switch gate electrodes respectively extend in a first direction, the first and second signal electrodes respectively have first and second signal wirings which are connected thereto and extend in a second direction substantially orthogonal to the first direction, and the first and second signal wirings are shared between a plurality of nonvolatile memory cells arranged in parallel in the second direction, and the memory gate electrode and the first and second switch gate electrodes are shared between a plurality of nonvolatile memory cells arranged in parallel in the first direction.