Patent ID: 6518166
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method of forming a dual damascene opening in low dielectric constant (low k) layers, on a semiconductor substrate, comprising the steps of:providing a lower level metal interconnect structure; forming a composite insulator layer on said lower level metal interconnect structure, comprised of an underlying low k layer, a stop layer, and an overlying low k layer; forming a via opening in said composite insulator layer; performing a liquid phase deposition procedure to form an undoped silicon oxide layer on the sides of said via opening; forming a trench in said overlying low k layer, wherein said via opening is located below said trench, and with said via opening now comprised with liquid phase deposited undoped silicon oxide spacer; and forming a metal structure in said trench and in said via opening, with a metal via structure located in said via opening, contacting said underlying lower level metal interconnect structure.