Patent ID: 8936978
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A process of forming a multigate structure comprising: providing a plurality of ultra-thin silicon or carbon bodies of less than 10 nanometers thick on a semiconductor substrate, forming multigate structures on the substrate, wherein the multigate structures comprise a plurality of gate electrodes; forming dielectric spacers electrically isolating the multigate structures from the ultra-thin silicon or carbon bodies, electrolessly depositing metallic layer selectively on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and on the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, wherein the electrolessly deposited metallic layer and ultra-thin silicon or carbon bodies form source and drain regions; and wherein the electrolessly depositing employs a electroless plating solution that comprises a pH adjusting agent, a buffer, a complexing agent, a stabilizer, and one or more surfactants and wherein the electroless plating solution during the deposition is at a temperature of about 40° C. to about 95° C.; which process further comprises providing a silicide layer of at least 2 nanometers and less than 20 nanometers thickness located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies intermediate the electrolessly deposited metallic layer.