Patent ID: 7705902
Filing Date: 2010-04-27
Classification: H04N

Abstract:
1. An image signal processing apparatus comprising: a) an image sensing unit which sequentially outputs an image signal corresponding to an object image in a first frame rate; b) a memory having a first frame memory region and second frame memory region; c) a display unit which sequentially displays an image of the input image signal in a second frame rate; and d) a memory control unit which controls a writing operation and reading operation of said memory, wherein said memory control unit controls the memory to write the image signal which is sequentially output in the first frame rate from said image sensing unit on the first frame memory region or second frame memory region, and sequentially output the image signal read from the first frame memory region or second frame memory region to said display unit in the second rate; and e) a determination unit which determines whether or not the first frame rate is higher or lower than the second frame rate, wherein if said determination unit determines that the first frame rate is higher than the second frame rate, said memory control unit controls to repeat writing a plurality of different frame image signal on the second frame memory region as the writing operation while controls not to execute the writing operation on the first frame memory region until the reading operation from the first frame memory region is completed, and wherein if said determination unit determines that the first frame rate is lower than the second frame rate, said memory control unit controls to repeat reading same frame image signal from the first frame memory region as the reading operation while controls not to execute the writing operation on the second frame memory region until the writing operation on the second frame memory region is completed.