Patent ID: 6343346
Filing Date: 2002-01-29
Classification: G06F

Abstract:
A shared memory processing system, comprising:a multi-stage network; a shared memory; a plurality of processing nodes interconnected by said multi-stage network, each processing node including a section of said shared memory, a local processor, at least one local cache and a local invalidation directory, said local invalidation directory for tracking which of said plurality of processing nodes have accessed copies of data held in said shared memory at said local processor; means for writing a second data to replace a first data in said at least one cache at a first node, and either writing the same second data selectively to replace said first data in shared memory at said first node or sending that same second data over said network to be written to a section of shared memory of a second node; means responsive to said local invalidation directory for identifying a set of processing nodes having copies of said first data; and means for generating and sending invalidation messages over said network for invalidating said copies of first data in said set of processing nodes.