Patent ID: 6181730
Filing Date: 2001-01-30
Classification: H04L

Abstract:
A pull-in circuit for pseudo-random pattern for carrying out a pull-in of a parallel receiving data having n bits inputted into a receiving-data input terminal and a parallel pseudo-random pattern having n bits generated by a parallel pseudo-random pattern generation circuit, and for inputting the parallel receiving data to the parallel pseudo-random pattern generation circuit in accordance with a latch signal received by a latch signal input terminal; comprising:a pseudo-random pattern operating circuit for operating a pseudo-random pattern, which inputs consecutive N bits of the receiving data and outputs a pseudo-random pattern having consecutive x bits which do not have common bits with the N bits;a comparison circuit for comparing the consecutive x bits outputted from the pseudo-random pattern operating circuit with other consecutive x bits of the receiving data corresponding to the consecutive x bits, which outputs a coincidence detection signal if the consecutive x bits are entirely coincident with the other consecutive x bits;a one-shot circuit for passing only a first pulse outputted from the comparison circuit after a start signal is outputted to a latch start signal input terminal, which outputs the pulse to the latch signal input terminal of the parallel pseudo-random pattern generation circuit;a delay circuit for delaying the receiving data; anda bit error detection circuit for detecting a bit error, which receives an output from the delay circuit and an output from the parallel pseudo-random generation circuit, which compares each bit of the output from the delay circuit with that of the output from the parallel pseudo-random generation circuit and which outputs a result thereof to a bit error detection output terminal.