Patent ID: 6165868
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A process for monolithic device isolation, comprising:providing a wafer of P- silicon, having upper and lower surfaces;forming shallow trenches, having a width, in said lower surface;over-filling the trenches with a dielectric material and then planarizing so that said trenches are just filled;through a mask, bombarding said upper surface with nuclear particles and then annealing the wafer, whereby transmutation doping occurs in all bombarded areas and conductive isolation moats of N type silicon, extending downwards from said upper surface to the level of the shallow trenches, are formed;forming components for digital and analog integrated circuits in said upper surface, said digital and analog circuits being separated one from another by said moats, and being thereby electrically isolated from one another; anddepositing a metal layer over said lower surface.