Patent ID: 6288568
Filing Date: 2001-09-11
Classification: G11C,H03K

Abstract:
A configurable logic block (CLB) having a plurality configurable logic element (CLE) slices, wherein each of CLE slices comprises:a first function generator (F) having a first write data input terminal;a second function generator (G) having a second write data input terminal;a first multiplexer (1016) having an input terminal coupled to receive a first bypass signal (BX) and an output terminal coupled to the first write data terminal; anda second multiplexer (1010) having an input terminal coupled to receive a second bypass signal (BY), an alternate input terminal (ALTDIG) coupled to receive an alternate input signal, and an output terminal coupled to the second write data terminal, an input terminal of the first multiplexer, and an alternate output terminal (DIG).