Patent ID: 6124143
Filing Date: 2000-09-26
Classification: G01R,H01L

Abstract:
A process monitor structure for an integrated circuit having a core logic portion and a plurality of bond pads, the integrated circuit manufactured in a semiconductor process having at least first and second types of transistors for forming logic gates, the semiconductor process further utilizing multiple layers of interconnect material to form interconnect wires for signal paths between circuit components, the process monitor structure comprising:process monitor circuitry including at least one signal delay path, the process monitor circuitry providing output pulses representative of the relative electrical characteristics of the first type of transistor and the second type of transistor, the output pulses further providing information for detecting process variations in the multiple layers of interconnect material; andsupplemental metal routing line(s) formed of the multiple layers of interconnect material and electrically coupled to and forming a portion of the at least one signal delay path, a substantial portion of the supplemental metal routing line(s) being disposed external to the core logic region of the integrated circuit.