Patent ID: 7923775
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a plurality of trench patterns formed over a substrate, the plurality of trench patterns defining a plurality of trenches; gate insulation layers formed over sidewalls of the trenches; gate electrodes formed in the trenches, wherein the gate electrodes completely fill inner spaces of the trenches on the gate insulation layer; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trenches, wherein when the source region is formed in the upper portion of the substrate, the drain region is formed in the lower portion of the substrate, and when the source region is formed in the lower portion of the substrate, the drain region is formed in the upper portion of the substrate, wherein the source and the drain regions formed in the lower portions of the substrate are buried bit lines, the buried bit lines being not faced with a bottom surface of the gate electrodes and being faced with sidewalls of the gate electrodes.