Patent ID: 9135988
Filing Date: 2015-09-15
Classification: G06F,G11C,H03K

Abstract:
1. A semiconductor device comprising: an instruction decoder configured to decode an instruction read from a storage equipment; one or a plurality of non-volatile registers, each non-volatile register having an address allocated, said each non-volatile register including at least one flip-flop, said flip-flop including: a holding circuit configured to hold data in a volatile manner; and a non-volatile element configured to hold data in a non-volatile manner; and a non-volatile register control circuit configured to control said one or plurality of non-volatile registers, wherein an instruction set decodable by said instruction decoder comprises at least: a write instruction including information specifying an address of said non-volatile register and information specifying writing of data from said holding circuit to said non-volatile element in said non-volatile register; and a load instruction including information specifying an address of said non-volatile register and information specifying loading from said non-volatile element to said holding circuit in said non-volatile register, said non-volatile register control circuit performing control such that, when an instruction decoded by said instruction decoder is said write instruction, data held in said holding circuit is transferred and written to said non-volatile element in said non-volatile register having an address specified by said write instruction, while, when said instruction decoded by said instruction decoder is said load instruction, data held in said non-volatile element is transferred to and held in said holding circuit in said non-volatile register having an address specified by said load instruction.