Patent ID: 7206915
Filing Date: 2007-04-17
Classification: G06F

Abstract:
1. A digital computer comprising at least one processor for producing virtual addresses over a range of virtual addresses, at least one translation buffer coupled to said at least one processor for producing physical addresses from the virtual addresses in accordance with a current virtual-to-physical address mapping, and a random access memory being addressable by the physical addresses and coupled to said at least one processor for supplying data to said at least one processor, wherein the random access memory includes physical memory having a range of physical addresses that is greater than the range of virtual addresses, and the digital computer is programmed with a plurality of different virtual-to-physical address mappings for identical virtual addresses to define a plurality of respective virtual memory spaces having the different virtual-to-physical address mappings for the identical virtual addresses, and wherein the digital computer is programmed with a virtual space manager, the virtual space manager including an allocation routine for responding to an allocation request from an application for allocation of at least one page of the physical memory by returning an indication of said at least one page of the physical memory, and a mapping routine for responding to a mapping request from the application, the mapping request including the indication of said at least one page of the physical memory, the mapping routine being executable by the digital computer for switching the current virtual-to-physical address mapping to a virtual-to-physical address mapping including the indicated said at least one page of the physical memory, and wherein the indication of said at least one page of the physical memory is a cookie, and the digital computer is programmed with a cookie cache of state information on a last page of virtual memory having been mapped into the physical memory.