Patent ID: 6355554
Filing Date: 2002-03-12
Classification: H01L

Abstract:
A method of fabricating an interconnection to an underlying microelectronic layer, the underlying microelectronic layer covered by an insulation layer having a surface opposite the underlying microelectronic layer, the method comprising the steps of:removing a portion of the insulation layer to form a plurality of contact holes therethrough and thereby expose a portion of the underlying microelectronic layer, wherein at least one contact hole of said contact holes has a different contact size than the other contact holes; forming a conductive material on the insulation layer and in the contact holes to a predetermined thickness, such that the conductive material bridges a largest contact hole of the contact holes at the upper side of the largest contact hole forming a void therein; and reflowing the conductive material to thereby fill the contact holes by supplying a high pressure such that at least the void formed in the largest contact hole is filled.