Patent ID: 7565637
Filing Date: 2009-07-21
Classification: G06F,H01L

Abstract:
1. A computer-implemented method of designing a package for a semiconductor device, the method comprising steps of: setting an acceptable noise value of the package, wherein the package includes a package substrate; a signal line formed on an upper surface of the package substrate; a first connection terminal formed on a bottom surface of the package substrate and electrically connected to the signal line; a second connection terminal connected to the signal line and to a chip mounted on the package substrate; and a sealing resin which covers the package substrate and the chip; designing via a computer the signal line layout on the basis of information on connection between the package substrate and the chip; and performing an optimization on the signal line layout so that an amount of noise which occurs due to the signal line remains within the acceptable noise value, wherein the performing the optimization step on the signal line layout includes: analyzing data input to the package and data output from the package; and modifying the signal line layout on the basis of an analysis result obtained in the analyzing process, wherein the analyzing step includes comparing an input waveform input to the second connection terminal with an output waveform output from the first connection terminal and verifying the input waveform and the output waveform.