Patent ID: 6424191
Filing Date: 2002-07-23
Classification: G05F,H03L

Abstract:
In a clock generator circuit having a phase lock loop circuit, a current sink circuit having a stable output current for maintaining a voltage at the input of a voltage controlled oscillator, said current sink circuit comprising:an emitter degeneration resistor coupled to the low side of a supply voltage and coupled to a first node; a transistor device comprising: an emitter coupled to said first node; a collector coupled to an output node; and a base, wherein said current sink circuit supplies current from said output node; an operational amplifier circuit having an output coupled to said base of said transistor device, said operational amplifier circuit also having a first input and a second input, said first input coupled to said first node to provide a feedback loop, said operational amplifier circuit for maintaining constant any current flowing through said transistor device to provide a high output impedance for said current sink circuit, wherein the input voltage to said voltage controlled oscillator is maintained at a stable level; and a bias voltage applied to said second input of said operational amplifier circuit.