Patent ID: 6956776
Filing Date: 2005-10-18
Classification: G06F

Abstract:
1. A buffer memory status detection circuit comprising: a comparator output signal asserted when a sum of a first address pointer value of an embedded first-in, first-out (“FIFO”) memory array plus a first offset pointer value equals a second address pointer value of the embedded FIFO memory array; a first flip-flop set when the comparator output signal is asserted, and having a first data input port, a first data output port, and a first clock port coupled to a first clock signal in a first clock domain; a second flip-flop set when the comparator output signal is asserted and reset when the reset signal is asserted, and having a second data input port, a second data output port, and a second clock port coupled to a second clock signal in a second clock domain; a first inverter coupling the second data output to the first data input; and a second inverter coupling the first data output to the second data input.