Patent ID: 6366989
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A synchronous dynamic random access memory controller comprising:a high speed interface having an input buffer with input entry buffers for receiving transactions, said input buffer having a valid bit for each input entry buffer, said input entry buffers storing transactions received from a high speed bus; and a low speed interface for retrieving transactions from said input buffer, said low speed interface including a memory sequencer that uses said valid bit for each of said input entry buffers to synchronize said high speed interface with respect to said low speed interface, wherein said high speed interface has an input buffer state machine that, after storing one of said transactions in one of said input entry buffers, sets a corresponding input entry buffer valid bit, an output buffer for outputting data to said high speed bus, said output buffer having output entry buffers with output data beat buffers, each output data beat buffer of each output entry buffer having an output data beat buffer valid bit, and an output buffer state machine that, after outputting data in response to a read transaction stored in one of said output entry buffers, resets a corresponding output data beat buffer valid bit, and said memory sequencer initially sets said input entry buffer valid bits and said output data beat buffer valid bits.