Patent ID: 6891915
Filing Date: 2005-05-10
Classification: G06F

Abstract:
1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor 2 k for generating a divided fixed-point output signal, comprising: (a) a signal input for applying the data value sequence of the fixed-point input signal; (b) a first addition circuit which adds the digital data value present at the signal input to a data value temporarily stored in a register to form a first aggregate data value; (c) a shift circuit which shifts the first aggregate data value present by k data bits to the right so that higher-order data bits of the first aggregate data value are delivered at an output of the shift circuit; (d) a logic circuit which logically ANDs the k lower-order data bits of the first aggregate data value with a logical data value in the case of a logically low output control signal of a control logic and logically ORs these bits with an inverted logical data value in the case of a logically high output control signal of the control logic and delivers them to the register for temporarily storing the logically combined data value; (e) a second addition circuit which adds the data value delivered by the shift circuit to one to form a second aggregate data value in the case of a logically high output control signal of the control logic; (f) a signal output for delivering a sequence of the second aggregate data value as the divided fixed-point output signal; (g) the control logic generating an output control signal which is logically high when the first aggregate data value is a negative number which cannot be divided by the dividing factor 2