Patent ID: 7260890
Filing Date: 2007-08-28
Classification: B32B,H01F,H01L,H05K,Y10T

Abstract:
1. A method of fabricating 3-D multilayer interconnect structures, comprising; providing a first organic layer of a first melting point having a first single sided circuitized conductive layer; providing a second organic layer of a second melting point having a second single sided circuitized conductive layer and including at least one metal filled z-axis via connection stud, wherein the first and second melting points are different; capping the z-axis stud of the second organic layer with a high temperature bonding material; and bonding the first organic layer to the second organic layer; wherein the first organic layer having the first single-sided circuitized conductive layer and the second organic layer having the second single-sided circuitized layer are provided prior to the step of bonding, wherein the first organic layer forms a fusion bond with the second organic layer, and the cap on the second organic layer forms a metal to metal bond with the first conductive layer, and wherein the first and second organic layers remain substantially the same prior to and subsequent to the step of bonding.