Patent ID: 8719738
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A system for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each having shape corners at respective locations in the layout, the system comprising: a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the computer system further having access to computer instructions and data which, when applied to the computer system, perform the steps of: traversing a plurality of shape corners of shapes in the region; for each particular one of the traversed shape corners, populating a layout topology database with an association between (1) an identification of the particular shape corner and (2) one or more particular values which depend upon the particular shape corner location; comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules; and where a design rule violation is detected, reporting it to a user.