Patent ID: 6085295
Filing Date: 2000-07-04
Classification: G06F

Abstract:
In a computer system having a plurality of interconnected shared memory multiprocessor nodes, each of said nodes having at least one processor and a memory, a method of providing coherent shared memory access from any of said processors to any of said memories of said system, said method comprising:a. for each line of data in each memory of each node, maintaining a list of those of said processors of said node that have said line in their caches;b. if a memory command is issued from one of said processors of one of said nodes, and if said command is directed to a memory of another node of said system, then sending said memory command directly to an adapter of said one node;c. when said adapter receives said command, forwarding said command from said adapter to another adapter of said other node;d. when said other adapter receives said command, forwarding said command from said other adapter to a local memory of said other node;e. updating said list of processors in said local memory of said other node to include or exclude said other adapter.f. if a memory command is issued from one of said processors of one of said nodes, and if said command is directed to a memory of latter said one node, then sending said memory command directly to said local memory;g. when said local memory receives said command, and if an adapter of latter said one node is in said list of processors for a line associated with latter said command, then forwarding said command to latter said adapter;h. when latter said adapter receives said command, forwarding said command to one or more adapters of remote nodes which have cache copies of said line; andi. when said adapters of remote nodes receives said command, forwarding said command to one or more processor of said remote nodes.