Patent ID: 6316309
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of forming a semiconductor device comprising the steps of:forming an array of pillars in a substrate of semiconductor material, said array of pillars being arranged in rows and columns and being separated by trenches;forming a trench capacitor or a pair of trench capacitors around each of said pillars in a lower portion of each of said trenches separating said pillars, said trench capacitor or a pair of trench capactiors including an adjoining out-diffused source region;forming a transistor in an upper portion of each of said trenches, said transistor being formed on top of a collar region, said collar region dielectric separating said lower and upper portions of each of said trenches, or in a recessed area above and between one of said pair of trench capacitors; andforming a drain region on top of each pillar.