Patent ID: 6642081
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method for adding a second circuit layer to a first wafer comprising a first circuit layer, said method comprising the steps of:providing a plurality of bonding pads on a first surface of said first wafer; providing a second wafer comprising a substrate of a wafer material and said second circuit layer, said second circuit layer being fabricated on a first surface of said substrate and being covered by a layer of dielectric material, said wafer further comprising a plurality of vias extending a predetermined distance from said first surface of said substrate into said substrate, said vias including a layer of stop material, said stop material being more resistant to CMP than said wafer material; providing a plurality of bonding pads on said second wafer, there being a one to one correspondence between said bonding pads on said first and second wafers; positioning said first and second wafers such that said bonding pads on said first wafer are brought in contact with said bonding pads on said second wafer; causing said corresponding bonding pads to bond to one another; and thinning said second wafer by removing a portion of said second wafer by CMP of the surface of said second wafer that is not bonded to said first wafer, said stop layer in said vias determining the amount of material that is removed, wherein said vias are filled with a conducting material thereby forming a plug extending from said surface of said second wafer having said bonding pads to said stop layer and wherein said step of thinning said second wafer leaves a portion of said plugs elevated above said surface of said second wafer remaining after removing said portion of said second wafer.