Patent ID: 6124760
Filing Date: 2000-09-26
Classification: H03F

Abstract:
A transconductance control circuit, comprising:a differential input terminal wherein first and second differential MOS transistor pairs are parallel connected;a first current source for providing a first bias current, the first current source includinga first PMOS transistor having a source thereof connected to a supply voltage terminal, anda second PMOS transistor having a source thereof connected to a drain of the first PMOS transistor, a first bias voltage applied through a gate thereof, and a drain thereof connected in common to a gate of the first PMOS transistor and respective sources of the first differential MOS transistor pair; anda second current source for providing a second bias current, the second current source includinga first NMOS transistor having a drain thereof connected to respective sources of the second differential MOS transistor pair, and a second bias voltage applied to a gate thereof, anda second NMOS transistor having a drain thereof connected to a source of the first NMOS transistor, a gate thereof connected to a drain of the first NMOS transistor, and a source thereof connected to ground.