Patent ID: 6653233
Filing Date: 2003-11-25
Classification: H01L

Abstract:
A process of providing a semiconductor device with electrical interconnection capability comprising the steps of:(a) depositing an electrically conductive seed layer on a semiconductor device provided with topographical features; (b) depositing a sacrificial material selected from the group consisting of perfluoroacrylate, a paraffin wax, nylon, polybutene, polydimethylsiloxane, copolymers of dimethyl siloxane and methyl methacrylate and mixtures thereof, soluble in liquid or supercritical carbon dioxide, on said semiconductor device, (c) polishing the surface of said semiconductor device with a chemical mechanical polish wherein said seed layer and said sacrificial material is removed from all but topographical features of said semiconductor device and; (d) contacting said semiconductor device with a material selected from the group consisting of liquid carbon dioxide and supercritical carbon dioxide wherein said sacrificial material is removed from said topographical of said semiconductor device.