Patent ID: 6787817
Filing Date: 2004-09-07
Classification: H01L

Abstract:
A semiconductor device in which on a semiconductor substrate, a buffer layer, a channel layer, a first conductivity type carrier providing layer and a barrier layer are formed from the side of the semiconductor substrate, and a source electrode, a drain electrode, a gate electrode between said source electrode and said drain electrode, an ohmic layer connected electrically to said source electrode, and an ohmic layer connected electrically to said drain electrode are formed, wherein a region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are formed from said gate electrode side at the side far from said semiconductor substrate of the end surface of said barrier layer opposite said semiconductor substrate and between said ohmic layer and said gate electrode, the sheet impurity concentration of said region including a low impurity concentration semiconductor is lower than that between the bottom surface of said gate electrode at the side of said semiconductor substrate and the end surface of said channel layer opposite said semiconductor substrate, the sheet impurity concentration of said region including a high impurity concentration semiconductor is higher than that of said region including a low impurity concentration semiconductor, and said region including a high impurity concentration semiconductor and said region including a low impurity concentration semiconductor are formed consecutively between one end surface of an operating region of the semiconductor device and the other end surface facing the end surface, respectively.