Patent ID: 6510070
Filing Date: 2003-01-21
Classification: G06F,G11C

Abstract:
In a semiconductor memory device having word lines, rows of memory cells coupled to respective word lines, sense lines, sense amplifiers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of refreshing said memory cells, comprising the steps of:receiving a row address corresponding to data stored in said cache cells; transferring said data from said cache cells via said column data lines to said sense lines, and amplifying the data thus transferred; disconnecting said column data lines from said sense lines, thereby leaving amplified data on said column data lines; activating a first word line after said disconnecting; using said sense amplifiers to refresh the memory cells coupled to said activated first word line; and receiving at least one column address and transferring data between corresponding column data lines and said data bus, while said sense amplifiers are refreshing said memory cells.