Patent ID: 7141854
Filing Date: 2006-11-28
Classification: H01L

Abstract:
1. A double-gated transistor structure, comprising: a) a substrate having an SOI structure formed thereover; the SOI structure including a lower SOI oxide layer and an upper patterned, rounded SOI silicon layer; the upper patterned, rounded SOI silicon layer including side walls, a source region portion and a drain region portion connected by a channel portion; b) a gate area within the lower SOI oxide layer and the upper patterned, rounded SOI silicon layer; c) a top patterned oxide layer over the upper patterned, rounded SOI silicon layer; the top patterned oxide layer not being over a top portion of the upper patterned, rounded SOI silicon layer within the gate area; d) a rounded oxide layer over a portion of the side walls of the patterned upper SOI silicon layer; e) an undercut in the lower SOI oxide layer defining a bottom portion of the patterned, rounded upper SOI silicon layer within the gate area; f) a conformal oxide layer over: and g) a gate within the gate area; the gate including an upper gate portion above the patterned, rounded upper SOI silicon layer, and a lower gate portion under the patterned, rounded upper SOI silicon layer.