Patent ID: 8161247
Filing Date: 2012-04-17
Classification: G06F

Abstract:
1. In a computing environment, a method of detecting memory accesses by other agents, the method comprising: a thread executing a processor level instruction included as part of an instruction set architecture for a processor, setting a read, or write monitor to detect writes, or reads or writes respectively by other agents on a first set of one or more memory locations in a cache local to a processor for the thread; the thread executing a processor level instruction included as part of an instruction set architecture for a processor, setting a read, or write monitor to detect writes, or reads or writes respectively on a second set of one or more different memory locations in a cache local to a processor for the thread; adding read and write monitoring indicator states to a cache state for each cache line in the cache; the thread executing a processor level instruction included as part of an instruction set architecture for a processor which causes the thread to suspend execution of instructions pending loss of a read or write monitor for the first or second set of one or more memory locations; the thread suspending execution of instructions whereby a processor for the thread enters a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations, including causing the processor to enter a low power mode without causing the cache control hardware to enter a low power mode; detecting a conflicting access on the first or second set of one or more memory locations using a cache coherence system for the cache or detecting a timeout; and as a result of detecting a conflicting access or detecting the timeout, the thread resuming execution of instructions.