Patent ID: 7617353
Filing Date: 2009-11-10
Classification: G06F,G11C

Abstract:
1. A flash memory circuit, wherein said circuit access an IDE apparatus, comprising: a flash memory controller for outputting a latch signal, a writing signal, a reading signal and a data, wherein said flash memory controller comprises a firmware, said firmware sets a clock signal for accessing said IDE apparatus equal to clock signal of said flash memory, and sets a special access count and a special access address; a latch circuit controlled by said latch signal, wherein said latch signal controls said latch circuit to access a special address, and said special address is latched in said latch circuit; and an IDE apparatus controlled by said writing signal or said reading signal, wherein said writing signal controls said IDE apparatus for writing said data to said IDE apparatus according to said special address, and said reading signal controls said IDE apparatus for reading said data from said IDE apparatus according to said special address.