Patent ID: 6072711
Filing Date: 2000-06-06
Classification: G11C,H01L

Abstract:
A ferroelectric memory device, comprising:first and second control lines insulatively formed over first and second active regions of a semiconductor substrate in a first direction, the first and second active regions being isolated from each other;first electrode regions formed in the first active region on both sides of the first control line and second electrode regions formed in the second active region on both sides of the second control line;a first ferroelectric layer formed over the first and second control lines;a first conductor connected to one of the second electrode regions of the second active region and formed on the first ferroelectric layer formed over the first control line;a second conductor connected to one of the first electrode regions of the first active region and formed on the first ferroelectric layer formed over the second control line; andfirst and second bit lines formed in a second direction, the first bit line being connected to the other one of the first electrode regions formed in the first active region, the second bit line being connected to the other one of the second electrode regions formed in the second active region.