Patent ID: 7325211
Filing Date: 2008-01-29
Classification: G06F

Abstract:
1. A method for determining clock skew to avoid hold time violations, comprising: obtaining a total delay from a clock generator to a source by adding a first delay associated with each delay element in a clock tree path leading to the source; obtaining a total delay from the clock generator to a destination by adding a second delay associated with each delay element in a clock tree path leading to the destination; obtaining a source sum delay of the delay elements in the clock tree path from the source to a common point; obtaining a destination sum delay of the elements in the clock tree path from the destination to the common point; subtracting the source sum delay from the total delay to the source to obtain an actual delay to the source; subtracting the destination sum delay from the total delay to the destination to obtain an actual delay to the destination; and obtaining a skew value by subtracting the actual delay to the source from the actual delay to the destination, wherein the source is a memory element from which data are transferred and the destination is a memory element, which receives the transferred data from the source, and the common point is a closest common point from the source and the destination in the clock tree path between the clock generator and the source, and the clock generator and the destination.