Patent ID: 6107140
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of patterning a gate electrode, comprising the steps of:providing a semiconductor structure, with an upper silicon layer, and having: an active area; a sacrificial silicon oxide layer overlying said semiconductor structure; a first polysilicon layer overlying said sacrificial silicon oxide layer; and a silicon nitride layer overlying said polysilicon layer;patterning said silicon nitride, first polysilicon, and sacrificial oxide layers to form a gate conductor opening within said active area and to expose sidewalls of said polysilicon layer;growing a gate oxide layer over the semiconductor structure within said gate conductor opening and over the exposed sidewalls of said first polysilicon layer;depositing a second polysilicon layer over the structure, filling said gate conductor opening;polishing said second polysilicon layer to remove the excess of said second polysilicon layer from said nitride layer, forming a polysilicon gate conductor within said gate conductor opening and over said gate oxide layer; said polysilicon gate conductor having an exposed upper surface;oxidizing said exposed upper surface of said polysilicon gate conductor to form a hard mask oxide layer over said polysilicon gate conductor;etching and removing said nitride layer from said first polysilicon layer;etching and removing said first polysilicon layer from said semiconductor structure; andetching and removing said hard mask oxide layer and said gate oxide sidewalls thereby exposing the side walls of said polysilicon gate conductor.