Patent ID: 8069444
Filing Date: 2011-11-29
Classification: G06F

Abstract:
1. A method for achieving fair cache memory sharing in a processor having a plurality of cores, each of which has a thread running thereon, and a cache memory that is shared by the threads, the method comprising: allotting a respective CPU time quantum to each of the threads, wherein the CPU time quantum allotted to each thread is the share of CPU time allotted for the thread to run on the processor; computing for a given one of the threads a fair CPU latency value as a product of a value representing the number of thread cycles per instruction (CPI) which the given thread would experience in the case that the cache memory was equally shared by the threads and the CPU time quantum that was allotted to the given thread; computing an actual CPU latency value as a product of the actual number of thread cycles per instruction which the given thread is currently experiencing and the CPU time quantum that was allotted to the given thread; and performing an adjustment to the CPU time quantum allotted to the given thread, wherein the adjustment causes the actual CPU latency value of the given thread to become equal to the computed fair CPU latency value.