Patent ID: 8559247
Filing Date: 2013-10-15
Classification: G11C

Abstract:
1. A circuit comprising: a precharge circuit coupled to receive a clock signal, wherein the precharge circuit is configured to precharge an evaluation node to a first logic level during a first phase of the clock signal; a pull-down circuit having an input node coupled to receive an input signal, wherein the pull-down circuit is configured to, during a second phase of the clock signal, provide a pull-down path between the evaluation node and a ground node responsive to receiving the input signal at the first logic level; and a keeper circuit, wherein the keeper circuit is configured to, during the second phase of the clock signal, hold the evaluation node at the first logic level responsive to the input node receiving the input signal at a second logic level; wherein the first logic level, on the input node, is referenced to a first supply voltage, and wherein the first logic level, on the evaluation node, is referenced to a second supply voltage.