Patent ID: 8686758
Filing Date: 2014-04-01
Classification: H03K

Abstract:
1. An I/O circuit, comprising: a first transistor having a drain coupled to a first switch, wherein the first switch selectively couples the first transistor to one of an I/O pin or one of a plurality of inputs of a second switch, wherein the first switch includes a single input and multiple outputs, and wherein the second switch includes a single output; a second transistor, wherein a source of the second transistor is coupled to the single output of the second switch, wherein the second switch selectively couples the second transistor to the first transistor through the one of the plurality of inputs of the second switch and the first switch; a third transistor having a source coupled to the I/O pin and a drain coupled to a third switch, wherein the third switch selectively couples the third transistor to one of a ground potential through a first output of the third switch or a first input of a fourth switch through a second output of the third switch, so that the third and fourth switches are configured for being selectively in series with one another; and a fourth transistor having a source coupled to an output of the fourth switch, wherein the fourth switch selectively couples the fourth transistor to one of the I/O pin or the third transistor.