Patent ID: 8788796
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. A Reduced Instruction Set Computing (RISC) processor comprising: a floating-point register file containing a plurality of floating-point registers, a decoding section for decoding operation instructions of the RISC processor, and a floating-point operation section connected to the decoding section for reading and writing the floating-point register file according to an output value of the decoding section so as to perform a floating-point operation, wherein: the decoding section includes a pointer register for maintaining a stack operation pointer and storing a value of the stack operation pointer, the floating-point operation section includes a pointer operation module, which operates the pointer register so as to emulate a stack operation of the stack operation pointer, and modify and monitor a status of the stack operation pointer when a floating-point register stack operation is emulated, the RISC processor includes a control register for controlling the status of the floating-point registers and controlling the decoding section and the floating-point operation section to emulate the floating-point register stack operation using the floating-point register file, the control register maintains a stack enable bit, wherein the stack enable bit denotes that the RISC processor will emulate the floating-point register stack operation when the stack enable bit is set to 1, and that the RISC processor will not emulate the floating-point register stack operation when the stack enable bit is set to 0, and the value of the stack operation pointer is n, and in the case of the stack enable bit being 1: