Patent ID: 6564360
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A method of setup time check in a static timing analysis for judging whether a timing violation occurs on a logic circuit, said logic circuit having a first sequential logic gate for receiving a first input signal and a first clock signal, and exporting a first signal at a first output terminal, wherein said first clock signal is a primary clock or a defined clock that is defined from said primary clock; a second sequential logic gate for receiving a second input signal and a second clock signal, and exporting a second signal at a second output terminal, wherein said second clock signal is a primary clock or a defined clock that is defined from said primary clock; a combinatorial logic circuit unit, including a plurality of logic gates, said combinatorial logic circuit unit is used to receive said first signal and said second signal, and export a third signal and a fourth signal; and a third sequential logic gate, including a signal input terminal, a clock input terminal, and a third output terminal, wherein a plurality of first signal propagation paths included between said signal input terminal and said first output terminal, a plurality of second signal propagation paths included between said clock input terminal and said second output terminal, said signal input terminal is used to receive said third signal, and said clock input terminal is used to receive said fourth signal, wherein said third sequential logic gate has a setup time; said method of setup time check comprising:finding out one of said first signal propagation paths, which has a maximum sum of propagation delay time for said logic gates, said maximum sum of propagation delay time for said logic gates is a first maximum delay time; finding out one of said second signal propagation paths, which has a minimum sum of propagation delay time for said logic gates, said minimum sum of propagation delay time for said logic gates is a first minimum delay time; and judging whether said first maximum delay time is less than said first minimum delay time subtracted by said setup time of said third sequential logic gate, wherein if it is, then said first signal propagation paths and said second signal propagation paths have passed a setup time check in a static timing analysis.