Patent ID: 6088781
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A microprocessor comprising:a first unit coupled to receive a stride instruction, wherein said first unit is configured to decode said stride instruction, said stride instruction having at least a base address operand, a stride operand, and a repetition count operand; anda second unit coupled to receive said stride instruction from said first unit, wherein said second unit is configured to execute a plurality of load memory operations in response to a particular execution of said stride instruction, and wherein a number of said plurality of load memory operations is specified by said repetition count operand of said stride instruction, and wherein said second unit is configured to generate a first address corresponding to a first load memory operation of said plurality of load memory operations from at least said base address operand, and wherein said second unit is configured to add said stride operand to said first address to generate a second address corresponding to a second load memory operation of said plurality of load memory operations.