Patent ID: 6016561
Filing Date: 2000-01-18
Classification: G11C

Abstract:
A memory system operable in a normal mode of operation and a test mode of operation, comprising:sewning circuitry which generates x number of data bits during a read cycle;a detection circuit which detects a first pattern among the x number of data bits;an output circuit which generates y number of output data bits in reponse to the detected first pattern, which is less than the x number, which are arranged in a second pattern which is indicative of the first pattern detected by the detection circuit; anda read path circuit, coupled to the sag circuitry, the detection circuit and the output circuit, which transfers the x number of data bits to x number of output nodes in a first read cycle operating in the normal mode of operation and which transfers the y number of output data bits to y number of output nodes in a second read cycle operating in the test mode of operation.