Patent ID: 6055623
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode method for setting and testing conditions with specialized update and branch instructions comprising the steps of: storing in an internal code array milli-mode routines as said set of millicode simple instructions, and when milli-mode detection logic coupled to instruction registers of said processor detects that a macro-instruction, which is being decoded, is of a type that is to be interpreted in said milli-mode architected operating state then said milli-mode architected state is enabled with a milli-mode recognition signal and macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers, whereupon a milli-mode entry point address is generated to address the millicode stored in said internal code array which are fetched from said internal code array and sent to said processor instruction registers whereupon the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode, and whereupon on entry to a milli-mode millicode routine one or more millicodes provide an editing function in which the editing function instruction for an ESA/390 Edit or Edit and Mark instruction processes one byte of an input pattern string, generating one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string; andwherein the editing function instruction for processing the next byte in a string provides that a single byte is processed for an ESA/390 Edit or Edit and Mark instruction and the processor's MGR pair R&sub2. register contains the pattern byte to be processed (from operand 1 of the ED or EDMK) in bits 16:23; the fill byte in bits 8:15; and the next operand 2 byte from the ED or EDMK in bits 56:63 (i.e. bits 24:31 of MGR R&sub2.+1) and in which the result byte generated is placed in bits 24:31 of MGR R&sub1. by the editing function instruction.