Patent ID: 6731144
Filing Date: 2004-05-04
Classification: G11B,H03L

Abstract:
A delay lock loop circuit comprising:a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data; an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, said sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of said third pulse data and, when said count value has reached said maximum value and said minimum value, setting a next count value to said initial value, said up/down counter executing a count-up operation at a rising edge of said third pulse data when said count value of said sub counter is said maximum value and a count-down operation when said count value is said minimum value; a delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter; a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal; and a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count.