Patent ID: 6686771
Filing Date: 2004-02-03
Classification: H03F,H03K

Abstract:
A differential circuit comprising in combination:a. first and second power supply conductors for conducting first and second power supply voltages, respectively, defining an operating voltage range; b. a negative input terminal for receiving a first voltage within the operating voltage range; c. a positive input terminal for receiving a second voltage within the operating voltage range; d. first and second CMOS transistors each having drain, source, and gate terminals, the gate terminal of the first CMOS transistor being coupled to the negative input terminal, and the gate terminal of the second CMOS transistor being coupled to the positive input terminal; e. a first level shift circuit coupled to the negative input terminal for receiving the first voltage and producing a first level-shifted voltage, the first level-shifted voltage being at least partially responsive to the first voltage, the first level-shifted voltage being less than the first voltage; f. a second level shift circuit coupled to the positive input terminal for receiving the second voltage and producing a second level-shifted voltage, the second level-shifted voltage being at least partially responsive to the second voltage, the second level-shifted voltage being less than the second voltage; g. a third CMOS transistor having source, gate, and drain terminals, the drain terminal thereof being coupled to the source terminal of the first CMOS transistor, the gate terminal thereof being coupled to the first level shift circuit for receiving the first level-shifted voltage, the source terminal of the third CMOS transistor conducting a current conducted by the source terminal of the first CMOS transistor; h. a fourth CMOS transistor having source, gate, and drain terminals, the drain terminal thereof being coupled to the source terminal of the second CMOS transistor, the gate terminal thereof being coupled to the second level shift circuit for receiving the second level-shifted voltage, the source terminal of the fourth CMOS transistor conducting a current conducted by the source terminal of the second CMOS transistor; i. a fifth CMOS transistor having source, gate and drain terminals, the source terminal thereof being coupled to the drain terminal of the first CMOS transistor, and the gate terminal thereof being coupled to the first level shift circuit for receiving the first level-shifted voltage; and j. a sixth CMOS transistor having source, gate and drain terminals, the source terminal thereof being coupled to the drain terminal of the second CMOS transistor, the gate terminal thereof being coupled to the second level shift circuit for receiving the second level-shifted voltage, and the drain terminal thereof being coupled in common to the drain terminal of the fifth CMOS transistor; and k. a source of a reference current coupled between one of the power supply conductors and the common drain terminals of the fifth and sixth CMOS transistors.