Patent ID: 6445621
Filing Date: 2002-09-03
Classification: G11C

Abstract:
In a data memory circuit, a method for level shifting first and second bit data signals for output on first and second latch nodes of a latching circuit having a first and second capacitance, respectively, comprising:providing a first data line, having a greater capacitance than said first capacitance, for selective connection to the first latch node; providing a second data line, having a greater capacitance than said second capacitance, for selective connection to the second latch node; isolating the first and second data lines from the respective first and second latch nodes; selectively connecting said latching circuit to first and second voltage sources, said first voltage being of magnitude being greater than the magnitude of said second voltage; equalizing said first and second data lines to a third voltage magnitude, said third voltage being less than said first voltage magnitude and greater than said second voltage; disconnecting said latching circuit from said first and second voltage sources; connecting said first and second latch nodes to said first and second data lines, respectively; and providing said first and second bit data signals to said first and second latch nodes, and disconnecting said first and second latch nodes from said first and second data lines, and connecting said latch to said first and second voltage sources and driving one of said first and second latch nodes to said first voltage magnitude greater than said third voltage magnitude and driving the other of said first and second latch nodes to a second voltage magnitude less than said third voltage magnitude, based upon the relative magnitudes of said first and second bit data signals.