Patent ID: 8252680
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A process comprising: forming a recess in a dielectric layer, wherein the dielectric layer is disposed above and on a first interconnect, wherein the recess includes a feature wall and a feature bottom, and wherein forming the recess exposes at least a portion of the first interconnect at the feature bottom; and forming a liner structure in the recess under conditions to remove the liner structure from the feature bottom and to expose the first interconnect at an upper surface thereof, and wherein forming the liner structure includes: forming a barrier first layer in the recess to cover the feature wall and the feature bottom; forming a liner second layer in the recess to cover the barrier first layer; applying a radio frequency (RF) bias under conditions to remove the barrier first layer and the liner second layer from the feature bottom; forming a seed third layer in the recess to cover the liner second layer and the feature bottom; and applying an RF bias under conditions to remove the seed layer from the feature bottom and to expose the first interconnect at an upper surface thereof.