Patent ID: 7898991
Filing Date: 2011-03-01
Classification: G06F,H03M,H04J,H04L

Abstract:
1. A multiplexing stage, comprising: a plurality of input demultiplexers configured to demultiplex a plurality of parallel data signals into a plurality of demultiplexed signals; a plurality of synchronizing flip flops, each coupled to a different one of the plurality of input demultiplexers and configured to receive and synchronize the plurality of demultiplexed signals into a plurality of retimed signals; one or more output multiplexers coupled to the synchronizing flip flops and configured to sample the plurality of retimed signals in a pre-defined order to generate one or more serial data signals therefrom; and means for deterministically mapping the plurality of parallel data signals to the one or more serial data signals, the means for deterministically mapping being coupled between the one or more output multiplexers and at least one of the plurality of synchronizing flip flops, wherein the means for deterministically mapping includes a first plurality of static multiplexers coupled between the one or more output multiplexers and a first synchronizing flip flop, the first plurality of static multiplexers configured to select either a test signal or a first set of the plurality of demultiplexed signals for inclusion in the one or more serial data signals.