Patent ID: 6829178
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory array including a plurality of nonvolatile memory elements; a counter circuit that counts a fail count in a write operation or in an erase operation; a register that sets an allowable value of the fail count; a comparison circuit that compares said allowable value with said fail count; and a plurality of external terminals, wherein each of said nonvolatile memory elements is capable of storing information by executing said write operation or by executing said erase operation, wherein a first external terminal of said plurality of external terminals is for inputting a command code that specifies an arbitrary one of operations of said nonvolatile semiconductor memory device, wherein said write operation is specified by inputting a first command code from said first external terminal, and said erase operation is specified by inputting a second command code from said first external terminal, wherein when said fail count has exceeded the allowable value, neither of said write operation nor said erase operation are executed, even if said first command code or said second command code is input from said first external terminal, wherein an address signal is input from said first external terminal, wherein a second external terminal of said plurality of external terminals inputs a control signal which indicates whether the first external terminal is a inputting said command code or said address signal, and wherein an input of said control signal inputted from said second external terminal is inhibited by an output signal of said comparison circuit.