Patent ID: 6337240
Filing Date: 2002-01-08
Classification: H01L,Y10S

Abstract:
A method for fabricating an embedded dynamic random access memory (DRAM) on a semiconductor substrate, having a DRAM region and a periphery region, the method comprising:forming a first oxide layer and a second oxide layer on the substrate respectively at the DRAM region and the periphery region, wherein a thickness of the first oxide layer is different from a thickness of the second oxide layer; forming a polysilicon layer over the substrate; sequentially forming a silicide layer and a cap layer on the polysilicon layer at the DRAM region; patterning the cap layer, the silicide layer, the polysilicon layer, and the first oxide layer to form a first gate structure at the DRAM region, and simultaneously patterning the polysilicon layer and the second oxide layer to form a second semi-gate structure at the periphery region; implanting ions onto the substrate, using the first gate structure and the second semi-gate structure as a mask, to form a first lightly doped region in the substrate at the DRAM region and a second lightly doped region in the substrate at the periphery region; forming a first spacer on each sidewall of the first gate structure, and a second spacer on each sidewall on each sidewall of second semi-gate structure; implanting ions onto the substrate, using the first gate structure, the first spacer, the second semi-gate structure, and the second spacer as a mask, to form a first heavily doped region in the substrate at the DRAM region and a second heavily doped region in the substrate at the periphery region, wherein the first lightly doped region and the first heavily doped region serve as a first interchangeable source/drain region, and the second lightly doped region and the second heavily doped region serve as a second interchangeable source/drain region, forming an insulating layer over the substrate at the DRAM region; performing a self-aligned silicide (Salicide) process to form a first Salicide layer on the second semi-gate structure and a second Salicide layer on the second interchangeable source/drain region, wherein the first Salicide layer and the second semi-gate structure form a second gate structure at the periphery region; and forming a capacitor, which is electrically coupled to the first interchangeable source/drain region at the DRAM region.