Patent ID: 9006841
Filing Date: 2015-04-14
Classification: G11C,H01L

Abstract:
1. A structure for an SRAM memory cell comprising a substrate; a first active area that is physically isolated from all other active areas in the memory cell, the first active area being part of a first data storage node and a drain region of a first transistor; a second active area that is physically isolated from all other active areas in the memory cell, the second active area being part of a second data storage node and a drain region of a second transistor; a third active area that is physically isolated from all other active areas in the memory cell, the third active area forming part of the first data storage node and a drain region of a third transistor; a fourth active area that is physically isolated from all other active areas in the memory cell, the fourth active area being part of the second data storage node and drain region of a fourth transistor; a fifth active area that is part of the first data storage node and is common physical area shared by a fifth and sixth transistor; a sixth active area that is part of the second data storage node and is common physical area shared by a seventh and eighth transistor, the first active area at least partially disposed between the third active area and the sixth active area; a first metal layer that electrically connects the first, third and fifth active areas to form the first data storage node; and a second metal layer that electrically connects the second, fourth and sixth active areas to form the second data storage node.