Patent ID: 7936072
Filing Date: 2011-05-03
Classification: H01L

Abstract:
1. A semiconductor device having multilayer wirings of a dual damascene structure, comprising: a first wiring layer formed on a semiconductor substrate; and a second wiring layer formed on the first wiring layer, wherein the first wiring layer includes a first insulation film, a plurality of first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to the plurality of first vias in the second insulation film, wherein the second wiring layer includes a third insulation film, a plurality of second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to the plurality of second vias in the fourth insulation film, wherein an aspect ratio L of the wiring having a minimum wiring width of the first wiring layer and an aspect ratio V of the vias in the first wiring layer are in a relationship of L≧V, and wherein the aspect ratio L of the wiring having the minimum wiring width of the second wiring layer and the aspect ratio V of the vias in the second wiring layer are in a relationship of L<V.