Patent ID: 9213679
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A device with a capability of processing a Fast Fourier Transform (FFT) radix 2 butterfly operation, comprising a plurality of latches, a complex multiplier, a complex adder-subtractor, a plurality of switches and a complex conjugate Arithmetic Logical Unit (ALU), wherein: the complex conjugate ALU is configured to convert input data X into a conjugate of the input data X; a fourth switch is configured to select between the input data X and the conjugate of the input data X to output the selected data; a first switch is configured, under control of an external control signal, to select between the input data X and the conjugate of the input data X to send to one of a first latch, a second latch and a third latch in each clock to temporarily store the sent data; the complex multiplier is configured to have two inputs of which one is from the first latch and another is from a second switch, wherein data generated by the complex multiplier is output to a fifth latch to be latched; the second switch is configured, under control of an external control signal, to select between output data of the second latch and a complex constant 1.0 to input to the complex multiplier; the complex adder-subtractor is configured to have two inputs of which one is from the fifth latch and another is from a third switch; the third switch is configured to have three inputs which respectively are from output of the third latch, output of a fourth latch and a complex constant 0.0, and the third switch is configured, under control of an external control signal, to select one input to transmit the selected input to the complex adder-subtractor; and the fourth latch is configured to store output of the complex adder-subtractor, and to form an accumulator together with the complex adder-subtractor; wherein output of the fourth latch is output Y of the device.