Patent ID: 8772865
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. An MOS transistor comprising: a semiconductor substrate having a surface; an active region of the MOS transistor; a plurality of active trenches formed in the semiconductor substrate and within the active region wherein each active trench of the plurality of active trenches includes a shield conductor and an overlying gate conductor; a source region formed as a first doped region on the surface of the semiconductor substrate adjacent to each active trench; a termination region that is external to the active region; a shield contact trench formed in the semiconductor substrate and within the termination region, the shield contact trench having a first conductor within the shield contact trench; a gate contact trench formed in the semiconductor substrate and positioned near both the shield contact trench and at least one active trench of the plurality of active trenches, the gate contact trench having a second conductor within the gate contact trench and wherein no source region is adjacent to the gate contact trench; a source conductor overlying the plurality of active trenches and forming electrical contact to the source region of each active trench of the plurality of active trenches; a third conductor overlying the shield contact trench and forming electrical contact to the first conductor; and a fourth conductor overlying the gate contact trench and forming electrical contact the second conductor wherein the third conductor and the fourth conductor are substantially coplanar not electrically connected together.