Patent ID: 7071546
Filing Date: 2006-07-04
Classification: H01L,Y10T

Abstract:
1. A chip stack for forming a circuit of a plurality of integrated circuits formed on discrete semiconductor substrates, said chip stack comprising: a first semiconductor substrate having first and second faces and an integrally formed first integrated circuit having one or more interconnection pads formed proximate to said first face of said first semiconductor substrate, wherein said first semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said first semiconductor substrate, electrically conductive vias that pass internally in a step-wise manner from said first face to said second face of said first semiconductor substrate, and electrically conductive vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first semiconductor substrate; a second semiconductor substrate having first and second faces and an integrally formed second integrated circuit having one or more interconnection pads formed proximate to said first face of said second semiconductor substrate, wherein said second semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said second semiconductor substrate, electrically conductive vias that pass internally in a step-wise manner from said first face to said second face of said second semiconductor substrate, and electrically conductive vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second semiconductor substrate; one or more of said interconnection pathways from said first semiconductor substrate to said second semiconductor substrate enable electrical interconnections between said first integrated circuit to said second integrated circuit when said first and second semiconductor substrates are vertically stacked; and wherein at least one of said interconnection pathways is comprised of an electrically conductive via that passes internally through at least one of said semiconductor substrates in a step-wise manner.