Patent ID: 6383863
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of fabricating a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of:providing insulator capped gate structures on an underlying gate insulator layer, with source/drain regions located in portions of said semiconductor substrate not covered by said insulator capped gate structures; forming a planarized first composite insulator layer; forming a capacitor opening and a bit line contact opening in said planarized first composite insulator layer, with said capacitor opening, and said bit line contact opening, self-aligned to said insulator capped gate structures, and exposing top portions of said source/drain regions; forming a capacitor structure in said capacitor opening, and a bit line contact structure in said bit line contact opening; removing a top insulator layer component of said planarized first composite insulator layer, forming insulator spacers from said top insulator layer component on the sides of a top portion of said capacitor structure and of on the sides of a top portion of said bit line contact structure; removing exposed portions of capping insulator layers from portions of said insulator capped gate structures, exposing conductive gate layer component of said insulator capped gate structures, exposed between said capacitor structure and said bit line contact structure; forming a metal silicide layer on exposed portions of said conductive gate layer, and to form a metal silicide layer on top surface of said capacitor structure and on top surface of said bit line contact structure; forming a second planarized composite insulator layer; forming a first opening in said planarized second composite insulator layer exposing a portion of a metal silicide layer overlying said conductive gate layer component, and forming a second opening in said planarized second composite insulator layer exposing a portion of a metal silicide layer located overlying said bit line contact structure; and forming metal plug structures in said first opening, and in said second opening in said planarized second composite insulator layer.