Patent ID: 6403478
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of via formation in the manufacturing of an integrated circuit device comprising:providing semiconductor device structures in and on the substrate of a semiconductor wafer wherein said semiconductor device structures include gate electrodes, source and drain regions and metal interconnection lines; depositing a dielectric layer overlying said semiconductor device structures; etching a via opening through said dielectric layer to contact one of said metal interconnection lines; loading said wafer into a deposition chamber and warming said wafer to a temperature of between 370Â° C. and 380Â° C. at a pressure between 2 and 3 Torr wherein said temperature not greater than 380Â° C. prevents protrusion of said metal interconnection line into said via opening; thereafter conformally depositing a barrier layer within said via opening wherein the temperature of said wafer remains at or below 380Â° C. wherein said temperature not greater than 380Â° C. prevents protrusion of said metal interconnection line into said via opening; depositing a first metal layer overlying said barrier layer and filling said via opening; annealing said first metal layer; and etching said first metal layer to leave a metal plug within said via opening thereby completing said via formation in the fabrication of said integrated circuit device.