Patent ID: 6401193
Filing Date: 2002-06-04
Classification: G06F

Abstract:
A method for prefetching data to a low level memory of a computer system that includes a processor and multiple memory levels comprising the steps of:generating data prefetch prediction information for a plurality of instructions that utilize a deterministic source addressing mode, including utilizing said deterministic source addressing mode as a basis for identifying associations between instruction location indicators for locating said instructions and next data prefetch indicators for locating data to be prefetched, such that said deterministic addressing mode is used with each said instruction to calculate a particular next data prefetch indicator to be associated with the particular instruction location indicator for locating said instruction, wherein said data prefetch prediction information is generated to indicate said association between said particular next data prefetch indicator and said particular instruction location indicator; storing said data prefetch prediction information in a manner that enables searching therethrough, said storing of said data prefetch prediction information being distinguishable from storing said instructions; upon execution of a sequence of said instructions, identifying an instruction location indicator of a specific upcoming instruction; utilizing said identified instruction location indicator of said specific upcoming instruction as a basis to execute a search of said data prefetch prediction information so as to identify a specific next data prefetch indicator associated with said identified instruction location indicator; searching said memory levels of said computer system for data related to said specific next data prefetch indicator; and transferring said data related to said specific next data prefetch indicator to said low level memory of said computer system.