Patent ID: 8310428
Filing Date: 2012-11-13
Classification: G09G

Abstract:
1. A driving voltage output circuit having a plurality of high-side voltage followers and a plurality of low-side voltage followers, the high-side voltage followers outputting driving voltages equal to or greater than a reference potential and equal to or less than a high-side power supply potential, the low-side voltage followers outputting driving voltages equal to or greater than a low-side power supply potential and equal to or less than the reference potential, the driving voltages being supplied to column lines in a matrix display panel responsive to display data, each column line being periodically switched between receiving a driving voltage from one of the high-side voltage followers and receiving a driving voltage from one of the low-side voltage followers, each of the high-side voltage followers and each of the low-side voltage followers separately comprising: a differential input stage having an inverting input terminal, a non-inverting input terminal, a first transistor with a control terminal connected to the non-inverting input terminal, a second transistor with a control terminal connected to the inverting input terminal, and a first current mirror connected to controlled terminals of the first and second transistors to supply the second transistor with a current equal to a current conducted by the first transistor, the first and second transistors operating as a differential amplifier to generate a first potential at a node at which the first transistor and the first current mirror are interconnected and a second potential at a node at which the second transistor and the first current mirror are interconnected; a control stage including a control circuit for generating a third potential responsive to a difference between the first potential and the second potential, a third transistor with a control terminal receiving the first potential, and a fourth transistor with a control terminal receiving the third potential, the third and fourth transistors being of mutually opposite channel types, the third and fourth transistors being connected in a push-pull configuration between a terminal supplying the high-side power supply potential and a terminal supplying the low-side power supply potential to generate a control potential at a node at which the third and fourth transistors are mutually interconnected; and an output stage including a fifth transistor with a control terminal receiving the first potential and a sixth transistor with a control terminal receiving the control potential, the fifth and sixth transistors being of mutually identical channel types, the fifth and sixth transistors being connected in series between a terminal supplying a particular power supply potential and a terminal supplying the reference potential to generate a driving voltage at an output terminal at which the fifth and sixth transistors are mutually interconnected, the particular power supply potential being the high-side power supply potential in the high-side voltage followers and the low-side power supply potential in the low-side voltage followers, the output terminal being connected to the inverting input terminal of the input stage and to one of the column lines.