Patent ID: 6493414
Filing Date: 2002-12-10
Classification: G11C

Abstract:
A system for providing a serial bit sequence that represents one or more information parameters stored in an integrated-circuit chip, comprising:a plurality of fuse modules, wherein each fuse module has a fuse that is blown or not blown to represent a respective bit of the serial bit sequence at an output terminal thereof; a parallel-load/serial-shift shift-register that has a shift-register output terminal and that has a number of serially-connectable bit storage cells, wherein each bit storage cell stores a respective bit of the serial bit sequence, wherein each of said serially-connected bit storage cells has a bit-cell data input terminal and a bit-cell data output terminal; wherein each of said bit storage cells has a respective fuse-input transmission gate that has an input terminal coupled to an output terminal of a respective one of the plurality of fuse modules and that has an output terminal coupled to a respective bit storage cell data input terminal, wherein the fuse-input transmission gate is controlled by a TEST MODE signal to provide parallel loading of the bit storage cells of the shift register with the bits of the bit sequence; each of said bit storage cells, except for the starting shift register bit cell, also has a serial-data transmission gate that has an input terminal coupled to an output terminal of an adjacent lower-order one-bit storage cell and that has an output terminal coupled to a respective bit storage cell data input terminal of a higher-order bit storage cell, wherein the respective transmission gates are controlled by a SHIFT signal to serially connect the bit storage cells together to provide for serially shifting data through adjacent cells of the shift register to the output terminal of the shift register; a two-input data selector and buffer having first and second input terminals and an output terminal, wherein the first input terminal is coupled to an output terminal of a memory array for storing normal-data in the integrated-circuit chip, wherein the second input terminal is coupled to the data output terminal of the parallel-load/serial-shift shift-register; wherein the system in a TEST MODE has the respective fuse-input transmission gates turned off, the respective serial-data transmission gates are on, and the two-input data selector and buffer provides data at its output terminal from the shift-register; and wherein the system in a non-TEST MODE has the respective fuse-input transmission gates on, the respective serial-data transmission gates are off, and the two-input data selector and buffer provides normal data at its output terminal.