Patent ID: 8673709
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method comprising: forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, wherein a portion of the semiconductor substrate between and adjoining the first STI region and the second STI region forms a semiconductor strip; recessing top surfaces of the first STI region and the second STI region, wherein a top portion of the semiconductor strip forms a semiconductor fin comprising a first fin portion and a second fin portion; forming a gate dielectric on a top surface and sidewalls of the first fin portion, wherein the gate dielectric is not on the second fin portion; forming a gate electrode on the gate dielectric, wherein the gate electrode covers the first fin portion and a first portion of the first STI region, and wherein a second portion of the first STI region is not covered by the gate electrode; and after the step of forming the gate electrode, recessing the second portion of the first STI region.