Patent ID: 8837243
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. An integrated memory built-in self-test system, comprising: a memory subsystem comprising a memory array and configured to read data from and write data to addresses in the memory array; sequential control logic configured to control testing a plurality of addresses in the memory array by performing write operations of test data to a sequence of addresses in an address sequence and read operations of output data from the sequence of addresses in the address sequence, the sequential control logic having a plurality of states and outputting state information corresponding to a current state of the plurality of states; write data decoding logic configured to receive at least a portion of the state information from the sequential control logic and generate test data values and expected data values; memory control signal decoding logic configured to receive at least a portion of the state information from the sequential control logic and generate a current memory control signal set in a memory control signal set sequence, the current memory control signal set corresponding to a current address in the address sequence; address counter logic configured to receive at least a portion of the state information from the sequential control logic and generate addresses in the address sequence, the memory subsystem testing memory locations in response to addresses generated by the address counter logic and memory control signals generated by the memory control signal decoding logic; address comparison logic configured to receive the current address and compare the current address with a maximum address and to output a maximum address indication when the current address reaches the maximum address; data comparison logic configured to receive data read from a tested memory location in response to a memory address generated by the address counter logic, the data comparison logic further configured to compare the data read from a tested memory location with an expected data value to determine whether the tested memory location functions to accurately store the test data and to output a pass-fail indication of whether the tested memory location functions to accurately store the test data; and at least one pipeline register disposed between a pair of elements selected from: the memory control signal decoding logic and the memory subsystem; the address counter logic and the address comparison logic; the address comparison logic and the sequential control logic; the address comparison logic and the address counter logic; the address comparison logic and the memory control signal decoding logic; the data comparison logic and the sequential control logic; the data comparison logic and the address counter logic; and the data comparison logic and the memory control signal decoding logic.