Patent ID: 8901741
Filing Date: 2014-12-02
Classification: H01L

Abstract:
1. A method of forming a high performance dual damascene interconnnect structure comprising wiring interconnect network having conductive lines embedded in an intermetal dielectric (IMD) medium having a dielectric constant (k eff ) between about 1 and 2.2, said dielectric medium having engineered porosity; said interconnect structure with a nanocolumnar porous dielectric forming a wiring interconnect network comprising line features that traverse a distance across a chip, and via features which connect together lines in different levels of interconnects in a multilevel stack, said method comprising the steps of: said first planar dielectric layer material encases a set of conductive vias and supporting thereon a set of conductive lines on said top surface of said first dielectric layer material, said composition of said dielectric layers being selected from the group consisting of (a) an organic thermoset dielectric selected from the group consisting of polyimides, polyarylene ethers, benzocyclobutene; (b) a dielectric spun on glass films formed from a substrate selected from the group consisting of tetra ethyl orthosilicate, methyl silsesquioxane, hydrogen silsesquioxane and combinations thereof; (c) hydrogenated amorphous dielectrics comprising silicon, carbon, hydrogen, and oxygen deposited by plasma enhanced chemical vapor deposition (PECVD); (d) undoped silicon oxide glass (USG) and fluorine doped silicon oxide glass (FSG) deposited by PECVD; (e) porous versions of (a) to (d); depositing a hard mask stack layer on said line level dielectric layer; depositing a first photoresist to an exposed upper surface of said hard mask layer; patterning and transferring a line trench opening and a via opening into said line level and said via level dielectric respectively; filling said line trench and said via opening with a conductive liner and a conductive fill material and planarizing to form interconnect lines and vias; depositing a random brush polymer layer on a top surface of said interconnect lines and said hard mask layer and depositing a diblock polymer on an exposed surface of said random brush polymer, and thermally curing said polymers; developing said diblock polymer and forming a stencil pattern comprising a regular array of nanometer sized holes to form a barrier cap layer containing a-regular array of nanoscale holes; and transferring the said regular of nanoscale hole pattern into said transferring the hole pattern into said cap, said hard mask layer said line level and said via level dielectric layers being positioned in the regions between said interconnect lines using a reactive ion etching process; removing remaining said diblock polymer using a suitable wet or dry etch; recessing said cap and said hard mask layers by etching so that they are slightly below the top surface of said interconnect lines; depositing a second dielectric cap layer to close off the tops of said regular array of holes, and optionally planarizing said second dielectric cap layer.