Patent ID: 8352714
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A method for operating a system having memory and a processor implementing instructions in a pipeline manner in which execution of each instruction involves a plurality of stages over a plurality of time cycles, wherein: (i) the plurality of stages includes a plurality of non-final stages and a final stage; (ii) at a given time cycle, each of a plurality of different instructions is at a different one of the stages in a pipeline; and (iii) the processor has one or more temporary registers that (i) store intermediate values generated by processing instructions and (ii) may be changed during the non-final stages of execution of an instruction and one or more permanent registers that may not be changed during the non-final stages of execution of an instruction, the method comprising: the system detecting a watchpoint event associated with execution of a watchpoint instruction at a non-final stage; and the system halting processing of the processor after changing at least one temporary register associated with execution of the watchpoint instruction, but before changing any permanent registers associated with execution of the watchpoint instruction or any subsequent instructions following the watchpoint instruction in the pipeline, wherein, before halting the processing of the processor, the processor fetches appropriate data from the temporary registers, the permanent registers, or the memory for at least one instruction in the pipeline.