Patent ID: 8400832
Filing Date: 2013-03-19
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a first circuit unit provided in a major surface of a semiconductor substrate; a second circuit unit provided in the major surface to oppose the first circuit unit along a first direction parallel to the major surface; and an intermediate unit provided between the first circuit unit and the second circuit unit, the first circuit unit including: the second circuit unit including: the intermediate unit including: the first one diffusion layer including a first connection region, a first midpoint region provided on the first gate electrode side of the first connection region and connected to the first connection region, and a first inner connection region provided inside the first connection region and electrically connected to the first interconnect, a width of the first midpoint region along the second direction being narrower than a width of the first connection region along the second direction, the first other diffusion layer being electrically connected to the third interconnect, the second one diffusion layer including a second connection region, a second midpoint region provided on the second gate electrode side of the second connection region and connected to the second connection region, and a second inner connection region provided inside the second connection region and electrically connected to the second interconnect, a width of the second midpoint region along the second direction being narrower than a width of the second connection region along the second direction, the second other diffusion layer being electrically connected to the fourth interconnect, an impurity type of the first and second connection regions, the first and second midpoint regions, and the first and second inner connection regions being a first conductivity type, an impurity concentration of the first and second inner connection regions being higher than an impurity concentration of the first and second connection regions, a distance along the first direction from a boundary between the first connection region and the first midpoint region to an edge of the first gate electrode on the first connection region side being longer than a distance along the first direction from a boundary between the second connection region and the second midpoint region to an edge of the second gate electrode on the second connection region side.