Patent ID: 7215170
Filing Date: 2007-05-08
Classification: H03K

Abstract:
1. A logic circuit coupled between a power supply node and a ground node and comprising a plurality of bipolar junction transistors, wherein each current path extending between the power supply and ground nodes includes no more than one base-emitter junction, and wherein the plurality of bipolar junction transistors comprises: a first pair of transistors controlled by a clock signal supplied to the logic circuit and coupled for receiving a pair of differential input signals; a second pair of transistors controlled by a complementary clock signal supplied to the logic circuit and coupled for receiving a pair of differential latch signals generated by the first pair of transistors; a third pair of transistors controlled by at least one of a SET signal and a RESET signal, wherein at least one of the third pair of transistors is coupled to the first and second pairs of transistors for changing a polarity of at least one of the pair of differential latch signals when the SET or RESET signal is asserted; and a first, a second and a third additional transistor, each coupled in a common-emitter configuration with a different one of the first, second and third pairs of transistors.