Patent ID: 6426256
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A method for manufacturing an embedded dynamic random access memory (DRAM) self-aligned borderless contacts (SAC), said method comprising:providing a substrate having a first device region and a second device region, said first device region comprising a first metal oxide semiconductor (MOS) transistor and a plurality of first isolation structures formed on said first device region, said second device region comprising a second metal oxide semiconductor (MOS) transistor and a plurality of second isolation structures formed on said second device region; forming a silicide block layer over said second device region; forming an etching stop layer covering said first device region and said silicide block layer of said second device region; forming a mask layer on said first device region to expose said etching stop layer of said second device region; removing said etching stop layer not covered by said mask layer; forming a first dielectric material layer on said first device region and said second device region, said first dielectric material layer defining and patterning out a first contact window on said silicide block layer of said second device region; forming a second dielectric material layer on said first device region and said second device region, said second dielectric layer defining and patterning out a second contact window on said first dielectric material layer of said second device region; forming a third dielectric material layer on said first device_region and said second region; forming at least a third contact window coupled to said first transistor of said first device region; and forming a metallic node on said third contact window.