Patent ID: 6518105
Filing Date: 2003-02-11
Classification: H01L,Y10S

Abstract:
A process for manufacturing a tunneling-biased NMOSFET comprising:providing a P-type silicon wafer having a top surface and a buried oxide layer located a distance below said top surface, forming oxide filled trenches that extend downwards from said top surface as far as said buried layer, said trenches being disposed so as to fully enclose a volume of P-type silicon, thereby forming a P-well on said top surface, forming a dielectric layer to a thickness that is less than the tunneling threshold of said dielectric layer; depositing a layer of polysilicon on said dielectric layer; patterning said polysilicon layer to form a gate pedestal, having two opposing long sides that extend from a first end over a first oxide filled trench across said P-well to a second end abutting a second oxide filled trench; removing all of said dielectric layer not under said polysilicon gate; through a first mask, implanting donor ions in a first region that overlaps both of said long sides and that does not overlap either of said ends, thereby forming source and drain regions on opposing sides of said gate pedestal; and through a second mask, implanting acceptor ions in a second region that overlaps one of said ends, whereby a tunneling connection is formed between said P-well and that part of said polysilicon gate that is within said second region.