Patent ID: 7689953
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A method, comprising: accessing, by a processing unit, information indicative of a transistor-level circuit design that characterizes a plurality of transistors in a circuit, connectivity between the transistors, and transistor-level parasitics; generating, in the processing unit, a cell-level circuit design based on the transistor-level circuit design, the cell-level circuit design comprising a plurality of cells, each cell being characterized by the information indicative of the transistor-level circuit design prior to initiating a static timing analysis, wherein generating the cell-level circuit design comprises determining at least one component of at least one of a channel-connected region or a channel-connected region group, wherein determining said at least one component of at least one of a channel-connected region and a channel-connected region group comprises folding together gates that match within a selected tolerance or range; and applying, in the processing unit, the static timing analysis to the cell-level circuit design to determine at least one time delay associated with the transistor-level circuit design.