Patent ID: 6452831
Filing Date: 2002-09-17
Classification: B82Y,G11C,H01L,Y10S

Abstract:
A memory integrated circuit comprising:row and column driving and addressing circuitry; a first memory array including a first plurality of memory cells formed from n-type silicon and arranged in rows and columns, the first plurality of memory cells having a first latency, the first plurality of memory cells coupled to the driving and addressing circuitry, each memory cell having a body of semiconductor material having one or more islands of semiconductor material surrounded by an insulator formed in a respective pore extending into the body of the semiconductor material; and a second memory array including a second plurality of memory cells formed from n-type silicon and arranged in rows and columns, the second plurality of memory cells having a second latency greater than the first latency, the second plurality of memory cells coupled to the driving and addressing circuitry.