Patent ID: 9088279
Filing Date: 2015-07-21
Classification: H03K

Abstract:
1. A timing margin circuit of a local clock buffer circuit located within a microelectronic device, the timing margin circuit comprising: a self-timed feedback circuit; an inverter logic gate having an inverter input and an inverter output, the inverter input receiving an input clock signal; a NAND logic gate having a first NAND input that is coupled to the inverter output, a second NAND input, and a NAND output; and a logic device having a first logic device input that is coupled to the inverter output, a second logic device input that receives a mode selection signal, and a logic device output that couples to the second NAND input, the NAND logic gate generating, at the NAND output, a first time delayed input clock signal having a first time delay based on the mode selection signal being at a first logic state, and a second time delayed input clock signal having a second time delay based on the mode selection signal being at a second logic state, the first and the second time delayed input clock signal controlling a falling edge transition of a local clock signal derived from the input clock signal, wherein the first time delayed input clock signal controls the falling edge transition of the local clock signal to occur within a time window that follows a rising edge transition of the local clock and terminates at a finite pulse interval determined by the self-timed feedback circuit.