Patent ID: 7660173
Filing Date: 2010-02-09
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells selected in relation to a plurality of word lines and a plurality of bit lines; an address decoder selecting at least one word line in response to a refresh address and selecting all of the plurality of bit lines in response to a hidden write signal when a CBR refresh operation is requested during a test mode; a hidden write control circuit generating the hidden write signal when the CBR refresh operation is requested during the test mode; a refresh address generating circuit generating the refresh address when the CBR refresh operation is requested during the test mode; and a data input circuit applying data internally generated in response to the hidden write signal to all of the plurality of bit lines when the CBR refresh operation is requested during the test mode, wherein the hidden write signal is generated when a CBR signal requesting the CBR refresh operation is enabled while a test signal requesting a test mode setting for the test mode is enabled.