Patent ID: 9093555
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: forming a first layer of a dual layer hard mask over a gate of a p-channel metal oxide semiconductor (PMOS) transistor, said first layer being halogen-containing silicon nitride formed by a plasma enhanced chemical vapor deposition (PECVD) process with a halogenated silane reagent and ammonia; forming a second layer of said dual layer hard mask on said first layer, said second layer being silicon nitride formed by a PECVD process free of a halogenated reagent; removing said second layer and said first layer from horizontal surfaces of said integrated circuit by an anisotropic etch, leaving said second layer and said first layer on lateral surfaces of gate offset spacers disposed on lateral surfaces of said gate of said PMOS transistor; subsequently removing material from a substrate of said integrated circuit to form source/drain cavities adjacent to said gate of said PMOS transistor; subsequently heating said integrated circuit at a temperature of at least 750° C. for at least 30 seconds in a hydrogen containing ambient which includes at least 0.5 percent hydrogen; subsequently forming silicon-germanium (SiGe) source/drain regions in said source/drain cavities by an epitaxial process; and subsequently removing said second layer and said first layer by a wet etch process.