Patent ID: 6456537
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A method of erasing a memory cell having a gate node coupled to a gate structure, a source node coupled to a source structure, a drain node coupled to a drain structure, wherein a floating gate structure is disposed between the gate structure and the source structure and the drain structure such that a charge is stored in the floating gate structure when the memory cell is programmed and wherein the charged is removed from the floating gate structure when the memory cell is erased, comprising:in an erase cycle, (a) selecting the memory cell; (b) applying a drain potential to the drain node of the selected memory cell having a first polarity and applying a source potential to the source node of the selected memory cell having the first polarity; (c) concurrently with (b), applying a gate potential to the gate of the selected memory cell having a second polarity; and (d) maintaining the drain potential and the gate potential until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.