Patent ID: 8580608
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A fabrication method of a package structure having an embedded semiconductor component, comprising the steps of: providing a carrier board having two opposite surfaces and having a core layer, a first metal layer formed on two opposite surfaces of the core layer, a release layer formed on the first metal layer, and a second metal layer formed on the release layer; performing a patterning process to form a plurality of connection columns on the second metal layer and expose portions of the second metal layer; forming a first insulating protection layer on the exposed portions of the second metal layer, with the connection columns being exposed from the first insulating protection layer; mounting at least a chip on the connection columns, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the electrode pads being electrically connected to the connection columns through a plurality of solder bumps, respectively; forming an encapsulant on the first insulating protection layer to encapsulate the chip; removing the carrier board; and forming a built-up structure on the first insulating protection layer and the connection columns.