Patent ID: 6451639
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method of forming a gate in a semiconductor device comprising the steps of:forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device; depositing successively a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer; forming a hard mask layer as a mask pattern and patterning the dummy gate silicon layer using the mask pattern as an etch barrier; forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by carrying out thermal oxidation on the resultant structure after the patterning step; forming spacers at both sidewalls of the dummy gate silicon layer; depositing an insulating interlayer on the resultant structure after the spacer forming step; polishing the insulating interlayer so as to expose the dummy gate silicon layer; forming a damascene structure by removing the dummy gate silicon and the insulating layers by using the insulating interlayer as another etch barrier; depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure; and polishing the gate metal and insulating layers until the insulating layer is exposed.