Patent ID: 6487135
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A semiconductor device, comprising:a first circuit including a plurality of memory cells, said first circuit operating in response to a first clock signal; a second circuit and a third circuit which are coupled with said first circuit; and a bus for coupling said first circuit to said second and third circuits, wherein: said second circuit outputs, in response to a second clock signal, a first a dress signal to said first circuit; said third circuit outputs, in response to a third clock signal, a second address signal to said first circuit; said first circuit includes a refresh control circuit for executing a refresh operation for the memory cells in response to a fourth clock signal and an address latch for storing said first or second address signal in response to said first clock signal; and said first clock signal has a frequency equal to or more than a sum of frequencies respectively of said second, third, and fourth clock signals.