Patent ID: 6460169
Filing Date: 2002-10-01
Classification: G06F

Abstract:
A method for positioning of unit pins in a VLSI design, including the steps of:(a) identifying, in a VLSI chip design, external nets with unit pins located in a sub-optimal position with respect to minimum net length, by; determining a minimal net length for any external net with unit pins assigned; determining a minimal net length for an external net without unit pins assigned; calculating a difference between said minimal net length for an external net with unit pins assigned and said minimal net length for an external net without unit pins assigned; identifying as an external net with unit pins in a sub-optimal position, units nets where said differences exceeds a threshold; (b) running a routing program on each external net identified in the identifying step positioning unit pins for said net in accordance with where the minimal line crosses a unit boundary; (c) positioning unit pins for said net in accordance with where the wire route crosses a unit boundary.