Patent ID: 8239603
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. A system comprising: a low pin count (LPC) bus operating according to an LPC protocol; an I/O controller coupled to the LPC bus; a second bus coupled to the I/O controller, wherein the second bus has a reduced pin count relative to the LPC bus and operates according to a second bus protocol; and a plurality of devices coupled to the second bus; wherein the I/O controller is configured to receive LPC bus transactions from the LPC bus, wherein the LPC bus transactions comprise device identification information identifying which of the plurality of devices are targeted by the LPC bus transactions; wherein the I/O controller is further configured to translate the received LPC bus transactions into corresponding second bus transactions, wherein the corresponding second bus transactions comprise the device identification identifying which of the plurality of devices are targeted by the LPC bus transactions, and transmit the corresponding second bus transactions onto the second bus; wherein each of the plurality of devices is configured to: wherein the plurality of devices appear to the system as if they were transmitting and receiving data through respective LPC interfaces; wherein the I/O controller includes a processing unit configured to initiate bus transactions on the second bus; and wherein the I/O controller further includes a bus arbitration unit configured to arbitrate ownership of the second bus between the processing unit and the LPC bus.