Patent ID: 6801447
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A ferroelectric storage device, comprising:(a) a ferroelectric memory cell comprising a selection transistor and a ferroelectric capacitor, said selection transistor having a drain or a source connected to one terminal of said ferroelectric capacitor; (b) a word line connected to a gate of said selection transistor; (c) a bit line connected to a source or a drain of said selection transistor, said source or drain not being connected to said ferroelectric capacitor; and (d) reading means having a bit line charge circuit for charging said bit line to a predetermined voltage while said word line is activated, said reading means detecting a quantity of charge used by said bit charge circuit in charging said bit line to said predetermined potential to read out data stored in said ferroelectric memory cell, said reading means further comprising (1) a sub bit line connected to said bit line charge circuit so as to supply charge for charging said bit line; (2) a sub bit line charge circuit for pre-charging said sub bit line to a first potential; (3) a sense amplifier for amplifying voltage of said sub bit line after said bit line is charged via said bit line charge circuit; and (4) a second bit line charge circuit, wherein said reading means activates said sub bit line charge circuit, pre-charges said sub bit line to said first potential and pre-charges said bit line to a second potential by activating said second bit line charge circuit, inactivates said sub bit line charge circuit and said second bit line charge circuit, activates said bit line charge circuit, and activates said sense amplifier to amplify voltage of said sub bit line after said word line is activated and a memory cell for reading is selected to perform a reading operation.