Patent ID: 7626254
Filing Date: 2009-12-01
Classification: H01L

Abstract:
1. A semiconductor package comprising: an embedded chip comprising a plurality of embedded chip pads; a substrate having the embedded chip mounted thereon and comprising a plurality of redistribution pads for redistributing the embedded chip pads; first bonding wires for connecting the embedded chip pads to the redistribution pads; a first protective layer formed to bury the embedded chip and the substrate, and comprising first via holes for exposing the redistribution pads; first vias connected to the redistribution pads through the first via holes; a first chip mounted on the first protective layer and comprising a plurality of first chip pads; second bonding wires for connecting the first chip pads to the first vias; a second protective layer formed to entirely bury the embedded chip and the first chip, and comprising second via holes for exposing the first vias; second vias connected to the first vias through the second via holes; and external connection terminals connected to the second vias.