Patent ID: 6018796
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A data processor comprising:processing means for processing an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n; andswitching means for switching said number of pipeline stages of said processing means between n and m,wherein at least one pipeline stage of the processing means has a processing content that is divisible into a plurality of sequential partial operations,the processing means processing all partial operations in a single stage when pipeline control is performed in n-stages and processing each partial operation in a separate stage when pipeline control is performed in m-stages,each stage being performed by a different individual processing means, and at least one of the individual processing means including:a plurality of partial operation means that each execute one partial operation; anda plurality of transmission holding means, each of which is provided between a partial operation means and a succeeding partial operation means, the transmission holding means transmitting a processing result of a partial operation means when pipeline control is performed in n-stages and holding a processing result of a partial operation means before transmitting to the succeeding partial operation means in a next stage when pipeline control is performed in m-stages,whereby, in at least one individual processing means, all partial operation means operate in a same stage when pipeline control is performed in n-stages and each partial operation means operates in a different stage when pipeline control is performed in m-stages.