Patent ID: 6288942
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A nonvolatile semiconductor storage device comprising:a semiconductor substrate;a plurality of memory transistors aligned in row and column directions on said semiconductor substrate, a plurality of said memory transistors connected in series in the column directions forming a NAND memory cell;a plurality of selection transistors to connect or disconnect said memory transistors to or from bit lines for delivering signals to said memory transistors;a plurality of insulating portions formed on said semiconductor substrate between individual said memory transistors adjacent in row directions and between individual said selection transistors adjacent in row directions to isolate said memory transistors and said selection transistors;a plurality of implanted regions formed in said semiconductor substrate under said insulating portions and having the same conduction type as that of said semiconductor substrate;a plurality of first impurity regions formed in said semiconductor substrate under said insulating portions in locations between memory transistors adjacent in row directions, said first impurity regions having the same conduction type as that of said semiconductor substrate and having a higher concentration than that of said implanted regions; anda plurality of second impurity regions formed in said semiconductor substrate under said insulating portions in locations between connected portions of said bit lines adjacent in row directions with said selection transistors, said second impurity regions having the same conduction type as that of said semiconductor substrate and having a higher concentration than that of said implanted regions.