Patent ID: 8406258
Filing Date: 2013-03-26
Classification: H03K,H03M,H04J

Abstract:
1. An integrated circuit with a configurable high-speed serial interface, the integrated circuit comprising: a plurality of communication channels, each channel including circuitry arranged to communicate a serial data stream using a reference clock signal, wherein the plurality of channels are grouped into a plurality of modules, each module comprising multiple channels; a clock multiplexer in each channel which is configured to select the reference clock signal from a plurality of input clock signals; a ring clock multiplication unit in each module which is arranged to output a clock signal; a first low-jitter clock generator circuit using a first inductor-capacitor-based oscillator circuit to generate a first low-jitter clock signal; a second low-jitter clock generator circuit using a second inductor-capacitor-based oscillator circuit to generate a second low-jitter clock signal, wherein the first and second inductor-capacitor-based oscillator circuits have different tuning ranges; and clock distribution circuitry arranged to input the first and second low-jitter clock signals to each said clock multiplexer, wherein the clock distribution circuitry is further arranged to input said clock signal to the clock multiplexers for the channels in that module.