Patent ID: 7882335
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A method of scheduling execution of a load instruction in a processor having at least one cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other, the method comprising: receiving an issue group of instructions; determining if at least one load instruction is in the issue group and, if so, scheduling the at least one load instruction in a first pipeline based upon a priority list, wherein the priority list prioritizes the load instruction dealing with semaphores as having a highest priority, the load instruction dealing with a store address conflict as having a second highest priority, the load instruction dealing with a reliable miscount as having a third highest priority, the load instruction dealing with a unreliable miscount as having a fourth highest priority, the load instruction dealing with a dependent load as having a fifth highest priority, the priority list prioritizes the load instruction dealing with a chained compare instruction as having a sixth highest priority, the load instruction dealing with a writeback instruction as having a seventh highest priority, and the load instruction dealing with a end of chain instruction as having an eighth highest priority; and scheduling execution of the issue group of instructions in the cascaded delayed execution pipeline unit.