Patent ID: 8122312
Filing Date: 2012-02-21
Classification: G01R,G06F

Abstract:
1. A method, in a data processing system, for internally controlling logic built-in self test in a multiple core microprocessor, the method comprising: receiving a test program at a control core within the multiple core microprocessor, wherein the multiple core microprocessor comprises a plurality of processing cores including the control core; setting, by the control core under control of the test program, voltage and frequency for a test core within the plurality of processing cores; configuring, by the control core under control of the test program, a logic built-in self test engine of the test core; running, by the logic built-in self test engine, a logic built-in self test on test logic within the test core; receiving, by the control core under control of the test program, logic built-in self test results from the test core; and storing, by the control core under control of the test program, the logic built-in self test results.