Patent ID: 6060740
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A non-volatile semiconductor memory device comprising:a semiconductor substrate;a plurality of semiconductor active regions formed in said semiconductor substrate, in a state isolated from each other;a plurality of insulative element isolation regions which are formed between said plurality of semiconductor active regions, respectively;a source region and a drain region formed in each of said plurality of semiconductor active regions, said source region and said drain region being located apart from each other;a first gate insulation film formed in said plurality of semiconductor active regions between said source region and said drain region;a charge storage layer which capacitively couples, through said first gate insulation film, to said corresponding one of said plurality of semiconductor active region and said drain region;a second gate insulation film formed at least on said charge storage layer; anda control gate which capacitively couples to said charge storage layer through said second gate insulation film,wherein said control gate extends, above said plurality of semiconductor active regions adjacent to each other, over said plurality of insulative element isolation regions, andsaid second gate insulation film formed on said charge storage layer extends to an upper surface of said plurality of insulative element isolation regions lying under said control gate and to an upper surface of said plurality of insulative element isolation regions other than said upper surface of said plurality of insulative element isolation regions lying under said control gate.