Patent ID: 6759293
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising:a) forming a contact hole to expose a joining portion by etching an inter-layer insulation layer disposed on top of a semiconductor substrate; b) forming a contact plug inside the contact hole; c) molding an etch stop layer and a sacrificial oxide layer on the contact plug and the inter-layer insulation layer; d) molding a storage node hole to expose the contact plug by etching the etch stop layer and the sacrificial oxide layer; e) molding a silicide layer on the contact plug; f) forming a TiN bottom electrode comprising a TiN layer inside the storage node hole by a CVD method; g) separating the TiN bottom electrode by removing the TiN layer; h) exposing the TiN bottom electrode by removing the sacrificial oxide layer; i) forming a dielectric layer on the TiN bottom electrode pattern; and j) molding a top electrode on the dielectric layer.