Patent ID: 8219755
Filing Date: 2012-07-10
Classification: G06F

Abstract:
1. A cache comprising: a tag memory configured to store tags of cache blocks stored in the cache, wherein the tag memory is coupled to receive an index corresponding to an input address and is configured to output at least one tag responsive to the index; and a comparator coupled to receive the at least one tag from the tag memory and a tag portion of the input address, wherein the comparator is configured to compare the at least one tag to the tag portion of the input address to generate a hit/miss indication, and wherein the comparator comprises dynamic circuitry, and wherein the comparator is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion of the input address matches the at least one tag from the tag memory, and wherein the comparator comprises first circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result, and wherein the output remains in a precharge state established during a precharge phase of the dynamic circuitry responsive to the first circuitry inhibiting the state change during the evaluate phase, and wherein the precharge phase and the evaluate phase are phases of the dynamic circuitry that are controlled by a clock, and wherein the dynamic circuitry is coupled to receive a plurality of pairs of dynamic signals, wherein each pair of dynamic signals represents either a bit of the tag portion of the input address or a bit of the at least one tag, and wherein a first signal of each pair represents the bit of the at least one tag or the bit of the tag portion of the input address and a second signal of each pair represents a complement of the bit of the at least one tag or the bit of the tag portion of the input address, and wherein the first circuitry is configured to inhibit assertion of the first signal and to inhibit assertion of the second signal corresponding to each bit of either the at least one tag or the tag portion of the input address responsive to an assertion of the control signal, wherein inhibiting the assertion of the first signal and the second signal results in the first result from the dynamic circuitry.