Patent ID: 8667252
Filing Date: 2014-03-04
Classification: G06F

Abstract:
1. A portion of a processing system comprising: a plurality of processing clusters each including a register file, an arithmetic logic unit, a load/store unit a plurality of write ports, a plurality of read ports and connection configuration logic; a runtime reconfigurable interconnect coupling the plurality of processing clusters, wherein the runtime reconfigurable interconnect is selectively alterable to connect any first one of the processing clusters with any second one of the processing clusters using any portion of the runtime reconfigurable interconnect; and an interface to a processor, wherein the plurality of processing clusters and the runtime reconfigurable interconnect execute a program segment designated by the processor, the program segment including a configuration portion setting a configuration of the runtime reconfigurable interconnect, the configuration portion of the program segment including, for each write port of one of the processing clusters, a receive bit indicating whether data received data should be written to a corresponding register file address for a location within the register file and, for each read port of the one processing cluster, for each read port of the one processing cluster, a send bit indicating whether data should be read from a corresponding register file address for a location within the register file.