Patent ID: 6502172
Filing Date: 2002-12-31
Classification: G06F

Abstract:
A memory access control system for controlling a memory access operation suitable for use between a CPU and a memory unit, wherein the CPU can issue a read request and issue an L1 write-back signal after a predetermined time to indicate that a write back operation is desired, the memory access control system comprising:a CPU interface circuit coupled to the CPU, wherein when the CPU interface circuit receives the read request from the CPU, an internal read request is issued without waiting for the L1 write-back signal, wherein when the CPU interface circuit receives the L1 write-back signal, a read-stop signal is promptly issued; and a memory control unit coupled between the CPU interface circuit and the memory unit, wherein when the memory control unit receives the internal read request from the CPU interface circuit, a read operation is accordingly performed, and when the memory control unit receives the read-stop signal, the read operation stops and the write back operation accordingly starts.