Patent ID: 7546422
Filing Date: 2009-06-09
Classification: G06F

Abstract:
1. In a cache-coherent device including a coherency engine, an integrated cache, divided into a plurality of distributed caches, and a plurality of client ports, a method for processing a transaction, comprising: receiving a transaction request for a data element at one of said plurality of client ports, said transaction request includes an address; determining, using a coherency engine, whether said address is present in one of the plurality of distributed caches, each of said distributed caches assigned to one of said plurality of client ports; and monitoring whether said data element is requested in exclusive state and whether said data element can be granted exclusive state transmitting said data element for said read transaction request from said one of said plurality of distributed caches to one of said plurality of client ports prefetching one or more cache lines ahead of said read transaction request; and updating a coherency state information in said plurality of distributed caches wherein said transaction request is a read transaction request wherein a coherency state is stored as a set of status bits in said plurality of distributed caches and utilized by a cache coherency protocol, wherein said set of status bits for each data element in the cache include: a modified bit, an exclusive bit, a shared bit, an invalid bit, an exclusive prime bit, a modified prime bit, a modified-exclusive prime bit, a conflict bit, and a shared conflict bit.