Patent ID: 7248536
Filing Date: 2007-07-24
Classification: G11C

Abstract:
1. An integrated semiconductor memory comprising: a word line driver that includes a driver segment; a word line having a master word line and having at least one word line segment, the word line segment being connected to the driver segment of the word line driver and the driver segment being coupled to the master word line; and a multiplicity of memory cells, each memory cell having a transistor coupled to a word line; wherein the word line segment, depending on a bias voltage of the master word line and by means of the driver segment, is electrically connectable either to a first line providing a first potential, which deactivates the word line segment, or to a second line, the second line being able to be biased such that it provides either a second potential, which activates the word line segment, or a third potential, the magnitude of which lies between the first potential and the second potential; and wherein, in a first operating mode, in which, upon deactivation of the word line segment, the word line segment is biased with the third potential via the second line, the electrical connection between the word line segment and the first line remains interrupted.