Patent ID: 7462885
Filing Date: 2008-12-09
Classification: H01L

Abstract:
1. An electrostatic discharge-protected MOS structure comprising: a semiconductor substrate of a first conductivity type; a first well of the first conductivity type formed in the semiconductor substrate; a second well of a second conductivity type disposed adjacent to the first well, the second conductivity type being different from the first conductivity type; a source region and a drain region, both doped with impurities of the second conductivity type and formed in the first well and the second well, respectively; a P+ diffusion region formed inside the second well; an oxide layer and a polysilicon layer formed on top of the first well and the second well for forming a gate electrode of the MOS structure; a parasitic SCR comprising at least a parasitic PNP bipolar transistor formed by the P+ diffusion region formed inside the second well, the second well, and the semiconductor substrate and at least a parasitic NPN bipolar transistor formed by the second well, the semiconductor substrate, and the source region respectively; and a buried layer of the second conductivity type interposed at least between the second well and the semiconductor substrate, wherein the buried layer lowers a resistance of the semiconductor substrate such that during an ESD event, ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure, wherein a dimension of the buried layer is adjusted to improve an ESD performance of the MOS structure.