Patent ID: 8429350
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. An integrated circuit device, comprising: a processor core; a level one (L1) cache; a level two (L2) cache; and a history count, kept for each cache line in the L1 cache, the history count for indicating a number of load references to data in the cache line a last time the cache line was called in to the L1 cache; and a comparator configured to compare the history count to a reference count to determine when the reference count is equal to the history count, and a confirmation count that corresponds to reliability of an estimate that the cache line in the L1 cache is marked as least recently used, and when the history count equals the reference count, the confirmation count is incremented and an L1 extended cache directory and count flags is moved to an L2 extended cache directory.