Patent ID: 6765830
Filing Date: 2004-07-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory array having a plurality of dynamic memory cells, a plurality of word lines and a plurality of bit line pairs, wherein the word lines and the bit line pairs are crisscrossed, and each memory cell is disposed between one of the word lines and one of the bit line pairs; a first decoder coupled to the word lines of the memory array, decoding a first address signal and outputting a first select signal to turn on a desired word line of the memory array; a sense amplifier circuit coupled to the bit line pairs of the memory array; a second decoder for decoding a second address signal, and outputting a second select signal; a first delay circuit coupled to the second decoder, delaying the second select signal a first determined time and outputting a sensing enable signal to the sense amplifier circuit, wherein the sense amplifier circuit senses a desired bit line pair connected to the desired word line, amplifies and outputs desired data according to the sensing enable signal; a second delay circuit coupled to the first delay circuit and the sense amplifier circuit, delaying the second select signal a second determined time as an output enable signal after receiving the second select signal; and a latch circuit coupled to the sense amplifier circuit, latching the desired data output from the sense amplifier circuit, and outputting the desired data when receiving the output enable signal.