Patent ID: 6465157
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method to fabricate dual damascene trenches in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate; providing a dielectric layer overlying said semiconductor substrate; depositing a first photoresist layer overlying said dielectric layer; exposing said first photoresist layer to define via trench patterns wherein said photoresist layer is not yet developed; depositing a second photoresist layer overlying said first photoresist layer; exposing said second photoresist layer to define interconnect trench patterns; developing said second photoresist layer and said first photoresist layer simultaneously to complete said via trench patterns in said first photoresist layer and said interconnect trench patterns in said second photoresist layer; etching through said dielectric layer where defined by said via trench patterns in said first photoresist layer to form said via trenches and where defined by said interconnect trench patterns in said second photoresist layer to form interconnect trenches; depositing a metal layer overlying said dielectric layer and filling said via trenches and said interconnect trenches; and polishing down said metal layer to the top surface of said dielectric layer to complete said dual damascene trenches in the manufacture of the integrated circuit device.