Patent ID: 6175893
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A read-only memory connectable to a microcontroller data bus and address bus wherein the read-only memory comprises:memory circuits for storing a sequential array of code words executable by the microcontroller;memory address decoding circuits for selecting one code word of the array of code words;means for conveying the selected code word to the data bus when a read signal is received from the microcontroller;means for storing an address transmitted on the address bus by the microcontroller when an address latch signal is asserted by the microcontroller, the stored address being connected to the memory address decoding circuits;means for incrementing the stored address each time a read signal is received from the microcontroller anda ready circuit having a ready state and a not-ready state for delaying the microcontroller when the not-ready state is asserted, wherein the not-ready state is asserted by the ready circuit when the read signal is received immediately after an address is stored in the storing means and wherein the ready state is asserted by the reads circuit when a read signal is received subsequent to an internal access from the stored address.