Patent ID: 8443175
Filing Date: 2013-05-14
Classification: G06F

Abstract:
1. A microprocessor integrated circuit, comprising: first and second processors; an internal memory, accessible by the first and second processors; and a bus interface unit, configured to interface to a bus external to the microprocessor integrated circuit for providing access to a memory external to the microprocessor integrated circuit, wherein the bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor; wherein the first processor is configured to write debug information to the internal memory; wherein the first processor is further configured to detect an event and to provide a notification of the event to the second processor; wherein the second processor is coupled to the bus interface unit and is configured to execute microcode in response to the event notification received from the first processor, wherein the microcode is configured to read the debug information from the internal memory and to write the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor; wherein the second processor is configured to execute user programs and the microcode, and wherein the first processor is configured to execute only programs developed by the manufacturer of the microprocessor integrated circuit.