Patent ID: 6798049
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A semiconductor package comprising:a circuit board having an upper surface, an opposite lower surface, an opening through the circuit board, a first circuit pattern on the lower surface including bond fingers and ball lands, and a second circuit pattern on the upper surface including at least bond fingers, wherein the first and second circuit patterns are electrically connected to each other through one or more via holes; a first semiconductor chip having a first surface on which a plurality of input/output pads are formed, said first semiconductor chip being disposed within the opening of the circuit board; a second semiconductor chip having a first surface on which a plurality of input/output pads are formed, said second semiconductor chip being in a vertical stack with and bonded to the first semiconductor chip so that the respective input/output pads are oriented in opposite directions; electrical connection means connecting the input/output pads of the first and second semiconductor chips to the bond fingers formed on the lower and upper surfaces of the circuit board, respectively; a hardened first encapsulant covering a portion of the lower surface of the circuit board around the opening and the first semiconductor chip and filling the opening; a hardened second encapsulant covering a portion of the upper surface of the circuit board, and the second semiconductor chip; and a plurality of conductive balls each fusion-bonded on one of the ball lands of the lower surface of the circuit board.