Patent ID: 8614485
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a semiconductor substrate comprising at least one raised surface located above and vertically offset from a recessed surface of said semiconductor substrate; a FinFET located on said raised surface of the semiconductor substrate, wherein said FinFET includes a gate dielectric and a gate electrode surrounding a semiconductor body; an oxide liner located directly on said recessed surface of said semiconductor substrate and having an uppermost surface that is coplanar with said raised surface of said semiconductor substrate, and a recessed surface vertically offset and located beneath said uppermost surface of said oxide liner and positioned between said uppermost surface of said oxide liner and a bottommost surface of said oxide liner, wherein no portion of said oxide liner extends beneath the semiconductor body; and an etched back anisotropic oxide located directly on said recessed surface of said oxide liner and spaced apart from said semiconductor body by said gate dielectric and a first portion of said gate electrode that are located in a region between a vertical sidewall of said etched back anisotropic oxide and a vertical sidewall said semiconductor body and on said uppermost surface of said oxide liner, wherein said first portion of said gate electrode directly contacts said uppermost surface of said oxide liner and wherein a second portion of said gate electrode directly contacts an uppermost surface of said etched back anisotropic oxide, said first portion and said second portion of said gate electrode are located on one side of the semiconductor body and said uppermost surface of said etched back anisotropic oxide is vertically offset and located entirely beneath an uppermost surface of said semiconductor body and entirely beneath an uppermost surface of said gate electrode.