Patent ID: 6518628
Filing Date: 2003-02-11
Classification: H01L

Abstract:
An integrated CMOS circuit arrangement, comprising:a semiconductor substrate; at least one trench formed in a principal surface of the semiconductor substrate; a first MOS transistor arranged at the principal surface in a region doped with a first conductivity type wherein a current flow through the first MOS transistor occurs substantially parallel to a sidewall of the trench; a second MOS transistor, that is complementary to the first MOS transistor, arranged at a floor of the trench in a region doped with a second conductivity type which is opposite the first conductivity type wherein a current flow through the second MOS transistor occurs substantially parallel to the sidewall of the trench; and a doped, buried layer having a contact, the buried layer arranged in the semiconductor substrate at a level lower than the second MOS transistor wherein a source/drain region of the second MOS transistor connects to the buried layer.