Patent ID: 6972456
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns, wherein each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and control gates in the form of side walls formed along both side surfaces of the word gate, wherein each of the control gates includes a first control gate and a second control gate in mutual contact; a first insulating layer is disposed between the first control gate and the semiconductor layer, and a side insulating layer is disposed between the first control gate and the word gate; a second insulating layer is in direct contact with the second control gate and the semiconductor layer and disposed between the second control gate and the semiconductor layer; and a thickness of the first insulating layer is larger than a thickness of the second insulating layer.