Patent ID: 6429695
Filing Date: 2002-08-06
Classification: H03K

Abstract:
A differential comparison circuit comprising:a first MOS transistor using a gate terminal thereof as a first input terminal and a source terminal thereof as a second input terminal; a second MOS transistor having the same conduction type as that of said first MOS transistor, and using a gate terminal thereof as a third input terminal and a source terminal thereof as a fourth input terminal; a latch circuit having a first input/output terminal thereof connected to a drain terminal of said first MOS transistor and a second input/output terminal thereof connected to a drain terminal of said second MOS transistor; and a bias circuit for bringing said first and second MOS transistor into the same bias condition; wherein a difference of the input signals supplied to said first and second input terminals is compared with a difference of input signals supplied to said third and fourth input terminals, and a comparison result is outputted from said first and second input/output terminals.