Patent ID: 6215713
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A bitline decoder connected to a complementary pair of bitlines of a semiconductor memory carrying selected information in particular memory cells, said decoder comprising:first and second control circuits (CCs) respectively connected to said first and second complementary bitlines and to a first voltage;first and second nodes respectively connected to said first and second CCs, said first and second CCs controlling the application of a first voltage according to logical states sensed on respective ones of said bitlines;first and second cross-coupled circuits (XCs) respectively connected to said first and second CCs at said respective first and second nodes, said first and second XCs producing corresponding first and second output signals representative of information in particular cells of a semiconductor memory; anda done line and first and second control circuits connected to said done line and respectively controlled by said first and second nodes.