Patent ID: 8402349
Filing Date: 2013-03-19
Classification: G06F,G11C,H03M

Abstract:
1. A flash memory interface comprising: a flash memory controller configured to communicate with one or more flash memory devices; a data buffer configured to store write data for the one or more flash memory devices; and a data scramble unit configured to modify the write data to generate scrambled data to be written to the one or more flash memory devices, wherein the data scramble unit includes a first circuit coupled to receive, as an input, at least a portion of an address identifying a location in the one or more flash memory devices to which the scrambled data is to be written, wherein the data scramble unit is configured to perform a logic operation on the input to generate a seed, and wherein the data scramble unit further includes a pseudo-random number generator coupled to receive the seed and to generate a series of pseudo-random numbers from the seed, and wherein the data scramble unit is configured to generate the scrambled data responsive to the series of pseudo-random numbers and the write data from the data buffer, and wherein the data scramble unit is configured to transmit the scrambled data to the flash memory controller, and wherein the portion of the address comprises a least significant portion, and wherein the input to the first circuit is a width that is an integer multiple of a width of the least significant portion of the address, and wherein the first circuit is coupled to receive the least significant portion a plurality of times within the width of the input.