Patent ID: 8648841
Filing Date: 2014-02-11
Classification: G09G

Abstract:
1. A scan-line driving device for a LCD apparatus, comprising: a PWM signal generating circuit configured for outputting a PWM signal with a first potential and a second potential, the PWM signal further having a predetermined duty cycle; a first impedance having a first terminal and a second terminal; a second impedance having a first terminal and a second terminal, the resistance value of the second impedance being different from that of the first impedance, and the first terminal of the second impedance and the first terminal of the first impedance being both electrically coupled to a ground potential; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being electrically coupled to the ground potential; a first scan driver comprising a first core circuit and a first transistor, the first core circuit having a first PWM signal input terminal, the first transistor having a first source/drain terminal, a second source/drain terminal and a gate terminal, the first source/drain terminal of the first transistor being electrically coupled to the first PWM signal input terminal and the second terminal of the capacitor, the second source/drain terminal of the first transistor being electrically coupled to the second terminal of the first impedance, and the gate terminal of the first transistor being configured for receiving a turn-on control signal; and a second scan driver comprising a second core circuit and a second transistor, the second core circuit having a second PWM signal input terminal, the second transistor having a first source/drain terminal, a second source/drain terminal and a gate terminal, the first source/drain terminal of the second transistor being electrically coupled to the second PWM signal input terminal and the second terminal of the capacitor, the second source/drain terminal of the second transistor being electrically coupled to the second terminal of the second impedance, and the gate terminal of the second transistor being configured for receiving the turn-on control signal; wherein the PWM signal generating circuit comprises: a P-type transistor having a first source/drain terminal, a second source/drain terminal and a gate terminal, the first source/drain terminal of the P-type transistor being electrically coupled to a positive-charge pump, and the gate terminal of the P-type transistor being configured for receiving duty-cycle control signal; and a N-type transistor having a first source/drain terminal, a second source/drain terminal and a gate terminal, the first source/drain terminal of the N-type transistor being electrically coupled to a negative-charge pump, the second source/drain terminal of the N-type transistor being electrically coupled to the second source/drain terminal of the P-type transistor and configured for outputting the PWM signal, and the gate terminal of the N-type transistor being configured for receiving the duty-cycle control signal; an inverter electrically coupled between the gate terminal of the P-type transistor and the duty-cycle control signal and between the gate terminal of the N-type transistor and the duty-cycle control signal, the inverter having an input terminal and an output terminal, the input terminal of the inverter being configured for receiving the duty-cycle control signal, and the output terminal of the inverter being configured for outputting an inverted signal of the duty-cycle control signal.