Patent ID: 6510191
Filing Date: 2003-01-21
Classification: G06F,H03K,H03L

Abstract:
A frequency synthesizer comprising:a system clock for producing a reference clock signal oscillating at a first frequency; a controller for generating a frequency control value corresponding to an output clock signal having a second frequency; circuitry for producing from the frequency control value and the reference clock signal a series of address values; a look-up table (LUT) for storing a plurality of tap addresses, the LUT configured to receive the series of address values and, in response to receiving the series of address values, to output a series of tap addresses, each address value having one tap address associated therewith; a delay line configured to receive the reference clock signal and to produce therefrom a plurality of phase shifted clock signals, each phase shifted clock signal oscillating at the first frequency and being shifted in phase with respect to the reference clock signal and with respect to the other phase shifted clock signals; a selection circuit configured to receive the series of tap addresses and the plurality of phase shifted clock signals and to output, in response to receiving the series of tap addresses, a series of phase shifted clock signals, each tap address having a phase shifted clock signal associated therewith; and a sampling circuit configured to receive the series of phase shifted clock signals and to output in response thereto samples of the series of phase shifted clock signals in the temporal order the phase shifted clock signals are received by the sampling circuit, each sample including at least a portion of one of the phase shifted clock signals and the samples of the series of phase shifted clock signals forming the output clock signal at the second frequency.