Patent ID: 6343363
Filing Date: 2002-01-29
Classification: G06F,Y02D

Abstract:
A method of invoking a low power operational mode used in a programmed computer system, comprising the steps:(a) programming the computer system to cause a processor included in the computer system to execute instructions at least one of which is a halt instruction; (b) supplying clock signals to a plurality of subcircuits in the processor, the plurality of subcircuits including a pipeline subcircuit to execute the instructions and an interrupt handling subcircuit to handle interrupts generated by external interrupt logic; (c) executing in the pipeline subcircuit a halt instruction; (d) in response to the pipeline subcircuit executing the halt instruction, (i) entering the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generating an acknowledgement signal to the external logic indicating that the processor is entering the low power operational mode; (e) generating in the external logic an interrupt when the processor is in the low power mode; and (f) handling such interrupt in the interrupt handling subcircuit so as to increase the power consumption of the pipeline subcircuit.