Patent ID: 7791127
Filing Date: 2010-09-07
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising a plurality of memory cell transistors arranged in a matrix on a substrate, the semiconductor memory comprising: a first memory cell transistor including: a first floating gate electrode provided on the substrate and insulated from the substrate; and a first control gate electrode provided on the first floating gate electrode and insulated from the first floating gate electrode; and a second memory cell transistor adjacent to the first memory cell transistor in a row direction of the matrix, the second memory cell transistor including: a second floating gate electrode provided on the substrate and insulated from the substrate and separated from the first floating gate electrode, an upper surface of the second floating gate electrode being larger than a lower surface of the second floating gate electrode, and the upper surface of the second floating gate electrode being lower than an upper surface of the first floating gate electrode; and a second control gate electrode provided on the second floating gate electrode and insulated from the second floating gate electrode.