Patent ID: 7898284
Filing Date: 2011-03-01
Classification: B82Y,H01L

Abstract:
1. An asynchronous nanoelectronic circuit configured to operate according to quasi-delay insensitive principles, comprising: a compute tile having an n-plane, a p-plane and a routing plane, said compute tile including at least a first logic element and a second logic element, said first logic element having at least a first input and at least a first output, said second logic element having at least a second input and at least a second output, said first input and said second input each configured to receive an input signal, said first output and said second output each configured to be connected to one of a high reference voltage via a pullup element and a low reference voltage via a pulldown element; and a state-holding element connected to at least one of said first output and said second output, said state-holding clement comprising a selected one of a C-element, a precharge function-block, and a read-write register, said state-holding element configured to hold steady a state of at least one of said first output and said second output during a time when at least one of said first output and said second output is disconnected from a respective one of said high reference voltage and said low reference voltage; said asynchronous nanoelectronic circuit configured to provide a computationally stable output according to quasi-delay insensitive principles.