Patent ID: 6218234
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method for fabricating an analog capacitor integrated circuit device comprising:providing an isolation region separating a first active area from a second active area in a semiconductor substrate;providing a first gate oxide layer overlying said semiconductor substrate in said first and second active areas;depositing a first polysilicon layer overlying said first gate oxide layer and said isolation region;depositing an oxide layer overlying said first polysilicon layer;depositing a nitride layer overlying said oxide layer;thereafter etching away said nitride layer, said oxide layer, and said first polysilicon layer where they are not covered by a mask to form a first polysilicon gate electrode in said first active area and to form a polysilicon capacitor bottom plate and overlying capacitor dielectric comprising said oxide layer and said nitride layer overlying said isolation region;thereafter removing said first gate oxide layer in said second active area andforming a second gate oxide layer overlying said semiconductor substrate in said second active area wherein said second gate oxide layer has a thickness less than the thickness of said first gate oxide layer;depositing a second polysilicon layer overlying said second gate oxide layer, said bottom capacitor plate and capacitor dielectric, and said first polysilicon gate electrode;thereafter etching away said second polysilicon layer where it is not covered by a mask to form a second polysilicon gate electrode in said second active area and to form a top capacitor plate overlying said bottom capacitor plate having said capacitor dielectric layer therebetween; andcompleting said analog capacitor integrated circuit device.