Patent ID: 6799231
Filing Date: 2004-09-28
Classification: G06F

Abstract:
A virtual input/output (I/O) device coupled to a memory controller in a microprocessor of a computer, the virtual I/O device and a memory unit being arranged to communicate with the memory controller via a common interface so that any of a plurality of peripherals connected to the virtual I/O device is capable of coupling to an arithmetic and logic unit (ALU) in the microprocessor via the virtual I/O device and the memory controller sequentially, wherein the ALU is capable of writing an instruction packet into the virtual I/O device via the memory controller when a peripheral device is to be commanded by the ALU, the virtual device sends the written instruction packet to the peripheral, and the peripheral is commanded by the microprocessor to perform an assigned task in response to receiving of the instruction packet; and wherein, in response to receiving of a response packet from the peripheral, the virtual I/O device commands the ALU to read the received response packet from the virtual I/O device via the memory controller.