Patent ID: 9183334
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method of verifying connectivity of signals in a circuit design, comprising: on a programmed processor, performing operations including: inputting parameter values that customize a parameterizable version of the circuit design; generating a configured version of the circuit design based on the input parameter values, wherein the configured version specifies connections from a plurality of source pins of ports of circuit blocks of the configured version to a plurality of destination pins of ports of circuit blocks of the configured version; determining from the input parameter values, expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version; and generating a connectivity checker that includes an HDL code, wherein for each expected source-destination connection of the expected source-destination connections the HDL code forces a first signal value on a source pin of said each expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of said each expected source-destination connection matches the first signal value.