Patent ID: 8489902
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of chips configured to receive an external voltage, wherein each one of the chips is configured to detect a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic, wherein each one of the chips comprises: a signal delay characteristic detection block configured to detect the signal delay characteristic using a clock signal and to generate a code signal corresponding to the signal delay characteristic by counting the clock signal; and an internal voltage generation block configured to control a level of the internal voltage based on the code signal and to output the internal voltage, wherein the count clock signal is generated in a delay interval of a divided clock signal based on the divided clock signal, a delayed divided clock signal, and the clock signal, wherein the divided clock signal is generated by dividing frequency of the clock signal, and wherein the delayed divided clock signal is generated by delaying the divided clock signal.