Patent ID: 8178909
Filing Date: 2012-05-15
Classification: G11C,H01L,H03K,Y10S

Abstract:
1. A dual port memory cell, comprising a pair of layout cells arranged adjacent to each other and comprising a fixed set of patterned layers and contacts below and inclusive of a first layer of metal interconnect that are substantially identical to each other within each of the pair of layout cells; a second layer of metal interconnect dielectrically spaced above the first layer of metal interconnect, wherein a first via extends between the first layer of metal interconnect and the second layer of metal interconnect to each other, wherein the location of the first via or the location of a part of the second layer of metal interconnect in a first of the pair of layout cells is different from the location of the first via or the location of the part of the second layer of metal interconnect in the second of the pair of layout cells, and wherein the second layer of metal interconnect comprises two complementary pairs of bit lines extending in a first direction; and a third layer of metal and interconnect dielectrically spaced about the second layer of metal interconnect, wherein a second via extends between the second layer of metal interconnect and the third layer of metal interconnect to each other, wherein the location of the second via or the location of a part of the third layer of metal interconnect in the first of the pair of layout cells is different from the location of the second via or the location of the part of the second layer of metal interconnect in the second of the pair of layout cells, and wherein the third layer of metal interconnect comprises a first word line and a second word line extending in a second direction perpendicular to the first direction.