Patent ID: 7870524
Filing Date: 2011-01-11
Classification: G01R

Abstract:
1. A computer-implemented method for verifying the performance of a unit in an integrated circuit, the method comprises: generating, by a processor during processing of a performance measuring tool, expected performance data, expected functional outputs, and interface transactions for the unit based on system level stimulus for the entire integrated circuit; embedding the expected performance data in the interface transactions, wherein the expected performance data resides in a data structure with identification information of the unit and a start trigger indicative of a beginning of a test or a end trigger indicative of an end to the test; applying, by the processor during processing of a register transfer level (RTL) implementation of the unit, the interface transactions to generate actual functional outputs and actual performance data for the unit; verifying whether the actual functional outputs are correct based on the expected functional outputs; and determining whether the expected performance of the unit is achieved based on the comparison between the expected performance data and the actual performance data.