Patent ID: 6559821
Filing Date: 2003-05-06
Classification: G09G,H01L,H04N

Abstract:
A matrix substrate comprising:a shift register for scanning provided with an inverter at an output stage of said shift register; and a sampling transistor for sampling an output from the inverter of said shift register for scanning, wherein said sampling transistor is provided with a CMOS transistor, the inverter of the output stage is connected to gates of pMOS and nMOS, each forming a part of the CMOS transistor of said sampling transistor, and, when the CMOS transistor of said sampling transistor is turned off, a timing of inputting, into the gate of the pMOS, the output from the inverter connected to the gate of pMOS of the CMOS transistor of the sampling transistor is earlier than a timing of inputting, into the gate of nMOS, the output from the inverter connected to the gate of said n-MOS of the CMOS transistor of the sampling transistor.