Patent ID: 6693827
Filing Date: 2004-02-17
Classification: G11C

Abstract:
A memory cell sensing circuit comprising:a main cell and a reference cell; a first loading unit for providing a preset voltage to a sensing node of the main cell; a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell; a first switching unit for adjusting the potential of the sensing node of the main cell; a second switching unit for controlling the potential of the sensing node of the reference cell; a main cell bit line voltage controlling unit coupled to the sensing node of the main cell, for adjusting the potential of a bit line of the main cell; a reference cell bit line voltage controlling unit coupled to the sensing node of the reference cell, for adjusting the potential of a bit line of the reference cell; and a sense amplifier for sensing a state of the main cell by comparing the potential of the sensing node of the main cell and that of the sensing node of the reference cell.