Patent ID: 9196749
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A programmable device comprising: a first well having a top surface and a bottom surface, the first well of a first conductivity type; a transistor having a source region of a second conductivity type within the first well, a drain region of the second conductivity type within the first well, an insulating layer disposed over the top surface of the first well, and a gate disposed over the insulating layer; a substrate region surrounding the first well, having a top surface and a bottom surface, the substrate region of the first conductivity type; a junction of the second conductivity type disposed within the substrate region; a second well surrounding the substrate region, the second well having a top surface and a bottom surface, the second well of the first conductivity type, wherein the junction, the first well and the second well are included as portions of a junction field effect transistor (JFET); and a guard ring surrounding the second well, the guard ring having a top surface and a bottom surface, the guard ring of the second conductivity type.