Patent ID: 8359445
Filing Date: 2013-01-22
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a memory controller; a plurality of memory components; a control bus coupled to the memory controller and coupled to each memory component of the plurality of memory components at a different point along its length such that respective, different times are required for control information to propagate on the control bus from the memory controller to each memory component of the plurality of memory components; a plurality of dedicated differential data signaling paths coupled to the memory controller, each dedicated differential data signaling path of the plurality of dedicated differential data signaling paths coupled respectively to a memory component of the plurality of memory components; and wherein the memory controller includes circuitry to transmit respective differential data signals to the plurality of memory components via the plurality of dedicated differential data signaling paths after delaying by respective, different time intervals to at least account for the respective, different times required for the control information to propagate on the control bus from the memory controller to each respective memory component of the plurality of memory components.