Patent ID: 6300172
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of fabricating an SOI transistor device, comprising the sequential steps of:providing a silicon semiconductor structure;forming a silicon oxide layer over said silicon semiconductor structure;forming a silicon-on-insulator layer over said silicon oxide layer;implanting a well in said silicon-on-insulator layer;growing a gate oxide layer over said silicon-on-insulator layer;depositing a polysilicon layer over said gate oxide layer;patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer;filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs);patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls;removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs;forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor;forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; andforming silicide regions on said source and drain.