Patent ID: 7709365
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A method for forming a CMOS well structure, comprising: forming a first mask on a substrate, the first mask having a plurality of openings; etching the substrate between the plurality of openings in the first mask to a predetermined depth; forming a plurality of first conductivity type wells over the substrate, each of the plurality of first conductivity type wells formed in a respective opening in the first mask; removing upper portions of the plurality of first conductivity type wells to a predetermined depth lower then an upper surface of the first mask; forming a silicon dioxide cap over each of the first conductivity type wells; removing the first mask; forming a plurality of first conductivity type implant regions in the substrate, each of the plurality of first conductivity type implant regions formed in a respective exposed surface of the substrate; forming sidewall spacers on sidewalls of each of the first conductivity type wells; and forming a plurality of second conductivity type wells, each of the plurality of second conductivity type wells being formed between respective first conductivity type wells, wherein the plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process over exposed surfaces of the first conductivity type implant regions.