Patent ID: 7646664
Filing Date: 2010-01-12
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first memory cell block includes a first plurality of word lines on the first semiconductor layer including a first word line of the first plurality coupled to a first row of memory cells on the first semiconductor layer, wherein the second memory cell block includes a second plurality of word lines on the second semiconductor layer including a second word line of the second plurality coupled to a second row of memory cells on the second semiconductor layer, wherein the first plurality of word lines including the first word line is between the first and second semiconductor layers, and wherein the second semiconductor layer is between the first plurality of word lines and the second plurality of word lines; a first row decoder adjacent the memory cell array wherein the first row decoder is configured to control the first word line; a second row decoder adjacent the memory cell array wherein the second row decoder is configured to control the second word line; a first wiring electrically connecting the first row decoder and the first word line, the first wiring including a first word line contact electrically contacting the first word line in a direction perpendicular with respect to the first semiconductor layer, a first metal line electrically connected to the first word line contact in a direction parallel with respect to the first semiconductor layer, and a first decoder contact electrically connected between the first metal line and the first decoder in a direction perpendicular with respect to the first semiconductor layer; a second wiring electrically connecting the second row decoder and the second word line; and an insulating layer on the second semiconductor layer and on the second word line wherein the second semiconductor layer is between the first semiconductor layer and the insulating layer, wherein the first metal line is disposed on the insulating layer so that the insulating layer is between the first metal line and the first row decoder.