Patent ID: 6735223
Filing Date: 2004-05-11
Classification: H04J,H04L,H04Q

Abstract:
An apparatus for transmitting a packet in a packetizing system, comprising:an adder for generating a time stamp value by adding a cycle time value corresponding to a data segmentation size to an offset value which is set based on at least one of a data delay time and an amount of jitter; a memory for receiving and storing input data according to the time stamp in units of packets; a window generator for estimating the time stamp value generated by the adder and determining a transmission time range; and a controller for adding the time stamp generated by the adder to the input data in units of packets, which are stored in the memory, controlling the output of the input data in units of packets, to which the time stamp is added, from the memory, and controlling the offset value when overflow generated by read and write timing errors is detected in the memory.