Patent ID: 7535784
Filing Date: 2009-05-19
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first cell array which has a plurality of memory cells arrayed in row and column directions; a word line which is connected to the plurality of memory cells arrayed in the row direction; a first bit line which is connected to the plurality of memory cells arrayed in the column direction in the first cell array; a first sense amplifier which is connected to the first bit line; a first dummy cell array which has a plurality of dummy cells arrayed in row and column directions; a dummy word line which is connected to the plurality of dummy cells arrayed in the row direction; a first dummy bit line which is connected to the plurality of dummy cells arrayed in the column direction in the first dummy cell array and receives an output from the dummy word line; a first sense amplifier activation circuit which activates the first sense amplifier in accordance with a first control signal output from the first dummy bit line; a second cell array which has a plurality of memory cells arrayed in the row and column directions, the plurality of memory cells arrayed in the row directions being connected to the word line; a second bit line which is connected to the plurality of memory cells arrayed in the column direction in the second cell array; a second sense amplifier which is connected to the second bit line; a second dummy cell array which has a plurality of dummy cells arrayed in row and column directions, the plurality of dummy cells arrayed in the row directions being connected to the dummy word line, the plurality of dummy cells arrayed in the column directions being located between the first cell array and the second cell array, and the plurality of dummy cells arrayed in the column directions being connected to the word line; a second dummy bit line which is connected to the plurality of dummy cells arrayed in the column direction in the second dummy cell array and receives the output from the dummy word line; and a second sense amplifier activation circuit which activates the second sense amplifier in accordance with a second control signal output from the second dummy bit line.