Patent ID: 6247070
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A memory system comprising:a memory controller;a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;a first bidirectional data bus coupled to the memory controller, the memory controller communicating first data information to the bidirectional data bus for a write operation and receiving the first data information from the bidirectional data bus during a read operation;a second bidirectional data bus coupled to the memory controller, the memory controller communicating second data information to the second bidirectional data bus for a write operation and receiving the second data information from the second bidirectional data bus during a read operation;a first and second memory module, the first and second memory module each having a first memory subsystem and a second memory subsystem; anda first and second socket, the first socket adapted to receive the first memory module and to couple the first memory module to the unidirectional command and address bus and to the first bidirectional data bus, the second socket adapted to receive the second memory module and to couple the second memory module to the unidirectional command and address bus and to the second bidirectional data bus.