Patent ID: 6798420
Filing Date: 2004-09-28
Classification: G06T,G09G,H04N

Abstract:
A system comprising:an input for receiving compressed video data; an input for receiving data representing graphics; a video decoder for processing the compressed video data to generate a video for displaying; a display engine for processing the data representing graphics to generate graphics for displaying; and means for overlaying the video and the graphics to generate an output video, wherein the display engine includes a plurality of line buffers that are used during conversion of a graphics format from a first format to a second format which is compatible with a video format, wherein the line buffers are implemented in a single-port RAM configured to simulate a dual-port RAM, wherein the single-port RAM has been configured to be twice as wide and half as deep, and wherein two words are concurrently read in a read operation during a first memory access cycle, and two words are concurrently written in a write operation during a second memory access cycle, and wherein the read operation during the first memory access cycle and the write operation during the second memory access cycle immediately following the first memory access cycle can be performed on a same one of the line buffers or different ones of the line buffers.