Patent ID: 6767820
Filing Date: 2004-07-27
Classification: H01L

Abstract:
The process of forming a solderable top surface for a semiconductor die having a metallic top electrode structure; said process comprising the deposition of a mask layer over the surface of a wafer containing a plurality of identical die having said metallic top electrode structure; photolithographically opening at least first and second openings in said mask layer over each of said plurality of die; depositing a first metal layer which adheres to metallic electrode over said mask layer and onto the metallic electrode surface exposed by said at least first and second openings; depositing a second metal layer which is solderable over said first metal layer; removing said mask layer and the first and second metal layers overlying said mask layer and leaving in place the metals formed in said at least first and second openings, forming a passivation insulation layer over the silicon surface exposed by the removal of said mask layer with said metals remaining in said at least first and second openings and protruding beyond the surface of said passivation insulation layer and terminating in a common plane above said passivation layer; and thereafter singulating said die from said wafer.