Patent ID: 9082515
Filing Date: 2015-07-14
Classification: G11C

Abstract:
1. A variable resistance nonvolatile memory device comprising: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, the variable resistance element having a resistance state which reversibly changes between a first low resistance state by an application of a first low-resistance write pulse and a first high resistance state by an application of a first high-resistance write pulse, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; a memory cell selection circuit that selects at least one of the memory cells from the memory cell array by selecting at least one of the word lines and at least one of the bit lines; a write circuit that rewrites a resistance value of the variable resistance element of the selected memory cell by applying a voltage pulse to the selected memory cell; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in the first low resistance state, wherein the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in an inactive state, and the write circuit sets the faulty memory cell detected by the detection circuit to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state.