Patent ID: 9110135
Filing Date: 2015-08-18
Classification: G01R

Abstract:
1. A method of testing a chip comprising: scanning first input data into a first scan channel, wherein the first scan channel comprises a first plurality of scannable latches configured to apply the first input data to logic circuits on the chip and further configured to receive first output data from the logic circuits on the chip; scanning second input data into a second scan channel, wherein the second scan channel comprises a second plurality of scannable latches configured to apply the second input data to the logic circuits on the chip and further configured to receive second output data from the logic circuits on the chip; hashing output data from the first scan channel using a first XOR on the first scan channel; hashing output data from the second scan channel using a first XOR on the second scan channel; hashing output data from the first XOR on the first scan channel using a second XOR on the first scan channel; outputting data from the second XOR on the first scan channel to a rotator; creating adjustment data using the output data from the second XOR on the first scan channel by the rotator; transmitting the adjustment data to a second XOR on the second scan channel; and hashing the adjustment data and output data from the first XOR on the second scan channel using a second XOR on the second scan channel.