Patent ID: 7046543
Filing Date: 2006-05-16
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: memory cells arranged in rows and columns, each memory cell including a capacitor including a cell plate electrode for receiving a reference voltage, and a storage electrode arranged facing to the cell plate node, for accumulating electric charges corresponding to storage data; a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells on a corresponding row, the word lines comprising an interconnection line formed in a same interconnection layer as the cell plate electrodes, the cell plate electrodes and the word lines being arranged in pairs; word line selecting circuitry for selecting a word line arranged corresponding to an addressed row in accordance with an address signal; and cell plate voltage control circuitry for changing a voltage of a cell plate electrode provided for a selected word line on the addressed row from a predetermined reference voltage level after the word line is selected, and returning the cell plate electrode voltage to the reference voltage level when the selected word line is deactivated, and maintaining the voltage level of the cell plate electrode for a non-selected word line other than the selected word line at the reference voltage level.