Patent ID: 6372559
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of forming a self-aligned vertical double gate MOSFET device comprising the steps of:(a) growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; (b) patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; (c) forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; (d) removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; (e) recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; (f) forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; (g) selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cmâˆ’2 or greater; (h) selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; (i) removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; (j) etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and (k) saliciding any exposed silicon surfaces.