Patent ID: 9042172
Filing Date: 2015-05-26
Classification: G11C

Abstract:
1. A packaged SPI-NAND flash memory device comprising: an eight pin package comprising active pins DI/IO0, DO/IO1, WPb/IO2, HOLDb/IO3, CLK, and CSb, a VDD pin, and a GND pin in compliance with a SPI protocol; an internal supply voltage generator coupled to the VDD pin for receiving an external supply voltage VDD and generating an internal supply voltage INTVDD from the external supply voltage VDD; a selectable-level buffer coupled to the active pins, and further being coupled to the VDD pin and to the internal supply voltage generator for selectively operating the active pins at the external supply voltage VDD or at the internal supply voltage INTVDD; a NAND flash memory array; a page buffer coupled to the NAND flash memory array; an input/output control circuit coupled to the selectable-level buffer and to the page buffer for controlling data flow between the selectable-level buffer and the page buffer; and control logic coupled to the selectable-level buffer, the input/output control circuit, the page buffer, and the flash memory array for controlling memory read, program and erase operations of the NAND flash memory array in accordance with commands received via the selectable-level buffer.