Patent ID: 7563676
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method for manufacturing a non-volatile memory cell array, the method comprising the steps of: (a) forming a plurality of isolation layers a predetermined distance apart from each other and parallel to each other, on a semiconductor substrate; (b) forming a plurality of lines orthogonal to the isolation layers and a predetermined distance apart from each other, in which the lines include a tunnel oxide layer, a first electrode layer, an inter-electrode dielectric layer, and a first capping layer; (c) forming an insulating spacer on a sidewall of each line; (d) forming a source area by implanting a first dopant into an upper part of the semiconductor substrate between the lines; (e) selectively removing the first capping layer from the lines; (f) forming a common source line on the source area between neighboring insulating spacers while forming a pair of second electrode layers a predetermined distance apart from each other on the inter-electrode dielectric layers; (g) forming a plurality of gates opposite to each other by removing a portion of the line exposed between the second electrode layers; and (h) forming a drain area by implanting a second dopant into an upper part of the semiconductor substrate between the gates.