Patent ID: 6313522
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A semiconductor structure comprising:a base substrate having a first surface including a first plurality of base substrate bond pads formed thereon;a first substrate having a first surface, a second surface and at least one cavity formed therein, one of said first and second surfaces including a first plurality of first substrate bond pads, at least one of said first plurality of first substrate bond pads being electrically coupled to at least one of said first plurality of base substrate bond pads;at least one semiconductor device having a plurality of semiconductor device bond pads, said at least one semiconductor device being positioned generally within said at least one cavity between said base substrate and said first substrate with at least one of said plurality of semiconductor device bond pads electrically coupled to at least one of said first plurality of base substrate bond pads; anda plurality of said semiconductor devices, each of said plurality of semiconductor devices comprising a plurality of bond pads formed thereon, and wherein said first substrate comprises a plurality of cavities, each of said plurality of semiconductor devices being positioned within respective ones of said plurality of cavities with at least one of said plurality of bond pads of each of said plurality of semiconductor devices being electrically coupled to respective ones of said plurality of bond pads of said base substrate.