Patent ID: 8969167
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a mold structure on a lower structure; patterning the mold structure to form a plurality of holes exposing the lower structure; forming a protection layer on sidewalls of the mold structure exposed by the holes; forming lower electrodes in the holes provided with the protection layer; removing the mold structure to expose the protection layer; removing the protection layer to expose sidewalls of the lower electrodes; and sequentially forming a dielectric film and an upper electrode on the lower electrodes; wherein the forming of the mold structure comprises sequentially stacking a mold layer and a supporting layer having an etch selectivity with respect to the mold layer, on the lower structure, and wherein the protection layer is locally formed on the sidewall of the mold layer to expose a sidewall of the supporting layer.