Patent ID: 9214396
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A method of forming a transistor device, comprising the subsequently performed steps: forming a gate electrode on a first semiconductor material layer; forming an interlayer dielectric over said gate electrode and said first semiconductor material layer; forming a first opening in said interlayer dielectric at a predetermined distance laterally spaced from said gate electrode on one side of said gate electrode and a second opening in said interlayer dielectric at a predetermined distance laterally spaced from said gate electrode on another side of said gate electrode, said first and second openings reaching to said first semiconductor material layer; forming cavities in said first semiconductor material layer through said first and second openings formed in said interlayer dielectric; and performing at least one epitaxial growth process through said first and second openings to form embedded second semiconductor material layers in said cavities, said embedded second semiconductor material layers completely filling said cavities.