Patent ID: 6440828
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A process of fabricating a semiconductor device on a substrate, comprising the steps of:a) preparing a crystalline silicon layer including a first region having a first conductivity type and a second region spaced apart from said first region and having a second conductivity type opposite to said first conductivity type; b) forming an insulating layer over said crystalline silicon layer; c) forming a first opening and a second opening in said insulating layer so as to expose said first region and said second region to said first opening and said second opening, respectively; d) implanting a first dopant impurity of said first conductivity type into said first region and said second region through said first opening and said second opening so as to make said first region and said second region amorphous; e) covering said first region with a mask; f) implanting a second dopant impurity of said second conductivity type into said second region through said second opening in a quantity greater than said first dopant impurity so as to maintain said second region in said second conductivity type; g) removing said mask; h) depositing a refractory metal layer on the amorphous first region and the amorphous second region so that said refractory metal layer is in contact with said amorphous first region and said amorphous second region; and i) treating said refractory metal layer with heat so as to partially convert said refractory metal layer to refractory metal silicide layers in contact with said amorphous first and amorphous second regions.