Patent ID: 6320426
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A self-calibrating circuit of a high speed comparator, supplied with a power source from a first voltage source and a second voltage source, wherein the high speed comparator comprises a latch control terminal, a first analog input terminal, a second analog input terminal, a first digital output terminal, and a second digital output terminal, the latch control terminal receives a latch signal, the first analog input terminal receives a first analog signal, the second analog input terminal receives a second analog signal, the first digital output terminal outputs a first digital signal, and the second digital output terminal outputs a second digital signal, the self-calibrating circuit comprising:a first negative phase logic switch, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the latch control terminal;a second negative phase logic switch, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the second digital output terminal;a first positive phase logic switch, comprising a power source terminal coupled to the first digital output terminal, a control terminal coupled to the second digital output terminal, and a load terminal;a second positive phase logic switch, comprising a power source terminal coupled to the load terminal of the first positive phase logic switch, a control terminal coupled to the first analog input terminal, and a load terminal;a third negative phase logic switch, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the second digital output terminal, and a control terminal coupled to the latch control terminal;a fourth negative phase logic switch, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the second digital output terminal and a control terminal coupled to the first digital output terminal;a third positive phase logic switch, comprising a power source terminal coupled to the second digital output terminal, a control terminal coupled to the first digital output terminal and a load terminal;a fourth positive phase logic switch, comprises a power source terminal coupled to the load terminal of the third positive phase logic switch, a load terminal coupled to the load terminal of the second positive phase logic switch, and a control terminal coupled to the second analog input terminal;a fifth positive phase logic switch, comprising a power source terminal coupled to the load terminal of the second positive phase logic switch, a load terminal coupled to the second voltage source, and a control terminal coupled to the latch control terminal;a first current source circuit, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the first positive phase logic switch, and a data control terminal;a second current source circuit, comprising a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the third positive phase logic switch, and a data control terminal; anda control logic circuit, comprising a calibration control terminal, a latch signal input terminal, a first data output terminal, a second data output terminal and a digital signal input terminal, wherein the calibration control terminal receives a calibration signal, the latch signal input terminal is coupled to the latch control terminal, the first data output terminal is coupled to the data control terminal of the first current source circuit, the second data output terminal is coupled to the data control terminal of the second current source circuit, and the digital signal input terminal is coupled to the first digital output terminal.