Patent ID: 6339807
Filing Date: 2002-01-15
Classification: G06F

Abstract:
A multiprocessor system having a plurality of processor elements operating independently and transmitting information through a common bus, comprising:a request value generator generating a bus request value according to a priority level of the processor element when the processor element requests a utilization of the common bus, said priority level being variable, a transmitter transmitting a bus request signal and bus request value to the bus when the processor element requests the utilization of the common bus, a controlling circuit judging the priority of utilizing the bus according to the utilization situation of the common bus and the bus request value of the processor element transmitting the bus request signal when the processor element transmits the bus request signal, and a bus arbitrating circuit connected to the common bus to determine which processor element will utilize the common bus according to the utilization situation of the bus and the priority levels of the processor elements transmitting bus request signals to the common bus where there is a plurality of processor elements transmitting bus request signals and said controlling circuit can not determine which processor element having priority of utilizing the bus.