Patent ID: 7656714
Filing Date: 2010-02-02
Classification: G11C

Abstract:
1. A memory device comprising: a memory cell; a plurality of serially connected bitline selection transistors connected to the memory cell via a bitline; a high voltage generating circuit configured to provide a high voltage that is higher than a power voltage to the bitline selection transistors; a bitline bias transistor connected between a sense amplifier and the bitline selection transistors; a bitline bias circuit configured to receive the high voltage supplied from the high voltage generating circuit and to supply the high voltage supplied from the high voltage generating circuit as a bias voltage to the bitline bias transistor in parallel with the high voltage provided to the bitline selection transistors in response to a driving voltage, wherein the bitline bias circuit is also configured to maintain the bitline bias voltage at a substantially constant level during a read operation, wherein the sense amplifier connected to the bitline bias transistor is configured to sense and amplify a current of the bitline, wherein the driving voltage is generated when a division voltage is lower than a reference voltage, and wherein the division voltage is generated by dividing the bias voltage.