Patent ID: 8884682
Filing Date: 2014-11-11
Classification: H01L,H03K

Abstract:
1. A power semiconductor device comprising: an output transistor connected between a power supply terminal and an output terminal; a control circuit configured to control a charging operation and a discharging operation of a first node connected with a gate of the output transistor and control an ON/OFF condition of the output transistor; a first discharge route from the first node to the output terminal; and a second discharge route from the first node to a ground terminal, wherein a period during which the output transistor is in the ON condition stably after the first node is charged is an ON period, and a period during which the output transistor is the OFF condition stably after the first node is an OFF period, wherein a transition period from the OFF period to the ON period is a turn-on period, and a transition period from the ON period to the OFF period is a turn-off period, wherein in the turn-on period and the ON period, the control circuit charges the first node, and deactivates the first discharge route and the second discharge route, wherein in the turn-off period and the OFF period, the control circuit deactivates the second discharge route and activates the first discharge route, and discharges from the first node through the first discharge route, wherein when a load abnormality has occurred, the control circuit activates both of the first discharge route and the second discharge route to discharge from the first node through both of the said first discharge route and the second discharge route, wherein the second discharge route comprises: a discharge transistor having a drain which is connected with the first node, and a source and a back gate which are connected with the second node; and a countercurrent prevention device connected between the second node and a third node to prevent a flow of current from the third node to the second node, wherein when the load abnormality has occurred, the control circuit turns on the discharge transistor, and in the OFF period at least, the control circuit sets a gate voltage of the discharge transistor to a high level.