Patent ID: 6653712
Filing Date: 2003-11-25
Classification: G11C,H01L

Abstract:
A memory array disposed above a substrate comprising:a first plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction; a second plurality of parallel spaced-apart rail-stacks disposed above the first rail-stacks, the second plurality of rail-stacks running in a second direction different than the first direction such that a projection of the second rail-stack on the first rail-stack defines intersections with the first plurality of rail-stacks; a layer of low conducting material separating the first plurality of rail-stacks from the second plurality of rail-stacks, the layer of low conducting material at each intersection of the first and second rail-stacks separating a first conductivity type doped silicon material in one of the first rail-stacks from a second conductivity type doped silicon material in one of the second rail-stacks; and wherein the silicon on one side of each intersection is more lightly doped than the silicon on the opposite side of each intersection, such that the passage of a current equal to or greater than a predetermined threshold from one of the first rail-stacks to one of the second rail-stacks causes a diode to form at the intersection of these rail-stacks.