Patent ID: 7840777
Filing Date: 2010-11-23
Classification: G06F

Abstract:
1. In a computer, the computer comprising a memory, a reconfigurable computational array of logic elements interconnected in a dedicated static fashion, each logic element selecting inputs from other previous logic elements and reconfigured in parallel (hereafter as array), a successively configurable data pipe that communicates operating data bi-directionally between the memory and the array (hereafter as data pipe), and a successively configurable instruction pipe that communicates reconfiguration data to the array (hereafter as instruction pipe), a method of computing, the method comprising: (a.) the memory communicatively coupled with the instruction pipe, and the data pipe and storing a plurality of instructions each comprising reconfiguration data for reconfiguring the array, a plurality of data directives that control all data movement to and from the memory, to and from the array, and to the instruction pipe, operating data, and safe settling time data for determining a number of memory cycles to wait before latching data processing results settled in the array; (b.) the data pipe successively configured for moving input operating data from the memory and into the array in accordance with the data pipe executing the plurality of data directives; (c.) the array for processing the operating data in accordance with the reconfiguration data; (d.) reconfiguring the array in accordance with the reconfiguration data at a time zero; (e.) successively configuring the data pipe in accordance with the data pipe executing the plurality of data directives; (f.) communicating output operating data to the data pipe; (g.) communicating the input operating data from the data pipe to the array; and (h.) directing the array to latch a data processing result comprising output operating data after a time equal to time zero plus a safe settling time determined by the safe settling time data.