Patent ID: 7412672
Filing Date: 2008-08-12
Classification: G01R

Abstract:
1. A method for generating broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of: a) compiling the HDL (hardware description language) code modeled at gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model; b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions; c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model; d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing; and e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met, wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above; and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.