Patent ID: 6509766
Filing Date: 2003-01-21
Classification: G06F,H03K

Abstract:
A method of multiplying an input clock signal having a first cycle time to obtain an output clock signal having a selected cycle time which is shorter than said first cycle time, comprising:a) generating a pulse in response to an input clock signal, said input clock signal having a first cycle time; b) delaying said pulse by a time delay; c) generating a second pulse in response to said delayed pulse; d) delaying said second pulse by said time delay; e) repeating c) and d) zero or more times to generate a train of pulses including said delayed pulse and at least one said second pulse, said train of pulses being generated within said first cycle time; f) adjusting said time delay based on a number of pulses in said pulse train, and repeating a) through f) to obtain an output clock signal having a selected cycle time which is shorter than said first cycle time.