Patent ID: 6718477
Filing Date: 2004-04-06
Classification: G06F

Abstract:
In an integrated circuit, a delay lock loop comprising:a reference delay line having a first input programmably coupled to one of an external clock and an internal clock and selectably coupled through an inverter programmably disposed in series with said reference delay line; a feedback delay line having an input programmably coupled to a feedback clock and selectably coupled through an inverter programmably disposed in series with said feedback delay line; a phase detector having an input programmably coupled to an output of said reference delay line and a second input coupled to an output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; a control logic circuit having an input programmably coupled to an output of said phase detector; a programmable delay line having inputs programmably coupled to the control logic circuit to receive data, a clock input coupled to said reference clock and an output; a clock doubler having an input programmably coupled to said output of said delay line; and a clock tree having an input programmably coupled to an output of said clock doubler and an output forming the feedback clock coupled to said input of said feedback delay line.