Patent ID: 6411230
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A circuit arrangement for converting a parallel data stream into a serial data stream and for intermediate storage and clocked supply of the data stream, characterized in that a first shift register (1) is provided in which the parallel data stream is stored in bit frames in dependence upon an externally supplied processor clock and which supplies a serial data stream by means of bit-wise scanning of the stored data, which serial data stream is applied in parallel to all memory locations of a second, bit-wise addressable shift register (2) from which the data stored therein are serially read in dependence upon a serial clock, and which supplies the serial data stream, in that the second shift register (2) is assigned to a load shift register (3) supplying a level indicator which constantly marks the limit between memory cells of the second shift register (2) with valid, stored data and memory cells which are to be newly written with data, and in that storage of the data supplied by the first shift register (1) in the second shift register (2) is effected in dependence upon the level indicator in such a way that a bit present in all memory cells of the second shift register (2) and supplied by the first shift register (1) is stored in that memory cell to be newly written with data which is most proximate to the level indicator and adjoins the memory cells written with valid data.