Patent ID: 7476933
Filing Date: 2009-01-13
Classification: H01L

Abstract:
1. An apparatus comprising: a semiconductor substrate having an array portion and a logic portion; at least one U-shaped semiconductor structure formed in the substrate array portion, the semiconductor structure comprising a first source/drain region positioned atop a first pillar, a second source/drain region positioned atop a second pillar, and a U-shaped channel connecting the first and second source/drain regions, wherein the U-shaped channel is contiguous with the semiconductor substrate; an elongated spacer formed adjacent to the U-shaped semiconductor structure, wherein the elongated spacer is formed in an intermediate-depth trench that is deeper than a shallow trench that separates the first pillar from the second pillar, the intermediate-depth trench having a floor defined by the semiconductor substrate; a deep trench having a floor defined by the semiconductor substrate, the floor of the deep trench being deeper than the floor of the intermediate trench, wherein the deep and shallow trenches are parallel to each other; and at least one transistor device formed over the substrate logic portion, the transistor device including a gate dielectric layer and a gate material, wherein the gate dielectric layer is elevated with respect to the first and second source/drain regions.