Patent ID: 8837244
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. A memory output circuit, capable of receiving bit line data and bit bar line data output by a memory cell array, comprising: a pre-charge circuit, capable of pre-charging a first node and a first inverse node, wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node; a pre-amplifier circuit, capable of respectively generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node; and a sense amplifier, capable of receiving a sense enable signal, and detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node according to the sense enable signal, wherein the pre-amplifier circuit comprises: