Patent ID: 8331151
Filing Date: 2012-12-11
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a memory region including memory cells configured to store data; a redundant region including memory cells configured to store data; and a control unit which is responsive to an erase command to execute, prior to an erase operation corresponding to the erase command, an error detection operation on data read from the memory region to detect whether the memory region is a defective memory region to be replaced by the redundant region, wherein the control unit comprises: an error correction circuit for performing an error detection/correction operation on the data read from the memory region; an error correction region coordinate memory unit for storing coordinates of the memory region when a number of detected error bits exceeds a number of error-correctable bits in the error detection/correction operation, whereby the memory region is a defective memory region; and a control circuit for selecting the redundant region, instead of the memory region, indicated by the coordinates stored in the error correction region coordinate memory unit in response to the input of a read/write operation command.