Patent ID: 6931495
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. A processor system, comprising: a processor adapted to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit dirty information storing part adapted to store non-write-back information in units of address range smaller than that of said cache line, said information indicating that the write-back to said external memory is not yet performed; a mode information storing part adapted to store specific mode flag information which is set or reset in order to determine whether to be in a mode for not performing unnecessary write-back operation; and a write-back determining part adapted to decide whether to write back a certain cache line before performing a DMA transfer based on said non-write-back information, when said specific mode flag is set and the write-back of the cache line is instructed, and adapted to perform the DMA transfer after writing back said cache line when said specific mode flag is not set.