Patent ID: 7746685
Filing Date: 2010-06-29
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising SRAM cells arranged in matrix, each SRAM cell including; a first inverter containing a first PMOS transistor and a first NMOS transistor, a second inverter containing a second PMOS transistor and a second NMOS transistor, said first and second inverters having respective inputs and outputs cross-connected, a first transfer transistor connected between a first bit line and the output terminal of said first inverter, and a second transfer transistor connected between a second bit line and the output terminal of said second inverter, said first and second transfer transistors having respective gates connected to a word line, said second bit line used in single-ended reading of data therefrom, wherein said first NMOS transistor and said first transfer transistor are formed in a first well with respective identical gate lengths and gate widths, wherein said second NMOS transistor and said second transfer transistor are formed in a second well with respective identical gate lengths and gate widths, said gate widths made wider than said gate widths of said first NMOS transistor and said first transfer transistor.