Patent ID: 6498059
Filing Date: 2002-12-24
Classification: G02F,H01L

Abstract:
A method for fabricating a thin film transistor (TFT), comprising steps of:(a) providing an insulation substrate; (b) forming a conductive layer on said insulation substrate; (c) defining said conductive layer as a gate conducting structure by a first photolithography and etch process; (d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching said data line layer, said source/drain layer and said junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, wherein said junction layer has relative good selective etching ratios to said data line layer and said source/drain layer respectively; and (e) heat-treating said junction layer to reduce resistance between said source/drain structure and said channel layer.