Patent ID: 8947275
Filing Date: 2015-02-03
Classification: H03M

Abstract:
1. A digital background calibration apparatus using capacitor division and swapping in order to reduce a capacitor mismatch effect of an Analog to Digital Converter (ADC), the apparatus comprising: a Digital to Analog Converter (DAC) configured to select any one of an input signal, a ground voltage, and a reference voltage in response to a first control signal and a second control signal, convert the selected signal or voltage into an analog signal, and output a first conversion signal and a second conversion signal as the converted analog signal; a comparator configured to convert the first conversion signal and the second conversion signal into digital signals, output a first digital signal and a second digital signal as the converted digital signals, and output a third digital signal as a comparison value of the first conversion signal and the second conversion signal; a Successive Approximation Register (SAR) configured to output a first register signal and a second register signal using the first digital signal and the second digital signal and output the first control signal using the third digital signal; a calibration unit configured to output a digital code calibration signal by calibrating a mismatch value of the first register signal in response to an external control signal; and a bit controller configured to output the second control signal using the second register signal in response to the external control signal, wherein the digital code calibration signal is fed back to one side of the calibration unit, and the input signal comprises a first input signal and a second input signal.