Patent ID: 6965533
Filing Date: 2005-11-15
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array including a word line, a plurality of data lines across the word line, and a plurality of memory cells provided at intersections of the word line and the plurality of data lines, the plurality of data lines being divided into a plurality of data line groups; a data encoder comparing write data with data stored in selected memory cells and encoding the write data according to the comparing result; a plurality of column selector groups each including a plurality of column selectors, each of the plurality of column selectors being coupled to corresponding one of the plurality of data lines; wherein when the word line is selected, each of the plurality of column selector groups selects at least one data line in corresponding to the data line group, and wherein the plurality of data lines in each of the plurality of data line groups are arranged in a row.