Patent ID: 6316961
Filing Date: 2001-11-13
Classification: H03K

Abstract:
A logic gate circuit, comprising:a first load provided between one electric potential and a first node, wherein said first load charges said first node in response to a control signal;a second load provided between said one electric potential and a second node, wherein said second load charges said second node in response to said control signal;a logic circuit provided between said first node and a third node, wherein said logic circuit electrically connects said first node and the third node in response to plural input signals;a reference field effect transistor including a source-drain path formed between said second node and said third node, and a gate which is connected to said first node;a drive circuit provided between said third node and another electric potential, wherein said drive circuit drives said logic circuit and said reference field effect transistor in response to said control signal;a first feed-back field effect transistor including a source-drain path formed between said first node and said logic circuit, and a gate which is connected to said second node; anda second feed-back field effect transistor including a source-drain path formed between said second node and said reference field effect transistor, and a gate which is connected to said first node.