Patent ID: 6825124
Filing Date: 2004-11-30
Classification: H01L,Y10S

Abstract:
A method of forming a metal line in a semiconductor device, comprising the steps of:forming an interlay insulating film on a semiconductor substrate in which a lower line is formed; patterning the interlay insulating film to form an aperture unit for forming an upper line connected to the lower line; cooling the semiconductor substrate in which the aperture unit is formed at a given temperature; implementing a cleaning process using a hydrogen reduction reaction in order to remove polymer formed on a sidewall of the aperture unit and a metal oxide film formed on the lower line, wherein the cleaning process is implemented at a temperature of about 25Â° C.-50Â° C. to minimize degradation of the interlay insulating film; implementing an annealing process in-situ within a chamber in which the cleaning process is implemented, wherein the annealing process is implemented in two steps, the first step implemented to mitigate stress and detach OH radicals or H2O residue absorbed on the sidewall of the aperture unit, and the second step implemented at a temperature higher than that of the first step to accomplish densification of the interlay insulating film and the lower line; and burying the aperture unit with a conductive material to form an upper line.