Patent ID: 7352215
Filing Date: 2008-04-01
Classification: H03K,H03M

Abstract:
1. A latch circuit, comprising: a bistable pair of transistors with both transistors connected directly between a reset switch and a node, and having a first port for receiving a first current signal and producing a first output voltage, and a second port for receiving a second current signal and producing a second output voltage; and a vertical latch including a first transistor and a second transistor, each of said first transistor and said second transistor having a control terminal, a first non-control terminal, and a second non-control terminal, said control terminal of said first transistor connected directly to said first non-control terminal of said second transistor at said first port, said control terminal of said second transistor connected directly to said first non-control terminal of said first transistor, and said second non-control terminal of said first transistor connected directly to said node, wherein said first transistor is a first type, said second transistor is a second type, and said first type is different from said second type.