Patent ID: 6178110
Filing Date: 2001-01-23
Classification: H01L,Y10S

Abstract:
A static memory cell formed in a semiconductor substrate, comprising:first and second nodes;a first drive MOS transistor having a drain connected to said first node and a gate connected to said second node;a second drive MOS transistor having a drain connected to said second node and a gate connected to said first node;a first transfer MOS transistor having a source connected to said first node;a second transfer MOS transistor having a source connected to said second node;a first load element connected to said first node; anda second load element connected to said second node,the drain of said first drive MOS transistor and the source of said first transfer MOS transistor being formed by a first impurity region in said semiconductor substrate,the drain of said second drive MOS transistor and the source of said second transfer MOS transistor being formed by a second impurity region in said semiconductor substrate,said static memory cell further comprising:a first metal silicide layer formed on said first impurity region and the gate of said second drive MOS transistor; anda second metal silicide layer formed on said second impurity region and the gate of said first drive MOS transistor,said first and second load elements being formed on said first and second metal silicide layers, respectively.