Patent ID: 6651235
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A method for an automated placement and routing (P&R) tool for designing a layout on a constrained area of a semiconductor substrate of an integrated circuit (IC) described by a first netlist as interconnected cells organized into a hierarchy of circuit modules, wherein the cells form signal paths subject to signal path delay constraints, wherein the P&R tool includes a cell library containing a description of each cell of the IC, and wherein the first netlist identifies each cell by reference to its description in the cell library, the method comprising the steps of:a. modifying the first netlist to produce a second netlist also describing the IC as being interconnected cells organized into a hierarchy of circuit modules, wherein while the first netlist describes a portion of the IC as being implemented by a group of cells, the second netlist describes the same portion of the IC as being implemented by a single cell; b. producing a trial layout of the IC as described by the second netlist in accordance with cell descriptions included in the cell library in a manner that is biased toward positioning most closely interconnected cells nearest one to another in the semiconductor substrate; and c. producing estimates of areas of semiconductor substrate needed to separately contain circuit modules of the IC described by the second netlist based on positions within the trial layout of cells forming those circuit modules.