Patent ID: 6245614
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of manufacturing a self-aligned split-gate flash memory cell on a semiconductor wafer, the semiconductor wafer comprising a substrate, at least two select gates formed on the substrate, and a dielectric layer formed on each of the select gates, the method comprising:forming a polysilicon spacer on each of the inner walls between the two select gates;forming a drain in the substrate adjacent to each of the outer walls of the two select gates;forming a source in the substrate between the two polysilicon spacers;forming a silicon oxide layer on the surface of the semiconductor wafer to cover the dielectric layers, select gates and polysilicon spacers;performing a dry etching process to remove a predetermined thickness of the silicon oxide layer and to remove the dielectric layer above each of the select gates down to a predetermined thickness;forming an insulating layer over each of the polysilicon spacers; andforming a control gate above the two polysilicon spacers;wherein each of the two polysilicon spacers acts as a floating gate of the spilt-gate flash memory cell and is used to enhance the coupling ratio of the spilt-gate flash memory cell.