Patent ID: 8171260
Filing Date: 2012-05-01
Classification: G06F

Abstract:
1. An apparatus, comprising: a memory storing a fetch-block branch target buffer coupled to at least one pipeline and operable to provide control signals to the at least one pipeline in response to a fetch address corresponding to the block entry, the fetch-block branch target buffer comprising a length multiplexer operable to select, according to the value representing the branch prediction, one of the length value associated with the first fetch-block and a maximum length, wherein the least one pipeline is operable to fetch from the memory using the fetch address a number of instructions corresponding to the selected length, wherein the fetch-block branch target buffer comprises a branch prediction cache operable to store a plurality of block entries associated with a plurality of different fetch-blocks, and wherein the branch prediction cache comprises one of: a four-way set associate content addressable memory, direct mapped content addressable memory, fully associative content addressable memory, a memory array, a heap, a tree, a trie, a linked list, and a hash table.