Patent ID: 6373766
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) for storing a plurality voltage levels in each of a plurality of memory cells, the memory having a plurality of complementary bit lines each having memory cell capacitors coupled thereto through memory access transistors for reading data from the memory cells, the bit lines being divided into sub-bit lines by switches, the memory comprising:a) a first group of sense amplifiers associated with the plurality of bit lines for sensing sign data from selected ones of the plurality of memory cells; and b) a second group of sense amplifiers associated with the plurality of bit lines for sensing magnitude data from selected ones of the plurality of memory cells in response to sign data feedback signals from the first group of sense amplifiers, the second group of sense amplifiers including a plurality of skewed inverters for switching at multiple voltage levels in response to the magnitude data and the feedback sign data.