Patent ID: 9166041
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a first active region and a second active region formed of a semiconductor layer formed on the semiconductor substrate via an insulating layer, the first active region and the second active region each being surrounded when seen in a plan view by a device isolation region penetrating through the semiconductor layer and the insulating layer; a first MISFET formed in the first active region; a second MISFET formed in the second active region; a first region and a second region each surrounded when seen in a plan view by the device isolation region and having the semiconductor layer and the insulating layer removed therefrom; a first semiconductor region of a first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view; a second semiconductor region of the first conductivity type formed in the semiconductor substrate so as to include the first active region and the first region when seen in a plan view and having impurity concentration higher than that of the first semiconductor region; a third semiconductor region of a second conductivity type that is different from the first conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view; and a fourth semiconductor region of the second conductivity type formed in the semiconductor substrate so as to include the second active region and the second region when seen in a plan view and having impurity concentration higher than that of the third semiconductor region, wherein the second semiconductor region is contained in the first semiconductor region, the second semiconductor region has a bottom surface at a shallower level than a bottom surface of the first semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the first active region and the first region when seen in a plan view, the second semiconductor region extends to also under the portion of the device isolation region interposed between the first active region and the first region when seen in a plan view, the fourth semiconductor region is contained in the third semiconductor region, the fourth semiconductor region has a bottom surface at a shallower level than a bottom surface of the third semiconductor region and at a deeper level than a bottom surface of a portion of the device isolation region interposed between the second active region and the second region when seen in a plan view, and the fourth semiconductor region extends to also under the portion of the device isolation region interposed between the second active region and the second region when seen in a plan view.