Patent ID: 8427889
Filing Date: 2013-04-23
Classification: G11C

Abstract:
1. A main word line driving circuit for driving word lines in a memory device, comprising: a first level shifting unit configured to convert a decode signal into a first operative signal, wherein the first level shifting unit comprising: a latching unit; a first NMOS transistor having a gate connected to a second bias voltage, a source connected for receiving the decode signal, and a drain connected to the latching unit; and a second NMOS transistor having a gate connected for receiving the decode signal, a source connected to a third bias voltage, and a drain connected to the latching unit; a second level shifting unit configured to convert the decode signal into a second operative signal; and an inverting unit configured to receive the first and second operative signals for driving the word lines; wherein a supply voltage of the first level shifting unit is selectively switched to a first bias voltage when the word lines in the memory device are selected or partially selected and switched to the second bias voltage regardless of a first word line activation signal and a second word line activation signal when the word lines in the memory device are deselected.