Patent ID: 8339828
Filing Date: 2012-12-25
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a source line; a bit line; first signal lines; second signal lines; word lines; memory cells connected in parallel between the source line and the bit line; a potential generating circuit generating and supplying writing potentials and reference potentials; a boosting circuit supplying a potential to the potential generating circuit; a first driver circuit configured to drive the second signal lines and the word lines to select, according to an address signal, a memory cell connected to the bit line; a second driver circuit configured to select a first signal line and output any of the writing potentials to the selected first signal line; and a reading circuit to which a potential of the bit line and the reference potentials are input and configured to determine a data stored in a selected memory cell according to the potential of the bit line and the reference potentials, wherein one of the memory cells includes: wherein the second transistor includes an oxide semiconductor layer, wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other, wherein the source line and the first source electrode are electrically connected to each other, wherein the first drain electrode and the third source electrode are electrically connected to each other, wherein the bit line and the third drain electrode are electrically connected to each other, wherein one of the first signal lines and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein one of the second signal lines and the second gate electrode are electrically connected to each other, and wherein one of the word lines and the third gate electrode are electrically connected to each other.