Patent ID: 6673678
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method of manufacturing a non-volatile semiconductor memory device comprising:at least one memory element including: a semiconductor substrate having a principal surface comprising a first region and a second region; a floating gate formed on the first region; a control gate formed on the floating gate; a first source/drain region formed in the first region; and a second source/drain region formed in the first region apart from the first source/drain region, located by the floating gate and the control gate therebetween; and at least one access gate transistor for selectively activating the memory element, the access gate transistor comprising: a gate electrode formed on the second region; a third source/drain region that is formed in the second region and is electrically connected to the second source/drain region; and a fourth source/drain region formed in the second region apart from the third source/drain region, located by the gate electrode therebetween, wherein the manufacturing method comprising: a step of forming a tunnel insulation layer on the first region; a step of forming on the tunnel insulation layer a first conductive layer which becomes the floating gate; a step of forming a dielectric layer on the first conductive layer; a step of forming a gate insulation layer on the second region; a step of forming a second conductive layer on the dielectric layer and the gate insulation layer; a step of forming the control gate and the gate electrode by selectively etching the second conductive layer; and a step of forming the floating gate by selectively etching the first conductive layer, wherein, when the first conductive layer is selectively etched, the principal surface in the area between the floating gate and the gate electrode is also unavoidably etched to form a groove section, and wherein the manufacturing method further comprising: a step of performing a first ion implantation in the semiconductor substrate in a manner to cover the groove section so that a first impurity region is formed in the semiconductor substrate; and a step of performing a second ion implantation in the semiconductor substrate in a manner to cover the groove section so that a second impurity region and at least one of the first, second, third, and fourth source/drain regions are formed in the semiconductor substrate, the second impurity region overlapping with the first impurity region at the groove section, the second source/drain region and the third source/drain region being electrically connected by the first impurity region and the second impurity region, wherein the first and second ion implantations have the same conductivity type.