Patent ID: 6294315
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method of forming a metal wiring, comprising the steps of:(a) forming a first interlayer dielectric film on a semiconductor substrate;(b) forming an etch stop layer on the first interlayer dielectric film;(c) forming a second interlayer dielectric film on the etch stop layer;(d) forming a photosensitive polymer pattern on the second interlayer dielectric film, the photosensitive polymer pattern having a first hole with a first width, the first hole exposing a surface region of the second interlayer dielectric film;(e) forming a photoresist pattern overlying both the photosensitive polymer pattern and the exposed surface region of the second interlayer dielectric film, the photoresist pattern having a second hole, with a second width smaller than the first width, the second hole exposing a sub-region of the surface region of the second interlayer dielectric film;(f) sequentially dry-etching the exposed sub-region of the second interlayer dielectric film and the etch stop layer underlying the exposed sub-region using the photoresist pattern as an etch mask, thereby forming a third hole, said third hole defining a second interlayer dielectric film pattern and an etch stop layer pattern and exposing a sub-region of the first interlayer dielectric layer underlying the second hole;(g) removing the photoresist pattern; and(h) dry-etching the first interlayer dielectric film using the etch stop layer pattern as an etch mask, and the second interlayer dielectric film using the photosensitive polymer pattern as an etch mask, thereby forming a wiring region in the second interlayer dielectric layer and a via hole region in the first interlayer dielectric layer.