Patent ID: 9099491
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A method for fabricating a heterojunction field-effect transistor, said method comprising: implanting p-type dopants in order to form an implanted area in a first layer of a III-V semiconductor alloy, removing an upper part of said first layer and of said implanted area by maintaining vapor phase epitaxy conditions, stopping said removing when a density of said p-type dopants at an uppermost face of said implanted area is maximal, forming a second layer of a III-V semiconductor alloy by vapor phase epitaxy on said implanted area and on said first layer, forming a third layer of a III-V semiconductor alloy by vapor phase epitaxy in order to form an electron gas layer at an interface between said third layer and said second layer, and forming a control gate on said third layer plumb with said implanted area.