Patent ID: 7966594
Filing Date: 2011-06-21
Classification: G06F

Abstract:
1. An integrated circuit design system configured to insert dummy surfaces into various layers of a physical design of a multilayer integrated circuit organized in interconnected units containing interconnected blocks composed of interconnected cells through execution of macros in computer-aided design software tools comprising display means and means for command entry by a user, comprising: storage means for storing information related to the physical design of the multilayer integrated circuit; calculating means for determining a design of the interconnected blocks and/or integrated circuits, area verification means for recognizing exclusion areas; and processing means for performing selective insertion of the dummy surfaces based on an insertion hierarchy that reflects a hierarchy of the physical design of the integrated circuit using an individual implementation of the interconnected blocks and a first interconnection routing for said interconnected blocks, and using an individual implementation of the interconnected units and a second interconnection routing for said interconnected units, wherein the patterns of the dummy surfaces are established selectively in accordance with the design of the blocks of the multilayer integrated circuit and based on at least one or more designs of standards cells and custom cells.