Patent ID: 6163186
Filing Date: 2000-12-19
Classification: G06F,H03K,H03L,Y10S

Abstract:
A system comprising:a first switch which controls feed of a first power supply voltage;a second switch which controls feed of a second power supply voltage;a PLL circuit which includes a first circuit that is operated by said first power supply voltage, and a second circuit that is operated by said second power supply voltage;a wiring line which feeds said first circuit with a feedback clock signal outputted from said second circuit;said first circuit which includes a phase comparator circuit which detects a phase difference between a reference clock signal and said feedback clock signal, a control circuit which produces a control voltage conforming to an output of said phase comparator circuit, and a voltage-controlled oscillator circuit which generates a clock signal of a frequency conforming to the control voltage;said second circuit including a circuit which receives an output of the voltage-controlled oscillator circuit and provides said feedback clock signal; anda setting circuit which detects a state of operating state of said PLL circuit whose frequency is higher than a predetermined frequency for said PLL circuit due to said feedback clock signal being electrically disconnected, and which brings said PLL circuit into a predetermined state in accordance with a result of the detection;wherein the feedback clock signal becomes electrically disconnected in one of the following three cases including:a first case in which the second switch does not supply the second voltage to the second circuit;a second case in which the second circuit does not provide the feedback clock signal even though the second switch supplies the second voltage to the second circuit; anda third case in which before the feedback clock signal is properly supplied to the phase comparator, the phase comparator outputs a result of a comparison.