Patent ID: 6246605
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A unit memory cell of a static RAM comprising:a flip-flop circuit including first and second inverters, said first inverter including a first driver transistor and a first load element and said second inverter including a second driver transistor and a second load element, first and second word transistors connected respectively to said first and second inverters, wherein a channel pattern for said first driver transistor of said first inverter and a channel pattern for said second driver transistor of said second inverter are symmetrical about a point, a channel pattern for said first word transistor and a channel pattern for said second word transistor are symmetrical about the point;a channel pattern for said first load element of said first inverter and a channel pattern for said second load element of said second inverter are asymmetrical; anda gate pattern for said first load element is different from a gate pattern for said second load element.