Patent ID: 6649981
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A semiconductor device, comprising:a first base layer having a first conductivity type, said first base layer having first and second surfaces and further having a high resistance; a second base layer, provided in said first surface, having a second conductivity type; an emitter layer, provided in said second base layer, having said first conductivity type; a gate electrode provided through a gate insulating film over said second base layer disposed between said emitter layer and said first base layer; a buffer layer, formed in said second surface, having said first conductivity type and further having a high impurity concentration; a first activation rate, defined by an activated first conductivity type impurity density [cmâˆ’2] in said buffer layer due to SR analysis/a first conductivity type impurity density [cmâˆ’2] in said buffer layer due to SIMS analysis, being 25% or more; a collector layer, provided in said buffer layer, having said second conductivity type; and a second activation rate, defined by an activated second conductivity type impurity density [cmâˆ’2] in said collector layer due to SR analysis/a second conductivity type impurity density [cmâˆ’2] in said collector layer due to SIMS analysis, being more than 0% and 10% or less.