Patent ID: 6555425
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A method of manufacturing a transistor, comprising the steps of:providing a substrate, wherein the substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate; forming a conformal dielectric layer over the polysilicon layer, the offset spacer and the source/drain; forming a spacer on the sidewall of a portion of the conformal dielectric layer over the offset spacer; removing a portion of the conformal dielectric layer to expose the polysilicon layer and the source/drain; and performing a selective epitaxial growth process to form an epitaxial layer on the polysilicon layer and the source/drain, wherein a portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.