Patent ID: 7451070
Filing Date: 2008-11-11
Classification: G06F

Abstract:
1. A method for running samples in a hardware assisted simulator including a bus functional model, comprising the steps of: counting on a software readable register a number of samples provided to said hardware assisted simulator in execution of a transaction on said bus functional model; storing for said bus functional model variables including a sample count retrieved from said bus functional model and a last actual sampling value given said hardware assisted simulator; applying a binary convergence algorithm to generate new sampling values based on said last sampling value given to said hardware assisted simulator and said last actual sampling value used by a given bus functional model for a transaction; maintaining a DOIT flag as a single bit hardware register set to start a current transaction and reset to signal completion of said current transaction; maintaining a counter for accumulating said actual sampling values; responsive to receiving a new transaction from a test program for execution, fetching a value F from said counter as said last actual sampling value; executing said binary convergence algorithm on said value F to calculate a value Snew as said new sampling value; initializing for said current transaction a command register specifying a transaction for execution; resetting said counter, setting said DOIT flag, sampling said simulator Snew times, for each said sampling incrementing said counter and registering results, then disabling said counter, resetting said DOIT flag; and responsive to said DOIT flag being reset, fetching said results to said test program.