Patent ID: 8122177
Filing Date: 2012-02-21
Classification: G06F

Abstract:
1. An integrated circuit (“IC”), comprising: a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port; a PCIe switch; and a PCIe endpoint device coupled to the PCIe root complex through the PCIe switch, the PCIe endpoint device configured to initiate data transfer between the main memory and the PCIe endpoint device; wherein the PCIe endpoint device includes a slave interface configured to enable the CPU to monitor data transfer between the PCIe endpoint device and main memory and a master interface including a READ direct memory access (“DMA”) engine and a TRANSMIT DMA engine, and wherein the READ DMA engine comprises a RECEIVE descriptor ring and the TRANSMIT DMA engine comprises a TRANSMIT descriptor ring.