Patent ID: 6330627
Filing Date: 2001-12-11
Classification: G06F

Abstract:
A fast data transfer system comprising:a plurality of memory modules;a controller located adjacent to the memory modules in a direction where the memory modules are arranged and communicating data with each of the memory modules;a clock generator for generating at least one clock;at least one clock line having a go line portion and a return line portion, which extend in opposite direction along the arrangement of the memory modules and the controller, at least one clock generated by the clock generator being inputted to at least one clock line at an end of its go line portion and transferred over at least one clock line, and at least one clock transferred over the go and return line portions of at least one clock line being inputted to each of the memory modules and the controller, data input/output operations of each of the memory modules and the controller being performed in synchronism with at least one clock; andcontrol circuits provided in each of the memory modules and the controller and including a timing signal generating circuit responsive to a go clock transferred over the go line portion of at least one clock line and a return clock transferred over the return line portion of at least one clock line for generating an intermediate timing signal having a timing which positioned in the middle of a phase displacement that occurs between the go clock and the return clock within two periods of at least one clock.