Patent ID: 7609082
Filing Date: 2009-10-27
Classification: G01R

Abstract:
1. A process for testing signal path resistance in a bussed signal path of an interconnect structure, wherein said interconnect structure comprises a bussed first signal path wherein said bussed first signal path provides electrical connections between a first tester connection point and a first plurality of probes disposed on said interconnect structure and said interconnect structure comprises a plurality of second signal paths wherein each second signal path provides an electrical connection between a different one of a plurality of second tester connection points and a different one of a plurality of second probes, said process comprising: connecting the interconnect structure to a tester so that said bussed signal path is connected to a first tester input/output port and ones of the plurality of second signal paths are connected to corresponding ones of said second tester input/output ports; providing a reference wafer comprising a plurality of separate networks, each network providing electrical interconnections between ones of a plurality of test points on said reference wafer; bringing the plurality of probes of the interconnect structure into contact with said reference wafer so that one of said first probes is connected through one of said test points to one of said plurality of separate networks and so ones of said second probes are connected through ones of said test points to said one of said plurality of separate networks; measuring a resistance of a portion of said bussed signal path connected to said one of said plurality of separate networks.