Patent ID: 6144598
Filing Date: 2000-11-07
Classification: G11C

Abstract:
In a RAMBUS dynamic random access memory (""RDRAM"") having a multiplexed data/address bus and a plurality of input terminals adapted to receive respective control signals including a row sense control signal, the RDRAM including a row address latch circuit that latches a row address applied on at least part of the data/address bus responsive to a first transition of the row sense control signal, and a row sense control circuit that causes a row of memory cells corresponding to the latched row address to be sensed responsive to the first transition of the row sense control signal, a method of conducting a core noise test in the RDRAM, comprising:prior to conducting the core noise test, decoupling the row address latch circuit from the row sense control input terminal;prior to conducting the core noise test, coupling the row address latch circuit to a first control input terminal other than the control terminal to which the row sense control signal is applied;prior to the core noise test, applying a row address to the row address latch circuit on at least part of the data/address bus of the RDRAM, the row address corresponding to row of memory cells that is to be sensed during the core noise test;coupling a first control signal to the first control input terminal while the row address corresponding to the row that is to be sensed during the core noise test is present on the data/address bus, the first control signal causing the row address to be latched in the row address latch;during the core noise test, precharging a bank of memory cells in the RDRAM;during the core noise test, accessing a memory cell in a column of a row of memory cells that has been sensed prior to the core noise test, the memory cell that is accessed being designated by a column address applied on at least part of the data/address bus of the RDRAM; andduring the core noise test, applying the first transition of the row sense control signal to a control input terminal of the RDRAM, the first transition of the row sense control signal causing the row sense control circuit to sense the row of memory cells corresponding to the latched row address.