Patent ID: 6284607
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide, the method comprising:defining, on a common semiconductor substrate, respective active areas for low-voltage transistors and high-voltage transistors, separated by isolation regions;depositing a layer of gate oxide onto said active areas;depositing a layer of polysilicon over the gate oxide layer;first masking and then etching away the polysilicon layer to define respective gate regions of said low-voltage and high-voltage transistors;conformably depositing a dielectric layer on the respective gate regions and on portions of the gate oxide layer positioned laterally of the respective gate regions;using a differential spacer mask to partially shield the dielectric layer in areas over junctions of the high voltage transistors, the differential spacer mask having gaps over the low voltage transistors and over the gate regions of the high voltage transistors; andetching the dielectric layer through the gaps in the differential spacer mask, thereby removing portions of the dielectric layer over the gate regions of the low voltage transistors and the high voltage transistors.