Patent ID: 6130552
Filing Date: 2000-10-10
Classification: G06F,H03K,H03L

Abstract:
A programmable logic device comprising:an array comprising logic blocks configurable to perform logical functions, wherein each logic block comprises a plurality of inputs and outputs;an interconnect structure comprising a plurality of first conductors in a first direction and a plurality of second conductors in a second direction, wherein the first conductors are between rows of the array and the second conductors are between columns of the array, and the interconnect structure is configurable to couple signals from one logic block in the array to another logic block in the array;a reference clock signal;a clock synchronization circuit receiving the reference clock signal and a feedback clock signal, and generating a synchronized clock output signal, wherein the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block; anda multiplexer comprising a first input coupled to the reference clock signal and a second input coupled to the synchronized clock output signal, and the reference clock signal or the synchronized clock output signal is selectably coupled to an input of a logic block through the multiplexer.