Patent ID: 6240002
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A content addressable memory protection circuit, comprising:a memory cell having a read terminal for reading contents of the memory cell;a pass transistor coupled to the read terminal; anda latch having a first inverter with an input terminal and an output terminal coupled to the read terminal by the pass transistor and a second inverter with input and output terminals respectively coupled to the output and input terminals of the first inverter, the first inverter including a pull-down transistor coupled between the output terminal of the first inverter and a first voltage reference and having a control terminal coupled to the input terminal of the latch, and a pull-up transistor coupled between the output terminal of the first inverter and a second voltage reference and having a control terminal coupled to the input terminal of the latch, wherein the first inverter further includes a bias transistor coupled with the pull-up transistor between the output terminal and the second voltage reference.