Patent ID: 8509255
Filing Date: 2013-08-13
Classification: G06F

Abstract:
1. A method of hardware packet pacing using a direct memory access controller in a multi-node parallel computer, comprising: establishing in a first node a token counter on a direct memory access controller initially set to a first predetermined value; establishing in the first node maximum pacing submessage size, the maximum pacing submessage size being a value less than or equal to the first predetermined value; establishing in the first node a remaining bytes count, the remaining bytes count initially set to a message length field value in an original remote get packet; setting in the first node a submessage size to the maximum pacing submessage size or the remaining bytes count, whichever is less; waiting in the first node for the token counter to be greater than or equal to the submessage size; injecting a remote get packet of the submessage size to a network of at least one or more other nodes when the token counter is greater than or equal to the submessage size and decrementing the token counter and the remaining bytes count by the submessage size; and repeating the steps of setting, waiting and injecting until the remaining bytes count is zero.