Patent ID: 7447960
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A method of efficiently loading scan and non-scan memory elements in a logic circuit simulator, the method comprising the steps of: clearing a signal distribution network coupled to the scan and non-scan memory elements by clocking zeros and propagating the zeros in the signal distribution network wherein the propagating of the zeros is dependent on the depth of the signal distribution network and wherein the signal distribution network further comprises a control signal input; loading a previously determined set of values into each of the scan memory elements wherein the loading is initiated with a power on reset event and wherein the previously determined set of values are obtained by extracting them from the scan memory elements of the logic circuit simulator; and propagating the values from the scan memory elements to the non-scan memory elements wherein a circuit clock is temporarily suspended and the scan memory elements are toggled from a function path to a scan path and wherein the values are further extracted from the scan memory elements and analyzed and stored on a host device.