Patent ID: 7783862
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A processor that processes Single Instruction Multiple Data (SIMD) instructions, which SIMD processor comprises: an Instruction Fetch Unit (IFU) that loads a SIMD instruction and applies it as input to a SIMD Instruction Decode Unit (SIDU); and wherein the SIMD Instruction Decode Unit (SIDU) decodes the applied SIMD instruction and produces output signals used to control subsequent processing of the instructions including: (a) SIMD operation identification signals which identify the instruction to be executed; (b) SIMD field width identification signals which identify the field width supplied as an operation modifier to the instruction; (c) SIMD source operand identification signals which identify source locations from which operand values for the SIMD instruction are to be taken; (d) SIMD half-operand modifier signals which identify field value modifications, if any that are applied to select one half of the bits of each field of an operand based on respective half-operand modifier codes of the decoded instruction; and (e) SIMD destination operand identification signals which identify the destination location for a value resulting; wherein: the SIMD half-operand modifier signals comprise one or more signals for each operand that cause high half-operand modification or low half-operand modification of each field of the operand; and high half-operand modification of a field of n bits sets the values of the high n/2 bits into the low n/2 bit positions in the field and sets the high n/2 bit positions in the field to 0, and low half-operand modification of a field of n bits sets the high n/2 bit positions of the field to 0.