Patent ID: 6167479
Filing Date: 2000-12-26
Classification: G06F

Abstract:
In a data processing system having a processor coupled to a memory, the processor being capable of executing machine instructions that are included within the predetermined instruction set of the data processing system, the processor including an addressing circuit to cause the processor to execute a predetermined instruction sequence retrieved from the memory, and the processor further including interrupt circuits to execute control sequences whereby execution of the processor is re-directed from the predetermined instruction sequence to execution of an interrupt handling instruction sequence upon the occurrence of predetermined interrupt events, an interrupt test system for testing interrupt sequence execution, comprising:a storage device to store interrupt injection signals, each of said interrupt injection signals being associated with a respective one of the machine instructions;addressing circuits coupled to said storage device to read from said storage device at least one of said interrupt injection signals associated with a respective one of the machine instructions being executed; andinterrupt encode logic coupled to said storage device to receive said at least one of said interrupt injection signals and to cause the interrupt circuits to execute a selected one of the control sequences to re-direct the processor execution from said respective one of the machine instructions being executed to a selected one of the interrupt handling instruction sequences if said at least one of said interrupt injection signals is at a predetermined logic level.