Patent ID: 6653874
Filing Date: 2003-11-25
Classification: H03L

Abstract:
A clock producing circuit receiving first and second reference clocks at first and second input terminals and comprising:a first phase locked loop connected to said first input terminal for receiving said first reference clock to produce a first output clock having first phase according to said first reference clock; a second phase locked loop having a digital filter with filter coefficients and connected to said second input terminal for receiving said second reference clock to produce a second output clock having second phase according to said second reference clock; and a comparing portion connected to said first phase locked loop and said second phase locked loop for comparing said first phase with said second phase to supply a filter coefficient control signal representative of difference between said first phase and said second phase to said digital filter; wherein said digital filter updates said filter coefficients according to said filter coefficient control signal so as to reduce said difference between said first phase and said second phase.