Patent ID: 7633109
Filing Date: 2009-12-15
Classification: H01L

Abstract:
1. A memory device comprising: a substrate; a trench capacitor formed in the substrate, wherein the trench capacitor has a top surface being coplanar with a top surface of the substrate; a buried gate formed in the substrate, wherein the buried gate has a top surface being coplanar with the top surface of the substrate; a drain region formed between the trench capacitor and the buried gate in the substrate; and a conducting strap formed on a portion of the top surface of the substrate to electrically connect the trench capacitor to the drain region; wherein the buried gate comprises: an insulating layer formed in a bottom surface of the buried gate; a gate matter formed on the insulating layer; a conductor formed on the gate matter; an inner spacer formed on the gate matter and between the conductor and the substrate; and a cap layer covered the conductor and the inner spacer.