Patent ID: 7984398
Filing Date: 2011-07-19
Classification: G06F

Abstract:
1. A computer-executed method for designing a circuit with multiple voltage domains, the method comprising: parsing, by using a computer, a description of a circuit design which includes multiple voltage domains to obtain: a parsed design which identifies signals that cross voltage domains, and a voltage domain hierarchy such that a first voltage domain in the voltage domain hierarchy is always off whenever a second voltage domain which is above the first voltage domain in the voltage domain hierarchy is off; performing register transfer logic (RTL) simulation using the parsed design, which includes: assigning a don't care symbol to signals in voltage domains in standby mode, assigning logic value “0” to signals in voltage domains in shutdown mode, and not modifying logic values which did not change from a previous simulation timestep; performing gate level simulation using the parsed design, which includes: using a leakage power value for voltage domains in standby mode, using a zero power value for voltage domains in shutdown mode, and not performing delay calculations in voltage domains that are in standby or shutdown mode; synthesizing the parsed design to obtain a synthesized design, wherein for each signal that crosses voltage domains, synthesizing the parsed design includes: inserting level shifting logic if the signal crosses from a low voltage domain to a high voltage domain, and not inserting level shifting logic if the signal crosses from a high voltage domain to a low voltage domain; performing formal verification on the synthesized design, which includes automatically checking if: a voltage domain indicator signal for a first voltage domain is driven by a second voltage domain that is higher than the first voltage domain in the voltage domain hierarchy, signals associated with scan chains do not cross voltage domains, and buffer trees do not cross voltage domains; and performing placement and routing on the synthesized design to obtain a placed and routed design, wherein performing placement and routing includes: generating a placement constraint for each cell associated with a third voltage domain to ensure that each cell associated with the third voltage domain is placed in an area associated with the third voltage domain, and generating placement and routing constraints for clock trees to ensure that each clock tree is placed and routed within a single voltage domain.