Patent ID: 6385104
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of bit lines and a plurality of word lines installed perpendicular to said plurality of bit lines and a plurality of memory cells disposed at the intersections of the bit lines and the word lines, a row decoder which selects a prescribed word line out of said plurality of word lines in response to a row address when a control signal is in an activated state and brings all the word lines to an unselected state when said control signal goes to an inactivated state, a test mode decision circuit which decides that the device is in a test mode and generates a test signal, and a control signal generating circuit which brings said control signal to the activated state and keeps it there for a prescribed duration in response to an instruction signal, wherein said control signal generating circuit is provided with a means for changing said control signal to the inactivated state in response to the occurrence of the test signal sooner than in a normal operation.