Patent ID: 6916700
Filing Date: 2005-07-12
Classification: H01L

Abstract:
1. A mixed-mode process introducing a hard mask layer, comprising the steps of: providing a semiconductor structure; sequentially forming a first conductive layer, a dielectric layer, and a second conductive layer on the semiconductor structure; forming a first stacked structure in a portion of the second conductive layer and the dielectric layer, and revealing the first conductive layer exposed by the first stacked structure; conformably depositing a mask layer over the first conductive layer and covering the first stacked structure thereon; and patterning the mask layer and the first conductive layer to simultaneously form a capacitor and a second stacked structure on the semiconductor structure, wherein the capacitor comprises the first stacked structure, a patterned mask layer thereon and a patterned first conductive layer therebelow and the second stacked structure comprises a patterned first conductive layer and a patterned mask layer stacked thereabove.