Patent ID: 8576150
Filing Date: 2013-11-05
Classification: G09G

Abstract:
1. A liquid crystal display comprising: a plurality of pixels arranged at intersections where multiple pairs of data lines, each pair consisting of two data lines, intersect with a plurality of row scanning lines, each of the pixels including: wherein each of the positive-polarity signal pixel circuit part and the negative-polarity signal pixel circuit part is formed by a plurality of metal layers laminated on a semiconductor substrate while interposing interlayer films therebetween, the positive-polarity signal pixel circuit part and the negative-polarity signal pixel circuit part include their mutually-paired circuit components and lines arranged line-symmetrically to either or both of a first pixel center line in parallel with a column-wise direction of the pixels on the metal lavers and a second pixel center line in parallel with a cross-sectional direction of the metal layers, power lines of the second transistor and power lines of the fourth transistor on predetermined one of the metal layers are formed in parallel with the first pixel center line, in an outer circumferential position of the pixels, and the first and second switching transistors are switched in a predetermined period shorter than a vertical scanning period to apply the voltage of the positive-polarity video signal and the voltage of the negative-polarity video signal retained in the first and second retentive capacities to the pixel electrode alternately, thereby driving the liquid crystal element in alternating current, wherein each of the metal layers includes a first through-hole and contact formed on the first pixel center line and the second pixel center to connect the pixel electrode with respective output terminals of the first and second switching transistors, the first and second retentive capacities are formed by first and second metal layers of the plurality of metal layers, the first metal layer being adjacent to the second metal layer, and one interlayer film between the first metal layer and the second metal layer, the positive-polarity signal pixel circuit part includes a second through-hole and contact formed in predetermined two or more metal layers to connect the first retentive capacity with the first and second transistors on the semiconductor substrate, respectively, the negative-polarity signal pixel circuit part includes a third through-hole and contact formed in the predetermined two or more metal layers to connect the second retentive capacity with the third and fourth transistors on the semiconductor substrate, respectively, the second through-hole and contact and the third through-hole and contact are arranged symmetrically to each other with respect to the first pixel center line and also arranged at the substantial center of the pixel so as to adjoin the first through-hole and contact, and an opening is formed at a central portion of the pixel excepting at least pixel portions forming the first through-hole and contact, the second through-hole and contact and the third through-hole and contact on either the first metal layer or the second metal laver, which is closer to the semiconductor substrate.