Patent ID: 7325232
Filing Date: 2008-01-29
Classification: G06F

Abstract:
1. A method of compiling a high level language to map a plurality of tasks and a plurality of data onto a very long instruction word configurable multiple processor, distributed memory hardware architecture, the method comprising: a) describing a task-level network of behaviors that defines an embedded system in the very long instruction word configurable multiple processor, distributed memory hardware architecture, each of the task-level network of behaviors being related to each other through control and data flow; b) predicting a schedule of tasks for the task-level network of behaviors; c) allocating the plurality of tasks to at least two processors and allocating the plurality of data to at least two distributed memories in the very long instruction word configurable multiple processor, distributed memory hardware architecture in response to the predicted schedule of tasks; and d) generating machine executable code with the allocated plurality of tasks and allocated plurality of data for the very long instruction word configurable multiple processor, distributed memory hardware architecture that enables parallel execution of very long instruction word operations.