Patent ID: 6344687
Filing Date: 2002-02-05
Classification: H01L

Abstract:
A dual-chip package, comprising:a die pad; a plurality of first metal studs located around the die pad; a plurality of second metal studs around the first metal studs; a plurality of conductive traces electrically connecting the first metal studs and the second metal studs; a first chip attached to a top surface of the die pad and electrically connected to respective top ends of the first metal studs; a second chip attached to a bottom surface of the die pad and electrically connected to respective bottom ends of the first metal studs; and an insulating material sealing the first chip, the second chip, the connection between the first chip and the first metal studs, the connection between the second chip and the first metal studs, and the conductive traces, wherein the first studs are entirely enclosed, leaving only one end of each second stud exposed for external connection.