Patent ID: 8194453
Filing Date: 2012-06-05
Classification: H01L

Abstract:
1. A three dimensional stacked nonvolatile semiconductor memory comprising: a semiconductor substrate; a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side; and a driver disposed between the first and second blocks, wherein each of the first and second blocks is comprised of at least two conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least two conductive layers by being insulated therefrom, and a columnar semiconductor having a lower end connected to the semiconductor substrate and an upper end connected to the bit line and passing through the at least two conductive layers, wherein each of the at least two conductive layers is comprised of one of a select gate line and a word line, wherein a select gate transistor is comprised of the select gate line and the columnar semiconductor, and a memory cell is comprised of the word line and the columnar semiconductor, and wherein at least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and the select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver.