Patent ID: 7624251
Filing Date: 2009-11-24
Classification: G06F

Abstract:
1. A method for executing a load-partial instruction, comprising: receiving the load-partial instruction to be executed, wherein the load-partial instruction specifies a source address in memory, which is arbitrarily aligned; and executing the load-partial instruction, which involves loading a partial-vector-sized datum from a naturally-aligned memory region encompassing the source address into a register, and in doing so, if the source address is unaligned, rotating the bytes of the partial-vector-sized datum by swapping a set of bytes residing at addresses lower than the source address with a set of bytes residing at addresses greater than or equal to the source address, wherein rotating the bytes of the vector involves rotating the bytes N positions, wherein N is equivalent to either the source address specified by the instruction modulo the vector length in bytes or the source address specified by the instruction modulo the vector length in bytes subtracted from the vector length in bytes, wherein rotating the bytes of the partial-vector-sized datum occurs before the partial-vector-sized datum reaches the register, and wherein rotating the bytes of the partial-vector-sized datum involves using alignment circuitry which is located along a load-store path between the memory and the register to cause the byte at the specified source address to reside at the least-significant byte position within the partial-vector-sized datum for a little-endian memory transaction, or to cause the byte to be positioned at the most-significant byte position within the partial-vector-sized datum for a big-endian memory transaction.