Patent ID: 8731136
Filing Date: 2014-05-20
Classification: G09G,G11C

Abstract:
1. A gate shift register comprising a plurality of stages configured to receive a plurality of gate shift clocks and sequentially output a scan pulse, wherein a kth stage of the plurality of stages includes: a scan direction controller including first and second forward thin film transistors (TFTs) and first and second reverse TFTs, the scan direction controller serving to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals; a node controller including first to eighteenth TFTs, the node controller serving to control charging and discharge operations of each of a Q an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs, the output unit serving to output a first scan pulse and a second scan pulse based on voltage levels of the Q wherein: each of the plurality of gate shift clocks has a pulse width of three horizontal periods and is generated as a 6-phase cyclic clock, wherein a phase of the 6-phase cyclic clock is shifted on a per horizontal period basis; and adjacent gate shift clocks of the plurality of gate shift clocks overlap each other during two horizontal periods, wherein: the first scan pulse functions as a first carry signal; the second scan pulse functions as a second carry signal; and the first input terminal is connected to a second output node of a k−2th stage, the second input terminal is connected to a first output node of a k−1th stage, the third input terminal is connected to a second output node of a k+1th stage, and the fourth input terminal is connected to a first output node of a k+2th stage; the first TFT discharges the Q the second TFT discharges the Q the third TFT applies a forward driving voltage to the QB the fourth TFT applies a reverse driving voltage to the QB the fifth TFT applies odd AC driving voltage to a first node as a gate electrode and a source electrode of the fifth TFT are connected to an odd alternating current (AC) driving voltage supply line; the sixth TFT discharges the first node to the low potential voltage based on the voltage level of the Q the seventh TFT applies the odd AC driving voltage to the QB the eighth TFT discharges the first node to the low potential voltage based on the voltage level of the Q the ninth TFT discharges the QB the tenth TFT discharges the Q the eleventh TFT discharges the Q the twelfth TFT applies the forward driving voltage to the QB the thirteenth TFT applies the reverse driving voltage to the QB the fourteenth TFT applies even AC driving voltage to a second node as a gate electrode and a source electrode of the fourteenth TFT are connected to an even AC driving voltage supply line; the fifteenth TFT discharges the second node to the low potential voltage based on the voltage level of the Q the sixteenth TFT applies the even AC driving voltage to the QB the seventeenth TFT discharges the second node to the low potential voltage based on the voltage level of the Q the eighteenth TFT discharges the QB