Patent ID: 8575952
Filing Date: 2013-11-05
Classification: G01R,H01L

Abstract:
1. A test method comprising: preparing a semiconductor device including a first circuit block, a second circuit block, a first lead-out line coupled to the first circuit block, a second lead-out line coupled to the second circuit block, a first pad coupled to the first lead-out line, a second pad coupled to the second lead-out line, first shielding lines which are provided at both sides of the first lead-out line respectively and are adjacent to the first lead-out line and second shielding lines which are provided at both sides of the second lead-out line respectively and are adjacent to the second lead-out line; applying a test voltage to both the first pad and the second pad to perform a short-circuit test of the semiconductor device; and monitoring for a leakage current flowing through at least one of the first shield lines and the second shield lines.