Patent ID: 7253519
Filing Date: 2007-08-07
Classification: H01L

Abstract:
1. A chip packaging structure, comprising: a chip having a first passivation layer and at least a bonding pad, wherein the bonding pad is exposed by the first passivation layer and the first passivation layer has at least a recess, the whole recess has a sidewall and a bottom surface being exposed; a redistribution layer formed over the first passivation layer, wherein the redistribution layer electrically connects with the bonding pad and extends from the bonding pad to the recess, and in contact with the sidewall and the bottom surface of the recess and the redistribution layer further comprises: a second passivation layer formed over the first passivation layer and the redistribution layer, wherein the second passivation layer has an opening that exposes the redistribution layer above the recess; and at least a bump disposed inside the opening and electrically connected to the redistribution layer above the recess.