Patent ID: 6911850
Filing Date: 2005-06-28
Classification: H03L

Abstract:
1. A semiconductor integrated circuit comprising: a delay circuit including a plurality of delay elements series-connected to each other, each having a delay time which is controlled in accordance with a voltage; a phase comparison circuit for comparing a phase of an m-th clock signal and a phase of an (m+N)th clock signal in said delay circuit to obtain a phase difference, where m is not less than 1 and N is not less than 1; a comparison control signal generating circuit for generating a comparison control signal so as to control said phase comparison circuit to generate a predetermined voltage when said phase difference between the phase of said m-th clock signal and the phase of said (m+N)th clock signal exceeds a predetermined range; and a filter circuit for filtering a voltage generated by said phase comparison circuit and applying said filtered voltage to said plurality of delay elements of said delay circuit.