Patent ID: 6487207
Filing Date: 2002-11-26
Classification: H04L

Abstract:
A data switch comprising;Y input serial access memories each for receiving an input data package of a predetermined length X; a dynamic random access memory array; Y output serial access memories each for storing an output data package of a predetermined length X; data transfer buses for transferring input data packages from the Y input serial access memories to the dynamic random access memory array, the data transfer buses further transferring the input data packages from the dynamic random access memory array to the Y output serial access memories; an input edit buffer for editing the input data package prior to transferring to the dynamic random access memory; an output edit buffer for editing the input data package prior to transferring to the Y output serial access memories; and a controller for configuring the Y input and output serial access memories to store a portion of the full data package of length X, such that an X length data package can be serially input or output from the Y input and output serial access memories in X/Y clock cycles.