Patent ID: 6442065
Filing Date: 2002-08-27
Classification: G11C

Abstract:
A method for operating a memory cell configuration having dynamic gain memory cells, which comprises:providing memory cells each having at least one memory transistor with a gate electrode and first and second drain/source regions; writing a first information item to a memory cell by charging a gate electrode of a memory transistor of the memory cell with a first voltage; writing a second information item to the memory cell by charging the gate electrode of the memory transistor with a second voltage; respectively reading out the first information item and the second information item by applying an operating voltage to a first source/drain region of the memory transistor and applying a read-out voltage to a second source/drain region of the memory transistor; setting the first voltage to lie between the second voltage and the read-out voltage; setting the read-out voltage to lie between: the first voltage minus a threshold voltage of the memory transistor and the second voltage minus the threshold voltage of the memory transistor; and selecting the operating voltage such that the memory transistor is in an off state when the first information item is read out.