Patent ID: 7624322
Filing Date: 2009-11-24
Classification: G01R

Abstract:
1. An integrated circuit comprising: a first circuit portion containing a first plurality of memory elements operating according to a first clock signal received on a first clock path; a second circuit portion containing a second plurality of memory elements operating according to a second clock signal received on a second clock path; an interacting path from an output path of a first memory element in said first circuit to a data input of a second memory element in said second circuit; and an encoder to receive a third clock signal on a third clock path and a fourth clock signal on a fourth clock path, said encoder to also receive one or more signals indicating durations in which said integrated circuit is being tested according to a scan based test approach and a scan enable signal indicating capture cycles during said test, said encoder operating to provide capture pulses on said first clock path and said second clock path, said encoder controlling the timing of provision of said pulses on said first clock path and said second clock path during said capture cycles such that a timing violation is avoided in said second memory element when receiving data from said first memory element.