Patent ID: 7280392
Filing Date: 2007-10-09
Classification: G11C,H01L

Abstract:
1. An integrated memory device, comprising: a plurality of memory cells individually comprising a memory element having a non-reactive resistance whose magnitude is programmable to assume either a first, high-resistance state or a second, low-resistance state, wherein the non-reactive resistance of a memory cell programmed in a high-resistance state is greater than the non-reactive resistance of a memory cell programmed in low-resistance state; a plurality of first and second lines for accessing the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines; and a checking unit configured to determine whether to invert data values to be stored in memory cells coupled to at least a section of respective first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values.