Patent ID: 7159057
Filing Date: 2007-01-02
Classification: G06F

Abstract:
1. An evaluation chip comprising: a plurality of interrupt priority order determining circuits being configured to perform a logical operation on a plurality of control signals used for interrupt priority order modifying control and a plurality of interrupt signals, said plurality of control signals being applied from outside said evaluation chip, each of said plurality of interrupt priority determining circuits being configured to output an interrupt modifying signal; a plurality of interrupt signal generating circuits being configured to perform a logical operation on a plurality of said interrupt modifying signals and a plurality of interrupt request signals being applied from outside said evaluation chip, said plurality of interrupt signal generating circuits being configured to output said interrupt signals; an interrupt vector address generating circuit being configured to encode said plurality of interrupt signals and to generate interrupt vector addresses; and an instruction executing device being configured to decode interrupt instructions having been received in a priority order from outside said evaluation chip and to encode successively decoded results based on said interrupt vector addresses.