Patent ID: 6823421
Filing Date: 2004-11-23
Classification: G06F

Abstract:
A method comprising:programming a first address translation unit in a first input/output (I/O) processor for a minimum amount of memory addresses required to accept control transactions on a first bus; programming a second address translation unit in the first I/O processor to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device; in response to an incoming host request being received from a host, determining whether the host request's reply address overlaps with the memory address range for the second address translation unit; and if the host request's reply address overlaps with the memory address range, dynamically changing a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via the local memory of the first I/O processor.