Patent ID: 6127833
Filing Date: 2000-10-03
Classification: G01R,H01L

Abstract:
A semiconductor device test carrier comprising:a printed circuit board (CB) substrate having a top surface, a bottom surface, and periphery;a rectangular cavity centrally located on said top surface and extending through to said bottom surface;said cavity is concentric within a conductive ground trace patternly provided on the top surface of said PCB substrate;conductive corner power traces are provided adjacent each corner of said ground trace, anda ruled pattern of conductive wire bond fingers encircling said corner power traces are also provided in a linear array on each of four sides encircling said power traces;a first interstitial ball pad array encircling said conductive wire bond pads connects the bottom surface by way of conductive vias and communicates with a second interstitial ball pad array at the bottom surface;a glass plate fitted and bonded to the underside of said PCB substrate forms a transparent bottom supporting surface for said rectangular cavity;a semiconductor device with its backside bonded to said glass substrate within said cavity, bares both front and back sides of said device for EMMI failure analysis.