Patent ID: 9178037
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprising a semiconductor; forming a first sacrificial gate dielectric layer disposed on said substrate in an area for a first MOS transistor having a first polarity; forming a second sacrificial gate dielectric layer disposed on said substrate in an area for a second MOS transistor having a second, opposite, polarity; forming a first sacrificial gate on said first sacrificial gate dielectric layer; forming a second sacrificial gate on said second sacrificial gate dielectric layer; forming a protective dielectric layer over said substrate adjacent to said first sacrificial gate and said second sacrificial gate; forming a first gate block over said second sacrificial gate; removing said first sacrificial gate and said first sacrificial gate dielectric layer to form a first gate cavity in said area for said first MOS transistor; forming a first liner of dielectric material over said protective dielectric layer adjacent to said first gate cavity, said first liner extending into said first gate cavity; forming a second liner of a different dielectric material on said first liner, said second liner extending into said first gate cavity; removing said second liner from a bottom of said first gate cavity, leaving said second liner on vertical surfaces of said first liner in said first gate cavity; removing said first liner from a top surface of said protective dielectric layer and from said bottom of said first gate cavity so as to expose said substrate; removing said second liner in said first gate cavity, leaving said first liner in place in said first gate cavity as a first L-shaped spacer; forming a first permanent gate dielectric layer on said substrate and said first L-shaped spacer in said first gate cavity; forming a first replacement gate on said first permanent gate dielectric layer, said first permanent gate dielectric layer and said first replacement gate overlapping a portion of the said first L-shaped spacer contacting said substrate; and removing said first gate block.