Patent ID: 7132701
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A process for forming a contact for a semiconductor device comprising: forming a first compound semiconductor layer, wherein the first compound semiconductor material layer includes a first compound semiconductor material and has a first conductivity type dopant; forming a second compound semiconductor layer on the first semiconductor layer, wherein the second compound semiconductor layer includes a second compound semiconductor material and has a second conductivity type dopant and the second conductivity type is opposite the first conductivity type; forming a third compound semiconductor layer on the second compound semiconductor layer, said third compound semiconductor layer of said first conductivity type dopant, wherein the first, second and third layers are active layers in a transistor device; patterning the third compound semiconductor layer to define an opening therein with a wall, said opening exposing a portion of the second active layer; and forming a fourth compound semiconductor material upon at least a portion of the exposed second active compound semiconductor layer wherein the fourth compound semiconductor material has the second conductivity type dopant and has a dopant concentration that is higher than the dopant concentration of the second compound semiconductor layer; depositing a planar layer of insulating material and patterning the planar layer of insulating material to have contact openings over the third and fourth layer; and forming contacts in the openings in the planar layer of insulating material from the surface of the planar layer to the third layer and through the fourth layer to the underlying second layer in order to provide a substantially common plane for the upper surfaces of the contacts to the third and second layers.