Patent ID: 8237140
Filing Date: 2012-08-07
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a substrate; a pair of transistors having a common source region and two drain regions in the substrate; a dielectric layer over the substrate, first and second contact plugs and a common source line in the dielectric layer; an electrode structure having first, second, and third electrode members, wherein the first, second, and third electrode members have coplanar top surfaces; an insulating structure separating each electrode member from one another, the insulating structure having first and second fence members and having a base member, the first fence member between the first and second electrode members, the second fence member between the second and third electrode members, the base member at an intermediate position between the second electrode member and the common source line; a pair of bridges of phase change material, including a first bridge on the first and second electrode members across the first fence member, and a second bridge on the second and third electrode members across the second fence member; and a first contact plug on the second electrode member.