Patent ID: 6127261
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A method of depositing a premetal interlayer dielectric on a semiconductor substrate using a PECVD reactor comprising:precoating an inner surface of the PECVD reactor;wafer temperature soaking the semiconductor substrate;depositing a plurality of layers of a premetal dielectric layer in in-situ deposition upon the semiconductor substrate using the PECVD reactor with each subsequent layer being deposited after a previous layer with no intervening handling, depositing the plurality of layers including:depositing an undoped silane-based oxide layer;depositing a phosphorus silicate glass laver; anddepositing a TEOS-based oxide layer;cleaning the semiconductor substrate following deposition of the plurality of layers; andchemical mechanical polishing the TEOS-based oxide layer without exposing the doped silane-based oxide following the cleaning.