Patent ID: 6083810
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method of semiconductor integrated circuit fabrication, comprising:forming an oxide layer upon a substrate;depositing a silicon layer upon the oxide layer;wherein the silicon layer is formed at a temperature maintained at between 350-550.degree. C. from a chemical precursor selected from the group consisting of disilane and higher order silanes, whereby the formation of silicon crystals is inhibited during deposition so that the as-deposited silicon layer is substantially amorphous;forming a material layer upon the substantially amorphous as-deposited silicon layer at a temperature such that the substantially amorphous as-deposited silicon layer is at least partially converted to polycrystalline material;patterning the material layer;oxidizing the substrate to form a field oxide;removing the material layer and unoxidized portions of the silicon layer; andforming a transistor upon the substrate.