Patent ID: 9116406
Filing Date: 2015-08-25
Classification: G02F,H01L

Abstract:
1. A pixel structure, which is formed on a substrate, the substrate comprising at least two scan lines and at least one data line formed thereon, the pixel structure comprising: a main pixel comprising a first thin film transistor and a first storage capacitor, a gate of the first thin film transistor electrically coupled to one of the two scan lines, a source of the first thin film transistor electrically coupled to the data line, a drain of the first thin film transistor electrically coupled to a first end of the first storage capacitor, and a second end of the first storage capacitor electrically coupled to a common electrode; a first subpixel comprising a second thin film transistor, a third thin film transistor, a second storage capacitor, and a third storage capacitor, a gate of the second thin film transistor electrically coupled to the one of the two scan lines, a source of the second thin film transistor electrically coupled to the data line, a drain of the second thin film transistor electrically coupled to a first end of the second storage capacitor and a source of the third thin film transistor, a second end of the second storage capacitor electrically coupled to the common electrode, a gate of the third thin film transistor electrically coupled to the other one of the two scan lines, a drain of the third thin film transistor electrically coupled to the a first end of the third storage capacitor, and a second end of the third storage capacitor electrically coupled to the common electrode; and a second subpixel comprising a fourth thin film transistor, a fifth thin film transistor, and a fourth storage capacitor, a gate of the fourth thin film transistor electrically coupled to the one of the two scan lines, a source of the fourth thin film transistor electrically coupled to the source of the second thin film transistor, a drain of the fourth thin film transistor electrically coupled to a first end of the fourth storage capacitor and a source of the fifth thin film transistor, a second end of the fourth storage capacitor electrically coupled to the common electrode, and a gate of the fifth thin film transistor electrically coupled to the other one of the two scan lines, wherein different voltages are provided for the main pixel, the first subpixel, and the second subpixel by the first to the fifth thin film transistors and the first to the fourth storage capacitors.