Patent ID: 6287925
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method for forming highly conductive drain and source of a field effect transistor in an active device area of a semiconductor substrate, the method including the steps of:A. implanting a first dopant into said active device area to form a drain extension preamorphization region and a source extension preamorphization region;B. implanting a second dopant into said drain extension preamorphization region to have a drain extension dopant profile along a depth of said drain extension preamorphization region and into said source extension preamorphization region to have a source extension dopant profile along a depth of said source extension preamorphization region, said drain extension dopant profile having a drain extension dopant peak and said source extension dopant profile having a source extension dopant peak;C. performing a RTA (Rapid Thermal Anneal) to recrystallize a portion of said drain extension preamorphization region from a junction between said drain extension preamorphization region and said semiconductor substrate to below said drain extension dopant peak, and to recrystallize a portion of said source extension preamorphization region from a junction between said source extension preamorphization region and said semiconductor substrate to below said source extension dopant peak; andD. performing a LTP (Laser Thermal Process) to recrystallize a remaining portion of said drain extension preamorphization region that has not been recrystallized in said step C to activate a substantial portion of said second dopant in said drain extension preamorphization region, and to recrystallize a remaining portion of said source extension preamorphization region that has not been recrystallized in said step C to activate a substantial portion of said second dopant in said source extension preamorphization region.