Patent ID: 8492869
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A 3D integrated circuit structure comprising: an interface wafer, the interface wafer including a first wiring layer on one side of the interface wafer, an interface layer on the other side of the interface wafer, and through-silicon vias; a first active circuitry layer including active circuitry and a second wiring layer, the first active circuitry layer being bonded face down to the interface wafer, the second wiring layer of the first active circuitry layer being directly bonded to the first wiring layer of the interface wafer; and an additional wafer including active circuitry and a third wiring layer, a stack structure being bonded face down to the additional wafer, the stack structure including the interface wafer and the first active circuitry layer, wherein the first active circuitry layer is less expensive to manufacture relative to the additional wafer.