Patent ID: 7915129
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A method of forming a metal-oxide semiconductor (MOS) transistor on a wafer, the method comprising: forming a gate oxide region and a field oxide region on a substrate, wherein the gate oxide region has a thickness of at least 400 Angstroms; forming a polysilicon layer on the gate oxide region and the field oxide region; forming a sacrificial nitride layer on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region; forming a polysilicon gate by selectively removing portions of the polysilicon layer and the sacrificial nitride layer to expose a portion of the gate oxide region adjacent to the polysilicon gate; forming source/drain regions adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation; forming a spacer layer over the polysilicon gate and source/drain region; selectively removing the spacer layer, the sacrificial nitride layer, and the gate oxide region located over the source/drain region to form sidewall spacers at each end of the polysilicon gate; forming a pre-metal dielectric layer on the high-voltage MOS transistors; and planarizing the pre-metal dielectric layer.