Patent ID: 8053312
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a device isolation region in a substrate; forming photoresist patterns on the substrate where a plurality of gate structures are to be formed; reducing widths of the photoresist patterns by using a descum process until the widths of the photoresist patterns are smaller than those of the gate structures; removing predetermined portions of the substrate using the reduced-width photoresist patterns as an etch mask, thereby forming a plurality of protruded patterns, each of the protruded patterns protruding upwardly from the substrate and having a first side and a second side sloping downward from a top provided between the first and second sides such that each protruded pattern forms a cross-sectional shape of a trapezoid; and forming a plurality of gate conductive layers for the gate structures over the protruded patterns, respectively, wherein the width of each gate conductive layer is greater than the width of each protruded pattern, wherein each gate conductive layer is formed over the first side, the top, and the second side of the corresponding protruded pattern so as to extend below the top of the protruded pattern and along profiles of the first side, the top and the second side of the protruded pattern.