Patent ID: 7984326
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A method of memory downsizing in a computer memory subsystem, the computer memory subsystem comprising one or more channels of computer memory, each channel comprising a plurality of Dual In-line Memory Modules (‘DIMMs’), each DIMM capable of on-die termination (‘ODT’), the method comprising: identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem; disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs; determining, by the firmware module, whether signal integrity for the computer memory subsystem meets acceptability criteria when ODT is enabled for the defective DIMM; and if signal integrity meets the acceptability criteria, continuing, by the firmware module, the POST without disabling any non-defective DIMMs in the same particular channel as the defective DIMM.