Patent ID: 7256440
Filing Date: 2007-08-14
Classification: H01L

Abstract:
1. A semiconductor memory cell having a trench and a planar select transistor, the memory cell comprising: a substrate; a trench arranged in the substrate and having a trench inner wall with a lower region, a middle region and an upper region; a dielectric layer arranged in the lower region at the trench inner wall; a first insulation collar arranged at the trench inner wall in the middle and upper regions, the first insulation collar having an upper edge; a first flilling of the trench comprising a conductive material in the lower and middle regions; a first insulation layer for forming an insulation cover, the first insulation layer being arranged in the trench on the conductive material in an upper region of the trench and being connected to the insulation collar, the first insulation layer which forms the insulation cover covering the upper edge of the first insulation collar so as to extend to the trench inner wall above the upper edge of the first insulation collar; an opening in the insulation collar, which a buried doped region in the substrate, the buried doped region being electrically conductively coupled to the conductive material in the opening in order to form a buried strap; a planar select transistor, having the first gate contact of a first word line, a first diffusion region and a second diffusion region; the first diffusion region being arranged in the substrate and being electrically conductively coupled to the buried doped region; and the second diffusion region being arranged in the substrate and being electrically conductively connected to a bit line contact.