Patent ID: 7305513
Filing Date: 2007-12-04
Classification: G11C

Abstract:
1. A circuit for preventing over-erase in a nonvolatile memory, comprising: a normal cell circuit including a normal cell and a first bit switch for recording an erasing verification of the nonvolatile memory; a reference cell circuit including a reference cell and a second bit switch for verifying an erasing status of the nonvolatile memory; a sense amplifier which receives and compares outputs of the normal cell circuit and the reference cell circuit, so as to verify the erasing or programming state of the normal cell; a constant current source for providing a constant current to the normal cell during an erase operation of the normal cell, thereby preventing over-erase, wherein the constant current is positioned between the first bit switch and the sense amplifier; and wherein the first bit switch is positioned between the normal cell and the sense amplifier, and the second bit switch is positioned between the reference cell and the sense amplifier.