Patent ID: 6300182
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:A. forming a pillar of semiconductor material on a layer of buried insulating material, wherein said pillar has a top surface, a left side surface, a right side surface, a front side surface, and a back side surface, and wherein said pillar has a width and a length;B. forming a dielectric structure comprised of a hardmask dielectric material on said top surface of said pillar;C. forming a first gate dielectric on said left side surface of said pillar and forming a second gate dielectric on said right side surface of said pillar, along a gate length of said length of said pillar;D. depositing a gate electrode material on said dielectric structure and on said first gate dielectric and said second gate dielectric to surround said pillar at said top surface and said left and right side surfaces of said pillar for said gate length of said pillar;E. implanting a first gate dopant at an angle directed toward said gate electrode material on said left side surface of said pillar such that said first gate dopant is not implanted into said gate electrode material on said right side surface of said pillar; andF. implanting a second gate dopant at an angle directed toward said gate electrode material on said right side surface of said pillar such that said second gate dopant is not implanted into said gate electrode material on said left side surface of said pillar;wherein said first gate dopant is different from said second gate dopant such that a threshold voltage at said gate electrode material of said field effect transistor is less than about 0.4 Volts.