Patent ID: 6804771
Filing Date: 2004-10-12
Classification: G06F

Abstract:
A processor for executing instructions, the processor comprising:a processing unit; and a register file having a normal access mode and a transposed access mode for accessing an operand, the register file comprising: an array of storage areas for storing at least one operand for said instructions, wherein the array is organized into a plurality of rows of storage areas and a plurality of columns of storage areas, said at least one operand occupying a plurality of storage areas, wherein each storage area of said plurality of storage areas includes a common plural number of bits; a first decoder for selecting all storage areas in an addressed row of storage areas during normal access mode; and a second decoder for selecting all storage areas in an addressed column of storage areas during transposed access mode, wherein for any operation of a read operation and a write operation one of either the normal access mode and transposed access mode is implemented allowing not more than one of either the first decoder and second decoder to be active to concurrently address multiple storage areas among the array of storage areas to access a given operand, wherein said addressed multiple storage areas for the given operand are along a common row during normal access mode and are along a common column during transposed access mode.