Patent ID: 8990646
Filing Date: 2015-03-24
Classification: G06F,G11C

Abstract:
1. A system comprising: a memory controller to perform an error test routine in response to encountering a memory error, to test for a type of the memory error by changing a content of a memory module to identify a failure pattern, based on writing a cacheline and reading back the cacheline, indicating that the type of the memory error is a hard memory error and identifying which of a plurality of types of hard memory failures caused the hard memory error based on performing at least a pin failure test and a channel failure test, and to adjust a memory handling procedure associated with the memory controller to isolate the memory error in response to a positive outcome of the error test routine, wherein the memory controller is to perform the error test routine and adjust the memory handling procedure at runtime transparent to an operating system; and a storage to store information corresponding to isolating the memory error.