Patent ID: 9136825
Filing Date: 2015-09-15
Classification: H03H

Abstract:
1. A circuit comprising: a first filter comprising a plurality of N paths in parallel between an input and an output, each of-the N paths comprising a first sub-circuit and a switch; a second filter comprising a plurality of N paths in parallel between an input and an output, each of the N paths comprising a second sub-circuit and a switch; clock signals to selectively control switches of the first filter at a same frequency for a first on-time duration, and to selectively control switches of the second filter at the same frequency for a second on-time duration, in which at least one of a) the first and second on-time durations are different, and b) the first and second sub-circuits are different; and a combiner for adding signals from the output of the first filter and from the output of the second filter; where the first filter, the second filter and the combiner together form an N-path tunable filter wherein a center frequency of a response of the N-path tunable filter is controlled by the frequency of the clock signals by shifting an amplitude of a response at the center frequency of the first filter and the second filter, and where an output of the combiner represents a difference between the amplitude of the response of the first filter and the amplitude of the response of the second filter.