Patent ID: 8189405
Filing Date: 2012-05-29
Classification: G11C

Abstract:
1. A data readout circuit comprising: a 1st PMOS transistor configured to operate in a saturation region and including a source connected to a power supply, a drain connected to an input terminal connected to a memory cell of a data readout object, and a gate to which a 1st bias voltage is supplied; a 2nd PMOS transistor including a source connected to the drain of said 1st PMOS transistor, a drain connected to an output terminal, and a gate to which a 2nd bias voltage is supplied; a 1st NMOS transistor including a drain connected to the drain of said 2nd PMOS transistor, a source grounded, and a gate to which a 3rd bias voltage is supplied; and a bias voltage supply section causing said 2nd PMOS transistor to operate in a saturation region and supplying the 2nd bias voltage to the gate of the 2nd PMOS transistor, wherein the 2nd bias voltage is adjusted so as to keep a reference voltage of said input terminal at a junction point between the drain of said 1st PMOS transistor and the source of said 2nd PMOS transistor.