Patent ID: 8252693
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer, the method comprising: forming a semiconductor structure comprising first, second and third layers; etching a first conducting layer to form a first trench for the first conductive trace; patterning a layer of material on the second layer in the first trench to define a patch area on the second layer, wherein the patch area is disposed in a location at which the first trench crosses over the third electrical trace; and etching a second trench in the second layer in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench while leaving material of the layer under the patch area.