Patent ID: 6391525
Filing Date: 2002-05-21
Classification: G03F,H01L

Abstract:
A method of forming a circuit structure for a memory cell containing at least one sub-lithographic gate conductor comprising:providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions, wherein the sidewall template mask comprises at least one of silicon oxynitride, a nitrogen rich film, a photoresist material, a low K polymer material; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask, wherein the sidewall film comprises at least one of silicon oxynitride, silicon oxide, and an acid catalyzed photoresist; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions thereby exposing other portions of the preliminary gate conductor film; removing exposed other portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors leaving exposed the vertical portion of the sidewall film; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.