Patent ID: 6809963
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a memory cell array having multiple twin memory cells arrayed both in a row direction and in a column direction, where each of the twin memory cells has one word gate, a first non-volatile memory element controlled by a first control gate, and a second non-volatile memory element controlled by a second control gate; multiple word lines, each of which is provided for each row of the memory cell array and is shared by the word gates of plural twin memory cells arrayed in the row direction; multiple bit lines, each of which is provided for every pair of adjoining twin memory cells in the row direction and is shared by the first non-volatile memory element included in one twin memory cell of the twin memory cell pair and by the second non-volatile memory element included in the other twin memory cell to be extended in the column direction; an address generation circuit that generates multiple addresses varying sequentially from a specified address; an access control circuit that regulates operations of at least the multiple word lines and the multiple bit lines according to the multiple addresses generated by the address generation circuit, so as to control a reading operation of information; and a detection circuit that detects information read via the multiple bit lines, in the process of selecting the sequentially varying multiple addresses to read information from non-volatile memory elements corresponding to the multiple addresses, the access control circuit causing plural non-volatile memory elements arrayed in the column direction on a preset column to be selected sequentially according to the varying multiple addresses, among the multiple non-volatile memory elements arrayed in the row direction and in the column direction.