Patent ID: 7474234
Filing Date: 2009-01-06
Classification: H03M

Abstract:
1. A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to said pin to a sequence of logic low and logic high values, said decoder comprising: an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of said input signal, said edge detection circuit being connected to said up/down counter to start up counting from a reset value (Nres) upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction, and a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.