Patent ID: 8327071
Filing Date: 2012-12-04
Classification: G06F

Abstract:
1. A method for transmitting messages in a multiprocessor system, comprising: outputting a message produced by a central processing unit (CPU) that is coupled to a parallel processing unit only through a system memory bridge directly to a cache associated with a processing core bypassing a system memory, wherein the cache is one of a plurality of caches that reside within the parallel processing unit and the processing core is one of a plurality of processing cores that reside within the parallel processing unit; translating a virtual address corresponding to the message into a physical address corresponding to a location in a parallel processing memory that is coupled to the cache; storing the message and at least a portion of the physical address in the level 2 cache, wherein the cache may later evict the message and write the message to the parallel processing memory; updating a ready value to indicate that the message is available in the cache; and reading the message from the cache by the processing core.