Patent ID: 6828188
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having, on a single semiconductor substrate, a high-density region containing transistor elements arrayed at a high density and a low density region containing transistor elements arrayed at a low density, comprising the steps of:forming a gate oxide film on a surface of said semiconductor substrate; forming gate electrodes on a surface of said gate oxide film, and forming oxide films on said gate electrodes; uniformly forming a first nitride film having a predetermined thickness on the surface with the gate electrodes formed thereon; masking said high-density region of said semiconductor substrate, and etching said first nitride film in only said low-density region to expose said gate oxide film in gaps between said gate electrodes; uniformly forming a second nitride film having a predetermined thickness on said oxide films which overlies said gate electrodes, on said first nitride film which overlies sides of said gate electrodes, and on said gate oxide film which overlies said semiconductor substrate in said low-density region; forming an interlayer insulating film with an impurity introduced therein on a surface of said second nitride film; annealing said semiconductor device formed so far in an atmosphere containing water vapor; self-aligning said high-density region using said first nitride film positioned on sides of said gate electrodes as an etching stopper to form contact holes reaching said semiconductor substrate in said interlayer insulating film, wherein portions of said second nitride film that are in direct contact with said first nitride film and that are positioned on at least one of the respective sides of said gate electrodes are removed as a result of the self-aligning step; forming contact electrodes connected to said semiconductor substrate in said contact holes; and annealing said semiconductor device formed so far with a forming gas to recover an interfacial level; and planarizing a top surface of the interlayer insulating film; and wherein the step of self-aligning said high-density region comprises the steps of: forming an oxide film on the planarized top surface of the interlayer insulating film; and in said high-density region, masking the oxide film in a particular pattern using a fluorine-based resist, wherein the step of planarizing a top surface of the interlayer insulating film is performed after the step of annealing in an atmosphere containing water vapor and before the step of self-aligning said high-density region.