Patent ID: 7681083
Filing Date: 2010-03-16
Classification: G06F

Abstract:
1. A data processing system, comprising: a system bus; a host bridge connected to the system bus, wherein the host bridge includes a table having a plurality of entries; and a plurality of input/output units connected to the host bridge without a bridge chip located external of the host bridge for isolating errors in the plurality of input/output units from other components of the data processing system, wherein each input/output unit is identified by an identifier and each of the plurality of entries is capable of being assigned to a different input/output unit, wherein the host bridge includes functionality for isolating errors in the plurality of input/output units from other components of the data processing system using the identifier and the table to access an input/output unit State Array that indicates a state of an operation of the at least one of the plurality of input/output units.