Patent ID: 7676643
Filing Date: 2010-03-09
Classification: G11C

Abstract:
1. A data interface device for accessing a memory, comprising: a board clock used in the memory; and selective data capturing, wherein the board clock and the selective data capturing are used to improve an operating rate of the memory interface and to match a point of time that data outputted from the memory is inputted to a memory controller with a internal clock produced by the memory controller, or to match a point of time that data is outputted from the memory controller with the board clock, by feeding back the board clock to the memory controller in order to vary a delay time of data input to the memory controller, and checking a relative phase difference between the board clock and the internal clock in order to synchronize data input to the memory controller with the internal clock, thereby accomplishing memory interface without use of an internal DLL circuit; wherein the selective data capturing uses a register part for storing data inputted into the memory controller; wherein the register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and a feedback clock, and the internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller, thereby the feedback clock is generated.