Patent ID: 7863123
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method of forming a transistor having a high-gate dielectric and a metal, metal alloy or conductive metal compound gate, said method comprising steps of forming a gate stack including a high-κ dielectric layer, a metal, metal alloy or conductive metal compound gate layer on a substrate and at least one of a gate body and a cap, forming silicided regions corresponding to at least one of a source and a drain of said transistor, forming a liner layer over said gate stack and said at least one of a source and a drain of said transistor, forming a layer of fill material having a height equal to or greater than said gate stack, selectively etching said fill material to said liner layer, selectively etching said liner layer and said gate stack to said metal gate and said at least one of a source and drain region, and filling openings formed by said selectively etching steps with metal, metal alloy and/or one or more conductive metal compounds.