Patent ID: 6356960
Filing Date: 2002-03-12
Classification: G06F

Abstract:
A computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said first memory storing instructions for operation of said CPU, said integrated circuit device further comprising a debugging port connected to said bus on the integrated circuit chip and to an external debugging computer device having a second memory, said chip having circuitry responsive to first, second and third control signals from said external debugging device via said debugging port whereby said first control signal stops execution by the CPU of instructions obtained from said first memory, said second control signal causes said CPU to fetch from said second memory a debugging routine to be executed by the CPU and said third control signal restarts operation of the CPU after said debugging routine with execution of instructions from an address determined by said external debugging device, whereby said instructions in said first memory are independent of said debugging routine.