Patent ID: 6584006
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A memory device comprising:a plurality of bit lines; a plurality of word lines, the plurality of word lines forming a cross-point array with the plurality of bit lines; a plurality of memory cells, whereby one of the plurality of memory cells is located at each of the cross-points in the array; a bit decoder coupled to the bit lines, the bit decoder having current sources and current sinks coupled to the bit lines; a word decoder coupled to the word lines, the word decoder having current sources and current sinks coupled to the word lines; and a first series of switch circuits coupled to two adjacent bit lines, the first series of switch circuits located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines; whereby the memory cell at the corresponding cross-point is selected for writing when the corresponding bit and word lines are provided with a programming current.