Patent ID: 9006765
Filing Date: 2015-04-14
Classification: F21L,F21Y,H01L

Abstract:
1. An apparatus, comprising: a plurality of light emitting diode chips, each comprising a generally planar active area, wherein a ratio of a length of the active area to a width of the active area is at least 1.5:1; and a package having a recess defined by a bottom surface and four sidewalls in which pairs of sidewalls are generally co-parallel and intersect to define four corners of the recess, the plurality of light emitting diode chips disposed in the recess, and arranged around the periphery of the recess, with lengths of the light emitting diode chips co-parallel to the sidewalls, and each end of each of the light emitting diode chips disposed around the periphery of the recess either abuts one of the corners of the recess, or abuts an edge of another light emitting diode chip arranged around the periphery of the recess, and one or more of the plurality of light emitting diode chips are indirectly coupled to receive a biasing voltage from a pair of bonding wires respectively connected to different light emitting diode chips of the plurality.