Patent ID: 6430705
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A method implemented in a hardware test system for testing a plurality of microprocessors having one or more of a plurality of silicon revisions, the method comprising:defining a base test class having one or more member test operations; defining a plurality of derived classes, said derived classes inheriting said one or more member test operations from the base class, each of said derived classes corresponding to one of said plurality of silicon revisions and including particular instructions corresponding to a microprocessor of said corresponding silicon revision, wherein said particular instructions control the routing of test signals to said corresponding microprocessor; for each of said plurality of microprocessors, instantiating an object from a corresponding one of said plurality of derived classes; for each of said plurality of microprocessors, executing said one or more member test operations of said corresponding object, wherein said executing generates a plurality of said test signals; and inputting said test signals to each of said plurality of processors.