Patent ID: 7783950
Filing Date: 2010-08-24
Classification: G11B,H03M

Abstract:
1. A data writing apparatus for writing main data and parity data used for error correction of the main data, to a storage apparatus, the data writing apparatus comprising: a writing circuit for writing the main data and the parity data to the storage apparatus; a parity generation circuit for generating the parity data in parallel with writing of the main data; and a timing adjustment circuit for performing adjustment so that a head of the generated parity data appears after a tail-end of the main data, consecutively, as regards timing of writing; wherein the main data and the parity data, whose timing is adjusted by the timing adjustment circuit, are provided to the writing circuit; wherein the timing adjustment circuit delays the main data, with, as a delay amount, a value obtained by subtracting, from time required for generation of the parity data in the parity generation circuit, time required for supplying data from the head to the tail-end of the main data, to the writing circuit.