Patent ID: 6516407
Filing Date: 2003-02-04
Classification: G06F

Abstract:
An information processor comprising:an instruction register for storing a fetched instruction, said instruction being one of instructions including an operational instruction with a function of generating a first condition code, a condition code conversion instruction having a reference condition code, a conditional instruction having a reference flag; an instruction decoder for decoding an instruction stored in said instruction register; a control circuit for performing a control to execute said stored instruction in response to a decoded result; a first condition code register; a second condition code register; and a condition code conversion circuit for converting contents of said first condition code register into a second condition code depending on said reference condition code, said second condition code having a condition flag, wherein said control circuit makes said generated first condition code stored into said first condition code register in response to a decoded result of said operational instruction, makes said converted second condition code stored into said second condition code register in response to a decoded result of said condition code conversion instruction, and performs a control to execute an operation of said conditional instruction in response to a decoded result of said conditional instruction only when said reference flag coincide with said condition flag in said second condition code register.