Patent ID: 6163173
Filing Date: 2000-12-19
Classification: H03K

Abstract:
A dynamic circuit comprising:an intermediate precharge node;an output logic stage connected to said intermediate precharge node and providing an output;a logic threshold adjustment circuit connected to said output logic stage; said logic threshold adjustment circuit receiving a selection input to adjust a logic threshold of said output logic stage;said logic threshold adjustment circuit including a plurality of series connected P-channel field effect transistors (PFETs) connected in series with a plurality of series connected N-channel field effect transistors (NFETs); said plurality of PFETs and said plurality of NFETs being coupled between a supply voltage and ground potential with a source terminal of a top one of said PFETs coupled to a supply voltage, and a source terminal of a bottom one of said NFETs coupled to a ground connection; a drain of a common connected ones of said series connected PFETs and NFETs being coupled to said output node and a gate terminal of common connected ones of said series connected PFETs and NFETs being coupled to said intermediate precharge node; both said top one of said PFETs and said bottom one of said NFETs having a gate input selectively receiving said selection input to adjust a logic threshold of said output logic stage.