Patent ID: 7949695
Filing Date: 2011-05-24
Classification: G06F

Abstract:
1. A two's complement digital circuit comprising: a first converter receiving a first floating-point data and converting said first floating-point data into a two's complement format data by preserving the sign bit and the exponent and by taking the two's complement of the mantissa; a register connected to the first converter buffering the two's complement format data from the first converter; a first shifter connected to the register fetching the two's complement format data from the register and aligning the two's complement format data by a respective exponent; an operator connected to the first shifter directly operating on the two's complement format data; a second shifter connected to the operator normalizing the two's complement format data and directly storing the two's complement format data to the register; and a second converter connected to the register receiving the two's complement format data from the register, converting said two's complement format data to a second floating-point data by preserving the sign bit and the exponent and by taking the two's complement of the mantissa to obtain the second floating-point data, and outputting said second floating-point data.