Patent ID: 6134639
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A serial access memory circuit comprising:a memory array for storing data;a serial access register having first and second portions, each portion having a plurality of addressable cells for storing data from the memory array, the first portion having a last cell with a last address;a counter circuit responsive to a start address signal for providing a sequence of address signals based on the start address signal, with each address signal corresponding to a cell in the serial access register;an output pipeline circuit having a data buffer for storing data from one of the addressable cells based on one of the sequence of address signals and an output circuit coupled to the data buffer to output data from another cell based on an address signal preceding the one address signal; anda control circuit coupled to the counter circuit, including at least one logic gate, and responsive to:(a) the data buffer storing data from the last cell of the first group of cells, or(b) the counter circuit providing an address signal corresponding to an address exceeding the last address of the first portion to re-start the counter circuit at another start address corresponding to a cell in the second portion of the serial access register.