Patent ID: 6944744
Filing Date: 2005-09-13
Classification: G06F

Abstract:
1. A processor, comprising: an instruction scheduler configured to receive instructions and schedule the instructions for issuance, wherein said instructions comprise first instructions specifying a first data type having a first bit-width and second instructions specifying a second data type having a second bit-width; a functional unit configured to receive instructions issued from said scheduler and to perform an operation according to each issued instruction, wherein said functional unit comprises a plurality of functional unit portions, wherein each functional unit portion is configured to operate on operands of said first data type, and wherein said plurality of functional unit portions are configured to be locked together to operate on operands of said second data type; wherein said scheduler is configured to independently schedule said first instructions to separate ones of said plurality of functional unit portions, to atomically schedule a first one of said second instructions to said functional unit with the plurality of functional unit portions locked together to operate concurrently on an operand of said first one of said second instructions, and to independently schedule a second one of said second instructions to said functional unit, wherein said plurality of functional unit portions are configurable to operate non-concurrently on portions of an operand of said second one of said second instructions.