Patent ID: 6021073
Filing Date: 2000-02-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array comprising memory cells arranged in matrix form having row lines and column lines, the memory cells in a same row being commonly connected to one of the row lines, the memory cells in a same column being commonly connected to one of the column lines;voltage boosting means, connected to at least one power source terminal of the row decoder, for boosting a power source voltage externally applied, the voltage boosting means generating a boosted voltage which is higher than the power source voltage, the boosted voltage being applied to the row decoder as a power source, and then applied to a row line selected by the row decoder, wherein the boosted voltage is applied to the memory cells through the selected row line by the row decoder; andat least two layered metal wiring layers for transmitting signals, a signal for selecting the memory cell is transmitted via at least one of the metal wiring layers.