Patent ID: 9006074
Filing Date: 2015-04-14
Classification: H01G,H01L

Abstract:
1. A method of forming an integrated circuit, comprising the steps of: providing a substrate comprising a semiconductor; forming a plurality of transistors in said substrate; forming at least one metal level over said substrate, said metal level containing metal interconnects; forming a bottom plate of an isolation capacitor; forming a silicon dioxide dielectric layer of said isolation capacitor over said bottom plate; forming a polymer dielectric layer of said isolation capacitor over said silicon dioxide dielectric layer, said polymer dielectric layer extending across said integrated circuit; forming a via hole through said polymer dielectric layer; forming a top plate of said isolation capacitor over said polymer dielectric layer; forming a bond pad on said top plate; and forming another bond pad outside said isolation capacitor, said another bond pad being electrically coupled to an instance of said metal interconnects through a via in said via hole.