Patent ID: 6185120
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A semiconductor memory device which utilizes a folded bit line system, comprising:a plurality of bit lines which are placed in a parallel direction;a plurality of word lines which are placed in a vertical direction, said bit lines and said word lines being perpendicularly crossed to each other;a plurality of device region patterns which are arranged so as to cross said bit lines and said word lines;said device region pattern has first wiring patterns in both ends and a second wiring pattern in a center portion,a capacitor contact is arranged in each of said first wiring patterns,a bit contact is arranged in said second wiring pattern,a separating distance between adjacent device region patterns being equal to a first space which corresponds to a closest vertical distance between said capacitor contacts,a separating distance between closest portions of said adjacent device region patterns being equal to a second space,each of said device region pattern being inclined relative to said bit line with a predetermined angle so that the first space exceeds the second space.