Patent ID: 6411557
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A memory redundancy circuit in single-port hierarchical memory structure having a predetermined memory access speed and a memory access period, comprising:a. a memory module having (1) memory cells disposed to store data, the memory cells including a designated group of memory cells being assigned to represent a logical portion of the memory structure and a redundant group of memory cells; (2) hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; (3) hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; (4) a redundancy controller coupled with the designated group and the redundant group, the redundancy controller assigning the redundant group to the logical portion of the memory structure, responsive to a preselected memory group condition, and providing redundancy thereby; b. hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifiers of selected memory modules; c. hierarchically-coupled local and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.