Patent ID: 8030972
Filing Date: 2011-10-04
Classification: H03K

Abstract:
1. A latched comparator circuit comprising: a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit; a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit; a reset terminal for receiving a reset signal; reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal; a load unit operatively connected to the cross-coupled pair of transistors; and a bias circuit arranged to receive the reset signal and to bias the load unit such that a conductivity of the load unit is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal; wherein the load unit comprises a first load circuit operatively connected between a first transistor of the cross-coupled pair of transistors and a reference node, and a second load circuit operatively connected between a second transistor of the cross-coupled pair of transistors and the reference node, wherein the bias circuit is arranged to bias the first and the second load circuit such that a conductivity of the first load circuit and a conductivity of the second load circuit are higher during the second phase of the reset signal than during the first phase of the reset signal; wherein the first and second transistors of the cross-coupled pair are MOS transistors of the same type; wherein the first/second load circuit comprises a first/second load transistor of the same type as the first/second transistor of the cross-coupled pair, the first/second load transistor having a drain terminal operatively connected to the source terminal of the first/second transistor of the cross-coupled pair, a source terminal operatively connected to the reference node, and a gate terminal arranged to receive a bias voltage; wherein the bias circuit comprises: a first MOS transistor of opposite type to the first and second load transistor, wherein the first MOS transistor is arranged to be biased with a dc voltage on its gate terminal; a bias-voltage generating transistor of the same type as the first and second load transistor, wherein the gate terminal of the bias-voltage generating transistor is operatively connected to the drain terminal of the first MOS transistor and the source terminal of the bias-voltage generating transistor is operatively connected to the reference node; and a switch device operatively connected between the drain and gate terminals of the bias-voltage generating transistor, wherein the switch device is arranged to be closed during the first phase of the reset signal and open during the second phase of the reset signal; and wherein the bias circuit is arranged to generate the bias voltage for the first and the second load transistor on the gate terminal of the bias-voltage generating transistor.