Patent ID: 8384437
Filing Date: 2013-02-26
Classification: G06F,H03K

Abstract:
1. A semiconductor device comprising clock gating logic, the clock gating logic comprising: clock freezing logic arranged to receive a clock signal comprising a selected clock polarity and an enable signal, and output a gated clock signal substantially corresponding to a selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state; polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal; and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of the comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic; wherein the polarity comparison logic and the selector logic are further arranged such that, upon the enable signal transitioning from the active state to the inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal.