Patent ID: 9136264
Filing Date: 2015-09-15
Classification: H01L,H03F

Abstract:
1. A metal oxide semiconductor (MOS) transistor comprising: an active region including a channel region; a trench insulating isolation region disposed in a substrate and surrounding the active region to define the active region in the substrate; a gate electrode disposed over the active region without overlapping with the isolation region; a source region and a drain region disposed in first and second portions of the active region, respectively, the first and second portions being disposed at first and second sides of the gate electrode, respectively, the first side opposing the second side; a first blocking region disposed in a third portion of the active region and including a first portion disposed between a third side of the gate electrode and the isolation region and directly between the source region and the drain region in a plan view, the first portion being coplanar with the source and drain regions; and a second blocking region disposed in a fourth portion of the active region and including a second portion disposed between a fourth side of the gate electrode and the isolation region and directly between the source region and the drain region in a plan view, the fourth side opposing the third side, the second portion being coplanar with the source and drain regions, wherein the source region and the drain region have a first conductivity type and the first and second blocking regions have a second conductivity type opposite to the first conductivity type.