Patent ID: 7087959
Filing Date: 2006-08-08
Classification: H01L

Abstract:
1. A metal-oxide-semiconductor (MOS) device, comprising: a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane; first and second source/drain regions formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; a gate formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions; a first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions; and a shielding structure formed substantially in the first dielectric region, at least a portion of the shielding structure being disposed adjacent at least one of a bottom wall of the first dielectric region and at least one sidewall of the first dielectric region; wherein at least a portion of the gate is formed on a sidewall of the first dielectric region proximate the second source/drain region and at least a portion of the shielding structure is formed on the bottom wall of the first dielectric region, the shielding structure being spaced apart from the gate.