Patent ID: 6727734
Filing Date: 2004-04-27
Classification: G11C,H03L

Abstract:
A delay-locked loop producing an output clock signal at a clock output terminal from an input clock signal applied to a clock input terminal, the delay-locked loop comprising:a comparator having a first comparison input terminals coupled to receive the input clock signal and a second comparison input terminal coupled to receive the output clock signal, the comparator generating at least one delay command signal indicative of the timing of the input clock signal relative to the timing of the output clock signal, the comparator comprising: a comparison circuit coupled to receive the input clock signal and the output clock signal, the comparison circuit generating comparison pulses corresponding to the timing of the input clock signal relative to the output clock signal; an integrator coupled to receive the comparison pulses, the integrator generating a control signal responsive thereto; and a control circuit coupled to receive the control signal, the control circuit generating the at least the one delay command signal; and a variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other; a delay select circuit receiving at least the one delay command signal from the comparator, the delay select circuit being operable to generate at least one control signal responsive to the at least one delay command signal; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which the input clock signal is coupled to produce the output clock signal between the clock input terminal and the clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal.