Patent ID: 9123579
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a memory array region and a periphery region; a stack structure of memory layers formed over the substrate in the memory array region; a transistor structure having a gate structure formed in the periphery region; an underlying layer between and adjacent to both the substrate and a bottom portion of the stack structure in the memory array region, the underlying layer solely comprising one or more non-conducting layers between the substrate and the stack structure in the memory array region; and a semiconductor layer formed on a sidewall of the stack structure and disposed in a vertical direction with respect to a major surface of the substrate, wherein the underlying layer has a thickness that is approximately equal to a height between the substrate and the bottom portion of the stack structure in the memory array region, a bottom portion of the gate structure in the periphery region is disposed at a height from the substrate that is less than the height between the substrate and the bottom portion of the stack structure in the memory array region, a first vertical surface of the semiconductor layer contacts an insulating layer formed over the gate structure, and a second vertical surface of the semiconductor layer is in contact with each of the memory layers of the stack structure.