Patent ID: 6115282
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A dynamic memory comprising:a memory cell array made of memory capacitor cells at the various intersections between plural bit line pairs and plural word lines for storing memory data in each cell;a RAS signal input to the memory cell array having an active state and a de-active state;a bit line equalizer which precharges the bit line pairs to a prescribed voltage;plural sense amplifiers which amplify a minute voltage difference that appears on the bit line pairs;a word line driving circuit which drives one word line selected from the plural word lines;wherein upon activation of the RAS signal, signaling a memory operation, a series of setting operations are initiated, and upon deactivation of the RAS signal a series of resetting operations are initiated, andmeans responsive to the state of the RAS signal for stopping the setting operation when the RAS signal is reset from an active state to the de-active state before driving of the word line is commenced so that the memory cell capacitor connected to the word line is not connected to the bit line for the current memory operation.