Patent ID: 8683249
Filing Date: 2014-03-25
Classification: G06F,Y02D

Abstract:
1. A computer system comprising: a first nonvolatile memory that stores a first program, accepts read and write operations while operating at a first power consumption, and holds the first program while operating at a second power consumption smaller than the first power consumption; a second nonvolatile memory that stores a second program or data, accepts read and write operations while operating at a third power consumption, and holds the stored program or data while operating at a fourth power consumption smaller than the third power consumption; a processor that executes the first program or the second program at a fifth power consumption when receiving a restart instruction and stops execution of the first program or the second program at a sixth power consumption smaller than the fifth power consumption when receiving a temporary halt instruction; a first power control circuit that causes the first nonvolatile memory to operate at the first power consumption and transmits the restart instruction to the processor when detecting change of an input signal to the processor, and causes the first nonvolatile memory to operate at the second power consumption and transmits the temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed; and a second power control circuit that causes the second nonvolatile memory to operate at the third power consumption before the processor executes the second program, or before the processor reads the data, or before the processor writes the data, wherein time necessary for the first nonvolatile memory to be able to accept the read and write operations from the processor from when the first power control circuit causes the first nonvolatile memory to operate at the first power consumption is shorter than time necessary for the second nonvolatile memory to be able to accept the read and write operations from the processor from when the second power control circuit causes the second nonvolatile memory to operate at the third power consumption.