Patent ID: 6583644
Filing Date: 2003-06-24
Classification: H03K

Abstract:
An output buffer circuit for buffering output data, the circuit comprising:a bias voltage generator for generating first and second bias voltages responsive to a reference voltage; an output driver in signal communication with said bias voltage generator for driving an output terminal; a first slew rate controller in signal communication with said output driver for controlling a pull-up slew rate of said output driver in response to said output data and said first bias voltage; a second slew rate controller in signal communication with said output driver for controlling a pull-down slew rate of said output driver in response to said output data and said second bias voltage; a slew rate compensator in signal communication with the output ends of said first and second slew rate controllers and said output terminal for compensating for slew rate variation in response to a change in the load capacitance of the output terminal; and a high voltage protector for dropping a voltage applied to the output terminal and providing the dropped voltage to the output driver and the slew rate compensator if a voltage higher than a power supply voltage is applied to the output terminal.