Patent ID: 6746924
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A method of fabricating an asymmetric extension MOSFET device using a drain side spacer comprising:forming a semiconductor device having a substrate on which a gate conductor having sidewalls separates a source region and a drain region, and having an oxide layer formed over the gate conductor, the source region and the drain region, and a nitride layer formed over the oxide layer; forming a photoresist mask over at least a portion of the drain region; performing an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and on at least one sidewall of the gate conductor from damage by the angled ion implant, such that the angled ion implant selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor to form damaged portions of the nitride layer; removing the damaged portions of the nitride layer while leaving the undamaged portions of the nitride layer as a nitride mask to protect at least a portion of the drain region and at least one gate sidewall from a subsequent dopant implant; and performing at least one dopant implant into the source region and the drain region while using the undamaged portions of the nitride layer as a mask to form the asymmetric extension MOSFET device.