Patent ID: 6818505
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A non-volatile semiconductor memory device comprising:a semiconductor substrate; a gate insulating film provided on a main surface of said semiconductor substrate; an interlayer insulating film provided on said gate insulating film; a first floating gate electrode provided to be in contact with said gate insulating film and embedded in said interlayer insulating film with an upper surface only being exposed; a second floating gate electrode provided on said interlayer insulating film; a third floating gate electrode provided to cover said first floating gate electrode, said second floating gate electrode and said interlayer insulating film so as to electrically connect said first floating gate electrode and said second floating gate electrode; an insulating film provided to cover said third floating gate electrode; and a control gate electrode provided to cover said insulating film; wherein said second floating gate electrode has a bottom surface positioned to be higher than an upper surface of said first floating gate electrode.