Patent ID: 7630243
Filing Date: 2009-12-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part capable of accumulating and retaining an electric charge injected from the second electrode, the nonvolatile memory cells capable of reading stored contents according to a conductive state between the second electrodes that varies depending on a potential of the first electrode and an accumulated electric charge amount of the charge retention part, and arranged in a row direction and a column direction in a form of a matrix, wherein the first electrodes of the memory cells on the same row are connected to a common word line, one of the second electrodes is connected together between the two adjacent memory cells in the row direction, one of the second electrodes of each of the memory cells on the same column is connected to a common first bit line, the other of the second electrodes of each of the memory cells on the same column is connected to a common second bit line, and the first bit lines and the second bit lines are alternately arranged; a read circuit for selecting a pair of the first bit line and the second bit line connected to a selected memory cell to be read, applying a first read voltage to the selected first bit line, applying a second read voltage to the selected second bit line, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line, the second adjacent bit line being the first bit line that is adjacent to the selected second bit line on the opposite side of the selected first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.