Patent ID: 8369169
Filing Date: 2013-02-05
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a voltage generator configured to generate a first high voltage, a second high voltage, a first low voltage, and a second low voltage; and a sense amplifier comprising a first inverter and a second inverter constituting a latch between a first line and a second line, wherein an NMOS transistor of the first inverter and an NMOS transistor of the second inverter have well biases different from each other and a PMOS transistor of the first inverter and a PMOS transistor of the second inverter have well biases different from each other, wherein the first high voltage and the first low voltage are used as well biases of the first inverter, and the second high voltage and the second low voltage are used as well biases of the second inverter, wherein the voltage generator comprises: a first high voltage generator configured to generate the first high voltage and adjust the level of the first high voltage in response to a first high voltage tuning signal; a second high voltage generator configured to generate the second high voltage and adjust the level of the second high voltage in response to a second high voltage tuning signal; a first low voltage generator configured to generate the first low voltage and adjust the level of the first low voltage in response to a first low voltage tuning signal; and a second low voltage generator configured to generate the second low voltage and adjust the level of the second low voltage in response to a second low voltage tuning signal.