Patent ID: 6996014
Filing Date: 2006-02-07
Classification: G01R,G11C

Abstract:
1. A nonvolatile memory device comprising: an array of memory cells to store data; a Y-gating circuit to gate data stored in a group of the memory cells; and a page buffer circuit coupled between the memory cell array and the Y-gating circuit, wherein the page buffer circuit comprises a first latch having a first latch node and a second latch node; a first switch configured to connect the first latch node to a sense line; a second switch configured to connect the first latch node to a data line via the Y-gating circuit; a reset part configured to reset the first latch; a third switch connected to the sense line and the second latch node and configured to discharge the second latch node; a current source configured to supply a current to the sense line; a second latch having a third latch node and fourth latch node; a set part configured to set the second latch; a fourth switch connected to the sense line and the third latch node and configured to discharge the third latch node; a fifth switch configured to isolate the third latch node from the sense line; a sixth switch configured to connect either one of the third and fourth latch notes to the data line via the column gate circuit; and a seventh switch connected to the first latch node and configured to output program pass/fail information.