Patent ID: 6479869
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A semiconductor device comprising:a one-chip substrate having a circuit formation region allocated on one surface thereof; a plurality of external connection terminals arranged on said one surface outside said circuit formation region; an internal circuit provided in said circuit formation region; a power line connected to one of said external connection terminals and to said internal circuit; a guard ring formed in said circuit formation region to surround said internal circuit; active elements formed parasitic to said guard ring, formed along said guard ring, formed overlying said guard ring, and connected to said power line, each of said active elements being operable to maintain a blocking state when a voltage applied from said power line is equal to or lower than a proper operating voltage for said internal circuit, and each of said active elements being operable to become conductive when said applied voltage exceeds said proper operating voltage for said internal circuit before said applied voltage reaches a breakdown voltage of said internal circuit; and capacitive elements formed parasitic to said guard ring, formed along said guard ring, formed overlying said guard ring, and connected to said power line.