Patent ID: 9196447
Filing Date: 2015-11-24
Classification: H01J,H01L,H01T

Abstract:
1. A method for forming a self-aligned gated emitter cell, comprising: providing a multilayer structure, comprising: using a first lithography process to define a via at a portion of the at least one gate electrode layer; forming the via through the at least one gate electrode layer, the via having a first lateral dimension in a plane of the gate electrode layer; using at least a second lithography process to define: using at least one etching process to etch at least a portion of the gate electrode layer to form the gate aperture and the etch barrier, and to etch at least a portion of the intermediate layer to form an emitter structure. at least partially surrounded by a trench, the multilayer structure, such that a tip of the emitter structure is formed proximate to a center of the etch barrier.