Patent ID: 7189594
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A method for fabricating wafer level package having a plurality of separation and conductive layers formed on a surface of an integrated circuit chip, the method comprising the steps of: forming at least one first separation layer on the surface of the integrated circuit chip having a bondpad thereon, wherein a portion of the bondpad is exposed; forming at least one first conductive layer on the at least one first separation layer, wherein the at least one first conductive layer is electrically coupled to the bondpad and extends substantially laterally away therefrom in a predetermined direction for a first predetermined length; forming at least one second separation layer on the at least one first conductive layer wherein a portion of the at least one first conductive layer extending substantially laterally away from the bondpad in the predetermined direction for a first predetermined distance is exposed; forming at least one second conductive layer on the at least one second separation layer wherein the at least one second conductive layer is electrically coupled to the exposed portion of the at least one first conductive layer and extends substantially laterally away from the bondpad in the predetermined direction; and forming at least one third separation layer on the at least one second conductive layer wherein a portion of the at least one second conductive layer extending substantially laterally away from the bondpad in the predetermined direction is exposed wherein solder is electrically couplable to the exposed portion of the at least one second conductive layer whereby the solder is electrically communicable with the bondpad and the exposed portion of the at least one first conductive layer is substantially adjacent to the extremity of the at least one first conductive layer distal to the bondpad, and a chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.