Patent ID: 7965767
Filing Date: 2011-06-21
Classification: H04N

Abstract:
1. An apparatus, comprising: an input buffer to receive a reference kernel, the reference kernel comprising multiple actual pixel values; a first filtering module to produce, through filtering in a first direction, a first set of one or more half-sample interpolated pixel values from a plurality of the actual pixel values; a second filtering module coupled serially to the first filtering module to produce, through filtering in a second direction, a second set of one or more half-sample interpolated pixel values from the first set of one or more half-sample interpolated pixel values; a third filtering module, parallel to the first filtering module, to produce through filtering in a second direction, a third set of one or more half-sample interpolated pixel values from a plurality of the actual pixel values substantially simultaneously with the second filtering module; a logic circuit to generate a quarter-sample interpolated pixel value from a combination of pixel values selected from the actual pixel values, the first set of interpolated pixel values, the second set of interpolated pixel values, and the third set of interpolated pixel values.