Patent ID: 6721908
Filing Date: 2004-04-13
Classification: H03M

Abstract:
A device for generating L addresses, which are smaller in number than 2mÃ—Ng virtual addresses, for reading data from an interleaver memory in which L data bits are stored, the device comprising:a selection circuit including Ng PN (Pseudo Noise) generators each including m memories, wherein one of the PN generators generates (OSVâˆ’1) offset values (OSV) satisfying OSV=2mÃ—Ngâˆ’L and (2mâˆ’OSV) non-zero states in response to a first clock signal, and the other PN generators each generate (2mâˆ’1) non-zero states, wherein the selection circuit periodically selects the PN generators according to a predetermined order in response to a select signal and outputs a state generated from the selected PN generator; means for detecting each offset state from one PN generator, providing said select signal for not selecting said one PN generator so that the detected offset state is not output, and generating high address bits related to each selection of the PN generators in response to clock pulses of a second clock signal having a shorter period than the first clock signal; means for generating low address bits determined by subtracting one from each state output from the selection circuit when a number of selection periods of the PN generators is smaller than 2m, and generating low address bits corresponding to 2mâˆ’1 when the number of selection periods is 2m; and an address buffer for storing the addresses, said L addresses each being comprised of the high address bits and the low address bits.