Patent ID: 6255188
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method of forming a field oxide and an active area for an integrated circuit, comprising:forming a layer of silicon dioxide over a substrate;forming a layer of polysilicon over said silicon dioxide layer;forming a layer of silicon nitride over said polysilicon layer;substantially removing said silicon nitride and polysilicon layers over said substrate in a region where said field oxide is to be formed, wherein at least a portion of the remaining silicon nitride layer and remaining polysilicon layer form respectively a silicon nitride mask and a polysilicon buffer configured in a substantially stacked manner to substantially define said active area;forming a field oxide in said field oxide region;substantially removing said silicon nitride mask; andapplying an etching selectivity solution to said polysilicon buffer to substantially remove said polysilicon buffer without substantially affecting said field oxide, said etching selectivity solution including at least one component selected from the group consisting essentially of HPO.sub.3, HNO.sub.3, and CH.sub.3 COOH.