Patent ID: 6541840
Filing Date: 2003-04-01
Classification: H01L

Abstract:
An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, said first P-well region is formed in contact on both sides of the first N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a first node and a second node formed between said first P-well region and said bottom N-well region, wherein a fixed number of second N-well regions without transistors or dispersion regions are formed in said first P-well region.