Patent ID: 6727151
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising:providing a sacrificial oxide layer on a substrate; depositing a polish stop layer overlying said sacrificial oxide layer; depositing an oxide layer overlying said polish stop layer; forming an opening through said oxide layer and said polish stop layer to said sacrificial oxide layer; forming first polysilicon spacers on sidewalls of said opening wherein said first polysilicon spacers form said elevated source/drain structure; forming second polysilicon spacers on said first polysilicon spacers; removing said oxide layer and said sacrificial oxide layer exposed within said opening; growing an epitaxial silicon layer within said opening; forming a gate dielectric layer within said opening overlying said second polysilicon spacers and said epitaxial silicon layer; depositing a gate material layer within said opening; and polishing back said gate material layer, said first polysilicon spacers and said second polysilicon spacers to said polish stop layer thereby completing formation of said MOSFET having an elevated source/drain structure in the fabrication of said integrated circuit device.