Patent ID: 7000146
Filing Date: 2006-02-14
Classification: G06F

Abstract:
1. A system comprising: a voltage monitor to monitor a voltage of the system and to transmit a voltage monitor signal if the voltage falls below a predetermined threshold; a power delay circuit to transmit a power delay signal in response to receiving a voltage monitor signal and to transmit a reset signal if the voltage monitor signal indicates a reset condition or in response to an external event reset signal; a memory sub-system to store digital data and having a self-refresh circuit, the self-refresh circuit causing the memory sub-system to enter into a self-refresh sequence; and a memory controller to control and configure the memory sub-system, the memory controller having a power fail controller to receive a power delay signal or a reset signal from the power delay circuit, the power controller asserting a system reset signal and sending two configuration signals in response to the power delay signal or external event reset signal, the configuration signals indicating whether the external event reset signal was detected for at least a predetermined amount of time and at least one of a power failure or an external reset event is detected.