Patent ID: 6990149
Filing Date: 2006-01-24
Classification: H04N

Abstract:
1. A circuit for full matching a plurality of candidate blocks in a search window with a reference block, the circuit comprising: an address generator which generates a first address signal and a second address signal according to an address skip signal; a reference block memory which stores a plurality of reference block pixel data composing the reference block and outputs the reference block pixel data that are stored in response to the first address signal; a search window memory which stores a plurality of candidate block pixel data in two separate sub-regions of the search window memory and outputs the candidate block pixel data that are stored from each of the sub-regions in response to the second address signal; a processor element unit including a plurality of processor elements, each of said processor elements receiving a control signal, the reference block pixel data, and the candidate block pixel data and calculating and accumulating absolute differences between the reference block pixel data and the corresponding candidate block pixel data to output an accumulated absolute difference (AAD) value for all of the reference block pixel data; a comparison unit which receives a predetermined minimum AAD value and the AAD values sequentially output from the processor element unit, compares the minimum AAD value with each of the AAD values and outputs the control signal for each of the processor elements, the control signal being disabled when the AAD value is greater than the minimum AAD value, said control signal controlling whether to enable or disable the corresponding processor element performing AAD value computation; and a logic circuit which receives the control signals and outputs the address skip signal according to the logic state of the control signals.