Patent ID: 7315935
Filing Date: 2008-01-01
Classification: G06F

Abstract:
1. A microprocessor comprising: a plurality of functional units, wherein said plurality of functional units is configured to collectively operate on a maximum number of operands in a given execution cycle, wherein said plurality of functional units is grouped into a plurality of distinct issue slots, and wherein each of said plurality of issue slots includes at least two functional units of different types; a register file configured to provide a number of read ports that is insufficient to provide said maximum number of operands to said plurality of functional units in said given execution cycle; and an arbitration logic coupled to allocate said read ports of said register file for use by selected functional units during said given execution cycle, wherein said arbitration logic is configured to allocate portions of said read ports to functional units included in each of said plurality of issue slots, and wherein said portions are respectively associated with said issue slots.