Patent ID: 6084435
Filing Date: 2000-07-04
Classification: H03K

Abstract:
A logic circuit comprising:a first transistor having a logic signal supplied to a base and a collector connected to an output node;a second transistor having a collector connected to an emitter of the first transistor and an emitter connected to a reference potential, wherein a collector current is supplied to the first transistor corresponding to the level of the control signal supplied to the base;a p-channel insulated gate field-effect transistor connected between a power supply and an output node;first bias circuit for supplying a bias voltage to a gate of the p-channel insulated gate field-effect transistor as the load; andan n-channel insulated gate field-effect transistor connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, anda second bias circuit for supplying a bias voltage to the gate of the n-channel insulated gate field-effect transistor.