Patent ID: 8091049
Filing Date: 2012-01-03
Classification: G06F

Abstract:
1. A method for generating a transistor-level description of a subcircuit, the method comprising: receiving a gate-level description of the subcircuit, wherein the subcircuit is to be simulated using a transistor-level simulator, wherein the subcircuit includes a first cell and a second cell, wherein an output of the first cell is coupled with an input of the second cell, and wherein the second cell needs to be sensitized so that the second cell is in a desired state when the subcircuit is simulated; modifying, by computer, the subcircuit by inserting an analog switch between the first cell and the second cell so that the output of the first cell is coupled with a first input of the analog switch and an output of the analog switch is coupled with the input of the second cell, wherein the analog switch is used to apply a sensitization sequence to the second cell to bring the second cell to the desired state; generating a transistor-level description of the modified subcircuit; and storing the transistor-level description of the subcircuit, thereby enabling the transistor-level simulator to simulate the subcircuit.