Patent ID: 6023439
Filing Date: 2000-02-08
Classification: G01R,G11C,H03K

Abstract:
An apparatus comprising:a programmable logic array formed on a semiconductor substrate, the programmable logic array including:a plurality of logic blocks formed on the semiconductor substrate, each of the logic blocks provided to perform logic functions, each logic block comprising a number of substantially identical programmable logic elements; anda plurality of memory blocks formed on the semiconductor substrate, each of the memory blocks including a plurality of memory cells arranged in a memory array of rows and columns and provided to perform memory functions within the programmable logic array,wherein one of the memory blocks further comprises:read/write control circuitry to configure the one memory block as either read only memory or random access memory, the read/write control circuitry being further configured to control access to the one memory block; andconfiguration control circuitry to variable control the width of the one memory block.