Patent ID: 8296526
Filing Date: 2012-10-23
Classification: G06F

Abstract:
1. An apparatus comprising: a first processor that accesses memory according to a first clock frequency; a second processor that accesses memory according to a second clock frequency; a memory device configurable to selectively operate according to the first clock frequency or the second clock frequency; and a memory controller to enable dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency, in which the memory controller comprises wherein the memory controller is configured such that after access to a particular shared memory bank is granted to the first processor, the second clock domain requestor sends an arbitration request signal to the first clock domain requestor, and the first clock domain requestor sends an arbitration grant signal to the second clock domain requestor after the first clock domain requestor determines that memory access requests from the first processor to the particular shared memory bank have been completed.