Patent ID: 6466590
Filing Date: 2002-10-15
Classification: H04L

Abstract:
A cell group processing device for a common memory switch having a plurality of output ports, which includes at least one individualized output port group, and at least one grouped output port group, wherein each of said plurality of output ports being assigned to a unique group number, said cell group processing device comprising:a multiplexer for multiplexing cells received through a plurality of input ports; a header converter means for sequentially receiving headers extracted from the multiplexed cells, determining whether the cells are valid, and for generating a valid verified signal and a group signal for a valid cell; an idle address generator means for sequentially assigning idle addresses at which cells are stored in response to said valid verified signal; a processor for providing an initial grouping information and an initial address buffer select information when a switch module is initialized; a group information memory means including a first table for storing said initial grouping information, said group information memory means determining grouping information corresponding to a group signal stored in said first table, an address buffer select memory means including a second table for storing said initial address buffer select information, said address buffer select memory means replacing the initial address buffer select information with a next address buffer select information upon reception of the next address buffer select information, and determining address buffer select information corresponding to a group signal stored in said second table; an address buffer select information generator means for receiving grouping information and the address buffer select information, for determining the next address buffer select information, and for outputting the next address buffer select information to said address buffer select memory means; a plurality of address buffers enabled by said address buffer select information, for storing idle addresses assigned by the idle address generator; and, a common memory for storing the cells received from the multiplexer at the idle addresses.