Patent ID: 6414351
Filing Date: 2002-07-02
Classification: H01L

Abstract:
An information handling system comprising:a processor; an input/output subsystem coupled to the processor; and a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including: a first set of one or more transistors each having a gate dielectric of a first thickness; a second set of one or more transistors each having a gate dielectric layer of a second thickness thinner than the first thickness; a floating-gate poly layer over the dielectric layer of the second set of one or more transistors; an inter-poly nitride layer over the floating-gate poly layer; a control-gate poly layer over the inter-poly nitride layer; a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end; a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench; a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench; a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and a nitride layer covering the source end from the inter-poly nitride layer to the substrate.