Patent ID: 8943444
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. A method comprising: generating an aggregate reliability model using a manufacturing line distribution, wherein the aggregate reliability model is generated using reliability failure mechanisms; selecting a line center within a process window of the aggregate reliability model; assigning a percentage of the manufacturing line distribution to each performance process window bin within the process window; calculating a product fail rate for each of the performance process window bins, wherein the calculating the product fail rate comprises setting different fail rates for each of the reliability failure mechanisms as a function of the performance process window for each performance process window bin; calculating a composite fail rate for the manufacturing line distribution based on the percentage of the manufacturing line distribution assigned to each performance process window bin and the product fail rate calculated for each of the performance process window bins; calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution; calculating a product reliability fail rate for a semiconductor product manufactured at the selected line center such that reliability for the semiconductor product is assessed for the selected line center, wherein the product reliability fail rate is calculated based on the composite fail rate for the manufacturing line distribution; and optimizing the line center to minimize the product fail rate for each of the performance process window bins, wherein the optimizing the line center comprises: wherein at least the step of generating the aggregate reliability model is performed using a processor.