Patent ID: 8558575
Filing Date: 2013-10-15
Classification: H03K,H03L

Abstract:
1. A system for generating an output clock used for N.5 modulus division, the system comprising: an edge-slip circuit having an input to accept a modulus count, an input to accept a divisor select signal, an input to accept a clock signal having a frequency greater than a modulus count frequency, an input to accept an output clock signal, and an output to supply a clock slip signal (NE); an exclusive-or (XOR) having an input to accept a buffered clock signal (NF), an input to accept the clock slip signal (NE), and an output to supply the output clock signal as follows: the output clock signal having a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels; and, the output clock signal frequency equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.