Patent ID: 8415734
Filing Date: 2013-04-09
Classification: H01L

Abstract:
1. A memory device, comprising: a substrate; a plurality of memory cells, each memory cell, of the plurality of memory cells, including: a plurality of source regions formed in the substrate, each source region, of the plurality of source regions, being formed adjacent to a first side of each memory cell of the plurality of memory cells; a plurality of drain regions formed in the substrate, each drain region, of the plurality of drain regions, being formed adjacent to a second side, of each of the plurality of memory cells, that is opposite the first side; a protection layer formed on: a top surface of each of the plurality of source regions, a top surface of each of the plurality of drain regions, the first dielectric layer of each of the plurality of memory cells, the charge storage layer of each of the plurality of memory cells, the second dielectric layer of each of the plurality of memory cells, and the control gate layer of each of the plurality of memory cells, the protection layer including oxynitride, and a thickness of the protection layer ranging from about 50 Å to about 150 Å; spacers formed: a third dielectric layer formed over each of the plurality of memory cells and the spacers, the third dielectric layer contacting: