Patent ID: 6927133
Filing Date: 2005-08-09
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: forming a two layer structure comprising a gate insulation film and a gate electrode on a partial area of a surface of a semiconductor substrate; forming a lamination film on surfaces of the semiconductor substrate, gate insulating film and gate electrode conformable to the surfaces, the lamination film having a structure of at least three layers, each of the three layers being made of insulating material, and a middle layer being made of material easier to trap carriers than other two layers; forming a conductive side wall spacer on a surface of the lamination film in areas along a side wall of the gate electrode; etching the lamination film at least to a bottom of the middle layer in an area not covered with the side wall spacers; implanting first impurities into a surface layer of the semiconductor substrate by using the gate electrode and the side wall spacer as a mask; forming a first insulating film by locally oxidizing the surface of the semiconductor substrate not covered with the gate electrode and the side wall spacer; removing an insulating film formed on an upper surface of the gate electrode and on a surface of the side wall spacer; and forming a connection member electrically connecting the upper surface of the gate electrode and the surface of the side wall spacer.