Patent ID: 6617085
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A method of forming an integrated circuit having first gate lengths in a first subcircuit thereof and second gate lengths less than said first gate lengths in a second subcircuit thereof comprising the steps of:preparing a substrate; forming a gate stack layer over said substrate and a composite hardmask layer over said gate stack layer, said composite hardmask layer comprising a first hardmask layer and an etch control layer over said hardmask layer; patterning a layer of resist above said gate stack layer with a pattern of a gate layer of said integrated circuit having a first gate length; etching said composite hardmask layer to transfer said pattern to said hardmask layer; blocking said first subcircuit with a blocking mask, leaving a set of composite hardmask lines in said second subcircuit; etching said composite hardmask lines with a wet etch that attacks said first hardmask layer in preference to said etch control layer, whereby said set of hardmask lines have said second gate length less than said first gate length; etching said gate stack using both said first and second gate lengths of hardmask; and completing transistors with gates of said first and second gate lengths and connecting said transistors to form said integrated circuit.