Patent ID: 7194672
Filing Date: 2007-03-20
Classification: H03M

Abstract:
1. A cyclic redundancy check (CRC) verification apparatus having constant delay, comprising: a data buffer which stores an input data frame; a control information buffer which stores control information on the data frame; a CRC generation unit which performs CRC verification of the data frame; an input control unit which receives an input control signal, generates a CRC enable signal, sends the CRC enable signal to the CRC generation unit, generates information on a write address which increases sequentially irrespective of the input of the data frame, sends the write address information to the data buffer and the control information buffer, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receives the CRC verification result from the CRC generation unit and stores the CRC verification result in the address in which the start part of the data frame is stored, and provides a read address synchronization signal that makes a read address follows with a predetermined offset after the write address; and an output control unit which receives the read address synchronization signal, generates the read address which increases sequentially, sends the read address to the data buffer and the control information buffer, reads data stored in the data buffer, and outputs a different output control signal together with the data according to the CRC result, wherein the CRC verification apparatus receives input frames at a constant rate irrespective of a received data frame while CRC verification is performed.