Patent ID: 8866263
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. An integrated circuit, comprising an ESD device including: a semiconductor substrate including an isolated bipolar transistor region; an epitaxial layer of semiconductor material having a given conductivity type formed over the substrate in the isolated region; a buried collector region of the given conductivity type formed in the isolated region in one or both of the epitaxial layer and substrate; a connector region of the given conductivity type formed in the epitaxial layer and extending between a surface of the epitaxial layer and the buried collector region; a collector region of the given conductivity type formed at the surface in the connector region; a base well region of opposite conductivity type formed in the epitaxial layer adjacent the surface at a location different from the location of the collector region; a base region of the opposite conductivity type formed at the surface in the base well region; an emitter region of the given conductivity type formed at the surface in the base well region at a location spaced from the location of the base region; and contacts respectively formed to provide electrical contact to the collector region, the base region and the emitter region; wherein the contacts formed to provide electrical contact to the emitter region comprise a plurality of via clusters to a single diffused region of the emitter region, wherein the via clusters are separated from each other and each of the via clusters provides a multi-dimensional array of vias; and wherein the contacts formed to provide the electrical contact to the emitter region further comprise metal silicide island areas formed in spaced positions over the emitter region offset from edges of the emitter region; and each of said via clusters providing electrical contact to a respective different one of the metal silicide island areas.