Patent ID: 6815328
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method for manufacturing an integrated semiconductor device, having a plurality of connection levels, comprising:forming a first conductive region above a substrate of semiconductor material; forming a first insulating region of dielectric material above the first conductive region; forming a first through region of electrically conductive material inside the first insulating region, and in direct electrical contact with the first conductive region; forming a second conductive region above the first insulating region, in a position not aligned and not in contact with the first through region; forming a second insulating region of dielectric material, covering the second conductive region; forming, inside the second insulating region, a second through region of electrically conductive material, extending as far as the first through region, aligned and in direct electrical contact with the first through region; and forming, above the second insulating region, a third conductive region aligned and in direct electrical contact with the second through region, wherein the first conductive region is of metal material, a third insulating region extends above the substrate, and the first conductive region extends above the third insulating region.