Patent ID: 7903576
Filing Date: 2011-03-08
Classification: H04L

Abstract:
1. A network system comprising: a bus, a set of network ports, said set of network ports including a set of input network ports for receiving data traffic and a set of output network ports for outputting said data traffic, said set of input network ports including at least a first port; logic arrangement for analyzing said data traffic and for displaying said statistical data pertaining to said data traffic, said logic arrangement including at least a first counter and a second counter, said first counter and said second counter being associated with said first port, said logic arrangement being configured to increment said first counter for each occurrence of a valid data packet at said first port, said logic arrangement being further configured to increment said second counter for each byte of data received at said first port; wherein said logic arrangement includes a field-programmable field array (FPGA), said FPGA is configured to perform analysis of said RX_DV signal and said RX_CLK signal to determine a utilization rate of a network device; wherein said FPGA increases said first counter by one when said RX_DV rising edge is received, said RX_DV rising edge indicating a first valid data packet is being received by said first port; wherein said FPGA increases said second counter when at least said RX_CLK falling edge is received wherein said bus is a reduced gigabit media independent interface (RGMII), said bus being configured to direct a copy of said data traffic to a set of monitoring devices, said data traffic including a plurality of control signals; wherein at least a portion of said plurality of control signals includes an RX_DV signal, said RX_DV signal including an RX_DV rising edge and an RX_DV falling edge; and a visual display arrangement, said visual display arrangement being configured to display statistical data pertaining to said data traffic.