Patent ID: 7696050
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming an N-channel type MISFET and a P-channel type MISFET on a semiconductor substrate, said N-channel type MISFET comprising a laminated structure of a first gate insulation film and a first gate electrode, a first sidewall at a side surface of said first gate electrode of the N-channel type MISFET, first and second lightly doped drain (LDD) regions sandwiching a region of said semiconductor substrate which is under said first gate insulation film of the N-channel type MISFET, said P-channel type MISFET comprising a laminated structure of a second gate insulation film and a second gate electrode, a second sidewall at a side surface of said second gate electrode of the P-channel type MISFET, third and fourth LDD regions sandwiching a region of said semiconductor substrate which is under said second gate insulation film of the P-channel type MISFET; (b) after step (a), forming a P-type source region and a P-type drain region in said P-channel type MISFET; (c) after step (a), forming an N-type source region and an N-type drain region in said N-channel type MISFET; (d) after steps (b) and (c), forming a mask layer for selectively covering said P-channel type MISFET without covering said N-channel type MISFET; (e) after step (d), implanting ions into said N-type source region and said N-type drain region of said N-channel type MISFET with said P-channel type MISFET being covered by said mask layer; and (f) after step (e), carrying out silicidation of said gate electrode of the N-channel type MISFET, said N-type source region and said N-type drain region implanted with said ions in said N-channel type MISFET, said second gate electrode of the P-channel type MISFET and said P-type source region and said P-type drain region in said P-channel type MISFET.