Patent ID: 6507534
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A column decoder circuit for page reading of a semiconductor memory, comprising:a first level decoder stage having an input connected to an address bus and an output connected to a first level bus; a second level decoder stage having at input connected to said address bus and connected an output connected to a second level bus; and a plurality of bit selection stages, each including a plurality of selection branches and a multiplexer, said selection branches being connected to respective inputs of said multiplexer and having a plurality of first level selector stages and a second level selector stage, each of said first level selector stages being connected to said first level bus, to respective bit lines, and to a respective second level selector stage, each second level selector stage having a first addressing circuit for addressing a first group of bit lines; a second addressing circuit for addressing a second group of bit lines, and a selection circuit for selecting one of said first and second groups of bit lines.