Patent ID: 6790726
Filing Date: 2004-09-14
Classification: H01L,Y10S

Abstract:
A method for producing an integrated ferroelectric or DRAM semiconductor memory configuration on a wafer substrate, which comprises:forming memory cells having a selection transistor and two storage capacitors addressed by the selection transistor per memory cell and respectively forming the two storage capacitors for each memory cell from front and rear sides of the wafer substrate by: A) preparing a substrate wafer and forming electrode regions of the selection transistor as a CMOS transistor from the front side of the wafer; B) etching a recessed region in the rear side of the wafer; C) forming a first electrically conductive plug within the recessed region to contact the first plug with an electrode region of the selection transistor formed in step A; D) forming a first storage capacitor in the recessed region from the rear side of the wafer to electrically conductively connect an electrode plate of the first storage capacitor, which electrode plate faces the electrode region of the selection transistor, to the electrode region of the selection transistor through the first plug formed in step C; E) forming a second electrically conductive plug from the front side of the wafer to contact the second plug to the electrode region of the selection transistor contacted with the electrode plate of the first storage capacitor, and F) forming a second storage capacitor from the front side of the wafer to electrically conductively connect an electrode plate of the second storage capacitor, which electrode plate faces the electrode region of the selection transistor, to the electrode region of the selection transistor through the second plug formed in step E.