Patent ID: 8516419
Filing Date: 2013-08-20
Classification: G06F

Abstract:
1. A device configured to verify equivalence between circuit description and assertion description, the device comprising: an assertion based verification unit configured to perform assertion based verification of the circuit description on the basis of the assertion description, and generate pass information or failure information, the pass information being generated when operation of a signal described in the assertion description in which a preliminary condition is satisfied is observed in the circuit description, the failure information being generated when the operation of the signal is not observed in the circuit description; a logic generating unit configured to extract a signal corresponding to the failure information from the assertion description and generate an input/output logic of the circuit description from the extracted signal; a signal restriction generating unit configured to generate a signal restriction on the basis of the input/output logic; an evaluating unit configured to evaluate validity of the signal restriction; an assertion description modifying unit configured to modify the assertion description when the validity indicates invalid; and an outputting unit configured to output the signal restriction when the validity indicates valid and output the modified assertion description when the validity indicates invalid, wherein the outputting unit outputs failure information comprising a waveform selected from a circuit transition state when the signal restriction cannot be generated and the assertion description cannot be modified.