Patent ID: 6610567
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A process of fabricating a DRAM having a guard ring, comprising the steps of:(a) providing a semiconductor substrate having a memory array area and a guard ring area; (b) selectively etching said semiconductor substrate to form a first trench on said memory array area and a second trench on said guard ring area respectively, wherein the dimension of said second trench is smaller than that of said first trench; (c) respectively forming a first thermal oxide layer containing dopants and a second thermal oxide layer containing dopants on the sidewalls of said first trench and said second trench; (d) partially removing said first and said second thermal oxide layers so that the distance between the top portion of said first trench and the remaining first thermal oxide layer is larger than that between the top portion of said second trench and the remaining second thermal oxide layer; (e) performing a thermal treatment to diffuse said dopants of said first and said second thermal oxide layers into said semiconductor substrate to form a first doped strap and a second doped strap respectively; (f) respectively forming a first doped plate and a second doped plate on the upper surfaces of said semiconductor substrate around said first trench and said second trench so that said first doped strap is separated from said first doped plate by a predetermined distance, and said second doped strap is connected to said second doped plate.