Patent ID: 8927397
Filing Date: 2015-01-06
Classification: B82Y,H01L,Y10S

Abstract:
1. A method of fabricating an electronic device, comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX); patterning at least one first set of nanowires and first set pads in the SOI layer and at least one second set of nanowires and second set of pads in the SOI layer, wherein the first set of pads are attached at opposite ends of the first set of nanowires in a ladder-like configuration and wherein the second set of pads are attached at opposite ends of the second set of nanowires in a ladder-like configuration; selectively forming a conformal gate dielectric layer surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device; forming a first metal gate stack on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration; and forming a second metal gate stack surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.