Patent ID: 6801144
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array including plural memory cells; an input/output circuit inputting plural bits of serial data from outside and outputting the plural bits of serial data to outside; a register section comprising a first register and a second register, the first register receiving the plural bits of serial data from the input/output circuit and converting the plural bits of serial data into parallel data, the second register receiving plural bits of parallel data from the plural memory cells and converting the plural bits of parallel data into serial data; and a signal generating circuit generating plural first control signals and plural second control signals, the plural first control signals supplying a conversion timing for each bit when the plural bits of serial data are converted into the parallel data, the plural second control signals supplying a conversion timing for each bit when the plural bits of parallel data are converted into the serial data, the signal generating circuit controlling a timing of one of rise and fall of the plural first control signals and sets which of the plural memory cells should store a value for each bit, of the plural bits of serial data, and controlling a timing of one of rise and fall of the plural second control signals and sets which number of value of the serial data should be the value for each bit, of the plural bits of parallel data read from the plural memory cells.