Patent ID: 7086030
Filing Date: 2006-08-01
Classification: G06F

Abstract:
1. A computer-implemented method for preparing a design in a high-level modeling system, comprising: generating hardware description language (HDL) code for one or more of a plurality of high-level subsystems in a high-level design tagged by a user for HDL code generation; reusing previously generated HDL code instead of generating new HDL code for each high-level subsystem tagged by the user for HDL code reuse; and for each high-level subsystem for which HDL code is generated, displaying for the user a first block, a second block, and a simulation-multiplexer block having input ports coupled to output ports of the first and second blocks, wherein the first block represents a high-level subsystem, the second block represents HDL code generated from the high-level subsystem, and the simulation multiplexer block has a user-configurable attribute that specifies whether the previously generated HDL code is to be reused.