Patent ID: 6414888
Filing Date: 2002-07-02
Classification: G11C

Abstract:
A semiconductor storage device comprising:a cell array having a plurality of memory cells that are arranged in matrix form; a plurality of sub-word lines to serve as signal lines for selection in each row of said cell array; a plurality of main word lines to serve as signal lines for collective selection of a plurality of rows of said cell array via plural ones of said sub-word lines; a row decoder for generating a row selection signal for said main word lines and a row selection signal for said sub-word lines by decoding an address signal that is input externally; mutual switching means for switching among operation modes that include an ordinary operation mode, a waiting mode, and a burn-in mode; and line-to-line burn-in means of said main word lines for being capable to apply a different voltage respectively as a burn-in stress voltage between adjacent said main word lines in the burn-in mode.