Patent ID: 7613024
Filing Date: 2009-11-03
Classification: G11C

Abstract:
1. A memory array arranged in rows and columns, each of the columns of the memory array comprising: a sense amplifier for the respective column of memory cells operable to sense a voltage difference applied between first and second inputs; first and second global digit lines coupled to the first and second inputs of the sense amplifier, respectively, for the respective column of memory cells; a first plurality of local digit lines each of which is selectively coupled to a first plurality of memory cells in the same column of the memory array; a second plurality of local digit lines each of which is coupled to a second plurality of memory cells in the memory array that are different from the memory cells in the first plurality, the plurality of memory cells to which the digit lines in the second plurality are coupled being in the same column as the plurality of memory cells to which the digit lines in the first plurality are coupled; a third plurality of local digit lines each of which is coupled to a third plurality of memory cells in the memory array that are different from the memory cells in the first and second pluralities, the plurality of memory cells to which the digit lines in the third plurality are coupled being in the same column as the plurality of memory cells to which the digit lines in the first and second pluralities are coupled; a fourth plurality of local digit lines each of which is coupled to a fourth plurality of memory cells in the memory array that are different from the memory cells in the first, second and third pluralities, the plurality of memory cells to which the digit lines in the fourth plurality are coupled being in the same column as the plurality of memory cells to which the digit lines in the first, second and third pluralities are coupled; and respectively coupling circuits selectively coupling each of the local digit lines in the first and third pluralities of memory cells to the first global digit lines and each of the local digit lines in the second and fourth pluralities of memory cells to the second global digit line, each of the coupling circuits including a first transistor having its gate coupled to the local digit line, and its source and drain respectively coupled between a specific voltage and the global digit line, each of the coupling circuits further comprising a second transistor having its gate coupled to receive a global word line voltage and its source and drain respectively coupled between the local digit line and the global digit line.