Patent ID: 8094501
Filing Date: 2012-01-10
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first semiconductor layer provided in a surface area of a semiconductor substrate; a first memory cell array formed on the first semiconductor layer and having a plurality of first memory cells including a charge accumulation layer and a control gate; a second semiconductor layer provided in a surface area of the semiconductor substrate and electrically separated from the first semiconductor layer; a second memory cell array formed on the second semiconductor layer and having a plurality of second memory cells including a charge accumulation layer and a control gate; and a driver circuit which independently controls potentials of the first semiconductor layer and the second semiconductor layer, the driver circuit applying erase voltages to the first and second semiconductor layers during an erase operation, wherein the erase voltages for the first and second semiconductor layers are controlled by separate control signals independently, and are applied to the first and second semiconductor layers.