Patent ID: 7457186
Filing Date: 2008-11-25
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: memory cells including floating bodies in an electrically floating state and storing data depending on the number of majority carriers within the floating bodies; a memory cell array including the memory cells disposed two dimensionally; word lines connected to the memory cell arrayed in rows of the memory cell array; bit lines connected to the memory cell arrayed in columns of the memory cell array; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines which is read out from the counter cell array, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation for at least one polarity data when the number of times of activating one of the word lines has reached a predetermined value in a data read cycle in which data is read out from the sense amplifier to an outside of the memory cell array or in a data write cycle in which the sense amplifier receives data from the outside of the memory cell array and writes the data to the memory cell, the sense amplifier executing the refresh operation during the same data read cycle in which the number of times of activating of the one of the word lines has reached the predetermined value or during the same data write cycle in which the number of times of activating of the one of the word lines has reached the predetermined value, the refresh operation being an operation in which data is readout and the data readout is written back into the memory cell that originally stored the data.