Patent ID: 6025752
Filing Date: 2000-02-15
Classification: H03F

Abstract:
An inverting amplifying circuit comprising:an inverter circuit having an input and an output, said inverter circuit comprising an odd number of CMOS inverters serially connected;a feedback capacitance connected in parallel with said inverter circuit;an input capacitance connected to said input of said inverter circuit for inputting a voltage to said inverter circuit;a first refresh switch connected in parallel with said feedback capacitance for short-circuiting said feedback capacitance when in a refresh mode;a second refresh switch connected to said input capacitance for inputting a refresh voltage equal to a threshold voltage of said inverter circuit to said input of said inverter circuit when in the refresh mode; anda first sleep switch which connects a ground voltage or to a saturation voltage directly to a terminal of one of said CMOS inverters of said inverter circuit when n a sleep mode.