Patent ID: 6763367
Filing Date: 2004-07-13
Classification: G06F

Abstract:
A reduction circuit for compressing a carry-save partial product matrix having n rows, a constant value row, and a stored carry-save accumulated sum, into a carry-save accumulator, said reduction circuit comprising:a compressor array for generating an accumulated carry-save sum, said compressor array includes circuit means for performing an (n+2)-to-2 compression, wherein said circuit means for performing an (n+2)to-2 compression includes two adders, wherein each of said adders includes four levels of logic gates coupled between five inputs and two outputs for combining values received at said five inputs to generate a sum value and a carry value at said two outputs, wherein said four levels of logic gates includes XOR logic gates; and a carry-save adder coupled between said carry-save accumulator and said compressor array for pre-reducing said constant value row and said accumulated carry-save sum into a two-row intermediate carry-save sum.