Patent ID: 6696874
Filing Date: 2004-02-24
Classification: H03K

Abstract:
A single-event upset immune latch circuit, comprising:a first dual-input inverter for receiving a first input to provide a first intermediate output, wherein said first dual-input inverter includes two p-channel transistors and two n-channel transistors connected in series; a second dual-input inverter for receiving a second input to provide a second intermediate output, wherein said second dual-input inverter includes two p-channel transistors and two n-channel transistors connected in series; a first inverter for receiving said first and second intermediate outputs from said first and second dual-input inverters to provide a first output, wherein said first inverter includes a p-channel transistor and an n-channel transistor connected in series; and a second inverter for receiving said first and second intermediate outputs from said first and second dual-input inverters to provide a second output, wherein said second inverter includes a p-channel transistor and an n-channel transistor connected in series.