Patent ID: 8213247
Filing Date: 2012-07-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cell transistors arranged in a matrix and each configured to store data; and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes: a plurality of reference cell transistors employed to successively produce varying amounts of currents; a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents; and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal, wherein one of the varying amounts of currents is a maximum tolerable current amount that is allowed to flow through any one of the memory cell transistors.