Patent ID: 6590253
Filing Date: 2003-07-08
Classification: H01L

Abstract:
In a process of fabricating a memory cell having stack and select transistors, the steps of: forming floating gates for the stack transistors from a poly-1 layer on a substrate, forming a shallow diffusion region in the substrate beneath one side of each of the floating gates, forming a dielectric film over the floating gates, forming a gate oxide on the substrate for the select transistors, forming control gates and select gates of a poly-2 material on the dielectric film and the gate oxide, with the control gates being narrower than the floating gates and centered above the floating gates, forming a deep diffusion region in the substrate beneath each of the other sides of the floating gates, forming oxide spacers around the control gates, floating gates and select gates, and forming source and drain regions in the substrate for the select transistors by LDD implantation.