Patent ID: 8164496
Filing Date: 2012-04-24
Classification: H03F

Abstract:
1. A multi-stage analog-to-digital converter that compensates for mismatches in signals during normal operation, comprising: a first analog-to-digital converter that converts an analog input signal into a corresponding first stage digital signal; an analog delay unit that delays the analog input signal to generate a delayed analog input signal; a first mismatch equalizer that compensates mismatches between the delayed analog input signal and a first stage analog signal during normal operation of the multi-stage analog-to-digital converter in response to first matching parameters and that outputs a first stage matched digital signal; a first digital-to-analog converter that converts the first stage matched digital signal to the first stage analog signal; a subtractor that subtracts the delayed analog input signal from the first stage analog signal to generate a residual analog signal; a second analog-to-digital converter that converts the residual analog signal into a corresponding second stage digital signal; a second mismatch equalizer that compensates mismatches between the first stage digital signal and the second stage digital signal output by the second analog-to-digital converter during normal operation of the multi-stage analog-to-digital converter in response to second matching parameters and that outputs a second stage matched digital signal; and a mismatch estimator that monitors the second stage digital signal during normal operation of the multi-stage analog-to-digital converter and that generates the first matching parameters indicating an amount of mismatch between the delayed analog input signal and the first stage analog signal and that generates the second matching parameters indicating an amount of mismatch between the first stage digital signal and the second stage digital signal, the mismatch estimator updating the first and second matching parameters during normal operation of the multi-stage analog-to-digital converter, wherein the mismatch estimator continually monitors the second stage digital signal and continually updates the first matching parameters and the second matching parameters during normal operation of the multi-stage analog-to-digital converter, and wherein the first and second mismatch equalizers adaptively compensate mismatches between the analog input signal and the first stage analog signal, and between the first stage digital signal and the second stage digital signal, respectively, during normal operation of the multi-stage analog-to-digital converter.