Patent ID: 8116152
Filing Date: 2012-02-14
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell including an anti-fuse storage element and a selection transistor, a first terminal of the selection transistor being connected to one end of the anti-fuse storage element, a control terminal of the selection transistor being connected to a word line, and a second terminal of the selection transistor being connected to a bit line; a precharge control circuit to receive an input of a write enable signal and to generate a bit line control signal, a word line control signal, a write permission signal and a first control signal in response to the write enable signal; a power supply circuit to receive an input of the write permission signal and to supply a write voltage to the other end of the anti-fuse element in response to the write permission signal; a bit line potential control unit to receive inputs of an address control signal, the bit line control signal and the first control signal, and to control the potential of the bit line in response to the address control signal, the bit line control signal and the first control signal; and a word line potential control unit to receive inputs of the address control signal, the word line control signal and the first control signal, and to control the potential of the word line in response to the address control signal, the word line control signal and the first control signal, wherein before a write operation of the anti-fuse storage element is executed, the potential of the one end of the anti-fuse storage element is raised, so that the anti-fuse storage element is set to be in a precharged state.