Patent ID: 6768433
Filing Date: 2004-07-27
Classification: H03M

Abstract:
A biphase-mark decoding system, comprising:a programmable clock; a data buffer; a receiver module coupled to the data buffer for, receiving an external biphase-mark input stream, recovering timing information from the input stream, and decoding the input stream to generate decoded data and storing the decoded data in the data buffer; an audio out module coupled to the buffer and the programmable clock for reading the decoded data from the data buffer at a rate determined by the programmable clock; and a processor coupled to the receiver module for executing a software-based frequency locked loop that uses the timing information from the receiver module to calculate a sampling frequency of the input stream, and then adjusts a frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.