Patent ID: 7640523
Filing Date: 2009-12-29
Classification: G06F

Abstract:
1. A method for forming a package for a semiconductor die, comprising: determining an upper limit of total number of vias available for a power distribution network for the package; determining an upper limit of loop inductance for the semiconductor die, wherein the upper limit of loop inductance for the semiconductor die creates a threshold voltage (ΔV) low enough that the ΔV does not affect the operation of devices coupled to the power distribution network on the semiconductor die; determining at least one via layout pattern, the loop inductance of the at least one via layout pattern not exceeding the upper limit of loop inductance, an upper limit of total number of vias of the at least one via layout pattern not exceeding the upper limit of total number of vias available for the power distribution network for the package, the at least one via layout pattern defining a placement relationship between vias used for power and vias used for ground; and packaging the semiconductor die wherein the at least one via layout pattern is utilized for the package.