Patent ID: 6838344
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A twin MONOS memory embedded in a CMOS device comprising: memory area and a CMOS area separated by isolation regions in a substrate; a deep N-well in said memory area and in said CMOS area underlying a P-well wherein said deep N-well allows a negative voltage to be applied to said P-well; polysilicon memory gates in said memory area having silicon control gates on sidewalls of said memory gates having an oxide-nitride-oxide (ONO) layer therebetween wherein said ONO layer also underlies said control gates and overlies a control gate channel wherein said nitride portion of said ONO layer underlying said control gates provides storage in said memory area, wherein a channel length of said control gates is less than 50 nm, and wherein said control gates have a height of at least 50 nm less than a height of said memory gates; polysilicon CMOS gates in said CMOS area; a polysilicon control gate contact pad lying between two of said memory gates overlying said substrate and on sidewalls of said two memory gates; source and drain regions in said substrate adjacent to said gates in said CMOS area and in said memory area; and metal contacts through a dielectric layer overlying said gates to said source and drain regions forming word line contacts and control gate contacts to complete said Twin MONOS memory device.