Patent ID: 6088269
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A nonvolatile floating gate device comprising:a substrate of a first conductivity type having a first surface, a first substrate region and a second substrate region, each said substrate region being disposed in said first surface and being of a second conductivity type opposite to said first conductivity type;a first electrically insulated conductive layer spaced from said first surface having a first portion capacitively coupled to said second substrate region and a second portion overlaying a first predetermined channel area of said first surface disposed between said first substrate region and said second substrate region;a second electrically insulated conductive layer having a first portion spaced from said first surface and disposed generally intermediate said first substrate region and said second portion of said first layer and a second portion overlaying said first layer, said first portion of said second layer overlaying a second predetermined channel area of said first surface, said second layer being capacitively coupled to said first layer, wherein the capacitive coupling between said first layer and said second substrate region is greater than the capacitive coupling between said first and said second layers; andprogramming means for selectively tunneling electrons onto said first layer from said substrate, said programming means comprising a first application means for selectively applying a first potential to said first substrate region, a second application means for selectively applying a second potential to said second substrate region, and a third application means for selectively applying a program control potential to said second layer, said program control potential being selected to invert the conductivity type of said second channel area to provide a conduction path between said first substrate region and said first channel area, said first and second application means acting to create a potential difference between said first and second substrate regions, said capacitive coupling between said first portion of said first layer and said second substrate region coupling a substantial amount of said second potential to said first layer, such that electrons are caused to tunnel from said substrate to said first layer, said programming means forming a primary inversion region in said second channel area adjacent to said first substrate region, a primary pinchoff region in said second channel ares and adjacent to said primary inversion region, and a secondary inversion region in said first channel area and adjacent to said primary pinchoff region, said primary pinchoff region being formed such that hot electrons are generated therein and caused to tunnel from said substrate to said first layer.