Patent ID: 6584607
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A method of performing timing-driven layout of a circuit, comprising the steps of:(a) generating an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks; (b) calculating wiring capacitance values of the respective blocks using the initial layout result; (c) calculating fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b); each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value; (d) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result; (e) defining the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and (f) changing circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.