Patent ID: 6304837
Filing Date: 2001-10-16
Classification: G01R

Abstract:
An automated test vector verification method, comprising:receiving an AVF test file of an integrated circuit design;receiving a DUT test file of the integrated circuit design;executing the AVF test file and the DUT test file to produce an input vector, an environment file, and an expected output vector;providing the input vector to a standalone chip on a model test station;executing the environment file that causes the input vector to be processed through the standalone chip on the model test station, the executing configured to produce an output vector from the model test station;comparing the output vector from the model test station with the expected output vector;modifying a test file data that is used to generate the AVF test file data and the DUT test file data;generating a new AVF test file data and a new DUT test file data;running the automated test vector verification method using the new AVF test file data and the new DUT test file data; anddetermining whether the comparing produces a match that indicates that the AVF test file data is free of errors.