Patent ID: 8319288
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A semiconductor device comprising a CMOS inverter coupled circuit in which CMOS inverters are connected in at least two or more stages, wherein: said CMOS inverters are composed of vertical MOS transistors in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are provided in a vertical hierarchical structure, said columnar semiconductor layer is provided between said source diffusion layer and drain diffusion layer, and a gate electrode is formed on the sidewall of said columnar semiconductor layer; said CMOS inverter coupled circuit includes a first CMOS inverter in the first stage that is composed of multiple vertical MOS transistors aligned in the first column on a substrate and a second CMOS inverter in the second stage that is composed of multiple vertical MOS transistors aligned in the second column on said substrate; said multiple vertical MOS transistors aligned in the first column are composed of one or multiple first NMOS vertical transistors formed on a first N+ source diffusion layer and one or multiple first PMOS vertical transistors formed on a first P+ source diffusion layer; said first N+ source diffusion layer and first P+ source diffusion layer are formed next to each other; a first potential is supplied to said first N+ source diffusion layer and a second potential is supplied to said first P+ source diffusion layer; the gate electrode of said one or multiple first NMOS vertical transistors and the gate electrode of said one or multiple first PMOS vertical transistors are connected and form a first gate wire; a first contact for supplying an input voltage to the first CMOS inverter is formed at an end of said first gate wire; a first N+ drain diffusion layer is formed in the upper part of columnar semiconductor layers composing said one or multiple first NMOS vertical transistors, and a second contact connecting said first N+ drain diffusion layer and a first wiring layer to which the output voltage of said first inverter is output is formed on said first N+ drain diffusion layer; a first P+ drain diffusion layer is formed in the upper part of columnar semiconductor layers composing said one or multiple first PMOS vertical transistors, and a third contact connecting said first P+ drain diffusion layer and the first wiring layer to which the output voltage of said first inverter is output is formed on said first P+ drain diffusion layer; said multiple vertical MOS transistors aligned in the second column are formed by one or multiple second NMOS vertical transistors formed on said first N+ source diffusion layer and one or multiple second PMOS vertical transistors formed on said first P+ source diffusion layer; the gate electrode of said one or multiple second NMOS vertical transistors and the gate electrode of said one or multiple second PMOS vertical transistors are connected and form a second gate wire; a fourth contact for supplying an input voltage to the second CMOS inverter is formed at the other end of said second gate wire; said fourth contact is connected to said first wiring layer; a second N+ drain diffusion layer is formed in the upper part of columnar semiconductor layers composing said one or multiple second NMOS vertical transistors, and a fifth contact connecting said second N+ drain diffusion layer and a second wiring layer to which the output voltage of said second inverter is output is formed on said second N+ drain diffusion layer; a second P+ drain diffusion layer is formed in the upper part of columnar semiconductor layers composing said one or multiple second PMOS vertical transistors, and a sixth contact connecting said second P+ drain diffusion layer and the second wiring layer to which the output voltage of said second inverter is output is formed on said second P+ drain diffusion layer; and said first CMOS inverter and second CMOS inverter are alternately connected.