Patent ID: 7339399
Filing Date: 2008-03-04
Classification: H03M

Abstract:
1. An impedance control system comprising: a target circuit having a controllable impedance; a replica circuit having a structure identical to said target circuit; a first binary counter providing said replica circuit with a first impedance control code indicative of a counter value of said first binary counter, wherein an impedance of said replica circuit is controlled in response to said first impedance control code; a comparator comparing a voltage received from said replica circuit with a reference signal; a second binary counter responsive to an output signal from said comparator for counting a number of times when said output signal is set to a predetermined state; and a control circuit extracting upper multiple bits out of a counter value of said second binary counter, and generating a second impedance control code indicative of said upper multiple bits, wherein said impedance of said target circuit is controlled in response to said second impedance control code.