Patent ID: 7349934
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. An integrated circuit device, comprising: an input for receiving an initial data argument comprising a plurality of bits; circuitry for providing a first shift argument indicating a number of shift positions in a first direction, the first shift argument comprising a plurality of bits; circuitry for providing a second shift argument indicating a number of shift positions in a second direction, the second shift argument comprising a plurality of bits; a plurality of rotate stages, each comprising an input and an output; wherein one rotate stage, in the plurality of rotate stages, is coupled to receive the initial data argument; wherein each rotate stage, in the plurality of rotate stages, other than the one rotate stage, is coupled to receive a data argument from an output of another one of the rotate stages in the plurality of rotate stages; wherein a first rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage in response to a least significant bit in the first shift argument; wherein a second rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the corresponding rotate stage in response to a least significant bit in the second shift argument; wherein a third rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the third rotate stacie in response to a sum of respective second and third bit positions of the first and second shift arguments; and wherein a fourth rotate stage, in the plurality of rotate stages, is operable to rotate the data argument input into the fourth rotate stage in response to a sum of respective fourth and fifth bit positions of the first and second shift arguments.