Patent ID: 7893671
Filing Date: 2011-02-22
Classification: G05F

Abstract:
1. A regulator to provide an output voltage of a constant level at an output node, said regulator comprising: a pass transistor to provide a conductive path between a pair of terminals of said pass transistor, wherein a resistance offered by said conductive path is determined by a control voltage on a third terminal of said pass transistor, said conductive path coupling a first reference potential to said output node; an amplifier to generate said control voltage based on a difference of a reference voltage and a voltage proportionate to said output voltage; a current source to source current to said output node when turned on; a current sink to sink current from said output node when turned on; a control unit to turn on said current source when voltage at said output node is below said constant level and to turn on said current sink when voltage at said output node is above said constant level; a voltage divider circuit coupled between said output node and a second reference potential, and to provide said voltage as a fixed fraction of the strength of said output voltage at a measurement node; wherein said control unit contains a first plurality of transistors comprising: a first transistor with a first current terminal coupled to said second reference potential and a control terminal coupled to a bias voltage; a second transistor with a first current terminal coupled to a second current terminal of said first transistor, and a control terminal coupled to said measurement node; a third transistor with a first current terminal coupled to said second current terminal of said first transistor, and a control terminal coupled to said reference voltage; a fourth transistor with a first current terminal coupled to said first reference potential and a second current terminal couple to a second current terminal of said second transistor and a control terminal coupled to a second bias voltage; a fifth transistor with a first current terminal coupled to said first reference potential and a second current terminal couple to a second current terminal of said third transistor and a control terminal coupled to said second bias voltage; a sixth transistor with a first current terminal coupled to said first reference potential and a control terminal coupled to said second current terminal of said fourth transistor; and a seventh transistor with a first current terminal coupled to said second reference potential and a second current terminal coupled to a second current terminal of said sixth transistor, said second current terminal of said seventh transistor also coupled to a control terminal of said seventh transistor.