Patent ID: 6430655
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A random access memory system, comprising:at least one cache data RAM having a first port by which an index signal can be received and a second port by which data stored at a location that is identified by the received index signal can be output; at least one scratchpad data RAM having a first port by which the index signal can be received and a second port by which data stored at a location that is identified by the received index signal can be output; at least one cache tag RAM having a first port by which the index signal can be received and a second port by which tag data stored at a location that is identified by the received index signal can be output, wherein each of said at least one cache tag RAM is associated with one of said at least one cache data RAM; at least one first determining circuit that is coupled to said second port of a corresponding cache tag RAM and being operative to determine whether an identified address corresponds to an address output by said corresponding cache tag RAM; and at least one second determining circuit being operative to determine whether said identified address corresponds to a value that is produced independently of the index signal, wherein results from said at least one first determining circuit and said at least one second determining circuit are used to determine whether said at least one cache data RAM or said at least one scratchpad data RAM should be accessed.