Patent ID: 7146489
Filing Date: 2006-12-05
Classification: G06F

Abstract:
1. For use in a system involving an Embedded-DRAM processor, a method for intelligent caching comprising the steps of: splitting an architecture into first and second portions, said first portion comprising a set of functional units and a set of architectural registers exercised thereby, said second portion comprising at least one functional unit capable of moving data between a main memory implemented as one or more banks of DRAM without a caching system that employs cache hits and cache misses, and said set of architectural registers; and splitting a single program into first and second concurrently executing portions which each concurrently execute distinct subsets of parallely dispatched instructions from one or more instruction streams, said first portion of said program executed on said first portion of the architecture, said second portion of said program executed on said second portion of said architecture; wherein said second portion of said architecture is operative to prefetch data from said main memory into said architectural registers prior to being processed by said first portion of said architecture, and wherein said second portion of said architecture is operative to move results produced by said first portion of said architecture into main memory after they are produced by said first portion of said architecture; and prior to when said first portion of said architecture executes a conditional branch instruction having a condition, said second portion of said architecture prefetches first and second data sets from memory into said architectural registers, said first data set being needed for use as instruction operands when said condition evaluates to true, said second data set being needed for use as instruction operands when said condition evaluates to false.