Patent ID: 7990760
Filing Date: 2011-08-02
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to said cell array in said bit line direction, wherein said cell array includes first P-well regions and first N-well regions shaped in stripes extending in said bit line direction and arranged alternately in said word line direction, wherein said SRAM cell is formed point-symmetrically in said first P-well region and said first N-well regions located on both sides thereof, said peripheral circuit includes second P-well regions and second N-well regions extending in said bit line direction and arranged alternately in said word line direction, and includes a read circuit arranged adjacent to one side of said cell arrays in said bit line direction and operative to read data from said SRAM cell, and said read circuit is arranged such that the length of a basic circuit pattern thereof in said word line direction is equal to an integer multiple of the length of a circuit pattern of said SRAM cell in said word line direction.