Patent ID: 8209648
Filing Date: 2012-06-26
Classification: G06F

Abstract:
1. A method of evaluating constrained circuit designs, comprising: specifying a plurality of constrained designs, wherein each constrained design includes a circuit design that includes circuit elements and connections between circuit elements, and each constrained design further includes timing constraints for paths along the connections between circuit elements, the timing constraints including one or more timing exceptions including false paths that are not active paths, multi-cycle paths that correspond to multiple clock cycles, maximum delays along paths, or minimum delays along paths; generating a timing graph for each circuit design, wherein each timing graph includes nodes corresponding to circuit elements and edges corresponding to connections between circuit elements; mapping the timing constraints for each circuit design to a timing-graph constraint set for a corresponding timing graph; using a computer to evaluate the constrained designs by comparing the timing-graph constraint sets and determining a presence or absence of one or more paths with a constraint error that corresponds to an inconsistent, conflicting or missing constraint; and providing a timing-constraint report to a user, wherein the timing-constraint report includes values for the presence or absence of one or more paths with a constraint error.