Patent ID: 8987126
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit, comprising: providing a semiconductor substrate having a first trench and a second trench, each of the first and second trenches being defined by sidewall spacers and a silicon material at the semiconductor substrate; depositing a layer of a high-k dielectric material within both the first and second trenches including along and in contact with an entirety of exposed vertical walls of the sidewall spacers; forming a sacrificial material layer within an entirety of only the second trench and not within the first trench and in contact with the high-k dielectric material in the second trench; depositing a layer of a work function shifter material in the first trench over and in contact with the high-k dielectric material to form an overlapping region in the first trench, wherein the workfunction shifter material comprises an oxide of a metallic element, and wherein the entirety of the second trench remains filled by the sacrificial material and thus no work function shifter material is deposited in the second trench; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material so as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric material and work function shifter material in the overlapping region within the first trench, wherein the transformed dielectric material comprises an oxide of two metallic elements in combination; removing an entirety of the sacrificial material from within the second trench so as to re-expose the high-k dielectric material therein; and depositing a layer of a first replacement gate fill material into the first trench and over and in contact with the transformed dielectric material and into the second trench and over and in contact with the high-k dielectric material.