Patent ID: 6642086
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A method of fabricating a thin film transistor (TFT) array substrate, comprising:providing a substrate; depositing a first metallic layer on the substrate; forming a gate electrode and gate line on the substrate by patterning the first metallic layer using a first mask process; forming a first insulation layer over the gate electrode, gate line and substrate; forming an intrinsic semiconductor layer on the first insulation layer; forming an extrinsic semiconductor layer on the intrinsic semiconductor layer; depositing a second metallic layer on the extrinsic semiconductor layer; forming a data line, source and drain electrodes and a first capacitor electrode having an island shape over the gate line by patterning the second metallic layer and extrinsic semiconductor layer by using a second mask process; forming a second insulation layer over the data line, source and drain electrodes and first capacitor electrode; forming a drain contact hole by patterning the second insulation layer using a third mask process, simultaneously, forming a pixel region and gate contact hole by patterning the first and second insulation layers and intrinsic semiconductor layer, simultaneously, exposing the portion of the first capacitor electrode by patterning the second insulation layer; depositing a transparent conductive electrode over a surface formed by the third mask process; and patterning the transparent conductive electrode by using a fourth mask process to form an electrode connecting layer connecting the first capacitor electrode with the gate line, and to form a pixel electrode connected to the drain electrode via the drain contact hole, the pixel electrode having a second capacitor electrode extended from the pixel electrode, the second capacitor electrode overlapping the first capacitor electrode and spaced apart from the electrode connecting layer.