Patent ID: 8125036
Filing Date: 2012-02-28
Classification: H01L,Y10S

Abstract:
1. An integrated circuit comprising: a semiconductor material having a surface, wherein the semiconductor material is subdivided laterally into a central region and an edge region; an arrangement of one or more semiconductor components that is formed in the central region of the semiconductor material; a planar passivation layer that is formed on the surface in the edge region, the passivation layer comprising a planar bottom surface, wherein an entirety of the planar bottom surface is in direct contact with the surface of the semiconductor material; two or more channel stopper zones that are connected via connections and that are formed in the edge region; and an oxide layer that is provided on the surface of the semiconductor material in the edge region, the oxide layer being separate from the passivation layer, wherein the oxide layer is formed above and in contact with the two or more channel stopper zones and is adjacent to the passivation layer with only one of the connections in between regions and directly follows the passivation layer.