Patent ID: 7714363
Filing Date: 2010-05-11
Classification: H01L

Abstract:
1. A semiconductor integrated circuit that drives a display device, wherein an active element is formed in the semiconductor integrated circuit, a plurality of layers are formed in the semiconductor integrated circuit, each layer being formed by arranging a planar first metal wiring layer, formed on a region where the active element is formed, that supplies a first potential supplied from outside to an active element formed in the semiconductor integrated circuit and a planar second metal wiring layer, formed on the region where the active element is formed, that supplies a second potential supplied from outside to the active element and wherein: the planar shape of the semiconductor integrated circuit is a rectangular shape; the first metal wiring layer on the lowermost layer of the plurality of layers is disposed on both sides of the semiconductor integrated circuit in the longitudinal direction thereof and the second metal wiring layer on the lowermost layer is disposed on both sides of the semiconductor integrated circuit in the longitudinal direction thereof and adjoining the first metal wiring layer on the outer side of the first metal wiring layer; the second metal wiring layer on the uppermost layer of the plurality of layers is disposed such that its peripheral edge is positioned, in the longitudinal direction of the semiconductor integrated circuit, at an inner side of the semiconductor integrated circuit than the peripheral edge of the second metal wiring layer on the lowermost layer, the first metal wiring layer on the uppermost layer is disposed on, in the longitudinal direction of the semiconductor integrated circuit, the inner side of the semiconductor integrated circuit than the second wiring layer on the uppermost layer, and a portion or all of the output terminals of the semiconductor integrated circuit are formed on, in the longitudinal direction of the semiconductor integrated circuit, an outer side of the second metal wiring layer on the uppermost layer within a region directly above the region in which the active element is formed.