Patent ID: 8104010
Filing Date: 2012-01-24
Classification: G06F

Abstract:
1. A semiconductor integrated circuit design supporting method, the method using a circuit design supporting system comprising: a memory unit which stores cell information that contains the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file that defines a drive factor of each of the plurality of IO cells; a pad laying out section; a package virtual designing section; an electric characteristics data calculating section; and a noise risk calculating section, the method comprising: tentatively laying out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, with the aid of the pad laying out section; preparing a package drawing based on coordinates of the power supply pads and the input-output pads, with the aid of the package virtual designing section; calculating inductance of the power supply pads, using the package drawing, with the aid of the electric characteristics data calculating section; and calculating noise risk of each of the input-output pads, using the inductance of the power supply pads and the drive factor definition file, with the aid of the noise risk calculating section, wherein: the noise risk calculating section uses an inductance of a first power supply pad, an inductance of a second power supply pad, and a drive factor of each of “n” number (“n” is an integer of 2 or more) of input-output pads laid out between the first and second power supply pads to: calculate a first product by multiplying the drive factor of each of the “n” number of input-output pads with the inductance of the first power supply pad; calculate a first integrated value for each of the “n” number of input-output pads by sequentially adding up the first product, starting from the side of the first power supply pad; calculate a second product by multiplying the drive factor of each of the “n” number of input-output pads with the inductance of the second power supply pad; calculate a second integrated value for each of the “n” number of input-output pads by sequentially adding up the second product, starting from the side of the second power supply pad; and compare the first and second integrated values for each of the “n” number of input-output pads for extraction of a smaller one as the noise risk, wherein the calculations are performed by a computer.