Patent ID: 6743704
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a first gate electrode, having a first impurity diffusion layer of a first conduction type formed in a polycrystalline silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in order, and a second gate electrode having a second impurity diffusion layer of a second conduction type formed in said polycrystalline silicon layer and a high-melting-point metal layer or high-melting-point metal silicide layer, formed in order, and positioned at a distance from said first gate electrode; wherein said method comprises:(a) implanting impurities of the first and the second conduction types respectively into different first and second regions of the polycrystalline silicon layer from above said polycrystalline silicon layer; (b) forming, after implanting impurities in the polycrystalline silicon layer, an impurity thermal diffusion prevention layer which prevents diffusion of said impurities implanted into the polycrystalline silicon layer on said polycrystalline silicon layer; (c) forming said high-melting-point metal layer or high-melting-point metal silicide layer so as to cover said polycrystalline silicon layer extending from said first region to said second region, to form a compound layer comprising said polycrystalline silicon layer with said impurities implanted, said impurity thermal diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer; (d) heat-treating said compound layer, and diffusing said first and second impurities implanted respectively into said first and second regions in said polycrystalline silicon layer, to form said first and second impurity diffusion layers; and, (e) patterning a layered structure comprising said polycrystalline silicon layer in which are formed said first and second impurity diffusion layers, said impurity thermal diffusion prevention layer, and said high-melting-point metal layer or high-melting-point metal silicide layer, to form said first and second gate electrodes.