Patent ID: 6359908
Filing Date: 2002-03-19
Classification: H04J

Abstract:
A frame synchronous circuit comprising:a first and a second shift registers for inputting an SDH (Synchronous Digital Hierarchy) signal alternately in every 1 bit; a first and a second A1-byte detecting logic device for detecting an A1-byte from respective inputs which are inputted thereto by way of two sets of outputs for 1 byte which are shifted with each other by 1 bit, from among respective outputs of said first and said second shift registers; a latched-circuit for latching to output data with 1 byte as a unit from output of said first and said second shift registers while synchronizing with detected output of said first A1-byte detecting logic device; and a switching circuit for switching data input order of said SDH signal inputted to said first and said second shift registers by virtue of detected output of said second A1-byte detecting logic device.