Patent ID: 6470479
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A method of verifying the reliability of a semiconductor integrated circuit using a cell library database, said semiconductor device including a plurality of cells connected with each other by at least one intercellular interconnect line, said cell library database containing inner-cell input/output load capacity information including input load capacity and output load capacity of each of said plurality of cells, and information about a way to calculate a failure rate of an inner-cell interconnect line based on load capacity on an external terminal of each of said plurality of cells,said method comprising the steps of: (a) obtaining load capacity on said external terminal on the basis of said inner-cell input/output load capacity information; and (b) calculating a failure rate of an inner-cell interconnect line in a cell which has said external terminal, on the basis of said load capacity on said external terminal according to said way to calculate a failure rate, said steps (a) and (b) being performed for each of said plurality of cells.