Patent ID: 7915746
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A semiconductor wafer comprising: a substrate; an active area on the substrate, with an integrated circuit in the active area; a dicing area around said active area; a seal ring along a periphery of said active area; a first interconnect disposed closely to an inner periphery of said seal ring; a protective layer covering said active area and said seal ring, and having a groove and a first via therein, the groove at an area between said seal ring and said first interconnect; a protective film on the protective layer and filling the groove in said protective layer, said protective film having a second via therein; and a second interconnect on said protective film and electrically connected to said integrated circuit through the first and second vias, wherein an aspect ratio of the groove in said protective layer is 0.5 or more.