Patent ID: 8675394
Filing Date: 2014-03-18
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: n bit lines, n being a natural number; m memory cells electrically connected to one of the bit lines, m being a natural number; and m+1 word lines, wherein each of the memory cells comprises: wherein the second transistor includes an oxide semiconductor layer, wherein the one of the bit lines is electrically connected to the first drain electrode and the second drain electrode of a (k−1)-th memory cell, wherein a k-th word line is electrically connected to the second gate electrode of a k-th memory cell and is electrically connected to the first source electrode and one electrode of the capacitor of the (k−1)-th memory cell, k being a natural number of greater than or equal to 2 and less than or equal to m+1, and wherein the first gate electrode of the (k−1)-th memory cell, the second source electrode of the (k−1)-th memory cell, and the other electrode of the capacitor of the (k−1)-th memory cell are electrically connected to one other.