Patent ID: 9203415
Filing Date: 2015-12-01
Classification: G06F,H03K,H03L,H04L

Abstract:
1. A signal synchronization circuit comprising: at least one synchronizer comprising a number N of series connected clock delay elements, N being equal to or greater than unity the synchronizer being adapted to adapt an asynchronous signal originating from a first clock domain, to a second clock domain; a clock signal generator arranged for generating a modulated clock signal adapted to clock the N clocked delay elements of the at least one synchronizer, wherein the clock generator is arranged to receive a clock signal and at least one operating value and to generate the modulated clock signal from said clock signal modified based on said operating value; and a clock gate with an input and an output, said input being arranged to receive the clock signal and said output being adapted to output the modulated clock signal from the clock signal generator, the clock gate being controlled by a control signal generated by the clock signal generator based on said operating value, wherein the operating value is tied to a desired increase in a synchronization time shift introduced by the synchronizer.