Patent ID: 6552951
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A dual-port memory cell, comprising:(a) a first selection transistor and a second selection transistor, (a1) whose load paths are arranged in series and between a first and a second data line; and (a2) whose control terminals are respectively connected to a first and a second word line, it being possible for the selection transistors to be driven independently of one another via their control terminals; and (b) a capacitive element, (b1) which has a first output terminal, which is connected to a load path terminal of the first selection transistor and a second output terminal, which is different from the first output terminal and which is connected to a load path terminal of the second selection transistor; (b2) approximately the same potential being present at the output terminals, wherein the capacitive element is designed as a memory transistor, whose load path is arranged between the series-connected load paths of the selection transistors and which can be controlled via a control terminal, to which a supply potential is applied, a voltage across the load path of the memory transistor corresponding to a turn-on voltage thereof, the first output terminal and the second output terminal of the capacitive element being directly connected to a respective load path terminal of the first selection transistor and the second selection transistor.