Patent ID: 6397312
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A memory subsystem comprising:a controller including an output circuit for outputting a read command, and a read data input circuit for retrieving read data; a plurality of memory devices each including a command input circuit for retrieving said read command, and a read data output circuit for outputting said read data which is read from said memory device in response to said read command; a clock or data strobe line connected between said controller and said plurality of memory devices; and a data line connected between said controller and said plurality of memory devices to transfer said read data, wherein in an initializing operation, said controller counts and stores a number of cycles of a clock signal as an access time from a time point when said controller outputs said read command to the time point when said controller retrieves said read data from said memory device to enable said controller to retrieve said read data at a correct timing; and said memory subsystem further comprising at least one delay circuit arranged on said clock or data strobe line, between said controller and a selected one of said plurality of memory devices or between said memory devices, a delay amount of said at least one delay circuit being determined so that said access time is displaced from a value approximately equal to an integer multiple of the cycle of said clock signal.