Patent ID: 6225824
Filing Date: 2001-05-01
Classification: G11C

Abstract:
An output buffer circuit, comprising:an input node that receives an input logic signal that varies between a first logic value and a second logic value;an output node;a first output drive device that couples the output node to a first drive voltage node in response to the potential at a first pre-drive node;a first standard pre-drive circuit having a first controllable impedance path between the first pre-drive node and a first enable potential, the first controllable impedance path having a low impedance value when the input logic signal transitions from a first logic value to a second logic value;a supply voltage indication node that receives a supply voltage indication signal that indicates at least a first operating voltage or a second operating voltage; anda first phased pre-drive circuit having a second controllable impedance path between the first pre-drive node and the first enable potential, the first controllable impedance path having a low impedance value when the first phased pre-drive circuit is enabled,the first phased pre-drive circuit being enabled when the input logic signal transitions from the first logic value to the second logic value and the supply voltage indication signal indicates the first operating voltage, andthe first phased pre-drive circuit being enabled a predetermined delay after the input logic signal transitions from the first logic value to the second logic value when the supply voltage indication signal indicates the second operating voltage.