Patent ID: 6028815
Filing Date: 2000-02-22
Classification: G11C

Abstract:
An integrated memory, comprising:word lines;bit lines intersecting said word lines;memory cells disposed at intersection points of and connected to said word lines and said bit lines for storing bits, a number of said bits in each case forming a byte and a number of bytes in each case forming a word;byte selection lines, each of said byte selection lines upon being addressed selecting all of said bit lines of a respective byte;masking decoders connected to said byte selection lines and generating byte addressing signals outputted on said byte selection lines for addressing said byte selection lines;masking signals received by said masking decoders and allocated to a respective byte in at least one of a multiplicity of words;word selection lines;a column decoder connected to said masking decoders via said word selection lines, said column decoder outputting word address signals on said word selection lines, if addressed, each of said word selection lines causing all of said byte selection lines for one of said multiplicity of words to be simultaneously selected if none of said masking signals are active; andeach of said masking signals, if activated, preventing an addressed one of said word selection lines from selecting a respective byte selection line allocated to a corresponding byte of a corresponding word.