Patent ID: 6812747
Filing Date: 2004-11-02
Classification: G05F,G11C,H03K

Abstract:
A comparator comprising:first and second inputs for respectively receiving first and second voltages; first and second PMOS transistors arranged as current mirrors, each PMOS transistor comprising a gate, a source and a drain; said first PMOS transistor having its source connected to the first input for receiving the first voltage, and said second PMOS transistor having its source connected to the second input for receiving the second voltage; a first current source connected in series with said first PMOS transistor for defining a first branch of the comparator; a second current source connected in series with said second PMOS transistor for defining a second branch of the comparator; and an output of the comparator connected between one of the drains of said first and second PMOS transistors and the corresponding first or second current source connected in series therewith for providing an output signal based upon a comparison of the first and second voltages, the output signal having a first value when the second voltage is higher than the first voltage and a second value when the second voltage is lower than the first voltage.