Patent ID: 8095739
Filing Date: 2012-01-10
Classification: G06F

Abstract:
1. A method of data processing in a data processing system employing a weakly ordered storage architecture, the data processing system including a first set of processing units and a second set of processing units coupled to each other and data storage by an interconnect fabric, said first set of processing units including one or more first processing units and said second set of processing units including one or more second processing units, wherein each first processing unit has a first processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories, and wherein each second processing unit has a second processor core and an associated cache hierarchy including at least a level one, level two and level three cache memories, said method comprising: receiving at least one kill-type command at a first processing unit via the interconnect fabric; and in response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of the first processing unit while the at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after said at least one kill-type command is complete.