Patent ID: 7253440
Filing Date: 2007-08-07
Classification: G02F,G09G,H01L

Abstract:
1. A semiconductor device comprising: a substrate having an insulating surface; at least first and second semiconductor islands formed over said substrate wherein each of the semiconductor islands has a channel region and a pair of impurity regions; an insulating film formed over said substrate, said insulating film including at least first and second gate insulating films formed over said first and second semiconductor islands, respectively; at least first and second gate electrodes formed over said first and second semiconductor islands respectively with said first and second gate insulating films interposed therebetween; a wiring formed on said insulating film for electrically connecting one of the impurity regions of the first semiconductor island with the second gate electrode wherein said wiring is connected to said one of the impurity regions through a hole opened in said insulating film; a data line formed on said insulating film connected to the other one of the impurity regions of the first semiconductor island; a first interlayer insulating film formed over the first and second semiconductor islands, the first and second gate electrodes, the wiring and the data line; a voltage supply line formed on said first interlayer insulating film connected to one of the pair of impurity regions of the second semiconductor island; a second interlayer insulating film formed over said first interlayer insulating film and said voltage supply line; a pixel electrode formed over said second interlayer insulating film connected to the other one of the pair of the impurity regions of the second semiconductor island.