Patent ID: 6197679
Filing Date: 2001-03-06
Classification: H01L,Y10S

Abstract:
A method of manufacturing a semiconductor device having a first interconnection layer and a second interconnection layer provided over said first interconnection layer and connected through a connecting hole, comprising:forming a metal film to be said first interconnection layer on a semiconductor substrate;forming a conductive antireflection film on said first metal film;forming an oxide film on said antireflection film;forming a resist layer on said oxide film;selectively irradiating said resist layer which light using a halftone phase shift mask followed by development, thereby forming resist patterns for forming said connecting hole and an overlay mark;etching said oxide film using said resist patterns for said connecting hole and said overlay mark as masks, thereby forming said connecting hole in said oxide film as well as a pattern of an oxide film for an overlay mark; andforming a second interconnection layer to be electrically connected to said first interconnection layer through said connecting hole using said overlay mark as a reference for alignment by means of lithography technique.