Patent ID: 7214987
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a lower semiconductor substrate having an active region; an upper silicon pattern positioned above the active region; a MOS transistor including a body region within the upper silicon pattern, source/drain regions separated by the body region, and a gate electrode insulated from the upper silicon pattern and positioned on a surface of the body region; a buried insulating layer between the lower semiconductor substrate and the upper silicon pattern; and a through plug that penetrates the buried insulating layer and electrically connects the body region of the MOS transistor with the lower semiconductor substrate, the through plug being closer to one of the source/drain regions than another one of the source drain regions, an upper surface of the through plug outside a depletion layer when a source voltage is applied to the one of the source/drain regions, the upper surface of the through plug inside the depletion layer when a drain voltage is applied to the one of the source/drain regions.