Patent ID: 7139204
Filing Date: 2006-11-21
Classification: G11C

Abstract:
1. A dual-port memory device, comprising: an array of dual-port memory cells; read/write logic to read from and write to the array of dual-port memory cells; and memory testing logic to cause the read/write logic to perform a read operation at a first port of a first dual-port memory cell while the first dual-port memory cell is in a stressed condition, the read operation occurring at a frequency substantially equivalent to a maximum operating frequency of the dual-port memory device, and the stressed condition caused by emulating a write operation at a second port of the dual-port memory cell during the read operation, wherein the memory testing logic includes a command scan register to receive one or more serially issued commands from a built-in self-test processor, each command including a data portion, a memory address, and a memory test command.