Patent ID: 6010932
Filing Date: 2000-01-04
Classification: H01L,Y10S

Abstract:
A method of producing a memory cell, comprising:providing an intermediate structure comprising a substrate having at least one thick field oxide area, at least one implanted drain region, and at least one implanted source region; said intermediate structure further including at least one transistor gate member spanned between said at least one drain region and said at least one source region on an upper surface of said substrate; said intermediate structure further including a bitline within at least one layer of insulative material, wherein said bitline is in electrical communication with said at least one source region, and a storage poly layer on an upper surface of said at least one insulative material layer wherein a portion of said storage poly layer extends through said at least one insulative material layer to contact said at least one drain region;applying an etch mask on said storage poly layer, wherein said etch mask includes a boundary opening for defining a storage poly node in said storage poly layer and includes at least one aperture positioned over said storage poly layer for forming at least one recess in said storage poly node;simultaneously etching said storage poly layer through said boundary opening to form said storage poly node and through said at least one aperture to form said at least one recess in said storage poly node, wherein said simultaneously etching includes etching said storage poly layer through said boundary opening at a greater rate than etching said storage poly layer through said at least one aperture;removing said etch mask;applying a layer of capacitor dielectric on said storage poly node; andapplying a layer of plate electrode material on said capacitor dielectric.