Patent ID: 7308623
Filing Date: 2007-12-11
Classification: G11C

Abstract:
1. An integrated circuit, comprising: processing logic operable to perform data processing operations on data; at least one memory unit operable to store data for access by the processing logic; and a memory test controller operable to execute test algorithms in order to seek to detect any memory defects in said at least one memory unit; the memory test controller comprising: a storage for storing algorithm defining information for each of a plurality of test algorithms forming a sequence of test algorithms to be executed as a test procedure for at least one of said at least one memory unit; an interface operable during a single programming operation to receive the algorithm defining information for each of said plurality of test algorithms in the sequence and to cause said algorithm defining information to be stored in the storage; and algorithm processing logic operable, following said single programming operation, to execute said sequence of test algorithms for said at least one of said at least one memory unit.