Patent ID: 8441429
Filing Date: 2013-05-14
Classification: G09G,H04N

Abstract:
1. A clock generation circuit generating a first clock based on a second clock serving as reference, the first clock being synchronized with a periodical signal made up of a periodic pulse train, the clock generation circuit comprising: a detector detecting a period of the periodical signal as a number of clocks A of the second clock; and a divider (i) receiving (a) the number of clocks A outputted from the detector and (b) a total number of clocks B of the first clock which is set as a fixed value corresponding to one period worth of the period of the periodical signal and (ii) outputting, as the first clock, a dividing clock obtained by dividing the second clock by A/B wherein, the divider includes a compare-select circuit; an output circuit; and an adder adding an output value of the compare-select circuit to the total number of clocks B, the compare-select circuit comparing the number of clocks A with an output value C of the adder, and when the output value C is less than the number of clocks A, the compare-select circuit outputting the output value C, and when the output value C is equal to or more than the number of clocks A, the compare-select circuit outputting a value in which the number of clocks A is subtracted from the output value C, and the output circuit outputting a pulse each time the output value C is of a value equal to or more than the number of clocks A.