Patent ID: 7586349
Filing Date: 2009-09-08
Classification: H03K

Abstract:
1. A CMOS integrated circuit for correction of the duty cycle of a clock signal, comprising: a correction amplifier with an input to which an input clock signal is applied and an output to which a charge capacitor is connected; a voltage controlled resistor arrangement connected in the current path of the correction amplifier and having a resistance control input; and a duty cycle detector with an input to which the output of the correction amplifier is applied and with a detection output that supplies a correction voltage representative of a detected duty cycle; the duty cycle detector comprising a buffer amplifier and an RC low pass circuit which is formed by a low pass capacitor and a resistor connected to the output of the buffer amplifier; the RC low pass circuit having a time constant t=R*C that is much greater than a period of the clock signal; and the output of the duty cycle detector being applied to the resistance control input of the voltage controlled resistor arrangement.