Patent ID: 9032208
Filing Date: 2015-05-12
Classification: H04L,H04W

Abstract:
1. A communication terminal comprising: a memory coupled to a processor; a cipher key block storage which stores a cipher key for one-time pad cipher as a plurality of cipher key blocks generated by dividing the cipher key with a predetermined number of bits; an identifying information transmitter which transmits first identifying information, including a cipher key cartridge, that specifies the plurality of cipher key blocks stored by the cipher key block storage to a partner's terminal of communication, wherein the cipher key cartridge includes the plurality of cipher key blocks in encrypted form; an identifying information receiver which receives from the partner's terminal second identifying information that specifies only cipher key blocks included in cipher key blocks retained by the partner's terminal among the plurality of cipher key blocks specified by the first identifying information transmitted by the identifying information transmitter; and a cipher communication logic which copies the cipher key blocks specified by the second identifying information received by the identifying information receiver from the cipher key block storage to a volatile memory device, opens the cipher key blocks specified by the second identifying information in the volatile memory device, simultaneously to opening the cipher key blocks specified by the second identifying information in the volatile memory device, erases the cipher key blocks specified by the second identifying information from the cipher key block storage, and performs cipher communication with the partner's terminal by the one-time pad cipher using the cipher key blocks copied to the volatile memory device, wherein the cipher communication is performed using bits of each of the plurality cipher key blocks of the cipher key cartridge sequentially and each of the cipher key block and capable time length of the cipher communication is calculated by dividing number of remaining bits of the cipher key cartridge by twice of bit rate of a communication; and the communication terminal further comprising a hardware cipher key block erasing part which first erases the cipher key block of which all bits have been used by the cipher communication logic, wherein the cipher key block erasing part further erases the cipher key block which has been used for the cipher communication by the cipher communication logic when communication with the partner's terminal is finished even if there remain unused bits in the cipher key block which has been used for the cipher communication by the cipher communication logic.