Patent ID: 8207881
Filing Date: 2012-06-26
Classification: H03M

Abstract:
1. An analogue to digital converter comprising: first and second sets of ordered nodes, each first node having a corresponding second node; for each first node, a respective first resistor and current source pair, the resistor of each pair being coupled between the first node and a first converter input and the current source of each pair being coupled to the respective first node; for each second node, a respective second resistor and current source pair, the resistor of each pair being coupled between the second node and a second converter input and the current source of each pair being coupled to the respective second node; and a plurality of first comparators, each first comparator having its first input connected to a first node and its second input connected to the corresponding second node; wherein each of the first resistor and current source pairs are configured so as to provide an orderly progression of voltages at the first nodes and each of the second resistor and current source pairs are configured so as to provide an orderly progression of voltages at the second nodes.