Patent ID: 7962322
Filing Date: 2011-06-14
Classification: G05F,G11C

Abstract:
1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium; the design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit for compensating for a variance in the resistance of a buried resistor, and wherein said design structure further comprises: a waveform that is representative of the thermal characteristics of a first and second buried resistor; and functions to compensate for the variance in resistance according to the waveform the compensation circuit ( the differential driver ( the first thermal compensation unit ( the slow response circuit ( 514 ) comprises a third pFET (Pl) coupled in series with a third resistor (Rl 1 ) coupled in series with a first capacitor (Cl), a fifth resistor (Rl 2 ) coupled in series to a third nFET (Nl), the fifth resistor (Rl 2 ) and the third nFET (Nl) are coupled in parallel to the first capacitor (Cl) and further coupled to ground; the third pFET (Pl) further coupled to the output of the first inverter (INVA), receives a first inverter signal at its gate; an eighth resistor (R the fast response circuit ( a sixth resistor (Rf a ninth resistor (R 3 ) is coupled to the fourth resistor (Rf 1 ) and the second capacitor (Cr), the ninth resistor (R 3 ) is further coupled in series to a seventh resistor (R 1 ), which is further coupled to the gate of the first pFET (PA), thereby altering the resistance of the first pFET (PA) to compensate for variance in resistance of first resistor ( 506 ).