Patent ID: 6972229
Filing Date: 2005-12-06
Classification: H01L

Abstract:
1. A method comprising: forming at least two isolation regions in a semiconductor substrate; forming a first well between the two isolation regions to define a body region; forming a first oxide layer above a first portion of the body region; forming a first dielectric layer above the first oxide layer; forming a first polysilicon layer above said first dielectric layer, said first polysilicon layer forming a control gate of a non-volatile device; forming a second dielectric layer above the first polysilicon layer; forming a first spacer above the body region and adjacent said first polysilicon layer; forming a second oxide layer above a second portion of the body region not covered by said first spacer; forming a second polysilicon layer over the second oxide layer, the first spacer, and the second dielectric layer; said second polysilicon layer forming a guiding gate of the non-volatile device; forming a masking layer over the second polysilicon layer; forming a via in the masking layer and positioned above the first portion of the body region; removing the second polysilicon layer, the second dielectric layer, the first polysilicon layer, the first dielectric layer, and the first oxide layer from regions exposed in the via to form self-aligned source/drain regions; forming a second spacer to define source and drain implant regions of the non-volatile device; and delivering n-type implants in the defined source and drain regions of the non-volatile device.