Patent ID: 7271069
Filing Date: 2007-09-18
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a buried layer overlying the substrate and in contact with the substrate, the buried layer comprising a plurality of discrete layers, at least two of the plurality of discrete layers having differing elastic moduli; a semiconductor layer overlying and in contact with the buried layer; a first transistor of a first conductivity type having a channel region that is formed within the semiconductor layer and overlying a first region of the buried layer, wherein the first region of the buried layer has a first effective elastic modulus of predetermined value to optimize stress in the channel of the first transistor; and a second transistor of a second conductivity type having a channel region that is formed within the semiconductor layer and overlying a second region of the buried layer, wherein the second region of the buried layer has a second elastic effective modulus of predetermined value to optimize stress in the channel of the second transistor in a manner different than the first transistor.