Patent ID: 6933798
Filing Date: 2005-08-23
Classification: H03C,H03L

Abstract:
1. A method for amplitude trimming between an analog modulation signal and a digital modulation signal for a PLL circuit operating based on a two-point modulation, the method which comprises: locking the PLL circuit onto a desired carrier frequency without impressing any modulation; impressing the analog modulation signal into the PLL circuit, which is locked, via a summation point connected to an input of a voltage-controlled oscillator and impressing the digital modulation signal into a frequency divider configured in a feedback path of the PLL circuit resulting in a PLL control error; obtaining a signal that is characteristic of the PLL control error from the PLL circuit; and changing a modulation swing in the analog modulation signal such that the signal that is characteristic of the PLL control error has a value that is the same as a value of the signal that is characteristic of the PLL control error before the analog modulation signal and the digital modulation signal were impressed.