Patent ID: 8612899
Filing Date: 2013-12-17
Classification: G03F,G06F

Abstract:
1. A computer-implemented method of modifying an integrated circuit (IC) design, the method comprising: applying a detection rule to identify a set of regions that are defect candidates in a first layout of the IC design, the detection rule associated with a predetermined correction rule; simulating a lithographic process locally, on each piece of the first layout representing each region in said set of regions identified by use of the detection rule; evaluating a set of images generated by said simulating, to identify a subset of regions from the set of regions that correspond to defects in the images, the subset being smaller than the set; and applying, by a computer, at least the predetermined correction rule associated with the detection rule to change at least one region in the subset of regions identified by said evaluating of the set of images, to obtain a second layout.