Patent ID: 7424059
Filing Date: 2008-09-09
Classification: H04L

Abstract:
1. A data transfer circuit comprising: a transmission section including a first register for loading and outputting transmission data according to a timing of a transmission clock signal when a writing enable signal is supplied, and a strobe generation unit for starting a transmission of a strobe signal and a count of the transmission clock signals when the writing enable signal is supplied, and for stopping the transmission of the strobe signal when a counted value of the transmission clock signals reaches a set value; a reception section including a second register for loading and holding the transmission data according to a timing of a reception clock signal, an edge detection unit for receiving the strobe signal and for outputting a valid signal having a pulse width corresponding to one cycle of the reception clock signal when the stop of the strobe signal is detected, and a third register for loading the transmission data held in the second register and outputting it as reception data according to a timing of the reception clock signal when the valid signal is supplied; and a first transfer line to which the transmission data is output from the first register, and from which the transmission data is loaded to the second register, wherein the transmission data is transferred in the data transfer circuit by means of the clock signals having different frequencies between the transmission section and the reception section.