Patent ID: 6313539
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode;a selection transistor formed at the substrate;an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; anda diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor,wherein the diffusion barrier film is a Ta.sub.x Si.sub.1-x N.sub.y film or a Hf.sub.x Si.sub.1-x N.sub.y film (where 0.2<x<1 and 0<y<1), andthe lower electrode includes an Ir film, a thin film, and an IrO.sub.2 film which are sequentially formed so that said thin film is located between said Ir film and said IrO.sub.2 film, and wherein a formation temperature of said thin film is less than a formation temperature of said IrO.sub.2 film.