Patent ID: 8917803
Filing Date: 2014-12-23
Classification: H04L

Abstract:
1. A circuit for characterizing a receiver, comprising: a decision feedback equalizer (DFE) circuit coupled to a communication signal, the DFE circuit configured to generate a filtered signal from the communication signal, wherein the filtered signal is a sum of the communication signal and a variable weighting of a symbol recently sampled from the filtered signal; a clock-and-data recovery (CDR) circuit coupled to the DFE circuit, the CDR circuit configured to produce a sequence of sampled symbols from sampling the filtered signal at a variable phase relative to a clock signal; a data checker coupled to the CDR circuit, the data checker configured to generate an indication of an error in the sequence of sampled symbols; and an eye-scan controller coupled to the DFE and CDR circuits and the data checker, wherein the eye-scan controller is configured to vary the variable weighting and the variable phase through a plurality of value combinations, and the eye-scan controller is configured to check for the indication of the error for each of the plurality of value combinations; wherein the eye-scan controller: