Patent ID: 8431478
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A method of forming solder cap bumps on a semiconductor device, said method comprising steps of: providing a semiconductor substrate having a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer deposited on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; forming a plurality of conductive pillars at the pad openings of the passivation layer, so that the conductive pillar are electrically connected to the pads through the pad openings; depositing a patternable layer to cover the passivation layer and the conductive pillars, wherein the patternable layer has a plurality of pillar openings with predetermined size on top of the conductive pillars; disposing a solder ball in each pillar opening, wherein size of the solder ball is appropriated to and smaller than the predetermined size of the pillar opening; removing the patternable layer to expose the passivation layer, the conductive pillars, and the solder balls on the conductive pillars; and performing a reflow soldering on the solder ball to form a hemisphere solder cap on the conductive pillar, and further form the solder cap bump.