Patent ID: 6904510
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. A data processor which uses storage units that are subdivisible into predetermined fields for executing instructions that cause the data processor to handle numbers from respective ones of the fields separately, an instruction set of the processor comprising a conditioned assignment instruction with operand locations for addressing storage locations of a plurality of address storage units, the data processor being arranged to respond to the conditioned assignment instruction by executing a respective operation for each field in parallel, the respective operation for each particular field being conditioned by respective condition data for that particular field, characterized in that the data processor comprises for each particular field a respective multiplexer, controlled by condition data for that particular field, the multiplexer for each particular field having a first and second input coupled to a respective port for receiving a content of that particular field in a first and second storage location addressed by a first and second one of the operand locations respectively, and an output for supplying a multiplex output to that particular field in a result of the conditioned assignment instruction.