Patent ID: 6163146
Filing Date: 2000-12-19
Classification: G01R

Abstract:
An IC testing method in which loader loads IC's to be tested on IC carriers disposed in an m-row, n-column array on a test tray and in which a test section connects IC's to be tested with sockets disposed in an m-row, k-column array on a socket attachment, the column on the socket attachment corresponding to every a-th column of IC carriers, where both m and k are integers equal to or greater than two, n=ak where a is an integer equal to or greater than two, comprising the steps of:(a) determining whether or not the number of IC's to be tested in the loader is equal to or greater than the number of IC carriers;(b) if the number of IC's to be tested is equal to or greater than the number of IC carriers, causing the loader to load IC's to be tested on all of the IC carriers in the test tray, causing the test section to connect the IC's to be tested in the k columns which correspond to every a-th column of the IC carriers with the corresponding sockets to perform a test of simultaneously measurement, and repeating the test a times while translating the test tray by an IC carrier array pitch, thus completing a test for all the IC's to be tested on the test tray; and(c) if it is determined at step (a) that the number of IC's to be tested is less than the number of IC carriers, disposing the IC's to be tested at respective positions in a sequence of columns which are subject to a simultaneous measurement in the test section, causing the test section to connect the IC's to be tested which are located in a manner corresponding to every a-th column of IC carriers with the corresponding sockets to perform a test of simultaneous measurement, and repeating the test while translating the test tray by an IC a carrier array pitch, thus completing a test for all the IC's to be tested on the test tray.