Patent ID: 7888952
Filing Date: 2011-02-15
Classification: G01R

Abstract:
1. A circuit arrangement for balancing a resistance circuit, said resistance circuit including a field-effect transistor as a controllable resistor and a reference resistor, said circuit arrangement comprising: a control circuit configured to control the field-effect transistor by a gate-source voltage such that a resistance between a drain electrode and a source electrode of the field-effect transistor is in a predefinable ratio to said reference resistor, said control circuit including a balancing operation circuit, providing a first reference current to the reference resistor and providing a second reference current to the drain-source path of the field-effect transistor, wherein said first and second reference currents function to provide a differential voltage between a first voltage drop caused by the first reference current at the reference resistor and a second voltage drop caused by the second reference current at the drain-source path of the field-effect transistor.