Patent ID: 9178053
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A transistor device, comprising: an isolation region positioned in a semiconductor substrate that defines an active region in said substrate; a gate structure positioned above said substrate; a plurality of source/drain regions positioned in said active region on opposite sides of said gate structure, each of said source/drain regions having first and second portions, wherein said second portions extend to and contact said isolation region and wherein said first portion has a first junction depth relative to an upper surface of said active region and said second portion has a second junction depth relative to said upper surface of said active region, said second junction depth being greater than said first junction depth; and a plurality of halo regions positioned in said active region, wherein each of said halo regions has an outer edge that is spaced apart from an inner surface of said isolation region and defines a space within said active region that is free of said halo region, wherein, for each of said source/drain regions, said first portion is vertically located above one of said halo regions and said second portion is located above one of said spaces within said active region that is free of said halo regions, and wherein a deepest portion of each of said halo regions extends to a depth below said upper surface of said active region that is greater than a deepest portion of a respective one of said source/drain regions.