Patent ID: 8537094
Filing Date: 2013-09-17
Classification: G09G,G11C

Abstract:
1. A shift register, comprising a plurality of stages, {S n }, connected in serial, n=1, 2, . . . , N, N being a positive integer, wherein each stage S n comprises: (a) a first output for outputting a gate signal, G(n), and a second output for outputting a stage carry signal, ST(n); (b) a pull-up circuit electrically coupled between a node, Q(n), and the second output; (c) a pull-up control circuit electrically coupled to the node Q(n); (d) a pull-down circuit electrically coupled between the node Q(n) and the first output, wherein the pull-down circuit comprises a first pull-down circuit and a second pull-down circuit; (e) a pull-down control circuit electrically coupled between the node Q(n) and the pull-down circuit, wherein the pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit; and (f) a control circuit electrically coupled between the node Q(n) and the first output; wherein each of the first and second pull-down control circuits comprises: wherein the pull-up control circuit of the stage S a first transistor T a second transistor T