Patent ID: 7557639
Filing Date: 2009-07-07
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor device comprising: a logic circuit including a plurality of MOS transistors to which a power supply voltage and a sub-power supply voltage lower than said power supply voltage are supplied at a power supply side and to which a ground voltage and a sub-ground voltage higher than said ground voltage are supplied to at a ground side; a main power supply line for supplying said power supply voltage; and a main ground line for supplying said ground voltage, wherein a unit circuit constituting said logic circuit includes: wherein a first diffusion layer in which said third PMOS transistor and said first and second PMOS transistors at opposite sides thereof are arranged; a second diffusion layer in which said third NMOS transistor and said first and second NMOS transistors at opposite sides thereof are arranged; a first wiring layer including a wiring of each gate of said MOS transistors; a second wiring layer including a wiring of each drain/source of said MOS transistors; and a third wiring layer including said main power supply line and said main ground line are stacked on a semiconductor substrate.