Patent ID: 7310585
Filing Date: 2007-12-18
Classification: H01L

Abstract:
1. A method, comprising: selecting an integrated circuit chip at a selected level of fabrication; determining coordinates of potential failures of said integrated circuit chip based on one or more risk of failure analyses performed ancillary to fabrication of said integrated circuit chip; automatically generating one or more enhanced defect inspection regions for inspecting images of said integrated circuit chip based on-said coordinates; automatically selecting one or more enhanced defect inspection parameters for each of said one or more enhanced defect inspection regions based on said one or more risk of failure analyses; generating an enhanced defect inspection recipe, said enhanced defect inspection recipe including locations of said one or more enhanced defect inspection regions on said integrated circuit chip, an enhanced defect inspection parameter and a value for said enhanced defect inspection parameter for each of said one or more enhanced defect inspection regions; and placing said integrated circuit chip into an image based defect inspection tool capable of edge and image density comparisons and performing an inspection evaluating potential defects based on images from at least one of said one or more enhanced defect inspection regions and said enhanced defect inspection recipe.