Patent ID: 9019152
Filing Date: 2015-04-28
Classification: H01J,H01L

Abstract:
1. A standard wafer fabrication method, consisting of: forming a first layer of semiconductor material on a substrate; forming a first layer of oxide on the first layer of semiconductor material; forming a second layer of semiconductor material on the first layer of oxide; patterning the second layer of semiconductor material to form two or more bars; forming a second layer of oxide on the bars and the first layer of oxide; and etching the first layer of oxide and the second layer of oxide to completely remove the second layer of oxide on top of the bars and to remove the first layer of oxide on the first layer of semiconductor material between the bars to expose the first layer of semiconductor material between the bars, the second layer of oxide remaining on the opposite sides of each of the bars forming a first sidewall spacer and a second sidewall spacer respectively.