Patent ID: 6230306
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A method for optimizing the routing of nets in an integrated circuit device, said method comprising:a. dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction;b. forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and with edges connecting the vertices;c. for each of a plurality of the edges in said routing graph, computing an individual edge occupancy value, wherein the individual edge occupancy value is computed by determining at least one of a probability of a wire passing through said edge and a number of actual wires passing through said edge;d. for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge; ande. routing a net as a function of said penalty value.