Patent ID: 6440791
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A self-aligned bit-line contact opening and node contact opening fabrication process, comprising the following steps:providing a substrate having a periphery MOS active region and a memory MOS, wherein a first gate is formed on the periphery MOS active region, and a first cap layer is formed on the first gate, and where the memory cell MOS includes a second gate, a second cap layer on top of the second gate, and a source/drain region in the substrate on opposite sides of the second gate; forming a conformal insulation layer above the substrate, that uses a material same as the first cap layer and the second cap layer; covering the memory MOS with a photoresist layer; performing anisotropic etching on the periphery MOS active region, using the photoresist as a mask, to form a first spacer on a sidewall of the first gate and first cap layer; performing an ion implantation step, using the photoresist layer, the first cap layer and the first spacer as a mask, to form a source/drain region in the substrate on opposite sides of the first spacer, completing the periphery MOS; removing the photoresist layer; depositing a dielectric layer over the substrate; forming a self-aligned bit-line contact opening and a self-aligned node contact opening in the dielectric layer on opposite sides of the second gate, as well as exposing a portion of the insulation layer, and simultaneously forming a periphery gate contact opening in the dielectric layer above the first gate, to expose the first cap layer; and performing an anisotropic etching step on the insulation layer in the self-aligned bit line contact opening and the self-aligned node contact opening, to form a second spacer on a sidewall of the second gate and second cape layer, and simultaneously etching through the first cap layer in the periphery gate contact opening, to expose the first gate.