Patent ID: 6654818
Filing Date: 2003-11-25
Classification: G06F

Abstract:
A data processing system, comprising:a processor; a system memory accessible to the processor; a host bridge connected between the processor and an I/O bus; a first I/O adapter coupled to the host bridge, wherein the first I/O adapter is enabled to generate a 32-bit address; a second I/O adapter coupled to the host bridge, wherein the second I/O adapter is enabled to generate a 64-bit address; a Translation Control Entry (TCE) table suitable for translating an address generated by the first adapter to a 64-bit address and for determining whether DMA access to the translated address is authorized; and an Access Control Table (ACT), distinct from the TCE and suitable for determining whether DMA access to the address generated by the second I/O adapter is authorized; and means for processing memory accesses generated by the first adapter through the TCE table and for processing memory accesses generated by the second adapter through the ACT wherein memory accesses generated by the second adapter avoid the TCE.