Patent ID: 6947052
Filing Date: 2005-09-20
Classification: G06F

Abstract:
1. A method for reducing execution time of a program executed on a digital system by improving hit rate in a cache of the digital system, comprising the steps of: a) determining cache performance during execution of the program over a period of time as a function of address locality; b) identifying a first occurrence of high cache miss rate over a first portion of time within the period of time associated with a first address locality; c) identifying a second occurrence of high cache miss rate over the first portion of time associated with a second address locality; d) determining that the first address locality and the second address locality generally map to a same region of the cache, wherein said step of determining comprises overlying an interference grid on the plot responsive to the first address locality such that a plurality of lines are displayed at other address localities that map to the same region in cache as the first address locality; and e) relocating a portion of the program contained in the second address locality to a different address locality that generally maps to a different region of the cache.