Patent ID: 8574992
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A method for manufacturing a memory device, the method comprising: forming a plurality of stacks of conductive strips separated by insulating material; forming vertical connectors interconnecting first ends of the conductive strips of respective stacks in the plurality of; forming a memory layer on surfaces of the conductive strips of the stacks; forming conductive material over the stacks and on top surfaces of the vertical connectors; and patterning the conductive material to form a plurality of conductive lines and form contact pads, the plurality of conductive lines extending across, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the conductive strips and the plurality of conductive lines, and the contact pads on the top surfaces of the vertical connectors, wherein the contact pads and conductive material of the conductive lines are part of the same patterned level of material, such that memory elements in the memory layer are defined in the interface regions, thereby establishing a 3D array of memory cells accessible via the plurality of conductive lines and the contact pads.