Patent ID: 7352836
Filing Date: 2008-04-01
Classification: G06F

Abstract:
1. A controller for synchronizing transfers of data items stored in memory across clock domains, the controller comprising: a first control module in a first clock domain; a second control module in a second clock domain; a plurality of synchronizers, each synchronizer being in electrical communication with the first and second control modules, each synchronizer having circuitry to provide a synchronization signal to the second control module in response to a request signal received from the first control module, to generate an acknowledgment signal from the synchronization signal, and to provide the acknowledgment signal to the first control module, wherein the first control module maintains a record for each synchronizer indicating whether that synchronizer is presently ineligible to receive a request signal from the first control module, the first control module deeming a given synchronizer to be ineligible if the first control module has yet to receive an acknowledgment signal from that synchronizer for a request signal previously sent by the first control module to that synchronizer, the first control module selecting an eligible synchronizer when the first control module issues the request signal.