Patent ID: 6115761
Filing Date: 2000-09-05
Classification: G06F

Abstract:
An electronic system having a dual-descriptor FIFO, the system comprising:a data bus;a FIFO in communication with said bus;a Writer module in communication with said bus for providing data to the FIFO, the Writer module including:a write controller for transferring data to the FIFO;a first WRITE pointer indicating a location within the FIFO into which the Writer module may write data, the first WRITE pointer being accessible by the write controller; anda first READ pointer indicating a location within the FIFO from which a Reader module may read data, the first READ pointer being accessible by the write controller; andwherein the Reader module is in communication with said bus for reading said data from the FIFO written into said FIFO by said Writer module, the Reader module including:a read controller for transferring data from the FIFO;a second WRITE pointer indicating a location within the FIFO into which the Writer module may write data, the second WRITE pointer being accessible by the read controller; anda second READ pointer indicating a location within the FIFO from which the Reader module may read data, the second READ pointer being accessible by the read controller; andwherein said pair of WRITE pointers and said pair of READ pointers are each capable of pointing to common locations within said FIFO.