Patent ID: 7612585
Filing Date: 2009-11-03
Classification: H03K

Abstract:
1. A pull-up circuit for an input buffer, comprising: a pad; a first PMOS transistor having a gate is directly electrically coupled to the pad and a source and a drain; a second PMOS transistor having a source and a drain, wherein the first and second PMO transistors are coupled in series, and the drain of the second PMOS transistor is coupled to the pad; a first node coupled to substrates of the first PMOS transistor and the second PMOS transistor; a power supply coupled to the source of the first PMOS transistor; and a resistor coupled to a drain of a third PMOS transistor and coupled to the pad, where a source of the third PMOS transistor is coupled to power and a gate of the third PMOS transistor is coupled to the output of a PMOS-NMOS stack.