Patent ID: 6192458
Filing Date: 2001-02-20
Classification: G06F

Abstract:
A method of addressing a cache directory for a variable size cache, comprising:selecting at least one congruence class within a cache directory utilizing an index field from an address;for a first cache size, employing an address bit from the address to eitherselect a congruence class among congruence classes selected utilizing the index field, orselect one group of cache directory entries within a congruence class selected utilizing the index field;for a second cache size, comparing a mode bit to a predetermined logic state at one or more comparators comparing an address tar to cache directory entries to enable selection of any cache directory entry within the selected congruence class or group of cache directory entries;comparing an address tag field from the address to each cache directory entry within the selected congruence class or group of cache directory entries; andresponsive to identifying a match between a cache directory entry and the address tag field, selecting a portion of a cache memory associated with the matching cache directory entry.