Patent ID: 6949946
Filing Date: 2005-09-27
Classification: G01R

Abstract:
1. An integrated semiconductor circuit, comprising: a plurality of pad cells to be monitored in one operating mode by a functional test, said plurality of pad cells each having a connecting pad, an upstream output driver, and a connection for an input signal; a signal transmitter for producing periodic signal sequences, said signal transmitter having a connection for a periodic output signal connected to said connections for an input signal of said plurality of pad cells to be tested, in order to test a transmission response of said plurality of pad cells in said one operating mode; and shift register cells each connected in series between said connection for an input signal of a respective one of said plurality of pad cells and said connection of said signal transmitter for an output signal; said connections for an input signal of said plurality of pad cells being connected in parallel to said connection of said signal transmitter for an output signal.