Patent ID: 6340615
Filing Date: 2002-01-22
Classification: H01L

Abstract:
A method of forming a trench capacitor in a dynamic random access memory cell, comprising the steps of:a) forming a first trench pattern in a layered masking layer on a surface of a semiconductor body; b) etching a trench into said semiconductor body through said first trench pattern; c) forming a first capacitor plate disposed in said semiconductor body about said trench; d) forming a dielectric layer on inner surfaces of said trench; e) partially filling said trench with semiconductor material to form a capacitor plate within said trench; f) forming a dielectric collar in an upper portion of said trench; g) partially filling said dielectric collar with said semiconductor material; h) removing an upper portion of said dielectric collar above a top surface of said semiconductor material; and i) forming a strap disposed on said top surface of said semiconductor material; wherein the improvement comprises: (i) forming a second trench pattern disposed about and larger than said first trench pattern, (ii) etching an upper masking layer of said layered masking layer through said second trench pattern, stopping on a lower masking layer of said layered masking layer comprising substantially the same material as said dielectric collar, thereby exposing a pull back region of said substrate disposed about said trench and covered by said lower masking layer; and (iii) implanting said strap and said rim portion with a dopant.