Patent ID: 8339858
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A memory device, comprising: a first memory cell selectively coupled to a first bit line; a second memory cell selectively coupled to a second bit line; a sense amplifier selectively coupled to the first bit line and the second bit line; a data latch in communication with the sense amplifier; and a control in communication with the sense amplifier; wherein the control is configured to select a voltage to apply to a control gate of the first memory cell and a control gate of the second memory cell during programming of a selected memory cell, selected from the group consisting of the first memory cell and the second memory cell, in response to at least a data value contained in the data latch; and wherein the data value in the latch is to be programmed into a subsequent memory cell subsequent to the programming of the selected memory cell.