Patent ID: 8618830
Filing Date: 2013-12-31
Classification: G06F,H03K,Y02D

Abstract:
1. An electronic circuit, comprising: a plurality of arrays of a plurality of composite circuit elements; a full interconnect coupled to the plurality of composite circuit elements within each array of the plurality of arrays of the plurality of composite circuit elements; and a plurality of cluster queues coupling adjacent arrays of the plurality of composite circuit elements; wherein each composite circuit element of the plurality of composite circuit elements within an array of the plurality of arrays comprises: a configurable circuit element configurable for at least one data operation, the at least one data operation corresponding to at least one context; a plurality of data input queues configurably coupled to a selected bus of the full interconnect within the array for source-based addressing for the at least one context; a plurality of data output queues; a register to store at least one configuration and control word for the at least one context, the at least one configuration and control word comprising a plurality of configuration bits for the configurable circuit element, a data source address or identification, a designation of one or more data input queues of the plurality of data input queues for the at least one context, and a designation of one or more data output queues of the plurality of data output queues for the at least one context; and an element controller coupled to the configurable circuit element, the element controller to allow execution of the at least one data operation when the one or more data input queues have input data and the one or more data output queues have a status to accept output data for the at least one data operation.