Patent ID: 6075389
Filing Date: 2000-06-13
Classification: G01R,H03K

Abstract:
An operation speed measuring circuit comprising:one input terminal;a first path, connected to said input terminal and including a plurality of logic gates of same kind connected in series, for generating a predetermined propagation delay time in an inputted signal;a second path, connected to said input terminal and including an integer number of logic gates of same kind as said first path connected in series, for generating a propagation delay time smaller than the predetermined propagation delay time in the inputted signal;a frequency divider for dividing a frequency of the signal inputted from said input terminal;a selection gate circuit for selecting one of a first signal propagated via said first path and a second signal propagated via said second path in accordance with an output signal from said frequency divider, said first path and said second path comprising buffers; andat least one output terminal for outputting the signal selected by said selection gate circuit;said selection gate circuit including:a first gate comprising an AND gate for controlling propagation of an input, to said first path, of the signal inputted from said input terminal in accordance with the output signal from said frequency divider;a second gate comprising an OR gate for controlling propagation of an input, to said second path, of the signal inputted from said input terminal in accordance with the output signal from said frequency divider; anda third gate for outputting a result of a logic operation of the first and second signals.