Patent ID: 6204723
Filing Date: 2001-03-20
Classification: G05F,G11C

Abstract:
A semiconductor circuit for providing decoupling capacitance for an internal semiconductor voltage supply comprising:a plurality of memory cell capacitors connected in series at a selected node; anda source of biasing voltage connected to the series connected memory cell capacitors at the selected node for maintaining the voltage level at the node lower than the voltage level of the internal semiconductor voltage supply wherein the source of biasing voltage provides a bias voltage Vbiasout and draws a quiescent current which is very low compared to the total current of the semiconductor chip andwherein the bias voltage VA has a voltage range between VAmin and VAmax, wherein the bias circuit provides an output bias current Ibiasout having a value near zero (0.0 mAmps) when VAmin is equal to or less than VAnom-1/2Vpeak, and when VAmax is equal to or greater than VAnom+1/2Vpeak.