Patent ID: 7870521
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. A computer implemented method comprising: identifying a plurality of sequential nodes in a design file, wherein the design file represents an electronic device, each sequential node of the plurality of sequential nodes is to receive an enable signal that gates a clock signal provided to a respective sequential device, the enable signal to enable or disable propagation of information through the respective sequential device; determining an effective switching capacitance for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device wherein: determining the effective switching capacitance for the first sequential node based upon the statically predicted operation of the first device is in response to determining that the first device is within a defined downstream distance of the first sequential node; and determining the effective switching capacitance for the first sequential node based upon the statically predicted operation of the second device downstream from the first sequential node in response to determining that the second device is within the defined downstream distance of the first sequential node, wherein the effective switching capacitance of the first sequential node is not based upon the statically predicted operation of the second device when the second device is not within the defined downstream distance of the first sequential node downstream from the first sequential node and of a second device downstream from the first device; storing the effective switching capacitance for the first sequential node; and repeating determining the effective switching capacitance for each other sequential node of the plurality of sequential nodes.