Patent ID: 7454651
Filing Date: 2008-11-18
Classification: G06F

Abstract:
1. A main-board, comprising: a CPU (Central Processing Unit); a chipset having a phase-locked circuit, a CPU-bus circuit and a memory-bus circuit, wherein the phase-locked circuit is electrically connected to the CPU-bus circuit and the memory-bus circuit, and the CPU-bus circuit is electrically connected to the CPU, wherein a transmission frequency ratio of an information-transmitting frequency of the CPU-bus circuit to an information-transmitting frequency of the memory-bus circuit is initially set by the CPU; and a clock-rate control-signal generating module electrically connected to the CPU and the chipset and generating a clock-rate control signal to be transmitted to the phase-locked circuit of the chipset, wherein the phase-locked circuit resets the transmission frequency ratio of an information-transmitting frequency of the CPU-bus circuit to an information-transmitting frequency of the memory-bus circuit according to the clock-rate control signal.