Patent ID: 8255850
Filing Date: 2012-08-28
Classification: G06F

Abstract:
1. A process of designing integrated circuits comprising: A. receiving an integrated circuit design containing a first circuit block and a second circuit block, the circuit blocks containing the same transistors and corresponding interconnects, having similar fundamental characteristics/material, and having a sensitivity model represented by the same function; B. determining a time duration of stress for each circuit block in a same age, the determining including analyzing the functions/interconnections of each circuit block to determine the respective time durations of stress of each block; C. estimating a corresponding time delay introduced in each circuit block due to respective time durations of stress; D. computing, by a computer, a circuit path delay for a first path, which includes each of the first and second circuit blocks, using the estimated delay of each block in the first path, including summing the estimated delays of the circuit blocks in the first path; and E. fabricating an integrated circuit if the path delay of the first path meets desired timing constraints.