Patent ID: 7370264
Filing Date: 2008-05-06
Classification: H03M

Abstract:
1. A circuit, comprising: an encode unit adapted to receive a data word and operable to encode the data word using a matrix to generate corresponding check bits, the encode unit including components to implement a matrix having, 11 rows and 528 columns, the matrix having elements generated in groups of four columns for rows row an 11×11 identity matrix concatenated onto end of the 11×528 matrix to form an 11×539 matrix; and a last 1×11 column matrix concatenated onto the end of the identity matrix to form an 11×540 matrix; a compare unit coupled to the encode unit to receive the generated check bits and adapted to receive a second set of check bits, and operable to compare the check bits from the encode unit to the second set of check bits and to generate an error signal indicating the result of the comparison; a buffer adapted to receive and store the data word and operable to provide the data word on an output responsive to an enable signal; and a corrector unit coupled to the compare unit and to the buffer and operable to activate the enable signal responsive to the error signal indicating no errors have been detected and operable to correct single bit errors in the data word stored in the buffer responsive to the error signal indicating a single bit error and to thereafter activate the enable signal.