Patent ID: 8207753
Filing Date: 2012-06-26
Classification: G11C,H03K

Abstract:
1. An integrated circuit comprising: a number of latches, wherein each latch in the number of latches has a plurality of inputs and a plurality of storage nodes, and wherein the plurality of storage nodes include a number of pairs of circuit nodes that form a number of upsettable circuit node pairs, and wherein each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes; and a number of filters, wherein each filter in the number of filters has an input and a plurality of outputs, each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches, and each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.