Patent ID: 6800513
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device comprising:preparing a wafer in which a first semiconductor layer comprising an amorphous semiconductor or polycrystal semiconductor, a first insulative film and a second semiconductor layer are stacked in this order, forming a second insulative film at a partial region on a main surface of the second semiconductor layer of the wafer including a region to be formed with a gate electrode, forming an impurity layer at high concentration in a region in the first semiconductor layer opposing to the region to be formed with the gate electrode, forming a third insulative film on the second semiconductor layer at the region to be formed the gate electrode and disposing an upper gate electrode on the region to form the gate electrode above the main surface of the second semiconductor layer in contact with the third insulative film, wherein the impurity layer at high concentration is formed by implanting desired impurity ions passing through the second insulative layer, the second semiconductor layer and the first insulative layer into the first semiconductor layer to obtain a maximum impurity concentration in the first semiconductor layer.