Patent ID: 9189724
Filing Date: 2015-11-17
Classification: G06K,H04B,H04L

Abstract:
1. A semiconductor device comprising: a reception circuit configured to receive an amplitude-modulated carrier wave from an antenna, to demodulate said carrier wave, and to extract a clock signal from the carrier wave; a logic circuit configured to perform a data process on a reception signal by the reception circuit; and a PLL circuit configured to receive the clock signal extracted by the reception circuit, to generate an internal clock signal of the logic circuit, and to control synchronization of the internal clock signal with the extracted clock signal, wherein the PLL circuit is further configured to continue to generate the internal clock signal during a period of stopping of a change in the extracted clock signal, wherein the PLL circuit comprises an error current generation circuit coupled to a low pass filter, and a voltage controlled oscillation circuit coupled to an output of the low pass filter, wherein the error current generation circuit outputs an error current signal to the low pass filter which is based on a charge error signal and a discharge error signal, wherein the error current generation circuit is configured to output said error current signal to cause the low pass filter to stop charging/discharging during the period of stopping of a change in the extracted clock signal and wherein the PLL circuit comprises