Patent ID: 8627160
Filing Date: 2014-01-07
Classification: G01R,H03K

Abstract:
1. A logic device, comprising: a first group of clock gating cells configured to receive an input clock signal, wherein each clock gating cell of the first group of clock gating cells comprises a first delay element configured to delay the input clock signal by a first duration during a scan shift operation of the logic device, wherein the first delay element comprises a first programmable delay element configured to set the first duration based on a first programmable delay input; a first group of flip-flops coupled to the first group of clock gating cells; a second group of clock gating cells configured to receive the input clock signal, wherein each clock gating cell of the second group of clock gating cells comprises a second delay element configured to delay the input clock signal by a second duration, different from the first duration, during the scan shift operation, wherein the second delay element comprises a second programmable delay element configured to set the second duration based on a second programmable delay input; a second group of flip-flops coupled to the second group of clock gating cells, wherein the first group of flip-flops and the second group of flip-flops are configured to receive the input clock signal delayed by the first duration and the input clock signal delayed by the second duration, respectively, during the scan shift operation; and a feedback circuit coupled to the first delay element and to the second delay element and configured to generate the first programmable delay input and the second programmable delay input based on instantaneous voltage droop (IVD) associated with the scan shift operation.