Patent ID: 8595498
Filing Date: 2013-11-26
Classification: G06F

Abstract:
1. A method for authenticating access to a secured chip by a test device, the method comprising steps of: receiving, by the test device, a challenge produced by the secured chip, the test device storing at least one common key derived from a unique identifier of the secured chip, at least one test key derived from unique identifier of the test device and means for applying a bidirectional mathematical operation to the received challenge; combining, by the test device, the received challenge with the test key by applying a bidirectional mathematical operation, encrypting, by the test device, a result of the bidirectional mathematical operation with the common key stored on the test device, to obtain a cryptogram; sending by the test device, the cryptogram to the secured chip, the secured chip storing the same common key, a reference digest resulting from a cryptographic function on the test key and means for applying to the challenge a reverse operation of the bidirectional mathematical operation; decrypting, by the secured chip, the cryptogram with the common key stored on the secured chip; obtaining, by the secured chip, an image key representing the test key by applying, with the challenge, the reverse operation of the bidirectional mathematical operation previously used by the test device; calculating, by the secured chip, an expected digest of the image key with a cryptographic one-way function; verifying, by the secured chip, validity by comparing the expected digest with the reference digest; and if the result of the comparison between the digest of the image key and the reference digest is positive, accessing, by the test device, the secure chip in a test mode, wherein the challenge is produced by the secured chip using a hardware pseudo-random number generator or by an algorithm implemented in a stored generation program, or the challenge is produced by a counter which increments or decrements from a given start value at each connection of the test device to the secured chip or at each test request sent to said secured chip, or wherein the challenge comprises a time stamp including a current date and hour with a predetermined precision, and wherein the bidirectional mathematical operation comprises a logical addition, multiplication or XOR operation.