Patent ID: 7480198
Filing Date: 2009-01-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: memory cells including floating bodies in an electrically floating state and storing data based on a number of majority carriers within the floating bodies; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory cells; transfer gates connected to between the bit lines and the sense nodes; and latch circuits latching data to the sense nodes, wherein in a data read operation, a selection word line is in an inactive state during a latch period which is from immediately before the latch circuits start a data latch operation until when the transfer gate disconnects the bit lines from the sense nodes after the latch operation, the selection word line being one of the word lines and being connected to selection memory cells from which data is to be read to the sense nodes.