Patent ID: 6260086
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A controller circuit that transfers a set of peripheral data words, comprising:a microprocessor that performs a transfer multiple command by generating sequential addresses within a predetermined range of addresses, wherein each of the sequential addresses is associated with one peripheral data word of the set of peripheral data words; anda peripheral device, comprisingan aliasing circuit, coupled to the microprocessor, that is responsive only to addresses within the predetermined range of addresses for generating a transfer control signal, wherein the aliasing circuit generates the transfer control signal in response to each of the sequential addresses,a first in first out (FIFO) register for storing the set of peripheral data words, anda data bus register coupled to the microprocessor, the FIFO register, and the aliasing circuit, wherein the data bus register transfers a peripheral data word in the set of peripheral data words between the microprocessor and the FIFO register in response to the transfer control signal.