Patent ID: 7411838
Filing Date: 2008-08-12
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first selection gate disposed in a first region on a substrate; a first storage node disposed in a second region adjacent to said first region; a local bit line disposed in a third region adjacent to said second region; a second storage node disposed in a fourth region adjacent to said third region; a second selection gate disposed in a fifth region adjacent to said fourth region on said substrate; a control gate disposed on said first storage node and said second storage node; and a drive circuit that controls voltages applied to said substrate, said first selection gate, said local bit line, said second selection gate, and said control gate; wherein said drive circuit performs a first control to selectively draw electrons out of said first storage node to said local bit line through F-N tunneling by respectively applying a negative voltage to said control gate, a positive voltage to said second selection gate, a voltage lower than the voltage applied to said second selection gate to said first selection gate, and a positive voltage to said local bit line during a writing operation.