Patent ID: 6711725
Filing Date: 2004-03-23
Classification: G06F

Abstract:
A method of creating a conformal outline for layout of one or more devices on an integrated circuit, the method comprising the steps of:(a) defining a plurality of input rectangles in a Cartesian coordinate system having a first axis and a second axis, each input rectangle having two edges parallel to the first axis and two sides parallel to the second axis; (b) acquiring coordinates on the first axis where the sides of each input rectangle reside; (c) forming a sorted list of the acquired coordinates; (d) initializing a variable I=2; (e) identifying from the input rectangles first and second candidate rectangles having one of their respective sides positioned at the smallest and largest coordinates in the sorted list, respectively; (f) setting the other of the sides of the respective first and second candidate rectangles equal to the coordinate on the first axis stored in the Ith position in the sorted list thereby forming a shared side; (g) for each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, modifying the lengths of the sides of the candidate rectangle as required so that they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles; and (h) when the shared side with respect to one candidate rectangle does not coincide with or overlap the shared side with respect to the other candidate rectangle, modifying the length of the shared side with respect to the one candidate rectangle so that it coincides with or overlaps the shared side with respect to the other candidate rectangle.