Patent ID: 6578065
Filing Date: 2003-06-10
Classification: G06F

Abstract:
In a computer system comprising a multi-thread processor, a main memory, a cache memory, and a thread scheduler, a method of scheduling the execution of reads in the multi-thread processor, the method comprising:transmitting from the multi-thread processor to the cache memory an address that identifies a data line to be retrieved; performing a lookup operation in the cache memory for the address, wherein if performing the lookup operation in the cache memory does not locate the address, then sending a cache miss signal and ownership information to the thread scheduler, forming a lookup operation in the main memory for the address, transmitting the data line corresponding to the address from the main memory to the cache memory, and retrieving the data line corresponding to the address; and wherein if performing the lookup operation in the cache memory does locate the address, then sending a cache hit signal and ownership information to the thread scheduler, and retrieving the data line corresponding to the address; updating a figure of merit from the data line information for each thread of a plurality of threads, wherein the figure of merit is selected from the group consisting of the number of data lines owned by a thread, the number of data lines brought into the cache by a thread over a defined time interval, the number of accesses to the cache by a thread, the number of hits for a thread over a defined time interval, and the number of data lines hit by threads other than the thread that brought the data lines into the cache over a given time interval; and if a cache miss occurred, transmitting a signal to the multi-thread processor to enable a thread based on the figures of merit of the plurality of threads.