Patent ID: 8305785
Filing Date: 2012-11-06
Classification: H02M,Y02B

Abstract:
1. A power source apparatus utilizing a synchronous rectification system, comprising: a main transformer having a primary coil, and a first secondary coil and a second secondary coil having first ends connected to each other through a tap mutually electromagnetically coupled to said primary coil; a first field effect transistor having a drain connected to a second end of said first secondary coil, a source connected to a reference electric potential, and a gate to which a first drive signal is supplied; a second field effect transistor having a drain connected to a second end of said second secondary coil, a source connected to the reference electric potential, and a gate to which a second drive signal is supplied; and a gate driver configured to generate the first drive signal and the second drive signal in accordance with a drain voltage of said first field effect transistor and a drain voltage of said second field effect transistor, for driving said first field effect transistor and said second field effect transistor in a complementary style, a first comparator for comparing a drain voltage of said first field effect transistor with a reference voltage; a second comparator for comparing a drain voltage of said second field effect transistor with the reference voltage; a first delay circuit for delaying the first drive signal by a previously set dead time; a second delay circuit for delaying the second drive signal by the previously set dead time; a first circuit for generating the second drive signal in accordance with an output signal from said first comparator, and the first drive signal delayed by said first delay circuit, and outputting the second drive signal to each of said gate of said second field effect transistor, and an input of said second delay circuit; and a second circuit for generating the first drive signal in accordance with an output signal from said second comparator, and the second drive signal delayed by said second delay circuit, and outputting the first drive signal to each of said gate of said first field effect transistor, and an input of said first delay circuit.