Patent ID: 9009372
Filing Date: 2015-04-14
Classification: G06F,Y02D

Abstract:
1. A processor in which a plurality of nodes, each including a processor core and a distributed shared cache memory, are arranged two-dimensionally in an X-axis direction and a Y-axis direction, the processor comprising: a first connecting unit that connects a node located at a position other than both ends in the X-axis direction and a node located adjacent to the node located at the position other than both ends in the X-axis direction, and connects a node located at the either end in the X-axis direction and a node adjacent to the node located at the either end in the X-axis direction; and a second connecting unit that connects a node located at a position other than both ends in the Y-axis direction and a node located adjacent to the node located at the position other than both ends in the Y-axis direction, and connects a node located at the either end in the Y-axis direction and a node adjacent to the node located at the either end in the Y-axis direction, wherein the cache memories included in the respective nodes are divided into banks in the Y-axis direction, coherency of the cache memories in the X-axis direction is controlled by a snoop system, and the cache memories are shared by the nodes.