Patent ID: 6376293
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of fabricating a transistor, comprising the steps of:providing a silicon substrate with an upper surface of a first conductivity type; forming a silicon epitaxial layer of a second conductivity type on said upper surface of said silicon substrate surface; forming a disposable gate over a first defined region of said silicon epitaxial layer; forming a plurality of outer sidewall structures adjacent to said disposable gate; forming a plurality of source/drain regions adjacent to said outer sidewall structures; forming an insulator layer over said source/drain regions; removing said disposable gate without substantially removing any other exposed material; forming a plurality of inner sidewall structures adjacent to said outer sidewall structures; removing said silicon epitaxial layer that lies between said inner sidewall structures thereby exposing a portion of said silicon substrate; forming a gate dielectric over said exposed portion of said silicon substrate; and forming a gate electrode over said gate dielectric.