Patent ID: 6636572
Filing Date: 2003-10-21
Classification: G11B

Abstract:
An architecture for processing a digital feedback control signal, resulting from processing an incoming signal, having a bit rate frequency, and a separate timing reference signal, the processed feedback signal controlling a synchronization circuit, comprising:parallel paths, having stages, for processing the digital feedback signal; and a structure facilitating cross-referenced processing between said parallel paths, wherein the processing on each of said paths is done at half the bit rate frequency of the incoming signal; wherein said structure employs: an XOR gate on one of said paths and an {overscore (XOR)} gate on the other of said paths; an overflow detection circuit in each of said paths; an error detection circuit, having an output, in each of said paths; a band and overflow detection circuit, having an output, in each of said paths; a summer, having an output, for summing said outputs from each of said error detection circuits; a multiplexer, having an output, for processing outputs from each of said error detection circuits, said summer, and each of said band and overflow circuits; a reference clock, having an output; and a register for processing said outputs from said multiplexer and said reference clock into a control signal for a timing recovery circuit.