Patent ID: 6278640
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) comprising:bit lines and word lines;memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage Vdd bit charge storage capacitor, the FET having a gate connected to a corresponding word line;a high voltage supply which supplies a controlled high voltage Vpp which is in excess of the high logic level voltage Vdd but less than a transistor damaging voltage;applying circuitry applying the controlled high voltage Vpp to the word line through the source-drain circuit of a pass FET, the applying circuitry including a level shifter with latching which receives word line selection signals only at Vdd logic levels to drive and latch word line control signals at Vpp voltage levels.