Patent ID: 7486558
Filing Date: 2009-02-03
Classification: G06F,G11C,Y02D

Abstract:
1. A non-volatile memory device having addressable pages of memory cells in a core array, comprising: a set of data latches for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits; a first-in-first-out queue for incoming memory operations and for outputting the queued memory operations to be executed in the core array; a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined; a queue manager for accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation; wherein whenever a memory operation being executed in the core array is mergeable with one or more queued memory operations to be outputted from the queue, said queue manager terminates the memory operation being executed and instead executes a combined memory operation of the mergeable memory operations; and whenever two or more queued memory operations to be outputted from the queue are mergeable among themselves but not with a memory operation being executed in the core array, said queue manager executes a combined queued memory operation of the mergeable memory operations after the memory operation being executed in the core array has completed.