Patent ID: 6833595
Filing Date: 2004-12-21
Classification: H01L

Abstract:
A semiconductor device including first and second transistors formed on a semiconductor chip, each having a terminal commonly connected to a node, said device comprising:a main line of a first gate eletrode layer of said first transistor extending in a first direction; two branches branching substantially perpendicularly from said main line of said first gate electrode layer, said two branches extending in a second direction; a first diffusion layer of said first transistor coupled to a first contact hole; a second diffusion layer of said first transistor coupled to a second contact hole; a third diffusion layer of said first transistor coupled to a third contact hole; a main line of a second gate electrode layer of said second transistor extending in said first direction, said second gate electrode layer being electrically separated from said first gate electrode layer; two branches branching substantially perpendicularly from said main line of said second gate electrode layer, said two branches extending in said second direction; a fourth diffusion layer of said second transistor coupled to a fourth contact hole, said fourth diffusion layer electrically coupled to said first diffusion layer as said terminal inside of said semiconductor chip; a fifth diffusion layer of said second transistor coupled to a fifth contact hole; and a sixth diffusion layer of said second transistor coupled to a sixth contact hole, wherein said first diffusion layer, one of said branches of said first gate electrode, said second diffusion layer, the other of said branches of said first gate electrode, said third diffusion layer, said fourth diffusion layer, one of said branches of said second gate electrode, said fifth diffusion layer, the other of said branches of said second gate electrode, and said sixth diffusion layer are arranged in this order in a line extending in said first direction.