Patent ID: 9136336
Filing Date: 2015-09-15
Classification: B82Y,H01L

Abstract:
1. An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physically separated from each other by a gap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each other, wherein the first semiconductor layer is doped with a different type impurities selected from n-type impurities and p-type impurities than the second semiconductor layer; a third electrode on the first semiconductor layer overlapping the first graphene layer; a fourth electrode on the second semiconductor layer overlapping the second graphene layer; and an output electrode connected to the third electrode and the fourth electrode, wherein the first semiconductor layer faces the back gate substrate with the first graphene layer therebetween, and the second semiconductor layer faces the back gate substrate with the second graphene layer therebetween.