Patent ID: 8665125
Filing Date: 2014-03-04
Classification: H03M

Abstract:
1. An electronic device for analog-to-digital conversion of an analog input signal, the device comprising: a successive approximation register (SAR), a capacitive analog-to-digital converter (CDAC) comprising a plurality of capacitors coupled with a first side to a common node, a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage level at the common node with another voltage level, and a successive approximation register (SAR) control stage for providing a digital code representing a conversion result, wherein the electronic device is configured to operate in a calibration mode, in which the electronic device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors and to perform a conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor.