Patent ID: 7115937
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate; a first insulating layer formed on the substrate; a contact plug formed in the first insulating layer; a capacitor element lower electrode formed on the first insulating layer and connected to the contact plug; a second insulating layer formed burying the capacitor element lower electrode and its surroundings; a capacitive insulating film formed covering the capacitor element lower electrode; and a capacitor element upper electrode formed above the capacitor element lower electrode with the capacitive insulating film interposed in between, such that the capacitor element lower electrode becomes a capacitance-defining area, wherein a plurality of capacitor elements composed of the capacitor element lower electrode, the capacitive insulating film and the capacitor element upper electrode are arranged in a capacitor element group, and wherein a surface of the capacitor element lower electrodes and the second insulating layer is planarized by polishing, and a surface area of the capacitor element group is within the range of 10,000 to 100,000 μm