Patent ID: 9006741
Filing Date: 2015-04-14
Classification: B82Y,G11C,H01L

Abstract:
1. A memory device comprising: a first conductive layer; a second conductive layer; a memory layer interposed between the first conductive layer and the second conductive layer, wherein: a first partition wall and a second partition wall over the first conductive layer, the first partition wall and the second partition wall each having tapered shapes at its sides; and an insulating layer over the second conductive layer, the first partition wall and the second partition wall, wherein the memory layer is provided over the first conductive layer between the first partition wall and the second partition wall, wherein a side surface of the memory layer and a side surface of the second conductive layer are in contact with the side with the tapered shape of the first partition wall or the second partition wall, wherein a top of the first partition and a top of the second partition are over a top surface of the second conductive layer, wherein the insulating layer is in contact with a whole top surface of the second conductive layer and is in contact with the top of the first partition wall and the top of the second partition wall, and wherein the insulating layer is separated from the side surface of the second conductive layer by the first partition wall or the second partition wall.