Patent ID: 9124260
Filing Date: 2015-09-01
Classification: G09G,H03K

Abstract:
1. A flip-flop comprising: a first CMOS circuit; a second CMOS circuit; a plurality of input terminals; a first output terminal; a second output terminal; an input transistor; a power supply; and a regulator circuit, wherein the first CMOS circuit includes a first transistor which is a P channel transistor and a second transistor which is an N channel transistor, the first transistor having a gate terminal and a drain terminal thereof connected to a gate terminal and a drain of the second transistor, respectively, the second CMOS circuit includes a third transistor which is a P channel transistor and a fourth transistor which is an N channel transistor, the third transistor having a gate terminal and a drain terminal thereof connected to a gate terminal and a drain terminal of the fourth transistor, respectively, a gate side of the first CMOS circuit, a drain side of the second CMOS circuit, and the first output terminal are connected to each other, a drain side of the first CMOS circuit, a gate side of the second CMOS circuit, and the second output terminal are connected to each other, the input transistor has a gate terminal, a source terminal, and a drain terminal thereof connected to (i) a first input terminal, (ii) a second input terminal, and (iii) each of the first CMOS circuit and the second CMOS circuit, respectively, the power supply (i) is connected to the first CMOS circuit or the second CMOS circuit and (ii), when a first input signal supplied to the first input terminal is turned to be active, is electrically connected to the second input terminal, the regulator circuit regulates an electric potential between the second input terminal and the power supply when the second input terminal and the power supply are electrically connected to each other.