Patent ID: 7504340
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A method for providing contact etch selectivity for etching a contact etch hole through a dielectric layer of an integrated circuit, the method comprising the steps of: obtaining an etch rate through the dielectric layer of the integrated circuit, the etch rate taking into account a reactive ion etch (RIE) lag value for the dielectric layer and a desired aspect ratio of the contact etch hole; selecting a diameter value for the contact etch hole based on the etch rate, wherein selecting the diameter value comprises selecting a first diameter value for a first plurality of contact etch holes based on a first etch rate, the first etch rate taking into account the RIE lag value and a desired aspect ratio of the first plurality of contact etch holes, and selecting a second diameter value for a second plurality of contact etch holes based on a second etch rate, the second etch rate taking into account the RIE lag value and a desired aspect ratio of the second plurality of contact etch holes; and storing the selected diameter value for the contact etch hole in a memory.