Patent ID: 7447107
Filing Date: 2008-11-04
Classification: G11C

Abstract:
1. A random access memory, comprising: multiple state machines including a first state machine and a second state machine, wherein the first state machine is configured to provide first signals to control the random access memory and provide first command operations that provide a first type and generation of memory and the second state machine is configured to provide second signals to control the random access memory and provide second command operations that provide a second type and generation of memory that is different than the first type and generation of memory; and selection circuitry that fully selects only one of the multiple state machines, wherein the selection circuitry conducts the first signals to select the first state machine and provide the first command operations and the selection circuitry conducts the second signals to select the second state machine and provide the second command operations, wherein the first state machine is configured to provide single data rate dynamic random access memory command operations and the second state machine is configured to provide double data rate dynamic random access memory command operations.