Patent ID: 8249139
Filing Date: 2012-08-21
Classification: H04L

Abstract:
1. A data receiver, comprising: an equalizer, compensating incoming signal according to a configuration, and outputting corrected signal; a clock data recovery (CDR) unit, coupled to the equalizer to receive the corrected signal, using a clock to sample the corrected signal for generating raw data, and outputting phase information of the clock; and an equalizer controller, coupled to the CDR unit and the equalizer, wherein the equalizer controller receives the phase information, and tunes the configuration in accordance with the phase information, wherein during an i wherein a cycle of the clock is divided into a plurality of phases, and the phase information indicates that the CDR unit samples the corrected signal at a k wherein the equalizer controller further finds the one of the statistical results having a least number of the phases used to sample the corrected signal, and applies the corresponding one of the setup values to the configuration.