Patent ID: 6323687
Filing Date: 2001-11-27
Classification: H03K

Abstract:
An output buffer for a digital integrated circuit chip, the chip having a core which is powered by a first supply voltage VCC which is received at a first supply voltage port, said output buffer comprising:a second supply voltage port for receiving a second supply voltage VCCQ;a power return line port;an output port for providing a voltage output;an input port for receiving an input data value representative of the voltage value to be provided at said output, the input data value having a first state when a logic-low voltage is to be generated at the output and a second state when a logic-high voltage is to be generated at the output;a comparator having a first input coupled to a scaled version of the second supply voltage VCCQ, a second input coupled to a reference voltage V.sub.REF, and an output providing a voltage which is related to the difference between the scaled version and the reference voltage;a pull-up transistor having a gate electrode, a source electrode, and a drain electrode, one of the source and drain electrodes being coupled to the second voltage supply port and the other of said source and drain electrodes being coupled to the output;a pull-down transistor having a gate electrode, a source electrode, and a drain electrode, one of the source and drain electrodes being coupled to the return line port and the other of said source and drain electrodes being coupled to the output; anda first logic control circuit responsive to the input data value and the value of the comparator output for discharging the gate of the pull-up transistor when the input data value is in its second state, said first logic control circuit discharging the gate of the pull-up transistor at a rate which varies with the value of the comparator output.