Patent ID: 7222214
Filing Date: 2007-05-22
Classification: G06F

Abstract:
1. A programmable non-volatile memory device comprising: programmable non-volatile memory having blocks that are identified by internal addresses; an address bus interface configured to receive external addresses as part of read and write operations; and block switching logic operatively associated with the programmable non-volatile memory and the address bus interface and configured to enable a translation rule that applies to an external address to be changed from a first translation rule that maps the external address to a first internal address to a second translation rule that maps the external address to a second internal address, wherein the first translation rule is different from the second translation rule; and wherein the block switching logic includes a selection cell, which is a portion of the programmable non-volatile memory, and wherein the applied translation rule is changed from the first translation rule to the second translation rule by changing at least one bit of the selection cell.