Patent ID: 6444576
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method to connect pads on front side of a chip to pads on back side of said chip, comprising:a) forming multi-levels of metalization over a field oxide on a front side of a silicon substrate with metalized vias connecting levels of metalization and with an intermetal dielectric (IMD) between and over said metalization. b) forming an oxide on backside of said silicon substrate using plasma enhanced chemical vapor deposition (PECVD), c) forming a first opening in said IMD on a front side of said silicon substrate to create a first hole over a second level metal land connected by means of a via to a first level metal land on top of said field oxide, d) forming a second opening in the oxide on the backside of said wafer opposite said first opening, e) etching a second hole from backside of said silicon substrate to said field oxide using oxide on back side of said silicon substrate as a mask. f) etching said second hole into said field oxide and stopping at said first level metal land, g) depositing an oxide coating on walls of said second hole by means of a PECVD to produce a continuous and uniform coating, h) depositing electroless copper or electroless nickel in said second hole to fill said second hole from said first level metal land to said backside of said silicon substrate, i) etching back said metal in said second hole, j) preparing said first hole and said second hole for a solder bump, j) depositing said solder bump onto metalization in said first hole on front side of said silicon substrate using a hot solder dip, k) depositing said solder bump onto metalization in said second hole on said backside of said silicon substrate using a hot solder dip.