Patent ID: 6261892
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate, comprising the steps of:forming a portion of at least one of the isolation regions to expose a first area of the substrate;depositing a mask layer over the integrated circuit including the first area;forming the mask layer to expose a second area of the substrate within the first area;converting a portion of the substrate to a selectively etchable material, wherein the selectively etchable material lies in an area subjacent to the second area and extends only partially to the bottom surface of the substrate;selectively etching the selectively etchable material to form a void;removing the mask layer to expose the isolation region;depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region;depositing a dielectric layer over the conductive layer wherein the dielectric layer extends at least to the height of the isolation region;polishing the surface of the dielectric layer until the surface is planar and the top surface of the isolation region is exposed; andforming at least one patterned conductive layer over the surface of the dielectric layer that is coplanar with the surface of the isolation region.