Patent ID: 6035372
Filing Date: 2000-03-07
Classification: G06F

Abstract:
A microprocessor to operate in an environment of multiple processors sharing a common bus, said microprocessor having at least RAS and CAS outputs for exclusive coupling, via said common bus, to RAS and CAS inputs of a private DRAM, the microprocessor comprising a DRAM Control Register having at least one bit which is set to designate whether the DRAM is private to the microprocessor, a read circuit which reads the one bit and determines whether the bit is set, and a control logic circuit coupled to the read circuit for controlling functions of the microprocessor according to whether the DRAM is private to it such that in case the DRAM is private to the microprocessor, the microprocessor keeps the status of the RAS and CAS outputs even if the microprocessor releases the common bus.