Patent ID: 6462987
Filing Date: 2002-10-08
Classification: G11C

Abstract:
A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and a bit line, the reading circuit comprising:an array line, selectively connectable to said bit line, and a reference line; a precharging circuit for precharging said array line and said reference line at a preset precharging potential; a comparator having a first terminal connected to said array line, and a second terminal connected to said reference line; and equalization means for equalizing potentials of said array line and reference line, in a precharging step, said equalization means comprise an equalization line distinct from said reference line; and controlled connection means for connecting, in said precharging step, said equalization line to said array line and to said reference line, and for disconnecting said equalization line from said array line and from said reference line, at the end of said precharging step.