Patent ID: 7761280
Filing Date: 2010-07-20
Classification: G06F

Abstract:
1. A method of simulating the operation of a data processing apparatus to determine timing information of data transfers, the data processing apparatus comprising a number of master logic units and slave logic units coupled via a bus, the data processing apparatus being configured to perform the data transfers between the master logic units and the slave logic units over the bus, the method comprising the steps of: a) generating anticipated timing information for each successive data transfer over the bus by assuming that each successive data transfer can occur with exclusive access to the bus; b) determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus; and c) in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating machine-readable revised timing information for those data transfers for use in correcting said anticipated timing information as part of simulation output results, the revised timing information being generated using bus status information until those data transfers have been completed.