Patent ID: 6453425
Filing Date: 2002-09-17
Classification: G06F,G11C

Abstract:
An apparatus comprising:a first circuit configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal; a second circuit configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal; and a third circuit configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal, wherein said first enable signal and said second enable signal have transitions only when said one or more output signals are at said predetermined logic level.