Patent ID: 6349390
Filing Date: 2002-02-19
Classification: G06F

Abstract:
A memory module for attachment to a computer system having a memory bus comprising;a printed circuit card, memory storage chips on said card to store data bits and associated ECC check bits, tabs on said circuit card to couple the card and the memory bus, logic circuitry to selectively operatively connect and disconnect the memory chips and the memory bus, a signal processing element connected in circuit relationship with said memory chips, logic circuitry to selectively permit said signal processing element to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all one bit errors in the stored data bits and stored associated check bits, and re-store the correct data bits and associated check bits in the memory chips when said memory chips and said memory bus are disconnected, whereby at least single bit soft errors occurring during storage of data bits and check bits can be corrected before that data is read from the memory chips to the memory bus.