Patent ID: 8143138
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method of fabricating a dual-damascene interconnect structure, comprising: forming openings in a first resist layer disposed above a low dielectric constant (low-k) dielectric layer; etching openings in the low-k dielectric layer; depositing a first liner layer to protect the low-k dielectric layer; forming openings in a second resist layer; etching additional openings in the low-k dielectric layer that is disposed on an etch stop layer; etching openings in the etch stop layer disposed on a first metal layer; depositing a second liner layer to protect the low-k dielectric layer; removing the first resist layer prior to depositing the first liner layer; removing the second resist layer prior to depositing the second liner layer; and depositing a second metal layer on the second liner layer.