Patent ID: 6154163
Filing Date: 2000-11-28
Classification: H03M

Abstract:
A finite state logic network of the sequential type, the finite state logic network comprising:a successive approximation shift register having a serial output terminal comprising:a plurality of register elements, each register element connected to other register elements, including a comparison input terminal and an output terminal and being configurable for selectively storing any of a plurality of data values based upon the state of the successive approximation shift register, the data values including the data value stored in the register element, a data value stored in another register element and a data value corresponding to a signal appearing on the comparison input terminal, each register element comprising a switch element having a first conduction terminal coupled to an output terminal of the another register element and a second conduction terminal;a serial line connected to the second conduction terminal of the switch element of each register element, the serial line being coupled to the serial output terminal of the successive approximation ADC, a value appearing on the serial output terminal of the successive approximation ADC during an analog-to-digital conversion operation corresponds to a value stored by the register element most recently converted.