Patent ID: 6809935
Filing Date: 2004-10-26
Classification: H01L,H05K

Abstract:
A structure for providing thermal stress relieve for packages that are used for the mounting of semiconductor devices, comprising:a circuit board on which at least one point of electrical contact has been provided; one or more layers of thermal stress relieve material created on said circuit board; one or more semiconductor devices for mounting on said circuit board, said semiconductor devices having been provided with points of electrical contact; and electrical contact between said point of electrical contact provided on said circuit board and said points of electrical contact provided in said semiconductor devices, said electrical contact having been established using Printed Circuit Board technology or Build Up Board technology, said Printer Board technology comprising creating one or more openings in said one or more layers of thermal stress relieve material aligned with said at least one point of electrical contact provided on said circuit board, by depositing a layer of conductive material over said created layers of thermal stress relieve material, including said one or more openings and by creating an upper layer of interconnect lines and contact pads formed by patterning said layer of conductive material on said layer of said thermal stress relieve material; a layer of dielectric deposited over said upper layer of interconnect lines, including said exposed thermal stress relieve material; a solder mask deposited over said layer of dielectric; and an array of conductive pads in the layer of dielectric created by patterning said layer of dielectric, said conductive pads having been connected to at least one of said points of electrical contact provided on said circuit board, said conductive pads further being points of electrical contact for said semiconductor devices.