Patent ID: 6040217
Filing Date: 2000-03-21
Classification: H01L

Abstract:
A fabricating method of an ultra-fast pseudo-dynamic nonvolatile flash memory, wherein a characteristic of the memory is to comprise a capacitor coupled to a local bit line, the method comprising:providing a substrate with a P-well, dividing the substrate into a memory cell region and a peripheral region, forming a field oxide layer on the substrate for electrical isolation;forming a first gate oxide layer and a first polysilicon layer on the memory cell region of the substrate in sequence, and implanting a first N-type dopant into the first polysilicon layer;forming a dielectric layer on the memory cell region of the substrate;forming a second gate oxide layer on the peripheral region of the substrate;forming a second polysilicon layer over the substrate;etching the second polysilicon layer on the peripheral region to form a gate layer;etching the second polysilicon layer, the dielectric layer, and the first polysilicon layer on the memory cell region to form a stacked layer on the memory cell region;removing a part of the field oxide layer by self-aligned-source etching, implanting a second N-type dopant into the memory cell region of the substrate by medium doped drain ion implantation to form a plurality of first doped regions;implanting a third N-type dopant into the peripheral region of the substrate by lightly doped drain ion implantation to form a plurality of second doped regions;forming an oxide spacer layer over the substrate, implanting a fourth N-type dopant to perform a source/drain ion implantation and form a plurality of first sources and a plurality of first drains on the memory cell regions of the substrate, and a second source on the peripheral region of the substrate, wherein a step of the self-aligned-source etching to remove the part of the field oxide layer is to connect the first sources;forming a first oxide layer and a first opening therein to expose the first and the second drains;forming a tungsten plug to fill the contact;forming a third polysilicon layer which covers the memory cell region of the substrate;forming a oxy-nitride layer to cover the third polysilicon layer entirely; andcovering a first metal layer over the substrate and patterning the first metal layer;wherein, the first metal layer on the memory cell region, the oxy-nitride layer, and the third polysilicon layer form the capacitor, while the third polysilicon layer forms the local bit line.