Patent ID: 7577774
Filing Date: 2009-08-18
Classification: G06F,H04L

Abstract:
1. An enhanced direct memory access unit comprising: a plurality of ports, each port operating to perform at least one of supplying data as a source port or receiving data as a destination port and at least one port operating to perform both supplying data as a source port and receiving data as a destination port; a queue manager receiving and prioritizing data transfer requests, each data transfer request specifying a source port, a destination port and an amount of data to transfer from said source port to said destination port, said prioritizing including for each data transfer request assigning a data source channel and separately and independently assigning a data destination channel; a plurality of source channel registers storing data corresponding to a plurality of data source channels; a source pipeline supplying a read command to a source port specified in a data transfer request under control of a corresponding one of said source channel registers; a plurality of destination channel registers storing data corresponding to a plurality of destination channels, each of said destination channel registers different from each of said source channel registers; a destination pipeline supplying write command and write data to a destination port specified in a data transfer request under control of a corresponding one of said destination channel registers; and said queue manager initiating in response to a second data transfer request a second source read command in said same data source channel of said first data transfer request after completion of a first source read command in response to a first data transfer request and before completion of the corresponding destination write command in the assigned data destination channel of said first data transfer request.