Patent ID: 7924611
Filing Date: 2011-04-12
Classification: G11C

Abstract:
1. A method for programming a data bit by a page buffer circuit coupled to a bitline in a flash memory device having a plurality of wordlines and a plurality of multi-level cells, each of the multi-level cells being coupled to the bitline and one of the wordlines, the method comprising: initializing a higher-bit register and a lower-bit register; storing a first or second internal data bit into the higher-bit register in response to a first or second higher read-control signal and an input data bit received through an input/output node; transferring the first or second internal data bit from the higher-bit register to the lower-bit register through a sensing node in response to a first program control signal; detecting a voltage of the sensing node which is determined by the first or second internal data bit and storing a first lower sensing data bit into the lower-bit register in accordance with a result of the detection in response to a first lower read-control signal; reading a lower data bit from one of the multi-level cells that corresponds to a selected wordline and a selected bitline; detecting a voltage of the sensing node which is determined by the lower data bit and storing a second lower sensing data bit into the lower-bit register in accordance with a result of the detection in response to the first lower read-control signal; generating a lower verifying data bit in response to the second lower sensing data bit and determining whether a logical value of the lower verifying data bit is an established value; outputting the second lower sensing data bit to the selected bitline through the sensing node in response to a second program control signal while a program voltage is being supplied to the selected wordline when the logical value of the lower verifying data bit is different from the established value, making the second lower sensing data bit programmed into the selected multi-level cell; and repeating the steps of reading, storing the second lower sensing data bit, determining, and outputting until the logical value of the lower verifying data bit reaches the established value.