Patent ID: 8130015
Filing Date: 2012-03-06
Classification: H03L

Abstract:
1. A semiconductor device comprising: a phase determining circuit that generates a first phase determination signal based on phases of a first clock signal and a second clock signal each constituting one cycle in a high period and a low period; a sampling circuit that generates a second phase determination signal based on at least the first phase determination signal; and a clock generating unit that generates a third clock signal by delaying the first clock signal based on the second phase determination signal, the second clock signal being generated based on the third clock signal, wherein the sampling circuit sets the second phase determination signal as a signal that increases a delay amount regardless of the first phase determination signal, when a rising edge of the second clock signal is in the high period of the first clock signal, the sampling circuit sets the second phase determination signal as a signal that increases the delay amount based on the first phase determination signal, when a rising edge of the second clock signal reaches the low period from a high period of the first clock signal, and the sampling circuit sets the second phase determination signal as a signal that decreases the delay amount based on the first phase determination signal, when a rising edge of the second clock signal reaches a high period from a low period of the first clock signal.