Patent ID: 7575964
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: a) forming a sacrificial layer on a lower semiconductor substrate; b) patterning the sacrificial layer to form an opening to expose a portion of the lower semiconductor substrate; c) forming an upper silicon epitaxial layer on the lower semiconductor substrate having the opening; d) patterning the upper silicon epitaxial layer, the sacrificial layer, and the lower semiconductor substrate to form a trench that defines an active region, the active region including an upper silicon pattern extending across the exposed lower semiconductor substrate, and sacrificial layer patterns exposed on sidewalls of the trench; e) selectively removing the exposed sacrificial layer patterns; f) forming buried insulating layers and an isolation layer, respectively, filling spaces, from which the sacrificial layer patterns are removed, and the trench; g) forming gate electrodes on the lower semiconductor substrate having the isolation layer formed thereon, insulated from the upper silicon pattern, and intersecting the upper silicon pattern, the gate electrodes spaced apart from one another and passing over opening sidewalls that face each other; h) forming a source region and a drain region along opposite sides of the gate electrodes, each drain regions being located over a corresponding one of the buried insulating layers; and i) forming a bit line and a cell capacitor being electrically connected with the source region and the drain region, respectively.