Patent ID: 6420920
Filing Date: 2002-07-16
Classification: G11C,H03K

Abstract:
A phase splitter for generating first and second complimentary output clock signals from an input clock signal, the phase splitter comprising:an even number of series connected inverters, the first of the inverters in the series coupled to receive the input clock signal and the last of the inverters in the series generating the first output clock signal; an odd number of series connected inverters, the first of the inverters in the series coupled to receive the input clock signal and the last of the inverters in the series generating the second output clock signal; a first pair of transistors each of which is coupled between an output of one of the inverters in the even number of series connected inverters and respective first and second nodes; and a second pair of transistors each of which is coupled between an output of one of the inverters in the odd number of series connected inverters and respective third and fourth nodes.