Patent ID: 6437455
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A semiconductor memory device comprising:memory cells each of which includes two load transistors, two driver transistors, and two access transistors, wherein: each of the memory cells includes first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers; the first and second gate-gate connecting layers are formed over a semiconductor substrate; the first and second drain-drain connecting layers are formed over a first interlayer dielectric and connect drains of the load transistors with drains of the driver transistors; the first and second drain-gate connecting layers are formed over a second interlayer dielectric; the first drain-gate connecting layer connects the first drain-drain connecting layer to the second gate-gate connecting layer; the second drain-gate connecting layer connects the second drain-drain connecting layer to the first gate-gate connecting layer; and the first and second gate-gate connecting layers, the first and second drain-drain connecting layers, and the first and second drain-gate connecting layers are formed in different layers.