Patent ID: 6242763
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure, said protection structure comprises:a semiconductor substrate;a thin film layer separated from a bulk silicon substrate by an insulator inside said semiconductor substrate;a first isolation region formed in said thin film layer;a second isolation region formed in said thin film layer;a first region having a first conductivity type formed in between said first and second isolation region but not adjoining to any of them;second region formed in between said first region and said second isolation region but only adjoining to said first region, said second region being of a second conductivity type which is different to said first conductivity type;a third region formed in between said first isolation region and said first region, said third region being of said first conductivity type;a fourth region formed in between said second isolation region and said second region, said fourth region being of said first conductivity type;a fifth region having an exposed upper surface formed in said first region, said fifth region being of said second conductivity type;a sixth region having an exposed surface formed in said second region, said sixth region being of said second conductivity type;a seventh region having an exposed upper surface formed in said second region and overlapping said first region, moreover, said seventh region is in between said fifth and sixth region, said seventh region being of said first conductivity type;a first contact on said structure coupled to said third region and said fifth region; anda second contact on said structure coupled to said fourth region and said sixth region.