Patent ID: 7689771
Filing Date: 2010-03-30
Classification: G06F

Abstract:
1. A method of coherency management in a multi-processor data processing system having multiple upper level cache memories and a lower level cache memory, said method comprising: removing a cache line from a first of the multiple upper level cache memories and transmitting a castout request for the cache line from the first upper level cache memory to a lower level cache memory, said castout request including an indication of an exclusive ownership coherency state; in response to the castout request, placing the cache line in the lower level cache memory in said exclusive ownership coherency state and recording a source indication at said lower level cache indicating which of said multiple upper level cache memories was a source of said cache line; and in response to a subsequent data request from one of the multiple upper level cache memories, the lower level cache memory determining by reference to said source indication whether the data request was received from the source of the cache line, and if so, supplying the cache line in response to the data request in the exclusive ownership coherency state.