Patent ID: 9054694
Filing Date: 2015-06-09
Classification: H03K

Abstract:
1. A circuit arrangement comprising: a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node; a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage; a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage; a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage; a bypass circuit element connected in parallel to the load, the by pass circuit element having a first end and a second end, the first end coupled to the level shifting stage and a second end for coupling to the second reference voltage; wherein the first input voltage is configured to switch between a first logic state and a second logic state and the second input voltage is configured to switch between the second logic state and the first logic state; wherein the level shifting stage is configured to generate a first output voltage at the output node when the first input voltage is in the first logic state and the second input voltage is in the second logic state and the level shifting stage is configured to generate a second output voltage at the output node when the first input voltage is in the second logic state and the second input voltage is in the first logic state; wherein the bypass circuit element is configured to allow current to flow through upon application of an external voltage for bypassing the load; wherein the level shifting stage comprises a first set of sequentially coupled pull-up and pull-down sub-circuits cross-coupled to a second set of sequentially coupled pull-up and pull-down sub-circuits to generate a positive feedback loop; wherein the first set of sequentially coupled pull-up and pull-down sub-circuits comprises a first pull-up transistor comprising a control electrode, a first controlled electrode and a second controlled electrode; and a first pull-down transistor comprising a control electrode, a first controlled electrode and a second controlled electrode; wherein the first pull-up transistor is sequentially coupled to the first pull-down transistor by coupling the first controlled electrode of the first pull-up transistor to the first controlled electrode of the first pull-down transistor; and wherein the circuit arrangement further comprises a delay balancer sub-circuit coupled in parallel to the first pull-down transistor.