Patent ID: 9159618
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a first interlayer insulation layer disposed over the substrate; first transistors disposed over the substrate and buried in the first interlayer insulation layer; a multilayered interconnect layer disposed over the first interlayer insulation layer, wherein a second interlayer insulation layer of the multilayered interconnect layer is disposed over the first interlayer insulation layer, and a third interlayer insulation layer of the multilayered interconnect layer is disposed over the second interlayer insulation layer; capacitance devices disposed in third interlayer insulation layer of the multilayered interconnect layer above the second interlayer insulation layer; a gate electrode and a diffusion layer of each of the first transistors; a metal interconnect in contact with the upper surface of the gate electrode, extended in a direction identical with the gate electrode and buried in the first interlayer insulation layer; first contacts coupled to the diffusion layer of the first transistor and buried in the first interlayer insulation layer, wherein the metal interconnect includes a material identical with that of the first contact; second transistors disposed over the substrate and situated in a logic circuit region which is a region different from a memory circuit region including the first transistors; a second contact for coupling the second transistor with a first interconnect, wherein the first interconnect is situated in the lowermost interconnect layer of the second interlayer insulation layer of the multilayered interconnect layer and extends entirely through the second interlayer insulation layer, the lowermost interconnect layer and the second contact being disposed below the capacitance devices, and wherein the second contact includes a material identical with that of the metal interconnect; and bit lines situated in the memory circuit region, disposed in the layer identical with the first interconnect, and coupled to the diffusion layer of each of the first transistors, the bit lines arranged entirely below the capacitance devices and extending entirely through the second interlayer insulation layer.