Patent ID: 6393507
Filing Date: 2002-05-21
Classification: G06F

Abstract:
A computer system, comprising:a processor; a memory; a processor-to-memory bus coupled between the processor and the memory; a core logic unit; at least one peripheral device; a status register within the core logic unit that indicates a status of the at least one peripheral device; an updating mechanism for updating the status register to indicate changes in the status of the at least one peripheral device, wherein the updating mechanism includes, a plurality of address inputs coupled to address lines of the processor-to-memory bus, an address detecting circuit coupled to a set of higher order bits in the plurality of address inputs, for detecting an address in a reserved range of addresses specified by the set of higher order bits, and a decoder circuit coupled to a set of lower order bits in the plurality of address inputs, for detecting references to particular addresses in the reserved range of addresses, wherein the status register is coupled to a set of outputs from the decoder circuit, so that a reference to a particular address in the reserved range of addresses by a peripheral device feeds through the decoder circuit and updates status information for the peripheral device in the status register, the status register including outputs coupled to the processor so that the status register can be read by the processor.