Patent ID: 6195771
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A semiconductor device formed on a wafer, comprising:a semiconductor memory circuit; anda test circuit for testing the semiconductor memory circuit;wherein said semiconductor memory circuit includes a plurality of memory cells disposed in the form of a matrix having rows and columns for respectively storing data therein, and is activated based on a test pattern so as to generate the data stored in the respective memory cells for every column as output data; andwherein said test unit includes:a test pattern generator, which generates said test pattern indicative of a type of test to be performed and an expected value to be obtained by testing according to the test pattern, in response to a received command;a decision unit, which compares the output data with the expected value and generates a result of the comparison; anda translation unit, which converts the result of the comparison into address data and generates the address data.