Patent ID: 7479815
Filing Date: 2009-01-20
Classification: H03K,H03L

Abstract:
1. A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced, the apparatus comprising: a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in accordance with a defined divider value, the prescalar circuit including at least a resynchronization element and a prescalar front-end configured to generate an intermediate signal characterized by a 50% duty cycle; a first programmable counter disposed to receive the prescaled signal, said first programmable counter characterized by a first effective program counter value of A/2, wherein A comprises an integral value; a second programmable counter disposed to receive the prescaled signal and to produce a divided signal utilized within the phase-locked loop, said second programmable counter characterized by a second effective program counter value of B/2, wherein B comprises an integral value; and a control circuit connected to the first programmable counter and to the second programmable counter wherein the control circuit generates, when A comprises an odd value and B comprises an even value, a first resynchronization signal causing resynchronization of the first programmable counter with respect to a trailing edge of the waveform defining the prescaled signal and a second resynchronization signal causing resynchronization of the second programmable counter with respect to a leading edge of the waveform.