Patent ID: 6337886
Filing Date: 2002-01-08
Classification: H04B,H04L

Abstract:
A receiving apparatus comprising:a counter for counting for a prescribed period of time the number of bits having one of two different levels, out of bits forming a digital signal which is entered and having the two different levels, and supplying a count signal; a bit rate detector for calculating the bit rate of said digital signal from the count signal and supplying a multiplying factor selection signal; a differentiating circuit, into which said input digital signal is entered, for supplying a pulse signal at a varying point of said input digital signal; a rectifying circuit for accomplishing full-wave rectification of the pulse signal, and supplying a rectified pulse signal; a band-pass filter for passing harmonics of the clock component of said input digital signal contained in the rectified pulse signal; and a frequency dividing circuit, into which said harmonics are entered, for frequency-dividing said harmonics by a ratio set on the basis of said multiplying factor selection signal, and supplying a resultant frequency-dividing clock signal.