Patent ID: 7835199
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: a memory cell array having a plurality of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns; a plurality of wordlines comprising a main wordline and a plurality of sub wordlines, each of the plurality of wordlines being coupled to a corresponding one of the plurality of rows; a plurality of bitlines, each of the plurality of bitlines coupled to a corresponding one of the plurality of columns; a row decoder comprising a main decoder coupled to the main wordline and a sub decoder coupled between the main wordline and each of the plurality of sub wordlines and being coupled to the plurality of wordlines and configured to supply a step-down voltage to the plurality of wordlines during a standby period, the step-down voltage being lower in magnitude than a power supply voltage; and a first voltage switch coupled to the sub decoder and comprising a step-down unit configured to receive the power supply voltage and output the step-down voltage, and a first switching unit configured to supply the step-down voltage to the sub decoder in response to a standby signal.