Patent ID: 7468617
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit structure comprising: a plurality of input circuits, each input circuit for receiving a signal compliant with a different input/output (I/O) standard; each input circuit comprising: a pair of inverters, each inverter comprising at least one MOS transistor having a source, a drain and a gate, the gate being connected to an input of the inverter; and a PMOS transistor and an NMOS transistor connected to each pair of inverters, the PMOS transistor and the NMOS transistor connected in series between a power supply and ground, each transistor comprising a source, a drain and a gate, the PMOS transistor being connected between the power supply and a first output node and the NMOS transistor being connected between ground and the first output node, each gate being connected to an output of one of the pair of inverters, the gate of each NMOS transistor and the gate of the inverter to which it is connected having widths such that the ratio of the widths of the gate of the NMOS transistor and the gate of the inverter to which it is connected in each input circuit is substantially the same and the widths of the gates of the NMOS transistor in at least two input circuits being substantially different.