Patent ID: 7281115
Filing Date: 2007-10-09
Classification: G06F

Abstract:
1. A method for clearing address translation buffer entries of a translation lookaside buffer (TLB) address translation buffer in a computer system, the computer system comprising a plurality of page tables and a plurality of address translation tables providing translation information to translate virtual addresses to memory addresses, each address translation buffer entry dynamically caching address translation information, the method comprising the steps of: the computer system fetching a Dynamic Address Translation Table Entry (IDTE) instruction from a main storage, the instruction comprising an opcode and a second field for determining second information, the second information comprising an address space control element (ASCE) address or an origin address of an address translation table consisting of: a first region table having entries comprising addresses of a second region table origins, a second region table having entries comprising addresses of third region table origins, a third region table having entries comprising addresses of segment table origins, or a segment table having entries comprising addresses of page table origins wherein a page table comprise memory addresses; determining from the opcode that the instruction is configured to initiate execution of a clear operation; and executing the instruction, the executing step comprising the steps of: