Patent ID: 6211083
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A method of forming a metal silicide region, for a metal oxide semiconductor field effect transistor, (MOSFET), device, on a semiconductor substrate, comprising the steps of:forming a polysilicon gate structure, on an underlying gate insulator layer;forming insulator spacers on the sides of said polysilicon gate structure;forming a heavily doped source/drain region located in a region of said semiconductor substrate, not covered by said polysilicon gate structure, or by said insulator spacers;depositing a metal layer;performing a first anneal procedure to form a first phase, metal silicide region on the top surface of said polysilicon gate structure, and on the top surface of said heavily doped source/drain region, with portions of said metal layer, located on said insulator spacers, remaining unreacted;removing said portions of said metal layer, from said insulator spacers;depositing a capping silicon oxide layer, with said capping silicon oxide layer comprised with a compressive stress;performing a second anneal procedure, convert said first phase, metal silicide region, to a second phase, metal silicide phase;depositing an interlevel insulator layer;performing a planarization procedure;forming a via hole in said interlevel insulator layer, and in said capping silicon oxide layer, exposing a portion of the top surface of a second phase, metal silicide region that resides on a heavily doped source drain/region; andforming a metal plug structure in said via hole.