Patent ID: 7812455
Filing Date: 2010-10-12
Classification: H01L

Abstract:
1. An interconnect comprising: a semiconductor substrate; a first insulator layer formed on the semiconductor substrate, wherein the first insulator layer comprises at least one of SiO a first via formed in the first insulator layer by etching through the first insulator layer to the semiconductor substrate, wherein a first metal (M1) is deposited in the first via; a M1-N an etch-stop layer formed on the first insulator layer to protect the first insulator layer, wherein the etch-stop layer selectively exposes the M1-N a second insulator layer formed on the etch-stop layer, wherein the second insulator layer comprises at least one of SiO a trench formed in the second insulator layer by etching the second insulator layer to a selected depth; a second via formed in the second insulator layer by further etching the second insulator layer from the trench to the M1-N a seed layer coating the trench and the second via, wherein the seed layer comprises a second metal (M2) and makes contact with the M1-N