Patent ID: 6456517
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a random access memory chip; and a package having the random access memory chip, wherein the package includes a plurality of pins for electrically connecting the random access memory chip to an external device, and wherein the plural pins provide memory functions commonly to a random access memory device and to an electrically erasable and programmable non-volatile semiconductor memory device that includes a NAND-type flash memory device, each of the pins being arranged at a position of a pin corresponding to the non-volatile semiconductor memory device, wherein the plural pins are composed of input/output pins for receiving address and data, power supply voltage pins, ground voltage pins, a read enable pin, a chip enable pin, a command latch enable pin, an address latch enable pin, and a write enable pin, and wherein the non-volatile semiconductor memory comprises: a memory cell array having EEPROM cells in which rows and columns are arranged; a first latch circuit for receiving a row address; a row selection circuit for selecting at least one of the rows in response to a row address outputted from the first latch circuit; a page buffer circuit for reading data stored in cells corresponding to the selected row, and latching the read-out data; a second latch circuit for receiving and temporarily storing the latched row address to the first latch circuit; a comparator for receiving row addresses each latched to the first and second latch circuits, and comparing whether the row addresses are matched with one another; and a read control logic for controlling an operation of the row selection circuit according to an output signal of the comparator.