Patent ID: 6118723
Filing Date: 2000-09-12
Classification: G11C

Abstract:
A semiconductor memory device comprising:an array of memory cells arranged in columns and rows, the array being divided into a plurality of sub-arrays;a plurality of main word lines, each said main word line extending over a number of the sub-arrays that are arranged on the same row;a plurality of sub-word select lines;a plurality of sub-word drivers, each said sub-word driver being selected by specifying particular one of the main word lines and particular one of the sub-word select lines in combination, more than one of the sub-word drivers being associated with each said sub-array; anda plurality of sub-word lines, each said sub-word line being driven by associated one of the sub-word drivers and connected to associated one of the memory cells,wherein the sub-arrays are classified into a plurality of blocks, each said block including an associated set of the sub-arrays arranged on the same row, andwherein more than one of the sub-word select lines are associated with each said block, andwherein each said sub-word select line includes: a portion placed in parallel to the main word lines; and a plurality of portions that are all connected to the parallel portion and arranged in the respective sub-arrays within the same block to cross the main word lines at right angles.