Patent ID: 6111815
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A semiconductor burst nonvolatile semiconductor memory comprising:a memory cell group for storing data therein;an input terminal group to which an address signal is supplied;an intermediate terminal;an output terminal group;a latch circuit which stores data read out from the memory cell group and outputs the same data from an address indicated by a signal supplied to the output terminal group;a first address counter circuit and a second address counter circuit coupled respectively between the input terminal group and the intermediate terminal group, each address counter circuit of the first address counter circuit and the second address counter circuit latching therein an address signal which is supplied to the input terminal group, and outputting the latched address signal to the intermediate terminal group and a burst address signal generated by itself to the intermediate terminal group when receiving a first burst control signal of first level and selected by selection signals, each address counter circuit of the first address counter circuit and the second address counter circuit transferring the address signal which is supplied to the input terminal group to the intermediate terminal group when receiving a first burst control signal of second level and selected by the selection signals;a selection circuit which outputs the selection signals to alternately select either the first address counter circuit or the second address counter circuit in response to a second burst control signal; anda decoder circuit which decodes a signal which is supplied to the intermediate terminal group and outputting the decoded signal to the output terminal group.