Patent ID: 9087861
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of manufacturing a vertical type memory device, comprising: stacking a first lower insulating layer, a lower sacrificial layer and a second lower insulating layer on a substrate; forming a stacking structure by alternately and repeatedly stacking sacrificial layers and insulating layers on the second lower insulating layer; etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure on the lower sacrificial layer, the preliminary stepped shape pattern structure having a stepped shape at an edge portion thereof; forming a pillar structure making contact with a surface of the substrate through the preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers, the pillar structure including a channel pattern; partially etching the preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers to form a stepped shape pattern structure having a first opening portion extending in a first direction and a second opening portion extending in a second direction perpendicular to the first direction, the second opening portion being formed by cutting at least an edge portion of the lower sacrificial layer; forming gaps in the stacking structure by removing the sacrificial layers and at least a portion of the lower sacrificial layer; and forming word lines and selection lines in the gaps.