Patent ID: 8975712
Filing Date: 2015-03-10
Classification: G06F,H01L

Abstract:
1. A method, comprising: forming first and second transistor devices in and above adjacent first and second active regions that are separated by an isolation region formed in a semiconductor substrate, said first and second transistors comprising at least one source/drain region and a shared gate structure: forming a continuous conductive line that spans across said isolation region, wherein said continuous conductive line contacts said at least one source/drain region of each of said first and second transistors; and performing an etching process through a patterned mask layer on said at least one continuous conductive line to form separated first and second unitary conductive source/drain contact structures, wherein said first unitary conductive source/drain contact structure contacts only said at least one source/drain region of said first transistor and said second unitary conductive source/drain contact structure contacts only said at least one source/drain region of said second transistor.