Patent ID: 6218297
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method for patterning a platinum layer in the fabrication of integrated circuits, the method comprising:providing a substrate assembly including a surface in a reaction chamber;forming a patterned metal-containing adhesion layer on the surface, resulting in at least one exposed surface region of the substrate assembly;forming platinum on the patterned metal-containing adhesion layer and the at least one exposed surface region of the substrate assembly;annealing the substrate assembly including the patterned metal-containing adhesion layer and the platinum thereon, wherein annealing the substrate assembly comprises exposing the substrate assembly to a temperature less than the melting point of the at least one exposed surface region for a time period sufficient to cause pooling of the platinum on the at least one exposed surface region of the substrate assembly; andremoving platinum from the at least one exposed surface region of the substrate assembly.