Patent ID: 6794710
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A split-gate flash memory structure, comprising:a substrate having a trench therein; a floating gate formed inside the trench, wherein the upper surface of the floating gate is lower than the upper surface of the substrate; a tunnel oxide layer formed between the floating gate and the substrate; a select gate formed inside the trench, wherein the upper surface of the select gate is protruding beyond the upper surface of the substrate; gate dielectric layer formed between the floating gate and the select gate; a dielectric layer formed between the select gate and the substrate, wherein a portion of the dielectric layer is physically in contact with a sidewall of the trench and the select gate; and a source/drain region formed on each side of the select gate in the substrate, wherein the source/drain region and the floating gate are separated from each other by a distance.