Patent ID: 6411116
Filing Date: 2002-06-25
Classification: G01R,Y10T

Abstract:
A test circuit comprising:a first plurality of input terminals and a first plurality of output terminals formed on a semiconductor substrate; a plurality of buffers coupled between the first plurality of input terminals and the first plurality of output terminals on the semiconductor substrate, a portion of the first plurality of output terminals being coupled to a compliant interconnect media wherein the compliant interconnect media is a dielectric material having a plurality of conductive fibers formed therethrough; a current sensing and blocking circuit for sensing current through one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined current limit is exceeded, the current sensing and blocking circuit being formed on the semiconductor substrate; a voltage sensing and blocking circuit for sensing voltage through the one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined voltage limit is exceeded, the voltage sensing and blocking circuit being formed on the semiconductor substrate; a feedback circuit for receiving data from at least one of the voltage sensing and blocking circuit, the current sensing and blocking circuit, and the plurality of buffers, and using this data to provide test information, the feedback circuit being formed on the semiconductor substrate; a temperature circuit coupled to the feedback circuit, the temperature circuit being used for receiving and processing temperature information, the feedback circuit being formed on the semiconductor substrate.