Patent ID: 6667931
Filing Date: 2003-12-23
Classification: H04N

Abstract:
A memory circuit (MEM) able to temporarily store a first block of data comprising no more than N components, and able to produce a second block of N lines of a component of said data, said memory circuit comprising data banks able to receive data words, and address controllers associated to the data banks, and able to store:N first words (SA1-SAN) of a first component (A) which are mutually vertically contiguous in N first data banks having N different numbers, N second words (SAN+1-SA2N) of the first component which are mutually vertically contiguous and horizontally contiguous to the N first words, in N second data banks which have N other different numbers, and N words (SY1-SYN, SYN+1-SY2N) of a second component (Y), which are mutually vertically contiguous and correspond to the same data as N words (SA1-SAN, SAN+1-SA2N) of the first component, in data banks which have numbers corresponding to a circular permutation of the database numbers associated to the N words of the first component.