Patent ID: 8697539
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method of forming a semiconductor device or structure, comprising: a) providing a first fin between a first STI region and a second STI region; b) providing a second fin between the second STI region and a third STI region; c) depositing an insulation layer on an upper surface of the second STI region and at least partially over upper surfaces of the first and second fins; d) etching the insulation layer until the insulation layer has a height that is approximately 50-75 percent of a height of one of the first and second fins with respect to a top surface of the STI region; and e) forming a conductive layer over surfaces of the insulation layer and the first and second fins to provide an interconnect between the first and second fins such that the conductive layer is separated from the first, second, and third STI regions by the insulation layer.