Patent ID: 6727763
Filing Date: 2004-04-27
Classification: H03L

Abstract:
A cellular phone having a plurality of time slots in a single frame each utilizing a different frequency and a phase locked loop (PLL) synthesizer comprising:a phase comparator for comparing a phase of a first frequency signal having a first frequency against a phase of a reference frequency signal; a voltage controlled oscillator (VCO) having an input node receiving a frequency control voltage controlled based on a result of the comparison by said phase comparator, and an output node outputting a second frequency signal having a second frequency controlled based on said frequency control voltage; a frequency divider for receiving said second frequency signal to divide said second frequency and to output said first frequency signal; and a loop filter connected at said input node of said VCO for passing said frequency control signal to said VCO, said loop filter having providing different time constants for a filter function and a means for applying one of said time constants in accordance with particular transitions between said plurality of time slots in said single frame in accordance with a required locking time to minimize bandwidth of said loop filter.