Patent ID: 8878287
Filing Date: 2014-11-04
Classification: H01L

Abstract:
1. A field effect transistor (FET) device, comprising: a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer on both sides of the first trench, the body region extending partially the depth of the first trench; a gate dielectric layer formed on the sidewall of the first trench; a conductive spacer formed on the sidewall of the first trench and being insulated from the semiconductor layer by the gate dielectric layer, the conductive spacer acting as the gate of the FET device; a dielectric layer formed over the conductive spacer and insulating the conductive spacer in the first trench; a second trench formed in the first trench over the dielectric layer and extending beyond a bottom portion of the first trench, the semiconductor layer being exposed at a bottom portion of the second trench; a conductive layer of a semiconductor material having the first conductivity type and being heavily doped, the conductive layer filling the first trench and the second trench and being in contact with the exposed semiconductor layer at the bottom portion of the second trench, the conductive layer acting as the drain of the FET device; and a source region of the first conductivity type formed in a top portion of the body region adjacent the first trench, wherein the FET device comprises a channel formed in the body region along the sidewall of the first trench from the source region to a bottom portion of the body region.