Patent ID: 6177336
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate, having an isolation structure to isolate the MOS transistor, the method comprising:sequentially forming a gate oxide layer, a polysilicon layer, and a cap layer on the substrate so as to form a first-stage gate on the substrate;forming an interchangeable source/drain region at each side of the first-stage gate in the substrate forming an insulating layer over the cap layer;performing a planarization process to expose the cap layer;removing the cap layer to form an opening that exposes the polysilicon layer;performing a self-aligned selective local implantation process, using the insulating layer as a mask; andfilling the opening with a conductive layer to form a gate structure on the substrate, wherein the conductive layer consequently replaces the cap layer of the first-stage gate structure, and wherein a preliminary conductive layer is formed over the substrate to fill the opening and a planarization process removes the preliminary conductive layer so that a remaining portion of the preliminary conductive layer is the conductive layer filling the opening.