Patent ID: 9054228
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A semiconductor package comprising: a first semiconductor chip comprising a plurality of through-silicon vias (TSVs); a plurality of connection terminals on a first surface of the first semiconductor chip and respectively connected to the plurality of TSVs; a second semiconductor chip on a second surface of the first semiconductor chip; a thermal interface material (TIM) layer on the first semiconductor chip and in contact with side surfaces of the second semiconductor chip; a heat spreader on the second semiconductor chip and the TIM layer; a substrate on the first surface of the first semiconductor chip such that the first semiconductor chin is disposed between the second semiconductor chip and the substrate; and an underfill layer between the first semiconductor chip and the substrate, wherein side surfaces of the first semiconductor chip, the TIM layer, and the heat spreader are substantially coplanar with each other, wherein an edge portion of the first surface of the first semiconductor chip comprises a recess defined by a portion of a scribe lane, wherein the side surface of the first semiconductor chip terminates at the recess, and wherein the underfill layer only partially extends on the side surface of the first semiconductor chip.