Patent ID: 8010916
Filing Date: 2011-08-30
Classification: G06F,Y02P

Abstract:
1. A method for estimating a test yield for a semiconductor product, said method comprising: estimating, by a computer and based on critical area analyses, both a front end of line faults sensitivity for each library element in a set of library elements identified in an inventory and a shorts sensitivity for each library element in said set of library elements; selecting, by said computer and based at least on requirements for said product, at least two library elements from said set to form said product; estimating, by said computer, a wiring faults sensitivity for said product as formed by said at least two library elements; and computing, by said computer, a test yield estimate for said product based on said front end of line faults sensitivity for each of said at least two library elements, said shorts sensitivity for each of said at least two library elements and said wiring faults sensitivity for said product.