Patent ID: 6239023
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method of forming conducting lines within a damascene structure, consisting of:providing a semiconductor substrate;forming damascene metal plugs within said semiconductor substrate;depositing a layer of intra-level dielectric over said semiconductor substrate;patterning and etching said layer of intra-level dielectric, said patterning and etching said layer of intra-level dielectric creating a pattern of intra-dielectric openings, said openings being aligned with said damascene plugs, creating damascene metal wiring openings, further creating additional intra-level dielectric openings adjacent to said damascene metal wiring openings for created damascene metal wiring openings that have no adjacent damascene metal wiring openings as measured in a direction that is perpendicular to a longitudinal direction of said damascene metal wiring openings, no adjacency being determined by a lack of damascene metal wiring openings over a distance not exceeding twice a width at a top of a cross section of said damascene metal wire openings, said additional intra-level dielectric openings being created adjacent to said damascene metal wire openings, said adjacency being on one or both sides of said damascene metal wire openings;depositing a layer of metal over said patterned intra-level dielectric and over exposed surface of said semiconductor substrate; andplanarizing said layer of metal, creating a damascene pattern.