Patent ID: 6281709
Filing Date: 2001-08-28
Classification: H03K

Abstract:
A logic interface on a semiconductor chip for coupling an on-chip logic input signal to an off-chip output, comprising:a fuse option coupled to the logic input signal; anda logic circuit includinga pull-up transistor coupled to the output and to a supply voltage, the pull-up transistor having a gate coupled to the fuse option such that the supply voltage is totally disconnected from the output regardless of the state of the input signal when the fuse option is in a first state, and the supply voltage is connected to the output in response to the input signal when the fuse option is in a second state;a pull-down transistor coupled to the output and to a reference potential, the pull-down transistor being permanently connected to input signal such that the reference potential is connected to the output in response to the input signal regardless of the state of the fuse option.