Patent ID: 6403466
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit comprising:a substrate having a device provided thereon; forming a dielectric layer over the substrate; forming an opening in the dielectric layer; depositing a barrier layer to line the opening; depositing a seed layer over the barrier layer; depositing a conductor core layer over the seed layer, filling the opening in the dielectric layer; removing the seed layer and barrier layer above the dielectric layer with a first chemical-mechanical process; depositing a conductive layer over the conductor core layer wherein any voids or dishing in the conductor core are filled; and removing the conductive layer above the dielectric layer with a second chemical-mechanical polishing process wherein the second chemical-mechanical polishing process is a combination of electropolishing and abrasiveless CMP with very low mechanical pressure which is less abrasive than the first chemical-mechanical polishing process.