Patent ID: 6778459
Filing Date: 2004-08-17
Classification: G11C

Abstract:
A circuit for generating an antifuse read sequence in a memory device, comprising:an antifuse read control for generating a first read signal in response to a first memory read command and a second read signal in response to a second memory read command; at least one input operably coupled to the antifuse read control for conducting a command signal to the antifuse read control; a first output operably connected to the antifuse read control for conducting the first read signal from the antifuse read control in response to the first memory read command conducted to the antifuse read control through the at least one input; and a second output operably connected to the antifuse read control for conducting the second read signal from the antifuse read control in response to the second memory read command conducted to the antifuse read control through the at least one input.