Patent ID: 8700845
Filing Date: 2014-04-15
Classification: G11C,H04L

Abstract:
1. A system having a plurality of memory devices, the system comprising: a first memory device and a second memory device of the plurality of memory devices; a first shift register of the first memory device to receive serial address and command information at a first memory input pin of the first memory device, the first shift register being configured to couple in parallel to a first shift register of the second memory device and first shift registers of any other remaining memory devices of the plurality of memory devices to receive serial address and command information in parallel with the first shift register of the first memory device; and a second shift register of the first memory device to receive data only at a second memory input pin of the first memory device and shift the data to provide shifted data at a memory output pin of the first memory device, the shifted data from the memory output pin to be communicated to a second shift register of the second memory device.