Patent ID: 9153479
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A device comprising: a semiconductor substrate; at least three conducting features embedded into the semiconductor substrate, wherein each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3), wherein the first conducting feature has a top surface facing away from the semiconductor substrate; a first barrier layer separating the semiconductor substrate and the first conducting feature; a second barrier layer formed over the top surface of the first conducting feature and extending beyond the first barrier layer into the semiconductor substrate such that the second barrier layer extends into the semiconductor substrate at a greater depth than the first barrier layer; and a gap structure isolating the first and second conducting features.