Patent ID: 6581112
Filing Date: 2003-06-17
Classification: G06F

Abstract:
A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory, such random access memory and DMA receiver being coupled to a central processing unit by a bus, such central processing unit being coupled to a local cache memory, the source of such data providing an address for the data, such address being the location the random access memory where the data is to be stored, such DMA receiver, comprising:an address register; a first data register; a duplicate data register having an input coupled to an output of the first data register; a selector having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register, such selector coupling one of the pair of inputs to an output thereof selectively in accordance with a select signal; a state machine, response to a receive write enable signal from the source, for: loading the address into the address register and loading the data into the first data register; transferring the data onto the bus for storage in the random access memory at the address loaded into the address register and checking to determine whether the data corresponding to the address being written into the random access memory is currently stored in the local cache memory; and transferring the data in the first data register into the duplicate data register; wherein if the data is located in the local cache memory, the state machine waits for the central processing unit to copy data in the local cache memory to the addresses in the random access memory, produce the select signal to couple the data in the duplicate data register to the bus, and overwrite the data in the local cache memory with the data provided on the bus by the duplicate data register.