Patent ID: 7990484
Filing Date: 2011-08-02
Classification: G02F,H01L

Abstract:
1. A method of fabricating a thin film transistor array panel, the method comprising: forming a gate line assembly and a storage capacitor line assembly on an insulating substrate such that the gate line assembly has a gate line and a gate electrode; forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor line assembly; forming a semiconductor pattern on the gate insulating layer; forming a data line assembly and a storage capacitor conductive pattern on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has a data line, a source electrode and a drain electrode, and the storage capacitor conductive pattern are partially overlapped with the storage capacitor line assembly to thereby form a first storage capacitor; forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern; forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive pattern, respectively; and forming a pixel electrode on the passivation layer such that the pixel electrode is connected to the drain electrode and the storage capacitor conductive patterns through the first and the second contact holes while forming a second storage capacitor in association with parts of the storage capacitor lines assembly, wherein the storage capacitor conductive pattern has an island shape.