Patent ID: 6521477
Filing Date: 2003-02-18
Classification: B81B,H01L,Y10S

Abstract:
A method for vacuum packaging integrated circuit devices, comprising:forming on a device wafer a plurality of integrated circuit devices; forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices; forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings; forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings; aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and mating the device wafer with the lid wafer in a vacuum environment to form a vacuum package within each of the plurality of first sealing rings and second sealing rings, each vacuum package enclosing one or more of the plurality of integrated circuit devices.