Patent ID: 6232833
Filing Date: 2001-05-15
Classification: H03F

Abstract:
In a class D amplifier with a bridge circuit, a low jitter circuit comprising in combination:a pulse width modulator;a driver circuit coupled between the pulse width modulator and a MOSFETs bridge circuit for controlling gates of the MOSFETs in the bridge circuit;the MOSFETs bridge circuit comprising high and low side MOSFETs in series with each other and connected to the driver circuit and between high and low voltage power;a dead time circuit connected between high and low power supply rails and having a RC time delay circuit for delaying the turn on of one of the MOSFETs;a logic circuit coupled to the dead time circuit and having a pair of latches to use the RC time delay to set both turn on delays of the MOSFETs;a pair of latches for rapidly turning off the other MOSFET; andpositive and negative shunt current regulators, said positive shunt current regulator configured for connecting to the high power supply rail, said negative shunt current regulator configured for connecting to said low power supply rail, said positive and negative shunt current regulators for removing ripple from said high and low power supply rails.