Patent ID: 7892958
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate insulation film on a substrate including memory cell and peripheral circuit regions; forming a first doped silicon layer on the gate insulation film in the memory cell region and a first-conductivity transistor region of the peripheral circuit region; forming a first metal layer on the gate insulation film of a second-conductivity transistor region of the peripheral circuit region; forming a second doped silicon layer on the first doped silicon layer and the first metal layer; and patterning the first metal layer, and the first and second doped silicon layers to form a first gate structure comprising the first and second doped silicon layers in the memory cell region and first-conductivity transistor region of the peripheral circuit region and to form a second gate structure comprising the first metal layer and the second doped silicon layer in the second-conductivity transistor region of the peripheral circuit region.