Patent ID: 7244668
Filing Date: 2007-07-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a gate and source/drain regions on a semiconductor substrate, spacers at both sides of the gate, and isolation layers defining the source/drain regions; chemisorbing a transition metal source onto a surface of the substrate and forming a transition metal mono-layer on the gate and source/drain regions; chemisorbing a semiconductor source onto the transition metal mono-layer and forming a semiconductor mono-layer; repeating the formation of the transition metal mono-layer and the semiconductor mono-layer; annealing the substrate to form a C-54 phase silicide layer; and patterning the C-54 phase silicide layer to remain on the upper surfaces of the gate and source/drain regions, wherein the patterning includes forming a mask pattern by photolithography to mask the silicide layer on the gate and source/drain regions and dry etching the silicide layer using the spacers and the isolation layers as an etch stop layer.