Patent ID: 9041203
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A semiconductor device comprising: a terminal metal layer, wherein said terminal metal layer comprises a pad to couple said semiconductor device to another semiconductor device; a first layer and a second layer, wherein said first and said second layer are below said terminal metal layer; a third layer, wherein said third layer comprises a plurality of data storage elements, wherein each data storage element of said plurality of data storage elements is accessible to a different bitline positioned at different layers; and a plurality of bitlines wherein a first portion of said plurality of bitlines is in said first layer and a second portion of said plurality of bitlines is in said second layer, and wherein said first layer and said second layer are adjacent, wherein said first portion of said plurality of bitlines is further in said second layer and wherein said second portion of said plurality of bitlines is further in said first layer, wherein said first portion and said second portion of said plurality of bitlines switch layers over one or more sectors, wherein each sector has a different sector select area, and wherein a first portion of a first bitline of said first portion of said plurality of bitlines in said second layer comprises a first sub-portion of a first width and a second sub-portion of a second width.