Patent ID: 6801986
Filing Date: 2004-10-05
Classification: G06F

Abstract:
A method for executing a load locked and a store conditional instruction in a processor, comprising:executing the load locked instruction to read a memory block, and said processor in response to executing the load locked instruction issuing a read modify system command to read said block and to take ownership of said block by said processor, and also setting a lock flag for the address of said memory block, and writing a value of said memory block into a cache of said processor as a cache copy of said memory block; resetting said lock flag upon receipt of an invalidate message for said cache copy of said memory block, if any said invalidate messages are received by said processor; waiting for a selected time interval before said processor surrenders ownership of said memory block upon receipt of an ownership request message, if any is received by said processor after execution of said load locked instruction; executing the store conditional instruction, and said processor in response to executing said store conditional instruction testing said lock flag, and if said lock flag is set, writing to said cache copy of said memory block.