Patent ID: 6188599
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A ferroelectric memory having a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines, the ferroelectric memory comprising:a main cell array having a plurality of main cells, each main cell being coupled to corresponding wordline, plateline and bitline;a reference cell array having a plurality of reference cells, each reference cell being coupled to corresponding wordline, plateline and reference bitline;a sense amplifier array having a plurality of sense amplifiers for sensing data on each bitline and each reference bitline;a driver for providing driving signals to the wordlines and the platelines;a switching unit for selective connection of the bitlines and the reference bitline to input/output nodes and reference nodes, respectively, on the sense amplifier array; anda pull-up transistor for pulling-up a level of the reference bitline to a level of a supply voltage.