Patent ID: 7211827
Filing Date: 2007-05-01
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a plurality of gate lines formed on a substrate and including a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a plurality of data lines formed at least on the semiconductor layer; a plurality of drain electrodes separated from the data lines; a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes; a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the second insulating layer, and arranged alternate to the pixel electrodes, each common electrode having an edge spaced apart from an edge of the pixel electrodes and substantially parallel to the edge of the pixel electrodes, wherein the common electrodes of adjacent pixel areas are connected to each other.