Patent ID: 6804158
Filing Date: 2004-10-12
Classification: G11C

Abstract:
A semiconductor memory device once setting an operation state to a reset state according to change in an operation cycle during a normal mode, and altering an operation node of a region specified by an address according to change in said address, said semiconductor memory device comprising:a memory cell array including a plurality of memory cells; an operation node to select said memory cell; and an activation circuit selectively activating said operation node according to said address by altering a potential on said operation node to a predetermined potential, wherein said activation circuit alters, in a special mode, the potential on said operation node to said predetermined potential according to a sequence differing from the sequence of altering the potential on said operation node to said predetermined potential in said normal mode, and said activation circuit comprises a driver including a power supply node, and activating said operation node, a first transistor connected between said power supply node and a first node receiving a first power supply potential, and a second transistor connected between said power supply node and a second node receiving a second power supply potential lower than said first power supply potential.