Patent ID: 8239724
Filing Date: 2012-08-07
Classification: G06F

Abstract:
1. An apparatus for error correction for a data storage device, comprising: an input interface that is arranged and configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, wherein each of the channel controllers is arranged and configured to control operations associated with one or more memory chips, wherein the input interface comprises: a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction on the single request stream using an error correction algorithm and the error correction information to generate correction solutions, wherein the corrector module is a shared resource for the multiple channel controllers; and an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers, wherein the output interface comprises expander logic circuitry that is configured to de-serialize the correction solutions and to broadcast the correction solutions to the channel controllers.