Patent ID: 6182263
Filing Date: 2001-01-30
Classification: G11B,H03M,H04L

Abstract:
sup.th to a (N-1)-th column according to a sequence of data transmission and sequentially from a 0.sup.th to a (M-1)-th row according to the sequence of data transmission;means for permitting a matrix block of (K.times.M) rows.times.N columns to exist, the matrix block including K of the information data blocks arranged sequentially according to the sequence of data transmission;means for adding a first error correcting check word of K bytes to each column of (K.times.M) bytes of the matrix block to turn each of the N columns into a Reed-Solomon code word C2 of (K.times.(M+1)) bytes, the error correcting check word of K bytes existing on a byte by byte basis at a position corresponding to every M bytes of information data; andmeans for adding a second error correcting check word of P bytes to each row of N bytes to turn each of the (K.times.(M+1)) rows into a Reed-Solomon code word C1 of (N+P) bytes, wherein:the error correcting product code block is a Reed-Solomon error correcting product code block of (K.times.(M+1).times.(N+P)) bytes having an information section of K of the information data blocks of (K.times.M.times.N) bytes, anda sum of (M.times.N) bytes of an information data block and an average number of bytes of a check word added thereto are held to a constant value of (M+1).times.(N+P) bytes.