Patent ID: 6194915
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a first line to which a first voltage is supplied;a second line to which a second voltage, lower than the first voltage, is supplied;a third line;a fourth line;a p-channel MISFET having a source coupled to the first line, a drain and a gate, wherein a substrate potential of the p-channel MISFET is supplied from the third line;an n-channel MISFET having a source coupled to the second line, a drain coupled to the drain of the p-channel MISFET and a gate, wherein a substrate potential of the n-channel MISFET is supplied from the fourth line;a first switching MISFET of a p-channel type having a source coupled to the third line and a drain coupled to the first line, wherein the first switching MISFET is turned on in a first operation mode in which the substrate potential of the p-channel MISFET is determined based on the first voltage being applied on the first line, and wherein the first switching MISFET is turned off in a second operation mode in which the substrate potential of the p-channel MISFET is determined based on a third voltage, higher than the first voltage, being applied to the third line,a second switching MISFET of an n-channel type having a source coupled to the fourth line and a drain coupled to the second line, wherein the second switching MISFET is turned on in the first operation mode in which the substrate potential of the n-channel MISFET is determined based on the second voltage being supplied to the second line, and wherein the second switching MISFET is turned off in the second operation mode in which the substrate potential of the n-channel MISFET is determined based on a fourth voltage, lower than the second voltage, being applied on the fourth line.