Patent ID: 6022788
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A method of forming an isolation region in an integrated circuit comprising the steps of:forming at least one trench in a surface of a semiconductor substrate so that the surface has at least two high regions and at least one low region thereof;forming a layer of oxide on the at least two high regions and on the at least one low region of the substrate;forming a sacrificial layer of nitride on the oxide layer;partially removing outer surface portions of the nitride layer by partially etching back the nitride layer so as to leave a relatively thin layer of nitride overlying the at least one high region and a relatively thicker nitride spacer overlying sidewall regions of the at least one trench; andremoving the remaining portions of the nitride layer and portions of the oxide layer so that other portions of the oxide layer remain overlying the at least one low region of the substrate and so that an outer surface of the at least two high regions and the at least one filled trench in combination provide a substantially planar surface.