Patent ID: 7350180
Filing Date: 2008-03-25
Classification: G06F

Abstract:
1. A method of deriving an absolute clock edge to be used when an inherited clock context is encountered in HDL source code that is input to a translation tool, comprising: (a) providing a tokenizer means, (b) providing source code that comprises an HDL function and which said tokenizer partitions into a sequence of tokens, (c) providing a parser means which: (d) performing elaboration processing which traverses said node tree using said node references, and which comprises performing an inheritance search if the processing encounters a clock context node with an associated inherited edge, (e) starting said inheritance search from the encountered node or search node and moving up said node tree from said search node using said node references until a higher controlling clock context node or controlling node is found, (f) obtaining a found clock edge associated with the found controlling node, (g) obtaining a derived edge for said search node, said derived edge being an absolute edge, and the derivation using said found clock edge and said inherited edge associated with said search node, whereby an inherited clock context can direct subsequent processing of statements under its control in order to instantiate storage elements with state changes that occur on the clock context's derived edge, and whereby functions that use inherited clock contexts can be used in circuit designs selected from the group of rising edge and falling edge and both edges.