Patent ID: 6118313
Filing Date: 2000-09-12
Classification: H03K

Abstract:
A digital frequency-multiplying circuit comprising:a plurality of cascaded first delay circuits;each of said first delay circuits including a plurality of cascaded delays,a first delay circuit of the cascaded first delay circuits receiving an input signal to be frequency-doubled,a logic circuit receiving said input signal and a delayed output signal outputted from at least the first delay circuit of said cascaded first delay circuits, for generating a frequency-multiplied signal;a delay amount discriminating means receiving a first delayed output signal outputted from a final first delay circuit of said cascaded first delay circuits and another delayed output signal from said first delay circuit of said cascaded first delay circuits for discriminating at a transition timing of said input signal, whether said frequency-multiplied signal advance or delays in obtaining optimum duty ratio; anda delay amount control means responding to the result of the discrimination of said delay amount discriminating means for generating a delay control signal optimizing a delay amount of said cascaded first delay circuits.