Patent ID: 6229752
Filing Date: 2001-05-08
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit device having a memory and a data bus for coupling with a CPU on a semiconductor substrate, said memory comprising:a memory cell array;a sense amplifier block connected to said memory cell array;a row decoder connected to said memory cell array;a column decoded connected to said sense amplifier block; anda controller for controlling said memory cell array, said row decoder, said column decoder, and said sense amplifier block,wherein said controller holds an address in a memory cycle after another address is entered in the next memory cycle,wherein said controller compares an address in a memory cycle with another address in the next memory cycle and makes the data held in said sense amplifier block output to an outside of said memory without reading data from said memory array when both addresses match as a result of said comparison, andwherein said controller further outputs a signal, which indicates readiness for data outputting to said data bus and data writing to said memory via said data bus, to said CPU.