Patent ID: 6252465
Filing Date: 2001-06-26
Classification: H03L

Abstract:
A phased locked loop (PLL) circuit comprising:a voltage controlled oscillator generating an oscillation clock having a frequency and including a plurality of first variable delay stages;a delay unit for outputting a first delay signal having a frequency and a phase, with a delay according to the frequency of said voltage controlled oscillator, of input data and including a plurality of second variable delay stages, said first and second variable delay stages being identical and respectively connected in cascade, wherein a delay control current supplied to switch sections of said first variable delay stages of said voltage controlled oscillator is also input to switch sections of said second variable delay stages;a latching unit for outputting a second delay signal having a frequency and a phase, by latching the input data according to the oscillation clock output by said voltage controlled oscillator; anda phase comparing unit for comparing the phase of the first delay signal to the phase of the second delay signal.