Patent ID: 7826578
Filing Date: 2010-11-02
Classification: G06F

Abstract:
1. A data processing system comprising: an input data port for receiving input data samples asynchronous to a native clock signal and having an input sample rate controlled by a first received sampling clock signal; first retiming circuitry for synchronizing the first received sampling clock signal with the native clock signal to generate a first synchronized sampling clock signal; a first sample rate converter for converting the input data samples from the input sample rate to another sample rate synchronous with a rate of the native clock signal, wherein the input data samples are clocked into the first sample rate converter by the first synchronized sampling clock signal and the another sample rate is selectively increased and decreased relative to the input sample rate sample rate by a selected one of integer and fractional multiples of the rate of the native clock signal; a data converter for converting data samples output from the first sample rate converter to another format; an analog to digital converter for converting an analog signal into output data samples with a sample rate synchronous with the rate of the native clock signal; second retiming circuitry for synchronizing a second sampling clock signal with the native clock signal to generate a second synchronized sampling clock signal; a second sample rate converter for converting the sample rate of the output data samples from the sample rate synchronous with the rate of the native clock signal to an output sample rate, wherein the output data samples are clocked out of the second sample rate converter by the second synchronized sampling clock signal and the output sample rate is selectively increased and decreased relative to the sample rate by a selected one of integer or fractional multiples of the rate of the second synchronized sampling clock signal; and an output port for outputting the output data samples in response to the second received sampling clock signal such that output data samples are asynchronous to the native clock signal.