Patent ID: 6741520
Filing Date: 2004-05-25
Classification: G11C

Abstract:
An integrated circuit memory device having a synchronizing clock signal and including a plurality of external data input paths, said memory device comprising:a write data sort circuit for loading data applied to said external data input paths on a first transition of said synchronizing clock signal to either a first or second internal data path and alternatively loading data applied to said external data input paths on a second opposite transition of said synchronizing clock signal to the opposite one of said first or second internal data paths; a data-in sort clock circuit for operatively controlling said write data sort circuit and receiving said synchronizing clock signal and a data strobe signal for causing said write data sort circuit to latch said data on said first and second data paths when an internal write clock signal is active and to pass said data on said first and second data paths to respective internal output nodes when said internal write clock signal is not active.