Patent ID: 8996348
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A computer implemented method for conducting fault sensitivity analysis of a digitally-calibrated circuit design, the method comprising: receiving a fault free digitally-calibrated circuit design, a fault, a fault interval time period, and a calibration interval time period; simulating calibration of the fault free digitally-calibrated circuit design; simulating calibration of the fault free digitally-calibrated circuit design with the fault integrated into an analog portion of the digitally-calibrated circuit design; simulating a circuit response of the fault free digitally-calibrated circuit design with a circuit simulator from after the calibration of the fault free digitally-calibrated circuit design until the end of the fault interval time period; simulating the fault free digitally-calibrated circuit design with the fault from the beginning of the fault interval time period until the end of the fault interval time period; and determining whether the fault is detectable.