Patent ID: 6275905
Filing Date: 2001-08-14
Classification: G06F

Abstract:
A multiprocessing computer system comprising:a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes:a first processing node configured to generate a read command to read a designated memory location in a memory associated with a second processing node,wherein said second processing node configured to receive said read command and to responsively transmit a probe command to each of at least one remaining processing node in said plurality of processing nodes regardless of whether a copy of said designated memory location is cached within any of said at least one remaining processing node, and to responsively transmit a first read response to said first processing node including a first data packet containing data from said designated memory location,wherein said at least one remaining processing node includes a third processing node configured to transmit, in response to said probe command and upon detecting a modified copy of said designated memory location cached within said third processing node, a memory cancel response to said second processing node and a second read response to said first processing node, said second read response including a second data packet containing said modified copy of said designated memory location, andwherein said memory cancel response causes said second processing node to cancel transmission of said first read response to said first processing node.