Patent ID: 7420859
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A memory device comprising: a memory array having a plurality of memory regions, each memory region comprising a plurality of rows of memory cells; a plurality of data path access units, each data path access unit being associated with at least one memory region, and being operable to access the memory cells in the associated at least one memory region; each memory region having at least one associated memory region selected from said plurality of memory regions such that the data path access unit associated with that memory region is different to the data path access unit associated with the at least one associated memory region; the memory array providing a plurality of redundant rows for use in place of any faulty row in the memory array, for each memory region any redundant row used in place of a faulty row in that memory region being provided in said at least one associated memory region; storage for maintaining a record identifying each faulty row and the redundant row to be used in place of that faulty row; control logic operable for a read access request specifying a read address to cause a lookup operation to be performed in order to obtain read data, the lookup operation being performed in both the memory region identified by that read address and the at least one associated memory region; the control logic further comprising comparison logic for performing a comparison operation to determine with reference to said storage whether said read address corresponds to one of said faulty rows as identified in said record; the control logic further being operable to cause to be output the read data obtained from the memory region identified by said read address if the comparison operation determines that said read address does not correspond to one of said faulty rows, but otherwise to cause to be output the read data obtained from the associated memory region containing the redundant row identified in said record.