Patent ID: 6316727
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A multi-chip semiconductor package, comprising:a first chip having a first surface and a second surface, the first surface having a plurality of first bonding pads;a second chip having a third surface and a fourth surface, the third surface having a plurality of second bonding pads;a lead frame comprising a die pad and a plurality of leads, the die pad having a fifth surface and a sixth surface, and the leads have an inner portion and an outer portion, wherein the fifth surface is attached to the second surface, and the sixth surface is attached to the third surface, and the die pad has an area smaller than that of the first chip and the second chip so as to expose the second bonding pads;a plurality of wires, respectively coupling the first bonding pads and the second bonding pads to the inner portion of the leads; anda packaging material in which the first chip, the second chip, and the inner portion of the leads are sealed.