Patent ID: 7260753
Filing Date: 2007-08-21
Classification: G01R,G11C

Abstract:
1. A test interface for providing test access by synchronous test equipment to an asynchronous circuit, the test interface comprising: synchronous-to-asynchronous (S2A) conversion circuitry operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data; asynchronous logic operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit, the asynchronous output data resulting from application of the asynchronous input data to the asynchronous circuit, operation of the asynchronous logic being synchronized at least in part with a clock signal associated with the synchronous test equipment; and asynchronous-to-synchronous (A2S) conversion circuitry operable to receive the asynchronous output data from the asynchronous logic, convert the asynchronous output data to synchronous output data, and serially transmit the synchronous output data to the synchronous test equipment; wherein the asynchronous logic comprises a shift register which is operable alternately to receive the asynchronous input data serially from the S