Patent ID: 6509218
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A front stage process of a fully depleted SOI device, comprising:providing an SOI substrate comprising an insulation layer and a crystalline silicon layer above the insulation layer; forming an isolation layer in the crsytalline silicon layer that defines a first type MOS active region and is connected to the insulation layer; forming an epitaxial suppressing layer above the crystalline silicon layer on the outside of the first-type active region; selectively forming a second type doped epitaxial silicon layer above the crystalline silicon layer in the first type MOS active region, wherein the second type doped epitaxial silicon layer is formed in-situ; selectively forming an undoped epitaxial silicon layer above the second type doped epitaxial silicon layer; and removing the epitaxial suppressing layer.