Patent ID: 6622242
Filing Date: 2003-09-16
Classification: G06F

Abstract:
For generating an array output signal representing an array output data word in response to a rearrangement input signal and an array input signal representing an array input data word, a functional unit comprising:A) a series of J stages Sj of selector modules, where 0&lE;j&lE;Jâˆ’1, with each of which is associated a respective stage input data word and a respective stage output data word, the stage input data word associated with stage S0 being the array input data word, the stage input data word associated with each other stage Sj being the stage output data word associated with stage Sjâˆ’1, the array output data word being the stage output data word associated with stage SJâˆ’1, each data word comprising a respective ordered set of N data units Dn, where n=0, 1, 2, . . . , Nâˆ’1, each stage comprising N selector modules Mn, where n=0, 1,2 . . . , Nâˆ’1, each module Mn in a stage receiving, as its pass input data unit, data unit Dn of the stage input data word associated with that stage and generating, as its module output data unit, data unit Dn of the stage output data word associated with that stage, whereby each selector module Mn in a stage is associated with the respective data unit Dn in the stage output data word associated with that stage and is also associated with the corresponding data unit Dn in the stage input data word associated with that stage, at least one of the stages being a shuffle stage, at least one other stage being an unshuffle stage, wherein: i) each stage is associated with a respective subgroup size; ii) the selector modules of each unshuffle stage form unshuffle subgroups of s consecutive selector modules, where s is the subgroup size associated with that unshuffle stage, and the stage input and output data words associated with that stage thereby form respective sets of unshuffle subgroups of the data units associated with those selector modules; iii) the selector modules of each shuffle stage form shuffle subgroups of s consecutive selector modules, where s is the subgroup size associated with that shuffle stage, and the stage input and output data words associated with that stage thereby form shuffle subgroups of the data units associated with those selector modules; iv) the selector modules in each unshuffle stage are connected to receive as respective unshuffle input data units the data units so selected from the stage input data word associated with that stage that, when those selector modules forward their unshuffle input data units as their respective module output data units, the stage output data word associated with that stage is the result of unshuffling the unshuffle subgroups of the stage input data word associated with that stage; and v) the selector modules in each shuffle stage are connected to receive as respective shuffle input data units the data units so selected from the stage input data word associated with that stage that, when those selector modules forward their shuffle input data units as their respective module output data units, the stage output data word associated with that stage is the result of shuffling the shuffle subgroups of the stage input data word associated with that stage; and B) a control circuit that interprets at least a plurality of the rearrangement input signal's possible values as calling for shuffle/unshuffle operations employing different selected combinations of the stages and so controls the stages in response to the rearrangement input signal that, when the rearrangement input signal assumes one of the values in that plurality: i) each selector module in an unshuffle stage forwards its unshuffle input data unit as its module output data unit when the selected combination of stages called for by the rearrangement input signal includes that stage; ii) each selector module in a shuffle stage forwards its shuffle input data unit as its module output data unit when the selected combination of stages called for by the rearrangement input signal includes that stage; and iii) each selector module in a stage forwards its pass input data unit as its module output data unit when the selected combination of stages called for by the rearrangement input signal excludes that stage.