Patent ID: 8400576
Filing Date: 2013-03-19
Classification: G02B,G02F,G09G,H01L

Abstract:
1. A method of producing a pixellated display device including a display medium, an array of transistors, addressing lines for controlling the transistors, and an array of pixel electrodes located at least partly between the array of transistors and the display medium and via which respective portions of the display medium are controllable by the transistors, wherein each pixel electrode is controllable through a respective transistor via one of said addressing lines and also overlaps with another of said addressing lines and/or a counter electrode connected thereto for capacitive coupling therewith, wherein each transistor is a thin-film transistor including source, drain and gate electrodes, and wherein each pixel electrode is connected to one of the underlying source or drain electrodes of the respective transistor via a conductive vertical interconnect through one or more insulator layers, and wherein the method comprises defining in said one or more insulator layers holes that extend down to the underlying source or drain electrodes using a photoablative technique that discriminates between the underlying source or drain electrodes and said one or more insulator layers; and then depositing conductive material in said holes.