Patent ID: 6472265
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A method of manufacturing an embedded DRAM, which is suitable for a substrate having a memory cell region and a logic circuit region, wherein a plurality of gate conductors are formed on the substrate in the memory cell region and the logic circuit region, and a spacer is formed on a sidewall of each gate conductor, the method comprising:forming an epitaxy layer on the exposed substrate to serve as source/drain regions in the logic circuit region and a source region and a drain region in the memory cell region; forming a silicide layer on the source/drain regions in the logic circuit region and the source region and the drain region in the memory cell region; forming a conformal barrier layer over the substrate; forming a dielectric layer over the substrate to cover the gate conductors; performing a first etching step to remove a portion of the dielectric layer over the silicide layer to form a plurality of contact openings using the barrier layer as an etching stop layer; performing a second etching step to remove a portion of the barrier layer until a portion of the silicide layer is exposed; and forming a plurality of metal plugs in the contact openings.