Patent ID: 7032092
Filing Date: 2006-04-18
Classification: G06F

Abstract:
1. A memory controller for supporting different memory modes, the memory controller comprising: a determining device for determining a memory mode, the determining device generating a memory selection signal; a memory writing device using the memory selection signal to provide a data selection signal, wherein the data selection signal is chosen from a first clock signal or a second clock signal, the memory writing device further providing a data mask signal, wherein the data mask signal is chosen among a byte mask signal, a third clock signal, or a fourth clock signal, the memory writing device still further providing a memory data signal, wherein multiunit data are adapted to be carried therein, the memory data signal being controlled by the fourth clock signal or a fifth clock signal; and a memory reading device for receiving the data selection signal, the data mask signal, and a reference voltage, the memory reading device providing at least one differential signal and choosing one differential signal based upon the memory selection signal and delaying the one differential signal for a predetermined time period for locking data on the memory data signal.