Patent ID: 9128871
Filing Date: 2015-09-08
Classification: G06F,G11C

Abstract:
1. A non-volatile memory based solid state storage system comprising: a printed circuit board; a plurality of non-volatile memory chips mounted to the printed circuit board, each non-volatile memory chip divided into planes, each plane divided into blocks, each block divided into pages, and each page including a plurality of non-volatile memory cells arranged to store a page of digital data, the plurality of non-volatile memory chips divided into lanes, each lane having a predefined number greater than one non-volatile memory chips, each non-volatile memory chip including a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, non-volatile memory cells within the non-volatile memory chip; and a system controller mounted to the printed circuit board, the system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the non-volatile memory chips of each lane nearly simultaneously, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system; wherein the system controller is configured to store data received over the external communications bus in the plurality of non-volatile memory chips in the form of page stripes, each page stripe comprising a plurality of pages stored in the non-volatile memory chips, each of the plurality of pages being stored in a non-volatile memory chip that is different from, but in the same plane and block as, each of the non-volatile memory chips in which the other pages within the page stripe are stored, the plurality of pages making up each page stripe including: the page stripes stored by the system controller including: a first page stripe stored within the plurality of non-volatile memory chips, the first page stripe having N data pages and one data protection page, where N is an integer greater than three; and a second page stripe stored within the plurality of non-volatile memory chips, the second page stripe having M data pages and one data protection page, where M is an integer less than N, wherein each of the data pages within the second page stripe is stored within a non-volatile memory chip of a lane that also stores data from a data page within the first page stripe.