Patent ID: 7764715
Filing Date: 2010-07-27
Classification: H03M,H04J,H04L

Abstract:
1. A circuit for multiplexing a plurality of data signals into an output data stream comprising: a plurality of circuit elements, wherein a transition of each circuit element of said plurality of circuit elements is clocked by a first clock signal received from a source other than one of the plurality of circuit elements, wherein an output of each circuit element of said plurality of circuit elements comprises an individual data signal of said plurality of data signals and wherein said first clock signal is in-phase with said transition; a selector coupled to said plurality of circuit elements for receiving each of the individual output data signals from the plurality of circuit elements and for sequentially selecting each of said individual data signals to generate said output data stream as the output of the selector, wherein said selector is clocked to control said selecting by a second clock signal received from a source other than one of the plurality of circuit elements, wherein said second clock signal is out of phase with respect to said first clock signal by a fixed offset; and a compensator that is separate from the plurality of circuit elements coupled to said selector for compensating for a clock-to-data delay corresponding to said transition of each said circuit elements, wherein said second clock signal is transmitted to said selector through said compensator, and wherein said compensator retards said second clock signal to said selector by a compensating delay corresponding to said clock-to-data delay.