Patent ID: 7215565
Filing Date: 2007-05-08
Classification: G11C

Abstract:
1. A method for operating a passive-matrix addressable ferroelectric or electret memory device wherein said memory device comprises: one or more arrays or matrices with memory cells in the form of a ferroelectric or electret thin-film polarizable material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first and second set of respective parallel electrodes, wherein the electrodes of the first set forming word lines in the device, are provided in substantially orthogonal relationship to the electrodes of the second set forming bit lines in the device, wherein the electrodes of said first and second set are provided in direct or indirect contact with the thin-film material of the memory cells, whereby a polarization state in individual memory cells can be read, erased or written by applying appropriate voltages to the individual electrodes of respectively said first and second set of electrodes, wherein the method implements a voltage pulse protocol based on a one-third voltage selection rule whereby non-addressed cells are subjected to disturbing voltages across them not exceeding approximately ⅓ of the switching voltage Vs, wherein the voltage pulse protocol comprises a read cycle and a write/erase cycle respectively with time sequences of voltage pulses of predefined amplitudes, polarities and lengths, wherein the read cycle comprises applying a set of voltage differences to electrodes of respectively said first and second set of electrodes in case data are read out from the memory cells, and wherein the write/erase cycle comprises steps for applying another set of voltage differences to electrodes of respectively said first and second set of electrodes, and wherein the method includes a refresh procedure with the following steps, a) a first step for selecting according to criteria programmed in a memory device controller, one or more cells for refresh and entering the one or more cells thus selected, in a refresh request processed in the controller, b) a second step for monitoring and processing the refresh requests, taking into account ongoing or scheduled memory operations and the priorities assigned thereto, and initiating the refresh procedure, c) a third step for applying simultaneously to the one or more cells selected for refresh a voltage pulse of a defined polarity and a magnitude corresponding to the coercive voltage or higher, while all non-selected memory cells are subjected to zero voltage or a voltage significantly less than the coercive voltage, and d) a fourth step for applying simultaneously to all selected cells a single voltage pulse or a train of voltage pulses, at least one of the voltage pulses having a polarity opposite the defined polarity in step c) and with a magnitude corresponding to the coercive voltage or higher, while all non-selected cells are subjected to zero voltage or a voltage significantly less than the coercive voltage.