Patent ID: 8694689
Filing Date: 2014-04-08
Classification: G06F

Abstract:
1. A storage system, comprising: a plurality of storage devices which are based upon a plurality of logical volumes; and a controller which receives from an external device an I/O (Input/Output) request designating any one among said plurality of logical volumes; wherein: said controller comprises an external interface for receiving the I/O request from said external device, a cache memory for temporarily storing write data included in the I/O request and read data designated by the I/O request, and a plurality of microprocessors; said plurality of microprocessors comprises one or more first processors and one or more second processors; each first processor is a microprocessor whose duty is to perform first processing and not to perform second processing; each second processor is a microprocessor whose duty is to perform the second processing and not to perform the first processing; said first processing includes, upon said I/O request being received by said external interface, analyzing said I/O request, executing processing corresponding to said I/O request, and returning a response for said I/O request to said external device, the processing corresponding to said I/O request including at least one set of operations selected from: said second processing is specific processing, among processing other than said first processing, and includes at least one set of operations selected from: said first processing is performed by each first processor in parallel with said second processing performed by each second processor, said controller includes a local memory; said local memory stores processor type information which includes, for each microprocessor, a processor type value which specifies whether the microprocessor is a first processor or a second processor, and processor utilization rate information which includes a utilization rate for each microprocessor; at least one microprocessor among said plurality of microprocessors is a representative processor; the representative processor performs first changeover decision processing periodically or aperiodically, and in the first changeover decision processing, performs processes (D) through (G) described below: (D) by referring to said processor type information and to said processor utilization rate information, specification of a first utilization rate, which is the utilization rate of a first processor, and a second utilization rate, which is the utilization rate of a second processor; (E) calculation of a first value on the basis of one or more said first utilization rates which have been specified, and a second value on the basis of one or more said second utilization rates which have been specified; (F) comparison of said first value which has been calculated with a first threshold value, and, in response to said first value exceeding said first threshold value, updating of the processor type value which corresponds to one of said second processors from a value which denotes an second processor to a value which denotes a first processor; and (G) comparison of said second value which has been calculated with a second threshold value, and, in response to said second value exceeding said second threshold value, updating of the processor type value which corresponds to one of said first processors from a value which denotes a first processor to a value which denotes a second processor; some microprocessor among said plurality of microprocessors other than said representative processor performs second changeover decision processing periodically or aperiodically, and in the second changeover decision processing, performs processes (H) through (J) described below: (H) comparison of the utilization rate of said microprocessor with a third threshold value; (I) in response to the utilization rate of said microprocessor exceeding said third threshold value and the processor type value which corresponds to said microprocessor denoting a second processor, updating of the processor type value which corresponds to one of said first microprocessors from a value which denotes a first processor to a value which denotes a second processor; and (J) in response to the utilization rate of said microprocessor exceeding said third threshold value and the processor type value which corresponds to said microprocessor denoting a first processor, updating of the processor type value which corresponds to one of said second microprocessors from a value which denotes a second processor to a value which denotes a first processor; and each of the microprocessors performs changeover processing periodically or aperiodically, and in the changeover processing for each microprocessor, in response to the processor type value which corresponds to the microprocessor specifying a processor type which is different from a current processor type of the microprocessor and the first processing or the second processing to be performed by this microprocessor not being completed, the microprocessor performs the non-completed first or second processing.