Patent ID: 6387795
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A wafer-level packaging comprising:providing a wafer that has a plurality of bonding pads formed thereon, an under bump metal (UBM) being respectively formed on the bonding pads that are exposed through a patterned passivation layer formed on the wafer; forming a stress buffer layer that can be patterned on the wafer; patterning the stress buffer layer to form a plurality of first openings and cutting paths, the first openings exposing the under bump metals (UBM); filling a first solder material in the first openings; arranging a mask on the stress buffer layer, wherein the mask has a plurality of second openings communicating with the first openings; filling the second openings of the mask with a second solder material; and reflowing the first and second solder materials to form a plurality of bumps as external connections for the wafer.