Patent ID: 6784019
Filing Date: 2004-08-31
Classification: B82Y,H01L

Abstract:
A method for fabricating a semiconductor package, comprising the steps of:(1) preparing a leadframe, which includes: a die pad having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads arranged around the die pad; (2) performing a first die-attachment process to mount a first semiconductor chip on the downset portion of the die pad; the first semiconductor chip having a substantially rectangularly-shaped active surface formed with a plurality of I/O pads along the shorter sides thereof and an inactive surface adhered to the centrally-located downset portion of the die pad; (3) performing a first wire-bonding pricess to bond a set of bonding wires for electrically connecting the respective I/O pads of the first semiconductor chip to the corresponding leads; (4) performing a second die-attachment process to mount a second semiconductor chip on the die pad; the second semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad so as to form an intercrossedly-stacked dual-chip arrangement with the first semiconductor chip; and (5) performing a second wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the second semiconductor chip to the corresponding leads.