Patent ID: 6321310
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A computer system comprising:a processing system for processing data;a dynamic random access memory for storing data processed by, or to be processed by, the processing system;a memory access controller for controlling access to the dynamic random access memory;at least one data buffer for buffering data to be written to or read from the dynamic random access memory, wherein a number of such data buffers is configurable by the computer system under hardware or software control and wherein an access time of the data buffer is less than an access time of the dynamic random access memory;a burst instruction controller for issuing burst instructions to the memory access controller, the memory access controller being responsive to such a burst instruction to transfer a plurality of data words between the dynamic random access memory and the data buffer in a single data burst, wherein in a data burst a row of memory locations in the memory is selected, and a sequence of accesses local to that row is performed; anda burst instruction queue for queuing burst instructions so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.