Patent ID: 6562647
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A process of fabricating a semiconductor device package comprising:providing a semiconductor wafer comprising a plurality of dice separated by scribe lines, each die comprising a semiconductor device, a surface of a front side of each die comprising a passivation layer and at least one connection pad; attaching a conductive substrate to a back side of the wafer; cutting through the wafer along a scribe line to form a first cut, the first cut exposing the substrate and a side edge of a die, a kerf of the first cut having a first width W1; forming a metal layer which extends from the portion of the conductive substrate exposed by the first cut, along the side edge of the die, and onto at least a portion of the passivation layer; cutting through the conductive substrate along a line that corresponds to the scribe line to form a second cut, a kerf of the second cut having a second width W2 that is smaller than the first width W1 such that at least a portion of the metal layer remains on the side edge of the die and forms a part of a conductive path between the conductive substrate and a location on the front side of the die.