Patent ID: 6306721
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method of forming a salicided polysilicon to metal capacitor as part of a semiconductor device, comprising the steps of:providing a semiconductor substrate as a base for the salicided polysilicon to metal capacitor, an isolation region of field oxide having been provided on the surface of the substrate;forming a layer of polysilicon on the surface of the region of field oxide, patterning and etching said layer of polysilicon, forming a patterned layer of polysilicon overlying said layer of field oxide;saliciding the surface of the patterned and etched layer of polysilicon, forming a first conductor element;depositing a layer of etch stop material over the surface of the region of field oxide, including the surface of the salicided layer of polysilicon;depositing a layer of dielectric over the surface of the layer of etch stop material;depositing a layer of. refractory metal over the surface of the layer of dielectric;etching said layer of refractory metal, creating a pattern of refractory metal, said pattern of refractory metal aligning with said patterned and etched layer of polysilicon;etching said layer of dielectric down to the layer of etch stop material using said patterned layer of refractory metal as a mask, partially exposing the surface of said etch stop layer, partially removing said layer of dielectric from underneath said pattern of refractory metal;cleaning the surface of the pattern of refractory metal and the surface of said partially exposed etch stop layer;depositing a layer of silane based oxide over the surface of said pattern of refractory metal and the surface of said partially exposed etch stop layer, enclosing areas underneath said pattern of refractory metal from which said layer of dielectric has been partially removed; andetching said layer of silane based oxide, partially exposing the surface of said pattern of refractory metal creating a second conductor element, partially exposing the surface of said layer of etch stop material, thereby further enclosing areas underneath said pattern of refractory metal from which said layer of dielectric has been partially removed.