Patent ID: 8441847
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. A method for programming a multi-level phase change memory cell, comprising: applying a sequence of write pulses as a programming signal to said multi-level phase change memory cell; and adjusting in real time at least one parameter of said write pulse as a function of a resistance error; wherein said resistance error is determined as the difference between the resistance of the multi-level phase change memory cell and a reference resistance level; wherein said reference resistance level is a desired resistance of said multi-level phase change memory cell; and wherein said parameter of said write pulse of said programming signal is determined on the basis of said resistance error by calculating said write pulse parameter using either step A, step B, or step C as follows: wherein step A comprises calculating said write pulse parameter in the analog domain by summing a write offset signal and a feedback signal to generate a write signal applied to said multi-level phase change memory cell, subtracting a reference current I wherein step B comprises calculating iteratively said write pulse parameter in the discrete domain as follows: P(k+1)=f(P(k), R wherein step C comprises calculating iteratively said write pulse parameter in the discrete domain, wherein said write pulse parameter is a write pulse amplitude, as follows: P(k+1)=P(k)+k