Patent ID: 6753694
Filing Date: 2004-06-22
Classification: H03K

Abstract:
A single event upset (SEU) immune three-input AND-NOR circuit comprising:primary p-channel CMOS transistors, T1, T3 and T5, and redundant p-channel CMOS transistors, T2, T4 and T6; and primary n-channel CMOS transistors, T8, T10 and T12, and redundant n-channel CMOS transistors, T7, T9 and T11; wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that, a first primary input, A1, is coupled with the gate of T1 and the gate of T12; a first redundant input, A2, is coupled with the gate of T2 and the gate of T11; a second primary input, B1, is coupled with the gate of T3 and the gate of T10; a second redundant input, B2, is coupled with the gate of T4 and the gate of T9; a third primary input, C1, is coupled with the gate of T5 and the gate of T8; a third redundant input, C2, is coupled with the gate of T6 and the gate of T7; the source of T1 is coupled with a power supply; the drain of T1 is coupled with the source of T2; the drain of T2 is coupled with the drain of T4; the source of T3 is coupled with the power supply; the drain of T3 is coupled with the source of T4; the drain of T4 is coupled with the drain of T2; the source of T5 is coupled with the drain of T2 and the drain of T4; the drain of T5 is coupled with the source of T6; the drain of T6 is coupled with an output, Y; the drain of T7 is coupled with the output, Y; the source of T7 is coupled with the drain of T8; the source of T8 is coupled with ground; the drain of T9 is coupled with the output, Y; the source of T9 is coupled with the drain of T10; the source of T10 is coupled with the drain of T11; the source of T11 is coupled with the drain of T12; and the source of T12 is coupled with ground.