Patent ID: 6460107
Filing Date: 2002-10-01
Classification: G06F

Abstract:
An integrated circuit (IC) comprising:internal bus; a plurality of event counters coupled to the internal bus, each being responsive to one of a plurality of events of the internal bus, wherein the plurality of events include a grant of bus ownership to a bus master on the internal bus, and wherein at least one of the events represents a portion of total ownership time of the internal bus, and wherein at least one of the plurality of events represents an acquisition latency of the internal bus; a plurality of registers coupled to the event counters, each containing a value of a respective one of the event counters, the registers being coupled to the internal bus and accessible therefrom; and address translation unit coupled between the internal bus and an external bus for transporting transactions therebetween, wherein the internal bus, the plurality of event counters, the plurality of registers, and the address translation unit are formed on the same IC chip being a production chip and not a test chip.