Patent ID: 7402861
Filing Date: 2008-07-22
Classification: H01L

Abstract:
1. A select gate of a NAND memory array, comprising: a first dielectric layer formed on a semiconductor substrate; a first conductive layer formed on the first dielectric layer; conductive spacers formed on sidewalls of the first conductive layer and located between an upper surface of the first conductive layer and the first dielectric layer; a second dielectric layer overlying the first conductive layer and the conductive spacers; a second conductive layer formed on the second dielectric layer; and a third conductive layer formed on the second conductive layer, passing though a portion of the second conductive layer and the second dielectric layer so that a portion of the third conductive layer contacts the first conductive layer, the third conductive layer electrically connecting the first and second conductive layers, wherein the portion of the third conductive layer that contacts the first conductive layer is interposed between first and second portions of the second dielectric layer of the select gate.