Patent ID: 8207782
Filing Date: 2012-06-26
Classification: H03F

Abstract:
1. A circuit to minimize thermally generated offset voltages comprising: a differential pair of transistors having a first transistor and a second transistor; a third transistor coupled between the differential pair of transistors and a current source; a pair of bypass transistors having a first bypass transistor and a second bypass transistor; a third bypass transistor coupled between the pair of bypass transistors and the current source; a differential input having a first input coupled to the first transistor and the first bypass transistor and having a second input coupled to the second transistor and the second bypass transistor; and control circuitry coupled to the third transistor and the third bypass transistor for controlling current through the pair of bypass transistors, the control circuit configured to control the third bypass transistor to prevent the pair of bypass transistors from conducting current when a difference between the first input and the second input is small and configured to control the third bypass transistor so that at least one of the bypass transistors conducts current when the difference between the first input and the second input is relatively large.