Patent ID: 6548354
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A process for manufacturing a semiconductor memory device, comprising:forming in a semiconductor material chip a first memory cell that includes a first MOS transistor by forming a first gate electrode in a first layer of conductive material and a second gate electrode in a second layer of conductive material superimposed on the first layer of conductive material; forming in the chip a second memory cell that includes a second MOS transistor having a control gate and a floating gate that are both shielded by a layer of shielding material for preventing information stored in the second memory cell from being accessible from the outside; and wherein said floating gate electrode is formed simultaneously with the first gate electrode of the first memory cell by definition of said first layer of conductive material, and wherein said layer of shielding material is formed by definition of said second layer of conductive material.