Patent ID: 7111184
Filing Date: 2006-09-19
Classification: G06F

Abstract:
1. A method for deterministic communication across clock domains in a data processing system comprising the steps of: generating a first clock for driving a first clock domain of the data processing system and generating a second clock for driving a second clock domain of the data processing system, the second clock being time delayed from the first clock by a clock distribution delay; determining a phase delay caused by the clock distribution delay, and applying a programmable offset, calculated based on the clock distribution delay, to stop the first clock for a time period to produce an adjusted first clock, the adjusted first clock for compensating for the clock distribution delay for a predetermined portion of the second clock domain; and transmitting a signal from the second clock domain to the first clock domain in response to an event occurring in the predetermined portion of the second clock domain, the signal being received in the first clock domain on a predetermined edge of the adjusted first clock.