Patent ID: 6201744
Filing Date: 2001-03-13
Classification: G11C

Abstract:
A semiconductor memory device having a plurality of non-redundant sense amplifiers, a plurality of non-redundant memory cells coupled to said non-redundant sense amplifiers, at least one redundant sense amplifier, and a plurality of redundant memory cells coupled to said at least one redundant sense amplifier, said redundant memory cells being used to replace defective memory cells among said non-redundant memory cells, comprising:a data bus with switchable data paths coupled to said non-redundant sense amplifiers and said at least one redundant sense amplifier;a driving circuit, coupled to said non-redundant sense amplifiers and said at least one redundant sense amplifier, that simultaneously activates both said at least one redundant sense amplifier and at least one of said non-redundant sense amplifiers; anda redundancy control circuit that receives an address signal, and that produces a switching signal having a value that depends on whether a defective memory cell is addressed by said address signal,wherein said data bus with switchable data paths comprisesa first data bus, coupled to said non-redundant sense amplifiers, that transfers data read from said non-redundant memory cells and amplified by said non-redundant sense amplifiers,a second data bus, coupled to said at least one redundant sense amplifier, that transfers data read from said redundant memory cells and amplified by said at least one redundant sense amplifier,a third data bus that transfers data read in accordance with said address signal, anda switching circuit, coupled to said first, second and third data buses and to receive the switching signal from said redundancy control circuit, that selects one of said first and second data buses in accordance with the value of the switching signal and that transfers the data on the selected one of said first and second data buses to said third data bus, thereby redirecting access from the defective memory cell to a redundant memory cell when the defective memory cell is addressed.