Patent ID: 6261904
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A process for making an array of two-bit floating gate transistors for a semiconductor memory device, comprising:providing a silicon wafer substrate having parallel rows of bit-line oxide and a floating gate ONO layer on said silicon wafer substrate and said bit-line oxide, said floating gate ONO layer comprising a first silicon dioxide layer, a silicon nitride layer on said first silicon dioxide layer, and a second silicon dioxide layer on said silicon nitride layer;depositing a hard mask layer on said floating gate ONO layer;creating a multitude of openings in said hard mask layer centered upon said rows of bit-line oxide and centered between said rows of bit-line oxide;depositing a spacer layer on said hard mask layer;reducing said spacer layer to spacers within said openings by anisotropically etching said spacer layer;etching through said second silicon dioxide layer and said silicon nitride layer within said openings, thereby exposing said first silicon dioxide layer;at least partially filling said openings with third silicon dioxide; and,removing said hard mask layer and said spacers and leaving at least a portion of said third silicon dioxide at least partially filling said openings.