Patent ID: 7986576
Filing Date: 2011-07-26
Classification: G11C

Abstract:
1. A memory array, comprising: a first digit line coupled with a row of memory cells including an initial memory cell at an unterminated end configured to be coupled with a first sense amplifier, and further including a last memory cell at a terminated end configured to be located proximate a second sense amplifier; a second digit line coupled with a row of memory cells including an initial memory cell at an unterminated end configured to be coupled with the second sense amplifier, and further including a last memory cell at a terminated end configured to be located proximate the first sense amplifier; and an equilibrate circuit coupled with the first digit line and configured to couple the first digit line to an equilibration reference in response to an equilibrate signal, wherein the equilibrate circuit is formed at an edge of the memory array according to layout criteria of the memory array.