Patent ID: 7613046
Filing Date: 2009-11-03
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory elements to which data is written by a write operation; and a control circuit, wherein: in a first write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if any of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation; and in a second write sequence, the control circuit simultaneously stores data in “n” (“n” being a natural number) numbers of said plurality of the memory elements in the write operation and then the control circuit repeats the write operation and a verify operation if “k” (“k” being a natural number which is equal to or less than “n”) or greater numbers of said “n” numbers of the memory elements are memory elements written insufficiently in the verify operation.