Patent ID: 8423840
Filing Date: 2013-04-16
Classification: G11C

Abstract:
1. A pattern generator employed in a memory test apparatus, the pattern generator comprising: an address signal generating circuit configured to generate an address signal which designates an address to be accessed in a memory under test; an operation inhibition signal generating unit configured to generate a plurality of patterns of operation inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being subjected to an operation; a selector configured to select one from among the plurality of patterns of operation inhibition signals generated by the operation inhibition signal generating unit, and to output the operation inhibition signal thus selected; and an address signal operation circuit configured to receive the address signal, an operation control signal, which is an instruction to perform an operation on the address signal, and the operation inhibition signal selected by the selector, and to perform an operation on only the bits of the address signal that are not prevented from being to subjected to the operation according to the operation inhibition signal when the operation control signal is asserted, and to output the resulting address signal.