Patent ID: 6760895
Filing Date: 2004-07-06
Classification: G06F

Abstract:
A design method of semiconductor device comprising:a first step of calculating delay, judging as to whether or not a targeted in-cycle transfer is attainable, and laying out logic circuits, circuit elements and wirings between the logic circuits and the circuit elements repeatedly until the targeted in-cycle transfer becomes attainable; a second step of calculating the delay judging as to whether or not the targeted in-cycle transfer is attainable, and modifying the wirings repeatedly until the targeted in-cycle transfer becomes attainable; a third step of calculating a crosstalk noise level, judging as to whether or not malfunctioning occurs, and modifying the wirings repeatedly until malfunctioning subsides; and a fourth step of using data of the layout and wirings for mask data, the data of the layout and wirings being obtained by carrying out the third step, wherein when calculating the delay in the first step, an actual load of the semiconductor device after laying out the logic circuits, the circuit elements and the wirings is considered and a total capacitance (Ctotal) of a selected subject line of the wirings with the assumption of grounding of other lines of the wirings is used, wherein when calculating the delay in the second step, the actual load of the semiconductor device and crosstalk after carrying out the first step are considered and the total capacitance (Ctotal) is used, and wherein when calculating the crosstalk noise level, the actual load of the semiconductor device after carrying out the second step is considered and the total capacitance (Ctotal) and a coupling capacitance (Cp) between the subject line and an adjacent line are used.