Patent ID: 7502724
Filing Date: 2009-03-10
Classification: G01R,G06F

Abstract:
1. A test simulator simulating a test of a semiconductor device, comprising: a test pattern holding means for holding a plurality of existing test patterns and for holding a value of an internal register in the semiconductor device for a simulation test; a device output holding means for preliminarily holding an output obtained in response to one of the existing test patterns; a test pattern generating means for generating a new test pattern for the simulation test; a test pattern deciding means for deciding whether the new test pattern is equal to one of the existing test patterns; a simulation skipping means for skipping at least a part of the simulation test by reading the output from said device output holding means and using the output as an output in response to the new test pattern without supplying the new test pattern to the semiconductor device when the new test pattern is at least partially equal to the one of the existing test patterns and a value of the internal register in the semiconductor device when the new test pattern starts to be supplied for the simulation test is equal to the value of the internal register held in said test pattern holding means; a termination register value holding means for holding a value of the internal register in the semiconductor device after the one of the existing test patterns stops being supplied; and a register value setting means for setting the internal register in the semiconductor device to the value of the internal register held in said termination register value holding means when at least a part of the simulation test is skipped by said simulation skipping means.