Patent ID: 6134647
Filing Date: 2000-10-17
Classification: G06F,H04L

Abstract:
A data processing system comprising:(A) a plurality of nodes;(B) a serial data bus interconnecting the nodes in a series in a closed loop for passing address and data information among said nodes, wherein each of the nodes is connected to exactly one preceding node and exactly one successive node; and(C) at least one of said plurality of nodes including:(a) a processor;(b) a printed circuit board;(c) a memory partitioned into a plurality of sections, a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory;(d) a local bus connecting said processor, said block sharable memory, and said printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board; and(e) the printed circuit board having(i) a sensor for sensing data transferred into the said directly sharable memory;(ii) a queuing device for queuing sensed data;(iii) a serializer for serializing queued data;(iv) a transmitter for transmitting serialized data onto said serial bus to the successive processing node;(v) a receiver for receiving serialized data from the preceding processing node;(vi) a deserializer for deserializing received serialized data into parallel data; and(vii) means responsive to sensing of transferred data for controlling proper dispersal of said transferred data.