Patent ID: 6262917
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A flash memory device comprising:a substrate, and the substrate comprises a trench formed in the substrate;a gate oxide layer, wherein the gate oxide layer is located on the substrate on a side of the trench;a floating gate, wherein the floating gate is located on the gate oxide layer;a source region, wherein the source region is located in the substrate at a bottom of the trench;a drain region, wherein the drain region is located on one side of the floating gate in a part of the substrate where the trench is not formed;a dielectric layer, wherein the dielectric layer is located on the substrate and the dielectric layer is conformal to the floating gate, the gate oxide layer and the trenches, wherein the dielectric layer directly contacts a top surface of the floating gate; anda control gate, wherein the control gate is located on the dielectric layer.