Patent ID: 6492258
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method for making a semiconductor chip having electrically conductive lines, comprising:providing at least one substrate; establishing at least one predetermined pattern of at least one conductive interconnect line supported by the at least one substrate, said at least one line comprising at least one first layer comprising titanium, at least one second layer comprising aluminum, and at least one intermetallic layer formed and disposed between the at least one first layer and the at least one second layer; annealing the at least one predetermined pattern of at least one conductive interconnect line; and depositing an interlayer dielectric (ILD) formed and disposed between said adjacent lines, at least a portion of said at least one intermetallic layer comprising an interfusion between a surface of said at least one aluminum layer and a surface of said at least one titanium layer without said at least one aluminum layer being subjected to hydrostatic stress during said ILD depositing step, said at least one aluminum layer comprising at least one metal additive selected from a group consisting essentially of copper (Cu), nickel (Ni), zinc (Zn), gold (Au), titanium (Ti), indium (In), chromium (Cr), silver (Ag), palladium (Pd), silicon (Si), and platinum (Pt), and said at least one aluminum layer exhibiting reduced void formation as a result of said interfusion without said at least one aluminum layer being subjected to hydrostatic stress during said ILD depositing step.