Patent ID: 6816091
Filing Date: 2004-11-09
Classification: G01D,H03M

Abstract:
An interpolation circuit comprising:a circuit that generates out-of-phase ramp signals and complements of said ramp signals; a fractional signal circuit that generates one or more fractional ramp signals from said ramp signals; first and second comparators, each comparator comprising a first input and a second input and generating a comparator output signal indicative of whether said first input is greater than said second input; first, second, third and fourth multiplexers, each multiplexer having multiplexer inputs comprising said ramp signals and said fractional ramp signals, each multiplexer coupling said multiplexer input signals to a corresponding input of said first comparator or of said second comparator, said input being determined by a multiplexer control signal coupled to that multiplexer; and a finite state machine having state inputs comprising said comparator output signals and a current state signal for indicating one of a plurality of states, said finite state machine generating a next state signal from said state inputs, said current state signal being replaced by said next state signal in response to a clock signal, said current state signal determining said multiplexer control signals for each of said multiplexers.