Patent ID: 7870311
Filing Date: 2011-01-11
Classification: H04L

Abstract:
1. A system for controlling a packet flow using a JTAG interface comprising: a packet processor engine programmed to interpret the packets from a packet memory, to determine a packet chain switching decision at a controller level, wherein the switching involves changing from a first continuous stream of packets to a second continuous stream of packets, and to perform switching between packet chains in response to events, the packet processor engine sending a selected packet chain to a remote host processor separate from the system, wherein determining the packet chain switching decision by the packet processor engine is performed in response to an asynchronous event and is performed independently of the remote host processor; a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain; prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains; a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the active buffer chains that have been started; and a status register of the packet processor engine, having a chain active group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.