Patent ID: 7680232
Filing Date: 2010-03-16
Classification: H03L,H04L

Abstract:
1. A multi-mode clock data recovery circuit having at least two modes of operation, comprising: a switch that conveys a recovered clock signal to a frequency detector and a phase detector; a first mode of operation in which the switch is coupled to an output of a controlled oscillator, the switch conveying said output of said controlled oscillator as the recovered clock signal; and a second mode of operation in which the switch is coupled to an output of a phase interpolator, the switch conveying said output of said phase interpolator as the recovered clock signal, wherein in the first mode of operation, if a frequency of the recovered clock signal differs from a frequency of a reference clock signal by at least a tolerance point, an output of the frequency detector is selectively conveyed to the controlled oscillator at least until the frequency of the recovered clock signal differs from the frequency of the reference clock signal by at most an acceptable difference.