Patent ID: 6055188
Filing Date: 2000-04-25
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array having first and second memory cell groups which are simultaneously selected during an erasing or writing operation;a first bit line connected to said first memory cell group;a second bit line connected to said second memory cell group;a node connected to said first and second bit lines; anda data circuit where data is input during erase or write verify read;wherein said data circuit includes a latch circuit for storing the data, the data being based on first data read from said first memory cell group and second data read from said second memory cell group, the data indicating that the erasing or writing operation is completed being stored in said latch circuit if both of the first and second data indicate that the erasing or writing operation of corresponding memory cells are completed, and the data indicating that the erasing or writing operation is incomplete being stored in said latch circuit if at least one of the first and second data indicates that the erasing or writing operation of a corresponding memory cell is insufficient.