Patent ID: 8300370
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. An ESD protection circuit for protecting an internal circuit from being damaged by an ESD current, comprising a first MOS transistor coupled to a pad and the internal circuit, for limiting the ESD current and shunting part of the ESD current to a first voltage path; and a second MOS transistor coupled to the first MOS transistor, for limiting the ESD current and shunting part of the ESD current to a second voltage path; wherein a drain of the first MOS transistor comprises first contacts coupled to a first node and second contacts coupled to a second node, and a first resistive area formed between the first contacts and the second contacts functions as a first diffusion resistor to increase impedance at the drain of the first MOS transistor, and a source of the first MOS transistor is coupled to the first voltage path, wherein a drain of the second MOS transistor comprises third contacts and fourth contacts, and a second resistive area formed between the third contacts and the fourth contacts functions as a second diffusion resistor to increase impedance at the drain of the second MOS transistor, and a source of the second MOS transistor is coupled to the second voltage path, and wherein when the first diffusion resistor is N-type, the second diffusion resistor has a type different from the N-type, and when the first diffusion resistor is P-type, the second diffusion resistor has a type different from the P-type.