Patent ID: 7529133
Filing Date: 2009-05-05
Classification: G11C

Abstract:
1. A semiconductor storage apparatus comprising: a memory cell array having a plurality of data cells arranged in a plurality of rows and a plurality of columns, the plurality of data cells including a plurality of MOS transistors respectively, the plurality of MOS transistors having different types of operating characteristics to store data according to said types, said MOS transistors in each column being connected to each other in series such that a source of one said MOS transistor is coupled to a drain of next said MOS transistor; a plurality of bit lines, each said bit line being defined by said MOS transistors in each said column, a cell current flowing in each said bit line; a plurality of sense amplifiers, each sense amplifier being associated with each said bit line: a readout circuit for reading said data from one of said data cells based on a cell current occurring in one of said bit lines; and a step-down circuit connected to all of said plurality of bit lines for supplying a constant voltage to said data cells, regardless of values of the cell currents on said plurality of bit lines, wherein said step-down circuit has a current-mirror-type reference-potential-generating-circuit, and said constant voltage is smaller than a power source voltage.