Patent ID: 7205570
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: a first conductive layer formed on an insulating substrate; a gate insulating layer on the first conductive layer; a semiconductor layer on the gate insulating layer; a second conductive layer formed at least in part on the semiconductor layer and including a data line, a drain electrode and a data pad located at an end of the data line, the second conductive layer including a lower film of barrier metal and an upper film of Al or Al alloy; a passivation layer covering the semiconductor layer; and a third conductive layer formed on the passivation layer and contacting the second conductive layer, the third conductive layer including a pixel electrode and a pad electrode, wherein at least an edge of the upper film lies on the lower film such that the lower film includes a first portion and a second portion exposed out of the upper film of the drain electrode and the data pad respectively, and the pixel electrode and the pad electrode, respectively, contact the first portion and the second portion of the lower film; the edge of the upper film of the drain electrode around the first portion is separated from the pixel electrode, and the edge of the upper film of the data pad around the second portion is separated from the pad electrode.