Patent ID: 6979859
Filing Date: 2005-12-27
Classification: G11C,H01L

Abstract:
1. A flash memory cell, comprising: a first trench formed at a top side of a semiconductor body or a semiconductor layer; a floating gate electrode arranged in the first trench isolated from the semiconductor material of a sidewall of the first trench by a first dielectric layer; a control gate electrode arranged in the first trench, isolated from the floating gate electrode by a second dielectric layer, and provided with an electrical lead; doped regions for source and drain arranged in the semiconductor material forming the sidewall in a longitudinal direction of the first trench at a distance from one another on both sides of the floating gate electrode, the doped regions being provided with contact connections and being electrically conductively connected to a respective bit line; a second trench arranged parallel to the first trench and at a distance from the sidewall provided with the floating gate electrode, so that a semiconductor ridge is present between the first and second trenches; and a gate electrode arranged in the second trench on a sidewall of the semiconductor ridge opposite the floating gate electrode, isolated from the semiconductor material by a third dielectric layer, and provided with an electrical lead.