Patent ID: 8513779
Filing Date: 2013-08-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate comprising at least first and second device regions of different surface crystal orientations; an n-channel field effect transistor (n-FET) and a p-channel field effect transistor (p-FET), wherein the n-FET comprises source, drain, and channel regions that are located in one of the first and second device regions, wherein the p-FET comprises source, drain, and channel regions that are located in the other of the first and second device regions, and wherein the n-FET and p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate, said conductive connector having an upper surface that is flush with an upper surface of the semiconductor substrate and having a bottommost surface that is present at a greater depth in the semiconductor substrate than a bottommost surface of the source and drain of the nFET and the pFET; and a recessed dielectric spacer located between the first and second device regions and under the conductive connector, wherein said conductive connector has outermost sidewall surfaces that are vertically coincident to outermost sidewall surfaces of the recessed dielectric material.