Patent ID: 6507124
Filing Date: 2003-01-14
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device, comprising:a memory cell including a first driver transistor of a first conduction type, a second driver transistor of the first conduction type, a first load transistor of a second conduction type, a second load transistor of the second conduction type, a first transfer transistor of the first conduction type and a second transfer transistor of the first conduction type; a well contact region of the first conduction type; and a well contact region of the second conduction type, wherein the memory cell, the well contact region of the first conduction type, and the well contact region of the second conduction type are provided in a plurality, respectively, the memory cell is equipped with first and second gate electrode layers, first and second drain-drain connection layers, and first and second drain-gate connection layers, the first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor, the second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor, the first drain-drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor, the second drain-drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor, the first drain-gate connection layer connects the first drain-drain connection layer and the second gate electrode layer, the second drain-gate connection layer connects the second drain-drain connection layer and the first gate electrode layer, the drain-gate connection layers, the drain-drain connection layers, and the gate electrode layers are provided in different layers, respectively, in plan view, the first and second gate electrode layers are located between the first drain-drain connection layer and the second drain-drain connection layer, the well contact region of the first conduction type is provided for each specified number of memory cells arranged in a first direction, and the well contact region of the second conduction type is provided for every two of memory cells arranged in a second direction, which is perpendicular to the first direction.