Patent ID: 8423878
Filing Date: 2013-04-16
Classification: G06F,H03M

Abstract:
1. A memory controller comprising: first and second interface controllers configured to exchange data with external devices; and an internal block connected between the first and second interface controllers, wherein the first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block, wherein each of the first and second interface controllers is configured to generate at least one parity bit corresponding to the received data and to transmit the received data and the corresponding at least one parity bit to the internal block, and to receive at least one external parity bit corresponding to the received data, and wherein a section for transmission of the received at least one external parity bit and a section for transmission of the generated at least one parity bit have an overlapping section on a signal path in each of the first and second interface controllers.