Patent ID: 8502561
Filing Date: 2013-08-06
Classification: H03K

Abstract:
1. Signal value storage circuitry comprising: first signal transmission circuitry having a first processing signal input, a first processing signal output and a first clock signal input, said first signal transmission circuitry being configured to transmit a processing signal received at said first processing signal input to said first processing signal output when a first clock signal received at said first clock signal input has a first open value and to block transmission of said processing signal received at said first processing signal input to said first processing signal output when said first clock signal has a first closed value; storage circuitry having a storage input and a storage output, said storage input being connected to said first processing signal output and said storage circuitry being configured to capture said processing signal output from said first processing signal output, to store said processing signal when said storage input is not driven and to output said processing signal stored within said storage circuitry from said storage output; second signal transmission circuitry having a second processing signal input, a second processing signal output and a second clock signal input, said second processing signal input being connected to said storage output and said second signal transmission circuitry being configured to transmit said processing signal received at said second processing signal input to said second processing signal output when a second clock signal received at said second clock signal input has a second open value and to block transmission of said processing signal received at said second processing signal input to said second processing signal output when said second clock signal has a second closed value; transition detector circuitry having a transition detector input connected to receive said processing signal from one of said storage input and said storage output, said transition detector circuitry being configured to assert an error signal if said processing signal from one of said storage input and said storage output changes during an error detection period.