Patent ID: 8825955
Filing Date: 2014-09-02
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus comprising: a processor core configured to perform data processing operations; a cache having a data array and a corresponding tag array, said data array configured to store data values for access by said processor core and said tag array configured to store tag portions of addresses associated with said data values in tag entries of said tag array, said cache configured to perform a tag lookup procedure in response to a received address, said tag lookup procedure comprising comparing a tag portion of said received address with an identified set of tag entries in said tag array to determine if a data value associated with said received address is stored in said cache, said identified set of tag entries being determined by an index portion of said received address, wherein said data array comprises a partial tag store configured to store a partial tag value in association with each entry in said data array, said partial tag value comprising a strict subset of the tag portion stored in a corresponding entry of the tag array, wherein said data array is configured to perform a data access procedure in parallel with said tag lookup procedure, said data access procedure comprising comparing a partial tag value of said received address with partial tag values stored in association with a set of data entries in said data array corresponding to said identified set of tag entries in said tag array, wherein said data array is configured to read out a selected data value from an entry in said set of data entries in said data array if a match condition occurs, said match condition comprising said partial tag value of said received address matching a partial tag value stored in association with that entry, wherein said cache comprises exclusivity circuitry configured to ensure that at most one partial tag value of said partial tag values stored in association with said set of data entries can generate said match condition, wherein said exclusivity circuitry comprises an additional bit stored in association with each said partial tag value associated with each entry in said data array, wherein said data array is configured such that said match condition further requires said additional bit to have a predetermined value and said cache is configured to administer values of said additional bits such that at most one additional bit stored in association with each said partial tag value stored in association with said set of data entries can have said predetermined value.