Patent ID: 8489663
Filing Date: 2013-07-16
Classification: G06F

Abstract:
1. A system for anticipating a number of leading zeros in a significand of a decimal floating-point (DFP) result, wherein the DFP result is a sum or a difference of first and second decimal floating-point (DFP) operands, the system comprising: an adder array configured to perform a decimal digit addition of a first data value and a second data value to generate a carry operand and a sum operand, wherein the first and second data values are corrected significands for the first and second DFP operands; a parallel prefix network configured to add the first and second data values; a subtraction unit configured to compute a difference value by subtracting a left shift amount (LSA) and a first count value, wherein the first count value represents a number of leading zeros in a significand of the first DFP operand; a first anticipator circuit configured to generate a first leading zero count based on the carry operand, the sum operand, the difference value and a second count value, wherein the second count value represents a number of leading zeros in a significand of the second DFP operand; a second anticipator circuit configured to generate a second leading zero count based on data including the carry operand, the sum operand and a shift indication signal; and a multiplexer configured to select one of the first leading zero count and the second leading zero count based on an indicator signal that indicates an effective operation.