Patent ID: 6301685
Filing Date: 2001-10-09
Classification: G01R

Abstract:
An error propagation path extraction system for extracting an error propagation path through an inverse logical inference system for estimating the logical state of the input terminal of a combinational circuit in accordance with the logical state of the output terminal of the circuit by using a back track system for estimating the logical state of every signal line by repeating the implication for estimating the logical state of the input/output line of a gate not estimated yet in accordance with the logical state of the input/output line of a gate already estimated; the system comprising:error propagation path influenced line retrieval means for retrieving a signal line connected with said error propagation path as said signal line whose logical state is an object to be decided; andfailing output terminal connection related line extraction means for extracting a signal line having a possibility of propagating an error to a failing output terminal from said error propagation path in accordance with the retrieval result by said error propagation path influenced line retrieval means.