Patent ID: 9160314
Filing Date: 2015-10-13
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: a first inverter configured to receive a first data bit and output a binary logical compliment of the first data bit; a master latch configured to receive the binary logical compliment of the first data bit, a first clock signal, a second clock signal, a first control signal and a second control signal (RETN), wherein the first clock signal, the second clock signal, the first control signal and the second control signal determine when a binary logical value of the first data bit is presented on an output of the master latch and when the output of the master latch is latched in the mater latch; a transfer gate wherein the transfer gate transfers data from the output of the master latch to an output of the transfer gate when the first clock signal transitions from a high logical value to a logical low value; a slave latch configured to receive the output of the transfer gate, a second data bit, the first clock signal, the second clock signal, the first control signal, the second control signal (RETN), a first slave control signal and a second slave control signal wherein the first clock signal, the second clock signal, the first control signal, the second control signal, the first slave control signal and the second slave control signal determine whether the output of the transfer gate or the second data bit is latched in the slave latch.