Patent ID: 6510489
Filing Date: 2003-01-21
Classification: G06F,G11C

Abstract:
A memory interface circuit for controlling and refreshing a semiconductor memory device, comprising:a memory bus arbitrating circuit which receives a plurality of request signals and selects a request signal of highest priority among two or more simultaneously received request signals, wherein said request signals include a first refresh request signal, a second request signal having a priority which is lower than that of the first refresh request signal, and at least one third request signal each having a priority which is lower than that of the first refresh request signal and the second request signal; a memory controlling circuit which controls the semiconductor memory device in accordance with the request signal of highest priority selected by said memory bus arbitrating circuit, and outputs a terminating signal when a process in accordance with the second request signal ends; a logical counter which generates a count value corresponding to an elapsed time, and which is reset when the semiconductor memory device is refreshed; a monitoring circuit which outputs a monitoring signal when the count value of said logical counter exceeds a comparison value; a gate circuit which outputs the first refresh request signal to said memory bus arbitrating circuit when both of the terminating signal and the monitoring signal are input to the gate circuit.