Patent ID: 6255893
Filing Date: 2001-07-03
Classification: G01R,H01L

Abstract:
A circuit, comprising:an overstress detector having at least two input terminals and an output terminal, the overstress detector comprising a first PFET coupled source-to-drain between a first node and a second node, a fuse coupled between the second node and a third node, a first NFET coupled drain-to-source between the third node and a fourth node, and wherein a gate of the first PFET is coupled to an enable signal source, and the gate of the first NFET is coupled to the drain of the first NFET;a reference voltage generator having an output terminal; anda comparator having a first input terminal coupled to the output terminal of the overstress detector, a second input terminal coupled to the output terminal of the reference voltage generator, and an output terminal;wherein the overstress detector generates a first voltage indicative of the absence of an overstress condition, and a second voltage indicative of an overstress condition.