Patent ID: 6018177
Filing Date: 2000-01-25
Classification: G11C,H01L

Abstract:
A four level DRAM cell to retain two bits of digital data, fabricated on a semiconductor substrate of a material of a first conductivity type, comprising:a) a pass transistor having a source connected to a bit line voltage generator, a gate connected to a word line voltage generator, and a drain;b) a trench capacitor, formed within the semiconductor substrate, having a top plate connected to said drain and a bottom plate connected to a substrate biasing voltage source;c) a stack capacitor, formed above the semiconductor substrate, having a first plate connected to the drain and a second plate connected to a coupling-gate control voltage generator;d) an interconnecting block that will interconnect the top plate of the trench capacitor to the first plate of the stack capacitor; ande) an insulating layer to isolate the stack capacitor from the trench capacitor.