Patent ID: 6180538
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device comprising the steps of:providing a semiconductor substrate; using a rapid-thermal-chemical-vapor-deposition apparatus to form a first silicon oxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon oxide layer, and a second layer of silicon oxide overlying the silicon nitride layer, wherein the first and second oxide layers are formed by a high temperature oxide deposition process,wherein the high temperature oxide deposition process is carried out at a temperature of about 700.degree. C. to about 800.degree. C., andwherein the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer are sequentially formed in a single wafer processing apparatus in the absence of exposure to ambient atmosphere.