Patent ID: 8086984
Filing Date: 2011-12-27
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit, said method comprising: extracting a parasitic parameter of the semiconductor integrated circuit, based on a layout data of the semiconductor integrated circuit; generating a timing information, by performing a highly-accurate IR drop analysis on the semiconductor integrated circuit based on the layout data, generating a first delay information based on a first IR drop information obtained by performing the highly-accurate IR drop analysis and the parasitic parameter, and performing a static timing analysis based on the parasitic parameter, the first IR drop information, and the first delay information, the first IR drop information comprising static information; generating a second delay information by performing a dynamic IR drop analysis for the semiconductor integrated circuit based on the layout data to generate a second IR drop information and performing a delay calculation in consideration of a dynamic IR drop based on the timing information and the second IR drop information, the second IR drop information comprising dynamic information, the highly-accurate IR drop analysis being a different analysis from the dynamic IR drop analysis; generating a third delay information by performing the delay calculation in consideration of a crosstalk based on the parasitic parameter and the timing information; performing a timing verification based on the first delay information, the second delay information, and the third delay information to determine whether a timing of the semiconductor integrated circuit is converged; and calculating a noise cycle of the semiconductor integrated circuit by a computer, using a noise cycle calculating unit included in an information processing device; based on the second IR drop information to generate a noise cycle information, and determining a delay value of a delay circuit, using a delay pass circuit generating unit included in the information processing device, based on the noise cycle information, wherein the generating the third delay information performs the delay calculation, using a delay calculating unit included in the information processing device, in consideration of the dynamic IR drop based on the delay circuit, which determines the delay value based on the noise cycle, to generate the second delay information.