Patent ID: 8143812
Filing Date: 2012-03-27
Classification: H03K,H05B,Y02B

Abstract:
1. An apparatus comprising: a plurality of terminals; a clamp circuit including: a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the second transistor receives a first enable signal; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the third transistor receives a second enable signal; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the second passive electrodes of the second and third transistors, and wherein the control electrode of the fourth transistor receives a bias voltage.