Patent ID: 6031420
Filing Date: 2000-02-29
Classification: H03F

Abstract:
Operational amplifier arrangement (OAA) including a first arrangement input terminal (IN1) and a second arrangement input terminal (IN2) between which a differential input voltage (vin) is applied, said operational amplifier arrangement (OAA) further including an arrangement output terminal (OUT) for delivering an output voltage, said operational amplifier arrangement (OAA) further includinga first operational amplifier (OA1) having a first input terminal (INN1) of a first polarity type (-) and coupled to said first arrangement input terminal (IN1), said first operational amplifier (OA1) having a second input terminal (INP1) of a second polarity type (+) opposite to said first polarity type, and a first amplifier output terminal (OUT1),a second operational amplifier (OA2) having a second amplifier negative input terminal (INN2) and coupled to said first amplifier output terminal (OUT1) of said first operational amplifier (OA1), said second operational amplifier (OA2) having a second amplifier positive input terminal (INP2) to which a DC voltage (Vref2) is supplied, said second operational amplifier (OA2) further including a second amplifier output terminal (OUT2) coupled to said arrangement output terminal (OUT), and to said second amplifier negative input terminal (INN2) via a compensation capacitor (Cc),characterised in that said operational amplifier arrangement further includesa third operational amplifier (OA3) having a third amplifier negative input terminal (INN3) which is coupled via a hold capacitor (Ch) to the ground potential, said third operational amplifier (OA3) further having a third amplifier positive input terminal (INP3) to which a DC reference voltage (Vref3) is supplied, said third operational amplifier (OA3) further having a third amplifier output terminal (OUT3) coupled to said first amplifier output terminal (OUT1) at a common junction point (J),a clock generation means (CG), including a clock input terminal (clk) coupled to an arrangement clock input terminal (clkin) to which an input clock signal is applied, a clock output and an inverted clock output, said clock generation means (CG) being adapted to generate from said input clock signal, a clock signal for delivery to said clock output, and an inverted clock signal, substantially inverted with respect to said clock signal, for delivery to said inverted clock output,a first switch (SW1) having series terminals respectively coupled to said junction point (J) and to said second amplifier negative input terminal (INN2) respectively, and a first switch control terminal coupled to said clock output of said clock generation means (CG),a second switch (SW2) having series terminals respectively coupled to said first input terminal (INN1) and said second input terminal (INP1) of said first operational amplifier (OA1) respectively, and a second switch control terminal coupled to said inverted clock output of said clock generation means (CG),a third switch (SW3) having series terminals respectively coupled to said third amplifier negative input terminal (INN3) and said third amplifier output terminal (OUT3) respectively, and a third switch control terminal coupled to said inverted clock output of said clock generation means (CG),a fourth switch (SW4) having series terminals respectively coupled to said first arrangement input terminal (IN1) and to said first input terminal (INN1) of said first operational amplifier (OA1) respectively, and a fourth switch control terminal coupled to said clock output of said clock generation means (CG).