Patent ID: 6772271
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A data processing apparatus comprising:a main memory having a plurality of successive memory spaces with a series of main addresses set thereto; first through nth memory banks having a plurality of successive memory spaces with a series of bank addresses set commonly thereto; a data processing circuit for reading stored data in said main memory and said memory banks successively from said main addresses and said bank addresses; and bank switching means for controlling a memory bank as a readout destination for said data processing circuit; said main memory storing in an arbitrary memory space thereof a bank switching instruction which designates a first bank address of the first memory bank, said first through (n-1)th memory banks each having a virtual space where no stored data is present in respective final bank address thereof, said nth memory bank storing in the memory space represented by the final bank address thereof a main return instruction which designates a particular main address of said main memory; said data processing circuit having means for switching the readout destination therefor to the first bank address of the first memory bank when the data processing circuit reads said bank switching instruction from said main memory, and switching the readout destination to said particular main address when the data processing circuit reads said main return instruction from the final bank address of said nth memory bank; said bank switching means comprising means for switching said readout destination to the first bank address of each of the second through nth memory banks each time the readout destination for the data processing circuit reaches the bank address of the virtual space in each of the first through (n-1)th memory banks.