Patent ID: 9063729
Filing Date: 2015-06-23
Classification: G06F

Abstract:
1. A processor comprising: a core to execute instructions, the core including at least one arithmetic logic unit; and an instruction generator coupled to the core, wherein the instruction generator is to receive a memory-access instruction including address data corresponding to an address in a memory to couple to the processor and non-address data including instruction data and to compare the address data to an address range, to generate an index signal having a value corresponding to one of a set of index values to access one of a set of execution instruction parameters identified by the set of index values, and to combine the non-address data and the execution instruction parameter identified by the index signal to generate an execution instruction if the address data of the memory-access instruction is within the address range, wherein the instruction generator is to output the execution instruction to the core if the execution instruction is generated, and otherwise to output the memory-access instruction to the core.