Patent ID: 7709954
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. A method for preparing an integrated circuit device having a circuit pattern, on a silicon substrate, the circuit pattern having bond pads, for packaging in a wafer-level chip-scale (WLCS) package, the method comprising: depositing a first organic dielectric layer on the silicon substrate, covering the circuit pattern of the IC device; defining bond pad openings above the bond pads of the circuit pattern and bump pad openings at a predetermined distance from the bond pad openings in the first organic dielectric layer; depositing a metal layer on the first dielectric layer and filling the bond pad openings and bump pad openings, the metal layer having a top layer of metal and a bottom layer of metal; defining bond pad connections and bump pad connections by removing the top layer of metal in areas other than the bond pad openings and bump pad openings, and leaving the bottom layer of metal in areas not having bond pad or bump pad connections; defining connection traces from the bond pad connections to the bump pad connections, in the bottom metal layer; depositing a second organic dielectric layer on the silicon substrate, enveloping the circuit pattern; and removing the second organic dielectric layer from the bump pad connections and exposing the bump pad connections.