Patent ID: 8436805
Filing Date: 2013-05-07
Classification: G02F,G09G

Abstract:
1. An active matrix substrate comprising: scanning signal lines each extending in a row direction; data signal lines each extending in a column direction; retention capacitor lines each extending in the row direction; first and second transistors each provided near the vicinity of each intersection of the scanning signal lines and the data signal lines so that each of the first and second transistors is connected to a corresponding scanning signal line and a corresponding data signal line; and first and second pixel electrodes each provided in each pixel region, said first pixel electrode being connected to the first transistor and said second pixel electrode being connected to the second transistor, wherein: one retention capacitor line is provided so as to correspond to a space between two pixel regions adjoining each other in the column direction, a plurality of capacitor electrodes are provided so as to overlap the retention capacitor line so that (a) either of first and second pixel electrodes provided in one of the two pixel regions and (b) either of first and second pixel electrodes provided in the other one of the two pixel regions are electrically connected, respectively, to corresponding ones of the plurality of capacitor electrodes provided so as to overlap the retention capacitor line, said first pixel electrode provided in each pixel region is electrically connected to a corresponding one of the plurality of capacitor electrodes that is provided so as to overlap one of two adjacent retention capacitor lines, and said second pixel electrode provided in the each pixel region is electrically connected to a corresponding one of the plurality of capacitor electrodes that is provided so as to overlap the other one of the two adjacent retention capacitor lines, an interconnection line for electrically connecting said first or second pixel electrode to a corresponding one of the plurality of capacitor electrodes is provided, said first pixel electrode is connected to a drain electrode of the first transistor and said second pixel electrode is connected to a drain electrode of the second transistor, said first pixel electrode is provided so as not to overlap any lines connected to the drain electrode of the second transistor and said second pixel electrode is provided so as not to overlap any lines connected to the drain electrode of the first transistor, one pixel region is provided between two adjacent retention capacitor lines such that a scanning signal line is provided between the pixel region and one of the two retention capacitor lines, in a part of the pixel region along the scanning signal line, a part of said second pixel electrode is positioned, but any part of said first pixel electrode is not positioned, a non-pixel electrode forming region in which neither of said first and second pixel electrodes is formed, is provided in a part of the pixel region, adjacent to the scanning signal line, and said first pixel electrode is electrically connected to a drain electrode of the first transistor via the interconnection line or a drain lead line that crosses the non-pixel electrode forming region.