Patent ID: 9110479
Filing Date: 2015-08-18
Classification: G05F,H02J,H02M

Abstract:
1. A voltage balancing circuit comprising: n-number of groups of resistances series-connected between a high voltage side first reference node and a low voltage side (n+1)-th reference node, between first and second main terminals to which DC voltage is supplied, where n≧3; n-number of groups of main circuit capacitors series-connected between the high voltage side first output node and the low voltage side (n+1)-th output node between the first and second main terminals supplying DC voltage; (n−1)-number of voltage stabilization circuits configured between k-th reference nodes of the n-number of groups of resistances and k-th output nodes of the n-number of groups of main circuit capacitors respectively where 2≦k≦n, each voltage stabilization circuit including first and second transistors of first and second conductivity types opposed to each other, respectively and having commonly connected reference input terminals and commonly connected output terminals, the reference input terminals being connected to the k-th reference nodes of the n-number of groups of main circuit capacitors, the output terminals being connected to the k-th output nodes of the n-number of groups of main circuit capacitors, wherein when voltage of each reference input terminal is higher than voltage of each output terminal, power is supplied from a source node via the first transistor to the output terminal, and when the voltage of each reference input terminal is lower than the voltage of each output terminal, power is supplied from the output terminal via the second transistor to a destination node, whereby the voltage of the output terminal is stabilized so as to correspond with the voltage of the reference input terminal; and wherein the k-th voltage stabilization circuit is configured in such a manner that the first transistor is connected via a first resistance to a (k−a)-th output node serving as the source node and the second transistor is connected via a second resistance further connected to a (k+b)-th output node serving as the destination node, where 2≦k≦n, 1≦a≦k−1 and 1≦b≦n+1−k.