Patent ID: 7585793
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A method for reducing tearing-off defects when applying a high temperature (HT) heat treatment to a semiconductor wafer that comprises a silicon-on-insulator (SOI) structure, which method comprises: providing a heating chamber for conducting a HT heat treatment of the SOI semiconductor wafer, wherein the heating chamber is initially provided at an initial heating temperature; providing the SOI semiconductor wafer at a first temperature for introduction into the heating chamber; and ramping-up the initial temperature of the heating chamber to conduct the HT heat treatment; wherein during the HT heat treatment, either the first temperature of the SOI semiconductor wafer is provided at a lower temperature below 600° C., or the ramping-up temperature of the heating chamber is provided at a rate slower than 10° C./min, or both are provided, so that the resulting heat treated wafer exhibits reduced tearing-off defects compared to silicon-on-insulator wafers treated by a conventional HT heat treatment.