Patent ID: 6472902
Filing Date: 2002-10-29
Classification: G01R

Abstract:
A semiconductor device in which input data is gated according to an internal control signal generated within the semiconductor device, the semiconductor device comprising:N number of data input terminals for inputting input data, where N is an integer that is two or greater; a test mode input terminal for inputting a test mode signal; an OR device that obtains a logical sum of the internal control signal and the test mode signal; N number of gate circuits that are supplied with the input data applied to the N data input terminals, respectively, the N gate circuits passing the input data applied to the data input terminals when an output of the OR device is active; an internal circuit that is supplied with outputs of the N gate circuits; a first stage AND device having a first input that is supplied with an output of a first one of the N gate circuits and a second input that is supplied with the test mode signal; and second through Nth stage AND devices respectively having first inputs that are supplied with outputs of second through Nth ones of the N gate circuits, respectively, and second inputs that are supplied with outputs of immediately preceding ones of the first through Nth stage AND devices, respectively.