Patent ID: 6887757
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A method of fabricating a flash memory device, comprising the steps of: providing a substrate partitioned into a memory cell region and a peripheral circuit region; forming a tunnel dielectric layer over the memory cell region and forming a liner layer over the peripheral circuit region; forming a first conductive layer over the substrate; patterning the first conductive layer over the memory cell region to form a gate conductive layer; forming an inter-gate dielectric layer over the substrate; forming a silicon nitride layer over the inter-gate dielectric layer; removing portions of the silicon nitride layer, the inter-gate dielectric layer, the first conductive layer and the liner layer from the peripheral circuit region; forming a gate dielectric layer over the peripheral circuit region and converting the remaining portion of the silicon nitride layer over the memory cell region into an oxide layer; forming a second conductive layer over the substrate; and patterning the second conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region to form a plurality of memory gates, and patterning the second conductive layer over the peripheral circuit region to form a plurality of gates.