Patent ID: 7538417
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor chip having a main surface, wherein the main surface has a first area, and a second area located outside and adjacently to the first area; first, second and third electrode pads formed on the main surface in the second area, wherein the first, second and third electrode pads are aligned with each other and wherein the second electrode pad is located between the first and third electrode pads; a first insulating layer formed on the main surface in the first and second areas, wherein the first, second and third electrode pads are exposed from the first insulating layer; a first exterior terminal formed above a top surface of the first insulating layer in the first area; a second exterior terminal formed above the top surface of the first insulating layer in the first area; a first conductive pattern extending on the top surface of the first insulating layer, the first conductive pattern electrically connected to the second electrode pad, and electrically connected to the second exterior terminal; a second insulating layer formed on the first insulating layer and on the first conductive pattern; and a second conductive pattern extending on a top surface of the second insulating layer, the second conductive pattern electrically connected to the first and third electrode pads and the first exterior terminal, wherein the second conductive pattern is positioned along lateral sides of the second exterior terminal to entirely surround the second exterior terminal.