Patent ID: 6482708
Filing Date: 2002-11-19
Classification: G11C,H01L

Abstract:
A method for manufacturing a nonvolatile memory device comprising:(a) forming a stacked gate where a first insulating layer, a floating gate, a second insulating layer and a control gate are stacked in a cell region of a semiconductor substrate having a cell region and a peripheral circuit region; (b) implanting an impurity and diffusing the impurity to form a drain overlapped by part of the stacked gate; (c) implanting an impurity with a dose lower than that of the drain to form a lightly doped source overlapped by part of the stacked gate; (d) forming a spacer on a sidewall of the stacked gate; (e) forming a photoresist layer pattern on the drain; (f) performing implantation into the lightly doped source using the stacked gate, the spacer and the photoresist layer pattern as a mask to form a highly doped source connected to the lightly doped source, without being overlapped by the stacked gate, wherein the highly doped source has a depth lower than that of the drain.