Patent ID: 8564352
Filing Date: 2013-10-22
Classification: H03K,H04L

Abstract:
1. A phase interpolator circuit, comprising: an interpolator core that generates an output clock signal by interpolating between at least a phase of a first input clock signal and a phase of a second input clock signal, wherein the phase of the first input clock signal is earlier than the phase of the second input clock signal, wherein the interpolator core performs interpolation by detecting an arrival of an edge of the first input clock signal and in response to said detecting, by switchably connecting a first current source to an output node to apply a first current that charges a capacitance of the output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator circuit, and by detecting an arrival of an edge of the second input clock signal and in response to said detecting, by switchably connecting a second current source to the output node to apply a second current that charges the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator circuit; and a controller that controls the first current source to generate a first current having a variable magnitude that is selected to adjust a timing at which the capacitance at the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator circuit and thereby adjust a phase shift of the output clock signal output from the voltage comparator circuit.