Patent ID: 9026060
Filing Date: 2015-05-05
Classification: H03F,H04B

Abstract:
1. An apparatus comprising: a first matching circuit having an input connected to a node and an output connected to an input of a first amplifier, the first matching circuit translates on-state and off-state impedances of the first amplifier to first translated on-state and off-state impedances at the input of the first matching circuit; a second matching circuit having an output connected to the node and an input connected to an output of a second amplifier, the second matching circuit translates on-state and off-state impedances of the second amplifier to second translated on-state and off-state impedances at the output of the second matching circuit; the second translated off-state impedance configured to reduce power loss associated with a first signal flowing in a first signal path between the node and the input of the first matching circuit; and the first translated off-state impedance configured to reduce power loss associated with a second signal flowing in a second signal path between the output of the first matching circuit and the node.