Patent ID: 8976164
Filing Date: 2015-03-10
Classification: G09G

Abstract:
1. A circuit for eliminating shutdown afterimages of a display, including a plurality of stages of time division circuits, the time division circuit in each stage comprises: a comparator, a MOS transistor, a first resistor, a second resistor, a third resistor and a capacitor, wherein a first terminal of the first resister serves as a first input terminal of the time division circuit of the stage, and a second terminal thereof serves as an output terminal of the time division circuit of the stage; a first terminal of the second resistor is connected with a second terminal of the third resistor, a second terminal of the second resistor serves as a second input terminal of the time division circuit of the stage, and a first terminal of the third resistor is grounded; an non-inverting terminal or an inverting terminal of the comparator is connected with a second terminal of the capacitor and the second terminal of the third resistor, the inverting terminal or the non-inverting terminal of the comparator is connected with a reference voltage of the time division circuit of the stage, an output terminal of the comparator is connected with a gate of the MOS transistor, a drain of the MOS transistor is connected with the second terminal of the first resistor; a first terminal of the capacitor is grounded; and the inverting terminals of the comparators of the time division circuits in each stage are connected with each other, the non-inverting terminals are also connected with each other, and the first input terminals of the time division circuits in each stage are shared, and the second input terminals of the time division circuits in each stage are also shared.