Patent ID: 6728086
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A power-rail ESD protection circuit with a dual trigger design, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line;the power-rail ESD protection circuit comprising: a control circuit, which is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage; and a NMOS device, whose source and drain are respectively connected to the first power line and the second power line, whose substrate is coupled to receive the substrate-triggering voltage, and whose gate is coupled to receive the gate-driving voltage, for bypassing ESD current from the first power line and the second power line, wherein the control circuit includes N serially-cascaded diodes, wherein the positive end of the first diode is connected to the first power line and the negative end of the last diode is connected to the second power line, and wherein the positive end of the (A)th diode is connected to the substrate of the NMOS device, and the positive end of the (B)th diode is connected to the gate of the NMOS device, where A and B are predetermined to allow the positive end of the (A)th diode to supply the substrate-triggering voltage and the positive end of the (B)th diode to supply the gate-driving voltage; and wherein in the event of ESD in the first power line and the second power line, the substrate-triggering voltage applied to the substrate of the NMOS device is greater than the gate-driving voltage applied to the gate of the NMOS device.