Patent ID: 7674658
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, comprising: providing a substrate; forming a first semiconductor pattern and a second semiconductor pattern on the substrate; forming sequentially a gate insulation layer and a gate metal layer on the substrate to cover the first semiconductor pattern and the second semiconductor pattern; forming a first mask pattern and a second mask pattern on the gate metal layer, wherein the first mask pattern is located over the first semiconductor pattern and exposes a first source/drain region of the first semiconductor pattern correspondingly, and the second mask pattern is located over the second semiconductor pattern and exposes a second source/drain region of the second semiconductor pattern correspondingly; using the first mask pattern and the second mask pattern as masks to pattern the gate metal layer so as to form a first gate pattern and a second gate pattern respectively; using the first mask pattern, the first gate pattern, the second mask pattern and the second gate pattern as masks to perform a first type ion doping process on the first source/drain region and the second source/drain region so that the first source/drain region and the second source/drain region have a first conductive state; performing an etching process on the first mask pattern and the second mask pattern to remove a portion of exterior walls of the first mask pattern and the second mask pattern so that a portion of the first gate pattern and a portion of the second gate pattern are exposed; using the remaining first mask pattern and the remaining second mask pattern as masks to etch the first gate pattern and the second gate pattern so as to form a first gate and a second gate and correspondingly exposing a first lightly doped region beside the first source/drain region in the first semiconductor pattern and a second lightly doped region beside the second source/drain region in the second semiconductor pattern; using the first gate and the second gate as masks to perform a first type ion light doping process in the first lightly doped region and the second lightly doped region so that the first lightly doped region and the second lightly doped region have a first conductive state; removing the remaining first mask pattern and the remaining second mask pattern; forming a patterned mask layer on the substrate, the patterned mask layer exposing correspondingly the second semiconductor pattern; using the patterned mask layer to perform a second type ion counter-doping process in the second source/drain region and the second lightly doped region so as to transform the conductive state of the second source/drain region and the second lightly doped region from the first conductive state to a second conductive state; and removing the patterned mask layer.