Patent ID: 6208907
Filing Date: 2001-03-27
Classification: G06F,H03K

Abstract:
A method for creating an integrated circuit, said method comprising the steps of:preparing a mask set for fabricating an integrated circuit, said mask set including transistor layout masks and a transistor interconnection layer mask, said interconnection layer mask being designed to effect connections between transistors defined by said transistor layout masks in a first circuit configuration, said first circuit configuration including a clock terminal arranged for receiving a clock signal, said first circuit configuration being selectively operable to provide a predetermined logic function, said predetermined logic function being synchronized relative to said clock signal; andproviding at least one unconnected transistor device in said transistor layout masks, said unconnected transistor being arranged to be unconnected in said first circuit configuration, said unconnected transistor device being arranged to be selectively connected within a second configuration of said integrated circuit by modification of only said transistor interconnection layer mask, said second circuit configuration being disconnected from said clock terminal, said second circuit configuration being selectively operable to provide said predetermined logic function in a manner which is unsynchronized relative to said clock signal.