Patent ID: 8729636
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. An integrated circuit comprising a substrate carrying at least one transistor comprising an alternating grid of source and drain regions separated by a grid of gate regions, wherein the respective source regions are vertically connected to a first metal layer and the respective drain regions are vertically connected to a second metal, at least one of the first metal layer and the second metal layer comprising a metal grid of a plurality of interconnected metal portions arranged such that said grid comprises a plurality of gaps for connecting respective substrate portions to a further metal layer; and wherein the grid comprises a plurality of unit cells, each unit cell comprising a grid of N building blocks, N being an integer having a value of at least four, said N building blocks comprising a single substrate contact and (N−1) source and drain regions, the source and drain regions of the unit cells being separated by at least a part of the grid of gate regions.