Patent ID: 7605032
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A method for forming an integrated circuit comprising a transistor, the method comprising: forming a trench in a semiconductor substrate of a first conduction type; forming a gate dielectric on the substrate in the trench; forming a first conductive filling in the trench as a gate electrode on the gate dielectric; removing a portion of the first conductive filling in the french down to a depth below the substrate surface; forming doped regions by introducing impurities of a second conduction type into the surface of the substrate in the trench; the doped regions extending to a depth at least as far as a surface of the first conductive filling; forming an insulation spacer above the first conductive filling in the trench; and forming a second conductive filling in the trench as an upper part of the gate electrode; the second conductive filling being in electrical contact with the first conductive filling and being electrically insulated from the doped regions by the insulation spacer.