Patent ID: 7224635
Filing Date: 2007-05-29
Classification: G11C

Abstract:
1. A memory system comprising: a memory cell, the memory cell including: a first and a second inverter, the first and second inverters being cross-coupled to form a memory cell latch loop, the memory cell latch loop having a true output and a complementary output; a first write port, the first write port configured to be coupled to the true output of the memory cell latch loop, the first write port coupled to a first bitline and a wordline; a second write port, the second write port configured to be coupled to the complementary output of the memory cell latch loop, the second write port coupled to a second bitline and the wordline, each of the first and second write ports having a two-transistor stack with an input coupled to the memory cell latch loop at either the true output or the complementary output; and a first read port, the first read port configured to be coupled to a single read bitline, the first read port coupled to the complementary output of the memory cell latch loop and a first read wordline, the first read port being a two-transistor stack.