Patent ID: 6087222
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method of forming a vertical transistor FET memory device comprising:forming a set of trenches each having trench sidewalls and a trench bottom in a semiconductor substrate,forming threshold implant regions in said substrate within said trench sidewalls,ion implanting doped drain regions in said substrate near the surface of said substrate and ion implanting doped source regions in the base of said substrate below said trenches with oppositely doped channel regions in said substrate therebetween,forming a tunnel oxide layer over said substrate including said trenches,forming a blanket thick floating gate layer of doped polysilicon over said tunnel oxide layer filling said trenches and extending above said trenches,etching said floating gate layer down below the top of said trenches,forming an interelectrode dielectric layer over said floating gate layer and over said tunnel oxide layer,forming a blanket thick control gate layer of doped polysilicon over said interelectrode dielectric layer, andpatterning said control gate layer.