Patent ID: 6380839
Filing Date: 2002-04-30
Classification: H01C,Y10T

Abstract:
A method of fabricating an electronic device, comprising the steps of:(1) providing a laminated structure comprising a conductive polymer PTC layer sandwiched between first and second metal layers; (2) isolating selected areas of the first and second metal layers to form, respectively, first and second arrays of electrode strips; (3) forming a pattern of thermal stress relief areas in each of the electrode strips in the first and second arrays; (4) forming a first plurality of insulation areas on the exterior surface of each of the first array of electrode strips and a second plurality of insulation areas on the exterior surface of each of the second array of electrode strips; (5) forming a plurality of first terminals, each electrically connected to one of the electrode strips in the first array, and a plurality of corresponding second terminals, each electrically connected to one of the electrode strips in the second array, each of the first terminals being isolated from a corresponding second terminal by one of the first plurality of insulation areas and one of the second plurality of insulation areas; and (6) separating the laminated structure into a plurality of devices, each comprising a conductive polymer layer sandwiched between a first electrode formed from one of the electrode strips in the first array and a second electrode formed from one of the electrode strips in the second array; a first terminal in electrical contact with the first electrode; and a second terminal in electrical contact with the second electrode.