Patent ID: 7188044
Filing Date: 2007-03-06
Classification: G01R

Abstract:
1. A coordinated testing system for simultaneously testing a plurality of integrated circuit (IC) devices, the testing system comprising: a plurality of IC test devices, each IC test device operable to perform a first test scheme on a first IC device under test by said IC test device, said first test scheme including one or more different tests available to be performed on said first IC device under test by said IC test device, such that one or more of said plurality of different tests available to be performed by said IC test device may be idle during performance of said first test scheme on said first IC device under test, each of the plurality of IC test devices being physically located at a geographical site that is distinct from the geographical location of the remainder of the plurality of IC test devices; a distribution engine connected to each of the plurality of IC test devices for monitoring the IC test devices to identify idle tests in the plurality of IC test devices and to utilize the plurality of IC test devices to combine the idle tests to perform a second test scheme on a second IC device under test.