Patent ID: 6985484
Filing Date: 2006-01-10
Classification: H04L

Abstract:
1. An apparatus for transmitting packets of data concurrently between a plurality of devices, comprising: a switching matrix having a plurality of ports programmed to route packets from a source port to one of several destination ports, wherein the packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification; a first device coupled to the switching matrix; a second device coupled to the switching matrix; a third device coupled to the switching matrix, wherein the third device can transmit a first packet to the first device or the second device while the second device transmits a second packet to either the first device or the third device and while the first device transmits a third packet to either the second device or the third device, wherein each packet includes a coherent transaction bit that determines whether a packet is to be included in a coherent memory operation.