Patent ID: 6830953
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A method for forming a MOSFET type semiconductor device having significantly reduced leakage currents in either direction between a gate electrode and source, drain and channel regions formed within a semiconductor substrate, comprising:providing a substrate of a first semiconductor material; forming a pair of spaced apart source and drain regions of a first conductivity type in said substrate; forming a channel region of a second conductivity type between said source and drain regions, said channel region having an electron affinity &khgr;C; forming a dielectric layer on the substrate, said dielectric layer covering at least said channel region; forming a gate electrode on the dielectric layer, said gate electrode being formed of a second semiconductor material having an electron affinity &khgr;G and said electrode being formed substantially over the channel region but with the possibility of overlapping said source and drain regions; and wherein &khgr;G is less than &khgr;C.