Patent ID: 8625381
Filing Date: 2014-01-07
Classification: H01L

Abstract:
1. A stacked semiconductor device comprising a stacked plurality of n chips, wherein each chip comprises: the j first upper electrodes are configured to receive a previous identification code from a lower adjacent chip in the stacked plurality of n chips, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code, and the current identification code is applied through the j lower electrodes and j first TSVs to communicate the current identification code to the upper adjacent chip, wherein each chip further comprises: an identification code decoder configured to receive the current identification code from the identification code generator and decode the current identification code to generate an n-bit chip code; a chip selection code transmitter comprising a second upper electrode disposed on the first layer and a second TSV disposed under the second upper electrode and configured to receive a chip selection code from an external source or an adjacent chip in the stacked plurality of n chips; and a selection signal generator receiving the n-bit chip code and the chip selection code and configured to enable a chip selection signal when an n-bit chip selection signal corresponding to the chip selection code matches the n-bit chip code.