Patent ID: 7018781
Filing Date: 2006-03-28
Classification: H01L

Abstract:
1. A method for fabricating a first contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, comprising: A) providing a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on a surface of the semiconductor; B) producing an insulator layer on the semiconductor surface; C) forming a sacrificial layer on the insulator layer, where regions between the mutually adjacent gate electrode tracks are essentially filled and the gate electrode tracks are covered; D) forming material plugs on the sacrificial layer for defining a first set of contact openings between the mutually adjacent gate electrode tracks; E) anistropically etching the sacrificial layer, where the material plugs with the underlying sacrificial layer blocks; F) producing a vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, where the regions between the mutually adjacent gate electrode tracks are essentially filled and an essentially planar surface is formed, wherein step F comprises the following steps F1–F6: G) etching sacrificial layer material from the vitreous layer for removing the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks; H) removing the uncovered insulator layer above the first set of contact openings on the semiconductor surface between the mutually adjacent gate electrode tracks; and I) filling the contact opening regions with a conductive material, in the process forming an essentially planar surface with the surrounding vitreous layer.