Patent ID: 6258643
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method for fabricating a twin gate CMOS, said method comprising:providing a semiconductor substrate incorporating a device;forming isolations in the semiconductor substrate;forming a P-well and N-well on two sides of said isolation;forming a gate oxide layer above said P-well and N-well;forming a polysilicon layer in-situ doped with first conductivity-type ions above said gate oxide layer;in order forming a first dielectric layer and a first photoresist layer above said polysilicon layer, wherein etching respective patterns on said first dielectric layer and said polysilicon layer until the said gate oxide is exposed, wherein the remained polysilicon layer defines a N.sup.+ -type gate area of CMOS circuits;depositing a amorphous silicon layer, and then doped with second conductivity-type ions by implantation on said gate oxide layer above said semiconductor substrate;forming a second dielectric layer on said amorphous silicon layer;depositing a SOG (spin-on glass) layer above the semiconductor substrate;removing said SOG layer, major said second dielectric layer, and a portion of said amorphous silicon layer until said first dielectric layer is exposed by chemical mechanical polishing; andetching back the bulgy amorphous silicon layer, and then etch the first dielectric layer and second dielectric layer until upper portion of the N.sup.+ -type polysilicon layer and P.sup.+ -type amorphous silicon layer are exposed, wherein said amorphous silicon layer to define a P.sup.+ -type gate area of CMOS circuits.