Patent ID: 6677786
Filing Date: 2004-01-13
Classification: G06F

Abstract:
The frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency, the frequency rate multiplier comprising:an accumulator register to store, based upon a first clock signal at said input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, wherein the first most significant bit is outputted as the output of the frequency rate multiplier; a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add said accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first and a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register, wherein the secondary adder is an increment adder.