Patent ID: 7645687
Filing Date: 2010-01-12
Classification: H01L

Abstract:
1. A method of fabrication of variable work function gates in a FUSI device comprising the steps of: providing a substrate having a NMOS region and a PMOS region; forming a gate dielectric layer over the substrate; forming a gate electrode layer over the gate dielectric layer; performing a pre-dope gate layer implant process to implant impurities into the gate electrode layer; forming a cap layer over the gate electrode layer after the pre-dope gate layer implant process; patterning the cap layer, the gate electrode layer and the gate dielectric layer to form a NMOS gate structure in the NMOS region and a PMOS gate structure in the PMOS region; forming NMOS source/drain (S/D) regions in the NMOS region adjacent to the NMOS gate structure and forming PMOS S/D regions in the PMOS region adjacent to the PMOS gate structure, wherein a thickness of the cap layer is selected to enable doping of the gate electrode layer of the NMOS and PMOS gate structure through the cap layer according to workfunction requirements during formation of the S/D regions; forming silicon layers over the NMOS and PMOS S/D regions; depositing a metal over the substrate and the NMOS gate and the PMOS gate; and annealing the substrate to form fully silicided NMOS gate with raised silicided NMOS S/D regions and a fully silicided PMOS gate with raised silicided PMOS S/D regions.