Patent ID: 9092322
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. A processor system comprising: a first storage unit that is composed of a plurality of electrically rewritable non-volatile memory cells; a second storage unit that stores an access prohibit flag, the access prohibit flag being capable of SW itching value from a first value to a second value; a first processor that issues an access request to the first storage unit and authentication information corresponding to the access request; a second processor that evaluates whether or not the authentication information issued from the first processor is valid; a copy register that stores a value corresponding to the first value when a value of the access prohibit flag is the first value and stores a value corresponding to an evaluation result by the second processor when the value of the access prohibit flag is the second value; and an access control circuit that controls whether or not to allow access from the first processor to the first storage unit based on the value stored to the copy register.