Patent ID: 8861586
Filing Date: 2014-10-14
Classification: H04N

Abstract:
1. A system comprising: a processor; and memory coupled to the processor, the system configured to execute a decoder that decodes frames of encoded data, the decoder comprising: wherein the decoded first frame is identified as an in-order frame if macroblocks in the encoded first frame arrive at the decoder in a specified order and otherwise the decoded first frame is identified as an out-of-order frame, and wherein the decoded first frame is identified as a reference frame if another frame relies on information in the decoded first frame for decoding and otherwise the decoded first frame is identified as a non-reference frame; and wherein the second deblocker is selected to deblock the decoded first frame if the decoded first frame is classified as an out-of-order non-reference frame and otherwise the first deblocker is selected to deblock the decoded first frame.