Patent ID: 6792581
Filing Date: 2004-09-14
Classification: G06F

Abstract:
A method comprising:for an integrated circuit model, identifying a lazy cut-point frontier and an eager cut-point frontier, the lazy cut-point frontier being one of inputs of the model and a cut-point frontier closest to a prior cut-point frontier and the eager cut-point frontier being a cut-point frontier closest to outputs of the model, each of the lazy and eager cut-point frontiers being associated with a set of variables indicating signal lines that pass through the respective cut-point frontier; computing a ratio of one of reconverging and non-reconverging variables to a total number of variables for each of the identified lazy and eager cut-point frontiers, a reconverging variable identifying a signal line that has a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line, a non-reconverging variable identifying a signal line that does not have a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line; and selecting from the lazy and eager cut-paint frontiers based on the computed ratios.