Patent ID: 9000511
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a substrate having an active region defined by a device isolation region, the device isolation region having a trench and an air gap, a sidewall of the trench being straight from a top to a bottom of the trench such that a width of the trench decreases with increasing depth; a device isolation pattern positioned at a lower portion of the trench such that the air gap is positioned at an upper portion of the trench conformal to the straight sidewall of the trench; a memory cell layer including insulation layers of a tunnel insulation layer, a trap insulation layer and a blocking insulation layer, wherein the insulation layers are sequentially stacked on the active region, wherein a top of the air gap is defined by at least one layer of the insulation layers and a bottom of the air gap is defined by a layer other than the at least one layer of the insulation layers, wherein the at least one layer defining the top of the air gap extends from the active region toward the device isolation region; and a control gate electrode positioned on the cell structure.