Patent ID: 7349956
Filing Date: 2008-03-25
Classification: G06F,H04L

Abstract:
1. A computer circuit coupled to a data bus and communicating with a Host PC, comprising: a video input buffering circuit receiving RGB video signals from the Host PC; an analog to digital converter circuit coupled to the video input buffering circuit to receive and digitize the RGB video signals; a main gate array circuit to receive the digitized RGB video signals from the analog to digital converter circuit; a video memory circuit to store the digitized RGB video signals; a second gate array circuit coupled to the main gate array circuit, the second gate array circuit bridging data between the main gate array circuit and the data bus; a system clock circuit providing clock signals to the main and second gate array circuits; a main cpu, communicating with the main and second gate array circuits to direct data between the video memory circuit and the second gate array circuit, the main gate array also controlling data traffic between the analog to digital converter circuit, the video memory circuit, and the main cpu; a keyboard cpu in communication with the main cpu and at least one of an external keyboard and an external mouse; and a pixel clock generator to provide a pixel clock signal to the analog to digital converter circuit, the pixel clock generator reproducing in frequency and phase a host pixel clock signal used by the Host PC to produce the RGB video signals received by the video input buffering circuit.