Patent ID: 6320420
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A dynamic logic element comprising:a dynamic logic circuit portion producing an output signal in response to an input signal by performing a precharge operation and a discharge operation at a dynamic node; anda detecting circuit portion which stops said precharge operation at said dynamic node when a potential level of said dynamic node reaches a predetermined potential level, wherein said detecting circuit portion comprises:a MOS transistor of a first channel type which has a source terminal coupled to a power supply terminal, a gate terminal coupled to an output terminal of said dynamic logic element, and a drain terminal coupled to a dynamic node for retaining a precharge condition; anda MOS transistor of a second channel type which has a drain terminal coupled to said dynamic node for retaining a precharge condition, a gate terminal coupled to a clock input terminal of said dynamic logic element, and a source terminal coupled to a the ground terminal, said second channel type being opposite to said first channel type; andsaid dynamic logic element comprises a first channel type MOS transistor for precharging, a plurality of second channel type MOS transistors constituting a MOS logic network, a second channel type MOS transistor for discharging and an inverter element;wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power terminal, a gate terminal coupled to said dynamic node for retaining a precharge condition, and a drain terminal coupled to a dynamic node for retaining an output signal;wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and a drain terminal of said second channel type MOS transistor for discharging;wherein a source terminal of said second channel type MOS transistor for discharging is coupled to the ground terminal, and a gate terminal of said second channel type MOS transistor is coupled to said dynamic node for retaining a precharge condition; andwherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal.