Patent ID: 6262579
Filing Date: 2001-07-17
Classification: B23K,H01L,H05K

Abstract:
A method for testing for open circuits on et two-sided common circuit base, said method comprising:(a) providing a two-sided common circuit base having (i) upper and lower major surfaces, (ii) a plurality of plated ugh holes traversing through said common circuit base, said plated through holes having an exposed contact surface on said lower major surface, and (iii) a thin film metal interconnect structure formed over said upper major surface, said thin film interconnect structure including an upper dielectric layer deposited over a thin film metalization layer and having contact openings etched through said dielectric layer at selected locations, (iv) wherein every exposed contact surface on said lower major surface is electrically connected to metalization in at least one of said contact openings;(b) forming a seed layer over said upper dielectric layer and over said contact openings;(c) forming a photoresist layer over said seed layer and patterning said photoresist layer to expose selected portions of said seed layer, wherein said selected portions correspond generally to said contact openings and define locations at which upper contact pads are formed on said common circuit base;(d) performing a plating operation to simultaneously plate first and second conductive layers over said common circuit base, wherein said first conductive layer is plated over exposed portions of said seed layer in areas where upper contact pads are formed and said second conductive layer is plated over said exposed contact surfaces on said lower major surface in areas where lower contact pads are formed; and(e) inspecting the bottom of said common circuit base for open circuits.