Patent ID: 7906806
Filing Date: 2011-03-15
Classification: H01L

Abstract:
1. Non-volatile memory device comprising at least one memory cell on a substrate in a semiconductor material, each memory cell comprising: a channel region in between two doped regions of said substrate; a floating gate above said channel region, said floating gate comprising at least two layers constructed in different conductive or semiconductive materials; a first dielectric separating the floating gate from the substrate, said first dielectric being constructed in one or more dielectric materials and having predetermined properties enabling charge transfer by tunnelling between the channel region and the floating gate upon programming and erasing the cell; a control gate above said floating gate, said control gate being constructed in one or more conductive or semiconductive materials; a second dielectric separating the control gate from the floating gate, said second dielectric being constructed in one or more dielectric materials and having predetermined properties for suppressing charge transfer between the floating gate and the control gate; a first interface being defined as the contact surface between the channel region and the first dielectric; a second interface being defined as the contact surface between the first dielectric and the floating gate; a third interface being defined as the contact surface between the floating gate and the second dielectric; a fourth interface being defined as the contact surface between the second dielectric and the control gate; wherein at least two of the layers of the floating gate are separated by an intermediate dielectric layer having a predetermined thickness enabling direct tunnelling current between the layers; and wherein an overlap of the control and floating gates is larger than an overlap of the floating gate and the channel.