Patent ID: 6262447
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A two-dimensional array of single polysilicon DRAM cells comprising:a plurality of DRAM cells arranged in a two-dimensional matrix, each of said DRAM cells comprising:(1) a deep n-well in a silicon substrate;(2) a p-well within said deep n-well;(3) a gate structure over and straddling said deep n-well and said p-well, said gate structure being a stack of a thin gate oxide layer and a conductive layer; and(4) a n.sup.+ region within said p-well and adjacent to a sidewall of said gate structure;a plurality of column bitlines, each of said plurality of column bitlines connected to the n.sup.+ regions of all of said DRAM cells that are in a common column;a plurality of row wordlines, each of said plurality of row wordlines connected to the gate structures of all of said DRAM cells that are in a common row.