Patent ID: 6944074
Filing Date: 2005-09-13
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a normal word line block including a plurality of normal word lines, each of the plurality of normal word lines being coupled to a normal memory cell; a redundant word line block including a plurality of redundant word lines, each of the plurality of redundant word lines being coupled to a redundant memory cell and configured to replace a fail normal word line of the plurality of normal word lines, the fail normal word line being coupled to a fail memory cell; a comparator configured to compare a first address and a second address associated with the fail normal word line coupled to the fail memory cell, and generate a redundant word line enable signal if the first address and the second address are the same; a row decoder and word line driver coupled to the normal word line block, the row decoder and word line driver being configured to select a normal word line from the plurality of normal word lines according to the first address; and a redundant row decoder and word line driver coupled to the redundant word line block and the comparator, the redundant row decoder and word line driver being configured to select a redundant word line corresponding to the first address based on the redundant word line enable signal, wherein when the first address and the second address are the same during a refresh operation and a normal operation, the fail normal word line is selected by the row decoder and word line driver at the same time as the redundant word line is selected by the redundant row decoder and word line driver.