Patent ID: 8692605
Filing Date: 2014-04-08
Classification: H03K

Abstract:
1. A receiving circuit for a core circuit comprising: a first receiving-path unit capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal; wherein the first receiving-path unit comprises: an input buffer capable of operating in a core power domain and receiving a first clamped signal; a switch controlled by an enable signal and having an input terminal receiving the input signal and an output terminal providing the first clamped signal to the input buffer; wherein when a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the enable signal is asserted, and the switch is capable of being turned on according to the asserted enable signal to pass the input signal to the output terminal to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal; wherein when the level of the input signal is higher than the first predetermined voltage level, the enable signal is de-asserted, the switch is capable of being turned off according to the de-asserted enable signal, and the output terminal provides the first clamped signal whose level is substantially equal to a level of the enable signal; wherein the enable signal is generated according to an input/output (I/O) power voltage and an I/O ground voltage and a core power voltage.