Patent ID: 7935578
Filing Date: 2011-05-03
Classification: H01L

Abstract:
1. A method of manufacturing a thin film transistor array panel, the method comprising: forming a first electrode and a second electrode that are separated from each other on a substrate; forming a silicon layer comprising amorphous silicon and polycrystalline silicon on the substrate, the silicon layer having a lower portion and an upper portion, wherein a ratio of polycrystalline silicon to amorphous silicon in the lower portion is different than a ratio of polycrystalline silicon to amorphous silicon in the upper portion; forming a semiconductor by patterning the silicon layer; forming a gate insulating layer on the semiconductor; forming a third electrode to overlap the semiconductor on the gate insulating layer; forming a passivation layer on the third electrode; and forming a pixel electrode on the passivation layer, wherein the upper portion is nearer to the third electrode than the lower portion, and wherein forming the silicon layer comprises forming a seed layer utilizing a mixture gas of an inactive gas and a hydrogen gas in a reaction chamber, and then subsequently growing the silicon layer on the seed layer by introducing the inactive gas in an absence of hydrogen gas in the reaction chamber.