Patent ID: 7895327
Filing Date: 2011-02-22
Classification: G06F,G09C,H04L

Abstract:
1. An integrated circuit comprising: a signal modifier to introduce a pseudo-randomly selected modification to a state-transition pattern of at least one signal which is involved in internal processing of secret data within said integrated circuit, wherein the signal modifier is to obfuscate said secret data processed within a hardware implementation of said integrated circuit and to protect said secret data from a side-channel attack; and control logic adapted to regulate said signal modifier such that a different pseudo-randomly selected signal modification is introduced intermittently, wherein the secret data obfuscated within said integrated circuit comprises at least one of: (a) an encryption key; (b) decrypted data resulting from decrypting, within said integrated circuit, of encrypted input data; wherein the signal modifier is to distort, during operation of a logical circuit within said integrated circuit, a timing of a power consumption spike of said logical circuit; wherein the signal modifier is implemented using at least a hardware component.