Patent ID: 6605505
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A process for producing an integrated semiconductor memory configuration, which comprises:providing a configuration of selection transistors having source regions and an insulation layer formed with contact holes extending through to the source regions; subsequently providing first contact plugs in the contact holes; subsequently applying at least one first electrode on a surface of the insulation layer; and forming the first electrode with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes; subsequently depositing a dielectric layer on the surfaces of the first contact plugs, the regions of the surface of the insulation layer adjacent the contact holes, and the first electrode; subsequently depositing a second layer of electrode material on the dielectric layer; subsequently separating the second layer of electrode material into sections to produce second electrodes; subsequently exposing the surfaces of the first contact plugs by etching the dielectric layer and the second electrodes and removing oxidized regions of the contact plugs; and subsequently producing second contact plugs above the exposed first contact plugs electrically connecting a respective one of the second electrodes to a respective one of the first contact plugs.