Patent ID: 7682919
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A method in the fabrication of an integrated circuit including a PMOS varactor and a vertical bipolar npn transistor, said method comprising the steps of: providing a p-doped substrate; simultaneously forming a buried n+-doped region for the PMOS varactor and a buried n+-doped region for the npn transistor in said substrate; simultaneously forming in said substrate an essentially n-doped region above the buried n+-doped region for the PMOS varactor and an n-doped region above the buried n+-doped region for the npn transistor; simultaneously forming field isolation areas, in a horizontal plane, around said n-doped regions; forming a PMOS gate region on said essentially n-doped region for the PMOS varactor; forming a p-doped base in the n-doped region above the buried n+-doped region for the npn transistor and an n-doped emitter in the p-doped base; simultaneously forming an n-doped contact to the buried n+-doped region for the PMOS varactor and an n-doped collector contact to the buried n+-doped region for the npn transistor; said contacts being separated from, in a horizontal plane, said n-doped regions; and forming a gate terminal connected to the PMOS gate region and a bulk terminal connected to the n-doped bulk contact.