Patent ID: 7453736
Filing Date: 2008-11-18
Classification: G11C

Abstract:
1. A method of erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the erasing method comprising: applying an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from the program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage; wherein the time interval is determined by performing the following: performing an endurance test of a memory cell using an initial time interval; attempting to successfully read the memory cell; and repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval, based upon whether the attempting was able to successfully read the memory cell.