Patent ID: 8666690
Filing Date: 2014-03-04
Classification: G01R,G06F

Abstract:
1. A multi-core integrated circuit, comprising: a plurality of processor cores including a first set of processor cores and a second set of processor cores, wherein the first and second sets of processor cores include corresponding first and second sets of test access ports (TAPs); a plurality of TAP controllers corresponding to the plurality of processor cores, wherein the plurality of TAP controllers includes first and second TAP controllers connected to the first and second sets of processor cores respectively, and wherein the first and second TAP controllers connect the corresponding first and second sets of TAPs to corresponding first and second debug ports of the multi-core integrated circuit; and a debug control circuit connected between the plurality of TAP controllers and the first and second debug ports, wherein the debug control circuit includes at least one mode select pin for receiving a configuration signal from an external debugging apparatus and generating at least one select signal, wherein the debug control circuit configures the first and second TAP controllers and the corresponding first and second debug ports in a predetermined debugging mode, based on the at least one select signal, and receives input data at at least one of the first debug port and the second debug port from the external debugging apparatus, and routes output debug data to at least one of the first and second debug ports, based on debugging of at least one of the first and second sets of processor cores by the external debugging apparatus.