Patent ID: 6780715
Filing Date: 2004-08-24
Classification: H01L,Y10S

Abstract:
A method for fabricating a memory-logic combined semiconductor device, the method comprising the steps of:(a) providing a substrate having a first region and a second region adjoining the first region; (b) forming a first gate forming material layer in the first region; (c) forming a second gate forming material layer in the second region and in the first region having the first gate forming material layer formed therein; d) selectively patterning the second gate forming material layer simultaneously with completely removing the second gate forming material layer in the first region except in a boundary area between the first and second regions to form second gates in the second region and to form a boundary dummy pattern layer at the boundary area of the first and second regions; and (e) selectively patterning the first gate forming material layer to form first gates in the first region.