Patent ID: 6130853
Filing Date: 2000-10-10
Classification: G11C

Abstract:
An address decoding circuit for decoding from an input address a first output and a second output in the same memory cycle, comprising:a first, a second, and a third class decoder each of said class decoders comprising a first, a second, and a third input and a first and a second output, said class decoders consisting of logic gates for determining classes of memory addressing;a first, a second, a third, and a fourth even pre-decoder with a first and second set of inputs and an output, said first set of inputs connected to said input address, said second set of inputs connected to said outputs of said class decoders, said even pre-decoders consisting of logic gates for selecting even columns of a memory;a first, a second, a third, and a fourth odd pre-decoder with a first and second input and an output for each of said odd pre-decoders, said inputs of said odd pre-decoders connected to said input address, said odd pre-decoders consisting of logic gates for selecting odd columns of said memory;an odd match circuit with a first set of inputs connected to a select circuit, and a second set of inputs connected to said input address, and an output for selecting a redundant odd column of said memory; andan even match circuit with a first set of inputs connected to a select circuit, a second set of inputs connected to said input address, a third set of inputs connected to said first and second outputs of said class decoders, and an output for selecting a redundant even column of said memory.