Patent ID: 6506634
Filing Date: 2003-01-14
Classification: G11C

Abstract:
A method for producing a semiconductor memory device, said method comprising:a memory producing step of integrating and forming a memory circuit having a defective address memory circuit, which includes a first fuse circuit wherein mechanical fuses capable of being cut by a reactive ion etching are arranged, and a second fuse circuit wherein electric fuses capable of electrically cut or short-circuited are arranged; a first programming step of carrying out a first defect analyzing test for said memory circuit and selectively cutting a corresponding fuse of said first fuse circuit by the reactive ion etching in accordance with the result of said first defect analyzing test; and a second programming step of carrying out a second defect analyzing test for said memory circuit and selectively cutting or short-circuiting a corresponding fuse of said second fuse circuit by applying an electric signal thereto in accordance with the result of said second defect analyzing test.