Patent ID: 8607171
Filing Date: 2013-12-10
Classification: G03F

Abstract:
1. A method of modifying a first integrated circuit (IC) layout based on a second IC layout where the second IC layout includes a modification of the first layout, the method being performed by one or more processors, the method comprising: selecting a large block of the second IC layout using the one or more processors; performing, at the one or more processors, a correction operation on the large block, thereby generating a corrected large block; selecting a first small block using the one or more processors, wherein the first small block is a portion of the first layout; selecting a second small block using the one or more processors, wherein the second small block is a portion of the corrected large block; removing the first small block from the first IC layout using the one or more processors; removing all but the second small block from the second IC layout using the one or more processors; and merging the first and second IC layouts using the one or more processors.