Patent ID: 6564353
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A method of designing a clock distributing circuit which distributes and supplies a clock signal from at least one clock-supplying element to a plurality of clock-receiving elements, comprising:a first temporary wiring temporarily wiring a signal line which directly connects said clock-supplying element with each of said clock-receiving elements disposed at predetermined positions, through the shortest path, and fixing the temporary wiring result which should be adopted in after-mentioned final wiring; a first judgment judging whether or not clock skew in said plurality of clock-receiving elements has been optimized by said signal line temporarily wired in said first temporary wiring; a first grouping dividing said plurality of clock-receiving elements into a plurality of groups when it is judged in said first judgement that said clock skew has not been optimized; a first buffer insertion (a) assigning a single buffer to each of said groups obtained by said first grouping, (b) lining-up a plurality of buffer-insertion candidate positions where said buffer can be inserted and disposed, (c) temporarily wiring, for each of the lined-up buffer-insertion candidate positions, both a signal line which connects said buffer, disposed at said buffer-insertion candidate position, with each of said clock-receiving elements belonging to said group through the shortest path, and a signal line which connects said buffer, disposed at said buffer-insertion candidate position, with said clock-supplying element through the shortest path, and fixing the temporary wiring results should be adopted in after-mentioned final wiring, (d) selecting a buffer-insertion candidate position, which can optimize clock skew and clock propagation delay time in said clock-receiving elements belonging to said group, from among said plurality of buffer-insertion candidate positions, based on temporary wiring results obtained for all of said plurality of buffer-insertion candidate positions, to determine the selected buffer-insertion candidate position as a position where said buffer should be actually inserted and disposed, and (e) inserting and disposing said buffer at the selected candidate position, while obtaining the temporary wiring results; and a final wiring determining wiring paths of signal lines which connect said clock-supplying element, said plurality of clock-receiving elements, and said buffer, according to the temporary wiring results obtained in said first temporary wiring and said first buffer insertion; wherein said first temporary wiring, said first judgement, said first grouping, and said first buffer insertion are repeatedly executed, while the buffers inserted into said plurality of groups by said first buffer insertion are being regarded as said plurality of clock-receiving elements, until it is judged in said first judgement that the clock skew has been optimized; and wherein said final wiring is executed when it is judged in said first judgement that the clock skew has been optimized.