Patent ID: 7981755
Filing Date: 2011-07-19
Classification: H01L

Abstract:
1. A method of manufacturing a memory device comprising: providing at least one metal stud positioned in a first via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the first via and the at least one metal stud; etching the at least one metal stud selective to the electrically conductive liner to provide at least one recessed metal stud, wherein the electrically conductive liner extends along an entire length of sidewalls of the at least one recessed metal stud; forming a second dielectric layer atop the at least one recessed metal stud and filling the first via, the second dielectric layer having an upper surface that is coplanar with an upper surface of the first dielectric layer and an upper surface of the electrically conductive liner, wherein the upper surface of the electrically conductive liner is exposed; forming a phase change memory cell within a second via of a third dielectric layer that is present atop the second dielectric layer, wherein the phase change memory cell is in contact with the upper surface of the electrically conductive liner; and forming a barrier metal layer atop the phase change material cell, wherein the barrier metal layer is also present in the second via, wherein sidewalls of the barrier metal layer are aligned with sidewalls of the phase change material cell.