Patent ID: 8942332
Filing Date: 2015-01-27
Classification: H04L

Abstract:
1. A circuit for reducing inter symbol interference, comprising: an inverting device having an input lead and an output lead, wherein said input lead supplies a serial stream of binary data bits which are inverted by said inverting device and output to said output lead; a decision logic circuit including at least one logic gate having a first input connected to said input lead and a second input connected to said output lead, wherein said decision logic circuit produces a first control signal when a low-to-high change in signal level between two consecutive data bits of the serial stream of binary data bits is detected, and wherein said decision logic circuit produces a second control signal when a high-to-low change in signal level between two consecutive data bits of the serial stream of binary data bits is detected; and a pull circuit operatively connected to a first voltage level, a second voltage level, said input lead, and an output of said decision logic circuit, wherein said pull circuit connects said input lead to said first voltage level when said pull circuit receives said first control signal, and wherein said pull circuit connects said input lead to said second voltage level when said pull circuit receives said second control signal.