Patent ID: 6215721
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A multi-bank semiconductor memory device, comprising:a plurality of memory banks arranged in the direction of a row, each memory bank having a plurality of local I/O line pairs extended in a direction of a column, and a plurality of global I/O line pairs extended in a direction of a row;an I/O sense amplifier block disposed between adjacent pairs of said plurality of memory banks, said I/O sense amplifier block having a plurality of I/O sense amplifiers arranged in the direction of a column; anda plurality of column-decoder blocks disposed between each adjacent pair of said memory banks, wherein at least one of said plurality of global I/O line pairs is extended from a first memory bank to an adjacent memory bank and intersects another global I/O line pair on said column-decoder block, and extends on a second memory bank in the direction of an adjacent row.