Patent ID: 8440272
Filing Date: 2013-05-14
Classification: H01L

Abstract:
1. A method for fabricating and testing a semiconductor wafer comprising: providing a silicon substrate, multiple metal oxide semiconductor (MOS) devices in or over said silicon substrate, a first dielectric layer over said silicon substrate and over said multiple MOS devices, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, multiple metal pads over said silicon substrate and over said multiple MOS devices and said first and second dielectric layers, and a passivation layer over said metallization structure, over said first and second dielectric layers and over outer edges of said multiple metal pads, wherein said passivation layer comprises a nitride layer, wherein multiple first openings in said passivation layer expose respective portions of said multiple metal pads; forming multiple metal traces over said passivation layer and on said multiple exposed portions of said multiple metal pads, wherein said multiple metal traces are not on said outer edges of said multiple metal pads, wherein said multiple metal traces have multiple contact points over said passivation layer and being located in a top surface of said multiple metal traces, wherein said multiple contact points are not in vertical alignment with any portion of said multiple exposed portions of said metal pads, wherein each one of said multiple contact points is connected to each one of said respective multiple metal pads via the contact point's corresponding metal trace through one of said multiple first openings, wherein said forming of said multiple metal traces comprises sputtering a titanium-tungsten-alloy layer with a thickness between 0.02 and 0.5 μm over said passivation layer and on said multiple exposed portions of said metal pads, next forming a seed layer with a thickness between 0.02 and 0.3 μm on said titanium-tungsten-alloy layer, next forming a photoresist layer on said seed layer, wherein multiple second openings in said photoresist layer expose multiple regions of said seed layer, next forming a third metal layer with a thickness between 1 and 30 micrometers over said multiple regions, said third metal comprising one or more of gold, copper, nickel, and palladium, next removing said photoresist layer, next removing said seed layer not under said third metal layer, and then etching said titanium-tungsten-alloy layer not under said third metal layer by immersion in an etchant containing hydrogen peroxide at a temperature between 35 and 50 degrees C. with circulation flow; and contacting multiple probe tips of a probe card with some of said multiple contact points to probe said semiconductor wafer.