Patent ID: 8141020
Filing Date: 2012-03-20
Classification: G06F

Abstract:
1. A method of designing a semiconductor chip including a plurality of device-containing layers, said method comprising steps of: optimizing placement of functional blocks in a device-containing layer under a constraint of optimizing interlayer connectivity between said device-containing layer and at least one adjacent device-containing layer that is separated vertically from said device-containing layer; calculating, for a functional block among said functional blocks in said device-containing layer, a value for lateral heat flow between said functional block and at least one adjacent functional block among said functional blocks in said device-containing layer; determining if said value for lateral heat flow is less than a predetermined threshold value; modifying one or more of placement of said functional block, placement of said at least one adjacent functional block, placement of an interlayer interconnect structure array providing electrically conductive paths from said device-containing layer to another device-containing layer, and configuration of said interlayer interconnect structure array only if said value for lateral heat flow is less than said predetermined threshold value; and running a program using a processing device or a processor unit to execute one or more of said optimizing, calculating, determining and modifying steps.