Patent ID: 7178121
Filing Date: 2007-02-13
Classification: G06F

Abstract:
1. A method comprising steps of: (a) providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; (b) providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; (c) calculating and generating as output a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided in step (a); and (d) calculating and generating as output a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided in step (a).