Patent ID: 6150856
Filing Date: 2000-11-21
Classification: G06F,H03L

Abstract:
A delay lock loop comprising:a delay line having first and second inputs and an output, the first input being configured to receive a clock signal;a clock driver having an input coupled to the output of the delay line and configured to drive the delayed clock signal to provide a driven output clock signal at a clock driven output to drive a system;an output model having an input coupled to the clock driver output, and an output, the output model being configured to model delays in the system and provide a modeled delay at the output of the output model;a phase detector having a pair of inputs and an output, the phase detector's output being operably coupled with the second input of the delay line; anda delay element having a first input coupled to the output of the output model, having a second input coupled to the clock signal received by the delay line; and having first and second outputs coupled to the inputs of the phase detector, the delay element being configured to present an additional delay to the phase detector which is in addition to the modeled delay provided by the output model.