Patent ID: 7437500
Filing Date: 2008-10-14
Classification: G11C

Abstract:
1. A core comprising: a write logic intellectual property (IP) block configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM); a read logic IP block configured to communicate data from said double data rate (DDR) synchronous dynamic random access memory (SDRAM) to said memory controller, wherein said read logic IP block comprises a plurality of physical read datapaths, each of the physical read datapaths configured to receive (i) a respective portion of read data signals from the DDR memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal; a master delay IP block configured to receive a reference clock and generate (i) one or more delays for said read logic IP block and (ii) a lock signal; and an address and control logic IP block configured to control said write logic IP block and said read logic IP block, wherein said core is configured to couple said double data rate (DDR) synchronous dynamic random access memory (SDRAM) and said memory controller.