Patent ID: 8589763
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. A cache memory system, comprising: a cache memory to store data containing a tag division and a data division; an error detection unit to detect an error in the tag division and the data division; and a control unit to control the cache memory in a write through manner by defining a signal of a result of a logical product of a signal indicating that there is a cache hit in cache hit information in the tag division and a signal indicating that there is no error detected in an error detecting process by the error detection unit as cache hit information to be transmitted to a CPU, wherein data of an address corresponding to data in the cache memory in which an error has occurred is read from the main memory when the error has occurred as in a case in which there is a cache mishit, and the data in the cache memory which has caused the error is replaced with the read data.