Patent ID: 6255844
Filing Date: 2001-07-03
Classification: G01R

Abstract:
A semiconductor testing apparatus comprising:a plurality of testing circuits each of which can be coupled to a predetermined maximum number of terminals of a different respective one of a plurality of devices under test, wherein each testing circuit is configured to supply testing signals to terminals of the respective device under test, to subject the signals received from terminals of the respective device under test to testing, and to provide output signals indicative of whether the signals from the terminals are satisfactory;an additional testing circuit that can be coupled simultaneously to additional terminals of multiple ones of the devices under test, wherein the additional testing circuit is configured to supply testing signals to the additional terminals, to subject signals received from the additional terminals to testing, and to provide output signals indicative of whether the signals from the additional terminals are satisfactory; andan arithmetic circuit configured to receive the output signals from each of the plurality of testing circuits and the additional testing circuit, and to provide a respective signal for each device under test indicative of whether that device under test is unsatisfactory based on the received output signals.