Patent ID: 6763471
Filing Date: 2004-07-13
Classification: G06F,Y02D

Abstract:
A single chip microcomputer comprising:a central processing unit; a read only memory which stores a program executed by said central processing unit; a random access memory which holds data processed by said central processing unit; an oscillator which supplies a low-speed clock signal to said central processing unit; a peripheral circuit which transfers a signal to said central processing unit and receives a signal from said central processing unit; and a control circuit, said control circuit supplying: a first voltage to said central processing unit, said read only memory, said random access memory and said peripheral circuit in synchronization with rising and falling of said low-speed clock signal, said first voltage enabling said central processing unit, said read only memory, said random access memory and said peripheral circuit to change their operations when operating with said low-speed clock signal; and a second voltage to said central processing unit with passage of predetermined time after said rising and falling of said low-speed clock signal, said second voltage being lower than said first voltage and enabling said central processing unit, said read only memory, said random access memory and said peripheral circuit to maintain their operations when operating with said low-speed clock signal.