Patent ID: 6383878
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method of integrating salicide process and self-aligned contact process comprising steps of:providing a semiconductor substrate defined as a memory device area and a periphery area wherein a plurality of doped gate electrodes and source/drain regions are formed in both the memory device area and the periphery area; forming an oxide layer on the exposed surface of the semiconductor substrate to cover the gate electrodes and then forming a plurality of spacers on the sidewalls of the gate electrodes respectively; forming a barrier layer and a buffering layer sequentially on the exposed surface of the semiconductor substrate to fill the gap between adjacent gate electrodes in the memory device area; removing the buffering layer and the barrier layer from the top of the gate electrodes to expose the oxide layer positioned on the top of the gate electrodes in the memory device area and the periphery area and expose the oxide layer overlying the semiconductor substrate in the periphery area; removing the exposed oxide layer and the underlying gate electrodes until the gate electrode reaches a predetermined height; performing the salicide process to form a silicide on the exposed surface of the gate electrodes in the memory device area and the periphery area and on the source/drain regions in the periphery area; forming a gate cap layer on the silicide which is covered on the gate electrodes; forming an inter-layer dielectric on the exposed surface of the semiconductor substrate; and performing the self-aligned contact process to form a contact hole which exposes the source/drain region positioned between adjacent gate electrodes in the memory device area.