Patent ID: 6552935
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A nonvolatile memory device, comprising:more than two core banks of nonvolatile memory cells, memory cells in each core bank being arranged in addressable rows and columns of nonvolatile memory cells; a plurality of address decode circuits, each core bank of nonvolatile memory cells being associated with a distinct address decode circuit so as to connect addressed memory cells to a plurality of column lines in the core bank of nonvolatile memory cells; a plurality of sense amplifiers coupled to the column lines; data output circuitry connected to sense output signals generated by at least some of the sense amplifiers; nonvolatile storage elements capable of maintaining memory bank configuration information; control circuitry for grouping the core banks of nonvolatile memory cells into at least two groups of one or more core banks based upon the memory bank configuration information, and controlling the address decode circuits, sense amplifiers and the data output circuitry so that memory access operations are capable of being substantially simultaneously performed on the groups of core banks.