Patent ID: 8984316
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. An apparatus comprising: a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state in response to a request, the transition to the first reduced power state including the processor to store context data for the apparatus into a volatile system memory; and power management logic to transition the apparatus to a second reduced power state, the power management logic to write the context data from the volatile system memory to a first nonvolatile memory for the transition to the second reduced power state, wherein the power management logic is to implement one or more security measures for the write of the context data into the first nonvolatile memory and for the recovery of the context data from the first nonvolatile memory, the one or more security measures including the power management logic to store a security element for the context data, the security element being an encryption key or password required to access the context data stored in the first nonvolatile memory, the power management logic to store the encryption key or password in a second nonvolatile memory; wherein the second nonvolatile memory is inaccessible to any entities other than the power management logic.