Patent ID: 7863713
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A semiconductor device comprising a circuit having at least a pair of transistors of different conductivity types, wherein a transistor of one conductivity type is formed using a first semiconductor layer provided on an SOI substrate and a first gate insulating layer covering at least part of a surface of said first semiconductor layer, a transistor of another conductivity type is formed using a second semiconductor layer provided on said SOI substrate and a second gate insulating layer covering at least part of a surface of said second semiconductor layer, a surface of a first region for forming a channel of said first semiconductor layer has a first crystal plane, a surface of a second region provided on a plane crossing the surface of said first region for forming a channel on a side of said first semiconductor layer has a second crystal plane different from said first crystal plane and adapted to provide a different mobility of carriers than said first crystal plane, a surface of a first region for forming a channel of said second semiconductor layer has a first crystal plane, a surface of a second region provided on a plane crossing the surface of said first region for forming a channel on a side of said first semiconductor layer has a second crystal plane different from said first crystal plane and adapted to provide a different mobility of carriers than said first crystal plane, and, given that an effective mass of electrons at the surface of said first region for forming the channel of said first semiconductor layer is me an effective mass of holes at the surface of said first region for forming the channel of said second semiconductor layer is mh a width of the surface of said first region for forming the channel of said first semiconductor layer is We, a width of the surface of said second region for forming the channel of said first semiconductor layer is He, a width of the surface of said second region for forming the channel of said second semiconductor layer is Wh, a width of the surface of said second region for forming the channel of said second semiconductor layer is Hh, a length of the surface of said first region for forming the channel of said first semiconductor layer is L an actual effective electron mass mee of said first semiconductor layer and an actual effective hole mass mhe of said first semiconductor layer when L wherein He and Hh are determined so as to establish mee=mhe and to satisfy We=Wh and He=Hh, thereby configuring said transistor of one conductivity type and said transistor of another conductivity type so that areas of channel regions thereof are substantially equal or equivalent to each other and operating speeds thereof are substantially equal or equivalent to each other.