Patent ID: 7969808
Filing Date: 2011-06-28
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a memory array including a plurality of memory cells, each memory cell including a floating body transistor having a first node, a second node, and a gate node, connected to at least one bit line, at least one source line and at least one word line, respectively; and a control unit for performing a refresh operation in response to a refresh command by selecting one of the at least one source line and the at least one bit line, wherein if first data is stored at a memory cell connected to the selected line, a first current caused by bipolar junction operation flows; wherein the control unit further performs a write operation by applying a bit line write voltage to the at least one bit line according to data information, then applying a source line write voltage to the at least one source line, and then applying a word line write voltage to the at least one word line, wherein the source line write voltage is greater than the bit line write voltage and the word line write voltage, and wherein a difference between the source line write voltage and the bit line write voltage for the word line write voltage induces the bipolar junction operation according to the data information.