Patent ID: 7023085
Filing Date: 2006-04-04
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a semiconductor package with reduced parasite capacitance, comprising: preparing a substrate, which is predefined with at least a pair of passive-component pads and a plurality of signal pads; preparing a passive component having a first connecting end and a second connecting end; preparing a semiconductor chip, which has an active surface and an inactive surface, and whose active surface is formed with at least a pair of ground/power pads and a plurality of signal pads, wherein a plurality of first-type bumps and second-type bumps are formed through a bumping process respectively over the ground/power pads and the signal pads, where the first-type bumps are smaller in height than the second-type bumps; bonding the first connecting end and the second connecting end of the passive component to the passive-component pads on the substrate; mounting the semiconductor chip onto the substrate, wherein the first-type bumps are bonded to the first connecting end and the second connecting end of the passive component while the second-type bumps are bonded to the signal pads on the substrate; and performing a flip-chip underfill process to form a flip-chip underfill layer in the gap between the chip and the substrate for serving as an encapsulation body.