Patent ID: 9113136
Filing Date: 2015-08-18
Classification: H04N

Abstract:
1. A video processing apparatus, comprising: a decoding circuit, for decoding a plurality of video signals to generate a plurality of decoded video signals; a setting circuit, coupled to the decoding circuit, for selecting a main decoded video signal from the plurality of decoded video signals, and selecting at least one sub-decoded video signal from the other decoded video signals, wherein each of the main decoded video signal and the sub-decoded video signal includes a plurality of frames; a processing circuit, for performing an image processing operation upon the main decoded video signal and the at least one sub-decoded video signal to generate a processed video signal; a first buffer, coupled to the processing circuit, the first buffer serving as an on-screen buffer for storing the processed video signal being displayed or to be displayed and serving as an on-process buffer for storing the processed video signal being mixed or to be mixed, cyclically; a second buffer, coupled to the processing circuit, the second buffer serving as the on-process buffer for storing the processed video signal being mixed or to be mixed and serving as the on-screen buffer for storing the processed video signal being displayed or to be displayed, cyclically, wherein the first buffer and the second buffer do not serve as the on-screen buffer simultaneously, and the first buffer and the second buffer do not serve as the on-process buffer simultaneously; and a display unit, coupled to the first buffer and the second buffer, for cyclically displaying the processed video signal read from the first buffer and the second buffer on a display device.