Patent ID: 6411485
Filing Date: 2002-06-25
Classification: H01L

Abstract:
An ESD protection circuit for use with a multi-voltage power supply circuit having a first internal circuit using a first system voltage and a second internal circuit using a second system voltage, with the first internal circuit having a first set of bonding pads and the second internal circuit having a second set of bonding pads;the ESD protection circuit comprising: a first ESD bus; a first set of ESD protection units each being coupled between the first ESD bus and one of the first set of bonding pads of the multi-voltage power supply circuit, and each of which is capable of being switched on in the event of an ESD stress to the associated one of the first set of bonding pads, wherein the first set of ESD protection units each comprise: a first resistor having a first end and a second end, with the first end being connected to a corresponding pad of the first set of bonding pads; a second resistor having a first end and a second end, with the first end being connected to the first ESD bus; a PNP transistor having a base connected to the second end of the first resistor, an emitter connected to a corresponding pad of the first set of bonding pads, and a collector connected to the second end of the second resistor; an NPN transistor having a base connected to the second end of the second resistor, a collector connected to the second end of the first resistor, and an emitter connected to the first ESD bus; a first PMOS transistor having a source connected to the second end of the first resistor, a substrate connected to a corresponding pad of the first set of bonding pads, a drain connected to the source of a subsequent PMOS transistor whereby a string of serially connected plurality of PMOS transistors are configured, and a gate connected to the drain; a last PMOS transistor having a drain connected to the first ESD bus, a gate connected to the drain, a source connected to the drain of the second PMOS transistor, and a substrate connected to the source; and a predetermined number of transistors connected between the first and third PMOS transistors having a source connected to the drain of the preceding PMOS transistor, a drain connected to the source of the subsequent PMOS transistor, a gate connected to the drain, and a substrate connected to the source; a second ESD bus; a second set of ESD protection units each being coupled between the second ESD bus and one of the second set of bonding pads of the multi-voltage power supply circuit, and each of which is capable of being switched on in the event of an ESD stress to the associated one of the second set of bonding pads; and a routing circuit coupled between the first ESD bus and the second ESD bus, which allows an ESD-induced transient current in the first ESD bus to flow to the second ESD bus and an ESD-induced transient current in the second ESD bus to flow to the first ESD bus.