Patent ID: 7038270
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A non-volatile memory device comprising: a semiconductor substrate of a first conductivity type; a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked on the semiconductor substrate; a lower insulating pattern and a tunnel insulating pattern, wherein the lower insulating pattern and the tunnel insulating pattern are interposed between the charge storage layer and the semiconductor substrate; a heavily doped region of the first conductivity type which is formed in the semiconductor substrate under the tunnel insulating pattern and spaced apart from an upper surface of the semiconductor substrate at a predetermined distance below the upper surface, wherein the tunnel insulating pattern is thinner than the lower insulating pattern in thickness and disposed at the side of the lower insulating pattern, and wherein the charge storage layer is a silicon nitride layer; and a lightly doped region formed in the surface of the semiconductor substrate, wherein the lightly doped region has the first conductivity type and is formed under the tunnel insulating pattern.