Patent ID: 6780691
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising:providing a gate electrode overlying a substrate and isolated from said substrate by a gate dielectric layer; forming isolation regions in and on said substrate wherein said isolation regions have a stepped profile wherein an upper portion of said isolation regions partly overlaps and is offset from a lower portion of said isolation regions in the direction away from said gate electrode wherein said step of forming said isolation regions comprises: forming first dielectric spacers on sidewalls of said gate electrode; performing local oxidation of silicon to form said lower portion of said isolation regions in and on said substrate adjacent to said first spacers; forming second dielectric spacers overlying said lower portion of said isolation regions and adjacent to said first spacers; forming an oxide layer overlying said lower portion of said isolation regions wherein said oxide layer forms said offset upper portion of said isolation regions; and thereafter removing said first and second spacers; implanting ions into said substrate between said gate electrode and said isolation regions to form source/drain extensions; forming dielectric spacers on sidewalls of said gate electrode and said isolation regions; and depositing a conductive layer overlying said substrate, said gate electrode, and said isolation regions and planarizing said conductive layer to leave said conductive layer adjacent to said gate electrode and separated from said gate electrode by said dielectric spacers wherein said conductive layer forms elevated source/drain junctions and wherein said elevated source/drain junctions completely overlie said source/drain extensions and wherein an upper portion of said elevated source/drain junctions extends into said stepped portion of said isolation regions thereby completing formation of said MOSFET having an elevated source/drain structure in the fabrication of said integrated circuit device.