Patent ID: 6714455
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a plurality of non-volatile memory cells each of which has a storage structure and an electrically alterable parameter representing data of at least two bits, wherein the eleotrically alterable parameters of the plurality of non-volatile memory cells are shiftable to at least three mutually different first, second and third program states from an erase state; reference, value generating circuitry generating programming reference values for programming the first, second and third program states, and generating read reference values, which are different from the programming reference values, for reading the first, second and third program states; and sensing/program-verifying circuitry receiving the parameter of one non-volatile memory cell, the read reference values and the programing reference values; wherein the sensing/program-verifying circuitry generates data of at least two bits represented by the electrically alterable parameter, verifies whether the electrically alterable parameter is shifted to the parameter indicating a selected one state of the, first, second and third program states, and programs the electrically alterable parameter until it has been verified that the eleetrically alterable parameter has been shifted to the selected one state, wherein the programing reference values are used for verifying whether the electrically alterable parameter is shifted to the first, second or third program state, and the read reference values are used for detecting whether the electrically alterable parameter is near to the first. second or third program state, and wherein the reference value generating circuitry generates the program reference values, and the read reference values such that one of a programming reference value and a read reference value is shifted from and dependent upon the other.