Patent ID: 8289058
Filing Date: 2012-10-16
Classification: H03L

Abstract:
1. A phase locked loop (PLL) having two or more outputs, the PLL comprising: a voltage controller oscillator (VCO) that outputs an output signal having a first frequency at an output terminal; a first frequency divider electrically coupled to the output terminal creating a first divided output signal having a first divided output frequency; a shifter circuit having a shifter circuit input electrically coupled to the output terminal and a shifter circuit output, the shifter circuit also including an activation input that receives an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal; and a second frequency divider electrically coupled to the shifter circuit output creating a second divided output signal based on the shifter circuit output and having a second divided output frequency; wherein the shifter circuit further includes: a first D flip-flop having an input coupled to the activation signal and a first D flip-flop output, the first D flip-flop having a clock input coupled to the output signal; a first inverter having an input coupled to the first D flip-flop output and an output; a logic gate having inputs coupled to the output of the inverter and the activation signal and an output; a second D flip-flop having an input electrically coupled to the output of the logic gate and a second D flip-flop output, the first D flip-flop having a clock input coupled to the output signal; and one or more signal conditioning elements coupled between the activation input and the first D flip-flop.