Patent ID: 8787092
Filing Date: 2014-07-22
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus, comprising: a plurality of memory cells, the plurality of memory cells are arranged in an array, each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal, wherein each of the memory cells is configured as a structure of three transistors and one capacitor (3T1C), and the floating gate is a single-poly gate; and a signal generator, coupled to the memory cells, when the nonvolatile memory apparatus executing a programming operating, the signal generator providing a programming signal to the control gate terminals of the memory cells, wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage, when the nonvolatile memory apparatus executing the programming process, the signal generator further providing a first and a second bit-line signals to the bit-line terminals of the inhibited and non-inhibited memory cells respectively, wherein, the voltage level of the first bit-line signal is larger than the second bit-line signal.