Patent ID: 7075137
Filing Date: 2006-07-11
Classification: H01L

Abstract:
1. A semiconductor memory having charge trapping memory cells, the memory comprising: a semiconductor body; memory transistors formed the semiconductor body, each memory transistor having a channel region between source and drain regions, a gate electrode and a dielectric storage layer sequence between the gate electrode and the channel region; isolations regions disposed in the semiconductor body, the isolation regions arranged at a distance from one another in a longitudinal direction of the channel regions, the isolation regions located between the memory transistors; bit lines arranged along the isolation regions; word lines arranged in rows running transverse with respect to the bit lines and in a manner electrically insulated from the bit lines at a distance from one another, the gate electrode each memory transistor being electrically coupled to a relevant word line, wherein the longitudinal direction of a channel region runs transversely with respect to the relevant word line associated with that channel region; electrically conductive interconnects coupling ones of the bitlines to ones of the source and drain regions of the memory transistors; and an electrical insulation disposed between two successive isolation regions between relevant bit lines in order to divide the semiconductor memory into slices at predetermined distances between two successive relevant bit lines.