Patent ID: 6263452
Filing Date: 2001-07-17
Classification: G06F

Abstract:
A method of operating a fault tolerant computer system having a plurality of input/output (I/O) processors and a plurality of I/O controllers coupled to said plurality of input/output processors, each of said I/O controllers being assigned to one of said I/O processors and each of said I/O controllers having associated controller data structures, the method comprising the steps of:a) detecting an error in one of the input/output processors;b) reassigning all I/O controllers assigned to said input/output processor in which an error is detected to the other input/output processor which is coupled to the said I/O controllers;c) isolating the faulty input/output processor from the system without system shutdown and continuing normal system operation using said other input/output processor;d) replacing said faulty input/output processor with another input/output processor and rendering said replacement input/output processor operative by coupling and reassigning said I/O controllers to said replacement input/output processor; ande) reinitiating controller data structures so the replacement input/output processor can be controlled by said reassigned I/O controllers.