Patent ID: 6534852
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A semiconductor package, comprising:a substrate having: a dielectric layer having an upper surface and a lower surface; a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer; a plurality of solder ball pads disposed on the lower surface of the dielectric layer; a plurality of vias each electrically connecting one of the solder ball pads to one of the bonding pads through one of the traces; at least a first metal reinforcing layer disposed on the lower surface of the substrate in regions where the solder ball pads are not formed to reinforce the strength of the substrate and to serve as a ground plane for the semiconductor package; and a protective layer coated on the upper surface and the lower surface of the substrate without covering the bonding pads on the upper surface and the solder ball pads on the lower surface; a plurality of solder balls each attached to one of the solder ball pads for connecting to external circuits; a chip attached to the substrate, and having a plurality of chip pads each electrically connected to one of the bonding pads; a package body encapsulating the chip and at least the upper surface of the substrate; wherein the first metal reinforcing layer is divided into a number of separate units according to the distance from neutral point (DNP) of the substrate.