Patent ID: 8069318
Filing Date: 2011-11-29
Classification: G11C

Abstract:
1. A method for communicating between an IO bus and eight flash memory banks, wherein the IO bus comprises a bus write enable signal and a bus data signal, wherein the bus write enable signal and the bus data signal each comprise bit streams having a period p1/8, and wherein the method comprises: for each of the eight flash memory banks: generating a memory write enable signal having a period p1; writing a memory data signal into a register when the memory write enable signal is in an on state, wherein said writing a memory data signal into a register is triggered by a next change of state of the bus write enable signal and continues for a period p1/8; and writing the memory data signal, having a period of p1, into the flash memory bank from the register, wherein said writing the memory data signal into the flash memory bank continues for a period p1; wherein data bits of the bus data signal are successively written into the eight flash memory banks, and wherein transfer of each memory data signal into a respective register is done in one-eighth of a time needed to transfer each memory data signal from the respective register into the respective flash memory device.