Patent ID: 7394156
Filing Date: 2008-07-01
Classification: G06F,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device comprising: a plurality of logic cells composed of CMOS-type base cells arranged on a semiconductor substrate; m wiring layers, m being a natural number; and at least one functional block, wherein: at least one of a horizontal wiring connection within the logic cells and a horizontal wiring connection between the logic cells is present in the device, and any horizontal wiring connection within the logic cells and any horizontal wiring connection between the logic cells that are present are constituted only in n upper wiring layers among the m wiring layers, n being a natural number with n<m; lower (m−n) wiring layers comprise first contact vias and first wiring patterns connected to respective first contact vias; connection between the logic cells and the functional block, or between the functional blocks is conducted by using only the upper n wiring layers among m wiring layers; the semiconductor integrated circuit device further comprises at least one power supply cell comprising the CMOS-type base cell arranged on the semiconductor substrate and the m, n and (m−n) wiring layers, the lower (m−n) wiring layers of the at least one power supply cell comprise second contact vias disposed at positions corresponding to at least one grid of a power supply in the base cells and second wiring patterns connected to the second contact vias; second wiring patterns of neighboring power supply cells are connected to each other; and the at least one power supply cell is positioned adjacent to at least one of the logic cells.