Patent ID: 8836631
Filing Date: 2014-09-16
Classification: G09G

Abstract:
1. A scan driving circuit having a shift register unit with a plurality of stages, each stage comprising: an input terminal configured to provide an input signal; an output terminal; first, second, and third clock terminals configured to transmit respective first, second, and third clock signals; a first transistor configured to transfer the input signal from the input terminal according to the second clock signal from the second clock terminal, the second clock terminal being directly connected to a gate of the first transistor; a switch section configured to transfer a first supply voltage signal from a first voltage source to the output terminal according to the first clock signal from the first clock terminal when the input signal is transmitted through the first transistor, wherein the switch section includes a third transistor, a fourth transistor, and a fifth transistor, the fifth transistor being configured to transfer the first supply voltage signal from the first voltage source to the output terminal according to signals transferred through the third and fourth transistors, the third transistor is directly connected between a second voltage source and having a gate directly connected to the first clock terminal, and the fifth transistor is connected between the first voltage source and the output terminal; and a storage section including a second transistor and a capacitor, the capacitor maintaining a predetermined voltage configured to receive and store the input signal from the first transistor and to activate the second transistor by controlling on/off the third clock signal from the third clock terminal to the output terminal according to the input signal.