Patent ID: 7208818
Filing Date: 2007-04-24
Classification: H01L

Abstract:
1. A flat-lead power semiconductor package comprising: a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a source lead, a gate lead, a drain lead, and a first lead frame pad, the first lead frame pad including a FET die coupled thereto; source and gate lead bonding areas disposed in a same plane of a top surface of the FET die; a plurality of large diameter aluminum bonding wires having a thickness of 20 mils connecting the source of the FET die to the source lead bonding area and a single bonding wire connecting the gate of the FET die to the gate bonding area; and a resin body encapsulating the FET die, bonding wires and at least a portion of the lead frame.