Patent ID: 6768745
Filing Date: 2004-07-27
Classification: H04J,Y10S

Abstract:
A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:a common bus of predetermined bit width for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs: a first partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and a second partition bus of the predetermined bit width for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs; and an expansion shelf containing at least one expansion LSU and an expansion interface unit (ESI) connected to the at least one HSU of a shelf unit for exchange data between the shelf unit and the expansion shelf; wherein the first, second, third, and fourth buses of respective first and second partition buses have a bit width less than the predetermined bit width to enable increased flexibility of signal transmissions to and from a SONET network; wherein the at least one HSU, at least two LSUs, and common, first and second partition buses, are contained in the shelf unit; wherein the shelf unit further comprises a system control processor unit (SCU) for controlling the processes of the units contained in the shelf, at least one system timing and control synchronization unit (STU) for controlling the timing and synchronization between the units contained in the shelf unit, and at least one power supply unit for powering the units contained in the shelf unit; wherein the data transmitted from the expansion shelf has the same frame alignment as the data transmitted from the shelf unit relative to the at least one HSU for eliminating the need for frame alignment buffering on the at least one HSU.