Patent ID: 8064240
Filing Date: 2011-11-22
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of plate lines; first to eighth bit lines; a plurality of cell transistors comprising gate electrodes connected to the word lines; a plurality of ferroelectric capacitors, each of which is connected in parallel with one of the cell transistors between a source and a drain of the one of the cell transistors; and a sense amplifier configured to detect data in one of the ferroelectric capacitors, wherein one of the cell transistors and one of the ferroelectric capacitors configure a memory cell, a plurality of the memory cells are connected in series in order to configure first to eighth memory cell blocks, the first to the eighth memory cell blocks each include at least one memory cell connected to the same shared word line, first ends of the first to the eighth memory cell blocks are respectively connected to the first to the eighth bit lines via block selection transistors, second ends of the first to the eighth memory cell blocks are respectively connected to the different plate lines, one of the first to the fourth bit lines and one of the fifth to the eighth bit lines are configured to be selectively connected to the sense amplifier during an operation, and numbers of the memory cells connected in series between the block selection transistors and the plate lines are different in each of the first to the fourth memory cell blocks, and are different in each of the fifth to the eighth memory cell blocks.