Patent ID: 8484436
Filing Date: 2013-07-09
Classification: G06F

Abstract:
1. A system comprising a memory controller, wherein the memory controller is configured to receive read requests from a processor and return memory words from memory, and wherein the memory controller comprises: an address comparator configured to determine a difference between a previous read request address and a current read request address and to determine whether the difference is positive and less than a specified address difference and, if so, indicate a limited backwards jump; and a loop entry cache configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump wherein the memory controller is configured to receive a first read type indicator from the processor indicating whether the current read request corresponds to a data read or an instruction read and a second read type indicator from the processor indicating whether the previous read request corresponds to a data read or an instruction read and store the current memory word in the loop entry cache only when both the first and second read type indicators indicate an instruction read.