Patent ID: 6611153
Filing Date: 2003-08-26
Classification: G06F,H03K

Abstract:
A method of forming an interconnect structure in a field programmable gate array (FPGA) comprising:providing a FPGA having a plurality of logic components arranged in a plurality of rows and columns and having input ports and output ports; providing a plurality of sets of first row conductors coupled to a first row logic component and a set of second row conductors coupled to a second row logic component, each one in said sets of first row conductors and second row conductors having different designator, and said first row logic component adjacent to said second row logic component; providing a plurality of sets of first column conductors coupled to a first column logic component and a set of second column conductors coupled to a second column logic component, each one in said sets of first column conductor and second column conductors having a different designator, said first column logic component adjacent to said second column logic component; providing a plurality of vertical routing conductors, each one in said sets of vertical conductors having a different designator, said sets of vertical routing conductors forming a first plurality of intersections with said sets of output conductors; providing a plurality of sets of horizontal routing conductors, each one in said sets of horizontal routing conductors having a different designator, said sets of horizontal routing conductors forming a second plurality of intersections with said sets of input conductors and forming a third plurality of intersections between said sets of vertical routing conductors, said third intersection having four quadrants; and providing programmable interconnect elements at selected intersections in said first, second and third pluralities of intersections.