Patent ID: 7548108
Filing Date: 2009-06-16
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device, comprising: a power terminal receiving a high voltage higher than a power supply voltage of the device; a first MOS transistor coupled between the power terminal and a first internal node, the first internal node coupled to a row decoder and driver block of a memory device, and the row decoder and driver block selectively drives word lines of the memory device in response to a row address signal; a second MOS transistor coupled between the power terminal and a second internal node, a third MOS transistor, having a relatively thin gate insulation layer, coupled between the first internal node and a third internal node; a fourth MOS transistor, having a relatively thin gate insulation layer, coupled between the second internal node and a fourth internal node; a fifth MOS transistor coupled between the third internal node and a ground voltage, the fifth MOS transistor controlled by a first input signal, and the first input signal includes the row address signal and a block selecting signal from the memory device; and a sixth MOS transistor coupled between the fourth internal node and the ground voltage, the sixth MOS transistor controlled by an inverted version of the first input signal.