Patent ID: 7353310
Filing Date: 2008-04-01
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a multi-stage pipelined network defining a read pipeline and a write pipeline between a plurality of initiators and a memory, the multi-stage pipelined network including first and second stages, wherein the first stage is disposed intermediate the second stage and the memory; a first access controller coupled to the first stage of the multi-stage pipelined network, the first access controller including a first arbitration circuit, a first read control circuit disposed in the read pipeline and a first write control circuit disposed in the write pipeline; a second access controller coupled to the second stage of the multi-stage pipelined network, the second access controller including a second arbitration circuit, a second read control circuit disposed in the read pipeline and a second write control circuit disposed in the write pipeline; wherein the second arbitration circuit is configured to receive a first request for access to the memory from a first initiator coupled thereto and forward the first request to the first arbitration circuit, wherein the first arbitration circuit is configured to generate an identification signal that identifies the first initiator, a push signal that initiates processing of the first request, and a read/write selection signal that selectively activates one of the read and write pipelines, the first arbitration circuit further configured to output the identification, push and read/write selection signals to the second arbitration circuit, the first and second read control circuits and the first and second write control circuits to initiate processing of the first request to communicate data between the first initiator and the memory over one of the read and write pipelines.