Patent ID: 6762637
Filing Date: 2004-07-13
Classification: H03K

Abstract:
An edge-triggered D-Flip-Flop circuit, comprising:a master circuit having a data input terminal, a master switch controlled by a clock signal and connected with one end of said data input terminal, and a first inverter having an input terminal connected to said master switch and an output terminal, said master circuit having no feedback structure; a slave circuit having a slave switch controlled by said clock signal and connected to said output terminal of said first inverter, a second inverter having an input terminal connected to said slave switch and an output terminal, and a feedback-loop including a feedback-switch and a third inverter connected between said input terminal and said output terminal of said second inverter; set and reset inputs for respectively setting and resetting information stored in said slave circuit; a set switch connected between said input terminal of said second inverter and a ground potential; a reset switch connected between said output terminal of said second inverter and the ground potential; each of said master switch and said slave switch being a single n-channel metal oxide semiconductor field-effect transistor (MOSFET), said master switch n-channel MOSFET having a first source/drain-terminal connected to said data input and a second source/drain-terminal connected to said input terminal of said first inverter; and said set switch and said reset switch being n-channel MOSFETs.