Patent ID: 6489826
Filing Date: 2002-12-03
Classification: H03K

Abstract:
A clock generation system comprising:a waveform stabilizer that receives and stabilizes an input clock signal; an inverter that receives said input clock signal from said waveform stabilizer and outputs an inverted input clock signal; a programmable clock generator coupled to said waveform stabilizer and said inverter for modifying a non-overlap period between two non-overlapping clock signals, comprising: a first logic gate having first and second inputs and a first output, wherein said first input receives said input clock signal and said first output outputs a first non-overlapping clock signal; a second logic gate having third and fourth inputs and a second output, wherein said third input receives said inverted input clock signal and said second output outputs a second non-overlapping clock signal; a first programmable delay module having a fifth input coupled to said first output of said first logic gate and having a third output coupled to said fourth input of said second logic gate, wherein said first programmable delay module receives said first non-overlapping clock signal and selectively delays said first non-overlapping clock signal to output a first delayed clock signal; and a second programmable delay module having a sixth input coupled to said second output of said second logic gate and having a fourth output coupled to said second input of said first logic gate, wherein said second programmable delay module receives said second non-overlapping clock signal and selectively delays said second non-overlapping clock signal to output a second delayed clock signal; and a clock driver circuit coupled to said first output of said first logic gate and to said second output of said second logic gate for driving said first and second non-overlapping clock signals; wherein said first programmable delay module comprises: a first delay path that receives said first non-overlapping clock signal, wherein said first delay path comprises a first plurality of serially-connected delay elements; a first plurality of connection points, wherein each of said first plurality of connection points is located after a different one of said first plurality of serially-connected delay elements; and a first multiplexer coupled to said first plurality of connection points, wherein said first multiplexer selects one of said first plurality of connection points and receives said first delayed clock signal from said selected connection point, and wherein the amount of delay introduced by said first delay module is modified by changing which one of said first plurality of connection points is selected by said first multiplexer.