Patent ID: 6777994
Filing Date: 2004-08-17
Classification: G06F,H03K

Abstract:
A clock generator, which comprises:M delay units (DC) in order of 1 to M, each one of which has invert (âˆ’) and non-invert (+) inputs, and further has invert (âˆ’) and non-invert (+) outputs, wherein a phase difference between two clock signals from the invert (âˆ’) and non-invert (+) outputs in each delay unit (DU) is substantially 180 degrees, and a phase interval between the invert outputs of each two adjacent delay units is substantially equivalent to &thgr;, wherein M is an integer greater than 2; a first set of impedances (Ra), wherein the n-th impedance (Ran) is connected to the invert (âˆ’) outputs of the (nâˆ’1)-th DU and n-th DU, wherein n is an integer greater than 1 and up to M, and M is defined as above; and a second set of impedances (Rb), wherein the n-th impedance (Rbn) is connected to the non-invert (+) outputs of the (nâˆ’1)-th DU and n-th DU, wherein both n and M are defined as above, wherein the first and second sets of the impedances have substantially identical impedance, so that a phase shift error originating from a mismatch effect among the M DUs will generate an averaging current flowing through the first and second sets of impedances, and thus phase shift error will be reduced compensatively, and further comprising M amplifiers (AP), each one of which has two inputs and two outputs, wherein two inputs of the (nâˆ’1)-th AP are connected to the two outputs of the (nâˆ’1)-th DU, wherein Ran connects the first output of the (nâˆ’1)-th AP to the first output of the n-th AP, and Rbn connects the second output of the (nâˆ’1)-th AP to the second output of the n-th AP, wherein n, M, Ran, and Rbn are defined as above, wherein the M APs act as buffers among the M DUs, the first set of impedances, and the second set of impedances, in order to make the M DUs independent from a variation effect of the first set and second set of impedances.