Patent ID: 8130557
Filing Date: 2012-03-06
Classification: G06F

Abstract:
1. A memory system comprising: a nonvolatile semiconductor memory comprising a first block and a second block, each of the first and second blocks comprising write unit areas, each of the write unit areas comprising memory cells, each of the memory cells configured to store more-than-one bits data; and a controller configured to receive write-data from outside of the memory system, the controller configured to write the write-data in the first block such that each of the memory cells in the first block stores only one-bit data, the controller configured to read the write-data stored in the first block and write the write-data read from the first block in the second block such that each of the memory cells in the second block stores more-than-one bits data, the controller further configured to write write-data in the first block when data having a logical address identical to a logical address of the write-data exists in the first block.