Patent ID: 7064026
Filing Date: 2006-06-20
Classification: H01L,Y10S

Abstract:
1. A method of forming a semiconductor device, comprising: forming at least one gate pattern on a substrate; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed; and forming a shared contact hole exposing parts of the top surface of the gate pattern and LDD-type source/drain regions of the substrate adjacent to the gate pattern, and simultaneously etching and removing at least a portion of the spacer together with the interlayer insulation layer at the shared contact hole.