Patent ID: 6143591
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A semiconductor processing method of forming a thin film transistor comprising:providing a substrate;defining a source template portion, a channel template portion and a drain template portion of the substrate;forming an insulator layer over the substrate;forming a semiconductive layer over the insulator layer;forming a depletion region within the semiconductive layer, the depletion region being over the source template portion, the channel template portion and the drain template portion, the depletion region being proximate the insulator layer and having a different thickness over the channel template portion than over the source and drain template portions;while the depletion region is formed, exposing the semiconductive layer to an electrolytic etching composition to etch the semiconductive layer to about the depletion region, the etched semiconductive layer comprising a different thickness over the channel template portion than over the source and drain template portions, the etched semiconductive layer over the channel template portion comprising a transistor channel, the etched semiconductive layer over the source template portion comprising a transistor source, and the etched semiconductive layer over the drain template portion comprising a transistor drain, the transistor channel comprising a thickness configured to create a desired threshold voltage;forming a transistor gate proximate the channel; andincorporating the transistor source, transistor drain, transistor channel and transistor gate into a thin film transistor.