Patent ID: 6667233
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A method for forming a silicide layer of a semiconductor device, the method comprising:(a) forming a lower insulating layer having a contact hole partially exposing an impurity junction region of a transistor on a semiconductor substrate; (b) forming a metal layer on the semiconductor substrate including the exposed portion of the impurity junction region and the sidewall of the contact hole; (c) performing a thermal annealing process by raising the temperature of the semiconductor substrate up to 600Â° C. at a speed ranging from 20 to 50Â° C. second; (d) performing a thermal annealing process by raising the temperature of the semiconductor substrate up to a range from 800 to 900Â° C. at a speed ranging from 200 to 300Â° C. second, wherein the semiconductor substrate is maintained at the highest temperature for less than one second; (e) forming a silicide layer on the impurity junction dropping temperature of the semiconductor substrate to below 700Â° C. at a speed ranging from 70 to 90Â° C. second; and (f) removing the non-reacted metal layer from the semiconductor substrate.