Patent ID: 6411267
Filing Date: 2002-06-25
Classification: G09G

Abstract:
A monitor comprising:a display screen for displaying an image; a frame memory for storing one or more frames of video display data for display by the display screen; clock control means for varying the timing at which the display data are read out from the frame memory to the display screen to manipulate the image displayed on the display screen, wherein the clock control means comprises: (a) a voltage controlled oscillator (VCO) that outputs clock pulses for reading display data out of the frame memory; (b) a frequency divider supplied with the clock pulses and producing an output horizontal sync pulse every predetermined number of clock pulses; (c) a phase comparator supplied with both a horizontal clock signal from an external source that also supplies the display data to the frame memory and the horizontal sync pulse from the frequency divider, the phase comparator producing a phase error signal representing the difference in phase between the horizontal sync pulse and the horizontal clock signal and supplying the phase error signal as one input to the VCO and to the frequency divider; and (d) a second input of the VCO for receiving a reference signal input for varying the period and timing of the clock pulses as a function of the waveform of the reference signal input.