Patent ID: 6219811
Filing Date: 2001-04-17
Classification: G01R

Abstract:
A multi-chip semiconductor structure capable of providing interconnect testing capability, comprising:a plurality of integrated circuit chips including a first chip and a second chip;said first chip having a first transceiver and a first storage coupled to said first transceiver;said second chip having a second transceiver and a second storage coupled to said second transceiver wherein said second chip further comprises a sensing circuit coupled to said second storage and said second transceiver, said sensing circuit for sensing when data is transferred between said first and said second chip;a selector circuit on one of said plurality of chips and coupled to all of said plurality of chips, said selector circuit having a circuit portion capable of controlling selection of said first and said second chip for the interconnect testing, said selector circuit further capable of selectively enabling said first and said second transceiver to enable transfer of test data from said first storage to said second storage.