Patent ID: 6274394
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method for determining the fail patterns of fabricated wafers in an automated WAT procedure, comprising the steps of:(1) performing N test items on selected samples from the fabricated wafers, from which a total of N fail percentages are obtained respectively from the N test items;(2) formulating the N fail percentages as an N-dimensional test-result vector, in which the (i)th element represents the fail percentage of the (i)th test item, for i=1 to N;(3) providing an N.times.N conversion matrix based on empirical data from the relationships between test items and known process problems; and(4) obtaining an N-dimensional fail-pattern vector with fail patterns as a basis by multiplying the N-dimensional test-result vector with the N.times.N conversion matrix, wherein a resulting fail-pattern vector has N elements, with the (j)th element representing the percentage of the (j)th fail pattern, for j=1 to N.