Patent ID: 6043114
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:preparing a semiconductor body having a first conductivity type and having a predetermined impurity concentration at a whole of a principal surface of said semiconductor body;forming an epitaxial layer of said first conductivity type on said principal surface of said predetermined impurity concentration such that said epitaxial layer contacts said principal surface of said predetermined impurity concentration and has the same impurity concentration as a designed impurity concentration of said predetermined impurity concentration;forming a well region in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer;forming an oxide film, serving as a gate insulating film of a MISFET, on a surface of said epitaxial layer by oxidation of said surface of said epitaxial layer; andforming a gate electrode of said MISFET on said oxide film,wherein said predetermined impurity concentration at the whole of said principal surface of said semiconductor body is lower than an impurity concentration of a portion of said well region where a channel region of said MISFET is formed.