Patent ID: 6018797
Filing Date: 2000-01-25
Classification: G05B,G06F

Abstract:
An integrated circuit electronic computer comprising:address and data lines connectable to memory for exchanging data on the data lines at a memory address corresponding to an address on the address lines;instruction decoding circuit attached to the data lines for receiving an instruction therefrom and providing decoded instruction signals;a plurality of storage registers communicating with the address and data lines and the instruction decoding circuit to receive and transmit data from and to the data lines;an arithmetic/logic/relay ladder unit connected to the storage registers, the data lines, and the instruction decoding circuit for receiving data from at least one register to operate on that data, according to an instruction signal, to produce an output;wherein the arithmetic/logic/relay ladder unit operates on the data according to different instruction signals to execute arithmetic instructions, logic instructions and relay ladder instructions;wherein the integrated circuit electronic computer further includes a program counter communicating with the address lines to provide a fetch address from external memory where a next instruction will be found, and wherein the program counter is conditionally altered in response to an instruction signal to produce a branch in execution of instructions upon a condition based on the output of the arithmetic/logic/relay ladder unit's execution of an earlier relay ladder instruction.