Patent ID: 8050379
Filing Date: 2011-11-01
Classification: G09G,G11C

Abstract:
1. A shift register, comprising a plurality of shift register units, each shift register unit comprising: a nor gate comprising a first input terminal connected to an input terminal of the shift register unit, a second input terminal connected to a first output terminal of the shift register unit, and an output terminal; an and gate comprising a first input terminal connected to the input terminal, a second input terminal connected to the first output terminal, and an output terminal connected to a second output terminal of the shift register unit; a first switch circuit controlled by the output terminal of the nor gate and configured for providing a clock signal to a first common node of the shift register unit; a second switch circuit controlled by the output terminal of the nor gate and configured for providing a low level signal to the first common node; a third switch circuit controlled by the input terminal and the first common node and configured for providing a high level signal to a second common node of the shift register unit; a fourth switch circuit controlled by the first output terminal and the first common node and configured for providing a high level signal to the second common node; a fifth switch circuit controlled by the first common node and the first output terminal and configured for providing a low level signal to the second common node; a sixth switch circuit controlled by the first common node and the input terminal and configured for providing a low level signal to the second common node; and an inverter connected between the second common node and the first output terminal.