Patent ID: 6754801
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A processing element for use in a massively parallel processor, said processing element comprising:a first data bus for receiving data from a portion of a main memory associated with said processing element; a second data bus for sending data to said portion of said main memory associated with said processing element; a plurality of internal data buses, each of said plurality of internal data buses having a width of a plurality of bits; and a register having a width of a plurality of bits, said register connected to at least one of said internal data buses, said width of said register being equal to said width of said at least one of said internal data buses, wherein each bit of said register can be loaded in parallel from said at least one of said internal data buses, said register further having a serial input at a first end for receiving a single bit from at least one neighboring processing element into a first bit of said plurality of bits of said register and a serial output at a second end of said register for sending to at least one neighboring processing element a single bit out from a last bit of said plurality of bits of said register.