Patent ID: 8077616
Filing Date: 2011-12-13
Classification: H04L

Abstract:
1. A data transmission apparatus having a plurality of packet data processing blocks processing packet data between an input port and an output port, comprising: a reception processing block connected with said input port, equipped with a processing section and a temporary memory which stores a processing result of the packet data; a routing processing block connected with an output of said reception processing block, equipped with a processing section and a temporary memory which stores a processing result of the packet data; a filtering processing block connected with an output of said routing processing block, equipped with a processing section and a temporary memory which stores a processing result of the packet data; a queuing processing block connected with an output of said filtering processing block, equipped with a processing section and a temporary memory which stores a processing result of the packet data; an output processing block whose input is connected with an output of said filtering processing block and whose output is connected with said output port and a second output port, equipped with a processing section and a temporary memory which stores a processing result of the packet data; and a processing result storing block whose input is connected with outputs of said reception processing block, said routing processing block, said filtering processing block and said queuing processing block and whose output is connected with said output processing block, equipped with a storage section, a memory control section, a write section to said storage section and a read section from said storage section; said reception processing block receives packet data having a header, a data field and a processing result field from a receiver port, performs assigning an address in said storage section provided from said memory control section in said processing result storing block, and outputs said processing result of said packet data and stores the same in said temporary memory; said routing processing block selects a transmit port for transmitting out said data, from a plurality of transmit ports, based on a source address and a destination address carried in said header, and outputs and stores said processing result of said data in said temporary memory; said filtering processing block determines based on the transmit port selected, whether said data are to be discarded, performs processing for discarding said data when determined that said data are to be discarded, and outputs and stores said processing result of said data in said temporary memory; said queuing processing block stores said data in a transmit queue according to data priority, when said data were not discarded in said filtering processing block, and outputs and stores said processing result of said data in said temporary memory; said output processing block outputs said data stored in said transmit queue to said output port by appending the processing results to said data when said data were not discarded in said filtering processing block and outputs and stores the processing results at a second output port in said temporary memory, when said data were discarded; in said processing result storing block, said memory control section offers the address in said storage section to said reception processing block and enables a validity bit and an Used bit in offered address, said write section stores the processing results of each processing block in said storage section via the temporary memories in each processing block, and further, said read section reads out the stored information in the storage section and sends to the output processing block; in each processing block, after the address is assigned, the packet data is moved to a next processing block together with the assigned address when the Used bit of the address remains enabled, and the validity bit is disabled when the packet data is of the kind that need not be traced; and said memory control section disables the Used bit when detecting that a corresponding valid bit is to be disabled, and assigns the address of the disabled Used bit in the storage section to new packet data input to the reception processing block.