Patent ID: 7369618
Filing Date: 2008-05-06
Classification: H04L

Abstract:
1. A signal transmission circuit for transmitting a digital signal from a first circuit block to a second circuit block via a signal line, the first circuit block comprising a transmitting circuit including: a transition detection circuit for sequentially detecting a transition of a logic level of a supplied input digital signal so as to detect a high level period during which a logic high level is output to the signal line, and, a low level period during which a logic low level is output to the signal line; first and second transmitting capacitors; a precharge switch for setting a predetermined logic high voltage in the first transmitting capacitor at each low level period; a first transmitting switch for generating a small voltage change in the signal line at each high level period, the voltage change being in accordance with a voltage of the first transmitting capacitor that is set during a preceding low level period; a predischarge switch for setting a predetermined logic low voltage in the second transmitting capacitor at each high level period; and a second transmitting switch for generating a small voltage change in the signal line at each low level period, the voltage change being in accordance with a voltage of the second transmitting capacitor that is set during a preceding high level period, the second circuit block comprising a receiving circuit including: an inverter for amplifying a small voltage change in the signal line; a receiving capacitor inserted between an input terminal and an output terminal of the inverter; an equalizing switch inserted between the input terminal and the output terminal of the inverter; a first level circuit for supplying a first detection signal when a small positive voltage change in the signal line is detected from a voltage of the output terminal of the inverter; a second level circuit for supplying a second detection signal when a small negative voltage change in the signal line is detected from a voltage of the output terminal of the inverter; an output circuit for supplying an output digital signal having a logic level in accordance with a logic level of the input digital signal, in accordance with the first and second detection signals; and an equalizing control circuit for forcing the equalizing switch to be on for a certain period after the first detection signal or the second detection signal is supplied so as to set a voltage of the receiving capacitor to a predetermined voltage.