Patent ID: 6728910
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A system for self-test and self-repair of a semiconductor memory, said system comprising:a first portion of the memory, comprising an array of m rows and n columns; a second portion of the memory, comprising a array of p rows and n columns; test circuitry adapted to access the first and second portions as a single joint array comprising m+p rows and n columns, test the entirety of the joint array and detect rows failing the test, wherein the test circuitry comprises a single built-in self-test (BIST) engine having a fixed array size; repair circuitry adapted to replace failed rows in the first portion with non-failing rows from the second portion; and wherein the test circuitry is further adapted to retest the first and second portions of memory, while ignoring failing rows in the second portion.