Patent ID: 7528477
Filing Date: 2009-05-05
Classification: H01L

Abstract:
1. Castellation wafer level packaging for packaging an integrated circuit chip, said packaging comprising: an integrated circuit chip having active circuit areas having a top surface; at least one active circuit area contact, each of the at least one active circuit area contacts coupled to an active circuit area; a passivation layer having a top surface formed on the top surface of the active circuit areas, wherein the passivation layer encapsulates the at least one active circuit area contact such that a top surface of the at least one active circuit area contact is exposed; and at least one castellation contact formed on the top surface of the passivation layer and that extends normal to the top surface of the passivation layer, each of the at least one castellation contacts coupled to an active circuit area contact, wherein each of the at least one castellation contacts is (a) large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste, and (b) substantially encapsulated by a material such that no top surface of the castellation contact is encapsulated, wherein the at least one castellation contact is in direct contact with the material, and wherein the material is different from the passivation layer.