Patent ID: 6785851
Filing Date: 2004-08-31
Classification: H04L

Abstract:
An apparatus, comprising:a first counter group having a first set of N-bit registers, only one of the N-bit registers to increment in a clock cycle in response to a first input received, the first input being one of a first set of inputs designated to be received by the first counter group; a first adder to increment in response to incrementing the only one N-bit register in the first counter group; a second counter group having a second set of N-bit registers, only one N-bit register in the second counter group to increment in the clock cycle in response to a second input received, the second input being one of a second set of inputs designated to be received by the second counter group, the second input being different from the first input; and a second adder to increment in response to incrementing the only one N-bit register in the second counter group.