Patent ID: 6604116
Filing Date: 2003-08-05
Classification: G06F,Y10S

Abstract:
A memory controller for managing memory transactions from a plurality of processors, wherein the memory controller is connected between a memory and at least one bus, the plurality of processors are connected to the one bus, and each transaction originated from a particular processor of the plurality of processors, the memory controller comprising:a storage queue for storing status information of the memory transactions from the one bus; and a state machine for determining whether any of the transactions are completed transactions based on the status information, and if there are no completed transactions, determines which of the transactions is a partially completed transaction that is most likely to become a completed transaction based on the status information; wherein if there is at least one completed transaction, then the memory controller forms a response and returns the response to the originating processor; and if there are no completed transactions, the memory controller sets up a response for the partially completed transaction and holds the response until the partially completed transaction becomes a completed transaction.