Patent ID: 7027548
Filing Date: 2006-04-11
Classification: H03D,H03L

Abstract:
1. A delay-locked-line (DLL) comprising: a voltage-controlled delay line (VCDL) that varies a timing of a delayed clock signal with respect to an intermediate clock signal in response to a magnitude of a control voltage; a phase detector connected to the VCDL that detects a difference in phase between a reference clock signal and the delayed clock signal, the phase detector asserting an up signal when the reference clock signal leads the delayed clock signal, a down signal when the reference clock signal lags the delayed clock signal, and a synch signal when the reference clock signal and the delayed clock signal are in phase; a charge pump connected to the phase detector that outputs a pump voltage, the charge pump increasing the pump voltage when the up signal is asserted, decreasing the pump voltage when the down signal is asserted, and leaving the pump voltage unchanged when the synch signal is asserted; a filter connected to the charge pump and the VCDL that filters the pump voltage to output the control voltage; and a delay circuit that varies a timing of the intermediate clock signal with respect to the reference clock signal by adding or subtracting incremental units of delay in response to the control voltage and the logic states of the up signal, the down signal, and the synch signal; and wherein the VCDL includes: a voltage-controlled current stage that outputs a switching current having a magnitude defined by the magnitude of the control voltage; and a fine-delay stage having a number of devices, the devices having a propagation delay, a magnitude of the propagation delay being defined by the magnitude of the switching current, the delayed clock signal being delayed in time from the intermediate clock signal by the propagation delay, and wherein the phase detector includes: a D-Q flip-flop having a D input connected to receive the delayed clock signal, a clock input connected to receive the reference clock signal, and a Q output; an XNOR gate having a first input connected to receive the delayed clock signal, a second input connected to receive the reference clock signal, and an output; a first inverter having an input connected to the Q output, and an output; a second inverter having an input connected to the output of the first inverter, and an output; a first NOR gate having a first input connected to the output of the XNOR gate, a second input connected to the output of the second inverter, and an output that outputs the up signal; and a second NOR gate having a first input connected to the output of the XNOR gate, a second input connected to the output of the first inverter, and an output that outputs the down signal.