Patent ID: 7936621
Filing Date: 2011-05-03
Classification: G11C,H03L

Abstract:
1. A double data ratio synchronous type dynamic random access memory, comprising: a semiconductor chip having a clock generating circuit and an internal circuit whose operation is controlled by clock signals from the clock generating circuit, wherein the internal circuit comprises: a plurality of word lines; a plurality of data lines; a plurality of dynamic type memory cells which are coupled to the plurality of word lines and the plurality of data lines; a plurality of sense amplifiers each of which is coupled to the plurality of data lines; a data signal output circuit which is coupled to the plurality of sense amplifiers and outputs data signals to outside of the double data ratio synchronous type dynamic random access memory from the plurality of dynamic type memory cells in synchronism with rising and falling of clock signals generated by the clock generating circuit; and a data strobe signal output circuit which is operated in response to clock signals from the clock generating circuit and which is synchronized with data signals from the data signal output circuit, wherein the clock generating circuit comprises: a delay circuit which receives first clock signals and generates second clock signals by delaying the first clock signals for predetermined time; a phase comparing circuit which compares a phase of the first clock signals and a phase of third clock signals based on the second clock signals and generates control signals; and a control circuit which controls the delay circuit for coinciding the phase of the first clock signals and the third clock signals in accordance with the control signals, wherein the semiconductor chip comprises: a first power source pad for supplying a first power source voltage to the delay circuit; a second power source pad for supplying a second power source voltage which is lower than the first power source voltage to the delay circuit; a third power source pad for supplying a third power source voltage to the data signal output circuit; and a fourth power source pad for supplying a fourth power source voltage which is lower than the third power source voltage to the data signal output circuit, wherein the double data ratio synchronous type dynamic random access memory includes: a first terminal which is coupled to the first power source pad; a second terminal which is coupled to the second power source pad; a third terminal which is coupled to the third power source pad and which is different from the first terminal; and a fourth terminal which is coupled to the fourth power source pad and which is different from the second terminal, wherein a first path for supplying power to the delay circuit includes the first terminal, the first power source pad, the second terminal and the second power source pad, wherein a second path for supplying power to the internal circuit includes the third terminal, the third power source pad, the fourth terminal and the fourth power source pad and wherein the second path is different from the first path.