Patent ID: 8588019
Filing Date: 2013-11-19
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell storing data in accordance with an amount of current supplying capability: a bit line electrically connected to the memory cell, the bit line transmitting the data of the memory cell; a first transistor having a gate terminal connected to a first signal line supplied with at least a first potential as a transfer control voltage, one source/drain terminal connected to the bit line, and another source/drain terminal connected to a sense node; a second transistor having a gate terminal connected to the sense node, a drain terminal connected to an output node, and a source terminal connected to a signal line supplied with a low potential, the second transistor amplifying a signal transmitted from the bit line to the sense node via the first transistor; a sense node potential supplying circuit supplying a second potential to the sense node in response to a precharge control signal; a bit line potential supplying circuit supplying a third potential to the bit line in response to the precharge control signal; and a potential control circuit controlling at least the first to third potentials, wherein the potential control circuit controls the first potential to be set between the second and third potentials, controls the second potential to be larger in absolute value than the third potential, and controls a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential to be smaller in absolute value than the third potential and larger in absolute value than the low potential, and a potential of the bit line transitions from the third potential toward the low potential in accordance with the data of the memory cell, regardless of “1” or “0” of the data.