Patent ID: 7312141
Filing Date: 2007-12-25
Classification: H01L

Abstract:
1. A method of manufacturing an integrated circuit, comprising: providing a dielectric layer having a bottom surface disposed over a semiconductor substrate; forming a metal filled trench filled with a layer of metal in said dielectric layer, said metal filled trench extending from a top surface of said dielectric layer toward said bottom surface of said dielectric layer; forming a plurality of square dielectric pedestals in said metal filled trench, said dielectric pedestals filled with said dielectric layer, said dielectric pedestals extending from a top surface of said metal filled trench to a bottom surface of said metal filled trench; forming an additional trench filled with said layer of metal disposed in said dielectric layer, said additional metal filled trench extending from a top surface of said dielectric layer toward said bottom surface of said dielectric layer; forming a plurality of additional square dielectric pedestals disposed in said metal filled trench, said additional dielectric pedestals filled with said dielectric layer, said additional dielectric pedestals extending from a top surface of said metal filled trench to a bottom surface of said metal filled trench; and said metal filled trench having a first width, said dielectric pedestals having a second width less than said first width, said additional metal filled trench having a third width, said additional dielectric pedestals having a fourth width less than said third width, wherein said first width divided by said second width is equal to said third width divided by said fourth width.