Patent ID: 9099493
Filing Date: 2015-08-04
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a dummy gate on an ETSOI layer of a substrate, the substrate having an SOI layer, a buried oxide layer on the SOI layer, and the ETSOI layer on the buried oxide layer; epitaxially forming at least two raised source/drain regions adjacent to the dummy gate; forming a protective cap on the at least two raised source/drain regions; applying at least one acid to remove the dummy gate from the ETSOI; depositing a gate dielectric layer on the protective cap and on the ETSOI after removing the dummy gate from the ETSOI layer; forming a replacement metal gate on the gate dielectric layer to replace the removed dummy gate; removing the gate dielectric layer from the protective metal cap and the protective cap from the at least two raised source/drain regions; forming a passivation layer on the replacement metal gate; forming a silicide contact on each of the at least two raised source/drain regions; depositing a dielectric layer on the passivation layer and on the silicide contacts; forming first vias through the dielectric layer to the silicide contacts; and forming a second via through the dielectric layer and the passivation layer to the replacement metal gate.