Patent ID: 6453276
Filing Date: 2002-09-17
Classification: G01R,G06F

Abstract:
A method for generating a test input representing a number of user defined test conditions for a circuit design having a number of circuit sections, the test input including a number of test conditions that represent logic states that are used by a logic simulator to control one or more nodes of the circuit design when simulating the behavior of the circuit design, the method comprising the steps of:providing a template for allowing a user to enter a number of test conditions, wherein the template is logically divided into a number of predefined regions; entering a number of test conditions into the template including providing a first portion of selected test conditions in a first one of the predefined regions and a second portion of selected test conditions in a second one of the predefined regions, wherein the first predefined region is associated with a first circuit section and the second predefined region is associated with a second circuit section; and processing the template to provide the test input to be used by the logic simulator to simulate the behavior of the circuit design.