Patent ID: 7039847
Filing Date: 2006-05-02
Classification: G11C

Abstract:
1. A coding-decoding device using a memory device and an operation device having a programmable hardware logic circuit, for converting first sentences expressed with binary numbers into second sentences expressed with binary numbers of b bits, wherein said memory device stores b pieces of conversion logic equations, each including the bit values of said first sentence as elements, for calculating the bit values of said second sentence, and wherein said operation device, according to plural execution unit logic equations obtained by dividing into execution units said b pieces of conversion logic equations stored in said memory device, sequentially constitutes logics for each of said execution unit logic equations, and sequentially divides and calculates from said first sentences, on the basis of said constituted logics, said second sentences, the coding-decoding device comprising a conversion logic equation producing device for producing said b pieces of conversion logic equations by converting all the first sentences into second sentences according to a given conversion method, giving a term representing the logical product of all the bit values constituting the first sentence corresponding as the term corresponding to the bit for which the bit value of the second sentence obtained by conversion is a logic “1”, and taking a logical sum of the logical product for each of b bits of the bit values of the second sentences.