Patent ID: 6465364
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method for fabricating contact plugs of an embedded memory, the method comprising:providing a semiconductor wafer with both a memory array region and a periphery circuit region defined on the surface of the silicon substrate of the semiconductor wafer; forming separately a plurality of MOS transistors in the memory array region and the periphery circuit region, forming a first dielectric layer in the memory array region; forming a plurality of landing pads in the dielectric layer in the memory array region; forming a stop layer on the surface of the semiconductor wafer; forming a second dielectric layer on the surface of the stop layer; forming a first photoresist layer on the surface of the semiconductor layer; performing a first etching process to define a pattern of plurality of contact plugs in the first photoresist layer in both the memory array region and the periphery circuit region; using the pattern of the first photoresist layer as a hardmask to etch the second dielectric layer down to the surface of the stop layer so as to form a plurality of contact plug holes in the second dielectric layer; removing the stop layer on the bottom surface of each contact plug hole; and filling each contact plug hole with a conductive layer, so as to form in-situ each contact plug in both the memory array region and the periphery circuit region.