Patent ID: 6144585
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A semiconductor storage device comprising:at least first and second memory cells connected serially to each other, each memory cell having a control gate and an electric charge accumulating layer, and a threshold value of a gate voltage of each memory cell being controlled to be one of a plurality of different values to thereby store data taking one of 2.sup.n possible values where n is an integer greater than 1 in each memory cell;a voltage control circuit for applying voltages to the control gates of said at least first and second memory cells in accordance with a control signal;a sense amplifier for detecting whether or not a current flows across the serially connected at least first and second memory cells when said voltage control circuit applies voltages to the control gates of said at least first and second memory cells; anda signal control circuit for receiving an output signal of said sense amplifier and for outputting the control signal for controlling said voltage control circuit to (i) apply a first voltage having a value larger than a predetermined one of said plurality of different values to the control gate of said first memory cell and apply a preset voltage having a value larger than a maximum one of said plurality of different values to the control gate of the other memory cell, (ii) apply a second voltage having a value smaller than the value of the first voltage to the control gate of said first memory cell and apply the preset voltage to the control gate of the other memory cell when said sense amplifier detects a current flow due to application of the first voltage, (iii) apply a third voltage having a value larger than the value of the first voltage to the control gate of said first memory cell and apply the preset voltage to the control gate of the other memory cell when said sense amplifier detects no current flow in spite of application of the first voltage, (iv) apply a fourth voltage having a value larger than a predetermined one of said plurality of different values to the control gate of said second memory cell and apply the preset voltage to the control gate of the other memory cell, (v) apply a fifth voltage having a value smaller than the value of the fourth voltage to the control gate of said second memory cell and apply the preset voltage to the control gate of the other memory cell when said sense amplifier detects a current flow due to application of the fourth voltage, and (vi) apply a sixth voltage having a value larger than the value of the fourth voltage to the control gate of said second memory cell and apply the preset voltage to the control gate of the other memory cell when said sense amplifier detects no current flow in spite of application of the fourth voltage; whereby said data stored in each memory cell is read in fewer than 2.sup.n -1 operations.