Patent ID: 9202817
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a dielectric layer and a dummy gate layer on a substrate; patterning the dielectric layer and the dummy gate layer to form a plurality of gate stacks on the substrate; sequentially forming a tunneling layer, a charge trapping layer, a blocking layer, and a main gate layer on the substrate; patterning the tunneling layer, the charge trapping layer, the blocking layer, and the main gate layer, such that the gate stacks become at least one split gate stack with the tunneling layer, the charge trapping layer, the blocking layer, and the main gate layer and at least one logic gate stack; forming sources and drains corresponding to the split gate stack and the logic gate stack; and respectively replacing at least one of the dummy gate layer and the main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and at least one metal logic gate.