Patent ID: 7199462
Filing Date: 2007-04-03
Classification: H01L,H05K

Abstract:
1. A parent substrate for producing a plurality of unit substrates for a semiconductor device, the parent substrate comprising: an insulation layer having first and second surfaces opposing to each other; upper and lower conductor patterns respectively formed on the first and second surfaces of the insulation layer; and upper and lower photo solder resist (PSR) layers respectively formed over the first and second surfaces of the insulation layers and covering at least some area of the upper and lower conductor patterns, wherein the parent substrate defines an upper part and a lower part divided by a reference surface passing through the center line of the insulation layer, wherein, when an equivalent thermal expansion coefficient α where α b , α c and α p are thermal expansion coefficients of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, E b , E c and E p are elastic moduli of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and v b , v c and v p are volume ratios of upper insulation layer, upper conductor pattern and upper PSR layer, respectively, and when an equivalent thermal expansion coefficient α lower of the lower part is defined as follows: where α b , α c and α p are thermal expansion coefficients of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, E b , E c and E p are elastic moduli of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, and v b , v c and v p are volume ratios of lower insulation layer, lower conductor pattern and lower PSR layer, respectively, an equivalent thermal expansion coefficient ratio (α upper /α lower ) of α upper to α lower is selected to be within a range of between 0.975 and 1.165.