Patent ID: 7054196
Filing Date: 2006-05-30
Classification: G11C,H01L

Abstract:
1. A method for programming a P-channel electrical erasable programmable read-only memory (EEPROM) having an N-well, a floating gate, a control gate, a P-type source region, a P-type drain region and a select transistor coupling the drain region to a bit line, the method comprising the steps of: grounding the N-well; applying a first positive voltage to the control gate; applying a second positive voltage or a programming current to the source region; and applying a first negative voltage to the bit line and switching on the select transistor, so that the first negative voltage is passed to the drain region, wherein the second positive voltage or the programming current leads to a forward bias capable of turning on a parasitic bipolar transistor that includes the source region, the drain region and the N-well, and a reverse bias between the drain region and the N-well is capable of generating an electron current between the source region and the drain region for injection into the floating gate.