Patent ID: 6452603
Filing Date: 2002-09-17
Classification: G06T

Abstract:
A circuit for use in a texture system, the circuit comprising:a nearest texel bus that carries a first group of texels, hereinafter nearest texels, that are located nearest to a to-be-displayed pixel, the nearest texels being at a level of detail L; a surrounding texel bus that carries a second group of texels, hereinafter surrounding texels, that each touch a nearest texel in the first group, the surrounding texels also being at the level of detail L; a coordinate input bus that carries, at the level of detail L, two coordinates of a to-be-displayed pixel; a level of detail bus that carries a fractional level of detail p of the to-be-displayed pixel; a texel output bus that carries a texel at a level of detail L+p; and an interpolation subcircuit coupled to receive signals from the coordinate input bus, the level of detail bus, the nearest texel bus, and the surrounding texel bus, the interpolation subcircuit being configured to generate an interpolated texel at the level of detail L+p using the nearest texels and the surrounding texels and to supply the interpolated texel to the texel output bus.