Patent ID: 6103575
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of manufacturing a single-poly flash memory cell on a semiconductor substrate, said method comprising the steps of:(a) forming a gate oxide layer on said semiconductor substrate, said gate oxide layer having at least a thin portion and at least a thick portion;(b) forming a polysilicon layer atop said gate oxide layer;(c) patterning and etching said polysilicon layer to produce a floating gate and a control gate, said floating gate located atop said thin portion of said gate oxide layer, said control gate being atop said control gate being atop said thick portion of said gate oxide layer;(d) forming dielectric regions between said control gate and said floating gate;(e) forming dielectric sidewall spacers of said control gate and said floating gate; and(f) ion implanting dopants into said semiconductor substrate using said dielectric regions, sidewall spacers, floating gate, and control gate as a mask to form source and drain regions.