Patent ID: 6493267
Filing Date: 2002-12-10
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a non-volatile memory cell; a bit line coupled to said non-volatile memory cell; a flip-flop circuit having first and second nodes, said flip-flop circuit holding write data supplied thereto; a switching circuit disposed between said bit line and said first node of said flip-flop circuit, said switching circuit responsive to a switching signal for electrically connecting said bit line and flip-flop circuit during a write operation for writing the write data to said non-volatile memory cell; and a MOS transistor circuit including first and second MOS transistors coupled in series between said first node of said flip-flop circuit and a first potential node, said first MOS transistor having a gate supplied with a potential of said bit line, and said second MOS transistor having a gate supplied with a clock signal.