Patent ID: 6686630
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A sub-0.05 &mgr;m double-gated MOSFET device comprising:a substrate which includes a source region and a drain region abutting a sub-0.05 &mgr;m doped channel region, said source and drain regions do not extend beyond a lower surface of the channel region, said channel region is located in a portion of a semiconducting material layer of a silicon-on-insulator wafer, and said semiconducting layer having a thickness of less than about 200 Ã¥ and is sandwiched between two gate dielectrics; an implanted doped backside gate electrode formed beneath said channel region; and a polysilicon frontside gate electrode formed over said channel region, said implanted-doped backside gate electrode, said channel region and said polysilicon frontside gate electrode are self-aligned to each other and to the source and drain regions.