Patent ID: 6482724
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of fabricating a transistor, comprising the steps of:providing a silicon substrate with a region of a first conductivity type; forming an insulator layer over said substrate; forming a disposable gate over said insulator layer over said substrate region of said first conductivity type; forming a plurality of sidewall structures adjacent to said disposable gate; forming source and drain regions adjacent to said sidewall structures; forming an insulator layer over said source and drain regions; removing said disposable gate to form a gap between said plurality of sidewall structures without substantially removing any other exposed material; implanting a dopant species of a first conductivity type at an angle into said gap to form a localized high threshold voltage region adjacent to an extension region wherein said high threshold voltage region does not extend over the entire gap; removing said insulator layer in said gap exposing a portion of said silicon substrate; forming a gate dielectric over said exposed portion of said silicon substrate; and forming a gate electrode over said gate dielectric.