Patent ID: 6029266
Filing Date: 2000-02-22
Classification: G11B,H03M,H04L

Abstract:
An error correcting apparatus of a digital processing system to correct errors in channel data, comprising:a demodulator to demodulate said channel data to demodulation data and generating error flags based upon the errors occurs during the demodulation;a synchronous detector to receive said error flags and demodulation data generated from said demodulator, and to detect a synchronizing signal of said demodulation data to distinguish data by a unit of code capable of correcting the errors;a first decoder to decode said demodulation data and said error flags by a unit of row by said synchronizing signal, and to correct general errors and erasure errors of the errors of said demodulation data; anda second decoder to decode said demodulation data and said error flags by a unit of column by said synchronizing signal, and to correct other general errors and erasure errors of said demodulation data that said first decoder is unable to correct.