Patent ID: 6576947
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A DRAM cell capacitor comprising:a first insulating layer formed on an integrated circuit substrate; a contact plug formed in the first insulating layer, and electrically connected to the substrate wherein the contact plug protrudes from a top surface of the first insulating layer; a cylindrical storage node formed on top and sidewall surfaces of the contact plug and the top surface of the first insulating layer; a second insulating layer formed on the first insulating layer, wherein the thickness of the second insulating layer is almost equal to the protrusion height of the contact plug, and the second insulating layer is completely separated from the contact plug by the cylindrical storage node; and a third insulating layer formed on the second insulating layer, wherein the etch selectivity of the third insulating layer is different from that of the second insulating layer.