Patent ID: 6472308
Filing Date: 2002-10-29
Classification: H01L

Abstract:
An integrated circuit manufacturing process for fabricating a borderless via for interconnecting a first bottom metal line to a second top metal line in a multilevel metallization structure on a semiconductor substrate, said first bottom metal line having a top conducting surface, comprising the steps of:providing a semiconductor substrate having devices therein to be connected, having an insulating layer on said substrate, and having a bottom metal layer deposited onto said insulating layer on said substrate; patterning and etching said bottom metal layer to provide said first bottom metal line having an exposed top conducting surface and an edge surface, and to expose portions of said insulating layer; forming a dielectric layer surrounding said bottom metal line, said dielectric layer having a top dielectric surface substantially locally planar with said top conducting surface of said bottom metal line near said bottom metal line; depositing a non-conducting via etch stop layer onto said top conducting surface of said bottom metal line and said top dielectric surface; depositing an ILD layer onto said via etch stop layer; etching a via having a first and a second portion through said ILD layer to expose the region of said via etch stop layer under said via, said via etch stop layer being substantially unetched by said via etch, said first via portion being atop said via etch stop layer atop said bottom metal line, and said second via portion being atop said via etch stop layer atop said dielectric layer, said via having a bottom surface and a side surface; removing said exposed region of said via etch stop layer to expose the region of said top conducting surface of said bottom metal line and the region of said top dielectric surface under said via; depositing a barrier/nucleation/adhesion layer onto said via side surface and onto said exposed portion on said top conducting surface of said bottom metal line and said top dielectric surface; and filling said via with a conductive material wherein during said via filling step said top surface and said edge surface of said bottom metal line are protected by intervening layers from exposure to reactants and reaction products of said via filling step.