Patent ID: 7636018
Filing Date: 2009-12-22
Classification: H03L

Abstract:
1. A phase locked loop (PLL), comprising: a plurality of phase shifters, shifting a phase of an input signal so as to generate a plurality of shifted signals; a plurality of phase frequency detectors (PFDs), coupled to the phase shifters, the PFDs comparing the phase of the input signal with the phase of a frequency division output signal or comparing the phase of the shifted signals with the phase of the frequency division output signal to generate a plurality of voltage control signals, wherein the PFDs perform phase comparisons within a cycle of the input signal; a plurality of charge pumps (CPs), coupled to the PFDs, in response to the voltage control signals, the CPs controlling a node voltage; a voltage controlled oscillator (VCO), in response to the node voltage, the VCO oscillating and generating an output signal; a frequency divider, dividing the frequency of the output signal from the VCO so as to generate the frequency division output signal; and a circulator, coupled to the frequency divider, the circulator selectively outputting the frequency division output signal to the PFDs.