Patent ID: 8385340
Filing Date: 2013-02-26
Classification: H04L

Abstract:
1. A packet processor, comprising: a memory storing microcode that specifies respective sets for a plurality of types of a plurality of packets, each of the packets having a type of the plurality of types, and the respective set for each type specifies a plurality of elementary operations for each of a plurality of stages other than an initial stage of the plurality of stages; and a programmable compute pipeline coupled to the memory for sequentially processing the plurality of packets, wherein: wherein the programmable compute pipeline is one of a plurality of programmable compute pipelines arranged in a programmable protocol pipeline for a plurality of protocol layers, and for each first and successive second one of the programmable compute pipelines in the programmable protocol pipeline, the first programmable compute pipeline is programmable to determine a second offset from a first offset and provide the second offset to the second programmable compute pipeline.