Patent ID: 7651937
Filing Date: 2010-01-26
Classification: H01L

Abstract:
1. A bumping process of forming a conductive bump on a wafer, comprising: providing a wafer having a plurality of pads; forming an under-bump metallurgy layer (UBM layer) on the pad; coating a conductive first photo-resist layer on the wafer to cover the UBM layer; coating a second photo-resist layer on the conductive first photo-resist layer; removing at least a portion of the second photo-resist layer to form an opening above the UBM layer, wherein the conductive first photo-resist layer maintains electric connection with the UBM layer; forming a solder layer in the opening by electroplating process; and removing the conductive first photo-resist layer and the second photo-resist layer expect the portion of the conductive first photo-resist layer under the solder layer.