Patent ID: 6539504
Filing Date: 2003-03-25
Classification: G06F,G11B

Abstract:
A memory system, comprising:a memory in which memory words are stored that respectively have a data word and a control word, the memory having a) two memory units, wherein a data word segment and a control word segment are respectively stored together in each memory unit, and b) two error monitoring apparatuses that carry out an error monitoring of the memory word for multi-bit errors based on the control word; a memory control unit for controlling the memory, the memory control unit having an additional two error monitoring apparatuses for error monitoring between the memory control unit and the memory; and a doubled line structure between the memory control unit and the memory for doubled transfer of the memory words between the memory control unit and the memory, wherein the doubled line structure between the memory and the memory control unit is partially cross-connected such that one of the two segments of each data word being transferred is cross-connected.