Patent ID: 7115967
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A memory disposed above a substrate comprising: a plurality of memory levels organized as first alternate levels disposed between second alternate levels; a plurality of two terminal memory cells incorporated into each of the levels; one terminal of the cells in each of the first alternate levels and each of the second alternate levels being coupled to first lines shared by the cells in each pair of first and second alternate levels; the other terminal of the cells in each of the first alternate levels being coupled to second lines; and the other terminal of the cells in each of the second alternate levels being coupled to third lines, wherein each cell comprises, when programmed, a diode and an antifuse layer, wherein the diodes comprise an N− region and a P+ region, wherein the N− regions in the diodes in at least one of the first and second alternate levels has a smaller cross-section than the P+ region.