Patent ID: 7269808
Filing Date: 2007-09-11
Classification: G06F

Abstract:
1. A design verification method, comprising: providing in a design a design electrically conductive line and a design electrically conductive contact region being in direct physical contact with the design electrically conductive line; modeling a simulated electrically conductive line of the design electrically conductive line; simulating a possible electrically conductive contact region of the design electrically conductive contact region, wherein the design electrically conductive contact region and the possible electrically conductive contact region are not identical; and determining that the design electrically conductive line and the design electrically conductive contact region are potentially defective if an interfacing surface area of the simulated electrically conductive line and the possible electrically conductive contact region is less than a pre-specified value; wherein the possible electrically conductive contact region has a minimum linear size in a reference plane that is parallel to the interfacing surface within a linear size tolerance of a fabrication process which will be used to fabricate the design electrically conductive contact region.