Patent ID: 8093662
Filing Date: 2012-01-10
Classification: G11C,H01L

Abstract:
1. A semiconductor memory comprising: a plurality of bit lines that extend on a memory cell array along the column length of the memory cell array; a plurality of word lines that extend along the row length of the memory cell array; and a plurality of first via contacts formed at respective one ends of the bit lines, wherein, the bit lines are linearly formed, and the lengths of at least two adjacent bit lines along the column length differ from each other; the first via contacts are in contact with part of one of the plurality of bit lines and are disposed on a straight line along the row length; the respective one ends of the bit lines contacted to the plurality of first via contacts are disposed on a straight line along the row length; and respective one ends of a plurality of bit lines adjacent to the bit lines contacted to the plurality of the first via contacts are disposed on a straight line along with the row length.