Patent ID: 6800905
Filing Date: 2004-10-05
Classification: H01L

Abstract:
An asymmetric field effect transistor (FET) comprising:a patterned stack including at least a vertical semiconductor body having sidewalls located on an upper non-recessed surface of an insulator that is located on a substrate; a gate dielectric located on each sidewall of said vertical semiconductor body, a p-type gate portion located on one side of the vertical semiconductor body and an n-type gate portion located on an opposing side of the vertical semiconductor body, said gate portions together with said vertical semiconductor body forming a single asymmetric FET device that is located on said lapper surface of the insulator; a double implanted region located adjacent to each of said gate portions and on said insulator; An interconnect located at least over said p-type gate portion and said n-type gate portion; and a planarizing structure above said interconnect.