Patent ID: 7973572
Filing Date: 2011-07-05
Classification: H03K

Abstract:
1. An output buffer, comprising: a first input stage circuit; a first output stage circuit connected to a first data line, wherein the first data line is connected to a plurality of first pixels on a first column, the first output stage circuit generates a first data signal to the plurality of first pixels, and the plurality of first pixels display brightness according to the first data signal; a second output stage circuit connected to a second data line, wherein the second data line is connected to a plurality of second pixels on a second column, the second output stage circuit generates a second data signal to the plurality of second pixels, and the plurality of second pixels display brightness according to the second data signal; a first switching module coupled between the first input stage circuit and the first output stage circuit; and a second switching module coupled between the first input stage circuit and the second output stage circuit, wherein when the plurality of first pixels receive the first data signal, the plurality of second pixels does not receive the first data signal, and when the plurality of second pixels receive the second data signal, the plurality of first pixels does not receive the second data signal.