Patent ID: 6764923
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of manufacturing a multi-layered wafer with at least one device component thereon, comprising the steps:a) providing a first initial wafer (110) comprising silicon and including a first substrate (900), a first insulating intermediate layer (901) on said first substrate, and a first surface layer on said first insulating intermediate layer; b) providing a second initial wafer (400) comprising silicon, and including a second substrate; c) forming at least one laterally limited silicide area (414, 415, 416) formed of a silicide in and/or on said first surface layer of said first initial wafer; d) providing at least one insulating layer (401) on at least one of an exposed surface of said second initial wafer after said step b) and an exposed surface of said first surface layer of said first initial wafer after said step c); e) after said steps a), b), c) and d), bonding together said first initial wafer and said second initial wafer along a new outer surface of said at least one insulating layer (401); f) after said step e), removing said first substrate (900) and at least part of said first insulating intermediate layer (901) of said first initial wafer, to leave said multi-layered wafer including at least part of said first surface layer, said at least one laterally limited silicide area (414, 415, 416), at least part of said second initial wafer (400), and said at least one insulating layer (401) between said at least one laterally limited silicide area and said at least one part of said second initial wafer; and g) fabricating said at least one device component in and/or on said first surface layer to include said at least one laterally limited silicide area respectively as a functional element of said at least one device component.