Patent ID: 6524938
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method for the creation of a gate electrode structure with improved profile control, comprising the steps of:providing a substrate, said substrate having been provided with at least one region of Shallow Trench Isolation (STI) over the surface thereof; creating a layer of gate oxide over the surface of said substrate, thereby including the surface of said at least one STI region provided over the surface of said substrate; depositing a layer of gate material over the surface of said layer of gate oxide; depositing a layer of hardmask material over the surface of said layer of gate material to a first thickness; creating at least one first gate electrode over the surface of said substrate, further creating at least one second gate electrode over the surface of said region of Shallow Trench Isolation, said first and second gate electrodes comprising a patterned layer of gate material over which a patterned layer of hardmask material remains in place to a second thickness; creating a layer of liner oxide over sidewalls of said patterned and etched layer of gate material and over the surface of said substrate; depositing a layer of gate spacer material over the surface of said layer of liner oxide; and etching the deposited layer of gate spacer material, thereby creating gate spacers overlying sidewalls of said patterned and etched layer of gate material, thereby furthermore removing said patterned layer of hardmask material overlying said patterned and etched layer of gate material.