Patent ID: 6957245
Filing Date: 2005-10-18
Classification: G06F

Abstract:
1. A method of generating carry information during an arithmetic operation of a first input signal A and second input signal B, the method comprising: generating a plurality of carry-create signals in response to logical combinations of corresponding first groups of bit pairings of the first and second input signals; generating a plurality of carry-transmit signals in response to logical combinations of corresponding second groups of bit pairings of the first and second input signals, wherein the first groups of bit pairings are different from the second groups of bit pairings; and logically combining the carry-create and carry-transmit signals to create a number of accumulated carry-create signals that represent accumulated carry information at predetermined bit intervals, wherein each carry-create signal is generated according to the logical expression J[z→x]=(Az|Bz)+(Ay|By)+(Ax|Bx), where | is the logical AND operation and + is the logical OR operation, and x, y, and z represent consecutive bit positions of the input signals.