Patent ID: 7291543
Filing Date: 2007-11-06
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor wafer having a first surface and a second surface, the first surface having a plurality of circuitry elements forming a plurality of semiconductor dice thereon, at least one semiconductor die having a plurality of spaced apart bond pads located thereon; the method comprising: forming electrically conductive bumps on the plurality of spaced apart bond pads of the at least one semiconductor die, the conductive bumps having a height thereof extending above the plurality of spaced apart bond pads of the at least one semiconductor wafer, the conductive bumps including conductive bumps formed by at least one of screen printing, plating, sputtering, evaporation, or selective deposition/layering and layer removal; covering a portion of the height of the conductive bumps; applying a structural material to a portion of the first surface of the semiconductor wafer, the structural material disposed between the electrically conductive bumps to expose a portion of the height of the conductive bumps extending thereabove for connecting the conductive bumps to at least one circuit of a substrate; and performing a thinning process on the second surface of the semiconductor wafer.