Patent ID: 8300490
Filing Date: 2012-10-30
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a word line coupled to memory cells and configured to transmit a word line signal; at least one word repeater circuit including a first load circuit that is disposed on the word line; a first dummy word line disposed along the word line and configured to transmit a first dummy word line signal; at least one dummy repeater circuit including a second load circuit that is disposed on the first dummy word line; bit lines coupled to the memory cells; column switches configured to couple the bit lines to data lines, respectively; a column selection line disposed along the word line and configured to transmit a column selection signal for controlling each column switch; and at least one column repeater circuit disposed on the column selection line and configured to output the column selection signal in synchronization with the first dummy word line signal input to the first dummy repeater circuit.