Patent ID: 8166371
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a cell array formed by a plurality of memory cells storing page data therein arranged in a matrix, wherein the page data is stored in the cell array in units of pages the page data is divided into a plurality of sectors, the plurality of sectors are divided into a plurality of code words and a plurality of check codes corresponding to the plurality of code words, and the plurality of sectors are successively transferred to a latch circuit; a plurality of shift registers able to successively shift and hold the plurality of code words included in the page data to be written; a first switch circuit for receiving the page data to be written including the plurality code words and inputting at least a successive code word of the plurality of code words to the plurality of shift registers; a second switch circuit for selectively outputting the successive code word data of each shift register in which the successive code words are all shifted; a check code generation circuit for checking the successive code words selected so as to be output by the second switch circuit and generating the check codes; and an additional circuit for adding the check codes to the successive code words selectively output by the second switch circuit and outputting the same as the main code words to the latch circuit.