Patent ID: 7257764
Filing Date: 2007-08-14
Classification: H03M,H04B,H04L

Abstract:
1. A receiver, comprising: a demodulator that is operable to demodulate an input signal stream thereby generating a demodulated signal stream that includes FEC (Forward Error Correction) blocks; an FEC decoding chain functional block that is operable to be configured to perform FEC decoding of a first plurality of FEC blocks of the demodulated signal stream using a first plurality of FEC decoding parameters; wherein the FEC decoding chain functional block is operable to detect a CP (Control Packet) when performing FEC decoding of the first plurality of FEC blocks of the demodulated signal stream; a parameter extraction functional block that is operable to extract a second plurality of FEC decoding parameters from the CP; wherein the parameter extraction functional block is operable to provide the second plurality of FEC decoding parameters to the FEC decoding chain functional block; wherein the FEC decoding chain functional block is operable to be reconfigured to perform subsequent FEC decoding using the second plurality of FEC decoding parameters; wherein the second plurality of FEC decoding parameters corresponds to a second plurality of FEC blocks that is located a number of FEC blocks after the CP within the demodulated signal stream; and wherein the FEC decoding chain functional block performs FEC decoding of the second plurality of FEC blocks of the demodulated signal stream using the second plurality of FEC decoding parameters.