Patent ID: 8081530
Filing Date: 2011-12-20
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells connected between a word line and a bit line pair; a bit line sense amplifier configured to amplify voltages of data from the bit line pair and then transmitting the data to a local data line pair; a local sense amplifier configured to amplify voltages of the data from the local data line pair and then transmitting the data to a global data line pair in response to a first and a second control signals; and a sense amplifier configured to amplify the voltages of the data from the global data line pair and then transmitting the data to an input/output line pair during a read operation; wherein the local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.