Patent ID: 8400383
Filing Date: 2013-03-19
Classification: G02F,G09G

Abstract:
1. A liquid crystal display comprising: a first and a second data lines that are arranged in a column direction to receive a data voltage; a first pixel electrode that is positioned on the left side of the first data line on a first line; a second pixel electrode that is positioned on the right side of the first data line on the first line; a first gate line that is arranged between the first line and a second line underlying the first line in a line direction perpendicular to the column direction; a second gate line that is arranged between the first line and the second line in the line direction, the second gate line underlying the first gate line; a first thin film transistor that is positioned on the left side of the first data line on the first line to supply a first data voltage received from the first data line to the first pixel electrode in response to a first gate pulse received from the first gate line; a second thin film transistor that is positioned on the right side of the first data line on the first line, crosses over the first gate line to be connected to the second pixel electrode, and supplies a second data voltage received from the first data line to the second pixel electrode in response to a second gate pulse received from the second gate line; a third gate line that is arranged between the second line and a third line underlying the second line in the line direction; a fourth gate line that is arranged between the second line and the third line in the line direction, the fourth gate line underlying the third gate line; a third pixel electrode that is positioned on the left side of the first data line on the second line; a fourth pixel electrode that is positioned on the right side of the first data line on the second line; a third thin film transistor that is positioned on the left side of the first data line on the second line, crosses over the third gate line to be connected to the third pixel electrode, and supplies a fourth data voltage received from the first data line to the third pixel electrode in response to a fourth gate pulse received from the fourth gate line; and a fourth thin film transistor that is positioned on the right side of the first data line on the second line to supply a third data voltage received from the first data line to the fourth pixel electrode in response to a third gate pulse received from the third gate line, wherein the first to fourth gate pulses are sequentially supplied to the first to fourth gate lines, respectively, wherein the first, second, third and fourth data voltages are sequentially supplied to the first, second, fourth and third pixel electrodes, respectively, and wherein different data voltages having a same polarity are respectively applied to the first and second data lines during 1 horizontal period, and polarities of the data voltages being inverted every 1 horizontal period.