Patent ID: 6405355
Filing Date: 2002-06-11
Classification: G01R

Abstract:
In an electronic design automation system, a computer implemented method of constructing a scan chain, said method comprising the steps of:a) receiving a netlist description of an integrated circuit design having a plurality of functional pins; b) inserting scan cells to said netlist description, said scan cells being coupled serially together to form a scan chain; c) placing said scan cells to determine a cell layout, wherein said step (c) is performed without regard to any predetermined constraint designating a functional pin as a scan-in port and without regard to any predetermined constraint designating a functional pin as a scan-out port of said scan chain; d) based on said cell layout of said step (c), selecting a first functional pin of said plurality of functional pins to be a scan-in port of said scan chain; and e) modifying said netlist description to couple said first functional pin to a leading scan cell of said scan chain.