Patent ID: 9223915
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A computer implemented method for checking, verifying, or testing a multi-fabric electronic design in a multi-fabric electronic design environment, comprising: using at least one processor to perform a process the process comprising: receiving a request for checking correctness of a multi-fabric electronic design across at least a first design fabric and a second design fabric; automatically transmitting a request for action related to the request from a first session of a first EDA tool to a second session of a second EDA tool; identifying second connectivity information for second design data in the second design fabric by using the second session of a second EDA tool in response to the request for action; and checking the correctness of the multi-fabric electronic design in the first design fabric with the first session of a first electronic design automation (EDA) tool by using at least the second connectivity information.