Patent ID: 9136255
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A package stack structure comprising: a first package including a first, semiconductor chip, a first package substrate, and a first molding compound, the first semiconductor chip disposed on the first package substrate, wherein sides of the first semiconductor chip are surrounded by the first molding compound, and a top surface of the first semiconductor chip is exposed; a second package including a second semiconductor chip, a second package substrate, and a second molding compound, the second semiconductor chip disposed on the second package substrate and disposed in the second molding compound; a plurality of via plugs disposed in the first molding compound for electrically connecting the first package and the second package; a first interposing element disposed between the top surface of the first semiconductor chip and a bottom surface of the second package substrate; and a second interposing element positioned between the first package and the second package to form an air space, the air space providing an air path to outer areas of the package stack structure, wherein the first interposing element, occupies an area smaller than the top surface of the first semiconductor chip.