Patent ID: 6828633
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A semiconductor device, comprising:a first gate structure and a second gate structure formed on a silicon-on-insulator substrate; a source region disposed between a side of the first gate structure and a side of the second gate structure; a first drain region formed on another side of the first gate structure, corresponding to the source region, wherein the first gate structure, the source region, and the first dram region form a first transistor; a second drain region formed on another side of the second gate structure, corresponding to the source region, wherein the second gate structure, the source region and the second drain region form a second transistor; a doped region formed in the silicon-on-insulator substrate, wherein the doped region connects with a substrate portion underneath the first gate structure but is isolated from a substrate portion underneath the second gate structure; and a conductive line, connected with the doped region and the second drain region, wherein the substrate portion underneath the first gate structure is floating when the second transistor is turned off, and the substrate portion underneath the first gate structure is tied to the source region when the second transistor is turned on.