Patent ID: 7689897
Filing Date: 2010-03-30
Classification: G01R

Abstract:
1. A method for testing an integrated circuit, the method comprises: providing a first high frequency clock signal by a first high frequency clock source of the integrated circuit; receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information; generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information, wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit; providing the first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; and generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information, wherein the first low frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit.