Patent ID: 6209119
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A module synthesizing apparatus for synthesizing a layout module for a data path circuit, comprising:a logic-level processing unit for specifying cells in said data path circuit based on logic circuit data representing said data path circuit on a logic level;a cell-property estimating unit for obtaining a geometrical function parameterized by delay for a cell provided with a circuit configuration on a transistor level; anda synthesis processing unit for setting circuit configurations on the transistor level for the respective cells specified by said logic-level processing unit, supplying the set circuit configurations on the transistor level to said cell-property estimating unit, and then synthesizing a layout module based on geometrical functions of the respective cells to minimize a dead area between the cells, which have been parameterized by delays and have been obtained by said cell-property estimating unit.