Patent ID: 7742427
Filing Date: 2010-06-22
Classification: H04L

Abstract:
1. An internal loop-back architecture for a parallel serializer/deserializer (SERDES), comprising: a transmitter macro including a plurality of transmit elements arranged in a parallel architecture; and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit elements includes a loop-back arrangement with each of the plurality of receive elements, and wherein the plurality of transmit elements are individually addressable in a row and column arrangement; and the plurality of receive elements are individually addressable in a row and column arrangement, wherein adjoining transmit elements in a row are coupled together to access the communication channel and wherein adjoining receive elements in a row are coupled together to access the communication channel.