Patent ID: 8291305
Filing Date: 2012-10-16
Classification: G06F,H03M

Abstract:
1. A method, comprising: providing a cache; providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, wherein both the parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines, and wherein the first portion of the tag entry and the second portion of the tag entry are mutually exclusive portions of the tag entry; providing a read access to the cache; and in response to the read access resulting in a hit of the first one of the plurality of cache lines, providing the first portion of the tag entry and the one or more parity bits to parity logic which detects occurrence of a single-bit parity error in the first portion of the tag entry and providing the second portion of the tag entry and the EDC field to EDC logic which detects occurrence of a multiple-bit error in the second tag portion.