Patent ID: 6630855
Filing Date: 2003-10-07
Classification: G06F

Abstract:
A phase alignment method on a same integrated circuit (IC) die, comprising:providing a first clock distribution spine to receive a clock signal from a clock signal generator; providing at least one additional clock distribution spine on the same IC die; and providing a PLL (Phase Locked Loop) for each of the at least one additional clock distribution spines, each PLL having an REF (Reference) input and an FBK (Feedback) input, and an output; wherein the REF input of each PLL is directly connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective at least one additional clock distribution spine and the output of each PLL is connected to its respective at least one additional clock distribution spine to provide a clock signal thereto, each PLL providing phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted to its respective at least one additional clock distribution spine.