Patent ID: 6144239
Filing Date: 2000-11-07
Classification: G06F,G11C,H03L

Abstract:
A phase control circuit comprising a semiconductor integrated circuit and a control unit,wherein said semiconductor integrated circuit comprises:a register for storing a designated value;a delay element group for delaying an input signal by a delay quantity set based on said designated value to output said input signal delayed by said delay quantity as a delay signal;a PLL circuit for inputting said delay signal and a clock signal and for outputting a phase adjustment signal; anda first latch circuit for latching a write data, which is written in another circuit, in response to a latch signal, said other circuit being supplied with said clock signal,a second latch circuit for latching a read data, which is read from said other circuit, in response to said latch signal,wherein said phase adjustment signal is supplied to said delay element group as said input signal and is supplied to said latch circuits as said latch signal,wherein said control unit sequentially supplies predetermined values to said register as said designated value and judges whether said write data is coincident with said read data, each time said predetermined value is supplied to said register, said designated value being held in said register, when both of said read and write data are judged to be coincident with each other.