Patent ID: 7590146
Filing Date: 2009-09-15
Classification: G06F,H04J,H04L

Abstract:
1. An information processing unit in which in case a data signal is asynchronously transmitted from a transmission source to a transmission destination which is different in a protocol, a data transmission signal is transmitted from the transmission source to the transmission destination beforehand and a data transmission completion signal is transmitted from the transmission destination to the transmission source after the transmission of the data signal is completed, comprising: a transmission source functional block, controlled by a clock of the transmission source for converting the data transmission signal issued by the transmission source to a protocol of the transmission destination; a first transmission source register, which is controlled by the clock of the transmission source and to which the data transmission signal output from the transmission source functional block is input; an input signal bus, provided on a boundary between the clock of the transmission source and a clock of the transmission destination for converting the data transmission signal from the clock of the transmission source to the clock of the transmission destination; a first transmission destination register, which is controlled by the clock of the transmission destination and to which the data transmission signal that passes the input signal bus is input; a second transmission destination register, which is controlled by the clock of the transmission destination and to which the data transmission completion signal issued by the transmission destination is input; a transmission destination functional block, controlled by the clock of the transmission destination for converting the data transmission completion signal output from the second transmission destination register to the protocol of the transmission source; a third transmission destination register, which is controlled by the clock of the transmission destination and to which the data transmission completion signal output from the transmission destination functional block is input; an output signal bus, provided on the boundary between the clock of the transmission destination and the clock of the transmission source for converting the data transmission completion signal from the clock of the transmission destination to the clock of the transmission source; a second transmission source register, which is controlled by the clock of the transmission source and to which the data transmission completion signal that passes the output signal bus is input; a third transmission source register, which is controlled by the dock of the transmission source and to which the data signal issued by the transmission source is input; an input data bus, provided on the boundary between the clock of the transmission source and the clock of the transmission destination for converting the data signal from the clock of the transmission source to the clock of the transmission destination; a fourth transmission destination register, which is controlled by the clock of the transmission destination and to which the data signal that passes the input data bus is input; a transmission source multiplexer controlled by a clock of the transmission source for selecting the data signal issued by the transmission source every transmission; a buffer controlled by the clock of the transmission source and having size equal to the maximum burst size of the transmission source for holding the data signal output from the transmission source multiplexer; a transmission destination multiplexer controlled by a clock of the transmission destination for selecting the data signal output from the buffer every transmission; and a transmission destination register which is controlled by the clock of the transmission destination and to which the data signal output from the transmission destination multiplexer is input.