Patent ID: 6108237
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A computer, comprising:a microprocessor;a timing unit, operatively coupled to the microprocessor;an I/O interface module, operatively coupled to the microprocessor;a random access memory operatively coupled to the microprocessor;a non-volatile memory array, including a bit line and a floating gate memory device, operatively coupled to the microprocessor; anda read-biasing and amplifying circuit, including:an input operatively coupled to the bit line,an output operatively coupled to the microprocessor,a quick-charging device, operatively coupled to the input and the output, that simultaneously raises the potentials of the bit line and the output, wherein the potential of the output then continues to be raised when the potential of the bit line is no longer raised,a resistive load, distinct from the quick-charging device, for a floating gate memory device being sensed, anda feedback circuit, operatively coupled to the input that prevents the potential of the bit line from exceeding a read-bias potential.