Patent ID: 6424002
Filing Date: 2002-07-23
Classification: G11C,H01L

Abstract:
A transistor array, comprising:a semiconductor substrate having a main surface and a plurality of transistors arranged in a matrix on the main surface of said semiconductor substrate, each of said plurality of transistors, comprising: first and second impurity regions to be source and drain regions formed on the main surface of said semiconductor substrate and having a channel region therebetween; first and second floating gate electrodes positioned apart from each other on said channel region; and one common control gate electrode extending on said first and second floating gate electrodes, first and second transistors of said plurality of transistors arranged adjacently in a row-direction using said source or drain region commonly, the control gate electrodes of said plurality of transistors arranged in the row-direction extending in a direction passing over both said source and drain regions to form a common word line, in each of said plurality of transistors, the coupling capacitance between said floating gate electrode and said control gate electrode being set larger than the coupling capacitance between said floating gate electrode and said semiconductor substrate, wherein the control gate electrodes and common word line are homogenous.