Patent ID: 8981422
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising the steps of: (a) forming a first gate electrode, a second gate electrode, and a third gate electrode extending in a first direction along a major surface of a semiconductor substrate, the first gate electrode and the second to electrode being aligned in the first direction and the first gate electrode and the third gate electrode being aligned in a second direction perpendicular to the first direction, over the semiconductor substrate via a gate insulating film; (b) forming source/drain regions on the major surface of the semiconductor substrate on both sides of the first, second, and third gate electrodes in the second direction, (c) forming a first sidewall on a side wall of the first gate electrode, a second sidewall on a side wall of the second gate electrode, and a third sidewall on a side wall of the third gate electrode, (d) after the step (b) and step (c), sequentially forming a first insulating film and a second insulating film over the semiconductor substrate from the semiconductor substrate to cover the first, second, and third gate electrodes, the source/drain region, and the first, second, and third sidewalls, (e) between the first gate electrode and the third gate electrode in the second direction of a planar view, forming a first through-hole penetrating the first insulating film and the second insulating film and subsequently forming a contact plug inside the first through-hole, wherein the first direction is a gate width direction, wherein the second direction is a gate length direction, wherein the first gate electrode is disposed adjacent the second gate electrode in the first direction, wherein the first gate electrode is disposed adjacent the third gate electrode in the second direction, wherein the first insulating film is an insulating film including a silicon nitride film, and serves as an etching stopper film in forming the first through-hole, and wherein a first lowest position of the upper surface of the first insulating film disposed in a first region between the first gate electrode and the second gate electrode in the first direction of a planar view is higher than a second lowest position of the upper surface of the first insulating film disposed in a second region between the first gate electrode and the third gate electrode in the second direction of a planar view.