Patent ID: 6164840
Filing Date: 2000-12-26
Classification: G06F

Abstract:
A processor-implemented method for ensuring cache-consistency of data contained in an instruction cache of a processor wherein said instruction cache receives from a main memory by means of an external cache, data for processing by said processor and wherein a write cache stores data from the processor, by means of the external cache, to the main memory said method comprising:invalidating in the instruction cache any data of a first memory address of the main memory which is present in the instruction cache each time a store to the same first memory address is allocated to the write cache;storing in the external cache and then invalidating in the write cache any data of a second memory address of the main memory which is present in the write cache each time a fetch from the same second memory address is sent to the instruction cache; andexecuting a flush instruction at least in a case where the instruction cache includes a store to a third memory address of the main memory and then an execution of another instruction of the same third memory address, the flush instruction being executed between the store and the execution of the other instruction, and preventing fetching from the instruction cache of any instructions subsequent to the flush instruction at least until the store to the third memory address has been allocated to the write cache.