Patent ID: 6281067
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A self-aligned silicide process for forming a silicide layer over word lines in a memory cell region of a substrate and a silicide layer over transistors in a logic circuit region of the substrate, comprising the steps of:forming a first transistor and a second transistor in the substrate, wherein the first transistor is formed inside the logic circuit region and includes a first gate conductive layer and a first source/drain region, and wherein the second transistor is formed inside the memory cell region and includes a second gate conductive layer and a second source/drain region;forming a silicon nitride blocking layer over the first transistor, the second transistor and the substrate;removing a portion of the blocking layer to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer such that the second source/drain region is still covered by the remaining blocking layer; andforming a metal silicide layer over the first gate conductive layer, the first source/drain region and the second gate conductive layer.