Patent ID: 6532168
Filing Date: 2003-03-11
Classification: G11C

Abstract:
A magneto-resistive memory comprising:a latch circuit including a first inverter and a second inverter coupled together in a cross-coupled configuration, each of the first and second inverters having a positive supply terminal, a negative supply terminal, an input terminal and an output terminal, the positive supply terminal of the first and second inverters coupled to a power supply voltage; the latch circuit further including a load transistor for loading a state into the latch circuit, the load transistor having a source terminal coupled to the input terminal of the first inverter, a drain terminal coupled to the input terminal of the second inverter, and a gate terminal; at least one magneto-resistive memory cell having a first magneto-resistive bit with a first end and a second end, and a second magneto-resistive bit having a first end and a second end, the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit being selectively coupled to ground through one or more switching means; a first word line coupled to the negative supply terminal of the first inverter and extending adjacent the first magneto-resistive bit of at least one magneto-resistive memory cell, each of the first magneto-resistive bits having a first end coupled to the first word line; a second word line coupled to the negative supply terminal of the second inverter and extending adjacent the second magneto-resistive bit of at least one magneto-resistive memory cell, each of the second magneto-resistive bits having a first end coupled to the second word line; and a write transistor having a source terminal coupled to the first word line, a drain coupled to the second word line, and a gate coupled to a write control terminal, the write transistor for selectively connecting the first word line and the second word line depending on the state of the write control terminal.