Patent ID: 6769082
Filing Date: 2004-07-27
Classification: G01R,H03K

Abstract:
A semiconductor testing device that tests a semiconductor device, comprising:a pattern generator that generates a test pattern to be fed into said semiconductor device; a delay unit that generates a delay clock having a delay amount corresponding to an operation characteristic of said semiconductor device; a shaped test pattern generator that generates a shaped test pattern by shaping said test pattern based upon said delay clock; a device insertion unit used for mounting said semiconductor device thereon and inputting said shaped test pattern to said semiconductor device; and a comparator that judges whether said semiconductor device is good or not based upon said output signal output by said semiconductor device in response to said shaped test pattern, wherein said delay unit includes a delay element that operates on two power supply voltages Vss and Vdd and that delays an input clock by said delay amount to generate said delay clock, said voltage Vss being smaller than said voltage Vdd, and an addition circuit that outputs a predetermined voltage that is larger than said voltage Vss and smaller than said voltage Vdd in response to said output of said delay element, wherein said addition circuit has an input terminal and an output terminal connecting with said input terminal.