Patent ID: 7948020
Filing Date: 2011-05-24
Classification: G11C,H01L

Abstract:
1. A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) comprising: a substrate; and an asymmetric non-volatile memory (NVM) cell including: a source region and a drain region diffused into the substrate and separated by a channel region; and an integral polycrystalline silicon (polysilicon) floating gate including an elongated first portion disposed over the channel region, and an elongated second portion disposed over a central area of the drain region, the elongated second region being spaced from the elongated first region, wherein the polysilicon floating gate, source region and drain region are formed such that a gate-drain capacitance between said polysilicon floating gate and said drain region is substantially higher than a gate-source capacitance between said polysilicon floating gate and said source region, and wherein the CMOS IC further includes means for programming the polysilicon floating gate by transferring a positive programming potential from the drain region to the polysilicon floating gate, and for erasing the polysilicon floating gate by transferring a potential lower than 0.5V from the drain region to the polysilicon floating gate.