Patent ID: 6502196
Filing Date: 2002-12-31
Classification: G06F,Y02D

Abstract:
A voltage converter for implementing a suspension-to-RAM (STR) mode of power management in a computer system, comprising:a flip-flop; a resume and initialization logic circuit for producing a resume signal, connected to a first input terminal of the flip-flop; a suspension-to-RAM (STR) logic circuit for producing a STR signal, an output terminal of the STR logic circuit being connected to a second input terminal of the flip-flop; a first voltage-conversion unit connected to an output terminal of the flip-flop so that when the resume signal is at a low level while the STR signal is at a high level, a suspension voltage is applied to a system memory of the computer; and a second voltage-conversion unit connected to a complementary output terminal of the flip-flop so that when the resume signal is at a high level while the STR signal is at a low level, a source voltage is applied to the system memory of the computer.