Patent ID: 6529053
Filing Date: 2003-03-04
Classification: G06F

Abstract:
A reset circuit adapted to reset a plurality of circuit modules, the circuit modules being adapted to enable internal resets in response to a reset signal, the reset circuit comprising:a reset module adapted to generate the reset signal; a clock module having an external clock reference and at least one clock module output for each of the plurality of circuit modules, the clock module being adapted to provide a reset clock signal to each of the circuit modules via the clock module outputs in response to the generated reset signal, the reset clock signal having the frequency of the external clock reference; and a plurality of synchronization modules, each coupled to one of the plurality of circuit modules and having a reset input port coupled to the reset module and a clock input port coupled to one of the clock module outputs and being adapted to use the reset signal and the reset clock signal to provide an internal reset signal at the circuit module to which it is coupled, each of the internal reset signals being synchronized via the reset clock signal.