Patent ID: 6560275
Filing Date: 2003-05-06
Classification: H04J

Abstract:
An interconnection interface for transmitting digital data, said interface defining a physical interface between a sending module and a receiving module that send and receive data, said sending module and said receiving module connected to one another by a plurality of point-to-point serial links forming a global data link, said interconnection interface comprising in each of said modules:multiplexing means associated with each of said plurality of serial links, said multiplexing means disposed in a physical layer of each of said modules, said multiplexing means distributing said data being transmitted through said global link at a speed determined by said sending module to at least one parallel link, each of said at least one parallel link conveying a part of the data being transmitted at a speed higher than a speed of data blocks sent by said sending module, said multiplexing means including: a sending block comprised of a plurality of clock signal generating blocks, each clock signal generating block using sending logic for a link to which the clock signal generating block is connected, said sending block synchronizing the plurality of clock signal generating blocks; means for demultiplexing the at least one parallel link respectively conveying data parts received, and for reconstituting the data parts received, synchronously and with integrity, at a speed corresponding to a speed allowable by said receiving module, said means for demultiplexing including: a receiving block comprised of a plurality of clock signal retrieving blocks, each of said clock signal retrieving blocks using receiving means for a link to which the clock signal retrieving block is connected, said receiving block defining a clock domain related to reception of links connected to a same module.