Patent ID: 6716660
Filing Date: 2004-04-06
Classification: G02F,H01L

Abstract:
A method for fabricating a thin film transistor array substrate, comprising the steps of:forming a gate line assembly on an insulating substrate with an Ag alloy, the Ag alloy comprising Ag and an alloy element bearing a low melting point, the gate line assembly comprising a gate electrode and a gate line; forming a gate insulating layer on the substrate such that the gate insulating layer covers the gate line assembly; forming a semiconductor layer on the gate insulating layer; forming a data line assembly on the semiconductor layer, the data line assembly comprising a source electrode, a drain electrode and a data line; forming a protective layer on the substrate such that the protective layer covers the data line assembly; forming a contact hole exposing the drain electrode at the protective layer; and forming a pixel electrode on the protective layer such that the pixel electrode is connected to the drain electrode through the contact hole.