Patent ID: 9172645
Filing Date: 2015-10-27
Classification: H04L

Abstract:
1. An apparatus, comprising: a processor configured to be operatively coupled to a memory and that is configured to execute a switch module; and the switch module configured to receive an order identifier of a first data packet from a first stage of a multi-stage switch; the switch module configured to receive an indicator of an available capacity of a first module of a second stage of the multi-stage switch, and an indicator of an available capacity of a second module of the second stage of the multi-stage switch; the switch module configured, when the order identifier is assigned, to direct the first data packet to the first module when the available capacity of the second module is higher than the available capacity of the first module; the switch module is configured, when the order identifier is flexible, to direct the first data packet to the first module when the available capacity of the first module is above a threshold.