Patent ID: 6658611
Filing Date: 2003-12-02
Classification: G01R,G11C

Abstract:
A built-in self-test (BIST) system for a semiconductor memory, comprising:a parameter register file having a plurality of externally programmable registers, for storing parameters to test the memory; a BIST machine for controlling read/write operations of the memory in response to the parameters stored in the parameter register file, sensing an occurrence of an error according to the read/write operations and producing error test results in the form of one or more signatures; a multi-input signature register (MISR) for compressing test results from the BIST machine; and a clock input circuit for receiving a first clock signal having a first frequency and for receiving a clock doubling selection signal, and for outputting a second clock signal to the BIST system and the memory so as to test the memory, wherein the second clock signal has the first frequency when the clock doubling selection signal has a first value, and the second clock signal has a second frequency as a double of the first frequency, when the clock doubling selection signal has a second value.