Patent ID: 6314099
Filing Date: 2001-11-06
Classification: H04L

Abstract:
An address match determining device comprising:storage means for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N-m) bits of the corresponding address code;extract means for receiving an N-bit address code included in a packet to be transmitted by way of a transmission line, and for extracting the high-order m bits and remaining low-order (N-m) bits from the address code received; andsearch and determination means for searching through said table stored in said storage means for one 1-bit address match determination data specified by the first index composed of the extracted high-order m bits and the second index composed of the extracted low-order (N-m) bits, and for determining whether the 1-bit address match determination data searched for indicates that the received address code is available.