Patent ID: 9171932
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A display panel comprising: a gate line disposed on a substrate and extending in a first direction; a gate electrode extending from the gate line; a planarization layer covering the gate line and the gate electrode and comprising an opening exposing a portion of the gate electrode, wherein the planarization layer has a first thickness over the gate electrode and a second thickness spaced apart from the gate electrode in a plan view, and wherein the first thickness is less than the second thickness, such that the planarization layer has a flat upper surface over a boundary of the gate electrode; a gate insulation layer covering the planarization layer and the portion of the gate electrode exposed by the opening in the planarization layer; an active layer disposed on the gate insulation layer and corresponding to the gate electrode; a data line disposed on the substrate and extending in a second direction; a source electrode extending from the data line and covering a portion of the opening; a drain electrode spaced apart from the source electrode and covering a portion of the opening; and a pixel electrode connected to the drain electrode.