Patent ID: 6137064
Filing Date: 2000-10-24
Classification: H01R,H05K

Abstract:
A circuit comprising:(a) a multi-layer structure;(b) a multi-connection via disposed in said multi-layer structure, said multi-connection via provided from a single hole having at least first and second separate electrically isolated segments within the hole with the first segment having a first predetermined width and the second segment having a second predetermined width; and(c) a circuit component having a plurality of surface mount contacts, with a first one of the plurality of surface mount contacts disposed on at least a portion of the first segment of said multi-connection via and a second one of the plurality of surface mount contacts disposed on at least a portion of the second segment of said multi-connection via and wherein the widths of each of the first and second segments of said multi-connection via are selected such that said multi-connection via provides a predetermined impedance characteristic to said circuit component.