Patent ID: 7062612
Filing Date: 2006-06-13
Classification: G06F

Abstract:
1. A computer system having one or more processors and a system memory, the computer system comprising: a first processor; a cache coupled to the first processor; a first bus controller; a system bus coupled to both the first bus controller and the system memory, the first bus controller sending a data transfer request for transferring data to the system memory via the system bus; a second bus controller coupled to both the cache and the system bus, the second bus controller both snooping the data transfer request and sending a snoop request to the cache; detector means for determining whether the snoop request has a valid entry in the cache; data transmission means for, upon determining that the snoop request has a valid entry in the cache, catching said data from the system bus as said data is being transferred to the system memory and directly sending said data to only the cache for update to maintain a valid entry for said data in the cache, thereby enabling the first processor to directly access said data from the valid entry in the cache; a second processor; and a direct memory access controller (DMAC) coupled to both the second processor and the first bus controller.