Patent ID: 7825471
Filing Date: 2010-11-02
Classification: G11C,Y10S

Abstract:
1. A semiconductor memory device comprising: a first well region of a first conductivity type; at least first and second SRAM cells adjacently arranged to each other, said first and second SRAM cells each including a first transfer transistor and a drive transistor formed on said first well region, said first transfer transistor and said drive transistor being coupled in series between a bit line and a power source line; a first diffusion region of said first conductivity type arranged between said drive transistor of said first SRAM cell and said drive transistor of said second SRAM cell to apply a first well potential to said first well region; wherein said first transfer transistor and said drive transistor of said first SRAM cell, said first transfer transistor and said drive transistor of said second SRAM cell, and said first diffusion region are arranged on a straight line; a second well region of a second conductivity type; and a second diffusion region of said second conductivity type to apply a second well potential to said second well region, wherein: said first SRAM cell includes a first load transistor formed on said second well region; said second SRAM cell includes a second load transistor formed on said second well region; and said second diffusion region is arranged between said first and second load transistors; a third well region of said first conductivity type arranged so that said second well region is placed between said first and third well regions; a third diffusion region of said first conductivity type to apply said first well potential to said third well region; a fourth diffusion region of said first conductivity type to apply said first well potential to said third well region, wherein: said first and second SRAM cells each further includes at least a second transfer transistor and a second drive transistor formed on said third well region, said second transfer transistor and said second drive transistor being coupled in series between a second bit line and said power source line; and said second transfer transistors and said second drive transistors of said first and second SRAM cells are arranged between said third and fourth diffusion regions.