Patent ID: 8056038
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. A method for measuring timing performance of an integrated circuit (IC) chip, said IC chip being represented by a hierarchical design, the method comprising: using a computer, performing an initial static timing run on at least one partition of said hierarchical design, each input of said at least one partition being assigned a unique phase tag; determining dependencies of timing values on at least one partition boundary condition; generating a checkpoint timing based on said determined dependencies of timing values, said checkpoint timing comprising at least one of arrival time (AT), required arrival time (RAT) and slew values, and incorporating said at least one of AT, RAT and slew values into a subsequent static timing analysis run; performing a local update of said at least one of AT, RAT, and slew values and dependencies thereof based on said new boundary condition values; and measuring said timing performance of said at least one partition of said hierarchical design based upon said locally updated at least one of AT, RAT and slew values.