Patent ID: 9171743
Filing Date: 2015-10-27
Classification: H01L

Abstract:
1. A method comprising: receiving a semiconductor layer including multiple transistors; fabricating at least one interconnect layer on the semiconductor layer to connect the multiple transistors in parallel with each other; fabricating a first conductive layer on the at least one interconnect layer, the at least one interconnect layer electrically coupling the multiple transistors to the first conductive layer, the first conductive layer being a material having a first resistivity; and electrically coupling a second conductive layer to the first conductive layer, the second conductive layer being a material having a second resistivity, the second resistivity being less than the first resistivity; partitioning the first conductive layer to include a source node region and a drain node region, the source node region of the first conductive layer and the drain node region of the first conductive layer being electrically isolated from each other, the source node region of the first conductive layer electrically coupled to source nodes of the multiple transistors via connectivity through the multiple interconnect layers, the drain node region of the first conductive layer electrically coupled to drain nodes of the multiple transistors via connectivity through the multiple interconnect layers; partitioning the second conductive layer to include a first region and a second region, the first region and the second region in the second conductive layer being electrically isolated from each other; electrically coupling the first region of the second conductive layer to the source node region of the first conductive layer; and electrically coupling the second region of the second conductive layer to the drain node region of the first conductive layer.