Patent ID: 6673683
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method for fabricating a field effect transistor device comprising:providing a semiconductor substrate having formed thereover a patterned dummy layer; forming within the semiconductor substrate a pair of source/drain regions while employing the patterned dummy layer as a mask; forming adjoining a pair of opposite sidewalls of the patterned dummy layer a pair of patterned sacrificial layers and stripping the patterned dummy layer from adjoining the pair of patterned sacrificial layers to provide an aperture defined by the pair of patterned sacrificial layers; forming adjoining a pair of sidewalls of the aperture a pair of spacer layers and forming at the bottom of the aperture a gate dielectric layer to leave remaining a partially filled aperture; forming upon the pair of patterned sacrificial layers, the pair of spacer layers and the gate dielectric layer a blanket gate electrode material layer which completely fills the aperture; planarizing the blanket gate electrode material layer, the pair of patterned sacrificial layers and the pair of spacer layers to form a gate electrode, the pair of planarized patterned sacrificial layers and the pair of planarized spacer layers having a pair of blunt tips; stripping the pair of planarized patterned sacrificial layers and the pair of planarized spacer layers from the gate electrode; and implanting, while employing the gate electrode as a mask, a pair of lightly doped extension regions into the semiconductor substrate.