Patent ID: 6285623
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A memory system according comprising:A. a memory chip;B. a plurality of banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each comprising:a. a plurality of memory-cell blocks; each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;b. at least one column decoder located at at least a first end of every column of memory cells and connected to said column-selecting lines;c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;e. a cell-array controller located at a second end of every row of memory cells, for controlling the reading and writing of the multi-bit data;C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;D. a data bus provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, on one hand, and said data input/output region, on the other;E. a CPU chip generating said clock signal; andF. an I/O bus connecting between said memory chip and said CPU chip.