Patent ID: 6631069
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A memory system, comprising:a controller; a command link coupled to the controller; a data link coupled to the controller; and a memory device coupled to the command link and the data link, wherein the memory device comprises: an array of memory cells, wherein at least one memory cell has a capacitor, the capacitor comprising: a bottom electrode; a top electrode; a dielectric layer interposed between the bottom electrode and the top electrode; and at least one metal oxynitride barrier layer, wherein each metal oxynitride barrier layer is interposed between the dielectric layer and an electrode selected from the group consisting of the bottom electrode and the top electrode; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.