Patent ID: 8389353
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A method of forming an array of memory cells individually comprising a field effect transistor and a charge storage device, comprising: forming a plurality of spaced lines over semiconductive material of a semiconductor substrate; forming anisotropically etched sidewall spacers on opposing sides of the spaced lines, individual of the lines having greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines; removing the spaced lines from between the spacers to form alternating first and second mask openings between the spacers, the first mask openings being located where the spaced lines were located and being wider than the second mask openings, the respective first openings having laterally innermost edges defined by laterally innermost edges of the spacers, the respective second openings having laterally innermost edges defined by laterally outermost edges of the spacers; using the first mask openings to etch inter-transistor trenches into the semiconductive material and using the second mask openings to etch intra-transistor trenches into the semiconductive material, the inter-transistor trenches being etched wider and deeper within the semiconductive material than are the intra-transistor trenches; the inter-transistor trenches and the intra-transistor trenches being etched into the semiconductive material simultaneously; providing a pair of source/drain regions within the semiconductive material on opposing sides of individual of the intra-transistor trenches between immediately adjacent of the inter-transistor trenches; providing a channel region within the semiconductive material elevationally inward of the pair of source/drain regions between immediately adjacent of the inter-transistor trenches; and forming a plurality of wordlines, a plurality of bit lines, and a plurality of charge storage devices; individual of the charge storage devices being in electrical contact with one of the pair of source/drain regions of an individual transistor; one of the bit lines being in electrical contact with the other of the pair of source/drain regions of the individual transistor; one of the wordlines being received operably proximate the channel region of the individual transistor.