Patent ID: 6184076
Filing Date: 2001-02-06
Classification: H01L,Y10S

Abstract:
A method for forming a DRAM integrated circuit having cylindrical capacitors in a cell array and having peripheral devices, comprising:(a) providing a silicon wafer having a self-aligned-polysilicon gate MOSFETs formed on its surface, said MOSFETs being configured to form DRAM cell devices in an array and peripheral devices;(b) forming a first insulative layer over said silicon wafer;(c) patterning and etching bitline contact openings in said first insulative layer;(d) depositing and patterning a first polysilicon layer over said silicon wafer and into said bitline contact openings to form bitlines;(e) depositing a second insulative layer over said silicon wafer;(f) depositing an etch-stop layer over said second insulative layer;(g) patterning and etching openings for the lower sections of said cylindrical capacitors in said etch-stop layer, said second insulative layer and said first insulative layer;(h) depositing a third insulative layer over said silicon wafer;(i) depositing and patterning a first photoresist layer to define the upper sections of said cylindrical capacitors;(j) etching said third insulative layer whereupon said etch-stop layer halts etching everywhere except in said openings which are etched to expose subjacent active areas of said cell devices;(k) removing said first photoresist layer;(l) depositing a first doped polysilicon layer over said silicon wafer;(m) depositing a fourth insulative layer over said first doped polysilicon layer;(n) planarizing said fourth insulative layer;(o) etching said fourth insulative layer until the uppermost portions of said first doped polysilicon layer are exposed;(p) etching said first doped polysilicon layer, removing only the exposed uppermost portions thereof, said uppermost portions being co-planar with said silicon wafer thereby forming a lower storage plates of said cylindrical capacitors;(q) etching said fourth insulative layer with an isotropic wet etching technique;(r) depositing a second photoresist layer over said silicon wafer;(s) patterning a second photoresist layer to cover said cell devices thereby exposing said etch-stop layer over said peripheral devices;(t) etching said etch-stop layer over said peripheral devices;(u) Removing said second photoresist layer;(v) depositing a capacitor dielectric layer over said silicon wafer;(w) depositing a second doped polysilicon layer over said capacitor dielectric layer;(x) patterning said second doped polysilicon layer thereby forming upper cell plates;(y) depositing a fifth insulative layer over said silicon wafer;(z) patterning and etching contact openings in said fifth insulative layer;(aa) depositing a barrier layer over said silicon wafer;(ab) forming contact metallization in said contact openings;(ac) depositing and patterning a first layer of wiring metallization over said silicon wafer; and(ad) forming additional wiring layers separated by insulative layers and interconnected with vias to complete said DRAM integrated circuit.