Patent ID: 6658609
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells, each arranged at an intersection between one of a plurality of word lines and one of a plurality of bit lines, wherein the plurality of word lines form a plurality of word line groups; a plurality of driver circuits, each connected to one of the plurality of word line groups; a first decoder circuit connected to the plurality of driver circuits to selectively at activate the driver circuits; a second decoder circuit connected to the plurality of driver circuits to select predetermined ones of the word lines in each of the plurality of word line groups, wherein the first decoder circuit substantially simultaneously activates the plurality of driver circuits in response to a test mode signal and the second decoder circuit selects the predetermined word lines in a predetermined pattern in response to the test mode signal; a test mode circuit connected to the first and second decoder circuits to send the test mode signal to the first and second decoder circuits; an oscillator circuit connected to the test mode circuit to generate an oscillation signal having a predetermined cycle in response to the test mode signal; and a pattern generating circuit connected to the oscillator circuit and the second decoder to send a word line selection signal having the predetermined pattern to the second decoder circuit in accordance with the oscillation signal.