Patent ID: 7675800
Filing Date: 2010-03-09
Classification: G11C

Abstract:
1. A semiconductor memory which comprises a plurality of banks each having dynamic memory cells and operating independently, and operates in response to an access request, the semiconductor memory comprising: a main refresh address counter changing a main block address when the main block address coincides with an access block address corresponding to the access request, and sequentially generating a main row address and the main block address in synchronization with a main count signal; a sub refresh address counter set valid when the main block address coincides with the access block address, receiving, as a sub block address and a sub row address, the main block address and the main row address transferred from the main refresh address counter, sequentially generating the sub row address in synchronization with a sub count signal, and set invalid after outputting a final sub row address; an address selection circuit selecting addresses not coinciding with the access block address, out of the main block address and the main row address, and the sub block address and the sub row address, and outputting the selected addresses; a counter control circuit outputting, in response to a refresh request, one of the main count signal and the sub count signal corresponding to the addresses output by the address selection circuit; a refresh counter control circuit controlling operations of the main refresh address counter, the sub refresh address counter, the address selection circuit, and the counter control circuit, and making the sub refresh address counter operate with priority over the main refresh address counter during a period in which the sub refresh address counter is valid; and an operation control circuit executing an access operation of one of the banks in response to the access request and executing a refresh operation of one of the banks in response to the refresh request.