Patent ID: 7943441
Filing Date: 2011-05-17
Classification: H01L

Abstract:
1. A method for forming a thin-film transistor array substrate, comprising: providing a substrate comprising a light-shielding layer, a semiconductor layer, and a first metallic layer sequentially stacked thereon; patterning the first metallic layer, the semiconductor layer and the light-shielding layer to form a source, a drain, and a channel disposed between the source and the drain; forming a dielectric layer covering the substrate, the source, the drain, and the channel; forming a patterned photoresist on the dielectric layer; removing the dielectric layer not covered by the patterned photoresist to partially expose a surface of the drain; forming a transparent conductive layer covering the patterned photoresist, the partially-exposed surface of the drain, and the substrate; removing the patterned photoresist and a portion of the transparent conductive layer covering the patterned photoresist altogether; and forming a gate on the dielectric layer subsequent to removing the patterned photoresist and the portion of the transparent conductive layer covering the patterned photoresist altogether, wherein the gate is disposed between the source and the drain, and corresponding to the channel.