Patent ID: 6265313
Filing Date: 2001-07-24
Classification: H01L,Y10S

Abstract:
A method of manufacturing a copper interconnect, comprising the steps of:providing a semiconductor substrate having a dielectric layer thereon, wherein the dielectric layer further comprises a copper layer embedded within the dielectric layer;forming a first inter-metal dielectric layer over the dielectric layer;forming a patterned mask layer over the first inter-metal dielectric layer;forming a second inter-metal dielectric layer over the patterned mask layer;patterning the second inter-metal dielectric layer to form at least a trench;etching the first inter-metal dielectric layer to form a via opening exposing the copper layer, wherein the exposed copper immediately oxidizes into a copper oxide layer on the copper layer while being exposed;forming a barrier layer along surfaces of the trench and the via opening;removing the barrier layer and the copper oxide layer on the copper layer surface by using radio frequency argon/hydrogen; andforming a conductive layer to fill the trench and the via opening.