Patent ID: 7473599
Filing Date: 2009-01-06
Classification: G11C,H01L

Abstract:
1. A method for manufacturing a memory unit capable of storing single-bit or multi-bits information, said method comprising the steps of: providing a substrate with a gate dielectric and a gate structure formed thereon, wherein said gate structure acts as a control gate and a select gate; performing an optional pocket ion implantation by using said gate structure as a mask to form pocket doped regions nearby said gate edge in said substrate; forming a first oxide layer over said gate structure; forming a charge-trapping layer over said first oxide layer, and subsequently forming a second oxide layer over said charge-trapping layer; performing an etching to etch said second oxide layer, said charge-trapping layer and said first oxide layer to form sandwich spacers comprised of said second oxide layer/ said charge-trapping layer/ said first oxide layer on the sidewall of said gate structure; performing an ion implantation by using said gate structure and said sandwich spacers as a mask to form source/drain doped regions in said substrate, wherein junctions of said substrate to said source/drain doped regions locate right under said sandwich spacers.