Patent ID: 8056033
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. An integrated circuit design apparatus, comprising: a power supply voltage variation analysis tool, as executed by a processor on said apparatus, calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module, executed by the processor, comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level; a redesign module, executed by the processor, adapted to redesign said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level; a delay variation calculation module, executed by the processor, adapted to correct circuit delay data of said respective instances based on said variations of said power supply voltages of said respective instances; and a static timing analysis tool, executed by the processor, performing a timing verification of said target integrated circuit, wherein, in said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level.