Patent ID: 7795079
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure, comprising: providing a conductive layer having a plurality of recesses and a first patterned solder resist layer on the conductive layer, wherein the first patterned solder resist layer and the recesses are at two opposite sides of the conductive layer; removing a part of the conductive layer exposed by the first patterned solder resist layer forming a patterned conductive layer; bonding a plurality of chips onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the conductive layer; electrically connecting the chips to the conductive layer by a plurality of bonding wires; forming at least one molding compound to encapsulate the conductive layer, the first patterned solder resist layer, the chips and the bonding wires; and separating the molding compound and the patterned conductive layer.