Patent ID: 7430099
Filing Date: 2008-09-30
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit for protecting an internal circuit of a semiconductor, the ESD protection circuit being installed between an input/output pad and an input buffer including a first NMOS transistor, the ESD protection circuit comprising: a first electrostatic protection unit connected to a power source supply pad, wherein the first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit; a driver driven by the first driving voltage, wherein the driver generates a second driving voltage by an ESD current; and a second electrostatic protection unit driven by the second driving voltage for discharging the introduced ESD current into the power source supply such that a voltage applied to a gate of the first NMOS transistor is reduced; wherein the power source supply pad includes a power source voltage supply pad and a ground voltage supply pad, wherein the second electrostatic protection unit includes a second NMOS transistor having a drain connected to the gate of the first NMOS transistor and the input/output pad, a source connected to the ground voltage supply pad, a substrate connected to the source, and a gate connected to the driver, and wherein the driver comprises: