Patent ID: 7700435
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. A method for fabricating a deep trench DRAM array, the method comprising the steps of: providing a semiconductor substrate having thereon a memory array region; and forming a plurality of trench capacitor patterns within the memory array region of the semiconductor substrate, the plurality of trench capacitor patterns comprising first dummy trench capacitor patterns disposed in a first column, second dummy trench capacitor patterns disposed in a first row, and a plurality of effective trench capacitor patterns, wherein each of the first dummy trench capacitor patterns in the first column has an extended width along a first direction, and each of the second dummy trench patterns has an extended length along a second direction independent from the first direction, each of the plurality of effective trench capacitor patterns has an effective width and an effective length with regard to the extended width and the extended length.