Patent ID: 8049483
Filing Date: 2011-11-01
Classification: G05F

Abstract:
1. A reference voltage generation circuit comprising: a first depletion mode field effect transistor (FET) having a source, a drain, and a gate, with the gate connected to an enable terminal, and the drain connected to a power supply terminal; a second depletion mode FET having a source, a drain, and a gate, with the drain connected to the source of the first depletion mode FET; a first resistor having a first end connected to the source of the second depletion mode FET, and a second end connected to the gate of the second depletion mode FET; a first bipolar transistor having an emitter, a base, and a collector, with the collector connected to the second end of the first resistor; a second resistor having a first end connected to the emitter of the first bipolar transistor, and a second end that is grounded; a second bipolar transistor having an emitter, a base, and a collector, with the collector connected to the source of the first depletion mode FET, and the base connected to the source of the second depletion mode FET; a third bipolar transistor having an emitter, a base, and a collector, with the base and collector connected to the base of the first bipolar transistor and to the emitter of the second bipolar transistor; a third resistor having a first end connected to the emitter of the third bipolar transistor, and a second end that is grounded; a third depletion mode FET having a source, a drain, and a gate, with the drain connected to the second end of the first resistor and to the collector of the first bipolar transistor; and a fourth bipolar transistor having an emitter, a base, and a collector, with the base and collector connected to the gate and the source of the third depletion mode FET, and the emitter grounded, wherein source voltage of the second depletion mode FET is output as a reference voltage.