Patent ID: 7596773
Filing Date: 2009-09-29
Classification: G06F

Abstract:
1. A method of placing a set of macros in an area representing a die of an integrated circuit, said method being performed in a digital processing system, said method comprising: receiving a set of present placements, wherein each of said set of present placements indicates a corresponding present location where each of said set of macros is placed in said area; computing a set of present measures wherein each of said set of present measures represents an optimalness of corresponding placement; forming a set of new placements, wherein each of said set of new placements is formed from a corresponding plurality of present placements, wherein said corresponding plurality of present placements are comprised in said set of present placements, wherein a first new placement contained in said set of new placements is formed from a first present placement and a second present placement, wherein a first subset of macros in said first new placement are placed in identical locations as specified by said first present placement and a second subset of macros are placed in identical locations as specified by said second present placement, wherein said first subset of macros and said second subset of macros are contained in said set of macros; locating a fifth placement in one of said set of present placements, said fifth placement having a plurality of overlapping macros which overlap, wherein said plurality of overlapping macros are contained in said plurality of macros, determining a new location for at least one of said plurality of overlapping macros; and shifting said one of said plurality of overlapping macros to said new location, wherein said locating, determining and said shifting are performed computationally without requiring human intervention; wherein said determining comprises: