Patent ID: 7554133
Filing Date: 2009-06-30
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a monolithic semiconducting substrate formed in a chip, the chip having a peripheral edge, a backside, and an opposing top on which circuitry is formed, a first ring of bonding pads formed along at least a portion of the peripheral edge, at least one of the bonding pads configured as a power pad and at least one of the bonding pads configured as a ground pad, an intermediate power bus disposed interior to the first ring of bonding pads on the chip, the intermediate power bus forming no direct electrical connections to any core devices, an intermediate ground bus disposed interior to the first ring of bonding pads on the chip, the intermediate ground bus forming no direct electrical connections to any core devices, a power pad wire forming an exclusive electrical connection to the power pad at a first end of the power pad wire, and forming an electrical connection to the intermediate power bus at a second end of the power pad wire, a ground pad wire forming an exclusive electrical connection to the ground pad at a first end of the ground pad wire, and forming an electrical connection to the intermediate ground bus at a second end of the ground pad wire, a power strap forming an electrical connection to the intermediate power bus at a first end of the power strap, and forming an electrical connection to a power mesh at a second end of the power strap, and a ground strap forming an electrical connection to the intermediate ground bus at a first end of the ground strap, and forming an electrical connection to a ground mesh at a second end of the ground strap.