Patent ID: 7088136
Filing Date: 2006-08-08
Classification: H03K

Abstract:
1. A programmable logic region on a programmable logic device, comprising: combinational logic that provides an output data value on a combinational logic output line; a logic region output line through which data from the logic region is routed to logic on the programmable logic device; and a zero-delay latch circuit connected between the combinational logic output line and the logic region output line that is selectively configured to serve as either a level-sensitive latch having an output that tracks the output data value when enabled or a zero-delay path that does not delay the output data value traveling from the combinational logic output line to the logic region output line, wherein the zero-delay latch circuit comprises a tri-state output driver having an input connected to the combinational logic output line and having an output connected to the logic region output line.