Patent ID: 6574230
Filing Date: 2003-06-03
Classification: H04L

Abstract:
A scheduling apparatus capable of being coupled to a plurality of memory buffers, each buffer capable of inputting data packet units and outputting data packets corresponding to a respective single data stream, the scheduling apparatus comprising scheduling logic operable to:upon input of a first data packet unit to a first memory buffer of said plurality of memory buffers, determine whether a first outputting parameter corresponding to a front packet within the first memory buffer is met; and if the first outputting parameter is met, output the front packet from the first memory buffer; wherein the scheduling logic further operates to select a round-robin (RR) memory buffer during each inputting of a data packet unit, each memory buffer cyclically being selected as the RR memory buffer; and wherein the scheduling logic further operates, if the first outputting parameter is not met, to determine whether an RR outputting parameter corresponding to a front packet within the RR memory buffer is met and to output the front packet from the RR memory buffer if the RR outputting parameter is met.