Patent ID: 8643122
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a source region and a drain region of the semiconductor device grown on the substrate; a gate disposed on the substrate between the source region and the drain region; an interlayer dielectric disposed on the source region and the drain region, and disposed on and adjacent to the gate; openings inside the interlayer dielectric to the source region, and to the drain region; one or more shaped surface areas on the source region and the drain region, wherein the one or more shaped surface areas are hexagonal-like surface areas, pentagonal-like surface areas, or brimmed surface areas; a contact layer disposed on and adjacent to the interlayer dielectric, and the one or more shaped surface areas, wherein the contact layer provides a contact conformal to the one or more shaped surface areas, and wherein the contact layer is a silicide that comprises nickel silicide, cobalt di-silicide, or erbium di-silicide; a metal layer disposed on and adjacent to the contact layer; a planarized surface, wherein a portion of the contact layer and a portion of the metal layer are removed selective to the interlayer dielectric; and a capping layer disposed on the planarized surface.