Patent ID: 6218291
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method for forming a contact plug in an integrated circuit, comprising:forming a conductive structure on a semiconductor substrate having a plurality of diffusion regions therein;forming a first insulating layer over the semiconductor substrate including the conductive structure, the first insulating layer having a higher step at a first region where the conductive structure is formed in a group than at a second region where the conductive structure is not found;after forming the first insulating layer, etching the first insulating layer using a contact hole forming mask to form a contact hole;after etching the first insulating layer, forming a conductive layer filling the contact hole on the first insulating layer;etching the conductive layer until an upper surface of the first insulating layer is exposed;forming a second insulating layer over the first insulating layer; andplanarization-etching the second and first insulating layers to form a contact plug and simultaneously to planarize a substrate surface by leaving a part of the second insulating layer in the second region.