Patent ID: 7202524
Filing Date: 2007-04-10
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: a floating gate comprising a lower portion in a trench defined in a surface of a substrate and an upper portion above the surface of the substrate, wherein the upper portion comprises a concave upper surface; a gate insulating layer on inner walls of the trench and interposed between the trench and the lower portion of the floating gate; a source region in the substrate proximate a first sidewall of the trench; a control gate comprising a first portion on the substrate proximate a second sidewall of the trench opposite the first sidewall, and a second portion on at least a portion of the upper portion of the floating gate; an inter-gate insulating layer on the concave upper surface of the upper portion of floating gate and interposed between the floating gate and the control gate; a tunneling insulating layer on the inter-gate insulating layer and interposed between the inter-gate insulating layer and the control gate; and a drain region in the substrate proximate to and spaced apart from the second sidewall of the trench.