Patent ID: 8212155
Filing Date: 2012-07-03
Classification: H01F,H01L

Abstract:
1. An integrated passive device, comprising: a first conductive line section positioned on a planar topmost surface of a carrier and having width W and thickness T, where T/W at least 0.5; a second conductive line section positioned on said planar topmost surface of said carrier wherein a nearest distance from said second conductive line section to said first conductive line section is S, where S is at most 1.5.T; a substrate; and a bump positioned directly on said first conductive line section, said bump including a height that has a region of a high melting-point conductor and a region of a low melting-point conductor, said bump securing said first conductive line section to said substrate and having a height of at least 30 μm wherein said bump is positioned between said first conductive line section and said substrate.