Patent ID: 6686224
Filing Date: 2004-02-03
Classification: G01R,H01L

Abstract:
A chip manufacturing method for forming a number of substantially rectangular integrated circuits, each connected to at least one test pad through a test wiring, arranged through section lines on the surface of a circuit substrate, sectioning said circuit substrate along said section lines into said individual integrated circuits to form a number of circuit chips, and conducting a circuit test as required on at least some of said integrated circuits of a number of said circuit chips through said test pads, said method comprising the steps of:setting a first and a second section lines in parallel to each other along at least one of four sides of each of said substantially rectangular integrated circuits arranged and formed on the surface of said circuit substrate; forming said test pads and/or at least part of each of said test wirings in gaps between said first and second section lines; conducting said circuit test after sectioning said circuit substrate along said first section line positioned outside; and cutting each said circuit chip along said second section line after conducting said circuit test to remove from each said circuit chip a portion thereof in which said test pad and/or at least the part of said test wiring are positioned.