Patent ID: 6360343
Filing Date: 2002-03-19
Classification: G01R

Abstract:
An event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal, comprising:an event memory for storing timing data of each event formed with an integer multiple of a reference clock period (integral part data) and a fraction of the reference clock period (fractional part data) and information indicating a type of event to be generated by said event based test system, said timing data being a time difference between two adjacent events, where events are defined as any changes in a signal generated by said test system for testing the DUT at timings relative to a predetermined reference point which is a fixed timing point common to all of the events and wherein said reference point is unrelated to test cycles used in traditional test systems; an address sequencer for generating address data for accessing said event memory to read out said timing data therefrom; a timing count logic for summing said timing data to produce an overall time of each event relative to said predetermined reference point, said timing count logic including a delay means for adding one reference clock period every time when a sum of said fraction exceeding said reference clock period; an event generation circuit for generating each event based on said overall time and said information on said event type for formulating said test signal or strobe signal; and a host computer for controlling an overall operation of said event based test system through a test program.