Patent ID: 6073267
Filing Date: 2000-06-06
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit comprising:an instruction memory for receiving an address signal, outputting an instruction code signal corresponding to said address signal, and storing an instruction code in advance:a first memory for receiving a clock signal and sequentially outputting and storing said address signal in synchronization with said clock signal;a second memory for temporarily storing and outputting said instruction code signal in synchronization with said clock signal; andan error detecting circuit detecting an error in operation of said instruction memory by comparing a check code signal generated every cycle of said clock signal with check data corresponding to said instruction code and its address value in accordance with a signal outputted from said second memory and said address signal,wherein said error detecting circuit includesa third memory for temporarily storing and outputting a post address signal in synchronization with said clock signal;a check code generating circuit for generating said check code signal in accordance with signals outputted from said second and third memory;a check data memory for storing said instruction code and said check data corresponding to its address value in advance and outputting a check data signal corresponding to said address signal;a fourth memory for temporarily storing and outputting said check data signal outputted from said check data memory in synchronization with said clock signal; anda comparator for comparing a signal outputted from said fourth memory with said check code signal output from said check code generating circuit and outputting a compared result signal.