Patent ID: 9047494
Filing Date: 2015-06-02
Classification: B60R,G06F,H04L,H04W

Abstract:
1. A system for preventing use of a device for a period of time, the system comprising: a memory and a processor; at least a first subsystem deployed in the memory and executed by the processor that receives, through a network in a first manner, a first instruction to disable a functionality of the device at a specified time; at least a second subsystem deployed in the memory and executed by the processor that disables the functionality based on the first instruction; at least a third subsystem deployed in the memory and executed by the processor that receives, after passage of the period of time, a second instruction to re-enable the functionality; at least a fourth subsystem deployed in the memory and executed by the processor that verifies that the second instruction is given by a combination of two or more entities, wherein the combination has been pre-approved to re-enable the functionality; and at least a fifth subsystem deployed in the memory and executed by the processor that re-enables the functionality based on verification of the second instruction by the fourth subsystem.