Patent ID: 8648586
Filing Date: 2014-02-11
Classification: G05F

Abstract:
1. A circuit comprising: a power transistor portion defining a source, a drain, and a gate, the power transistor portion responsive to a voltage at the gate and a voltage at the source to output a first voltage at the drain of the power transistor portion, the power transistor portion including a plurality of transistors; a first transistor sizing circuit coupled to the power transistor portion, the first transistor sizing circuit operable to selectively reconfigure the power transistor portion in the transistors enabled therein based on a bias voltage of the power transistor portion, thereby controlling the size of the power transistor portion and regulating the first voltage for varying load conditions; a mirror transistor portion defining a source, a drain, and a gate, the gate of the mirror transistor portion coupled to the gate of the power transistor portion, the mirror transistor portion responsive to a voltage at the gate and a voltage at the source to output a second voltage at the drain of the mirror transistor portion, the mirror transistor portion including a plurality of transistors; a feedback amplifier coupled to the power transistor portion and the mirror transistor portion, the feedback amplifier responsive to the first voltage and the second voltage, to output a difference in magnitude of the first voltage and the second voltage; an output transistor coupled to the feedback amplifier and the mirror transistor portion, the output transistor responsive to the difference in magnitude of the first voltage and the second voltage to provide an output voltage; an analog to digital converter (ADC) coupled to the output transistor to convert the output voltage to a digital signal; and a second transistor sizing circuit coupled to the mirror transistor portion, the output transistor, and the ADC, the second transistor sizing circuit responsive to the output voltage and operable to selectively reconfigure the mirror transistor portion in the transistors enabled therein based on the output voltage, thereby controlling the size of the mirror transistor portion and varying the output voltage due to loading effect of the ADC.