Patent ID: 7482219
Filing Date: 2009-01-27
Classification: H01L

Abstract:
1. A method, comprising: forming a first etch stop layer above a first transistor element and a second transistor element; forming a first contact etch stop layer above said first etch stop layer, said first contact etch stop layer having a first type of intrinsic stress; forming a first mask layer above said first and second transistor elements to expose said first contact etch stop layer over said first transistor element and cover said second transistor element; removing a first portion of said first contact etch stop layer formed above said first transistor element by an etch process using said first etch stop layer as an etch stop; forming a second etch stop layer above said first and second transistor elements; and forming a second contact etch stop layer on said second etch stop layer, said second contact etch stop layer having a second type of intrinsic stress other than said first type.