Patent ID: 9225561
Filing Date: 2015-12-29
Classification: H04L

Abstract:
1. A pipelined decision feedback equalizer, comprising: a programmable digital-to-analog converter (DAC) configured to provide a programmable voltage to a plurality of decision feedback equalized (DFE) sections; a capacitive element associated with each of the plurality of DFE sections, each capacitive element being coupled to an input connection by a first switch and coupled to an output connection by a second switch; clock logic configured to control the first switch and the second switch so that a predefined voltage signal is applied to each capacitive element at a predefined time such that a charge corresponding to the predefined voltage signal is applied to each capacitive element; and the clock logic causing the second switch to couple each capacitive element to the output connection so as to apply the voltage on each capacitive element as a filter coefficient to a summing element.