Patent ID: 6337238
Filing Date: 2002-01-08
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor memory device, comprising the steps of:forming a metal-insulator-semiconductor transistor on a substrate such that said metal-insulator-semiconductor transistor includes a gate electrode connected to a word line and first and second diffusion regions formed in said substrate at both sides of said gate electrode and such that said first diffusion region is connected to a bit line; providing an interlayer insulation film on said substrate so as to cover said metal-insulator-semiconductor transistor; forming a contact hole in said interlayer insulation film so as to expose said second diffusion region; filling said contact hole by a conductive plug; depositing consecutively a layer of an Ir alloy and a layer of an oxide of said Ir alloy on said interlayer insulation film so as to cover said conductive plug; patterning said layer of Ir alloy and said layer of oxide of said Ir alloy to form a lower electrode pattern; depositing an insulation film on said lower electrode pattern; patterning said insulation film to form a capacitor insulation film; depositing a conductor layer on said capacitor insulation film; and patterning said conductor layer to form an upper electrodes, wherein said step of patterning said lower electrode pattern is conducted by a dry etching process conducted in an oxygen atmosphere while using a mask pattern of Pt.