Patent ID: 6490283
Filing Date: 2002-12-03
Classification: G06F,H04L

Abstract:
A communication system with a first processor providing first addresses with a first number of bits to select a first device and a second processor providing second addresses with a second number of bits to select a second device, said communication system characterized in thatthe first and second processors are coupled to the first and second devices by a shared bus having a total number of bit lines which is smaller than or equal to the sum of first number of bits and the second number of bits, the bit lines are assigned to a first set, a second set, and a shared set and wherein bits with a first significance of said first address are coupled to lines of said first outer set, bits with the first significance of said second address are coupled to lines of said second outer set, and bits with a second, opposite significance of said first and second addresses are multiplexed to lines of said shared set.