Patent ID: 7791415
Filing Date: 2010-09-07
Classification: H03L

Abstract:
1. A fractional-N synthesized chirp generator, comprising: a fractional-N synthesizer configured to receive a reference frequency input signal and a first frequency control value, the fractional-N synthesizer configured to transform the reference frequency input signal and the first frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner, the fractional-N synthesizer comprising: a frequency synthesizer comprising: a voltage controlled oscillator; and a programmable frequency divider, the programmable frequency divider configured to receive a second frequency control value; a sigma-delta modulator module comprising: a sigma-delta modulator configured to receive one or more lower significant values of the first frequency control value and the reference frequency input signal, the sigma-delta modulator configured to transform the one or more lower significant values of the frequency control value to a third frequency control value utilizing a pseudo-random sequence, the third frequency control value representing a fractional count value when averaged over a time window; and a summation block configured to add the third frequency control value and one or more most significant values of the first frequency control value, the summation block configured to produce the second frequency control value having a frequency spectra content that is higher than a loop bandwidth defined by the frequency synthesizer; and a digital ramp synthesizer configured to receive the reference frequency input signal, the digital ramp synthesizer configured to generate the first frequency control value utilizing the reference frequency input signal, the digital ramp synthesizer configured to provide the first frequency control value to the fractional-N synthesizer, the first frequency control value varying with time, the digital ramp synthesizer comprising: a ramp synthesizer block comprising: an up-chirp ramp rate block configured to provide an up-chirp ramp rate; a down-chirp ramp rate block configured to provide a down-chirp ramp rate; a selector configured to select the up-chirp ramp rate or the down-chirp ramp rate based on a counter control value, the selector configured to produce a frequency ramp control value; and a frequency control value generation block configured to produce the first frequency control value utilizing the reference frequency input signal and the frequency ramp control value; and a ramp controller block comprising: an upper frequency limit block configured to provide an upper frequency limit value; a lower frequency limit block configured to provide a lower frequency limit value; a second selector configured to select the upper frequency limit value or the lower frequency limit value based on a counter control value, the second selector configured to produce a frequency limit value; and a compare logic block configured to receive the frequency limit value and the first frequency control value, the compare logic block configured to produce a counter control value.