Patent ID: 7643363
Filing Date: 2010-01-05
Classification: G11C

Abstract:
1. An integrated circuitry operable in a normal operation mode and in a test operation mode, comprising: processing circuit means; output circuit means associated with the processing circuit means; and storage means with a plurality of memory cells, wherein the output circuit means is formed to process an output signal, in the normal operation mode, from the processing circuit means and provide a processed output signal at an output terminal of the integrated circuitry; wherein the output circuit means is further formed to provide, in the test operation mode, a test signal as the processed output signal based on a drive signal that may be supplied externally or from the processing circuit means; wherein the storage means is formed to receive, in the test operation mode, the test signal and perform an evaluation of a memory property of at least one memory cell of the plurality of memory cells based on the test signal, and, in response to this evaluation, to output an evaluation signal indicating the memory property of the at least one memory cell of the plurality of memory cells.