Patent ID: 6832296
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A microprocessor for executing a prefetch instruction specifying a block of cache lines to be prefetched from a System memory into a cache of the microprocessor, the microprocessor comprising:a prefetch count register, for storing a count of the cache lines remaining to be prefetched; a general purpose register, coupled to said prefetch count register, for storing an initial value of said count, said initial value loaded into said general purpose register by an instruction prior to the prefetch instruction; control logic, coupled to said prefetch count register, for copying said initial value from said general purpose register to said prefetch count register in response to decoding the prefetch instruction; and a comparator, coupled to said control logic, for determining whether a number of free response buffers in the microprocessor is greater than a threshold value; wherein said control logic delays prefetching the cache lines until said number of free response buffers is greater than said threshold value, wherein said threshold value is programmable.