Patent ID: 7046072
Filing Date: 2006-05-16
Classification: H03K,H03L

Abstract:
1. A phase selector for selecting a differential output, the phase selector comprising: a first transistor circuit for receiving a first differential input signal; a second transistor circuit for receiving a second differential input signal; and a pair of output lines connected to the first and second transistor circuits, wherein the output lines provide the differential output, and wherein the first and second transistor circuits are substantially matched, wherein each transistor circuit includes: a current source connected to a first voltage source; a first pair of transistors, wherein gates of the first pair of transistors receive one of the first and second differential input signals, sources of the first pair of transistors are connected to the current source, a drain of one transistor of the first pair of transistors is connected to a first node, and a drain of another transistor of the first pair of transistors is connected to a second node; a second pair of transistors, wherein gates of the second pair of transistors receive a first control signal, drains of the second pair of transistors are connected to a second voltage source, a source of one transistor of the second pair of transistors is connected to the first node, and a source of another transistor of the second pair of transistors is connected to the second node; a third pair of transistors, wherein gates of the third pair of transistors receive a second control signal, a source of one transistor of the third pair of transistors is connected to the first node, a source of another transistor of the third pair of transistors is connected to the second node, a drain of one transistor of the third pair of transistors is connected to one of the pair of output lines, and a drain of another transistor of the third pair of transistors is connected to another of the pair of output lines; and a fourth pair of transistors, wherein gates of the fourth pair of transistors receive a third control signal, a source of one transistor of the fourth pair of transistors is connected to the first node, a source of another transistor of the fourth pair of transistors is connected to the second node, a drain of one transistor of the fourth pair of transistors is connected to one of the pair of output lines, and a drain of another transistor of the fourth pair of transistors is connected to another of the pair of output lines.