Patent ID: 8327199
Filing Date: 2012-12-04
Classification: G01R

Abstract:
1. An integrated circuit (IC), comprising: an input/output (I/O) pin, wherein the I/O pin is configured as one of a test pin and a user I/O pin; a first selector circuit having an output coupled to a logic block, wherein the first selector circuit selectively couples one of the I/O pin or another I/O pin to the logic block; a second selector circuit having an output coupled to an output buffer, wherein the second selector circuit is configured to select one of a user output or a test output as an output of the I/O pin; a third selector circuit having an output coupled to the output buffer, wherein the third selector circuit selectively enables and disables the output buffer; and a plurality of switches, wherein each of the plurality of switches is configurable to couple to the first, second and third selector circuits, and wherein a configuration of the switches determines each of the outputs of the first, second and third selector circuits.