Patent ID: 7471302
Filing Date: 2008-12-30
Classification: G06F,G09G

Abstract:
1. A display driver, comprising: a parity generation circuit that generates s-bit (s is an integer of one or more) parity data for n-bit (n is an integer greater than one) display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit that performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder that decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits that latch the data decoded by the decoder; and a plurality of data line driver sections that drive data lines of a display panel based on the data latched by the latch circuits, the parity generation circuit generating the s-bit parity data based on a sum of a value of each bit of the n-bit display data so that a sum of a value of each bit of the (n+s)-bit display data becomes an even number or an odd number, and outputs the (n+s)-bit display data to the display memory, when a value held in a memory cell is more frequently rewritten as “0” than “1” upon occurrence of a malfunction of a transistor connected with a wordline of the memory cell of the display memory, the s-bit parity data being set so that the sum of a value of each bit of the (n+s)-bit display data output from the parity generation circuit is an odd number, and when the held value is more frequently rewritten as “1” than “0” upon occurrence of a malfunction of the transistor connected with the wordline of the memory cell of the display memory, the s-bit parity data being set so that the sum of a value of each bit of the (n+s)-bit display data output from the parity generation circuit is an even number.