Patent ID: 6236085
Filing Date: 2001-05-22
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:a semiconductor substrate of a first conductivity type;a source region of a second conductivity type disposed in said semiconductor substrate;a drain region of the second conductivity type disposed in said semiconductor substrate to be spaced from said source region;a floating gate disposed over a portion of said semiconductor substrate between said source region and said drain region;a control gate disposed to overlap with said floating gate with an insulation film interposed;a first impurity region of the second conductivity type disposed under said floating gate in contact with said drain region and spaced from said source region, said first impurity region having an impurity concentration lower than that of said drain region; anda second impurity region of the first conductivity type disposed under said floating gate to encompass at least said first impurity region, said second impurity region having an impurity concentration higher than said semiconductor substrate and creating a PN junction in association with said first impurity region so that a net impurity concentration of the first conductivity type along said PN junction is higher at a first region contacting a side of said first impurity region than a second region contacting a bottom of said first impurity region.