Patent ID: 7626437
Filing Date: 2009-12-01
Classification: G11C,H03K

Abstract:
1. An apparatus for converting a first differential clock signal and a second differential clock signal into a single-ended output clock signal, the apparatus comprising: a first voltage rail; a second voltage rail; an NMOS differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the NMOS differential amplifier receives the first differential clock signal, and wherein the second input terminal of the NMOS differential amplifier receives the second differential clock signal; a PMOS differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the PMOS differential amplifier receives a first differential clock signal, and wherein the second input terminal of the PMOS differential amplifier receives a second differential clock signal a bias circuit including: a NAND gate that is coupled to the output terminals of the PMOS and NMOS differential amplifiers; a first inverter that is coupled to the NAND gate; and a second inverter that is coupled to the first inverter, wherein the second inverter outputs the single-ended output clock signal.