Patent ID: 7493536
Filing Date: 2009-02-17
Classification: G01R,H03K

Abstract:
1. An integrated circuit comprising: A. plural circuits within the integrated circuit, including a first, functional core logic circuit, a second, scan data circuit, a third, control circuit, and a fourth, control circuit; B. an input terminal for inputting data to the integrated circuit; C. an input memory circuit having first and second data inputs, first and second control inputs, and a memory data output, the input memory circuit being separate from the second, scan data circuit; D. the first, functional core logic circuit having a data input and there being a first connection formed between the memory data output and the data input of the first, functional core logic circuit within the integrated circuit; E. a second connection formed between the first data input of the input memory circuit and the input terminal; F. the second, scan data circuit having a data output, and there being a third connection formed between the data output from the second, scan data circuit within the integrated circuit and the second data input, the data output of the second, scan data circuit being coupled to the data input of the first, functional core logic circuit through the input memory; G. the third, control circuit having a control output, and there being a fourth connection formed between the control output from the third, control circuit within the integrated circuit and the first control input, the fourth connection being separate from the second, scan data circuit; and H. the fourth, control circuit having a control output, and there being a fifth connection formed between the control output from the fourth, control circuit within the integrated circuit and the second control input, the fifth connection being separate from the second, scan control circuit.