Patent ID: 6185668
Filing Date: 2001-02-06
Classification: G06F

Abstract:
An apparatus for facilitating speculative execution of instructions in a data processing system, comprising:a register file comprising a plurality of registers, each one of the plurality of registers configured to store one of a plurality of instructions;a plurality of single-bit storage units disposed separately from the register file;a multiple bit write bus coupled to the plurality of single bit storage units; anda multiple bit read bus coupled to the plurality of single bit storage units;wherein each one of the plurality of single-bit storage units corresponds to one of the plurality of registers and is configured to store one of a plurality of speculative bits,wherein the plurality of single-bit storage units are configured to simultaneously receive and store the plurality of speculative bits; andwherein each one of the plurality of speculative bits is operable to indicate an occurrence of an exception, wherein each one of the plurality of speculative bits indicates the occurrence of the exception if the execution of an instruction stored in a corresponding register generates an exception.