Patent ID: 7221763
Filing Date: 2007-05-22
Classification: H04L

Abstract:
1. An advanced encryption standard (AES) architecture which provides high throughput and low latency, comprising: a maximum parallel encryption circuit that receives a plurality of data bytes to be encrypted and implements one round of the AES algorithm in one clock cycle; a maximum parallel key scheduling circuit that generates sub-keys in one clock cycle in parallel with said maximum parallel encryption circuit, said sub-keys provided to said maximum parallel encryption circuit; and a controller that controls the operation of said maximum parallel encryption and key scheduling circuits such that said AES architecture performs one round of the AES algorithm in one clock cycle; wherein said AES architecture employs a chosen key-length k and a data-block length m, said maximum parallel key scheduling circuit comprising: a first key scheduling sub-circuit that receives a previously-generated sub-key and generates a current sub-key; a second key scheduling sub-circuit that receives the current sub-key and generates a next sub-key; and a roundkey assembly sub-circuit which receives said previously-generated sub-key, said current sub-key, said next sub-key and which assembles an m-bit roundkey from said previously-generated sub-key, said current sub-key, and said next sub-key, and provides said roundkey to said maximum parallel encryption circuit.