Patent ID: 6278654
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A synchronous flash memory device comprising:an array of non-volatile memory cells arranged in banks of rows and columns;address connections to receive address signals;a clock connection to receive an external clock signal;a chip select (CS#) connection to receive a chip select signal;a row address strobe (RAS#) connection to receive a row address strobe;a column address strobe (CAS#) connection to receive a column address strobe;a write enable (WE#) connection to receive a write enable signal; andcontrol circuitry to perform a burst read operation of memory cells in a first block of the array and interrupt the burst read operation when the chip select signal is active, the row address strobe is either active or inactive, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.