Patent ID: 6753714
Filing Date: 2004-06-22
Classification: H03K

Abstract:
A flip-flop receiving a data (D) input and a clock (CLK) input, said flip-flop comprising:a master latch receiving said D input and a feedback input on a first path and a second path respectively, said master latch generating a first output when clocked; a slave latch being coupled to receive said first output, said slave latch generating a second output when clocked; a clock generation circuit clocking said master latch and said slave latch based on said CLK input, said clock generation circuit controlling said master latch and said slave latch such that said master latch and said slave latch do not have internal transitions due to clocking when said flip-flop is to be disabled; a feedback circuit providing said second output as said feedback input on said second path when said flip-flop is disabled; wherein said feedback circuit comprises only a first pass gate such that a number of transistors contained in said flip-flop are minimized; wherein said flip-flop further receives a disable (ENZ) input, wherein said ENZ input indicates whether said flip-flop is presently enabled or disabled, wherein said ENZ signal is provided to said clock generation circuit; and wherein said clock generation circuit generates a clock enable signal (EN) having a logical high when said flip-flop is to be enabled, and a clock disable signal (ENZZ) having a logical high when said flip-flop is to be disabled, wherein said clock generation circuit further generates a CKB signal by performing an AND logical operation of said EN signal and said CLK signal, said clock generation circuit generating a CKZ signal which is a logical inversion of said CKB signal.