Patent ID: 6460064
Filing Date: 2002-10-01
Classification: G06F

Abstract:
A multiplier for multiplying n bits and n/2 bits wherein a word multiplication is implemented by input of two words, comprising:a first encoder receiving the lower byte and a word control signal and outputting a first encoding signal and a second encoding signal which is the result of NANDing the first encoding signal and the word control signal; a second encoder receiving the upper byte and the word control signal and outputting a third encoding signal and a fourth encoding signal which is the result of NANDing the third encoding signal and the word control signal; a partial product generating unit including submodules receiving the first to fourth encoding signals and the word control signal and generating partial products; an operating unit receiving the partial products and outputting a first sum signal, a second sum signal, a first carry word signal and a second carry word signal; a first adder receiving the first sum signal and the first carry word signal and outputting a first carry and a first output signal; and a second adder receiving the second sum signal and the second carry word signal and outputting a second carry and a second output signal.