Patent ID: 7560755
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A junction field effect transistor (JFET) integrated into a substrate, comprising: a substrate having at least a portion thereof which is semiconductor, said semiconductor having an active area defined by non conductive material surrounding a well region doped to a predetermined conductivity type; source, drain, channel, well and gate regions each having predetermined doping levels and junction depths so as to be doped with impurities appropriate to the type of JFET being formed and with doping impurity concentrations of said gate, channel and well region and junction depths of a gate-channel junction and a channel-well junction being controlled such that depletions regions around said gate-channel junction and said channel-well junction cause pinchoff at a predetermined voltage depending upon whether an enhancement mode or depletion mode device is desired; source and drain contacts to said source and drain regions and formed of a first conductive material and doped to a first conductivity type having a first dielectric layer covering them; a self-aligned gate contact to said gate region and formed of polysilicon doped to a second conductivity type, said polysilicon having been polished back to be nearly flush with a top of said first dielectric layer covering said source and drain contacts, said self-aligned gate contact being separated and insulated from said source and drain contacts by a spacer dielectric structure.