Patent ID: 8053869
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit device package, the method comprising: providing a wafer containing a matrix of integrated circuit device members, each one of said integrated circuit device members having a respective electrically active face and an opposing backside, and a saw street circumscribing each one of said integrated circuit members; mounting the wafer to an electrically non-conductive substrate so that the electrically active face is in contact with said substrate; subsequently forming a trough partially through said wafer from said backside of said wafer in alignment with said saw street, said trough having a first width; subsequently forming a channel beginning at a base of said trough and extending from said trough to a depth effective to pierce said electrically active face, said channel having a second width that is less than said first width, removing the singulated integrated circuit device member from the electrically non-conductive substrate; connecting the electrically active face to circuitry having electrical contacts extending therefrom to provide interconnection to an external conductor; and applying a dielectric molding resin to partially encapsulate the integrated circuit device member while leaving exposed said backside and said electrical contacts on opposing sides of the package, said molding resin contacting said step feature to provide a feature effective to