Patent ID: 6962826
Filing Date: 2005-11-08
Classification: G01R,Y10T

Abstract:
1. A method for in-line electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising: inserting a substrate into an in-line electrical test socket; positioning one or more IC dice on a surface of the substrate and pressing interconnection bumps of the one or more IC dice into conductive contact with conductive quick-cure epoxy pads of the substrate to form the flip-chip semiconductor assembly while the substrate is inserted into the in-line electrical test socket; electrically testing the flip-chip semiconductor assembly using the in-line electrical test socket while the substrate is inserted into the in-line electrical test socket and before sealing of the one or more IC dice; repairing the flip-chip semiconductor assembly if it fails the electrical testing; curing the conductive quick-cure epoxy pads of the substrate; and sealing the one or more IC dice of the flip-chip semiconductor assembly.