Patent ID: 6137337
Filing Date: 2000-10-24
Classification: G09G

Abstract:
A sampling clock signal generation circuit of a liquid crystal display device generating sampling clock signals with a master clock signal generated from an external reference synchronous signal, comprising:a synchronousness compensation section receiving the external reference synchronous signal and the master clock signal as input signals, to generate a synchronousness compensation signal; anda sampling clock signal generation section being initialized by the synchronousness compensation signal and dividing the master clock signal, to generate the sampling clock signals synchronized with the external reference synchronous signal, wherein the sampling clock signal generation section includes:a first sampling clock signal generation section being initialized by the synchronousness compensation signal and generating a first pulse signal at a falling edge of the master clock signal;a second sampling clock signal generation section being initialized by the synchronousness compensation signal and generating a second pulse signal at a rising edge of the master clock signal;an output section receiving the first and second pulse signals to generate the sampling clock signals synchronized with the external reference synchronous signal; andan output control section controlling the output of the second sampling clock signal generation section so that the second sampling clock signal generation section generates the second pulse signal after the first sampling clock signal generation section generates the first pulse signal.