Patent ID: 8659144
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A semiconductor package comprising: a plurality of electrical connectors; a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads that provide power to the core logic, and a plurality of input/output signal pads that carry signals to and from the core logic, wherein each core logic input-power pad and core logic output-power pad, and each input signal pad and output signal pad, has an electrical connector of the plurality of electrical connectors extending therefrom; and a package substrate configured to provide power to the core logic of the semiconductor die and having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer, the first metal redistribution layer providing a first electrical potential to each of the input-power contact pads, the second metal redistribution layer providing a second electrical potential to each of the output-power contact pads, wherein each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.