Patent ID: 6337590
Filing Date: 2002-01-08
Classification: G11C,H03L

Abstract:
In a digital delay locked loop (DLL) comprising a phase detector for receiving and comparing a reference clock signal (CLKR) and an internal clock signal (CLKI), a digital delay circuit having a variable delay line for delaying an output of the phase detector, and through an output driver, providing a DLL output clock signal (CLK_IO); and a reference delay feedback circuit for receiving the CLK_IO signal, delaying the CLK_IO signal and providing the delayed CLK_IO signal as the internal clock (CLKI) signal to an input of the phase detector, the improvement in the DLL comprising: a region entry detector for detecting that said reference clock signal (CLKR) and said internal clock signal (CLKI) are within a phase detection region; a control circuit for receiving the output of the phase detector and said region entry detector, said control circuit controlling the variable delay in the digital delay circuit substantially locking the reference clock (CLKR) and the internal clock (ICLKI) signals together in synchronization within said phase detection region; wherein said phase detection region is greater than or equal to one half and less than a full period of the reference clock.