Patent ID: 6750692
Filing Date: 2004-06-15
Classification: G06F,H03K

Abstract:
A circuit for generating an internal clock signal, the circuit comprising:a first delay means for delaying an external clock signal by a first delay time; a dividing means for dividing an output signal from the first delay means; a first signal generation means for generating a first signal with a pulse width equivalent to a skew monitor time, by delaying an output signal from the dividing means by a second delay time, and by combining the output signal from the dividing means with a signal delayed by the second delay time; a second signal generation means for generating a second signal with a pulse width equivalent to a third delay time at an edge of the output signal from the first delay means; a time/digital signal converter means for converting the skew monitor time equivalent to the pulse width of the first signal into a first digital signal and a second digital signal in response to the first signal; and a digital signal/time converter means for reproducing the skew monitor time by inputting the first and second digital signals in response to the second signal, and generating the internal clock signal being delayed by a fourth delay time from the skew monitor time reproduced.