Patent ID: 7164305
Filing Date: 2007-01-16
Classification: H03K

Abstract:
1. A high-voltage tolerant input buffer circuit comprising: a first NMOS transistor having a source terminal coupled to an input pin, a gate terminal coupled to a first reference voltage, and a drain terminal coupled to a first output terminal; a second NMOS transistor having a gate terminal coupled to said first reference voltage and a source terminal coupled to said first output terminal; a first PMOS transistor having a gate terminal coupled to a drain terminal of said second NMOS transistor, a drain terminal coupled to a second reference voltage lower than said first reference voltage and a source terminal coupled to a second output terminal; a second PMOS transistor having a drain terminal coupled to the drain terminal of said second NMOS transistor, a source terminal coupled to said second output terminal; and a gate terminal coupled to a control voltage; and a third PMOS transistor having a drain terminal coupled to said second output terminal, a source terminal coupled to a supply voltage, and a gate terminal coupled to said control voltage.