Patent ID: 6630857
Filing Date: 2003-10-07
Classification: H03K

Abstract:
A semiconductor integrated circuit device comprising:a first circuit including a first MOS transistor and a first memory circuit; and a first power supply voltage control circuit supplying a first power supply voltage to the first circuit; and a substrate bias control circuit supplying a first substrate bias voltage to the first MOS transistor; a second circuit including a second memory circuit; and a second power supply voltage control circuit supplying a second power supply voltage to the second circuit; wherein in a first mode, the substrate bias control circuit controls the first substrate bias voltage to be a first voltage and the first power supply voltage control circuit controls the first power supply voltage to be a second voltage; wherein in a second mode, the substrate bias control circuit controls the first substrate bias voltage to be a third voltage so that a subthreshold voltage of the first MOS transistor becomes higher than that in the first mode and the first power supply voltage control circuit controls the first power supply voltage to a voltage lower than the second voltage and sufficiently high for holding data of the first memory circuit; and wherein in the second mode, the second power supply vohage control circuit controls the second power supply voltage to be lower than that in the first mode, so that data of the second memory circuit is erased.