Patent ID: 8339856
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array comprising an array of NAND cell units each comprising a memory string comprising a plurality of electrically rewritable memory cells connected in series, and a drain-side select transistor and a source-side select transistor connected to ends of the memory string, respectively; and a control circuit configured to apply to the memory cell array various voltages for reading, writing, and erasing data, the NAND cell unit comprising: a first columnar semiconductor layer formed extending in a direction perpendicular to a substrate and functioning as bodies of the memory cells; a plurality of first conductive layers formed around the first columnar semiconductor layer with a charge accumulation layer for accumulating charges and a gate-insulating film sandwiched therebetween, the first conductive layers being formed over a plurality of layers, and each of the first conductive layers functioning as a word-line for selecting the memory cell; a second columnar semiconductor layer formed in contact with a first end portion of the first columnar semiconductor layer and formed extending in a direction perpendicular to the substrate, the second columnar semiconductor layer functioning as a body of the drain-side select transistor; a second conductive layer formed around the second columnar semiconductor layer with a gate-insulating film sandwiched therebetween, the second conductive layer functioning as a select-gate-line of the drain-side select transistor, a third columnar semiconductor layer formed in contact with a second end portion of the first columnar semiconductor layer and formed extending in a direction perpendicular to the substrate, the third columnar semiconductor layer functioning as a body of the source-side select transistor; and a third conductive layer formed around the third columnar semiconductor layer with a gate-insulating film sandwiched therebetween, the third conductive layer functioning as a select-gate-line of the source-side select transistor, a bit-line being connected to one end of the second columnar semiconductor layer, a source-line being connected to one end of the third columnar semiconductor layer, and the NAND cell units sharing the same first conductive layer and forming a block as a unit of an erase operation of the memory cell, the control circuit being configured to erase a selected block in the erase operation by applying a predetermined potential to the source-line and the third conductive layer to generate a current to increase a potential of the first columnar semiconductor layer and by providing a first voltage to the first conductive layer, and the control circuit being configured to keep the first conductive layers at a floating state for a first period, and during a second period after the first period, to switch the first conductive layers from the floating state to a state in which the first conductive layer is charged to a second voltage higher than the first voltage, in an unselected block in the erase operation.