Patent ID: 6813598
Filing Date: 2004-11-02
Classification: G06F

Abstract:
A mixed-level logic simulation apparatus comprising:memory cell array subdecoder operation model providing means for providing an operation model corresponding to a memory cell array and a subdecoder circuit; a sense amplifier and I/O gate operation model providing means for providing an operation model corresponding to a sense amplifier and an I/O gate circuit; a transistor and gate element operation model providing means for providing an operation model of a transistor and a gate element; circuit connection data providing means for providing circuit connection data prescribing connection of logic circuits; input test pattern providing means for providing a test pattern to an input part of the logic circuit; function and logic simulation means for executing logic simulation of the logic circuit based on the input test pattern; simulation result displaying means for displaying a result of simulation obtained by said function and logic simulation execution means in order to verify that a function of the logic circuit is realized, wherein circuit operation of the logic circuit comprising transistors, logic gates and functional blocks is tested, using models of switches, gates and functions.