Patent ID: 7141835
Filing Date: 2006-11-28
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a memory cell storing data; and a bit line pair and at least one word line connected to said memory cell; wherein said memory cell includes first and second charge holding circuits holding charges corresponding to said data and charges corresponding to inverted data of said data, respectively, first and second access transistors provided between one bit line of said bit line pair and said first charge holding circuit and between the other bit line of said bit line pair and said second charge holding circuit, respectively, and each having first and second gate electrodes, and first and second charge compensating circuits compensating for charges leaked from said first and second charge holding circuits, respectively, each of said first gate electrodes of said first and second access transistors is connected to a corresponding word line, said second gate electrode of said first access transistor is connected to a first node that interconnects said second charge compensating circuit, said second charge holding circuit and said second access transistor, said second gate electrode of said second access transistor is connected to a second node that interconnects said first charge compensating circuit, said first charge holding circuit and said first access transistor, said first access transistor transmits the charges corresponding to said data between said one bit line of said bit line pair and said first charge holding circuit when said first gate electrode is activated, and discharges the charges leaking to said first charge holding circuit into said one bit line of said bit line pair when said first gate electrode is inactivated and said second gate electrode is activated, and said second access transistor transmits the charges corresponding to said inverted data between said other bit line of said bit line pair and said second charge holding circuit when said first gate electrode is activated, and discharges the charges leaking to said second charge holding circuit into said other bit line of said bit line pair when said first gate electrode is inactivated and said second gate electrode is activated.