Patent ID: 6830177
Filing Date: 2004-12-14
Classification: H01L,H05K,Y02P

Abstract:
A method of connecting an area grid array chip scale package (CSP) to a printed wiring board (PWB), comprising:forming a lead matrix in a conductive material by etching the conductive material in a predetermined pattern to form a plurality of conductive leads substantially parallel to one another and substantially perpendicular to the CSP and the PWB, the leads being formed integrally with at least one tie bar, each lead having a body with first and second ends; orienting a first side of the lead matrix so that the first ends of the leads are aligned with a reciprocal matrix of conductive surface pads on the area grid array CSP; electrically connecting the conductive surface pads of the area grid array CSP to the respective first ends of the leads; removing the tie bar from the lead matrix; orienting a second side of the lead matrix so that the second ends of the leads are aligned with a reciprocal matrix of conductive surface pads of the PWB; and electrically connecting the conductive surface pads of the PWB to the respective second ends of the leads thereby establishing an electrical connection between the area grid array CSP and the PWB, the lead bodies defining a space between the carrier and the chip or board to which the first ends of the leads are connected, the space containing the intermediate portion of the lead bodies.