Patent ID: 7701058
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a substrate including a shallow trench isolation (STI) structure; a first gate dielectric located on a semiconductor portion of said substrate; a block of undoped polysilicon located directly on a top surface of said shallow trench isolation (STI) structure; a first block of doped polysilicon located directly on said first gate dielectric and in direct contact with said block of undoped polysilicon at a first boundary; a block of undoped polysilicon metal silicide located directly on a top surface of said block of undoped polysilicon; and a first block of doped polysilicon metal silicide located directly on a top surface of said first block of doped polysilicon and located directly on an edge of said block of undoped polysilicon metal silicide, wherein said edge of said block of undoped polysilicon metal silicide vertically coincides with said first boundary.