Patent ID: 9002915
Filing Date: 2015-04-07
Classification: G06F,H03K

Abstract:
1. A circuit for shifting bussed data, the circuit comprising: a first column of shift blocks, the first column shifting the bussed data by a given number of bits, the given number of bits being specified by a value of a plurality of first bits of a multi-bit shift control input; a first compare block that determines a value of a second bit of the multi-bit shift control input and creates an output reflecting that value; and a second column of multiplexer blocks coupled to the first column, the second column having a control input coupled to the output of the first compare block, the second column shifting the bussed data by one byte when the second bit of the multi-bit shift control input has a first value, the second column not shifting the bussed data when the second bit of the multi-bit shift control value has a second value different from the first value, wherein the shift blocks and the multiplexer blocks each comprise a logic block programmable to function as a shift block or as a multiplexer block.