Patent ID: 9182810
Filing Date: 2015-11-10
Classification: G06F,Y02D

Abstract:
1. A method for conserving power in a computing device having a plurality of resources and at least one processor, comprising: defining a plurality of low power resource modes in a compilable expression, each of the plurality of low power resource modes identifying a set of resource dependencies, power savings and latency time characteristics associated with a resource as well as a low power state into which each of the plurality of resources can be placed when not in use; selecting at runtime a combination of low power resource modes maximizing power savings and latency savings; compiling the defined plurality of low power resource modes to generate one or more synthetic low power resources each having one or more synthetic low power resource modes that represent functionality, power savings, latency time and resource dependencies characteristics of the selected combination of low power resource modes; controlling at least one synthetic low power resource and selecting, at an idle time, at most one synthetic low power resource mode for each synthetic low power resource based on the synthetic low power resource mode's power savings, latency time, and resource dependency requirements based on current operating conditions of the computing device; and entering and exiting the selected synthetic low power resource modes in the appropriate order when the processor becomes and leaves idle.