Patent ID: 8300474
Filing Date: 2012-10-30
Classification: G06F,G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array including a selected memory cell as a target of a program operation; a row decoder that selects a selected word line connected to the selected memory cell; a data latch circuit that latches program data stored in the selected memory cell; a verify circuit that judges completion/non-completion of storing of the program data in the selected memory cell; and a control circuit that outputs status information to an external controller before the program operation terminates, wherein the control circuit is configured to: repeat an application of a write pulse and a verify read operation to the selected word line, perform a read operation from the selected memory cell after the storing of the program data is judged to be completed by the verify circuit, and output the status information indicating that the program operation has passed to the external controller when data read by the read operation and the program data match and the status information indicating that the program operation has failed to the external controller when both do not match, wherein the data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.