Patent ID: 7390717
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A method for fabricating a power semiconductor device, comprising the steps of: forming a mask layer over a surface of a semiconductor body of a first conductivity; patterning said mask layer with a plurality of first openings, wherein each of said first plurality of openings extends to and thereby exposes the surface of said semiconductor body; forming inside spacers along sidewalls of each of said first plurality of openings; defining a plurality of trenches in said semiconductor body by etching through said inside spacers; forming a gate electrode in each of said plurality of trenches; forming an insulation cap over each of said gate electrodes; forming outside spacers along sidewalls of each of said insulation caps, wherein said outside spacers define second openings exposing the surface of said semiconductor body; and using said outside spacers to form regions of a second conductivity along the surface of said semiconductor body.