Patent ID: 6518660
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A semiconductor package comprising:a substrate having an upper surface and a lower surface, wherein a plurality of substrate pads are on the upper surface, and one or more of the plurality of substrate pads extend to form a ground pattern; an integrated circuit chip having a plurality of bond pads, one or more of the plurality of the bond pads being a ground bond pad, wherein the chip is bonded on the upper surface of the substrate, and the plurality of the bond pads are electrically connected to corresponding substrate pads; and a lid attached to the upper surface of the substrate thereby to cover the chip, wherein the lid defines a ground projection that projects into a cavity defined between the upper surface of the substrate and the lid and electrically connects the lid to the ground pattern, and wherein the ground projection is connected to the ground pattern by an electrically conductive adhesive.