Patent ID: 6212670
Filing Date: 2001-04-03
Classification: G06F,H03K

Abstract:
A method of implementing a logic circuit, comprising:(1) receiving a first netlist defining circuit components and connections between said circuit components, said first netlist including a plurality of subnets;(2) determining whether each of said plurality of subnets is to be implemented with a look-up table circuit or a product-term circuit;(3) implementing, based on said step (2), each of a first subset of said plurality of subnets in a look-up table circuit and each of a second subset of said plurality of subnets in a product-term circuit;(4) separating said plurality of subnets into high fan-in subnets and low fan-in subnets, wherein said high fan-in subnets have a number of inputs that is greater than a first predetermined number of inputs, and wherein said low-fan-in subnets have a number of inputs that is equal to or less than said predetermined number of inputs; and(5) implementing each said high fan-in subnets in a product-term circuit, and each said low fan-in subnets in a look-up table circuit.