Patent ID: 6202172
Filing Date: 2001-03-13
Classification: G01R,G06F

Abstract:
With an programmable digital processor device including a memory and a programmable digital processor coupled to the memory via an instruction bus and a data bus, a method for debugging the programmable digital processor device, the method comprising the steps of:a) asserting a reset instruction to place a smart debug interface circuit coupled to a programmable digital processor of a device into a known state;b) placing said programmable digital processor into a wait state;c) issuing an instruction to said programmable digital processor via said smart debug interface circuit;d) issuing a no operation instruction via said smart debug interface circuit such that said programmable digital processor executes one instruction at a time, if said programmable digital processor includes a multistage pipeline; ande) placing said programmable digital processor into a wait state when said programmable digital processor completes execution of said instruction.