Patent ID: 6314151
Filing Date: 2001-11-06
Classification: H03D,H03L,H04L

Abstract:
A phase comparator comprising:a first data fetching circuit for fetching an input signal in response to a transition timing of a clock signal having a frequency about half that of said input signal;a second data fetching circuit, connected to said first data fetching circuit, for fetching an output signal of said first data fetching circuit in response to a transition timing of an inverted signal of said clock signal;a first exclusive OR circuit, connected to said first data fetching circuit, for performing an exclusive OR operation upon said input signal and the output signal of said first data fetching circuit;a second exclusive OR circuit, connected to said first and second data fetching circuits, for performing an exclusive OR operation upon the output signal of said first data fetching circuit and an output signal of said second data fetching circuit;an inverter, connected to said first exclusive OR circuit, for inverting an output signal of said first exclusive OR circuit;a first AND circuit, connected to said second data fetching circuit and said second exclusive OR circuit, for performing an AND operation upon the output signal of said second data fetching circuit and an output of said exclusive OR circuit;a second AND circuit, connected to said first exclusive OR circuit and said first AND circuit, for performing an AND operation upon the output signal of said first exclusive OR circuit and an output of said first AND circuit to generate a leading signal; anda third AND circuit, connected to said inverter and said first AND circuit, for performing an AND operation upon the output signal of said inverter and The output of said first AND circuit to generate a lagging signal.