Patent ID: 6359482
Filing Date: 2002-03-19
Classification: H03K,H03L,Y10S

Abstract:
A processor system comprising:a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second logic circuit is a NAND gate; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.