Patent ID: 8859420
Filing Date: 2014-10-14
Classification: H01L,H05K,Y10S,Y10T

Abstract:
1. A method of fabricating an interconnect element, comprising: fabricating a first metal layer overlying a carrier layer, the first metal layer comprised of a first metal and including a plurality of metal traces, each of the metal traces having a first surface overlying the carrier layer, an opposed second surface, and an edge surface extending between the first and second surfaces; providing a dielectric element to overlie said metal layer and said carrier layer such that outer surfaces of said plurality of metal traces and a first major surface of said dielectric element are adjacent to said carrier layer, and inner surfaces of said plurality of metal traces are disposed within recesses in said dielectric element remote from said outer surfaces, said dielectric element having a second major surface remote from said first major surface; providing a plurality of metal posts extending from said inner surfaces of said plurality of metal traces at least to said second major surface of said dielectric element, said posts formed from a second metal; plating an etching metal layer comprised of a third metal between each of said plurality of posts and said metal traces, the etching metal layer extending along said edge surfaces of said plurality of metal traces; and etching said carrier layer to expose said first major surface of said dielectric element and portions of said outer surfaces of said plurality of metal traces not protected by said etching layer, wherein the etching metal layer protects surfaces of said posts and portions of said first metal layer not protected by said etching layer during the step of etching.