Patent ID: 9177862
Filing Date: 2015-11-03
Classification: B81B,H01L

Abstract:
1. A fabrication method of a semiconductor stack structure, comprising the steps of: providing a wafer having a first surface with a plurality of conductive pads and a second surface opposite to the first surface; disposing the wafer on a first carrier via the first surface thereof; forming a plurality of vias in the wafer via the second surface thereof to expose the conductive pads, respectively; singulating the wafer from the second surface thereof so as to obtain a plurality of chips; moving the chips from the first carrier to a second carrier having a plurality of positioning portions such that the chips are disposed on the second carrier via the second surfaces thereof and the positioning portions are located between the chips, thereby exposing the first surfaces of the chips and forming gaps between the chips; bonding the chips to a substrate via the first surfaces thereof, wherein the substrate has a plurality of blocks disposed on a surface thereof and corresponding in position to the conductive pads, respectively; removing the second carrier and the positioning portions; forming an isolation layer on the second surfaces of the chips, sidewalls of the vias and side surfaces of the chips, wherein the conductive pads are exposed from the vias, respectively; forming a redistribution layer on portions of the isolation layer on the second surfaces of the chips and forming conductive vias in the vias for electrically connecting the redistribution layer and the conductive pads; forming a protection layer on the isolation layer and the redistribution layer on the second surfaces of the chips; and cutting the substrate along the gaps between the chips to obtain a plurality of semiconductor stack structures.