Patent ID: 6583635
Filing Date: 2003-06-24
Classification: G01R,H01L

Abstract:
A testing apparatus for testing a semiconductor integrated circuit device, comprising:a base capable of receiving a semiconductor integrated circuit device, the base comprised of a plurality of contacts in electrical communication with a plurality of internal conductors, the internal conductors in electrical communication with a plurality of external contacts and capable of electrical connection to test circuitry; an elastically resilient pad that is electrically conductive normal to the plane of the pad, the elasticity resilient pad providing electrical isolation across the plane of the pad, the pad being positioned over the base resulting in a portion of the pad establishing electrical communication between the plurality of contacts on the base and a surface of the pad; an interconnect comprising a die attachment surface having a plurality of raised contacts on a first surface and configured to electrically engage contacts on the semiconductor integrated circuit device, the interconnect further comprising vias in electrical communication with contacts extending between the first surface and a second surface; a cover; and a force applying mechanism for securing the semiconductor integrated circuit device to the interconnect and pressing the semiconductor integrated circuit device, the interconnect, the pad, and the base together.