Patent ID: 7948808
Filing Date: 2011-05-24
Classification: G11C

Abstract:
1. A data output circuit of a semiconductor memory device, comprising: a data output pin where a predetermined number of a plurality of global input/output lines is allocated; a multiplexer selectively outputting data signals from the predetermined number of the plurality of global input/output lines to the data output pin in response to control signals; and a controller generating the control signals in response to operation mode signals corresponding to the data bandwidth, and the address signals provided for data signal selection, wherein the operation mode signals comprises at least an operation mode X wherein the multiplexer comprises a switching unit selectively outputting the corresponding data signals in response to the control signals from the respective global input/output lines, and wherein the switching unit comprises an inverter inverting the control signals; and a tri-state inverter having one terminal receiving the control signals inverted by the inverter and having the other terminals receiving the control signals, wherein the switching unit controls the output of the data signals.