Patent ID: 6363465
Filing Date: 2002-03-26
Classification: G11C

Abstract:
A data transfer system comprising:a system having a plurality of successive stages connected in series, each of the stages performing a partial operation necessary for transferring data in synchronism with a control clock, the system transferring data by sequentially operating the stages and performing pipeline control to allow two or more stages to simultaneously transfer data; a clock generating and switching circuit for selectively providing first clock signals substantially in phase with an external clock signal or providing second clock signals having successive different phases corresponding to sequentially increasing delays with respect to an external clock signal, the clock generating and switching circuit comprising: a plurality of clock signal units, each clock signal unit receiving a clock signal substantially in phase with the external clock signal and a control signal causing the clock signal unit to output one of the first clock signals substantially in phase with the external clock signal or to output one of the second clock signals having a phase successively delayed with respect to a prior one of the second clock signals, a first one of the clock signal units delaying the clock signal substantially in phase with the external clock signal to generate a first one of the second clock signals, a second one of the clock signal units receiving the first one of the second clock signals output by the first one of the clock signal units and delayed with respect to the external clock signal, the second one of the clock signal units and delaying the first one of the second clock signals and outputting the delayed first one of the second clock signals as a second one of the second clock signals, wherein the clock generating and witching circuit selectively provides one of the first clock signal or one of the second clock signals as internal clock signals to at least some of the stages to perform at least in part pipeline control of the stages, wherein in a first mode, all of the successive stages are controlled by the external clock signal, and in a second mode, only a first stage of the successive stage is controlled by the external clock signal, and the other stages are controlled by the internal clock signals generated by the clock generating and switching circuit.