Patent ID: 6097777
Filing Date: 2000-08-01
Classification: G11B,H03L,H04L

Abstract:
A PLL circuit supplied with a composite signal read from a recording medium in a format which includes a repetitive signal including a pulse train of a substantially constant duty ratio and a random signal including a pulse train having a format allowing variations in duty ratio, said repetitive signal and said random signal arranged essentially in time series, said PLL circuit comprising:variable oscillating means for generating an output signal having a frequency according to a control voltage indicator;phase frequency comparing means for comparing a read repetitive signal with said output signal in terms of phase and frequency to generate a phase frequency error signal;phase comparing means for comparing a read random signal with said output signal in terms of phase to generate a phase error signal; anda loop filter for filtering said phase frequency error signal to extract a wide band component when a read signal is a repetitive signal and filtering said chase error signal to extract a narrow band component when a read signal is a random signal, to generate said control voltage indicator.