Patent ID: 9059107
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of packaging a semiconductor device, the method comprising: forming a first redistribution layer (RDL) over a carrier by forming a plurality of through assembly vias (TAVs) over the first RDL by coupling an integrated circuit die over the first RDL, a first side of the integrated circuit die coupled to the first RDL, the integrated circuit die having contacts disposed at and extending above a second side of the integrated circuit die opposite the first side; forming a molding compound over the first RDL, the TAVs, and around the integrated circuit die; forming a second RDL over the molding compound, the TAVs, and the integrated circuit die by wherein the second RDL includes a plurality of second conductive elements each having a contact pad configured to accept a conductive bump thereon and disposed within a second dielectric, first ones of the plurality of second conductive elements each connected to respective ones of the contacts, a first contact pad of at least one of the first ones of the second conductive elements aligned directly over and electrically connected with a respective one of the contacts; and forming a conductive bump on the first contact pad by patterning the fourth insulating material to expose portions of the second conductive material, at least a first exposed portion of the second conductive material aligned directly over the integrated circuit die, and forming a plurality of conductive bumps over the exposed portions of the second conductive material, at least one of the plurality of conductive bumps disposed on the first exposed portion, wherein the conductive bump is aligned directly over the integrated circuit die.