Patent ID: 7415730
Filing Date: 2008-08-19
Classification: G01R

Abstract:
1. A microcomputer comprising: a first memory where a normal-operation program is stored; a second memory where a functional test program is stored; a test mode detection circuit which monitors a signal supplied through an external terminal and detects if a test mode is designated; a central processing unit (CPU) which accesses said first memory and runs said normal-operation program when said test mode is not designated, and accesses said second memory and runs said functional test program when said test mode is designated; a memory management unit which monitors an access address and data with respect to said first and second memories and causes said CPU to execute a specific operation when there has been an unauthorized illegitimate access; and a test circuit which sends a preset specific instruction to said CPU when, in said test mode, a security test signal has been output from said CPU and a specific memory area of said first and second memories has been accessed, wherein the preset specific instruction is provided from a register within said test circuit.