Patent ID: 7345460
Filing Date: 2008-03-18
Classification: H02M,Y10S

Abstract:
1. An integrated circuit comprising: (a) a temperature-adaptive digital DC-to-DC voltage converter comprising a power stage with one or more power switches, one or more inductors, and one or more capacitors; (b) a delay-line based digital controller comprising a temperature sensing circuit, a clock generator, and a pulse-width modulator; wherein said temperature sensing circuit comprises a plurality n of delay cells for creating a propagation delay in response to temperature changes in said integrated circuit; wherein said clock generator is adapted to generate a reference clock signal; and wherein said pulse-width modulator is connected to said output power supply to detect abnormal voltage changes in said integrated circuit and to generate an error signal for operating the power stage in an on-state or off-state condition; wherein: (c) when the temperature in said integrated circuit is normal, said integrated circuit performs normal operations without any interference from said delay-line based digital controller; when the output of the propagation delay is greater than about the output of said reference clock, said delay-line based digital controller signals said pulse-width modulator to increase the output voltage supplied to said integrated circuit by switching on at least one of said one or more power switches to charge at least one of said one or more inductors to deliver the stored charge to at least one of said one or more capacitors; wherein as the charge of at least one of said one or more capacitors increases, output voltage increases to increase the output of said power stage and thus to decrease the output of the propagation delay; and wherein if the output of the propagation delay is less than about the output of said reference clock, said delay-line based digital signals said pulse-width modulator to decrease the output voltage supplied to said integrated circuit by switching on at least one of said one or more power transistors to charge at least one of said one or more capacitors with less inductor current; wherein as the charge of at least one of said one or more capacitors decreases, output voltage decreases to increase the propagation delay.