Patent ID: 8059375
Filing Date: 2011-11-15
Classification: H01L,H02H

Abstract:
1. An apparatus, comprising: a first circuit node; a second circuit node; a first capacitor and a first resistor coupled in series between the first circuit node and the second circuit node; a third circuit node disposed between the first capacitor and the first resistor; a control circuit coupled to the first, second, and third circuit nodes, and configured to output a first control signal at a fourth circuit node and a second control signal at a fifth circuit node responsive to an increase in voltage at the third circuit node; and a first transistor and a second transistor coupled in series between the first circuit node and the second circuit node, wherein a gate of the first transistor is coupled to the fourth circuit node and a gate of the second transistor is coupled to the fifth circuit node, wherein the control circuit comprises: wherein a gate of the sixth transistor is coupled to a circuit node between the third and fourth transistors, a gate of the seventh transistor is coupled to a fixed potential, and a gate of the eighth transistor is coupled to a circuit node between the fourth and fifth transistors.