Patent ID: 6085318
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A microprocessor based system comprising:a first bus;a microprocessor coupled to the first bus;a system memory coupled to the microprocessor through the first bus;a second bus coupled to the first bus;a first mass storage device coupled to the microprocessor through the second bus, the first mass storage device for reading a first storage medium;a controller coupled to the microprocessor through the second bus;a second mass storage device coupled to the microprocessor through the second bus, the second mass storage device for reading a second storage medium which includes a boot record and an image which emulates the first storage medium, the boot record containing identification information and information for accessing the image, the image containing boot code and other code;a boot memory responsively coupled to the microprocessor, the boot memory containing:a set of computer instructions for determining if a boot record is present on the second storage medium;a set of computer instructions for loading the information from the boot record into the system memory;a set of computer instructions for determining the location of the image on the second storage medium wherein the location is determined using the boot record information loaded into memory;a set of computer instructions for loading the boot code from the image on the second storage medium; anda set of computer instructions for causing the microprocessor to execute the boot code to load the other code located in the image on the second storage medium.