Patent ID: 6529058
Filing Date: 2003-03-04
Classification: H03K

Abstract:
A circuit for generating stable clock signals with respect to at least one of process, temperature and voltage variations, comprising:a current source to generate a constant current having a first value; a current over capacitance (I/C) portion coupled to said current source and between a supply voltage and ground, said I/C portion consisting of first and second I/C stages; and a capacitor having a second value and coupled to a node formed by an output of said first I/C stage and an input of said second I/C stage; wherein application of a clock signal directly connected to an input of said first I/C stage generates an output at a logic gate coupled to an output of said second I/C stage, said output having a stable delay based on said first and second values; wherein at least one of said first and second values changeable to adjust an amount of the delay.