Patent ID: 6828198
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of forming gate electrode layer portions having differing widths, comprising the steps of:a) providing a structure having two or more active areas; b) forming a gate electrode layer over the structure; c) forming a hard mask layer over the gate electrode layer; d) patterning the hard mask layer within the two or more active areas to form two or more respective hard mask layer portions within the two or more active areas; the two or more respective hard mask layer portions having a first width; e) selectively trimming at least one of the two or more respective hard mask layer portions to reduce the width of the trimmed at least one of the two or more respective hard mask layer portions to a second width; and f) patterning the gate electrode layer. to form respective two or more gate electrode layer portions wherein at least one of the two or more gate electrode layer portions has a second width less than at least one other of the two or more gate electrode layer portions.