Patent ID: 8987070
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A method of forming an isolation region in a semiconductor substrate, the method comprising the steps of: providing a substrate having a substrate layer, a buried oxide (BOX) layer disposed on said substrate layer, a silicon on insulator (SOI) layer disposed on said buried oxide (BOX) layer, a pad oxide layer disposed on said silicon on insulator (SOI) layer, and a pad nitride layer disposed on top of said pad oxide layer; etching through the layers to said substrate layer to form a shallow trench region and an unetched region; etching the pad oxide layer to form ears and etching the BOX layer to form undercuts; depositing a conformal nitride or hafnium oxide liner on said shallow trench region and said unetched region; depositing a soft mask over the surface of said shallow trench region and said unetched region filling the shallow trench region; etching the soft mask so that it is recessed to the top of the BOX layer; etching the liner off of said unetched region, sidewalls of said pad nitride layer, and sidewalls of said SOI layer; removing the soft mask; and filling and polishing the shallow trench region.