Patent ID: 8423946
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A circuit comprising: a plurality of cells in a first region of said circuit, each of said plurality of cells being configured for connection to any one of a plurality of power rails, wherein a first subset of the plurality of cells has a first power pin configured to be connected to a first power rail of said plurality of power rails and a second power pin configured to be connected to a second power rail of said plurality of power rails; the first power rail of said plurality of power rails, coupled to the first subset through the first power pin said plurality of cells, said first power rail providing a first voltage, wherein the second power pin is physically deleted after coupling the first power pin to the first power rail; and the second power rail of said plurality of power rails, coupled to at least one remaining one of said plurality of cells, said second power rail providing a second voltage.