Patent ID: 8994101
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor layer; a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region; a first electrical contact connected to the second conductive regions; a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area, wherein the top of the first conductive region is etched back deeply throughout the device and the second electrical contact is a deep contact to the first conductive region; and a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact.