Patent ID: 8222734
Filing Date: 2012-07-17
Classification: H01L,H03G,H05K

Abstract:
1. An electronic device comprising: a wiring substrate having an obverse surface, a reverse surface opposite to the obverse surface, a plurality of first land pads formed over the obverse surface, and a plurality of second land pads formed over the reverse surface, and a third land pad formed over the reverse surface, and parts of the plurality of first land pads are electrically connected to parts of the plurality of second land pads; a semiconductor chip mounted over the obverse surface of the wiring substrate having a top surface, a bottom surface opposite to the top surface, and a plurality of pads formed over the top surface, the plurality of pads are electrically connected to the plurality of first land pads of the wiring substrate via a plurality of wires, respectively, and the bottom surface is electrically connected to the third land pad of the wiring substrate; a plurality of passive components mounted on the obverse surface of the wiring substrate and connected to the wiring substrate electrically; and a sealing body sealing the semiconductor chip and the plurality of wires; wherein the plurality of the second land pads are disposed over the bottom surface of the wiring substrate such that the second land pads of the plurality of the second land pads surround the third land pad, wherein the third land pad is divided into a plurality of regions, and wherein an area of one of the plurality of regions of the third land pad is larger than an area of one of the plurality of second land pads.