Patent ID: 7251723
Filing Date: 2007-07-31
Classification: G06F

Abstract:
1. A method of fault resilient booting in a multiprocessor system, comprising: designating one processor as a bootstrap processor; providing a reset signal that starts a watchdog timer timing; testing the bootstrap processor to verify that it will run BIOS code; setting a latch for disabling said bootstrap processor if the testing indicates a failure to run BIOS code or if the watchdog timer times out; starting a control unit timer for providing a time limit for a power on self-test; testing during the power on self-test the operation of said bootstrap processor; testing during a built-in self-test the operation of said bootstrap processor; setting a latch for disabling said bootstrap processor if the control unit timer times out; assigning the bootstrap process to another processor if said bootstrap processor fails a test; said testing steps being implemented in an appliance server management system.