Patent ID: 6323509
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A power semiconductor device comprising:a first semiconductor layer of a first conductivity type;an assembly of units including a first semiconductor region of a second conductivity type selectively formed in a first main surface of said first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of said first semiconductor region, a gate insulation film formed in contact with at least the surface of said first semiconductor region between said second semiconductor region and said first semiconductor layer, and a gate electrode formed on said gate insulation film;a first main electrode formed in contact with at least said second semiconductor region;a second semiconductor layer of the second conductivity type selectively formed in a second main surface of said first semiconductor layer in corresponding relation to a region in which said assembly of units is formed;a second main electrode formed in contact with a surface of said second semiconductor layer; anda current suppressing device for suppressing a main current flowing into said first semiconductor layer around said second semiconductor layer under a predetermined condition when a voltage is applied to said gate electrode so as to form a channel in said first semiconductor region.