Patent ID: 7447984
Filing Date: 2008-11-04
Classification: H03M

Abstract:
1. An apparatus, comprising: a metric generator that is operable to: a FIFO (First-In First-Out) buffer that is operable to queue the pairings of each possible value of n bits with its corresponding value of m bits having the highest likelihood; either an LDPC decoder or a turbo decoder that is operable to decode the soft information corresponding to the n bits of the m+n bit symbol according to either the LDPC code or the turbo code thereby generating an LDPC or turbo decoded bit stream; an interleaver that is operable to interleave the LDPC or turbo decoded bit stream thereby generating an n-bit symbol sequence; an m-bit un-pairing functional block that is operable to select an m-bit symbol sequence corresponding to the m+n bit symbol based the n-bit symbol sequence; a de-interleaver that is operable to de-interleave the m-bit symbol sequence thereby generating a second bit stream; and a RS (Reed-Solomon) decoder that is operable to decode the second bit stream thereby generating a RS decoded bit stream.