Patent ID: 7663134
Filing Date: 2010-02-16
Classification: G11C,H01L

Abstract:
1. An integrated circuit structure comprising: a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug; a word-line extending in a first direction, wherein the second terminal of the transistor is connected to the word-line; a first bit-line connected to the second end and extending in a second direction perpendicular to the first direction; and a second bit-line connected to the fourth end and extending in the second direction, wherein the first resistive memory cell comprises a first top electrode connected to the first bit-line, the second resistive memory cell comprises a second top electrode connected to the second bit-line, and wherein the first and the second top electrodes have a higher resistivity than the first and the second bit-lines.