Patent ID: 6448631
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A semiconductor standard cell architecture, comprising:a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit of the semiconductor standard cell architecture; a polysilicon layer being patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture; a first dielectric layer having a first dielectric thickness disposed over the polysilicon layer; a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are disposed over the dielectric layer and is configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit within the semiconductor standard cell architecture, the plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit, wherein the local interconnect metallization layer is a higher resistivity metal having lower electromigration than aluminum; and a second dielectric layer disposed over the local interconnect metallization layer, the second dielectric layer having a second dielectric thickness that is at least equal to the first dielectric thickness.