Patent ID: 6804239
Filing Date: 2004-10-12
Classification: H04L,H04Q

Abstract:
An integrated circuit that processes communication packets, the integrated circuit comprising:co-processor circuitry comprising context buffers and data buffers and configured to receive and store one of the communication packets in one of the data buffers, correlate the one communication packet with one of a plurality of channel descriptors, associate the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor, and prevent multiple valid copies of the one channel descriptor from existing in the context buffers; the co-processor circuitry configured to track a number of the data buffers associated with the one context buffer; the co-processor circuitry configured to determine if the one channel descriptor already exists in the context buffers and is valid, and if not, to transfer the one channel descriptor from off-chip memory to the one context buffer, and if so, to not transfer the one channel descriptor from the off-chip memory; the co-processor circuitry configured to set an in-use count and a validity indicator in response to transferring the one channel descriptor from the off-chip memory to the one context buffer wherein the in-use count tracks the number of the data buffers associated with the one context buffer and the validity indicator indicates that the one channel descriptor in the one context buffer is valid; the co-processor circuitry configured to increment the in-use count if the one channel descriptor is already in the one context buffer and is valid; the co-processor circuitry configured to transfer the one communication packet from the one data buffer, and in response, to decrement the in-use count; in response to transferring the one communication packet from the one data buffer, the co-processor circuitry is configured to clear the validity indicator and transfer the one channel descriptor to the off-chip memory if none of the data buffers are associated with the one channel descriptor; and a core processor configured to execute a packet processing software application that directs the core processor to process the one communication packet in the one data buffer based on the one channel descriptor in the one context buffer.