Patent ID: 6391795
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A process for forming a composite layer of low k silicon oxide dielectric material on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon, said composite layer of low k silicon oxide dielectric material exhibiting void-free deposition properties in high aspect ratio regions between closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and without exhibiting via poisoning characteristics, comprising the steps of:a) forming over said oxide layer and said metal lines a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties in high aspect ratio regions between said closely spaced apart metal lines, until said low k silicon oxide dielectric material reaches the level of the top of said metal lines on said oxide layer; and b) forming a second layer of low k silicon oxide dielectric material over said first layer at a higher deposition rate than said first layer.