Patent ID: 6465294
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method of fabricating a MOSFET device on a semiconductor substrate, featuring a stacked gate structure comprised of a metal gate contact structure, directly overlying a polysilicon gate structure, in a region in which said polysilicon gate structure, defined on an underlying gate insulator layer, is located on a portion of an active device region of said semiconductor substrate, comprising the steps of:forming said polysilicon gate structure on said gate insulator layer, on said active device region of said semiconductor substrate; forming silicon nitride spacers on the sides of said polysilicon gate structure; forming a heavily doped source/drain region in a portion of said active device region of said semiconductor substrate not covered by said polysilicon gate structure, or by said silicon nitride spacers; forming a metal silicide layer on the top surface of said polysilicon gate structure, and on the top surface of said heavily doped source/drain region; depositing a first ILD layer, with the topology of said first ILD comprised with a raised portion in a region in which said first ILD layer overlays the top surface of said polysilicon gate structure; depositing a silicon nitride layer on said first ILD layer, resulting in a raised portion of said silicon nitride layer, in a region overlying said raised portion of said first ILD layer; performing a chemical mechanical polishing (CMP), procedure to remove said raised portion of said silicon nitride layer, and to remove said raised portion of said first ILD layer, resulting in an opening in said silicon nitride layer, exposing a portion of said first ILD layer, in a region in which said first ILD layer directly overlays the top surface of said polysilicon gate structure; depositing a second ILD layer; forming rectangular shaped, contact holes, in said second ILD layer, in said silicon nitride layer, and in said first ILD layer, exposing a portion of said heavily doped source/drain region; forming a metal gate contact trench shape, comprised of a wide diameter opening in said second ILD layer, exposing a portion of the top surface of said silicon nitride layer, and exposing said opening in said silicon nitride layer, and comprised of a narrow diameter opening in a top portion of said first ILD layer, formed using said opening in said silicon nitride layer as a mask, exposing a portion of the top surface of said polysilicon gate structure, in a region in which said polysilicon gate structure is located on said active device region of said semiconductor substrate; depositing a metal layer completely filling said rectangular shaped contact holes, and completely filling dual said metal gate contact trench shape; removing regions of said metal layer from the top surface of said second ILD layer, resulting in the formation of metal contact structures in said rectangular shaped, contact holes, and resulting in the formation of a metal gate contact structure, in said metal gate contact trench shape, resulting in said stacked gate structure, comprised of said metal gate contact structure overlying and contacting said polysilicon gate structure, in a region in which said polysilicon gate structure is located on said active device region of said semiconductor substrate; and forming lower level metal interconnect structures, with first lower level metal interconnect structure located overlying and contacting a metal contact structure, and with a second lower level metal interconnect structure overlying and contacting said stacked gate structure.