Patent ID: 6545911
Filing Date: 2003-04-08
Classification: G11C

Abstract:
A flash memory erase method that comprises a plurality of memory cells, the method comprising:performing a first erase step, which includes applying a bias Vg to a plurality of gates of the memory cells, a bias Vd to a plurality of source/drain regions of the memory cells, wherein the bias Vd is gradually increased from an initial value to a predetermined value, and no inspection step is performed while increasing the bias Vd; and inspecting whether memory of all the memory cells is erased, and performing a second erase step when the answer is no, wherein the second erase step includes at least one voltage raise erase-inspection step to insure that memory of all the memory cells has been erased; wherein an ith voltage raise erase-inspection with a duration T(i) includes a voltage raise erase step and an inspection step afterwards, and the first voltage raise erase step has a value of Vd larger than the predetermined value of Vd, and when i>1, a value of the Vd at the ith voltage raise erase-inspection step is higher than that of the (iâˆ’1)th voltage raise erase-inspection step, wherein bias Vd can be divided into m stages from the initial value to the predetermined value, wherein the value Vd(j) of Vd at the jth stage is larger than Vd(jâˆ’1) at the (jâˆ’1)th stage.