Patent ID: 7509550
Filing Date: 2009-03-24
Classification: G01R,G11C

Abstract:
1. A computer-implemented method of diagnosing faults in a circuit-under-test comprising: receiving at least one error signature comprising multiple bits, wherein the error signature represents the logical combination of a compressed test response produced by a compactor in the circuit-under-test in response to at least one applied test pattern and a fault-free version of the compressed test response, and wherein the bits of the error signature further comprise one or more error bits that indicate errors at corresponding one or more bit locations of the compressed test response; evaluating plural potential-error-bit-explaining scan cell candidates using a search tree; determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells; and providing an output of any such determined one or more failing scan cells.