Patent ID: 9140741
Filing Date: 2015-09-22
Classification: G01R,G11C

Abstract:
1. An integrated circuit chip comprising: a plurality of test input pads; a plurality of single-ended type buffers configured to receive a plurality of test input signals input to the plurality of test input pads in a connectivity test mode; a plurality of differential-type buffers configured to receive a plurality of signals input to the plurality of test input pads in a normal mode; a signal combination unit configured to combine the plurality of test input signals input through the plurality of single-ended type buffers, and to generate a plurality of test output signals; and a plurality of test output pads configured to output the plurality of test output signals in the connectivity test mode, wherein the plurality of differential-type buffers are configured to compare voltage levels of the plurality of signals input to the test input pads in a normal mode with a voltage level of a reference voltage.