Patent ID: 6700415
Filing Date: 2004-03-02
Classification: G11C

Abstract:
A sense amplifier comprising:a) a sense amp input node for receiving a data signal from a bitline of a memory cell; b) an output node for producing a sense amplifier output signal; and c) a latch circuit for latching the sense amplifier output signal having: i) an enable signal input node for receiving an enable signal; ii) a sensing circuit electrically coupled between the sense amp input node and the output node and also electrically coupled to the enable signal input node, the sensing circuit having a sensing circuit input to receive the data signal from a sense latch node and receiving the enable signal from the enable signal input node and producing a sensing circuit output signal indirectly coupled to the output node producing the sense amplifier output signal, the sensing circuit including a first inverter and a second inverter connected in parallel, an input of the first inverter being electrically connected to the sense latch node and an output of the second inverter being electrically connected to the output node; iii) a first feedback path including a first feedback transistor electrically connected to the output of the second inverter and the sense latch node; and iv) a second feedback path including a second feedback transistor and a third feedback transistor connected in series, the second feedback transistor having a gate terminal connected to the output of the second inverter, having a drain terminal connected to the first feedback transistor and having a source terminal connected to the third feedback transistor, the third feedback transistor being connected to the sense latch node and receiving a boost enable signal at a gate terminal.