Patent ID: 7973344
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A process for making a double gate structure for a Junction Field Effect Transistor, comprising: A) thermally growing a layer of silicon dioxide (pad oxide) on a silicon substrate; B) depositing a layer of silicon nitride over said silicon dioxide layer; C) forming in said silicon substrate, so as to define the perimeter of an active area, a Shallow Trench Isolation trench (STI trench) filled with silicon dioxide deposited by chemical vapor deposition (CVD oxide) at least a portion of which has been densified so that said silicon dioxide is stressed at the edges of said STI trench, and polishing said CVD oxide back to flush with the top of said nitride layer; D) removing said nitride layer; E) etching away said layer of silicon dioxide (pad oxide) with a silicon dioxide etch process that also etches said stressed silicon dioxide at the edges of said STI trench to form divots; F) forming a doped channel region in a well of opposite conductivity in said active area so as to form a back gate PN junction; said divots being at least deep enough that any conductive material in said divots will be in electrical contact with said well; G) forming a doped channel region in a well of opposite conductivity in said active area so as to form a back gate PN junction; H) depositing a layer of polysilicon over the whole structure so as to cover said active area and fill said divots around the perimeter of said active area; I) selectively doping portions of said polysilicon layer with appropriate conductivity enhancing impurities in a location where a gate surface contact is to be formed; and J) patterning and anisotropically etching said polysilicon layer so as to form a polysilicon gate surface contact with a doped polysilicon stringer under said polysilicon gate surface contact at the intersection of said polysilicon gate contact and said perimeter of said active area.