Patent ID: 8102195
Filing Date: 2012-01-24
Classification: H03L

Abstract:
1. A digital phase locked loop circuit comprising: a reference clock generator for providing a reference clock signal; a digital filter for providing filtered digital codes; a digital controlled oscillator coupled to the digital filter to receive the filtered digital codes and provide an output signal; a frequency divider coupled to receive the output signal and provide a frequency divided signal; and a phase delay quantizer coupled to the frequency divider, reference clock generator and digital filter; the phase delay quantizer operable to quantize a phase delay and between the reference clock signal and the frequency divided and to provide digital codes to the digital filter based upon signals from the frequency divider and the reference clock generator, wherein the phase delay quantizer quantizes the phase delay between the reference clock and the divided frequency signals without the use of oversampling, wherein the phase delay quantizer comprises a plurality of interpolated delay stages, wherein an interpolated delay chain in the phase delay quantizer forms a circular ring so that the delay stages can be reused.