Patent ID: 8423938
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A wire-spacing verification method for a computer, the method comprising: calculating, by one or more processors of the computer, a characteristic impedance of each wire model disposed in a substrate model based on a propagation rate of a signal in the wire model and rise time or fall time of an element model for transmitting the signal; calculating, by the one or more processors of the computer, a reference impedance for predetermined sections of the wire model; creating, by the one or more processors of the computer, a distribution map in a direction of a section length with respect to the characteristic impedance of each of the sections for which the reference impedance is calculated; calculating, by the one or more processors of the computer, an index indicating a degree of mismatch with the reference impedance based on the created distribution map; and making, by the one or more processors of the computer, an approval/denial determination on the wire model based on the index.