Patent ID: 6011709
Filing Date: 2000-01-04
Classification: G06F,G11C

Abstract:
In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, at least one row of cache cells coupled to respective column data lines, and a data bus, a method of executing a cache replace cycle, comprising the steps of:receiving a row address not corresponding to data not stored in any of said cache cells;selecting a row of cache cells;transferring data from said row of cache cells to said write buffers, with amplification by said sense amplifiers;transferring data from said memory cells via said sense lines to said column data lines and said row of cache cells, with amplification by said sense amplifiers;disconnecting said column data lines from said sense lines;receiving at least one column address and transferring data between corresponding column data lines and said data bus; andtransferring data from said write buffers to said memory cells, with amplification by said sense amplifiers.