Patent ID: 7161204
Filing Date: 2007-01-09
Classification: H01L

Abstract:
1. An array of capacitors for dynamic random access memory (DRAM) devices comprised of: a substrate having partially completed device areas for said DRAM devices; a first insulating layer having first openings to said substrate; capacitor node contact plugs in said first openings; a second insulating layer with second openings aligned over and to said node contact plugs, and capacitor bottom electrodes in said second openings; wherein, as viewed from top of the array of capacitors, each of the capacitor bottom electrodes comprises outer surfaces interdigitated with corner portions, each electrode being generally diagonally aligned with at least one other electrode, the second insulating layer extends between the outer surfaces of each adjacent pair of electrodes, and corner portions of each diagonally aligned pair of electrodes face each other across a space disposed between the diagonally aligned pair of electrodes and unobstructed by the second insulation layer; and an interelectrode dielectric layer on said bottom electrodes, and capacitor top electrodes on the interelectrode dielectric layer.