Patent ID: 7424508
Filing Date: 2008-09-09
Classification: G06F

Abstract:
1. A carry look-ahead adder comprising: a carry generation circuit, organized into M blocks, arranged to perform first logic combinations on an N-bit addend and an N-bit augend, which results in carry propagation bit values and carry kill bit values, respectively, where M and N are positive integers and M<N; a block carry circuit arranged to perform second logic combinations on the carry kill bit values, and to perform third logic operations and fourth logic operations on the propagation bit values and the carry kill values, a bit carry circuit, having a Manchester carry chain configuration, to perform a fifth logic combination on the carry propagation bit values and the carry kill bit values which results in first bit carry signals for a case where a block carry exists in each of the M blocks and results in second carry bit signals for a case where no block carry exists; a control circuit to generate selection-control signals based upon the block carry signals, generation of the selection-control signals not logically being controlled by clock signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals, to add the carry propagation bit values and the selected carry signals and accordingly to output a final sum result.