Patent ID: 6406971
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A fabrication method for an embedded direct random access memory (DRAM), comprising:providing a substrate which has been divided into a memory cell region and a periphery circuit region, wherein the periphery circuit region further comprises a P type metal oxide semiconductor (PMOS) region and an NMOS region; forming a plurality of MOS, each comprising a gate and a source/drain region, on the substrate of the memory cell region and periphery circuit region; forming a barrier layer over the substrate to cover a designated region in which a self-aligned silicide is not formed, wherein the region comprises at least portions of the PMOS and NMOS regions in the memory cell and periphery circuit regions; performing a self-aligned silicide fabrication step to form a metal silicide on the area outside the region in which the self-aligned silicide is not formed; forming a first dielectric layer over the substrate that covers the memory cell region and the periphery circuit region; forming at least a first landing pad and at least a second landing pad in the dielectric layer of the memory cell region, wherein the first and second landing pads are electrically connected to the source/drain region of the memory cell; forming a second dielectric layer over the substrate that covers the first dielectric layer and the first and second landing pads; forming a bit-line contact opening in the second dielectric layer of the memory cell region, and a first contact opening in the first and second dielectric layers of the NMOS region, wherein the bit-line contact opening exposes the first landing pad and the first contact opening exposes the NMOS; performing an N-type ion implantation step to implant N-type ions into the first landing pad and the MOS in the NMOS region, exposed by the bit-line contact opening and the first contact opening; forming a first bit-line contact and a first contact in the bit-line contact opening and the first contact opening; forming a bit-line above the substrate, wherein the bit line is electrically connected to the bit-line contact; forming a third dielectric layer above the substrate; forming a storage node contact opening in the third and second dielectric layers of the memory cell region and forming a second contact opening in the third, the second and the first dielectric layers of the PMOS region, wherein the storage node contact opening exposes the landing pad and the second contact opening exposes the MOS of the PMOS region; performing a P-type ion implantation step to implant P-type ions into the second landing pad and the MOS in the PMOS region, exposed by the storage node contact opening and the second contact opening; forming a storage node contact and a second contact in the storage node contact opening and the second contact opening; and forming a capacitor above the substrate that is electrically connected to the node contact.