Patent ID: 6122653
Filing Date: 2000-09-19
Classification: G06T

Abstract:
A block IIR processor comprising a first input register storing data of the block length ""L"" and capable of shifting the stored data by an integer times a data word length, a first coefficient register file, a second input register, a second coefficient register file, a third input register, a third coefficient register file, a register, a shift register, an accumulator and a multiply-and-accumulate unit for multiplying respective data blocks in the register by a least significant word in the shift register, and for adding the result of the multiplication to a value of the accumulator, for executing a parallel operation of ""L"" multiply-and-accumulate operations,wherein input data of the block size ""L"" is stored in the first input register, and a content of the fist input register is transferred to the shift register, and while shifting rightward the content of the shifter register one data word length by one data word length, values of a respective register in the first coefficient register file, corresponding to a column, all values in which are not 0 (zero), are transferred to the register, so that a parallel multiply-and-accumulate operation is executed a plurality of times in the multiply-and-accumulate operation unit, with the result that a first matrix vector multiplication is executed, and then, the result of the multiplication is accumulated in the accumulator,wherein a content of the second input register is transferred to the shift register, and while shifting rightward the content of the shifter register one data word length by one data word length, values of a respective register in the second coefficient register file, corresponding to a column, all values in which are not 0 (zero), are transferred to the register, so that a parallel multiply-and-accumulate operation is executed a plurality of times in the multiply-and-accumulate operation unit, with the result that a second matrix vector multiplication is executed, and then, the result of the multiplication is accumulated in the accumulator,wherein a content of the third input register is transferred to the shift register, and while shifting rightward the content of the shifter register one data word length by one data word length, values of a respective register in the third coefficient register file, corresponding to a column, all values in which are not 0 (zero), are transferred to the register, so that a parallel multiply-and-accumulate operation is executed a plurality of times in the multiply-and-accumulate operation unit, with the result that a third matrix vector multiplication is executed, and then, the result of the multiplication is accumulated in the accumulator, andwherein the value of the accumulator is stored in the third input register, and is outputted as a filter output, and the value of the first input register is stored in the second input register.