Patent ID: 6721848
Filing Date: 2004-04-13
Classification: G06F

Abstract:
A mechanism to translate from a virtual bus to a physical interconnect, comprising:a plurality of processors; a plurality of local caches, each local cache corresponding to one of the plurality of processors, wherein the plurality of processors and the local caches are coupled to one or more virtual buses; one or more intermediary inclusive caches (IIC), one of the IICs coupled to one of the one or more virtual buses and each of the IICs coupled to the physical interconnect, wherein each of the IICs includes a memory array, the memory array storing one or more memory lines from the main memory, and storing, for each memory line, an address tag, data, and virtual address bits and wherein the IIC additionally stores a pre-fetched memory line, the pre-fetched memory line including the address tag and the data, and further including a pre-fetch status bit, wherein the pre-fetch status bit includes an ON and an OFF indication, and wherein the pre-fetch status bit is switched to an OFF state when a virtual address for the pre-fetched memory line is presented on a virtual bus coupled to the IIC; and a main memory coupled to the physical interconnect.