Patent ID: 6728869
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A computation engine, comprising:an operation unit operable to receive a first operand and a second operand, wherein the operation unit combines the first operand and the second operand to produce a result; a memory operably coupled to the operation unit and operable to receive a destination address and source address information, wherein the memory stores the result produced by the operation unit at the destination address, wherein the memory has a memory latency, wherein the memory generates memory source data in response to the source address information; a first memory bypass register operably coupled to the operation unit, wherein during a clock cycle subsequent to a clock cycle within which the result is generated by the operation unit, the first memory bypass register stores the result to produce a first stored result, wherein the first stored result is a time-delayed version of the result produced by the operation unit; and a selection block operably coupled to the operation unit, the memory, and the first memory bypass register, wherein the selection block selects the second operand provided to the operation unit based on selection information received, wherein the second operand is selected from a set of potential operands that include the first stored result and the memory source data.