Patent ID: 7755942
Filing Date: 2010-07-13
Classification: G11C

Abstract:
1. A memory cell array, comprising: a plurality of memory cells disposed in columns and in rows, each memory cell including a transistor having a gate, a source and a drain; a plurality of word lines extending in the row direction, wherein the gates of transistors in the memory cells disposed in each row are commonly connected to one of the word lines; a plurality of sub bit lines extending in the column direction, wherein the sources of the transistors in the memory cells disposed in a first column and the drains of the transistors in the memory cells disposed in a second column, which is adjacent to the first column, are commonly connected to one of the sub bit lines; a main bit line; and a plurality of transistor pairs each having a source selector and a drain selector, wherein the word lines are sandwiched between the transistor pairs, and wherein one of the transistors in each transistor pair has a terminal that is directly connected to the main bit line.