Patent ID: 6215337
Filing Date: 2001-04-10
Classification: G11C,H03K

Abstract:
A switch comprising:an n-channel FET having an n-channel width; anda p-channel FET having a p-channel width;wherein a source node of said p-channel FET is coupled to a drain node of said n-channel FET and a drain node of said p-channel FET is coupled to a source node of said n-channel FET and a gate node of said p-channel FET and a gate node of said n-channel FET are configured to be coupled to complementary clock signals;wherein said complementary clock signals operate at a lower frequency than a center frequency of a band-limited signal applied to a first terminal of said switch; andwherein said p-channel width is larger than said n-channel width in order to increase the linearity of said switch.