Patent ID: 9058901
Filing Date: 2015-06-16
Classification: G01R,G11C

Abstract:
1. A semiconductor apparatus comprising: a receiver configured to receive a plurality of input signals; a signal processing unit configured to process the plurality of input signals received by the receiver and output the processed signals as a plurality of internal signals, respectively; a multiplexer (MUX) unit configured to selectively output the plurality of internal signals or a test input data and a plurality of latch signals, as the plurality of MUX output signals, in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in synchronization with a latch clock signal, respectively; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal, wherein the MUX unit comprises: a first MUX configured to receive a first internal signal and the test input data, and select one of the first internal signal and the test input data in response to the input/output select signal as a first MUX output signal, a second MUX configured to receive a second internal signal being different from the first internal signal and the first MUX output signal, and select one of the second internal signal and the first MUX output signal as a second MUX output signals, and a third MUX configured to receive a third internal signal being different from the first and second internal signals and the second MUX output signal, and select one of the third internal signal and the second MUX output signal as a third MUX output signals.