Patent ID: 6654308
Filing Date: 2003-11-25
Classification: G11C

Abstract:
A memory having N write ports, wherein N is greater than 2, comprising:a first data memory unit having a plurality of storage locations addressable by a range of addresses, and having less than N write ports; a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory unit having less than N write ports; and a control unit configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range, the control unit including multiple control memory units each having less than N write ports, wherein one of the multiple control memory units has first and second write ports and is configured such that a first value is written through the first write port when a predetermined write port associated with the first data memory unit is used to write, and such that a second value is written through the second write port when another predetermined write port associated with the second data memory unit is used to write, and wherein the first and second values are determined independently of data read from a control memory unit.