Patent ID: 6072732
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A memory, comprising:a write driver generating data on a pair of write bit lines;a memory cell having a pair of bit lines, wherein each memory cell bit line is selectively connected to a corresponding one of the write bit lines through a first resistive element;a reset circuit connected to the write bit lines and operable to generate a reset signal for resetting the memory in preparation for a next memory operation in response to a detected write bit line data transitions indicative of the occurrence of a write operation to the memory cell; anda delay mimic circuit connected to the write bit lines between the write driver and the reset circuit, the delay mimic circuit introducing a delaying effect on the passage of write bit line data prior to processing by the reset circuit that substantially corresponds to a delaying effect on the passage of write bit line data due to driving the memory cell bit lines through the first resistive element.