Patent ID: 7526023
Filing Date: 2009-04-28
Classification: H04L

Abstract:
1. Clock-data recovery circuitry for a programmable logic device, said clock-data recovery circuitry being associated with an interface channel of said programmable logic device and being subject to cross-talk from at least one signal source on said programmable logic device separate from said interface channel, said clock-data recovery circuitry comprising: a loop circuit having an input and a plurality of output taps, wherein (a) signals on both said input and said output taps are derived from said interface channel, and (b) the loop circuit at a given time uses fewer than said plurality of output taps; a respective decision-feedback equalizer circuit accepting a respective output signal from each of at least one of said output taps, each said respective decision-feedback equalizer circuit having a programmable coefficient, and output of each said decision-feedback equalizer circuit being fed back to said input of said loop circuit; at least one respective programmable selector between at least one respective one of said output taps and one said respective decision-feedback equalizer circuit, for programmably selecting between said output tap and said at least one signal source separate from said interface channel; wherein: when said at least one respective one of said output taps is unused, said at least one signal source separate from said interface channel is programmably selected and applied to said respective decision-feedback equalizer circuit; and said programmable coefficient is adjusted to minimize cross-talk from said one of said at least one signal source separate from said interface channel.