Patent ID: 6225225
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A method of forming shallow trench isolation in the fabrication of an integrated circuit device comprising:providing a pad oxide layer overlying a silicon substrate;depositing a polishing stop layer overlying said pad oxide layer;patterning said polishing stop layer, said pad oxide layer, and said silicon substrate to form shallow trenches;depositing a trench oxide layer overlying said polishing stop layer and completely filling said shallow trenches;polishing down said trench oxide layer to the top surfaces of said polishing stop layer;etching down said trench oxide layer to a level below that of said pad oxide layer;thereafter depositing a silicon nitride layer overlying said polishing stop layer and said trench oxide layer;depositing a polishing layer overlying said silicon nitride layer;polishing down said polishing layer and said silicon nitride layer to said top surfaces of said polishing stop layer wherein said polishing layer protects said silicon nitride layer overlying said trench oxide layer and on sidewalls of said polishing layer from said polishing down;etching away said polishing stop layer;etching away said silicon nitride sidewalls; andetching away said polishing layer and said pad oxide layer where said silicon nitride layer overlying said trench oxide layer acts as an etching stop and protects underlying said trench oxide layer to complete said formation of said shallow trench isolation in the fabrication of said integrated circuit device.