Patent ID: 8760912
Filing Date: 2014-06-24
Classification: G11C,H03K

Abstract:
1. A circuit comprising: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first node, a second node, a third node, and a fourth node, wherein: a drain of the first NMOS transistor and a drain of the first PMOS transistor are electrically connected to the third node; a drain of the second NMOS transistor and a drain of the second PMOS transistor are electrically connected to the first node; a drain of the third NMOS transistor and a drain of the third PMOS transistor are electrically connected to the fourth node; a drain of the fourth NMOS transistor and a drain of the fourth PMOS transistor are electrically connected to the second node; a gate of the first NMOS transistor and a gate of the first PMOS transistor are electrically connected to the second node; a gate of the second NMOS transistor and a gate of the second PMOS transistor are electrically connected to the fourth node; a gate of the third NMOS transistor and a gate of the third PMOS transistor are electrically connected to the first node; a gate of the fourth NMOS transistor and a gate of the fourth PMOS transistor are electrically connected to the third node; a source of the second NMOS transistor and a source of the second PMOS transistor are electrically connected to the third node; and a source of the fourth NMOS transistor and a source of the fourth NMOS transistor are electrically connected to the fourth node.