Patent ID: 6023426
Filing Date: 2000-02-08
Classification: G11C

Abstract:
In a semiconductor integrated circuit memory device having a correction structure for performing a correction operation on overerased memory cells in the memory device after erase, said correction structure comprising, in combination:a cell matrix having a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting said rows of word line, each of said memory cells including a floating gate array transistor having its control gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source and substrate connected to a ground potential;means for applying first positive pulse voltages to each word line in a first timed sequence on a word line by word line basis;means for simultaneously applying a second positive pulse voltage to each bit line in a second timed sequence on a bit line by bit line basis when said first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied;said first positive pulse voltages each having a magnitude of approximately +5.0 volts; andsaid second positive pulse voltages each having a magnitude of approximately +4.5 volts.