Patent ID: 6044020
Filing Date: 2000-03-28
Classification: G11C

Abstract:
An erasable programmable nonvolatile semiconductor memory device comprising:a memory cell array having a plurality of memory blocks each divided into a plurality of segments, wherein each of the segments has a plurality of word lines, a plurality of bit lines arranged to intersect the word lines, and a plurality of memory cells connected to the word lines and the bit lines;means for decoding segment select signals to generate a decode signal that selects one of the segments, said means for decoding being connected to a first power node and a second power node;a plurality of level shifters, each connected to the first power node, said plurality of level shifters for receiving word line select signals, said word line select signals for selecting one of the word lines in the selected segment, said plurality of level shifters for outputting a first voltage upon said selection of said one of the word lines; andmeans connected to the first power node and a second power node, for applying the first voltage to a word line driver of the selected word line during read, write, and test modes of operation, and for applying a second voltage supplied from the second power node to the word line driver of the selected word line during an erase mode of operation, in response to the decoded signal from the means for decoding.