Patent ID: 8330530
Filing Date: 2012-12-11
Classification: G05F,H01L,H02M,H03F,H03G,H03H,H03K,H04B

Abstract:
1. An apparatus for disabling a bias voltage for biasing one or more switches, the apparatus comprising: a first complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well, the well having a p-type doping, and the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier; a well bias control block for biasing the well voltage of the first switch, the well bias control block configured to bias the well voltage of the first switch to at least two voltage levels; and a disable circuit configured to disable the well bias control block during initialization of the power amplifier so as to prevent the well bias control block from biasing the well, the disable circuit further configured to enable the well bias control block after initialization of the power amplifier.