Patent ID: 6173351
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A bridge for a multi-processor system, the bridge comprising a first processor bus interface for connection to a first I/O bus for a first processing set, a second processor bus interface for connection to a second I/O bus for a second processing set, a device bus interface for connection to a device bus and a bridge control mechanism configured to be operable:in a combined, lockstep mode, to monitor lockstep operation of the first and second processing sets by monitoring signals on the first and second I/O buses and to detect a difference between the monitored signals as being indicative of an occurrence of a lockstep error; andin a split mode, following the occurrence of the lockstep error, to arbitrate between the first and second processing sets for access to the device bus pending re-establishment of an equivalent state in the processing sets for restarting the combined mode.