Patent ID: 7042033
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. An MOS transistor formed on a semiconductor substrate of a first conductivity type comprising: (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer formed on the interfacial layer that comprises a material that is selected from the group consisting of Ta (c) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer; (d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface; (e) a source and drain regions of a second conductivity type; (f) a pair of first non-conductive spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer; and (g) a pair of second non-conductive spacers that are adjacent to the first spacers and the high dielectric constant layer and are formed on the interfacial layer.