Patent ID: 6157973
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A microcomputer formed on a chip, comprising:a data input/output pad;bus interface circuitry connected to said data input/output pad through a first bus for making an interface for inputting and outputting an information signal through said data input/output pad;a first memory connected with said bus interface circuitry through a second bus for performing transfer of an information signal including data and an instruction with said bus interface circuitry;first bidirectional transfer circuitry with a latch function of latching an applied signal, and connected to said first memory through a third bus for bidirectionally transferring at least data with said first memory;second bidirectional transfer circuitry with a latch function of latching an applied signal, and connected with said first bidirectional transfer circuitry through a fourth bus for transferring at least data bidirectionally at least with said first bidirectional transfer circuitry;a second memory connected with said second bidirectional transfer circuitry through a fifth bus for performing transfer of an information signal with said second bidirectional transfer circuitry; andprocessor circuitry connected with said second bidirectional transfer circuitry through a sixth bus for performing transfer of an information signal with said second bidirectional transfer circuitry, executing an instruction included in the information signal and transmitting data of a result of execution to said sixth bus.