Patent ID: 8383448
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A method of fabricating a metal oxide semiconductor (MOS) device, comprising: providing a substrate comprising a complementary metal oxide semiconductor (CMOS) image sensor region and a non-CMOS image sensor region; forming a plurality of gates and source/drain regions of transistors on the substrate; forming a photodiode doped region in the CMOS image sensor region; forming a floating node doped region in the CMOS image sensor region; forming a spacer stacked layer covering the gate of each of the transistors on the substrate, the spacer stacked layer at least comprising a bottom layer, an inter-layer, and a top layer from bottom to top; forming a first mask layer on the substrate, the first mask layer having an opening exposing at least the photodiode doped region of the CMOS image sensor region, the opening being extended to a part of the transistor adjacent to the photodiode doped region; performing a removing process through the first mask to remove the top layer and the inter-layer exposed by the opening, thereby to allow the bottom layer to be exposed by the opening; removing the first mask layer; forming a second mask layer on a region correspondingly exposed by the opening, thereby the second mask layer covering the bottom layer exposed by the opening; removing a portion of the top layer and the inter-layer exposed by the second mask layer so as to form a spacer on a sidewall of the gate of each of the transistors exposed by the second mask; removing the second mask layer; forming a salicide block (SAB) layer on the substrate and removing a portion of the top layer, the inter-layer, and the bottom layer with use of the SAB layer as an etching mask so as to expose a plurality of predetermined regions; and forming a metal silicide layer on each of the predetermined regions.