Patent ID: 6858902
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A semiconductor device for protecting an integrated circuit input/output pad against ESD events, comprising: a substrate of a first conductivity type, said substrate having a resistivity; a multi-finger MOS transistor in said substrate, said MOS transistor comprising a source region, connected to ground potential, a gate region, connected to ground potential, and a drain region, connected to said pad; a well of the opposite conductivity type in said substrate, said well positioned in close proximity to said transistor regions; an interdigitated diode in said well, said diode having a plurality of anode regions of said first conductivity type, connected to said pad and said drain, and a plurality of cathode regions of said opposite conductivity type, connected to power; each transistor region aligned with a corresponding diode region such that said diode-anode regions are positioned at a close proximity to said source regions, and said diode-cathode regions positioned at said close proximity to said drain regions; each of said transistor and diode regions, respectively, coupled by said proximity and said connections, creating a localized parasitic silicon-controlled rectifier (SCR) comprising an SCR-anode formed by said diode-anode, a first base region formed by said well, a second base region formed by said substrate, and an SCR-cathode formed by said transistor source, said SCR operable to distribute an ESD current at low voltage.