Patent ID: 7923327
Filing Date: 2011-04-12
Classification: H01L

Abstract:
1. A method of fabricating a non-volatile memory device, the method comprising: forming an oxide layer and a nitride layer on a semiconductor substrate; forming a first nitride layer pattern by selectively etching the nitride layer; doping the semiconductor substrate with first impurities using the first nitride layer pattern as a mask to form an electron injection region; forming a partial oxide layer pattern thicker than the oxide layer by oxidizing the electron injection region; forming a second nitride layer pattern by selectively etching the first nitride layer pattern; etching the semiconductor substrate using the second nitride layer pattern and the partial oxide layer pattern as a mask to form a trench around the electron injection region; forming a device isolation layer pattern by gap-filling the trench with a dielectric and then removing the second nitride layer pattern; forming a control gate region by selectively implanting the semiconductor substrate with second impurities; selectively etching the partial oxide layer pattern and a portion of the device isolation layer pattern to expose a top surface and a side surface of the electron injection region; forming a first tunnel oxide layer and a second tunnel oxide layer by re-oxidizing an entire surface of the semiconductor substrate, the first tunnel oxide layer being on the control gate region, the second tunnel oxide layer being on the top surface and the side surface of the electron injection region; and forming a floating gate electrode covering at least a portion of the control gate region and an edge of the electron injection region, wherein the top surface of the electron injection region has an area concavely depressed, and wherein a portion of the floating gate is disposed in the concavely depressed area of the electron injection region.