Patent ID: 8891688
Filing Date: 2014-11-18
Classification: H04B,H04L

Abstract:
1. A receiver circuit receiving a receiver signal of a differential binary phase shift keying, the receiver circuit comprising: a delayed correlation computing unit which carries out a delayed correlation computation that determines a correlation value correlated to a sampling value before one symbol period, with regard to each of sampling values of the receiver signal; a capture unit which captures a synchronous timing of the receiver signal, on the basis of the correlation value calculated by the delayed correlation computing unit; a decoding unit which decodes the receiver signal in use of the captured synchronous timing as a reference in a case where the synchronous timing of the receiver signal is captured by the capture unit; and a no signal period detecting unit which detects a no signal period which does not receive the receiver signal, wherein the capture unit cancels the capture of the synchronous timing in a case where the no signal period is detected by the no signal period detecting unit; and a data processing unit which detects on the basis of a decoded data which is decoded by the decoding unit whether or not an error bit and an end timing of the receiver signal are included, wherein the capture unit cancels the capture of the synchronous timing in the case where inclusion of the end timing and the error bit is detected by the data processing unit.