Patent ID: 6353333
Filing Date: 2002-03-05
Classification: H03K

Abstract:
An interface circuit that operates in response to a positive supply voltage and a ground supply voltage, the interface circuit comprising:an input/output (I/O) pin for providing a connection to an external circuit; an output buffer coupled to the I/O pin, the output buffer comprising a PMOS pullup transistor, an NMOS pulldown transistor, and a NMOS isolation transistor, the PMOS pullup transistor being coupled between the positive supply voltage and the I/O pin, the NMOS isolation transistor being coupled between the I/O pin and the NMOS pulldown transistor and being gate-coupled to the positive supply voltage, and the NMOS pulldown transistor being coupled between the NMOS isolation transistor and the ground supply voltage; an impedance control circuit connected to the output buffer, the impedance control circuit being coupled to receive a tristate signal and a data out signal, the impedance control circuit enabling one of the PMOS pullup transistor and the NMOS pulldown transistor and disabling the other one of the PMOS pullup transistor and the NMOS pulldown transistor when the tristate signal is at a first state, and the impedance control circuit disabling the PMOS pullup transistor and the NMOS pulldown transistor when the tristate signal is at a second state; an isolation circuit coupled between the output buffer and the I/O pin, the isolation circuit comprising: a first PMOS transistor connected between the positive supply voltage and the body of the PMOS pullup transistor, the body of the first PMOS transistor being connected to the body of the PMOS pullup transistor and the gate of the first PMOS transistor being connected to the I/O pin; a second PMOS transistor connected between the positive supply voltage and the body of the PMOS pullup transistor, the body and the gate of the second PMOS transistor being connected to the body of the PMOS pullup transistor; a third PMOS transistor connected between the body of the PMOS pullup transistor and the I/O pin, the body of the third PMOS transistor being connected to the body of the PMOS pullup transistor, and the gate of the third PMOS transistor being connected to the positive supply voltage; and a fourth PMOS transistor connected between the body of the PMOS pullup transistor and the I/O pin, the body and the gate of the fourth PMOS transistor being connected to the body of the PMOS pullup transistor; and a pullup protection circuit coupled between the impedance control circuit and the output buffer, the pullup protection circuit comprising: an NMOS pass transistor connected between the impedance control circuit and the gate of the PMOS pullup transistor, the gate of the NMOS pass transistor being coupled to the positive supply voltage; a fifth PMOS transistor connected between the positive supply voltage and the gate of the PMOS pullup transistor, the body of the fifth PMOS transistor being connected to the body of the PMOS pullup transistor, and the gate of the fifth PMOS transistor being connected to the I/O pin; and a sixth PMOS transistor connected between the body and the gate of the PMOS pullup transistor, the body of the sixth PMOS transistor being connected to the body of the PMOS pullup transistor, and the gate of the sixth PMOS transistor being coupled to the positive supply voltage.