Patent ID: 7302664
Filing Date: 2007-11-27
Classification: G06F

Abstract:
1. A method, in a data processing system, for decoupling capacitor insertion in a circuit design, comprising: obtaining circuit data, wherein the circuit data identifies characteristics of the circuit design; partitioning the circuit design into one or more cells based on the circuit data; determining a voltage noise map for each cell of the one or more cells; applying a required capacitance mapping function to the voltage noise map for each cell of the one or more cells to identify a required capacitance for each cell of the one or more cells; inserting one or more decoupling capacitors into at least one cell of the one or more cells based on the required capacitance for the at least one cell; and outputting a new voltage noise map including the one or more decoupling capacitors inserted into the at least one cell, wherein the required capacitance mapping function is: 0 for abs(u(x,y)−alpha)<threshold, where c(x,y) is a capacitance for the cell location on the integrated circuit given by arid coordinates x and y, u(x,y) is a voltage noise at the cell located at grid coordinates x and y, alpha is a noise value, beta is a mapping function characteristic value, and gamma is a translation parameter for converting local noise into a capacitance value.