Patent ID: 6847543
Filing Date: 2005-01-25
Classification: G11C

Abstract:
1. A method for driving a non-volatile memory circuit comprising: a first inverter which comprises a first transistor and a second transistor each having a gate and a drain, the gates of said first and second transistors being connected to each other, and the drains of said first and second transistors being connected to each other with a first node therebetween; a second inverter which comprises a third transistor and a fourth transistor each having a gate and a drain, the gates of said third and fourth transistors being connected to each other, and the drains of said third and fourth transistors being connected to each other with a second node therebetween; a fifth transistor which comprises a gate and is connected between a first bit line and said first node, said gate being connected to a word line; and a sixth transistor which comprises a gate and is connected between a second bit line and said second node, said gate being connected to said word line; said first node being connected to the gate of said third transistor and to the gate of said fourth transistor; said second node being connected to the gate of said first transistor and to the gate of said second transistor; the source of said first transistor and the source of said third transistor being connected to a ground line; the source of said second transistor and the source of said fourth transistor being connected to a power line; the circuit further being provided with a first resistor element and a second resistor element whose resistance values can be electrically modified; the positional relationship of said first resistor element and said second resistor element being selected from the following first to fourth positional relationships: a first positional relationship in which said first resistor element is connected between the source of said first transistor and said ground line, and said second resistor element is connected between the source of said third transistor and said ground line; a second positional relationship in which said first resistor element is connected between the source of said second transistor and said power line, and said second resistor element is connected between the source of said fourth transistor and said power line; a third positional relationship in which said first resistor element is connected between said first node and the drain of said first transistor, and said second resistor element is connected between said second node and the drain of said third transistor; and a fourth positional relationship in which said first resistor element is connected between said first node and the drain of said second transistor, and said second resistor element is connected between said second node and the drain of said fourth transistor; the method comprising: