Patent ID: 8635515
Filing Date: 2014-01-21
Classification: H03M

Abstract:
1. An encoder apparatus comprising: a receive module that receives a data stream, said data stream including a plurality of parity data blocks each having a first length and a plurality of user data blocks each having a second length greater than said first length; a parity generation module that generates a plurality of parity bits based on said data stream and a codeword; and a parity insertion module that combines said plurality of parity bits and said data stream to generate encoded bits; wherein: a placeholder insertion module inserts placeholders for parity bits in each of said parity data blocks to bring the length of each of said parity data blocks to said second length; an error-correcting encoder module generates error-correcting parity bits from said data stream after insertion of said placeholders; an interleaver module interleaves said error-correcting parity bits in said data stream; a first encoder module processes syndrome bits of said user data blocks to generate first coded bits to replace said placeholders in said parity data blocks; and parity data blocks containing said interleaved error-correcting parity bits are processed with said user data blocks by said first encoder module to generate second coded bits for other of said parity blocks not containing said interleaved error-correcting parity bits.