Patent ID: 8582597
Filing Date: 2013-11-12
Classification: H04Q

Abstract:
1. A time slot interchanger comprising: a time slot interchange circuit coupled with channels and configured to interchange time slots of channel signals included in a multiplexed transmission signal; an address control memory circuit to generate write addresses and read addresses for interchanging the time slots, the write addresses and the read addresses being notified to the time slot interchange circuit; and a channel-setting data processing circuit to receive alarm data and channel-setting data indicating the time slots to which the channel signals constituting the multiplexed transmission signal are allocated, and process the channel-setting data in accordance with the alarm data, and wherein the channel-setting data processing circuit includes: wherein the write address and read address are generated based on the channel-setting data stored in the second memory circuit, and the first transmission capacity is 1/n of the second transmission capacity, wherein n is an integer and the alarm data for processing the channel-setting data of said all channels is processed by implementing processing repeated n times, and wherein the alarm data includes control bits usable to switch transmission data from a work bandwidth to a protection bandwidth in response to an alarm, the control bits for each channel settable to a logic value of “0” when work bandwidths are selected and a logic value of “1” when protection bandwidths are selected.