Patent ID: 7010741
Filing Date: 2006-03-07
Classification: G06F,G11C

Abstract:
1. A circuit for detecting and correcting errors in an array of content addressable memory (CAM) cells coupled to wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching data in the CAM cells, said circuit comprising: (a) at least one row parity CAM cell per row of said array, said row parity CAM cell being coupled to the matchline of an associated row, said row parity CAM cell storing a value representing a panty of a predefined portion of an associated row; (b) at least one column parity CAM cell per column of said array, said column parity CAM cell being coupled to the bitline of an associated column, said column parity CAM cell storing a value representing a parity of a predefined portion of an associated column; (c) a control circuit for reading, writing, and searching data stored in the CAM cells in said array; and (d) a parity check circuit for comparing a calculated parity of said predefined portion of data read from a row of said array with data from said associated row parity CAM cell, wherein if said calculated parity and said stored parity data do not match, said parity check circuit compares a calculated parity of each column with data from associated column parity CAM cells, until a mismatch is determined, thereby identifying said error, said parity circuit inverting data stored at an intersection of said row and said column mismatches.