Patent ID: 7576386
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A non-volatile memory cell comprising: a silicon substrate having a main surface; a source region in a portion of the silicon substrate proximate the main surface; a drain region in a portion of the silicon substrate proximate the main surface, the drain region being spaced apart from the source region; a well region disposed in a portion of the silicon substrate proximate the main surface between the source region and the drain region; a bottom oxide layer formed on the main surface of the substrate, the bottom oxide layer disposed on a portion of the main surface proximate the well region; a dielectric charge storage layer disposed above the bottom oxide layer relative to the main surface of the silicon substrate; a dielectric tunneling layer disposed above the charge storage layer relative to the main surface of the silicon substrate, the dielectric tunneling layer including, in order relative to the main surface of the silicon substrate and outward, a first dielectric oxide layer, an insulating dielectric layer having a hole barrier height less than that of the first dielectric oxide layer and a second dielectric oxide layer; and a control gate disposed above the dielectric tunneling layer relative to the main surface of the silicon substrate; and a voltage applied in an operating mode establishing an electric field across the data storage structure which induces hole tunneling current through the dielectric tunneling layer to reduce negative charge in the charge storage layer.