Patent ID: 6026228
Filing Date: 2000-02-15
Classification: G06F

Abstract:
An estimation method of an integrated circuit design on a top-down approach for designing at a behavior level an integrated circuit which is an object of design with specified constraints thereby generating a behavior level description data of the object of design and successively generating a description data corresponding to lower levels of abstraction from said behavior level description data, said method comprising the steps of:preparing a database wherein a variety of modules capable of being used as constituent elements of the object of design are registered as parametrized models, and instance generating information representing a procedure for generating an instance which is a module implemented by giving a parameter value to each of the various modules and feature estimation information representing a method of estimating specified design features representing the features of the various modules are stored every abstraction level of said design on the top-down approach for the various modules;generating a behavior level description data by generating instances by means of the instance generating information and the parameter values of the modules registered in said database and by describing at the behavior level the object of design with said instances used as constituent elements;extracting from said database the feature estimation information of the modules described as the constituent elements of the object of design in said behavior level description data and estimating design features of the modules by means of said feature estimation information and said parameter values of the modules;executing a floorplan corresponding to said behavior level description data on the basis of the design features of said modules; andestimating design features representing features of the design at the behavior level corresponding to said behavior level description data on the basis of a result of said floorplan.