Patent ID: 6725307
Filing Date: 2004-04-20
Classification: G06F

Abstract:
A data processing system comprising:a plurality of master devices, a plurality of bidirectional master device buses, wherein a master device bus connects one or more master devices to a bus access controller; a bus access controller (BAC) including: an address BAC (ABAC), wherein the ABAC is connected to each master device bus in the plurality of master device buses; a data BAC (DBAC), wherein the DBAC is connected to each master device bus in the plurality of master device buses; a set of control lines between the ABAC and the DBAC; a plurality of ABAC ports, wherein each ABAC port connects to address/control lines of each master device bus; and a plurality of DBAC ports, wherein each DBAC port connects to data lines of each master device bus.