Patent ID: 9170775
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A multiplier-accumulator block operative to zero or initialize an accumulator output value comprising: a first multiplier having a first input operative to receive a first input signal, a second input operative to receive a second input signal, and a first output, wherein the first input signal and the second input signal are concatenated in a predetermined order and sent to the first output; a second multiplier having a first input operative to receive a third input signal, a second input operative to receive a fourth input signal, and a second output, wherein the first multiplier is separate and distinct from the second multiplier, and wherein the first multiplier operates in parallel with the second multiplier; an accumulator having a first input operative to receive the first output, a second input operative to receive the second output, a third input operative to receive a feedback output, and an accumulator output, wherein the feedback output is set to zero; and a register block having an input operative to receive the accumulator output and a register block output, wherein the first input signal and the second input signal are both set to zero, and wherein the feedback output is concatenated to the first output.