Patent ID: 6864741
Filing Date: 2005-03-08
Classification: G05F

Abstract:
1. An electronic circuit comprising: a plurality of bipolar transistors, the first having its base connected to a reference, the following ones forming a series connection with their bases connected to the emitter of the preceding ones, and the collectors connected to a potential capable of supplying the current needed while maintaining the bipolar transistors in their linear region; MOSFET level shifters inserted between some of the base to emitter connections with a gate connected to the emitter, a source connected to the base and a drain connected to a potential capable of supplying the current at which the MOSFETs are biased, the type of MOSFET chosen to reduce the overall operating voltage of the circuit; a second plurality of bipolar transistors operating with lower current densities than the first plurality and connected in the same fashion as in the first plurality, and with level shifters connected in the same fashion as in the first plurality and operating at the same current densities as the level shifters in the first plurality; a differential amplifier with its positive input terminal connected to the emitter of the last transistor in the first plurality, its negative input connected to the emitter of the last transistor in the second plurality, and its output connected to the base of the first transistor in the second plurality; a transistor whose base is connected to the output of the amplifier and whose emitter is the output node of the circuit, and current sources biasing all the transistors.