Patent ID: 6014739
Filing Date: 2000-01-11
Classification: G06F

Abstract:
A microprocessor comprising:a register file, wherein said register file includes a standard register set comprising a plurality of standard registers and an extension register set comprising a plurality of extension registers; andan instruction decode circuit adapted to receive a microprocessor instruction, wherein said microprocessor instruction includes an extension register key field, and further wherein said instruction decode circuit is configured to access the contents of a selected extension register of said extension register set in response to receiving said microprocessor instruction if said extension register key field contains an extension register key value, and wherein said instruction decode circuit is further configured to access the contents of a selected standard register of said standard register set in response to receiving said microprocessor instruction if the contents of said extension register key field equal a value other than said extension register key value;wherein said extension register key field of said microprocessor instruction serves as a standard register field if said extension register key field contains a value other than said extension register key value, wherein said instruction decode circuit is configured to use the contents of said standard register field to select said selected standard registers and wherein said instruction decode unit selects said selected standard register by indexing said standard register set according to the contents of said standard register field.