Patent ID: 6235633
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method for making metal plugs in an intermetal dielectric layer comprising the steps of:providing a semiconductor substrate having semiconductor devices and a planar insulating layer on surface of said substrate;depositing a conducting layer on said planar insulating layer;patterning said conducting layer to form electrical interconnections for said semiconductor devices;depositing a planar intermetal dielectric layer over said electrical interconnections;depositing a hard mask layer on said intermetal dielectric layer;etching contact openings in said hard mask layer and said intermetal dielectric layer to said electrical interconnections;depositing a conformal barrier layer on said hard mask layer and in said contact openings;depositing a metal layer sufficiently thick to fill said contact openings and to form an planar surface;forming metal plugs in said contact openings by a first chemical/mechanical polishing of said metal layer and said barrier layer selectively to said hard mask;using a second chemical/mechanical polishing to remove said hard mask layer and polishing said metal plugs at a comparable polishing rate and thereby minimizing electrical shorts between adjacent said metal plugs.