Patent ID: 7564934
Filing Date: 2009-07-21
Classification: H04L

Abstract:
1. A method of digital signal processing of multi-sampled phase (DSP MSP), recovering data from a received signal, which comprises capturing multiple samples of the signal per a symbol time with sub-clocks of a sampling clock defining known phase displacements versus the sampling clock; the DSP MSP method comprising the steps of: using multiple sequential processing stages and parallel processing phases of said captured samples; driving said sequential processing stages with the sampling clock or clocks synchronous to the sampling clock; driving consecutive said parallel processing phases with clocks which are shifted in time by corresponding consecutive periods of said sampling clock and have 2 or more times lower frequencies than a frequency of the sampling clock, in order to multiply processing times assigned for said parallel phases; passing outputs of a one parallel processing phase to a next parallel phase, wherein output register bits of an original parallel phase are re-timed by clocking them into an output register of the next parallel phase simultaneously with processing results of the next parallel phase; using said passed outputs in a following sequential processing stage which belongs to the next parallel processing phase; detection of phases of rising and falling edges of the signal by using said signal samples captured at said known phase displacements; evaluation of a length of a pulse of the signal by using said phases of signal edges; calculation of a number of data bits received in the pulse by using said evaluation of the pulse length.