Patent ID: 9122580
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A flash memory system, comprising: a flash memory controller having a processing unit; and a flash memory coupled to the flash memory controller and having a reserved area and a data area, wherein the reserved area has a recording area and the data area has a plurality of valid data pages and a plurality of invalid data pages, and wherein the processing unit controls the recording area for recording a plurality of invalid data page messages corresponding to the invalid data pages, respectively, and the invalid data page messages represent a plurality of page addresses of the invalid data pages correspondingly; wherein the recording area further comprises a log directory and a log content corresponding to the log directory, wherein the log directory has a plurality of message sections and the log content has a plurality of sets of address fields corresponding to the message sections respectively, and wherein each of the message sections has a region indicator, a starting recording position, a recording length, a total recording amount and a previous version pointer; wherein the starting recording position of each message section corresponds to a filed length of each set of address fields and the starting recording position of the recoding content; and wherein the log directory of the current version is sequentially linked to the log director the at least one previous version according to the previous version pointer for connecting the message sections with the same region indicator.