Patent ID: 7855443
Filing Date: 2010-12-21
Classification: H01L

Abstract:
1. A stack structure of semiconductor packages, comprising: a lower semiconductor package comprising a substrate, a semiconductor chip mounted on and electrically connected to the substrate, and an encapsulant formed on the substrate and encapsulating the semiconductor chip; and an upper semiconductor package mounted on the lower semiconductor package, wherein the upper semiconductor package comprises a substrate having a first surface and a second surface opposite to the first surface, a semiconductor chip mounted on and electrically connected to the first surface of the substrate, a plurality of electrical connection pads and dummy pads formed on the second surface of the substrate, and a plurality of solder balls implanted to the electrical connection pads and the dummy pads, wherein the upper semiconductor package is electrically connected to the substrate of the lower semiconductor package by the solder balls implanted to the electrical connection pads of the upper semiconductor package, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads of the upper semiconductor package, wherein at least one of the dummy pads of the second surface of the substrate of the upper semiconductor package is located at a position corresponding to that closely adjacent to one of a middle portion, one end, and two ends of each edge of the encapsulant of the lower semiconductor package, so that the solder balls implanted to the dummy pads contact the encapsulant of the lower semiconductor package, and wherein the dummy pads are provided with the solder pads for supporting the upper semiconductor package only and are free from electrical connection.