Patent ID: 6033981
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method to eliminate the formation of voids in a gap between closely spaced conducting lines in an integrated circuit device comprising:providing a substrate;providing said closely spaced conducting lines having said gap therebetween on said substrate;depositing a first HDP oxide layer overlying tops and sidewalls of said conducting lines and said substrate;isotropically etching said first HDP oxide layer exposing an upper portion of said sidewalls of said conducting lines;depositing an insulating layer overlying said first HDP oxide layer and said exposed conducting line sidewalls;removing said insulating layer overlying said HDP oxide layer on said tops of said conducting lines using chemical mechanical polishing;etching away exposed areas of said first HDP oxide layer overlying said tops of said conducting lines;thereafter removing said insulating layer;forming insulating spacers on said upper portion of said sidewalls of said conducting lines;depositing a second HDP oxide layer overlying said first HDP oxide layer, said conducting lines and said insulating spacers thereby filling said gap between said conducting lines; andcompleting said integrated circuit device.