Patent ID: 6385118
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory array having word lines, data lines and memory cells; a plurality of sense amplifiers connected to said data lines; a plurality of word drivers connected to said word lines; a drive circuit connected to said plurality of sense amplifiers; and a timing circuit which forms an operation timing signal for said drive circuit, wherein each of said plurality of word drivers comprises a first transistor with a gate insulation film having a first thickness, wherein said timing circuit comprises a second transistor with a gate insulation film having said first thickness, wherein said drive circuit comprises a third transistor with a gate insulation film having a second thickness smaller than said first thickness, wherein said first transistor is supplied with a first power supply voltage, and wherein said second and third transistors are supplied with a second power supply voltage lower than said first power supply voltage.