Patent ID: 6468850
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A manufacturing method for manufacturing a semiconductor memory device having a peripheral circuit area, a memory cell area, and a border region positioned in a border between the peripheral circuit area and the memory cell area on a main surface of a semiconductor substrate, the method comprising:(a) the step of forming a device isolation structure on the main surface, (b) the step of forming a first well in contact with the border region but not in contact with the memory cell area, by ion-implanting an impurity in the peripheral circuit area only, (c) the step of forming a second well of a first conductivity type by ion-implanting an impurity in the memory cell area, wherein the second well is shallower in depth than the first well and is formed down to a level lower than the device isolation structure, (d) the step of forming a third well of a second conductivity type by ion-implanting an impurity in the memory cell area, wherein the third well is equal in depth to the second well and is adjacent to the second well beneath the device isolation structure, and (e) the step of forming a field effect transistor in the memory cell area, wherein the step (e) comprises the step of forming dummy elements that do not function as active device elements in the border region at substantially the same device element forming density as that of the memory cells in the memory cell area.