Patent ID: 6154054
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of forming a field programmable gate array having a plurality of logic modules, comprising:forming a plurality of logic modules; andforming a plurality of conductive plug-type antifuses over the logic modules, each of the conductive plug-type antifuses having a region of amorphous silicon in contact with a conductive plug, less than three percent of all antifuses of the field programmable gate array comprising an amorphous silicon region having a corner (from the top-down perspective) disposed within a lateral distance DIS of the conductive plug of the antifuse, an antifuse of the field programmable gate array being separated from another antifuse of the field programmable gate array by lateral distance DIS, there being no antifuses of the field programmable gate array separated by a lateral distance smaller than lateral distance DIS.