Patent ID: 8983062
Filing Date: 2015-03-17
Classification: G09C,H04L

Abstract:
1. A cryptographic processing device comprising a cryptographic processing circuit configured to divide and input constituent bits of data to be subjected to data processing into a plurality of lines, and repeatedly perform a data converting operation on the data in the respective lines by using a round function, wherein the cryptographic processing circuit has a structure designed to input n/d-bit data formed by dividing n-bit data as input data by a division number d to the respective lines, and repeatedly perform a calculation as a round calculation including the data converting operation using the round function, the cryptographic processing circuit performs an operation in which the n/d-bit data of each line having output data of the round calculation is redivided into d/2 sets of data, the redivided data is recombined to restructure d sets of n/d-bit data different from output data of a round calculation of a previous stage, and the restructured data is set as input data for a round calculation of the next stage, the round function includes an F-function and an exclusive OR operation to be performed on a output or an input of the F-function with data of another line, and the cryptographic processing circuit sets a result of the round calculation of the previous stage as the input to the round calculation of the next stage by performing an operation that satisfies the following distribution conditions (1) through (3): (1) F-function input-side data series are distributed to XOR-side data series of the next round function, (2) XOR-side data series are distributed to F-function input-side data series of the next round function, and (3) each one of data series divided into d/2 sets is distributed to d/2 data series of the next round function without overlaps.