Patent ID: 8389363
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising: forming masking material over semiconductive material of a substrate; forming array circuitry trenches through the masking material and into the semiconductive material; depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material; after depositing the array gate material, forming peripheral circuitry trenches through the masking material; depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material; the array circuitry trenches being formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the array circuitry trenches are formed, the grounded gate trenches being formed into trench isolation material received within the substrate semiconductive material.