Patent ID: 7620763
Filing Date: 2009-11-17
Classification: G06F

Abstract:
1. A memory chip comprising: a data bus having “N bits”, the data bus consisting of: a first group of I/O signals having “M bits” configured to receive data to be stored into the memory chip; and a second group of I/O signals having “N−M bits” configured to drive data read from the memory chip; wherein a value of “M” is programmable; a third group of I/O signals having “M” bits configured to drive data to be stored in a second memory chip; a fourth group of I/O signals having “N−M” bits configured to receive data read from the second memory chip; a fifth group of I/O signals configured to receive an address/command word; a sixth group of I/O signals configured to forward the address/command word received on the fifth group of I/O signals to the second memory chip only if the address/command word received on the fifth group of I/O signals is not targeted for the memory chip; a first write queue for holding one or more data words to be written into an away on the second memory chip; a read queue for holding data read from the second memory chip; the memory chip configured to receive a first write data word from the first group of I/O signals into the first write queue, using a bus clock, the first write data word driven from the first write queue onto the third group of I/O signals after the memory chip completes driving a second write data word onto the third group of I/O signals, using the bus clock, from the first write queue; and the memory chip further configured to receive a first read word from the fourth group of I/O signals into the read queue, using the bus clock, and driving the first read data word from the read queue onto the second group of I/O signals, using the bus clock, after the memory chip completes driving a second read data word onto the second group of I/O signals from the read queue; wherein the first write data word is associated with a first address/command word; the second write data word is associated with a second address/command word; the first read data word is associated with a third address/command word; and the second read data word is associated with a fourth address/command word.