Patent ID: 7973687
Filing Date: 2011-07-05
Classification: H03K,H03M

Abstract:
1. A differential switch circuit comprising: a first differential switch basic circuit; and a second differential switch basic circuit coupled in parallel, where the first differential switch basic circuit includes a first common source node shared by a plurality of transistors, and the second differential switch basic circuit includes a second common source node shared by a plurality of transistors, wherein the first common source node and the second common source node are alternately reset to a predetermined voltage in each clock cycle, the first common source node is coupled to a drain node of a first transistor, the second common source node is coupled to a drain node of a second transistor, a source node of the first transistor and a source node of the second transistor are coupled to each other to form a third common source node, the third common source node is coupled to an output of a current source, the current source includes a current source transistor, and a cascode transistor which is cascode-coupled to a drain node of the current source transistor, and the third common source node is coupled to a drain terminal of the cascode transistor.