Patent ID: 8829484
Filing Date: 2014-09-09
Classification: H01L

Abstract:
1. A memory array comprising: a plurality of paired-cell structures; each of the paired-cell structures comprising: wherein the bottom electrodes, programmable material and top electrode are comprised by two memory cells within the paired cell structures; wherein the paired-cell structures are over a base comprising conductive contacts; wherein the conductive contacts are electrically coupled with the bottom electrodes; wherein each of the bottom electrodes has at least one segment which extends at angle of from greater than 30° to less than or equal to about 85° relative to a planar topography of the base; wherein the to electrodes extend substantially parallel to the planar topography of the base and are in one-to-one correspondence with the paired-cell structures; and wherein each of the bottom electrodes has two or more segments extending at different angles than one another relative to the planar topography of the base.