Patent ID: 6069662
Filing Date: 2000-05-30
Classification: H04N

Abstract:
An apparatus for displaying a plurality of compressed images, comprising at least a processing circuit supplied with a plurality of video signals of interlace type for producing a single video signal including a plurality of compressed images, said processing circuit including:means for skipping at least one of said input video signals for conversion into a compressed image signal at least vertically by line;a memory having two field storage areas for storing said compressed image signals by field;means for generating addresses of said memory;first select means for storing said compressed image signals in said two field storage areas alternately by field in accordance with said addresses;means for suspending the write operation into said memory in order to display a frozen image;skipping restriction means for causing said skipping means to suspend the skipping or reduce the rate of skipping to one half with respect to a field of said input video signal immediately before said write operation is suspended by said write operation suspension means;second select means for storing said compressed image signals from said skipping means alternately between said two field storage areas by line according to said addresses;means for reading said two field storage areas alternately by field; andmeans for producing a read signal from said read means as a compressed image display signal.