Patent ID: 7132751
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. An apparatus, comprising: an insulating layer; a plurality of spaced-apart semiconductor lines formed on the insulating layer; a plurality of spaced-apart conductive gate lines formed on the insulating layer, with each of the plurality of gate lines being disposed to intersect the plurality of semiconductor lines at a plurality of intersections and including a plurality of front gates and a plurality of back gates; the plurality of semiconductor lines including a plurality of body regions disposed at the plurality of intersections, with each of the plurality of body regions including a channel and each of the plurality of body regions being formed from a silicon carbide material; and at least one of the plurality of body regions having a pair of gate-adjacent opposed sides with one of the front gates being adjacent to one of the pair of gate-adjacent opposed sides and one of the back gates being adjacent to the other one of the pair of gate-adjacent opposed sides.