Patent ID: 8255733
Filing Date: 2012-08-28
Classification: G06F

Abstract:
1. An integrated circuit comprising: a closed loop control system adapted to provide a clock signal; a first digital-to-analog converter (DAC) adapted to provide a control signal to the closed loop control system to provide coarse tuning of the closed loop control system; a memory adapted to store a control signal value based on the coarse tuning of the closed loop control system; a second DAC adapted to receive the control signal value stored in the memory and provide a reference signal based on the control signal value; and a plurality of delay circuits, wherein each of the delay circuits comprises: a plurality of delay stages configured in a series and adapted to receive the clock signal and provide a delayed clock signal; a third DAC adapted to provide a control signal to the plurality of delay stages to control the delay applied by the plurality of delay stages to the clock signal, wherein the third DAC receives the reference signal from the second DAC to control the delay range and the delay step size; and a decoder adapted to receive a delay select control signal and provide a select control signal to the third DAC to select the delay that the third DAC sets for the plurality of delay stages.