Patent ID: 8233312
Filing Date: 2012-07-31
Classification: G11C,H01L

Abstract:
1. A DRAM (dynamic random access memory) cell utilizing floating body effect, comprising a buried oxide layer, a first N type semiconductor region provided on the buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, and a gate region provided on the P type semiconductor region, including a gate dielectric layer and a gate electrode on the gate dielectric layer, wherein a second N type semiconductor region is provided on one side of the P type semiconductor region and the second N type semiconductor region is communicated with the first N type semiconductor region; wherein an electrical isolation region is provided around an active region formed by the P type semiconductor region, the first N type semiconductor region and the second N type semiconductor region; wherein a depletion region is formed by the first N type semiconductor region and the P type semiconductor region, and the second N type semiconductor region and the P type semiconductor region, and a floating body is formed by the electrical isolation region and the depletion region; wherein a electrode connected to bit line is provided on the second N type semiconductor region.