Patent ID: 7971130
Filing Date: 2011-06-28
Classification: G06F,G11C,H03M

Abstract:
1. A memory apparatus comprising: a memory block comprising a plurality of memory cells, each memory cell configured to operate with multi-level signals; a low density parity check (LDPC) coder configured to LDPC encode data values to provide LDPC encoded data values to be written into the memory cells; an interleaver configured to interleave the LDPC encoded data values with bit interleaved code modulation to generate interleaved LDPC encoded data values; and a mapper configured to map the interleaved LDPC encoded data values to modulation codes in accordance with a constellation map, wherein a set of least significant bits is mapped to a modulation code corresponding to a lowest transmission voltage level, and a set of most significant bits is mapped to a modulation code corresponding to a highest transmission voltage level.