Patent ID: 6278303
Filing Date: 2001-08-21
Classification: G06F,H03L,Y02D

Abstract:
A semiconductor device, having a standby mode and an active mode of operation, comprising:a synchronizing clock generation circuit generating a source clock signal in synchronization with an external clock signal, said synchronizing clock generation circuit includinga clock delay circuit delaying, for a particular delay period, said source clock signal to output a feed back clock signal, anda signal generation circuit generating said source clock signal according to a phase difference between said external clock signal and said feed back signal when said device is operating in said active mode and when said device is operating in said standby mode;a clock supply circuit receiving said source clock signal and configuredto output an intermediate clock signal via an output when said device is operating in said active mode, andto inactivate the output when said device is operating in said standby mode;a clock transmission unit transmitting said intermediate clock signal; andan internal circuit receiving an internal clock signal corresponding to said intermediate clock signal from said clock transmission unit to carry out a predetermined operation, said internal circuit includinga data retain circuit receiving and retaining data according to said internal clock signal.