Patent ID: 6818937
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A memory array comprising:a plurality of substantially parallel bit lines at least partially on a substrate; a plurality of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed on one of the bit lines such that the body region is located above the bit line, the second source/drain region including an upper semiconductor surface; a plurality of first word line pairs, each first word line pair disposed in first trenches extending orthogonal to the bit lines, each first word line in the first word line pair separated from the other first word line in the first word line pair, and wherein each word line in the plurality of first word line pairs has a side facing the vertically formed body which has a vertical length of less than 6.0 &mgr;m; a plurality of second word line pairs, each second word line pair disposed in second trenches that are interdigitated with the first trenches, wherein the second trenches extend orthogonal to the bit lines, each second word line in the second word line pair separated from the other second word line in the second word line pair, and wherein each word line in the plurality of second word line pairs has a side facing the vertically formed body which has a vertical length of less than 6.0 &mgr;m; and a plurality of isolation trenches extending parallel to and between the bit lines, and interposed between ones of the access transistors.