Patent ID: 6462994
Filing Date: 2002-10-08
Classification: G11C

Abstract:
A semiconductor memory device, comprising:an address buffer for receiving an external address; a row decoder for decoding a row address provided by the address buffer, and generating a word line selecting signal; a column decoder for decoding a column address provided by the address buffer, and generating a bit line selecting signal; a memory cell array having a plurality of memory cells, each of the plurality of memory cells being activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal, respectively; a redundancy logic cell for replacing defect cells in the memory cell array; a plurality of defect cell address latches for storing defect cell addresses corresponding to the defect cells in the memory cell array, the defect cells being detected in a memory test; a plurality of comparators for outputting repair signals when an address stored in the plurality of defect cell address latches corresponds to the external address received by the address buffer; and a redundancy controller for generating a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to a repair signal outputted in a normal mode, and generating another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.