Patent ID: 6750555
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A semiconductor memory device having SRAM memory cell comprising:a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein an input node of said first inverter is connected to an output node of said second inverter; and an input node of said second inverter is connected to an output node of said first inverter; one of a drain and a source of said third nMOS transistor is connected to the output node of said first inverter; the other of the drain and the source thereof is connected to a first bit line; and a gate thereof is connected to a word line; one of a drain and a source of said fourth nMOS transistor is connected to the output node of said second inverter; the other of the drain and the source thereof is connected to a second bit line; and a gate thereof is connected to said word line; a first diffusion region forming said first nMOS transistor and said third nMOS transistor and a second diffusion region forming said second nMOS transistor and said fourth nMOS transistor, respectively, are arranged in linear shapes without having any bent part; and current driving capabilities of said first and second nMOS transistors are higher than those of said third and fourth nMOS transistors, wherein a driving voltage of said word line is lower than a power supply voltage supplied to said first and second inverters.