Patent ID: 6601223
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A method for estimating the interconnect delay times in an integrated circuit using a resistor-capacitor (RC) tree model, comprising the steps of:a) initializing an effective capacitance for each RC tree node; b) initializing a delay on each RC tree segment; c) computing slew at a source node of the RC tree, using an effective capacitance last calculated for the source node; d) computing remaining slews for each node in the RC tree by propagating outward to sinks from the source; e) recomputing effective capacitances for each RC tree node by propagating inward to the source node from the sinks; f) updating the delay of each RC tree segment using effective capacitances recomputed in step (e); g) recomputing the source node slew using an effective capacitance recomputed in step (e); and h) repeating steps (d) to (h) until the source node slew computed at step (c) is within a specified threshold from the source node slew recomputed at step (g).