Patent ID: 6643766
Filing Date: 2003-11-04
Classification: G06F

Abstract:
An apparatus for minimizing cache miss latency in an out of order instruction execution system, comprising:a plurality of address reorder buffer slots each having stored therein an address corresponding to a data line of a plurality data lines, each of said plurality of data lines being stored in at least one of a cache memory and a memory hierarchy; at least one pre-fetch slot configured to, upon detection of a cache miss of a first data line resulting from an access request from at least one of said plurality of address reorder buffer slots, determine at least one additional data line to be pre-fetched into said cache memory from said memory hierarchy; and a logic associated with said at least one pre-fetch slot, said logic configured to provide an indication whether said at least one additional data line is already being requested from said memory hierarchy by any of said plurality of address reorder buffer slots, wherein if said at least one additional data line has not already been requested, the apparatus issues a pre-fetch request for said at least one additional data line from said memory hierarchy to said cache memory.