Patent ID: 7208980
Filing Date: 2007-04-24
Classification: G01R,H03F,H03M

Abstract:
1. A differential comparator comprising: a first transistor receiving a first input current at a first node; and a second transistor receiving a second input current at a second node, wherein the first and the second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and the second transistors, and are connected together as a latch to provide an output during a latch phase; wherein a gate-source voltage of the first transistor is stored on a parasitic capacitance of the first transistor during the reset phase; wherein a gate-source voltage of the second transistor is stored on a parasitic capacitance of the second transistor during the reset phase; wherein the gate-source voltage of the first transistor and the gate-source voltage of the second transistor comprise the offset voltage.