Patent ID: 8693250
Filing Date: 2014-04-08
Classification: H01L

Abstract:
1. A three dimensional stacked nonvolatile semiconductor memory comprising: a semiconductor substrate; a memory cell array including a first block and a second block above the semiconductor substrate; and a driver electrically connected between the first block and the second block, wherein the first block includes a first memory cell, a second memory cell and a first select gate transistor, the second block includes a third memory cell, a fourth memory cell and a second select gate transistor, the first memory cell is stacked above the semiconductor substrate, the second memory cell is stacked above the first memory cell, the third memory cell is stacked above the semiconductor substrate, the fourth memory cell is stacked above the third memory cell, the driver commonly connects both a gate of the first select gate transistor and a gate of the second select gate transistor, and the first select gate transistor and the second select gate transistor are disposed in a same layer.