Patent ID: 8039343
Filing Date: 2011-10-18
Classification: G06K,H01L

Abstract:
1. A method of forming a scratch resistant integrated circuit structure, comprising: forming an active region; forming a dielectric overlying the active region; forming a capacitive electrode overlying the dielectric, wherein the capacitive electrode and each conductive region between the capacitive electrode and the active region are formed of a conductive material having a hardness greater than a hardness of aluminum; forming an oxide over the capacitive electrode and an interlevel dielectric adjacent the capacitive electrode; forming a passivation layer including a silicon nitride layer and a silicon carbide layer over the oxide and over the capacitive electrode; and forming ESD protection within the passivation layer, wherein the capacitive electrode and each conductive region between the capacitive electrode and the active region are formed of a conductive material having a hardness at least as great as a hardness of the passivation layer.