Patent ID: 6962848
Filing Date: 2005-11-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure, each first structure having a top surface; forming first doped regions in the semiconductor substrate, wherein each pair (S wherein for each pair of structures (S the method further comprises: for each pair (S forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control gates in the first structure, the conductive gates being insulated from the floating and control gates.