Patent ID: 8949493
Filing Date: 2015-02-03
Classification: G06F,G11C,H04L

Abstract:
1. A configurable scrambler in an integrated circuit (“IC”) comprising: a plurality of linear feedback shift register (“LFSR”) circuits, each coupled to receive data in one of a plurality of data lanes; and selection circuits coupled between the LFSR circuits, the selection circuits being configurable to select between two modes of the configurable scrambler, the two modes including: a first mode in which each of the plurality of LFSR circuits scramble data in a corresponding lane separately and a second mode in which two or more of the LFSR circuits are combined to scramble data in two or more of the plurality of the lanes, wherein combining the LFSR circuits includes providing a scramble output of a first LFSR circuit to a scramble input of a second LFSR circuit, the first LFSR circuit being coupled to one of the plurality of lanes and the second LFSR circuit being coupled to another of the plurality of lanes.