Patent ID: 7209057
Filing Date: 2007-04-24
Classification: H03M

Abstract:
1. Decode circuitry for decoding a multi-bit digital data and outputting an electric signal indicating a decoding result, comprising: a first bit group decode circuit arranged corresponding to a first bit group of said multi-bit digital data of a multiplicity of bits, and decoding said first bit group, said multi-bit digital data being divided into a plurality of bit groups at least one of which includes plural bits, the bit groups including said first bit group, said first bit group decode circuit including a plurality of first sub-decode circuits arranged corresponding to respective sets each including a plurality of output candidates, and said first sub-decode circuits commonly receiving the bit or bits of said first bit group and each first sub-decode circuit selecting one output candidate from a corresponding set of the output candidates; and a second bit group decode circuit arranged corresponding to a second bit group of said multi-bit digital signal of the multiplicity of bits, and decoding the bit or bits of said second bit group to select an output of said first bit group decode circuit for outputting the electric signal indicating a decode result, said second bit group decode circuit including a plurality of second sub-decode circuits arranged corresponding to the first sub-decode circuits, and commonly receiving said second bit group to select the outputs of corresponding first sub-decode circuits for outputting selected outputs to an output line, respectively, each second sub-decode circuit including a series connection body of switching element or elements provided for the bit or bits of the second bit group and being selectively made conductive in response to the respective bit or bits in said second bit group, the series connection bodies of the second sub-decode circuits being commonly coupled to said output line, and the electric signal indicating said decoding result being supplied to said output line.