Patent ID: 6748483
Filing Date: 2004-06-08
Classification: G09G,G11C,H04B

Abstract:
A process of operating a DRAM system comprising:A. providing at least plural groups of parallel address signals from a processor; B. carrying plural parallel array data signals on plural array data leads to and from an array of a dynamic random access memory formed on an integrated circuit chip including representing one data bit with one data signal; C. carrying parallel array address signals on parallel array address leads to the array including representing one address bit with one address signal; D. randomly addressing random locations in the array with the array address signals by addressing one data word of plural data bits; E. writing one word of data bits from the array data leads to each addressed random location; F. reading one word of data bits to the array data leads from each addressed random location; G. receiving a first continuous clock signal formed of rising and falling edges regularly spaced in time at a first clock signal terminal; G. receiving a second continuous clock signal formed of rising and falling edges regularly spaced in time at a second clock signal terminal; H. receiving the parallel address signals at plural address terminals while the first and second clock terminals receive the first and second continuous clock signals, the received address signals occurring in plural groups separated in time; I. coupling the received address signals to the array address leads including indicating an address of a random location in the array with the received address signals; J. receiving address control data signals at the plural address terminals, the address control data signals controlling the parallel address signals carried to the array address leads; K. receiving and sending parallel data signals at plural data terminals including representing one data word with each set of parallel data signals; and L. coupling the plural data terminals with the array data leads including: i. receiving the parallel data signals synchronous with the first continuous clock signal for writing the data signals in the array at the random location indicated by the received address signals; and ii. sending the parallel data signals synchronous with the second continuous clock signal for reading the data signals from the array at the random location indicated by the received address signals.