Patent ID: 8560991
Filing Date: 2013-10-15
Classification: G01R,G06F

Abstract:
1. A method of automated debugging of a design under test in a verification environment, the method comprising: identifying, using a computer, a failing test of the design under test in the verification environment; determining a plurality of inputs of the failing test, wherein the verification environment creates the plurality of inputs; dividing the plurality of inputs of the failing test into a plurality of groups; generating a plurality of altered tests of the design under test in the verification environment with each altered test comprising a group altered test comprising the plurality of groups with at least one group altered; executing the plurality of altered tests of the design under test in the verification environment; identifying at least one altered test from the plurality of altered tests that results in a passing altered test; and determining the at least one input altered in each respective altered test that results in the passing altered test.