Patent ID: 6492851
Filing Date: 2002-12-10
Classification: H03L

Abstract:
A digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals, comprising:a first delay locked loop that is feedback-controlled and that contains a first voltage-controlled delay line comprising delay buffers having a first type of propagation delay time concatenated in h stages and that receives a selected one of said reference clock signals; a second delay locked loop that is feedback-controlled and that contains i second voltage-controlled delay lines that are each connected to one of a respective output of i stages of outputs of said first voltage-controlled delay line and said selected at least one of said reference clock signals, each said second voltage-controlled delay line comprising delay buffers having a second type of propagation delay time concatenated in j stages; a third delay locked loop that is feedback-controlled and that contains a third voltage-controlled delay line that is composed of delay buffers having said second type of propagation delay time concatenated in k stages; and a selector that switches a clock signal from one of selected ones of stages of said first voltage-controlled delay line and said second voltage-controlled delay line to be an input into said third voltage-controlled delay line wherein, a delay control voltage or current for maintaining resolution that is generated by said third delay locked loop that feedback-controls said third voltage-controlled delay line is supplied to each of the delay buffers of each of said second voltage-controlled delay lines.