Patent ID: 6738393
Filing Date: 2004-05-18
Classification: H04J,H04L

Abstract:
A frame synchronization circuit used on a reception side of a data transmission system utilizing a frame composition in which a frame synchronization code is scatteredly positioned in a frame, said frame synchronization circuit comprising:a first frame synchronization code detector that: 1) detects said frame synchronization code from a received data sequence, 2) compares said frame synchronization code with a correct frame synchronization code in a forward direction on a time axis and 3) outputs a first checked result in bit form, each bit of said first checked result indicating whether a bit of said frame synchronization code has a same value of a corresponding bit of said correct frame synchronization code, and 4) outputs a prescribed bit position in said frame synchronization code as a first frame position; a second frame synchronization code detector that: 1) detects said frame synchronize on code from said received data sequence, 2) compares said frame synchronization code detected by said second frame synchronization code detector with said correct frame synchronization code in a backward direction on said time axis and 3) outputs a second checked result in bit form, each bit of said second checked result indicating whether a bit of said flame synchronization code detected by said second frame synchronization code detector has a same value of a corresponding bit of said correct frame synchronization code, and 4) outputs a prescribed bit position in said frame synchronization code detected by said second frame synchronization code detector as a second frame position; a difference circuit for obtaining a length between said first frame position and said immediately following second frame position; a data loss and data insertion pectic judgment circuit determining a data loss period and a data insertion period in said received data sequence according to said length output from said difference circuit said first checked result and said second checked result; and a synchronization judgement circuit determining and outputting a frame synchronization position depending on said first frame position, said second frame position, and a determination of said data loss and data insertion period judgment circuit.