Patent ID: 7187602
Filing Date: 2007-03-06
Classification: G06F,G11C

Abstract:
1. A method of reducing memory failures in an individual integrated circuit (IC) having an array of memory cells comprising: testing the array using error correction code (FCC) prior to packaging; repairing defects detected during testing which are not correctable by ECC; performing a read operation to a memory address for a memory location in the array after packaging; retrieving a data word of information from the memory location in the array corresponding to the memory address; determining whether the data word contains an error using ECC; when the error is not correctable by ECC, determining availability of a redundancy unit within the IC for repairing a defective memory element corresponding to the error, wherein the redundancy unit includes a fuse block and a corresponding redundant memory element; and if a redundancy unit is available, programming the fuse block of the redundancy unit with the memory address of the error to cause the redundant memory element corresponding to the fuse block to replace the defective memory element.