Patent ID: 7212744
Filing Date: 2007-05-01
Classification: H03K,H03M,H04J

Abstract:
1. A receiver circuit, comprising: a synchronous circuit that recovers and outputs a clock signal having a frequency of f “j” pieces of multipliers that output each clock signal acquired by multiplying a clock signal output from the synchronous circuit by predetermined multiple ratio via “j” pieces of interconnects (j: one or larger natural number); and a synchronous digital circuit that has “j” pieces of parallel input terminals including one common to the input of the synchronous circuit, “j×k” pieces of parallel output terminals and “j” pieces of parallel clock input terminals, decides and recovers “j” pieces of data signals the data rate of each of which is f the “j” pieces of parallel terminals to which data signals are input of the synchronous digital circuit function as the input terminal of the receiver circuit and the “j×k” pieces of parallel terminals from which the data signals are output function as the output terminal of the receiver circuit; and first to “j”th interconnects connecting the output. terminal of the synchronous circuit and the input terminals of the “j” pieces of multipliers and “j+1”th to “2×j”th interconnects connecting the “j” pieces of multipliers and the “j” pieces of parallel clock input terminals of the digital circuit are arranged so that delays t