Patent ID: 6646926
Filing Date: 2003-11-11
Classification: G11C

Abstract:
A flash memory device comprising:a memory array having a plurality of erasable blocks of memory cells, wherein the memory cells in each block are arranged in rows; a control circuit to control memory operations to the memory array, wherein the control circuit applies a first number of erase pulses to a block being erased in a first stage and a second number of erase pulses to the block in a second stage, further wherein the second number of erase pulses applied in the second stage is a fraction of the first number of erase pulses applied in the first stage and based on the number of erase pulses needed in the first stage to verify a predetermined number of rows in the block have been erased, the control circuit does not use rows that have not been verified as being erased in subsequent memory operations to the block; and a register having a plurality of register sub-blocks coupled to the control circuit, wherein each register sub-block is associated with a block of memory cells, further wherein each register sub-block has a register memory cell for each row in a block of memory cells for the control circuit to store data indicating if the associated row has been verified as being erased.