Patent ID: 7262472
Filing Date: 2007-08-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a plurality of active regions including a p-type active region; an insulated gate electrode structure formed on each of said active regions, said insulated gate electrode structure having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of each of said insulated gate electrode structures; source/drain regions having extension regions having a conductivity type opposite to a conductivity type of each of said active regions and formed in said active regions on both sides of each of said insulated gate electrode structures and source/drain diffusion layers having the conductivity type opposite to the conductivity type of each of said active regions and formed in said active regions outside of said side wall spacers, n-type source/drain regions being formed in said p-type active region; first recess regions formed in said n-type source/drain region, said first recess regions having regions creeping under said side wall spacers at a level below said gate insulating film; and a first nitride film having a tensile stress formed covering said p-type active region and burying said first recess regions.