Patent ID: 8564037
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a device isolation groove defining first to fourth device formation portions, the second device formation portion facing to the first device formation portion, the third device formation portion connecting to the first device formation portion in a first direction so that the third device formation portion does not reach the second device formation portion, the fourth device formation portion connecting to the second device formation portion in opposite the first direction so that the fourth device formation portion does not reach the first device formation portion, a plurality of wiring portions crossing over the third and fourth device formation portions, the plurality of wiring portions comprising a first wiring portion, wherein the third and fourth device formation portions are positioned adjacently between the first and second device formation portions, wherein the third and fourth device formation portions have first and second trenches, respectively, and wherein the first wiring portion fills the first and second trenches.