Patent ID: 7554519
Filing Date: 2009-06-30
Classification: G09G

Abstract:
1. A system-for adjusting clock phase in a digital display including a first analog-to-digital converter that generates a first digital signal based on an analog input signal and a first clock signal, the system comprising: a first clock phase adjustment circuit, which is communicatively coupled to the first analog-to-digital converter, and which provides the first clock signal to the first analog-to-digital converter; a second analog-to-digital converter that receives at least a portion of the analog input signal and a second adjusted clock signal, and that generates a second digital signal based on the input signal and the second adjusted clock signal; a second clock phase adjustment circuit, which is communicatively coupled to the second analog-to-digital converter, and which provides the second adjusted clock signal to the second analog-to-digital converter; and a controller, which is communicatively coupled to the second analog-to-digital converter and to the first and second clock phase adjustment circuits, the controller being adapted to determine a selected phase of the second adjusted clock signal using the second clock phase adjustment circuit and the second digital signal, and to cause the first clock phase adjustment circuit to adjust the phase of the first clock signal based on the selected phase; wherein the analog input signal comprises a plurality of channels and the second analog to digital converter receives a single channel of the analog input signal.