Patent ID: 6601176
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A power management system for providing energy to volatile ram in a processor based electronic system installed in a vehicle having an engine, said vehicle including an engine crank signal for detecting a startup condition of said engine and having a main electrical power source, said power management system comprising:a main processor board for performing information processing including an input for said engine crank signal and a main processor coupled to said volatile ram; a vehicle input/output processor board for performing real time processing of vehicle interfaces, user inputs, and overall power management of a plurality of peripheral devices, said input/output processor board being coupled to said main processor board and including an input for said engine crank signal; a primary voltage regulator for powering said main processor board and generating a primary regulated output votage in response to a primary input voltage, said primary voltage regulator being coupled to said input/output processor board and being coupled to said main electrical power source; and a secondary voltage regulator coupled to said volatile ram and responsive to said engine crank signal to provide power substantially only during startup of said engine, said secondary voltage regulator generating a secondary regulated output voltage in response to a secondary input voltage and being coupled to said main electrical power source; wherein said primary voltage regulator provides said primary regulated output voltage when said primary input voltage is within a primary voltage range; wherein said secondary voltage regulator provides said secondary regulated output voltage when said secondary input voltage is within a secondary voltage range and wherein said secondary voltage range includes voltages lower than said primary voltage range; and wherein said main processor board detects said engine crank signal and enters into a suspend mode in which predetermined devices controlled by said main processor board are shut down and in which said main processor board stores a current state of said predetermined devices into said volatile ram.