Patent ID: 8149862
Filing Date: 2012-04-03
Classification: H03M,H04J,H04L

Abstract:
1. A multi-protocol serializer/deserializer (SerDes) circuit for communicating between an internal logic circuit and an external link, comprising: a plurality of internal communication terminals configured to receive outbound information from the logic circuit and transmit inbound information to the logic circuit; an external communication terminal configured to transmit outbound information to the external link and receive inbound information from the external link; a select terminal configured to accept a mode select signal representing a plurality of different communication protocols, said communication protocols differing in communication signaling and format and not only in communication speed; and a single SerDes core configured to handle each of said plurality of different protocols, said SerDes core coupled to the select terminal and configured to transmit outbound data conforming with one of said plurality of communication protocols in response to the mode select signal, and to receive inbound data respective to one of said plurality of communication protocols in response to the mode select signal.