Patent ID: 7894490
Filing Date: 2011-02-22
Classification: H04J,H04L

Abstract:
1. A signal separating circuit for receiving a multiplexed signal D and separating the multiplexed signal D into data signals D 1 and D 2 of respective channels, when the multiplexed signal D is a signal obtained by time-division multiplexing data signals of two channels, of a data signal of a first channel which is an RZ (Return to Zero) signal having a pulse period T 1 and a logic “1” pulse width m and a data signal of a second channel which is an RZ signal having a pulse period T 2 and a logic “1” pulse width n, the values m and n satisfying the relation n < m, the signal separating circuit comprising: a first differentiating unit which receives said multiplexed signal D, detects a leading edge of logic “1” of the data signal of each channel and outputs a first pulse signal P a first pulse widening unit which outputs a second pulse signal P in which min(m, T 2 ) is a smaller one of said m and said T 2 ; a first pulse generating unit which judges whether said multiplexed signal D is logic “1” or logic “0” at timing of a trailing edge of said second pulse signal P a second pulse generating unit which judges whether said multiplexed signal D is logic “1” or logic “0” at timing of a trailing edge of said second pulse signal P