Patent ID: 8716151
Filing Date: 2014-05-06
Classification: H01L

Abstract:
1. A method of fabricating semiconductor devices, comprising: forming at least two adjacent gate lines on a substrate, and forming a doped area in the substrate between the two adjacent gate lines; depositing a first interlayer dielectric layer overlying the gate lines on the substrate, the first interlayer dielectric layer having a recess between the two adjacent gate lines; depositing a hard mask layer on the first interlayer dielectric layer; etching the hard mask layer, so as to form an opening in the hard mask layer, from which at least a portion of the recess above the doped area is exposed; forming a diblock copolymer over an exposed portion of the recess above the doped area, the diblock polymer being composed of a first component and a second component, wherein only the opening is filled with the diblock polymer; performing a self-assembly process on the diblock copolymer, so as to form a circular pattern of the first component above the doped area, the circular pattern of the first component being surrounded by the second component; removing the first component; and etching the first interlayer dielectric layer by using the second component and the hard mask layer as masks, until the doped area is exposed, so as to form a first contact hole for contacting the doped area, wherein the diblock copolymer over the exposed portion of the recess above the doped area before performing a self-assembly process on the diblock copolymer has a substantially rectangular shape.