Patent ID: 6362656
Filing Date: 2002-03-26
Classification: G11C,H03K

Abstract:
A semiconductor memory device, comprising:a memory cell array having a plurality of memory cells; a data output buffer coupled to the memory cell array; a programmable output driver circuit, said programmable output driver circuit comprising: first and second control signal lines; a first pull-up/pull-down driver circuit, said first pull-up/pull-down driver circuit having first and second data inputs, a first control signal input electrically coupled to said first control signal line, a first complementary control signal input and an output; a second pull-up/pull-down driver circuit, said second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively, a second control signal input electrically coupled to said second control signal line, a second complementary control signal input and an output electrically coupled to the output of said first pull-up/pull-down driver circuit; and means, responsive to an address and at least one command signal selected from the group consisting of a row address strobe signal, a column address strobe signal and a write enable signal, for generating a first control signal on the first control signal line and a second control signal on the second control signal line.