Patent ID: 6974979
Filing Date: 2005-12-13
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array including a cell unit composed of at least one memory cell and at least one select gate transistor; a word line which is connected to the memory cell and extends in a row direction on the memory cell array; a select gate line which is connected to the select gate transistor and extends in the row direction on the memory cell array; a select gate bypass line which is formed above the select gate line and extends in the row direction on the memory cell array; a bit line extending in a column direction on the memory cell array; a shunt area which is located in the memory cell array and extends in the column direction, and where a location of the at least one memory cell is forbidden; a contact section, which is located in the shunt area, for connecting the select gate bypass line to the select gate line; a first line, which is located in the shunt area, and which is connected to an area where the at least one memory cell is formed; and a second line, which is located above the first line in the shunt area, and which is connected to a source line.