Patent ID: 6112298
Filing Date: 2000-08-29
Classification: G06F

Abstract:
A method for debugging a data processing system, said data processing system having a processor which has an instruction execution pipeline, comprising the steps of:executing system code in said processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in said instruction pipeline;halting said normal operation of said processor in a manner that saves a plurality of states representative of said overlapping operations;executing debug code in said processor instruction execution pipeline to perform a debug operation on said processor; andcontinuing execution of said system code in said processor instruction execution pipeline by restoring said plurality of states in a manner that no extraneous operations occur within said data processing system; andwherein the step of halting further comprises:halting the processor on a phase boundary before at least one of the plurality of overlapping operations is complete and then storing as a first state first contents of a plurality of memory elements within the processor;executing one phase of the instruction execution pipeline and then storing as a second state second contents of the plurality of memory elements; andrepeating the step of executing one phase and then storing another state until all of the plurality of overlapping operations is complete.