Patent ID: 7041538
Filing Date: 2006-05-09
Classification: H01L

Abstract:
1. A method of fabricating a recessed channel CMOS device comprising: providing a patterned oxide layer over an SOI layer, said patterned oxide layer exposing a portion of said SOI layer; thinning the exposed portion of the SOI layer to form a recessed channel region; forming a gate dielectric on said recessed channel region; forming sacrificial nitride spacers on portions of said gate dielectric so as to protect exposed walls of said SOI layer and said oxide layer and forming a gate conductor on other portions of the gate dielectric not containing said sacrificial nitride spacers; recessing the oxide layer exposing SOI layer abutting the recessed channel region; forming source/drain diffusion regions in said exposed SOI layer abutting the recessed channel region; and removing the sacrificial nitride spacers and forming extension implant regions in said SOI layer such that said extension implant regions have an abrupt lateral profile and are located beneath the gate conductor, wherein said abrupt lateral profile comprises a lateral drop of 1 decade in concentration in 50 Å or less distance for n-extensions and 150 Å or less for p-extensions.