Patent ID: 8664057
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. A method, comprising: forming a gate layer stack above a first active region and a second active region of a semiconductor device, said gate layer stack comprising a dielectric material, at least one electrode material formed above said dielectric material and a dielectric cap material having a first thickness formed above said at least one electrode material; selectively reducing a thickness of said dielectric cap material above said second active region from said first thickness to a second thickness, wherein selectively reducing said thickness comprises removing an upper portion of said dielectric cap material from above said second active region while leaving a lower portion of said dielectric cap material above said second active region; after selectively reducing said thickness of said dielectric cap material, patterning said gate layer stack so as to form a first gate electrode structure comprising said dielectric cap material having said first thickness above said first active region and a second gate electrode structure comprising said dielectric cap material having said second thickness above said second active region; and forming a strain-inducing semiconductor alloy selectively in said first active region.