Patent ID: 6807505
Filing Date: 2004-10-19
Classification: G01R,G11C

Abstract:
An electronic circuit comprising:a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects, a main unit for implementing a normal mode function of the electronic circuit, and a test unit for testing the interconnects, the electronic circuit having a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit, wherein the test unit comprises at least one combinatorial circuit implementing at least one of an XNOR function and an XOR function with at least two function inputs and a function output, the function inputs being connected to particular I/O nodes arranged to operate as input nodes of the test circuit and the function output being connected to a particular I/O node arranged to operate as output node of the test circuit.