Patent ID: 6828611
Filing Date: 2004-12-07
Classification: H01L

Abstract:
An integrated circuit ferroelectric memory device, comprising:an integrated circuit transistor having a source region and a drain region; a ferroelectric capacitor on the integrated circuit transistor having first and second sidewalls, the ferroelectric capacitor including a first electrode consisting of a single material adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween; a contact plug directly connected to the first electrode that electrically couples the ferroelectric capacitor to the source region of the integrated circuit transistor; an insulating layer on the first and second sidewalls of the ferroelectric capacitor, the insulating layer having a surface that is substantially coplanar with an upper surface of the second electrode; a plate line directly on the ferroelectric capacitor; and a stripe line adjacent the second electrode and remote from the first electrode.