Patent ID: 6964920
Filing Date: 2005-11-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a first conductive line on a semiconductor substrate; forming an insulating layer on the semiconductor substrate and the first conductive line; forming a first photoresist pattern on the insulating layer, in order to expose parts of the insulating layer where a plurality of via holes will be formed; using the first photoresist pattern as an etching mask, etching the parts of the insulating layer where the plurality of via holes will be formed to a certain thickness so as not to expose the first conductive line; forming a second photoresist pattern on the insulating layer, in order to expose parts of the insulating layer where each via hole will be formed; using the second photoresist pattern as an etching mask, selectively etching the plurality of via holes in each of said parts of the insulating layer in order to expose the first conductive line; forming a third photoresist pattern on the insulating layer in order to expose parts of the insulating layer where the trenches will be formed; using the third photoresist pattern as an etching mask, etching trenches in the insulating layer to a certain thickness; forming a metal barrier on the insulating layer and in the via holes; and forming a plug by depositing a conductive layer sufficiently to fill the via holes, and then planarizing the conductive layer until the conductive layer is substantially coplanar with the insulating layer.