Patent ID: 9218883
Filing Date: 2015-12-22
Classification: G11C

Abstract:
1. A memory cell circuit, comprising: a memory cell having a source terminal, a drain terminal, and a gate terminal; a current source that provides channel current for the memory cell, wherein the current source is coupled to the source terminal or the drain terminal of the memory cell; a linearizing amplifier that sets a drain-to-source voltage of the memory cell using a feedback loop, from the source terminal or drain terminal of the memory cell, to the gate terminal of the memory cell; and circuitry for continuously programming the memory cell at an adaptive rate, based on a target voltage for programming, using the feedback loop to monitor the gate terminal of the memory cell and continuously adapt at least one of an amount of current that is supplied by the current source or the drain-to-source voltage of the memory cell set by the linearizing amplifier.