Patent ID: 6380016
Filing Date: 2002-04-30
Classification: H01L

Abstract:
Method for the manufacture of integrated circuits comprising the steps of:a. growing a gate dielectric layer on a silicon substrate, b. depositing a polysilicon layer over the gate dielectric layer, and polysilicon layer having: i. a plurality of first gate regions for n-channel CMOS transistors, ii. a plurality of second gate regions for p-channel CMOS transistors each of said plurality of second gate regions connected to one of said plurality of first gate regions, iii. a plurality of ROM gate regions for n-channel ROM devices, said plurality of ROM gate regions having a first group of ROM gate regions to be programmed on and a second group of ROM gate regions to be programmed off, c. masking said second gate regions with an implant mask leaving said first gate regions exposed, d. implanting n-type impurities into said first gate regions, e. masking said first gate regions with an implant mask, leaving said second gate regions exposed, and said second group of ROM gate regions exposed, f. simultaneously implanting p-type impurities into said second gate regions, and into said second group of ROM gate regions, g. masking said first plurality of gate regions, said second plurality of gate regions, and said plurality of ROM gate regions of said polysilicon layer with an etch mask, h. etching said polysilicon layer using said etch mask to form p-channel CMOS gates, n-channel CMOS gates and ROM gates, and thereafter: j. implanting into the silicon substrate: i. n-type impurities adjacent the first gate regions to form sources and drains for the n-channel CMOS transistors, ii. p-type impurities adjacent the second gate regions to form sources and drains for the p-channel CMOS transistors, iii. n-type impurities adjacent the first group of ROM gate regions to form sources and drains for the n-channel ROM devices.