Patent ID: 6437361
Filing Date: 2002-08-20
Classification: B82Y,G02F,H01L

Abstract:
A semiconductor device comprising:a quantum well lamination structure having at least one quantum well layer and at least two barrier layers alternatively laminated, the quantum well layer forming a quantum well for electron and hole and the barrier layer forming a potential barrier to electron and hole, the quantum well layer having a first heavy hole level and a second heavy hole level on the valence band side thereof; an n-type semiconductor layer in contact with one surface of said quantum well lamination structure; and a p-type semiconductor layer in contact with the other surface of said quantum well lamination structure, wherein a difference between a transition wavelength between a ground level for electron on a conduction band side of the quantum well layer and the first heavy hole level on the valence band side and a transition wavelength between the ground level for electron on the conduction band side of the quantum well layer and a second heavy hole level on the valence band side is 40 nm or smaller over the whole range from a flat band state of said quantum well lamination structure with a normal bias voltage being applied between said n-type semiconductor layer and said p-type semiconductor layer to a state with a certain reverse bias voltage being applied, the quantum well layer has a third heavy hole level on the valence band side; and a value of an overlap integral of a wave function of electron at the ground level on the conduction band side of the quantum well layer and a wave function of hole at the third heavy hole level on the valence band side reduces as the reverse bias voltage is increased, over the whole range from a state that the bias voltage is not applied between said n-type semiconductor layer and said p-type semiconductor layer to a state with a certain reverse bias voltage being applied.