Patent ID: 6615310
Filing Date: 2003-09-02
Classification: G11C,H03M

Abstract:
A circuit for accessing all memory words within a memory device for comparison with new data, comprising:a first latch and second latch combination; a plurality of memory words within a memory device; compare logic for each of the plurality of memory words; wherein the new data is launched onto the compare logic from the first latch for comparison with old data within each of the memory words prior to launching the new data from the second latch into one of the plurality of memory words; and wherein the compare logic includes a compare logic unit for each of the plurality of memory words, each compare logic unit including: an exclusive OR gate for each bit of a respective one of the plurality of memory words, each exclusive OR gate having a first input coupled to an output of the first latch and a second input coupled to an output from the respective one of the plurality of memory words; an AND gate with a plurality of inputs, each of the plurality of inputs is coupled to a respective output of a respective exclusive OR gate; and an output latch having an input coupled to an output of the AND gate.