Patent ID: 6784722
Filing Date: 2004-08-31
Classification: G05F,H03K

Abstract:
An integrated circuit, comprising:a bias generation circuit to set a desired body bias voltage; a first plurality of transistors; a first body bias grid coupled to the first plurality of transistors to provide a first body bias signal to the first plurality of transistors; a first differential difference amplifier (DDA) having first and second inputs coupled to the bias generation circuit to receive the desired body bias voltage, and a third input to receive a first local supply voltage, the first DDA configured to generate a first intermediate output signal; a first output buffer coupled to the first DDA to receive the first intermediate output signal, the first output buffer generating a first output signal having a desired gain, said first DDA having a fourth input coupled to receive said first output signal, to cause said first output signal to reference to variations in said first local supply voltage received at said third input, said first output signal coupled to said first body bias grid to provide said first body bias signal to the first plurality of transistors; a second plurality of transistors; a second body bias grid coupled to the second plurality of transistors to provide a second body bias signal to the second plurality of transistors; a second DDA having first and second inputs coupled to the bias generation circuit to receive the desired body bias voltage, and a third input to receive a second local supply voltage, the second DDA configured to generate a second intermediate output signal; and a second output buffer coupled to the second DDA to receive the second intermediate output signal, the second output buffer generating a second output signal having a desired gain, said second DDA having a fourth input coupled to receive said second output signal, to cause said second output signal to reference to variations in said second local supply voltage received at said third input of said second DDA, said second output signal coupled to said second body bias grid to provide said second body bias signal to the second plurality of transistors.