Patent ID: 6392305
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A chip scale package (CSP) of semiconductor comprising:a chip, having a first surface and a second surface wherein the first surface of the chip has a gate region and a first source/drain region while the second surface of the chip has a second source/drain region; a first conductive block, disposed on the first surface of the chip and electrically connected to the gate region; a second conductive block, disposed on the first surface of the chip and -electrically connected to the first source/drain region; a third conductive block, disposed on the second surface of the chip and electrically connected to the second source/drain region; and an insulating material, over the first surface to be filled between the first conductive block and the second conductive block, and over the second surface to be filled between the third conductive block and the chip, wherein the insulating material between the first conductive block and the second conductive block are exposed.