Patent ID: 7349259
Filing Date: 2008-03-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell unit having a plurality of memory cells connected in series; a first select transistor connected to the memory unit at a first end; a bit line connected to said memory cell unit via the first select transistor; and a control circuit to apply a first voltage to a first bitline, a second voltage to a second bitline and a third voltage to a third bitline when a programming voltage is applied to a selected word line, the first voltage being lower than the second voltage, the second voltage being lower than the third voltage, the programming voltage being higher than a power supply voltage, wherein the control circuit applies the first voltage to the first and second bitlines when starting applying the third voltage to the third bitline, and then the control circuit applies the first and second voltages to the first and second bitlines, respectively.