Patent ID: 7296167
Filing Date: 2007-11-13
Classification: G06F

Abstract:
1. A node comprising, integrated onto a single integrated circuit chip: a plurality of processor cores; and a node controller coupled to the plurality of processor cores, wherein the node controller is coupled to receive an external request transmitted to the node, and wherein the node controller is configured to transmit a corresponding request to at least a subset of the plurality of processor cores responsive to the external request, and wherein the node controller is configured to receive respective responses from each processor core of the subset, each processor core transmitting the respective response independently in response to servicing the corresponding request and capable of transmitting the response on different clock cycles than other processor cores, and wherein the node controller is configured to transmit an external response to the external request responsive to receiving each of the respective responses, and wherein the external request is a system management message requesting that a power management state be entered by each of the plurality of processor cores.