Patent ID: 6625242
Filing Date: 2003-09-23
Classification: H03L

Abstract:
A delay locked loop that generates an advanced clock signal that is synchronized with a reference clock signal, comprising:a phase sensing pump that senses a phase difference between a signal related to the advanced clock signal and the reference clock signal, to supply a control signal that controls a voltage level in accordance with the direction of the phase difference; a variable delay circuit that delays the reference clock signal, based on the voltage level of the control signal supplied from the phase sensing pump; a phase inversion controller that compares the phase of the reference clock signal with the phase of a delayed clock signal delayed by the variable delay circuit, to generate a phase shift control signal; and a phase shifter that generates the advanced clock signal by shifting the phase of the delayed clock signal by the reference phase value when a phase difference of the delayed clock signal with respect to the reference clock signal is more than a reference phase value, and without shifting the phase of the delayed clock signal when a phase difference of the delayed clock signal with respect to the reference clock signal is less than the reference phase value.