Patent ID: 6643794
Filing Date: 2003-11-04
Classification: G11C

Abstract:
A semiconductor storage unit comprising:a memory cell array that is sectioned into a plurality of blocks; a redundant memory cell; and a redundant memory cell selection circuit for replacing a defective memory cell in the memory cell array with the redundant memory cell in such a manner that the replacement is correlated with a first block selection signal for selecting a prescribed block from among the plurality of blocks and a second block selection signal that is reverse in logical value to the first block selection signal, wherein the redundant memory cell selection circuit comprises: first field-effect transistors to whose gates the first block selection signal is input; second field-effect transistors to whose gates the second block selection signal is input and that are different in channel conductivity type from the first field-effect transistors; and fuses connected between the sources or drains of the first field-effect transistors and those of the second field-effect transistors.