Patent ID: 7178000
Filing Date: 2007-02-13
Classification: G06F

Abstract:
1. A system, comprising: a system memory; a system data bus for providing, in a sequence, read data words retrieved from the system memory and write data words for storage in such system memory, such read data words and write data words being provided on the system data bus at a predetermined system clock rate; a memory data bus connected to the system memory; a system memory controller for enabling the system memory to store therein the write data words on the memory data bus at a rate twice the system clock rate and for enabling read data words stored in the system memory to be retrieved therefrom and provided on the memory data bus at twice the system clock rate; a synchronizer, coupled between the system data bus and the memory data bus, for enabling the read data words retrieved from the system memory at a rate twice the system clock rate to be provided on the system data bus at the system clock rate and for enable write data words provided on the system data bus at the system clock rate to be provided on the memory data bus at twice the system clock rate; a trace buffer section comprising: