Patent ID: 6247118
Filing Date: 2001-06-12
Classification: G06F

Abstract:
A method for error recovery in a RISC data processing system having a pipeline history cache and a pipeline including multiple stages, comprising the steps of:fetching an instruction having an instruction fetch address;storing the instruction fetch address in the pipeline history cache, wherein the pipeline history cache comprises a memory register file including a stage register for each pipeline stage;executing or at least partially executing the instruction;validating the execution or partial execution of the instruction;implementing a state change based upon validating the instruction;if an error is detected in said step of validating the execution of the instruction, then performing the following steps:fetching the instruction utilizing the instruction fetch address stored in the pipeline history cache, andre-executing or at least partially re-executing the instruction; andwherein said step of storing the instruction fetch address in the pipeline history cache includes storing the instruction fetch address in a first in, first out register file.