Patent ID: 6486034
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A process for manufacturing an LDMOS device, comprising:providing a Pâˆ’ substrate; on said substrate, depositing a first epitaxial layer of Nâˆ’ silicon having a first resistivity; on said first epitaxial layer of Nâˆ’ silicon depositing a second epitaxial layer of Nâˆ’ silicon having an upper surface and a second resistivity that is lower than said first resistivity, whereby said first and second epitaxial layers have a mean resistivity that is approximately equal to that of an LDMOS device that has only one Nâˆ’ epitaxial layer; forming a Pâˆ’ base region in the second epitaxial layer; and forming a layer of gate oxide covered by a polysilicon gate, an N+ source in the base region and an N+ drain in the second Nâˆ’ epitaxial layer.