Patent ID: 8351278
Filing Date: 2013-01-08
Classification: G11C

Abstract:
1. A jam latch device for a data node, comprising: a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; and an isolation device that selectively decouples the feedback inverter from a first power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the first power supply rail coincides with resetting the data node to the first logic state; wherein the data node comprises an output node of a memory array, and wherein the reset device comprises a first n-type field effect transistor (NFET) that resets the data output node to a logic low state.