Patent ID: 6921716
Filing Date: 2005-07-26
Classification: H01L

Abstract:
1. A wafer bumping process, comprising the steps of: providing a wafer, said wafer comprising a plurality of bonding pads and a passivation layer covering a surface of said wafer and exposing said bonding pads; forming a first under bump metallurgy layer covering said passivation layer and said bonding pads; forming a first patterned photoresist layer on said first under bump metallurgy layer, said first patterned photoresist layer comprising a plurality of first openings corresponding to said bonding pads and exposing a portion of said first under bump metallurgy layer; forming a second under bump metallurgy layer within said first openings; forming a second patterned photoresist layer on said first patterned photoresist layer, said second patterned photoresist layer comprising a plurality of second openings, said second openings being larger than said first openings to expose a portion of said second under bump metallurgy layer; filling said second openings with a solder material, wherein the solder material covers said exposed portion of said second under bump metallurgy layer; reflowing said solder material to form a plurality of solder bumps; after reflowing said solder material, removing said second patterned photoresist layer and said first patterned photoresist layer to expose a portion of said first under bump metallurgy layer; and removing said exposed portion of said first under bump metallurgy layer.