Patent ID: 9070752
Filing Date: 2015-06-30
Classification: C25D,H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming an interlayer dielectric on a substrate including a cell array region and a peripheral circuit region; etching the interlayer dielectric to form a plurality of cell recess regions in the cell array region and to form a plurality of dummy recess regions in the cell array region between the cell recess regions and the peripheral circuit region; forming a seed layer on the interlayer dielectric; and performing an electroplating process to form a plating layer filling the cell recess regions and the dummy recess regions, wherein the cell array region comprises a cell pattern region, in which the cell recess regions are formed, and a dummy pattern region, in which the dummy recess regions are formed, wherein each of the cell recess regions is a linear groove continuously extending along a first direction, wherein the dummy recess regions comprise a plurality of grooves that discontinuously extend along the first direction and are separated from one another by the interlayer dielectric, and wherein an area occupied by the interlayer dielectric in the dummy pattern region is less than that in the peripheral circuit region and greater than that in the cell pattern region.