Patent ID: 6794267
Filing Date: 2004-09-21
Classification: H01L

Abstract:
A process of manufacturing a semiconductor device, the process comprising:forming elements on a wafer, and thereafter forming an interlayer insulating film on the wafer over at least the elements; flattening the interlayer insulating film formed by chemical mechanical polishing, wherein a stopper layer is formed only at an edge region of the device so that no layer portion deposited along with the stopper layer remains on the device during the chemical mechanical polishing of the interlayer insulating film at any location other than as part of the stopper layer at the edge region of the device, the stopper layer preventing the interlayer insulating film from being excessively polished by the chemical mechanical polishing at the edge region of the device compared to a remainder of the interlayer insulating film, wherein the stopper layer is formed before or after forming the interlayer insulating film.