Patent ID: 8984260
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A method for executing scalar instructions in a processor including a vector execution unit including a plurality of processing lanes, each processing lane configured to perform an operation of a vector instruction to generate a processing lane result, and a dot product adder configured to sum the processing lane results to generate a vector instruction result, the method comprising: analyzing instructions stored in an instruction buffer associated with the processor utilizing a predecode logic coupled to the instruction buffer to identify a plurality of scalar instructions in an instruction stream for which a functionally equivalent vector instruction exists, wherein the plurality of scalar instructions includes a subset of scalar instructions generating independent results and a scalar add instruction for performing an add operation of the independent results; generating the functionally equivalent vector instruction based on the plurality of scalar instructions, wherein the vector instruction is configured to perform an operation based on each scalar instruction of the subset of scalar instructions and an add operation based on the scalar add instruction; substituting the functionally equivalent vector instruction for the plurality of scalar instructions in the instruction stream; and executing the functionally equivalent vector instruction in the vector execution unit to generate a vector instruction result by: