Patent ID: 6279072
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A memory control circuit for a computer system, comprising;a memory system having a plurality of memory locations corresponding to respective addresses;an error correction circuit;an error correction memory;a data bus coupled to a first set of memory locations of the memory system; anda coupling device coupling a second set of memory locations of the memory system to the error correction circuit, the coupling device comprising:a first switching circuit having a first data port coupled to the second set of memory locations of the memory system, a second data port coupled to the data bus, a third data port coupled to the error correction circuit, and a mode select input, the switching circuit being operable responsive to a first mode select signal to couple the first data port to the second data port, and being operable responsive to a second mode select signal to couple the first data port to the third data port; anda second switching circuit having a first data port coupled to the third data port of the first switching circuit, a second data port coupled to the error correction memory, a third data port coupled to the error correction circuit, and a control input, the second switching circuit being operable responsive to a first control signal to couple the first data port to the third data port, and being operable responsive to a second control signal to couple the second data port to the third data port.