Patent ID: 8369145
Filing Date: 2013-02-05
Classification: G06F,G11C

Abstract:
1. A processor based system comprising: an interface bus; a control module in communication with a processor via the interface bus; a controller in communication with the control module, wherein the control module is configured to perform operations controlled by the controller; a memory array comprising a plurality of memory cells, each programmable to store an amount of electric charge representative of a desired state selected from at least three sequential data states, wherein the memory array is in communication with the control module via a memory device bus; wherein the control module comprises at least one data buffer for receiving original data intended to be programmed into the memory cells and further comprises over-program detection circuitry selected from the group consisting of at least one look-up table and decode logic circuits, wherein the over-program detection circuitry is used to generate an overprogrammed signal representative of one or more of the memory cells having been erroneously programmed to one of the sequential data states which is subsequent to the desired state.