Patent ID: 9041119
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A method comprising: forming a first transistor in a first region of a substrate by forming a first gate stack on top of said first region of said substrate, said first region including a source region and a drain region of said first transistor; forming a second transistor in a second region of said substrate by forming a second gate stack on top of said second region of said substrate, said second region including a source region and a drain region of said second transistor; covering said first transistor with a mask, said mask does not cover said second transistor; creating recesses in said source and drain regions of said second transistor; removing said mask from said first transistor; and forming stressors in said recesses through an epitaxial growing process, said epitaxial growing process causes silicon-germanium or silicon-carbide to be epitaxially formed on top surfaces of said source and drain regions, of said first transistor, that are exposed after removing said mask.