Patent ID: 8951873
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate comprising a first material having a first etch rate and a first oxidation rate; a gate structure overlying the semiconductor substrate; a channel region in the semiconductor substrate and underneath the gate structures; stressor regions formed in the semiconductor substrate proximate the gate structure and directly adjacent to the channel region comprising a second material having a second etch rate that is different from the first etch rate and a second oxidation rate that is different from the first oxidation rate, wherein the stressor regions have a thickness in a direction perpendicular to a top surface of the semiconductor substrate that is greatest directly adjacent to the channel region and that decreases in thickness with increasing distance from the channel region in a direction parallel to the top surface of the semiconductor substrate; and a silicon material overlying an entirety the stressor regions and comprising a third material having the first etch rate and the first oxidation rate, the silicon material fully encapsulating the stressor regions, wherein an entirety of a top surface of the silicon material overlying the stressor regions and the top surface of the semiconductor substrate underneath the gate structure are co-planar with respect to one another.