Patent ID: 7852686
Filing Date: 2010-12-14
Classification: G11C

Abstract:
1. A memory circuit comprising: at least one memory cell for storing a charge representative of a datum, the memory cell coupled to a row select signal and a column signal and outputting a small voltage on the column signal responsive to the row select signal; a sense amplifier circuit coupled to the column signal and to another complementary column signal for receiving a small signal differential voltage, having a cross coupled latch comprised of two inverters receiving the small signal differential voltage and having outputs coupled to the column signal and to the complementary column signal, and receiving a pull down control signal and a pull up control signal; and a differential signal generator circuit coupled to a positive supply voltage and to a negative supply voltage and receiving an enable signal, the differential signal generator circuit generating the pull down control signal and pull up control signal substantially instantaneously, responsive to the enable signal; and wherein the differential signal generator circuit further comprises: a sense amplifier equalization circuit coupled to the pull up control signal and the pull down control signal, the sense amplifier equalization circuit operable to equalize the pull up control signal and the pull down control signal to a first potential in a pre-charge operation; and wherein the sense amplifier equalization circuit is coupled to the first node and to the second node and the sense amplifier equalization circuit further comprises a first transistor receiving the first node at a control input and coupled between the pull up control signal and a first voltage terminal, the first voltage terminal receiving a positive voltage that is one selected from a first positive voltage and a second positive voltage that is greater than the first positive voltage by a boost voltage; and a second transistor having a control input coupled to the second node and coupled between the pull down control signal and a second voltage terminal, the second voltage terminal receiving a ground voltage that is one selected from a first ground voltage and a second ground voltage that is lower than the first ground voltage by a boost voltage.