Patent ID: 6646323
Filing Date: 2003-11-11
Classification: H01L

Abstract:
An integrated circuit MIM capacitor, comprising:a primary electrically insulating layer overlying a substrate; a first electrically conductive layer overlying the primary electrically insulating layer, wherein the first electrically conductive layer and the primary electrically insulating layer have a plurality of secondary enlarged vias defined therein, wherein the secondary enlarged vias extend down to the substrate, and whereby portions of the first electrically conductive layer interlace the secondary enlarged vias; a first electrically insulating layer overlying the first electrically conductive layer, wherein the first electrically insulating layer has a primary enlarged via defined therein, whereby the primary enlarged via contains the plurality of secondary enlarged vias and defines a capacitor region; a first electrode layer overlying the first electrically insulating layer, the first electrically conductive layer, the primary insulating layer, and the substrate in a generally conformal manner, whereby the first electrode layer makes electrical contact to the portions of the first electrically conductive layer which interlace the secondary enlarged vias at a plurality of points; a dielectric layer overlying the first electrode layer in a generally conformal manner; and a second electrode layer overlying the dielectric layer, wherein the second electrode layer fills the secondary enlarged vias and overlies the primary enlarged via in a generally conformal manner, thereby defining a capacitor within the capacitor region.