Patent ID: 6812872
Filing Date: 2004-11-02
Classification: H03L,H03M

Abstract:
A data combiner comprising:a. a first data-combiner output terminal; b. a second data-combiner output terminal; c. an inductor connected between the first and second data-combiner output terminals; d. a first current-steering circuit including: i. a first clock terminal receiving a first clock signal of a first clock phase; ii. a second clock terminal receiving a second clock signal of a second clock phase; iii. a first data terminal receiving a first series of data bits; iv. a second data terminal receiving a second series of data bits synchronized with the first set of data bit so that pairs of data bits arrive at the first and second data terminals substantially simultaneously; and v. a data output terminal; vi. wherein the current-steering circuit combines the first and second data streams into a third series of data bits and provides the third series of data bits on the data output terminal; and e. a current source connected to the data output terminal.