Patent ID: 8896472
Filing Date: 2014-11-25
Classification: H03M

Abstract:
1. An N-bit digital-to-analog converter (DAC) comprising: 2 (N−M) stages associated with (N−M) least significant bits of the DAC, each of the (N−M) stages generating the current and comprising a resistive network, each of the (N−M) stages further comprising a pair of switches adapted to deliver the current generated in the stage to the stage's associated resistive network in response to differential data, each resistive network operable to scale the current it receives and deliver the scaled current defined by a binary weight of its associated stage, the (N−M) stages delivering their scaled currents to the pair of current summing nodes; and an impedance attenuator comprising a differential amplifier coupled to the pair of summing nodes and adapted to maintain an impedance of each of the current summing nodes and a voltage difference between the current summing nodes within a range defined by a gain of the differential amplifier.