Patent ID: 8952457
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. An ESD protection circuit, comprising: a substrate of a first conductivity type; an annular well region of a second conductivity type, disposed in the substrate; two first regions of the first conductivity type, disposed in the substrate and surrounded by the annular well region, wherein the first regions are straight, isolated and parallel with each other along a direction, one of the first regions are coupled to a first voltage source, and the other of the first regions is coupled to a substrate triggering circuit; and at least one transistor, disposed on the substrate between the two first regions and directly contacted with the substrate of the first conductivity type, wherein the at least one transistor comprises a metal-oxide-semiconductor transistor of the second conductivity type comprising a source, a gate and a drain, the source is coupled to the first voltage source, and the annular well region and the drain are coupled to a second voltage source.