Patent ID: 6292873
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A high-performance dual-ported shared memory that provides independent storage and retrieval operations on blocks of computer words to a first computer bus and to a second computer bus without introducing wait states in either computer bus following initiation of a storage or retrieval operation, both computer buses controlled by a clock and providing transfer of a computer word having a first width during each clock cycle, the high-performance dual-ported shared memory comprising:a first port connected to the first computer bus;a second port connected to the second computer bus;a memory component that provides an address space of memory words having a second width equal to twice the first width; anda multiplexer/demultiplexer component that combines pairs of computer words received from the first computer bus via the first port into memory words and that combines pairs of computer words received from the second computer bus via the second port into memory words for storage in the memory component and that separates memory words retrieved from the memory component into pairs of computer words, both computer words of each pair provided by the multiplexer/demultiplexer component to either the first or the second computer bus via the first or second port, the multiplexer/demultiplexer component buffering computer words so that, on each clock cycle, the multiplexer/demultiplexer component transfers a computer word to, or receives a computer word from, each computer bus and transfers a memory word to, or receives a memory word from, the memory component.