Patent ID: 7996715
Filing Date: 2011-08-09
Classification: G06F,Y10S

Abstract:
1. Multi nodal computer system comprising: a plurality of nodes each of which includes chips of different types, wherein one of said chips on each node is a clock chip which is connected to the other chips included on that node via a local communication path and is central to the other chips on that node; a system communication path that connects the clock chips on each node; the clock chip is capable of providing a clock signal for synchronizing the other chips on the node; the other chips on each node are capable of sending a check stop request to the clock chip in case of a malfunction, wherein the check stop request is selected from a group including: a system check stop, a node check stop, and a chip check stop; the clock chip is capable of selectively disabling one or more chips that caused a malfunction on the node; in case of a system check stop, the system communication path drops and the local communication path drops, wherein the local communication path drops after a delay following the system communication path drop; in case of a node check stop, any processor unit chips of the node are stopped while any cache chips remain active; and in case of a chip check stop, the other chips on each node capable of sending a chip check stop request communicates to other nodes over the system communication path, which continue to run, about the chip check stop, and in case the chip check stop is received from a processor unit chip or a Memory Bus Adapt (MBA) chip of a first node, a cage controller shifts out data from the MBA chip and the processor unit chip into main memory of the first node, a processor unit chip of a second node processes the shifted out data, and the cage controller escalates the chip check stop condition to a system check stop condition.