Patent ID: 6260998
Filing Date: 2001-07-17
Classification: G01R

Abstract:
A method for testing an electronic module to evaluate solder joint failures caused by thermally induced stress, the method comprising:determining a thermal shock endurance test profile that represents field temperature conditions;estimating time/cycles to failure of solder joints in the electronic module as a function of the field temperature conditions represented by the thermal shock endurance test profile using numerical simulation techniques;selecting a design life target and a reliability target for the electronic module;comparing the design life target of the electronic module with the estimated time/cycles to failure of at least one solder joint in the electronic module;determining between robust, marginal, and non-robust electronic module designs based on the design life duration of the electronic module and the estimated time/cycles to failure of the at least one solder joint in the electronic module; anddetermining an accelerated thermal shock endurance test specification including temperature profile and test duration for testing a marginal electronic module design, wherein the accelerated thermal shock endurance test specification is determined as a function of the field temperature conditions represented by the thermal shock endurance test profile and the design life target and the reliability target of the electronic module.