Patent ID: 6090700
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method for forming interconnects in an integrated circuit, the method comprising:patterning a plurality of first conductive contacts over a substrate;forming a first dielectric layer over said first conductive contacts and said substrate;forming a silicon nitride layer atop said first dielectric layer, said silicon nitride layer having a thickness of about 3500 to 6000 angstroms;forming a plurality of openings through selected portions of said silicon nitride layer and said first dielectric layer such that said first conductive contacts are exposed;filling said plurality of openings with a second conductive layer;etching back the second conductive layer until the surfaces of the second conductive layer in the openings are near the boundary of said silicon nitride layer and said first dielectric layer; andremoving said silicon nitride layer.