Patent ID: 6417689
Filing Date: 2002-07-09
Classification: G06F,H03K

Abstract:
A computer-implemented method for placing output signals in output pins of function blocks of a programmable logic device, each function block including one or more output pins and the output signals including signals of one or more voltage levels, comprising:grouping the output signals into logical output banks (LOBs), the output signals in each LOB having a common voltage level; associating one or more function blocks with each LOB; and for each function block and a current LOB with which the function block is associated, selecting one or more unplaced signals for placement in the function block as a function of a number of unplaced output signals in the current LOB, a number of output pins in function blocks associated with LOBs other than the current LOB, and a number of output pins in all function blocks that are associated with the current LOB and that have no assigned output signals.