Patent ID: 6938225
Filing Date: 2005-08-30
Classification: G01R

Abstract:
1. An apparatus comprising: a double-edge-triggered flip-flop (DETFF) scan cell including at least first and second latches coupled to function as a double-edge triggered flip-flop in a functional mode, the at least first and second latches including first and second dual-ported latches, each of the dual-ported latches to receive a test mode clock signal at a time when an integrated circuit that includes the DETFF scan cell is in a test mode, and a functional mode clock signal at a time when the integrated circuit that includes the DETFF scan cell is in a functional mode; a hold scan circuit coupled to an output of the DETFF scan cell to provide hold scan capability to hold a functional mode data value during a test mode; and first and second tri-state drivers, the first tri-state driver being coupled to an output of the first dual-ported latch, the second tri-state driver being coupled to an output of the second dual-ported latch, at least one of the first and second tri-state drivers to be coupled to the hold scan circuit, the hold scan circuit comprising a sustain circuit.