Patent ID: 6107139
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of forming a capacitor for a DRAM memory cell, the method comprising the steps of:forming an interlayer dielectric;forming a nitride layer over said interlayer dielectric layer;forming a contact hole in said nitride layer and said interlayer dielectric;forming a first polysilicon layer in said contact hole and over said nitride layer;forming an oxide layer over said first polysilicon layer, patterning and etching said oxide layer and said first polysilicon layer to form an intermediate structure over said contact hole;forming first polysilicon spacers on the sides of said intermediate structure;removing a portion of said oxide layer of said intermediate structure so that the tops of said first polysilicon spacers are exposed;forming nitride spacers on the sides of said first polysilicon spacers, said nitride spacers not extending to the top of said first polysilicon spacers;forming second polysilicon spacers on said nitride spacers and said first polysilicon spacers;removing said oxide layer;removing said nitride spacers and said nitride layer; andforming a dielectric layer and a top conductive layer over the bottom storage node.