Patent ID: 6271556
Filing Date: 2001-08-07
Classification: H01L

Abstract:
An integrated circuit comprising:a semiconductor substrate;a first recessed region and a second recessed region in said semiconductor substrate, said first recessed region having sides extending from a first bottom surface, said second recessed region having sides extending from a second bottom surface;a first insulating layer adjacent to said semiconductor substrate and covering said first bottom surface and a portion of at least one of said sides of said first recessed region, and a second insulating layer defined overlying said second recessed region;a field effect transistor, said field effect transistor including a first source/drain region adjacent to said first recessed region and a second source/drain region adjacent to said second recessed region;a first conductor defined within said first recessed region, said first conductor being coupled to said first source/drain region to define a bit-line structure; anda second conductor defined within said second recessed region, said second conductor being coupled to said second source/drain region to define a capacitor structure.