Patent ID: 9170569
Filing Date: 2015-10-27
Classification: G05B,G06F,H04L

Abstract:
1. A method for electing active master circuitry from two redundant primary and secondary master circuitry, the primary and secondary master circuitry being directly connected to a fieldbus and linked together by a terminal cable and each having an active operating mode and a standby mode with active monitoring, and also having one and the same interface, wherein each of the primary and secondary master circuitry also has one and the same state machine, a pair of primary output/input, and a pair of secondary output/input, the method comprising: designating one of the primary and secondary master circuitry as the active master circuitry, and the other master circuitry as the standby master circuitry with active monitoring; linking, by the terminal cable, the pair of primary output/input of the primary master circuitry to the pair of secondary output/input of the secondary master circuitry instead of the pair of primary output/input of the secondary master circuitry, wherein the linking establishes a directional relation that designates a default state of the primary master circuitry as the active operating mode and designates a default state of the secondary master circuitry as the standby mode at a startup of the primary master circuitry and the secondary master circuitry; detecting on the secondary input of the secondary master circuitry, by the secondary master circuitry, a presence of the primary master circuitry if the primary master circuitry is capable of operating; proposing, by the state machine of the secondary master circuitry, the standby mode with the active monitoring when the presence of the primary master circuitry is detected; detecting on the primary input of the primary master circuitry, by the primary master circuitry, a presence of the secondary master circuitry if the secondary master circuitry is capable of operating; and proposing, by the state machine of the primary master circuitry, the active operating mode when the presence of the secondary master circuitry is detected.