Patent ID: 7061283
Filing Date: 2006-06-13
Classification: H04L

Abstract:
1. A circuit comprising: a first driver circuit coupled to a programmable current source, and receiving a rail-to-rail differential input signal; a programmable delay circuit coupled to the first driver circuit and configured to delay the rail-to-rail differential input signal; a second driver circuit coupled to the programmable delay circuit; and a summation circuit coupled to the first driver circuit and the second driver circuit and outputting a small signal differential output signal; a pulse generator receiving the rail-to-rail differential input signal and a differential output signal of the programmable delay circuit; and a third driver circuit coupled to the pulse generator wherein the small signal differential output signal of the summation circuit is produced by adding together a differential output signal of the first driver circuit to a differential output signal of the second driver to a differential output signal of the third driver.