Patent ID: 6356494
Filing Date: 2002-03-12
Classification: G11C

Abstract:
An automatic precharge apparatus of a semiconductor memory device, comprising:an automatic precharge signal generating means for receiving external control signals and generating an internal precharge command signal, and outputting an automatic precharge signal by using the internal precharge command signal signal and control signals related to a bust operation, a ras precharge signal generating means for receiving the automatic precharge signal and then generating a ras precharge signal, a delay means for outputting a write recovery signal after a predetermined constant delay time, which is disabled in a reading operation and only enabled in a writing operation, when the internal precharge command signal is input during a writing/reading operation, a ras generating means for generating a ras signal without a delay when inputting an external precharge command signal, but generating the ras signal after the predetermined constant delay time in response to the write recovery signal when inputting the ras precharge signal.