Patent ID: 8830760
Filing Date: 2014-09-09
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a plurality of memory cells; and a sense amplifier including a sense node that transmits a voltage according to a current flowing in a corresponding one of the memory cells and configured to detect a logic of data based on the voltage of the sense node, wherein a write sequence of writing data in a selected memory cell among the memory cells is performed by repeating write loops each including a write stage of writing data in the selected memory cell and a verify read stage of verifying that the data has been written in the selected memory cell by performing discharge from the sense node through the selected memory cell, and the sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop among the write loops, a period of discharge from the sense node to the selected memory cell at the verify read stage in a second write loop following the first write loop.