Patent ID: 8151136
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A digital processing device comprising a main processor and one or more application processors, the digital processing device comprising: a nonvolatile memory, the nonvolatile memory being coupled to the main processor through an MP-NM bus, the nonvolatile memory comprising a code data area and a backup area, first code data being written in the code data area, second code data being backed up in the backup area, the second code data being identical to the first code data; and a shared memory, the shared memory being shared by the main processor and the application processor, the first code data or a third code data being written in the shared memory, wherein if the first code data has an error, the main processor writes in the shared memory the second code data or the third code data that is error-corrected by a predetermined error correcting method, and the main processor or the application processor performs an operation corresponding to the third code data, and wherein the shared memory has two or more ports, and one of the ports is assigned to the main processor and another one of the ports is assigned to the application processor.