Patent ID: 7214990
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A Static Random Access Memory (SRAM) cell comprising: a first NMOS transistor; a first PMOS transistor, said first PMOS transistor and said first NMOS transistor including a first common gate; a second NMOS transistor; a second PMOS transistor, said second PMOS transistor and said second NMOS transistor including a second common gate; a first resistor, one end of said first resistor electrically coupled to said drain of said first PMOS transistor and said drain of said first NMOS transistor, and the other end of said first resistor electrically coupled to said second common gate; a second resistor, one end of said second resistor electrically coupled to said drain of said second PMOS transistor and said drain of said second NMOS transistor, and the other end of said second resistor electrically coupled to said first common gate; a pre-metal dielectric layer that extends over said first and second NMOS transistors, said first and second PMOS transistors and said first and second common gates, an opening extending through said pre-metal dielectric layer; a first contact that extends through said pre-metal dielectric layer so as to electrically couple to said drain of said first NMOS transistor and said drain of said first PMOS transistor; and a first metal segment that extends over said pre-metal dielectric layer and extends over said first contact such that said first metal segment is electrically coupled to said first contact, said first resistor extending between said second common gate and said first metal segment so as to resistively couple said second common gate to said first metal segment.