Patent ID: 7882284
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A compute unit with an internal bit First In First Out (FIFO) circuit, the compute unit comprising: an arithmetic logic unit; a local memory array comprising a lookup table addressable only within the compute unit; a configuration register including a FIFO base address field, a length field, and a read/write mode field for configuring a portion of said lookup table as a bit FIFO circuit providing a bit stream having an arbitrary number of bits; and a read/write pointer register responsive to an instruction having a lookup table identification field, a length of bits field, and a register extract/deposit field for selectively transferring in a single cycle between said bit FIFO circuit and a data register a bit field having a length specified in the length of bits field, wherein the arithmetic logic unit, the lookup table, the configuration register, and the read/write pointer register intercommunicate directly rather than over a system bus.