Patent ID: 7957172
Filing Date: 2011-06-07
Classification: G11C

Abstract:
1. A system for retaining M bits of state data of an integrated circuit during power down, said system comprising: M serially coupled scan flip flops divided into M/N groups, each of said groups containing a merged scan flip flop and a final scan flip flop, said M serially coupled scan flip flops containing said M bits of state data; said merged scan flip flop in each of said groups being coupled to a respective read port of a memory unit, and said final scan flip flop of each of said groups being coupled to a respective write port of said memory unit, said system thereby enabling said memory unit to save said M bits of state data in N clock cycles; wherein said M serially coupled scan flip flops are powered by a first power supply and wherein said memory unit is powered by a second power supply.