Patent ID: 7936636
Filing Date: 2011-05-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a data output unit configured to output data in synchronization with a data output clock; and a clock control unit configured to selectively transfer the data output clock to the data output unit under the control of a read command and an internal read command generated by domain-crossing of the read command, wherein the clock control unit comprises: a first controller configured to generate a first control signal for controlling the data output clock to be transferred to the data output unit using the read command and the internal read command; a second controller configured to generate a second control signal for controlling the data output clock to be transferred to the data output unit using an output enable signal; and a clock buffer configured to receive the first control signal and the second control signal and to transfer the data output clock to the data output unit in response to the first control signal and the second control signal.