Patent ID: 6376304
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of fabricating a semiconductor memory device including a memory cell array region comprised of a plurality of first MISFETs formed on a main surface of a semiconductor substrate in said memory cell array region and a peripheral circuit region comprised of a plurality of second MISFETs formed on the main surface of said semiconductor substrate in said peripheral circuit region, comprising:forming a first interlayer insulating film covering said plurality of first MISFETs, said plurality of second MISFETs and the main surface of said semiconductor substrate; forming a plurality of first interconnect lines and bit liens on said first interlayer insulating film; forming a second interlayer insulating film covering said plurality of first interconnect lines, said bit lines and the surface of said first interlayer insulating film; forming a third interlayer film, covering only the surface of said second interlayer insulating film over said peripheral circuit region to effect a recess in said memory cell array region; forming a plurality of storage capacitors on the surface of said second interlayer insulating film of said memory cell array region and inside the recess of said third interlayer insulating film; forming a fourth interlayer insulating film covering said plurality of storage capacitors and an upper surface of said third interlayer insulating film; and forming a plurality of second interconnect lines on said fourth interlayer insulating film.