Patent ID: 6377498
Filing Date: 2002-04-23
Classification: G11C

Abstract:
A nonvolatile ferroelectric memory device, comprising:a main cell array including first and second memory arrays each having a plurality of cell arrays; first and second local wordline drivers between the first and second memory arrays that respectively output a driving signal for cells of the first and second memory arrays; a main wordline driver that provides a main control signal to activate one of the first and second local wordline drivers; a redundancy cell array including first and second redundancy memory arrays each having a plurality of cell arrays, wherein the redundancy cell array corrects an error generated when a row address of the main cell array is selected; first and second redundancy local wordline drivers that respectively output the driving signal for cells in the first and second redundancy memory arrays; a row redundancy driving circuit connected to the main wordline driver to provide an inactive signal to the main wordline driver when the error is generated for the selected the row address of the main cell arrays and further connected to the first and second redundancy local wordline drivers to provide a redundancy control signal to the first and second redundancy local wordline drivers; and a decoder connected to the first and second local wordline drivers of the main cell array and the first and second redundancy local wordline drivers of the redundancy cell array to provide the driving signal corresponding to any cell of the main cell array and the redundancy cell array.