Patent ID: 7345947
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A system, comprising: (a) a microprocessor having a memory array with word-line rows each including: (i) bit cells coupled to a word-line node and to a virtual ground node, the word-line node to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive, the virtual ground node to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode, and (ii) a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes, wherein current leakage in the bit cells and word-line driver circuit is reduced during the standby mode with the virtual ground node being at the elevated voltage; and (b) a wireless interface component to be coupled to the microprocessor chip to establish a wireless link between the microprocessor and a device outside of the system.