Patent ID: 6261972
Filing Date: 2001-07-17
Classification: H01L,Y10S

Abstract:
A process for forming thin and thick gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a silicon substrate;b) implanting a dopant through said sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer;d) subjecting said nitrided silicon layer to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through said photoresist;g) stripping said photoresist and said sacrificial oxide layers; andh) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas of the substrate to form said thin and thick oxides.