Patent ID: 8809182
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A method of providing stress relief to lead (Pb)-free controlled collapse chip connections (C4s) in an integrated circuit chip comprising the steps of: providing an integrated circuit chip with its face covered with at least one insulating layer overlying top metallization of the integrated circuit chip, wherein the at least one insulating layer Comprises a first insulating layer having a first thickness on and contacting, the top metallization and a second insulating layer having a second thickness greater than the first thickness; depositing a soft thick insulating layer on and substantially thicker than the at least one insulating layer at each of the positions of the C4 to form cushions under the bottom of the C4s for stress relief; each of said cushions surrounding a C4 position and with the edges or periphery of the cushion aligned with the C4 ball, when deposited; forming vias through the insulating layer to the top metallization of the integrated circuit chip throughout the chip and not limited to the perimeter of the chip; depositing metal pads in the vias and on the cushions and with a connecting metal wire between the pads; depositing a passivating insulating layer on the metal pads and wire; forming vias in the passivating layer to the metal pads over the cushions; and depositing lead-free C4 solder balls aligned with the edges or periphery of the cushions.