Patent ID: 7507620
Filing Date: 2009-03-24
Classification: H01L,Y02E

Abstract:
1. A method for manufacturing a vertical diode having a low capacitance and formed in a front surface of a semiconductor substrate of a first conductivity type forming a first electrode of the diode, the substrate having a plane, the method comprising the steps of: forming a semiconductor layer of a second conductivity type; digging, outside of a diode forming region, to a digging depth at least until the substrate is exposed; forming, on the substrate, a conductive track having a thickness substantially greater than the digging depth, the conductive track having an upper surface onto which contact balls are formable; in a separate step from forming the conductive track, forming a metallization on a portion of the semiconductor layer forming a second electrode of the diode, the metallization having an upper surface onto which a contact ball is formable, the upper surface of the conductive track and the upper surface of the metallization being coplanar in a plane parallel to the substrate plane, and the metallization having a thickness; and simultaneously forming a first contact ball on said metallization and a second at least two contact balls on the track, the first contact ball and the second at least two contact balls defining a plane parallel to the substrate plane, wherein the thickness of the conductive track which is directly under the contact balls is greater than the thickness of the metallization.