Patent ID: 7719901
Filing Date: 2010-05-18
Classification: G11C

Abstract:
1. A solid state memory device, comprising: an array of non-volatile memory cells; circuitry for control and/or access of the array of non-volatile memory cells; wherein the circuitry for control and/or access of the array of non-volatile memory cells is adapted to receive an input analog data signal indicative of a desired threshold voltage of a target memory cell during a write operation on the memory device, to store a voltage level of the input analog data signal indicative of the desired threshold voltage of that target memory cell, to compare the threshold voltage of that target memory cell to the stored voltage level, and to increase the threshold voltage of that target memory cell if it is found to be less than the stored voltage level during the write operation; and wherein the circuitry for control and/or access of the array of non-volatile memory cells is further adapted to generate an output analog data signal indicative of a threshold voltage of a target memory cell of the array during a read operation of the memory device.