Patent ID: 7515476
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: an even bit line and an odd bit line connected to a memory cell array; a first register coupled to the even bit line and configured to store data; a second register coupled to the odd bit line and configured to store data; a first precharge unit to precharge an even sense node with a high level or supplying supplementary current, the even sense node defined at a node associated with the even bit line and the first register; a second precharge unit to precharge an odd sense node with a high level or supplying supplementary current the odd sense node defined at a node associated with the odd bit line and the second register, wherein the odd sense node is electrically isolated from the even sense node; and a bit line select unit to connect the even bit line and the even sense node and connect the odd bit line and the odd sense node.