Patent ID: 7460040
Filing Date: 2008-12-02
Classification: H03K,H03M

Abstract:
1. A serial data interface for use with a programmable logic device, said serial data interface being adapted to receive and deserialize a serial data signal, said serial data interface comprising: a clock source that provides a clocking signal having a plurality of phases; a dynamic phase alignment module that operates on serial data input to said interface and on said plurality of phases of said clocking signal to align said serial data with one of said phases of said clock signal to which it is closest in phase and to provide a phase-aligned data signal and to output said one of said phases as a phase-aligned clock signal; a clock tree module that derives a data clock using said clocking signal; serial data processing circuitry to deserialize said data signal based on an input clock signal; and a clock selector that selects one of said data clock and said phase-aligned clock signal as said input clock signal.