Patent ID: 8817542
Filing Date: 2014-08-26
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a semiconductor layer; a memory cell array having memory strings, each of the memory strings having a plurality of memory cells connected in series, each of the memory cells including a charge accumulation layer formed on the semiconductor layer via a gate insulating film and a control gate formed on the charge accumulation layer via an inter-gate insulating film; word lines connected to the control gates; bit lines electrically connected to one ends of the memory strings; a source line electrically connected to the other ends of the memory strings; and a control circuit configured to control a voltage applied to the semiconductor layer, the control gates, the bit lines, and the source line, when executing a read operation, the control circuit being operative to begin application of a first voltage to the source line at a first time, the first voltage having a positive value, and begin application of a second voltage to at least one of unselected word lines at the first time or thereafter, the unselected word lines being the word lines connected to unselected memory cells which are the memory cells other than a selected memory cell selected from among the plurality of memory cells, the second voltage setting the memory cells to a conductive state regardless of retained data of the memory cells.