Patent ID: 7504291
Filing Date: 2009-03-17
Classification: H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor device comprising an MOS transistor provided on an SOI layer of an SOI substrate in which a semiconductor substrate, a buried oxide film and said SOI layer are sequentially provided, and a body contact portion provided in a surface of said SOI layer and capable of fixing an electric potential from an outside, a gate electrode of said MOS transistor having a shape seen on a plane such that at least one of ends in a direction of a gate width is enlarged in a direction of a gate length to constitute a gate contact pad, said body contact portion being provided in said surface of said SOI layer on an outside of said end in said direction of said gate width of said gate contact pad and being electrically connected to a channel formation region provided under said gate electrode through said SOI layer, and a gate insulating film of said MOS transistor including a first portion having a first thickness and a second portion having a second thickness in said direction of said gate width, said second thickness being greater than said first thickness, the method comprising the steps of (a) selectively forming an insulating film having said second thickness including said second portion of said gate insulating film on said SOI layer; (b) selectively forming an insulating film having said first thickness including said first portion of said gate insulating film on said SOI layer to be provided continuously with said insulating film having said second thickness including said second portion, wherein said step (a) includes a step of forming said insulating film having said second thickness in a region to be a lower part of at least said gate contact pad; forming a trench isolating film for defining an active region to be a region in which said MOS transistor is to be formed, a region in which said body contact portion is to be formed, and a connecting portion of said active region and said body contact portion formation region and for electrically isolating said MOS transistor, said step (a) further comprising the steps of: said step (b) being executed after said step (a) and including a step of removing said underlaid oxide film and then forming said insulating film having said first thickness where said underlaid oxide film was removed.