Patent ID: 8656326
Filing Date: 2014-02-18
Classification: G06F

Abstract:
1. A method implemented in a programmable computing system for clock gating synthesis for an integrated circuit design, the computing system having at least one processing unit and a memory accessible by the processing unit, the memory storing a hardware description of at least a portion of the integrated circuit design, the memory also storing a set of program instructions that when executed by the processing unit causes the computing system to perform steps comprising: (a) selecting a flip-flop from the hardware description that has been identified as having at least one of an expected probability of activity below a first threshold and the absence of an enable input; (b) traversing a fan-in path of the selected flip-flop until one of another flip-flop and a primary input is reached; (c1) whenever the fan-in path reaches a primary input with an activity level below a second threshold, then computing, using a computer system, a stability condition for the primary input; (c2) whenever the fan-in path reaches another flip-flop with either an enable input or an activity level below a third threshold, then computing, using the computer system, a stability condition for that flip-flop; (d) repeating fan-in path traversal and stability condition computation for other paths of the selected flip-flop until all fan-in paths have been traversed; (e) combining all computed stability conditions for the fan-in path of the selected flip-flop with OR logic; (f) performing a differential power computation, using the computer system, of the combined stability conditions for the flip-flop and retaining the combined stability conditions in the design whenever power savings are achieved; and (g) repeating steps (a)-(f) for all other identified flip-flops in the integrated circuit design.