Patent ID: 8440483
Filing Date: 2013-05-14
Classification: H01L

Abstract:
1. A method of fabricating an array substrate, comprising: forming a first metal layer on a substrate including a transistor region in a pixel region; forming a gate insulating layer on the first metal layer and an active layer of polycrystalline silicon on the gate insulating layer, the gate insulating layer and the active layer disposed in the transistor region, forming a second metal layer on an entire surface of the substrate including the active layer; forming a gate line, an etch-stopper and a gate electrode by patterning the second metal layer and the first metal layer, the gate electrode disposed in the transistor region and under the gate insulating layer, the etch-stopper disposed on the active layer, and the gate line contacting an end of the gate electrode; forming an interlayer insulating layer disposed on the gate line and including an opening, wherein the opening corresponds to the etch-stopper such that the opening is divided into first and second semiconductor contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact layers of impurity-doped amorphous silicon, a source electrode, a drain electrode and a data line on the interlayer insulating layer, the first and second ohmic contact layers respectively contacting both sides of the active layer through the first and second semiconductor contact holes, the source electrode and the drain electrode respectively disposed on the first and second ohmic contact layers, and the data line crossing the gate line to define the pixel region and being connected to the source electrode; removing a portion of the etch-stopper exposed through a space between the source electrode and the drain electrode; and forming a pixel electrode in the pixel region and contacting the drain electrode.