Patent ID: 6168905
Filing Date: 2001-01-02
Classification: G02B,G03F

Abstract:
A method for preparing a multi-level terraced structure in a semiconductor material, comprising the steps of: preparing only one substrate comprising an etching material; preparing a photomask with a pattern comprising masked areas and intervals therebetween; forming a layer of etching mask material on the substrate; transferring said pattern of said photomask to said layer of etching mask material by lithographic technology to obtain an etching mask; and etching said layer of etching mask material in an etchant; wherein said photomask comprises a plurality of regions and each region comprises a plurality of masked areas and intervals therebetween wherein the width of the masked areas belonging to the same region comprises a constant value; characterized in that width of said masked areas varies from region to region at a constant difference, as follows: b.sub.n-1 -b.sub.n =.DELTA.H/C.sub.2 ; wherein b, represents the width of the masked areas of the nth region, .DELTA.H represents a constant difference in the height of levels of the multi-level structure to be prepared, C.sub.2 represents a constant relative to a misaligned angle to the crystal lattice plane direction and b.sub.n-1 >b.sub.n and that the width intervals between said masked areas is of a constant value.