Patent ID: 9224748
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a silicon substrate; a first insulating element and a second insulating element disposed on the silicon substrate; a first bit line region disposed in the silicon substrate underlying the first insulating element and a second bit line region disposed in the silicon substrate underlying the second insulating element; a first charge storage node disposed along a sidewall of the first insulating element and a second charge storage node disposed along a sidewall of the second insulating element; wherein a third charge storage node and a fourth charge storage node are disposed along other sidewalls of the first and second insulating elements, respectively, and wherein the first, second, third, and fourth charge storage nodes are each disposed along a portion less than the full height of each respective insulating element sidewall; oxidized epitaxially grown silicon disposed on the silicon substrate between the first charge storage node and the second charge storage node, wherein edges of the first and second charge storage nodes contact opposite edges of the oxidized epitaxially grown silicon, wherein a height of the oxidized epitaxially grown silicon isles than a height of the charge storage nodes disposed along respective insulating element sidewalls, wherein the epitaxially grown silicon is substantially all oxidized, and wherein a portion of the silicon substrate underlying the oxidized epitaxially grown silicon is oxidized; and a control gate layer contiguously overlying the charge storage nodes, the first and second insulating elements, and the oxidized epitaxially grown silicon.