Patent ID: 6020774
Filing Date: 2000-02-01
Classification: G06F

Abstract:
A gated CTS method for synthesizing a logic circuit including at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements driven directly by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal that is outputted from each of the control gates under control of the control signal, the gated CTS method comprising the steps of:(1) grouping the first logic elements according to whether they are driven by a gated version of the clock signal from the clock generator or a non-gated version of the clock signal from the clock generator;(2) connecting each group of the first logic elements via a first buffer to one of the control gates;(3) connecting each of the second logic elements via a second buffer to the clock generator; and(4) connecting one input end of each of the control gates to the clock generator.