Patent ID: 6870231
Filing Date: 2005-03-22
Classification: H01L

Abstract:
1. An SRAM cell comprising: a semiconductor substrate; first and second active regions in the semiconductor substrate, the first active region each having a first end and a second end, opposite the first end; a first gate electrode on the first and second active regions, the first gate electrode being adjacent the first end of the first active region; a second gate electrode on the first and second active regions, the second gate electrode being substantially parallel to the first gate electrode and being adjacent the second end of the first active region; a first node line configured to electrically connect the first end of the first active region to the second active region adjacent to the first gate electrode, the first node line being substantially parallel to the first gate electrode; a second node line configured to electrically connect the second end of the first active region to the second active region adjacent to the second gate electrode, the second node line being substantially parallel to the second gate electrode; a first local interconnection configured to electrically connect the first node line to the second gate electrode; and a second local interconnection configured to electrically connect the second node line to the first gate electrode.