Patent ID: 6523056
Filing Date: 2003-02-18
Classification: G06Q,G07F

Abstract:
A process for comparing two main storage registers, said registers comprising an equal number of words, each word having a value defined by at least one logical element, characterized in that it comprises the steps of:defining at least one auxiliary storage register (A) comprising several words, each word having a value defined by several logical elements; setting the logical elements of the auxiliary storage register (A) to random values; calculating a first sum (SA1) of the values of the words of the auxiliary storage register; comparing the respective words (i) of the main storage registers two by two, for each comparison of two respective words of the main storage register randomly selecting one of the words of the auxiliary storage register, modifying the value of randomly selected word by a first predetermined value if said words of the main storage registers are identical, and modifying the value of said randomly selected word by a second predetermined value if said words of the main storage registers are different; calculating a second sum (SA2) of the values of the words of the auxiliary storage register, modifying the second sum by a value equal to said first value multiplied by the number of words (n) of the main storage registers; comparing said first and second sums (SA1, SA2), and in the event of an equality, declaring that said main storage registers are identical, and, in the event of an inequality, declaring that said main storage registers are different.