Patent ID: 6725334
Filing Date: 2004-04-20
Classification: G06F

Abstract:
A method for exclusive two-level caching in a chip-multiprocessor; comprising:relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy; providing a first tag-state structure in a first level cache of the two-level cache system, the first tag-state structure having state information; maintaining in a second-level cache of the two-level cache system a duplicate of the first tag-state structure; extending the state information in the duplicate of the first tag-state structure, but not in the first tag-state structure, to include an owner indication; providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible; and at any given time of a cache line lifetime in the chip-multiprocessor, associating a single owner with the cache line.