Patent ID: 6801456
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A method for programming a PMOS single-transistor memory unit, said PMOS single-transistor memory unit being comprised of a silicon dioxide-silicon nitride-silicon dioxide (ONO) dielectric stack disposed on an N-well, a P type polysilicon gate disposed on said ONO dielectric stack, a P type doped source region disposed in said N-well at one side of said P type polysilicon gate, and a P type doped drain region disposed in said N-well on the other side of said P type polysilicon gate, the method comprising:biasing said P type polysilicon gate of said PMOS single-transistor memory unit to a word line voltage VWL; biasing said P type doped source region of said PMOS single-transistor memory unit to a source line voltage VSL that is greater than the word line voltage VWL, wherein |VWLâˆ’VSL|â€ƒis larger than threshold voltage of said PMOS single-transistor memory unit, so as to provide an adequate gate-to-source bias to turn on a P-channel of said PMOS single-transistor memory unit; biasing said P type doped drain region of said PMOS single-transistor memory unit to a bit line voltage VBL, wherein said bit line voltage VBL is smaller than said source line voltage VSL, so as to provide a lateral electric field for P-channel hot holes, wherein said lateral electric field forces said P-channel hot holes passing through said P-channel in an accelerated drift rate to said P type doped drain region, thereby inducing hot electrons near said P type doped drain region, and wherein some of induced hot electrons are injected into said ONO dielectric stack; and biasing said N-well to a well voltage VNW, wherein said well voltage VNW is equal to said source line voltage VSL.