Patent ID: 8990458
Filing Date: 2015-03-24
Classification: G06F,G11C

Abstract:
1. A memory controller configured to control a storage memory, the memory controller comprising: a command decode part; a mode selection part that selects one of a MLC-mode and a SLC-mode, after a write command is decoded by the command decode part; and a write part that executes a data writing to the storage memory by using one of the MLC-mode and the SLC-mode selected by the mode selection part, wherein the mode selection part is configured to: check whether a first data written from a host to a buffer memory is a time-continuous data that is written continuously during a predetermined period; execute the data writing of a second data from the buffer memory to the storage memory in the MLC-mode, when the first data is the time-continuous data; and execute the data writing of the second data from the buffer memory to the storage memory in the SLC-mode, when the first data is not the time-continuous data.