Patent ID: 7078824
Filing Date: 2006-07-18
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip having a main surface; an internal circuit which is formed over the main surface of the semiconductor chip, the internal circuit including a plurality of memories, a first switching circuit which can change capacitances of the plurality of memories and a second switching circuit which supplies a given output signal to the plurality of memories; an interface circuit which is formed over the main surface of the semiconductor chip, the interface circuit including a plurality of I/O cells which are arranged around the internal circuit; a plurality of bonding pads which are formed over the main surface of the semiconductor chip, the plurality of bonding pads being arranged between the plurality of I/O cells and sides of the semiconductor chip, the plurality of bonding pads including a first power source bonding pad, a second power source bonding pad, and a plurality of signal bonding pads; a plurality of first changeover bonding pads which are formed over the first switching circuit, the plurality of first changeover bonding pads being supplied with an output signal in response to an input signal from the first switching circuit; a second changeover bonding pad which is formed over the second switching circuit, the second changeover bonding pad inputting the output signal which is supplied from the first switching circuit; a power source wiring which is formed over the main surface of the semiconductor chip, the power source wiring being connected to the first and second power source bonding pads in common, wherein the power source wiring supplies an operational potential to the plurality of I/O cells; a plurality of leads which are arranged in around the semiconductor chip, the plurality of leads including a power source lead and a plurality of signal leads; a plurality of bonding wires including a first bonding wire for electrically connecting the first power source bonding pad with the power source lead, the plurality of bonding wires including a second bonding wire for electrically connecting the first power source bonding pad with the second power source bonding pad, the plurality of bonding wires including a third bonding wire for electrically connecting the plurality of signal bonding pads with the plurality of signal leads, respectively, the plurality of bonding wires including a changeover bonding wire for electrically connecting a part of the plurality of first changeover bonding pads with the second changeover bonding pad; and a sealing body which seals the semiconductor chip, the plurality of bonding wires, and a part of the plurality of leads.