Patent ID: 7523419
Filing Date: 2009-04-21
Classification: G06F,H01L

Abstract:
1. A method of designing a wiring layout for a semiconductor integrated device using a designing apparatus, said method comprising: insulating a diffusion layer from an element comprising an electrode; connecting a first wiring to said electrode; and providing an (n+1)th wiring parallel to and adjacent to a nth wiring, where n is an integer greater than or equal to one, wherein said first to (n+1)th wirings are arranged such that an area ratio of a sum of an area of said first wiring plus a summation of areas of wirings from a second wiring to said (n+1)th wiring to an electrode area of said electrode is less than or equal to a predetermined value that gives charge-up damage to an insulating film of said electrode, said summation of the areas of the wirings from said second wiring to said (n+1)th wiring being given as a summation of the areas of the wirings from said second wiring to said (n+1)th wiring each multiplied by a predetermined coefficient a