Patent ID: 6172545
Filing Date: 2001-01-09
Classification: H03K

Abstract:
A delay circuit on a semiconductor device, the delay circuit comprising:a plurality of p-channel transistors and a plurality of n-channel transistors connected in series from a high-potential power supply to a low-potential power supply;an input signal being commonly supplied to the gate terminals of said plurality of p-channel transistors and n-channel transistors; andthe junction point of the p-channel transistor farthest from said high-potential power supply and the n-channel transistor farthest from said low-potential power supply providing an output terminal;wherein the current drive capabilities of said plurality of p-channel transistors and the current drive capabilities of said plurality of n-channel transistors are different, ranging from the transistors closer to said power supplies to the transistors closer to said output terminal; andwherein a ratio of said current drive capabilities of said p-channel transistors closer to said power supplies to said p-channel transistors closer to said output terminal is equal to a ratio of said current drive capabilities of said n-channel transistors closer to said power supplies to said n-channel transistors closer to said output terminal.