Patent ID: 7109570
Filing Date: 2006-09-19
Classification: H01L

Abstract:
1. An integrated circuit package comprising: a die pad having a first face and a second face opposite to said first face; a plurality of leads each having a first face and a second face opposite to said first face, wherein said plurality of leads is disposed substantially around at least a portion of said die pad, and said first face of at least one of said plurality of leads has a recess formed therein, said recess having inner walls; an integrated circuit chip having a first face and a second face opposite to said first face wherein said second face is coupled to said first face of said die pad; a plurality of wires each linking said integrated circuit chip to one of said plurality of leads; and an encapsulant enclosing said integrated circuit chip, said plurality of wires, said first face of said die pad, and a portion of said first face of each of said plurality of leads, wherein said encapsulant forms a plurality of side walls, and at least one of said side walls intersects said first face of said at least one of said plurality of leads between the inner walls of said recess formed therein.