Patent ID: 6703279
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A process to form a metal contact for a memory device, comprising the following steps:providing a semiconductor substrate having a first FET of a first conductivity type and a second FET of a second conductivity type in a support area and a third FET of the second conductivity type in an array type; providing a first diffusion region adjacent to the first FET, a second diffusion region adjacent to the second FET, and a third diffusion region adjacent to the third FET; forming a dielectric layer on the semiconductor substrate; respectively forming first, second, and third contact openings in the dielectric layer to the first, second, third diffusion regions; forming a doped SixGe1âˆ’x layer of a second conductivity type within the first, second, and third contact openings, wherein 0masking the second and third contact openings; removing the doped SixGe1âˆ’x layer within the first contact opening; implantation a dopant of a first conductivity type into the first diffusion region; conformally forming a cobalt layer over the semiconductor substrate; transforming the cobalt layer into a cobalt silicide layer by reacting the cobalt layer with the underlying SixGe1âˆ’x layer in the second and third contacting openings; and filling a metal plug into the first, second, and third contact openings.