Patent ID: 7474000
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A structure for providing multilevel electrical connectivity within an integrated circuit, the structure comprising: a first plurality of vias, each having a top end and a bottom end; a second plurality of vias, each having a top end and a bottom end, wherein the first and second pluralities of vias are vertically overlapping; a first routing level at a first height, said first level connected to the first plurality of vias at the bottom end of each first via; and a second routing level at a second height, said second level connected to the second plurality of vias at the bottom end of each second via, wherein the first height is different from the second height, wherein both routing levels are formed above a substrate, wherein the first and second vias are evenly spaced and have a common first pitch, and further comprising a third routing level, the third routing level above the first and second vias connected at the top end of each first and second via, vertically opposite the first and second routing levels, wherein the third routing level comprises memory lines in a memory array, and wherein the first plurality of vias are not connected to any routing level above the first routing level and below the third routing level, and wherein the second plurality of vias are not connected to any routing level above the second routing level and below the third routing level.