Patent ID: 7539884
Filing Date: 2009-05-26
Classification: G06F

Abstract:
1. A method of power-gating instruction scheduling for power leakage reduction, comprising: receiving a program; generating a control-flow graph by dividing the program into a plurality of blocks and linking the blocks according to the program, wherein the control-flow graph contains control commands; analyzing utilization of power-gated components of a processor executing the program; generating first power-gating instruction placement based on the control-flow graph and the utilization of the power-gated components, the first power-gating instruction placement comprising a plurality of power-off instructions and a plurality of power-on instructions to shut down inactive components; generating second power-gating instruction placement by modifying the first power-gating instruction placement, wherein the second power-gating instruction placement comprises compound power-off instructions and compound power-on instructions generated by combining the combinable power-off instructions and combining the combinable power-on instructions respectively; inserting power-gating instructions into the program according to the second power-gating instruction placement; and executing the program by the processor.