Patent ID: 6629222
Filing Date: 2003-09-30
Classification: G11C

Abstract:
An apparatus that synchronizes a data signal and a data strobe signal received from a random access memory, wherein the random access memory is configured to adhere to the double data rate (DDR) memory interface standard, the data strobe signal being sent by the random access memory in order to latch the data signal, wherein the apparatus resides within a processor, the apparatus comprising:a mechanism that initiates a read operation to the random access memory including sending a target address for the read operation to the random access memory; an input driver that receives the data signal from the random access memory, the data signal containing data retrieved from the target address; a register comprised of a first set of flip-flops and a second set of flip-flops coupled to the input driver that stores the data signal, the register including a clock input for latching the data signal into the register, wherein the first set and the second set are used alternately in ping-pong fashion to improve throughput; an enable input on the input driver for enabling the input driver to drive the data signal into the register; a first programmable delay circuit coupled to the enable input to delay an enable signal from the system clock feeding into the enable input so as to synchronize the driving of the input driver with the data signal received from the random access memory; and a second programmable delay circuit coupled between the data strobe signal and the clock input of the register, the second programmable delay circuit being configured to delay the data strobe signal from the memory so as to synchronize the data strobe signal with the data signal received from the random access memory.