Patent ID: 6504200
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A DRAM cell configuration, comprising:a plurality of memory cells each having a vertical transistor and a capacitor; a substrate formed with substantially parallel trenches each having side walls and having a bit line arranged therein in a lower part thereof; an insulation formed in the lower part of a respective said trench between said bit line and said substrate, except for a strip-type cut-out formed parallel to said trench and in said first sidewall of said trench; a further insulation formed on parts of said side walls of said trench above the lower part of said trench and an upper area of said bit line; word lines extending transversely with respect to said bit line, said word lines, except for downwardly directed protuberances that reach into said trenches and that are arranged above said bit lines, running above said substrate, and an insulating layer isolating said word lines from said substrate; said protuberances of said word lines and insulating structures being arranged alternately above said bit line in said trench; said transistors having upper source/drain regions and lower source/drain regions arranged between said trenches and under said word lines; further insulating structures formed in said substrate for insulating from one another upper source/drain regions of mutually adjacent transistors along said trench; and wherein said upper source/drain regions of said transistors are connected to said capacitors of said memory cells.