Patent ID: 6738395
Filing Date: 2004-05-18
Classification: H04J

Abstract:
A pointer processor system comprising;an input port for receiving input data; a parallel array of pointer processing strips, for adjusting line clock domain input data to system clock domain output data; means for distributing input data from the input port to the pointer processing strips according to a distribution order; a pointer interpreter delay block controlling input data reading on at least a pair of an ith and jth pointer processing strips, such that corresponding input data is read on the jth pointer processing strip after a predetermined pointer interpreter pair delay from a time moment when corresponding input data is read on the ith pointer processing strip, wherein i and j are integers assigned to the pointer processing strips according to the distribution order and j is greater than i; means for collecting output data from the pointer processing strips according to a collection order; and an output port for transmitting output data.