Patent ID: 6233531
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A microprocessor, comprising:a memory unit including a plurality of memory locations for storing data, wherein the memory unit is coupled to receive a plurality of high order address signals and at least one low order address signal, and wherein the high order address signals and the at least one low order address signal specify an address of a single one of the memory locations;circuitry coupled to the memory unit for producing the high order address signals;a bus monitor unit coupled to address, data, and control signal lines within the microprocessor and configured to detect a selected event occurring within the microprocessor and to produce an event signal and the at least one low order address signal in response to the selected event;wherein when the bus monitor unit produces the event signal, the contents of the memory location having the address specified by the high order address signals and the at least one low order address signal is incremented;wherein the bus monitor unit is configured to detect n selected events, and wherein n.gtoreq.1, and wherein the bus monitor unit is configured to produce a low order address signals in response to any one of the n selected events, and wherein a is an integer and a.gtoreq.log.sub.2 (n), and wherein the high order address signals and the a low order address signals specify an address of a single one of the memory locations of the memory unit; andwherein the high order address signals produced by the circuitry divide the memory locations of the memory unit into sections, and wherein each section corresponds to a different one of a plurality of time periods of a data acquisition period, and wherein each section includes n memory locations, and wherein each of the n memory locations corresponds to a different one of the n selected events, and wherein each section is used to store data relating to the n selected events occurring during the corresponding time period.