Patent ID: 6698000
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A semiconductor process parameter determining method to obtain optimum wiring width and wire spacing of each wiring layer, comprising the steps of:inputting a first process parameter as an input parameter; obtaining a predetermined circuit characteristic by performing a simulation on a gate level and/or a transistor level by use of said input parameter with a second process parameter, of each wiring layer constructing a semiconductor device, as a variable; determining whether said simulation is completed or not; extracting a parameter having a shortest delay time in said second process parameter for each wiring layer obtaining a desired circuit characteristic; and outputting said extracted, second process parameter for each wiring layer, wherein the first process parameter is selected from at least one, or two or more of a gate scale, an in-the-same-layer wiring adjacent probability, a between-different-layers wiring overlapping probability, the number of wiring layer, library information, a plurality of wiring materials, a plurality of via materials, floorplan information, and a netlist.