Patent ID: 6049486
Filing Date: 2000-04-11
Classification: G11C

Abstract:
A method to erase a flash EEPROM cell, which is comprised of a source and a drain diffused within a first well of a first conductivity type which is diffused into a second well of a second conductivity type which is further diffused in to a semiconductor substrate of the first conductivity type, and a control gate, a floating gate, and a tunneling oxide disposed upon the semiconductor substrate, to improve a write/erase threshold voltage closure from repeatedly writing and erasing said flash EEPROM cell, comprising the steps of:negative gate erasing said flash EEPROM to remove charges from said floating gate by the steps of:applying a first relatively large negative voltage pulse to said control gate of said flash EEPROM,concurrently applying a first moderately large positive voltage pulse to said source,concurrently applying a ground reference potential to said first well and said semiconductor substrate, andconcurrently disconnecting said drain and second well to allow said drain and second well are floating; thensource erasing said flash EEPROM cell to further remove charges from said floating gate by the steps of:floating said drain and said second well,concurrently applying the ground reference potential to said semiconductor substrate, said drain, and said first well, andconcurrently applying a relatively large positive voltage pulse to said source; and thenchannel erasing said flash EEPROM cell to detrap charges from the tunneling oxide by the steps of,applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell,concurrently applying a second moderately large positive voltage pulse to said first well,concurrently applying a ground reference potential to the semiconductor substrate, andconcurrently floating said drain, said source, and said second well.