Patent ID: 6470425
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A cache memory having a plurality of entries, comprising:a hit/miss counter checking a cache hit or a cache miss on each of said plurality of entries; and a write controller controlling an inhibition of a replacement of each of said plurality of entries based on a result of the checking made by said hit/miss counter, wherein said hit/miss counter comprises a hit counter counting a number of sequential cache hits on each of said plurality of entries, wherein said write controller inhibits the replacement of each of said plurality of entries based on the number in said hit counter, wherein said write controller comprises: a hit threshold register in which the number of sequential cache hits is set as a condition for inhibiting the replacement of each of said plurality of entries; and a sequential hit detector detecting that the number of sequential cache hits has exceeded the number stored in the hit threshold register, and wherein when said sequential hit detector detects that the number of sequential hits has exceeded the number stored in said hit threshold register, the replacement of a corresponding entry of said plurality of entries is inhibited.