Patent ID: 6300191
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method of fabricating a capacitor under bit line structure, for a dynamic random access memory (DRAM), device, on a semiconductor substrate, comprising the steps of:forming transfer gate transistors on said semiconductor substrate, comprised of gate structures located on an underlying gate insulator layer, with first insulator spacers on the sides of said gate structures, and comprised with source/drain regions located in a region of said semiconductor substrate not covered by said gate structures;forming self-aligned contact (SAC), openings in said first insulator layer, exposing top portions of said source/drain regions;forming conductive plugs in said SAC openings, having a first group of conductive plugs and a second group of conductive plugs;forming capacitor openings in a second insulator layer, exposing the top portion of a first group of conductive plugs to be used for storage node contacts, and forming a bit line contact hole, exposing said second group of conductive plugs to be used as a lower level bit line contact structure;depositing a conductive layer, such as a first polysilicon layer, with said conductive layer covering exposed surfaces of said capacitor openings, and with said first polysilicon layer completely filling said bit line contact hole;removing portions of said conductive layer from the top surface of said second insulator layer, to form storage node structures in said capacitor openings, and to simultaneously form an upper level, bit line contact structure in said bit line contact hole;depositing a capacitor dielectric layer, a second polysilicon layer, and an overlying third insulator layer;performing a patterning procedure in said third insulator layer, in said second polysilicon layer, and in said capacitor dielectric layer, to form a bit line opening, exposing the top surface of said upper level bit line contact structure, and to simultaneously define capacitor structures, comprised of an overlying top electrode structure, said capacitor dielectric layer, and said storage node structure, with said top electrode structure comprised of said second polysilicon layer;forming second insulator spacers on the sides of said bit line opening; andforming a bit line structure in said bit line contact opening.