Patent ID: 7074317
Filing Date: 2006-07-11
Classification: C25F,H01L

Abstract:
1. A method for producing a plurality of trench capacitors in a p-doped silicon layer for integrated semiconductor memories, the method which comprises: providing a p-doped silicon layer having a predetermined resistivity of less than 0.3 ohm cm, a front side, and a rear side; producing start nuclei on the front side of the p-doped silicon layer; applying an electrolyte to the front side of the p-doped silicon layer, the electrolyte being an organic solution having an added amount of hydrofluoric acid or fluorine; applying an electrical voltage between the rear side of the p-doped silicon layer and the electrolyte such that an electric current having a given current density flows in the p-doped silicon layer and the plurality of trenches are produced; when performing the step of applying the electrical voltage, setting the electrical voltage such that the current density is 1–10 mA/cm producing a respective first electrode in each of the plurality of trenches; applying a respective capacitor dielectric to the first electrode in each of the plurality of trenches; and producing a respective second electrode in each of the plurality of trenches.