Patent ID: 7773424
Filing Date: 2010-08-10
Classification: G11C,H01L

Abstract:
1. A circuit for a nonvolatile memory cell comprising: a charge-altering terminal; an output terminal configured to provide a signal corresponding to a state of the memory cell when reading the nonvolatile memory cell; a first transistor including a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal; and a second transistor including a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal, wherein the circuit is designed such that when changing the state of the memory cell, the second transistor would be active and no significant amount of charge carriers would be transferred between the gate electrode of the first transistor and the active region of the first transistor.