Patent ID: 6958627
Filing Date: 2005-10-25
Classification: G06F

Abstract:
1. An asynchronous digital pipeline circuit for processing data in an environment, the environment providing data for processing and a first request signal, the circuit comprising: a first processing stage comprising a first latch controller responsive to a second acknowledgment signal received from the environment and a first done signal received from a first data latch, and configured to assert a first enable signal when the second acknowledgment signal is received and to de-assert the first enable signal when the first done signal is received; a first data latch having a setup time and configured to receive the data and the first request signal from the environment, wherein each signal transition on the first request signal indicates a new data item, the first data latch having an enabled phase and a disabled phase responsive to the first enable signal, wherein the data latch is enabled in the enabled phase to pass the data to a first data output and the data latch is disabled in the disabled phase, such that the passing of the data to the data output in the enabled phase also transmits a second request signal to the environment, transmits a first acknowledgment signal to the environment, and transmits the first done signal to the first latch controller, wherein the delay time comprising the receipt of first request signal to the transmitting of the first done signal