Patent ID: 8957458
Filing Date: 2015-02-17
Classification: G11C,H01L

Abstract:
1. An asymmetric bi-stable semiconductor memory cell comprising: a floating body region having at least two stable charge levels indicative of a state of the asymmetric bi-stable semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a third region in direct electrical contact with said floating body region and located below said floating body region; and a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate wherein said gate is spaced apart from said first region; wherein performance characteristics of said first side are different from performance characteristics of said second side.