Patent ID: 7557000
Filing Date: 2009-07-07
Classification: H01L,Y10S

Abstract:
1. A method for forming a semiconductor integrated device comprising: providing a semiconductor substrate; forming a dielectric layer overlying the semiconductor substrate; forming a gate layer overlying the dielectric layer; forming a hard mask overlying the gate layer; patterning the gate layer to form a gate structure including edges using the hard mask as a protective layer; forming a dielectric layer overlying the gate structure to protect the gate structure including the edges; forming spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure; etching a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed; maintaining the hard mask overlying the gate structure; depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material; causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region; and removing the hard mask from the gate structure to expose a top portion of the gate structure, the top portion of the gate structure being substantially free from any silicon germanium material.