Patent ID: 6886078
Filing Date: 2005-04-26
Classification: G06F,G11C

Abstract:
1. A compilable semiconductor memory circuit having a plurality of hierarchically organized levels, comprising: a first level memory portion for storing data therein, said first level memory portion having first level Data In (DIN) and Data Out (DOUT) buffer blocks associated therewith for effectuating data operations with respect to a location in said first level memory portion, said first level DIN buffer block including Local Data In (LDIN) driver circuitry; a second level memory portion for storing data therein, said second level memory portion having second level Data In (DIN) and Data Out (DOUT) buffer blocks associated therewith for effectuating data operations with respect to a location in said second level memory portion; multiplexing circuitry disposed in said first level DIN buffer block, said multiplexing circuitry being actuatable for providing data accessed through said second level DOUT buffer block to said LDIN driver circuitry in said first level DIN buffer block, whereby data accessed from said second level memory portion is selectively loaded into said first level memory portion in a loading operation that is substantially simultaneous relative to accessing of said data in said second level memory portion; a third level memory portion for storing data therein, said third level memory portion having third level Data In (DIN) and Data Out (DOUT) buffer blocks associated therewith for effectuating data operations with respect to a location in said third level memory portion; and multiplexing circuitry disposed in said second level DIN buffer block, said multiplexing circuitry being actuatable for providing data accessed through said third level DOUT buffer block to LDIN driver circuitry provided in said second level DIN buffer block, who whereby data accesses from said third level memory portion is selectively loaded into said second level memory portion in a loading operation that is substantially simultaneous relative to accessing of said data in said third level memory portion, wherein said multiplexing circuitry disposed in said first level DIN buffer block is selectively operable for providing said data accessed through said third level DOUT buffer block to said LDIN driver circuitry in said first level DIN buffer block for substantially simultaneously loading said data into said first level memory portion.