Patent ID: 8929172
Filing Date: 2015-01-06
Classification: G11C

Abstract:
1. A pipe register circuit comprising: an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals; and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section so that data of a cell array is not outputted to the address storage section but is outputted to an output driver, wherein the address storage section comprises: a first counter part configured to output a plurality of address pipe input control signals such that the address signals are sequentially stored in synchronization with the clock, when the read command signal is input; a first transmission part configured to sequentially transmit the address signals in correspondence with the address pipe input control signals output from the first counter part; a register part configured to sequentially store the address signals transmitted from the first transmission part; a second counter part configured to output address pipe output control signals such that the address signals stored in the register part are sequentially output in correspondence with the address output control signal output from the address output control section; and a second transmission part configured to transmit the address signals in correspondence with the address pipe output control signals output from the second counter part.