Patent ID: 6553524
Filing Date: 2003-04-22
Classification: G01R

Abstract:
A method for automatic validation of test hardware of an integrated circuit device, comprising:a) extracting and validating a test hardware portion of connectivity of the integrated circuit device, comprising: 1) during a first extraction procedure, validating the connectivity of a plurality of test signals, residing at a plurality of test signal output ports of a test control block of the test hardware portion comprised of a plurality of serially-connected scan latch instances, to the plurality of serially-connected scan latch instances; 2) generating and logging any test signal connectivity errors identified during validating the connectivity of the plurality of test signals to the plurality of serially-connected scan latch instances; 3) during a second extraction procedure, validating the inter-connectivity of the plurality of serially-connected scan latch instances; and 4) generating and logging any scan latch inter-connectivity errors identified during validating the inter-connectivity of the plurality of serially-connected scan latch instances; b) representing the extracted and validated test hardware portion of the connectivity of the test hardware in a block description language; c) using any logged test signal connectivity errors and any scan latch inter-connectivity errors to improve the test hardware portion.