Patent ID: 8837239
Filing Date: 2014-09-16
Classification: G11C

Abstract:
1. A latency control circuit comprising: a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals; a deviation information generating unit configured to generate a deviation signal on the basis of a delay value excluding a command decoder delay time from a delay time that the input clock signal undergoes in a chip, and latency information; a clock selector configured to generate a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information; a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal; and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals output from the clock selector with the variable delay duplication signal output from the command signal processing unit.