Patent ID: 8310856
Filing Date: 2012-11-13
Classification: G11C

Abstract:
1. A memory comprising: first and second bit lines; and a plurality of ferroelectric memory cells connected between said first and second bit lines; a word select circuit that selects one of said ferroelectric memory cells, a read circuit that generates a potential on said first bit line indicative of a value stored in said selected one of said plurality of ferroelectric memory cells, each ferroelectric memory cell comprising; a ferroelectric capacitor characterized by first and second polarization states; a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal, said ferroelectric capacitor being connected between said control terminal and said first switch terminal; a first gate that connects said first switch terminal to said bit line in response to said word select circuit selecting that ferroelectric memory cell; and a second gate that connects said control terminal to said second bit line in response to said word select circuit selecting that ferroelectric memory cell.