Patent ID: 6822494
Filing Date: 2004-11-23
Classification: H03L

Abstract:
A register controlled delay locked loop (DLL) using a comparison reference clock and a delay monitoring clock which are internal clocks synchronized with an external clock, the register controlled delay locked loop (DLL) comprising:a first delay line having a plurality of sub delay chains grouped with a plurality of delay units for receiving the internal clock; a second delay line having a plurality of sub delay chains grouped with a plurality of delay units and receiving the delay monitoring clock and generating a second delayed clock; a delay model for generating a delay model signal by reflecting a delay condition of a real clock path on the second delayed clock from the second delay line; a phase comparison means for generating a phase comparison signal by comparing a phase of the comparison reference clock with the delay model signal from the delay model; a shift register control means for generating a shift control signal by responding to the phase comparison signal from the phase comparison means; a master shift register for selecting one of the sub delay chains of the first delay line and the second delay line by responding to the shift control signal; and a slave shift register for selecting one of the delay units in the sub delay chain selected by the master shift register according to the shift control signal.