Patent ID: 6753565
Filing Date: 2004-06-22
Classification: H01L,Y10S

Abstract:
An array of capacitors comprising:first, second and third memory cell capacitors comprising first, second and third bottom container-shaped electrodes, respectively; a bit line contact laterally positioned between the first and second memory cell, the bit line contact downwardly extends from a vertical height above a top of the first and second bottom electrodes; a trench laterally positioned between the second and third bottom electrodes; a common top electrode capacitively coupled to the first, second and third bottom electrodes via a capacitor dielectric layer, wherein the top electrode includes a lateral clearance opening above the top of the first bottom electrode and around the bit line contact, the top electrode is capacitively coupled to an interior of the first, second and third bottom electrodes and an portion of the exterior of the second and third bottom electrodes located only in the trench; and a bit line contact insulation region surrounding the bit line contact and filling a region between the bit line contact and the bottom electrode.