Patent ID: 7406668
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. A method of selecting portions of a logic design for implementation in an FPGA having a predetermined FPGA architecture so as to facilitate possible conversion of the FPGA implementation to a structured ASIC implementation of said logic design in a structured ASIC having a predetermined structured ASIC architecture, said FPGA architecture employing multiple instances of programmable logic elements, and said structured ASIC architecture employing multiple instances of hard logic elements, each of which has less logic capacity than each of said programmable logic elements, comprising: weighting candidate portions of the logic design with weightings that reflect both a first cost of implementing the candidate portion in one of the programmable logic elements and a second cost of implementing the candidate portion in a number of the hard logic elements needed to implement that candidate portion; and selecting from among the candidate portions finally selected portions of the logic design to be implemented in the FPGA based at least in part on the weightings of the candidate portions.