Patent ID: 7683491
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A semiconductor device comprising: a package substrate which has first and second pads to which a power supply voltage is applied on an upper surface thereof; a first memory chip which is arranged on the package substrate and which has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and which has a plurality of memory pads provided along the first side, the first and second power supply pads having the power supply voltage applied thereto; and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, and arranged on the first memory chip, which has the same structure as the first memory chip, which has a first power supply pad provided on the first side and a second power supply pad provided on the second side perpendicular to the first side, and which has a plurality of memory pads provided along the first side, wherein the first and second power supply pads are provided at diagonal corners of the first and second memory chips, respectively, the first power supply pads of the first and second memory chips are electrically connected with the first pad of the package substrate, the second power supply pads of the first and second memory chips are electrically connected with the second pad of the package substrate, and the plurality of memory pads of the second memory chip are electrically connected with the plurality of memory pads of the first memory chip by bonding wires, respectively.