Patent ID: 9183156
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method for implementing read-copy update in a shared-memory computing system having two or more processors operatively coupled to a shared memory and to associated incoherent caches, said method comprising: recording cacheline information identifying cachelines containing data that has been rendered obsolete in an incoherent cache associated with one processor of said two or more processors due to a data update being performed by said one processor of said two or more processors; said incoherent cache caching copies of data stored in said memory without hardware-implemented cache coherency support; said recording comprising said one processor of said two or more processors storing said cacheline information in a local cache record data structure associated with said one processor of said two or more processors; communicating said recorded cacheline information to different processors of said two or more processors; said communicating comprising either said different processors reading said local cache record data structure or said one processor of said two or more processors merging said cacheline information from said local cache record data structure into a global cache record data structure that stores cacheline information merged from two or more local cache record data structures associated with different processors, said cacheline information being merged either directly into said global cache record data structure or through a hierarchy comprising one or more levels of intermediate cache record data structures; and using said communicated cacheline information to identify cachelines that contain said obsolete data in incoherent caches associated with said different processors and flush said obsolete data from said identified cachelines.