Patent ID: 6727135
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method of forming a CMOS device comprising the steps of:(a) providing a plurality of patterned gate stack regions on a surface of a semiconductor substrate, wherein each of said patterned gate stack regions includes exposed vertical sidewalls; (b) forming a composite spacer on each exposed vertical sidewall, said composite spacer including a bilayer comprising a nitride layer and a Si-containing film, wherein said Si-containing film is thicker than said nitride layer and is formed on said nitride layer; (c) forming deep source and drain regions in said surface of said semiconductor substrate; d) removing said Si-containing film and forming shallow junctions in said semiconductor substrate in areas abutting each of said patterned gate stack regions; (e) removing portions of said nitride layer so as to form an L-shaped nitride spacer on each vertical sidewall of said patterned gate stack regions and activating said source and drain regions; and (t) forming silicide contacts in exposed regions of said semiconductor substrate not containing said L-shaped nitride spacer.