Patent ID: 6642879
Filing Date: 2003-11-04
Classification: H03M

Abstract:
A method for powering down an analog-to-digital converter (â€œADCâ€ ) into a sleep mode, comprising the steps of:in response to an analog-to-digital converter (â€œADCâ€ ) receiving a normal set of serial clock pulses, outputting, by a serial interface controller, converted data requested by a user through a serial interface; in response to the ADC receiving a sleep set of serial clock pulses powering down, by a state machine of the ADC, the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level; and in response to the ADC being in the sleep mode and the ADC receiving a wake-up set of serial clock pulses, powering up, by the state machine, the ADC from the sleep mode; and wherein a serial clock signal of the ADC provides either the normal set of serial clock pulses, the sleep set of serial clock pulses or the wake-up set of serial clock pulses and the state machine distinguishes which one of the three sets of serial clock pulses is being provided by the serial clock signal.