Patent ID: 8279702
Filing Date: 2012-10-02
Classification: G11C,H01L

Abstract:
1. A semiconductor apparatus comprising: an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes, which have different code values or of which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.