Patent ID: 6512295
Filing Date: 2003-01-28
Classification: H01L

Abstract:
An electronic package, comprising:a circuitized substrate having an upper surface; a semiconductor chip mounted on said upper surface of said circuitized substrate and electrically and mechanically coupled to said substrate, said semiconductor chip having a substantially planar upper surface and at least one edge surface being substantially perpendicular to said substantially planar upper surface; a thermally conductive member comprising a laminate of a plurality of woven mesh layers and having upper and lower surfaces, at least said lower surface of said thermally conductive member being thermally coupled to said substantially planar upper surface of said semiconductor chip, said thermally conductive member further having at least one edge surface extending around a defined perimeter of said thermally conductive member; and dielectric material being imparted to at least an areal portion of said circuitized substrate, against at least a portion of said at least one edge surface of said thermally conductive member, against a portion of said upper surface of said mesh-like thermally conductive member and against at least a portion of said at least one edge surface of said semiconductor chip.