Patent ID: 7941435
Filing Date: 2011-05-10
Classification: G06F

Abstract:
1. A circuit, comprising: a byte shift register array comprising a hash key output and a plurality of linear feedback shift registers (LFSRs), wherein each LFSR of the plurality of LFSRs implements a same finite state machine and is initialized to an initial state; a memory having a hash key input coupled to the hash key output and a match output, and the memory comprising a plurality of stored digital signatures each keyed to a particular hash key; and logic coupled to the byte shift register array which, when executed, is operable for performing the steps of: reading a subset of input elements, of a plurality of input elements, into each LFSR of the plurality of LFSRs; (a) reading a next input element, of the plurality of input elements, into each LFSR of the plurality of LFSRs; (b) determining, based on a hash key indicated by one of the LFSRs of the plurality of LFSRs and the memory, whether said indicated hash key matches a hash key of a stored digital signature of the plurality of digital signatures, wherein the indicated hash key corresponds to multiple elements of the plurality of input elements; (c) resetting said one of the LFSRs to the initial state without resetting any of the other LFSRs of the plurality of LFSRs; and repeating (a)-(c) for each next input element in the plurality of input elements.