Patent ID: 6696857
Filing Date: 2004-02-24
Classification: H03K

Abstract:
A high speed CMOS Dual Modulus prescaler circuit comprising:data or D-flip flops connected serially in a chain wherein a flip-flop positive output Q of stage N is connected to a D-input of an N+1 flip-flop stage, a P-channel metal oxide semiconductor field effect transistor, PMOS FET whose gate is connected to a negative output of a last stage of said serial chain of D-flip flops, an N-channel metal oxide semiconductor field effect transistor, NMOS FET whose drain is connected to said PMOS FET, a two input NAND gate whose one input is a positive output of said last flip-flop of said serial chain of D-flip flops and whose second input is a node control signal and whose output drives said gate of said NMOS FET, a second NMOS FET whose gate is attached to a drain of said first NMOS FET, and a second or final D-flip flop whose data input comes from a positive output of said previous D-flip flop.