Patent ID: 6437616
Filing Date: 2002-08-20
Classification: H03L,Y10S

Abstract:
A delay lock loop circuit comprising:a delay block coupled to receive a clock signal and operable to delay the clock signal by a elected delay amount to generate a delayed clock signal; a phase detector coupled to receive the clock signal and the delayed clock signal, and operable to compare phases of the clock signal and the delayed clock signal, and operable to generate a phase comparison signal in response to the phase comparison; a lock detector coupled to receive the clock signal and the delayed clock signal, and operable to compare timing of the clock signal and the delayed clock signal, and operable to generate a potential lock indication signal in response to the timing comparison; a controller coupled to receive the phase comparison signal and the potential lock indication signal, and operable to provide a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal, and operable to interrupt the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and operable to generate a true lock indication signal in response to the potential lock indication signal subsequent to the interruption of the clock signal to the delay block.