Patent ID: 8040746
Filing Date: 2011-10-18
Classification: G11C

Abstract:
1. A zero leakage read only memory (ROM) including a memory array, the memory array comprising a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of memory cells, wherein each of the plurality of memory cells are connected to a plurality of word lines, comprising: one or more address decoders for selecting at least one of the plurality of bit lines and word lines; a plurality of sense amplifiers for sensing the plurality of bit lines, wherein each of the plurality of sense amplifiers is associated with a corresponding bit line of the plurality of bit lines; a reference word line column for vertical tracking of the at least one of the plurality of word lines using a first predefined loopback; a reference bit line column comprising a reference bit line for vertical tracking of at least one of the plurality of bit lines using a second predefined loopback; and a control circuit comprising: