Patent ID: 8447008
Filing Date: 2013-05-21
Classification: H03K

Abstract:
1. A shift frequency demultiplier with automatic reset function which is N-frequency demultiplication, wherein N>2, comprising: N-1 registers connected with each other and defined from a first register to an (N-1)th register; N-2 AND gates defined from a first AND gate to an (N-2)th AND gate and a reverser, wherein each of said N-1 registers has an input end, an output end, a reset end and a clock end, wherein for said registers from said first register to said (N-2)th register, said output end of every register is connected with said input end of a next register adjacent thereto, said output end of said (N-1)th register is connected with said input end of said first register by said reverser, wherein said reset end of said (N-1)th register is connected with a system reset signal end, said system reset signal end and said output end of said (N-1)th register are respectively connected with two input ends of each of said N-2 AND gates, an output end of each of said N-2 AND gates is connected with said reset end of a corresponding register, wherein said clock end of each of said N-1 registers is connected with a clock signal end.