Patent ID: 9105567
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A process of making an electrostatic discharge diode in an integrated circuit, comprising: A. forming an N-type buried layer in a semiconductor substrate; B. forming a deep N-type implant region in the substrate extending down from a first level of the substrate to the N-type buried layer; C. forming a first N well region in the substrate and extending down to the N-type buried layer; D. forming a second N well region in the substrate and extending down from the first level of the substrate to the N-type buried layer, the second N well region being formed next to the deep N-type implant region; E. forming a P-type epitaxial region in the substrate and extending down from the first level of the substrate to the N-type buried layer between the first N well region and the second N well region; and F. forming a P-type source/drain region in the substrate over the first N well region and a portion of the P-type epitaxial region.