Patent ID: 9141173
Filing Date: 2015-09-22
Classification: G06F,Y02D

Abstract:
1. A method for thread consolidation in a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip, the method comprising: running an application having software threads on the operating system; mapping the software threads to physical cores in the multi-core processing chip; identifying one or more idle hardware threads in the multi-core processing chip; identifying one or more idle accelerator units in the accelerator chip; executing the software threads on the physical cores and the accelerator unit; obtaining, by the controller module, performance and power consumption information from the multi-core processing chip and the accelerator chip at predetermined intervals; determining whether to consolidate the software threads based on performing an efficiency calculation, wherein the efficiency calculation is a function of the obtained performance and power consumption information at predetermined intervals before consolidation; consolidating, by the controller module, the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core, the consolidating responsive to the obtained performance and power consumption information; activating, by the controller module, a power savings mode for the one or more idle physical cores; performing an additional efficiency calculation based on performance and power consumption values obtained before and after the consolidating comparing the calculated efficiency to a threshold value; and undoing the consolidating if the calculated efficiency is below the threshold value.