Patent ID: 9059811
Filing Date: 2015-06-16
Classification: H04J,H04L

Abstract:
1. A computer-implemented method of adjusting a local clock at a receiver in a packet network, wherein the local clock is generated by a phase locked loop locked to a master clock with the aid of time-stamped timing packets arriving over the network from the master clock with a packet delay distribution about a nominal delay, comprising: filtering the timing packets to adjust for the packet delay distribution; deriving a control input for the phase locked loop from the timing packets; determining an amount of skew in the packet delay distribution about the nominal delay, where the skew represents the departure from a Gaussian distribution, by computing an average arrival time, separating the timing packets into early and late packets arriving before and after the average arrival time, and statistically processing the arrival times of the separated timing packets to determine the skew; and prior to filtering the timing packets, selectively adjusting the arrival times of timing packets to correct for the amount of skew by adjusting the arrival time of the timing packets to a value that would be expected if the packet delay distribution was Gaussian packet delay distribution.