Patent ID: 6248652
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:forming a first dielectric layer to be a gate dielectric film on a surface of a one conductivity type semiconductor substrate;forming a second dielectric layer on said first dielectric layer;forming a third dielectric layer on said second dielectric layer;forming a groove of predetermined width, in said second and third dielectric layer to a depth which exposes a surface of said first dielectric layer;forming a heavily doped region in said semiconductor substrate through said groove, the heavily doped region being located at a predetermined depth from said surface of said semiconductor substrate below said groove, having the same conductivity type as said semiconductor substrate and having a higher dopant concentration than that of said semiconductor substrate, with the width of the heavily doped region being substantially equal to the width of the groove;forming an electrode material in said groove;removing said second and third dielectric layers; andforming diffusion layers by introducing an opposite type dopant into said semiconductor substrate using said electrode material as a mask.