Patent ID: 6943591
Filing Date: 2005-09-13
Classification: H03K,H04L

Abstract:
1. An apparatus for detecting a fault condition in a differential signal having a valid common-mode voltage, comprising: an input buffer circuit that is arranged to produce a first buffered signal and second buffered signal in response to the differential signal; a first comparator circuit that is arranged to produce a first signal in response to the first buffered signal and a first reference signal; an integrator that is arranged to provide a first integrated signal in response to the first buffered signal, and the first comparator circuit is arranged to produce the first signal in response to the first integrated signal and the first reference signal, whereby the integrator operates as a speed trap, and wherein the integrator includes a level shifter circuit and a capacitance circuit, the level shifter circuit providing isolation between the input buffer circuit and the capacitance circuit, and the capacitance circuit is arranged to average the first buffered signal; a second comparator circuit that is arranged to produce a second signal in response to a second buffered signal and second reference signal; and an output circuit that is arranged to produce a fault detection signal in response to the first signal and the second signal, whereby the fault detection signal indicates the fault condition that is due to at least one of a short condition, an open condition, and a termination by abnormal means.