Patent ID: 6023179
Filing Date: 2000-02-08
Classification: H03K

Abstract:
A method of implementing a flip-flop, said flip-flop configured to receive a clock signal having a first clock period followed by a second clock period, said flip-flop having a first mode and a second mode, said method comprising:configuring said flip-flop into one of said first mode and said second mode;during a second phase of said first clock period, providing from said flip-flop an output signal having a constant logic level;during a first phase of said second clock period:precharging a voltage of a node of said flip-flop to a predetermined logic level, andmaintaining said output signal with said constant logic level provided during said second phase of said first clock period; andduring a second phase of said second clock period:receiving an input signal corresponding to said one of said first mode and said second mode;causing said voltage of said node to be at a logic level as a function of a logic level of said input signal received during said second phase of said second clock period,providing said output signal with a logic level as a function of said logic level of said input signal received during said second phase of said second clock period, andmaintaining said predetermined logic level of said voltage of said node when said input signal has a logic level that remains unchanged for a predetermined time period beginning when said second phase of said second clock period begins.