Patent ID: 8426308
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A method for use in fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; etching a semiconductor substrate to form a primary via hole in an upper surface of the substrate; forming a layer of low-k dielectric material that extends into the primary via hole and covers the upper surface of the substrate; selectively etching the layer of low-k dielectric material to remove some of the material from the primary via hole and leave low-k dielectric material on the upper surface of the substrate, thereby simultaneously forming a via insulating layer of low-k dielectric material on surfaces that delimit sides and the bottom of the primary via hole, and an inter metal dielectric layer of low-k dielectric material on the upper surface of the semiconductor substrate, wherein the via insulating layer delimits a secondary via hole within the primary via hole; form a metal layer on the semiconductor substrate including within the secondary via hole; and removing the metal layer from the upper surface of the semiconductor substrate.