Patent ID: 6812079
Filing Date: 2004-11-02
Classification: H01L,Y10S

Abstract:
A method of fabricating a junction field effect transistor (JFET) comprising:a) on an n++ substrate, forming an n-type epitaxial layer comprising a dopant concentration less than said n++ substrate; b) forming a n+ source region disposed on top of a surface of said n-type epitaxial layer, said n+ source region having a dopant concentration in between said n++ substrate and said n-type epitaxial layer; c) forming a plurality of well regions in said n-type epitaxial layer surrounding said n+ source region; d) forming a plurality of p-type gate regions surrounding bottoms of said plurality of well regions in said n-type epitaxial layer; and e) forming an altered n-type epitaxial region below said plurality of well regions for extending depletion regions surrounding said plurality of p-type gate regions into said n-type epitaxial layer without compromising an active region of said JFET.