Patent ID: 6614702
Filing Date: 2003-09-02
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array comprising a plurality of memory cells; a pair of bit lines coupled to at least one memory cell of the memory cell array; a sense amplifier having a pair of sense amplifier inputs wherein the sense amplifier senses a difference between voltages of the pair of sense amplifier inputs and amplifies the voltage difference; a pair of isolation switches wherein each isolation switch of the pair is coupled between one of the pair of bit lines and one of the pair of sense amplifier inputs wherein the pair of isolation switches electrically couples the respective bit lines and the sense amplifier inputs responsive to a coupling signal provided on an isolation control signal line coupled to control electrodes of the isolation switches; a control switch coupled between the isolation control signal line and a power voltage node of the sense amplifier wherein the control switch electrically couples the isolation control signal line to the power voltage node of the sense amplifier during a first period of operation of the sense amplifier for the memory cell.