Patent ID: 8823561
Filing Date: 2014-09-02
Classification: H04J,H04W

Abstract:
1. A de-mapping circuit for a de-mapping of input words of a first length into output words of a second length different from the first length, comprising: a word register of the first length for successively storing each of the inputs words responsive to cycles of a clock; a plurality of temporary registers of the second length for temporarily storing the output words, a plurality of sets of first multiplexers corresponding to the plurality of temporary registers, each first multiplexer configured to select a bit from the input words stored in the word register, the sets corresponding to the temporary registers such that the bits selected by each set of first multiplexers are stored by the corresponding temporary register to form the temporarily-stored output words, wherein the selection by the first multiplexers is configured by address signals; and a memory for storing the address signals for the multiplexers.