Patent ID: 8890599
Filing Date: 2014-11-18
Classification: H02H,H03K

Abstract:
1. A circuit comprising: a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage, wherein the clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold; a first switch to supply the reference voltage to the comparator, the first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage; and a second switch coupled to the input voltage and a second feedback path in the comparator, the second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.