Patent ID: 6490196
Filing Date: 2002-12-03
Classification: G11C,H01L

Abstract:
A method of programming, reading, and erasing a flash memory cell capable of storing two bits (â€œleftâ€  bit and â€œrightâ€  bit) of information, said flash memory cell comprising an embedded gate electrode formed in a trench of a substrate and isolated from said substrate by an ONO layer deposited on an interior surface of said trench, an N-type drain region located on surface of said substrate and next to said embedded gate electrode, an N-type source region located beneath said trench in said substrate and having a distance from said drain region, and left and right P-type doping regions formed, respectively, between said drain region and said source region on left and right sides of said embedded gate electrode in said substrate, the method comprising:executing a programming process, comprising the steps of: applying a negative word line voltage on said gate electrode; applying a positive bit line voltage on said drain region; grounding said source region and said first doping region; and applying a negative voltage on said second doping region; executing an erase process, comprising the steps of: applying a positive word line voltage on said gate electrode; floating said drain region; grounding said source region and one of said first doped region and said second doped region; and applying a negative voltage on the other one of said first doped region and said second doped region; executing a read process, comprising the steps of: applying a positive word line voltage on said gate electrode; grounding said drain region and said first doping region; applying a positive source line voltage that is lower than said word line voltage on said source region; and applying a negative voltage on said second doping region.