Patent ID: 6110827
Filing Date: 2000-08-29
Classification: H01L,Y10S

Abstract:
A planarization method for a self-aligned contact process suitable for use on a silicon substrate having a preformed MOS transistor that forms a construction having an uneven surface, the method comprising:forming an oxide layer on and in conformance with the uneven surface;forming an etch discriminatory layer on and in conformance with the oxide layer surface;forming a planarization layer above the etch discriminatory layer, the planarization layer filling up the uneven surface and creating a smooth plane surface, wherein the oxide layer, the etch discriminatory layer and the planarization layer are formed in the above order;forming a contact window mask above the planarization layer; andsequentially etching, using the contact window mask as a cover, first the planarization layer, then the etch discriminatory layer, followed by the oxide layer, to expose source/drain terminals of the MOS transistor.