Patent ID: 9052888
Filing Date: 2015-06-09
Classification: G06F

Abstract:
1. A computer-implemented method executed by at least one processor for processing a plurality of instructions in a computer program to be executed by a processor that includes a vector processing unit that processes a plurality of vector instructions that operate on data in a plurality of vector registers, the method comprising the steps of: analyzing a portion of the computer program; generating from a first set of instructions in the computer program that does not include any of the plurality of vector instructions a second set of instructions that includes at least one of the plurality of vector instructions; determining when a second cost of processing the second set of instructions is less than a first cost of processing the first set of instructions; when the second cost is less than the first cost, determining when the second set of instructions is likely to cause the processor running the computer program to stall when executing the second set of instructions by determining a ratio of vector instructions in the second set of instructions to total instructions in the second set of instructions; when the second set of instructions is not likely to cause the processor running the computer program to stall when executing the second set of instructions, substituting the second set of instructions for the first set of instructions in the computer program; when the second cost is not less than the first cost or when the second set of instructions is likely to cause the processor running the computer program to stall when executing the second set of instructions, not substituting the second set of instructions for the first set of instructions in the computer program.