Patent ID: 6248632
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A method of forming a gate electrode with a polycide structure in a semiconductor device, comprising the steps of:forming a gate insulating layer on a semiconductor substrate;forming a doped polysilicon layer on the gate insulating layer;forming a nitrogenous polysilicon layer on the surface of the polysilicon layer, wherein the nitrogenous polysilicon layer is formed by ion-implanting nitrogen ion (N2.sup.+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen;forming a metal suicide layer on the nitrogenous polysilicon layer, wherein the metal silicide is formed of a compound selection from the group consisting of vanadium silicide (VSi.sub.2), chromium silicide (CrSi.sub.2) and zirconium silicide (ZrSi.sub.2); andetching the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer sequentially to form a gate electrode.