Patent ID: 8642989
Filing Date: 2014-02-04
Classification: G11C,H01L

Abstract:
1. A Resistive Random Access Memory (RRAM) cell comprising a two-state resistor and a resistive switching memory cell connected in series, wherein the two-state resistor comprises a lower conductive electrode, a two-state resistor functionality layer, and a middle conductive electrode, and wherein the two-state resistor functionality layer comprises an n-p-n junction or a p-n-p junction consisted of any one or more of doped Si, Ge, GaAs, InP, and SiGe, wherein the two-state resistor is configured so that: the two-state resistor comes into a low-resistance state from a high-resistance state when a forward sweeping voltage reaches a forward ON voltage V when the sweeping voltage is swept back from V the two-state resistor comes into the low-resistance state from the high-resistance state when a reverse sweeping voltage reaches a reverse ON voltage V when the sweeping voltage is swept back from V