Patent ID: 7290201
Filing Date: 2007-10-30
Classification: G11C,H03K,H04L

Abstract:
1. A method comprising: receiving an input clock signal having a first set of edges and a second set of edges; receiving a first set of data values associated with the first set of edges of the input clock signal and a second set of data values associated with the second set of edges of the input clock signal; providing a first clock signal with a first clock manager in response to the input clock signal, wherein the first clock signal has a third set of edges that are synchronous with the first set of edges of the input clock signal; storing the first set of data values in response to the third set of edges of the first clock signal; providing a second clock signal with a second clock manager in response to the input clock signal, wherein the second clock signal has a fourth set of edges that are synchronous with the second set of edges of the input clock signal; and storing the second set of data values in response to the fourth set of edges of the second clock signal.