Patent ID: 6108235
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A memory device, in which a plurality of memory blocks are provided and which performs a writing and an erasing of data by units of said memory blocks, comprising:a writing/erasing circuit for writing data to or erasing data from a selected memory block in response to a write/erase signal;a protection designation storage unit for storing, for each of said memory blocks, protection designation data for inhibiting the writing and the erasing of data; anda specific block designation storage unit for storing, for each of said memory blocks, specific block designation data for inhibiting a release of protection,wherein, when the release of protection is not effected, a writing/erasing operation by said writing/erasing circuit is inhibited in accordance with said protection designation data which corresponds to said selected memory block; when the release of said protection is effected and said specific block designation data corresponding to said selected memory block are in a non-designating state, said writing/erasing operation is permitted; and when the release of protection is effected but said specific block designation data corresponding to said selected memory block are in a designating state, said writing/erasing operation is inhibited in accordance with said protection designation data.