Patent ID: 6744297
Filing Date: 2004-06-01
Classification: H03K

Abstract:
An inverter circuit comprising:an input end receiving an input signal having a low level and a high level, wherein said low level is greater than zero volt; a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to said input end and a source electrode coupled to a voltage source; a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of said PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground; a voltage drop device coupled to said gate electrode of said first NMOS transistor and said input end to provide a voltage drop from said input end to said gate electrode of said first NMOS transistor; a discharge path coupled between said voltage dray device and around for facilitating voltage drop effect of said voltage drop device, thereby eliminating a current leakage of said first NMOS transistor at said low level of said input signal; and a fourth N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode and a source electrode connected to said voltage drop device and said discharge path in series, respectively, and a gate electrode coupled to said input end for further voltage drop.