Patent ID: 6388927
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A system for testing a semiconductor memory device, said system comprising:a first common line within the memory device, wherein the first common line is coupled to each of a first set of bit lines within an array of bit lines; a second common line within the memory device, wherein the second common line is coupled to each of a second set of bit lines within the array, and wherein the first and second sets of bit lines are interleaved such that one bit line of the second set is interposed between two adjacent bit lines of the first set; a voltage source adapted to apply a voltage between the first and second common lines; a current monitor, adapted to detect a current between the first and second common lines induced by the applied voltage; and a plurality of switches, wherein a first set of the switches is adapted to electrically connect each bit line of the first set of bit lines to the first common line only when a test signal is active, and wherein a second set of the switches is adapted to electrically connect each bit line of the second set of bit lines to the second common line only when the test signal is active.