Patent ID: 6624461
Filing Date: 2003-09-23
Classification: G11C,H01L

Abstract:
A memory arrangement comprising:a first conductive layer; an insulating layer; a second conductive layer that is separated from the first conductive layer by the insulating layer; a plurality of memory cells, the memory cells each comprising: at least one selection transistor; and a stacked capacitor arranged between the first and second conductive layer; the memory arrangement further comprising word lines configured to drive a predetermined plurality of the memory cells; bit lines configured to drive the predetermined plurality of the memory cells, the bit lines comprising at least one first bit line and at least one second bit line, the first bit line and the second bit line being complementary to one another upon a readout of the memory cells, the bit lines being respectively conducted partly in the first conductive layer and the bit lines being connected from there to at least a part of the plurality of memory cells and the bit lines being respectively conducted in part in the second conductive layer, wherein a part of the first bit line or, respectively, a part of the second bit line that is conducted in the first conductive layer and a part of the first bit line or, respectively, a part of the second bit line that is conducted in the second conductive layer are connected to one another through the insulating layer via at least one first contact or, respectively, via at least one second contact; and at least one of the first contact and the second contact are arranged above an active region overlapping with a via hole to one of the memory cells.