Patent ID: 7836372
Filing Date: 2010-11-16
Classification: G01R

Abstract:
1. A memory controller comprising: a write data buffer configured to store write data received from one or more write operations on an interconnect to which the memory controller is coupled, wherein the one or more write operations are sourced by one or more processors coupled to the interconnect; a plurality of drivers configured to drive write data from the write data buffer on a plurality of pins to which a plurality of memory modules are capable of being coupled, wherein each of the plurality of drivers is coupled to a respective one of the plurality of pins; a plurality of receivers configured to receive data from the plurality of pins, wherein each of the plurality of receivers is coupled to the respective one of the plurality of pins; a merge buffer which, in a normal mode of operation, is configured to store addresses and corresponding data of one or more read-modify-write operations, and wherein a read address from a first read operation received from the interconnect is compared to addresses in the merge buffer to determine which data to provide in response to the first read operation; and a controller that, in a loopback test mode of operation and in response to a first write operation, is configured to cause first write data to be transmitted from the write data buffer through the plurality of drivers and the plurality of receivers, wherein the write data is captured from the plurality of receivers in the merge buffer, and wherein, in response to the first read operation and in response to a match in the comparison of the read address to the addresses in the merge buffer, the controller is configured to cause the first write data to be transmitted on the interconnect from the merge buffer.