Patent ID: 8111543
Filing Date: 2012-02-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising a memory cell configured to store data, wherein the memory cell comprises: a first inverter comprising a first load transistor and a first drive transistor connected in series; a second inverter comprising a second load transistor and a second drive transistor connected in series, comprising an output connected to an input of the first inverter, and an input connected to an output of the first inverter; a first write access transistor comprising a drain connected to a gate of the second drive transistor, a gate of the second load transistor, a drain of the first drive transistor, and a drain of the first load transistor; a second write access transistor comprising a drain connected to a drain of the second drive transistor, a drain of the second load transistor, a gate of the first drive transistor, and a gate of the first load transistor; a first access transistor comprising a drain connected to a source of the first write access transistor; a second access transistor comprising a drain connected to a source of the second write access transistor; a first read drive transistor comprising a source connected to the source of the first write access transistor, a gate connected to the drain of the first write access transistor, and a drain set to a voltage source potential; a second read drive transistor comprising a source connected to the source of the second write access transistor, a gate connected to the drain of the second write access transistor, and a drain set to the voltage source potential; a write word line connected to a gate of the first write access transistor and a gate of the second write access transistor; a read word line connected to a gate of the first access transistor and a gate of the second access transistor; a first bit line connected to a source of the first access transistor; and a second bit line connected to a source of the second access transistor.