Patent ID: 6366616
Filing Date: 2002-04-02
Classification: G06T,H04N

Abstract:
A motion vector estimating apparatus, comprising:processing elements of M columns and N rows (M and N are positive integers), wherein said processing elements are cascade-connected in each of said N rows, wherein each of said processing elements calculates an absolute value of a difference between a corresponding pixel data of a current block and one pixel data of each of reference blocks, and adds the absolute value to an output from a previous state of processing element to output the adding result to a next state of processing element, and wherein said N rows are cascade-connected to allow pipeline processing; M reference data column buses provided for said M columns, respectively; N reference data row buses provided for said N rows, respectively; (MÃ—N) selectors, which are respectively provided for said processing elements to allow one of the pixel data on the corresponding one of said M reference data column buses and the pixel data on the corresponding one of said N reference data row buses to said corresponding processing element as the reference block pixel data; and a current block pixel data bus for transferring current block pixel data to each of said processing elements, wherein said processing elements are cascade-connected in each of said N rows (N is an even number), wherein odd-numbered ones of said N rows in an upper half are cascade-connected via first FIFO units, each of which is provided for two adjacent odd-numbered rows, wherein even-numbered ones of said N rows in said upper half are cascade-connected via second FIFO units, each of which is provided for two adjacent even-numbered rows, wherein odd-numbered ones of said N rows in a lower half are cascade-connected via third FIFO units, each of which is provided for two adjacent odd-numbered rows, and wherein even-numbered ones of said N rows in said lower half are cascade-connected via fourth FIFO units, each of which is provided for two adjacent odd-numbered rows, and wherein said block matching circuit further includes fifth and sixth FIFO units connected to last stages of processing elements in said cascade connections for the odd-numbered rows and the even-numbered rows in said upper half, respectively.