Patent ID: 7675322
Filing Date: 2010-03-09
Classification: H03K

Abstract:
1. A level shifting circuit, comprising: a level shifting unit configured to generate first and second output signals responsive to first and second input signals, respectively, the first and second input signals ranging between first and second voltage levels, the first and second input signals being a first differential pair, the first and second output signals ranging between the first voltage level and a third voltage level greater than the second voltage level, the first and second output signals being a second differential pair, a duty ratio of the first and second output signals being determined based on delay times of the first and second input signals; and an output buffer unit configured to invert the first and second output signals to provide third and fourth output signals respectively; wherein the level shifting unit comprises: an output unit, coupled to a high power supply voltage node, that provides the first and second output signals, the output unit comprising a cross-coupled latch having first and second P-type metal-oxide-semiconductor (PMOS) transistors, a gate terminal of the first PMOS transistor being coupled through the delay control unit to a drain terminal of the second PMOS transistor, a gate terminal of the second PMOS transistor being coupled through the delay control unit to a drain terminal of the first PMOS transistor, source terminals of the first and second PMOS transistor being coupled to the high power supply voltage node, the first and second output signals being provided at the drain terminals of the first and second PMOS transistors, respectively; an input unit, coupled to the delay control unit and a ground voltage node that receives the first and second input signals, the input unit comprising first and second N-type metal-oxide-semiconductor (NMOS) transistors having gate terminals to which the first and second input signals are respectively provided, and source terminals that are coupled to the ground voltage node; and a delay control unit, coupled to the output unit, that controls the delay times of the first and second input signals to match duties of the first and second output signals, the delay control unit comprising: a first transmission gate coupled between the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor; and a second transmission gate coupled between the drain terminal of the second PMOS transistor and the drain terminal of the second NMOS transistor.