Patent ID: 6919750
Filing Date: 2005-07-19
Classification: H03L

Abstract:
1. A clock signal generation circuit for generating multiphase clock signals in accordance with a master clock signal having a predetermined frequency, comprising: a master DLL circuit section adapted to generate a first delay signal obtained by delaying the master clock signal by a first delay time and generate a first pulse signal having a pulse width of the first delay time in accordance with the master clock signal and the first delay signal; a multiphase clock generation circuit section adapted to generate multiphase internal clock signals in accordance with the master clock signal and generate delay internal clock signals obtained by delaying the multiphase internal clock signals, respectively; and a slave DLL circuit section constituted by slave DLL circuits each for delaying, by a second delay time, corresponding one of the delay internal clock signals generated by the multiphase clock generation circuit section, thereby outputting the delayed delay internal clock signals which form the multiphase clock signals, wherein the master DLL circuit section generates a first control signal which is changed in voltage in accordance with the first pulse signal, and adjusts the first delay time to have a first predetermined value in accordance with the generated first control signal, and wherein each of the slave DLL circuits generates a second pulse signal having a pulse width of the second delay time, and generates a second control signal which is changed in voltage in accordance with the first and second pulse signals, and adjusts the second delay time to have a second predetermined value in accordance with the generated second control signal.