Patent ID: 6205508
Filing Date: 2001-03-20
Classification: G06F

Abstract:
A multiprocessing computer system comprising:an I/O subsystem;an I/O interrupt controller coupled to receive a first interrupt request from said I/O subsystem and to responsively generate a first interrupt message;a plurality of processing nodes, wherein each of said plurality of processing nodes includes:a corresponding processor core, anda corresponding local interrupt controller coupled to said corresponding processor core,wherein a first processing node of said plurality of processing nodes is coupled to receive said first interrupt message, wherein said first processing node is configured to determine a first interrupt message recipient for said first interrupt message, wherein said first interrupt message recipient includes at least one of said plurality of processing nodes; anda plurality of dual-unidirectional links, wherein each dual-unidirectional link interconnects a respective pair of processing nodes from said plurality of processing nodes,wherein said first processing node is configured to generate a first interrupt command from said first interrupt message and to route said first interrupt command to said first interrupt message recipient through a first one of said plurality of dual unidirectional links without having to arbitrate for said first one of said plurality of dual unidirectional links.