Patent ID: 6347050
Filing Date: 2002-02-12
Classification: G11C

Abstract:
A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in, and a junction-field-effect transistor of a first conductivity type for current control,said semiconductor memory cell having;(a) a first semi-conductive region having a second conductivity type, (b) a second semi-conductive or conductive region formed in a surface region of the first region, said second region forming a rectifier junction together with the first region, (c) a third semi-conductive region formed in a surface region of the first region and spaced from the second region, said third region having a first conductivity type, (d) a fourth semi-conductive or conductive region formed in a surface region of the third region, said fourth region forming a rectifier junction together with the third region, and (e) a fifth semi-conductive or conductive region formed in a surface region of the third region and spaced from the fourth region, said fifth region forming a rectifier junction together with the third region, wherein;(A-1) source/drain regions of the first transistor are constituted of the second region and the third region, (A-2) a channel forming region of the first transistor is constituted of a surface region of the first region sandwiched by the second region and the third region, (A-3) a gate region of the first transistor is formed on a barrier layer formed on the surface region of the first region sandwiched by the second region and the third region, (B-1) source/drain regions of the second transistor are constituted of the first region and the fourth region, (B-2) a channel forming region of the second transistor is constituted of a surface region of the third region sandwiched by the first region and the fourth region, (B-3) a gate region of the second transistor is formed on a barrier layer formed on the surface region of the third region sandwiched by the first region and the fourth region, (C-1) gate regions of the junction-field-effect transistor are constituted of the fifth region and a portion of the first region facing the fifth region, (C-2) a channel region of the junction-field-effect transistor is constituted of part of the third region sandwiched by the fifth region and said portion of the first region, (C-3) source/drain regions of the junction-field-effect transistor are constituted of the third region extending from both ends of the channel region of the junction-field-effect transistor, (D) the gate region of the first transistor and the gate region of the second transistor are connected to a first memory-cell-selecting line, (E) the second region is connected to a predetermined potential, (F) the fourth region is connected to a second memory-cell-selecting line, and (G) the fifth region is connected to a second predetermined potential.