Patent ID: 9159663
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having an upper surface and a lower surface opposite to the upper surface, the substrate being defined by first and second sides opposite to each other and by third and fourth sides opposite to each other, the substrate further comprising a plurality of first and second bond fingers and a plurality of first and second lands, the plurality of first and second bond fingers each including a plurality of first and second input/output (I/O) bond fingers, and the plurality of first and second lands each including a plurality of first and second I/O lands; a first semiconductor chip stacked on the upper surface of the substrate, the first semiconductor chip having a first end portion near the first side of the substrate and a second end portion near the second side of the substrate, the first semiconductor chip comprising a plurality of first electrode pads disposed along a line extending between the first and second end portions of the first semiconductor chip and being parallel to the third and fourth sides of the substrate, the plurality of first electrode pads including a plurality of first I/O electrode pads and a plurality of first command and address (CA) electrode pads, the plurality of first I/O electrode pads arranged on the first end portion; each one of the plurality of first I/O bond fingers being connected to a corresponding one of the plurality of first I/O electrode pads, the plurality of first I/O bond fingers arranged next to the first I/O electrode pads and arranged near the first side of the substrate; each one of the plurality of first I/O lands being connected to a corresponding one of the plurality of first I/O bond fingers, the plurality of first I/O lands arranged next to the plurality of first I/O bond fingers and arranged near the first side of the substrate; a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a third end portion near the first side of the substrate and a fourth end portion near the second side of the substrate, the second semiconductor chip comprising a plurality of second electrode pads disposed along a line extending between the third and fourth end portions of the second semiconductor chip and being parallel to the third and fourth sides of the substrate, the plurality of second electrode pads including a plurality of second I/O electrode pads and a plurality of second CA electrode pads, the plurality of second I/O electrode pads arranged on the fourth end portion; each one of the plurality of second I/O bond fingers being connected to a corresponding one of the plurality of second I/O electrode pads, the plurality of second I/O bond fingers arranged next to the second I/O electrode pads and arranged near the second side of the substrate; and each one of the plurality of second I/O lands being connected to a corresponding one of the plurality of second I/O bond fingers, the plurality of second I/O lands arranged next to the plurality of second I/O bond fingers and arranged near the second side of the substrate, wherein an edge of the first end portion of the first semiconductor chip substantially aligns with an edge of the third end portion of the second semiconductor chip in a stacking direction of the first and second semiconductor chips.