Patent ID: 8717807
Filing Date: 2014-05-06
Classification: G11C

Abstract:
1. A static random access memory comprising a memory cell array storing at least one piece of data and including a plurality of memory cells each containing a first inverter, a second inverter, a first control FinFET (Fin-based Field Effect Transistor) and a second control FinFET, wherein said first inverter and said second inverter are cross coupled to each other, and wherein said first control FinFET is connected to said first inverter, and wherein said second control FinFET is connected to said second inverter; a plurality of first bit lines and second bit lines, wherein each said first bit line is connected to said first control FinFETs, and wherein each said second bit line is connected to said second control FinFETs; a plurality of read-control lines each supplying a read voltage and each connected to said memory cells arranged in an identical horizontal row parallel to said read-control line; a plurality of read-control FinFETs each connected to all said memory cells and all said second bit lines and controlling the read data, wherein each said read-control FinFET includes a plurality of read voltage control lines each connected to said source and determining voltages of that said memory cells are connected to; and a plurality of keeper circuits supplying a keeping voltage when said second bit line is at a high-level voltage, and each connected to said memory cells arranged along an identical vertical column along the bit line direction.