Patent ID: 6118158
Filing Date: 2000-09-12
Classification: H01L,Y10S

Abstract:
A static random access memory (SRAM) device having a memory cell array region in which a plurality of unit cells are arranged in a matrix such that cells adjacent in the Y-axial direction are symmetrical with respect to the X-axis, and cells adjacent in the X-axial direction are symmetrical with respect to the Y-axis, the unit cell comprising:first and second P-wells and an N-well, all formed in a rectangular region such that the N-well is sandwiched between the first and second P-wells;first and second P-well pick-up regions, the first P-well pick-up region being formed in the first P-well, and the second P-well pick-up region being formed in the second P-well, the first and second P-well pick-up regions being arranged at opposite corners of the rectangular region;a first active region formed in the first P-well at a predetermined distance from the first P-well pick-up region;a second active region formed in the second P-well at the predetermined distance from the second P-well pick-up region, the second active region being substantially similar in shape to the first active region, but displaced in location from the first active region by a rotation of 180 degrees around the center of the rectangular region;a third active region formed in the N-well between the first and second active regions, the third active region being in the shape of a bar pattern parallel to the Y-axial direction, wherein a lower end of the bar pattern of the third active region is elongated to a lower border of the N-well;a fourth active region formed in the N-well between the first and second active regions, the fourth active region being in the shape of a bar pattern parallel to the Y-axial direction, wherein an upper end of the bar pattern of the fourth active region is elongated to an upper border of the N-well, the fourth active region being substantially similar in shape to the third active region, but displaced in location from the third active region by a rotation of 180 degrees around the center of the rectangular region;a first N-well pick-up region formed in the N-well contacting a first side end of the third active region, and elongated to a first side border of the N-well;a second N-well pick-up region formed in the N-well contacting a second side of the fourth active region, and elongated to a second side border of the N-well;a first gate electrode arranged adjacent to the second active region, crossing the first active region and the third active region adjacent to the first active region;a second gate electrode arranged adjacent to the first active region, crossing the second active region and the fourth active region adjacent to the second active region;first and second word lines arranged parallel to the Y-axis, crossing the first and second active regions;a first contact for electrically connecting the first and second gate electrode to the second and first active regions, respectively;a second contact for electrically connecting the first and second gate electrodes to the third and fourth active regions, respectively;first and second power contacts each for exposing the first N-well pick-up region and the third active region adjacent to the first N-well pick-up region, and the second N-well pick-up region and the fourth active region adjacent to the second N-well pick-up region, respectively;a power line arranged in the Y-axial direction, covering the first and second power contacts;a first ground contact for exposing the first active region located between the first N-well pick-up region and the P-well pick-up region;a second ground contact for exposing the second active region located between the second N-well pick-up region and the P-well pick-up region;a first ground line arranged in the Y-axial direction, covering the first ground contact;a second ground line arranged in the Y-axial direction covering the second ground contact;a first bit line contact for exposing the first active region located at the border of the first P-well region;a first bit line arranged in the X-axial direction, covering the first bit line contact;a second bit line contact for exposing the second active region located at the border of the second P-well region; anda second bit line arranged in the X-axial direction, covering the second bit line contact.