Patent ID: 6919260
Filing Date: 2005-07-19
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor substrate having shallow trench isolation regions and a device region sandwiched by the shallow trench isolation regions, without using doped silicon oxide containing a melting-temperature-lowering dopant of boron or phosphorus for lowering the melting-temperature of the silicon oxide for performing reflow by doped silicon oxide for planarization, the method comprising: (a) forming a plurality of grooves on part of a surface of the semiconductor substrate; (b) depositing oxide films in the grooves by a CVD method using an electrically inert organic silicon source, which does not contain the melting-temperature-lowering dopant; (c) removing upper parts of the oxide films so as to planarize a surface of a resultant structure until surface areas of the semiconductor substrate are substantially exposed, each of the exposed surface areas of the semiconductor substrate serving as a top surface of a corresponding device region; and (d) changing ring structure of the oxide films, after said removing, by annealing the semiconductor substrate so as not to melt the oxide films at a substrate temperature which is greater than or equal to 1150° C. but less than or equal to 1350° C. so that dislocation density generated in the corresponding device region in a vicinity of the grooves is less than 1 μm