Patent ID: 6405321
Filing Date: 2002-06-11
Classification: G06F

Abstract:
Apparatus for processing data, said apparatus comprising:(i) a processor core operable under control of program instructions; (ii) a clock circuit for supplying a system clock signal to said processor core; (iii) a test clock circuit for supplying a test clock signal to said processor core; (iv) a clock selector for selecting which one of said system clock signal and said test clock signal drives operation of said processor core; and (v) an auxiliary circuit coupled to said processor core and driven by said system clock signal irrespective of which clock signal is selected for supply to said processor core by said clock selector, said auxiliary circuit being accessed by said processor core only when executing a program instruction from a subset of said program instructions; (vi) wherein said clock selector selects said system clock signal during normal operation and said test clock signal during loading of program instructions during test operation, said clock selector being responsive to one or more clock selecting bits within each program instruction to be executed during said test operation to select independently for each program instruction either said test clock signal or said system clock signal for driving said processor core to execute that program instruction, said clock selector selecting said system clock signal to drive operation of said processor core during test operation to execute a program instruction from said subset of program instructions such that operation of said processor core is synchronized with said auxiliary circuit.