Patent ID: 7029999
Filing Date: 2006-04-18
Classification: H01L

Abstract:
1. A method for fabricating a transistor with a polymetal gate electrode structure, the method comprising: forming a gate insulation layer on a substrate; forming a patterned gate stack structure over the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a lower layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer, the silicon oxide-based capping layer including a horizontal portion and a vertical portion that together enclose the patterned gate stack structure; and performing a gate re-oxidation process, wherein the silicon oxide-based capping layer is formed by performing an atomic layer deposition (ALD) technique which includes the steps of: