Patent ID: 7186617
Filing Date: 2007-03-06
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, comprising: forming a resistor pattern on a substrate; forming an interlayer dielectric layer on the resistor pattern; patterning the interlayer dielectric layer to form at least one opening exposing the resistor pattern; and forming a plug pattern that fills the at least one opening, wherein the plug pattern and the resistor pattern are comprised of a same material wherein forming the resistor pattern comprises: forming a device isolation layer that defines a cell array region and a resistor region in the substrate; forming a gate insulation layer on the cell array region; forming a first conductive layer on the gate insulation layer and the substrate; patterning the first conductive layer to form a first conductive pattern, the first conductive pattern exposing the device isolation layer; forming a gate interlayer dielectric layer on the first conductive pattern that has at least one opening that exposes a top surface of the first conductive pattern; forming a second conductive layer on the gate interlayer dielectric layer; and patterning the second conductive layer, the gate interlayer dielectric layer and the first conductive pattern to form a cell gate pattern and the resistor pattern in the cell array region and the resistor region, respectively.