Patent ID: 6821812
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A process for mounting, in a large substrate, a small sample having formed in one surface thereof integrated circuit structure, said small sample mounted in said large substrate in a manner which permits access to said integrated circuit structure on said surface of said small sample, while suppressing formation of a visible gap around the edge of the sample comprises:a) first mounting said small sample in a tapered opening formed completely through an intermediate die with said surface of said sample having said integrated circuit structure therein mounted adjacent the small portion of said tapered opening directly abutting one or more edges of said small portion of said tapered opening in said die; and b) then mounting said intermediate die in an opening in said large substrate in a manner wherein said surface of said small sample having said integrated circuit structure faces away from said opening in said large substrate to permit access to said integrated circuit structure by test equipment; wherein said tapered opening in said die is sized to equal at least one dimension of said small sample to thereby suppress formation of a visible gap between said small portion of said tapered opening and said one or more edges of said small sample.