Patent ID: 6707740
Filing Date: 2004-03-16
Classification: G11C

Abstract:
A semiconductor memory comprising:a plurality of memory cells; a plurality of sense amplifiers for amplifying parallel read data from said memory cells, respectively; a plurality of read amplifiers for amplifying said read data amplified in said sense amplifiers up to respective predetermined logic levels, in which at least one of the read amplifiers has a higher drivability than drivabilities of the rest of the read amplifiers; a connection switching circuit for connecting said sense amplifiers to a predetermined one of said read amplifiers, according to an address; a data output circuit for outputting said read data amplified in said read amplifiers in order, starting from read data corresponding to said read amplifier having a higher drivability, during burst read operation in which said read data are successively outputted to the exterior of the memory; and a plurality of data bus lines for connecting said read amplifiers and said data output circuit, respectively.