Patent ID: 6249878
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A system, comprising:(A) a bus;(B) an addressable memory coupled to the bus, such memory comprising:(a) a control logic; and(b) a random access memory;(c) a buffer memory coupled between the bus and a random access memory, such buffer memory having:(1) a write buffer memory;(2) a read buffer memory;(3) an operation selection section having:(i) a plurality of operation units, each one thereof being configured to perform a predetermined operation on data fed to a pair of input ports thereof, one of such input ports being fed by an output of the write buffer memory and the other input port being fed by an output of the read buffer memory; and,(ii) a selector fed by outputs of the plurality of operation units, for coupling a selected one of the operation unit outputs to the random access memory selectively in accordance with a control signal fed to the selector by the control logic.