Patent ID: 6781646
Filing Date: 2004-08-24
Classification: G02F,H01L

Abstract:
A substrate comprising:a plurality of scanning wires; a plurality of signal wires intersecting said scanning wires in a matrix fashion; and a plurality of semiconductor elements placed at intersection points between said scanning wires and said signal wires wherein each of said plurality of semiconductor elements includes: a semiconductor layer having a channel region and a pair of semiconductor regions of a given conductivity type which sandwich said channel region and which are each made of a high-resistance region and a low-resistance region; a first electrode formed on said channel region with an insulating film interposed therebetween; and a second and a third electrode connected to the low-resistance regions of said pair of semiconductor regions of said given conductivity type; wherein each of said plurality of scanning wires comprises said first electrode of the corresponding one of said plurality of semiconductor elements; and wherein said first electrode has a first wiring formed on said insulating film and a second wiring formed on said first wiring such that said second wiring is directly in contact with a side surface of said first wiring, part of said second wiring being overlaid on part of the high-resistance regions of said pair of semiconductor regions of said given conductivity type with said insulating film interposed therebetween.