Patent ID: 6303451
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method for forming a transistor within an integrated circuit comprising the steps of:providing a semiconductor substrate;forming a gate dielectric layer overlying the semiconductor substrate;forming a gate electrode overlying the gate dielectric layer;forming a spacer layer overlying the gate electrode;etching the spacer layer to form a structure and a sidewall spacer, wherein the structure comprises the sidewall spacer and the gate electrode, and wherein a first portion of the sidewall spacer overlies a first portion of the semiconductor substrate, a second portion of the sidewall spacer overlies a second portion of the semiconductor substrate, and the gate electrode lies between the first portion of the sidewall spacer and the second portion of the sidewall spacer;measuring at least a portion of the structure, after etching the spacer layer to determine an implant condition; andimplanting a dopant into the semiconductor substrate using the implant condition to form a first doped region and a second doped region.