Patent ID: 7151308
Filing Date: 2006-12-19
Classification: H01L

Abstract:
1. A semiconductor chip package, comprising: an interconnection substrate; a peripheral substrate having an opening; a central substrate being disposed in the opening of the peripheral substrate and substantially coplanar with the peripheral substrate, wherein the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate; a semiconductor chip sandwiched between the interconnection substrate and the central substrate, the interconnection substrate having a recessed cavity for receiving the semiconductor chip; a plurality of central solder balls disposed on a bottom surface of the central substrate and electrically connected to the semiconductor chip; and a plurality of peripheral solder balls disposed on a bottom surface of the peripheral substrate and electrically connected to the semiconductor chip through the interconnection substrate; wherein the peripheral substrate is substantially separated from the central substrate thereby decreasing the stresses on the peripheral substrate due to coefficient of thermal expansion mismatch; and the central substrate and the peripheral substrate are completely separated from each other.