Patent ID: 7669017
Filing Date: 2010-02-23
Classification: G06F,H04L

Abstract:
1. A method of buffering data in a circuit processing data in both a natural address order and a modified address order, the method comprising: storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading a portion of the first block of data stored in the buffer according to the other addressing order of the natural address order and the modified address order; reading the entire first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading data of the first block of data stored in the buffer according to the other addressing order, wherein writing is disabled when reading the portion of the first block during the step of reading the portion of the first block of data.