Patent ID: 7072222
Filing Date: 2006-07-04
Classification: G11C

Abstract:
1. A nonvolatile memory comprising: a plurality of nonvolatile memory cells each of which has an arbitrary one of a programmed state and an erased state; a plurality of input/output terminals; a command decode circuit which is capable of decoding an arbitrary one of commands received via said plurality of input/output terminals; a voltage generator; a plurality of word lines; and a control circuit, wherein in performing an erase operation in response to decoding an erase command by said command decode circuit, said control circuit controls shifting a state of all of said nonvolatile memory cells coupled to one word line to said erased state, wherein in performing a program operation in response to decoding a write command, which is accompanied with address information and data, by said command decode circuit, said control circuit controls selection of one word line in accordance with said address information, supply of a program voltage generated by said voltage generator to said one word line, and storage of said data into first ones of said nonvolatile memory cells coupled to said one word line, wherein said write command is capable of being accompanied with 512 byte data, wherein all of said first ones of said nonvolatile memory cells coupled to said one word line have said erased state before performing said program operation, and wherein another one of said nonvolatile memory cells coupled to said one word line has said programmed state before performing said program operation and has said programmed state after performing said program operation.