Patent ID: 6016071
Filing Date: 2000-01-18
Classification: G06F,H03L,Y02D

Abstract:
A switchable internal source clock generation circuit for use in a power management system to provide a system clock signal, comprising:synchronous counter circuitry with a synchronous load input and an asynchronous clear input, the synchronous counter circuitry configured to provide, at an output, a count output clock signal;multiplexer circuitry having a first input and a second input; andflip-flop circuitry having an input coupled to the output of the multiplexer circuitry, and an output, wherein the output of the flip-flop circuitry is sampled responsive to a reference clock signal and is provided as the system clock signal, wherein the reference clock signal is referenced to an external oscillator clock,wherein:the first input of the multiplexer circuitry is coupled to receive the count output clock signal and the second input of the multiplexer is coupled to the output of the flip-flop circuitry; andthe multiplexer circuitry includes selection circuitry that selects, to provide to the output of the multiplexer circuitry and responsive to a state of a selection control signal, one of the output of the flip-flop circuitry, such that the system clock signal has a first frequency, and the count output clock signal, such that the system clock signal has a second frequency.