Patent ID: 6137995
Filing Date: 2000-10-24
Classification: H03C,H03L,H04B

Abstract:
An integrated transceiver circuit, comprising:a single side-band mixer in a receiver section of the integrated transceiver circuit having a first input coupled for receiving a first signal and a second input coupled for receiving a second signal; anda phase lock loop in a transmitter section of the integrated transceiver circuit having an input coupled to an output of the single side-band mixer, wherein the phase lock loop supplies an output signal that has a frequency that differs from the first signal by a programmable offset frequency, wherein the phase lock loop further comprises:a phase detector having a first input coupled to an output of the single side-band mixer;a summing circuit having a first input coupled to an output of the phase detector and a second input coupled for receiving a third signal;a low pass filter having an input coupled to an output of the summing circuit;a controlled oscillator having an input coupled to an output of the low pass filter; anda frequency dividing circuit having an input coupled to an output of the controlled oscillator and an output coupled to a second input of the phase detector.