Patent ID: 6828194
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method of programming a Flash EEPROM memory cell device, wherein said Flash EEPROM memory cell comprises:a semiconductor substrate; a tunneling oxide layer overlying said semiconductor substrate; a floating gate overlying said tunneling oxide; an interpoly dielectric overlying said floating gate; a control gate overlying said interpoly dielectric; a shallow and abrupt drain junction within said semiconductor substrate adjacent to said tunneling oxide layer; an angled pocket junction lying within said semiconductor substrate adjacent to said drain junction and counter-doped to said drain junction; and a deeper and less abrupt source junction lying within said semiconductor substrate; wherein said method of programming said Flash EEPROM cell comprises the steps of: applying a voltage to said drain junction of said cell to effect a positive bias above a common ground reference; applying a voltage to said control gate of said cell to effect a positive bias above said common ground reference; applying a voltage to said substrate of said cell to effect a negative bias below said common ground reference; floating said source junction of said cell; and charging said floating gate of said cell by back bias hot electron injection sufficiently to program said cell.