Patent ID: 6348805
Filing Date: 2002-02-19
Classification: G01R

Abstract:
A method for determining a pin layout for a test fixture for an electrical interconnect device, the test fixture having a plurality of test points each of which is to be connected to one of a plurality of grid points using one of a plurality of pins that is associated with said one of a plurality of grid points, comprising the steps of:for each of a plurality of said test points, identifying adjacent grid points that are within a first predetermined deflection distance; determining a difficulty metric for each of said plurality of test points based on the number, density and location of competing test points; assigning one of said pins and its associated grid point to each of said test points according to the difficulty metric, with the test points having the highest difficulty metric being assigned pins first; and redetermining the difficulty metric for those test points within a maximum deflection distance of each test point as it is assigned a pin.