Patent ID: 8054138
Filing Date: 2011-11-08
Classification: G06F,H03B,Y02D

Abstract:
1. An electronic circuit comprising: a first oscillator generating a first clock, a power supply impedance of the first oscillator being configured to be variable and controllable; a second oscillator generating a second clock, a frequency of the second clock being higher than a frequency of the first clock; a third oscillator generating a third clock, a frequency of the third clock being higher than the frequency of the second clock; and a control circuit setting the power supply impedance of the first oscillation circuit to a high impedance when the second and the third oscillators are halted, setting the power supply impedance of the first oscillator to a medium impedance when the second oscillator is in operation and the third oscillator is halted, and setting the power supply impedance of the first oscillator to a low impedance when the third oscillator is in operation and the second oscillator is halted.