Patent ID: 6190982
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating a metal-oxide-semiconductor (MOS) transistor on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, the method comprising:forming a gate in a predetermined area on the surface of the semiconductor wafer;performing a first ion implantation process to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD);forming a uniform and oxygen-free dielectric layer on the surface of the semiconductor wafer that covers the gate;forming a silicon oxide layer on the surface of the dielectric layer;performing an anisotropic dry etching process to vertically remove a portion of the silicon oxide layer, a remaining portion of the silicon oxide layer forming a spacer on each wall of the gate; andperforming a second ion implantation process to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.