Patent ID: 9153499
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate including first, second, and third source/drain regions; a first conductive plug in contact with the first source/drain region, wherein the first conductive plug has a first width and a first height and includes a first material; an interlayer insulating layer shaped and dimensioned to cover the first conductive plug and the substrate; a second conductive plug shaped and dimensioned to vertically penetrate the interlayer insulating layer and to contact the second source/drain region, wherein the second conductive plug has a second width and a second height and includes a second material; an etch stop layer on the interlay insulating layer and the second conductive plug; a third conductive plug shaped and dimensioned to vertically penetrate the interlayer insulating layer and to contact the third source/drain region, wherein the third conductive plug has a third width and a third height and includes a third material, wherein the second material is formed of a noble metal, a noble metal oxide or a perovskite-based conductive oxide; a lower electrode formed on the interlayer insulating layer, wherein the lower electrode penetrates the etch stop layer, and wherein the lower electrode and the second conductive plug are integrally formed without an interface therebetween by continuously depositing the second material; a capacitor dielectric layer formed on the lower electrode; an upper electrode formed on the capacitor dielectric layer; and a supporter in direct contact with a sidewall of the lower electrode, wherein the capacitor dielectric layer is in direct contact with a top surface of the supporter and a bottom surface of the supporter.