Patent ID: 8078942
Filing Date: 2011-12-13
Classification: G06F

Abstract:
1. A processor comprising: a first register file configured to store speculative register state, the first register file protected by a first error protection scheme; a second register file configured to store committed register state, the second register file protected by a second error protection scheme; a check circuit coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed, wherein the check circuit is configured to detect an error in the value responsive to the value and the check bits; a control unit coupled to the check circuit and configured to cause reexecution of the first instruction responsive to the error detected by the check circuit; and a second check circuit coupled to receive a source operand read from the first register file for a second instruction and corresponding one or more check bits, wherein the second check circuit is configured to detect a source error in the source operand, and wherein the control unit is coupled to the second check circuit and is configured to cause reexecution of a second instruction responsive to the source error.