Patent ID: 6141631
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A method for simulating behavior of a logic cell including inertial delay behavior in a VITAL compliant system, said logic cell having an input port, an output port, and an intrinsic propagation delay, said input port being coupled to receive an input signal, said output port being coupled to generate an output signal, said method comprising the steps of:modeling said logic cell using a first internal VITAL logic cell model to represent said inertial delay behavior and a second internal VITAL logic cell model to represent transport delay behavior;specifying a first propagation delay associated with said first internal VITAL logic cell model and a transport delay associated with said second internal VITAL logic cell model;coupling said first and second internal logic cell models wherein said first internal VITAL logic cell model dictates said inertial delay behavior and wherein said second internal VITAL logic cell model accounts for said intrinsic propagation delay of said logic cell; andsimulating said logic cell.