Patent ID: 9026568
Filing Date: 2015-05-05
Classification: G06F,H03M

Abstract:
1. A computer system, comprising: a data processor and memory accessible by the data processor, the memory storing a data set; and a direct memory access (DMA) controller in communication with the data processor, the DMA controller comprising circuitry to control movement of the data set from a first element of the memory to a second element of the memory, where the second element of the memory has an access latency for accesses by the DMA controller that is longer than that of the first element of the memory, the data processor provides parameters via a DMA descriptor for a data compression procedure by the DMA controller, the parameters including an identifier of the data set to be moved and parameters identifying characteristics of the data compression procedure, the DMA controller including logic to perform data compression according to the parameters identifying the characteristics of the data compression procedure on the data set in the first element of the memory to form a compressed data set, and to store the compressed data set and parameters identifying characteristics of the compressed data set in the second element of the memory, wherein the data compression procedure produces one or more packets of compressed data of the compressed data set, wherein the parameters include indicators of a number of packets and a number of samples per packet in the compressed data set.