Patent ID: 6174756
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method for forming an integrated circuit (IC) comprising:providing a substrate including as least first and second regions separated by an isolation region, the first region comprising first device features that are separated by wide gaps, the second region comprising second device features separated by narrow gaps, wherein the sides of the first and second devices include a first spacer formed from a dielectric material;depositing an interlevel dielectric layer to sufficiently fill the narrow gaps between the second device features in the second region;etching the interlevel dielectric layer, whereby the etching forms second spacers on the side of the first features over the first spacers and removes the interlevel dielectric layer on the top of wide spaces while leaving the narrow spaces in the first region filled with the interlevel dielectric layer,implanting dopants to form deep junctions for the first devices, wherein the interlevel dielectric layer used to form the second spacers of the first devices protects the second region from being affected by the implant.