Patent ID: 7326977
Filing Date: 2008-02-05
Classification: H01L

Abstract:
1. An FET, comprising: a two layer body of semiconductor material having a top surface; said body comprising a first layer of a first conductivity type and having a first dopant concentration; said body additionally comprising only a second layer on said first layer thereby constituting the remainder of said body and being of said same conductivity type and having a dopant concentration less than that of said first layer; substantially like spaced apart source and drain regions formed within said second layer in a symmetric structural arrangement and being of an opposite conductivity type than said first and second layers; an oxide coating on said top surface of said body; a buried channel region having a same said opposite conductivity type as said source and drain regions extending only between said source and drain regions at their lower extremity, said channel region being spaced below said top surface by a distance d, whereby a volume of semiconductor material of said same conductivity type as said second layer is provided between said source and drain regions and between a bottom surface of said oxide coating and a top surface of said buried channel region and a bottom surface of said oxide coating; a gate member on said oxide coating; a conductive well of said first conductivity type having a dopant concentration greater than that of said second layer located to the side of one region of said source and drain regions, and extending from said top surface of said body drain to a top surface of said first layer; connections for applying bias potential to said source and drain regions; and, a connection between said well and one region of said source and drain regions for connecting a predetermined potential to said first layer for preventing said body from electrically floating during operation.