Patent ID: 7610474
Filing Date: 2009-10-27
Classification: G06F

Abstract:
1. An apparatus comprising: a processor pipeline; and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline, the processor pipeline being configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions including (i) a first call-type instruction encountered by the first stage and an instruction in a delay slot for said first call-type instruction wherein said instruction in said delay slot is indicative of the tail-call elimination sequence and further wherein the instruction in the delay slot restores, to a designated location of the processor pipeline, a return address associated with a second call-type instruction after the first call-type instruction saves an associated return address to the designated location of the processor pipeline, and the processor pipeline being configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.