Patent ID: 8368440
Filing Date: 2013-02-05
Classification: H03L

Abstract:
1. A phase-locked loop (PLL) circuit comprising: a phase/frequency detector (PFD) configured to compare phase and frequency of an input signal with those of a feedback signal and generate a first signal; a digital filter configured to filter the first signal in a digital mode and generate first digital data comprising most significant bits (MSBs) and least significant bits (LSBs); a digital low pass filter (LPF) configured to a perform low-pass-filtering on the LSBs of the first digital data in the digital mode and generate filtered second digital data; a digitally-controlled oscillation (DCO) circuit configured to perform a digital-to-analog conversion (DAC) operation on the second digital data and the MSBs of the first digital data to generate a second signal, generate an oscillation control signal based on the second signal, and generate an output clock signal oscillating in response to the oscillation control signal; and a frequency divider configured to divide a frequency of the output clock signal to generate the feedback signal.