Patent ID: 6799264
Filing Date: 2004-09-28
Classification: G06F

Abstract:
A computer system comprising:a processor that is configured to execute the program instructions that are contained in a memory; and a memory access system that includes: a plurality of instruction latches, each instruction latch of the plurality of instruction latches being associated with a corresponding partition of a plurality of cyclically sequential partitions of the memory; wherein the memory access system is configured to co-temporaneously: determine whether an instruction addressed by the processor is contained in a first instruction latch of the plurality of instruction latches, based on an identification of the partition of the memory corresponding to the addressed instruction, load a first plurality of instructions, including the addressed instruction, from the memory and into the first instruction latch, if the addressed instruction is not in the first instruction latch, and load a second plurality of instructions from the memory and into a second instruction latch of the plurality of instruction latches, if the second plurality of instructions is not in the second instruction latch, so that the first and second plurality of items are available for direct access by the processor from the corresponding first and second instruction latches.