Patent ID: 7486532
Filing Date: 2009-02-03
Classification: G11C,H01L

Abstract:
1. A semiconductor multi-chip package, having n address pins and a control pin, comprising: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor chip whose memory density is greater than the first semiconductor memory chip, the second semiconductor chip being packaged on the first semiconductor memory chip and having at least (n+1) address pads, a second control pad, and a second address controller, wherein the n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins, wherein the first and second control pads are connected to a control pin, and wherein the first and second address controllers are operable in a mutually exclusive manner according to a signal applied to the control pin.