Patent ID: 6476692
Filing Date: 2002-11-05
Classification: H03B

Abstract:
A distributed balanced frequency multiplier comprising:a branching section, having first and second input transmission lines, each of said first and second input transmission lines having first and second ends, said first ends of first and second input transmission lines being coupled to a branch point, distributing a fundamental input signal from said branch point to said first and second input transmission lines; a joining section, having first and second output transmission lines, each of said first and second output transmission lines having first and second ends, said second ends of first and second output transmission lines being coupled to a join, synthesizing signals from said first and second output transmission lines at said join; a first transistor, having a control input and a current path, said control input being coupled to said second end of first input transmission line, a first end of said current path being grounded, a second end of said current path being coupled to said first end of first output transmission line; a second transistor, having a control input and a current path, said control input being AC grounded, first and second ends of said current path being coupled to said second end of second input transmission line and said first end of second output transmission line, respectively; and an amplitude attenuating element coupled to one of said first input transmission line, said second input transmission line, said first output transmission line, or said second output transmission line.