Patent ID: 7439542
Filing Date: 2008-10-21
Classification: H01L

Abstract:
1. An integrated semiconductor structure comprising: a substrate containing a second semiconducting layer having a second crystallographic orientation and a first upper surface, wherein said second crystallographic orientation is (110) or (111); a first epitaxial semiconductor material portion having a first crystallographic orientation, wherein said first crystallographic orientation is different from said second crystallographic orientation, and a second upper surface, wherein said second upper surface is coplanar with said first upper surface; a buried insulating layer located beneath said second semiconducting layer and a portion of said first epitaxial semiconductor material portion; a second epitaxial semiconductor material portion located in an opening in said buried insulator layer and epitaxially aligned to said first epitaxial semiconductor material portion; a first semiconductor layer contacting said buried insulating layer and said second epitaxial semiconductor material portion and having said first crystallographic orientation; and a first semiconductor device located on said second semiconducting layer and a second semiconductor device located on said first epitaxial semiconductor material portion, wherein said second semiconductor device includes source and drain diffusion regions that are located on said buried insulating layer, wherein a body portion of said second semiconductor device is in contact with said second epitaxial semiconductor material portion, wherein said opening has a width that is at least as great or smaller than a width of a gate conductor of said second semiconductor device.