Patent ID: 9029257
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method of planarizing a plurality of electrically conductive posts that extend into a semiconductor substrate, the method comprising: forming a liner across a substrate surface and along sidewall surfaces and top surfaces of the posts; forming fill material over the liner and between the posts, the fill material comprising one or more organic compositions; planarizing to form a planarized surface extending across the fill material, the liner and the posts; after the planarizing, (a) removing the fill material from between the posts while leaving the liner along sidewall surfaces of the posts and across the substrate surface between the posts, and (b) forming patterned electrically insulative material across the liner; the patterned electrically insulative material defining inset regions around planarized upper surfaces of the posts; forming electrically conductive caps within the inset regions and directly against the planarized upper surfaces of the posts and along the sidewall surfaces of the posts; regions of the conductive caps along the sidewall surfaces of the posts being spaced from the sidewall surfaces by the liner; and wherein the liner comprises silicon nitride having one or more pinholes extending therein; and wherein the patterned electrically insulative material fills said one or more pinholes.