Patent ID: 6237058
Filing Date: 2001-05-22
Classification: G06F

Abstract:
An interrupt load distribution system for determining the status of load for each processor in a shared bus type multiprocessor system, scheduling interrupt requests that are generated, and distributing load within the system, comprising:processor statistical information table for storing processor statistical information, consisting of processor activity ratios under the use by the operating system, processor activity ratios under the use by processes executing under a processor bind, and number of processes requesting a bind from each processor;interrupt schedule information table for storing interrupt schedule information which represents a basic rule for distributing interrupt load within an appropriate range;interrupt scheduling means for referring to information in said processor statistical information table and said schedule information table at fixed time intervals and re-scheduling interrupt load distribution as necessary to achieve appropriate distribution; andnotifying means incorporating an interrupt notification destination information table that stores information concerning the destination to which an interrupt is to be notified, which is updated during re-scheduling by said interrupt scheduling means, for notifying the designated processor of an interrupt request based on information in said interrupt notification destination information table.