Patent ID: 7488660
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. A method for forming a structure in a semiconductor substrate, said structure including a gate electrode stack of a gate dielectric layer and a gate electrode formed over said substrate, and raised source/drain junctions, said method including the steps comprising: forming said gate electrode stack comprising said gate dielectric layer and said gate electrode on said substrate with said gate electrode stack having sidewalls and a top surface; forming Lightly Doped Drain/Doped Source (LDD/LDS) regions in said substrate self-aligned with said gate electrode; forming a conformal etch-stop layer on said device; forming sidewall spacers having a given width over said etch-stop layer on said sidewalls of said gate electrode stack; etching away portions of said etch-stop layer unprotected by said sidewall spacers; and forming Raised Source/Drain (RSD) regions on said substrate over exposed portions of said LDD/LDS regions in said substrate and covering said etch-stop layer over at least a portion of said sidewalls of said gate electrode.