Patent ID: 6939743
Filing Date: 2005-09-06
Classification: H01L

Abstract:
1. A method of packaging and interconnecting plural power transistor dies to operate at a first frequency, without oscillation at a second frequency higher than said first frequency but lower than a cutoff frequency of the transistors, the method comprising: mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common, interior central landing area of the conductive layer on the substrate via separate electrical leads, the leads being sized to substantially the same electrical length and providing a first impedance corresponding to said electrical length from the common area to each gate that will pass the first frequency substantially unattenuated and providing a second impedance from the gate of one die to the gate of a second die that will substantially attenuate the second frequency.