Patent ID: 7157335
Filing Date: 2007-01-02
Classification: H01L

Abstract:
1. A method of fabricating a dual bit memory device comprising: forming a charge trapping dielectric layer on a semiconductor substrate; depositing a resist layer on the charge trapping dielectric layer; patterning the resist layer to selectively leave openings in the resist layer; performing a bitline implant through the openings in the resist layer to form bitlines that operate as acting sources and acting drains; removing the resist layer; forming a wordline layer on the charge trapping dielectric layer; patterning the wordline layer to form wordlines that overlie the bitlines; forming a relatively thin undoped TEOS liner on the wordlines and the charge trapping dielectric layer; forming a BPTEOS interlayer dielectric layer on the relatively thin TEOS layer; forming wordline and bitline contact vias in the BPTEOS interlayer dielectric layer by selectively etching through the BPTEOS interlayer dielectric layer, and the relatively thin TEOS layer; forming bitline contacts in the bitline vias that contact bitlines and wordline contacts in the wordline vias that contact wordlines.