Patent ID: 9218852
Filing Date: 2015-12-22
Classification: G06F,G11C,Y02D

Abstract:
1. An apparatus comprising: a first semiconductor die including a memory core, wherein the memory core is a three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate and that includes circuitry associated with operation of the multiple memory cells; a second semiconductor die including periphery circuitry associated with the memory core; and a third semiconductor die that includes a memory controller, wherein the second semiconductor die includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of the memory controller, wherein the second semiconductor die further includes a memory interface coupled to the 3D memory core, wherein the memory controller includes a host interface configured to enable communication with a host device and wherein the first serializer/deserializer interface of the memory controller is configured to enable communication with the 3D memory core via the second semiconductor die, and wherein the memory controller at the third semiconductor die is configured to operate as a memory controller of the 3D memory core.