Patent ID: 6134649
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A processor comprising:a predecode unit configured to generate predecode information corresponding to a plurality of instruction bytes received by said processor, said predecode information including a first indication corresponding to a particular instruction byte within said plurality of instruction bytes, wherein said first indication is indicative, in a first state, that said particular instruction byte is a boundary of an instruction, and wherein said predecode information includes a control transfer indication corresponding to said particular instruction byte, and wherein said control transfer indication is indicative, in a first state, that said instruction of which said particular instruction byte is said boundary is a control transfer instruction, and wherein said control transfer indication is indicative of an alternate feature of said instruction if said first indication corresponding to said particular instruction byte is in a second state indicating that said particular instruction byte is not said boundary of said instruction; andan instruction cache coupled to said predecode unit, wherein said instruction cache is configured to store said plurality of instruction bytes and said predecode information received from said predecode unit.