Patent ID: 7210082
Filing Date: 2007-04-24
Classification: G01R,G06F

Abstract:
1. A method for performing ATPG and fault simulation for testing faults in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing two or more clocks, a plurality of combinational logic gates, and one or more scan chains, each scan chain comprising one or more scan cells coupled in series; said method comprising: (a) performing a forward and/or backward clock analysis on said scan-based integrated circuit to determine the driving and observing clocks for all inputs and outputs of said combinational logic gates belonging to said scan-based integrated circuit; (b) labeling selected inputs and outputs of said combinational logic gates belonging to said scan-based integrated circuit as unobservable and/or uncontrollable according to said selected clock order in said selected capture operation to eliminate the effects of clock skew between different clock domains; and (c) performing ATPG and/or fault simulation on said scan-based integrated circuit according to said selected inputs and outputs of said combinational logic gates and said selected capture operation.