Patent ID: 6653709
Filing Date: 2003-11-25
Classification: H01L

Abstract:
An output circuit with enhanced ESD performance for a CMOS integrated circuit device comprising:a driver PMOS transistor with source connected to a voltage supply, with gate connected to an input signal, and with drain connected to an output pad; a dummy PMOS transistor with source and gate connected to said voltage supply, and with drain connected to said output pad; a driver NMOS cascaded stack comprising a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor has source connected to ground and gate connected to said input signal, wherein said second NMOS transistor has gate connected to said voltage supply, source connected to said first NMOS transistor drain, and drain connected to said output pad, and wherein said second NMOS transistor has a pâˆ’ region underlying an n+ region only in said drain; and a dummy NMOS cascaded stack comprising a third NMOS transistor and a fourth NMOS transistor wherein said third NMOS transistor has gate and source connected to said ground, wherein said fourth NMOS transistor has gate connected to said voltage supply, source connected to said third MOS transistor drain, and drain connected to said output pad, and wherein said fourth NMOS transistor has a pâˆ’ region underlying an n+ region only in said drain.