Patent ID: 7542370
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A decoder circuit comprising: a first bias node for conveying a first selected voltage for a first mode of operation and a second selected voltage for a second mode of operation, said first bias node traversing and associated with a plurality of decoder output driver circuits; a second bias node for conveying a first unselected voltage for the first mode of operation and a second unselected voltage for the second mode of operation, said second bias node traversing and associated with the plurality of decoder output driver circuits; each of the plurality of decoder output driver circuits respectively comprising: a decoder output node; a first coupling circuit for coupling the decoder output node, when selected, to the first bias node; and a second coupling circuit coupled in series with a third coupling circuit, said second and third coupling circuits for coupling the decoder output node, when unselected in the first mode of operation, to the first unselected voltage conveyed on the second bias node and, when unselected in the second mode of operation, to the second unselected voltage conveyed on the second bias node, and for limiting the respective voltage across each of said second and third coupling circuits when the decoder output node is selected in each of the first and second modes of operation, to a value less than the difference between the first selected voltage and the first unselected voltage in the first mode of operation, and to a value less than the difference between the second selected voltage and the second unselected voltage in the second mode of operation.