Patent ID: 6593790
Filing Date: 2003-07-15
Classification: H03K

Abstract:
A power-up detector comprising a first PMOS FET having its gate connected to ground, and its source connected to a positive power supply, a pair of series connected resistors connected directly between the drain of said first PMOS FET and ground, a second PMOS FET having its source-drain circuit connected in series with an NMOS FET between said voltage power supply and ground, the drain of the NMOS FET being connected to the drain of said second PMOS FET, the gate of the second PMOS FET being connected to ground, the gate of the NMOS FET being connected to the junction between said pair of resistors, an output node at the junction between the drain of the second PMOS FET and the drain of the NMOS FET, and an inverter connected to the junction between the drains of said second PMOS FET and said NMOS FET.