Patent ID: 6603162
Filing Date: 2003-08-05
Classification: G03F,H01L

Abstract:
A semiconductor integrated circuit device comprising a semiconductor substrate having a semiconductor element formed over a main surface of the semiconductor substrate, a first pattern formed on said main surface or any layer on said main surface, and a second pattern formed over an upper layer of said first pattern,said first pattern comprises a plurality of first dummy patterns, said second pattern comprises a plurality of second dummy patterns having a pattern pitch and pattern width of identical design dimensions as said first dummy patterns, said second dummy patterns are formed over inter-pattern spaces of said first dummy patterns in its flat surface position, and each second dummy pattern is isolated from each of the other second dummy patterns, wherein: said first pattern further comprises another dummy pattern having a larger area than that of said first dummy pattern, said second pattern further comprises a pattern used for optical recognition, and said pattern used for optical recognition is formed so that it is enclosed within the flat shape of said other dummy pattern.