Patent ID: 7000080
Filing Date: 2006-02-14
Classification: G06F

Abstract:
1. In a computer system having a plurality of processors and a main memory organized into a plurality of memory blocks, the processors having one or more caches, a method for resolving a late race condition between a first processor and a second processor for a selected memory block, the method comprising: defining a plurality of channels within the computer system for exchanging command packets among the processors and main memory, the channels including a Q issuing a Write_Back (WB) command from the first processor to main memory, the WB command including a modified version of the selected memory block taken from the first processor's cache; forwarding from main memory to the first processor a memory reference request specifying the selected memory block, the memory reference request initiated by the second processor; in response to the memory reference request, issuing a Loop command from the first processor to main memory on the QWB channel; in response to the WB command, writing the modified data back to main memory; and in response to the Loop command, issuing a memory reference response from main memory to the second processor.