Patent ID: 6465299
Filing Date: 2002-10-15
Classification: H01L,Y10S

Abstract:
A method for fabricating a memory, comprising the steps of:(1) selectively etching a semiconductor substrate inclusive of an active region and a device isolation region for isolating the active region, to form a trench for forming a plurality of wordlines; (2) implanting impurity ions in an entire surface inclusive of the trench for forming wordlines; (3) forming wordlines at sides of the trench for forming wordlines including the steps of: (1) forming a gate oxide film, a polysilicon layer, and a silicide layer in succession on an entire surface inclusive of a trench, and selectively removing the gate oxide film, the polysilicon layer, and the silicide layer to leave the gate oxide film, the polysilicon layer, and the silicide layer only in the trench, and (2) selectively leaving the gate oxide film, the polysilicon layer, and the silicide layer only at sides of the trench for forming wordlines by photolithography; (4) forming the insulating layer for protecting the wordlines and a planar first ILD layer, and etching selectively, to form a bitline contact hole; (5) forming a bitline contact plug layer in the bitline contact hole, and forming a bitline in a direction vertical to the wordline; and, (6) forming a second ILD layer on an entire surface, forming a storage node contact, and stuffing the storage node contact hole, to form a storage node contact plug layer.