Patent ID: 7787296
Filing Date: 2010-08-31
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a plurality of memory blocks constituted by electrically programmable nonvolatile semiconductor memory cells; a memory cell array constituted by the plurality of memory blocks; an interface that communicates with an external device; an erase circuit to erase data in a selected memory block in accordance with an address and an erase command input to the interface, when the erase command is input from the interface, the erase circuit executing the erase command when a protect flag in the selected memory block has a first value and not executing the erase command when the protect flag has a second value; and a read circuit which reads, in accordance with the address input to the interface, the protect flag that is stored in a part of the selected memory block, the protect flag read by the read circuit being able to be output to the external device through the interface.