Patent ID: 6310912
Filing Date: 2001-10-30
Classification: H02M,H03M

Abstract:
A method for increasing a definition of conversion of a PWM signal using an up/down N-bit counter, the method comprising the steps of:increasing a dimension of an N-bit digital value to an N+2 bit digital value, the N+2 bit digital value having two least significant bits and N most significant bits;using the two least significative bits to select one among three intermediate levels between two consecutive values representable by an N-bit digital value according to a predefined table of combinations;using the N most significative bits to store four values in respective ones of four registers, the four stored values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit input digital value incremented by 1; andusing the two least significative bits and an up/down output signal of the up/down N-bit counter to select a pair of the four stored values to be compared during each up-counting phase and down-counting phase of the up/down N-bit counter as a function of the predefined table of combinations.