Patent ID: 6562687
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A method of manufacturing an MIS transistor on a semiconductor substrate comprising the steps of:a) forming a sacrificial dummy gate (112) on a pedestal layer (102) formed on a substrate (100), the dummy gate being set above a channel region (118) of the substrate; b) forming source and drain regions (114, 116) in the substrate such that they are self-aligned to lateral edges of the dummy gate and define, at least in part, the channel region; c1) coating the lateral edges of the dummy gate with at least one electrical insulation substance and removing the dummy gate to obtain a well (130) above the channel region; c2) forming interior lateral spacers (122) on the sides of the well; c3) doping a part (140) of the channel region by ionic implantation in the well, using the interior lateral spacers as an implantation mask; d) forming a definitive gate (150) in the well, the definitive gate separated from the substrate by a gate insulator layer, wherein the step of forming the definitive gate is preceded by a step of removing at least a part of the pedestal layer located at the bottom of the well and at least a part of the pedestal layer (102) extending under the spacers of the sides of the well, to form at least one recess (142) above a part of the source and drain regions, the definitive gate extending into said at least on recess.