Patent ID: 6088782
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A method for updating vector registers in a parallel processor, the parallel processor having a plurality of vector registers, a sequencer, and the method comprising:receiving an instruction in the sequencer;decoding the instruction;executing the instruction by performing the following steps:determining a source register from the plurality of vector registers, the source register having a plurality of source element positions each containing an associated source data value;reading a first source data value from a first source element position in the source register;determining a destination register from the plurality of vector registers, the destination register having a plurality of destination element positions each containing an associated destination data value;determining a destination rotation step value;rotating data values in the destination register through a number of element positions equal to the destination rotation step value; andwriting the first source data value into a predetermined element position in the destination register.