Patent ID: 8698545
Filing Date: 2014-04-15
Classification: G06G

Abstract:
1. Analog multiplier circuitry comprising: (a) a first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a first supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the first supply voltage; and (b) chopping circuitry including a first X switch for chopping a first differential input signal between sixth and seventh conductors to provide a corresponding chopped differential input signal between the second and fourth conductors, and a second X switch for un-chopping a first differential output signal produced between the third and fifth conductors by the first multiplier circuit to provide a corresponding un-chopped differential output signal between eighth and ninth conductors.