Patent ID: 7176093
Filing Date: 2007-02-13
Classification: H01L

Abstract:
1. A semiconductor processing method of forming integrated circuitry, comprising: forming a plurality of transistors, wherein a first transistor has a storage node defined by one of a drain and a source, and has a storage side including the storage node, wherein a second transistor has a storage node defined by one of a drain and a source, and a storage side including the storage node wherein the first transistor has a contact node, and has a contact side including the contact node, wherein the second transistor has a contact node and has a contact side including the contact node, wherein the contact side of the first transistor is adjacent the contact side of the second transistor; and masking the entire storage node of both the first and second transistors and thereafter simultaneously doping the contact nodes of the first and second transistors to form asymmetric junction profiles.