Patent ID: 7198968
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A method of fabricating a thin film transistor array substrate, comprising: forming a first conductive pattern group on a substrate using a first etch resist and a first soft mold, the first conductive pattern group including a gate electrode and a gate line; forming a gate insulating film on the substrate and the first conductive pattern group; forming a second conductive pattern group and a semiconductor pattern on the gate insulating film using a second etch resist and a second soft mold, the second conductive pattern group including a source electrode, a drain electrode, and a data line, the semiconductor pattern defining a channel region between the source electrode and the drain electrode; forming a passivation film on the gate insulating film, the second conductive pattern group and the semiconductor pattern using a third etch resist and a third soft mold, the passivation film defining a contact hole therethrough; and forming a third conductive pattern group on the passivation film using a fourth etch resist and a fourth soft mold, the third conductive pattern group including a pixel electrode.