Patent ID: 7069419
Filing Date: 2006-06-27
Classification: G06F

Abstract:
1. An integrated circuit comprising: a field programmable gate array (FPGA) core having logic clusters, static random access memory modules and routing resources; an FPGA virtual component interface translator having inputs and outputs, said inputs connected to said field programmable gate array core, wherein said FPGA virtual component interface translator is configured to translate signals from a first protocol to a second protocol; a microcontroller; a microcontroller virtual component interface translator having inputs and outputs, said inputs connected to said microcontroller, wherein said microcontroller virtual component interface translator is configured to receive a signal from said FPGA core in said second protocol and translate said signal into a third protocol for said microcontroller; a system bus connected to said outputs of said field programmable gate array virtual component interface translator and to said outputs of said microcontroller virtual component interface translator; and direct connection between said microcontroller and said routing resources of said field programmable gate array core.