Patent ID: 6856000
Filing Date: 2005-02-15
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semiconductor substrate with an upper surface; a n-type collector region contained in said semiconductor substrate; a p-type collector region contained in said semiconductor substrate and separated from said n-type collector region; a p-type base region contained in said n-type collector region; a n-type base region contained in said p-type collector region; a n-type emitter region with an upper surface contained in said p-type base region; a p-type emitter region with an upper surface contained in said n-type base region; a first interfacial oxide layer with an upper surface formed on said upper surface of said n-type emitter region; a second interfacial oxide layer with an upper surface formed on said upper surface of said p-type emitter region; a p-type polysilicon emitter layer formed on said upper surface of said second interfacial oxide layer wherein said p-type polysilicon emitter layer does not contain fluorine; and a n-type polysilicon emitter layer formed on said upper surface of said first interfacial oxide layer wherein said n-type polysilicon emitter layer contains fluorine.