Patent ID: 7345946
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A memory device circuit, comprising: a plurality of wordlines, each having a plurality of volatile memory cells coupled thereto; and a plurality of level shift circuits, one level shift circuit coupled to one corresponding wordline, each level shift circuit translating an input signal at a decode node that transitions between a first high voltage level and a first low voltage level to an output signal that transitions between a second high voltage level and second low voltage level, the second high voltage being higher than the first high voltage, the second low voltage being lower than the first low voltage; and a discharge circuit coupled to each wordline, each discharge circuit including a first discharge path that provides a first current path between at least one wordline and the first low voltage level and a second discharge path that provides a second current path between the at least one wordline and the second low voltage level, the second discharge path being enabled after the first discharge path is enabled, in a precharge operation.