Patent ID: 6069813
Filing Date: 2000-05-30
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory array having a main word line, a subword line corresponding to said main word line, a data line and a plurality of memory cells;a sense amplifier coupled to said data line;a decoder having an output terminal coupled to said subword line and a first input terminal coupled to said main word line; anda driver, coupled to a second input terminal of said decoder, outputting selection level voltage to be supplied to said subword line,wherein said memory array is formed in a first area,wherein said decoder is formed in a second area which is adjacent to said first area,wherein said driver is formed in a third area which is adjacent to said second area,wherein said sense amplifier is formed in a fourth area which is adjacent to said first and third areas,wherein said first, second, third and fourth areas are quadrilateral areas, andwherein said third area is an intersection area which is indicated by extending said second and fourth areas.