Patent ID: 7217610
Filing Date: 2007-05-15
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor product which has a semiconductor substrate with at least one memory region and a logic region, comprising: applying a dielectric layer serving as gate dielectric and a semiconductor layer to a surface of the semiconductor substrate in the memory region and in the logic region, the semiconductor layer comprises a first and a second partial layer, which covers the first partial layer either in the logic region or in the memory region, resulting in the semiconductor layer being reinforced in one of the two regions by application of the second partial layer to the first partial layer; patterning the semiconductor layer in the memory region with the formation of gate electrodes; introducing dopants for forming source and drain regions, in the memory region, adjacent to the gate electrodes formed there, into the semiconductor substrate; substantially filling the interspaces between the gate electrodes in the memory region with an insulation material; and patterning, in the logic region, the semiconductor layer with the formation of gate electrodes and the gate electrodes formed therein are doped, one portion of these gate electrodes being n-doped and the other portion being p-doped.