Patent ID: 8249199
Filing Date: 2012-08-21
Classification: H04L

Abstract:
1. A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus comprising: acquiring early votes, optimal votes, and late votes; determining which of the early votes, optimal votes, and late votes are allowed and weighted based on a criteria; disallowing the early votes, optimal votes, and late votes not determined as allowed based on the criteria; weighing the early votes, optimal votes, and late votes determined as allowed based on the criteria, wherein the early votes, optimal votes, and late votes that would make the CDR move to an extreme of a zero crossing are weighted less; accumulating the allowed and weighted early votes, optimal votes, and late votes and adjusting a recovered clock phase based on the accumulated early votes, optimal votes, and late votes; adding a lookup table in the CDR, wherein the lookup table comprises weights; determining which of the early votes, optimal votes, and late votes to weigh; and applying the weights to the early votes, optimal votes, and late votes, wherein the value of weight to be added or subtracted is looked up in the lookup table.