Patent ID: 7817652
Filing Date: 2010-10-19
Classification: H04L

Abstract:
1. A system for processing a data packet, the system comprising: a first data buffer comprising a first plurality of locations, the first data buffer configured to receive at least one input data packet comprising a plurality of data portions in a clock cycle comprising a plurality of subcycles by receiving a data portion of the plurality of data portions during each subcycle of the plurality of subcycles and to store each data portion of the plurality of data portions into a location of the first plurality of locations; a second data buffer comprising a second plurality of locations, each location of the second plurality of locations configured to store a data portion; a pointer table comprising a plurality of pointers configured to map the first plurality of locations to the second plurality of locations for avoiding a power spike; and a processor coupled to the first data buffer, the second data buffer, and the pointer table, the processor configured to generate an output data packet comprising a sequence of data portions having a sequential order, based on the plurality of data portions and the pointer table, the second data buffer further configured to store each data portion of the sequence of data portions into the second data buffer successively in the sequential order.