Patent ID: 7849428
Filing Date: 2010-12-07
Classification: G06F

Abstract:
1. A computer implemented method for implementing a clock gating scheme for at least one predefined section of logic comprised of a reference circuit design, wherein said reference circuit design is based on a predetermined reference clock gating scheme for said section of logic, characterised by the steps of: a) defining a trigger event for at least one predefined section of logic comprised of said reference circuit design, which trigger event defines a cycle in which valid input data arrive at said logic section's input; b) determining a latency time describing a propagation delay time for signal propagation between the input of said logic section and each output thereof; c) deriving a new clock gating scheme for said logic section, which has a reduced number of clock activations for a predefined set of latches comprised of said circuit section, resulting in a respectively modified circuit design; d) calculating, by the computer, relevant equivalence checking time points by adding said latency time to a time corresponding to said trigger event; e) performing a formal verification based, sequential equivalence check of the outputs of said reference circuit design and said modified circuit design only at said relevant time points; f) responsive to said sequential equivalence check indicating equivalent, defining said modified circuit design, which is associated with an improved clocking gating scheme than that one of said initial design, as a new reference design; and g) repeating steps c) to e) until a predefined loop exit criterion is evaluated to TRUE.