Patent ID: 6114767
Filing Date: 2000-09-05
Classification: H01L,Y10S

Abstract:
An EEPROM semiconductor device comprising:(a) a plurality of field insulating films each extending perpendicularly to word lines;(b) a plurality of memory cells arranged in a matrix, each memory cell including a floating gate, a control gate formed on said floating gate, the control gate also operating as one of said word lines that corresponds to a row in the matrix in which said each memory cell is disposed, and having source and drain regions located at either sides of said control gate;(c) a first bit line extending perpendicularly to said word lines and connecting drain regions of said memory cells with each other, said first bit line corresponding to a first metal wiring layer;(d) a first common source line extending in parallel with said word lines and connecting source regions of said memory cells with each other, said first common source line being disposed entirely above said word lines with respect to a distance from a semiconductor substrate, said first common source line having a top portion and a bottom portion with the top portion being wider than the bottom portion; and(e) a common extended source line that extends downwardly from said first common source line so as to connect said first common source line to a source region disposed within said semiconductor substrate, said common extended source line having a top portion and a bottom portion with the top portion of said common extended source line connected to the bottom portion of said first common source line, and with the top portion of said common extended source line being wider than the bottom portion of said common extended source line,wherein said first common source line corresponds to a second metal wiring layer,wherein said first common source line has a greater width than each of said word lines to result in a low resistance of said first common source line.