Patent ID: 6301649
Filing Date: 2001-10-09
Classification: G06F,G09G,G11C

Abstract:
A semiconductor memory device comprising:first and second memory banks each including a Y decoder, an X decoder, and a memory cell array having a plurality of X lines each including a plurality of memory cells;a control signal generator outputting control signals;an input/output circuit coupled to the memory cell arrays of the memory banks and said control signal generator;an address generator coupled to the X decoders and Y decoders of said memory banks and said control signal generator, said address generator outputting X and Y addresses to the X decoders and Y decoders in response to the control signals; andan address translator coupled to the address generator, said address translator receiving an address signal and translating the address signal to a predetermined address so that a plurality of serial line data of matrix data serially inputted into the semiconductor memory device are divided into continuous data sets each having a predetermined number of continuous data, and so that the continuous data sets are located on a first area including (2n-1)th X lines of the first bank and 2nth X lines of the second bank, and a second area including (2n-1)th X lines of the second bank and 2nth X lines of the first bank in turn, where n is a natural number,said address generator having a special serial Y address generator coupled to the Y decoders of the memory banks and an X address generator coupled to the X decoders of the memory banks, the special serial Y address generator fixing a low-order Y address and incrementing a high-order Y address during a row direction serial access mode, and the special serial Y address generator incrementing a Y address during a column direction serial access mode.