Patent ID: 6411560
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A semiconductor memory device comprising:plural memory cells; plural bit line pairs, provided correspondingly to said plural memory cells, and each for inputting or outputting data to or from a memory cell; plural sense amplifiers, provided correspondingly to said plural bit line pairs, and each supplying a first power supply voltage to one of a corresponding bit line pair when data is inputted to or outputted from said memory cell; plural global data line pairs provided correspondingly to said plural bit line pairs; a write/read circuit supplying a second power supply voltage lower than said first power supply voltage to one of a corresponding global data line pair when data is written onto said memory cell, and receiving said second power supply voltage from said one of said corresponding global data line pair when data is read from said memory cell; a column decoder circuit outputting an activation signal for activating a bit line pair provided correspondingly to a memory cell to or from which data is inputted or outputted among said plural bit line pairs when data is inputted to or outputted from said memory cell, and a deactivation signal for deactivating bit line pairs provided correspondingly to memory cells other than said memory cell to or from which data is inputted or outputted; and plural gate circuits provided correspondingly to said plural bit line pairs and said plural global data line pairs, wherein each of said plural gate circuits connects a corresponding bit line pair to a corresponding global data line pair when receiving said activation signal, while disconnecting a corresponding bit line pair from a corresponding global data line pair when receiving said deactivation signal, and a current flowing from said bit line pair toward said global data line pair through a gate circuit receiving said activation signal is smaller than a predetermined value.