Patent ID: 6011911
Filing Date: 2000-01-04
Classification: G06F

Abstract:
A computer implemented method for verifying a portion of layout data of an integrated circuit device where said layout data comprises a plurality of cells having parent-child relationships and organized according to a hierarchical tree, said method comprising the steps of:a) defining an array of top level bins corresponding to the surface area of a top level cell of said integrated circuit wherein a parent cell can include multiple top level bins;b) constructing a linked list for each top level bin wherein said linked list contains a listing of bins of all instances within said top level bin and any local geometry within said top level bin; andc) identifying overlap areas within said integrated circuit by searching through all link lists of said top level bins and recording top level bins having bins of two or more cell instances indicated in their corresponding linked lists; andd) performing layout verification only on layout geometries associated with said overlap areas identified in step c).