Patent ID: 7076714
Filing Date: 2006-07-11
Classification: G11C

Abstract:
1. A de-serializing circuit for a receive sub-vector that is a subset of Q-many bits associated with a previous serialization and whose de-serialized version is one member of a sequential plurality of similarly de-serialized received sub-vectors that combine to form a complete receive vector that is subsequently operated upon by a test system, the de-serializing circuit comprising: Q-many MUX's, each MUX having at least (Q+1)-many data inputs to which are coupled the bits of a receive sub-vector to be de-serialized, the correspondence between the (Q+1)-many data inputs and the bits of the receive sub-vector to be de-serialized being the same for each MUX; each MUX having an output bit that will represent the signal at one of the (Q+1)-many data inputs of that MUX; Q-many latches, each latch associated with a MUX and having an input coupled to the output bit of its associated MUX and also having an output coupled to an input of its associated MUX; each MUX also having a collection of at least m control inputs, 2 a memory having an address and containing addressable locations each storing a set of control signal values of (Q·m)-many bits representing the respective values of the m-many control signals for the Q-many MUX's and also having data outputs coupling members of the set of control signal values to the control inputs of their respective MUX's; the output bits for the Q-many MUX's forming an accumulated latched collection of sub-vectors constituting a de-serialized receive vector, according to a de-serialization defined by the addressed set of control signal values; and a programmatically controlled address applied to the memory and that selects a pre-defined de-serialization stored in the memory and that is to be performed upon the receive sub-vectors.