Patent ID: 6891546
Filing Date: 2005-05-10
Classification: G06F,G06T

Abstract:
1. A cache memory for three-dimensional graphics texture mapping, comprising: a first DRAM bank for storing all texels of predetermined upper levels of LOD (Level of Detail) and a second DRAM bank for storing only a working set currently needed among the remaining levels of LOD, wherein said first and second DRAM banks including SAM ports, respectively, each of said SAM ports reading a texture for a trilinear interpolation and fetching new texture sub-clips from the outside; a sub-clip loader connected to said SAM ports of said first and second DRAM banks and for fetching new texture sub-clips from an external system memory; a sub-clip predictor for performing a hardware-based prefetch of a sub-clip to be soon needed; a plurality of data paths providing between said first and second DRAM banks and a trilinear interpolator, said data paths being adapted to access eight texels existing in the integer coordinates and LOD mapped into a texture space of a pixel to be rendered on a display screen, such that a trilinear interpolation is performed in one clock cycle; a controller for controlling said components; and a CAM for checking if eight texels existing at an integer coordinate relative to an LOD and (u, v) coordinates are located in said first and second DRAM banks, when the LOD and (u, v) coordinates mapped into a texture space with respect to a pixel to be rendered on a display screen are input to said controller.