Patent ID: 7452807
Filing Date: 2008-11-18
Classification: H01L,Y10T

Abstract:
1. A method of forming a metal wiring in a semiconductor device, comprising: forming at least one metal layer on a substrate; forming at least one barrier metal layer on the at least one metal layer; forming a metal blocking layer on the at least one barrier metal layer; forming a hard mask layer on the metal blocking layer; forming a hard mask pattern on the metal blocking layer by partially etching the hard mask layer, without an exposure of the at least one barrier metal layer; forming a metal blocking layer pattern on the at least one barrier metal layer by partially etching the metal blocking layer using the hard mask pattern as an etching mask; and forming the metal wiring having at least one barrier metal layer pattern and at least one metal layer pattern on the substrate by partially etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask.