Patent ID: 6242954
Filing Date: 2001-06-05
Classification: G06F,H03L

Abstract:
A timing clock generation circuit for regulating a phase of a reference clock and generating a timing clock comprising:a first variable delay circuit which delays said reference clock for a delay time and outputs said timing clock, and which comprises a rough variable delay circuit including rough delay units and a fine variable delay circuit including fine delay units each having an unit delay time which is shorter than each of said rough delay units, wherein the rough and fine variable delay circuits are serially connected together;a feedback clock, said feedback clock having a same phase as said timing clock output from said first variable delay circuit;a variable clock, said variable clock generated by delaying said feedback clock with a dummy circuit for a predetermined time period;a rough phase comparing/delay controlling circuit for comparing the phase of the reference clock with a phase of said variable clock and controlling said rough variable delay circuit so that the phases of the reference and variable clocks match;a fine phase comparing/delay controlling circuit for comparing the phases of said variable clock and said reference clock and controlling said fine variable delay circuit so that the phases of the variable and reference clocks match; anda DLL controlling circuit for activating said rough phase comparing/delay controlling circuit at an initiation of phase adjustment, maintaining the delay time of said rough variable delay circuit after said rough phase comparing/delay controlling circuit detects lock on, and activating said fine phase comparing/delay controlling circuit, so as to cause said fine variable delay circuit to carry out delay control.