Patent ID: 8135557
Filing Date: 2012-03-13
Classification: G01R,G11C

Abstract:
1. A testing apparatus, comprising: an input part configured to input circuit description data in which a circuit structure of a semiconductor integrated circuit is described, a clock domain of the semiconductor integrated circuit, and a first test vector used to test a normal operation of the semiconductor integrated circuit; and an asynchronous transfer point extraction unit configured to extract an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain; a simulation unit configured to calculate a logic circuit output and a first external output in the normal operation of the semiconductor integrated circuit in accordance with the circuit description data and the first test vector; and a second test vector generation unit configured to randomly select any simulation time and generate a second test vector used to test a violation of the semiconductor integrated circuit by inverting a signal of an asynchronous transfer point of the logic circuit output when the signal of the asynchronous transfer point of the logic circuit output is not identified in the selected simulation time, wherein the simulation unit calculates a second external output in the violation of the semiconductor integrated circuit in accordance with the circuit description data and the second test vector.