Patent ID: 6274906
Filing Date: 2001-08-14
Classification: H01L,Y10S

Abstract:
A MOS transistor comprising:a semiconductor substrate doped with a first conductivity type-impurity;a gate insulating layer formed on the semiconductor substrate;a gate electrode formed on the gate insulating layer;a dielectric layer formed on the gate electrode;a first spacer formed on the dielectric layer;a second spacer formed on a first side wall of the first spacer;a first impurity layer of low concentration formed at a first depth by implantation of a second conductivity type impurity in the semiconductor substrate to be self-aligned near the edge of the gate electrode;a second impurity layer of middle concentration formed at a second depth deeper than the first depth by implantation of the second conductivity type impurity in the semiconductor substrate to be self-aligned near the edge of the first spacer;a third impurity layer having a higher impurity concentration than that of the semiconductor substrate, the third impurity layer being formed at a third depth such that it surrounds the second impurity layer of middle concentration, the third impurity layer having a side region horizontally located beyond a side region of the second impurity layer but not being horizontally located beyond a side region of the first impurity layer, the third impurity layer being formed by implantation of a first conductivity type impurity in the semiconductor substrate to be self-aligned near the edge of the first spacer; anda fourth impurity layer of high concentration formed at a fourth depth deeper than the third depth by implantation of the second conductivity type impurity in the semiconductor substrate to be self-aligned near the edge of the second spacer.