Patent ID: 6098167
Filing Date: 2000-08-01
Classification: G06F

Abstract:
A method for maintaining the architectural state of a processor having a set of architectural registers and an architectural register table which includes an entry corresponding to each respective architectural register, the method comprising the steps of:(a) dispatching an instruction which targets a target architectural register included in the set of architectural registers, the instruction being associated with an identification tag;(b) upon dispatch of the instruction, writing the identification tag associated with the instruction to a target architectural register table entry corresponding to the target architectural register if the identification tag associated with the instruction is more recent than a prior identification tag stored in the target architectural register table entry;(c) writing a content record of the target architectural register to an entry in a history buffer table upon dispatch of the instruction;(d) storing the result from executing the instruction directly to the target architectural register if the identification tag associated with the instruction matches the identification tag stored in the target architectural register table entry at the time the result from executing the instruction becomes available; and(e) storing the result from executing the instruction to an entry in the history buffer table if the identification tag associated with the instruction does not match the identification tag stored in the target architectural register table entry at the time the result from executing the instruction becomes available.