Patent ID: 6076098
Filing Date: 2000-06-13
Classification: G06F

Abstract:
An adder operable to receive first and second binary numbers and a carry signal indicative of a carry from a previous arithmetic operation, and operable to generate in parallel first and second sums derived from the first and second binary numbers and the carry signal, the first and second sums each having a plurality of bits, the first sum representing a sum of the first and second binary numbers and the carry signal, the second sum representing a sum of the first and second binary numbers and the carry signal plus one, the adder comprising:a carry look-ahead tree operable to receive the first and second binary numbers, and operable to generate a plurality of values derived from the first and second binary numbers;a summing circuit having a plurality of carry look-ahead tree input terminals operable to receive from the carry look-ahead tree a plurality of the values derived from the first and second binary numbers, the summing circuit further having at least one carry input terminal operable to receive the carry signal, the summing circuit being operable to generate at least one of the bits of the first sum in response to the plurality of bits received at the carry look-ahead tree input terminals and the carry signal, the summing circuit being operable to generate, in parallel with the at least one bit of the first sum, at least one of the bits of the second sum in response to the plurality of bits received at the carry look-ahead tree input terminals and the carry signal.