Patent ID: 7238555
Filing Date: 2007-07-03
Classification: G11C,H01L

Abstract:
1. A semiconductor fabrication process, comprising: forming a gate stack including a gate electrode overlying a gate dielectric overlying a channel body of a semiconductor substrate, the channel body overlying a buried dielectric layer; forming source/drain structures in source/drain regions of the substrate disposed on either side of the channel body, said forming of the source/drain structures including forming, in the source/drain regions, a layer of a second semiconductor material overlying a first semiconductor material, wherein a bandgap of the second material is different than a bandgap of the first material; forming a capping layer comprising the first semiconductor material overlying the layer of the second semiconductor material; and using the gate stack as a mask, patterning the capping layer and the layer of the second semiconductor material to form a two-dimensional migration barrier for liming vertical and lateral migration of majority carriers in the channel body.