Patent ID: 6944081
Filing Date: 2005-09-13
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of cell arrays including a plurality of blocks which comprises a plurality of memory cells and a means for reading data from said plurality of memory cells; a plurality of first word selecting signal lines for said plurality of cell arrays respectively, and said plurality of first word selecting signal lines extending in a first direction; a first word decoder selectively activating a first word selecting signal to be supplied to said plurality of first word selecting signal lines in accordance with an address signal; a plurality of second word selecting signal lines for said plurality of cell arrays respectively, and said plurality of second word selecting signal lines extending in a second direction different from said first direction, so that said plurality of second word selecting signal lines penetrate said plurality of blocks; a second word decoder selectively activating a second word selecting signal to be supplied to said plurality of second word selecting signal lines commonly to said plurality of blocks in accordance with said address signal; and a word driver for activating at least one word line in accordance with said first and second word selecting signals, wherein in a refresh operation, at least one cell array of said plurality of cell arrays is non-selected, and the remaining of said plurality of cell arrays is selected as at least one selected cell array, and said first and second word decoders of said at least one selected cell array are activated, and said first and second word selecting signals included in said at least one selected cell array are batch-selected by said first word decoder.