Patent ID: 7237081
Filing Date: 2007-06-26
Classification: G06F

Abstract:
1. A method of operating a digital system in a secure mode of operation, the digital system having a CPU with at least one interrupt source, comprising the steps of: authorizing entry of the CPU into the secure mode of operation; enabling access to a secure memory only when in secure mode; executing an environment setting routine from a portion of the secure memory, wherein environment setting routine re-maps interrupts from a non-secure interrupt vector table (IVT) in a non-secure memory to a secure IVT in a portion of the secure memory and then enables interrupts; executing a secure instruction routine from the secure instruction memory; and receiving an interrupt while executing the secure instruction routine such that the secure instruction routine is pre-empted and execution is transferred via the secure IVT to a secure interrupt service routine (ISR) in the secure memory, said secure ISR redirecting the CPU to perform an exception exit sequence that performs the steps of: