Patent ID: 9093642
Filing Date: 2015-07-28
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a non-volatile memory device including a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction intersecting the first direction, and a non-volatile memory cell array layer where a plurality of non-volatile memory cells are arranged at intersection portions of the first wirings and the second wirings so as to be interposed, the method comprising: sequentially stacking a first wiring material layer which is to be the first wiring and a memory-layer constituting layer constituting the plurality of non-volatile memory cells above a substrate; performing dry etching so that the memory-layer constituting layer and the first wiring material layer are etched to form a first pattern having a first line-and-space pattern extending in the first direction in a memory cell formation region and a first wiring hookup region adjacent to the memory cell formation region in the first direction and so that the memory-layer constituting layer and the first wiring material layer are removed in a second wiring hookup region adjacent to the memory cell formation region in the second direction; forming an interlayer insulating film to be embedded between line patterns constituting the first line-and-space pattern in the memory cell formation region and the first wiring hookup region, and forming the interlayer insulating film in a region which is removed by the dry etching in the second wiring hookup region; forming a second wiring material layer which is to be the second wiring on the interlayer insulating film and the memory-layer constituting layer; performing dry etching so that the second wiring material layer, the memory-layer constituting layer, and the interlayer insulating film are processed to form, in the memory cell formation region and the second wiring hookup region, a second pattern including a second line-and-space pattern extending in the second direction and a first dummy pattern, and so that the second wiring material layer and the memory-layer constituting layer are removed in the first wiring hookup region, the first dummy pattern being connected to all line patterns constituting the second line-and-space pattern; and removing at least a portion of the first dummy pattern.