Patent ID: 6063661
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAM, said stacked capacitor being formed on a silicon substrate and having a silicon dioxide layer, said bottom polysilicon electrode, a dielectric layer and a top polysilicon electrode, said method comprising the steps of:(a) forming by deposition a first polysilicon layer on said silicon dioxide layer;(b) doping impurity ions into said first polysilicon layer such that said first polysilicon layer becomes a doped first polysilicon layer;(c) activating said impurity ions doped into said first polysilicon layer such that said doped first polysilicon layer becomes an activated and doped first polysilicon layer;(d) following thereafter, forming by deposition a second polysilicon layer on said activated and doped first polysilicon layer whereby said second polysilicon layer is deposited directly and completely on said first polysilicon layer;(e) doping impurity ions into said second polysilicon layer such that said second polysilicon layer becomes a doped second polysilicon layer;(f) activating said impurity ions doped into said second polysilicon layer such that said doped second polysilicon layer becomes an activated and doped second polysilicon layer; and(g) etching with a phosphoric acid solution said activated and doped second polysilicon layer such that a rugged surface is formed on said activated and doped second polysilicon layer, while leaving said first polysilicon layer substantially unaffected by said etching.