Patent ID: 6392916
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A ferroelectric random access memory device comprising:a memory cell array including a plurality of memory cells where rows and columns are arranged with a matrix shape, wherein each of the memory cells has a ferroelectric capacitor and an access transistor; a sense amplifier circuit for sensing a data state of each of the memory cells using a reference voltage; and a reference circuit for supplying the reference voltage to the sense amplifier circuit, wherein the reference circuit includes: a dumping voltage supply circuit for generating dumping voltages when power is supplied, wherein voltage levels of the dumping voltages are different from each other; a polarization state detection circuit including plural dummy cells, each of which has a ferroelectric capacitor and an access transistor, for checking a polarization state of each of the ferroelectric capacitors in response to the dumping voltages corresponding to the dummy cells, respectively, the polarization state detection circuit for further outputting pass/fail signals corresponding to the dummy cells, respectively, as a checking result, each of the pass/fail signals indicating whether a voltage corresponding to a polarization state of the ferroelectric capacitor is higher or lower than a dumping voltage; a decoder circuit for decoding the outputted pass/fail signals from the polarization state detection circuit to generate selection signals; and a reference voltage generator for internally generating distribution voltages corresponding to the selection signals, respectively, and outputting one of the distribution voltages as the reference voltage in response to the selection signals, wherein voltage levels of the distribution voltages are different from each other.