Patent ID: 8831157
Filing Date: 2014-09-09
Classification: H03L,H04L

Abstract:
1. A clock and data recovery circuit comprising: a sampler circuit arranged to receive a data signal and a sampling clock and generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal; a de-multiplexer circuit arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal; a voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal comprising preliminary up and down signals; a digital filter circuit arranged to filter the decimated feedback signal from the voting circuit and to output a filtered feedback signal comprising up and down signals which are filtered versions of the preliminary up and down signals; a finite state machine circuit arranged to receive the filtered feedback signal and generate an interpolator control signal; and a phase interpolator circuit arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal.