Patent ID: 7707390
Filing Date: 2010-04-27
Classification: G06F

Abstract:
1. A multi-threaded in-order superscalar processor having an instruction pipeline comprising: a plurality of fetched instruction queues in to which instructions from respective program threads are placed; an issue stage responsive to instructions to select one or more of said instructions to be issued in parallel to respective execution units; and dependency hint circuitry disposed outside and upstream of said issue stage in said instruction pipeline, said dependency hint circuitry being coupled to at least one of said plurality of fetched instruction queues and responsive to at least two instructions adjacent in program order and stored therein to selectively associate hint data with a marked instruction, said hint data indicating that said marked instruction has no data dependency upon any other instruction of said at least two instructions; wherein said hint data for said marked instruction indicates that said marked instruction should not be issued in parallel with any other instructions of said at least two instructions unless said hint data indicates no data dependency thereupon.