Patent ID: 6014329
Filing Date: 2000-01-11
Classification: G11C,H01L

Abstract:
A flash-erasable semiconductor memory device, comprising:a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region; and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film;addressing means supplied with address data for selecting a memory cell transistor in said memory cell array;writing means for writing information into said selected memory cell transistor;reading means for reading information from said selected memory cell transistor;erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously, said erasing means erasing information by removing electric charges from said floating gate electrodes of said memory cell transistors by causing to flow a tunneling current through said gate insulation film, said erasing means comprising word line selection means for selecting a word line; anderase control means for controlling said word line selection means supplying a gate voltage to said control electrode with a polarity and a magnitude sufficient for causing to flow said tunneling current of said electric charges through said gate insulation film, wherein said memory cell array comprises a main memory cell array and a redundant memory cell array each including a plurality of said memory cell transistors, said main memory cell array including a plurality of main word lines in correspondence to said plurality of memory cell transistors arranged into a plurality of rows, said redundant memory cell array including at least one redundant word line in correspondence to said plurality of memory cell transistors arranged into one or more rows; and wherein said word line selection means comprises row addressing means supplied with row address data that forms a part of said address data for selecting a word line in said main memory means; discrimination means supplied with said row address data for discriminating whether said row address data selects a defective word line in said main memory cell array; and redundant addressing means supplied with row address data and an output of said discrimination means for selecting a redundant word line in response to said output of said discrimination means.