Patent ID: 6738894
Filing Date: 2004-05-18
Classification: G06F

Abstract:
A single-chip data processor comprising:a central processing unit; an electrically erasable and programmable memory including: a first area storing a first vector address, and a second area storing an operation program which the central processing unit executes in a normal operation mode; a memory having an area storing a second vector address; and an interrupt controller providing an interrupt request to the central processing unit in response to an interrupt event, wherein the operation program in the second area is capable of erasing or programming in an erase or programming mode, and wherein, if the interrupt controller provides an interrupt request to the central processing unit during the normal operation mode, the first vector address stored in the first area is used to respond to the interrupt request, and wherein, if the electrically erasable and programmable memory is in an erase or programming mode, and if the interrupt controller provides the interrupt request to the central processing unit, then the second vector address in the area of the memory is used to respond to the interrupt request.