Patent ID: 6174775
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method of fabricating a polycide, dual gate structure, on a semiconductor substrate, comprising the steps of:providing an isolation region, in a first region of said semiconductor substrate;providing a P well region, in a second region of said semiconductor substrate;providing an N well region, in a third region of said semiconductor substrate;growing a gate insulator layer, on regions of said semiconductor substrate, not occupied by said isolation region;depositing a first undoped polysilicon layer;converting said first undoped polysilicon layer to a dual doped polysilicon layer, with said dual doped polysilicon layer comprised of an N type doped, polysilicon region, located on a first portion of said gate insulator layer that overlays said P well region, and comprised of a P type doped, polysilicon region, located on second portion of said gate insulator layer that overlays said N well region;depositing a second undoped polysilicon layer, on and in contact with said dual doped polysilicon layer;depositing a metal silicide layer, on said second undoped polysilicon layer;depositing a capping insulator layer on said metal silicide layer; andpatterning of said capping insulator layer, of said metal silicide layer, of said second undoped polysilicon layer, and of said dual doped polysilicon layer, to create a polycide, dual gate structure, with a first portion of said polycide, dual gate structure, comprised with said N type doped, polysilicon region, overlying said P well region, and with a second portion of said polycide, dual gate structure comprised with said P type doped, polysilicon region, overlying said N well region.