Patent ID: 6362989
Filing Date: 2002-03-26
Classification: G06F,G11C

Abstract:
In a semiconductor memory device having word lines, rows of memory cells coupled to respective word lines, sense lines, sense amplifiers coupled to said sense lines, cache cells coupled to said sense lines, and a data bus, a method of executing a memory access cycle, comprising the steps of:receiving a row address designating a row of memory cells; determining if data of said row of memory cells are currently present in said sense amplifiers and said cache cells; transferring said data from said cache cells to said sense lines, if said data are currently present in said cache cells but not in said sense amplifiers, and amplifying the data thus transferred; transferring said data from said memory cells to said sense lines, if said data are currently present in neither said cache cells nor said sense amplifiers, and amplifying the data thus transferred; receiving at least one column address and transferring data between corresponding sense lines and said data bus, thereby completing said memory cycle; and leaving said sense amplifiers enabled when said memory cycle ends, so that said sense amplifiers continue to hold amplified data of the row of memory cells designated by said row address.