Patent ID: 6903581
Filing Date: 2005-06-07
Classification: H03K

Abstract:
1. A method comprising: utilizing a first of a plurality of circuit configurations with an output buffer, the first circuit configuration having a thick gate P-channel MOS (PMOS) transistor as a pull-up transistor to a first voltage supply voltage level and an N-channel MOS (NMOS) pull-down transistor to a reference voltage; utilizing a second of the plurality of circuit configurations with the output buffer, the second circuit configuration having a thick gate N-channel MOS (NMOS) transistor as a pull-up transistor to a second voltage supply voltage level and an NMOS pull-down transistor to the reference voltage, the second voltage supply voltage level being different than the first voltage supply voltage level; and selectively operating the output buffer with the plurality of circuit configurations, including at least one of the first and the second circuit configurations, to interoperate through an input/output pad responsive to the output buffer with external integrated circuit chips having separate threshold voltage levels.