Patent ID: 7268585
Filing Date: 2007-09-11
Classification: H03K

Abstract:
1. A signal routing architecture for a programmable logic device comprising: a plurality of configurable logic blocks; a plurality of high fan-out routing lines; a plurality of local routing lines programmably coupleable to ones of said configurable logic blocks and programmably coupleable to ones of said high fan-out routing lines; an aggregation interconnect programmably coupleable to ones of said local routing lines and ones of said high fan-out routing lines; wherein: the aggregation interconnect is configurable to receive a signal from one of the local routing lines and route the signal to at least two of the high fan-out routing lines; the aggregation interconnect is configurable to electrically connect at least one of the high fan-out routing lines with at least one other of the high fan-out routing lines; wherein a path length from the aggregation interconnect to each of the at least two high fan-out routing lines is the same.