Patent ID: 6035182
Filing Date: 2000-03-07
Classification: H03K,H03L

Abstract:
A single counter dual modulus frequency divider apparatus comprising:a programmable divider configured to receive an input signal and a modulus control, the modulus control to set a programmable divide value of the programmable divider, the programmable divider to divide the input signal by the programmable divide value to produce a divided signal;a programmable counter configured to receive the divided signal at a first input and a count control at a second input, the count control to set a count value of the programmable counter, the programmable counter to count periods of the divided signal and produce a counted signal; anda re-timer and clock generation circuit coupled to the programmable divider and the programmable counter to process the counted signal and produce the modulus control and an output divided signal, the re-timer and clock generation circuit including:a latch to process the counted signal and produce a synchronized load signal for application to a third input of the programmable counter,a first AND gate for receiving the synchronized load signal and the divided signal and producing a load clock signal for application to a fourth input of the programmable counter,a toggle flip-flop to receive the load clock signal and produce the output divided signal, anda second AND gate to receive an inverted output divided signal and the synchronized load signal to produce the modulus control.