Patent ID: 6653881
Filing Date: 2003-11-25
Classification: H03K

Abstract:
A programmable clock generator that generates two non-overlapping clock signals, comprising:a first logic gate that generates a first non-overlapping clock signal; a second logic gate that generates a second non-overlapping clock signal; a first delay element that receives said first non-overlapping clock signal and generates a first output signal that is received by said second logic gate; and a second delay element that receives said second non-overlapping clock signal and generates a second output signal that is received by said first logic gate; wherein said first delay element comprises a first plurality of delay lines, wherein each of said first plurality of delay lines comprises a different number of first delay elements, a first demultiplexer that receives a first control signal and selectively transmits said first non-overlapping clock signal over one of said first plurality of delay lines based on said first control signal, and a first multiplexer that receives a second control signal and selects one of said first plurality of delay lines for providing said first output signal based on said second control signal.