Patent ID: 6765186
Filing Date: 2004-07-20
Classification: G11C,H01L,H04N

Abstract:
An imager comprising:a plurality of imager cells each comprising a photoreceptor establishing a photoreceptor potential well, a transfer gate establishing a readout potential well, and a sense node; and a multi-mode controller coupled to the plurality of imager cells, the multi-mode controller comprising circuitry implementing at least one of a high-light mode of operation providing charge accumulation in the photoreceptor potential well and the readout potential well, and a Snap mode of operation simultaneously activating a plurality of the transfer gates to initiate readout of a plurality of the imager cells; the multi-mode controller further comprises circuitry for implementing a low-light mode providing charge accumulation in the photoreceptor potential well that is constrained by an integration potential well established by the transfer gate during an integration period.