Patent ID: 6157988
Filing Date: 2000-12-05
Classification: G06F

Abstract:
In a pipelined processor, a method for reducing pipeline stalls caused by branching, said method comprising the steps of:prefetching instructions into a first stage of said pipeline;propagating instructions into one or more subsequent stages of said pipeline;computing a conditional outcome in one of said subsequent stages;concurrently with processing at a specified stage in said pipeline, analyzing one or more instruction op-codes to determine whether a cacheable branch instruction is present, and, if said branch instruction is present, sending a tag relating to said branch instruction to a branch cache;determining, in response to said conditional outcome, whether a branch is to be taken, and, if said branch is to be taken, sending a branch taken signal to said branch cache;if the conditional outcome indicates a branch is not to be taken, continuing to fetch instructions into said pipeline and to execute said instructions; andon receipt of said current branch tag, said branch cache performing the steps of:examining a collection of stored branch tags to find a stored branch tag which matches said current branch tag;if said current branch tag is not found in said collection of stored branch tags and said branch is to be taken:signaling a cache miss;causing said pipeline to fill one or more designated pipeline stages starting at a branch target address, said designated pipeline stages being pipeline stages that stall according to said branch, and causing said branch cache to store said current branch tag and one or more instructions contained within said designated pipeline stages; andif said branch taken signal is received and said current branch tag is found in said collection of stored branch tags:signaling a cache hit;sending a branch target address to the prefetch unit so that instruction fetching can proceed from said branch target address; andproviding data stored in said cache to one or more of said designated pipeline stages so that execution can continue without delay irrespective of said conditional outcome.