Patent ID: 6628292
Filing Date: 2003-09-30
Classification: G09G

Abstract:
Circuitry for storing pixel commands to facilitate reordering of the pixel commands, each pixel command comprising pixel data and pixel row/bank and column addresses to facilitate reordering of the pixel commands, comprising:a bus for receiving a pixel commands from a pipeline, each pixel command accompanied by pixel data, a pixel row/bank address and a pixel column address; a row/bank address storage array for storing each received pixel command's row/bank address in a row/bank address entry when the received pixel command's row/bank address is not currently stored in the row/bank address storage array; a multi-line column address storage array for storing in an available line of the column address storage array the MSBs of the pixel command's column addresses when such MSBs are not currently stored in a line of the column address storage array that is currently associated with the row/bank address entry matching the command's row/bank address; a line-in-use bit array having columns associated with columns of the row/bank address storage array and rows associated with lines of the column address storage array, wherein cells of the line-in-use bit array associate the row/bank address entry matching the command's row/bank address with the line of the column address storage array in which the pixel's column address MSBs are stored when such an association has not been made for a previously-received command; and a multi-line pixel data storage array, having lines of pixel entry locations which are associated with the lines of the column address storage array, for storing the pixel command's pixel data within a line of pixel entries in the pixel data storage array which is associated with the line of the column address storage array in which the command's column address MSBs are stored.