Patent ID: 8477547
Filing Date: 2013-07-02
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: first and second memory groups that each comprise memory cells and redundancy memory cells; first main page buffers assigned to the first memory group and second main page buffers assigned to the second memory group, wherein the first and second main page buffers are configured to each store data for a program operation or a read operation of the memory cells of the respective memory group; at least one first redundancy page buffer assigned to the first memory group and at least one second redundancy page buffer assigned to the second memory group, wherein the at least one redundancy page buffers of the first and second memory groups are each configured to store data for a defective column of the respective memory group in the at least one redundancy memory cell of the respective memory group; and a data transfer circuit configured to transfer data from a first main page buffer of the first main page buffers that corresponds to the defective column of the first memory group to the at least one second redundancy page buffer before the program operation and transfer data of the at least one second redundancy page buffer to the first main page buffer corresponding to the defective column of the first memory group after the read operation.