Patent ID: 9064591
Filing Date: 2015-06-23
Classification: G11C

Abstract:
1. A semiconductor device including an OTP memory cell, comprising: a first switching unit for transferring a first bias voltage in response to a bias enable signal; a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit; and a second switching unit for coupling a second terminal of the first MOS transistor to a first bit line in response to a second gate signal, wherein, in a programming mode, the first bias voltage is supplied with a predetermined level, the first gate of the first MOS transistor is supplied with a high level voltage having a higher level than the first bias voltage to break down an insulating layer of the first gate, and the second gate signal and the bias enable signal have a turn-on voltage to turn on the first and second switching unit respectively.