Patent ID: 6069825
Filing Date: 2000-05-30
Classification: G11C

Abstract:
An apparatus integrated on a chip for selectively charging conductive lines of a programmable non-volatile memory array, comprising:a) a conductive line decoder for selecting at least one of said conductive lines for programming;b) a high voltage generator for generating a high voltage;c) an oscillator for generating voltage pulses;d) capacitive circuitry connected to a charge transfer node corresponding to said at least one of said conductive lines, for capacitively coupling said voltage pulses to said charge transfer node;e) oscillator output control circuitry connected to said oscillator and said capacitive circuitry, and responsive to said conductive line decoder, for transmitting said voltage pulses to said capacitive circuitry only if said at least one of said conductive lines is selected for programming; andf) selective charge transfer circuitry connecting said high-voltage generator and said at least one of said conductive lines, and coupled to said charge transfer node, for selectively transferring charge increments from said high-voltage generator to said at least one of said conductive lines in response to said voltage pulses received at said charge transfer node.