Patent ID: 9112012
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A method for fabricating a transistor comprising: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a silicon nitride layer directly on the gate dielectric layer, wherein the silicon nitride layer includes a first surface in contact with the gate dielectric layer and a second surface opposite to the first surface, the second surface including silicon atoms having a concentration higher than the first surface, wherein the silicon nitride layer includes a double layer structure including a nitrogen-rich layer on the gate dielectric layer and a silicon-rich layer on the nitrogen-rich layer, such that the double layer structure includes a stepped band gap provided by the silicon-rich layer having a band gap and the nitrogen-rich layer having a different band gap, wherein the nitrogen-rich layer on the gate dielectric layer is formed by controlling a consistent concentration of silicon atoms through the nitrogen-rich layer, and wherein an atom number ratio of nitrogen atoms to silicon atoms in the nitrogen-rich layer is greater than about 1.2, and the nitrogen-rich layer has a thickness ranging from about 1 nm to about 4 nm; forming a gate electrode layer directly on the silicon nitride layer; forming a sidewall spacer on the semiconductor substrate and along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer; and forming a source region and a drain region in the semiconductor substrate on sides of the gate electrode layer and the sidewall spacer.