Patent ID: 8344385
Filing Date: 2013-01-01
Classification: H01L

Abstract:
1. A vertical-type non-volatile memory device, comprising: an insulation layer pattern on a substrate, the insulation layer pattern having a linear shape; single-crystalline semiconductor patterns on the substrate directly on a sidewall of the insulation layer pattern, the single-crystalline semiconductor patterns comprising a pillar shape extending in a vertical direction that is oriented perpendicular relative to a major surface of the substrate; a tunnel oxide layer on the single-crystalline semiconductor pattern; a lower electrode layer pattern directly on the tunnel oxide layer and on the substrate; a plurality of insulation interlayer patterns on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a distance along the single-crystalline semiconductor pattern; a charge-trapping layer and a blocking dielectric layer on the tunnel oxide layer between the insulation interlayer patterns; a plurality of control gate patterns on the blocking dielectric layer between the insulation interlayer patterns; and an upper electrode layer pattern on the tunnel oxide layer and on an uppermost portion of the insulation interlayer pattern.