Patent ID: 6121810
Filing Date: 2000-09-19
Classification: G11B

Abstract:
A method for calibrating a delay line of a read/write channel integrated delay line calibration apparatus in a direct access storage device (DASD) comprising the steps of:configuring the delay line as a ring oscillator for calibration; the delay line including a plurality of delay blocks;comparing a delay line ring frequency to a reference frequency, andadjusting a delay of the delay line until said delay line ring frequency and said reference frequency are equal; said delay adjusting step including the steps of generating an N-bit calibrate value, and applying said generated N-bit calibrate value to a delay adjust digital-to-analog converter (DAC) coupled to the delay line for calibration adjustment of the delay line and controlling a delay of each said delay block within the delay line by said delay adjust digital-to-analog converter (DAC).