Patent ID: 6128679
Filing Date: 2000-10-03
Classification: G06F

Abstract:
A computer which is comprised of:an instruction processor, coupled to a memory and an I/O port, which directly executes a first set of object code instructions;a native operating system for all program in said memory, which is a compilation of instructions in said first set;a foreign application program in said memory, which is a compilation of instructions in a second set that differs from said first set, including a TRANSMIT I/O instruction and a RECEIVE I/O instruction;an emulator program, in said memory, which is a compilation of instructions in said first set that interprets said second set of instructions; characterized in that said emulator program includesa Send thread which calls into said native operating system, to send data from said foreign application program to said I/O port in response to said transmit I/O instruction;a Get thread which calls into said native operating system to receive data for said foreign application program from said I/O port in response to said receive I/O instruction; and,a single Result thread which a) processes one result descriptor that is received from said native operating system when data is sent for said Send thread, and processes another result descriptor that is received from said native operating system when data is received for said Get thread, and b) is completely blocked from running at any time on said instruction processor between the processing of said result descriptors.