Patent ID: 6124177
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method for fabricating improved MOSFET devices on a semiconductor substrate having device areas comprising the steps of:depositing a first insulating layer and a second insulating layer and patterning to form openings for FET polysilicon gate electrodes over said device areas;depositing and etching back a third insulating layer to form arc-shaped first sidewall spacers in said openings;implanting an anti-punchthrough dopant in said substrate between said first sidewall spacers; forming a gate oxide on said device areas in said openings;depositing a polysilicon layer and polishing back to form polysilicon gate electrodes in said openings aligned over said gate oxide;isotropically etching said second insulating layer, said first insulating layer, and said arc-shaped first sidewall spacers, leaving free-standing said polysilicon gate electrodes having a shape determined by said arc-shaped sidewall spacers, whereby said polysilicon gate electrodes gradually increase in width as a function of increasing height from said gate oxide;ion implanting a dopant through said polysilicon gate electrodes to form graded, lightly doped source/drain areas adjacent to said gate oxide and concurrently doping said gate electrodes;depositing and anisotropically etching back a fourth insulating layer to form second sidewall spacers and air spacers adjacent to said gate electrodes;ion implanting source/drain con tact areas adjacent to said second sidewall spacers and concurrently doping said polysilicon gate electrodes;depositing and annealing a metal layer to form a metal silicide on said polysilicon gate electrodes and on said source/drain contact areas and removing said metal that is unreacted to complete said MOSFET devices.