Patent ID: 6165807
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for forming and measuring silicide test devices to monitor and evaluate the quality of a semiconductor junction after the formation of a silicide layer over said junction comprising:(a) providing a silicon wafer having a region of a first conductivity type;(b) forming a field oxide isolation on said wafer, said field oxide isolation having at least two openings and wherein a first opening of said at least two openings is rectangular with straight edges and a second opening of said at least two openings is rectangular with serpentine edges on at least one side;(c) forming a rectangular polysilicon gate stack band over said field oxide isolation concentric with said first opening;(d) forming sidewall spacers adjacent to said polysilicon gate stack band;(e) implanting dopant impurity ions of a second conductivity type into said wafer, thereby forming semiconductor junctions in said at least two openings;(f) depositing a silicon oxide layer on said wafer;(g) patterning said silicon oxide layer to form oxide islands within said second opening and a rectangular band in said first opening whereby said rectangular band overlaps said straight edges such that a first area of silicon is exposed within said first opening, and a second area of silicon is exposed in said second opening;(h) depositing a refractory metal layer over said wafer;(i) depositing a protective layer on said refractory metal layer;(j) annealing said wafer, thereby forming silicide pads within each of said openings;(k) etching said wafer with an aqueous etchant whereupon said protective layer and residual unreacted refractory metal are removed and a first test device is formed in said first opening and a second test device is formed in said second opening;(l) Forming a contact to said region of said first conductivity type;(m) applying test probes to said contact and to said silicide pads;(n) measuring leakage currents of said junctions; and(o) performing EMMI tests on said first and said second test devices with said junctions under reverse bias.