Patent ID: 9219067
Filing Date: 2015-12-22
Classification: G11C,H01L

Abstract:
1. An array of memory cells on an integrated circuit device, comprising: a plurality of memory cells arranged in at least one column, wherein: each of said memory cells comprises a plurality of transistors forming two complementary memory nodes, one of said complementary memory nodes storing a value and another of said complementary memory nodes storing a complement of said value; each respective one of said complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, said respective pair of pull-up or pull-down transistors being connected in series and having a respective shared node therebetween; for a particular one of said memory cells, one of said respective shared nodes associated with one of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of said memory cells, and another of said respective shared nodes associated with another of said complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a third one of said memory cells.