Patent ID: 6316301
Filing Date: 2001-11-13
Classification: G06F,H01L

Abstract:
A method of sizing each of a plurality of PMOS pull-up transistors relative to the size of each of a plurality of NMOS pull-down transistors in a logic circuit, wherein respective pairs of the plurality of PMOS pull-up and NMOS pull-down transistors may receive corresponding ones of a plurality of input signals, the method comprising:selecting an NMOS transistor width;determining an effective NMOS transistor width from the NMOS transistor width;multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying capacity ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors;dividing a result of the multiplying step by the number of parallel-connected transistors that simultaneously turn on to generate a PMOS transistor width; andsizing each of the PMOS pull-up transistors to the PMOS transistor width.