Patent ID: 6766440
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A digital system comprising a central processing unit (CPU) having an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles, the CPU comprising:a first functional unit interconnected with a first set of registers, the first functional unit operable to exchange operand data with the first set of registers; a second functional unit interconnected with a second set of registers, the second functional unit operable to exchange operand data with the second set of registers, wherein a write to said first and second sets of registers is performed over multiple pipeline cycles; first cross-path circuitry connected to an input of the second functional unit and to a port on the first set of registers, the cross-path circuitry being operable to access the first set of registers for providing operand data from the first set of registers to the second functional unit; wherein the cross-path circuitry is operable to stall both the first functional unit and the second functional unit in response to accessing a selected register in the first register set during a given CPU cycle if the selected register is being updated by the first functional unit; wherein the first cross-path circuitry comprises a first stall register connected to receive operand data from the first functional unit in parallel with the first set of registers; and wherein to minimize CPU cycle time length, the first cross-path circuitry is operable to provide a first operand from the first stall register during a given CPU cycle if the first operand was being stored into the selected register of the first register set during the mediately prior CPU cycle, such that the instruction execution pipeline is stalled for one CPU cycle when the first operand is provided from the first stall register.