Patent ID: 6681319
Filing Date: 2004-01-20
Classification: G06F

Abstract:
A digital system comprising a processing engine, wherein the processing engine comprises:an instruction buffer operable to buffer single and compound instructions pending execution thereof; a decode mechanism configured, to decode instructions from the instruction buffer, the decode mechanism being responsive to a predetermined tag in an instruction, the predetermined tag being representative of the instruction being a compound instruction formed from separate programmed memory instructions, to decode at least first data flow control for a first programmed instruction and at least second data flow control for a second programmed instruction; and wherein the compound instruction is a compound memory access instruction formed by combining separate first and second programmed memory access instructions such that a compound address field of the compound instruction is formed at the same bit positions as an address field for a hard programmed dual memory instruction and wherein the compound address field is decoded into first and second memory addresses for first and second memory address instructions respectively.