Patent ID: 7899992
Filing Date: 2011-03-01
Classification: G06F

Abstract:
1. A cache circuit comprising: a cache memory configured to hold at least either data read/written by an information processor from/into main memory connected to a bus or an instruction code read from the main memory; a cache control circuit configured to read data or an instruction code from the cache memory and output the read data or instruction code to the information processor in response to a read request for the data or the instruction code from the information processor if a cache hit is determined, read data or an instruction code from the main memory and allow the read data or instruction code to be held in the cache memory as well as output the read data or instruction code to the information processor if a cache miss is determined, and write data in the cache memory in response to a write request for the data from the information processor; and a cache entry invalidating circuit configured to invalidate an entry of data or an instruction code held in the cache memory according to a number of cache hits, wherein the cache entry invalidating circuit invalidates data or an instruction code in the cache memory when the number of cache hits is greater than a predetermined number.