Patent ID: 8589734
Filing Date: 2013-11-19
Classification: G06F

Abstract:
1. A computer-implemented method for checking a processor, the method comprising: obtaining a test program of the processor, the test program comprising a plurality of transactions, the plurality of transactions comprising instructions for the processor, wherein at least one transaction of the plurality of transactions is a multiple memory accesses transaction configured, when executed, to perform multiple memory accesses using two or more instructions, wherein at least one of the instructions of the transactions is a read instruction, the read instruction associated with alternative values to be read by the read instruction, and with identifications of transactions of the plurality of transactions that are operable to set each of the alternative values to be read by the read instruction; simulating an execution by the processor of the test program, wherein said simulating is performed by a computer having a storage device; determining a value read by the read instruction during said simulating; updating a transaction order graph retained in the storage device, wherein each node of the transaction order graph is associated with operating one of the plurality of transactions, and wherein at least one of the transaction order graph is associated with operating the multiple memory accesses transaction, said updating based upon at least: a first transaction executing the read instruction; and a second transaction associated in the test program with setting the value read by the read instruction; and in response to identification of a cycle in the transaction order graph, providing an error indication.