Patent ID: 6750505
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A memory device comprising:a substrate; and a plurality of memory cells in said substrate arranged in rows and columns to define a matrix of memory cells, each memory cell comprising a floating gate defined by a stacked structure comprising a first dielectric layer, and a first conducting layer isolated from said substrate by the first dielectric layer, at least one trench in said substrate adjacent said floating gate, a second dielectric layer in said at least one trench, and conductive extensions contacting said first conducting layer of said floating gate and extending laterally outwardly therefrom over adjacent portions of said second dielectric layer, said conductive extensions having upper surface portions being substantially coplanar with adjacent upper surface portions of said first conducting layer of said floating gate, said conductive extensions having a thickness substantially equal to a thickness of said first conducting layer of said floating gate.