Patent ID: 6803284
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method for manufacturing an integrated circuit on a substrate, including nonvolatile memory in an array portion of the substrate and other circuitry in a non-array portion of the substrate, comprising:forming gate dielectric layers in the array portion and in the non-array portion of the substrate; covering the gate dielectric layers with a first layer of polysilicon in the array portion and in the non-array portion of the substrate; covering the first layer of polysilicon with a layer of silicon nitride in the array portion and in the non-array portion of the substrate; patterning lines in a wordline direction in the array portion, and etching said layer of silicon nitride and said first layer of polysilicon to form line structures in the array portion; patterning lines orthogonal to the wordline direction in the array portion over said line structures, and etching said line structures to form gate electrode structures, the gate electrode structures including remaining portions of said first polysilicon layer and said silicon nitride layer; implanting dopants into the substrate through uncovered regions of the gate dielectric layer in the array portion, between the lines orthogonal to the wordline direction; removing said lines orthogonal to the wordline direction; depositing a dielectric material between the gate electrode structures to fill gaps among the gate structures; planarizing the array portion and the non-array portion to a level exposing said silicon nitride layer and said dielectric material in the gaps among the gate electrode structures; removing said layer of silicon nitride from said non-array portion and from said gate structures, leaving the remaining portions of said first layer of polysilicon and said dielectric material filling the gaps among the gate electrode structures; covering the remaining portions of said first layer of polysilicon and said dielectric material filling the gaps among the gate electrode structures with a second layer of polysilicon material; patterning wordlines in the array portion over said gate electrode structures, and transistor gate structures in said non-array portion, and etching the remaining portions of said first layer of polysilicon and said second layer of polysilicon according to the patterning to form wordlines in the array portion and transistor gate structures in the non-array portion; implanting dopants to form source and drain regions in the non-array portion; forming self aligned silicide in source and drain regions in the non-array portion; applying a dielectric layer over the array portion and the non-array portion; and applying patterned metallization over the dielectric layer.