Patent ID: 7701767
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of memory cells arranged in an array; a plurality of bit-lines, each bit-line forming a column in the array; a plurality of control-gate lines, each control-gate line forming a control-gate sub-row in the array; a plurality of erase gate lines, each erase gate line forming an erase gate sub-row in the array; a plurality of common-source lines, each common-source line forming a common-source sub-row in the array; a plurality of word-lines, each word-line forming a word-line row in the array; a plurality of straps, each strap electrically coupled to at least one of the control-gate line, the erase gate line, the common-source line and the word-line, wherein each strap is electrically coupled through a strap-contact in a strap-contact cell to each of the control-gate line, the erase gate line, the common-source line, and the word-line; a first memory cell electrically connected to a first bit-line, a first control-gate line, a shared erase gate line, a shared common-source line, and a first word-line; a second memory cell electrically connected to the first bit-line, a second control-gate line, the shared erase gate line, the shared common-source line and a second word-line, wherein the first memory cell and the second memory cell form a unit set; a plurality of strap-contact cells, wherein each strap-contact cell has substantially a same length as the unit set and has a width from about one to three times a width of the unit set; and a plurality of strap-contact corridors, each strap-contact corridor forming a sub-column in the array, wherein each strap-contact corridor comprises at least one strap-contact cell, and wherein a width of each strap-contact corridor is substantially the width of each strap-contact cell.