Patent ID: 7461305
Filing Date: 2008-12-02
Classification: G01R

Abstract:
1. A circuit for determining a degree of buffering required along a data bus to avoid race conditions, comprising: a plurality of memory elements sorted in sequence, wherein a first memory element of the plurality of memory elements receives a data stream, the input for each additional memory element other than the first memory element is the output from the first first memory element; delay elements defined to add delays to the inputs of the additional memory elements starting with a third memory element, wherein a memory element of order n receives the output from the first memory element after passing through (n−2) delay elements, wherein all of the delay elements introduce a same amount of time delay; and a plurality of comparators, wherein each comparator is associated with one of the additional memory elements, wherein each comparator compares the data stream and an output of the associated additional memory element, wherein each comparator identifies whether a race condition is present between the first memory element and the corresponding additional memory element.