Patent ID: 7590961
Filing Date: 2009-09-15
Classification: G06F,H03K

Abstract:
1. A method of designing an integrated circuit comprising digital circuitry for signal skew adjustment comprising the steps of: determining a skew of a signal in the digital circuitry of the integrated circuit having at least one digital logic cell from a cell library; and incorporating at least one skew adjusting cell from the cell library into the digital circuitry of the integrated circuit, wherein the at least one skew adjusting cell is configured to adjust the skew of the signal in the integrated circuit to a desired amount; wherein the step of incorporating at least one skew adjusting cell from the cell library comprises the step of selecting the at least one skew adjusting cell from a group of skew adjusting cells in the cell library; wherein each of the skew adjusting cells of the group performs a substantially similar combinatorial logic function to that of the at least one digital logic cell of the cell library; wherein the skew adjusting cells of the group are designed at a transistor level to provide varying amounts of skew, such that the group of skew adjusting cells covers a range of designed-in skews; wherein the at least one skew adjusting cell incorporated from the cell library has a skew that differs from that of the at least one digital logic cell of the cell library; wherein the at least one skew adjusting cell comprises at least one transistor with a smaller width/length ratio than at least one corresponding transistor of the at least one digital logic cell; and wherein at least one of the steps is performed by a computer-assisted design instrument comprising at least one processor coupled to a memory.