Patent ID: 7915158
Filing Date: 2011-03-29
Classification: H01L

Abstract:
1. A method for forming an electro-static discharge protection device on an integrated circuit, comprising: providing a wafer including a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer, wherein the more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer, and wherein at least one of the misaligned vias forms a narrow gap with another misaligned via; forming a cavity trench through the second dielectric layer, wherein the cavity trench is formed in the second dielectric layer between the narrow gap that separates the misaligned vias; depositing a pinching layer over an opening in the second dielectric layer created by the formation of the cavity trench, wherein the pinching layer pinches off the opening creating a high aspect ratio; and depositing a third dielectric layer over the second dielectric layer, wherein the third dielectric layer hermetically seals the pinching layer and the cavity trench to provide electro-static discharge protection.