Patent ID: 6122707
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A system comprising:a plurality of content addressable memory (CAM) arrays, each CAM array comprising encoding means and an array of core cells, of w words.times.b bits, associated with the encoding means, each CAM array being able to provide, through its respective encoding means, a hit signal resulting from a search operation in response to a clock signal; anda plurality of logic circuits, each logic circuit being associated with the respective CAM array to receive the hit signal therefrom, each logic circuit comprising timing signal generation means for generating a self-timed signal in response to the clock signal, each logic circuit comprising logic means for logically combining a propagation-in hit signal provided from an upstream logic circuit and the hit signal provided from the associated CAM array, so that a propagation-out hit signal is provided to a downstream logic circuit, in response to the self-timed signal.