Patent ID: 7165124
Filing Date: 2007-01-16
Classification: G06F

Abstract:
1. A data transfer control system for data transfer through a bus, comprising: a command processing section which receives a command packet transferred through a first bus, issues a command indicated by the command packet to a device connected to a second bus, and orders start of a direct memory access (DMA) transfer through the second bus; a command comparison section which compares contents of a first command packet transferred through the first bus before a bus reset with contents of a second command packet transferred through the first bus after the bus reset, when the bus reset that clears node topology information has occurred during the processing of the first command packet; and a command abort section which waits for completion of a DMA transfer which has been started based on the first command packet, and aborts the command which has been issued to the device connected to the second bus based on the first command packet after the completion of a DMA transfer of the first command packet, when the contents of the first command packet are determined to be different from the contents of the second command packet.