Patent ID: 6563154
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A capacitor structure, integrated with a polysilicon gate in a silicon integrated circuit, comprising:a phosphorus-doped polysilicon gate that consists of a first layer of polysilicon, that was formed at a temperature between about 600 and 650Â° C., on which lies a second layer of phosphorus-doped polysilicon that was formed at a temperature between about 520 and 580Â° C., the second polysilicon layer having a thickness between about 2,000 and 3,800 Angstroms; said first and second polysilicon layers having been formed at the same deposition rate; a dielectric layer on the second polysilicon layer, wherein the second polysilicon layer having a roughness value that is between about 60 and 80 Angstroms at an interface to said dielectric layer; and a conductive layer on said dielectric layer.