Patent ID: 8815675
Filing Date: 2014-08-26
Classification: H01L

Abstract:
1. A manufacturing method of a nonvolatile semiconductor memory comprising: (a) laminating a second insulating film, a gate film and a hard mask film in this order which cover a first gate electrode of a first memory cell transistor formed over a first region of a semiconductor substrate through a first insulating layer and a third gate electrode of a second memory cell transistor formed over a second region of said semiconductor substrate through said first insulating layer; (b) forming a first hard mask layer which covers a bottom portion and a side surface of a concave portion formed using said gate film between said first gate electrode and said third gate electrode by etching said hard mask film; and (c) forming a second gate electrode of said first memory cell transistor over said first region, a fourth gate electrode of said second memory cell transistor over said second region, and a connection layer which connects said second gate electrode and said fourth gate electrode under said first hard mask layer by etching said gate film; and (d) exposing an upper portion of said connection layer by etching back said first hard mask layer covering a bottom portion of said concave portion to remain said first hard mask layer such that said first hard mask layer covers side surfaces of said concave portion.