Patent ID: 6746898
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A chip packaging method comprising:providing a substrate having a heat sink and a film layer, the film layer positioned on a surface of the heat sink; forming a plurality of openings penetrating through the film layer and exposing the surface of the heat sink; providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface; mounting the dies onto the surface of the heat sink exposed by the openings of the film layer, the backside of the dies facing the surface of the heat sink; allocating a first dielectric layer over the film layer and the active surface of the dies, the first dielectric layer patterned to form a plurality of first thru-holes that penetrate through the first dielectric layer and expose the metal pads of the dies; and allocating a first patterned wiring layer over the first dielectric layer, the first patterned wiring layer electrically connected to the metal pads of the dies through the first thru-holes.