Patent ID: 8552565
Filing Date: 2013-10-08
Classification: H01L

Abstract:
1. A chip package, comprising: a substrate having an upper surface and a lower surface; a plurality of conducting pads in a stacked structure, comprising at least an upper conducting pad above a lower conducting pad, wherein the upper conducting pad is located under the lower surface of the substrate, wherein the upper conducting pad of the conducting pads has at least an opening or a trench exposing the lower conducting pad of the conducting pads; a dielectric layer located between adjacent conducting pads; a hole extending from the upper surface towards the lower surface of the substrate, wherein a sidewall or a bottom of the hole exposes a portion of the conducting pads, and an upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface, wherein a thickness of at least one of the conducting pads near the hole increases along a direction away from the hole; and a conducting layer located in the hole and electrically contacting at least one of the conducting pads.