Patent ID: 6943713
Filing Date: 2005-09-13
Classification: G08C

Abstract:
1. Process for sequential addressing of inputs of is multiplexer that includes plural stages of switches from its inputs to its output and that is addressed at a level of each stage of switches by an elementary counter provided with a counting input, with a reinitialization input, with counting outputs controlling the switches of a relevant stage and with an overflow output, and chained to the elementary counters of lower stages of switches by linking its counting input to an overflow output of the elementary counter of the lower stage to constitute a global addressing counter, the process comprising: using, for addressing of the stage of switches of lower level closest to the inputs of the multiplexer, an elementary counter having a capacity or counting cycle length that can be adjusted on command; providing controllable circuits for shunting the elementary counters of the stages of intermediate switches; periodically generating a counting order for the counting input of the elementary counter of the stage of switches of lower level to describe successive counting cycles; altering a configuration of the global addressing counter, at a start of each of the counting cycles of the elementary counter of the stage of switches of lower level, by acting on a length of a forthcoming counting cycle of this elementary counter of the stage of switches of lower level as well as on in-activity shunting circuits of the elementary counters of the stages of intermediate switches.