Patent ID: 6703661
Filing Date: 2004-03-09
Classification: G11C,H01L

Abstract:
A contactless NOR-type memory array, comprising:a semiconductor substrate of a first conductivity type having a plurality of parallel isolation regions, wherein each of a plurality of active regions is formed between two nearby parallel isolation regions; a plurality of gate regions being defined on said semiconductor substrate and transversely to the plurality of parallel isolation regions, wherein each of the plurality of gate regions is formed between a common-source region and a common drain-region; each of the plurality of gate regions comprising an elongated control-gate layer being sandwiched between an interlayer dielectric layer formed on its top and an intergate dielectric layer formed at its bottom to act as a word line and a plurality of integrated floating-gate layers being formed beneath said intergate dielectric layer, wherein each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed on a thin tunneling-dielectric layer in said active region and two extended floating gate layers being formed separately on side portions of said two nearby parallel isolation regions; said common-source region comprising a plurality of common-source diffusion regions being formed in first surface portions of said semiconductor substrate in the plurality of active regions, a pair of first dielectiic spacers being formed over first sidewalls of nearby gate regions and on a first flat bed being formed alternately by said common-source diffusion region in said active region and an etched raised field-oxide layer in said parallel isolation region, a common-source conductive layer being formed over said first flat bed between said pair of first dielectric spacers, and a second thick-oxide layer being formed over said common-source conductive layer; said common-drain region comprising a plurality of common-drain diffusion regions being formed in second surface portions of said semiconductor substrate in the plurality of active regions, a pair of second dielectric spacers being formed over second sidewalls of nearby gate regions and a plurality of common-drain conductive islands being formed between said pair of second dielectric spacers, wherein each of the plurality of common-drain conductive islands is formed over a portion of said common drain diffusion region and its neat-by raised field-oxide layers; and a plurality of bit lines being formed above the plurality of active regions and transversely to the plurality of word lines, wherein each of the plurality of bit lines is formed over said second thick-oxide layers in said common-source regions, said interlayer dielectric layers in said gate regions and said common-drain conductive islands in said common-drain regions and a hard masking layer is formed over a metal layer to simultaneously pattern and form said metal layer and said common-drain conductive islands to form a bit line being integrated with said common-drain conductive islands.