Patent ID: 6563755
Filing Date: 2003-05-13
Classification: G11C

Abstract:
A semiconductor memory device comprising at least one memory cell periodically needing a refresh operation to hold stored information; and a time multiplexing circuit, whereinwhen a first memory operation on said memory cell to read stored information or to write information to be stored is instructed, said time multiplexing circuit performs one of a second memory operation having a different address designation from the first memory operation and an autonomous refresh operation before or after the first memory operation, and an access time period needed for the first memory operation and said one of the second memory operation and the autonomous refresh operation is set shorter than a sum of a first time period required for the first memory operation and a second time period required for said one of the second memory operation and the refresh operation, and sets of information stored in the memory cell in the first memory operation and in said one of the second memory operation and the refresh operation are not mutually affected.