Patent ID: 8786990
Filing Date: 2014-07-22
Classification: H01L,H02H

Abstract:
1. A circuit comprising: an ESD trigger circuit; and a plurality of I/O cells, each of the I/O cells including a first driver having a first source, a first drain, and a first gate, and a second driver having a second source, a second drain, and a second gate, wherein the ESD trigger circuit provides a first signal using a first ESD trigger terminal of the ESD trigger circuit to turn on the first driver in each of the I/O cells during an ESD event and a second signal using a second ESD trigger terminal of the ESD trigger circuit to turn on the second driver in each of the I/O cells during the ESD event to form a plurality of parallel ESD paths that include turned-on first drivers and turned-on second drivers; wherein each of the I/O cells further includes: an I/O pad coupled to the first and second drains; and a compare circuit coupled to the I/O pad, wherein the compare circuit receives the first and second signals, and compares a pad voltage at the I/O pad with the first and second signals.