Patent ID: 8422330
Filing Date: 2013-04-16
Classification: G06F

Abstract:
1. A memory controller comprising: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory, the memory having a plurality of the banks, from each of which the data element sequence is read out in response to an input of the read-address; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.