Patent ID: 7733727
Filing Date: 2010-06-08
Classification: G11C

Abstract:
1. A receiver circuit of a semiconductor memory apparatus, the receiver circuit comprising: a first data determining unit configured to detect and amplify a voltage level difference between first and second external data to generate first and second sense signals and for generating first internal data in response to the first and second sense signals; a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals configured to swing between a maximum voltage level and a minimum voltage level determined based on a first code; a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and generate second internal data in response to the third and fourth sense signals; and a second offset control unit configured to generate third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.