Patent ID: 6367054
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A computer implemented method of generating finite state data for designing a cascade decomposed logic circuit from finite state data defining current states, next states, input states and output states for a logic circuit, the method comprising:determining functions defining all transitions from a current state to a next state of the logic circuit caused by an input to the logic circuit; determining sets of circuit states which include the possible states of the logic circuit using said functions; assigning levels to said sets of circuit states, each level corresponding to one of a cascaded plurality of circuit units; defining each circuit unit to have a plurality of unit states, each unit state comprising a set of circuit states of the logic circuit; assigning said sets of states to said plurality of cascaded circuit units as unit states for the circuit units on the basis of the assigned levels, wherein the circuit states of each of at least two unit states of a circuit unit are subsets of a set of circuit states of a unit state of an immediately preceding circuit unit in the cascade, said subsets are a cover of said set, and at least one circuit unit has a unit state which is a set of circuit states of an immediately preceding circuit unit in the cascade; and determining next sets of circuit states for the circuit units using said functions and the circuit states of at least one preceding circuit unit in the cascade.