Patent ID: 6472271
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A planarization method of memory unit of a flash memory, comprising the steps of:forming a polysilicon layer having a memory unit pattern and a silicon nitride layer on a semiconductor substrate, said patterned polysilicon being separately used as a polysilicon of peripheral circuit and polysilicon floating gates; depositing an oxide layer over said semiconductor substrate; removing part of said oxide layer to separate oxide layer on and beside said silicon nitride and to still remain excess of said oxide layer; depositing a second silicon nitride layer on said semiconductor substrate to cover said etched oxide layer and said exposed silicon nitride; removing said oxide layer and said second silicon nitride on said polysilicon of peripheral circuit; removing said remained oxide layer on said silicon nitride on said polysilicon of peripheral circuit by sideward etching; and simultaneously removing said silicon nitride layer, said remained oxide layer, and said second silicon nitride layer.