Patent ID: 7663216
Filing Date: 2010-02-16
Classification: G11C,H01L

Abstract:
1. A semiconductor package, comprising: a plurality of stacked substrate layers including at least a first substrate layer and a second substrate layer, the plurality of stacked substrate layers each including a pattern of electrical traces, the pattern of electrical traces on each substrate layer including at least a first trace and a second trace, the first trace on each layer electrically coupled to each other and the second trace on each layer electrically coupled to each other; a plurality of semiconductor die affixed to the plurality of stacked substrate layers, one semiconductor die per substrate layer; a first opening defined through the first trace on the first layer so that a current to the first traces on the first and second substrate layers reaches the semiconductor die on the second substrate layer but is prevented from reaching the semiconductor die on the first substrate layer; and a second opening defined through the second trace on the second layer so that a current to the second traces on the first and second substrate layers reaches the semiconductor die on the first substrate layer but it prevented from reaching the semiconductor die on the second substrate layer, the first and second openings allowing unique addressability of the semiconductor die on the first and second substrate layers.