Patent ID: 6372554
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, said method comprising the steps of:forming a plurality of semiconductor elements and associative leads in a first region within a plurality of chip regions partitioned on a principal surface of a semiconductor wafer; patterning, during formation of the semiconductor elements and leads, a first conductive layer constituting one of said semiconductor elements and said leads to form a first fuse in a scribe region on the principal surface of said semiconductor wafer while forming a second fuse in a second region within said chip regions; forming a first pad in said scribe region by patterning of a third conductive layer formed on the principal surface of said semiconductor wafer for causing said first pad and said first fuse to be electrically connected together via a second conductive layer formed to overlie said first conductive layer; forming, after having formed a passivation film on the principal surface of said semiconductor wafer with said third conductive layer formed thereon, a resin layer with photosensitivity on the principal surface of said semiconductor wafer on which said passivation film was formed; subjecting said resin layer to exposure and development processing to form said resin layer having a first opening overlying said first pad formed in said scribe region and also having a second opening overlying said second fuse formed in said second region; and etching said passivation film underlying said first opening by use of said resin layer having said first and second openings formed therein as a mask to thereby expose said first pad while etching said passivation film underlying said second opening to form an opening for use in fuse cutting in a dielectric film overlying said second fuse, wherein said scribe region is such that said resin layer covers patterns of the second and third conductive layers overlying said first fuse.