Patent ID: 6479386
Filing Date: 2002-11-12
Classification: B24B

Abstract:
A process of forming a semiconductor wafer which inhibits the formation of surface features of a nanotopology scale on a polished front side of the wafer, the process comprising the steps of:slicing a wafer from an ingot of semiconductor material; etching the wafer to remove damage from at least one side thereof; applying wax in flowable form to a mounting surface of the polishing block; pressing a back side of the semiconductor wafer into the wax on the polishing block to bond the wafer to the polishing block, the pressing of the wafer into the wax against the polishing block moving the wafer from a relaxed configuration to a deformed configuration; prior to any polishing of the wafer as mounted on the polishing block, heating the wax bonding the wafer to the polishing block to a temperature of up to 95Â° C. and for a time selected to soften the wax and permit the wafer to move relative to the polishing block toward the relaxed configuration without breaking the bond of the wafer to the polishing block thereby to relieve stress in the wafer; polishing the front side of the wafer as mounted on the polishing block by holding the polishing block and rubbing the front side of the wafer against a polishing pad in the presence of a polishing slurry; removing the polished wafer from the polishing block; and cleaning the wafer.