Patent ID: 6738242
Filing Date: 2004-05-18
Classification: H02H

Abstract:
A bus-switch chip protected from pin-to-pin electro-static-discharge (ESD) pulses comprising:a first pin; a second pin; a bus-switch transistor having a drain coupled to the first pin and a source coupled to the second pin and a gate coupled to a bus-switch gate node, the bus-switch transistor connecting the first pin to the second pin when an activating voltage is applied to the bus-switch gate node, but isolating the first pin from the second pin when an isolating voltage is applied to the bus-switch gate node during normal operation when power is applied to the bus-switch chip; a first coupling capacitor, coupled between the first pin and a first coupling-gate node, for generating an activating voltage on the first coupling-gate node during an ESD pulse applied to the first pin; a first coupling transistor responsive to the first coupling-gate node, for connecting the first pin to a first grounding-gate node when the first coupling capacitor generates the activating voltage on the first-coupling gate node; and a first grounding transistor, responsive to the first grounding-gate node, for connecting the second pin to the bus-switch gate node when the first coupling transistor connects the ESD pulse on the first pin to the first grounding-gate node, whereby the bus-switch transistor is shut off by being connected to the second pin when the ESD pulse is applied to the first pin.