Patent ID: 7193926
Filing Date: 2007-03-20
Classification: G11C

Abstract:
1. A memory device for reducing leakage current, the memory device comprising: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; N controllers for controlling the 2N switching blocks, respectively, each of the controllers having an output; and N inverters, each inverter of the N inverters having an input coupled to the output of a corresponding one of the N controllers, each inverter of the N inverters having an output that is coupled to a corresponding pair of the 2N switching blocks; wherein an output signal from each of the N controllers is inverted by a corresponding inverter, and wherein said inverted signal from a controller turns off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.