Patent ID: 7430652
Filing Date: 2008-09-30
Classification: G06F

Abstract:
1. A hardware accelerator module comprising: a plurality of hardware accelerators configured to perform algorithmic operations on data; an interface configured to couple the hardware accelerator module to a computing device such that the hardware accelerator module is removably attachable to the computing device, the computing device being configured to execute software and receive an input file; a data transmission path extending between the plurality of hardware accelerators; and a task management unit configured to receive a data structure comprising indications of a plurality of operations to be performed on the input file by the plurality of hardware accelerators, the data structure being generated by the computing device prior to execution of any of the plurality of operations by respective of the hardware accelerators, wherein the plurality of operations are determined based at least partly on one or more characteristics of the input file, the task management unit being further configured to originally generate headers indicating respective algorithmic operations to be performed by the respective hardware accelerators for transmission to respective hardware accelerators; wherein said data structure and said input file are received from the computing device via the interface and each of said plurality of operations are executed by the hardware accelerator module independent of additional communication with said computing device.