Patent ID: 8219950
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. A set of two cells for performing a same logical function, each of said two cells comprising a semiconductor inverting device, said semiconductor inverting device comprising at least one NMOS transistor and at least one PMOS transistor; a first of said two cells configured to operate with an input of zero during an inactive period where said cell does not change state; a second of said two cells configured to operate with an input of one during an inactive period where said cell does not change state; said first cell having a first ratio of a width of said at least one PMOS transistor and said at least one NMOS transistor within said semiconductor inverting device; and said second cell having a second ratio of a width of said at least one PMOS transistor and said at least one NMOS transistor within said semiconductor inverting device; wherein said first ratio is not equal to said second ratio and said first and second ratios are such that a sum of a delay in a rise time of a signal propagated by said first cell and a fall time of a signal propagated by said second cell is substantially equal to a delay in a fall time of a signal propagated by said first cell and a rise time of a signal propagated by said second cell, even when said signal is propagated directly after said inactive period.