Patent ID: 6507807
Filing Date: 2003-01-14
Classification: G06F

Abstract:
An apparatus for determining a total effective RC delay of each branch of a network and for determining which branch has the largest total effective RC delay, the network being comprised in an integrated circuit, each branch having a primary RC delay associated therewith, the primary RC delay of each branch being attributable to one or more resistances and one or more capacitances comprised by the branch, the apparatus comprising:a computer programmed to execute a rules checker algorithm, wherein when the rules checker algorithm is executed by the computer, the rules checker algorithm analyzes each branch to determine a total effective RC delay of each branch, wherein the total effective RC delay of a particular branch includes the primary RC delay attributable to said one or more resistances and said one or more capacitances of the particular branch and an effect that said one or more resistances and said one or more capacitances of any other branches have on the particular branch, the rules checker algorithm determining which branch has the largest total effective RC delay.