Patent ID: 8062946
Filing Date: 2011-11-22
Classification: H01L

Abstract:
1. A method of fabrication a strained-channel transistor structure with improved transport properties, comprising: providing a substrate having a first semiconductor material with a first natural lattice constant, a gate dielectric layer on the substrate, a gate electrode on the gate dielectric layer, and a first spacer on a sidewall of the gate electrode; recessing the surface of the substrate not covered by the spacer and gate dielectric layer to form a recess; filling the recess with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone; forming a cap layer on the second semiconductor material, the cap layer comprising the first semiconductor material with the first natural lattice constant; and forming a first source region and a first drain region oppositely adjacent to the gate dielectric layer, one or both of the first source region and the first drain region comprising the lattice-mismatched zone and the cap layer; forming a second spacer overlying the first spacer; and forming a second source region adjacent to the first source region and second drain region adjacent to the first drain region, wherein the first semiconductor material is silicon.