Patent ID: 6417790
Filing Date: 2002-07-09
Classification: H03K,H03M

Abstract:
A data serializer comprising:n data inputs, where n is an integer greater than one; n clock inputs, wherein each clock input is out of phase with the other clock inputs and corresponds to one of the n data inputs; a differential output stage comprising first and second differential data outputs and n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of the n data inputs; and an input stage comprising, for each of the n data inputs: a first logic AND circuit having first, second and third inputs which are coupled to the data input, the corresponding clock input and an inverse of the clock input that next trails the corresponding clock input in phase, respectively, and an output which is coupled to the first control input of the corresponding pair of control inputs through p-channel drive transistors; and a second logic AND circuit having first, second and third inputs which are coupled to an inveise of the data input, the corresponding clock input and the inverse of the clock input that next trails the corresponding clock input in phase, respectively, and an output which is coupled to the second control input of the corresponding pair of control inputs through p-channel drive transistors.