Patent ID: 7952133
Filing Date: 2011-05-31
Classification: H01L

Abstract:
1. A flash memory comprising: a semiconductor substrate including a device isolation region and an active region; a stack gate on the active region, the stack gate comprising a gate insulation layer formed on the semiconductor substrate, a floating gate formed on the gate insulation layer, a dielectric layer formed on the floating gate, and a control gate formed on the dielectric layer; a drain terminal on one side of the stack gate; a source terminal on an opposite side of the stack gate; an insulation layer covering the semiconductor substrate and the stack gate; a drain contact penetrating the insulation layer on the one side of the stack gate, the drain contact making electrical contact with only the drain terminal; a source line penetrating the insulation layer on the opposite side of the stack gate, the source line interconnecting source terminals of adjacent stack gates; and a source line contact on the source line, wherein the drain contact and the source line consist essentially of identical materials.