Patent ID: 6396743
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A control circuit for a non-volatile memory array having a plurality of sectors, each sector having a plurality of non-volatile memory cells connected by a line, said control circuit for receiving a first voltage (V) and for distributing said first voltage to said plurality of sectors, said circuit comprising:a plurality of first transistors each first transistor having a first terminal, a second terminal and a channel therebetween, and a gate for controlling the flow of current between said first and second terminals; wherein the first terminal of each first transistor is connected to the line of a different sector; the second terminals of said plurality of first transistors are connected together to receive the first voltage; a second transistor having a first terminal, a second terminal, and a channel therebetween, and a gate for controlling the flow of current between said first and second terminals; wherein the first terminal of said second transistor is connected to said second terminals of said plurality of first transistors; said gate of said plurality of first transistors and said gate of said second transistor are connected together and to said second terminal of said second transistor; and a current limiter circuit connected to said second terminal of said second transistor for limiting the current (I) supplied to said sectors.