Patent ID: 8183127
Filing Date: 2012-05-22
Classification: H01L

Abstract:
1. A method for bonding first and second wafers comprising: depositing a dielectric layer on a surface of said first wafer; constructing a plurality of metallic bonding pads comprising a bonding layer that extends into said dielectric layer of said first wafer, said pads extending a first distance above said dielectric layer of said first wafer, at least one of said pads being connected electrically to a circuit layer in said first wafer; wherein said bonding pads on said first wafer comprise a bonding layer that extends into a first bonding surface, said bonding pads extending a first distance above said first bonding surface, and wherein said first wafer is divided into a plurality of chip circuit areas and wherein within each chip circuit area, each sub-area greater than 500 μm within said chip circuit area is characterized by metal surface density equal to the fraction of that sub-area that is covered by metal, wherein said metal surface density for each one of said sub-areas is constant to within ±10 percent, and wherein said bonding pads have a maximum dimension greater than 0.5 μm and less than 20 μm; depositing a dielectric layer on a surface of said second wafer; constructing a plurality of pads comprising a bonding layer that extends into said dielectric layer on said second wafer, said pads extending a first distance above said dielectric on said second wafer, at least one of said pads being connected electrically to a circuit layer in said second wafer, wherein each pad on said dielectric layer of said first wafer contacts a corresponding pad on said dielectric layer of said second wafer when said first and second wafers are aligned such that said dielectric layers on said first and second wafers are adjacent to one another; planarizing said pads on both of said wafers; and bonding said pads on said dielectric layer of said first wafer to said corresponding pads on said dielectric layer of said second wafer.