Patent ID: 7764565
Filing Date: 2010-07-27
Classification: G11C

Abstract:
1. An integrated circuit device comprising: a memory array including at least one memory block, said memory block comprising at least two memory banks, said memory banks having intermediate non-shared sense amplifiers therebetween; and a plurality of column decoder bands associated with said memory block and coupled to a number of I/O pads of said device by a datapath, wherein said memory array comprises: at least a left-side first memory block and at least a right-side second memory block, said first and second memory blocks comprising at least two of said memory banks; a first of said column decoder bands associated with said first memory block and coupled to a first number of I/O pads by a first datapath; and a second of said column decoder bands associated with said second memory block and coupled to a second number of I/O pads by a second datapath.