Patent ID: 6275501
Filing Date: 2001-08-14
Classification: H04L

Abstract:
A network node comprising:a serial physical sublayer (PHY) chip, comprising:a single bit transmit data input,a single bit receive data output, andserial PHY control signal input/output (I/O) lines;a parallel PHY chip, comprising:a multi-bit transmit data input,a multi-bit receive data output, andparallel PHY control signal I/O lines; and,a media access control (MAC) chip, comprising:a multi-bit transmit data output, the multi-bit transmit data output being coupled to the multi-bit transmit data input, and one bit of the multi-bit transmit data output being coupled to the single bit transmit data input,a multi-bit receive data input, the multi-bit receive data input being coupled to the multi-bit receive data output, and one bit of the multi-bit receive data input being coupled to the single bit receive data output, andparallel control signal I/O lines, the parallel control signal I/O lines being coupled to the parallel PHY control signal I/O lines.