Patent ID: 6574149
Filing Date: 2003-06-03
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a pair of impurity-diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulation film on the semiconductor substrate between said pair of impurity-diffused layers to thereby trap carriers at different positions in the gate insulation film by applying a predetermined voltage to said gate electrode, wherein a tunnel current is supplied between the semiconductor substrate and said gate electrode by applying a first voltage to the semiconductor substrate including said pair of impurity-diffused layers and applying a second voltage to said gate electrode, and wherein the tunnel current erases the carriers trapped in the gate insulation film, said semiconductor memory further comprising: a first well of the same conductivity type as the semiconductor substrate in which said pair of impurity-diffused layers are formed, and a second well which covers an area form a side surface to a bottom surface of the first well, wherein the first voltage is applied to said first well and said pair of impurity-diffused layers.