Patent ID: 6181640
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A semiconductor memory device including a memory cell array composed of a plurality of memory cells, a plurality of word lines for selectively accessing the memory cell, a plurality of bit lines for loading data to/from the memory cell, comprising:an address transition detector for detecting a transition of an address signal externally applied thereto and producing a precharge signal having a first predetermined active duration;a dummy bit line unit for producing a dummy bit line signal in response to an activation of at least one word line;a pulse generator for generating a pulse, the pulse signal becoming active in response to both an activation of a write enable signal externally applied and a de-activation of the precharge signal, and the pulse signal having a second predetermined active duration;a latch for producing a latch signal, the latch signal being reset in response to the precharge signal or the pulse signal and being set in response to the dummy bit line signal; anda write signal generator for producing a write signal, the write signal becoming active in response to the latch signal and becoming non-active in response to the latch signal,wherein the data externally applied is transferred to the memory cell through the bit line only when the write signal is active.