Patent ID: 7763537
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A method for forming a metal interconnection of a semiconductor device, comprising: forming a first metal interconnection on a semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate including the first metal interconnection; forming a via hole and a trench on the via hole by selectively removing the interlayer dielectric layer; forming a metal diffusion blocking layer on the interlayer dielectric layer formed with the trench and the via hole; forming a second metal film on the metal diffusion blocking layer; selectively polishing the second metal film and the metal diffusion blocking layer through a chemical mechanical polishing (CMP) process to form a second metal interconnection in the via hole and the trench below a top portion of the metal diffusion blocking layer such that the top surface of the second metal interconnection is recessed below the top surface of the metal diffusion blocking layer; etching the interlayer dielectric layer by an etching process to a depth corresponding to a height of the second metal interconnection; and forming a protection layer covering the etched interlayer dielectric layer, the metal diffusion blocking layer, and the second metal interconnection.