Patent ID: 6518111
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising:forming a collector region in a semiconductor substrate; forming an isolation structure adjacent at least a portion of the collector region; forming a gate stack layer adjacent at least a portion of the isolation structure wherein forming the gate stack layer comprises forming a gate polysilicon layer and forming a base layer adjacent the gate polysilicon layer; forming a base region of the semiconductor substrate adjacent at least a portion of the collector region, wherein the base region comprises a base link up region proximate a lateral edge of the base region; forming a diffusion source layer adjacent at least a portion of the base link up region; and removing a portion of the gate stack layer to form a base electrode adjacent a portion of the base region and a gate electrode spaced apart from the base electrode, wherein the gate electrode is located at a complementary metal oxide semiconductor (CMOS) area of the semiconductor device.