Patent ID: 7102914
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. A DRAM device comprising: a deep trench capacitor formed in a semiconductor substrate for receiving and storing a voltage; a storage cell including a vertical pass transistor having source and drain regions formed in a p-well, said drain region formed by a diffusion in said p-well outside said deep trench capacitor adjacent a first buried strap to conduct said voltage to said trench capacitor; and a control cell for controlling the threshold voltage of the vertical pass transistor according to a voltage of a gate connecting a second buried strap and diffusion region formed in the p-well region, said second buried strap region and diffusion region formed in said p-well region of said control cell being at a lower depth than the first buried stray and diffusion region formed in said p-well region of said storage cell, wherein a voltage applied at a gate connecting said second buried strap and diffusion region controls said threshold voltage of the vertical pass transistor in accordance with a depletion region formed in said p-well region by application of said applied gate voltage.