Patent ID: 8614122
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A method, comprising: forming a first hard mask layer on a first active region and a second active region of a semiconductor device wherein the first and second active regions are separated by an isolation region; forming a second hard mask layer on said first hard mask layer and said isolation region; forming an etch mask above said second active region and at least a portion of said isolation region; with said etch mask in position, performing one or more plasma-assisted etch process to remove said first hard mask layer and said second hard mask layer from said first active region; forming a layer of a semiconductor alloy on said first active region and using at least one of said first hard mask layer and said second hard mask layer on said second active region as a growth mask; exposing said second active region; and forming a first gate electrode structure of a first transistor on said layer of a semiconductor alloy and a second gate electrode structure of a second transistor on said second active region, said first and second gate electrode structures comprising a metal-containing gate electrode material and a gate insulation layer comprising a high-k dielectric material.