Patent ID: 8243003
Filing Date: 2012-08-14
Classification: H03K

Abstract:
1. A level shift circuit comprising: a first level shifter connected between a first power supply terminal that supplies a first voltage and a first output terminal and a second output terminal, the first level shifter receiving a first input signal and a second input signal from a first input terminal and a second input terminal, respectively, and setting one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shifter connected between a second power supply terminal that supplies a second voltage and the first and second output terminals, the second level shifter setting an other of the first and second output terminals to a second voltage level, while the one of the first and second output terminals being set to the first voltage level by the first level shifter; and a circuit that receives a first control signal, disconnects a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that has been set to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals and connects a current path in the second level shifter between the second power supply and the other of the first and second output terminals, for a first time interval including the time point when the first and second input signals are supplied to the first and second input terminals, and cancels the disconnection of the current path between the one of the first and second output terminals and the second power supply terminal for a second time interval after the first time interval, wherein the setting the one of the first and second output terminals to the first voltage level by the first level shifter and the setting the other of the first and second output terminals to the second voltage level by the second level shifter are operated in the first time interval, and wherein output amplitudes at the first and second output terminals are set to be larger than amplitudes of the first and second input signals.