Patent ID: 9019513
Filing Date: 2015-04-28
Classification: B41J,G06K

Abstract:
1. A multi-dimensional data registration integrated circuit for driving array-arrangement devices, comprising: a plurality of the i-th hierarchy sets, each of the i-th hierarchy sets is further divided into a plurality of the (i+1)-th hierarchy sets, wherein both i and n are positive integers and 0<i<n; a i-th hierarchy address selection circuit, comprising a signal generating unit and a multiplexing unit, wherein the signal generating unit generates an enabling signal based on a first timing signal and an input data, the multiplexing unit is electrically connected to the signal generating unit via a shift register and shifts the input data based on the enabling signal and a second timing signal to further generate n bits of address signals, the shift register generate a set of enabling signals via a first control circuit, a second control circuit, or a third control circuit, wherein the first, second, and third control circuits enable the signals once for every two, there, and four timing periods, respectively, a logic operation is performed between the address signal and one of the set of enabling signals to drive a cell circuit, the i-th hierarchy address selection circuit is used to scan the plurality of the i-th hierarchy sets and select at least one of the i-th hierarchy sets to function; and a data supply circuit to follow a scan sequence of the j-th hierarchy address selection circuit and write a plurality of data into the selected j-th hierarchy sets, and 1<j<(n+1).