Patent ID: 7519788
Filing Date: 2009-04-14
Classification: G06F,G11C

Abstract:
1. A memory hub, comprising: a link interface receiving memory requests for access to memory locations in at least one memory device; a memory device interface adapted to couple memory requests to memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a memory controller coupled to the link interface and the memory device interface, the memory controller adapted to couple memory requests to the memory device interface responsive to memory requests received from the link interface responsive to a core clock signal, the memory controller further adapted to adjust the timing at which read memory requests are coupled to the memory device interface responsive to a write-read pointer offset signal; and a read data synchronizing circuit coupled to the memory device interface, the read synchronization module, and the memory controller, the read data synchronizing circuit coupling read data from the memory devices operating according to a memory device clock signal to the memory controller, the read data synchronizing circuit comprising: