Patent ID: 9218074
Filing Date: 2015-12-22
Classification: G06F,G09G,G11C,H03K

Abstract:
1. A gate drive circuit in which multiple stages are connected together one after each other, the stages configured to output a plurality of gate signals, an n-th stage, ‘n’ being a natural number, comprising: a pull-up part configured to output a high voltage of a first clock signal applied through a first clock terminal as a high voltage of an n-th gate signal; a carry part configured to output a high voltage of the first clock signal as a high voltage of an n-th carry signal; a pull-down part configured to pull-down the n-th gate signal into a first low voltage in response to a high voltage of a carry signal of an (n+1)-th stage; a switching part configured to output a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal; a first maintaining part configured to maintain the n-th gate signal into the first low voltage in response to the first signal; and a second maintaining part configured to maintain the n-th gate signal into the first low voltage in response to a second signal having a phase different from that of the first signal, wherein the second signal is applied through a second clock terminal, the second signal being a second clock signal having a phase different from a phase of the first clock signal, wherein the first clock terminal of the n-th stage that receives the first clock signal is different from the second clock terminal of the n-th stage that receives the second clock signal, and wherein the second maintaining part comprises an eighteenth transistor having a control terminal connected to the second clock terminal, an input terminal configured to receive the n-th gate signal, and an output terminal configured to receive the first low voltage.