Patent ID: 7807533
Filing Date: 2010-10-05
Classification: G11C,H01L

Abstract:
1. A method of forming non-volatile memory, comprising: forming a first dielectric layer above a substrate; forming a first layer of gate material above the first dielectric layer; forming a second dielectric layer above the first layer of gate material; forming a second layer of gate material above the second dielectric layer; forming floating gate stacks from the first dielectric layer, first layer of gate material, second dielectric layer and second layer of gate material, a floating gate is provided by the first layer of gate material in each of the floating gate stacks; forming source/drain regions between pairs of adjacent floating gate stacks, where the floating gate stacks and the source/drain regions are formed in a plurality of NAND strings extending parallel to one another in an array; and forming shallow trench isolation regions in the substrate which extend parallel to one another in strips alongside the NAND strings, the shallow trench isolation regions also extend parallel to the NAND strings; forming word lines which extend parallel to one another in the array, where the word lines are connected to the floating gate stacks; performing a selective epitaxial process to grow shield layers on the source/drain regions between the pairs of adjacent floating gate stacks, the shield layers are grown on the source/drain regions between each pair of adjacent floating gate stacks within each NAND string, and are not grown above the shallow trench isolation regions, the shield layers extend to a height which is above a top of the first dielectric layer and above a bottom portion of the first layer of gate material, the height is partway between a top and bottom of the floating gate in each floating gate stack, so that the shield layers act as shield plates which reduce capacitive coupling between floating gates of each pair of adjacent floating gate stacks.