Patent ID: 7519757
Filing Date: 2009-04-14
Classification: G06F,G11C,H05K

Abstract:
1. A system comprising: a controller chip; and a memory module coupled to the controller chip, the memory module comprising: a first edge finger and a second edge finger disposed along an edge of the memory module, the first edge finger to receive a first signal from the controller chip and the second edge finger to receive a clock signal from the controller chip; a first signal line having a first end coupled to the controller chip by the first edge finger, the first signal line having a segment disposed along a length of the memory module that is parallel to the edge of the memory module, wherein the first signal traverses the segment of the first signal line until reaching a first termination at an end of the first signal line; a clock line having a first end coupled to the second edge finger, the clock line to carry a clock signal that traverses the clock line alongside the first signal until the clock signal reaches a second termination at an end of the clock line; a first synchronous memory device connected to the segment of the first signal line and the clock line such that the first signal and the clock signal arrive at the first synchronous memory device at substantially the same time; and a second synchronous memory device connected to the segment of the first signal line and the clock line such that the first signal and the clock signal arrive at the second synchronous memory device at substantially the same time and after the first signal and the clock signal arrive at the first synchronous memory device.