Patent ID: 9202890
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method for manufacturing a dummy gate in a gate-last process, comprising: providing a semiconductor substrate without trench; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon, α-Si, on the gate oxide layer; depositing an oxide-nitride-oxide, ONO, structured hard mask on the bottom-layer α-Si; depositing top-layer α-Si on the ONO structured hard mask; depositing a hard mask layer on the top-layer α-Si; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and forming the dummy gate on the semiconductor substrate without trench, by etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si in accordance with the photoresist lines and removing the photoresist lines, the hard mask layer and the top-layer α-Si.