Patent ID: 7396757
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A method for forming an interconnect structure, comprising: forming interconnect features embedded in a first dielectric layer deposited on a substrate, said interconnect features having patterned exposed interconnect areas; forming a second layer material on the portion of said first dielectric layer surrounding said exposed interconnect areas; forming a cap layer on said exposed interconnect areas; depositing a multi-phase photoresist on said second layer material and said cap layer; and separating the portion of said multi-phase photoresist contiguous with said second layer material into a pattern of different phase materials, wherein said multi-phase photoresist is a two-phase photoresist having a first phase (A) photoresist and a second phase (B) photoresist, wherein second phase photoresist has a higher etching resistance that said firs phase (A) photoresist.