Patent ID: 7211885
Filing Date: 2007-05-01
Classification: H01L

Abstract:
1. A memory and/or data processing device comprising at least two stacked layers forming a stack with each of the layers having a thickness of 1 μm or less, the stack either forming a self-supporting structure or being provided on a substrate, and the stack including at least one of the layers staggered in at least one direction such that steps in the staggered layers being formed by exposed portions of the separate layers in the stack and with a step height corresponding to a thickness of respective layers, one or more contact pads provided on each step in the staggered layers in electrical connection with memory and/or processing circuits in the respective layer, and one or more electrical edge deposition connections provided on and extending over the step in direct contact with the step in each layer in the form of electrical conducting structures on the step and over and on an edge between the steps in each layer and deposited on a surface of the layers, the electrical edge connections contacting one or more contact pads in the layers and providing electrical connection between each layer and also between the layers and contact pads.