Patent ID: 8971144
Filing Date: 2015-03-03
Classification: G06F,G11C,H04L

Abstract:
1. A system for providing write-protection functionality to a memory device comprising: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device, further wherein, after the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device, the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device.