Patent ID: 6060924
Filing Date: 2000-05-09
Classification: G01R

Abstract:
A semiconductor integrated circuit formed on a semiconductor chip, comprising:a first shift register including a plurality of first flipflops each including a first latch circuit for latching a first scanning data in response to a first clock signal and a second latch circuit for latching output data of said first latch circuit in response to an inverted signal of the first clock signal, an output of each of the second latch circuits being inputted as the first scanning data to the first flipflop in a next stage; anda second shift register including a plurality of second flipflops each including a third latch circuit for latching a second scanning data in response to a second clock signal, which differs from the first clock signal and an inversion of the first clock signal, and a fourth latch circuit for latching output data of said third latch circuit in response to a third clock signal, an output of each of the fourth latch circuits being inputted as the second scanning data to the second flipflop in the next stage.