Patent ID: 6584523
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A device for prioritizing access to a bus, comprising:an input register to receive at least one asynchronous binary signal of a first type representing a request for access to the bus issued by at least one respective entity of a plurality of entities; an output register; and a wired logic priority decoder connected to the input register and to the output register, the priority decoder issuing at least one binary signal of a second type to authorize the access of the at least one requesting entity to the bus based on a determination of priority among different access requests; connection circuit to connect the prioritizing device to at least one other prioritizing device of a same type to organize the sharing of the bus therebetween; a token generator to generate a token; a token regenerator to receive the token from the token generator and to output the token on an output signal line; and a receiver circuit to receive the token sent by the at least one other prioritizing device.