Patent ID: 9142274
Filing Date: 2015-09-22
Classification: G11C

Abstract:
1. A memory device, comprising: a memory array including a plurality of memory cells including respective data storage elements, wherein a data storage element of a memory cell has a transition time for the data storage element to transition from a first data state to a second data state during a write operation; a write tracking cell including a transition modeling element that models the transition time of the data storage element, wherein the transition modeling element comprises: a pair of cross-coupled inverters having complimentary storage nodes, wherein a first complimentary storage node is coupled to an input node of the write tracking cell via a first access transistor, and a second complimentary storage node is coupled to an output node of the write tracking cell via a second access transistor whose source/drain regions are shorted together; and a controller configured to measure the modeled transition time provided by the write tracking cell and further configured to set a pulse length applied to the memory cell during the write operation based on the measured modeled transition time.