Patent ID: 8248348
Filing Date: 2012-08-21
Classification: G09G,H03K

Abstract:
1. A level shifter circuit, comprising: a level shifter for level shifting two kinds of clock signals which are out of phase with each other so as to have non-overlapping high level periods and/or non-overlapping low level periods, said level shifter being provided for each of the two kinds of clock signals and carrying out level shifting so that a high level of the clock signal is converted to either a high level or low level of a predetermined power voltage, and a low level of the clock signal is converted to the other level of the predetermined power voltage, said level shifter carrying out the level shifting using a predetermined voltage that is generated by flowing a predetermined constant current through a predetermined circuit of the level shifter during a non-active period of the corresponding clock signal; and level shifting control circuitry for suspending the level shifting during a specific time period of the non-active period, by preventing the constant current from flowing into the predetermined circuit, wherein the level shifting control circuitry uses an output voltage which results from level shifting in an active period of the other clock signal different from the corresponding clock signal so as to prevent the constant current from flowing into the predetermined circuit, and wherein the specific time period of the non-active period corresponds to the active period of the other clock signal.