Patent ID: 6772300
Filing Date: 2004-08-03
Classification: G06F

Abstract:
A computer system comprising:a main memory; and a chip set coupled to the main memory, comprising: mapping logic to translate transaction addresses to physical addresses; and linked list logic, coupled to the mapping logic, for managing out of order accesses to the main memory, the linked list logic including: a transaction memory; a first bank controller coupled to the transaction memory to store transaction data to be transmitted to a first bank of the main memory within the transaction memory according to a first linked list; a second bank controller coupled to the transaction memory to store transaction data to be transmitted to a second bank of the main memory within the transaction memory according to a second linked list; first selector logic coupled to the first bank controller and the second bank controller to select data to be transmitted to the transaction memory from either the first bank controller or the second bank controller; second selector logic coupled to the first bank controller and the second bank controller to select data to be transmitted to the main memory from either the first bank controller or the second bank controller; and arbitration logic coupled to the second selector logic, the first bank controller and the second bank controller.