Patent ID: 9008254
Filing Date: 2015-04-14
Classification: H03L

Abstract:
1. An apparatus comprising: a phase detector for receiving a first input clock and a second input clock and generating a phase error signal representing a timing difference between the first input clock and the second input clock, wherein the phase error signal comprises a first plurality of waveforms each having a first duration and a second plurality of waveforms each having a second duration, the second plurality of waveforms corresponding to deterministic jitter; a mask circuit for masking the phase error signal to generate a masked phase error signal in accordance with a deterministic jitter indicator signal that indicates a deterministic jitter of the first input clock, the masked phase error signal corresponding only to the first plurality of waveforms; a loop filter for filtering the masked phase error signal to generate an oscillator control signal; and a control oscillator for generating an output clock in accordance with a control of the oscillator control signal.