Patent ID: 9036689
Filing Date: 2015-05-19
Classification: H04L

Abstract:
1. A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer connected to outputs of a plurality of analog-to-digital converters (ADCs) based on time-interleaved successive approximation registers, the VPDA MIMO equalizer comprising: a plurality of sub-equalizers classified into a first sub-equalizers group and a second sub-equalizers group, wherein each of a plurality of sub-equalizers included in the first sub-equalizers group is connected to outputs of a first ADC group and each of a plurality of sub-equalizers included in the second sub-equalizers group is connected to outputs of a second ADC group; and a decision unit configured to determine recovered data using an output symbol of the plurality of sub-equalizers, wherein one sub-equalizer included in the first sub-equalizers group relates to other one sub-equalizer included in the second sub-equalizers group, and the recovered data is determined by the decision unit based on outputs of the one sub-equalizer and the other one sub-equalizer, wherein each of the plurality of sub-equalizers comprises a plurality of additional-equalizers for distributed arithmetic, and each of the additional-equalizers corresponds to one of bits according to a resolution of the ADCs.