Patent ID: 6930342
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A semiconductor memory having a memory cell array region and peripheral circuit region, comprising: a gate electrode formed on a semiconductor substrate via an insulating film in each of said memory cell array region and peripheral circuit region, and including a conductive layer; a first oxide film formed on side surfaces of said conductive layer of said gate electrode and on said semiconductor substrate in said memory cell array region; a second oxide film formed on side surfaces of said conductive layer of said gate electrode and on said semiconductor substrate in said peripheral circuit region, and having a film thickness smaller than that of said first oxide film; a first nitride film formed on side surfaces of said gate electrode in said memory cell array region; and a second nitride film formed on side surfaces of said gate electrode in said peripheral circuit region, and having a film thickness larger than that of said first nitride film.