Patent ID: 7419878
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A fabrication process for a power MOSFET comprising: forming a first trench in a substrate; forming a second trench in the substrate; doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench; forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus including a metal/silicide region; planarizing a structure including the substrate and the conductive gate structure in the first and second trenches; depositing a contact layer after planarizing the structure, wherein the contact layer includes a first region contacting the vertical device adjacent to the first trench and a second region overlying the second trench and contacting the gate bus; and forming a first polysilicon layer that lines at least one of the first and second trenches; depositing a metal on the first polysilicon layer; etching the metal back to leave portions of the metal in depressions in the first polysilicon layer; and depositing a second polysilicon layer so that the metal that is remaining on the first polysilicon layer is surrounded by polysilicon in at least one of the first and second trenches; further comprising reacting the metal with the surrounding polysilicon to form suicide.