Patent ID: 6748479
Filing Date: 2004-06-08
Classification: G06F,H04L

Abstract:
An apparatus comprising:one or more interface circuits, each interface circuit coupled to a respective interface, wherein the one or more interface circuits are coupled to receive packets and coherency commands from the interfaces; an interconnect; a memory controller coupled to the interconnect and configured to couple to a memory; a memory bridge coupled to the interconnect; a packet direct memory access (DMA) circuit coupled to the interconnect; and a switch coupled to the interface circuits, the memory bridge, and the packet DMA circuit, wherein the switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit, wherein the memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands, and wherein the packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in the memory.