Patent ID: 8098735
Filing Date: 2012-01-17
Classification: H04N

Abstract:
1. A circuit comprising: a first module configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from said parsing of said 8×8 CABAC residual block, wherein said plurality of metric signals comprises (i) a first metric signal indicating a parsed significant coefficient flag, (ii) a second metric signal configured to count from zero to a last scanning position of a non-zero coefficient in said 8×8 CABAC residual block, (iii) a third metric signal configured to count a number of non-zero coefficients in said 8×8 CABAC residual block, and (iv) a fourth metric signal configured to control a next coefficient level scanning position; a second module configured to generate a scanning position signal based on said first, said second, said third, and said fourth metric signals, wherein said scanning position signal specifies the scanning position of the next coefficient level; and a third module configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling said parsed residual blocks based on said scanning position signal.