Patent ID: 8223560
Filing Date: 2012-07-17
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region, electrons flow through the channel region between the source region and the drain region; an electrically insulating layer adjacent to the source region, drain region and channel region; a floating gate element adjacent to the electrically insulating layer, the electrically insulating layer separates the floating gate element from the channel region; a control gate electrode adjacent to the floating gate element, the floating gate element separates the control gate electrode from the electrically insulating layer, the channel region, electrically insulating layer, floating gate element and control gate electrode being stacked in a vertical direction; and a plurality of magnetic particles having a particle size in a range from 1 to 6 nanometers within the channel region.