Patent ID: 7354822
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A method of fabricating a DRAM cell comprising the steps of: forming a deep trench capacitor within a substrate, said deep trench being partially filled with polysilicon and topped by a trench top oxide; forming a vertical transistor by diffusing a drain adjoining to the outer surface of said deep trench and contiguous to said trench top oxide; forming said vertical transistor gate oxide on the walls of said deep trench; filling the upper portion of said deep trench with a first gate material to a first height of said deep trench, and a second gate material on top of said first gate material, said second gate material only partially filling said deep trench to a second height of said deep trench, said first and second heights being less than the total depth of said deep trench; forming spacers on the exposed walls of said deep trench; filling the remainder of said deep trench contacting said second gate material with conductive material, an uppermost gate material being surrounded by said spacers; and successively implanting into said substrate a buried plate, a well, and a transistor source.