Patent ID: 6721225
Filing Date: 2004-04-13
Classification: G11C

Abstract:
A semiconductor memory device having an active state wherein data can be read and written and a standby state wherein the data are held, comprising:a memory cell array including a plurality of memory cells arranged in a matrix; a refresh controller which refreshes data stored in the plurality of memory cells; wherein said refresh controller comprises: a first refresh cycle generator which generates a first refresh cycle; a second refresh cycle generator which generates a second refresh cycle having a period shorter than the first refresh cycle; and a refresh processor which performs refresh operation when refresh operation becomes possible after the first refresh cycle is generated by said first refresh cycle generator and, when refresh operation is not performed for a period longer than the first refresh cycle generated by said first refresh cycle generator, performs refresh operations successively based on the second refresh cycle generated by said second refresh cycle generator in the longer period or after the end of the longer period.