Patent ID: 9159392
Filing Date: 2015-10-13
Classification: G11C,H01L

Abstract:
1. A memory subsystem, comprising: a semiconductor material of a first type; a plurality of arrays of memory cells formed over semiconductor material of the first type and comprising a first array of memory cells and a last array of memory cells; a plurality of sets of local word line drivers formed using the semiconductor material of the first type, each of the local word line drivers being formed between respective adjacent ones of the plurality of arrays of memory cells, each of the local word line drivers in each set being coupled to a respective one of a plurality of word lines extending through the plurality of arrays of memory cells, each of the local word line drivers including at least one transistor, all of the transistors in the local word line drivers being of a first type; a well of semiconductor material of the second type formed in the semiconductor material of the first type; and a plurality of global word line drivers formed using the well of semiconductor material of the second type, each of the plurality of global word line drivers being coupled to a respective one of the plurality of word lines extending through the plurality of arrays of memory cells, each of the plurality of global word line drivers including at least one transistor of the second type formed using the well of semiconductor material of the second type.