Patent ID: 7836362
Filing Date: 2010-11-16
Classification: G11C

Abstract:
1. A device comprising: a plurality of supply paths coupled to a supply node; a plurality of memory segments, each of the memory segments being coupled to the supply node via one of the supply paths; a plurality of switching units, each of the switching units being coupled to one of the supply paths and to a corresponding memory segment, the corresponding memory segment being one of the memory segments, wherein each of the switching units includes an enable mode for coupling the corresponding memory segment to the supply node, and a disable mode for decoupling the corresponding memory segment from the supply node, and wherein each of the switching units includes a transistor having a first terminal directly coupled to at least one memory cell included in one of the memory segments, a second terminal directly coupled to the supply node, and a gate to receive a signal; and at least one redundant segment for replacing at least one memory segment of the plurality of memory segments.