Patent ID: 7062690
Filing Date: 2006-06-13
Classification: G01R,G11C

Abstract:
1. A system for testing a fast synchronous digital circuit with an external test device outputting signal conditions on a signal path, comprising: a semiconductor chip for transmitting test signals, including at least one of test data, control, address, and clock signals, to a circuit to be tested, the test system evaluating response signals generated by the circuit to be tested based upon the test signals, said semiconductor chip being implemented as a single chip separate from said test device and said circuit to be tested and inserted into a signal path between the test device and the circuit to be tested, said semiconductor chip having: means for generating the test signals for the circuit to be tested, said generating means connected to said receiving means; means for sending the test signals to the circuit to be tested and for receiving the response signals generated by the circuit to be tested, said sending means connected to said generating means; means for switching said semiconductor chip between two operating modes as a function of switching criteria, said two operating modes including: said switching means connected to the test device, to said receiving means, and to said generating means, said switching means being programmed to switch said semiconductor chip into said programming mode only within certain periods when said semiconductor chip is not accessing any of said registers of said register unit for generating test signals, and the test device being adapted to calculate said certain periods for switching said switching means to said programming mode, once, and to store said certain periods in storage means of said test device.