Patent ID: 6201416
Filing Date: 2001-03-13
Classification: H03K

Abstract:
A field effect transistor logic circuit having an output terminal to be connected to a gate of an input field transistor in a next stage field effect transistor logic circuit, the field effect transistor logic circuit including a depletion transistor having a drain connected to a first power supply voltage, an enhancement transistor having a drain connected at a node to a source of the depletion transistor, a gate of said enhancement transistor being connected to an input terminal, a source of said enhancement transistor being connected to a second power supply voltage which is lower than the first power supply voltage, and a high level potential limiting circuit connected between said node and said output terminal, for lowering a potential of said output terminal to a level which turns on a drain-source channel of said input field effect transistor of said next stage field effect transistor logic circuit but which never turns on a gate-source of said input field effect transistor of said next stage field effect transistor logic circuit, when the potential on said node is at a high level and a lower level lowering circuit connected between said output terminal and said second power supply voltage, and having an input connected to said input terminal, for pulling down the potential of said output terminal to the potential of the second power supply voltage when the potential on said node is at a low level.