Patent ID: 8609488
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A method of forming a vertical transistor and at least a conductive line electrically coupled therewith, comprising: forming trenches in semiconductive material, the semiconductive material between the trenches comprising an elevationally outer source/drain portion and an elevationally mid-channel portion there-below; forming masking material laterally over at least elevationally inner sidewall portions of the trenches; ion implanting conductivity modifying impurity through bases of the trenches into semiconductive material there-below; diffusing the impurity into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below the mid-channel portion, and forming an elevationally inner source/drain below the mid-channel portion, the inner source/drain comprising said semiconductive material between the trenches which has the impurity therein; forming a conductive line laterally over and electrically coupled to at least one of opposing sides of the inner source/drain; and forming a gate elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion, a gate dielectric being provided laterally between the gate and the mid-channel portion.