Patent ID: 9104526
Filing Date: 2015-08-11
Classification: G06F,G11C

Abstract:
1. A transaction splitting apparatus, comprising: a hardware processor to control one or more processor-executable units: a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory; and a second processing unit to translate an address of the at least one sub-transaction to interleave the at least one sub-transaction by accessing different banks of the plurality of banks, wherein the at least one sub-transaction accesses the different banks of the plurality of banks consecutively, and wherein the first processing unit splits, into the at least one sub-transaction, commands that are associated with addresses of which a most significant bit (MSB) through an (L plus W plus 1)-th bit from a least significant bit (LSB) are the same, when the at least one sub-transaction has a maximum burst length of 2