Patent ID: 6442061
Filing Date: 2002-08-27
Classification: G11C,H01L

Abstract:
A memory cell, comprising:a first bit line, a second bit line, a first state node, a second state node, a memory cell enable line, a ground line, a first pass gate transistor having a gate oxide with a first thickness, the first pass gate transistor having a source electrically connected to the first bit line, a drain electrically connected to the first state node, and a gate electrically connected to the memory cell enable line, a second pass gate transistor having a gate oxide with the first thickness, the a second pass gate transistor having a source electrically connected to the second bit line, a drain electrically connected to the second state node, and a gate electrically connected to the memory cell enable line, a first state node transistor having a gate oxide with a second thickness, wherein the first thickness is greater than the second thickness, the first state node transistor having a source electrically connected to the ground line, and a gate electrically connected to the second state node, and a second state node transistor having a gate oxide with the second thickness, the second state node transistor having a source electrically connected to the second state node, a drain electrically connected to the ground line, and a gate electrically connected to the first state node.