Patent ID: 6087870
Filing Date: 2000-07-11
Classification: H03K

Abstract:
An output circuit comprising:a timing signal output circuit producing a timing signal;a delay circuit receiving said timing signal supplied from said timing signal output circuit, and generating a delay signal which is obtained by delaying said timing signal for a predetermined period of time; anda bus signal output means receiving said timing signal supplied from said timing signal output circuit and said delay signal supplied from said delay circuit;wherein said bus signal output means comprises:a logic circuit, receiving said timing signal and said delay signal, for outputting a signal for enabling the use of a bus when said timing signal is asserted and outputting a signal for disabling the use of said bus when said delay signal is asserted; anda bus buffer, receiving said signal for enabling the use of a bus supplied from said logic circuit, for outputting data while said logic circuit outputs said signal for enabling the use of a bus.