Patent ID: 7266015
Filing Date: 2007-09-04
Classification: G11C

Abstract:
1. A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, comprising the steps of: detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell, said charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, said charge gain detecting reference cell having a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell; and subjecting to a redundancy substitution a memory cell whose tendency of the charge loss and/or the charge gain is detected.