Patent ID: 8237288
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. An integrated circuit chip comprising: a through silicon via (TSV) formed through a semiconductor substrate; a first end of the TSV connected to a first metallization layer on a device side of the semiconductor substrate; a contact grid formed in the first metallization layer, the contact grid comprising a pattern of intersecting metal lines covering the first end of the TSV; at least one other metal line in the first metallization layer connected to the contact grid such that current can pass between the TSV and the at least one other metal line by way of the contact grid; a second end of the TSV connected to a second metallization layer on a grind side of the semiconductor substrate; a first flat edge on a cross-section of the first end at the intersection of the first end and the first metallization layer, wherein the first flat edge and the contact grid are positioned such that a metal line from the contact grid runs parallel to and contacts an entire length of the first flat edge and overlaps the first flat edge by at least one and one-half times a thickness of the metal line; and a second flat edge on a cross-section of the second end at the intersection of the second end and the second metallization layer.