Patent ID: 6775716
Filing Date: 2004-08-10
Classification: G06F,Y02D

Abstract:
A high-performance DMA controller which is a data transfer controller for controlling data transfer between a main storage means holding various kinds of data, and a plurality of local storage means, said data transfer controller comprising:an interface for generating a control signal for controlling the main storage means; a data I/O unit for controlling input and output of data; a parameter holding unit for holding various kinds of parameters that are required for execution of data transfer; a data transfer request receiver for receiving requests of data transfer; and a start command receiver for receiving a start/stop command of the data transfer controller; wherein said data transfer request receiver receives, from a data transfer request source, reservations of plural data transfer requests comprising execution priority information and local storage means type information, each information being arbitrarily set by the data transfer request source, and holds the local storage means type information in association with each execution priority information; and said data transfer controller receives only the reservations of data transfer requests until a start command is issued from a system controller for controlling the whole apparatus and, when a start command is issued from the system controller, the data transfer controller sequentially decodes the local storage means type information of the reserved data transfer requests having relatively high execution priorities, in chronological order of the data transfer requests, and then sequentially takes parameters required for data transfer from the parameter holding unit according to the decoding result, to execute data transfer.