Patent ID: 6408426
Filing Date: 2002-06-18
Classification: G06F

Abstract:
A method for determining locations of interconnect repeater farms in an integrated circuit design, said design defined by a netlist defining a layout of said integrated circuit and a routing list defining a list of interconnect nets associated with said layout, said method comprising the steps of:calculating optimal unconstrained repeater locations for each net in said routing list; defining a set of repeater farms to areas of concentration of said optimal unconstrained repeater locations; calculating optimal constrained repeater locations for each net in said routing list wherein said optimal constrained repeater locations are constrained to said defined repeater farms; selecting a set of sub-optimal nets from said routing list that are hurt the most in terms of a set of performance criteria when constrained to said repeater farms; calculating the optimal unconstrained repeater locations for said selected set of sub-optimal nets; and defining additional repeater farms to areas of concentration of said calculated optimal unconstrained repeater locations of said sub-optimal nets.