Patent ID: 6330189
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array having a matrix arrangement of electrically rewritable memory cells which form a plurality of memory cell units each including a plurality of said memory cells;a decode circuit for decoding an address and selecting a memory cell of said memory cell array;a sense amplifier circuit for detecting read-out data from said memory cell array and latching write data to said memory cell array;a read-out control means for reading out data from a memory cell selected from a memory cell unit selected by said decode circuit;a write control means for writing data in a memory cell selected from a memory cell unit selected by said decode circuit by applying a write voltage thereto; anda write verify read-out control means for reading out data from a selected memory cell in order to confirm the status of data writing by said write control means, under a bias condition ensuring a larger memory cell current to flow in its conductive status than that during data read-out operation by said read-out control means.