Patent ID: 8030634
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A memory array, comprising: a structure, including dielectric fill material and having conductive lines at a lower portion thereof; a plurality of diodes, each diode in the plurality of diodes having a first semiconductor layer having a first conductivity type, coupled to a corresponding conductive line in the structure, a second semiconductor layer having a second conductivity type, and a contact surface over the second semiconductor layer; vias in the dielectric fill material, and aligned with and overlying respective diodes on the plurality of diodes; spacers on interior sidewalls of the vias in contact with respective diodes, each spacer defining a self-centered opening in the center of the via exposing the contact surface of the respective diode, wherein the variability in width among the self-centered openings is less than the variability in width among the plurality of vias; memory material within the self-centered openings upward from the contact surface of the respective diodes, the memory material making contact with the contact surface; and a top electrode in contact with the memory material.