Patent ID: 6403484
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of forming shallow trench isolation regions in the manufacture of an integrated circuit device comprising:depositing a first etch stop layer on the surface of a semiconductor substrate; etching a plurality of isolation trenches through said first etch stop layer into said semiconductor substrate; depositing an oxide layer over said first etch stop layer and within said isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after said oxide layer fills said isolation trenches, said deposition component is discontinued while continuing said sputtering component until corners of said first etch stop layer are exposed at edges of said isolation trenches whereby said oxide layer within said isolation trenches is disconnected from said oxide layer overlying said first etch stop layer; thereafter depositing a second etch stop layer overlying said oxide layer within said isolation trenches, said oxide layer overlying said first etch stop layer, and exposed said first etch stop layer corners; polishing away said second etch stop layer until said oxide layer overlying said first etch stop layer is exposed; removing exposed said oxide layer overlying said first etch stop layer wherein said second etch stop layer protects said oxide layer within said isolation trenches during said removing; and removing said first and second etch stop layers to complete planarized said shallow trench isolation regions in said manufacture of said integrated circuit device.