Patent ID: 9171735
Filing Date: 2015-10-27
Classification: G03F,H01L

Abstract:
1. A method for fabricating a semiconductor integrated circuit comprising: providing a semiconductor substrate with an overlying process layer; determining a required trench pattern to be etched into the process layer, wherein the required trench pattern comprises three or more trenches; decomposing the required trench pattern into a first pattern and a second pattern, the second pattern including an isolated trench positioned between trenches of the first pattern and further including a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench, wherein the isolated trench is a portion of the required trench pattern and the plurality of density balancer patterns correspond to a plurality of dummy features different than the required trench pattern; generating a first lithographic mask implementing the first pattern and a second lithographic mask implementing the second pattern including the isolated trench and the density balancer patterns; patterning a first resist layer overlying the process layer with the first lithographic mask and etching the process layer with the patterned first resist layer as an etch mask; and patterning a second resist layer overlying the process layer with the second lithographic mask and etching the process layer with the patterned second resist layer as an etch mask to implement the isolated trench of the required trench pattern in the process layer, wherein the plurality of dummy features are produced in the process layer from the plurality of density balancer patterns.