Patent ID: 6246634
Filing Date: 2001-06-12
Classification: G11C

Abstract:
An integrated memory circuit comprising:a first array of non-volatile memory cells;a second array of volatile memory cells;a first address bus for carrying a first address signal, internal to said circuit, said first address bus, coupled to receive an externally supplied address signal;a second address bus for carrying a second address signal, internal to said circuit;a first data bus for carrying a first data signal, internal to said circuit, said first data bus, coupled to receive an externally supplied data signal;a second data bus for carrying a second data signal, internal to said circuit;each of said first and second arrays of memory cells further comprising an access circuit for connecting said array of memory cells to said first address bus or said second address bus, and for connecting said array of memory cells to said first data bus or said second data bus; anda control circuit responsive to said externally supplied data signal and to said externally supplied address signal for transferring data from said first array of non-volatile memory cells to said second array of volatile memory cells along said second data bus.