Patent ID: 6670251
Filing Date: 2003-12-30
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising steps of:(a) forming a gate electrode of a metal-insulator-semiconductor field-effect transistor over a main surface of a semiconductor body; (b) after said step (a), introducing an impurity in said semiconductor body to form a first semiconductor region of n-type conductivity serving as a source or drain region of said metal-insulator-semiconductor field-effect transistor; (c) after said step (b), forming a side wall spacer on said surfaces of said gate electrode; (d) after said step (c), introducing arsenic in said first semiconductor region to form a shallow high concentration region of said first conductivity type; (e) after said step (c), introducing phosphorus in said first semiconductor region to form a deep low concentration region of said first conductivity type; (f) after said steps (d) and (e), forming a cobalt layer over said shallow high concentration region and said main surface; (g) after step (f), performing heat treatment to form a cobalt suicide layer on said shallow high concentration region; and (h) after step (g), removing unreacted cobalt of said cobalt layer, wherein a junction depth of said shallow high concentration region is greater than a junction depth of said deep low concentration region, and wherein a dose amount of the arsenic is greater than a dose amount of the phosphorus, such that an impurity concentration of said shallow high concentration region is greater than an impurity concentration of said deep low concentration region.