Patent ID: 7749897
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising a wiring structure formed using a dual damascene process, comprising; sequentially forming a first interlayer insulation film and a second interlayer insulation film, at least one of the first and second interlayer insulation films being made of a low dielectric constant material; forming a first silicon oxide film by CVD using SiH forming a first antireflection film containing nitrogen by CVD; forming a first chemically amplified resist film to cover the first silicon oxide film; forming a pattern of an opening in a position over the first chemically amplified resist film; forming a via hole to extend through the first silicon oxide film, the first interlayer insulation film, and the second interlayer insulation film, while using the pattern formed over the first chemically amplified resist film as a mask; filling the via hole with a filler; forming a second silicon oxide film by CVD using SiH forming a second antireflection film containing nitrogen by CVD; forming a second chemically amplified resist film to cover the second antireflection film; forming a pattern of a wiring groove in an area of the second chemically amplified resist film including the via hole; forming the wiring groove by etching the second interlayer insulation film while using the second chemically amplified resist film as a mask; and filling the via hole and the wiring groove with a conductive material.