Patent ID: 6177824
Filing Date: 2001-01-23
Classification: H03K

Abstract:
A level shifting circuit for a semiconductor device, comprising:a first input port configured to receive a voltage mode selection signal, the voltage mode selection signal being set to one of a first logic level and a second logic level;a second input port configured to receive a bias voltage, the bias voltage being set to one of a power supply voltage and a transistor threshold voltage;a third input port configured to receive a charge pump voltage, the charge pump voltage being set to one of a predetermined negative voltage and a ground voltage;a fourth input port configured to receive an input signal, the input signal being set to one of the first logic level and the second logic level;a first pair of transistors of a first conductivity type;back gate control means which controls back gates of the first pair of transistors, the back gate control means receiving the input signal and the voltage mode selection signal;a second pair of transistors of a second conductivity type, the second pair of transistors connected in series with the first pair of transistors, respectively, and the second pair of transistors connected to receive the bias voltage; anda third pair of transistors of the second conductivity type, the third pair of transistors connected in series with the second pair of transistors, respectively, and the third pair of transistors connected to receive the charge pump voltage,wherein an output of the level shifting circuit is taken from a node that connects the one of the first pair of transistors with the one of the second pair of transistors.