Patent ID: 6680499
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate; an interlayer insulating film formed on said semiconductor substrate; a first electrode formed on said interlayer insulating film; a first ferroelectric film formed on said first electrode; a second electrode formed on said first ferroelectric film, the second electrode having an extension layer portion forming a first plate line layer, the first plate line layer connected to a first source/drain region of a first memory cell transistor via a first contact plug formed in the interlayer insulating film; a second ferroelectric film formed on said second electrode; a third electrode formed on said second ferroelectric film; a second plate line layer connected to said third electrode via a second contact plug and connected to a second source/drain region of a second memory cell transistor via a third contact plug; a first bit line layer connected to the first drain/source region via a fourth contact plug; and a second bit line layer connected to the second drain/source region via a fifth contact plug.