Patent ID: 8037356
Filing Date: 2011-10-11
Classification: G05B,G06F,H04L

Abstract:
1. A system for validating communications between a plurality of processors comprising: a plurality of loop back paths, wherein each of the loop back paths is coupled to a corresponding one of the plurality of processors, wherein each loop back path includes an attenuation element of a predetermined value, said attenuation elements configured to attenuate a one of aplurality of signals transmitted from each of the corresponding one of the plurality of processors by a predetermined amount so as to generate a plurality of attenuated loop back signals; a plurality of signal transmission paths, wherein each of the signal transmission paths is configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors; a plurality of data checkers, wherein each of the data checkers is configured to compare one of the plurality of attenuated loop back signals to a corresponding one of the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed; and a synchronization subsystem configured to time synchronize the data checkers so as to facilitate the comparing of the attenuated loop back signals and corresponding one of the plurality of transmission signals; wherein the predetermined value of the attenuation elements are selected so as to provide an attenuation with respect to the attenuation in the signal transmission paths from the ones of a plurality of processors to another of the plurality of processors so as to facilitate detection of a weak transmitter.