Patent ID: 9009420
Filing Date: 2015-04-14
Classification: G06F

Abstract:
1. A method in a computer aided design system for generating a functional design model of a mechanism for performing cacheline polling in a data processing system having a plurality of processes, said method comprising: generating a functional computer-simulated representation of a mechanism for requesting an action by a first process to be performed by a second process; generating a functional computer-simulated representation of a mechanism for executing a store and reserve (STAR) instruction that sets a Buffer Busy indicator within a memory location of a shared memory, initializes a state of a buffer data to be accessed, and stores a specific data value within a reservation register to reserve said memory location, wherein said reservation register is located within a level 2 cache; generating a functional computer-simulated representation of a mechanism for reading said memory location by said first process via a load operation to determine whether said requested action has been completed by said second process; generating a functional computer-simulated representation of a mechanism for stalling said load operation until said reservation on said memory location is lost; and generating a functional computer-simulated representation of a mechanism for in response to said requested action completing, resetting said reservation in said memory location by resetting said specific data value within said reservation register by said second process, wherein resetting said specific data value within said reservation register further comprises resetting a registration status bit within a condition register that corresponds to said specific data value.