Patent ID: 8890247
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming non-contiguous first conductivity type semiconductor regions entirely within a semiconductor base layer of a semiconductor-on-insulator substrate, wherein a gap comprising a semiconductor material portion of said semiconductor base layer is present between each non-contiguous first conductivity type semiconductor region, and wherein said semiconductor-on-insulator substrate further comprises at least one buried dielectric material layer located on a surface of the semiconductor base layer, and a semiconductor-on-insulator layer located on an uppermost surface of said at least one buried dielectric material layer; patterning said semiconductor-on-insulator layer forming at least one first active device region and a second active device region, wherein said first active device region is located above one of said non-contiguous first conductivity type semiconductor regions and said second active device region is located atop another of said non-contiguous first conductivity type semiconductor regions, and wherein said first and second active device regions are both vertically offset from said gap; forming a first transistor within said first active device region and a second transistor within said second active device region; forming an interconnect structure straddling each of said first and second transistors; and removing said semiconductor base layer of said semiconductor-on-insulator substrate stopping on a surface of each of said non-contiguous first conductivity type semiconductor regions and a surface of said at least one buried dielectric material layer.