Patent ID: 6030868
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other, comprising the steps of:forming a first polysilicon (poly I) layer on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells;forming an interpoly dielectric layer over the poly I layer;etching at least a portion of the interpoly dielectric layer to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer; andtransforming the exposed portion of the poly I layer into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell.