Patent ID: 6130546
Filing Date: 2000-10-10
Classification: G01R

Abstract:
Apparatus for testing an integrated circuit (IC) die having a pattern of die bumps located thereon comprising:a probe card having a probe card surface;a plurality of surface mount pads on the probe card surface arranged in a pattern substantially corresponding to the pattern of die bumps on the IC die;a plurality of electrical probes each having a top end and a bottom end;said plurality of electrical probes arranged in a pattern substantially corresponding to the pattern of the die bumps to be tested, each probe corresponding to a selected die bump;said plurality of electrical probes further arranged such that in use said top end is in mechanical and electrical contact with said surface mount pads on the probe card and said bottom end is in electrical contact with said die bumps on the IC die;a means for holding the probes together in the pattern;a plurality of test contacts located around the periphery of the probe card surface;means for electrically connecting each surface mount pad with a corresponding test contact; andan integrated circuit tester having a plurality of test channels, each test channel being electrically connected to a selected test contact of the probe card, thereby forming a continuous conductive path between the integrated circuit tester and the die bumps on the IC die.