Patent ID: 9159786
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate of a first conductivity; a first region of a second conductivity formed over the substrate; a body region of the first conductivity formed in the first region; an isolation region formed in the first region; a first drain region of the second conductivity formed in the first region, wherein the first drain region and the substrate are separated by the first region; a first source region of the second conductivity formed in the first region, wherein the first source region and the first drain region are formed on opposing sides of the isolation region; a second source region and a second drain region formed in the first region, wherein the second source region and the second drain region are formed on opposing sides of a second isolation region; a first dielectric layer formed over the first region in a gate trench; a first gate formed over the first dielectric layer in a gate structure, wherein the body region extends from a sidewall of the isolation region to a sidewall of the gate structure and a bottommost surface of the body region is higher than a bottommost surface of the isolation region; a second dielectric layer formed over the first gate; and a second gate formed over the second dielectric layer in the gate structure, wherein the second source region and the first source region are formed on opposing sides of the gate structure, and wherein a bottommost surface of the gate trench is level with a bottommost surface of the isolation region.