Patent ID: 8990125
Filing Date: 2015-03-24
Classification: G06F,G06K,G06N,G06Q,G06T,G09B,G10L,H04H,H04L,H04N,Y10S

Abstract:
1. An apparatus for generating a signature for an input signal, comprising: a processor; and a memory coupled to the processor and configured to store at least instructions causing for execution of a plurality of computational cores, wherein the instructions includes a plurality of subsets of instructions, each subset of instructions causes the execution of one computational core from the plurality of computational cores and is coded to have properties that have at least some statistical independency from other subset of instructions, thereby the properties are independent of each other computational core, wherein each subset of instructions causes its respective computational core to generate responsive of the input signal a first signature element and a second signature element, the first signature element is a robust signature; wherein a plurality of first signature elements include a first signature of the input signal and a plurality of second signature elements include a second signature of the input signal, the first signature is determined respective of a first threshold value and the second signature is determined respective of a second threshold, wherein the first threshold is higher than the second threshold.