Patent ID: 6920057
Filing Date: 2005-07-19
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of functional blocks, each of which is arranged as a certain lump of circuit functions; a signal line, arranged in a region of each of said functional blocks for exchanging a signal between each of said functional blocks and the outside; a common bus line which is provided on a region of said plurality of functional blocks and commonly for said plurality of blocks and which is connected to said signal line via a contact; wherein each of said functional blocks is a plurality of cores comprising a set of electrically rewritable nonvolatile memory cells, which further comprises a decoder circuit including a pre-decoder, attached to each of said cores, for decoding an address signal to select a core from said cores, and a row decoder and a column decoder for further decoding an output decode signal of said pre-decoder to select a matrix of each of said cores; and wherein said common bus line is provided over a region of said pre-decoder of each of said cores arranged in row directions.