Patent ID: 6397281
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A data storage system, comprising:(A) a plurality of control/data buses; (B) a memory section coupled to the plurality of control/data buses, such memory section, comprising: (i) a common memory region; (ii) a plurality of control logic sections interconnected through an arbitration bus, each one being coupled between a corresponding one of the control/data buses and the common memory region, each one of such control logic sections comprising: (a) a control logic for controlling transfer of data between the common memory region and the one of the plurality of control/data buses coupled to said one of the logic sections, such control logic producing a control/data bus request for the one of the control/data buses coupled thereto and for effecting the transfer in response to a control/data bus grant fed to the control logic; and (b) a bus arbitration section coupled to the arbitration bus for: (1) receiving a control/data bus request from the control logic in such one of the control logic sections and from the other control logic sections coupled to such arbitration bus; (2) for granting access to the control/data bus to one of the control logic sections in accordance with the bus requests coupled to the bus arbitration section; (3) for receiving control/data bus grants from the other control logic sections coupled to such arbitration bus; and (4) for distributing the control/data bus request produced by the control logic in said control logic section to the other control logic sections coupled to the arbitration bus.