Patent ID: 6144221
Filing Date: 2000-11-07
Classification: H03K

Abstract:
A interface circuit comprising:a terminal that supplies a first power source (Vdd) having a first potential;a terminal that supplies a second power source (Vss) having a second potential lower than the first potential;a first driver circuit (P8, N2) that receives a data signal input;a second driver circuit (P1, N1) and a first node (node a) connecting an output from the first driver circuit to an input of the second driver circuit;an input/output pad connected to an output of the second driver circuit;a first protection circuit (P2, P5) that sets the second driver circuit to an off state by setting the first node to a potential higher than the first potential in response to a potential higher than the first potential of the first power source being applied from an external source to the input/output pad;a second node (node b) and a second protection circuit (P2, P6, P7) that sets the first driver circuit (P8, N2) to an off state when a potential higher than the first potential of the first power source is applied from an external source to the input/output pad by setting the second node to a potential higher than the first potential, said second node connected between the terminal for supplying the first power source and the terminal for supplying the second power source; anda third protection circuit (N3) that controls a state of the first driver circuit (P8, N2) by setting the second node to the second potential when a potential substantially equal to the second power source is applied to the input/output pad from an external source.