Patent ID: 7557634
Filing Date: 2009-07-07
Classification: H03K

Abstract:
1. A low power CMOS driver circuit for power output, comprising: a plurality of terminals receiving one or more sequenced input low voltage control signals; a potential shifting circuit configured to receive at least two of the said low voltage control signals and issue high voltage output control signals; a high voltage output stage comprising a first control gate and a second control gate, wherein the first control gate is configured to receive at least one of the said low voltage control signals; and an output buffer circuit coupled to the output of the potential shifting circuit and the second control gate of the high voltage output stage, comprising one or more coupled output buffer cells, each output buffer cell comprising: wherein the said received input low voltage control signals are mutually independent and sequenced by low voltage drivers such that, when one of the P-channel and N-channel MOS transistors of the buffer or high voltage output stage is turned on, the other one of these transistors in the same stage is turned off to avoid any simultaneous conduction of these transistors, and wherein when one of the P-channel and N-channel MOS transistors of the last buffer is turned on, the same type transistor in the high voltage output stage is turned off.