Patent ID: 6673661
Filing Date: 2004-01-06
Classification: H01L

Abstract:
A method for fabricating a thin film transistor comprising:providing a planar substrate; forming over the planar substrate a topographic first gate electrode; forming upon the topographic first gate electrode a first gate dielectric layer; forming separated by the first gate electrode and the first gate dielectric layer a pair of source/drain layers; forming upon the pair of source/drain layers and the first gate dielectric layer a semiconductor channel layer which forms a recess with respect to the pair of source/drain layers; forming upon the semiconductor channel layer a second gate dielectric layer; and forming upon the second gate dielectric layer and also separating the pair of source/drain layers a second gate electrode, wherein: the pair of source/drain layers is formed in a self-aligned fashion with respect to the first gate electrode; and the second gate electrode is formed in a self-aligned fashion with respect to the pair of source/drain layers and the first gate electrode.