Patent ID: 8962482
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising: providing an insulating layer; forming a plurality of vias through the insulating layer, wherein forming the vias comprises masking the insulating layer using a photolithography reticle, with a first positive photoresist film and employing a first radiation exposure level, and etching unmasked areas of the insulating layer; forming a plurality of conductive plugs through the insulating layer, wherein forming the conductive plugs comprises filling the vias with a conductive material; depositing an isolation layer over the insulating layer and over the conductive plugs; after depositing the isolation layer, forming a plurality of openings through the isolation layer, wherein forming the openings comprises masking the isolation layer using the photography reticle, using a second positive photoresist film and employing a second radiation exposure level that is at least about 5% lower than the first radiation exposure level, and etching unmasked areas of the isolation layer, each opening exposing an upper surface of a corresponding one of the conductive plugs and having a width smaller than a corresponding width of the corresponding one of the conductive plugs; after etching to form the openings, filling the openings with a blanket metal layer comprising aluminum in direct contact with the conductive plugs; masking the metal layer with a third photoresist film on the metal layer; and etching the metal after depositing the third photoresist film on the metal layer to form an elongated conductive line, wherein the conductive plugs are formed at one level of a metallization scheme and the elongated conductive line is formed above two or more conductive plugs at a second level of the metallization scheme.