Patent ID: 7031190
Filing Date: 2006-04-18
Classification: G11C

Abstract:
1. A structure for testing a NAND flash memory, comprising: a first string select transistor for controlling transfer of a voltage inputted via a first bit line; a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto; a second string select transistor for controlling transfer of a voltage inputted via a second bit line; a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto; and a measurement pad connected to a point where the first or the second string select transistor and an adjacent flash memory cell are connected.