Patent ID: 6512299
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A semiconductor device comprising:a gate insulating film formed on a main surface of a silicon substrate having a deviceisolation region; a gate electrode comprising polycrystalline silicon; an LDD-MOSFET formed into the main surface of said silicon substrate along a first side of the gate electrode; a spacer formed on a second side of the gate electrode opposite the first side including said LDD-MOSFET; a high-density doped layer; a first metal silicide layer disposed on an upper surface of the gate electrode; a second metal silicide layer abutting the gate insulating film and disposed on an upper surface of the high-density doped layer to be in contact with the high-density doped layer along an entire length of a bottom segment of the second metal silicide layer; a common contact in physical contact with said first metal silicide layer and said second metal silicide layer for connecting both the gate electrode and the high-density doped layer to an upper wiring, wherein the gate electrode and the high-density doped layer are electrically connected to the upper wiring via the first and second metal silicide layers through a contact plug buried in the common contact, and wherein said common contact includes a metal barrier film disposed along peripheral edges of the common contact, wherein a bottom peripheral edge of the barrier film is in continuous contact with the second metal silicide layer.