Patent ID: 6040723
Filing Date: 2000-03-21
Classification: G06F

Abstract:
An interface circuit comprising:a clock signal generator outputting a clock signal and an inversion clock signal;a shift signal generator receiving a start signal, the clock signal and the inversion clock signal, and outputting shift signals having odd shift signals and even shift signals, the odd shift signals including a first odd shift signal and subsequent odd shift signals, wherein the first odd shift signal is generated in response to the start signal and the clock signal, wherein the even shift signals are generated in response to a previous one of the odd shift signals and the inversion clock signal, and wherein the subsequent odd shift signals are generated in response to a previous one of the even shift signals and the clock signal;a data distribution circuit receiving data, the clock signal and the inversion clock signal, said data distribution circuit outputting odd data in response to the data and the clock signal, and outputting even data in response to the data and the inversion clock signal;a plurality of odd data output circuits each of which receives the odd data and outputs the received data in response to one of the odd shift signals, respectively; anda plurality of even data output circuits each of which receives the even data and outputs the received data in response to one of the even shift signals, respectively.