Patent ID: 6118159
Filing Date: 2000-09-12
Classification: H01L

Abstract:
An electrically programmable memory cell configuration, comprising:a substrate having substantially parallel trenches formed therein, said trenches having bottoms, first flanks and second flanks opposite said first flanks;lower bit lines running along said bottoms of said trenches;upper bit lines disposed between and adjacent to respective neighboring two of said trenches;each of said lower bit lines and each of said upper bit lines having a first part and a second part disposed parallel and adjacent to said first part, said first part and said second part each having a dopant concentration, said dopant concentration of said second part being higher than said dopant concentration of said first part, said second part of each of said lower bit lines being disposed in a region of a respective one of said first flanks, said second part of each of said upper bit lines being disposed adjacent to a respective one of said second flanks;word lines disposed transversely with respect to said trenches in said substrate;vertical MOS transistors having channel regions and soure/drain regions, said source/drain regions each formed of one of a part of a respective one of said upper bit lines and a part of a respective one of said lower bit lines, respective two of said vertical MOS transistors disposed next to each other along a respective one of said word lines and sharing one of a respective one of said lower bit lines and a respective one of said upper bit lines;floating gate electrodes separated from each other and disposed on said first flanks and said second flanks;first dielectrics separating said floating gate electrodes from said channel regions of said vertical MOS transistors;control gate electrodes electrically connected to said word lines, said control gate electrodes being separated from each other and disposed next to each other along a respective one of said trenches; andsecond dielectrics separating said control gate electrodes from said floating gate electrodes.