Patent ID: 9166846
Filing Date: 2015-10-20
Classification: H04L

Abstract:
1. An eye diagram construction display apparatus applied to a data stream, the eye diagram construction display apparatus comprising: an amplifier receiving the data stream; a first equalizer electrically connected to the amplifier; an addition unit electrically connected to the first equalizer; a second equalizer electrically connected to the addition unit; a bit error rate check unit electrically connected to the addition unit; a clock recovery unit electrically connected to the addition unit and the bit error rate check unit; a clock synthesizer electrically connected to the clock recovery unit; a processing unit electrically connected to the addition unit, the bit error rate check unit and the clock recovery unit; and a display unit electrically connected to the processing unit, wherein the amplifier amplifies the data stream with a variable gain pattern to obtain an amplified data stream after the amplifier receives the data stream; the amplifier sends the amplified data stream to the first equalizer; the first equalizer processes the amplified data stream to obtain a first equalization signal after the first equalizer receives the amplified data stream; the first equalizer sends the first equalization signal to the addition unit; the second equalizer sends a second equalization signal to the addition unit; the addition unit adds the first equalization signal to the second equalization signal to obtain a totaling equalization signal after the addition unit receives the first equalization signal and the second equalization signal; the addition unit sends the totaling equalization signal to the bit error rate check unit, the clock recovery unit and the processing unit; the clock synthesizer sends a clock synthesis signal to the clock recovery unit; the clock recovery unit generates a clock recovery signal after the clock recovery unit receives the totaling equalization signal and the clock synthesis signal; the clock recovery unit sends the clock recovery signal to the bit error rate check unit and the processing unit; the bit error rate check unit checks a bit error rate of the totaling equalization signal to obtain a bit error rate signal after the bit error rate check unit receives the totaling equalization signal and the clock recovery signal; the bit error rate check unit sends the bit error rate signal to the processing unit; the processing unit is configured to process the totaling equalization signal, the clock recovery signal and the bit error rate signal to obtain an eye serial signal after the processing unit receives the totaling equalization signal, the clock recovery signal and the bit error rate signal; the eye serial signal comprises a plurality of eye signals; the processing unit fetches a middle eye signal of the eye serial signal and fetches two of a half of the eye signal at both sides of the middle eye signal to obtain an eye diagram signal; the processing unit is configured to process the eye diagram signal with histogram scanning, bilinear interpolation and bicubic interpolation; the processing unit amplifies the eye diagram signal; the processing unit sends the eye diagram signal to the display unit; the display unit displays a content of the eye diagram signal after the display unit receives the eye diagram signal.