Patent ID: 7002629
Filing Date: 2006-02-21
Classification: H04N

Abstract:
1. A charge coupled device (CCD) image detector comprising: an image area of an array of rows of gates, each gate of said image area array being operative to collect and store a charge content representative of a picture element (pixel) of an image, said rows of gates of the image area being operative concurrently by a first clock signal to transfer in parallel the charge contents of the gates of each row to the gates of an adjacent row in a predetermined direction through said image area; a storage area of an array of rows of gates, each gate of said storage area array being operative to store a charge content, said rows of gates of the storage area being operative concurrently by a second clock signal to transfer in parallel the charge contents of the gates of each row to the gates of an adjacent row in the predetermined direction through said storage area, said storage area array of rows disposed in said CCD detector such that a first row of said image area array of rows is adjacent a last row of said storage area array of rows to accommodate a transfer in parallel of the charge contents of the gates of said first row of the image area to the gates of said last row of the storage area, wherein the image and storage areas are operative by the first and second clock signals, respectively, to transfer the charge contents of the rows of the image area array to rows of the storage area array; a buffer area of an array of rows of gates, each gate of said buffer area array being operative to store a charge content, said rows of gates of the buffer area being operative concurrently by a third clock signal to transfer in parallel the charge contents of the gates of each row to the gates of an adjacent row in the predetermined direction through said buffer area, said buffer area array of rows disposed in said CCD detector such that a first row of said storage area array of rows is adjacent a last row of said buffer area array of rows to accommodate a transfer in parallel of the charge contents of the gates of said first row of the storage area to the gates of said last row of the buffer area, wherein the storage and buffer areas are operative by the second and third clock signals, respectively, to transfer the charge contents of the rows of the storage area array to rows of the buffer area array; a readout register of a row of gates, each gate of said readout register being operative to store a charge content, said readout register disposed in said CCD detector such that a first row of said buffer area array of rows is adjacent the row of said readout register to accommodate a transfer in parallel of the charge contents of the gates of said first row of the buffer area to the gates of said readout register as controlled solely by the third clock signal, said row of gates of the readout register being operative concurrently by a fourth clock signal to transfer serially the charge contents of the gates thereof through said register in a predetermined direction to an output signal line; and a timing controller operative to perform the following tasks: