Patent ID: 7116570
Filing Date: 2006-10-03
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode column address signals applied to the external address terminals; a plurality of memory cell arrays each operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals, each of the memory cell arrays being fabricated in a respective array well formed in a semiconductor substrate and isolated from each other; a data path circuit operable to couple data signals corresponding to the data between each of the arrays and external data terminals of the memory device; a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals; a plurality of access circuits each of which selectively couples a predetermined one of the external terminals to a respective one of the array wells, each of the access circuits comprising: