Patent ID: 6265916
Filing Date: 2001-07-24
Classification: H03L

Abstract:
A clock multiplier circuit for generating a high frequency clock signal having small jitters from a low frequency input clock, said clock multiplier circuit comprising:a counter for counting the number of pulses of a predetermined output clock signal;an expected value generating circuit for generating an expected value for the number of pulses of said predetermined output clock signal per a first period which is longer than one period of said predetermined output clock signal;a comparator circuit for comparing a counted value of said counter with said expected value per said first period to output a comparative information on the comparative result;a delay control circuit for generating a delay control signal indicative of change of a frequency of said predetermine output clock signal in accordance with said comparative information; andan output clock signal generating circuit operative in digital from and at least including a delay element for generating said predetermined output clock signal through an output node thereof by changing the frequency in accordance with said delay control signal, and an output-stopping logic element for stopping a generation of said predetermined output clock signal and having two inputs and one output, one input of which is connected to said output node of said delay element and the other input of which receives an enable signal, and the output of which is connected to an input node of said delay element.