Patent ID: 6461959
Filing Date: 2002-10-08
Classification: H01L

Abstract:
A method for fabricating contact plugs of an embedded memory, the method comprising:providing a semiconductor wafer with both a memory array region and a periphery circuit region defined on a surface of a silicon substrate of the semiconductor wafer; forming a first dielectric layer and an undoped polysilicon layer in sequence on the surface of the semiconductor wafer; performing a first ion implantation process on the undoped polysilicon layer in the memory array region to transform the undoped polysilicon layer in the memory array region to a doped polysilicon layer; forming a passivation layer and a first photoresist layer in sequence on the surface of the semiconductor wafer; performing a first photolithographic process to define a plurality of gate patterns in the first photoresist layer in the memory array region; using the gate patterns of the first photoresist layer as a hard mask to etch the passivation layer and the doped polysilicon layer located in the memory array region down to a surface of the first dielectric layer to form gates in the memory array region; removing the first photoresist layer; performing a first ion implantation process to form a lightly doped drain (LDD) adjacent to each gate in the memory array region; forming a silicon nitride layer, a second dielectric layer, and a second photoresist layer in sequence on the surface of the semiconductor wafer; performing a second photolithographic process to define a plurality of contact plug patterns in the second photoresist layer in the memory array region; using the contact plug patterns of the second photoresist layer as a hard mask to etch the second dielectric layer, the silicon nitride layer, and the first dielectric layer located in the memory array region down to the surface of the silicon substrate to form a plurality of contact plug holes in the second dielectric layer; removing the second photoresist layer; filling each contact plug hole with a polysilicon layer to form each contact plug in the memory array region; removing the second dielectric layer, the silicon nitride layer and the passivation layer in the periphery circuit region; forming a third photoresist layer on the surface of the semiconductor wafer; performing a third photolithographic process to define a plurality of gate patterns in the third photoresist layer in the periphery circuit region; using the gate patterns of the third photoresist layer as a hard mask to etch the undoped polysilicon layer located in the periphery circuit region down to the surface of the first dielectric layer to form gates in the periphery circuit region; removing the third photoresist layer; in the periphery circuit region, forming an LDD adjacent to each gate, and a spacer on the walls of each gate; forming a source and a drain adjacent to each gate in the periphery circuit region; and performing a self-aligned silicide (salicide) process to form a metal silicide layer on a top surface of each contact plug, on a top surface of each gate, and on a surface of each source and drain in the periphery circuit region.