Patent ID: 6332152
Filing Date: 2001-12-18
Classification: G06F,H03M

Abstract:
An arithmetic unit comprising: a comparator circuit which takes as inputs first data as comparison reference data and second data as data to be compared with said first data, and performs a comparison between said first and said second data, and which, when said first and said second data match as the result of said comparison, outputs a value 1 and sets a match signal active, and when said first and said second data do not match, outputs said second data and sets said match signal inactive; a shifter to which an output of said comparator circuit is input, and which shifts, or does not shift, the output of said comparator circuit, depending on the state of said match signal supplied from said comparator circuit; an adder circuit which accepts an output of said shifter at one input thereof; a register to which an output of said adder circuit is input; and a selection circuit which accepts a value 0 at one input thereof and an output of said register at the other input, and which couples one or the other of said inputs to the other input of said adder circuit in accordance with a selection signal, and wherein:with said selection circuit selecting either said value 0 or the output of said register in accordance with said selection signal, when said first and said second data do not match, said second data that does not match said first data is output by being paired with a count of the number of times that said second data matched said first data since the last occurrence of a mismatch between said first and said second data.