Patent ID: 7916556
Filing Date: 2011-03-29
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line; wherein the sense amplifier circuit includes a differential sense amplifier having first and second differential inputs and whose second differential input is supplied with a reference voltage, a pull-up section adapted to pull up the first differential input to a constant voltage, a read gate transistor connected between the sense line and the first differential input, and adapted to turn on if the sense line potential drops below an initial voltage in response to a cell current, and a threshold correction section adapted to generate a voltage corrected from the initial voltage by making or breaking a diode connection of a given transistor, the impact of whose threshold voltage on the sense line potential is to be eliminated, and also adapted to apply the corrected voltage to the control terminal of the read gate transistor.