Patent ID: 6097230
Filing Date: 2000-08-01
Classification: H03K

Abstract:
An integrated D-type latch/D-type flip-flop circuit, comprising:an input terminal and an output terminal for the conduction of data signals;first and second storage circuits interposed between said input and output terminals for the storage of said data signals, and each connected to receive a first and second set of complementary signals at respective control terminals thereof; wherein each set of said complementary signals are derived independently of one another;a first inverter circuit interposed between said input terminal and said first storage circuit, and connected to receive said first set of complementary signals at respective control terminals thereof;a second inverter circuit interposed between said first storage circuit and said second storage circuit, and connected to receive said first and second set of complementary signals at respective control terminals thereof; andfirst and second control circuits; wherein said first control circuit is operatively connected between said input terminal and said first storage circuit, and in parallel with said first inverter circuit; wherein said second control circuit is operatively connected between said input terminal and said second storage circuit, and said input terminal and said output terminal; wherein the propagation time delay of a data signal from said input terminal to said first storage circuit via the first control circuit most nearly approximates the propagation time delay of a data signal from said input terminal to said second storage circuit via the second control circuit;whereby said second set of complementary signals are independent of the state of said first set of complementary signals.