Patent ID: 6037206
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method for fabricating a capacitor of a dynamic random access memory (DRAM), the method comprisingproviding a substrate, wherein a field effect transistor comprising a gate and two interchangeable source/drain regions is formed on the substrate,forming an insulating layer over the substrate;patterning the insulating layer to form a contact window which exposes one of the interchangeable source/drain regions;forming a first conductive layer over the insulating layer with the contact window being filled so that the first conductive layer is electrically coupled to said one of the interchangeable source/drain regions through the contact window;forming a patterned photoresist layer over the first conductive layer;performing an etching process using a plasma ion source with high ion energy, low pressure and high density and the patterned photoresist layer as a mask to define the first conductive layer so that an opening through the first conductive layer and the patterned photoresist layer is formed to expose the insulating layer and a fence-like plate is formed around a periphery of the opening;after removing the patterned photoresist layer, forming a second conductive layer to cover the fence-like plate and the first conductive layer, wherein the second conductive layer and the fence-like plate together form a sharp upper end;performing an etching back process so that the sharp upper end is rounded and a plurality of capacitor areas are formed;forming a dielectric thin film over the substrate; andforming a third conductive layer over the dielectric thin film to act as an upper electrode.