Patent ID: 8769461
Filing Date: 2014-07-01
Classification: G06F

Abstract:
1. A method of processing a circuit design for implementation on a target device, comprising: for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver; on a programmed processor generating in a memory, a representation of a rectilinear Steiner arborescence (RSA) tree from the second driver and the plurality of loads, the RSA tree including nodes representative of the plurality of loads and a plurality of Steiner points; selecting a subset of the plurality of Steiner points in the RSA tree; wherein the selecting the subset of the plurality of Steiner points includes forming a plurality of clusters from the plurality of loads and Steiner points, for each cluster the forming includes adding one or more loads and one or more Steiner points to the cluster until a cost of the cluster satisfies a threshold, the cost is a function of a number of the one or more loads in the cluster and a total wire length between a Steiner point last added to the cluster and the one or more loads, and the Steiner point last added to the cluster is selected for the subset; assigning respective replicated instances of the first driver to locations on the target device associated with the subset of Steiner points; and assigning connections from each of the respective replicated instances of the first driver to a respective subset of the plurality of loads.