Patent ID: 8223654
Filing Date: 2012-07-17
Classification: H04L

Abstract:
1. An application-specific integrated circuit for use in optimizing a packet network, the application-specific integrated circuit comprising: a processing unit that executes instructions; a memory that stores said instructions; an internal data bus; an input/output (I/O) interface arranged between said internal data bus and at least one external network device for communicating data packets containing network performance information between said internal data bus and said at least one external network device; a first data path line in communication with said processing unit designated for communicating only packets that include real-time data content, wherein the first data path line in communication with said processing unit is coupled to a first network interface port that is designated for receiving only packets that include real-time data content; a second data path line in communication with said processing unit designated for communicating only packets that do not include real-time data content, wherein the second data path line in communication with said processing unit is coupled to a second network interface port that is designated for receiving only packets that do not include real-time data content; a third data path line in communication with said processing unit designated for communicating only packets that include real-time data content, wherein the a third data path line in communication with said processing unit is coupled to a third network interface port that is designated for transmitting only packets that include real-time data content; and a fourth data path line in communication with said processing unit designated for communicating only packets that do not include real-time data content, wherein the fourth data path line in communication with said processing unit is coupled to a fourth network interface port that is designated for transmitting only packets that do not include real-time data content.