Patent ID: 7549022
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. A system for providing hardware access to a plurality of guest operating systems, comprising: a memory; a cache comprising at least two cache lines, wherein each cache line is associated with a plurality of memory pages that are spaced at a noncontiguous, regular interval; at least one guest; a host configured to assign a plurality of memory pages used by said plurality of guest operating systems; wherein said memory pages of said plurality of guest operating systems are spaced at said noncontiguous, regular interval, so that all memory pages used by one of said plurality of guest operating systems are associated with a first restricted subset of said at least two cache lines; and at least one processor, wherein a context switch can be performed to allow at least one second guest to execute on said at least one processor, and wherein said host is configured to assign a cache line other than the restricted subset of cache lines to said second guest associated with a separate set of memory pages spaced at said noncontiguous, regular interval for use by said second guest.