Patent ID: 6589834
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A method of forming a dynamic random access memory (DRAM) integrated circuit structure, the method comprising:providing a p-type semiconductor substrate; forming a first n-type well in the semiconductor substrate to define a first pn junction between the first n-type well and the p-type semiconductor substrate, the first n-type well having a first dopant concentration; forming a second n-type well in the semiconductor substrate that is spaced apart from the first n-type well, the second n-type well defining a second pn junction between the second n-type well and the p-type semiconductor substrate, the second n-type well having a dopant concentration that is greater than the first dopant concentration of the first n-type well; forming a p-type well in the first n-type well to define a third pn junction between the p-type well and the first n-type well; forming a plurality of DRAM storage cells comprising a DRAM storage cell array directly in the p-type semiconductor substrate; and forming a plurality p-type transistors in the second n-type well and a plurality of n-type transistors in the p-type well.