Patent ID: 7666740
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A method for manufacturing a nonvolatile semiconductor memory device comprising: sequentially forming a first oxide layer, a first poly-silicon layer, and a first insulation layer on a semiconductor substrate; implanting a dopant into the semiconductor substrate, which is exposed by an etching process performed using a photoresist pattern provided on the first insulation layer, to form source/drain regions; performing a re-oxidation process to form a second oxide layer on the source/drain regions; forming first spacers on the second oxide layer at opposite sides of the second oxide layer; filling a second insulation layer between the neighboring first spacers, and removing the second insulation layer on the source regions; forming source lines on the respective source regions from which the second insulation layer was removed; forming second spacers to come into contact with the respective first spacers after removing the first insulation layer; forming an upper silicon oxide layer on the source lines and forming a lower silicon oxide layer on an underside between the neighboring second spacers; forming control gates between the neighboring second spacers; performing a salicide process to reduce a resistance of the control gates; forming a poly metal dielectric (PMD) layer covering the control gates, and planarizing the PMD layer by a chemical mechanical polishing (CMP) process; and filling an electrically conductive material in a plurality of contact holes perforated through the PMD layer and the second insulation layer, to form contacts.