Patent ID: 6245689
Filing Date: 2001-06-12
Classification: H01L

Abstract:
An integrated circuit manufacturing process for making a thin dielectric layer on an exposed clean surface of a silicon substrate, comprising the steps of:installing said silicon substrate in an annealing chamber;providing a first ambient pressure of nitric oxide gas in said annealing chamber;annealing said substrate at a first elevated temperature for a first period of time;removing said nitric oxide gas from said annealing chamber;providing a second ambient pressure of oxidizing gas in said annealing chamber;annealing said substrate at a second elevated temperature for a second period of time;said thin dielectric layer comprising a silicon oxynitride (SiO.sub.x N.sub.y) dielectric layer on said exposed clean surface of said silicon substrate, said SiO.sub.x N.sub.y dielectric layer having an interface with said silicon substrate, and further having a surface opposite said interface, said SiO.sub.x N.sub.y dielectric layer containing a first peak in nitrogen concentration proximal said interface, said first peak in nitrogen concentration extending across said SiO.sub.x N.sub.y dielectric layer, said SiO.sub.x N.sub.y dielectric layer further having a second peak in nitrogen concentration at said surface, said second peak in nitrogen concentration extending across said SiO.sub.x N.sub.y dielectric layer, for inhibiting diffusion of dopants from contacting surfaces through said dielectric layer.