Patent ID: 9093020
Filing Date: 2015-07-28
Classification: G09G

Abstract:
1. A display driving integrated circuit (IC), comprising: a plurality of source drivers; and a timing controller configured to output a plurality of signals to the plurality of source drivers, at least one of the timing controller and the plurality of source drivers configured to operate in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period, wherein in the power down mode, the timing controller is configured to output at least one of a constant DC voltage and a high impedance setting signal to the plurality of source drivers, an internal circuit of the timing controller is configured such that a bias current flowing through a clock signal generator included in the timing controller is reduced, an internal circuit of the plurality of source drivers is configured such that an internal bias current of the internal circuit is reduced, and the plurality of source drivers are configured to have their internal on die termination (ODT) resistance values modified.