Patent ID: 6289428
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A method in a superscalar processor for efficiently recovering from misaligned data addresses, said processor including a memory device partitioned into a plurality of addressable memory units, each of said plurality of addressable memory units having a width of a first plurality of bytes, said method comprising the steps of:determining whether a data address included within a memory access instruction is misaligned, said data address being misaligned when said data address includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit, said first and second data segments being separated by an addressable memory unit boundary;in response to a determination that said data address is misaligned, replacing said memory access instruction with a first, a second, and a third internal instruction;executing said first internal instruction which accesses said first memory unit and obtains only said first data segment;executing said second internal instruction which accesses said second memory unit and obtains only said second data segment; andexecuting said third instruction, said third instruction merging said first and second data segments together, so that in response to said memory access instruction having the misaligned data address, the processor executes the plurality of internal instructions having aligned data addresses.