Patent ID: 6038161
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A ferroelectric memory, comprising:a first ferroelectric capacitor;a second ferroelectric capacitor;a first bit line,a second bit line;a first connecting means for connecting one end of said first ferroelectric capacitor to said first bit line;a second connecting means for connecting one end of said second ferroelectric capacitor to said second bit line;a third connecting means for connecting the other end of said first ferroelectric capacitor to said second bit line;a fourth connecting means for connecting the other end of said second ferroelectric capacitor to said first bit line;a first supply means for supplying a first re-write signal due to a first bit line signal to said second bit line; anda second supply means for supplying a second re-write signal due to a second bit line signal to said first bit line.