Patent ID: 9153647
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a plurality of devices disposed over a substrate, the plurality of devices being comprised of at least two field effect transistors (FETs) comprising an n-type FET (nFET) device and a p-type FET (pFET) device; where the nFET and the pFET each have the same channel material stacks each comprised of a heterostructure, the heterostructure being comprised of at least one first layer of semiconductor material (A) having a thickness (tA) and at least one second layer of semiconductor material (B) having a thickness (tB), where the second layer of semiconductor material is adjacent to the first layer of semiconductor material and is different from the first layer of semiconductor material; where for the nFET device current flow is proportional to tA and for the pFET device current flow is proportional to tB, and where an effective device width (W) of the nFET device is a function of tA and the effective device width of the pFET device is a function of tB.