Patent ID: 7797609
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. An apparatus having a computer-readable medium encoded with instruction executed within the apparatus for merging a first data block including first data, and a second data block including second data and an original Error Correction Code (ECC) having a plurality of ECC check bits, the apparatus comprising: a data unit enable module to identify data units of the first data to be merged into corresponding data units of the second data; a data merge module arranged to merge the identified data units of the first data into the corresponding data units of the second data to create merged data; and a plurality of check bit generation modules each comprising means for determining whether a state of a respective one of the ECC check bits differs from its original state in the original ECC in response to merging the identified data units, and for establishing a respective revised ECC check bit based on the determination, wherein the respective revised ECC check bits from the plurality of check bit generation modules collectively provide a merged ECC for the merged data.