Patent ID: 9195459
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. A simultaneously accessible memory device comprising: an instruction decoding unit for decoding an inputted instruction and producing a decoding signal; a control and logic unit producing a control signal based on the decoding signal; a first memory with a first memory array and a first page buffer; and a second memory with a second memory array and a second page buffer; when the inputted instruction is a preset instruction, the preset instruction is used to execute data access on the first memory and access a backup data on the second memory based on a same data, namely, the same data is read from or written into the first and second memories simultaneously; when the inputted instruction is a preset instruction, the control signal of the control and logic unit simultaneously enables the first memory array, the first page buffer, the second memory array and the second page buffer; when the inputted instruction is a normal instruction, the control signal of the control and logic unit simultaneously enables the first memory array and the first page buffer; the control and logic unit comprises a decision unit which is used to decide whether the inputted instruction is a preset instruction or a normal instruction, and the decoding signal includes a first enable signal and a second enable signal; the decision unit comprises: