Patent ID: 7188133
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A floating point arithmetic device for outputting a value obtained by multiplying two real numbers as floating point numbers, resulting in a floating point number, wherein the floating point numbers include a mantissa and an exponent, said floating point arithmetic device comprising: a first register of N bits, including a high-order bit field of U bits and a low-order bit field of L bits, where N≧(U+L), for storing a floating point number, wherein the high-order bit field is of higher-significance than the low-order bit field, the high-order bit field stores the entire mantissa of the first number as a fixed point number, and the low-order bit field stores the entire exponent of the first number as an integer; a second register of N bits, including a high-order bit field of U bits and a low-order bit field of L bits, where N≧(U+L), for storing a floating point number, wherein the high-order bit field is of higher-significance than the low-order bit field, the high-order bit field stores the entire mantissa of the second number as a fixed point number, and the low-order bit field stores the entire exponent of the second number as an integer; a multiplier for multiplying the entire value of said first register as a fixed point number and the entire value of said second register as a fixed point number to obtain a multiplication result, wherein the multiplication result contains a mantissa bit field of at least U bits and an exponent bit field of at least L bits, wherein bits in the mantissa bit field are of higher-significance than bits in the exponent bit field; an adder for adding the entire value of said first register as a fixed point number and the entire value of said second register as a fixed point number to obtain an addition result, wherein the addition result contains a mantissa bit field of U bits and an exponent bit field of L bits, wherein bits in the mantissa bit field are of higher-significance than bits in the exponent bit field; and a bit combiner for combining the highest-order U bits of the mantissa bit field of the multiplication result with the L bit exponent bit field of the addition result.