Patent ID: 6764889
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of forming a vertical MOSFET, comprising the steps of:forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region; forming a source region of first conductivity type in the base region; forming a deep trench having a sidewall that extends adjacent the base region, in the semiconductor substrate; lining the deep trench with a an electrically insulating layer; refilling the lined deep trench with a trench-based source electrode; selectively etching the trench-based source electrode to define a shallow trench therein and expose a portion of the electrically insulating layer that extends on the sidewall of the deep trench; selectively etching the portion of the electrically insulating layer to expose an upper portion of the sidewall of the deep trench and reveal the base region; lining the shallow trench with a gate insulating layer that extends on the exposed upper portion of the sidewall of the deep trench and a bottom and sidewalls of the shallow trench; forming a gate electrode that extends on a surface of the semiconductor substrate and extends into the lined shallow trench; and forming a surface source electrode that electrically connects the trench-based source electrode, source region and base region together.