Patent ID: 9159675
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a substrate; a semiconductor layer arranged on the substrate; an insulating layer arranged on an upper portion of the semiconductor layer; and a patterned metallic layer arranged on the insulating layer and on a top side of the integrated circuit, the patterned metallic layer including a plurality of bumps to output and receive signals to and from an outside and an external alignment mark visible from the top side of the integrated circuit, wherein the semiconductor layer includes a main semiconductor area and an alignment mark area spaced apart from the main semiconductor area, the alignment mark area includes an internal alignment mark, the internal alignment mark being a pattern visible by an infrared camera from a bottom and opposite side of the integrated circuit, wherein the pattern of the internal alignment mark corresponds to a doping pattern of the semiconductor layer and not an etching pattern of the semiconductor layer, the internal alignment mark being defined by one of a portion of the semiconductor layer within the alignment mark area that includes a p-type dopant or a portion of the semiconductor layer within the alignment mark area that is absent of a p-type dopant.