Patent ID: 8283665
Filing Date: 2012-10-09
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. logic circuitry; B. parallel scan paths coupled to the logic circuitry, each scan path having a scan input and a scan output; C. stimulus data circuitry having a serial input, control inputs, a serial output, and parallel outputs coupled with the scan inputs of the parallel scan paths, the stimulus data circuitry including shift elements connected in series and each shift element includes a multiplexer having a serial data input, a fixed logic level input, and an output and each shift element includes a flip-flop having an input connected to the output of the multiplexer and an output connected to the scan input of one parallel scan path; and D. header data circuitry having a serial input connected with the serial output of the stimulus data circuitry, control inputs, a command output and a frame marker output, the header data circuitry including two shift elements connected in series, each shift element includes a multiplexer having a serial data input, a fixed logic level input, and an output, each shift element includes a flip-flop having an input connected to the output of the multiplexer and an output, the output of one shift register is connected to the command output, and the output of the other shift register is connected to the frame marker output.