Patent ID: 8351241
Filing Date: 2013-01-08
Classification: G11C,H01L,H02H

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a first electrode structure spatially disposed in a first direction and provided on a portion of the semiconductor substrate; a second electrode structure spatially disposed in a second direction angled relative to the first direction; a resistive switching element located between the first electrode structure and the second electrode structure, the resistive switching element being configured to change in resistance when a voltage is applied between the first electrode structure and the second electrode structure, the voltage being greater than a first threshold voltage; and a dielectric breakdown element configured to cause rectification, the dielectric breakdown element being serially connected to the resistive switching element and disposed between the resistive switching element and one of the electrode structures, the dielectric breakdown element having a breakdown voltage less than the first threshold voltage.