Patent ID: 7501322
Filing Date: 2009-03-10
Classification: H01L

Abstract:
1. A method of forming a semiconductor device on a semiconductor substrate, comprising: forming a select gate pattern, a first storage gate pattern, and a second storage gate pattern on a surface of the substrate, wherein the first storage gate pattern is closer to the select gate pattern than the second storage gate pattern; forming continuous source/drain regions in the substrate between the select gate pattern and the first storage gate pattern, and between the first storage gate pattern and the second storage gate pattern; forming a trench in the substrate between the select gate pattern and the first storage gate pattern to separate the continuous source/drain region therebetween into a split source/drain region, wherein the split source/drain region comprises spaced apart first and second source/drain subregions, and wherein, after forming the trench, the surface of the substrate that extends from the first storage gate pattern to the second storage gate pattern is substantially planar such that a trench is not formed between the first and second storage gate patterns; forming a connecting region in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion, wherein the connecting region and the split source/drain region have a same conductivity type, and wherein the connecting region has a higher carrier concentration than a carrier concentration of the split source/drain region; and forming an insulating layer between the select gate pattern and the first storage gate pattern, and between the first and second storage gate patterns, wherein the insulating layer fills the trench, and wherein no conductive layer is formed between the select gate pattern and the first storage gate pattern.