Patent ID: 9007826
Filing Date: 2015-04-14
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory strings, each memory string including a plurality of memory cells connected in series, each memory cell storing multi-valued data; a word line that connects to one of the a plurality memory cells; a bit line that is connected to a first end of the memory string; a source line connected to a second end of the memory string; a sense amplifier circuit configured to determine the data to be stored in the memory cell by detecting the potential or the electric current of the bit lines; and a control circuit configured to execute a first page writing operation to form an intermediate voltage distribution by changing a threshold voltage of the memory cells connected to the word line, a first verify operation to determine if the first page writing operation to the memory cell has been completed by using a first verify voltage, a second page writing operation to change the intermediate voltage distribution, a second verify operation to determine if the second page writing operation to the memory cell has been completed by using a second verify voltage and a step-up operation that increases the program voltage by a step-up voltage amount based on results of the verify reading, wherein the control circuit is configured to execute the first page writing operation which forms the intermediate voltage distribution, and a first read operation which reads data from the intermediate voltage distribution by using a determine voltage higher than the first verify voltage, and to change the second verify voltage based only on the result of the first read operation.