Patent ID: 6083273
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A static timing analyzer for semiconductor integrated circuits comprising:a memory device for storing a net list as data for circuit connections;a specifying device for specifying a clock node for receiving an input clock signal; anda control unit connected to said memory device;said memory device including:constructing means for constructing a circuit having transistors on the basis of said net list read out of said memory device, said constructed circuit including a sequential circuit;recognizing means for recognizing said clock node specified by said specifying device from said circuit constructed by said constructing means, said clock node corresponding to at least one of a gate and source/drain region of said transistors;dividing means for dividing said sequential circuit of said constructed circuit into a plurality of combinational circuits by tracing said recognized clock node on the basis of a clock signal and determining if the output node of said circuit can achieve a high impedance state in response to the clock signal; andsearching means for searching for paths in said combinational circuits divided by said dividing means.