Patent ID: 7441072
Filing Date: 2008-10-21
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, wherein each memory cell has a threshold voltage set at any of first to fourth threshold value levels selectively to store any of four different data codes each including first data and second data, said first threshold value level is lower than a first determination level, said second threshold value level is higher than said first determination level and lower than a second determination level, said third threshold value level is higher than said second determination level and lower than a third determination level, and said fourth threshold value level is higher than said third determination level, said first to fourth threshold value levels correspond to said four data codes, respectively, rearranged by a procedure including i) a first step of dividing and rearranging said four data codes in two groups in accordance with whether each data code has said first data having a first logic or a second logic, and ii) a second step of rearranging two data codes of each of said groups in accordance with whether each data code has said second data having said first or second logic, said data codes corresponding to said first and second threshold levels, respectively, have said first data of said first logic, and said data codes corresponding said third and fourth threshold levels, respectively, have said first data of said second logic, in one of said groups of said data codes having said first data of said first logic, one of said data codes having said second data of said first logic corresponds to a threshold value level lower than the other of said data codes having said second data of said second logic does, and in the other of said groups of said data codes having said first data of said second logic, one of said data codes having said second data of said first logic corresponds to a threshold value level higher than the other of said data codes having said second data of said second logic does; a cell selection circuit operative in response to an address signal to collectively select any m of said plurality of memory cells of said memory cell array, m being an integer of at least two; a data read/write circuit operative in accordance with said first to third determination levels to perform an operation reading/writing m data codes from/to said m memory cells selected by said cell selection circuit; and a data input/output circuit transmitting and receiving said first and second data of said m data codes between outside of the nonvolatile semiconductor memory device and said data read/write circuit through k input/output nodes by every k bits, k being a natural number, wherein said first and second data of each data code are transmitted and received at different times, respectively, through a single one of said input/output nodes, wherein said data read/write circuit performs: