Patent ID: 6128209
Filing Date: 2000-10-03
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate having a memory cell array area, a peripheral circuit area surrounding the memory cell array area, and a boundary area located between the memory cell array and the peripheral circuit area, wherein the memory cell array area, the peripheral circuit area and the boundary area are located on a principal surface of the semiconductor substrate;a plurality of active regions formed in the memory cell array area;a plurality of dummy active regions formed in the boundary area;a plurality of word lines which extend parallel to each other in a first direction and which cross over said active regions;a dummy word line which extends in the first direction and which crosses over said dummy active regions;an insulation layer covering over said word lines and said dummy word line;a plurality of bit lines, formed over said insulation layer, and which extend parallel to each other in a second direction substantially perpendicular to the first direction and which cross over said active regions and said dummy active regions, and said plurality of bit lines being electrically connected to said active regions by through holes defined in said insulation layer, and said plurality of bit lines being electrically isolated from said dummy active region;a dummy bit line, formed over said insulation layer, and which extends in a second direction and which cross over said active regions and said dummy active regions, and said dummy bit line being electrically isolated from said dummy active regions; anda plurality of memory cells, which are arranged at said active regions, each of which includes a capacitor and a switching transistor.