Patent ID: 6204123
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method for fabricating a vertical floating gate transistor on a substrate having a first conductivity type, the method comprising:doping in a first area of the substrate to form a first doped region having a second conductivity type, said doping in the first area including implanting the substrate with a first dopant and a second dopant that differs from the first dopant, the first and second dopants forming the first doped region, wherein the first dopant has a higher diffusion rate than the second dopant;after the step of doping in a first area, forming an epitaxial layer of the first conductivity type over the first doped region, a portion of the epitaxial layer providing a channel for the vertical floating gate transistor, wherein the step of forming the epitaxial layer causes the first and second dopants to diffuse, the first dopant extending further into the portion of the epitaxial layer that provides the channel than the second dopant;doping in a second area to form a second doped region, the second doped region having the second conductivity type and residing above the portion of the epitaxial layer that provides the channel;forming a trench that extends through at least a portion of the first doped region, the epitaxial layer, and the second doped region;forming a first gate electrode in the trench, the first gate electrode being separated from the first and second doped regions by a first insulating layer; andforming a second gate electrode that is separated from the first gate electrode by a second insulating layer.