Patent ID: 6438066
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells arranged in rows and columns; a plurality of clock input terminals each for receiving an external clock signal; a clock input circuit; means for changing a combination of connections between said plurality of clock input terminals and said clock input circuit; a mode register for receiving and holding external instructions indicating an operational mode; a control circuit for controlling read/write operation timing of said semiconductor memory device by outputting a column selection control signal, said control circuit determining timing for activating said column selection control signal; a column select circuit responsive to said column selection control signal for selecting a memory cell column according to an address signal; a gate circuit for transmitting data to/from the selected memory cell column; a data input circuit for receiving write data to transmit said write data to said gate circuit; and a data output circuit for receiving data from said gate circuit and outputting read data in synchronization with an output of said clock input circuit.