Patent ID: 7380222
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A method for performing verification, said method comprising: selecting a set of gates to add to a first localization netlist; forming a refinement netlist; computing a min-cut with sinks comprising one or more gates in said refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers of said original netlist which are not part of said refinement netlist; and obtaining a final localized netlist by adding one or more gates to said refinement netlist to grow said refinement netlist until reaching one or more cut-gates of said min-cut, and wherein said step of computing a min-cut further comprises computing a min-cut with sinks comprising one or more gates in said refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers of said original netlist which are not part of refinement netlist, and wherein said step of computing said min-cut further comprises computing said min-cut to include one or more items of logic that is not combinationally driven logic and one or more gates which are sequentially driven by registers in said first localization netlist and said set of gates to add.