Patent ID: 8963208
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method, comprising: providing a structure comprising a semiconductor substrate, a semiconductor layer provided above said semiconductor substrate and a dielectric layer provided between said semiconductor substrate and said semiconductor layer; forming a trench isolation region, providing electrical isolation between a portion of said semiconductor layer in a second part of said structure and a first part of said structure, before said portions of said semiconductor layer and said dielectric layer in said first part of said structure are removed; after forming said trench isolation region, removing portions of said semiconductor layer and said dielectric layer in said first part of said structure so that said semiconductor substrate is exposed in said first part of said structure, wherein portions of said dielectric layer and said semiconductor layer in said second part of said structure remain on said semiconductor substrate; forming a semiconductor region directly on the exposed semiconductor substrate in said first part of said structure; and forming a first transistor in said second part of said structure, said first transistor comprising an active region provided in said portion of said semiconductor layer in said second part of said structure.