Patent ID: 6503783
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A method for creating complementary semiconductor transistor devices on a silicon wafer comprising:forming a buried silicon dioxide (BOX) insulation layer in the silicon wafer; growing epitaxial silicon atop the silicon wafer so as to form an active layer above the buried insulation layer; implanting n-type or p-type dopants into the active layer to create n-wells and p-wells respectively so as to form complementary device regions in the active layer; implanting n-type and p-type dopant atoms through the complementary device regions such that the dopant atoms come to reside within the BOX insulation layer underlying the device regions so as to create a borophosphosilicate glass (BPSG) within the BOX layer; implanting dopant atoms into gate regions of the device regions so as to adjust the threshold voltage of the transistor devices; forming a gate stack on the active layer adjacent the gate regions; and implanting dopant atoms into the device regions such that the dopant atoms come to reside within the device regions adjacent the gate regions so as to form source and drain regions and wherein the gate stack substantially inhibits penetration of the dopant atoms into the gate regions of the device regions.