Patent ID: 6477635
Filing Date: 2002-11-05
Classification: G06F

Abstract:
A processor comprisinga load/store unit having a level one (L1) cache and coupled to a memory subsystem, the load/store unit further having a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises: circuitry for receiving an L1 cache reload from the memory subsystem, circuitry for comparing a real address of the L1 cache reload to addresses in the real address tag array, circuitry for calculating an effective address corresponding to the real address of the L1 cache reload if the comparison results in a hit, circuitry for using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array; and circuitry for reloading the L1 cache using the calculated effective address.