Patent ID: 8107290
Filing Date: 2012-01-31
Classification: G11C,H01L

Abstract:
1. A memory cell structure for a memory device, comprising: a substrate; a read transistor having a floating gate node; a tunnelling capacitor connected to the floating gate node and having a first programming terminal; a coupling capacitor stack connected to the floating gate node and having a second programming terminal and having an intermediate node between adjacent coupling capacitors in the coupling capacitor stack, wherein each said intermediate node is isolated from the substrate and is a floating node having a floating voltage during operation of said memory device, the coupling capacitor stack formed of at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, the coupling capacitor stack having a larger capacitance than the tunnelling capacitor; wherein during a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node; and wherein during a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node.