Patent ID: 8407277
Filing Date: 2013-03-26
Classification: G06F

Abstract:
1. A full subtractor cell comprising: an exclusive-NOR gate having a first input coupled to a first bit and a second input coupled to a second bit; an exclusive-OR gate having a first input coupled to an output of the exclusive-NOR gate and a second input coupled to a carry input bit, the exclusive-OR gate having an output to generate the sum output bit thereon; a first AND gate having a first input coupled to the output of the exclusive-NOR gate and a second input coupled to the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having a first input coupled to the first bit and a second input coupled to an output of the inverter gate to receive the complemented second bit; and an OR gate having a first input coupled to an output of the first AND gate and a second input coupled to an output of the second AND gate, the OR gate having an output to generate the carry output bit thereon.