Patent ID: 6642599
Filing Date: 2003-11-04
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate having a main surface; and a semiconductor layer formed on the main surface of said semiconductor substrate with an insulating layer therebetween, and having an element formation region for forming an element having an insulated gate transistor portion and another element formation region for forming another element, wherein said semiconductor layer is provided with a trench surrounding at the surface of said semiconductor layer a periphery of said element formation region for electrically isolating said element formation region from said another element formation region, said insulated gate transistor has a source region and a drain region spaced from each other and formed at the surface of said semiconductor layer, and said source region is located in said element formation region at said surface of said semiconductor layer and surrounds said drain region, the semiconductor device further comprising a source leading interconnection layer electrically connected to said source region, and a drain leading interconnection layer electrically connected to said drain region, wherein said drain leading interconnection layer extends above said source leading interconnection layer in a direction crossing said source leading interconnection layer and electrically isolated from said source leading interconnection layer.