Patent ID: 6251721
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming gate electrodes in a first region over a semiconductor substrate and one gate electrode in a second region over said semiconductor substrate, and then forming first impurity diffusion layers on both sides of said gate electrodes in said first and second regions;forming a first passivation film in said first and second regions;forming an insulating film in said first and second regions, processing said insulating film in said second region to form a side wall on both sides of the gate electrode in said second region to expose a surface of said semiconductor substrate on both sides of said side wall;forming, in said semiconductor substrate exposed on both sides of said side wall, a second impurity diffusion layer partially to overlap said first impurity diffusion layer;forming a second passivation film in said first and second regions; andforming a first connection hole for exposing said first impurity diffusion layer in said first region, and a second connection hole for exposing said second impurity diffusion layer in said second region, by using said first and second passivation films.