Patent ID: 7859883
Filing Date: 2010-12-28
Classification: B82Y,G11C

Abstract:
1. A memory device comprising: a plurality of memory cells each comprising a recordable layer between two metal layers, the recordable layer comprising a first sub-cell and a second sub-cell; wherein each memory cell is constructed and designed to change from an as-deposited state to an initialized state upon application of an initialization signal, from the initialized state to a first inscribed state upon application of a first write signal, and from the initialized state to a second inscribed state upon application of a second write signal, the memory cell having a resistor-like current-voltage (I-V) characteristic when in the as-deposited state, a diode-like I-V characteristic when in the initialized state, and resistor-like I-V characteristics when in the first and second inscribed states for voltages within a predetermined range, wherein for a voltage within a specified range that is applied across the two metal layers, the memory cell has a lower resistance in the as-deposited state than in the initialized state, a higher resistance in the initialized state than in the first inscribed state, and a higher resistance in the initialized state than in the second inscribed state.