Patent ID: 7449927
Filing Date: 2008-11-11
Classification: H03L

Abstract:
1. A delay locked loop, comprising: a clock delay compensation block for receiving a clock signal inputted from an external to thereby generate a multi-phase signal and multi-phase clocks; a phase control block for generating a phase control signal controlling a shifting operation based on the multi-phase signal and the multi-phase clocks; and a multi-phase delay control block for performing the shifting operation based on the phase control signal to control the clock delay compensation block, wherein the clock delay compensation block includes: a clock buffer for buffering the clock signal to generate rising and falling clocks; a phase comparator for comparing the rising and the falling clocks with a feed-back internal clock to output a comparison result; a delay controller for performing a shifting operation based on the comparison result to generate a register signal controlling a phase delay amount; a multi-phase delay line for delaying the rising and the falling clocks based on the comparison result to generate a second multi clock and generating a first multi clock in response to a delay control signal outputted from the multi-phase delay control block, wherein the first multi clock have a different phase with the second multi clock; a dummy delay line for delaying one of output signals of the clock buffer; a replica model for delaying an output of the dummy delay line by a predetermined amount modeled based on delay elements to generate the feed-back internal signal; and an output buffer for synchronizing data input through a data bus with the second multi clock to generate the synchronized data.