Patent ID: 9000530
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A memory device comprising: a first plurality of semiconductor nanowires tethered between first and second landing pads and suspended over a substrate; a first gate electrode extending across said first plurality of semiconductor nanowires, each of said first plurality of semiconductor nanowires being surrounded by said first gate electrode, said semiconductor nanowires of said first plurality thereby being gate-all-around (GAA) semiconductor nanowires; a first, a second, and a third field effect transistor (FET), each formed, with said first gate electrode, by at least one of said first plurality of semiconductor nanowires, said first, second, and third FETs each having a source/drain contact; a second plurality of semiconductor nanowires tethered between third and fourth landing pads and suspended over said substrate; a second gate electrode extending across said second plurality of semiconductor nanowires, each of said second plurality of semiconductor nanowires being surrounded by said second gate electrode, said semiconductor nanowires of said second plurality thereby being GAA semiconductor nanowires; a fourth, a fifth, and a sixth FET, each formed, with said second gate electrode, by at least one of said second plurality of semiconductor nanowires, said fourth, fifth, and sixth FETs each having a source/drain contact; said first gate electrode being aligned with and cross-coupled to a one of said third and fourth landing pads of said second plurality of semiconductor nanowires, and said second gate electrode being aligned with and cross-coupled to a one of said first and second landing pads of said first plurality of semiconductor nanowires, said first and second gate electrodes each having a gate contact, wherein each of said source/drain contacts is elevated over said landing pads and said gate electrodes relative to said substrate, and each of said gate contacts are elevated over said source/drain contacts relative to said substrate, and wherein said source/drain contact of said first FET is connected to a bitline connection; said source/drain contacts of said second and fifth FETs are each connected to ground connections; said source/drain contacts of said third and fourth FETs are each connected to operating voltage connections; said source/drain contact of said sixth FET is connected to a bitline bar connection; and said gate contacts of said first and second gate electrodes are connected to a word line connection.