Patent ID: 8725958
Filing Date: 2014-05-13
Classification: G06F,Y02D

Abstract:
1. A data processor comprising: a plurality of processors; a plurality of cache memories each corresponding to a respective processor of the plurality of processors, and each coupling the respective processor to a common memory, wherein each cache memory of the plurality of cache memories receives a snoop access from a processor other than the corresponding processor and updates a cache state of its own cache line in response to the snoop access in order to maintain cache coherency, wherein each processor of the plurality of processors executes a predetermined instruction in a spinlock process to output a spin wait request to the corresponding cache memory, and wherein each cache memory includes a control unit which receives a read request from the corresponding processor, and outputs an acknowledge response to the read request to the corresponding processor in response to the updating of the cache state after receiving the spin wait request from the corresponding processor.