Patent ID: 6567309
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor device, comprising:an oscillator configured to output a plurality of phase shifted clocks; a voltage boosting circuit configured to input a plurality of driving clocks and outputting a boosted voltage higher than a power supply voltage; a voltage detection circuit configured to detect whether said boosted voltage is higher than a predetermined voltage or not and to output a detection signal, wherein said detection signal is in a first logic state when said boosted voltage is lower than said predetermined voltage and said detection signal is in a second logic state when said boosted voltage is higher than said predetermined voltage; and a clock signal control circuit configured to input said plurality of phase shifted clocks and said detection signal, and to output said plurality of driving clocks, wherein said clock signal control circuit transfers said plurality of phase shifted clocks to output said plurality of driving clocks when said detection signal is in said first logic state, said clock signal control circuit stops transferring said plurality of phase shifted clocks when said detection signal changes from said first logic state to said second logic state, and said clock signal control circuit holds each logic state of said plurality of driving clocks when said detection signal is in said second logic state.