Patent ID: 8261276
Filing Date: 2012-09-04
Classification: G06F,Y02D

Abstract:
1. A computer implemented method of managing thread priority settings to achieve a target power efficiency mode of a processor, the computer implemented method comprising: receiving an instruction or command from a higher-level system control to set a current power consumption of the processor; determining a target power efficiency mode for the processor; updating thread priority settings in a thread switch control register for an executing thread to control at least one of balance flush speculation or dispatch flush speculation to achieve the target power efficiency mode; wherein the updating step further comprises: updating the thread priority settings to enable balance flush speculation and dispatch flush speculation if a global completion table entry threshold number is met to achieve one of a medium power efficiency mode and a low power efficiency mode; responsive to detecting the thread is a dispatch stall, determining whether a balance flush miss cycle counter for the executing thread is less than a threshold number of cycles; responsive to a determination that the balance flush miss cycle counter for the executing thread is less than a threshold number of cycles, performing a balance flush on the executing thread; and responsive to a determination that the balance flush miss cycle counter for the executing thread is not less than a threshold number of cycles, ignoring the dispatch stall of the executing thread.