Patent ID: 7817216
Filing Date: 2010-10-19
Classification: G02F

Abstract:
1. A flat panel display, comprising: a plurality of gate lines and a plurality of data lines formed on a substrate; an anti-electrostatic wire comprising a first portion and a second portion formed between a gate line and an adjacent gate line; an interlayer insulating layer formed on the anti-electrostatic wire and the gate lines; a source electrode and a drain electrode formed on the interlayer insulting layer; a passivation layer formed on the source electrode and the drain electrode; an anti-electrostatic circuit coupled to a data line, and formed on the interlayer insulating layer; and a gate insulating layer formed on the substrate, the gate lines and the anti-electrostatic wire being formed on the gate insulating layer, wherein the interlayer insulating layer has an opening, the opening corresponding to a gap separating the first portion of the anti-electrostatic wire from the second portion of the anti-electrostatic wire, wherein the passivation layer fills the gap between the first portion and the second portion of the anti-electrostatic wire, and wherein the passivation layer contacts the source electrode, the drain electrode, and the gate insulating layer.