Patent ID: 8352887
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A method for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each having shape corners at respective locations in the layout, for use by a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the method comprising the steps of: the computer system traversing a plurality of shape corners of shapes in the region; for each corner in at least a subset of at least two of the shape corners, the computer system populating a layout topology database with values in dependence upon the respective corner location; after the layout topology database has been populated with values in dependence upon the corner location of all corners in the subset, the computer system comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules; and where a design rule violation is detected, reporting it to a user.