Patent ID: 9135960
Filing Date: 2015-09-15
Classification: G05F,G11C

Abstract:
1. A signal receiver circuit comprising: a selection signal generator configured to generate first and second selection signals in response to at least one of an electrical open/short state of a fuse and test mode signals; an internal reference voltage generator configured to amplify an external reference voltage signal after reducing static electricity created by the external reference voltage signal to generate a plurality of internal voltage signals and configured to generate an internal reference voltage signal using the plurality of internal voltage signals in response to the first and second selection signals; and a buffer configured to buffer an internal signal in response to the internal reference voltage signal to generate a control signal for controlling an internal circuit, wherein the external reference voltage signal is inputted from an external device for determining a logic level of the internal signal, and wherein the internal reference voltage generator includes: a voltage divider configured to divide a voltage level of an internal node to generate the divided voltage signals and an input division voltage signal; a driver configured to drive a level of the internal node in response to a pull-up signal generated according to a comparison result of the input division voltage signal and the first internal voltage signal; and a reference voltage selector configured to output one of the divided voltage signals as the second internal voltage signal in response to the first selection signal, a reference voltage controller configured to amplify the second internal voltage signal to generate at least two divided voltage signals and configured to output one of the divided voltage signals as a third internal voltage signal in response to the first selection signal.