Patent ID: 6108776
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A millimode capable computer method for a system havinga central processor and a normal mode of operation and a millimode of operation,a cache, an instruction fetch unit, and instruction decode unit, and an execution unit, and the instruction fetch unit coupled to a branch history table for control of instructions processing in normal mode and milli-mode, comprising the steps of:providing control for millicode to allow the BHT operations to continue except when special situations occur that require control of instruction fetch operations, and for directing instruction fetch for both a global BHT disable and for separate millicode disables and wherein said branch history table operations can be turned off for some sections of code execution, but not disabled for all, byproviding a millimode operation for system operations that require control of type of cache functions that can occur and when instruction fetches can occur under millimode control including two processes used to control branch table history actions, a first process of which globally disables branch table history BHT actions and a second process of which enables branch table history BHT action,determining which of the two processes will be used by the specific millicode sequence being invoked, andat the time of entry into a specific millicode sequence initializing millicode control registers to desired values where one bit in one of said millicode control registers when initialized to a value of one will result in the matching mechanism of the branch history table to be disabled and no further instruction fetches of the targets of these entries will be performed,and, later, after said millicode sequence has passed sensitive parts of the millicode sequence routine millicode turns this control bit off and re-enables branch history table functions.