Patent ID: 6754737
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A method for enforcing ordering between read and write transactions for an adapter unit configured to connect to a bus, the adapter unit having at least one read buffer and at least one write buffer containing a plurality of slots, the method comprising:enqueuing, in the write buffer, a first initiator write transaction to be performed on the bus; enqueuing, in the write buffer, a second initiator write transaction to be performed on the bus after the first initiator write transaction; receiving, in the read buffer, an initiator read transaction request, the read buffer having a read context register for the initiator read transaction request, wherein the read context register includes a write contingency flag entry for each slot of the plurality of slots in the write buffer and wherein performance, on the bus, of the read transaction request is required to follow the performance, on the bus, of the first initiator write transaction, but not the second initiator write transaction; clearing the write contingency flags in the read context register for the initiator read transaction request; if, after receiving the read transaction request, the performance of the first and second initiator write transactions have not started on the bus, setting, in the read context register, a write contingency flag associated with the slot in the write buffer occupied by the first write transaction, to indicate the dependence of the read transaction request on the first initiator write transaction in the write buffer; performing the first write transaction on the bus; after the performance of the first write transaction is completed, clearing the write contingency flag of the first write transaction in the read context register; and if the write contingency flag of the first write transaction is not set in the read context register, performing the read transaction request on the bus.