Patent ID: 7176738
Filing Date: 2007-02-13
Classification: G06F,H03L

Abstract:
1. A clock chip comprising: a clock input capable of receiving a reference clock; an M divider circuit having an input, a control input, and an output, said input coupled to said clock input; a frequency generation block having a clock input, a feedback input, and an output, said input coupled to said M divider output; a N divider circuit having an input, a control input, and an output, said input coupled to said frequency generation block output, and said output coupled to said frequency generation block feedback input; an O divider circuit having an input, a control input, and an output, said input coupled to said frequency generation block output, and said output capable of connection to a destination; a control logic block having one or more inputs, and one or more outputs, said one or more inputs capable of receiving one or more signals; one or more sources of information having one or more outputs; a selector logic block having one or more control inputs, one or more inputs, and one or more outputs, said one or more control inputs coupled to receive said control logic block one or more outputs, and said one or more inputs coupled to receive said one or more sources of information; and said selector logic block one or more outputs coupled to one or more divider controls selected from the group consisting of said M divider circuit control input, said N divider circuit control input, and said O divider circuit control input.