Patent ID: 6077732
Filing Date: 2000-06-20
Classification: H01L,Y10S

Abstract:
A method of forming a bottom gated thin film transistor comprising the following steps:providing a transistor gate on a substrate;providing a thin film transistor layer outwardly of the transistor gate, the thin film transistor layer comprising a source area, a channel area, a drain area, and a drain offset area;providing a sidewall spacer laterally adjacent the transistor gate over the drain offset area and leaving the channel area outwardly exposed;with the masking sidewall spacer in place, implanting a conductivity enhancing impurity of a first type into the thin film channel area to provide a thin film channel region; andmasking the channel area and the drain offset area while implanting conductivity enhancing impurity of a second type into the thin film source and drain areas to define thin film source and channel regions.