Patent ID: 8779494
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A high-k metal gate random access memory, comprising: a substrate having a plurality of trenches; a plurality of bit line units disposed on the substrate and alternately arranged with the trenches; a plurality of source regions, wherein each of the source regions is disposed on the respective bit line unit, wherein the source regions is made of polysilicon doped with n-type ions; a plurality of gate structures, wherein each of the gate structures is connected to the respective source region, wherein each gate structure has a metal gate and a channel area formed therein; a plurality of drain regions, wherein each drain region is disposed on the respective gate structure; a plurality of word lines units arranged between the source and drain regions, wherein the word line units partially cover the gate structures; and a plurality of capacitance units, wherein each capacitance unit is in connection with the respective drain region.