Patent ID: 6038167
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A multi-level nonvolatile memory device formed on a single chip, comprising:a plurality of memory cells each of which stores data as a threshold voltage;a write circuit which is coupled to the plurality of memory cells, by which a write operation is executed for a first memory cell in a first period so that a threshold voltage of the first memory cell is brought to a first threshold voltage region, and by which a write operation is executed for a second memory cell in a second period which is different from the first period so that a threshold voltage of the second memory cell is brought to a second threshold voltage region which is different from the first threshold voltage region;a binary data holding circuit which is coupled to the write circuit and which holds first binary data for indicating the first memory cell and second binary data for indicating the second memory cell;a plurality of binary data registers each of which stores binary data to be written to memory cells; anda converter circuit which is coupled to the plurality of binary registers and to the binary data holding circuit and which forms the first binary data and the second binary data in accordance with the stored binary data in the plurality of binary data registers.