Patent ID: 7053688
Filing Date: 2006-05-30
Classification: H04L

Abstract:
1. A constrained coefficient adder for adding an adaptive differential control voltage and a forcing differential control voltage, comprising: a first diode-connected transistor conducting current from a first node; a second diode-connected transistor conducting current from a second node; a first differential transistor pair, wherein current steering within the first differential pair of the current from the first current source is responsive to the adaptive differential control voltage; and a second differential pair, wherein current steering within the second differential pair of the current from the second current source is responsive to the forcing differential control voltage, and wherein the current steered by a first transistor in each of the first and second differential pairs is supplied by the first node, and wherein the current steered by a second transistor in each of the first and second differential pairs is supplied by the second node such that if the forcing differential control voltage steers all the current to either of the first or second transistors in the second differential pair a current difference between the current conducted by the first and second diode-connected transistors cannot change sign responsive to changes in the adaptive differential control voltage, the current difference representing the addition of the adaptive differential control voltage and the forcing differential control voltage.