Patent ID: 8614911
Filing Date: 2013-12-24
Classification: G11C

Abstract:
1. A method for programming a phase change memory (PCM) cell in a PCM memory cell array having a plurality of rows of word lines connected at respective word line terminals of said memory cells and plurality of columns of bit lines connected at respective bit line terminals of said memory cells, the method comprising: selecting an individually selectable adiabatic logic device of a set of selectable adiabatic logic devices, each adiabatic logic device of said set associated with a respective row of PCM cells; receiving an input ramped signal at said selected adiabatic logic device of said set of adiabatic logic devices and responsively generating a first output ramping signal in adiabatic fashion; applying said first output ramping signal to a word line terminal in said adiabatic fashion to select a row of memory cells for programming those PCM cells associated with the word line, said first output ramping signal applied for a defined time duration to a row corresponding to said selected adiabatic logic device; and, applying one or more second signals to respective bit line terminals of selected one or more memory cells of said selected row concurrent with the applying said first signal to the word line terminal.