Patent ID: 6704861
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A system for executing computer instructions in parallel, comprising:an identification for each instruction to be executed, said identification being independent of an execution order of said identified instruction; means for grouping instructions into a plurality of sets according to said identification, instructions having identical identifications being grouped into the same set, each set including a plurality of instructions, said plurality of instructions of each set arranged in a normal execution order, said sets for executing said plurality of instructions of said sets substantially in parallel as a plurality of execution flows, there being one execution flow associated which each set, each instruction of said plurality of instructions of each set having said identification to distinguish the instructions of said sets when said sets are executed in parallel as said associated plurality of execution flows; means for reordering said plurality of instructions within said sets to accelerate execution, said instructions being reordered independent of said identification of the instructions; means for marking predetermined instructions of said sets if said predetermined instructions have data dependencies or control dependencies unresolvable by said means for reordering; a computer system executing said sets in parallel as said plurality of execution flows; means for determining if particular one of said predetermined instructions of said sets is subject to an exception condition while executing; and means, responsive to detecting said exception condition, for repeating execution of a particular set identified by said identification of said particular predetermined instruction to resolve said exception condition.