Patent ID: 6594732
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A computer system comprising:a host bus; a CPU connected to said host bus; a main memory connected to said host bus; a cache memory connected to at least one of said host bus and said CPU, said cache memory storing cache data, wherein a tag address and a flag are provided for each of said cache data and said flag indicates one of a clean state in which said corresponding cache data is written back into said main memory and a dirty state in which said corresponding cache data is not yet written back into said main memory; and a memory controller connected to said host bus, said cache memory and said main memory, wherein said memory controller writes back dirty write back cache data into said main memory in a continuous write back mode when said host bus is not used, wherein said dirty write back cache data is a part of said cache data stored in said cache memory, and each of said dirty write back cache data is written back and each of said dirty write back cache data includes a predetermined portion in said tag address, wherein said memory controller cancels said continuous write back mode when said CPU accesses said cache memory or said main memory in a memory access using said host bus.