Patent ID: 6317005
Filing Date: 2001-11-13
Classification: G09G,H04L,H04N

Abstract:
Process of clock recovery during the sampling of computer-type signals, the sampling clock being generated from a phase locked loop or PLL which multiplies a given frequency by an integer number or ""division rank"", wherein the process comprises the following steps:Gauging of the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the computer-type signals in such a way as to obtain a first value dependent on the said position,carrying out of a sampling clock phase correction,by comparing the first position-dependent value with a reference value in such a way as to obtain a second signed value,by accumulating the second signed values during the given frequency,by transforming the accumulated values into an analog value dependent on the sampling phase-shift and by applying the value thus obtained to the PLL so as to phase-shift the sampling clock, andcarrying out of a sampling clock frequency correction,by measuring the alteration in the phase error between two consecutive analog ramps,by determining and accumulating the sign of this alteration,then, when the accumulated value exceeds a positive or negative threshold value, by sending an increment of +1 or -1 depending on the threshold value in relation to the division rank of the PLL.