Patent ID: 8972995
Filing Date: 2015-03-03
Classification: G06F

Abstract:
1. An interconnect for an integrated circuit, comprising: where the interconnect is configured to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores, including a target memory core, which are coupled to the interconnect; and a tag and thread logic configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core, where a tag-arbiter per thread is implemented to handle tag parallelism to arbitrate between tagged requests of the same thread to determine an order in which requests in that thread should be scheduled for memory accesses, wherein the tag and thread logic is configured to handle servicing of tags and threads concurrently by applying an efficiency and latency algorithm to optimize decisions based on overall memory efficiency accesses and per-thread Quality-of-Service latency requirements to re-order a servicing order of per-tag requests within a same thread out of the initial issue order.