Patent ID: 7716098
Filing Date: 2010-05-11
Classification: B41J,B42D,G06F,G06K,G06Q,G07F,G11C,H01L,H04L,H04N

Abstract:
1. An integrated circuit including at least one CMOS circuit comprising at least first and second transistors that change state within a period of time and at least one decoy CMOS circuit comprising third transistors, each of the first and second transistors exhibiting low resistance in one state and high resistance in another state, the at least one CMOS circuit being configured such that timing of the change of state of the first transistor relative to the second transistor is controlled so as to prevent the transistors having simultaneous intermediate resistances between the low and high resistances, thereby to reduce optical emission by the at least one CMOS circuit compared to causing the changes of state of the first and second transistors to happen simultaneously, wherein the third transistors of the decoy CMOS circuit emit light during a change in state, the decoy CMOS circuit being disposed near at least one of the first and second transistors of the CMOS circuit so that light emissions from the decoy CMOS circuit hinder optical detection of a pattern of light emitted by the CMOS circuit.