Patent ID: 7459940
Filing Date: 2008-12-02
Classification: H03K

Abstract:
1. A Local Clock Buffer (LCB) for clocking a CMOS Integrated Circuit (IC) chip, said LCB comprising: a plurality of series connected logic gates, a global clock being provided to one of said plurality of series connected logic gates, and at least one other of said plurality of series connected logic gates providing a local clock, said plurality of series connected logic gates comprising: an inductor in each of said plurality of series connected logic gates, one or more devices in each series connected logic gate being connected through said inductor in alternating gates to a supply line and a supply return, wherein each said local clock has an identified critical edge, said identified critical edge is a rising edge inductors being located to sharpen said critical edge, and wherein a second of said plurality of series connected logic gates provides a second local clock, said second local clock being a capture clock, said identified critical edge is a falling edge and said plurality of series connected logic gates further comprises: a NAND gate driven by said first inverter; and a third inverter driven by said NAND gate and driving said capture clock.