Patent ID: 6182271
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A method for placing a plurality of cells, each containing a particular pattern of first wiring, in a plurality of routing layers of a substrate, in which second wiring is previously routed, in designing an integrated circuit, said method comprising:(a) selecting at least one cell among the plural cells and a local substrate area corresponding to the selected one cell for the prospective placement of the selected one cell;(b) judging whether the second wiring of the plural routing layers overlaps the first wiring of the selected one cell in at least one of the plural routing layers inside the selected local substrate area; and(c) placing the selected one cell in the selected local substrate area if the second wiring of the plural routing layers does not overlap the first wiring of the selected one cell in any one of the plural routing layers at the selected local substrate area.