Patent ID: 9161454
Filing Date: 2015-10-13
Classification: H01L,H05K,Y10T

Abstract:
1. An electrical device package structure comprising: a dielectric layer having a first surface, a second surface opposite to the first surface, a first caving pattern disposed on the first surface and caved into the first surface, at least one second caving pattern disposed on the second surface and caved into the second surface and at least one through hole extended from the first caving pattern to the second caving pattern; an electrical device embedded in the dielectric layer and having at least one electrode and the electrode exposing the second caving pattern; a first conductive pattern filled in the first caving pattern; a second conductive pattern filled in the second caving pattern and connected with the electrode of the electrical device; a conductive via filled in the through hole and connected with the first conductive pattern and the second conductive pattern; a first solder mask disposed on the first surface and the first conductive pattern of the dielectric layer, and exposing portions of the first conductive pattern, wherein a surface of the electrical device directly contacted with the first solder mask and a surface of the first conductive pattern directly contacted with the first solder mask are located in a single plane; and a second solder mask disposed on the second surface and the second conductive pattern of the dielectric layer, and exposing portions of the second conductive pattern.