Patent ID: 8539291
Filing Date: 2013-09-17
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a first circuit having data input leads connected to the inputs of input data buffers, control output leads connected to the outputs of control output buffers, and a first scan path coupled between a test data input lead and a test data output lead, the first scan path including: B. a second circuit having data output leads coupled to respective data input leads of the first circuit and having a control input lead coupled to a control output lead of the first circuit, the data output leads being connected to the outputs of tri-state data output buffers, each tri-state data output buffer having a tri-state control input for, when active, placing the output of the tri-state data output buffer in a high impedance output state, the control input lead being connected to the input of a control input buffer, and a second scan path coupled between the test data input lead and the test data output lead, the second scan path including: C. leads coupling the first and second scan paths between the test data input lead and the test data output lead.