Patent ID: 6819135
Filing Date: 2004-11-16
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of super-regions of programmable logic, each super-region comprising: at least one region of programable logic, each region comprising at least one subregion of programmable logic; a memory region; an inter-region interconnection conductor; first interconnection circuitry configured to selectively interconnect at least one of the subregions with a region feeding conductor; second interconnection circuitry configured to selectively interconnect the region feeding conductor and the inter-region interconnection conductor; third interconnection circuitry configured to selectively interconnect the memory region and the inter-region interconnection conductor; and the first, second, and third interconnection circuitry configured such that signals can be conveyed between the memory region and the at least one of the subregions; and fast interconnection circuitry extending to all of the super-regions and configurable to receive a plurality of fast signals from a plurality of sources and to convey to each of a plurality of multiplicities of the super-regions selected ones of the fast signals.