Patent ID: 7242219
Filing Date: 2007-07-10
Classification: H03K

Abstract:
1. A circuit for a parity tree, the circuit comprising: a pull-up circuit, wherein the pull-up circuit includes a first transistor coupled between a voltage node and an inverted output node, a second transistor coupled between the output node and a first cross-couple node, and a third transistor coupled between the first cross couple node and the voltage node; a pull-down circuit, wherein the pull-down circuit includes a fourth transistor coupled between the voltage node and an output node, a fifth transistor coupled between the output node and a second cross-couple node, and a sixth transistor coupled between the second cross-couple node and a ground node; and a cross-couple circuit coupled between the pull-up circuit and the pull-down circuit; wherein for a given combination of input signals, a pull-up path exists between one the output node and the inverted output node and the voltage node through at least a portion of the pull-up circuit, and wherein a pull-down path exists between the other one of the output node and the inverted output node and the ground node through at least a portion of the pull-down circuit.