Patent ID: 8184484
Filing Date: 2012-05-22
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: memory cells for which current path is connected in series and each of which includes a charge accumulation layer and a control gate; word lines each connected to the control gate of a corresponding one of the memory cells; a driver circuit which repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to an unselected one of the word lines, and of applying a third voltage less than the second voltage to unselected two of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines, the selected one of the word lines and the unselected one of the word lines being located between the unselected two of the word lines; and a control circuit which, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold, the control circuit stepping up the second voltage after the first voltage has reached the first threshold.