Patent ID: 6467056
Filing Date: 2002-10-15
Classification: G11C

Abstract:
A method of checking a memory circuit in a semiconductor integrated circuit formed on a semiconductor chip, wherein said memory circuit is comprised of a plurality of mats, the method comprising the steps of:forming a test circuit including a data processing circuit on the semiconductor chip, said data processing circuit being comprised of: a microprogram controlled control circuit with a microprogram memory storing a predetermined algorithm, which generates a control signal for checking said memory circuit in accordance with said predetermined algorithm and reads written data, wherein said predetermined algorithm includes one of an algorithm for an all â€œ0â€  determination test, an algorithm for an all â€œ1â€  determination test, an algorithm for an N2 pattern test and an algorithm for a marching test, an arithmetic circuit which forms test data according to said control signal from said control circuit, and data determining means which determines data read from said memory circuit and outputs the result of determination; checking said mats using the test circuit in accordance with the predetermined algorithm; and using a mat judged to be free of a defect as a memory which stores the results of determination of other mats therein.