Patent ID: 8384220
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device having a buried interconnection in interconnection layers over a main surface of a semiconductor substrate, wherein electrical connection of interconnections are provided over and under an interconnection layer of a predetermined buried interconnection, among said interconnection layers, such that a first connecting conductor portion disposed in a connecting hole extending from an upper interconnection toward said interconnection layer of a predetermined buried interconnection and a second connecting conductor portion disposed in a connecting hole extending from a lower interconnection toward said interconnection layer of a predetermined buried interconnection are electrically connected in the vertical direction via a connecting conductor portion for relay disposed in a connecting groove of said interconnection layer of a predetermined buried interconnection in which electrical connections of said connecting conductor portion for relay with another conductive part is limited to an electrical connection at an upper surface thereof with said first connecting conductor portion and an electrical connection at a lower surface thereof with said second connecting conductive portion, said connecting conductor portion for relay is sized with an alignment margin so that, with respect to a plan view of said main surface of the substrate, the length of said connecting conductor portion for relay, measured in an extending direction of the predetermined buried interconnection, is larger than the width of said connecting conductor portion for relay, measured in a direction perpendicular to the extending direction, and is, at most, twice the width of said connecting conductor portion for relay in the direction perpendicular to the extending direction.