Patent ID: 6353237
Filing Date: 2002-03-05
Classification: H01L

Abstract:
An ESD protection circuit, comprising:an SCR connected between a first circuit node and a second circuit node, said SCR having a floating anode gate that is formed of a floating type N-type semiconductor layer; a diode connected between an anode that is a first P-type doped region formed in said N-type semiconductor layer and a cathode gate of said SCR that is a P-type semiconductor layer in contact with said N-type semiconductor layer to establish a junction therebetween to activate said SCR so that a potential between said first circuit node and second circuit node can be clamped at about a holding voltage of said SCR during an ESD event, wherein said diode has a cathode and an anode connected to the anode and cathode gate of said SCR; and an ohmic contact region formed in said P-type semiconductor layer; wherein said SCR has a cathode being a first N-type doped region formed in said P-type semiconductor layer, and wherein said cathode of said diode is a second N-type doped region formed in said P-type semiconductor layer.