Patent ID: 6762955
Filing Date: 2004-07-13
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory including a memory cell array having a plurality of memory cell units, one of which has a plurality of rewritable nonvolatile memory cell transistors connected in series, said nonvolatile memory cell transistors comprising:a first insulating film formed on a substrate; at least two charge storage layers formed on the first insulating film; a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, a top of the control gate having a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, the flat surface extending from one of the at least two charge storage layers to the other of the at least two charge storage layers; and a second insulating film formed between the at least two charge storage layers and the control gate, both of a bottom of the at least two charge storage layers and a bottom of the second insulating film being on a face which is substantially flat.