Patent ID: 8804406
Filing Date: 2014-08-12
Classification: G11C

Abstract:
1. An electronic storage device, comprising: a bit cell circuit adapted for connection with a first bit line and a second bit line in the storage device; a feedback circuit, the feedback circuit comprising a first transistor, the first transistor being operatively coupled to a first voltage potential, the first transistor being responsive to the first bit line; and a read accelerator circuit, the read accelerator circuit comprising second, third, and fourth transistors, the second, third, and fourth transistors being operatively coupled between the feedback circuit and a second voltage potential, the second transistor being responsive to a read line, the third transistor being responsive to the second bit line, the fourth transistor being responsive to the first bit line, the read accelerator circuit being configured to provide a discharge path for at least one of the first bit line and the second bit line during a read access of the bit cell.