Patent ID: 6064227
Filing Date: 2000-05-16
Classification: H03K

Abstract:
An output buffer circuit comprising:a low voltage power supply terminal for accepting a low voltage;a first high voltage power supply terminal for accepting a first high voltage higher than the low voltage;a second high voltage power supply terminal for accepting a second high voltage greater than the first high voltage;a control circuit for receiving a data input signal and an enable signal, and for generating a first data signal and a second data signal,the first data signal and the second data signal each being equal to the logical complement of the data input signal when the enable signal is present,the first data signal and the second data signal each having a voltage level intermediate to the low voltage and the first high voltage;a first intermediate voltage generation circuit for providing a second intermediate voltage;a level-shifting circuit connected to said control circuit and to said first intermediate voltage generation circuit for receiving the first data signal and the second intermediate voltage, and for generating a third data signal having a voltage intermediate to a first intermediate voltage and the second high voltage; andan output circuit comprising first and second P-channel transistors connected in series between said second high voltage power supply terminal and an output terminal, and first and second N-channel transistors connected in series between said low voltage power supply terminal and said output terminal,said first P-channel transistor having a gate operatively connected to said level-shifting circuit to receive the third data signal, said second P-channel transistor having a gate operatively connected to said first intermediate voltage generation circuit to receive the second intermediate voltage, said first N-channel transistor having a gate operatively connected to said control circuit to receive the second data signal, said second N-channel transistor having a gate operatively connected to receive a third intermediate voltage; anda second intermediate voltage generating circuit for generating said third intermediate voltage,said second intermediate voltage generating circuit having a second series combination of a plurality of series short-circuited N-channel transistors and a plurality of series diode-connected N-channel transistors,said second series combination being connected between said low voltage power supply terminal and said first high voltage power supply terminal, andeach of said plurality of series short-circuited N-channel transistors having a connection between its source and its gate, and a connection between its drain and its gate.