Patent ID: 9013228
Filing Date: 2015-04-21
Classification: H03K

Abstract:
1. A method to provide power to an integrated system, comprising: providing the integrated system with supply, ground, and body bias voltages, the body bias voltages including a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage; selecting out of the voltages provided, voltages to bias bodies of MOS transistors of a processing unit in the integrated system; and supplying through a branch the bodies of the n-channel MOS transistors of the processing unit with at least one of the voltages selected, the branch including three sub-branches, each sub-branch having only two n-channel branch transistors between an input of the respective sub-branch and an output of the respective sub-branch, the two n-channel branch transistors mounted in series such that at least one of the branch transistors is off when the respective sub-branch is not selected, a first one of the two n-channel branch transistors of a first sub-branch controllable with a first signal level or a second signal level, and a second one of the two n-channel branch transistors of the first sub-branch controllable with the second signal level or a third signal level, the first signal level, the second signal level, and the third signal level all different from each other.