Patent ID: 6243284
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A multivalued mask ROM comprising:a plurality of word lines;a plurality of bit lines which are wired in directions crossing with the plurality of word lines respectively;a plurality of cell transistors, which are arranged in a matrix form at intersection points at which the word lines and the bit lines intersect; andat least one of a ground line being connected with ground potential and a power source line being connected with power source potential,wherein gates of the cell transistors which align along each of the word lines are connected with a same word line,one of source and drain of each of the plurality of cell transistors which align along each of the bit lines is connected with one of the bit line, the ground line or the power source line, while the other of the source and drain is connected with a line which is not connected with one of the source and drain within the bit line, ground line or power source line, andwherein all of the ground lines are connected together at a common ground potential level, and connections between the bit lines, ground lines and power source lines and source and drain of each cell transistor are made according to any one of the following combinations:(1) none of the source and drain are connected to any of the lines;(2) one of the source and drain is connected to one bit line, while the other is connected to the GND line; and(3) the source and drain are connected to adjacent bit lines respectively.