Patent ID: 8072792
Filing Date: 2011-12-06
Classification: G11C,H01L,Y10T

Abstract:
1. An integrated circuit, comprising: a plurality of voltage supply contacts; a plurality of resistive memory cells, each comprising a resistive memory element and an active area by means of which the resistive memory element may be brought into signal connection with a voltage supply contact; and a plurality of wordlines and a plurality of bitlines adapted to select a predetermined resistive memory cell, wherein at least four resistive memory cells are in signal connection with a given one of the plurality of voltage supply contacts, wherein of said at least four resistive memory cells, two resistive memory elements are arranged above or under one bitline and two other resistive memory elements are arranged above or under another bitline, and wherein of said at least four resistive memory cells, two active areas are arranged above or under one wordline and two other active areas are arranged above or under another wordline, wherein a direction of a current that flows in each active area is at an angle other than 90° with respect to an orientation of the plurality of wordlines.