Patent ID: 6070259
Filing Date: 2000-05-30
Classification: G01R

Abstract:
A scannable dynamic logic element comprising:first and second supply terminals;a clock input;a test enable input;a data output;a precharge circuit coupled between the first supply terminal and the data output and having a precharge control input coupled to the clock input;a boolean pull-down circuit coupled between the data output and the second supply terminal and comprising a logic data input, a first evaluation control input which is coupled to the clock input and a first enable input which is coupled to the test enable input; anda test scan pull-down circuit comprising a test enable transistor, a test data input transistor and an evaluation transistor which are coupled together in series between the data output and the second supply terminal, wherein the test enable transistor has a control terminal, which is coupled to the test enable input, the test data input transistor has a control terminal, which forms a test data input, and the evaluation transistor has a control terminal, which forms a second evaluation control input and is coupled to the clock input.