Patent ID: 6980586
Filing Date: 2005-12-27
Classification: H04J,H04L

Abstract:
1. A pseudo-noise encoded digital data clock recovery circuit for recovering an original bit stream from a received chip stream, comprising: a correlator to correlate a pseudo-noise sequence with the received chip stream and generating a correlator output, the pseudo-noise sequence to modulate the original bit stream; a phase controller, coupled to the correlator to histogram the correlator output of the correlator over the plurality of bit periods, wherein the phase controller includes a plurality of counters to histogram the correlator output over all sample positions in a bit period for the plurality of consecutive bit periods, each of the counters corresponding to each of the sample positions within the bit period and, wherein each of the counters is incremented when a corresponding thresholded correlator output generates a spike at the corresponding sample position; and a bit clock generator, coupled to the phase controller, to generate a bit clock which determines a sampling position of the received chip stream to recover the original bit stream from the received chip stream, the bit clock generator to use the histogram of the correlator output to select/adjust the sample position for the bit clock, wherein the bit clock generator adjusts the sample position of the bit clock to a position where the corresponding counter exceeds a threshold and, wherein the bit clock generator retains the same sample position of the bit clock where no counters exceed the threshold.