Patent ID: 6180451
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of forming a DRAM capacitor, comprising:providing a semiconductor substrate comprising at least a gate and source/drain region;forming an insulation layer to cover the gate and the source/drain region;forming a contact plug penetrating the insulation layer to couple with the source/drain region;forming and patterning a doped amorphous silicon layer to couple with the contact plug;performing a first annealing process to transform the doped amorphous silicon layer into a poly-silicon layer and to form a hemispherical grain structure on a surface of the poly-silicon;performing a second annealing process in a dopant-containing ambient on the poly-silicon layer and the hemispherical grain structure;forming a dielectric layer to cover the poly-silicon layer and the hemispherical grain structure; andforming a top electrode to cover the dielectric layer.