Patent ID: 8129757
Filing Date: 2012-03-06
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a substrate region; and a gate electrode level region formed above the substrate region, the gate electrode level region having a size of up to about 965 nanometers as measured in any direction parallel to the substrate region, the gate electrode level region including at least six linear-shaped conductive structures each formed to extend lengthwise in a first direction, the at least six linear-shaped conductive structures including — a first linear-shaped conductive structure including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, the first linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the first linear-shaped conductive structure, a second linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the first transistor type, the second linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the second linear-shaped conductive structure, a third linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the second transistor type, the third linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the third linear-shaped conductive structure, a fourth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the first transistor type, the fourth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fourth linear-shaped conductive structure, a fifth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the second transistor type, the fifth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fifth linear-shaped conductive structure, a sixth linear-shaped conductive structure including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, the sixth linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the sixth linear-shaped conductive structure, wherein the substrate region includes a non-active region between transistors of the first transistor type and transistors of the second transistor type, wherein each non-gate portion of the first, second, third, fourth, fifth, and sixth linear-shaped conductive structures extends over the non-active region of the substrate region, and wherein at least two of the non-gate portions of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.