Patent ID: 6166606
Filing Date: 2000-12-26
Classification: G09G,H03L,H04N

Abstract:
An apparatus comprising:a system clock input providing a system clock;a synchronizing signal input providing a sequence of synchronizing pulses;a voltage-controlled oscillator for generating an output clock running at an output clock frequency, said voltage-controlled oscillator having a stop/start input connected to said synchronizing signal input, a correction signal input for controlling said output clock frequency; anda feedback circuit connected to said output clock of said voltage-controlled oscillator and said system clock signal for producing said correction signal input for said voltage-controlled oscillator,wherein said correction signal is generated by comparing a first pulse duration of at least one cycle of the output of the voltage-controlled oscillator with a second pulse duration of the same number of cycle of said system clock, wherein each of the synchronizing pulses resets said voltage-controlled oscillator.