Patent ID: 8953783
Filing Date: 2015-02-10
Classification: G06F,H04L

Abstract:
1. An arithmetic device connected to a memory device, the arithmetic device comprising: an arithmetic processing circuit configured to perform a plurality of arithmetic processes, the plurality of arithmetic processes being executed in a sequence according to an encryption method; an address generating circuit configured to generate addresses in the memory device, which stores, in consecutive addresses, N pieces of data (N being an integer) for each of a plurality of types of data used for the plurality of arithmetic processes, based on an upper bit and an offset, the upper bit being an upper bit of an address of a first piece of data from among the N pieces of data for one of the plurality of types of data, and the offset being a value corresponding to a counter value and being based on the address of the first piece of data; and a controller configured to control the arithmetic processing circuit so that each of the plurality of arithmetic processes is executed in the sequence and to specify an update of the counter value at a timing of modifying the type of the data and at a timing of modifying the data used in the plurality of arithmetic processes.