Patent ID: 6088518
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A method for porting an integrated circuit layout from a reference process to a target process comprising the steps of:(a) placing components related to the reference process on a grid, wherein the grid is determined by equations that are based upon the architecture of the layout;(b) determining a grid for the target process using the equations with target process design rules wherein step (b) further comprises:(b1) providing a minimum dimension of the components for the reference process;(b2) providing a minimum overlap of the components for the reference process;(b3) converting the minimum dimension and the minimum overlap for the reference process to minimum dimension and minimum overlap for the target process based upon design rules of the target process; and(c) mapping the location of the components on the grid of the target process gridpoint to gridpoint from the reference process to the target process.