Patent ID: 6204137
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method to form transistor gates in the manufacture of an integrated circuit device comprising:depositing a silicon nitride layer overlying a semiconductor substrate;patterning said silicon nitride layer and said semiconductor substrate to form trenches for planned shallow trench isolations;depositing a trench oxide layer overlying said silicon nitride layer and filling said trenches;polishing down said trench oxide layer to said silicon nitride layer to complete said shallow trench isolations;thereafter patterning said silicon nitride layer to form dummy gates where said transistor gates are planned;depositing an oxide liner layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;implanting ions into said semiconductor substrate to form lightly doped drain junctions;forming sidewall spacers adjacent to said dummy gates and said shallow trench isolations;thereafter implanting ions into said semiconductor substrate to form source and drain junctions;thereafter depositing an interlevel dielectric layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;polishing down said interlevel dielectric layer to said dummy gates;etching away said dummy gates to form openings for planned transistor gates;depositing a gate oxide layer lining said openings for planned transistor gates;depositing a gate electrode layer overlying said gate oxide layer and filling said openings for planned transistor gates; andpatterning said gate electrode layer to complete said transistor gates and to complete the local interconnects for said transistors in the manufacture of the integrated circuit device.