Patent ID: 6658544
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A method, comprising:specifying an asynchronous memory design with a number of macros; selecting at least one of the macros to include a synchronous memory in the asynchronous memory design, wherein the synchronous memory defined by the at least one of the macros includes a clock input and the circuitry defined by the at least another of the macros includes: a detection circuit responsive to one or more memory address inputs to generate a trigger signal; and a monostable multivibrator circuit responsive to the trigger signal to change a control signal provided to the clock input from a first state to a second state and the monostable multivibrator circuit is further responsive to the interlock signal to change the control signal from the second state to the first state; selecting at least another of the macros to include circuitry in the asynchronous memory design to asynchronously control access to the synchronous memory; and defining the synchronous memory to provide an interlock signal to the circuitry.