Patent ID: 6984890
Filing Date: 2006-01-10
Classification: H01L

Abstract:
1. A power semiconductor package, comprising a substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a first power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which a first power electrode and a control electrode are disposed and a bottom surface including a second power electrode; a second power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which a first power electrode and a control electrode are disposed and a bottom surface including a second power electrode; a plurality of conductive pads disposed only at the second side edge of the substrate on the upper surface; at least, one wire bond extending from the control electrode of the first power semiconductor die to one of the conductive pads; at least another wire bond extending from the control electrode of the second power semiconductor die to another one of the conductive pads and a plurality of wire bonds being extended from the first power electrode of the first power semiconductor die to the first power electrode of the second semiconductor die.