Patent ID: 6369596
Filing Date: 2002-04-09
Classification: G01R

Abstract:
An arrangement for testing integrated circuit devices, said arrangement comprisinga test fixture defined as comprising a top major surface and a bottom major surface and including a plurality of bond pad sites disposed in a predetermined pattern on said top major surface, said test fixture further comprising a first vacuum port disposed therethrough and at least a second vacuum port; and a test socket defined as including a recessed top portion and an opposing bottom surface, said test socket including a plurality of alignment features protruding beyond said bottom surface for mating with selected ones of said test fixture bond pad sites upon placement of said test socket upon said test fixture, said test socket further comprising a vacuum channel formed within said bottom surface and disposed to align with the first vacuum port of said test fixture such that upon application of a vacuum force said test socket will remain in physical contact with said text fixture, said test socket including at least one vacuum port aligned with said test fixture at least a second vacuum port such that upon insertion of an integrated circuit device in the recessed top portion of said test socket said integrated circuit device will be pulled into physical contact with said test socket by a vacuum applied thereto.