Patent ID: 7583218
Filing Date: 2009-09-01
Classification: H03K

Abstract:
1. A comparator that outputs a comparison result obtained by comparing two signals, comprising: a positive buffer that converts a positive comparison signal, which has a level according to a difference between the two signals, into a positive logic signal that indicates a logic level; a negative buffer that converts a negative comparison signal, which has a level that is inverted in relation to the positive comparison signal, into a negative logic signal that indicates a logic level that is inverted in relation to the positive logic signal; a latch core that, at a timing at which a latch period in which the comparison result is held begins, acquires the logic level of the positive logic signal and the logic level of the negative logic signal and holds the acquired logic levels; and a potential control section that, prior to a timing at which the latch period ends, sets an output end of the positive buffer to have a potential that is identical to that of an output end of the negative buffer.