Patent ID: 8396089
Filing Date: 2013-03-12
Classification: H03F

Abstract:
1. An apparatus comprising: a plurality of input pins; a plurality of filters, wherein each filter is coupled to at least one of the input pins; a multiplexer having a plurality of multiplexer inputs and a plurality of multiplexer outputs, wherein each multiplexer input is coupled to at least one of the filters; an amplifier stage that is coupled to each multiplexer output forming a signal path for each multiplexer output, wherein the amplifier stage includes a clamp that is adapted to clamp at least one of the multiplexer outputs; a plurality of buffers, wherein each buffer is coupled between at least one of the multiplexer outputs and the amplifier stage; a plurality of switches, wherein at least one of the switches is coupled between each buffer and the amplifier stage; and a controller that is coupled to the multiplexer and each of the switches, wherein the controller is adapted to actuate each of the switches coupled between its corresponding buffer and the amplifier stage so as to switch the corresponding buffer into one of the signal paths when a clamping condition occurs.