Patent ID: 6452834
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A dynamic random access memory (DRAM) cell comprising:an access transistor adapted to be activated by a word line (WL) coupled to said access transistor, said access transistor adapted to control data access to said DRAM cell; a read-amplifying (RA) transistor having a gate whose charge level is adapted to represent a binary bit being stored by said DRAM cell, said gate coupled to said access transistor; a write bit line (WBL) coupled to said access transistor, said WBL adapted to transfer a binary bit into said DRAM cell; a read bit line (RBL) coupled to said RA transistor, said RBL adapted to transfer out of said DRAM cell a binary bit that indicates the charge level present on the gate of said RA transistor; a read control line (RCL) coupled to said RA transistor, wherein in response to said RA being activated, said RCL is adapted to provide to said RBL a current that is amplified by said activated RA transistor.