Patent ID: 8039886
Filing Date: 2011-10-18
Classification: G11C,H01L

Abstract:
1. A depletion-type NAND flash memory comprising: a NAND string composed of a plurality of serially connected depletion-type FETs; a control circuit which controls gate potentials of the plurality of depletion-type FETs in a read operation; a particular potential storage; and an adjacent memory cell threshold storage, wherein each of the plurality of depletion-type FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer; the adjacent memory cell threshold storage stores a threshold of a source line side depletion-type FET adjacent to a source line side of a selected depletion-type FET; and the control circuit applies a potential to the gate electrode of the source line side depletion-type FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.