Patent ID: 8737118
Filing Date: 2014-05-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first SRAM cell and a second SRAM cell: a write circuit connected to a write enable signal, a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first sense amplifier provided with the first bit line pair; a second sense amplifier provided with the second bit line pair; a first switch circuit provided between the first bit line pair and the second bit line pair and connected to a first control signal different from the write enable signal; and a controller configured to control the first switch circuit by the first control signal to render the first bit line pair and the second bit line pair conductive at a first timing, in a case of testing the first SRAM cell, wherein the first switch circuit is provided between the first sense amplifier and the second sense amplifier.