Patent ID: 6034427
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A package for supporting at least one integrated circuit chip, said package having a first outer surface and a second outer surface opposite said first outer surface, said package comprising:a dielectric layer located between said first outer surface and said second outer surface.a plurality of chip bonding pads supported by at least said dielectric layer and formed in a first predetermined configuration suitable for connection to a plurality of pads on said integrated circuit chip;a plurality of ball attach pads supported by at least said dielectric layer and formed in a second predetermined configuration;an electrical conductor formed at least in the center of a hole defined by said dielectric layer, said electrical conductor being part of an electrical path between one of said ball attach pads and one of said chip bonding pads, said electrical conductor including at least one conductive particle and a binding material; anda portion of an electrically conductive layer, said portion having a contiguous surface covering said hole, said contiguous surface being in contact with said electrical conductor.