Patent ID: 7456489
Filing Date: 2008-11-25
Classification: G03F,H01L

Abstract:
1. A wafer which wafer comprises a number of exposure fields and which wafer comprises a number of lattice fields in each exposure field, wherein each lattice field contains an IC and each IC contains a plurality of IC components, and which wafer comprises a first group of first saw paths and a second group of second saw paths wherein all of the first saw paths of the first group run parallel to a first direction and have a first path width and wherein all of the second saw paths of the second group run parallel to a second direction intersecting the first direction and have a second path width and wherein the first saw paths and the second saw paths are provided and designed for a subsequent segregation of the lattice fields and the ICs contained therein, and wherein in each exposure field at least two control module fields are provided, each of which control module fields runs parallel to the first direction and thus to the first saw paths and contains at least one optical control module, wherein each control module contains a plurality of control module components, and wherein each control module field within an exposure field comprises a plurality of control module field sections and is distributed among several lattice fields, and wherein each control module field section is located in a lattice field and contains at least one control module component.