Patent ID: 9043585
Filing Date: 2015-05-26
Classification: G06F,Y02D

Abstract:
1. An apparatus, comprising: an interface for communicating with a plurality of digital signal processors; logic coupled to the interface and configured to send and receive data via the interface; wherein the logic is configured to determine an operating state for each of the plurality of digital signal processors, wherein the operating state is selected from a group comprising a ready state, a first energy saving state, and a second energy saving state; wherein the logic is configured to determine a first number of digital signal processors selected from the plurality of digital signal processors to operate in the ready state, select a first set of digital signal processors corresponding to the first number of digital signal processors to operate in the ready state, and signal the first set of digital signal processors via the interface to operate in the ready state; wherein the logic is configured to determine a second number of digital signal processors selected from the plurality of digital signal processors to operate in the first energy saving state, select a second set of digital signal processors to be maintained in the first energy saving state corresponding to the second number of digital signal processors, and signal the second set of digital signal processors via the interface to operate in the first energy saving state; wherein the logic is configured to determine a third number of digital signal processors selected from the plurality of digital signal processors to operate in the second energy saving state, select a third set of digital signal processors corresponding to the third number of digital signal processors to operate in the second energy saving state, and signal the third set of digital signal processors to operate in a second energy saving state; wherein the logic is configured to determine a set of digital signal processors that will be handling a selected digital signal processing task, and manage an operating state of one or more of the plurality of digital signal processors in accordance with the set of digital signal processors that will be handling the selected digital signal processing task; and wherein the logic determines the second number of digital processors to be maintained in the first energy saving state based temporal data associated with a plurality of calls.