Patent ID: 8341583
Filing Date: 2012-12-25
Classification: G06F

Abstract:
1. A packaging design supporting device for placing logic cells in a semiconductor integrated circuit and designing wirings between the logic cells, the packaging design supporting device comprising: a selection data acquisition unit that selects one of logic cells and inputs a change with respect to the selected logic cell; a bulk fix data generation unit that generates bulk fix data by which a bulk layer of the semiconductor substrate is fixed, and places a design-change dummy logic cell which is not wired in a region where no logic cell is placed in the bulk layer after the bulk fix data are generated, and generates a design-change logic cell by wiring the design-change dummy logic cell in the region where the design-change dummy logic cell is placed after the bulk fix data are generated; and a selection cell move determination unit that prohibits the change with respect to the selected logic cell when the bulk fix data generation unit generates the bulk fix data and the change with respect to the selected logic cell is input to the selection data acquisition unit.