Patent ID: 6080633
Filing Date: 2000-06-27
Classification: H01L

Abstract:
A method for forming the lower electrode of a capacitor comprising:providing a semiconductor substrate;forming a first dielectric layer over the substrate;forming a silicon nitride layer over the first dielectric layer;forming an oxide layer on the silicon nitride layer;patterning the oxide layer, the silicon nitride layer and the first dielectric layer to form a contact opening exposing a specified region of semiconductor substrate;forming a first conductive layer over the oxide layer that also fills the contact opening making electrical connection with the specified region in the substrate;forming a first hemispherical grained silicon layer over the first conductive layer;forming a second dielectric layer over the first hemispherical grained silicon layer;patterning the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer to expose a portion of the oxide layer;forming a second conductive layer over the second dielectric layer, the first conductive layer and the oxide layer;forming a second hemispherical grained silicon layer over the second conductive layer;removing a portion of the second conductive layer and the second hemispherical grained silicon layer that lies above the oxide layer and the second dielectric layer to expose the oxide layer and the second dielectric layer, and resulting in a portion of the second conductive layer and the second hemispherical grained silicon layer that remains attached to the sidewalls of the second dielectric layer and the first conductive layer; andremoving the second dielectric layer, wherein the oxide layer is also removed.