Patent ID: 6709915
Filing Date: 2004-03-23
Classification: H01L,Y10S

Abstract:
A method for forming an integrated circuit memory device comprising the steps of:providing a semiconductor substrate having active regions; forming a plurality of word line structures on the active regions; forming word line contact plugs, each of which is disposed between adjacent word line structures; forming an insulating layer on the semiconductor substrate and the word line contact plugs; forming bit line structures on the insulating layer so as to be in electrical contact with predetermined word line contact plugs selected from among the word line contact plugs; depositing an interlayer insulating layer on the bit line structures; forming an etch stopper on the interlayer insulating layer; forming storage node contact holes by etching predetermined portions of the interlayer insulating layer and the etch stopper to expose non-selected word line contact plugs; forming storage node contact plugs in the storage node contact holes; forming storage node electrodes to be in electrical contact with the storage node contact plugs; removing the remaining etch stopper to expose surfaces on upper portions of the storage node contact plugs; forming a dielectric layer on the exposed surfaces of the storage node contact plugs and the storage node electrodes; forming a plate electrode on the dielectric layer; and selectively removing the interlayer insulating layer between the storage node contact plugs to expose surfaces of the storage node contact plugs.