Patent ID: 7779199
Filing Date: 2010-08-17
Classification: G06F,G11C,Y02D

Abstract:
1. A storage device, comprising: a flash memory device being a main storage medium; a cache memory for use for the flash memory device; and a control circuit, wherein based on a write command and address information provided from outside, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data, wherein a unit cell is set based on a write unit or an erase unit of the flash memory device, and the unit cell includes a plurality of sectors, and when a write command comes for writing of block data to any of the sectors or successive sector groups, the control circuit segments the block data into sub blocks in accordance with the unit cell, and selects either the flash memory device or the cache memory as the writing destination of each of the sub blocks in accordance with predetermined criteria for each of the sub blocks, wherein the unit cell includes one or more writing pages, and is a collective write unit of the flash memory device, and wherein for each of the sub blocks, the control circuit checks an entry of the cache memory corresponding to the unit cell or data therein, and based on a check result, selects the writing destination for each of the sub blocks.