Patent ID: 6525559
Filing Date: 2003-02-25
Classification: H03K,H04L

Abstract:
A fail-safe biasing circuit comprising:a pair of differential inputs including a first differential input and a second differential input that are driven to opposite states during data reception; a first pull-up between the first differential input and a power supply, the first pull-up having a first switching transistor having a first channel in series with a first resistor, the first switching transistor conducting current in the first channel in response to a voltage on a first gate node connected to a gate of the first switching transistor; a first connecting transistor that conducts current between the first differential input and the first gate node when power is off and the power supply is grounded; a first grounding transistor that conducts current between a ground and the first gate node when the power is on and the power supply is not grounded; a second pull-up between the second differential input and a power supply, the second pull-up having a second switching transistor having a second channel in series with a second resistor, the second switching transistor conducting current in the second channel in response to a voltage on a second gate node connected to a gate of the second switching transistor; a second connecting transistor that conducts current between the second differential input and the second gate node when the power is off and the power supply is grounded; and a second grounding transistor that conducts current between a ground and the second gate node when the power is on and the power supply is not grounded, whereby leakage currents in the first and second pull-ups are reduced when power is off by biasing the first and second gate nodes to turn off the first and second switching transistors.