Patent ID: 8045390
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A system comprising: a memory array having a number of memory cells; a number of word lines each coupled to at least one of the memory cells in a corresponding row; a number of bit lines each coupled to at least one of the memory cells in a corresponding column; a set of dynamic reference cells, each dynamic reference cell being connected to one of the word lines to provide a dynamic reference value for determining a status of at least one of the memory cells coupled to a word line corresponding to the dynamic reference cell; a number of first sensing amplifier each coupled to the memory cells in a corresponding column for reading a cell value of at least one of the memory cells coupled to the corresponding word line; a second sensing amplifier coupled to the set of dynamic reference cells for reading a dynamic value from one of the dynamic reference cells; a mini-cell reference array providing a static reference value that remains substantially stable over time; a number of comparators each coupled to an associated first sensing amplifier and the mini-cell reference array as well as the second sensing amplifier for comparing the cell value, the dynamic reference value and the static reference value directly from the mini-cell reference array to determine a status of one memory cell in the corresponding column, wherein the dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the memory cells coupled with the corresponding word line by sharing the same word lines with the memory cells, each of the dynamic reference cell operates through a same cycle as the associated memory cells, each cycle including a programming process and an erasing process.