Patent ID: 6436762
Filing Date: 2002-08-20
Classification: H01L

Abstract:
An improved process for fabricating an array of memory cells on a dynamic random access memory (DRAM) device comprising the steps of:providing a semiconductor substrate having partially completed DRAM devices consisting of an array of device areas surrounded and electrically isolated by field oxide regions, each of said device areas having field effect transistors with gate electrodes and first and second source/drain areas having first and second plug contacts, respectively, said plug contacts extending upward through an interpolysilicon oxide (IPO) layer; forming crown capacitors on said substrate electrically contacting said first plug contacts; forming a blanket conformal conducting layer over said capacitors for capacitor top electrodes; using a patterned photoresist mask and anisotropically etching to pattern said conducting layer and forming openings in said conformal conducting layer aligned over said second plug contacts; and further, recessing said openings in said conformal conducting layer under said photoresist mask by isotropic etching to increase critical dimensions for bit-line openings; removing said photoresist mask; depositing an interlevel dielectric layer on said substrate and etching bit-line contact openings in said interlevel dielectric layer aligned over and within said openings in said conducting layer, and further etching to said second plug contacts, wherein said recessed openings in said conformal conducting layer improves the isolation margin between said capacitor top electrodes and said bit-line contact openings; forming bit-line contact plugs in said bit-line contact openings to said second plug contacts and depositing and patterning a second conducting layer to form bit lines to complete said array of memory cells.