Patent ID: 6708303
Filing Date: 2004-03-16
Classification: G01R

Abstract:
A scan circuit comprising:normal data input; a scan data input; a scan enable input; a normal data output; a scan data output; a clock input; a multiplexer having a first input coupled to said normal data input, a second input coupled to said scan data input, an output, and a control input coupled to said scan enable input, said multiplexer coupling said first input to said output when said control input has a first logic state and connecting said second input to said output when said control input has a second logic state different from the first logic state; an operational circuit including a flip-flop having a clock input coupled to said clock input of said scan circuit, a data input coupled to said output of said multiplexer, a data output coupled to said normal data output of said scan circuit and an inverted data output having an opposite digital state than said normal data output; and a NAND gate having a first input coupled to said inverting data output of said flip flop, a second input coupled to said scan enable input, and an output coupled to said scan data output.