Patent ID: 9025400
Filing Date: 2015-05-05
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a plurality of memory units respectively comprising a plurality of memory cells; a data bus shared by the memory units and transferring data from the memory units or to the memory units; and a timing controller comprising a delay time unit shared by the memory units sharing the data bus, the timing controller being configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal, wherein the delay time unit comprises: a latch circuit configured to latch an input signal; a delay element configured to output a latched signal in the latch circuit after a predetermined delay time elapses since receiving the input signal; a logical gate configured to activate an output when both an output of the latch circuit and an output of the delay element are activated; and a pulse-width-determining delay element connected between the delay element and the latch circuit, the pulse-width-determining delay element being configured to determine a pulse width of a signal output from the logical gate.