Patent ID: 8048746
Filing Date: 2011-11-01
Classification: H01L

Abstract:
1. A method of forming an integrated circuit on a substrate, the integrated circuit having a memory cell region including a plurality of memory cell transistors each having a gate electrode, and a peripheral region including low voltage transistors (LVT) and high voltage transistors (HVT) outside of the memory cell region, the method comprising: forming a first trench isolation (TI) within the memory cell region for isolating at least one of the memory cell transistors, and forming a second trench isolation (TI) for isolating at least one of the low voltage transistors (LVT) and forming a third trench isolation (TI) for isolating at least one of the high voltage transistors (HVT); and forming a tunnel barrier layer having first and second dielectric layers within the memory cell region between the gate electrodes of the memory cell transistors and the substrate, and within the peripheral region.