Patent ID: 6049484
Filing Date: 2000-04-11
Classification: G11C

Abstract:
A method to erase a flash EEPROM cell, which is comprised of a control gate, a floating gate, a source, a drain, and a tunneling oxide disposed upon a semiconductor substrate, to improve a write/erase threshold voltage closure from repeatedly writing and erasing said flash EEPROM cell, comprising the steps of:erasing said flash EEPROM cell by the steps of,applying a large positive voltage pulse to the source of said EEPROM cell,concurrently applying a ground reference potential to said control gate and semiconductor substrate,concurrently floating said drain; and thendetrapping said flash EEPROM cell by the steps of:floating said source and drain,concurrently applying the ground reference potential to said semiconductor substrate,concurrently applying a relatively large negative voltage pulse to said control gate.