Patent ID: 6118157
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method for blocking a voltage comprising:applying the voltage to a drain region of a split-gate MOS transistor;applying a second voltage to a source region and to a substrate region of the split-gate MOS transistor, the substrate region defining a channel area separating the source and the drain regions;applying the second voltage to a first gate of the split-gate MOS transistor, the first gate overlapping a portion of the source region and extending along a portion of said channel area; andapplying a third voltage to a second gate of the split-gate MOS transistor, the second gate overlapping a portion of the drain region and the first gate, and extending along a remaining portion of the channel area, wherein a dielectric material separates the first and second gates from one another and from the substrate, wherein the third voltage is greater than the second voltage, wherein the first voltage is greater than the third voltage and is blocked from reaching the source region, and wherein the split-gate MOS transistor does not enter the gated-diode breakdown region.