Patent ID: 8202781
Filing Date: 2012-06-19
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising the steps of: etching a silicon substrate to form a plurality of silicon pillars; filling a first insulation layer into gaps between the silicon pillars, excluding gate forming gaps; etching isotropically surfaces of lower portions of the silicon pillars in the gate forming gaps not filled with the first insulation layer; forming gates in the lower portions of the silicon pillars which are isotropically etched; removing the first insulation layer; forming drain areas in portions of the silicon substrate below the gates; forming a second insulation layer to fill the gaps between the silicon pillars having the gates selectively formed on a surface of the lower portions thereof; forming word lines in the second insulation layer to connect gates arranged in a direction; forming a third insulation layer to fill the gaps between the silicon pillars including the word lines; forming source areas in portions of the silicon pillars over the gates, such that the source areas, the drain areas, and the gates constitute vertical pillar transistors; and annealing the resultant silicon substrate formed with the source areas, such that the drain areas of the vertical pillar transistors are connected with one another, wherein the drain areas arranged perpendicular to the direction of the word lines, wherein the gates are respectively formed only on opposite surfaces of two adjacent vertical pillar transistors, such that the gates of the two adjacent vertical pillar transistors face each other.