Patent ID: 6742012
Filing Date: 2004-05-25
Classification: G06F

Abstract:
Apparatus for processing data, comprising:a multiplying circuit including: an adder tree for performing multiplication and addition operations in order to generate an output of size 3W/2 bits, and at least one recirculate path for routing selected bits of said output to an input of said adder tree, and an instruction decoder responsive to a multiply instruction to control said multiplying circuit to generate a multiplication result for the computation MÃ—N, where M and N are W bit data words, wherein the multiplying circuit is arranged to execute a first operation in which the data word N is multiplied by the most significant W/2 bits of the data word M to generate a first intermediate result having 3W/2 bits, and to then execute a second operation in which the data word N is multiplied by the least significant W/2 bits of the data word M to generate a second intermediate result having 3W/2 bits, wherein the mulitiplying circuit is arranged to shift the first intermediate result by W/2 with respect to the second intermediate result, and wherein the adder tree is arranged to add the shifted first intermediate result to the second intermediate result to generate the multiplication result.