Patent ID: 6768343
Filing Date: 2004-07-27
Classification: H03K

Abstract:
A cascaded chain of clocked half-rail differential logic circuits with sense amplifier and shut-off comprising:a first clocked half-rail differential logic circuit with sense amplifier and shut-off, said first clocked half-rail differential logic circuit with sense amplifier and shut-off comprising: a first clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal; a first clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal; at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal; and at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal; a second clocked half-rail differential logic circuit with sense amplifier and shut-off, said second clocked half-rail differential logic circuit with sense amplifier and shut-off comprising: a second clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal; a second clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal; at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal; and at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal; a first clock signal coupled to said first clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal; a second clock signal coupled to said second clocked half-rail differential logic circuit with sense amplifier and shut-off first clock in terminal and said first clocked half-rail differential logic circuit with sense amplifier and shut-off second clock in terminal, wherein; said at least one first clocked half-rail differential logic circuit with sense amplifier and shut-off data out terminal is coupled to said at least one second clocked half-rail differential logic circuit with sense amplifier and shut-off data in terminal, further wherein; said second clock signal is delayed with respect to said first clock signal by a predetermined delay time.