Patent ID: 6320814
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A semiconductor device comprising a memory having X rows or X columns, where X is between Nth power of 2 and (N-1) th power of 2, and N is an natural number, an address decoder that decodes an address signal addressing rows or columns of said memory for an intermediate word size to be accessed, and a surplus address detection circuit that detects accesses to addresses larger than said X by the said address signal, wherein:said address decoder is equipped with plural pre-decoders that decode the address signals classified into plural groups, and a post-decoder that generates a selection signal to select a row or column to be accessed by combining the outputs of said plural pre-decoders;said surplus address detection circuit detects accesses to addresses larger than said X by the outputs of said plural pre-decoders; andthe number of input signals of said surplus address detection circuit is smaller than that of outputs of said plural pre-decoders.