Patent ID: 6788562
Filing Date: 2004-09-07
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in an array: anda plurality of selection transistors arranged respectively on one side and on another side opposing to said one side of sad memory cell array; wherein two electrically conductive regions formed in separation from each other on the substrate surface are interconnected to form a set of sub bit lines, the set of the sub bit lines being connected to one main bit line via an associated one of the selection transistors; and wherein there are arranged, in a region in the memory cell array area defined between a pair of electrically conductive regions composing one set of said sub bit lines, each one of paired electrically conductive regions forming two sets of sub bit lines respectively connected via selection transistors to two main bit lines on both sides adjacent to a main bit line associated with the set of the sub bit lines, and each one of paired electrically conductive regions forming two sets of sub bit lines respectively connected to the two neighboring main bit lines via selection transistors on the opposite side of the memory cell array, totaling at four sub bit lines.