Patent ID: 8119497
Filing Date: 2012-02-21
Classification: H01L,H05K

Abstract:
1. A method for forming an electronic, optical or optoelectronic circuit member comprising: providing a plurality of semiconductor chips, each including an integrated circuit formed on an active surface of said semiconductor chip; forming a releasable bond layer over each of said semiconductor chips in contact with said active surface; coupling an associated die mount to each of said semiconductor chips through said associated releasable bond layer; grinding each of said semiconductor chips from a second surface opposite said active surface, to reduce thickness thereof, thereby forming a corresponding plurality of reduced thickness semiconductor chips; joining at least one of said reduced thickness semiconductor chips to a first dielectric layer; removing said associated releasable bond layer and said die mounts from each of said at least one reduced thickness semiconductor chip; and forming at least a second dielectric layer over said first dielectric layer and over said at least one reduced thickness semiconductor chip to form said electronic, optical or optoelectronic circuit member.