Patent ID: 8291357
Filing Date: 2012-10-16
Classification: H01L

Abstract:
1. An identification circuit for a chip, said identification circuit comprising: multiple pairs of conductors on said chip, said pairs of conductors being electrically connected in parallel, and each of said multiple pairs of conductors comprising: a first conductor; a second conductor separated from said first conductor by approximately a specific distance; and between said first conductor and said second conductor, one of a short and an open, said specific distance being predetermined such that the occurrence of any one of said short and said open is possible between any one of said multiple pairs of conductors; a first voltage rail; a pull-up resistor connected to said first voltage rail, each said first conductor being electrically connected to said first voltage rail through said pull-up resistor; a second voltage rail; a pull-down resistor connected to said second voltage rail, each said second conductor being electrically connected to said second voltage rail through said pull-down resistor, each said first conductor being pulled up by said first voltage rail and each said second conductor being pulled down by said second voltage rail such that shorts and opens between said multiple pairs of conductors create a unique pattern of logic values that serves as one of an on-chip-identifier and a private key.