Patent ID: 6475901
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising:forming a plurality of interconnects of substantially same height over a silicon substrate; forming a first insulating layer over the plurality of interconnects, the first insulating layer covering top and side surfaces of the plurality of interconnects; forming a second insulating layer on the first insulating layer over the top surfaces and between the plurality of interconnects, the second insulating layer having substantially a same thickness as the plurality of interconnects; forming an adhesive layer over the second insulating layer; forming a support insulating layer over the second insulating layer, the adhesive layer and the support insulating layer being formed as substantially horizontal layers between the plurality of interconnects and as substantially non-horizontal layers over the top surfaces of the plurality of interconnects; polishing the second insulating layer, the adhesive layer and the support insulating layer that are formed over the top surfaces of the plurality of interconnects; and forming an intermediate insulating layer over the second insulating layer.