Patent ID: 9000962
Filing Date: 2015-04-07
Classification: H03M

Abstract:
1. A system for adaptive self-calibration to remove sample timing error in time-interleaved analog-to-digital conversion (ADC) of an analog signal comprising: a plurality of ADC channels recursively sampling the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples, the output samples being combinable for digital reconstruction of the analog signal; a timing skew detection unit coupled to said ADC channels, said timing skew detection unit generating for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment, said timing skew detection unit generating the timing skew factor for each sample segment based adaptively on the output samples for a selective combination of segments thereabout including at least one preceding sample segment and at least one succeeding sample segment with reference to said sample segment; and, a plurality of timing control units respectively coupled to said ADC channels, said timing control units adjusting time delays for the sampling clock within respective sample segments responsive to corresponding ones of the timing skew factors generated by said timing skew detection unit; whereby the series of sample segments is aligned substantially with the sampling clock.