Patent ID: 6277755
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method for fabricating an interconnect, the method comprising the steps of:forming a first dielectric layer on a substrate;forming a gradient silicon oxy-nitride layer on the first dielectric layer, wherein a more oxide-concentrated film is formed at a bottom of the silicon oxy-nitride layer and a more nitride-concentrated film is formed at a top of the silicon oxy-nitride layer, so as to reduce a dielectric constant of the silicon oxy-nitride layer;forming a second dielectric layer on the gradient silicon oxy-nitride layer;forming a trench line in the second dielectric layer with the gradient silicon oxy-nitride layer serving as an etch-stop;removing portions of the gradient silicon oxy-nitride layer and the first dielectric layer;forming a via under the trench line in the gradient silicon oxy-nitride layer and the first dielectric layer; andfilling the via and the trench line with a conductive material.