Patent ID: 6486885
Filing Date: 2002-11-26
Classification: G11C,H04N

Abstract:
A memory device for storing a sequential image data in succession and outputting the stored image data, comprising:a memory unit comprising N memory blocks, each memory blocks being capable of individual serving; a write address generator for generating a write address signal to write into the memory unit; a read address generator for generating a read address signal to read from the memory unit; and a controller for controlling the write address signal and the read address signal so that each start address for writing and reading for each image data is shifted as unit of the memory block and the writing and reading operation are not simultaneously performed to same memory block, each image data having a size being equivalent to one of M blocks (Mwherein said controller replaces a predetermined number of bits from a most significant bit of the read address signal with a predetermined number of revised bits for selecting a memory block to read out the image data and replaces a predetermined number of bits from a most significant bit of the write address signal with a predetermined number of revised bits for selecting a memory block to write the image data.