Patent ID: 7457979
Filing Date: 2008-11-25
Classification: H03L,H04L

Abstract:
1. A synchronous follow-up apparatus, comprising: a PLL portion that outputs a first clock signal; and a control loop portion that includes: a reference frequency signal generating portion that outputs a reference frequency signal; a clock signal generating portion that generates a second clock signal having the same frequency as a frequency of the first clock signal based on the reference frequency signal; and a frequency control signal generating portion that generates a frequency control signal to change the frequency of the second clock signal based on a frequency difference between the first clock signal and the second clock signal and outputs the frequency control signal to the clock signal generating portion, wherein the frequency control signal generating portion includes: a first counter which is operated synchronously with the frequency of the first clock signal; a second counter which is operated synchronously with the frequency of the second clock signal; and a calculator which calculates a phase difference between output signals output from the first and second counters that occurs after a predetermined time, and generates the frequency difference between the first clock signal and the second clock signal based on the calculated phase difference.