Patent ID: 8504796
Filing Date: 2013-08-06
Classification: G06F,G11C

Abstract:
1. A method of handling memory access requests in a digital memory system, said digital memory system comprising a plurality of memory banks wherein each of said plurality of memory banks may operate concurrently and independent of each other, said method comprising: receiving a first memory access request, said first memory access request identifying a first virtualized memory address in a virtualized memory address space; using said first virtualized memory address as an index into a first copy of a changeable memory mapping table implemented in said plurality of memory banks to obtain a first memory bank identifier that identifies a first memory bank of said plurality of memory banks currently storing data associated with said first virtualized memory address; handling said first memory access request by accessing said first memory bank using a first physical memory address, said first physical memory address comprising said first memory bank identifier and a subset of said first virtualized memory address; simultaneously receiving a second memory access request along with said first memory access request, said second memory access request comprising a write operation, said second memory access request identifying a second virtualized memory address in said virtualized memory address space; using said second virtualized memory address as an index into a second copy of said changeable memory mapping table implemented in said plurality of memory banks to obtain a current second memory bank identifier that identifies a second memory bank of said plurality of memory banks currently storing data associated with said second virtualized memory address; writing data from said second memory access request to a new second physical memory address in a third memory bank if a second memory bank is the same as said first memory bank currently being used to service said first memory access request; and updating said both said first copy and said second copy of said changeable memory mapping tables to associate said second virtualized memory address with said third memory bank.