Patent ID: 6133748
Filing Date: 2000-10-17
Classification: H03K

Abstract:
A circuit comprising:a first transistor;a second transistor coupled to the first transistor at an output node such that a current path through the first and second transistors and the output node is formed when the first and second transistors are conductive;a first input node configured to receive a data signal;a second input node configured to receive an enable signal; anda logic circuit coupled to the first and second transistors and the first and second input nodes, the logic circuit comprising a first delay circuit and a second delay circuit, the first and second delay circuits being coupled to the first input node, wherein the logic circuit is configured to provide a first control signal to the first transistor and a second control signal to the second transistor, the first control signal being a function of an output signal of the first delay circuit and the data and enable signals, the second control signal being a function of an output signal of the second delay circuit and the data and enable signals, the first control signal being independent of the output signal of the second delay circuit, the second control signal is independent of the output signal of the first delay circuit, wherein the first and second control signals cause the first transistor to be substantially non-conductive before the second transistor becomes conductive and the second transistor to be substantially non-conductive before the first transistor becomes conductive.