Patent ID: 6686243
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A fabrication method for flash memory applied to a semiconductor substrate having an active area isolated by an isolation structure, said method comprising:etching said isolation structure to a depth to form a recessed isolation structure; forming a conformal first dielectric layer on a surface of said active area and said recessed isolation structure; etching said first dielectric layer to form spacers on sides of said active area; performing a thermal oxidation process to form a tunnel oxide layer on the surface of said active area; forming a conformal doped silicon layer over said tunnel oxide layer and said recessed isolation structure; filling said recessed isolation structure with a sacrificial layer; forming an oxide layer on an exposed surface of said doped silicon layer; removing said sacrificial layer and said doped silicon layer with said oxide layer serving as a mask to expose a surface of said recessed isolation structure; removing said oxide layer; forming a second dielectric layer on the surface of said doped silicon layer and said recessed isolation structure; forming a conductive layer over said second dielectric layer; patterning said conductive layer to form word lines; and performing an ion implantation using said word lines as a mask to form source/drain regions in said active area.