Patent ID: 6214686
Filing Date: 2001-04-10
Classification: H01L

Abstract:
A method of fabricating capacitive storage nodes for one transistor, one capacitor cell dynamic random access memories (DRAMs) on a semiconductor substrate comprising;forming masking layers on a semiconductor substrate;etching openings through said masking layers to the surface of said semiconductor substrate to form trenches;masking one trench of adjacent said trenches with at least one semiconductor etch resistant material;removing a portion of the semiconductor substrate at the bottom of the other of said adjacent trenches to a depth below the bottom of said one trench;removing said semiconductor etch resistant material over said one trench; andetching said trenches isotropically to form bulbous enlargements within said trenches such that a bulbous enlargement etched in said one trench is at a different depth from a bulbous enlargement etched in said other trench.