Patent ID: 8912653
Filing Date: 2014-12-16
Classification: H01L

Abstract:
1. A method comprising: forming a plurality of integrated circuits on a semiconductor wafer, each integrated circuit having a plurality of contact pads on an upper surface; forming a passivation structure overlying the upper surface of the wafer, the passivation structure including a first dielectric layer on the upper surface of the wafer, a second dielectric layer on the first dielectric layer, the first dielectric layer having a first etch rate and the second dielectric layer having a second etch rate that is different from the first etch rate; etching a pattern into the passivation structure to expose the contact pads of the plurality of integrated circuits, portions of the passivation structure remaining on the upper surface of the wafer; forming a rough upper surface of the passivation structure by first removing portions of the second dielectric layer and then removing more portions of the second dielectric layer while also removing portions of the first dielectric layer with an ionized gas, remaining portions of the passivation structure including high points that include the second dielectric layer and low points that include the first dielectric layer; and cutting the semiconductor wafer into a plurality of semiconductor die.