Patent ID: 7369444
Filing Date: 2008-05-06
Classification: G11C

Abstract:
1. A memory controller, comprising: an interface; a circuit to output write data and a write address to a first storage array in a memory device and a read address to a second storage array in the memory device, a first storage circuit to a store a first plurality of commands for the first storage array; and a second storage circuit to store a second plurality of commands for the second storage array; wherein the memory controller outputs a first command from the first plurality of commands to the first storage array when a second command from the second plurality of commands is output to the second storage array, wherein the first command initiates storing the write data in the first storage array and the second command initiates accessing read data from the second storage array, wherein the write data and write address are output at the interface during a first period of time and the read address is output at the interface during a second period of time, wherein the second period of time is immediately after the first period of time.