Patent ID: 6187636
Filing Date: 2001-02-13
Classification: H01L

Abstract:
An method of making a memory device, comprising the steps of:forming a first insulation layer on a substrate;forming a first conductive layer on a portion of the first insulation layer;forming impurity regions in the substrate;forming a second insulation layer on sidewalls of the first conductive layer pattern;forming, on each of two sides of the first conductive layer pattern, a conductive sidewall spacer on the second insulation layer and the first insulation layer wherein the conductive sidewall spacers form a floating gate;forming a third insulation layer on the conductive sidewall spacers such that the first, second and third insulation layers together completely surround the conductive sidewall spacers; andforming a continuous third conductive layer pattern on the first, second and third insulation layers, the continuous third conductive layer pattern conductively coupled to the first conductive pattern.