Patent ID: 7086056
Filing Date: 2006-08-01
Classification: G06F

Abstract:
1. A processor unit for implementing a series of functions comprising a program for implementing said series of functions, said program comprising a plurality of at least three processes, wherein said program is executed by switching between said plurality of at least three processes based on priority levels assigned to individual ones of said plurality of at least three processes, and at least two processes of different respective priority levels manipulate a common memory area, wherein said program includes a memory manipulation process for implementing memory read/write operations as one of said plurality of at least three processes, wherein each of said plurality of at least three processes except said memory manipulation process requests memory manipulation by giving a memory read/write instruction as a need arises during execution of said program, and said memory manipulation process performs the requested memory manipulation in response to said instruction when activated, wherein a specific priority level is assigned to said memory manipulation process so that execution of memory manipulation requested by a first process is not interrupted by execution of memory manipulation requested by a second process irrespective of priority levels of said first and second processes, and wherein said instruction includes identification information for identifying a process that requests the memory manipulation.