Patent ID: 7691714
Filing Date: 2010-04-06
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit, comprising: forming a well region by doping a semiconductor substrate with a given conductivity type dopant; forming a gate structure over the well region; forming lightly doped source/drain extension implants by implanting the well region proximate the gate structure with an opposite conductivity type dopant; implanting a dislocation loop forming species into the lightly doped source/drain extension implants and performing an anneal to form dislocation loops to generate strain in a channel region below the gate structure; the dislocation loop forming species being implanted to a depth less than a depth of the lightly doped source/drain extension implants; and the dislocation loop forming species being implanted using a same mask used to form the lightly doped source/drain extension implants; forming sidewalls on the gate structure following implanting the dislocation loop forming species; and forming heavily doped source/drain implants by implanting the well region proximate the sidewalls with the opposite conductivity type dopant.