Patent ID: 6822892
Filing Date: 2004-11-23
Classification: G01R,G11C

Abstract:
A memory storage device comprising:a row line and a column line; a memory cell including a cell resistor connected between said row line and said column line; a control transistor having a first gate, a first terminal connected to said column line and a second terminal; a switch for grounding said row line; an amplifier having a first input connected to a first reference voltage source, a second input connected to said column line, and an output connected to said first gate; a capacitor having a terminal connected to said second terminal of said control transistor; a current supply transistor having a second gate, a first terminal connected to a power source, and a second terminal connected to said capacitor terminal; a comparator having a first input connected to a second reference voltage source, and a second input connected to said capacitor terminal, said comparator having a pulse output which is connected to said second gate for turning on said current supply transistor when a voltage at said capacitor terminal falls below said second reference voltage; and a circuit responsive to the output of said comparator for determining the resistance of said cell resistor.