Patent ID: 8486776
Filing Date: 2013-07-16
Classification: H01L

Abstract:
1. A method comprising: growing an SiGe layer on a silicon on insulator wafer; patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed; amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer in the NFET region; performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region; removing the SiGe layer from the NFET region; and performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.