Patent ID: 6417690
Filing Date: 2002-07-09
Classification: H03K

Abstract:
A physical layout of a programmable logic circuit wherein the first programmable logic circuit comprises:a first logic cluster comprising a plurality of programmable interconnected cells configured to perform logic functions on logic signals, the cells positioned along a first dimension; routing lines of a first set of routing lines programmably coupled to input/output ports of the cells of the logic cluster through a first set of programmable switches; the first set of programmable switches comprising a first memory and passgate array positioned adjacent to the cells along a second dimension; a logic block comprising a plurality of the logic clusters and a second set of routing lines, routing lines of the second set of routing lines configured to couple to the input/output ports of the programmable interconnected cells of the logic clusters through a second set of programmable switches; and the second set of programmable switches comprising a second memory and passgate array positioned next to the first memory and passgate array along the second dimension; a first set of tab networks configured to interface the second set of routing lines of the logic block with at least two sets of routing lines, said first set of tab networks positioned adjacent to the logic block along the first dimension and comprising; a third set of programmable switches selectively coupled to a first routing line of said second set of routing lines and at least one routing line of each of the sets of said at least two sets of routing lines, and a set of programmable drivers to drive the routing lines, each programmable driver coupled to at least two independent programmable signal paths, wherein the programmable signal paths each comprises a first programmable switch of the set of programmable switches selectively coupled to a second routing line of a first set of routing lines of the at least two sets of routing lines, and a second programmable switch of the set of programmable switches selectively coupled to a third routing line of a second set of routing lines of the at least two sets of routing lines.