Patent ID: 6444520
Filing Date: 2002-09-03
Classification: H01L,Y10T

Abstract:
A method of fabricating conductive plugs in an array of DRAM cells comprising the steps of:providing a silicon substrate with at least one gate interconnect including a protective cap overlying a gate layer, active areas of a first and a second conductivity type, and at least one word line; forming a protective layer atop said substrate; defining at least one set of first and second plug openings in said protective layer, wherein said first opening outwardly exposes the active area of the first conductivity type, and wherein said second opening outwardly exposes the protective cap of said gate interconnect; forming a first doped polysilicon layer of the first conductivity type on the surface of the protective layer of a depth at least sufficient to fill the first and the second plug openings; defining at least one third plug opening in said protective layer and said first doped polysilicon layer, wherein said third opening outwardly exposes the active area of the second conductivity type; redefining the second plug opening in said protective layer and said first doped polysilicon layer to outwardly expose the gate layer of said gate interconnect, and wherein the steps of defining the third plug opening and redefining the second plug opening are conducted simultaneously; forming a second doped polysilicon layer of the second conductivity type on the surface of the first doped polysilicon layer of a depth at least sufficient to fill the second and the third plug openings; isolating the first doped polysilicon layer in the first plug opening, and the second doped polysilicon layer in the second and third plug openings to form isolated conductive plugs in each plug opening, wherein said isolating step comprises chemical mechanical polishing to expose the protective layer; and forming at least one capacitor atop the protective layer and the conductive plugs.