Patent ID: 6058059
Filing Date: 2000-05-02
Classification: G11C

Abstract:
A sense/output circuit for a memory device, the memory device having a pair of complementary bit lines and being driven by a system voltage, the sense/output circuit comprising:a sense amplifier coupled to the complementary bit lines for amplifying the differential data signal representative of data on the complementary bit lines, the amplified signal being transferred to a pair of complementary data lines;an equalizing transistor connected across the data lines for equalizing the data lines into an equalized voltage state;a first PMOS transistor whose source is connected to the system voltage, whose drain is connected to a first complementary data line, and whose gate is connected to a first sense amplification enable signal, such that during a waiting state of each read cycle, the first PMOS transistor is switched on by the first sense amplification enable signal to pull the first complementary data line to a high-voltage logic state;a second PMOS transistor whose source is connected to the system voltage, whose drain is connected to a second complementary data line, and whose gate is connected to the first sense amplification enable signal, such that during waiting state of each read cycle, the second PMOS transistor is switched on by the first sense amplification enable signal to pull the second complementary data line to a high-voltage logic state;a first NAND gate having a first input end connected to the first complementary data line and a second input end connected to a second sense amplification enable signal;a second NAND gate having a first input end connected to the second complementary data line and a second input end connected to the second sense amplification enable signal;an inverter whose input end is connected to receive the second sense amplification enable signal;a first transmission gate whose input end is connected to the output end of the first NAND gate, and whose ON/OFF state is controlled by the second sense amplification enable signal;a second transmission gate whose input end is connected to the output end of the second NAND gate, and whose ON/OFF state is controlled by the second sense amplification enable signal; andan output buffer, coupled to the output end of the first transmission gate and the output end of the second transmission gate, for buffering the output signals from the first and second transmission gates;whereinduring each read cycle, the first and second sense amplification enable signals are both pulled up to a high-voltage logic state to switch on the sense amplifier and both the first and second transmission gates, and subsequently, when the respective data signals on the complementary data lines are complementary to each other, the second sense amplification enable signal and the first sense amplification enable signal are successively switched to a low-voltage logic state, thereby switching off the sense amplifier and the first and second transmission gates.