Patent ID: 6256262
Filing Date: 2001-07-03
Classification: G11C

Abstract:
A memory device comprising:a global decoder circuit having opposite first and second sides, and opposite third and fourth sides between said first and second sides;two memory cell array devices, each of which is disposed adjacent to a respective one of said first and second sides of said global decoder circuit, and has global word lines coupled to said global decoder circuit, and bit lines;two data input buffers, each of which is disposed at said third side of said global decoder circuit adjacent to a respective one of said memory cell arrays and is coupled to the respective one of said memory cell arrays, each of said data input buffers being adapted to receive input data and to transmit the input data to the respective one of said memory cell arrays;a write control circuit coupled to and disposed adjacent to said third side of said global decoder circuit, said write control circuit being adapted to receive write address sets corresponding to the input data and to generate appropriate write address and write control signals that are provided to said global decoder circuit upon receipt of the write address sets to enable writing of the input data into said memory cell array devices;write clock means, disposed adjacent to said third side of said global decoder circuit and coupled to said data input buffers, for generating write clock signals that are provided to said data input buffers so as to control transmission of the input data from said data input buffers to said memory cell array devices;a read control circuit coupled to and disposed adjacent to said fourth side of said global decoder circuit, said read control circuit being adapted to receive read address sets and to generate appropriate read address and read control signals that are provided to said global decoder circuit upon receipt of the read address sets to enable reading of said memory cell array devices;two multiplexer sets, each of which is coupled to said bit lines of a respective one of said memory cell array devices;two output circuits, each of which is coupled to a respective one of said multiplexer sets; andread clock means, disposed adjacent to said fourth side of said global decoder circuit and coupled to said output circuits, for generating read clock signals that are provided to said output circuits so as to control output of data by said output circuits.