Patent ID: 7671579
Filing Date: 2010-03-02
Classification: G01R,H03K

Abstract:
1. A signal delay measurement circuit, comprising: an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal; an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal, wherein a measured delay of the emulated signal path is calculated from the delayed version of the test clock signal when the delayed version of the test data signal is clocked through the output register.