Patent ID: 8354347
Filing Date: 2013-01-15
Classification: H01L

Abstract:
1. A method for forming interconnections in an integrated circuit (IC) comprising: providing a substrate with forming an etch stop stack over the substrate, covering the circuit component and the substrate, the etch stop stack comprises primary and secondary etch stop layers, the secondary etch stop layer includes a bottom surface which contacts the contact region on the surface of the substrate and the planar top surface of the trench isolation region and the primary etch stop layer is disposed above a top surface of the secondary etch stop layer, wherein the secondary etch stop layer, which is below the primary etch stop layer, comprises a high k material which is different from the isolation material of the trench isolation region; forming an interlayer dielectric (ILD) layer over the etch stop stack; and patterning the ILD layer to form a contact via therein to the contact region, wherein the patterning the ILD layer comprises