Patent ID: 6381692
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A system, comprising:a plurality of execution units, each independently capable of executing information contained in an instruction, and each operating to complete operation of an instruction and signal its readiness to complete another instruction in a time it takes to finish executing the instruction, without reference to a common system clock; an instruction obtaining part including a program counter coordinating obtaining instructions from an instruction memory: a first cache memory, including designations associated with said plurality of execution units, stored in an order which represents an order of execution by instructions in said plurality of execution units; a second cache memory, including information on instructions which are to be executed by said plurality of execution units; and a write back unit, responsive to said first and second cache memories, and operating to detect an exception, and to cancel writing from said execution units in response to said exception, and reconstructing unit order based on information in said first cache memory and determining which instruction causes the exception based on information in said second cache memory, otherwise discarding the information in said second cache memory.