Patent ID: 7173444
Filing Date: 2007-02-06
Classification: G01R,H01L

Abstract:
1. A structure comprising: a semiconductor wafer having a plurality of dies each having a circuit and a plurality of contact pads, the plurality of contact pads including a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal, the third contact pad being connected to a programmable self-test engine (PSTE) embedded in the corresponding die such that the test control signal activates the PSTE to perform a self-test; and a plurality of interconnection lines routed though a plurality of scribe areas disposed between the plurality of dies, wherein the plurality of interconnection lines include a first interconnection line routed perpendicular to a second interconnection line to form a testing grid pattern which allows the plurality of dies to be tested individually or in multiples with the power supply voltage, the ground voltage, and the test control signal, wherein the first interconnection line and the second interconnection line are separate interconnect lines disposed on separate layers of the semiconductor wafer; a probe card having a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of dies, wherein during wafer test the plurality of sets of probe pins come in contact with the corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.