Patent ID: 8972819
Filing Date: 2015-03-03
Classification: G06F,G11C,H03K

Abstract:
1. An integrated circuit comprising: a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits; a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry; and a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein, said first scrub circuit comprising spatially redundant circuitry; wherein the first EDAC circuit and the first scrub circuit each includes at least one of buried guard ring (BGR) structures and parasitic isolation device (PID) structures; and wherein the spatially redundant circuitry of the first EDAC circuit and the first scrub circuit comprises dual interlocked storage cell (DICE) circuits.