Patent ID: 6373765
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A sense amplifier circuit for differentially amplifying potentials between a first bitline and a second bitline, said sense amplifier circuit comprising:(a) a first sense transistor, its source-drain circuit coupled between said first bitline and a restore signal node, and a gate coupled to said second bitline; (b) a second sense transistor source-drain circuit coupled between said second bitline and said restore signal node and a gate coupled to said second bitline; (c) a first threshold transistor and a second threshold transistor having a first and a second threshold voltage, respectively, said first and said second threshold transistors having their respective gates coupled to said gate of said first sense transistor; (d) a third threshold transistor and a fourth threshold transistor having a third and a fourth threshold voltage, respectively, said third and said fourth threshold transistors having their respective gates coupled to said gate of said second sense transistor; (e) a first selection transistor and a second selection transistor connected in series with said first threshold transistor and said second threshold transistor, respectively, having their gates connected to respective first and a second selection signal; and, (f) third selection transistor and a fourth selection transistor connected in series to said third threshold transistor and said fourth threshold transistor, respectively, having their gates connected to a third and a four selection signal, respectively, said selection transistors being responsive to said selection signals for selectively enabling said threshold transistors, whereby the switching threshold of said sense amplifier is varied.