Patent ID: 7544562
Filing Date: 2009-06-09
Classification: H01G,H01L

Abstract:
1. A method for manufacturing an integrated circuit with a capacitor electrode structure, comprising: providing a substrate comprising contact pads arranged in lines and rows on a surface of the substrate, the lines being non-parallel to the rows; applying a first mold on the substrate; forming at least one first trench into the first mold above the contact pads, the first trench spanning over at least two contact pads arranged in one row; forming first supporting walls from a first dielectric layer on side walls of the at least one first trench; applying a second mold on the substrate; forming at least one second trench into the second mold, the second trench spanning over at least two contact pads arranged in one line; forming second supporting walls from a second dielectric layer on side walls of the at least one second trench; applying a conductive layer on the first and second supporting walls for forming a first electrode of the capacitor structure.