Patent ID: 7253098
Filing Date: 2007-08-07
Classification: H01L

Abstract:
1. Method of forming an interconnect structure comprising the steps of: depositing a dielectric layer of ultra low-k material; forming a hard mask over the dielectric layer, wherein the hard mask comprises: a layer of silicon carbide (SiC) material including (SiCOH) material overlying the dielectric layer; and a layer of oxide material overlying the silicon carbide material; etching trenches in the dielectric layer; depositing a liner over the hard mask and within the trenches; and overfilling the trenches with a conductive material; perfoming a chemical mechanical polishing process to remove the conductive material which is atop the liner, thereby exposing the liner; removing the portion of the liner which is atop the hard mask using a Gas Cluster Ion Beam (GCIB), leaving the conductive material protruding from the trenches; and removing the layer of oxide material using a wet etch process, leaving the layer of silicon carbide material, the conductive material and the liner material above the layer of silicon carbide material protruding from the trenches; and performing a touch-up polishing process to remove the conductive material and the liner protruding from the trenches.