Patent ID: 6713340
Filing Date: 2004-03-30
Classification: G11C,H01L

Abstract:
A method for fabricating a memory device, comprising:defining a first active region and a second active region on a semiconductor substrate; forming a first gate electrode on the first active region of the substrate, and forming a second gate electrode on the second active region of the substrate; forming a first insulating layer having first and second contact holes to respectively expose the substrate on a first side of the first and second gate electrodes; forming ferroelectric capacitors, wherein first electrodes of the ferroelectric capacitors are in the contact holes; and forming a first split wordline that is coupled to a second electrode of a second ferroelectric capacitor in the first contact hole and coupled to the first gate electrode, and forming a second split wordline that is coupled to a second electrode of a first ferroelectric capacitor in the second contact hole and coupled to the second gate electrode.