Patent ID: 8151118
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A device for use in enforcing security in a system the device comprising: a timeout timer configured to be reset in response to receipt of a signal from a master device that is separate from the device; a processor, that at least in part, determines when an event has occurred, the event comprising an expiration of time at the timeout timer that occurs unless the device receives the signal from the master device that causes the timeout timer to reset; a cryptographic function coupled to the processor for authenticating communications with the master device; a switch coupled to the processor and responsive to a signal from the processor related to the event that blocks a “power OK” signal external to a corollary device, wherein blocking the “power OK” signal prevents the corollary device from beginning its power up sequence, and wherein the corollary device is coupled to and physically separate from the device; and a port coupled to the processor for communication with the master device, wherein the port is coupled to a communication channel dedicated to communication between the master device and one or more other devices, each of the other devices being substantially identical to the device and including a respective switch configured to block a “power OK” signal to a different, respective corollary device that is coupled to and physically separate from the other device.