Patent ID: 6751279
Filing Date: 2004-06-15
Classification: H03L

Abstract:
An arrangement for a clock supply of high bit-rate switching network structures in a digital narrowband switching system, comprising:a PLL system comprising a crystal-controlled oscillator that locks a switching network clock to a clock phase generated by a central clock generator and outputs a low-voltage normal bit-rate, low frequency, clock signal and a low-voltage frame clock signal for normal bit-rate switching network structures; an analog, discrete sine oscillator in a phase-locked loop that converts said normal bit-rate clock signal into a high-frequency clock signal; and a low-voltage pseudo-ECL arrangement, that, after stabilization with a reference clock, generates a high bit-rate, high frequency, clock signal suitable for high bit-rate switching network structures by division and outputs it, said low-voltage pseudo-ECL arrangement also outputting an output-side high bit-rate, high frequency, frame clock signal of the same frequency decoupled in phase position from an input-side frame clock signal that has a predetermined phase relation relative to said high bit-rate clock signal.