Patent ID: 8937499
Filing Date: 2015-01-20
Classification: H03L

Abstract:
1. A delay locked loop, comprising: a delay line configured to receive a clock input signal based on a reference clock and to output a first edge of a delay edge signal according to a control signal; an injector configured to receive a first edge of the reference clock and, in response to a first trigger, send a first edge of the clock input signal to the delay line and generate a first edge of a reference edge signal delayed by a predetermined unit of the reference clock period; a synchronizer configured to detect the first edge of the delay edge signal having been output by the delay line, and in response, send the injector a second trigger to send a second edge of the clock input signal to the delay line; and an edge detector configured to perform a first comparison of a timing of the first edge of the delay edge signal to a timing of the first edge of the reference edge signal, and to send the control signal to the delay line to decrease or increase a delay setting of the delay line based on the first comparison.