Patent ID: 8541874
Filing Date: 2013-09-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first memory chip having a main surface, a first electrode and a second electrode on the main surface; a second memory chip having a third electrode, a fourth electrode, a first electrode penetrating the second memory chip and a second through electrode penetrating the second memory chip; a logic chip having a first side, a second side opposite the first side, a fifth electrode, a sixth electrode, a seventh electrode and an eighth electrode; the first memory chip stacked over the second memory chip; the logic chip formed under the second memory chip; the first electrode electrically connecting to the first through electrode; the second electrode electrically connecting to the second through electrode; the first through electrode electrically connecting to the third electrode; the second through electrode electrically connecting to the fourth electrode; the third electrode electrically connecting to the fifth electrode; the fourth electrode electrically connecting to the sixth electrode; the fifth electrode and the sixth electrode arrayed in a central area of the logic chip in a cross sectional view; the seventh electrode arrayed along the first side of the logic chip in the cross section view; and the eighth electrode arrayed along the second side of the logic chip in the cross section view, wherein a pitch between the first electrode and the second electrode is equal to a pitch between the fifth electrode and the sixth electrode, and a pitch between the seventh electrode and the eighth electrode is wider than the pitch between the fifth electrode and the sixth electrode.