Patent ID: 6534388
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method of fabricating a P channel, metal oxide semiconductor, (PMOS), device, on a semiconductor substrate, featuring the use of a monolayer of silicon nitride, used to retard out diffusion of P type dopants from a P type polysilicon gate structure, and from a P type lightly doped source/drain, (LDD), region, comprising the steps of:forming said P type polysilicon gate structure on an underlying first gate insulator layer; forming said P type LDD region, in a region of said semiconductor substrate not covered by said P type polysilicon gate structure; performing an oxidation procedure to create a polysilicon oxide layer on the surface of said P type polysilicon gate structure, and forming a second gate insulator layer, on the surface of said P type LDD region, with said second gate insulator layer greater in thickness than said first gate insulator layer; performing a plasma nitridation procedure to create said monolayer of silicon nitride, at a thickness between about 3 to 5 Angstroms, on the surface of said P type polysilicon gate structure, underlying said polysilicon oxide layer, and creating said monolayer of silicon nitride on the surface of said P type LDD region, underlying said second gate insulator layer; forming insulator spacers on the sides of said polysilicon oxide layer, located on the sides of said P type polysilicon gate structures; and forming a heavily doped, P type source/drain region, in an area of said semiconductor substrate not covered by said P type polysilicon gate structure or by said insulator spacers.