Patent ID: 7966591
Filing Date: 2011-06-21
Classification: G06F

Abstract:
1. A method comprising: receiving an Register Transfer Level (RTL) description of an electronic device provided for a design test; receiving a test bench environment to drive stimulus into the electronic device; identifying at least one register to be verified during the design test; receiving a property list including a plurality of properties, wherein each property includes a cause and an effect; creating a new property instance of a property in the property list upon receiving an enqueue cause, the new property instance added to a set of property instances; transitioning a property instance in the set of property instances from a waiting state to a pending state based on a dequeue cause; advancing a property instance in the set of property instances from the pending state to an active state and then to an expired state based on a defined time window; creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects; inserting a property instance from the set of property instances into each of the plurality of solutions when the property instance enters to active state; pruning solutions from the current solution space which have not used a property instance entering the expired state; and computing, by one or more computer processors a new solution space based on the current solution space and a target transition.