Patent ID: 6418353
Filing Date: 2002-07-09
Classification: G03F

Abstract:
A computer-controlled system for optimizing device sizing in the manufacture of integrated circuits, the system comprising:a photolithography module comprising a light source for etching wafer masks, the photolithography module having at least one operating parameter; a wafer process for producing integrated circuits using the wafer masks produced by the photolithography module, the wafer process producing first and second updated process parameters; a derator processor coupled to the photolithography module for combining the first updated process parameter from the wafer process with the operating parameter from the photolithography module to determine the minimum manufacturable device size that can be effectively manufactured by the wafer process; a form factor processor coupled to the derator processor to generate circuit designs based on said minimum manufacturable device size; and a processor coupled to the derator processor for receiving the second updated process parameter from the wafer process and transferring said second process parameter to the derator processor, thereby enabling a redetermination of the minimum manufacturable device size that can be effectively manufactured by the wafer process.