Patent ID: 9147468
Filing Date: 2015-09-29
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: a plurality of stacks of conductive strips, the plurality of stacks including even stacks and odd stacks; a plurality of active pillars arranged between corresponding even and odd stacks of conductive strips in the plurality of stacks, defining a multi-layer array of interface regions at cross-points between opposing side surfaces of the active pillars and conductive strips in the corresponding even and odd stacks of conductive strips; a 3D array of even memory cells in the interface regions accessible via the active pillars and conductive strips in the even stacks of conductive strips and odd memory cells in the interface regions accessible via the active pillars and conductive strips in the odd stacks of conductive strips; and control circuitry configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in at least one of the even memory cell and odd memory cell in a given frustum of a selected active strip.