Patent ID: 7571283
Filing Date: 2009-08-04
Classification: G06F

Abstract:
1. A system for maintaining a best-case demand redispatch of an instruction, comprising: a bus system; a communications unit connected to the bus, wherein data is sent and received using the communications unit; a dispatch unit connected to the bus system for dispatching instructions; and a load/store unit connected to the dispatch unit, wherein the load/store unit receives the dispatched instructions for execution; and wherein responsive to a demand miss, the load/store unit sends a fetch request to a next level cache in a memory hierarchy, examines a cache line of the demand miss to identify a critical sector of the cache line, generates a best-case data return arrival time by determining a fastest time the next level cache is able to return the critical sector of the cache line; and sends a speculative warning to a dispatch unit to coincide with the best-case data return arrival time, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as data in the next level cache becomes available to a processor core.