Patent ID: 6362491
Filing Date: 2002-03-26
Classification: G03F

Abstract:
A method of measuring overlay accuracy, comprising:providing an integrated circuit wafer having a layer of photoresist formed thereon; providing a first mask having a first circuit pattern and a first overlay pattern adjacent to said first circuit pattern; providing a second mask having a second circuit pattern and a second overlay pattern adjacent to said second circuit pattern; providing an exposure and alignment system; aligning said first mask and exposing said layer of photoresist with images of said first circuit pattern and said first overlay pattern using said exposure and alignment system and a first exposure step; aligning said second mask to said integrated circuit wafer and exposing said layer of photoresist with images of said second circuit pattern and said second overlay pattern using said exposure and alignment system and a second exposure step; developing said layer of photoresist thereby forming images of said first circuit pattern, said first overlay pattern, said second circuit pattern, and said second overlay pattern in said layer of photoresist; and determining the alignment accuracy of said second circuit pattern relative to said first circuit pattern by visually comparing the position of the image of said first overlay pattern to the image of said second overlay pattern.