Patent ID: 9196363
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; a first well having a first conductivity type and formed in a main surface of the semiconductor substrate; a second well having a second conductivity type opposite to the first conductivity type and located so as to be included in the first well; a third well having the second conductivity type and located so as to be included in the first well and extend along the second well, while being electrically isolated from the second well; and a nonvolatile memory cell located so as to two-dimensionally overlap the second and third wells, wherein the nonvolatile memory cell includes: a floating gate electrode located so as to extend in a first direction and two-dimensionally overlap the second and third wells; an element for writing/erasing data located at a first position where the floating gate electrode two-dimensionally overlaps the second well; and a field effect transistor for reading data located at a second position where the floating gate electrode two-dimensionally overlaps the third well, wherein the element for writing/erasing data includes: a first electrode formed of a portion of the floating gate electrode which is formed at the first position; a first insulating film formed between the first electrode and the semiconductor substrate; a first semiconductor region and a second semiconductor region which are formed at respective positions in the second well between which the first electrode is interposed; and the second well, wherein the field effect transistor for reading data includes: a second electrode formed of a portion of the floating gate electrode which is formed at the second position; a second insulating film formed between the second electrode and the semiconductor substrate; and a third semiconductor region and a fourth semiconductor region which are formed at respective positions in the third well between which the second electrode is interposed, wherein the first semiconductor region has the first conductivity type, the second semiconductor region has the second conductivity type, and each of the third and fourth semiconductor regions has the first conductivity type, and wherein a length of the first electrode in a second direction crossing the first direction is smaller than a length of the second electrode in the second direction.