Patent ID: 7825708
Filing Date: 2010-11-02
Classification: H03L

Abstract:
1. An integrated circuit comprising: a first phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit providing an oscillator output signal, and a feedback divider circuit; a second phase-locked loop (PLL) circuit configured to be selectively coupled to supply a control value to the feedback divider circuit to thereby control the oscillator output signal; a nonvolatile storage; a selector circuit coupled to the nonvolatile storage and the second PLL circuit; wherein while the second phase-locked loop circuit is not selected by the selector circuit to control the first PLL circuit, the first PLL circuit is coupled to receive a first control value as the control value to control a divide ratio of the feedback divider circuit, the first control value being determined at least in part according to a stored control value stored in the nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal; and wherein, while the second PLL is selected by the selector circuit to supply a second control value as the control value to the feedback divider circuit, the second control value is determined according to a detected difference between a feedback signal corresponding to the oscillator output signal and a reference signal coupled to an input of the second PLL circuit.