Patent ID: 7459394
Filing Date: 2008-12-02
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising: forming a trench in an interlayer dielectric through a dual damascene process; depositing a barrier metal layer directly on an overall surface of the interlayer dielectric and the trench, the barrier metal layer preventing diffusion of copper; depositing a copper layer in the trench; planarizing the copper layer to form a copper line, wherein the barrier metal layer on the interlayer dielectric is removed; performing a wet etching process to remove a top portion of the copper line, wherein the barrier metal layer within an upper portion of the trench is removed; depositing a dielectric barrier layer on the etched copper line; and performing a planarization process to flatten the dielectric barrier layer such that the top surface of the dielectric barrier layer is formed on a same horizontal plane with the top surface of the interlayer dielectric, wherein the lower surface of the dielectric barrier layer is formed directly on the copper line and the barrier metal layer, and wherein the side surface of the dielectric barrier layer directly contacts the interlayer dielectric.