Patent ID: 7937607
Filing Date: 2011-05-03
Classification: G06F

Abstract:
1. An asynchronous data holding circuit comprising: a source synchronizer configured to receive an enable signal, which is synchronized with a system clock signal, in response to one of a rising edge and a falling edge of the enable signal, to acquire the other one of the rising edge and the falling edge of the enable signal in synchronization with a communication clock signal, and to output the received enable signal in synchronization with the communication clock signal, a first data holding unit configured to acquire and hold a data signal received, in response to the enable signal output from the source synchronizer and the communication clock signal, a destination synchronizer configured to output the enable signal in synchronization with the system clock signal, and a second data holding unit configured to acquire and hold the data signal held in the first data holding unit in response to the enable signal output from the destination synchronizer, and the system clock signal.