Patent ID: 8006145
Filing Date: 2011-08-23
Classification: G01R,G11C

Abstract:
1. A semiconductor integrated device comprising: a plurality of memory cell arrays arranged with a plurality of electrically reprogrammable memory cells; a control circuit which controls operations of an internal high voltage generation circuit, a latch circuit of a plurality of latch circuits that are arranged corresponding to a number of bits of test parameter data provided from an external tester, and an address register; a data program/read circuit which transfers programming data to said plurality of memory cell arrays and which reads out data from said plurality of memory cell arrays; a data input/output circuit which transfers externally input data to said data program/read circuit and which externally outputs data transferred from said data program/read circuit; and a signal generation instruction circuit which receives an externally provided command and instructs said control circuit so that a predetermined internal control signal is generated, said address register including an internal selection circuit which is connected with said control circuit, said address register transferring externally input address data to said data program/read circuit, one end of said latch circuit being connected to said control circuit, said data input/output circuit, and said address register, and the other end of said latch circuit being connected to said data program/read circuit, an input of said latch circuit being connected to an output of said selection circuit, and an output of said latch circuit being connected to an input of said selection circuit so that the output of said latch circuit is fed back to said selection circuit, said latch circuit latching said test parameter data which is provided from said external tester via said selection circuit, said latch circuit transferring said test parameter data to said data program/read circuit, said latch circuit latching said test parameter data, which is programmed to said plurality of memory cell arrays and read out from said plurality of memory cell arrays by said data program/read circuit, and outputting said test parameter data to said selection circuit and externally, said control circuit receiving an instruction from said signal generation instruction circuit, generating said internal control signal which activates said selection circuit at a timing at which a fixed value data of said test parameter data is changed, and transferring said internal control signal to said selection circuit, and said selection circuit receiving said internal control signal and controlling so that said fixed value data of said test parameter data is changed.