Patent ID: 6604192
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A computer system for processing instructions of a computer program, comprising:a pipeline configured to simultaneously process a first instruction in a first stage of said pipeline and a second instruction in a second stage of said pipeline, said first stage configured to transmit a first set of attribute data associated with said first instruction and to transmit a first encoded register identifier associated with said first instruction, said second stage configured to transmit a second set of attribute data associated with said second instruction and to transmit a second encoded register identifier associated with said second instruction; a first decoder coupled to said first stage and configured to receive said first encoded register identifier, said first decoder configured to decode said first encoded register identifier into a first decoded register identifier and to transit said first decoded register identifier; a second decoder coupled to said second stage and configured to receive said second encoded register identifier, said second decoder configured to decode said second encoded register identifier into a second decoded register identifier and to transmit said second decoded register identifier; comparison logic interfaced with said first and second decoders, said comparison logic configured to receive said first and second decoded register identifiers and to receive said first and second sets of attribute data, said comparison logic configured to detect a data hazard based on said first and second decoded register identifiers and based on said first and second sets of attribute data; a first attribute interface coupled to said first decoder and said comparison logic, said first attribute interface configured to receive said first decoded register identifier and said first set of attribute data and to combine said first set of attribute data with said first decoded register identifier; and a second attribute interface coupled to said second decoder and said comparison logic, said second attribute interface configured to receive said second decoded register identifier and said second set of attribute data and to combine said second set of attribute data with said second decoded register identifier.