Patent ID: 9105506
Filing Date: 2015-08-11
Classification: H01L

Abstract:
1. A dynamic memory structure, comprising: a substrate; a first strip semiconductor material disposed on said substrate and extending along a first direction; a gate standing astride said first strip semiconductor material, extending along a second direction and dividing said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region, wherein a source width of said first source terminal along said second direction is greater than a first channel width of said first strip semiconductor material along said second direction; a first dielectric layer partially sandwiched between said gate and said first strip semiconductor material, wherein a first thickness of the first dielectric layer on top surface of the first strip semiconductor material is different from a second thickness of the first dielectric layer on the sidewalls of the first strip semiconductor material; a first capacitor unit disposed on said substrate and comprising said first source terminal serving as a bottom electrode, a second dielectric layer partially covering said first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer partially covering said second dielectric layer to serve as a top electrode, wherein said capacitor dielectric layer and said top electrode cover said first source terminal having said source width greater than said first channel width of said first strip semiconductor material; and wherein said first source terminal and said first drain terminal have asymmetric shapes.