Patent ID: 6275432
Filing Date: 2001-08-14
Classification: G11C

Abstract:
A method of reading and writing in an integrated circuit memory having a plurality of bit line pairs with a plurality of corresponding sense amplifiers associated therewith and coupled thereto, each sense amplifier including a latch having internal latch nodes communicable with one or more corresponding bit lines, the method comprising the steps of:powering a selected sense amplifier latch by selectively operating first and second local sense amplifier drive transistors connected to said selected latch;for reading data from a memory cell along a bit line communicating with said selected sense amplifier latch:(a) developing a latch node signal at said internal latch node, said latch node signal corresponding to the data from the memory cell, and(b) operating a local read amplifier associated with said selected sense amplifier, said operating the local read amplifier step including(i) applying at least one data read signal to said local read amplifier and(ii) using said latch node signal to control said at least one data read signal without the data read signal substantially affecting said latch node signal; andfor writing data into a selected sense amplifier or to a memory cell along a bit line corresponding to said selected sense amplifier, operating a local data write circuit associated with said sense amplifier, said operating the local write circuit step including:(i) applying at least one data write signal to said local data write driver circuit,(ii) developing a write signal in said local data write driver circuit, and(iii) communicating said write signal to both an internal node of the sense amplifier latch corresponding to the memory cell and to the corresponding bit line.