Patent ID: 6297162
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method to form dual damascene interconnects in the manufacture of an integrated circuit device comprising:providing a semiconductor substrate;providing first conductive traces in a first dielectric layer overlying said semiconductor substrate;depositing a diffusion barrier layer overlying said first dielectric layer and said first conductive traces;depositing a first etch stop layer overlying said diffusion barrier layer wherein said first etch step layer comprises silicon oxynitride;nitridizing said first etch stop layer to decrease the etch rate of said first etch stop layer;depositing a second dielectric layer overlying said diffusion barrier layer;depositing a second etch stop layer overlying said second dielectric layer wherein said second etch stop layer comprises silicon oxynitride; nitridizing said second etch stop layer to decrease the etch rate of said second etch stop layer;depositing a third dielectric layer overlying said second etch stop layer;patterning said third dielectric layer to form trenches for planned second conductive traces wherein said second etch stop layer stops the etch process for said patterning;patterning said second etch stop layer and said second dielectric layer to form vias;etching through said first etch stop layer and said diffusion barrier layer to expose said first conductive traces;depositing a metal layer overlying said third dielectric layer and filling said vias and said trenches;polishing down said metal layer to complete said dual damascene interconnects; andcompleting said integrated circuit device.