Patent ID: 6370652
Filing Date: 2002-04-09
Classification: G06F

Abstract:
An electronic circuit comprising:discrete first and second integrated circuits each having a respective command protocol diverse from that of the other; the first integrated circuit (102) having a clock input, a strobe input, a data input, a shift register, and an output register; the second integrated circuit (104) having a clock input, a chip enable input, a data input, a register, and an address decoder; a clock signal source for supplying a clock signal comprising clock pulses to the clock inputs of the integrated circuits via a clock line; a data signal source for supplying a serial data signal to the data inputs of the integrated circuits via a data line; a chip enable signal source for supplying to the chip enable input of the second integrated circuit a chip enable signal comprising chip enable pulses that have leading edges defining change from a first logic state to a second logic state and trailing edges defining change from the second logic state to the first logic state; the second integrated circuit's command protocol allowing serial data at its data input to be clocked in by clock pulses at its clock input when the chip enable signal is in the second logic state after the address decoder has detected that the second integrated circuit has been correctly addressed by data preceding the data that is to be entered in the second integrated circuit's register, and disallowing serial data at its data input from being clocked in by clock pulses at its clock input either when the chip enable signal is in the first logic state or when the address decoder has failed to detect correct addressing of the second integrated circuit; an interface circuit (106) interfacing the chip enable signal to the strobe input of the first integrated circuit and supplying to the strobe input a strobe signal comprising pulses that have leading edges defining change from the first logic state to the second logic state and trailing edges defining change from the second logic state to the first logic state; the first integrated circuit's command protocol allowing serial data at its data input to be clocked into its shift register by clock pulses at its clock input and transfer of the data from its shift register to its output register when the strobe signal is in the second logic state, and disallowing transfer of the data from its shift register to its output register when the strobe signal is in the first logic state; and in response to change in the chip enable signal from the first logic state to the second logic state, the interface circuit causes the strobe signal to remain in the first logic state, and in response to change in the chip enable signal from the second logic state to the first logic state, the interface circuit causes the strobe signal to change from the first logic state to the second logic state, and then after a delay time, change back to the first logic state.