Patent ID: 9136376
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a plurality of active pillars, each of the active pillars including a first impurity region disposed over a surface of a substrate, a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is arranged at a constant interval over the first impurity region; a gate electrode extending across each of the plurality of active pillars along a row of second impurity regions and disposed over sidewalls of the second impurity regions in the row, wherein the sidewalls of the second impurity regions in the row are each disposed between second impurity regions that are adjacent in a corresponding active pillar of the active pillars; and a bit line disposed between adjacent first impurity regions, disposed under the gate electrode, crossing the gate electrode, and being in contact with one of the adjacent first impurity regions, wherein the first, second, and third impurity regions comprise impurities of the same polarity.