Patent ID: 6544856
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A method for forming a trench capacitor having an increased trench capacitance forming a memory element of a semiconductor component, which comprises the steps of:providing a silicon substrate; applying an oxide layer on the silicon substrate; applying a nitride layer on the oxide layer; forming a hard mask having an opening formed therein from the nitride layer and the oxide layer using a photolithographic process, the opening determining a position of a trench to be formed; etching the silicon substrate, through the opening, down to a first depth to form the trench; depositing conformally an arsenic glass in the trench; filling the trench with photoresist; etching the photoresist down to a second depth being less than the first depth; etching the arsenic glass selectively with respect to the photoresist; incinerating residual photoresist in the trench; driving out arsenic from the arsenic glass into the silicon substrate, thereby producing an n+-doped substrate region; etching remaining parts of the arsenic glass; subsequently performing a wet-chemical etching widening the n+-doped substrate region selectively both with respect to a lightly doped substrate region and with respect to the oxide layer and the nitride layer; depositing a node dielectric in the trench; and depositing a n+-type polysilicon in the trench on the node dielectric.