Patent ID: 6078987
Filing Date: 2000-06-20
Classification: G11C

Abstract:
A memory circuit comprising:a cam array having n rows and x columns of cam cells, at least one cam cell being coupled to a match line, a cam word line, and to a cam bit line;a first ram array having n rows and y columns of first ram cells, at least one first ram cell being coupled to a ram word line, and a first ram bit line;a second ram array having n rows and z columns of second ram cells, at least one second ram cell being coupled to the ram word line, and a second ram bit line;n ram word line drivers, at least one ram word driver having an output coupled to the ram word line;n match sense amplifiers, at least one match sense amplifier having an input coupled to the match line and an output coupled to the at least one ram word line driver;y first ram write driver circuits, at least one first ram write driver circuit having a first output coupled to the first ram bit line, a first input configured to receive a first data input signal, and a control input configured to receive a first ram write enable signal;wherein the at least one first ram write driver circuit is configured to charge the first ram bit line in response to receiving the first ram write enable signal;z second ram write driver circuits, at least one second ram write driver circuit having a second output coupled to the second ram bit line, a second input configured to receive a second data input signal, and a control input configured to receive a second ram write enable signal;wherein the at least one second ram write driver circuit is configured to charge the second rain bit line in response to receiving the second write enable signal;wherein the first ram write enable signal is separate and distinct from the second ram write enable signal.