Patent ID: 7944258
Filing Date: 2011-05-17
Classification: H03L

Abstract:
1. A semiconductor integrated circuit including a delay line of a delay locked loop, comprising: the delay line of the delay locked loop including: a delay variation detecting unit configured to receive a reference clock signal, to delay the reference clock signal for generating a plurality of delayed clock signals, to compare the reference clock signal with the plurality of the delayed clock signals, respectively, and to selectively enable a plurality of detection signals according to a variation in a delay time of the delayed clock signals, wherein the variation in the delay time is caused by changes of an operating voltage and an operating temperature, and the plurality of delayed clock signals have different delay times, respectively; and a plurality of delay units configured to receive the detection signals and an input signal, to determine a delay amount according to a number of enabled detection signals among the detection signals and to delay the input signal by the determined delay amount so as to compensate the variation in the delay time of the delay line according to the detection signals, wherein each of the delay units includes a first logic element having an output, a delay compensating unit configured to receive the detection signals and the output of the first logic element and delay the output of the first logic element by a delay time set according to the number of enabled detection signals of the detection signals, and a second logic element configured to receive the output of the delay compensating unit, and wherein the first logic element is a NAND gate or a NOR gate that has a first input terminal configured to receive the output of a previous delay unit or the reference clock signal, and a second input terminal, and is configured to operate as an inverter according to a level of the second input terminal.