Patent ID: 6510503
Filing Date: 2003-01-21
Classification: G06F,G11C,Y02D

Abstract:
A memory subsystem comprising:a) at least two semiconductor devices; b) a main bus containing a plurality of bus lines for carrying substantially all data, and command information needed by said devices, said semiconductor devices including at least one memory device connected in parallel to said bus; c) a loopback clock structure including a pair of said bus lines constituting first and second lines of said loopback clock, each said memory device including first and second clock inputs for connection to respective ones of said clock lines; and d) a controller coupled to one end of said bus lines for issuing write data command signals to said memory devices, receiving read data from said memory devices and for generating a loopback clock signal on said first clock line and receiving a return loopback clock signal on said second clock line, said controller including respective output driver circuits for driving said data command signals and said loopback clock signal, said driver circuits being identical, to thereby minimize skew between said clock and data signals.