Patent ID: 8850109
Filing Date: 2014-09-30
Classification: G06F,Y02D

Abstract:
1. An apparatus comprising: a first circuit configured to parse a first data word into a first data portion in a first signal and a second data portion in a second signal and parse a first address into a first address portion and a second address portion, wherein said first address portion contains higher order bits than said second address portion; and a second circuit comprising a plurality of memory blocks, said second circuit being configured to store said second data portion in said second signal in a particular one of said memory blocks using said first data portion in said first signal to determine said particular memory block and said first address portion to determine a particular one of a plurality of locations within said particular memory block, and generate a second address by concatenating said first address portion and said first data portion, wherein said first data portion is not stored in said apparatus and said particular location is determined independently of said second address portion.