Patent ID: 6225211
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A method for making stacked and borderless via structures for multilevels of electrically conducting interconnections for integrated circuits comprising the steps of:a) providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned first conducting layer formed thereon and having a planar first insulating layer coplanar with surface of said patterned first conducting layer;b) depositing a blanket first etch-stop layer on said first insulating layer;c) depositing a second insulating layer on said first etch-stop layer;d) depositing a blanket second etch-stop layer on said second insulating layer;e) patterning said second etch-stop layer and having openings over said patterned first conducting layer where via holes are desired;f) depositing a blanket third insulating layer over said second etch-stop layer and over said openings;g) using a photoresist mask and anisotropic plasma etching to etch trenches for conducting lines in said third insulating layer to said second etch-stop layer, while said trenches extending over said openings in said second etch-stop layer are concurrently etched in said second insulating layer to said first etch-stop layer over said patterned first conducting layer to form via holes;h) removing selectively said second etch-stop layer in said trenches and said first etch-stop layer in said via holes;i) depositing a blanket conformal barrier layer on surface of said trenches and said via holes;j) depositing a conformal second conducting layer and filling said vias and said trenches;k) chemically/mechanically polishing back said second conformal conducting layer and said barrier layer to said third insulating layer to form conducting lines in said trenches and to form conducting plugs in said via holes, said conducting lines self-aligned to said conducting plugs;l) repeating steps b) through k) for each additional level of electrically conducting interconnections as required to complete the wiring of said integrated circuits.