Patent ID: 7772680
Filing Date: 2010-08-10
Classification: H01L,Y10S

Abstract:
1. An arrangement of fuse-type constructions, comprising: a semiconductor substrate comprising a surface; a plurality of electrically conductive interconnects having contact surfaces at or beneath a first elevational level relative to the substrate, an entirety of the substrate surface being below the first elevational level; a plurality of electrically conductive links extending upwardly from the contact surfaces of the electrically conductive interconnects; and an electrically conductive plate in direct and physical contact with all of the electrically conductive links of said plurality of electrically conductive links and in electrical contact with all of the electrically conductive interconnects of the plurality of electrically conductive interconnects, the electrically conductive plate being at a second elevational level above said first elevational level, each individual link of said plurality of electrically conductive links contacting the electrically conductive plate in a different one of a plurality of non-overlapping regions relative to all other links of said plurality of electrically conductive links, each of said non-overlapping regions of the plurality of non-overlapping regions being defined to be a fuse-type construction; and wherein the plurality of electrically conductive interconnects comprises three or more electrically conductive interconnects and wherein the plurality of electrically conductive links comprises three or more electrically conductive links.