Patent ID: 6664603
Filing Date: 2003-12-16
Classification: H01L,Y10S

Abstract:
A semiconductor device having a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor, the semiconductor device comprising:a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; and a first drain-gate wiring layer that is continuous with the first gate-gate electrode layer, provided in a manner to extend in a direction transverse to the first gate-gate electrode layer, and provided at least between an active region for the first load transistor and an active region for the first driver transistor, wherein a distance L1 between the edges of the first drain-gate wiring layer and the active region for the first driver transistor is greater than or equal to a distance L2 between the edges of the first drain-gate wiring layer and the active region for the first load transistor.