Patent ID: 9130026
Filing Date: 2015-09-08
Classification: H01L

Abstract:
1. A III-N (tri nitride) semiconductor device, comprising: a buffer layer disposed above a semiconductor substrate; a crystalline or poly crystalline III-N layer disposed above the buffer layer; a crystalline passivation layer disposed above the crystalline or poly crystalline III-N layer; a source region and a drain region disposed onto and in direct contact with an upper region of the crystalline or poly crystalline III-N layer; a gate electrode disposed above the crystalline passivation layer at a lateral position between the source region and the drain region; a gate dielectric disposed beneath the gate electrode and abutting a top surface of the crystalline passivation layer, wherein the gate dielectric horizontally extends over upper surfaces of the source region and the drain region; and an amorphous passivation layer abutting the top surface of the crystalline passivation layer on opposite sides of the gate dielectric.