Patent ID: 9070711
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: forming a replacement gate structure that is positioned within a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; performing at least one etching process to recess said sidewall spacers and said replacement gate structure and thereby define recessed sidewall spacers and a recessed replacement gate structure, wherein an upper surface of said recessed sidewall spacers is positioned above an upper surface of said recessed replacement gate structure; forming an etch stop layer above said recessed sidewall spacers and said recessed replacement gate structure, said etch stop layer defining an etch stop recess; forming a second layer of insulating material in said etch stop recess; forming a third layer of insulating material above said second layer of insulating material and above said etch stop layer; with said etch stop layer in position, performing at least one first contact etching process to form a self-aligned contact opening that extends through at least said third layer of insulating material and said first layer of insulating material and thereby exposes a source/drain region of said transistor; and with said etch stop layer in position, forming a self-aligned contact in said self-aligned contact opening that is conductively coupled to said source/drain region.