Patent ID: 6546532
Filing Date: 2003-04-08
Classification: G06F

Abstract:
A method for identifying cells in a circuit design database using a placement tool, the circuit design database having one or more levels of hierarchy including one or more logic functions composed of one or more other logic functions and/or one or more leaf cells, the leaf cells forming the lowest level of hierarchy in the circuit design database, each of the leaf cells having one or more inputs and one or more outputs, the circuit design database having one or more nets, each of the nets connecting an output port of a source leaf cell to an input port of one or more destination leaf cells, the method comprising the steps of:selecting one or more placed leaf cells as base objects; identifying an input port of selected base objects; selecting one or more source leaf cells in the circuit design database that have an output port connected to the identified input port of the selected base objects; and performing a placement function on selected ones of the selected source leaf cells.