Patent ID: 9006860
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A CMOS semiconductor die comprising: a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas within the insulation layer collectively covering a first area of the major surface within a first device region over the major surface; a plurality of N-metal gate areas within the insulation layer collectively covering a second area of the major surface within the first device region; a plurality of dummy P-metal gate areas within the insulation layer collectively covering a third area of the major surface within a second device region over the major surface; and a plurality of dummy N-metal gate areas within the insulation layer collectively covering a fourth area of the major surface within the second device region; wherein the N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in size compared to the P-metal gate areas of the plurality P-metal gate areas within the first device region, and the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in size with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region.