Patent ID: 6330199
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell array blocks respectively including a plurality of partial blocks and a predetermined number of redundant partial blocks,said plurality of memory cell array blocks also including a plurality of column select signal lines connected to the plurality of partial blocks and a predetermined number of redundant column select signal lines connected to the predetermined number of redundant partial blocks;control signal generators, respectively included for each of the predetermined number of redundant column select signal lines, that generate a predetermined number of block control signals by dividing the plurality of memory cell array blocks into a predetermined number of groups;a predetermined number of defective redundant enable signal generators included for each of the predetermined number of redundant column select signal lines, that generate a predetermined number of redundant enable signals when defective addresses corresponding to each of the predetermined number of block control signals are input; andselectors, respectively included for each of the predetermined number of redundant column select signal lines, that generate each of the predetermined number of redundant enable signals as a select signal that selects the corresponding redundant column select signal line in response to each of the predetermined number of block control signals.