Patent ID: 9018692
Filing Date: 2015-04-28
Classification: H01L

Abstract:
1. An integrated circuit device including a plurality of layers of memory cells, comprising: a first level including a plurality of first-type conductor lines which are symmetrical about respective primary axes and arranged generally in parallel; a second level over the first level, and including a plurality of second-type conductor lines arranged generally in parallel and orthogonal to the plurality of first-type conductor lines in the first level; a third level over the second level, and including a plurality of first-type conductor lines which are symmetrical about respective primary axes and arranged generally in parallel; a fourth level over the third level, and including a plurality of second-type conductor lines arranged generally in parallel and orthogonal to the plurality of first-type conductor lines in the first level; the primary axes of first-type conductor lines in the plurality of first-type conductor lines in the first level being aligned with the primary axes of corresponding first-type conductor lines in the plurality of first-type conductor lines in the third level; the primary axes of second-type conductor lines in the plurality of second-type conductor lines in the second level being aligned with the primary axes of corresponding second-type conductor lines in the plurality of second-type conductor lines in the fourth level; a first array of data storage structures at cross points between upper surfaces of the first-type conductor lines in the first level and lower surfaces of the second-type conductor lines in the second level; a second array of data storage structures at cross points between lower surfaces of the first-type conductor lines in the third level and upper surfaces of the second-type conductor lines in the second level; and a third array of data storage structures at cross points between upper surfaces of the first-type conductor lines in the third level and lower surfaces of the second-type conductor lines in the fourth level; wherein the first-type conductor lines act as one of word lines and bit lines, and the second-type conductor lines act as the other of word lines and bit lines, including: crossbar structures of fill material orthogonal to the plurality of first-type conductor lines in the first and third levels, the crossbar structures having vertical features of fill material between stacks in a plurality of self-aligned stacks of first-type conductor lines extending from a level of bit lines in a bottom layer to a level of first-type conductor lines in a top layer in the plurality of self-aligned stacks of first-type conductor lines, and including horizontal features of fill material between the first-type conductor lines in the stacks extending from a region between first-type conductor lines in one of the stacks to a region between first-type conductor lines in another of the stacks, leaving openings in the fill material through which the plurality of first-type conductor lines extend, and wherein the crossbar structures are disposed at spaced apart locations whereby there are regions between the crossbar structures across which the plurality of first-type conductor lines extend; and isolation material, different than said fill material, between the plurality of first-type conductor lines in said regions between the crossbar structures.