Patent ID: 7491995
Filing Date: 2009-02-17
Classification: B82Y,H01L

Abstract:
1. A memory, comprising: a nanofin transistor, including a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions, the nanofin transistor further comprising a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator; a data-bit line connected to the first source/drain region; at least one word line connected to the surrounding gate of the nanofin transistor; and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential, wherein the vertically-oriented channel region includes crystalline silicon, and wherein the vertically-oriented channel region either is in a crystalline nanofin structure grown on a crystalline wafer or is in a crystalline nanofin structure defined by etches into a crystalline wafer wherein the nanofin structure is formed using a sidewall spacer technique that involves forming a sidewall spacer to provide the nanofin structure with a cross-sectional thickness in a first direction that is approximately equal to a thickness of the sidewall spacer and substantially less than a minimum feature size.