Patent ID: 6107211
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of forming poly gate and polycide gate in a semiconductor device fabricated on a starting substrate, said method comprising:(a) forming a gate oxide layer on said starting substrate;(b) sequentially depositing a polysilicon layer and a capped dielectric layer;(c) patterning a poly gate by using a first photoresist layer, and etching said capped dielectric layer and a portion of said polysilicon layer;(d) removing said first photoresist layer;(e) forming spacers on the sidewall of said polysilicon layer;(f) depositing a silicide layer;(g) patterning a polycide gate by using a second photoresist layer, and etching said silicide layer and said polysilicon layer; and(h) removing said second photoresist layer.