Patent ID: 6051464
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method for fabricating a capacitor of a dynamic random access memory DRAM), the method comprising:providing a substrate, wherein the substrate contains a pre-formed field effect transistor, and wherein the pre-formed field effect transistor contains source/drain regions;forming a dielectric layer on the substrate;forming an etching stop layer on the dielectric layer;patterning the etching stop layer and the dielectric layer to form a contact window to expose the source/drain regions;forming a first conducting layer on the etching stop layer, wherein the first conducting layer covers the etching stop layer and fills the contact window, and wherein the first conducting layer is electrically connected to the source/drain regions through the contact window;forming a hemispherical-grained silicon (HSG) layer on the first metal layer, wherein the HSG layer comprises a plurality of hemispherical silicon grains;forming a plurality of spacers wherein each of the spacers individually surrounds one of the hemispherical silicon grains correspondingly, and wherein each of the spacers exposes a top surface of the surrounded hemispherical silicon grain, and wherein each of the spacers is separated from a neighboring one by a distance;removing the HSG layer and a portion of the first conducting layer by using the a mask consisting of the spacers and using the etching stop layer as an etching end point;removing the spacers;forming a dielectric film on a exposed surface of the first conducting layer; andforming a patterned second conducting layer on the substrate.