Patent ID: 7657692
Filing Date: 2010-02-02
Classification: G06F,G06K,G07C

Abstract:
1. A peripheral component interconnect express (PCIE) to extended universal-serial bus (EUSB) bridge comprising: a PCIE physical layer having an input connection to a first pair of differential lines and having an output connection to a second pair of differential lines; a PCIE data link layer, coupled to the PCIE physical layer, for sequencing PCIE packets and for detecting link errors; a PCIE transaction layer, coupled to the PCIE data link layer, for inserting a header for a PCIE protocol into outbound PCIE packets, and for extracting the header from inbound PCIE packets; an EUSB transaction layer for inserting a header for a EUSB protocol into output parallel words, and for extracting the header from input parallel words; an EUSB data-link layer, coupled to the EUSB transaction layer, for adding sequence numbers and checksums to packets of the output parallel words, and for verifying checksums and using the sequence numbers to order the input parallel words; an EUSB bus interface, having an input connection to a first pair of differential lines and having an output connection to a second pair of differential lines; an EUSB physical layer, coupled to the EUSB data-link layer and to the EUSB bus interface, for converting incoming serial data from the EUSB bus interface to the input parallel words and for converting the output parallel words into outgoing serial data for transmission over the EUSB bus interface; and a high-level bridging converter module, coupled to the PCIE transaction layer and to the EUSB transaction layer, for converting PCIE packets into parallel words forming EUSB packets, whereby PCIE is bridged to EUSB.