Patent ID: 8378654
Filing Date: 2013-02-19
Classification: G05F,H02M

Abstract:
1. A voltage regulator circuit, comprising: a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, and a first op-amp output; a PMOS transistor; a first NMOS transistor; and a bias circuit outside the op-amp, wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and the bias circuit is electrically coupled to the gate of the first NMOS transistor and configured to bias the first NMOS transistor in saturation mode.