Patent ID: 7660969
Filing Date: 2010-02-09
Classification: G06F

Abstract:
1. An apparatus for concurrently dispatching instructions of a plurality of threads of execution in a microprocessor, the apparatus comprising: a group indicator, for each thread of the plurality of threads, that indicates which one of a plurality of groups of the plurality of threads said thread belongs to; a group priority indicator, for each group of said plurality of groups, that indicates a priority of said group, said priority indicating a priority for dispatching instructions of the plurality of threads of said group relative to other groups of said plurality of groups; hardware selection logic, coupled to said group indicators and said group priority indicators, configured to select a thread of the plurality of threads, for dispatching to execution an instruction thereof, based on said group indicators and said group priority indicators; and a group priority generator, configured to generate dynamic values of said group priority indicators, wherein said group priority generator is configured to change said priorities of said plurality of groups only after each issuable thread in a highest priority group of said plurality of groups has had its opportunity in round-robin order to issue an instruction.