Patent ID: 8873303
Filing Date: 2014-10-28
Classification: G11C

Abstract:
1. A method of operating a non-volatile memory having an array of memory cells, comprising: providing a set of read/write circuit stacks for operating on a group of memory cells of the array in parallel; operating each stack of read/write circuits on a subgroup of memory cells in parallel by cooperating a subgroup of sense amplifiers and data latches with a processor; latching input or output data of the subgroup of sense amplifiers with the data latches; providing each sense amplifier with at least one node with sense amplifier data; coupling the processor to the at least one node with sense amplifier data and the data latches for processing data therebetween; providing the processor with an input logic and an output logic; selectively coupling the input logic to either the at least one node with sense amplifier data or the data latches to retrieve data therefrom, and responsive to a first set of control signals to generate first resultant data; and generating second resultant data with the output logic responsive to a second set of control signals and the first resultant data, and selectively coupling the processor to either the at least one node with sense amplifier data or the data latches to store the second resultant data thereto.