Patent ID: 6373342
Filing Date: 2002-04-16
Classification: H03K,H03L

Abstract:
A circuit for controlling the signal delay in a charging capacitor inverter by varying the trip point voltage level of an in-line trip point controlled transistor, thereby effecting the delay time before the circuit's output switches, wherein the in-line trip point controlled transistor is conductive when a voltage associated with a discrete charging capacitor exceeds the trip point voltage level of the inline trip point controlled transistor such that output signal jitter associated with the circuit is reduced below that achievable without use of an in-line trip point controlled transistor, wherein the circuit comprises:an input transistor; a charging capacitor; an in-line trip point controlled transistor, and an output transistor, and further wherein the output of said current source is coupled to the positive side of said charging capacitor, to the source of said in-line trip point transistor, and to the drain of said input transistor; the drain of said in-line trip point traitor is coupled to the drain of said output transistor and to the output signal terminal; a dc bias input control voltage is coupled to the gate of said in-line trip point transistor; an input signal is coupled to the gate of said input transistor and to the gate of said output transistor; a power supply voltage is coupled to the input of said current source; and the sources of said input and output transistors and the negative side of said charging capacitor are coupled to signal ground.