Patent ID: 8594114
Filing Date: 2013-11-26
Classification: G11C

Abstract:
1. A data bus structure for a data bus comprising: a first data bus group associated with a first non-zero speed requirement; a second data bus group associated with a second non-zero speed requirement different from the first data bus group; sorting circuitry for assigning input data to either the first data bus group and to the second data bus group, respectively, or to the second data bus group and to the first data bus group, respectively, depending upon the relative non-zero speed characteristics of the input data; a first multiplexer for receiving data from the first data bus group having an input for receiving a first clock signal, and an output coupled to a first data output line; and a second multiplexer for receiving data from the second data bus group having an input for receiving a second clock signal, and an output coupled to a second data output line.