Patent ID: 8165258
Filing Date: 2012-04-24
Classification: H03L,H04L

Abstract:
1. A clock generating device, comprising: a frequency divider, having an input node coupled to a transmission interface, for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit, having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node; wherein the frequency divider divides a clock recovery (CR) pattern of the input data to generate the reference clock signal with a desired frequency for the clock/data recovery circuit, and the clock/data recovery circuit locks the reference clock signal to generate the output clock signal within an interval of the CR pattern in a link training process.