Patent ID: 7362318
Filing Date: 2008-04-22
Classification: G09G,H01L,H03M

Abstract:
1. A display apparatus presenting a gray-scale expression according to a digital signal of a plurality of bits, comprising: a plurality of voltage nodes through which a plurality of gray-scale voltages including a series of levels in a gradual manner are transmitted, respectively; a plurality of first signal lines transmitting said plurality of bits of said digital signal, respectively; a plurality of second signal lines provided along the same direction as said plurality of first signal lines and transmitting inverted signals of said plurality of bits, respectively; a decode circuit selecting one of said plurality of gray-level voltages according to said digital signal to output a selected gray-scale voltage among said plurality of gray-scale voltages to an output node as a display voltage; and pixels each for displaying a brightness value corresponding to said display voltage selected by said decode circuit, wherein said decode circuit includes a plurality of decode paths formed so as to intersect said first and second signal lines between said plurality of voltage nodes and said output node, each of said plurality of decode paths include a plurality of field effect transistors corresponding to said plurality of bits of said digital signal, said plurality of field effect transistors are connected serially between said output node and a corresponding voltage node of said plurality of voltage node, each of the gates of said plurality of field effect transistors is connected to one signal line of said first and second signal lines transmitting the corresponding bit and the inverted signal of the corresponding bit, respectively, in each of said plurality of field effect transistors, a capacitance is formed between the other signal line not connected to said gate of said first and second signal lines and a node to which the source or drain thereof is connected electrically, and in one decode path selected according to said digital signal among said plurality of decode paths, said plurality of field effect transistors are all turned on and, in each of the other decode paths, at least one of said plurality of field effect transistors is turned off.