Patent ID: 8461679
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A chip package comprising: a substrate comprising a first pad having a top surface with a first region, a second region and a third region between said first and second regions, and a solder mask layer on said first and second regions, wherein an opening in said solder mask layer is over said third region; a chip over said substrate, wherein said chip comprises a second pad vertically over said third region; a copper pillar between said third region and said second pad, wherein said copper pillar has a width greater than that of said opening; a nickel-containing layer between said third region and said copper pillar; a tin-containing layer between said nickel-containing layer and said third region, wherein said tin-containing layer comprises a lower portion in said opening, and an upper portion over said lower portion, over said opening and above a horizontal level of a top surface of said solder mask layer, wherein said top surface of said solder mask layer faces said chip; and an underfill between said chip and said substrate.