Patent ID: 8884680
Filing Date: 2014-11-11
Classification: G05F,H03K

Abstract:
1. A signal electric potential conversion circuit, comprising: a capacitor having one end receiving an input signal, and having the other end connected to a termination node; and a termination circuit configured to receive a potential of the termination node, wherein the termination circuit includes: an impedance of the first connection element is reduced when the potential of the termination node is lower than a first potential higher than the power supply voltage of the second power supply, and an impedance of the second connection element is reduced when the potential of the termination node is higher than a second potential which is lower than the power supply voltage of the first power supply and which is higher than the first potential, wherein the termination circuit includes: wherein the control potential generating circuit includes: wherein the control potential generating circuit controls a gate potential of the second NMOS transistor such that a source potential of the second NMOS transistor is equal to the first potential output from the bias circuit, and outputs the gate potential of the second NMOS transistor as the control potential.