Patent ID: 6108256
Filing Date: 2000-08-22
Classification: G11C

Abstract:
A precharge circuit for precharging bit lines coupled to a read sense amplifier and a RAM cell, comprising:a set of precharge transistors coupled to said bit lines for precharging said bit lines, one precharge transistor per bit line;a first transistor being operatively coupled to turn on said set of precharge transistors when said RAM cell is not being read, said first transistor being operative to reduce the gate-to-source voltage V.sub.GS of said set of precharge transistors such that each of said precharge transistors output a reduced precharge voltage to the associated bit line; anda transistor pair coupled to said set of precharge transistors and being operative to switch said precharge transistors for reading said RAM cell, said RAM cell outputting a differential signal onto said bit lines when said precharge transistors are turned off, wherein said read sense amplifier monitors said bit lines to detect said differential signal on said bit lines as a data bit.