Patent ID: 6418550
Filing Date: 2002-07-09
Classification: H04L

Abstract:
A line error checking circuit for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said error checking circuit comprising:a differentiating circuit that generates a first differential signal for the first line and a second differential signal for the second line, which correspond to a time derivation of a potential curve of the respective first and second line; a reference signal source that provides a reference signal; a summing circuit that generates a sum signal representing the sum of the two differential signals and the reference signal; an assessment circuit that generates a no-error signal signaling a situation free from line errors is generated when the sum signal is equal to the reference signal or is within a predetermined range on both sides of the reference signal; and, when the no-error signal does not appear: generates a first error signal signaling a line error of the first line is generated when the first differential signal is equal to the sum signal; generates a second error signal signaling a short-circuit between both lines is generated when both differential signals are different from the sum signal; and generates a third error signal signaling a line error of the second line when the second differential signal is equal to the sum signal.