Patent ID: 6714466
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A semiconductor memory device comprising:a test means for performing a test operation for an alternative one of row and column, detecting defective cells on the alternative unit of the row and column; and a repair analysis means for performing a repair analysis in which a failed-address data involved in defective cells on the alternative one of the row and column are rearranged with including moving and exchanging between the failed-address data in a unit of row and column; wherein the repair analysis means includes: a temporary buffer unit having a plurality of temporary buffers for storing the failed-address data for the defective cells; a data buffer receiving the failed-address data stored in one of the temporary buffers; a storage means receiving the failed-address data from the data buffer and for rearranging a structure of the failed-address data; and a controller for controlling operations of the temporary buffer unit, the data buffer and the data storage means.