Patent ID: 6683355
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A system, comprising:a memory device having at least one semiconductor structure formed on a substrate assembly, said structure including: a raised source; a raised drain; a gate located between said source and said drain; a first capping layer in communication with at least a portion of said gate and said source; a first portion of a gate oxide region in communication with at least a portion of said gate and said source; said source, said gate, said first capping layer, and said first portion of said gate oxide region defining a first gap therein, said first gap having one of a gas and a vacuum therein, wherein no dielectric material is positioned between said first gap and any one of said gate, said source, said first capping layer, and said first portion of said gate oxide region; a first implant junction area located in said substrate assembly beneath said first gap and extending partially beneath said gate and said source; a second capping layer in communication with at least a portion of said gate and said drain; a second portion of said gate oxide region in communication with at least a portion of said gate and said drain; said drain, said gate, said second capping layer, and said second portion of said gate oxide region defining a second gap therein, said second gap having one of a gas and a vacuum therein, wherein no dielectric material is positioned between said second gap and any one of said gate, said drain, said second capping layer, and said second portion of said gate oxide region; and a second implant junction area located in said substrate assembly beneath said second gap and extending partially beneath said gate and said drain; a processor; and a bus connecting said processor and said memory device.