Patent ID: 6762647
Filing Date: 2004-07-13
Classification: H03F,H03G

Abstract:
An electronic circuit comprising:a bias transistor comprising a base and a collector, the bias transistor outputting a reference DC bias voltage to a power amplifier; a clamping transistor comprising a base and a collector, the collector of the clamping transistor being coupled to the collector of the bias transistor; a buffer transistor comprising a base and an emitter, the emitter of the buffer transistor being coupled to the base of the clamping transistor; a peak detector diode comprising an anode and a cathode, the cathode of the peak detector diode being coupled to the base of the buffer transistor; a first set of diodes and a second set of diodes, wherein the first set of diodes is coupled between an output of the power amplifier and the anode of the peak detector diode, and wherein the second set of diodes is coupled between the anode of the peak detector diode and a ground.