Patent ID: 8516447
Filing Date: 2013-08-20
Classification: G06F

Abstract:
1. A computer-implemented method, comprising: executing a host code section; identifying, during execution of the host code section, a host code block in the host code section; categorizing, during execution of the host code section, the host code block by a function, wherein the function is performance sensitive or not performance sensitive; and upon categorizing the host code block by the function as being not performance sensitive, processing the host code block, wherein processing the host code block includes: copying, during execution of the host code section, the host code block from the host code section to a stub code block in a stub code section; copying, during execution of the host code section, the stub code block to the host code block in the host code section; re-routing at least one reference of the host code block to be a reference of the stub code block prior to termination of execution of the host code section; and re-routing at least one reference of the stub code block to be a reference of the host code block prior to termination of execution of the host code section.