Patent ID: 8546947
Filing Date: 2013-10-01
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer, and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug; a first dielectric layer between said first and second copper layers, wherein said copper plug is in said first dielectric layer; an insulating layer over said silicon substrate, said first dielectric layer and said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening; a first metal layer on said first contact point and over said insulating layer, wherein said first metal layer comprises a first conductive layer and an aluminum layer on said first conductive layer; a second dielectric layer over said first metal layer and said insulating layer, wherein a second opening in said second dielectric layer is over a second contact point of said first metal layer; and a second metal layer over said second contact point and said second dielectric layer, wherein said second metal layer comprises a second conductive layer and a gold-containing layer over said second conductive layer, wherein said second metal layer is connected to said second contact point through said second opening.