Patent ID: 7750707
Filing Date: 2010-07-06
Classification: H03H

Abstract:
1. An apparatus, comprising: a plurality of differential pairs of transistors implemented to receive a plurality of clock signals, wherein: a first plurality of switches, controlled by a first plurality of control signals including a first control signal and a second control signal, such that a first subset of the first plurality of switches is controlled by the first control signal, a second subset of the first plurality of switches is controlled by the second control signal, a third subset of the first plurality of switches is controlled by an inversion of the first control signal, and a fourth subset of the first plurality of switches is controlled by an inversion of the second control signal, implemented to select a sector by employing the first plurality of control signals, wherein a range between 0 degrees and 360 degrees is sub-divided into a plurality of sectors such that each sector includes a plurality of possible phases between that sector's uppermost phase and that sector's lowermost phase, inclusive; a second plurality of switches, controlled by a second plurality of control signals, implemented to select a phase of an output signal such that the selected phase is within the selected sector; a plurality of current sources implemented selectively to steer current to coupled sources of selected differential pairs of transistors of the plurality of differential pairs of transistors based on connectivity of the first plurality of switches and the second plurality of switches; and an output signal having the selected phase is output from coupled drains of the plurality of differential pairs of transistors, wherein the selected phase is included within the selected sector.