Patent ID: 6169028
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method for fabricating a metal interconnect structure, comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises a conductive layer formed therein; forming a dielectric layer on the semiconductor substrate; removing a part of the dielectric layer to form a dual damascene opening exposing the conductive layer and to form a trench in the dielectric layer; forming a conformal barrier layer on the dielectric layer; forming a copper layer on the barrier layer, wherein a part of the copper layer positioned in the trench has a thickness equal to a depth of the trench; forming a cap layer on the copper layer; removing a part of the cap layer and a part of the copper layer until the barrier layer is exposed; and removing a part of the copper layer, the exposed barrier layer, and a remaining part of the cap layer that are outside the trench and the dual damascene opening, so that the dielectric layer is exposed.