Patent ID: 7961123
Filing Date: 2011-06-14
Classification: H03M

Abstract:
1. An apparatus comprising: a clock generator that generates a plurality of clock signals; a plurality of analog-to-digital converters (ADCs), wherein each ADC is associated with at least one of the clock signals so as to sample an input signal at a plurality of sampling instants, and wherein a correlation function exists between samples from a two or more of the ADCs; a correction circuit that is coupled between the clock generator and at least one of the ADCs; and an estimator that is coupled to the correction circuit and each of the ADCs, wherein the estimator calculates the correlation function and iteratively provides adjustments to the correction circuit to account for sampling mismatch between the plurality of ADCs by employing a gradient descent formulation for a predetermined cost function, wherein the predetermined cost function is a function of the correlation function.