Patent ID: 8525290
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A method for forming a memory cell access array, comprising: providing a single-crystalline semiconductor body having a first conductivity type; forming a layer of a hard mask material over the semiconductor body; forming first trenches in a first direction to a first depth in the semiconductor body, resulting in ridges surmounted by a patterned hard mask; depositing an antireflective coating material to fill the first trenches and to form a thin layer of antireflective coating material over the patterned hard mask; forming second isolation trenches in a direction orthogonal to the first direction to a second depth less than the first depth, resulting in crenellations in the ridges isolating single-crystalline semiconductor islands surmounted by hard mask material; filling the first and second trenches with a dielectric fill and planarizing to expose the hard mask material; removing the hard mask material; performing a first implant of a second conductivity type to a depth less than the first depth; and performing a second implant of the first conductivity type to a depth less than the depth of the first implant.