Patent ID: 6200855
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device having a cell region, a core region and a peripheral region, comprising:forming a gate electrode on a semiconductor substrate, and covering an upper surface and side walls of said gate electrode with an insulating material;implanting impurity ions into said semiconductor substrate at both sides of said gate electrode to form a first conduction type region and a second conduction type region;forming a first insulating layer on said semiconductor substrate, covering said gate electrode;etching said first insulating layer until a surface of said gate electrode and a surface of said semiconductor substrate of said first conduction type region are exposed, so as to form contact holes;filling said contact holes with a metal layer to form contact plugs;forming a pad on said first insulating layer so as to be electrically connected to said contact plugs, and making an upper face and side walls of said pad covered with the insulating material;forming a second insulating layer on said first insulating layer, covering said pad;sequentially etching said second and first insulating layers and said insulating material until a surface of said semiconductor substrate of at least said second conduction type region and a surface of said pad are exposed, so as to form second contact holes; andfilling said second contact holes with a metal layer to form contacts for connecting a wiring.