Patent ID: 6108807
Filing Date: 2000-08-22
Classification: G01R

Abstract:
An apparatus for enabling individual control of functional input/output (I/O) pins in an integrated circuit which includes a boundary scan test architecture, said apparatus comprising:at least one boundary scan cell coupled to ones of said functional input/output pins of said integrated circuit, said boundary scan cell including a capture flip-flop responsive to input signals and an update flip-flop responsive to an output of said capture flip-flop; anda set of logic gates coupled to said boundary scan cell, said set of logic gates including a first logic gate operable to receive a control signal and having an output coupled to a clock input of said update flip flop for blocking said clock input upon application of said control signal, wherein said I/O pin is alternately configurable, depending on content of said capture flip-flop when said control signal is applied to receive contents of said update flip-flop and to be controlled by system logic of said integrated circuit wherein said update flip-flop contents is either logic 0 or logic 1.