Patent ID: 6215709
Filing Date: 2001-04-10
Classification: G11C

Abstract:
In a memory device storing data in an array of rows and columns, the array including a plurality of I/O lines selectively coupled to either respective sense amps responsive to a global column signal or to a respective data write driver responsive to an I/O select signal, a method of biasing the I/O lines before the I/O lines are coupled to either the sense amps or the data write drivers, the method comprising:prior to accessing the memory array, determining whether the access with be a read access or a write access;if the access is determined to be a read access, biasing at least some of the I/O lines to a bias voltage for a first period of time; andif the access is determined to be a write access, biasing at least some of the I/O lines to a bias voltage for a second period of time that is shorter than the first period of time.