Patent ID: 6614067
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A polysilicon dual gate structure, on a semiconductor substrate, featuring a metal plug structure, located overlying, and contacting, a dopant interface region, in said polysilicon dual gate structure, comprising:said polysilicon dual gate structure, on an underlying gate insulator layer, traversing a first region of said semiconductor substrate, and traversing a second region of said semiconductor substrate; insulator spacers on the sides of said polysilicon dual gate structure; N type, source/drain regions, in an area of said first region of said semiconductor substrate, not covered by said polysilicon dual gate structure, or by said insulator spacers; P type, source/drain regions, in an area of said second region of said semiconductor substrate, not covered by said polysilicon dual gate structure, or by said insulator spacers; an N type region, located in first portion of said polysilicon dual gate structure, in a area in which said first portion of said polysilicon dual gate structure overlays said first region of said semiconductor substrate; a P type region, located in a second portion of said polysilicon dual gate structure, in an area in which said second portion of said polysilicon dual gate structure overlays said second region of said semiconductor substrate; a metal silicide layer located on the top surface of said polysilicon dual gate structure, on the top surface of said N type, source/drain region, and on the top surface of said P type, source/drain region; an insulator layer on said polysilicon dual gate structure, on said N type, source/drain region, and on said P type, source/drain region; a first opening in said insulator layer, exposing a first portion of said metal silicide layer, in region in which said first portion of said metal silicide layer directly overlays the dopant interface, in said polysilicon dual gate structure, with said dopant interface comprised of the interface between said P type region, and said N type region; a second opening in said insulator layer, exposing a second portion of said metal silicide layer, in a region in which said second portion of said metal silicide layer overlays a portion of said N type region, in said polysilicon dual gate structure; a third opening in said insulator layer, exposing a third portion of said metal silicide layer, in a region in which said third portion of said metal silicide layer overlays a portion of said P type region, in said polysilicon dual gate structure; a first metal plug structure in said first opening; a second metal plug structure in said second opening; a third metal plug structure in said third opening; a first metal interconnect structure, overlying and contacting, said second metal plug structure; and a second metal interconnect structure, overlying and contacting, said third metal plug structure.