Patent ID: 6305004
Filing Date: 2001-10-16
Classification: G06F

Abstract:
A method for automatically wiring nets that personalize an integrated circuit chip, module or card while improving yield, reducing capacitance and noise coupling, the method comprising the steps of:a) converting the integrated circuit chip, module or card into a grid graph and assigning an initial cost to arcs forming the grid graph, the grid graph and the initial cost being suited to a maze router;b) applying the maze router to provide an initial routing for all the nets on the grid graph and modifying the arc costs after routing each of the nets, the modified arc cost conforming with the maze router;c) iteratively rerouting with the maze router all the nets on the grid graph and modifying the costs of the arcs until changes in the total cost of the arcs fall below a predetermined threshold; andd) repeating steps a) through c) measuring at the end of each cycle the yield, capacitance, power, or noise coupling to determine if changes in the costs translates into an improvement.