Patent ID: 6249027
Filing Date: 2001-06-19
Classification: H01L

Abstract:
A semiconductor device comprising:a partially depleted SOI device including (a) a semiconductor substrate, (b) an insulating layer formed along a surface of said semiconductor substrate, and (c) a transistor formed on said insulating layer such that said insulating layer is interposed between said transistor and said semiconductor substrate, said transistor including source and drain regions of a first conductivity type formed on said insulating layer, an intermediate region of a second conductivity type formed on said insulating layer and between said source and drain regions, and a gate electrode aligned over said intermediate region, wherein said intermediate region includes a depletion region defining a channel of said transistor and a non-depletion region defining a bulk of said transistor;first, second, third and fourth terminals electrically coupled to said source region, said drain region, said gate electrode and said bulk, respectively; and,a bias voltage generator, said bias voltage generator selectively supplying a single selected bias voltage directly to said fourth terminal wherein said fourth terminal is isolated from said first through third terminals and further wherein:said bias voltage is supplied directly to said fourth terminal and said bulk of said transistor to tune a threshold voltage of said transistor of said partially depleted SOI device to account for variations in the processing of said partially depleted SOI device, the temperature of said partially depleted SOI device and the activity of said partially depleted SOI device.