Patent ID: 7471130
Filing Date: 2008-12-30
Classification: G11C,H03L

Abstract:
1. A clock synchronization and skew adjustment circuit comprising: a clock source; a delay line having a plurality of delay elements coupled to the clock source, wherein the plurality of delay elements of the delay line are sequentially coupled in a delay line chain, where the delay line has a plurality of output taps, where the plurality of delay elements of the delay line are graduated in unit time delay, and where each delay element of the plurality of delay elements has a fixed non-zero amount of unit time delay; and a control circuit coupled to the delay line and coupled to the clock source, wherein the control circuit is adapted to synchronize a generated clock signal of the clock synchronization and skew adjustment circuit to a clock signal received from the clock source by selecting an output tap of the plurality of output taps of the delay line; and wherein at a selected point in the delay line a following section having a fixed non-zero delay of one or more delay elements is graduated so that each delay element in the following section of one or more delay elements has a greater fixed non-zero unit time delay than delay elements in a previous section having a fixed non-zero delay of one or more delay elements in the delay line.