Patent ID: 6320446
Filing Date: 2001-11-20
Classification: G06F,H03K

Abstract:
An improved circuit, the circuit comprising:a first low-power CMOS circuit, coupled to a low power supply level and ground, having an output for providing a control signal at either a high level equal to the low power supply level or a low level equal to the ground level;a level shifting circuit, coupled to a high power supply level and ground, having an input coupled to receive the control signal and having an output for providing a level-shifted control signal having a high level equal to a high power supply level and a low level equal to the ground level;a second low-power CMOS circuit, coupled to the low power supply level and ground, having an output for providing a logic signal at either a high level equal to the low power supply level or a low level equal to a ground level;a third low-power CMOS circuit, coupled to a low power supply signal and ground, having an input for receiving the logic signal;a pass transistor having gate, drain and source terminals, wherein the drain terminal is coupled to the output of the second low-power CMOS circuit to receive the logic signal, the source terminal is coupled to the input of the third low-power CMOS circuit, and the gate terminal is coupled to the output of the level shifting circuit, with a threshold voltage of the pass transistor being less than the difference between the high and low power supply levels;where the level shifted control signal has an amplitude that is greater than the low power supply level, so that a large current can flow between the drain terminal and the source terminal, wherein when the logic signal is transmitted between the second low power CMOS circuit and the third low power CMOS circuit a charge time and a discharge time of the parasitic capacitance are minimized.