Patent ID: 7748001
Filing Date: 2010-06-29
Classification: G06F

Abstract:
1. A processor comprising: a first thread livelock unit coupled to a first logical processor; a second logical processor; wherein said first thread livelock unit, in response to detecting a first special condition, which includes an instruction buffer associated with the first logical processor being empty and the second logical processor performing a high priority lock operation that is to assert a previous stall of the first logical processor, and the second logical processor de-asserting the previous stall of the first logical processor, is to bypass a wait state which is to determine if a live-lock condition exists and to assert a stall of the second logical processor, and wherein the first thread live-lock unit, in response to determining a second special condition has lasted longer than a first amount of time, is to request priority from an arbitrator for the first logical processor over at least the second logical processor.