Patent ID: 6357018
Filing Date: 2002-03-12
Classification: G06F

Abstract:
A computer system comprising:at least one processor; at least one memory; basic input output system (BIOS) firmware stored in said at least one memory, said BIOS firmware including instructions for causing said at least one processor to perform a prescribed continuity and integrity check of a memory bus channel having a serial topology; and memory bus channel having a serial topology, said memory bus channel including data lines, control lines, and clock lines extending from a first end of said memory bus channel to a termination end of said memory bus channel opposite the first end, wherein said memory bus channel further includes a memory bus controller and a clock generator, the memory bus controller being disposed at the first end of said memory bus channel and the clock generator being disposed at the termination end of said memory bus channel, further wherein at least one memory module is disposed in said memory bus channel in a serial manner from the first end to the termination end, wherein each data line includes a pull-down resistor coupled between the data line and a ground potential, the pull-down resistor further being coupled to the data line at a position in-between the memory bus controller and a first memory module of said memory bus channel, wherein each data line further includes a pull-up resistor coupled between the data line and a termination voltage potential at the termination end of said memory bus channel, and further wherein a state of a respective data line can be read by the memory controller during the continuity and integrity check of the data line.