Patent ID: 9098418
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A processor comprising: a cache hierarchy comprising at least two caches arranged in two levels; a first prefetch unit associated with a first cache of the at least two caches, wherein the first prefetch unit is configured to maintain a first prefetch table comprising a plurality of entries, wherein each entry comprises a stream identifier (ID) and attributes associated with a corresponding stream; a second prefetch unit associated with a second cache of the at least two caches, the second prefetch unit being different from the first prefetch unit, wherein the second prefetch unit is configured to maintain a second prefetch table with an entry for each entry in the first prefetch table including a stream ID and attributes associated with a corresponding stream; and a prefetch training mechanism associated with the first cache; wherein the prefetch training mechanism is configured to generate training information for each of a plurality of streams, wherein the training information is utilized for determining whether the first prefetch unit is to issue prefetch requests for data corresponding to the plurality of streams into the first cache; wherein the prefetch unit is configured to convey said training information to the second prefetch unit; and wherein said second prefetch unit is configured to issue prefetch requests for data corresponding to a plurality of streams into the second cache based on attributes stored in the second prefetch table.