Patent ID: 8719626
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A system comprising: a processor comprising a plurality of channel cards, each having one or more channels; a switch operatively coupled to the one or more channels; one or more I/O devices comprising one or more ports, the one or more I/O devices being operatively coupled to the switch by the one or more ports; a plurality of control units, wherein each control unit controls communication between the processor and at least one of the one or more I/O devices and comprises at least one of the one or more channels and at least one of the one or more ports; and a memory, disposed on the processor, operable for storing information relating to detected channel path errors associated with each of the plurality of control units, wherein the memory comprises a two dimensional array associated with each of the plurality of control units, wherein the two dimensional array comprises one or more rows that correspond to channel paths and one or more columns that correspond to time periods, and wherein each element of the two dimensional array includes a counter configured to store a number of errors that occurred on the channel path associated with the element during the time period associated with the element.