Patent ID: 6185703
Filing Date: 2001-02-06
Classification: G11C

Abstract:
A microprocessor comprising:an embedded memory, the embedded memory including a tag memory;a plurality of input connectors to receive input signals from an external bus;a plurality of output connectors to provide output signals to the external bus;a plurality of reconfigurable input and output signal paths, coupled to the embedded memory and the plurality of input and output connectors, which, when the microprocessor is operating in a direct access test mode, provide the input signals from an external bus directly to the embedded memory and the output signals directly from the embedded memory to the external bus and disable normal operation of the microprocessor;a dedicated memory test queue, coupled to the plurality of reconfigurable input and output signal paths, configured to receive and store a plurality of memory testing commands when coupled to the external bus in a single external bus clock cycle; anddedicated direct access test mode control logic, coupled to the dedicated memory test queue, configured to provide the plurality of memory testing commands to the embedded memory serially over a plurality of consecutive microprocessor clock cycles, the plurality of microprocessor clock cycles being equal in duration to the single external bus clock cycle.