Patent ID: 8053301
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A method of forming a device, comprising the following steps in the order named: providing a wafer having a pad oxide layer, the wafer including a silicon substrate and having nFET regions and pFET regions; removing the pad oxide layer to expose a silicon channel above the nFET regions and the pFET regions; performing a wet oxide etch preclean on the silicon channel; growing a silicon germanium (SiGe) epitaxial layer on the silicon channel, wherein the silicon germanium (SiGe) epitaxial layer is directly connected to the silicon channel and functions as part of the silicon channel; depositing a hardmask layer on the silicon germanium (SiGe) epitaxial layer; applying a positive photoresist layer on the hardmask layer above the pFET regions; removing the hardmask layer above the nFET regions; removing the positive photoresist layer; removing the silicon germanium (SiGe) epitaxial layer above the nFET regions; and removing the hardmask layer above the pFET regions.