Patent ID: 6537862
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A method of fabricating a semiconductor device having a gate all around (GAA) structure transistor comprising the steps of:preparing a SOI substrate comprising a SOI layer and a buried oxide layer on an underlying substrate layer; patterning the SOI layer to form an active layer pattern; stacking an etch stopping layer having an etch selectivity with respect to the buried oxide layer and the active layer pattern, over the active layer pattern; patterning the etch stopping layer to expose a channel region of the active layer pattern and the buried oxide layer; isotropically etching the buried oxide layer using the patterned etch stopping layer as an etch mask to form a cavity at a bottom of the channel region of the active layer pattern; and filling both the cavity and the space between the patterned etch stopping layer with a conductive material.