Patent ID: 8957708
Filing Date: 2015-02-17
Classification: G05F,H03K

Abstract:
1. An output buffer that is configured to output an output signal via an output line in response to an input signal, the output signal having a voltage value corresponding to a power-supply voltage, the output buffer comprising: a first MOS transistor that has a source terminal thereof applied with the power-supply voltage and a gate terminal thereof supplied with the input signal; a second MOS transistor that has a drain terminal thereof connected to the output line and a source terminal thereof connected to a drain terminal of the first MOS transistor; and a bias generation circuit that is configured to generate a bias voltage and to supply the bias voltage to a gate terminal of the second MOS transistor so as to turn on the second MOS transistor, wherein the bias generation circuit changes the voltage value of the bias voltage in accordance with a voltage value of the power-supply voltage to make a voltage between the gate and source terminals of the second MOS transistor constant.