Patent ID: 6448610
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A memory cell configuration, comprising:a first memory cell and a second memory cell adjacent said first memory cell, said first memory cell including: a substrate; a trench formed in said substrate, said trench having a bottom region, a middle region, a top region, and an inner wall; an insulating collar disposed on said inner wall in said middle region of said trench; a dielectric layer disposed at least in said bottom region of said trench; a conductive trench filling disposed to at least partially fill said bottom region of said trench and said middle region of said trench; an epitaxially grown layer disposed on said inner wall in said top region of said trench and disposed on said conductive trench filling; and a second dielectric layer disposed above said epitaxially grown layer in said top region of said trench, said second dielectric layer being annular and formed with an internal opening; an insulating trench formed in said substrate and surrounding said first memory cell and said second memory cell; and an active region formed between said first memory cell and said second memory cell, said active region being doped.