Patent ID: 6750129
Filing Date: 2004-06-15
Classification: H01L

Abstract:
A process for forming a fusible link in an integrated circuit comprising:(a) forming a second dielectric layer on a surface of an underlying metal interconnect and a first dielectric layer; (b) depositing an oxide layer at a thickness effective to prevent cracking of the oxide layer during a laser fuse process; (c) forming a via in the oxide layer and the second dielectric layer extending to the underlying metal interconnect; (d) filling the via with a conductive material; (e) forming a final metal layer; (f) patterning the final metal layer to form a fusible link electrically connected to the via; (g) forming a dielectric etch stop layer over the patterned final metal layer and the oxide layer; (h) depositing a passivation layer over the dielectric etch stop layer; and (i) removing the passivation layer from above at least a portion of the fusible link and a surrounding area.