Patent ID: 6169003
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method of forming a FET having a self-aligned pocket implant, comprising the steps of: forming a substrate having a substrate dielectric layer thereon and a first oxide layer over said substrate dielectric layer, said first oxide layer having an upper surface; forming a trench through said first oxide layer, said substrate dielectric layer, and partially through said substrate, said trench having a bottom and side walls; forming a second oxide layer along said bottom and said side walls of said trench within said substrate; selectively ion implanting a dopant into said substrate to form lightly doped layers adjacent said side walls of said trench within said substrate; ion implanting a self-aligned channel implant and a pocket implant at predetermined respective depths in said substrate below said trench bottom; forming side-wall spacers on said side walls of said trench; said side-wall spacers each having a top surface below said upper surface of said first oxide layer; forming a gate dielectric layer on said bottom of said trench between said side-wall spacers; forming a planarized gate electrode having an upper surface substantially level with said upper surface of said first oxide layer; removing said first oxide layer and said substrate dielectric layer; and ion implanting a dopant into said substrate to form heavily doped layers adjacent said side wall spacers.