Patent ID: 8125835
Filing Date: 2012-02-28
Classification: G11C

Abstract:
1. A memory architecture, comprising: an array of non-volatile memory cells; a pair of independently controlled voltage pumps coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitude of the positive and negative voltage biases is applied across a storage node of an accessed memory cell; a plurality of registers for storing programmable values used by the voltage pumps to independently control the magnitudes of the positive and negative voltage biases; a control mechanism coupled to the voltage pumps for controlling a duration of the positive and negative voltage biases; and a processor coupled for determining and setting the programmable values stored within the plurality of registers and for supplying a pump enable signal to the control mechanism, wherein the processor adjusts the duration of the pump enable signal based on a temperature measurement received from a temperature sensor.