Patent ID: 6826109
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A semiconductor integrated circuit device, comprising:a RAM macro having an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of said input circuit, said input circuit being activated on the basis of a first signal and said decoder circuit being activated on the basis of a second signal; and a clock input terminal and a gate circuit, wherein said first signal is a signal which is received synchronously with a clock signal supplied from said clock input terminal and controls said gate circuit, wherein said gate circuit uses a signal supplied from said clock input terminal as a signal for activating said input circuit, and wherein said RAM macro has a first operation mode in which a timing of receiving the input signal is set to a first timing and a second operation mode in which a timing of receiving the input signal is set to a second timing later than said first timing.