Patent ID: 7587190
Filing Date: 2009-09-08
Classification: G06F,Y02D

Abstract:
1. A low power frequency doubler circuit, the circuit comprising: a first clock generator, wherein the first clock generator includes an oscillator, implemented in a current steering topology which generates a first clock at a first frequency, and wherein the first clock generator includes a duty cycle correction circuit comprising: a charge pump, which receives a differential clock from the oscillator, and wherein the charge pump provides a differential charge output; a capacitor, one plate of the capacitor being electrically coupled to a positive end of the differential charge output and another plate of the capacitor being electrically coupled to the negative end of the differential charge output; a current generating circuit, which includes a differential input stage, the differential input stage being electrically coupled to a pair of current mirrors and wherein the current generator circuit receives the differential charge output and provides a positive delta current and a negative delta current to the oscillator; and a second clock generator, wherein the second clock generator generates a second clock, and wherein the second clock has a positive going clock edge for each edge of the first clock.