Patent ID: 6043535
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A transistor, comprising:a drain region;a source region opposite the drain region;a channel region in a first substrate layer extending between the source region and the drain region;a front gate comprising a first gate layer disposed outwardly from the first substrate layer and a second gate layer disposed outwardly from the first gate layer, the front gate separated from the channel region by a dielectric layer, said front gate having a pair of sidewall spacers on opposing ends thereof; anda self-aligned implant region disposed inwardly from the channel region, in approximate vertical alignment with the front gate and having a width approximately equal that of the front gate and the distance between said sidewall spacers;further comprising a buried dielectric layer disposed inwardly from the first substrate layer, wherein the self-aligned implant region comprises a back gate embedded within the buried dielectric layer inwardly from the channel region of the first substrate layer, in approximate vertical alignment with the front gate and having a width approximately equal that of the front gate.