Patent ID: 7994008
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A process for fabricating a planar transistor with two independent gates, comprising: forming a first layer of a semiconductor material on a second layer that is selectively etchable with respect to said first layer of semiconductor material; forming a third layer that is selectively etchable with respect to said material on said first layer of semiconductor material; selectively removing the selectively etchable material of the second and third layers; depositing a conducting material where the selectively etchable material has been removed to form first and second electrically independent gates for a single planar transistor device; forming a semiconductor channel for the single planar transistor device lying between the first and second electrically independent gates and comprising the first layer of the semiconductor material; and forming a dielectric zone lying between the first and second electrically independent gates and comprising an oxide of the semiconductor material.