Patent ID: 6630859
Filing Date: 2003-10-07
Classification: G05F

Abstract:
A low voltage supply band gap circuit, which uses NMOS and PMOS device bias, comprising:a first PN diode whose N side is connected to ground and whose P side is connected to the gate of an N-channel MOSFET which forms a plus input of a differential voltage comparator, a second PN diode whose N side is connected to ground and whose P side is connected to one node of a first resistor, said first resistor whose other node is connected to the gate of another N-channel MOSFET which forms a minus input of the differential voltage comparator, a bias NMOS FET whose drain is connected in common to the sources of both said NMOS FET and said another NMOS FET of said differential voltage comparator, a second resistor which is connected to an output of said differential voltage comparator and to the plus input of said differential voltage comparator, a third resistor which is connected to the output of said differential voltage comparator and to the minus input of said differential voltage comparator, a first PMOS FET whose drain is connected to said second resistor and whose gate is connected to ground and whose source is connected to a voltage supply, a second PMOS FET whose drain is connected to said second resistor and whose gate is connected to the drain of said NMOS FET and whose source is connected to the voltage supply, a third PMOS FET whose drain is connected to the drain of said NMOS FET and whose gate is connected to the drain of said another NMOS FET and whose source is connected to the voltage supply, a fourth PMOS FET whose gate and drain are connected to the drain of said another NMOS FET and whose source is connected to the voltage supply.