Patent ID: 6159661
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A dual damascene process comprising steps of:providing a semiconductor substrate that has a conductive layer already formed thereon;forming a first dielectric layer over the conductive layer and the substrate;forming a first mask layer on the first dielectric layer;forming a first cap layer on the first mask layer;patterning the first cap layer by photolithography and etching so as to form a first opening therein above the first conductive layer;removing a photoresist layer using an oxygen plasma;etching the first mask layer using the first cap layer as a mask to expose a portion of the first dielectric layer;forming a second dielectric layer over the first dielectric layer so that the first dielectric layer and the second dielectric layer are connected together through at least the exposes portion of the first dielectric layer;forming a second mask layer on the second dielectric layer;forming a second cap layer on the second mask layer;patterning the second cap layer by photolithography and etching to form a second opening exposing a portion of the second mask layer;etching the second mask layer using the second cap layer as a mask, and then etching the second dielectric layer additionally using the second mask layer as a mask to form a metal wiring opening that exposes a portion of the first dielectric layer and the first opening of the first cap layer;removing a photoresist layer using an oxygen plasma;etching the first dielectric layer and forming a via opening in the first dielectric layer that exposes the conductive layer, wherein the first cap layer and the first mask layer cooperate to serve as an etching mask for etching the first dielectric layer; andforming an interconnecting layer over the second dielectric layer and also filling the metal wiring opening and the via opening, so that the conductive layer is electrically coupled to the interconnecting layer.