Patent ID: 8327180
Filing Date: 2012-12-04
Classification: G06F

Abstract:
1. A data processing device formed as a semiconductor integrated circuit to be coupled to an external memory device for performing data transmission and reception, said data processing device comprising: a central processing unit operated at a first voltage; a clock pulse generation circuit capable of generating different clock pulse signals; and an interface unit for data transmission and reception to and from the external memory device, wherein said interface unit includes: an external clock output terminal for outputting a clock signal derived from a clock pulse signal generated by the clock pulse generation circuit; an output driver for driving said external clock output terminal to output said clock signal; a load circuit capable of imparting, to the clock signal extracted from a position in a stage previous to said output driver in a clock signal path, a variable delay in accordance with a delay resulting from an external load coupled to said external clock output terminal; both said output driver and said load circuit operating at a second voltage different from said first voltage; a plurality of external data input terminals for receiving data from the external memory device; and a plurality of latch circuits, operated at said first voltage, for latching data received by said plurality of external data input terminals, wherein said latch circuits latch data based on the clock signal as delayed by said load circuit.