Patent ID: 6835595
Filing Date: 2004-12-28
Classification: H01L

Abstract:
A semiconductor package, comprising:an insulating layer formed on a wafer that is provided with an electrode; an opening portion made in a region conformable to said electrode in said insulating layer; a rerouting layer connected to said electrode through said opening portion; a sealing resin layer which seals said wafer, said insulating layer, and said rerouting layer; and a post penetrating through said sealing resin layer, a solder bump being formed on an upper surface of said post; wherein said post comprises: a resin projection portion formed on said insulating layer; and a conductive layer that coats at least an upper surface of said resin projection portion and is connected to said rerouting layer and said solder bump; wherein a boundary between said post and said sealing resin layer is present outside said upper surface of said post as is viewed in plan; and wherein an inner surface of said opening portion made in said sealing resin layer is inclined inwards to form a groove surrounding a periphery of said upper surface of said post, and said boundary is divided by said groove.