Patent ID: 7703055
Filing Date: 2010-04-20
Classification: G06F,Y02P

Abstract:
1. A method of enhancing yield of semiconductor integrated circuit devices by implementing a system, the method comprising: determining a plurality of experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, the hole being polygonal in structure, and storing the plurality of experimental values in a first storage unit in the system; forming a plurality of test patterns representing each of the experimental values on a wafer; calculating experimental value-based systematic fault rates from the plurality of test patterns, and storing the experimental value-based systematic fault rates in a second storage unit in the system; converting each of the experimental value-based systematic fault rates of the hole into experimental value-based systematic fault rates per unit hole length using a length of sides of the hole, the length of sides of the hole being a sum of lengths of all sides of the hole, of each of the test patterns by a conversion unit in the system; calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values in a desired layout by a first calculation unit in the system; and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of a side of the hole calculated for the each of experimental values in the desired layout by a second calculation unit in the system.