Patent ID: 8679924
Filing Date: 2014-03-25
Classification: H01L

Abstract:
1. A method, comprising: forming a first mask layer above a semiconductor layer of a semiconductor device, said first mask layer comprising a gate opening that defines a lateral size and position of a gate electrode; forming a second mask layer in said gate opening, said second mask layer comprising a plurality of mask features defining a lateral size and position of a plurality of fins to be formed in said semiconductor layer; performing an etch process using said first and second mask layers to form said fins in a portion of said semiconductor layer and to define a space between said fins in said semiconductor layer, said space having sidewalls; removing said second mask layer; after removing said second mask layer, forming a dielectric material in said gate opening so as to adjust an electrically effective height of said plurality of fins by forming said dielectric material above said first mask layer and within said gate opening and removing a first excess portion of said dielectric material by using said first mask layer as a stop material, wherein removing the first excess portion of said dielectric material comprises performing a chemical mechanical planarization (CMP) process and using said first mask layer as a CMP stop layer; performing a single process operation to form a gate insulation layer on said fins and on said sidewalls of said space; and forming a gate electrode in said gate opening above said gate insulation layer.