Patent ID: 6525987
Filing Date: 2003-02-25
Classification: G11C

Abstract:
A memory for storing and retrieving data values, each data value being associated with a row address, said memory comprising:C bit lines, where C>1; R row lines, where R>1; an array of memory storage cells organized as R rows and C columns, there being one such column associated with each bit line and one such row associated with each row line, each memory storage cell storing a data value and having circuitry for coupling that data value to said bit line associated with said column in which said memory cell is located, said value being coupled in response to a row control signal on said row line associated with said row in which said memory cell is located; a row select circuit for generating said row control signal on one of said row lines in response to one of said row addresses being coupled to said row select circuit, said row select circuit comprising a memory for storing a mapping of said row addresses to said row lines, said mapping determining which of said row lines is selected for each possible value of said row address; and wherein said R row lines are divided into Nr normal row lines and Nrs spare row lines, Nr and Nrs being greater than 0, and wherein said row select circuit comprises: a first decoding circuit for generating one of said row select signals on one of said Nr normal row lines in response to said row address being coupled thereto, said first decoding circuit further comprising an inhibit circuit for preventing that row select signal from being applied to that normal row line; and a second decoding circuit for storing Nrs entries, each entry having space for storing a first value specifying one of said row addresses and a second value specifying one of said Nrs spare row lines, said second decoding circuit determining if one of said entries includes a first value that matches said row address, said second decoding circuit causing said inhibit circuit in said first decoding circuit to prevent the application of said row select signal and said second decoding circuit generating one of said row select signals on said spare row line specified by said second value in that entry if such a match is determined.