Patent ID: 7624138
Filing Date: 2009-11-24
Classification: G06F

Abstract:
1. An apparatus comprising: a first circuit to receive a first packed data comprising at least four byte data elements a second circuit to receive a second packed data comprising at least four byte data elements; a decoder to decode a plurality of instructions including a first instruction and a second instruction, the first instruction comprising a first source field indicating a first location to access said first packed data, and a second source field indicating a second location to access said second packed data; a multiply-adder circuit, enabled by the decoded first instruction, to multiply each of a first pair of byte data elements of the first packed data with respective byte data elements of the second packed data and to generate a first 16-bit result representing a first sum of products of the first pair of multiplications, and to multiply each of a second pair of byte data elements of the first packed data with respective byte data elements of the second packed data and to generate a second 16-bit result representing a second sum of products of the second pair of multiplications; a third circuit to store a third packed data comprising at least said first and second 16-bit results in response to the first instruction; an adder circuit, enabled by the decoded second instruction, to add said first and second 16-bit results of the third packed data to generate a third 16-bit result representing a third sum of products of the first and second pairs of multiplications; and a fourth circuit to store a fourth packed data comprising at least said third 16-bit result in response to the second instruction.