Patent ID: 6153471
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method of fabricating a flash memory, comprising:providing a substrate, wherein a first oxide layer is formed and a first masking layer is patterned on the first oxide layer;with the first masking layer serving as a mask, forming a plurality of strip-like trench isolation structures in the substrate;forming a plurality of strip-like openings in the substrate, with orientation of the openings approximately perpendicular to the trench isolation structures, wherein each of the openings includes a first portion that crosses the masking layer and exposes the substrate, and a second portion that crosses the strip-like trench isolation structures and does not expose the substrate;forming a plurality of spacers on sidewalls of the openings, wherein the spacers do not completely cover the sidewalls of the openings so that tops of the spacers within the first portion of the opening are isolated by an interface between the substrate and the first oxide layer with a distance;filling the openings with a plurality of doped first conducting layers wherein there is a dopant in the doped first conducting layers;with the spacers serving as masks, driving the dopant from the doped first conducting layers into the substrate through the interface to form a plurality of source/drain regions;removing the first masking layer and the first oxide layer until the substrate is exposed;forming a tunneling oxide layer on the substrate, the source/drain regions, and the first conducting layers;forming a plurality of patterned strip-like second conducting layers on the tunneling oxide layer, wherein the second conducting layers are approximately aligned with the doped first conducting layers and at least correspond to the source/drain regions, respectively;forming a dielectric layer at least on exposed surfaces of the second conducting layers;forming a third conducting layer over the substrate; andpatterning the third conducting layer to form a plurality of strip-like control gates so that an orientation of the control gates is approximately perpendicular to the doped first conducting layers, and continually defining the dielectric layer and the second conducting layers to form a plurality of floating gates.