Patent ID: 9202551
Filing Date: 2015-12-01
Classification: G06F,G11C,Y02D

Abstract:
1. A stacked memory device comprising: a plurality of memory strata, each memory stratum of the plurality of memory strata including a plurality of tiles of memory, the stacked memory device including a plurality of channels, wherein each channel of the plurality of channels includes a column of tiles addressable by row and column; and a system element coupled with the memory strata, the system element including a memory controller for control of the memory strata; wherein each channel of the stacked memory device includes: wherein each instance of the logic being operable to establish one of the following bus modes for the respective channel: wherein, for a channel that is in the first bus mode, a first set of bits of a received command, the first set of bits being received on a subset of the first set of pins of the command bus of the channel, is used to identify the type of command, and interpreting a command in the first bus mode includes: