Patent ID: 9058878
Filing Date: 2015-06-16
Classification: G11C

Abstract:
1. A read method of a semiconductor memory device, comprising: performing a first read operation on target cells by using a first read voltage; performing a first error correction operation based on read data of the first read operation; determining whether the first error correction operation is feasible or unfeasible; terminating the first read operation on the target cells when the first error correction is feasible; performing a second read operation on first cells adjacent to the target cells along a first direction by using voltages to classify the first cells into an erase state, a first program state, a second program state or a third program state when the first error correction is unfeasible; setting the first read voltage to a second read voltage according to a combination of the first cells as a result of the second read operation; performing a third read operation on the target cells by using the second read voltage; performing a second error correction operation based on read data of the third read operation; determining whether the second error correction operation is feasible or unfeasible; terminating the third read operation on the target cells when the second error correction is feasible; and treating the target cells as a fail cell when the second error correction is unfeasible.