Patent ID: 8325127
Filing Date: 2012-12-04
Classification: G09G,G11C

Abstract:
1. A shift register, comprising a plurality of shift register stages, {S n }, n=1, 2, . . . , N, N being a positive integer, electrically coupled to each other in series, each stage S n comprising: (a) a stage shift circuit having a first input for receiving a first control signal, HC (b) a de-multiplexing circuit comprising a first switch circuit and a second switch circuit, wherein the first switch circuit has a first input for receiving a first clock signal CK wherein each of the first control signal HC n , the first clock signal CK 1 and the second clock signal CK 2 is characterized with a waveform alternating between a high voltage level and a low voltage level, wherein the high voltage levels of the first control signal HC n , the first clock signal CK 1 and the second clock signal CK 2 have widths, W H , W 1 and W 2 , respectively, satisfying the following relationship of: