Patent ID: 7657810
Filing Date: 2010-02-02
Classification: G01R

Abstract:
1. A test architecture within an integrated circuit comprising; parallel scan paths having scan inputs for receiving stimulus data and scan outputs for outputting response data, a test stimulus data register having a serial input, a serial output, and parallel outputs, a test command register having a serial input and at least one command output, a test response data register having parallel inputs and a serial output, a test controller having a scan clock input and a command input, a connection formed between the scan inputs of the parallel scan paths and the parallel outputs of the test stimulus data register, a connection formed between the scan outputs of the parallel scan paths and the parallel inputs of the test response data register, a connection formed between the serial output of the test stimulus data register and the serial input of the test command register, and; a connection formed between the command input of the test controller and the command output from the test command register.