Patent ID: 7544558
Filing Date: 2009-06-09
Classification: H01L

Abstract:
1. A method for integrating double diffused metal oxide semiconductor (DMOS) into sub-micron complementary metal oxide semiconductor (CMOS) process, comprising the following steps: burying buried layers of a required conductivity type into a semiconductor substrate, and forming tub and well structures needed in the succeeding steps, said well being formed in said tub; defining active regions, and performing a thermal oxidation process to form required field oxide layers at ends of said well structures; sequentially forming a first polysilicon layer and a silicon nitride layer, and patterning said first polysilicon layer and said silicon nitride layer to form a pattern required by DMOS bodies, and performing a body ion implant process and a drive-in process to form required DMOS bodies; utilizing a plasma enhanced chemical vapor deposition (PECVD) process to form a silicon oxide (SiO performing the standard CMOS process, and sequentially forming DMOS gates, drains and pad electrodes.