Patent ID: 8429634
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A semiconductor device comprising: an arithmetic processing circuit; a ROM; a RAM; and a memory control circuit, wherein the arithmetic processing circuit is configured to execute a program to generate processing data and then terminate the program, wherein the ROM is configured to store the program, the program having stack analysis means and optimization means, wherein the RAM comprises a plurality of memory blocks, a border being defined between adjacent ones of the memory blocks wherein the processing data is divided into a plurality of stacks to be stored in the RAM, wherein the stack analysis means analyzes the stacks to obtain an analysis result that identifies a status of use of the stacks, including operations writing to the stacks, operations reading from the stacks, identification of contiguous writing stacks that do not cross the border between adjacent memory blocks, and identification of contiguous writing stacks that do cross the border between adjacent memory blocks, and provides a stack pointer, wherein the optimization means reads the analysis result and performs optimization of the processing data by wherein the memory control circuit stores the optimized stacks in the memory blocks.