Patent ID: 6362497
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A semiconductor integrated circuit having a substrate and a logic circuit and a plurality of power source systems formed in the substrate, comprising:an I/O region partitioned into a plurality of partitioned I/O regions each having at least a part of one of the plurality of power source systems formed therein; a core area distinct from the I/O region and having the logic circuit formed therein; and an ESD/EOS protection circuit for each power source system, the ESD/EOS protection circuit having power source system protective elements, wherein at least some of the power source system protective elements of at least some of the ESD/EOS protection circuits are formed in the partitioned I/O region for the corresponding power source system, and at least some of the power source system protective elements of at least some of the ESD/EOS protection circuits are formed in the core area.