Patent ID: 7688668
Filing Date: 2010-03-30
Classification: G11C

Abstract:
1. A memory comprising an array of semiconductor memory storage cells, each cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; each of said two devices comprising a power source input, such that each device can be powered independently of the other; and said array further comprising power control circuitry for controlling power supplied to said two power source inputs of each of said cells, wherein each of said cells comprise two high voltage level power source inputs and a single low voltage level power source input, said power control circuitry is configured to independently control a high voltage level input to each of said two high voltage level power source inputs and to supply a low voltage input to said low voltage power source input, said power control circuitry, in response to powering up the memory, is configured to provide a high voltage level signal to one of said power source inputs of each of said cells before the other one of said power source inputs, such that each cell is initialized to store a predetermined known value dependent upon which power source input received said high voltage level first.