Patent ID: 6407945
Filing Date: 2002-06-18
Classification: G11C

Abstract:
A method for reading non-volatile semiconductor memory configurations, which comprises:determining a high threshold and a low threshold voltage based on a charge state of a floating gate for a transistor; applying a reverse bias between a bulk and a source of the transistor during reading; and shifting a threshold voltage by &ggr;({square root over (âˆ’VSB+2&phgr;f+L )}âˆ’{square root over (2&phgr;f+L )}) when the transistor is an NMOS transistor by applying the bias and shifting a threshold voltage by âˆ’&ggr;({square root over (VSBâˆ’2&phgr;f+L )}âˆ’{square root over (âˆ’2&phgr;f+L )}) when the transistor is a PMOS transistor by applying the bias, where &ggr; is the substrate control factor, &phgr;f is the Fermi voltage of the bulk, and VSB is the bias between the bulk and the source of the transistor.