Patent ID: 9019925
Filing Date: 2015-04-28
Classification: H04B,H04L,H04W

Abstract:
1. An integrated circuit, comprising: mapping circuitry including a block interleaver, which, in operation, said block interleaver has 4 columns where nulls, a number of which is a difference between a size of the block interleaver and a total number of the DVRBs, are inserted in a same row of second and fourth columns of the block interleaver, and the DVRB numbers are written row by row and read out column by column, and said mapping circuitry maps two of the DVRBs, the numbers of which are written in a same row of first and third columns of the block interleaver, to PRBs in a same frequency within a subframe, and maps two of the DVRBs, the numbers of which are written in a same row of the second and fourth columns of the block interleaver, to the PRBs in a same frequency within a subframe.