Patent ID: 8158482
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method of forming a transistor, comprising: introducing at least one dopant species into an active region so as to have a first lateral spatial relation with respect to an edge of a first exposed sidewall of a gate electrode at a drain side and having a second lateral spatial relation with respect to an edge of a second exposed sidewall of said gate electrode at a source side, said first and second lateral spatial relations differing from each other, wherein said first and second exposed sidewalls are substantially symmetric; after introducing said at least one dopant species into said active region, forming a first spacer element on said first exposed sidewall of said gate electrode at said drain side and forming a second spacer element on said second exposed sidewall of said gate electrode at said source side, said first and second spacer elements having a different width; and forming asymmetric drain and source regions on the basis of said first and second spacer elements.