Patent ID: 6301678
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of data input/output pins;a plurality of memory cells receiving/transmitting a signal from/to respective ones of said plurality of data input/output pins;a plurality of control pins receiving a signal for controlling an internal operation;test signal generation means for detecting a specific test mode in response to a signal received from said plurality of control pins and for generating a corresponding test signal; andtest means for testing an operation of said plurality of memory cells, based on said test signal and in response to a signal input from a specific data input/output pin among said plurality of data input/output pins, and for externally supplying a result of said test from said specific data input/output pin; whereinsaid specific data input/output pin is lined up with a line of said plurality of control pins.