Patent ID: 8200945
Filing Date: 2012-06-12
Classification: G06F

Abstract:
1. A microprocessor, comprising: a vector unit to execute a vector instruction, wherein the vector unit includes a vector register file having a primary vector register file and a secondary vector register file; a first data bus and a second data bus wherein the first and second data busses both couple the vector unit to a data memory; a first input multiplexer coupled to and capable of receiving inputs from both the first data bus and the second data bus and providing a single output to the primary vector register file, and a second input multiplexer, independent of the first input multiplexer, also coupled to and capable of receiving inputs from both the first data bus and the second data bus and providing a single output to the secondary vector register file; wherein the first data bus comprises a first portion of a data memory bus and the second data bus comprises a second, different portion of the data memory bus, and wherein the data memory bus has a width equal to at least a sum of the first portion and the second, different portion of the data memory bus; and wherein said first and second multiplexers enable the vector unit to replicate data on the first data bus in both the primary and secondary vector register files or replicate data on the second data bus in both the primary and secondary vector register files by each multiplexer selecting a same input from among the data on the first data bus and data on the second data bus as the output for that multiplexer.