Patent ID: 8384649
Filing Date: 2013-02-26
Classification: G09G,G11C

Abstract:
1. A gate drive device for a liquid crystal display, including multiple stages of shift register units and a plurality of clock signal lines, each of said plurality of clock signal lines being connected to the multiple stages of shift register units, to enable the multiple stages of shift register units to generate a gate drive signal, each stage of shift register unit including a signal output terminal, wherein a first discharge circuit modular is connected between the signal output terminal for the i-th stage of shift register unit and the signal output terminal for the (i+1)-th stage of shift register unit, said first discharge circuit modular is used for causing the charges of a high level signal outputted from the signal output terminal for the i-th stage of shift register unit to be discharged to the signal output terminal for the (i+1)-th stage of shift register unit, wherein 1≦i≦the number of the stages of shift register units−1; wherein the device further comprises a second discharge circuit modular, wherein a first clock signal line comprises a first clock signal primary line and a first clock signal secondary line, a second clock signal line comprises a the second clock signal primary line and a second clock signal secondary line; said first clock signal primary line and the first clock signal secondary line are connected in parallel; said second clock signal primary line and a second clock signal secondary line are connected in parallel; and wherein the second discharge circuit modular is connected between the first clock signal line and the second clock signal line, the second discharge circuit modular is used for causing the charges of a high level signal on the first clock signal primary line to be discharged to the second clock signal primary line, or for causing the charges of a high level signal in the second clock signal primary line to be discharged to the first clock signal primary line; and wherein the second discharge circuit modular comprises a third thin film transistor and a fourth thin film transistor; for each of the odd number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the third thin film transistor are connected to the first clock signal primary line, the drain of the fourth thin film transistor is connected to the source of the third thin film transistor, the source of the fourth thin film transistor is connected to the second clock signal primary line, the gate of the fourth thin film transistor is connected to the second clock signal secondary line, and the gate of the second thin film transistor is connected to the second clock signal secondary line; and for each of the even number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the third thin film transistor are connected to the second clock signal primary line, the drain of the fourth thin film transistor is connected to the source of the third thin film transistor, the source of the fourth thin film transistor is connected to the first clock signal primary line, the gate of the fourth thin film transistor is connected to the first clock signal secondary line, and the gate of the second thin film transistor is connected to the first clock signal secondary line.