Patent ID: 6480981
Filing Date: 2002-11-12
Classification: G01R

Abstract:
An output stage of a multi-stage algorithmic pattern generator, which is comprised of:multiple input registers which hold input addresses and input data words; a multiplexer means, having a plurality of parallel data inputs which concurrently receive said input addresses and input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams in response to said control signals by selectively passing bits from said input addresses and input data words thru said multiplexer means to output terminals on said multiplexer means; a partitioning circuit, which receives said serial bit streams from said output terminals on said multiplexer means, and which partitions each serial bit stream into a corresponding sequence of output words; and, a memory address generator which generates a sequence of memory addresses; and a memory which receives said sequence of memory addresses and in response sends said sequence of control signals from a memory output to said control inputs of said multiplexer means.