Patent ID: 8572534
Filing Date: 2013-10-29
Classification: G06F

Abstract:
1. A method for designing a digital circuit using a hardware description language (HDL), the method using a computer and comprising the steps of: specifying a module in a first clock domain, using the HDL, wherein the HDL is an HDL having Term Rewriting System (TRS) rules; specifying an interface to the module in a second clock domain, the first and second clock domains driven by clock signals that are of different clock families and driven by different oscillators; and detecting, by an HDL compiler, the specification of the interface in the second clock domain and automatically instantiating a synchronizer interconnecting the module in the first clock domain with the interface in the second clock domain, the HDL compiler is a Term Rewriting System Compiler (TRSC); specifying one or more TRS rules in the second clock domain to interchange signals with the interface, the one or more TRS rules each having a predicate and an action body; wherein the step of specifying an interface to the module in a second clock domain further comprises the step of: implementing a converter to convert an interface of the module in the first clock domain, to be the interface of the module in the second clock domain, wherein a name of the converter is overloaded to provide different functionality dependent upon parameters provided to the converter.