Patent ID: 8250309
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. A data processor comprising: a control register configured to store a cache control value; data accessing logic, responsive to a data access instruction and to said cache control value, configured to look for data to be accessed in a cache if said cache control value has a predetermined value and to not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value; a further cache control value, said data accessing logic, responsive to a data access instruction and to both said cache control value and said further cache control value, configured to look for data to be accessed in a cache if said cache control value has a predetermined value and said further cache control value does not have a second predetermined value and to not to look for said data to be accessed in said cache if either said cache control value does not have said predetermined value or said further cache control value has said second predetermined value, said data processor configured to set said further cache control value to have said second predetermined value in response to a detected predetermined state of said data processor and to re-evaluate said further cache control value in response to said data processor detecting said data processor leaving said predetermined state, said predetermined state comprising execution of a sequence of data access instructions accessing a memory region that is not cacheable.