Patent ID: 6338158
Filing Date: 2002-01-08
Classification: G06F

Abstract:
A hardware model of an integrated circuit for use in design validation of an integrated circuit wherein said integrated circuit includes a plurality of electrically interconnected and functionally interdependent standardized cell libraries, said libraries selectively including functional system blocks and application specific standard parts, said model comprising:a plurality of silicon building blocks, each of said silicon building blocks having selectively functional system blocks and application specific standard parts identical to a respective one of said standardized cell libraries such that the model exhibits the same functional performance as said integrated circuit, wherein said plurality of building blocks are each electrically isolated from one another and function independently of one another; a multiplexer circuit coupled to said plurality of silicon building blocks and to I/O pins of said integrated circuit; and a control circuit coupled to other I/O pins of said integrated circuit for controlling said multiplexer, whereby different ones of the silicon building blocks are exercised in concert with one another to perform design validation.