Patent ID: 7207022
Filing Date: 2007-04-17
Classification: G06F

Abstract:
1. A layout design method for semiconductor integrated circuits, comprising: generating a first pre-layout net list consisting of data from a first cell library including logic blocks having metal oxide semiconductor field-effect transistors (MOSFETs) with a first threshold voltage; replacing at least some of the logic blocks in the pre-layout net list with data from a second cell library including logic blocks having MOSFETs with a second threshold voltage, the second threshold voltage being higher than the first threshold voltage, thereby generating a second pre-layout net list; analyzing propagation delay times in the second pre-layout net list and detecting first timing errors; iteratively modifying the second pre-layout net list, giving priority to at least some paths on which the first timing errors were detected for use of cells in the first cell library, until the first timing errors are reduced below a predetermined threshold value; placing the cells included in the modified second pre-layout net list in appropriate positions to create a cell layout; routing wiring among the cells in the cell layout, thereby generating layout data; analyzing propagation delay times in the layout data and detecting second timing errors; and optimizing the layout data on paths on which the second timing errors were detected.