Patent ID: 6859850
Filing Date: 2005-02-22
Classification: H04N

Abstract:
1. A memory controller having a plurality of channels, the memory controller comprising: input circuitry for receiving data to be stored in the memory; storage means for storing the base and top addresses of a plurality of circular buffers in the memory to which the received data is to be stored, and for storing a write pointer for each buffer; addressing circuitry for generating the address of one of the plurality of circular buffers to which the received data is to be written in dependence on a stored base and top address and write pointer; and output circuitry for writing the data into one of the plurality of circular buffers at the generated address, wherein at least one of the channels of the memory controller is arranged to control the storage of data in one of the plurality of circular buffers, and at least one of the channels is arranged to retrieve data from only a respective buffer.