Patent ID: 6337581
Filing Date: 2002-01-08
Classification: H03K

Abstract:
A transmission circuit comprising:a driver circuit alternately controlled to a precharge period and an evaluation period according to a first control signal, said driver circuit precharging an output node to a first source potential during the precharge period and driving the output node to either one of the first source potential and a second source potential according to a potential at an input node during the evaluation period; a signal line coupled to the output node of said driver circuit so as to be driven by said driver circuit; and a receiving circuit having a first node and a second node, said receiving circuit being alternately controlled to the precharge period and the evaluation period according to a second control signal to precharge the first and second nodes to the first source potential together during the precharge period, and discharge the second node according to a potential at the first node and discharge the first node according to a potential on said signal line during the evaluation period, thereby making a distinction as to the potential on said signal line with the potential at the first node as a reference potential; wherein said receiving circuit includes, a first load provided between the first source potential and the first node and driven based on the second control signal; a second load provided between the first source potential and the second node and driven based on the second control signal; an activation circuit provided between a third node and the second source potential, for driving the third node to the second source potential during the evaluation period; a first feedback field effect transistor having a source-to-drain path inserted between the first node and a fourth node and a gate connected to the second node; a second feedback field effect transistor having a source-to-drain path inserted between the second node and a fifth node and a gate connected to the first node; an input field effect transistor having a source-to-drain path inserted between the third node and the fourth node and a gate to which said signal line is connected; and a reference field effect transistor having a source-to-drain path inserted between the third node and the fifth node and a gate connected to the first node.