Patent ID: 6598214
Filing Date: 2003-07-22
Classification: G06F

Abstract:
A method of designing a circuit comprising a plurality of transistors, wherein each transistor of the plurality of transistors comprises an active region, a gate, a first source/drain in the active region, a second source/drain in the active region, and at least one contact in each of the first source/drain and the second source/drain; the method comprising the steps of:specifying a first set of distances for each transistor in a first set of transistors in the plurality of transistors, wherein the first set of distances comprises a gate length, a gate width, and a distance representative of one or both of a first contact-to-edge distance and a first contact-to-gate distance; specifying a second set of distances for each transistor in a second set of transistors in the plurality of transistors, wherein the second set of distances comprises a gate length, a gate width, and a distance representative of one or both of a second contact-to-edge distance and a second contact-to-gate distance; wherein either or both the second contact-to-edge distance is greater than the first contact-to-edge distance and the second contact-to-gate distance is greater than the first contact-to-gate distance; and wherein, for each transistor in the second set of transistors, the step of specifying a second set of distances is responsive to a determination of a benefit from a larger drive current to be provided by the transistor in the second set of transistors.