Patent ID: 8667259
Filing Date: 2014-03-04
Classification: G06F,Y02D

Abstract:
1. A data processor, comprising; a cache unit having a plurality of cache memories; a branch prediction unit, when an instruction is a branch instruction, configured to perform a conditional branch prediction indicating whether a conditional branch of the branch instruction is taken or not taken and a cache WAY prediction indicating in which cache memory, from among the plurality of cache memories, data of the branch instruction is stored and to output a branch prediction data which is based on the conditional branch prediction and the cache WAY prediction; and a control unit configured to control an activation of each of the plurality of cache memories, wherein the branch prediction data has a plurality of states which transits between each other in response to a result of the conditional branch prediction and the cache WAY prediction, wherein the control unit is configured to control the activation of each of the plurality of cache memories based on a current state of the branch prediction data among the plurality of states.