Patent ID: 6617524
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A packaged integrated circuit comprising:a substrate having a top surface and an edge; an integrated circuit die mounted on the substrate; an encapsulant over the top surface of the substrate, wherein the encapsulant has a perimeter, wherein a first portion of the perimeter is a first distance away from the edge of the substrate; a first barrier trace on the top surface, closest to the first portion of the perimeter of the encapsulant, and substantially parallel to the first portion of the perimeter of the encapsulant, wherein a portion of the first barrier trace is a second distance away from the edge of the substrate and the second distance is less than or equal to the first distance; a first bond connection on the top surface and inside the perimeter; a second bond connection on the top surface and inside the perimeter; a first electrical trace on the substrate and electrically connected to the first bond connection; and a second electrical trace adjacent to the first electrical trace and electrically connected to the second bond, wherein a portion of the first barrier trace is between the first and second electrical traces.