Patent ID: 8339862
Filing Date: 2012-12-25
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; an n type well formed in the semiconductor substrate; a plurality of memory cells arranged in matrix, each of the memory cells having a first p type MIS transistor formed in the n type well and a second p type MIS transistor formed in the n type well, the first p type MIS transistor and the second MIS type transistor being connected in series, the second p type MIS transistor having a charge accumulation layer, a drain connected to the first p type MIS transistor and a source opposite to the drain; a plurality of bit lines arranged in parallel; a plurality of selection lines, each connected to a corresponding gate of the first p type MIS transistor, the plurality of selection lines arranged in parallel and perpendicular to the plurality of bit lines; a plurality of word lines, each connected to a corresponding gate of the second p type MIS transistor; and a programming circuit for programming a selected row of the plurality of memory cells, the programming circuit providing a first positive voltage (Vwell) to the n type well, providing a second positive voltage (Vcg) to a selected word line of the plurality of word lines, and providing a third positive voltage (Vsl) lower than the first positive voltage to the source of the second MIS type transistor, and providing a fourth voltage (Vbl) lower than the third positive voltage (Vsl) to the drain of the second MIS type transistor via the first p type MIS transistor.