Patent ID: 6072748
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A word line selection circuit for selecting a word line comprising:a first decoding circuit for receiving first address signals and for generating a first selection signal in response to the first address signals;a second decoding circuit for receiving second address signals and for generating a second selection signal in response to the second address signals, including a decoding portion and a buffer portion, the buffer portion being connected to the decoding portion, the decoding portion generating a decoding signal, the decoding signal being applied to the buffer portion, the second selection signal being generated from the buffer portion; andan N-channel MOS transistor having a gate for receiving the first selection signal, one end of a current path connected in such a manner as to receive the second selection signal, said N-channel MOS transistor transferring the second selection signal for selecting the word line in response to the first selection signal;wherein the word line is selected in response to the first selection signal from the first decoding circuit and the second selection signal from the buffer portion of the second decoding circuit.