Patent ID: 7953961
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequences of operations, based on one or more sequences of instructions, to an execution circuit of the processor, wherein the instruction processing circuit comprises: a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a sequence of operations of a first type; a cache circuit operable to: a sequencer circuit operable to select a next sequence of operations and to receive, from the cache circuit, a first indication of whether or not the next sequence of operations is held therein, and, if the first indication indicates that the next sequence of operations is not held therein to activate the decoder circuit to generate the next sequence of operations, wherein the sequencer circuit is further operable to determine whether or not to activate the cache circuit to cache at least a portion of the next sequence of operations from the decoder circuit; and an operations fetch circuit operable to convey the next sequence of operations to the execution circuit, and operable to receive a second indication, if any, that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, wherein the operations fetch circuit is operable to switch, based on the second indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.