Patent ID: 6173238
Filing Date: 2001-01-09
Classification: G01R,G11C

Abstract:
A memory testing apparatus provided with a failure analysis memory for storing failure data resulting from a test of a semiconductor memory under test, said failure analysis memory comprising a memory part comprising a plurality of memory elements to which failure data are distributed by an interleave operation and stored therein, each of said plurality of memory elements having a storage maintaining operation to be executed at regular time intervals, said failure analysis memory comprising:a clock generating part generating a clock for operating the memory elements of said memory part independent of a reference clock used in testing the semiconductor memory under test;means for generating a refresh request signal at regular time intervals in order to maintain the stored contents of the memory elements, said means for generating a refresh request signal being supplied with an operating clock from said clock generating part;an address selection part, supplied with the same address signal as that given to the semiconductor memory under test, taking out a row address signal and a column address signal from the supplied address signal corresponding to an arrangement of row and column addresses of each of said memory elements;synchronizing means, supplied with a row address signal and a column address signal selected by said address selection part and with a failure data from a logical comparator means, for changing them to a row address signal, a column address signal and a failure data all of which are in synchronism with a clock generated from said clock generating part;failure data compression means for compressing failure data occurring at the same address in close time to each other in row address signals, column address signals, and the failure data outputted from said synchronization means into one failure data; anda data distribution control part controlling the plurality of memory elements each storing failure data outputted from said failure data compression means to determine one of the memory elements in which a failure data is to be stored.