Patent ID: 7808852
Filing Date: 2010-10-05
Classification: G11C

Abstract:
1. A layout method of a semiconductor memory device including a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal, first and third prechargers configured to receive a first precharge voltage and precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation, and second and fourth prechargers configured to receive a second precharge voltage to precharge the data signals transmitted to the first and second pair of local input/output data lines to the second precharge voltage in response to the second precharge control signal during a precharge operation, the method comprising: sharing a first active area between the first precharger and the second precharger and sharing a second active area between the third precharger and the fourth precharger.