Patent ID: 7111256
Filing Date: 2006-09-19
Classification: G03F

Abstract:
1. A method for analyzing overlay error data obtained from an overlay target of a semiconductor component the method comprising: (a) providing an overlay error value, a systematic error metric, and a noise metric for the overlay target; and (b) determining a characteristic related to the overlay error value based on analysis of the systematic error metric and/or the noise metric, wherein the characteristic is selected from a group consisting of (i) a characteristic that defines whether the overlay error value is a flyer, (ii) a confidence level (iii) a bias value representing a difference between an DI (development inspection) overlay value and a FI (final inspection) overlay value, wherein the DI overlay value results from a target after a photoresist layer has been developed and prior to a process utilizing such developed photoresist layer and the FI overlay value results from the process utilizing the developed photoresist, and (iv) a characteristic that defines whether a process excursion has occurred.