Patent ID: 6052331
Filing Date: 2000-04-18
Classification: G11C

Abstract:
A synchronous semiconductor memory device operating in synchronization with an external clock signal, comprising:a memory array having a plurality of memory cells arranged in a matrix of rows and columns, said memory array being divided into a plurality of memory blocks;a plurality of memory selecting circuits provided corresponding to said plurality of memory blocks respectively, each for selecting a memory cell in a corresponding memory block independent from the other memory block in accordance with an address signal;a plurality of read circuits provided corresponding to said plurality of memory blocks respectively, for reading data stored in said selected memory cell; anda control circuit for controlling an operation of said synchronous semiconductor memory device in accordance with an external control signal, includinga timing control circuit provided common to said plurality of memory blocks, for delaying said external control signal for generating a timing control signal controlling operation timing of the selected memory block, anda plurality of block control circuits provided corresponding to said plurality of memory blocks respectively, each for controlling an operation of the corresponding memory block in accordance with said timing control signal.