Patent ID: 6368903
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of making an FET device comprising:providing a first dielectric layer; depositing a substrate layer on the dielectric layer; forming a body contact region of a first conductivity type in the substrate layer; forming FET source and drain regions of a second conductivity type in the substrate layer; forming a channel region of the first conductivity type in the substrate, the channel region abutting the body contact region and separating the FET source and drain regions along edges of the FET source and drain regions, the first conductivity type material in said body contact region being thinner than the first conductivity type material in the channel region; depositing a gate above the substrate layer over the channel region; and depositing a second dielectric layer on the body contact region, wherein the FET source and drain regions of the second conductivity type and the channel region of the first conductivity type directly abut the body contact region of the first conductivity type along only a first common border so that the first conductivity type of both the channel region and the body contact region is continuous along a portion of the only first common border.