Patent ID: 7944424
Filing Date: 2011-05-17
Classification: G02F,G09G

Abstract:
1. A pixel control device, being electrically connected to a sub-pixel, the pixel control device being configured to provide a first voltage level, a second voltage level, and a third voltage level to the sub-pixel, the pixel control device comprising: a first transistor, having a gate, a source and a drain; a second transistor, having a gate, a source and a drain; a third transistor, having a gate, a source and a drain; a first capacitor with fixed capacitance, directly coupled between the drain of the first transistor and the drain of the second transistor; a second capacitor with fixed capacitance, directly coupled between the drain of the second transistor and the drain of the third transistor; a scan line, coupled to the gate of the first transistor, the gate of the second transistor and the gate of the third transistor, and for controlling the first transistor, the second transistor, and the third transistor to be switched on; a first data line, coupled to the source of the first transistor and the source of the second transistor and for providing a first data-referenced voltage level to the first transistor and the second transistor when the first transistor and the second transistor are switched on; a second data line, coupled to the source of the third transistor and for providing a second data-referenced voltage level to the third transistor when the third transistor is switched on; a first energy storing device, being coupled to the drain of the first transistor, for providing the first voltage level in response to the first data-referenced voltage level when the first transistor is switched on; a second energy storing device, being coupled to the second terminal of the first capacitor and the drain of the second transistor, for providing the second voltage level in response to the first data-referenced voltage level when the first transistor and the second transistor are switched on; and a third energy storing device, comprising a seventh capacitor with variable capacitance and a eight capacitor with fixed capacitance, the seventh capacitor and the eight capacitor being coupled to the drain of the third transistor, for providing the third voltage level in response to the second data-referenced voltage level when the third transistor is switched on; wherein the first voltage level and the first data-referenced voltage level form a first ratio, the second voltage level and the first data-referenced voltage level form a second ratio, and the third voltage level and the second data-referenced voltage level form a third ratio.