Patent ID: 6022776
Filing Date: 2000-02-08
Classification: H01L

Abstract:
A method for forming a DRAM cell of a DRAM circuit, said DRAM circuit including a periphery region and a cell region, said DRAM cell being in said cell region and comprised of an access transistor and a capacitor, said access transistor having a gate, a source, and a drain, said periphery region including a plurality of gates, the method comprising the steps of:depositing a silicon oxynitride layer over said gates, said silicon oxynitride layer acting as a bottom anti-reflection coating and directly in contact with said gates;removing said silicon oxynitride layer that lies over said DRAM cell;forming a landing pad over said source and a bitline pad over said drain; forming a first oxide layer over said landing pad and said bitline pad;forming a capacitor over said landing pad;forming a second oxide layer over said capacitor; and forming metal contacts to at least on of said plurality of gates in said periphery region using said silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.