Patent ID: 7305567
Filing Date: 2007-12-04
Classification: H04L

Abstract:
1. An apparatus comprising: a microcontroller unit to store an instruction into an execution queue; an execution queue unit to generate a widely decoded functional execution instruction to control a datapath pipeline by execution of the instruction stored in the execution queue; and a plurality of functional units, each of the plurality of functional units coupled with the datapath pipeline, each of the plurality of functional units having a different function and each of the functional units to execute the widely decoded functional execution instruction asynchronous to generation of the widely decoded functional execution instruction by the execution queue unit, wherein one of the plurality of the functional units is to execute a data ciphering operation based on the execution of the widely decoded functional execution instruction, wherein the plurality of functional units include an advanced encryption standard unit, a data encryption standard unit and a hash unit, and wherein the datapath includes a first stage with the plurality of functional units and a second stage with operational logic to process the output of the first stage.