Patent ID: 6611270
Filing Date: 2003-08-26
Classification: G09G

Abstract:
A microcomputer having an on-screen display, comprising:a first register for registering an access mode value indicating a first access mode corresponding to a first bus cycle or a second access mode corresponding to a second bus cycle longer than the first bus cycle; a first storing circuit for storing first data; a display data storing circuit for storing display data; a first control unit for outputting address data of the first storing circuit or address data of the display data storing circuit to access the first storing circuit or the display data storing circuit and to process the first data or the display data; an address decoder for decoding the address data output by the first control unit to identify whether the address data indicates the first storing circuit or the display data storing circuit, outputting a first address value when the address data indicates the first storing circuit, and outputting a second address value when the address data indicates the display data storing circuit; a first logical circuit, connected with the first register and the address decoder, for producing a first logical value indicating the second access mode when the first register registers the access mode value indicating the first access mode and the second address value indicating the display data storing circuit is output by the address decoder; a picture display logical circuit for accessing the display data storing circuit to display the display data stored in the display data storing circuit on the on-screen display; and a bus interface unit for receiving the first logical value from the first logical circuit, setting the access mode of the first control unit to the second access mode according to the first logical value to make the first control unit access the display data storing circuit in a first half of the second bus cycle and to make the picture display logical circuit access the display data storing circuit in a second half of the second bus cycle.