Patent ID: 7335906
Filing Date: 2008-02-26
Classification: G11C,H01L

Abstract:
1. A phase change memory device comprising: a semiconductor substrate; a plurality of cell arrays stacked above said semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of said memory cells, bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of said matrix and word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of said matrix; a read/write circuit formed on said semiconductor substrate as underlying said cell arrays for reading and writing data of said cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of said cell arrays in said first direction to connect said bit lines of the respective cell arrays to said read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define said cell layout region in said second direction to connect said word lines of the respective cell arrays to said read/write circuit.