Patent ID: 7477712
Filing Date: 2009-01-13
Classification: G06F,H04L

Abstract:
1. A system for synchronous data transfer between clock domains, comprising: a data path adaptable to align a control signal from a first clock domain to a second clock domain; a count calibrator operable to measure delay between the first and second clock domains; a controller operatively associated with the data path and the count calibrator, the controller responsive to operating parameters to configure the adaptable data path to align the control signal received on a logical clock cycle of the first clock domain to a logical clock cycle of the second clock domain based on the delay measured by the count calibrator; and wherein the adaptable data path is configured with a delay equal to M minus N where M is a maximum expected separation (M) of logical clock cycles between the first and second clock domains and N is a predetermined number of clock cycles needed to synchronously transfer data between the first and second clock domains.