Patent ID: 6710402
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A vertical MOS transistor comprising:a semiconductor substrate having a first conductivity type; an epitaxial growth layer having the first conductivity type formed on the semiconductor substrate; a body region having a second conductivity type formed on the epitaxial growth layer; a trench having a sidewall extending through the body region of the second conductivity type and having a bottom surface disposed inside of the epitaxial growth layer of the first conductivity type; a gate insulating film formed of a first gate material and extending along an upper surface of the body region of the second conductivity type and the sidewall and the bottom surface of the trench and having a U-shaped form so as to define a U-shaped void within the trench; a polycrystalline silicon gate partially filling the internal void of the gate insulating film; a second gate material comprised of one of a silicon oxide film and a silicon nitride film filling a remaining portion of the internal void not filled by the polycrystalline silicon gate so as to be in contact with the polycrystalline silicon gate and having a sidewall and a bottom surface that are surrounded by the gate insulating film and the polycrystalline silicon gate; a source region of the first conductivity type formed in the upper surface of the body region of the second conductivity type and around the trench so as to be in contact with the gate insulating film; a gate electrode connected to the polycrystalline silicon gate and the second gate material; a source electrode connected to the source region; and a drain electrode connected to the semiconductor substrate.