Patent ID: 8045372
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A flash memory device, comprising: a plurality of memory cell blocks, each memory cell block being associated with select lines, pass word lines, and word lines, at least one pass word line being provided between one select line and one word line, the pass word line having a structure in the same manner as the word line; an operating voltage generator to output operating voltages to global select lines, global word lines and global pass word lines; a block switching unit to connect the global word lines to the word lines and the global select lines to the select lines in response to a block select signal; and a voltage supply circuit configured to supply the select lines and the pass word lines of an unselected memory cell block with a ground voltage in response to a block select inverse signal, wherein word lines of the unselected memory cell block are set to a floating state when the ground voltage is supplied to the select lines and the pass word lines of the unselected memory cell block.