Patent ID: 6849468
Filing Date: 2005-02-01
Classification: H01L

Abstract:
1. A method for manufacturing a ferroelectric random access memory (FeRAM) capacitor, the method comprising the steps of: a) preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first interlayer dielectric (ILD), a second ILD and a storage node; b) forming a first bottom electrode on the active matrix; c) forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; d) planarizing the third ILD until a top face of the first bottom electrode is exposed; e) forming a second bottom electrode on a top face of the first bottom electrode; f) carrying out a first annealing process for deforming a surface of the second bottom electrode in order to uniformly grow up grains in a dielectric layer along the surface of the second bottom electrode; g) forming the dielectric layer on exposed surfaces of the first bottom electrode, the second bottom electrode and the third ILD; h) carrying out a second annealing process; and i) forming a top electrode on the dielectric layer.