Patent ID: 6137374
Filing Date: 2000-10-24
Classification: H03K

Abstract:
A low power clock oscillator circuit for reducing circuit power consumption comprising;a resonant network configured as a Colpitts oscillator for providing an input waveform of a specified frequency to the oscillator circuit;a first amplifier including an input coupled to the resonant network and an output coupled to the resonant network through a load resistor for producing a sinusoidal output having an oscillating frequency substantially equal to the input waveform frequency, said first amplifier having a supply terminal for receiving a supply voltage;a bias resistor coupled between the first amplifier input and the first amplifier output;a second amplifier having an enable input and a signal input connected to the output of the first amplifier for converting the first amplifier sinusoidal output to a continuous pulse output, said second amplifier having a single supply terminal for receiving a supply voltage, wherein the second amplifier supply voltage is greater than the supply voltage of the first amplifier;whereby powering the first amplifier from the lower supply voltage causes a reduction in supply current thereby reducing the power consumption of the clock oscillator circuit.