Patent ID: 6242933
Filing Date: 2001-06-05
Classification: G01R,Y10T

Abstract:
A method of interfacing between a test board and a probe handler for high-speed semiconductor device testing, comprising:a probe socket, said probe socket comprising a socket base and a socket top cover, said socket base comprising means for socket base alignment, said socket base further comprising an opening for insertion of said socket top cover, said socket base further comprising a multiplicity of openings with a multiplicity of pogo pins to contact a Device Under Test, said opening for insertion of said socket top cover aligning with said socket top cover thereby allowing alignment, insertion and attachment of said top cover to said socket base, said socket top cover comprising means for aligning and attaching said socket top cover to said socket base plate, said socket top cover further comprising a multiplicity of openings for pogo pins;a device package strip, at least one semiconductor device being mounted on said device package strip;a strip carrier frame, at least one device package strip being mounted on said strip carrier frame; anda means for mounting said device package carrier strip to a strip carrier frame.