Patent ID: 6512689
Filing Date: 2003-01-28
Classification: G11C

Abstract:
Magnetoresistive random access memory architecture free of isolation devices comprising:a plurality of data columns, each including an associated column bitline, and a plurality of spaced apart digitlines; the plurality of data columns each including a first plurality of non-volatile magnetoresistive elements each programmable to one of an Rmax and an Rmin state connected to have information stored therein, the first plurality of non-volatile magnetoresistive elements in each of the data columns each being connected at one end to the associated column bitline and at another end, one each, to a digitline of the plurality of digit lines; a reference column including a second plurality of non-volatile magnetoresistive elements positioned adjacent to the data column, the reference column having an associated reference bitline coupled to the second plurality of non-volatile magnetoresistive elements; a plurality of data current conveyor circuits, one each coupled to each of the associated column bitlines, each data current conveyor circuit having an output terminal; a reference current conveyor circuit coupled to the reference bitline and having an output terminal; a differential amplifier having first and second inputs; and selection circuitry coupling the output terminal of a selected one of the plurality of data current conveyor circuits to the first input of the differential amplifier and the output terminal of the reference current conveyor circuit to the second input of the differential amplifier for differentially comparing a data voltage generated from the selected one of the plurality of data current conveyor circuits to a reference voltage generated from the reference current conveyor circuit and providing a data output signal.