Patent ID: 6927135
Filing Date: 2005-08-09
Classification: H01L,Y10S

Abstract:
1. A method of fabricating multiple sets of field effect transistors, comprising: forming an etch stop layer over an insulative capping layer over a conductive gate layer over a substrate, the etch stop layer and the insulative capping layer being of different compositions; patterning and etching the etch stop layer, the insulative capping layer, and the conductive gate layer to form a first set of conductive gate constructions over the substrate; forming and planarizing a dielectric material over the first set of gate constructions; after forming and planarizing the dielectric material, patterning and etching the insulative capping layer and the conductive gate layer to form a second set of conductive gate constructions over the substrate; and wherein the patterning and etching the insulative capping layer and the conductive gate layer to form the second set of conductive gate constructions also patterns and etches remnant of the etch stop layer to constitute a portion of the second set of conductive gate constructions.