Patent ID: 7112532
Filing Date: 2006-09-26
Classification: H01L

Abstract:
1. A method for forming a dual damascene structure, comprising: providing a silicon substrate containing one or more electronic devices; forming a first dielectric layer of a first thickness over said silicon substrate; forming a first etch stop layer over said first dielectric layer; forming a second dielectric layer of a second thickness over said first dielectric layer; forming an anti-reflective coating layer over said second dielectric layer prior to etching of a first trench; etching said first trench in said second dielectric layer; simultaneously etching a second trench to a first depth in said second dielectric layer and etching said first trench in said first dielectric layer wherein the first depth is approximately equal to the second thickness; removing the first etch stop layer at a bottom portion of the first trench; forming a liner film in the first trench and the second trench; and forming a contiguous copper layer in the first trench and the second trench.