Patent ID: 7034592
Filing Date: 2006-04-25
Classification: H03K,H03L

Abstract:
1. A clock control circuit comprising: a multi-phase multiplication clock generating circuit receiving an input clock to generate first to nth clocks of respective different phases (termed multi-phase multiplication clocks) obtained by frequency multiplying the input clock; a switch for selecting two sets each of two neighboring ones of said first to nth clocks output from said multi-phase multiplication clock generating circuit; a first interpolator receiving the first set of two clocks output from said switch to generate a first signal, a propagation delay of said first signal corresponding to division of timing difference of said first set of two clocks; a second interpolator receiving the second set of two clocks output from said switch to generate a second signal, a propagation delay of said second signal corresponding to division of timing difference of said second set of two clocks; a third interpolator receiving said first and second signals of said first and second interpolators to generate a third signal, a propagation delay of said third signal corresponding to division of timing difference of said first and second signals; a ratio of the internal division of the timing difference of at least one of said first to third interpolators being variably set; and a control circuit for outputting a switching signal for said switch and a control signal for variably setting the ratio of the internal division of the timing difference of said interpolators.