Patent ID: 7471588
Filing Date: 2008-12-30
Classification: G11C

Abstract:
1. A dual port memory array circuit, comprising: a dual port memory array having memory cells that are accessed using bit lines and word lines; address circuitry that is connected to the dual port memory array using the word lines; bit line read-write circuitry that is connected to the dual port memory array using the bit lines; and bit line voltage clamping circuitry in the bit line read-write circuitry that limits how much signals on the bit lines drop during read operations, wherein the bit line voltage clamping circuitry comprises first transistors and second transistors, wherein each one of the first and second transistors has a source and a drain, wherein the bit line voltage clamping circuitry is connected between the bit lines and a power supply voltage source, and wherein the source and drain of one of the first transistors and the source and drain of one of the second transistors are connected in series between each of the bit lines and the power supply voltage source.