Patent ID: 6531733
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A structure of a flash memory cell, comprising:a substrate, wherein the substrate comprises: an isolation region; a channel region; a trench located on the isolation region, wherein the size of the isolation region and the size of the trench are both larger than the size of the channel region, and the channel region is all covered by both the isolation region and the trench; and a source and a drain, wherein the source and the drain are located besides two sides of the channel region respectively; a crystallized semiconductor film located on a portion of the trench, wherein the crystallized semiconductor film is connected with the source and the drain respectively; an oxide layer; a floating gate; a dielectric layer; and a control gate, wherein the crystallized semiconductor film is surrounded and encompassed by a portion of the oxide layer, a portion of the floating gate, a portion of the dielectric layer, and the control gate in sequence, and the bottom and the sidewall of the trench are covered by an other portion of the oxide layer, an other portion of the floating gate, an other portion of the dielectric layer, and the control gate in sequence.