Patent ID: 9191187
Filing Date: 2015-11-17
Classification: H03L,H04L

Abstract:
1. A reception circuit comprising: a first clock recovery circuit that detects an edge from a data signal superimposed with a clock and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected; a phase adjustment circuit that adjusts a phase of the data signal so as to coincide with a phase of the recovered clock; a second clock recovery circuit that, based on a phase difference between the data signal whose phase has been adjusted by the phase adjustment circuit and a feedback clock from the voltage controlled oscillator, adjusts an oscillation frequency of the recovered clock by means of the voltage controlled oscillator; and a determination circuit that determines a value of the data signal, whose phase has been adjusted by the phase adjustment circuit, at a timing when a signal level of the recovered clock transitions; wherein the phase adjustment circuit adjusts the phase of the data signal by delaying the data signal based on a delay amount in the first clock recovery circuit.