Patent ID: 7999382
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A semiconductor device fabrication method comprising: forming a first interlayer insulating film on a semiconductor substrate; forming a second interlayer insulating film including a plurality of grooves, on the first interlayer film; forming a first barrier metal on inner surfaces of the grooves; forming a first interconnect part and a first bonding electrode part, including a copper film, on the first barrier metal; forming a second barrier metal on the first interconnect part and the first bonding electrode part; forming a metal film on the first interconnect part via the second barrier metal, and patterning the metal film and forming a second interconnect part on the first interconnect part via the second barrier metal; depositing a metal film on the first bonding electrode part via the second barrier metal, and patterning the metal film and forming a second bonding electrode part on the first bonding electrode part via the second barrier metal; and depositing a third interlayer insulating film on the entirety of the semiconductor substrate, and forming an opening on the third interlayer insulating film that exposes the surface of the second bonding electrode part, wherein the first interconnect part and the first bonding electrode are completely surrounded on sides and bottom by the first barrier metal and the second barrier metal covers the top, and the first interconnect part and the second interconnect part are formed as an interconnect part in a top interconnect layer.