Patent ID: 6440827
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A method for fabricating a semiconductor component and the method being adapted from a further method for fabricating at least two MOS transistor types, which comprises the steps of:providing a semiconductor substrate having at least one first zone of a second conductivity type for transistors of a first transistor type and a second zone of a first conductivity type for transistors of a second transistor type; applying a first insulating layer to the semiconductor substrate; introducing a first dopant of the first conductivity type into the first zone in a first region of a crossover point between a yet to be formed first conductive connection running in the semiconductor substrate and a yet to be formed second conductive connection running on the semiconductor substrate; introducing a second dopant of the second conductivity type into the second zone in a second region of a crossover point between the yet to be formed first conductive connection and a yet to be formed third conductive connection running on the semiconductor substrate; applying a conductive layer to the first insulating layer from which the second conductive connection and the third conductive connection are to be formed from; applying a first mask using a phototechnology process, the first mask covering the second zone substantailly completely and, in the first zone covering only gate tracks of the transistors of the first transistor type that are to be produced and also an area of the conductive layer forming the second conductive connection running on the semiconductor substrate; using the first mask for one of fully removing first areas of the conductive layer and removing only some of the conductive layer in the first areas forming first partially remaining areas functioning as an insulation layer; introducing at least one third dopant of the first conductivity type into the semiconductor substrate; applying a second mask using the phototechnology process, the second mask covering the first zone substantially completely and, in the second zone covering only gate tracks of the transistors of the second transistor type that are to be produced and parts of the conductive layer forming the third conductive connection running on the semiconductor substrate; using the second mask for one of fully removing second areas of the conductive layer and partially removing some of the conductive layer in the second areas forming second partially remaining areas functioning as an addition part of the insulation layer; introducing at least one fourth dopant of the second conductivity type into the semiconductor substrate; increasing a temperature so that the first conductive connection running in the semiconductor substrate is formed by regions impregnated by the first dopant, the second dopant, the third dopant and the fourth dopant, the first conductive connection, the second conductive connection and the third conductive connection defining wiring running in and on the semiconductor substrate.