Patent ID: 6781586
Filing Date: 2004-08-24
Classification: G06T

Abstract:
An interpolation processing apparatus, comprising:a plurality of element processors connected in sequence, wherein the number of element processors is at least equal to the number of pixels in a row or a column of input data to be processed; each element processor for performing an arithmetic operation process in parallel with the other element processors on the row or column of the input data being processed; and control means for commonly controlling said element processors so that said element processors individually perform a weighted addition process of the input data with weighting coefficients to effect interpolation processing for the input data; each of said element processors having a memory for temporarily storing at least data in the course of the arithmetic operation process, the memories having number data allocated thereto which individually correspond to sequential order numbers of the input data; said control means controlling said element processors to perform the arithmetic operation process based on the number data to simultaneously produce the weighting coefficients which are to be used for the weighted addition process by the corresponding element processors.