Patent ID: 7696791
Filing Date: 2010-04-13
Classification: H03F,H03K

Abstract:
1. An electrical circuit, comprising: a first input FET that partially controls output voltage signals responsive to an input voltage; a gate load coupled to a gate of the first input FET; a drain load coupled to a drain of the first input FET; a source load coupled to a source of the first input FET; a controllable variable current generator providing a current to the source of the first input FET, biasing the source of the first input FET to a reference voltage, wherein the controllable variable current generator comprises a source bias FET and an op amp, a source of the source bias FET and a positive input terminal of the op amp coupled to the source of the first input FET, a gate of the source bias FET coupled to the output terminal of the op amp, and a negative input terminal of the op amp coupled to a reference voltage conductor; a first input conductor coupled to the gate of the first input FET and an input voltage signal including a variable input signal applied to the first input conductor; and a gate bias voltage source coupled to the gate load wherein the gate bias voltage source comprises a gate bias FET, a bias current generator, and a bias resistor, and the gate load comprises a first input gate resistor, the bias current generator providing a current to a drain of the gate bias FET with the drain of the gate bias FET coupled to a gate of the gate bias FET and a first terminal of the first input gate resistor, a source of the gate bias FET coupled to the bias resistor, and a second terminal of the first input gate resistor coupled to a gate of the first input FET.