Patent ID: 6821842
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A process for fabricating a dynamic random access memory (DRAM), comprising the steps of:providing a substrate; forming a plurality of trenches in the substrate; forming a capacitor inside each trench; patterning a plurality of active regions on the substrate; forming a plurality of word lines on the substrate; forming a pair of source/drain regions in each active region; and forming a plurality of bit lines over the substrate, wherein a first side edge of each active region has a first trench whose capacitor is coupled to the active region, furthermore, a second side edge of an adjacent active region has a second trench such that a word line passes through both the active region and the second trench, moreover, the area in the active region covered by the word line serves as a channel region; the source/drain regions of each active region are electrically connected to a capacitor and a bit line; and after forming the trenches but before patterning the active regions, further comprises performing an ion implantation tilted at an angle along the word line direction to form a doped region on each side of the predetermined channel region in the substrate such that the dopants within the doped regions has a conductive type identical to that of the substrate.