Patent ID: 8793675
Filing Date: 2014-07-29
Classification: G06F

Abstract:
1. A method executed by a processor, the method comprising: identifying a loop for speculative parallelization based on control and data dependence information; generating one or more speculation guards to preserve speculation information, corresponding to the loop, in response to a determination that the loop is to be parallelized; determining mis-speculation information for both control and data speculation based on execution of an inspection code, wherein the inspection code is to be generated based on the one or more speculation guards; and generating one or more split loops, corresponding to the loop, based on the mis-speculation information, wherein the loop is parallelized based on successful data speculation for every iteration of a dependence edge, carried by the loop, between a store operation which has a non-linear array subscript and a load operation which has a linear or a non-linear array subscript.