Patent ID: 7444274
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A computer implemented method for verifying a circuit design comprising: propagating a plurality of provided assertions as one or more groups of related assertions within a circuit design; classifying one assertion in each of the one or more groups of related assertions as a first requirement for verifying the circuit design, in which two assertions are related if the two assertions are propagated from a same provided assertion or one of the two assertions is propagated from the other of the two assertions; selecting a requirement from the first requirement of each of the one or more groups of related assertions to verify; isolating a portion of the circuit design containing the selected requirement; avoiding circular reasoning, in which an assumption is directly or indirectly used to prove itself; verifying the selected requirement in the isolated portion of the circuit design using one or more of the plurality of provided assertions not selected as the selected requirement in the isolated portion of the circuit design as one or more assumptions; and storing a result of the act of verifying the selected requirement in the isolated portion of the circuit design in a computer readable medium.