Patent ID: 6774662
Filing Date: 2004-08-10
Classification: G01R,G11C

Abstract:
A parallel tester for testing a panel of memory modules comprising:a plurality of upper test heads, each upper test head having pad contactors for making electrical contact with metal pads on one of the memory modules on the panel of memory modules; a plurality of lower test heads, each lower test head having pad contactors for making electrical contact with metal pads on the memory module on the panel of memory modules; a plurality of test drivers for applying test signals to the upper and lower test heads, the test signals for applying test conditions to the memory modules through the pad contactors and the metal pads, each test driver sensing current or voltage conditions on at least one of the metal pads and comparing the current or voltage conditions to predetermined conditions to determine when the memory module has failed; and a positioner that handles the panel and moves the panel into a test position between the upper and lower test heads and removes the panel from the test position after testing by the test driver; wherein the upper test heads are lowered relative to the panel in the test position, and the lower test heads are raised relative to the panel in the test position, to make contact with the metal pads on upper and lower surfaces of a plurality of the memory modules on the panel; wherein the plurality of memory modules on the panel are tested in parallel.