Patent ID: 6331721
Filing Date: 2001-12-18
Classification: H01L

Abstract:
A semiconductor memory device fabricated in accordance with a process comprising the steps of:forming a plurality of insulation regions on a semiconductor substrate to define at least one active region on the substrate;forming a first insulating layer at said active region;forming a patterned first silicon layer on a portion of said first insulating layer;forming a patterned second insulating layer overlying at least a portion of said first silicon layer;forming a recess in said first insulating layer underneath said first silicon layer by removing portions of said first insulating layer between said first silicon layer and said substrate, said recess exposing portions of said substrate and said first silicon layer;forming a patterned third insulating layer on said exposed portions of said substrate and said first silicon layer, said third insulating layer partially filling said recess;forming a patterned second silicon layer covering at least a portion of said third insulating layer and further filling said recess;forming a patterned fourth insulating layer on at least a portion of said second silicon layer; andforming a patterned third silicon layer on at least a portion of said fourth insulating layer.