Patent ID: 7818542
Filing Date: 2010-10-19
Classification: G06F

Abstract:
1. A processing unit comprising: an instruction cache configured to store a plurality of variable length instructions retrieved from the memory unit and which are to be executed by the processing unit; an instruction buffer configured to store instruction bytes associated with the plurality of variable length instructions that have been retrieved from the instruction cache; and a length decode unit configured to obtain a plurality of the instruction bytes from the instruction buffer; wherein the length decode unit is configured to perform a length decode operation for each of the plurality of instruction bytes, wherein, for each instruction byte, the length decode unit is configured to estimate the instruction length of a current variable length instruction associated with a current instruction byte; and wherein, during the length decode operation, for each instruction byte, the length decode unit is further configured to estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction and a byte position of the current instruction byte within a scan window, and to store within a pointer buffer that is separate from the instruction buffer, a first pointer to the estimated start of the next variable length instruction.