Patent ID: 9001601
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A memory device including a repair circuit, the repair circuit comprising: a fail bit location information table configured to store row address information and column address information of at least one defective cell in a normal area of a memory cell array; a row address comparison unit configured to store the row address information of the at least one defective cell, the row address information provided from the fail bit location information table, compare the row address information of the at least one defective cell with a row address of a first access cell, and output a first row match signal when the row address of the first access cell matches a row address in the row address information of the at least one defective cell; a column address comparison unit configured to store the column address information of the at least one defective cell, the column address information provided from the fail bit location information table, output a column address of a first defective cell from among the column address information of the at least one defective cell according to the first row match signal, compare the column address of the first defective cell with a column address of the first access cell, and output a first column address replacement signal for repairing the first access cell when the column address of the first defective cell is the same as the column address of the first access cell; a column decoder configured to disable the column address of the first access cell and enable a column address of a first spare cell according to the first column address replacement signal; and a row decoder configured to enable the first access cell according to the row address of the first access cell, wherein the repair circuit is configured to replace the first defective cell in the normal area of the memory cell array with the first spare cell in a spare area of the memory cell array, the first spare cell connected to an intersection of a row corresponding to the row address of the first access cell and a column corresponding to a first spare column, the spare area of the memory cell array disposed separately arranged from the normal area of the memory cell array.