Patent ID: 6141734
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A method for implementing load-locked and store-conditional instruction primitives in a data processing system consisting of a plurality of processors, the method eliminating the need for specific lock address or lock flag status registers in each processor for each block of memory for which interlocking is desired, and the method comprising the steps of, in one of the processors:upon receiving a load-locked instruction specifying a load-locked source address, obtaining the contents of a memory location corresponding to the load-locked source address, and writing the contents thereof to a corresponding location in a local cache memory associated with the processor, setting an associated valid bit and clearing an associated cache dirty bit;upon receiving a store-conditional instruction specifying a data source and a store-conditional destination address, determining whether the contents of the specified store-conditional destination address are present in the local cache memory as indicated by the valid bit, and therefore a cache hit, or are not present in the cache, and therefore a cache miss; andif a cache miss occurs, not storing the contents of the data source in the local cache memory at a location corresponding to the store-conditional destination address the store-conditional instruction thereby failing;if a cache hit occurs, and the associated dirty bit is set, storing the contents of the data source in the local cache memory at a location corresponding to the store-conditional destination address, the store-conditional instruction thereby succeeding; andif a cache hit occurs, and the associated dirty bit is cleared, obtaining permission from other processors in the system before storing the contents of the data source in the local cache memory and before permitting the store-conditional instruction to succeed.