Patent ID: 6671858
Filing Date: 2003-12-30
Classification: G06F

Abstract:
A method of designing a hierarchical-layout of a semiconductor integrated circuit device, the method comprising:determining an arrangement area where a high-order hierarchical functional block is to be arranged in a core area, the core area being an area in which a group of integrated circuits is located; determining arrangement areas where a plurality of low-order hierarchical functional blocks are to be arranged in the arrangement area of the high-order hierarchical functional block so that distances between the low-order hierarchical functional blocks is minimized; arranging cells constituting the low-order hierarchical functional blocks in each of the low-order hierarchical functional blocks; establishing signal connection terminals for connecting input/output terminals of the arranged cells to a corresponding low-order functional block; connecting the cells constituting the low-order hierarchical function blocks to each other by a first wiring layer including a first via in each of the arrangement areas of the low-order hierarchical functional blocks; connecting the low-order hierarchical functional blocks to each other by connecting a second wiring layer including a second via, different from the first wiring layer including the first via, to input/output terminals of the cells for which the signal connection terminals are established via the high-order hierarchical functional block; and connecting the high-order hierarchical functional block with the low-order hierarchical functional blocks using the second wiring layer including the second via which connects the low-order hierarchical functional blocks to each other.