Patent ID: 8609504
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A method of forming a capacitor, comprising: providing a substrate having a lower interconnect level including a first dielectric layer having a first conductive feature embedded therein, a first dielectric capping layer on said lower interconnect level, an insulating layer on said first dielectric capping layer, and a patterned hardmask layer having a top surface on said insulating layer, wherein said insulating layer has a via that extends partially through said first dielectric capping layer, said via having sidewalls and a bottom; forming a first electrode layer over said sidewalls and said bottom of said via and said top surface of said hardmask layer; forming a first high-k dielectric material layer over said first electrode layer; forming a first conductive plate layer over said first high-k dielectric material layer; forming a via gouging at said bottom of said via by removing a portion of said first conductive plate layer, a portion of said first high-k dielectric material layer, a portion of said first electrode layer, a portion of said first dielectric capping layer and a portion of said first conductive feature, said via gouging having sidewalls and a bottom and extending partially through said first conductive feature; forming a second high-k dielectric material layer over said first conductive plate layer and over said sidewalls and said bottom of said via gouging; selectively removing said second high-k dielectric material layer at said bottom and lower sidewalls of said via gouging; filling said via and said via gouging with a second electrode material; partially removing said second electrode material to form a recess at said top of said via; forming a second dielectric capping layer in said recess; and forming an upper interconnect level including a second dielectric layer having a second conductive feature embedded therein over said insulating layer, wherein said second conductive feature is in contact with said first conductive plate layer.