Patent ID: 6413861
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of fabricating a salicide layer of an embedded memory, the method comprising:providing a semiconductor wafer comprising a silicon substrate, a memory array region and a periphery circuit region defined on the substrate; forming a plurality of gates on the silicon substrate of both the memory array region and the periphery circuit region; forming a barrier layer on the semiconductor wafer to cover each gate in the memory array region and in the periphery circuit region; forming a dielectric layer on the barrier layer, the dielectric layer filling a space between two gates; performing a chemical mechanical polishing (CMP) process with the barrier layer atop each gate as an end point to remove the dielectric layer atop the gates, and to align the dielectric layer remaining between two gates with the surfaces of the two gates; forming a photoresist layer on the semiconductor wafer to at least cover the memory array region; using the photoresist layer as a mask to perform an etching process to remove the dielectric layer and the barrier layer down to the surface of the silicon substrate; removing the photoresist layer and the barrier layer atop each gate of the memory array region; and performing a salicide process to simultaneously form a salicide layer atop each gate of the memory array region, on the substrate adjacent to each gate of the periphery circuit region, and atop each gate of the periphery circuit region.