Patent ID: 6429715
Filing Date: 2002-08-06
Classification: G06F,H03L

Abstract:
A programmable logic device integrated circuit, comprising:a balanced clock tree having an input node and a plurality of output nodes; a delay-locked loop circuit having a reference signal input, a feedback signal input, and an output, the output being coupled to the input node of the balanced clock tree; a plurality of interface cells disposed along an edge of the programmable logic device integrated circuit, each of said interface cells comprising an output buffer, each of said output buffers being adapted for driving a signal off-chip, each of said output buffers having an input and an output, the input of each output buffer being coupled to a corresponding respective one of the output nodes of the balanced clock tree; and a matrix of configurable logic blocks (CLBs), the plurality of interface cells being disposed in a row between the matrix of configurable logic blocks and the edge of the programmable logic device integrated circuit.