Patent ID: 6563349
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A method of generating a glitch free output when selecting from a plurality of clock signals, said method comprising:(a) providing an OR logic gate and a plurality of AND logic gates, each of said OR logic gate and said plurality of AND logic gates comprises an output and a plurality of inputs, wherein the output of each of said plurality of AND logic gates is connected as an input of said OR logic gate; (b) providing a clock signal and a select signal as two inputs to a corresponding one of said plurality of AND logic gates; (c) introducing delays into at least one of said select signal and said clock signal corresponding to each one of said plurality of AND logic gates to ensure a desired delay exists between transitions on the corresponding select signal and the clock signal by synchronizing one of said select signal and said clock signal to one edge of a given clock signal and another one of said select signal and said clock signal to another edge of said given clock signal; (d) introducing delays into at least a plurality of said select signals and said clock signals to avoid the occurrence of a high to low transition on one input followed by low to high transition on another input of said select signal and said clock signal of said OR gate within a desired duration by synchronizing each of said slower clock signal and the select signals corresponding to said faster clock signal and said slower clock signal to an edge of said faster clock signal; wherein said plurality of clock signals comprise a faster clock signal and a slower clock signal, wherein said method further comprises receiving a sleep signal, wherein one of the two select signals corresponding to said faster clock signal and said slower clock signal is to be set to a high logical level when said sleep signal is at one logical level and another one of said two select signals is to be selected when said sleep signal is at another logical level, wherein said desired delay prevents glitches at the output of each of said plurality of AND gates and wherein said desired duration prevents glitches at the output of said OR gate, and whereby the output of said OR logic gate represents said glitch free output.