Patent ID: 6272595
Filing Date: 2001-08-07
Classification: G06F

Abstract:
An N-way, set associative cache memory comprising:a memory array having N sets of data bit lines and N sets of associated address tag bit lines;an addressing circuit which generates a tag compare address and a set address for a read operation, and write control signals for a write operation;N amplifier circuits, each of which is coupled to corresponding sets of the data/address tag bit lines of the memory array, each of the N amplifier circuits having outputs which provide data and address tags sensed from the respective data/address tag bit lines of the memory array;N read/write (R/W) circuits, each of which is correspondingly coupled to the outputs of the N amplifier circuits and also to the addressing circuit, each of the R/W circuits comprising:a buffer circuit for buffering write data/address information preceding a write operation, the buffer circuit including a comparator which generates a set compare result when the set address matches the write address;comparator means for comparing the address tags sensed by the N amplifier circuits with the tag compare address to produce a match signal; andmultiplexer means controlled by the set compare result and match signal for selecting as a cache output either a write data bit from the buffer circuit or a data bit sensed from the memory array.