Patent ID: 6212628
Filing Date: 2001-04-03
Classification: G06F,G06T

Abstract:
An apparatus for processing data, comprising:at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes processing resources coupled together to form a pipelined architecture having at least two stages; anda controller for receiving instructions and generating therefrom the processing element command words that are supplied to the at least one processing element, wherein the controller comprises:means for converting each received instruction into a sequence of one or more first-type instructions having a first format that includes a first processing element stage field and a second processing element stage field, wherein the first processing element stage field specifies a first processing element stage operation to be performed during a first clock cycle, and the second processing element stage field specifies a second processing element stage operation to be performed during a second clock cycle that is subsequent to the first clock cycle; andmeans for converting the sequence of one or more first-type instructions into the sequence of processing element command words,wherein:each of the processing element command words has a second format that includes fields specifying first and second processing element stage operations that are to be performed during a same clock cycle;each of said at least one processing element includes a synchronous random access memory (RAM) that requires application of a read address one clock cycle in advance of a clock cycle in which the contents of the addressed location in the synchronous RAM are needed at an output of the synchronous RAM; andthe controller further includes means for detecting that one of the fields in a first-type instruction specifies that a synchronous RAM read operation is to be performed, and in response to said detection the controller supplies the read address to each of said at least one processing element one clock cycle in advance of a generated processing element control word that specifies the synchronous RAM read operation.