Patent ID: 7804089
Filing Date: 2010-09-28
Classification: G02F,H01L

Abstract:
1. A TFT (thin film transistor) array substrate comprising: a gate electrode connected to a gate line; a source electrode connected to a data line; a pixel region defined by crossing the gate line and the data line; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode, the pixel electrode directly on a gate insulating layer; a channel passivation layer formed the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; a data pad having a data pad lower electrode separated from the data line, wherein the data pad is electrically connected to the data line and the data pad lower electrode through a jumping electrode, wherein the data pad includes the data pad lower electrode formed of the same material as the gate electrode and a data pad upper electrode that connects through a contact hole to the data pad lower electrode with a gate insulating layer in between, and a plurality of transparent conductive pattern formed of the same material as the pixel electrode on the data line, the source and drain electrodes, respectively, wherein a space between the transparent conductive pattern formed on the source electrode and the transparent conductive pattern formed on the drain electrode are 4-5 μm, and a space between the transparent conductive pattern formed on the data line and the pixel electrode are 4-5 μm, wherein the pixel electrode directly contacts an upper surface of the gate insulating layer.