Patent ID: 6421404
Filing Date: 2002-07-16
Classification: H03L,H04L

Abstract:
A phase-difference detector comprising:a data input terminal for inputting a data input signal; a first register circuit for receiving the data input signal from the data input terminal in synchronism with the decay timing of a base clock signal; a second register circuit for receiving the data input signal from the data input terminal in synchronism with the rise timing of the base clock signal; a first exclusive OR circuit, two input terminals of which are connected with an input terminal and an output terminal of the first register circuit; a second exclusive OR circuit, two input terminals of which are connected with the output terminal of the first register circuit and an output terminal of the second register circuit; a first AND circuit, the inverted signal of an output of the first exclusive OR circuit and the inverted signal of the base clock signal being input into two input terminals of said first AND circuit; a second AND circuit, the inverted signal of an output of the second exclusive OR circuit and the base clock signal being input into two input terminals of said second AND circuit; a third AND circuit, the output of the first exclusive OR circuit and the inverted signal of the base clock signal being input into two input terminals of said third AND circuit; an OR circuit, outputs of the second and third AND circuits being input into two input terminals of said OR circuit; a first output terminal for outputting an output of the first AND circuit; and a second output terminal for outputting an output of the OR circuit.