Patent ID: 8843693
Filing Date: 2014-09-23
Classification: G06F,G11C

Abstract:
1. A memory, comprising: an array of nonvolatile memory cells accessible page by page; each page being a group of data with a logical address and for storing in the array at a physical address; said array of nonvolatile memory cells are organized into a plurality of blocks, each block having memory cells that are erasable together; each block further partitioned into a plurality of sub-blocks, each sub-block for accommodating data corresponding to a logical group of logical addresses; a sequence of scrambling keys; a key selector for selecting a key for scrambling a page of data, said key selector selecting the key from said sequence of scrambling keys as a function of the logical address and the physical address; said physical address is a relative page address in a sub-block; and a data scrambler/unscrambler for scrambling the page of data when it is unscrambled as a function of the selected key or for unscrambling the page of data when it is scrambled as a function of the selected key; and wherein: said sequence of scrambling keys has a length L; said physical address is one of a sequence of such physical addresses, the sequence having a length N; and said function of the logical address and the physical address of the page of data depends on (logical address) mod L and (physical address) mod N.