Patent ID: 6184713
Filing Date: 2001-02-06
Classification: H03K

Abstract:
A monolithic, High-Density Complex Programmable Logic Device (HCPLD) for programmably implementing designs having parallel data words that are at least B bits wide, where B is an integer equal to or greater than 32, said HCPLD having at least 64 I/O terminals for communicating with external circuitry and at least 256 result-storing macrocells, said HCPLD further comprising:(a) a two-tiered hierarchical switch matrix construct having a Global Switch Matrix (GSM) and a plurality of Segment Switch Matrices (SSM's) operatively coupled to the GSM; and(b) for each one of the SSM's, a respective plurality of at least four programmable, Super Logic Blocks (SLB's) operatively coupled to the one SSM such that each SLB can receive in parallel a first number, K of SLB input signals from the SSM and such that each SLB can supply in parallel a second number, M of SLB output signals to the SSM, where said combination of each one SSM and its respective plurality of SLB's defines a segment;(b.1) wherein the number, K of SLB input signals is greater than 112.5% of B, the bit-width of said to-be-implemented designs; and(b.2) wherein the number, M of SLB output signals per SLB is greater than B divided by the number of SLB's in each segment.