Patent ID: 6815762
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A semiconductor integrated circuit device having a first portion for a memory array and a second portion for a circuit other than the memory array on a semiconductor substrate comprising:a MISFET arranged in said first portion, said MISFET having first semiconductor regions and a gate electrode between said first semiconductor regions; second semiconductor regions arranged in said second portion; a first insulating film formed over said semiconductor substrate to cover said first and second portions; a plurality of first openings formed simultaneously in said first insulating film above both said first and second portions; a plurality of first conductor plugs formed in said first openings in said first insulating film on said first semiconductor regions in said first portion and on said second semiconductor regions in said second portion; a first conductive strip formed on said first insulating film in said first portion and electrically connected to one of the first semiconductor regions of said MISFET through one of said first conductor plugs, wherein said first conductive strip is formed in a separate manufacturing step from said first conductor plugs; and a second conductive strip formed on said first insulating film in said second portion and electrically connected to said second semiconductor regions through said first conductor plugs to electrically connect said second semiconductor regions to one another through said second conductive strip, wherein said second conductive strip is formed in a separate manufacturing step from said first conductor plugs; insulative spacers formed at least over one of upper surfaces or sidewalls of said first and second conductive strips; a second insulating film formed over said first insulating film and said first and second conductive strips; a second opening formed in said second insulating film over an upper surface of one of the first conductor plugs formed in one of said first opening in the first insulating film and connected to the other of said first semiconductor regions of said MISFET; a second conductor plug formed in said second opening in said second insulating film to electricaily connect with said one of said first conductor plugs connected to the other of said first semiconductor regions of said MISFET; and a third conductive strip formed on said second insulating film an electrically connected to said second conductor plug, wherein one of first conductor plugs is directly physically connected to one of the first semiconductor regions and the first conductive strip in said first portion and another of the first conductor plugs is directly physically connected one of the second semiconduotor regions and the second conductive strip in the second portion.