Patent ID: 7801717
Filing Date: 2010-09-21
Classification: G06F,H01L

Abstract:
1. A method, comprising: providing a circuit pattern; generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, wherein the feasible area is identified in a design rule check (DRC) environment; simulating a planarization process with the density report to generate a thickness report for a plurality of regions and identifying a hot spot on the circuit pattern for dummy insertion, wherein the hot spot includes a region whose thickness deviates from a thickness of a neighboring region by an amount that is greater than a predefined thickness; inserting a virtual dummy pattern in the feasible area that was identified as the hot spot and adjusting the density report accordingly, wherein the inserting the virtual dummy pattern is conducted outside the DRC environment; simulating, after the inserting, another planarization process with the adjusted density report to determine whether the hot spot has been eliminated; if the hot spot has not been eliminated, repeating the inserting and simulating the another planarization process; and if the hot spot has been eliminated, fabricating a semiconductor device with a structure corresponding to a final resulting virtual dummy pattern.