Patent ID: 7593831
Filing Date: 2009-09-22
Classification: G01R

Abstract:
1. A circuit for testing a delay module having an input, an output, and control lines to control delay of said delay module, said circuit comprising: an inverter chain having an output that is coupled to said input of the delay module to form a ring oscillator that oscillates at a frequency dependent upon setting of said control lines; a counter having an input that is coupled to said output of said delay module and configured to generate a plurality of counts in response to settings of said control lines; a first register having an input that is coupled to an output of said counter and configured to store a first count of said plurality of counts; and a comparator having an input that is coupled to an output of said counter and an input that is coupled to an output of said first register, and configured to compare a second count of said plurality of counts output from said counter with said first count stored in the register to determine whether said delay module is operating correctly.