Patent ID: 6226766
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A self-testing smart memory, comprising:a data RAM, said data RAM for storing data accessible by other smart memories;a data path, connected to said data RAM, wherein said data path includes a plurality of processing elements operable to perform specific functions;a broadcast RAM connected to said data path, said broadcast RAM for storing data accessible by said data path and by external devices accessing the smart memory;memory test circuitry, coupled to said broadcast RAM and said data RAM, for testing said broadcast RAM and said data RAM, wherein said testing includes: writing a pattern to said data RAM and said broadcast RAM and comparing the contents of said data RAM and said broadcast RAM with said pattern;data path test circuitry, coupled to said data path, for testing said specific functions of said plurality of processing elements of said data path, wherein said testing includes: writing another pattern to said data path and comparing a response from said data path with an expected result; anda test controller, coupled to said data path test circuitry and said data path, for controlling said data path to perform said specific functions on said another pattern.