Patent ID: 6432797
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A method of forming shallow trench isolation in the fabrication of an integrated circuit device comprising:etching a trench into a semiconductor substrate; depositing an oxide layer overlying said semiconductor substrate and filling said trench; forming a layer of nitrogen-rich oxide at the surface of said oxide layer overlying said trench; and planarizing said trench-filling oxide layer to said semiconductor substrate wherein said nitrogen-rich oxide layer is planarized more slowly than said trench-filling oxide layer resulting in a portion of said trench-filling oxide layer remaining overlying said trench after said trench-filling oxide layer overlying said semiconductor substrate has been removed wherein said portion of said trench-filling oxide layer remaining provides a smooth transition between said shallow trench isolation and said active areas completing said formation of said shallow trench isolation in said fabrication of said integrated circuit device.