Patent ID: 6528840
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate with a top surface and a trench formed therein; a first insulating layer disposed in the bottom of said trench and partially covering a first sidewall and a second sidewall of said trench; an impurity doped polysilicon layer disposed on top of said first insulating layer; a source region in said semiconductor substrate at a top of said first sidewall of said trench; a drain region in said semiconductor substrate at a top of said second sidewall of said trench; a second insulating layer disposed on top of said polysilicon layer and on said top surface of said semiconductor substrate, wherein said second insulating layer is thicker over said polysilicon layer than over said semiconductor substrate; a gate disposed on top of said second insulating layer, a third insulating layer disposed on top of said gate; a control gate disposed over said third insulating layer; a fourth insulating layer disposed over said control gate; and an erase gate disposed over said fourth insulating layer.