Patent ID: 7764215
Filing Date: 2010-07-27
Classification: H03F,H03M

Abstract:
1. An Analog-to-Digital Converter (ADC) comprising: an analog input having an analog input voltage; a Successive-Approximation-Register (SAR) having a digital value that is successively adjusted to converge to closer approximations of the analog input voltage; a digital-to-analog converter (DAC), receiving a reference voltage and the digital value from the SAR, for generating a converted analog voltage represented by the digital value; a series of stages including a first stage and a final stage, the first stage receiving the converted analog voltage and the analog input voltage as stage inputs, the final stage outputting compare results as stage outputs, wherein each intermediate stage in the series of stages has stage inputs coupled to stage outputs of a prior stage and stage outputs connected to stage inputs of a following stage; a final latch, coupled to receive the compare results from the final stage, for latching the compare results for transmission to the SAR, wherein the SAR adjusts the digital value based on the compare results from the final latch; wherein each stage in the series of stages comprises: whereby offsets are stored on the offset-storing capacitor that is isolated from the stage inputs by using the dual-input differential amplifier with two pairs of differential inputs.