Patent ID: 7707351
Filing Date: 2010-04-27
Classification: G06F,H04L

Abstract:
1. A memory section, comprising: one or more memory devices that store data locatable by one or more addresses, the memory devices receiving control signals; a memory section controller that receives a request for data stored by the one or more memory devices, determines one or more addresses for the requested data, determines a destination identifier for use in forwarding the requested data to a specific destination device, and transfers a control signal to the memory devices including the determined addresses to the memory device storing the requested data; a memory interface device that receives from the memory device the requested data stored by the memory devices, receives from the memory section controller the determined destination identifier for use in forwarding the requested data, combines the requested data and the determined destination identifier, and forwards the combined requested data and destination identifier to the specific destination device; wherein the memory interface device further includes at least one set of shift registers interconnected in series including: