Patent ID: 6826079
Filing Date: 2004-11-30
Classification: G11C

Abstract:
A process of making a data storage device, comprising:forming a plurality of word lines; forming a plurality of bit lines; forming a resistive crosspoint array of memory cells, each memory cell connected to a respective bit line and coupled to a respective word line; forming a unidirectional conductive path from the bit line to the word line through the memory cell; applying a sense signal to a selected one of the plurality of word lines; and applying a leakage current diverting signal to unselected ones of the plurality of the word lines, wherein the leakage current diverting signal applying step comprises forming an equipotential generator coupled to the word lines and the bit lines and operable to set voltage levels in the resistive crosspoint memory cell array to substantially prevent parasitic currents from interfering with the sense signal.