Patent ID: 6772310
Filing Date: 2004-08-03
Classification: G06F,Y10S

Abstract:
A computer system, comprising:a drive array that stores data and corresponding parity data; a main memory; a processor coupled to the main memory that generates and stores data in the main memory and that sends a logical request to transfer the stored data to the drive array; and an array controller coupled to the drive array, the main memory and the processor that receives the logical request and that transfers the stored data to the drive array, comprising: a transfer buffer; a local memory that stores an index indicating free data sectors and non-zero data sectors within the transfer buffer; and processing circuitry coupled to the transfer buffer and the local memory that receives the logical request, that transfers the stored data to the transfer buffer, that combines the stored data with corresponding data from the drive array to generate new parity data and that stores the stored data and the new parity data to the drive array, and when otherwise idle, that scans the index for free and non-zero sections in the transfer buffer and that zeroes data sectors of at least one of the free and non-zero sections within the transfer buffer.