Patent ID: 6734693
Filing Date: 2004-05-11
Classification: G01R,G11C

Abstract:
A semiconductor integrated circuit comprising:first and second semiconductor storage circuits which store information; a first test circuit which is supplied with test signals to test an operation of the first semiconductor storage circuit, the test signals including a test input signal, a test output signal, and a test sync signal used for synchronization with the operation of the first semiconductor storage circuit; and a second test circuit which is connected to a stage subsequent to the first test circuit, the second test circuit receiving the test signals from the first test circuit to test an operation of the second semiconductor storage circuit, wherein the first test circuit uses the test input signal as information to operate the first semiconductor storage circuit in synchronization with the test sync signal and supplies the test input signal to the second test circuit in the subsequent stage, and the first test circuit also synchronizes a signal, which is determined by performing a logical operation between an output of the first semiconductor storage circuit and the test output signal supplied thereto, with the test sync signal and supplies the signal to the second test circuit as a test output signal.