Patent ID: 7581153
Filing Date: 2009-08-25
Classification: G06F

Abstract:
1. A memory, comprising: a memory array for storing data; a bus for data, addresses, and commands; a data register coupled to the bus to store the data written to and read from the memory array; a command register coupled to the bus for receiving external memory commands for controlling the writing of the data to the memory array or the reading of the data from the memory array; an address register coupled to the bus to address the memory array; an Error Correction Code (ECC) circuit coupled between the data register and the memory array for calculating an ECC; and means responsive to external commands and structured to control the ECC circuit for selectively outputting to the bus information associated to the ECC or to store the ECC into the memory array, the external commands being different from the external memory commands controlling the writing of the data to the memory array or the reading of the data from the memory array.