Patent ID: 6693841
Filing Date: 2004-02-17
Classification: G11C

Abstract:
A memory device comprising:a memory array having a plurality of banks of memory cells arranged in rows and columns; multiple-output buffers coupled to the plurality of banks to provide data on output nodes; a first set of data paths coupled between the plurality of banks and the multiple-output buffers to couple data from a predetermined quantity of columns of one of the plurality of banks to the multiple-output buffers; a second set of data paths coupled between the plurality of banks and the multiple-output buffers, the second set of data paths comprise first compression logic to couple the predetermined quantity of columns from each of the plurality of banks to a quantity of the multiple-output buffers that is less than the predetermined quantity of columns; and multiplex circuitry coupled to the output buffers and the first and second sets of data paths to selectively couple one of the data paths to the multiple-output buffers.