Patent ID: 6140700
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A semiconductor chip package, comprising:a package body including a recess and a plurality of barrier parts formed along one lateral side thereof, each of the barrier parts having a first region and a second region projecting from the first region away from the lateral side, and adjacent first regions being separated by a slot;a semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, disposed in the recess of the package body, said semiconductor chip being disposed such that said plurality of bonding pads are adjacent said barrier parts;a conductive member disposed in each slot;a connecting member, associated with each bonding pad, electrically connecting the associated bonding pad with a corresponding conductive member; anda sealing member sealing the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members.