Patent ID: 8835246
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: forming at least one transistor over a substrate, the at least one transistor comprising a first gate dielectric structure disposed over the substrate, a work-function metallic layer being disposed over the first gate dielectric structure, a conductive layer being disposed over the work-function metallic layer, and a source/drain (S/D) region being disposed adjacent to each sidewall of the first gate dielectric structure; forming at least one resistor structure over an isolation feature in the substrate, the at least one resistor structure comprising a first doped semiconductor layer disposed over the substrate, wherein a top surface of the at least one resistor is substantially level with a top surface of the at least one transistor; and forming a second doped semiconductor layer over the conductive layer.