Patent ID: 6261952
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming an inter-layer dielectric, comprising a dielectric material having an upper surface and overlying a substrate;forming a plurality of spaced apart openings in the inter-layer dielectric;filling the openings with a copper (Cu) or Cu alloy to form a pattern comprising neighboring spaced apart interconnect members each having an upper surface;planarizing such that the upper surface of neighboring interconnect members is substantially coplanar with the upper surface of the inter-layer dielectric;selectively removing a portion of the dielectric material leaving a remaining portion of the dielectric material of the inter-layer dielectric between neighboring interconnect members forming a recess therebetween, such that the upper surface of the neighboring interconnect members extends higher, with respect to the substrate, than the upper surface of the inter-layer dielectric comprising the remaining portion of dielectric material between the neighboring interconnect members; anddepositing a diffusion barrier layer on the upper surface of the inter-layer dielectric and on the upper surface of the neighboring interconnect members filling the recess.