Patent ID: 7529788
Filing Date: 2009-05-05
Classification: H03H

Abstract:
1. A method of designing a digital filter which multiplies signals of taps in a tapped delay line made up of a plurality of delayers by given filter coefficients, adds up the results of multiplication, and outputs the addition result, comprising: carrying out a filter design using at least one of a first unit filter and a second unit filter, 0 or more said first unit filters and 0 or more said second unit filters are arbitrarily cascade connected; said first unit filter has basic filter coefficients of an asymmetric numerical sequence whose values are set in such a way that a total value of the numerical sequence is non-zero and that a total value of every other value in said numerical sequence equals to another total value of every other value in said numerical sequence, each having the same sign; and said second unit filter has basic filter coefficients of an asymmetric numerical sequence whose values are set in such a way that a total value of the numerical sequence is zero and that a total value of every other value in said numerical sequence equals to another total value of every other value in said numerical sequence, each having the opposite sign.