Patent ID: 8286107
Filing Date: 2012-10-09
Classification: G03F,G06F

Abstract:
1. A method for accelerating process compensation technique (PCT) processing of a semiconductor chip layout, comprising: operating a computer to replace selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, wherein each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image; following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, operating a computer to perform a chip-wide PCT processing operation on the semiconductor chip layout for a given chip level; and operating a computer to record the chip-wide PCT processed semiconductor layout for the given chip level on a computer readable storage medium.