Patent ID: 6917229
Filing Date: 2005-07-12
Classification: H03L

Abstract:
1. A DLL circuit having a low jitter, comprising: a delay model unit for compensating a time difference between a reference clock signal and a delayed clock signal, and generating a compensation signal; an input buffer for receiving the reference clock signal and an inverted reference clock signal in order to output a clock signal and an inverted clock signal by respectively buffering the reference clock signal and the inverted reference clock signal; a phase detection unit for generating a comparison signal based on a delay difference between the compensation signal and the inverted clock signal according to an operating mode; a control unit for generating a plurality of control signals based on the comparison signal, the inverted clock signal and the clock signal; a delay unit for delaying the clock signal and the inverted dock signal and for performing a duty correction in response to the plurality of control signals; and an output buffer for outputting the delayed dock signal by buffering an output signal of the delay unit, wherein one of a normal mode and a fast mode is selected as the operating mode based on a result of comparing a delay amount of one unit delay included in the delay unit with the delay difference.