Patent ID: 6163045
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A memory cell comprising:a transistor including a gate and first and second diffusion regions;a trench capacitor formed in a substrate, wherein the trench capacitor includes a dielectric collar formed within a first well region of the substrate in an upper portion of a trench, a buried diffusion region formed in a second well region below the first well region in the substrate surrounding a lower portion of the trench capacitor, a node diffusion region formed above the collar that electrically connects the transistor and the capacitor;a third diffusion region formed in the first well region without extending into the second well region, the third diffuision region being formed in the substrate and having a peak dopant concentration region adjacent to the collar wherein the collar has a thickness of between about 15 nm to about 20 nm, the third diffusion region comprising a dopant concentration sufficient to increase a gate threshold voltage of a parasitic transistor formed between the buried diffusion region and the node diffusion, so as to reduce leakage to less than or equal to 1 f amps.