Patent ID: 8909948
Filing Date: 2014-12-09
Classification: G06F,H02J,H02M

Abstract:
1. A system, comprising: a power management device configured to manage power for a digital logic core and for a plurality of analog blocks, the power management device comprising: a power regulator block configured to receive an input power supply voltage and to output a regulated power supply voltage, wherein the power regulator block comprises a power regulator configured to output the regulated power supply voltage for use by the digital logic core, a first low voltage detector configured to determine whether the input power supply voltage is high enough for operation of the digital logic core and to be disabled by one or more control signals when the input power supply voltage is below a threshold, a second low voltage detector configured to determine whether the input power supply voltage is high enough for operation of the analog blocks and to be disabled by the one or more control signals when the input power supply voltage is below the threshold, a bandgap reference generator configured to generate a reference voltage inputted to the power regulator and the first and second low voltage detectors, wherein the power regulator block is configured to be controlled by signals from the digital logic core once the input power supply voltage achieves a predetermined level following a power on reset and unless the regulated power supply voltage is not high enough for operation of the digital logic core; and a masking block comprising a power on reset circuit, a plurality of level shifters, a plurality of logic gates and a delay block, wherein the masking block is configured to operate without receiving the regulated power supply voltage and to output the one or more control signals disabling the first and second low voltage detectors when the input power supply voltage is below the threshold.