Patent ID: 8937841
Filing Date: 2015-01-20
Classification: G11C

Abstract:
1. A driver for a semiconductor memory, comprising: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted memory cell address, a target charge current value, and a bucket charge current value; a current supply unit configured to supply a target charge current to a memory cell corresponding to the memory cell address in response to the target charge current select signal; and a bucket charge current supply unit configured to supply a bucket charge current to the memory cell corresponding to the memory cell address to pre-charge the memory cell in response to the bucket charge current select signal; a charge bucket calibrator configured to calibrate the bucket charge current value to pre-charge a parasitic component within the memory cell corresponding to the memory cell address and provide the calibrated bucket charge current value to the selection controller; a first sample and hold unit configured to sample a first voltage level at an end of a pre-charge period during which the bucket charge current flows into a test cell; and a second sample and hold unit configured to sample a second voltage level at an end of a stabilization period during which the target charge current flows into the test cell.