Patent ID: 7847611
Filing Date: 2010-12-07
Classification: H03K

Abstract:
1. A level shifter for shifting a level of a signal input and outputting a signal output with the shifted level, comprising: a Not gate coupled to a first voltage source so to be operable between a first high level being substantially equal to a level of the first voltage source and a low level being substantially equal to a reference voltage, and having an input end coupled to the signal input; a first PMOS transistor having a source coupled to a second voltage source and a gate coupled to a control end; a first NMOS transistor having a drain coupled to the drain of the first PMOS transistor and outputting therefrom the signal output, having a gate coupled to an output end of the Not gate, and having a source coupled to the reference voltage; a second NMOS transistor having a gate coupled to the signal input, a drain coupled to the control end, and a source coupled to the reference voltage; a racing problem reducing unit coupled to the output end of the Not gate, the control end and the second voltage source, whereby the first PMOS transistor is turned off in response to a control signal from the control end when the output end of the Not gate is at the first high level, thereby obtaining the signal output at the low level; and a leakage current preventing unit disposed between the second voltage source and the reference voltage, whereby the first PMOS transistor is turned on in response to a control signal from the control end when the output end of the Not gate is at the low level, thereby obtaining the signal output at a second high level associated with the second voltage source.