Patent ID: 6350652
Filing Date: 2002-02-26
Classification: H01L

Abstract:
A process for manufacturing electronic devices having floating gate nonvolatile memory cells, comprising:defining an active area in a substrate of semiconductor material; forming a first insulating region on top of said active area; depositing a first dielectric material layer on top of said substrate; said first dielectric material layer comprising a tunnel area; forming a floating gate region on top of said first dielectric material layer and on top of said first insulating region, said forming the floating gate region comprising depositing a first semiconductor material layer on top of said dielectric material layer and of said first insulating region and selectively removing said first semiconductor material layer using a floating gate mask having an outer delimiting side, an opening with an internal delimiting side facing said outer delimiting side at a preset distance, in that said step of selectively removing comprises the step of removing said first semiconductor material layer at the side of said external delimiting side and below said opening, forming a hole in said floating gate region, and filling said hole with an electrically insulating material; forming a second insulating region surrounding said floating gate region; forming a control gate region on top of said floating gate region; and forming conductive regions in said active area.