Patent ID: 7541232
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. A method of fabricating high electron mobility transistors on a unitary structure having a contact layer, comprising the steps of: (a) etching a contact layer of the structure to a third etch stop to define a first recess portion of a power HEMT gate recess having a first power HEMT gate recess portion width; (b) etching the contact layer of the structure to the third etch stop to define a partial depletion mode HEMT gate recess having a depletion mode gate width less than the first power HEMT gate recess portion width; (c) etching the structure in the power HEMT gate recess through the third etch stop to a second etch stop to define a second recess portion of the power HEMT gate recess, having a second recess portion width less than the first recess portion width; (d) etching in the depletion mode HEMT gate recess through the third etch stop to the second etch stop to define a depletion mode HEMT gate recess; (e) forming a gate electrode in the power HEMT gate recess; and (f) forming a gate electrode in the depletion mode HEMT gate recess.