Patent ID: 6076146
Filing Date: 2000-06-13
Classification: G06F

Abstract:
A method for retrieving a cache line of instruction bytes from a main memory subsystem and storing the cache line of instruction bytes into an instruction cache of a microprocessor, comprising:allocating a cache holding register for said cache line of instruction bytes, wherein said cache holding register is configured to store an address corresponding to said cache line of instruction bytes, and wherein said cache holding register further includes storage for said cache line of instruction bytes;receiving said cache line of instruction bytes as a plurality of packets into said cache holding register, each of said plurality of packets received during a different clock cycle;predecoding each packet of said plurality of packets in response to receiving said packet, said predecoding including detecting a predicted-taken branch instruction;fetching a target cache line of instruction bytes from said instruction cache in response to detecting said predicted-taken branch instruction, said target cache line of instruction bytes identified by a target address of said predicted-taken branch instruction;receiving remaining packets of said plurality of packets into said cache holding register; andstoring said cache line of instruction bytes into said instruction cache in response to said receiving remaining packets.