Patent ID: 8589746
Filing Date: 2013-11-19
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. first adapter circuitry having a first bidirectional test clock lead for carrying a clock signal and a first bidirectional data and control lead for carrying at least one of a test data in signal, a test mode select signal, and a test data out signal; B. second adapter circuitry having a second bidirectional test clock lead for carrying a clock signal and a second bidirectional data and control lead for carrying at least one of a test data in signal, a test mode select signal, and a test data out signal, the second bidirectional test clock lead being connected to the first bidirectional test clock lead, and the second bidirectional data and control lead being connected to the first bidirectional data and control lead; C. functional logic; and D. test circuitry having a test clock in lead, a test mode select in lead, a test data in lead, and a test data out lead, the test circuitry including a test access port controller, which includes a state machine, that is connected to the test clock in lead and the test mode select in lead and that has control outputs, an instruction register having an input connected to the test data in lead, an output coupled to the test data out lead and a control input connected to the control outputs of the controller, and a data register having a serial input connected to the test data in lead, a serial output coupled to the test data out lead, and inputs and outputs coupled to the functional logic, the test clock in lead being coupled to the first bidirectional test clock lead, and the test mode select lead, the test data in lead, and the test data out lead selectively being coupled to the first bidirectional data and control lead.