Patent ID: 9037831
Filing Date: 2015-05-19
Classification: G06F

Abstract:
1. A method of operating a memory management unit within a processor, the method comprising: providing a page table correlating a read virtual address with a corresponding read physical address for read data stored in a memory; during a read operation executed by the processor, receiving the read virtual address and accessing a translation lookaside buffer to determine whether the read virtual address matches the read physical address; and if the read virtual address matches the read physical address according to the translation lookaside buffer, providing the read physical address as a translation for the read virtual address, else if the read virtual address does not match the read physical address according to the translation lookaside buffer, storing the read virtual address in a first queue buffer and subsequently outputting the stored read virtual address from the first queue buffer, accessing the translation lookaside buffer using the read virtual address output by the first queue buffer to determine whether the read virtual address matches the read physical address according to the translation lookaside buffer, and upon determining that the read virtual address does not match the read physical address according to the translation lookaside buffer, accessing the page table using the read virtual address to determine a different read physical address, and outputting the different read physical address.