Patent ID: 9190468
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first conductivity type or second conductivity type semiconductor substrate; a first conductivity type drift layer formed on said semiconductor substrate; a plurality of quadrangle-shaped second conductivity type well regions disposed periodically in a surface layer of said drift layer with a length of a first side in plan view being a and a length of a second side orthogonal thereto in plan view being b; a first conductivity type source region formed in a surface layer of each of said well regions; a gate electrode formed over from each of said source region to said drift layer via a gate insulating film; and a channel region specified in said well regions opposite to each of said gate electrode, wherein when a direction of said first side is an x-axis direction and a direction of said second side is a y-axis direction, and when a distance between each of said well regions in said x-axis direction is A and a distance between each of said well regions in said y-axis direction is B, a second well region adjacent to a first well region in the x-axis direction, among said well regions, is disposed misaligned from said first well region in the y-axis direction by a width larger than zero and smaller than b+B, and a third well region adjacent to the first well region in the y-axis direction, among said well regions, is disposed misaligned from said first well region in the x-axis direction by a width larger than zero and smaller than a+A.