Patent ID: 8891315
Filing Date: 2014-11-18
Classification: G11C

Abstract:
1. A method of erasing a nonvolatile memory device which includes a plurality of memory blocks each formed of a plurality of strings, the method comprising: applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block comprising at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells; wherein the respective gates of the at least two dummy cells are connected to a plurality of dummy lines, wherein the different levels of voltage are applied to the respective gates of the at least two dummy cells in response to the dummy lines not being floated, and wherein the different levels of voltages are induced to the respective gates of the at least two dummy cells in response to the dummy lines being floated.