Patent ID: 6991979
Filing Date: 2006-01-31
Classification: H01L

Abstract:
1. A complementary metal oxide semiconductor (CMOS) structure comprising: a gate region formed on a surface of a semiconductor substrate, said gate including an dielectric layer formed on exposed vertical sidewalls thereof and a substrate surface; a vertical nitride spacer element formed on each said vertical sidewall of said gate stack overlying said dielectric layer, whereby a portion of said dielectric layer underlies said vertical nitride spacer above said substrate surface such that an edge of said portion of said dielectric layer underlying said vertical nitride spacer is aligned with an outer edge of said vertical nitride spacer element; a nitride plug formed over said gate stack, vertical nitride spacer elements an said edge of said portion of dielectric layer underlying said vertical nitride spacer, said nitride plug encapsulating and sealing said underlying dielectric layer; and, silicide contacts formed on other portions of said semiconductor substrate adjacent said patterned gate region, for contact with drain and source regions formed in said semiconductor substrate.