Patent ID: 8355239
Filing Date: 2013-01-15
Classification: G01D,G01P,H03L

Abstract:
1. A phase locked loop (PLL) circuit, comprising a first signal detector having a first input terminal configured to receive a varying first input signal, a second input terminal configured to receive a second input signal that corresponds to the center of the first signal, and an output terminal configured to provide an output signal corresponding to a phase difference between the first and second input signals; a delay estimator having an input terminal configured to receive the output signal from the first signal detector, wherein the delay estimator is configured to use a prediction algorithm based on past values of the output signal from the first signal detector and the received output signal from the first signal detector to output a phase difference estimation signal; a variable delay circuit having an input terminal configured to receive the phase difference estimation signal and an output terminal configured to provide an output signal representing the second input signal phase shifted based on the phase difference estimation signal.