Patent ID: 6424003
Filing Date: 2002-07-23
Classification: H01L

Abstract:
In an EEPROM cell including a floating gate, a programmable junction region, and a tunneling oxide layer separating said programmable junction region and said floating gate, said tunneling oxide layer defining a tunneling window which allows for programming and erasing of said floating gate by tunneling electrons therethrough, wherein the improvement comprising:said programmable junction region having a width dimension and length dimension so as to define a first area; said tunneling window having a width dimension and a length dimension so as to define a second area; said floating gate having a width dimension and a length dimension so as to define a third area; said width dimension of said tunneling window being greater than said width dimension of said programmable junction region so as to overlap said programmable junction region; said length dimension of said tunneling window being less than said length dimension of said programmable junction region so as to be confined within the length dimension of said programmable junction region; said length dimension of said floating gate being less than said length dimension of said tunneling window so that said tunneling window is overlapping said floating gate; and said width dimension of said floating gate being larger than said width dimension of said tunneling window so that said floating gate is overlapping said tunneling window, whereby said tunneling window is self-aligned by edges formed said length dimension of said floating gate so as to form a self-aligned tunneling window.