Patent ID: 7098109
Filing Date: 2006-08-29
Classification: H01L

Abstract:
1. A method for manufacturing a multi-level SONOS memory cell, comprising: providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a substrate, an insulation layer and a silicon layer; patterning the silicon layer to form a silicon stripe; forming a composite dielectric layer over the silicon stripe, wherein the composite dielectric layer is a silicon oxide/silicon nitride/silicon oxide layer, and the composite dielectric layer covers a top part and two sidewalls of the silicon stripe; forming a conductive stripe over the SOI substrate, wherein the conductive stripe is perpendicular to the silicon stripe; removing the composite dielectric layer not covered by the conductive stripe; forming source/drain regions in the silicon stripe beside two sides of the conductive stripe; forming spacers on the sidewalls of the silicon stripe and the overlapping portion of the conductive stripe and the silicon stripe; and removing the conductive stripe not cover by the spacers to form a first control gate and a second control gate on the two sidewalls of the silicon stripe.