Patent ID: 9064092
Filing Date: 2015-06-23
Classification: G06F

Abstract:
1. An integrated circuit comprising: compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes through parallel bus links; a network extension unit at each end of each row or column of the array, inserted in the bus between two compute nodes, the extension unit having a normal mode establishing the continuity of the bus between the two corresponding compute nodes, and an extension mode dividing the bus in two independent bus segments; a set of parallel/series converters forming each an outgoing serial channel for transmitting in series on a first external terminal of the circuit data presented in parallel on a bus segment; a set of series/parallel converters forming each an incoming serial channel for transmitting in parallel on a bus segment data arriving in series on a second external terminal of the circuit; and a load balancer common to the extension units of a same edge of the array, configured to allocate available outgoing serial channels between the bus segments for which an outbound transmission is in progress.