Patent ID: 8247883
Filing Date: 2012-08-21
Classification: H01L,H05K

Abstract:
1. An apparatus comprising: a first conductor or semiconductor layer; a first insulator layer deposited on the first conductor or semiconductor layer; a second conductor or semiconductor layer deposited on the first insulator layer; a second insulator layer deposited on the first insulator layer and covering the second conductor or semiconductor layer, the second insulator layer defining a shielded region; and a third conductor or semiconductor layer deposited on the first conductor or semiconductor layer and encapsulating the first and second insulator layers; wherein at least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing, and wherein one of the first and second conductor or semiconductor layers is a gate and the third conductor or semiconductor layer includes a source and drain of a transistor device.