Patent ID: 8327092
Filing Date: 2012-12-04
Classification: G06F

Abstract:
1. An electronic device comprising: a memory module comprising a first memory block, a second memory block, a programmable storage location, and a memory controller; the first memory block comprising a plurality of data unit locations, and an address decoder coupled to a first access port of the memory controller, the address decoder to select one of the plurality of data unit locations for access in response to receiving address information via the first access port; the second memory block comprising a plurality of data unit locations, and an address decoder coupled to a second access port of the memory controller, the address decoder to select one of the plurality of data unit locations for access in response to receiving address information via the second access port; the programmable storage location to store configuration information; and the memory controller comprising a control port coupled to the programmable storage location, the memory controller to access a first portion of the first memory block and a first portion of the second memory block as interleaved memory or as non-interleaved memory or as a mixture of interleaved memory and non-interleaved memory based upon the programmable configuration information, wherein the configuration information includes a value indicating a size of the first portion of the first memory block to be accessed as interleaved memory.