Patent ID: 7262988
Filing Date: 2007-08-28
Classification: G11C

Abstract:
1. A memory circuit comprising: a latch circuit having a first inverter and a second inverter; a first ferroelectric capacitor that gives a first capacitance to a power supply terminal of the first inverter; a second ferroelectric capacitor that gives a second capacitance different from the first capacitance to a power supply terminal of the second inverter; and a voltage source that starts supplying a drive voltage for driving the latch circuit to the power supply terminal of the first inverter to which the first capacitance is given and the power supply terminal of the second inverter to which the second capacitance is given, wherein a first end of the first ferroelectric capacitor is connected to the power supply terminal of the first inverter, a first end of the second ferroelectric capacitor is connected to the power supply terminal of the second inverter, and the voltage source is connected to each of the power supply terminals and each of the first ends.