Patent ID: 6188246
Filing Date: 2001-02-13
Classification: H03K

Abstract:
A semiconductor circuit comprising a logic circuit section and a latch circuit section,wherein said logic circuit section includes:higher and lower potential side actual power supply lines;higher and lower potential side quasi power supply lines;a CMOS logic circuit connected between said higher and lower potential side quasi power supply lines and composed of MOS transistors having a first threshold voltage; anda power connection section which connects at least one of said higher and lower potential side actual power supply lines to a corresponding one of said higher and lower potential side quasi power supply lines, a remaining one of said higher and lower potential side actual power supply lines being directly connected to a corresponding one of said higher and lower potential side quasi power supply lines, wherein said power connection section includes at least one control MOS transistor having a second threshold voltage higher than said first threshold voltage,wherein said latch circuit section includes:a first CMOS inverter connected between said higher and lower potential side quasi power supply lines;a latch circuit operatively and selectively connected to said first CMOS inverter in series and composed of second and third CMOS inverters connected in series; anda transfer gate having said second threshold voltage and disposed between said first CMOS inverter and said latch circuit.