Patent ID: 6566241
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of forming a metal contact in a semiconductor device having an active metal contact region and a bit line contact region, the method comprising:forming gate stacks on a semiconductor substrate; forming gate spacers on the sidewalls of the gate stacks; forming a lower interlayer dielectric layer to cover the gate stacks and the gate spacers; forming first contact holes which perforate the lower interlayer dielectric layer and expose an active region of the semiconductor substrate; filling the first contact holes with a metal barrier layer and a conductive plug; removing an upper portion of the metal barrier layer to form at least one groove in the lower interlayer dielectric layer surrounding the upper sides of the conductive plug; filling the grooves with an etch stopper; etching the lower interlayer dielectric layer so that the etch stopper protrudes above the lower interlayer dielectric layer; forming a bit line stack by sequentially stacking a bit line conductive layer and a bit line capping layer on the conductive plug in the bit line contact region; forming an etch stopper on the conductive plug in the active metal contact region and bit line spacers at the sidewalls of the bit line stack in the bit line contact region; forming an upper interlayer dielectric layer to cover the etch stopper, the bit line stack, and the bit line spacers; etching a portion of the upper interlayer dielectric layer to form second contact holes which expose the etch stopper and the surface of the bit line capping layer; removing the etch stopper and the exposed portion of the bit line capping layer pattern to form third contact holes which expose the conductive plug in the active metal contact region and the bit line conductive layer in the bit line contact region; and filling the third contact holes with a conductive layer.