Patent ID: 6901419
Filing Date: 2005-05-31
Classification: G06F

Abstract:
1. A processor operable to process P-bit length data and Q-bit length data and to output the processed data, said processor comprising: a first register operable to store a P-bit length data; and a second register operable to store a Q-bit length data, wherein said processor is operable to output a processed data having a higher part and a lower part in one cycle, wherein the lower part of the processed data comprises a higher part of the P-bit length data, wherein the higher part of the processed data comprises a lower part of the Q-bit length data, wherein the higher part of the P-bit length data is m bits in length, wherein the Lower part of the Q-bit length data is n bits in length, and wherein a bit length of the P-bit length data, the Q-bit length data and the processed data are equal to m+n bits in length.