Patent ID: 8331651
Filing Date: 2012-12-11
Classification: G06K,G06T,H01L

Abstract:
1. An apparatus for inspecting a defect of a circuit pattern formed on a semiconductor wafer comprising: SEM image obtaining means for obtaining a SEM image of an inspection region on the semiconductor wafer formed with the circuit pattern; defect inspecting and classifying means for comparing the SEM image of the inspection region obtained by the SEM image obtaining means with a reference image, and for classifying the SEM image of the inspection region on the semiconductor wafer; and an outputting means for outputting results classified by the defect inspecting and classifying means; wherein the defect inspecting and classifying means further comprises: comparison shape forming means for forming a plurality of comparison shapes corresponding to the SEM image of the inspection region by deforming the shape of the circuit pattern in accordance with a plurality of shape deformation rules using design data corresponding to the circuit pattern within the inspection region, and for selecting a shape similar to the SEM image of the inspection region out of the plurality of comparison shapes formed as the comparison shape; and shape comparing and classifying means for classifying the SEM image using information of the comparison shape selected in the comparison shape forming means and the inspection shape of the circuit pattern of the SEM image of the inspection region.