Patent ID: 8266198
Filing Date: 2012-09-11
Classification: G06F

Abstract:
1. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry for providing products of inputs and sums of said products to output a result, said arithmetic circuitry comprising a plurality of fundamental processing units, each of said fundamental processing units including: a plurality of partial product generators, each respective one of said partial product generators having a respective pair of inputs different from inputs of each other one of said partial product generators and providing a respective plurality of vectors representing a respective partial product, compressor circuitry that compresses each respective plurality of vectors into a smaller number of vectors representing said respective partial product, and circuitry for adding, in one operation, partial products represented by said smaller number of vectors produced by all of said plurality of partial product generators, each said respective partial product being unroutable to any output of said specialized processing block, thereby being unavailable for output, except after being added, by said circuitry for adding, to other of said respective partial products; said specialized processing block further comprising: rounding circuitry that provides both: a first user-selectable option to round said result to a nearest integer, and a second user-selectable option to round said result to a nearest even integer.