Patent ID: 6470458
Filing Date: 2002-10-22
Classification: G06F

Abstract:
A method for dynamic synchronization of data processing system processor chips, said method comprising the steps of:launching a pulse from a secondary chip to a primary chip, said chips being coupled together via a plurality of links; evaluating a clock pattern related to said pulse with a reference clock pattern of said primary chip; and synchronizing a clock phase of said secondary chip to said clock phase of said primary chip based on a result of said comparing step; wherein said evaluating comprises: transmitting a synchronization pattern between said secondary chip and said primary chip, wherein said pattern is first transmitted to said primary chip from said secondary chip, then re-transmitted to said secondary chip; logging a number of clock cycles required for said pattern to return to said secondary chip; comparing said number of clock cycles to a predetermined value to yield a result; and adjusting said local clock of said secondary chip based on said result.