Patent ID: 9105327
Filing Date: 2015-08-11
Classification: G06F,G11C

Abstract:
1. A memory controller comprising: input circuitry configured to receive a differential pair of data strobe signals from a memory, said input circuitry configured to generate a logical data strobe signal in dependence on a voltage difference between said differential pair of data strobe signals; hysteresis circuitry configured, when switched to an active state, to increase by a predetermined offset a threshold voltage difference at which said input circuitry is configured to change a logical state of said logical data strobe signal; and gate signal generation circuitry configured to generate a data strobe gating signal, wherein said memory controller is configured to interpret said logical data strobe signal as valid when said data strobe gating signal is asserted, wherein said memory controller is configured to perform a training process to determine a timing offset for said data strobe gating signal with respect to said logical data strobe signal, wherein said training process comprises a first phase in which said hysteresis circuitry is in said active state and a second phase in which said hysteresis circuitry is not in said active state.