Patent ID: 8013449
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A chip comprising: a silicon substrate; an ESD circuit on said silicon substrate; an internal circuit on said silicon substrate; a driver, receiver or I/O circuit on said silicon substrate; a dielectric layer over said silicon substrate; a fine-line metallization structure over said silicon substrate and in said dielectric layer, wherein said fine-line metallization structure comprises a first interconnecting structure connected to a first terminal of said driver, receiver or I/O circuit, a second interconnecting structure connected to said internal circuit, and a third interconnecting structure connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit, wherein said fine-line metallization structure comprises a copper line and a first adhesion layer at a bottom of said copper line and at a sidewall of said copper line; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and a fourth interconnecting structure over said passivation layer, wherein said fourth interconnecting structure is connected to said first and second vias, wherein said first terminal is connected to said internal circuit through, in sequence, said first interconnecting structure, said first via, said fourth interconnecting structure, said second via and said second interconnecting structure, wherein said fourth interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a sidewall not covered by said second adhesion layer.