Patent ID: 8816759
Filing Date: 2014-08-26
Classification: H03K

Abstract:
1. An electric circuit comprising: a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, wherein the first delay amount and the second delay amount are shorter than a clock period of the first clock; an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock; a selector configured to: receive the first clock and the second clock, select one of the first clock and the second clock based on a mode signal, and output the selected one as a clock signal; and a scan circuit including a shift register in which a plurality of flip-flop circuits are connected in a form of a chain, the scan circuit configured to capture data in synchronization with the clock signal when a mode signal indicates a second mode and to shift the captured data in synchronization with the clock signal when the mode signal indicates a first mode.