Patent ID: 6643760
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A memory system, comprising:a memory logically organized in M bit wide blocks as a plurality of rows of 2N columns, where N and M are positive integers; and a memory interface, connected to the memory to receive an address specifying a memory block and supply the corresponding memory contents of up to (N+1) blocks, whereby said address is supplied to the first N of said columns, the memory interface comprising: an adder connected to receive a first portion of the address and supply said first portion with one added thereto, wherein said first portion of the address is sufficient to specify the row to which a block belongs; and an input multiplex circuit connected to the second N of said columns to receive the address, the output of the adder, and a portion of the address sufficient to specify whether the address the specified block belongs to the first N of said columns, whereby the second N of said columns is supplied with the address when the specified block belongs to the second N of said columns and is supplied with the output of the adder when the specified block belongs to the first N of said columns.