Patent ID: 6310804
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A semiconductor memory comprising:a first sub-array and a second sub-array; andcircuitry coupled to the first sub-array and second sub-array used to store row addresses of defective rows in the first sub-array and second sub-array and activate a redundant row in one sub-array of the first sub-array and second sub-array when receiving a row address matching one of the stored defective row addresses while disabling a redundant row arranged in the other sub-array of the first sub-array and second sub-array in an order complementary to that of the activated redundant row, the circuitry comprising:a plurality of fuse banks to store the row addresses of defective rows and output a match signal in response to receiving a row address matching one of the stored row addresses of defective rows;at least a first row decoder and at least a second row decoder connected to the respective first sub-array and second sub-array to activate redundant rows in at least one sub-array of the first sub-array and second sub-array in response to receiving the match signal; anda plurality of enable fuses connected between the plurality of fuse banks and the at least a first row decoder and the at least a second row decoder to conduct the match signal to the first row decoder and isolate the match signal from the second row decoder to disable activation of the redundant row in the second sub-array of the first sub-array and second sub-array.