Patent ID: 8621303
Filing Date: 2013-12-31
Classification: G01R,G06F

Abstract:
1. A Design-For-Test (DFT) circuit comprising: a first multiplexer coupled to receive a clock signal, an inverted version of the clock signal, and a clock polarity control signal, wherein the first multiplexer is operable to output one of the clock signal or the inverted version of the clock signal according to the clock polarity control signal; a burst counter coupled to the first multiplexer, wherein the burst counter is operable to output a signal at a first logic state for a predefined pulse count; and a second multiplexer coupled to receive the clock polarity control signal, the clock signal, and the signal output from the burst counter, wherein the second multiplexer is operable to output one of the clock polarity control signal or the clock signal according to the signal output from the burst counter.