Patent ID: 6275960
Filing Date: 2001-08-14
Classification: G06F,G11C

Abstract:
A method of self-test and correction of errors due to a loss charge for a flash memory comprising an array of cells organized in rows and columns, and being erasable and programmable by whole sectors in which the array is divided, the method comprising the steps of:realizing at least one additional row and at least one additional column of cells for each memory sector;storing parity codes in the additional at least one row and in the additional at least one column, respectively, byreading in sequence all bytes of a first row of a sector, counting the number of ""1""s in the first row, verifying a parity, and programming a respective parity bit in the additional at least one column, and repeating the reading, counting, verifying and programming operations by incrementing a row address until executing the operations for a last row of the sector, andreading in sequence all bytes of a first column of the sector, counting the number of ""1""s in the first column, verifying a parity, and programming a respective parity bit in the additional at least one row and repeating the reading, counting, verifying and programming operations by incrementing a column address until executing the operations for a last column of the sector; andcarrying out periodically a self-test routine and eventual correction routine comprising the following stepsrepeating the reading in sequence per bytes and parity check,verifying parity consistency of the parity check value with the respective stored parity bit,if the verifying parity consistency is negative, retaining a current row address and proceeding to sequentially verify column parity starting from the first column until identifying a column for which verification yields a negative result thereby identifying a failed bit, andif the failed bit is ""1"" reprogramming it to ""0"".