Patent ID: 8068150
Filing Date: 2011-11-29
Classification: G06F,H04N

Abstract:
1. A memory access control apparatus comprising: a memory controller controlling a memory adopting a double data rate format; a double-data-rate physical interface adjusting the timing of an interface signal transferred between the memory controller and the memory; a double-data-rate physical-interface controller controlling the double-data-rate physical interface; and a clock controller controlling the frequency of a clock signal, wherein a first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller on the basis of a blanking signal indicating the presence of access from a master device to the memory; a second request signal for resetting the double-data-rate physical interface is supplied to the double-data-rate physical-interface controller on the basis of a response signal to the first request signal, supplied from the memory controller; a third request signal for changing the clock frequency is supplied to the clock controller on the basis of a response signal to the second request signal, supplied from the double-data-rate physical-interface controller; a fourth request signal for setting a parameter for the double-data-rate physical interface in accordance with the clock frequency subjected to the change is supplied to the double-data-rate physical-interface controller on the basis of a response signal to the third request signal, supplied from the clock controller; and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller on the basis of a response signal to the fourth request signal, supplied from the double-data-rate physical-interface controller, whereby changing the clock frequency of the memory.