Patent ID: 7998791
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A method of packaging integrated circuits, comprising: attaching a plurality of dice to a leadframe panel, each die being positioned within a device area of the leadframe panel, each device area including a plurality of leads that surround the die; electrically connecting the dice to associated leads within their respective device areas with electrical connections; positioning a heat sink panel over the leadframe panel, the heat sink panel including a plurality of integrally connected heat sinks, each heat sink having a top surface and an opposing bottom surface that both overlie an active surface of an associated die, the bottom surface of the heat sink being positioned over and thermally coupled with the active surface of the associated die using an associated spacer, wherein the associated spacer does not extend beyond the periphery of the active surface of the associated die and wherein the heat sinks of the heat sink panel are connected through tab portions that are recessed relative to the top surfaces of the heat sinks; pressing the top surface of each heat sink flush against a mold cavity to help seal off the top surfaces of the heat sink, there being gaps between the recessed tab portions of the heat sink panel and the mold cavity; encapsulating portions of the leadframe panel, dice and heat sink panel with a molding material such that the molding material enters the gaps between the recessed tab portions and the mold cavity to cover the tab portions of the heat sink panel while leaving the top surface of each heat sink uncovered with molding material, wherein the encapsulated heat sink panel is physically supported over the leadframe panel only by the molding material and the spacers that are attached to the active surfaces of the dice; and singulating the leadframe panel, molding material and heat sink panel to provide a plurality of individual integrated circuit packages, whereby each integrated circuit package includes an associated die and an associated heat sink that is exposed on an outer surface of the integrated circuit package, wherein any spacer within each integrated circuit package that attaches to the associated heat sink is positioned directly between the active face of the associated die and the associated heat sink.