Patent ID: 8120941
Filing Date: 2012-02-21
Classification: G11C

Abstract:
1. A memory array comprising: a plurality of memory cells arranged into an M number of rows and an N number of columns with each memory cell comprising a resistive sense element (RSE) and a switching device; a total number of M+N+1 control lines extending adjacent to and connected with the memory cells so that the switching devices of the memory cells along each row are connected to a respective one of said M control lines and the memory cells along each column are connected between a respective pair of said N+1 control lines; and a control circuit which programs a selected memory cell by setting each of said N+1 control lines on one side of the selected memory cell along a selected row to a first voltage level and each of the remaining said N+1 control lines on an opposing second side of the selected memory cell along the selected row to a second voltage level different from the first voltage level.