Patent ID: 7718496
Filing Date: 2010-05-18
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: providing a substrate having at least one logic nFET region, at least one SRAM nFET region, at least one logic pFET region and at least one SRAM pFET region; selectively forming crystalline silicon germanium in the logic pFET region; growing an interfacial layer dielectric over the logic nFET region, the SRAM nFET region, the logic pFET region and the SRAM pFET region; depositing a high-K layer over the interfacial layer dielectric; forming a capping layer in the logic nFET region over a side of the high-K layer opposite the interfacial layer dielectric; depositing a metal layer over the capping layer in the logic nFET region and over the high-K layer in the SRAM nFET region, the logic pFET region and the SRAM pFET region; depositing a silicon layer over the metal layer; performing an etch through the interfacial layer dielectric, the high-K layer, the capping layer, the metal layer and the silicon layer to form a logic nFET gate stack over the logic nFET region, and through the interfacial layer dielectric, the high-K layer, the metal layer and the silicon layer to form a SRAM nFET gate stack over the SRAM nFET region, a logic pFET gate stack over the logic pFET region and a SRAM pFET gate stack over the SRAM pFET region.