Patent ID: 7808043
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having an NMOS region and a PMOS region; a first gate electrode on the substrate of the NMOS region; a second gate electrode formed to be spaced apart from the first gate electrode on the substrate of the PMOS region; an auxiliary spacer on a sidewall of the first gate electrode, wherein the auxiliary spacer is selectively formed in the NMOS region, wherein the auxiliary spacer is not formed on an upper surface of the first gate electrode; a second gate spacer on a sidewall of the second gate electrode, wherein a stress property of the second gate spacer is different from a stress property of the auxiliary spacer, wherein the second gate spacer is not formed on an upper surface of the second gate electrode; and an etch stop layer on the substrate having the auxiliary spacer and the second gate spacer, wherein the etch stop layer and the auxiliary spacer are formed of a material having a same stress property.