Patent ID: 6323671
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A circuit for performing a -charge gain stress test for a nonvolatile memory having plurality of cells, comprising:a reference current generator that generates a reference current;a comparator that compares a cell current from a selected one of the nonvolatile memory cells with the reference current and outputting a compare result;a first switch controlled by a first control signal to selectively connect the comparator or a first voltage to a drain of the selected nonvolatile memory cell;a second switch controlled by the first control signal to selectively connect the first voltage or a second voltage to a gate of the selected nonvolatile memory cell, or controlled by a second control signal to selectively connect the first voltage or a third voltage to the gate of the selected nonvolatile memory cell; anda third switch controlled by the second control signal to selectively connect the first voltage or a fourth voltage to a source of the selected nonvolatile memory cell.