Patent ID: 8927966
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A dynamic random access memory unit, comprising: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, wherein a material of the two isolation regions is nonconductive, and a semiconductor contact layer is formed between the two isolation regions and is a charge channel; a source, a drain and a channel region formed on the two isolation regions and the semiconductor contact region respectively and constituting a transistor operating region, wherein the transistor operating region is spatially partially separated from the charge storing region by the two isolation regions, and the transistor operating region is connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed on the drain.