Patent ID: 7234022
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A system, comprising: a storage array including a plurality of mass storage devices; an array controller configured to perform block operations on data stored to the storage array, wherein the array controller includes a memory configured to provide an addressable block operand storage space and to store within the block operand storage space block operands received from one or more of said plurality of mass storage devices; and a cache accumulator memory comprising a plurality of block storage locations and a functional unit configured to perform a block operation on one or more block operands to generate a block result; wherein the plurality of block storage locations of the cache accumulator memory are configured to cache a portion of the block operand storage space of the memory; wherein in response to an instruction using an address in the memory to identify a first block operand, the cache accumulator memory is configured to: wherein the plurality of block storage locations of the cache accumulator memory are further configured to accumulate an intermediate result of a block accumulation operation performed on the first block operand, wherein the intermediate result is both a result of and an operand of the block accumulation operation, such that during the block accumulation operation, the plurality of block storage locations of the cache accumulator memory are concurrently configured both to cache certain ones of the block operands and to accumulate the intermediate result of the block accumulation operation.