Patent ID: 8559237
Filing Date: 2013-10-15
Classification: G11C

Abstract:
1. A method for verifying erase of pages of non-volatile memory array having n blocks, each block having m pages of memory cells, each of n and m being a positive integer greater than one, each block having a plurality of strings of memory cells on a substrate and m wordlines across the plurality of strings, each wordline being operably connected to a respective one of the m pages of memory cells, the method comprising: selecting at least one of the n blocks; selecting any one or ones of the m pages in the selected block; applying a select verify voltage to the wordline or wordlines corresponding to the selected any one or ones of the m pages for causing the memory cell of the selected any one or ones of the m pages to conduct if erased; applying an unselect verify voltage to the wordline or wordlines corresponding to unselected one or ones of the m pages for causing the memory cell of the unselected one or ones of the m pages to conduct regardless of a respective state of the memory cell of the unselected one or ones of the m pages; and sensing a state of each of the plurality of strings for verifying erase of the memory cell of the wordline or wordlines corresponding to the selected any one or ones of the m pages.