Patent ID: 8929129
Filing Date: 2015-01-06
Classification: G05F,G11C

Abstract:
1. A device, comprising: first and second signal lines; first and second transistors of a first conductivity type coupled in series between the first and second signal lines and coupled to each other at a first node; third and fourth transistors of a second conductivity type coupled in series between the first and second lines and coupled to each other at a second node; a power supply node coupled in common to the first and second nodes; a fifth transistor of the first conductivity type coupled between the first and second signal lines; and a sixth transistor of the second conductivity type coupled between the first and second signal lines, wherein each of the first, second and fifth transistors is configured to receive a first control signal at a gate electrode thereof, each of the third and fourth transistors is configured to receive a second control signal, that is different from the first control signal, at a gate electrode thereof, and the sixth transistor is configured to receive a third control signal, that is different from the second control signal and complementary to the first control signal, at a gate electrode thereof.