Patent ID: 6388533
Filing Date: 2002-05-14
Classification: G06F

Abstract:
A ring oscillator clock circuit comprising:a plurality of ring oscillator stages disposed in a linear chain from a first ring oscillator stage to a last ring oscillator state, each ring oscillator stage including a propagate input, a propagate output, a return input, a return output; a latch storing either a first state or a second state, said latch having a true output and a complement output, a first AND gate having a first input connected to said propagate input, a second input connected to said true output of said latch and an output connected to said propagate output, a second AND gate having a first input connected to said propagate input, a second input connected to said complement output of said latch and an output, and a third AND gate having a first input connected to said return input, a second input connected to said output of said second AND gate and an output connected to said return output; an output stage connecting said return output of said first ring oscillator stage to said propagate input of said first ring oscillator stage to circulate a ring pulse, said output stage generating an oscillator clock signal; wherein said propagate input of a ring oscillator stage is connected to said propagate output of a prior ring oscillator state; wherein said return input of a ring oscillator stage is connected to said return output of a next ring oscillator state; wherein said propagate output of said last ring oscillator stage is connected to said return input of said last ring oscillator stage.