Patent ID: 6584109
Filing Date: 2003-06-24
Classification: H04L

Abstract:
A repeater having a plurality of ports for providing connections between media segments coupled thereto, comprising:ten megabit per second (Mbit/s) repeater logic for connecting ten megabit per second devices to a ten megabit per second backplane; one hundred megabit per second (Mbit/s) repeater logic for connecting one hundred megabit per second devices to a one hundred megabit per second backplane; and a port switching fabric, coupled to the ten megabit per second repeater logic and to the one hundred megabit per second repeater logic, for determining the transmission rate of a signal at a port and routing the signal to one of the repeater logic according to the transmission rate determination; a media access controller (MAC) for controlling functions including the transmission, loopback and reception of Ethernet frames; a direct memory access (DMA) controller for servicing the media access controller and controlling memory; and a transmit and receive FIFO, coupled to the MAC, for providing latency for the DMA controller.