Patent ID: 8878307
Filing Date: 2014-11-04
Classification: H01L,Y10S

Abstract:
1. An electronic device comprising a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a diffusion region of at least one transistor, wherein a single dielectric layer extends from a top surface of said gate conductor region to a conductive interconnect, said conductive interconnect disposed directly over and adjacent to the single dielectric layer, and further wherein said shared contact does not extend to a top surface of said single dielectric layer, wherein the electronic device comprises an SRAM cell, and further wherein said device comprises (a) a first shared contact between (i) a gate conductor region shared by a first N-channel MOSFET and a first P-channel MOSFET and (ii) a drain diffusion region of a second N-channel MOSFET, (b) a second shared contact between (i) a gate conductor region shared by said second N-channel MOSFET and a second P-channel MOSFET and (ii) a drain diffusion region of said first P-channel MOSFET.