Patent ID: 9135007
Filing Date: 2015-09-15
Classification: G06F

Abstract:
1. A micro controller configured for system processing in a digital controlled power supply system, comprising: an A/D converter configured to perform A/D conversion of voltage signals from the digital controlled power supply system; a processing unit configured to perform filter operation of data from the A/D converter; a pulse width modulator configured to set a duty of a pulse width modulation waveform to drive a power MOS transistor in the digital controlled power supply system; a direct memory access controller configured to perform data transfer from the A/D converter to the processing unit and data transfer from the processing unit to the pulse width modulator; and a central processing unit configured to perform system processing for the digital controlled power supply system, wherein the processing unit performing the filter operation comprises: a program memory configured to store an operation processing sequence, which is configured with a row of instructions; a program counter configured to set an address indicative of which instruction is to be executed in the operation processing sequence; and a control logic circuit configured to control operation processing comprising: storing in the program memory the operation processing sequence, wherein each of the instructions of the operation processing sequence is configured to include a bit field having instruction stop flag information indicative of whether to stop execution of the instruction and bit field information indicative of an execution resumption trigger condition of the instruction; setting in the program counter an address indicative of which instruction is to be executed in the operation processing sequence; and executing an instruction whose instruction stop flag information is cleared and proceeding to processing of the next instruction, in which: execution of the instruction whose instruction stop flag information is set is stopped if the execution resumption trigger condition in the bit field information is not satisfied; and the instruction whose instruction stop flag information is set is executed if the execution resumption trigger condition in the bit field information is satisfied, and processing is proceeded to the next instruction, thereby to enable executing the filter operation by said processing unit independently from and simultaneously with the system processing performed by the central processing unit.