Patent ID: 7670932
Filing Date: 2010-03-02
Classification: H01L

Abstract:
1. A method for fabricating an MOS structure, the method comprising: providing a semiconductor substrate; fabricating a gate stack on the semiconductor substrate; forming a first mask overlying the semiconductor substrate, the first mask having an opening; epitaxially growing semiconductor material on the semiconductor substrate within the opening; forming a second mask overlying the semiconductor material; etching the epitaxially grown semiconductor material using the second mask as an etch mask to form a contact projection on the semiconductor substrate; removing the second mask; removing the first mask; implanting ions of a conductivity-determining type within the semiconductor substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the semiconductor substrate; forming a metal silicide layer on the contact projection; and forming a contact to the metal silicide layer, wherein the contact is in electrical communication with the impurity-doped regions via the contact projection.