Patent ID: 6215835
Filing Date: 2001-04-10
Classification: H03L,H04L

Abstract:
A method of recovering a data clock signal responsive to a serial data stream, the method comprising the steps of:providing a first clock signal to a first input to a first phase-locked loop circuit, the first clock signal having a predetermined frequency substantially equal to an expected frequency of the serial data stream;generating a second clock signal responsive to the first clock signal so that the second clock signal has substantially the same frequency as the first clock signal, wherein the step of generating the second clock signal is performed by the first phase-locked loop circuit;providing the serial data stream to a second input to the first phase-locked loop circuit;without changing the frequency of the first clock signal, fine tuning the second clock signal responsive to the serial data stream so that the second clock signal forms a recovered clock signal in synchrony with the serial data stream.