Patent ID: 8053808
Filing Date: 2011-11-08
Classification: H01L

Abstract:
1. A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain, wherein the semiconductor power device further comprising: a source metal connected to said source, and a gate metal configured as a metal band extended from a gate pad surrounding a peripheral region of said semiconductor substrate connected to a gate pad wherein said gate metal and said gate pad are separated from said source metal by a metal gap; an ESD protection circuit comprising a plurality of alternating doped polysilicon regions of opposite conductivity types extended as parallel straight strip segments parallel to said metal band constituting Zener diodes extending across said metal gap and having at least an outermost straight strip segment disposed directly under said gate metal the parallel strip segments contact an inner of said gate metal and at least an innermost straight strip segment opposite said outermost straight strip segment disposed directly under the source metal and the parallel strip segments contact an outer edge of said source metal wherein said Zener diodes disposed on a top surface of said semiconductor substrate near said peripheral region of said semiconductor substrate; said ESD protection circuit further comprises a first set of said doped polysilicon regions extended as said parallel straight strip segments constituting a first set of said Zener diodes along edges of said gate pad as a first stage of said ESD protection circuit and said ESD protection circuit further comprises a second set of doped polysilicon regions extended as said parallel straight strip segments constituting a second set of Zener diodes as a second stage of said ESD protection circuit wherein each of said first and second stages having the outermost straight strip segment disposed directly under and the parallel strip segments contact the inner edge of the gate metal disposed at said peripheral region away from said gate pad; and said first stage of said ESD protection circuit is disposed on edges of said gate pad having a width perpendicularly across said first set of doped polysilicon regions extended as the parallel straight strip segments greater than a width perpendicularly across said second set of doped polysilicon regions extended as the parallel straight strip segments of said second stage of said ESD protection circuit disposed at said peripheral region away from said gate pad.