Patent ID: 7095816
Filing Date: 2006-08-22
Classification: H03L,H04J,H04L

Abstract:
1. A clock/data recovery circuit comprising: a voltage control oscillator for generating a clock signal of a frequency of 1/K (K=2, 3, . . . ) of a bit rate of an input data signal; a delay circuit for delaying said input data signal for timing adjustment; a demultiplexer for demultiplexing said input data signal into M demultiplexed signals (M=2, 3, . . . ) by using said clock signal; a multiplexer for multiplexing said M demultiplexed signals by using said clock signal; a phase comparator for comparing phases of an output signal of said delay circuit and an output signal of said multiplexer; a lowpass filter for extracting DC voltage from an output signal of said phase comparator and for inputting said DC voltage to said voltage control oscillator as a control voltage; wherein said clock/data recovery circuit outputs said clock signal generated by said voltage control oscillator as a recovery divided clock signal, and outputs said M demultiplexed signals from said demultiplexer as recovery parallel data signals.