Patent ID: 6614865
Filing Date: 2003-09-02
Classification: G06F,H03L

Abstract:
A clock generator comprising:a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; an external clock output circuit for generating an external clock signal from the divided clock signal; an internal clock output circuit for generating an internal clock signal from the divided clock signal; and a phase adjusting circuit for adjusting a phase of the internal clock signal with that of the external clock signal, wherein said frequency divider further comprises a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a lock signal supplied from said phase adjusting circuit is active, generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is made inactive.