Patent ID: 6559676
Filing Date: 2003-05-06
Classification: H03K

Abstract:
An output buffer circuit comprising:a power supply node supplied with a power supply potential level; a ground node supplied with a ground potential level; a data output node which outputs data; a first transistor of a first conductive type, which is coupled between said power supply node and said data output node and which has a control electrode; a second transistor of a second conductive type, which is coupled between said ground node and said data output node and which has a control electrode; a data input node which received data; a first pull up transistor of the first conductive type, which is provided at a first current path between said power supply node and the control electrode of said first transistor and which charges the control electrode of said first transistor to the power supply potential level in response to data at said data input node; a first pull down transistor of the second conductive type, which is provided at a second current path between said ground node and the control electrode of said first transistor and which discharges the control electrode of said first transistor to the ground potential level in response to data at said data input node; a second pull up transistor of the first conductive type, which is provided at a third current path between said power supply node and the control electrode of said second transistor and which charges the control electrode of said second transistor to the power supply potential level in response to data at said data input node; a second pull down transistor of the second conductive type, which is provided at a fourth current path between said ground node and the control electrode of said second transistor and which discharges the control electrode of said second transistor to the ground potential level in response to data at said data input node; a slew-rate control node; a third transistor of the first conductive type, which is coupled between said power supply node and said slew-rate control node and which has a control electrode connected to the control electrode of said first transistor; a fourth transistor of the second conductive type, which is coupled between said ground node and said slew-rate control node and which has a control electrode connected to the control electrode of said second transistor; a first variable resistance circuit which is provided at the second current path and which has a resistance value, the resistance value of said first variable resistance circuit is changed in response to a potential of said slew-rate control node; and a second variable resistance circuit which is provided at the third current path and which has a resistance value, the resistance value of said second variable resistance circuit is changed in response to a potential of said slew-rate control node.