Patent ID: 6614686
Filing Date: 2003-09-02
Classification: G11C

Abstract:
Non-volatile memory circuit for recording multiple bit information, comprising:a plurality of cell transistors, which have first and second source-drain regions formed at a substrate surface, and a first insulating layer, a non-conductive trapping gate, a second insulating layer, and a control gate, formed sequentially on a channel region between the first and second source-drain regions, wherein cell transistors record data by trapping charge locally at at least both ends of said trapping gate; a plurality of word lines, which are connected with the respective control gates of said plurality of cell transistors arranged in a row direction; a plurality of source-drain lines, which are connected commonly with the source-drain regions of said cell transistors that are adjacent in said row direction; and a plurality of page buffers, which are respectively connected with said plurality of source-drain lines, which supply, to each source-drain line within a group of adjacent source-drain lines, a combination of a floating state, a read-out voltage state, a reference voltage state, a read-out voltage state, and a floating state, in sequential order, and which read out said recorded data from the source-drain lines in said read-out voltage state.