Patent ID: 6798708
Filing Date: 2004-09-28
Classification: G06F,G11C

Abstract:
A memory controller for controlling memories by utilizing serial data, comprising:interface means for inputting at least serial data including an instruction bit train with addition of a start bit at the beginning thereof, a clock signal synchronized with the serial data, a chip enable signal for designating a relevant apparatus and a reset signal for resetting the relevant apparatus; serial data storing means for storing the serial data depending on the clock signal during an active period in which the chip enable signal is inputted; access control means for executing a memory access depending on content of the instruction bit train stored in the serial data storing means; enabling signal generating means for generating an enabling signal to enable operation of the access control means based on the an timing of the active period; and inhibiting means for inhibiting generation of the enabling signal based on the active period end timing when the relevant apparatus is reset during the active period.