Patent ID: 6779012
Filing Date: 2004-08-17
Classification: G06F

Abstract:
In a computer system including:a central processing unit; a memory connected to the processing unit by a processor bus; and a floating point logic in the central processing unit comprising an apparatus for performing a square root operation on a radicand, producing a root digit, the apparatus comprising: a digit generator, the digit generator computing the root digit dependent on a number of bits of a current signed digit partial remainder, the radicand selected as the current signed digit partial remainder for computing a first root digit; a multiplexor coupled to the digit generator, the multiplexor selecting a binary correction term dependent on the root digit; an adder which receives a the binary correction term and the current signed digit partial remainder and generates a signed digit result by subtracting the binary correction term from the current signed digit partial remainder; and a scaler coupled to the adder, the scaler computing a next signed digit partial remainder dependent on the signed digit result, the next signed digit partial remainder selected as the current signed digit partial remainder for computing a next root digit.