Patent ID: 7342766
Filing Date: 2008-03-11
Classification: H01L

Abstract:
1. An on-chip capacitor having a plurality of layers; each capacitor layer comprising a pair of frames, such that a first frame of the pair is electrically connected to first frames on each other layer and a second frame of the pair is electrically connected to second frames on each other layer; a plurality of tines projecting from each frame within the respective layer, the tines from each frame meshing so as to form an array of sequentially alternating tines to provide a layer capacitance within the layer, wherein the multi-layer capacitor further includes a plurality of projections from said tines, said projections extending between frames of adjacent layers so as to provide an interstitial capacitance between the layers, such that the total capacitance of the on-chip capacitor is the sum of each layer capacitance and each interstitial capacitance.