Patent ID: 7541289
Filing Date: 2009-06-02
Classification: H01J,H01L

Abstract:
1. A method of processing a semiconductor wafer, comprising: roughening the interior surface of a metal lid to a surface roughness in excess of RA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling; forming a conductive via in a dielectric layer of the semiconductor wafer, covering the conductive via with an overlying dielectric layer and forming a high aspect ratio opening of 65 nm or less through the overlying dielectric layer to the conductive via to expose a face of the conductive via; removing residue from the exposed face of the conductive via while capturing at least a portion of said residue on the roughened interior surface of said lid, by: forming a barrier layer on sidewall surfaces of said high aspect ratio opening; and depositing a conductor over said barrier layer in said high aspect ratio opening.