Patent ID: 9058458
Filing Date: 2015-06-16
Classification: G06F,H01L

Abstract:
1. A method of assembling a serializer-deserializer (SERDES) and integrated circuit package comprising: providing a logic die having a logic circuit; providing a SERDES structure of at least a first SERDES die having a first SERDES circuit and a second SERDES die having a second SERDES circuit, the first SERDES die and the second SERDES die discrete from one another, the first and second SERDES dies positioned adjacent in a plane, the SERDES structure selected from a menu of SERDES circuit and SERDES die combinations; stacking the logic die vertically on the SERDES structure and the SERDES structure vertically on a package substrate; communicatively connecting at least the first SERDES circuit to transmit and receive data in parallel from the logic circuit and to transmit and receive data in serial from a package substrate.