Patent ID: 6187619
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for fabricating a MOS transistor and an ESD protective transistor in a silicon substrate, said method comprising the steps of:providing an isolation region in said silicon substrate, said isolation region separating a functional region which has a first poly-gate for forming said MOS transistor from an ESD protective region which has a second poly-gate for forming said ESD protective transistor;forming a first insulating layer on all resulting surfaces;performing a first ion implantation to all resulting surfaces using first conductive ions so as to form a first lightly doped drain region in said functional region and to form a second lightly doped drain region in said ESD protective region;performing a second ion implantation with a tilted angle to all resulting surfaces using second conductive ions so as to form a first anti-punchthrough region beneath said first poly-gate and to form a second anti-punchthrough region beneath said second poly-gate, said second conductive ions having an opposite electrical conductivity to said first conductive ions;masking said functional region utilizing a photoresist layer;performing a third ion implantation with a tilted angle to said ESD protective region using two kinds of said first conductive ions co-implanted so as to form a doped region beneath said second poly-gate;forming a second insulating layer on said ESD protective region using said photoresist layer as a mask;removing said photoresist layer;forming dielectric spacers on sidewalls of said first poly-gate and on a portion of first lightly doped drain region using said second insulating layer as an mask so that a remnant of said lightly doped drain region serves as first source/drain region;forming a self-aligned silicide layer on said first poly-gate and said first source/drain region;performing a fourth ion implantation to all resulting surfaces so as to form said first source/drain region in said functional region using said second insulating layer as a mask;forming a third insulating layer on all resulting surface; andperforming a thermal annealing to said substrate so as to form ultra-shallow junctions in said functional region and DDD junctions in said ESD protective region.