Patent ID: 6449699
Filing Date: 2002-09-10
Classification: G06F

Abstract:
A method for partitioning memory in a cache coherent symmetric multiprocessor system (SMP) to provide cache coherency for inter cache transfers, the SMP comprising, a plurality of processors each associated with cache memory; a shared memory; a shared communications bus; and a memory controller, said method comprising the following steps:subdividing said shared memory into a plurality of independent memory partitions and assigning each of said plurality of memory partitions to at least one of said plurality of processors; executing said plurality of processors in a single cache coherence domain on said shared communications bus; monitoring inter cache requests for cache lines by requesting processors from responding processors on said shared communications bus of the SMP for detecting if an address associated with an inter cache request for a cache line is outside of a memory partition assigned to a requesting processor; and correcting a memory partition assigned to a responding processor that responds to the inter cache request with an inter cache transfer of the cache line resulting in an illegal inter cache transfer via a write back of data representing the cache line to the memory partition assigned to the responding processor, wherein each of said plurality of independent memory partitions of said SMP retains independent fault protection properties.