Patent ID: 6500748
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:forming a semiconductor element on a semiconductor substrate; forming an insulating layer above said semiconductor element, wherein said insulating layer has a flat upper surface; etching said insulating layer to form first and second grooves and a plurality of pillars in said first groove, said first groove having a lattice pattern by said plurality of pillars, each pillar having a flat upper surface; forming a hole directly under said second groove; filling said first groove with a first layer of conductive material to form a bonding pad; filling said second groove with a second layer of conductive material to form a wiring layer; filling said hole with a third layer of conductive material to form a contact plug, said bonding pad, said wiring layer and said contact plug are formed simultaneously; forming an etching stopper layer on said insulating layer and said first and second layers of conductive material; forming a passivation layer on said etching stopper layer; etching said passivation layer to form an opening of said passivation layer above said first layer of conductive material, said passivation layer being etched selectively with respect to said etching stopper layer, thereby removing only said passivation layer; and removing only portions of said etching stopper layer exposed by the opening of said passivation layer, said etching stopper layer being etched selectively with respect to said insulating layer, thereby the flat upper surface of said insulating layer coincides with surfaces of said first and second layers of conductive material.