Patent ID: 7630208
Filing Date: 2009-12-08
Classification: H01G,H05K,Y02P

Abstract:
1. A multilayer chip capacitor comprising a capacitor body having a multilayer structure where a plurality of dielectric layers are stacked; and a plurality of external electrodes formed on a side surface of the capacitor body, wherein the capacitor body includes a first capacitor unit and a second capacitor unit, all of which are arranged along a lamination direction, wherein the first capacitor unit includes at least a pair of first and second internal electrodes (the first and second internal electrodes have different polarities), all of which are alternately disposed in the inside of the capacitor body to face each other while being isolated in the dielectric layers, wherein the second capacitor unit includes a plurality of third and fourth internal electrodes (the third and fourth internal electrodes have different polarities), all of which are alternately disposed in the inside of the capacitor body to face each other while being isolated in the dielectric layers, wherein a plurality of the external electrodes include at least one first external electrode coupled to the first internal electrode, at least one second external electrode coupled to the second internal electrode, at least one third external electrode coupled to the third internal electrode, and at least one fourth external electrode coupled to the fourth internal electrode, and wherein the first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.