Patent ID: 8217467
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a substrate comprising a cell array region and a peripheral circuit region; a device isolation pattern on the substrate, the device isolation pattern defining a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region; a first common source region, a plurality of first source/drain regions and a first drain region in the first active region; a second common source region, a plurality of second source/drain regions and a second drain region in the second active region; a third source/drain region in the third active region; a common source line contacting the first common source region and the second common source region; a first landing plug connected to the first drain region; a second landing plug connected to the second drain region; a third landing plug connected to the third source/drain region; a first bit line coupled to the first landing plug and a second bit line coupled to the second landing plug, wherein the third landing plug is coupled to one of the first bit line and the second bit line, wherein the first bit line and the second bit line are located at different heights above the substrate, and wherein the top surfaces of the common source line, the third landing plug, and at least one of the first landing plug and the second landing plug are substantially coplanar.