Patent ID: 8634260
Filing Date: 2014-01-21
Classification: G11C

Abstract:
1. A device comprising: a set of input nodes supplied with a plurality of defective addresses, each of the defective addresses comprising a more significant bit portion, that contains at least one bit including a most significant bit, and a less significant bit portion, that contains two or more bits including a least significant bit; first and second latch circuits each electrically connected to the set of input nodes; a control circuit configured to control the first and second latch circuits such that the first latch circuit latches a first one of the defective addresses to produce a first latched defective address and that the second latch circuit does not latch a second one of the defective addresses, that is equal in less significant bit portion to the first latched defective address, and latches a third one of the defective addresses, that is different in less significant bit portion from the first latched defective address, to produce a second latched defective address; a first non-volatile memory coupled to the first latch circuit and configured to be written with the first latched defective address; and a second non-volatile memory coupled to the second latch circuit and configured to be written with the second latched defective address.