Patent ID: 8350597
Filing Date: 2013-01-08
Classification: G01R,H03K

Abstract:
1. A circuit arrangement comprising: a first comparator with a first input terminal and a second input terminal, said first comparator having a first input offset voltage when said first and second input terminals are short-circuited; a second comparator with a third input terminal and a fourth input terminal, said second comparator having a second input offset voltage when said third and fourth input terminals are short-circuited; and a third comparator with a fifth input terminal and a sixth input terminal, said third comparator having a third input offset voltage when said fifth and sixth input terminals are short-circuited; wherein, said third comparator is configured in a first phase to compensate said first and second input offset voltages and minimize the offset errors generated by said third input offset voltage; and said second comparator is configured in a second phase to compensate said first input offset voltage based on said first phase, said second phase being subsequent to said first phase; and each one of said first, second and third comparators has its output coupled together to a high impedance node.