Patent ID: 9223520
Filing Date: 2015-12-29
Classification: G06F,G11C,H04L

Abstract:
1. A memory controller for a multi-node computing circuit, the computing circuit including multiple computational nodes and an interconnection network interconnecting the computational nodes to each other and to the memory controller, wherein the computational nodes are organized in clusters of computational nodes and wherein the interconnection network includes a hierarchy of crosspoint switches to facilitate communication between a computational node in one cluster with a computational node in another cluster, the computational nodes communicating via at least one service, the memory controller comprising: a network interface allowing one of the plurality of nodes to communicate with the memory controller for a request via the at least one service, the at least one service including one or a group of: a peek and poke service, a memory random access (MRA) service, a direct memory access (DMA) service, a point-to-point (PTP) service, a real-time input (RTI) service and a message service; and a memory interface configured to access a memory to fulfill the request.