Patent ID: 9059165
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first wiring layer defined on a main surface of a semiconductor substrate; a second wiring layer defined above the first wiring layer; an interlayer insulation layer formed between the first and second wiring layers; first and second lines extending along in a first direction on the first wiring layer; third and fourth lines extending along in a second direction crossing the first direction on the second wiring layer; and a plurality of conductor plugs penetrating through the interlayer insulation film, wherein the first line in the first wiring layer includes a first connection region and a first non-connection region, the third line in the second wiring layer includes a second connection region and a second non-connection region, the second connection region in the second wiring layer overlapping the first connection region in the first wiring layer, the plurality of conductor plugs is disposed in the interlayer insulating layer between the first and second connection regions and electrically couples the first and second connection regions, a distance between the first connection region and the second line is smaller than a distance between the first non-connection region and the second line, and a distance between the second connection region and the fourth line is smaller than a distance between the second non-connection region and the fourth line, wherein one of the first and second connection regions is formed into a polygon having five or more sides.