Patent ID: 6226685
Filing Date: 2001-05-01
Classification: H04L,H04Q

Abstract:
A control circuit in a network switch for multicast packet transmission, comprising:an internal control buffer subdivided into a plurality of storage sections for storing a plurality of buffer-control records each comprising a control pointer, a counter value, an addressing tag number, and a valid bit for each coming multicast packet;addressing tag generating means for generating said addressing tag number for each coming multicast packet in response to said addressing tag number and said valid bit stored in each storage section of said internal control buffer; andcontrol means for determining if said counter value and said control pointer of said coming multicast packet is to be stored in one of said storage sections of said internal control buffer according to said addressing tag number generated by said addressing tag generating means upon receiving a multicast packet request, and transmitting said multicast packet, that is found by accessing said addressing tag number and said control pointer, to a plurality of output ports, wherein said counter value indicates the number of transmission times for said coming multicast packet.