Patent ID: 8705280
Filing Date: 2014-04-22
Classification: G11C,H01L

Abstract:
1. A semiconductor structure comprising: an assembly of a PFET and an NFET in a series connection, wherein a source/drain node of said PFET and a source/drain node of said NFET constitute a common node, and a gate electrode of said PFET and a gate electrode of said NFET constitute a common floating gate that is not electrically connected to any other node of any other transistor and is configured to trap and retain electrical charges therein and is electrically floating; and a programming device configured to inject electrical charges by causing said electrical charges to pass from a channel, or a drain, of one of said PFET and said NFET through one of a gate dielectric of said PFET and a gate dielectric of said NFET into said common floating gate.