Patent ID: 7224625
Filing Date: 2007-05-29
Classification: G11C

Abstract:
1. Method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets (D 0 –D 3 ) are written to the semiconductor memory per data burst (DB), in which write access is initiated by a write command (WR) and the data packets (D 0 –D 3 ) which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal (WDQS), where the data packets (D 0 –D 3 ) are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal (WDQS), and where the data strobe write clock control signal (WDQS) has a defined state at the start of the write operation.