Patent ID: 7227249
Filing Date: 2007-06-05
Classification: H01L

Abstract:
1. A three-dimensional stacked semiconductor package, comprising: a lead that includes an inner lead portion, an outer lead portion, an inner distal end, an outer distal end and first and second opposing surfaces, wherein the inner lead portion is adjacent to the inner distal end and spaced from the outer distal end, the outer lead portion is adjacent to the outer distal end and spaced from the inner distal end, the inner and outer lead portions are adjacent to and integral with one another, the first surface of the lead faces in a first direction, the second surface of the lead faces in a second direction opposite the first direction, and the first and second surfaces of the lead extend across the inner and outer lead portions; a first semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the first chip includes a first conductive pad, the first surface of the first chip faces in the first direction, the second surface of the first chip faces in the second direction, the first chip is disposed vertically beyond the inner lead portion in the first direction, the second surface of the first chip and the first surface of the inner lead portion face towards one another, the inner lead portion extends within and outside a periphery of the first chip and the outer lead portion is disposed outside the periphery of the first chip; a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad, the first surface of the second chip faces in the first direction, the second surface of the second chip faces in the second direction, the second chip is disposed vertically beyond the inner lead portion in the second direction, the first surface of the second chip and the second surface of the inner lead portion face towards one another, the inner lead portion extends within and outside a periphery of the second chip, the outer lead portion is disposed outside the periphery of the second chip and the first chip vertically overlaps the second chip; a first insulative adhesive that contacts and is sandwiched between the second surface of the first chip and the first surface of the inner lead portion; a second insulative adhesive that contacts and is sandwiched between the first surface of the second chip and the second surface of the inner lead portion; a first wire bond that contacts and electrically connects the first pad and the first surface of the inner lead portion, wherein the first wire bond extends vertically beyond the first chip in the first and second directions, is disposed vertically beyond the second chip in the first direction, extends within and outside the peripheries of the first and second chips, contacts the inner lead portion at a first bond site outside the peripheries of the first and second chips and extends vertically beyond the inner lead portion in the first direction but not the second direction; a second wire bond that contacts and electrically connects the second pad and the first surface of the inner lead portion, wherein the second wire bond is disposed vertically beyond the first chip in the second direction, extends vertically beyond the second chip in the first direction but not the second direction, is disposed within the peripheries of the first and second chips, contacts the inner lead portion at a second bond site within the peripheries of the first and second chips, extends vertically beyond the inner lead portion in the first and second directions and contacts the first adhesive, and the first bond site is laterally spaced from and coplanar with the second bond site; and an encapsulant that contacts the first and second chips, the first and second adhesives and the first wire bond.