Patent ID: 9189331
Filing Date: 2015-11-17
Classification: G06F,H03K,H03M,Y02D

Abstract:
1. A data processing system comprising: a central processing unit executing program instructions to manipulate data; a memory attribute register having plural entries, each entry storing a plurality of memory attributes for a corresponding memory address range, said memory attributes including a write-through enable (WTE) bit indicating a write-through or a write-back for said corresponding memory address range; a first data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; a second level memory including a second level cache connected to said central processing unit and to said first data cache temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; a data memory controller connected to said first data cache, said data memory controller upon a central processing unit write to data cached in said first data cache a unified memory controller connected to said second level cache, said unified memory controller upon a central processing unit write to data cached in said second level cache said write-through enable (WTE) bit of each entry of said memory attribute register is located in said data memory controller and at least one of said plurality of memory attributes of each entry of said memory attribute register is located in said unified memory controller.