Patent ID: 6815276
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of fabricating a high power MOS transistor, the method comprising:forming a first transistor segment in a substrate, the first transistor segment comprising a first source segment, a first drain segment, and a first gate segment, wherein the first transistor segment comprises a first segment area determined according to a safe operating area specification for the high power MOS transistor; forming a second transistor segment spaced in the substrate from the first transistor segment by at least a thermal diffusion distance, the second transistor segment comprising a second source segment, a second drain segment, and a second gate segment, wherein the second transistor segment comprises a second segment area determined according to the safe operating area specification, and wherein the thermal diffusion distance is based on a pulse time specification; coupling the first and second source segments to a source structure; coupling the first and second drain segments to a drain structure; and coupling the first and second gate segments to a gate structure.