Patent ID: 6055610
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A distributed-memory multiprocessor system with directory-based cache coherency, said system comprising:plural memory cells communicatively coupled to each other and collectively including plural processors, user-data caches, main memories, fast coherency directories, and coherency controllers;each of said cells including at least one of said processors, at least one of said caches, one of said coherency controllers, one of said main memories, and one of said fast coherency directories;each of said main memories storing user data and including a main coherency directory that presents coherency information;each of said fast coherency directories storing incomplete tags;each of said coherency controllers responding to requests for data by accessing its respective fast coherency directory and its respective main coherency directory concurrently so that predictive recalls based on information retrieved from said fast coherency directory can be initiated before the corresponding information is retrieved from said main coherency directory.