Patent ID: 8661384
Filing Date: 2014-02-25
Classification: G06F

Abstract:
1. A verification support apparatus comprising: a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value, wherein the simulation result is a result of a simulation in which a given input pattern is provided to circuit data of the circuit-under-test that includes a first clock domain and a second clock domain that receives a signal from the first clock domain asynchronously; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive the signal in the second clock domain; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit.