Patent ID: 6658632
Filing Date: 2003-12-02
Classification: G01R

Abstract:
An electrical circuit, comprising:a first flip-flop having a data input configured to receive a functional signal generated by application logic, a clock input controlled by a functional clock signal, and an output configured to provide a first flip-flop output signal; a first multiplexer having a first input coupled the output of said first flip-flop, a second input configured to receive a test mode shift-in signal, an output, and a select input, wherein the state of said select input determines whether said first flip-flop output signal or said shift-in signal is presented at said output of said first multiplexer; a second flip-flop having a data input coupled to said output of said first multiplexer, a clock input controlled by a first test clock signal, and an output; a third flip-flop having a data input coupled to said output of said second flip-flop, a clock input controlled by a second test clock signal, and an output configured to provide a third flip-flop output signal; and an output storage element comprising a second multiplexer and a fourth flip-flop, said second multiplexer having a first input configured to receive said functional signal, a second input coupled to said output of said third flip-flop, an output, and a mode select input, wherein the state of said mode select input determines whether said functional signal or said third flip-flop) output signal is presented to the output of said second multiplexer, and said fourth flip-flop having a data input coupled to said output of said second multiplexer and a clock input controlled by said functional clock signal.