Patent ID: 7957186
Filing Date: 2011-06-07
Classification: G11C

Abstract:
1. A non-volatile memory system comprising: a single-level cell (SLC) array composed of a plurality of SLCs; and a multi-level cell (MLC) array composed of a plurality of MLCs, wherein the SLC array and the MLC array share a same data bus to output read SLC data and read MLC data from the SLC array and MLC array, respectively, wherein the SLC array and the MLC array simultaneously receive a read instruction, wherein the SLC array and the MLC array are responsive to the read instruction to simultaneously initiate a read operation in accordance with the read instruction, and wherein outputting of the read MLC data from the MLC array on the data bus begins after completion of outputting of the read SLC data from the SLC array on the data bus.