Patent ID: 6728799
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A data input/output circuit, comprising:register circuit comprising a plurality of data registers that form shift register blocks, wherein each data register comprises a plurality of scan cells comprising a data shift input, a data shift output and a shift clock input, and wherein the data shift inputs and outputs of the scan cells are coupled to pass data through the register circuit in sequence according to signals at the shift clock input, the couplings between data registers forming data access nodes; and an I/O control circuit having an address bus input, the I/O control circuit including a plurality of transmission gate circuits coupling the respective data access nodes to a data input/output port, the I/O control circuit also including selection circuitry coupled to the transmission gate circuits for selecting one of the transmission gate circuits on the basis of input on the address bus, so as to enable data to pass between the data register circuit and the input/output port through the selected transmission gate and for shifting data through the scan cells until required data appears at the input/output port.