Patent ID: 9013892
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A chip stacking structure, comprising: a plurality of microbump structures; a plurality of first substrates, stacked upon each other by a first part of the microbump structures, and each of the first substrates comprises at least one first redistribution layer; at least one first space layer, located between the first substrates, wherein the first part of the microbump structures is disposed in the at least one first space layer, and is configured to connect the at least one first redistribution layer of the first substrates; a plurality of second substrates, stacked on at least one of the first substrates by a second part of the microbump structures, and each of the second substrates comprises at least one second redistribution layer; and at least one second space layer, located between the first substrates and the second substrates, wherein the second part of the microbump structures is disposed in the at least one second space layer, and is configured to connect the at least one first redistribution layer of the first substrates and the at least one second redistribution layer of the second substrates, wherein the first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.