Patent ID: 6469355
Filing Date: 2002-10-22
Classification: G11C,H01L

Abstract:
A configuration for voltage buffering in a dynamic memory using CMOS technology, comprising:a driver; a PMOS transistor in said driver; a NMOS transistor in said driver; a p-conducting semiconductor substrate to be connected to a low supply voltage for supplying a first voltage thereto; an n-conducting well structure provided in said p-conducting semiconductor substrate, said n-conducting well structure to be connected to a high supply voltage for supplying a second voltage thereto; a p-conducting semiconductor region enclosed by said n-conducting well structure, said p-conducting semiconductor region being supplied with a third voltage; and a semiconductor bulk region of said PMOS transistor being supplied with the second voltage; said NMOS transistor being provided in said p-conducting semiconductor region; and said n-conducting well structure and said bulk region of said PMOS transistor being connected in parallel; said p-conducting semiconductor bulk region being connected to a negative word line reverse voltage for supplying the third voltage thereto for voltage buffering; and the second voltage being higher than said first voltage and the third voltage.