Patent ID: 6961337
Filing Date: 2005-11-01
Classification: H04L,Y10S

Abstract:
1. A system for processing a packet, wherein said packet includes a source address bit pattern and a destination address bit pattern that are each processed by a task processor in accordance with a data tree, said data tree including a plurality of nodes linked by branches wherein an instruction that is associated with each node is utilized for selecting a next branch in accordance with said source address bit pattern or said destination address bit pattern, said system comprising: a first bank of registers for loading an instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said source address bit pattern; a second bank of registers for loading an instruction to be executed by said task processor at one or more nodes of said data tree in accordance with said destination address bit pattern; instruction load means for loading said first and second bank of registers; and a task scheduler that enables said instruction load means to load a next instruction to said first bank of registers and enables said second bank of registers to transfer an instruction loaded therein for processing by said task processor during a first time cycle domain, wherein said task scheduler further enables said instruction load means to load a next instruction to said second bank of registers and enables said first bank of registers to transfer an instruction loaded therein for processing by said task processor during a second time cycle domain that is interleaved in an alternating manner with said first time cycle domain.