Patent ID: 6791316
Filing Date: 2004-09-14
Classification: G01R

Abstract:
A semiconductor test system for testing an IC device under test (DUT), comprising:a plurality of pin cards each configuring at least one test pin and having at least a driver for supplying test vectors to a DUT, a comparator for comparing an output signal of the DUT, a phase lock loop (PLL) circuit for generating a clock signal for the test pin; a test head for storing the plurality of pin cards therein; and a load board for mounting the DUT at about a center thereof, the load board being formed on the test head and electrically connected to the plurality of pin cards; where the pin cards are arranged in a radial manner in the test head so that an inner edge of the pin card is proximate with a center of the test head and an other edge of the pin card is proximate with a wall of the test head, and the driver, the comparator and the PLL circuit are formed in an area close to the inner edge of the pin card, thereby minimizing a round-trip-delay (RTD) between the pin card and the DUT as well as establishing equi-distance therebetween.