Patent ID: 6956260
Filing Date: 2005-10-18
Classification: H01L

Abstract:
1. An integrated semiconductor memory, comprising: a plurality of memory cells in a semiconductor substrate, each said memory cell having: a storage capacitor in a trench, a trench filling above said storage capacitor, said trench filling having a first, thin insulation layer with an inner side and a first conductive filling on the inner side of the first insulation layer in said trench; a land formed of substrate material and having two mutually opposite side walls and a further side wall; a vertical selection transistor formed at said land of substrate material; word lines running along said two mutually opposite side walls of said land, and a second, thin insulation layer separating said word lines from said land; said first insulation layer of said trench filling adjoining said further side wall of said land; said first conductive filling short-circuiting said word lines on said mutually opposite side walls and electrically conductively connecting said word lines; and said second insulation layer being formed with cutouts and each two word lines running in common at said land being conductively connected to one another and to said first conductive fillings through said cutouts of said second insulation layer.