Patent ID: 9075623
Filing Date: 2015-07-07
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: an integrated circuit chip; a processing core disposed on the chip and including an issue unit and a fixed point execution unit, wherein the issue unit is configured to issue instructions to the fixed point execution unit for execution thereby; and external auxiliary execution unit (AXU) interface logic disposed on the integrated circuit chip and coupled to the issue unit, wherein the external AXU interface logic is configured to receive instructions issued by the issue unit and communicate the instructions over an external AXU interface to an off-chip AXU for execution thereby, wherein the external AXU interface has an indeterminate latency, wherein the external AXU in response to communicating an instruction to the off-chip AXU, and to signal an error in response to not receiving the response, and wherein the external AXU interface logic is configured to convert the instruction to an appropriate format for the external AXU interface by one or more of packetizing the instruction, serializing the instruction or stepping down to a lower frequency.