Patent ID: 6963966
Filing Date: 2005-11-08
Classification: G06F

Abstract:
1. A circuit implementation of a central processing unit (CPU) in a programmable logic device (PLD) comprising an array of similar programmable logic blocks and programmable routing resources interconnecting the logic blocks, the circuit implementation comprising: at least a first one of the logic blocks configured to implement an instruction register; at least a second one of the logic blocks configured to implement an accumulator pointer; at least a third one of the logic blocks configured to implement an operation block; at least a fourth one of the logic blocks comprising one or more programmable function generators configured as RAM blocks, the at least a fourth logic block being configured to implement a register file within the one or more function generators; a first set of routing resources configured to couple the first logic block to the second, third, and fourth logic blocks; and a second set of routing resources configured to couple the fourth logic block to the second and third logic blocks.