Patent ID: 6038661
Filing Date: 2000-03-14
Classification: G06F

Abstract:
A single-chip data processor comprising:a central processing unit; anda storage circuit, adapted for storing an exception code in response to an exception event, wherein the exception code corresponds to the exception event, comprising:a first portion adapted for storing the exception code corresponding to a first type of exception event that occurs synchronously with the operation of the central processing unit; anda second portion adapted for storing the exception code corresponding to a second type of exception event that occurs asynchronously with the operation of the central processing unit; andwherein the central processing unit includes:a program counter;a plurality of general purpose registers;a base register storing a vector base address, the vector base address representing a start address of a vector table corresponding to a plurality of exception handlers, wherein the vector base address is changeable in response to a program executed by the central processing unit, anda control unit which, in response to the occurrence of an exception event, writes a first instruction address into the program counter based on the vector base address and a predetermined vector offset, wherein the predetermined vector offset is assigned in advance to the exception event and provided in response to the exception event so that a first exception handler assigned to the first instruction address may be executed,wherein the central processing unit calculates a second instruction address of a second exception handler from the first exception handler by utilizing the exception code stored in the storage circuit as an address offset without the calculation effecting the plurality of general purpose registers.