Patent ID: 8804398
Filing Date: 2014-08-12
Classification: G11C,H01L

Abstract:
1. A reversible resistive memory, comprising: a plurality of reversible resistive cells, each of the reversible resistive cells including a reversible resistive film and a diode as program selector having at least a first active region with a first type of dopant for a first terminal of the diode, and a second active region with a second type of dopant for a second terminal of the diode, both active regions being fabricated from sources or drains of CMOS devices and residing in a common CMOS well, the first terminal of the diode being coupled to a first terminal of the reversible resistive film, the reversible resistive film being programmable reversibly by conducting a current flowing through the reversible resistive film, wherein the current is high and/or short duration for programming one state and low and/or long duration for programming another state; a plurality of local wordlines, each coupled to a plurality of the reversible resistive cells via the second terminal of the diodes and having a first resistivity; a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and a plurality of bitlines, each coupled to a plurality of the reversible resistive cells via the second terminal of reversible resistive film.