Patent ID: 7057310
Filing Date: 2006-06-06
Classification: G05F

Abstract:
1. A dual-output voltage regulator packaged in a 5 -pin chip providing a first terminal voltage and a second terminal voltage to double data rate (DDR) DRAM, comprising: a first regulator unit including a first transistor unit and a comparator unit, the first regulator unit receiving an input voltage and providing the first terminal voltage via the first transistor unit, the comparator unit connected to one of the pins for inputting a shutdown signal via this pin, rendering the comparator unit with shutdown function ; and a second regulator unit including a second transistor unit, a third transistor unit and a divided voltage unit, the second regulator receiving the input voltage and the first terminal voltage such that the divided voltage unit provides a plurality of reference voltages for directing the second and third transistors to output the second terminal voltage, wherein the second terminal voltage is half the first terminal voltage and the second regulator unit is capable of sourcing current and sinking current.