Patent ID: 7489035
Filing Date: 2009-02-10
Classification: H01L

Abstract:
1. An integrated circuit (IC) chip package comprising: a circuit substrate including a top surface, a bottom surface, and a plurality of bond fingers formed on the top surface; at least one IC chip disposed on the top surface of the circuit substrate and including a plurality of first input/output I/O terminals and a plurality of second I/O terminals; a decoupling capacitor extending at least partway along a defined periphery around the IC chip on the top surface of the circuit substrate; a plurality of first bonding wires electrically coupling the first I/O terminals of the IC chip to the bond fingers of the circuit substrate; and a plurality of second bonding wires electrically coupling the second I/O terminals of the IC chip to the decoupling capacitor, wherein the decoupling capacitor includes a plurality of bond pads formed thereon and a plurality of connection vias formed therein, wherein the bond pads are connected to the second bonding wires, and wherein the connection vias electrically couple the bond pads to the top surface of the circuit substrate.