Patent ID: 8933534
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. An isolation structure of high-voltage driving circuit, comprising: a P-type substrate; a P-type epitaxial layer arranged on the P-type substrate; a low-voltage region and a high-voltage region arranged on the P-type epitaxial layer; a HV-LV junction terminal region arranged between the low-voltage region and the high-voltage region; a first P-type junction isolation region arranged between the HV-LV junction terminal region and the low-voltage region, said first P-type junction isolation region being composed of a P-type buried layer and a first P-type well; a second P-type junction isolation region arranged in the interior zone of the first P-type junction isolation region and working with the first P-type junction isolation region to enclose an isolated region; a high-voltage insulated gate field effect transistor (IGFET) arranged in the isolated region and utilizing the HV-LV junction terminal region as its drift region; wherein, the high-voltage region is partially located in the isolated region, the partial high-voltage region in the isolated region comprises a first N-type deep well arranged in the P-type substrate and a first N-type well region arranged in the P-type epitaxial layer, and the N-type well region is on the top surface of the first N-type deep well; the partial high-voltage region outside of the isolated region comprises a second N-type deep well arranged in the P-type substrate and a second N-type well region arranged in the P-type epitaxial layer, and the N-type well region is the top surface of the second N-type deep well; the first N-type deep well extends towards and into the HV-LV junction terminal region, the second N-type deep well extends towards and into the HV-LV junction terminal region, wherein, the second P-type junction isolation region is a second P-type well region arranged in the P-type epitaxial layer, and the second P-type well region is arranged on the surface of the P-type substrate; the second P-type well region in a part of the second P-type junction isolation region in the HV-LV junction terminal region is substituted by a N-type well region, and the N-type well region is on the P-type epitaxial layer and is surrounded by the second P-type well region; the implanted area of the N-type well region in unit area of the second P-type junction isolation region increases gradually in the direction from the high-voltage region to the low-voltage region.