Patent ID: 8131940
Filing Date: 2012-03-06
Classification: G06F

Abstract:
1. An apparatus for processing memory transactions, comprising: a queue to store transaction identification numbers, wherein each transaction identification number corresponds to a transaction of a request for ownership of an individual memory line; and a home agent to interact with a plurality of memory agents, wherein the home agent comprises: a response monitor configured to observe a snoop response of a first memory agent, wherein the snoop response comprises a partial address of a memory line of the first memory agent; and a conflict resolver configured to establish priority of conflicting requests for memory lines of the plurality of memory agents, wherein the conflict resolver is configured to compare the partial address with a full address for at least one of the memory transactions, and wherein the partial address comprises fewer bits than the number of bits of the full address, and wherein the conflict resolver is configured to suspend conflict resolution for memory transactions which match the partial address of the memory line until the conflict resolver receives a full address for the memory line, and wherein the conflict resolver is configured to access the transaction identification numbers of the queue to enable the establishment of the priority of conflicting requests, and wherein each of the transaction identification numbers comprises fewer bits than the partial address.