Patent ID: 6242800
Filing Date: 2001-06-05
Classification: H01L

Abstract:
A semiconductor device comprising:a conductive lead frame having a main pad area, a first plurality of pins comprising at least four pins integral with said main pad area in which at least two of said pins extend from one edge of said main pad and at least another two of said pins extend symmetrically and in line with respect to said two pins from another edge of said pad that is opposite to said one edge, said integral pins being arranged to contact a heat removing substrate external to a molded housing, a second plurality of pins each separated from one another and from said main pad area;a semiconductor die having opposing surfaces and including a MOSFET die having a source electrode, a drain electrode and a gate electrode, a first one of said opposing surfaces of said semiconductor die being disposed adjacent to said main pad area and including said drain electrode in electrical contact with the bottom surface of said main pad area and in electrical contact with said first plurality of pins, a second one of said opposing surfaces of said semiconductor die including said source electrode and said gate electrode each electrically connected to a respective one of said second plurality of pins;said molded housing for encapsulating said lead frame and said semiconductor die;said first and second pluralities of pins extending outside said molded housing for external connection such that heat generated by said MOSFET die is conducted from said die to said main pad area and is then conducted by each of said first plurality of pins to the substrate external of said molded housing, said first plurality of pins being sufficiently wide to efficiently remove heat from said semiconductor die; andsaid first and second plurality of pins being downwardly bent along the side edges of said housing and terminating on a common plane to define a surface mount device.