Patent ID: 8154073
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a first conductive type, wherein the substrate has a principal surface and a backside surface, and wherein the substrate includes an inner region and a periphery region; a vertical type trench gate MOS transistor disposed in a surface portion of the principal surface in the inner region of the substrate; a Schottky barrier diode disposed in another surface portion of the principal surface in the inner region of the substrate; a plurality of trenches disposed on the principal surface of the substrate; and a poly silicon film filled in each trench of the plurality of trenches through an insulation film between the poly silicon film and an inner wall of each trench of the plurality of trenches, wherein the plurality of trenches have a stripe pattern without crossing each other so that the inner region on the principal surface of the substrate is divided into a plurality of separation regions by the plurality of trenches, the plurality of separation regions includes a first separation region and a second separation region, the first separation region includes a first conductive type region and a second conductive type layer disposed on the principal surface of the substrate, the second conductive type layer provides a channel region of the MOS transistor, the first conductive type region is disposed on a surface portion of the second conductive type layer, and adjacent to a first trench of the plurality of trenches, the first conductive type region provides a source of the MOS transistor, the poly silicon film in the first trench is coupled with a gate wiring of the MOS transistor, the plurality of trenches further includes a second trench, which is not adjacent to the first conductive type region, the poly silicon film in the second trench is coupled with a source wiring or the gate wiring of the MOS transistor, the substrate in the second separation region is exposed on the principal surface in such a manner that the substrate is coupled with the source wiring of the MOS transistor, the source wiring and the substrate in the second separation region provide a Schottky barrier in the Schottky barrier diode, the first separation region has a first width between a first two adjacent trenches of the plurality of trenches, the second separation region has a second width between a second two adjacent trenches, the plurality of trenches further includes at least two third trenches, the third trenches are connected between the second two adjacent trenches so that the second two adjacent trenches and the third trenches provide a ladder structure, the second separation region is divided into a plurality of separation portions each bounded by the at least two third trenches and the second two adjacent trenches, and the first separation region has a first length, in a direction perpendicular to the second width, the first length being on the principal surface of the substrate, the plurality of separation portions of the second separation region having a total length, in a direction perpendicular to the second width, the total length being on the principal surface of the substrate, the first length being longer than the total length.