Patent ID: 7579876
Filing Date: 2009-08-25
Classification: G11C,H03K

Abstract:
1. An integrated circuit comprising: a first transistor and a second transistor, wherein the first and second transistors are adapted to receive input signals at their gate terminals; a bias circuit coupled between the first and second transistors and a reference voltage terminal; a first resistor and a second resistor coupled to a corresponding first terminal of the first and second transistors, respectively; a first pad and a second pad coupled to the corresponding first terminal of the first and second transistors, respectively; a third transistor and a fourth transistor coupled between a supply voltage terminal and the first and second resistors, respectively, wherein the third and fourth transistors are adapted to receive a control signal at their gate terminals; and wherein the integrated circuit is adapted to provide a first signal type via the first and second pads in the event that the control signal provides a first voltage level, and wherein the integrated circuit is adapted to receive a second signal type via the first and second pads in the event that the control signal provides a second voltage level, and wherein the bias circuit and the first and second transistors are switched off in the event that the control signal provides the second voltage level.