Patent ID: 6023429
Filing Date: 2000-02-08
Classification: G11C,H03K

Abstract:
A delay circuit, comprising:a timer circuit having an input terminal adapted to receive a delay circuit input signal, a control terminal adapted to receive a control voltage, and an output terminal, the timer circuit being constructed to generate on the output terminal a timer output signal that transitions from a first output voltage to a second output voltage following a transition of the delay circuit input signal from a first input voltage to a second input voltage by a delay that is a function of the magnitude of the control voltage; anda level translation circuit having an input terminal coupled to the output terminal of the timer circuit, an output terminal, and first and second supply terminals adapted to receive first and second supply voltages, respectively, the level translation circuit being constructed to generate a delay circuit output signal that transitions from the first supply voltage to the second supply voltage responsive to a transition of the timer output signal from the first output voltage to the second output voltage.