Patent ID: 8455939
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A NAND device comprising: a source, a drain and a channel located between the source and drain; a plurality of floating gates located over the channel; a plurality of electrically conducting fins, wherein each of the plurality of electrically conducting fins is located over one of the plurality of floating gates, the plurality of electrically conducting fins comprising a material other than polysilicon; and a plurality of control gates, wherein each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins; wherein: each pair of adjacent fins is interdigitated with at least a first portion of one of the plurality of control gates; the plurality of electrically conducting fins extend upward from the plurality of floating gates; the plurality of control gates comprise a plurality of control gate rails; each of the plurality of control gate rails have a plurality of electrically conducting first portions; and each of the plurality of electrically conducting first portions comprises a strip which extends downward from one of the plurality of the control gate rails between the pair of adjacent electrically conducting fins.