Patent ID: 8111571
Filing Date: 2012-02-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality of memory cells at intersections of the word lines and the bit lines; a plurality of sense amplifiers configured to detect signal levels of the bit lines and to amplify the signal levels of the bit lines; a replica circuit comprising a replica word line, a replica bit line intersecting the replica word line, and a replica memory cell at an intersection of the replica word line and the replica bit line, the replica circuit being configured to simulate a read-out operation of the memory cell; and a timing generator configured to quantize a replica delay time from a reference time to when a signal level of the replica bit line changes, and to generate an activation time for the sense amplifier based on a quantization result.