Patent ID: 6864722
Filing Date: 2005-03-08
Classification: G06F

Abstract:
1. A phase detector operable in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising: at least one first flip flop operable to sample said second clock signal with a rising edge of said first clock signal, said at least one first flip flop thereby operating to generate a one-to-zero transition in a first sampled clock signal following coincident rising edges between said first and second clock signals; and at least one second flip flop operable to sample said second clock signal with a falling edge of said first clock signal, said at least one second flip flop operating to generate a zero-to-one transition in a second sampled clock signal following said coincident rising edges between said first and second signals, wherein a movement in one of said one-to-zero and zero-to-one transitions is operable to track a movement in said coincident rising edges corresponding to a phase difference between said first and second clock signals.