Patent ID: 6708193
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A multiplier operable to perform both signed and unsigned multiplication, said multiplier comprising:a multiplier array that includes an unsigned array portion for computing partial products of operands A and B excluding the most significant bits of such operands A and B, a second portion for computing (SA*2Nâˆ’1*Bâ€²) for unsigned multiplication and for computing (SA*(âˆ’1)*2Nâˆ’1*Bâ€²) for signed multiplication, a third portion for computing (SB*2Nâˆ’1*Aâ€²) for unsigned multiplication and for computing (SB*(âˆ’1)*2Nâˆ’1*Aâ€²) for signed multiplication, and a fourth portion for computing SA*SB for unsigned multiplication and for computing SA+SB for signed multiplication, wherein N is the number of bits in each operand, SA is the most significant bit for operand A, SB is the most significant bit for operand B, Aâ€² is the bits of operand A excluding its most significant bit, and Bâ€² is the bits of operand B excluding its most significant bit.