Patent ID: 8698301
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A semiconductor package comprising: an upper package including an upper package substrate that includes first through fourth upper sides, the upper package further including first through fourth upper semiconductor devices on the upper package substrate; and a lower package including a lower package substrate, a lower semiconductor device that is on the lower package substrate and that includes first through fourth inner sides corresponding respectively to the first through fourth upper sides of the upper package substrate, and first through fourth lower chip connection elements respectively connected to the lower semiconductor device at positions nearest the first through fourth inner sides of the lower semiconductor device, wherein a longest side of each of the first through fourth upper semiconductor devices is nearest the corresponding one of the first through fourth upper sides of the upper package substrate, and wherein each of the first through fourth lower chip connection elements electrically connects the corresponding one of the first through fourth upper semiconductor devices with the lower semiconductor device.