Patent ID: 6707166
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate which has a chip region and a pad region which is at a periphery of the chip region; a semiconductor chip which is located on the chip region and includes an electrode pad which is formed thereon; a conductive pad which is placed on the pad region; a first wall which is arranged in the pad region; a second wall which is arranged on the semiconductor chip and faces towards the first wall, wherein the second wall is formed of resin; a conductive line which electrically connects the electrode pad with the conductive pad and is arranged between the first wall and the second wall; and an encapsulating material which encapsulates the conductive line and is contained between the first and second walls, wherein an upper surface of the first wall and an upper surface of the second wall are set at a substantially same level.