Patent ID: 6788548
Filing Date: 2004-09-07
Classification: G06F,G11C,H01R,H05K

Abstract:
Adapter apparatus for adapting memory control signals of a first specification to memory control signals of a second specification, the apparatus receiving memory modules, wherein each of the memory modules comprises a plurality of data terminals and a plurality of control terminals, comprising:first data terminals and first control terminals, the first control terminals receiving memory control signals of the first specification; a first socket for receiving a first memory module with second data terminals and second control terminals, wherein the second data terminals are associated to the data terminals of the first memory module, wherein the second control terminals are associated to the control terminals of the first memory module, the second control terminals receiving memory control signals of the second specification; a second socket for receiving a second memory module with third data terminals and third control terminals, wherein the third data terminals are associated to the data terminals of the second memory module, wherein the third control terminals are associated to the control terminals of the second memory module, the third control terminals receiving memory control signals of the second specification; a signal transformation circuit with an input and an output, wherein the input is connected to the first control terminals, and wherein the output is connected to the second control terminals and to the third control terminals, the signal transformation circuit transforming the memory control signal of the first specification from the first control terminals to the memory control signal of the second specification for the second and third control terminals, wherein a first group of first data terminals is directly connected to the second data terminals, and wherein a second group of first data terminals is directly connected to the third data terminals.