Patent ID: 7999256
Filing Date: 2011-08-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first dielectric layer; a second dielectric layer disposed under the first dielectric layer; an internal circuit; first interconnects disposed in the first dielectric layer; second interconnects disposed in the second dielectric layer; and electrode pads arranged in a plurality of rows and electrically connected to the internal circuit via the first interconnects, wherein each of the electrode pads has a probe region permitting probe contact and external connection and a non-probe region prohibiting probe contact but permitting external connection, none of the first interconnects formed in the first dielectric layer are disposed under and vertically aligned with the probe region, each of the first interconnects formed in the first dielectric layer are disposed under and vertically aligned with the non-probe region, each of the second interconnects is disposed directly under the probe region and the non-probe region, no dielectric layer having interconnects is disposed between the electrode pads and the first dielectric layer.