Patent ID: 8432741
Filing Date: 2013-04-30
Classification: G11C

Abstract:
1. A nonvolatile memory device comprising: a memory cell array comprising at least one dummy memory cell connected to at least one dummy wordline, a NAND string comprising a plurality of memory cells connected in series between a string selection transistor and a ground selection transistor through the at least one dummy memory cell, a plurality of wordlines connected to the plurality of memory cells, a string selection line connected to the string selection transistor, and a ground selection line connected to the ground selection transistor; a row selection circuit coupled to the memory cell array through the string selection line, the ground selection line and the plurality of wordlines, and configured to provide wordline voltages to the plurality of wordlines based on address signals; and a voltage generator configured to generate the wordline voltages; wherein, during a read-out operation mode of the nonvolatile memory device, a dummy read-out voltage is applied to the at least one dummy wordline, a read-out voltage is applied to unselected wordlines connected to unselected memory cells in the NAND string and a selection voltage is applied to a selected wordline connected to a selected memory cell to be read out, the dummy read-out voltages having a first voltage level and the read-out voltage having a second voltage level greater than the first voltage level, the selection voltage being lower than the read-out voltage.