Patent ID: 8166282
Filing Date: 2012-04-24
Classification: G06F

Abstract:
1. A system, comprising: a memory subsystem coupled to a processor; the processor having N thread units to support speculative multithreading; and a register versioning table coupled to the thread units, the register versioning table having N×R entries, the register versioning table to indicate, for each of the N thread units, whether the thread unit has written a value for each of R architectural registers; wherein each thread unit includes a validation buffer to store speculatively precomputed live-in values; wherein each thread unit further includes a local register file for the R architectural registers, wherein each thread unit determines whether the precomputed live-in values match local register file values, if such values match, the precomputed live-in values are marked valid; and a global register file to hold the committed state for each of the R architectural registers, wherein the global register file is accessed by a thread unit when the thread unit performs a read to a register not available in its local register file and no less-speculative thread has written the register without committing it.