Patent ID: 8477483
Filing Date: 2013-07-02
Classification: H01L,H03H,Y10T

Abstract:
1. An electronic component comprising: a component obtained by separating a mother substrate including a plurality of components to define a plurality of individual devices, the component including a conductive layer, an insulating layer, a first plating layer, an external terminal, and a plurality of power supply lines, the conductive layer including an electrode and a plurality of pads, the insulating layer being disposed on a surface of the mother substrate so as to cover a portion of the conductive layer and including pad openings each surrounding a corresponding one of the plurality of pads so as to expose at least a central portion of the pad, the first plating layer being electrolytically plated in each of the pad openings of the insulating layer, the external terminal being disposed on the first plating layer, the power supply lines being arranged to apply power to the plurality of pads exposed through the pad openings when electrolytic plating is performed; wherein in the mother substrate before being separated into the plurality of individual devices, at least one of the plurality of pads provided at a side of one of two neighboring devices of the plurality of individual devices is electrically connected to at least two of the plurality of pads provided at a side of the other of the two neighboring devices via different power supply lines; the different power supply lines are separated from each other on a boundary between the two neighboring devices; in the component, the plurality of power supply lines are disposed along a divided surface formed when the plurality of components are separated from the mother substrate so as to be separated from one another; in the mother substrate before being separated into the plurality of individual devices, the insulating layer includes a boundary opening extending along the boundary between the two neighboring devices; a second plating layer is disposed on the plurality of power supply lines exposed through the boundary opening by the electrolytic plating; and the second plating layer is arranged along a divided surface formed when the plurality of individual devices are separated from the mother substrate.