Patent ID: 7305534
Filing Date: 2007-12-04
Classification: G06F

Abstract:
1. A data processing apparatus having a secure domain and a non-secure domain, in the secure domain devices of the data processing apparatus having access to secure data which is not accessible in the non-secure domain, the data processing apparatus comprising: a device bus; a plurality of devices coupled to the device bus, at least one of the devices being operable in a plurality of modes, including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain; a memory coupled to the device bus and operable to store data required by the devices, the memory divided between secure memory for storing secure data and non-secure memory for storing non-secure data, each of the devices being operable to issue onto the device bus a memory access request when access to an item of data in the memory is required, each memory access request pertaining to either said secure domain or said non-secure domain; and partition checking logic coupled to the device bus and operable whenever a memory access request as issued by any of the devices pertains to said non-secure domain to detect if the memory access request is seeking to access the secure memory, and upon such detection to prevent the access specified by that memory access request.