Patent ID: 7972904
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. A wafer level packaging method comprising: providing a wafer including a plurality of bumps disposed on a surface of the wafer; placing a dielectric tape on a mold plate; laminating the wafer and the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and the bumps be embedded in the dielectric tape; removing the mold plate; and flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces of the bumps and the flattened surface of the dielectric tape are coplanar; wherein the mold plate has a plurality of holes to accommodate the individual bumps; wherein the bumps with a plurality of extruded tips penetrate through the dielectric tape and the extruded tips are accommodated in the holes during the laminating step; and wherein the bumps during the laminating step have a height greater than the thickness of the dielectric tape but smaller than the total thickness of the thickness of the dielectric tape plus the depth of the corresponding holes.