Patent ID: 8164189
Filing Date: 2012-04-24
Classification: H01L

Abstract:
1. A multi-chip semiconductor device comprising: a wiring substrate having an opening formed in a central portion thereof, a plurality of first electrode terminals arranged and formed on a front surface thereof near the opening, a plurality of second electrode terminals arranged and formed on the front surface of a peripheral portion thereof and a plurality of wirings used to electrically connect corresponding ones of the plurality of first and second electrode terminals to one another and formed on the front surface, a first semiconductor chip having a plurality of first bump electrodes arranged and formed on a front surface thereof, a second semiconductor chip which has a plurality of second bump electrodes containing a plurality of bump electrodes for connection with an exterior arranged and formed on a front surface thereof and is arranged with the front surface thereof set to face the front surface of the first semiconductor chip with the wiring substrate disposed therebetween, those of the plurality of second bump electrodes other than the plurality of bump electrodes for connection with the exterior being electrically connected to the plurality of first bump electrodes of the first semiconductor chip in the opening of the wiring substrate and the plurality of second bump electrodes for connection with the exterior being electrically connected to the plurality of first electrode terminals of the wiring substrate; a package substrate which has a plurality of electrodes for connection with the exterior formed on a front surface thereof, a concave portion formed on a back surface thereof to receive the second semiconductor chip and a plurality of third electrode terminals electrically connected to the plurality of electrodes for connection with the exterior and formed on the back surface of an area other than the concave portion, the second semiconductor chip being received in the concave portion and adhered thereto; and a plurality of third bump electrodes which electrically connect the third electrode terminals of the package substrate with the plurality of second electrode terminals of the wiring substrate.