Patent ID: 8569757
Filing Date: 2013-10-29
Classification: H01L

Abstract:
1. A device with amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure, the device comprising: a substrate; a dielectric layer on the substrate, the dielectric layer being associated with a first surface; one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions being associated with a second surface and including an n-type a-Si layer, a diffusion barrier layer, and a conductive layer, the n-type a-Si layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the conductive layer, the second surface consisting of n-type a-Si and being substantially co-planar with the first surface; an i-type a-Si layer overlying the surface of the n-type a-Si and the dielectric layer; a p-type a-Si layer overlying the i-type a-Si layer; an aluminum oxide layer on the p-type a-Si layer; and at least one control gate overlying the aluminum oxide layer.