Patent ID: 9103919
Filing Date: 2015-08-11
Classification: G01T,G06F,G16H

Abstract:
1. A method for transmitting register contents of a CT detector with hierarchical hardware structure between a central control and hardware components connected thereto, each with at least one field-programmable gate array (FPGA), wherein the FPGAs are divided into at least two hardware levels and, during ongoing readings of the CT detector, write and readout processes of register contents are performed cyclically beyond a hierarchy level and asynchronously to the readings, write and readout commands between the central control and the first hierarchy level of the FPGAs are executed, the method comprising: forming the first hierarchy level by a control unit which contains a register table for the read-out register contents of FPGAs lying relatively lower down in the hierarchy and a register buffer for register contents to be written; forwarding to the next respective hierarchy level, with each respective new reading, new register contents arriving during respective preceding reading from the central control at the control unit for FPGAs lying relatively lower down in the hierarchy; re-entering into the register table of the control unit, with each respective new reading, the register contents of all FPGAs lying relatively lower down in the hierarchy; and reading out, in an event of a readout command transferred asynchronously from the central control, the register contents exclusively from the register table.