Patent ID: 6830988
Filing Date: 2004-12-14
Classification: H01L

Abstract:
A method of forming an isolation structure for an integrated circuit, the method comprising:providing a single crystalline silicon substrate; forming a subsurface vertical isolation layer in the silicon substrate; forming an oxidation mask on an upper surface of the silicon substrate to expose selected regions of the silicon substrate; etching the selected regions of the silicon substrate to provide a plurality of spaced-apart raised precursor active device regions of the silicon substrate that are separated by a plurality of sunken precursor isolation regions of the silicon substrate; forming a layer of polysilicon over the oxidation mask and over exposed surfaces of the sunken precursor isolation regions; forming a layer of silicon nitride over the layer of polysilicon; forming a layer of silicon oxide over the layer of silicon nitride; anisotropically etching the layer of silicon oxide to stop on the layer of silicon nitride, thereby forming oxide spacer structures adjacent to the raised precursor active device regions, the oxide spacer structures being separated from the raised precursor active device regions by intervening silicon nitride and polysilicon; removing exposed regions of the layer of silicon nitride to reveal polysilicon overlying the raised precursor active device regions and the sunken precursor isolation regions; removing the oxide spacer structures; oxidizing the sunken precursor isolation regions to grow silicon oxide that extends into contact with the vertical subsurface isolation layer and such that recesses are created between the grown silicon oxide and the raised precursor active device regions, the oxidizing step causing polysilicon on the upper surface of the raised precursor active device regions to be converted to silicon oxide; depositing silicon oxide over the oxidation mask on the raised precursor active device regions and to fill the recesses between the grown silicon oxide and the raised precursor active device regions; and planarizing the deposited silicon oxide to stop on the oxidation mask.