Patent ID: 6747507
Filing Date: 2004-06-08
Classification: G05F

Abstract:
A bias generator circuit comprising:a first transistor; a second transistor having a first end coupled to a first end of the first transistor, a second end coupled to a second end of the first transistor, and a gate coupled to a gate of the first transistor; an amplifier having a first input coupled to the second end of the first transistor and to the gate of the second transistor, and a second input coupled to a control voltage node; a third transistor having a first end coupled to the second end of the first transistor; a fourth transistor having a first end coupled to a second end of the third transistor and having a gate coupled to an output of the amplifier; a fifth transistor; a sixth transistor having a first end coupled to a first end of the fifth transistor, a second end coupled to a second end of the fifth transistor, and a gate coupled to a gate of the fifth transistor; a seventh transistor having a first end coupled to the second end of the fifth transistor; and an eighth transistor with a first end coupled to a second end of the seventh transistor and having a gate coupled to a gate of the fourth transistor; and wherein the first, second, fifth, and sixth transistors are PMOS transistors; and the third, fourth, seventh, and eighth transistors are NMOS transistors.