Patent ID: 6205071
Filing Date: 2001-03-20
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cells arranged alignedly in at least one column;a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair; andsense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state,wherein said sense amplifier activation control circuitry comprises:a power supply line for supplying a power supply voltage driving said sense amplifier,a sense amplifier drive transistor connected between said sense amplifier and said power supply line, for coupling said power supply line and said sense amplifier to drive said sense amplifier when conductive, anda sense amplifier drive signal generation circuit responsive to said sense amplifier activation signal for applying a sense amplifier drive signal to said sense amplifier drive transistor to render said sense amplifier drive transistor conductive, and responsive to said write operation activation signal for changing a voltage level of said sense amplifier drive signal to reduce an on-resistance of said sense amplifier drive transistor.