Patent ID: 6207507
Filing Date: 2001-03-27
Classification: G11C,H01L

Abstract:
A method of manufacturing a multi-level flash memory cell a semiconductor substrate, said method comprising the steps of:(a) forming a deep n-well in said semiconductor substrate;(b) forming a p-well within said deep n-well;(c) forming a gate oxide layer on semiconductor substrate;(d) forming a first polysilicon layer over said gate oxide layer;(e) patterning and etching said first polysilicon layer and said gate oxide layer to form an intermediate structure within the width of said p-well;(f) forming a first dielectric layer over said intermediate structure;(g) depositing a second polysilicon layer over said first dielectric layer;(h) etching back said second polysilicon layer to form two polysilicon sidewall spacers adjacent said intermediate structure;(i) forming source and drain regions adjacent said polysilicon sidewall spacers;(j) forming a second dielectric layer over said semiconductor substrate;(k) forming a third polysilicon layer over said second dielectric layer; and(l) patterning and etching said third polysilicon layer and said second dielectric layer to form a control gate that is insulated from and extends at least over and between said two polysilicon sidewall spacers.