Patent ID: 7596671
Filing Date: 2009-09-29
Classification: G06Q,G07F

Abstract:
1. A computer system comprising: a processor; a memory controller; a memory; a memory bus communicating with the memory and the memory controller; and a memory management module installed on the memory bus between the memory controller and the memory, wherein the memory management module is configured to: deny access of the memory controller to a first portion or all of the memory when one or more of a payment condition has not been met or a tampering condition has been met, wherein the first portion includes memory addresses that are inaccessible by the memory controller; eavesdrop on at least one of the memory bus, a DRAM, a Southbridge, or a Northbridge for an out-of-compliance memory signal, wherein the out-of-compliance memory signal includes a memory access signal having an address that is within the first portion; and if the out-of-compliance memory signal is received, the memory management module is further configured to issue a reboot command, and upon reboot, enforce a memory limitation by informing BIOS that only a second portion of the memory is available, wherein the memory addresses of the second portion and the memory addresses of the first portion are mutually exclusive; and if the memory management module notices memory has been limited by the BIOS and if the memory management module discovers the out-of-compliance memory si-lal in which the BIOS has failed to enforce the memory limitation, the memory management module is further configured to instruct the system to increase a number of memory addresses within the first portion; wherein the memory management module is further configured to, upon reboot, initialize the on-board dynamic memory to discover information related to a physical memory, the information related to the physical memory comprising: an amount of currently-installed physical memory; and a difference between the amount of currently-installed physical memory and a previously-installed physical memory; wherein the memory management module comprises: