Patent ID: 8501575
Filing Date: 2013-08-06
Classification: H01G,H05K,Y10T

Abstract:
1. A method of forming a multilayer capacitor within a laminated circuit packaging structure, the method comprising: a) providing an assembly comprising a dielectric substrate having parallel traces of electrically conductive material formed on a major surface thereof and a layer of photoimageable dielectric laminated to said major surface, covering said major surface and said parallel traces of electrically conductive material; b) exposing and etching said photoimageable dielectric above said parallel traces of electrically conductive material to reveal said parallel traces of electrically conductive material through openings in said photoimageable dielectric defined by individual traces of electrically conductive material; c) plating copper onto said revealed parallel traces of electrically conductive material, filling said openings to a thickness that is coplanar with a top surface of a remaining portion of said layer of photoimageable dielectric; d) exposing and etching said photoimageable dielectric a second time between said copper-plated parallel traces of electrically conductive material to create openings defined by adjacent copper-plated parallel traces of electrically conductive material; and e) dispensing a capacitor-forming material into said openings defined by adjacent copper-plated parallel traces of electrically conductive material, filling said openings to form a vertically-oriented multilayer capacitor, the capacitance thereof being proportional to the thickness of said photoimageable dielectric.