Patent ID: 6624014
Filing Date: 2003-09-23
Classification: H01L

Abstract:
A process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions, comprising:providing a substrate comprising a P well region, a N well region and a shallow trench isolation; forming at least a gate on each of the P well region and the N well region; forming a diffusion source layer on the substrate by performing a plasma enhanced chemical vapor deposition (PECVD); implanting P type ions in the diffusion source layer on the N well region to form a P type diffusion source layer; implanting N type ions in the diffusion source layer on the P well region to form a N type diffusion source layer; forming a spacer at each sidewall of the gate; implanting P type ions in the N well region and N type ions in the P well region in the substrate; and performing a thermal process to diffuse ions from the diffusion source layer to the substrate to form a N type source/drain region and a N type ultra shallow junction in the N well region and a P type source/drain region and a P type ultra shallow junction in the P well region.