Patent ID: 7224024
Filing Date: 2007-05-29
Classification: G11C,H01L

Abstract:
1. A device, comprising: a vertical transistor having a source region, a drain region, and a body region therebetween, and further having a first side and a second side; a gate opposing the body region on the first side of the vertical transistor; and a floating body back gate opposing the body region on the second side of the vertical transistor, wherein the floating body back gate has a thickness approximately equal to the thickness of the gate, wherein the gate is connected to a word line to selectively provide the gate with at least a first word line potential and a second word line potential during memory cell operation, the drain region is connected to a bit line to selectively provide the drain region with at least a first bit line potential and a second bit line potential during memory cell operation, the source region is connected to a source line to selectively provide the source region with at least a first source line potential and a second source line potential during memory cell operation, and a fixed potential is applied to the floating body back gate during memory cell operation.