Patent ID: 6323091
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device on a semiconductor substrate including a memory region having programmed cells and unprogrammed cells, and a peripheral region having transistors of a first conductivity type, and transistors of second conductivity type opposite to said first conductivity type, said method comprising the steps of:forming a gate insulation layer on said semiconductor substrate;forming gate structures on said gate insulation layer;performing a first ion implantation of said first conductivity type to form LDD structures of said first conductivity type in said memory region and said peripheral region;forming a mask which covers said unprogrammed cells, and said transistors of said first conductivity type, and exposes a part of said programmed cells;performing a second ion implantation of said second conductivity type by using said mask to form LDD structures of said second conductivity type in said transistors of said second conductivity type, and said part of said programmed cells;forming spacers on side walls of said gate structures;performing a third ion implantation of said first conductivity type by using said gate structures and said spacers to form source regions and drain regions in said programmed cells, said unprogrammed cells, and said transistors of said first conductivity type; andperforming a fourth ion implantation of said second conductivity type to form source regions and drain regions in said transistors of said second conductivity.