Patent ID: 6055285
Filing Date: 2000-04-25
Classification: G06F,H04J

Abstract:
A synchronization circuit which controls an interface between a write controller and a read controller in a buffer system, the write controller providing a write pointer in synchronism with a first clock and the read controller providing a read pointer in synchronism with a second clock, the synchronization circuit comprising:a first latch which receives the write pointer in synchronism with the first clock and which generates a latched write pointer;a second latch which receives the latched write pointer and which generates a synchronized write pointer in synchronism with the second clock;a third latch which receives the read pointer in synchronism with the second clock and which generates a latched read pointer;a fourth latch which receives the latched read pointer and which generates a synchronized read pointer in synchronism with the first clock; andsynchronization logic which generates first, second, third and fourth latch enable signals which control the first, second, third and fourth latches, respectively, the synchronization logic timing the first latch enable signal with respect to the second latch enable signal to assure that the latched write pointer is stable with respect to the second clock signal before the second latch is enabled to generate the synchronized write pointer, the synchronization logic timing the first latch enable signal with respect to the second latch enable signal to assure that the second latch has received a previous value of the latched write pointer before enabling the first latch to generate a new value of the latched write pointer, the synchronization logic timing the fourth latch enable signal with respect to the third latch enable signal to assure that the latched read pointer is stable with respect to the first clock signal before the fourth latch is enabled to generate the synchronized read pointer, the synchronization logic timing the third latch enable signal with respect to the fourth latch enable signal to assure that the fourth latch has received a previous value of the latched read pointer before enabling the third latch to generate a new value of the latched read pointer.