Patent ID: 6067267
Filing Date: 2000-05-23
Classification: G11C

Abstract:
A FIFO architecture, comprising:a first FIFO stack including first and second subarrays of registers;a second FIFO stack including third and fourth subarrays of registers;first, second, third and fourth multiplexers for receiving output from the first, second, third and fourth subarrays, respectively, and for outputting the same;first, second, third and fourth read pointers associated with said first, second, third and fourth subarrays, respectively;a fifth multiplexer connected to each of the first and second multiplexers and receiving output from the first FIFO stack via the first and second multiplexers;a sixth multiplexer connected to each of the third and fourth multiplexers and receiving output from the second FIFO stack via the third and fourth multiplexers; anda seventh multiplexer connected to each of the fifth and sixth multiplexers and receiving output from both the first and second FIFO stacks via the fifth and sixth multiplexers, respectively.