Patent ID: 6576946
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A semiconductor device comprising capacitor cells, bit lines, word lines and MOS transistors in a memory cell area over a semiconductor substrate wherein;gates of said MOS transistors are comprised of said word lines; said capacitor cell is electrically connected to either a source area or a drain area of said MOS transistor; said capacitor cell comprises a first electrode and a second electrode formed over said first electrode; said first and second electrodes are separated by a dielectric layer; said first electrode comprises a bottom body and a plurality of wall-shaped bodies, each one of said plurality of wall-shaped bodies having a bottom end electrically connected to said bottom body and a top end which does not physically connect to the top end of an adjacent wall-shaped body; said bottom bodies of each capacitor cell are formed on a first insulator over said MOS transistors; insulator strips are formed between said adjacent bottom bodies on said first insulator; said bottom body is surrounded by said insulator strip; said adjacent bottom bodies are electrically separated by said insulator strip, wherein; the top surface of said bottom bodies and the top surface of said insulator strips are at the same level; said wall-shaped bodies parallel to each other are arranged in a direction parallel to an arrangement of said word line.