Patent ID: 6353997
Filing Date: 2002-03-12
Classification: H05K,Y10T

Abstract:
A layer build-up process for forming a multi-layer board, comprising the steps of:providing a conductive substrate; half-etching a portion of the conductive substrate to form a plurality of bumps; filling the space between the bumps with a dielectric material such that only top surfaces of the bumps are exposed; half-etching the bumps to reduce their height so that the top surfaces of the bumps is at a level below a top surface of the dielectric layer; applying joining material to the top surface of each bump; providing a core substrate having one or more insulation layers and a plurality of first wiring layers with each insulation layer sandwiched between two neighboring wiring layers; pressing the conductive substrate and the core substrate together such that the bumps on the conductive substrate are electrically connected to the first wiring layer through the joining material; and patterning the conductive substrate to form a second wiring layer such that the second wiring layer is electrically connected to the first wiring layer through the bumps, wherein the second conductive layer, the bumps and the dielectric material layer together constitute a composite layer unit.