Patent ID: 9021413
Filing Date: 2015-04-28
Classification: G06F,H01L

Abstract:
1. An integrated circuit of matched devices, the integrated circuit comprising: a) N main-devices by each composed of 4×K sub-devices, wherein said sub-devices form K device arrays, wherein each of said device arrays comprises four sub-device groups arrayed symmetrically around a vertical axis and a horizontal axis, wherein each of said sub-device groups comprises N sub-devices arrayed with equal distance along a direction of said vertical axis, wherein K and N are integers, and wherein N is at least two; b) metal lead wires arrayed in parallel along said vertical axis and with equal distance, wherein said metal lead wires lead out said main-devices; c) a common connecting wire that connects common nodes of said sub-devices together; and d) wherein said 4×K sub-devices composed of four sub-devices of one of said device arrays is arrayed symmetrically around said vertical and horizontal axes, and other corresponding four sub-devices of remaining of said K device array, are coupled in series or in parallel to form one of said N main-devices that is configured to be connected to a peripheral circuit through said metal lead wires.