Patent ID: 7827428
Filing Date: 2010-11-02
Classification: G06F,H04J,H04Q

Abstract:
1. A system, comprising: a plurality of processor chips, each processor chip in the plurality of processor chips having heartbeat signal generation logic; and at least one communication link between the plurality of processor chips, wherein: the at least one communication link couples the plurality of processor chips into a computing cluster, heartbeat signal generation logic of a first processor chip synchronizes a first heartbeat signal transmitted by the first processor chip with second heartbeat signals of other second processor chips in the plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time, and the first processor chip in the plurality of processor chips generates an internal system clock signal based on the first heartbeat signal such that, through synchronization of the first heartbeat signal with the second heartbeat signals of the other second processor chips of the plurality of processor chips, the internal system clock signals of each processor chip of the plurality of processor chips are synchronized.