Patent ID: 6342414
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method of forming a semiconductor structure comprising the steps of:forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures; removing the temporary gate to form a recess with a bottom and sidewalls between the dielectric structures; depositing a high dielectric constant (high K) gate dielectric layer in the recess on the bottom and sidewalls; depositing a low temperature silicidation metal over the semiconductor structure including the recess; removing the low temperature silicidation metal except for a portion in the recess; depositing silicon over the semiconductor structure; annealing to cause the silicon and the portion of the low temperature silicidation metal in the recess to interact to form a self-aligned low temperature metal silicide gate; and planarizing the semiconductor structure to remove the silicon.