Patent ID: 6012137
Filing Date: 2000-01-04
Classification: G06F

Abstract:
An application specific integrated circuit for performing digital audio/video processing, comprisinga video decoder for decoding compressed video data delivered thereto;an audio decoder for decoding compressed audio data delivered thereto;a memory interface for delivering data to a dynamic random access memory for storing video and audio data, and for retrieving data from said dynamic random access memory; anda central processing unit connected to said video decoder, said audio decoder, and said memory interface for controlling computations performed thereby, said central processing unit comprising:an instruction memory storing instructions, said instruction memory having an output for delivery of a current instruction to said central processing unit to control operations thereof,a register file storing data for use in digital computations performed by said central processing unit, said register file having an input through which data can be stored into registers thereof, and an output through which data stored in registers thereof is delivered, said register file selecting a register to receive data from said input and deliver data to said output in response to said current instruction output by said instruction memory,a datapath connected to said output of said register file including components for performing digital computations upon data delivered through said output of said register file, and connected to said input of said register file for storing results of computations into said register file,a program counter having an output connected to said instruction memory for delivering a current memory address thereto to cause said instruction memory to select an instruction therein for delivery to said central processing unit, anda multiplexer, an output of said multiplexer being connected to said program counter for delivering an instruction memory address thereto, a first input of said multiplexer connected to said output of said register file, a second input of said multiplexer being derived from said current instruction output from said instruction memory and said current memory address output from said program counter, said multiplexer being responsive to said current instruction output from said instruction memory to deliver digital signals received at either said first or said second inputs thereof to said program counter.