Patent ID: 6211864
Filing Date: 2001-04-03
Classification: H04N

Abstract:
An apparatus for compressing a digital image into a memory module, comprising:a) a processor module processing blocks of pixel values from the digital image and generating data packets therefrom;b) a counter electrically coupled to the processor module, the counter determining the number of bits in each data packet generated by the processor module and accumulating the number of bits to yield a current memory total;c) a comparator electrically coupled to the counter, the comparator determining for each data packet whether the sum of the current memory total and the number of counted bits in the data packet exceeds a reference signal representing the cumulative memory allocation based on the total number of processed blocks of pixel values for the digital image; andd) an output device electrically coupled to the processor module output and comparator, the output device writing the data packet generated by the first processor module to a memory module if the sum of the current memory total and the number of counted bits does not exceed the cumulative memory allocation.