Patent ID: 6731513
Filing Date: 2004-05-04
Classification: B81B,G02B,H01L

Abstract:
A shielded multi-conductor interconnect bus comprising:a substrate; a first dielectric layer overlying and supported by at least a portion of said substrate; a plurality of parallel electrically conductive lines formed on said first dielectric layer, wherein there is no intervening electrically conductive layer between said plurality of parallel electrically conductive lines and said substrate; a plurality of parallel electrically conductive walls formed on said first dielectric layer, each said electrically conductive wall including an upper section extending vertically above the level of said electrically conductive lines; and an electrically conductive shield formed in a spaced relation above said electrically conductive lines and in contact with said upper sections of said electrically conductive walls; wherein said electrically conductive lines and said electrically conductive walls are arranged in pattern wherein one of said electrically conductive walls is located between sets of said electrically conductive lines, each said set of electrically conductive lines including at least one of said electrically conductive lines.