Patent ID: 8074059
Filing Date: 2011-12-06
Classification: G06F

Abstract:
1. A system comprising at least one element of hardware for performing deterministic processing, the system comprising: a processing entity adapted to execute a plurality of instructions including a first one instruction and at least another one instruction in a first execution; a component adapted to restrict a time of execution of the first one instruction of the plurality of instructions according to a predetermined time of execution for the first one instruction, wherein the predetermined time of execution for the first one instruction comprises a constant value by the processing entity, wherein the constant value includes a maximum execution time of execution for the first one instruction; wherein the component is further adapted to restrict a time of execution of the another one instruction of the plurality of instructions according to a predetermined time of execution for the another one instruction, wherein the time of execution for the another one instruction comprises a constant value by the processing entity; wherein the processing entity executes the plurality of instructions in a constant total time of execution, based on the constant value of the time of execution for the first one instruction and the constant value of the time of execution for any of the another one instruction; and wherein the component is further adapted to adjust the constant total time of execution of the plurality of instructions including the first one instruction and any of the another one instruction for one or more executions after the completion of the first execution to be a same constant value over the one or more executions after the completion of the first execution.