Patent ID: 8923053
Filing Date: 2014-12-30
Classification: G11C,H01L

Abstract:
1. A method of erasing at least one selected sub block of a nonvolatile memory device, the method comprising: allowing each of at least one string select lines to float, the nonvolatile memory device including the at least one string select line, the nonvolatile memory device including a memory cell array including a substrate and a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to the substrate, each of the plurality of memory cells connected to at least one word line, each of the plurality of memory blocks further including at least one string select transistor connected to the at least one string select line, at least one ground select transistor connected to at least one ground select line, and at least one separator, connected to at least one dummy word line, separating the memory cells into a plurality of sub blocks; applying a first voltage to the at least one word line of the at least one selected sub block; applying a second voltage to the at least one dummy word line; allowing each of the at least one ground select lines to float; and applying an erase voltage to the substrate to erase the at least one selected sub block.