Patent ID: 6818507
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device including a memory region that includes a non-volatile memory device and a logic circuit region that includes a peripheral circuit for the non-volatile memory device, the method comprising:forming a semiconductor substrate having a conductive layer that is to become a word gate of the non-volatile semiconductor device; forming a stopper layer above the conductive layer; forming sidewall-like control gates on both side surfaces of the conductive layer through ONO films above a semiconductor layer of the memory region; forming a gate electrode of a dielectric gate field effect transistor above the semiconductor layer of the logic circuit region; forming a dielectric layer over an entire surface of the memory region and the logic circuit region of the semiconductor substrate; forming a polishing restricting layer uniformly above a part of the dielectric layer in the logic circuit region; and polishing the dielectric layer uniformly over both the memory region and the logic circuit region such that the stopper layer within the memory region is exposed, and the gate electrode within the logic circuit region is not exposed.