Patent ID: 6362612
Filing Date: 2002-03-26
Classification: G05F

Abstract:
A bandgap voltage reference circuit for providing a stable reference output voltage, said bandgap voltage reference circuit comprising:(a) an operational amplifier having a first input terminal, a second input terminal and an output terminal; (b) a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is connected to the first input terminal of the operational amplifier; (c) a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is connected to the second input terminal of the operational amplifier; (d) a first bipolar transistor having a base terminal, an emitter terminal, and a collector terminal, wherein the base terminal of the first bipolar transistor is connected to the collector terminal of the first bipolar transistor, and wherein the emitter terminal of the first bipolar transistor is connected to the second terminal of the first resistor; (e) a second bipolar transistor having a base terminal, an emitter terminal, and a collector terminal, wherein the base terminal of said second bipolar transistor is connected to the collector terminal of said second bipolar transistor, and wherein the collector terminal of said second bipolar transistor is connected to the collector terminal of said first bipolar transistor, and wherein the emitter terminal of the second bipolar transistor is connected to the second terminal of the second resistor; (f) a first CMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the first CMOS transistor is connected to the output terminal of the operational amplifier, and wherein the source terminal of the first CMOS transistor is connected to a voltage supply, and wherein the drain terminal of the first CMOS transistor is connected to the first terminal the operational amplifier; (g) a second CMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the second CMOS transistor is connected to the output terminal of the operational amplifier, and wherein the source terminal of the second CMOS transistor is connected to the voltage supply, and wherein the drain terminal of the second CMOS transistor is connected to the second terminal the operational amplifier; (h) a third CMOS transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the third CMOS transistor is connected to the output terminal of the operational amplifier, and wherein the source terminal of the third CMOS transistor is connected to the voltage supply; (i) a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is connected to the drain terminal of the third CMOS transistor; and (j) a third bipolar transistor having a base terminal, an emitter terminal, and a collector terminal, wherein the base terminal of the third bipolar transistor is connected to the collector terminal of the third bipolar transistor, and wherein the emitter terminal of the third bipolar transistor is connected to the second terminal of the third resistor.