Patent ID: 6090649
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A method of fabricating heterojunction field effect transistor comprising the steps of:forming a buffer layer on a semiconductor substrate;forming a channel layer on the buffer layer;forming a spacer layer on the channel layer;forming a carrier supply layer on the spacer layer;forming a Schottky barrier layer on the carrier supply layer;forming an etching stopper layer on the Schottky barrier layer;forming a cap layer containing a high concentration dopant on the etching stopper layer;forming a source electrode and a drain electrode apart from each other on the cap layer;forming a first recess in a separate region sandwiched between the source and drain electrodes of the cap layer by removing the cap layer by etching and forming a second recess in the etching stopper layer exposed by removal of the cap layer, thereby exposing the Schottky barrier layer below the etching stopper layer; andforming a gate electrode partly on a surface of the Schottky barrier layer exposed in the recess and partly on the stopper layer exposed in the recess.