Patent ID: 8264025
Filing Date: 2012-09-11
Classification: H01L

Abstract:
1. A nonvolatile memory device comprising: an active region of a semiconductor substrate defined between opposing device isolation layer segments; a tunnel insulating structure disposed on an upper surface of the active region; a charge storage structure comprising a lower charge storage structure disposed on the tunneling insulating structure and an upper charge storage structure disposed on the upper charge storing structure, wherein a width of the charge storage structure is less than or equal to a width of an upper surface of the active region; wherein each one of the opposing device isolation layer segments comprises an insulating layer filling a trench separating the active region from an adjacent active region of the semiconductor substrate, wherein the insulating layer comprises: a gate interlayer dielectric layer conformally disposed over an upper surface of the upper charge storage structure, the spacers, and the recessed upper surface; and a control gate electrode disposed on the gate interlayer dielectric layer.