Patent ID: 7075838
Filing Date: 2006-07-11
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array connected to one of a plurality of wordlines and a plurality of bitline pairs; a sense amplifier amplifying data read from the memory cell array; a control circuit controlling writing/reading of data to/from the memory cell array; a row decoder decoding an address signal and outputting a decoded signal to select one of the plurality of wordlines; a bitline-pair voltage setting circuit setting a voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode; and a wordline driver setting low-level voltages of the plurality of wordlines to a wordline test voltage in the test mode, wherein the wordline test voltage can be set to be different from the low-level voltages of the plurality of wordlines in a normal operation mode, wherein the wordline driver comprises: an odd wordline driver connected to an odd wordline; and an even wordline driver connected to an even wordline, wherein the odd wordline driver and the even wordline driver can independently set the low-level voltages of the odd wordline and the even wordline, respectively, in the test mode.