Patent ID: 6243302
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A synchronous memory device, comprising:a plurality of pipelatch circuits storing data as pull-up and pull-down signals, transferring the stored data to pull-up and pull-down lines and producing initialization signals to initialize the pull-up and pull-down lines in response to a pipe count signal;common pull-up and pull-down lines coupled to the pull-up and pull-down lines in response to the pipe count signal and the initialization signals;initialization means for supplying a power supply to the pull-up and pull-down lines in response to a reset signal, the pipe count signal and the initialization signals;an output buffer outputting the data transferred by the common pull-up and pull-down lines; anda precharging mean for precharging the pull-up and pull-down lines and the common pull-up and pull-down lines in response to an output signal from the output buffer, wherein the common pull-up and pull-down lines is precharged to a ground voltage level.