Patent ID: 8921898
Filing Date: 2014-12-30
Classification: H01L

Abstract:
1. A device, comprising: an array of a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each column comprises an N-well region and at least one P-well region, said N-well region and said at least one P-well region extending between a first end of the column and a second end of the column; at least one N-well contact area, each N-well contact area electrically contacting at least one of said N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first end and the second end of the column; and at least one P-well contact area, each P-well contact area electrically contacting at least one of said P-well regions, wherein each of the at least one P-well region of at least one of the columns is electrically contacted at only one of the first end and the second end of the column.