Patent ID: 6841001
Filing Date: 2005-01-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: forming a variable mismatch layer comprising a first semiconductor material on a substrate, the substrate having a first in-plane unstrained lattice constant; forming a first layer comprising a first semiconductor material on the variable mismatch layer, the first layer having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant; and wherein the variable mismatch layer is configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate; and wherein the step of forming a variable mismatch layer comprises forming a second layer disposed adjacent the substrate, where the second semiconductor material has a third in-plane unstrained lattice constant that is mismatched with the first in-plane unstrained lattice constant and the second layer is formed to have an in-plane strained lattice constant that differs from the second in-plane unstrained lattice constant of the first layer by less than about 1%.