Patent ID: 7440329
Filing Date: 2008-10-21
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: memory cells including floating bodies in an electrically floating state and storing data based on the number of majority carriers within the floating bodies; a first dummy cell and a second dummy cell generating a reference data which becomes a data detection reference at the time of detecting the data of the memory cells and storing first data and second data of mutually opposite polarities, respectively; word lines connected to gates of the memory cells; a first dummy word line and a second dummy word line connected to a gate of the first dummy cell and a gate of the second dummy cell, respectively; a pair of bit lines connected to sources or drains of the memory cells; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as the reference data or detecting the second data using the first data as the reference data in a refresh operation of the first and the second dummy cells, the refresh operation being an operation in which data stored in the first or the second dummy cell is read, then the data is written back to the same dummy cell.