Patent ID: 9077259
Filing Date: 2015-07-07
Classification: H02M,H03K

Abstract:
1. A driver circuit comprising: a first switch configured to selectively couple a first driving node to a power supply node, wherein the first driving node is coupled to each transistor in a first set of two or more PMOS transistors; a second switch configured to selectively couple a second driving node to a ground node, wherein the second driving node is coupled to each transistor in a second set of two or more NMOS transistors; one or more delay modules disposed between the first and second driving nodes along a serial electrical path; an output node coupled to at least one transistor in each of the first and sets of transistors; a current sensor coupled in series with the output node; an inductor-capacitor (LC) tank coupled to the current sensor, the LC tank including an inductor coupled to a capacitor by a tank node; a comparator, said comparator comparing a voltage of the tank node against a reference voltage; a filter coupled to an output of the comparator; an adder having first and second inputs coupled to outputs of the current sensor and filter, respectively, said adder generating an adder output as the sum of said first and second inputs; and a pulse width modulation (PWM) generator, said PWM generator having an input coupled directly to an output of said adder, said PWM generator controlling the first and second switches, wherein gate terminals of the respective transistors in the first set are coupled together and gate terminals of the respective transistors in the second set are coupled together, wherein the driver circuit is configured to propagate a first drive signal in a first direction along the serial electrical path for biasing the first and second sets of transistors when the transistors in the first set, before receiving the first drive signal, are in a first state, wherein the driver circuit is configured to propagate a second drive signal in a second direction along the serial electrical path when the transistors in the first set, before receiving the second drive signal, are in a second state, wherein the one or more delay modules include one or more dummy transistors, each dummy transistor having a source and a drain coupled to each other and to a source of each transistor in the first or second sets, the one or more dummy transistors configured to delay propagation of the first and second drive signals along the serial electrical path.