Patent ID: 6473316
Filing Date: 2002-10-29
Classification: H02M,Y02B

Abstract:
A phase control circuit comprising:a first pair of output stages for generating a first output signal and a second output signal based on a clock signal so that said first and said second output signals are pulse signals having opposite polarities; a second pair of output stages, reset by a reset signal, for generating a third output signal and a fourth output signal which have phases controlled with respect to the first and the second output signals by the first and the second output signals respectively and also by a set signal produced based on a control signal, so that said third and said fourth output signals are pulse signals having opposite polarities; first delay means for delaying, before output, the rising of the first through the fourth output signals; and delay pulse means for generating a delay pulse based on low level periods of the delayed first and second output signals, and for resetting said second pair of output stages using said delay pulse as said reset signal.