Patent ID: 9158731
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A multiprocessor arrangement for communication between a plurality of processors, comprising: a plurality of processor circuits, each configured and arranged to access memory using a processor logic clock having a processor logic clock rate, a first memory block comprising a first port configured and arranged to provide access to the first memory block at a first memory clock rate that is faster than the processor logic clock rate, and a second memory block comprising a second port configured and arranged to provide access to the second memory block at a second memory clock rate that is faster than the processor logic clock rate, wherein a first group of processor circuits of the plurality of the processor circuits that are configured and arranged to stagger respective processor logic clocks to each sequentially access the first memory block using the first port and during a single clock cycle of the processor logic clock, and a second group of processor circuits of the plurality of the processor circuits that includes a processor circuit from the first group of processor circuits and wherein the processor circuits in the second group of processor circuits are configured and arranged to stagger respective processor logic clocks to each sequentially access the second memory block using the second port and during a single clock cycle of the processor logic clock.