Patent ID: 6590818
Filing Date: 2003-07-08
Classification: G11C

Abstract:
A method for testing a memory array comprising:implementing the memory array with a plurality of memory cells, each of the memory cells comprising a plurality of transistors; writing the memory array; conditioning a plurality of bit lines and complementary bit lines in the memory array by charging each of the plurality of bit lines and complementary bit lines respectively to a predetermined first voltage and to a predetermined second voltage, the predetermined first voltage and the predetermined second voltage having values that do not change bit states of fully functional bits of the memory array when the fully functional bits are addressed; activating a predetermined word line, the predetermined word line selecting a row of memory cells and making all of the plurality of transistors of each memory cell in the row of memory cells to electrically conduct; reading the predetermined word line; comparing results from the reading of the predetermined word line with bit values that were written to the predetermined word line to determine if any memory cell bit states in the predetermined word line were modified; and identifying modified memory cells as failing the testing.