Patent ID: 8185789
Filing Date: 2012-05-22
Classification: G01R

Abstract:
1. A process of delay testing logic circuitry with a test pattern of stimulus data bits originally produced for a contiguous scan path, comprising: A. sequentially shifting a first group of the test pattern of stimulus data bits from a single input lead through a memory part and a first subdivision of parallel connected, equal length subdivisions of a divided scan path, the shifting a first group including completely shifting data bits out of the first subdivision on a single output lead and storing a last input stimulus data bit to be shifted into the first subdivision in the memory part; B. sequentially shifting a second group of the test pattern of stimulus data bits from the single input lead through a second subdivision of the parallel connected, equal length subdivisions of a divided scan path, the shifting a second group including shifting all but the last input stimulus data bit into the second subdivision and all but the last data bit out of the second subdivision on the single output lead; C. simultaneously shifting the last input stimulus data bit into the first and second subdivisions and applying the first and second groups of test pattern of stimulus data bits to the logic circuitry in parallel to produce in the logic circuitry response data bits; D. simultaneously capturing the response data bits in the first and second subdivisions; and E. sequentially shifting the response data bits from the first and second subdivisions on the single output lead.