Patent ID: 6396764
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A memory comprising:a first memory segment comprising an array of rows and columns of two-transistor, one-capacitor memory cells, each column associated with first and second bitlines, a selected column of cells in the first segment accessed through a dedicated sense amplifier coupled to the first bitline associated with the selected column of the first segment; a second memory segment comprising an array of rows and columns of columns of two-transistor, one-capacitor memory cells, each column associated with first and second bitlines, a selected column of cells in the second segment accessed through a dedicated sense amplifier coupled to the first bitlines associated with the selected column of the second segment; a read input/output line coupled to the sense amplifier accessing the first bitline of the selected column of the first segment for reading data from the first segment during a selected access cycle, the second bitline of the selected column of the first segment being substantially simultaneously precharged; and a write input/output line coupled to the sense amplifier accessing the first bitline of the selected column of the second segment for simultaneously writing data to the second memory segment during the selected access cycle, the second bitline of the selected column of the second segment being substantially simultaneously precharged.