Patent ID: 6436850
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of manufacturing a multilevel semiconductor device, which method comprises the sequential steps of:forming a first dielectric layer on a substrate; forming a first patterned metal layer on the first dielectric layer, the first patterned metal layer having gaps therein and comprising a first metal feature; forming a second dielectric layer covering the first patterned metal layer and filling said gaps, said second dielectric layer comprising a low dielectric constant (low k) material; forming a third dielectric layer over said second dielectric layer; forming a first through-hole in said second and third dielectric layers, said first through-hole exposing a portion of the upper surface of the first metal feature; subjecting the exposed surfaces of the second and third dielectric layers to a degassing heat treatment at a temperature below which the low k material is degraded and for a first time interval; immediately after the degassing heat treatment, depositing, for a second time interval, a plug of electrically conductive material filling the first through-hole, thereby defining a first via; and depositing, for a third time interval, a first electrically conductive layer on said third dielectric layer and in electrical contact with said first via; wherein, the first time interval is equal to or shorter than the longer of the second and third time intervals.