Patent ID: 6268993
Filing Date: 2001-07-31
Classification: H01L,H02H

Abstract:
An electrostatic discharge protection circuit for a protected, high-voltage pad of a semiconductor device to protect its internal circuits from electrostatic discharge, the protected high-voltage pad being designed to receive voltages during the operation of the internal circuits that are greater than a rated voltage of the semiconductor device, the protection circuit comprising:a clamp stage, comprising at least two cascode-connected transistor clamps between the protected high-voltage pad and a reference conductor, that sinks electrostatic charge from the protected high-voltage pad to the reference conductor and away from the internal circuits; anda control stage that activates the clamp stage to couple electrostatic charge from the protected high-voltage pad and deactivates the clamp stage when the internal circuits are operational by reference to a control signal, which is derived from a reference pad, the reference pad powered to the less than or equal to the process rated voltage during normal operation, the control stage performing level shifting during normal operation such that the voltage across each transistor clamp does not exceed the process rated voltage and during electrostatic discharge events so that the transistor clamps are activated with a voltage derived from the protected pad.