Patent ID: 6828635
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A bipolar junction transistor structure integratable with a CMOS structure comprised of:a substrate having first and second device areas surrounded by trench isolation regions; first wells of an N type dopant for transistor collector contacts in said first device areas; second wells of a P type dopant in said second device areas adjacent to said first device, areas for transistor base regions; third wells of said N type dopant under said first and second wells and under said trench isolation regions for transistor subcollectors; gate electrode masking elements over said transistor base regions isolating transistor base contact regions from transistor emitter regions, while concurrently providing CMOS FET gate electrodes elsewhere on said substrate; first lightly doped drains of said N type dopant for said CMOS FETs and in said transistor emitter regions; second lightly doped drains of said P type dopant for said CMOS FETs and in said transistor base contact regions; sidewall spacers on said gate electrodes and on said gate electrode masking elements; source/drain areas of said N type dopant for said CMOS FETs, and concurrently providing emitters in said transistor emitter regions over and within said transistor base regions; source/drain areas of said P type dopant for said CMOS FETs, and concurrently providing ohmic base contacts in said base contact regions, said emitters separated from said base contact regions by said gate electrode masking elements.