Patent ID: 9218856
Filing Date: 2015-12-22
Classification: G11C

Abstract:
1. A memory comprising: a memory array having a memory array ground terminal at a memory array ground potential, wherein the memory array is configured to function in a higher power mode and a lower power mode; a supply ground terminal located external to the memory array, wherein the supply ground terminal is at a supply ground potential; a voltage bias source connected from the memory array ground terminal to the supply ground terminal to raise the memory array ground potential above the supply ground potential by a voltage differential; a switching device connected in parallel with the voltage bias source, wherein the switching device is configured to (i) conduct during the higher power mode and thereby bypass the voltage bias source to reduce the voltage differential and (ii) refrain from conducting during the lower power mode and thereby not bypass the voltage differential device and not reduce the voltage differential; a power supply configured to provide a supply voltage at a higher level to power the memory array; and a processor configured to