Patent ID: 6137328
Filing Date: 2000-10-24
Classification: H03K

Abstract:
A clock phase correction circuit for receiving an external clock and generating an internal clock, the clock phase correction circuit comprising:a delay means for generating the internal clock;a model portion for receiving the internal clock generated from the delay means as an input and generating a feedback clock;a phase detector for receiving the external clock and the feedback clock generated from the model portion, comparing a phase of the external clock with a phase of the feedback clock, and generating a detection signal;a controller which is operated by the detection signal generated from the phase detector and transmits a control signal to the delay means to control the delay means; anda track portion which receives the external clock, an inverted external clock, and the feedback clock and reduces a phase difference between the external clock and the feedback clock,wherein the delay means which receives an output signal of the track portion as input is controlled by a control signal from the controller, and generates the internal clock.