Patent ID: 6529050
Filing Date: 2003-03-04
Classification: H03K

Abstract:
A buffer comprising:a pull up block that receives an input signal, the input signal having a plurality of edges, the pull up block outputting a first signal in response to the input signal a delay time after the input signal is received, the first signal beginning a transition from a first logic level to a second logic level at a first time, the pull up block having: a first inverter having an input connected to receive the input signal, and an output, the first inverter including a first p-channel transistor and a first n-channel transistor connected to the first p-channel transistor, the first n-channel transistor having a length and a width, and being wider than the first p-channel transistor; and a second inverter having an input connected to the output of the first inverter, and an output that outputs the first signal; a first driver transistor connected to the pull up block and an output node, the first driver transistor receiving the first signal, sourcing a first current to the output node when a voltage level of the first signal is in a first voltage range, and stopping the first current when the voltage level of the first signal is in a second voltage range; a pull down block connected to the pull up block, the pull down block receiving the input signal and outputting a second signal in response to the input signal a delay time after the input signal is received, the second signal beginning a transition from the first logic level to the second logic level at a second time, the second time being different from the first time, the pull down block having: a third inverter having an input connected to receive the input signal, and an output; and a fourth inverter having an input connected to the output of the third inverter, and an output that outputs the second signal; and a second driver transistor connected to the pull down block and the output node, the second driver transistor receiving the second signal, sinking a second current from the output node when a voltage level of the second signal is in a first voltage range, and stopping the second current when the voltage level of the second signal is in a second voltage range.