Patent ID: 8933544
Filing Date: 2015-01-13
Classification: H01L

Abstract:
1. An integrated circuit system, comprising: a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide; a second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide, wherein a frontside of the first metal layer oxide of the first device wafer is bonded to a frontside of the second metal layer oxide of the second device wafer at a bonding interface between the first metal layer oxide and the second metal layer oxide, wherein one of the first device wafer and second device wafer comprises an imager chip and an other one of the first device wafer and second device wafer comprises a processing chip; a conductive path coupling the first conductor to the second conductor, wherein the conductive path is formed in a cavity etched between the first conductor and the second conductor and etched through the bonding interface and through the second semiconductor layer from a backside of the second device wafer; and a first metal electromagnetic interference (EMI) shield disposed in one of the first metal layer oxide and second metal layer oxide, wherein the first EMI shield is included in a metal layer of said one of the first metal layer oxide and the second metal layer oxide nearest to the bonding interface.