Patent ID: 8878614
Filing Date: 2014-11-04
Classification: H03L

Abstract:
1. A phase-locked loop circuit, comprising: an oscillator that generates an oscillation signal, the oscillator having a power-supply terminal and a control terminal; a detection block that detects a phase difference between a phase of the oscillation signal and a phase of a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference; an integral path including a regulator that receives the integral signal and supplies a regulated integral signal to the power-supply terminal of the oscillator, the regulator having a feedback loop including an error amplifier; and a proportional path to supply the proportional signal, separately from the integral signal, to the control terminal of the oscillator to adjust a delay parameter of the oscillator, wherein the oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal, the integral path supplies the regulated integral signal to the power-supply terminal of the oscillator in an analog form, the proportional path supplies the proportional signal to the control terminal of the oscillator in a digital form to select selectable circuit components to adjust the oscillation frequency, the regulator is a voltage regulator, the oscillator is a voltage-controlled oscillator that generates the oscillation signal having the oscillation frequency dependent on a voltage of the regulated integral signal, the oscillator is a ring oscillator having a plurality of delay cells connected in series, each of the delay cells includes a plurality of branches including respective inverters and switches to connect the inverters in parallel with each other, the proportional signal selects a number of the branches connected in parallel in each of the delay cells.