Patent ID: 6026472
Filing Date: 2000-02-15
Classification: G06F

Abstract:
A multiprocessor system comprising:a first processor bus;at least one processor connected to said first processor bus;an expansion bus;a first system memory;a first dual-ported memory controller connected to said first system memory, said first dual-ported memory controller having a first port connected to said first processor bus to manage transactions between said at last one processor connected to said first processor bus to manage transactions between said at least one processor connected to said first processor bus and said first system memory, and a second port connected to said expansion bus to manage transactions with said expansion bus;a second processor bus;at least one processor connected to a second processor bus;a second system memory;a second dual-ported memory controller connected to said second system memory, said second dual-ported memory controller having a first port connected to said second processor bus to manage transactions between said at least on processor connected to said second processor bus and said second system memory, and a second port connected to said expansion bus to manage transactions with said expansion bus;and wherein each one of said first and second dual-ported memory controllers includes:a plurality of page access counters, each one or said page access counters corresponding to a different memory page address within said first and second system memories; andsystem memory page access monitoring logic connected to the processor bus connected to said one or said first and second dual-ported memory controllers to read a memory page address associated with a transaction initiated by a processor connected to the processor bus connected to said one of said first and second dual-ported memory controllers and incrementing a value maintained within the page access counter corresponding to the memory page address associated with said transaction, said memory page access monitoring logic having:a maximum count register containing a maximum page access count value which is the number of page accesses permitted to any page address within said shared memory, andcompare logic to compare the maximum page access count value contained within said maximum count register with the values maintained within said page access counters and to generate an interrupt signal indicating the completion of system memory page access monitoring logic operation when the value maintained within one of said page access counters equals or exceeds said maximum page access count value.