Patent ID: 6754805
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A method for performing a digital signal processing operation comprising:providing a configurable computation engine including a plurality of M computation cells, where M is an integer greater than two, each given computation cell including at least one storage element, a comparator that compares an operand supplied thereto with respect to a data value stored in said at least one storage element, and control logic operably coupled to at least one multiplexer that configures operation of the given computation cell in response to configuration control data supplied thereto, wherein said computation engine also includes a global control register that supplies the configuration control data to the control logic for the M computation cells in parallel; providing first configuration control data from the global control register to the control logic of the M computational cells in parallel to configure the computation cells to perform correlation processing operations; operating the computation engine to perform a correlation operation; providing second configuration control data from the global control register to the control logic of the M computational cells in parallel to reconfigure the computation cells to perform filtering processing operations; operating the computation engine to perform a filtering operation; providing third configuration control data from the global control register to the control logic of the M computational cells in parallel to reconfigure the computation cells to perform sorting processing operations; and operating the computation engine to perform a sorting operation.