Patent ID: 6509603
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A split gate FET semiconductor device comprising:a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, said device having a channel with said channal having a channel width, a tunnel oxide layer formed over said substrate, a floating gate electrode layer including a layer of N+ doped polysilicon formed over said tunnsel oxide layer, said floated gate electrode layer having been patterned into a split gate floating gate electrode having a narrower width than said channel width, an interelectrode dielectric layer formed over said floating gate electrode and the exposed portion of said tunnel oxide, a control gate electrode including a layer composed of P+ doped polysilicon formed over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode having been patterned into a gate electrode stack above said channel, a surce region and a drain region having been ion implanted into said surface of said substrate with a P type of dopant, and said source region and said drain region being self-aligned with said gate electrode stack.