Patent ID: 6147902
Filing Date: 2000-11-14
Classification: G11C

Abstract:
A memory device having an array of memory cells, comprising:at least one memory block, including multiple-level memory cells each adapted for storing N.gtoreq.2 bits of information;electrically erasable and programmable bilevel memory cells each one adapted for storing one bit of information;means for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals (A0A21) supplied to the memory device, wherein said at least one memory block comprises a first sub-block including a first number of columns of multiple-level memory cells, a second sub-block including N groups (each made up of a second number of columns of bilevel electrically erasable and programmable memory cells, and wherein said means comprises first column selection means for selecting one column out of said first number of columns of the first sub-block, and second column selection means for simultaneously selecting one column out of said second number of columns of each of said N groups, the selection of either said one column of multiple-level cells or said N columns of bilevel electrically erasable and programmable cells being mutually exclusive and depending on the address signals.