Patent ID: 7444454
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. An ASIC array, comprising: three or more ASIC devices, each of said ASIC devices being a separate chip from the other of said three or more ASIC devices and having at least a first serial connection and a second serial connection; wherein a first serial connection of a first one of said three or more ASIC devices is coupled to a first serial connection of a second one of said ASIC devices with no other serial connection therebetween to form a first serial data communication link; wherein a second serial connection of said first one of said three or more ASIC devices is coupled to a first serial connection of a third one of said three or more other ASIC devices with no other serial connection therebetween to form a second serial data communication link; and wherein a second serial connection of said second one of said three or more ASIC devices is coupled to a second serial connection of said third one of said three or more ASIC devices with no other serial connection therebetween to form a third serial data communication link; wherein each of said first, second and third serial data communication links comprise duplex serial data communication links; and wherein said three or more ASIC devices of said ASIC array are configured to bi-directionally transfer data packets across each of said first, second and third duplex serial data communication links such that one data packet is transferred in whole by a given one of said first, second and third duplex serial data communication links during transfer of said data packet across said given one of said first, second and third duplex serial data communication links.