Patent ID: 6370057
Filing Date: 2002-04-09
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a plurality of areas that are arranged iteratively, each of said areas including: a memory cell array region; a sense amplifier and precharge circuit region; and a row decoder region, said memory cell array region having: bit lines precharged in a precharge circuit provided in said sense amplifier and precharge circuit region; word lines crossing said bit lines; and memory cells arranged at intersections of said bit lines and said word lines, said memory cells including a plurality of capacitors to which a plate electrode is connected in common, wherein in each said areas, said plate electrode is extended from said memory cell array region to said precharge circuit region, and said plate electrode is in contact with a power supply terminal of said precharge circuit in said precharge circuit region, and said precharge circuits precharge said bit lines at a potential corresponding to a potential of said plate electrode.