Patent ID: 7433251
Filing Date: 2008-10-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory array blocks, each block having a plurality of memory cells arranged in rows and columns; a plurality of redundancy data storage circuits, distributively arranged, corresponding to and along regions having corresponding memory array blocks placed thereon, each data storage circuit individually storing redundancy data for specifying a defective column of a corresponding memory array block, each of the redundancy data storage circuits including (i) a program circuit for programming and storing the redundancy data of the corresponding memory array block and (ii) a hold circuit receiving and holding storage data of the program circuit, the program circuit and the hold circuit being arranged oppositely with respect to the corresponding memory array block; and a plurality of row decoder circuits arranged in correspondence with the memory array blocks and on an opposite side of the corresponding memory array blocks from the corresponding redundancy data storage circuits for the corresponding memory array blocks, each row decoder circuit decoding a received address signal to select an addressed row in the corresponding memory array block.