Patent ID: 6106573
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A microprocessor comprising:a tracing control register;an instruction cache coupled to said tracing control register;an instruction alignment unit coupled to said instruction cache;a microcode instruction unit coupled to said instruction alignment unit and said instruction cache;one or more functional units coupled to said instruction unit;wherein said instruction cache is configured to fetch a first instruction, wherein said instruction cache is configured to dispatch said first instruction to said instruction alignment unit and said microcode instruction unit, wherein said microcode instruction unit is configured to cause a trace routine to be dispatched to said one or more functional units in response to said tracing control register indicating that said instruction is to be traced, wherein said trace routine is configured to cause state information to be stored to a memory, wherein said microcode instruction unit is configured to dispatch a plurality of microcode instructions that correspond to said first instruction to said one or more functional units in response to said first instruction not corresponding to a directly decodable instruction, and wherein said microcode instruction unit is configured to cause said instruction alignment unit to dispatch said first instruction to said one or more functional units in response to said instruction corresponding to a directly decodable instruction.