Patent ID: 7968956
Filing Date: 2011-06-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a p-channel MIS transistor formed on the semiconductor substrate, the p-channel MIS transistor having a first gate dielectric formed on the semiconductor substrate, a first gate electrode layer formed on the first gate dielectric and including Ta and C, and a first polysilicon layer formed on the first gate electrode layer; and an n-channel MIS transistor formed on the semiconductor substrate, the n-channel MIS transistor having a second gate dielectric formed on the semiconductor substrate, a second gate electrode layer formed on the second gate dielectric and having the same composition and orientation as those of the first gate electrode, and a second polysilicon layer formed on the second gate electrode layer, wherein a mole ratio of Ta to a total of C and Ta, (Ta/(Ta +C)), is larger than 0.5 in the first gate electrode layer and the second gate electrode layer, and each of the first gate electrode layer and the second gate electrode layer has an NaCl-prototype polycrystalline structure.