Patent ID: 6774390
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A semiconductor device comprising:an insulating layer having a major surface; a semiconductor board formed on a selected portion of the major surface of the insulating layer, the semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface; a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, the semiconductor layer having a lattice constant different from that of the semiconductor board, and having source and drain regions spaced apart from each other and a channel region between the source and drain regions, a channel length direction of the channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the channel region being larger than the area of the bottom surface of the semiconductor board; a gate insulating layer formed on the channel region of the semiconductor layer; and a gate electrode formed on the gate insulating layer.