Patent ID: 8575015
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, comprising: forming an epitaxial layer of semiconductor material of first conductivity type over a semiconductor substrate; forming a laterally elongated trench in the epitaxial layer; forming a layer of dielectric material on sidewalls and a bottom of the trench; forming a layer of hard mask material over the dielectric layer within the trench; forming a deep well of the first conductivity type in the epitaxial layer laterally spaced from an end of the trench; performing a first etch to remove a selected portion of the layer of dielectric material from the sidewalls and bottom at an opposite end of the trench; forming a shallow well of a second conductivity type to define a body region of a MOSFET within the epitaxial layer, underneath and surrounding sides of a remaining portion of the layer of dielectric material proximate the opposite end; wherein forming the shallow well includes implanting dopant underneath the remaining portion through a portion of the trench vacated by the removed portion of the layer of dielectric material; forming a shallow implant region of the first conductivity type to define a source region of the MOSFET underneath and surrounding the opposite end of the trench; performing a second etch through the portion of the trench vacated by the removed portion of the layer of dielectric material to remove another portion of the first layer of dielectric material from the sidewalls and bottom proximate the opposite end of the trench; removing the layer of hard mask material from the trench; forming a gate dielectric layer over the sidewalls and bottom of portions of the vacated by the removed portion and removed another portion of the layer of dielectric material; and forming a layer of gate electrode material within the trench, to define a gate electrode of the MOSFET over the layer of gate dielectric material and to define a field plate of the MOSFET over remaining portions of the layer of dielectric material.