Patent ID: 6826248
Filing Date: 2004-11-30
Classification: H03L

Abstract:
A phase locked loop circuit comprising:a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal; a charge pump configured to output a current signal in accordance with said up/down signal; an oscillator configured to output an oscillation signal of a frequency in accordance with said current signal; frequency dividing parts configured to divide the frequency of said oscillation signal and generating said frequency divided signal; phase frequency judging parts configured to judge whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed a predetermined reference value; and changeover parts configured to switch a value of a current flowing through said charge pump depending upon whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed said reference value.