Patent ID: 8559144
Filing Date: 2013-10-15
Classification: H02H

Abstract:
1. An ESD protection circuit, comprising: a PNP structure with a p-type emitter defining an anode, a p-type collector defining a cathode, and an n-type base defining a control gate, wherein the p-type emitter of the PNP structure is coupled to a high voltage node, the ESD protection circuit further comprising, an n-type emitter on the cathode side of the control gate, and an auto-biasing circuit connected to the n-type emitter for controlling electron flow into the n-type emitter, wherein the auto-biasing circuit comprises an NMOS transistor, a first reference Zener diode and a first resistor, wherein the NMOS transistor is controlled by the first reference Zener diode connected between a gate of the NMOS transistor and the high voltage node, wherein the first resistor is coupled between the gate of the NMOS transitor and ground, a second resistor coupled between the n-type base of the PNP structure and the high voltage node, a low voltage reference Zener diode coupled between the n-type base of the PNP structure and ground, wherein the low voltage reference Zener diode is configured to control the base of the PNP structure, and a diode coupled between the p-type collector of the PNP structure and ground, wherein the ESD protection circuit if configured to conduct current through the PNP structure when the voltage on the high voltage node is lower than the breakdown voltage of the first reference Zener diode and starts conducting current through the n-type emitter when the voltage on the high voltage node exceeds the breakdown voltage of the first reference Zener diode thus selectively increasing the current carrying capacity of an ESD device.