Patent ID: 7910427
Filing Date: 2011-03-22
Classification: G11C,H01L,Y10S

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of: providing a semiconductor substrate having a main surface, first MISFETs formed on a first MISFET forming area of the main surface, second MISFETs formed on a second MISFET forming area of the main surface, each of the first MISFETs having a gate electrode formed over the semiconductor substrate, a side wall spacer formed on a side surface of the gate electrode and a source region and a drain region formed in the semiconductor substrate, each of the second MISFETs having a gate electrode formed over the semiconductor substrate, a side wall spacer formed on a side surface of the gate electrode and a source region and a drain region formed in the semiconductor substrate; forming a first insulating film over the first MISFETs and the second MISFETs so as to cover the first MISFETs and the second MISFETs; removing a first portion of the first insulating film such that the first MISFETs are exposed and a second portion of the first insulating film such that a portion of the drain region of the second MISFETs are exposed; forming a refractory metal film over the first portion, the second portion and the first insulating film such that the first insulating film covers the gate electrode of the second MISFET and exposes the second portion; and forming first silicide films on the source region, the drain region and the gate electrode of the first MISFETs and second silicide films on the portion of the drain region of the second MISFETs.