Patent ID: 9189586
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. An integrated circuit layout, comprising: a doped substrate, wherein the doped substrate includes a plurality of parallel rows of doped wells, and wherein the doped substrate is interleaved among the rows of doped wells and the doping of the wells is of a different type than the doping of the substrate; a power switch cell, wherein the power switch cell bridges two parallel rows of the doped wells; a standard cell placed in a column with the power switch cell, wherein a first portion of the standard cell facing the power switch cell is positioned on one of the rows of doped wells bridged by the power switch cell with a second portion of the standard cell positioned on the doped substrate, wherein the first portion comprises logic of a type complementary to the doping of the wells, and the second portion comprises logic of a type complementary to the doping of the substrate; wherein the standard cell has a height substantially equivalent to the height of one of the doped wells, and wherein the power switch cell has a height that is at least double the height of the standard cell.