Patent ID: 8269542
Filing Date: 2012-09-18
Classification: H03K

Abstract:
1. A differential latch comprising a first data holding transistor and a second data holding transistor, said differential latch comprising: a first resetting transistor that is connected to a gate electrode of said first data holding transistor and is controlled by a reset signal; a first switching transistor that is connected to the gate electrode of said first data holding transistor and is controlled by a switch signal, being an inverted version of said reset signal; a second resetting transistor that is connected to the gate electrode of said second data holding transistor is controlled by the reset signal; a second switching transistor that is connected to the gate electrode of said second data holding transistor and is controlled by said switch signal; a first equalizing transistor for equalizing a load capacity that has a load capacity identical to that of said second resetting transistor and is connected to the gate electrode of said first data holding transistor; and a second equalizing transistor for equalizing a load capacity that has a load capacity identical to that of said first resetting transistor and is connected to the gate electrode of said second data holding transistor.