Patent ID: 6894336
Filing Date: 2005-05-17
Classification: H01L

Abstract:
1. A memory device comprising: a semiconductor wafer having a surface; a plurality of trenches formed in the semiconductor wafer, each trench including a top portion, and each trench having a first sidewall that is convexly curved and a second sidewall that is not convexly curved; a plurality of vertical access transistors, each transistor formed in the top portion of one of the trenches, wherein the transistor includes a curved channel disposed substantially perpendicular to the semiconductor wafer surface and wherein each vertical access transistor comprises a source region and a drain region formed in the semiconductor wafer disposed along the convexly curved sidewall of the trench, each transistor further including a gate insulating layer formed only along the convexly curved sidewall of the trench and a gate conductor formed in contact with the gate insulating layer, wherein the curved channel is disposed vertically between the source and drain regions and along the convexly curved sidewall of the trench so that the channel is convex.