Patent ID: 6406961
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A process for producing a memory structure, comprising steps of:providing a substrate; sequentially applying a tunnel dielectric layer and a first conductive layer onto said substrate; creating a trench in said first conductive layer; applying a first insulating layer onto said first conductive layer, which fills said trench; creating an implanting window in said first insulating layer; defining a source region on said substrate through said implanting window; applying a masking layer onto said substrate with said first conductive layer, said first insulating layer and said implanting window, and etching said masking layer to form a patterned mask; reacting a portion of said first conductive layer without the shield of said patterned mask to form a second insulating layer, and removing said patterned mask, and an unreacted portion of said first conductive layer exposed from the shield of said patterned mask, thereby forming a floating gate structure; forming an insulating spacer structure around said floating gate structure; applying a second conductive layer onto said substrate with said second insulating layer and said insulating spacer structure, and etching said second conductive layer to form a control gate structure; and defining a drain region on said substrate.