Patent ID: 8701059
Filing Date: 2014-04-15
Classification: G06F

Abstract:
1. A method for repartitioning a multilevel hierarchical description of a design unit comprising a plurality of macros, the method comprising the steps of: dissecting each macro of an original hierarchical design into combinational logic, latches and data signal cones, said data signal cones linking inputs of a first latch macro through one or more combinational logic macros to outputs of a second latch macro, wherein each latch macro comprises at least one latch, each input and output of each latch macro coinciding with an input or an output of a latch within said latch macro, and wherein a combinational logic macro comprises at least one logic gate; and creating, using a data processing system, a new hierarchical design by moving combinational logic from a latch macro to a combinational logic macro, said new hierarchical design having the same data signal cones as said original hierarchical design.