Patent ID: 7385233
Filing Date: 2008-06-10
Classification: H01L

Abstract:
1. A gate array integrated circuit comprising at least one unit cell, said at least one unit cell further comprising: a PMOS transistor and an NMOS transistor each comprising a respective active region thereof, the active regions defining a longitudinal direction extending between them and defining a field region disposed between them, the field region excluding the active region of said PMOS transistor and said NMOS transistor; a poly-silicon layer including a plurality of longitudinal portions of said poly-silicon layer being arranged in parallel to each other in the longitudinal direction to bridge between active regions of said PMOS transistor and said NMOS transistor, said longitudinal portions including a plurality of gate terminal regions each having an elongated share and extending in a lateral direction that is substantially perpendicular to longitudinal direction, each of the gate terminal regions having a space sufficient to dispose a plurality of connections thereon arrayed in the lateral direction; and a plurality of connecting parts in the space on at least one of the gate terminal regions.