Patent ID: 7622344
Filing Date: 2009-11-24
Classification: H01L

Abstract:
1. A method for manufacturing complementary metal oxide semiconductor (CMOS) transistors comprising steps of: providing a substrate having at least a first type gate structure and a second type gate structure, each of the gate structures comprising a gate dielectric layer, a gate conductive layer, and a hard mask layer; performing a source/drain formation process to form a first type source/drain area in the substrate at two sides of the first type gate structure and a second type source/drain area in the substrate at two sides of the second type gate structure; performing an etching back process to etch back and thin down the hard mask covering the first type gate structure; performing an etching process to form recesses in the substrate respectively at two sides of the second type gate structure through a patterned cap layer; and performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in each recess.