Patent ID: 6809967
Filing Date: 2004-10-26
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a first memory cell block capable of rewriting data, said first memory cell block having at least one first memory cell; a second memory cell block capable of rewriting data, said second memory cell block having at least one second memory cell adjacent to said first memory cell; a first data transfer line, said first data transfer line being electrically connected to said first memory cell block directly or via a selective element to select said first memory cell block; a second data transfer line, said second data transfer line being electrically connected to said second memory cell block directly or via a selective element to select said second memory cell block; a charge circuit, said charge circuit charging any one of said first data transfer line and said second data transfer line; a first data store circuit, said first data store circuit having a stable point in at least two voltages; a second data store circuit, said second data store circuit being electrically connected to said first data store circuit; a third data store circuit, said third data store circuit being electrically connected to said first data store circuit; a charge/discharge circuit, said charge/discharge circuit charging or discharging a first voltage node on the basis of the data held in said third data store circuit; a first connecting circuit, said first connecting circuit electrically connecting said first voltage node to any one of said first and second data transfer lines; a fourth data store circuit, said fourth data store circuit having a stable point in at least two voltages; and a second connecting circuit, said second connecting circuit electrically connecting said fourth data store circuit to said first voltage node.