Patent ID: 6285627
Filing Date: 2001-09-04
Classification: G11C

Abstract:
An address transition detector for a high density flash memory device, said flash memory device comprising a plurality of inputs and an array of single level flash memory cells, said address transition detector comprising:first one or more signal transition detectors coupled with a first one or more of said plurality of inputs through a first one or more signal paths, each of said first one or more signal transition detectors operative to detect when a corresponding of said first one or more of said plurality of input signals transition and generate a first transition detect signal;second one or more signal transition detectors coupled with a second one or more of said plurality of inputs through a second one or more signal paths, each of said second one or more signal transition detectors operative to detect when a corresponding of said second one or more of said plurality of input signals transition and generate a second transition detect signal;a transition signal path coupled with said first one or more signal transition detectors and operative to transmit said first transition detect signal;an equalization circuit coupled with said second one or more signal transition detectors and operative to transmit said second transition detect signal;an address transition detect pulse generator coupled with said transition signal path and said equalization circuit and operative to receive said first and second transition detect signals and generate an address transition detect pulse wherein said address transition detector is located closer to said second one or more of said plurality of inputs than said first one or more of said plurality of inputs; andwherein said first one or more signal paths are characterized by a first delay and said equalization circuit is characterized by a second delay wherein said first delay is substantially equivalent to said second delay.