Patent ID: 7379370
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a plurality of memory blocks each including a plurality of memory cells and a plurality of word lines connected to the memory cells; a plurality of word line groups formed in each of said memory blocks and each including a predetermined number of word lines; a refresh request generation circuit generating a refresh request to refresh the memory cells in a predetermined cycle; a refresh address generation circuit sequentially generating, in response to said refresh request, refresh addresses each indicating a word line connected to the memory cells to be refreshed; first word decoders formed corresponding to said word line groups, respectively, and each selecting a word line selection signal line to select any of the word lines in said word line group according to the refresh address or an external address; second word decoders formed corresponding to said word lines, respectively, and each selecting, in response to the selection of said word line selection signal line, any of the word lines in said word line group according to the refresh address or the external address; and a word control circuit holding, after a refresh operation, a selection of the word line selection signal line selected in each of said memory blocks corresponding to the refresh address, and unselecting, in response to an access request, only the selected word line selection signal line in the memory block indicated by the external address corresponding to this access request, wherein at least one bit of a lowest order of the refresh address generated by said refresh address generation circuit is assigned to select the memory block.