Patent ID: 6591345
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A processor comprising:a vector execution unit; a scalar processor unit; a cache controller; and a bank-interleaved cache memory, wherein said vector execution unit retrieves strided vectors of data and instructions stored in said bank-interleaved cache memory in a plurality of cache banks, wherein strided vectors of data and instructions stored in said bank-interleaved cache memory are retrieved by: determining T, given a stride S and an odd number R, from S=2T*R; and comparing T and W, and if T<=W, W defining a cache bank 2W words wide, then, for 0<=i<2(Wâˆ’T), 0<=j<2P, P defining said bank-interleaved cache memory to include 2P sets and j comprises a cache set number, and 0<=k<2N, N defining 2N cache banks in a set of said bank-interleaved cache memory and k comprises a bank number, words are accessed on the same cycle at the set and bank numbers of j and k, respectively, wherein j and k are related to an address of the words by address=i+2(Wâˆ’T+N)j+2(Wâˆ’T)k and wherein the address is computed as a base address plus a product of an index value and stride S.