Patent ID: 6442636
Filing Date: 2002-08-27
Classification: G06F

Abstract:
A parallel bus system capable of expansion, having a central processing unit, at least one peripheral device, and a parallel bus for connecting said central processing unit and said at least one peripheral device, said parallel bus comprising:1. a peripheral device selecting line; 2. a system clock line; 3. several other lines arranged to form lines for transmitting simultaneously a byte of said system, wherein said byte is an instruction byte, an address byte, or a data byte, wherein said instruction byte is put on said bus first, followed by said address byte, and then said data byte, and wherein a first bit of said byte specifies whether said byte is an instruction byte, wherein said peripheral device selecting line is a line used by said central processing unit for informing all of said peripheral devices whether to accept said bytes, and wherein at least one said instruction byte is used to designate said peripheral device to accept a following address byte and data byte.