Patent ID: 6292861
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A processor comprising:a processor core connected to an internal bus;a first interface circuit connected between the internal bus and a first bus; anda second interface circuit connected between the internal bus and a second bus, wherein said first interface circuit comprises a first address buffer register andholds an address on the internal bus in said first address buffer register in response to a read request from said processor core,outputs content of said first address buffer register to the first bus when comprising a bus ownership for the first bus and provides data on the first bus to the internal bus, andprovides an internal ready signal through the internal bus to said processor core, and wherein said second interface circuit comprises a second address buffer register andholds an address on the internal bus in said second address buffer register in response to a read request from said processor core,outputs content of said second address buffer register to the second bus and provides data on the second bus to the internal bus, andprovides an internal ready signal through the internal bus to said processor core, wherein each of the read request from said processor core to said first or second interface circuit is a combination of an internal address strobe signal and the address in said first or second address buffer register, respectively.