Patent ID: 8629008
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A method of forming a semiconductor structure comprising: forming a gate stack and a gate spacer laterally surrounding said gate stack on a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate; performing at least one processing step on said SOI substrate after forming said gate spacer, wherein at least one recessed region having a bottom surface below a level of a bottommost surface of said top semiconductor layer is formed through a portion of said top semiconductor layer and at least in an upper portion of a buried insulator layer in said SOI substrate; forming a dielectric material liner on sidewalls and a bottom surface of said at least one recessed region and over said gate spacer and said gate stack; and forming at least one dielectric fill portion that fills said recessed region at least above said level of said bottommost surface of said top semiconductor layer.