Patent ID: 7346813
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. An apparatus comprising: a plurality of core logic blocks, each of the plurality of core logic blocks configured to generate one or more indications of one or more events; a plurality of first event blocks, wherein each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block, and wherein each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block, wherein each event is assigned to a bit position within the register at which that event is recordable, and wherein each first event block is configured to classify at least one event into one or more of a plurality of classes, and wherein each first event block comprises at least one second register programmable with a mapping of events to the plurality of classes; and a second event block coupled to the plurality of first event blocks, wherein the second event block is configured to initiate one or more actions responsive to one or more events recorded in one or more of the plurality of first event blocks.