Patent ID: 8896635
Filing Date: 2014-11-25
Classification: G09G

Abstract:
1. A display device comprising: a plurality of pixels; a plurality of scanning lines for inputting a scanning voltage to the plurality of pixels, the plurality of scanning lines being divided into “b” number of first scanning groups, each of the first scanning groups including anywhere from 1 to “a” number of the scanning lines; a scanning line drive circuit which supplies the scanning voltage to the plurality of scanning lines; “a” number of gate lines belonging to a first group, being connected to the scanning line drive circuit; “b” number of gate lines belonging to a second group, being connected to the scanning line drive circuit; “b” number of reverse gate lines belonging to the second group, being connected to the scanning line drive circuit; a plurality of first transistors, each having a first electrode, a second electrode, and a control electrode, the first electrode being connected to one of the gate lines belonging to the first group, the second electrode being connected to one of the plurality of scanning lines, the control electrode being connected to one of the gate lines belonging to the second group; and a plurality of second transistors, each having a first electrode, a second electrode, and a control electrode, the first electrode being connected to one of the plurality of scanning lines, a predetermined reference potential being applied to the second electrode, the control electrode being connected to one of the reverse gate lines belonging to the second group, wherein: the control electrodes of the first transistors connected to the scanning lines belonging to each first scanning group are all connected to same one of the gate lines belonging to the second group; the control electrodes of the second transistors connected to the scanning lines belonging to each first scanning group are all connected to same one of the reverse gate lines belonging to the second group; when a selective scanning voltage is applied to any one of the gate lines belonging to the second group and a non-selective reversal scanning voltage is applied to any one of the reverse gate lines belonging to the second group, wherein the first transistors being connected to the any one of the gate lines belonging to the second group and the second transistors being connected to the any one of the reverse gate lines belonging to the second group are both connected to the scanning lines belonging to same one of the first scanning groups, so that the first transistors being connected to the scanning lines belonging to the same one of the first scanning groups are turned on and the second transistors being connected to the scanning lines belonging to the same one of the first scanning groups are turned off; and when a non-selective scanning voltage is applied to the any one of the gate lines belonging to the second group and a selective reversal scanning voltage is intermittently applied to the any one of the reverse gate lines belonging to the second group, so that the first transistors being connected to the scanning lines belonging to the same one of the first scanning groups are turned off and the second transistors being connected to the scanning lines belonging to the same one of the first scanning groups are intermittently turned on.