Patent ID: 9000562
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a capacitor bottom plate formed in a first metal layer and an interconnect feature formed in the first metal layer; a continuous dielectric layer formed directly on the capacitor bottom plate and the interconnect feature, the continuous dielectric layer having a first portion with a first thickness over the capacitor bottom plate and a second portion with a second thickness over the interconnect feature, the second thickness being greater than the first thickness, wherein the continuous dielectric layer is a single material and does not extend into a region below a top surface of the capacitor bottom plate and between the capacitor bottom plate and the interconnect feature; a capacitor top plate directly over the first portion of the continuous dielectric layer overlying the capacitor bottom plate; and a second dielectric layer extending over and in contact with a top surface of the capacitor top plate, wherein the capacitor top plate has a non-planar interface with a continuous portion of the second dielectric layer.