Patent ID: 8923061
Filing Date: 2014-12-30
Classification: G11C

Abstract:
1. A programming method for a nonvolatile memory device that includes a plurality of strings, each including a source select transistor, a plurality of memory cells, and a drain select transistor that are connected in series between a common source line and a bit line, the programming method comprising: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; applying a second voltage to an unselected bit line during the first period; applying, when a selected word line belongs to a first word line group adjacent to the common source line, a third voltage that is greater than the first voltage to the common source line during a second period in which a selected memory cell is programmed; and applying, when the selected word line belongs to a second word line group adjacent to the bit line, a fourth voltage that is greater than the second voltage to the unselected bit line during the second period.