Patent ID: 6304118
Filing Date: 2001-10-16
Classification: H03L,H04N,Y10S

Abstract:
A synchronous circuit comprising:a discrete time oscillator receiving an increment value and outputting a count value, said discrete time oscillator being a counter incremented by said increment value in response to an operating clock signal;a phase error detector having:a first circuit latching a first difference value between a first value of a reference signal in response to an (n-1)-th operating clock signal and a second value of said reference signal in response to an n-th operating clock signal,a second circuit latching a second difference value between said second value of said reference signal in response said n-th operating clock signal and an edge determination threshold,an edge detector detecting an edge of said reference signal when a value of said reference signal passes said edge determination threshold value, andcircuitry for calculating a correction rate based on a ratio of said first difference value and said second difference value; and outputting a phase error signal based on said correction rate and said count value; anda correction circuit varying said increment value based on said phase error signal.