Patent ID: 6222762
Filing Date: 2001-04-24
Classification: G11C,H01L

Abstract:
A multi-state memory comprising:a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors, each sector comprising an array of rows and columns;cell operating circuitry comprising:sense circuitry organized in a column oriented manner;steering elements organized in a column oriented manner; andselect circuitry organized in a row oriented manner,wherein one or more selected cells along a row are capable of being read simultaneously;a reference source;verification circuitry for selected cells for applying to associated steering elements of said selected cells conditions corresponding to verification of corresponding write state and for receiving read data using said reference source for determining if a selected one of said memory cells has been adequately programmed to the conduction characteristics associated with a desired programmed state; andwrite circuitry organized in a column oriented manner,wherein a selected one or more of said memory cells are capable of being written simultaneously with associated steering elements set to corresponding write states, and including termination circuitry for terminating the programming of selected memory cells along said row being programmed when said verification circuitry indicates said selected memory cells have been adequately programmed to their desired states.