Patent ID: 9135521
Filing Date: 2015-09-15
Classification: G06K,H04N

Abstract:
1. An image processing apparatus, comprising: a control unit to divide input image array data into a plurality of sub-blocks; a first arithmetic logic unit (ALU) to generate an integral image of at least one of the plurality of sub-blocks; a first memory and a second memory, wherein the control unit determines each of the plurality of sub-blocks to be included in any one of a first sub-block group and a second sub-block group, stores the integral image of each sub-block included in the first sub-block group on the first memory, and stores the integral image of each sub-block included in the second sub-block group on the second memory; and a first buffer memory to store an integral value of a bottom row of the integral image of each sub-block included in the first sub-block group, and an integral value of a bottom row of the integral image of each sub-block included in the second sub-block group.