Patent ID: 6618032
Filing Date: 2003-09-09
Classification: G09G

Abstract:
A display apparatus comprising a driving circuit having:a pulse generating circuit to generate, in addition to two original clock pulse signals, second clock pulse signals for a thinning purpose with a desired timing in a desired horizontal period in an operation to display a video signal having a vertical-pixel count greater than a predetermined vertical-pixel count of a display unit as a vertically reduced picture on a screen on said display unit by using two kinds of adjacent fields by writing a video signal in a horizontal period into two adjacent gate lines of said display unit, the number of gate lines to be driven being greater than the number of gate lines of said display unit, the video signal of each of the lines in the horizontal direction being thinned out for displaying the reduced picture, the lines being positioned away from each other in the vertical direction of the video signal, the number of lines being equal to a difference between the predetermined vertical-pixel count of said display unit and a vertical-pixel count of the video signal, the two original clock pulse signals being generated in a horizontal period as required in an operation of displaying a video signal having a vertical-pixel count equal to said predetermined vertical-pixel count of said display unit, said second clock pulse signals having pulses corresponding to positions of said original clock pulse signals to be thinned, and to repeat generation of said original clock pulse signals for each horizontal period and generation of said second clock pulse signals for a desired horizontal period; a gate-clock generating circuit to receive said original clock pulse signals and said second clock pulse signals from said pulse generating circuit and to generate gate-clock signals obtained as a result of superposing all of said original clock pulse signals on some of said second clock pulse signals wherein the number of said superposed second clock pulse signals is equal to a difference obtained as a result of subtraction of said vertical-pixel count of said display unit from said predetermined vertical-pixel count of said video signal, said second clock pulse signals being in a desired horizontal period, said gate-clock signals containing the original clock pulse signal thinned by the desired superposed second clock pulse signals and being for said two kinds of adjacent fields; and a gate driving circuit to receive said gate clock signals from said gate-clock generating circuit and to generate gate driving signals used for driving a predetermined number of gate lines as pulses of said gate clock signals for each horizontal period, wherein said gate clock signals generated from said gate-clock generating circuit cause said gate driving circuit to generate different gate driving signals for two adjacent gate lines in the same field, and wherein said display apparatus is a TFT-type liquid-crystal display apparatus.