Patent ID: 6127846
Filing Date: 2000-10-03
Classification: H03K

Abstract:
A programmable logic array device comprising:a plurality of regions of programmable logic, each of said regions being configured to produce an output signal which is a programmable function of a plurality of input signals applied to that region, said regions of programmable logic being arranged in a two-dimensional array having a plurality of rows of length l and having 2.sup.p columns, where p.gtoreq.3, such that each said row has 2.sup.p regions;a plurality of vertical conductors adjacent to each of said columns configured to selectively convey signals between regions in said columns;a plurality of horizontal conductors adjacent to each of said rows configured to selectively convey signals between regions in said row, said horizontal conductors adjacent to each of said rows comprising q groups of conductors, where 3.ltoreq.q.ltoreq.p, each rth group (for r=1, . . . , q) comprising r conductors each of length 2.sup.-(r-1) l, each of said r conductors being adjacent, and conveying signals among, 2.sup.p-(r-1) of said 2.sup.p regions.