Patent ID: 6107183
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method of forming an interlevel dielectric comprising the steps of:providing a first dielectric layer over a surface of a substrate situated on a semiconductor wafer;depositing a conductive layer on said first dielectric layer;depositing an electrically conductive additional layer on said conductive layer;patterning said conductive layer and said additional layer by:forming a patterned mask layer on said additional layer, andetching through said additional layer and said conductive layer and into said first dielectric layer, leaving a space between adjacent remaining portions of said conductive layer, said adjacent remaining portions of said conductive layer forming lines of conductive material;depositing a layer of dielectric material to fill each said space, wherein:the layer of dielectric material in each said space has a bottom surface;each line of conductive material has a bottom surface; andthe bottom surface of the layer of dielectric material in each said space is lower than the bottom surface of each line of conductive material that is adjacent thereto;removing said layer of dielectric material from the top thereof downward to at least to the level of the top of said additional layer;removing said additional layer on said lines of conductive material to form a top surface on each of the lines of conductive material that is lower than the top surface of the layer of dielectric material; anddepositing a second dielectric layer over the top surface of each line of conductive material and the top surface of the layer of dielectric material.