Patent ID: 9003652
Filing Date: 2015-04-14
Classification: H05K,Y02P,Y10T

Abstract:
1. A method of fabricating a circuit board, comprising: patterning a surface pad on a surface conductive layer; patterning at least one clearance in a conductive reference plane layer, the at least one clearance creating a reference pad, the reference pad connected to adjacent portions of the conductive reference plane layer by at least one conductive spoke adjacent the at least one clearance; patterning a differential trace pair in an embedded conductive signal layer; joining the surface conductive layer and the conductive reference plane layer to opposite sides of a first dielectric layer such that the reference plane layer underlies the first surface pad; and joining the embedded conductive signal layer and the conductive reference plane layer to opposite sides of a second dielectric layer such that the differential trace pair passes under the first reference pad.