Patent ID: 7877667
Filing Date: 2011-01-25
Classification: G11C

Abstract:
1. A semiconductor memory which is mounted on a semiconductor device for correcting an error in data to be inputted thereto/outputted therefrom and stores the data, the semiconductor memory comprising: a plurality of memory cell arrays each storing the data; a read circuit reading the data from the memory cell array; a read data latch latching the read data from the read circuit; an input data latch latching input data received by the semiconductor device; a computing unit performing arithmetic processing on the input data of the input data latch and the read data of the read data latch; a selector selecting one of data obtained by the arithmetic processing of the computing unit and the input data from the input data latch in accordance with presence/absence of an error in the data; and a write buffer writing the data of the selector to the memory cell array, wherein when the error in the data is to be corrected, the semiconductor memory corrects the error in the data based on the data from the computing unit.