Patent ID: 6235619
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method for forming a contact hole in the manufacture of a semiconductor device, comprising:a laminating process for laminating in sequence at least a first layer, a second layer, and a third layer, in which said second layer and said third layer are laminated sequentially over said first layer so as to cover a plurality of gate electrodes formed on said first layer;a first etching process in which an opening unit is formed between said gate electrodes and said third layer is etched using said second layer as an etching stopper;a depositing process in which an insulating material film is deposited on a side wall of said opening unit and a bottom portion of said opening unit to a thickness with which said insulating material film functions as a spacer for insulation; anda second etching process in which a contact hole is formed by anisotropically etching said insulating material film deposited at said bottom portion of said opening unit and said second layer beneath said insulating material film to expose said first layer;wherein said plurality of gate electrodes extend substantially parallel to each other in a first direction crossing an activation region, and said contact hole is formed between said gate electrodes, andwherein, in said depositing process, said insulating material film is deposited to a thickness with which a portion between a conductive material to be embedded inside said contact hole and said electrodes will be securely insulated, and a diameter of said opening unit in said first direction parallel to said electrodes after said insulating material film has been deposited is shorter than a length in said first direction of said activation region in which said contact hole is formed.