Patent ID: 7162590
Filing Date: 2007-01-09
Classification: G06F

Abstract:
1. Apparatus for processing data, said apparatus comprising: a plurality of processor cores operable to perform respective data processing operations, at least two of said processor cores being operable in a coherent multi-processing mode sharing access to a coherent memory region; and a memory access control unit operable to receive memory access requests via respective memory buses from said plurality of processor cores and in response to a memory access request from one of said processor cores operating in said coherent multi-processing mode to perform coherent multi-processing management operations to control access to said coherent memory region; wherein at least those memory buses of processor cores operating in said coherent multi-processing mode include a main portion and a coherent multi-processing portion, said main portion carrying main signals generated by said processor cores and specifying a memory access request using a uni-processing memory request protocol and said coherent multi-processing portion carrying additional signals generated by said processor cores and used by said memory access control unit in combination with said main signals to perform coherent multi-processing management operations to control access to said coherent memory region.