Patent ID: 6380592
Filing Date: 2002-04-30
Classification: G11C,Y10S

Abstract:
A semiconductor memory comprising:a first word line; first and second bit lines; a precharge line; first and second cross-coupled inverters, the first inverter including a first P-channel transistor and a first N-channel transistor, and the second inverter including a second P-channel transistor and a second N-channel transistor one terminal of each of the first and second N-channel transistors being connected to the precharge line; first and second access transistors, the first access transistor selectively coupling the first bit line to an input node of the first inverter, and the second access transistor selectively coupling the second bit line to an input node of the second inverter; and a control circuit for supplying a voltage pulse to the precharge line during an operation for writing data to the memory so as to precharge the input node of the first inverter and the input node of the second inverter to the same predetermined logic level.