Patent ID: 7203867
Filing Date: 2007-04-10
Classification: G06F

Abstract:
1. A processor system, comprising: a first program storage which stores a first program; a second program storage which stores a second program; a program counter which outputs execution addresses of said first and second programs; a first address storage which stores a first address in said first program; a second address storage which stores a second address in said second program; a comparator which compares whether or not said program counter coincides with said first address; an address changing unit which changes said program counter to said second address, when it is determined to have coincided by said comparator; a data bus which updates said first address stored in said first address storage and said second address stored in said second address storage; and an instruction decoder which provides a result of decoding instructions read out from said first and second program storages to said data bus, wherein said first address stored in said first address storage and said second address stored in said second address storage are updated based on the result of said instruction decoder.