Patent ID: 8598941
Filing Date: 2013-12-03
Classification: H03F

Abstract:
1. A compensation circuit for controlling a variation in output impedance of at least one buffer circuit, the compensation circuit comprising: a monitor circuit including a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor, the monitor circuit being configured to track an operation of an output stage of the buffer circuit and being operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in at least one of process, voltage and temperature (PVT) conditions to which the buffer circuit may be subjected; and a control circuit coupled with the monitor circuit, the control circuit being operative to generate a set of digital control bits as a function of the at least first control signal, the set of digital control bits being operative to concurrently compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions; wherein the pull-up portion in the monitor circuit comprises: a reference circuit operative to generate at least one of a reference voltage and a reference current as a function of a second control signal supplied to the monitor circuit, the second control signal being indicative of a prescribed voltage at which a pull-up impedance of the buffer circuit is measured; and a pull-up circuit including the at least one PMOS transistor and at least a first resistor connected in series with the at least one PMOS transistor, the pull-up circuit being operative to receive the at least one of the reference voltage and the reference current and to generate a pull-up signal indicative of the status of at least one characteristic of the corresponding pull-up portion in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected.