Patent ID: 6057187
Filing Date: 2000-05-02
Classification: H01L,Y10S

Abstract:
A fabrication method for a DRAM structure with multiple memory cells sharing the same bit-line contact, comprising:(a) providing a substrate;(b) defining an active region on said substrate, comprising a center region and a plurality of protrusions connected to two sides of said center region;(c) defining a plurality of word-lines on said active region, each word-line disconnected from the others and crossing said corresponding protrusion;(d) forming a plurality of channels at where said protrusions are overlapped by said word-lines, and doping said active regions via said word-lines to form a sharing drain region at said center region and a plurality of source regions where said protrusions are outside said channel regions;(e) forming an insulator capping said substrate, and then forming a bit-line contact exposing a partial surface of said sharing drain region;(f) forming a bit-line on said substrate that crosses said center region and is electrically connected to said sharing drain region via said bit-line contact; and(g) forming a plurality of metal lines electrically connecting to said corresponding word-lines.