Patent ID: 6564359
Filing Date: 2003-05-13
Classification: G06F,H03L

Abstract:
A clock control circuit comprising:a multiphase clock generating circuit, receiving a clock signal input thereto, for generating and outputting a plurality of clocks, phases of which differ from one another; a selector circuit, receiving a plurality of clocks output from said multiphase clock generating circuit, for selecting as an output signal one of the clocks received; a phase comparator circuit for detecting and outputting a phase difference between an output signal obtained by delaying the output signal of said selector circuit through a first variable delay circuit and one of the clocks output from said multiphase clock generating circuit; a filter for smoothing a phase difference detection signal output from said phase comparator circuit, an output signal of said filter being supplied to said first variable delay circuit for varying a delay time thereof; and a second variable delay circuit, a delay time thereof varied by the output signal of said filter, wherein a signal obtained by delaying the input clock signal through said second variable delay circuit is delivered as an output clock.