Patent ID: 7174431
Filing Date: 2007-02-06
Classification: G06F

Abstract:
1. A method for resolving ambiguous invalidates in a computer system having a plurality of data processing entities, a shared memory organized into a plurality of memory blocks, and one or more coherency units for maintaining status information over the memory blocks, at least some of the data processing entities having one or more caches and configured to issue requests for selected memory blocks, the method comprising the steps of: deleting a clean version of a given memory block from the cache of a first data processing entity without notifying the one or more coherency units; issuing from the first data processing entity a request for write access to the given memory block; receiving at the first data processing entity an un-ordered invalidate targeting the given memory block, the invalidate identifying a second data processing entity; issuing an Invalidate_Acknowledgement (IAck) from the first data processing entity to the second data processing entity; and upon receiving the given memory block at the first data processing entity, storing the block in the first data processing entity's cache in a valid state, and leaving the block in the valid state despite the earlier receipt of the invalidate.