Patent ID: 6027967
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method of making a capacitor structure comprising:providing a space extending between a pair of gate stacks on a semiconductor substrate to expose a charge conducting region formed therein;forming a layer of insulating material within said space and over said pair of gate stacks, said layer of insulating material substantially filling said space between said gate stacks;forming a hard mask layer over said layer of insulating material, said hard mask layer comprising a first group of alternating layers of a doped material and an undoped material, said first group of alternating layers of said doped material and said undoped material being formed during one deposition cycle;selectively removing a portion of said hard mask layer and a portion of said layer of insulating material, thereby forming a topographical structure projecting from each of said gate stacks, said topographical structures having a trench therebetween;depositing another layer over said topographical structures and in said trench therebetween;selectively removing a portion of said layer of insulating material and a portion of said another layer, thereby forming a recess which exposes said charge conducting region between said pair of gate stacks;forming a second group of alternating layers of said doped material and said undoped material over said topographical structures and in said recess, said second group of alternating layers of said doped material and said undoped material being formed during one deposition cycle;selectively removing portions of said doped material and said undoped material that are situated above the charge conducting region and between the pair of gate stacks; andselectively removing a greater portion of said doped material or said undoped material, thereby increasing the exposed surface area of the other of said doped material or said undoped material, respectively, and thereby forming a capacitor storage node adjacent to and in contact with each said gate stack, said capacitor storage node having alternating layers of said doped material and said undoped material.