Patent ID: 8350595
Filing Date: 2013-01-08
Classification: G06F,H03L,Y02D

Abstract:
1. A semiconductor integrated circuit having a phase comparison circuit to compare a phase between first and second clocks provided with different signal amplitudes, wherein the phase comparison circuit uses the first clock as an activation signal for a differential input stage, differentially amplifies the second clock based on a reference voltage equivalent to half a drive voltage for the second clock, and senses and latches a differential amplification result, comprising: a first circuit using a first power-supply voltage for operation and a second circuit using a second power-supply voltage for operation, wherein the semiconductor integrated circuit uses a comparison result from the phase comparison circuit, performs clock delay adjustment between a path for transmitting a clock to the first circuit and a path for transmitting a clock to the second circuit along a clock tree for transmitting a clock to the first circuit and the second circuit, and synchronizes both clocks.