Patent ID: 8076955
Filing Date: 2011-12-13
Classification: G06F,H03K

Abstract:
1. A method comprising: providing a configurable logic device comprising a plurality of configurable logic cells, each configurable logic cell comprising a plurality of multi-bit registers, at least one multi-bit register being accessible both in a parallel and in a serial fashion; selectively coupling, using an input selection facility, an output of a first multi-bit register to the input of a second multi-bit register, the input selection facility causing a bit-shift-operation of the output of the second multi-bit register for each clock cycle; performing a temporal multiplication algorithm for multiplicands present on the inputs of the first multi-bit register; selectively coupling, using the input selection facility, the output of the first multi-bit register to the input of the first multi-bit register of another one of the configurable logic cells; and performing a spatial multiplication algorithm for multiplicands present on the inputs of the first multi-bit registers of the each configurable logic cell and the another one of the configurable logic cells.