Patent ID: 8471324
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a plurality of stacked gates located on a substrate, wherein there are a first gap and a second gap among the stacked gates, and a dimension of the first gap is smaller than a dimension of the second gap, wherein each of the stacked gates further comprises a self-aligned silicide layer; a first doped region located in the substrate under the first gap; a second doped region located in the substrate under the second gap; a spacer material layer located in the first gap; two first spacers located at sidewalls of the stacked gates in the second gap, wherein there is a pipe or a seam between the first spacers, and a material of the first spacers and a material of the spacer material layer are the same; an insulating layer filled up the pipe or the seam, wherein the first spacers and the insulating layer do not cover the plurality of stacked gates; a dielectric layer located on the substrate and covering the insulating layer and the stacked gates; a contact window located in the dielectric layer, the insulating layer, and the first spacers in the second gap, wherein the contact window is electrically connected to the second doped region; and a silicide layer located merely between the contact window and the second doped region, wherein a material of the self-aligned silicide layer is different from a material of the silicide layer.