Patent ID: 6144577
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A semiconductor memory device formed on a main surface of a semiconductor substrate, comprising:first to nth memory cell blocks each having memory cells arranged in rows and columns, n representing a natural number;first to nth local data buses provided for said first to nth memory cell blocks, respectively;first to mth global data buses for communicating data with said memory cell blocks, m representing a natural number smaller than n;a connection controlling circuit outputting first to mth control signals to connect the first to the mth global data buses to m ones of the first to the nth local data buses, respectively; andfirst to mth connection circuits provided for connecting the first to the mth global data buses with m ones of the first to the nth local data buses, respectively, an ith connection circuit of the first to the mth connection circuits selectively connecting one of the ith to the (i+n-m)th local data buses with the ith global data bus in response to the ith control signal, i representing a natural number from one to m.