Patent ID: 8468484
Filing Date: 2013-06-18
Classification: G06F,Y02P

Abstract:
1. A method of designing a circuit layout of an electronic integrated circuit, the circuit comprising component contact areas, voltage states, and nets, the method being embodied in a data processing apparatus having at least an arithmetic processor and memory, the method comprising the steps of: a. determining the effect on the voltage state of one or more nets in the circuit, due to a single event occurring near each contact area, for each contact area in the circuit; b. categorizing the contact areas in such a way that contact areas for which a single event have opposing effects on the voltage state of the nets in the circuit, and for which a single event has a non-opposing effect on the voltage state of the nets in the circuit, are identified; c. placing these contact areas in such a way that when a single event has opposing effects on the voltage state of the circuit nets, the opposing first and second contact areas are placed as close to each other as permitted by the circuit and by the design rules; d. placing a first contact area and a second contact area, with non-opposing effects on the voltage state of the nets in the circuit, said non-opposing effects caused by a single event, wherein the first and second contact areas are non-adjoining, and placing a third contact area in between the first and second contact areas, wherein said third contact area has an effect on the voltage state of the nets in the circuit opposing those of the first and second contact areas, and wherein the third contact area's effect on the voltage state of the nets in the circuit is caused by a single event; e. adjusting the contact areas so that the opposing effects of a single event are of approximately equal magnitude, to substantially minimize the effect of the single event on the voltage state of the nets in the circuit; f. designing a mask layout of the integrated circuit, the mask layout based on the circuit layout designed using this method; and g. storing the mask layout in the data processing apparatus memory.