Patent ID: 6275894
Filing Date: 2001-08-14
Classification: G11C

Abstract:
The bank selector circuit for a non-volatile memory device with a flexible bank partition architecture, comprising:(a) a memory boundary option designating a memory partition boundary selected from a plurality of predetermined memory partition boundaries, the memory boundary option capable of generating a partition boundary indicator signal based upon the selected memory partition boundary, the memory boundary option comprising a partition indicator circuit capable of designating the selected memory partition boundary that separates the memory into the upper memory bank and the lower memory bank, wherein the partition indicator circuit further comprises:(i) an upper bank conductive line comprising first and second upper bank conductive line segments separated by an upper bank conductive line gap identifying the selected memory partition boundary, the first upper bank conductive line segment having a first end capable of receiving a DC common voltage, and the second upper bank conductive line segment having a second end capable of being grounded; and(ii) a lower bank conductive line comprising first and second lower bank conductive line segments separated by a lower bank conductive line gap identifying the selected memory partition boundary, the first lower bank conductive line segment having a first end capable of receiving the DC common voltage, the second lower bank conductive line segment having a second end capable of being grounded;(b) an encoder, coupled to the memory boundary option, capable of generating a plurality of code bits of a bank selector code with values of the bits selected based upon a location of the partition of memory into an upper memory bank and a lower memory bank at the selected memory partition boundary in response to receiving the partition boundary indicator signal; and(c) a decoder coupled to receive the bank selector code from the encoder and further coupled to receive a plurality of memory address bits of a memory address, the decoder having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.