Patent ID: 7804728
Filing Date: 2010-09-28
Classification: G11C

Abstract:
1. A method of memory operation, comprising: providing an array of static random access memory (SRAM) cells, the array including rows and columns of SRAM cells; providing true and complement bitlines to each of the columns of the array; precharging during a precharge operation, by first and second precharge devices, the true and complement bitlines, respectively, of the columns up to a first predetermined voltage; reading during a read operation, by a sense amplifier, a memory state of a particular cell in a column of the array; equalizing during a voltage equalization operation, by an equalization device in each column, voltages on the true and complement bitlines of each column, thus providing an equalized voltage for each of the columns of the array; determining, by a control circuit, if the equalized voltage of a column of the array is less than a second predetermined voltage; and performing another read operation after the voltage equalization operation when the control circuit determines that the equalized voltage of a column of the array is not less than the second predetermined voltage.