Patent ID: 7373453
Filing Date: 2008-05-13
Classification: G06F

Abstract:
1. A method of interleaving memory banks of a memory element connected with a multi-layer bus system, comprising: receiving signals from master and/or slave devices requesting access to a bus of one of a plurality of layers and generating respective control signals; and receiving the control signals in a plurality of sets and generating corresponding signals required to access specific memory banks of the memory element, the specific memory banks accessed based on the generated corresponding signals, wherein signals to access the memory banks corresponding to the plurality of master and/or slave devices connected with a second layer are received during a time delay between the signals to access the memory banks corresponding to the plurality of master and/or slave devices connected with a first layer and transmission of data to the plurality of master and/or slave devices connected with the first layer, and wherein a first memory bank of the memory element is specifically accessed by the master and/or slave devices connected with the first layer and a second memory bank of the memory element is specifically accessed by the master and/or slave devices connected with the second layer.