Patent ID: 6148034
Filing Date: 2000-11-14
Classification: H04N

Abstract:
A circuit that determines a sum squared error between a vector v and a vector u comprising:a) one or more binary-to-residue converter means, each having an input and an output;b) a residue-to-binary converter means having an input and an output;c) one or more residue number adder means having two inputs and an output wherein the outputs are the sums, represented in residue number format, of the two inputs, represented in residue number format; andd) one or more means having two inputs and an output, wherein the outputs, represented in residue number format, are the square of the difference between a variable applied on one input, which is represented in residue number format, with a variable applied on the other input, which may be represented in binary number format or in residue number format;e) wherein binary number inputs are coupled to inputs to binary-to-residue converters, wherein binary-to-residue converter outputs are coupled to part d means inputs, wherein adder inputs are coupled to part d means outputs or adder outputs, and wherein one adder output is coupled to a residue-to-binary converter, such that the latter's binary number output is the sum squared error of the vector v and the vector u applied to inputs to part d means.