Patent ID: 6735110
Filing Date: 2004-05-11
Classification: G11C

Abstract:
A memory device having single event upset resistant circuitry, comprising:a first inverter having a first input node and a first output node; a second inverter having a second input node and a second output node; a first transistor having a first source/drain contact coupled to the first input node and a second source/drain contact coupled to the second output node; a second transistor having a third source/drain contact coupled to the second input node and a fourth source/drain contact coupled to the first output node; the first transistor and the second transistor programmable to provide low resistances less than 1000 ohms and high resistances of more than 100,000 ohms, wherein the first transistor and the second transistor each have floating bodies, and wherein the first transistor and the second transistor each have a gate coupled to a gate bias voltage source, the gate bias voltage source putting the first transistor and the second transistor into a partially conductive state to provide the high output resistances.