Patent ID: 6373348
Filing Date: 2002-04-16
Classification: H01L,H03H

Abstract:
A high speed differential attenuator comprising:a low temperature co-fired ceramic substrate having first and second dielectric layers with each dielectric layer having top and bottom surfaces; a voltage potential lead formed on the top surface of the first dielectric layer for receiving an integrated circuit device where the bottom surface of the integrated circuit device is a voltage input lead for the integrated circuit device; first and second parallel resistor-capacitor divider networks formed as part of the substrate with each divider network having first and second parallel resistors and capacitors and an input node and a center tapped output node with each input node coupled to receive an input signal and each output node coupled to an input of the integrated circuit device; each divider network having first and second conductive elements formed on the top surface of the first dielectric layer functioning as first capacitive plates for the first and second capacitors and a third conductive element disposed between the first and second dielectric layers and positioned beneath the first conductive element functioning as the other capacitive plate for the first capacitor with the first and second conductive elements being electrically coupled together; a fourth conductive element disposed between the first and second dielectric layers and positioned beneath both of the second conductive elements of the divider networks and the voltage potential lead functioning as the other capacitive plate for the second capacitors of the divider networks and as a heat transfer layer; first and second electrically conductive vias respectively coupled to the input nodes of the divider networks and to the respective third conductive elements disposed between the dielectric layers; and at least a first thermally conductive via formed between the top and bottom surfaces of the second dielectric layer below the voltage potential lead and thermally coupled to the fourth conductive element disposed between the dielectric layers.