Patent ID: 8248131
Filing Date: 2012-08-21
Classification: H03K

Abstract:
1. A timing generating circuit generating a predetermined timing of a processing signal, comprising a phase shift circuit, a phase shift controller, and a counter circuit, wherein (A) the phase shift circuit receiving a repeat signal generates a signal of which a phase is shifted by a predetermined quantity on the basis of the repeat signal, (B) the phase shift controller controls the phase shift circuit to output one of first to M-th signals of which phases are differently shifted each other, and (C) the counter circuit counts the number of output signals of the phase shift circuit and generates a count end signal (which is a signal output after counting up or down is ended) when a count value reaches a set value, whereby the counter circuit outputs a synthesized timing signal including a timing of the repeat signal and a timing shifted by the phase shift circuit, wherein the timing generating circuit further includes a delay circuit used in the phase shift circuit, the delay circuit comprising: a serial-connection delay circuit group including Q delay circuits having at least two different delay times, a bypass switch group including Q bypass switches connected between both terminals of the respective delay circuits, and an output switch group including Q switches connected between a terminal apart from a signal input side of the respective delay circuits and an output terminal.