Patent ID: 6426953
Filing Date: 2002-07-30
Classification: H04L

Abstract:
A high speed ATM bus (100) used in an ATM network node equipment for transferring ATM cells between a plurality of connected adapters (10-1, . . . , 10-N), said ATM bus (100) comprising a clock signal (CLK), a synchronization signal (SYNC), an adapter identification bus (SID) and a data bus (S(0-31));said high speed ATM bus (100) characterized in that it behaves as an ATM cell serial/parallel bus responsive to said clock signal (CLK) and to said synchronization signal so as to perform three operation modes on said data bus (S(0-31)): a bus request operation mode; a bus acknowledge operation mode; and an ATM cell transfer operation mode from a first adapter to a second adapter.