Patent ID: 7499519
Filing Date: 2009-03-03
Classification: G11C

Abstract:
1. A shift register comprising: a first data storage unit and a second data storage unit; a first multiplexer having an output coupled to an input of the first data storage unit; a second multiplexer having a first input coupled to an output of the first data storage unit and an output coupled to an input of the second data storage unit; a third data storage unit having an output coupled to a second input of the second muliplexer, wherein an output of the second data storage unit and an input of the third data storage unit are coupled to each other with no multiplexer disposed therebetween; a fourth data storage unit having an output coupled to an input of the first multiplexer; and a third multiplexer having an output coupled to an input of the fourth data storage unit, a first input being coupled to the output of the third data storage unit, and a second input being coupled to the output of the first data storage unit.