Patent ID: 7279780
Filing Date: 2007-10-09
Classification: H01L,Y10S

Abstract:
1. A lead frame for an integrated circuit package, the lead frame comprising: an outer frame portion; a die paddle configured for attachment to a semiconductor die; and a plurality of discretely defined leads extending inwardly and cantilevered from the outer frame portion, each of the plurality of leads having a first bonding region and at least a second bonding region arranged in a grid array about the die paddle, the grid array including a first peripheral row of bonding regions spaced about a periphery of the die paddle and at least one other peripheral row of bonding regions spaced outwardly from the first peripheral row of bonding regions and inwardly of the outer frame portion, wherein the first bonding region and the at least a second bonding region of each lead are coupled to each other by a portion of the lead exhibiting a thickness that is less than a thickness of at least one of the associated first bonding region and at least a second bonding region.