Patent ID: 7613044
Filing Date: 2009-11-03
Classification: G11C

Abstract:
1. A method for high voltage operation on selected memory cells of a semiconductor memory device comprising a memory cell array comprising a plurality of memory cells including the selected memory cells, each of said plurality of memory cells accessed by one of a plurality of word lines and one of a plurality of bit lines, the method comprising the steps of: providing a continuous high voltage level on selected ones of the plurality of word lines to the selected memory cells; and maintaining the continuous high voltage level at a first high voltage supply node connected to a bit line decoder, wherein the bit line decoder controls access to the selected memory cells for high voltage operation thereon by sequentially providing the high voltage level to a first portion of the plurality of bit lines, discharging the first portion of the plurality of bit lines, providing the high voltage level to a second portion of the plurality of bit lines, and discharging the second portion of the plurality of bit lines.