Patent ID: 8174899
Filing Date: 2012-05-08
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cell transistors are arranged; a first bit line connected to one of plurality of memory cell transistors; a second bit line connected to another of plurality of memory cell transistors; and a write controller configured to control in a write operation that a verification operation subsequent to a program operation is carried out with a program voltage increasing stepwise for each program operation, wherein the write controller controls that a first verification operation is carried out at a first verification level for the plurality of memory cell transistors connected to the first and second bit lines, subsequently to the first verification operation, a program operation is carried out in a state where a first voltage is applied to the first and second bit lines, and a verification operation for the memory cell transistor subsequent to the program operation is carried out as a second verification operation at the first verification level.