Patent ID: 8125020
Filing Date: 2012-02-28
Classification: H01L

Abstract:
1. A device for non-volatile memory, the device comprising: a cell stack comprising: a select gate formed adjacent to a first sidewall of the cell stack, the cell stack having two sidewalls that include end portions of the tunneling dielectric layer, the charge storage layer, the blocking dielectric layer, and the control gate, the select gate only overlying the first sidewall of the two sidewalls of the cell stack; a first oxide region formed adjacent to a full length of the first sidewall of the cell stack; a second oxide region formed adjacent to a full length of a second sidewall of the cell stack; a first spacer formed between the first oxide region and the select gate; a second spacer formed adjacent to the second oxide region; and a drain region and a source region formed in the substrate, wherein the drain region is formed adjacent to the select gate, and wherein the source region is formed adjacent to the cell stack opposite the drain region, and wherein the channel region is formed between the drain and the source regions, wherein, when a selected bias of a first polarity is applied to the control gate and the select gate relative to the channel region of the substrate, charges of an opposite polarity are injected from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the opposite polarity charges in the charge storage layer, and wherein, when a selected bias of a second polarity opposite to the first polarity is applied to the control gate relative to the channel region of the substrate, charges of the first polarity are directly tunneled from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the first polarity charges in the charge storage layer.