Patent ID: 7197624
Filing Date: 2007-03-27
Classification: G06F

Abstract:
1. An array processor comprising: processing elements grouped into a plurality of clusters, wherein each processing element is identified as a node in a torus network; a first cluster having a first plurality of processing elements, the number of processing elements in the first cluster being less than the number of nodes in the torus network; a first cluster switch to which each processing element of the first plurality of processing elements is connected; and a cluster control line connected to the first cluster switch for carrying a control signal, the control signal controlling the operation of the first cluster switch to selectively establish a connection path between two processing elements of the first plurality of processing elements, wherein the two processing elements are transpose nodes of the torus network and wherein each connection path established through the first cluster switch is communicatively equivalent to a connection path between two nearest neighbor processing elements disposed in the torus network.