Patent ID: 7135707
Filing Date: 2006-11-14
Classification: H01L,Y10S

Abstract:
1. A semiconductor device comprising: a semiconductor region comprising a source region, a drain region, a channel region, and a pair of regions between the channel region and the source and drain regions, said pair of regions formed of a same material as said channel region wherein each of said pair of regions has a first portion contiguous to the channel region and a second portion contiguous to the source or drain regions; an insulating film formed over said semiconductor region; a first conductive layer vertically overlapped with the channel region and having the insulating film interposed therebetween; a second conductive layer formed over said first conductive layer; a third conductive layer formed over said insulating film; a fourth conductive layer formed over said third conductive layer; an interlayer insulating film formed over said first conductive layer, said second conductive layer, said third conductive layer, and said fourth conductive layer; at least one contact hole in said interlayer insulating film; and a wiring connected to one of said source and drain regions; wherein a width of the first conductive layer is narrower than that of the second conductive layer, wherein the second conductive layer extends beyond side edges of the first conductive layer and extending portions of the second conductive layer overlap the first portions of said pair of regions while the second portions are not overlapped by said second conductive layer, wherein a width of said third conductive layer is narrower than that of said fourth conductive layer, wherein said fourth conductive layer extends beyond side edges of the third conductive layer, wherein said wiring overlaps with said third conductive layer and said fourth conductive layer, and wherein an impurity concentration of the channel is the same as that of the first portion and the second portion.