Patent ID: 7191373
Filing Date: 2007-03-13
Classification: G01R

Abstract:
1. An apparatus for inserting a DFD (design-for-debug) circuitry in an integrated circuit to debug or diagnose selected fault types in scan cores, the integrated circuit containing two or more said scan cores each having a scan clock; said apparatus comprising: (a) a DFD selector for indicating which said scan cores and said selected fault types will be debugged or diagnosed simultaneously; (b) a scan connector for connecting multiple scan chains in said scan cores to a boundary-scan chain in said integrated circuit; (c) a scan clock generator for generating an ordered sequence of capture clocks for connection to said scan clocks in said scan cores; and (d) a multiplexer for connecting said DFD selector and said scan connector to a TAP (test access port) controller in said integrated circuit.