Patent ID: 6469328
Filing Date: 2002-10-22
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising:a memory cell formed by a plurality of transistors, gate wiring layers of all of the transistors forming said memory cell being arranged to extend in one direction, wherein: of the transistors forming said memory cell, first transistors which are coupled to word lines are arranged on an outer side of second transistors which are coupled to a power supply, within the memory cell, and the gate wiring layers of at least two of said second transistors which are coupled to the power supply are connected to each other, a plurality of power lines, a first one of which running within the memory cell, two word lines running on both sides of the first power line, a second power line intersecting the first power line, and two bit line pairs running on both sides of the second power line; and wherein a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and a source/drain of the transistor, forming said adjacent memory cell and a bulk layer of a substrate contact are used in common by reversing a layout of said certain cell with respect to both an x-axis direction and a y-axis direction.