Patent ID: 6701506
Filing Date: 2004-03-02
Classification: G06F,H03K

Abstract:
A method for inserting a delay in a node in an electrical design at an output terminal of a logic gate whereby an input capacitance as seen by a parent node at an input terminal of said logic gate is maintained, said method comprising:inserting a first new logic gate between said parent node and said input terminal of said logic gate, said first new logic gate being of the same cell type as said logic gate, having the same input capacitance in an input terminal corresponding to said input terminal of said logic gate, and being positioned near said logic gate to reduce wire capacitance between said first new logic gate and said logic gate; and determining if said delay is successfully added by said insertion; and if said delay is not successfully added by said insertion, adding said delay by, instead inserting said first new logic gate, inserting a second new logic gate at said output terminal of a said logic gate, a combination of said logic gate and said second new logic gate giving said delay to be added.