Patent ID: 6279146
Filing Date: 2001-08-21
Classification: G06F

Abstract:
A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses, and verification engine comprising:a. a first hardware model and a second hardware model, each configured as a said component and having a set of hardware model input/output pins;b. a first bus wrapper connected to said first hardware model and a second bus wrapper connected to said second hardware model;c. a set of bus lines, each said bus line being connected to said first bus wrapper and said second bus wrapper;d. wherein each said bus wrapper further has switchable communicative circuitry that switchably communicatively connects each said hardware model input/output pin to a bus line and has a control block controlling said switchable communicative circuitry;e. a system controller connected to at least some of said bus lines and adapted to transmit a sequence of time synchronization information to each said bus wrapper control block, said time synchronization information sufficient to permit said control blocks to uniformly determine a time slot number; andf. wherein said control blocks uniformly determine said time slot number in response to said time synchronization information and in response thereto each control block switches at least one said input/output pin into communicative contact with a said bus line so that at least one said input/output pin from said first hardware model is connected to at least one said input/output pin of said second hardware model.