Patent ID: 8710915
Filing Date: 2014-04-29
Classification: G05F

Abstract:
1. An apparatus, comprising: a plurality of circuits, each of which operates with a reference voltage; a constant current generator which includes a band gap reference circuit configured to generate a criterion voltage for a first pMOS (p-channel type Metal-Oxide-Semiconductor) transistor and a bias circuit configured to generate a gate voltage for a second pMOS transistor operating in a saturation condition, the constant current generator generating a substantially constant current and distributing said substantially constant current to each of said circuits; and a plurality of converters, each of said converters respectively corresponding to each of said circuits, each of which converts said substantially constant current to said reference voltage and respectively provides said reference voltage to each of said circuits, wherein respectively corresponding first pMOS and second pMOS transistors are serially cascaded, and wherein said second pMOS transistor outputs said substantially constant current to each of said converters.