Patent ID: 7484073
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A method for implementing within a computer processor tagged translation lookaside buffer (“tagged TLBs”) consistency across a virtualized computing environment: virtualizing a plurality of processes of a plurality of logical processors in the virtualized computing environment via a virtual machine monitor or hypervisor component for virtualizing one or more guests including the plurality of logical processors; maintaining, for each address space within a plurality of different logical processors, an epoch and address space identifier (ASID) for each logical processor upon which a guest address space is utilized; maintaining, by the virtual machine monitor or hypervisor component updates to said epoch and ASID values, tagged TLB data consistency associated with the plurality of processes on behalf of each of the plurality of logical processors that ensures the consistency of the tagged TLB data across all of the plurality of processes.