Patent ID: 9218775
Filing Date: 2015-12-22
Classification: G09G

Abstract:
1. A display driving circuit for use in a display device in which by supplying retention capacitor wire signals to retention capacitor wires forming capacitors with pixel electrodes included in pixels, signal potentials written to the pixel electrodes from data signal lines are changed in a direction corresponding to polarities of the signal potentials, the display device comprising: a shift register including a plurality of stages provided in such a way as to correspond to a plurality of scanning signal lines, respectively, said display driving circuit alternately switching between (i) a first mode in which to carry out a display by converting resolution of a video signal by a factor of n at least in a column-wise direction, assuming that a direction in which scanning signal lines extend is a row-wise direction, and (ii) a second mode in which to carry out a display by converting the resolution of the video signal by a factor of m at least in the column-wise direction, n being an integer of two or greater, m being an integer different from n, during the first mode, signal potentials having the same polarity and the same gray scale being supplied to pixel electrodes included in respective n pixels that correspond to n adjacent scanning signal lines and that are adjacent to each other in the column-wise direction, a direction of change in the signal potentials written to the pixel electrodes from the data signal lines varying every n adjacent rows, during the second mode, signal potentials having the same polarity and the same gray scale being supplied to pixel electrodes included in respective m pixel(s) that correspond to m adjacent scanning signal line(s) and that are adjacent to each other in the column-wise direction, and the direction of change in the signal potentials written to the pixel electrodes from the data signal lines varying every m adjacent row(s), the display driving circuit having retaining circuits provided in such a way as to correspond one-by-one to the respective stages of the shift register, a retention target signal being inputted to each of the retaining circuits, an output signal from a current stage and an output signal from a subsequent stage that is later than the current stage being inputted to a logic circuit corresponding to the current stage, when an output from the logic circuit becomes active, a retaining circuit corresponding to the current stage loading and retaining the retention target signal, the output signal from the current stage being supplied to a scanning signal line connected to pixels corresponding to the current stage, and an output from the retaining circuit corresponding to the current stage being supplied as the retention capacitor wire signal to a retention capacitor wire that forms capacitors with pixel electrodes of the pixels corresponding to the current stage, the retention target signal that is inputted to each of the retaining circuits being set according to each of the modes, wherein the output signal from the subsequent stage as inputted during the first mode to the retaining circuit corresponding to the current stage and the output signal from the subsequent stage as inputted during the second mode to the retaining circuit corresponding to the current stage are outputted from different stages from each other.