Patent ID: 6594326
Filing Date: 2003-07-15
Classification: G06F,H04L

Abstract:
A method of synchronizing a control signal, the control signal being synchronous to a second clock, the method comprising the steps of:generating a plurality of intermediate clock signals, each one of said plurality of intermediate clock signals being generated by delaying a first clock, a last one of said plurality of intermediate clock signals being the second clock; receiving the control signal; synchronizing the control signal with one of said of intermediate clock signals to produce one of a plurality of intermediate control signals; synchronizing said one of said plurality of intermediate control signals with another of said plurality of intermediate clock signals to produce another of said plurality of intermediate control signals with a phase corresponding to a phase of said another of said plurality of intermediate clock signals; and repeating said step of synchronizing said one of said plurality of intermediate control signals to produce said plurality of intermediate control signals with phases corresponding to phases of said plurality of intermediate clock signals; whereby the phase of the control signal is incrementally shifted.