Patent ID: 6477652
Filing Date: 2002-11-05
Classification: G06F,H04L

Abstract:
A cryptographic checksum circuit, comprising:a keystream generator configured to generate a secret keystream according to a common secret key, said secret keystream including a string of binary random numbers; a postfix circuit configured to augment a plurality of postfix bits after an original message, thereby generating a postfixed message; a demultiplexer having two output terminals, said demultiplexer being configured to direct the postfixed message to one of the output terminals under the control of the secret keystream; a first mixer configured to receive output of one output terminal of the demultiplexer; a second mixer configured to receive output of the other output terminal of the demultiplexer; a first compression circuit configured to receive an output of said first mixer, wherein content of said first compression circuit is used as a first part of a checksum output; a second compression circuit configured to receive an output of said second mixer, wherein content of said second compression circuit is used as a second part of the checksum output; a first transmission gate configured to receive an output bit of said second compression circuit, said output bit of the second compression circuit being then transferred to said first mixer through said first transmission gate under control of the postfixed message; and a second transmission gate configured to receive an output bit of said first compression circuit, said output bit of the first compression circuit being then transferred to said second mixer through said second transmission gate under control of the postfixed message.