Patent ID: 7194559
Filing Date: 2007-03-20
Classification: G06F

Abstract:
1. A circuit, comprising: a bi-directional data bus; a master I/O driver coupled to a data line of the bi-directional data bus and having a plurality of selectable on-impedance values; a reference voltage generator configured to generate a reference voltage including; a calibration comparator coupled to the master I/O driver and the reference voltage generator, and configured to compare the reference voltage and a voltage on an output of the master I/O driver to generate a calibration comparison; off-chip driver impedance adjustment circuitry configured to generate an impedance adjustment signal in response to the calibration comparison; a slave I/O driver coupled to the data line and having a plurality of selectable on-impedance values; and slave impedance adjustment circuitry coupled to the slave I/O driver, and configured to select an on-impedance value for the slave I/O driver in response to the impedance adjustment signal.