Patent ID: 8908745
Filing Date: 2014-12-09
Classification: H03H,H04L

Abstract:
1. A circuit, comprising: a transmitter filter comprising a quasi digital filter that utilizes digital data as inputs provided to a shift register buffer stage and clocked through the shift register buffer stage in a discrete-time manner and outputs of the shift register buffer stage that are continuous-time analog signals which are weighted and summed in an analog domain; a receiver filter comprising an analog filter; and a communicative coupling between the transmitter filter and the receiver filter; wherein the transmitter filter and the receiver filter are matched for noise reduction, wherein the transmitter filter compensates for non-ideal filtering properties of the receiver filter by adjusting its taps, and wherein the combined responses of the transmitter filter and the receiver filter satisfy the Nyquist criteria; wherein the transmitter filter comprises a pulse shaping quasi digital finite impulse response filter, wherein the transmitter filter is dynamically adaptable to compensate for optical channel distortion impairments; and wherein the receiver filter comprises an inductor-capacitor ladder based filter, wherein only a single separate receiver filter is used per I and Q data streams prior to demodulation and decision slicing of a multi-level, multi-bit modulation formatted signal.