Patent ID: 6324122
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A RAM module synchronizable with a signal, comprising:a memory array having a plurality of memory cells;peripheral circuits, connected with the memory array, controlling the operation of the RAM module, and including peripheral set-up phase circuits controlling the operation of a set-up phase and having a plurality of set-up branches, each with a destination, the branches including a longest set-up branch that is the set-up branch that takes the longest interval of time to communicate with its destination, the longest set-up branch being characterized by a critical set-up time equal to the time needed for a signal to propagate to the destination of the set-up branch; anda signal transition doubler, connected with the peripheral circuits, receiving the signal, and including:a delay circuit that receives the signal as an input and outputs a delayed signal that is delayed by at least the critical set-up time; anda logic circuit that receives the signal and the delayed signal as inputs and in response outputs a signal that has twice as many transitions of the signal.