Patent ID: 6225155
Filing Date: 2001-05-01
Classification: H01L

Abstract:
A method of forming a salicide layer in an embedded dynamic random access memory, comprising the steps of:providing a substrate having a memory region and a logic region;forming a dual polysilicon gate in the logic region and a polysilicon gate on the memory region, wherein the dual polysilicon gate and the polysilicon gate respectively have source/drain regions;forming an insulating layer over the substrate;forming a hard material layer on the insulating layer;forming an inter-layer dielectric layer over the substrate;etching back a portion of the inter-layer dielectric layer to expose a portion of the hard material layer;removing a portion of the inter-layer dielectric layer in the logic region to further expose the hard material layer in the logic region;removing the exposed portion of the hard material layer to expose the insulating layer in the logic region and the insulating layer in the memory region about above the polysilicon gate;removing the exposed portion of the insulating layer to expose the dual polysilicon gate and the source/drain region in the logic region, and the polysilicon gate in the memory region; andforming a salicide layer on the dual polysilicon gate, the source/drain region in the logic region, and the polysilicon gate in the memory region.