Patent ID: 6125067
Filing Date: 2000-09-26
Classification: G11C

Abstract:
A semiconductor memory comprising:first and second sub-arrays; andcircuitry coupled to the first and second sub-arrays adapted to store row addresses of defective rows in the first and second sub-arrays and activate a redundant row in one sub-array of the first and second sub-arrays in response to receiving a row address matching one of the stored defective row addresses while disabling a redundant row arranged in the other sub-array of the first and second sub-arrays in an order complementary to that of the activated redundant row, the circuitry comprising:fuse banks adapted to store the row addresses of defective rows and output a match signal in response to receiving a row address matching one of the stored row addresses of defective rows;first and second row decoders coupled to the respective first and second sub-arrays adapted to activate redundant rows in at least one sub-array of the first and second sub-arrays in response to receiving the match signal; andenable fuses coupled between the fuse banks and the row decoders adapted to conduct the match signal to the first row decoder and isolate the match signal from the second row decoder to disable activation of the redundant row in the second sub-array of the first and second sub-arrays.