Patent ID: 8710557
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A method for fabricating a MOS transistor having a combined-source structure with low power consumption, comprising the following steps: 1) defining an active region over a semiconductor substrate by a shallow isolation; 2) growing a gate dielectric layer; 3) depositing a gate electrode layer, and then forming a main gate pattern and a extending gate pattern by photolithographing and etching the gate electrode layer; 4) performing photolithographing to form a doped source region, and performing an ion implantation by using a photoresist and the gate as a mask to form a highly-doped source region; 5) performing photolithographing to form a doped drain region, and performing an ion implantation by using a photoresist and the gate as a mask to form a highly-doped drain region; and performing a rapid high temperature annealing to activate the doped impurities; 6) performing photolithographing to form a metal region in the source, sputtering a metal layer, and performing a low temperature annealing to form a compound made of the metal and the semiconductor; and then removing the unreacted metal to form a Schottky source region; and 7) performing conventional CMOS subsequent processes, comprising depositing a passivation layer, opening a contact hole, and a metallization, to form the MOS transistor.