Patent ID: 6268813
Filing Date: 2001-07-31
Classification: H03M

Abstract:
A method of testing a charge redistribution analog-to-digital converter; the converter having a binary weighted capacitor array with a plurality of capacitors, each capacitor having a pair of plate, one plate of each capacitor being electrically connected to a common node, a comparator having one input electrically connected to the common node and having an output, and successive approximation logic circuitry electrically connected to the comparator output and the array for selectively connecting the capacitors to one of a high reference voltage, low reference voltage or analog input signal voltage to develop a digital output in a successive charge redistribution conversion process comprising sample, hold and charge redistribution phases; the test method comprising on a single semiconductor chip:providing a test generator for generating a test pattern sequence in the form of a digital signal;connecting said common node to a common mode voltage and concurrently therewith selectively connecting the other plate of each capacitor to one of the high or low reference voltage to charge the capacitors according to a predetermined test pattern sequence provided by said test generator during the sample phase, said logic circuitry responsive to said test pattern sequence for connecting said plates of said capacitor to one of the high or low reference voltage;then disconnecting said common node from said common mode voltage and concurrently commonly connecting said other plate of each capacitor to the low reference voltage during a hold phase;then returning said common node to said common mode voltage to provide a digital output; andcomparing said digital output to an expected output for the predetermined test pattern sequence which is the original test pattern sequence.