Patent ID: 6606701
Filing Date: 2003-08-12
Classification: G06F

Abstract:
A micro-processor comprising:(a) a pre-fetch queue FIFO which fetches and stores therein a command code; (b) a pre-fetch queue valid indicating that an effective command code is stored in said pre-fetch queue FIFO; (c) an access priority judging circuit receiving a pre-fetch request signal indicating that there is vacancy in said pre-fetch queue FIFO, a queue empty signal indicating that said pre-fetch queue FIFO is entirely empty, and an operand data request signal indicating that there has been generated an operand data access, and determining a kind of next bus access; (d) a bus state control circuit transmitting a bus interface signal, based on said kind of next bus access having been determined by said access priority judging circuit, and also transmitting a burst transfer signal indicating that a memory is in a condition for carrying out burst transfer; and (e) an access register storing data about the previous bus access, said access priority judging circuit taking a command fetch access in preference to an operand data access in the next bus access when data stored in said access register is a command fetch access, and said pre-fetch request signal, said operand data request signal, and said burst transfer signal are all transmitted.