Patent ID: 6414689
Filing Date: 2002-07-02
Classification: G06F,G09G

Abstract:
A First-In-First-Out (FIFO) interface apparatus coupled to a Central Processing Unit (CPU), a Graphics Engine (GE), and a frame buffer, the FIFO interface apparatus comprising a write FIFO buffer coupled to the GE and the frame buffer, the write FIFO buffer transferring data packets generated by the GE to the frame buffer, wherein each data packet comprising a predetermined number of data bytes processed by the GE, a first address flag bit, and a second address flag bit, the first and second address flag bits are used to determine a next write address in the frame buffer for storing the predetermined data bytes from an immediately subsequent data packet, the first address flag bit indicating whether the predetermined number of data bytes in each data packet are to be added to a present write address to determine the next write address, the second address flag bit indicating whether a number of bytes contained in a scan line are to be added to an updated starting write address to determine the next write address.