Patent ID: 6314495
Filing Date: 2001-11-06
Classification: G06F

Abstract:
An apparatus including a data processing system that avoids deadlocks while processing an operation from a system bus which can be sourced by at least one of a plurality of processors and initiated at least once from the same processor, the apparatus comprising:a plurality of caches each associated with one of said multiple processors;a plurality of snooping means, included in each of said plurality of caches, for processing snooped operations on the system bus, each one of the snooping means including:address means for indicating which instance of an operation the snooping means is currently processing;source means for indicating what processor sourced the operation the snooping means is currently processing;means for determining when a condition is present on the system bus, the condition including an absence of retry relative to the operation on said system bus; andprocessing means to ensure that, based on said condition, each of the other processors have finished processing the current operation before proceeding to indicate that the operation has been completed, thereby causing said operation to be accepted by said plurality of snooping means at the same time according to the presence of said condition on said system bus.