Patent ID: 7894279
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A semiconductor storage device precharging a bit line pair to a ground potential, the semiconductor storage device comprising: a sense amplifier connected between the bit line pair; a storage cell connected to one of the bit line pair and storing data; a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node; a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor being controlled from the first transistor; and a capacitor setting a potential of the reference cell node, wherein the semiconductor storage device aids charge and discharge of the capacitor when the second transistor is in the conduction state by using a negative-phase current of a current flowing between the reference cell node and the second transistor, the capacitor is connected between a bias node and the reference cell node and sets the potential of the reference cell node according to a stored charge amount, the bias node being supplied with a bias voltage generated by a bias voltage generating circuit, and the reference cell node and the bias node are electrically connected when the second transistor is in the conduction state so that the negative-phase current of the current flowing between the reference cell node and the second transistor is generated to aid the charge and the discharge of the capacitor.