Patent ID: 8885392
Filing Date: 2014-11-11
Classification: G11C

Abstract:
1. A memory circuit, comprising: a first inverter and a second inverter having a first connection and a second connection to each other, the first inverter and the second inverter disconnected from a potential source of power, wherein an output of the first inverter is coupled to an input of the second inverter to form the first connection, wherein an output of the second inverter is coupled to an input of the first inverter to form the second connection, wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor, wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are coupled to the first connection and wherein a drain of the first PMOS transistor and a drain of the first NMOS transistor are coupled to the second connection; a first programmable switch coupled to the first connection; and a second programmable switch coupled to the second connection, wherein the first programmable switch is coupled to a first voltage level so that the memory circuit carries a logic low value and coupled to a second voltage level so that the memory circuit carries a logic high value, and the second programmable switch is coupled to the second voltage level so that the memory circuit carries the logic low value and coupled to the first voltage level so that the memory circuit carries the logic high value, wherein each of the first programmable switch and the second programmable switch includes one from a set consisting of a via switch and a metal programmable switch, and wherein both the first programmable switch and the second programmable switch are programmed contemporaneously.