Patent ID: 6441635
Filing Date: 2002-08-27
Classification: G01R

Abstract:
A method for testing integrated circuits present on a wafer, in which a plurality of elementary test steps are classified into statistically essential tests and statistically secondary tests and both a full test sequence for an integrated circuit, which includes both the statistically essential elementary tests and the statistically secondary elementary tests, and a limited test sequence for an integrated circuit, which includes only statistically essential elementary test steps, are defined, wherein the method includes a test loop comprising:testing K integrated circuits on the wafer in a first test step by application of the full test sequence to each integrated circuit; if a number of integrated circuits failing at least one statistically secondary elementary test during the first test step is smaller than a predetermined number Q1, testing N integrated circuits following the K integrated circuits on the wafer in a next test step by application of the limited test sequence to each integrated circuit; and if the number of integrated circuits failing at least one statistically secondary elementary test during the first test step is greater than or equal to the predetermined number Q1, testing M integrated circuits following the K integrated circuits on the wafer in the next test step by application of the full test sequence to each integrated circuit.