Patent ID: 6509784
Filing Date: 2003-01-21
Classification: H02M

Abstract:
An integrated circuit (IC) for providing an enabling signal (EN) to a converter, said integrated circuit (IC) comprising:a monitoring circuit (FET1, R2, D1, Io, M, S1) for providing a control signal (CS) in response to a level of a line voltage (Vline) on a first connection terminal (8) of the integrated circuit (IC), and a start-up circuit (FET2, Istrt_up, Vcc_strt-Lev, COMP, S2) for providing the enabling signal (EN) to the converter in response to the control signal (CS) and a generated voltage level (Vcc), said generated voltage level (Vcc) being generated in response to the level of the line voltage (Vline) on the first connection terminal (8), wherein the monitoring circuit and the start-up circuit are sensing the level of the line voltage (Vline) only via the first connection terminal (8, and wherein the monitoring circuit (FET1, R2, D1, Io, M, S1) comprises: a first transistor means (FET1) connected to the first connection terminal (8), current limiting means (R2) connected to the first transistor means (FET1), a voltage limiting device (D1) having a breakdown voltage, said voltage limiting device (D1) being connected to the current limiting means (R2) so that current may be drawn through the first transistor means (FET1), the current limiting means (R2) and the voltage limiting device (D1) when the breakdown voltage across the voltage limiting device (D1) has been exceeded, a reference current source (Io) for providing a reference current, means (M) for comparing the current drawn through the first transistor means (FET1), the current limiting means (R2) and the voltage limiting device (D1) with the provided reference current (Io), and to generate the control signal (CS) when the current drawn through the first transistor means (FET1), the current limiting means (R2) and the voltage limiting device (D1) exceeds the reference current (Io), and a controllable first switching means (S1) for providing, in its closed position, essentially zero voltage across the voltage limiting device (D1) and thereby reduce the current drawn through the first transistor means (FET1) and the current limiting means (R2).