Patent ID: 6724257
Filing Date: 2004-04-20
Classification: H02M

Abstract:
An error amplifier circuit comprising:a differential amplifier receiving a first input signal and a second input signal, said differential amplifier generating an output signal on an output terminal indicative of the difference between said first input signal and said second input signal; a cascode gain stage coupled to received said output signal of said differential amplifier and generating a second output signal, said cascode gain stage being biased by a bias current generated by a current mirror; and an amplifier receiving said second output signal from said cascode gain stage and generating a third output signal; wherein said cascode gain stage is biased by a control signal for causing said current mirror to generate said bias current having substantially constant magnitude over variations in voltage differences of said first input signal and said second input signal; and wherein said differential amplifier comprises: a first transistor having a control terminal coupled to receive said first input signal, a first current handling terminal coupled to a second bias current and a second current handling terminal coupled to a second current mirror; and a second transistor having a control terminal coupled to receive said second input signal, a first current handling terminal coupled to said second bias current and a second current handling terminal coupled to said second current mirror; wherein said second current handling terminal of said first transistor and said second transistor form said output terminal of said differential amplifier.