Patent ID: 7474716
Filing Date: 2009-01-06
Classification: H04L

Abstract:
1. An improved data recovery circuit for recovering the data sample in a set of data samples obtained by oversampling the data to recover in an incoming stream of data bits in which the maverick data edge are detected and suppressed comprising: a data input for receiving said incoming stream of data bits serially transmitted on a high speed communication link with jitter and skew at a specified data rate synchronous with a reference clock; oversampling means coupled to said data input to sample the data bits to recover by the n phases (C edge detection means coupled to said oversampling means and configured to compare at least two consecutive data samples and to generate a corresponding set of signals (E first memory means coupled to said edge detection means and configured to collect the data edge information in a corresponding set of signals (E′ maverick edge detection/suppression means coupled to said first memory means; selection determination means coupled to said maverick edge detection/suppression means and configured to use the memorized data edge information signals to generate selection signals (S selection validation means coupled to said selection determination means to validate said selection signals and generating validated selection signals (VS second memory means coupled to said selection validation means to memorize the validated values of said selection signals in a corresponding set of signals (MVS data sample selection means coupled to said oversampling means to receive the data samples (D