Patent ID: 6172526
Filing Date: 2001-01-09
Classification: H03K

Abstract:
A semiconductor interface circuit connected between a first semiconductor device driven by a first level power voltage and a second semiconductor device driven by a second level power voltage which is higher than said first level power voltage, said semiconductor interface circuit comprising:an output buffer circuit being connected to said first semiconductor device; andat least a depletion type field effect transistor connected between said output buffer circuit and said second semiconductor device,wherein said at least depletion type field effect transistor has a driving capability substantially equal to or near a driving capability of said output buffer circuit;wherein said output buffer circuit is provided within a first rectangular region defined by a common width and a first length, and said at least depletion type field effect transistor is provided within a second rectangular region defined by said common width and a second length, and said first and second rectangular regions are aligned in a length direction to form a semiconductor interface circuit rectangular-shaped cell unit defined by a standardized size of said common width and a sum of said first and second lengths.