Patent ID: 8559224
Filing Date: 2013-10-15
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device comprising: a memory cell array including a substrate and a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to the substrate, each of the plurality of memory cells further including at least one separator, separating the memory cells into a plurality of sub blocks being separately erasable, wherein the plurality of memory cells form a plurality of strings, each string including at least two memory cells stacked in the direction perpendicular to the substrate, and wherein each string includes an active pillar forming a channel of the at least two memory cells and extending in the direction perpendicular to the substrate, at least two conductors forming gates of the at least two memory cells and surrounding the active pillar in each string, and the at least one separator separating the at least two memory cells.