Patent ID: 6441434
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor layer having source, drain, and body regions which are operatively coupled together; a gate operatively coupled with the source, drain, and body regions; and a first electrically-conducting region within the source and body regions, the first electrically-conducting region electrically coupling the source region and the body region; a second electrically-conducting region, wherein the second electrically-conducting region is at least partially within the drain region; wherein the source and drain regions each have a deep-doped subregion, the deep-doped subregions being asymmetric with one another about the gate; wherein the source and drain regions have respective shallow-doped subregions, and wherein the shallow-doped subregions are symmetric with one another about the gate; wherein the electrically-conducting regions are symmetric with one another about the gate; and wherein the electrically-conducting regions are semiconductor-metal compound.