Patent ID: 6194247
Filing Date: 2001-02-27
Classification: H01L,H05K,Y10S

Abstract:
A method of forming a warp-resistant integrated circuit package, comprising the steps of:(a) providing an integrated circuit package, said package having an integrated circuit die disposed within said package;(b) selecting a neutral thermodynamic axis to coincide with a plane approximately through the center of said die;(c) providing a first layer of material for said package, said first layer of material having a first coefficient of thermal expansion (CTE);(d) providing a second layer of material for said package, said second layer of material having a second CTE;wherein said first and second layers of material are disposed about said selected axis such that the thickness and orientation of said first and second layers are selected in relation to each other and to said other material layers comprising said package, and in relation to said related axis, such that the vectorial summation of all moments of each said layer about said axis is as close to zero as possible; andwherein the dimensions of each said layer is calculated using the equation:m.apprxeq.(E)(h)(t).DELTA.(a).DELTA.(T)where m is the moment of the layer; E is the Young's modulus of elasticity of the layer material; h is the moment-arm distance of the center of the layer from the neutral thermodynamic axis; t is the layer thickness; .DELTA.(a) is the difference in CTE between the layer and the material containing the neutral thermodynamic axis; and .DELTA.(T) is the temperature difference between assembly bonding temperature and operation temperature.