Patent ID: 6867103
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device comprising: providing a SOI substrate comprising a doped silicon layer and a buried oxide layer wherein said doped silicon layer comprises a first type and overlies said buried oxide layer; implanting ions into said SOI substrate to form higher concentration regions in said doped silicon layer wherein said higher concentration regions comprise said first type and are closer to the buried oxide layer than to the top surface of the doped silicon layer; forming MOS gates comprising an electrode layer overlying said doped silicon layer with a gate oxide layer therebetween wherein said higher concentration regions underlie and span the lateral length of said MOS gates; and forming source and drain regions in said doped silicon layer to complete said transistors in the manufacture of said integrated circuit device wherein said source and drain regions contact said higher concentration regions and comprise a second type.