Patent ID: 7188289
Filing Date: 2007-03-06
Classification: G01R

Abstract:
1. A test circuit for testing a test target circuit and outputting a test result to a tester, comprising: a test target circuit; a built-in self-test circuit connected to the test target circuit and performing a test of the test target circuit; a first clock generator supplying a first clock to the test target circuit and the built-in self-test circuit; a tester synchronous circuit receiving a test result from the built-in self-test circuit and outputting the test result in synchronization with the tester; and a second clock generator supplying a second clock with a lower frequency than the first clock to the tester synchronous circuit, wherein the built-in self-test circuit repeats the test the number of times determined by the first clock and the second clock, and the tester synchronous circuit selects and outputs a test result so as to output all test results from the built-in self-test circuit.