Patent ID: 6355982
Filing Date: 2002-03-12
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device comprising:a memory cell array in which memory cells of a static type are arranged in a matrix; a plurality of pairs of bit lines extending in a column direction of the memory cell array, each of said pairs of bit lines being connected in common to memory cells on a same column of the memory cell array; a plurality of word lines extending in a row direction of the memory cell array, each word line being connected in common to memory cells on a same row of the memory cell array; a plurality of grounded lines disposed on both sides of each pair of bit lines in a direction parallel to the bit lines, for supplying a ground potential to the memory cells, formed of a layer same as that of the pairs of bit lines and extending in the column direction; and power supplying lines, for supplying a power potential to the memory cells, formed of a conductive layer other than a diffusion layer, the conductive layer being different from that of the pairs of bit lines and extending in the row direction.