Patent ID: 7984397
Filing Date: 2011-07-19
Classification: G06F,Y02E,Y04S

Abstract:
1. A method of automatically reducing stacked vias in a power network of an integrated circuit (IC), the method comprising: determining an IC design, a power network of the IC design, a target voltage drop of the power network, and congestion information based on the IC design and the power network; identifying any connectivity-necessary stacked vias and uncongested stacked vias of the power network based on the congestion information, the connectivity-necessary stacked vias being stacked vias necessary for power connectivity, and the uncongested stacked vias being stacked vias in uncongested areas of the IC; virtually removing any feasible stacked vias of the power network, wherein feasible stacked vias are other than connectivity-necessary stacked vias and uncongested stacked vias; determining whether the target voltage drop is exceeded in the power network; when the target voltage drop is exceeded, updating a measurement of a severity of at least a maximum voltage drop on the IC; after updating, virtually returning a set of voltage drop improvement stacked vias to the power network, the set of voltage drop improvement stacked vias being a subset of the feasible stacked vias; using a computer, repeating determining, updating, and virtually returning until the target voltage drop is not exceeded; physically removing any stacked vias of the power network other than connectivity-necessary stacked vias, uncongested stacked vias, and voltage drop improvement stacked vias; and outputting the power network with reduced stacked vias.