Patent ID: 6043678
Filing Date: 2000-03-28
Classification: H03K

Abstract:
An input circuit comprising:an input terminal which receives an external signal;a first power terminal which receives a first electric potential;a second power terminal which receives a second electric potential which is lower than said first electric potential of said first power terminal;an inverting buffer which inverts a logic level of said external signal and propagates an output signal in response thereto;a first bipolar transistor which propagates said external signal from said input terminal to said buffer after said external signal falls from a logic high level to a logic low level;a second bipolar transistor which propagates said external signal from said input terminal to said buffer after said external signal rises from said logic low level to said logic high level;a first electric current cut off switch which cuts off an electric current route formed between said first bipolar transistor terminal when said buffer outputs said logic high level;a second electric current cut off switch which cuts off an electric current route formed between said second bipolar transistor and said second power terminal when said buffer outputs said logic low level; anda voltage clamping circuit which provides an electric potential which is lower than the electric potential of said first power terminal to said second electric current cut off switch.