Patent ID: 6724671
Filing Date: 2004-04-20
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of memory elements each of which stores a binary information corresponding to an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated from said semiconductor substrate, and each of which including a source and a drain formed on said semiconductor substrate; and a power source unit applying an approximately same voltage to said sources and said drains in a test mode operation for judging whether the electric charge injected into said floating gates in advance can be held or not, wherein said power source unit includes a power source applying a predetermined voltage to said drains in the test mode operation, and a switching element inserted between said power source and said sources, in order to apply a predetermined same voltage to said sources and said drains by using said power source as a common power source in the test mode operation, wherein a plurality of bit lines are each electrically connected to respective ones of said plurality of memory elements and said switching element, and wherein said switching element is formed of an element having a same structure as an element forming said memory elements.