Patent ID: 6323680
Filing Date: 2001-11-27
Classification: G06F,H03K

Abstract:
A programmable logic device comprising:a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; andan interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions; wherein:each region in at least a subset of said plurality of regions of programmable logic has additional logic dedicated to the performance of functions forming at least part of a multiplication operation; andsaid additional logic comprises a first logic unit for performing at least portions of both (i) two partial products of two multiplicands and (ii) summing said two partial products.