Patent ID: 9198281
Filing Date: 2015-11-24
Classification: G06F,H01L,H05K

Abstract:
1. A leadframe for semiconductor packages, comprising: a die pad; a side rail around the die pad; a tie bar connecting the die pad and the side rail; and a plurality of leads extending from the side rail in close proximity to the die pad, comprising a first lead with no branch and a second lead being at opposite locations of the leadframe relative to a center line through the die pad, wherein the first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values, wherein the plurality of leads are spaced apart from each other, and the plurality of leads further comprise a third lead adjacent to the first lead, and fourth lead adjacent to the second lead, wherein the plurality of leads are directly and electrically connected to a chip attached on the die pad through a plurality of bonding wires, and each of the first and second leads is connected to a different one of the plurality of bonding wires, wherein a pitch between the first and third leads is different from a pitch between the second and fourth leads.