Patent ID: 7091540
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A memory cell of a semiconductor device, comprising: a substrate having active regions and field regions; a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate; first self-aligned contact regions (BC SAC region) formed between adjacent pass gates and access gates; and second self-aligned contact regions (DC SAC region) formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions, and wherein the width of each of the first self-aligned contact regions is made larger than the width of each of the second self-aligned contact regions by each one of the plurality of access gates having a width smaller than a width of an adjacent pass gate.