Patent ID: 6873534
Filing Date: 2005-03-29
Classification: H05K,Y02P

Abstract:
1. A memory module comprising: a generally planar printed circuit board comprising an edge, a common signal trace connector area along the edge, and a first side, the printed circuit board having a first lateral portion and a second lateral portion; a first row of memory integrated circuits identical to one another, the first row positioned on the first side of the printed circuit board, the first row being in proximity to the common signal trace connector area, the integrated circuits of the first row having a first orientation direction, the first row having a first number of integrated circuits on the first lateral portion and a second number of integrated circuits on the second lateral portion; a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row being located physically farther from the common signal trace connector than is the first row, the integrated circuits of the second row having a second orientation direction at a non-zero angle relative to the first orientation direction, the second row having a third number of integrated circuits on the first lateral portion and a fourth number of integrated circuits on the second lateral portion; a first addressing register comprising at least one register integrated circuit, the first addressing register coupled to the integrated circuits of the first row on the first lateral portion and coupled to the integrated circuits of the second row on the first lateral portion; a second addressing register comprising at least one register integrated circuit, the second addressing register coupled to the integrated circuits of the first row on the second lateral portion and coupled to the integrated circuits of the second row on the second lateral portion, wherein the first addressing register and the second addressing register access data bits of non-contiguous subsets of a data word; a first plurality of data lines electrically connecting data pins of the first row of integrated circuits to the common signal trace connector area; and a second plurality of data lines electrically connecting data pins of the second row of integrated circuits to the common signal trace connector area, whereby lengths of corresponding data lines of the first plurality of data lines and the second plurality of data lines are substantially the same.