Patent ID: 6154512
Filing Date: 2000-11-28
Classification: H03L,H04L

Abstract:
A digital phase locked loop (DPLL) for synchronizing a local data clock with timing information from received data, during a fraction of a frame period, comprising:a transition detect unit for detecting the bit transitions of said received data;a digital phase comparator electrically coupled to said transition detect unit for determining the phase difference between said timing information and said local data clock;a phase regulator electrically coupled to said digital phase comparator and a local clock source for advancing or retarding said local data clock; anda control unit for enabling and disabling said synchronizing in accordance with a predetermined rate, wherein said predetermined rate is a function of a predetermined disable period of time (Td), a predetermined enable period of time (Te), said local clock source (LCS), and said local data clock (LDC), thereby synchronizing said local data clock with timing information from received data, during a fraction of a frame period.