Patent ID: 6457163
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A computer-implemented method for symbolically representing a physical integrated circuit layout of a multiple-gate semiconductor device, the layout being comprised of a plurality of gate glue-blocks interconnected by a plurality of active-layer glue-blocks, the method comprising the machine-executed steps of:(a) automatically creating working shapes of the gate glue-blocks according to user-defined gate glue-block parameters; and (b) automatically creating working shapes of the active-layer glue-blocks in accordance with the working shapes of adjacent ones of the gate glue-blocks, including the machine-executed steps of extracting relevant design rules of an applied fabrication technology from a fabrication technology file to determine minimum geometrical distances among the working shapes, and creating the working shapes of the active-layer glue-blocks such that the distances among the working shapes exceed the minimum geometrical distances as defined by the relevant design rules.