Patent ID: 6097658
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A DRAM having a plurality of memory cells comprising:a data read/write circuit reading or writing data for the memory cells;a self-refresh circuit refreshing data stored in the memory cells;power supply unit which supplies electric power to said data read/write circuit and said self-refresh circuit, said electric power having an equal voltage level in a normal operation mode as well as in a self-refresh mode;pre-charge unit which pre-charges bit lines with half of said equal voltage level in tile normal operation mode and half of said equal voltage level in the self-refresh mode, wherein the bit lines are connected to the memory cells for reading and writing data; andcapacitors each connected to a corresponding one of the bit lines for absorbing charges of the bit lines in the self-refresh mode after said pre-charge unit pre-charges the bit lines so that a voltage level of the bit lines can become lower than half of said equal voltage level.