Patent ID: 8164372
Filing Date: 2012-04-24
Classification: G11C,H03L

Abstract:
1. A semiconductor device comprising: a data output terminal; a Delay Locked Loop (DLL) circuit that generates a first internal clock signal having a first voltage amplitude based on an external clock signal; a first level shift circuit that converts the first internal clock signal into a second internal clock signal having a second voltage amplitude; a second level shift circuit that converts first internal data signals having the first voltage amplitude into second internal data signals having the second voltage amplitude; a clock dividing circuit that generates a plurality of select clock signals including at least a third internal clock signal and a fourth internal clock signal having the second voltage amplitude with different phases from each other based on the second internal clock signal; and an output circuit that sequentially outputs external data signals having the second voltage amplitude from the data output terminal in synchronization with the select clock signals based on the second internal data signals.