Patent ID: 8421128
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a first highly doped semiconductor region located directly beneath a top surface of a semiconductor substrate; a second highly doped semiconductor region located directly beneath said top surface of said semiconductor substrate and disjoined from said first highly doped semiconductor region; at least one doped semiconductor region located directly beneath said top surface of said semiconductor substrate and laterally abutting said first highly doped semiconductor region and said second highly doped semiconductor region; a middle-of-line (MOL) dielectric layer located on and above said semiconductor substrate; at least one thermally conductive via located above and vertically abutting said at least one doped semiconductor region, embedded within said MOL dielectric layer, and comprising a conductive material; metal contacts embedded within said MOL dielectric layer and connected to said first highly doped semiconductor region and said second highly doped semiconductor region; at least one wiring level dielectric layer located above said at least one thermally conductive via and said metal contacts; and back-end-of-line (BEOL) wiring structures including metal lines and metal vias, located above a top surface of said at least one thermally conductive via, and connecting said metal contacts to other semiconductor devices or input/output pads, wherein said at least one doped semiconductor region, said first highly doped semiconductor region, and said second highly doped semiconductor region are the only conductive components which are located in said semiconductor substrate and to which said at least one thermally conductive via is electrically connected, wherein said first highly doped semiconductor region has a doping of a first conductivity type, said second highly doped semiconductor region has a doping of a second conductivity type, said second conductivity type is the opposite of said first conductivity type, and said at least one doped semiconductor region is a single doped semiconductor region.