Patent ID: 6483157
Filing Date: 2002-11-19
Classification: H01L,Y10S

Abstract:
A transistor, comprising:a gate oxide interposed between a silicon substrate and a polysilicon gate conductor, said gate conductor and said gate oxide having a pair of opposed, first and second sidewall surfaces, wherein the sidewall surfaces of said gate oxide and said gate conductor are substantially aligned, and wherein said gate oxide comprises a plurality of barrier atoms; a first implant region arranged within said silicon substrate and aligned on one side with said first sidewall surface; a second implant region arranged within said silicon substrate and aligned on one side with said second sidewall surface; and a third implant region arranged within said silicon substrate and extending within the second implant region and aligned on one side a spaced lateral distance from said second sidewall surface; wherein said second implant region comprises a lightly doped drain (LDD) species arranged at a concentration level less than species arranged within the first and third implant regions.