Patent ID: 6457162
Filing Date: 2002-09-24
Classification: G06F

Abstract:
A method for circuit verification, comprising:partitioning a first circuit into a first number of partitions, wherein the first number of partitions of the first circuit are ordered, from a first partition to a last partition, in order of increasing structural dependence; partitioning a second circuit into the first number of partitions, wherein the first number of partitions of the second circuit are ordered, from a first partition to a last partition, in order of increasing structural dependence; selecting a consequent partition of the first circuit and a consequent partition of the second circuit; selecting an antecedent partition of the first circuit that is less structurally dependent than the consequent partition of the first circuit and an antecedent partition of the second circuit that is less structurally dependent than the consequent partition of the second circuit; and verifying equivalency of the consequent partition of the first circuit and the consequent partition of the second circuit by determining veracity of an implication, wherein an antecedent of the implication includes an assertion that the antecedent partition of the first circuit and the antecedent partition of the second circuit are equivalent and a consequent of the implication includes an assertion that the consequent partition of the first circuit and the consequent partition of the second circuit are equivalent.