Patent ID: 8319257
Filing Date: 2012-11-27
Classification: G06F,H01L

Abstract:
1. A semiconductor device, comprising: a first transistor region including a first active region and a plurality of first gate electrodes extending in a first direction, the plurality of first gate electrode sharing the first active region; a second transistor region including a second active region and a plurality of second gate electrodes extending in the first direction, the plurality of second gate electrode sharing the second active region; dummy gate patterns extending in the first direction and sandwiching the first transistor region and the second transistor region, the dummy gate patterns being arranged in parallel with the plurality of first gate electrodes and the plurality of second gate electrodes; and a shared dummy gate pattern extending in the first direction and located between the first and second transistor regions and being adjacent to the first transistor regions and to the second transistor regions, wherein: a width of the first active region in the first direction at a first gate electrode which is a closest gate electrode to the shared dummy pattern among the plurality of first gate electrodes is longer than a width of the second active region in the first direction at a second gate electrode which is a closest gate electrode to the shared dummy pattern among the plurality of second gate electrodes, a first gate width of the first gate electrode on the first active region in the first direction is longer than a second gate width of the second gate electrode on the second active region in the first direction, a length of the shared dummy gate pattern in the first direction is equal to or longer than the first gate width, and is longer than the second gate width, the dummy gate patterns includes a first dummy gate pattern and a second dummy gate pattern, the first dummy gate pattern and the shared dummy gate pattern sandwiches the first transistor region, and the second dummy gate pattern and the shared dummy gate pattern sandwiches the second transistor region, and a length of the first dummy gate pattern in the first direction is longer than a length of the second dummy gate pattern in the first direction.