Patent ID: 6175533
Filing Date: 2001-01-16
Classification: G11C

Abstract:
An integrated circuit having an array of memory cells, each for storing a data bit corresponding to one of a low and a high voltage, each memory cell comprising:(a) a memory element coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit;(b) at least one write-access port, each write-access port comprising a write-access switch having an input terminal coupled to a data input line, an output terminal coupled to the data node, and a control terminal coupled to a write control line for switching the write-access switch on or off to provide a write-data bit from the data input line to the write-access port; and(c) a preset switch having a first terminal coupled to the inverse data node, a second terminal coupled to a low voltage source sufficient to cause the data node to store a logic-1 data bit when the preset switch is on, and a preset control terminal for switching the preset switch on or off in response to a write preset signal applied thereto;the integrated circuit further comprising memory control logic for generating the write preset signal such that the write preset signal switches the preset switch on before each write of a write-data bit to the memory cell via the write-access port to precharge the data node to the high voltage before writing the write-data bit to the memory cell, and for providing a write control signal to the write control line, after said preset switch precharges the data node, that switches on the write-access switch to write the write-data bit to the precharged data node.