Patent ID: 6740934
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A structure for electrostatic discharge (ESD) protection of the output of an integrated circuit with resistor loading, comprising:resistive means coupled between output pad and an integrated circuit, said resistive means protecting said integrated circuit from receiving an excess of current; a MOS transistor of a first conductivity type comprising a source, a drain, and a gate, the drain and source of said MOS transistor coupled between the junction of said resistive means and said integrated circuit, and a power supply return terminal, respectively, said MOS transistor deposited in a region of a second conductivity type of a semiconductor substrate, where the gate of said MOS transistor is in communication with said power supply return terminal; a heavily doped region of first conductivity type deposited adjacent to the drain of said MOS transistor in said region, said heavily doped region coupled to said output pad; a first parasitic bipolar transistor of first conductivity type, having an emitter, a collector, and a base, created by the source and the drain of said MOS transistor, and said region of a second conductivity type, respectively, said first parasitic bipolar transistor of first conductivity type coupled to said output pad via said resistive means; a second parasitic bipolar transistor of first conductivity type, having an emitter, a collector, and a base, created by the source of said MOS transistor, said heavily doped region, and said region of a second conductivity type, respectively, said second parasitic bipolar transistor of first conductivity type connected directly to said output pad.