Patent ID: 7902008
Filing Date: 2011-03-08
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a stressed MOS device in and on a semiconductor substrate comprising the steps of: forming a gate electrode overlying the semiconductor substrate; etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode; selectively growing a stress inducing material in the first trench and in the second trench to create a stress condition in the semiconductor substrate; ion implanting conductivity determining impurity ions into the stress inducing material to form a source region in the first trench and a drain region in the second trench, wherein the gate electrode defines a channel region in the semiconductor substrate between the source region and the drain region; and forming a layer of mechanically hard material overlying and in direct contact with a substantially planar surface of the stress inducing material after the step of ion implanting conductivity determining impurity ions into the stress inducing material to form the source region and the drain region and before any step comprising heating to a temperature greater than about 600° C. to prevent dislocation nucleation at the substantially planar surface of the stress inducing material during subsequent heating steps; and then electrically activating the conductivity determining impurity ions in the source region and the drain region by heating the stress inducing material to a temperature greater than about 600° C. after the step of forming the layer of mechanically hard material without decreasing stress applied along the channel region by the stress inducing material.