Patent ID: 7138830
Filing Date: 2006-11-21
Classification: H03K

Abstract:
1. An output buffer having an input node and an output node, comprising: a first pair of output drive transistors connected in series by their sources and drains between two nodes of a power supply providing power having a supply voltage, comprising a first pull-up transistor and a first pull-down transistor, each of the first pair of transistors having a gate, the common connection node of the first pull-up transistor and the first pull-down transistor being connected to the output node; a logic circuit configured to receive an input signal at a logic level and to control the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node; a second pair of output drive transistors connected in series by their sources and drains between the two nodes of the power supply, comprising a second pull-up transistor and a second pull-down transistor, each of the second pair of transistors having a gate, the common connection node of the second pull-up transistor and the second pull-down transistor being connected to the output node; a first control circuit configured to provide an output having a first logic value when the supply voltage is above a predetermined level, and to provide an output having a second logic value when the supply voltage is below the predetermined level, the first control circuit comprising a second control circuit responsive to the output of the control circuit and configured to receive the input signal and to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit has the second logic value.