Patent ID: 8332727
Filing Date: 2012-12-11
Classification: G06F

Abstract:
1. A flash memory system comprising: a flash memory comprising a plurality of flash memory cells, the cells comprising a main cell that stores main data and a parity cell that stores parity data; an error correction circuit (ECC) configured to receive codewords comprising the stored main data and a corresponding one of the stored parity data and perform error correction on a received codeword by executing an operation on a finite field corresponding to the codeword, wherein an element of the finite field comprises a codeword from an erased page of the flash memory, wherein the ECC comprises an ECC decoder that performs error correction on the received codewords, and the ECC decoder comprises: an error detection unit that includes at least one of an addition operator and a multiplication operator and detects errors in the received codewords, the addition operator executes an XNOR operation on the finite field and the multiplication operator executes at least one of an XNOR operation and an OR operation on the finite field, wherein the codeword from the erased page of the flash memory serves as an identity element for addition in the operation on the finite field, and wherein all bits of the codeword from the erased page have a value corresponding to “1”, wherein the multiplication operator comprises: a second inverter inverting output of the operation unit and outputting the inverted output.