Patent ID: 8188767
Filing Date: 2012-05-29
Classification: H03K

Abstract:
1. A method for designing a logic circuit for performing a given logic function, said logic circuit to be constructed from interconnected logic elements, said logic elements comprising: a common logic input; a first dedicated logic terminal; a second dedicated logic terminal; a high-voltage terminal configured for connection to a high constant voltage, wherein said high-voltage terminal is separate from said first dedicated logic terminal and from said second dedicated logic terminal; a low-voltage terminal configured for connection to a low constant voltage, wherein said low-voltage terminal is separate from said first dedicated logic terminal and from said second dedicated logic terminal; a p-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; and an n-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; said common logic input being connected to said gate connection of said p-type transistor and to said gate connection of said n-type transistor, said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal, and said bulk connection of said p-type transistor to said high-voltage terminal, said bulk connection of said n-type transistor to said low-voltage terminal, said method comprising the steps of: setting a synthesized function equal to said given logic function; and performing a synthesis recursion cycle comprising: if said synthesized function comprises a single non-inverted logic variable, providing a logic circuit design comprising an input terminal for said non-inverted logic variable and discontinuing said synthesis recursion cycle; if said synthesized function comprises a high logic signal, providing a logic circuit design comprising a connection to a high logic level, and discontinuing said synthesis recursion cycle; if said synthesized function comprises a low logic signal, providing a logic circuit design comprising a connection to a low logic level, and discontinuing said synthesis recursion cycle; and if said synthesized function comprises either an inverted single variable or a multi-variable function, performing the steps of: extracting a first logic function, and a second logic function from a Shannon expansion of said synthesized function for a selected logic variable; setting said synthesized function to said first logic function; performing a synthesis recursion cycle to obtain a circuit design for a first sub-circuit; setting said synthesized function to said second logic function; performing a synthesis recursion cycle to obtain a circuit design for a second sub-circuit; providing a logic circuit design comprising a logic element having an input terminal for said selected logic variable at a common terminal of a logic element, an output of said first sub-circuit connected to the first dedicated logic terminal of said logic element, an output of said second sub-circuit connected to the second dedicated logic terminal of said logic element, and a circuit output at the common diffusion logic terminal of said logic element; and discontinuing said synthesis recursion cycle.