Patent ID: 8828795
Filing Date: 2014-09-09
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor package, the method comprising: preparing a base substrate, the base substrate including a semiconductor chip mounting region; forming a first connection terminal, a second connection terminal, and a third connection terminal on the base substrate, the first, second, and third connection terminals being adjacent to the semiconductor chip mounting region and being spaced apart from each other; forming a first ball land on the base substrate and electrically connected to the first connection terminal; forming a second ball land spaced apart from the first connection terminal, the first ball land disposed between the second ball land and at least one of the first through third connection terminals; forming a third ball land spaced apart from the first and second connection terminals, the first and second ball lands disposed between the third ball land and at least one of the first through third connection terminals; forming an insulating layer that at least partially exposes at least one ball land out of the ball lands, the insulating layer covering at least another ball land adjacent to the connection terminals out of the ball lands; and forming a conductive wire that connects the at least one ball land exposed by the insulting layer to one of the connection terminals.