Patent ID: 6620706
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A wafer scale condensed memory matrix for use in one of a thin small outline plastic package and a memory card comprising:a substrate comprised of one of silicone, ceramic, and printed circuit board; a wafer including a plurality of semiconductor dice thereon, each semiconductor die of said plurality of semiconductor dice having an array of die connection structures carried on a surface of said wafer, a layer of at least one dielectric material, filling interstices between said array of die connection structures, a surface of said wafer having die connection structures juxtaposed against and in conductive relationship with a corresponding array of circuit connection structures carried by said substrate, said array of circuit connection structures comprising first attachment bumps, said at least one dielectric material layer filling interstices between said circuit connection structures, said plurality of semiconductor dice comprising a plurality of memory dice; a thermally conductive layer on a portion of said surface of said wafer opposite said surface carrying said die connection structures; and a heat dissipation device connected to a portion of said thermally conductive layer.