Patent ID: 6882565
Filing Date: 2005-04-19
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell array in which memory cells each of which stores information by using a magneto-resistive effect are arranged in a matrix; a constant current circuit which is connected to a first potential supply source and used to write data in each memory cell in the memory cell array; and a current peak suppressing circuit configured to suppress a current peak that is generated at a write start timing due to charges which flow out from a parasitic capacitance connected to an output terminal of the constant current circuit or charges which flow into the parasitic capacitance, the current peak suppressing circuit having switch circuits to selectively supply an output from the constant current circuit to a specific write line, and a circuit portion which connects one of two terminals of each of the switch circuits to a second potential supply source having a potential different from that of the first potential supply source before the timing of the start of the write operation and short-circuits the two terminals of each of the switch circuits immediately after the start of the write operation.