Patent ID: 6763422
Filing Date: 2004-07-13
Classification: G06F

Abstract:
A cache memory for temporarily storing a part of data stored in a main memory as pieces of cache data, for access by an arithmetic unit, and employing an N-way set associative method in which said cache data is managed for each of said ways, said cache memory comprising:a plurality of data memory macro units having a storing position for each of said pieces of cache data, each being designated by a way number used to identify one of said N ways, an index number determined by part of a corresponding address data at which said piece of data is stored in said main memory, and a word number determined by another part of said corresponding address in said main memory, said plurality of data memory macro units each being able to be accessed simultaneously; and a plurality of multiplexers, each connected to a data input terminal of one of said data memory macro units to allow simultaneous writing of N pieces of said cache data to said plurality of data memory macro units; wherein pieces of said cache data designated by said same index number and different word numbers are stored together in each of said data memory macro units, and wherein pieces of said cache data designated by said same index number and different way numbers, are stored in different data memory macro units.