Patent ID: 6420267
Filing Date: 2002-07-16
Classification: H01L

Abstract:
A process for forming an integrated barrier/plug memory cell structure comprising:etching a area in a semiconductor substrate; depositing a conductive barrier/plug material within said etched area, said conductive plug material being selected from the group consisting of titanium nitride, tungsten nitride, titanium aluminum nitride, tantalum silicon nitride, or a combination thereof; planarizing said deposited conductive plug material; depositing a first conductor selected from the group consisting of platinum, the noble metals, alloys of noble metals, alloys of noble metals with noble or nonnoble metals, metals whose oxides are conducting, electrically conducting oxides, electrically conductive-oxidation-resistant nitrides and electrically conductive materials whose oxides are insulating; patterning and etching said deposited first conductor; depositing a high dielectric constant material over said patterned and etched first conductor; and depositing a second conductor on said deposited high dielectric constant material.