Patent ID: 7533275
Filing Date: 2009-05-12
Classification: G06F

Abstract:
1. A data processing apparatus comprising: an operation processing unit connected to a data bus and configured to perform a read cycle by outputting a read control signal to a memory to read a read data word output by said memory to said data bus, and a write cycle by outputting a write control signal to said memory and a write data word to said data bus to write said write data word in the memory; and a pseudo-data generating circuit connected to said data bus, said read control signal output from said operation processing unit, and said write control signal output from said operation processing unit, said pseudo-data generating circuit configured to generate pseudo-data and output the generated pseudo-data to said data bus according to an output timing based on said read control signal and said write control signal output from said operation processing unit, the output timing controlled to cause the pseudo-data generating circuit to output the generated pseudo-data between a read cycle and an immediately following write cycle, between a write cycle and an immediately following read cycle, between a read cycle and an immediately following read cycle, or between a write cycle and an immediately following write cycle, and the output timing controlled to prevent the pseudo-data generating circuit from outputting the generated pseudo-data during the read cycle and the immediately following write cycle, during the write cycle and the immediately following read cycle, during the read cycle and the immediately following read cycle, or during the write cycle and the immediately following write cycle.