Patent ID: 7406046
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. A scheduler for a memory system for buffer storage of data processed by at least one data processing unit, comprising: a write unit for writing data objects to the memory system, said write unit: a counter connected to said write unit and incremented by said write unit when the data object string is written to the memory system to correspond to an amount of data contained in the data packet and the filling data in the tilling objects; a time out signaling unit connected to said counter, said time out signaling unit: said write unit having a control path and a data path; said data path having a counting device incremented linearly in accordance with a linear nominal data arrival curve; and said data path having an effective data address generator calculating a time wheel distribution as a function of a calculated cumulative amount of data and of a count produced by the counting device, as follows: where R(t) is an amount of data in a received data packet, and α is the linear nominal data arrival curve.