Patent ID: 6081910
Filing Date: 2000-06-27
Classification: G06F,G11C

Abstract:
A circuit for allowing a two-pass fuse blow to an integrated circuit of a memory type comprising:i.) memory means including:a standard array having a plurality of word lines,a redundant array provided with redundant word lines,a decoder means coupled to said standard array, andcomparator means coupled to said redundant array and to said decoder means;the circuit further comprising:ii) ABIST means driving said memory means for providing said memory means with self-test patterns;iii) data compression means responsive to said ABIST means and to said memory means for detecting and address of at least one of said word lines and said redundant word lines in said memory means that is defective; andiv) fail register means responsive to said ABIST means and to said data compression means for storing an address of a defective word line and for generating a number indicative of the number of defective word lines that exceeds the number of redundant word lines of said redundant array,v) said comparator means for comparing the addresses of said word lines and redundant word lines with the detected addresses of said defective word lines and for selecting a predetermined word line of said redundant array;vi) OR-gate means having inputs for receiving signals generated by said comparator means and having an output connected to a latching means of said circuit; andvii) AND-gate means having a first input connected to said latching means and a second input responsive to signals generated by said data compression means, for generating a signal to said fail register means which is indicative of a defective line address of said redundant word lines.