Patent ID: 6795883
Filing Date: 2004-09-21
Classification: G06F

Abstract:
A method of dividing a configuration space, applied to a computer system comprising a microprocessor, a north bridge control chip, a first bus, a south bridge control chip, and a second bus, wherein the first bus is coupled to the north bridge control chip and south bridge control chip and the south bridge chip is further coupled to the second bus, the method comprising:providing a first actual configuration space in the north bridge control chip to store a plurality of configuration values relating to the a plurality of devices connected to the north bridge control chip; providing a second actual configuration storage space in the south bridge control chip to store a plurality of configuration values relating to the second bus; and transmitting a write operation cycle to both the north bridge control chip and the south bridge control chip when the microprocessor is performing the write operation cycle related to the configuration spaces, wherein: the first actual configuration space is written to only when the write operation cycle is addressed to the first actual configuration space; and the second actual configuration space is written to only when the write operation cycle is addressed to the second configuration storage space; when the microprocessor is performing a read operation cycle related to the configuration spaces, selecting data read from the first actual configuration space only when the read operation cycle is addressed at the first actual configuration space; and selecting data read from the second actual configuration space only when the read operation cycle is addressed at the second actual configuration storage space.