Patent ID: 6770950
Filing Date: 2004-08-03
Classification: H01L,Y10S

Abstract:
A non-volatile semiconductor memory cell structure, comprising:a substrate having a shallow first-type well layer, a second-type well layer and a deep first-type well layer, wherein the deep first-type well layer is at a greater depth than the shallow first-type well layer and the second-type well layer is between the shallow first-type well layer and the deep first-type well layer; a plurality of stack gates above the shallow first-type well layer of the substrate; and a plurality of source terminals and drain terminals between the stack gates, wherein depth of the source terminal is long enough to pass through the shallow first-type well layer and connect with the second-type well layer, and both the source terminals and the drain terminals are second-type-doped regions; wherein each source terminal further includes: a lightly doped region close to the substrate surface; and a heavily doped region underneath the lightly doped region but in connection with the lightly doped region such that the heavily doped region passes through the shallow first-type well layer in connection with the second-type well layer; wherein both the lightly doped region and the heavily doped region are second-type-doped regions with a dopant concentration greater in the heavily doped region than the lightly doped region.