Patent ID: 6653666
Filing Date: 2003-11-25
Classification: H01L,Y10S

Abstract:
A vertical J-FET semiconductor configuration, comprising:a semiconductor region of a first conductivity type defining a first semiconductor region having a first surface; a first contact with a highly doped contact layer serving as a source, said first contact disposed on said first surface; two second contacts serving as a gate, said first contact disposed between said two second contacts; three second semiconductor regions being of a second conductivity type that is opposite said first conductivity type, a first one of said second semiconductor regions being short-circuited with said first contact and having a width smaller than that of said highly doped contact layer, a second one of said second semiconductor regions connected to one of said two second contacts, a third one of said second semiconductor regions connected to another one of said two second contacts; said second one of said second semiconductor regions and said third one of said second semiconductor regions extending in said first semiconductor region below said first one of said second semiconductor regions; said three second semiconductor regions at least partially overlapping in a projection onto a horizontal plane; at least one channel region formed in said first semiconductor region and between said three second semiconductor regions; and a current path leading from said first contact and running only though said first semiconductor region at least until passing said second one of said second semiconductor regions and said third one of said second semiconductor regions.