Patent ID: 6077738
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A method of forming a planarized top surface topography for an insulator layer overlying DRAM devices, comprised with crown shaped capacitor structures, and overlying peripheral, non-DRAM devices, on respective regions of a semiconductor substrate, comprising the steps of:providing a first set of transfer gate transistors, for said DRAM devices, in a first portion of said semiconductor substrate, and providing a second set of transfer gate transistors, for said peripheral, non-DRAM devices, in a second portion of said semiconductor substrate, with storage node contact plugs, located in storage node contact holes, formed in a first insulator layer, contacting source/drain regions, of said first set of transfer gate transistors;forming a thin insulator mask, and a second insulator layer, overlying said first insulator layer, in said peripheral, non-DRAM device region, while only said second insulator layer, overlays said first insulator layer, in said DRAM device region;depositing a third insulator layer, and forming capacitor openings in said third insulator layer, and in said second insulator layer, exposing the top surface of said storage node contact plugs, in said DRAM device region;forming crown shaped, storage node structures, in said capacitor openings;removing said third insulator layer, and said second insulator layer, in said DRAM device region, exposing vertical sides of said crown shaped storage node structures, while said thin insulator mask protects underlying, said second insulator layer, in said peripheral, non-DRAM device region;forming said crown shaped capacitor structure, via formation of a capacitor dielectric layer, on said crown shaped, storage node structures, followed by the formation of upper plate structures, with said thin insulator mask removed in said peripheral, non-DRAM device region, in situ after formation of said upper plate structure; andforming a planarized fourth insulator layer, overlying said crown shaped capacitor structures, and overlying said second insulator layer, in said peripheral, non-DRAM device region.