Patent ID: 7266631
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A data processing system, comprising: a system bus; a host bridge connected to the system bus; at least one input/output unit connected to the host bridge; at least one of a traffic class mechanism in conjunction with virtual channel resources and a relaxed ordering mechanism for differentiating input/output unit data flow operations; and functionality in the host bridge for controlling the input/output unit data flow operations using the at least one of the traffic class mechanism in conjunction with virtual channel resources and the relaxed ordering mechanism, wherein the host bridge includes a table having a plurality of entries, each of the plurality of entries associating an input/output unit with at least one of a traffic class identifier and a relaxed ordering bit value, and wherein the host bridge includes functionality for controlling input/output unit data flow operations using at least one of the traffic class identifier and the table and the relaxed ordering bit value and the table, wherein the input/output unit data flow operations comprise MMIO operations, and wherein a portion of bits of an MMIO Load/Store address are used as an index in a lookup mechanism using the table in the host bridge to at least one of associate the traffic class identifier with an input/output unit and specify a relaxed ordering bit value.