Patent ID: 6014682
Filing Date: 2000-01-11
Classification: H03H,H04L

Abstract:
In a digital filter, the improvement comprising:a W bit wide register having a register input, a register output and a sample clock input;a W bit wide first-adder having first and second first-adder inputs, a first-adder output and a carry output;a coefficient generator having an address input and a plurality of multi-bit filter coefficient outputs;the first first-adder input being coupled to receive a frequency word;the first-adder output being coupled to the register input;the register output being coupled to the address input of the coefficient generator and to the second first-adder input;the register clock input being coupled to receive a sample clock signal;the carry output being coupled to provide a shift control signal;the address input of the coefficient generator is P bits wide, wherein P is less than W, and wherein only the P most significant bits of the register output are coupled to the address input of the coefficient generator, the coefficient generator storing M times 2.sup.P coefficients, M coefficients at each coefficient generator address; anda plurality M of multiplier-accumulator circuits, each multiplier-accumulator circuit being coupled to receive a respective one of each M filter coefficient outputs of the coefficient generator and a signal sample at the sample clock rate, multiply the same together and accumulate the results in an accumulator, the multiplier-accumulator circuits being coupled in series and responsive to a shift control input to shift the contents of each accumulator in the series of multiplier-accumulator circuits to the accumulator of the next multiplier-accumulator circuit, the contents of the accumulator of the last multiplier-accumulator circuit forming the multiplier-accumulator circuits' output.