Patent ID: 7158638
Filing Date: 2007-01-02
Classification: H04L

Abstract:
1. An encryption circuit that generates from a cipher key a plurality of round keys having a number of bits corresponding to a predetermined processing block length and executing, for each processing block length, input data and round key encryption/decryption processing, by means of a round function unit comprising an XOR operation unit that XORs the input data and one of the round keys and a round processing unit that iterates round processing that includes Byte Sub transformation, Mix Column transformation and Round Key Addition, which are executed at execution block length that is smaller than said predetermined processing block length, the round processing further including Shift Row transformation which is performed on data having the predetermined processing block length, wherein: said round processing unit comprises: a first selector that segments input data having the predetermined processing block length into data segments having the execution block length; a first Round Key Addition circuit that adds said round key value to input data for each said execution block length; an intermediate register/Shift Row transformation circuit that temporarily stores the output of said first Round Key Addition circuit and executes Shift Row transformation using said predetermined processing block length; a Byte Sub transformation circuit wherein said intermediate register/Shift Row transformation circuit value is inputted for each said execution block length and Byte Sub transformation is executed; a second Round Key Addition circuit wherein said intermediate register/Shift Row transformation circuit value is inputted for each said execution block length and said round key value is added for each said execution block length; a Mix Column transformation circuit executing Mix Column transformation on the output of said second Round Key Addition circuit; and a second selector that outputs to said first Round Key Addition circuit one output from among the outputs of said first selector, intermediate register/Shift Row transformation circuit, Byte Sub transformation circuit, or Mix Column transformation circuit, the second selector enabling the first Round Key Addition circuit, the Byte Sub transformation circuit and the Mix Column transformation circuit to perform continuously at the execution block length without an extra processing circuit.