Patent ID: 6548400
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method for fabricating circuit interconnects comprising vias and trenches between metal lines, at least one metal line overlaid by a stack of insulating layers alternating between etch stop and dielectric layers, comprising the steps of:depositing a layer of photoresist on the uppermost insulating layer of said stack; patterning said photoresist layer to create a plurality of separate masks, each mask having outer dimensions defining said trenches, and at least one hole in each trench defining said via; adjacent patterns spaced apart by a distance substantially greater than the diameter of said via, and aligned so that the distance between said masks is substantially greater than the diameter of a single via; and exposing the masked surface to a plasma etchant; thereby providing differential plasma etch rates for said insulating layers, whereby the etch rate is approximately 20% greater between said masks than inside said via hole.