Patent ID: 6607955
Filing Date: 2003-08-19
Classification: H01L

Abstract:
A method of forming self-aligned contacts in a semiconductor device, the method comprising:forming a gate oxide layer, a gate electrode layer, a first gate mask layer, and a second gate mask layer on a semiconductor substrate; etching the second gate mask layer, the first gate mask layer, and the gate electrode layer to form a plurality of gate electrode configurations which are spaced apart; forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations; forming an interlayer insulating layer on an entire surface of the semiconductor substrate; using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate, removing the self-aligned contact mask; filling the exposed semiconductor substrate with a conductive material; and planarizing the conductive material and the second gate mask layer and stopping at the first gate mask, wherein the first gate mask layer, the second gate mask layer, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer, and wherein the second gate mask layer has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask layer.