Patent ID: 7560327
Filing Date: 2009-07-14
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming a gate dielectric layer over a substrate; forming a gate conductive layer over the gate dielectric layer, the gate conductive layer having a first portion and a second portion; forming a first amorphous carbon layer over the gate conductive layer, wherein the first amorphous layer comprises a first portion and a second portion; forming a first patterned photosensitive layer over the first amorphous carbon layer, the first patterned photosensitive layer exposing the first portion of the first amorphous carbon layer, the second portion of the first amorphous carbon layer being covered by the first patterned photosensitive layer; etching the first amorphous carbon layer using the first patterned photosensitive layer as an etch mask to form a patterned first amorphous carbon layer, wherein the patterned amorphous carbon layer exposes the first portion of the gate conductive layer and covers the second portion of the conductive layer; stripping the first patterned photosensitive layer; performing a first ion implantation process using at least the patterned first amorphous carbon layer as an ion implantation barrier to implant an impurity of a first type onto the first portion of the gate conductive layer; removing the first patterned amorphous carbon layer; forming a second amorphous carbon layer over the gate conductive layer, wherein the second amorphous carbon layer comprises a first portion and a second portion; forming a second patterned photosensitive layer over the second amorphous carbon layer, the second patterned photosensitive layer exposing the second portion of the second amorphous carbon layer, the first portion of the second amorphous carbon layer being covered by the second patterned photosensitive layer; etching the second amorphous carbon layer using the second patterned photosensitive layer as an etch mask to form a second patterned amorphous carbon layer, wherein the second patterned amorphous carbon layer exposes the second portion of the gate conductive layer and covers the first portion of the gate conductive layer; stripping the second patterned photosensitive layer; performing a second ion implantation process using at least the second patterned amorphous carbon layer to implant an impurity of a second type onto the second portion of the gate conductive layer; performing a second ion implantation process using at least the patterned amorphous carbon layer to implant an impurity of a second type onto the second portion of the gate conductive layer; removing the second patterned amorphous carbon layer; and patterning the gate conductive layer to form a gate structure.