Patent ID: 6545950
Filing Date: 2003-04-08
Classification: G04G

Abstract:
A method of calibrating an electronic clock having an output signal, comprising the steps of:providing a calibration reference signal; providing a base reference signal having an actual frequency and an ideal frequency associated therewith, the electronic clock being responsive to the base reference signal; setting an ideal number of cycles of the calibration reference signal in an ideal calibration interval, the ideal calibration interval being based on a set number of cycles of the base reference signal at its ideal frequency; determining an actual number of cycles of the calibration reference signal in an actual calibration interval, the actual calibration interval being based on the set number of cycles of the base reference signal at its actual frequency; determining a difference between the actual number of cycles of the calibration reference signal and the ideal number of cycles of the calibration reference signal; and adjusting a frequency of the electronic clock output signal based on the difference between the actual number of cycles of the calibration reference signal and the ideal number of cycles of the calibration reference signal.