Patent ID: 6387765
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method for forming an extended metal gate and a self-aligned contact comprising the steps of:a. providing a semiconductor structure (11); said semiconductor structure having a gate dielectric layer thereon; said gate dielectric layer having a gate silicon layer thereon; said gate silicon layer having a doped silicon oxide layer thereon; said doped silicon oxide layer having a disposable gate layer thereon; b. patterning said disposable gate layer; said doped silicon oxide layer, said gate silicon layer, said gate dielectric layer and semiconductor structure to form trenches for shallow trench isolation; c. forming shallow trench isolation (STI) structures by depositing and planarizing a first dielectric layer in the trenches; d. patterning said disposable gate layer, said doped silicon oxide layer, said gate silicon layer and said gate dielectric layer to form gate structure having sidewalls; e. forming dielectric spacers on said sidewalls of said gate structure; f. forming a gapfill layer over said semiconductor structure and said gate structure and planarizing said gapfill layer stopping on said disposable gate layer; g. forming a silicon nitride layer on said disposable gate layer and said gapfill layer; h. forming a second dielectric layer over said silicon nitride layer; i. patterning said second dielectric layer to form a trench over said gate structure; said trench having a width greater than the width of said gate structure; j. removing said silicon nitride layer in a bottom of said trench; k. removing said disposable gate layer; whereby said doped silicon oxide layer is exposed; l. removing said doped silicon oxide layer using an etch selective to undoped silicon oxide; whereby said gate silicon layer is exposed; m. forming a barrier layer over said gate silicon layer; and n. forming a metal gate layer on said barrier layer.