Patent ID: 8471306
Filing Date: 2013-06-25
Classification: G06F,H01L

Abstract:
1. A design structure, comprising design data embodied in a non-transitory computer readable medium, said design data comprising elements that when processed in a computer-aided design system generate a machine executable representation of a double sided integrated circuit chip, wherein said double sided integrated circuit chip comprises: one or more first devices of a first substrate, said first substrate comprising a first oxide layer, a first silicon layer on said first oxide layer, a first dielectric isolation in said first silicon layer, and a first lowermost dielectric layer on both said first silicon layer and said first dielectric isolation; one or more second devices of a second substrate, said second substrate comprising a second oxide layer, a second silicon layer on said second oxide layer, a second dielectric isolation in said second silicon layer, and a second lowermost dielectric layer on both said second silicon layer and said second dielectric isolation; a top surface of said first oxide layer abutting and directly bonded to a top surface of said second oxide layer; electrically conductive first contacts in physical and electrical contact with said first devices, said first contacts extending from a top surface of said first lowermost dielectric layer through said first lowermost dielectric layer to said first devices; electrically conductive second contacts in physical and electrical contact with said first devices, said second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said second dielectric isolation, through said first oxide layer, and through said second oxide layer to those portions of said first devices formed in said first silicon layer; one or more first wiring levels on said first lowermost dielectric layer, each wiring level of said one or more first wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of said first lowermost wiring level of said first wiring levels in physical and electrical contact with said first contacts; and one or more second wiring levels on said second lowermost dielectric layer, each wiring level of said one or more second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said one or more second wiring levels in physical and electrical contact with said second contacts.