Patent ID: 7539054
Filing Date: 2009-05-26
Classification: G11C

Abstract:
1. A method for programming a first and second tri-gate structure in a non-volatile SRAM cell from a bit line pair, said non-volatile SRAM having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said volatile portion having an SRAM cell having a word line, a node supplying power to said SRAM cell and a bit line pair with a first bit line and a second bit line, said method comprising: coupling a drain of a first recall transistor in said first tri-gate structure to said first bit line of said bit line pair; coupling a drain of a second recall transistor in said second tri-gate to said second bit line of said bit line pair; erasing a first SONOS transistor in said first tri-gate structure and a second SONOS transistor in said second tri-gate structure, said first and second SONOS transistors associated with said non-volatile portion of said SRAM cell; isolating said volatile portion from said non-volatile portion by turning off a first store transistor in said first tri-gate structure and turning off a second store transistor in said second tri-gate structure; applying a programming pulse and a programming voltage to said first and second SONOS transistors in said first and second tri-gate structures so as to program at least one of said first and second tri-gate structures in said non-volatile portion; maintaining said first bit line at a voltage corresponding to a high condition for said first bit line and maintaining said second bit line at approximately ground; and applying a voltage to a first recall transistor in said first trigate structure and applying voltage to a second recall transistor in said second tri-gate structure sufficient to turn on said first and second recall transistors, wherein said first recall transistor coupled to said first bit line is cutoff such that said first SONOS transistor coupled to said first recall transistor remain erased and wherein said second recall transistor coupled to said second bit line is on and said second SONOS transistor coupled to said second recall transistor is programmed.