Patent ID: 7548119
Filing Date: 2009-06-16
Classification: G06F

Abstract:
1. A digitally controlled oscillator (DCO) for generating an output clock, comprising a frequency control unit for generating a frequency control word; a DCO accumulator for accumulating said frequency control word during each cycle of a master clock and generating an enable signal each time said DCO accumulator overflows, said DCO accumulator also outputting a remainder value with said enable signal; an overflow counter for counting each occurrence of said enable signal and responsive to a clock frequency signal to generate an output signal at a frequency determined by said clock frequency signal; a jitter shaping circuit responsive to said frequency control word, said remainder value, and said output signal of said overflow counter, for shifting low frequency digital jitter in said output signal into higher frequency jitter, said jitter shaping circuit comprising: an error resolution circuit responsive to said remainder value and said frequency control word to generate an error value representing a timing error in said output signal; an error accumulator for accumulating said error value; and a clock advancement circuit for advancing the output signal from the overflow counter by a one master clock cycle when the accumulated error value reaches one master clock cycle; and wherein said error resolution circuit sets said error value to the difference between said remainder value and said frequency control word during advancement of said output signal and otherwise sets said error value to said remainder value.