Patent ID: 7742553
Filing Date: 2010-06-22
Classification: H03C,H03L

Abstract:
1. A transceiver for processing high data rate serial data, comprising: clock data recovery (CDR) circuitry for receiving the high data rate serial data and recovering a clock from the high data rate serial data, the CDR circuitry further including a phase locked loop (PLL) that initially operates at an initial voltage controlled oscillator (VCO) clock frequency and subsequently operates at a frequency based upon a clock rate of the high data rate serial data; a VCO initial frequency calibration circuit for setting the initial VCO clock frequency for the PLL of the CDR circuitry, wherein the VCO initial frequency calibration circuit sets the initial VCO clock frequency within a programmable phase locked loop lock range of the clock rate of the high data rate serial data based upon a frequency of a reference clock, and wherein the VCO initial frequency calibration circuit further comprises: a frequency detection block for an indication of a difference between the reference clock and a divided VCO clock; a frequency calibration block that produces a digital output signal having a magnitude based upon the indication of the difference between the reference clock and the divided VCO clock; a digital-to-analog controller for converting the digital output signal to an n-bit VCO adjust signal, wherein the n-bit VCO adjust signal comprises an analog voltage coupled to control the initial VCO clock frequency; and a circuit adapted to open the PLL and close the VCO initial frequency calibration circuit to calibrate the initial VCO clock frequency, the circuit being further adapted to close the PLL and open the VCO initial frequency calibration circuit while the n-bit VCO adjust signal maintains the calibrated initial VCO clock frequency to enable the PLL to further adjust the VCO clock frequency from the calibrated initial VCO clock frequency, where the n-bit VCO adjust signal is set to an initial value which may be adjusted while calibrating the initial VCO clock frequency by the VCO initial frequency calibration circuit to enable the CDR circuitry to generate the initial VCO clock frequency within the programmable phase locked loop lock range of the clock rate of the high data rate serial data before closing the PLL and opening the VCO initial frequency calibration circuit, and wherein a phase detection module of the PLL is coupled to receive a phase of the high data rate serial data and a phase of a feedback signal, generated at an output of the PLL to enable the VCO clock frequency to correspond to the frequency of the high data rate serial data after calibrating the initial VCO clock frequency.