Patent ID: 6480037
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A sense amplifier circuit of a semiconductor memory device comprising:first and second output nodes for outputting a detected and amplified signal; a latch having first and second inverters cross-coupled between the first and second output nodes; first and second input transistors having drains connected to drains of NMOS transistors in the first and second inverters respectively, for inputting, at respective gates, a bit line and a complement bit line; a driving transistor, connected between a common pull-down node of the first and second input transistors and ground for pulling down an electric potential of the pull-down node to the level of ground in response to activation of a control signal; and voltage control transistors, connected between the drain and source of the NMOS transistors in the first and second inverters, respectively, for maintaining a voltage at the drain and source of the NMOS transistors in the first and second inverters at a substantially identical level in response to the control signal shifting from its pre-charge level to its activation level.