Patent ID: 7876640
Filing Date: 2011-01-25
Classification: G11C,H03L

Abstract:
1. A clock synchronization circuit, comprising: a voltage controlled delay line (VCDL) configured to generate an output clock signal in response to an input clock signal, the output clock signal having a delay relative to the input clock signal according to a control voltage; a phase detector coupled to the VCDL and configured to receive a reference clock signal and the output clock signal from the VCDL, the phase detector configured to generate output signals indicative of a phase difference between the reference clock signal and the output clock signal from the VCDL; a control voltage generator circuit coupled to the phase detector and the VCDL, the control voltage generator circuit configured to generate the control voltage to adjust the delay of the VCDL in accordance with the phase detector output signals; and a control voltage tracking circuit coupled to the VCDL and the control voltage generator circuit, the control voltage tracking circuit configured to provide the VCDL with a initial control voltage during a first mode and configured to enable the phase detector following the first mode, the control voltage tracking circuit further configured to record the control voltage from the control voltage generator and provide a recovery control voltage for the VCDL based on the recorded control voltage during a second mode.