Patent ID: 8959001
Filing Date: 2015-02-17
Classification: G01R

Abstract:
1. A test pattern generation method for a semiconductor integrated circuit subjected to scan design, the method comprising: sequentially selecting, by using a computer, a test pattern from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit; estimating power consumption in each of regions obtained by substantially equally dividing a layout region of the semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit; searching for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions; and generating a first new test pattern sequence constituted by a plurality of test patterns including no don't care bit by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.