Patent ID: 8588024
Filing Date: 2013-11-19
Classification: G11C

Abstract:
1. A memory comprising: an array of memory cells arranged in rows of memory cells and columns of memory cells; word-lines coupling to corresponding ones of the rows of memory cells; write-lines coupling to corresponding columns of memory cells; a row address decoder, coupled to the word-lines and a row address input, adapted to activate at least one of the word-lines in response to a row address; write drivers coupled to corresponding ones of the write-lines; and a column address decoder, coupled to the write drivers and a column address input, having: wherein memory cells coupled to an activated word-line are enabled memory cells; wherein the column address decoder is adapted to enable at least one of the write drivers, in accordance with a first column address on the column address input, to write desired data into enabled ones of the plurality of memory cells, and is further adapted to enable a plurality of the write drivers, selected in accordance with a second column address on the column address input and in response to the reset signal, to write a preselected data value into enabled ones of the plurality of memory cells; wherein first column address has a first bit-width and the second column address has a second bit width, the first bit width being greater than the second bit width; and wherein the pre-decoder partially decodes a column address on the column address input to form a plurality of intermediate outputs, each intermediate output corresponding to a bit of the column address input; the reset circuit forces more than one of the plurality of the intermediate outputs to an active state in response to the reset signal, and the decoder enables those write drivers corresponding to a logical combination of the enabled ones of the intermediate outputs.