Patent ID: 6586970
Filing Date: 2003-07-01
Classification: G11C

Abstract:
A two stage decoder circuit, comprising:a first stage circuit suitable for receiving a first portion of address bits from an address bus to generate a control signal, the first stage circuit including a pseudo AND gate; a second stage circuit suitable for receiving a second portion of address bits from the address bus, the second stage circuit including a plurality of subcircuits, each of the plurality of subcircuits being suitable for receiving an address bit from the second portion of address bits from the address bus, each of the plurality of subcircuits generating a word line signal and having a discharging current; and a discharging transistor controlled by the control signal of the first stage circuit through a single critical path, the discharging transistor providing a common discharge path for the discharging currents of the plurality of subcircuits of the second stage circuit, wherein the pseudo AND gate comprises first and second PMOS transistors arranged in parallel, drains of the first and second PMOS transistors being connected to a node and sources of the first and second PMOS transistors being connected to a positive power supply; first and second NMOS transistors, a source of the first NMOS transistor being connected to a drain of the second NMOS transistor, a drain of the first NMOS transistor being connected to the node, and a source of the second NMOS transistor being connected to either a negative power supply or ground; and an inverter having an output terminal connected to a gate of one of the first and second PMOS transistors and an input terminal connected to the node.