Patent ID: 8575669
Filing Date: 2013-11-05
Classification: B82Y,H01L

Abstract:
1. A semiconductor memory device, comprising: a first gate pattern formed on an active region; a second gate pattern provided adjacent to a first side of the first gate pattern, wherein the second gate pattern is formed on a field isolation layer defining the active region; a third gate pattern provided adjacent to a second side of the first gate pattern, the second side opposing the first side, wherein the third gate pattern is formed on the active region; a capacitor directly coupled to the active region between the first and second gate patterns; a plate layer coupled to an upper portion of the capacitor, the plate layer extending in a first direction; and a bit line coupled to the active region between the first and the third gate patterns, the bit line extending in the first direction, wherein the capacitor comprises: a lower electrode including a seed layer and a plurality of conductive components extending from the seed layer; a dielectric layer formed over the seed layer and the conductive components; and an upper electrode formed over the dielectric layer, wherein the lower electrode, the dielectric layer, and the upper electrode are provided in a trench defined by the first and the second gate patterns, and wherein the seed layer is directly formed on a whole surface of a sidewall as well as a bottom surface of the trench defined by the first and the second gate patterns, and wherein the plurality of conductive components are directly formed on a bottom and a sidewall surface of the seed layer.