Patent ID: 8332201
Filing Date: 2012-12-11
Classification: G06F

Abstract:
1. A circuit verification method for a deeply embedded portion of a logic pipeline circuit, the method comprising: accessing a first hardware description language (HDL) code representative of the logic pipeline circuit, wherein one or more inputs of the deeply embedded portion are directly inaccessible to the first HDL code; executing the first HDL code to simulate operation of the logic pipeline circuit; for the deeply embedded portion of the logic pipeline circuit, accessing a second HDL code representative of the embedded portion, the second HDL code having direct access to the one or more inputs of the deeply embedded portion; forcing, with a processing device, the one or more inputs of the deeply embedded portion to one or more known values using the second HDL code; receiving, by the processing device, an output signal from the deeply embedded portion of the logic pipeline circuit, the output signal being based on the forced inputs; comparing, with the processing device, the received output signal with an expected value; and verifying, based on the comparison of the received output signal and the expected value, operation of the deeply embedded portion, wherein the verification of the operation of the deeply embedded portion is independent of an operation of another portion of the logic circuit.