Patent ID: 6314477
Filing Date: 2001-11-06
Classification: H04L

Abstract:
An interface controller that operates together with a communications network host to implement a number of network communications protocol layers, the interface controller coupled to a receiver that is, in turn, coupled to a communications network transport medium through which the receiver receives a data sequence, the data sequence composed of a number of data frames that contain data, the interface controller comprising:a direct memory access engine for transferring data from a received data frame to a host memory buffer;a transaction status block allocated within host memory and initialized by the host to represent a data sequence, the transaction status block containing information fields and referencing a number of arbitrarily-sized and byte-aligned host memory buffers; anda logic component that assembles data, received in data frames, in host memory, sequentially ordering the data according to an order specified by the data sequence, processing each data frame received by the receiver, both in the case that the data frame is received in-order with respect to the data sequence and in the case that the data frame is received out-of-order with respect to the data sequence, by directing the direct memory access engine to transfer one or more data blocks from the received data frame into one or more locations within one or more host memory buffers, the number of data block transfers depending on the relative sizes of the data to be transferred and the available space remaining in the host memory buffer to which the data is transferred, the logic component determining a host memory buffer and location within the host memory buffer into which to transfer a data block by using the information fields and host memory buffer references contained in the transaction status block.