Patent ID: 9164842
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. An integrated circuit for performing data processing, said integrated circuit comprising: a latch configured to receive and to store a signal value; an error detector configured to detect errors in operation of said integrated circuit by detecting a late arriving transition in said signal value received by said latch; error-repair circuitry configured to repair errors in operation of said integrated circuit a plurality of processing stages, a processing stage output signal from at least one processing stage being supplied as a processing stage input signal to a following processing stage, wherein said at least one processing stage comprises: wherein said error detector comprises a comparator configured to compare said non-delayed value and said delayed value to detect a change in said processing logic output signal following said non-delayed capture time indicative of said processing logic not having finished said processing operation at said non-delayed capture time; and said error-repair logic is configured, when said comparator detects said change, to perform an error-repair operation suppressing use of said non-delayed value by said following processing stage.