Patent ID: 9202879
Filing Date: 2015-12-01
Classification: E21B,H01L

Abstract:
1. A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising: forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity; forming a gate dielectric over said top surface of said semiconductor substrate in said gate cavity; forming a work function material layer on said gate dielectric; forming a dielectric material portion on an horizontal portion of said work function material layer within said gate cavity; etching said work function material layer, wherein a remaining portion of said work function material layer becomes a work function material portion; and forming a conductive material portion over said dielectric material portion and said work function material portion, wherein a gate electrode of said field effect transistor comprises said conductive material portion and said work function material portion.