Patent ID: 6117717
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A process for fabricating an intermediate semiconductor device as part of a series of BiCMOS fabrication steps including the formation of a split polysilicon layer used to form a bipolar transistor structure, a PMOS transistor structure, and an NMOS transistor structure, the process comprising the steps of:a. forming an epitaxial layer of semiconductor material of a certain conductivity type on a semiconductor substrate;b. forming an insulative oxide layer on a surface of said epitaxial layer;c. depositing on a surface of said insulative oxide layer amorphous silicon material to form a protective silicon layer thereon;d. implanting through and under a first portion of said insulative oxide layer and said protective silicon layer a first dopant of a certain conductivity type as a precursor to forming the PMOS transistor structure;e. implanting through and under a second portion of said insulative oxide layer and said protective silicon layer a second dopant of a certain conductivity type as a precursor to forming the NMOS transistor structure;f. implanting through and under a third portion of said insulative oxide layer and said protective silicon layer a third dopant of a certain conductivity type as a precursor to forming the bipolar transistor structure;g. removing said third portion of said insulative oxide layer and said protective silicon layer associated with the bipolar transistor structure; andh. depositing on the surface of the PMOS and NMOS transistor structures and the surface of the bipolar transistor structure after said removing a layer of silicon material as a precursor to forming gates of the MOS transistor structures and an emitter of the bipolar transistor structure.