Patent ID: 6760744
Filing Date: 2004-07-06
Classification: G06F

Abstract:
A digital processing system P, for processing of digital data and signal structures, wherein the data and signal structures comprise repeated sequences and/or nested patterns, the digital processing system comprising:a regular tree with n+1 levels S0, S1, . . . Sn and of degree k, where n and k are numbers; a circuit Pn on the level Sn and that forms the root node of the tree, such that the nearest level Snâˆ’1 is provided nested in the circuit Pn; k circuits Pnâˆ’1 which form the child nodes of the root node, and an underlying level Snâˆ’q in the circuit Pn, where qâˆˆ{1,2 . . . nâˆ’1}; including kq circuits Pnâˆ’q provided nested in the kqâˆ’1 circuits Pnâˆ’q+1 on the overlying level Snâˆ’q+1, each circuit Pnâˆ’q+1 on this level including k circuits Pnâˆ’q, such that a defined zeroth level Snâˆ’q=S0 in the circuit Pn for q=n includes from knâˆ’1+1 to kn circuits P0 which constitute kernel processors in the processing system P and on this level S0 form leaf nodes in the tree, the kernel processor P0 being provided nested in a number of 1 to k in each of the knâˆ’1 circuits P1 on the level S1, such that each of the circuits P1, P2 . . . Pn on respective levels S1, S2 . . . Sn includes comprises a logic unit E which is connected with those circuits P0, P1 . . . Pnâˆ’1 on the respective nearest underlying level S0, S1 . . . Snâˆ’1 provided nested in the respective circuits P1, P2, . . . Pn and configures a network of the former circuits in the respective circuits P1, P2 . . . Pn, wherein each of the circuits P0, P1 . . . Pn has identical interfaces I.