Patent ID: 8536916
Filing Date: 2013-09-17
Classification: H03L

Abstract:
1. An all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising: a thermometer pulse coder including a plurality of frequency control word signal lines, where the thermometer pulse coder is configured to: a digitally controlled oscillator configured to receive a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control world signal lines and generate an output clock signal at a frequency determined using at least the frequency control word; a feedback divider configured to receive the output clock signal from the digitally controlled oscillator and generate a feedback signal; and a phase detector configured to receive a reference clock signal and a feedback signal from the feedback divider and generate a phase error signal, which is provided to a digital loop filter configured to generate a binary encoded frequency control word that is input to the thermometer pulse coder.