Patent ID: 7674704
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A method of manufacturing semiconductor device including an interconnect, comprising: forming on a semiconductor substrate an insulating layer in which a wide interconnect trench which is relatively wide and a narrow interconnect trench which is relatively narrow are formed; forming a first metal layer in said wide interconnect trench and in said narrow interconnect trench; forming by an electrolytic plating method a second metal layer including the same metal as that of said first metal layer, in a in said bottom of wide interconnect trench and in a relatively great thickness in said bottom of narrow interconnect trench; forming an alloy layer including the same metal as that of said second metal layer and containing an impurity by a sputtering method on said second metal layer in said wide interconnect trench and in said narrow interconnect trench; diffusing said impurity from said alloy layer into said metal layer, so as to form a metal layer having a relatively high impurity concentration in said wide interconnect trench, and a metal layer having a relatively low impurity concentration in said narrow interconnect trench; and removing said alloy layer and said metal layer formed in an external region of said respective interconnect trenches, so as to form a relatively wide interconnect in said wide interconnect trench and a relatively narrow interconnect in said narrow interconnect trench, so as to constitute a first interconnect.