Patent ID: 7580443
Filing Date: 2009-08-25
Classification: H03C,H04B

Abstract:
1. A clock generating circuit comprising: a PLL (Phase-Locked Loop) circuit and a modulator, wherein a frequency dividing ratio of a feedback-purpose frequency divider in said PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of said modulator to perform a frequency modulation whereby a spectrum is spread, wherein said modulator comprises a multiple modulation profile generating circuit, and moves a turning point of said modulation profile so as to disperse a degree of frequency, wherein said modulator further comprises: a ΔΣbit converting circuit; and a modulation factor switching circuit, wherein said ΔΣbit converting circuit performs a pulse width modulation by which a multiple modulation profile outputted by said multiple modulation profile generating circuit is converted into 1 bit, and wherein said modulation factor switching circuit switches a frequency spread width which is determined based upon both the frequency dividing ratio of said feedback-purpose frequency divider and a value which is added to said frequency dividing ratio in response to the output of said ΔΣbit converting circuit.