Patent ID: 6802050
Filing Date: 2004-10-05
Classification: G06F,H01L

Abstract:
A method, comprising:fetching a profile of a manufacturing process that is to be used to manufacture a circuit structure, said profile containing specific design rules of said manufacturing process; fetching a generic description of a layout for said circuit structure, said generic description describing said layout without reference to specific design rules of said manufacturing process; and, executing a layout method that uses said profile, said generic description and a characteristic description of each transistor in said circuit structure to generate, in a software environment, a layout for said circuit structure that is targeted for said manufacturing process, said layout method further comprising: placing a gate structure relative to a diffusion region, said gate structure having a pair of gate fingers that project beyond said diffusion region along a y axis, said gate structure having a landing area large enough to support one or more vias from a metal 1 layer, said gate structure part of a gate node for a transistor in said circuit structure; running a pair of source fingers at a metal 1 layer over said diffusion area and along said y axis, said pair of source fingers being outside said pair of gate fingers, said pair of source fingers being an extension of a metal 1 source wire running along an x axis, said metal 1 source wire running on an opposite side of said diffusion region than said landing area; and placing a metal 1 gate pad layer over said landing area.