Patent ID: 6412036
Filing Date: 2002-06-25
Classification: G06F

Abstract:
An apparatus for testing I/O interface in a computer system, said apparatus communicating with said computer system and a first I/O interface in said computer system via a signal medium, said apparatus comprising:a memory means; a clock generator for outputting a clock signal; an I/O interface, said I/O interface communicating with said first I/O interface in said computer system via said signal medium; and a controller, said controller being connected to said I/O interface and synchronizing with the clock signal, said controller, under control of the clock signal, writing data transmitted from said I/O interface into said memory means, said controller reading out the data stored in said memory means and then transmitting the data to said first I/O interface through said I/O interface when a predetermined condition becomes effective; wherein said controller includes: a start/end detection circuit, wherein the data received by said I/O interface is transmitted to said start/end detection circuit through a RX signal line, and said start/end detection circuit detects a start moment and an end moment of the data on said RX signal line and sends out a status signal; a function mapper, said function mapper transmitting the data of said controller to said first I/O interface through a TX signal line and said I/O interface; a control circuit, said control circuit, in response to said status signal, sending out a reset signal; a counter, said counter, in response to said reset signal, outputting an address signal to said memory means for writing data into said memory means or reading out data from said memory means.