Patent ID: 8896363
Filing Date: 2014-11-25
Classification: H03K

Abstract:
1. An analog switching circuit comprising: a first terminal, a second terminal and a control terminal, wherein the first terminal is configured to receive an input signal, the second terminal is configured to provide an output signal, and the control terminal is configured to receive a switching control signal; a first logic circuit having an input, a first output and a second output, wherein the input is electrically coupled to the control terminal configured to receive the switching control signal, the first output is configured to provide a first control signal and the second output is configured to provide a second control signal; an N-type metal oxide semiconductor field effect transistor (NMOS) having a source, a drain, a gate and a backgate, wherein the source is electrically coupled to the first terminal, the drain is electrically coupled to the second terminal, and the gate is configured to receive the first control signal; a P-type metal oxide semiconductor field effect transistor (PMOS) having a source, a drain, a gate and a backgate, wherein the source of the PMOS is electrically coupled to the first terminal, the drain of the PMOS is electrically coupled to the second terminal, and the gate is configured to receive the second control signal; a first control circuit, having a first input, a second input and an output, wherein the first input is electrically coupled to the first terminal, the second input is electrically coupled to the control terminal, and the output is electrically coupled to the backgate of the NMOS, and further wherein the first control circuit is configured to control the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit, having a first input, a second input and an output, wherein the first input of the second control circuit is electrically coupled to the first terminal, the second input of the second control circuit is electrically coupled to the control terminal, and the output of the second control circuit is electrically coupled to the backgate of the PMOS, and further wherein the second control circuit is configured to control the backgate voltage of the PMOS based on the input signal and the switching control signal; wherein the first control circuit comprises: a first control switch, having a first end electrically coupled to the first terminal configured to receive the input signal, a second end electrically coupled to the backgate of the NMOS and a control end configured to receive a third control signal; a second control switch, having a first end electrically coupled to the backgate of the NMOS, a second end electrically coupled to a reference ground and a control end configured to receive a fourth control signal; and a first RS flip latch having a SET input, a RESET input, a first output and a second output, wherein the first output of the first RS flip latch is electrically coupled to the control end of the first control switch configured to provide the third control signal, and the second output of the first RS flip latch is electrically coupled to the control end of the second control switch configured to provide the fourth control signal; wherein when the switching control signal is in a first logic state, the SET input is enabled, the first control switch is turned ON and the second control switch is turned OFF, and when the switching control signal is in a second logic state, the RESET input is enabled, the first control switch is turned OFF and the second control switch is turned ON.