Patent ID: 8225047
Filing Date: 2012-07-17
Classification: G06F

Abstract:
1. A memory system comprising: a volatile semiconductor memory; a nonvolatile semiconductor memory from which data is read out and to which data is written in a page unit and in which data is erased in a block unit, the block unit being twice or larger natural number times as large as the page unit; and a controller configured to transfer data stored in the nonvolatile semiconductor memory to the volatile semiconductor memory, when the data designated by a readout request is stored in the nonvolatile semiconductor memory, said controller configured to predict the amount of data to be transferred based on at least one prior data transfer and to perform one of a first pre-fetch and a second pre-fetch in dependence upon the predicted amount of data to be transferred, wherein performing the first pre-fetch includes reading out data, from the nonvolatile semiconductor memory to the volatile semiconductor memory, which corresponds to data between a terminal end of a logical address range designated by a readout request being currently processed and a boundary of a logical address aligned in the page unit in which the terminal end is included; and performing the second pre-fetch includes reading out data, from the nonvolatile semiconductor memory to the volatile semiconductor memory, which corresponds to data between a terminal end of a logical address range designated by a readout request being currently processed and a next boundary of the logical address aligned in the page unit.