Patent ID: 8488408
Filing Date: 2013-07-16
Classification: G11C,H05K

Abstract:
1. A semiconductor memory device comprising: echo clock circuitry including at least one data output circuit and an echo clock output pair (CQ and CQB), wherein the echo clock circuitry is configured to provide an echo clock signal as a function of a reference clock signal; first power and ground pads for the echo clock outputs, the power pads being dedicated, wherein the power pads for the echo clock outputs CQ and CQB are connected, and ground pads for the echo clock outputs CQ and CQB are connected; second power and ground pads for data output circuits, wherein the data output power pads are connected together and the data output ground pads are connected together; wherein buses associated with each of the first power and ground pads are separate/distinct from respective buses of the second power and ground supply pads/buses.