Patent ID: 8476715
Filing Date: 2013-07-02
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a first region and a second region; first conductive lines on the first region, the first conductive lines being laterally spaced apart at a first interval; second conductive lines on the second region, the second conductive lines being laterally spaced apart at a second interval, the second interval being wider than the first interval; a first dielectric layer in spaces between the first conductive lines, a top surface of the first dielectric layer being lower than top surfaces of the first conductive lines; a second dielectric layer in spaces between the second conductive lines, the first dielectric layer having a dielectric constant different from a dielectric constant of the second dielectric layer; a barrier insulating pattern between the first dielectric layer and the first conductive lines, the barrier insulating pattern including a bottom portion parallel with the substrate and sidewall portions extending from side ends of the bottom portion; and a spacer within the spaces between the first conductive lines, the spacer having an etching selectivity with respect to the first dielectric layer, and the spacer covering an entire top surface of the first dielectric layer and top surfaces of the sidewall portions of the barrier insulating layer, the top surfaces of the sidewall portions being below the spacer.