Patent ID: 8860186
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. An integrated circuit comprising: a semiconductor substrate having a first surface topped with a stack of interconnection levels, each interconnection level comprising conductive tracks separated by an insulating material; at least one via crossing the semiconductor substrate providing an electric connection between a second surface of the semiconductor substrate and at least one of the conductive tracks, the walls and the bottom of said at least one via being covered by a conductive layer; and in an interconnection level or at the surface of the stack of interconnection levels and opposite to said at least one via, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, wherein said at least one region is insulated from the conductive tracks and extends at least to an outer boundary of a projection of a cross-section of said at least one via on to said at least one region.