Patent ID: 6323711
Filing Date: 2001-11-27
Classification: H03K

Abstract:
A programmable clock generator for modifying the non-overlap period between two non-overlapping clock signals, comprising:a first logic gate having first and second inputs and a first output, wherein said first input receives an input clock signal and said first output outputs a first non-overlapping clock signal;a second logic gate having third and fourth inputs and a second output, wherein said third input receives an inverted input clock signal and said second output outputs a second non-overlapping clock signal;a first delay module having a fifth input coupled to said first output of said first logic gate and having a third output coupled to said fourth input of said second logic gate, wherein said first delay module comprises:a first delay path that receives said first non-overlapping clock signal, wherein said first delay path comprises a first plurality of serially-connected delay elements,a first plurality of connection points, wherein each of said first plurality of connection points is located after a different one of said first plurality of serially-connected delay elements, anda first multiplexer coupled to said first plurality of connection points, wherein said first multiplexer selects one of said first plurality of connection points and receives a delayed clock signal from said selected connection point, and wherein the amount of delay introduced by said first delay module is modified by changing which one of said first plurality of connection points is selected by said first multiplexer; anda second delay module having a sixth input coupled to said second output of said second logic gate and having a fourth output coupled to said second input of said first logic gate.