Patent ID: 7800228
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A semiconductor structure comprising: A lower interconnect level comprising a first dielectric material having at least one conductive feature embedded therein, said at least one conductive feature is spaced apart from said first dielectric layer by a barrier layer; an upper interconnect level comprising a second dielectric material having at least one opening that is in direct contact with said at least one conductive feature of the lower interconnect level, wherein said at least one opening comprises a via having at least one vertical sidewall that is located atop the at least one conductive feature within the first dielectric material, said via is misaligned relative to the surface of said at least one conductive feature; a dielectric capping layer located, in part, between said upper and lower interconnect levels, said dielectric capping layer extends upon a portion of the at least one conductive feature of said lower interconnect level; a Co-containing buffer layer disposed in said at least one opening on an exposed upper surface of said at least one conductive feature of the lower interconnect level and on exposed upper surface of the barrier layer which is recessed relative to the upper exposed surface of the at least one conductive feature, wherein a portion of said Co-containing buffer layer laterally abuts a sidewall of said dielectric capping layer; first and second liners located within said at least one opening, wherein said first liner has a first portion on an entire top surface of said Co-containing buffer layer, and a second portion atop a recessed surface of the first dielectric material within said via that is misaligned, wherein the first liner is discontinuous between first and second portions; and a conductive material located on said second liner in said at least one opening.