Patent ID: 8563378
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: alternately forming insulating interlayers and sacrificial layers on a substrate, the insulating interlayers and the sacrificial layers having a first opening exposing the substrate; forming a semiconductor pattern in the first opening, the semiconductor pattern contacting the substrate and protruding above an uppermost insulating interlayer; forming a second opening through the insulating interlayers and the sacrificial layers, the second opening exposing a portion of the substrate adjacent to the semiconductor pattern; forming grooves among the insulating interlayers by selectively removing the sacrificial layers, the grooves partially exposing sidewalls of the semiconductor pattern; forming gate structures in the grooves, respectively; forming a common source line in the second opening, the common source line contacting the substrate and protruding above the uppermost insulating interlayer; forming an etch stop layer pattern on the semiconductor pattern wherein the semiconductor pattern protrudes above the uppermost insulating interlayer and on the common source line and wherein the common source line protrudes above the uppermost insulating interlayer; forming an additional insulating interlayer on the uppermost insulating interlayer; and forming contact plugs through the additional insulating interlayer, the contact plugs contacting the semiconductor pattern and the common source line, respectively.