Patent ID: 7199433
Filing Date: 2007-04-03
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device, comprising: a first memory cell of a dynamic random access memory including a transfer MISFET and a first capacitor element; a first conductive film electrically connected to one of a drain region and a source region of said transfer MISFET; a first insulating film formed on said first conductive film; and a second conductive formed on said first insulating film, wherein said first capacitor element is comprised on said first conductive film, said first insulating film and said second conductive film; a second memory cell of a static random access memory including a first first- channel MISFET, a second first-channel MISFET, a first second-channel MISFET, and a second second-channel MISFET, wherein a drain region of said first first-channel MISFET is electrically connected to a drain region of said first second-channel MISFET, a gate electrode of said second first-channel MISFET, and a gate electrode of said second second-channel MISFET, wherein a drain region of said second first-channel MISFET is electrically connected to a drain region of said second second-channel MISFET, a gate electrode of said first first-channel MISFET, and a gate electrode of said first second-channel MISFET; a third conductive film electrically connected to said drain region of said first first-channel MISFET; a second insulating film formed on said third conductive film; and a fourth conductive film formed on said second insulating film; wherein a second capacitor element is comprised of said third conductive film, said second insulating film and said fourth conductive film, wherein said third conductive film is comprised of a same level layer as said first conductive film, wherein said second insulating film is comprised of a same level layer as said first insulating film, and wherein said fourth conductive film is comprised of a same level layer as said second conductive film.