Patent ID: 6044225
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A data channel controller coupleable to a base computer system including a base memory, said data channel controller comprising:a) a pool memory including a plurality of first buffers;b) an arbiter system that implements a circular arbitration transfer mechanism and is coupled to said pool memory to selectively enable transfer of data with respect to a predetermined first buffer in response to first and second request signals;c) a peripheral device including a second buffer coupleable to said pool memory, said peripheral device operating to transport data through said second buffer with respect to a peripheral interface at a predetermined data demand transfer rate and to provide said first request signal to said arbiter system under first predetermined conditions with respect to the presence of data in said second buffer to obtain a transfer of data between said predetermined first buffer and said second buffer at a rate equivalent to said predetermined data demand transfer rate; andd) a base system interface including a third buffer coupleable to said pool memory, said base system interface providing said second request signal under second predetermined conditions with respect to the presence of data in said predetermined first buffer to obtain a transfer of data between said predetermined first buffer and base memory through said third buffer at a rate equivalent to said predetermined data demand transfer rate.