Patent ID: 6603680
Filing Date: 2003-08-05
Classification: G11C

Abstract:
A semiconductor device which allows one electrically erasable and programmable nonvolatile memory cell to store multi-valued information therein, comprising:a sense latch having a pair of input/output terminals; bit lines provided in association with the respective input/output terminals of the sense latch; a plurality of nonvolatile memory cells selectively connected to the bit lines and capable of electrically performing erasure and writing; data latches respectively connected to the bit lines; a first logic combining circuit connected to the data latches and the sense latch; and a control circuit connected to the sense latch, the data latches and the first logic combining circuit; wherein the first logic combining circuit generates control data used to define to which threshold voltage state a threshold voltage state of one nonvolatile memory cell is set, every plural bits of write data and to supply the generated data to the corresponding sense latch and data latches respectively on a parallel basis, and wherein the control circuit is capable of performing program control so as to control the operations of the sense latch, the data latches and the first logic combining circuit to thereby bring each volatile memory cell to a predetermined threshold voltage state according to a logic value of the control data supplied from the first logic combining circuit to the sense latch and successively bring volatile memory cells to predetermined threshold voltage states according to logic values of control data supplied from the data latches to the sense latch.