Patent ID: 8432200
Filing Date: 2013-04-30
Classification: H03L

Abstract:
1. A phase-locked loop (PLL), comprising: a calibration circuit for generating a calibration current; a voltage-controlled oscillator (VCO), including: a phase detector, connected to the VCO, for generating an error signal based on an input reference signal and a fraction of the oscillator signal; a current adder circuit, connected to the voltage-to-current converter and the calibration circuit, for summing a fraction of the first current and a fraction of the calibration current to generate a second current; a reference current generation circuit, connected to the calibration circuit, for generating a third current; a dual charge pump circuit, including a first charge pump and a second charge pump, connected to the phase detector and the current adder circuit, for receiving the error signal and the second current, and generating first and second charge pump currents having a predetermined ratio, wherein the second charge pump current is generated by summing a fraction of the second current and a fraction of the third current; and an active loop filter connected to the dual charge pump circuit, the reference current generation circuit and the voltage-to-current converter, wherein the active loop filter generates the control voltage based on the first and second charge pump currents, and wherein the active loop filter includes: