Patent ID: 6779104
Filing Date: 2004-08-17
Classification: G06F

Abstract:
An apparatus to process instructions comprising an out-of-order processor having a set of architectural registers readable and writable by the instructions, the out-of-order processor to predict a direction of an execution path among certain of the instructions, to determine a set of the certain instructions in the predicted path that do not employ the output of any other instructions in the same path, to form a block of instructions from at least some of the instructions in the set, to copy the architectural registers specified in the block of instructions to respective separate registers, to replace the register specifications in the block of instructions to specify the separate registers rather than the architectural registers themselves, to determined, after replacing all the register specifications, an improved execution order among all the instructions in the block so as to increase performance of the processor, to execute the instructions in the improved order, to determine that the predicted execution path direction is valid, and to write, after determining that the direction is valid, at least some of the separate registers to respective ones of the architectural registers.