Patent ID: 6539511
Filing Date: 2003-03-25
Classification: G01R

Abstract:
A semiconductor integrated circuit device comprising:at least one I/O cell coupled to a pad and including at least one of an input circuit for inputting a signal and an output circuit for outputting a signal; at least one test cell including a boundary scan register provided in correspondence to the circuit included in said I/O cell, said boundary scan register capable of serially transferring test data in a boundary scan test mode in accordance with a shift instruction; and test control circuitry for setting said boundary scan register of said test cell in either one of a set state and a reset state in response to a test mode instruction signal to set a logical level of an output signal of said boundary scan register to a prescribed value, for setting an operating state of said I/O cell in accordance with said output signal from said boundary scan register of said test cell.