Patent ID: 6366936
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A pipelined FFT (fast Fourier transform) processor including a CBFP (convergent block floating point) algorithm, comprising:an inverse multiplexer for inverse-multiplexing an 8K-/2K-point input data; a first to sixth radix-4 operation circuit for receiving an output of the inverse multiplexer and performing a butterfly operation; a multiplexer connected between the first and second radix-4 operation circuits and for selectively outputting an output of the inverse multiplexer or a first butterfly unit; a radix-2 operation circuit connected to the sixth radix-4 operation circuit and for performing a butterfly operation; a convergent block floating point circuit connected to respective output terminals of the radix-4 operation circuit and the radix-2 operation circuit and for scaling a butterfly operation result; an addition circuit for accumulation and adding scaling indexes outputted from the convergent block floating point circuit; and a decoder for scaling an output of the radix-2 operation circuit in accordance with the scaling indexes outputted form the addition circuit.