Patent ID: 7994072
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above a first transistor formed above a substrate, said first stress-inducing layer generating a first type of strain in a channel region of said first transistor; forming a first interlayer dielectric material above said first stress-inducing layer; forming a second stress-inducing layer above said first transistor, said second stress-inducing layer generating said first type of strain in said channel region of said first transistor; forming a second interlayer dielectric material above said second stress-inducing layer; and forming a contact opening in said first and second interlayer dielectric materials using said first and second stress-inducing layers as etch stop layers, wherein an average thickness of said first interlayer dielectric material is greater than a thickness of said first stress-inducing layer and a thickness of said second stress-inducing layer, respectively.