Patent ID: 6865706
Filing Date: 2005-03-08
Classification: G01R

Abstract:
1. A method for testing an integrated circuit, the method comprising: defining a list of faults for which an integrated circuit is tested; generating a test vector comprising a plurality of bits defining test inputs to the integrated circuit; assigning values to a portion of the plurality of bits of the test vector to detect at least one unmarked target fault selected from the list of faults, whereby a remainder of the bits of the test vector are left as unspecified bits; marking said at least one unmarked target fault as detected; repeating the generating, assigning, and marking until all target faults of the list of faults are marked; non-randomly filling a plurality of the unspecified bits for each test vector with values that enable each test vector to be compressed; and compressing each test vector to create a compressed vector having fewer bits.