Patent ID: 7012310
Filing Date: 2006-03-14
Classification: G11C,H01L

Abstract:
1. An array of Read Only Memory (ROM) cells, each cell for storing one of n (n>2) possible states, said array comprising: a semiconductor substrate of a first conductivity type having a first concentration; an array of ROM cells arranged in a plurality of rows and columns in said substrate; each ROM cell having a first region of a second conductivity type in said substrate different from said first conductivity type; a second region of said second conductivity type in said substrate, spaced apart from said first region; a channel between said first region and said second region; said channel having three portions: a first, a second and a third portion; a gate spaced apart and insulated from at least said second portion of said channel; said ROM cell being in one of a plurality of n (n>2) possible states, characterized by: said array of ROM cells arranged with ROM cells in the same row having their gates connected in common; said array of ROM cells arranged with ROM cells in the same column having their first regions connected in common, and second regions connected in common, with each pair of columns of adjacent ROM cells sharing a common first region; and wherein said one of a plurality of n (n<2) possible states of each ROM cell is determined by supplying a first voltage to said gate; a second voltage to said first region and a third voltage to said second region; and measuring a first current flowing from said second region to said first region; and supplying said first voltage to said gate; a second voltage to said second region and a third voltage to said first region; and measuring a second current flowing from said first region to said second region; and determining said one state based upon said first current measured and said second current measured.