Patent ID: 6377089
Filing Date: 2002-04-23
Classification: H03K

Abstract:
An output driver reducing overshoots of voltage at a first power supply voltage and undershoots of voltage at a second power supply voltage, comprising:a first circuit for converting a first input signal to a first voltage that exceeds the first power supply voltage; a second circuit for converting a second input signal to a second voltage that exceeds the first power supply voltage, the second input signal being complementary to the first input signal; a first n-channel pull up field-effect transistor (FET), having a drain terminal coupled to the first power supply voltage, a source terminal coupled to an output node, and a gate terminal coupled to the first voltage, wherein the first n-channel pull up FET couples the first power supply voltage to the output node when the first n-channel pull up FET is on; a first n-channel pulldown FET, having a source terminal coupled to the second power supply voltage, a drain terminal coupled to the output node, and a gate terminal coupled to the second voltage, wherein the first n-channel pulldown FET couples the second power supply voltage to the output node when the first n-channel pulldown FET is on; a second n-channel pull up FET, having a drain terminal coupled to a third voltage between the first and second power supply voltages in magnitude, a source terminal coupled to the output node, and a gate terminal coupled to the first voltage, the second n-channel pull up FET being turned off when a voltage at the output node monotonously increases from the third voltage to first power supply voltage; a second n-channel pulldown FET, having a source terminal coupled to a fourth voltage between the second power supply voltage and the third voltage in magnitude, a drain terminal coupled to the output node, and a gate terminal coupled to the second voltage, the second n-channel pulldown FET being turned off when a voltage at the output node monotonously decreases from the fourth voltage to the second power supply voltage; and whereby a voltage swing at the output node includes a fall range of voltages between the first and second power supply voltages.