Patent ID: 6327650
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A computer systemmemory for storing data and programs of instructions;a downstream processor for manipulating said data in accordance with said instructions, said downstream processor being coupled to said memory for fetching said instructions and for reading data therefrom and writing data thereto, said downstream processor having a downstream register set including a first bank and a second bank, said downstream processor reading from and writing to an active one of said first bank and said second bank;a bank selector for determining which one of said first and second banks is the active bank and which is not the active bank;an upstream processor for manipulating said data in accordance with said instructions, said upstream processor being coupled to said memory for fetching said instructions and for reading data therefrom and writing data thereto, said upstream processor having an upstream register set, said upstream processor reading data from said upstream register set, said upstream processor concurrently writing to said upstream register set and the one of said first and second banks of said downstream processor that is not the active bank; andcontrol logic for receiving program-done indications from said upstream and downstream processors, said control logic issuing a context-switch command to said bank selector at least in part as a function of said program-done indications;wherein said upstream register set includes a third bank of registers and a fourth bank of registers, said bank selector changing which one of said first and second banks is the active bank for said second processor and which one of said third and fourth banks is the active bank for said first processor in response to said context-switch command.