Patent ID: 6544824
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A method of fabrication of a vertical transistor; comprising the steps of:a) forming a doped region in a substrate; forming sequentially on substrate, a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer; b) forming a trench through said first spacer dielectric layer, said first gate electrode, said second spacer dielectric layer, said second gate electrode and said third spacer dielectric layer; said trench having sidewalls; c) forming a gate dielectric layer over said sidewalls of said trench; d) forming sequentially, in said trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer; e) forming a cap layer over said third spacer dielectric layer and said fourth doped layer; and f) forming contacts to said doped region, said first gate electrode said second doped layer, and said fourth doped layer.