Patent ID: 7843830
Filing Date: 2010-11-30
Classification: H04L

Abstract:
1. A packet switch comprising: a switch fabric having multiple input and output data ports; a plurality of ingress port pipes connected to provide input data to corresponding switch fabric input data ports; a plurality of egress port pipes connected to receive output data from corresponding switch fabric output data ports; a first ingress unit connected to provide input data to at least one of the ingress port pipes, the ingress unit transmitting epoch-formatted first packet data on the connected ingress port pipe during a first epoch and temporarily retaining the first packet data in memory beyond the end of the first epoch, the ingress unit comprising retransmission logic capable of initiating a retransmission of the retained first packet data during at least a second epoch; and a first egress unit connected to receive output data from at least one of the egress port pipes, the egress unit receiving the epoch-formatted first packet data on the connected egress port pipe, the egress unit comprising a data integrity unit to check the epoch-formatted first packet data for errors, and retransmission logic, comprising a retransmit monitor to track the error performance for epoch data received by the egress unit, capable of generating an error signal to another component of the packet switch when the epoch-formatted first packet data is received with an error and disabling error signal generation when the error performance does not meet an error criteria.