Patent ID: 9218780
Filing Date: 2015-12-22
Classification: G09G,G11C

Abstract:
1. A gate driving circuit including two sets of cascaded shift registers, wherein each of shift registers in a first set of cascaded shift registers is connected to a corresponding odd row gate line, and each of shift registers in a second set of cascaded shift registers is connected to a corresponding even row gate line; each of the shift registers is further connected to two Thin Film Transistors TFTs, wherein sources of the two TFTs are both connected to an output terminal of a shift register, drains of the two TFTs are both connected to a first level signal line, and gates of the two TFTs receive a first control signal and a second control signal respectively, so that at least one of the two TFTs is turned on when the shift register to which the two TFTs are connected outputs a switching-off voltage; wherein a first clock signal and a second clock signal of the first set of cascaded shift registers are configured respectively to be the first control signal and the second control signal of the two TFTs connected to a corresponding shift register of the second set of cascaded shift registers, and a first clock signal and a second clock signal of the second set of cascaded shift registers are configured respectively to be the first control signal and the second control signal of the two TFTs connected to a corresponding shift register of the first set of cascaded shift registers.