Patent ID: 6834320
Filing Date: 2004-12-21
Classification: G06F

Abstract:
An optimized bus connection for acceptance of bus transactions, provided with a first store operating according to a FIFO principle, in which bus transactions arriving from a higher-level processor system for execution by the optimized bus connection are temporarily stored in their sequence of arrival, the optimized bus connection comprising:a first functional section coupled to an output of the first store for classifying the bus transactions temporarily stored in the first store, and including means for classifying those transactions that must be executed in a strictly logical sequence as a first class of transactions, and those transactions that do not have to be executed in a strictly logical sequence as a second class of transactions, a second functional section coupled to an output of said first functional section and comprising at least first and second functional lines disposed in parallel, wherein said first functional line is allocated to the first class of transactions, and is provided with a storage structure functioning according to the FIFO principle, and wherein said second functional line is allocated to said second class of transactions, and has a storage structure suitable for random accesses, and a third functional section with an execution unit coupled to the functional lines of the second functional section, and comprising means for organizing the transactions allocated to said at least first and second functional lines of the second functional section into a serial sequence for forwarding to the higher-level processor system, wherein the organizing means of said execution unit moves a transaction of the second class ahead of a transaction of the first class, depending on a state of the higher-level processor system.