Patent ID: 8614463
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A layout configuration for a memory cell array comprising: a top area, a bottom area, and a plurality of gap areas defined between the bottom area and the bottom area; a pair of comb-like doped layers having a first conductivity type respectively formed in the top area and the bottom area; a dual fishbone layer comprising at least a first fishbone-shaped doped region having a second conductivity type formed in the gap areas, the second conductivity type and the first conductivity type being complementary; and at least a second fishbone-shaped doped layer having the first conductivity type formed in the gap areas, wherein the comb-like doped layers are physically contacted with the first fishbone-shaped doped region, and the first fishbone-shaped doped region is physically contacted with the second fishbone-shaped doped layer.