Patent ID: 8316284
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A method of error correction code (ECC) debugging for a system comprising: receiving data having an ECC; determining whether a data error has occurred; generating a first syndrome of an error result; decoding flipped data bits; determining whether the data error is correctable; processing the received data and the decoded flipped bits to correct the data based on determining that the data error is correctable; outputting corrected data having an ECC; generating a trap update signal based on determining that the data error is uncorrectable; saving the first syndrome in a first register; saving a second syndrome in a second register; inputting contents of the first register and the first syndrome into a first comparator; inputting contents of the second register and the first syndrome into a second comparator; determining whether the trap update signal matches an output of the first comparator; incrementing a first debug counter based on determining that the trap update signal matches the output of the first comparator; determining whether the trap update signal matches an output of the second comparator; incrementing a second debug counter based on determining that the trap update signal matches the output of the second comparator; receiving the trap update signal; and saving the received data having an ECC based on receiving the trap update signal.