Patent ID: 9153294
Filing Date: 2015-10-06
Classification: G11C

Abstract:
1. A semiconductor memory device connected to a memory controller, the semiconductor memory device comprising: a cell array comprising a plurality of cell regions; a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address; and a refresh address generator configured to generate the counting address and a modified address as a refresh address in response to a control signal provided from the memory controller, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells, wherein the refresh address indicates that a refresh operation is to be performed on only the first cell region where the control signal is in a first logic state, and the refresh address indicates that a refresh operation is to be performed on both the first and second cell regions where the control signal is in a second logic state.