Patent ID: 8605526
Filing Date: 2013-12-10
Classification: G11C

Abstract:
1. A memory device, comprising: a memory cell comprising: a pair of cross-coupled inverters configured to cooperatively store at least one bit of data, and first and second access transistors having their respective sources coupled to respective inputs of the inverters; first and second bitlines coupled to respective drains of the first and second access transistors, respectively; a wordline coupled to first and second gates of the first and second access transistors, respectively; first and second bitline drivers coupled to the first and second bitlines, respectively; the first and second bitline drivers configured to selectively assert a predetermined current pulse to the first and second bitlines based on an expected data state to be written to the memory cell; and distortion circuitry coupled to the first and second bitlines and configured to add current to or subtract current from at least one of the first or second bitlines while the wordline is asserted to test a write or read margin of the memory cell; wherein the distortion circuitry comprises pre-charge circuitry coupled to at least one of the first and second bitlines, wherein the pre-charge circuitry is configured to deliver a pre-determined charge to the at least one bitline in order to test the write or read margin of the memory cell; and wherein the pre-charge circuitry comprises: pull down circuitry coupled to at least one of the first and second bitlines and configured to selectively add or subtract the current from the at least one of the first and second bitlines to test the write or read margin.