Patent ID: 6072737
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A test circuit in an embedded DRAM including an array of memory cells, a logic circuit, and the test circuit formed in a semiconductor substrate, the test circuit comprising:a first external terminal adapted to receive at least one test signal;a plurality of comparison circuits, each comparison circuit including a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal, and each comparison circuit comparing the binary values of the read and expect data signals and developing an inactive error signal on an output when the compared signals have the same binary values and an active error signal when the compared signals have different binary values;a storage circuit coupled to the outputs of the comparison circuits, the storage circuit latching the en-or signals output by the comparison circuits and sequentially transferring the latched error signals onto a second external terminal of the embedded DRAM; anda test control circuit coupled to the comparison circuits, the first external terminal, and the storage circuit the test control circuit operable responsive to the at least one test signal being active to apply data from addressed memory cells respectively on the first inputs of the comparison circuits and apply respective expect data on the second inputs of the comparison circuits, and the test control circuit controlling the storage circuit to latch the resulting error signals and thereafter sequentially transfer the latched error signals onto the second external terminal.