Patent ID: 7099207
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array, which comprises a plurality of memory cells, at least one of the plurality of memory cells storing program data received from a memory; a row address buffer, which receives a row address signal via an address pin in response to a first strobe signal; a column address buffer, which receives a column address signal via the address pin in response to a second strobe signal; a write protection circuit, which is enabled or disabled in response to a first control signal, the write protection circuit, when enabled, outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals; and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array corresponding to the decoded column address signal, or disables the column selection lines of the memory cell array.