Patent ID: 7098702
Filing Date: 2006-08-29
Classification: H03F

Abstract:
1. A transconductor circuit comprising: a main circuit comprising a first MOS transistor, a second MOS transistor connected to the first MOS transistor in differential pair arrangement, and first and second resistors connected between sources of the first and second MOS transistors; an auxiliary circuit comprising a third MOS transistor connected to a drain of the first MOS transistor and a fourth MOS transistor connected to a drain of the second MOS transistor, the third and fourth MOS transistors being electronically interconnected; and a plurality of current sources which supply main and the auxiliary circuits with bias currents, wherein a first input voltage is applied to a gate of the first MOS transistor of the main circuit; a second input voltage is applied to a gate of the second MOS transistor; an input voltage is a difference between the first and second input voltages; the auxiliary circuit is designed so that the third and fourth MOS transistors operate in sub-threshold regions when the input voltage is within a first range between a negative constant voltage—Va and a positive constant voltage Va, and so that one of the third and fourth MOS transistors operates in a saturation region when the input voltage is within a second range between less than the negative constant voltage—Va and more then the positive constant voltage Va; a gate of the third MOS transistor is connected to the source of the first MOS transistor and a drain of the third MOS transistor is connected to the drain of the first MOS transistor; and a gate of the fourth MOS transistor is connected to the source of the second MOS transistor and a drain of the fourth MOS transistor is connected to the drain of the second MOS transistor.