Patent ID: 6728851
Filing Date: 2004-04-27
Classification: G06F,G11C

Abstract:
A memory storage system for increasing the performance of write operations of sector information to storage locations within nonvolatile memory unit, said nonvolatile memory unit including one or more nonvolatile memory devices, the sector locations organized into sub-blocks, each sub-block including more than one sector and each sub-block being individually addressable and erasable and a plurality of sub-blocks defining a block comprising:memory control circuitry, coupled to the nonvolatile memory unit, responsive to sectors which each include sector information, received from a host, said received sectors being identified by sectors numbers of a predetermined order, said memory control circuitry for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said particular block being identified by the same virtual physical block address (VPBA) and assignable based upon the identification of a free location within said memory unit, said memory control circuitry for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block and regardless of the predetermined order of the sector numbers of the received sectors, wherein writing of sector information to the first sector locations of the sub-blocks of the particular block are performed substantially concurrently thereby increasing the performance of write operations.