Patent ID: 6134653
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A processor, comprising:a) an instruction sequencer;b) an instruction RAM associated with said instruction sequencer;c) a data bus and an instruction bus, said instruction sequencer being coupled to said data bus and said instruction bus;c) an arithmetic logic unit coupled to said data bus and said instruction bus;d) a plurality of general purpose registers associated with said arithmetic logic unit, said plurality of general purpose registers being arranged as at least two sets; ande) means for exclusively selecting each set, one at a time, for access by said arithmetic logic unit in response to an instruction from said instruction sequencer;f) a shared set of general purpose registers which are always accessible to said arithmetic logic unit regardless of which one of said at least two sets is selectively and exclusively accessed; andg) coprocessor interface means for coupling a coprocessor to at least one of said two sets of registers when said at least one of said two sets of registers is not exclusively selected for access by said arithmetic logic unit such that the coprocessor can load said at least one of said two sets of registers when it is not being accessed by said arithmetic logic unit.