Patent ID: 7895488
Filing Date: 2011-02-22
Classification: G01R

Abstract:
1. A circuit comprising: clock gating circuitry receiving first and second input signals, wherein said first input signal is a clock signal, said circuit operating in first and second modes, wherein said clock gating circuitry prevents propagation of said clock signal as a function of said second input signal during said first mode; and further circuitry sending a control signal to said clock gating circuitry to control said clock gating circuitry independent of said second input signal so that said clock signal propagates through said clock gating circuitry when said circuit operates in said first mode, wherein the clock gating circuitry receives the control signal at a test enable port for testing transition delay faults at the test enable port, wherein said first mode is a test mode, and said second mode is a functional mode, and wherein said second input signal is a pseudorandom test pattern.