Patent ID: 6353260
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A semiconductor device in which an electrically conductive substrate is covered with a dielectric layer comprising:a trench with a dual damascene structure comprising a trench line space stacked above a contact hole in said dielectric layer, said trench reaching down to expose a portion of said substrate, said trench having walls, a tantalum metal film is formed superjacent to said dielectric layer covering said walls of said trench and covering said portion of said substrate, grain boundaries of said tantalum metal film having been filled with at least one of tantalum oxide and tantalum nitride forming a stuffed tantalum metal film, with a film filling grain boundaries/interstices with additional tantalum oxide formed on the surface of the tantalum metal film, a copper seed film formed above said stuffed tantalum metal film, a bulk copper layer superjacent to said copper seed film, and said device was planarized to expose the top surface of said dielectric layer, with surplus portions of said filled tantalum metal film, said copper seed film, and said bulk copper layer removed.