Patent ID: 6643738
Filing Date: 2003-11-04
Classification: G06F

Abstract:
A data processor with a cache memory, the cache memory comprising:an input for receiving a main memory address; a plurality of cache memory locations; an associative memory for storing at least a first and second groups of associations for mapping the main memory address to the plurality of cache memory locations, one or more cache memory location of the plurality of cache memory locations being dynamically assignable to either of the first or second group for use in associations; selection means for selecting a selected group for the main memory address; and an address mapping unit arranged for selecting and addressing an addressed cache memory location that is associated with the main memory address in the selected group; wherein a stream access unit for accessing data in the cache memory for a stream of iteratively computed main memory addresses, the data processor being arranged to associate the main memory addresses of accessed data from the stream upon access for that stream all to cache memory locations using associations of the first group; wherein the address mapping unit maps the main memory addresses for which the first group is selected on the basis of their rank number in the stream.