Patent ID: 6601220
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A method for determining the precharge time of a domino logic circuit having a plurality of cascaded stages, at least one stage having an unclocked evaluation path, the method comprising:decomposing the at least one stage into at least one channel connected component; simulating the channel connected component to determine the pull-up time of the channel connected component relative to a transition of a clock signal; determining the pull-up times of the stages excluding the at least one stage, the pull-up time for each said stage comprising the time difference between the trailing edge of an output signal from the respective stage and the trailing edge of the clock signal; and summing the pull-up time of the channel connected component with the pull-up times of the stages excluding the at least one stage to determine the precharge time of the domino logic circuit.