Patent ID: 7247532
Filing Date: 2007-07-24
Classification: H01L

Abstract:
1. A method for fabricating a high voltage transistor, comprising: preparing a substrate including an insulation layer and a silicon layer formed on the insulation layer; patterning the silicon layer to definite a transistor region; forming a highly concentrated drain junction region of a first conductive type by implanting a first conductive type impurity to the transistor region; forming a drain junction region of the first conductive type on the highly concentrated drain junction region of the first conductive type by growing an epitaxial layer of the first conductive type; forming a body region of a second conductive type in a predetermined portion of the drain junction region of the first conductive type; forming a plurality of gate patterns in other predetermined portions of the drain junction region bordered by the body region of the second conductive type and the drain junction region of the first conductive type; and forming a plurality of highly concentrated drain regions of the first conductive type and a plurality of highly concentrated source regions of the first conductive type by implanting the first conductive type impurity to the drain junction region of the first conductive type and the body region of the second conductive type.