Patent ID: 7243173
Filing Date: 2007-07-10
Classification: G06F

Abstract:
1. A method for receiving parallel address, data and control bus information from a microelectronic CPU and transferring said information at a transfer rate of at least 800 Mbaud to a destination at a distance of at least three inches from the microelectronic CPU and presenting the data as reconstituted parallel address, data and control bus information for utilization by peripheral devices, the method comprising: receiving the parallel address, data and control bus information near the microelectronic CPU and converting said information to serial data information in a plurality of serial data streams, including read/write type and transaction number information in the serial data information, wherein the transaction number information changes with each new transfer, transmitting the serial data streams to peripheral circuits near the destination and converting the serial data streams to parallel address, data and control bus information to reconstitute the microelectronic CPU information buses as peripheral information buses, wherein the serial data streams are transparent to the peripheral devices on the peripheral information buses; and wherein the converting of said information from the serial data streams to reconstituted parallel address, data and control bus information extracts the read/write type and the transaction number information to determine the occurrence of a new transaction and to assist in identifying the address and data information received in the serial data streams and is carried out without assistance by a second CPU on the peripheral information buses.