Patent ID: 7473618
Filing Date: 2009-01-06
Classification: H01L,H05K

Abstract:
1. A method for reducing stress and warpage in flip chip packages comprising: providing a flip chip package, the flip chip package including an organic substrate, an integrated circuit chip, and a cap member; providing a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip; soldering a bottom side of the organic substrate to a top side of the temporary structure, wherein solder interconnections are applied to a plurality of solder pads on the top side of the temporary structure, the position of the solder pads on the top side of the temporary structure mirroring the position of a plurality of solder pads on the bottom side of the organic substrate; bonding a bottom side of the integrated circuit chip to a top side of the organic substrate with controlled chip collapse columns; coupling the cap member to the top side of the organic substrate; applying a first force to the flip chip package in a first direction; and applying a second force to the temporary structure in a second direction opposite the first direction in order to shear the top side of the temporary structure from the bottom side of the organic substrate to remove the temporary structure from the flip chip package, wherein the first and second forces are parallel to the top side of the temporary structure, and wherein upon removal of the temporary structure from the flip chip package the solder interconnections remain on the solder pads on the bottom side of the organic substrate.