Patent ID: 7844934
Filing Date: 2010-11-30
Classification: G06F

Abstract:
1. A method for designing a semiconductor integrated circuit layout, comprising the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; automatically arranging, by a computer device, wiring between said basic logic cells; searching for a blank area in which none of said basic logic cells is arranged; forming a rectangular region in said blank area; arranging fill cells in said rectangular region and grouping said fill cells into pseudo-hierarchical cells to form a hierarchy; arranging fill cells in the remaining blank areas after each rectangular region is formed; and performing optical proximity effect correction on the semiconductor integrated circuit pattern, wherein the size of an X-direction of said rectangular region is more than twice the size of a corresponding X-direction of a smallest fill cell among said fill cells, and the size of a Y-direction of said rectangular region is more than twice the size of a corresponding Y-direction of said smallest fill cell.