Patent ID: 6251740
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of forming a substantially vertical plate capacitor in interlayer dielectric material which separates conductors of a relatively upper interconnect layer and a relatively lower interconnect layer in an integrated circuit, said method comprising the steps of:forming a capacitor via downward through the interlayer dielectric material to expose a conductor of the relatively lower interconnect layer;forming a first conductive layer having a U-shaped portion into the capacitor via and onto the exposed conductor of the relatively lower interconnect layer;forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer;forming a connection via in the interlayer dielectric to extend between the conductors of the relatively upper and relatively lower interconnect layers;forming a second conductive layer having a U-shaped portion on the U-shaped capacitor dielectric material; andforming a U-shaped portion of the second conductive layer in the connection via simultaneously with forming the U-shaped portion of the second conductive layer in the U-shaped capacitor dielectric material.