Patent ID: 6539070
Filing Date: 2003-03-25
Classification: H04L

Abstract:
A clock synchronizing circuit comprising:a sampler inputting thereto an input signal and a sampling clock, before outputting sampling signal by sampling said input signal with the condition of â€˜Nâ€™ times of symbol rate; a sequencer inputting thereto a symbol clock, a sequence start signal, and said sampling clock, before outputting a sign switching signal, a cosine component integration signal, a sine component integration signal, and an initial phase establishment signal; a cosine/sine output circuit inputting therein an integration clock, said sampling signal, said sign switching signal, said cosine component integration signal, and said sine component integration signal, before outputting a cosine signal corresponding to cosine component of an initial phase of said symbol clock and a sine signal corresponding to a sine component of the initial phase of said symbol clock; an angle detector inputting thereto said cosine signal and said sine signal, before obtaining initial phase of said symbol clock, thus outputting it as an initial phase signal; a sampling clock generation circuit inputting thereto said initial phase signal and said initial phase establishment signal, before outputting both of said sampling clock which has fixed phase before initial phase establishment, and which is subjected to phase control in such a way that said symbol clock is synchronized with said input signal at the time of initial phase establishment, and said integration clock; and a frequency divider for dividing said sampling clock into symbol clock with 1/N times frequency in order to input it to said sequencer.