Patent ID: 6571329
Filing Date: 2003-05-27
Classification: G06F

Abstract:
An information processing apparatus which includes one or more instruction fetch ports for fetching an instruction, and detects a possibility for overwrite of an instruction fetched from the instruction fetch port, comprising:an instruction fetch counter unit counting a length of an instruction sequence containing all instructions which are fetched before a last fetched instruction, said instructions and said last fetched instruction having sequential addresses; and an instruction overwrite possibility determination unit using an address of an instruction at a specified position in all instruction sequences, a storage target address at which an execution result of a completed store instruction is stored, and an output value of said instruction fetch counter unit, and detecting a possibility for overwrite of an instruction wherein: at least a part of a range of the storage target address overlaps the address of an instruction in all instruction sequences, and at least a part of the instruction sequences is overwritten.