Patent ID: 6892287
Filing Date: 2005-05-10
Classification: H04L

Abstract:
1. A reassembly control system for partial reassembly of portions of data frames using cells of the data frames received from a data network and for outputting partially reassembled frames to downstream logic, wherein the data network supports a plurality of concurrent connections and each of the data frames is associated with one of the plural connections, said reassembly control system comprising: a partial reassembly buffer comprising a random access memory and logically divided into a plurality of frame buffers, each sized for receiving the portion of each data frame to be partially reassembled; an input controller for receiving the cells of the data frames from the data network; and an output controller for outputting to a capture buffer the cells received by said input controller, wherein said input controller comprises means for determining, for each received cell, whether the each cell is in the portion of the data frame to be partially reassembled, means for transferring to said partial reassembly buffer the received cells that are determined to be in the portion of the data frame to be partially reassembled and for transferring to said output controller the received cells not determined to be in the portion of the data frame to be partially reassembled, and means for storing the transferred cells of each data frame as a contiguous block in a corresponding one of the plural frame buffers.