Patent ID: 6657461
Filing Date: 2003-12-02
Classification: G01R

Abstract:
An integrated circuit device having a switchable test circuit comprising:a clock input to said device for receiving an external clock signal; a clock buffer circuit coupled to receive said external clock signal and an internal clock signal derived from said external clock signal having a frequency substantially higher than said external clock signal; a clock selection signal having first and second states thereof coupled to said clock buffer circuit for alternatively causing said clock buffer circuit to couple said external clock signal to an internal clock signal line when said clock selection signal is in said first state thereof or to couple said internal clock signal to said internal clock signal line when said clock selection signal is in said second state thereof; a clock enable input to said device for receiving an external clock enable signal; a clock enable buffer circuit coupled to said clock buffer circuit to receive said external clock enable signal; a switch to select between the external clock signal and the internal clock signal; and an output coupled to the switch for providing either the external clock signal or the internal clock signal.