Patent ID: 7092476
Filing Date: 2006-08-15
Classification: G06F,H03L

Abstract:
1. A clock signal generator comprising: a phase detector for comparing a digital input clock signal with a reference signal to generate a digital phase detection signal; circuitry for generating a memory index from said digital phase detection signal; a memory storing digital data representing real and imaginary parts of a digital complex waveform accessible by said memory index; a digital to analog converter for converting digital data accessed from said memory into an analog complex waveform, the digital to analog converter comprising: low pass filters for filtering said real and imaginary parts of said digital complex waveform; bandpass filters for filtering the analog complex waveform to reduce jitter in a binary clock signal derived therefrom; and a phase locked loop for generating the binary clock signal from said analog complex waveform and a complex reference signal, wherein the binary clock signal has a rate near an integer multiple of a rate of said analog complex waveform.