Patent ID: 8846503
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane, comprising the steps of: (1) fabricating a substrate; (2) forming a first semiconductor material and a first oxide layer on the substrate; (3) treating lithography etching process to the first semiconductor material and the first oxide layer, so as to make the first semiconductor material to a stepped semiconductor layer on the substrate, wherein the stepped semiconductor layer comprises a bottom layer and a stair layer, and a height difference is formed between the bottom layer and the stair layer; (4) forming an isolation layer for covering the substrate, the stepped semiconductor layer and the first oxide layer except for a plurality of through holes opened on the bottom layer of the stepped semiconductor layer, wherein the through holes are used as epitaxy seed windows; (5) forming a second semiconductor material on the isolation layer, wherein part of the second semiconductor material would be filled into the through holes, so as to contact with the bottom layer of the stepped semiconductor layer; (6) treating lithography and etching process to define the second semiconductor material, so as to make the second semiconductor material to be a bar-shaped semiconductor covering the through holes and being across the step of the first semiconductor to form a disconnected overlapped semiconductor, wherein the bar-shaped semiconductor and the overlapped semiconductor are formed on the bottom layer and the stair layer of the stepped semiconductor layer, respectively; (7) forming a second oxide layer for covering the product of the aforesaid step (6), and modulating the thickness of the second oxide layer to completely cover the stepped semiconductor layer; (8) treating a rapid thermal anneal process to the product of the aforesaid step (7), so as to make the bar-shaped semiconductor laterally grow from the seed windows on the bottom layer toward the stair layer of the stepped semiconductor layer through epitaxy; (9) treating a wet etching process to the product of the aforesaid step (8), so as to remove the first oxide layer, the isolation layer, and the overlapped semiconductor on the stair layer, and the second oxide layer; and (10) a crystallized bar-shaped semiconductor layer is formed on the bottom layer of the stepped first semiconductor, wherein one end surface of the crystallized bar-shaped semiconductor layer is terminated to the vertical end surface of the stair layer of the stepped semiconductor layer.