Patent ID: 9064581
Filing Date: 2015-06-23
Classification: G06F,G11C

Abstract:
1. A method of operating a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including multi-level memory cells coupled to word lines and bit lines, the method comprising: performing a first program operation on selected memory cells coupled to a selected word line using a first Incremental Step Pulse Program (ISPP) scheme, the first program operation including, applying a first pass voltage to an unselected word line during a first program period; applying a second pass voltage higher than the first pass voltage to the unselected word line during a second program period following the first program period; and applying a third pass voltage higher than the second pass voltage to the unselected word line during a third program period following the second program period, wherein the first program period includes at least two program loops, each of the second program period and the third program period includes at least one program loop, and memory cells coupled to the unselected word line and the selected memory cells coupled to the selected word line are included in a same memory block among the plurality of memory blocks, wherein the first program operation is a most significant bit (MSB) page program operation, further comprising: performing a second program operation on the selected memory cells coupled to the selected word line using a second ISPP scheme, wherein the second program operation is a least significant bit (LSB) page program operation.