Patent ID: 7188229
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A method of handling translation lookaside buffer (TLB) miss exceptions in a memory management unit of a multi-processor computer system having a plurality of Central Processing Units (CPU's), the method comprising: initiating an access instruction; determining that a TLB miss exception event has occurred, wherein determining that a TLB miss exception event has occurred includes testing a context identifier for the affected virtual address to determine whether a TLB miss exception has occurred; invoking a miss exception handler; determining the nature of the TLB miss exception event; resolving the miss exception event; returning to initiating an access instruction; wherein determining the nature of the TLB miss exception event includes testing the context identifier for the affected virtual address to determine whether the TLB miss exception event results from one of an unassigned context identifier, a translation storage buffer (TSB) resizing operation that affects the virtual address, and an unmapping of a shared translation table entry (TTE) that is associated with the virtual address wherein the TTE comprises a shared memory resource; wherein resolving the miss exception events includes resolving each type of miss exception event in accordance with specified miss exception resolution protocol for each type of miss exception event.