Patent ID: 7505043
Filing Date: 2009-03-17
Classification: G06T

Abstract:
1. A device comprising: a cache configured to store data, said cache comprising a size; and a processor, coupled to said cache, configured to determine a size and a position of a bounding box that entirely encompasses a graphics image, to subdivide said bounding box to generate a plurality of sub-blocks upon determining that said size of said bounding box is not equal to said size of said cache, to process said sub-blocks based on a substantially Z-shaped pattern block processing order to determine when said sub-blocks overlap said graphics image, to subdivide said sub-blocks, upon determining that said sub-blocks have individual sizes that are not equal to said size of said cache, into a plurality of tiles for sub-blocks comprising graphics image data, such that each of said tiles is sized equal to said size of said cache, to load data, associated with a tile, into said cache, and to utilize said data in said cache to generate pixels for said associated tile of said graphics image.