Patent ID: 6468877
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of fabricating an air-gap spacer of a semiconductor device, comprising the steps of:providing a semiconductor substrate having at least a pair of STIs defining an active region; forming a gate electrode on said substrate within said active region; said gate electrode having an underlying gate dielectric layer; forming a liner oxide layer over the structure, covering the sidewalls of said gate dielectric layer, said gate electrode, and over the top surface of said gate electrode; forming a liner nitride layer over said liner oxide layer; forming a thick oxide layer over the structure; planarizing said thick oxide layer, said liner nitride layer, and said liner oxide layer level with said top surface of said gate electrode, and exposing said liner oxide layer at either side of said gate electrode; removing said planarized thick oxide layer and a portion of said liner oxide layer and a portion of said gate dielectric layer under said gate electrode to form a cross-section inverted T-shaped opening on either side of said gate electrode; forming a gate spacer oxide layer over the structure at least as thick as said gate electrode, wherein said gate spacer oxide layer partially fills said inverted T-shaped opening from the top down; wherein air gap spacers are formed proximate the bottom of said inverted T-shaped opening; and etching said gate spacer oxide layer, liner nitride layer, and liner oxide layer to form gate spacers proximate said gate electrode; said gate spacers having an underlying etched liner nitride layer and liner oxide layer.