Patent ID: 7979750
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. An apparatus in a data processing system for synchronizing the triggering of a plurality of hardware trace facilities using a system bus, said apparatus comprising: said plurality of hardware trace facilities including a first hardware trace facility and a second hardware trace facility; said data processing system including a first processor that includes said first hardware trace facility and a first plurality of processing units that are coupled together utilizing said system bus; said data processing system including a second processor that includes said second hardware trace facility and a second plurality of processing units that are coupled together utilizing said system bus; said system bus for transmitting information among said first and second plurality of processing units when said first and second processors are in a normal, non-tracing mode, said information being formatted according to a standard system bus protocol; said system bus for transmitting trigger events to said plurality of hardware trace facilities, said trigger events being formatted according to said standard system bus protocol; one of said plurality of hardware trace facilities selected to be a master hardware trace facility; and said master hardware trace facility transmitting trigger events generated within said master hardware trace facility to said plurality of hardware trace facilities utilizing said system bus.