Patent ID: 6487125
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A non-volatile integrated circuit memory comprising:an EEPROM array comprising a first plurality of memory cells; and a flash EPROM array comprising a second plurality of memory cells, wherein a memory cell in each of the first and second plurality of memory cells includes a double-poly stacked-gate having a gate terminal, a source region having a terminal, and a drain region having a terminal, wherein the memory cell is programmed by inducing hot electron injection and erased by inducing electron tunneling both through its drain side, wherein a drain terminal of each memory cell in the EEPROM array is coupled to a bitline disposed within the EEPROM array through an associated drain-select transistor, and wherein the memory cells along a row in the EEPROM array are divided into a predesignated number of groups, the gate terminals of memory cells in each group being connected together and to first and second signal lines through an associated pair of first and second group-select transistors.