Patent ID: 6917119
Filing Date: 2005-07-12
Classification: H01L,H04B,H05K

Abstract:
1. A Chip Scale package using re-routed bump metal on a semiconductor surface, comprising: a contact pad overlying a semiconductor substrate; a passivation layer overlying said contact pad and said semiconductor substrate while exposing a part of said contact pad; a dielectric layer overlying said passivation layer and said contact pad while exposing a part of said contact pad; a layer of conductive material overlying said layer of dielectric and said exposed part of said contact pad; a re-routing metal layer overlying said layer of conductive material; and a solder bump overlying said re-routing metal layer wherein said solder bump comprises a stack of a solder layer overlying a pillar metal layer with a UBM layer therebetween and wherein said UBM layer overhangs the entire vertical edges of said pillar metal layer and wherein an oxide layer overlies the surfaces of said pillar metal layer and said UBM layer.