Patent ID: 7535760
Filing Date: 2009-05-19
Classification: G11C,H01L

Abstract:
1. A non volatile memory device, comprising: a memory cell array having a plurality of non volatile memory cells; a DRAM interface for exchanging data, a command and an address with an external device; a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device; and a DRAM buffer memory having a plurality of dynamic memory cells, each of the dynamic memory cells having one transistor with a floating body, the DRAM buffer memory performing one of receiving and buffering data from the memory cell array and outputting the buffered data to the DRAM interface in response to the control operation of the controller and buffering data received from the DRAM interface and outputting the buffered data to the memory cell array.