Patent ID: 7397131
Filing Date: 2008-07-08
Classification: H01L

Abstract:
1. A semiconductor device, comprising: first and second gate electrodes in a cell array region of a substrate and a third gate electrode in a peripheral region of the substrate, each gate electrode having opposing first and second sidewalls and a top surface, each of the first and second gate electrodes having an upper portion which is narrower than a bottom portion; a first impurity diffusion region in the cell array region between the first and second gate electrodes; a second impurity diffusion region in the peripheral region adjacent to the third gate electrode; a first silicide layer on the second impurity diffusion region; a silicon nitride liner on the sidewalls and on the top surface of each gate electrode; and a self-aligned contact pad between the first and second gate electrodes to be electrically connected to the first impurity diffusion region, wherein the first sidewalls of the first and second gate electrodes are adjacent to the self-aligned contact pad, wherein the upper portions of the first sidewalls of the respective first and second gate electrodes angle toward each other to present a sloped profile, and wherein the second sidewalls of the first and second gate electrodes are substantially vertical.