Patent ID: 7839711
Filing Date: 2010-11-23
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a semiconductor layer; a source layer and a drain layer provided within the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, the body region being in an electrically floating state, and the body region accumulating a charge or discharging a charge to store logic data; a gate dielectric film provided on the body region; a gate electrode provided on the body region via the gate dielectric film; a driver driving the gate electrode; and a sense amplifier sensing logic data from a memory cell including the source layer, the drain layer, and the body region, or writing logic data to the memory cell, wherein a refresh operation recovering degradation of logic data of the memory cell includes a first refresh operation and a second refresh operation, in the first refresh operation, a first potential higher than a potential of the gate electrode in a data holding state is applied to the gate electrode in a state having a potential substantially equal to a potential of the source layer applied to the drain layer, and thereafter a potential of the gate electrode in the data holding state is applied to the gate electrode, thereby a first current passes to the memory cell, and in the second refresh operation, a second potential higher than a potential of the gate electrode in the data holding state is applied to the gate electrode, and a third potential higher than a potential of the gate electrode in the data holding state is applied to the drain layer, thereby a second current passes to the memory cell, and a state of the memory cell is shifted to an equilibrium state in which an amount of the first current flowing during one cycle of the refresh operation becomes substantially equal to an amount of the second current flowing during one cycle of the refresh operation.