Patent ID: 6717839
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A self-referenced ferroelectric memory including bit-line shielding comprising:an array of 1T/1C ferroelectric memory cells including a word line node, a bit-line node, and a plate line node; a plurality of bit-line columns having a lower end and an upper end, coupled to the bit-line node of a first subset of the 1T/1C ferroelectric memory cells; a plurality of interleaved complementary bit-line columns having a lower end and an upper end, coupled to the bit-line node of a second subset of 1T/1C ferroelectric memory cells; a plurality of word line rows coupled to the word line nodes of the first subset of 1T/1C ferroelectric memory cells; a plurality of plate line rows coupled to the plate line nodes of the 1T/1C ferroelectric memory cells; a plurality of interleaved complementary word line rows coupled to the word line nodes of the second subset of 1T/1C ferroelectric memory cells; a pre-amplifier coupled to each of the upper end of the bit-line columns and complementary bit-line columns; a sample and hold circuit coupled to each of the preamplifiers; a sense amplifier coupled to each of the sample and hold circuits; means for grounding at least two adjacent bit-line columns in a first operational mode, coupled to the lower end of the bit-line columns; and means for grounding at least two adjacent complementary bit-line columns in a second operational mode, coupled to the lower end of the complementary bit-line columns.