Patent ID: 6418545
Filing Date: 2002-07-09
Classification: G01R

Abstract:
A reduced pin full scan integrated circuit (IC) testing system comprising:a functional logic component adapted to perform functional operations; a plurality of scan chains coupled to said functional logic component, said plurality of scan chains adapted to scan test said functional logic component; a controller coupled to said plurality of scan chains, said controller adapted to receive scan test signals and provide scan operation signals to said plurality of scan chains; a set of scan test pins coupled to said controller, said set of scan test pins adapted to receive scan test signals; a multiplexer (MUX) coupled to said controller, said MUX adapted to select between a clock domain provided by said controller and a second clock domain; and a phase lock loop (PLL)/clock generator coupled to said MUX, said PLL/clock generator adapted to provide said second clock domain to said plurality of scan chains.