Patent ID: 7385857
Filing Date: 2008-06-10
Classification: G11C

Abstract:
1. A method for preventing oversaturation in a first and second tri-gate structure in a non-volatile SRAM cell, said non-volatile SRAM having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said method comprising: a) measuring a threshold erase voltage for each SONOS transistor in said cell when applying an erase voltage said each SONOS transistor; b) generating a saturated erase condition voltage for each SONOS transistor in said cell by performing a plurality of erase procedures in succession; c) calculating a delta value for the difference between said threshold erase voltage and said saturated erase condition voltage; d) determining if said delta value is within a specified range; e) modifying said erase voltage if said delta value is outside said range and thereafter repeating said steps a) through d) of said method until said delta is within said specified range; and f) storing said erase voltage if said delta value is within said specified range.