Patent ID: 9159695
Filing Date: 2015-10-13
Classification: H01L

Abstract:
1. A package structure, comprising: a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar, wherein L is different from W, wherein the bump structure further comprises an under bump metallurgy layer; and a substrate comprising a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region, wherein the conductive pillar of the chip is attached to the pad region of the substrate via a solder joint region to form an interconnection between the conductive pillar and the pad region, wherein the solder joint region contacts a center of a major top surface of the conductive pillar along the long axis of the conductive pillar, wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis; and wherein L is greater than d1, and W is less than d2.