Patent ID: 8704383
Filing Date: 2014-04-22
Classification: H01L

Abstract:
1. A semiconductor package assembly comprising: a semiconductor chip comprising at least one low-k dielectric layer having a k value of less than about 3.0; a silicon-based package substrate having a thickness of less than about 200 μm; a package substrate having a first surface and a second surface, the first surface of the package substrate being attached directly to a first surface of the silicon-based package substrate, the semiconductor chip being disposed over a second surface of the silicon-based package substrate; a plurality of solder bumps interposed between the semiconductor chip and the second surface of the silicon-based package substrate; a plurality of under bump metallizations formed on the second surface of the silicon-based package substrate disposed to receive the plurality of solder bumps; a plurality of wire bond lands overlying the second surface of the silicon-based package substrate; a plurality of conductive traces disposed on the silicon-based package substrate each having a horizontal portion and each coupling at least one of the under bump metallizations to at least one of the wire bond lands; and at least one bond wire connection electrically coupling one of the wire bond lands to a conductive land on the first surface of the package substrate.