Patent ID: 8102632
Filing Date: 2012-01-24
Classification: H03K

Abstract:
1. A circuit for protecting low voltage devices within an integrated circuit (IC) from an electrostatic discharge (ESD) event, comprising: a high voltage input/output (IO) pin associated with a high voltage level; a low voltage IO pin associated with a low voltage level; a voltage drop network coupled to the high voltage IO pin and comprising a plurality of forward-biased diodes connected in series to drop the high voltage level on the high voltage IO pin to the low voltage level; and a first shunt circuit coupled to the high voltage IO pin via the voltage drop network and a second shunt circuit coupled to the low voltage IO pin, the first and second shunt circuits being configured to operate in tandem during the ESD event; each shunt circuit having an NMOS shunt transistor coupled between the voltage drop network and a ground terminal and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.