Patent ID: 8364907
Filing Date: 2013-01-29
Classification: G06F

Abstract:
1. A processor comprising: a data cache; and an interface unit comprising a memory request buffer coupled to receive a victim block evicted by the data cache to be written back to memory, wherein the interface unit is configured to convert the victim block writeback into a cache fill for the data cache responsive to detecting at least one store memory operation issued by the processor to write data to the victim block, wherein the at least one store memory operation is already in the memory request buffer upon receipt of the victim block at the memory request buffer, and wherein the interface unit is configured to merge the victim block data into the store data already stored in the memory request buffer and corresponding to the at least one store memory operation, wherein a result of the merge is the victim block data updated with the store data, and wherein the memory request buffer is further coupled to receive an additional cache fill request corresponding to a load memory operation that missed in the data cache, wherein the memory request buffer is configured to store the additional cache fill request awaiting transmission to memory to read data from the memory, and wherein the interface unit is configured to return a second cache fill corresponding to the additional cache fill request to the data cache in response to receiving the data corresponding to the additional cache fill request from memory.