Patent ID: 8236662
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: forming at least one pad layer over an active semiconductor area; forming an opening in said at least one pad layer to expose said active semiconductor area; depositing an intrinsic base layer directly on said active semiconductor area and over said at least one pad layer; forming a pedestal etch stop layer on said intrinsic base layer; forming at least one emitter pedestal layer on said pedestal etch stop layer; forming an emitter pedestal directly on said intrinsic base layer; removing portions of said pedestal etch stop layer that are not covered by said emitter pedestal; selectively depositing an extrinsic base layer on exposed portions of said intrinsic base layer and over said at least one pad layer after formation of said emitter pedestal, wherein a semiconductor material of said extrinsic base layer does not grow from surfaces of said emitter pedestal; and forming a mesa structure with substantially planar and vertical sidewall surfaces, wherein each of said substantially planar and vertical sidewall surfaces contains a surface of said at least one pad layer, a surface of said intrinsic base layer, and a surface of said extrinsic base layer.