Patent ID: 8791552
Filing Date: 2014-07-29
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, the memory cell including a variable resistance element that is electrically rewritable by applying an electric signal having a different polarity and a current control element connected in series and passing currents in both directions through the variable resistance element, the current control element including: a first conductivity-type semiconductor into which a first impurity is doped; an i-type semiconductor in contact with the first conductivity-type semiconductor; a second conductivity-type semiconductor into which a second impurity is doped, and the second conductivity-type semiconductor being in contact with the i-type semiconductor opposite to the first conductivity-type semiconductor; and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor, the impact ionization acceleration unit generating more impact ions than between the i-type semiconductor and the other of the first conductivity-type semiconductor and the second conductivity-type semiconductor, wherein a diffusion length of the second impurity in the second conductivity-type semiconductor is longer than a length of the i-type semiconductor in a direction where the i-type semiconductor and the second conductivity-type semiconductor are arranged, and the impact ionization acceleration unit is formed in a junction portion between the first conductivity-type semiconductor and the i-type semiconductor.