Patent ID: 7115977
Filing Date: 2006-10-03
Classification: H01L

Abstract:
1. A multi-chip package type semiconductor device, comprising: an insulating substrate having thereon a first conductive pattern and a second conductive pattern; a first semiconductor chip having a plurality of first internal circuits on the insulating substrate, the first semiconductor chip having a plurality of first terminal pads, each of which is connected to one of the first internal circuits and a plurality of conductive relay pads, each of which is isolated from the first terminal pads, and each of the conductive relay pads including a first area and a second area; which is different from the first area, wherein each first terminal pad and each conductive relay pad are alternatively aligned; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip being smaller than the first semiconductor chip, and having a second internal circuit and having a second terminal pad connecting to the second internal circuit; a plurality of first metal bumps, each of which is formed on one of the conductive relay pads in the first area; a second metal bump formed on the second terminal pad; a first bonding wire, wherein one end thereof is formed on one of the first terminal pads and the other end is formed on the first conductive pattern; a second bonding wire, wherein one end thereof is formed on the second conductive pattern and the other end is formed at the top of the first metal bump on one of the conductive relay pads in the first area; and a third bonding wire, wherein one end thereof is formed on the one of the conductive relay pads in the second area and the other end is formed at the top of the second metal bump, wherein the lengths of the first, second and third bonding wire are approximately the same.