Patent ID: 6778526
Filing Date: 2004-08-17
Classification: H04L

Abstract:
A high speed interface for fast path processing of a plurality of data packets comprising:a master port for uni-directionally transferring the data packets; a slave port for uni-directionally receiving the data packets; and a bus infrastructure configured to accommodate the uni-directional transfer of the data packets, said master port and said slave port being coupled to said bus infrastructure; wherein said master port includes a source for generating synchronization signals, a first source generating a first identification signal indicating the beginning of each data packet, and a second source generating a second identification signal indicating the completion of each data packet, said first identification signal and said second identification signal each having one of said synchronization signals assigned thereto; wherein said slave port includes a receiver for receiving said synchronization signals, said first identification signal and said second identification signal, said synchronization signals confirming the receipt of each data packet via identifying the beginning and the completion of each data packet; and wherein said master port transfers the data packets to the slave port across the bus infrastructure at a rate of about 10 gigabits per second.