Patent ID: 7899144
Filing Date: 2011-03-01
Classification: H04L

Abstract:
1. A semiconductor integrated circuit device comprising: a clock signal generating circuit inputting a first phase comparison signal and generating a clock signal with a phase corrected based on the first phase comparison signal; a first circuit outputting the first phase comparison signal indicating whether the phase of the clock signal is appropriate with respect to a phase of an input data signal by phase comparison between the input data signal and the clock signal and outputting a first recovered data signal by latching the input data signal by the clock signal; wherein the first circuit comprises: a second circuit latching the input data signal by the clock signal using a plurality of thresholds different from each other as logic determination references and outputting a first candidate comprised of a second recovered data signal and a second phase comparison signal and a second candidate comprised of a third recovered data signal and a third phase comparison signal by processing a latch result; a third circuit receiving the output of the second circuit, selecting one of the first candidate and the second candidate and outputting the selected one as the first recovered data signal and the first phase comparison signal, and wherein the third circuit performs the operation of selecting one of the first candidate and the second candidate at a focused data cycle based on a symbol of the first recovered data signal at a previous data cycle.