Patent ID: 6400612
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A memory comprising:a two-dimensional array of data storage cells organized as a plurality of rows and columns, each data storage cell having first, second, third, and fourth terminals, each data storage cell sinking a current between said first and second terminals indicative of a charge stored therein when said third terminal is at said first potential; a plurality of bit lines, one corresponding to each column, said first terminal of each data storage cell in each column being connected to said bit line corresponding to that column when said third terminal is at said first potential and each data storage cell being disconnected from that bit line when said third terminal is at a second potential; a plurality of column select lines, one corresponding to each column and one additional column select line adjacent to either said first or last column, said fourth terminal of each data storage cell in each column being connected to said column select line corresponding to that column; and a plurality of row select lines, one corresponding to each row, said third terminal of each data storage cell in each row being connected to said row select line corresponding to that row, wherein said second terminal of each data storage cell in each column is connected to said column select line of an adjacent column.