Patent ID: 8892929
Filing Date: 2014-11-18
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a plurality of cores; and an uncore including at least one shared cache memory, a plurality of logic units including a memory controller, a router, and a power control unit (PCU), wherein the PCU is to clock gate at least one of the plurality of logic units and the at least one shared cache memory when the processor is in a low power state, after a plurality of time periods have occurred in which the plurality of logic units were persistently empty of transactions and no in-flight transactions were present in the plurality of logic units, the PCU including a plurality of timers each to track a different time period and the clock gate is to occur if the uncore has been persistently empty for at least each of the different time periods and prevent incoming transactions from one or more off-socket channels, wherein the uncore is to determine whether the plurality of logic units were persistently empty for a first time period and prevent transactions from an out-of-band (OOB) channel and determine whether the plurality of logic units were persistently empty for a second time period.