Patent ID: 8586990
Filing Date: 2013-11-19
Classification: H01L

Abstract:
1. A thin film transistor (TFT) array substrate, comprising; a gate interconnection line comprising a gate line, a gate electrode, and a gate pad arranged on an insulating substrate; a gate insulating layer arranged on the gate interconnection line; a semiconductor layer arranged on the gate insulating layer; a data interconnection line comprising a data line, a source electrode, and a drain electrode arranged on the semiconductor layer; a second passivation layer arranged on the first passivation layer and comprising silicon nitride; a third passivation layer arranged on the second passivation layer and comprising silicon nitride; and a pixel electrode electrically connected to the drain electrode through the first contact hole, and formed on the first passivation layer; and wherein the pixel electrode is formed at least partially by removing the second passivation layer and the third passivation layer from the insulating substrate, and wherein the second passivation layer is formed at a first temperature and comprises an undercut, and the third passivation layer is formed at a second temperature that is higher than the first temperature.