Patent ID: 6806128
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:(a) forming a gate electrode over a substrate; (b) implanting ions of a first n-type impurity in the substrate at both ends of said gate electrode, thereby forming source/drain extended regions; (c) forming side wall spacers on the side walls of said gate electrode; (d) implanting ions of a second n-type impurity in said substrate in self alignment with said gate electrode and said side wail spacers, to form source/drain diffused regions comprising a higher impurity concentration than said source/drain extended regions; (e) cleaning said substrate; and (f) depositing a refractory metal film over said substrate, and forming a silicide layer on a surface of said source/drain diffused regions by heat treatment, wherein said method further comprises, after said step (c), a step of implanting ions of a third n-type impurity into said substrate in self alignment with said gate electrode and said side wall spacers, to form a semiconductor region comprising a higher impurity concentration than said source/drain extended regions, and wherein said source/drain extended regions, said semiconductor region, said silicide layer, and said source/drain diffused regions are arranged in the order of mention from a channel region toward the end portion of said side wall spacers in the substrate.