Patent ID: 7189644
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A method for forming a low resistance MOSFET device comprising: forming a gate region atop a surface of a substrate; subsequently, forming source and drain extension regions in the substrate, wherein a channel region is formed between said source and drain extension regions in the substrate; subsequently, forming first spacers each having a first spacer width on sidewalls of said gate region; subsequently, forming source and drain regions in the substrate abutting the source and drain extension regions, respectively; subsequently, forming first silicide regions each having a first vertical silicide thickness in said substrate, wherein the first vertical silicide thickness from about 2 to about 15 nm; subsequently, forming second spacers atop said substrate each having a second spacer width along sidewalls of the first spacers, wherein said second spacers protect said first silicide regions in said substrate; and subsequently, forming second silicide regions in said substrate, wherein said second silicide regions each have a second vertical silicide thickness that is greater than said first vertical silicide thickness.