Patent ID: 6191025
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of fabricating a conductor in an integrated circuit, comprising:providing a silicon substrate;depositing a layer of first dielectric on said silicon substrate;depositing a layer of second dielectric on said layer of first dielectric;depositing a layer of third dielectric on said layer of second dielectric, wherein said layer of third dielectric is a sacrificial layer;removing a part of said layer of third dielectric down to a level between the top of said layer of second dielectric and the top of said layer of third dielectric, using a first removal means, thereby planarizing said substrate;depositing a layer of fourth dielectric on said layer of third dielectric after planarizing said substrate;patterning and etching said layer of fourth dielectric, using an etching means chosen so that said layer of second dielectric acts as an etch stop, thereby forming a trench;depositing a layer of barrier metal on said top surface of said layer of fourth dielectric, the bottom of said trench, and all sidewalls of said trench;depositing a layer of conductor metal on said layer of barrier metal so as to more than fill said trench; andremoving said conductor metal and said barrier metal down to the level of said fourth dielectric layer, using a second removal means, thereby forming a damascene conductor.