Patent ID: 6287911
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A fabrication method of a semiconductor device, comprising the steps of:(a) defining a first section and a second section on a main surface of a semiconductor substrate;(b) forming a first gate insulating layer on said main surface of said substrate in said first section and a second gate insulating layer on said main surface of said substrate in said second section;(c) forming a conductive layer on said first and second gate insulating layers to cover said first and second sections;(d) patterning said conductive layer in said first section, thereby forming a first gate electrode on said first gate insulating layer in said first section without forming any gate electrode in said second section;(e) forming a first pair of source/drain regions in said first section at each side of said first gate electrode, thereby constituting a first MOSFET in said first section;(f) selectively forming a dielectric masking layer to cover said first section while uncovering said second section;(g) patterning said remaining conductive layer in said second section while masking said first section by said masking layer, thereby forming a second gate electrode on said second gate insulating layer in said second section;(h) forming a second pair of source/drain regions in said second section at each side of said second gate electrode, thereby constituting a second MOSFET in said second section;(i) forming a refractory metal layer to cover said first and second sections in such a way that said refractory metal layer is contacted with said second pair of source/drain regions in said second section; and(j) heat-treating said substrate with said refractory metal layer to form a pair of silicide layers on said second pair of source/drain regions in said second section due to silicidation reaction of said refractory metal with said second pair of source/drain regions.