Patent ID: 8642418
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than the first n-type MISFET, and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than the first p-type MISFET, comprising steps of: (a) forming a gate insulating film of the first n-type MISFET over the first region, forming a gate insulating film of the first p-type MISFET over the second region, forming a gate insulating film of the second n-type MISFET over the third region, and forming a gate insulating film of the second p-type MISFET over the fourth region; (b) forming a first gate electrode over the gate insulating film of the first n-type MISFET, forming a second gate electrode over the gate insulating film of the first p-type MISFET, forming a third gate electrode over the gate insulating film of the second n-type MISFET, and forming a fourth gate electrode over the gate insulating film of the second p-type MISFET; (c) after the step (b), under a condition which a first resist pattern covers the first, second and fourth regions, forming third n-type impurity regions in the third region by ion implantation method; (d) after the step (b), under a condition which a second resist pattern covers the first, second and third regions, forming third p-type impurity regions in the fourth region by ion implantation method; (e) after the steps (c) and (d), forming first insulating films over side surfaces of the first, second, third and fourth gate electrodes; (f) after the step (e), under a condition which a third resist pattern covers the second, third and fourth regions, forming first n-type impurity regions in the first region by ion implantation method; (g) after the step (f), forming second insulating films over the side surfaces of the first, second, third and fourth gate electrodes via the first insulating films; (h) after the step (g), under a condition which a fourth resist pattern covers the first, third and fourth regions, forming first p-type impurity regions in the second region by ion implantation method; (i) after the step (h), forming third insulating films over the side surfaces of the first, second, third and fourth gate electrodes via the first and second insulating films, wherein a thickness of each the third insulating films is thicker than a thickness of each the first and second insulating films; (j) after the step, (i), under a condition which a fifth resist pattern covers the second and fourth regions, forming second n-type impurity regions in the first region and forming fourth n-type impurity regions in the third region by ion implantation method, wherein an impurity concentration of each the second n-type impurity regions is higher than an impurity concentration of each the first n-type impurity regions, and wherein an impurity concentration of each the third n-type impurity regions is higher than an impurity concentration of each the fourth n-type impurity regions; and (k) after the step (i), under a condition which a sixth resist pattern covers the first and third regions, forming second p-type impurity regions in the second region and forming fourth p-type impurity regions in the fourth region by ion implantation method, wherein an impurity concentration of each the second p-type impurity regions is higher than an impurity concentration of each the first p-type impurity region, and wherein an impurity concentration of each the third p-type impurity regions is higher than an impurity concentration of each the fourth p-type impurity regions.