Patent ID: 6260185
Filing Date: 2001-07-10
Classification: G06F,H03K

Abstract:
A method of designing a logic circuit to be integrated on semiconductor, as implemented by using a designing device comprising a central processing unit, a memory device and a man-machine interface device, characterized in that a program stored in the memory device executes the following steps of:(a) having logic functions being inputted which are for determining logic relationship between logic inputs and logic outputs and a target specification of delay times between the logic inputs and the logic outputs;(b) forming a binary decision diagram as defined in the following paragraph (b-1) for at least part of the logic functions as inputted;(b-1) the binary decision diagram being one formed by combining a plurality of nodes each having a control variable, two input edges and one output, wherein the control variable of each node represents a logic input to a relevant logic portion, either one of the two input edges of each node is selected according a logical value of the control variable, and a signal applied to the selected input edge is transferred to the output of the node;(c) determining a pass-transistor logic circuit which includes a plurality of pass-transistor circuits each corresponding to one of at least part of a plurality of nodes in the binary decision diagram formed in the step (b), each pass transistor circuit being one defined in the following paragraph (c-1);(c-1) the pass transistor circuit comprising a control input, a first input, a second input, an output, a first field effect transistor having a source-drain path connected between the first input and the output, and a second field effect transistor having a source-drain path connected between the second input and the output, wherein a gate of the first field effect transistor responds to a signal applied to the control input, a gate of the second field effect transistor responds to an inverted signal of the signal applied to the control input, and a signal of either one of the first input and the second input is transferred to the output;(d) checking whether simulated delay time of the pass-transistor logic circuit obtained in the step (c) meets the target specification given in the step (a), and executing the following steps (e), (f) and (g), if the target specification is not met;(e) replacing at least one partial diagram which includes plural nodes, in the binary decision diagram, with one replacing node and a group of nodes which provide a control variable to said one node, said one node and said group of nodes satisfying conditions indicated in the following paragraphs (e-1) and (e-2);(e-1) a group of diagram elements connected to tips of input edges of the replacing node, of the binary decision diagram after the replacing coinciding with a group of diagram elements connected to tips of input edges of said plural nodes included in said one partial diagram to be replaced, of the binary decision diagram before the replacing and located outside of said one partial diagram to be replaced;(e-2) the control variable of the replacing node in the diagram after the replacing being able to be expressed by logical combination of plural control variables of said plural nodes included in said one partial diagram in the binary decision diagram before the replacing, so that a logic function of the binary decision diagram after the replacing is identical to a logic function of the binary decision diagram before the replacing;(f) determining another pass-transistor logic circuit corresponding to said binary decision diagram after said replacing, said another pass-transistor logic circuit including a plurality of pass-transistor circuits each corresponding to one of at least part of nodes in the binary decision diagram after the replacing each pass transistor circuit being one defined in the paragraph (c-1), said another pass-transistor logic circuit adopting the following signal supplying schemes;a first signal supplying scheme being adopted between first and second pass-transistor circuits, according to which first signal supplying scheme an input signal applied to a control input of one pass transistor circuit is a signal of an output of other pass transistor circuit, a second signal supplying scheme being adopted between the second pass-transistor circuit and a third pass-transistor circuit, according to which second signal supplying scheme an input signal applied to either one of the first input and the second input of one pass-transistor circuit is a signal of an output of other pass transistor circuit,said first pass-transistor circuit being one corresponding to one of said group of nodes within said binary decision diagram after said replacing which supplies a control variable to said one replacing node, said second pass-transistor circuit being one corresponding to said one replacing node, said third pass-transistor circuit being one corresponding to a node connected to one of two input edges of said one replacing node; and(g) checking whether simulated delay time of said another pass-transistor circuit meets the target specification.