Patent ID: 6968400
Filing Date: 2005-11-22
Classification: G06F,Y02D

Abstract:
1. A digital system comprising: at least a first processor having an address space; a local memory connected to the first processor and occupying a portion of the address space of the processor, the local memory operable to respond to transfer requests from the first processor, the local memory comprising a data array arranged as a plurality of segments and a plurality of valid bits operable to indicate that a corresponding segment contains valid data, wherein each of the plurality of segments has a corresponding indicator bit within the plurality of valid bits; and direct memory access (DMA) circuitry connected to the local memory, the DMA circuitry operable to transfer data to a selectable portion of segments of the plurality of segments from a selectable region of a second memory and operable to set, to a valid state, a selected portion of valid bits of the plurality of valid bits corresponding to the selectable portion of segments; and miss detection circuitry connected to the plurality of valid bits, the miss detection circuitry having a miss signal for indicating when a miss is detected in response to a request from the first processor to a first segment; wherein the processor stalls in response to the miss signal until the DMA circuitry sets a first valid bit corresponding to the first segment to a valid state.