Patent ID: 6756813
Filing Date: 2004-06-29
Classification: G11C,H03K

Abstract:
A voltage translator which is connected to a first operating voltage source and a second operating voltage source, and supplies a positive first operating voltage from said first operating voltage source or supplies a second operating voltage lower than an earth potential from said second operating voltage source to a wordline depending on an output signal of a decoder, comprising:a first PMOS transistor which has a first main electrode connected to said first operating voltage source and a second main electrode connected to said wordline; a first NMOS transistor which has a first main electrode connected to said second operating voltage source and a second main electrode connected to said wordline; a second PMOS transistor which has a first main electrode connected to said first operating voltage source, a second main electrode connected to a control electrode of said first PMOS transistor, and a control electrode connected to said wordline; a second NMOS transistor which has a first main electrode connected to said second operating voltage source, a second main electrode connected to a control electrode of said first NMOS transistor, and a control electrode connected to said wordline; a third NMOS transistor which has a first main electrode coupled to the earth potential, a second main electrode connected to the control electrode of said first PMOS transistor, and a control electrode which receives the output signal of said decoder; a third PMOS transistor which has a first main electrode connected to a logical control voltage source, a second main electrode connected to the control electrode of said first NMOS transistor, and a control electrode which receives the output signal of said decoder; an inverter which has an input terminal which receives the output signal of said decoder; a fourth NMOS transistor which has a first main electrode connected to the control electrode of said first PMOS transistor, a second main electrode connected to an output terminal of said inverter, and a control electrode connected to said wordline; and a fourth PMOS transistor which has a first main electrode connected to the control electrode of said first NMOS transistor, a second main electrode connected to the output terminal of said inverter, and a control electrode connected to said wordline.