Patent ID: 6578128
Filing Date: 2003-06-10
Classification: G06F

Abstract:
A system, comprising:a memory having a plurality of contiguous processor memory regions; a plurality of processors, each one of such processors being associated with a corresponding one of the processor memory regions; wherein: each one of such processors provides a plurality of sets of successive processor addresses; the addresses in each one of such sets having a successive series of used addresses and a successive series of reserve addresses, the last used address in each one of the sets being separated from the first used address in the next successive set of addresses by a gap of addresses, G; each one of the used addresses in the sets of processor addresses corresponding to one of the processor memory regions; the addresses provided by each one of the processors for the set of processor addresses corresponding to the same processor memory region being different; a plurality of personal address translators, each one being fed by a corresponding one of the processors, the translators mapping the processor addresses fed thereto to virtual addresses, wherein: such virtual addresses have a plurality of sets of virtual address regions; each virtual address region corresponding to one of the processor memory regions, and wherein: the personal translators map the set of processor addresses corresponding to the same processor memory region to the corresponding one of the sets of virtual address regions; a common address translator fed by the virtual addresses, for mapping the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.