Patent ID: 7490279
Filing Date: 2009-02-10
Classification: G11C

Abstract:
1. A built-in self-test (BIST) system formed as part of an integrated circuit for testing memory circuitry formed as part of the integrated circuit, the memory circuitry including a plurality of memory storage cells, each memory cell including a specified number of storage bits and having a specified address associated therewith, the BIST system comprising: (a) a test interface shift register having the same specified number of storage bits as said memory storage cells; (b) a BIST controller that generates write enable signals and read enable signals, the BIST controller including (c) a comparator, the memory circuitry being responsive to a read enable signal generated by the BIST controller for providing the contents of the specified memory storage cell to the comparator, the comparator comparing the contents of the specified memory storage cell and the test pattern provided to the specified memory storage cell by the test interface shift register, the comparator generating a pass signal if the contents of the specified memory storage cell matches the test pattern.