Patent ID: 7315471
Filing Date: 2008-01-01
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array configured by arranging a plurality of memory cells in a matrix, each of which is capable of having one of a 2 a plurality of bit lines, each of which is connected to said plurality of memory cells arranged in the column direction; a plurality of word lines, each of which is connected to said plurality of memory cells arranged in the row direction; an n number of flag cells which are selected at the same time when the memory cells are selected by each of the word lines; and a control section which, when writing the data in a k-th page (2<k<n) composed of a k number of bits into the memory cells selected by the word line, writes specific data into a k number (2<k<=n) of the flag cells and which, when reading the data in an i-th page (i<=n) from the memory cells, determines from the data read from the i-th flag cell whether the k-th page has been written into the memory cells.