Patent ID: 7055084
Filing Date: 2006-05-30
Classification: H04L

Abstract:
1. A method for regulating a threshold and a relative phase of a sampling clock signal with respect to a phase of a binary signal by evaluation of error correction signals, wherein the threshold is associated with an optimum ratio, the method comprising the steps of: evaluating both a number of 1-bits detected as erroneous and a number of 0-bits detected as erroneous; adjusting the threshold according to the evaluating step to achieve the optimum ratio of the number of 1-bits detected as erroneous and the number of 0-bits detected as erroneous; evaluating a number of bits detected as erroneous before a transition between binary states and a number of bits detected as erroneous after a transition between the binary states; and adjusting the phase of the sampling clock signal such that the number of bits detected as erroneous before and after the transition between the binary states are substantially the same.