Patent ID: 8937299
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A fin field effect transistor, comprising: a substrate formed from a monocrystalline silicon or germanium material; a dielectric layer having trenches formed therein, the dielectric layer having a lower surface present on a first portion of an upper surface of the substrate; an etch stop layer atop the dielectric layer; a plurality of parallel fins formed from a III-V material in the trenches and being in contact with a second portion of the upper surface of the substrate that is adjacent and coplanar with the first portion of the upper surface of the substrate, the trenches being initially dimensioned and configured to have a high aspect ratio including a height to width ratio of greater than about 1:1 to enable non-lattice-matched crystalline III-V material to be formed on the substrate, wherein the high aspect ratio trenches provide that the III-V semiconductor is in direct contact with the silicon substrate and is a monocrystalline structure that is relatively defect free, a doped portion of the plurality of parallel fins being positioned above an upper surface of the etch stop layer and an undoped portion of the plurality of parallel fins being positioned below the etch stop layer; a gate stack including a barrier layer, a gate dielectric and a gate conductor formed transversely to the plurality of parallel fins, wherein the barrier layer is present on a sidewall and upper surface of the doped portion of the plurality of parallel fins; and raised source and drain regions formed from a III-V material and being in contact with the fins on opposite sides of the gate stack.