Patent ID: 6067249
Filing Date: 2000-05-23
Classification: G11C

Abstract:
A layout of a flash memory, comprising:a plurality of memory cells each having a cell transistor having a cell gate electrode having a floating gate and a control gate, and a source/drain electrode for thereby storing and erasing a data;a selection transistor having two gate electrodes, a common drain electrode between the gate electrodes and a source electrode formed outside the same and having a predetermined channel width larger than two times compared to the channel width of the cell transistor, and the drain electrode and source electrodes which are crossingly formed to each other with respect to the axis of the word lines through which a driving voltage is applied to the gate electrodes for thereby selecting a corresponding memory cell;a pair of cell bit lines connected with the source electrode of the selection transistor and connected in parallel with the drain electrode of the memory cell transistor for inputting/outputting the data to the cell transistor; anda pair of array bit lines connected with a drain electrode of the selection transistor and a peripheral circuit, whereby the selection transistor selecting a first cell transistor among the memory cells is connected with a first cell bit line among a pair of the cell bit lines through the source electrode, and is connected with the second array bit line among a pair of the array bit lines through the drain electrode, and another selection transistor selecting the second cell transistor is connected with the second cell bit line through the source electrode and is connected with the first array bit line through the drain electrode.