Patent ID: 6259652
Filing Date: 2001-07-10
Classification: G11C

Abstract:
A synchronous integrated memory, comprising:memory cells;a FIFO memory connected to said memory cells, said FIFO memory having at least two memory stages each for simultaneously buffer-storing two data items read from said memory cells;each of said memory stages having a first output for outputting a respective buffer-stored first data item and a second output for simultaneously outputting a respective buffer-stored second data item;a first output unit having an input connected to said first output of each of said memory stages of said FIFO memory and a data output outputting the first data item respectively received from said memory stages in dependence on a first clock signal; anda second output unit having an input. connected to said second output of each of said memory stages of said FIFO memory, a register for buffer-storing the second data item respectively received from said FIFO memory, and a data output for subsequently outputting said second data item in dependence on a second clock signal.