Patent ID: 6301636
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A system comprising a common bus and a plurality of content addressable memory (CAM) chips which are cascaded and connected to the common bus, each of the CAM chips comprising:a CAM array including:(i) encoding means; and(ii) an array of core cells, of w words.times.b bits, associated with the encoding means, each of the core cells comprising data storage means, the core cells of each word being associated with a respective match line, the CAM array of each of the CAM chips being able to provide, through that encoding means, hit and match address signals resulting from a search operation on that CAM chip in response to a clock signal;timing signal means for generating a self-timed signal in response to the clock signal;hit propagation means for providing a propagation-out hit signal to a downstream CAM chip in response to the self-timed signal; andmatch address transfer means for transferring the match address signal resulting from the search operation on that CAM chip to the common bus in response to the self-timed signal, wherein the hit propagation means of each of the CAM chips comprises a first logic circuit for responding to the self-timed signal provided from the timing signal means of that CAM chip, the hit signal provided from the CAM array of that CAM chip and a propagation-in hit signal provided from an upstream CAM chip.