Patent ID: 7541625
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising a real pattern group including a plurality of wiring patterns for providing connection either between a pair of circuits, between a pair of elements or between a circuit and an element, the real pattern group being formed in each of a plurality of wiring layers, and a plurality of dummy patterns formed in a region of each said wiring layer in which the real pattern group is not placed, wherein, when the direction of extension of one of the plurality of wiring patterns is used as a reference direction, the plurality of dummy patterns extend in a direction forming an angle of 45 degrees with respect to the reference direction, and the plurality of dummy patterns include a potential-fixed dummy pattern connected to a fixed potential and floating dummy patterns prevented from being connected to a fixed potential, some of the floating dummy patterns are located adjacent to the associated wiring patterns, and one of the dummy patterns adjacent to said some of the floating dummy patterns located adjacent to the associated wiring patterns is the potential-fixed dummy pattern.