Patent ID: 6472919
Filing Date: 2002-10-29
Classification: H03K

Abstract:
A latch, said latch comprising:an input line; a first node coupled to said input line; a first pass gate coupled to said first node; a second node coupled to said first pass gate such that said first pass gate is coupled between said first node and said second node; a first inverter having an input coupled to said second node, said first inverter comprising transistors, said first inverter having an output; a feedback stage having an input node coupled to said output of said first inverter and an output node coupled to said second node, said feedback stage comprising: a first transistor comprising a first flow electrode, a second flow electrode and a control electrode, said first transistor control electrode being coupled to said feedback stage input node; a second transistor comprising a first flow electrode, a second flow electrode and a control electrode, said second transistor control electrode being coupled to said feedback stage input node and said first transistor control electrode, said second transistor first flow electrode being coupled to said second flow electrode of said first transistor; a third transistor comprising a first flow electrode, a second flow electrode and a control electrode, said third transistor second flow electrode being coupled to said first transistor second flow electrode and said second transistor first flow electrodes; a fourth transistor comprising a first flow electrode, a second flow electrode and a control electrode, said fourth transistor first flow electrode being couple to said first transistor second flow electrode said second transistor first flow, electrode and said third transistor second flow electrode a feedback pass gate coupled between said first transistor second flow electrode and said second transistor first flow electrode; wherein each of said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage has approximately the same channel length and approximately the same channel width as all other transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage, further wherein; a stack height of said transistors of said feedback stage is equal to a stack height of said transistors of said feedback pass gate; further wherein; said transistors of said first inverter and said first, second, third and fourth transistors of said feedback stage are low threshold transistors.