Patent ID: 8378423
Filing Date: 2013-02-19
Classification: H01L

Abstract:
1. A dual-gate transistor, comprising: a substrate; a bottom gate formed on the substrate; a first dielectric layer covering the bottom gate and the substrate; a semiconductor layer formed on the first dielectric layer over the bottom gate; first and second electrodes formed on the semiconductor layer and spaced from each other with an interval therebetween; a second dielectric layer formed on the substrate so as to cover the first electrode, the second electrode and portion of the semiconductor layer; and a top gate formed on the second dielectric layer, wherein both the top gate and the bottom gate have two opposite end sections, one end section of the top gate is overlapped with the first electrode and another end section of the top gate is non-overlapped with the second electrode, and the two opposite end sections of the bottom gate are overlapped with the first and second electrodes respectively.