Patent ID: 8558582
Filing Date: 2013-10-15
Classification: G11C,H02P,H03M

Abstract:
1. A packaged controller comprising: a first die comprising an analog-to-digital converter (ADC), a first serial bus interface, and a sequencer, wherein the sequencer is coupled to supply a start convert signal to the ADC; a second die comprising a second serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer, wherein the ADC is coupled to receive an analog signal from the second die, wherein the analog multiplexer couples an output lead of a selected one of the sample/hold circuits to the ADC, wherein a serial bus clock signal is communicated from the first serial bus interface to the second serial bus interface, wherein in response to a trigger signal being asserted within the first die the sequencer causes a multi-bit value to be communicated from the first serial bus interface to the second serial bus interface, wherein the multi-bit value determines which one of the sample/hold circuits is coupled through the analog multiplexer to the ADC, and wherein a latency period between a time when the trigger signal is asserted and a time when a sample/hold signal that is supplied to the plurality of sample/hold circuits is asserted is less than eight periods of the serial bus clock signal; and a package that contains the first die and the second die.