Patent ID: 7099179
Filing Date: 2006-08-29
Classification: G11C,H01L

Abstract:
1. A re-writable memory, comprising: a substrate; a two-terminal cross point memory array formed above the substrate and including: driver circuits, each driver circuit in electrical communication with the cross point array and operable to deliver the first voltage during a first cycle to a first group of memory plugs, and the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and address circuits in electrical communication with the driver circuits and configured to receive binary information and an address signal, the address circuits further configured to distribute the binary information to decoder circuits according to the address signal, so as to facilitate writing of the received binary information to the two-terminal memory plugs in page mode.