Patent ID: 6154511
Filing Date: 2000-11-28
Classification: H03L,H04L

Abstract:
A clock extraction method for receiving non-return-to-zero signals for signal regeneration whereina signal obtained by frequency-dividing received non-return-to-zero signals by m, where m is a pre-set integer, and then detecting edges of the frequency-divided signal, anda signal obtained by frequency-dividing a signal generated by a voltage-controlled oscillator at a frequency substantially equal to a transmission rate of the received non-return-to zero signals by n, where n is a pre-set integer,are phase-compared to each other to produce a phase error signal to extract synchronized clock signals, andproviding an absolute value of the phase error signal, wherein the signal obtained by frequency dividing the signal generated by the voltage-controlled oscillator produces a divided frequency signal wherein a falling edge of the divided frequency signal should sometimes be detected for a correct phase error, and providing an absolute value of the phase error signal compensates for the phase comparison with the divided frequency signal.