Patent ID: 7035137
Filing Date: 2006-04-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: word lines formed along a first direction; bit lines formed along a second direction which intersects the first direction; memory cells including magneto-resistive elements and arranged at intersections of the word lines and the bit lines; a row decoder which selects at least one of the word lines; a column decoder which selects at least one of the bit lines; and a write circuit which supplies first and second write currents to a selected word line and selected bit line selected by the row decoder and column decoder respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line, the write circuit including first and second current sources whose supply currents have different temperature dependencies, the first and second current sources being set to be one of an enable state and a disable state in accordance with an ambient temperature, at least one of current values of the first and second write currents being controlled in accordance with the supply currents of the first and second current sources.