Patent ID: 7760279
Filing Date: 2010-07-20
Classification: G02F

Abstract:
1. A panel, comprising: a first substrate; a gate line formed on the first substrate; a gate insulating layer covering the gate line; a semiconductor layer formed on the gate insulating layer; a data line intersecting the gate line and including a source electrode formed on the semiconductor layer; a drain electrode formed on the semiconductor layer and facing the source electrode; a connection assistant separated from the data line; a passivation layer covering the semiconductor layer and including contact holes exposing the connection assistant; and a pixel electrode including a plurality of sub-pixel electrodes and formed on the passivation layer, wherein the sub-pixel electrodes of one pixel are respectively connected to the connection assistant through the contact holes, and wherein the sub-pixel electrodes of the one pixel are electrically connected to each other through the connection assistant and at least one of the sub-pixel electrodes is electrically connected to the drain electrode.