Patent ID: 6295601
Filing Date: 2001-09-25
Classification: G06F

Abstract:
A processor configured to execute instructions in an instruction stream, at least some of the instructions being capable of giving rise to respective trap shadows, each of the at least some of the instructions capable of giving rise to respective trap shadows being associated with one of a plurality of trap barrier classes, the processor comprising:A. an instruction execution control configured to control execution of said instructions in said instruction stream;B. a trap barrier class indication generator configured to provide a trap barrier class indication for each of said trap barrier classes for which a trap shadow exists for the instructions whose execution is being controlled by said instruction execution control; andC. the instruction execution control including an execution stall control configured to stall execution of instructions in the instruction stream following a partial trap barrier instruction associated with a trap barrier class for which said trap barrier class indication generator is providing said trap barrier class indication, the instruction execution control being configured to not stall execution if the instructions following the partial trap barrier instruction are of a different class than that associated with the trap barrier class indication.