Patent ID: 9003170
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. An apparatus comprising: an execution unit that is operable to store a result in a destination operand as a result of an instruction, the instruction to indicate a first source operand in a register and a second source operand in one of a register and memory, the first source operand to have one of 16 bits, 32 bits, and 64 bits and the second source operand to have one of 32 bits and 64 bits, the result to have: a first range of bits having a first end at a least significant bit that is implicitly indicated by the instruction and a second end one bit before a bit position indicated by a value in a least significant byte of the first source operand, each bit in the first range identical in value to a bit of the second source operand in a corresponding position; and a second range of bits, starting at the indicated bit position and ending at a most significant bit, in which all bits have a value of zero.