Patent ID: 6157056
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cell rows and a plurality of transistors in which a first memory cell row having at least a memory cell transistor;a first transistor connected to either a drain side or a source side of the first memory cell row;a second memory cell row having at least a memory cell transistor;a second transistor connected to either a drain side or a source side of the second memory cell row;a third memory cell row having at least a memory cell transistor;a third transistor connected to either a drain side or a source side of the third memory cell row;a fourth memory cell row having at least a memory cell transistor; anda fourth transistor connected to either a drain side or a source side of the fourth memory cell row, wherein the first and second transistors are connected to either a data line or a source line through a first contact common to both the first and second transistors, and form a first memory cell group, the third and fourth transistors are connected to either a data line or a source line through a second contact common to both the third and fourth transistors, and form a second memory cell group, gate electrodes of the first and third transistors are connected in common to a first gate line, gate electrodes of the second and fourth transistors are connected in common to a second gate line, and said first and second memory cell groups are separated from each other such that an element separation region is inserted between said first and second memory cell groups; anda third gate line provided at a space between the first and second gate lines, the first contact being formed between the first and third gate lines, and the second contact being formed between the second and third gate lines.