Patent ID: 7273787
Filing Date: 2007-09-25
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a gate dielectric layer, comprising: providing a substrate divided into at least a high-voltage circuit region and a low-voltage circuit region; forming a first dielectric layer over the substrate, wherein the first dielectric layer serves as a gate dielectric layer in the high-voltage circuit region; forming a mask layer over the first dielectric layer; patterning the mask layer, the first dielectric layer and the substrate to form a trench in the substrate; forming an isolation layer over the substrate to fill the trench; removing the mask layer to expose the surface of the first dielectric layer; removing the first dielectric layer in the low-voltage circuit region to expose the surface of the substrate; and forming a second dielectric layer over the substrate in the low-voltage circuit region, wherein the second dielectric layer has a thickness smaller than the first dielectric layer.