Patent ID: 6707142
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A semiconductor device comprising a plurality of vertically stacked semiconductor chip packages, each of said packages comprising a semiconductor chip; a plurality of electrode pads on the chip at its active surface; and a plurality of conductive leads for electrically connecting the electrode pads to external world;each of said conductive leads including power pins for power signal for the semiconductor chip; data pins for inputting and outputting data to and from the semiconductor chip; control signal pins; and no connection (NC) pins; wherein said device comprises a plurality of pin connection parts for connecting the conductive leads of one package (â€œfirst packageâ€ ) to the respective corresponding conductive leads of the next stacked package (â€œsecond packageâ€ ); and wherein said first package comprises at least one control signal (â€œcoupling CS pinâ€ ) and at least one NC pin (â€œcoupling NC pinâ€ ), which are next to each other; said coupling CS pin being coupled to said coupling NC pin in such a way that they are electrically connected; and only one of said coupling CS pin or said coupling NC pin being electrically connected to the corresponding pin of the second package.