Patent ID: 7852343
Filing Date: 2010-12-14
Classification: G06F,H04N

Abstract:
1. An information processing device, comprising: a DRAM having a burst mode which burst-transfers data of successive column addresses; at least one data processor operable to issue an access request; and an address converter operable to convert access addresses which are included in the access request issued from said at least one data processor, wherein at least one of said at least one data processor is operable to access an M×N rectangular area, where M and N are positive integers, said address converter is operable to convert access addresses so that a column address of data at a (K+m)th column of an Lth line and a column address of data at a Kth column of an (L+n)th line become successive, where K, m, L, and n are positive integers, m≦M, and n≦N, and at least one rectangular area of said DRAM is a frame memory which stores image data, the at least one rectangular area is M pixels×N lines in the image data, and said at least one data processor is operable to perform one of motion compensation and motion estimation, where n=2n′ and n′ is a positive integer, wherein the DRAM burst-transfers the data at the (K+m)th column of the Lth line and the data at the Kth column of the (L+n)th line in the burst mode by successively accessing the column address of the data at the (K+m)th column of the Lth line and the column address of the data at the Kth column of the (L+n)th line.