Patent ID: 6687809
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A method comprising:maintaining load addresses of load instructions that have not been retired in a load buffer of a first processor; snoping the load buffer to determine whether a store address of a store instruction being dispatched matches one of the load addresses in the load buffer of the first processor, aborting a speculative state of the first processor in response to a match between the store address associated with the store instruction and one of the load addresses in the load buffer; maintaining store addresses of the store instructions dispatched during a last predetermined number of cycles in a first data structure of the first processor; in response to a load instruction being executed, determining whether a load address of the load instruction being executed matches one of the store addresses in the first data structure; and replaying the load instruction if the load address of the load instruction matches one of the store addresses in the first data structure.