Patent ID: 6038158
Filing Date: 2000-03-14
Classification: G11C

Abstract:
Semiconductor memory having first and second memory cell arrays in which memory cells are formed at the intersections of several bit line pairs and several extended bit line pairs extending in the same direction as that of said bit line pairs with several word lines, sense amplifier banks provided between the aforementioned memory cell arrays and which contain several sense amplifiers respectively connected to the bit line pair of the aforementioned first memory cell array via a first switching means, connected to the extended bit line pair of the aforementioned first memory cell array via a second switching means, connected to the bit line pair of the aforementioned second memory cell array via a third switching means, and connected to the extended bit line pair of the aforementioned second memory cell array via a fourth switching means, and a control circuit to control the conduction/nonconduction of the aforementioned first, second, third, and fourth switching means; wherein, the aforementioned control circuit makes one of the aforementioned first, second, third, and fourth switching means conductive and the others nonconductive in response to an address signal at the time of memory access.