Patent ID: 8767464
Filing Date: 2014-07-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array having at least two memory banks, wherein the memory banks can be accessed simultaneously, each of the memory banks comprises a plurality of memory cells formed in columns and rows, wherein gates of each row of the memory cells are coupled to each word line in common respectively, and each column of the memory cells is coupled to each bit line respectively; a first receive device for receiving address information; a second receive device for receiving a command related to an access operation; a word line selection device for decoding column address information received by the first receive device, and selecting a word line according to a decoding result; and a controller device controlling the word line selection device according to the command received by the second receive device, wherein, the controller device instructs the word line selection device to perform a first read operation according to a first read command, and instructs the word line selection device to perform a second read operation according to a second read command; wherein, the first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n−1)-th word line of the other one of the memory banks, and wherein, the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other one of the memory banks.