Patent ID: 9092236
Filing Date: 2015-07-28
Classification: G06F

Abstract:
1. An apparatus for producing an adaptive instruction prefetching and fetching memory system comprising: a static native instruction code (NIC) conversion system; and a dynamic adaptive instruction code (AIC) reversion system; wherein the apparatus for producing an adaptive instruction prefetching and fetching memory system is operable to: transform NIC comprising the native instructions compiled by a compiler running on a computer to AIC for delivering the same and compatible order of the native instructions to a microprocessor in a precise and timely manner via packed nonnative and non-packed native instruction (PINI) and/or native instructions and associative information of the packed nonnative instruction (NIPI) caches, which are at least two times faster than clock speed of the microprocessor; wherein the precise and timely manner delivering is to deliver the native instructions, which are possibly executed by the microprocessor, to the microprocessor with at least two times faster delivering speed than the clock speed of the microprocessor; generate the AIC comprising mixed PINIs as a first type of the AIC (FAIC), and NIPIs as a second type of the AIC (SAIC) for sequentially or concurrently prefetch and/or fetch PINIs and/or NIPIs to the microprocessor via the PINI and/or NIPI caches, which are at least two times faster than the clock speed of the microprocessor; transform the native instruction sequences in the NIC to the PINIs in the FAIC and the NIPIs in the SAIC by the compiler running on the computer before runtime; store the PINIs in the FAIC and the NIPIs in the SAIC to sequentially or concurrently accessible locations in a single or plurality of instruction memories; access sequentially or concurrently a single or plurality of the PINIs and/or the NIPIs stored in a single or plurality of PINI and/or NIPI caches accessing at least two times faster than the clock speed of the microprocessor during the PINI and/or NIPI prefetch and fetch operations; reduce fraction of the NIC by excluding and diminishing unconditional flow control native instructions used in the NIC from the PINIs in the FAIC and the NIPIs in the SAIC; reversely transform the PINIs in the FAIC with the NIPIs in the SAIC to the same or compatible order of native instructions during the PINI and NIPI fetch operations by the dynamic AIC reversion system; access a PINI in the FAIC to reversely transform the associated NIPI to a single or plurality of native instructions transformed in the PINI before runtime by the dynamic AIC reversion system and deliver the single or plurality of native instructions to the microprocessor via the NIPI caches operating at least two times faster than the clock speed of the microprocessor; transform subroutine call and return native instructions and a single or plurality of native instructions found in the subroutine in the NIC to a pair of PINI and NIPI by the compiler running on the computer in order to deliver the same or compatible order of the native instructions in the subroutine to the microprocessor for producing the same or compatible result within reduced time; transform a loop comprising a plurality of native instructions in the NIC to a pair of PINI and NIPI by the compiler running on the computer in order to deliver the same or compatible order of the native instructions in the loop to the microprocessor for producing the same or compatible result within reduced time; transform multi-level loops comprising a plurality of loops in hierarchical order in the NIC to a single loop in the AIC by transforming the outer loop in the NIC to a single loop in the AIC after transforming the inner loop in the NIC to a PINI and a single or plurality of NIPIs by the compiler running on the computer in order to deliver the same or compatible order of the native instructions in each level of loop to the microprocessor for producing the same or compatible result within reduced time; and prevent unauthorized usage of the PINIs and the NIPIs stored in the main PINI and NIPI memories by transforming orders of the PINIs and the NIPIs to the different sequences and/or allocating the PINIs and the NIPIs to the different locations in the single or plurality of main PINI and NIPI memories.