Patent ID: 6226723
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A computer memory device, comprising:an array of memory modules, each of which includes a matrix of memory cells, a plurality of data transfer ports, and a plurality of control transfer ports, with a memory interface coupled between said matrix of memory cells and said plurality of data transfer ports and said plurality of control transfer ports, wherein said memory interface of each memory module of said array includes chip-select logic in data communication with two of said plurality of control transfer ports defining select-in and select-out ports, and further including means in data communication with said array for storing address information within said chip-logic, said address information differing from address information stored in said chip-select logic of the memory modules of said array;a controller having a system input port a plurality of data output ports, and a plurality of control/address output ports, said controller being adapted to produce control signals including chip address information and cell address information;a data transfer bus coupled between said plurality of data transfer ports and said data output ports; anda control/address bus coupled between said plurality of control transfer ports and said control output ports, so that one of said plurality of control transfer ports of each of said modules are connected in common to transmit said chip select information and said address information between said controller and said array.