Patent ID: 7378317
Filing Date: 2008-05-27
Classification: H01L

Abstract:
1. A method for forming an MOS device, comprising: providing a semiconductor substrate of a first conductivity type having an upper surface; first implanting through the upper surface a first dose of a first conductivity type to form a first doped region that extends downwardly from the upper surface; forming a gate dielectric on the upper surface; depositing a gate conductor and an overlying dielectric layer on the gate dielectric; masking and etching the gate conductor and the overlying dielectric layer to provide at least two first spaced-apart openings extending to the gate dielectric and defining a lateral extent of the gate, wherein the lateral extent of the gate extends beyond the first doped region and over a portion of the semiconductor substrate that was masked during the first implanting step, and wherein the portion of the semiconductor substrate is adjacent to the first doped region at the upper surface; after the first implanting step, the forming step, the depositing step, and the masking and etching step, performing second implanting through the upper surface in the at least two first spaced-apart openings a second dose of a second opposite conductivity type to form second doped regions of a second opposite conductivity type in the substrate, wherein the second doped regions extend downwardly from the upper surface, and wherein the second doped regions are separated from the first doped region by the portion of the semiconductor substrate that was masked during the first implanting step; and anytime after the second implanting step, heat treating the device so that, in combination with the first and second doses, the first doped region and the second doped regions expand to meet, and so that the net active impurity concentration N