Patent ID: 7650131
Filing Date: 2010-01-19
Classification: H04L

Abstract:
1. A wireless receiver which is used for a digital signal transmission system to wirelessly transmit a digital signal by packetizing and modulating it, and selectively sets the shortest arithmetical bit length satisfying a required communication quality when performs demodulation arithmetical processing to demodulate the digital signal to be packet-transmitted, comprising: an error vector magnitude (EVM) calculation unit configured to calculate an EVM value that is a measure indicating a difference form a known ideal result by inputting a demodulating arithmetical result by the arithmetical bit length; and an arithmetical bit length selection unit configured to predict a bit error rate by using the EVM value as an evaluation criterion and for selecting an arithmetical bit length by which the bit error rate becomes optimum, wherein the demodulating arithmetical processing is performed by the selected arithmetical bit length.