Patent ID: 6707814
Filing Date: 2004-03-16
Classification: H04L,H04Q

Abstract:
A communication control apparatus for receiving reception cells and for transmitting transmission cells, each of the reception cells and the transmission cells having a header field assigned with an identifier and a payload field assigned with a payload, said communication control apparatus comprising:a physical layer device, connected to a network, having a function of a physical layer in an asynchronous transfer mode (ATM); a receiving section, connected to said physical layer device, for receiving said reception cells supplied from said network via said physical layer device, said receiving section including a memory for selectively storing the reception cells as stored cells, said receiving section carrying out, on the basis of a value of the identifier in the header field of each of the reception cells, decision of reception, verification for various errors, and reassembly of a reception packet constituted by a plurality of reception cells; a transmitting section, connected to said physical layer device, for carrying out cell segmentation of a transmission packet constituted by a plurality of transmission cells to be transmitted and rate control for the transmission cells, said transmitting section transmitting the transmission cells to said network via said physical layer device; and a direct memory access (DMA) controller, connected to said receiving section, said transmitting section, and a system bus, for interfacing said receiving section and said transmitting section with said system bus, said receiving section further comprising: address filtering means, connected to said physical layer device, for identifying a value of a particular address in the payload included in the payload field of a first cell for the reception packet to produce an address filtered signal indicative of an identified value; and write-in control means, connected to said address filtering means and said memory, for determining whether or not the reception packet should be received on the basis of the identified value indicated by the address filtered signal, said write-in control means writing the reception packet in said memory when the reception packet should be received, said write-in control means sequentially discarding all of the reception packet without writing any portion of the reception packet into said memory when the reception packet should not be received; wherein: the particular address consisting of a LAN emulation client (LEC) ID and a medium access control (MAC) address, said receiving section including a cell information table for storing cell information every channel, wherein said address filtering means comprises: an address storing section, connected to said physical layer device, for storing data including the particular address in the payload of the payload field as stored data; an address extracting section, connected to said address storing section, for extracting the LEC ID and the MAC address from the stored data to produce an extracted LEC ID and an extracted MAC address; LEC ID filtering means, connected to said cell information table and said address extracting section, for carrying out an LEC ID filtering on the basis of the extracted LEC ID and an LEC ID for the channel of the first cell that is read out of said cell information table to produce an LEC ID filtered signal; and MAC address filtering means, connected to said address extracting section, for carrying out an MAC address filtering on the basis of the extracted MAC address; wherein said MAC address filtering means comprises: a first MAC address filtering section for carrying out a broadcast filtering on the extracted MAC address for a broadcast to produce a first MAC address filtered signal; a second MAC address filtering section for carrying out a unicast filtering on the extracted MAC address for a unicast to produce a second MAC address filtered signal; and a third MAC address filtering section for carrying out a multicast filtering on the extracted MAC address for a multicast to produce a third MAC address filtered signal; and wherein said first MAC address filtering section comprises an AND circuit, connected to said address extracting section, for ANDing the extracted MAC address bit by bit to produce an ANDed result as the first MAC address filtered signal.