Patent ID: 6072682
Filing Date: 2000-06-06
Classification: H01L,H02H

Abstract:
A protected integrated semiconductor circuit capable of being activated in a dynamic circuit activated only by a transient condition, comprising:a power supply terminal and a ground terminal;first and second resistive elements;a first VDMOS transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the first transistor being coupled to the ground terminal through the first resistive element, the first terminal of the first transistor being coupled to the ground terminal through the second resistive element, and the second terminal being coupled to the power supply terminal through a capacitive element; anda second VDMOS transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the second transistor being coupled between the first terminal of the first transistor and the first resistive element, the first terminal of the second transistor being coupled to the ground terminal, and the second terminal of the second transistor being coupled to the power supply terminal, the channel region of the second VDMOS transistor structured to hold the operation of the first VDMOS transistor in a triode range, wherein the second VDMOS transistor is structured to be held at the range of the saturation range while holding the first VDMOS transistor in the triode range.