Patent ID: 6111897
Filing Date: 2000-08-29
Classification: H04J,H04N

Abstract:
A multiplexing apparatus in a digital communication system with a variable frame structure, comprising:FIFO means for buffering data inputted at a fixed speed and outputting the buffered data when the current region is a data region of a frame;write control means for outputting a write address to said FIFO means in response to a data input clock;read control means for outputting a read address to said FIFO means in response to a data output clock;stuff/delete determination means for generating a stuff indication signal and a delete indication signal in response to said write address from said write control means, said read address from said read control means and a frame synchronous signal, said stuff indication signal indicating the extension of said data region of said frame, said delete indication signal indicating the reduction of said data region of said frame; andmultiplexing means for multiplexing output data from said FIFO means to output frame data, said multiplexing means being further adapted to output a read control signal to said read control means in response to said stuff and delete indication signals from said stuff/delete determination means to control said read address from said read control means.