Patent ID: 6609247
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A method for debugging a system in a processor comprising:executing a plurality of instructions with an execution engine; retiring the instructions from the execution engine after the instructions are executed, wherein the executing comprises executing some of the instructions while retiring others of the instructions; writing information regarding the instructions to an execution trace buffer (ETB) as the instructions retire and while the execution engine processes others of the plurality of instructions, wherein the step of writing information comprises writing information based on a pre-selected mode of operation, wherein the step of writing comprises writing macroinstruction address information when operating in a macroinstruction mode and writing micro-ip address when operating in a microinstruction mode; and reading the information from the ETB, wherein the method is implemented in a mixed-architecture processor that processes both microinstructions and macroinstructions, and wherein the step of writing information comprises writing information regarding both microinstructions and macroinstructions.