Patent ID: 6845472
Filing Date: 2005-01-18
Classification: G06F,G11C

Abstract:
1. A system for detecting errors in a memory device, the system comprising: a memory sub-system comprising: a plurality of memory cartridges configured to store data words; a cleansing device configured to periodically initiate an internal READ command to the plurality of memory cartridges in response to an event, the internal READ command being issued to the plurality of memory cartridges on a memory network bus; and a monitoring device configured to monitor the memory network bus and further configured to change the frequency of periodic initiations of the internal READ commands based on the number of requests on the memory network bus over a period of time; and a host controller operably coupled to the memory sub-system and comprising error detection logic configured to detect errors in a data word which has been read from the plurality of memory cartridges.