Patent ID: 7867059
Filing Date: 2011-01-11
Classification: B24B,B24D,H01L

Abstract:
1. A process for planarizing a semiconductor wafer, comprising: holding the wafer in a workpiece holder in a free-floating position during grinding, double-side grinding the semiconductor wafer, in which the semiconductor wafer is simultaneously ground on both sides using two colinear, double spindle grinding tools, each double spindle haying an inner sub-spindle with one of a rough or finish grinding wheel and an outer sub-spindle with the other of a rough or finish grinding wheel, wherein the double-side grinding grinds firstly by simultaneously rough-grinding opposite sides of wafer and then by simultaneously finish-grinding opposite sides of wafer, wherein the semiconductor wafer, between rough-grinding and finish-grinding, remains positioned in one grinding machine, and a substantially constant load is applied to the wafer during the transition from rough-grinding to finish-grinding.