Patent ID: 6295571
Filing Date: 2001-09-25
Classification: G06F

Abstract:
An adapter for coupling a processor system to a shared memory unit over a dedicated data link, the processor system having a data bus for access to a local memory and a standard expansion bus coupled to the data bus, the shared memory unit having at least one bank of shared memory, the adapter comprising:a expansion bus interface coupling the adapter to the expansion bus of the processor system;an input/output port coupling the adapter to the shared memory unit via the dedicated data link;means coupled to the expansion bus interface for monitoring processor memory accesses on the data bus;means coupled to the data bus monitoring means for detecting when a monitored processor memory access is a processor memory access operation to a memory address value within a range of addresses corresponding to the shared memory;means coupled to the detecting means for translating the monitored processor memory access operation into a shared memory access request including an associated address and data;means for outputting the shared memory access request to the input/output port and, in turn, to the shared memory unit; andmeans coupled to the expansion bus interface for placing a memory access completion acknowledgement indication on the expansion bus;whereby it is transparent to the processor system whether the memory access operation is addressed to the local memory or to the shared memory.