Patent ID: 6437382
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A semiconductor device comprising:a diffusion layer formed on a semiconductor substrate; an interlayer insulator which covers a surface of the semiconductor substrate and whose surface is planarized; and a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator, the buried conductive layer in the contact hole including a lower plug member and an upper barrier layer, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film, wherein the lower electrode has a flat upper surface and a side-wall sloped configuration such that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer.