Patent ID: 6107121
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method for assembling a semiconductor device package comprising the steps of:forming an integrated circuit chip stack having at least three integrated circuit chips, said stack having a substantially planar bottom surface with a plurality of terminals extending therefrom;forming a carrier substrate having a bottom surface with a cutout portion extending to said bottom surface and having a plurality of terminals adapted to be electrically connected to said terminals of said chip stack via said cutout portion;mounting said chip stack through said cutout portion of said carrier substrate such that said chip stack lies substantially flush with the bottom surface of said carrier substrate;making electrical connections between said terminals of said chip stack and said terminals of said substrate from said bottom surfaces of the chip stack and carrier substrate respectively; andencapsulating said chip stack and said carrier substrate to support said chip stack mounted on said carrier substrate, and to provide protection from the environment.