Patent ID: 9142511
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A structure comprising: a planar insulating layer; a first semiconductor layer overlying the planar insulating layer, the first semiconductor layer having a planar bottom surface contacting a top surface of the planar insulating layer; a second semiconductor layer underlying the planar insulating layer, the second semiconductor layer having a planar top surface contacting a bottom surface of the planar insulating layer; one or more through vias each of which passes through the planar insulating layer and the first and second semiconductor layers; wherein each through via comprises: a respective first via portion passing through the first semiconductor layer and having a first sidewall portion adjacent to the planar insulating layer and provided by the first semiconductor layer; a respective second via portion passing through the second semiconductor layer; and a respective third via portion passing through the planar insulating layer; wherein in at least one through via, at least adjacent to the planar insulating layer, the first via portion is wider than the third via portion.