Patent ID: 6269097
Filing Date: 2001-07-31
Classification: H04L,H04Q

Abstract:
A time switch for TDM communication systems having a control memory performing a word operation comprising:(a) 16 input ports divided into an upper block and a lower block;(b) an address bus coupled to a processor for providing the control memory with control information;(c) a 16 bit data bus, which consists of a lower and an upper bit data bus, coupled to the processor;(d) an upper and lower multiplexer for sending 8 bit data being transmitted into the upper and lower input ports, respectively, into a data memory;(e) said data memory comprising an upper data memory and a lower data memory for saving the upper and lower block 8 bit data, respectively;(f) a control memory having an upper 256.times.16 bits (512 byte) control memory for controlling said upper data memory and a lower 256.times.16 bits (512 byte) control memory for controlling said lower data memory;(g) an upper and lower output conversion block for converting exchanged 8 bit data according to an output status;(h) an upper and lower demultiplexer for sending the converted 8 bit data into output ports assigned by each bit; and(i) 16 output ports divided into an 8 bit upper block and an 8 bit lower block, respectively.