Patent ID: 9112050
Filing Date: 2015-08-18
Classification: H01L

Abstract:
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: introducing a substrate supported by a substrate carrier into a plasma etch chamber, the substrate having a patterned mask thereon covering integrated circuits and exposing streets of the substrate, and the substrate carrier having a backside, wherein the substrate carrier comprises an outer tape frame and supporting dicing tape, and wherein the outer tape frame is thermally conductive; supporting at least a portion of the backside of the substrate carrier on a chuck of the plasma etch chamber; cooling substantially all of the backside of the substrate carrier, the cooling comprising cooling at least a first portion of the backside of the substrate carrier by the chuck, wherein cooling substantially all of the backside of the substrate carrier comprises cooling the tape frame and the substrate; and plasma etching the substrate through the streets to singulate the integrated circuits while performing the cooling substantially all of the backside of the substrate carrier; and wherein cooling substantially all of the backside of the substrate carrier, further comprises cooling the tape frame of the backside of the substrate carrier with a cooling concentric chuck ring surrounding the chuck.