Patent ID: 8977810
Filing Date: 2015-03-10
Classification: G06F

Abstract:
1. A memory controller comprising: an interface for receiving user transactions; an interface for communicating data with a memory device; and logic for: receiving a user transaction; determining one or more memory commands based on the user transaction, the one or more determined memory commands including one or more row memory commands and/or one or more column memory commands, each row memory command being configured to cause access to a group of data cells associated with a particular row of the memory device, each column memory command being configured to cause access to a particular data cell of an accessed row of the memory device; assigning each of the determined one or more memory commands to a respective pool slot in a memory command pool that includes a plurality of pool slots, the memory command pool also including one or more previously assigned memory commands in respective pool slots, the one or more previously assigned memory commands being associated with one or more previously received user transactions; determining one or more command dependencies for one or more of the determined one or more memory commands, each determined command dependency indicating a dependency relationship between or among the respective determined memory command and one or more of the other memory commands in the memory command pool; generating one or more bit vectors based on the determined one or more command dependencies, each bit vector being generated for a respective one of the determined one or more memory commands, each bit vector including a plurality of bits, each bit indicating whether the respective one of the determined one or more memory commands associated with the bit vector is dependent on an issuance of a respective one of the one or more other memory commands in the memory command pool associated with the bit or vice versa; and reordering issuances of one or more of the determined one or more memory commands relative to one or more of the other memory commands to improve an efficiency of the communication of data between the logic and the memory device, the reordering being based on the one or more bit vectors to prevent the issuance of any memory command from the memory command pool prior to the issuance of all other ones of the memory commands in the memory command pool on which it depends.