Patent ID: 6181748
Filing Date: 2001-01-30
Classification: H04L

Abstract:
A pulse shaping circuit apparatus for reshaping digital input signals for use in an ISDN U-interface, said circuit apparatus comprising:(a) at least two control clock signal generators responsive to control logic circuitry;(b) a switched-capacitor integrator circuit, said integrator circuit being electrically coupled to and being controlled by a first control clock signal generator member of said at least two control clock signal generators, said integrator circuit having integrator circuit element means for generating a first staircase-shaped waveform in response to a first set of non-overlap, variable period clock pulse signals and a reset signal generated by said first control clock signal generator member;(c) a sample and hold circuit, said sample and hold circuit being electrically coupled to and being controlled by a second control clock signal generator member of said at least two control clock signal generators and also being electrically coupled to said integrator circuit and having sample and hold circuit elements for generating a second staircase-shaped waveform in response to both a first set of non-overlap, constant period clock pulse signals from said second control clock signal generator member and to an analog voltage input from said integrator circuit, said analog voltage input comprising said first staircase-shaped waveform, said second staircase-shaped waveform comprising a reshaped signal; and(d) a low-pass filter and line driver circuit combination for outputting a filtered reshaped signal.