Patent ID: 9053962
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a first area; a gate electrode formed over said first area of said semiconductor substrate; a first active region formed in said first area of said semiconductor substrate at a lateral side of said gate electrode; a first silicide layer formed at least on a sidewall surface of said gate electrode, said first silicide layer being electrically connected to said first active region; a second silicide layer, that is electrically connected to said first silicide layer, formed on a surface of said first active region; and a contact via-plug formed on said second silicide layer and connected to said first silicide layer and said second silicide layer, wherein said sidewall surface includes a first sidewall surface and a second sidewall surface that faces said first sidewall surface, and said first silicide layer is formed at said first sidewall surface and said second sidewall surface.