Patent ID: 6016555
Filing Date: 2000-01-18
Classification: G06F

Abstract:
A method for debugging a processor within a data processing system, the processor having an instruction execution pipeline with at least a first pipeline phase followed by a second pipeline phase, comprising the steps of:forming a software breakpoint instruction within a sequence of instructions by replacing a field within an operational instruction with a predetermined breakpoint code;fetching and executing a portion of the sequence of instructions in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in the instruction pipeline;fetching and partially executing the software breakpoint instruction in the first pipeline phase of the instruction pipeline;halting the normal operation of the instruction pipeline in response to decoding the breakpoint code in the second pipeline phase of the instruction pipeline;performing a debug function in response to decoding the breakpoint code; andrestarting the normal operation of the instruction pipeline after the step of performing a debug function without refetching the operational instruction which was replaced by the software breakpoint instruction in a manner such that the operational instruction is executed as if the field within the operational instruction had not been replaced with the predetermined breakpoint code.