Patent ID: 8331555
Filing Date: 2012-12-11
Classification: G06F,H03K,H04L

Abstract:
1. An MD5 processing apparatus comprising a programmable device programmed to include: a plurality of processing engines, wherein each processing engine is configured to perform one stage of an MD5 process, wherein each MD5 process stage comprises four MD5 operations in a corresponding MD5 round, each processing engine comprising: a generator coupled to each of the processing engines, the generator being configured to pre-calculate a plurality of MD5 pre-adder values including the MD5 pre-adder value concurrently with the performing of the stages of the MD5 process by the processing engines; wherein each stage of the MD5 process performs the four MD5 operations of the corresponding MD5 round via the corresponding sub-stage units for advancing register values in the A register, B register, C register and D register respectively from A wherein each of the processing engines is configured to perform four iterations of the corresponding stage of the MD5 process to complete the corresponding MD5 round before supplying a corresponding output value, wherein a first processing engine of the processing engines is configured to supply the corresponding output value to a second processing engine of the processing engines; and wherein the second processing engine is configured to output an MD5 digest value as the corresponding output value.