Patent ID: 7439133
Filing Date: 2008-10-21
Classification: G11C,H01L

Abstract:
1. A method for forming a memory array, comprising: providing a semiconductor substrate; forming a plurality of first conductive lines on the semiconductor substrate, wherein the first conductive lines comprise a mask layer as an upper part and a first conductive layer as a lower part; forming a spacer at each side wall of the first conductive lines; forming a second conductive layer on the semiconductor substrate between every two first conductive lines to form a plurality of second conductive lines; forming a plurality of diffused lines in the semiconductor substrate between the first conductive lines where no second conductive layers are formed; depositing a first dielectric layer over the first conductive lines and the semiconductor substrate; planarizing the first dielectric layer using the top of the first conductive lines as a stop layer; removing the mask layer as the upper part of the first conductive lines; filling a third conductive layer as the upper part on the lower part of the first conductive lines, wherein the first conductive line and the third conductive layer have a total thickness more than the thickness of the second conductive line; removing a portion of the first dielectric layer to expose a top and partial side surface of the third conductive layer of the first conductive lines; forming a second dielectric layer on the exposed top and partial side surface of the third conductive layer of the first conductive lines; and forming a fourth conductive layer on the second dielectric layer and patterning the fourth conductive layer to form a plurality of lines over the third conductive layer and the first conductive lines and perpendicular to the diffused lines and defining a plurality of conductive blocks from the third conductive layer and the first conductive lines.