Patent ID: 6034545
Filing Date: 2000-03-07
Classification: H03K

Abstract:
A macrocell for a data processing circuit, comprising:macrocell logic; anda single interface for connecting the macrocell logic to a bus of the data processing circuit where the bus may be either one of a unidirectional bus or a bidirectional bus, the interface comprising:an input bus connected to an input bus terminal and an output bus connected to an output bus terminal;a buffering circuit for buffering the output bus from the macrocell logic; anda mode input terminal for receiving a mode value, the mode value being arranged to control the buffering circuit; wherein the buffering circuit is responsive to a first mode value to enter an inactive state when no data is being output from the macrocell, and is responsive to a second mode value to permanently drive the output buswherein said unidirectional bus connection is arranged such that the output bus terminal is coupled to a first unidirectional bus on the data processing circuit and the input bus terminal is coupled to a second unidirectional bus on the data processing circuit, said unidirectional bus connection is enabled in response to the second mode value being supplied to the mode input terminal; andwherein said bidirectional bus connection is arranged such that the input bus terminal and output bus terminal are connected together externally to the macrocell to enable the macrocell to be coupled to a bidirectional bus on the data processing circuit, and the bidirectional bus connection is enabled in response to the first mode value being supplied to the mode input terminal and the buffering circuit is responsive to an output enable signal to enter an active state when data is output from the macrocell.