Patent ID: 9081621
Filing Date: 2015-07-14
Classification: G06F

Abstract:
1. One or more computer storage memory hardware devices having computer-executable instructions embodied thereon that, when executed, perform a method for controlling an allocation rate of a logical processor to a root partition and to one or more virtual processors, wherein the logical processor is one of a plurality of logical processors that are partitioned on a physical machine to execute threads issued by the one or more virtual processors, the method comprising: monitoring over a window of time a pattern of input/output (I/O) operations performed by the root partition, wherein the logical processor is mapped to the root partition such that the root partition is exclusively scheduled on the logical processor; periodically updating a hardware interrupt rate stored in an interrupt table accessible by a scheduler during the window of time, wherein the hardware-interrupt rate is derived as a function of the pattern of I/O operations; and scheduling, by the scheduler, the one or more virtual processors to the plurality of logical processors, the scheduling comprising allocating the logical processor to execute threads, issued by the one or more virtual processors at a first rate and to execute the I/O operations, issued by the root partition, at a second rate, wherein the first rate is less than the second rate, inversely proportional to a hardware-interrupt rate stored in the interrupt table, greater than zero, and excluding the one or more virtual processors from being allocated to the logical processor at a rate greater than the first rate.