Patent ID: 9100264
Filing Date: 2015-08-04
Classification: H04B,H04L

Abstract:
1. A receiver configured to demodulate a pulse-width modulated (PWM) signal, comprising: multiple first delay cells coupled to one another in series in a first signal path, wherein said multiple first delay cells are operable to propagate a first signal along said first signal path for duration of a first interval between a first logic-level transition of said PWM signal and a second logic-level transition of said PWM signal; multiple second delay cells coupled to one another in series in a second signal path, wherein said multiple second delay cells are operable to propagate said first signal along said second signal path for duration of a second interval between said second logic-level transition of said PWM signal and a third logic-level transition of said PWM signal, wherein said second logic-level transition is between said first and third logic-level transitions and is followed by said third logic-level transition, wherein an interval between said first and third logic-level transitions represents a pulse period of said PWM signal, wherein each of said multiple first and second delay cells is operable to delay said first signal input to said each of said multiple first and second delay cells for a period of time as its output, wherein said first signal propagating along said second signal path is configured to change a logic level at said output of one of said multiple second delay cells; and a signal switch having an output port coupled to an input port of one of said multiple first delay cells, wherein said signal switch is configured to pass said first signal from an input port of said signal switch to said output port of said signal switch for duration of said first and second intervals.