Patent ID: 6629170
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A byte lane selectable performance monitor bus included within a semiconductor substrate, comprising:a plurality of byte lanes included within said semiconductor substrate configured for functional connection to a performance monitor unit, said performance monitor unit being located in a first area of said semiconductor substrate; a plurality of selection stages included within said semiconductor substrate functionally connected to the plurality of byte lanes;, wherein the plurality of selection stages selects, from a plurality of signals, monitored signals to be placed on the byte lanes, wherein the number of the plurality of signals is greater than the number of the plurality of byte lanes and wherein each stage of the plurality of selection stages progressively reduces the number of the plurality of signals sent to the next stage; wherein said plurality of signals excludes enable signals for enabling said plurality of selection stages for indicating a time to select signals for sampling; and said plurality of selection stages being distributed throughout said semiconductor substrate such that ones of said plurality of selection stages are located in areas of said semiconductor substrate which are not in proximity to said first area of said semiconductor substrate, wherein only selected only of said plurality of signals are received within said first area.