Patent ID: 8873293
Filing Date: 2014-10-28
Classification: G11C

Abstract:
1. A method for erasing, comprising: accessing data indicating an amount of program-erase cycles in a three-dimensional non-volatile memory, a plurality of sets of memory cells are formed above a substrate in multiple physical levels of memory cells in the three-dimensional non-volatile memory, the three-dimensional non-volatile memory comprising alternating word line layers and dielectric layers, the plurality of sets of memory cells comprises columnar active areas which are formed in memory holes which extend through the alternating word line layers and dielectric layers, each memory cell of the plurality of sets of memory cells has a control gate formed by one of the word line layers, each set of memory cells of the plurality of sets of memory cells comprises a drain end and a source end; and in connection with an erase operation of selected memory cells of the plurality of sets of memory cells, the selected memory cells are associated with one or more selected word line layers of the word line layers, applying a plurality of erase voltages, in turn, to each set of the plurality of sets of memory cells, each erase voltage charges up the columnar active areas to a charged state, driving a voltage of the one or more selected word line layers lower after each erase voltage so that threshold voltages of the selected memory cells are driven lower, the plurality of erase voltages include an initial erase voltage and a subsequent erase voltage which is stepped up from the initial erase voltage by a step size which is based on the data, and the step size is relatively higher when the amount of program-erase cycles is relatively higher.