Patent ID: 6330644
Filing Date: 2001-12-11
Classification: H04N

Abstract:
A signal processor comprising:a plurality of processing units, arranged to carry out a plurality of processes which differ from one another, wherein the plurality of processing units include an image data I/O unit, an audio data processing unit, an encoder, and an encoded data I/O unit, and wherein the encoder includes an orthogonal transformer for orthogonally transforming image data and a quantizer for quantizing the transformed image data;a memory unit, arranged to store information data, said memory unit being used in common by said plurality of processing units;a clock generator, arranged to generate a plurality of reference clocks respectively corresponding to the processes performed by said plurality of processing units;an address conversion unit, arranged to, when one of the plurality of processes is to be executed, generate respective appropriate addresses using the respective reference clocks in accordance with the one process;a mode designation unit, arranged to designate an operation mode from a plurality of operation modes; anda controller, arranged to sequentially cause each of said plurality of processing units to access said memory unit by using the respective appropriate addresses for the plurality of processes performed respectively by said plurality of processing units,wherein said controller sets a priority for each of said plurality of processing units in accordance with the operation mode designated by said mode designation unit, and controls access of each of said plurality of processing units to said memory unit in accordance with the set priority for each of said plurality of processing units.