Patent ID: 8724479
Filing Date: 2014-05-13
Classification: H04L

Abstract:
1. An apparatus, comprising: a validation engine implemented in at least one of a memory or a processing device, the validation engine implemented within a first edge device not included in a multi-stage switch fabric, the validation engine configured to define a plurality of validation packets, a number of validation packets from the plurality of validation packets being based on a number of data paths from a plurality of data paths across the multi-stage switch fabric and between the first edge device and a second edge device, the validation engine configured to send each validation packet from the plurality of validation packets to a packet forwarding engine of the first edge device, each validation packet from the plurality of validation packets to cause the packet forwarding engine to send that validation packet to the second edge device via a data path from the plurality of data paths and the second edge device to validate the plurality of data paths across the multi-stage switch fabric and between the first edge device and the second edge device based on a number of received validation packets from the plurality of validation packets.