Patent ID: 8533505
Filing Date: 2013-09-10
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus comprising: first processing circuitry and second processing circuitry where both circuitries are configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time; power control circuitry for independently controlling the power supply to the first processing circuitry and the second processing circuitry; a workload transfer controller configured to be responsive to a transfer stimulus to initiate a transfer of performance of the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing circuitry being placed in a power saving condition by the power control circuitry. the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry: wherein: at least the source processing circuitry has a cache; the power control circuitry is configured, following said transfer, to maintain at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry; the data processing apparatus comprises cache snooping circuitry configured during the snooping period to snoop data values in the cache of the source processing circuitry and to retrieve the snooped data values for the destination processing circuitry; and the power control circuitry is configured to place said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period, wherein the power control circuitry is configured to place the source processing circuitry, other than the cache, in the power saving condition during the snooping period. and to place the cache of the source processing circuitry in the power saving condition following the end of the snooping period, wherein the cache of the source processing circuitry is part of a cache hierarchy within the source processing circuitry, and during the snooping period the cache is maintained in the powered state while at least one other cache in the cache hierarchy is in the power saving condition.