Patent ID: 6222784
Filing Date: 2001-04-24
Classification: G11C,H01L

Abstract:
A semiconductor memory circuit having a memory cell array and a sense amplifier array, comprising:a plurality of pairs of bit lines arranged in parallel with one another in the memory cell array, each of said pairs of bit lines disposed within a predetermined width, said pairs of bit lines including a plurality of first pairs of bit lines and a second pair of bit lines;a pair of data buses substantially arranged in perpendicular to the pairs of bit lines in the sense amplifier array;a plurality of sets of peripheral circuits formed in the sense amplifier array with the predetermined width, each set of the peripheral circuits being electrically connected to one of the first pairs of bit lines and the pair of data buses, each set of the peripheral circuits located at a corresponding area of the corresponding one of the first pairs of bit lines; andan independent circuit located at a corresponding area of the second pair of bit lines in the sense amplifier array within the predetermined width, wherein said independent circuit is not electrically connected to said pairs of bit lines.