Patent ID: 8572342
Filing Date: 2013-10-29
Classification: G06F,G11C

Abstract:
1. A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprising: an inter-memory data transfer control unit performing data transfer between the memories, the inter-memory data transfer control unit including an operation start trigger receiving unit for receiving an operation start trigger from the processor, a parameter acquiring unit for acquiring a transfer instruction parameter including information on a data transfer instruction created by the processor, a read unit for reading data from the memory designated by the transfer instruction parameter, a write unit for writing the data read by the read unit into the memory designated by the transfer instruction parameter, wherein when the write unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the write unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory, when a data transfer instructed by the processor is completed, in order to confirm that writing into the memory is completed as to the write destination memory at the end of the data transfer, the write unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the memory, and the inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.