Patent ID: 6807602
Filing Date: 2004-10-19
Classification: G06F

Abstract:
A computer system, comprising:memory systems, each of said memory systems having memory and a memory controller for storing and retrieving data; at least one processor configured to transmit requests to write data values, said requests including bus addresses; a first mapper configured to map said bus addresses into memory addresses, each of said memory addresses identifying a memory location in one of said memory systems, said first mapper configured to map a consecutive set of bus addresses such that memory addresses mapped from said consecutive set of bus addresses are interleaved across a plurality of said memory systems, said first mapper further configured to identify a plurality of checksum system identifiers in response to said requests, said checksum system identifiers identifying each of said plurality of memory systems, said first mapper configured to utilize said checksum system identifiers to indicate locations of checksum values to be updated based on said data values, said first mapper having a plurality of entries, each of said entries identifying a respective block of contiguous memory within a respective one of said memory systems, said first mapper configured to map one of said bus addresses to one of said entries and to one of said memory addresses identifying a memory location within the block of contiguous memory identified by said one of said entries; and a second mapper having access keys, said second mapper configured to map, to different ones of said access keys, a plurality of different bus addresses that are mapped to a same one of said entries by said first mapper such that each of said different ones of said access keys is mapped to less than all of said plurality of different bus addresses by said second mapper.