Patent ID: 6455886
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a trough formed in the substrate; a bit line buried in the trough and surrounded by a dielectric material; a buried strap connecting the bit line to the substrate; a trough top dielectric formed in the trough above the bit line; a dopant rich source provided between the trough top dielectric and the bit line; source/drain diffusion formed in the substrate adjacent to the buried strap; an extension of the source/drain diffusion being formed by out-diffusion of dopants from the dopant rich source into the substrate; a gate conductor formed in the trough over the trough top dielectric; a node diffusion formed at a surface of the substrate, the node diffusion, the source/drain diffusion and the gate conductor forming a transistor, a channel of the transistor extending in a straight line from the node diffusion to the source/drain diffusion; and a contact area within a rhomboid shape active region connected to said node diffusion for providing a contact for a stacked capacitor.