Patent ID: 6992927
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. An apparatus including an integrated nonvolatile memory circuit having a plurality of control devices, comprising: a memory electrode for conveying an electrode voltage indicative of a charge state corresponding to a data bit; a control electrode for conveying a control voltage; a write electrode for conveying a write voltage; a read electrode for conveying a read voltage; an erase electrode for conveying an erase voltage; an input electrode for conveying an input data signal; an output electrode for conveying an output data signal; a control device with at least first and second electrodes connected to said memory and control electrodes, respectively; a write device with at least first, second and third electrodes connected to said memory, write and input electrodes, respectively; a read device with at least first, second and third electrodes connected to said memory, read and output electrodes, respectively; and an erase device with at least first and second electrodes connected to said memory and erase electrodes, respectively.