Patent ID: 9122411
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A signal order-preserving method, comprising: when writing, into at least one first first input first output (FIFO) memory, data of a request signal that comes from at least one corresponding first upstream device, writing invalid data into at least one second FIFO memory corresponding to at least one second upstream device in a same clock cycle as that of writing the data of the request signal; and reading the data of the request signal from the at least one first FIFO memory, reading the invalid data from the at least one second FIFO memory, discarding the invalid data, and conveying the data of the request signal to a downstream device, wherein writing the invalid data into the at least one second FIFO memory corresponding to the at least one second upstream device in the same clock cycle as that of writing the data of the request signal, when writing, into the at least one first FIFO memory, the data of the request signal that comes from the at least one corresponding first upstream device, comprises: