Patent ID: 6556398
Filing Date: 2003-04-29
Classification: H01L

Abstract:
An ESD protection circuit for preventing an internal circuit from being damaged by ESD, wherein the internal circuit is connected to a pad, the ESD protection circuit comprising:a first transistor having a drain connected to the pad and through which ESD flows when the pad suffers ESD; a second transistor having a source and gate both connected to an input node for a supply voltage and having a drain coupled to a source of the first transistor; and a voltage divider connected between the pad and the input node for the supply voltage, comprising an upper load and an lower load connected in series, the upper load and lower load also being coupled to the pad and the input node for the supply voltage respectively, and the gate of the first transistor being connected to where the upper load and lower load are connected together for receiving a bias voltage when ESD occurs.