Patent ID: 7778107
Filing Date: 2010-08-17
Classification: G11C

Abstract:
1. An apparatus for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the apparatus comprising: for each bit of the first multi-bit block address portion, a respective address detection circuit for detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and a combining circuit for combining outputs of the address detection circuits to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi-bit block address portion of the second address; and N inputs, where N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion; wherein for each input of the N inputs, the apparatus is configured to receive through the input a bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and wherein each address detection circuit comprises: a rise detecting circuit for detecting rising address transitions; a fall detecting circuit for detecting falling address transitions; and a combining circuit for combining outputs of the rise detecting circuit and the fall detecting circuit.