Patent ID: 8802563
Filing Date: 2014-08-12
Classification: H01L,Y02P

Abstract:
1. A method of fabricating an interconnect structure comprising: forming a pad stack on a surface of a dielectric material, said dielectric material having a dielectric constant of about 4.0 or less; providing at least one opening through said pad stack and into a portion of said dielectric material; forming a diffusion barrier and at least one conductive material within said at least one opening and on an upper surface of the pad stack, wherein said at least one conductive material is selected from a conductive metal, an alloy including at least two conductive metals and a conductive metal silicide; removing a portion of the diffusion barrier atop said pad stack, a portion of said at least one conductive material atop said pad stack and said pad stack by planarization, wherein a remaining portion of said diffusion barrier and a remaining portion of the at least one conductive material within the at least one opening each has an upper surface that is coplanar with an upper surface of the dielectric material; intentionally forming hollow-metal related defects at an upper surface of said at least one conductive material and that extend inward into the at least one conductive material, wherein said intentionally forming said hollow-metal related defects occurs after and separate from said planarization by utilizing an etching process selected from wet etching and dry etching; and filling said hollow-metal related defects with a surface repair material selected from a metal or metal alloy, wherein said filling of said hollow-metal related defects provides said surface repair material having an uppermost surface that is coplanar with said uppermost surface of the at least one conductive material and said upper surface of the dielectric material.