Patent ID: 9087580
Filing Date: 2015-07-21
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor memory cell comprising: a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions; wherein said capacitorless transistor and said non-volatile memory are connected in series; wherein current flowing to said resistance change element flows through said floating body; wherein one of said predetermined conditions comprises loss of power to said cell; wherein said cell is configured to perform a shadowing process when said data in said floating body is loaded into and stored in said nonvolatile memory; wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.