Patent ID: 7869256
Filing Date: 2011-01-11
Classification: G11C

Abstract:
1. A non-volatile memory device comprising: a memory cell array comprising a plurality of memory cells disposed in a matrix of rows and columns, wherein each one of the memory cells in the memory cell array stores data in accordance with voltage polarities applied to opposite ends of the memory cell; a first decoder configured to decode a first portion of a row address associated with one of the plurality of memory cells into a first address, the first decoder being disposed in a row direction with respect to the memory cell array; a second decoder configured to decode a second portion of the row address different from the first portion into a second address, the second decoder being disposed in a column direction with respect to the memory cell array and the row address being completely defined by the first and second addresses; a driver communicating data to be stored in the memory cell array and configured to apply bias voltages to word lines in the memory cell array responsive to the first address or the second address in accordance with a value of the data to be stored, wherein the memory cell array further comprises a plurality of sub cell arrays, wherein the second decoder comprises a plurality of second decoders respectively disposed in each one of the plurality sub cell arrays, and wherein the driver comprises a plurality of drivers respectively disposed in each one of the plurality of sub cell arrays and adjacent to each one of the plurality of the second decoders; and a plurality of power switches, each respectively supplying power to one of the plurality of sub cell arrays, wherein each of the plurality of power switches comprises