Patent ID: 6115804
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A computer system comprising:a node interconnect;first and second processing nodes that are each coupled to said node interconnect, wherein said first processing node includes a system memory and a first processor and a second processor that each have a respective one of a first cache hierarchy and a second cache hierarchy, said first and second cache hierarchies being coupled by a local interconnect, and wherein said second processing node includes at least a system memory and a third processor having a third cache hierarchy;wherein each of said first cache hierarchy and said third cache hierarchy concurrently store an unmodified copy of a particular cache line in a Recent coherency state due to receiving at said second processing node a read request for a copy of said particular cache line from said first cache hierarchy, wherein said copy of said particular cache line can be sourced by shared intervention from both said first cache hierarchy and said third cache hierarchy, and wherein said first cache hierarchy sources a copy of said particular cache line to said second cache hierarchy by shared intervention in response to a read request by said second cache hierarchy utilizing communication on only said local interconnect and without communication on said node interconnect.