Patent ID: 9131240
Filing Date: 2015-09-08
Classification: H04N

Abstract:
1. A video decoding apparatus to decode an input bitstream, the apparatus comprising: a decoder unit configured to control a video decoding operation on the input bitstream; and a multi-core processor configured to perform the video decoding operation on the input bitstream using the decoding unit, the multi-core processor comprising: a first core configured to parse the input bitstream into a plurality of slices and to allocate the plurality of slices; and a second core to receive an allocated slice from the first core, to generate a plurality of macroblocks by decoding the received slice, to store the plurality of macroblocks in first and second buffers included in an auxiliary memory thereof, to transfer the stored macroblocks from the first and second buffers to a main memory, and to reconstruct an image for the macroblocks, wherein the second core transfers the stored macroblocks from one of the first and second buffers to the main memory while the second core simultaneously stores the macroblocks in the other buffer from among the first and second buffers, and wherein the first and second buffers repeatedly store and transfer macroblocks in turns, wherein the second core repeatedly stores the macroblocks in the first buffer, transfers the macroblocks stored in the first buffer to the main memory while storing the macroblocks in the second buffer in response to the first buffer being full, and transfers the macroblocks stored in the second buffer to the main memory while storing the macroblocks in the first buffer, in response to the second buffer being full, until all of the plurality of macroblocks for the received slice are transferred to the main memory.