Patent ID: 6301158
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a plurality of word lines;a plurality of bit lines;a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells having a charge storage layer, a control gate, a drain, a source and a channel region, and storing data based on an amount of charges stored in the charge storage layer, the control gates of the memory cells of one row being connected to one of the word lines, adjacent ones of the memory cells of one row being connected such that the drain of one of the adjacent ones is connected to the source of the other, adjacent ones of the memory cells of one column being connected such that the drain of one of the adjacent ones and the source of the other are connected to one of the bit lines;a row decoder, supplied with an address signal, for selecting the word line;a column decoder, supplied with an address signal, for selecting the bit line; anda program circuit for programming data in the memory cells,said program circuit executing data programming such that data programming for the memory cells of one column is completed first and then data programming for the memory cells of an adjacent column is started, and such that data programming makes progress from the memory cells at one end of the memory cell array to the memory cells at the other end of the memory cell array.