Patent ID: 6313034
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A method for forming an integrated circuit device structure upon a semiconductor substrate comprising:forming upon a semiconductor substrate a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure, the PBLOCOS oxidation mask structure comprising:a blanket pad oxide layer formed upon the semiconductor substrate;a blanket polysilicon buffer layer formed upon the blanket pad oxide layer; anda patterned silicon nitride layer formed upon the blanket polysilicon buffer layer;forming a pair of Field OXide (FOX) isolation regions through complete thermal oxidation of portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed adjoining the patterned silicon nitride layer of the PBLOCOS oxidation mask structure, the pair of FOX isolation regions when completely formed defining an active semiconductor region of the semiconductor substrate, the active semiconductor region having formed thereupon a patterned pad oxide layer upon which is formed a patterned polysilicon buffer layer upon which in turn is formed the patterned silicon nitride layer;removing from the patterned polysilicon buffer layer the patterned silicon nitride layer;etching sequentially the patterned polysilicon buffer layer and the patterned pad oxide layer to yield an etched patterned polysilicon buffer layer and an etched patterned pad oxide layer which leave exposed a first portion of the active semiconductor region of the semiconductor substrate;forming over the etched patterned polysilicon buffer layer, the etched patterned pad oxide layer and the first portion of the active semiconductor region of the semiconductor substrate a blanket second polysilicon layer; andetching sequentially the blanket second polysilicon layer, the etched patterned polysilicon buffer layer and the etched patterned pad oxide layer to leave exposed a second portion of the active semiconductor region of the semiconductor substrate separated from the first portion of the active semiconductor region of the semiconductor substrate by a twice etched patterned pad oxide layer and a twice etched patterned polysilicon buffer layer, where:the twice etched patterned pad oxide layer forms a gate oxide layer within a field effect transistor;the twice etched patterned polysilicon buffer layer forms at least in part a gate electrode within the field effect transistor; andan etched second polysilicon layer formed from the blanket second polysilicon layer forms a shunt between the gate electrode of the field effect transistor and a first source/drain electrode of the field effect transistor, where the first source/drain electrode of the field effect transistor is formed within the first portion of the active semiconductor region of the semiconductor substrate.