Patent ID: 6506652
Filing Date: 2003-01-14
Classification: H01L,Y10S

Abstract:
A method comprising:providing a substrate with an insulative layer formed thereon; forming a gate layer on said insulative layer; forming a thin first spacer layer with a first thickness on said gate layer and said substrate; forming a thick second spacer layer with a second thickness on said thin first spacer layer; removing a portion of said thick second spacer layer to form thick second spacers, maintaining said second thickness; recessing said thick second spacers deeper than a surface level of said gate layer, said thick second spacers having a flat top; removing a portion of said thin first spacer layer to form recessed thin first spacers, exposing sidewalls of said gate layer; depositing a reactant layer on said gate layer; annealing said reactant layer and said gate layer to form a conductive layer, such that upper surface of said gate layer becomes level with said flat top; and removing an unreacted portion of said reactant layer.