Patent ID: 6747895
Filing Date: 2004-06-08
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:(a) a memory cell comprising second semiconductor regions for a source and a drain, respectively, formed in a first semiconductor region in a semiconductor substrate; a charge accumulation layer formed on a region between said second semiconductor regions for the source and the drain, through a gate insulating film; and a control electrode provided on said charge accumulation layer through an insulating film; (b) a third semiconductor region formed between said first semiconductor region and the semiconductor substrate; (c) first voltage application means for applying a voltage to said control electrode; (d) a second voltage application means for applying a voltage to said first semiconductor region; and (e) a third voltage application means for applying a voltage to said third semiconductor region; and (f) means for determining a threshold voltage of said memory cell, wherein a first voltage is applied to said control electrode and a second voltage is applied to said first semiconductor region during a first period, thereby allowing electrons accumulated in said charge accumulation layer to be pulled out into said first semiconductor region, the threshold voltage of said memory cell is determined in a second period following said first period, if it is determined that the threshold voltage of said memory cell is higher than a predetermined threshold voltage, the first voltage is applied to said control electrode and the second voltage is applied to said first semiconductor region in a third period following said second period, thereby allowing the electrons accumulated in said charge accumulation layer to be pulled out into said first semiconductor region, and a third voltage is applied to said third semiconductor region during said first to third periods.