Patent ID: 6509772
Filing Date: 2003-01-21
Classification: H03K

Abstract:
A flip-flop comprising:a data input node to receive a data signal; a first pass element connected to the data input node, and controlled by one phase of a clock signal, wherein the first pass element includes a plurality of source terminals and a plurality of drain terminals and only two of the source and drain terminals connect directly together; a second pass element connected to the first pass element at a first internal node and at a second internal node separated from the first internal node, and controlled by another phase of the clock signal, wherein the second pass element includes a plurality of source terminals and a plurality of drain terminals and only two of the source or drain terminals connect directly together; a plurality of inverters connected to a selected pass element among the first and second pass elements to delay the clock signal to the selected pass element by more than two inverters delay; and a memory unit connected to the second pass element to provide an output signal to an output node.