Patent ID: 7749816
Filing Date: 2010-07-06
Classification: H01L

Abstract:
1. A method to form an integrated circuit constrained by a gate pitch, the method comprising: identifying the gate pitch of a substrate, the gate pitch being a distance between a centerline of a first gate and a centerline of a second gate that facilitates placement of a contact between the gates and in contact with a diffusion area of the substrate; forming cell structures with the substrate, wherein forming cell structures with the substrate comprises forming gates in the substrate at the gate pitch and doping the substrate; forming a first set of metallization layers over the substrate to interconnect the cell structures, the first set of metallization layers comprising lines, the lines being substantially parallel to the gates, wherein at least one of the first set is an adjusted metallization layer comprising adjusted lines, the adjusted lines being substantially parallel to the gates, the adjusted lines being pitched at the gate pitch and substantially vertically aligned with the gates, and, wherein at least another of the first set is an unadjusted metallization layer comprising lines pitched at a first wire pitch, wherein the first wire pitch is different from the gate pitch, wherein the lines of the adjusted metallization layer connect to the cell structures with contacts; and forming a second set of metallization layers over the substrate comprising lines, the lines being orthogonal to the gates, wherein the lines of the first set of metallization layers interconnect with the lines of the second set of metallization layers with vias to form circuitry of the integrated circuit.