Patent ID: 6311286
Filing Date: 2001-10-30
Classification: G06F

Abstract:
A memory controller for adaptively generating timing signals for controlling one or more memory elements having coded timing values in a computer system, comprising:means for reading and decoding the coded memory element timing values present in the memory element;means responsive to said means for reading and decoding for profiling the timing characteristics of said one or more memory elements as one or more profiles relative to the coded memory element timing values of the memory elements in use in the computer system;means for storing said one or more profiles of said one or more memory elements that may be controlled by said memory controller;means for automatically selecting said one or more profiles based on the coded timing values, said one or more profiles corresponding to said one or more memory elements in the computer system for adaptively providing a plurality of predetermined timing characteristic values representing timing characteristics of the memory circuits based on the coded memory element timing values of the memory elements in use in the computer system;means responsive to the timing characteristics values for calculating a plurality of timing control values representing time intervals between memory timing events,the timing control values includingfirst timing control values representing memory timing events relative to the start of a memory operation cycle, and second timing control values representing memory timing events relative to other memory timing events; anda state machine responsive to the first and second timing control values for generating actual timing signals for adaptively controlling operation of the memory elements.