Patent ID: 6693001
Filing Date: 2004-02-17
Classification: H01L

Abstract:
A method of fabricating a semiconductor integrated circuit device, comprising the steps of:(a) forming an isolation groove in a silicon surface of a first major surface of a wafer so as to divide the silicon surface into two regions which are to be first and second regions; (b) forming a first insulating film of silicon oxide by chemical vapor deposition over the silicon surface and in the isolation groove; (c) planarizing the silicon surface covered with the first insulating film by removing the first insulating film outside the isolation groove with chemical mechanical polishing; (d) forming two gate electrodes to be N- and P-type gate electrodes respectively over the first and second regions, each of said two gate electrodes having a silicon film to be a polysilicon conductive film; (e) forming N-type source and drain regions in the first region, said N-type source and drain regions constituting a first insulated gate field effect transistor together with the N-type gate electrode; (f) forming P-type source and drain regions in the second region, said P-type source and drain regions constituting a second insulated gate field effect transistor together with the P-type gate electrode doped with boron; (g) depositing a Co film on the silicon surface over said N-type and P-type source regions and drain regions, and upper surfaces of said N- and P-type gate electrodes respectively isolated from said N-type and P-type source regions and drain regions with insulating side walls, by sputtering, from a Co sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, and wherein a sum of Fe and Ni in the Co sputtering target is not greater than 50 ppm by weight, wherein the sputtering is performed in such a manner that the composition of the deposited Co film is substantially the same as that of the Co sputtering target; (h) performing first rapid thermal annealing at a first temperature to the first major surface covered with the Co film so as to form Co monosilicide films on the silicon surface and the upper surfaces, leaving a remaining Co film not formed into Co monosilicide, wherein the first temperature is a temperature that creep-up across the insulating side walls substantially does not take place; (i) removing the remaining Co film, remaining over the first major surface, by wet etching; and (j) after step (i), performing second rapid thermal annealing at a second temperature higher than the first temperature to the first major surface so as to form Co disilicide films on the silicon surface and the upper surfaces.