Patent ID: 6055555
Filing Date: 2000-04-25
Classification: G06F

Abstract:
An interface circuit for performing parallel arithmetic and round operations comprising:a first adder circuit receiving a true result of an arithmetic operation in an intermediate format as an input, and outputting both the true result in a final format and a first representable number approximating the true result;a second adder circuit, connected in parallel to the first adder circuit, the second adder circuit receiving the true result in the intermediate format and a 1 as inputs, and outputting a second representable number approximating the true result said second adder circuit comprising:a carry save adder receiving as inputs the L-bit true result in the intermediate format and a 1, the carry save adder outputting an L-bit output in the intermediate format; anda carry propagate adder connected to the output of the carry save adder, said carry propagate adder converting the L-bit output from the carry save adder in the intermediate format to an L-bit output in the final format, the N most significant bits of the L-bit output of the carry propagate adder comprising the second N-bit representable number; anda selection circuit connected to the outputs of the first and second adder circuits, the selection circuit outputting either the first or second representable number as a rounded result of the arithmetic operation.