Patent ID: 6683932
Filing Date: 2004-01-27
Classification: H03K

Abstract:
A single-event upset immune frequency divider circuit, comprising:a dual-path shift register having a clock input, a signal input pair, and a plurality of signal output pairs, wherein said clock input receives an input clock signal; a dual-path multiplexor having a plurality of signal input pairs and an output pair, wherein said plurality of signal input pairs are respectively connected to said plurality of signal output pairs of said dual-input shift register, wherein one of said signal output pairs of said dual-path shift register is selected by said dual-path multiplexor to feed back into said signal input pair of said dual-path shift register; and a summing circuit for summing said output pair of said dual-path multiplexor to generate an output clock signal, wherein said output clock signal is a fraction of the frequency of said input clock signal.