Patent ID: 8432003
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A semiconductor device comprising: an element isolating region provided on a principal surface of a semiconductor substrate; and an element forming region provided on said principal surface to be surrounded by said element isolating region, wherein a first direction and a second direction are defined on said principal surface so as to be orthogonal to each other, wherein an outer circumferential shape of said element forming region has a first side extending along said first direction, wherein said element forming region comprises: a first transistor region; a second transistor region arranged between said first side and said first transistor region; and a dummy region arranged on a side of said second transistor region in said first direction, wherein said first transistor region comprises a first channel forming region extending to face to said first side, said second transistor region comprises a second channel forming region extending to face to said first side, said first channel forming region comprises a non-facing region that does not face to said second channel forming region, and said dummy region faces to said non-facing region in said second direction, wherein said element isolating region is formed of a first material that is an insulating material, wherein said first transistor region and said second transistor region are formed of a second material that is a semiconductor material, wherein said dummy region is formed of said second material, wherein said first transistor region and said second transistor region are next to each other, wherein said second material is continued between said first transistor region and said second transistor region, wherein said first transistor region and said dummy region are next to each other in said second direction, wherein said second material is continued between said first transistor region and said dummy region, wherein said first transistor region is divided into two first diffusion regions by said first channel forming region, and said second transistor region is divided into two second diffusion regions by said second channel forming region, wherein a first dummy gate forming region is provided in said dummy region so as to extend along said first direction and divide said dummy region into two dummy diffusion regions, wherein one of said two first diffusion regions are adjacent to one of said two dummy diffusion regions, wherein a second dummy gate forming region is provided in said element forming region such that said one first diffusion region and said one dummy diffusion region are divided, and wherein a second dummy gate is provided on said second dummy gate forming region, and wherein a voltage is applied to said second dummy gate such that said one first diffusion region and said one dummy diffusion region are electrically separated.