Patent ID: 7508192
Filing Date: 2009-03-24
Classification: G01R,H01L

Abstract:
1. A circuit comprising: an input terminal configured to feed an input signal into the circuit; an output terminal configured to output a signal processed by the circuit; a processing circuit connected between the input terminal and the output terminal and configured to process the input signal; a supply voltage terminal configured to supply a supply voltage to the circuit; a ground terminal connected to the circuit; wherein the processing circuit comprises a capacitive element with a first and a second capacitance terminal, wherein the capacitive element comprises a series connection of two series capacitors which are connected to each other at an inner capacitance node; wherein the first or the second capacitance terminal is coupled to a reference terminal, the reference terminal comprising the input terminal, the output terminal, the supply voltage terminal or the ground terminal, such that direct current or alternating current flows, provided that the alternating current has a frequency such that the series capacitors have an impedance of more than 500 Ω; and a testing terminal coupled to the inner capacitance node, wherein at least one of the two series capacitors is positioned between the testing terminal and the reference terminal.