Patent ID: 7538443
Filing Date: 2009-05-26
Classification: H01L

Abstract:
1. A method for identifying misalignments in an overlapping region of a stitched circuit in an integrated circuit fabrication process, comprising: creating a first circuit using a reference mask, wherein the first circuit includes a first part of an offset dependent resistor structure in the overlapping region; creating a second circuit using a secondary mask, wherein the second circuit includes a second part of the offset dependent resistor structure in the overlapping region, wherein the offset dependent resistor structure includes a plurality of nubs that interconnect the first part and the second part of the offset dependent resistor structure; measuring a resistance across the offset dependent resistor structure; and determining an amount of misalignment based on the measured resistance; wherein: one of the parts of the offset dependent resistor structure comprises a pair of open rectangular substructures, each having two open terminal points; and the other part of the offset dependent resistor structure comprises three substructures that interconnect with the open terminal points of the rectangular substructures to form a single electrical pathway when the first and second parts are superimposed.