Patent ID: 7547969
Filing Date: 2009-06-16
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first metal layer over said silicon substrate; a dielectric layer on said first metal layer and over said silicon substrate; a second metal layer on said dielectric layer; a passivation layer on said second metal layer and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact pad of said second metal layer, a second opening in said passivation layer is over a second contact pad of said second metal layer, and a third opening in said passivation layer is over a third contact pad of said second metal layer, wherein said first, second and third contact pads are aligned in a first line, wherein said second contact pad is between said first and third contact pads, and wherein said passivation layer comprises a nitride layer; a patterned metal layer on said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a fourth contact pad on said first contact pad, wherein said fourth contact pad is connected to said first contact pad through said first opening, wherein said patterned metal layer comprises a fifth contact pad connected to said second contact pad through said second opening, wherein the position of said fifth contact pad from a top perspective view is different from that of said second contact pad, and wherein said patterned metal layer comprises a sixth contact pad on said third contact pad, wherein said sixth contact pad is connected to said third contact pad through said third opening; a first metal bump on said fourth contact pad and over said first contact pad; a second metal bump on said fifth contact pad, wherein the position of said second metal bump from said top perspective view is different from that of said second contact pad; and a third metal bump on said sixth contact pad and over said third contact pad, wherein said first and third metal bumps are aligned in a second line parallel with said first line, and wherein said third metal bump comprises a gold layer, having more than 50 percent by weight of gold and having a height between 8 and 50 micrometers, over said third and sixth contact pads.