Patent ID: 6444515
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method of fabricating a semiconductor device, comprising the steps of:forming a gate electrode on a main surface of a semiconductor substrate; forming a hard mask insulating layer greater than about 120 nm thick on a top surface of said gate electrode; forming a thin insulating layer to cover said gate electrode and said hard mask insulating layer; forming a nitride stopper layer between about 40 nm and 100 nm thick directly on said thin insulating layer; forming an interlayer insulating layer to cover said nitride stopper layer; forming a contact hole that reaches said main surface and forming a sidewall nitride layer on a side surface of said gate electrode by etching said interlayer insulating layer, said nitride stopper layer, and said thin insulating layer successively, said sidewall nitride layer to have a height in a direction perpendicular to said main surface greater than a thickness of said gate electrode in said direction perpendicular to said main surface by at least 20 nm; and forming an interconnection layer in said contact hole.