Patent ID: 9099170
Filing Date: 2015-08-04
Classification: G11C

Abstract:
1. A semiconductor device comprising: a pre-signal generator configured to generate a pre-input control signal and a pre-output control signal and configured to generate a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated; and a data output portion configured to receive an input control signal provided by a first transmission line through which the pre-input control signal is transmitted, a latch pulse signal provided by a second transmission line through which the pre-latch pulse signal is transmitted, and a first output control signal provided by a third transmission line through which the pre-output control signal is transmitted, wherein the data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and wherein the data output portion shifts the first output control signal in response to the shift clock signal to generate a second output control signal.