Patent ID: 6172912
Filing Date: 2001-01-09
Classification: G11C

Abstract:
A programming method for a virtual ground type nonvolatile semiconductor memory comprising: a number of electrically data-programmable, erasable floating gate field effect transistors that are memory cells, each having a control gate, drain and source with a floating gate, arranged matrix-wise in rows and columns; a plurality of row lines, each connecting the control gates of memory cells located in one row; and a plurality of column lines, each commonly connecting the drain of the memory cell and the source of its adjacent memory cell, these memory cells constituting columns respectively, forming a virtual ground type array wherein each memory cell is adapted to have three or more number of storage states so as to store multilevel data by differentiating the amount of charge on the floating gate,the programming method being characterized in that the memory cells are programmed starting sequentially in the order of degree of the difference in charge amount in the floating gate from the erased state.