Patent ID: 8278996
Filing Date: 2012-10-02
Classification: G11C

Abstract:
1. A reference current generating circuit, comprising: an operational amplifier having one input terminal to receive a reference voltage; N first field effect transistors (N is integer) each having a gate to commonly receive an output voltage of the operational amplifier and a drain; a series circuit including a plurality of resistors connected in series and having one terminal connected to each of drains of the first field effect transistors and feed backing a voltage at one of connection points of the resistors to the other input terminal of the operational amplifier; M second field effect transistors (M is an integer not less than 2) each having a gate to commonly receive an output voltage of the operational amplifier; and a plurality of first switches to select the second field effect transistors to generate a reference current by merging current through each of the selected second field effect transistors; a third field effect transistor having a gate to receive the reference current; a sense amplifier to compare a drain current of the third field effect transistor with an input current; an automatic trimming value decision circuit to decide a trimming value so as to set a difference between the drain current and the input current to be zero; a non-volatile memory to store the trimming value determined by the automatic trimming value decision circuit; a writing control circuit to control the writing in the non-volatile memory; and a trimming control circuit to adjust a number of the second field effect transistors to be selected by the first switches based on either one of the trimming values decided by the automatic trimming value decision circuit or stored in the non-volatile memory.