Patent ID: 8598664
Filing Date: 2013-12-03
Classification: H01L

Abstract:
1. A field effect transistor comprising: a semiconductor substrate; an insulator layer on said semiconductor substrate; a semiconductor layer on said insulator layer, said semiconductor layer having a top surface and an essentially uniform thickness of less than 3 nm; a gate stack on said top surface, said gate stack having opposing sidewalls; gate sidewall spacers on said top surface adjacent to said opposing sidewalls; an epitaxial semiconductor layer on said top surface positioned laterally adjacent to said gate sidewall spacers; a channel region within said semiconductor layer aligned below said gate stack; and source/drain regions within said semiconductor, said channel region being positioned laterally between said source/drain regions, said top surface of said semiconductor layer being planar and said top surface being fully protected from silicon loss during processing such that said top surface is essentially damage-free and such that a first portion of said top surface of said semiconductor layer between said channel region and said gate stack is level with a second portion of said top surface of said semiconductor layer between said source/drain regions and epitaxial semiconductor layer.