Patent ID: 6803314
Filing Date: 2004-10-12
Classification: H01L

Abstract:
A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:providing metal lines covered by an insulating layer overlying a semiconductor substrate; depositing an organic dielectric layer overlying said insulating layer; depositing an inorganic dielectric layer overlying said organic dielectric layer wherein no etch stop layer is formed between said organic dielectric layer and said inorganic dielectric layer; etching a via pattern into said inorganic dielectric layer; etching said via pattern into said organic dielectric layer using patterned said inorganic dielectric layer as a mask; and thereafter etching a trench pattern into said inorganic dielectric layer wherein said organic dielectric layer acts as an etch stop to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.