Patent ID: 7354798
Filing Date: 2008-04-08
Classification: H01L,Y10S

Abstract:
1. A method for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers, the method comprising the steps of: providing a first wafer having a front surface and a back surface, the first wafer having devices formed in a region adjacent to the front surface thereof; forming a via in the first wafer extending from the front surface, the via being characterized by a lateral dimension at the front surface; removing material from the first wafer at the back surface thereof; forming an opening in the back surface of the first wafer, thereby exposing the via, the opening having a lateral dimension grater than said lateral dimension of the via; forming a layer of conducting material in said opening; providing a second wafer having a front surface and a back surface, the second wafer having devices formed therein adjacent to the front surface thereof; forming a stud on the front surface of the second wafer; forming a layer of bonding material on the front surface of the second wafer, the studs projecting vertically therefrom; aligning the stud to the opening in the back surface of the first wafer; and bonding the second wafer to the first wafer using the layer of bonding material, so that the stud makes electrical contact with the via, further comprising the steps of: forming a via in the second wafer extending from the front surface thereof, the via being characterized by a lateral dimension at the front surface; removing material from the second wafer at the back surface thereof; forming an opening in the back surface of the second wafer, thereby exposing the via therein, said opening having a lateral dimension greater than said lateral dimension of the via; forming a layer of conducting material in said opening; providing a third wafer having a front surface, the third wafer having devices formed therein adjacent to the front surface thereof; forming a stud on the front surface of the third wafer; forming a layer of bonding material on the front surface of the third wafer, the studs projecting vertically therefrom; aligning the stud to the opening in the back surface of the second wafer; and bonding the third wafer to the second wafer using the layer of bonding material, so that the stud of the third wafer makes electrical contact with the via of the second wafer, with the stud of the second wafer, and with the via of the first wafer.