Patent ID: 6119222
Filing Date: 2000-09-12
Classification: G06F

Abstract:
A method of operating a microprocessor to execute a program of instructions, comprising:applying a branch instruction address to a branch target buffer, the branch target buffer having a plurality of entries, each having a tag field for storing a branching instruction identifier, having a target field for storing a branch target fetch address, and having a first prefetch field for storing a first prefetch address;monitoring the execution of a sequence of instructions following a first branching instruction to detect a first instruction associated with a cache miss;associating the first detected instruction with the first branching instruction; andupdating the first prefetch field of an entry in the branch target buffer corresponding to the first branching instruction, with address and control information corresponding to the first detected instruction; andresponsive to a portion of the applied branch instruction address matching the tag field of one of the plurality of entries, applying the branch target fetch address of the matching entry to a first level cache memory, and applying the first prefetch address to a second, higher, level memory.