Patent ID: 6660618
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising a multi-layer metallization system having reduced variation of vertical capacitance, which method comprises the sequential steps of:(a) providing a substrate comprising a laterally extending surface having a plurality of spaced apart, electrically conductive features formed thereon, said plurality of features including relatively narrow and relatively wide features with relatively narrow and relatively wide spaces between adjacent features; (b) forming a first, blanket layer of a low dielectric constant (â€œlow kâ€ ) material over said substrate surface, said blanket layer filling the spaces between adjacent features and covering said features, the thickness of said blanket layer varying over said laterally extending surface and including thinner, recessed portions in the relatively wide spaces between adjacent features and thicker, non-recessed portions; (c) selectively forming a layer of an etch-resistant mask material over the thinner, recessed portions of said blanket layer; (d) selectively etching the thicker, non-recessed portions of said blanket layer of first, low k material exposed by said layer of mask material to substantially planarize the surface thereof; (e) removing the layer of etch-resistant mask material; (f) successively forming a relatively thinner layer of a second, oxide-based dielectric material and a relatively thicker layer of a third, low k material on the planarized surface of said layer of first, low k material; and (g) forming at least one via extending through said second and third dielectric material layers by an etching process.