Patent ID: 6552944
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A sense amplifier circuit for a memory array, wherein the read function is performed solely by a set of four transistors and a current source comprising:a current source coupled to a read data line to supply charge to the read data line; a first transistor having a control gate and a current path, the control gate coupled to a first bitline of the memory array, the current path coupled between the read data line and a current path of a second transistor; the second transistor having a control gate and a current path, the control gate coupled to a first read enable signal of the memory array, the current path coupled between the current path of the first transistor and a ground potential; a third transistor having a control gate and a current path, the control gate coupled to a second bitline of the memory array, the current path coupled between the read data line and a current path of a fourth transistor; the fourth transistor having a control gate and a current path, the control gate coupled to a second read enable signal of the memory array, the current path coupled between the current path of the third transistor and a ground potential; wherein the first and second read enable signals which are coupled to the control gates of the second and fourth transistors, respectively, are utilized to provide multiplexing between the first and second bitlines to the read data line during a read operation.