Patent ID: 8370642
Filing Date: 2013-02-05
Classification: H04L

Abstract:
1. A cryptographic processing apparatus comprising: at least one register configured to store data for operation; a first operation block configured to execute an operation in accordance with the data stored in said register; a second operation block configured to execute a logic operation between one of (a) a register-stored value and a key and (b) an operation result of said first operation block; and a first decode block configured to decode binary data in units of the predetermined number of bits to convert said binary data into decode data having the number of bits higher than the number of bits of said binary data, wherein an operation result of said second operation block is stored in said register, and said first decode block is arranged such that data propagating along a signal wiring: from a supply block of at least one of (a) the register-stored value and a round key and (b) said first operation block, to said second operation block is supplied in a state where binary data is decoded in units of the predetermined number of bits to be converted into decode data having the number of bits higher than the number of bits of the binary data, wherein said register includes a first register and a second register; said first decode block is arranged for decoding binary data of an input plaintext to convert into said decode data and supplying said decode data selectively to said first register and said second register; said first operation block executes an operation in accordance with data stored in said second register; said second operation block executes an exclusive-OR operation between the stored value of said first register and an operation result of said first operation block; an operation result of said second operation block is stored in said second register; and a processor and a memory device to execute the blocks.