Patent ID: 7109738
Filing Date: 2006-09-19
Classification: G01R,G11C,H01L

Abstract:
1. A partially fabricated wafer having a test structure overlying the substrate of the wafer, the test structure comprising: a first ring oscillator comprising an even number of inverters and a NAND gate having two inputs and an output, said inverters coupled in series having a first input connected to said output of said NAND gate and a final output connected to said first input of said NAND gate, whereby said first ring oscillator has a frequency of oscillation influenced by transistor characteristics and intra device parasitics; a second ring an oscillator comprising an even number of inverters, a NAND gate having two inputs and an output, a device under test (DUT) line and a passive conductor parallel to said DUT line, said inverters coupled in series having a first input connected to said output of said NAND gate and a final output connected to said first input of said NAND gate and said DUT line coupled between said output of an inverter and said input of a successive inverter, whereby said second ring oscillator has a frequency of oscillation being influenced by the transistor characteristics, intra device parasitics, resistive and capacitive parasitics of said DUT line relative to said passive conductor; and a third ring oscillator comprising an even number of inverters, a NAND gate having two inputs and an output, a device under test (DUT) line and an aggressor conductor parallel to said DUT line, said inverters coupled in series having a first input connected to said output of said NAND gate and a final output connected to said first input of said NAND gate and said DUT line coupled between said output of an inverter and said input of a successive inverter, whereby said third ring oscillator has a frequency of oscillation being influenced by the transistor characteristics, intra device parasitics, resistive, capacitive and inductive parasitics of said DUT line relative to said aggressor conductor.