Patent ID: 7679195
Filing Date: 2010-03-16
Classification: H01L

Abstract:
1. A wafer, comprising: a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits; a plurality of dielectric layers formed in the at least one scribe line having aligned process control monitor (PCM) pads formed therein; a passivation layer in the at least one scribe line between the two integrated circuits, on a topmost one of the plurality of dielectric layers and above a level of the PCM pads, and a conductive structure in the at least one scribe line between the two integrated circuits, above a topmost one of the PCM pads, the conductive structure having a first portion on the passivation layer and contacting a device under test, the first portion being continuous with a contact portion extending vertically from the first portion to contact the topmost PCM pad, the contact portion having a thickness that is small relative to a length of the topmost PCM pad, the conductive structure sized and shaped to contact and cover a minority portion of the topmost PCM pad with a majority portion of the topmost PCM pad exposed for access by a circuit probe.