Patent ID: 6272567
Filing Date: 2001-08-07
Classification: G11C

Abstract:
In a network for interfacing parallel I/O data packet information packets (PIP) source resources with I/O destination resources through a central shared memory data path comprised of a central shared multi-port internally cached DRAM memory system (AMPIC DRAM) and a separate control path therefor, and wherein each I/O resource has the capability simultaneously to receive PIP data stream traffic from all the other I/O resources, a method of eliminating PIP traffic congestion as the number of I/O resources and/or bandwidth requirements significantly increase, that comprises, interposing an AMPIC DRAM system in the control path for simultaneously absorbing and storing all PIP streams without stalling an I/O source resource incoming data stream, wherein the control path is provided for unicast traffic, and the interposed AMPIC DRAM system is separated into an AMPIC Quality of Service (QOS) memory for enabling priority control, and an AMPIC LINK memory for enabling packet re-assembly at I/O destination resources.