Patent ID: 6240038
Filing Date: 2001-05-29
Classification: G11C

Abstract:
An array write port for writing to an array of memory cells, comprising:a row decoder operably connected to a row of one or more cells to provide a row enable signal for enabling the one or more cells, the row decoder having a row address input for receiving a row address signal, a port 1 input for receiving a port 1 signal, a port 2 input for receiving a port 2 signal, and an output for generating the row enable signal in response to being selected by the row address signal and receiving one of the port 1 and port 2 signals;a write driver for writing data into the one or more cells, the write driver having port 1 and port 2 write data inputs for receiving first and second data signals, a port 1 input for receiving the port 1 signal, a port 2 input for receiving the port 2 signal, and an output for providing a write data signal in response to receiving one of the port 1 and port 2 signals, the value of the write data signal corresponding to the first data if the port 1 signal is received and corresponding to the second data if the port 2 signal is received, the write driver output being operably connected to at least one of the one or more cells for writing the write data value therein when the row enable signal is generated; anda pulse generator operably connected to the row decoder and write driver for providing the port 1 and port 2 signals, the pulse generator having a clock input for receiving a clock signal with first and second phases, wherein the pulse generator generates the port 1 signal in the first clock phase and generates the port 2 signal in the second clock phase.