Patent ID: 8765542
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A method, comprising: forming a gate structure of a transistor above a surface of a semiconductor substrate, said gate structure being comprised of at least one layer of metal, a silicon-containing layer of material positioned above said at least one layer of metal and a protective cap layer positioned above the silicon-containing layer of material; forming a sidewall spacer proximate said gate structure; after forming said sidewall spacer, forming a sacrificial layer of material above said protective cap layer, above said sidewall spacer and above said semiconductor substrate; forming an OPL layer above said sacrificial layer; reducing a thickness of said OPL layer such that, after said reduction, an upper surface of said OPL layer is positioned at a level that is below a level of an upper surface of said protective cap layer; with said OPL layer in position, performing a first etching process to remove said sacrificial layer from above said protective cap layer to thereby expose said protective cap layer for further processing; performing at least one second etching process to remove said protective cap layer; and after removing said protective cap layer, performing at least one process operation to remove at least one of said OPL layer or said sacrificial layer from above said surface of said semiconductor substrate.