Patent ID: 6808989
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A method of fabricating a stacked gate region comprising:providing a substrate having at least one semiconductor layer; forming a tunnel oxide layer over said substrate; forming a first polysilicon layer over said tunnel oxide layer; forming a nitride layer over said first polysilicon layer; masking selected areas of said first polysilicon layer; etching unmasked areas of said first polysilicon layer leaving at least one floating gate layer; patterning trench areas in the substrate; depositing field oxide in said trench areas sequentially after said patterning; performing planarization to planarize a surface of said stacked gate region; performing an oxide etch back to remove selected amounts of said field oxide; removing said nitride layer before depositing a second polysilicon layer; and depositing said second polysilicon layer over said substrate and removing selected portions of said second polysilicon layer so as to leave polysilicon wings formed adjacent to said at least one floating gate layer and having a side in contact with a portion of said field oxide.