Patent ID: 6510472
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A buffer circuit coupling an input bus having a first portion and a second portion to an output bus, each of the first portion, the second portion, and the output bus carrying data of a predetermined width, the buffer circuit comprising:a first plurality of registers coupled to store data from the first portion of the input bus; a second plurality of registers coupled to store data from the second portion of the input bus and from a data order signal; an unload counter that provides an unload count that selects one of the first plurality of registers and a corresponding one of the second plurality of registers; and a multiplexer that provides either the selected one of the first plurality of registers or the corresponding one of the second plurality of registers to the output bus, the multiplexer responsive to the data order signal stored in the corresponding one of the second plurality of registers.