Patent ID: 8101989
Filing Date: 2012-01-24
Classification: H01L

Abstract:
1. A memory cell comprising: a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region; a multilayer stack over the channel including a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, and a top dielectric structure disposed above the charge trapping structure and above the channel region; and a word line disposed above the top dielectric structure and above the channel region; wherein the conductive layer in the multilayer stack has an area over the channel region equal within manufacturing limitations to an area of the channel re ion beneath the word line and between the source and drain.