Patent ID: 7439120
Filing Date: 2008-10-21
Classification: H01L

Abstract:
1. A method for fabricating a stress enhanced MOS circuit, the method comprising the steps of: depositing a layer of polycrystalline silicon gate forming material onto a layer of gate insulator; etching the layer of polycrystalline silicon gate forming material to form a polycrystalline silicon gate structure overlying the layer of gate insulator; depositing a stress liner layer in contact with the polycrystalline silicon gate structure formed from the layer of polycrystalline silicon gate forming material; planarizing the stress liner layer to expose a top portion of the polycrystalline silicon gate structure; etching the polycrystalline silicon gate structure to remove a first portion of the polycrystalline silicon gate structure, leaving a second portion of the polycrystalline silicon gate structure in contact with the gate insulator, and leaving an etched void bounded in part by the stress liner layer; filling the void with an electrically conductive stressed material, wherein the electrically conductive stressed material contacts the polycrystalline silicon gate structure; and planarizing a surface of the electrically conductive stressed material.