Patent ID: 8797801
Filing Date: 2014-08-05
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device comprising: a first memory string including a first memory cell and a second memory cell; a second memory string including a third memory cell and a fourth memory cell; a first word line electrically connected to a gate of the first memory cell and a gate of the third memory cell; a second word line electrically connected to a gate of the second memory cell and a gate of the fourth memory cell; a bit line electrically connected to one end of the first memory string and one end of the second memory string; a first source line electrically connected to the other end of the first memory string; a second source line electrically connected to the other end of the second memory string; and a control circuit configured to perform a read operation for the first memory cell on the condition that a first voltage is applied to the first word line, a second voltage is applied to the second word line, a third voltage is applied to the bit line, a fourth voltage is applied to the first source line, a fifth voltage is applied to the second source line, the second voltage is higher than the first voltage and the fourth voltage is different from the fifth voltage, wherein the non-volatile semiconductor memory device includes a plurality of memory cells, the plurality of memory cells being stacked above a semiconductor substrate, the plurality of memory cells including the first memory cell, the second memory cell, the third memory cell and the fourth memory cell.