Patent ID: 6020871
Filing Date: 2000-02-01
Classification: G09G

Abstract:
A bidirectional scanning circuit comprising:a plurality of switching means controlled to be turned ON and OFF by a clock signal and mutually connected in series;a plurality of feedback means connected to respective series connecting points of respective of said switching means and being controlled activation by said clock signal, for preventing attenuation of amplitude of branched signals at respective series connecting points;a plurality of buffer means for inputting outputs of said feedback means;a plurality of logic gate means for inputting outputs of a (J)th (J is natural number) and (J+1)th buffer means;first and second input/output terminals for inputting and outputting a start pulse for initiation of scanning;assuming sequential K (K is an integer greater than or equal to 6) in number of series connecting points of said switching means being N(1) to N(K-1) from the ends and assuming that the terminals at both ends are N(0) and N(K),first direction shifting input means connected between said first input/output terminal and a terminal of N(L)th order (L is an integer of 0.ltoreq.L.ltoreq.K-6);second direction shifting output means connected between said first input/output terminal and a terminal of N(R)th order (R is an integer of 0.ltoreq.R.ltoreq.K-6);second direction shifting input means connected between said second input/output terminal and a terminal of N(M)th order (M is an integer of 6.ltoreq.M.ltoreq.K);first direction shifting output means connected between said second input/output terminal and a terminal of N(Q)th order (Q is an integer of 6.ltoreq.Q.ltoreq.K, .vertline.L-Q.vertline.=.vertline.R-M.vertline.); anda plurality of scanning output terminals leading out respective output pulses of said logic gate means of G(L+1) to G(M-2) as taking said logic gate means as G(1) to G(K-1) in sequential order from said end.