Patent ID: 7585763
Filing Date: 2009-09-08
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit transistor comprising: forming in an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon; selectively forming an implant-blocking mask on the second active area; implanting extension dopants into the first active area on opposite sides of the first insulated gate to form source and drain extension regions while the implant-blocking mask blocks the dopants from the second active area; forming an anti-reflective coating on the first active area; directionally etching the anti-reflective coating on the first active area to form anti-reflective coating sidewall spacers on opposite sidewalls of the first insulated gate, while retaining the implant-blocking mask on the second active area; implanting source/drain dopants into the first active area on opposite sides of the first insulated gate to form source and drain regions while the implant-blocking mask blocks the source/drain dopants from the second active area and the anti-reflective coating sidewall spacers block at least some source/drain dopants from the first active area beneath the anti-reflective coating sidewall spacers and the source and drain extension regions remain beneath the anti-reflective coating sidewall spacers; and removing the implant-blocking mask and the anti-reflective coating sidewall spacers.