Patent ID: 7247525
Filing Date: 2007-07-24
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of conductor layers on a substrate comprising a first insulation layer, a second insulation layer and a third insulation layer, selectively removing said third insulation layer, said second insulation layer and said first insulation layer to form a through hole, depositing a conductive material to form a first conductor film and to cover internal walls of said through hole, and plating copper over said first conductor film to form a second conductor film as a conductor wiring, and disposing a third insulation layer of a conductor layer positioned at a lower-layer part among said conductor layers to serve as a first insulation layer of a conductor layer positioned at an upper-layer part adjacent to said conductor layer positioned at a lower-layer part, and forming said second insulation layer of a conductor layer positioned at a lower-layer part among said conductor layers as to have a dielectric constant smaller than that of a conductor layer positioned at an upper-layer part among said conductor layers.