Patent ID: 6335251
Filing Date: 2002-01-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed, comprising the steps of:forming a gate electrode on a silicon substrate through a gate insulating film; forming a first insulating film on the overall surface to cover the gate insulating film and the gate electrode; forming, on the first insulating film, a second insulating film made of a material which is different from the first insulating film; etching the overall surface of the second insulating film by using the first insulating film to serve as an etching stopper so as to selectively leave the second insulating film on the side wall of the gate electrode; removing the first insulating film in a region which is not covered with the second insulating film by etching and selectively leaving the first insulating film between the second insulating film and the silicon substrate; epitaxial-growing silicon in a state in which the surface of the silicon substrate around the first and second insulating films is exposed to form, on the silicon substrate around the first and second insulating films, a silicon film free from any facet in, a portion which is made contact with the second insulating film; implanting ions of impurities into the surface of the silicon substrate through the silicon film and performing annealing to form a source diffusion layer and a drain diffusion layer on the surface of the silicon substrate; and converting at least the surface portion of the silicon film into a metal silicide film.