Patent ID: 8421139
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A transistor comprising: a buried oxide layer above a substrate; a silicon layer above the buried oxide layer; a first fin structure and at least a second fin structure on the substrate; a deep trench area between the first fin structure and second fin structure, wherein the deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate that is below the insulator layer; a high-k metal gate within the deep trench area, wherein the high-k metal gate comprises a high-k dielectric layer and a metal layer; a polysilicon layer within the deep trench area adjacent to the metal layer, wherein the polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer; a poly strap in the deep trench area on top of the high-k metal gate and the polysilicon material, wherein the poly strap is dimensioned to be below a top surface of the first fin structure and the second fin structure, wherein the first fin structure and the second fin structure are electrically coupled to the poly strap.