Patent ID: 8330484
Filing Date: 2012-12-11
Classification: G01R

Abstract:
1. An integrated circuit comprising: an output port comprising an integrated circuit debug port including output contacts for coupling the integrated circuit to external equipment via external connectors, the output port receiving a plurality of internal operational signals generated during operation of the integrated circuit on a plurality of busses, the operational signals routed to the output contacts for connection of the operational signals to external equipment via the external connectors; a connection test signal store dynamically loadable with output contact test pattern signals generated by the integrated circuit; means for selecting operational signals from the integrated circuit or test pattern signals from the connection test signal store for passing to the output port, wherein upon selection of the test patterns from the connection signal store the external equipment monitors the integrity of electrical connections between each of the output contacts and the external connectors by detecting expected transitions in each signal of the test pattern signals as successive transitioning test signal sequences that are dynamically loaded for testing integrity of the electrical connections.