Patent ID: 6391741
Filing Date: 2002-05-21
Classification: B81C,G11B,H01L

Abstract:
A process for assembling a group of elements having at least one first element and one second element, said first element including a microstructure without package, the process comprising:forming a first wafer of semiconductor material comprising a plurality of microstructures including first and second operating regions separated from each other by first trenches, forming a second wafer of semiconductor material comprising blocking regions connecting a plurality of first and second intermediate regions, said first and second intermediate regions separated from each other by second trenches; joining said first wafer and second wafer to form a composite wafer wherein said first operating regions are fixed to said first intermediate regions, and said second operating regions are fixed to said second intermediate regions; cutting said composite wafer into a plurality of units, each unit including at least one first operating region and one second operating region, and one first intermediate region and one second intermediate region; fixing said first intermediate region of at least one unit to said second element; and removing said blocking regions.