Patent ID: 7046093
Filing Date: 2006-05-16
Classification: H03L,Y10S

Abstract:
1. A phase locked loop (PLL) circuit, comprising: a controlled oscillator circuit operative to generate an output clock signal responsive to an oscillator control voltage according to a plurality of selectable transfer functions; an oscillator control signal generator circuit that generates the oscillator control signal responsive to the output clock signal and a reference clock signal, wherein the oscillator control signal generator circuit comprises: a transfer function control circuit operative to transition operation of the controlled oscillator circuit from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control voltage, wherein the transfer function control circuit is operative to transition operation of the controlled oscillator circuit from the first transfer function to the second transfer function responsive to a voltage range criterion for the oscillator control voltage and wherein the transfer function control circuit is operative to enable and disable the charge pump circuit based on the voltage range criterion for the oscillator control voltage.