Patent ID: 8395929
Filing Date: 2013-03-12
Classification: G11C

Abstract:
1. A device, comprising: an integrated circuit die including a front-end-of-the-line (FEOL) portion and a back-end-of-the-line (BEOL) portion, the BEOL portion is integrally fabricated directly above and in contact with the FEOL portion, the FEOL portion comprises a silicon substrate including active circuitry; a plurality of first and second conductive array lines configured in a two-terminal cross-point array that is disposed in the BEOL portion, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry; a read voltage generator included in the active circuitry and configured to apply a read voltage to a selected one of the plurality of first conductive array lines; a bias element included in the active circuitry and configured to generate a bias signal that is applied to a remainder of the plurality of first conductive array lines; a switch included in the active circuitry and configured to apply a pre-charge voltage to the plurality of second conductive array lines, to disconnect the pre-charge voltage from the plurality of second conductive array lines, and to connect a floating voltage potential to the plurality of second conductive array lines after disconnecting the pre-charge voltage; sense amp circuitry included in the active circuitry and configured to sense a current flowing through each of the plurality of second conductive array lines; compare circuitry included in the active circuitry and configured to compare the current flowing through each of the plurality of second conductive array lines with at least one reference signal; and read data circuitry included in the active circuitry and configured to generate read data for each of the plurality of second conductive array lines based on the comparing.