Patent ID: 6239367
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A multi-chip chip scale package, comprising:a film carrier, further comprising:an insulation film, wherein the insulation film comprises a peripheral region and an inter-layer region and the inter-layer region isolates a hollow region enclosed by the peripheral region into a plurality of chip disposing regions; anda plurality of conductive wires, arranged on the insulation film both in the peripheral region and the inter-layer region;a plurality of chips, respectively disposed over the chip disposing regions and the hollow region respectively on each side of the insulation film with inner surfaces respectively located over the chip disposing regions face to the inner surface of the chip located over the hollow region and each of the inner surfaces of the chips having a plurality of bumps respectively connecting with the conductive wires respectively disposing on the peripheral region and the inter-layer region of the isolation film;at least a circuit component, on the film carrier and electrically connected to the conductive wires; andan insulation material, filled in between the chips to seal the inner surfaces, while the chips have their outer surfaces exposed.