Patent ID: 7506107
Filing Date: 2009-03-17
Classification: G06F

Abstract:
1. A shared memory multiprocessor system in which a plurality of nodes mutually connected to one another via an internode link share data; wherein: each of said nodes includes: one or more pieces of processors equipped with a cache memory; a main memory; a chip set; a front side bus for connecting said processor to said chip set; and a main memory bus for connecting said main memory to said chip set, said chip set includes: a front side bus control unit; a coherency control unit; a main memory bus control unit; an internode link control unit; and a cache tag for holding a data cache status of the cache memory provided in the processor connected to said front side bus, said front side bus control unit includes: a circuit for transmitting a data reading access, a data write-back access, and a cache snoop response to said coherency control unit, which are received from the processor via said front side bus; a circuit for transmitting the cache snoop access via said front side bus to the processor, which is received from said coherency control unit; and a circuit for transmitting read data via said front side bus to the processor, which is received from said intermode link control unit in accordance with data reply notification received from said coherency control unit, said main memory bus control unit includes: a circuit for transmitting a data reading access and a data write-back access via said main memory bus to a main memory, which are received from said internode link control unit; a circuit for transmitting data write-back completion notification to said internode link control unit in correspondence with the transmission of said data write-back access to said main memory; and a circuit for transmitting the read data to said internode link control unit, which is received via said main memory bus from said main memory, said internode link control unit includes: a circuit for broadcasting both the data reading access received from said coherency control unit and the data write-back completion notification received from said main memory bus control unit to the nodes via said internode link; a circuit for transmitting both the data write-back access and the data re-reading access, which are received from said coherency control unit, via said internode link to a node equipped with a main memory which stores thereinto data of a subject address, and also for transmitting the read data received from said main memory bus control unit via said internode link to a node which issued a subject data reading access; a circuit for transmitting the coherency response received from said coherency control unit via said internode link to a node equipped with the coherency control unit which has transmitted the data reading access; a circuit for selecting the data reading accesses from the nodes via said internode link in synchronism with the nodes so as to order the selected data reading accesses; a circuit for selecting the data writing completion notification received from the nodes via said internode link in synchronism with the nodes so as to order the selected data writing completion notification; a circuit for comparing a subject address of said ordered data reading access with a subject address of said ordered data writing completion notification and for adding the comparison result to the data reading access; a circuit for transmitting said data reading access to which said comparison result is added to both said coherency control unit and said main memory control unit; a circuit for transmitting said ordered data writing completion notification to said coherency control unit; a circuit for transmitting the read data to said front side control unit, which are received from the nodes via said internode link; a circuit for transmitting both the data write-back accesses and the data re-reading accesses to said main memory control unit, which are received from the nodes via said internode link; and a circuit for transmitting the coherency responses to said coherency control unit, which are received from the nodes via said internode link, and wherein: said coherency control unit includes: a circuit for transmitting the data reading access and the write-back access to said internode link control unit, which are received from said front side bus control unit; a circuit for referring to said cache tag from the subject address of the data reading access to which said comparison result is added and which is received from said internode link control unit so as to judge a data cache state of the processor connected to said front side bus; a circuit for transmitting a cache snoop access to said front side bus control unit in accordance with the judgment of said data cache state; a circuit for producing a coherency response by combining said data cache state with the cache snoop response received from said front side bus control unit, and for transmitting the produced coherency response to said internode link control unit; a circuit for producing data reply notification in accordance with the coherency response received from the internode link control unit so as to transmit said produced data reply notification to said front bus control unit, and for producing a data re-reading access so as to transmit the produced data re-reading access to said internode link control unit; and a circuit for completing the transmitted data write-back in accordance with the data write-back completion notification received from said internode link control unit.