Patent ID: 6369630
Filing Date: 2002-04-09
Classification: G11C

Abstract:
A single event upset (SEU) hardened integrated circuit comprising:an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state, the latch comprising: a first CMOS inverter including a first p-channel field effect transistor, a first n-channel field effect transistor, and a first data node located between the first p-channel transistor and the first n-channel transistor; a second CMOS inverter including a second p-channel field effect transistor, a second n-channel field effect transistor and a second data node located between the second p-channel field effect transistor and the second n-channel field effect transistor, wherein the first CMOS inverter is cross-coupled to the second CMOS inverter via a first coupling segment and a second coupling segment, wherein the first coupling segment and the second coupling segment are not within the first CMOS inverter and the second CMOS inverter, wherein the first p-channel field effect transistor is symmetric with the second p-channel field effect transistor, and wherein the drain area of the first n-channel transistor is greater than the drain area of the second n-channel transistor resulting in the first data node having a first nodal capacitance and the second data node having a second nodal capacitance asymmetric with the first nodal capacitance; an SEU hardening component operably positioned within the first coupling segment or the second coupling segment of the latch, wherein the SEU hardening component is a thin film resistor; and a supply voltage operably coupled to the asymmetric bi-stable latch, wherein upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state.