Patent ID: 6961888
Filing Date: 2005-11-01
Classification: H03M

Abstract:
1. An apparatus for performing low density parity check encoding operations, the apparatus comprising: memory including a set of memory locations for storing L Z-bit vectors, where Z is a positive integer greater than one and L is a positive integer; a vector unit operation processor including a circuit for performing Z parity calculations in parallel to compute a Z-bit vector, each bit of the computed Z-bit vector being generated by one of the Z parity calculations, an accumulator for storing the computed Z-bit vector, and an output device for passing the computed Z-bit vector to said memory; and a reordering device coupled to the memory and to the vector unit operation processor, the reordering device for passing Z-bit vectors between said memory and said vector unit operation processor and for performing a bit level reordering operation on elements of at least one Z-bit vector, in response to reordering control information, as the at least one Z-bit vector is passed between said memory and said vector unit operation processor by said reordering device.