Patent ID: 8640063
Filing Date: 2014-01-28
Classification: G06F

Abstract:
1. A computer-implemented method for synthesizing soft error tolerant combinational circuits, comprising the steps of: inputting an original gate level combinational circuit; specifying a maximum number of inputs M to the original gate level circuit; extracting smaller sub-circuits from the original gate level circuit based on the maximum number of inputs M and subject to constraints of limiting the number of inputs M for a feasible running time, limiting the number of outputs per each extracted circuit to 1, restricting for each extracted sub-circuit the number of fan-outs to other circuits to zero; returning a list of the extracted sub-circuits subject to the constraints; determining a number of controllability don't care (CDC) conditions for each sub-circuit in the list, thereby discovering a set of care minterms for each extracted sub-circuit; computing, via simulation, the probability of each care minterm to occur for each extracted sub-circuit; producing a new multi-level sub-circuit from each of the extracted sub-circuits; maximizing logical fault masking against the occurrence of a single fault applied to each of the new multi-level sub-circuits, wherein the maximizing is based on the computed probabilities; and merging the new multi-level sub-circuits back to the original inputted gate level combinational circuit.