Patent ID: 6598146
Filing Date: 2003-07-22
Classification: G06F

Abstract:
A data-processing arrangement comprising:a plurality of elementary circuits including processing circuits (PRC) and memory circuits (MEM), a controller (MCP) that is programmed to successively apply, in response to a task-initialization data (TID), control data to different subsets of elementary circuits so as to cause the data-processing arrangement to process a block of data (DB) in accordance with a certain data-processing chain (DPC) whereby each subset of elementary circuits implements a different element (E) of the data-processing chain (DPC); wherein the controller (MCP) comprises a control processor (CPU) and a control memory (CMEM), the control memory (CMEM) comprising: a collection of subroutines (SR), each subroutine corresponding to an element (E) of a data-processing chain (DPC) and causing the control processor (CPU) to apply control data (CD) to a subset of elementary circuits (PRC/MEM) which, in response, will carry out the element (E) of the data-processing chain (DPC) concerned, each subroutine (SR) that relates to an element (E) of the data-processing chain (DPC) which is succeeded by another element (E) further causing the control processor (CPU) to write a pointer (P) in a task-continuation file (TCF), the pointer (P) indicating the subroutine (SR) that relates to the subsequent element (E) of the data-processing chain (DPC) concerned; and a basic control program (KRNL) that repetitively causes the control processor (CPU) to read a new task-initialization data (RD(TID), which indicates a subroutine (SR) that relates to a first element of a data-processing chain (DPC), to read the pointers that are contained in the task-continuation file (RD(PETCF) and to execute the subroutines indicated by said new task-initialization data and said pointers (EXEC (SR)).