Patent ID: 6480432
Filing Date: 2002-11-12
Classification: G11C

Abstract:
A flash memory device comprising:a memory cell array having a plurality of memory cell blocks, each memory cell block having cells arranged in rows and columns, each row including a word line coupled to a plurality of EPROM cells, each column including a bit line coupled to a plurality of EPROM cells, one of said memory cell blocks being selected by block selection signals, contents of EEPROM cells coupled to a selected word line being read on respective bit lines; a mask ROM cell array having a plurality of mask ROM cell rows and a plurality of mask ROM cell columns, each mask ROM cell row arranged in each memory cell block, different mask ROM cell rows having different contents to each other, each mask ROM cell column having transfer gates coupled to a bit line, each mask ROM cell row including a word line coupled to said transfer gates; a mask ROM cell row selecting circuit, arranged for each mask ROM cell row, for making said transfer gates, which are in said memory cell block corresponding to an activated one of said block selection signals, on-state when a test mode signal is active; and a word decoder, arranged for each memory cell block, for activating one of said word lines in response to input signals of predecoded address when said test mode signal is inactive and corresponding block selection signal is active and for inactivating all said word lines when said test mode signal is active.