Patent ID: 6696876
Filing Date: 2004-02-24
Classification: H03K

Abstract:
A clock interpolation circuit, comprising:a first plurality of capacitors coupled to an output node of the circuit and selectively coupled in parallel; a first plurality of switches coupled in series with the first plurality of capacitors, each switch of the first plurality of switches having an open position and a closed position and each switch having a first end coupled to a first clock with a first phase and a second end coupled to a capacitor of the first plurality of capacitors, the first plurality of switches controlled by a plurality of control signals that affect the position of each of the first plurality of switches; a second plurality of capacitors coupled to the output node of the circuit and selectively coupled in parallel; a second plurality of switches coupled in series with the second plurality of capacitors, each switch of the second plurality of switches having an open position and a closed position and each switch having a first end coupled to a second clock with a second phase and a second end coupled to a capacitor of the second plurality of capacitors, the second plurality of switches controlled by a plurality of control signals that affect the position of each of the second plurality of switches, wherein the output node provides an interpolated output clock having a phase determined by a ratio of a first capacitance of selected capacitors from the first plurality of capacitors and a second capacitance of selected capacitors from the second plurality of capacitors, an amplifier configured to accept the interpolated clock; and a circuit configured to set a common mode voltage at differential inputs of the amplifier.