Patent ID: 8689156
Filing Date: 2014-04-01
Classification: G06F

Abstract:
1. A method of generating a hardware design for a pipelined parallel stream processor, the method comprising: defining, on a computing device, a processing operation designating processes to be implemented in hardware as part of the pipelined parallel stream processor; defining, on a computing device, a graph representing the processing operation as a parallel structure in the time domain as a function of clock cycles, the graph comprising at least one data path to be implemented as a hardware design for the pipelined parallel stream processor and comprising a plurality of parallel branches configured to enable data values to be streamed therethrough, the or each data path being represented as comprising at least one input, at least one output, at least one discrete object corresponding directly to a hardware element to be implemented in hardware as part of the pipelined parallel stream processor, the or each discrete object being operable to execute a function for one or more clock cycles and having a predefined latency associated therewith, the predefined latency representing the time required for the hardware element to execute the function, the data values propagating through the data path from the at least one input to the at least one output as a function of increasing clock cycle; defining, on a computing device, the at least one data path and associated latencies of the graph as a set of algebraic linear inequalities; collectively solving, on a computing device, the set of linear inequalities for the entire graph; using, on a computing device, the solved linear inequalities to improve the scheduling of the at least one data path in the graph to produce an improved graph; inserting buffering into at least some of the branches of the data path; merging two or more buffers into a single buffer or allocating a single buffer to two or more branches of the at least one data path; and utilizing, on a computing device, the improved graph to define an improved hardware design for implementation in hardware as the pipelined parallel stream processor.