Patent ID: 7489546
Filing Date: 2009-02-10
Classification: G11C

Abstract:
1. A NAND memory array, comprising: an array of non-volatile memory cells arranged in rows and columns, each memory cell comprising a field-effect transistor capable of being programmed to have one of two or more mutually exclusive ranges of threshold voltages; a plurality of bit lines selectively coupled to columns of the memory cells; and a plurality of word lines coupled to rows of the memory cells; wherein the columns of the memory cells are further grouped into a plurality of strings of memory cells; wherein a first string of the memory cells of the plurality of strings of memory cells comprises a plurality of memory cells coupled source to drain; wherein a first memory cell of the first string of memory cells has a source/drain region coupled only to a first source/drain region of a first select gate; wherein a last memory cell of the first string of memory cells has a source/drain region coupled only to a first source/drain region of a second select gate; wherein the first select gate has a remaining source/drain region coupled to a first bit line of the plurality of bit lines; and wherein the second select gate has a remaining source/drain region coupled to the first bit line.