Patent ID: 7471111
Filing Date: 2008-12-30
Classification: H03K

Abstract:
1. A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node, comprising: a PMOS transistor having a source connectable to a first one of two terminals of a power supply, having a gate, and having a drain connected to the output node, the PMOS transistor also having a first parasitic capacitance between its gate and drain, the first parasitic capacitance having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions; an NMOS transistor having a source connectable to a second of the two terminals of the power supply, having a gate, and having a drain connected to the output node, the NMOS transistor also having a second parasitic capacitance between its gate and drain, the second parasitic capacitance having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions; a first current source arranged to generate a first current having a level corresponding to the value of the first parasitic capacitance, and to provide the first current to the gate of the PMOS transistor; a second current source arranged to generate a second current having a level corresponding to the value of the second parasitic capacitance and to provide the second current to the gate of the NMOS transistor; a level shifter arranged to receive an input signal having a voltage varying in a first range and to provide a first output signal to the gate of the PMOS transistor varying in a second range suitable for the PMOS transistor and to provide a second output signal to the gate of the NMOS transistor varying in a third range suitable for the NMOS transistor; a first clamping transistor having a source connectable to the first terminal of the power supply, and having a drain and a gate both connected to the gate of the PMOS transistor; and a second clamping transistor having a source connectable to the second terminal of the power supply, and having a drain and a gate both connected to the gate of the NMOS transistor.