Patent ID: 6288422
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A 6F.sup.2 memory cell structure comprising:a plurality of capacitors each located in a separate trench in a substrate;a plurality of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor;a plurality of isolation troughs in a striped pattern about said transistors, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts;a respective wordline electrical contact connected to each respective gate conductor; anda bitline contacted to each bitline diffusion, wherein said bitline diffusion has a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.