Patent ID: 6169694
Filing Date: 2001-01-02
Classification: G01R

Abstract:
A circuit for conducting a fully on-chip wafer level burn-in test for a chip, comprising: a high voltage generating unit for receiving an external power supply voltage and generating a high voltage for gate oxide film failure screening for a cell in response to said received external power supply voltage; a pad on-chip unit for detecting a wafer burn-in signal and generating a wafer burn-in test mode entry signal upon detecting said wafer burn-in signal; a bit line pre-charge voltage generating unit for generating a bit line pre-charge voltage for said gate oxide film failure screening for said cell in response to said wafer burn-in test mode entry signal output from said pad on-chip unit; and a cell plate voltage generating unit for generating a cell plate voltage for capacitor failure screening for said cell in response to said wafer burn-in test mode entry signal.