Patent ID: 6032231
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A system for arranging and operating a multiprocessor computer server system having a ""split-transaction bus"" architecture, said multiprocessor computer server system including a plurality of bus module means operating with a bus cycle split into an address phase and a data phase, and arranged for access by at least one resource means, the resource means including requesting processor means, to facilitate ""RETRY"", said system also including:Cache Tag means and Address Compare means, wherein said system isarranged so that a first of said plurality of bus module means stores address for said Resource means in a Cycle Tag means;means for comparing a further address corresponding to at least one subsequent address bus cycle to the address stored in the Cache Tag means; andmeans for sending a ""RETRY"" direction to any other bus module means requesting access, as indicated when the address stored in the Cache Tag matches the further address, wherein said storing is effected when said Resource means completes the address phase, and wherein said Cache Tag means is arranged to support ""cacheable lock"" means arranged to perform load READ, WRITE sequences, including modifications thereof.