Patent ID: 7778068
Filing Date: 2010-08-17
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of word lines; a first bit line crossing the plurality of word lines; a plurality of memory cells provided at intersections of the plurality of word lines and the first bit line; a read voltage supply circuit supplying a first voltage to read out information from one of the plurality of memory cells at a read operation from the plurality of memory cells; and a write voltage supply circuit supplying the first voltage to rewrite information to one of the plurality of memory cells at a rewrite operation to the plurality of memory cells, wherein each of the plurality of memory cells has a tunneling magneto-resistance, which has a tunneling film, a fixed layer, and a free layer, and a MOSFET whose gate is connected to a corresponding one of the plurality of word lines; wherein the tunneling film is provided between the fixed layer and the free layer, wherein a spin in the free layer rewrites information utilizing spin transfer torque, and wherein a time period of flowing current in the tunneling magneto-resistance at the read operation from the plurality of memory cells is shorter than a time period of flowing current in the tunneling magneto-resistance at the rewrite operation to the plurality of memory cells.