Patent ID: 6820257
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A method of compiling a source program to produce hardware, including the steps of:(a) carrying out data flow analysis of the source program to produce a data flow representation of the source program, which data flow representation comprises a number of multipliers each arranged to accept first and second input arguments having first and second input bit widths respectively, and to produce an output having an output bit width; (b) optimising the data flow representation so that said input bit widths and output bit width are minimised, even if this results in the input bit widths and output bit width not all being the same for some or all of said multipliers; and (c) carrying out high level synthesis on the optimised data flow representation, including sharing functional units, having input and output bit widths, between said multipliers in such a way that the area of silicon required to produce said functional units is minimised, even if this results in said functional unit input and output bit widths not all being the same.