Patent ID: 7702840
Filing Date: 2010-04-20
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a core for tiling a portion of the integrated circuit with a first version of the core and a second version of the core, the core being an application specific circuit version of an interface device; the first version and the second version in combination having a sharable physical interface; each of the first version and the second version having N lanes; the N lanes coupled to a same physical layer-side bus of the sharable physical interface; the first version of the core and the second version of the core each having a physical layer module coupled to the same physical layer-side bus; the first version being a primary version and the second version being a secondary version responsive to a shared interface mode; and the N lanes of the second version and the N lanes of the first version are available to the first version of the core via the physical layer-side bus of the sharable physical interface, wherein the N lanes of the second version and the N lanes of the first version provide a 2-by-N lane physical layer interface to the first version in the shared interface mode.