Patent ID: 8860121
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; an element isolation insulator disposed in an upper layer portion of the semiconductor substrate and partitioning the upper layer portion into a semiconductor region; a gate electrode provided on a part of an area immediately above the semiconductor region; a gate insulating film provided between the semiconductor region and the gate electrode; a source region formed in the semiconductor region; and a drain region formed in the semiconductor region, a region of the semiconductor region immediately below the gate electrode being located between the source region and the drain region, a width in a direction to the drain region from the source region of a lower portion of the semiconductor region that does not include the source region and the drain region, and that is below an upper portion including the source region and the drain region, being smaller than a width in the direction to the drain region from the source region of the upper portion to form concavities at the lower portion.