Patent ID: 7719313
Filing Date: 2010-05-18
Classification: H03K

Abstract:
1. A buffer circuit comprising: a first differential signal input node; a second differential signal input node; a first differential signal output node; a second differential signal output node; a first field effect transistor (FET) having a source, a drain and a gate, wherein the gate is coupled to the first differential signal input node, and wherein the source is directly coupled to the first differential signal output node; a second field effect transistor (FET) having a source, a drain and a gate, wherein the drain is coupled to the drain of the first FET, wherein the gate is coupled to the second differential signal input node, and wherein the source is directly coupled to the second differential signal output node; and a latch having a first input node and a second input node, wherein the first input node of the latch is the first differential signal output node, and wherein the second input node of the latch is the second differential signal output node, wherein the latch further comprises: