Patent ID: 7067419
Filing Date: 2006-06-27
Classification: H01L

Abstract:
1. A method for avoiding effects due to a misalignment that may occur between features in an interconnect structure of a semiconductor device, the interconnect structure having a dielectric material deposited over an underlying interconnect layer and having a via extending through the dielectric material for establishing a connection between an underlying conductor and a trench in an upper portion of the dielectric material, said method comprising the steps of: (a) forming a mask layer over the dielectric material, said mask layer comprising at least two pairs of mask films; (b) etching the mask layer to a first predetermined depth forming a via within the mask layer without exposing the underlying dielectric material; (c) etching the mask layer to a second predetermined depth of the mask layer less than the first predetermined depth forming a trench within the mask layer without exposing the underlying dielectric material; (d) in the event a misalignment occurs between the via and the trench within said mask layer, removing from the via within said mask layer a material left in said via due to said misalignment, thereby restoring the via within said mask layer to its original size; (e) forming a via through the dielectric material to the underlying conductor corresponding to the dimensions of the via formed within the mask layer; and (f) forming a trench in the dielectric material to a predetermined depth of the dielectric material corresponding to the dimensions of the trench formed within the mask layer, thereby ensuring dimensional correspondence of the via and trench in the dielectric material to the via and trench within the mask layer notwithstanding the occurrence of said misalignment.