Patent ID: 8581408
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A semiconductor device having a plurality of insulating layers and a plurality of wiring layers layered in an alternating fashion in the semiconductor device, the semiconductor device comprising: two wiring layers, including an upper-side wiring layer and a lower-side wiring layer, that are layered so as to sandwich one of the insulating layers; a first upper-side wiring path formed in the upper-side wiring layer; a first lower-side wiring path formed in the lower-side wiring layer so as to face said first upper-side wiring path while sandwiching a first section of said one of the insulating layers between said first upper-side wiring path and said first lower side wiring path, a wiring width of said first upper-side wiring path being smaller than a wiring width of the first lower-side wiring path; a second upper-side wiring path formed adjacent to said first upper-side wiring path; and a second lower-side wiring path formed adjacent to said first lower-side wiring path and facing said second upper-side wiring path while sandwiching a second section of said one of the insulating layers between said second upper-side wiring path and said second lower-side wiring path, a wiring width of said second upper-side wiring path being greater than a wiring width of the second lower-side wiring path, wherein the wiring width of said second upper-side wiring path is greater than the wiring width of said first upper-side wiring path, and the wiring width of the second lower-side wiring path is less than the wiring width of the first lower-side wiring path.