Patent ID: 9053782
Filing Date: 2015-06-09
Classification: G11C,H03K

Abstract:
1. A memory device comprising: at least one memory cell comprising: first and second pairs of transistors each pair coupled in series between first and second supply voltages, wherein a first storage node between the first pair of transistors is coupled to control terminals of the second pair of transistors, and a second storage node between the second pair of transistors is coupled to control terminals of the first pair of transistors; and a first resistance switching element coupled between said first supply voltage and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; a fifth transistor directly coupled between said first storage node and a first access line; and a sixth transistor coupled between said second storage node and a second access line, wherein said fifth transistor is controlled by a first control line and said sixth transistor is controlled by a second control line independent of the first control line.