Patent ID: 7545189
Filing Date: 2009-06-09
Classification: H03L

Abstract:
1. A DLL circuit comprising: a first buffer that receives a power-down mode signal and a first external clock signal; a second buffer that receives the power-down mode signal and an inverted signal of the first clock signal; a first delay line that receives an output signal of the first buffer and which delays the output signal of the first buffer for a predetermined period of time; a second delay line that receives an output signal of the second buffer and which delays the output signal of the second buffer for a predetermined period of time; an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit that delays an output of the second delay line; a phase comparing unit that controls to enter into a disable state and to exit from the disable state based on the power down mode signal and an output signal of the replica delay unit and compares phase differences between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller that controls delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator, a delay line controller that controls delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator, wherein the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.