Patent ID: 6574721
Filing Date: 2003-06-03
Classification: G06F

Abstract:
An apparatus comprising:at least one processor; a memory coupled to the at least one processor; a global address space that may be accessed by the at least one processor via a plurality of global addresses; a local address space that may be accessed by the at least one processor via a plurality of local addresses; a process executed by the at least one processor; a hardware address translation mechanism coupled to the at least one processor that indicates an addressing error when an address generated by the process crosses a predefined boundary for the global address space; and an address space processor residing in the memory and executed by the at least one processor that operates in response to the indication of the addressing error from the hardware address translation mechanism, and in response thereto, dynamically determines whether the address generated by the process is a global address or a local address, and that indicates an addressing error if the address generated by the process is a global address, and if the address generated by the process is a local address, the address space processor determines whether the address generated by the process accesses the local address space, and if the address generated by the process does not access the local address space, indicating an addressing error to the process, and if the address generated by the process accesses the local address space, allowing the process to access the address.