Patent ID: 7287105
Filing Date: 2007-10-23
Classification: G06F,H04L

Abstract:
1. A receive buffer circuit comprising: a data buffer configured for latching a received data word in response to any edge transition on one of a first receive clock and a second receive clock, the first receive clock having a corresponding first phase at a prescribed frequency and the second receive clock having a corresponding second phase at the prescribed frequency, the second phase having a phase difference of one fourth of a clock cycle relative to the first phase, the prescribed frequency being one of a group of prescribed available frequencies, the received data words latched within the clock cycle of the first receive clock forming a corresponding buffer entry; a multi-phase clock generator configured for generating first, second, third and fourth secondary receive clock signals at a second frequency that is at most one half the prescribed frequency and having respective phases based on the first receive clock and the second receive clock, the first and third secondary receive clock signals having respective phases relative to the first and second phases, respectively, and the second and fourth secondary clock signals having respective phases relative to the inverses of the first and second phases, respectively; an edge detection module configured for detecting a first number of clock edges of the first, second, third, and fourth secondary receive clock signals having occurred within a clock cycle of a local clock, the local clock having a frequency greater than twice the second frequency; and buffer control logic configured for reading a selected number of the buffer entries from the data buffer based on the first number of clock edges having occurred within the clock cycle of the local clock, the buffer control logic including: (1) an edge counter configured for incrementing a stored value in response to the first number of clock edges, (2) a lookahead table having a plurality of entries specifying the prescribed available frequencies and respective pointer offsets, each pointer offset representing a corresponding latency encountered between latching the buffer entry in the data buffer at the corresponding prescribed available frequency and detection of the corresponding edges by the edge detection module, the lookahead table configured for incrementing the edge counter by a selected one of the pointer offsets based on a determined frequency determined as matching a corresponding one of the prescribed available frequencies, and (3) threshold logic configured for identifying a presence of valid data in the data buffer based on the stored value of the edge counter exceeding a selected prescribed threshold from a plurality of available thresholds, wherein in response to the identified presence of valid data: (a) the threshold logic is configured for causing the selected number of the received data words to be read from the data buffer, the selected number of the received data words corresponding to the selected prescribed threshold, and (b) the threshold logic is configured for decrementing the edge counter by the selected number of the received data words.