Patent ID: 7406634
Filing Date: 2008-07-29
Classification: G06F

Abstract:
1. A method for accessing a first peripheral device coupled via a bus to a system-on-a-chip (SOC) including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the SOC further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the SOC after a watchdog time-out period expires, said method comprising: flagging the first TLB entry as invalid; executing a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation; with the exception handler: programming the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watch dog timer period expires.