Patent ID: 6486694
Filing Date: 2002-11-26
Classification: H03K

Abstract:
A logic cell, comprising:a. a first and a second Josephson input circuit with first and second data input lines respectively, each said input circuit containing a plurality of Josephson elements arranged to generate a SFQ pulse and sustain a SFQ persistent current in response to an input signal applied to the respective data input line, b. a first and a second Josephson clock circuit with first and second clock input lines respectively, each said clock circuit containing at least one Josephson element arranged to provide a SFQ clock pulse in response to an input pulse applied to the respective clock input line, c. said first Josephson clock circuit being arranged to be in electrical contact with said first Josephson input circuit such that a portion of said SFQ persistent current from said first input circuit combines with a portion of said SFQ clock pulse from said first clock circuit to trigger the generation of a first SFQ output pulse, d. said second Josephson clock circuit being arranged to be in electrical contact with said second Josephson input circuit such that a portion of said SFQ persistent current from said second input circuit combines with a portion of said SFQ clock pulse from said second clock circuit to trigger the generation of a second SFQ output pulse, e. said first Josephson input circuit arranged to be in electrical contact with said second Josephson input circuit at a common circuit portion such that a portion of said SFQ persistent current from said first input circuit combines with a portion of said SFQ persistent current from said second input circuit within said common circuit portion to trigger the generation of a third SFQ output pulse.