Patent ID: 6138266
Filing Date: 2000-10-24
Classification: G06F

Abstract:
A method of verifying the functionality of a target design representing an integrated circuit said target design receiving a plurality of primary inputs and generating a plurality of primary outputs, said method comprising the steps of:(a) dividing said target design into a plurality of combinatorial blocks and a plurality of sequential elements, wherein said plurality of combinatorial blocks are divided into a plurality of sequences of stages with each output of one stage being provided as input to a subsequent stage in each sequence according to the dependencies in said target design;(b) computing a truth table for each of said plurality of combinatorial blocks to generate a plurality of truth tables, wherein each of said plurality of truth tables identifies an output value corresponding to each combination of input values of a corresponding one of said plurality of combinatorial blocks;(c) storing each of said truth tables in a random access storage device (RASD) containing a plurality of memory locations each accessible by a corresponding memory address, wherein the output value of each row of said plurality of truth tables is stored at a memo location having a memory address formed by the input values for the row such that each of said plurality of combinatorial blocks is evaluated by accessing said RASD having a memory address formed by the input values for the truth table;(d) receiving a plurality of primary input values, each of said plurality of primary input values corresponding to one of said plurality of primary inputs,(e) determining primary output values corresponding to said plurality of primary outputs by evaluating the output values of said plurality of combinatorial blocks, wherein the output values of some of said plurality of combinatorial blocks are used iteratively as input values of some other of plurality of combinatorial blocks in a subsequent stage according to said target design until said primary output values are generated,wherein the determined primary output values are used to verify the functionality of said target design, andwherein the output of each of said plurality of combinatorial blocks is determined by accessing the output value in a corresponding truth table stored in step (c) such that the functionality is verified in a speedy manner.