Patent ID: 6219072
Filing Date: 2001-04-17
Classification: G09G,H04N

Abstract:
A microcomputer comprising:a central processing unit (CPU) for instruction execution,an on-screen display (OSD) circuit for display of character information on a display screen,a read only memory (ROM) which is arbitrarily divided into a first ROM storage space for use by said CPU and a second ROM storage space for use by said OSD circuit,a random access memory (RAM) which is arbitrarily divided into a first RAM storage space for use by said CPU and a second RAM storage space for use by said OSD circuit,a common bus which is made up of a data bus and an address bus and to which said CPU, said OSD circuit, said ROM, and said RAM are connected in such a way as to allow said CPU and said OSD circuit to acquire an exclusive right to use said ROM and said RAM, anda bus liberation signal line over which when said common bus is not in use by said CPU, a message that said common bus is made available to said OSD circuit is sent to said OSD circuit from said CPU.