Patent ID: 8448100
Filing Date: 2013-05-21
Classification: G03F

Abstract:
1. A computer implemented method, comprising: (a) analyzing in a computer an initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; (b) constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; (c) classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; (d) causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications; wherein before step (d), prompting a user to input a number N of classifications to be displayed at any given time; and wherein step (d) includes initially displaying those multi-patterning conflict cycle graphs having the first N classifications.