Patent ID: 6251761
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of fabricating an integrated circuit MOSFET transistor, comprising the steps of:forming a dielectric layer with an upper surface over a semiconductor body;forming a high-K dielectric layer with an upper surface over said dielectric layer;subjecting said high-K dielectric layer to a remote plasma nitridation to convert said upper surface of the high-K dielectric to a nitride layer;forming a conductive layer on said nitride layer;patterning and etching said conductive layer, said high-K dielectric layer, said dielectric layer and said nitride layer to form a gate stack;forming drain extension regions in said semiconductor body adjacent said gate stack;forming sidewall spacers over said semiconductor body adjacent said gate stack; andforming source/drain regions in said semiconductor body adjacent said sidewall spacers.