Patent ID: 9000838
Filing Date: 2015-04-07
Classification: H03L,H05K,Y10T

Abstract:
1. A method of reducing interference present in a circuit formed on an integrated circuit comprising the steps of: identifying a conductive trace in a first layer of the integrated circuit, the conductive trace carrying high frequency digital current in the circuit; fabricating first and second conductive strips in the proximity of the identified conductive trace to help contain the high frequency current flowing through the conductive trace, wherein the first conductive strip has first and second opposite ends, wherein the first end makes a connection to a reference voltage, and wherein the second end makes no connection; fabricating a third conductive strip in a second layer of the integrated circuit above the conductive trace, the third conductive strip oriented substantially parallel to the conductive trace; fabricating a first set of vias to couple the first conductive strip to the third conductive strip; and fabricating a second set of vias to couple the second conductive strip to the third conductive strip.