Patent ID: 9202844
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate having first conductivity-type impurities; a lower interconnection on the substrate and having second conductivity-type impurities; a switching device on the lower interconnection; a semiconductor blocking layer between the substrate and the lower interconnection, the semiconductor blocking layer having the same horizontal width as the lower interconnection; and an additional blocking layer that includes carbon (C) and/or germanium (Ge) between the lower interconnection and the switching device, wherein the semiconductor blocking layer comprises: a lower blocking layer in contact with an active region in the substrate and having the first conductivity-type impurities; and an upper blocking layer in contact with the lower interconnection and having the second conductivity-type impurities, and wherein the additional blocking layer comprises a lower additional blocking layer in contact with the lower interconnection; and an upper additional blocking layer in contact with the lower additional blocking layer, wherein a width of the lower additional blocking layer exceeds a width of the upper additional blocking layer, wherein the semiconductor blocking layer comprises a silicon layer that is doped with first conductivity-type impurities and carbon (C), germanium (Ge), or a combination thereof.