Patent ID: 8643056
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A power semiconductor device including a device section in which a current flows in a vertical direction between a first electrode and a second electrode opposed to each other, and a termination section surrounding the device section in a horizontal plane orthogonal to the vertical direction, the device comprising: a first semiconductor layer of a first-conductivity-type impurity; a first drift layer formed on the first semiconductor layer and including a first epitaxial layer of the first-conductivity-type impurity, a plurality of first first-conductivity-type pillar layers of the first-conductivity-type impurity, and a plurality of first second-conductivity-type pillar layers of a second-conductivity-type impurity, the first epitaxial layer having a lower concentration of first-conductivity-type impurity than the first semiconductor layer, the plurality of first first-conductivity-type pillar layers and the plurality of first second-conductivity-type pillar layers alternately and repeatedly arranged in a first direction parallel to the horizontal plane only in the device section in the first epitaxial layer, and the plurality of first first-conductivity-type pillar layers having a higher concentration of the first-conductivity-type impurity than the first epitaxial layer; a second drift layer formed on the first drift layer and including a second epitaxial layer of the first-conductivity-type impurity, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers, the second epitaxial layer of the first-conductivity-type impurity having a higher concentration of the first-conductivity-type impurity than the first epitaxial layer, the plurality of second second-conductivity-type pillar layers spaced along the first direction in the device section in the second epitaxial layer and connected to the first second-conductivity-type pillar layers, the plurality of second first-conductivity-type pillar layers made of the second epitaxial layer sandwiched between adjacent ones of the second second-conductivity-type pillar layers and connected to the first first-conductivity-type pillar layers, the plurality of third second-conductivity-type pillar layers spaced along the first direction in the termination section in the second epitaxial layer and arranged on the first epitaxial layer, and the plurality of third first-conductivity-type pillar layers made of the second epitaxial layer sandwiched between adjacent ones of the third second-conductivity-type pillar layers and arranged on the first epitaxial layer; a plurality of second-conductivity-type base layers selectively formed in a surface of the second drift layer in the device section and electrically connected to the second second-conductivity-type pillar layers; a first-conductivity-type source layer selectively formed in a surface of the second-conductivity-type base layers; and a gate electrode formed via a gate insulating film on the first-conductivity-type source layer, the second-conductivity-type base layers, and the second first-conductivity-type pillar layers, the first electrode being electrically connected to a surface of the first semiconductor layer on opposite side of the first drift layer, and the second electrode being electrically connected to the first-conductivity-type source layer and the second-conductivity-type base layers.