Patent ID: 6385702
Filing Date: 2002-05-07
Classification: G06F

Abstract:
A method of maintaining cache coherency in a computer system having a plurality of processing units, each processing unit having a respective cache hierarchy, said method comprising:in response to a processing unit executing a read operation requesting a value, issuing a read request requesting the value from an upper level cache of the processing unit, said processing unit having a cache hierarchy including the upper level cache and a lower level cache; in response to the read request, loading the value into a cache line of the upper level cache; in response to loading the value into the upper level cache from system memory without loading it into any other cache of the computer system, marking the cache line with a first exclusive state indicating that the upper level cache holds the value exclusive of all other caches of the computer system including the lower level cache; in response to loading the value into the upper level cache from the lower level cache, marking the cache line with a different second exclusive state indicating that the cache hierarchy of the processing unit holds the value exclusive of any other cache hierarchy in the computer system; and in response to loading the value from an intervening cache of another processing unit, selectively marking the cache line with one of the first exclusive state and a shared state in accordance with current programming of said cache.