Patent ID: 6784062
Filing Date: 2004-08-31
Classification: H01L

Abstract:
A method of forming a pair of transistor gates of opposite conductivity type during semiconductor fabrication comprising the steps of:forming transistor gate stack layers comprising a polysilicon layer having first and second lateral sections, the first lateral section having a dominant first-type conductive dopant therein, the second lateral section having a dominant second-type conductive dopant therein; etching the gate stack material and an upper portion of the polysilicon layer to form a first partial gate stack comprising an upper portion of the first lateral section and a second partial gate stack comprising an upper portion of the second lateral section, after the etching, a lower portion of the polysilicon layer remains to form a first lateral section extension beyond the first partial gate stack and a second lateral section extension beyond the second partial gate stack; forming a first mask that covers the partial second gate stack and the second lateral section extension and exposes the partial first gate stack and the first lateral section extension; with the first mask present, forming a first-type conductive transistor gate by removing the exposed first lateral section extension; forming a second mask that covers the first-type conductive transistor gate and exposes the partial second gate stack and the second lateral section extension exposed; with the second mask present, forming a second-type conductive transistor gate by removing the exposed second lateral section extension.