Patent ID: 8564053
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A trench MOSFET with a plurality of transistor cells in active area and multiple trenched floating gates in termination area, comprising: an epitaxial layer of a first conductivity type onto a substrate of said first conductivity type, wherein said epitaxial layer having a lower doping concentration than said substrate; a plurality of source regions of said first conductivity type formed near top surface of said epitaxial layer only in said active area, said source regions having a higher doping concentration than said epitaxial layer; a plurality of first type body regions of a second conductivity type formed underneath said source regions in said active area; a plurality of second type body regions of said second conductivity type formed in said epitaxial layer around outside of said active area, and said source regions being not disposed on top of said second type body regions; a plurality of first type trenched gates in said active area, surrounded by said source regions and said first type body regions; at least one second type trenched gate surrounded by said second type body regions and extending to said first type trenched gates for gate connection, wherein said at least one second type trenched gate is connected to a gate metal pad for wire bonding; said multiple trenched floating gates as third type trenched gates formed in parallel in said termination area around outside of said active area, said multiple trenched floating gates having floating voltage and surrounded by said second type body regions, having trench depth equal to or deeper than body junction of said second type body regions; an EPR ring in said termination area and surrounding outside of said multiple trenched floating gates, said EPR ring comprising a fourth type trenched gate shorted with a third type body region of said second conductivity type adjacent edge of the device through a EPR metal.