Patent ID: 7858425
Filing Date: 2010-12-28
Classification: H01L,Y02E,Y02P

Abstract:
1. A method of manufacturing a PIN diode in a Silicon On Insulator (SOI) substrate, comprising the steps of: obtaining a semiconductor structure comprising a p depositing a first photoresist layer upon said top surface of said active silicon layer in a desired pattern; etching said active silicon layer to form a first aperture for an anode region and a second aperture for a cathode region; stripping said first photoresist layer; applying a first applied layer of silicon dioxide to an upper surface of the resulting structure having a top surface and a bottom surface; applying a second photoresist layer upon said top surface of said first applied layer of silicon dioxide in said desired pattern; etching said first applied silicon dioxide layer to expose said top surface of said p stripping said second photoresist layer; applying a third photoresist layer upon an upper surface of the resulting structure; implanting a p+ region in said exposed top surface of said p− type substrate in said anode region; stripping said third photoresist layer; applying a fourth photoresist layer upon said upper surface of the resulting structure; implanting an n+ region in said exposed top surface of said p stripping said fourth photoresist layer; depositing a metal layer upon an upper surface of the resulting structure; and applying a fifth photoresist layer upon said upper surface of the resulting structure; etching unwanted metal from said metal layer in a desired pattern to form a first metallic anode contact in electrical communication with said anode region thereby creating a PIN diode anode contact, and to form a second metallic cathode contact in electrical communication with said cathode region, thereby creating a PIN diode cathode contact; and stripping said fifth photoresist layer.