Patent ID: 9047951
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells; a word line electrically connected to one of the memory cells; m bit lines, one of the bit lines being electrically connected to one of the memory cells, m being an integer equal to or greater than 2, the m bit lines extending in a first direction; and k sense amplifiers disposed within a first width of k bit lines, k being an integer equal to or greater than 2 and equal to or less than m, k sense amplifiers including a first sense amplifier and a second sense amplifier, the first sense amplifier including first to fifth lines and transistors, the transistors being disposed one by one in the first direction, gates of the transistors being parallel to one another, a longer side width of a first contact electrically connected to an active area of the transistor is substantially identical to a width of the bit line, the first and second lines being capable of transferring a complementary data, the third line being a power line, the fourth line being electrically connected to at least one of the transistors, the fifth line being electrically connected to the second sense amplifier.