Patent ID: 6875655
Filing Date: 2005-04-05
Classification: H01L

Abstract:
1. A method for fabricating an array of capacitors for dynamic random access memory (DRAM) devices comprising the steps of: providing a substrate having partially completed device areas for said DRAM devices; forming a first insulating layer over said substrate; forming first openings in said first insulating layer and forming capacitor node contact plugs in said first openings to said substrate; depositing a second insulating layer and forming second openings for capacitor bottom electrodes aligned over and to said node contact plugs; forming a first conducting layer in said second openings to form said capacitor bottom electrodes; patterning said second insulating layer to leave portions between and contacting adjacent said bottom electrodes to provide physical support for said bottom electrodes, and to expose portions of outer sidewalls of said bottom electrodes for increased capacitance; forming an interelectrode dielectric layer on said bottom electrodes, and depositing and patterning a second conducting layer to form top electrodes for said array of capacitors.