Patent ID: 8004319
Filing Date: 2011-08-23
Classification: G06F,H03K

Abstract:
1. A clock divider, comprising: a first circuit, including first logic to perform a first comparison of a first number and a count value to generate a first signal; a second circuit, including second logic to perform a second comparison of a second number and the count value to generate a second signal; and a first multiplexer including a first input coupled to the first circuit to receive the first signal, a second input coupled to the second circuit to receive the second signal, a selection input to receive a first clock signal, and an output, wherein the first multiplexer outputs an output signal via the output, as a divided clock signal, based on the first clock signal, the first signal, and the second signal, wherein the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.