Patent ID: 7958279
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. A semiconductor integrated circuit apparatus comprising: a data transmitter circuit configured to transmit transfer data to a data reception unit, the data transmitter circuit having shift registers which store the transfer data, and a transmission control circuit having a first data converter circuit which converts each of bits of the transfer data from the shift registers to 2-bit complementary data to output converted data to first and second output terminals, and a transfer managing circuit which outputs a data transfer completion signal to a third output terminal, following transfer of the transfer data to output the signal to the third output terminal, the transfer managing circuit outputting the transfer completion signal in response to a termination of the transfer of the converted data to the data reception unit, and the first data converter circuit being configured to output a clock signal supplied to the shift registers and the transfer managing circuit in response to a reception acknowledge signal and a transfer allowing signal supplied from the data reception unit; first, second, and third transmission lines connected to the first, second, and third output terminals, respectively; a plurality of data receiver circuits included in the data reception unit having a plurality of shift registers, input control circuits each connected to an input side of each of the shift registers, the input control circuit having a second data converter circuit which restores 2-bit complementary data transferred from the data transmitter circuit via the first and second transmission lines to the transfer data; and a data output control circuit connected to an output side of each of the shift registers, the data output control circuits converting each of the bits of the transfer data restored by the second data converter circuit into 2-bit complementary data to output the converted data to a data receiver circuit at a next stage, the plurality of data receiver circuits being connected in series to the data transmitter circuit via the input control circuit and data output control circuit, wherein each of the data receiver circuits is configured to output a reception acknowledge signal being sent to a data receiver circuit at a former stage when a following stage reception acknowledge signal has been received from a data receiver circuit at a following stage with respect to transfer data transmitted therefrom to the data receiver circuit at the following stage, and wherein a data receiver circuit in a first data receiver circuit connected to receive the converted data from the data converter circuit is configured to output the reception acknowledge signal to the data converter circuit in the data transmitter circuit.