Patent ID: 7417914
Filing Date: 2008-08-26
Classification: G11C

Abstract:
1. A semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks, in which data is read or written by the local block, and in which each local block has a read error protection circuit for preventing a read error from occurring in the case of data being read from a memory cell, the read error protection circuit including: a first transistor having an input terminal connected to an auxiliary connection line of a memory cell included in the local block, a first output terminal connected to a main common bit line for reading data from or writing data into a local block included in each column is connected, and a second output terminal connected to a constant high-level voltage power supply; and a second transistor having an input terminal connected to a main connection line of a memory cell included in the local block, a first output terminal connected to an auxiliary common bit line for reading data from or writing data into a local block included in each column, and a second output terminal connected to the constant high-level voltage power supply.