Patent ID: 6981185
Filing Date: 2005-12-27
Classification: H03K

Abstract:
1. An apparatus for correcting duty cycle error in a data transmission system, comprising: an oversampler being configured to oversample an input signal; an accumulator coupled to the oversampler, the accumulator being configured to generate an accumulated high bit signal and an accumulated low bit signal from the oversampled input signal received from the oversampler; a comparator coupled to the accumulator, the comparator being configured to receive an accumulated high bit signal and an accumulated low bit signal from the accumulator, the comparator also being configured to compare an amount of the accumulated high bit signal and the accumulated low bit signal; a successive approximation register (SAR) logic coupled to the comparator, the SAR logic being configured to receive a compared signal from the comparator and to determine a duty cycle error, the SAR logic capable of generating polarity data and magnitude data for correcting the duty cycle error; and an output register coupled to the SAR logic, the output register being configured to forward the polarity data to an adjustable driver and to send the magnitude data to a digital analog converter (DAC).