Patent ID: 6026224
Filing Date: 2000-02-15
Classification: G06F,Y02P

Abstract:
An automated method for inserting redundant via pairs in an integrated circuit design comprising the steps of:determining single vias in the wiring design;examining directions in an area in a first level around each single via for wire segments;for each direction for which a wire segment is detected, testing to see if the area in an adjacent level is valid;creating a redundant via pair in the area of the adjacent level the test shows as valid;if no redundant via is created, examining directions in an area in the adjacent level around each single via for wire segments;for each direction for which a wire segment is detected, testing to see if the area in the first level is valid;creating a redundant via pair in the area of the first level the test shows as valid;if no redundant via pair is created and there are directions around each single via remaining unexamined, testing an area around the unexamined directions on both levels adjacent the single via to see if they are valid; andcreating a redundant via pair in the area around the unexamined direction the test shows as valid,wherein the test for inserting redundant via pairs on detected wire segments in the first level is whether a grid point one track in the same direction away from the single via in the adjacent level is valid and the test for inserting the redundant via pair on detected wire segments in the adjacent level is whether a grid point one track in the same direction away from the single via in the first level is valid.