Patent ID: 6587914
Filing Date: 2003-07-01
Classification: G06F,G11C

Abstract:
A non-volatile semiconductor memory device comprising an address buffer block, a matrix of non-volatile memory cells, and an output buffer block, said address buffer block configured to receive input signals external to the memory device, that in a first operating mode are controlled by devices external to the memory device, and to transmit signals to said matrix of memory cells that are adapted to decode said received signals and to transmit in turn output decoded signals through said output buffer block, and further comprising a command block formed with the matrix of non-volatile memory cells, the command block comprising a command interpreter and an internal counter and no CPU and activatable through an external control signal that, once activated, puts the memory device in a second operating mode as a sequential machine to perform a predefined set of instructions stored in the matrix of memory cells in which said command block receives at least a part of said signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to said address buffer block, so to have a feedback inside said memory device to enable execution by the command block of a succession of limited only non-computational instructions stored in said matrix of memory cells autonomous of any CPU.