Patent ID: 6313537
Filing Date: 2001-11-06
Classification: H01L

Abstract:
A semiconductor device having a multi-layered pad, comprising:a first interlevel insulating layer formed on a semiconductor substrate;a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region;a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad;a first conductive plug formed in the first via hole;a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug;a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad;a second conductive plug formed in the second via hole;a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug; anda plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region at substantially the same time as the first or second conductive pads, the plurality of buffer layers being a same material as the first or second conductive pads.