Patent ID: 8755231
Filing Date: 2014-06-17
Classification: G11C

Abstract:
1. A flash memory, comprising: a flash memory chip; a serial-to-parallel converter for receiving a serial data and converting the serial data into a parallel data; and a data mode decision circuit connected to an output terminal of the serial-to-parallel converter for receiving the parallel data and generating an inversion control signal, the data mode decision circuit applying an inversion processing to the parallel data and then outputting an inverted parallel data to the flash memory chip under control of the inversion control signal; wherein the data mode decision circuit at least comprises a digital-to-analog converter, a level shifter and an inversion circuit; the digital-to-analog converter is connected to the output terminal of the serial-to-parallel converter, and is used for converting the parallel data into an analog initial control signal; the level shifter is connected to an output terminal of the digital-to-analog converter, and is used for shifting a level of the analog initial control signal and then outputting the inversion control signal to the inversion circuit; the inversion circuit has an input terminal connected to the output terminal of the serial-to-parallel converter, the inversion circuit applying the inversion processing to the parallel data and then outputting the inverted parallel data to the flash memory chip under the control of the inversion control signal.