Patent ID: 6574780
Filing Date: 2003-06-03
Classification: G06F

Abstract:
A method for electronically modeling and estimating characteristics of a multi-layer integrated circuit chip carrier having at least one chip thereon; comprising the steps of:providing said chip carrier having at lease one redistribution layer thereon, said at least one redistribution layer including at least one conductive layer; receiving specified input parameters; said parameters comprising ground rule and physical parameters selected from the group of parameters consisting of pad size, procoat opening size, minimum wiring width and spacing, chip contact pitch, chip size, border size and percent ground/voltage of chip I/Os; and through build up technology generating said representation responsive to said parameters; selectively receiving or deriving a netlist of interconnections between said chip and said carrier; responsive to said input parameters and netlist, generating a representation of an optimized estimated fanout of said interconnections; and graphically displaying said optimized estimated fanout together with a set of carrier parameters derived from said optimized estimated fanout.