Patent ID: 9077352
Filing Date: 2015-07-07
Classification: H03L,H04L

Abstract:
1. A clock regeneration circuit comprising: a signal input terminal inputted with a pulse width modulation signal having a prescribed period and a fixed average duty cycle; a D flip-flop circuit including a clock terminal, an input terminal supplied with a power supply voltage, an output terminal and a reset terminal; a reset signal generation circuit connected to the signal input terminal and configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal; a delay circuit connected to the signal input terminal and configured to delay the pulse width modulation signal by a first delay time and output toward the clock terminal; a comparator including a first input terminal, a second input terminal supplied with a reference voltage, and an output terminal, and configured to output a signal having the prescribed period; a first capacitor connected between the first input terminal and ground; and a feedback circuit including a current source having a control terminal, the current source being configured to change one of charge rise time and discharge fall time of the first capacitor by voltage of the control terminal changed in response to the signal of the comparator to control duty cycle of the signal of the comparator to a prescribed value.