Patent ID: 9105332
Filing Date: 2015-08-11
Classification: G11C,H01L

Abstract:
1. A variable resistance nonvolatile memory device comprising: a plurality of first signal lines and a plurality of second signal lines which cross; a memory cell array including a plurality of memory cells disposed at cross points at which the first signal lines and the second signal lines cross, the memory cells each having an end connected to one of the first signal lines and another end connected to one of the second signal lines; and a write circuit which generates a bipolar voltage to be applied to the memory cells via the first signal lines and the second signal lines; wherein the memory cells each further include: a variable resistance element of which a resistance state changes to a low resistance state when a first voltage of a first polarity is applied, and changes to a high resistance state when a second voltage of a second polarity opposite to the first polarity is applied, the high resistance state being higher than the low resistance state in resistance value; and a current steering element in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being a given value less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, and in each of the memory cells, the variable resistance element and the current steering element are connected in series.