Patent ID: 6707868
Filing Date: 2004-03-16
Classification: H04L

Abstract:
A timing recovery system, comprising:a transceiver core having an input side and an output side, the transceiver core processing transmit and receive data at a predetermined baud rate; an analog front end, coupled to the transceiver core, for transmitting and receiving analog signals over a network; a phase detector, coupled to the transceiver core, the phase detector generating a phase error estimate signal based upon a sampling of a received signal at the transceiver core; and a timing controller, coupled to the phase detector, for receiving the phase error estimate signal and generating a receive and transmit phase control signal for controlling timing of the analog front end; wherein the phase detector further comprises: a channel estimator for generating a coefficient error signal that is used to tune the channel estimator and for generating a phase reference value; and a comparator, coupled to the channel estimator, the comparator receiving the phase reference value from the channel estimator and a nominal reference value for processing to generate the phase error estimate signal of the received signal.