Patent ID: 7236116
Filing Date: 2007-06-26
Classification: H03M

Abstract:
1. A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests, used in the digitally testable architecture of a reconfigurable switched-capacitor input circuit, and comprising: an analog input signal, including a positive phase voltage signal and a negative phase voltage signal; multiple DC voltage sources, including: a first DC voltage source, a second DC voltage source, a third DC voltage source, and a fourth DC voltage source; an operational amplifier, having a first input end, a second input end, a first amplifier output end and a second amplifier output end, and amplifying the voltage difference between said second input end and said first input end to generate an output voltage between said first amplifier output end and said second amplifier output end; at least two switched-capacitor sets, wherein each said switched-capacitor set further comprises: a first capacitor, a second capacitor and multiple analog-signal switches; each said capacitor has a bottom end and a top end; a first of said at least two switched-capacitor sets corresponds to a first digital stimulus and a second of said at least two switched-capacitor sets corresponds to a second digital stimulus; and each said first digital stimulus and said second digital stimulus is a Sigma-Delta modulated digital stimulus bit-stream; and a digital switching-signal generator, receiving at least: a digital mode signal, a clock signal, and said first and second digital stimuli, and creating multiple switching signals to control said analog-signal switches of said switched-capacitor sets, wherein said digital mode signal has two logic states, including a normal mode and a test mode, and said clock signal is used to create at least two non-overlapped clock phases, including a first clock phase and a second clock phase; said first switched-capacitor set is controlled by said first digital stimulus and said second switched-capacitor set is controlled by said second digital stimulus and each behaves as one-bit digital-to-charge converter when said digital mode signal is in said test mode state, wherein said second digital stimulus is the same as said first digital stimulus but later than said first digital stimulus by several cycles.