Patent ID: 6714885
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips, comprising the steps of:(a) checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map; (b) forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located; (c) plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process; and (d) classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map, wherein, in the step (b), disparity chips are formed by sequentially searching defective chips on a wafer map and by combining the defective chip searched among non-defective chips which did not form a disparity chip with non-defective chips directly above, below, to the left and right and the defective chips which are not combined with the adjacent non-defective chips among the searched defective chips are excluded from the maximum reliability region.