Patent ID: 7840368
Filing Date: 2010-11-23
Classification: G01R,G11C

Abstract:
1. A test circuit, comprising: a first reset pulse generator configured to generate a first reset pulse when a test mode selection signal or a power-up signal is activated; a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to test information data received as a predetermined consecutive test information data, wherein the test mode maintenance signal is inactivated by the first reset pulse; a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when the power-up signal is activated; and a test mode selection signal generator configured to receive a shifted test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, an activation of the specific test mode selection signal being controlled by the second reset pulse, wherein different types of the test modes are operated according to the test information data.