Patent ID: 6503818
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A method for forming within an integrated circuit microelectronics fabrication a dielectric layer comprising:providing a semiconductor substrate; forming within and upon the semiconductor substrate an integrated circuit microelectronics fabrication; forming over the integrated circuit microelectronics fabrication a silicon oxide dielectric layer; forming within the silicon oxide dielectric layer a contact via hole pattern to the underlying integrated circuit microelectronics fabrication; forming over the patterned silicon oxide dielectric layer a low dielectric constant dielectric layer having a dielectric constant of from about 2.5 to 3.3; treating the low dielectric constant dielectric layer with a plasma formed in nitrous oxide (N2O) gas to form a plasma treated low dielectric constant dielectric layer having a dielectric constant of from about 2.5 to 3.3; forming a silicon containing dielectric mask layer over the plasma treated low dielectric constant dielectric layer; forming upon the silicon containing dielectric mask layer a patterned photoresist etch mask layer of a trench pattern to interconnect the via hole pattern; etching the trench pattern into and through the silicon containing dielectric mask layer and underlying low dielectric constant dielectric layer to form a conductor pattern interconnecting the previously formed contact via hole pattern; further etching the contact via hole pattern through the low dielectric constant dielectric layer to the underlying integrated circuit microelectronics fabrication formed within the semiconductor substrate; stripping the photoresist etch mask layer; and forming an inlay pattern of conductor material within the via hole contact pattern and the trench interconnection pattern to form a dual damascene interconnection pattern.