Patent ID: 6703312
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of simultaneously patterning features having a first width in a first portion of an integrated circuit, and having a second width in a second portion of an integrated circuit, comprising:depositing a feature layer over a substrate; depositing a hardmask material layer over said feature layer; depositing and patterning a photoresist using a critical dimension mask to define photoresist patterns in both a first portion and a second portion of said substrate; patterning said hardmask material layer with said photoresist patterns to form hardmask patterns in both said first portion and said second portion; providing sidewall spacers on sidewalls of said hardmask patterns in said second portion; and simultaneously etching said feature layer in both said first portion and said second portion, using said hardmask patterns in said first portion to define features having a first width in said first portion, and using said hardmask patterns and said remaining sidewall spacers in said second portion to define features having a second, different width in said second portion.