Patent ID: 6437613
Filing Date: 2002-08-20
Classification: G11C,H03K,H03L

Abstract:
A clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal, the clock generating circuit comprising:a mirror delay circuit for receiving the reference clock signal and delaying the reference clock signal by a predetermined mirror delay time to generate a delay clock signal; a multiplexer for selecting and outputting one of the delay clock signal and the internal clock signal in response to a predetermined toggle control signal; a first divider for dividing the signal transmitted from the multiplexer by 2 to generate a first divided signal; a second divider for dividing the reference clock signal by 2 to generate a second divided signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; and a fast comparator for providing a pre-clock signal for generating the internal clock signal, in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level of one of the first and the second pumping signals with respect to a predetermined reference voltage.