Patent ID: 6301653
Filing Date: 2001-10-09
Classification: G06F

Abstract:
A digital signal processor for use in executing a plurality of instructions contained in an instruction packet, said processor comprising:a plurality of register blocks, each containing operands;a plurality of data path units, wherein each of said data path units comprises a plurality of functional units, for executing said instructions using said operands and yielding results;a coupling fabric configured to facilitate communication between said register blocks and said data path units, wherein said coupling fabric comprises a plurality of forwarding paths wherein each of said forwarding paths is configured to couple two of said data path units together, said forwarding paths being unidirectional; anda scheduler which contains information regarding said coupling fabric, said scheduler configured to forward each of said plurality of instructions to one of said data path units based on the configuration of said coupling fabric; and whereinsaid plurality of data path units equals M data path units, wherein said coupling fabric is further configured to couple each of said register blocks to L of said M data path units, where 1<L<M.