Patent ID: 9196317
Filing Date: 2015-11-24
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a first memory block including a plurality of first vertical strings, wherein the first vertical strings include a plurality of first control gates which are stacked in order, respectively; a second memory block including a plurality of second vertical strings electrically coupled in series with the plurality of first vertical strings, respectively, wherein the second memory block is stacked on the first memory block, and the second vertical strings include a plurality of second control gates which are stacked in order, respectively; first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings; a plurality of first source lines located under the first memory block and electrically coupled to the plurality of first vertical strings, respectively; a plurality of second source lines located above the second memory block and electrically coupled to the second vertical strings, respectively; a bit line voltage supply circuit; a read/write circuit; and a switch configured to couple the first bit lines to the bit line voltage supply circuit or the read/write circuit, wherein the first control gates and the second control gates of the same position in the respective strings are electrically coupled in common.