Patent ID: 6111450
Filing Date: 2000-08-29
Classification: H03K

Abstract:
An integrated circuit having an adaptive buffer for interfacing with a signaling path, the adaptive buffer being configured to operate in a first voltage signaling mode on the signaling path, the first voltage signaling mode having a first logical high voltage, and a second voltage signaling mode on the signaling path, the second voltage signaling mode having a second logical high voltage, the first logical high voltage being of a higher potential than the second logical high voltage, the buffer being provided with a supply voltage, the adaptive buffer comprising:a buffer circuit adapted to communicate with the signaling path; anda control circuit adapted to be connected to the signaling path and the supply voltage, the control circuit being operative in the second voltage signaling mode to clamp a signaling path voltage to the supply voltage upon the occurrence of the signaling path voltage being higher than the second logical high voltage.