Patent ID: 7496825
Filing Date: 2009-02-24
Classification: H03M

Abstract:
1. An apparatus for error-correcting a digital signal including a cyclic redundancy code (CRC), the apparatus comprising: a memory storing CRC syndromes, the syndromes corresponding to respective ones of each of the possible single-bit error conditions of a received signal; a comparator configured to sequentially compare a CRC syndrome for a received signal with syndromes in said memory; a counter configured to be incremented or decremented for each comparison by the comparator until a match is found or the CRC syndromes stored in the memory have been exhausted; and an inverter for inverting a bit of said received signal in dependence on a value of said counter, wherein the CRC code is provided as the modulo-2 quotient of data bits and a generator polynomial providing that for single-bit errors there is a one-to-one relationship between error bit position and syndrome value, said quotient being given by the mathematical expression: wherein the division is modulo-2 division, M(x) are the data bits, G(x) is the generator polynomial, k is the number of CRC code bits, and a transmitted data block is given by: