Patent ID: 7953951
Filing Date: 2011-05-31
Classification: G06F

Abstract:
1. A multi-threading processor for processing a sequence of instruction threads, comprising a plurality of execution stages, each stage capable of performing a step in the execution of an instruction; a plurality of memory locations, each memory location having an address and capable of storing an instruction from a different one of a sequence of n instruction threads, where n is the number of addresses in the sequence of addresses from which a thread is chosen; a time-division multiplexer that repetitively generates an ordered sequence of memory location addresses for selecting thread instructions i=1,2 . . . n, each thread i selected by accessing the contents of a different memory location, each different memory location containing an instruction of a different thread; a complementary thread determiner to determine an address that is the complement of an address generated by the time-division multiplexer for a complementary thread; wherein the complementary thread of a thread i is defined to be the thread (i+n/2) modulo(n), where n is an even number greater than 3; and a thread selector that selects a first thread instruction from an address provided by the multiplexer if the first thread is not stalled and that selects a second thread instruction from the complementary address determined by the complementary thread determiner if the first thread is stalled.