Patent ID: 8593896
Filing Date: 2013-11-26
Classification: G11C

Abstract:
1. An apparatus, comprising: a memory array comprising a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the plurality of memory cells arranged along rows of the memory array; a plurality of write word lines coupled to the plurality of memory cells arranged along rows of the memory array; a plurality of read bit line pairs coupled to the plurality of memory cells arranged in columns of the memory array; a plurality of write bit line pairs separate from the read bit line pairs and coupled to the plurality of memory cells arranged in columns of the memory array; and a plurality of differential read write back sense amplifiers, each coupled to a read bit line pair and to a write bit line pair corresponding to one of the columns of the plurality of memory cells, configured to differentially sense small signal read data on the read bit line pair, latch the sensed data into a latch of a respective sense amplifier, and output the sensed data from the latch onto the write bit line pair, responsive to control signals.