Patent ID: 6134179
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving address signals and control signals in synchronization with a clock signal and inputting/outputting storage data, comprising:a plurality of memory cell blocks each having a plurality of memory cells arranged in a matrix of rows and columns;an address bus provided common to said plurality of memory cell blocks for transmitting said address signals to each of said plurality of memory cell blocks, said address bus includingan address signal line time-divisionally transmitting a row address signal designating a memory cell position in the row direction and a column address signal designating a memory cell position in the column direction; anda plurality of selecting circuits provided corresponding to said plurality of memory cell blocks, for selecting said memory cells in response to said address signals from said address bus,each of said selecting circuits includinga column selecting circuit holding data corresponding to said column address signal for performing column selection of said memory cells in response to said column address signal.