Patent ID: 6603692
Filing Date: 2003-08-05
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells; a digit line connected to each memory cell and having first and second ends; a plurality of word lines each crossing said digit line and each coupled to an associated one of said memory cells; a word driver for activating one of said word lines that corresponds to a content of a word selection signal; an input buffer coupled to receive said word selection signal; a first pre-charge circuit arranged on a side of said first end of said digit line; and a second pre-charge circuit arranged on a side of said second end of said digit line; a sense amplifier arranged near to said first pre-charge circuit; said word lines including a first word line near to said first pre-charge circuit and a second word line near to said second pre-charge circuit; wherein a period of time from said input buffer receiving a first word selection signal to activation of said second word line is shorter than a period of time from said input buffer receiving a second word selection signal to activation of said first word line.