Patent ID: 8694843
Filing Date: 2014-04-08
Classification: G01R,G06F

Abstract:
1. A non-transitory computer readable medium carrying one or more sequences of instructions for causing a digital processing system to facilitate testing of logic circuits on an integrated circuit, wherein execution of said one or more sequences of instructions by one or more processors contained in said digital processing system for testing said integrated circuit causes said digital processing system to perform the actions of: scanning compressed test patterns into the integrated circuit; decompressing the compressed test patterns; forming test data from the decompressed test patterns; shifting the test data into scan-in chains; halting cycling of clocks to pipelined memory banks on the integrated circuit to prevent incorrect data from being read into scan-out chains by the pipelined memory banks during testing of the logic circuits; launching the test data from the scan-in chains into the logic circuits during a first clock cycle; capturing data from outputs of the logic circuits into scan-out chains during a second clock cycle; wherein the second clock cycle immediately follows the first clock cycle, the second and first clock cycles having the same period.