Patent ID: 6438047
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array receiving and outputting data through data I/O line groups; at least one redundant cell control adapted to storing a defective cell address, generating a redundant cell enable control signal when the defective cell address is equal to an input cell address, generating a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generating a redundant cell write control signal during a write operation in response to the redundant cell enable control signal; a sense amplifier connected to an I/O line group commonly connected to the data I/O line groups, adapted to amplify and output data outputted from the memory cell array during the read operation, and disabled in response to the redundant cell read control signal; and at least one redundant cell adapted to store input data transferred to the I/O line group in response to the redundant cell write control signal and outputting stored data in response to the redundant cell read control signal.