Patent ID: 6750515
Filing Date: 2004-06-15
Classification: H01L

Abstract:
An integrated circuit device, comprising:a semiconductor substrate; an isolation layer formed over the semiconductor substrate; and a layer of silicon material, formed over the isolation layer, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, a second n-type portion contiguous with the second p-type portion, a third p-type portion contiguous with the second n-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion formed entirely in the second n-type portion and spaced apart from the third p-type portion, wherein the second n-type portion includes the third n-type portion and the third p-type portion, each of which being spaced apart from the isolation layer, wherein the first, second, and third n-type portions and the first, second, and third n-type portions collectively form a rectifier, wherein the first n-type portion and the first n-type portion form a cathode of the rectifier, wherein the third n-type portion and the third p-type portion form an anode of the rectifier; and wherein the third p-type portion and the fourth p-type portion define a source region and a drain region of a PMOS transistor.