Patent ID: 6300211
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory device, comprising the steps of:forming a mask insulating layer having an opening on a semiconductor substrate;perforating a first trench within said semiconductor substrate by using said mask insulating layer as a mask;forming a sidewall oxidation-resistant layer on a sidewall of said first trench;perforating a second trench within said semiconductor substrate by using said sidewall oxidation-resistant layer as a mask;performing a thermal oxidizing operation upon said semiconductor substrate by using said sidewall oxidation-resistant layer as a mask, so that a buried silicon oxide layer is formed within said second trench;removing a bottom portion of said buried silicon oxide layer by using a dry etching process;perforating a third trench within said semiconductor substrate by using said sidewall oxidation-resistant layer and said buried silicon oxide layer as a mask;forming a substrate-side capacitor electrode within said semiconductor substrate on an inner surface of said third trench;removing said sidewall oxidation-resistant layer after said substrate-side capacitor electrode is formed;forming a capacitor insulating layer on said substrate-side capacitor electrode after said oxidation-resistant layer is removed;burying a capacitor electrode in said first, second and third trenches after said capacitor insulating layer is formed;forming first and second source/drain regions within said semiconductor substrate, said second source/drain region being in contact with said capacitor electrode through said buried silicon oxide layer; andgrowing a silicide layer on said second source/drain region and said capacitor electrode.