Patent ID: 7054959
Filing Date: 2006-05-30
Classification: G06F

Abstract:
1. A data transfer control device for data transfer through a bus, comprising: a transfer number reservation register which is used by a processing section to reserve a number of transfers for an isochronous packet which includes isochronous data and is transferred to a first bus side in an isochronous transfer cycle; and a first memory access control circuit which reads an isochronous packet from a first memory and automatically transfers the thus-read isochronous packet to the first bus side in the isochronous transfer cycle, until the number of transfers which is reserved in the transfer number reservation register reaches zero, and wherein: a storage area of the first memory includes a header area and a data area; the header area includes Kth and Lth page areas; the transfer number reservation register includes transfer number reservation registers for the Kth and Lth pages, for reserving a number of transfers for the Kth and Lth page areas; and while the processing section is preparing an isochronous header to be written to the Kth page area, the first memory access control circuit reads an isochronous header written to the Lth page area and isochronous data written to the data area, and automatically transfers an isochronous packet configured of the thus-read isochronous header and isochronous data, to the first bus side in each isochronous transfer cycle, until a number of transfers which is reserved in the transfer number reservation register for the Lth page reaches zero.