Patent ID: 6144708
Filing Date: 2000-11-07
Classification: H03D,H04L

Abstract:
A phase-locked loop circuit with an equalizer, said phase-locked loop circuit that corrects an influence due to a phase error on a radio data communication terminal which equalizes received signals by obtaining a transmission line characteristic during a preamble duration in a narrow band modulation mode, comprising:received signal reproducing means for reproducing a real part amplitude value and an imaginary part amplitude value based on tap coefficients set to said equalizer and data demodulated by said equalizer, said real part amplitude value and said imaginary part amplitude value each being a received signal before demodulation;timing means for providing timing to a reproduced received signal obtained by delaying and reproducing said receive signal;phase difference detecting means for detecting a phase difference between said reproduced received signal and said delayed received signal before demodulation;weighting means for weighting in a given ratio to remove an influence of distortion due to noises;integrating means for integrating the phase difference in symbol units;vector converting means for converting an integrated value into a cosine value and a sine value; andphase correcting means for correcting the phase of said demodulated received signal based on said cosine value and said sine value.