Patent ID: 8350387
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A semiconductor storage device comprising: a memory cell transistor formed on a semiconductor substrate; a selective transistor which is formed on the semiconductor substrate and whose source is connected to a drain of the memory cell transistor; a first interlayer insulating film which is formed on the semiconductor substrate and which covers the memory cell transistor and the selective transistor; a first insulating layer formed on the first interlayer insulating film by use of a material higher in dielectric constant than the first interlayer insulating film; a second insulating layer formed on the first insulating layer and including a material lower in dielectric constant than the first insulating layer; a contact plug which penetrates the first insulating layer and which is provided in the first interlayer insulating film and which is electrically connected to a drain of the selective transistor; and a bit line which is formed on the first insulating layer, which is extended along the memory cell transistor and the selective transistor and which is in contact with the contact plug, wherein, in a cross section of the bit line, a bottom surface of the bit line is located lower than an upper surface of the contact plug, the bit line is in contact with a side surface of the contact plug and is in direct contact with an upper surface of the first insulating film, and the bit line is also in contact with a side surface of the second insulating layer.