Patent ID: 6483139
Filing Date: 2002-11-19
Classification: G11C,H01L

Abstract:
A semiconductor memory device formed on a semiconductor substrate, comprising:a memory cell having an MOS transistor and a capacitor connected in series for storing a data signal, wherein said MOS transistor includes a gate insulating film formed on a surface of said semiconductor substrate, a gate electrode formed on a surface of the gate insulating film, and an impurity diffusion region formed on the surface of said semiconductor substrate on either side of the gate electrode, said capacitor includes an impurity diffusion region formed on the surface of said semiconductor substrate, an insulating film formed on a surface of the impurity diffusion region, and a plate electrode formed on a surface of the insulating film for receiving a reference potential, and the gate electrode of said MOS transistor and the plate electrode of said capacitor are formed by a same interconnection layer.