Patent ID: 7751270
Filing Date: 2010-07-06
Classification: G11C

Abstract:
1. A method for operating a memory device comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, comprising the steps of: a) determining an actual value of a bit integrity parameter of the memory cells, said actual value taking into account the standby voltage which is actually supplied to the memory cells and environmental changes which are experienced by the memory device in use, b) comparing said actual value with a predetermined minimal value of the bit integrity parameter, said predetermined minimal value taking into account possible variations in cell properties as a result of process variations, said comparison yielding a comparison result, c) adjusting the standby voltage towards a more optimal value based on said comparison result, such that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value.