Patent ID: 6197693
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method for forming a gate electrode of a semiconductor device comprising the steps of:forming, in turn, a layer of polysilicon, an etching stopping layer and a sacrificed layer over a semiconductor substrate (first step);selectively etching the sacrificed layer, the etching stopping layer and the polysilicon layer to form a pattern of the gate electrode (second step);performing a thermal oxidation process in order to compensate for etching damage generated (third step);forming an inter-layer insulating layer over the entire structure after completion of the thermal oxidation and partially removing the interlayer insulating layer until the sacrificed layer is exposed (fourth step);removing the sacrificed layer and the etching stopping layer to form an opening through which the polysilicon layer is exposed (fifth step);forming a layer of metal over the entire structure after forming the opening (sixth step); andselectively removing the metal layer to remain the metal layer only in the opening, thereby, forming the gate electrode made of the polysilicon layer and the metal layer (seventh step).