Patent ID: 8941172
Filing Date: 2015-01-27
Classification: G11C,H01L

Abstract:
1. A non-volatile memory device, comprising: a first vertical channel layer and a second vertical channel layer, both of which, generally protrude upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer above the semiconductor substrate and configured to couple the first vertical channel layer and the second vertical channel layer; and stack layers formed along outer walls of the first vertical channel layer, the second vertical channel layer and the pipe channel layer, wherein the pipe channel layer includes an extension part passing through the stack layers and coupled to the semiconductor substrate.