Patent ID: 6423581
Filing Date: 2002-07-23
Classification: H01L,Y10T

Abstract:
A method of encapsulating an integrated circuit with an encapsulant comprising:providing a die; providing a first solder resist layer; forming a first conductive layer over the first solder resist layer; forming at least one continuous laminate layer over the first conductive layer; forming at least one cavity laminate layer over the at least one continuous laminate layer, so as to define an underlying cavity; forming at least one ledge laminate layer over the at least one cavity laminate layer, so as to define a void portion having a width less than a width of the underlying cavity; forming a second conductive layer over the at least one ledge laminate layer, so as to define a void portion aligned with the void portion of the at least one ledge laminate layer; forming a second solder resist layer over the second conductive layer, so as to define a void portion aligned with the void portion of the second conductive layer, wherein the void portion of the second solder resist layer, the void portion of the second conductive layer, the void portion of the at least one ledge laminate layer and the underlying cavity form a void having a varying profile; placing the die over the second solder resist layer; and forming the encapsulant over the die and at least a portion of the second solder resist layer and forming the encapsulant in the void such that the void is substantially filled and the encapsulant bonds with the continuous laminate layer.