Patent ID: 7245624
Filing Date: 2007-07-17
Classification: H04L

Abstract:
1. A processor comprising: scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements, the scheduling circuitry being configurable for utilization of at least one time slot table in scheduling the data blocks for transmission; and an interval computation element associated with the scheduling circuitry and operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table, a particular location in the time slot table being assigned to one or more of the transmission elements as a function of both a current time and the transmission interval, the transmission interval being adjustable under control of the interval computation element so as to facilitate maintenance of a desired service level for one or more of the transmission elements; wherein the scheduling circuitry comprises a hardware-implemented scheduler; wherein the interval computation element comprises a software-implemented element external to the hardware-implemented scheduler; and wherein adjustment of the transmission interval by the interval computation element allows the hardware-implemented scheduler to support at least one scheduling algorithm not otherwise supported by the hardware-implemented scheduler alone.