Patent ID: 8889522
Filing Date: 2014-11-18
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device having a plurality of capacitors comprising: embedding a gate material in an insulating layer; forming a plurality of metal contacts; forming first and second capacitors, wherein each of the capacitors comprises: a lower electrode formed from a first metal layer; forming a dielectric so as to cover the surface of the lower electrode; and forming an upper electrode from a second metal layer formed on the dielectric; connecting each of the lower electrodes of the first and second capacitors to a first gate material via the metal contacts, wherein the first and second capacitors are connected in series via the first gate material; forming third and fourth capacitors, each capacitor comprising: a lower electrode; forming a dielectric so as to cover the surface of the lower electrode; and forming an upper electrode formed on the dielectric, wherein the third and fourth capacitors are connected in series via second gate material; and connecting each of the lower electrodes of the third and fourth capacitors to a second gate material via the metal contacts, wherein the third and fourth capacitors are connected in series via the second gate material, wherein the upper electrodes of the second capacitor and the fourth capacitor share a common metal portion, and wherein the common metal portion is electrically coupled to a first voltage terminal through a first metal plate; and wherein the upper electrodes of the first capacitor and the third capacitor are eiectrically coupled to a second voltage terminal through a second metal plate.