Patent ID: 8497702
Filing Date: 2013-07-30
Classification: H03K

Abstract:
1. An integrated circuit comprising: an array of interconnected configurable processing logic elements, each logic element performing data processing controlled by a configuration stored in said logic element; and a power controller formed of one or more of said logic elements configured to serve as said power controller and generating one or more power control signals; wherein said array contains one or more regions each containing one or more of said logic elements; each region having a corresponding region controller responsive to at least one of said one or more power control signals to switch said one or more logic elements within said region between a plurality of different power states; and said one or more regions each include said one or more of logic elements and said region controller controls said power state for said one or more logic elements within said region, wherein said power controller is responsive to power state demands of logic elements within a region to generate said one or more power control signals for said region corresponding to all logic elements within said region having a highest power state currently required by any of said logic elements within said region.