Patent ID: 6191446
Filing Date: 2001-02-20
Classification: H01L,Y10S

Abstract:
An integrated circuit comprising:a trench arranged within a semiconductor substrate;a pair of gate dielectrics arranged upon a pair of opposed sidewall surfaces of the trench, wherein a first gate dielectric is arranged upon a first opposed sidewall surface and a second gate dielectric is arranged upon a second opposed sidewall surface;a first gate conductor arranged within the trench and spaced from the first opposed sidewall surface of the trench by the first gate dielectric, wherein the first gate conductor comprises a first pair of opposed lateral surfaces;a second gate conductor arranged within the trench and spaced from the second opposed sidewall surface of the trench by the second gate dielectric, wherein the second gate conductor comprises a second pair of opposed lateral surfaces; anddielectric sidewall spacers arranged upon the first pair of opposed lateral surfaces and the second pair of opposed lateral surfaces.