Patent ID: 6426895
Filing Date: 2002-07-30
Classification: G11C

Abstract:
A memory system in which a program is completed with a page as a unit, comprising:an intermediate circuit successively holding program data that forms said page in a division unit where the program data are divided into a plurality of division units; a memory-cell array in which a plurality of memory cells, each including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in said charge accumulating means, and at least one selection transistor having a shared channel formation region and said memory transistor are arranged, and in which the plurality of memory cells arranged in the direction of a word line are connected in a cascade connection; word lines to which a gate of the selection transistor of each memory cell cascade-connected in the direction of said word line are commonly connected; and a control circuit successively reading the divided unit data held in said intermediate circuit when programming, electrically dividing said memory-cell array in every interval of a plurality of the memory cells in response to said division unit in the direction of the word line by driving the control gate of said memory transistor, and writing said division unit data to said memory-cell array by parallelly applying programming pulses to the control gates of the memory transistors in a predetermined bit unit.