Patent ID: 6577539
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array including memory cells arranged in matrix form having row lines and column lines, each of the memory cells including a cell transistor having a floating gate and a control gate, and storing data in accordance with a storage state of charges of the floating gate, the memory cells in the same row being commonly connected to one of the row lines, the memory cells in the same column being commonly connected to one of the column lines; row selection means, connected to the row lines, for selecting one of the row lines; programming means for programming a memory cell, the programming means injecting electrons to a floating gate to program desired data to the memory cell; and programming voltage generating means, connected to the row selection means, for generating a programming voltage for injecting electrons to the floating gate, the programming voltage being generated at a first node, the programming voltage generating means including a transistor and voltage control transistors, the transistor having a drain, a source and a gate, the transistor being connected between the first node and a power supply node, wherein the programming voltage has a plurality of voltage levels, the voltage levels of the programming voltage are generated by selectively turning on the voltage control transistors and changing a gate voltage of the transistor, the programming voltage is applied to the row selection means, and the programming voltage having one of the voltage levels is applied to the selected row line by the row selection means to inject electrons to the floating gate.