Patent ID: 6627523
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A method of forming a metal wiring in a semiconductor device, comprising the steps of;forming a seed layer on a semiconductor substrate in which given structures including a lower metal wiring are formed, wherein said seed layer is formed of one of aluminum, titanium, and tungsten; forming a photosensitive film on said seed layer; patterning said photosensitive film to expose said seed layer on a portion in which said lower metal wiring is formed; forming a metal layer on said exposed seed layer by an electroplating method; removing said photosensitive film; forming a diffusion barrier layer on the entire structure including said metal layer; sequentially etching said diffusion barrier layer and said seed layer by a blanket etch process, thereby forming an upper metal wiring in which said seed layer remains below said metal layer and a diffusion barrier layer spacer remains on a sidewall of said metal layer; and forming an insulating film on the entire structure including said upper metal wiring, and then performing a planarization process to expose a top of said upper metal wiring.