Patent ID: 6030897
Filing Date: 2000-02-29
Classification: H01L,Y10S

Abstract:
A method of forming an alignment mark in a planar semiconductor IC structure to be used in a subsequent lithographic step comprising the steps of:a) providing a structure comprised of a semiconductor substrate having at least one shallow trench in a first region of the substrate and at least one shallow alignment trench in a second region of the substrate;b) conformally depositing a layer of a filling material onto the structure adequate to overfill the shallow trenches so that respective depressions are created in said filling material above the locations of said trenches;c) planarizing the structure with a planarizing medium to fill the depression over the trench formed in the first region, said depression formed over said alignment trench in the second region being preserved; and,d) uniformly etching back the structure down to the surface of the substrate to transfer only said depression formed above the alignment trench in said filling material creating thereby a recess therein that can be used as an alignment mark for said photolithographic step.