Patent ID: 6367065
Filing Date: 2002-04-02
Classification: G06F,G11C,H03K

Abstract:
A design tool to design a N-NARY logic circuit, comprising:a syntax statement, said syntax statement further comprises encoded information describing the desired logical function of the N-NARY logic circuit and encoded information describing a specific transistor configuration that further comprises a precharge circuit, an evaluation circuit, a plurality of output drivers, and a shared logic tree circuit having multiple evaluation paths wherein one and only one evaluation path is active during an evaluation cycle, said shared logic tree circuit receives one or more 1-of-N input signals and produces one or more 1-of-N output signals; and a compiler that processes and decodes said syntax statement, said compiler produces from said syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of said shared logic tree circuit, said precharge circuit, said evaluation circuit, and said plurality of output drivers.