Patent ID: 9088277
Filing Date: 2015-07-21
Classification: H03K

Abstract:
1. An output driver circuit comprising: an electrically conductive medium; an output logic inverter stage having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the electrically conductive medium; a first biasing network having a first input that is coupled to the electrically conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each respective input of the first and the second switch, the second positive supply voltage being greater than the first positive supply voltage, wherein, based on the second switch coupling the electrically conductive medium to the ground supply voltage and the received clock signal generating a logic low, the first biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch; a clocking source that receives the clock signal and generates an inverted version of the clock signal, wherein the clocking source includes a logic inverter; an input logic inverter stage coupled to the output logic inverter stage, the input logic inverter stage having a fifth switch adapted to couple the first positive supply voltage to the each respective input of the first and the second switch, and a sixth switch adapted to couple the ground supply voltage to the each respective input of the first and the second switch; and a seventh switch coupled between the first positive supply voltage and the fifth switch, wherein the seventh switch receives the inverted version of the clock signal.