Patent ID: 6071804
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A method of fabricating bit lines by damascene, comprising:providing a substrate having a first dielectric layer;forming a first hard material layer on the first dielectric layer;patterning the first hard material layer and the first dielectric layer to form a bit line contact window in the first dielectric layer and the first hard material layer, so as to expose a portion of the substrate;forming a first conductive layer in the bit line contact window to serve as a bit line contact;forming a second dielectric layer over the first hard material layer;patterning the second dielectric layer to form an opening in the second dielectric layer to expose the first conductive layer in the bit line contact window and a portion of the first hard material layer;forming a hard material spacer on each sidewall of the opening of the second dielectric layer; andforming a second conductive layer in the opening to serve as the bit line.