Patent ID: 6016533
Filing Date: 2000-01-18
Classification: G06F

Abstract:
A cache array comprising:a plurality of memory locations;a plurality of storage locations, wherein each storage location is configured to store a way prediction, wherein a first portion of a requested address selects a set of way predictions;a decoder coupled to said plurality of memory locations and said plurality of storage locations, wherein said decoder is configured to receive and decode a second portion of said requested address, wherein said decoder is configured to select a first subset of said plurality of memory locations based upon said second portion of said requested address and said set of way predictions;a plurality of pass transistors coupled to said plurality of memory locations, wherein said plurality of pass transistors are configured to receive a third portion of said requested address, wherein said plurality of pass transistors are configured to select a second subset of said plurality of memory locations based upon said third portion of said requested address;a sense amp unit coupled to said plurality of pass transistors, wherein said sense amp unit is configured to read the contents of any memory locations that are located within an intersection of said first subset and said second subset; anda column select decoder coupled to said plurality of pass transistors and configured received and decode said third portion of said requested address, wherein said column select decoder is configured to enable a set of pass transistor within said plurality of pass transistors based upon said decoded third portion of said requested address.