Patent ID: 6912560
Filing Date: 2005-06-28
Classification: G06F

Abstract:
1. An adder comprising: a plurality of computational stages each associated with one or more bit positions of the adder, the plurality of computational stages including one or more computational stages for generating a sum output signal and a primary carry-output signal of the adder; and a flag generation circuit coupled to at least one signal line of at least one of the computational stages and operative to generate an overflow flag for the adder, the overflow flag being separate and distinct from the primary carry-output signal, the overflow flag being generated utilizing a transmit signal and a generate signal of the adder; wherein the adder comprises an n-bit adder and the primary carry-output signal comprises a primary carry-output signal c n−1 of the n-bit adder, and wherein the transmit signal and generate signal are (n−1)th transmit signal and (n−1)th generate signal respectively of the n-bit adder.