Patent ID: 9136333
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a first conductive type, wherein the semiconductor substrate includes a first surface and a second surface opposite to the first surface, and the semiconductor substrate has a first portion and a second portion; a drift layer having the first conductive type, wherein the drift layer is disposed in a surface portion of the first surface of the semiconductor substrate; a vertical MOSFET disposed in the first portion of the semiconductor substrate; and an accumulation FET for operating in an accumulation mode and disposed in the second portion of the semiconductor substrate, wherein the vertical MOSFET includes: the drift layer; a base layer having a second conductive type, wherein the first conductive type is different from the second conductive type, wherein the base layer is disposed in the drift layer; a source region having the first conductive type, wherein the source region is disposed in the base layer in such a manner that the source region is separated from the drift layer by the base layer; a first gate insulation film disposed between the source region and the drift layer through the base layer; a first gate electrode disposed on the first gate insulation film, wherein the first gate electrode provides a channel in a part of the base layer, which contacts the first gate insulation film; a source electrode electrically coupling with the source region and the base layer; and a drain electrode disposed on the second surface of the semiconductor substrate, and the accumulation FET includes: a second trench disposed in the drift layer; a second gate insulation film disposed on an inner wall of the second trench; and a second gate electrode disposed on the second gate insulation film in the second trench, wherein a part of the drift layer contacting the second trench is coupled with the source electrode of the vertical MOSFET, wherein the first gate electrode and the second gate electrode are independent from each other so that different voltages are applicable to the first gate electrode and the second gate electrode, respectively.