Patent ID: 6084442
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A digital oscillator for generation of a target clock signal by dividing a working clock signal where each pulse has a positive going edge and a negative going edge, comprising: a first divider circuit which is clocked by the positive going edge of the working clock signal and divides the working clock signal by a first division factor; a second divider circuit which is clocked by the negative going edge of the working clock sign and divides the working clock signal by a second division factor; a first controlled switch which alternately directs a control word to the first and second divider circuits; a second controlled switch that alternately selects an output of the first and second divider circuits to form the target clock signal; each divider circuit having a logic module which detects occurrence of the edge of the control word and stores this event, with this event triggering a division by the second division factor and a common control circuit coupled to the first and second divider circuits and the first and second controlled switches to synchronize the operation of the divider circuits with the controlled switches.