Patent ID: 8232203
Filing Date: 2012-07-31
Classification: H01L

Abstract:
1. A method of manufacturing a memory device, the method comprising: providing a substrate; forming a number of memory sectors on the substrate, each of the memory sectors coupled to an adjacent one via a first diffused region in the substrate and coupled to another adjacent one via at least one second diffused region in the substrate; forming a first dielectric layer on the memory sectors; forming a first conductive structure through the first dielectric layer to the first diffused region, and forming at least one second conductive structure through the first dielectric layer to the at least one second diffused region; forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure; etching back the first conductive structure; removing the patterned first mask layer; forming a second dielectric layer on the first dielectric layer and the at least one second conductive structure; and leveling the second dielectric layer, wherein leveling the second dielectric layer exposes the at least one second conductive structure, further comprising: