Patent ID: 9130520
Filing Date: 2015-09-08
Classification: G05F,H01L,H03F,H04L

Abstract:
1. A differential output circuit comprising: a differential pair including a first transistor and a second transistor which respectively receive input signals having mutually reversed phases; a third transistor and a fourth transistor respectively cascode-coupled to the first transistor and the second transistor, and having the same conductivity type as the first transistor and the second transistor; a first output terminal and a second output terminal coupled to respective drains of the third transistor and the fourth transistor; a voltage divider circuit which divides an intermediate potential between respective potentials of the first output terminal and the second output terminal and supplies the divided potential to respective gates of the third transistor and the fourth transistor; two buffer circuits which supply the respective input signals to respective gates of the first transistor and the second transistor; and a power supply circuit which lowers a first power supply voltage and supplies the lowered voltage to the two buffer circuits as a second power supply voltage.