Patent ID: 8364434
Filing Date: 2013-01-29
Classification: H03F

Abstract:
1. A calibration circuit for adjusting an impedance of an output buffer having a pull-up circuit and a pull-down circuit, the calibration circuit comprising: a first replica buffer provided correspondingly to one of the pull-up circuit and the pull-down circuit; and a second replica buffer provided correspondingly to the other of the pull-up circuit and the pull-down circuit, wherein in response to an issuance of a first calibration command, a calibration operation is performed on one of the first and second replica buffers while postponing performing the calibration operation on the other of the first and second replica buffers until a subsequent issuance of the first calibration command, and in response to an issuance of a second calibration command, the calibration operation is performed on both the first replica buffer and the second replica buffer.