Patent ID: 7839177
Filing Date: 2010-11-23
Classification: H03D

Abstract:
1. A phase detector comprising: transistors that generate first and second phase error signals, wherein the phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path, wherein the phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path, wherein a first subset of the transistors are coupled between a supply voltage terminal and a ground terminal, wherein a second subset of the transistors are coupled between a supply voltage terminal and a ground terminal, wherein the first reset path comprises at least one transistor in the first subset and at least one transistor in the second subset, wherein a third subset of the transistors are coupled between a supply voltage terminal and a ground terminal, wherein a fourth subset of the transistors are coupled between a supply voltage terminal and a ground terminal, and wherein the second reset path comprises at least one transistor in the third subset and at least one transistor in the fourth subset; a first inverter coupled to an output terminal of the second subset of transistors and to input terminals of the first and the third subsets of transistors, wherein the first reset path comprises the first inverter; and a second inverter coupled to an output terminal of the fourth subset of transistors and to input terminals of the first and the third subsets of transistors, wherein the second reset path comprises the second inverter.