Patent ID: 7346643
Filing Date: 2008-03-18
Classification: G06F

Abstract:
1. A floating-point unit (FPU) configurable to perform multiply-add (Madd) operations comprising: a multiplier unit configured to receive and multiply mantissas for first and second floating-point operands to generate a multiplier output mantissa for a floating-point product of the first and second floating-point operands, wherein the multiplier unit is further configurable to operate in a first operating mode defined by the multiplier output mantissa being rounded, not normalized or denormalized, and having a pseudo-normalized format and a range greater than a normalized mantissa; and an adder unit coupled to the multiplier unit, the adder unit configured to receive and combine the multiplier output mantissa for the floating-point product and a mantissa for a third floating-point operand to generate an FPU output mantissa for a floating-point Madd result.