Patent ID: 6784705
Filing Date: 2004-08-31
Classification: H03G,H03K

Abstract:
A power on reset circuit comprising:a power supply line; a first port to which a power-saving mode signal is input; a second port from which a reset signal is output; a signal generator which is controlled in accordance with the power-saving mode signal to generate a control signal; an edge generator which is controlled in accordance with the control signal to generate an edge signal; a first delay circuit which outputs a delayed power-saving mode signal obtained by delaying the power-saving mode signal; a charging circuit which is controlled in accordance with the delayed power-saving mode signal to speed up an increase of a level of the control signal; and an output inhibit circuit coupled to the output of the edge generator and which outputs an edge waveform as a reset signal from said second port during a period of changing from a power-off state, in which no power is supplied to said power supply line, to a power-on state, in which power is supplied to said power supply line, and does not output the reset signal from said second port when a voltage of the power-saving mode signal is changed.