Patent ID: 6764901
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A method of fabricating a memory array, the method comprising:forming from a single unbonded substrate a number of access transistors separated by trenches, each access transistor formed in a pillar of semiconductor material that extends outwardly from the single unbonded substrate wherein each access transistor includes, in order, a first source/drain region, a body region and a second source/drain region formed vertically thereupon; filling the trenches with a polysilicon layer, the polysilicon layer having a top surface below a top surface of the body region; forming a nitride layer over the access transistors and the polysilicon layer; removing first portion of the nitride layer and the entire polysilicon layer to form a plurality of bridges, each of the bridges including second portion of the nitride layer, each of the bridges extending through a column of access transistors; forming a trench capacitor in the trenches, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor, wherein the trench capacitor is formed directly on the single unbonded substrate; forming a number of word lines in the trenches that separate adjacent rows of access transistors, wherein each trench includes two word lines with a gate of each word line interconnecting alternate access transistors on opposite sides of the trench; forming a number of bit lines that interconnect second source/drain regions of selected access transistors.