Patent ID: 7652917
Filing Date: 2010-01-26
Classification: G11C,H01L

Abstract:
1. A semiconductor device having a nonvolatile memory cell, comprising: a semiconductor substrate; a first well having a first conductivity type and formed in the semiconductor substrate; a second well having a second conductivity type opposite to the first conductivity type and formed in the first well; a third well having the second conductivity type, formed in the first well and electrically separated from the second well; and a floating gate formed over the second and third wells, wherein the nonvolatile memory cell has an element for programming and erasing data arranged over the second well and a capacitor element arranged over the third well, wherein the element for programming and erasing data includes: a first portion of the floating gate formed over the second well; a first impurity region formed in the second well and having the first conductivity type; a second impurity region formed in the second well, having the second conductivity type and having a higher concentration than the first impurity region; a third impurity region formed in the second well and having the second conductivity type; and a fourth impurity region formed in the second well, having the second conductivity type and having a higher concentration than the third impurity region, wherein the capacitor element includes: a second portion of the floating gate formed over the third well; a fifth impurity region formed in the third well and having the first conductivity type; a sixth impurity region formed in the third well, having the first conductivity type and having a higher concentration than the fifth impurity region; a seventh impurity region formed in the third well and having the second conductivity type; and an eighth impurity region formed in the third well, having the second conductivity type and having a higher concentration than the seventh impurity region, wherein the first and second impurity regions are arranged on a first side of the floating gate, wherein the third and fourth impurity regions are arranged on a second side opposite to the first side of the floating gate, wherein the first and second impurity regions are physically away from the third and fourth impurity regions, wherein the fifth and sixth impurity regions are arranged the on the first side of the floating gate, wherein the seventh and eighth impurity regions are arranged on the second side of the floating gate, and wherein the fifth and sixth impurity regions are physically away from the seventh and eighth impurity regions.