Patent ID: 7894274
Filing Date: 2011-02-22
Classification: G11C

Abstract:
1. A memory with improved write current, comprising: a bit line, having a first terminal and a second terminal; a first write switch, having a first terminal, a second terminal and a control terminal, wherein the first and second terminals of the first write switch are coupled to a first voltage source and the first terminal of the bit line, respectively, and there is a parasitic capacitor between the first terminal and the control terminal of the first write switch; a first control circuit, receiving a bit line select signal and coupled to the control terminal of the first write switch, wherein the first control circuit discharges the first parasitic capacitor when the bit line select signal is disabled, the first control circuit charges the first parasitic capacitor and turns on the first write switch when the bit line select signal is enabled, and the first voltage source is actuated after the control terminal of the first write switch reaches a pre-determined voltage level.