Patent ID: 6130906
Filing Date: 2000-10-10
Classification: H04B

Abstract:
A parallel-code-matched filter, responsive to a combined-spread-spectrum signal having a plurality of linearly combined spread-spectrum signals, with each spread-spectrum signal including a plurality of symbols, with each symbol having a symbol-time duration, with each symbol having a chip-sequence signal different from a multiplicity of chip-sequence signals used by symbols embedded in other spread-spectrum signals of the plurality of linearly-combined spread-spectrum signals, said parallel-code-matched filter for detecting, during the symbol-time duration, a combined multiplicity of symbols from the plurality of linearly combined spread-spectrum signals arriving in parallel at the parallel-code-matched filter, comprising:a demultiplexer for demultiplexing, sequentially, a sequence of the combined multiplicity of symbols, occurring during the symbol-time duration;a plurality of symbol registers, coupled to said demultiplexer, with each symbol register sequentially selected by said demultiplexer, for storing a combined multiplicity of chip-sequence signals, occurring during the symbol-time duration, corresponding to the combined multiplicity of symbols, occurring during the symbol-time duration, of the plurality of linearly-combined spread-spectrum signals;a first multiplexer, coupled to said plurality of symbol registers, for selecting a selected-shift register from the plurality of symbol registers, with the selected-shift register not simultaneously selected by said demultiplexer;a shift-left register, coupled to said first multiplexer, for shifting left the combined multiplicity of chip-sequence signals stored in said selected-shift register;a shift-right register, coupled to said first multiplexer, for shifting right the combined multiplicity of symbols stored in said selected-shift register;a second multiplexer, coupled to said first multiplexer, to said shift-left register and to said shift-right register, for selecting sequentially one of the selected-shift register, the shift-right register and the shift-left register;a reference register for storing a plurality of replicas of the chip-sequence signals embedded in the plurality of linearly-combined spread-spectrum signals;a reference multiplexer, coupled to said reference register, for sequentially selecting, during the symbol-time duration, each of the plurality of replicas of the chip-sequence signals;an EXCLUSIVE-OR (XOR) bank, coupled to said second multiplexer and to said reference multiplexer, for comparing the combined multiplicity of chip-sequence signals stored in one of said selected-shift register, said shift-left register and said shift-right register, as selected by said second multiplexer, with each of the plurality of replicas of the chip-sequence signals as sequentially selected by said reference multiplexer, and for generating a plurality of outputs; andan adder tree, coupled to said XOR bank, for adding the plurality of outputs from said XOR bank, thereby generating an output signal.