Patent ID: 8046649
Filing Date: 2011-10-25
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate, the functional circuits including at least one set of IP core circuits, the IP core circuits including: a. a test data input lead extending beyond the periphery of the core functional circuits; b. a test data output lead extending beyond the periphery of the core functional circuits; c. a test clock lead extending beyond the periphery of the core functional circuits; d. a test mode select lead extending beyond the periphery of the core functional circuits; e. a second test data input lead extending beyond the periphery of the core functional circuits; f. a second test data output lead extending beyond the periphery of the core functional circuits; g. control signal leads extending beyond the periphery of the core functional circuit; and h. external register present leads extending beyond the periphery of the core functional circuit; and C. first scan circuits serially formed on the substrate outside of the periphery of the IP core circuits, the first scan circuits being formed between and connecting together the core functional input leads and the rest of the functional circuits, the first scan circuits being formed between and connecting together the core functional output leads and the rest of the functional circuits, and the first scan circuits being connected to the second test data input lead, the second test data output lead, and the control signal leads; and D. second scan circuits formed on the substrate outside of the periphery of the IP core circuits, the second scan circuits being separate from the first scan circuits, and the second scan circuits being connected to the second test data input lead, the second test data output lead, and the control signal leads.