Patent ID: 6268992
Filing Date: 2001-07-31
Classification: H01L

Abstract:
An electrostatic discharge (ESD) protection circuit using a parasitic silicon controlled rectifier (SCR) in a CMOS circuit, comprising:a semiconductor wafer with a p-substrate;an n-well in said p-substrate;an n.sup.+ source in said p-substrate;a p.sup.+ contact region in said p-substrate;said p.sup.+ contact region and said n.sup.+ source connected to a reference voltage;a p.sup.+ source in said n-well;a first n.sup.+ contact region in said n-well;a second n.sup.+ contact region in said p-substrate;a capacitance between said second n.sup.+ contact region and said p-substrate to couple an AC current from an electrostatic discharge into said p-substrate;said p.sup.+ source, said first and said second n.sup.+ contact region connected to a voltage supply;a parasitic pnp bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector formed by said p.sup.+ source, said n-well, and said p-substrate, respectively;a parasitic npn bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector formed by said n.sup.+ source, said p-substrate, and said n-well, respectively;a first parasitic resistor created in said n-well, said first parasitic resistor extending between said first n.sup.+ contact region and said base of said parasitic pnp transistor;a second parasitic resistor created by said p-substrate, said second parasitic resistor extending between said p.sup.+ contact region and said base of said parasitic npn transistor; andan SCR comprised of said parasitic bipolar transistors, said base of said parasitic pnp bipolar transistor connected to said collector of said parasitic npn bipolar transistor, and said collector of said parasitic pnp bipolar transistor connected to said base of said parasitic npn bipolar transistor.