Patent ID: 7120060
Filing Date: 2006-10-10
Classification: G11C

Abstract:
1. A method for trimming a flash reference cell located in a memory array of a memory device, the method comprising: erasing the flash reference cell below a desired Vt level; applying a first program pulse having a predetermined voltage level and is applied for a predetermined period of time to the flash reference cell to increase a floating gate charge of the flash reference cell; accessing the flash reference cell to create a cell current in a bitline coupled to a drain of the reference cell; comparing, with a sense amplifier, the cell current with an externally provided constant reference current, wherein the constant reference current is indicative of a desired memory cell current; and applying further program pulses to the flash reference cell, while maintaining the constant reference current, when the cell current is less than the reference current until a digital output of the sense amplifier changes state to indicate that the flash reference cell is programmed to a desired level, each further program pulse having the predetermined voltage level and is applied for the predetermined period of time without change in the predetermined voltage level or predetermined period of time from the first program pulse such that all program pulses experienced by the flash reference cell are at the predetermined voltage level and for the predetermined period of time.