Patent ID: 6199150
Filing Date: 2001-03-06
Classification: G06F

Abstract:
A data memory apparatus, comprising:at least one high-speed memory device and at least one low-speed memory device forming a memory map including at least a first memory area to which the at least one high-speed memory device is assigned and a second memory area to which the at least one low-speed memory device is assigned;an access control unit for controlling access to the at least one high-speed memory device and the at least one low-speed memory device;a high-speed bus which provides high speed data transfer between the at least one high-speed memory device and the access control unit, the high-speed bus being relatively short in length and located in relatively close physical proximity to the access control unit;a low-speed bus which provides low speed data transfer between the at least one low-speed memory device and the access control unit, the low-speed bus being relatively long in length and located in relatively remote physical proximity to the access control unit;whereby an access speed to the first memory area is faster than an access speed to the second memory area.