Patent ID: 7532521
Filing Date: 2009-05-12
Classification: G11C

Abstract:
1. A flash memory device comprising: a nonvolatile memory core; and a buffer memory to temporarily store data for the nonvolatile memory core; wherein the buffer memory is divided into first and second mats, each mat including a plurality of wordlines and bitlines; wherein a bit of data can be transferred from the second mat while columns of the first mat are being precharged; and wherein after the last data bit belonging to a first active row of the first mat is transferred during an (N−1)th cycle of a clock signal, the first active row of the first mat is deactivated, a first precharge signal is enabled during an Nth cycle of the clock signal to precharge columns of the first mat, and a data bit belonging to a first active row of the second mat is transferred during the Nth cycle of the clock signal.