Patent ID: 6509606
Filing Date: 2003-01-21
Classification: G11C,H01L

Abstract:
A memory cell structure comprising:a semiconductor material having a first conductivity type; spaced-apart source and drain regions formed in the semiconductor material, the source and drain regions having a second conductivity type opposite the first conductivity type and defining a channel region having the first conductivity type therebetween; a well region having the second conductivity type formed in the semiconductor material, the well region being spaced-apart from the source and drain region to define an intervening region of said semiconductor material therebetween, the well region, intervening region of said semiconductor material and the channel region having substantially co-planar upper surfaces; a contact region having the second conductivity type formed in a first central portion of the well region; a unitary region of dielectric material having a first open-rectangle portion formed on the upper surface of the well region around the perimeter of the contact region, a second portion that is connected to the first open-rectangle portion and is formed at the upper surface of the intervening region of said semiconductor material, and a third portion that is connected to the second portion and is formed on the upper surface of the channel region; a unitary region of conductive material having a first open-rectangle portion formed on the first open-rectangle portion of the dielectric material and a second portion that is connected to the first open-rectangle portion and is formed on the second and third portion of the dielectric material; and a perimeter doped region having the first conductivity type that is formed in the semiconductor material and circumscribes the source region, the drain region, the well region and the intervening region.