Patent ID: 6249478
Filing Date: 2001-06-19
Classification: G11C

Abstract:
An address input circuit capable of inputting an address data which has been fixed at the H-level or L-level to an address buffer or capable of inputting an address data from an address pad to the address buffer, comprising:a first circuit having a first fuse between a first node and a first power source and a second fuse between a second power source and the first node, the first node being set at a potential close to the voltage of the first power source;a second circuit having a third fuse between a second node and the first power source and a fourth fuse between the second power source and the second node, the second node being set at a potential close to the voltage of the second power source;a switching transistor wherein the control gate is connected to the second node, the source or drain is connected to the first node and the drain or source is connected to the address buffer; anda fifth fuse connected between the address pad and the address buffer.