Patent ID: 6031402
Filing Date: 2000-02-29
Classification: H03L

Abstract:
A clock synchronizing circuit, comprising:a phase comparator circuit that outputs a first phase error detecting signal based on a time-delayed external clock signal and a feedback clock signal, and a second phase error detecting signal based on a first external clock signal and a time-delayed feedback clock signal;a phase compensator circuit that inputs the first external clock signal and outputs a second external clock signal, wherein the phase compensator circuit has a first mode of operation, in which the phase compensator circuit phase-compensates the first external clock signal to generate the second external clock signal, and a second mode of operation, in which the phase compensator circuit does not phase-compensate the first external clock signal; anda controller that selects one of the first and second modes of operation based on the first and second phase error detecting signals;wherein the time-delayed external clock signal and the time-delayed feedback clock signal are generated by a first time-delay circuit and a second time-delay circuit, respectively, and wherein the first and second time-delay circuits comprise a first and second schmitt trigger, respectively.