Patent ID: 9165865
Filing Date: 2015-10-20
Classification: H01L

Abstract:
1. A power transistor package comprising: a leadframe including a flat plate and a coplanar flat strip spaced from the plate, the plate having a first thickness and the strip having a second thickness smaller than the first thickness, the plate and the strip having terminals; a field-effect power transistor chip having a third thickness, a first and a second contact pad on one chip side, and a third contact pad on the opposite chip side, the first pad being attached to the plate, the second pad being attached to the strip, and the third pad being coplanar with the terminals; and encapsulation compound filling the thickness difference between plate and strip, and spaces between chip and terminals, wherein the compound has a surface coplanar with the plate and the opposite surface coplanar with the third pad and the terminals, the distance between the surfaces being equal to the sum of the first and third thicknesses.