Patent ID: 6037810
Filing Date: 2000-03-14
Classification: H03K

Abstract:
An electronic system comprising:a plurality of delay stages, each delay stage having a first control signal input terminal to receive a respective first input control signal and having a first control signal output terminal to provide a first output control signal in a delayed response to receipt of the respective first input control signal, wherein the first control signal input terminal of each delay stage, except for a first delay stage, is coupled to the first control signal output terminal of another respective one of the plurality of delay stages, and the first control signal input terminal of the first delay stage is for receiving the first input control signal from a signal source; anda plurality of output buffer drivers each coupled to a respective one of the delay stages, each output buffer driver having a first control terminal to receive the first output control signal from the respective one of the delay stages and having a first output terminal for coupling to a load;wherein each delay stage further includes a second control signal input terminal to receive a respective second input control signal and having a second control signal output terminal to provide a second output control signal in a delayed response to receipt of the respective second input control signal, wherein the second control signal input terminal of each delay stage, except for the first delay stage, is coupled to the second control signal output terminal of another respective one of the plurality of delay stages, and the second control signal input terminal of the first delay stage is for receiving the second input control signal from the signal source; andwherein each of the plurality of output buffer drivers further includes a second control terminal to receive the second output control signal from a respective one of the plurality of delay stages and having a second output terminal for coupling to the load.