Patent ID: 8314763
Filing Date: 2012-11-20
Classification: G09G

Abstract:
1. A display device comprising: a panel; a timing controller generating an embedded clock data signal combining image data and a clock signal; and a column driver driving the panel in response to the embedded clock data signal, wherein data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, including a high voltage level representing a first value of a data bit, a low voltage level representing a second value of a data bit, and a middle voltage level representing a value of a data bit that is the same as a previous data bit, wherein the timing controller determines whether a current data bit DIN[n] of the embedded clock data signal has a same value as a previous data bit DIM[n−1] of the embedded clock data signal, wherein, upon determining that the current data bit DIN[n] has the same value as the previous data bit DIN[n−1], the timing controller communicates the current data bit DIN[n] at the middle voltage level, and wherein, upon determining that the current data bit DIN[n] does not have the same value as the previous data bit DIN[n−1], the timing controller communicates the current data bit DIN[n] at the high voltage level to represent the first value, or at the low voltage level to represent the second value.