Patent ID: 6735726
Filing Date: 2004-05-11
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit device comprising:a memory circuit comprising dynamic memory cells each comprising a storage capacitor and an address selection MOSFET, and provided with an information sustaining mode; and a data holding control circuit comprising an additional memory circuit, an ECC circuit and an error rate setting circuit, wherein said ECC circuit operates in said information sustaining mode to carry out a first operation of reading out a plurality of pieces of data from said memory circuit, generating inspection bits for detection and correction of an error existing in said pieces of data and storing said inspection bits into said additional memory circuit and to carry out a second operation of reading out said pieces of data from said memory circuit, reading out said inspection bits from said additional memory circuit and detecting and correcting an error existing in said pieces of data, wherein said error rate setting circuit carries out an error rate monitoring operation of adding a first value according to a first detection signal indicating non-existence of an error detected by said ECC circuit to a total value and subtracting a second value according to a second detection signal indicating existence of an error detected by said ECC circuit from the total value, said second value being larger than said first value, and wherein said error rate setting circuit carries out an error rate setting operation of changing a refresh cycle according to said total value.