Patent ID: 7146592
Filing Date: 2006-12-05
Classification: G06F,H01L,H03K

Abstract:
1. A hierarchical design method of an integrated logic circuit wherein at least one of a plurality of modules of a top level in hierarchical design comprises an internal circuit; and a plurality of external buffer cells, disposed along a periphery of the internal circuit, through which signal input/output is made between the internal circuit and a chip I/O cell or another of the plurality of modules, the method comprising: providing the external buffer cells each having a driving capability for enabling direct driving of a transistor inside the chip through a wire with a maximum Manhattan length in a module-disposed region on the chip: and disposing the plurality of modules and determining position of each of the external buffer cells, based on a temporary wiring between the plurality of modules and between ones of the plurality of modules and the chip I/O cells.