Patent ID: 6524935
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of preparing a relaxed SiGe layer on an insulator comprising the steps of:forming a graded Si1âˆ’xGex epitaxial layer on a first single crystalline semiconductor substrate, where the concentration x of Ge has a value in the range from 0.2 to 0.5 at its upper surface, forming a relaxed Si1âˆ’yGey epitaxial layer over said graded Si1âˆ’xGex layer, where the concentration y of Ge is equal to or about said value x, forming a hydrogen-rich defective layer in said relaxed Si1âˆ’yGey layer via hydrogen bombardment, smoothing the surface of said relaxed Si1âˆ’yGey epitaxial layer to provide a surface roughness in the range from about 0.3 nm to about 1 nm root mean square (RMS), selecting a second substrate having an insulator layer thereover, said insulator layer having a major surface with a surface roughness in the range from about 0.3 nm to about 1 nm RMS, bonding said top surface of said relaxed Si1âˆ’yGey epitaxial layer on said first substrate to the top surface of said insulator layer on said second substrate, said step of bonding including the step of annealing, and separating said relaxed Si1âˆ’yGey layer at said hydrogen-rich defective layer to form a first structure containing said first substrate, said graded Si1âˆ’xGex layer and a relaxed Si1âˆ’yGey layer on the upper surface and a second structure containing said second substrate and said insulator layer with a relaxed Si1âˆ’yGey layer on the upper surface whereby said relaxed SiGe layer on an insulator is formed, said step of separating including a plurality of thermal treatment cycles.