Patent ID: 6373767
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A memory comprising a plurality of storage words, a data line and a plurality of reference lines, and a read circuit,each storage word comprising a data memory cell and a plurality of reference memory cells, each memory cell comprising an isolation transistor and a storage element having first and second terminals for storing a charge, said charge determining a conductivity value measurable between said first and second terminals, said isolation transistor being connected to said first terminal and connecting said first terminal to one of said lines, said first terminal of said data memory cell being connected to said data line and said first terminal of each of said reference memory cells being coupled to a corresponding one of said reference lines when said isolation transistors are in a conducting state, said isolation transistors being placed in said conducting state by a signal on a word line connected to each of said isolation transistors in said storage word, and said read circuit generating a digital value by comparing the conductivity of said data line with a continuous conductivity curve determined by the conductivities of said reference lines.