Patent ID: 6662290
Filing Date: 2003-12-09
Classification: G11C

Abstract:
An address counter comprising a plurality of address counting blocks, wherein each address counting block includes:a first inverting means for receiving and inverting an external address in response to a first control signal and an inverted first control signal; a second inverting means for receiving and inverting a previous internal address in response to a second control signal and an inverted second control signal; a third inverting means for inverting an inverted external address or an inverted previous internal address that is provided from the first or the second inverting means to thereby output an output address; a latching means for latching the inverted external address or the inverted previous internal address; a logic means for generating a parity signal by logically combining an output signal from the latching means and output signals from the latching means of previous address counting blocks; a first transmission gate for providing the second inverting means with a delayed output signal of the latching means as the previous internal address in response to a previous parity signal and an inverted previous parity signal supplied from a preceding address counting block; and a second transmission gate for supplying the second inverting means with an inverted delayed output signal of the latching means as the previous internal address in response to the previous parity signal and the inverted previous parity signal, wherein the first and the second transmission gates inversely operate responsive to the previous parity signal and the inverted previous parity signal.