Patent ID: 7730383
Filing Date: 2010-06-01
Classification: G06F,G11C

Abstract:
1. An error detection circuit for a multilevel memory device including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits, the circuit comprising: an encoding circuit coupled to the memory cells, the encoding circuit to receive a page of bits including a plurality of data words, the encoding circuit operable to arrange the bits of the plurality of data words for storage in the memory cells and to develop error check bits for at least a portion of the plurality of data words, and operable to store the arranged bits and the error check bits in the memory cells, the encoding circuit comprising: a decoding circuit coupled to the memory cells and operable to read the arranged bits of the data words and the error check bits from the memory cells, the decoding circuit providing selected ones of the data words as read from the memory cells and performing error check correction on non-selected ones of the data words using the bits of those non-selected ones of the data words and the check bits read from the memory cells, and providing the other words after performing error checking and correction on those other words.