Patent ID: 8379445
Filing Date: 2013-02-19
Classification: G11C

Abstract:
1. A semiconductor storage device, comprising: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines and arranged in a matrix; and a control circuit configured to control a potential of each of said plurality of word lines and said plurality of bit lines, wherein the control circuit reads data from a memory cell connected to a selected word line at a first read level before an erase operation, calculates a number “a” of memory cells exceeding the first read level, simultaneously erases n number of memory cells (where n is a natural number equal to or greater than 2) included in said plurality of memory cells of the memory cell array using a first erase voltage during an erase operation, performs a verify operation at a first verify level, obtains a number k (k<=a) of cells (where k is a natural number equal to or greater than 1) included in the number “a” and exceeding the first verify level, determines a second erase voltage based on the number “k/a”, and performs a second erase voltage using the second erase voltage.