Patent ID: 6871315
Filing Date: 2005-03-22
Classification: H03M

Abstract:
1. A decoding circuit, for decoding a plurality of code words transmitted in interleaved manner to simultaneously decode a plurality of code words on a reception side, said decoding circuit comprising a decoder which decodes a plurality of said code words simultaneously, wherein said decoder comprises: syndrome calculating means for deriving a syndrome polynomial of the plurality of code words; error position polynomial and error value polynomial leading means for leading an error position polynomial and error value polynomial for the plurality of code words on the basis of coefficients of the syndrome polynomial derived by said syndrome calculating means; error position and error value calculating means for leading an error position and an error value of the code word on the basis of coefficients of the error position and the coefficient of the error value lead by said error position polynomial and error value polynomial leading means; and error correcting means for correcting a received code word on the basis of the error position and the error value lead by said error position and error value calculating means.