Patent ID: 6425115
Filing Date: 2002-07-23
Classification: G06F,H01L

Abstract:
A method comprising:generating a first data cell comprising first data, wherein the first data represents a first delay circuit having a first signal propagation delay between signal input and signal output of the first delay circuit, wherein the first delay circuit is configured to be contained within a first area on a silicon substrate, wherein the first area is larger than an area occupied by the first circuit; storing the first data cell in a memory; generating a second data cell comprising second data, wherein the second data represents a second delay circuit having a second signal propagation delay between signal input and signal output of the second delay circuit, wherein the second delay circuit is configured to be contained within a second area on silicon substrate, wherein the second area is larger than an area occupied by the second circuit; storing the second data cell in memory; wherein the first signal propagation delay is different than the second signal propagation delay; wherein the first area is equal in size to the second area; and wherein the first delay circuit comprises a first n-channel transistor coupled to a first p-channel transistor, wherein the second delay circuit comprises a second n-channel transistor coupled to a second p-channel transistor, and wherein the second delay circuit further comprises a capacitor coupled to the second n-channel and p-channel transistors.