Patent ID: 7977195
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A method for manufacturing at least one structure for a double grid field effect transistor, comprising: forming, on an isolating face of a first substrate, a stack comprising successively at least one layer of rear grid material, a layer of rear grid isolator, one semi-conducting zone for each structure to be manufactured, an electrically insulating layer of a front grid, at least one layer of front grid material and a masking element for each structure to be manufactured, placed facing the semi-conducting zone; forming in the at least one layer of front grid material a pattern reproducing a shape of the masking element and comprising etching of the layer of front grid material to eliminate the front grid material outside said pattern; forming on free faces of the pattern a sacrificial spacer covering a first part of the semi-conducting zone; eliminating an exposed part of the electrically insulating layer of the front grid, thus revealing a second part of the semi-conducting zone that defines areas for source and drain regions of the transistor; forming, after the eliminating the exposed part of the electrically insulating layer of the front grid, a protective layer over the second part of the semi-conducting zone; eliminating, after the forming the protective layer, the sacrificial spacer covering said first part of the semi-conducting zone; and etching, after eliminating the sacrificial spacer, the first part of the semi-conducting zone, which is no longer covered by the sacrificial spacer, to delineate a channel of the transistor.