Patent ID: 7401281
Filing Date: 2008-07-15
Classification: G01R,G11C

Abstract:
1. A hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions, the architecture comprising: a BIST logic controller that is separate from said embedded memory arrays, said BIST logic controller operates at a lower frequency than said embedded memory arrays and performs test functions common to all of said embedded memory arrays at said lower frequency; and a plurality of blocks of test logic in communication with said BIST logic controller, each one of said blocks is incorporated into a corresponding one of said embedded memory arrays under test, said each one of said blocks operates at a same frequency as said corresponding one of said embedded memory arrays, said same frequency comprising a higher frequency relative to said frequency of said BIST logic controller, said each one of said blocks performs test functions unique to said corresponding one of said embedded memory arrays at said same frequency, said BIST logic controller further communicates, to said each one of said blocks of test logic, instructions at said lower frequency, and said each one of said blocks further locally processes said instructions at said higher frequency.