Patent ID: 8216901
Filing Date: 2012-07-10
Classification: H01L

Abstract:
1. A fabrication method of a trenched MOS device comprising the steps of: providing a semiconductor base; forming a gate trench in the semiconductor base, the gate trench extending downward from an upper surface of the semiconductor base; forming a gate electrode in the gate trench; forming a dielectric structure above the gate electrode, the dielectric structure protruding the upper surface of the semiconductor base; forming a well in an upper portion of the semiconductor base; forming a source region in the well and adjacent to the gate electrode; depositing a first dielectric layer over the semiconductor base as a whole; forming a heavily doped region in the well by using the dielectric structure and the first dielectric layer lining a sidewall of the dielectric structure with a first dielectric thickness as an ion implantation mask, and the source region being substantially shielded by the first dielectric layer on the sidewall of the dielectric structure; removing at least a portion of the first dielectric layer to expose the source region and the heavily doped region, the source region having a width dimension determined by the first dielectric thickness; and forming a source metal layer connecting to the source region and the heavily doped region.