Patent ID: 8558343
Filing Date: 2013-10-15
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a semiconductor element in a semiconductor substrate; first wires formed over the semiconductor element and formed at a first wiring layer; second wires electrically connected to the first wires and formed at a second wiring layer which is one level upper than the first wiring layer; third wires electrically connected to the second wires and formed at a third wiring layer which is one level upper than the second wiring layer; fourth wires electrically connected to the third wires and formed at a fourth wiring layer which is one level upper than the third wiring layer; a power supply wire formed at a fifth wiring layer which is one level upper than the fourth wiring layer; and a fuse formed at the third wiring layer, wherein the fuse includes a copper film, the power supply wire overlaps the fuse in a planar view, a diffusion preventing film having the first, second, third and fourth wires does not overlap the fuse in a planar view and surrounds the fuse in a planar view, and in regions which overlap the fuse in a planar view, no wire is formed in the second and fourth wiring layers.