Patent ID: 6430684
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A method of operating a processor, comprising the steps of:fetching an instruction, the instruction comprising: an instruction opcode; a first data operand bit group corresponding to a first data operand; a second data operand bit group corresponding to a second data operand; and wherein at least one of the first data operand and the second data operand consists of an integer number N bits; and at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N; executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand; wherein the number of manipulated bits is in response to the at least one immediate bit manipulation operand; and wherein the manipulating step is further in response to the instruction opcode.