Patent ID: 6138211
Filing Date: 2000-10-24
Classification: G06F

Abstract:
An LRU memory capable of performing a pseudo replacement policy, comprising:an address decoding means for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD in response to a first phase of a CLOCK signal and to produce a WRITE.sub.-- WORD in response to a second phase of the CLOCK signal;an LRU storing means for storing a plurality of LRU data, producing an LRU data from a cell corresponding to the READ.sub.-- WORD as a READ.sub.-- DATA, and writing a WRITE.sub.-- DATA to a cell corresponding to the WRITE.sub.-- WORD;a way hit decoding means for decoding a WAY.sub.-- HIT so as to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal;a data modifying means for latching the READ.sub.-- DATA from the LRU storing means to produce a DETECTED DATA and modifying the READ.sub.-- DATA in response to the MODIFY CONTROL signal so as to producing the WRITE.sub.-- DATA to the LRU storing means; anda write way decoding means for analyzing the DETECTED DATA in accordance with the pseudo replacement policy, so as for producing a WRITE.sub.-- WAY.