Patent ID: 6808991
Filing Date: 2004-10-26
Classification: H01L

Abstract:
A fabrication method for a non-volatile memory device, said method comprising:providing a semiconductor substrate comprising a dielectric layer formed on thereon, an insulating composite layer formed on said dielectric layer; forming a patterned protective patterning layer and a patterned first sacrificial layer on said insulating composite layer; using at least said first patterned sacrificial layer as mask, introducing impurities into said substrate; trimming said protective patterning layer; patterning said first sacrificial layer by using said protective patterning layer as masks, wherein said first sacrificial layer comprises an opening that exposes said insulating composite layer; removing said protective patterning layer; filling a second sacrificial layer in said opening of said first sacrificial layer; patterning said first sacrificial layer and said insulating composite layer by using said second sacrificial layer as masks and exposing said dielectric layer; removing said second sacrificial layer; and forming a control gate on said composite layer.