Patent ID: 7230658
Filing Date: 2007-06-12
Classification: G02F

Abstract:
1. An array substrate comprising: a substrate; first and second gate lines extending in a first direction and a data line extending in a second direction on the substrate, the first and second gate lines crossing the data line to define first and second pixel regions adjacent along the first direction; first and second driving thin film transistors in the first and second pixel regions, respectively, and connected to the first gate line and the data line; a synchronization adjusting thin film transistor in the first pixel region and connected to the second gate line; a connection line connected to the first driving thin film transistor and the synchronization adjusting thin film transistor, the connection line disposed over the data line; and first and second pixel electrodes in the first and second pixel regions, respectively, the first pixel electrode connected to the synchronization adjusting thin film transistor, the second pixel electrode connected to the second driving thin film transistor.