Patent ID: 8665929
Filing Date: 2014-03-04
Classification: H04J,H04L

Abstract:
1. A method for assuring acquisition of symbol timing in a full-duplex data transceiver under inter-symbol interference conditions, comprising: determining a first frequency inaccuracy of a first local clock belonging to a transmitter, and a second frequency inaccuracy of a second local clock belonging to a receiver; assuring that a first free running frequency of the first local clock is lower than a second free running frequency of the second local clock, by setting a difference between the second free running frequency and the first free running frequency to a value higher than sum of the first inaccuracy and the second inaccuracy; using the first free running frequency to generate symbols at the transmitter; receiving the generated symbols at the receiver; decreasing, at the receiver, the frequency of the second local clock, to a third frequency value closer to the first free running frequency, using a first type decision-directed timing recovery mechanism that is limited to only decreasing and not increasing the frequency of the second local clock, wherein the limitation of the first type decision-directed timing recovery mechanism assures convergence into the third frequency value under substantial inter-symbol interference conditions; disabling the first type decision-directed timing recovery mechanism after reaching the third frequency value; and phase-locking the second local clock to substantially optimal phase under Minimum Mean Square Error (MMSE) criteria, using a second type decision-directed timing recovery mechanism, which is not limited to only decreasing the frequency of the second local clock.