Patent ID: 8693532
Filing Date: 2014-04-08
Classification: H04L

Abstract:
1. An apparatus comprising: an equalizer circuit configured and arranged to modify a frequency component of received signals based on an error signal; an absolute value circuit configured and arranged to assign a sign to each received signal by generating an output that is an absolute value of the received signal; a comparator circuit configured and arranged to, for each signal output from the absolute value circuit, process the signal to generate a signal having a voltage level limited to a predetermined value; a sign detection circuit configured and arranged to detect a sign of signals output by the equalizer circuit and to assign a sign to the output of the comparator circuit based upon the detected sign; and a summation circuit configured and arranged to sum the output of the equalizer with the output of the comparator circuit having the sign assigned thereto, and to provide the sum to the equalizer as the error signal.