Patent ID: 7930451
Filing Date: 2011-04-19
Classification: G06F

Abstract:
1. A buffer controller for managing a buffer memory having a free list, and comprising a plurality of buffer registers, said buffer controller comprising: a head pointer, pointing to a beginning of the free list; a tail pointer, pointing to the end of the free list; and a cache memory, storing addresses of a first plurality of unused buffer registers; wherein, when the buffer controller is asked to allocate a segment in form of a list, the first plurality of unused buffer registers is allocated to the segment before a second plurality of unused buffer registers is allocated to the segment; wherein each buffer register has one pointer, and a first buffer register in the list points to a last buffer register in the list, and the last buffer register in the list points to a second buffer register in the list; and wherein, when the buffer controller is asked to release the buffer registers in the list back to the buffer memory, the address corresponding to the first buffer register in the list is stored in the cache memory when the cache memory is not full, and the buffer controller directly links the rest of the buffer registers in the list to the end of said free list with the tail pointer pointing to the last buffer register in the list.