Patent ID: 6271682
Filing Date: 2001-08-07
Classification: G11C,H03K

Abstract:
An edge programmable timing signal generator, comprising:a memory subcircuit storing digital data coarsely defining desired rising and falling edges in a timing signal, said memory subcircuit adapted to output said digital data as a serial data stream at a serial output thereof;first and second programmable delay elements each having an input coupled to said serial data source and each adapted to introduce a delay into said serial data stream and to present said delayed serial data stream at an output thereof;a flip-flop circuit having a set input coupled to said output of said first programmable delay element to receive said delayed data stream presented thereon and having a reset input coupled to said output of said second programmable delay element to receive said delayed data stream presented thereon, and having an output for presenting a timing signal thereon;wherein said flip-flop circuit is responsive to assertion of said first delayed data stream to assert said timing signal and responsive to assertion of said second delayed data stream to deassert said timing signal.