Patent ID: 6940435
Filing Date: 2005-09-06
Classification: H03H,H03L,H03M

Abstract:
1. A method for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing, the method comprising the steps of: using for the timing clock of said digital signal processing a clock with a controllable frequency such that said digital signal processing can have a function suited for controlling the frequency of said timing clock, and converting the signal in synchronism with the timing clock of said digital signal processing when a delta-sigma converter or a switched-capacitor filter device is employed, wherein said timing and sample clocks are generated by dividing a fixed-frequency clock operating at a frequency substantially higher than that of said timing/sample clock by a digital divider of an integer division factor whose division factor is controlled by means of an at least second-degree delta-sigma modulator capable of delivering an output signal of two values so that one of the modulator output signal values selects the division factor to be N while the other value selects the division factor to be N+1, and the delta-sigma modulator controlling said integer-factor divider is adapted to be clocked by the timing signal generated by said integer-factor divider.