Patent ID: 7043626
Filing Date: 2006-05-09
Classification: G06F

Abstract:
1. A processor comprising: a first storage circuit comprising a free list, the free list including a set of physical register names and a corresponding set of indications each associated with one of the physical register names, wherein each indication is indicative, in a first state, that: (i) a physical register associated with a corresponding physical register name was assigned to store a register result and to store a flag result of a first instruction, and (ii) a subsequent instruction overwrites a logical register corresponding to a register result of the first instruction but not the flag result, and wherein each indication is indicative, in a second state, that at least one of (i) or (ii) is not detected, and wherein the first storage circuit is configured to output at least a first physical register name and a first indication corresponding to the first physical register name; a second storage circuit configured to store one or more physical register names separate from the free list, wherein the second storage circuit is configured to output a second physical register name; and a selection circuit coupled to receive the first physical register name from the first storage circuit and the second physical register name from the second storage circuit and further configured to receive the first indication, wherein the selection circuit selects the first physical register name as a selected physical register name responsive to the first indication being in the first state and selects the second physical register name as the selected physical register name responsive to the first indication being in the second state; wherein the selected physical register name is provided to a mapper circuit for assignment to a logical register.