Patent ID: 9026726
Filing Date: 2015-05-05
Classification: G06F

Abstract:
1. A data output circuit, comprising: a check data generation unit, configured to generate a first set of check data according to n1*b pieces of data in n*b pieces of data to be output, and generate a second set of check data according to the remaining n2*b pieces of data in the n*b pieces of data to be output, where n, n1, n2 and b are integer values corresponding to a number of pieces of data, n*b is a numerical multiplication of the n pieces of data and number of the b pieces of data, n1*b is a numerical multiplication of the n1 pieces of data and the b pieces of data, and, n2*b is a numerical multiplication of the n2 pieces of data and the b pieces of data; a first data processing unit, connected to an output end of the check data generation unit, and configured to: a first data output unit, connected to an output end of the first data processing unit, disposed with a first data bus and a first data bus inversion control line, and configured to output the n*b pieces of data, the first set of check data, the second set of check data, and the first inversion control data from the first data processing unit, wherein every time the n pieces of data are output through the first data bus, the first inversion control data corresponding to the n pieces of data is output through the first data bus inversion control line.