Patent ID: 8080989
Filing Date: 2011-12-20
Classification: G05F

Abstract:
1. A bandgap reference voltage generating circuit comprising: at least two bipolar transistors whose collectors are connected to a lower limit power supply voltage and are configured to generate a reference voltage by using a difference in emitter-base voltage; an operational amplifier configured to output a substantially constant voltage according to the reference voltage and an inverted reference voltage from the at least two bipolar transistors; a first PMOS transistor whose source is connected to an upper limit power supply voltage and is configured to supply a reference current to the at least two bipolar transistors; a second PMOS transistor whose source is connected to the upper limit power supply voltage and is configured to supply the reference current to the at least two bipolar transistors, the second PMOS transistor configured to turn on when the bandgap reference voltage generating circuit is in a sleep mode, such that the output of the operational amplifier is charged to a first set value and the first PMOS transistor is turned off; a third PMOS transistor whose source is connected to the upper limit power supply voltage; a fourth PMOS transistor whose source is connected to the upper limit power supply voltage and whose gate is connected to a drain of the third PMOS transistor, the fourth PMOS transistor configured to turn on when the bandgap reference voltage generating circuit is switched over from the sleep mode to an operation mode; a first NMOS transistor whose source is connected to the lower limit power supply voltage and whose drain is connected to a drain of the fourth PMOS transistor, the first NMOS transistor configured to be turned on when the fourth PMOS transistor is turned on, such that a drain voltage of the first NMOS transistor is charged to the first set value; and a second NMOS transistor whose drain is connected to the operational amplifier and whose gate is connected to the drain of the first NMOS transistor, the second NMOS transistor configured to be turned on when the drain voltage of the first NMOS transistor is charged, such that the output of the operational amplifier is discharged from the first set value to a second set value.