Patent ID: 8258009
Filing Date: 2012-09-04
Classification: H01L

Abstract:
1. A manufacturing method of a circuit substrate, the manufacturing method comprising: providing an inner circuit structure having an upper surface and a lower surface opposite to each other, a first conductive layer disposed on the upper surface and exposing a portion of the upper surface, a second conductive layer disposed on the lower surface and exposing a portion of the lower surface, wherein the inner circuit structure has a first dielectric layer disposed on the upper surface thereof and covering the first conductive layer, a second dielectric layer disposed on the lower surface thereof and covering the second conductive layer, a plurality of first conductive blind vias embedded in the first dielectric layer and connected to a portion of the first conductive layer, a plurality of second conductive blind vias embedded in the second dielectric layer and connected to a portion of the second conductive layer, and a fourth conductive layer disposed on the second dielectric layer, a first plating seed layer disposed between each of the first conductive blind vias and the first conductive layer, and a second plating seed layer disposed between each of the second conductive blind vias and the second conductive layer and on the second dielectric layer, a portion of the fourth conductive layer is electrically connected to the second conductive layer through the second conductive blind vias, and the fourth conductive layer and the second conductive blind vias are formed as an integrative unit; forming a third plating seed layer on the first dielectric layer and the plurality of the first conductive blind vias of the inner circuit structure thereby obtaining a semi-finished circuit substrate; cutting the semi-finished circuit substrate to form a plurality of circuit board units each having a circular shape, wherein each of the circuit board units comprise a plurality of circuit board sub-units each having a rectangular shape; fixing the plurality of the circuit board units respectively to a plurality of wafer carriers, so that the second dielectric layer of each of the circuit board units is in contact with the corresponding wafer carrier, wherein each of the circuit board units and the wafer carrier have substantially the same shape; forming a third conductive layer on the first dielectric layer of each of the circuit board units that are fixed on the wafer carriers, wherein the third conductive layer exposes a portion of the first dielectric layer, wherein a portion of the third conductive layer is electrically connected to the first conductive layer through the first conductive blind vias and the third plating seed layer therebelow, and the third plating seed layer is disposed between the third conductive layer and each of the first conductive blind vias; and removing the wafer carrier to expose a portion of the fourth conductive layer and a portion of the second dielectric layer.