Patent ID: 7849276
Filing Date: 2010-12-07
Classification: G06F

Abstract:
1. An integrated circuit active memory comprising: a memory interface coupled to receive externally generated commands and addresses through an external port, the memory interface further being operable to transmit data to and from the external port, the memory interface being operable to output memory control signals and processor control signals responsive to the externally generated commands, and to output processing element array addresses and memory device addresses responsive to the externally generated addresses; an array of processing elements coupled to the memory interface, each processing element in the array being operable to process varying widths of data, the processing elements in the array being selected by the processing element array addresses, the selected set of processing elements being further operable to receive data from the memory interface and to receive data from the memory interface responsive to the processor control signals, the selected set of processing elements further being operable to transmit the data to the memory interface responsive to the processor control signals; and a memory device coupled to the memory interface and to the array of processing elements, the memory device being operable responsive to the memory control signals to receive data from processing elements, and to store the data received from the processing elements at a location in the memory device selected by the memory device addresses, the memory device further being operable responsive to the memory control signals to receive data stored in the memory device at a location selected by the memory device addresses and to transmit the data stored in the memory device to the processing elements.