Patent ID: 9064702
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method for reducing defects in an active device area of a semiconductor device during fabrication, comprising: providing a substantially planar surface comprising an active device area adjacent an isolation structure; forming a stress-inducing layer over the substantially planar surface and patterning to remove a portion of the stress-inducing layer from the active device area while leaving the stress-inducing layer over the isolation region, the patterned stress-inducing layer being configured to induce a stress field in the active device area, the induced stress field resulting in a shear stress being applied on defects present in the active device area; forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, the screening layer being configured to screen part of the stress field induced by the patterned stress-inducing layer; performing an anneal process after forming the patterned stress-inducing layer over the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, wherein the stress field in the active device area has a sign and a magnitude that are conducive to movement of the defects in the active device area towards the contact interface during the anneal process; and removing the patterned stress-inducing layer from the substantially planar surface.