Patent ID: 6653861
Filing Date: 2003-11-25
Classification: H03K

Abstract:
A programmable interconnect circuit, comprising:a plurality of input/output (I/O) cells, wherein the I/O cells are arranged into a plurality N of I/O blocks, and wherein N is an integer and each I/O cell includes a multiplexer and a register associated with a pin of the programmable interconnect circuit; and a plurality of N routing structures corresponding to the plurality of N I/O blocks, each routing structure having a partially-populated first switch matrix for programmably routing input signals from each of the I/O cells into a first set of output signals, each routing structure also having a second switch matrix for programmably routing signals from the first set of output signals into a second set of output signals, the second set of output signals being coupled to I/O cells within the routing structure's I/O block.