Patent ID: 6563361
Filing Date: 2003-05-13
Classification: H03G

Abstract:
A voltage limiter circuit, comprising:a first current source; a first current sink; a first MOSFET of a differential amplifier having a gate terminal coupled to receive an amplified output from an operational amplifier, a source terminal coupled to the first current sink and a drain terminal coupled to the first current source; a first resistive load coupled to receive current from the first current source and also coupled to the drain terminal of the first MOSFET; a second current sink coupled to the drain terminal of the first MOSFET; a first current steering MOSFET whose source terminal is coupled to the drain terminal of the first MOSFET and to the first resistive load, the first current steering MOSFET being coupled to receive a first biasing signal at its gate terminal and whose source terminal is coupled to source current into the first resistive load; and a second current steering MOSFET whose source terminal is coupled to the drain terminal of the first MOSFET and to the first resistive load, the second current steering MOSFET being coupled to receive a second biasing signal at its gate terminal and whose source terminal further is coupled to sink current from the first resistive load.