Patent ID: 7525337
Filing Date: 2009-04-28
Classification: G11C,H03K,H04L

Abstract:
1. An on-die termination circuit for a semiconductor memory apparatus, comprising: a driving unit configured to receive a code having at least two bits, divide an input voltage on the basis of a resistance ratio of the driving unit according to the code, and output the divided voltage; and an on-die termination control unit configured to count the code based on whether or not line voltages according to the resistance ratio of the driving unit and a resistance of an external resistor unit correspond with a reference voltage, and to reset the code to a predetermined initial value when the counting of the code is stopped and a value of the code is a set value, wherein the on-die termination control unit includes: a first comparator configured to compare the line voltage with the reference voltage and output a comparison result signal, a second comparator configured to output a code count end signal according to the code and the comparison result signal, an internal clock generated configured to generate an internal clock according to an external clock and the code count end signal, a second reset signal generator configured to generate a second reset signal according to the code, the internal clock, and reset signal, and a code controller configured to count or reset the code according to the internal clock and the second reset signal.