Patent ID: 6855955
Filing Date: 2005-02-15
Classification: G02F

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate wire that transmits a gate signal formed on the substrate and including a gate line, and a gate electrode connected to the gate line; a storage wire formed on the substrate and separated from the gate line; a gate insulating layer formed on the substrate and covering the gate wire and the storage wire; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data wire formed on the gate insulating layer including a data line intersecting the gate line to define a pixel area, a source electrode connected to the data line and located on the semiconductor layer, and a drain electrode opposite the source electrode with respect to the gate line and located on the semiconductor layer; a conductor pattern formed on the gate insulating layer and overlapping the storage wire to form storage capacitance; a passivation layer covering the data wire and the semiconductor layer; and a pixel electrode formed substantially in the pixel area on the passivation layer and connected to the drain electrode or the conductor pattern, wherein the gate line or the conductor pattern includes a repairing extension overlapping the conductor pattern or the gate line.