Patent ID: 6504415
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A circuit comprising:clock-generation means for generating a reference set of matched clock signals, with each clock signal in the reference set being delayed a corresponding multiple of a nominal delay period relative to a given one of the clock signals; a first set of buffers having a set of clock inputs coupled to receive the reference set of matched clock signals and having a set of clock outputs for providing a set of first clock signals based on the reference set of matched clock signals; a second set of buffers having a set of clock outputs coupled to receive the reference set of matched clock signals and having a set of clock outputs for providing a set of second clock signals based on the reference set of matched clock signals; and a first subcircuit including: a first component having a clock input coupled to receive a first one of the first clock signals; and a second component having a clock input coupled to receive a first one of the second clock signals; and a second subcircuit substantially identical to the first subcircuit and including: a third component substantially identical to the first component and having a clock input coupled to receive a second one of the first clock signals; and a fourth component having a clock input coupled to receive a second one of the second clock signals.