Patent ID: 7317780
Filing Date: 2008-01-08
Classification: G09G,G11C

Abstract:
1. A shift registers circuit having a series of cascading shift registers, comprising: a first transistor having a gate, a first source/drain and a second source/drain, wherein the gate and the first source/drain of the first transistor is coupled to an output signal of a pre-stage shift register; a second transistor having a gate, a first source/drain and a second source/drain, wherein the gate of the second transistor is coupled to the second source/drain of the first transistor, the first source/drain of the second transistor is coupled to a first clock signal, and the second source/drain of the second transistor is coupled to an output, wherein the output is at a first voltage level when the second transistor is on and the first clock signal is at a high voltage level; and a pull-down module being coupled to the output, the output signal of the pre-stage shift register, an output signal of a post-stage shift register, a second and a third voltage level, wherein the output is at the second voltage level when an output signal of the post-stage shift register is at the second or the third voltage level, and the output is coupled to the third voltage level when an output signal of the post-stage shift register is at the first voltage level.