Patent ID: 8916478
Filing Date: 2014-12-23
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising: a first step of forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate so that the first fin-shaped silicon layer and the second fin-shaped silicon layer are connected to each other at the ends thereof to form a closed loop, forming a first insulating film around the first fin-shaped silicon layer and the second fin-shaped silicon layer, forming a first pillar-shaped silicon layer on the first fin-shaped silicon layer, and forming a second pillar-shaped silicon layer on the second fin-shaped silicon layer, a width of the first pillar-shaped silicon layer is equal to a width of the first fin-shaped silicon layer and a width of the second pillar-shaped silicon layer is equal to a width of the second fin-shaped silicon layer; a second step of, after the first step, forming n-type diffusion layers by implanting impurities in an upper portion of the first pillar-shaped silicon layer, an upper portion of the first fin-shaped silicon layer, and a lower portion of the first pillar-shaped silicon layer and forming p-type diffusion layers by implanting impurities in an upper portion of the second pillar-shaped silicon layer, an upper portion of the second fin-shaped silicon layer, and a lower portion of the second pillar-shaped silicon layer; a third step of, after the second step, forming a gate insulating film, a first polysilicon gate electrode, a second polysilicon gate electrode, and a polysilicon gate line so that the gate insulating film covers the peripheries and the tops of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, the first polysilicon gate electrode and the second polysilicon gate electrode cover the gate insulating film, and after the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line are formed, the top surface of polysilicon is higher than the gate insulating film on the n-type diffusion layer formed in the upper portion of the first pillar-shaped silicon layer and higher than the gate insulating film on the p-type diffusion layer formed in the upper portion of the second pillar-shaped silicon layer; a fourth step of, after the third step, forming a silicide in an upper portion of the n-type diffusion layer in the upper portion of the first fin-shaped silicon layer and in an upper portion of the p-type diffusion layer in the upper portion of the second fin-shaped silicon layer; a fifth step of, after the fourth step, depositing an interlayer insulating film, exposing the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line, etching the first polysilicon gate electrode, the second polysilicon gate electrode, and the polysilicon gate line, and then depositing a metal to form a first metal gate electrode, a second metal gate electrode, and a metal gate line, the metal gate line connected to the first metal gate electrode and the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer; and a sixth step of, after the fifth step, forming a first contact and a second contact so that the first contact is direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and the second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer.