Patent ID: 6529557
Filing Date: 2003-03-04
Classification: H03M

Abstract:
A high-speed add-compare selection apparatus, for use in a Viterbi algorithm processing apparatus having a branch metric calculator and a metric memory, comprising:first and second registers; means for supplying to the first and second registers first and second previous metric values, respectively, from the metric memory; a first adder for adding the first previous metric value from the first register and a branch metric value of a first present state calculated by the branch metric calculator, and adding the first previous metric value from the first register and a branch metric value of a second present state calculated by the branch metric calculator; a second adder for adding the second previous metric value from the second register and a branch metric value of a first next state calculated by the branch metric calculator, and adding the second previous metric value from the second register and a branch metric value of a second next state calculated by the branch metric calculator; and a comparator for comparing the outputs of the first and second adders and calculating a first survival metric value and a second survival metric value accordingly.