Patent ID: 6031886
Filing Date: 2000-02-29
Classification: H04L

Abstract:
A digital phase alignment apparatus in consideration of metastability, comprising:a multi-phase clock generating means for delaying source clock to generate first to n.sup.th multi-phase clocks;first multi-phase comparating and clock phase selecting means for detecting a clock whose transition is occurred in close vicinity of a center of external input data, among first to k+1.sup.th multi-phase clocks, to generate the k number of clock selecting signals, and generating a masking output signal when activated clock selecting signal is occured among k number of clock selection signals;second multi-phase comparating and clock phase selecting means for detecting a clock whose transition is occured in close vicinity of a center of external input data, among k+1.sup.th to 2k+1.sup.th multi-phase clocks, to generate the k number of clock selection signals, generating a masking output signal when activated clock selecting signal is occured among the k number of clock selecting signals, and masking activated clock selecting signal when the masking output signal of said first multi-phase comparating and clock phase selecting means is inputted;m.sup.th multi-phase comparating and clock phase selecting means for detecting a clock whose transition is occured in close vicinity of a center of external data, among n-k.sup.th to n.sup.th multi-phase clocks, to generate k number of clock selecting signals, generating a masking output signal when activated clock is occured among the k number of clock selection signals, and masking activated clock selecting signal when a masking input signal is inputted;a OR gate for ORing masking output signals of said multi-phase comparating and clock phase selecting means to generating a masking input signal, and supplying the masking input signal to said m.sup.th multi-phase comparating and clock phase selecting means;a synthetic clock generating means for synthesizing the n-1 number of clock selection signals; anda retiming buffer means for retiming external input data according to the synthesized clock of said synthetic clock generating means.