Patent ID: 6093614
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of forming a plurality of memory cells for DRAMS in a silicon wafer, each memory cell including a transistor in series with a capacitor, the method comprising the steps of:preparing a wafer that has at least a top surface portion that is monocrystalline silicon of one conductivity type;forming in the wafer vertical trenches in the top surface portion;forming a first dielectric layer over the walls of each of said vertical trenches for use as the dielectric of the capacitor of the cell;filling each of the vertical trenches with polysilicon of a conductivity type opposite the one conductivity type;forming a first recess in each of said vertical trenches;forming a dielectric layer over the side walls of said recesses;filling each of the first recesses with polysilicon of the opposite conductivity type;forming a second recess shallower than the first recess in each of the vertical trenches;cleaning the walls of each of said second recesses of dielectric for exposing monocrystalline silicon;refilling each of the second recesses with monocrystalline silicon that is of the one conductivity type for serving as the body of the transistor of the cell and that is epitaxially grown from the exposed monocrystalline silicon;forming in the wafer shallow trenches for surrounding pairs of vertical trenches to a depth below that of the second recesses and for exposing a portion of the epitaxially grown silicon of each of the vertical trenches;filling the shallow trenches with silicon oxide;etching new recesses in the silicon oxide-filled shallow trenches for reexposing portions of the epitaxially grown silicon;forming a layer for serving as the transistor gate dielectric over the exposed portions of the epitaxially grown silicon;filling the recesses in the silicon oxide-filled trenches for covering the gate dielectric with conductive material for use as the gate conductor; andforming a separate conductive region of the opposite conductivity type as the transistor drain in the monocrystalline portion of the wafer that lies between each pair of vertical trenches in which a cell hag been formed.