Patent ID: 8594264
Filing Date: 2013-11-26
Classification: H03L

Abstract:
1. A method, comprising: receiving an incoming clock signal and a plurality of phased clock signals, each of the phased clock signals having a different phase and a substantially same phase offset from one other of the phased clock signals; calibrating the signal paths of the incoming clock signal and the phased clock signals by adjusting independently-programmable delays in the signal paths of the incoming clock signal for each of the phased clock signals such that the incoming clock signal arrives at a respective one of a plurality of detection flip-flops at substantially the same time as a corresponding one of the phased clock signals; providing at least one detection signal based on the incoming clock signal and the phased clock signals; correcting one or more errors in the at least one detection signal contributed by noise in at least the incoming clock signal; and based on the at least one detection signal, selecting one of the phased clock signals as the most closely aligned of the phased clock signals to the predetermined clock phase, wherein the selected phased clock signal is output as the aligned output clock signal.