Patent ID: 6329281
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A method of fabricating a multilevel conductive interconnection for an integrated circuit device, comprising:providing a semiconductor substrate including a semiconductor device and having a dielectric layer formed thereon;forming a selective overlayer over the dielectric layer;forming a first patterned photoresist layer over the selective overlayer to define a first opening;etching the selective overlayer and the dielectric layer to a first predetermined depth using the first patterned photoresist layer as a mask to transfer the first opening through the selective overlayer and at least partially into the dielectric layer;removing the first patterned photoresist layer;forming a second patterned photoresist layer over the selective overlayer to define a second opening;etching the dielectric layer to a second predetermined depth, which is greater than the first predetermined depth, using the selective overlayer as a mask to transfer the first opening further into the dielectric layer;etching the selective overlayer using the second patterned photoresist layer as a mask to transfer the second opening substantially through the selective overlayer; andetching the dielectric layer using the selective overlayer as a mask to transfer the first opening through the dielectric layer exposing the semiconductor substrate, and the second opening into the dielectric layer to a third predetermined depth which is less than the second predetermined depth.