Patent ID: 7782103
Filing Date: 2010-08-24
Classification: H03L,H04L

Abstract:
1. A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit comprising: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a first delay control section for outputting a first delay control signal based on the comparison result from the phase comparator, the first delay control signal being a digital signal; and a second delay control section for outputting a second delay control signal based on a frequency of the clock signal, the second delay control signal being a digital signal, wherein the delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the first and second delay control signals, wherein the delay line includes: wherein each of the delay units includes a delay adjustment section for adjusting an amount of signal delay based on the other one of the first and second delay control signals, and wherein the delay adjustment section includes a plurality of loads connected together in parallel, and selectively connects or disconnects each of the loads based on the other one of the first and second delay control signals.