Patent ID: 6967870
Filing Date: 2005-11-22
Classification: G11C

Abstract:
1. An integrated circuit memory device capable of operating either in a NAND mode or in a NOR mode of operation, said device comprising: an array of floating gate memory cells arranged in a NOR configuration, and electrically coupled to a respective plurality of word lines and a plurality of bit lines; a plurality of sub-page buffers electrically coupled to said plurality of bit lines for storing data externally supplied to said device to be programmed into said memory cells coupled to said plurality of bit lines; a programming control circuit coupled to said plurality of sub-page buffers for initiating a programming operation to program data sequentially from one sub-page buffer into an associated sub-page of memory cells until data from said plurality of sub-page buffers are programmed into said plurality of sub-page memory cells; a first bus for supplying data and address to said device for programming in said NAND mode; a second bus for supplying a read address to said device for reading in said NOR mode; and a read control circuit including sense amplifier for reading data stored in said array at said read address and for outputting said data from said device.