Patent ID: 8860460
Filing Date: 2014-10-14
Classification: H03K

Abstract:
1. An integrated circuit, comprising: a logic region having a plurality of rows of circuitry including a spare row of circuitry; a plurality of routing segments each of which has a first end coupled to a respective one of the rows of circuitry and an opposing second end coupled to an adjacent one of the rows of circuitry; and a plurality of bypass circuits each of which is coupled between a respective pair of the routing segments, wherein the bypass circuits are operable to switch the spare row into use when one of the rows of circuitry contains a defective circuit, wherein each routing segment is operable to be driven by an associated routing segment using a respective one of the bypass circuits, wherein the plurality of bypass circuits comprises a plurality of multiplexers, and wherein each multiplexer in the plurality of multiplexers includes a first input operable to receive user signals, a second input that is coupled to one associated routing segment, and an output that is coupled to another associated routing segment.