Patent ID: 7466604
Filing Date: 2008-12-16
Classification: G11C

Abstract:
1. A static random access memory (“SRAM”), comprising: a plurality of SRAM cells arranged in an array, the array including a plurality of portions; and a plurality of voltage control circuits corresponding to respective ones of the plurality of portions, each of the plurality of voltage control circuits coupled to an output of a power supply, each voltage control circuit being operable to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells belonging to a selected portion of the array, the selected portion being selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected portion, wherein each voltage control circuit includes an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”), each of the NFET and the PFET having a conduction path connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.