Patent ID: 8018755
Filing Date: 2011-09-13
Classification: G11C

Abstract:
1. A memory device comprising: a power supply line; a first signal line; a second signal line; an output terminal; a reading circuit including a transistor and a clocked inverter; and a memory cell including a memory element, the memory cell being electrically connected to the second signal line and the reading circuit, wherein an input terminal of the clocked inverter is electrically connected to the second signal line, wherein an output terminal of the clocked inverter is electrically connected to the output terminal, wherein the transistor comprises: a first terminal electrically connected to the power supply line and serving as one of a source terminal and a drain terminal; a second terminal electrically connected to the memory cell through the second signal line and serving as the other of the source terminal and the drain terminal; a third terminal electrically connected to the first signal line and serving as a gate terminal; and a fourth terminal, wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and wherein an output terminal of the inverter is electrically connected to the third terminal of the transistor.