Patent ID: 6704020
Filing Date: 2004-03-09
Classification: G11C,H04N

Abstract:
An architecture for video decompressor to efficiently access synchronous memory, comprising:a synchronous memory device having an A-bank and B-bank for being stored with image data; and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display, wherein the image data has a plurality of luminance scan lines and every eight scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (8N+0)-th, (8N+1)-th, (8N+6)-th and (8N+7)-th scan lines, and the B-bank is sequentially stored with the (8N+2)-th, (8N+3)-th, (8N+4)-th and (8N+5)-th scan lines, where N is a non-negative integer, and wherein the image data has a plurality of chrominance scan lines and every eight scan lines are grouped for being periodically arranged in such a manner that the A-bank is sequentially stored with (8N+1)-th, (8N+2)-th, (8N+5)-th and (8N+6)-th scan lines, and the B-bank is sequentially stored with (8N+0)-th, (8N+3)-th, (8N+4)-th and (8N+7)-th scan lines, where N is a non-negative integer.