Patent ID: 6542996
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A method of implementing a suspend-to-RAM (STR) mode of operation in a computer system having a central processing unit (CPU), a first control chip coupled to the CPU, a second control chip and a system memory, wherein the system memory is coupled to the first control chip and has a self-refresh mode, the method comprising:deciding whether the computer system needs to switch into the STR mode or a normal mode of operation, such that if the computer system needs to switch into the STR mode of operation, then transferring data from a register within the first control chip to a memory unit coupled to the second control chip; pulling down the voltage level at a clock-enable pin of the system memory; and cutting off power to the first control chip completely under the direction of the second control chip on receiving a signal from a basic input/output system (BIOS) so that the system starts operating in the STR mode, whereas if the computer system needs to switch back from the STR mode to the normal mode of operation, the following steps are executed, including: resuming the supply of power to the first control chip under the direction of the second control chip on receiving a signal from the BIOS; storing the data in the memory unit to the register of the first control chip; and pulling up the voltage level at the clock-enable pin of the system memory, so as to allow the computer system to return to the normal mode.