Patent ID: 6625798
Filing Date: 2003-09-23
Classification: G06F

Abstract:
A method of translating multiple-bit conditional expressions, of a non-Verilog hardware description language (HDL) program used to specify a logic design to Verilog HDL, comprising:a) for a conditional expression of the non-Verilog HDL program, having a format of IF ifcond THEN expr1 ELSE expr2, determining a bit width of the conditional expression; b) if the conditional expression is a multiple-bit expression, the method further comprising: 1) creating a binary operator statement, having a plurality of bit-wise binary operators, that is equivalent to the conditional expression; 2) determining whether at least one of the expr1 expression or the expr2 expression are multiple-bit expressions nested within the binary operator statement; 3) if at least one of the expr1 expression or the expr2 expression are multiple-bit expressions nested within the binary operator statement, processing the at least one of the expr1 expression or the expr2 expression to create an always statement, equivalent to the binary operator statement and having the plurality of bit-wise binary operators, containing one or more incremental variables representative of the at least one of the expr1 expression or the expr2 expression that are multiple-bit expressions and translating the always statement to generate a Verilog HDL statement equivalent to the conditional expression; and 4) if the at least one of the expr1 expression or the expr2 expression are not multiple-bit expressions, translating the binary operator statement to generate a Verilog HDL statement equivalent to the conditional expression; c) repeating a)-b) for each conditional expression of a plurality of conditional expressions of the non-Verilog HDL program to generate a plurality of Verilog HDL statements equivalent to the plurality of conditional expressions; and d) performing synthesis on the plurality of Verilog HDL statements to generate a logic circuit representative of the non-Verilog HDL program.