Patent ID: 7296216
Filing Date: 2007-11-13
Classification: H03M

Abstract:
1. An apparatus, comprising: a Sum-Product (SP) soft decision decoder that performs a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within a Low Density Parity Check (LDPC) coded signal that is received from a communication channel, wherein the SP soft decision decoder is initialized based on the LDPC signal that is received from the communication channel and channel information corresponding to the communication channel over which the LDPC coded signal has been communicated; wherein the SP soft decision decoder generates a first plurality of hard decisions using the plurality of soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations; and a Bit-Flip (BF) hard decision decoder that performs a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder to generate a second plurality of hard decisions.