Patent ID: 7453305
Filing Date: 2008-11-18
Classification: H03F

Abstract:
1. A voltage level shifting circuit for level shifting a differential signal with a common mode voltage of the level shifted differential signal referenced to a voltage reference and for applying the level shifted differential signal to a differential input buffer circuit with propagation delays minimised, the differential input buffer circuit comprising first and second differential inputs for receiving the level shifted differential signal from the voltage level shifting circuit, the first and second differential inputs of the differential input buffer circuit having respective first and second intrinsic input capacitance, the voltage level shifting circuit comprising: a first input terminal for receiving a first signal of a differential signal pair of the differential signal; a second input terminal for receiving a second signal of the differential signal pair of the differential signal; a first resistive voltage divider circuit coupled between the first input terminal and a voltage reference terminal for receiving the voltage reference; a second resistive voltage divider circuit coupled between the second input terminal and the voltage reference terminal; first and second output taps formed, respectively, by the respective first and second resistive voltage divider circuits, on which taps are produced respective first and second level shifted signals of a level shifted differential signal pair of the level shifted differential signal with the common mode voltage thereof referenced to the voltage reference for applying to the first and second differential inputs, respectively, of the differential input buffer circuit; a first high-frequency-low-impedance circuit forming a direct-current-blocked, high-frequency-low-impedance pathway forming at least part of a path between the first input terminal and the first output tap for accommodating the first signal of the differential signal pair from the first input terminal to the first output tap with propagation delays minimised when the first level shifted signal of the level shifted differential signal pair is applied to the first differential input of the differential input buffer circuit, the first high-frequency-low-impedance circuit and the first resistive voltage divider circuit co-operating with the first intrinsic input capacitance of the first differential input of the differential input buffer circuit to form a first low pass filter; a second high-frequency-low-impedance circuit forming a direct-current-blocked, high-frequency-low-impedance pathway forming at least part of a path between the second input terminal and the second output tap for accommodating the second signal of the differential signal pair from the second input terminal to the second output tap for minimising propagation delays when the second level shifted signal of the level shifted differential signal pair is applied to the second differential input of the differential input buffer circuit, the second high-frequency-low-impedance circuit and the second resistive voltage divider circuit co-operating with the second intrinsic input capacitance of the second differential input of the differential input buffer circuit to form a second low pass filter; and the first and second low pass filters acting to filter out noise in the differential signal at frequencies above the cut-off frequencies of the first and second low pass filters.