Patent ID: 8686884
Filing Date: 2014-04-01
Classification: H03M

Abstract:
1. A serial interface comprising: a comparator to receive an input signal and a local offset signal; a first digital to analog converter (DAC) to selectably provide one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation; a second DAC to selectably provide one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation; and a test module to test the second DAC, the test module to cause the first DAC to determine a first test signal to provide to the global offset input of the comparator, to cause the second DAC to incrementally change a test signal provided to the comparator, and to evaluate the output of the comparator in response to the changes in the test signal to determine whether a function of the second DAC operates properly.