Patent ID: 6412101
Filing Date: 2002-06-25
Classification: G06F

Abstract:
A method for determining where to insert repeaters when designing an integrated circuit in order to reduce signal propagation delays in the integrated circuit, comprising the step of:(a) obtaining a description of an electrical network, said description indicating a source node, a plurality of sink nodes, a plurality of electrical branches connecting said source node with each said sink node, a plurality of resistances associated respectively with said branches, a plurality of capacitances associated respectively with said branches, and a plurality of timing constraints associated respectively with said branches, each said timing constraint representing a maximum propagation time delay between said source and a respective one of said sinks; (b) determining a slack parameter for each branch of said network, said slack parameter being computed for each branch by mathematically subtracting a signal propagation delay associated said each branch from a timing constraint associated with said each branch; (c) determining a main branch in said network as one of said branches that exhibits the largest one of said slack parameters; (d) producing a total slack parameter by mathematically combining said slack parameters; (e) determining how many of said repeaters, if any, should be inserted in at least one side branch extending from said main branch by simulating at least one repeater in at least one side branch and determining whether said total slack parameter decreases by insertion of said at least one repeater; (f) determining how many of said other repeaters, if any, should be inserted along said main branch using a first delay simulator and simulating at least one other repeater; and (g) determining a position for each of said other repeaters using a second delay simulator and simulating said other repeaters.