Patent ID: 6200846
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising the steps of:forming element isolation structures on a surface of a semiconductor substrate to define active regions for MISFETs;forming a gate insulating film on surfaces of the active regions;depositing a first conductive film on the element isolation structures and the gate insulating film;forming a capacitor dielectric film on the first conductive film;depositing a second conductive film on the capacitor dielectric film;patterning the second conductive film to leave an upper electrode made of the second conductive film above a partial area of the element isolation structure;depositing a first insulating film covering the upper electrode and the capacitor dielectric film;anisotropically etching the first insulating film to leave a first spacer insulating film on side walls of the upper electrode;removing the capacitor dielectric film in an area not covered with the upper electrode and the first spacer insulating film to expose the first conductive film;forming a first mask pattern on a surface of the first conductive film, the first mask pattern covering an area inclusive of an area where the upper electrode and the first spacer insulating film were formed and areas in the active regions where gate electrodes of the MISFETs are to be formed; andetching the first conductive film by using the first mask pattern as a mask, to leave a lower electrode made of the first conductive film under the upper electrode and to leave gate electrodes made of the first conductive film on the active regions.