Patent ID: 7132368
Filing Date: 2006-11-07
Classification: H01L

Abstract:
1. A method for processing integrated circuit devices, the method comprising: supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures, each of the gate structures having vertical regions defining sides of the gate structures, each of the gate structures being formed on a surface of a substrate region; forming a conformal dielectric layer overlying the MOS gate structures, the conformal dielectric layer having a predetermined thickness of material that covers each of the MOS gate structures including vertical regions; forming sidewall spacers on the sides of the gate structures from the conformal dielectric layer using an anisotropic etching process; exposing a portion of the substrate region during the formation of the sidewall spacers using the anisotropic etching process to cause physical damage to a portion of the exposed portion of the substrate; and applying a plasma treatment process including an isotropic etching component to the exposed portion of the substrate and sidewall spacers on the sides of the gate structures, the plasma treatment process comprising at least an etchant species of CF