Patent ID: 6661248
Filing Date: 2003-12-09
Classification: G01R

Abstract:
A tester for semiconductor integrated circuits comprising a testing circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested that comprises an A/D converter circuit to convert analog signals to digital signals, and a D/A converter circuit to convert digital signals to analog signals; a test assisting device disposed in the vicinity of and connected to said testing circuit board; and a test machine connected to said test assisting device; said test assisting device having a data circuit to generate digital test signals and to supply the test signals to said D/A converter circuit of said semiconductor integrated circuit to be tested; a testing D/A converter circuit to convert digital test signals from said data circuit to analog test signals and to supply the test signals to said A/D converter circuit of said semiconductor integrated circuit to be tested; a testing A/D converter circuit to convert analog test outputs of said D/A converter circuit of said semiconductor integrated circuit to be tested to digital test outputs; a measured data memory to store the digital test outputs from said A/D converter circuit of said semiconductor integrated circuit to be tested and the digital test outputs of said testing A/D converter circuit; and an analyzer portion to analyze each of said digital test outputs stored in said measured data memory; these data circuit, testing D/A converter circuit, testing A/D converter circuit, measured data memory, and analyzer portion being constituted so as to be separately provided on a plurality of circuit boards; and said tester for semiconductor integrated circuits being constituted so as to supply the test signals containing said digital test signals and said analog test signals to said semiconductor integrated circuit to be tested based on instructions from said test machine, and to supply the results of analysis of each digital test output stored in said measured data memory by said analyzer portion to said test machine.