Patent ID: 7332773
Filing Date: 2008-02-19
Classification: G11C,H01L

Abstract:
1. A method of forming a NAND architecture memory cell string, comprising: forming one or more raised areas on a substrate, the raised areas defining associated intervening trenches; forming a plurality of floating gate memory cells on the sidewalls of the one or more raised areas; forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the one or more associated intervening trenches, wherein the one or more source/drain regions formed at the bottom of the one or more associated intervening trenches have first and second edges that extend beyond opposite sidewalls of their respective trenches; and forming a first vertical select gate coupled to a first floating gate memory cell of the NAND architecture memory string and a second vertical select gate coupled to a last floating gate memory cell of the NAND architecture memory string.