Patent ID: 6954425
Filing Date: 2005-10-11
Classification: G06F,H04J

Abstract:
1. A method for compensating for clock signal difference between a switch and a peripheral device, the switch comprising a memory, a first counter and a second counter, the switch being used for receiving and transmitting a plurality of packets, the memory receiving the packets for temporary storage and being read for transmission of the packets, wherein each of the packets corresponds to a queue link node, an N-th packet corresponds to an N-th queue link node QLN(N) and an M-th packet corresponds to an M-th queue link node QLN(M), where N and M are integers, the method comprising: a receiving process, the receiving process comprising the steps of: a transmitting process, the transmitting process comprising the steps of: wherein when the M-th and (M+1)-th packets are transmitted respectfully, an inter-packet gap between the transmitted M-th and (M+1)-th packets is based on the inter-packet gap IPG(M−1, M), which is the inter-packet gap between the received (M−1)-th and M-th packets and is recorded into the M-th QLN(M) by the receiving process, so that congestion of the memory of the switch is reduced.