Patent ID: 7268418
Filing Date: 2007-09-11
Classification: H01L

Abstract:
1. A multi-chips stacked package, comprising: a substrate having an upper surface; a lower chip having a first active surface and a first back surface, wherein the lower chip is disposed above the upper surface of the substrate and electrically connected to the substrate via a plurality of first electrically conductive wires; an interposer disposed on the first active surface of the lower chip; an upper chip having a second active surface and a second back surface, wherein the upper chip is disposed above the interposer and electrically connected to the substrate via a plurality of second electrically conductive wires; and a supporting body disposed on the upper surface of the substrate and covered by the upper chip, wherein the top of the supporting body is higher than the top of the arc of each of the first electrically conductive wires and lower than the second back surface of the upper chip, and the second back surface of the upper chip is attached to the interposer, and wherein an encapsulation is disposed between one of the top of the supporting body and the second back surface of the upper chip.