Patent ID: 7164297
Filing Date: 2007-01-16
Classification: H03K

Abstract:
1. A clock synthesizer that divides a source clock by a fractional divide ratio N.R which is at least one, comprising: a logic circuit which determines an integer M such that the fractional divide ratio N.R divided by 2 a delay line having an input receiving a first clock and having a plurality of delay taps, wherein said first clock has a frequency which is the frequency of the source clock divided by a first value; a select circuit having a plurality of selectable inputs coupled to said plurality of delay taps, a select input receiving a tap select value, and an output providing a delay clock; an accumulator which adds said RNEW value to a sum value for each cycle of said delay clock and that performs a modulo function on said sum value to generate said tap select value; and a first clock divider circuit that transitions an output clock based on selected transitions of said delay clock wherein said transitions are selected to divide the frequency of the delay clock by a second value in which said first value multiplied by said second value is 2