Patent ID: 9184214
Filing Date: 2015-11-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a gate stack disposed above a device channel on the substrate, the gate stack comprising a metal gate conductor on a gate dielectric disposed on said device channel, wherein the thickness of the gate stack is in the range of 3-73 nm; a gate spacer extending from the surface of said substrate about the sides of the gate stack, the thickness of said gate spacer being as thick as said gate stack; a stress liner comprising a nitride layer on said substrate and overlaying the metal gate conductor and extending from said substrate between the gate spacers; a dielectric layer atop the stress liner; a gate contact above said device channel through said dielectric layer and said stress liner and in direct contact with the metal gate conductor, said gate contact being narrower than the length of the metal gate conductor and at least 3 times as tall as said gate stack; a source and drain region adjacent said gate spacer at each end of said gate stack; a silicide region on each of the source and drain regions, said stress liner separating each said silicide region at said substrate from a respective said gate spacer; and a source/drain contact through said dielectric layer and said stress liner and on an upper surface of each respective said silicide region, the source/drain contacts being at least 3 times as tall as said gate stack.