Patent ID: 9122465
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a processing core including an issue unit and at least one execution unit, wherein the issue unit is configured to issue instructions from first and second instruction streams to the at least one execution unit for concurrent execution of the first and second instruction streams by the at least one execution unit, the first and second instruction streams respectively including a first and second instances of a microcode instruction, the second instruction stream associated with a different process, application, or thread from the first instruction stream; and a programmable microcode unit coupled to the issue unit, the programmable microcode unit configured to, in response to software executing on the processing core, map a first instruction sequence to the microcode instruction by storing the first instruction sequence in a first partition among a plurality of partitions defined in one or more rewriteable memories, and map a second instruction sequence to the microcode instruction by storing the second instruction sequence in a second partition among the plurality of partitions defined in the one or more rewriteable memories, wherein the programmable microcode unit is further configured to, in response detection of the first instance of the microcode instruction in the first instruction stream during the concurrent execution of the first and second instruction streams, issue the first instruction sequence to the at least one execution unit, and in response to detection of the second instance of the microcode instruction in the second instruction stream during the concurrent execution of the first and second instruction streams, issue the second instruction sequence to the at least one execution unit.