Patent ID: 6891219
Filing Date: 2005-05-10
Classification: H01L

Abstract:
1. A vertical metal-insulator-metal (VMIM) capacitor in an integrated circuit (IC) that has a horizontal substrate, a lower metal interconnect layer and an upper damascene-metallization interconnect layer, the lower metal interconnect layer and the substrate being separated by a dielectric layer, the lower metal interconnect layer and the upper damascene-metallization interconnect layer being separated by an interlayer dielectric (ILD) layer, the upper damascene-metallization interconnect layer being at least partially formed by damascene-metallization steps, comprising: a first damascene-metallization vertical capacitor plate disposed at least partially within the upper damascene-metallization interconnect layer, the first vertical capacitor plate at least partially formed by the damascene-metallization steps used to form the upper damascene-metallization interconnect layer; a second damascene-metallization vertical capacitor plate laterally spaced from the first vertical capacitor plate and disposed at least partially within the upper damascene-metallization interconnect layer; and a capacitor dielectric interposed between the first vertical capacitor plate and the second vertical capacitor plate.