Patent ID: 6925544
Filing Date: 2005-08-02
Classification: G06F,H04L

Abstract:
1. A memory circuit for buffering data, the memory circuit having an address input bus with an address space for receiving address data, a data input bus for receiving data, and a data output bus for outputting data; comprising a buffer memory having a memory address space and memory address data, an address port for receiving the memory address data to address the buffer memory, a data input port to receive the data over the data input bus for storing in the buffer memory, and a data output port for outputting the data stored in the buffer memory over the data output bus; an address translator to receive the address data for translation into the memory address data and providing the memory address data to the address port of the buffer memory; and a memory allocation circuit having an allocation/de-allocation signal line for receiving allocation and de-allocation requests, a byte count bus for receiving a byte count with each of the allocation and de-allocation requests, an addressing bus for providing a first start address in response to an allocation request and receiving a second start address with a de-allocation request, and a control bus to load data to the address translator for translating the address data to the memory address data; wherein the address space is divided into address blocks, the memory address space is divided into memory blocks, and each address block comprises a fixed number of memory blocks; wherein the memory allocation circuit, in response, to the allocation request, allocates sufficient consecutive addresses in the address space in the address blocks and sufficient number of the memory blocks of the buffer memory to store the byte count amount of memory, provides the first start address over the address bus, and loads the data to the address translator for translating the address data to the memory address data; wherein the memory allocation circuit, in response, to the de-allocation request, de-allocates the address blocks starting at the first whole address block from the second start address for the whole address blocks of the byte count amount of memory and de-allocates the memory blocks corresponding to the de-allocated address blocks; and wherein the address translator comprises an indirection memory to store the data for translating the address data to the memory address data where the data in the indirection memory comprises the memory address data stored at indirection memory addresses corresponding to the address data.