Patent ID: 6580137
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A Damascene double gated, recessed channel transistor comprisingan extrinsic region around an intrinsic region, wherein the intrinsic region includes a plurality of layers in a trench in a semiconductor substrate, wherein the trench includes a merged gate trench and isolation trench, wherein the extrinsic region includes a source pedestal and a drain pedestal, wherein the gate trench is between the source pedestal and the drain pedestal, wherein the isolation trench is dielectrically filled and surrounds the source pedestal and the drain pedestal, wherein the plurality of layers are self-aligned to the trench, wherein the layers provide a double gated MOSFET, wherein the double gated MOSFET includes a top gate, a gate dielectric, a channel and a bottom gate, and wherein the top gate is over the gate dielectric, the gate dielectric is over the channel and the channel is over the bottom gate.