Patent ID: 8431998
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. An insulated gate semiconductor device comprising: a semiconductor substrate; a device region which is a region of the semiconductor substrate in which a plurality of cells of insulated gate transistors are formed, each of the transistors includes a source region; a first top terminal electrode layer disposed on the semiconductor substrate so as to cover a first portion of the device region, the first top terminal electrode layer being electrically connected to the device region but not being in direct physical contact with the first portion, the first portion having the cells formed therein; a second top terminal electrode layer disposed on the semiconductor substrate so as to cover a second portion of the device region, the second top terminal electrode layer being electrically connected to the device region but not being in direct physical contact with the second portion, the second portion having the cells formed therein, the second top terminal layer comprising a pad portion to which an electrical connection is made to receive a control signal for the transistors in the device region; and a protection diode formed in the semiconductor substrate so as to be outside the device region but adjacent the device region, wherein in plan view of the semiconductor substrate the pad portion and the protection diode do not overlap, the protection diode is disposed in a peripheral region of the semiconductor substrate and extends along at least one side of the semiconductor substrate, the cells are disposed below the pad portion so that the cells and the pad portion overlap in plan view of the semiconductor substrate, and the source regions of the transistors are disposed below the pad portion so that the source regions and the pad portion overlap in plan view of the semiconductor substrate.