Patent ID: 6660585
Filing Date: 2003-12-09
Classification: G11C,H01L

Abstract:
A method of producing a stacked gate flash memory cell to reduce disturb conditions, comprising:a) growing a gate oxide on top of a semiconductor substrate, b) forming a floating gate on top of said gate oxide, c) forming an upper oxide layer on top of said floating gate, d) forming a control gate on top of said floating gate with said upper oxide layer in between to produce a stacked gate, e) forming an LDD (lightly doped drain) in said substrate only on drain side of said stacked gate using said stacked gate as a mask, f) forming a source that is heavily doped in said substrate using said stacked gate as a mask, g) forming sidewall spacers on sides of said stacked gate of an insulating material, then h) forming a drain that is heavily doped in said substrate using a sidewall spacer located on the sidewalls of the stacked gate as a mask.