Patent ID: 6858498
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A method for manufacturing a memory, comprising: forming a first insulating layer on a substrate; forming a first polysilicon layer over the first insulating layer; forming a mask layer on the first polysilicon layer; etching the mask layer to expose portions of the first polysilicon layer, and to define a first patterned region, a second patterned region and a third patterned region, wherein the third patterned region is located between the first patterned region and the second patterned region, the exposed portions of the first polysilicon layer locate in the first patterned region and the second patterned region, and the width of the third patterned region is equal to a predetermined length; etching the first polysilicon layer to remove the portion of the first polysilicon layer located in the second patterned region; implanting ions in the substrate to form a first doped region in the second patterned region; oxidizing the substrate to form a first silicon oxide region in the first patterned region, wherein the first silicon oxide region is formed on the first polysilicon layer; stripping the mask layer; etching the first polysilicon layer to form a first gate with using the first silicon oxide region as a mask, wherein the first gate is located in the first patterned region and is positioned underneath the first silicon oxide region, and a distance between the first gate and the first doped region is equal to the predetermined length; and implanting ions in the substrate to form a second doped region adjacent to the first gate, wherein the first gate is located between the first doped region and the second doped region.