Patent ID: 6388909
Filing Date: 2002-05-14
Classification: G11C

Abstract:
An associative memory comprising:an array of CAM (Content Addressable Memory) cells each for storing therein a bit of data fed on a bit line, said array being formed in rows corresponding to words of the data and columns corresponding to bits of the word; each of said CAM cells comprising a first transistor circuit taking either one of a first and a second state, the first and the second state representing that the bit stored in said CAM cell is consistent and inconsistent, respectively, with a bit of a reference word fed on the bit line; a first plurality of logic circuits provided correspondingly to the rows, each of said first plurality of logic circuits producing a first signal representing that the first transistor circuits of all of the CAM cells in corresponding one of the rows take the first state, and otherwise which of the first and second states the first transistor circuit of the CAM cell at an LSB (Least Significant Bit) position of the corresponding one row takes; a second plurality of logic circuits provided correspondingly to the columns, each of said second plurality of logic circuits detecting whether or not all of the first transistor circuits in corresponding one of the columns take the first state, and producing a second signal when all of the first transistor circuits in the corresponding one column take the first state; and a plurality of drive circuits provided correspondingly to the columns for each receiving a bit of an input or reference word, and driving the bit line of said CAM cells in corresponding one of the columns in response to the bit received; each of said drive circuits being operative in response to the second signal produced from corresponding one of said second plurality of logic circuits to mask the bit line to cause the first transistor circuits of all of the CAM cells in the corresponding one column to take the first state; whereby the first signal is developed from the first logic circuit in one of the rows which includes the first transistor circuits all of which take the first state to thereby accomplish a longest coincidence data detection.