Patent ID: 8316175
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. A memory system, comprising a plurality of separately accessible memory areas; a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory areas, wherein, when any one of the data memory areas is occupied, the controller is adapted to reconstruct data stored in the one occupied data memory area by reading parity information and data stored in at least one data memory area other than the one occupied data memory area, wherein the controller is further adapted to calculate parity information associated with a plurality of data pages to be written; to consecutively store the plurality of data pages to the respective data memory areas; to consecutively store the parity information to the respective parity memory areas; and whereupon a write or erase operation is performed such that only one of the data memory areas or parity memory areas is occupied by the write or the erase operation at any given time.