Patent ID: 8396696
Filing Date: 2013-03-12
Classification: G06F

Abstract:
1. A method comprising: providing a system graph of an electronic circuit comprising impedance components; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; using a processor, partitioning the tree into at least a first subtree and a second subtree; identifying links of the system graph as at least one of a global link or a local link, wherein a global link forms a path from a branch of the first subtree to a branch of the second subtree, the first subtree is formed by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a predefined count and there are branches in the tree which have not yet been assigned to a subtree, the second subtree is formed by repeatedly adding branches of the tree, not already assigned to the first subtree, to the second subtree when a number of branches in the second subtree is less than the predefined count and there are branches in the tree which have not yet been assigned to a subtree, and a loop with the global link and branches of the first and second subtrees has a voltage drop of 0; calculating a first current and voltage solution for each branch of the first subtree without global links; and calculating a second current and voltage solution for each branch of the second subtree without global links.