Patent ID: 6113646
Filing Date: 2000-09-05
Classification: G01R

Abstract:
A method of selecting a probe card matrix layout for integrated circuit wafer testing, the method comprising:defining a maximum number of test sites in the probe card matrix in both X and Y directions;defining a maximum number of test sites in the probe card matrix;specifying a number of rows in the wafer;specifying a number of integrated circuits provided in each row of the wafer;analyzing the number of rows in the wafer and the number of integrated circuits provided in each row of the wafer to determine a number of touchdowns needed to test each integrated circuit provided in the wafer for a plurality of probe card matrix configurations, wherein analyzing comprises:selecting a probe card matrix having a width W from one to X, and a height H from one to Y;selecting a first H rows from the wafer;identifying a longest one of the first H rows which contain the most integrated circuit die;dividing the longest one of the first H rows by width W, rounding a result up to the nearest integer;selecting remaining rows of the wafer in sets of H rows, identifying a longest row in each set, dividing the longest rows by W, and rounding a result up to the nearest integer; andsumming the results to identify a number of touchdowns required to test the integrated circuit wafer;providing data indicating a minimum number of touchdowns for each one of the plurality of probe card matrix configurations; anddesigning an integrated circuit probe card using the provided data.