Patent ID: 6258622
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A packaging method for integrated circuit device, said integrated circuit device including a chip and a leadframe, a surface of the chip being disposed with multiple solder bumps for electrically connecting with external side, the leadframe having multiple lead fingers, said packaging method comprising steps of:metallurgically processing certain sections of the lead fingers of the leadframe for carrying the chip so as to make the sections solder-attachable;respectively aligning the solder-attachable sections of the lead fingers of the leadframe with the solder bumps of the chip; andthrough heating and pressurizing processing, respectively fixedly connecting the solder-attachable sections of the lead fingers of the leadframe with the solder bumps of the chip, andwherein the metallurgically Processing step of the lead fingers further comprising the steps of:disposing an insulating material layer on the solder-attachable sections of the lead fingers of the leadframe; andforming orifices at certain positions of the insulating material layer for exposing the solder-attachable sections of the lead fingers.