Patent ID: 6387758
Filing Date: 2002-05-14
Classification: H01L

Abstract:
A method for fabricating a vertical field effect transistor on a semiconductor substrate, the method including the steps of:A. forming a first drain or source contact region doped with a first dopant within an active device area of said semiconductor substrate; B. depositing a bottom layer of doped insulating material on said semiconductor substrate, said bottom layer of doped insulating material being doped with a second dopant; C. depositing a layer of dummy material on said bottom layer of doped insulating material; D. depositing a top layer of doped insulating material on said layer of dummy material, said top layer of doped insulating material being doped with a third dopant; E. etching an opening through said top layer of doped insulating material, said layer of dummy material, and said bottom layer of doped insulating material; wherein said opening is disposed over said active device area of said semiconductor substrate such that said opening has a bottom wall of said semiconductor substrate; F. filling said opening with a semiconductor material to form a semiconductor fill contained within said opening; wherein said semiconductor fill has at least one sidewall with a top portion of said at least one sidewall abutting said top layer of doped insulating material, and with a middle portion of said at least one sidewall abutting said layer of dummy material, and with a bottom portion of said at least one sidewall abutting said bottom layer of doped insulating material; G. etching away said layer of dummy material such that said middle portion of said at least one sidewall of said semiconductor fill is exposed; wherein a gate electrode opening disposed between said top and bottom layers of doped insulating material is formed when said layer of dummy material is etched away; H. forming a gate dielectric of said vertical field effect transistor on said exposed middle portion of said at least one sidewall of said semiconductor fill; wherein said middle portion of said semiconductor fill abutting said gate dielectric forms a channel region of said vertical field effect transistor; I. filling said gate electrode opening between said top and bottom layers of doped insulating material with a gate electrode material, wherein said gate electrode material abuts said gate dielectric to form a gate electrode of said vertical field effect transistor; wherein said gate dielectric and said gate electrode formed at said at least one sidewall of said semiconductor fill is disposed on a plurality of planes of said channel region of said vertical field effect transistor; and J. performing a thermal anneal such that said second dopant diffuses from said bottom layer of doped insulating material into said bottom portion of said semiconductor fill to form a first drain or source extension junction of said vertical field effect transistor, and such that said third dopant diffuses from said top layer of doped insulating material into said top portion of said semiconductor fill to form a second drain or source extension junction of said vertical field effect transistor.