Patent ID: 6673685
Filing Date: 2004-01-06
Classification: H01L

Abstract:
An improved process for fabrication of a semiconductor device, comprising a step of forming a mask on a film from which a gate electrode is formed and transferring a circuit pattern to said mask, a step of trimming the mask in which a pattern dimension of said mask is reduced from a pattern dimension produced by exposure of the mask, and a step of gate-electrode etching/trimming in which the gate electrode having a dimension corresponding to but smaller than said reduced dimension is formed,wherein said mask trimming step and said gate-electrode etching/trimming step are performed in a same chamber under different conditions, wherein a dry cleaning step and an ashing step are included and at least two of the mask trimming step, the gate-electrode etching/trimming step, the ashing step, and the dry cleaning step are carried out in different chambers and wafer transfer from one said chamber to another is performed in a vacuum environment, and wherein the wafer is inspected for dimensions and contaminants while being transferred without exposure to atmosphere through the mask trimming step, the gate-electrode etching/trimming step, the ashing step, and the dry cleaning step, and results of each inspection are used to control a condition of a subsequent step.