Patent ID: 6984564
Filing Date: 2006-01-10
Classification: H01L

Abstract:
1. A method of forming an SRAM cell in an integrated circuit having first and second pull-down and first and second pull-up transistors connected as cross-coupled inverters having first and second input nodes connected to first and second pass gate transistors, comprising the steps of: forming said transistors in a semiconductor substrate; depositing a first layer of dielectric material over at least one of said pass gate transistors at a deposition temperature such that said at least one pass gate transistor is subject to a compressive magnitude of compressive stress in operation, said magnitude of compressive stress being adapted to raise the threshold voltage of said at least one pass gate transistor; and applying stress to at least one of said pull-down transistors connected to said at least one pass gate transistor such that said at least one pull-down transistor is subject to a tensile magnitude of tensile stress in operation, said magnitude of tensile stress being adapted to lower the threshold voltage of said at least one pull-down transistor.