Patent ID: 6504782
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory apparatus, comprising:a memory cell array section; a first power supply generating circuit supplying a first power supply voltage of said memory cell array section; a second power supply generating circuit supplying a second power supply voltage of a write amplifier transmitting a write data to said memory cell array section, and wherein said first power supply generating circuit and said second power supply generating circuit are independent of each other; and wherein said first power supply generating circuit controls a supplying amount of said first power supply voltage in response to a first control signal; and wherein said first power supply generating circuit supplies a step-down voltage from an external power supply as said first power supply voltage and includes a first current mirror circuit and a first output transistor, and wherein said first current mirror circuit has first, second, third, fourth, fifth, and sixth transistors, each of said first, second, third, fourth, fifth, and sixth transistors having first and second electrodes and a control electrode, and wherein said second electrode of said first transistor is connected to said external power supply and said control electrode of said first transistor is connected to said first electrode of said first transistor, and wherein said second electrode of said second transistor is connected to said external power supply and said control electrode of said second transistor is connected to said control electrode of said first transistor, and wherein said first electrode of said third transistor is connected to said first electrode of said first transistor, and wherein said first electrode of said fourth transistor is connected to said first electrode of said second transistor and said control electrode of said fourth transistor is connected to a reference voltage of said first power supply voltage and said second electrode of said fourth transistor is connected to said second electrode of said third transistor, and wherein said first electrode of said fifth transistor is connected to said second electrode of said third transistor and said control electrode of said fifth transistor inputs said first control signal and said second electrode of said fifth transistor is connected to a first potential, and wherein said first electrode of said sixth transistor is connected to said second electrode of said fourth transistor and said control electrode of said sixth transistor is connected to said external power supply and said second electrode of said sixth transistor is connected to said first potential, and wherein said second electrode of said first output transistor is connected to said external power supply and said control electrode of said first output transistor is connected to said first electrode of said second transistor and said first electrode of said first output transistor is connected to said control electrode of said third transistor to output said first power supply voltage, and wherein a transistor size of said fifth transistor is different from a transistor size of said sixth transistor.