Patent ID: 9059194
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method of semiconductor device manufacture including a plurality of electronic elements formed on or in a semiconductor chip, said method comprising steps of forming apertures in a layer of material extending over other material comprising an electronic element, depositing semiconductor material in said apertures, recessing said semiconductor material in said apertures such that a surface of said semiconductor material is at a location intermediate between upper and lower surfaces of said layer of material, applying an organic planarizing layer (OPL) over a surface of said layer of material and within said apertures, partially removing said OPL within said apertures to form OPL plugs in said apertures, said OPL plugs being of differing thickness due to differing etch rates in different areas of said semiconductor chip, performing a material removal process on said layer of material around said apertures or OPL plugs, and removing said OPL plugs selectively to said layer of material and said semiconductor material whereby differences in amount of material removal due to said differing etch rates at different locations on said semiconductor chip are absorbed by said OPL plugs and said location of said surface of said semiconductor material remains between said upper and lower surfaces of said layer of material.