Patent ID: 8619880
Filing Date: 2013-12-31
Classification: H04N

Abstract:
1. A device comprising: a processor; a memory coupled with a processor; the processor operative to implement a set of instructions to commandeer an in-loop deblocking filtering engine and to universally correct blockiness in a decoded output signal during a post-loop filtering operation using the in-loop deblocking filtering engine, wherein universally correcting blockiness comprises: determine tile edges of inter macroblocks; turning on the in-loop deblocking filtering engine for tile edges not located on a block boundary of a respective inter macroblock to correct inherited blockiness; performing a strong filtering operation on skipped inter macroblocks by reducing all quantization step size thresholds by a constant, increasing a first filter offset, and increasing a second filter offset, wherein the skipped inter macroblocks are not coded and exclude motion vector and texture information in bitstream; performing the strong filtering operation on inter macroblocks that are not skipped but for which a coded block pattern is equal to zero by reducing all quantization step size thresholds by the constant, increasing the first filter offset, and increasing the second filter offset; determine tile edges of intra macroblocks, correcting the blockiness for the intra macroblocks using a calculated boundary strength based on a plurality of quantization step size thresholds and applying the post-loop filtering operation according to the calculated boundary strength on pixels around the block boundary of respective intra macroblocks; and wherein the calculated boundary strength is equal to an integer greater than zero, when the determined tile edges of intra macroblocks are on the block boundary of respective intra macroblocks and the calculated boundary strength is equal to zero, when the determined tile edges are not on the block boundary of respective intra macroblocks.