Patent ID: 6566209
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method of forming MOSFET transistors in the fabrication of an integrated circuit device comprising:providing a gate oxide layer overlying a semiconductor substrate; depositing a first metal layer overlying said gate oxide layer; depositing a silicon nitride layer overlying said first metal layer; patterning said silicon nitride layer and said first metal layer to form temporary gates for planned said MOSFET transistors; implanting ions into said substrate to form lightly doped drain regions wherein said temporary gates act as implanting masks; forming sidewall spacers adjacent to said temporary gates and overlying a part of said lightly doped drain regions; implanting ions into said substrate to form heavily doped junctions where said temporary gates and said sidewall spacers act as masks for said implanting and wherein said heavily doped regions and said lightly doped regions form the source and drain junctions for said planned MOSFET transistors; depositing a barrier layer overlying said semiconductor substrate; thereafter etching away said silicon nitride layer; depositing a second metal layer overlying said barrier layer, said first metal layer, and said sidewall spacers; and polishing down said second metal layer to below the top surfaces of said sidewall spacers to complete said MOSFET transistors by forming permanent gates from said temporary gates, and to form conductive connections overlying said source and drain junctions.