Patent ID: 6331788
Filing Date: 2001-12-18
Classification: H03K,Y10S

Abstract:
A field programmable gate array (FPGA) having a 2-input Boolean look-up-table-based (2LUT-based) architecture comprising:a. one or more arrays (tiles), each comprised of a plurality of LUTs arranged in a directed, repeatable x-column, y-row grid propagating in the positive y direction, with each LUT having only nearest neighbor connections to other LUTs and not any other bridging structures except at the boundaries, the definition of each LUT behavior in a tile being allowed to be distinct and individually programmable for a particular logic function;b. each of said tiles having no specialized routing structures, since logic functions can imitate wiring from any LUT input to an output, allowing the LUTs to emulate both logic and (virtual) wiring; andc. periodic, alternating neighborhood templates in both horizontal and vertical directions for all LUTs in a particular tile.