Patent ID: 9104479
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry configured to perform a round to integral floating-point operation for rounding a floating-point value to an integral floating-point value, said floating-point value having a significand and an exponent; and control circuitry configured to control said processing circuitry to perform said round to integral floating-point operation in response to execution of a floating-point round to integral floating-point instruction; said processing circuitry comprising: shifting circuitry configured to generate a rounding value by shifting a base value by a shift amount dependent on said exponent of said floating-point value; adding circuitry configured to add said rounding value to said significand of said floating-point value to generate a sum value; mask generating circuitry configured to generate a mask for clearing bits of said sum value having bit positions corresponding to fractional-valued bit positions of said significand; and masking circuitry configured to apply said mask to said sum value to generate said integral floating-point value, wherein said processing circuitry has at least one rounding mode for selecting, when said floating-point value lying between two integral floating-point values, which of said two integral floating-point values to round said floating-point value to during said round to integral floating-point operation, and wherein said processing circuitry has a round to nearest, ties to even, (RNE) rounding mode for rounding said floating-point value to the nearest of said two integral floating-point values, with floating-point values lying halfway between said two integral floating-point values being rounded to the one of said two integral floating-point value that is an even value, and wherein said RNE rounding mode, if said floating-point value lies halfway between said two integral floating-point values, and a least significant integral-valued bit of said significand has a zero bit value, then said mask generating circuitry is configured to correct said mask, and said masking circuitry is configured to apply said corrected mask to said sum value to clear a bit of said sum value having a bit position corresponding to said least significant integral-valued bit of said significand.