Patent ID: 6407585
Filing Date: 2002-06-18
Classification: H03K

Abstract:
A self-clocking dynamic logic gate coupled to receive an output signal from a first stage dynamic logic gate, the self-clocking dynamic logic gate comprising:a PMOS/NMOS transistor pair coupled between a high voltage rail and a low voltage rail for receiving the output signal which activates the PMOS transistor and deactivates the NMOS transistor when the output signal is in a first state and which activates the NMOS transistor and deactivates the PMOS transistor when the output signal is in a second state; at least one other transistor coupled between the PMOS/NMOS transistor pair and the low voltage rail for receiving an external input signal and activating if the external input signal is in a preselected state; and an output node configured between the PMOS/NMOS transistor pair, which is precharged to the high voltage rail when the PMOS transistor is activated and which is selectively discharged to the low voltage rail only if both the NMOS transistor is activated and the external input is in the preselected state, thereby activating the at least one other transistor.