Patent ID: 9195596
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. An apparatus comprising: a controller configured to generate (i) an index signal and (ii) an information signal in response to (i) one or more address signals and (ii) a data signal; and a memory configured to store said information signal in one of a plurality of cache lines comprising a plurality of sectors, wherein each of said plurality of cache lines has an associated one of a plurality of cache headers, wherein each of said plurality of cache headers includes (i) a first bit configured to indicate whether said associated cache line has all valid entries, (ii) a second bit configured to indicate whether said associated cache line has at least one dirty entry, and (iii) said index signal configured to point to a changeable location of a status block in said associated cache line containing status information for said associated cache line, wherein said status block stores status information about whether each sector of said plurality of sectors is current or not current, and said status information is stored only when said second bit is set to indicate at least one dirty entry in said associated cache line.