Patent ID: 6404667
Filing Date: 2002-06-11
Classification: G11C

Abstract:
A 2T-1C ferroelectric random access memory comprising:a semiconductor substrate having a plurality of potential wells formed by doping the semiconductor substrate with first impurities; a plurality of memory cells each having two transistors and one capacitor; a plurality of connection lines electrically connecting the memory cells in the form of a matrix; and a plurality of dummy capacitors, wherein the two transistors include: a source formed by doping a semiconductor within each potential well with second impurities; a first drain and a second drain formed by doping the semiconductor within each potential well with the second impurities in a predetermined interval, respectively, so as to be arranged in line with the source in a first direction; a first gate formed on an insulation layer which is formed on a first channel between the source and the first drain; and a second gate formed on an insulation layer which is formed on a second channel between the first drain and the second drain, and wherein the one capacitor includes: a bottom electrode formed on an insulation layer which is formed on the source; a ferroelectric layer formed on the bottom electrode; and a top electrode formed on the ferroelectric layer, and wherein the connection lines include: first word lines connecting the first gate arranged in the first direction in each memory cell; bit lines connecting the first drains of the memory cells arranged in the second direction, which is perpendicular to the first direction, and to which the dummy capacitors are commonly connected; second word lines connecting the second gate of the memory cells arranged in the second direction; sensing lines connecting the second drains of the memory cells arranged in the second direction; contact plugs connecting the source and the bottom electrode in each cell; and plate lines connecting the top electrodes of the memory cells arranged in the second direction.