Patent ID: 8189401
Filing Date: 2012-05-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; a first data latch circuit which latches first readout data read out from the memory cell by using a parameter of an actual read level; a second data latch circuit which latches second readout data read out from the memory cell by using a parameter of a level shifted to be higher than the actual read level; an arithmetic circuit which performs an arithmetic operation on the first readout data and the second readout data; a counter circuit which counts the number (N) of differences between the first readout data and the second readout data in an operation result from the arithmetic circuit; and a controller which compares the number (N) with a reference number (M), and performs control to output flag information outside if N≧M.