Patent ID: 7805645
Filing Date: 2010-09-28
Classification: G11C

Abstract:
1. A data processing apparatus comprising: a memory device having an array of memory cells for storing data values; test circuitry employed in a test mode of operation to execute one or more test patterns in order to detect any defective memory cells which, due to cell instability following a write operation, will malfunction in a normal mode of operation if a read operation follows said write operation, each test pattern causing a sequence of access requests to be issued to the memory device, where the timing of said sequence is controlled by a test mode clock signal; and dummy read control circuitry employed in the test mode of operation, and responsive at least to each write access request in the sequence of access requests, to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal, the dummy read control circuitry further, responsive to each write access request, to perform using the internal clock signal a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same at least one memory cell, the dummy read operation serving to stress the at least one memory cell with respect to cell stability, but with a result of the dummy read operation not being used by the test circuitry, whereby the dummy read operation causes said malfunction of any said defective memory cells to which said write operation is performed, such that a later read operation issued by said one or more test patterns to those defective memory cells will cause said malfunction to be detected irrespective of any delay between said write operation and said later read operation.