Patent ID: 6434070
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A semiconductor integrated circuit, comprising:a memory cell array region including a plurality of memory cells arranged in rows and columns, a plurality of word lines provided corresponding to the respective rows of said memory cells, and a plurality of bit lines provided corresponding to the respective columns of said memory cells; and a voltage generating circuit receiving a first power supply voltage for generating a bit line voltage for use in precharging said plurality of bit lines, said voltage generating circuit including a voltage transforming circuit receiving said first power supply voltage for generating a second power supply voltage having a voltage level equivalent to a reference value of said bit line voltage, and a voltage control circuit receiving said second power supply voltage for outputting said bit line voltage, said voltage control circuit including at least one of a voltage boost circuit boosting said second power supply voltage for generating said bit line voltage and a voltage step-down circuit reducing said second power supply voltage for generating said bit line voltage.