Patent ID: 7409533
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. An integrated circuit, comprising: a plurality of hardware object nodes each operating independently from one another, and each having a sending port structured to send an outgoing data message from its associated hardware object node, and structured to store the outgoing data message and a set of protocol information that describes a validity of data in the outgoing data message to be sent and indicates an ability for a next portion of the outgoing data message to be received by a successive object node, the sending port including a first register to store validity information received from a selector having a first input coupled to an output of a second register that selectively stores validity information, and having a second input that bypasses the second register; and a receiving port structured to receive an incoming data message for the associated hardware object node, and structured to store the incoming data message and a set of protocol information describing data received in the incoming data message and an indication of an ability for the associated hardware object to accept a next portion of the incoming data message, the receiving port including a third register to store validity information received from a selector having a first input coupled to an output of a fourth register that selectively stores validity information, and having a second input that bypasses the fourth register; and a communication network including a plurality of individual communication channels coupled between a sending port of a first respective one of the plurality of hardware object nodes and a receiving port of a second respective of one of the plurality of the hardware object nodes, at least two of the plurality of communication channels operating at different communication frequencies from one another.