Patent ID: 6570417
Filing Date: 2003-05-27
Classification: H03K

Abstract:
A dividing circuit comprising:a first circuit portion including a synchronous counter, the synchronous counter including at least a first group of bistable devices each including an output port and being configured (i) to receive as an input a master clock signal and (ii) to produce an output signal at the output port in response to receiving the master clock signal; and at least a second circuit portion including a plurality of stages, each stage including at least one bistable device from a second group of bistable devices and being coupled, at least indirectly, to one of the output ports of the first group of bistable devices and with the other stages to produce an output clock signal; wherein each stage is configured to receive as an input a respective slaved clock signal, each respective slaved clock signal being shifted in phase from the master clock signal; and wherein the at least second circuit portion is configured to produce the output clock signal, a frequency of the output clock signal being equal to a frequency of the master clock signal divided by a non-integer value.