Patent ID: 8022776
Filing Date: 2011-09-20
Classification: H03B,H03D,H03F

Abstract:
1. A cascode arrangement of transistors comprising: N stages, where N>1 and where each stage comprises: (i) a first transistor and a plurality of second transistors, each transistor of said first transistor and said plurality of second transistors having a control electrode and two current carrying electrodes, the control electrode of said first transistor being coupled to a circuit input for a first stage or to an output of a preceding stage in the path of at least one of said plurality of second transistors for any subsequent stages and the control electrode of the at least one of said plurality of second transistors being coupled to a bias voltage, and (ii) at least one transformer having a primary winding and a secondary winding, a first current carrying electrode of said first transistor being coupled to a first power supply source via the primary winding of the transformer, a second current carrying electrode of said first transistor being coupled to a second power supply source, and a second current carrying electrode of the at least one of said plurality of second transistors being coupled to a second power supply source via the secondary winding of the transformer, a first current carrying electrode of the at least one of said plurality of second transistors being coupled to said first power supply source via an inductive load and providing the output for either a succeeding stage or a circuit output for a final stage of said N stages; (iii) wherein each one of the control electrodes of said plurality of second transistors is coupled to a different bias voltage; and (iv) wherein at least one of said plurality of second transistors is transformer coupled to said first transistor and the remaining of said plurality of second transistors have associated transformers for interconnection to another one of said plurality of second transistors.