Patent ID: 6121135
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device comprising:providing a layer of gate silicon oxide over the surface of a semiconductor substrate;depositing a first layer of polysilicon overlying said gate silicon oxide layer;etching away said first polysilicon and said gate oxide layer where they are not covered by a mask to provide an opening to said semiconductor substrate where a planned buried contact junction will be formed;depositing a second polysilicon layer overlying said first polysilicon layer and said planned buried contact junction and doping said second polysilicon layer whereby said planned buried contact junction is formed in said semiconductor substrate underlying said doped second polysilicon layer;planarizing said second polysilicon layer;etching away said first and second polysilicon layers where they are not covered by a mask to provide an opening overlying a portion of said buried contact junction wherein a trench is etched into said semiconductor substrate where said semiconductor substrate is not covered by said gate oxide layer;depositing an oxide layer overlying said second polysilicon layer, said gate oxide layer exposed within said opening and within said trench;etching away said oxide layer where it is not covered by a mask wherein said trench and a portion of said second polysilicon layer overlying said buried contact junction and adjacent to said trench are exposed and whereby said oxide is removed from said trench;depositing a third polysilicon layer overlying said oxide layer and said second polysilicon layer and said trench exposed within said opening; andpatterning said third polysilicon layer whereby said third polysilicon layer forms a butted contact with said second polysilicon layer exposed within said opening completing said fabrication of said integrated circuit device.