Patent ID: 8072019
Filing Date: 2011-12-06
Classification: H01L

Abstract:
1. A flash memory comprising: a shallow trench isolation layer and an active region formed at a substrate; a plurality of stacked gates formed on the active region; a deep implant region formed at a lower side of the shallow trench isolation layer and the active region between the stacked gates; and a shallow implant region formed at a surface of the active region between the stacked gates, wherein the deep implant region comprises: a first ion implantation region formed at the active region between the stacked gates at a depth less than that of the shallow trench isolation layer; a second ion implantation region formed at the active region between the stacked gates at a depth greater than that of the first ion implantation region; and a third ion implantation region formed at the lower region of the shallow trench isolation layer and the active region between the stacked gates at a depth greater than that of the shallow trench isolation layer, wherein the third ion implantation region is connected in a straight line to the lowermost portion of the shallow trench isolation layer and the active region between the stacked gates.