Patent ID: 6274443
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method for manufacturing a MOS structure on a semiconductor substrate, comprising the steps of:forming a gate oxide layer over the semiconductor substrate;forming a polysilicon layer over said gate oxide layer;forming a first mask layer over said polysilicon layer;patterning and etching said first mask layer to form a first gate mask;anisotropically etching said polysilicon layer to form a first polysilicon gate, wherein said first polysilicon gate has sidewalls with sloped profiles, said sidewalls shield a portion of the semiconductor substrate;implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form one or more shallow extension junctions and a doped resistor region in the semiconductor substrate;anisotropically etching said first polysilicon gate to form a second polysilicon gate using said first gate mask as a mask, wherein said second polysilicon gate has sidewalls with substantially vertical profiles;removing said first gate mask;forming a resistor protect layer over said gate oxide layer, said doped resistor region, and said second polysilicon gate;selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, and a first sidewall spacer around said second polysilicon gate; andremoving said resistor protect mask to expose said resistor isolation.