Patent ID: 9019672
Filing Date: 2015-04-28
Classification: H01L,H02H

Abstract:
1. A chip with electrostatic discharge (ESD) protection function, comprising: a first power rail electrically connected to a source voltage; a second power rail electrically connected to a reference voltage; a pin; a P-type FinFET comprising a first terminal, a second terminal and a first control terminal, the P-type FinFET being configured to have the first terminal thereof electrically connected to the first power rail, and the first control terminal thereof configured for receiving a transmission signal; a first Fin-resistor comprising a third terminal, a fourth terminal and a second control terminal, the first N-type Fin-resistor being configured to have the third terminal and the second control terminal thereof both electrically connected to the second terminal, and the fourth terminal thereof electrically connected to the pin; an N-type FinFET comprising a fifth terminal, a sixth terminal and a third control terminal, the N-type FinFET being configured to have the sixth terminal thereof electrically connected to the second power rail, and the third control terminal thereof configured for receiving the transmission signal; a second Fin-resistor comprising a seventh terminal, an eighth terminal and a fourth control terminal, the second N-type Fin-resistor being configured to have the eight terminal and the fourth control terminal thereof both electrically connected to the fifth terminal, and the seventh terminal thereof electrically connected to the pin; a first diode configured to have an anode thereof electrically connected to the pin and a cathode thereof electrically connected to the first power rail; a second diode configured to have an anode thereof electrically connected to the second power rail and a cathode thereof electrically connected to the pin; and an ESD unit, electrically connected between the first and second power rails, configured to provide an ESD path between the first and second power rails.