Patent ID: 6894912
Filing Date: 2005-05-17
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cells wherein each of said plurality of memory cells is connected at one of a plurality of intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers coupled to said plurality of bit lines; a plurality of data registers which holds date inputted from data input/output terminal; an encoding control circuit; encoders to write data to said sense amplifiers based on data held in said plurality of data registers and signals outputted from said encoding control circuit; and a plurality of input/output lines, wherein encoders are coupled to the plurality or sense amplifiers by the pluralty of input/output lines; and wherein the plurality of the input/output lines transfer data from the encoders to the plurality of sense amplifiers and from the plurality of sense amplifiers to the encoders.