Patent ID: 9136334
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A semiconductor device comprising: an undoped group III-V compound channel layer between a group III-V compound semiconductor upper barrier layer and a group III-V compound semiconductor lower barrier layer; a carrier supply region of the group III-V compound semiconductor upper barrier layer between a first high-resistance region of the group III-V compound semiconductor upper barrier layer and a second high-resistance region of the group III-V compound semiconductor upper barrier layer; a low-resistance region of a first conductivity-type in the first high-resistance region, the first conductivity-type being opposite to a second conductivity-type; a source region of the second conductivity-type in the first high-resistance region, a source electrode and the low-resistance region touching the source region; a drain region of the second conductivity-type in the first high-resistance region, a drain electrode and the low-resistance region touching the drain region; a gate insulating layer between a gate electrode and the low-resistance region, the gate insulating layer physically isolating the gate electrode from the low-resistance region, wherein the second high-resistance region is between the carrier supply region and the undoped group III-V compound channel layer.