Patent ID: 6586815
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A semiconductor device having a plurality of memory-cell blocks, each memory-cell block comprising a pair of memory-cell areas and a fuse area sandwiched between the memory-cell areas, the fuse area comprising:a guard ring arranged in a peripheral part of the fuse area; a fuse window arranged within said guard ring; a plurality of dummy interconnections being arranged in parallel with each other, traversing said guard ring and said fuse window, each dummy interconnection comprising: a first fuse wiring having a first terminal portion; a second fuse wiring having a second terminal portion with a given distance apart from said first terminal portion, being arranged along the same direction as a longitudinal direction of said first fuse wiring, configured such that said given distance is measured along the longitudinal direction; an interlayer insulating film disposed on said first and second fuse wirings; a first pillar like contact plug burying a first contact hole formed in said interlayer insulating film configured such that the first pillar like contact plug is arranged on and contacted to said first terminal portion; a second pillar like contact plug burying a second contact hole formed in said interlayer insulating film configured such that the second pillar like contact plug is arranged on and contacted to said second terminal portion; and a fuse body configured to be arranged in a topology such that the fuse body is alternately arranged on at least three rows, the rows run in the direction perpendicular to the longitudinal direction of said first and second fuse wirings, and the fuse body is being disposed on said first and second pillar like contact plugs so as to electrically connect said first and second pillar like contact plugs wit each other, having a length not longer than a diameter of a laser beam used for blowing off the fuse body.