Patent ID: 7103055
Filing Date: 2006-09-05
Classification: H04L

Abstract:
1. A network switch for network communications, said network switch comprising: at least one data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate and a second data rate, said at least one data port interface including an ingress logic circuit in communication with said at least one data port interface for generating at least one of an ingress address resolution and a filtering search request; a CPU interface, said CPU interface configured to communicate with a CPU; a shared hierarchical memory structure, wherein said shared hierarchical memory structure includes an internal memory in communication with the at least one data port interface, and an external memory in communication with a memory management unit via an external memory interface; a communication channel, said communication channel for communicating data between said at least one data port interface, said internal memory, said CPU interface, and said memory management unit, and a unified table, said unified table being in connection with the communication channel, and the at least one data port interface, said unified table containing packet handling data for the network switch comprising address resolution information including L