Patent ID: 6740584
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A semiconductor device fabricating method comprising:a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon, upper surfaces and side surfaces of said conductive elements being covered with a silicon oxide film; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements; a third step of forming an interlayer insulating film so as to cover said etching resistant film, the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer, the lower interlayer having a higher etching rate than the upper interlayer; a fourth step of forming a hole in said interlayer insulating film, reaching at least to said etching resistant film between said plurality of conductive elements; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole to said semiconductor base layer; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching.