Patent ID: 8710669
Filing Date: 2014-04-29
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of said core substrate and a second surface opposite to said first surface; a via(s) which is disposed in each of said insulating layer and said core substrate, and connects said wiring layers to each other; a semiconductor element, mounted on said first surface of said core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on said first surface and directly connects the electrode terminal of said semiconductor element and the wiring layer disposed on said first surface, wherein a minimum wiring pitch of the wiring layer directly connected to said connecting portion is smaller than that of any of the wiring layer(s) disposed on said second surface.