Patent ID: 7964460
Filing Date: 2011-06-21
Classification: H01L

Abstract:
1. A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising: forming a first high-k gate dielectric disposed over a first region but not over a second region of a workpiece; forming a second high-k gate dielectric disposed over the second region but not over the first region of the workpiece, the second high-k gate dielectric comprising a top surface; forming a continuous conductive gate material layer comprising a first type of doping disposed over the first high-k gate dielectric and the top surface of the second high-k gate dielectric; implanting a metallic impurity into the second region but not into the first region; modifying the top surface of the second high-k gate dielectric to comprise the metallic impurity, wherein the modifying the top surface of the second high-k gate dielectric changes electrical behavior of the second high-k dielectric, and wherein the modifying is done during the implanting of the metallic impurity into the second region; forming an NMOS transistor in the first region, the NMOS transistor utilizing the first high-k gate dielectric as a gate dielectric, and forming a PMOS transistor in the second region, the PMOS transistor utilizing the second high-k gate dielectric as a gate dielectric.