Patent ID: 6441632
Filing Date: 2002-08-27
Classification: G01R

Abstract:
A self-aligning contractor assembly for testing semiconductor devices or device under test (DUT) comprising:a first plate with parallel bottom and top planar surfaces with a recessed portion on the bottom surface wherein the recessed portion has a plurality of small apertures of uniform size passing through both the top and bottom recessed surface; a second positioning plate having outer sidewalls around the periphery and a top and bottom planar surfaces which are parallel to the surfaces of the first plate and a plurality of small apertures extending through the bottom and top surfaces that are axially aligned with the aperture in the first plate; a third alignment plate positioned between said first plate and said second plate wherein the third alignment plate with top and bottom parallel planar surfaces that has an outer peripheral sidewalls that conformly fits within the recessed cavity formed by the recessed area of the first plate and having a plurality of large apertures that are axially aligned with said smaller apertures of the first and second plate; and a plurality of pogo pins that are biased at both ends and are loosely positioned within said aperture of the first and third plate such that the ends of said pogo pins extend beyond the top and bottom surfaces of the first and second plate.