Patent ID: 6794678
Filing Date: 2004-09-21
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device comprising:a first terminal which receives a first clock signal outside of said semiconductor integrated circuit device; a second terminal which receives an address signal outside of said semiconductor integrated circuit device; a third terminal which receives a second clock signal outside of said semiconductor integrated circuit device, said second clock signal has a frequency lower than a frequency of said first clock signal; a delay circuit which delays said address signal; a control circuit which receives said first clock signal, said second clock signal, and said address signal, and outputs a control, signal in accordance with whether said semiconductor integrated circuit is in a normal operation mode or a test mode for testing at least one of a write time and a bit-line precharge time; and a memory circuit which receives said control signal, and includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein in the normal operation mode, a selecting operation of one of said plurality of word lines is terminated by an output of said delay circuit, wherein in the test mode, another selecting operation of one of said plurality of word lines operation is terminated by said second clock signal.