Patent ID: 7461107
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. A converter circuit for converting a 1-redundant representation of an N-bit integer to a (1/K)-redundant representation in the form y 0 , . . . y N−1 and z K , z 2K , . . . , z [(N−1)/K]K are sets of binary values, the converter circuit comprising: a (K−1)-bit adder receiving (K−1) least significant bits of the 1-redundant representation, the (K−1)-bit adder providing a group of K least significant bits of the (1/K)-redundant representation, where K is an integer greater than 1 and less than N; a K′-bit adder receiving K′ most significant bits of the 1-redundant representation, the K′-bit adder providing a group of K′+1 most significant bits of the (1/K)-redundant representation, wherein K′ is an integer not greater than K; and at least one K-bit adder receiving a group of K bits of the 1-redundant representation between the K′ most significant bits and the K−1 least significant bits, each K-bit adder providing a group K+1 bits of the (1/K)-redundant representation between the group of most significant bits and the group of least significant bits.