Patent ID: 7822950
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A method of controlling a computer processor for processing a first and a second thread in a pipeline, each thread having one or more sequential instructions to perform in the pipeline, the method comprising the steps of: identifying a first instruction as being part of the first thread using a thread identifier, the first instruction associated with a program counter which includes information identifying the first thread and an address of the first instruction in a memory; responsive to said first instruction encountering the presence of a pipeline hazard, retrieving the program counter associated with the first instruction, canceling the first instruction and all subsequent instructions associated with the thread identifier in the pipeline in the first thread before a subsequent instruction from the first thread is processed in the pipeline while continuing to execute instructions from another thread and identifying the second thread from a scheduling table, the scheduling table specifying a predefined temporal order in which the first thread and second thread are retrieved to be processed; processing the second thread in the pipeline, wherein instructions of said first and second threads may be simultaneously processed in said pipeline; and refetching the cancelled instructions using the program counter and the thread identifier associated with the first instruction to re-execute the cancelled instructions of the first thread in the pipeline while said second thread is processed in said pipeline.