Patent ID: 6708244
Filing Date: 2004-03-16
Classification: G06F

Abstract:
A circuit comprising:a first storage circuit coupled to (i) a first bus interface and (ii) a second bus interface, wherein said first storage circuit is configured (i) to store a plurality of first message frames received from said first bus interface, (ii) to store a plurality of second message frames received from said second bus interface, (iii) to present said plurality of first message frames to said second bus interface and (iv) to present said plurality of second message frames to said first bus interface in response to one or more first message frame address signals and one or more second message frame address signals; and a control circuit (i) coupled to said first bus interface and said second bus interface and (ii) configured to store said one or more first and one or more second message frame address signals, wherein said one or more first and one or more second message frame address signals are transferred between said control circuit and (i) said first bus interface and (ii) said second bus interface such that said plurality of first message frames and said plurality of second message frames are transferred independently via said first storage circuit between said first and said second bus interfaces, wherein said first bus interface and said second bus interface simultaneously access said first storage circuit.