Patent ID: 7558139
Filing Date: 2009-07-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells, data being written to the memory cells by current carried in the memory cells; a plurality of word lines connected to nodes of the memory cells; a plurality of bit lines connected to the other nodes of the plurality of memory cells; a plurality of sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data to the memory cells via the bit lines and latching read data or data to be written; and a plurality of transfer gates connecting or disconnecting the sense amplifiers to or from the bit lines, wherein in a period of a serial access for continuously writing the data to the memory cells connected to an activated word line among the word lines, the transfer gates disconnect the sense amplifiers and the bit lines until all of the sense amplifiers to be selected in the serial access latch the data, and the transfer gates connect the selected sense amplifiers to the bit lines after all of the selected sense amplifiers latch the data.