Patent ID: 8321193
Filing Date: 2012-11-27
Classification: G06F

Abstract:
1. A design support system for supporting design of an integrated circuit which includes an interface circuit for communicating with a processor device that implements a predetermined function by executing a program, a user logical circuit that is hardware implementing a predetermined function, and an input/output (I/O) register circuit having an I/O register used for transmission and receipt of data between the processor device and the user logical circuit, the design support system comprising: an information apparatus for performing functions to design the integrated circuit; and a user interface for permitting a user to cause functions to be performed by said information apparatus to design the integrated circuit, wherein the information apparatus comprises: a memory for storing design data, and a processing unit for processing the design data in said memory, said processing performed by said processing unit includes: an I/O register access information extracting processing that generates I/O register access information based on the first behavior level design data which is design data at a behavior level subjected to modeling for the integrated circuit, the I/O register access information including information on access control from the user logical circuit to the I/O register and information on a specification of the I/O register; an address map edit processing that generates address map information including information on association of an software (SW) register with an hardware (HW) register, based on the I/O register access information and association of an SW address with an HW address, the association of the SW address with the HW address being acquired through the user interface, the SW register being a register defined on the processor device side, the HW register being a register defined on the user logical circuit side, the SW address being an address used when the processor device accesses the I/O register, the HW address being an address used when the user logical circuit accesses the I/O register; and an I/O register automatic generating processing that generates second behavior level design data, which is design data at the behavior level describing an internal structure of the I/O register circuit described in the first behavior level design data, based on the first behavior level design data and the address map information, wherein circuits that form the integrated circuit are classified into tiered groups and managed, and the I/O register access information outputted by the I/O register access information extracting processing includes information on at least one of: an I/O register scope that is information on access permission from the groups to the I/O register; an I/O register scope status that is information set in accordance with existence of writing of data from the groups to the I/O register or reading of data from the I/O register to the groups; an I/O register bit size that is information on a bit size of the I/O register; and an I/O register parity attribute that is information on existence of parity of the I/O register.