Patent ID: 6501675
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A dynamic random access memory device comprising:a plurality of wordlines; a plurality of memory cells for storing a 1-bit or a 0-bit; a pair of bitlines comprising a bitline true (BLT) and a bitline complement (BLC), each said plurality of memory cells being selectively connected to one of said BLT and BLC when a corresponding one of said plurality of wordlines is selected, a first pair of reference cells connected to said BLT; a second pair of reference cells connected to said BLC; and a controller for alternating said first pair of reference cells when a memory cell is connected to said BLC on successive cycles, and for alternating said second pair of reference cells when a memory cell is connected to said BLT on successive cycles; wherein said controller restores each of said BLT and said BLC to ground potential at a start of each cycle.