Patent ID: 6609233
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A method for providing improved load sensitivity modeling in a minimal level sensitive timing abstraction model modeling, comprising:extracting a plurality of parameters from a circuit that includes an input port and an output port; creating an echo-circuit that represents the plurality of parameters and models load sensitivity, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and includes a check node at the input port and a dummy latch node at the output port, wherein the dummy latch nodes is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port; and splitting the check node at the input port into multiple check nodes, wherein the multiple check nodes correspond to multiple input logic elements.