Patent ID: 7364959
Filing Date: 2008-04-29
Classification: H01L

Abstract:
1. A method for manufacturing a MOS transistor integrated into a chip of semiconductive material, said method comprising the steps of: forming first and second doped regions that extend from inside of the chip to a surface of the chip, the first doped region having a first conductivity type and the second doped region having a second conductivity type; forming an insulating layer of insulating material on the surface of the chip superimposing a conductive layer of conductive material on said insulating layer; defining directly above the second doped region an insulated gate electrode from said insulating and conductive layers; defining, from said insulating and conductive layers, an additional structure arranged on a first surface portion of the first doped region; and placing between the insulated gate electrode and the additional structure a dielectric spacer arranged on a second surface portion of the first doped region and on a surface portion of the second doped region.