Patent ID: 8984203
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A memory access control module, comprising: a first data interface for data transfer to and from a first data communication bus in accordance with a first data bus bit size and a first clock frequency; a plurality of arbitration modules connected for data communication with the first data interface in accordance with the first data bus bit size and the first clock frequency; a plurality of memory banks connected for data communication with the plurality of arbitration modules in accordance with the first data bus bit size and the first clock frequency, such that each of the plurality of memory banks is connected for data communication with a different one of the plurality of arbitration modules; a second data interface for data transfer to and from a second data communication bus in accordance with a second data bus bit size and a second clock frequency, the second data bus bit size an integer multiple of the first data bus bit size, the first clock frequency an integer multiple of the second clock frequency; a channelizer module connected for data communication with the second data interface in accordance with the second data bus bit size and the second clock frequency, the channelizer module further connected for data communication with the plurality of arbitration modules in accordance with the first data bus bit size and first clock frequency, the channelizer module defined to— a) segment data received from the second data interface during a store operation from the second data bus bit size into a number of data segments of the first data bus bit size, b) transmit the data segments of the first data bus bit size along respective data channels to addressed ones of the plurality of memory banks by way of corresponding ones of the plurality of arbitration modules in accordance with the first clock frequency during the store operation, c) receive data in accordance with the first data bus bit size and first clock frequency from addressed ones of the plurality of memory banks by way of corresponding ones of the plurality of arbitration modules during a load operation, and d) combine data received from the plurality of memory banks during the load operation into the second data bus bit size and transmit the combined data of the second data bus bit size to the second data interface in accordance with the second clock frequency.