Patent ID: 6526558
Filing Date: 2003-02-25
Classification: H03K

Abstract:
A method for configuring a field programmable gate array (FPGA) having long-haul interconnect lines and relatively shorter, short-haul interconnect lines for interconnecting configurable logic blocks (CLB's) of the FPGA, where the FPGA further has a plurality of shareable line drivers and a share-enabling plurality of dynamic multiplexers (DyMUX) that are connectable to said line drivers, where the line drivers can drive corresponding ones of the long-haul interconnect lines, said method comprising:(a) searching a supplied design definition for the presence of a source design component that is defined for producing and outputting a result signal and for the presence of one or more destination design components that are each defined for inputting the result signal, wherein placement of the source design component is constrained and placement of at least one of the destination design components is constrained such that use of a long-haul interconnect line is justified for conveying the result signal from the source design component to one or more of the destination design components; and (b) if such source and destination design components are found, modifying the placement of such design components so as to urge such design components towards placement near and use of the long-haul interconnect line for conveying the result signal therebetween.