Patent ID: 7741892
Filing Date: 2010-06-22
Classification: G11C

Abstract:
1. A data output controller comprising: a control signal generator configured to generate a control signal having a predetermined pulse width in response to a DQ off signal and a write signal; an enable signal generator configured to receive the control signal and a read signal and output a clock enable signal in synchronization with the control signal when the read signal is activated; and a clock generator configured to receive the clock enable signal and an internal clock signal, and generate a data clock signal in synchronization with the internal clock signal during an activation period of the clock enable signal, wherein the control signal generator includes: a first operation unit configured to perform a logical operation in response to a DQ off signal, a bank active signal and a write signal; a delay unit configured to output a delayed signal by delaying an output signal of the first operation unit; and a second operation unit configured to perform a logical operation with respect to the output signal of the first operation unit and the delayed signal of the delay unit.