Patent ID: 8643103
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; a first conductivity type semiconductor layer formed over the semiconductor substrate; a second conductivity type impurity layer formed in a surface layer of the semiconductor layer; a first conductivity type impurity layer formed in a surface layer of the second conductivity type impurity layer, excluding an edge thereof; a gate contact region formed such that, in a plan view, the first conductivity type impurity layer extends to surround the gate contact region; an upper gate electrode at least a portion of which is formed by way of an insulating layer over a region of the second conductivity type impurity layer in which the first conductivity type impurity layer is not formed, surrounding the first conductivity type impurity layer, wherein, in the plan view, the upper gate electrode is inwardly protruding at a portion of the upper gate electrode that overlaps with the gate contact region; a plurality of first buried gate electrodes formed in a region of the semiconductor layer in which the first conductivity type impurity layer is formed, buried in the semiconductor layer more deeply than the second conductivity type impurity layer, extending in parallel with each other along a first direction, and extending on both ends thereof beyond the first conductivity type impurity layer respectively thereby being connected to the upper gate electrode; a buried connecting electrode buried in the semiconductor layer at a position overlapping the upper gate electrode to a depth identical with that of the first buried gate electrodes, and connecting ends of the first buried gate electrodes to each other; and a plurality of source contacts buried in the semiconductor layer more deeply than the first conductivity type impurity layer and more shallowly than the bottom of the second conductivity type impurity layer, and each situated between each of the first buried gate electrodes, wherein at least some of the first buried gate electrodes extending in a direction overlapping the upper gate electrode situated in the gate contact region are situated at the ends thereof over the edge of the gate contact region in a plan view, wherein the ends are connected with each other by the buried connecting electrode, wherein the buried connecting electrode is not connected to the first buried gate electrodes on a side of the first buried gate electrodes situated adjacent to the first buried gate electrodes connected to each other at the ends thereof by the buried connecting electrode, and wherein the at least some of the first buried gate electrodes extend in a direction overlapping the gate contact region, in the plan view, only before reaching to a gate electrode disposed in the gate contact region, such that the at least some of the first buried gate electrodes are devoid of overlapping with the gate electrode disposed in the gate contact region.