Patent ID: 6806732
Filing Date: 2004-10-19
Classification: H03K

Abstract:
An interconnect multiplexing structure in a field programmable gate array (FPGA), the FPGA comprising a general interconnect structure comprising a plurality of signal lines, the interconnect multiplexing structure comprising:a first select terminal coupled to a first signal line from the general interconnect structure; a configuration memory cell; a plurality of data input terminals coupled to a first plurality of signal lines from the general interconnect structure; a first data output terminal coupled to a second signal line from the general interconnect structure; and a first multiplexing circuit having a plurality of multiplexing data terminals coupled to the data input terminals, a first multiplexing select terminal coupled to the first select terminal, a second multiplexing select terminal coupled to the configuration memory cell, and a multiplexing output terminal coupled to the first data output terminal, wherein the first multiplexing circuit comprises: an internal node; a plurality of transistors coupled between the plurality of multiplexing data terminals and the internal node; a plurality of logic gates controlling the plurality of transistors; and a buffer coupled between the internal node and the multiplexing output terminal.