Patent ID: 8030166
Filing Date: 2011-10-04
Classification: G11C,H01L

Abstract:
1. A method for manufacturing an array of memory cells on a semiconductor substrate, comprising: providing a substrate having a channel conductivity type with a first concentration of dopants; forming a plurality of insulator-filled trenches in the substrate, separated by strips of the semiconductor substrate; implanting lateral pockets of dopants having the channel conductivity type in the substrate along sides of the strips adjacent the plurality of insulator-filled trenches, so that the lateral pockets adjacent the insulator-filled trenches have a second concentration of dopants higher than the first concentration of dopants; forming dielectric charge trapping structures over the strips, and forming word lines arranged orthogonally with respect to the strips and over the dielectric charge trapping structures, the dielectric charge trapping structures and the word lines overlying at least portions of the lateral pockets in the strips; implanting source/drain dopants in the strips adjacent the word lines to define source/drain terminals having a conductivity type opposite to the channel conductivity type; and forming an array of bit lines over the word lines arranged to contact the strips.