Patent ID: 7082425
Filing Date: 2006-07-25
Classification: G06F,G06Q,Y10S

Abstract:
1. A real-time searching device comprising: a plurality of shift registers a number of shift registers corresponding to a maximum search term length plus one to accommodate for a misalignment condition, the shift registers including a first shift register and an additional shift register, the plurality of shift registers to receive a data stream of characters; a first plurality of memory units arranged in groups, a number of groups of the first plurality of memory units corresponding to the maximum search term length, each group of the first plurality of memory units having a number of memory units corresponding to a maximum dictionary size, each of the first plurality of memory units coupled to one of the shift registers except for the additional shift register, each of the first plurality of memory units indexed by a character in the shift register to which the memory unit is coupled, the first plurality of memory units to store a dictionary of search terms; a second plurality of memory units arranged in groups, a number of groups of the second plurality of memory units corresponding to the maximum search term length, each group of the second plurality of memory units having a number of memory units corresponding to the maximum dictionary size, each of the second plurality of memory units coupled to one of the shift registers except for the first shift register, each of the second plurality of memory units to be indexed by the character in the shift register to which the memory unit is coupled, the second plurality of memory units to store the dictionary of search terms; a first plurality of AND gates corresponding to the maximum search term length, each of the first plurality of AND gates coupled to receive input from one of each of the groups of the first plurality of memory units; a second plurality of AND gates corresponding to the maximum search term length, each of the second plurality of AND gates coupled to receive input from one of each of the groups of the second plurality of memory units; and an OR gate to receive input from each of the first and second plurality of AND gates, the OR gate to output a match data.