Patent ID: 8012796
Filing Date: 2011-09-06
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor package structure, comprising: providing a silicon substrate having a thickness t forming a pattern of conductive vias to a depth d below the first surface of silicon substrate, which is less than the thickness t forming a wiring layer on the first surface of the silicon substrate, wherein the wiring layer comprises a first pattern of electrical contacts and redistribution wiring that provides electrical connections between the first pattern of electrical contacts and the conductive vias; bonding a glass handler substrate to the wiring layer on the first surface of the silicon substrate; recessing the second surface of the silicon substrate to expose bottom portions of the blind conductive vias and reduce the thickness t forming an insulating layer on the recessed second surface of the silicon substrate with the bottom portions of the conductive vias exposed; forming electrical contacts on the exposed bottom portions of the conductive vias to provide a second pattern of electrical contacts; bonding the second pattern of electrical contacts to a third pattern of electrical contacts on a second package substrate layer; and removing the mechanical glass handler substrate, wherein forming a pattern of conductive vias in the first surface of the first silicon substrate comprises: