Patent ID: 6448606
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; shallow trench isolations having surface area profiles extending above the semiconductor substrate and disposed in the semiconductor substrate, the shallow trench isolations having planar top surfaces parallel to the semiconductor substrate, the surface area profiles are convex curves; a first dielectric layer disposed on the semiconductor substrate between the shallow trench isolations; a first conductive layer disposed over the first dielectric layer and between the insulator shallow trench isolations to form a floating gate, the first conductive layer having a planar top surface coplanar with the planar top surfaces of the shallow trench isolations and a conformal top surface conformal to the shallow trench isolations to extend below the planar top surfaces of the shallow trench isolations; a second dielectric layer disposed over the first conductive layer and in contact with the entire planar top surfaces of the shallow trench isolations, the second dielectric layer conformal to the first conductive layer; and a second conductive layer disposed over the second dielectric layer to form a control gate.