Patent ID: 6016273
Filing Date: 2000-01-18
Classification: G11C

Abstract:
A system comprising:an address bus;a data bus;a microprocessor coupled to the address and the data bus; anda nonvolatile memory device coupled to the address and the data bus, wherein the memory device is formed on a semiconductor chip which is separate from the microprocessor,wherein the memory device includes:a plurality of storage MOSFETs storing information as threshold voltages, the threshold voltages of the plurality of storage MOSFETs being changed from a first range toward a second range by erase operations;a control circuit which performs a first control operation to execute the erase operations and to execute a verify operation for verifying whether or not the threshold voltages of the storage MOSFETs are in the second range after the erase operations,wherein the control circuit performs a second control operation to execute the erase operations again to the storage MOSFETs if it is detected, in the verify operation, that the threshold voltages of the storage MOSFETs are not in the second range, andwherein the first and second control operations are carried out by the control circuit without further control of the control circuit by the microprocessor; andan output circuit which outputs information relating to a result of the verify operations in response to a signal from the microprocessor.