Patent ID: 6026033
Filing Date: 2000-02-15
Classification: G05F

Abstract:
A method for generating a voltage on an output node in a memory device, the voltage being generated in response to first and second bias voltages developed on first and second bias nodes, respectively, by two diode-coupled MOS transistors connected in series between the first and second bias nodes, one diode-coupled transistor receiving its back-bias voltage from the first bias node and the other diode-coupled transistor having its source coupled to the second bias node, the method comprising the steps of:applying a supply voltage to the memory device;driving the first bias voltage on the first bias node toward the supply voltage when the output voltage drops below a desired value;driving the output voltage toward the supply voltage in response to the first bias voltage;driving the second bias voltage on the second bias node toward a reference voltage when the output voltage rises above the desired value; anddriving the output voltage toward the reference voltage in response to the second bias voltage.