Patent ID: 6066879
Filing Date: 2000-05-23
Classification: H01L

Abstract:
An electrostatic discharge (ESD) protection device as part of high voltage n-channel metal oxide semiconductor (NMOS) transistors and protecting same, comprising:a semiconductor wafer with a p-substrate;a first n-well formed in said p-substrate;a first and a second n.sup.+ diffusion implanted in said first n-well;a first p.sup.+ diffusion implanted in said first n-well;a third n.sup.+ diffusion implanted in said p-substrate;a second p.sup.+ diffusion implanted in said p-substrate;said first and said second n.sup.+ diffusion, and said first p.sup.+ diffusion connected to a voltage supply;said third n.sup.+ diffusion and said second p.sup.+ diffusion connected to a reference potential;a first gate formed between said first n-well and said third n.sup.+ diffusion, said first gate, said first n-well, and said third n.sup.+ diffusion representing a gate, a source, and a drain of an NMOS transistor, respectively;a parasitic silicon controlled rectifier (SCR), further comprising:a parasitic pnp bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector of said parasitic pnp bipolar transistor formed by said first p.sup.+ diffusion, said first n-well, and said p-substrate, respectively; anda parasitic npn bipolar transistor, having an emitter, a base, and a collector, said emitter, said base, and said collector of said parasitic npn bipolar transistor formed by said third n.sup.+ diffusion, said p-substrate, and said first n-well, respectively.