Patent ID: 6092227
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A test circuit comprising:a memory device;data writing means for outputting m-bit data immediately after the m-bit data is captured from an input/output terminal of said data writing means in response to a clock signal, branching the m-bit data to n identical m-bit signals, and writing the n m-bit data signals into said memory device;function determining means for reading the n m-bit data signals written into said memory device, outputting one of the n m-bit data signals read from said memory device, comparing the one m-bit data signal read from said memory device to an m-bit expected value, and determining coincidence or non-coincidence between the one m-bit data signal read from said memory device and the m-bit expected value; anda wide data bus connected to said data writing means, said memory device, and said function determining means for transferring the n m-bit data signals between said data writing means, said memory device, and said function determining means.