Patent ID: 7411810
Filing Date: 2008-08-12
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: memory cell, wherein includes a diode as an access device and a capacitor as a storage device; and the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line; and the capacitor includes two plates, wherein one plate of the capacitor serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line; and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read; memory cell array, wherein includes decoders, data latches, main memory cells and dummy memory cells; and main memory cells configure main columns, dummy memory cells configure dummy column(s), dummy column(s) generates delayed signal based on the dummy cells to enable the main columns in order to start latching the stored data from the memory cell; and data latch, wherein includes current mirror and latch circuit, the current mirror is connected to the diode through the bit line, and the latch circuit is connected to the current mirror, and the latch circuit cuts off the current path of the bit line after latching data from the memory cell, when read.