Patent ID: 8343814
Filing Date: 2013-01-01
Classification: G11C,H01L

Abstract:
1. A method of forming a multi-ported CAM cell comprising: providing a first structure including at least a first active semiconductor layer and a first interconnect structure, wherein a first plurality of field effect transistors (FETs) is present in said first active semiconductor layer, and said first interconnect structure includes a first dielectric material and first conductive filled openings embedded therein and extending to said first plurality of field effect transistors; bringing a handling substrate into direct contact with an uppermost surface of said first structure; providing a second structure including at least a second active semiconductor layer and a second interconnect structure, wherein a second plurality of FETs is present on said second active semiconductor layer, and said second interconnect structure includes a second dielectric material and second conductive filled openings embedded therein and extending to said second plurality of field effect transistors, wherein one of said first plurality of FETs and said second plurality of FETs includes a storage element comprising a first set of complementary metal oxide semiconductor (CMOS) transistors, and the other of said first plurality of FETs and said second plurality of FETs includes a compare element comprising a second set of CMOS transistors; bringing a bottom surface of said first structure into contact with an uppermost surface of said second structure; forming a bonded structure, wherein said bonded structure includes at least said first structure and said second structure, and said first structure is bonded with said second structure within said bonded structure; removing said handling substrate from said bonded structure; and forming conductive filled vertical via holes that connect said first set of CMOS transistors to said second set of CMOS transistors to form multi-ported Content Addressable Memory (CAM) cells in which said storage element overlies or underlies said compare element, wherein said bonded structure includes at least another additional structure bonded to said second structure, wherein each of said at least another additional structure includes at least an additional active semiconductor layer and an additional interconnect structure, wherein another plurality of FETs is present on said additional active semiconductor layer.