Patent ID: 6065134
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A method for performing on-chip diagnosis and repairing of a configurable ASIC memory array, having a plurality of memory row lines intersecting a plurality of memory I/O lines, with a built-in self test circuit and with redundant memory row and I/O lines, the method comprising:testing with the built-in self test circuit the memory cells at the intersections of memory row lines and memory I/O lines to determine the number of defective cells in each memory row or I/O line;determining that a repair of the ASIC memory array is mandatory for a number of defective memory cells along any memory row line exceeding a first threshold;determining that a repair of the ASIC memory array is mandatory for a number of defective memory cells along any memory I/O line exceeding a second threshold;repairing the ASIC memory array by selectively repairing a single memory row line in response to the determination that the number of defective cells along the memory row line exceeds the first threshold; andrepairing the ASIC memory array by selectively repairing a single memory I/O line in response to the determination that the number of defective cells along the memory I/O line exceeds the second threshold.