Patent ID: 6320437
Filing Date: 2001-11-20
Classification: H03K

Abstract:
A duty cycle regulator for deriving through iterative feedback an output clock signal having a pre-selected duty cycle from an input clock signal having an input clock period and an associated arbitrary duty cycle, said duty cycle regulator comprising:a) a clock pulse generator means for receiving said input clock signal, said clock pulse generator means including means for deriving from said input clock signal a first clock signal followed by a second clock signal delayed from said first clock signal, said clock pulse generator means providing an input clock pulse through an output port when said first clock signal has a same predetermined value as said second clock signal;b) bistable means having an output clock port for providing said output clock signal, and further having a first bistable input port, coupled to said output port of said clock pulse generator means, for setting the bistable means to a first state in response to said input clock pulse and a second bistable input port for switching said bistable means to a second state in response to a delayed pulse; andc) delay means having an input port coupled to said output clock port for generating said delayed pulse after the bistable means is set to the first state, said delayed pulse having a duration of a pre-selected fraction of the input clock period, and said pre-selected fraction of the input clock period being adjustable and independent of an input clock frequency.