Patent ID: 6278319
Filing Date: 2001-08-21
Classification: H03K

Abstract:
An input-buffering device, comprising:a first PMOS transistor, wherein a source terminal of the first PMOS transistor is connected to a high voltage and a gate terminal of the first PMOS transistor is connected to a first input signal terminal;a second PMOS transistor, wherein a source terminal of the second transistor is connected to a drain terminal of the first PMOS transistor and a gate terminal of the second transistor is connected to a second input signal terminal;a first NMOS transistor, wherein a drain terminal of the first NMOS transistor is connected to a drain terminal of the second PMOS transistor, a gate terminal of the first NMOS transistor is connected to the second input signal terminal, and a source terminal of the first NMOS transistor is connected to a low voltage;a second NMOS transistor, wherein a drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor, a gate terminal of the second NMOS transistor is connected to the first input signal terminal and a source terminal of the second NMOS transistor is connected to the low voltage;a first inverter, wherein an input terminal of the first inverter is connected to the drain terminal of the second PMOS transistor;a second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the first inverter and an output terminal of the second inverter is connected to the drain terminal of the second PMOS transistor;a third inverter, wherein an input terminal of the third inverter is connected to the output terminal of the first inverter and an output terminal of the third inverter is connected to a first output signal terminal;a fourth inverter, wherein an input terminal of the fourth inverter is connected to the output terminal of the first inverter;a fifth inverter, wherein an input terminal of the fifth inverter is connected to an output terminal of the fourth inverter and an output terminal of the fifth inverter is connected to a second output signal terminal;at least one transistor group, wherein each transistor group includes a first control NMOS transistor and a second control NMOS transistor, wherein a drain terminal of the first control NMOS transistor is connected to the drain terminal of the second PMOS transistor, a gate terminal of the first control NMOS transistor is connected to the second input signal terminal, a drain terminal of the second control NMOS transistor is connected to the source terminal of the first control NMOS transistor, and a source terminal of the second control NMOS transistor is connected to the low voltage; andan adjustable voltage divider circuit for generating a bias voltage signal to a gate terminal of the second control NMOS transistor.