Patent ID: 6377075
Filing Date: 2002-04-23
Classification: H01L,H03K

Abstract:
In an electrical circuit fabricated using a sub-micron CMOS process of the type incorporating a first at least one CMOS transistor having a gate connected to a node taking a range of voltages and susceptible to hot carrier degradation and gate-oxide dielectric breakdown when operated at a first voltage level, the improvement comprising; connected between said gate and said node a second transistor biased at a voltage less than said first voltage level in an arrangement reducing the maximum voltage across the gate of said first transistor during operation of said circuit thereby avoiding said gate-oxide dielectric breakdown when operated at said first voltage level:wherein a source terminal of said second transistor is connected to the gate of said first transistor; and wherein a resistor is connected between the gate and source of said second transistor said resistor being of a value selected to prevent node drift due to leakage current of said second transistor.