Patent ID: 6134173
Filing Date: 2000-10-17
Classification: G01R,G11C,H03K

Abstract:
A programmable logic array integrated circuit comprising:a two dimensional array of Logic Array Blocks (""LABs""), each comprising:a memory block having a plurality of memory columns, each of said memory columns having a plurality of data inputs, a plurality of address inputs, and at least one data output;control means coupled to said memory columns;first interface means having a plurality of inputs coupled to said control means, a plurality of data inputs, and a plurality of outputs coupled to said data inputs of said memory columns;second interface means having a plurality of inputs coupled to said control means and a plurality of outputs coupled to said address inputs of said memory columns;third interface means having a plurality of inputs coupled to said data output of said plurality of memory columns, a plurality of inputs coupled to said control means, and a plurality of outputs;an intra-LAB plurality of conductors being programmably coupled to said control means;a plurality of first programmable selectors (""PLCs"") coupled between said intra-LAB plurality of conductors and said control means for selectively connecting said intra-LAB conductors to said control means; anda plurality of first function control elements (""FCEs"") coupled to said plurality of first PLCs for programmably controlling said first plurality of PLCs;a first plurality of conductors, each of which extends along a first dimension of said two dimensional array;a second plurality of conductors, each of which extends along a second dimension of said two dimensional array;a plurality of second PLCs coupled between said intra-LAB conductors and said first conductors for connecting a selected number of said first plurality of conductors to said intra-LAB plurality of conductors;a plurality of second function control elements (""FCEs"") coupled to said plurality of second PLCs for programmably controlling said plurality of second PLCs; anda plurality of output buffers coupled between said outputs of said third interface and said second conductors, each of said output buffers having a control input.