Patent ID: 9093986
Filing Date: 2015-07-28
Classification: H02J,H02M,H03K,H03L

Abstract:
1. A method of synchronizing a PWM device to a synchronization (sync) signal, the PWM device generating a primary PWM output signal from a clock circuit, the method comprising: determining when a frequency of the primary PWM output of the PWM device is within a predetermined error margin of a frequency of the sync signal; upon making such a determination, adjusting a clock circuit of the PWM device to force the frequency of the primary PWM output of the PWM device to match the frequency of the sync signal, and upon reaching this condition, aligning a phase of the primary PWM output of the PWM device with respect to a phase of the sync signal such that there is a phase offset between the sync signal and the primary PWM output, wherein the step of determining when the frequency of the primary PWM output of the PWM device is within a predetermined frequency error margin of the sync signal comprises: counting a number of sync pulses received within a period defined by a predetermined count of primary PWM pulses of slave devices; and determining if the count of sync pulses is within a predetermined count margin of the predetermined count.