Patent ID: 8351271
Filing Date: 2013-01-08
Classification: G11C

Abstract:
1. A semiconductor storage apparatus comprising: an output terminal; a pool capacitor connected between the output terminal and ground; a first voltage divider circuit connected between the output terminal and the ground to output a first monitor voltage obtained by dividing a voltage which is output from the output terminal with a first voltage division ratio; a first switch circuit connected between the output terminal and the first voltage divider circuit; a second switch circuit connected between the first voltage divider circuit and the ground; a third switch circuit connected between a first potential which is higher than a reference voltage and the first voltage divider circuit; a first amplifier circuit which compares the first monitor voltage with the reference voltage, outputs a first boost signal if the first monitor voltage is lower than the reference voltage, and outputs a first stop signal if the first monitor voltage is higher than the reference voltage; a first pump circuit which outputs a voltage obtained by boosting a power supply voltage to the output terminal in response to the first boost signal; a second voltage divider circuit connected between the output terminal and the ground to output a second monitor voltage obtained by dividing a voltage which is output from the output terminal with a second voltage division ratio, the second voltage division ratio being equal to the first voltage division ratio, the second voltage divider circuit being greater in resistance value than the first voltage divider circuit; a fourth switch circuit connected between the output terminal and the second voltage divider circuit; a fifth switch circuit connected between the second voltage divider circuit and the ground; a sixth switch circuit connected between the first potential which is higher than the reference voltage and the second voltage divider circuit; a second amplifier circuit which compares the second monitor voltage with the reference voltage, outputs a second boost signal if the second monitor voltage is lower than the reference voltage, and outputs a second stop signal if the second monitor voltage is higher than the reference voltage; a second pump circuit which outputs a voltage obtained by boosting the power supply voltage to the output terminal in response to the second boost signal, the second pump circuit being lower in boosting capability than the first pump circuit; a control circuit which controls activation/deactivation of the first amplifier circuit and the second amplifier circuit, and controls on/off of the first to sixth switch circuits; a memory cell which stores data; and a decoder which supplies a voltage depending upon the boost voltage output from the output terminal, to the memory cell, wherein the control circuit deactivates the first and second amplifier circuits, turns off the first, second, fourth and fifth switch circuits, and turns on the third and sixth switch circuits in response to an external signal based on reduction of current dissipation of a power supply which supplies the power supply voltage.