Patent ID: 8513061
Filing Date: 2013-08-20
Classification: H01L

Abstract:
1. A method for manufacturing a through silicon via (TSV), comprising: preparing a substrate having a metal thin film formed in a predetermined region of the substrate; preparing a semiconductor die (or semiconductor chip) having an insulation layer formed on a side of the semiconductor die (or semiconductor chip) formed with a via hole and formed with a through via hole by back grinding the other side of the semiconductor die (or semiconductor chip); aligning the substrate formed with the metal thin film and the semiconductor die (or semiconductor chip) formed with the insulation layer; forming a seed layer on one side including the via hole of the aligned semiconductor die (or semiconductor chip) wherein the seed layer is in direct contact with the metal thin film; and forming an electroplating layer on a top portion of the seed layer by using electroplating, including the inside of the via hole, wherein the preparing of the semiconductor die (or semiconductor chip) includes first surface treatment of a bonding surface of the semiconductor die (or semiconductor chip) formed with the through via hole such that the bonding surface of the semiconductor die (or semiconductor chip) has a hydrophilic surface, wherein the preparing of the substrate includes second surface treatment of a bonding surface of the substrate, and wherein the aligning includes spraying moisture or applying water drop to at least the bonding surface of the semiconductor die (or semiconductor chip) or the bonding surface of the substrate to form a wetting layer between the semiconductor die (or semiconductor chip) and the substrate, and then contacting the semiconductor die (or semiconductor chip) to the substrate to be self-aligned.