Patent ID: 7180348
Filing Date: 2007-02-20
Classification: G06F,H03K,Y02D

Abstract:
1. A circuit for storing a signal value, said circuit comprising: a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal; at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one storage latch said at least one storage latch being at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one storage latch in response to a predetermined clock signal value; wherein power supply to said circuit is arranged such that in response to a sleep signal: a voltage difference across at least a portion of said circuit is reduced such that said portion of said circuit is powered down; a voltage difference across said at least one storage latch is maintained; and a clock signal received by said tristateable device is held at said predetermined value such that said input of said storage latch is isolated.