Patent ID: 6392943
Filing Date: 2002-05-21
Classification: G11C

Abstract:
A method of reading an integrated circuit memory comprising at least one memory cell to be read, at least one reference memory cell, a data bit line connected to the at least one memory cell and a reference bit line connected to the at least one reference memory cell, the method comprising:applying a data signal to a data input of a differential amplifier, and applying a reference signal to a reference input of the differential amplifier; providing a reference current to the reference bit line and a fraction of the reference current to the data bit line using a read current generator connected to the differential amplifier; and performing an asymmetrical precharging for causing the data signal being received at the data input of the differential amplifier to be at a level higher than the reference signal being received at the reference input of the differential amplifier for switching an output signal of the differential amplifier to a corresponding logic state.