Patent ID: 7838968
Filing Date: 2010-11-23
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: a substrate having an insulating surface; a thin film transistor formed on the insulating surface, the thin film transistor comprising a semiconductor layer and a gate electrode with a gate insulating film interposed therebetween; a scanning line over the substrate; a first interlayer insulating film comprising silicon nitride formed over the thin film transistor and the scanning line; a source electrode formed over the first interlayer insulating film and electrically connected to the semiconductor film; a second interlayer insulating film comprising silicon nitride formed over the first interlayer insulating film and the source electrode; a pixel electrode formed over the second interlayer insulating film and electrically connected to the semiconductor film; and a third interlayer insulating film on and in contact with the second interlayer insulating film and the pixel electrode, wherein each of the first and second interlayer insulating films has an internal stress oriented in compressive direction and a variation of the internal stress in each of the first and second interlayer insulating films is within a range of ±50%.