Patent ID: 6593642
Filing Date: 2003-07-15
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a potential transmission line for transmitting an internal potential; a plurality of load capacitors dispersed along said potential transmission line, and each configured to receive said internal potential from said potential transmission line; a charge pump circuit for supplying charges to one end of said potential transmission line in synchronization with a clock signal; a potential detecting circuit for determining whether said internal potential at a predetermined position on said potential transmission line has reached a reference potential or not, setting an activation signal to a first level if reached, and setting the activation signal to a second level if not reached; a filter circuit for removing a pulse-like change in level from said activation signal; and a clock generating circuit being activated to issue said clock signal to said charge pump circuit when the activation signal processed by said filter circuit is at said second level.