Patent ID: 7864288
Filing Date: 2011-01-04
Classification: G02F

Abstract:
1. A manufacturing method of a LCD array substrate, comprising: forming a patterned first metal layer on a substrate to form at least a first conductive line, at least two second conductive lines and at least a gate electrode, wherein the first conductive line has at least a crossing region and electrically connects with the gate electrode, the second conductive lines are located separately at two sides of the crossing region of the first conductive line, and the first conductive line and the second conductive lines define a plurality of pixel areas; sequentially forming and patterning a dielectric layer and a semiconducting layer to cover the second conductive lines, the crossing region and the gate electrode, wherein the dielectric layer and the semiconducting layer on the second conductive lines have a first opening to expose the second conductive lines, the semiconducting layer above the gate electrode is used as a channel layer, and the dielectric layer is not disposed on the pixel areas; forming a patterned second metal layer over the substrate to separately form at least two third conductive lines, at least a fourth conductive line, at least a source electrode and at least a drain electrode, wherein the third conductive lines cover the first conductive line at two sides of the crossing region to form a scan line, the fourth conductive line covers the semiconducting layer on the second conductive lines and the crossing region to form a data line, the source electrode and the drain electrode are located at two sides of the channel layer to form at least a transistor, the third conductive lines don't connect with the fourth conductive line; forming a patterned passivation layer to cover the transistor, the scan line and the data line; and forming at least a pixel electrode over the substrate, wherein the pixel electrode electrically connects with the transistor.