Patent ID: 8902644
Filing Date: 2014-12-02
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a plurality of memory cells arranged in a row direction and in a column direction being orthogonal to the row direction; a first word line extending in the column direction; and a second word line extending in the column direction, wherein each of the plurality of memory cells comprises: a magnetoresistive element having a first lower terminal and a second lower terminal which are respectively connected to both ends of a conductive layer whose longitudinal direction is different from the column direction; a first transistor whose drain is connected to the first lower terminal and whose gate is connected to the first word line; and a second transistor whose drain is connected to the second lower terminal and whose gate is connected to the second word line, wherein the gate of the first transistor of each of at least two memory cells among the plurality of memory cells and which are adjacent to each other in the column direction is commonly connected to the first word line.