Patent ID: 7615845
Filing Date: 2009-11-10
Classification: B81B,H01L

Abstract:
1. An apparatus for reducing parasitic capacitance in a conductor in a micro-electro mechanical system (MEMS) device, the apparatus comprising: a silicon-on-insulator (SOI) substrate having a buried oxide layer; a dielectric layer formed on the surface of the SOI substrate; a conductor embedded in the SOI substrate and disposed between the dielectric layer and the buried oxide layer, the embedded conductor having a first end and a second end; one or more surface conductors deposited on top of the dielectric layer and in contact with the first end and second end of the embedded conductor, respectively; a boundary region surrounding the embedded conductor and separating an inner region and an outer region of the SOI substrate, the boundary extending through the SOI substrate to the buried oxide layer and providing a p-n junction between the boundary region and the outer region of the SOI substrate, which is reverse biased to electrically isolate the inner region from the outer region of SOI substrate; and an amplifier having an input connected to the first end of the embedded conductor and an output connected to the inner region of the SOI substrate, the amplifier configured to sense a voltage at the input and to reproduce a voltage approximately equal to the voltage at the output.