Patent ID: 6360353
Filing Date: 2002-03-19
Classification: G01R

Abstract:
A computer implemented method for testing alternating current characteristics of a computer model of an integrated circuit design, comprising:(a) supplying an AVF file and a Device Under Test (DUT) file of the integrated circuit design; (b) generating a test file containing data of a parameter of the integrated circuit design, wherein the parameter includes a setup and hold parameter, a pulse width parameter, and an out-to-out parameter; (c) parsing through a chip file of the integrated circuit design in order to extract netlist information, external signal names, bus definitions, and pull-up information; (d) parsing through the DUT file to extract input/output information, channel number information, and timing information; (e) splitting data of the AVF file into input vector data and output vector data; (f) generating an environment file that assists in simulating a physical test station; (g) running the environment file through Verilog using the input vector data and the output vector data in order to generate a log that indicates alternating current test results for the parameter data; (h) providing a report file, the DUT file, and the test file to the physical test station in order to generate physical test station data; (i) comparing the generated physical test station data with the report file that contains test data from testing the computer model of the integrated circuit design; and (j) determining inconsistencies between the generated physical test station data and the report file.