Patent ID: 6529555
Filing Date: 2003-03-04
Classification: H04N

Abstract:
A signal processor for splicing a compressed video bitstream A0 to a compressed video bitstream B0 to form at compressed bitstream C, the bitstreams A0, B0 and C having GOPs including I frames and P and/or B frames, the processing comprisingfirst and second inputs (A0, B0) for receiving the bitstreams A0 and B0 respectively, first means (1, 8; 3, 10) for re-encoding the GOPs of the bitstreams A0 and B0, re-encoded bitstreams AI and BI respectively having GOPs including only I frames, the transcoding parameters of the frames of the bitstreams A0 and B0 being retained unchanged in association with the corresponding I frames of the bitstreams AI and BI, means (141, 142, 51, 12) for splicing bitstream BI, to bitstream AI at a splice point (SPLICE), to produce a spliced I-frame bitstream, ( AI/BI) second means (14) for re-encoding the spliced I-frame bitstream ( AI/BI) as the compressed bitstream for supply to a downstream decoder (2) having a downstream buffer wherein the value of occupancy of the downstream buffer by the bitstream C is controlled over a transition region having a transitional GOP including the splice point (SPLICE) so that the said value of occupancy changes over the duration of the transition region from that of stream A0 to that of stream B0, and wherein the frames of the bitstream AI before the transition region are re-encoded re-using the transcoding parameters of the corresponding frames of the bitstream A0, and the frames of the bitstream BI after the transition region are re-encoded re-using the transcoding parameters of the corresponding frames of the bitstreams B0.