Patent ID: 6054734
Filing Date: 2000-04-25
Classification: H01L

Abstract:
A non-volatile semiconductor memory device with reduced read disturb comprising:a semiconductor layer having a first surface and a second surface;a first insulating layer formed on said first surface and a second insulating layer formed on said second surface; anda first gate electrode formed on said first insulating layer and a second gate electrode formed on said second insulating layer;a charge storing means located in said first insulating layer; anda channel region formed in said semiconductor layer between said first gate electrode and said second gate electrode;wherein a thickness of said semiconductor layer at said channel region is such that a first electric field of said first surface of said semiconductor layer exerts an influence on a second electric field of said second surface of said semiconductor layer such that both a first gate threshold voltage measured with respect to said first gate electrode and a second gate threshold voltage measured with respect to said second gate electrode are changed by a charge stored in said charge storing means.