Patent ID: 7065103
Filing Date: 2006-06-20
Classification: H04J,H04L

Abstract:
1. A channel processor for aligning a respective first data stream with a second data stream, each data stream being conveyed within a respective parallel channel and having substantially equivalent bit and frame rates, the channel processor being connected to a respective channel for processing the respective first data stream, and comprising: a) a framer for detecting incoming frames of the first data stream, and generate a local strobe signal indicative of a timing of the incoming frames; b) a memory for buffering the first data stream; c) an interface adapted to receive a master strobe signal from a selected adjacent channel processor; d) a switch circuit for selecting one of the local and master strobe signals; and e) an output timer for controlling a position of a read pointer for reading the buffered first data stream based on the selected one of the local and master strobe signals.