Patent ID: 8046206
Filing Date: 2011-10-25
Classification: G06F

Abstract:
1. A method of defining a configuration of hardware resources, comprising: a) executing, in a processing device, a subgraph isomorphism process to discover multiple sets of available resources in a programmable hardware resource space of an integrated circuit, each discovered set of available resources comprising semiconductor features to perform transformation of inputs to outputs for implementing a particular user module function, and to discover multiple available target placements of the discovered sets of available resources in the hardware resource space, wherein said hardware resource space is defined by a target graph, and wherein said user module is defined by a subgraph; b) in response to a selection of one of said multiple sets of available resources to implement the particular user module function together with selection of one of said multiple available placements, establishing configuration settings relating to connections between individual resources in the selected set of resources according to the selected placement by annotating said target graph, said configuration settings based on said subgraph mapping to said target graph and annotating said target graph to describe a way in which said user module will share resources in said selected set of resources; c) in response to receiving parameters for implementing said user module function, specifying attributes and operating parameters for particular ones of the selected set of resources by annotating said target graph to generate an annotated target graph; and d) sequentially repeating said a) through said c) for additional user modules defined by additional subgraphs, to provide a configuration of said hardware resource space to implement an integrated circuit design by superposing said subgraph and said additional subgraphs on said target graph.