Patent ID: 7721275
Filing Date: 2010-05-18
Classification: G06F

Abstract:
1. An apparatus comprising: a platform including a processor and a memory; a dynamic compiler to execute on the platform, and based on a byte code input, to generate an internal representation, and emit a first compiled machine code to the memory for execution by the processor; and a post pass processor (PPP) to obtain the first compiled machine code and to obtain compile time information from the internal representation and, prior to the processor's execution of the first compiled machine code, perform an optimization on the first compiled machine code without interpreting the first compiled machine code, and to rewrite the first compiled machine code as an optimized compiled machine code to the memory for execution by the processor; wherein the PPP comprises: an abstraction engine to create a control flow graph of the first compiled machine code enriched with the compile time information; a data flow analysis engine to perform data flow analysis on the control flow graph, wherein the data flow analysis comprises iteratively traversing nodes of the control flow graph and at each node, updating information about the data arriving at a control transfer associated with the each node traversed, and evaluating a relationship between a generated set, an incoming set and a killed set until incoming and outgoing sets do not change; and an optimization engine to remove redundant instructions from the first compiled machine code based on the data flow analysis performed on the control flow graph.