Patent ID: 7032207
Filing Date: 2006-04-18
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit, comprising: checking each border edge of a block area so as to determine whether a border edge is a first border edge where an external connection terminal is provided or a second border edge where no external connection terminal is provided; providing a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists; providing a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge; determining a layout of the block area through floor planning, placement and routing; extracting resistance and capacitance from the layout, for delay calculation and layout check, by utilizing the wiring prohibited area for the first border edge and the shielding line for the second border edge; and completing a layout of the block area through the delay calculation and layout check.