Patent ID: 8639874
Filing Date: 2014-01-28
Classification: G11C

Abstract:
1. A computer memory comprising: a DIMM (Dual Inline Memory Module) a plurality of DRAM (Dynamic Random Access Memory) chips mounted on the DIMM, the plurality of DRAM chips comprising a rank of memory including a spare DRAM in the rank of memory, each of the plurality of DRAM chips configured to be powered up or placed into a low power state via commands sent on one or more data signals (DQ signals) unique to the each of the plurality of DRAM chips comprising the rank of memory; each of the plurality of DRAM chips mounted on the DIMM comprises a command decoder to control clocking of signals on the one or more DQ signals, and a decoder to decode the DQ signals when clocked to the decoder, a first decoder output to place the DRAM in a low power state and a second decoder output to place the DRAM in a powered up state; and wherein the spare DRAM is placed in the low power state until a particular chip in the rank of memory fails, upon which the spare DRAM is placed in the powered up state and the particular chip in the rank of memory that failed is placed into the low power state.