Patent ID: 6876566
Filing Date: 2005-04-05
Classification: G11C

Abstract:
1. A differential non-volatile memory device comprising: at least first and second OTP memory cells that are each coupled between a supply voltage and a reference voltage, the first and second memory cells being programmed to store a bit and its complementary bit; a read circuit forming a first current path between the first memory cell and the reference voltage and a second current path between the second memory cell and the reference voltage for reading the bit and the complementary bit that are stored in the first and second memory cells, the first current path including a first circuit point that is associated with a first output terminal, and the second current path including a second circuit point that is associated with a second output terminal; and setting means that can be activated to bring the first and second circuit points to a voltage value that is substantially equal to the reference voltage, the setting means being able to set the value of the current flowing through each of the first and second current paths.