Patent ID: 6798244
Filing Date: 2004-09-28
Classification: H03K

Abstract:
A buffer comprising:an output signal node for receiving a data signal to be provided to an external circuit; an output pad for connecting to the external circuit; a driver transistor having a source-drain path connecting a first power supply terminal to the output pad, and having a gate; switching transistors connected to the output signal node and the gate of the driver transistor to provide a signal to the gate of the driver transistor based on a state of the data signal; and a connecting means which is connected to the first power supply terminal, a second power supply terminal, and the output pad, the connecting means for connecting the output pad to the second power supply terminal when a voltage on the output pad exceeds a voltage on the first power supply terminal, wherein the connecting means comprises:an overvoltage resistor having a first terminal connected to the pad, and having a second terminal; and a pass gate transistor having a first terminal coupled to the second terminal of the overvoltage resistor, a second terminal coupled to a second power supply terminal, and having a gate connected to the first power supply terminal.