Patent ID: 7125779
Filing Date: 2006-10-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming an etching mask comprising a first insulating film having an opening portion including a gate forming portion and source/drain extension regions forming portion on a surface of a semiconductor substrate; forming a trench in the semiconductor substrate corresponding with the opening portion; forming a gate insulating film comprising a second insulating film on an inner surface of the trench; forming a third insulating film to cover a surface of the semiconductor substrate; forming sidewall spacers comprising the third insulating film using anisotropic etching on side surfaces of the opening portion on source/drain sides respectively; forming a gate material film to cover the surface of the semiconductor substrate; etching-back the upper surfaces of the third insulating film and the gate material film to form a gate comprising the gate material film buried between the sidewall spacers on a central portion between both sides of the opening portion on the source/drain side; selectively removing the first and third insulating films to form a MIS-type field effect transistor having a self-aligned gate formed on the central portion between both sides of the trench on the source/drain side, in which a position where an impurity concentration of highly-doped source/drain regions in the direction of depth is maximum substantially coincides with a position where an impurity concentration of the source/drain extension regions in the direction of depth is maximum; implanting impurity ions into at least a bottom surface of the trench using the gate as a mask to form source/drain extension regions; forming a fourth insulating film to cover the surface of the semiconductor substrate; forming gate sidewall spacers comprising the fourth insulating film using anisotropic etching to cover an inner surface of the trench extending on the source/drain side of the gate; and implanting impurity ions by using the gate having the gate sidewall spacers as a mask to form the highly-doped source/drain regions substantially adjacent to side surfaces of the trench and connected to the source/drain extension regions on the bottom surface of the trench.