Patent ID: 7734880
Filing Date: 2010-06-08
Classification: G11C

Abstract:
1. A memory system comprising: a flash memory having a memory cell array storing program data including a final data, the flash memory being configured to execute a first program operation on a selected wordline, and then execute a second program operation on an adjacent word line disposed directly adjacent to the selected word line; and a memory controller configured to determine whether all of the program data are stored in the flash memory by the first and second program operations, such that when it is determined that all of the program data are stored in the flash memory, the memory controller outputs a dummy program command and a dummy address, thereby causing the flash memory to execute a dummy program operation, wherein after executing the dummy program operation on a wordline identified by the dummy address, the flash memory is further configured to execute the second program operation on a final wordline corresponding to the final data of the program data.