Patent ID: 7583549
Filing Date: 2009-09-01
Classification: G11C

Abstract:
1. A method for outputting a data of a target memory cell from a memory, wherein the target memory cell corresponds to a target readout bit line and the target readout bit line is one of a plurality of the readout bit lines, comprising: pre-charging of the voltages of the readout bit lines to logic high level; selecting the target memory cell and outputting the voltage of the target memory cell to the target readout bit line; detecting the voltage of the target readout bit line; and comparing the voltage of the target readout bit line and a source voltage, which is logic high level, with a sense amplifier to generate a output signal and an inverse output signal on a first output node and a second output node, wherein the inverse output signal is inverted to the output signal; wherein the sense amplifier comprises: a first differential input transistor, having a gate connected to one of the readout bit lines for receiving the voltage of the target readout bit line, and a source connected to a node electrically conductive selectively coupled to the target readout bit line a second differential input transistor, having a gate connected to the source voltage with the logic high level, and a source connected to the node electrically conductive selectively coupled to the target readout bit line.