Patent ID: 8615634
Filing Date: 2013-12-24
Classification: G06F,Y02D

Abstract:
1. A method of data processing in a data processing system including a processor core, a multi-level cache memory hierarchy including a lowest level cache, a memory controller, and a system memory, wherein the lowest level cache includes a cache controller that controls read and write access to a cache array of the lowest level cache and updates a cache directory of the lowest level cache to maintain coherence, wherein the lowest level cache includes a virtual write queue into which the memory controller has visibility, and wherein the virtual write queue is formed of only a subset of a cache array of the lowest level cache, said method comprising: the memory controller controlling read and write access to the system memory, wherein the system memory forms a lowest level of storage addressable by a real address space of the processor core, wherein the memory controller includes a physical write queue from which the memory controller write data received from the lowest level cache to the system memory, and wherein the controlling includes: