Patent ID: 7466596
Filing Date: 2008-12-16
Classification: G11C

Abstract:
1. A memory circuit comprising: a first non-volatile memory transistor with a floating gate electrode and a gate terminal; and a second non-volatile memory transistor with a floating gate electrode and a gate terminal; a first switch connected between a drain terminal of the first memory transistor and a bit line for reading out information stored in the memory circuit; a second switch connected between a drain terminal of the second memory transistor and the bit line, wherein the first switch and the second switch are formed to selectively couple the drain terminal of the first memory transistor or the drain terminal of the second memory transistor to the bit line during readout; and a drive circuit formed to write write data into one of the memory transistors in write operation, wherein the drive circuit is formed to apply equal signals to the gate terminals of the first memory transistor and the second memory transistor based on the write data; to apply a programming signal at a source terminal of the memory transistor to be written to, which allows to change a state stored in the memory transistor to be written to; and to drive a source terminal of a memory transistor not to be written to such that a state stored in the memory transistor not to be written to is not changed.