Patent ID: 8522087
Filing Date: 2013-08-27
Classification: G04F,G06F,G11C,H03M,H04L

Abstract:
1. In a system in which a counter configuration operates in cooperation with a delay configuration such that the counter configuration counts based on a given clock signal characterized by a given clock speed and a given clock interval to provide a given data output resolution with respect to timing an input interval as limited by the given clock speed and the counter configuration counts responsive to a selected clock edge in each given clock interval, and said delay configuration is used to divide the given clock interval to provide a delay configuration output that produces an enhanced data output having an enhanced resolution, with respect to timing the input interval, that is greater than the data output resolution that is available based on the given clock speed, an apparatus comprising: a correction arrangement configured to (i) monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of said input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and (ii) determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.