Patent ID: 6902978
Filing Date: 2005-06-07
Classification: H01L

Abstract:
1. A method for manufacturing a split-gate flash EEPROM cell comprising the steps of: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon layer on the gate oxide layer; forming a silicon nitride layer on the polysilicon layer; forming a trench in the silicon nitride layer and exposing part of the upper surface of the polysilicon layer to define a suspending gate region; forming a first oxide layer in the trench; forming a common source plug between two of the adjacent suspending gate regions; performing etching to remove the silicon nitride layer and the polysilicon layer and the gate oxide layer not covered by the first oxide layer, forming a suspending gate structure; forming a substrate trench in the semiconductor substrate on one side of the suspending gate structure, the substrate trench being located opposite to the common source plug; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the substrate trench; forming a polysilicon spacer on the inter polysilicon dielectric sidewall as the selection gate; and forming a drain on the semiconductor substrate in the substrate trench, the drain being adjacent to the selection gate.