Patent ID: 7405150
Filing Date: 2008-07-29
Classification: H01L

Abstract:
1. A method for fabricating an IC chip comprising: providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and wherein said first and second interconnecting structures are formed by a damascene process comprising a dielectric etching process, an electroplating process and a CMP process, wherein said electroplating process is followed by said CMP process, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer; and forming a polymer layer and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is in said polymer layer, wherein said third interconnecting structure is connected to said first and second interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said third interconnecting structure is formed by a process comprising sputtering a thin base metal layer, followed by forming a patterned photoresist layer, followed by electroplating a thick metal layer, followed by removing said patterned photoresist layer, followed by etching said thin base metal layer.