Patent ID: 6064242
Filing Date: 2000-05-16
Classification: G01R

Abstract:
An I/O pin electronics circuit to be used in a semiconductor test system for testing semiconductor devices, comprising:a voltage generation circuit for generating first and second drive voltages and a termination voltage to be used for testing a semiconductor device under test (DUT):a wave formatter for generating a test pattern signal and a driver enable signal;a first driver for directly supplying a first drive signal to a first pin of the DUT through a first signal path, the first drive signal being produced by a first combination of the drive voltages and the test pattern signal;a second driver for directly supplying a second drive signal to a second pin of the DUT through a second signal path, the second drive signal being produced by a second combination of the drive voltages and the test pattern signal;a control circuit connected between the first and second drivers and the wave formatter for controlling the operation of the first and second drivers based on the driver enable signal from the wave formatter; anda comparator, a first input of which is connected to both an output of the second driver and the second signal path, and a second input of which is provided with a reference voltage, for comparing an output signal of the DUT from the second signal path with the reference voltage;wherein the first driver is disabled and the second driver is enabled by the driver enable signal in a first test mode while the second driver is disabled and the first driver is enabled by the driver enable signal in a second test mode.