Patent ID: 7200021
Filing Date: 2007-04-03
Classification: B82Y,G11C,H01L

Abstract:
1. A stacked DRAM Memory Chip for a Dual In Line Memory Module comprising: (a) a predetermined number of at least four stacked DRAM memory dies; (b) wherein the stacked DRAM memory dies are each selectable by a corresponding internal memory rank signal; (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of internal address lines is provided for addressing the memory cells and is connected to all stacked DRAM memory dies; (e) wherein internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: