Patent ID: 6255969
Filing Date: 2001-07-03
Classification: H03K

Abstract:
A high-speed bit stream capture circuit, comprising:a transmission interface unit for receiving an incoming bit stream and producing therefrom a high-speed bit stream;a digital delay line coupled to said transmission interface unit, including a plurality of digital delay elements coupled in series and a plurality of taps, each tap coupled to the output of a distinct digital delay element of said plurality of digital delay elements, for receiving and delaying the high-speed bit stream;a latch having a plurality of latch inputs, each latch input being coupled to a respective tap of said plurality of taps, and a latch control input for receiving a latch control signal for latching and outputting through a plurality of latch outputs parallel data at said plurality of latch inputs; anda counter for counting to a prescribed number of bit stream periods from the start of said bit stream and, when said prescribed number of bit stream periods is counted, generating said latch control signal.