Patent ID: 6579776
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:forming a memory cell including an array of gate interconnections on a main surface of a semiconductor substrate; forming an inter-layer insulating film over regions of said memory cell and a continuing peripheral region of said regions; providing dummy pad contact holes, each at a gap between said gate interconnection and a bit line, in a dotted line along an end portion of said memory cell; forming a plug in each of said dummy pad contact holes; providing means for interrupting an electric conduction between one of said plugs in said dummy pad contact holes and said bit line in a path leading from said plug through an active region in said substrate, a pad contact and a bit line contact to said bit line; and polishing to planarize said inter-layer insulating film at the region of the memory cell including said dummy pad contact holes and the continuing peripheral region.