Patent ID: 7015725
Filing Date: 2006-03-21
Classification: H03L,Y10S

Abstract:
1. A delay-locked loop device capable of anti-false-locking, comprising: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupling to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupling to the phase detector for generating the control voltage to the voltage control delay circuit according to the control signal; a lock detector coupling to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of each delay unit of the voltage control delay circuit, comprising: a first shift register set comprising a plurality of shift registers each corresponding to a delay unit of the voltage control delay circuit for generating a first sequence of comparison signals according to a first divided phase and the output phases of each delay unit of the voltage control delay circuit; a second shift register set comprising a plurality of shift registers each corresponding to a shift register of the first shift register set for generating a second sequence of comparison signals according to a second divided phase and the first sequence of the comparison signals; and a logic module coupling to the second shift register set for generating the lock indication signal according to the second sequence of the comparison signals.