Patent ID: 6458639
Filing Date: 2002-10-01
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor device, comprising:providing a semiconductor substrate having a source region and a drain region therein, said source and drain regions respectively comprising source and drain extensions and being separated by a substantially undoped channel region; and forming at least one field effect transistor (FET), said FET forming step comprising the substeps of: forming a lower gate insulator layer on said substrate over said extensions and said channel region; forming an upper gate insulator layer on said lower gate insulator layer; forming a gate on said lower gate insulator layer disposed over said channel region and on said upper gate insulator layer, said lower gate insulator layer being disposed between said extensions and said gate, said upper gate insulator layer being disposed between said extensions and said gate, and sandwiched between the upper gate insulator layer and the gate, whereby only a single layer on the gate insulator layers is disposed between the gate and the channel region, said lower gate insulator layer including at least one nitride, and said upper gate insulator layer including at least one oxide.