Patent ID: 6174815
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A method for planarizing semiconductor devices, comprising the steps of:providing a silicon substrate having a surface topography;forming a stacked layer free of conductive material, including:forming a dielectric layer over the substrate, and etching back portions of the first dielectric layer to form a spacer layer;forming a second dielectric layer having an upper surface and a lower surface opposite the upper surface, the lower surface being formed only directly on the conformal spacer layer; andforming an insulating layer having an upper surface and a lower surface opposite the upper surface, the lower surface being formed only directly on the upper surface of the second dielectric layer; andfully etching back the insulating layer, and etching back portions of the second dielectric layer to form a planar surface, with the insulating layer having an etching rate greater than the etching rate of the second dielectric layer.