Patent ID: 6251719
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A process of creating a second layer of poly-2 overlying a first layer of poly-1, said layer of poly-1 serving as a gate electrode structure having sidewalls, said second layer of poly-2 serving as a layer of overlying poly-2 for said gate electrode structure, comprising the steps of:providing a semiconductor substrate;depositing a layer of ONO over the surface of the semiconductor substrate, said layer of ONO comprising a lower layer of oxide over which a layer of nitride over which an upper layer of oxide;depositing a layer of poly-1 over the surface of said layer of ONO;depositing a layer of TEOS-1 over the surface of said layer of poly-1;patterning said layer of TEOS-1 as a hard mask for the underlying layer of poly-1;etching said layer of poly-1 using said hard mask as an etch mask, creating a pattern of gate electrodes, partially exposing the surface of said substrate;depositing a layer of silicon nitride over said gate electrodes, including said partially exposed surface of said substrate;depositing a layer of TEOS-2 over the surface of said layer of silicon nitride;forming said layer of TEOS-2 as gate spacers on sidewalls of said gate electrodes;removing said silicon nitride layer from above said gate electrodes and from between said gate spacers;removing said upper layer of oxide of said layer of ONO from in between said gate spacers, partially exposing the surface of said layer of nitride contained within said layer of ONO;depositing a layer of protective oxide over said gate electrodes, said gate spacers and said partially exposed surface of said layer of nitride contained within said layer of ONO; anddepositing a layer of poly-2 over the surface of said protective oxide.