Patent ID: 6493863
Filing Date: 2002-12-10
Classification: G06F

Abstract:
A method of designing a semiconductor integrated circuit device, the method comprising the steps of:(a) inputting an application program including a behavioral description for designing the semiconductor integrated circuit device, partitioning, on a function-by-function basis, the application program including the behavioral description into blocks in which HW resources are to be placed, and generating an HW resource connection graph representing respective positions of the HW resources in each of the blocks and wires connecting the individual blocks; (b) inputting at least data on respective sizes of the HW resources from an HW library, provisionally placing the HW resources in the HW resource connection graph, and outputting provisional placement data; (c) calculating, as weights of signal lines between blocks, ratios of a parameter between the individual wires connecting the blocks which affects at least either one of power consumption and each wire delay; (d) judging whether or not each of the weights of signal lines between blocks is equal to or less than a threshold value; and (e) outputting, when each of the weights of signal lines between blocks becomes equal to or less than the threshold value, an RTL logic circuit described in an HDL, the generation of the blocks in the step (a) and the steps (b) to (d) being repeatedly performed till each of the weights of signal lines between blocks is judged equal to or less than the threshold value in the step (d).