Patent ID: 6699793
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a multi-layered spacer, comprising:(a) forming a plurality of gate electrodes each including a gate oxide layer, a gate conductive layer, and a capping dielectric layer on a semiconductor substrate; (b) forming a polyoxide layer on sidewalls of the gate oxide layer and the gate conductive layer and on the semiconductor substrate; (c) forming a silicon nitride layer over the surface of the semiconductor substrate having a step difference therewith; (d) depositing an oxide layer over the surface of the silicon nitride layer having a step difference therewith; (e) forming an external spacer by depositing a dielectric layer for a spacer over the surface of the oxide layer having a step difference therewith and then etching the dielectric layer by an anisotropic method; (f) forming a first interlevel dielectric layer on the entire surface of the semiconductor substrate; (g) forming a photoresist pattern which defines an area in which a pad will be formed; (h) etching the first interlevel dielectric layer using the photoresist pattern as an etching mask, using the silicon nitride layer originally formed at step (c) as an etch stop; (i) removing the photoresist pattern; and (j) thereafter removing the silicon nitride layer originally formed at step (c) and the gate polyoxide layer originally formed at step (b) on the semiconductor substrate between the gate electrodes.