Patent ID: 8953716
Filing Date: 2015-02-10
Classification: H04L

Abstract:
1. An apparatus comprising: a digital high pass filter having a cutoff frequency; a gear mechanism configured to successively change the cutoff frequency of the high pass filter based on a sequence of cutoff frequencies, wherein the sequence of cutoff frequencies includes a first cutoff frequency, a second cutoff frequency, and a third cutoff frequency, further wherein the first cutoff frequency is different from the second cutoff frequency and the third cutoff frequency and the second cutoff frequency is different from the third cutoff frequency; a direct current (DC) estimator configured to estimate a first DC offset of a first digital input signal to the high pass filter based, at least in part, on an output signal of the high pass filter operating with the first cutoff frequency; a direct current (DC) compensator configured to subtract the first DC offset from the first digital input signal to the high pass filter to produce a second digital input signal; wherein the DC estimator is further configured to estimate a second DC offset of the second digital input signal to the high pass filter based, at least in part, on the output signal of the high pass filter operating with the second cutoff frequency; wherein the DC compensator is further configured to subtract the second DC offset from the second digital input signal to the high pass filter to produce a third digital input signal; wherein the DC estimator is further configured to estimate a third DC offset of the third digital input signal to the high pass filter based, at least in part, on the output signal of the high pass filter operating with the third cutoff frequency; and wherein the DC compensator is further configured to subtract the third DC offset from the third input signal to the high pass filter.