Patent ID: 7723233
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A method for forming a gate electrode for a metal oxide semiconductor device having a substrate and formed with a well and opposing trench isolation portions with a first dielectric layer formed thereon, the method comprising the steps of: (a) depositing a first gate electrode layer of a predetermined thickness on said first dielectric layer defining an interface,; (b) doping said first gate electrode layer with a first dopant, defining a doped first gate electrode layer; (c) depositing a second gate electrode layer directly on said doped first gate electrode layer; (d) doping said second gate electrode layer with a second dopant defining a doped second gate electrode layer, said doped first gate electrode layer and said doped second gate electrode structure forming a structure; and (e) heat treating said structure to activate said first dopant and said second dopant with a heat treating temperature profile.