Patent ID: 6292884
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A microprocessor comprising:a register file including a plurality of registers; anda reorder buffer coupled to said register file, said reorder buffer including a plurality of lines of storage, wherein each of said plurality of lines of storage is configured to store information corresponding to up to a predefined maximum number of instructions that are concurrently retireable, said predefined maximum number of instructions being greater than one, and wherein said reorder buffer is configured to concurrently retire instructions represented within a first line of said plurality of lines of storage, and wherein said first line is configured to store a first last-in-line (LIL) indication corresponding to a first instruction represented in said first line, and wherein said first LIL indication is indicative of whether or not said first instruction represented in said first line is last, in program order, among said instructions represented within said first line to have a first register in said register file as a destination, and wherein said reorder buffer is configured to selectively update said first register in said register file with a first result of executing said first instruction responsive to said first LIL indication.