Patent ID: 6226772
Filing Date: 2001-05-01
Classification: H03M

Abstract:
A pipelined system for manipulating data symbols in accordance with the roots of a generator polynomial to produce ""j"" error correction symbols and j error syndromes, the system having n stages and in each stage including:A. j/n registers;B. j/n update adders for adding the contents of the registers to a next data symbol to produce update sums;C. j/n Galois Field multipliers that, respectively, multiply the update sums by j/n associated roots of the generator polynomial;D. a feedback path that includes j/n feedback adders and j/n gates that during encoding operations operate as a chain to pass a propagating sum through the feedback adders, with each feedback adder adding the product produced by the associated Galois Field multiplier to the propagating sum provided by the previous gate and providing the result to the associated register and to a next gate;E. in all stages except the last stage, first and second delay circuits, the first delay circuit holding a data symbol for a clock cycle and the second delay circuit holding a corresponding propagating sum produced in the clock cycle by a last feedback adder in the stage, the delay circuits providing the data symbol and the corresponding propagating sum to a next stage during the next clock cycle; andF. in the first stage, a switch for providing to the update adders in the first stage the data symbols or the sum produced by the last feedback adder in the last stage.