Patent ID: 6258727
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of forming metal lands at the M0 level onto a silicon structure comprising the steps of:a) providing a structure comprised of a silicon substrate having diffused regions formed therein and gate conductor stacks formed thereon; said structure being passivated by an insulating layer;b) forming contact holes exposing some tops of said gate conductor stacks and diffused regions;c) filling at least one of said contact holes exposing a diffused region with doped polysilicon to form a conductive stud therein which is coplanar with the insulating layer surface;d) depositing a layer of an anti-reflective coating (ARC) material onto the structure; said material filling contact holes not filled with doped polysilicon;e) forming a mask at the surface of the structure referred to as the M0 mask exposing the ARC material at desired locations above said contact holes;f) etching the masked structure through the ARC layer and through the insulating layer down to the desired depth in a RIE etcher with a non selective chemistry which etches doped polysilicon, ARC and insulating materials at substantially the same rate to create M0 land recesses;g) removing the remaining ARC material and the overlying mask; and,h) filling said land recesses with a conductive material such as a metal so that the metal and the insulating material top surface are substantially co-planar thereby defining M0 metal lands.