Patent ID: 7233529
Filing Date: 2007-06-19
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising: nonvolatile memory cells each having a threshold voltage which can be changed reversibly by electrical erasing and writing; and a control circuit for controlling the changing of the threshold voltage of each said nonvolatile memory cell, wherein said control circuit controls an erase process of performing simultaneous erasing to a plurality of the nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to a specified one of the nonvolatile memory cells assigned to said one unit when a limit of a threshold voltage distribution in an erase direction is determined to exceed a first level before an over-erase limit in the erase direction, and a second write process of performing writing to a specified one of the nonvolatile memory cells assigned to said one unit when the limit of said threshold voltage distribution in the erase direction is determined to exceed a second level before the over-erase limit in the erase direction after said first write process is completed, wherein said first level is closer to said over-erase limit than said second level, and wherein said second level is between said first level and an erase level indicating a limit of the threshold voltage distribution in a counter-erase direction, wherein said erase process is a process of causing a limit of the threshold voltage distribution in the counter-erase direction to reach an erase limit by repeating an erase verify which determines whether or not the limit of the threshold voltage distribution in the counter-erase direction has reached an erase determination level and erase voltage application which applies an erase voltage when the erase determination level has not been reached, wherein said first write process brings the limit of the threshold voltage distribution in the erase direction within a range under said first level by repeating a first write verify which determines whether or not the limit of the threshold voltage distribution in the erase direction exceeds said first level and first write voltage application which applies the write voltage when a result of the first write verify indicates the first level is exceeded, and wherein said control circuit repeats a first loop including said erase voltage application and the first write verify until the limit of the threshold voltage distribution in the erase direction exceeds said first level, then repeats a second loop including said erase voltage application and the erase verify, performs the first write verify partway through said second loop, and inserts the first write voltage application when the limit of the threshold voltage distribution in the erase direction exceeds said first level.