Patent ID: 8133814
Filing Date: 2012-03-13
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device comprising: forming an insulator layer overlying a semiconductor substrate; depositing a layer of polycrystalline silicon overlying the insulator layer; implanting conductivity determining impurity ions into at least an upper portion of the layer of polycrystalline silicon; etching through the at least upper portion of the layer of polycrystalline silicon using a first anisotropic etch chemistry to expose an edge portion of the at least upper portion of the layer of polycrystalline silicon; forming an oxide barrier on the edge portion; etching a further portion of the layer of polycrystalline silicon using the first anisotropic etch chemistry; and etching a final portion of the layer of polycrystalline silicon using a second anisotropic etch chemistry; wherein etching using the first anisotropic etch chemistry comprises etching using an etch chemistry selected to etch the insulator layer and polycrystalline silicon at comparable rates and wherein etching using the second anisotropic etch chemistry comprises etching using an etch chemistry selected to etch polycrystalline silicon at a substantially higher etch rate than the etch rate of the insulator layer; wherein etching using the first anisotropic etch chemistry comprises etching using an etch chemistry comprising CF