Patent ID: 9110777
Filing Date: 2015-08-18
Classification: G06F,H04M,Y02D

Abstract:
1. A method of operating a system having at least a first circuit portion and a second circuit portion, said method comprising the steps of: operating said first circuit portion at normal clock frequency; operating said second circuit portion in a back-up mode at low clock frequency while said first circuit portion operates at said normal clock frequency, such that said second circuit portion can rapidly come-online but has limited temperature bias instability degradation; wherein said step of operating said second circuit portion at said low clock frequency comprises operating said second circuit portion in a range from 1 Hertz to ten percent of said normal clock frequency; and bringing said second circuit portion on-line and operating said second circuit portion at said normal clock frequency within a few clock cycles of at least one of failure of said first circuit portion and a spike in workload; wherein said step of operating said second circuit portion in said back-up mode comprises running a hardware built-in-self-test pattern at said low clock frequency to exercise at least critical devices in critical circuit paths of said second circuit portion to achieve said limited temperature bias instability degradation.