Patent ID: 6307224
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor layer of a first conductivity type formed on an insulator layer;a first impurity diffusion region of a second conductivity type formed in a surface area of the semiconductor layer;a second impurity diffusion region of the first conductivity type formed in a surface area of the first impurity diffusion region and serving as a source region;a gate insulating layer formed on the first impurity diffusion region and covering a region between the source region and the semiconductor layer;a gate electrode formed on the gate insulating layer;a third impurity diffusion region of the first conductivity type formed in a surface area of the semiconductor layer at a predetermined position away from the first impurity diffusion region; anda fourth impurity diffusion region of the first conductivity type formed in a surface area of the third impurity diffusion region and serving as a drain region,the impurity concentration of the third impurity diffusion region being lower than that of the drain region and higher than that of the semiconductor layer.