Patent ID: 7193399
Filing Date: 2007-03-20
Classification: G05F

Abstract:
1. A voltage regulator comprising: a reference voltage circuit that generates a reference voltage in a normal operation mode and ceases operation in a sleep mode; an amplifier circuit that outputs in the normal operation mode a detection signal obtained by comparing a monitor voltage with the reference voltage and amplifying a difference therebetween and ceases operation in the sleep mode; a P-channel MOS transistor that is connected between a power terminal a power voltage is to be supplied and an output terminal an internal power voltage is to be outputted, and to be controlled in conduction according to a detection voltage; a resistance-based voltage-dividing circuit that is connected between a ground terminal a ground voltage is applied and the output terminal, and supplies to the amplifier circuit the monitor voltage obtained by dividing a voltage on the output terminal; and a sub-regulator circuit that generates a low power voltage different in magnitude from the internal power voltage and outputs same to the output terminal in the sleep mode, and ceases operation in the normal operation mode.