Patent ID: 7353446
Filing Date: 2008-04-01
Classification: H03M

Abstract:
1. A circuit for detecting and correcting errors in a bit stream, said circuit comprising: a. a plurality of bit circuit elements coupled to receive and store said bit stream, each bit circuit element corresponding to a specific bit in a bit pattern; b. at least one operation circuit element for performing operations between contents of at least two of said bit circuit elements; and c. at least two logic gates for determining if said contents of said bit circuit elements match specific bit patterns, at least one of said at least two logic gate receiving inputs from said bit circuit elements; wherein an output of said circuit causes a state of at least one bit in said bit stream to change if contents of said bit circuit elements match at least one of said plurality of specific bit patterns, and said bit patterns correspond to errors that have occurred in said transmitted data, and wherein at least one of said at least two logic gates detects bit patterns corresponding to errors that have been duplicated by a self-synchronous descrambler operating on said bit stream prior to said circuit; and wherein said plurality of bit circuit elements are cascaded such that each bit circuit element receives an input from a source chosen from a group consisting of: a. an immediately preceding bit circuit element, b. an output of an operation circuit element that performs a bitwise operation on contents of at least two of said bit circuit elements, c. and said bit stream.