Patent ID: 6573765
Filing Date: 2003-06-03
Classification: H03K

Abstract:
An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages, the I/O buffer comprising:an I/O node to receive an input signal; a PMOS pull-up transistor having gate, source, drain and body terminals, the source terminal coupled to the first supply voltage and the drain terminal coupled to the I/O node; a pull-down transistor having source and drain terminals, the source terminal coupled to the second supply voltage and the drain terminal coupled to I/O node; and a pull-up transistor bias circuit having a bias terminal coupled to the body and gate terminals of the pull-up transistor, a well pulling circuit having a first drive transistor coupled between the first supply voltage and the bias terminal to couple the bias terminal to the first supply voltage during the input mode in response to the input signal having a voltage less than a voltage threshold, the well pulling circuit further having a second drive transistor coupled between the bias terminal and the I/O node to couple the bias terminal to the I/O node during the input mode in response to the input signal having a voltage greater than the voltage threshold, and a PMOS drive circuit having a drive terminal coupled to the gate of the PMOS pull-up transistor and further coupled to the bias terminal through a balance switch to couple the body and gate terminals of the pull-up transistor during the input mode.