Patent ID: 6249901
Filing Date: 2001-06-19
Classification: G06F

Abstract:
An automatic memory characterization process comprising the steps of:(a) receiving a memory circuit netlist extracted from layout data defining an instance a memory circuit of a memory compiler design;(b) performing an automatic circuit reduction process on said circuit netlist to generate a critical path netlist;(c) generating a specification file based on a data sheet associated with at least one timing parameter to be characterized for said circuit, said specification file including at least one input signal parameter defining an associated input signal to be provided to a selected input node of said circuit, and at least one output loading parameter defining an associated output load to be applied to a selected output node of said circuit;(d) generating an updated stimulus file based on said input signal parameters;(e) generating an updated critical path netlist based on said critical path netlist and said at least one output loading parameter; and(f) performing at least one circuit simulation process based on said updated critical path netlist and said updated stimulus file to yield an associated value for said timing parameter.