Patent ID: 6025853
Filing Date: 2000-02-15
Classification: G06T,G09G

Abstract:
A graphics processing subsystem, comprising:at least four functionally distinct processing units, each including hardware elements which are customized to perform a rendering operation which is not performed by at least some others of said processing units; at least some ones of said processing units being connected to operate asynchronously to one another;a frame buffer, connected to be accessed by at least one of said processing units;said processing units being mutually interconnected in a pipeline relationship, such that said processing units jointly provide a pipelined multiple-instruction-multiple-device (MIMD) graphics processing architecture;wherein individual ones of said processing units receive messages and, in accordance with the content of each said respective message, programmably perform a respective graphics processing operation, and selectably transmit said respective message to a succeeding one of said processing units; andwherein said processing units include a memory access unit which reads and writes a local buffer memory.