Patent ID: 8607120
Filing Date: 2013-12-10
Classification: G06F,H03M

Abstract:
1. A memory system; comprising: a nonvolatile memory device; and a memory controller electrically coupled to said nonvolatile memory device, said memory controller comprising an error correction code (ECC) generation circuit configured to generate a first ECC code associated with first data written into said nonvolatile memory device and further configured to generate a second ECC code associated with a first portion of the first data in response to detecting a first data pattern within the first data; wherein said memory controller is configured to write the first and second ECC codes into said nonvolatile memory device along with writing the first data into said nonvolatile memory device; and wherein said memory controller is further configured to decode the first data when read from said nonvolatile memory device using the first and second ECC codes to detect at least one error in the first data.