Patent ID: 7427552
Filing Date: 2008-09-23
Classification: H01L

Abstract:
1. A method for fabricating integrated circuit devices, the method comprising: providing a semiconductor substrate, the semiconductor substrate having a peripheral region and a cell region; forming a first dielectric layer having a first thickness overlying a cell region and a second dielectric layer having a second thickness overlying the peripheral region; forming a pad oxide layer overlying the first dielectric layer and the second dielectric layer; forming a nitride layer overlying the pad oxide layer; patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained; forming a first trench structure having a first depth in the first trench region, while the portion of the first dielectric layer having the first thickness in the cell region protects the second trench region; removing the portion of the first dielectric layer to expose the second trench region; and subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth and to form a second trench structure having a third depth within the second trench region; whereupon the third depth is less than the second depth.