Patent ID: 6577164
Filing Date: 2003-06-10
Classification: H04L

Abstract:
An output circuit, comprising:a first output terminal; a second output terminal; a first power terminal for supplying a first voltage level; a second power terminal for supplying a second voltage level that is higher than the first voltage level; an input terminal receiving an input logical signal; a first constant voltage supply circuit generating a third voltage level that is higher than the first voltae level and is lower than the second voltage level; a second constant voltage supply circuit generating a fourth voltage level that is lower than the second voltage level and is higher than the third voltage level; and an output logic formation circuit connected to the first and second constant voltage supply circuits and the first and second output terminals, the output logic formation circuit generating a first output logical signal at the first output terminal and a second output logical signal at the second output terminal, wherein the first output logical signal has a logic corresponding to a logic of the input logical signal and the second output logical signal has a logic corresponding to an inverted logic of the input logical signal, and wherein the first and second output logic signals having either a fifth voltage level between the third voltage level and the fourth voltage level, or a sixth voltage level between the fifth voltage level and the fourth voltage level, based on the logic of the input logical signal, the output logic formation circuit including: a logic inverting circuit having an input receiving the input logical signal and an output providing an inverted input logical signal, a first transistor having a gate receiving the input logical signal, a first terminal connected to the first constant voltage supply circuit and a second terminal connected to the second output terminal, a second transistor having a gate receiving the input logical signal, a first terminal connected to the second constant voltage supply circuit and a second terminal connected to the second output terminal, a third transistor having a gate receiving the inverted input logical signal, a first terminal connected to the first constant voltage supply circuit and a second terminal connected to the first output terminal, and a fourth transistor having a gate receiving the inverted input logical signal, a first terminal connected to the second constant voltage supply circuit and a second terminal connected to the first output terminal.