Patent ID: 9041109
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A semiconductor structure comprising: at least one source region located on a single crystalline insulator layer; at least one drain region located on said single crystalline insulator layer; a planar channel region laterally contacting said at least one source region and said at least one drain region, said planar channel region including a single crystalline semiconductor material that is epitaxially aligned to a crystallographic structure of said single crystalline insulator layer and having a top surface that is more proximal to said single crystalline insulator layer than top surfaces of said at least one source region and said at least one drain region; a gate dielectric having a bottommost surface that contacts said top surface of said planar channel region; a gate electrode vertically spaced from said planar channel region by said gate dielectric; and a gate spacer laterally surrounding at least a lower portion of said gate electrode.