Patent ID: 6111899
Filing Date: 2000-08-29
Classification: H04L,H04Q

Abstract:
Interfacing device (INT) to be coupled between an incoming channel (IC) and an outgoing channel (OC) and to be used to replace M outgoing sets of bits out of N outgoing sets of bits (OS1, OS2, . . . , OSN) by M incoming sets of bits (IS1, IS2, . . . , ISM) received on said incoming channel (IC), M being an integer number smaller than N, said interfacing device (INT) comprising:a. outgoing register means (OR) provided to temporarily store said N outgoing sets of bits (OS1, OS2, . . . , OSN); andb. selection means (SEL) coupled between said incoming channel (IC) and said outgoing register means (OR), and provided to select said M outgoing sets of bits out of said N outgoing sets of bits (OS1, OS2, . . . , OSN) and to route said M incoming sets of bits (IS1, IS2, . . . , ISM) to said outgoing register means (OR) to thereby replace said M outgoing sets of bits,wherein said selection means (SEL) further comprises:c. a multiplexing unit (MUX) including N multiplexers (MUX1, MUX2, . . . , MUXN), each multiplexer being related to an outgoing set of bits of said N outgoing sets of bits (OS1, OS2, . . . , OSN), and having a control input, the multiplexer unit (MUX) having at most M input terminals adapted to sink at most M incoming sets of bits out of said M incoming sets of bits (IS1, IS2, . . . , ISM), and one output terminal adapted to source one of said at most M incoming sets of bits under control of a control signal applied to said control input if said related outgoing set of bits has to be replaced; andd. a control unit (CTRL) adapted to generate for said each multiplexer, said control signal and to apply said control signal via an output terminal of said control unit (CTRL) to said control input of said each multiplexer.