Patent ID: 7716563
Filing Date: 2010-05-11
Classification: H03M

Abstract:
1. A method for implementing a general convolutional interleaver, the method comprising: dividing an incoming data stream to a digital subscriber loop system into blocks of I bytes, wherein I is an interleaver block size in bytes; mapping each member of a block into a set of first-in, first-out shift registers (FIFOs) arranged in rows, wherein the number of elements nd in a row j is given by: wherein int(j·D/I) is an integer part of j·D/I and D is an interleaver block depth in bytes, and wherein using the number of elements in a row j as nd(j) provides general convolutional interleaving with no constraints, in an efficient manner, using (D−1)*(I−1)/2 memory locations for interleaved data in all cases; shifting the set of first-in, first-out shift registers (FIFOs) as the mapping step is performed; and reading elements shifted out of the set of first-in, first-out shift registers (FIFOs) in a different order from how they were mapped into the set of first-in, first-out shift registers (FIFOs), wherein the different order comprises reading indices of rows given by id(j), wherein id(j) is determined by: wherein rem(j·D/I) is a remainder part of j·D/I.