Patent ID: 7243039
Filing Date: 2007-07-10
Classification: G01R

Abstract:
1. A method for determining locations on an integrated circuit microchip to be probed, comprising: a. receiving a callout list of failures from a tester, said callout list including cell name and pin for each failure; b. interrogating a Def file to locate a Def entry matching said cell name and obtaining from said Def entry cell type, cell location, and cell orientation data; c. interrogating a Lef file to locate a Lef entry matching said cell type and obtaining from said Lef entry coordinates of said pin; d. interrogating a GDS file to locate a GDS entry matching said cell type and obtaining coordinates of polygons listed in said GDS entry; e. crossing the coordinates of said pin with the coordinates of said polygons to identify overlapping area; f. defining said overlapping area as the location to be probed.