Patent ID: 7701046
Filing Date: 2010-04-20
Classification: H01L

Abstract:
1. A stacked type chip package structure, comprising: a backplate, comprising a circuit layer disposed on a top surface of the backplate; a circuit substrate, disposed on the backplate, wherein the circuit substrate has an upper surface and an opposite lower surface, a portion of the lower surface of the circuit substrate is in physical contact with the top surface of the backplate, while another portion of the lower surface of the circuit substrate is exposed, and the circuit substrate has a receiving hole that is covered by the backplate; a first chip, disposed inside the receiving hole, wherein the first chip is electrically connected to the circuit substrate through the circuit layer of the backplate; a second chip, disposed above the first chip, and electrically connected to the circuit substrate; and an interposer, disposed between the first chip and the second chip, wherein a size of the interposer is smaller than that of the circuit substrate and the interposer is electrically connected to a ground of the circuit substrate by wire bonding technique.