Patent ID: 8891276
Filing Date: 2014-11-18
Classification: G11C

Abstract:
1. A non-volatile memory device, comprising: a plurality of back-end-of-the-line (BEOL) wordlines (WLs); a plurality of BEOL local bitlines (LBLs) selectively electrically coupled with a plurality of front-end-of-the-line (FEOL) global bit lines (GBLs); a plurality of BEOL discrete re-writable non-volatile two-terminal memory elements, each memory element positioned between a cross-point of one of the plurality of BEOL WLs with one of the plurality of BEOL LBLs and each memory element directly electrically in series with its respective WL and LBL; and a plurality of FEOL amplifiers electrically coupled with the plurality of BEOL LBLs and the plurality of FEOL GBLs.