Patent ID: 6313683
Filing Date: 2001-11-06
Classification: G01R,G06F

Abstract:
A method of providing clock signals to a plurality of load circuits in respective clock domains of a ASIC device having a balanced clock tree including a master clock line and branched clock lines feeding the clock signals to the load circuits and wherein the balanced clock tree is balanced with respect to delays and loads in the clock domains of the ASIC device to which the branched clock lines supply the clock signals, wherein the method comprises:a) generating derived clock signals by gating the master clock signal such that the derived clock signals have a frequency reduced from a frequency of the master clock signal by a factor n>1 (n=2, . . . , N), which is adapted to a need of the load circuits in a respective one of the clock domains, andb) routing either the master clock signal or the derived clock signal for a respective one of the clock domains to the load circuit of the respective clock domain, wherein the derived clock signals are generated and routed in a synchronous manner with respect to each other and the master clock signal.