Patent ID: 6751767
Filing Date: 2004-06-15
Classification: G06F

Abstract:
A test pattern compression method for executing test pattern compression processing in a distributed manner by a plurality of parallel processing units, comprising:(a) a repeated random-number fault simulation step which includes: (a1) creating test patterns in which undefined values in test patterns that inspect a logic circuit for faults defined for the logic circuit have been activated by assigning â€œ0â€  or â€œ1â€  to these undefined values based upon a random-number sequence; (a2) running a fault simulation on said logic circuit using fault information and the test patterns in which the undefined values have been activated; and (a3) generating and outputting, on the basis of results of the fault simulation, test patterns having undefined values assigned to values for pins of said logic circuit that do not participate in fault detection in the test patterns in which the undefined values have been activated; and (b) pattern merging the test patterns generated and output by said repeated random-number fault simulation step (a); wherein (c) the faults defined for said logic circuit are divided into a plurality of fault groups and the fault groups are assigned to respective ones of said plurality of parallel processing units; and (d) said plurality of processing units execute the repeated random-number fault simulation step for said logic circuit in parallel with one another using the fault groups that have been assigned to respective ones of said processing units.