Patent ID: 9035923
Filing Date: 2015-05-19
Classification: G09G

Abstract:
1. A semiconductor device comprising: a gate signal line; each of a first gate driver circuit and a second gate driver circuit configured to output a selection signal and a non-selection signal to the gate signal line; and a plurality of pixels electrically connected to the gate signal line, wherein in a period of a first frame period, during which the gate signal line is selected, both the first gate driver circuit and the second gate driver circuit are configured to output the selection signal to the gate signal line, wherein in another period of the first frame period, during which the gate signal line is not selected, the first gate driver circuit is configured to output the non-selection signal to the gate signal line, and the second gate driver circuit is configured to output neither the selection signal nor the non-selection signal to the gate signal line, wherein in a period of a second frame period, during which the gate signal line is selected, both the first gate driver circuit and the second gate driver circuit are configured to output the selection signal to the gate signal line, and wherein in another period of the second frame period, during which the gate signal line is not selected, the second gate driver circuit is configured to output the non-selection signal to the gate signal line, and the first gate driver circuit is configured to output neither the selection signal nor the non-selection signal to the gate signal line.