Patent ID: 6958513
Filing Date: 2005-10-25
Classification: H01L

Abstract:
1. An electrically erasable and programmable read only memory device comprising: a bulk material; a first layer of semiconductor material over said bulk material and having a first conductivity type; a first region formed in between said bulk material and said first layer, and having a second conductivity type; a trench formed into a surface of said first layer and having a sidewall and a bottom; a second region formed in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type; a channel region in said first between said first region and said second region, and extending generally along said sidewall of said trench; an electrically conductive floating gate disposed adjacent to and insulated from said channel region; an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate; and an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.