Patent ID: 6646299
Filing Date: 2003-11-11
Classification: H01L

Abstract:
An integrated circuit configuration, comprising:a substrate having a surface; at least two capacitors provided on said surface of said substrate; each of said capacitors having a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric; said first capacitor electrode and at least a given part of said second capacitor electrode having respective lateral faces, said first capacitor electrode and said second capacitor electrode being disposed such that only said respective lateral faces of said first capacitor electrode and of at least said given part of said second capacitor electrode are disposed opposite one another; said first capacitor electrode and said given part of said second capacitor electrode being composed of a material that is hard to etch; said capacitor dielectric being composed of a perovakite and being disposed between said lateral faces of said first capacitor electrode and of said given part of said second capacitor electrode disposed opposite one another; said first capacitor electrode being substantially composed of a given metal, said second capacitor electrode being configured such that only said given part of said second capacitor electrode is substantially composed of said given metal; an adhesive layer being composed of at least of one material selected from the group consisting of ruthenium, iridium, molybdenum, a ruthenium oxide, an iridium oxide, a molybdenum oxide, Tantalum and TaN, said adhesive layer having a first part and a second part; said first capacitor electrode being disposed on said first part of said adhesive layer and said second capacitor electrode being disposed on said second part of said adhesive layer; and said given part of said second capacitor electrode of a first one of said at least two capacitors being coherent with said given part of said second capacitor electrode of a second one of said at least two capacitors.