Patent ID: 6256244
Filing Date: 2001-07-03
Classification: G11C

Abstract:
In a semiconductor memory device including up and down cell blocks vertically arranged, and an array of sense amplifiers interposed between the cell blocks, the up and down cell blocks being selectively connected to the sense amplifiers in accordance with associated sense amplifier connection signals, respectively, a self refresh apparatus comprising:a refresh counter for generating word line selection signals and cell block selection signals required for a refresh operation in a self refresh mode for the cell blocks, respectively;block selection means for receiving a precharge signal along with the cell block selection signals, thereby selecting desired ones of the cell blocks respectively associated with the cell block selection signals while determining whether the selected cell blocks are in an active state or in a precharge state, respectively;sense amplifier selection control means for determining a variation in each of the sense amplifier connection signals in accordance with a variation in an associated one of the cell block selection signal; andsense amplifier selection means for controlling a potential level of each of the sense amplifier connection signals under a control of the sense amplifier selection control means.