Patent ID: 7209377
Filing Date: 2007-04-24
Classification: G11C

Abstract:
1. A ferroelectric memory device having memory cells using ferroelectric capacitors disposed at intersections of a plurality of word lines and a plurality of bit lines, respectively, the ferroelectric memory device comprising: a pair of main bit lines having generally identical line width and line length; a sense amplifier that lies between one of the main bit lines and the other of the main bit lines; a plurality of local bit lines associated with each of the main bit lines and disposed in parallel with the main bit lines; a plurality of switching elements, each provided between each of the local bit lines and the main bit line for selectively connecting one of the plurality of local bit lines to the main bit line; a plurality of memory cells, each provided at an intersection between each of the word lines and each of the plurality of local bit lines; and a plurality of dummy cells, each provided at an intersection between each of the word lines and the main bit line, and used for generating a reference potential, wherein one of the main bit lines is connected to one of the local bit lines through the switching element to readout data from one of the memory cells connected to the one of the local bit lines, and the dummy cell connected to the other of the main bit lines is selected to generate a reference potential.