Patent ID: 8724771
Filing Date: 2014-05-13
Classification: G11C

Abstract:
1. A shift register comprising a plurality of stages, each of the stages outputting a carry pulse and a scan pulse, wherein an nth one of the stages (where n is a natural number) comprises: a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line, the carry clock transfer line transferring any one of i carry clock pulses having different phases (where i is a natural number greater than 1), and a carry output terminal of the nth stage; a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line, the scan clock transfer line transferring any one of j scan clock pulses having different phases (where j is a natural number greater than 1), and a scan output terminal of the nth stage; and a stabilization switching device controlled by any one of the i carry clock pulses overlapping with the scan clock pulse applied to the scan output switching device and connected between a carry output terminal of an (n−p)th one of the stages (where p is a natural number less than n) and the set node or between a start transfer line, the start transfer line transferring a start pulse, and the set node.