Patent ID: 6569746
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of forming an integrated circuit device, comprising the steps of:forming a barrier metal layer on an integrated circuit substrate; forming a first electrically conductive layer that extends on the barrier metal layer; selectively etching the first electrically conductive layer to define a first wiring line and a lower capacitor electrode; forming an electrically insulating layer that extends on the first wiring line and on the lower capacitor electrode that is separate from the first wiring line; patterning the electrically insulating layer to define a first contact hole therein that exposes an upper surface of the lower capacitor electrode; forming a capacitor dielectric layer that extends on the electrically insulating layer and on the upper surface of the lower capacitor electrode; selectively etching the capacitor dielectric layer and the electrically insulating layer in sequence to define a second contact hole that exposes an upper surface of the first wiring line; and forming first and second electrically conductive plugs in the first and second contact holes, respectively.