Patent ID: 6590457
Filing Date: 2003-07-08
Classification: H03L,H04L

Abstract:
A phase detector, comprising:a data line transmitting data at least at a high clock rate; a first clock line for transmitting first clock signals and a second clock line for transmitting second clock signals; a first weighting device, a second weighting device and a third weighting device; a first flip-flop having a first input connected to said data line, a second input connected to said first clock line and an output; a second flip-flop having a first input connected to said output of said first flip-flop, a second input connected to said second clock line and an output; a third flip-flop having a first input connected to said output of said second flip-flop, a second input connected to said first clock line and an output; a first XOR gate having a first input connected to said data line, a second input connected to said output of said first flip-flop and an output connected to said first weighting device; a second XOR gate having a first input connected to said output of said first flip-flop and to said first input of said second flip-flop, a second input connected to said output of said second flip-flop and to said first input of said third flip-flop and an output connected to said second weighting device; a third XOR gate having a first input connected to said output of said second flip-flop and to said first input of said third flip-flop, a second input connected to said output of said third flip-flop and an output connected to said third weighting device; a fourth flip-flop having a first input connected to said data line, a second input connected to said second clock line and an output; a fifth flip-flop having a first input connected to said output of said fourth flip-flop, a second input connected to said first clock line and an output; a sixth flip-flop having a first input connected to said output of said fifth flip-flop and a second input connected to said second clock line; and correction devices for producing a correction signal; the first and second clock signals having clock rates corresponding to substantially half the high clock rate, and the first clock signals having a phase shifted by 180Â° with respect to a phase of the second clock signals.