Patent ID: 8006072
Filing Date: 2011-08-23
Classification: G06F

Abstract:
1. A method of operating a pipelined computer processor, said method comprising: identifying program instructions dependent upon results of prior program instructions in a set of instructions; dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, each instruction of said set belonging to only one subset; retrieving a first and a second instruction belonging to a first of said subsets and a third instruction belonging to a second of said subsets from an instruction pipeline; processing the first and the second instructions operating on a first piece of input data in a first pass to produce a first processed piece of input data, where the first and second instructions are separated by a time interval; and processing the first and the second instructions operating on a second piece of input data and the third instruction operating on the first processed piece of input data in a second pass, where the third instruction is processed during the interval separating the first and second instructions.