Patent ID: 7361534
Filing Date: 2008-04-22
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of: ion implanting a well region in the monocrystalline silicon substrate; depositing a gate electrode material overlying the monocrystalline silicon layer; providing a patterned mask overlying the gate electrode material, wherein the patterned mask comprises openings of a minimum lithography feature size; etching the gate electrode material to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size; then isotropically etching the gate electrode material to reduce the width of the first gate electrode, the second gate electrode and the spacer; ion implanting N-type impurity determining dopant ions into the well region of the monocrystalline silicon substrate using the spacer as an ion implant mask to form an N-type device region in the well region of the monocrystalline silicon substrate and into the monocrystalline silicon layer using the first gate electrode as an ion implant mask to form N-channel source and drain regions in the monocrystalline silicon layer; and ion implanting P-type impurity determining dopant ions into the well region of the monocrystalline silicon substrate using the spacer as an ion implant mask to form a P-type device region in the well region of the monocrystalline silicon substrate and into the monocrystalline silicon layer using the second gate electrode as an ion implant mask to form P-channel source and drain regions in the monocrystalline silicon layer.