Patent ID: 9141744
Filing Date: 2015-09-22
Classification: G03F,G06F

Abstract:
1. A method for generating a layout pattern comprising a FinFET structure layout, the method comprising: providing a layout pattern to a computer system, wherein the layout pattern comprises a sub-pattern; classifying the sub-pattern into a first sub-pattern and a second sub-pattern by the computer system; generating a plurality of first stripe patterns, wherein longitudinal edges of the first stripe patterns are aligned with longitudinal edges of the first sub-pattern by the computer system; generating at least one second stripe pattern by the computer system, wherein longitudinal edges of the second stripe pattern are aligned with longitudinal edges of the second sub-pattern, and widths of the second stripe pattern are different from the widths of the first stripe patterns; and outputting the first stripe patterns and the second stripe pattern to a photomask by the computer system.