Patent ID: 6374391
Filing Date: 2002-04-16
Classification: G06F

Abstract:
A method for estimating a parasitic capacitance coupled to a signal line forming a part of an integrated circuit incorporated in a semiconductor device, comprising the steps of:a) preparing a first piece of data information indicative of a minimum length for calculating a parasitic capacitance as a function of the length of a signal line, a second piece of data information indicative of a capacitance considered to be coupled to a unit length of signal lines and third pieces of data information used for estimating the parasitic capacitance coupled to a signal line through a known method; b) determining the length of a given signal line; c) comparing said length of said given signal line with said minimum length so as to determine whether or not said function is available for determining the parasitic capacitance coupled to said given signal line; d) determining said parasitic capacitance coupled to said given signal line by using said function once when said given signal line is equal to or greater than said minimum length; and e) determining said parasitic capacitance coupled to said given signal line by using said known method without execution of said step d) when said given signal line is less than said minimum length.