Patent ID: 6144675
Filing Date: 2000-11-07
Classification: H04J

Abstract:
A clock regeneration apparatus for regenerating and distributing a clock signal in a data transmission network that is organized by a plurality of transmission units linked in a ring topology, at least two of the plurality of transmission units each having an external clock source, the plurality of transmission units including a first transmission unit, and a second and third transmission units neighboring the first transmission unit, the clock regeneration apparatus being disposed in the first transmission unit and comprising:clock source list memory means for storing a clock source list containing entries for a plurality of clock sources out of which the first transmission unit can select a reference clock source for synchronization, the plurality of clock sources having different priority levels for the selection, the plurality of clock sources including at least two line clock sources provided from the second and third transmission units;master/slave data memory means for storing a master/slave mode flag indicating whether the first transmission unit serves as a master transmission unit that supplies the clock signal to the network or acting as a slave transmission unit that is supplied with the clock signal from the master transmission unit;clock selection control means for selecting, fromamong the plurality of clock sources, a reference clock source with which the first transmission unit is to be synchronized, based on the clock source list, the master/slave mode flag stored in the master/slave data memory means, and clock quality messages that the first transmission unit have received from the second and third transmission units; andclock quality transmission means for supplying either one of the second and third transmission unit that is not selected as the reference clock source by said clock source selection control means, with a message requesting not to use a corresponding line clock source for synchronization, if the master/slave mode flag stored in said master/slave data memory means indicates that the first transmission unit is acting as a slave transmission unit, and if the clock quality messages received from the second and third transmission units exhibit equal clock quality levels continually for a predetermined period.