Patent ID: 7480172
Filing Date: 2009-01-20
Classification: G11C

Abstract:
1. An MRAM array comprising: a plurality of MRAM devices arranged in rows and columns; a plurality of bit lines, each bit line associated with one column of the columns of the plurality of MRAM devices and adjoined to a free magnetic layer of each MRAM device of said column; a plurality of word lines, each word line associated with one row of the plurality of MRAM devices and comprising multiple word line segments, said word line segments in close proximity to a fixed magnetic layer of each MRAM device of a sub-grouping of said one row of MRAM devices; an MRAM programming circuit in communication with each of the plurality of bit lines and each of the multiple word line segments of the plurality of word line, said programming circuit providing a bidirectional bit line current to a selected bit line of the plurality of bit lines and a word line current pulse to one word line segment of one row of word line segments; and a field biasing device having a magnetic coupling to each of the plurality of MRAM devices to provide a magnetic biasing field to each of the MRAM device.