Patent ID: 6614842
Filing Date: 2003-09-02
Classification: H03H

Abstract:
An apparatus for receiving and processing a first waveform (SIG3) representing successive bits of a data sequence during successive data cycles, wherein a state of each successive bit of the data sequence is indicated by whether the first waveform transitions between voltage levels during a corresponding one of the data cycles, and wherein the apparatus produces an output digital data signal representing the data sequence, the apparatus comprising:filter means for filtering the first waveform to provide equalization and gain control, thereby producing a second waveform (SIG5) representing successive bits of the data sequence during successive data cycles, wherein the state of each successive bit of the data sequence is indicated by whether the second waveform transitions between defined voltage levels during a corresponding one of the data cycles, wherein the filter means implements a filter function having N adjustable coefficients adjusted by coefficient control signals (C1, C2, C3) supplied as input to the filter means, wherein N is an integer greater than 2, wherein each of the N adjustable coefficients influences a relationship between the first and second waveforms; a data slicer for repeatedly digitizing the second waveform in response to edges of a clock signal to produce data output indicating a voltage range of the second waveform; a clock signal generator for supplying the clock signal to the data slicer with a phase determined by a phase control signal; and an adaptive control circuit for processing the data output of the data slicer to produce and supply the coefficient control signals to the filter means, to produce and supply the phase control signal to the clock signal generator, and to produce the digital data signal.