Patent ID: 6108769
Filing Date: 2000-08-22
Classification: G06F

Abstract:
An apparatus for performing dependency checking in a superscalar microprocessor, comprising:a dependency table having a storage location for storing dependency information regarding a register, wherein said dependency information includes a first tag identifying an instruction which updates at least a portion of said register and a width identifying said portion of said register updated by said instruction, and wherein said instruction identified by said first tag is the most recent instruction in program order to update said register; anda control unit configured to detect dependencies between a set of concurrently decoded instructions and to assign a second tag for each source operand within said set of concurrently decoded instructions, wherein said second tag identifies one of said set of concurrently decoded instructions if said control unit detects an update of said source operand by said one of said set of concurrently decoded instructions, wherein said control unit is configured to supply said first tag from said storage location within said dependency table as said second tag if said source operand is stored in said register and said control unit does not detect an update of said source operand by said one of said set of concurrently decoded instructions.