Patent ID: 8234521
Filing Date: 2012-07-31
Classification: G06F

Abstract:
1. A fault-tolerant computer system comprising: a first subsystem comprising a first processor, a first cache, a first memory; a second subsystem comprising a second processor, a second cache, a second memory; a detector adapted to detect errors in the first and second subsystems before error propagation in the first subsystem or the second subsystem can cause contents of the first and the second memory to differ; and a fault tolerant logic component in communication with the first and second subsystems, the fault tolerant logic component adapted to distinguish a transient error from a non-recoverable error and select between a first re-sync procedure and a second re-sync procedure such that the first re-sync procedure is selected if the error is transient and the second re-sync procedure is selected if the error is a non-recoverable error and contents of the first and second memories are different and wherein the first re-sync procedure is selected if a non-recoverable error is not declared within a delay period that is less than about 90 milliseconds.