Patent ID: 7299342
Filing Date: 2007-11-20
Classification: G06F

Abstract:
1. A digital signal processor comprising: a plurality of accelerator units, each configured to perform one or more dedicated functions; a processor core coupled to the plurality of accelerator units, wherein the processor core includes an integer execution unit configured to execute integer instructions; and a complex computing unit coupled to the plurality of accelerator units, wherein the complex computing unit is configured to execute complex vector instructions; wherein the complex computing unit includes a first clustered execution pipeline including one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions, and a second clustered execution pipeline including one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions; and wherein each of the one or more complex arithmetic logic unit datapaths further includes a complex short multiplier accumulator datapath configured to multiply a complex data value by values in a set of numbers defined by {0, +/−1}+{0,+/−i} using two's complement arithmetic.