Patent ID: 6426255
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A process for manufacturing a semiconductor integrated circuit device having a memory cell which comprises a memory-cell selecting MISFET formed on the main surface of a semiconductor substrate, and a capacitor formed of a first electrode electrically connected to one of a source and a drain of the memory-cell selecting MISFET and a second electrode formed over the upper surface and side surface of the first electrode via a capacitative insulating film, which comprises:(a) forming the memory-selecting MISFET on the main surface of the semiconductor substrate and then forming thereover a first insulating film; (b) forming a conductive underlying film over the first insulating film and then forming thereover a second insulating film; (c) forming a groove in the second insulating film and then exposing the conductive underlying film at the bottom portion of the groove; (d) forming a conductor film, which is comprised mainly of a platinum metal, a platinum alloy or a conductive oxide of a platinum metal, over the conductive underlying film exposed at the bottom portion of the groove by electroplating with the conductive underlying film as a cathode electrode and embedding the conductor film inside the groove, wherein the embedding of the conductor film inside the groove further comprises (i) forming the conductor film to give a film thickness not less than the depth of the groove by electroplating with the conductive underlying film as a cathode electrode, and (ii) polishing back the conductor film by chemical mechanical polishing or etching back the conductor film by dry etching until at least the upper surface of the second insulating film is exposed; and(e) after the removal of the second insulating film, removing the conductive underlying film by etching with the conductor film as a mask, thereby forming the first electrode of the capacitor which is formed of the conductor film and the conductive underlying film thereunder.