Patent ID: 6556493
Filing Date: 2003-04-29
Classification: G11C

Abstract:
A method for testing a memory cell of the semiconductor device, comprising the steps of:a) determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell; b) testing an erasure verifying memory cell to be tested at a room temperature, wherein the step b) includes the steps of: b1) measuring and storing a second drain current flowing in the erasure verifying memory cell as a first data at a room temperature after erasing the erasure verifying memory cell; b2) erasing a sector of the erasure verifying memory cell; b3) measuring a third drain current of the erasure verifying memory cell at a room temperature; and b4) comparing the first drain current with the third drain current; c) detecting a fourth drain current by measuring the erasure verifying memory cell at a hot temperature and comparing the fourth drain current with the first drain current; d) varying the first drain trip point according to a current difference between the firs and the fourth drain currents; and e) setting a second trip point of the erasure verifying memory cell according to the varied first trip point.