Patent ID: 6867580
Filing Date: 2005-03-15
Classification: G01R

Abstract:
1. A system for testing reliability in an integrated circuit (IC), the system comprising: a core cell array comprising an array of rows and columns of test circuits; a row select circuit coupled to the core cell array and selecting at least one of the rows of test circuits from the core cell array; a plurality of column switches coupled to the core cell array; a column select circuit coupled to the column switches and controlling the column switches to select at least one of the columns of test circuits from the core cell array; a pair of global stress lines coupled to a first subset of the column switches, wherein a high stress current is applied from the global stress lines to a selected column of test circuits in the core cell array; and a pair of global sense lines coupled to the test circuits through a second subset of the column switches, wherein a resistance through a selected test circuit can be measured.