Patent ID: 8893104
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. A compiler method implemented within a compiler on a computing device, the method comprising: identifying operations that are capable of being performed on either a main pipe or an alternative pipe; identifying chains of dependent operations that are capable of being performed on either the main pipe or the alternative pipe; generating pseudo instructions, before performance of a register allocation process, that enable later generation of instructions capable of representing instructions for each of the main pipe and the alternative pipe during or after performance of the register allocation process; identifying points of execution at which a number of simultaneous live values will exceed a number of available registers in the main pipe; identifying live values associated with candidate chains of operations; choosing a chain of operations as a candidate to be moved to the alternative pipe based on relative costs of performing each chain of operations on the alternative pipe in order to reduce the number of simultaneous live values at identified points of execution that compete for registers in the main pipe; and generating actual instructions for the chosen chain of operations for execution on either the main pipe or the alternative pipe during or after performance of the register allocation process.