Patent ID: 6591327
Filing Date: 2003-07-08
Classification: G11C

Abstract:
A flash memory comprising:an address bus; a data bus; an array of addressable nonvolatile memory cells, connected to said address bus and said data bus; a latch for storing signals supplied from said address bus and said data bus; a decoder for decoding said signals stored in said latch, and in response to a first combination of said signals stored in said latch, said decoder for selecting a plurality of first nonvolatile memory cell sectors each of a first size, and in response to a second combination of said signals stored in said latch, said decoder for selecting a plurality of second nonvolatile memory cell sectors each of a second size, different from said first size; and control circuitry for controlling the erasure of at least one of the selected plurality of first sectors and at least one of the selected plurality of second sectors of said memory array in response to said first and second signal combinations, respectively; wherein each of said second sectors comprises a plurality of said first sectors.