Patent ID: 7143269
Filing Date: 2006-11-28
Classification: G06F

Abstract:
1. An apparatus for killing an instruction loaded into an instruction queue of a microprocessor during a first clock cycle and output from a bottom entry of the instruction queue during a second clock cycle subsequent to the first clock cycle, the apparatus comprising: a kill signal, for conveying a value generated during a third clock cycle subsequent to the first clock cycle; a kill queue, coupled to said kill signal, for loading said kill signal value generated during said third clock cycle, and for outputting said kill signal value during the second clock cycle; a load signal, coupled to said kill queue, for indicating during the second clock cycle whether the instruction was loaded into the bottom entry of the instruction queue during the first clock cycle, wherein if said load signal is true, said third clock cycle and the second clock cycle are a same clock cycle; and a valid signal, coupled to said kill queue, generated during the second clock cycle for indicating whether the instruction is to be executed by the microprocessor, wherein said valid signal is false if said kill signal value output by said kill queue during the second clock cycle is true.