Patent ID: 9134378
Filing Date: 2015-09-15
Classification: G01R,G06F

Abstract:
1. In an electronic design automation (EDA) tool, a method for calculating static seeds and dynamic seeds to enable generation of care bits for detecting faults in a circuit under test (CUT), the method comprising: receiving an integrated circuit (IC) design that includes a set of registers, a linear expander, and the CUT, wherein the linear expander is capable of generating the care bits based on data stored in the set of registers and scanning the care bits into a set of scan chains in the CUT, wherein the care bits comprise a set of static care bits and a set of dynamic care bits, wherein the static care bits are capable of being encoded by using a first system of linear equations based on static seeds, wherein the dynamic care bits are capable of being encoded by using a second system of linear equations based on dynamic seeds, and wherein the first system of linear equations includes an augmented equation for each static care bit which is capable of being determined by superposing linear equations of the static care bit and at least one corresponding dynamic care bit; calculating the static seeds based on the static care bits and the first system of linear equations; and calculating the dynamic seeds based on the dynamic care bits and the second system of linear equations.