Patent ID: 6324260
Filing Date: 2001-11-27
Classification: H04B,H04L,H04M,H04Q

Abstract:
A channel check test system comprising:a transmitting side digital circuit multiplication equipment (DCME) including:an input pattern generator for generating a nonlinear quantized input test pattern;a test pattern insertion circuit for inserting an output signal of said input pattern generator into a channel to be tested; andan encoder for encoding an output signal of said test pattern insertion circuit with high efficiency; anda receiving side DCME including:a decoder for decoding a received signal from said channel to be tested;a linear converting section for converting said decoded signal to a linear quantized PCM signal;an adder for adding a predetermined offset value to an output value of said linear converting section;a sign extracting section for extracting a sign from an output signal of said adder;a delay unit for delaying the extracted sign by a predetermined time;an exclusive OR arithmetic unit for performing an exclusive OR operation of said extracted sign and an output signal of said delay unit;a counter for counting the number of times of conformity in which an output value of said exclusive OR arithmetic unit is in conformity with a predetermined value; anda comparator for comparing a counted value of said counter and a predetermined threshold value and outputting judged results.