Patent ID: 6177838
Filing Date: 2001-01-23
Classification: H03F

Abstract:
A gain enhanced cascoded CMOS amplifier comprising:a first folding point gain enhanced transistor means connected between a first folding point node and a first amplifier output terminal, said first folding point node being coupled to a first power supply terminal;a first output coupling circuit coupling said first amplifier output terminal to a second power supply terminal;a first input transistor having a gate responsive to a first input voltage, a source, and a drain, said first input transistor having particular physical dimensions; anda first pole-isolating transistor having a drain connected to said first folding point node, a source connected to said drain of said first input transistor, and a gate responsive to an isolation bias voltage, said first pole isolating transistor having smaller physical dimensions than said particular physical dimensions of said first input transistor, wherein capacitive loading at said first folding point node is minimized to provide optimal settling behavior and stability in operation of said amplifier.