Patent ID: 6173300
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A circuit for determining a position of a leading logical one in a first n bit operand, the circuit comprising:a first circuit coupled to receive the first n bit operand and configured to generate a second n bit operand as a function of the first n bit operand;a second circuit coupled to receive the second n bit operand and configured to generate a third n bit operand as a function of the second n bit operand, wherein the third n bit operand represents a logical complement of the second n bit operand;a third circuit coupled to receive both the first and third n bit operands and configured to generate a fourth n bit operand as a function of the first and third n bit operands, wherein each bit of the fourth n bit operand represents a logical AND of corresponding bits of the first and third operands; anda fourth circuit coupled to receive the fourth n bit operand and configured to generate a k bit operand as a function of the fourth n bit operand, wherein the k bit operand represents the position of the leading one in the first n bit operand.