Patent ID: 8625370
Filing Date: 2014-01-07
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising: a first P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply; an input terminal connected to a gate terminal of the first P-type MOS transistor and gate terminals of the two or more N-type MOS transistors; an output terminal which is a connection node between the first P-type MOS transistor and one of the two or more N-type MOS transistors connected to the first P-type MOS transistor; one or more capacitors connected to the output terminal; the two or more N-type MOS transistors comprising a first N-type MOS transistor and a second N-type MOS transistor; a second P-type MOS transistor having a gate terminal connected to the input terminal; a source terminal of the second P-type MOS transistor connected to a connection node between the first N-type MOS transistor and the second N-type MOS transistor; and a drain terminal of the second P-type MOS transistor connected to the output terminal.