Patent ID: 9059091
Filing Date: 2015-06-16
Classification: H01L

Abstract:
1. A method for fabricating a transistor, comprising: forming a mask layer over a substrate; removing a polysilicon gate over a doped region of the substrate such that the doped region is exposed through a hole within the mask layer; covering the hole through which the doped region is exposed within the mask layer with a temporary layer; while the hole through which the doped region is exposed within the mask layer is covered with the temporary layer, depositing an interfacial layer on top and side surfaces of the mask layer and on a top surface of the doped region exposed through the hole, and depositing a layer on the interfacial layer adapted to one or more of: reducing a threshold voltage of the transistor and reducing a thickness of an inversion layer of the transistor; removing the temporary layer; forming a conductive plug within the hole of the mask layer, wherein the interfacial layer, the layer on the interfacial layer, and the conductive plug together are a replacement gate of the transistor.