Patent ID: 9034756
Filing Date: 2015-05-19
Classification: H01L

Abstract:
1. A method for forming an integrated circuit interconnect structure comprising: forming a first dielectric layer on a substrate; patterning the first dielectric layer to form an opening in the first dielectric layer; filling the opening and covering the first dielectric layer with a metal; patterning the metal to form interconnect features having first portions surrounded by the first dielectric layer and second portions extending across a major surface of the first dielectric layer; annealing the interconnect features, the annealing forming a barrier on the surface of the interconnect features, wherein at least a portion of the barrier is disposed between the first dielectric layer and a surface of the interconnect feature disposed within the first dielectric layer; and depositing a second dielectric material on the first dielectric layer and around the second portions of the interconnect features.