Patent ID: 7242056
Filing Date: 2007-07-10
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a semiconductor layer having a major surface formed along a plane; a first doped region of a first conductivity type in a first area of the surface; multiple layers over the first doped region, wherein the multiple layers define a window therein extending to the first doped region; a second doped region of a second conductivity type in the window; a third doped region of the first conductivity type over the second doped region; a gate oxide adjacent the second doped region; a first conductive layer comprising first and second laterally disposed regions, wherein the first region is adjacent the gate oxide, and wherein the second region is spaced apart from the gate oxide in a second area of the surface; a first dielectric layer overlying and in contact with the second region; a second conductive layer over the first dielectric layer; an insulator interposed between the first and the second regions of the first conductive layer so as to electrically isolate the first and the second regions; and wherein the first region, the second region, and the second conductive layer are electrically independent.