Patent ID: 8076957
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A semiconductor integrated circuit comprising: a first logic circuit including a first transistor and a first output node; a first impurity region of the first transistor coupled to the first output node; a second logic circuit including a second transistor and a second output node, the second logic circuit being disposed adjacent to the first logic circuit along the X axis; a second impurity region of the second transistor coupled to the second output node; a third logic circuit including a third transistor and a third output node, the third logic circuit being disposed adjacent to the second logic circuit along the Y axis orthogonal to the X axis; a third impurity region of the third transistor coupled to the third output node; a fourth logic circuit including a fourth transistor and a fourth output node, the fourth logic circuit being disposed adjacent to the third logic circuit along the X axis and disposed adjacent to the first logic circuit along the Y axis, and a fourth impurity region of the fourth transistor coupled to the fourth output node, wherein a first output signal is transmitted from the first output node to the second logic circuit, wherein a second output signal is transmitted from the second output node to the third logic circuit, wherein a third output signal is transmitted from the third output node to the fourth logic circuit, wherein a fourth output signal is transmitted from the fourth output node, wherein the first to fourth transistors share a well, wherein the first output signal and the second output signal have phases opposite to each other, wherein the second output signal and the third output signal have phases opposite to each other, and wherein the third output signal and the fourth output signal have phases opposite to each other.