Patent ID: 9063518
Filing Date: 2015-06-23
Classification: G04F

Abstract:
1. A method for the conversion of a time interval to a digital word, wherein the time interval, whose both start and end are detected by the use of a control module (CM), is mapped to a portion of electric charge proportional to the time interval, while the portion of electric charge is delivered during the time interval by the use of a current source (I) and is accumulated in an array (A) of capacitors (C n-1 , C n-2 , . . . , C 1 , C 0 ) whereas a capacitance value of a capacitor of a given index (C i ) is twice as high as a capacitance value of the capacitor of a previous index (C i-1 ) and charge accumulation is started from the capacitor (C n-1 ) having the highest capacitance value in the array (A) of capacitors and is realized from the start of the time interval to the end of the time interval detected by means of the control module (CM) or until the voltage (U n-1 ), which increases on the capacitor (C n-1 ) and is simultaneously observed by the use of the second comparator (K 2 ), equals the reference voltage (U L ) value, and in the latter case the charge accumulation is continued in the subsequent capacitor in the array (A) of capacitors whose capacitance value is twice lower than the capacitance value of the capacitor in which charge was accumulated directly before, and at the same time the voltage, increasing on the capacitor in which charge is currently accumulated, is compared to the reference voltage (U L ) value by the use of the second comparator (K 2 ), and the cycle is repeated until the end of the time interval is detected by means of the control module (CM), and afterwards, a function of the source capacitor (C i ), whose index is defined by the content of the source capacitor (C i ) index register in the control module (CM), is assigned by means of the control module (CM) to a capacitor (C x ) in the array (A) of capacitors by writing the value of the index of the capacitor (C x ) to the source capacitor (C i ) index register where the capacitor (C x ) is the last capacitor in which charge was accumulated, a function of the destination capacitor (C k ) whose index is defined by the content of the destination capacitor (C k ) index register in the control module (CM) is assigned by means of the control module (CM) to the subsequent capacitor in the array (A) whose capacitance value is twice lower than the capacitance value of the source capacitor (C i ) by writing a value stored in the source capacitor (C i ) index register reduced by one to the destination capacitor (C k ) index register, and then, the electric charge accumulated in the source capacitor (C i ) is transferred to the destination capacitor (C k ) by the use of the current source (I) and at the same time a voltage (U k ) increasing on the destination capacitor (C k ) is compared to the reference voltage (U L ) value by the use the second comparator (K 2 ), and also a voltage (U i ) on the source capacitor (C i ) is observed by the use of the first comparator (K 1 ), and when the voltage (U i ) on the source capacitor (C i ) observed by the use of the first comparator (K 1 ) equals zero during the charge transfer, the function of the source capacitor (C i ) is assigned to the current destination capacitor (C k ) by means of the control module (CM) on the basis of an output signal of the first comparator (K 1 ) by writing a current content of the destination capacitor (C k ) index register in the control module (CM) to the source capacitor (C i ) index register in the control module (CM), and also the function of the destination capacitor (C k ) is assigned to the subsequent capacitor in the array (A) whose capacitance value is twice lower than the capacitance value of the capacitor that operated as the destination capacitor directly before by reducing the content of the destination capacitor (C k ) index register by one, and charge transfer from a new source capacitor (C i ) to a new destination capacitor (C k ) is continued by the use of the current source (I), and when the voltage (U k ) on the destination capacitor (C k ) observed by the use of the second comparator (K 2 ) equals the reference voltage (U L ) value during the transfer of charge from the source capacitor (C i ) to the destination capacitor (C k ), the function of the destination capacitor (C k ) is assigned by means of the control module (CM) on the basis of an output signal of the second comparator (K 2 ) to the subsequent capacitor in the array (A) whose capacitance value is twice lower than the capacitance value of the capacitor that operated as the destination capacitor directly before by reducing the content of the destination capacitor (C k ) index register by one, and also the charge transfer from the source capacitor (C i ) to a new destination capacitor (C k ) is continued, while this process is still controlled by means of the control module (CM) on the basis of the output signals of the comparators (K 1 ) and (K 2 ) until the voltage (U i ) on the source capacitor (C i ) observed by the use of the first comparator (K 1 ) equals zero during a period in which the function of the destination capacitor (C k ) is assigned to the capacitor (C 0 ) having the lowest capacitance value in the array (A) of capacitors, or the voltage (U 0 ) increasing on the capacitor (C 0 ) and observed at the same time by the use of the second comparator (K 2 ) equals the reference voltage (U L ) value while the value one is assigned to these bits in the digital word, corresponding to the capacitors in the array (A) of capacitors, on which the voltage equal to the reference voltage (U L ) value has been obtained, and the value zero is assigned to the other bits by means of the control module (CM).