Patent ID: 6310799
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A negative resistance device comprising:a semiconductor structure comprising a semiconductor region of one conductivity type termed the bulk, a semiconductor region of second conductivity type termed the source wholly or partially contained in the bulk, a semiconductor region of second conductivity type termed the drain wholly or partially contained in the bulk, and a gate over at least part of the bulk and being insulated from the bulk;a bias means comprising means for biasing the structure to exhibit negative resistance characteristics, in whichthe source and the gate are each held at a fixed applied potential with respect to a bulk initial bias, and the gate to source applied potential difference is not greater than the threshold voltage of the structure;the drain is held at a fixed applied potential which is of greater magnitude than both the gate applied potential and the source applied potential; anda variable bias potential is applied to the bulk so that as it is swept towards the source applied potential the bulk current exhibits a negative resistance characteristic.