Patent ID: 9076815
Filing Date: 2015-07-07
Classification: H01L

Abstract:
1. A method of forming a transistor structure comprising: forming a gate structure above an active region of a semiconductor layer, forming a first spacer element on the sidewalls of said gate structure, said first spacer element having an internal stress; forming an intermediate spacer layer on said first spacer element; forming a second spacer element on said intermediate spacer element, said second spacer element having an internal stress; forming a metal silicide layer that has an interface with said semiconductor layer; removing a portion of said second spacer element after forming said metal silicide layer, wherein said second spacer element is only partially removed so as to leave a residual portion of said second spacer element; and performing an ion implantation in order to relax the internal stress in said residual portion of said second spacer element and said first spacer element.