Patent ID: 7898831
Filing Date: 2011-03-01
Classification: H01L,H02M,H03K

Abstract:
1. A circuit for limiting the maximum drain-source voltage (VDS) of the main switching FETs of a transformer-coupled push pull power conversion circuit with a maximum DC supply voltage V IN max ,the maximum VDS being accentuated by the leakage inductances of the push pull transformer and the power conversion circuit traces, the circuit for limiting maximum VDS comprises a circuit bridging in the drains of the main switchin FETs wherein the bridging circuit further comprises a series connection of two opposing Zener diodes each having a Zener voltage of Vzx and wherein, to insure full operational voltage range, said Vzx is selected to be slightly ≧2*V IN MAX whereby clamps the maximum VDS to a value of about V IN MAX +½ Vzx.