Patent ID: 6868015
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type, first and second spaced-apart terminals in the substrate of a second conductivity tupe, with a channel region therebetween; a first insulation layer disposed over said substrate; an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal; a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and an electrically conductive control gate having a first portion and a second portion, the first portion being substantially rectangularly shaped and positioned immediately adjacent to the second insulation layer, the second portion being substantially a spacer connected to the first portion and disposed over the floating gate and insulated therefrom.