Patent ID: 7672803
Filing Date: 2010-03-02
Classification: G01R,G11C

Abstract:
1. A system for providing programmable test conditions for a built-in self test circuit of a memory device, the system comprising: a flash memory; a BIST interface circuit adapted to receive one or more global variables associated with the test conditions of a plurality of memory tests used on the flash memory and to output results of the memory tests based on the value of the variables, wherein the global variables are shared between the plurality of memory tests; and wherein the global variables comprise one or more of: wherein test conditions associated with the global variables comprise: wherein the BIST interface circuit is adapted to adjust one or more test conditions of the shared global variables based on one or more earlier test results and use the adjusted one or more test conditions in an additional test; and a BIST circuit adapted to test operations of the flash memory based on the value of the variables programmed into the test conditions and to report results of the memory tests.