Patent ID: 7888211
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A method comprising: preparing a semiconductor substrate including a cell area and a peripheral area; forming a device isolation layer in the semiconductor substrate; forming a first well in the cell area of the semiconductor substrate and forming an oxide-nitride-oxide layer over the cell area of the semiconductor substrate having the device isolation layer; forming a second well in the peripheral area of the semiconductor substrate and forming a first oxide layer over the peripheral area of the semiconductor substrate; forming a first polysilicon layer over the oxide-nitride-oxide layer and the first oxide layer and performing a first etch process to form a memory gate including an oxide-nitride-oxide layer pattern and a first polysilicon pattern in the cell area; forming a second oxide layer pattern and a second polysilicon pattern over a first sidewall of the memory gate and forming a gate in the peripheral area; performing a third etch process on the semiconductor substrate so that the second oxide layer pattern and the second polysilicon pattern remain over only the first sidewall of the memory gate to form a select gate; and forming a first impurity area being a source area in the semiconductor substrate between the memory gates adjacent to each other using a photoresist pattern used in the third etch process.