Patent ID: 8935585
Filing Date: 2015-01-13
Classification: G01R

Abstract:
1. A test access port formed in an integrated circuit on a substrate, comprising: A. a test access port controller having a test mode select input, a test clock input, an enable input, and control outputs; B. a multiplexer having a test data output, a first input, and a second input; C. a data register having control inputs connected to the control outputs of the controller, a test data input and a test data output, the test data output being coupled to the first input of the multiplexer; D. an instruction register having control inputs connected to the control outputs of the controller, a test data input coupled to the test data input of the data registers, and a test data output coupled to the second input of the multiplexer; and E. a scan cell separate from the instruction register connected in series with the instruction register between the second input of the multiplexer and the test data input of the data register, the scan cell having a control input connected to the control inputs of the instruction register.