Patent ID: 6934816
Filing Date: 2005-08-23
Classification: G11C

Abstract:
1. In an integrated circuit memory device comprising a memory array having first and second ports that can each support asynchronous read and write access and a pulsed sense amplifier that receives data from the second port, a method of operating the memory device, comprising the steps of: writing first data from a data input buffer coupled to the first port to a write address in the memory array while simultaneously writing a copy of the first data to a bypass latch associated with the second port; reading second data from a read address in the memory array by activating the pulsed sense amplifier to latch the second data; and overwriting the latched second data with the copy of the first data from the bypass latch; wherein said writing step comprises overwriting old data at the write address with new data; wherein the read address equals the write address; and wherein the second data latched by the pulsed sense amplifier during said reading step is the new data.