Patent ID: 6240482
Filing Date: 2001-05-29
Classification: H04Q

Abstract:
An integrated circuit comprising:a circuit unit operable in a plurality of modes, wherein each mode corresponds to a different function of the integrated circuit, and in each mode, the circuit unit uses a first range of internal addresses to access a page in a first section of a memory; anda plurality of register sets, each register set corresponding to one of the plurality of modes and being accessible by the circuit unit when the circuit unit operates in the mode corresponding to the register set, wherein:the plurality of register sets includes a first register set that the circuit unit can access when operating in a first mode and a second register set that the circuit unit can access when operating in a second mode;the first register set includes a first register that identifies a page in the first section that the circuit unit accesses using the first range of addresses when the circuit unit operates in the first mode; andthe second register set includes a second register that identifies a page in the first section that the circuit unit accesses using the first range of addresses when the circuit unit operates in the second mode.