Patent ID: 6295595
Filing Date: 2001-09-25
Classification: G11C

Abstract:
A memory circuit having an address bus and a data bus, the memory circuit comprising:a memory array;an address decoder coupled to the memory array;a data tranceiver coupled to the memory array and the data bus; andan address mapping circuit coupled to the address bus and coupled to the address decoder by an internal address bus, wherein the memory address mapping circuit comprises:a first multiplexer having a first select terminal, a second select terminal, a first input terminal coupled to a first address line of the address bus and an output terminal coupled to a first internal address line of the internal address bus; anda second multiplexer having a first select terminal, a second select terminal, a first input terminal coupled to a second address line of the address bus, a second input terminal coupled to the first address line of the address bus, and an output terminal coupled to a second internal address line of the internal address bus.