Patent ID: 6502083
Filing Date: 2002-12-31
Classification: G06K,G06N

Abstract:
An integrated circuit neuron having a dual structure comprising:a data bus (DATA-BUS) which transports prototype vector components; an input bus (INPUT-BUS) which transports an actual influence field (AIF) and lower and upper limits thereof (MaxIF/MinIF), a category, a distance and norm/context data; a feed back bus (OR-BUS) which transports feed back signals; R/W memory means, connected to said data bus, for storing the prototype vector components as soon the neuron is engaged during a learning phase; computation means, connected to said data bus and input bus and to register means, for performing computation including calculating the distance between an input vector and the stored prototype to generate a distance signal, performing comparisons between data stored in said register means or present on said buses, and performing addition/subtraction operations on said data; register means for storing data transported on said buses or generated by said computation means; evaluation means for determining at least one of maximum value data or minimum value data stored in said register means, data stored in said R/W memory means, and data present on said buses, said memory means, register means, and evaluation means being arranged in two substantially equal structures; daisy chain means, connected to corresponding daisy chain means of two adjacent neurons when said integrated circuit neuron is part of an artificial neural network (ANN), for differentiating between different possible states of said integrated circuit neuron (free, first free and engaged); and logic control means for controlling said neuron, said neuron operating as one of a single neuron (single mode) and two independent neurons characterized as even and odd neurons (dual mode), said logic control means adapted for inhibiting the odd neuron.