Patent ID: 6256654
Filing Date: 2001-07-03
Classification: G06F

Abstract:
A signal processor comprising:a first adder configured to add a first previous sample and a second previous sample of an input signal to generate a sum value in each of a plurality of time intervals;a second adder configured to subtract the first previous sample and the second previous sample of the input signal to generate a difference value in each of the plurality of time intervals;a first linear combinative circuit configured to receive the sum value and the difference value, and to form a first linear combination of the sum value and the difference value in each of the plurality of time intervals;a second linear combinative circuit configured to receive the sum value and the difference value, and to form a second linear combination of the sum value and the difference value in each of the plurality of time intervals;a delay unit configured to receive the second linear combination value, and to delay the second linear combination for an amount of time equal to one of the plurality of time intervals;a third adder configured (a) to receive the first linear combination corresponding to a current one of the plurality of time intervals, (b) to receive the second linear combination corresponding to a previous one of the plurality of time intervals from the delay unit, (c) to add the current first linear combination and the previous second linear combination to generate a first output signal sample.