Patent ID: 8938628
Filing Date: 2015-01-20
Classification: G06F

Abstract:
1. A method for applying initial power-up power to a synchronous, high gate count, very large scale integrated circuit (VLSI) device such as an Application Specific Integrated Circuit (ASIC) or Field-Programmable Gate Array (FPGA), said VLSI circuit being synchronous in that every flip-flop within the circuit switches on the same clock, said VLSI circuit having a number of physical blocks geographically dispersed across the device, wherein one or more of the physical blocks produce different power transient characteristics from one another and include data paths which operate on the same clock, the method comprising the steps of: a) applying a power signal to each of the physical blocks while preventing the application of a system clock to each of the physical blocks; and b) selectively enabling the system clock to individual one(s) of the physical blocks by c) wherein the selective enabling of the system clock to individual one(s) of the physical blocks is done under software control; such that the physical blocks emerge from a reset state on a common clock edge.