Patent ID: 6212106
Filing Date: 2001-04-03
Classification: G06F,G11C,Y02D

Abstract:
A multi-bit match detection circuit, comprising:multiple comparison units which compare multiple complementary read signals read out from memory cells with corresponding multiple-bit data signals, which are the object of comparison bit by bit, and output complementary detection signals which indicate match/mismatch of every compared pair;multiple amplifier units each provided at each comparison unit, which start operation when a control signals for controlling operation is applied, and generate output signals indicating match/mismatch of said every compared pair by amplifying said detection signals to the predetermined logic level, wherein said multiple amplifier units are divided into two or more groups, and when said output signals indicating match of the corresponding bits are output from every first amplifier unit of every amplifier unit group, rest of the amplifier units in every amplifier unit group start operation at a time, and;a decision unit which decides if said multiple read signals and said multiple data signals match based on the output signals generated by said multiple amplifier units.