Patent ID: 9218887
Filing Date: 2015-12-22
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array configured to store data; peripheral circuits configured to perform a program verifying operation, a read operation, and an erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the peripheral circuits are configured to apply a first bit line voltage to bit lines when a read voltage is applied to a word line of selected memory cells in the read operation, apply a second bit line voltage to the bit lines when a first verifying voltage is applied to the word line in the program verifying operation, and apply a third bit line voltage to the bit lines when a second verifying voltage is applied to the word line in the erase verifying operation, wherein the second bit line voltage is higher than the first bit line voltage and the third bit line voltage is lower than the first bit line voltage, wherein the second bit line voltage is set to have a higher level than the first bit line voltage based on retention characteristics of the memory cells in the semiconductor memory device, and the third bit line voltage is set to have a lower level than the first bit line voltage based on disturb characteristics of the memory cells in the semiconductor memory device.