Patent ID: 7969781
Filing Date: 2011-06-28
Classification: G06F

Abstract:
1. A method of controlling a memory system including a plurality of blocks each having a first block size, the method comprising: receiving data with a logical block address (LBA) having a second block size, the second block size being smaller than the first block size; determining whether the LBA is consecutive to an LBA of a last written data stored in a block, the block being currently used for data write; when the LBA is consecutive to the LBA of the last written data, writing the data in an empty area of the block; determining whether the LBA is included in a logical address range of the first block size, the logical address range being determined by aligning the LBA of the last written data to the first block size; when the LBA is included in the logical address range, writing the data in the empty area of the block, and when the LBA is not included in the logical address range, assigning a new block and writing the data to an empty area of the new block.