Patent ID: 7248663
Filing Date: 2007-07-24
Classification: G06F

Abstract:
1. An apparatus for transforming data transmission speed, comprising: a transmission speed transforming circuit that receives data of a first transmission speed, through a first frame synchronizing signal of a first data bus of the first transmission speed, by synchronizing a first clock with a first reference clock of the first data bus; and a Dual Port Random Access Memory (DPRAM) coupled to receive and store the data from the transmission speed transforming circuit, wherein the transmission speed transforming circuit to read the stored data from the DPRAM and transmit the data with a second transmission speed, through a second frame synchronizing signal of a second data bus of the second transmission speed, by synchronizing a second clock with a second reference clock of the second data bus, wherein the transmission speed transforming circuit comprises: a data reception circuit that receives data of the first transmission speed through the first frame synchronizing signal by synchronizing the first clock of that data reception circuit with the first reference clock; a data transmission circuit that transmits data of the second transmission speed through the second frame synchronizing signal by synchronizing the second clock of the data transmission circuit with the second reference clock; an address control circuit that generates a control signal in order to write the data of the first transmission speed in the DPRAM and read the data of the second transmission speed from the DPRAM; a reception address generation circuit that generates addresses for writing the data of the first transmission speed in the DPRAM according to the control signal of the address control circuit; a reception data generation circuit that transforms the data of the first transmission speed into data to be written in the DPRAM; a transmission address generation circuit that generates addresses for reading the data of the second transmission speed from the DPRAM according to the control signal of the address control circuit; and a transmission data generation circuit that transforms the data of the second transmission speed into data to be transmitted by the data transmission circuit.