Patent ID: 8472231
Filing Date: 2013-06-25
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a memory unit comprising: wherein the first to fourth wirings are parallel to one another, wherein the first wiring and the fifth wiring are orthogonal to each other, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein the third memory cell comprises a fifth transistor, a sixth transistor, and a third capacitor, wherein the fourth memory cell comprises a seventh transistor, an eighth transistor, and a fourth capacitor, wherein a drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor, wherein a drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the second capacitor, wherein a drain of the fifth transistor is electrically connected to a gate of the sixth transistor and one electrode of the third capacitor, wherein a drain of the seventh transistor is electrically connected to a gate of the eighth transistor and one electrode of the fourth capacitor, wherein a gate of the fifth transistor is electrically connected to the first wiring, wherein a gate of the first transistor and the other electrode of the third capacitor are electrically connected to the second wiring, wherein the other electrode of the first capacitor and a gate of the seventh transistor are electrically connected to the third wiring, wherein a gate of the third transistor and the other electrode of the fourth capacitor are electrically connected to the fourth wiring, wherein the drain of the first transistor is electrically connected to a source of the third transistor, wherein a drain of the second transistor is electrically connected to a source of the fourth transistor, wherein the drain of the fifth transistor is electrically connected to a source of the seventh transistor, wherein a drain of the sixth transistor is electrically connected to a source of the eighth transistor, wherein the first transistor, the third transistor, the fifth transistor, and the seventh transistor have the same conductivity type, wherein the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor have the same conductivity type, and wherein the conductivity type of the first transistor is different from the conductivity type of the second transistor.