Patent ID: 7129754
Filing Date: 2006-10-31
Classification: H03K

Abstract:
1. A dynamic logic circuit comprising: a dynamic node receiving a bias current from a source of current having a first node coupled to a first voltage potential of a power supply and a second node for setting a level of the bias current in response to a voltage level of a load control signal; a logic tree coupling the dynamic node to a common node in response to a Boolean logic combination of a plurality of logic input signals; an electronic switch coupling the common node to a second voltage potential of the power supply during a first logic state of a clock signal and decoupling the common node from the second voltage potential of the power supply during a second logic state of the clock signal; and a static logic circuit having an input coupled to the dynamic node and a first output node generating a logic value of the dynamic node during the first logic state of the clock signal and maintaining the logic value of the dynamic node during the second logic state of the clock signal, wherein a duration of the first logic state of the clock signal is less than a duration of the second logic state of the clock signal, and wherein the duration of the first logic state of the clock signal is selected such that a leakage from the dynamic node does not affect an evaluation of the dynamic node.