Patent ID: 6353269
Filing Date: 2002-03-05
Classification: H01L

Abstract:
An embedded DRAM circuit with a logic circuit comprising the steps of:a semiconductor substrate having a logic region and a memory region having device areas, said logic region having salicide FETs; a planar first insulating layer on said substrate; first openings in said planar first insulating layer for contacts to said salicide FETs and openings in said first insulating layer for bit-line contacts and capacitor node contacts in said memory regions; metal plugs in said openings; a patterned first metal layer serving as a first level of metal interconnections including bit lines for said DRAM circuit; a planar second insulating layer having second openings over and to said capacitor node contacts, and via holes for said salicide FETs, and metal bottom electrodes in said second openings coplanar with metal contacts in said via holes; an interelectrode dielectric layer over said capacitor bottom electrodes; a patterned second metal layer serving as a second level of interconnections and as capacitor top electrodes, said top electrodes coplanar with said second level of interconnections.