Patent ID: 6673714
Filing Date: 2004-01-06
Classification: H01L,Y10S

Abstract:
A method of fabricating a sub-lithographic sized via, comprising:depositing a first polymer layer on a surface of an underlying layer, the first polymer layer including a first etch rate, and the underlying layer is an electrically conductive material; depositing a second polymer layer on the first polymer layer, the second polymer layer is photo active and includes a second etch rate, and wherein the first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched; patterning the second polymer layer to define an etch mask therein, the etch mask including a feature size that is within a lithography limit of a lithographic system used for the patterning; anisotropically etching the first polymer layer to remove all portions of the first polymer layer that are not covered by the etch mask; isotropically etching the first polymer layer and the etch mask such that the first polymer layer dissolves in a substantially lateral direction at a faster rate than the etch mask, the first polymer layer receding along the surface of the underlying layer defining an exposed surface thereon and receding along the etch mask defining an undercut portion thereon, and continuing the etching until the first polymer layer has dissolved to a sub-lithographic feature size that is less than the lithography limit; depositing a dielectric layer on the exposed portion of the underlying layer and substantially all of the etch mask except the undercut portion, the dielectric layer forming a via sidewall positioned adjacent to the first polymer layer; and lifting-off the first polymer layer and the etch mask to define a via including a minimum feature size that is substantially equal to the sub-lithographic feature size.