Patent ID: 9047432
Filing Date: 2015-06-02
Classification: G06F

Abstract:
1. A system, comprising: a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die; at least one non-transitory machine readable storage medium, including a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool, wherein the second gate level description includes connections between the first and second circuit patterns and power and ground ports, and the first gate level description includes connections between the first and second circuit patterns, except that the first gate level description does not include power and ground port connection patterns for the first and second circuit patterns; a processor-implemented first verification module for comparing portions of the first gate level description to corresponding portions of the second gate level description excluding power and ground port connection patterns for the first and second circuit patterns and outputting a verified second gate-level description of the first and second circuit patterns in which the portions of the second gate-level description match corresponding portions of the first gate-level description.