Patent ID: 8125256
Filing Date: 2012-02-28
Classification: H03H,H03K,H03L

Abstract:
1. A bias generator for biasing delay elements in a delay line employing one or more delay elements, said bias generator comprising: a bias generator variable resistance load element, said bias generator variable resistance load element connected between a power supply voltage and a given node; a voltage-controlled current source for generating a reference current; a current mirror formed of a first side and a second side, said first side connected to said voltage-controlled current source so that current in said first side and current in said second side is established based on said reference current; a reference voltage generator for generating a reference voltage; and an operational amplifier with: a non-inverting input connected to said given node; an inverting input connected to said reference voltage generator to receive said reference voltage; and an output connected to control current in said bias generator variable resistance load element, wherein said operational amplifier adjusts said output to minimize a difference between voltage levels at said non-inverting input and said inverting input; and an intermediate field effect transistor (FET), having a drain connected to said given node and a gate connected to said power supply voltage, configured so that a current through said intermediate FET includes said current in said second side of said current mirror.