Patent ID: 8074096
Filing Date: 2011-12-06
Classification: G06F

Abstract:
1. A semiconductor integrated circuit comprising: a control terminal coupled to a memory through a control bus; a data terminal coupled to the memory through a data bus; a memory controller coupled to the control terminal and the data terminal; and a first master and a second master coupled to the memory controller; wherein the memory controller supplies a control signal corresponding to a memory access based on the first master in synchronism with one of a rising edge and a falling edge of a clock signal and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with the other of the rising edge and the falling edge of the clock signal, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with one of the rising edge and the falling edge of the clock signal.