Patent ID: 8406364
Filing Date: 2013-03-26
Classification: H03L

Abstract:
1. A fractional frequency divider PLL device comprising: a ΣΔ modulator that outputs pseudo random numbers that are a 0 value, positive integer values, or negative integer values, a mean value of the pseudo random numbers being a predetermined fractional value, a three-modulus prescaler which has a set frequency division value, a first frequency division value obtained by decreasing the set frequency division value by N and a second frequency division value obtained by increasing the set frequency division value by N; a first counter which counts a first cycles of an output signal of the three-modulus prescaler and which outputs a fractional frequency division signal, a second counter which counts a second cycles of the output signal of the three-modulus prescaler which is smaller in number than the first cycles; and a control counter which counts cycles of the output signal of the three-modulus prescaler to a target count value which is an absolute numerical value of an output pseudo random number of the pseudo random numbers, in a period of time which is counted by the first counter and is not counted by the second counter, wherein the target count value is smaller in number than a value of the first cycles and an additional value of the first cycles to the target count value is smaller in number than the value of the first cycles, wherein the three-modulus prescaler outputs the first frequency division value when the output pseudo random number of the pseudo random numbers is a negative value and the second frequency division value when the output pseudo random number of the pseudo random numbers is a positive value, during a period of time until the control counter counts up the cycles to the target count value.