Patent ID: 6240008
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A DRAM system, said system comprising:a first capacitor coupled to a first word line (WL), said first capacitor further coupled via a first pass gate to a first bit line (BL);a second capacitor coupled to a second WL neighboring said first WL, said second capacitor further coupled via a second pass gate to a second BL neighboring said first BL, wherein said first capacitor and said second capacitor adapted to store complementary data bits for ensuring a `zero` being stored in one of said first capacitor or said second capacitor and for ensuring a voltage level `zero` being maintained on one of said first and said second BL's; anda sense amplifier (SA) operable in a differential sensing mode and a conventional sensing mode, said SA coupled to said first BL and second BL, wherein in said differential sensing mode said SA adapted to amplify a `zero` and a `one` unequally.