Patent ID: 7109088
Filing Date: 2006-09-19
Classification: H01L

Abstract:
1. A method of fabricating a mixed-signal integrated circuit having a metal-insulator-metal or polysilicon-insulator-polysilicon capacitor, the method comprising: forming a first interlayer dielectric film over said capacitor by a plasma deposition process, said first interlayer dielectric film having at least one contact hole extending to said capacitor; forming a first interconnecting line over said first interlayer dielectric film, said first interconnecting line being electrically connected to said capacitor through said at least one contact hole; forming a second interlayer dielectric film over said first interconnecting line, said second interlayer dielectric film having at least two first via holes extending to said first interconnecting line; and forming a second interconnecting line over said second interlayer dielectric film, said second interconnecting line being electrically connected to said first interconnecting line through said first via holes.