Patent ID: 6229329
Filing Date: 2001-05-08
Classification: G01R

Abstract:
A method of testing semiconductor integrated circuits by using a probe card comprising:a plurality of probe terminals placed opposite a plurality of testing electrodes of a plurality of semiconductor integrated circuit elements formed on a single wafer, respectively;a common voltage supply line for supplying a voltage to each of the plurality of probe terminals; anda plurality of positive temperature coefficient (PTC) elements placed between the common voltage supply line and the plurality of probe terminals,the method comprising the steps of:simultaneously testing the plurality of semiconductor integrated circuit elements by bringing the plurality of probe terminals into contact with the testing electrodes of the plurality of semiconductor integrated circuit elements, respectively, and applying a voltage to each of the testing electrodes from the common voltage supply line via the plurality of PTC elements; andpreventing voltage application to the testing electrode of a defective one out of the plurality of semiconductor integrated circuit elements which allows excessive currents to flow thereinto, because of an increase in resistance of one of the PTC elements electrically connected with the defective semiconductor integrated circuit element, which follows a temperature increase thereof caused by the excessive current-flow into the defective semiconductor integrated circuit element.