Patent ID: 8283210
Filing Date: 2012-10-09
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a base material having an upper surface quadrilateral in planar shape, a plurality of first bonding leads formed along a first board side of the upper surface, a plurality of second bonding leads formed along a second board side opposed to the first board side, and a lower surface opposite to the upper surface; (b) after the step (a), arranging a first semiconductor chip having a first front surface quadrilateral in planar shape, a plurality of first bonding pads formed along a first chip side of the first front surface, and a first back surface opposite to the first front surface over the upper surface of the base material so that the distance between the first chip side and the first board side is smaller than the distance between the first chip side and the second board side in a plan view; (c) arranging a second semiconductor chip having a second front surface quadrilateral in planar shape, a plurality of second bonding pads formed along a second chip side of the second front surface, and a second back surface opposite to the second front surface over the first semiconductor chip such that the distance between the second chip side and the first board side is smaller than the distance between the second chip side and the second board side in the plan view and the first bonding pads are exposed from the second semiconductor chip; (d) respectively electrically coupling the first bonding leads to the first bonding pads via a plurality of first wires; (e) respectively electrically coupling the first bonding pads to the second bonding pads via a plurality of second wires; (f) after the step (e), arranging a third semiconductor chip having a third front surface quadrilateral in planar shape, a plurality of third bonding pads formed along a third chip side of the third front surface, and a third back surface opposite to the third front surface over the second semiconductor chip such that the distance between the third chip side and the second board side is shorter than the distance between the third chip side and the first board side in the plan view and the second bonding pads are exposed from the third semiconductor chip; (g) arranging a fourth semiconductor chip having a fourth front surface quadrilateral in planar shape, a plurality of fourth bonding pads formed along a fourth chip side of the fourth front surface, and a fourth back surface opposite to the fourth front surface over the third semiconductor chip so that the distance between the fourth chip side and the second board side is smaller than the distance between the fourth chip side and the first board side in the plan view, substantially the entire surface of the second semiconductor chip is covered with the fourth semiconductor chip in the plan view, and the third bonding pads are exposed from the fourth semiconductor chip; (h) respectively electrically coupling the second bonding leads to the third bonding pads via a plurality of third wires; and (i) respectively electrically coupling the third bonding pads to the fourth bonding pads via a plurality of fourth wires; the step (d) including the steps of: (j1) forming a first bump electrode in one of the first bonding pads; (j2) after the step (j1), joining a ball portion of the first wire to one of the first bonding leads using a capillary; (j3) after the step (j2), joining part of the first wire to the front surface of the first bump electrode, wherein at the step (j1), the apical surface of the capillary is pressed against the front surface of the first bump electrode to form in the front surface of the first bump electrode an inclined plane whose height is reduced from the central part of the first front surface of the first semiconductor chip toward the first chip side, wherein at the step (j3), the part of the first wire is joined to the inclined plane, the step (e) including the steps of: (i1) forming a second bump electrode in one of the second bonding pads; (i2) after the step (i1), joining a ball portion of the second wire to the part of the first wire formed over one of the first bonding pads using the capillary; (i3) after the step (i2), joining part of the second wire to the front surface of the second bump electrode, wherein at the step (i1), the apical surface of the capillary is pressed against the front surface of the second bump electrode to form in the front surface of the second bump electrode an inclined plane whose height is reduced from the central part of the second front surface of the second semiconductor chip toward the second chip side, and wherein at the step (i3), the part of the second wire is joined to the inclined plane.