Patent ID: 6822509
Filing Date: 2004-11-23
Classification: H03F

Abstract:
A differential circuit with a linearity correction loop comprising:a main differential amplifier; a correction amplifier having a first input coupled to a first output of the main differential amplifier and to a first input node, and a second input coupled to a second output of the main differential amplifier and to a second input node; a first summing node having a first input coupled to the first input node, a second input coupled to a first output of the correction amplifier, and an output coupled to a first input of the main differential amplifier; a second summing node having a first input coupled to the second input node, a second input coupled to a second output of the correction amplifier, and an output coupled to a second input of the main differential amplifier; and wherein the first summing node comprises a first resistor coupled between the first input of the first summing node and the output of the first summing node, and a second resistor coupled between the second input of the first summing node and the output of the first summing node.