Patent ID: 6647465
Filing Date: 2003-11-11
Classification: G06F

Abstract:
A processor connected to at least one processor through a common bus, for executing cache control, comprising:a CPU; a cache memory; a tag memory connected to said cache memory, for holding address information of cache data; a resource for holding data common to said at least one processor; a write port provided to said resource and connected to said common bus; and a comparator for comparing address information of said tag memory with an access address from said CPU and outputting coincidence information to said cache memory, wherein a local bus for gaining access to said resource from said at least one processor is connected to a read port provided to said resource, wherein said cache memory has a write/read port connected to an internal bus from said CPU and a write port for accepting the common data from said at least one processor through an external bus connected to said common bus, and wherein said comparator includes: a first comparator connected to said tag memory, for comparing the access address from said CPU with the address information of said tag memory and giving an enable signal for activating said write/read port of said cache memory, and a second comparator connected to said tag memory, for comparing the access address from said at least one processor with the address information of said tag memory, and giving an enable signal for activating said write port of said cache memory.