Patent ID: 7313739
Filing Date: 2007-12-25
Classification: G01R,G11C

Abstract:
1. Apparatus comprising: a pipelined memory including multiple stages and a plurality of memory elements having addresses; a test module operative to perform a test on the plurality of memory elements by writing test data to the plurality of memory elements in the pipelined memory, redundantly writing said test data n−1times to the plurality of memory elements, and reading the test data from the plurality of memory elements; a first storage unit; a comparator to compare test output data that is output from the pipelined memory with data expected to be output from the pipelined memory to identify a failure of a memory element; logic to account for a timing latency that arises due to the multiple stages and identify an address of said memory element based on memory addresses of the test data input into the pipelined memory in response to receipt of a notification of the failure from the comparator; and a fail trace module operative to interrupt the test in response to the identification of the failure of a memory element and to store the identified address of said memory element in the storage unit thereby making the identified address available for output, where n is the number of pipeline stages.