Patent ID: 7339228
Filing Date: 2008-03-04
Classification: G11C,H01L

Abstract:
1. A method for fabricating a non-planar flash memory array, with shielded floating gates, comprising a plurality of memory cells, the method comprising: forming a mesa/valley structure, comprising a plurality of mesas and valleys, in a substrate; forming source/drain regions along sidewalls of the mesas between the tops of the mesas and the valleys; forming a gate insulator layer over the substrate; depositing a first polysilicon layer; etching the polysilicon to form a single floating gate in each valley and a single floating gate on top of each mesa; forming an intergate insulator layer over the floating gates; forming a second polysilicon layer over the integrate insulator and removing a portion of the second polysilicon layer to produce wordlines; and forming a metal layer between and substantially parallel to the wordlines to shield the floating gates.