Patent ID: 7509609
Filing Date: 2009-03-24
Classification: G06F

Abstract:
1. A method for reducing timing skew, the method comprising: identifying signal paths with rise and fall timing skews that are to be reduced to ensure timing requirements are met for correct signal operation, wherein the signal paths are identified from a chip database prior to routing the signals; inserting a serially coupled pair of signal inverting devices to compensate for unbalanced rise and fall timing skews in each identified signal path to form identified signal inverting paths, wherein the identified signal inverting paths include signal paths connected to and between the serially coupled pair of signal inverting devices; calculating the signal path distances for the identified signal inverting paths; finding, among the identified signal inverting paths, a longest signal path; lengthening selected signal paths of the remaining identified signal inverting paths to each have a length substantially equal to the longest signal path whereby delays of the identified signals are balanced and the rise and fall timing skews between the identified signal paths are reduced; placing in the signal path of each identified signal path a first signal inverting device close to the signal source of the identified signal, whereby the path connected from the signal source to the first signal inverting device is not selected for lengthening; placing in the signal path of each identified signal path a second signal inverting device midway in the signal path between the first signal inverting device and the receiving end of the signal path; and identifying the longest signal path among the signal paths connecting each first signal inverting device to its associated second signal inverting device and among the signal paths connecting each second signal inverting device to its associated receiving end of the signal path.