Patent ID: 7163861
Filing Date: 2007-01-16
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: a laminating step including forming tunnel insulating films, floating gates, dielectric films and control gates on first and second cell areas, the first and second cell areas being formed mutually adjacent to each other on a semiconductor substrate; and a plurality of impurity area formation steps to form sources and drains on the first and second cell areas, and to form an electric connection between one of the source and drain of the first cell area and one of the source and drain of the second cell area; wherein a connecting area is formed to have a lower electric resistance than impurity areas formed in one of the plurality of impurity area formation step; and wherein a groove is formed in the semiconductor substrate in the connecting area, and wherein the plurality of impurity area formation steps to form an electric connection between one of the source and drain of the first cell area and one of the source and drain of the second cell area includes implanting impurities from the plurality of impurity area formation steps into the semiconductor substrate under the groove.