Patent ID: 6574713
Filing Date: 2003-06-03
Classification: G06F

Abstract:
A method for scheduling memory operations into a program, said program executable in a device having a processor operatively coupled to a cache memory and to a main memory, said processor having a cache line size associated with memory operations, said method comprising:defining a threshold value; ascertaining a set of offsets corresponding to related memory operations in the program; sorting said set of offsets, said offsets including a maximum offset and a minimum offset, wherein said minimum offset initially defines the previously generated offset; creating a prefetch for the memory operation associated with the maximum offset in the set of offsets; creating a prefetch for the memory operation associated with the minimum offset in the set of offsets; and creating a prefetch for an offset within said set of offsets, other than said maximum offset and said minimum offset, which is not within the threshold value of the previously generated offset.