Patent ID: 8493132
Filing Date: 2013-07-23
Classification: G05F,G11C,H02M

Abstract:
1. A semiconductor device comprising: first and second internal voltage terminals supplied with first and second internal potentials, respectively, the first and second internal potentials being different from each other; a third internal voltage terminal supplied with a third internal potential; a Vss terminal supplied with a Vss potential; an output terminal: a voltage booster circuit coupled to the Vss terminal, the third internal voltage terminal and the output terminal, the voltage booster circuit boosting a potential difference between the third internal potential appearing at the third internal voltage terminal and the Vss potential at the Vss terminal to generate a boosted potential at the output terminal; and a switch circuit coupled to the first, second and third internal voltage terminals, the switch circuit connecting in a first switching state the first internal voltage terminal directly to the third internal voltage terminal so that the third internal voltage terminal receives the first internal potential as the third internal potential, and connecting in a second switching state the second internal voltage terminal directly to the third internal voltage terminal so that the third internal voltage terminal receives the second internal potential as the third internal potential.