Patent ID: 6165892
Filing Date: 2000-12-26
Classification: H01L,H05K

Abstract:
A method for forming a high density interconnect scheme on a common circuit base to connect a first integrated circuit to a second integrated circuit and/or to support components, said method comprising:(a) providing a common circuit base having first and second patterned conductive layers formed thereon and having an upper surface, said common circuit base also having at least one trench formed on said upper surface between raised features of said first conductive layer;(b) forming a first layer of a dielectric film over said common circuit base and over said raised features and said trenches;(c) patterning said first layer to remove portions of said first layer formed over said raised features;(d) forming a second layer of said dielectric film over said patterned first dielectric layer;(e) performing additional film deposition and film patterning steps to complete the layout of a thin film interconnect structure over said common circuit base; and(f) attaching an integrated circuit die to said common circuit base and electrically connecting said integrated circuit die to said thin film interconnect structure.