Patent ID: 7058740
Filing Date: 2006-06-06
Classification: G06F

Abstract:
1. An apparatus comprising: a bus arbiter coupled to first and second processors via first and second master buses, respectively, to generate an arbitration select signal based on result of arbitrating bus access information from the first and second processors; a first multiplexer coupled to the first and second master buses and a first slave bus in a plurality of slave buses to provide device access information selected from the bus access information using the arbitration select signal, the device access information being transferred to a first slave device connected to the first slave bus; a second multiplexer coupled to the first slave bus to provide bus response information from device response information using the device select signal; and a de-multiplexer coupled to the second multiplexer and the first and second master buses to transfer the bus response information to one of the first and second processors using the arbitration select signal.