Patent ID: 7902887
Filing Date: 2011-03-08
Classification: G11C,H03L

Abstract:
1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising: a clock signal receiver configured to receive the main clock signal and the data clock signal from a memory controller; and a phase tuner configured to: during coarse tuning, generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal, during the coarse tuning, generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another, during the coarse tuning, compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, during the coarse tuning, feed back each comparison result to the memory controller, and during fine tuning, compare a phase of a signal selected from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and feed back a comparison result to the memory controller.