Patent ID: 6853582
Filing Date: 2005-02-08
Classification: G11C

Abstract:
1. A nonvolatile memory, comprising: a power terminal; a ground terminal; a plurality of nonvolatile storage elements; a control circuit; and a boosting circuit for boosting a power supply voltage supplied to the power terminal, wherein a plurality of well regions are connected to back gates of the plurality of nonvolatile storage elements, a high voltage generated by the boosting circuit is applied to back gates of the nonvolatile storage elements to perform writing or erasing, and a magnitude of a load on the boosting circuit varies according to a number of the well regions to which the high voltage is applied upon erasing of each memory cell, and wherein the boosting circuit is controlled so that, regardless of the number of well regions to which the high voltage is applied, a voltage boosting speed at erasure is approximately equal to a voltage boosting speed when the magnitude of the load is large.