Patent ID: 6822478
Filing Date: 2004-11-23
Classification: G06F,Y02D

Abstract:
A circuit for capturing data on a bus, comprising: a plurality of flip-flops, each of said flip-flops receiving an input data bit and producing an output data bit upon assertion of a gated clock signal;comparison logic coupled to said flip-flops, said comparison logic determining whether any of said input data bits change state, wherein said comparison logic receives the input data bit and output data bit from each of said flip-flops and compares the logic states of said input data bit and output data bit from each of said flip-flops and, if the logic states of said bits do not match, asserts an enable signal to indicate that at least one of said input data bits has changed state; and clock logic that receives said enable signal and an external clock signal and generates the gated clock signal based on the logic state of the enable signal and external clock signal.