Patent ID: 6127699
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A semiconductor device, having a source, a drain and a gate electrode, fabricated by a process comprising the steps of:forming a plurality of field oxide regions on said substrate to isolate a plurality of active areas;forming a lightly doped region at one of said active areas;forming a doped silicon layer including dopants on said lightly doped region at said one active area and on the field oxide regions isolating said one active area;forming a patterned first dielectric layer on said doped silicon layer to define a gate area;forming a second dielectric layer on said first dielectric layer and said doped silicon layer;forming a third dielectric layer on said second dielectric layer;anisotropically etching said third and second dielectric layers to form a plurality of spacer regions surrounding said gate area and to expose said doped silicon layer at said gate area;forming a groove at said gate area by etching said exposed doped silicon layer and said substrate;forming a gate oxide layer in said groove and forming said source and said drain in said substrate by substantially driving said dopants in said doped silicon layer into said substrate; andforming said gate electrode in said groove.