Patent ID: 6292390
Filing Date: 2001-09-18
Classification: G11C,H01L,H03F,H03K

Abstract:
A semiconductor device comprising:a plurality of memory cells arranged in a matrix, each of said memory cells comprising a bipolar transistor and a respective switching element connected to the bipolar transistor of the respective memory cell;a plurality of bit lines each connected to the first terminal of said respective switching element;a plurality of word lines each connected to the control terminal of said respective switching element; andan amplifier unit which receives data read out from said memory cells,said bipolar transistor having a base, an emitter, a collector, a base-emitter junction and a collector-base junction, said bipolar transistor has a first operating region such that with a positive base-emitter voltage V.sub.BE in a first range and a predetermined positive collector-emitter voltage V.sub.CE, a positive base current I.sub.B is produced, a second operating region such that with a positive base-emitter voltage V.sub.BE in a second range greater than the first range and said positive collector-emitter voltage V.sub.CE, a negative base current I.sub.B is produced, said positive base-emitter voltage V.sub.BE being determined so that said negative base current I.sub.B is produced by impact ionization in said second operating region without actual breakdown, and a third operation region such that with a positive base-emitter voltage V.sub.BE in a third range greater than the second range andsaid positive collective emitter voltage V.sub.CE, a positive base current I.sub.B is produced; and a bias unit which biases the bipolar transistor to operate with the positive collector-emitter voltage V.sub.CE and at a boundary point between the second and third operation regions, including a voltage varying unit which varies a voltage applied to the base of said bipolar transistor so that when V.sub.BE exceeds a predetermined threshold and the voltage applied to the base of the bipolar transistor is removed by said bias unit, the transistor is self-latched at the boundary between the second and third operating regions to output from the base of the bipolar transistor an output voltage at a first level, and so that when the voltage applied to the base of said bipolar transistor is such that V.sub.BE is less than said threshold and said applied voltage is then removed by said bias unit, the bipolar transistor operates in said first operating region and outputs from the base an output voltage at a second level different than said first level, andwherein said bias unit comprises a switching element having first and second terminals, a conduction path between said first and second terminals, and a control terminal for controlling conductivity of said conduction path, said second terminal connected to the base of said bipolar transistor, wherein, when said conduction path is rendered conductive and a first logic level voltage in said first range is temporarily applied to the base of said bipolar transistor via said conduction path, said bipolar transistor operates in said first operating region during the time of application of said first logic level voltage to said base, and after said conduction path is rendered nonconductive resulting in cessation of application of said first logic level voltage to said base, said base assumes a stable low logic level at said base of said bipolar transistor, and when said conduction path is rendered conductive and a second logic level voltage in one of said second and third range sis temporarily applied to the base of said bipolar transistor via said conduction path, said bipolar transistor operates in one of said second and third operating regions during application of said second logic level, and upon said conduction path being rendered non-conductive resulting in the cessation of application of said logic level voltage to said base of said bipolar transistor, said base of said bipolar transistor assumes a stable high logic level at said boundary potential.