Patent ID: 9158716
Filing Date: 2015-10-13
Classification: G06F,G11C

Abstract:
1. A memory controller, comprising: a first circuit adapted to perform read and write operations over a memory bus according to signaling of a first memory type, the memory bus including a plurality of electrical paths coupled to a plurality of sockets; a second circuit, different from the first circuit, adapted to perform read and write operations over the memory bus according to signaling of a second memory type, different from the first memory type; and a switch coupled to only a first socket of the plurality of sockets and to the first circuit and second circuit, the switch adapted to: wherein the first and second circuits are adapted to concurrently communicate with memory modules of the first memory type and second memory type, respectively, via the memory bus, wherein communication between the first circuit and a memory module of the first type that is coupled to a second socket, different from the first socket, is unaffected by the selection made by the switch coupled to the first socket, and wherein: