Patent ID: 8823562
Filing Date: 2014-09-02
Classification: H03L,H03M,H04Q

Abstract:
1. A parallel-to-serial converter circuit that converts parallel first to fourth input data signals into a serial signal, the parallel-to-serial converter circuit comprising: a first latch group that based on a first clock signal of a given cycle, outputs the first input data signal at a first timing of the given cycle; a second latch group that outputs the second input data signal at a second timing that is of the given cycle and delayed by half a cycle of the given cycle relative to the first timing; a third latch group that outputs the third input data signal at the second timing; a fourth latch group that outputs the fourth input data signal at a third timing that is of the given cycle and delayed by one given cycle relative to the first timing; a first multiplexer that at each given cycle and based on a second clock signal having a phase that differs by ¼ cycle from the phase of the first clock signal, outputs the second input data signal, after outputting the first input data signal; a second multiplexer that at each given cycle and based on the second clock signal, outputs the fourth input data signal, after outputting the third input data signal and that outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer; and a third multiplexer that at each given cycle and based on the first clock signal, outputs the third and the fourth input data signals output from the second multiplexer, after outputting the first and the second input data signals output front the first multiplexer.