Patent ID: 8645954
Filing Date: 2014-02-04
Classification: G06F,Y02D

Abstract:
1. An apparatus, comprising: a first processor to execute a first set of instructions; a second processor to execute a second set of instructions; a first monitor adapted to determine whether the first processor will execute the first set of instructions to a predetermined acceptable performance level by monitoring an operational voltage potential of a portion of a core within the first processor, wherein the first monitor is further adapted to determine whether the first processor will execute the first set of instructions to a predetermined acceptable performance level by monitoring an operational frequency of the first processor, an internal synchronizing signal of the first processor, a number of wait states generated by the first processor, a rate at which memory external to the first processor is accessed, a cache hit/miss rate of the first processor, or an amount of current passing through all or a portion of the first processor, or a combination thereof; and a second monitor communicatively coupled to the first monitor and adapted to determine whether the second processor will execute the second set of instructions to the predetermined acceptable performance level, wherein the apparatus is adapted to execute a third set of instructions on the first processor when the second processor will not execute the third set of instructions to the predetermined acceptable performance level, and wherein the apparatus is adapted to maintain a database coupled to the first monitor to track an historical average of a processor demand associated with the first processor needed to execute the third set of instructions and to increase a power consumption of the first processor by increasing an operational parameter of the first processor if the first processor is unable to execute the third set of instructions to the predetermined acceptable performance level.