Patent ID: 7554855
Filing Date: 2009-06-30
Classification: G11C

Abstract:
1. A solid-state memory system comprising: a volatile memory including a plurality of volatile solid-state devices; a non-volatile memory including a plurality of non-volatile solid-state devices; a memory controller coupled to the plurality of volatile solid-state devices and the plurality of non-volatile solid-state devices; and a plurality of buses for coupling the memory controller to the plurality of volatile solid-state devices and the plurality of non-volatile solid-state devices, the plurality of buses configured to work independently in such a manner that they are capable of being accessed simultaneously; wherein the memory controller is configured to store write data in at least one of the volatile solid-state devices, the memory controller being further configured to transfer data from the at least one of the volatile solid-state devices to at least one of the non-volatile solid-state devices in response to a data transfer request.