Patent ID: 6458668
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method for manufacturing a hetero junction bipolar transistor, said method comprising the steps of:(a) forming an emitter metal in a vacuum evaporation manner on a substrate composed of an upper InGaAs/GaAs layer, an intermediate InGaP layer, and a lower GaAs layer; (b) carrying out a selective wet etching on said InGaAs/GaAs layer by using said emitter metal as a masking material; (c) forming a thin film of a material selected from the group of consisting of Si3N4, SiO2 and TiW on the surface of said emitter metal and said InGaP layer, in a vacuum evaporation manner; (d) carrying out patterning of a photoresist on said thin film by using a contact aligner to form a base opening; (e) carrying out the opening of said thin film positioned on said base opening in wet and dry etching manners; (f) carrying out a wet etching said intermediate InGaP layer; and (g) forming a base metal in a vacuum evaporation and carrying out the lifting off of said photoresist to thereby form base contact.