Patent ID: 7625796
Filing Date: 2009-12-01
Classification: H01L

Abstract:
1. A method for making an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure, the method comprising: providing a substrate; forming a first insulation layer on the substrate; forming one or more source or drain regions on the first insulation layer, each of the one or more source or drain regions being associated with a first surface and including an n-type a-Si layer, a barrier layer, and a conductive layer, the n-type a-Si layer being on the barrier layer, the barrier layer overlying the conductive layer, the first surface consisting of n-type a-Si; forming a second insulation layer on the first insulation layer, the second insulation layer being associated with a second surface, the second surface being substantially co-planar with the first surface; forming an i-type a-Si layer overlying the first surface and the second surface; forming a p-type a-Si layer overlying the i-type a-Si layer; forming an oxide-nitride-oxide (ONO) layer overlying the p-type a-Si layer; forming a metal layer overlying the ONO layer; and forming at least one control gate by patterning the metal layer.