Patent ID: 8933472
Filing Date: 2015-01-13
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising a gate line and a data line that define a pixel region including a thin film transistor region and a pixel electrode pattern region, wherein in the thin film transistor region a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an active layer and a passivation layer are provided, and a channel part is formed between the source electrode and the drain electrode and recessed to the inner of the active layer; in the pixel electrode pattern region the gate insulating layer, a pixel electrode, the passivation layer and a common electrode are formed, and a multi-dimensional electric field is formed between the common electrode and the pixel electrode when the common electrode and the pixel electrode are applied voltages, wherein a color resin layer is formed between the passivation layer and the common electrode, and wherein the color resin layer is made of a material having a dielectric constant of 3˜5 F/m and a thickness of 0.5 μm˜2 μm.