Patent ID: 7361992
Filing Date: 2008-04-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a multilayered film including a first dielectric film, an etching stopper and a second dielectric film stacked on said semiconductor substrate in this order; a first metal interconnect embedded in the multilayered film; a first via plug connected to the under surface of the first metal interconnect; a second metal interconnect embedded in the multilayered film; and a second via plug connected to the under surface of the second metal interconnect, wherein the dielectric constant of said etching stopper is larger than that of said first and second dielectric films, the upper surface of said etching stopper is located under the upper surface level of said first and second metal interconnects, the under surface of said etching stopper is located over the under surface level of said first and second metal interconnects, the etching stopper is positioned substantially below the middle level in the height of said first and second metal interconnects, the under surface of said first and second metal interconnects is located inside the first dielectric film, the distance between the first metal interconnect and the second metal interconnect is smaller than the distance between the first via plug and the second via plug, and the etching stopper is located between the first metal interconnect and the second metal interconnect.