Patent ID: 6820177
Filing Date: 2004-11-16
Classification: G06F

Abstract:
A system, comprising:at least one processor; a memory; and a logic circuit having a set of registers and coupled to the at least one processor by a first bus and coupled to the memory by a second bus, the logic circuit to map an address within a predetermined range of addresses to a particular register in the set of registers in response to a command with the address being issued by the at least one processor, and to reject the command without mapping in response to the command being issued by a non-processor device, and wherein: the logic circuit includes a first mode to accept protected commands and a second mode to accept at least one non-protected command, wherein the logic circuit includes control logic to execute a first command to write to the particular register, a second command to read from the particular register, a third command to perform an action in the logic circuit excluding a write to the set of registers and excluding a read to the set of registers, and a fourth command to be conveyed to a protected device external to the logic circuit, the processor includes first microcode to issue a first protected command to switch the logic circuit from the first mode to the second mode, and the processor includes second microcode to issue a second protected command to switch the logic circuit from the second mode to the first mode.