Patent ID: 7539893
Filing Date: 2009-05-26
Classification: G01R

Abstract:
1. A method for evaluating an integrated circuit, the method comprising: generating an estimate of a timing distribution for a first set of critical timing paths of the integrated circuit; generating an estimate of a timing distribution for a second set of critical timing paths of the integrated circuit; measuring, for a particular integrated circuit, at least a portion of the timing distribution for the second set of timing paths by testing specific path-delays; comparing the measured timing distribution and the estimated timing distribution for the second set of timing paths; using parameters from the comparison of the second set of critical paths and from the timing distribution for the first set of critical timing paths to extrapolate a critical timing path distribution for the first set of critical timing paths that is particular to the particular integrated circuit; and grading the integrated circuit based at least partially on the extrapolated critical timing path distribution.