Patent ID: 6104053
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A semiconductor device comprising:a capacitor including a first electrode consisting of a first conductive layer being formed in a logic circuit area, a first dielectric film consisting of a first interlayer isolation film being formed on said first electrode, a second electrode consisting of a second conductive layer being formed on said first dielectric film, a second dielectric film consisting of a second interlayer isolation film being formed on said second electrode, and a third electrode consisting of a third conductive layer being formed on said second dielectric film;a third interlayer isolation film being formed on said third electrode;a first opening being formed at least through said first, second and third interlayer isolation films to reach the upper surface of said first electrode;a second opening being formed at least through said second and third interlayer isolation films to reach the upper surface of said second electrode; anda third opening being formed at least through said third interlayer isolation film to reach the upper surface of said third electrode, whereinsaid first electrode has a first connecting region whose surface is exposed in said first opening,said second electrode has a second connecting region whose surface is exposed in said second opening,said third electrode has a third connecting region whose surface is exposed in said third opening, andsaid first and third connecting regions are connected with each other by a connecting wire through said first and third openings.