Patent ID: 6032241
Filing Date: 2000-02-29
Classification: G06F

Abstract:
For use in a processor having a physically-addressable cache, an address translation device for translating linear addresses received from a plurality of linear address sources and selectively accessing physical addresses, linear addresses, and controls signals stored in said address translation device, said address translation device comprising:an array of data cells for storing said physical addresses, linear addresses, and controls signals in a plurality of entries;an entry selection circuit for receiving a first linear address from a first linear address source and, in response thereto, generating an entry select output corresponding to said first linear address;a first switch controllable by said entry select output; anda second switch controllable by an address source select signal received from said first linear address source;wherein said entry select output and said address source select signal close said first and second switches to thereby form a connection path, the formation of said connection path causing a selected data cell to transfer a stored target bit stored therein to a data bit line of said address translation device.