Patent ID: 6788119
Filing Date: 2004-09-07
Classification: H03K,H03L

Abstract:
A delay lock loop (DLL), comprising:an input clock terminal; a feedback clock terminal; an output clock terminal; a phase shifter circuit having a first input terminal coupled to the input clock terminal of the DLL, a second input terminal coupled to the feedback clock terminal of the DLL, and first and second output terminals; a first phase detector coupled to the first and second output terminals of the phase shifter circuit; a first programmable inversion circuit having an input terminal coupled to the first output terminal of the phase shifter circuit, an output terminal, and a control terminal; a first delay circuit having an input terminal coupled to the output terminal of the first programmable inversion circuit, and further having an output terminal; a second programmable inversion circuit having an input terminal coupled to the output terminal of the first delay circuit, an output terminal, and a control terminal; a second delay circuit having an input terminal coupled to the output terminal of the second programmable inversion circuit, and further having a plurality of output terminals; a second phase detector having first and second input terminals coupled to first and last ones of the output terminals of the second delay circuit; an output generator circuit having a plurality of input terminals coupled to the output terminals of the second delay circuit, and further having an output terminal coupled to the output clock terminal of the DLL; and a control circuit coupled to each of the phase shifter circuit, the first and second phase detectors, the first and second delay circuits, and the output generator circuit.