Patent ID: 7199630
Filing Date: 2007-04-03
Classification: H03L

Abstract:
1. A delay locked loop comprising: a delay circuit that is configured to generate an output clock signal by delaying an input clock signal according to a voltage of a control signal, the delay circuit comprising an oscillating circuit to which the input clock signal is input; a phase detector that is configured to receive the output clock signal as a feedback signal, to detect a phase difference between the input clock signal and the feedback signal, and to output a result of detection; a charge pump that is configured to generate a current corresponding to the result of detection; and a loop filter that is configured to output the control signal as a voltage that corresponds to the current; wherein the oscillating circuit is configured to change a phase of the output clock signal in response to the control signal while maintaining the frequency of the output clock signal to correspond to the frequency of the input clock signal.