Patent ID: 7725645
Filing Date: 2010-05-25
Classification: G11C

Abstract:
1. An apparatus, comprising: a first memory device containing a non-volatile memory array; a memory controller to control operations with the memory array; and a memory bus coupled between the first memory device and the memory controller, the memory bus including a signal line; wherein the first memory device to perform a first set of multiple transmissions of a signal to the memory controller via the signal line, wherein for each of the multiple transmissions of the signal to the memory controller, the memory controller to perform a different respective latching of data on the memory bus during a read operation with the first memory device, and wherein the first memory device further to perform a second sending of the signal to the memory controller via the signal line, the second sending of the signal to indicate to the memory controller an end of at least one of a block write operation and an erase operation with the first memory device.