Patent ID: 6408385
Filing Date: 2002-06-18
Classification: G06F

Abstract:
A data processor for processing instructions including a subroutine call instruction and a subroutine return instruction, the data processor comprising:an instruction decoder decoding the instructions; an address bus transferring an address of an instruction to be fetched; an address generating unit generating a return address on the basis of said subroutine call instruction decoded by said instruction decoder, said return address being transferred to and stored in a store circuit as an accurate return address; a program counter stack capable of storing a predetermined number of predicted addresses, said return address generated by said address generating unit being transferred to and stored in said program counter stack on the basis of said subroutine call instruction decoded by said instruction decoder, said program counter stack outputting a predicted address to said address bus in a first period on the basis of said subroutine return instruction decoded by said instruction decoder; and a judging circuit receiving the accurate return address stored in said store circuit, and judging, on the basis of said subroutine return instruction decoded by said instruction decoder, whether the predicted address output from said program counter stack coincides with said accurate return address, wherein said accurate return address is transferred to said address bus in a second period after said first period when a judging result of said judging circuit indicates that the predicted address does not coincide with said accurate return address.