Patent ID: 9165628
Filing Date: 2015-10-20
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a first word line; a first, a second, and a third bit line; a first select transistor including a gate electrode connected to the first word line, and one end of the first select transistor connected to the first bit line via a first variable resistance element and other end of the first select transistor connected to the second bit line; a second select transistor including a gate electrode connected to the first word line, and one end of the second select transistor connected to the third bit line via a second variable resistance element and other end of the second select transistor connected to the second bit line; and a control circuit configured to apply a first voltage to the first word line, to apply a second voltage to the first bit line, to apply a third voltage different from the second voltage to the second bit line, and to set the third bit line in a floating state.