Patent ID: 8578182
Filing Date: 2013-11-05
Classification: G06F

Abstract:
1. A power lock-up setting method, adapted to an electronic apparatus, wherein the electronic apparatus comprises a power switch, a general purpose input/output (GPIO) interface, a control unit, a logic processing unit, and a processing module, the power lock-up setting method comprising: receiving a trigger signal by a pin of the GPIO interface and transmitting the trigger signal to the control unit, such that the control unit starts the electronic apparatus, and a power-on-self-test of the logic processing unit is performed by the processing module, wherein the trigger signal is generated by the power switch which is pressed; determining whether the GPIO interface is set to a power lock-up state by the logic processing unit, wherein a level of the pin is set to a disable level by the logic processing unit when the GPIO interface is set to the power lock-up state; and loading an operating system by the processing module to perform an operating system booting process, wherein under an operating environment of the operating system, the trigger signal is forbidden to be transmitted to the control unit when being generated again, wherein the logic processing unit comprises a basic input/output system (BIOS) and a baseboard management controller (BMC), in the step of determining whether the GPIO interface is set to the power lock-up state, whether the GPIO interface is set to the power lock-up state determined by the BIOS, and when the GPIO interface is set to the power lock-up state, a lock-up command is transmitted to the BMC by the BIOS such that the BMC sets the level of the pin to the disable level.