Patent ID: 6535046
Filing Date: 2003-03-18
Classification: H01L

Abstract:
In an integrated semiconductor circuit, the improvement comprising:a substrate of a p-conductivity type; a well of the p-conductivity type disposed in said substrate and electrically insulated from said substrate, said well having a well terminal; an NMOS transistor disposed in said well; a first potential of an operating voltage applied to the semiconductor circuit in a first operating mode; a second potential of the operating voltage applied to the semiconductor circuit in a second operating mode, the second potential being higher than the first potential; a control circuit having a terminal for an output signal with a potential to be altered by said control circuit, said terminal for the output signal connected to said well terminal, the output signal of said control circuit having a first reference-ground potential in the first operating mode, and the output signal of said control circuit having a second reference-ground potential in the second operating mode, the second reference-ground potential being higher than the first reference-ground potential; an inverter stage having an input terminal for an input signal and said NMOS transistor, said NMOS transistor having a well terminal and a source terminal connected to one another; and a further control circuit having an input terminal for an input signal and an output terminal for an output signal, said further control circuit raising a potential of the input signal in the second operating mode to be picked off, in a raised state, at said output terminal for the output signal of said further control circuit, said input terminal for the input signal of said inverter stage being connected to said output terminal for the output signal of said further control circuit; and the semiconductor circuit being operable in its intended function in both the first operating mode and the second operating mode.