Patent ID: 8964118
Filing Date: 2015-02-24
Classification: G09G,H04N

Abstract:
1. A display signal processing system, comprising: a V-by-One circuit capable of selecting a JEIDA mode and a VESA mode; an image processing circuit for converting a format of display signals from a signal source, and for outputting the converted display signals to the V-by-One circuit; and the V-by-One circuit comprises a signal input for connecting the image processing circuit to input the converted display signals, signal output, and a GPIO for selectively inputting a first or a second selection signal such that the V-by-One circuit transforms the converted display signal to be a first LVDS signal under the JEIDA mode or a second LVDS under the VESA mode, and then the first LVDS or second LVDS signal is output by the signal output, the first selection signal and the second selection signal are voltage signals, and the voltage of the first selection signal is higher than the voltage of the second selection signal; and wherein the system further comprises a first resistor and a second resistor, a first end of the first resistor is grounded, a second end of the first resistor connects to a first end of the second resistor and the GPIO, a second end of the second resistor connects to a power source such that the GPIO is controlled by the power source to generate the first or the second selection signal.