Patent ID: 9082630
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having a first area and a second area divided by a shallow trench isolation (STI) area; a first dummy structure on the STI area at the side of the first area of the substrate, comprising a first dummy gate stack; a second dummy structure on the STI area at the side of the second area of the substrate, comprising a second dummy gate stack with a high-k dielectric layer, a first spacer next to the second dummy gate stack, and a third dummy gate stack with a trench stack next to the first spacer; a first semiconductor structure on the first area of the substrate, comprising a first gate structure with a second intermediate layer and a second conductive layer over the second intermediate layer; and a second semiconductor structure on the second area of the substrate, comprising a high-k dielectric layer and a metal gate layer over the high-k dielectric layer.