Patent ID: 9159279
Filing Date: 2015-10-13
Classification: G02F,G09G

Abstract:
1. A liquid crystal display device, comprising: multiple scan lines; multiple data lines; and multiple sub-pixel units, and each sub-pixel unit includes a common electrode line, multiple display regions and multiple control switches for controlling the display regions to receive corresponding data voltages, wherein, the multiple control switches includes a first control switch set and a second control switch set, and the first control switch set and the second control switch set are connected in parallel with the same data line for applying the corresponding data voltages to the multiple display regions through the data line; wherein, the multiple display regions includes a first a first display region, a second display region, and a third display region; the first control switch set includes a first transistor; the second control switch set includes a second transistor and a third transistor; a gate electrode of the first transistor is connected with one of the scan lines, a source electrode of the first transistor is connected with the data line, and a drain electrode of the first transistor is connected with the first display region; a gate electrode of the second transistor is connected with the one scan line, a source electrode of the second transistor is connected with the data line, and a drain electrode of the second transistor is connected with the second display region; a gate electrode of the third transistor is connected with the one scan line, a source electrode of the third transistor is connected with the drain electrode of the second transistor, and a drain electrode of the third transistor is connected with the third display region; the first transistor is connected in series with a fourth transistor, and the third transistor is connected in series with a fifth transistor; a source electrode of the fourth transistor is connected with the drain electrode of the first transistor, a drain electrode of the fourth transistor is connected with the common electrode line, and a gate electrode of the fourth transistor is connected with the one scan line; a source electrode of the fifth transistor is connected with the drain electrode of the third transistor, a drain electrode of the fifth transistor is connected with the common electrode line, and a gate electrode of the fifth transistor is connected with the one scan line.