Patent ID: 8574984
Filing Date: 2013-11-05
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor integrated circuit device, the manufacturing method comprising: defining a first element area by forming an element separating area on a semiconductor substrate; forming a tunnel insulating film in the first element area; forming a floating gate above the tunnel insulating film and a first electrode pattern in the element separating area; forming a first insulating film above the floating gate and a second insulating film above the first electrode pattern; forming a control gate above the first insulating film and a second electrode pattern above the second insulating film; forming a source area and a drain area in the semiconductor substrate in the first element area; forming a first interlayer insulating film to cover the control gate and the second electrode pattern above the semiconductor substrate; forming, in the first interlayer insulating film, a conductive via plug that reaches the second electrode pattern; forming, above the first interlayer insulating film in the element separating area, a first wiring pattern capacitively-coupled to the second electrode pattern; and forming, above the first interlayer insulating film, a second wiring pattern electrically coupled to the second electrode pattern via the conductive via plug, and capacitively-coupled to the first wiring pattern.