Patent ID: 8542033
Filing Date: 2013-09-24
Classification: H03K

Abstract:
1. A domino logic circuit comprising: a first evaluation unit configured to precharge a first dynamic node and configured to discharge a footer node in a first phase of a clock signal, and configured to evaluate a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal; a second evaluation unit connected to the first dynamic node and the footer node, the second evaluation unit configured to precharge a second dynamic node in the first phase of the clock signal, and configured to determine a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal; and an output unit connected to the first and second dynamic nodes, the output unit configured to provide an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node, wherein the second evaluation unit includes,