Patent ID: 7858465
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: depositing a first insulating layer on a substrate; depositing a first electrode layer on the first insulating layer; depositing a second insulating layer on the first electrode layer; depositing a second electrode layer on the second insulating layer; depositing a third insulating layer on the second electrode layer; depositing a third electrode layer on the third insulating layer; processing the first to third insulating layers and the first to third electrode layers to form forming self-aligned silicide layers on surfaces of the gate electrode and the third capacitor electrode; depositing an inter layer dielectric that covers the transistor and the capacitor; forming, in the inter layer dielectric, a contact hole for the transistor, a contact hole for the first capacitor electrode, and a contact hole for the second capacitor electrode; embedding contact plug material in the contact hole for the transistor, the contact hole for the first capacitor electrode, and the contact hole for the second capacitor electrode; planarizing the contact plug material to form a contact plug for the transistor, a contact plug for the first capacitor electrode, and a contact plug for the second capacitor electrode and to expose the silicide layer on the third capacitor electrode; depositing a line layer that covers the contact plug for the transistor, the contact plug for the first capacitor electrode, the contact plug for the second capacitor electrode, and the silicide layer on the third capacitor electrode; and processing the line layer to form line patterns formed of the line layer.