Patent ID: 7676775
Filing Date: 2010-03-09
Classification: G01R,G11C

Abstract:
1. A method for determining root causes of fail patterns in integrated circuit chips, the method comprising: identifying, by using a computer, a plurality of potential defects that can occur in a given integrated circuit chip layout from a schematic used in the manufacture of the integrated circuit chip; identifying, by using the computer, a plurality of potential fail patterns in the given integrated circuit chip layout, the potential fail patterns comprising functional manifestations of defects in the integrated circuit chip; identifying, by using the computer, correlations between the identified potential defects and identified potential fail patterns that are root causes of the identified potential fail patterns; using the identified correlations to identify groupings of potential fail patterns and potential defects, each grouping comprising one potential defect and one or more potential fail patterns; and using the groupings of potential fail patterns and potential defects to identify actual defects in a production integrated circuit chip by: