Patent ID: 6821870
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A method of fabricating a heterojunction bipolar transistor comprising:process (a) for forming, on a first semiconductor layer of a first conductivity type which contains Si as a component and acts as a collector layer, a second semiconductor layer containing a SiGeC layer and having a narrower band gap than the first semiconductor layer and an average lattice strain of over 0.5% but below 1.0% after a subsequent heat treatment; process (b) for forming a third semiconductor layer containing at least Si and having a band gap wider than the second semiconductor layer onto the second semiconductor layer; process (c) for forming a conductive layer containing a first conductivity type impurity which is in contact with a part of the third semiconductor layer; process (d) for forming a base layer by introducing a second conductivity type impurity at least to a part of the second semiconductor layer by diffusing said second conductivity type impurity into said second semiconductor layer thermally; and process (e) for forming an emitter diffusion layer by diffusing the first conductivity type impurity in said conductive layer into the third semiconductor layer by a heat treatment.