Patent ID: 6105152
Filing Date: 2000-08-15
Classification: G11C

Abstract:
A method for testing a semiconductor memory device, the memory device having a plurality of memory cells accessible by a plurality of word lines and bit lines, the memory device having preparatory and control circuitry for preparing and selecting ones of the memory cells, word lines, and bit lines for a write or read operation, one set of the memory cells being coupled to a sense amplifier via at least one bit line, individual memory cells being configured to store an electrical charge indicative of a binary ""1"" or ""0"", the binary ""I"" or ""O"" being written to and read from an individual memory cell by applying a voltage level to a word line and applying or measuring a data voltage level indicative of a binary ""1"" or ""0"" on a bit line, the writing and reading occurring during a cycle of sequential timing signals that activates at least in part the sense amplifier, a word line, a bit line, and the preparatory and control circuitry, the timing signals within a cycle occurring in a sequential order at selected start times after commencement of the cycle, the timing signals having selected durations after their respective start times, the timing signals having selected voltage levels, the method for testing comprising the following steps:writing and reading test information to and from the memory cells during a testing period;during the testing period, controllably adjusting at least one of (1) start times of the timing signals in relation to commencement of a cycle, (2) the durations of the timing signals, and (3) the voltage levels of the timing signals, the controlled adjustment of timings and voltage levels resulting in an alteration of the data voltage level on the bit line to be sensed by the sense amplifier such that, in a case that the memory device has a defect, the data voltage level will be altered to a degree that causes the sense amplifier to incorrectly sense test information written to or read from a memory cell and to output an erroneous value;comparing the test information input to and output from the memory cells; andgenerating an error signal if the test information read from the memory cells is not the same as the information written to the memory cells.