Patent ID: 8384137
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semi-insulating GaAs substrate; an n type semiconductor layer formed in the semi-insulating GaAs substrate; a p type semiconductor layer formed in the n type semiconductor layer; an ohmic electrode layer formed on top of the p type semiconductor layer; a reaction layer formed in an interface between the ohmic electrode layer and the p type semiconductor layer; a gate electrode placed on top of a first surface of the semi-insulating GaAs substrate, and including a plurality of fingers; a source electrode placed on top of the first surface of the semi-insulating GaAs substrate, and including a plurality of fingers; a drain electrode placed on top of the first surface of the semi-insulating GaAs substrate, and including a plurality of fingers; a gate terminal electrode placed on top of the first surface of the semi-insulating GaAs substrate, and gathering together the fingers of the gate electrode; a source terminal electrode placed on top of the first surface of the semi-insulating GaAs substrate, and gathering together the fingers of the source electrode; a drain terminal electrode placed on top of the first surface of the semi-insulating GaAs substrate, and gathering together the fingers of the drain electrode; a gate pad placed on top of the ohmic electrode layer, and connecting the ohmic electrode layer and the gate terminal electrode together; and a backside metal electrode placed on top of a second surface of the semi-insulating GaAs substrate opposite to the first surface, and connected to the source terminal electrode.