Patent ID: 6480936
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A storing apparatus comprising:a cache control unit for, when a write access is received from an upper apparatus, caching write data into a data buffer area in a memory, notifying said upper apparatus of a normal end, and thereafter, writing the write data cached in said data buffer area onto a storing medium; an access kind discriminating unit for discriminating whether the write access from said upper apparatus is a random access in which write addresses are discontinuous or a sequential access in which the write addresses are continuous; and a buffer construction control unit for setting a random corresponding buffer construction which enables a buffer development and a medium writing that are suitable for said random access or a sequential corresponding buffer construction which enables a buffer development and a medium writing that are suitable for said sequential access, for changing the buffer construction to said sequential corresponding buffer construction when said sequential access is decided in a setting state of said random corresponding buffer construction, and for changing the buffer construction to said random corresponding buffer construction when said random access is decided in a setting state of said sequential corresponding buffer construction; wherein said access kind discriminating unit further sets an ascending order mode for an ascending order access in which a present address is increased from a previous address and sets a descending order mode for a descending order access in which the present address is decreased from the previous address, and said cache control unit caches the write data from a head position in a buffer section by an ascending order in said ascending order mode and caches the write data from an end position in the buffer section by a descending order in said descending order mode.