Patent ID: 6498387
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A wafer level package, said wafer level package comprising:a wafer having a plurality of dies formed thereon, wherein said wafer has a trench formed on a first side surface of said wafer and over a scribe line; a material attached on a second side surface of said wafer by a first adhesive material, wherein said material attached on said second side surface of said wafer is selected from the group of glass, quartz or ceramic; a second adhesive material formed over said plurality of dies and refilled into said trench, wherein said plurality of dies has a plurality of pads formed thereon; a circuit layout formed on and contacting an upper surface of said second adhesive material and connected to said plurality of pads; a solder mask covered on said circuit layout and said second adhesive material to expose a portion of said circuit layout; and solder balls formed on said exposed portion and connected to said circuit layout.