Patent ID: 6448600
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A DRAM cell configuration, comprising:a plurality of memory cells each having a capacitor and a transistor; a substrate having formed therein a first depression and a second depression spaced apart from said first depression; said capacitor being formed as a vertical capacitor having a storage node disposed in said first depression, and a capacitor dielectric in said first depression between said storage node and said substrate; said storage node adjoining said substrate at least in a contact region of a lateral surface of said first depression; said transistor having a gate electrode in said second depression at least at a first lateral surface of said second depression; a gate dielectric adjoining at least the first lateral surface and isolating said gate electrode from said substrate; said transistor having an upper source/drain region disposed in said substrate adjoining said second depression, and adjoining said storage node in the contact region of said lateral surface of said first depression; and said transistor having a lower source/drain region disposed deeper in said substrate than said upper source/drain region and adjoining said second depression.