Patent ID: 6137159
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor chip provided on a major surface thereof with an integrated circuit and a plurality of bonding pads;a power lead having an inner lead part and an outer lead part which is formed integrally with the inner lead part, the inner lead part having a first section laying in a region corresponding to the major surface of the semiconductor chip and a second section lying outside the region corresponding to the major surface of the semiconductor chip;a plurality of signal leads each having an outer lead part, and an inner lead part having a first section lying in a region corresponding to the major surface of the semiconductor chip and a second section lying outside the region corresponding to the major surface of the semiconductor chip;a plurality of first bonding wires electrically connecting the first section of the power lead to the bonding pads, respectively;a plurality of second bonding wires electrically connecting the first section of the signal leads to the bonding pads, respectively; anda resin body sealing therein the semiconductor chip, the inner lead part of the plurality of signal leads, the inner lead part of the power lead, and the first and the second bonding wires;wherein the first section of the inner lead part of the power lead is bonded to a plurality of separate regions of the major surface of the semiconductor chip,the first section of the inner lead part of the signal leads are spaced apart in a direction of the thickness thereof from the major surface of the semiconductor chip, andwherein said first section of said power lead and said first sections of said plurality of signal leads are disposed on said major surface of said semiconductor chip at different regions in a plane view.