Patent ID: 6611011
Filing Date: 2003-08-26
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns and a plurality of subarray rows; a peripheral circuit area extending in a first direction in a middle section of said memory cell array; a pad area extending in the first direction in a middle section of said memory cell array, which differs from the middle section in which said peripheral circuit area is formed; and a plurality of signal lines each formed in a second direction perpendicular to the first direction so as to connect said peripheral circuit area and a corresponding one of the subarrays of the subarray columns, wherein said pad area includes a plurality of pads arranged in the first direction at pitches corresponding to those of said plurality of subarray columns, and said plurality of signal lines are each formed linearly so as to pass between the pads in said pad area.