Patent ID: 6182175
Filing Date: 2001-01-30
Classification: G06F

Abstract:
A process for serial data transfer between a main processing unit and a peripheral unit connected to each other by a bus including a data line and a clock line,wherein the main processing unit controls synchronised transfer cycles by means of the clock line, including transfer cycles with addressing and direct transfer cycles,wherein, during each cycle, the main processing unit transmits on the data line a strobe pulse while the clock line is at a first logic level,wherein, before transmitting the strobe pulse in a transfer cycle with addressing, the main processing unit transmits on the data line bits of a transfer address, with corresponding synchronisation pulses on the clock line,wherein, after receiving the strobe pulse in a transfer cycle with addressing, the peripheral unit accesses to a memory location determined from the transfer address to write or read data bits successively presented on the data line synchronously with corresponding synchronisation pulses on the clock line,and wherein, after receiving the strobe pulse in a direct transfer cycle, the peripheral unit accesses to a memory location determined prior to said direct transfer cycle to write or read data bits successively presented on the data line synchronously with corresponding synchronisation pulses on the clock line.