Patent ID: 9165651
Filing Date: 2015-10-20
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a memory cell array including at least first and second groups of memory strings, each of the memory strings including at least first and second memory cells serially connected between first and second select transistors; a plurality of word lines including a first word line commonly connected to the first memory cells of the memory strings and a second word line commonly connected to the second memory cells of the memory strings; a plurality of bit lines each connected to a different memory string in each of the groups of memory strings; and a control unit configured to perform a first read operation and a second read operation sequentially, wherein a select line voltage is applied to the first word line and a non-select line voltage is applied to the other word lines while the first and second select transistors of the first group of memory strings are turned on during the first read operation, and the non-select line voltage that was applied to the other word lines during the first read operation remains applied to the other word lines while the first and second select transistors of the first group of memory strings are turned off and the first and second select transistors of the second group of memory strings are turned on during the second read operation.