Patent ID: 6571311
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A microcomputer comprising:a nonvolatile memory in which a programming mode and a normal reading mode are set; a register which is connected to the nonvolatile memory through a switch in the programming mode; a register data bus and a register address bus connected to the register; a memory data bus and a memory address bus connected between the nonvolatile memory and the register, and a central processing unit that accesses the nonvolatile memory through a cpu bus and the switch in the normal reading mode, wherein the switch connects the nonvolatile memory to the cpu bus in the normal reading mode and connects the nonvolatile memory to the register in the programming mode, wherein the register comprises a memory control signal register block, a memory address register block, a memory data register block and a register address decoder, wherein, when the programming mode is set at least one register control signal, at least one register address and register data are supplied to the register, the register data is stored to any one of the register blocks in accordance with an enable signal from the register address decoder which decodes the register address, and wherein each of the register data is read out from the register and supplied to the nonvolatile memory as a memory control signal, a memory address and a memory data without an operation of the central processing unit.