Patent ID: 8778792
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A method of fabricating a solder bump connection, the method comprising: forming a layer stack containing a first conductive layer and a second conductive layer on the first conductive layer; forming a dielectric passivation layer in an island region on a top surface of the second conductive layer, wherein the island region includes an inner sidewall and an outer sidewall; forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer and circumscribed by the inner sidewall of the island region; forming a conductive plug in the via opening that is coupled by the second conductive layer with the first conductive layer; and after the conductive plug is formed, removing field regions of the layer stack outside of the outer sidewall of the island region with a selective wet chemical etching process.