Patent ID: 6858544
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A method for forming a bit line of a semiconductor device, comprising the steps: (a) forming a P+ S/D region and an N+ S/D region on a semiconductor substrate; (b) forming a planarized interlayer insulating film on the entire surface of the resulting structure; (c) etching the interlayer insulating film to form a first opening exposing the P+ S/D region; (d) subjecting the entire surface of the resulting structure, including the first opening, to a P+ ion implantation process; (e) etching the interlayer insulating film to form a second opening exposing the N+ S/D region; (f) forming a barrier metal layer on the entire surface of the resulting structure including the first and second openings; (g) forming a tungsten layer filling the first and second openings on the entire surface of the resulting structure; and (h) selectively etching the tungsten layer and the barrier metal layer to form a bit line.