Patent ID: 7176551
Filing Date: 2007-02-13
Classification: H01L

Abstract:
1. A fuse structure for a semiconductor device, comprising: a first insulating layer, disposed on a substrate; a fuse layer disposed on said first insulating layer, said fuse layer including at least a polysilicon layer and a silicide layer comprising a plurality of blocks including a first block, a second block, a third block, a fourth block, and a plurality of connecting blocks including a first connecting block connecting said first and second blocks, a second connecting block connecting said second and third blocks, and a third connecting block connecting said third and fourth blocks being formed at the same layer, said second and third blocks being between said first and fourth blocks, said second block being close to said first block, said third block being close to said fourth block, said first, second, third, and fourth blocks being not connected to one another except for connection by said first, second, and third connecting blocks, wherein any of the connecting blocks has a width narrower than that of any of the blocks, at least one of the connecting blocks has a size different from that of the others of the connecting blocks, and at least one of the blocks has a size different from that of the others of the blocks; a second insulating layer, disposed on said fuse layer, said second insulating layer including a plurality of via plugs; a first top metal layer, disposed on said second insulating layer and connected to said via plugs, wherein said first top metal layer is electrically connected to said first block of said fuse layer through said via plugs; and a second top metal layer, disposed on said second insulating layer and connected to said via plugs, wherein said second top metal layer is electrically connected to said fourth block of said fuse layer through said via plugs.