Patent ID: 7892984
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A method for performing a shallow trench isolation in an integrated circuit device, comprising: forming a pattern of trenches in a semiconductor substrate during a process of the shallow trench isolation; and heating the integrated circuit device prior to treating the trenches with a hydrofluoric acid, wherein the forming of the pattern of trenched comprises: forming a first silicon oxide film on the semiconductor substrate; forming a silicon nitride film on the first silicon oxide film; forming a silicon oxynitride film on the silicon nitride film; applying a photoresist on the silicon oxynitride film; and forming a plurality of openings via the photoresist by an exposure technique; and etching the silicon oxynitride film, the silicon nitride film, the first silicon oxide film and the semiconductor substrate via the plurality of openings to form the pattern of trenches.