Patent ID: 6621295
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A priority encoding arrangement for identifying a highest priority signal in a selected state from a plurality of input signals, comprising:a priority routing block implemented on a programmable logic device (PLD), the priority routing block having a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and a priority encoder implemented on the PLD and having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports, the priority encoder configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state, wherein the PLD is configured with a current configuration bitstream and further comprising a run-time reconfiguration control arrangement coupled to the programmable logic device, the run-time reconfiguration control arrangement configured to generate from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports and reconfigure the PLD with the new configuration bitstream.