Patent ID: 8174069
Filing Date: 2012-05-08
Classification: H01L

Abstract:
1. A power semiconductor device on a semiconductor substrate, the device having a top surface and an opposed bottom surface below a part of which is a relatively thick portion of the semiconductor substrate, the power semiconductor device having a drift region which is relatively lowly doped, at least a portion of the drift region having either no semiconductor substrate positioned thereunder or a relatively thin portion of the semiconductor substrate thereunder, wherein the relatively thick portion of the substrate is thicker than the relatively thin portion of the substrate, the top surface of the device having a high voltage terminal and a low voltage terminal connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region, wherein the voltage applied to the high voltage terminal is higher than the voltage applied to the low voltage terminal, the drift region having a first edge located proximate the low voltage terminal and a second edge located proximate the high voltage terminal, the device having at least two MOS (metal-oxide-semiconductor) gates on the top surface of the device for controlling current level in the device during on-state of the device and for controlling switching of the device, wherein a first of the MOS gates is located over the first edge of the drift region and in contact with the drift region and a second of the MOS gates is located over the relatively thick portion of the substrate, on the opposite side of the first MOS gate to the drift region, and between the low voltage terminal and the first MOS gate, wherein inversion layer channels are formed under said first and second MOS gates on operation of said first and second MOS gates, the device having at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates, wherein if the inversion layer channels are electron channels then the or each relatively highly doped region is n type and if the inversion layer channels are hole channels then the or each relatively highly doped region is p type, wherein the relatively highly doped region is more highly doped than the relatively lowly doped region.