Patent ID: 7945806
Filing Date: 2011-05-17
Classification: H04L

Abstract:
1. A data processing apparatus comprising: initiator circuitry configured to initiate a transfer of payload data in a first clock cycle; recipient circuitry configured to receive the payload data the subject of the transfer in a later clock cycle; a communication channel configured to pass the payload data from the initiator circuitry to the recipient circuitry via a payload path, the communication channel further configured to pass transfer control information associated with the transfer between the initiator circuitry and the recipient circuitry via a transfer control information path, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information; and timing easing circuitry located within the transfer control information path of the communication channel configured to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry, the timing easing circuitry configured to be responsive to a specified timing easing value to determine a time for which that transfer control information is temporarily buffered before being output to the recipient circuitry; wherein the number of clock cycles that elapse between the first clock cycle and the later clock cycle is dependent on the specified timing easing value; and wherein the payload data is not buffered by the timing easing circuitry and the payload path is configured to provide a multi-cycle path for transfer of the payload data from the initiator circuitry to the recipient circuitry between the first clock cycle and the later clock cycle.