Patent ID: 7763540
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a first dielectric layer over a semiconductor device, the semiconductor device comprising a gate, source and drain regions, and a first liner formed on the gate and source and gate regions, wherein the first dielectric layer is formed over the source and drain regions to approximately the height of the gate; forming a second liner on the first dielectric layer, the second liner over the source and drain regions being at approximately the same height as the height over the gate of the first liner; forming a second dielectric layer on the second liner; using chemical mechanical polishing, removing the second dielectric layer and a portion over the gate of the second liner to expose the first liner over the gate, leaving at least a portion of the second liner over the source and drain regions; using etching, removing a portion of the first liner exposed over the gate to expose a top of the gate; with the source and drain regions still covered by portions of the first liner and first dielectric layer, performing a gate silicidation process.