Patent ID: 9065628
Filing Date: 2015-06-23
Classification: H03J,H03K,H03L,H04L

Abstract:
1. A method of operation within an integrated circuit device, the method comprising: operating a clock generating circuit in a closed-loop operating state to generate an output clock signal that is frequency-locked with respect to an oscillatory input signal; detecting a transition of the oscillatory input signal from a first nonzero frequency to a second nonzero frequency; in response to detecting the transition of the oscillatory input signal, switching the clock generating circuit from the closed-loop operating state to an open-loop operating state to enable the output clock signal to oscillate at a first free-running frequency; determining a frequency ratio between the first free-running frequency of the output clock signal and the second nonzero frequency of the oscillatory input signal; adjusting a frequency-lock range of the clock generating circuit, based at least in part on the frequency ratio, to transition the output clock signal from the first free-running frequency to a second free-running frequency; and after adjusting the frequency-lock range of the clock generating circuit and while the oscillatory input signal is oscillating at the second nonzero frequency, switching the clock generating circuit from the open-loop operating state to the closed-loop operating state to frequency-lock the output clock signal with respect to oscillatory input signal.