Patent ID: 7382168
Filing Date: 2008-06-03
Classification: H03K

Abstract:
1. A buffer circuit, comprising: a first buffer configured for operation with a first voltage supply having a first voltage level, an output node of the first buffer connected directly to an external pad of the buffer circuit, the first buffer being adapted to receive one of an input signal to the buffer circuit and a first signal indicative of the input signal and to generate a first output signal which is a function of the input signal, the first output signal being referenced to the first voltage level; a second buffer configured for operation with a second voltage supply having a second voltage level, the first voltage level being greater than the second voltage level, the second buffer being adapted to receive one of the input signal and a second signal indicative of the input signal and to generate a second output signal which is a function of the input signal, the second output signal being referenced to the second voltage level; and a controllable isolation circuit coupled between an output node of the second buffer and the external pad; wherein the buffer circuit is selectively operative in one of at least a first mode and a second mode in response to at least a first control signal, the isolation circuit being operative in the first mode to substantially isolate the second buffer from the external pad and being operative in the second mode to connect the output node of the second buffer to the external pad, the external pad being driven by the first output signal in the first mode and being driven by the second output signal in the second mode; wherein the output node of the second buffer is in a high-impedance state during the first mode, and the output node of the first buffer is in a high-impedance state during the second mode.