Patent ID: 6015736
Filing Date: 2000-01-18
Classification: H01L,Y10S

Abstract:
A method for providing at least one memory cell on a semiconductor comprising the steps of:(a) providing a tunneling barrier on the semiconductor;(b) providing at least one floating gate having a corner, a portion of the at least one floating gate including the corner being disposed substantially above the tunneling barrier; and(c) oxidizing the tunneling barrier, a portion of the semiconductor adjacent the at least one floating gate, and the portion of the at least one floating gate;wherein the portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate, the second rate being sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the at least one floating gate.