Patent ID: 7251765
Filing Date: 2007-07-31
Classification: G01R

Abstract:
1. A semiconductor integrated circuit, comprising: a first input circuit configured to receive a first input signal superimposing first data and a clock: a first delay circuit connected to the first input circuit, the first delay circuit generating a first delay clock and supplying the first delay clock to the first input circuit so that the first input circuit samples the first data from the first input signal in synchronization with the first delay clock: a second input circuit configured to receive a second input signal superimposing second data and a clock; a second delay circuit connected to the second input circuit, the second delay circuit generating a second delay clock and supplying the second delay clock to the second input circuit so that the second input circuit samples the second data from the second input signal in synchronization with the second delay clock; a first register connected to the first delay circuit to register a value of a first delay of the first delay clock; a second register connected to the second delay circuit to register a value of a second delay of the second delay clock; a clock supplying circuit connected to the first and second delay circuits and supplying a clock signal to the first and second delay circuits; a phase comparator connected to the first and second delay circuits to detect a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register, wherein the phase difference is compared with a test data in order to determine whether the first and second registers and the first and second delay circuits operate correctly.