Patent ID: 7076612
Filing Date: 2006-07-11
Classification: G06F,Y02D

Abstract:
1. A cache interface circuit, comprising: a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to said processor in response to processor requests; a main memory interface for issuing main memory access requests to a main memory and for receiving main memory data in response; a cache memory interface for issuing memory access requests to a cache memory, if operating in a cache mode, and for receiving cache memory data in response; a cache-bypass mode-control signal input for said processor to indicate a cache bypass mode, in response to a programmer instruction inserted in a program being executed by said processor explicitly for the purpose of switching to cache bypass mode, in which cache bypass mode memory access requests are serviced from said main memory; a power control output for switching off operating power to said cache memory in response to a command received at said cache-bypass mode-control signal input that indicates all memory access requests should be serviced from said main memory.