Patent ID: 8315123
Filing Date: 2012-11-20
Classification: G11C

Abstract:
1. A memory circuit comprising: an array of bit cells including a bit cell coupled to at least one bit line and a word line, said bit cell having a node storing a data value and a word line transistor configured to provide a current path between said node and a bit line of said at least one bit line with a conductance dependent upon a word line voltage of a word line signal upon said word line; and word line driver circuitry configured to control said word line voltage during a access to said bit cell: (i) to change during a first change period from a first voltage level at which said word line transistor has a low conductance to an intermediate voltage level at which said word line transistor has an intermediate conductance; (ii) substantially to maintain during a first delay period said intermediate voltage level; (iii) to change during a second change period from said intermediate level to a second voltage level at which said word line transistor has a high conductance; (iv) substantially to maintain during a second delay period said second voltage level; and (v) to change during a third change period from said second voltage level to said first voltage level; wherein said intermediate voltage level is between said first voltage level and said second voltage level.