Patent ID: 9136177
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method, comprising: forming a first layer of high-k insulating material above a first active region and a second active region defined in a semiconducting substrate; forming a sacrificial protection layer above said first layer of high-k insulating material; forming a patterned etch mask to cover said sacrificial protection layer above said first active region and expose said sacrificial protection layer above said second active region; performing one or more etching processes through said patterned etch mask to remove said first layer of high-k insulating material and said sacrificial protection layer from above said second active region while leaving said first layer of high-k insulating material and said sacrificial protection layer above said first active region; removing said sacrificial protection layer from above said first layer of high-k insulating material that is positioned above said first active region; forming a second layer of high-k insulating material above said first layer of high-k insulating material positioned above said first active region and above said second active region; forming at least one layer of metal above said second layer of high-k insulating material; and removing portions of said first and second layers of high-k insulating material and said at least one metal layer to thereby form a first gate stack positioned above said first active region and to form a second gate stack positioned above said second active region, wherein said first gate stack is comprised of at least said first and second layers of high-k insulating material and said at least one layer of metal and wherein said second gate stack is comprised of at least said second layer of high-k insulating material and said at least one layer of metal.