Patent ID: 7495465
Filing Date: 2009-02-24
Classification: H03K

Abstract:
1. A compensation circuit that compensates for process, voltage and temperature (PVT) variations in an integrated circuit, the integrated circuit including a plurality of functional modules, the compensation circuit comprising: a signal generator for generating a first signal and a second signal, wherein the signal generator includes a first comparator that receives a voltage reference signal and generates a reference current signal, an aligned process module connected to the first comparator and including a plurality of P-metal oxide semiconductor (PMOS) transistors from amongst the plurality of transistors, for generating the first signal using the reference current signal, whereby the first signal depends on aligned process corner for voltage and temperature associated with a plurality of transistors of the signal generator; and a skewed process module, coupled to the aligned process module and including at least one PMOS transistor and at least one N-metal oxide semiconductor transistor from amongst the plurality of transistors, for generating the second signal using the reference current signal, whereby the second signal depends on skewed process corners associated with the plurality of transistors of the signal generator; a first code generator, coupled to the signal generator and receiving the first signal, for generating a first calibration code based on the first signal; a second code generator, coupled to the signal generator and receiving the second signal, for generating a second calibration code based on the second signal; and a mapping module coupled to the first and second code generators for providing the first and second calibration codes to the plurality of functional modules, wherein the first calibration code compensates for the Aligned Process Corner, Voltage and Temperature variations associated with the plurality of functional modules, and the second calibration code compensates for the variations associated with the skewed process corners in the plurality of functional modules.