Patent ID: 8081523
Filing Date: 2011-12-20
Classification: G11C

Abstract:
1. A circuit with a memory array, comprising an array of memory cells, each cell having an output for producing an output signal; a plurality of sensing circuits, each at least coupled to the output of a respective one of the memory cells from a jointly addressable group of the memory cells, for comparing the output signal of the respective one of the memory cells with a reference signal to form a data signal from the output signal from the respective one of the memory cells; a reference generator circuit with inputs coupled to the outputs of the memory cells, and arranged to form the reference signal of the jointly addressable group of the memory cells; wherein each respective one of the memory cells of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells, the reference generator implementing the function so that the contributions are equalized for output signal values at more than a saturating distance above the reference signal, and that the contributions are equalized for output signal values at more than the saturating distance below the reference signal.