Patent ID: 6665209
Filing Date: 2003-12-16
Classification: G06F,G11C

Abstract:
A semiconductor circuit comprising:a first memory block having a plurality of first bit lines and a plurality of first SRAM memory cells coupled to said plurality of first bit lines; a second memory block having a plurality of second bit lines and a plurality of second SRAM memory cells coupled to said plurality of second bit lines; a first and second wiring line each laid over said first and second memory blocks and each extending in the direction of said plurality of first and second bit lines; a plurality of first MOSFETs, each having a source/drain path coupled between said first wiring line and each of said plurality of first bit lines, a plurality of second MOSFETs, each having a source/drain path coupled between said first wiring line and each of said plurality of second bit lines, a plurality of third MOSFETs, each having a source/drain path coupled between said second wiring line and each of said plurality of first bit lines, and a plurality of fourth MOSFETs, each having a source/drain path coupled between said second wiring line and each of said plurality of second bit lines.