Patent ID: 6204708
Filing Date: 2001-03-20
Classification: H03K

Abstract:
An improved master-slave flip-flop comprising:a master gating transistor pair having an input and an output, and first and second clock inputs, wherein the master gating transistor pair is conductive when the first and second clock inputs are at first and second logic levels, respectively, and is not conductive when the first and second clock inputs are at the second and first logic levels, respectively;a master latch having an input and an output, the master latch input coupled to the output of the master gating transistor pair, wherein the master latch will be set to a certain logic level that is the same as a logic level at the input of the master gating transistor pair when the master gating transistor pair is conductive, and will retain this certain logic level when the master gating transistor pair is not conductive;a slave gating transistor pair having an input and an output, and third and fourth clock inputs, wherein the slave gating transistor pair is conductive when the third and fourth clock inputs are at the first and second logic levels, respectively, and is not conductive when the third and fourth clock inputs are at the second and first logic levels, respectively, the input of the slave gating transistor pair is coupled to the master latch;a slave latch having an input and an output, the slave latch input coupled to the output of the slave gating transistor pair, wherein the slave latch will be set to a certain logic level that is the same as a logic level at the input of the slave gating transistor pair when the slave gating transistor pair is conductive, and will retain this certain logic level when the slave gating transistor pair is not conductive;a first clock generator having an input and an output, the output of the first clock generator is coupled to the first clock input of the master gating transistor pair;a second clock generator having an input and an output, the output of the second clock generator is coupled to the second clock input of the master gating transistor pair;a third clock generator having an input and an output, the output of the third clock generator is coupled to the third clock input of the slave gating transistor pair; anda fourth clock generator having an input and an output, the output of the fourth clock generator is coupled to the fourth clock input of the slave gating transistor pair;wherein,the first clock generator output logic level changes at a first input value biased toward the first logic level,the second clock generator output logic level changes at a second input value biased toward the second logic level,the third clock generator output logic level changes at the first input value biased toward the first logic level, andthe fourth clock generator output logic level changes at the second input value biased toward the second logic level,such that the first and second input values occur at mutually exclusive times;thereby preventing the master gating pair and slave gating pair from being conductive at the same time.