Patent ID: 6898659
Filing Date: 2005-05-24
Classification: G06F

Abstract:
1. An interface device for interfacing with a host by an m-bit unit, comprising: a first-in first-out (FIFO) memory for storing data; a flag signal generator circuit for generating a mode flag signal indicating whether a data transfer mode of the interface device is a multi-transfer mode where n-bit data is transmitted from the device to an n-bit bus, wherein n is integral times of m; an address checking circuit for generating a first detection signal and a second detection signal when the mode flag signal indicates the multi-transfer mode, the first detection signal indicating whether a first address from the host is a data width aligned address and the second detection signal indicating whether a second address from the host belongs to a data width aligned address range; and a control circuit for enabling m-bit data from the host to be stored in the FIFO memory as n-bit data in response to the first detection signal and the second detection signal, when the mode flag signal indicates the multi-transfer mode, wherein when the n-bit data is stored in the FIFO memory, the control circuit causes the stored n-bit data in the FIFO memory to be transmitted to the n-bit bus through a bus interface.