Patent ID: 8136014
Filing Date: 2012-03-13
Classification: G06F,G11C

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arrayed therein, the memory cells being capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage; a parity data adder circuit configured to add parity data for error correction to every certain data bits to be stored in the memory cell array; a frame converter circuit configured to uniformly divide frame data containing the data bits and the parity data into N pieces of subframe data; and a programming circuit configured to store the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits, wherein the parity data is stored in the N sub-pages in order beginning from a sub-page with the smallest variation in bits between adjacent threshold voltage states.