Patent ID: 9171516
Filing Date: 2015-10-27
Classification: G09G,G11C

Abstract:
1. A gate driver on array circuit, comprising multiple gate driver on array units connected in cascade, wherein the n-th gate driver on array unit of the gate driver on array circuit comprises a (n−2)-th signal input terminal, a (n+2)-th signal input terminal, a clock signal first input terminal, a clock signal second input terminal, a first low-level input terminal, a second low-level input terminal, a first output terminal and a second output terminal, wherein the first output terminal of the n-th gate driver on array unit is used to drive the active region of the array substrate; wherein, when the n-th gate driver on array unit is one of the third to the last first gate driver on array units, the (n−2)-th signal input terminal of the n-th gate driver on array unit is electrically connected to the second output terminal of the (n−2)-th gate driver on array unit; when the n-th gate driver on array unit is the first or the second gate driver on array unit, the (n−2)-th signal input terminal is used to input a pulse activation signal; when the n-th gate driver on array unit is one of the first to the last third gate driver on array units, the second output terminal of the n-th gate driver on array unit is electrically connected to the (n−2)-th signal input terminal of the (n+2)-th gate driver on array unit, and the (n+2)-th signal input terminal of the n-th gate driver on array unit is electrically connected to the first output terminal of the (n+2)-th gate driver on array unit; when the n-th gate driver on array unit is the last first or the last second gate driver on array unit, the second output terminal of the n-th gate driver on array unit is suspended, and the (n+2)-th signal input terminal is used to input a pulse activation signal; the first low-level input terminal is used to input a first low-level, the second low-level input terminal is used to input a second low-level, and the second low-level is less than the first low-level; the n-th gate driver on array unit of the gate driver on array circuit further comprises: a pulling-up driving unit, which is electrically connected with the (n−2)-th signal input terminal; a pulling-up unit, which is electrically connected with the pulling-up driving unit, the clock signal first input terminal, the first output terminal and the second output terminal, respectively; a first pulling-down unit, which is electrically connected with the clock signal first input terminal, the first low-level input terminal, the second low-level input terminal, the pulling-up driving unit and the pulling-up unit; a second pulling-down unit, which is electrically connected with the clock signal second input terminal, the first low-level input terminal, the second low-level input terminal, the first pulling-down unit, the pulling-up driving unit and the pulling-up unit; a third pulling-down unit, which is electrically connected with the (n+2)-th signal input terminal, the first low-level input terminal, the pulling-up driving unit, the pulling-up unit, the first pulling-down unit, the second pulling-down unit and the first output terminal; and wherein the input signals of the clock signal first input terminal and the clock signal second input terminal are a first clock signal, a second clock signal, a third clock signal or a fourth clock signal, the first clock signal and the third clock signal have opposite phases, the second clock signal and the fourth clock signal have opposite phases, and the waveforms of the first clock signal, the third clock signal and the second clock signal, the fourth clock signal are the same, but the initial phases are different.