Patent ID: 7424656
Filing Date: 2008-09-09
Classification: G01R

Abstract:
1. A clocking method for applying test patterns for detecting delay defects in cross-domain paths between interacting synchronous clock domains in a scan circuit, each said cross-domain path originating from a source memory element in one of said clock domains and terminating at a destination memory element in another of said clock domains and each said memory element forming part of a scan chain in said scan circuit, said scan method comprising the acts of: selectively aligning, for every test pattern either a capture edge or a launch edge of each domain clock with a corresponding edge of at least one other domain clock of said interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each clock domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain; and determining that a delay defect exists on a cross-domain path when a circuit response captured in its associated destination memory element is different from an expected response.