Patent ID: 6229331
Filing Date: 2001-05-08
Classification: G01R

Abstract:
An apparatus for inspecting patterns on semiconductor integrated devices, comprising:image pickup means for scanning patterns on first and second semiconductor integrated devices to form first and second images made of pixels represented with multivalued gray levels;an image memory for storing the first and second images;calculation means for sequentially reading the first and second images out of the image memory strip by strip, each strip consisting of at least two consecutive pixels aligned in one of row and column directions, and calculating an optimum grouping operator for a target pixel contained in the strip according to the gray levels of all pixels in the strip;grouping means for associating each pixel with a group according to a grouping operator calculated thus for the pixel;an image difference memory for storing gray level differences between the first and second images pixel by pixel;threshold setting means for setting an optimum threshold for each of the groups; anddefect detecting means for comparing the thresholds with the gray level differences pixel by pixel and detecting defects on any one of the first and second semiconductor integrated devices.