Patent ID: 6577149
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A test structure for detecting defects in a semiconductor wafer, comprising:An array of conduction units, said array having an upper side, a lower side, a left side, and a right side; a first set of test pads connected to conduction units situated along said left side of said array; a second set of test pads connected to conduction units situated along said right side of said array; a third set of test pads connected to conduction units situated along said upper side of said array; a fourth set of test pads connected to conduction units situated along said lower side of said array; a first set of conduction paths, each one of said first set of conduction paths running through a row of conduction units and connects one of said first set of test pads to one of said second set of test pads; a second set of conduction paths, each one of said second set of conduction paths running through a column of conduction units and connects one of said third set of test pads to one of said fourth set of test pads; wherein applying a predetermined set of test signals to said first, second, third, and fourth set of test pads, the location of a defect is determined from the response signals measured from said first, second, third, and fourth set of test pads.