Patent ID: 8580636
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A method for manufacturing a high integrated phase change memory device, the method comprising: providing a semiconductor substrate having a cell area and a peripheral area defined therein; forming a plurality of impurity regions formed in the cell area of the semiconductor substrate and the plurality of impurity regions extending parallel to each other in a first direction thereby forming a striped pattern; forming a gate electrode in the peripheral area of the semiconductor substrate and simultaneously forming a plurality of dummy gate electrodes in the cell area of the semiconductor substrate, wherein the dummy gate electrodes extend parallel to each other in a second direction that is perpendicular to the first direction; forming an interlayer dielectric layer pattern that forms a lattice structure in conjunction with the dummy gate electrodes such that the interlayer dielectric layer pattern covers the peripheral area and exposes portions of the plurality of impurity regions; and forming a PN diode in the exposed portions of the plurality of impurity regions.