Patent ID: 6727642
Filing Date: 2004-04-27
Classification: H01J

Abstract:
A double panel type flat field emitter display, consisting of a plurality of unit cells, each of the cells comprising:a front panel structure in which an anode is formed on a transparent front panel and coated with a phosphor; and a backing panel structure in which a cathode and a gate are formed on and beneath a channel insulator, respectively, underlaid by a backing panel, wherein the gate is configured to apply a voltage across the gate and the cathode, the cathode is covered with an insulating protective film and a protective gate, sequentially, in such a way that the protective gate is protruded toward a vacuum channel so that the edge of the protective gate is positioned above the cathode surface exposed to the vacuum channel, thereby protecting the emission spot from the high voltage exerted from the anode, the front panel structure being joined to the backing panel structure in a vacuum condition in such a way that the phosphor faces toward the cathode, wherein a low voltage is applied between the gate formed beneath the channel insulator and the cathode to emit electrons from a spot at which the fringe of the cathode is in contact with the channel insulator, to the vacuum channel, and a high voltage is applied to the anode to accelerate the emitted electrons and finally to collide them against the phosphor to luminesce, said emitted electrons being controlled in number by the voltage between the gate and cathode, said cells being arranged in a pattern to form a pixel which represents information.