Patent ID: 6407591
Filing Date: 2002-06-18
Classification: G06F,H03K

Abstract:
An apparatus comprising:a first amplifier that receives as inputs a clock signal and a reference clock signal, said first amplifier providing a first output; a first VDNMOS that receives said reference clock signal and outputs a modified reference clock signal; a second VDNMOS that receives said clock signal and outputs a modified clock signal; a second amplifier that receives said modified clock signal and said modified reference clock signal, said second amplifier providing a second output; a low swing detector that receives said modified reference clock signal and outputs a low swing signal indicative of a low voltage swing in said modified reference clock signal; a controller that receives said low swing signal and outputs a control signal if said low swing signal occurs for a predetermined number of times; and a multiplexer that receives said first output and said second output.