Patent ID: 6759285
Filing Date: 2004-07-06
Classification: H01L,Y10S

Abstract:
A method of forming a transistor comprising:providing a substrate having a conductive line disposed thereon, the conductive line comprising an insulating region, a conductive region and a silicide region; forming a first conductive material in electrical communication with the conductive line, the first conductive material having an upper surface; covering the upper surface with an insulative material; forming a structure over the insulative material, the structure comprising an SiO2 layer and a second conductive material over the SiO2 layer, the structure having a pair of opposing sidewalls having a lower portion comprising exposed SiO2 and an upper portion comprising exposed second conductive material; depositing a dielectric layer over the structure, over the insulative material and covering the pair of opposing sidewalls; without photomasking after the depositing, anisotropically etching the dielectric material to form insulative spacers that cover less than the entirety of the pair of opposing sidewalls; and forming an electrically conductive link between the first and second conductive materials, the electrically conductive link being in electrical contact with a portion of sidewall not covered by the insulative spacer.