Patent ID: 6924228
Filing Date: 2005-08-02
Classification: H01L

Abstract:
1. A method of forming a via contact structure, the method comprising the steps of: forming a lower interconnection line over a semiconductor substrate; sequentially forming an inter-metal dielectric layer and a hard mask layer on an entire surface of the semiconductor substrate having the lower interconnection line; patterning the hard mask layer and the inter-metal dielectric layer to form a via hole exposing the lower interconnection line; forming a sacrificial layer filling the via hole on the hard mask layer; forming an anti-reflective layer on the sacrificial layer; patterning the sacrificial layer, the anti-reflective layer, and the hard mask layer to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole, and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern; partially etching the inter-metal dielectric layer using the hard mask pattern as an etching mask to form a trench crossing over the via hole; and removing the second sacrificial layer pattern to expose the lower interconnection line.