Patent ID: 8258029
Filing Date: 2012-09-04
Classification: H01L

Abstract:
1. A method of forming a non-volatile memory cell comprising: (i) providing a semiconductor substrate having a main surface; (ii) forming an ion implantation resistant layer on the main surface of the memory array region; (iii) implanting N-type ions to form a channel region below the main surface of the semiconductor substrate, wherein the channel region has a doping type different from a doping type of the semiconductor substrate; (iv) removing the ion implantation resistant layer applied in step (ii); (v) depositing a first at least one dielectric layer and at least one charge trapping layer above the main surface of the semiconductor substrate, the at least one charge trapping layer disposed above the first at least one dielectric layer; (vi) forming an ion implantation resistant layer on the surface of the charge trapping layer outside a first and second source/drain target region below the main surface of the semiconductor substrate; (vii) implanting N-type ions to form a first and second source/drain region below the main surface of the semiconductor substrate; (viii) removing the ion implantation resistant layer applied in step (vi); (ix) depositing at least two wordline material layers on the surface of charge trapping layer; (x) forming an ion implantation layer on the surface of the wordline material layer; (xi) etching the wordline material layer for planarization; (xii) implanting P-type ions to form an insulating region below the main surface of the semiconductor substrate outside the region of the main surface with the wordline material layer disposed above; (xiii) removing the ion implantation resistant layer applied in step (x); (xiv) depositing an insulating layer on the surface of the charge trapping layer between the wordline material layers; and (xv) etching the insulating layer for planarization.