Patent ID: 8649460
Filing Date: 2014-02-11
Classification: G11C,H03K,H03M,H04L

Abstract:
1. A system for multi-wire encoding with an embedded clock, the system comprising: a first transmitter component, a first receiver component, and a first set of wires coupling the first transmitter component to the first receiver component; the first transmitter component being configured to: the first receiver component being configured to: a second transmitter component, a second receiver component, and a second set of wires coupling the second transmitter component to the second receiver component; the second transmitter component being configured to encode a second set of symbols by representing each symbol with a combination of signal levels transmitted on the second set of wires; and the second receiver component being configured to receive and decode the second set of encoded symbols under timing control of the receive clock; wherein the transmission of the first set and the second set of wires are grouped to reduce inter-symbol interference among the first set and the second set of encoded symbols.