Patent ID: 7095661
Filing Date: 2006-08-22
Classification: G11C

Abstract:
1. A semiconductor memory module, on which a plurality of semiconductor memory elements each having terminals for data signals, address/control signals, and clock signals are mounted, the semiconductor memory module comprising: clock signal lines wired so that said clock signals are in phase with the semiconductor memory elements; data signal lines wired to the semiconductor memory elements so as to have the same length; a register setting said address/control signals; and an address/command signal line wired in a daisy-chain shape to said semiconductor memory elements from said register, wherein each of said semiconductor memory elements has a variable delay circuit with respect to said address/control signals or to said clock signals for taking in said address/control signals, and a delay amount of said variable delay circuit is set so that the sum of said delay amount and a wiring delay time due to a wiring from said register becomes equal to a wiring delay time from said register to the farthest one among said semiconductor memory elements, or a delay amount of said variable delay circuit is set so that the sum of said delay amount and arrival timing of said clock signals to said semiconductor memory elements becomes equal to a wiring delay time from said register to said semiconductor memory elements.