Patent ID: 6539505
Filing Date: 2003-03-25
Classification: G01R,G11C

Abstract:
A semiconductor memory, comprising:a plurality of memory banks including a first memory bank and at least one second memory bank, each memory bank having memory cells; a test device connected to said memory banks, said test device being programmed to test the semiconductor memory by writing a predetermined data value to a memory cell of said first memory bank, reading out the data value from the memory cell of said first memory bank, comparing the read-out data value with the predetermined data value in order to determine a data value for the comparison result, by buffer-storing the data value for the comparison result in a memory cell of said second memory bank, and by reading out the stored data value for the comparison result for carrying out a redundancy analysis in which defective memory cells of said first memory bank are replaced by redundant memory cells; and a changeover device connected to each of said memory banks, said changeover device containing a multiplexer having an input and an output and a demultiplexer having an input and an output, said changeover device being connected to receive a respective address for selecting a memory bank, a terminal for a data signal of said memory bank connected to said output of said multiplexer and said input of said demultiplexer, said input of said multiplexer and said output of said demultiplexer each being connected to a signal line for the predetermined data value to be stored and the data value to be read out subsequently, and to a signal line for the data value for the comparison result to be written and to be read out subsequently.