Patent ID: 8058157
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A method for fabricating a structure comprising: forming a semiconductor fin over a substrate; and forming a gate electrode over the semiconductor fin, the gate electrode having a first stress in a first region located nearer the semiconductor fin and a second stress which is different than the first stress in a second region located further from the semiconductor fin, wherein said forming the gate electrode comprises providing a patterned gate electrode conductor material over said semiconductor fin, ion implanting into said patterned gate electrode conductor material to form a partially amorphized gate electrode comprising an unamorphized sub-layer located nearer the semiconductor fin and an amorphized sub-layer located further from the semiconductor fin, forming a stress imparting layer atop the partially amorphized gate electrode, performing a thermal annealing, said thermal annealing recrystallizes said amorphized sub-layer, while introducing stress to the recrystallized sub-layer forming the second region of the gate electrode, and removing the stress imparting layer, and wherein said unamorphized sub-layer provides said first region of the gate electrode.