Patent ID: 7199420
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a memory region provided on said semiconductor substrate, said memory region including a first transistor provided on a main surface of said semiconductor substrate, a first insulating layer covering said first transistor, a capacitor element formed on said first insulating layer, and a plurality of capacitor contact plugs connecting a diffusion layer of said first transistor and said capacitor element; a logic region provided on said semiconductor substrate, said logic region includes a second transistor provided on said semiconductor substrate and covered with said first insulating layer, an interconnect layer formed on said first insulating layer; and a boundary region located between said memory region and said logic region, provided on said semiconductor substrate, said boundary region including a dummy contact plug having its upper surface covered with an insulating layer and located in the same layer as said capacitor contact plug; wherein a conductive layer and a capacitor layer constituting said capacitor element are terminated at a position closer to an inner region of said memory region than said dummy contact plug is.