Patent ID: 6639861
Filing Date: 2003-10-28
Classification: G11C

Abstract:
An integrated memory, comprising:a sense amplifier; a terminal for a test mode signal; controllable switching devices connected to said sense amplifier and having control inputs; a memory cell array having memory cells, word lines connected to and selecting said memory cells, and bit lines connected to said memory cells for reading out or writing data signals to/from said memory cells, said bit lines connected to said controllable switching devices and, for reading out a data signal, said bit lines in each case can be coupled to said sense amplifier through one of said controllable switching devices; and a control circuit having an output connected to said control inputs of said controllable switching devices, said control circuit having an input connected to said terminal for the test mode signal, said control circuit configured in such a way that, within an access cycle, a respective switching device of said controllable switching devices can be switched into a non-conducting state on account of an active state of the test mode signal.