Patent ID: 8102743
Filing Date: 2012-01-24
Classification: G11B

Abstract:
1. A phase-locked loop circuit that generates a clock signal synchronized with an input signal with a predetermined frequency, comprising: an oscillator configured to oscillate and generate the clock signal; a converter configured to convert the input signal into a digital signal using the clock signal generated by the oscillator as a sampling clock; a frequency divider configured to divide a frequency of the clock signal generated by the oscillator to generate a comparison clock signal and send the comparison clock signal as a feedback; a normalizer configured to normalize an amplitude value of the digital signal generated by the converter; and an oscillation controller configured to control a phase of the clock signal generated by the oscillator so as to reduce a phase difference between the normalized digital signal generated by the normalizer and the comparison clock signal sent as a feedback by the frequency divider, wherein the normalizer includes: an amplitude measurement circuit configured to measure the amplitude value of the digital signal generated by the converter; a delay circuit configured to delay the digital signal generated by the converter by a time involved in measurement performed by the amplitude measurement circuit; and a divider circuit configured to divide the delayed digital signal generated by the delay circuit by the amplitude value measured by the amplitude measurement circuit.