Patent ID: 7667261
Filing Date: 2010-02-23
Classification: H01L

Abstract:
1. A split-gate memory cell, comprising: a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a continuously doped source region along a second direction formed in the semiconductor substrate, wherein a top level of the active regions is lower than a top level of the isolation regions; a pair of floating gates disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the pair of floating gates to prevent thinning from CMP; a pair of control gates self-aligned with the pair of floating gates and disposed on the pair of floating gates along the second direction; an oxide layer conformably and continuously formed along the continuously doped source region and a sidewall of a stacked structure of the floating gates and the control gates; a source line between the pair of control gates along the second direction; and a pair of select gates disposed on outer sidewalls of the pair of control gates respectively along the second direction, wherein the first direction is perpendicular to the second direction.