Patent ID: 8976563
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A semiconductor memory device having a hierarchical bit line architecture, the semiconductor memory device comprising: a first sub-memory array including a plurality of memory cells coupled in common to first sub bit lines in a cross-point manner; a second sub-memory array including a plurality of memory cells coupled in common to second sub bit lines in a cross-point manner; main bit lines including a first main bit line and a second main bit line, the first main bit line being coupled to one of the first sub bit lines via a first switching transistor, and the second main bit line being coupled to one of the second sub bit lines via a second switching transistor; and sense amplifiers including a first sense amplifier and a second sense amplifier, the first and second sense amplifiers being coupled to the main bit lines such that the main bit lines are arranged in a folded bit line structure, wherein: a total number of the first sub bit lines and the second sub bit lines is twice a number of the main bit lines, the first main bit line is connected to the first sense amplifier and extends over the second sense amplifier, the second main bit line is connected to the second sense amplifier and extends over the first sense amplifier, the first sense amplifier and the second sense amplifier are disposed in a sense amplifier region, and no memory cell is disposed in an area between the first sense amplifier and the second sense amplifier in the sense amplifier region in a plane view, and the first main bit line and the second main bit line are twisted in the sense amplifier region.