Patent ID: 7977783
Filing Date: 2011-07-12
Classification: H01L

Abstract:
1. A wafer level chip size package, comprising: a semiconductor die comprising: a first dielectric layer covering the passivation layer, the first dielectric layer comprising a first opening exposing the bond pad; a first redistribution layer formed on the first dielectric layer, the first redistribution layer being connected to the bond pad through the first opening; a second redistribution layer comprising a land, wherein the first redistribution layer is physically separated from the second redistribution layer on the first dielectric layer; a second dielectric layer covering the first redistribution layer and the second redistribution layer, the second dielectric layer comprising: a first Under Bump Metallurgy (UBM) layer formed on the land through the land opening; a second Under Bump Metallurgy (UBM) layer formed on the second dielectric layer, the second UBM layer connected to the first redistribution layer through the first redistribution layer opening and to the second redistribution layer through the via hole; and a solder ball on the first UBM layer.