Patent ID: 8605495
Filing Date: 2013-12-10
Classification: G11C,H01L

Abstract:
1. An integrated circuit, comprising: a plurality of bit lines and a plurality of word lines; and an array of memory cells passively coupled to the plurality of bit lines and the plurality of word lines, the memory cells in the array respectively including an anti-fuse element and an element of phase change material in series, the phase change material having a lower resistivity phase and higher resistivity phase; sense circuitry coupled to the array of memory cells, to sense whether a selected memory cell has a threshold below a read threshold; control circuitry coupled to the plurality of bit lines and the plurality of word lines to apply bias arrangements for operation of the memory cells, including: a first write bias arrangement to induce the higher resistivity phase in an active region of the element of phase change material of a selected memory cell establishing a first threshold for the selected memory cell below the read threshold, a second write bias arrangement to induce the higher resistivity phase in the active region of the element of phase change material of a selected memory cell establishing a second threshold for the selected memory cell above the read threshold; and a read bias arrangement to apply the read threshold to a selected memory cell.