Patent ID: 6285588
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A method to tighten the threshold voltage distribution curve in a memory device composed of multiple memory cells each having a source, a drain, a floating gate and a control gate, wherein the memory cells are organized in rows and columns with the rows being wordlines and the columns being bitlines, the method comprising:(a) applying a voltage of approximately 5 volts to the sources of all the memory cells;(b) allowing the drains of the all the memory cells to float; and(c) applying a negative voltage pulse followed by a positive voltage pulse to the control gates of all the memory cells, wherein a magnitude of the magnitude of the positive voltage pulse, a length in time of the positive voltage pulse, a length in time of the negative voltage pulse and a length in time between the negative voltage pulse and the positive voltage pulse is determined during a characterization procedure for the memory device.