Patent ID: 6710761
Filing Date: 2004-03-23
Classification: G09G

Abstract:
An active matrix device comprising:a plurality of pixels arranged in matrix form; a driver circuit for driving the plurality of pixels, said driver circuit comprising: a shift register circuit having a plurality of register circuits including a clocked inverter circuit and an inverter circuit connected in series; a plurality of digital data latch circuits having a first N-channel transistor and a second N-channel transistor in which the sources or drains are connected in series, P-channel transistor, and a digital data holding circuit, wherein: said clocked inverter circuit and said inverter circuit generate a timing signal on the basis of a clock signal, a clock back signal, and a start pulse inputted from outside, and feeds the timing signal to a register circuit neighboring said register circuit and a gate electrode of said second N-channel transistor; said P-channel transistor inputs a first electric current voltage to said digital data holding circuit in accordance with a reset signal that is inputted from outside to a gate electrode of the P-channel transistor; said first N-channel transistor takes in digital data inputted on the basis of said timing signal and feeds the digital data to the source or the drain of the second N-channel transistor; and the timing signal outputted from a register circuit neighboring said register circuit is fed to a gate electrode of said first N-channel transistor.