Patent ID: 6271773
Filing Date: 2001-08-07
Classification: G01R,H03L

Abstract:
A coherent sampling method comprising the steps of;digitizing (10) an input signal (1) sampled by a clock (3) to obtain a digital data (20);acquisition storing (30) for storing the digital data (20);synchronizing (100) with a trigger pulse as a reference trigger (RT1), which is applied after a first hold timing (h0) showing an end of a hold time duration (Tmh), among trigger pulses of a trigger (2) synchronizing the input signal (1) to recurrently obtain pulses as a synchronizing signal (52);operating a timebase (200) recurrentlyfor measuring a first time difference (Ts1) between a first pulse of the synchronizing signal (52) synchronizing with the first reference trigger (RT1) and a clock of timing (c1) of the clock (3) applied thereafter,for providing a second hold timing (h1), which shows an end of the hold time duration (Tmh), delayed by a delay time Td (=(Tc-Ts1) from a clock timing (c11) of the clock (3) applied just before the end of the hold time duration (Tmh), in which the delay time Td is a time difference between a clock cycle time (Tc) of the clock (3) and the first time difference (Ts1),for receiving a second pulse of the synchronizing signal (52) synchronizing with a second reference trigger (RT2) of the trigger (2), andfor measuring a second time difference (Ts2) between the second pulse of the synchronizing signal (52) and a clock of timing (c13) of the clock (3) applied thereafter;processing (40) recurrently,for determining a number of time bins M(=Tc/Tres) by dividing the clock cycle time (Tc) by a predetermined time resolution (Tres),for getting a time difference variation .delta.Ts(=Ts2-Ts1) between the first time difference (Ts1) and the second time difference (Ts2),for obtaining a reference trigger time period (Trr) between the first reference trigger (RT1) and the second reference trigger (RT2),for seeking coherent sampling conditions, by finding an integer Y that is a number (Floor[Trr/Tcr]) of pulses of the reference clock (RC) with a clock cycle time Trc for the reference trigger time period Trr, and by finding an integer X (Ceiling or Floor[Mod[Trr,Tcr](M/Tcr)]) that is prime to and is less than the number of time bins M,for calculating a new clock cycle time (Tc1) given by an equation of Tc,Tc=Trr/(Y+(X/M))for deciding a time position of the stored digital data (20) to be displayed on a basis of the first and second reference triggers (RT1 and 2) and of each of time points (SP) sampled by the clock (3), andfor instructing (48) to store waveform data to be displayed;generating (300) recurrently the clock (3) of the new clock cycle time (Tc1) so as to satisfy the coherent sampling conditions; andstoring (50) the waveform data to be displayed by the instruction (48) of the processing (40) step.