Patent ID: 8614135
Filing Date: 2013-12-24
Classification: H01L

Abstract:
1. A method of manufacturing a phase change memory device having a memory cell array region containing an array of memory cells and a peripheral circuit region containing transistors for driving the array, the method comprising: providing a substrate having an upper surface and which includes a semiconductor substrate, a word line at an upper portion of the semiconductor substrate in the cell array region, a layer of phase-change material disposed on and electrically connected to the word line, and a bottom metal stud exposed at the upper surface of the substrate and contacting the word line; and performing a damascene process comprising: forming on the upper surface of the substrate an insulation layer that covers the layer of phase-change material and the bottom metal stud, forming a phase change contact hole that extends through the insulation layer and exposes the layer of phase-change material, forming a top word line contact hole that extends through the insulation layer and exposes the bottom metal stud, forming both a top electrode on the layer of phase-change material and a bit line on the top electrode within the phase change contact hole, wherein the bit line is self-aligned with the top electrode, and forming a second metal stud in the top word line contact hole and in contact with the bottom metal stud.