Patent ID: 6579809
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A method for forming a field effect transistor gate which is narrow, comprising:depositing a high-k gate dielectric etch stop layer on a silicon wafer substrate; depositing a polysilicon layer on the gate dielectric etch stop layer; depositing a hard mask layer on the polysilicon layer; depositing a photoresist on the hard mask layer; patterning the photoresist to form a photoresist mask over a gate region and expose a photoresist erosion region; developing the photoresist so as to remove the exposed photoresist within the erosion region thereby leaving a photoresist mask in the gate region; trimming the photoresist mask to form a narrow photoresist mask in a narrow gate region, the narrow gate region being within the gate region and smaller than the gate region; etching the hard mask layer to form a hard mask over the narrow gate region; etching the portion of the polysilicon layer which is not covered by the hard mask; and etching the portion of the high-k gate dielectric etch stop layer which is not covered by the hard mask, wherein, after developing the photoresist so as to remove all exposed photoresist erosion region, placing the substrate within an enclosed high density plasma etching environment and performing the remaining steps in-situ.