Patent ID: 6191630
Filing Date: 2001-02-20
Classification: H03K

Abstract:
A delay circuit for delaying input signal having an inverter in which field-effect transistors of different channels are serially connected, a connection between the transistors is adopted as an output terminal of the inverter and input signals are applied to gates of the field-effect transistors, a capacitor connected to the output terminal of said inverter, and a discrimination circuit for discriminating a signal that appears at the output terminal of said inverter, said delay circuit comprising:a charging current control circuit connected to the gate of one of the field-effect transistors for controlling, on the basis of an input signal and a first delay time control signal, a charging current that flows into said capacitor; anda discharge current control circuit connected to the gate of the other of the field-effect transistors for controlling, on the basis of the input signal and a second delay time control signal, a discharge current from said capacitor.