Patent ID: 7009900
Filing Date: 2006-03-07
Classification: G11C

Abstract:
1. A circuit for reading out, evaluating and rewriting a charge state to a memory cell, the circuit comprising: a bit line; a memory cell coupled to the bit line; a reference bit line; a reference memory cell for providing a comparison potential, the reference memory cell being coupled to the reference bit line; a first n-channel field-effect transistor that includes a gate terminal coupled to the bit line and a drain terminal coupled to the reference bit line; a second n-channel field-effect transistor that includes a gate terminal coupled to the reference bit line and a drain terminal coupled to the bit line; a first p-channel field-effect transistor that includes a gate coupled to the bit line and a drain terminal coupled to the reference bit line; a second p-channel field-effect transistor that includes a gate terminal coupled to the reference bit line and a drain terminal coupled to the bit line; a first voltage source coupled to a source terminal of the first n-channel field effect transistor and to a source terminal of the second n-channel field-effect transistor, the first voltage source for driving a voltage potential from an upper through to a lower limit; and a second voltage source coupled to a source terminal of the first p-channel field effect transistor and to a source terminal of the second p-channel field-effect transistor, the second voltage source for driving a voltage potential from the lower through to the upper limit; wherein the first and second n-channel field-effect transistors have a first threshold voltage and the first and second p-channel field-effect transistors have a second threshold voltage and wherein the magnitudes of the threshold voltages of the first and second n-channel and the first and second p-channel field-effect transistors are in each case greater than half the potential difference between the upper and lower limits of the voltage potential.