Patent ID: 6298004
Filing Date: 2001-10-02
Classification: G06F,G11C,H03K,H03L

Abstract:
A semiconductor device, comprising:a clock input circuit receiving an external clock;a data output timing control circuit including a real delay circuit, the real delay circuit coupled to said clock input circuit for delaying an input signal for a delay time responsive to an output of one phase comparison circuit, said real delay circuit outputting a data output timing signal so that the data output timing signal is maintained to have a predetermined phase relationship to the external clock;a data output circuit outputting data in response to the data output timing signalsaid data output timing control circuit further including a dummy delay circuit coupled to said clock input circuit to produce said delay time; anda 1/N divider (where N is an integer) dividing a frequency of a reference clock output from said clock input circuit, and an output of said 1/N divider is coupled to said dummy delay circuit.