Patent ID: 8084826
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; an element isolation region for electrically isolating a first active region in an N-channel region from a second active region in a P-channel region in the semiconductor substrate; an n-channel field effect transistor having an n-channel gate formed on the first active region with a gate insulating film interposed therebetween and a first source/drain region formed on both sides of the n-channel gate in the first active region; a p-channel field effect transistor having a p-channel gate formed on the second active region with a gate insulating film interposed therebetween and a second source/drain region formed on both sides of the p-channel gate in the second active region; an n-channel contact liner formed over the first active region and side surfaces and a top surface of the n-channel gate and having a shrinkage force; a p-channel contact liner formed over the second active region and side surfaces and a top surface of the p-channel gate, formed continuously with the n-channel contact liner so as to have a larger thickness than that of the n-channel contact liner, and having an expansion force; and a contact liner formed between the first active region and n-channel field effect transistor and the n-channel contact liner and between the second active region and p-channel field effect transistor and the p-channel contact liner, wherein: the n-channel contact liner and the p-channel contact liner are made of a same base material and contain different impurity atoms from each other, and the contact liner is made of the same base material as that of the n-channel contact liner and the p-channel contact liner and has a smaller density of the impurity atoms than that of the impurity atoms in the n-channel contact liner and the p-channel contact liner.