Patent ID: 9196351
Filing Date: 2015-11-24
Classification: G11C

Abstract:
1. A method for carrying out read and write operations in a synchronous memory device having a shared I/O, the method comprising: receiving a read command directed to a first internal memory bank during a first timeslot; activating the first internal memory bank to access read data at a read address requested by the read command; receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot; determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur; receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot; outputting, if it was determined that the data collision would not occur, the read data with the normal read latency on the shared I/O during a fourth timeslot; activating the second internal memory bank to write the write data to a write address requested by the write command; and outputting, if it was determined that the data collision would occur, the read data with read latency greater than the normal read latency to the shared I/O during a fifth timeslot later than the third timeslot.