Patent ID: 7219246
Filing Date: 2007-05-15
Classification: H03L

Abstract:
1. A digital system having selectable clock speed based upon available supply voltage, said digital system comprising: a clock oscillator at a first frequency; a phase-locked-loop (PLL) having a PLL oscillator at a second frequency, wherein the second frequency is a multiple of the first frequency; a voltage comparator having an input coupled to a supply voltage, and an output that is at a first logic level when the supply voltage is greater than a reference voltage and is at a second logic level when the supply voltage is less than or equal to the reference voltage; a clock multiplexer having a first input coupled to the PLL oscillator, a second input coupled to the clock oscillator and an output of either the clock oscillator or the PLL oscillator wherein selection thereof is controlled by the voltage comparator output such that when the voltage comparator output is at the first logic level the PLL oscillator is coupled to the clock multiplexer output and when the voltage comparator output is at the second logic level the clock oscillator is coupled to the clock multiplexer output; a PLL control register having a digital device coupled to PLL control register, wherein the digital device reads from and writes to the PLL control register.