Patent ID: 7253099
Filing Date: 2007-08-07
Classification: H01L

Abstract:
1. A method comprising: forming a conductive line structure on a semiconductor substrate; forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the conductive line structure; forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in the same direction as a length direction of the conductive line structure and covering the conductive line structure; forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask; forming a photoresist pattern on the second interlayer insulating layer; etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole, wherein the first interlayer insulating layer and the second interlayer insulating layer are selectively etched with respect to the etch inducing and focusing mask, said SAC hole exposing a portion of the conductive line structure and a portion of the semiconductor substrate adjacent to the conductive line structure; and filling a conductive material in the SAC hole to form a SAC pad.