Patent ID: 8688432
Filing Date: 2014-04-01
Classification: G06F

Abstract:
1. A method for speeding memory management unit (MMU) simulation with direct address mapping on a host system, the host system supporting a full-system simulator on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least a part of the guest system, wherein the border is a specific logical address and wherein the simulator may shift its own codes and data to a logical space region higher than the border, and reserve the region lower than the border as a safe region for use with the guest system, such that a guest effective address used in the guest system which is lower than the border may be considered as a host effective address in the host system, and may be directly mapped to a host physical address by the host MMU.