Patent ID: 6191006
Filing Date: 2001-02-20
Classification: H01L,Y10S

Abstract:
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said method comprising the steps of:preparing an intermediate layer sandwiched between a silicon layer and a III-V group compound semiconductor layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer; andsubjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450.degree. C.,wherein said intermediate layer comprises an amorphous semiconductor layer capable of preventing a threading dislocation from extending through said amorphous semiconductor layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer, andsaid amorphous semiconductor layer comprising an amorphous semiconductor being kept in an amorphous state after said heat treatment has been carried out.