Patent ID: 7414445
Filing Date: 2008-08-19
Classification: G06F,G11C,H03L

Abstract:
1. A device for synchronizing an input clock signal with an output clock signal, comprising: first variable, controllable delay means for generating a first clock signal and at least a second clock signal from a clock signal fed to the first delay means; second delay means reproducing the characteristics of the delay of devices processing the output clock signal; first phase comparing means for determining the phase between the input clock signal and a clock signal delayed by the second delay means; first control means for controlling the delay of the second clock signal in the first delay means in correspondence with the phase determined by the first comparing means; a bistable trigger circuit for controlling the edges of the clock signal fed to the first delay means; second phase comparing means for determining the phase between the first clock signal delayed by means of the first delay means and the input clock signal; and second control means for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparing means.