Patent ID: 8971135
Filing Date: 2015-03-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: an input/output circuit configured to receive an address and data from an exterior; and a peripheral circuit configured to receive the address through the input/output circuit and generate a chip selection signal based on the address, wherein the input/output circuit comprises: a control pad circuit configured to apply or block at least one data strobe signal in response to the chip selection signal; and one or more input/output pad circuits configured to transfer the data to the peripheral circuit in response to the at least one data strobe signal, wherein the control pad circuit is configured to receive an original data strobe signal from the exterior and apply the at least one data strobe signal based on the original data strobe signal, the at least one data strobe signal including a first data strobe signal that is substantially the same as the original data strobe signal and a second data strobe signal obtained by inverting the original data strobe signal.