Patent ID: 9105693
Filing Date: 2015-08-11
Classification: H01L,H05K

Abstract:
1. A method for fabricating a microelectronic structure comprising; forming a first dielectric layer over a substrate; forming a plurality of conductor layers embedded and planarized within the first dielectric layer and including a plurality of apertures interposed between the plurality of conductor layers, wherein a barrier layer is located upon a bottom and sidewall of each conductor layer; forming a plurality of capping layers aligned upon top surfaces of the plurality of conductor layers; forming a plurality of spacers adjoining a plurality of sidewalls of the plurality of capping layers and having a thickness less than or equal to a width of the barrier layers; forming a liner layer incompletely filling the plurality of apertures; and forming a second dielectric layer located upon the liner layer and enclosing a plurality of voids interposed between the liner layer and the second dielectric layer, and separating the plurality of conductor layers, wherein the plurality of voids extends within the first dielectric layer deeper than the plurality of conductor layers.