Patent ID: 6560731
Filing Date: 2003-05-06
Classification: G11C

Abstract:
A method for checking a functionality of an integrated semiconductor memory, which comprises the steps of:testing a first group of memory cells resulting in test results; buffer storing the test results, separately for each tested memory cell, in at least triple copies in a second group of the memory cells; performing a comparison between the copies of each of the test results; determining information about a functional capability of the memory cells of the first group in a manner dependent on the comparison of the copies; and accessing the memory cells by use of addresses, the addresses of the memory cells contain a first address part through which one of the first group and the second group of the memory cells is accessed, and a second address part through which the memory cells within one of the first group and the second group are accessed, the addresses of each the memory cells contain a number of address bits, and the second address part of a memory cell of the second group is generated, proceeding from a corresponding second address part of a respectively tested memory cell of the first group by an address transformation by alteration of at least one of the address bits.