Patent ID: 8543753
Filing Date: 2013-09-24
Classification: G06F,G11C

Abstract:
1. A multi-use physical (PHY) architecture comprising: a PHY connection including one or more bit lines, the PHY connection communicatively coupled to a first processor; the PHY connection configurable to carry signals between the first processor and a second processor, or between the first processor and a memory; the one or more bit lines configured to carry signals bi-directionally at a first voltage in a first setting for the PHY connection when the PHY connection is configured to carry signals between the first processor and the memory, wherein data is transferred over the one or more bit lines using a bursting strobe signal; and the one or more bit lines configured to carry signals uni-directionally at a second voltage in a second setting for the PHY connection when the PHY connection is configured to carry signals between the first processor and the second processor, wherein data is transferred over the one or more bit lines using a continuous clock signal and the second voltage different than the first voltage.