Patent ID: 6930361
Filing Date: 2005-08-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a surface; a gate electrode formed over the surface of said semiconductor substrate with a gate dielectric film interposed therebetween; a pair of source and drain diffusion layers formed in said semiconductor substrate to oppose each other with a channel region laterally residing therebetween at a location immediately beneath said gate electrode, said source and drain diffusion layers each having a low resistivity region and an extension region being formed to extend from this low resistivity region toward said channel region and being lower in impurity concentration and shallower in depth than said low resistivity region; first impurity doped layer of a first conductivity type, the channel region being formed in said first impurity doped layer of the first conductivity type between the source/drain diffusion layers; a second impurity doped layer of a second conductivity type formed under said first impurity doped layer; and a third impurity doped layer of the first conductivity type formed under said second impurity doped layer, wherein said three impurity doped layers make up a multilayer lamination structure with two p-n junctions, one between said first and said second impurity doped layers and the other between said second and said third impurity doped layer, wherein said first impurity doped layer is equal to or less in junction depth than the extension region of each of said source/drain diffusion layers, and wherein said second impurity doped layer is determined in impurity concentration and thickness to ensure that this layer is fully depleted due to a built-in potential creatable between said first and third impurity doped layers.