Patent ID: 7586609
Filing Date: 2009-09-08
Classification: G03F

Abstract:
1. A method for analyzing overlay errors in lithography, comprising: performing interfield sampling and intrafield sampling to sample a plurality of positions on a wafer; measuring an overlay error value at each of the positions; and using an overlay error model including coefficients of intrafield and interfield overlay errors of different types to fit the measured overlay error values with respect to the positions, wherein the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error, wherein a pattern of the interfield sampling comprises at least four fields having four different X-coordinates and four different Y-coordinates and the X-coordinates and the Y-coordinates are wafer coordinates relate to the center of the wafer, wherein each field is apart from a center of the wafer by at least 50% of a radius of the wafer, and an angle between any two fields with respect to the center of the wafer is at least 30°.