Patent ID: 6138226
Filing Date: 2000-10-24
Classification: G06F,Y02D

Abstract:
A data processor comprising:a central processing unit;a memory unit;a controller;a cache memory unit including a plurality of entries, wherein each of the entries includes logical address information and physical address information corresponding to the logical address information;wherein, in response to a logical address from the central processing unit, the controller compares information from the logical address and logical address information in an entry of the cache memory unit corresponding to the logical address;wherein, if the information from the logical address and the logical address information in the entry are coincident, a cache-hit results;wherein, if the information from the logical address and the logical address information are not coincident, the controller generates physical address information based on the logical address, and the controller compares the generated physical address information and the physical address information in the entry;wherein, if the generated physical address information and the physical address information in the entry are coincident, a cache-hit results; andwherein, if the generated physical address information and the physical address information in the entry are not coincident, the controller accesses the memory unit.