Patent ID: 7515502
Filing Date: 2009-04-07
Classification: G11C

Abstract:
1. A method comprising: fabricating a memory array comprising one or more memory blocks, each memory block of said one or more memory blocks comprising memory cells arranged in rows and columns; for each memory block of said one or more memory blocks, designating memory cells in one or more adjacent rings of memory cells nearest a perimeter of said memory block as dummy memory cells; selecting a set of one to all of said one or more memory blocks to create a set of selected memory blocks; for each memory block of said set of selected memory blocks and before a final fabrication level of said memory array, electrically connecting dummy memory cells of selected rows together, electrically connecting dummy memory cells of selected columns together or both electrically connecting dummy memory cells of selected rows together and electrically connecting dummy memory cells of selected columns together; for each memory block of said of said set of selected memory blocks and before said final fabrication level, testing said selected rows, selected columns or selected rows and columns of dummy memory cells of said; for each memory block of said of said set of selected memory blocks and after said testing, completing fabrication of said memory block to said final fabrication level; for each memory block of said of said set of selected memory blocks, connecting said dummy cells at opposite ends of said selected rows of dummy memory cells to normally fabricated first pads of said memory array; for each memory block of said set of selected memory blocks, connecting dummy cells at opposites ends of said selected columns of dummy memory cells to normally fabricated second pads of said memory array of said memory array; forming a fuse between one or more of said first pads and said selected rows of dummy memory cells; forming a fuse between one or more of said second pads and said selected rows of dummy memory cells; for each memory block of said one or more memory blocks, except for dummy memory cells, electrically connecting each memory cell in each row of said memory array to a respective wordline and each wordline to a respective wordline driver; for each memory block of said one or more memory blocks except for dummy memory cells, electrically connecting each memory cell in each column of said memory array to a respective bitline and each bitline to a respective bitline decoder; wherein said selected rows, selected columns or selected rows and columns of dummy memory cells are rows, columns or rows and columns along said perimeter of said memory blocks of said set of selected memory blocks; and wherein said memory cells are selected from the group consisting of static random access memory cells and dynamic access memory cells.