Patent ID: 6249856
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A microprocessor for executing a set of instructions, comprising:a register file including a first plurality of registers each for holding integer data, a second plurality of registers each for holding integer and floating point data, and a third plurality of registers each for holding Boolean data;a first functional unit that executes an integer operation in response to a first instruction, wherein said first instruction specifies a register to access within said first plurality of registers or said second plurality of registers, and wherein said first functional unit is adapted to access said first plurality of registers or said second plurality of registers as specified by said first instruction, to read an operand value from either said first plurality of registers or said second plurality of registers as specified by said first instruction, and to write a result value to said first plurality of registers or said second plurality of registers as specified by said first instruction; anda second functional unit that performs a Boolean combinational operation in response to a second instruction, wherein said second instruction specifies a register to access within said third plurality of registers, and wherein said second functional unit is adapted to access said third plurality of registers as specified by said second instruction, to read an operand value from said third plurality of registers as specified by said second instruction, and to write a result value to said third plurality of registers as specified by said second instruction.