Patent ID: 6977941
Filing Date: 2005-12-20
Classification: H04L

Abstract:
1. A packet switch for transferring variable length packets received by plurality of input line interfaces to at least one of output line interfaces on a fixed length data block unit basis, comprising: a shared buffer memory commonly used by said input line interfaces; a multiplexer connected to said input line interfaces for multiplexing the received packets from the input line interfaces on the fixed length data block unit basis and supplying fixed length data blocks to said shared buffer memory; and a buffer controller connected to said shared buffer memory for controlling writing and reading out of each of said fixed length data blocks to and from the shared buffer memory, wherein said buffer controller comprises: a first controller for forming a plurality of input queues corresponding to variable length packets by linking write addresses of fixed length data blocks, and for linking an input queue, of which the last fixed length data block of a variable length packet has been written to said shared buffer memory, to an output queue corresponding to a destination output line of the variable length packet, and a second controller for accessing a plurality of output queues, each of which corresponds to one of said output line interfaces, in accordance with a predetermined order and for reading out fixed length data blocks from said shared buffer memory based on the linked addresses associated with said output queues.