Patent ID: 7939383
Filing Date: 2011-05-10
Classification: H01L,H05K

Abstract:
1. A method for fabricating a semiconductor package, comprising the steps of: preparing a metal carrier; applying a first dielectric material layer over a surface of the metal carrier, and forming a plurality of openings through the first dielectric material layer; applying a conductive material in the openings of the first dielectric material layer; forming a first conductive layer on the first dielectric material layer and the conductive material, wherein the first conductive layer comprises a plurality of conductive traces; applying a second dielectric material layer over the first conductive layer, wherein a plurality of conductive vias are formed through the second dielectric material layer; forming a second conductive layer on the second dielectric material layer, the second conductive layer comprising a plurality of conductive traces, wherein each of the conductive traces of the second conductive layer has a terminal, and the conductive traces of the second conductive layer are electrically connected to the conductive traces of the first conductive layer by the conductive vias; mounting at least one chip on the second dielectric material layer, and electrically connecting the chip to the terminals of the conductive traces of the second conductive layer; forming an encapsulant for encapsulating the chip and the second conductive layer; and removing the metal carrier to partly expose the first dielectric material layer and the conductive material.