Patent ID: 8237457
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a dielectric layer located on a top surface of a semiconductor substrate; and an electrical antifuse located within a recessed area in said dielectric layer, wherein said electrical antifuse includes: an inner conductive material portion; a dielectric metal oxide portion laterally abutting and enclosing said inner conductive material portion; and an outer conductive material portion laterally abutting and enclosing said dielectric metal oxide portion, wherein said outer conductive material portion is separated from said inner conductive material portion by said dielectric metal oxide portion, wherein a topmost surface of said outer conductive material portion is substantially coplanar with a top surface of said dielectric layer, a top surface of said dielectric metal oxide portion, and a top surface of said inner conductive material portion.