Patent ID: 8390048
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A semiconductor device comprising: a non-volatile memory cell, a first MISFET and a second MISFET, the non-volatile memory cell including: a first gate insulative film formed over a first region of a semiconductor substrate; a control gate electrode formed over the first gate insulative film; a second gate insulative film having a charge accumulation layer and formed over the first region and one side wall of the control gate electrode; and a memory gate electrode formed over the second gate insulative film, the first MISFET including: a third gate insulative film formed over a second region of the semiconductor substrate; and a first gate electrode formed over the third gate insulative film; the second MISFET including: a fourth gate insulative film formed over a third region of the semiconductor substrate; and a second gate electrode formed over the fourth gate insulative film, wherein a gate length of the control gate electrode is smaller than a height of the control gate electrode, wherein a gate length of the memory gate electrode is smaller than a height of the memory gate electrode, wherein the thickness of the third gate insulative film is smaller than that of the fourth gate insulative film, and wherein the first and third gate insulative films have the same thickness.