Patent ID: 6048797
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A method of manufacturing interconnects, comprising the steps of:providing a substrate having an insulating layer formed thereon;forming a first dielectric layer, which comprises at least a trench being divided into a first part and a second part by a coupling region on the insulating layer, wherein the coupling region constitutes a part of the first dielectric layer;filling the first part and the second part of the trench with a conductive layer so as to form a first conductive section and a second conductive section, respectively;forming a second dielectric layer to cover the first dielectric layer, the first conductive section, and the second conductive section:forming a via hole in the second dielectric layer to expose the coupling region and a portion of the first conductive section and the second conductive section adjacent to the coupling region;removing the coupling region exposed by the via hole to form a contact hole, the contact hole exposing sidewalls of the first and the second conductive sections under the via hole and having a smaller cross-sectional area than that of the via hole; andforming a plug to fill the via hole and the contact hole, the plug being in contact with both the first conductive section and the second conductive section.