Patent ID: 6069513
Filing Date: 2000-05-30
Classification: H03K

Abstract:
A sequential logic network including a D-type flip-flop, having an input gate for transmitting signals to a bistable output circuit of the flip-flop, said input gate having first and second terminals, a signal input terminal which forms an input terminal of the network, and a signal output circuit node for connection to the bistable output circuit, and being controlled jointly with the bistable output circuit of the flip-flop by timing signals which are synchronized in a predetermined manner and applied to control terminals of the flip-flop, wherein the input gate comprises first, second, and third electronic switches, each having first, second and control terminals, the first and second switches being connected, in series with each other through their respective first and second terminals, between the input terminal of the input gate and the output node thereof, the third switch being connected, with its first and second terminals between the first terminal of the input gate and a network power supply line, and that the control terminals of the first and third switches and the second terminal of the input gate are connected to an output terminal of the flip-flop forming an output terminal of the network, timing signals synchronized in a predetermined manner being applied to the control terminal of the second switch.