Patent ID: 8576601
Filing Date: 2013-11-05
Classification: G11C,H01L

Abstract:
1. A content addressable memory, comprising: a pair of spin MOSFETs including: a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET, wherein the stored data includes three values of “1”, “0” and “Don't care”, wherein, when the stored data is “1” or “0”, the first spin MOSFET is set in a first magnetization state while the second spin MOSFET is set in a second magnetization state, so that resistances thereof are differentiated from each other, and wherein, when the stored data is “Don't care”, both of the first spin MOSFET and the second spin MOSFET are set collectively in the first magnetization state.