Patent ID: 8429335
Filing Date: 2013-04-23
Classification: G11C

Abstract:
1. A MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit; and a controller, coupled to the memory array and the inverse bit storage section for receiving an original data and outputting a first input data to the memory array, if the controller determines that a first threshold-voltage distribution of the original data is over a threshold situation, the controller generates the first input data by inverting bit values of a first portion of the original data but not inverting bit values of a second portion of the original data, so that the first input data and the original data have different threshold-voltage distribution; if the controller determines that a second threshold-voltage distribution of the original data is over the threshold situation, the controller generates the first input data by inverting the bit values of the first portion of the original data and the bit values of the second portion of the original data, so that the first input data and the original data have different threshold-voltage distribution; if the controller determines that a third threshold-voltage distribution of the original data is over the threshold situation, the controller generates the first input data by inverting the bit values of the second portion of the original data but not inverting the bit values of the first portion of the original data, so that the first input data and the original data have different threshold-voltage distribution; and if the controller determines that a fourth threshold-voltage distribution is over the threshold situation, the controller generates the first input data by not inverting the bit values of the original data.