Patent ID: 6100730
Filing Date: 2000-08-08
Classification: H03K

Abstract:
An improved dynamic flip flop divider, comprising:a PHCI, a first NHCI, and a second NHCI wherein the output of the PHCI is coupled to a first n-channel gate input of the first NHCI;an output of the first NCHI is coupled to a first n-channel gate input and a p-channel gate input of the second NHCI;an output of the second NHCI is coupled to a first p-channel gate input and an n-channel gate input of the PHCI;a clock signal coupled to a second p-channel gate input of the PHCI, and to a second n-channel gate input and a p-channel gate input of the first NHCI, and to a first n-channel gate input of the second NHCI;a first additional n-channel device having a source coupled to a ground supply, a drain to the output of the first NHCI, and a gate coupled to a junction between n-channel devices in the second NHCI; anda second additional n-channel device having a source coupled to the ground supply, a drain coupled to the output of the second NHCI, and a gate coupled to the output of the PHCI.