Patent ID: 6401164
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A memory device comprising:a plurality of independent memory sectors; an input interface for receiving external address signals and for converting the external address signals into internal address signals for addressing individual memory locations of the memory device, said internal address signals comprising internal memory sector address signals allowing for individually addressing each memory sector; memory sector selection means for selecting one of the plurality of memory sectors according to a value of the internal memory sector address signals; first and second internal memory sector address signal paths coupled to the input interface, the first internal memory sector address signal path being structured to receive the internal memory sector address signals and supply first internal sector signals to the memory sector selection means with no logic inversion compared to the internal memory sector address signals, and the second internal memory sector address signal path being structured to receive the internal memory sector address signals and supply to the memory sector selection means second internal sector signals with logic inversion compared to the internal memory sector address signals; and programmable means for activating either one or the other of the first and second internal memory sector address signal paths, such that when the first internal memory sector address signal path is activated, the internal memory sector address signals are associated with a first one of the memory sectors, and when the second internal memory sector address signal path is activated, the internal memory sector address signals are associated with a second one of the memory sectors.