Patent ID: 6391781
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a shallow trench isolation, comprising:providing a semiconductor substrate having a main surface thereof; selectively forming a silicon nitride pattern on the main surface of the substrate; forming a trench on the main surface of the substrate using the silicon nitride pattern as a mask; depositing a silicon oxide layer on the trench and the silicon nitride pattern so that not only the trench is filled with the silicon oxide layer but also the silicon nitride pattern is covered by the silicon oxide layer; etching the silicon oxide layer by a chemical-mechanical polishing so that a level of a surface of the silicon oxide layer is substantially same to that of the silicon nitride pattern; forming a spin-on-glass (SOG) layer on the etched silicon oxide layer and the silicon nitride pattern; etching back the SOG layer and the silicon oxide layer by a plasma etching process so that the SOG layer is completely etched and a level of the silicon oxide layer is lower than that of the silicon nitride pattern; and removing the silicon nitride pattern.