Patent ID: 7177893
Filing Date: 2007-02-13
Classification: G06F

Abstract:
1. A circuit for determining a result (s k+2 ) of an operation of a type where s k , a k , and a k+1 respectively are first, second, and third operands represented in a form of signed fractional numbers coded over n bits, the circuit comprising: first means for determining a positive and negative parts of the third operand (a second means for calculating a first sum (s) equal to the sum of the first, second, and third operands (s third means for calculating a first (S′) and a second (S″) indicators, the first indicator (S′) being equal to a first value if s fourth means for providing the first sum if the first indicator is equal to said first value, providing the second sum if the second indicator is equal to said third value, and providing the third sum in the other cases.