Patent ID: 7907439
Filing Date: 2011-03-15
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing said word lines, and memory cells connected at intersections of said word lines and bit lines, said cell arrays arranged along said bit line; an input/output controller provided on at least one side of an array of said cell arrays along said bit line and operative to control input/output of data in relation to access to a memory cell; a plurality of bit line gates provided between said cell arrays and between said input/output controller and an adjacent cell array, each being operative to establish a connection between said bit lines in adjacent cell arrays, and between said input/output controller and said bit line in said adjacent cell array; and a controlling circuit operative to form a data transfer path between said memory cell and said input/output controller by opening said bit line gates sequentially along a direction of data transfer, thereby establishing an electrical connection sequentially between said bit line in an adjacent pair of said cell arrays and between said input/output controller and said bit line in said adjacent cell array when said controlling circuit accesses to said memory cell.