Patent ID: 8013649
Filing Date: 2011-09-06
Classification: H03K

Abstract:
1. A dynamic clock feedback latch, comprising: a feedback path, configured to receive a clock input and one or more data inputs, and configured to generate a data value on an output as a function of the one or more data inputs in response to the clock input going low, and configured to generate a predetermined latching value on the output after a delay from the clock input going high; a first transistor, configured to provide a charge path from a charging source to a node to pre-charge the node to a high value while the clock input is low and to not provide the charge path while the clock input is high; a second transistor, configured to provide a drain path for selectively draining the node from the pre-charged high value to a low value while the clock input is high and to not provide the drain path while the clock input is low; a third transistor, coupled between the node and the second transistor and controlled by the output of the feedback path during the delay to drain the node to a low value through the second transistor drain path if the data value is high and to retain the node to the pre-charged high value if the data value is low; wherein the feedback path generates the predetermined latching value on the output after the delay from the clock input going high to cause to be latched onto the node an inverted value of the data value that was generated on the output as a function of the one or more data inputs.