Patent ID: 6180460
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, said cells comprising MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, said process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of said first polysilicon layer, a third step of etch of said first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of said second polysilicon layer, a fifth step of definition of said rows through self-aligned selective etch of said second polysilicon layer, of said intermediate dielectric layer and of said first polysilicon layer, said self-aligned selective etch determining in said source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during said third step, and a sixth step of dopant introduction in said regions of active area for the formation of regions of source and drain of said cells, characterized in that before said fourth step a selective introduction of dopant is provided in correspondence of regions of said common source lines in which said excavations will be formed, for the formation of doped regions deeper than said excavations.