Patent ID: 6742011
Filing Date: 2004-05-25
Classification: G06F

Abstract:
Summation circuitry for adding a column of partial product bits produced by a multiplier in multiplying a first operand and a second operand, said circuitry comprising:first summation circuitry configured to produce a first summation of a first portion of said partial product bits, said first summation defined by a first plurality of bits, said first summation circuitry having first and second linear arrays of adders, said first summation circuitry defining a plurality of adder levels, each of said adder levels defined by said first summation circuitry comprising a different adder from said first linear array and a different adder from said second linear array, wherein a plurality of partial product bits of said first portion are input into said first summation circuitry at different ones of said adder levels defined by said first summation circuitry; second summation circuitry configured to produce a second summation of a second portion of said partial product bits, said second summation defined by a second plurality of bits, said second summation circuitry having third and fourth linear arrays of adders, said second summation circuitry defining a plurality of adder levels, each of said adder levels defined by said second summation circuitry comprising a different adder from said third linear array and a different adder from said fourth linear array, wherein a plurality of partial product bits of said second portion are input into said second summation circuitry at different ones of said adder levels defined by said second summation circuitry; and a linear array of adders configured to receive and to add said first and second plurality of bits.