Patent ID: 6642760
Filing Date: 2003-11-04
Classification: H03K,H03L

Abstract:
A circuit for selectively delaying a reference clock signal, comprising:a phase splitter having a first output and a second output; a first delay line having a set of output taps, the first delay line being coupled to the first output; a second delay line having a set of output taps, the second delay line being coupled to the second output; a first multiplexor coupled to the set of output taps from the first delay line, the first multiplexor providing an output that is coupled to a first storage device; a second multiplexor coupled to the set of output taps from the second delay line, the second multiplexor providing an output that is coupled to the first storage device; and means for comparing an output of the first storage device to an input clock signal and generating a first control signal.