Patent ID: 6931516
Filing Date: 2005-08-16
Classification: G06F

Abstract:
1. A pipelined instruction decoder for a multithread processor, the pipelined instruction decoder comprising: an instruction decode pipeline to decode instructions associated with a plurality of instruction threads, the instruction decode pipeline having a predetermined number of pipe stages; a valid bit pipeline in parallel with the instruction decode pipeline, the valid bit pipeline having the same predetermined number of pipe stages in parallel with the predetermined number of pipe stages of the instruction decode pipeline, the valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline; and a thread identification pipeline in parallel with the instruction decode pipeline and the valid bit pipeline, the thread identification pipeline having the same predetermined number of pipe stages in parallel with the predetermined number of pipe stages of the instruction decode pipeline and the valid bit pipeline, the thread identification pipeline to associate a thread identification at each pipe stage with each instruction being decoded in the instruction decode pipeline.