Patent ID: 6216256
Filing Date: 2001-04-10
Classification: G06F

Abstract:
A method of design of a semiconductor IC comprising:a first step of providing, as selectable logical cells, a first logical cell comprising a flip-flop, a second logical cell comprising a flip-flop having the same characteristic as that of the flip-flop of the first logical cell and a delay element connected to a signal input terminal of that flip-flop, and a third logical cell comprising a flip-flop having the same characteristic as that of the flip-flop of the first logical cell and a delay element connected to a signal output terminal of that flip-flop,a second step of determining layout and interconnections in the semiconductor IC based on a given logical net without using the second and third logical cells and outputting layout information,a third step of performing logical simulation based on the layout information to obtain timing information,a fourth step of verifying the possibility of erroneous operation due to timing deviations by comparing the timing information with given design specifications, anda fifth step of determining layout and interconnections in the semiconductor IC by replacing a first logical cell with a second or third logical cell at a location determined to have a possibility of erroneous operation caused by timing deviations as a result of verification of the fourth step and outputting the layout information,wherein the fourth step determines there is a possibility of erroneous operation due to timing deviations for cascade-connected flip-flops controlled in timing by the same clock when the signal propagation delay for a clock signal path between any two first and second flip-flops connected in the cascade-connected flip-flops is greater than the sum of the signal propagation delay of the first flip-flop, the signal propagation delay of the signal path between the first flip-flop and the second flip-flop, and the difference between the setup time and the holding time of the second flip-flop, andwherein the fifth step replaces the first logical cell having the first flip-flop by the third logical cell or replaces the first logical cell having the second flip-flop by the second logical cell when it determines there is a possibility of erroneous operation caused by timing deviations as a result of the verification of the fourth step.