Patent ID: 7616041
Filing Date: 2009-11-10
Classification: H03K

Abstract:
1. A circuit for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input configured to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is received at said data input, is clocked into said at least one latch and passes to said data output along said forward data path; wherein at least one of said at least one latch comprises a retention latch configured to retain a signal value during said sleep mode, and said circuit further comprises a tristateable device, arranged between said forward data path and said retention latch, configured to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein said circuit is responsive to receipt of a second sleep signal received after said first sleep signal and configured to enter said sleep mode such that said portion of said circuit is powered down by reducing a voltage difference across said portion of said circuit, and a voltage difference across said retention latch and said tristateable device is maintained; said circuit further comprising an output device between said retention latch and said data output, and a driving device in data communication with an input of said output device; wherein said output device and said driving device are configured to enter said sleep mode on receipt of said second sleep signal; and said driving device is configured to drive an input of said output device in response to said second sleep signal not being asserted.