Patent ID: 6701476
Filing Date: 2004-03-02
Classification: G01R

Abstract:
A test access mechanism for a circuit under test, the circuit under test having a functional portion to be tested, the functional portion implementing one or more predetermined circuit functions, the test access mechanism comprising:a test portion coupled to the functional portion, the test portion having a plurality of inputs, each connected to a respective data path for receiving inputs to the circuit under test and coupling the data paths to respective inputs of the circuit under test in response to a first value of a test mode signal, the test portion being scannable to input predetermined test data at a scan input in response to a first value of a scan select signal and clock the predetermined test data through a scan path of the test portion, the predetermined test data being coupled to the circuit under test in response to a second value of the test mode signal, the test portion separately performing a built-in self-test in response to a second value of the scan select signal by using at least two feedback paths from predetermined points in the scan path and performing a predetermined logic function with one or more predetermined logic gates to provide to the circuit under test a series of built-in self-test data bits, the built-in self-test data bits are clocked through the scan path to provide test data to determine if transistors in the circuit under test are properly switching and to determine if correct signal transitioning timing is being met, the test portion using same shift register circuitry to implement scan path testing exclusive from built-in self-test and with commonly shared circuitry.