Patent ID: 7351620
Filing Date: 2008-04-01
Classification: H01L,Y10S

Abstract:
1. A method of forming a semiconductor construction, comprising: providing a substrate; forming an insulative material over the substrate; forming a crystalline layer over the insulative material; the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium; forming a field effect transistor having a transistor gate and a pair of source/drain regions; the field effect transistor gate being over the crystalline layer, and the field effect transistor having an active region extending into the crystalline layer; at least a portion of the source/drain regions being comprised by the active region within the crystalline layer; the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium; and forming a bipolar transistor having a collector region, emitter region and a base region; the collector region and emitter region both being elevationally above the transistor gate; the base region electrically connecting with one of the source/drain regions of the field effect transistor.