Patent ID: 6717868
Filing Date: 2004-04-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of column selecting switches for connecting one of a plurality of bit lines, each of which is connected to memory cells, and a data input/output line when a word line is activated based on at least one external control signal; a column selecting section for selecting a column selecting switch corresponding to at least one external address signal that has made address transition every time at least one external address signal makes address transition while the word line is in active state; at least one control-signal certifying section for outputting a certified control signal in case transition of a signal inputted to an external control terminal is certified valid as the external control signal; and at least one address certifying section for outputting at least one certified address signal in case transition of a signal inputted to an external address terminal is certified valid as the external address signal; wherein the column selecting section is controlled to be active in accordance with transition of a signal inputted to the external control terminal.