Patent ID: 8642434
Filing Date: 2014-02-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure comprising: providing a semiconductor substrate with a PFET area and an NFET area; masking said PFET area with a mask; forming an embedded silicon carbon alloy in source and drain regions in said NFET area; growing, by selective deposition of a silicon material, a silicon layer in said PFET area and NFET area, wherein said silicon layer is present on said embedded silicon carbon alloy layer in said source and drain regions in said NFET area, and said silicon layer is present on source and drain regions in said PFET area, and said silicon layer is essentially free of carbon and germanium; depositing a metal on said silicon layer; and reacting said silicon layer with said metal to form a contact material of a metal silicide essentially free of carbon.