Patent ID: 9148952
Filing Date: 2015-09-29
Classification: H01L,H05K

Abstract:
1. A wiring board comprising: a core layer; a first wiring layer and a first insulating layer stacked on one surface side of the core layer; a first via wiring embedded in the first insulating layer by filling metal in a via hole in the first insulating layer; a plurality of second insulating layers and a second wiring layer alternately stacked on an upper surface of the first insulating layer; a plurality of second via wirings embedded in the plurality of second insulating layers by filling metal in via holes in the plurality of second insulating layers, respectively; a third wiring layer and a third insulating layer stacked on another surface side of the core layer; and a solder resist layer stacked on the third insulating layer, wherein each of the first insulating layer and the third insulating layer is composed of a thermosetting insulating resin, wherein each of the second insulating layers is composed of a photosensitive resin, wherein an upper end surface of the first via wiring embedded in the first insulating layer exposes from the upper surface of the first insulating layer to be directly connected with the second wiring layer, wherein the second wiring layer, that is individually formed from the first via wiring, is formed to extend from the upper end surface of the first via wiring embedded in the first insulating layer toward the upper surface of the first insulating layer, on the upper end surface of the first via wiring and the upper surface of the first insulating layer, wherein the second wiring layer is connected to the first wiring layer via the first via wiring, wherein the upper surface of the first insulating layer and the upper end surface of the first via wiring embedded in the first insulating layer are polished surfaces, wherein the upper end surface of the first via wiring embedded in the first insulating layer and the upper surface of the first insulating layer are flush with each other, wherein the first insulating layer and the third insulating layer include the same number of layers at the one surface side and the other surface side of the core layer, respectively, and wherein the wiring density of the second wiring layer is higher than the wiring density of the first wiring layer; wherein a pad for mounting an electronic component is formed in the second insulating layer, wherein a pad to be connected to an external device is formed in the third insulating layer, wherein a third via wiring is embedded in the third insulating layer by filling metal in a via hole in the third insulating layer, the third via wiring being integrally formed with the pad to be connected to the external device, and wherein the solder resist layer is provided with an open portion that exposes the pad to be connected to the external device.