Patent ID: 9064885
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. An electrostatic discharge resistant diode comprising: a wafer, the wafer including a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer, a top surface of the BOX layer being in physical contact with the silicon layer and an opposite bottom surface of the BOX layer being in physical contact with the silicon substrate; an N-type well in the silicon substrate; a first vertical column of P+ doped epitaxial silicon over the N-type well and extending through the BOX layer and the silicon layer; a second vertical column of N+ doped epitaxial silicon over the N-type well and extending through the BOX layer and the silicon layer; and a dielectric layer in physical contact with the BOX layer, the first vertical column and second vertical column, the dielectric layer does not extend beyond and is parallel to the top surface of the BOX layer.