Patent ID: 8445965
Filing Date: 2013-05-21
Classification: H01L

Abstract:
1. A structure, comprising: a first region of a semiconductor substrate separated from a second region of said semiconductor substrate by trench isolation formed in said substrate; a first field effect transistor comprising a first source/drains on opposite sides of a first channel region formed in said first region and a first gate electrode formed over said first channel region; and a second field effect transistor comprising second source/drains on opposite sides of a second channel region formed in said second region and a second gate electrode formed over said second channel region a first stressed layer having a first thickness over first gate electrode, said first stressed layer over said first region, said first stressed layer extending over all of said first gate electrode and extending over all of said first source/drains; a second stressed layer having a second thickness over said second gate electrode, said second stressed layer over second region, said second stressed layer extending over all of said second gate electrode and extending over all of said second source/drains; said first stressed layer and second stressed layer separated by a gap; a conformal passivation layer having a third thickness measured over a top surface of said first gate electrode or measured over a top surface of said second gate electrode, said conformal passivation layer directly on top surfaces of said first and second stressed layers and regions of a top surface of said trench isolation in said gap, a top surface of said passivation layer following the contours of said top surfaces of said first and second stressed layers and extending over and sealing said gap, said conformal passivation layer extending over all of said first field effect transistor and all of said second field effect transistor; and wherein said third thickness is less than said first thickness and said third thickness is less than said second thickness.