Patent ID: 6097649
Filing Date: 2000-08-01
Classification: G11C

Abstract:
A method for refreshing a memory structure, the memory structure including a sense amplifier circuit, a plurality of bit lines and a plurality of complementary bit lines coupled to the sense amplifier circuit, a plurality of word lines and a plurality of reference word lines coupled to the plurality of bit lines and the plurality of complementary bit lines, and the plurality of word lines each including a plurality of memory cells, the method comprising the steps of:(a) precharging the plurality of bit lines and the plurality of complementary bit lines to a voltage higher than a reference voltage;(b) selecting at least one of the plurality of word lines and at least one of the plurality of reference word lines;(c) discharging the plurality of bit lines by the sense amplifier circuit to a voltage of a logic low when at least one of the plurality of memory cells residing on the at least one of the plurality of word lines and on the plurality of bit lines stores a logic low, and discharging the plurality of complementary bit lines by the sense amplifier circuit to a voltage of a logic low when the at least one memory cell stores a logic high, therein creating a voltage difference between the plurality of bit lines and the plurality of complementary bit lines;(d) refreshing the voltage of the plurality of bit lines to the plurality of memory cells on the at least one of the plurality of word lines; and(e) restoring the plurality of bit lines and the plurality of complementary bit lines to the reference voltage.