Patent ID: 6597550
Filing Date: 2003-07-22
Classification: H01L,H02M,H03K

Abstract:
A high voltage integrated circuit chip for driving first and second power transistors arranged in a halfbridge configuration which allows for excessive negative voltage swing of an output node between the transistors in the halfbridge configuration, comprising:a voltage source connection; a ground connection; a substrate for the high voltage integrated circuit chip; first and second gate drivers formed in an epitaxial layer disposed over the substrate for driving the first and second power transistors in series in the halfbridge configuration; and a resistor disposed over the epitaxial layer and electrically connected at one end thereof to the voltage source connection and at another end thereof to the ground connection and the substrate through the epitaxial layer to limit the current flowing through a parasitic diode of the high voltage integrated circuit due to negative voltage transients at the output node.