Patent ID: 6728133
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first memory array having a plurality of first memory cells each storing data of a single bit and having a first address space allocated in a fixed fashion in advance; a second memory array, arranged in a different region from a region of said first memory array and formed on common semiconductor substrate with said first memory array, having a plurality of second memory cells each storing data of multi bits and having a second address space allocated in a fixed fashion in advance, said first address space being non-overlapping with said second address space, the first memory cells and the second memory cells being each constituted of a stacked field effect transistor having a floating gate; a first control circuit provided corresponding to said first memory array for controlling writing, reading and erasing of data for the first memory cells of said first memory array; and a second control circuit provided separate from said first control circuit and corresponding to said second memory array for controlling writing, reading and erasing of data for the second memory cells of said second memory array, wherein at least one of control operations of programming and erasing for the first memory cells by said first control circuit is different from said at least one of control operations of programming and erasing for the second memory cells by said second control circuit.