Patent ID: 7663617
Filing Date: 2010-02-16
Classification: G02F

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line disposed on the substrate and extending in a first direction; a capacitive electrode separated from the gate line and elongated in a second direction; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line and including a drain electrode; a coupling electrode overlapping the capacitive electrode and connected to the drain electrode; and a pixel electrode including first and second subpixel electrodes connected to the drain electrode and a third subpixel electrode interposed between the first and second subpixel electrodes, the third subpixel electrode connected to the capacitive electrode and spaced apart from the first subpixel electrode by a first gap that overlaps the capacitive electrode and the coupling electrode.