Patent ID: 6425122
Filing Date: 2002-07-23
Classification: G06F

Abstract:
In a computing system including a host processor connected to at least one target processor unit having a target processor, a code memory, a shared memory, and a shared control register, wherein the code memory, shared memory and shared control register are accessible by the host and target processor, a method for controlling the execution of a target processor with a host processor, comprising the steps of:(a) causing the target processor to fetch and execute an instruction from a location in the code memory, the location being identified by a current instruction pointer stored in the instruction pointer register in the target processor; (b) causing the target processor to test a single-step flag in the control register after the execution of the instruction; (i) if the single-step flag is not set (c) causing the target processor to return to step (a); (ii) if the single-step flag is set, (d) causing the target processor to copy the instruction pointer of the processor into a mailbox location in the shared memory; (e) causing the target processor to interrupt the host processor; and (f) causing the target processor to stop execution of instructions.