Patent ID: 6694402
Filing Date: 2004-02-17
Classification: G06F

Abstract:
A method for controlling access of a memory having a number of erases that is limited on a block basis, the memory containing user memory blocks (NB0, NB1), which are available for user data bytes (DS0,-DS2), in a computer, by means of an address conversion using a pointer table (AZTO) containing address pointers (AP0,-AP1023) to the memory blocks, each associated with a counter, which is increased each time a predefined erase-state criterion for the associated memory block is reached, characterized in that the pointer table (AZTO) is held in a memory block, each counter representing an erase utilization class (LN0,-LN1023) to the associated memory block, after each reach of an erase-state criterion of a specific memory block with an initial pointer position (AP1), the erase utilization classes (LN0,-LN1023) of other memory blocks are searched in the pointer table (AZTO) for a lowest value with a minimum distance to the erase utilization class of the associated memory block and when such an erase utilization class is found, the associated address pointer and erase utilization class are swapped with corresponding address pointer and utilization class in the initial pointer position (AP1) and the contents of the memory blocks associated to those two address pointers are swapped as well, and after each write and/or erase operation of a user memory block (NR0,-NR1), the completeness of the operation is checked and, if required, the given process is repeated with an accordingly longer write time or erase time, which is then rated as the erase-state criterion.