Patent ID: 8243564
Filing Date: 2012-08-14
Classification: G11B

Abstract:
1. A misjudgment correction circuit, comprising: an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes; a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal; a clock pulse generation section configured to generate a uniform series of clock pulses; a full addition signal H/L time periods detection section operative to determine a high time period of the binarized full addition signal and a low time period of the binarized full addition signal; a push-pull signal H/L detection section operative to determine a number of high-level push-pull signals and low-level push-pull signals during the high time period for each clock pulse within the high time period of the binarized full addition signal and a number of high-level push-pull signals and low-level push-pull signals during the low time period for each clock pulse within the low time period of the binarized full addition signal; a majority decision calculation section configured to calculate the total number of high-level push-pull signals and the total number of low-level push-pull signals in each one of the high time period and the low time period of the binarized full addition signal and to determine which one of either the high-level push-pull signals or the low-level push pull signals constitutes a majority of high-level or low-level push-pull signals within the high time period and the low-time period of the binarized full addition signal; and a wave correction section configured to correct the push-pull signal by forming either a high-level signal or a low-level signal for each one of a push-pull high time period and a push-pull low time period of the push-pull signal corresponding to the high time period and the low time period of the binarized full addition signal as determined by the majority decision calculation section.