Patent ID: 7026224
Filing Date: 2006-04-11
Classification: B81C,H01L

Abstract:
1. A method for dicing semiconductor chips, comprising: providing a substrate having an upper substrate level, a middle substrate level and a lower substrate level; providing a plurality of empty spaces in the middle substrate level, the empty spaces being enclosed by a respective substrate frame area, each of the empty spaces being situated under a corresponding semiconductor chip area in the upper substrate level, each corresponding semiconductor chip being delimited by a semiconductor chip peripheral area in such a way that a particular substrate frame area is distanced from a vertical extension of the corresponding semiconductor chip peripheral area by a lateral intermediate space; providing at least one substrate support element in each of the empty spaces to bond the lower substrate level to a particular semiconductor chip area in the upper substrate level; severing the upper substrate level above the particular intermediate space along the particular semiconductor chip peripheral area to laterally separate the semiconductor chip areas; and dicing the semiconductor chip areas into semiconductor chips by severing the substrate support elements.