Patent ID: 6358828
Filing Date: 2002-03-19
Classification: H01L

Abstract:
A method of forming a pair of transistors having source-drain paths of said transistors connected in series to a power supply:providing a first transistor of said pair having a first gate conductor arranged upon a first substrate between a first source implant and a first drain implant; depositing an interlevel dielectric upon the first source implant, upon the first drain implant and upon the first gate conductor; forming a second substrate within said interlevel dielectric a spaced distance above and laterally offset from said first gate conductor; forming a conductive plug through said interlevel dielectric to said first drain implant, wherein said conductive plug abuts a lateral surface of said second substrate; forming a second transistor of said pair having a second gate conductor arranged upon said second substrate between a second source implant and a second drain implant, wherein said second source implant is proximate to said conductive plug; and patterning an interconnect across a portion of said second substrate in electrical communication with both said second substrate and said second source.