Patent ID: 6789173
Filing Date: 2004-09-07
Classification: G06F

Abstract:
A multiprocessor system of a main memory shared type having a plurality of nodes mutually connected to each other by signal lines, each of said plurality of nodes comprising:a CPU having a cache memory; a main memory; and a node controller for performing communication control between said CPU, main memory and the other nodes in said plurality of nodes, said node controller having: a communication controller for controlling communication interface to said other nodes; a crossbar, provided between said communication controller and said signal lines, for determining a processing sequence of ones of memory access requests to the main memories in said plurality of nodes issued from at least one of said plurality of nodes, and for multicasting a memory access request obtained from said signal line or said communication controller to all or fewer than all of said other nodes if the memory access request is needed to be multicasted for cache coherency control; and a bypass controller means for validating or invalidating said crossbar and forming, when said crossbar is to be invalidated, a first bypass line leading memory access requests on said signal line to said communication controller and a second bypass line leading memory access requests directed to said other nodes from said communication controller to said signal line.