Patent ID: 6735697
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A circuit arrangement for electronic data processing comprising:a writeable memory for storing data to be protected against unauthorized access, a read-only memory for storing individualizing data, a control unit for generating given control signals in dependence on a reset signal sequence to be executed by the control unit during operation of the circuit arrangement, a scrambling pattern generator for generating scrambling pattern signals by combining at least a part of the individualizing data from the read-only memory with the control signals during the execution of the reset signal sequence and for subsequently outputting these scrambling pattern signals until the execution of a next reset signal sequence, and a scrambling logic unit for the scrambling of address and/or data signals of the data to be stored in the writeable memory in conformity with the scrambling pattern signals supplied by the scrambling pattern generator upon storage of this data, and for the corresponding descrambling of the data signals upon reading out from the erasable memory.