Patent ID: 6118719
Filing Date: 2000-09-12
Classification: G11C

Abstract:
A method of selectively deactivating from a high power state to a reduced power state each individual bank of memory in a computer system having a plurality of banks of memory, each bank of memory having at least one memory chip wherein each of said individual banks of memory is provided with at least one control signal specific thereto, and wherein each of said individual banks of memory is activated to said high power state for a read/write operation by the said at least one control signal, comprising the steps of:determining the interval between successive read/write cycles to each respective individual bank of memory,deactivating said each respective individual bank of memory from said high power active state to said reduced power inactive state by circuitry within each memory chip in said respective individual bank of memory when the interval between successive read/write cycles to said each respective individual bank of memory is equal to or greater than a given value, andreactivating each respective individual bank of memory to the active high power state from the reduced power inactive state responsive to the first read/write cycle to each respective individual bank of memory when the respective individual bank of memory is in the inactive reduced power state.