Patent ID: 7506133
Filing Date: 2009-03-17
Classification: G06F

Abstract:
1. A method for accessing a device by a host using a dedicated bus, the device having up to 2 M memory locations, the bus having N data lines and at least two control lines, wherein M is greater than N, and the host performs an address cycle by asserting a first control signal and a data cycle by de-asserting the first control signal, comprising: (a) performing a first address cycle to transmit a first address portion over the bus during the first address cycle; (b) storing the first address portion in a first register of the device in response to detecting the first address cycle; (c) performing a second address cycle to transmit a second address portion over the bus during the second address cycle; (d) storing the second address portion in a second register of the device in response to detecting the second address cycle; (e) performing a first data cycle if the first and second address portions, when combined, form a first address for one of the memory locations; (f) if the first data cycle is a write data cycle, transmitting a first datum from the host to the device during the first data cycle, and storing the first datum at the first address in response to detecting the first data cycle; and (g) if the first data cycle is a read data cycle, transmitting a second datum from the device to the host during the first data cycle in response to detecting the first data cycle, the second datum being stored at the first address, wherein the second address cycle is immediately subsequent to the first address cycle, and the first data cycle is immediately subsequent to the second address cycle.