Patent ID: 6017802
Filing Date: 2000-01-25
Classification: H01L,Y10S

Abstract:
A semiconductor manufacturing process comprising:providing a semiconductor substrate;forming a gate dielectric on an upper surface of said semiconductor substrate, wherein said semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region;forming a conductive gate upon an upper surface of said gate dielectric, wherein said conductive gate includes a first and a second sidewall;forming a first pair of spacer structures on said first and second sidewalls respectively of said conductive gate, wherein exterior sidewalls of said first pair of spacer structures are displaced from said first and second sidewalls of said conductive gate approximately by a source displacement;introducing a first source impurity distribution into said first source region of said semiconductor substrate, wherein a channel boundary of said first source region is laterally displaced from said second sidewall of said conductive gate by said source displacement and further wherein said first source region extends to first source depth below said upper surface of said semiconductor substrate;forming a second pair of spacer structures on respective exterior sidewalls of said first pair of spacer structures such that exterior sidewalls of said second pair of spacer structures are laterally displaced from said first and second sidewalls of said conductive gate by a drain displacement; andintroducing a drain impurity distribution into said detached drain region of said semiconductor substrate wherein a channel boundary of said detached drain region is laterally displaced from said first sidewall of said conductive gate by said drain displacement.