Patent ID: 6014328
Filing Date: 2000-01-11
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device formed on a semiconductor substrate, comprising:a plurality of memory cells arranged in a plurality of rows and a plurality of columns;a plurality of word lines arranged correspondingly to said plurality of rows, respectively;a plurality of bit lines arranged correspondingly to said plurality of columns, respectively;a source line supplying a first potential;each of said plurality of memory cells including:a memory cell transistor, anda MOS transistor;each of said memory cell transistors including:a control gate carrying a potential controlled by corresponding one of said word lines,a source and a drain to be connected and disconnected together under the control by said potential on said control gate anda floating gate;each of said MOS transistors selectively opening and closing a conduction path of a current flowing between said bit line and said source line through said corresponding memory cell transistor;said plurality of MOS transistors belonging to the same row commonly using a gate layer;said nonvolatile semiconductor memory device further comprising:a plurality of metal interconnections corresponding to the same rows;each of said plurality of metal interconnections being arranged above corresponding one of said gate layers with an insulating film having a plurality of connection holes therebetween;each of said metal interconnections being connected to corresponding one of said gate layers through the corresponding one of said connection holes; andswitch select means for selectively supplying a potential to each of said metal interconnections in response to an external address signal.