Patent ID: 6084792
Filing Date: 2000-07-04
Classification: H02M,Y02B

Abstract:
In a DC-to-DC power converter generally having a transformer core electromagnetically coupled to respective primary and secondary windings, and wherein the transformer core is excited in response to a predetermined input signal received at the primary winding so that the secondary winding generates a switching signal having multiple levels of amplitude including, at least during a predetermined switching interval, an amplitude level corresponding to substantially zero amplitude, a first circuit module comprising:first and second input terminals for receiving the switching signal;a first power transistor having respective gate, drain and source terminals, the drain terminal of said first power transistor coupled to the first input terminal of the circuit module, the gate terminal of said first power transistor coupled to the second input terminal of the circuit module;a second power transistor having respective gate, drain and source terminals, the drain terminal of said second power transistor coupled to the second input terminal of the circuit module, the gate terminal of that second power transistor coupled to the first input terminal of the circuit module, and the respective source terminals of the first and second power transistors being mutually coupled to one another; andcircuit means coupled to a predetermined one of the power transistors, the circuit means configured for substantially maintaining a predetermined voltage level across the gate terminal of the predetermined one of the power transistors at least during said switching interval of substantially zero amplitude, said predetermined voltage level being chosen to enable that predetermined power transistor to continue in a respective ""on"" state notwithstanding the presence said switching interval of substantially zero amplitude, said circuit means further configured for removing said predetermined voltage level upon termination of said switching interval of substantially zero amplitude to enable said predetermined power transistor to transition to a respective ""off"" state.