Patent ID: 6495420
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method for manufacturing one single transistor nonvolatile memory on a semiconductor substrate, said method comprising the steps of:forming a sacrificial dielectric layer on said semiconductor substrate; forming a first dielectric layer on said sacrificial dielectric layer; patterning said sacrificial dielectric layer and said first dielectric layer to form an opening therein, thereby exposing a portion of said semiconductor substrate; forming a second dielectric layer on said first dielectric layer and along a surface of said opening; etching said second dielectric layer to form side wall spacers on side walls of said opening, wherein said semiconductor substrate is exposed by said side wall spacers; forming a gate dielectric layer on said exposed semiconductor substrate; forming a first conductive layer on said first dielectric layer and refilling into said opening; removing said first conductive layer to achieve a planar surface; removing said first dielectric layer, said side wall spacers, said sacrificial dielectric layer, thereby forming a floating gate with a sharp corner; forming a tunneling dielectric layer on a surface of said floating gate; and forming a second conductive layer on said tunneling dielectric layer as a control gate.