Patent ID: 6704762
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A multiplier for executing a multiplication operation using a Booth's algorithm, comprising:a Booth decoder which divides a multiplier (Y) into a plurality of partial bit rows and outputs the divided bit rows; a first multiplier replacing circuit which replaces, with â€œ0â€ , a value of only a most significant bit (Y3) included in least significant half of bits of the multiplier (Y) in accordance with a first control signal (SIMD), so as to replace, with 0, a predetermined bit included in the plurality of bit rows; a plurality of partial product generating circuits each of which is arranged in a manner corresponding to each corresponding one of the partial bit rows divided by said Booth decoder, and generates a partial product, represented in bits which are twice as many as a bit number of a multiplicand (X), of the multiplicand (X) and each corresponding partial bit row; a first adder which adds bit rows including the least significant half of bits of the partial products generated by said plurality of partial product generating circuits; a second adder which adds bit rows including most significant half of bits of the partial products generated by said plurality of partial product generating circuits, in consideration of one or more carry signals; and a carry selecting circuit which selects either a bit row composed of â€œ0sâ€  or one or more carry signals which said first adder outputs, in accordance with the first control signal (SIMD), and supplies, to said second adder, the selected data as one or more carry signals, wherein each of said partial product generating circuits, which generates the partial product corresponding to the least significant half the bits included in the partial bit rows divided by said Booth decoder, generates either partial product of full bits of the multiplicand (X) and each corresponding partial bit row or of least significant half of bits of the multiplicand (X) and each corresponding bit row in accordance with a first select signal (SIMD), and each of said partial product generating circuits, which generates the partial product corresponding to the most significant half the bits included in the partial bit rows divided by said Booth decoder, generates either partial product of fill bits of the multiplicand (X) and each corresponding partial bit row or of the most significant half the bits of the multiplicand (X) and each corresponding bit row in accordance with the control signal (SIMD).