Patent ID: 6088761
Filing Date: 2000-07-11
Classification: G06F

Abstract:
An electronic system comprising:an integrated circuit chip including:a processor wherein the processor transmits and receives addresses and data;a memory controller;a bus interface having at least one address pin line, at least one data transfer pin line, and at least one control pin line, wherein the processor and the memory controller are coupled to the bus interface and the bus interface is both a memory interface and a system interface;a synchronous dynamic random access memory (S-DRAM) coupled to the bus interface wherein each of the at least one address pin line and each of the at least one data transfer pin line are shared by the processor and the S-DRAM; anda system interface bridge chip interconnected to the bus interface and to one or more peripheral devices, and including:a protocol module wherein said protocol module manages interactions on the bus interface between the processor, the S-DRAM, and the system interface bridge chip;wherein the memory controller identifies each address transmitted from the processor and determines if the address is a memory address or a peripheral address and when the address is a memory address, the memory controller performs a standard S-DRAM cycle to access the S-DRAM and when the address is a peripheral address, the memory controller notifies the protocol module and the protocol module asserts a BUSY signal onto the at least one control pin line of the bus interface and accepts a transaction as indicated by the peripheral address.