Patent ID: 6131149
Filing Date: 2000-10-10
Classification: G06F,G11C

Abstract:
A data processing system for reading data from a synchronous memory device, said system comprising:a system clock to provide a system clock pulse signal;said synchronous memory device formed as a first integrated circuit and operating in response to said system clock pulse signal;a processor operating in response to said system clock pulse signal, said processor to provide a control signal and a memory address for reading data from said synchronous memory device; anda memory controller formed as a second integrated circuit and coupled to said processor, said memory controller including:an input port for receiving said system clock pulse signal;a control signal logic circuit operating in response to said system clock pulse signal, said control signal logic circuit to forward said control signal received from said processor to said synchronous memory device;an address buffer operating in response to said system clock pulse signal, said address buffer to forward said memory address received from said processor to said synchronous memory device;an output port for providing said system clock pulse signal to said synchronous memory device;a programmable delay module receiving said system clock pulse signal from said output port to generate a skewed clock pulse signal, said skewed clock pulse signal generated by adding a time delay to said system clock pulse signal received from said output port; anda data buffer coupled to said programmable delay module, said data buffer to read data from said synchronous memory device in response to said skewed clock pulse signal, thereby increasing a data valid window in order to ensure valid data is read by said memory controller.