Patent ID: 7368983
Filing Date: 2008-05-06
Classification: H03F

Abstract:
1. An operational amplifier comprising: a first input terminal, a second input terminal, and an output terminal connected to one of the first and second input terminals for outputting output voltage; an operational amplifier circuit including a current mirror, having a first pair of transistors, and a first differential input unit, having a second pair of transistors connected to the current mirror; an offset adjustment circuit including a second differential input unit having a third pair of transistors connected to the current mirror; a first switch for switching between a first connection point, in which a gate of one of the second pair of transistors is connected to a gate of the other one of the second pair of transistors, and a second connection point, in which the gate of the one of the second pair of transistors is connected to the first input terminal; a second switch for switching between a first connection state, in which a gate of a first one of the third pair of transistors is connected to the first input terminal, and a first disconnection state, in which the gate of the first one of the third pair of transistors is disconnected from the first input terminal; a third switch for switching between a second connection state, in which a gate of a second one of the third pair of transistors is connected to the second input terminal, and a second disconnection state, in which the gate of the second one of the third pair of transistors is disconnected from the second input terminal; and an offset voltage holding unit, connected to the gates of the third pair of transistors, for holding an offset voltage derived from output voltage generated by the operational amplifier circuit when the first switch is switched to the first connection point, the second switch is switched to the first connection state, and the third switch is switched to the second connection state, the offset voltage holding unit generating a potential difference between the gates of the third pair of transistors in accordance with the held offset voltage when the first switch is switched to the second connection point, the second switch is switched to the first disconnection state, and the third switch is switched to the second disconnection state.