Patent ID: 7601574
Filing Date: 2009-10-13
Classification: H01L

Abstract:
1. A method for fabricating a stress enhanced MOS transistor comprising the steps of: forming a dummy gate electrode overlying a semiconductor substrate; forming side wall spacers on the dummy gate electrode; forming source and drain regions in the semiconductor substrate; depositing a dielectric buffer layer overlying the gate electrode, side wall spacers, and source and drain regions; forming a dielectric material overlying the dielectric buffer layer; polishing the dielectric buffer layer and the dielectric material to expose and remove a top portion of the dummy gate electrode and to leave a remaining portion of the dummy gate electrode; removing at least a portion of the dummy gate electrode to leave a void; depositing a stressed conductive layer to fill the void; polishing the stressed conductive layer to form a stressed gate electrode; removing the dielectric material; and depositing a stressed liner overlying the stressed gate electrode.