Patent ID: 8122218
Filing Date: 2012-02-21
Classification: G11C

Abstract:
1. A pipelined synchronous dynamic random access memory (SDRAM) comprising: a memory core having addressable memory elements; a read path, defined between an address input port and a data output port; the memory core being included in the read path, the read path including a plurality of pipeline stages, each of the plurality of pipeline stages including a latch responsive to a corresponding asynchronous control signal; and a plurality of delay elements associated with the plurality of pipeline stages, each of the plurality of delay elements being configured to provide the asynchronous control signal, the asynchronous control signal comprising a delayed version of a system clock signal, each of the plurality of delay elements having a latency corresponding to a latency of its associated one of the plurality of pipeline stages, such that each of the plurality of pipeline stages is controlled independently of the system clock signal.