Patent ID: 6037217
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a capacitor electrode structure in a DRAM device, comprising the steps of:preparing a semiconductor substrate formed with a MOSFET having a first source/drain region and a second source/drain region;forming a first insulating layer over the MOSFET;forming a first polysilicon layer over the first insulating layer;forming a plurality of openings in the first polysilicon layer at locations directly above the first and second source/drain regions of the MOSFET;forming a polysilicon-based sidewall structure on the sidewall of each of the openings in the first polysilicon layer;with the polysilicon-based sidewall structure and the first polysilicon layer serving as mask, performing an anisotropic etching process to etch away the exposed portions of the first insulating layer to thereby form a capacitor-node contact window to expose the first source/drain region and a bit-line contact window to expose the second source/drain region;forming a second polysilicon layer over the first polysilicon layer, which fills up the capacitor-node contact windows and the bit-line contact window;forming a metal silicide layer over the second polysilicon layer;forming a second insulating layer over the metal silicide layer;removing selected portions of the second insulating layer, the metal silicide layer, the second polysilicon layer, the first polysilicon layer, and the polysilicon-based sidewall structure other than those portions that lie directly above the second source/drain region, wherein the remaining portions in combination constitute a bit-line structure connected to the second source/drain region;forming a first insulating sidewall structure on the sidewall of each bit-line structure;forming a third insulating layer to cover the bit-line structure, with the third insulating layer being formed with an opening directly above the first source/drain region;forming a third polysilicon layer over the third insulating layer, with the third polysilicon layer being conformal to the third insulating layer and coming into contact with the second polysilicon layer in the capacitor-node contact window;forming a fourth insulating layer over the third polysilicon layer, with the fourth insulating layer being conformal to the third polysilicon layer;forming a fourth polysilicon layer over the fourth insulating layer, with the fourth polysilicon layer being conformal to the fourth insulating layer;forming a second insulating sidewall structure on the fourth polysilicon layer;with the second insulating sidewall structure serving as mask, performing a first selective removal process to remove the exposed part of the fourth polysilicon layer and part of the fourth insulating layer until exposing the third polysilicon layer;forming a fifth polysilicon layer which fills up the opening enclosed by the second insulating sidewall structure and comes into contact with the fourth polysilicon layer and the third polysilicon layer;performing a second selective removal process to remove selected portions of the fifth polysilicon layer, the fourth polysilicon layer, and the third polysilicon layer until exposing the third insulating layer; andperforming a third selective removal process to remove the third insulating layer, the fourth insulating layer, and the second insulating sidewall structure, wherein the fifth polysilicon layer, the fourth polysilicon layer, the third polysilicon layer, and the second polysilicon layer in combination constitute the intended capacitor electrode structure which is connected via the first polysilicon layer to the first source/drain region.