Patent ID: 8026753
Filing Date: 2011-09-27
Classification: H03K

Abstract:
1. A prescaling stage, comprising: a supply voltage terminal and a voltage reference terminal; a bistable latch circuit having respective master and slave portions coupled between the supply voltage terminal and the voltage reference terminal and feedback coupled to each other, each of the master and slave portions including: a differential stage coupled to the supply voltage terminal and including output terminals; a differential pair of cross-coupled transistors coupled to the output terminals of the differential stage; a transistor stage coupling the differential pair of cross-coupled transistors to the voltage reference terminal, the transistor stage having first and second transistors in parallel with each other and coupled to respective transistors in the pair of cross-coupled transistors and between the differential pair and an internal circuit node and having respective control terminals connected to each other; and a degeneration capacitance coupled to respective emitter or source terminals of the transistors of the differential pair and structured to increase a maximum working frequency of the bistable latch circuit.