Patent ID: 7964474
Filing Date: 2011-06-21
Classification: B01L,B41J,B81B,B81C,G01L,G01P

Abstract:
1. A method, comprising: forming a first oxide region and a second oxide region concurrently in a substrate, the first oxide region having a first width and a first depth; forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region; removing substantially all of the first oxide region to form a portion of a chamber, the removing exposing an internal surface of the substrate; forming a first MOS transistor adjacent to the second oxide region; forming a second MOS transistor separated from the first MOS transistor by the second oxide region; and etching the internal surface of the substrate to enlarge the chamber, the chamber having a second width that is greater than the first width and a second depth that is greater than the first depth.