Patent ID: 8024689
Filing Date: 2011-09-20
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit apparatus wherein a first wiring layer is provided with a plurality of first signal wirings having an equal width which are disposed in parallel with each other at a regular interval in a horizontal direction in a view showing a planar structure, at least two of the plurality of first signal wirings, which are adjacent to each other, are electrically connected to each other by at least two second signal wirings, said at least two second signal wirings extending in a vertical direction in a view showing a planar structure, the at least two first signal wirings and the at least two second signal wirings are disposed in the same wiring layer, at least one of a third signal wiring, which is provided in a different wiring layer from the first wiring layer, is electrically connected to at least one of the first signal wirings, said at least one of the third signal wiring extending in a vertical direction in a view showing a planar structure, at least one of a fourth signal wiring, which is provided in a different wiring layer from the first wiring layer, is electrically connected to at least one of the first signal wirings, said at least one of the fourth signal wiring extending in a vertical direction in a view showing a planar structure, and said at least one of the third signal wiring and said at least one of the fourth signal wiring are connected to at least one of the first signal wirings at a different point.