Patent ID: 6528858
Filing Date: 2003-03-04
Classification: H01L

Abstract:
A semiconductor wafer comprising:a layer of semiconductor material; an NMOS device, the NMOS device including: a first source, a first drain and a first body formed from the layer of semiconductor material, the first body disposed between the first source and the first drain; and a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode is disposed on a high-K gate dielectric layer that extends continuously from the first gate electrode to the layer of semiconductor material; and a PMOS device, the PMOS device including: a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain; and a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, the second gate electrode separated from the layer of semiconductor material by a standard-K gate dielectric.