Patent ID: 6904446
Filing Date: 2005-06-07
Classification: G06F

Abstract:
1. A floating point multiplier and accumulator for repetitively performing multiplication and addition operations to create a product of a first operand and a second operand and adding a third operand to the product, comprising: a multiplier array having a first input and a second input for respectively receiving the first operand and the second operand, and providing a sum and a carry; multiplexor circuitry coupled to the multiplier array for selectively bit shifting each of the sum and the carry; shifting circuitry for receiving the third operand and selectively bit shifting the third operand; adder circuitry coupled to the multiplexor circuitry and the shifting circuitry, the adder circuitry adding the sum, the carry and the third operand to provide at an output thereof a mantissa portion of a resultant operand that has not been normalized or rounded; and feedback circuitry coupled to the adder circuitry and the multiplier array, the feedback circuitry coupling the mantissa portion of the resultant operand to either the multiplier array or the shifting circuitry to be subsequently used as one of the first operand, the second operand or the third operand, such feedback being done without first performing normalization or rounding, thereby reducing latency associated with creating the product when one of the first operand, the second operand or the third operand has a value that is dependent upon a previous resultant operand calculated by the floating point multiplier and accumulator.