Patent ID: 7162666
Filing Date: 2007-01-09
Classification: G06F

Abstract:
1. A digital computer comprising: at least one processor and a random access memory, said at least one processor being coupled to the random access memory for access to the random access memory; said at least one processor being programmed with a watchdog thread that is normally executed by said at least one processor during a watchdog grace period, and the digital computer being programmed to shut down and restart when said at least one processor fails to execute the watchdog thread during the watchdog grace period; and said at least one processor being programmed with a periodic interrupt routine that is executed by said at least one processor for checking whether said at least one processor holds any spinlocks, and upon finding that said at least one processor does not hold any spinlocks, for executing the watchdog thread, and upon finding that said at least one processor holds at least one spinlock, for deferring execution of the watchdog thread until said at least one processor releases all of the spinlocks held by said at least one processor.