Patent ID: 6411665
Filing Date: 2002-06-25
Classification: H03L,H04L

Abstract:
A method of sampling a clock signal in a clock recovery circuit at times corresponding to transition events between first and second values of a data signal from which the clock signal is recovered, the method comprising the steps of;inputting the clock signal to a first latch switched by the data signal to be in a transparent state when the data signal has the first value and a hold state when the data signal has the second value; inverting the data signal and inputting the clock signal to a second latch clocked by the inverted data signal to be in a transparent state when the data signal has the second value and a hold state when the data signal has the first value; and multiplexing outputs of the first and second latches to select one of said outputs according to the value of the data signal to obtain a sampled output signal corresponding to the output of whichever one of the first and second latches is in the hold state.