Patent ID: 6617696
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A semiconductor apparatus having a robust and reliable MOSFET gate external connection, comprising:a semiconductor body having a first surface and a second surface; a source contact area on the first surface of the semiconductor body; a drain contact area on the second surface of the semiconductor body; a gate contact area on the first surface of the semiconductor body and separate from the source contact area; a source contact metallization layer overlying the source contact area; a gate contact metallization layer overlying the gate contact area; a source contact passivation layer overlying the source contact metallization layer and having one or more source contact openings each exposing a portion of the surface of the source contact metallization layer; a gate contact passivation layer overlying the gate contact metallization layer and having a first gate contact opening exposing a portion of the surface of the gate contact metallization layer; a first insulating layer overlying the gate contact passivation layer and the source contact passivation layer, having a second gate contact opening exposing the first gate contact opening, and completely overlying one or more source contact areas proximate to the gate contact area; a first conducting metal layer partially overlying the first insulating layer, connected to the gate contact metallization layer via the second gate contact opening; a metal plating layer overlying and in contact with the first conducting metal layer; a gate contact solder bump overlying the metal plating layer; one or more anchoring metal layers overlying the source contact passivation layer, electrically insulated from both the gate contact metallization layer and the source contact metallization layer; and one or more gate support solder bumps each overlying an anchoring metal layer.