Patent ID: 6512697
Filing Date: 2003-01-28
Classification: G11C

Abstract:
A circuit for speed and stability enhancement for a sense amplifier including a transmission transistor with an output coupled to a sense node and an input coupled to a data node connecting a data line to sense a memory state of a memory cell and transmit a data signal from said sense node through an output buffer, said circuit comprising:a first current mirror with a first and a second branches for mirroring a intermediate current on said second branch from said first branch, between said first branch and data node inserted with an offset current apparatus controlled by a first control signal to conduct an offset current; a second current mirror with a third branch for mirroring a leakage current in response to said intermediate current and a forth branch coupled to said sense node; and a charge current apparatus coupled to said sense node and controlled by an inverse signal of a second control signal to conduct a charge current.