Patent ID: 7561652
Filing Date: 2009-07-14
Classification: G06F

Abstract:
1. An electronic data processing device, comprising: a reference clock; a phase detector for receiving an input from said reference clock; a filter for receiving an input from said phase detector; a first adder for receiving an input from said filter; an oscillator for receiving an input from said first adder; a phase locked loop modulator for receiving an input from said oscillator, said modulator having: and an operative clock to provide spread spectrum clock control output from said oscillator to a clocked device, said spread spectrum clock control output having an operative profile that has a deviation of frequency of at least plus or minus 2.5 MHz and a modulation frequency of at least 150 kHz, wherein said spread spectrum clock control output being derived from said reference clock having a frequency of less than a central frequency defining the deviation of frequency.