Patent ID: 6077791
Filing Date: 2000-06-20
Classification: C23C,H01L

Abstract:
A process for forming a semiconductor device comprising the steps of:forming a metal interconnect over a semiconductor device substrate;exposing the semiconductor device substrate to a sintering gas at an elevated temperature within a first reactor, wherein the sintering gas has a first deuterated gas concentration that is at least one volume percent;introducing a first source gas and a second source gas into a second reactor, wherein:the first reactor and the second reactor are a same CVD reactor;the first source gas is a semiconductor source gas having a second deuterated gas concentration that is at least one volume percent;the second source gas includes a gas selected from a group consisting of oxygen, ozone, nitrous oxide, and a nitrogen source gas that includes molecules consisting of nitrogen atoms and other atoms having one proton; andreacting the first source gas and the second source gas within the second reactor to form an insulating layer over the semiconductor device substrate, wherein the insulating layer is at least 1000 angstroms thick.