Patent ID: 7795086
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device using a salicide process, comprising: forming a gate dielectric layer over a silicon substrate, said substrate defining a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region, over the gate dielectric layer, the first and silicon patterns each defining side walls and a top surface; forming a first mask pattern that covers the PMOS region and exposes the NMOS region; doping n-type impurities into the first silicon pattern in the exposed NMOS region and an exposed first portion of the silicon substrate that is adjacent to the first silicon pattern; forming a first metal layer that covers the side walls and the top surface of the first silicon pattern and the exposed first portion of the silicon substrate; forming a doped first gate and a first junction by performing a first heat treatment to silicify the first silicon pattern and the exposed first portion of the silicon substrate; forming a second mask pattern that covers the NMOS region and exposes the PMOS region; doping p-type impurities into the second silicon pattern in the exposed PMOS region and an exposed second portion of the silicon substrate that is adjacent to the second silicon pattern; forming a second metal layer that covers the side walls and the top surface of the second silicon pattern and the exposed second portion of the silicon substrate; and forming a doped second gate and a second junction by performing a second heat treatment to completely silicify the second silicon pattern and the exposed second portion of the silicon substrate.