Patent ID: 9190531
Filing Date: 2015-11-17
Classification: H01L

Abstract:
1. A method of forming a memory cell, the method comprising: etching a trench in a substrate; filling the trench with an oxide to form a shallow trench isolation (STI) region, wherein a portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge; forming a gate structure over the active region of the substrate and over the STI region wherein the gate structure comprises a charge trapping layer; and forming a wordline structure having first and second widths and having portions of the wordline structure of the first width centered above a bit line and portions of the wordline structure of the second width centered above the STI region and formed to extend across the STI region over the bitline-STI edge, wherein the second width is greater than the first width and wherein a lower surface of the portions of the wordline structure of the first width and the lower surface of the portions of the wordline structure of the second width lie in the same plane wherein the top surfaces of the portions of the wordline structure of the second width lie in the same plane and are centered along a same line as is the portions of the wordline structure of the first width.