Patent ID: 7026679
Filing Date: 2006-04-11
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device comprising: a semiconductor substrate, wherein said semiconductor substrate on a main surface thereof, comprises: a memory cell including a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line, a first insulating film formed over the MISFET for selecting said memory cell, a first hole formed in the first insulating film exposing one of a pair of source and drain region of the MISFET and part of a device isolation region, a first plug buried in a second hole and electrically connected to other one of said pair of source and drain region of the MISFET for selecting said memory cell, a second insulating film formed over the first insulating film and the first plug, a trench formed in the second insulating film and over the first plug, and a bit line and a second plug formed in the trench and in the first hole respectively and electrically connected to the one of said pair of source and drain region, wherein said bit line and said second plug are comprised of the same metallic material which is commonly buried in the same manufacturing step in both the trench and the first hole, wherein an upper surface of the bit line and an upper surface of the second insulating film is substantially at a same level, and wherein a width of said bit line is smaller than a minimum size determined by a limit of resolution of photolithography used to form the trench in which said bit line is formed.