Patent ID: 7759808
Filing Date: 2010-07-20
Classification: H01L,Y10S

Abstract:
1. A semiconductor substrate comprising a plurality of semiconductor elements which are arrayed in a matrix form and which are implemented, a dividing line on which the plurality of the implemented semiconductor elements are cut and separated into the individual elements, a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having the plurality of the semiconductor elements implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using the recognition camera, wherein the second recognition mark has a pattern shape which is arranged so that its center line is positioned on a line that extends from the dividing line and which is formed so as to be linearly symmetric with respect to the center line, and the pattern shape is formed so that a ratio of a length occupying a direction parallel to the dividing line is larger than that occupying a direction perpendicular to the dividing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.