Patent ID: 6261907
Filing Date: 2001-07-17
Classification: G11C,H01L

Abstract:
ANG. and 650 .ANG.;4) etching the first polysilicon layer so that a portion of the first polysilicon layer form a floating gate structure, using the oxide cap and the dielectric spacers as hard masks for the etching;5) implanting Boron to a sufficient concentration to shift an erase gate threshold voltage to around 1V;6) stripping a portion of the floating gate oxide on the silicon substrate;7) growing an erase gate oxide with thickness between 50 .ANG. and 250 .ANG.;8) growing a poly tunnel oxide on sidewalls of the floating gate structure during step (7);9) depositing and etching back an erase-gate polysilicon layer to form polysilicon sidewall spacers on said flash EEPROM device, said peripheral PMOS and NMOS transistors, wherein said polysilicon sidewall spacers having a thickness between 0.1 um and 0.3 um;10) forming polysilicon contact pads with a photolithography mask during step (9);11) stripping selected portions of the layer polysilicon sidewall spacers on one side of the flash EEPROM device, using a photolithography mask;12) etching a field oxide along source lines;13) implanting N.sup.+ Arsenic for the peripheral NMOS transistor as well as array cells;14) stripping the polysilicon sidewall spacers of peripheral PMOS and NMOS transistors followed by an N.sup.- implant; and15) implanting P.sup.+ Boron for the peripheral PMOS transistor.