Patent ID: 6653877
Filing Date: 2003-11-25
Classification: G06F,G11C

Abstract:
A semiconductor device comprising:a clock buffer circuit that receives an external clock signal from outside and outputs an internal clock signal; a clock interconnection that transmits an output of said clock buffer circuit; and first and second internal circuits that operate in accordance with said internal clock signal transmitted by said clock interconnection, each of said first and second internal circuits including: an adjusting circuit configured to delay said internal clock signal, and a synchronized circuit that operates in accordance with the output of said adjusting circuit, wherein said adjusting circuit is configured further to output an adjusted clock signal to reduce a time difference between a first propagation time and a second propagation time to less than a time difference between a third propagation time and a fourth propagation time, said first propagation time corresponds to a time period between a time point when said internal clock signal is output from said clock buffer circuit and a time point when said adjusted clock is output from said adjusting circuit of said first internal circuit, said second propagation time corresponds to a time period between a time point when said internal clock signal is output from said clock buffer circuit and a time point when said adjusted clock is output from said adjusting circuit of said second internal circuit, said third propagation time corresponds to a time period between a time point when said internal clock signal is output from said clock buffer circuit and a time point when said adjusting circuit of said first internal circuit receives said internal clock signal, and said fourth propagation time corresponds to a time period between a time point when said internal clock signal is output from said clock buffer circuit and a time point when said adjusting circuit of said second internal circuit receives said internal clock signal.