Patent ID: 6269433
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A computer system, comprising:a processor;a memory device; anda bridge device coupled between said processor and said memory device, wherein said bridge device includes:one or more queue storage elements configured to temporarily store transaction requests to the memory device; anda memory controller configured to execute transaction requests on the memory device, wherein the memory controller includes a least recently used (LRU) logic unit,wherein during the execution of a current transaction request, said memory controller is further configured to:examine pending transaction requests to determine a transaction request to execute next, andactivate an inactive portion of said memory if the next transaction request is directed to said inactive portion of memory, andwherein during the execution of the next transaction request, if the LRU logic unit is full, the memory controller is configured to inactivate a portion of memory to which a previous transaction request was directed.