Patent ID: 8837467
Filing Date: 2014-09-16
Classification: H03M

Abstract:
1. An integrated circuit comprising: high-speed serializer circuitry configured to operate at a data rate at least as fast as the fastest of a plurality of different selectable data rates; bit repeater circuitry configured to receive repeater input words, produce N copies of each bit of the repeater input words in consecutive bit positions of repeater output words, where the consecutive bit positions wrap over multiple repeater output words, and supply the repeater output words to the high-speed serializer circuitry at the operating data rate of the high-speed serializer circuitry, wherein N is an integer greater than 1; high-speed deserializer circuitry configured to operate at the data rate at least as fast as the fastest of the plurality of different selectable data rates; and downsampler circuitry configured to receive downsampler input words from the high-speed deserializer circuitry at the operating data rate of the high-speed deserializer circuitry, produce parallel received signals, where the parallel received signals are selected from a logical concatenation of N downsampler input words, and supply the parallel received signals at a selected one of the plurality of different selectable data rates.