Patent ID: 6248633
Filing Date: 2001-06-19
Classification: G11C,H01L

Abstract:
A method for fabricating a MONOS memory device comprising:forming a gate silicon oxide layer on the surface of a semiconductor substrate;depositing a first polysilicon layer overlying said gate silicon oxide layer;depositing a first nitride layer overlying said first polysilicon layer;patterning said first polysilicon layer and said first nitride layer to form word gates wherein a gap is left between two of said word gates;forming a first insulating layer on the sidewalls of said word gates;depositing a spacer layer overlying said word gates and said gate silicon oxide layer;anisotropically etching away said spacer layer to leave disposable spacers on the sidewalls of said word gates;implanting ions into said semiconductor substrate to form a lightly doped region wherein said disposable spacers act as an implantation mask;thereafter removing said disposable spacers;depositing a nitride-containing layer over said semiconductor substrate in said gap;depositing a second polysilicon layer overlying said word gates and said nitride-containing layer;anisotropically etching away said second polysilicon layer and said nitride-containing layer to leave polysilicon spacers on the sidewalls of said word gates wherein said polysilicon spacers form control sidewall spacer gates and wherein said nitride-containing layer underlying each of said control sidewall spacer gates forms a nitride region in which charge is stored;forming a second insulating layer on said control sidewall spacer gates;implanting ions into said semiconductor substrate to form a bit diffusion region wherein said control sidewall spacer gates act as an implantation mask;coating a gap filling material over the surface of said substrate wherein said gap-filling material fills said gap between said two of said word gates;planarizing said gap-filling material;thereafter removing said first nitride layer overlying said word gates; anddepositing a third polysilicon layer overlying said substrate wherein said third polysilicon layer forms a word line connecting underlying said word gates to complete said fabrication of said MONOS memory device.