Patent ID: 6499098
Filing Date: 2002-12-24
Classification: G06F

Abstract:
A method of operating a digital system, comprising the steps of:executing a sequence of instructions in an instruction pipeline of a processor core, wherein the instructions are fetched in response to a program counter from an instruction memory associated with the processor core; decoding a first memory access instruction from the sequence of instructions, wherein if a qualifier byte is associated with the memory access instruction then the memory access instruction is decoded in a qualified manner; accessing a first data item from a memory mapped register after mapping an address provided by the memory access instruction via a memory management unit if the qualifier byte is not present; or accessing the first data item from the memory mapped register by bypassing the memory management unit without mapping the address provided by the memory access instruction if the qualifier byte is present in a first type; and scheduling a second memory access instruction to be decoded in parallel with the first memory access instruction only when the byte qualifier is present, whereby the memory management unit can be used by the second memory access instruction since it is not used by the first memory access instruction.