Patent ID: 7746254
Filing Date: 2010-06-29
Classification: G11C,H03M

Abstract:
1. A sample and hold circuit for sampling and holding an input voltage, the sample and hold circuit comprising: an operational amplifier configured to convert the held voltage to a differential output voltage, the operational amplifier having inverting and non-inverting input terminals and inverting and non-inverting output terminals; a plurality of inverting-side capacitors, each inverting-side capacitor having a first end coupled to the inverting input terminal of the operational amplifier; a plurality of non-inverting-side capacitors, each non-inverting-side capacitor having a first end coupled to the non-inverting input terminal of the operational amplifier, the plurality of non-inverting-side capacitors being pared with the plurality of inverting-side capacitors to provide a plurality of capacitor pairs, each capacitor pair including one inverting-side capacitor and one non-inverting-side capacitor having a same capacitance; and a control circuit, in a sampling phase of the input voltage, configured to apply the input voltage to at least one of the plurality of inverting-side and non-inverting-side capacitors and apply a predetermined voltage to others of the plurality of inverting-side and non-inverting-side capacitors, the control circuit, in a holding phase of the input voltage, being configured to connect a second end of the inverting-side capacitor of at least one capacitor pair to the non-inverting output terminal of the operational amplifier, connect a second end of the non-inverting-side capacitor of the at least one capacitor pair to the inverting output terminal of the operational amplifier, and apply the input voltage to at least one of the inverting-side and the non-inverting-side capacitors of other capacitor pairs, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as α, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is defined as β, wherein a total capacitance of the inverting-side capacitors to which the input voltage is applied in the holding phase is defined as γ, wherein a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is defined as η, wherein α is substantially different from β, and wherein a total capacitance of the at least one capacitor pair is substantially equal to (α−β−γ+η)·(N/2), where N is a positive number.