Patent ID: 6984578
Filing Date: 2006-01-10
Classification: H01L

Abstract:
1. A method for production of an integrated circuit, comprising: providing at least one first gate stack, at least one second gate stack and at least one third gate stack on a surface of a substrate, wherein each of the first, second and third gate stacks is approximately the same height and includes a gate terminal; providing a common active region in the substrate at the surface of the substrate and between the first and second gate stacks; insulating the gate terminal of each of the first, second and third gate stacks with an encapsulation formed around each of the first, second and third gate stacks; providing a first insulating layer on the substrate for embedding the first, second and third gate stacks; providing a first mask on the first insulation layer, wherein the first insulation layer includes a first opening located above the third gate stack; uncovering the encapsulation formed around the third gate stack at a top side of the third gate stack by etching using the first mask; removing the first mask; selectively etching the uncovered encapsulation at the top side of the third gate stack with respect to the first insulation layer until a top side of the gate terminal of the third gate stack is uncovered; providing a second insulation layer on the substrate including the first insulation layer and the uncovered top side of the gate terminal of the third gate stack for covering the uncovered top side of the gate terminal of the third gate stack; providing a second mask on the substrate including the second insulating layer, wherein the second mask includes a second opening located above the top side of the gate terminal of the third gate stack, a third opening located between the third and second gate stacks and a fourth opening located above the common active region, partially overlapping the first and second gate stacks; and simultaneously forming a first contact hole, a second contact hole and a third contact hole by etching using the second mask, wherein the first and second insulation layers are selectively etched with respect to the encapsulations of the first, second and third gate stacks, the first contact hole uncovering the common active region at the surface of the substrate between the first and second gate stacks, the second contact hole uncovering the surface of the substrate between the second and third gate stacks and the third contact hole uncovering the top side of the gate terminal of the third gate stack.