Patent ID: 6256184
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A circuit on an IC chip having an I/O pad and I/O circuitry directly coupled to the I/O pad for transmitting and receiving signals over the I/O pad, the circuit comprising:a low threshold voltage FET coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad;the FET also coupled to a first voltage terminal for providing a shunting path for the ESD event, thereby effectuating said protecting the IC chip from the ESD event on the I/O pad; anda negative bias generator coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET thereby maintaining the FET in an off state during normal operation of the IC chip.