Patent ID: 6138188
Filing Date: 2000-10-24
Classification: G06F

Abstract:
A buffer management device for buffering data transmitted from a first component to a second component in a data processing system, the device comprising:a plurality of memory blocks, coupled between the first component and the second component, for temporarily storing the data transmitted from the first component to the second component, each of the memory blocks having a plurality of memory segments, and each of the memory segments having a plurality of memory units;a plurality of first tag memories, corresponding to the plurality of memory blocks, respectively, for storing addressing information pertaining to the memory units of the corresponding memory blocks in a first mode in which each of the memory blocks serves as a data storage unit;a plurality of second tag memories, corresponding to the plurality of memory blocks, respectively, for storing addressing information pertaining to the memory units of the corresponding memory blocks in a second mode in which each of the memory segments serves as the data storage unit; anda mode-switching circuit, coupled to the memory blocks, the first tag memories and the second tag memories, for activating each of the memory blocks to be operated in the first mode or in the second mode according to the addressing information pertaining to the data inputted from the first component.