Patent ID: 6628537
Filing Date: 2003-09-30
Classification: G06F,G06K,G11C,H01L,H05K

Abstract:
A system comprising:a host system, comprising: a computer system including a microprocessor; and a host system connector to receive a memory card and connectable to (1) receiving address, user data and command signals from said host system according to a given protocol and (2) providing user data and status signals to said host system according to said given protocol; a plurality of said memory cards which individually include a card connector that mechanically mates with the host system connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters; a memory controller including at least one controller microprocessor that executes commands from the host system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the host system connector, said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said host system and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said host system connector; and a communication circuit including a serial portion extending through the host system and memory card connectors to transfer user data between the host system and said at least one accessed memory cell group.