Patent ID: 6785874
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A layout verification method using a layout data of a semiconductor integrated circuit,said layout data containing plural polygons indicating wiring patterns, said polygons being made up of plural segments that are sides, said method comprising the steps of: (a) dividing plural segments forming one of said plural polygons in said layout data, based on a predetermined rule defined beforehand relative to the layout of other surrounding polygon; (b) with respect to said segments divided and segments not divided, detecting a width of wiring containing each of said segments and a width of space most adjacent to each of said segments; (c) evaluating the possibility of resolution of each of said segments by referring to data of conditions under which resolution can be performed, in which a predetermined conditione relative to the possibility of resolution of said segments in a wafer process is stored in association with a combination of said width of wiring and said width of space; and (d) outputting an error information when there is a segment of which possibility of resolution is negative based on the result of evaluation in said step (c).