Patent ID: 6069496
Filing Date: 2000-05-30
Classification: H03K

Abstract:
A high-speed dynamic complementary CMOS inverter for a dynamic logic circuit, said dynamic logic circuit evaluating during an evaluate phase of an arming signal and pre-charging during a pre-charge phase of said arming signal, comprising:a complementary CMOS inverter having an inverter trigger point tuned to a falling edge of an input signal received at an input node which produces an output signal at an output node, said output signal comprising an inverted version of said input signal and said CMOS inverter comprising:a PMOSFET having a source coupled to a power source, a gate coupled to the input node, and a drain coupled to the output node; andan NMOSFET having a source coupled to the output node, a gate coupled to the input node, and a drain coupled to a circuit ground;wherein the ratio of said PMOSFET to said NMOSFET is at least 12 to 1; anda pre-charge assist FET having a drain coupled to the output node and a gate coupled to an arming signal, said pre-charge assist FET operating to assist in pulling said output signal low when said input signal falls past said inverter trigger point and said arming signal enters said pre-charge phase.