Patent ID: 9001569
Filing Date: 2015-04-07
Classification: G11C

Abstract:
1. A memory circuit, comprising: a memory cell array including a plurality of memory cells arranged in a plurality of row groups and a plurality of column groups, where each row group of memory cells is connected to an associated wordline of a plurality of parallel wordlines, and each column group of memory cells is connected to at least one associated bitline of a plurality of parallel bitlines; a row-address post decoder including means for asserting a single wordline control signal in accordance with an associated row address value generated during a read/write operation; a plurality of wordline drivers connected between the row-address post decoder and the plurality of parallel wordlines such that each said wordline driver generates a high voltage signal on an associated one of the plurality of wordlines in response to an associated said asserted wordline control signal; means for disabling at least some of the plurality of wordline drivers, said means comprising one or more switch elements connected between a system power source and a power terminal of each of said plurality of wordline drivers, and control means for controlling said one or more switch elements to de-couple one or more of the wordline drivers from the system power source, and at least one source bias circuit including means for providing a first voltage to a source terminal of each of the plurality of memory cells in said each accessed column group during a first time period while said associated column address signal value is asserted during the read/write operation, and for providing a second voltage to the source terminal of each of the plurality of memory cells in at least one other adjacent non-accessed column group during the first time period, wherein the first voltage is lower than said second voltage.