Patent ID: 8492264
Filing Date: 2013-07-23
Classification: H01L

Abstract:
1. A method for forming a stack of interconnection levels of an integrated circuit, the method comprising: (a) forming an interconnection level comprising conductive tracks formed above conductive vias, the conductive tracks and the conductive vias being laterally separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer of the non-porous insulating material comprising at least one opening exposing at least one portion of the porous dielectric material; (c) repeating steps (a) and (b) to obtain an adequate number of interconnection levels of the stack, the conductive vias of a first interconnection level of the stack having another interconnection level below contacting the conductive tracks of the interconnection level below; and (d) annealing the stack of interconnection levels of the integrated circuit.