Patent ID: 6839268
Filing Date: 2005-01-04
Classification: G06F,G11C

Abstract:
1. A semiconductor circuit comprising: a first memory block having a plurality of first pairs of bit lines, a plurality of first word lines, and a plurality of first SRAM memory cells coupled to said plurality of first pairs of bit lines and first word lines; a second memory block having a plurality of second pairs of bit lines, a plurality of second word lines, and a plurality of second SRAM memory cells coupled to said plurality of second pairs of bit lines and said second word lines; a sense amplifier and a write amplifier; a first pair of wiring lines coupled to said sense amplifier; a second pair of wiring lines coupled to said write amplifier; a first switch circuit which electrically connects one pair of said plurality of said first and second pairs of bit lines to said first pair of wiring lines; and a second switch circuit which electrically connects one pair of said plurality of said first and second pairs of bit lines to said second pair of wiring lines, wherein said first pair of wiring lines lies over said first and second memory block, and extends in a first direction of which said plurality of first pairs of bit lines and second pairs of bit lines extend, wherein said second pair of wiring lines lies over said first and second memory block, and extends in said first direction, wherein said first pair and second pairs of wiring lines are formed in a first metal layer, wherein said plurality of first pairs of bit lines and second pairs of bit lines are formed in a second metal layer, wherein read operations of said first and second SRAM memory cells are performed by using said first pair of wiring lines, and wherein write operations of said first and second SRAM memory cells are performed by using said second pair of wiring lines.