Patent ID: 7463536
Filing Date: 2008-12-09
Classification: G11C

Abstract:
1. An integrated circuit comprising: a memory array including a first plurality of array blocks, each array block comprising a plurality of word lines and bit lines; a first data bus generally spanning the first plurality of array blocks, each of a first group of the first plurality of array blocks associated with the first data bus; a second data bus generally spanning the first plurality of array blocks, each of a second group of the first plurality of array blocks associated with the second data bus; a row selection circuit configured, in a first mode of operation, to simultaneously select a word line in a first array block within the first group and a word line in a second array block within the second group; and a column selection circuit configured, in the first mode of operation, to simultaneously couple one or more selected bit lines in the first array block to corresponding lines of the first data bus and one or more selected bit lines in the second array block to corresponding lines of the second data bus.