Patent ID: 6423588
Filing Date: 2002-07-23
Classification: H01L,Y10S

Abstract:
A method of manufacture of a semiconductor integrated circuit device, comprising:forming a first well region, a second well region and a third well region which are of a n-type conductivity, respectively; forming a fourth well region and a fifth well region which are of a p-type conductivity, respectively; forming a first insulating film having a first thickness on a surface of said first well region, on a surface of said second well region, and on a surface of said fourth well region; forming a second insulating film having a second thickness, less than that of said first insulating film, on a surface of said third well region and on a surface of said fifth well region; forming a first conductive film including a semiconductor layer on said first insulating film and said second insulating film; selectively introducing an impurity in portions of said semiconductor layer over said first well region, said fourth well region, and said fifth well region to form portions thereof having said n-type conductivity; selectively introducing an impurity in portions of said semiconductor layer over said second well region and said third well region to form portions thereof having said p-type conductivity; forming, by patterning said first conductive film, a first electrode of a capacitive element on said first insulating film formed over said first well region, a gate electrode of a first p-channel MISFET on said first insulating film formed over said second well region, a gate electrode of a second p-channel MISFET on said second insulating film formed over said third well region, a gate electrode of a first n-channel MISFET on said first insulating film formed over said fourth well region, and a gate electrode of a second n-channel MISFET on said second insulating film formed over said fifth well region, wherein said first well region serves as a second electrode of said capacitive element; and forming source and drain regions of said first p-channel MISFET having said p-type conductivity in said second well region, forming source and drain regions of said second p-channel MISFET having said p-type conductivity in said third well region, forming source and drain regions of said first n-channel MISFET having said n-type conductivity in said fourth well region, and forming source and drain regions of said second n-channel MISFET having said n-type conductivity in said fifth well region.