Patent ID: 6383904
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:A. forming a first layer of dielectric material on said semiconductor substrate; B. etching a seeding window through said first layer of dielectric material to expose said semiconductor substrate through said seeding window; C. depositing a layer of amorphous semiconductor material on said first layer of dielectric material, wherein said amorphous semiconductor material fills said seeding window to contact said semiconductor substrate through said seeding window; D. depositing a second layer of dielectric material on said layer of amorphous semiconductor material; E. etching a front gate opening through said second layer of dielectric material to expose said layer of amorphous semiconductor material through said front gate opening, wherein said front gate opening is disposed substantially away from said seeding window such that said front gate opening does not overlap said seeding window; F. implanting an amorphization dopant into said semiconductor substrate through said front gate opening to form a back gate region of amorphous semiconductor material in said semiconductor substrate, wherein the area of said back gate region is formed to be aligned with said front gate opening under said front gate opening; G. implanting a back gate dopant into said back gate region of amorphous semiconductor material through said front gate opening; H. forming a gate dielectric at a bottom of said front gate opening to contact said layer of amorphous semiconductor material; and I. filling a remaining portion of said front gate opening with a gate electrode material.