Patent ID: 6243666
Filing Date: 2001-06-05
Classification: G06F

Abstract:
For use in a digital logic device comprised of state devices clocked by a clock signal, the digital logic device being further comprised of combinational logic and interconnecting nets, wherein ones of the interconnecting nets are designated as condition indicators, each of the condition indicators indicative of a predetermined condition within said digital logic device, the digital logic device having interfaces, each of the interfaces to receive signals from, and provide signals to, an external logic device coupled to a respective one of the interfaces, a logic maintenance system, comprising:a bi-directional port to receive an external condition signal from the external logic device, wherein said external condition signal is indicative of one or more predetermined conditions within the external logic device;an internal condition detection circuit coupled to receive each of the condition indicators, said internal condition detection circuit to provide an internal condition indicator in response to the assertion of any of the condition indicators, said internal condition detection circuit further coupled to provide said internal condition indicator to said bi-directional port, and whereby said internal condition indicator may be provided to the external logic device;an external condition detection circuit coupled to said bi-directional port to detect the assertion of said external condition signal and in response thereto, to generate an external condition indicator; anda control unit coupled to receive said internal condition indicator and to receive said external condition indicator, said control unit to generate an action signal in response to receiving either said external condition indicator or said internal condition indicator, said action signal being provided to predetermined ones of the state devices to perform a selected control function.