Patent ID: 6222384
Filing Date: 2001-04-24
Classification: G11C,H03K

Abstract:
A level shifter circuit, comprising:an inverter for inverting an input signal;a first transistor having a gate to receive an input signal inverted by the inverter, a source coupled to a ground voltage, and a drain coupled to a first node;a second transistor having a gate to receive a first input signal, a source coupled to a ground voltage, and a drain coupled to a second node;a third transistor having a gate to receive an externally applied voltage, a source coupled to the second node, and a drain coupled to a third node;a fourth transistor having a gate coupled to the third node, and a drain coupled to a fourth node, wherein a source and a substrate receives a raised voltage;a fifth transistor having a gate coupled to the fourth node, and a drain coupled to the third node, wherein a source and a substrate receives the raised voltage;a sixth transistor having a gate coupled to the fourth node, and a drain coupled to a fifth node wherein a source and a substrate receive the raised voltage;a seventh transistor having a gate coupled to the fourth node, a drain coupled to the fifth node, and a source for receiving a second input signal;an eighth transistor having a gate coupled to the third node, a source coupled to the fifth node, and a drain coupled to receive the second input signal; anda ninth transistor having a gate to receive an externally applied voltage, a source coupled to the first node, and a drain coupled to a fourth node.