Patent ID: 6472758
Filing Date: 2002-10-29
Classification: H01L,Y10T

Abstract:
A semiconductor package with stacked dies, the package comprising:first and second semiconductor dies, each die having opposite top and bottom surfaces, a length and a width respectively equal to the corresponding length and width of the other die, and a plurality of wire bonding pads around the periphery of the top surface thereof; a plurality of conductive wires electrically connected to the wire bonding pads on the first die; a first layer of a hardened adhesive attaching the bottom surface of the second die to the top surface of the first die and encapsulating the wire bonding pads of the first die and the conductive wires connected thereto such that the bottom surface of the second die is superposed above the conductive wires connected to the first die without contacting the wires, and such that each portion of the second die located below a respective one of the wire bonding pads on the top surface of the second die is supported from below by the first layer of hardened adhesive; and, a monolithic body of an encapsulant over the first and second dies and the conductive wires.