Patent ID: 6714039
Filing Date: 2004-03-30
Classification: G06F

Abstract:
A transmission line of an integrated circuit, comprising:a driven end; a receiving end; one or more repeaters along said transmission line, at least one of said one or more repeaters comprising: a first PFET source coupled to a high voltage source, gate coupled to a repeater input, and drain coupled to a repeater output; and a first NFET source coupled to a low voltage source, gate coupled to said repeater input, and drain coupled to said repeater output; and one or more termination circuits corresponding to said one or more repeaters, each connected in close proximity to said repeater input of its respective corresponding repeater, at least one of said plurality of termination circuits comprising: a second PFET source coupled to a high voltage source, gate coupled to said repeater input, and drain coupled to said repeater input; and a second NFET source coupled to a low voltage source, gate coupled to said repeater input, and drain coupled to said repeater input; wherein first NFET and said second NFET are ratioed to vary similarly under process, voltage, and temperature (PVT) variation, and said first PFET and said second PFET are ratioed to vary similarly under process, voltage, and temperature (PVT) variation.