Patent ID: 7956401
Filing Date: 2011-06-07
Classification: C23C,H01L

Abstract:
1. A method of forming a transistor on a semiconductor substrate, the method comprising: forming a channel region between a source region and a drain region of a semiconductor substrate; forming a high-K dielectric gate dielectric layer on the channel region, the layer comprising a high-K dielectric film having a first crystal lattice structure defining a first grain and a second crystal lattice structure defining a second grain, the lattice structures defining an associated grain boundary at the intersection of the first and second grains and wherein at least two axes of the first grain are substantially aligned with corresponding axes of the second grain at the associated grain boundary; forming a remaining portion of a gate stack on the high-K dielectric gate dielectric layer in the channel region between the source region and the drain region; and forming a gate electrode coupled to the gate stack.