Patent ID: 6346839
Filing Date: 2002-02-12
Classification: G11C,H03L,Y10S

Abstract:
A delay locked loop circuit comprising:a phase detector coupled to receive first and second clocking signals and to produce a go-faster signal and a go-slower signal indicative of a phase relationship between said first and second clocking signals, wherein said phase detector includes a delay operable to delay said first clocking signal such that initially after power up or resetting the delay locked loop circuit, said phase detector determines said second clocking signal is received prior to said first clocking signal; a latch circuit coupled to receive said go-faster and go-slower signals and to produce a latched go-fast signal or a latched go-slow signal in response thereto, whereby after power up or resetting the delay locked loop circuit said latch circuit first produces said latched go-slow signal; and a voltage controlled delay line coupled to receive said latched go-fast and go-slow signals, said voltage controlled delay line producing said second clocking signal for input to said phase detector based on said received signals.