Patent ID: 6373414
Filing Date: 2002-04-16
Classification: H03M

Abstract:
A serial/parallel converter for converting N bits (N is a plural) of serial data, which are supplied in synchronization with a clock from a timing of a flag signal, into parallel data comprises:a pulse generator for repeatedly generating first to Nth timing pulses serially in synchronization with a clock; a flag signal latch circuit for latching said flag signal in response to a (2Iâˆ’1)th (I are all integers of 1&lE;I&lE;N/2) timing pulse and for outputting first to (N/2)th strobe signals corresponding to said flag signal in response to a (2Iâˆ’2)th (or Nth if I=1) timing pulse; a first-stage latch circuit for latching first to Nth serial data in response to said first to Nth timing pulses; N/2 groups of second-stage latch circuits for respectively latching, in response to a (2Iâˆ’2)th timing pulse, (2Iâˆ’1)th to (2Iâˆ’3)th ((Nâˆ’1)th if I=1) serial data latched by said first-stage latch circuit; and N/2 groups of final-stage gate circuits for respectively outputting in parallel, in response to said first to said (N/2)th strobe signals, (Nâˆ’1) bits of serial data latched by said second-stage latch circuits as well as Nth serial data latched by said first latch circuit.