Patent ID: 6166974
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A redundant circuit of a semiconductor memory device, comprising:a PMOS transistor, including a source coupled to a voltage supply with a voltage VCC, a gate to receive a precharge signal, and a drain;a fuse, including a terminal connected to ground, another terminal coupled to the drain of the PMOS transistor, and the fuse being coupled to a column address signal;a first inverter, including an input terminal coupled to the drain of the PMOS transistor and an output terminal;a switch, including an input terminal coupled to the output of the first inverter, and the switch being turned on/off according to a potential level of the precharge signal; anda second inverter, including an input terminal coupled to the output terminal of the switch and an output terminal to output a bit-switch control signal.