Patent ID: 8704529
Filing Date: 2014-04-22
Classification: G01R

Abstract:
1. A circuit test interface, comprising: a test voltage input pad; a test voltage output pad; a plurality of input buffers, each of the plurality of input buffers having a first input terminal, a second input terminal, and an output terminal, and wherein the first input terminal of each respective input buffer is coupled to one of a plurality of through-silicon vias (TSVs); a plurality of switch units, each of the plurality of switch units having a first terminal and a second terminal, wherein the first terminal of each of the switch units is coupled to the first input terminal of one of the plurality of input buffers and the corresponding TSV, and the second terminal of each of the switch units is coupled to the test voltage input pad; and a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.