Patent ID: 6737685
Filing Date: 2004-05-18
Classification: G11C,H01L,Y10S

Abstract:
A compact static random access memory (SRAM) cell layout for implementing one-port or two-port operation comprising:a plurality of field effect transistors (FETs); said plurality of FETs defining a storage cell and a pair of wordline FETs coupled to said storage cell; each of said plurality of FETs having a device structure extending in a single direction; said device structure of each of said plurality of FETs including a diffusion layer, a polysilicon layer and first metal layer; a local interconnect connecting said diffusion layer, said polysilicon layer and said first metal layer; said local interconnect including a metal local interconnect disposed on said diffusion and polysilicon layers for electrically connecting said diffusion and polysilicon layers and a metal contact extending between said metal local interconnect and said first level metal for electrically connecting said diffusion and polysilicon layers and said first level metal; and each of said pair of wordline FETs having a gate input connected to a wordline; said wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation.