Patent ID: 6964895
Filing Date: 2005-11-15
Classification: H01L

Abstract:
1. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, method comprising: forming a shallow trench isolation (STI) region in a semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate, and wherein the STI region extends a first depth below an upper surface of the semiconductor substrate; forming a buried source region having a first conductivity type below the upper surface of the semiconductor substrate, the buried source region having a top interface located below the upper surface of the semiconductor substrate and above the first depth, and a bottom interface located below the first depth; and etching a recessed region in the STI region adjacent to the semiconductor island region, wherein the recessed region extends a second depth below the upper surface of the substrate, the second depth being less than the first depth, and the top interface of the source region being located above the second depth.