Patent ID: 7587582
Filing Date: 2009-09-08
Classification: G06F

Abstract:
1. A method of executing a single instruction parallel multiply-add function on a processor, the method comprising: providing the processor with an opcode indicating a parallel multiply-add instruction having at least three source operands wherein each source operand includes at least two operand components; providing the processor with a first, a second and a third value of a first source operand, a second source operand and a third source operand, respectively in said at least three source operands, wherein each of the values comprises two or more of said at least two operand components and further wherein the first, second and third values are stored in respective source registers of the processor specified by the parallel multiply-add instruction; multiplying first operand components of the first and the second values to generate a first intermediate value; multiplying second operand components of the first and the second values to generate a second intermediate value; adding a first operand component of the third value to the first intermediate value to generate a first result value; adding a second operand component of the third value to the second intermediate value to generate a second result value; storing the first result value in a first portion of a result location; and storing the second result value in a second portion of the result location wherein the result location is a destination register of the processor specified by the parallel multiply-add instruction wherein said processor also supports at least one instruction in a set of instructions consisting of a parallel averaging instruction, a parallel shift instruction, a parallel power instruction, and a parallel reciprocal square root instruction.