Patent ID: 6538946
Filing Date: 2003-03-25
Classification: G11C,H01L

Abstract:
A semiconductor integrated circuit device having first and second memory cell formation regions at both ends of a sense amplifier formation region,wherein said sense amplifier formation region comprises: a sense amplifier circuit region; a first column selecting circuit region formed between said sense amplifier circuit region and first memory cell formation region; a second column selecting circuit region formed between said sense amplifier circuit region and second memory cell formation region; a first pre-charge circuit region formed between said sense amplifier circuit region and first memory cell formation region; and a second pre-charge circuit region formed between said sense amplifier circuit region and second memory cell formation region, wherein first and second bit lines are respectively formed on said first and second memory cell formation regions so as to extend to said sense amplifier formation region, wherein said first bit line extending from said first memory cell formation region extends to said sense amplifier circuit region via said the first pre-charge circuit region and said first column selecting circuit region, and wherein said second bit line extending from said second memory cell formation region extends to said first pre-charge circuit region via said second pre-charge circuit region, said second column selecting circuit region, said sense amplifier circuit region, and said first column selecting circuit region, and wherein a unit sense circuit is formed in said sense amplifier circuit region, said unit sense circuit amplifying the potential difference between said first bit line and said second bit line.