Patent ID: 8319530
Filing Date: 2012-11-27
Classification: H03F,H03K

Abstract:
1. A buffer circuit, comprising: a biasing circuit operable to generate first and second biasing signals; a capacitive network including an input adapted to receive an input signal and the capacitive network operable responsive to the input signal to generate first and second bootstrapped signals; and a push-pull stage including first and second control inputs and an output, the push-pull stage being coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively, the push-pull stage operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals; wherein the biasing circuit comprises elements sized to bias the push-pull stage between a turn-on threshold and a fully on state.