Patent ID: 6453405
Filing Date: 2002-09-17
Classification: G06F

Abstract:
A digital system, comprising;a microprocessor having at least a first load/store unit and a second load/store unit; a memory subsystem having at least first memory with a first memory port connected to the first load/store unit and a second memory with a second memory port connected to the second load/store unit; address generation circuitry in the first load/store unit having a first address output connected to the first memory port and a second address output selectively connected to the second memory port, the address generation circuitry operable to provide a first address on the first address output and a second address on the second address output, such that the first address is associated with an end of a circular buffer region in the memory subsystem and the second address is associated with an opposite end of the circular buffer region; and a extraction circuit connected to the first memory and to the second memory, wherein the extraction circuit is operable to provide an non-aligned data item to the first load/store unit extracted from a first aligned data item from the first memory responsive to the first address and from a second aligned data item from the second memory responsive to the second address, whereby a non-aligned access near the end of the circular buffer region provides a non-aligned data item that wraps around to the other end of the circular buffer.