Patent ID: 7185254
Filing Date: 2007-02-27
Classification: G01R,G06F

Abstract:
1. An apparatus for generating test pattern sequence which is applicable to a semiconductor integrated circuit to detect a fault, comprising a fault list memory for storing a fault list in which delay faults that may occur in a semiconductor integrated circuit under test are registered; a test pattern sequence generator for generating a test pattern sequence which comprises a plurality of test patterns and which sequence is usable for a transient power supply current testing to detect a selected delay fault in the semiconductor integrated circuit under test that is selected from the fault list, wherein the test pattern sequence is applied to the semiconductor integrated circuit to activate a location in the semiconductor integrated circuit that corresponds to where the selected delay fault occurs so that a transition signal is obtained at the location, and to cause a following logic gate whose input is connected to the location to propagate the transition signal to an output thereof; a test pattern sequence list memory for storing the test pattern sequence; and a control unit for controlling the fault list memory to select the selected delay fault from the fault list, for controlling the test pattern sequence generator to generate the test pattern sequence for the selected delay fault, and for controlling the pattern sequence list memory to store the test pattern sequence.