Patent ID: 6528819
Filing Date: 2003-03-04
Classification: H01L

Abstract:
An array substrate comprising:a plurality of gate lines on a substrate, each gate line having a gate electrode, a gate pad, and a gate line extension; a first insulation layer over said plurality of gate lines, over said gate electrodes, over said gate line extensions, and over said substrate; a plurality of gate line contact holes, each gate line contact hole passing through said first insulation layer to said gate line extension; a plurality of thin film transistors on said first insulation layer, each thin film transistor located over a gate electrode and having a source electrode, a drain electrode, and a semiconductor layer; a plurality of data lines on said first insulation layer, each data line electrically connecting to a plurality of source electrodes, wherein said plurality of data lines cross said plurality of gate lines to define a plurality of pixel regions; a ground line under each pixel region, said ground line being on said first insulation layer; a first capacitor electrode over said ground line and over a portion of said first insulation layer, said first capacitor electrode electrically connecting to said ground line, wherein said first capacitor electrode is comprised of a transparent conductive material; an electrode pattern over said gate lines extensions and contacting a plurality of said gate line extensions via said gate line contact holes; and an etch stopper on said first insulation layer and over said gate pads.