Patent ID: 7061408
Filing Date: 2006-06-13
Classification: G11C

Abstract:
1. An encoder for encoding a data word having a plurality of bits, wherein the data word is transmittable in parallel on a data bus, wherein for each bit a bus line is provided and wherein each bit may have one of two states, comprising: a means for examining the data word in order to determine whether a first number of bits of the data word with a first logical state or a second number of bits of the data word with a second logical state exceeds a predetermined threshold, the predetermined threshold being a value that is higher than 50% of the total number of bits of the data word; a means for changing the state of at least one bit of the data word from the number of bits exceeding the predetermined threshold in order to create an encoded data word if the predetermined threshold is exceeded by the data word, so that the first number of bits and the second number of bits of the encoded data word are below the predetermined threshold; and a means for creating auxiliary information referring to the at least one changed bit; wherein the means for changing has a number of programmable inverters, the number of the programmable inverters being at most 50% of the number of the bit lines.