Patent ID: 9219088
Filing Date: 2015-12-22
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a pixel region, a data-line pad region and a gate-line pad region; wherein the pixel region comprises: a pixel electrode, a gate electrode of a thin-film transistor (TFT), source and drain electrodes of the TFT, a connection electrode electrically connecting the pixel electrode with the drain electrode of the TFT, and a common electrode; the pixel electrode is provided on an upper surface of the substrate; the connection electrode is provided on an upper surface of the pixel electrode; the gate electrode of the TFT and the connection electrode are of a same layer and a same material; a semiconductor layer is formed between the source, drain electrodes and the gate electrode; an insulating layer is formed between the semiconductor layer and the gate electrode; the pixel electrode is electrically connected with the drain electrode of the TFT via the connection electrode; the common electrode comprises a portion that is of a same layer and a same material as the source, drain electrodes, moreover, the semiconductor layer and the insulating layer are sequentially formed between said portion that is of a same layer and a same material as the source, drain electrodes and the pixel electrode, wherein the portion where the common electrode overlaps with the pixel electrode constitutes a storage capacitor of the TFT; the data-line pad region comprises a data line and a data-line connection pad; the data line and the source and drain electrodes are of a same layer and a same material; and the gate-line pad region comprises a gate line and a gate-line connection pad; the gate line and the gate electrode are of a same layer and a same material; and the gate-line connection pad and the source and drain electrodes are of a same layer and a same material.