Patent ID: 6115319
Filing Date: 2000-09-05
Classification: G11C

Abstract:
A dynamic RAM comprising:a pair of complementary bit lines;a word line;a dynamic memory cell disposed at the intersection of one of said paired complementary bit lines and said word line;a first circuit which supplies said word line with a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage;a sense amplifier which receives a potential difference between a signal voltage read out from said dynamic memory cell to said one bit line and a precharge voltage of the other bit line, amplifies said potential difference, and thereby generates a high level corresponding to a third voltage and a low level corresponding to a fourth voltage;an output terminal which outputs a read signal based on said high and low levels generated by said sense amplifier;a second circuit which boosts the potential of a selected word line from said first voltage to a fifth voltage; anda third circuit which is controlled by a command designated by a control signal inputted in synchronism with a clock signal, which outputs said read signal in synchronism with said clock signal,wherein said second circuit acts, in synchronism with said clock signal, to boost the select level of said word line intermittently from said first voltage to said fifth voltage.