Patent ID: 7800431
Filing Date: 2010-09-21
Classification: G05F,G11C

Abstract:
1. An internal voltage generation circuit of a semiconductor device, comprising: a first logic circuit configured to receive a power down mode signal and a precharge flag signal, and generate a first output signal, the power down mode signal being enabled in a power down mode, the precharge flag signal being enabled in a precharge mode and disabled in an active mode, and the first output signal being enabled when the power down mode signal and the precharge flag signal are enabled; a second logic circuit configured to receive the first output signal and a clock enable signal, and generate a second output signal, the clock enable signal being disabled in the power down mode causing an internal clock of the semiconductor device to stop, to reduce power consumption, and the second output signal being enabled when the first output signal is enabled and the clock enable signal is disabled; a latch circuit configured to receive the second output signal and an inverted signal of the clock enable signal, and generate a level control signal, the level control signal being enabled when the second output signal is enabled, and being disabled when the clock enable signal is enabled; and an internal voltage generator for generating an internal voltage in response to the level control signal and outputting said internal voltage to an output node.