Patent ID: 8295365
Filing Date: 2012-10-23
Classification: H04L,H04N

Abstract:
1. A wireless receiver comprising: a bitstream analysis circuit which receives a bitstream signal including audio/video data and time data, receives a reference clock signal, detects and outputs the audio/video data and the time data in the bitstream by analyzing the bitstream signal, and outputs reference clock control data on the basis of the time data; a first digital phase-locked loop circuit which receives a system clock signal and the reference clock control data, and generates the reference clock signal to supply it to the bitstream analysis circuit; a reference time generation circuit connected to the first digital phase-locked loop circuit, the reference time generation circuit receives the reference clock signal to count it and generates a reference time signal synchronized with the reference clock signal at every specified time; a second digital phase-locked loop circuit which receives the system clock signal and the reference time signal and generates an audio master clock signal to be used at the time of audio signal reproduction in synchronization with the reference time signal; a third digital phase-locked loop circuit which receives at least the system clock signal and generates a video master clock signal to be used at the time of video signal reproduction; and an audio/video decoder which receives the audio/video data, the audio master clock signal and the video master clock signal and decodes the audio/video data in synchronization with the audio master clock signal and the video master clock signal to output an audio signal and a video signal, wherein the second digital phase-locked loop circuit includes: a first frequency dividing circuit which receives the system clock signal and divides frequency of the system clock signal by m (m is an arbitrary positive integer); a second frequency dividing circuit which receives the system clock signal and divides frequency of the system clock signal by (m+1); a first register connected to the first and the second frequency dividing circuits to set frequency dividing ratios of the first and the second frequency dividing circuits; a second register which sets a mixing ratio between output clock signals from the first and the second frequency dividing circuits; a first mixing circuit connected to the first and the second frequency dividing circuits and the second register, the first mixing circuit mixes the output clock signals from the first and the second frequency dividing circuits at a mixing ratio in response to the data in the second register, and outputs a mixed output clock signal; a first counter which receives and counts the output clock signal from the first mixing circuit; a third register which stores control data to specify a target frequency; and a first control circuit connected to the second register, the first counter and the third register, the first control circuit receives the reference time signal, compares a count value of the first counter for the reference time signal within a specified interval with the data in the third register, detects whether or not the output clock signal from the first mixing circuit has become an accurate frequency and updates the data in the second register in response to a detection result.