Patent ID: 8677060
Filing Date: 2014-03-18
Classification: G06F,G11C

Abstract:
1. A memory system comprising: a register coupled to a host system and operable to receive address and control signals from the host system; a volatile memory subsystem; a non-volatile memory subsystem; a controller coupled to the non-volatile memory subsystem; and a circuit coupled to the register, the volatile memory subsystem, and the controller, wherein: in a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system, and in a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.