Patent ID: 6876596
Filing Date: 2005-04-05
Classification: G11C

Abstract:
1. A bit line decoding circuit for accessing an array of two-bit memory cells comprising, a first stage containing pass gates whose first nodes are connected to sixteen bi-directional bit lines, whose second nodes are connected to bi-directional intermediate nodes, and whose third nodes are connected to first stage control signals wherein said control signals drive pairs of bits of said first stage pass gates, wherein said first stage control signals drive said pairs of pass gates which are associated with bit lines a second stage containing pass gates whose first nodes are connected to said bi-directional bit intermediate nodes, whose second nodes are connected to bi-directional sense driver lines, and whose third nodes are connected to second stage control signals, and bi-directional sense/driver circuits whose first nodes are from said second stage and whose second nodes are connected to selection switches which select which sense/driver circuit is accessed for reading or programming said two-bit memory cells.