Patent ID: 9136008
Filing Date: 2015-09-15
Classification: G11C

Abstract:
1. A flash memory apparatus, comprising: a memory unit, comprising a plurality of memory cells; a source discharge transistor, having a drain coupled to sources of the memory cells and having a source coupled to a ground; a pre-charge unit, coupled to a gate of the source discharge transistor and controlled by a pre-charge control signal to stop providing a pre-charge voltage to the gate of the source discharge transistor when the memory unit performs a data reading operation; a boost unit, coupled to the gate of the source discharge transistor and providing a boost voltage to the gate of the source discharge transistor according to a boost voltage control signal after the pre-charge unit stops providing the pre-charge voltage, wherein a level of the boost voltage is greater than a level of the pre-charge voltage; and a control unit, coupled to the pre-charge unit and the boost unit and sending the pre-charge control signal and the boost voltage control signal according to a read command.