Patent ID: 6285589
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A non-volatile semiconductor memory apparatus, comprising:a memory cell transistor, having an insulated floating gate electrode in which a charge is stored, said memory cell transistor varies a resistance thereof, when enabled, in accordance with an amount of charge stored in said floating gate electrode; a plurality of reference transistors, having a same structure as said memory cell transistor and being disposed in a row therewith; a bit line, which connected to said memory cell transistor; a plurality of reference bit lines, which connected to said plurality of reference transistors; a write circuit for supplying a common write clock having a predetermined cycle to said memory cell transistor and said plurality of reference transistors, and writing data to said memory cell transistor and said plurality of reference transistors; and a controller for detecting the resistances of said memory cell transistor and said plurality of reference transistors during leisure times in the writing operation of said write clock, stopping the supply of said write clock from said write circuit to said memory cell transistor when the detected resistance of said memory cell transistor reaches a purpose value corresponding to write data, and sequentially stopping the supply of said write clock from said write circuit to said plurality of reference transistors when the detected resistances of said plurality of reference transistors have reached a plurality of reference values which are set in steps.