Patent ID: 6723644
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device comprising:forming a plurality of conductive patterns at densities that differ, in first and second regions, along a surface of a semiconductor substrate, the density of the conductive patterns in the first region being greater than the density of the conductive patterns in the second region, and the conductive patterns comprising a first stopper layer at the top thereof, whereby trenches are formed between adjacent ones of all of the conductive patterns, the tops of the trenches thus being located at the same level as an upper surface of said first stopper layer; overfilling the trenches and forming an interlayer insulating layer on the conductive patterns wherein the interlayer insulating layer has a greater thickness at said first region than at said second region such that a step is defined in said interlayer insulating layer; forming a second stopper layer on the interlayer insulating layer; forming an etching mask on the second stopper layer that exposes and covers the first and second regions in which the conductive patterns are present; using the etching mask to etch the second stopper layer and the interlayer insulating layer at said first region, while leaving the second stopper layer and the interlayer insulating layer at said second region where the density of the conductive patterns is lower; performing a first polishing of the resultant structure using a slurry having a polishing rate that is higher for the interlayer insulating layer than for the first and second stopper layers so as to expose the surface of the first stopper layer at said first region; and performing a second polishing of the resultant structure using a slurry having a polishing rate that is higher for the second stopper layer than for the first stopper layer and the interlayer insulating layer so as to remove the second stopper layer from said second region.