Patent ID: 8335908
Filing Date: 2012-12-18
Classification: G06F,Y02D

Abstract:
1. Apparatus for processing data comprising: translation buffering circuitry configured to store a plurality of memory address translation entries, each translation entry providing a conversion from a virtual memory address to a physical memory address, said buffering circuitry comprising: a primary storage bank configured to store at least one primary address translation entry; a secondary storage bank configured to store at least one secondary address translation entry; storage bank accessing circuitry configured to be responsive to receipt of a virtual memory address for which a translation is required to perform parallel access to both said primary storage bank and said secondary storage bank to establish if any of said at least one primary address translation entry and said at least one secondary address translation entry represents a match for said virtual memory address; buffering management circuitry configured to transfer at least one address translation entry between said primary storage bank and said secondary storage bank depending upon an occupancy level of at least one of said primary storage bank and said secondary storage bank.