Patent ID: 6737321
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method of manufacturing a flash memory device, comprising the steps of:forming a plurality of oxide film line patterns and a plurality of isolating cell isolation films in a semiconductor substrate; forming tunnel oxide films and conductive layers for a floating gate at an exposed portion of the semiconductor substrate; patterning the conductive layers for the floating gate; sequentially forming a dielectric film, a conductive layer for a control gate and a hard mask layer on the entire structure including the conductive layers for the floating gate; patterning the conductive layers for the control gate and the patterned conductive layers for the floating gate to form a plurality of control gates and a plurality of floating gates; removing an exposed portion of the oxide film line pattern by means of a self-aligned source etch process to expose the semiconductor substrate; and forming a plurality of drains and a plurality of common source lines by means of a cell source/drain implantation process.