Patent ID: 6272583
Filing Date: 2001-08-07
Classification: G06F,G11C

Abstract:
A microprocessor for an image processing system, said microprocessor having a built-in dynamic random access memory (DRAM), comprising:input means for inputting data at a maximum of n bits at a time through a first external system bus and for storing said data into a first buffer, said first buffer having a maximum size of n.times.p bits, and p is a predetermined number, n and p being natural numbers;transfer means for transferring said data stored in said first buffer to said DRAM through an internal system bus, whose data transfer speed is higher and whose data width is wider than a data transfer speed and a data width of said first external system bus, said transferring occurring only when a) the number of data input operations performed by said input means reaches the predetermined number p not less than two and b) said first buffer is filled with said data; andoutput means for reading said data stored in said DRAM through said internal system bus, for writing said data into a second buffer, and for outputting said data in said second buffer to a second external system bus,wherein said first and second external system buses connected to said first buffer and said second buffer, respectively, operate independently of each other.