Patent ID: 6096131
Filing Date: 2000-08-01
Classification: B41C,B41N,H05K,Y10T

Abstract:
A multi-layered, laminate stencil for use in applying solder paste to a printed circuit board, said stencil comprising:a first layer of metal material having defined therein first and second pluralities of apertures and at least one polished surface;a second layer of metal material laminated to said first layer of metal material and overlying a selected portion of said at least one polished surface of said first layer to form a region of increased stencil thickness and to also leave exposed a portion of said at least one polished surface of said first layer having said first plurality of apertures therein, said second layer also including a polished surface and further including a third plurality of apertures therein, selected ones of said third plurality of apertures aligning with selected ones of said second plurality of apertures in said first layer.