Patent ID: 6610592
Filing Date: 2003-08-26
Classification: H01L

Abstract:
A method for integrating low-K dielectric materials in dual damascene interconnect semiconductor fabrication, comprising the steps of:a. providing a semiconductor structure having a dielectric layer thereover; said dielectric layer being comprised of a single homogeneous low-K material; said low-k material having a dielectric constant of less than about 3.2; b. patterning said dielectric layer to form a matrix of pillar openings together with via and interconnect openings within said low-k material; said matrix of pillar openings terminating on the surface of inactive areas of the semiconductor structure; said via openings terminating on the surface of active areas of the semiconductor structure; said interconnect openings being connected to the active areas of the semiconductor structure through said via openings; c. depositing a fill layer over said dielectric layer; thereby filling said matrix of openings together with said via and interconnect openings within said low-k dielectric with said fill layer; and d. planarizing said fill layer to form structural pillars together with vias and interconnect embedded in said low-k dielectric layer.