Patent ID: 8497970
Filing Date: 2013-07-30
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising: a base substrate; a display area comprising gate lines and data lines formed on the base substrate, wherein a pixel electrode and a first thin film transistor are formed in each of pixel units defined by the gate lines and the data lines which are crossed with each other, and the gate lines comprises a first gate line and a second gate line; and a dummy area which is at the periphery of the display area, which comprises a second thin film transistor and a connecting structure for each gate line, wherein the first gate line and the second gate line are connected with each other through the second thin film transistor and the connecting structure for the first gate line, wherein the gate lines further comprises a third gate line, the third gate line is connected with the second gate line through an additional thin film transistor and an additional connecting structure for the second gate line, the additional thin film transistor and the additional connecting structure are of the same structure as that of the second thin film transistor and the connecting structure for the first gate line, when a voltage of V is applied to the first gate line, the voltage over the second gate line is V wherein the resistance of the connecting structure and the additional connecting structure is set so that V