Patent ID: 8017469
Filing Date: 2011-09-13
Classification: H01L

Abstract:
1. A semiconductor fabrication process comprising: providing a wafer comprising a first semiconductor layer having a PMOS device area and an NMOS device area; forming a compressive silicon germanium layer on at least the PMOS device area; selectively forming a deposited first high-k dielectric layer over the compressive silicon germanium layer, where the first high-k dielectric layer is formed from a first dielectric material which has a first dielectric constant value of 7.0 or greater; depositing a second high-k dielectric layer over the first high-k dielectric layer in the PMOS device area and over the first semiconductor layer in the NMOS device area, where the second high-k dielectric layer is formed from a second dielectric material which has a dielectric constant value that is higher than the first dielectric constant value; and depositing one or more gate electrode layers over the second high-k dielectric layer.