Patent ID: 7958476
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. A power optimization method of deriving gated circuitry in an integrated circuit (IC) design, the method comprising: identifying, with one or more processors associated with one or more computer systems, one or more state machines in a representation of the IC design; generating, with the one or more processors associated with one or more computer systems, a synthesized netlist of the IC design based on the representation of the IC design; identifying downstream logic of at least one state machine in the one or more state machines; analyzing, with the one or more processors associated with one or more computer systems, the downstream logic; determining, with the one or more processors associated with one or more computer systems, one or more candidate blocks in the downstream logic of the synthesized netlist which are capable of being disabled; identifying, with the one or more processors associated with one or more computer systems, a sequential element in the one or more candidate blocks based on one or more states in the at least one state machine, wherein the one or more candidate blocks are controlled by the at least one state machine; identifying, with the one or more processors associated with one or more computer systems, a gating condition in the at least one state machine that inhibits a clock transition in the sequential element; inserting, with the one or more processors associated with one or more computer systems, a gating circuit in the IC design for gating the one or more candidate blocks in the downstream logic.