Patent ID: 6788596
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array having a plurality of memory cells accessed by an internal address; a plurality of redundant memory cells accessed by a failed cell address of a failed memory cell, the redundant memory cells being used for repairing the failed memory cell; a comparator for comparing data output from the memory cells during testing the semiconductor memory device as packaged and for generating a comparative output signal; a mode setting register for storing a failed cell address programming control signal in response to a mode control signal; an address generating circuit for generating the internal address by buffering and latching an externally applied address; a failed cell address programming circuit for latching the internal address output from the address generating circuit in response to the failed cell address programming control signal when the comparative output signal indicates that a failed memory cell is detected in the semiconductor memory device and programming the latched internal address as the failed cell address; and a failed cell address coding circuit for generating a redundant memory cell selection signal when the internal address output from the address generating circuit and the failed cell address output from the failed cell address programming circuit correspond, wherein the redundant memory cell is accessed in response to the redundant memory cell selection signal.