Patent ID: 7715272
Filing Date: 2010-05-11
Classification: G11C

Abstract:
1. A semiconductor device for counting a latency using a normal-phase clock and a reverse-phase clock which have phases in a mutually complementary relation and are obtained by frequency-dividing an external clock by two, comprising: a latency setting circuit capable of selectively setting the latency within a range of a predetermined number of clock cycles of the external clock; an input command circuit for outputting a normal-phase command signal obtained by capturing an input command signal using the normal-phase clock and a reverse-phase command signal obtained by capturing the input command signal using the reverse-phase clock; a first counter circuit including a plurality of latch circuits for sequentially shifting the normal-phase command signal based on the normal-phase clock; a second counter circuit including a plurality of latch circuits for sequentially shifting the reverse-phase command signal based on the reverse-phase clock; a selector circuit for selectively controlling a signal path so that when an even latency is set, the normal-phase command signal is transmitted through the first counter circuit while the reverse-phase command signal is transmitted through the second counter circuit, and when an odd latency is set, the normal-phase command signal is transmitted so as to be shifted from the first counter circuit to the second counter circuit while the reverse-phase command signal is transmitted so as to be shifted from the second counter circuit to the first counter circuit; and a control circuit for controlling so that all or part of the plurality of latch circuits of the first counter circuit and all or part of the plurality of latch circuits of the second counter circuit are activated in response to the input command signal and stopped after a predetermined operation period defined by a setting of the latency is elapsed.