Patent ID: 8664759
Filing Date: 2014-03-04
Classification: H01L

Abstract:
1. An integrated circuit die comprising: a substrate having an upper surface; at least one active device formed in a first area of the upper surface of the substrate; a plurality of layers formed on the upper surface of the substrate above the at least one active device; a first stacked heat conducting structure spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers; a lateral heat conducting structure formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure; and a second stacked heat conducting structure in thermal contact with the lateral heat conducting structure and spanning from a point proximate to a second area of the upper surface of the substrate through the plurality of layers, the second area of the substrate being laterally removed from the first area of the substrate; wherein the first stacked heat conducting structure is electrically isolated from the active device; wherein the first stacked heat conducting structure is formed vertically above the active device; wherein an initial element of the first stacked heat conducting structure is in thermal contact with an oxide layer overlying the active device; and wherein heat generated in the first area by the active device is conducted by the first stacked heat conducting structure to the lateral heat conducting structure.