Patent ID: 8067698
Filing Date: 2011-11-29
Classification: H01L,H05K

Abstract:
1. A wiring substrate for use in a semiconductor apparatus, comprising: a conductor layer laminated to a top surface and a bottom surface of a substrate core so as to pattern the substrate core; a via penetrating through the substrate core so as to electrically connect between the top surface and the bottom surface of the substrate core to which the conductor layer is laminated; a bonding pad positioning area positioned on the conductor layer laminated to the top surface of the substrate core; and a solder resist laminated to the top surface and the bottom surface of the substrate core to which the conductor layer is laminated, wherein the solder resist fills a portion in which the substrate core is penetrated, and the solder resist is not laminated to an external electrode positioning area on the bottom surface of the substrate core, wherein the solder resist laminated to the top surface of the substrate core is thickest in a center portion of the wiring substrate for use in the semiconductor apparatus on an inner area of the wiring substrate surrounded by the bonding pad positioning area, and forms a raised portion having a flat top surface.