Patent ID: 6961399
Filing Date: 2005-11-01
Classification: H03L

Abstract:
1. A phase locked loop (PLL) circuit having a receiver voltage controlled oscillator (VCO), a transmitter VCO, and a crystal oscillator, the PLL circuit comprising: a control circuit for generating a reference control signal in response to a reception enable signal and a transmission enable signal; a reception divider for receiving a reception division data signal in response to the reception enable signal and dividing an output signal of the receiver VCO according to the reception division data signal; a reference divider for receiving a reference division data signal in response to the reference control signal of the control circuit and dividing the output signal of the crystal oscillator according to the reference division data signal; a transmission divider for receiving a transmission division data signal in response to the transmission enable signal and dividing an output signal of the transmitter VCO according to the transmission division data signal; a first phase detector for detecting frequency and phase differences between an output signal of the reception divider and an output signal of the reference divider; and a second phase detector for detecting the frequency and phase differences between an output signal of the transmission divider and the output signal of the reference divider.