Patent ID: 8609509
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A method, comprising: forming a gate dielectric material and a first electrode material on a semiconductor layer of a semiconductor device; forming an isolation region in said semiconductor layer so as to laterally delineate active regions in said semiconductor layer, said isolation region extending through said gate dielectric material and said first electrode material; forming a second electrode material above said active regions and said isolation region; and forming gate electrode structures at least from said second electrode material, said gate dielectric material and said first electrode material, wherein a first end portion of at least one of said gate electrode structures is positioned above a first portion of said isolation region and a second end portion of said at least one of said gate electrode structures is positioned above a second portion of said isolation region, said first portion of said isolation structure being laterally separated from said second portion of said isolation structure by at least one of said active regions.