Patent ID: 6339003
Filing Date: 2002-01-15
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising the steps of:forming a field oxide layer defining an active area and a field area on a semiconductor substrate of a first conductive type; forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate; forming impurity regions of a second conductive type in the semiconductor substrate in use of the gate as a mask; forming a first insulating interlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate; forming a second insulating interlayer on the first insulating interlayer by depositing another insulator of which etch rate is different from that of the first insulating interlayer; forming a third insulating interlayer on the second insulating interlayer by depositing another insulator of which etch rate is different from that of the second insulating interlayer; and forming a first contact hole and second contact holes exposing the gate and heavily doped regions respectively by patterning the third to first insulating interlayer successively by photolithography.