Patent ID: 6222230
Filing Date: 2001-04-24
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate; anda plurality of transistors positioned on a plurality of active areas of the substrate, each of the transistors hang a doped region positioned in the substrate, a first insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region, the first insulating layer having a base, a first upwardly sloping sidewall having a first upper surface and a second upwardly sloping sidewall having a upper surface, a gate electrode positioned on the insulating layer and having first and second side surfaces projecting above the substrate, and a second insulating layer positioned on the substrate adjacent to the first and second side surfaces of the gate electrode and covering the first and second upper surfaces of the first insulating layer.