Patent ID: 7745326
Filing Date: 2010-06-29
Classification: H01L

Abstract:
1. A method of producing a semiconductor device including a plurality of wiring layers, comprising: forming a first interlayer-insulating film; forming a plurality of first grooves for wiring in the first interlayer-insulating film; forming a first wiring layer by filling metallic films in the first grooves for wiring; polishing and removing upper surfaces of the first wiring layer and the first interlayer-insulating film to flatten the upper surfaces thereof; forming a second interlayer-insulating film on flattened upper surfaces of the first wiring layer and the first interlayer-insulating film; simultaneously forming a first contact hole and a second groove for wiring in the second interlayer-insulating film; forming a second wiring layer including a wiring and plug by filling metallic films in the second groove for wiring; polishing and removing upper surfaces of the second wiring layer and the second interlayer-insulating film to flatten the upper surfaces thereof; etching the second interlayer-insulating film with the second wiring layer as a mask and removing a portion of the second interlayer-insulating film between the second wiring layers to provide grooves to be filled; depositing a third interlayer-insulating film on the second interlayer-insulating film and the second wiring layer; performing a thermal process at a predetermined temperature to promote dehydrating polymerization and solvent evaporation to generate pores in the third interlayer-insulating film so as to form a porous insulating film; and polishing and removing an upper surface of the third interlayer-insulating film to flatten the upper surface thereof.