Patent ID: 6507899
Filing Date: 2003-01-14
Classification: G06F

Abstract:
Interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output, comprising:an address buffer having an input and an output, said input receiving an address signal from said data handling unit; a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal; a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input; a second multiplexer for selecting either said memory data signal output or said data buffer output; a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer; and a further multiplexer comprising two inputs and an output is provided, said output being coupled with the data input of said memory, the first input being coupled with the output of said data buffer, and the second input receiving said data signal from said data handling unit.