Patent ID: 8207534
Filing Date: 2012-06-26
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line and a data line formed on the substrate and crossing each other; a thin film transistor connected to the gate line and the data line; and a pixel electrode connected to the thin film transistor, wherein the pixel electrode is comprised of a transparent conductive layer which comprises a first layer and a second layer formed upon the first layer; wherein the first layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO) or amorphous indium tin oxide (a-ITO); and wherein the second layer comprises indium tin oxide nitride (ITON) when the first layer comprises ITO, the second layer comprises indium zinc oxide nitride (IZON) when the first layer comprises IZO, and the second layer comprises amorphous indium tin oxide nitride (a-ITON) when the first layer comprises a-ITO.