Patent ID: 6745359
Filing Date: 2004-06-01
Classification: G01R

Abstract:
A masking circuit for use in an integrated circuit for masking bits in scan chains in said integrated circuit, comprising:mask storage means including: a scan chain mask register for storing a scan chain mask, said register having chain mask register elements, each said elements being associated with one or more scan chains identifying scan chains in which bits are to be masked; a bit position mask register for storing a position mask, said position mask register having position mask register elements, each said position mask register elements storing position mask bit identifying scan chain bit positions to be masked; and a gating circuit having a scan chain input for each said scan chain connected to the serial output of said scan chains, a bit position mask input connected to bit position mask register, a chain mask input connected to said chain mask register, first coupling means for coupling said position and chain mask inputs and generating a masking bit and second coupling means for coupling said masking bit with a serial output of each said scan chain.