Patent ID: 7473596
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A memory cell fabrication method comprising: forming an electrically isolated silicon base within a substrate; forming a second capacitor electrode by depositing a second electrode layer on the substrate, removing some of the second electrode layer, and forming a first opening completely through the second electrode layer, exposing the substrate; forming a capacitor dielectric by depositing a dielectric layer within the first opening and over a sidewall of the first opening, removing some of the dielectric layer, and forming a second opening completely through the dielectric layer, exposing the substrate; forming a combined first capacitor electrode and first transistor source/drain within the first and second openings and over the dielectric by epitaxial growth of a silicon column from the silicon base, the dielectric being between the first and second electrodes; and forming a vertical transistor above and including the first source/drain.