Patent ID: 7045414
Filing Date: 2006-05-16
Classification: H01L

Abstract:
1. A method of fabricating a transistor, comprising: providing a substrate comprising an isolation region and an active region; forming a first doped region in the active region of the substrate with a first plurality of ions; driving in the ions of the first doped region further into the substrate to enlarge the first doped region and to make boundaries of the first doped region graded; forming a gate electrode over the substrate after the driving in step, wherein at least part of the gate electrode is located in the active region, and wherein at least part of the gate electrode extends over a part of the first doped region; forming a spacer along edges of the gate electrode to form an intermediate structure; forming a second doped region with a second plurality of ions within the first doped region, wherein a gate-side boundary of the second doped region is spaced away from a closest edge of the gate electrode by a first spaced distance, wherein the gate-side boundary of the second doped region is spaced away from a closest edge of the spacer by a second spaced distance, the second spaced distance being less than the first spaced distance, and wherein the spacer does not cover the second doped region.