Patent ID: 7542349
Filing Date: 2009-06-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of nonvolatile memory cell transistors that are electrically data erasable and writable; a source line connected to sources of the nonvolatile memory cell transistors; a word line connected to control gates of the nonvolatile memory cell transistors; a high voltage generation circuit generating a high voltage for erasing and writing data; a high voltage switching circuit switching in response to a selection signal and outputting the high voltage generated by the high voltage generation circuit; a first switch outputting the high voltage outputted by the high voltage switching circuit to the source line in response to a write enable signal; a second switch outputting the high voltage outputted by the high voltage switching circuit to the word line in response to an erase enable signal; and a third switch outputting the high voltage generated by the high voltage generation circuit to the source line bypassing the high voltage switching circuit in response to the write enable signal.