Patent ID: 6381667
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A method that supports multiple delayed read transactions between a host bus and a peripheral bus in a computer system, comprising:receiving a first request from the host bus that is directed to the peripheral bus; storing the first request in a first buffer; sending the first request to the peripheral bus, so that the first request will be processed when the peripheral bus becomes available; if the first request is a read operation, waiting a predetermined amount of time to receive a pipelined request from the host bus that is directed to the peripheral bus, the pipelined request being received before the first request is completed; if the pipelined request is received and if the pipelined request is a read operation, storing the pipelined request in a second buffer, and sending the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available; and issuing a retry request across the host bus, the retry request causing both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions while the first request and the pipelined request are in process on the peripheral bus.