Patent ID: 6242980
Filing Date: 2001-06-05
Classification: H03F

Abstract:
A differential amplifier circuit for an oscillation circuit, said differential amplifier circuit comprising:a first signal and a second signal from first and second terminals, respectively, of an oscillator, each of said first and second signals having an operating point potential that is different than the other;a first MOS transistor of a first conductivity type having a source, a drain and a gate, and receiving said first signal at the gate thereof;a second MOS transistor of the first conductivity type having a source, a drain and a gate, and receiving said second signal at the gate thereof;a first current mirror circuit comprising a third and a fourth MOS transistors of a second conductivity type each having a source, a drain and a gate, the drains of said third and fourth MOS transistor being connected to the drains of said first and second MOS transistors, respectively, the gates of the third and fourth MOS transistors connected to each other and the gate and drain of said third MOS transistor;a fifth MOS transistor of the second conductivity type having a source, a drain and a gate, and receives the first signal at the gate thereof;a sixth MOS transistor of the second conductivity type having a source, a drain and a gate, and receiving the second signal at the gate thereof;a second current mirror circuit comprising a seventh and an eighth MOS transistors of the first conductivity type each having a source a drain and a gate, the drains of said seventh and eighth MOS transistors being connected to the drains of said fifth and sixth MOS transistors, respectively, the gates of the seventh and eighth MOS transistors being connected to each other and the gate and drain of said seventh MOS transistor being connected; andan output buffer circuit for generating an output signal based on a signal generated at the drain of said fourth MOS transistor and a signal generated at the drain of said eighth MOS transistor;wherein the gates of said third and fourth MOS transistors and the gates of said seventh and eighth MOS transistors are connected, and said output buffer circuit is a CMOS inverter having an input terminal being connected to the connection point between the drain of said fourth MOS transistor and the drain of said eighth MOS transistor.