Patent ID: 7307559
Filing Date: 2007-12-11
Classification: H03M

Abstract:
1. A parallel-to-serial converter circuit comprising: a select-signal generator circuit for generating a select signal specifying an integer (m1) which is set variably within a range of a predetermined number (m), where 0≦m1≦m; a parallel-to-serial converter section for receiving parallel data including an n-bit parallel data signal and in-bit parallel dummy data in synchrony with a first clock signal having a first frequency, and selecting, based on said specified integer m1, m1-bit parallel dummy data from said m-bit parallel dummy data together with said n-bit parallel data signal, to convert said selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal; and a serial-data synchronization circuit for synchronizing said (n+m1)-bit serial data signal with a second clock signal having a second frequency which is (n+m1) times said first frequency.