Patent ID: 8207613
Filing Date: 2012-06-26
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a cell array layer which is formed above the semiconductor substrate and includes a first wiring and a second wiring, which cross each other, and a memory cell connected to the first and second wirings at an intersection thereof; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third wiring and the fourth wiring, wherein the third wiring and the fourth wiring respectively extend in directions which are at right angles to each other, the semiconductor memory device further comprises a redundant wiring formed between the first wiring layer and the second wiring layer, the redundant wiring having a first portion extending in the same direction as an extending direction of the third wiring and a second portion extending in the same direction as an extending direction of the fourth wiring, and the third wiring and the first portion of the redundant wiring being connected by a plurality of contacts arranged along the first portion, and the fourth wiring and the second portion of the redundant wiring being connected by a plurality of contacts arranged along the second portion.