Patent ID: 8987142
Filing Date: 2015-03-24
Classification: H01L,Y10S

Abstract:
1. A multi-patterning method comprising: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer is coextensive with a pattern-free region adjacent and extending to a location where a respective first circuit pattern is to be formed, and patterning a second circuit pattern in the hard mask layer using a second mask, wherein the second circuit pattern is located between and excluded from the pattern-free regions adjacent the respective first circuit pattern in each of said two of the at least two first openings, wherein a distance between said two of the at least two first openings in the hard mask layer is a line width of the second circuit pattern.