Patent ID: 6026030
Filing Date: 2000-02-15
Classification: G11C

Abstract:
An echo IC, comprising:a plurality of storage cells arranged into an N.times.M matrix, each of said storage cells including a dynamic random access memory (DRAM) and N and M being positive integers;a plurality of clock signal inputs to said matrix; anda plurality of write terminals, read terminals, input terminals, and output terminals connected to respective said storage cells;wherein said matrix is arranged to be driven by N different clock signals to cause a series of digital pulse data is inputted into said matrix and outputted from said matrix,wherein each of said N different clock signals has a same period T and said N different clock signals are sequentially phase shifted one after another by a time T/N,wherein each pulse of said digital pulse data is separated by said time T/N,wherein each of said N different clock signals is maintained within a related pulse or delayed pulse of said digital pulse data, andwherein each of said N different clock signals drives each write terminal of N.times.M matrix storage cells of a related row and drives each read terminal of M storage cells of the next row, while said digital pulse data is inputted into each input terminal of the storage cells of the first column, each output terminal of the storage cells in each column are interconnected to an inverter, and an output of said inverter is connected to each input terminal of the storage cells of the next column.