Patent ID: 6781191
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A stacked gate flash memory cell, comprising:a substrate having a trench therein; a conductive layer disposed on the bottom of the trench; a pair of source regions, each disposed in the substrate adjacent to one sidewall of the trench and electrically connected by the conductive layer; a source isolation layer disposed on the conductive layer; a pair of tunnel oxide layers, respectively disposed on one sidewall of the trench and the source isolation layer; a U-shaped floating gate disposed on the source isolation layer, contacting the tunnel oxide layers thereby; a pair of control gate spacers, respectively disposed on each vertical portion of the U-shaped floating gate, substantially having the same width as the vertical portions; a U-shaped inter-gate dielectric layer disposed on the U-shaped floating gate and the control gate spacers; a control gate disposed in the U-shaped inter-gate dielectric; and a drain region disposed in the substrate adjacent to the trench.