Patent ID: 8661285
Filing Date: 2014-02-25
Classification: G06F,G11C

Abstract:
1. A DDR memory controller for read operations, comprising: a dqs clock driven by a DDR memory; a core clock originating within the DDR memory controller; a dqs delay element producing a delayed dqs; a dq read data register clocked by the delayed dqs; a core clock delay element that produces a capture clock; a first core domain register responsive to said dq read data register and clocked by said capture clock; a second core domain register responsive to said first core domain register and clocked by the core clock; a dynamically self-configuring logic circuit responsive to said read data register and said first and second core domain registers, for controlling said core clock delay element; and wherein the delay of the core clock delay element is set using said self-configuring logic circuit by a calibration procedure completed during operation of the DDR memory controller.