Patent ID: 6473330
Filing Date: 2002-10-29
Classification: G11C

Abstract:
A ferroelectric memory comprising:a memory cell unit comprising a plurality of memory cells in each of which one of two electrodes of a ferroelectric capacitor is electrically connected to a source of a first MOS transistor and the other electrode to a drain thereof; a plurality of word lines each of which is electrically connected to a gate of said first MOS transistor; a plate line electrically connected to one of the two electrodes of a first memory cell in said memory cell unit; a bit line electrically connected to the other electrode of a second memory cell in the memory cell unit via a block select switching device; a sense amplifier to compare and amplify voltages of a bit line pair of said bit line and a bit line complementary to said bit line; and a second MOS transistor inserted between the block select switching device and the sense amplifier; wherein a relation VPP12 is provided, VPP1 being a minimum voltage appearing at a gate of the second MOS transistor when a plate line voltage has been elevated and the sense amplifier is performing comparative amplification, and VPP2 being a maximum voltage appearing at the gate of the second MOS transistor when the plate line voltage has been lowered and the sense amplifier is performing comparative amplification.