Patent ID: 7975200
Filing Date: 2011-07-05
Classification: G06F,H03M

Abstract:
1. A method for designing an error correction code (ECC) decoding architecture using synthesis-time design parameters, the method comprising: receiving a plurality of predetermined architecture parameters; selecting a first plurality of semi-soft design constraints based on the plurality of predetermined architecture parameters; selecting a first parallel implementation of a plurality of processing modules employed within the ECC decoding architecture; generating a first version of the ECC decoding architecture based on the first plurality of semi-soft design constraints and the first parallel implementation of a plurality of processing modules; determining whether the first version of the ECC decoding architecture meets a time constraint; if the first version of the ECC decoding architecture does not meet the time constraint, then: if the first version of the ECC decoding architecture meets the time constraint, then employing the first version of the ECC decoding architecture to design at least a portion of the communication device that is operable to decode the coded signal.