Patent ID: 7472055
Filing Date: 2008-12-30
Classification: G06F

Abstract:
1. A deterministically operated emulation system for verifying performance of a device under test (DUT) comprising: an application module that generates transactions to evaluate the DUT; a hardware transactor coupled to the application module, the transactor converting the transactions to commands designated for the DUT; an emulator coupled to the transactor, the emulator having a hardware channel controller that forwards the commands to the DUT, which produces a set of events in response to the commands; an emulation clock that can be started by the application module and that can be stopped by the transactor, wherein the starting and stopping of the clock is accurate to within one clock cycle, wherein the hardware transactor gathers the data while the clock is stopped and forwards the data to multiple output channels simultaneously when the clock is restarted, wherein multiple, independent parallel transactions are executed, and; wherein the set of events can be viewed in real-time or recorded for later review and can be compared with a set of expected or predicted events to evaluate performance of the DUT.