Patent ID: 6773986
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory device, which comprises:forming at least one of a semiconductor substrate, a passivation region, and a surface region with a CMOS structure; forming a capacitor configuration of a plurality of capacitor devices serving as storage elements in a region of the at least one of the semiconductor substrate, the passivation region, and the surface region; at least one of forming and patterning respective ones of the capacitor devices at least one of partially and locally in a fashion extending substantially vertically with respect to the at least one of the horizontally extending semiconductor substrate, the passivation region, and the surface region, and, as a result, at least one of forming and patterning a three-dimensional configuration extending at least one of partially and locally into a third dimension with respect to the at least one of the semiconductor substrate, the passivation region, and the surface region for a respective one of the capacitor devices; and forming a contact connection of the capacitor devices and of the electrode devices with the CMOS structure by plug regions after production of the capacitor devices.