Patent ID: 8456916
Filing Date: 2013-06-04
Classification: G11C,H01L

Abstract:
1. An only-one-polysilicon layer non-volatile memory unit cell comprising: a first P-type transistor having a gate and a first source/drain; a second P-type transistor having a gate and a first source/drain; a N-type transistor pair having a third transistor and a fourth transistor that are connected, the third transistor and the fourth transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated; a first coupling capacitor, one end of the first coupling capacitor being connected to the gate of the first transistor and coupled to the first floating polysilicon gate, the other end of the first coupling capacitor receiving a first control voltage; and a second coupling capacitor, one end of the second coupling capacitor being connected to the gate of the second transistor and coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receiving a second control voltage, wherein the N-type transistor pair is connected to a switch transistor, when the switch transistor is turned on according to a word line signal, data stored in the only-one-polysilicon layer non-volatile memory unit cell are read out.