Patent ID: 6650010
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor substrate having an active device region and a passive region with multiple wiring levels separated by layers of insulating material extending therefrom to an uppermost wiring level of said semiconductor device and with at least some of said multiple wiring levels separated by low-k dielectric insulating material; a conductive pad formed at said uppermost wiring level in said passive region and at each successive wiring level therebeneath to at least the lowest of said wiring levels that is deposited upon other than a layer of low-k dielectric insulating material; and at least one conductive via having a cross-sectional area substantially smaller than the area of said conductive pad in contact with and arranged between the said conductive pad of said uppermost wiring level and the said conductive pad of the next lower wiring level and thence between each conductive pad at each said successive wiring level therebeneath to the said at least lowest of said wiring levels.