Patent ID: 6495406
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method for fabricating a field effect transistor comprising the steps of:providing a semiconductor substrate; forming a gate insulator layer covering the substrate; forming a first conductive layer on the gate insulator layer; forming an etch stop layer on the upper surface of the first conductive layer wherein the etch stop layer comprises undoped polysilicon formed contiguously with the first conductive layer; forming a second conductive layer covering the etch stop layer; forming a hard mask layer on the second conductive layer; patterning the hard mask layer to define a gate hard mask; etching the second conductive layer using the patterned hard mask as a mask to expose portions of the etch stop layer; forming sidewall spacers along exposed edges of the second conductive layer; implanting impurities through the etch stop layer, the first conductive layer, and the gate oxide using the patterned hard mask layer and the sidewall spacers as a mask to self-align source/drain regions; removing the sidewall spacers; etching the etch stop layer and the first conductive layer using the patterned hard mask as a mask; and implanting impurities through the first conductive layer and gate oxide using the hard mask as a mask to form lightly/doped source and drain regions.