Patent ID: 9123748
Filing Date: 2015-09-01
Classification: G11C,H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming first sacrificial layers and second sacrificial layers alternately with each other; forming channel holes by etching the first sacrificial layers and the second sacrificial layers; forming a floating gate material layer, a tunnel insulating layer, and a channel layer in the channel holes; forming slits by etching the first sacrificial layers and the second sacrificial layers; forming first recessed regions by removing the first sacrificial layers exposed in the slits; forming first charge blocking layers in the first recessed regions; forming conductive layers in the first recessed regions having the first charge blocking layers formed therein; forming second recessed regions by removing the second sacrificial layers exposed in the slits; forming floating gates by etching the floating gate material layer exposed through the second recessed regions; and forming interlayer insulating layers in the second recessed regions from which the floating gate material layer is etched.