Patent ID: 8426259
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A method for forming an array substrate comprising: 1) sequentially depositing a transparent conductive metal layer and a gate metal layer on a base substrate; 2) performing a patterning process by using a first dual-tone mask plate to form a pixel electrode pattern and a gate pattern comprising a gate electrode and a gate scanning line; 3) sequentially depositing a gate insulating layer and an active layer on the base substrate with the formed pixel electrode pattern and the gate pattern; 4) performing a patterning process by using a second dual-tone mask plate to form an active pattern corresponding to the gate electrode and a via hole in the gate insulating layer for exposing the pixel electrode, and remaining photoresist the active layer pattern; 5) depositing a source/drain metal layer on the base substrate with the active pattern and the via hole, through which the source/drain metal layer is in contact with the pixel electrode; 6) lifting off the photoresist remaining on the active layer pattern to remove the photoresist and a portion of the source/drain metal layer corresponding to the photoresist; and 7) performing a patterning process by using a third mask plate to forming a source/drain pattern, wherein the source/drain pattern comprises a data scanning line crossing with the gate scanning line, a source electrode and a drain electrode, and a portion of the drain electrode is in contact with the pixel electrode through the via hole.