Patent ID: 8222715
Filing Date: 2012-07-17
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first insulation interlayer, an etch stop layer and a second insulation interlayer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed; a second contact pad penetrating the first insulation interlayer, the etch stop layer and the second insulation interlayer and contacting the first contact pad; a pad spacer provided between the second contact pad and the first insulation interlayer and the second insulation interlayer; a landing pad provided on the second insulation interlayer and contacting the second contact pad, the landing pad having a cross-sectional area greater than that of the second contact pad; a lower electrode contacting the landing pad; and a dielectric layer and an upper electrode sequentially provided on the lower electrode.