Patent ID: 6084472
Filing Date: 2000-07-04
Classification: H03F,H03G

Abstract:
A multi-tanh cell comprising:a multi-tanh core having a plurality of differential pairs of transistors;a bias circuit coupled to the multi-tanh core for providing a plurality of bias currents and arranged so that each of the bias currents biases one of the differential pairs of transistors; anda bias signal generator for generating a bias signal responsive to a control signal;wherein the bias circuit varies the magnitude of a first one of the bias currents relative to at least a second one of the bias currents, thereby varying the shape of the transconductance function of the core;wherein the multi-tanh core includes a first differential pair of transistors coupled to a first node for receiving a first bias current, a second differential pair of transistors coupled to a second node for receiving a second bias current, and a third differential pair of transistors coupled to a third node for receiving a third bias current;wherein the bias circuit includes:a first bias transistor coupled to the first node for providing the first bias current;a second bias transistor coupled to the second node for providing the second bias current; anda third bias transistor coupled to the third node for providing the third bias current;wherein:the first bias transistor includes a first terminal coupled to the first node, a second terminal coupled to a power supply terminal, and a third terminal coupled to the bias signal generator to receive the bias signal;the second bias transistor includes a first terminal coupled to the second node, a second terminal coupled to the power supply terminal, and a third terminal coupled to the bias signal generator to receive the bias signal; andthe third bias transistor includes a first terminal coupled to the third node, a second terminal coupled to the power supply terminal, and a third terminal coupled to the bias signal generator to receive the bias signal; andwherein the bias circuit further includes:a first degeneration resistor coupled between the second terminal of the first bias transistor and the power supply terminal; anda second degeneration resistor coupled between the second terminal of the third bias transistor and the power supply terminal.