Patent ID: 9086834
Filing Date: 2015-07-21
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a first domain formed on a semiconductor die including a plurality of cores each to execute instructions; a second domain formed on the semiconductor die including at least one graphics engine to execute instructions; a non-volatile storage formed on the semiconductor die to store a plurality of maximum peak operating parameter values for an operating parameter, each of the maximum peak operating parameter values a function of a number of active cores of the processor; a storage formed on the semiconductor die to store a plurality of configurable clip parameter values for the operating parameter, based on a priori knowledge of a workload of an application to be executed on the processor, provided by a user; a configuration storage formed on the semiconductor die to store a plurality of parameter limits, each of the parameter limits corresponding to one of the maximum peak operating parameter values or a configurable clip parameter value less than the maximum peak operating parameter value obtained from the storage during runtime of the application to place a limit on an operating parameter, each of the non-volatile storage, the storage and the configuration storage comprising a different storage; and a power controller formed on the semiconductor die to place the limit on the operating parameter of at least one of the first domain and the second domain to a corresponding parameter limit obtained from the configuration storage, wherein the power controller is to store in the configuration storage a minimum of the corresponding maximum peak operating parameter value and the configurable clip parameter value, the configurable clip parameter value obtained from the user prior to execution of the workload, based on the a priori knowledge of the workload according to execution of the workload using the plurality of maximum peak operating parameter values to determine a failure surface.