Patent ID: 6711721
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A program product, which, when executed by a processor, performs a method for replacement of single vias by redundant vias on a semiconductor chip, comprising the steps of:determining a value for each single via on said chip indicative of a magnitude of a delay anomaly resultant from a resistive defect in said single via; replacing each single via with a redundant via if wiring area is available and no other single via contends for said area; comparing said value for each contending single via in a plurality of contending single vias in an area of contention where no more than one redundant via can be created; and replacing with a redundant via the contending single via in the plurality of contending single vias in the area of contention for which said value indicates the largest said delay anomaly would be caused by a resistive defect in said single via.