Patent ID: 6012148
Filing Date: 2000-01-04
Classification: G06F

Abstract:
An error detection and recovery circuit to monitor for hardware errors in a system having one or more logic units, the error detection and recovery circuit comprising:error detection means coupled to the one or more logic units for detecting errors in the one or more logic units, and for providing a plurality of error signals corresponding to different ones of the errors detected;first error recovery means for receiving the plurality of error signals, and for performing system-level recovery in response to each of the plurality of error signals;second error recovery means for receiving the plurality of error signals, and for performing unit-level recovery through real-time execution of error recovery routines at the logic unit generating the error; anderror recovery selection means, coupled to receive the plurality of error signals, for selectively enabling the first error recovery means to identify any of a first group of the plurality of error signals, and for selectively enabling the second error recovery means to identify any of a second group of the plurality of error signals.