Patent ID: 6757352
Filing Date: 2004-06-29
Classification: H03K

Abstract:
A power saving counter for a real time clock in an embedded system, the counter comprising:a first bit register for storing digital clock data, the first bit register comprising a first input for activating the first bit register according to an oscillating timing signal and a second input for receiving data to be stored in the first bit register; a first half adder for adding a first value to the value of the data stored in the first bit register, the first half adder comprising a first output for outputting a first binary sum term to the second input of the first bit register and a second output for outputting a first binary carry term according to the results of the addition; and a second bit register for storing digital clock data, the second bit register comprising a third input connected to an activation circuit for activating the second bit register when indicated by the oscillating timing signal and the first binary carry term.