Patent ID: 7180340
Filing Date: 2007-02-20
Classification: G06F,H03K,H03L

Abstract:
1. A frequency multiplier comprising: a delay circuit that receives a first clock signal having a first frequency and outputs a delayed clock signal, the delay circuit producing the delayed clock signal by applying a time delay to the first clock signal; an XOR gate that receives the first clock signal and the delayed clock signal, performs an XOR operation on the first clock signal and the delayed clock signal, and outputs a second clock signal; and a control circuit that detects a phase difference between the first clock signal and the delayed clock signal, and outputs a control signal to the delay circuit corresponding to the detected phase difference, the control signal being generated with respect to an internal first voltage and an internal second voltage reflecting the detected phase difference, wherein the control signal controls a duration of the time delay applied to the first clock signal by the delay circuit, the control signal is increased or decreased in response to a logic signal.