Patent ID: 6754863
Filing Date: 2004-06-22
Classification: G01R

Abstract:
A scan test interface comprising:a scan test interface register for storing information related to scan test operations that support both partial reset operations and full reset operations; a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices; a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register to support both a partial reset operation and full reset operation; a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain; a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain; and a reset circuit coupled to said scan test interface register, said reset circuit initiates a reset of said scan test interface register during a full reset operation, wherein said reset circuit comprises: a reset OR gate for issuing a reset signal when power is turned off or when a program scan interface (PSI) and test reset (TRSTN) signal are asserted; a voltage inverter coupled to said reset OR gate, said high logic voltage inverter outputs a logical one value momentarily when the power to said scan test interface is turned on and then outputs a logical zero value; a reset AND gate coupled to said reset OR gate, said reset AND gate outputs a logical one value when a program scan interface (PSI) signal and test reset (TRSTN) signal are asserted; and a test reset inverter coupled to said reset AND gate, said test reset inverter inverts said TRSTN signal.