Patent ID: 8028209
Filing Date: 2011-09-27
Classification: G01R,G06F,G11C

Abstract:
1. An apparatus comprising: one or more logic blocks; clock gating logic coupled with the one or more logic blocks to select one of a scan clock, an at-speed clock and a functional clock as an input clock to the one or more logic blocks; one or more memory blocks, wherein the clock gating logic is coupled with the one or more memory blocks to select one of the scan clock, the at-speed clock and the functional clock as another input clock to the one or more memory blocks; and one or more access logic blocks, each access logic block coupled with the clock gating logic and a respective one of the one or more memory blocks to facilitate one or more sequential pairs of a write enable signal and a read enable signal to the respective memory block using at least in part, a pulse from the clock gating logic.