Patent ID: 7919389
Filing Date: 2011-04-05
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor memory device comprising: a first region including a plurality of memory cell transistors, each memory cell transistor employing a first gate insulating layer having a laminated structure including at least a charge accumulating insulating layer; a second region including a plurality of transistors, each transistor employing a second gate insulating layer which is different from the charge accumulating insulating layer; and a third region including a plurality of transistors, each transistor employing a third gate insulating layer which is different from the charge accumulating insulating layer, and is thinner than the second gate insulating layer, the first, second and third regions being formed on a semiconductor substrate, wherein the first gate insulating layer is formed in the first, second and third region, the first gate insulating layer is removed in the second region, the second gate insulating layer is formed in the second region, mask layers to form element isolation trenches are formed in the first, second and third region, a first etching process is performed such that the charge accumulating insulating layer in the first region remains when the second gate insulating layer in the second region is already removed, and a second etching process is performed such that the first gate insulating layer in the first region is etched and at the same time the semiconductor substrate in the second region is etched, resulting in making a depth of a first element isolation trench in the first region, measured from a surface of the semiconductor substrate, shallower than a depth of a second element isolation trench in the second region, measured from the surface of the semiconductor substrate.