Patent ID: 6800522
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group pf the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line, wherein the bit line includes a diffusion barrier layer formed along the trench, a metal layer formed on the diffusion barrier layer and a hard mask insulation layer formed on the metal layer; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.