Patent ID: 8963967
Filing Date: 2015-02-24
Classification: G09G

Abstract:
1. A drive circuit driving each of pixels that are arranged in matrix in a display, each of the pixels being provided with a built-in memory that includes a liquid crystal cell, the drive circuit comprising: a division section configured to divide one frame period into a plurality of subfields, and to respectively divide one or more of the plurality of subfields to generate a plurality of division subfields, respective ones of the plurality of subfields corresponding to a respective bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and respective ones of the one or more of the plurality of subfields which have a period that is relatively long are divided into periods each equal to the period of a subfield which has a period that is relatively short; a correction section configured to rearrange, when bit arrays of the gray-scale data respectively corresponding to two adjacent pixels that are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two adjacent pixels to bring the first pixel bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two adjacent pixels, while maintaining the respective gray-scale levels of the first and second pixels; and an ON-OFF-period control section configured to control a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.