Patent ID: 6819593
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A method to suppress bit-line leakage in a nonvolatile memory cell comprising:providing an array of nonvolatile memory cells comprising source and bulk terminals wherein said array comprises a plurality of subarrays, wherein said sources of all said nonvolatile cells in each said subarray are coupled together to form a common subarray source, and wherein bulks of all said nonvolatile cells in said array are coupled together to form a common array bulk; forcing a first, non-zero voltage between said common subarray source and said common array bulk for a first said subarray that is selected for an access operation; and forcing a second, non-zero voltage between said common subarray source and said common array bulk for a second said subarray that is not selected for said access operation wherein said second, non-zero voltage will inhibit bit line leakage in said second subarry.