Patent ID: 9117850
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A method for fabricating a vertical JFET, the method comprising: providing a III-nitride substrate of a first conductivity type; forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate; forming a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer; forming a first masking layer coupled to the second III-nitride epitaxial layer; removing at least a portion of the first masking layer and the second III-nitride epitaxial layer to expose a vertical sidewall of the second III-nitride epitaxial layer and a horizontal surface of the first III-nitride epitaxial layer; forming a spacer coupled to the vertical sidewall of the second III-nitride epitaxial layer and the horizontal surface of the first III-nitride epitaxial layer; and removing at least a portion of the first III-nitride epitaxial layer to form a channel region of the vertical JFET, wherein the spacer is used as a mask to prevent removal of at least a portion of the horizontal surface of the first III-nitride epitaxial layer.