Patent ID: 8363497
Filing Date: 2013-01-29
Classification: G11C

Abstract:
1. A data control circuit comprising: an input/output line precharging circuit comprising: a drive signal generator configured to generate a drive signal in response to receiving a first enable signal that is activated in the reading operation and configured to generate the drive signal in response to receiving a second enable signal that is activated in the writing operation, wherein the input/output line precharging circuit is configured to precharge a global input/output line to a predetermined voltage when reading or writing operations are inoperative; and a driver comprising a number of MOS transistors and configured to drive the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation, wherein at least one of the MOS transistors, which drives the global input/output line, has a threshold voltage lower than threshold voltages of the other MOS transistors; wherein the first and second enable signals are different from each other.