Patent ID: 6260166
Filing Date: 2001-07-10
Classification: G01R

Abstract:
An observability register, of a plurality of observability registers connected in a serial chain manner, for generating sample data by sampling nodes of an electrical circuit, said observability register comprising:a tail portion for sampling said nodes of said electrical circuit in a manner such that the tail portion operates in a non-power consuming sleep mode during non-testing of the electrical circuit, said sleep mode eliminating power consumption outside of testing of the electrical circuit andwherein said nodes of said electrical circuit are sampled after an associated signal indicates that said nodes have been initialized;a serial input port for receiving input data to be operated on by the observability register;a serial output port for outputting output data operated on by the observability register;a configurable data path having a first configuration for transferring said sample data from said serial input port to said serial output port by bypassing said tail portion during non-testing, and said configurable data path having a second configuration for transferring said sample data from said serial input port to said serial output port by shifting said sample data through said tail portion during testing; anda control logic for configuring said configurable data path in said first configuration or in said second configuration.