Patent ID: 7870347
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. A data processing system comprising: memory device and a plurality of data processors accessing said memory device, at least one local memory unit associated with corresponding ones of said plurality of data processors, said local memory unit adapted to be selectively accessed by a memory access request of corresponding ones of said data processors, wherein said memory device and said local memory unit have a single address space and an address range within said single address space distinguishes between a memory access to said memory device and said local memory unit, a communication interface coupled between said memory device and said plurality of data processors and said at least one local memory unit, said communication interface including: a network of nodes and a memory interface, each node comprising at least one slave port for receiving a memory access request from a data processor or from a previous node and at least one master port for issuing a memory access request to a next node or to said memory device in accordance with the memory access request received at said slave port, wherein a corresponding one of the at least one master port is associated with a corresponding address range, wherein one or more slave ports are connected to a master port of a previous node, or to one of said data processors, and one or more said master ports are connected to the memory interface, wherein the memory interface arbitrates access to the memory device and said at least one local memory unit concurrently through corresponding master ports associated with corresponding address range based on an address associated with the memory access request, wherein the communication interface is positioned on a single chip, and wherein the memory device is not positioned on the single chip; and a cache controller, contained within at least one of said nodes, for controlling at least a section of the local memory unit as a cache memory, wherein at least a part of the local memory unit is used to locally store a copy of data residing in other local memories reachable via one of the master ports of the node.