Patent ID: 6404816
Filing Date: 2002-06-11
Classification: G06T,H04N

Abstract:
A video decoder, comprising:a variable length decoder(VLD) for decoding a received video bit stream in a form of a matrix to provide a matrix of discrete cosine transformation(DCT) coefficients and motion vectors; an inverse scanner for inverse scanning the matrix of DCT coefficients provided from the VLD; an inverse quantizer for inverse quantizing a signal from the inverse scanner; a transposter for transposing a matrix of signals from the inverse quantizer, the transposer including, a memory part, a mode signal detector for determining a matrix form of a signal from the inverse quantizer and providing a relevant mode signal, a write control circuit for writing the signals from the inverse quantizer on the memory part by any one unit either of a row unit or a column unit while shifting rows of the signals by the any one unit in sequence appropriately in response to the mode signal, a read control circuit for reading a matrix of signals written on the memory part by one unit different from the one unit in the writing either of the row unit or the column unit while shifting the matrix of signals by the one unit different from the one unit in the writing either of the row unit or the column unit in sequence, wherein the write control circuit writes the next signals from the inverse quantizer on a portion of the memory part emptied due to the shift in the reading by one unit identical to the one unit in the reading while shifting rows of the next signals by the one unit identical to the one unit in the reading in sequence; an inverse discrete cosine transformer(IDCT) for subjecting the transposed signals to inverse cosine transformation to provide spatial pixel values; a frame memory for storing a reference frame; a motion compensator for compensating the reference frame using the motion vector from the VLD; and, an adder for adding the signal from the motion compensator and the signal from the IDCT.