Patent ID: 7733149
Filing Date: 2010-06-08
Classification: H03K,H03L

Abstract:
1. A programmable delay element comprising: a buffer configured to receive a source signal at a first input of the delay element and to provide a first delayed replica of the source signal at a first output of the delay element; and a multiplexer having a first input coupled to the output of the buffer and a second input coupled to a second input of the delay element for receiving a second delayed replica of the source signal, the multiplexer comprising a plurality of current steering switches configured such that the state of each current steering switch is responsive to a corresponding portion of a control signal received at a control input of the multiplexer, and the multiplexer producing an output signal at a second output of the delay element, a first portion of said output signal being contributed by the first delayed replica and a second portion of said output signal being contributed by the second delayed replica, wherein the respective first and second portions are determined in accordance with the control input of the multiplexer.