Patent ID: 8791507
Filing Date: 2014-07-29
Classification: H01L

Abstract:
1. A semiconductor device having a layout structure, the layout structure comprising: a first cell placed at an end of a cell placement region, and having gate patterns extending in a first direction and arranged at a first pitch in a second direction perpendicular to the first direction, the gate patterns including at least two gate patterns placed on a diffusion layer; and a dummy pattern placed outside the cell placement region, and adjoining the first cell in the first direction, the dummy pattern being not a part of or not connected to a gate electrode of a transistor, wherein: the gate patterns of the first cell are terminated near a cell boundary with the dummy pattern, and terminal ends of the gate patterns are located at a same position in the first direction, and have a same width in the second direction, the dummy pattern has a pattern main body extending in the second direction, and at least two protruding portions protruding from the pattern main body toward the first cell in the first direction, the protruding portions form a plurality of opposing terminal ends placed near the cell boundary so as to face the terminal ends of the gate patterns of the first cell, respectively, and the opposing terminal ends are arranged at the first pitch in the second direction, are located at a same position in the first direction, and have a same width in the second direction.