Patent ID: 6133142
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising the steps of:forming a first dielectric layer on a substrate;forming a first patterned metal layer having gaps on the first dielectric layer, wherein the first patterned metal layer comprises a first metal feature having a composite structure comprising:a primary conductive portion with side surfaces and an upper surface having a first width; andan upper anti-reflective coating extending beyond at least one side surface of the primary conductive portion and having a second width greater than the first width;forming a second dielectric layer on the first patterned metal layer;etching the second dielectric layer to form a misaligned through-hole having an internal surface and exposing only a portion of an upper surface of the anti-reflective coating including a portion extending beyond a side surface of the primary conductive portion; andfilling the misaligned through-hole with conductive material to form a conductive via.