Patent ID: 7286000
Filing Date: 2007-10-23
Classification: H03K

Abstract:
1. A semiconductor device comprising: a plurality of first fuse units, each of which includes a fuse, and outputs a first fuse signal having a level determined in accordance with whether or not the fuse has been cut; a first decoder which receives the first fuse signals respectively output from the first fuse units, and decodes the received first fuse signals, thereby outputting a plurality of first control signals; a first delay which controls a timing of a predetermined first electric signal in response to the first control signals; a second decoder which receives the first fuse signals, and decodes the received first fuse signals, thereby outputting a plurality of second control signals; a second delay which controls a timing of a predetermined second electric signal in response to the second control signals; a plurality of second fuse units, each of which includes a fuse, and outputs a second fuse signal having a level determined in accordance with whether or not the fuse has been cut; and a third decoder which receives the second fuse signals respectively output from the second fuse units, and decodes the received second fuse signals, thereby outputting a plurality of third control signals, wherein each of the first delay and the second delay is determined to be enabled or disabled in response to a selected one of the third control signals.