Patent ID: 8520463
Filing Date: 2013-08-27
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising a memory macro including: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines, wherein a voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor, the voltage of the word lines is set at a first voltage if the threshold voltage of the n-channel transistor is lower than a predetermined voltage, at a second voltage if the threshold voltage of the n-channel transistor is higher than the predetermined voltage, and at the first or second voltage if the threshold voltage of the n-channel transistor is equal to the predetermined voltage, and the predetermined voltage increases with increase in the absolute value of the threshold voltage of the p-channel transistor linearly or in a curve.