Patent ID: 7143211
Filing Date: 2006-11-28
Classification: G06F

Abstract:
1. A processor arrangement comprising: a processor having a data port for reading and writing data; an input/output unit having a data port for reading and writing data; and a processor memory having a first and a second data port, wherein said processor data port is connected to said first processor memory data port and said input/output unit data port is connected to said second processor memory data port, wherein the processor memory is configured to have an input memory area and an output memory area, and wherein the processor arrangement is configured so that: writing data from said input/output unit is exclusively to the input memory area of said processor memory under exclusive address control of said input/output unit; reading data from said processor memory to said processor is exclusively from said input memory area of said processor memory under exclusive address control of said processor; wherein writing data from said processor is exclusively to said output memory area of said processor memory under exclusive address control of said processor; and wherein reading data from said processor memory to said input/output unit exclusively from said output memory area under exclusive address control of said input/output unit.