Patent ID: 8006144
Filing Date: 2011-08-23
Classification: G11C

Abstract:
1. A data processing apparatus comprising: (i) at least one memory; (ii) processing logic configured to perform data processing operations on data and configured to access said at least one memory; and (iii) memory testing logic configured to perform a transparent algorithm testing routine on said at least one memory, said data processing apparatus impeding said processing logic from accessing said at least one memory while said memory testing logic is performing said transparent algorithm testing routine; wherein (iv) said processing logic and said memory testing logic are configured to detect a system event, said memory testing logic being operable when performing said transparent algorithm testing routine to respond to detection of said system event by stopping said transparent algorithm testing routine and restoring said at least one memory to an initial state, said initial state being a state it was in immediately prior to commencement of said transparent algorithm testing routine, whereupon after restoring said at least one memory to said initial state said data processing apparatus is configured to allow said processing logic to access said at least one memory and to proceed to process said detected system event.