Patent ID: 8314480
Filing Date: 2012-11-20
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a bottom land pad array comprising inner terminals, middle terminals, and outer terminals; a first die containing a first integrated circuit device embedded in a first molding layer containing first conductive vias, the first integrated circuit device connected to first stud bumps which form the inner terminals, wherein the bottom of the inner terminals are not encapsulated by the first molding layer; a second die containing a second integrated circuit device embedded in a second molding layer containing second conductive vias, the second integrated circuit device connected to second stud bumps which are connected to the first conductive vias which form the middle terminals, wherein the bottom of the middle terminals are not encapsulated by the first molding layer; and a carrier frame connected to the second conductive vias, wherein the bottom of the carrier frame forms the outer terminals which are not encapsulated by the first molding layer and wherein the sides of the carrier frame are not encapsulated by the first molding layer or the second molding layer.