Patent ID: 6457094
Filing Date: 2002-09-24
Classification: G11C

Abstract:
A memory device comprising:at least one memory array, wherein each memory array is partitioned into N segments and each segment includes at least one bit line; N local I/O lines for each memory array, wherein one local I/O line is associated with each segment of the memory array, wherein each local I/O line operatively couples to zero or more of the at least one bit line based on at least one column select line, wherein each of the N local I/O lines associated with a particular memory array has a length that is a portion of a length of the memory array, and wherein the N local I/O lines associated with each memory array are arranged in a straight line and are positioned transverse to the at least one bit line in the memory array; and at least N write drivers, wherein each local I/O line is further associated with one write driver, and wherein each write driver the zero or more bit lines operatively coupled to the associated local I/O line, and wherein the memory device is operated in a double data rate (DDR) operation, wherein a block write operation is performed by writing to a first group of M bit lines during a first clock phase and to a second group of M bit lines during a second clock phase, and wherein the writing to the first group of M bit lines is initiated upon receiving masking information for the first group.