Patent ID: 6051458
Filing Date: 2000-04-18
Classification: H01L,Y10S

Abstract:
A method of forming a semiconductor device selected from memory and logic devices on a semiconductor substrate with an N-well and a P-well with P+ source/drain region sites in said N-well and N+ source/drain region sites in said P-well comprising the steps as follows:form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with an N-well with N type dopant and a P-well with P type dopant,form an N- lightly doped source (LDS) region at said source region site and an N- lightly doped drain (LDD) region at said drain region site in said P-well,form a P- LDS region and a P- LDD region in said N-well while forming a P- lightly doped halo region in said P-well below said N+ drain region site,form a counter doped halo region doped with N type dopant below said N+ source region site in said P-well to compensate P-type dopant previously formed by a source of dopant selected from the group comprising a P-halo dopant and said P-well dopant, where said counter doped halo region is formed,form spacers on said gate electrode sidewalls,thereafter form lightly doped regions self-aligned with said gate electrode in said source/drain region sites,form N+ type doped source/drain regions deeper than said N- LDS/LDD regions in said P-well in said N+ source/drain region sites, andform P+ type doped source/drain regions deeper than said P- LDS/LDD regions in said N-well in said P+ source/drain region sites.