Patent ID: 6594330
Filing Date: 2003-07-15
Classification: H03L

Abstract:
An integrated circuit (IC) having a phase-locked loop (PLL), the PLL comprising:(a) a phase detector (PD), configured to receive a PLL input signal and a PLL feedback signal and to generate PLL PD signals based on differences in phase between the PLL input and PLL feedback signals; (b) an accumulator/filter, configured to receive the PLL PD signals from the phase detector and to generate a digital control signal; and (c) a digitally controlled oscillator (DCO) comprising: (A) a DCO PD, configured to receive an oscillator clock signal and a DCO feedback signal and to generate DCO PD signals based on differences in phase between the oscillator clock and DCO feedback signals; (B) a charge pump (CP), configured to receive the DCO PD signals from the DCO PD and to generate a CP charge current; (C) a loop filter, configured to receive the CP charge current and to generate a loop-filter voltage control signal; (D) a voltage-controlled oscillator (VCO), configured to receive the loop-filter voltage control signal and to generate a PLL output signal based on the loop-filter control signal; (E) a dual-modulus divider, configured to receive the output signal and to generate the DCO feedback signal by applying one of two selected divisor values; and (F) a modulus controller, configured to receive the digital control signal from the accumulator/filter and to control which of the two selected divisors is applied by the dual-modulus divider, wherein: the accumulator/filter generates the digital control signal as a two-part digital control signal comprising an integer part INT and a fractional part FRAC; the two selected divisor values are based on the integer part INT; and the modulus controller controls how often the two selected divisor values are applied by the dual-modulus divider based on the value of FRAC.