Patent ID: 6020258
Filing Date: 2000-02-01
Classification: H01L,Y10S

Abstract:
A method of forming an integrated circuit comprising:providing a substrate covered by a layer of insulating material;providing a first level wiring line over the layer of insulating material, the first level wiring line having an upper surface and sidewalls;covering the upper surface and the sidewalls of the first level wiring line with an etch stop material;providing a dielectric layer over the first level wiring line;forming a first via through the dielectric layer to expose the etch stop material within the via, wherein the step of forming the first via includes a first etching process and a second etching process, wherein the first etching process has an etching rate higher than an etching rate of the second etching process;removing the etch stop material to expose the first level wiring line;providing a conductive plug within the first via; andproviding a second level wiring line in contact with the conductive plug.