Patent ID: 6646938
Filing Date: 2003-11-11
Classification: G11C

Abstract:
A static memory comprising:a memory cell array having a plurality of word lines, a plurality of bit line pairs, and memory cells, disposed at cross sections thereof, each having a pair of nodes which hold opposite levels; a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line pair, a plurality of self-timing dummy memory cells which are connected to the dummy word line and dummy bit line pair and have a pair of nodes holding opposite levels, and a plurality of load dummy memory cells connected to the dummy bit line pair, wherein said plurality of self-timing dummy memory cells drives the bit line together in response to a selection of dummy word line; and a timing control circuit for detecting a voltage change of the dummy bit line pair to generate a timing control signal, wherein one of the pair of nodes of the self-timing dummy memory cells are connected to a higher level so as to be fixed to a first status, and one of the pair of nodes of all of the load dummy memory cell are connected to a around level so as to be fixed to a second status opposite to the first status.