Patent ID: 8772146
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, comprising: forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, wherein the first gate pattern includes a first gate insulating layer and a silicon gate electrode; removing the dummy gate pattern to expose a surface of the substrate in the second active area; forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, wherein the first gate insulating layer has a thickness larger than a thickness of the second gate insulating layer; and forming a gate silicide on the silicon gate electrode after forming the second gate pattern, wherein the forming of the gate silicide comprises forming a mask pattern including a plurality of first contact holes and a second contact hole on the first gate pattern and the second gate pattern, and wherein the first contact holes are formed at opposing sides of the first gate pattern and the second gate pattern, and wherein the second contact hole is formed on the silicon gate electrode.