Patent ID: 8767531
Filing Date: 2014-07-01
Classification: H04L

Abstract:
1. A communications mechanism for communicating between digital data devices, comprising: a first plurality of parallel lines supporting a parallel communications link having N logical lanes for communicating data in a first direction from a first digital data device to a second digital data device, said first plurality of parallel lines comprising at least (N+1) lines; a calibration mechanism for periodically recalibrating lines of said first plurality of parallel lines; a switching mechanism coupled to said calibration mechanism for selectively enabling each line of said first plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said first plurality of parallel lines for calibration by said calibration mechanism while N lines of said first plurality of parallel lines not being calibrated are enabled for carrying functional data; a line fault detection mechanism for detecting a line fault in any of said first plurality of parallel lines; a line replacement mechanism coupled to said line fault detection mechanism and said switching mechanism, said line replacement mechanism responding to a detected line fault in a faulty line of said first plurality of parallel lines by causing said switching mechanism to disable the faulty line and enable previously calibrated lines of said first plurality of parallel lines other than the faulty line to carry functional data, said previously calibrated lines of said first plurality of parallel lines being calibrated prior to detection of the line fault a second plurality of parallel lines supporting a parallel link having P logical lanes for communicating data in a second direction from said second digital data device to said first digital data device, said second plurality of parallel lines comprising at least (P+1) lines; wherein said calibration mechanism is further for periodically recalibrating said second plurality of parallel lines; wherein said switching mechanism is further for selectively enabling each line of said second plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said second plurality of parallel lines for calibration by said calibration mechanism while P lines of said second plurality of parallel lines not being calibrated are enabled for carrying functional data; wherein said line fault detection mechanism is further for detecting a line fault in and of said second plurality of parallel lines; wherein said line replacement mechanism further responds to a detected line fault in a faulty line of said second plurality of parallel lines by causing said switching mechanism to disable the faulty line of said second plurality of parallel lines and enable previously calibrated lines of said second plurality of parallel lines other than the faulty line to carry functional data, said previously calibrated lines of said second plurality of parallel lines being calibrated prior to detection of the line fault.