Patent ID: 6163483
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A circuit for parallel programming nonvolatile memory cells having respective first terminals selectively connected together and to a common node and respective control terminals, the circuit comprising:a current mirror circuit having a first node and a second node, said second node being connected to said common node;an adjustable current generating circuit connected to said first node and having a control terminal; anda bias circuit including first negative feedback means and ramp generator means selectively activated; said first negative feedback means having a first input connected to said first node, a second input connected to said second node, and an output connected to said control terminals of said memory cells and forming a circuit output, and said ramp generator means connected to said control terminals of said memory cells; said bias circuit further comprises second negative feedback means having a first input, a second input, and an output; said first input of said second negative feedback means connected to said ramp generator means, said second input of said second negative feedback means connected to said control terminals of said memory cells, and said output of said second negative feedback means connected to said control terminal of said current generating circuit.