Patent ID: 6336178
Filing Date: 2002-01-01
Classification: G06F

Abstract:
A microprocessor comprising:a source of CISC-like instructions; a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including: a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, the code in an instruction class having a mutually-consistent definition of defined-usage bit-fields including a bit-field that is mapped using indirect specifiers so that a single mutually-uniform bit-length instruction code maps into a plurality of instruction versions, wherein the instruction classes include: a register operation (RegOp) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands, wherein the RegOp class further includes special register read and write operations and has defined-usage bit-fields including: an extension bit-field for specifying a condition code for a conditional move instruction and for specifying a special register to be read and written by the special register read and write operations.