Patent ID: 7301314
Filing Date: 2007-11-27
Classification: H02M,Y02B

Abstract:
1. A multi-phase buck converter comprising: a plurality of output switch arrangements each comprising a high side switch and a low side switch connected in series across a DC voltage and having a common connection coupled through a respective output inductor to a converter output node at which a converter output voltage is provided; a plurality of circuit arrangements providing pulse width modulated control signals to the high side and low side switches of each output switch arrangement for regulating the converter output voltage; a control arrangement providing a timing signal for controlling the start of conduction times of the high side and low side switches of each output switch arrangement and for providing an error signal related to a difference between the converter output voltage and a reference signal; a current sense arrangement coupled to each output inductor for providing a phase current signal related to the phase current provided by the respective output switch arrangement through the respective output inductor, there thus being provided a phase current signal for each output switch arrangement; and a circuit providing an average inductor current signal proportional to the average current through each output inductor, each current sense arrangement further comprising a current share adjusting circuit receiving the respective phase current signal and the average inductor current signal for producing a difference signal in accordance with the average inductor current signal and the respective phase current signal for the respective output switch arrangement, said difference signal adjusting the current through the respective output inductor to equalize the currents in each of the output inductors, wherein the circuit providing an average inductor current signal comprises a respective resistor coupling the phase current signal for each output switch arrangement to a common node, whereby the average inductor current signal is generated at said common node, the plurality of circuit arrangements each comprise a circuit for producing a ramp signal and a circuit comparing the ramp signal and said error signal and for producing said pulse width modulated control signals, and the current share adjusting circuit comprises an error amplifier for each output switch arrangement having as inputs said phase current signal for the respective output switch arrangement and said average inductor current signal, the error amplifier having an output coupled to a circuit for adjusting the slope of said ramp signal thereby to adjust the current in the respective output inductor.