Patent ID: 6636921
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A repeater circuit for providing buffered communications between a first bus having associated first bus signals and a second bus having associated second bus signals, the repeater circuit for use with a computing system providing a disable signal for disabling communications between the first and second buses, the repeater circuit comprising:a first bus to second bus driver circuit coupled to the first bus and the second bus for receiving the first bus signals and the disable signal and for providing first bus buffered signals to the second bus indicative of the first bus signals, wherein said first bus to second bus driver circuit is disabled when the disable signal is received; and a second bus to first bus driver circuit coupled to the first bus and the second bus for receiving the second bus signals and the disable signal and for providing second bus buffered signals to the first bus indicative of the second bus signals, wherein said second bus to first bus driver circuit is disabled when the disable signal is received, wherein the computing system further includes a bus device coupled to the first bus having a first address on the first bus and a second address on the second bus, the computing system capable of either providing first bus signals to the first bus indicative of the first address or second bus signals to the second bus indicative of the second address during an address phase of the first and second buses, wherein the repeater circuit further comprising: a bus phase detection circuit coupled to the first bus for detecting the address phase and for providing a phase signal indicative of the detection of the address phase, wherein the first bus to second bus driver circuit further includes a second bus address mapper for receiving the phase signal and an indication from the first bus of the frst address and for providing an indication of the second address to the second bus when the phase signal is received, and wherein the second bus to first bus driver circuit firther includes a first bus address mapper for receiving the phase signal and an indication from the second bus of the second address and for providing an indication of the first address to the first bus when the phase signal is received.