Patent ID: 7323406
Filing Date: 2008-01-29
Classification: H01L

Abstract:
1. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of: providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said top metal pads in recesses and planar with a first insulating layer on said substrate; forming a second insulating layer over said top metal pads and with openings to top surface of said top metal pads; forming elevated bond pads in said openings and extending above surface of said second insulating layer, with exposed sidewalls on said elevated bond pads; forming sidewall spacers on said exposed sidewalls; and forming an under-bump material barrier layer selectively on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu.