Patent ID: 6882688
Filing Date: 2005-04-19
Classification: H04N

Abstract:
1. A deblocking filter arithmetic apparatus comprising: first to eighth arithmetic blocks each for receiving, as inputs, simultaneously every two adjacent pixel data among a first to an eighth pixel data, for carrying out in parallel one of cycles of arithmetic processing comprising filter processing of first to eighth pixel data for removing block noises, every time two of the pixel data are input, and each for outputting filtered pixel data in parallel and corresponding to the first to the eighth pixel data and to which two of the pixel data are input simultaneously; an output selection circuit for selecting one outputs from the first to the eighth arithmetic blocks and for outputting the same; and a control circuit for controlling the arithmetic processing of each arithmetic block, in accordance with the cycles of the arithmetic processing, so that: the cycles of the arithmetic processing performed on each combination of arithmetic blocks up to the conclusion of the filter processing should be the same, among a combination of a first and second arithmetic block, a combination of a third and fourth arithmetic block, a combination of a fifth and sixth arithmetic block, and a combination of a seventh eighth arithmetic block, respectively, so that the filter processing of each combination of arithmetic blocks is concluded successively among the respective combinations, and said control circuit also for controlling said output selection circuit to select from the arithmetic blocks in for each combination of the arithmetic blocks and to perform a pipeline output.