Patent ID: 6144604
Filing Date: 2000-11-07
Classification: G11C

Abstract:
A read/write electronic memory bank, comprising a plurality of memory units, which receive a common clock signal having a repetitive clock cycle and have a common input port and a common output port, such that in each clock cycle an input word is written to the memory bank from the input port and an output word is read from the memory bank to the output port, each memory unit comprising:a) a single-port random-access memory (RAM) device; andb) a first-in first-out (FIFO) buffer, such that when the output word is to be read from the same memory unit to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port of the memory bank and the FIFO buffer, instead of between the respective port of the memory bank and the RAM device.