Patent ID: 6469941
Filing Date: 2002-10-22
Classification: G11C

Abstract:
A memory, comprising:a first bit line; a charge-storing element having a first plate and a second plate; an access device having a first end, a second end and a control terminal, the first end coupled to the first bit line, the second end coupled to the first plate of the charge-storing element and defining a node, and the control terminal coupled to a word line; a voltage driver circuit having a first terminal coupled to the second plate of the charge-storing element, and wherein the voltage driver circuit provides, a high logic level voltage to the second plate of the charge-storing element when a low logic level is present on a second bit line, a low logic level voltage to the second plate of the charge-storing element when a high logic level voltage is present on a second bit line, and substantially the same voltage as an intermediate voltage to the second plate of the charge-storing element when the intermediate voltage level is present on the second bit line.