Patent ID: 7157943
Filing Date: 2007-01-02
Classification: H02M

Abstract:
1. Circuitry, comprising: at least one first timing circuit including a first input, a first output, and a current source, the first input being electrically coupled to the first output, the first input being coupleable to at least one capacitor and at least one clamping element, wherein the current source is operative to apply a constant current to the capacitor, thereby generating a ramped timing signal at the first input and providing the ramped timing signal to the first output electrically coupled to the first input, and wherein the timing signal provided at the first output of the first timing circuit has an associated first state in the event only the capacitor is coupled between the first input and ground, and an associated second state in the event the clamping element is coupled between the first input and ground; and a second circuit operable in a plurality of modes having at least one control input and a second output, the control input being electrically coupled to the first output of the first timing circuit, wherein the second circuit is configured to operate in a first mode in the event the timing signal having the associated first state is provided to the control input via the first output, and to operate in a second mode in the event the timing signal having the associated second state is provided to the control input via the first output.