Patent ID: 8331178
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A memory device capable of operation in a burn in stress mode, the memory device comprising: M isolation word lines, wherein M is a positive integer multiple of 4; a plurality of active word lines; a plurality of bit lines; M first switches, wherein each first switch has a first terminal for receiving a low voltage, a second terminal for receiving a first control voltage, and a third terminal coupled to an isolation word line; and M second switches, wherein a (4n+1)th second switch has a first terminal for receiving a first stress voltage, a second terminal for receiving a second control voltage, and a third terminal coupled to a (4n+1)th isolation word line; a (4n+2)th second switch has a first terminal for receiving a second stress voltage, a second terminal for receiving the second control voltage, and a third terminal coupled to a (4n+2)th isolation word line; a (4n+3)th second switch has a first terminal for receiving the first stress voltage, a second terminal for receiving the second control voltage, and a third terminal coupled to a (4n+3)th isolation word line; and, a (4n+4)th second switch has a first terminal for receiving the second stress voltage, a second terminal for receiving the second control voltage, and a third terminal coupled to a (4n+4)th isolation word line; wherein n is a positive integer or zero, 4n≦M−4, and two active word lines are formed between each two consecutive isolation word lines, wherein the two active word lines and the plurality of bit lines are used for controlling a plurality of memory cells.