Patent ID: 7266630
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A CPU contained LSI comprising: a contained CPU; a first bus connected to the contained CPU; a second bus connected to an external CPU; and a bus adjusting circuit disposed between the first bus and the second bus to exclusively control accesses of the external CPU and the contained CPU to a device connected to the first bus; wherein the bus adjusting circuit is provided with an interrupt control circuit for informing of an interruption between the contained CPU and the external CPU; the interrupt control circuit includes an interrupt factor register having a plurality of bits in which the allocation and setting of bits of an interrupt factor are programmable and a circuit for outputting an interrupt signal; wherein, when a chip select signal and an address to access the device connected to the first bus from the external CPU are inputted during an access to the device connected to the first bus by the contained CPU, the bus adjusting circuit inputs the address to the first bus from the second bus by releasing a wait signal to permit the external CPU to access the device connected to the first bus and connecting the second bus to the first bus after stopping the access of the contained CPU to the first bus.