Patent ID: 6205083
Filing Date: 2001-03-20
Classification: G11C,H03K,H03L

Abstract:
A clock applying circuit for a synchronous memory comprising:(a) a clock input for receiving a clock input signal;(b) means connected to the synchronous memory for receiving a driving clock signal; and(c) a tapped delay line for receiving the clock input signal and for delivering said clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal, the delay line being comprised of a series of delay elements for carrying said clock input signal;(d) means for providing the driving clock signal from an output of one of the delay elements;(e) means for selecting an output from said one of the delay elements comprising a comparator for comparing the clock input signal with said driving clock signal and for selecting said output from said one of the delay elements based on a closest predetermined one of a rising or falling edge of a clock input signal following an enable time required at a particular enable terminal of the synchronous memory; and(f) means for providing the driving clock signal to said particular enable terminal.