Patent ID: 7091075
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit comprising: producing an n-well into an uppermost surface of a semiconducting substrate; doping a source dopant region, a drain dopant region, and a combination drain/source dopant region into the uppermost surface of the semiconducting substrate, the drain dopant region, the source dopant region, and the combination drain/source dopant region being lightly doped acceptor sites; doping a gate dopant region coupled to the drain dopant region, the gate dopant region having a higher concentration of acceptor sites than either of the dopant regions or the drain/source dopant region; depositing a floating gate region in proximity to the gate dopant region, the floating gate region configured as a floating programming gate; depositing silicon-germanium and silicon over the source dopant region and the drain dopant region to form epitaxial silicon-germanium/silicon regions, the silicon-germanium/silicon regions having a higher acceptor concentration than either of the dopant regions or the drain/source dopant region; fabricating a PMOS transistor from the source dopant region and the combination drain/source dopant region, the PMOS transistor configured to serve as a select transistor in a memory cell; fabricating a PMOS transistor from the drain dopant region, the gate dopant region, the combination drain/source dopant region, and the floating gate region, the PMOS transistor configured to serve as a memory transistor in the memory cell; and fabricating at least one bipolar device in the integrated circuit, the at least one bipolar device being in electrical communication with the select transistor and the memory transistor and having a breakdown voltage sufficient to withstand a programming voltage of the memory cell.