Patent ID: 6202139
Filing Date: 2001-03-13
Classification: G06F,G11C

Abstract:
A cache comprising:a plurality of ports operating, during use, at a first clock frequency, each of said plurality of ports configured to concurrently receive a different cache access according to a first clock signal having said first clock frequency; anda pipeline coupled to said plurality of ports, wherein said pipeline comprises a plurality of pipeline stages and is configured to select, into the pipeline, one cache access per clock cycle of a second clock signal having a second clock frequency, said second clock frequency being a multiple of said first clock frequency, the cache accesses selected in consecutive clock cycles of the second clock signal being selected from different ones of the plurality of ports, and wherein the multiple is greater than one, and wherein each of said plurality of pipeline stages is coupled to receive said second clock signal and is configured to operate responsive to the second clock signal.