Patent ID: 6165804
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A process for fabricating a capacitor in a semiconductor integrated circuit comprising:depositing a lower insulative layer over a portion of the integrated circuit having a buried contact;depositing a first conductive layer over the lower insulative layer;removing a portion of the first conductive layer to define a capacitor region having a top capacitor electrode comprising a remaining portion of the first conductive layer bounding the capacitor region;depositing a dielectric layer over the capacitor region;depositing a second conductive layer over the dielectric layer; forming a contact through the second conductive layer and the dielectric layer to form a bottom electrode within the capacitor region;removing a portion of the lower insulative layers, exposing the buried contact; anddepositing a third conductive layer over the capacitor region, thereby electrically connecting the buried contact to the bottom electrode.