Patent ID: 6216205
Filing Date: 2001-04-10
Classification: G06F

Abstract:
In a memory device containing a cache memory array, arranged as a plurality of registers of multiport memory cells, and a supplemental memory array, a method of operating the memory device as a first-in first-out memory buffer having a capacity greater than a capacity of the cache memory array, said method comprising the steps of;reading data from a current read register in the cache memory array;writing data to a current write register in the cache memory array;performing write arbitration to determine a next-to-write register as a first free register in the cache memory array if the current read and write registers are different registers; andperforming read arbitration to determine a next-to-read register as the current write register if the current write register contains next-to-read data relative to data in the current read register, or as a second free register in the cache memory array if the current read and write registers are different registers and the next-to-read register is not the current write register.