Patent ID: 6961821
Filing Date: 2005-11-01
Classification: G06F

Abstract:
1. A computer system comprising: a set associative cache memory; and a cache memory controller comprising a writable cache replacement control array, wherein guidelines used to rank states of cache lines for replacement can be dynamically changed by writing different data to said writable cache replacement control array, wherein said guidelines rank states of different cache lines within each set of cache lines independently of rankings within other sets of cache lines, wherein each set of cache lines comprises a cache line from each way of said set associative cache memory, wherein upon a cache miss within a set of cache lines, a cache line in said set of cache lines having a highest rank of said states is replaced before other cache lines in said set of cache lines having lower state rankings, and wherein said writable cache replacement control array encodes a mapping of cache line states to cache line replacement selection rankings.