Patent ID: 7863722
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor assembly, the method comprising: forming a first sidewall portion and a second sidewall portion in a mold material at a first side of a molded wafer in a lane between a first semiconductor die and a second semiconductor die embedded in the mold material, wherein the first and second sidewall portions are sidewalls of at least one trench in the mold material at the first side, and wherein the first die has a first bond-site at the first side and the second die has a second bond-site at the first side; electrically connecting the first bond-site with the first sidewall portion; electrically connecting the second bond-site with the second sidewall portion; forming at least one channel in a second side of the mold material opposite the first side at a portion overlapping the trench, wherein the channel is formed within a first footprint of the first die and within a second footprint of the second die; singulating the first and second dies; and stacking the first die on the second die, wherein the channel associated with the first die is at least approximately aligned with the channel associated with the second die.