Patent ID: 8698196
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A transient voltage suppressor (TVS) device comprising: a) an n-type semiconductor substrate; b) a first epitaxial layer of an n-type semiconductor material on the substrate; c) a buried layer of an n-type semiconductor material located within the first epitaxial layer; d) an implant layer of a p-type semiconductor material located within the first epitaxial layer below the buried layer, the implant layer extending laterally beyond the buried layer, an NPN junction being formed by the buried layer, implant layer, first epitaxial layer and substrate; e) a second epitaxial layer of a p-type semiconductor material supported on top of the first epitaxial layer; f) a set of trenches formed within the second epitaxial layer and the first epitaxial layer, each trench in the set being at least lined with a dielectric material, the set of trenches including a first trench at an edge of the buried layer and an edge of the implant layer, a second trench at another edge of the buried layer and extending into the implant layer, and a third trench at another edge of the implant layer, wherein the second trench is between the first and third trenches; and g) a set of source regions of an n-type semiconductor material formed within a top surface of the second epitaxial layer, the set of source regions including first and second source regions located between the first and second trenches, a third source region located between the second and third trenches and a fourth source region located such that the third trench is between the third and fourth source regions; and h) a pair of implant regions of a p-type semiconductor material formed in the second epitaxial layer, the pair of implant regions including a first implant region located between the first source region and the second source region, and a second implant region located between the third trench and the third source region adjacent a sidewall of the third trench, a vertical PN junction being formed by the buried layer, second epitaxial layer and first implant region, a lateral PN junction being formed by the third source region, second epitaxial layer and second implant region.