Patent ID: 8713491
Filing Date: 2014-04-29
Classification: G06F,Y02P

Abstract:
1. A method for pre-coloring IC layout data for a multiple patterning lithography process, comprising: generating a graphical IC layout file using a computing device, wherein the graphical IC layout file comprises a plurality of IC shapes comprising a plurality of word lines and a plurality of Y-control lines within an SRAM memory circuit, wherein the plurality of Y-control lines are oriented in parallel with the plurality of word lines; pre-coloring selective IC shapes using the computing device; operating a decomposition algorithm using the computing device, wherein the decomposition algorithm assigns two or more different colors to uncolored IC shapes, such that IC shapes assigned a same color are to be formed on a same mask of a multiple mask set used for the multiple patterning lithography process; wherein the pre-colored IC shapes are to be formed on a same mask independent of the two or more different colors assigned by the decomposition algorithm; wherein forming the pre-colored IC shapes on the same mask reduces processing variations between on-chip structures corresponding to the pre-colored IC shapes; and wherein pre-coloring one or more of the word lines and Y-control lines comprises placing a pre-coloring marker shape on the one or more of the plurality of word lines and Y-control lines, which indicates that the one or more of the plurality of word lines and Y-control lines are to be formed on the same mask.