Patent ID: 7363481
Filing Date: 2008-04-22
Classification: G06F

Abstract:
1. An information processing method realized in a system in which a processor including a plurality of central processing units and internal storage means, external storage means in which are stored a common code to be executed in common by the plurality of central processing units and an instruction code to be respectively executed by predetermined one of the central processing units, and host processing means are interconnected by a bus, the method characterized by comprising: a step of loading, by means of one of the central processing units, the common code and the instruction code defined to be executed by one of the central processing units, into the internal storage means from the external storage means in accordance with an instruction from the host processing means, and loading, by means of one of other central processing units, the instruction code defined to be executed by the one of other central processing units, into the internal storage means from the external storage means; and a step of executing the common code and the instruction code defined to be executed by the respective central processing units, which are loaded in the internal storage means, by means of the respective central processing units, wherein the common code, the instruction code loaded by the one of the central processing units, and the instruction code loaded by the one of the other central processing units share a common address space in the internal storage means.