Patent ID: 7420213
Filing Date: 2008-09-02
Classification: H01L

Abstract:
1. A thin film transistor array substrate, comprising: a substrate; a gate pattern on the substrate, the gate pattern including a gate electrode and a gate line connected to the gate electrode; a main gate insulating film formed of an organic material to cover the gate pattern; a semiconductor pattern overlapping the gate electrode such that the main gate insulating film is disposed between semiconductor pattern and the gate line; a source/drain pattern on the semiconductor pattern, the source/drain pattern including a data line crossing the gate line with the main gate insulating film therebetween, a source electrode and a drain electrode, wherein thesource electrode, the drain electrode and the semiconductor pattern define a thin film transistor disposed at the intersection between the gate line and the data line; a protective film having a contact hole at a portion of the drain electrode; a pixel electrode contacting the drain electrode through the contact hole; and a sub gate insulating pattern disposed between the gate pattern and the main gate insulating film overlapping the gate pattern, the sub gate insulating pattern including a ferroelectric material, wherein the sub gate insulating pattern is only on the gate pattern and contacts the gate pattern, and wherein a dielectric constant of the sub gate insulating pattern is greater than a dielectric constant of the main gate insulating film, wherein the sub gate insulating pattern includes any one of lead zirconate titanate, lead lanthanum titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth titanate, and strontium bismuth titanate niobate.