Patent ID: 8187965
Filing Date: 2012-05-29
Classification: H01L

Abstract:
1. A process for fabricating a semiconductor chip comprising: providing a semiconductor substrate, a dielectric layer over said semiconductor substrate, a copper layer over said semiconductor substrate and in said dielectric layer, wherein said copper layer has a top surface substantially coplanar with a top surface of said dielectric layer, and a separating layer over said semiconductor substrate, on said top surface of said dielectric layer and on said top surface of said copper layer, wherein an opening in said separating layer is over a contact point of said top surface of said copper layer, and said contact point is at a bottom of said opening, wherein said separating layer comprises a nitride; forming a titanium-containing layer over said contact point and said separating layer; forming a first gold layer on said titanium-containing layer; after said forming said first gold layer, forming a resist layer; after said forming said resist layer, electroplating a second gold layer with a thickness between 2 and 20 micrometers over said first gold layer; after said electroplating said second gold layer, removing said resist layer; and after said removing said resist layer, removing said titanium-containing layer not under said second gold layer.