Patent ID: 6277739
Filing Date: 2001-08-21
Classification: H01L

Abstract:
A method of fabricating a metal silicide layer, and an overlying barrier layer, on a conductive region in a semiconductor substrate, exposed at the bottom of a contact hole, comprising the steps of:providing said conductive region, in said semiconductor substrate;depositing an insulator layer;opening a contact hole in said insulator layer, exposing a portion of top surface of said conductive region, located at the bottom of said contact hole;implanting metal ions into a top portion of said conductive region, exposed at bottom of said contact hole, and into a top portion of said insulator layer;performing an anneal procedure in a nitrogen containing ambient to form said metal silicide layer on said conductive region, and to selectively form overlying, said barrier layer, on said metal silicide layer, with said barrier layer formed from said metal ions, and from nitrogen available in said nitrogen containing ambient, while said metal ions in said top portion of said insulator layer remain unreacted;forming a metal plug structure in said contact hole, overlying and contacting said barrier layer located on said metal silicide layer,removing said top portion of said insulator layer, comprised with said unreacted metal ions; andforming a metal interconnect structure, overlying and contacting top surface of said metal plug structure.