Patent ID: 6017796
Filing Date: 2000-01-25
Classification: H01L

Abstract:
A method for fabricating a flash EEPROM device, the method comprising the steps of:preparing a semiconductor substrate;forming a plurality of field oxide isolation layers at selected locations over the substrate to define at least one active region in the substrate;forming at least one gate structure within the active region, including a tunnel oxide layer, a first conductive layer over the tunnel oxide layer, a dielectric layer over the first conductive layer, a second conductive layer over the dielectric layer, and a topping layer over the second conductive layer;doping an impurity element into selected regions of the substrate so as to form at least one source region and at least one drain region beside the gate structure;forming a sidewall spacer on the sidewall of the gate structure;forming a metallization layer over the entire substrate;forming an insulating layer over the metallization layer;performing a selective removal process on the insulating layer in such a manner that the remaining part thereof covers the source region and the field oxide isolation layers neighboring the source region; andremoving all the part of the metallization layer that is uncovered by the remaining part of the insulating layer.