Patent ID: 6448636
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A multi-layered integrated semiconductor device comprising:first and second IC chips each having a plurality of wiring pads, the first and second IC chips being disposed substantially parallel to a plane and at least partially overlapping when viewed in a direction perpendicular to the plane, each of the plurality of wiring pads of the first IC chip at least partially overlapping with a corresponding one of the plurality of wiring pads of the second IC chip when viewed in the direction perpendicular to the plane; a first set of distributed monitoring pads formed on said first IC chip, said moitoring pads connected pairs; a second set of monitoring pads each formed on the second IC chip and at least partially overlapping with a corresponding one of said first monitoring pads when viewed in the direction perpendicular to the plane; and a multiplicity of external monitoring terminals each formed on said semiconductor device and connected to an associated one of said second monitoring pads, thereby allowing measurements of pad-to-pad resistances between corresponding monitoring pads of said first and second IC chips using an associated pair of said external monitoring terminals connected to said corresponding pads.