Patent ID: 8729643
Filing Date: 2014-05-20
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a first conductive gate level feature forming a gate electrode of a first transistor of a first transistor type; a second conductive gate level feature forming a gate electrode of a first transistor of a second transistor type; a third conductive gate level feature forming a gate electrode of a second transistor of the first transistor type; a fourth conductive gate level feature forming a gate electrode of a second transistor of the second transistor type, each of the gate electrodes of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type extending lengthwise in a parallel direction, the gate electrodes of the first transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned in the parallel direction, the gate electrodes of the second transistors of the first and second transistor types having respective lengthwise centerlines substantially aligned in the parallel direction, each of the first and second transistors of the first transistor type formed in part by a respective diffusion region of a first diffusion type, each of the first and second transistors of the second transistor type formed in part by a respective diffusion region of a second diffusion type, the diffusion regions of the first diffusion type collectively separated from the diffusion regions of the second diffusion type in the parallel direction by an inner non-diffusion region, a first conductive contacting structure connected to a portion of the first conductive gate level feature that extends over the inner non-diffusion region, the first conductive gate level feature electrically connected to the fourth conductive gate level feature through a first electrical connection that includes the first conductive contacting structure; and a second conductive contacting structure connected to a portion of the third conductive gate level feature that extends over the inner non-diffusion region, the second conductive contacting structure offset in the parallel direction from the first conductive contacting structure, the third conductive gate level feature electrically connected to the second conductive gate level feature through a second electrical connection that includes the second conductive contacting structure, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.