Patent ID: 7013442
Filing Date: 2006-03-14
Classification: G06F

Abstract:
1. A method of configuring a wiring layout in an integrated circuit, comprising: analyzing a signal path of the wiring layout, the signal path being between a source and a destination, the signal path having multiple branches and substantially parallel ground wires spaced from and on opposing sides of at least a portion of the signal path; for an upstream branch of the signal path, determining an upstream branch layout design that produces a loop resistance, a loop inductance, and a total capacitance between the signal path and the ground wires that create a selected time delay for signal propagation along the upstream branch; and for one or more downstream branches of the signal path connected to the upstream branch, determining respective downstream branch layout designs that produce respective loop resistances, loop inductances, and total capacitances between respective signal paths and respective ground wires in the one or more downstream branches that collectively create an impedance that substantially matches an impedance of the upstream branch.