Patent ID: 6737335
Filing Date: 2004-05-18
Classification: H01L,Y10S

Abstract:
A method of manufacturing a shallow trench isolation type semiconductor device, comprising the steps of:forming a gate insulating layer in a first region and in a second region of a silicon substrate, the gate insulating layer being greater in thickness in the first region, as compared to the thickness in the second region; providing an etch protection layer on the gate insulating layer; forming an etching mask pattern to expose first and second trench regions; etching the etch protection layer using the etching mask pattern; etching the gate insulating layer until the gate insulating layer in the second region is completely removed; removing the remaining gate insulating layer in the first region using an etchant wherein an etching selectivity of the substrate to the gate insulating layer is in the range of 1:1 to 3:1, to exposing the silicon substrate; and etching the exposed silicon substrate in the first region for a predetermined time to form a trench for device isolation.