Patent ID: 6184117
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method for reducing lateral silicide formation for a salicide process in an MOS manufacturing process, comprising steps of:a) providing a silicon substrate having thereon field oxide and gate oxide;b) overlying a polysilicon layer on the resulting silicon substrate;c) forming a capping layer on said polysilicon layer, said capping layer being formed of a material selected from a group consisting of silicon nitride (Si.sub.3 N.sub.4), phosphosilicate glass (PSG) and titanium nitride (TiN);d) removing portions of said polysilicon layer and said capping layer to form a gate structure with a residual capping layer thereon;e) forming a spacer structure beside said gate structure and said residual capping layer;f) removing said residual capping layer after said spacer structure is formed so that said spacer structure has a level higher than a top surface of said polysilicon layer; andg) performing said salicide process.