Patent ID: 6728813
Filing Date: 2004-04-27
Classification: G06F

Abstract:
A processor for an information processing equipment having an unit for executing calculation processes, comprising:a buffer which stores plural sets of write addresses for a system bus of said information processing equipment and plural data corresponding to said write addresses; a comparator for deciding whether write addresses in succession forming continuous write addresses exist in the write addresses stored in said buffer; a timer for measuring a predetermined time period after receipt of one access; and converting means for converting respective accesses corresponding to writing operations of the plural data, corresponding to said continuous write addresses, into fixed length burst transfer protocol which can be transmitted with a series of continuing data cycles following one address cycle, when said continuous write addresses are detected by said comparator, wherein said comparator determines whether said one access and a predetermined number of other accesses are continuous in the address thereof, when receiving said predetermined number of other accesses within said predetermined time period measured by said timer, and wherein said converting means outputs said accesses corresponding to write addresses stored in said buffer by converting said accesses into the fixed length burst transfer protocol when said one access and said predetermined number of other accesses are continuous in the address thereof.