Patent ID: 7894772
Filing Date: 2011-02-22
Classification: H03C,H03F,H03G

Abstract:
1. A limiter for minimizing an amount of phase change caused by input amplitude variations, comprising: a differential variable gain amplifier comprising a first amplifying section and a second amplifying section, the first amplifying section having a first amplifying device configured to receive a first portion of a differential signal having an amplitude component and a phase component and having a gain controlled by a first compensation capacitance and a first variable resistance, in which the first compensation capacitance minimizes an effect of parasitic capacitance in the first amplifying section and the first variable resistance adjusts a first gain portion in the first amplifying section, the second amplifying section having a second amplifying device configured to receive a second portion of the differential signal and having a gain controlled by the second compensation capacitor and a second variable resistance, in which the second compensation capacitance minimizes an effect of parasitic capacitance in the second amplifying section and the second variable resistance adjusts a second gain portion in the second amplifying section, wherein the amplitude component at an output of the differential variable gain amplifier remains substantially constant in response to a combined adjustment of the first gain portion and the second gain portion; wherein the first variable resistance comprises a first plurality of series-connected transistor devices and a first plurality of corresponding resistors, each transistor device of the first plurality of series-connected transistor devices having a gate terminal coupled to a first terminal of a corresponding resistor of a first plurality of corresponding resistors, a first portion of the gain of the differential variable gain amplifier adjustable through a control terminal coupled to a second terminal of each corresponding resistor; and wherein the second variable resistance comprises a second plurality of series-connected transistor devices and a second plurality of corresponding resistors, each transistor device of the second plurality of series-connected transistor devices having a gate terminal coupled to a first terminal of a corresponding resistor of the second plurality of corresponding resistors, a second portion of the gain of the differential variable gain amplifier adjustable through a control terminal coupled to a second terminal of each corresponding resistor.