Patent ID: 8749576
Filing Date: 2014-06-10
Classification: G06T

Abstract:
1. A processor comprising: a plurality of low fixed precision interpolators for computing a first set of pixel parameters for a geometric primitive; a plurality of high precision interpolators for computing a second set of pixel parameters for said geometric primitive, wherein said plurality of low fixed precision interpolators operate simultaneously with said plurality of high precision interpolators and wherein said plurality of high precision interpolators operate at a first power consumption level and said plurality of low fixed precision interpolators operates at a second power consumption level, wherein said first power consumption level is greater than said second power consumption level; a programmable scheduler for scheduling parallel execution of high precision interpolation computations and low fixed precision interpolation computations on said plurality of high precision interpolators and said low fixed precision interpolators, wherein said scheduling is operable to be based on assigning low fixed precision interpolation computations to said low fixed precision interpolators; and an output mechanism coupled to said low fixed precision interpolators and said high precision interpolators for outputting said first set of pixel parameters and said second set of pixel parameters, wherein said low fixed precision interpolators and said high precision interpolators both utilize Barycentric coordinate values for interpolation.