Patent ID: 7508714
Filing Date: 2009-03-24
Classification: G11C

Abstract:
1. An integrated circuit comprising: a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof; wherein each respective NAND string within a given memory block of a given memory plane is coupled to a respective global bit line that is not shared by other NAND strings within the given memory block of the given memory plane, and wherein some adjacent NAND strings within a memory block are coupled at opposite ends thereof to their respective global bit lines; wherein half of said NAND strings within the given memory block are each coupled at one end thereof to its respective global bit line, and the other half of said NAND strings within the given memory block are each coupled at the other end thereof to its respective global bit line; wherein each NAND string of a first group of M adjacent NAND strings within the given memory block is coupled at one end thereof to its respective global bit line, and each NAND string of an adjacent second group of M adjacent NAND strings within the given memory block is coupled at the other end thereof to its respective global bit line; and wherein a respective NAND string within the first group of M adjacent NAND strings is adjacent to a respective NAND string within the second group of M adjacent NAND strings, and are coupled at opposite ends thereof to their respective global bit lines.