Patent ID: 7106635
Filing Date: 2006-09-12
Classification: G11C

Abstract:
1. The A boosted memory array comprising: at least one bitline; at least one memory cell coupled to said bitline; a bitline booster circuit coupled to said bitline; a bitline booster circuit bitline boost enable signal input terminal coupled to said bitline booster circuit; a bitline boost enable signal coupled to said bitline booster circuit bitline boost enable signal input terminal, wherein; said bitline booster circuit comprises: a first NOR gate, a first input of said first NOR gate being coupled to said first bitline and a second input of said first NOR gate being coupled to said bitline boost enable signal; a first transistor, an output of said first NOR gate being coupled to a control electrode of said first transistor, a first flow electrode of said first transistor being coupled said first bitline, a second flow electrode of said first transistor being coupled to a supply voltage; a second NOR gate, a second input of said second NOR gate being coupled to said second bitline and a second input of said second NOR gate being coupled to said bitline boost enable signal; and a second transistor, an output of said second NOR gate being coupled to a control electrode of said second transistor, a first flow electrode of said second transistor being coupled said second bitline, a second flow electrode of said second transistor being coupled to said supply voltage.