Patent ID: 6307795
Filing Date: 2001-10-23
Classification: G11C

Abstract:
A memory device comprising:a first bank of memory cells arranged in rows and columns;a plurality of row lines for accessing memory cells in respective rows of said first bank based on a row address, said plurality of row lines being divided into a plurality of row blocks, each row block containing a respective plurality of row lines;a plurality of row decoders respectively coupled to said blocks of row lines for selectively activating an addressed row line;a plurality of column lines, each of said plurality of column lines being used to access memory cells in a respective column of said first bank;at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells; andat least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells, at least some of said segments of said at least one second redundant column having boundaries that are offset from boundaries of said segments of said at least one first redundant column.