Patent ID: 7733681
Filing Date: 2010-06-08
Classification: G11C

Abstract:
1. A memory comprising: a memory cell array including a plurality of subarrays; a word line arranged on the memory cell array; a main bit line arranged to intersect with the word line; a sub bit line arranged on each of the subarrays and configured to be connectable to the main bit line; a storage portion connected between the word line and the sub bit line; and a first transistor having a gate connected to the sub bit line, a first source/drain region connected to the main bit line and configured to control a potential of the main bit line during a read operation based on a potential of the sub bit line, and a second source/drain region configured to be connected to a reference higher than ground fixed voltage to maintain the first transistor in an OFF-state during a write operation to the storage portion.