Patent ID: 6321185
Filing Date: 2001-11-20
Classification: G06F

Abstract:
An estimation system of LSI power consumption, at which estimates the power consumption of a new LSI chip, comprising:an I/O part estimating section which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip;a data base of the ratio of each function which stores the ratio of the number of FF (flip-flop)/gates and the ratio of clock power/logic power;a modifiable circuitry part estimating section which calculates the ratio of the number of FF/gates and the ratio of clock power/logic power referring to said data base of the ratio of each function from the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates modifiable circuitry part power summing up the clock system power and the logic system power; andan LSI chip power calculating section which calculates the power of the new designing LSI chip summing up the I/O part power calculated at said I/O part estimating section and the modifiable circuitry part power calculated at said modifiable circuitry part estimating section.