Patent ID: 7888802
Filing Date: 2011-02-15
Classification: H01L

Abstract:
1. A bonding pad of a semiconductor device, comprising: a substrate; an interlayer insulation layer disposed on the substrate; an upper layer of wiring disposed on the interlayer insulation layer; and a plurality of lower layers of wiring juxtaposed one above the other in the interlayer insulation layer between the upper layer of wiring and the substrate, the lower layers of wiring being electrically conductively connected to the upper layer of wiring at a bottom surface of the upper layer of wiring that faces toward the substrate, and wherein the respective areas occupied by the lower layers of wiring sequentially increase in the interlayer insulation layer in a downward direction from the upper layer of wiring towards the substrate, and each of the lower layers of wiring projects further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.