Patent ID: 9117766
Filing Date: 2015-08-25
Classification: H01L

Abstract:
1. A method for forming an integrated circuit, comprising: forming a first plurality of mandrels on a first level over a substrate; forming a first plurality of mask lines along sidewalls of the first plurality of mandrels; forming a second plurality of mandrels on a second level over the first level; forming a second plurality of mask lines along sidewalls of the second plurality of mandrels, the second plurality of mask lines elongated generally parallel to the first plurality of the first and second pluralities of mask lines; selectively removing, relative to the mask lines, portions of exposed material on the first and second levels to form a pattern defined by mask lines of the first and the second pluralities of mask lines; transferring the pattern to an underlying material, wherein transferring the pattern to the underlying material comprises transferring the pattern to an amorphous carbon layer; and subsequently transferring the pattern to the substrate.