Patent ID: 6777804
Filing Date: 2004-08-17
Classification: H01L,H05K

Abstract:
A flip-chip package substrate, on which a chip shaped as a rectangle is suited to be disposed and to which the chip is suited to be electrically connected, the chip comprising two first opposite sides opposite to each other, two second opposite sides opposite to each other, a first centerline, and a second centerline, the first centerline perpendicularly and evenly dividing the first two opposite sides, the second centerline perpendicularly and evenly dividing the second two opposite sides, the substrate comprising:a plurality of electrically conductive layers sequentially stacked with each other; a plurality of isolation layers disposed between two neighboring layers of the electrically conductive layers respectively to electrically isolate the electrically conductive layers; and a plurality of via-hole traces penetrating at least one layer of the isolation layers to electrically connect at least two layers of the electrically conductive layers, wherein the substrate comprises a first surface and a corresponding second surface, the chip is adapted to be disposed on the first surface of the substrate, the substrate further comprises a core connection-pad layout region and a peripheral connection-pad layout region, both of them are disposed on the second surface of the substrate, the peripheral connection-pad layout region surrounds the core connection-pad layout region, and the peripheral connection-pad layout region comprises a first centerline neighboring region, a second centerline neighboring region, a third centerline neighboring region and a fourth centerline neighboring region, the first centerline neighboring region and the second centerline neighboring region are disposed on the substrate at two opposite sides of the chip, the third centerline neighboring region and the fourth centerline neighboring region are disposed on the substrate at the other two opposite sides of the chip, the first centerline traverses the first centerline neighboring region and the second centerline neighboring region, the second centerline traverses the third centerline neighboring region and the fourth centerline neighboring region, the second surface of the substrate comprises a plurality of common padable areas, a plurality of first central padable areas, a plurality of second central padable areas, a plurality of third central padable areas and a plurality of fourth central padable areas, part of the common padable areas are disposed in the core connection-pad layout region, the other part of the common padable areas are disposed in the peripheral connection-pad layout region and far away from the first centerline and the second centerline, the first central padable areas are disposed in the first centerline neighboring region, the second central padable areas are disposed in the second centerline neighboring region, the third central padable areas are disposed in the third centerline neighboring region, and the fourth central padable areas are disposed in the fourth centerline neighboring region, within the first centerline neighboring region, at both sides of the first centerline is respectively lined with the first central padable areas in three rows, the first central padable areas in each row are lined in parallel to the first centerline, the first centerline traverses between the first central padable areas arranged in two neighboring rows, and the ratio of the number of the first central padable areas with the connection pads for transmitting signals to the total number of the first central padable areas is either equal to or less than {fraction (2/7)}.