Patent ID: 9197198
Filing Date: 2015-11-24
Classification: H03K

Abstract:
1. A circuit comprising: a first transistor having a control terminal, a first terminal and a second terminal; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the first transistor is coupled to the first terminal of the second transistor; a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter, wherein a bias terminal of the first inverter is coupled to the second terminal of the first transistor and a bias terminal of the second inverter is coupled to the second terminal of the second transistor, the first inverter comprising: a third transistor having a control terminal, a first terminal, and a second terminal; a fourth transistor having a control terminal, a first terminal, and a second terminal; and a first capacitor coupled between the control terminal of the third transistor and the control terminal of the fourth transistor; the second inverter comprising: a fifth transistor having a control terminal, a first terminal, and a second terminal; a sixth transistor having a control terminal, a first terminal, and a second terminal; and a second capacitor coupled between the control terminal of the fifth transistor and the control terminal of the sixth transistor; and a precharge circuit coupled to the control terminal of the third transistor and the control terminal of the fifth transistor to produce a first reference voltage to the control terminal of the third transistor and the control terminal of the fifth transistor when the first and second inverters are disabled, wherein a voltage on the control terminal of the third transistor is less than a voltage on the control terminal of the fourth transistor and a voltage on the control terminal of the fifth transistor is less than a voltage on the control terminal of the sixth transistor when the first and second inverters are disabled.