Patent ID: 6746915
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A DRAM transistor structure comprising:a semiconductor substrate of a first conductivity type; a shallow-trench-isolation (STI) structure having an active region sandwiched by two parallel STI regions being formed over said semiconductor substrate; a transistor-stack being formed transversely across a portion of said active region and said two parallel STI regions, wherein said transistor-stack comprises a second masking dielectric layer over a capping-oxide layer being formed on an elongated second conductive layer with said elongated second conductive layer being formed on a first conductive layer over a gate-dielectric layer in said active region and over two first raised field-oxide layers in said two parallel STI regions; a common-drain region being located in a side portion of said transistor-stack comprising: a first sidewall dielectric spacer being formed over a sidewall of said transistor-stack and on a portion of a second flat bed being formed by two third raised field-oxide layers in said two parallel STI regions and a common-drain diffusion region of a second conductivity type in said active region, and a planarized third conductive island being formed on said common-drain diffusion region outside of said first sidewall dielectric spacer and between two second planarized dielectric layers being formed over said two third raised field-oxide layers in said two parallel STI regions; a common-source region being located in another side portion of said transistor-stack comprising: two source regions and one isolation region being located between said two source regions, wherein said isolation region comprises a self-aligned shallow trench in said semiconductor substrate to electrically isolate said two source regions with a first planarized dielectric layer being formed over said self-aligned shallow trench in said active region and on said two third raised field-oxide layers in said two parallel STI regions; and each of said two source regions being formed near said transistor-stack comprising said first sidewall dielectric spacer being formed over another sidewall of said transistor-stack and on a portion of a first flat bed being formed by a source diffusion region of said second conductivity type in said active region and said two third raised field-oxide layers in said two parallel STI regions, a thin third conductive island being formed on said source diffusion region between said first sidewall dielectric spacer and said first planarized dielectric layer, and a second sidewall dielectric-spacer island being formed on said thin third conductive island in said active region and between said two second planarized dielectric layers in said two parallel STI regions.