Patent ID: 6683502
Filing Date: 2004-01-27
Classification: H03L

Abstract:
A phase locked loop configured to receive a reference signal and to generate a PLL output clock signal, the phase locked loop comprising:a phase and frequency comparator coupled to receive the reference clock signal and a feedback clock signal; a charge pump coupled to the phase and frequency comparator; a voltage controlled oscillator coupled to the charge pump and coupled to generate the PLL output clock signal; a clock divider coupled to the voltage controlled oscillator and the phase and frequency comparator; and a PLL process variation compensation unit coupled to control a center frequency and a gain of the voltage controlled oscillator, wherein the PLL process variation compensation unit is operably configured to control the center frequency by: setting a divisor of the clock divider to a first value; and adjusting a bias signal of a voltage to current converter until frequency of the feedback clock signal is approximately equal to frequency of the reference clock signal.