Patent ID: 8762127
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. A processor comprising: a decoder to decode instructions of a source instruction set architecture (ISA); a pipeline including a plurality of units to execute instructions; a breakpoint cache including a plurality of entries each to store an emulation indicator to indicate if at least one of a set of instructions stored in an instruction storage corresponding to the entry is associated with translated code stored in a translation cache; a map cache including a plurality of entries each to store a mapping between a location of the source ISA instruction and a location for translated code stored in the translation cache for the source ISA instruction; and logic coupled to the breakpoint cache and the map cache to determine whether to cause a jump of control from a direct execution mode to an emulation execution mode based on at least one of a corresponding emulation indicator in the breakpoint cache and a mapping in the map cache.