Patent ID: 7266579
Filing Date: 2007-09-04
Classification: G06F

Abstract:
1. A parallel multiplier hardware architecture that delivers both a polynomial multiplication product with coefficients over GF(2) and a natural multiplication product, the multiplier architecture comprising: an array of AND gates with inputs connected to operand bits and with outputs providing a complete set of partial products of the operand bits, each partial product characterized by a bit significance or “weight”; an addition architecture arranged to add partial products of the same weight, the addition architecture constructed in multiple stages, a first group of stages arranged to add partial products without receiving any carry inputs from a lower weight portion of the addition architecture, a second group of stages arranged to add carry inputs from a lower weight portion of the addition architecture to results from previous stages, the stages in both groups providing carry outputs to a higher weight portion of the addition architecture; and means connected between the first and second groups of stages for extracting the first stage addition result as a polynomial multiplication product, the natural multiplication product being extracted from the end of the second group of stages.