Patent ID: 6627962
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A semiconductor memory, in which there is provided an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with said first conductive type, in which there is provided a floating gate electrode formed on said semiconductor substrate via a gate insulator, and in which there is provided a control gate electrode formed on said floating gate electrode via an interelectrode insulating film, comprising:said gate insulator provided n the surface of the semiconductor substrate other than said impurity diffusion region; a third insulating film with fi m thickness thicker than said gate insulator on the surface of said impurity diffusion region; an said floating gate electrode extended to a surface of a side wall of said third insulating film, wherein an interface between said gate insulator and said semiconductor substrate is substantially coplanar with an interface between said third insulating film and said impurity diffusion region.