Patent ID: 7166512
Filing Date: 2007-01-23
Classification: H01L

Abstract:
1. A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a plurality of first memory units an the substrate, wherein every two adjoining first memory units are separated from each other by a gap, and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially stacked on the substrate and the first composite layer comprises a first bottom dielectric layer, a first charge-trapping layer and a first top dielectric layer; forming a plurality of insulating spacers on the sidewalls of the first memory units; forming a second composite layer over the substrate, wherein the second composite layer comprises a second bottom dielectric layer, a second charge-trapping layer and a second top dielectric layer; forming a doped polysilicon layer over the substrate, wherein the doped polysilicon layer fills the gaps between various first memory units; removing a portion of the doped polysilicon layer so that the top surface of the doped polysilicon layer is at least lower than the top surface of the cap layer to form a plurality of trenches between the first memory units; forming a metallic layer over the substrate to fill the trenches; removing a portion of the metallic layer until the second composite layer is exposed, wherein the metallic layer together with the doped polysilicon layer form a plurality of second gates, the second gates together with the second composite layer form a plurality of second memory units, and the second memory units together with the first memory units constitute a memory cell column; and forming a source region and a drain region in the substrate on the two sides of the memory cell column.