Patent ID: 8823129
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. An integrated circuit, comprising: an input and/or output pad; a HVNW control circuit electrically coupled to a first voltage supply; a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and to the HVNW control circuit through an N+ in the floating HVNW; a low-voltage n-well (LVNW) connected to a second voltage supply through an N+ in the LVNW, a voltage level of the second voltage supply is lower than that of the first voltage supply; and a guard-ring HVNW disposed between the floating HVNW and the LVNW and electrically coupled to the HVNW control circuit, the HVNW control circuit being configured to control the guard-ring HVNW's voltage level.