Patent ID: 6345067
Filing Date: 2002-02-05
Classification: H04B,H04L

Abstract:
A clock regenerating circuit in direct spread spectrum communication system for regenerating a sampling clock signal for sampling a spread signal which is directly spread with a spread code so that a predetermined number of samples are sampled per one chip, including:means for dividing a frequency of the sampling clock signal to output a variable clock signal responsive to a control signal and having a different frequency from a clock which is in synchronization with a demodulation and correlation synchronizing pulse; a plurality of comparators, each providing a comparison result from comparing at least one predetermined threshold value with one of an associated plurality of differently delayed correlation signals obtained by conducting a correlation processing of said spread signal which is sampled according to said sampling clock signal; a window control unit for controlling presentation of the plurality of differently delayed correlation signals to the associated plurality of comparators; means for forming an advance/lag control signal by determining whether a timing of said sampled spread signal is advanced or lagged based upon each of the comparison results of said plurality of comparators, wherein the variable clock signal is output by using an advance and lag control signal from said advance/lag control signal forming means as a control signal for said sampling clock signal frequency dividing means; a plurality of adders each having a variable overflow value; and time window presetting means for presetting a time window for each output of said plurality of comparators responsive to at least one output of said plurality of adders, wherein said at least one predetermined threshold value in each of said plurality of comparators, said variable overflow value, and the time window in said time window presetting means are each separately variable.