Patent ID: 8154003
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A memory cell for use in an integrated circuit device, the memory cell comprising: a first electrode; a variable resistive material layer coupled to the first electrode; a first metal oxide layer coupled the variable resistive material layer; a second metal oxide layer formed on the first metal oxide layer, wherein the first metal oxide layer includes an interface with the variable resistive material layer, wherein the first metal oxide layer and the second metal oxide layer together form a constant resistance layer, the constant resistance layer providing the resistance of a current flowing from the first electrode is approximately equivalent to the resistance of a current flowing towards the first electrode; and a second electrode on the second metal oxide layer, wherein the second electrode includes an interface with the second metal oxide layer, wherein the second electrode includes a first metal, and wherein the second metal oxide layer includes an oxidized form of the first metal.