Patent ID: 6849549
Filing Date: 2005-02-01
Classification: H01L,Y10S

Abstract:
1. A method for forming a damascene structure to improve a chemical mechanical polishing (CMP) process while reducing the capacitance in an integrated circuit comprising the steps of: providing a semiconductor substrate comprising a dielectric insulating layer including a first damascene opening; blanket depositing a first resist layer to fill the first damascene opening and patterning the first resist layer to form an etching mask for etching a dummy damascene opening adjacent the first damascene opening; etching the dummy damascene opening into a thickness portion of the dielectric insulating layer; blanket depositing a bottom anti-reflective coating (BARC) layer to include filling the dummy damascene opening; forming a second damascene opening through a thickness portion of the dielectric insulating layer to at least partially encompass the first damascene opening; removing the BARC layer to exposed the dummy damascene opening; forming a metal layer to include filling the first and second damascene openings and the dummy damascene opening; and, planarizing the metal layer according to a CMP process to include removing a portion of the dielectric insulating layer greater than the dummy damascene opening depth to remove the dummy damascene.