Patent ID: 6204712
Filing Date: 2001-03-20
Classification: G06F,H05K

Abstract:
A method of minimizing clock uncertainty in a digital circuit, comprising a multi-line clock driver and a plurality of clocked circuits, linked to said clock driver with conductance traces of a printed circuit board, said method comprising:providing a multi-line clock driver sourced from a single clock and a single driver providing a plurality of same-frequency outputs;linking said plurality of same-frequency outputs of said multi-line clock driver together onto a common metal island of the printed circuit board;laying out a plurality of wide, relatively high-capacitance traces on the printed circuit board, each leading from said metal island to a respective one of the plurality of clocked circuits, and matched in length to within 20 mils;routing all of said plurality of wide traces on a single signal layer of the printed circuit board; andterminating all of said plurality of wide traces in the same manner.