Patent ID: 6301599
Filing Date: 2001-10-09
Classification: G06F

Abstract:
A multiplier circuit comprising:an encoder circuit which encodes a plurality of multiplier bits, wherein the encoder is comprised of:a first set of inverters for inverting the plurality of multiplier bits;a first set of pass gates coupled to the inverters, wherein the pass gates include an NPN transistor having a base coupled to an output of a first inverter and a PNP transistor having a base coupled to an input of the first inverter, said first set of pass gates accepting as inputs both inverted multiplier bits and non-inverted multiplier bits;a plurality of NAND gates coupled to the pass gates, wherein outputs from the first set of pass gates are input to the plurality of NAND gates, wherein the NAND gates output a plurality of control signals;a selector circuit coupled to the encoder circuit, wherein the selector circuit is comprised of:a second set of inverters which are coupled to receive some of the plurality of control signals generated by the encoder circuit;a second set of pass gates coupled to receive signals output from the inverters, wherein the second set of pass gates are coupled to receive bits corresponding to multiplicand operations and one of the bits corresponding to the multiplicand operations is selected for output by the selector circuit according to the plurality of control signals generated by the encoder circuit, the second set of pass gates comprising a first transistor having a base coupled to an output of a second inverter and a second transistor having a base coupled to an input of the second inverter;an output inverter coupled to the second set of pass gates which outputs a signal corresponding to a Booth encoder/selector.