Patent ID: 6550044
Filing Date: 2003-04-15
Classification: G06F

Abstract:
A method of synthesizing a clock tree for an integrated circuit design comprising the steps of:(a) constructing an initial balanced clock tree for an integrated circuit design; (b) calculating a clock arrival time for each clock driven cell in the initial clock tree; (c) performing a timing analysis from the clock arrival time calculated for each corresponding clock driven cell; (d) if a signal path having a first hold time violation is detected by the timing analysis, then inserting a first buffer to delay the clock arrival time at the corresponding clock driven cell by a first selected delay time to correct the first hold time violation; and (e) if a second hold time violation is introduced in a second signal path by the insertion of the first buffer, then inserting a second buffer in the second signal path to delay a signal arrival time by a second selected delay time to correct the second hold time violation.