Patent ID: 9196505
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate, the semiconductor substrate having an active surface at which an integrated circuit is formed and a backside surface opposite the active surface; forming an interlayer dielectric layer on the active surface; forming a lower organic insulation layer on the backside surface, the lower organic insulation layer having at least one first opening; forming a first seed layer on the lower organic insulation layer and within the at least one first opening; electroplating the semiconductor substrate to form a first conductive layer on the first seed layer and within the at least one first opening; forming an upper organic insulation layer on the interlayer dielectric layer on the active surface, the upper organic insulation layer having at least one second opening, wherein the at least one second opening exposes the interlayer dielectric layer; planarizing the first conductive layer to remove at least a portion of the first seed layer and at least a portion of the first conductive layer on the lower organic insulation layer, wherein a portion of the first conductive layer that remains in the at least one first opening after planarizing forms at least one of a first chip pad and a first wiring; after the above forming, electroplating, and planarizing steps, forming a second seed layer on the upper organic insulation layer and within the at least one second opening, wherein the second seed layer conformally covers bottom and side surfaces of the at least one second opening; forming a second conductive on the second seed layer and within the at least one second opening, and planarizing a portion of the second seed layer and a portion of the second conductive layer.