Patent ID: 6562732
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising a dual damascene structure (20) which comprises a metal layer (1), a first dielectric layer (2) provided with a via (3), a second dielectric layer (5) disposed on said first dielectric layer (2) and provided with an interconnect groove (6), and a metal in via (3) and interconnect groove (6) which forms a metal line (9) having an upper side (10), wherein the method further comprises the steps:removing the second dielectric layer (5), providing a disposable layer (12) on the first dielectric layer (2) and the metal line (9), planarizing the disposable layer (12) down to the upper side (10) of the metal line (9) providing a porous dielectric layer (13) on the disposable layer (12), and removing the disposable layer (12) through the porous dielectric layer (13) so as to form air gaps (14).