Patent ID: 6486059
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A dual damascene process comprising the steps of:providing a semiconductor substrate having at least a dual damascene opening, wherein the dual damascene opening has a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer; forming an oxide liner on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer; performing a degas step; after performing the degas step, forming a metal barrier layer conformally to cover the sidewall and bottom of the dual damascene opening and the surface of the second low-k dielectric layer; filling the dual damascene opening with a conductive layer; and removing the excess conductive layer outside the trench level, wherein the remaining part of the conductive layer serves as a dual damascene structure.