Patent ID: 6396101
Filing Date: 2002-05-28
Classification: H01L

Abstract:
An electronic device comprising an EEPROM cell, including a selection transistor and a memory transistor, formed in and on a substrate with a first conductivity type; said memory transistor having a cell structure forming a control gate region and a floating gate region, a first conductive region formed in said substrate of semiconductor material with a second conductivity type on a first side of said cell structure, said first conductive region being overlaid by a silicide region;said selection transistor comprising a selection gate region, a second and a third conductive region with said second conductivity type formed in said substrate, said third conductive region being arranged on a second side of said cell structure of said memory transistor; said first and third conductive regions are offset with respect to said floating gate region of said memory transistor wherein said second and third conductive regions are not overlaid by the silicide region.