Patent ID: 8365132
Filing Date: 2013-01-29
Classification: G06F

Abstract:
1. A computer-implemented method for debugging the power aspect of an IC design specified in a power specification format by displaying a power map that integrates the power specification and its corresponding circuit design, the method comprising he steps of: a. generating a knowledge data base from the circuit design; b. generating a power data base according to the power specification and the knowledge data base; c. generating and displaying the power map by using the power data base, wherein the power map comprises a plurality of power domains and each of the plurality of power domains is associated with the part of the circuit design that belongs to the power domain, wherein the power map is generated and displayed by using a computer; and d. checking and displaying the mismatches or errors according to the power specification and the circuit design for those signals connecting the power domains, comprising the sub-steps of: