Patent ID: 6317333
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A semiconductor device comprising:a ball grid array (BGA) substrate including an upper insulating layer comprising a plurality of laminated layers, an intermediate insulating layer, and a lower insulating layer comprising a plurality of laminated insulating layers;a plurality of lines on top surfaces of the insulating layers included in each of the upper, intermediate, and lower layers, respectively;a plurality of solder balls disposed on an outermost surface of the lower insulating layer; anda semiconductor chip having a plurality of electrodes connected to respective lines, the semiconductor chip being connected electrically to the plurality of solder balls through a plurality of via holes in each of the upper, lower, and intermediate insulating layers wherein the intermediate insulating layer is a material having thermal expansion characteristics substantially matching thermal expansion characteristics of a circuit board, the semiconductor device being mounted on the circuit board, and the upper and lower insulating layers have thermal expansion characteristics different from but similar to that of the intermediate insulating layer so that interlayer peeling of the BGA substrate is prevented.