Patent ID: 9165672
Filing Date: 2015-10-20
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to perform a program verification operation in order to sense whether programming of selected memory cells is completed, and each of the plurality of page buffers includes a first data latch and a second data latch; and a control logic configured to provide a set pulse for setting the first data latch and the second data latch of each of the plurality of page buffers to a program inhibit state according to a result of the program verification operation, the control logic providing the set pulse to at least two of the plurality of page buffers simultaneously such that the first data latch of a first one of the at least two of the plurality of page buffers and the second data latch of a second one of the at least two of the plurality of page buffers are set at the same time.