Patent ID: 6121073
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for fabricating fuse structures for semiconductor integrated circuits comprising the steps of:a) providing a semiconductor substrate having devices in device areas surrounded by a field oxide isolation;b) depositing a first polysilicon layer;c) patterning said first polysilicon layer to form portions of said devices and a first level of electrical interconnections, and further forming portions for fuses in said first level of electrical interconnections over said field oxide isolation;d) depositing an interpolysilicon oxide layer over said patterned first polysilicon layer;e) depositing a second polysilicon layer;f) patterning said second polysilicon layer to form a second level of electrical interconnections, and further having portions of said second polysilicon layer over said fuses to provide an etch-stop layer;g) depositing over said substrate an interlevel dielectric layer having via holes with interconnecting metal plugs;h) depositing and patterning over said interdielectric layer a metal layer to form the next level of electrical interconnections;i) carrying out steps g) through h) n times to complete said metal interconnections for said semiconductor integrated circuits, where the number of metal levels is n, and where n is at least 1;j) depositing a barrier layer on said substrate;k) coating a spin-on glass layer on said barrier layer;l) depositing a passivation layer on said spin-on glass layer;m) etching openings through said passivation layer, said spin-on glass layer, said barrier layer, and through said interlevel dielectric layers to said etch-stop layer over said fuses;n) removing completely said etch-stop layer to complete said fuse structures having said interpolysilicon layer that is uniformly thick across said substrate over said fuses.