Patent ID: 6198667
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A semiconductor memory apparatus, having a multi-bank memory array, comprising:a plurality of memory banks representing said memory array;a bank selector for simultaneously accessing at least two of the plurality of memory banks;an input/output controller for selectively outputting a plurality of write enable signals and a plurality of read enable signals in accordance with the number of memory banks selected, a multiple bank selection signal and a control signal; anda buffer unit for transmitting externally applied data to the plurality of memory banks according to the plurality of write enable signals and for outputting data from the plurality of memory banks according to the plurality of read enable signals;wherein at least one of the bank selector and the input/output controller includes a plurality of NAND gates,wherein the buffer unit includes a coincidence unit to indicate whether all of the data outputted from the plurality of memory banks have an identical logical value, and to output the identical logic value when all of the data have the identical logical value.