Patent ID: 7590175
Filing Date: 2009-09-15
Classification: G01R,H04J,H04L

Abstract:
1. A receive circuit comprising: a. a data input terminal to receive a stream of input data symbols; b. a first data sampler having a first data input port, a first data output port, and a first clock terminal to receive a first clock signal, the first data sampler to sample the input data symbols responsive to the first clock signal; c. a second data sampler having a second data input port, a second data output port, and a second clock terminal to receive a second clock signal, the second data sampler to sample the input data symbols responsive to the second clock signal; d. an expected-data source different from the second data output port to provide a stream of expected values representative of historical ones of the input data symbols; e. a decision feedback path extending from the expected-data source to the second data input port, the feedback path to produce a weighted sum of the stream of expected values; and f. clocking circuitry to provide the second clock signal to the second clock terminal at a different phase than the first clock signal.