Patent ID: 6144249
Filing Date: 2000-11-07
Classification: G05F

Abstract:
A bias current generator for generating a bias current that is a function of a clock frequency and a reference voltage, comprising:a first switch controlled by a first clock signal having the clock frequency;a first capacitor connected in parallel with the first switch between a first internal node and a supply voltage node at a supply voltage;a filter comprising:a second switch controlled by a second clock signal having the same clock frequency as and non-overlapping with the first clock signal, the second switch having an input and an output coupled respectively to the first internal node and a second internal node;a second capacitor coupled between the second internal node and the supply voltage node;a third switch controlled by the first clock signal, the input and output of the second switch being coupled respectively to the second internal node and a third internal node; anda third capacitor coupled between the third internal node and the supply voltage node, the third capacitor holding the voltage at the third internal node constant during one period of the first clock signal;an amplifier with a first input coupled to the third internal node, a second input coupled to a reference voltage node at the reference voltage, and an output;a transistor with a gate coupled to the output of the amplifier, a drain coupled to the first internal node and a source coupled to a ground node;wherein:when the first clock signal is active, the first capacitor is discharged and the voltage at the first internal node is at the supply voltage;when the first clock signal is inactive, the voltage at the first internal node ramps down from the supply voltage;a negative feedback loop including the first capacitor, first switch, transistor and amplifier is formed that controls the gate voltage of and thus the drain current drawn by the transistor, the feedback looping causing the voltage at the first internal node to ramp down from the supply voltage to the reference voltage by the time the first clock signal makes a transition from being inactive to active, the drain current being identical to the bias current;when the second clock signal makes a transition from being active to inactive, the voltage at the first internal node is sampled by the second capacitor onto the second internal node; andwhen the first clock signal makes a transition from being inactive to active, the voltage at the second internal node is coupled to the third internal node.