Patent ID: 6968480
Filing Date: 2005-11-22
Classification: H04L

Abstract:
1. A phase adjustable non-causal channel equalization system, the system comprising: a sampler having an input to receive a serial data stream, an input to receive a clock signal, an input to accept a control signal, and an output to provide samples of the serial data stream, sampled at a first phase and a second phase, with respect to a clock period, in response to the control signal; a clock generator having an output to supply the clock signal with the clock period; a non-causal comparator having an input connected to the sampler output to accept the samples, a input to accept threshold reference values, the non-causal comparator determining a first bit value for a current clock cycle by comparing a first bit estimate for the current clock cycle to bit values determined in non-current clock cycles, and having an output to supply a determination of first bit values responsive to the samples at the first phase, and a determination of first bit values responsive to the samples at the second phase; and an error analysis circuit having an input connected to the output of the non-causal comparator to accept first bit values, the error analysis circuit comparing first bit values responsive to the samples at the first phase, to first bit values responsive to the samples at the second phase, calculating an optimal phase for the determination of first bit values, and supplying the control signal to the sampler, responsive to the optimal phase; wherein the non-causal comparator includes: a multi-threshold circuit having an input connected to the sampler output to accept the samples, an input to accept threshold values, and outputs to provide a plurality of bit estimates for each sample, responsive to a plurality of voltage threshold levels; and, a non-causal circuit having inputs to accept bit estimates from the multi-threshold circuit and an output to supply the first bit value for a current clock in response to comparing the first bit estimate for the current clock cycle to bit values determined in non-current clock cycles, the non-causal circuit having an output connected to the error analysis circuit input to supply the first bit value; and wherein the non-causal circuit includes: a future decision circuit having inputs connected to the mutli-threshold circuit outputs to accept the bit estimates, the future decision circuit having outputs to supply the first bit estimate and a third bit value; a present decision circuit having inputs to accept the first bit estimate, the third bit value, and a second bit value, the present decision circuit comparing the first bit estimate to both the second bit value, determined for a clock period prior to the current clock cycle, and the third bit value, determined for a clock cycle subsequent to the current clock cycle, the present decision circuit having an output to supply the first bit value determined in response to comparing the first bit estimate to the second and third bit values; and, a past decision circuit having an input to accept the first bit value and an output to supply the second bit value.