Patent ID: 6743671
Filing Date: 2004-06-01
Classification: H01L

Abstract:
An integrated capacitor comprising:a semiconductor substrate; an outer vertical plate laid over the semiconductor substrate, the outer vertical plate consisting of a plurality of first conductive slabs connected vertically using multiple first via plugs, wherein the outer vertical plate defines a grid area; an inner vertical plate laid over the semiconductor substrate in parallel with the first vertical plate and encompassed by the grid area defined by the outer vertical plate, wherein the inner vertical plate consisting of a plurality of second conductive slabs connected vertically using multiple second via plugs; and a horizontal conductive plate laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof; wherein the inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.