Patent ID: 8027195
Filing Date: 2011-09-27
Classification: G11C

Abstract:
1. A method of operating a non-volatile memory system including a non-volatile memory circuit having an array of non-volatile memory cells formed along a plurality of word lines and a plurality of bit lines, the bit lines forming a plurality of subsets each connectable to a corresponding set of data registers, the method comprising: writing data into a first plurality of memory cells along a first of the word lines in a binary format, the first plurality of memory cells farmed along a corresponding first plurality of bit lines; reading the data from the first plurality of memory cells into the sets of registers corresponding to the first plurality of bit lines; rearranging the data from the first plurality of memory cells within the sets of registers, whereby the data is arranged into sets of registers corresponding to a second plurality of bit lines, the second plurality of bit lines being less than the first plurality of bit lines; and subsequently writing the rearranged data from the registers corresponding to the second plurality of bit lines into a second plurality of memory cells along a second of the word lines and formed along the second set of bit lines in a multi-state format.