Patent ID: 9122613
Filing Date: 2015-09-01
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus comprising: at least one processor for processing data in response to instructions said instructions indicating storage locations for said data and for said instructions by virtual addresses; a hierarchical data storage system for storing said data and said instructions in storage locations identified by physical addresses, said hierarchical data storage system comprising a memory and at least one cache; address translation circuitry for mapping said virtual addresses to said physical addresses; load store circuitry configured to receive access requests from said at least one processor, said access requests indicating storage locations to be accessed as virtual addresses, said load store circuitry being configured to access said address translation circuitry to identify said physical addresses that correspond to said virtual addresses of said received access requests, and to access said corresponding physical addresses in said hierarchical data storage system; preload circuitry configured to receive preload requests from said processor indicating by virtual addresses storage locations that are to be preloaded into at least one of said at least one caches, said preload circuitry having access to said address translation circuitry such that said corresponding physical addresses can be identified; and prefetch circuitry configured to monitor at least some of said accesses performed by said load store circuitry and to predict addresses to be accessed subsequently, said prefetch circuitry being configured to transmit said predicted addresses to said preload circuitry as preload requests; wherein said preload circuitry is configured to respond to said preload requests from said processor and from said prefetch circuitry to preload at least one of said at least one caches with said requested storage locations, wherein said prefetch circuitry is configured to transmit predicted physical addresses within a predetermined range to said preload circuitry such that they are located within in a same page table as said monitored access requests and on a predicted address being outside of said page table to stop sending said predicted addresses, until said monitored addresses move to a new page table.