Patent ID: 7277425
Filing Date: 2007-10-02
Classification: H04L

Abstract:
1. A router comprising: M1 clocked-parallel-data router core ingress ports; M2 clocked-parallel-data router core egress ports; wherein M1 is an integer greater than 1 and M2 is an integer greater than 1 respectively; M1 clocked-parallel-data switch fabric ingress ports; M2 clocked-parallel-data switch fabric egress ports; at least M1 always-up core ingress serial links for serializing clocked parallel data respectively at the M1 router core ingress ports, transmitting the serialized data respectively to the M1 switch fabric ingress ports, and deserializing the serialized data; at least M2 always-up core egress serial links for serializing clocked parallel data respectively at the M2 switch fabric egress ports, transmitting the serialized data respectively to the M2 router core egress ports, and deserializing the serialized data; and at least one digital switch fabric, having at least M1 clocked parallel-data-input ports and M2 clocked parallel-data-output ports, the switch fabric having the capability to concurrently switch parallel data from at least a subset of the M1 parallel-data-input ports to at least a corresponding subset of the M2 parallel-data-output ports according to a reconfigurable input port-to-output port mapping, the M1 clocked parallel-data-input ports connected respectively to receive clocked parallel data from the M1 switch fabric ingress ports, the M2 switch fabric egress ports connected respectively to receive clocked parallel data from the M2 clocked parallel-data-output ports.