Patent ID: 6714440
Filing Date: 2004-03-30
Classification: G11C

Abstract:
A memory comprising:a plurality of memory cells organized in rows and columns, each of the plurality of memory cells located at intersections of the rows and columns; a plurality of write bit lines, each of the plurality of write bit lines having a first end and a second end, wherein a first write current flowing from the first end to the second end of a selected one of the plurality of write bit lines is used for placing a data value in a predetermined memory cell of the plurality of memory cells, the first end of each of the plurality of write bit lines being directly connected to a terminal for receiving a predetermined supply voltage, the second end being coupled to a reference voltage terminal for allowing the first write current to flow to the reference voltage terminal; and a plurality of write word lines, each of the plurality of write word lines having a first end and a second end, wherein a second write current flowing from the first end to the second end of a selected one of the plurality of write word lines is used with the first write current for placing the data value in the predetermined memory cell of the plurality of memory cells, the first end of each of the plurality of write word lines being directly connected to the terminal for receiving the predetermined supply voltage.