Patent ID: 8940603
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a channel region and a source region in a substrate, the source region and the channel region being formed along a first plane; forming a floating gate electrode disposed directly above the channel region; forming an inter-level dielectric layer surrounding the floating gate electrode; forming a first metal level overlying the substrate and overlying the floating gate electrode, the first metal level including a first metal feature electrically coupled to the floating gate electrode and a second metal feature coupled to a control gate node, wherein the first metal feature surrounds the second metal feature from all directions when viewed from a second plane, and wherein the second plane is parallel to the first plane, wherein the first metal feature overlaps with the channel region and the second metal feature overlaps with the source region; and forming a second metal level above the first metal level, the second metal level comprising a third metal feature electrically coupled to the floating gate electrode, and a fourth metal feature coupled to the control gate node, wherein the fourth metal feature surrounds the third metal feature from all directions when viewed from a third plane, and wherein the third plane is parallel to the first plane, wherein the fourth metal feature overlaps with the channel region and the third metal feature overlaps with the source region.