Patent ID: 6202126
Filing Date: 2001-03-13
Classification: G06F

Abstract:
A method for preventing inadvertent invalidation of a most up-to-date copy of a data element stored in a first cache coupled to a first one of a plurality of central processing units in a computer system said computer system comprised of a system control logic coupled to each of said plurality of central processing units, said method comprising the steps of:A) evicting said data element from said first cache in response to a first part of a first command sequence;B) transferring a copy of said data element to one of a plurality of victim data buffers coupled to said first one of said plurality of central processing units, responsive to said first part of said command sequence;C) issuing, by said one of said plurality of central processing units, a second and a third part of said first command sequence to said system control logic;D) impeding the issuance of a set of command sequences from said one of said plurality of central processing units responsive to a plurality of data elements stored in said victim data buffers coupled to said one of said plurality of central processing units;E) releasing said one of said plurality of victim data buffers for use by another data element when a plurality of probe messages, pending in a probe queue coupled to said one of said plurality of central processing units, have each had an address comparison performed against victim data stored in said plurality of victim data buffers; andF) issuing a second set of command sequences, including said command pair, from all processors to a serialization point by means of an arbitration circuit wherein said probe messages comprises all probe messages pending in said probe queue prior to the issuance of said command pair to said serialization point.