Patent ID: 6448123
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A method of providing a low capacitance electrostatic discharge (ESD) protection device, comprising the steps of:providing a semiconductor having a P-substrate; depositing an N-well in said semiconductor, where said N-well has a junction capacitance of less than 0.035 pF; providing a first and a second NMOS transistor on either side of said N-well; arranging the drains of said NMOS transistors around said N-well, the drains of said NMOS transistors having a combined junction capacitance ranging from 0.1 pF to 1 pF; surrounding said first and said second NMOS transistor and said N-well with a P+ type guard ring; depositing a P+ diffusion in said N-well, the junction of said P+ diffusion and said N-well creating a diode; coupling the drains of said NMOS transistors and said P+ diffusion to the chip pad of said ESD protection device; coupling the sources of said NMOS transistors and said guard ring to a reference potential; utilizing a first parasitic SCR, created between said P+ diffusion and the source of said first NMOS transistor, to provide a first current path for said ESD voltage for the ESD protection of a MOS circuit; and utilizing a second parasitic SCR, created between said P+ diffusion and the source of said second NMOS transistor, to provide a second current path for said ESD voltage for the ESD protection of said MOS circuit.