Patent ID: 6576959
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection comprising:a drain extended nMOS transistor; a pnpn silicon controlled rectifier merged with said nMOS transistor so that a dual npn structure is created and both the source of said transistor and the cathode of said rectifier are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced; said rectifier having a diffusion region, forming an abrupt junction, resistively coupled to said drain, whereby the electrical breakdown-to-substrate of said rectifier can be triggered prior to the breakdown of said transistor drain; said rectifier having anode and cathode regions spaced apart by semiconductor surface regions; and insulating layers positioned over said surface regions, said layers having a thickness suitable for high voltage operation and ESD protection.