Patent ID: 7514966
Filing Date: 2009-04-07
Classification: H03K

Abstract:
1. A comparator comprising: first and second diode-connected transistors each having a gate, a source, a drain, and a channel formed between the source and the drain, wherein the channel of the first diode-connected transistor is coupled between a first common node and a first input, and the channel of the second diode-connected transistor is coupled between the first common node and a second input, wherein the first common node is configured to receive a first current; first and second current mirror transistors each having a gate, a source, a drain, and a channel formed between the source and the drain, wherein the gate and the source of the first current mirror transistor is coupled to the gate and the source, respectively, of the first diode-connected transistor, and the gate and the source of the second current mirror transistor is coupled to the gate and the source, respectively, of the second diode-connected transistor; first and second load devices, wherein the first load device is coupled between a supply voltage and the drain of the first current mirror transistor, and the second load device is coupled between the supply voltage and the drain of the second current mirror transistor; and a differential to single-ended stage having a pair of first differential inputs coupled to the drains of the first and second current mirror transistors, wherein the differential to single-ended converter stage is operable to form a single-ended output used to produce an output of the comparator.