Patent ID: 9202533
Filing Date: 2015-12-01
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein, where the number of the bays selected simultaneously is the number of simultaneously selected bays, and the number of the memory cells selected simultaneously in one of the bays is the number of simultaneously selected bits, the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.