Patent ID: 6930919
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A NAND-type flash memory device including a memory cell array having a plurality of memory blocks, comprising: a status cell array having a plurality of status cells and structured to store data indicating an erase/program status of the memory blocks; a data generation circuit structured to generate data indicating a program status of a selected memory block in response to a data input command and to generate data indicating an erase status of a selected memory block in response to a block erase setup command; a first signal generation circuit structured to generate a block status write enable signal and a clock signal in response to either one of an erase command and a program command; a selection circuit structured to select at least one of the status cells of the status cell array in response to a block address of the selected memory block; a write circuit which is structured to receive data from the data generation circuit in response to the clock signal during a program or erase operation and to write the received data in the selected status cell; and a control circuit structured to operate in response to a block status write enable signal from the first signal generation circuit and to control the write circuit to the store the data inputted to the write circuit in a selected status cell when an erase/program operation for the selected memory block is carried out.