Patent ID: 6826670
Filing Date: 2004-11-30
Classification: G06F,Y02D

Abstract:
A data processing apparatus, comprising:a plurality of memory units for storing data values; a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value; a memory controller for performing the access specified by the access request; attribute generation logic for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access; prediction logic for predicting the one or more predetermined attributes; clock generation logic responsive to the predicted predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit; checking logic for determining whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, for reinitiating the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic.