Patent ID: 9142636
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A method of fabricating a III-nitride based transistor comprising: forming a nitride-based layer on a substrate; forming a cap layer on the nitride-based layer, wherein the cap layer is different from the nitride-based layer; forming an etch stop layer on the cap layer, wherein the etch stop layer is different from the cap layer; forming a dielectric layer on the etch stop layer, wherein the dielectric layer is different than the etch stop layer; selectively etching the dielectric layer to the etch stop layer to form a gate recess that extends through the dielectric layer to the etch stop layer; after selectively etching the dielectric layer to the etch stop layer, selectively etching the etch stop layer in the gate recess to, or into but not through, the cap layer; and forming a gate contact in the gate recess, wherein the cap layer comprises a dielectric.