Patent ID: 7521307
Filing Date: 2009-04-21
Classification: H01L

Abstract:
1. A method for fabricating a CMOS structure comprising: forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate; forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor, where the first stressed layer and the second stressed layer abut and overlap; forming a blanket layer over the first stressed layer and the second stressed layer that abut and overlap; further masking the blanket layer over the first stressed layer and the second stressed layer to leave uncovered at least the portion of the first stressed layer and the second stressed layer that abut and overlap; and etching the blanket layer and at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.