Patent ID: 6392428
Filing Date: 2002-05-21
Classification: G01R,H01L

Abstract:
A wafer level interposer comprising:a multi-layer sheet having a first surface and a second surface; a first pattern of electrical contact pads disposed on the first surface and corresponding to a pattern of electrical contact pads disposed on a surface of a semiconductor wafer such that each electrical contact pad disposed on the first surface can be electrically connected to the corresponding electrical contact pad disposed on the surface of the semiconductor wafer; a second pattern of electrical contact pads disposed on the second surface; a testing connector disposed on a side of the multi-layer sheet, the testing connector comprising a plurality of testing contacts; a set of conductors each of which connect at least one electrical contact pad on the first surface to at least one electrical contact pad on the second surface; and a set of testing conductors each of which connect at least one electrical contact pad on the first surface to at least one testing contact.