Patent ID: 7353441
Filing Date: 2008-04-01
Classification: G01R,H03K

Abstract:
1. An apparatus comprising: a data input terminal; a data output terminal; a clock input terminal; a scan data input terminal; a first latch circuit which latches an input data inputted to the data input terminal at a leading edge of a clock signal inputted to the clock input terminal; a second latch circuit which latches the input data at a trailing edge of the clock signal; a selector which, during a period from the leading edge to the trailing edge of the clock signal, selects an output data from the first latch circuit to output a selected output data to the data output terminal, and, during a period of the trailing edge to a next leading edge of the clock signal, selects an output data from the second latch circuit to output a selected output data to the data output terminal; and a scan data output terminal which outputs an output data from the second latch circuit; a circuit which outputs the input data inputted to the data input terminal to the first latch circuit during a normal mode and outputs a scan data inputted to the scan data output terminal to the first latch circuit during a scan mode; and a circuit which outputs the input data inputted to the data input terminal to the second latch circuit during the normal mode and outputs the output data from the first latch circuit to the second latch circuit during the scan mode.