Patent ID: 6385115
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory array including a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns, said plurality of memory blocks being arranged aligned along a column direction; a plurality of sense amplifier bands placed corresponding to the memory blocks along said column direction, each sense amplifier band including sense amplifier circuits for sensing and amplifying data of selected memory cells of a corresponding memory block when activated; a power line laid extending over said plurality of memory blocks and said plurality of sense amplifier bands, said power line including sense amplifier power supply lines each for supplying a power supply voltage to sense amplifier circuits of a respective sense amplifier band and said sense amplifier power supply lines provided corresponding to the sense amplifier bands and extending along a row direction in corresponding sense amplifier bands and connected to one another; a sense amplifier power supply voltage generation circuit for generating a control voltage; and a plurality of drive circuits provided corresponding to the respective sense amplifier bands, each drive circuit being activated when sense amplifier circuits of a corresponding sense amplifier band are active, for supplying a current to a corresponding sense amplifier power supply line according to said control voltage.