Patent ID: 7724585
Filing Date: 2010-05-25
Classification: G11C

Abstract:
1. A static random access memory (SRAM) local evaluation circuit enabling read and write operations of an associated SRAM cell group comprising: a precharge write signal; a first precharge device being connected between a voltage supply VDD and a true bitline; a second precharge device being connected between the voltage supply VDD and a complement bitline; a precharge signal disabling said first and second precharge devices during read and write operations; a passgate device being connected between the complement bitline and a write data propagation input; said write data propagation input being held high during read operations and a write zero operation, and said write data propagation input transitioning low before a write one operation; a transistor stack connected in series with said first precharge device between said true bitline and a ground potential; said transistor stack receiving said precharge write signal and said write data propagation input; and said precharge write signal disabling said passgate device connected between the complement bitline and said write data propagation input during read operations; said precharge write signal enabling the passgate device connected between the complement bitline and the write data propagation input during the write zero operation, and said precharge write signal activating said transistor stack during the write one operation.