Patent ID: 8713277
Filing Date: 2014-04-29
Classification: G06F

Abstract:
1. An interface unit coupled to receive an indication from a memory controller that data corresponding to a read request is expected to be transmitted by the memory controller to the interface unit in a future clock cycle, wherein the interface unit comprises: a control circuit configured to generate a request to forward the data to a source of the read request responsive to the indication, wherein the control circuit is configured to generate the request N clock cycles after receiving the indication from the memory controller to permit forwarding of the data when the data is subsequently received in the future clock cycle, wherein N is a positive integer; and a delay monitor circuit configured to monitor delay for at least a portion of the time from the indication to the forwarding of the corresponding data, wherein the delay monitor circuit is configured to adaptively modify N for subsequent data forwardings for subsequent read requests to account for uncertainties in the delay responsive to detecting that the delay differs from N during the monitoring, wherein the uncertainties cause the delay to be different for different subsequent read requests directed to the same memory controller, and wherein the delay monitor circuit and the control circuit are configured to operate according to a first clock, and wherein N is measured in clock cycles of the first clock, and wherein the memory controller is configured to operate according to a second clock that is asynchronous to the first clock, wherein a cause of the uncertainty in the delay includes a synchronization from a second clock domain associated with the second clock to a first clock domain associated with the first clock.