Patent ID: 6091640
Filing Date: 2000-07-18
Classification: G11C

Abstract:
A semiconductor integrated circuit comprising:a plurality of electrically erasable and programmable non-volatile memory cells each of which has one of an erase threshold voltage region corresponding to an erase state and a write threshold voltage region corresponding to a write state; anda control circuit which controls to apply a first pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a first write operation mode, and a second pulse-shaped voltage to a memory cell of said plurality of non-volatile memory cells in a second write operation mode, wherein a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a first write threshold voltage region from said erase threshold voltage region in accordance with said first write operation mode, and a threshold voltage of said memory cell in said plurality of non-volatile memory cells changes to a second write threshold voltage region from said erase threshold voltage region in accordance with said second write operation,wherein each of said first and said second write operation modes is set by data or a command which is applied to said control circuit, andwherein the amount of change in threshold voltage of the memory cell applied with said first pulse-shaped voltage is larger than the amount of change in threshold voltage of the memory cell applied with said second pulse-shaped voltage.