Patent ID: 6544834
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A process of manufacturing a semiconductor device including:one of a substrate of a semiconductor and a substrate having a semiconductor layer as a surface thereof; a memory call selection MISFET formed on a main surface of the substrate; and an information storage capacity element having a first electrode, a second electrode and a capacity insulating film, the first electrode being electrically connected to a semiconductor region functioning as one of source and drain of the memory cell selection MISFET, the second electrode being formed opposite to the first electrode, the capacity insulating film being put between the first and second electrodes, the process comprising: (a) a step of depositing one of an electrically conductive metal film of metal, an electrically conductive oxide and an electrically conductive nitride by one of a sputtering and a CVD method and forming the first electrode, oriented in a (002) plane, by processing one of the metal film and the oxide film and the nitride film, the first electrode being formed by providing an oxidized region and an unchanged region of said one of the metal film and the oxide film and the nitride film, the oxidized region and the unchanged region having different etching speeds, and removing at least part of the unchanged region; (b) a step of depositing a tantalum oxide film on the first electrode by the CVD method; and (c) a step of forming the capacity insulating film by heat-treating the tantalum oxide film at a temperature under 700Â° C. to grow a crystal of the tantalum oxide, thereby to form a polycrystalline tantalum oxide film.