Patent ID: 8853095
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A method, comprising: forming a damascene conductor in a dielectric layer on a semiconductor substrate and a dielectric barrier layer on a top surface of said damascene conductor and a top surface of said dielectric layer; forming a dielectric stack on a top surface of said dielectric barrier layer, said dielectric stack comprising an interlevel dielectric layer on a top surface of said dielectric barrier layer; forming a lower hard mask layer on a top surface of said dielectric stack and an upper hard mask layer on a top surface of said lower hard mask layer; using a first reactive ion etch selective to said upper and lower hard mask layers over said interlevel dielectric layer, forming a via opening through said upper hard mask layer and said lower hard mask layer to a top surface of said dielectric stack; using a second reactive ion etch selective to said upper hard mask layer and said interlevel dielectric layer over said dielectric barrier layer, extending said via opening through said interlevel dielectric layer to said dielectric barrier layer; removing said lower hard mask layer using a wet etch; using a third reactive ion etch selective to said dielectric barrier layer over said damascene conductor and said interlevel dielectric layer to said damascene conductor, extending said via opening through said dielectric barrier layer to said damascene conductor; and filling said via opening with an electrical conductor.