Patent ID: 7344938
Filing Date: 2008-03-18
Classification: H01L

Abstract:
1. A fabricating method of a semiconductor device, the method comprises steps of: providing a substrate having a memory array, and a plurality of gate structures formed within a first area and a second area; forming a pad oxide layer on the substrate to cover the gate structures; forming a dielectric layer over the pad oxide layer and covering the gate structures; etching the dielectric layer from the first area to form a first spacer on the side walls of the gate structures within the first area; forming a first source/drain region in the substrate beside the side walls of the gate structures in the first area; etching the dielectric layer from the second area to form a second spacer on the side walls of the gate structures in the second area; and forming a second source/second drain region in the substrate beside the side walls of the gate structures in the second area.