Patent ID: 6367053
Filing Date: 2002-04-02
Classification: G06F

Abstract:
A method for use in modeling metalization structures in electrical circuits including a substrate on which the metalization structure is fabricated comprising the steps of:generating charge and/or current distributions from a source of current distribution on a metalization structure; setting a prescribed substrate shielding to obtain a prescribed substrate conductivity, said shielding being placed between the metalization structure and the substrate; shunting parasitic currents from said metalization structure through said shielding to a prescribed potential thereby minimizing long-range interactions between the metalization structures based on underlying characteristics of said charge and/or current distributions that generated said interactions; statically determining at least one admittance for said metalization structure; determining at least one admittance for said substrate; combining said at least one metalization structure admittance and said at least one substrate admittance to generate at least one complex admittance; and utilizing said at least one complex admittance to generate substrate grounding structures forming said shielding for said physical metalization structure to be fabricated, whereby the modeling method converges to correct resulting substrate grounding structures.