Patent ID: 6577689
Filing Date: 2003-06-10
Classification: H03L,H04L

Abstract:
A timing recovery system for recovering timing information from a received data signal having multi-level data therein, comprising:a phase encoder for determining the phase of the received data signal relative to a master clock signal; a phase error device for determining the error between an output phase value and the received phase of the received data signal to generate a phase error for each transition in the received data signal, said phase error device having: an averaging device for averaging the determined phase error value for each received transition in a decimation window of a predetermined potential transition length, and a decimator for outputting the averaged phase error value from said averaging device at the end of each decimation window as said output phase value; and a receive clock generator for generating a clock having a phase value relative to the master clock equal to the phase error output by said decimator.