Patent ID: 8420527
Filing Date: 2013-04-16
Classification: G03F,H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming trenches in a semiconductor substrate, wherein an active region and dummy regions are defined by trenches; (b) after the step (a), filling element isolation insulating films in the trenches; (c) after the step (b), forming first dummy interconnections over the semiconductor substrate; (d) after the step (c), forming a source region of a MISFET and a drain region of the MISFET in the active region; (e) after the step (d), forming a first interlayer insulating film over the first dummy interconnections; and (f) after the step (e), forming an interconnection and second dummy interconnections over the first interlayer insulating film, wherein the dummy regions, the first dummy interconnections and the second dummy interconnections are not functioning as an element, wherein the interconnection is electrically connected to one of the source region and the drain region, wherein, at the step (c), a gate electrode of the MISFET is formed over the active region as the same level layer as the first dummy interconnections, wherein the second dummy interconnections are formed by the same level layer as the interconnection, and wherein the dummy regions, the first dummy interconnections and the second dummy interconnections are arranged at a scribing area.