Patent ID: 6115305
Filing Date: 2000-09-05
Classification: G01R,G11C

Abstract:
In a circuit having a plurality of signal lines, a method for testing the electrical integrity of said signal lines, the method comprising:applying a first voltage potential to a first end of each signal line;in a chain of series-connected transistors, biasing each transistor thereof with the potential at a second end of each signal line, said chain of transistors having a first end terminal and a second end terminal, said second end terminal capable of being in a high-impedance state or a conductive state;applying a second voltage potential to said first end terminal of said chain of transistors; anddetecting a potential at said second end terminal of said chain of transistors;whereby an open in one of said signal lines is indicated by said second end terminal being in a high-impedance state, and the absence of an open in any of said signal lines is indicated by said second end terminal having a potential between ground potential and said second voltage potential.