Patent ID: 7299388
Filing Date: 2007-11-20
Classification: G01R,G11C

Abstract:
1. A method of testing and individually configuring a plurality of chips of a wafer comprising: (a) identifying said plurality of chips of said wafer for testing; (b) coupling said identified chips to a wafer test system, wherein said system issues commands to test and configure said plurality of identified chips; (c) assigning an identification to each of said identified chips and storing said assigned identification within a corresponding register of that chip in response to said identified chips receiving identification commands from said wafer test system; (d) selecting an identified chip; and (e) determining at least one parameter value for said selected chip and individually accessing said selected chip based on said assigned identification and storing each determined parameter value in the corresponding chip register to configure that chip in response to said identified chips receiving selection and parameter commands from said wafer test system, wherein at least two of said chips include different parameter values.