Patent ID: 7609569
Filing Date: 2009-10-27
Classification: G11C

Abstract:
1. A system for implementing row redundancy in integrated circuit memory devices, comprising: one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith; a discrete, redundant subarray associated with the one or more main subarrays, the redundant subarray also including a set of support circuitry associated therewith; a common global bit line shared by the one or more main subarrays and the redundant subarray; and redundancy steering control circuitry associated with the one or more main subarrays and the redundant subarray, wherein the redundancy steering control circuitry is configured such that word line activation of the one or more main subarrays and the redundant subarray is performed in parallel with address compare operations performed by the redundancy steering control circuitry, in that word line activation of the one or more main subarrays is not delayed by results of the address compare operations.