Patent ID: 7855534
Filing Date: 2010-12-21
Classification: G05F

Abstract:
1. A method for regulating a voltage using a linear voltage regulator, the linear voltage regulator having a first circuit with a primary output node and a second circuit having first and second inverters electrically to the primary output node, the method comprising: receiving a first voltage from a voltage source at the first circuit; removing frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node utilizing the first circuit; and removing frequency components of the output voltage in a second frequency range utilizing the first and second inverters of the second circuit, the second frequency range being greater than the first frequency range; wherein the second circuit further includes a P-FET transistor, the first inverter having a first input terminal and a first output terminal, the first input terminal being electrically coupled to the first output terminal, the first input terminal being further electrically coupled to a capacitor which is further coupled to electrical ground, the first inverter being further electrically coupled to the primary output node, the second inverter having a second input terminal and a second output terminal, the second input terminal being electrically coupled to the first output terminal of the first inverter, the second inverter being further electrically coupled to the primary output node, the P-FET transistor having a gate terminal, a drain terminal and a source terminal, the source terminal being electrically coupled to the voltage source, the drain terminal being electrically coupled to the primary output node, the gate terminal electrically communicating either directly or indirectly with the second output terminal of the second inverter, wherein removing frequency components of the output voltage in the second frequency range utilizing the second circuit, comprises: outputting a second voltage on the first output terminal of the first inverter that is less than the output voltage on the primary output node, when the output voltage at the primary output node is increased; outputting a high logic voltage from the second inverter on the second output terminal in response to the second voltage being less than the output voltage; and reducing the output voltage on the primary output node in response to the high logic voltage utilizing the P-FET transistor.