Patent ID: 6763511
Filing Date: 2004-07-13
Classification: G06F,H01L

Abstract:
A semiconductor integrated circuit comprising:a macro cell arranged on a chip; a plurality of power terminals formed on an upper portion of said macro cell, and a plurality of ground terminals formed thereon; a first wiring group including at least one power wiring and one ground wiring extended in a first direction along a first side of said macro cell; a second wiring group including at least one power wiring and one ground wiring extended in said first direction along a second side of said macro cell opposite to said first side; and a third wiring group, which is arranged in a second direction on said macro cell, and which include at least one power wiring and one ground wiring for establishing connection between said first wiring group and said second wiring group, wherein the power wiring and the ground wiring which form said third wiring group are respectively connected to the corresponding power terminal and the corresponding ground terminal on said macro cell and said first wiring group includes one ground wiring and two power wirings arranged on both sides of said wiring, and said second wiring group includes one power wiring and two ground wirings arranged on both sides of said power wiring.