Patent ID: 6548363
Filing Date: 2003-04-15
Classification: H01L

Abstract:
A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a field effect transistor (FET) device with attenuated drain leakage, short channel effect and punch-through leakage current comprising:providing a silicon semiconductor substrate; forming within the silicon semiconductor substrate field oxide isolation regions defining an active device region within said substrate; forming over the active region a silicon oxide gate oxide insulation layer; forming over the gate oxide insulation layer a patterned polycrystalline silicon layer which constitutes a gate electrode pattern; thermally oxidizing the silicon substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and beyond; forming spacers by etching back by means of anisotropic self-aligned etching the thicker silicon oxide layer at the edge of the gate electrode and beyond; using said spacers as a mask to implant ions to define shallow source and drain extension regions; and forming source and drain regions employing ion implantation using said spacers as a mask.