Patent ID: 6690347
Filing Date: 2004-02-10
Classification: G09G,G11C

Abstract:
A shift register in which multiple stages are connected one after another to each other, the multiple stage having a first stage in which a start signal is coupled to an input terminal, the shift register sequentially outputting output signals of respective stages, the multiple stages including odd stages for receiving a first clock signal and even stages for receiving a second clock signal having a phase opposite to the first clock signal,each of the multiple stages comprising: a pull-up means for providing a corresponding one of the first and second clock signals to an output terminal; a pull-up driving means connected to an input node of the pull-up means, for turning on the pull-up means in response to a front edge of an input signal and turning off the pull-up means in response to a front edge of an output signal of a next stage; a pull-down means for providing a first power voltage to the output terminal; and a pull-down driving means connected to an input node of the pull-down means, for turning off the pull-down means in response to the front edge of the input signal and turning on the pull-down means in response to the front edge of the output signal of the next stage.