Patent ID: 8754534
Filing Date: 2014-06-17
Classification: G06F,G11C,H01L

Abstract:
1. A semiconductor device in which a plurality of memory chips are mounted in a stacked manner on a main surface of a wiring board, wherein: the plurality of memory chips includes at least four memory chips, each of the plurality of memory chips has a front main surface facing away from the wiring board and a rear main surface opposite the front main surface and facing toward the wiring board, the front main surface of each of the plurality of memory chips has a respective first side, respective first terminals are formed on the first side of the front main surface of each of the plurality of memory chips, the plurality of memory chips are stacked in a dislocated manner along a direction perpendicular to the first side of each front main surface so that the first terminals provided on the first side of each front main surface are exposed from other memory chips of the plurality, the first side of a memory chip of a lowermost layer of the plurality of memory chips is disposed in line with a first side of the wiring board, a number of the memory chips dislocated continuously in a same direction is at least two, except for a memory chip of an uppermost layer in the plurality of memory chips, a memory chip of an uppermost layer in a group of the memory chips dislocated continuously in the same direction is stacked in a state of being rotated 180° degrees from each other memory chip in the group, an interposer is provided on the memory chip of the uppermost layer of the plurality of memory chips, the interposer is connected to a memory chip having the first terminals thereof disposed toward the first side of the wiring board or a memory chip having second terminals on a side opposite to the first side of the wiring board through first wires, the interposer is further connected to the wiring board through second wires, a memory controller chip for controlling the memory chips is provided on the interposer, and the memory controller chip is electrically connected to the interposer.