Patent ID: 7154803
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations within the memory sector according to an address, the redundancy scheme comprising: at least one redundant memory sector adapted to functionally replace one of the at least two memory sectors; a redundancy control circuitry for causing the functional replacement of a memory sector declared to be unusable by one of the at least one redundant memory sector, said redundancy control circuitry detecting an access request to a memory location within the unusable memory sector and diverting the access request to a corresponding redundant memory location in the redundant memory sector, associated with each memory location selector, respective power supply control means adapted to selectively connect/disconnect the associated memory location selector to/from a power supply distribution line, said power supply control means comprise a switch, responsive to the respective memory sector unusable status indicator element, for switching a supply voltage input (