Patent ID: 7099986
Filing Date: 2006-08-29
Classification: G06F

Abstract:
1. A computer system comprising: a central processing unit; a core logic chipset coupled to the central processing unit; a peripheral component interconnect (PCI) bus coupled to the core logic chipset and configured to: operate on a sequential series of clock cycles; implement registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol; a registered PCI device connected to the PCI bus and configured to: operate according to the registered PCI protocol; issue a first command on a first clock cycle of the PCI bus according to the registered PCI protocol; and issue a second command on a second clock cycle of the PCI bus according to the registered PCI protocol, wherein the second command is an extended command to the first command and is associated with a split completion issued on a C/BE[3:0]# portion of the PCI bus.