Patent ID: 9009579
Filing Date: 2015-04-14
Classification: G06F

Abstract:
1. An address translation checking device comprising: a memory management unit that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses in physical memory and virtual addresses in virtual memory, the memory management unit being provided with a buffer for storing translation table information indicating the translation table; a storage unit provided outside the memory management unit and that stores the translation table information and error detection information attached to the translation table information, the error detection information being for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the memory management unit; and an error detection unit that detects the presence or absence of the error on the basis of the error detection information, wherein a predetermined value is stored at a predetermined physical address in the physical memory, the error detection information is information for translation between the predetermined physical address and a virtual address, and the error detection unit uses the error detection information read into the buffer to read a value stored in the physical memory according to the virtual address corresponding to the predetermined physical address and detect whether or not the read value is the same as the predetermined value.