Patent ID: 6838722
Filing Date: 2005-01-04
Classification: H01L,Y10S

Abstract:
1. A trench-gated MIS device formed in a semiconductor chip and comprising: an active area containing transistor cells; a gate metal area containing no transistor cells; and a gate metal layer, wherein a trench is formed in a pattern on a surface of the semiconductor chip, the trench extending from the active area into the gate metal area, the trench having walls lined with a layer of an insulating material, a conductive gate material being disposed in the trench, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlaying the active and gate metal areas, an aperture being formed in the nonconductive layer over a portion of the trench in the gate metal area, the aperture being filled with a gate metal such that the gate metal contacts the gate material in an area of contact within the trench and wherein a first gate finger extends from the active area to the gate metal area. the area of contact between the gate contact material and the conductive gate material being located in a second gate finger, the second gate finger being perpendicular to the first gate finger.