Patent ID: 8724067
Filing Date: 2014-05-13
Classification: G02F,G09G

Abstract:
1. An active device array substrate comprising: a substrate; a plurality of first scan lines; a plurality of second scan lines, wherein the first scan lines and the second scan lines are alternately arranged along a first direction on the substrate; a plurality of data lines arranged in parallel along a second direction on the substrate and intersecting with the first scan lines and the second scan lines; and a plurality of pixels arranged to form a plurality of first pixel rows and a plurality of second pixel rows, the first pixel rows and the second pixel rows being alternately arranged along the first direction, each of the first pixel rows comprising a plurality of first pixels and a plurality of second pixels, the first pixels and the second pixels being alternately arranged along the second direction, the first pixels being electrically connected to the first scan lines and the data lines, the second pixels being electrically connected to the second scan lines and the data lines, each of the second pixel rows comprising a plurality of third pixels and a plurality of fourth pixels, the third pixels and the fourth pixels being alternately arranged along the second direction, the third pixels being electrically connected to the first scan lines and the data lines, the fourth pixels being electrically connected to the second scan lines and the data lines, the pixels located between two adjacent data lines are arranged in two columns, wherein among the pixels located in the same column, parts of the pixels in odd rows and the other parts of the pixels in even rows are electrically connected to different data lines, respectively, wherein the first pixels and the fourth pixels located between two adjacent data lines are substantially aligned in the first direction, and the second pixels and the third pixels located between two adjacent data lines are substantially aligned in the first direction, wherein the first pixels and the third pixels located between two adjacent data lines are electrically connected to one of the two adjacent data lines, and the second pixels and the fourth pixels located between two adjacent data lines are electrically connected to the other one of the two adjacent data lines.