Patent ID: 6574157
Filing Date: 2003-06-03
Classification: G11C

Abstract:
An adaptable redundancy circuitry having a plurality of fuse sets, fit to be implemented into a modular memory structure, the circuitry comprising:nine fuse-added elements, which receive address lines externally by one-to-one and respectively generates an output signal; three enable fuse elements, programmed according to a fuse set enable signal so as to respectively generate a line enable signal to enable a line defect memory, a sector enable signal to enable a sector defect memory and an MAT enable signal to enable an MAT defect memory; a first NAND gate having three inputs and an output, the three inputs respectively receiving the three bottom output signals of the nine fuse-added elements, and generating an output signal from the output; a second NAND gate having three inputs and an output, the three inputs respectively receiving the three middle output signals of the nine fuse-added elements, and generating an output signal from the output; a third NAND gate having three inputs and an output, the three inputs respectively receiving the three top output signals of the nine fuse-added elements, and generating an output signal from the output; a first NOR gate having three inputs and an output, the three inputs respectively receiving the output signals from the first NAND gate, the second NAND gate and the third NAND gate, and generating an output signal from the output; a second NOR gate having two inputs and an output, the two inputs respectively receiving the output signals from the second NAND gate and the third NAND gate, and generating an output signal from the output; an inverter, which receives an output signal of the third NAND gate and generates an inverted phase output signal; a fourth NAND gate having two inputs and an output, the two inputs respectively receiving the line enable signal and the output signal of the first NOR gate, and generating a line replacement signal from the output; a fifth NAND gate having two inputs and an output, the two inputs respectively receiving the sector enable signal and the output signal of the second NOR gate, and generating a sector replacement signal from the output; a sixth NAND gate having two inputs and an output, the two inputs respectively receiving the MAT enable signal and the inverted phase output signal, and generating an MAT replacement signal from the output.