Patent ID: 6396309
Filing Date: 2002-05-28
Classification: G11C,H03K

Abstract:
A clocked sense amplifier flip flop comprising:first and second dynamic data nodes; first and second precharge devices to precharge said first and second dynamic data nodes, respectively, during a first portion of a clock signal; a sense amplifier to discharge one of said first and second dynamic data nodes during a second portion of said clock signal based on a data signal at an input of said sense amplifier; a latch to latch a data bit from said first and second dynamic data nodes into an internal storage location of said latch in response to a control signal; and a keeper unit coupled to said first dynamic data node to maintain a low voltage level on said first dynamic data node for a remainder of said second portion of said clock signal when said first dynamic data node is discharged by said sense amplifier regardless of changes in said data signal during said remainder of said second portion of said clock signal.