Patent ID: 9030020
Filing Date: 2015-05-12
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a substrate; device regions provided in the substrate to extend in a first direction which is parallel to a principal plane of the substrate; select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction; and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions, wherein the contact region includes: first partial regions, in each of which three contact plugs are disposed on three successive device regions so that the three contact plugs are arranged on a straight line which is non-parallel to the first and second directions; and second partial regions, in each of which two contact plugs are disposed on two successive device regions so that the two contact plugs are arranged on a straight line which is non-parallel to the first and second directions, wherein the first and second partial regions are alternately disposed in the contact region along the second direction.