Patent ID: 6268247
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A process for forming a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions, which process comprises the steps of:in said active area regions, forming a gate oxide layer and defining a tunnel oxide region included in said gate oxide layer;depositing and partly defining a first polysilicon layer;forming an interpoly dielectric layer and removing said interpoly dielectric layer at least at said circuitry transistor;depositing a second polysilicon layer;selectively etching away, through a first mask, at least said second polysilicon layer at said cell and said first and second polysilicon layers of said circuitry transistor;selectively etching away, through a second mask, said interpoly dielectric layer and said first polysilicon layer at said cell;following the selective etch through said second mask, implanting dopant through said second mask at least at the channel region of the storage transistor for setting a threshold of the storage transistor.