Patent ID: 6479850
Filing Date: 2002-11-12
Classification: H01L,Y10S

Abstract:
A semiconductor integrated circuit comprising:a conductivity layer formed on a first inter-level insulating layer on a semiconductor substrate; a capping metal layer formed on the conductivity layer, where the capping metal layer has a higher selective etching rate than an oxide layer; a lower electrode in a â€œconductivity layer/capping metal layerâ€  deposition structure formed by selectively etching the capping and metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer; a second inter-level insulating layer formed on the first inter-level insulating layer having the lower electrode; an opening defined by the second inter-level insulating layer and the lower electrode formed by selectively etching the second inter-level insulating layer and the lower electrode to a predetermined end point, exposing a predetermined portion of the surface of the lower electrode, wherein a tapered capping metal layer remains along the lower edges at the closed end of the opening; and a dielectric layer in the opening between the lower electrode and an upper electrode.