Patent ID: 8791718
Filing Date: 2014-07-29
Classification: G06F,H03K

Abstract:
1. A sequential state element synchronizable in accordance with a clock signal that oscillates between a first clock state and a second clock state, the sequential state element comprising: a first sampling stage configured to sample a first input bit signal having a first input bit state and generate a first output bit signal having a first output bit state provided in accordance with the first input bit state while the clock signal is in the first clock state; a first feedback stage operable in a first feedback mode and a second feedback mode, wherein the first feedback stage is configured to drive the first output bit state of the first output bit signal while the clock signal is in the second clock state such that the first output bit state of the first output bit signal is held as provided from the first sampling stage when the first feedback stage is in the first feedback mode and the first output bit state is held in accordance to a majority bit state of a first feedback input bit signal that provides feedback for the first output bit signal, a second feedback input bit signal, and a third feedback input bit signal when the first feedback stage is in the second feedback mode.