Patent ID: 7340553
Filing Date: 2008-03-04
Classification: G06F

Abstract:
1. A data processing device, comprising: a first processing unit linked to a first bus, a second processing unit linked to a second bus, a first bus master linked to said first bus, a second bus master linked to said second bus, a first and a second communication channel linking said first and said second bus master with each other, and a control unit controlling the data transfer between said first and said second bus master via said first and said second communication channel, wherein each of the first and the second communication channels includes one or more hardware FIFO buffers, each hardware FIFO buffer having a first clock input linked to the first bus master and a second clock input linked to the second bus master, and wherein the control unit comprises an address register generator, whose input is connected to the first processing unit and whose output is connected to the second bus master, and the control unit comprises a further address register generator whose input is connected to the first processing unit and whose output is connected to the first bus master, each of the address register generator and the further address register generator generating a sequence of incremental addresses.