Patent ID: 8976597
Filing Date: 2015-03-10
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array configured having a plurality of NAND cell units arranged therein, each NAND cell unit configured having a plurality of memory cells connected in series, each memory cell configured capable of storing an erase state in which data is erased from a memory cell and a write state in which data is written to a memory cell; a plurality of word lines connected to the plurality of memory cells, respectively; and a control circuit, the control circuit being configured to execute an erase operation that includes an erase pulse application operation configured to apply an erase pulse voltage to a memory cell to change a memory cell from the write state to the erase state and an erase verify operation configured to apply an erase verify voltage to a memory cell to judge whether a memory cell is in the erase state or not, and the control circuit being configured capable of repeatedly executing the erase pulse application operation multiple times while increasing a voltage value of the erase pulse voltage, until it is judged by the erase verify operation that the erase operation is completed, the control circuit being configured such that, when a number of times of executions of the erase pulse application operation in one erase operation reaches a first number, the control circuit raises a value of the erase verify voltage in the erase verify operation, and the control circuit being configured to apply a voltage not smaller than 0 V to the plurality of word lines in the erase verify operation.