Patent ID: 6738845
Filing Date: 2004-05-18
Classification: G06F,H04W

Abstract:
A system, comprising:a first data processing subsystem comprising a first processor coupled to a first bus as a first bus master; a second data processing subsystem comprising a second processor coupled to a second bus as a second bus master; a direct memory access (DMA) subsystem comprising a DMA controller coupled to a third bus as a third bus master; a first slave subsystem comprising a memory unit coupled to a fourth bus; a second slave subsystem comprising a fifth bus; a first arbitration unit associated with the first slave subsystem, having each of the first, second, third and fourth busses coupled thereto, configured and arranged to arbitrate among at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem for access to the first slave subsystem, and to couple the fourth bus to any selected one of at least the first, second, and third busses so as to enable a selected one of at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the first slave subsystem; and a second arbitration unit associated with the second slave subsystem, having each of the first, second, third and fifth busses coupled thereto, configured and arranged to arbitrate among at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem for access to the second slave subsystem, and to couple the fifth bus to any selected one of at least the first, second, and third busses so as to enable a selected one of at least the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the second slave subsystem; wherein each of the first and second arbitration units is configured and arranged to operate independently such the first arbitration unit can enable any one of the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the first slave subsystem at the same time that the second arbitration unit enables any other of the first data processing subsystem, the second data processing subsystem, and the DMA subsystem to access the second slave subsystem; and wherein the DMA subsystem is configured and arranged such that, when the first and second arbitration units enables the DMA subsystem to access each of the first and second slave subsystems, the DMA controller can cause data to be transferred between the first slave subsystem and the second slave subsystem via the third bus.