Patent ID: 8942280
Filing Date: 2015-01-27
Classification: G01R,H04B,H04L

Abstract:
1. An apparatus for measuring timing jitter, the apparatus comprising: a converter configured to convert a signal to a digital signal; a phase-locked loop (PLL), coupled to the converter, configured to provide a clock signal according to a frequency of the signal; and an interpolator bank, coupled to the converter and including m interpolators configured to over-sample the digital signal, wherein m is an over-sampling rate and m is not smaller than 2, the interpolator bank configured to generate a sample a(t) at time t as: where X i denotes a sample received from an equalizer by j-th interpolator, k 1 =i−M, k 2 =i+N, k 2 >k 1 at time i, and M and N are integers.