Patent ID: 6486515
Filing Date: 2002-11-26
Classification: H01L

Abstract:
An electrostatic discharge device in a silicon-on-insulator integrated circuit comprising:a P+ region within a portion of an N-well in a silicon semiconductor substrate and a N+ region within a portion of said semiconductor substrate not occupied by said N-well wherein said P+ region and said N+ region form diodes of said electrostatic discharge device; forming an oxide layer overlying said semiconductor substrate; an oxide layer overlying said semiconductor substrate wherein openings in said oxide layer in active areas are filled with an epitaxial silicon layer wherein said epitaxial silicon layer also overlies said oxide layer; shallow trench isolation regions within said epitaxial silicon layer between said active areas wherein said shallow trench isolation regions extend to underlying said oxide layer; gate electrodes and associated source and drain regions in and on said epitaxial silicon layer between said shallow trench isolation regions; an interlevel dielectric layer overlying said gate electrodes and said associated source and drain regions; and a conducting layer filling first contacts through said interlevel dielectric layer to underlying said source and drain regions and filling second contact openings through said interlevel dielectric layer, said shallow trench isolations, and said oxide layer to said diodes to complete said electrostatic discharge device in a silicon-on-insulator integrated circuit.