Patent ID: 8741755
Filing Date: 2014-06-03
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor device, the method comprising: forming a plurality of element isolation regions extending in a first direction in parallel on a semiconductor substrate so that a plurality of active regions each sandwiched between adjacent two of the element isolation regions are defined in the semiconductor substrate, each of the element isolation regions having an element isolation insulating film filling an isolation trench formed in the semiconductor substrate, and the active regions being arranged at a predetermined pitch in a second direction intersecting with the first direction; forming a plurality of gate trenches extending in the second direction across the element isolation regions and the active regions, each of the gate trenches having a plurality of first trench portions crossing the active regions and a plurality of second trench portions crossing the element isolation regions, the first trench portions having bottom surfaces positioned at higher than bottom surfaces of the second trench portions so that each of the active regions have a plurality of first fin portions formed on the bottom surfaces of the first trench portions protruding with respect to the bottom surfaces of the second trench portions, and the second trench portions having a width in the first direction wider than a width of the first trench portions in the first direction so that each of the active regions have a plurality of second fin portions formed on side surfaces of the first trench portions protruding with respect to the side surfaces of the second trench portions; forming a plurality of conductive films each buries a lower portion of an associated one of the gate trenches; and forming a plurality of cap insulating films each covers an upper surface of an associated one of the conductive films so that the cap insulating films bury upper portions of the gate trenches.