Patent ID: 7678638
Filing Date: 2010-03-16
Classification: H01L

Abstract:
1. A method for manufacturing a MOSFET device, comprising: forming a ground plane of a monocrystalline Si based material, and selecting dopant impurities in said ground plane to be of a first type with a concentration of between about 1×10 depositing by selective epitaxy a body layer of between about 2 nm and 7 nm thickness over said ground plane, whereby creating an interface between said ground plane and said body layer, in-situ doping said body layer with impurities of a second type to a concentration of between about 5×10 disposing a gate insulator layer over said body layer; disposing a gate over said gate insulator layer, wherein said gate comprises a mid-gap workfunction metal which is in direct contact with said gate insulator layer, and patterning said gate to a length of less than about 40 nm; and forming a source and a drain, selecting dopant impurities in said source and said drain to be of said second type with a concentration of between about 5×10