Patent ID: 9130558
Filing Date: 2015-09-08
Classification: G06F,H01L,H03K

Abstract:
1. A circuit comprising: an arithmetic portion configured to perform a logic operation processing based on an input signal; and a data storage portion configured to store first data or second data, wherein the data storage portion comprises a first transistor configured to write the first data and a second transistor configured to write the second data, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer including a source region, a drain region, and a channel formation region between the source region and the drain region, wherein each of the first transistor and the second transistor comprises a gate electrode over the channel formation region and a protective insulating layer over the gate electrode, wherein the oxide semiconductor layer comprises a crystal aligned along a c-axis, and wherein the first data is an output potential from the arithmetic portion.