Patent ID: 6710441
Filing Date: 2004-03-23
Classification: H01L,H02M,Y02B

Abstract:
An integrated circuit assembly comprising:a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere; a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to a surface of the package; at least one metallization layer coupled with the substrate and configured to couple at least some of the sources in parallel and at least some of the drains in parallel; and wherein the semiconductive substrate further comprises a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package.