Patent ID: 6665828
Filing Date: 2003-12-16
Classification: G01R

Abstract:
A level sensitive scan design (LSSD) method of testing an IC having a plurality of logic units comprising the method steps of:partitioning a plurality of LSSD scan chains within each of said logic units, wherein each LSSD scan chain has a logic scan input and a logic scan output; positioning a plurality of scan blocks distributively in areas around said logic units, said scan blocks operable to receive and interconnect selected ones of said logic scan inputs, first selected ones of said logic scan outputs, and selected central scan switch outputs, wherein said scan blocks generate scan block outputs in response to scan block control signals; receiving in a central scan switch, tester inputs, second selected ones of said logic scan outputs and selected scan block outputs; generating in said central scan switch, central scan switch outputs, tester outputs and said scan block control signals; and selectively receiving in a first one of said scan blocks an output of a second one of said scan blocks.