Patent ID: 6584020
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A semiconductor memory device capable of conducting a device evaluation test, comprising:a memory cell array including a plurality of memory cells; and an intermediate voltage generating circuit for generating an intermediate voltage to be supplied to said memory cell array, wherein said intermediate voltage generating circuit includes an output stage including a first transistor connected between an output node and a power-supply node and a second transistor connected between said output node and a ground node, a reference stage including a first reference voltage generating circuit connected between a reference node and a power-supply node for generating a first reference voltage that is higher than a voltage of said reference node and that is to be supplied to a control electrode of said first transistor and a second reference voltage generating circuit connected between said reference node and a ground node for generating a second reference voltage that is lower than a voltage of said reference node and that is to be supplied to a control electrode of said second transistor, and a pad connected to said reference node for receiving a voltage externally supplied during said device evaluation test.