Patent ID: 8384138
Filing Date: 2013-02-26
Classification: H01L

Abstract:
1. An SRAM memory device, comprising: a semiconductor body including a logic region and a core region; a doped well region formed in an active region defined by isolation structure in the core region of the semiconductor body; respective gate electrodes of two transistors of adjacent memory cells formed over the active region, the gate electrodes having respective sides adjacent the isolation structure and sides away from the isolation structure; an epitaxial growth region formed in the well region on the sides of the gate electrodes away from the isolation structure, the epitaxial growth region inducing strain in respective channel regions defined under the gate electrodes; a first source/drain region formed in the epitaxial growth region and commonly shared by the two transistors; respective second source/drain regions of the two transistors formed in the well region on the sides of the gate electrodes adjacent the isolation structure; the second source/drain regions being formed in parts of the well region having no epitaxial growth region at least in moat tip regions adjacent the isolation structure; sidewall spacers formed on the respective gate electrodes; the epitaxial growth region extending below facing ones of the sidewall spacers of the two transistors, wherein the first source/drain region is self-aligned with the facing sidewall spacers, leaving portions of the epitaxial growth region laterally spaced from the first source/drain region, source/drain extension regions formed in the portions of the epitaxial growth region laterally spaced from the first source/drain region, a second doped well region formed in a second active region defined by second isolation structure in the logic region of the semiconductor body; respective second gate electrodes of second two transistors formed over the second active region, the second gate electrodes having respective sides adjacent the second isolation structure and sides away from the second isolation structure; a second epitaxial growth region formed in the second well region on the sides of the second gate electrodes away from the second isolation structure, the second epitaxial growth region inducing strain in second channel regions defined under the second gate electrodes; a third source/drain region formed in the second epitaxial growth region and commonly shared by the second two transistors; respective third epitaxial growth regions formed in the second well region on the sides of the second gate electrodes adjacent the isolation structure; and respective fourth source/drain regions of the second two transistors formed in the respective third epitaxial growth regions.