Patent ID: 7895545
Filing Date: 2011-02-22
Classification: G06F,Y02P

Abstract:
1. A method of designing a product chip, the method comprising: (a) using an automated tester to identify a plurality of signal paths within a chip design that can be readily identified from chip fail data; (b) using a software tool to remove a fraction of the signal paths that have physical design constraints to generate a subset of the signal paths; (c) constructing a physical implementation of the signal paths in the subset with the software tool by selecting an equal number of logic paths wired on each of a plurality of adjacent pairs of a plurality of wiring levels in a back-end-of-line (BEOL) interconnect structure; (d) identifying with the software tool one or more signal paths in the subset that are not constructed with the respective targeted physical implementation; (e) discarding the one or more signal paths from the subset that are not constructed with the respective targeted physical implementation; and (f) using the subset in a design of experiment (DOE) analysis with the software tool to identify yield detractors in the plurality of wiring levels of the back-end-of-line (BEOL) interconnect structure.