Patent ID: 8604592
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first insulating layer which has a specific dielectric constant of 3 or less; a first dummy metal which is formed in the first insulating layer; a second insulating layer which is formed on a surface of the first insulating layer and the first dummy metal; a third insulating layer which is formed on the second insulating layer, and which has a specific dielectric constant of 3 or less; a second dummy metal which is formed in the third insulating layer; a fourth insulating layer which is formed on a surface of the third insulating layer and the second dummy metal; a plurality of dummy vias which make plural interconnections between a surface of the first dummy metal and a bottom of the second dummy metal; and a seal which is formed through the first insulating layer, the second insulating layer and the third insulating layer so as to surround a circuit formation region of the semiconductor device, wherein the first dummy metal, the second dummy metal and the dummy vias are formed in a region which is outside the seal, in a direction towards an edge of the semiconductor device and away from the seal, each of the seal, the first dummy metal, the second dummy metal and the dummy vias includes Cu material, and the dummy vias are arranged along a plurality of columns in plan view in such a manner that the dummy vias form a zigzag arrangement in which the dummy vias that are arranged in adjacent columns are not aligned with one another in a spacing direction while the dummy vias in columns spaced apart from each other by one adjacent column are aligned with one another in the spacing direction.