Patent ID: 6324099
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a semiconductor substrate of a first conductivity type;first and second diffusion regions of a second conductivity type formed in a surface layer of said semiconductor substrate to define a channel region therebetween;a gate insulating film formed on the channel region, said gate insulating film including a carrier trap layer capable of trapping charge carriers;a gate electrode formed on said gate insulating film; anda control circuit for controlling: in a data write mode, to apply a high level voltage to said gate electrode, a low level voltage to one of said first and second diffusion regions, and a high level voltage to the other of said first and second diffusion regions to inject hot charge carriers of the second conductivity type in the carrier trap layer near the diffusion region applied with the high level voltage; in a data read mode, to flow carriers of the second conductivity type in the channel region along a direction opposite to a direction in the data write mode; and in a data erase mode, to apply a low level voltage or an opposite polarity voltage to said gate electrode, a low level voltage to the one of said first and second diffusion regions, and a high level voltage to the other of said first and second diffusion regions to inject hot charge carriers of the first conductivity type generated by an interband tunneling effect near the other of the first and second diffusion regions, into the carrier trap layer near the diffusion region applied with the high level voltage, and neutralize charge carriers of the second conductive type.