Patent ID: 8347036
Filing Date: 2013-01-01
Classification: G06F

Abstract:
1. A method of data processing in a data processing system including a plurality of lower level caches and a plurality of architecturally distributed system memories coupled by an interconnect fabric, wherein the plurality of lower level caches includes first, second and third lower level caches, wherein the first lower level cache is associated with a first processing unit having a first processor core and an associated first upper level cache and the second lower level cache is associated with a second processing unit having a second processor core and an associated second upper level cache, said method comprising: in response to a data request, the first processing unit: the first processing unit thereafter issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is a single intended destination of the victim cache line among the plurality of lower level caches; and in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache.