Patent ID: 8055965
Filing Date: 2011-11-08
Classification: G01R,G06F

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of said plurality of scan flip-flops, respectively, the clock input providing a clock signal, wherein said plurality of clock gating circuits are connected in series to form a chain and gating setting data is inputted serially through the chain connection, wherein each of said plurality of clock gating circuits controls a gating between the clock input and a corresponding portion of said plurality of scan flip-flops based on said gating setting data, and wherein one of said plurality of clock gating circuits gates clock pulses of the clock signal to said scan flip-flops corresponding to the one of said plurality of clock gating circuits and another one of said plurality of clock gating circuits excludes clock pulses to said scan flip-flops corresponding to said another one of said plurality of clock gating circuits, in response to said gating setting data.