Patent ID: 7893723
Filing Date: 2011-02-22
Classification: H01L

Abstract:
1. A logic gate device, comprising: a plurality of input terminals; an output terminal; first and second voltage terminals; a plurality of P channel MOS transistors wherein a source of each P channel MOS transistor in the plurality of P channel MOS transistors is directly connected to the first voltage terminal, wherein a drain of each P channel MOS transistor in the plurality of P channel MOS transistors is directly connected to the output terminal and wherein a gate of each P channel MOS transistor in the plurality of P channel MOS transistors is respectively coupled to different ones of the input terminals; and a first N channel MOS transistor and a plurality of second N channel MOS transistors coupled together in a stack with source-drain paths in series between the second terminal and the output terminal, and with gates of the first and second N channel MOS transistors respectively coupled to different ones of the input terminals; with a drain of the first N channel MOS transistor directly connected to the output terminal; wherein the second N channel MOS transistors are power transistors having high threshold voltages at least two times greater than the threshold voltage of the first N channel MOS transistor; and the first N channel MOS transistor is a standard transistor with a standard threshold voltage.