Patent ID: 6549985
Filing Date: 2003-04-15
Classification: G06F

Abstract:
A data cache in an in-order single instruction issue microprocessor, the data cache comprising:a cache memory, for storing data; an address register, coupled to said cache memory, for supplying an address to said cache memory; at least one buffer, for storing state information regarding a plurality of instructions in the data cache upon detection of a stall condition in the in-order single-issue microprocessor; and control logic, coupled to said buffer and said cache memory, configured to detect said stall condition, to save in response thereto said state information in said buffer, and to determine during said stall condition whether data specified by one or more of said plurality of instructions is missing in said cache memory, wherein said control logic is further configured to restore an address in said address register based on said state information stored in said buffer, wherein said control logic restores said address prior to termination of said stall condition.