Patent ID: 6353365
Filing Date: 2002-03-05
Classification: G05F

Abstract:
An integrated current reference circuit, comprising:a first current mirror and a second current mirror, each current mirror having a respective controlling node and a respective controlled node, the controlling node of the first current mirror being connected to the controlled node of the second current mirror and vice-versa, wherein the first current mirror comprises a first FET and a second FET, said first and second FETs each having a respective source, gate and drain terminal, said second FET further having a substrate terminal, the first FET having its gate and drain terminals connected together in common and forming the controlling node of the first current mirror, and the second FET having its gate terminal connected in common with the commoned gate and drain terminals of the first FET; and voltage offset circuitry connecting the source terminals of the first and second FETs to a supply terminal; wherein the substrate of the first FET is connected to its source terminal; and wherein the substrate terminal of the second FET is directly connected to the supply terminal to modify a threshold voltage of the second FET.