Patent ID: 6329840
Filing Date: 2001-12-11
Classification: H03K

Abstract:
A circuit comprising:a first circuit comprising a first timing compensation device, configured to generate a first control signal and a second control signal in response to (i) a first input signal and (ii) an enable signal, wherein said first control signal matches said second control signal;a second circuit configured to generate a third control signal and a fourth control signal in response to (i) a second input signal and (ii) said enable signal, wherein said third control signal matches said fourth control signal;a first output driver circuit comprising a first PMOS output transistor and a first NMOS output transistor configured to generate a first output signal in response to said first and second control signals, wherein turn on/off timing of said first PMOS output transistor and said first NMOS output transistor are altered in response to said first timing compensation device; anda second output driver circuit comprising a second PMOS output transistor and a second NMOS output transistor configured to generate a second output signal in response to said third and fourth control signals.