Patent ID: 6131151
Filing Date: 2000-10-10
Classification: H04N

Abstract:
A system for managing a frame store memory for receiving and processing a substantially continuous incoming digital datastream, the system comprising:a sequencing memory for storing addresses for accessing the frame store memory;a write address counter for accessing the sequencing memory to write frame store addresses into the sequencing memory, each frame store address indicating a start address for storing an incoming slice of data from the datastream into the frame store memory;a read address counter for accessing the sequencing memory to read stored frame store addresses from the sequencing memory and to provide the frame store addresses to the frame store memory, each stored frame store address indicating a start address for processing a selected slice of data stored in the frame store memory;a status memory for maintaining a corresponding indication as free or busy for each one of a plurality of segments of memory space in the frame store memory, each segment of memory space starting at a corresponding starting address and sized for storing at least one slice of data from the incoming datastream;a first circuit for clearing the corresponding indication in the status memory to the free state after processing of the selected slice of data stored in the frame store memory is completed, thereby making the corresponding segment of memory space available for storing a new incoming slice of data from the datastream into the frame store memory;a second circuit for searching the status memory to identify a free segment of memory space and storing the corresponding frame store address in the sequencing memory to provide a start address for storing the new incoming slice of data from the datastream into the frame store memory;a frame size register for storing a frame size characteristic of the incoming datastream; anda lookup table for storing a series of frame store addresses, each frame store address corresponding to a segment of memory space sized for one slice of data based on the frame size characteristic of the incoming datastream, wherein the second circuit accesses the lookup table to provide frame store addresses to the sequencing memory.