Patent ID: 6560147
Filing Date: 2003-05-06
Classification: G01R,G11C

Abstract:
A digital circuit comprising:a scan chain including a plurality of pairs of a selector and a flipflop arranged in cascade, wherein the scan chain performs a capture mode in which in response to a scan enable signal the flipflop captures data from an internal circuit in synchronization with a predetermined clock and a shift mode in which in response to the scan enable signal, one of the data stored in the flipflop and test data input from outside is shifted to a subsequent flipflop in synchronization with the predetermined clock; a clock generator which generates a clock signal in response to one of the rising edge and the falling edge of the clock pulse of a clock signal input from outside as a trigger; and a clock selector which receives the clock signal input from outside and the clock signal generated by the clock generator, and selects one of the two clock signals in response to the scan enable signal for switching between the shift mode and the capture mode, and then feeds the selected clock signal to the clock input terminal of at least one flipflop forming the scan chain.