Patent ID: 8441865
Filing Date: 2013-05-14
Classification: G11C

Abstract:
1. An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material, the memory device including a plurality of sectors of memory cells each one being formed in a respective well of the chip and each sector including a plurality word lines each one for accessing a corresponding block of memory cells of the sector, wherein the memory device includes: a first biasing line of the wells and a second biasing line of the word lines, biasing means for providing a first bias voltage to the first biasing line and a second bias voltage to the second biasing line, selection means for selectively connecting the first biasing line to the well of at least one selected sector and for selectively connecting the second biasing line to at least one selected word line of each selected sector, first charge transfer means for bringing the first biasing line from the first bias voltage to a target voltage according to a pilot transient trend, the target voltage being comprised between the first bias voltage and the second bias voltage, second charge transfer means for bringing the second biasing line from the second bias voltage to the target voltage, wherein the second charge transfer means includes means for binding the second biasing line to bring itself from the second bias voltage to the target voltage according to a transient trend being scaled with respect to the pilot transient trend.