Patent ID: 7185043
Filing Date: 2007-02-27
Classification: G06F

Abstract:
1. An apparatus for adding a first value ‘A’ and a second value ‘B’, each including a plurality of bits, wherein bits in corresponding bit positions of said first value and said second value form respective columns, said apparatus comprising: a plurality of combiner units each configured to provide a generate and propagate bit pair in response to receiving respective bits of said first value and said second value which correspond to a plurality of said respective columns; a carry creation unit coupled to said plurality of combiner units and configured to create an ordered plurality of carry bits each corresponding to one or more of said generate and propagate bit pairs; and a plurality of summation units each configured to generate a plurality of sum bits in response to receiving said respective bits of said first value and said second value which correspond to said plurality of said respective columns, wherein a subset of said plurality of summation units is configured to generate a portion of said plurality of sum bits in response to receiving respective ones of said ordered plurality of carry bits; wherein each of said plurality of combiner units is configured to create a generate bit G