Patent ID: 6759299
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method of manufacturing a flash memory device comprising the steps of:(a) preparing a semiconductor substrate divided into a main cell region and a peripheral region, wherein the peripheral region is divided into a high-voltage region in which a high-voltage transistor will be formed and a low-voltage region in which a low-voltage transistor will be formed; (b) forming a device isolation film in the semiconductor substrate; (c) performing a ion implantation process for forming well and a ion implantation process for controlling threshold voltage for the substrate, thus forming a well region; (d) etching a polysilicon layer and a gate oxide film to form forming gates for the high-voltage transistor and the low-voltage transistor; (e) forming a mask in the main cell region so that the peripheral region is opened and then performing an ion implantation process directly into the semiconductor substrate for the high-voltage region and the low-voltage region, thus forming a double doped drain (DDD) low-concentration junction region; (f) forming spacers at sidewalls of the gates in the high-voltage region and the low-voltage region; and (g) forming a mask in the main cell region so that the peripheral region is opened and then performing an ion implantation process directly into the substrate under the spacers of the high-voltage region and the low-voltage region, thus forming double doped drain (DDD) high-concentration junction regions.