Patent ID: 6337807
Filing Date: 2002-01-08
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell for storing information; a select transistor connected to said memory cell; a select circuit for outputting a first signal for selecting said memory cell; a select line connected the gate of said select transistor; a select line control circuit for driving said select transistor, said select line control circuit outputting a second signal in accordance with said first signal and a operation mode of said memory cell; a first transistor having a current path whose one end is connected to said select line control circuit and other end is connected to the gate of said select transistor, said first transistor transferring the second signal to said select line; a first gate line connected to the gate of said first transistor; a first voltage control circuit for supplying a voltage to said first gate line to turn on or off said first transistor; a word line control circuit for driving a word line connected to the gate of said memory cell, said word line control circuit outputting a third signal; a second transistor having a current path whose one end is connected to said word line control circuit and other end is connected to the word line, said second transistor transferring the third signal to the word line; a second gate line connected to the gate of said second transistor, said second gate line being disconnected from said first gate line; and a second voltage control circuit for supplying a voltage to said second gate line to turn on or off said second transistor.