Patent ID: 9117110
Filing Date: 2015-08-25
Classification: G06K

Abstract:
1. A face detection processing circuit comprising: a down-scaler configured to scale down a resolution of an input image including at least one subject person according to a down-scaling ratio to provide a first image; a face detection unit configured to detect a face of the at least one subject person in the first image and configured to generate a coordinate information of a region of the detected face region; a control unit configured to calculate a face detection index indicating a ratio of the face region to the first image based on the coordinate information of the face region to provide control signals based on the face detection index and a face detection signal indicating whether a face is detected in the first image; and a down-scaling ratio controller configured to adjust the down-scaling ratio in response to the control signal; wherein the control unit is configured to calculate the face detection index based on a sum of the face region, a peak area of the face region and a number of the detected faces.