Patent ID: 6788740
Filing Date: 2004-09-07
Classification: H04N

Abstract:
A video decoder comprising:base layer circuitry capable of receiving compressed base layer video data; and enhancement layer circuitry capable of receiving enhancement layer video data associated with said compressed base layer video data; and a controller associated with said enhancement layer circuitry capable of receiving a quantization parameter associated with said compressed base layer video data and predicting therefrom at least one all-zero bit plane associated with at least one block of said enhancement layer video data, wherein said controller is capable of inserting said at least one all-zero bit plane into said enhancement layer video data, wherein said controller is capable of determining a second all-zero bit plane associated with said at least one block of said enhancement layer video data, based on an upper bound of said at least one block and a value of at least one previously received bit plane associated with said at least one block, wherein said controller is capable of inserting said second all-zero bit plane into said enhancement layer video data.