Patent ID: 7903448
Filing Date: 2011-03-08
Classification: G11C

Abstract:
1. A resistance random access memory (RRAM) in which a write operation writing data having a first state and a second state to a selected memory cell is performed through first and second write paths formed in mutually opposite directions, the memory comprising: a plurality of word lines; a plurality of bit lines; a memory cell array having a plurality of memory cells which are disposed at the intersections of the word and bit lines to form a matrix of rows and columns and each have an access transistor and a resistive memory device, wherein the resistive memory device is formed of SrZrO3 disposed between a top electrode and a bottom electrode; and a plurality of source lines each disposed between every two word lines and in the same direction as the word lines, and each connected to source terminals of corresponding access transistors having gate terminals connected to corresponding two word lines, wherein when the first state and the second state write operations are performed respectively, a selected source line voltage and a selected word line voltage are maintained equally, and the selected source line voltage during the first state and the second state write operations is a positive voltage.