Patent ID: 7385837
Filing Date: 2008-06-10
Classification: G11C

Abstract:
1. A memory device comprising: a first bit line disposed over a semiconductor body; a second bit line disposed over the semiconductor body; and a memory cell coupled to at least one of the first bit line and/or the second bit line, the memory cell including a programmable component having an electrical resistance that depends on a programming state, the programmable component comprising at least one first switching element, which has a control electrode coupled to a first word line, and also comprising at least one second switching element, which has a control electrode coupled to a second word line; wherein the at least one first switching element opens a first current path when the first word line is activated, said first current path leading from one of the first or second bit lines via the programmable component as far as a first potential terminal, and wherein the at least one second switching element opens a second current path when the second word line is activated, said second current path leading from one of the two bit lines as far as a second potential terminal.