Patent ID: 6806539
Filing Date: 2004-10-19
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:an SOI substrate having a surface semiconductor layer, a gate electrode formed on the surface semiconductor layer via a gate insulating film, first conductive type source/drain regions formed in the surface semiconductor layer on both sides of the gate electrode, a second conductive type drawing diffusion layer formed in the surface semiconductor layer and contacting at least one of the first conductive type source/drain regions, a silicide layer which is formed on the surface semiconductor layer to partially or entirely overlie both said at least one of source/drain regions and the drawing diffusion layer which are immediately adjacent one another and of different conductivity types, wherein the suicide layer is grounded so as to provide means for causing holes/electrons generated due to soft error and/or alpha-ray(s) to be drawn out of a second conductivity type channel region via the drawing diffusion layer and the silicide layer, wherein the channel and drawing diffusion layer are of the same conductivity type, and the drawing diffusion layer is located between the channel and the at least one source/drain region so that the drawing diffusion layer is immediately adjacent the channel.