Patent ID: 7304503
Filing Date: 2007-12-04
Classification: H03K,H04L

Abstract:
1. A repeater circuit comprising: an output; a plurality of transistors; and a plurality of switches operative in a first switch position and in a second switch position, wherein said transistors and said switches are coupled to form a plurality of subcircuits, wherein if said switches are in said first switch position said subcircuits are arranged into a high performance repeater mode including first and second long delay circuits and first and second short delay circuits, wherein said long delay circuits and said short delay circuits enable generation of a pulse at said output in response to an input edge transition, wherein in said high performance repeater mode said first and second short delay circuits bypass said first and second long delay circuits to speed up availability of said repeater circuit after a response to said input edge transition, and wherein if said switches are in said second switch position said subcircuits are arranged into a normal repeater mode.