Patent ID: 8589762
Filing Date: 2013-11-19
Classification: G06F,G11C

Abstract:
1. A method of correcting errors in a memory device comprising: providing a memory device including at least a plurality of memory blocks and an error correction logic (ECL) entry block including a set of error correction logic (ECL) entries, wherein said set of ECL entries includes a plurality of subsets of ECL entries, and each subset of ECL entries is configured to provide error correction for a different number of bits per memory block in one or more of said plurality of memory blocks, and each of said plurality of memory is configured to store a pointer to an ECL entry within said ECL block; detecting a writing error in an error-containing memory block among said plurality of memory blocks; locating an available ECL entry in said ECL entry block; and storing an address of said available ECL entry in a pointer of said memory block and storing information for correcting all write errors in said error-containing memory block in said available ECL entry, wherein said ECL entry block includes a plurality of at least one occupancy bit, wherein each of said plurality of at least one occupancy bit is configured to indicate availability of a corresponding ECL entry for storing information for correcting write errors in a memory block.