Patent ID: 6781400
Filing Date: 2004-08-24
Classification: G01R

Abstract:
A method of testing plural semiconductor integrated circuit devices by using a burn-in board,the method comprising the steps of: mounting the semiconductor integrated circuit devices on the burn-in board, and simultaneously testing the plural semiconductor integrated circuit devices for electric characteristics by applying a voltage to respective testing electrodes of the plural semiconductor integrated circuit devices from a common voltage supply line via plural PTC elements on the burn-in board so as to perform a simultaneous burn-in process, and preventing voltage application to the testing electrode of a defective one out of the plural of semiconductor integrated circuit devices that allows excessive currents to flow thereinto, wherein the prevention of voltage application results from an increase in resistance of one of the plural PTC elements electrically connected with the defective semiconductor integrated circuit device, which follows a temperature increase thereof caused by the excessive current-flow into the defective semiconductor integrated circuit device.