Patent ID: 6604175
Filing Date: 2003-08-05
Classification: G06F

Abstract:
A memory system comprising:a memory configured to store a plurality of data packets, the data packets being associated with a plurality of data types; a memory controller coupled to the memory, the memory controller being configured to receive requests for data packets from a processing unit and pass requested data packets from the memory to the processing unit; and a cache coupled to the memory controller, the cache comprising a plurality of independently cached areas, the memory controller being configured to pass requested data packets from the memory to the cache, the memory controller being configured to pass requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller, the memory controller being configured to assign each independently cached area in the cache to store data packets associated with one data type, each independently cached area being associated with a data usage indicator, the memory controller being configured to (1) increment the data usage indicator of an independently cached area for each data packet passed from that independently cached area to the processing unit in response to a subsequent data packet request and (2) decrement the data usage indicators of other independently cached areas.