Patent ID: 8295101
Filing Date: 2012-10-23
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of sense amplifiers, each retaining in a volatile manner data from a memory cell sensed; a data bus; a plurality of transistors selectively causing said plurality of sense amplifiers to be electrically connected with said data bus, in accordance with an input address, respectively; a write amplifier connected to said data bus; an external terminal outputting data from said memory cell to an outside of said semiconductor device via said sense amplifier, said transistor, and said data bus in a first operation mode, said external terminal providing data externally supplied from an outside of said semiconductor device to said sense amplifier via said write amplifier, said data bus, and said transistor in a second operation mode; a mask mode in which data supplied from an outside of said semiconductor device via said external terminal is not outputted to said sense amplifier in said second operation mode; and a control circuit supplying an electric potential to a gate electrode of a first transistor of said transistors that is turned electrically conductive, in accordance with said input address, said electric potential being different depending on said first operation mode or said second operation mode, wherein, in said first operation mode, said control circuit supplies a first electric potential to said gate electrode of said first transistor, so that said first transistor has a first impedance value in a conductive state thereof, in said second operation mode, said control circuit supplies a second electric potential to said gate electrode of said first transistor, so that said first transistor has a second impedance value in a conductive state thereof, an absolute value of said second impedance value being lower than that of said first impedance value, and said control circuit further supplies said gate electrode of said first transistor, to which said mask mode is asserted, with a third electric potential less than said second electric potential, so that said first transistor has a third impedance value, an absolute value of said third impedance value being higher than that of said second impedance value.