Patent ID: 7671966
Filing Date: 2010-03-02
Classification: G03F

Abstract:
1. A highly parallel data bus architecture for operating a digitally programmable image transducer having an array of microelements that can be divided into in 2 n −1 columns and an associated image transducer memory array comprised of memory cells corresponding to respective microelements for storing a bit of pattern data that determines the microelement state, the architecture comprising: a) n memory arrays, where n is an integer greater than or equal to 2, with each memory array capable of storing a low-resolution pattern to be formed onto the microelement array; b) a parallel data bus electrically connecting the memory arrays to the image transducer memory array; c) one or more data bus switches within the data bus allowing the data transfer from any one of the n memory arrays to be switched to the image transducer memory array; and d) a memory control unit electrically connected to the n memory arrays and the one or more data bus switches, programmed such that 2