Patent ID: 7962880
Filing Date: 2011-06-14
Classification: G06F

Abstract:
1. A method for forming wires in a bus in an integrated circuit device minimizing coupling capacitance between wires in an array of wires in said bus connected between as output terminal array and an input terminal array, with each of said wires including an output section of said wire connected from an output terminal in said output terminal array to a transverse section of said wire connected to an input section of said wire connected to an input terminal in said input terminal array, formed by the steps as follows: forming said array of wires in said bus with said output sections and said input sections both arranged in said given sequence in said bus with said bus connecting between said output terminal array and said input terminal array; forming each said output section of said wires in said bus extending in parallel with each other and each said input section of said wires in said bus extending in parallel with each other; forming said transverse sections of said wires with at least one of said wires in said bus including a said transverse section crossing over a separate one of said wires in said bus and including a said input section re-crossing over an input section of said separate one of said wires in said bus so that at least one pair of wires with juxtaposed output sections and juxtaposed input sections have transverse sections separated by said one other of said wires in said sequence, and with said transverse sections extending in parallel with others of said transverse sections; and shifting the connections of said wires in said bus between said output terminal array and said input terminal array while retaining the sequence of wires from first to last ones of said output terminals to first to last ones of said input terminals; whereby aside from said first and last wires in said arrangement, said coupling capacitance across said bus is uniform.