Patent ID: 6593780
Filing Date: 2003-07-15
Classification: G06F

Abstract:
A circuit for selectively generating an output signal (CLK_OUT) from one or more input clock signals (CLK_SRC1, . . . , CLK_SRC_n), the circuit comprising:A) a multiplexer (MUX) having a plurality of inputs for the input clock signals, a control input for a signal (CFG_i) for selecting one of the input clock signals, and a multiplexer output for supplying the selected input clock signal (MUX_OUT); B) a signal latch (LATCH) arranged between the multiplexer output and the output of the circuit, in which the connection line to the multiplexer output comprises a switch (S); C) a switching logic (FSM) with a control input for an external clock selection signal (CFG), signal inputs for the signal (MUX_OUT) of the multiplexer output and the output signal (CLK_OUT) of the circuit, a clock input for a logic clock signal (FCLK), and a control output which is connected to the control input of the multiplexer, and a disable signal output which is connected to the switch (S), the switching logic being adapted in such a way that it opens the switch (S) when the signal (CFG) at its control input changes, subsequently passes on the changed signal (CFG) from its control input to its control output, and closes the switch (S) again when the output signal (MUX_OUT) at the multiplexer output has changed at least once and is equal to the output signal (CLK_OUT) of the circuit.