Patent ID: 8975919
Filing Date: 2015-03-10
Classification: H01L,H03K

Abstract:
1. An integrated circuit comprising: a substrate having circuitry including a bus; a core logic arranged for communication with the circuitry; a dual row I/O comprising a first plurality of I/O cells and a second plurality of I/O cells arranged in general alignment in relation to one another; a physical layer (PHY) logic arranged for communication with the dual row I/O and situated between the first plurality of I/O cells and the second plurality of I/O cells; and a first set of communication interconnects arranged between the first plurality of I/O cells and the PHY logic and a second set of communication interconnects arranged between the second plurality of I/O cells and the PHY logic, wherein each of the first set and the second set of communication interconnects are the same length.