Patent ID: 7836253
Filing Date: 2010-11-16
Classification: G06F

Abstract:
1. A cache memory arranged between a processor and a low-speed memory and performing a pipeline processing of a memory access made by the processor, comprising: a data memory being configured to store data corresponding to a subset of data stored in the low-speed memory; a tag memory being configured to store tag addresses corresponding to the data stored in the data memory; a hit decision unit being configured to decide whether there is a cache hit or a miss hit by comparing at least one tag address, acquired by searching the tag memory using an index address included in an input address supplied from the processor, with a tag address included in the input address; a latch circuit being configured to hold the tag address included in the input address supplied from the processor; a bypass circuit comprising a bypass line and a selector for selectively inputting the tag address held in the latch circuit to an input of the hit decision unit by bypassing the tag memory; and a controller being configured to control an update process of the tag memory by rewriting a tag address, corresponding to one of said at least one tag address and stored in the tag memory, with the tag address included in the input address, an update process of the data memory with data corresponding to the input address by reading out of the data corresponding to the input address from the low-speed memory, and a behavior of the bypass circuit so that the tag address held in the latch circuit is an input to the hit decision unit by bypassing the tag memory, when the hit decision result is the miss hit.