Patent ID: 8645665
Filing Date: 2014-02-04
Classification: G06F

Abstract:
1. A processor comprising: multiple processing cores; and memory management logic coupled to the multiple processing cores, the memory management logic operable to translate a guest virtual address to a first guest physical address and to translate the first guest physical address to a first host physical address in response to a memory access request including the guest virtual address, the memory management logic comprising: a first translation table base register to store a first base address, the first base address referencing a first level of a first multilevel translation table in memory, the first multilevel translation table providing a mapping of guest virtual addresses to guest physical addresses; a second translation table base address register to store a second base address, the second base address referencing a first level of a second multilevel translation table in memory, the second multilevel translation table providing a mapping of guest physical addresses to host physical addresses; and address translation logic coupled to the first translation table base register and to the second translation table base register, the address translation logic operable to access the second multilevel translation table to translate guest physical addresses formed during a walk of the first multilevel translation table to host physical addresses.