Patent ID: 9202901
Filing Date: 2015-12-01
Classification: H01L

Abstract:
1. A method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, comprising at least the following steps: 6.1 forming a Si epitaxial layer of a first conduction type and forming a local dielectric region in the resulting Si epitaxial layer, wherein a portion of the Si epitaxial layer in which the local dielectric region is not formed forms a Si collector region; 6.2 forming a base region of a second conduction type on the resulting structure of the step 6.1, forming a monocrystalline base region on top of the Si collector region, and forming a polycrystalline base region on top of the local dielectric region, wherein the base region is a composite layer consisting of Si and SiGe; 6.3 depositing or sputtering a first metal layer; 6.4 depositing a first silicon oxide layer; 6.5 selectively removing middle portions of the first silicon oxide layer and the first metal layer in sequence to form a first window which exposes the middle portion of the surface of the monocrystalline base region; 6.6 depositing a second silicon oxide layer; 6.7 depositing a silicon nitride layer and then forming a silicon nitride inner sidewall at the inner edge of the first window through an anisotropic etching process; 6.8 removing portions of the second silicon oxide layer which are not covered by the silicon nitride inner sidewall to form an emitter-base spacer dielectric region composed of a liner silicon oxide layer and the silicon nitride inner sidewall, opening an emitter window enclosed by the emitter-base spacer dielectric region to expose the middle portion of the surface of the monocrystalline base region; 6.9 depositing a polysilicon layer and heavily doping the polysilicon layer into a polysilicon layer of the first conduction type; 6.10 forming a protection layer on the polysilicon layer and then etching off portions of the polysilicon layer and the first silicon oxide layer which are not masked by the protection layer to form a heavily doped polysilicon emitter region of the first conduction type; 6.11 implanting ions of the second conduction type into the resulting structure of the step 6.10 to form a heavily doped monocrystalline base region and a heavily doped polycrystalline base region of the second conduction type by using the protection layer as a mask, and then removing the protection layer; 6.12 enabling the first metal layer to make a silicification reaction with the heavily doped polycrystalline base region, the heavily doped monocrystalline base region and a portion of the monocrystalline base region, which are in contact with the first metal layer, respectively, to obtain a base-region low-resistance metal silicide layer; and diffusing the impurities in the heavily doped polysilicon emitter region of the first conduction type formed in the step 6.10 outwards and downwards via the emitter window to form a heavily doped monocrystalline emitter region of the first conduction type; and 6.13 depositing a contact hole dielectric layer, forming contact holes, and leading out an emitter metal electrode and a base metal electrode.