Patent ID: 6975153
Filing Date: 2005-12-13
Classification: H03K

Abstract:
1. A hysteresis circuit, comprising: first, second, third, fourth and fifth CMOS transistors; sixth, seventh, eighth, ninth and tenth CMOS transistors of a type complementary to the first five CMOS transistors; an input terminal coupled to gates of said first, second, sixth and seventh CMOS transistors for applying an input signal; an output terminal coupled with gates of said fourth and ninth CMOS transistors, and with drains of said fifth and tenth CMOS transistors for generating an output signal; a first resistor coupled with sources of said seventh and ninth CMOS transistors, and source of said seventh CMOS transistor being connected to drain of said ninth CMOS transistor; a second resistor coupled with sources of said second and fourth CMOS transistors and to ground, and drain of said fourth CMOS transistor being connected to source of said second CMOS transistor; drain of said second CMOS transistor being connected to sources of said first and third CMOS transistors; gates of said third, fifth, eighth and tenth CMOS transistors being interconnected, and being connected to drains of said first and sixth CMOS transistors; and sources of said sixth and eighth CMOS transistors being interconnected, and drain of said eighth CMOS transistor and source of said fifth CMOS transistor being connected to ground.