Patent ID: 7342273
Filing Date: 2008-03-11
Classification: H01L

Abstract:
1. Intermediate active transistor structures for a semiconductor memory device comprising: transistor gates having generally vertical sidewalls in a memory array section and in periphery sections; n-type dopants in n-channel devices and p-type conductive dopants in p-channel devices at a first level of exposed silicon regions defined as active area regions of the transistor gates; spacers on the generally vertical sidewalls of the transistor gates having a thickness that is less than half the spacing between the transistor gates in the memory array section; epitaxial silicon completely covering the exposed silicon regions to form epitaxial silicon extension regions; and n-type source/drain regions of n-channel devices and p-type source/drain regions of p-channel devices at a second level of the exposed silicon regions and the epitaxial silicon extension regions.