Patent ID: 7236028
Filing Date: 2007-06-26
Classification: H03L

Abstract:
1. A delay-locked loop circuit receiving an input clock signal and generating an output clock signal whose delay is locked to the input clock, the circuit comprising: a voltage controlled delay line comprising a plurality of delay elements, the voltage controlled delay line receiving the input clock signal and generating a plurality of delayed clock signals having increasing amount of phase delay from a first delayed clock signal to a last delayed clock signal, the plurality of delay elements being controlled by a control voltage operative to vary the amount of phase delay provided by each delay element; a multiplexer receiving the plurality of delayed clock signals as input signals and also receiving a select signal, the multiplexer providing a selected one of the delayed clock signals as an output signal based on the select signal, the output signal of the multiplexer being the output clock signal; a phase detection control loop adapted to measure the phase difference between the input clock signal and the output clock signal and to generate the control voltage to adjust the amount of delay provided by each delay element in the voltage controlled delay line; and a phase selection control loop adapted to measure the voltage level of the control voltage and, based on the voltage level of the control voltage, to generate the select signal for the multiplexer to cause the multiplexer to select a delayed clock signal with an increased or decreased amount of phase delay relative to the currently selected delayed clock signal or to hold the currently selected delayed clock signal.