Patent ID: 6044390
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A system for performing a binary multiplication operation between first and second field elements in a Galios field including field elements, said system comprising:means for restructuring a mathematical representation of said first field element dependent on whether said first field element has one of an associated odd and even bit length;means for determining a zero-padded field element for adding to said restructured mathematical representation of said first field element to obtain a modified first field element;means for recursively structuring a multiplication operation between said modified first field element and said second field element to obtain a recursive mathematical representation of said multiplication operation, said recursive mathematical representation having an odd set of coefficients and an even set of coefficients and having an associated highest order coefficient;first shift registers for storing said odd set of coefficients during a first clock cycle, wherein said odd coefficients are serially outputted from said first register one coefficient per clock cycle;second shift registers for storing said even set of coefficients during said first clock cycle, wherein said even coefficients are serially outputted from said first register one coefficient per clock cycle;third register for storing second coefficients associated with said second field element during said first clock cycle, said second coefficients being parallely outputted from said third register;destination register for being preloaded with one of a zero value and said associated highest order coefficient at the beginning of said first clock cycle and for storing a current resultant logic operation value subsequent to said beginning of said first clock cycle;means for performing logic operations in at least one clock cycle with said first and second coefficients, at least one constant value, and a currently stored value in said destination register to obtain in each of said at least one clock cycle said current resultant logic operation value for each of said at least one clock cycle;storing said new current resultant logic operation value in said destination register for said each clock cycle.