Patent ID: 6656824
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of forming a sub-0.1 &mgr;m channel length MOSFET which comprises the steps of:forming a planar structure comprising a Si-containing substrate, a sacrificial oxide layer located atop a surface of said Si-containing substrate, a patterned polysilicon region located atop a portion of said sacrificial oxide layer and a dielectric material abutting said patterned polysilicon region; removing said patterned polysilicon region to provide an opening exposing a portion of said sacrificial oxide layer and implanting ions into said Si-containing substrate to form a device channel/body implant region, said device channel/body implant region having a length less than 0.1 &mgr;m; forming Si spacers on exposed vertical sidewalls of said dielectric material; removing said exposed portion of sacrificial oxide layer utilizing a chemical oxide removal etch to expose a surface of said Si-containing substrate; forming a gate dielectric on the exposed surface of said Si-containing substrate and oxidizing said Si spacers; forming a recessed poly-gate region in said gate dielectric, said recessed poly-gate having an oxide layer on an upper surface thereof; laterally etching said oxidized Si spacers and portions of said dielectric material which are above said recessed poly-gate to provide an area which is wider than said recessed poly-gate; forming a gate conductor in said area and removing remaining dielectric material; and forming nitride spacers on exposed vertical sidewalls of said recessed poly-gate that are beneath said gate conductor.