Patent ID: 6031408
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A square-law clamping circuit comprising:a first MOS transistor having a source for receiving a reference voltage, a gate, and a drain coupled to said gate of said first MOS transistor;a current source having a first terminal coupled to said drain of said first MOS transistor, and a second terminal coupled to a power supply voltage terminal, for conducting a predetermined current therethrough;a second MOS transistor having a source providing an input/output terminal, a gate coupled to said drain of said first MOS transistor, and a drain;a third transistor having a first current electrode coupled to said drain of said second MOS transistor, a control electrode coupled to said first current electrode of said third transistor, and a second current electrode coupled to said power supply voltage terminal; anda fourth transistor having a first current electrode for providing an output terminal of the square-law clamping circuit, a control electrode coupled to said first current electrode of said third transistor, and a second current electrode coupled to said power supply voltage terminal.