Patent ID: 6417544
Filing Date: 2002-07-09
Classification: H01L

Abstract:
A semiconductor device protection structure on a substrate to protect active devices from plasma charge induced damage comprising:a first doped region extending down from the surface of said substrate; an insulating layer for structure element isolation; a plurality of doped second regions within said first doped region; a doped third region within said substrate and adjacent to said first doped region; a doped fourth region within said substrate of opposite doping than said substrate; a thin insulation layer covered with a crystalline conducting layer on said substrate surface over the area between said third and fourth doped regions; a first metal conductor element one end of which is connected to said crystalline conducting layer with shape geometry conducive to process charge accumulation and which other end is connected to one said second doped regions; a second metal conductor element connecting said fourth doped region with said active device input pad; a third metal conductor element connecting said doped third region with one said doped second region closest to said third doped region and to a second voltage source; a top passivation layer covering said structure.