Patent ID: 7569435
Filing Date: 2009-08-04
Classification: H01L

Abstract:
1. A method of manufacturing a source-gated transistor, including: (a) providing a transparent substrate; (b) depositing a gate layer and patterning the gate layer to form a gate; (c) depositing a gate insulating layer; (d) depositing a thin film semiconductor layer; (e) depositing a transparent source layer defining a barrier with the semiconductor layer, using a step of back exposure through the substrate using the gate as a mask to define the barrier between source layer and the semiconductor layer; (f) depositing a positive photoresist layer; (g) exposing the positive photoresist layer through the transparent substrate and source layer using the gate as a mask to pattern the photoresist in self-alignment with the gate; (h) etching the transparent source layer to form a source region using the pattern defined directly or indirectly by the photoresist layer; (i) forming spacers at the edge of the source region; and (j) implanting dopants into drain regions of the semiconductor layer using the source region and spacers as a mask to form highly doped drain regions spaced from the source region by the width of the spacers.