Patent ID: 6211044
Filing Date: 2001-04-03
Classification: H01L

Abstract:
A process for fabricating a semiconductor device comprising the steps of:providing a semiconductor substrate having a gate layer overlying the semiconductor substrate and separated therefrom by a gate dielectric layer;forming an etch-stop layer overlying the gate layer;forming a composite hard-mask overlying the etch-stop layer,wherein the composite hard-mask includes a metal layer overlying the etch-stop layer and a reaction resistant layer overlying the metal layer, andwherein the hard-mask has a first length;forming a silicon layer overlying the composite hard-mask;reacting the metal layer and the silicon layer to form metal silicide regions, and leaving a residual metal layer having a second length,wherein the second length is less than the first length;removing the reaction resistant layer; andremoving portions of the metal etch-stop layer and the gate layer exposed by the residual metal layer.