Patent ID: 8595532
Filing Date: 2013-11-26
Classification: G06F,Y02D

Abstract:
1. An automatic power saving system for decreasing power demand during a power interruption while maintaining an appearance of full operation of a signal processor to an external device, the signal processor including predetermined power consuming circuits, a communications interface, and a state machine, comprising: a supply monitor for sensing when a power supply interruption during operation has occurred; a clock generator for providing a clock signal; a clock gate circuit interconnected between said clock generator and said predetermined power consuming circuits; and a response control circuit responsive to said supply signal for operating said clock gate circuit to halt the clock signal to said predetermined power consuming circuits during a sensed power interruption, the clock signal being provided to said power consuming circuits and said communication interface during full operation; said clock generator providing a clock signal to said communications interface regardless of the sensed power interruption for maintaining the appearance of full operations of the signal processor to the external device during the sensed power interruption.