Patent ID: 7440534
Filing Date: 2008-10-21
Classification: H03K

Abstract:
1. A counter characterized by comprising: n (n is an integer: n≧2) trigger flip-flops, each of said trigger flip-flops comprising: a master latch which writes and holds input data; and a slave latch which is connected to said master latch to write and hold the data held in said master latch complementarily to an operation of said master latch and output the held data, wherein said master latch comprises: a first inverter circuit; a second inverter circuit which has an input terminal connected to an output terminal of said first inverter circuit and an output terminal connected to an input terminal of said first inverter circuit; a first transistor of a first conductivity type which has one of input and output terminals connected to the output terminal of said first inverter circuit; a second transistor of the first conductivity type which has one of input and output terminals connected to the other of the input and output terminals of said first transistor; a third transistor of the first conductivity type which has one of input and output terminals connected to the output terminal of said second inverter circuit; a fourth transistor of the first conductivity type which has one of input and output terminals connected to the other of the input and output terminals of said third transistor; and a power supply which is connected to the other of the input and output terminals of each of said second transistor and said fourth transistor, a clock signal is commonly supplied to a control terminal of each of said first transistor and said third transistor, a first input signal is supplied to a control terminal of said second transistor, a second input signal having a polarity opposite to the first input signal supplied to the control terminal of said second transistor is supplied to a control terminal of said fourth transistor, said slave latch comprises: a fifth transistor of a second conductivity type which has one of input and output terminals connected to the output terminal of said first inverter circuit; a seventh transistor of the first conductivity type which has one of input and output terminals connected to the other of the input and output terminals of said fifth transistor; a sixth transistor of the second conductivity type which has one of input and output terminals connected to the output terminal of said second inverter circuit; and an eighth transistor of the first conductivity type which has one of input and output terminals connected to the other of the input and output terminals of said sixth transistor, the clock signal supplied to the control terminal of each of said first transistor and said third transistor is commonly supplied to a control terminal of each of said fifth transistor and said sixth transistor, said one of the input and output terminals of said eighth transistor is connected to a control terminal of said seventh transistor, said one of the input and output terminals of said seventh transistor is connected to a control terminal of said eighth transistor, said power supply is connected to the other of the input and output terminals of each of said seventh transistor and said eighth transistor, the control terminal of said second transistor is connected to said other of the input and output terminals of said fifth transistor, and the control terminal of said fourth transistor is connected to said other of the input and output terminals of said sixth transistor, and a signal from one of said one and said other of the input and output terminals of said sixth transistor in a (k−1)th (k is an integer: 2≦k≦n) trigger flip-flop of a preceding stage is supplied to a kth trigger flip-flop as the clock signal.