Patent ID: 6927589
Filing Date: 2005-08-09
Classification: G01R,H05K

Abstract:
1. A bump substrate for use during the testing of a semiconductor die having a plurality of bond pads on a surface thereof, each bond pad of said plurality having a raised contact bump thereon extending above said surface of said semiconductor die comprising: a bump substrate having a plurality of contact bump receiving sites formed therein corresponding to a pattern of said plurality of bond pads on said semiconductor die, each of said plurality of contact bump receiving sites having a plurality of sidewalls and a bottom and having a plurality of conductive traces located on at least portions of said plurality of sidewalls thereof for contacting a plurality of conductive traces on said bump substrate and for contacting a corresponding contact bump of said contact bumps on said plurality of bond pads received at said plurality of contact bump receiving sites, at least one conductive trace of said plurality of conductive traces extending along at least a portion of a sidewall of said plurality of sidewalls of a contact bump receiving site of said plurality of contact bump receiving sites and at least one other conductive trace of said plurality of conductive traces extending along at least a portion of another sidewall of said plurality of sidewalls and a portion of said bottom of said contact bump receiving site of said plurality of contact bump receiving sites, said plurality of conductive traces forming an array of a plurality of rows and a plurality of columns interconnecting each contact bump receiving site of said plurality of contact bump receiving sites to at least one adjacent contact bump receiving site of said plurality of contact bump receiving sites in an adjacent row of the plurality of rows and an adjacent column of the plurality of columns.