Patent ID: 7492847
Filing Date: 2009-02-17
Classification: H03M

Abstract:
1. A clock generation system for automatically generating a sampling signal and a holding signal to an analog front end circuit, the analog front end circuit transforming an analog signal outputted from an image sensor into a digital signal according to the sampling signal and the holding signal, the clock generation system comprising: a clock generator generating a plurality of clock signals according to a reference signal; and a comparing module receiving the plurality of clock signals, the comparing module comparing the analog signal with a first level signal generated by the image sensor and outputting a first comparison signal to the clock generator, the comparing module further comparing the digital signal with a second level signal and outputting a second comparison signal to the clock generator; wherein the clock generator selectively outputs a first clock signal, corresponding to the first comparison signal, of the plurality of clock signals as the sampling signal when the first comparison signal received by the clock generator is at a high state, the clock generator further selectively outputs a second clock signal, corresponding to the second comparison signal, of the plurality of clock signals as the holding signal when the second comparison signal received by the clock generator is at the high state.