Patent ID: 9177641
Filing Date: 2015-11-03
Classification: G11C

Abstract:
1. A memory device comprising: a memory cell comprising a variable resistance; a sense amplifier comprising a first input and a second input, the sense amplifier outputting a signal in accordance with a difference between the first and second inputs, and being selectively coupled at the second input to the memory cell; a resistor in a first path between the first input of the sense amplifier and a ground node; and a second path comprising the memory cell between the second input of the sense amplifier and the ground node, wherein the resistor has a value between a first resistance of the second path including the memory cell holding first data and a second resistance of the second path including the memory cell holding second data, and wherein the resistor comprises one of a gate resistance, a diffusion layer resistor, a metal resistor, a transistor resistor, and a combination thereof.