Patent ID: 6057218
Filing Date: 2000-05-02
Classification: H01L

Abstract:
A method for simultaneously manufacturing a poly gate and a polycide gate on an integrated circuit chip, comprising the steps of:preparing a gate oxide layer;depositing a polysilicon layer on the gate oxide layer;depositing a silicide layer;preparing a protective layer;patterning a polycide gate photoresist in a region whereto the polycide gate is going to produce;removing the protective layer not covered by the polycide gate photoresist;removing the silicide layer not covered by the polycide gate photoresist;patterning a poly gate photoresist in a region whereto the poly gate is going to produce;removing the polysilicon layer not covered by the poly gate photoresist and the protective layer; andremoving the poly gate photoresist to form the poly gate and the polycide gate.