Patent ID: 7587696
Filing Date: 2009-09-08
Classification: G06F,H01L

Abstract:
1. A semiconductor device that includes wiring in which signals are carried between elements of the semiconductor device and in which said semiconductor device is constructed in accordance with a minimum wiring spacing requirement, comprising: a first wiring provided in a first layer; a second wiring provided in said first layer and arranged parallel to said first wiring; a third wiring provided in said first layer, arranged parallel to said first and second wirings, and disposed between said first wiring and said second wiring so that a space between said first wiring and said third wiring is larger than a space between said second wiring and said third wiring; a fourth wiring provided in a second layer; and a via interconnecting said third wiring and said fourth wiring, said via having a larger width than said third wiring; wherein a center point of said via is disposed at a location offset from a longitudinal center axis of the third wiring in direction toward said first wiring, wherein the minimum wiring spacing requirement for said semiconductor device is maintained by having the center point of said via disposed at the location offset from the longitudinal center axis of the third wiring in direction toward said first wiring, and wherein a size of said via is not changed to a smaller size.