Patent ID: 8409883
Filing Date: 2013-04-02
Classification: H01L

Abstract:
1. A method for fabricating a phase change memory, comprising: providing a substrate including a storage substrate and a peripheral substrate; forming a sacrificial dielectric layer on the peripheral substrate; etching the storage substrate and forming an N-type ion buried layer on the storage substrate; forming a plurality of vertical LEDs on the N-type ion buried layer, wherein a top of a P-type conductive region is substantially flush with a top of the peripheral substrate; removing the sacrificial dielectric layer from the peripheral substrate; forming a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and forming a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, the storage STI units having thickness equal to thickness of the plurality of vertical LEDs, and the plurality of peripheral STI units having thickness equal to thickness of the plurality of storage STI units; and forming a plurality of phase change layers on the plurality of vertical LEDs and between the plurality of storage STI units, and forming a plurality of MOS transistors on the peripheral substrate and between the plurality of peripheral STI units.