Patent ID: 9164905
Filing Date: 2015-10-20
Classification: G06F,Y02D

Abstract:
1. A method of controlling a semiconductor integrated circuit device, said semiconductor integrated circuit device comprising a cache which includes a first storage device, and a second storage device having a type different from that of said first storage device, said cache being interposed between a processor and a memory and being connected to the processor and the memory, and said cache being configured to cache therein data of the memory, and said first storage device being configured to operate at a voltage below the lower limit voltage at which said second storage device is configured to operate, said method comprising: supplying a first source voltage and a second source voltage independently to said first storage device and said second storage device, respectively, said first source voltage being lower than said second source voltage; operating, by a control unit for controlling said semiconductor integrated circuit device, switchable controls between a first mode allowing only said first storage device of said cache to operate, and a second mode allowing said first storage device or said second storage device of said cache to operate; operating, in said first mode, by a power supply unit, to the first source voltage which is set lower than the lower limit voltage at which said second storage device of said cache is configured to operate, to said first storage device of said cache, while, by said control unit, interrupting power supply to said second storage device of said cache from said power supply unit; and said control unit, in said first mode, accessing said first storage device of cache in accordance with a request to access the data in the memory from the processor, and in said second mode, accessing at least one of said first storage device and said second storage device of said cache in accordance with the request to access the data in the memory from the processor.