Patent ID: 8841774
Filing Date: 2014-09-23
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first wiring; a second wiring which is arranged under the first wiring; and a first via which is formed between the first wiring and the second wiring and electrically connects the first wiring and the second wiring, wherein: in a planar view, the first wiring comprises: the bending portion, the first wiring region and the second wiring region are formed on a same layer, in a planar view, the first via is formed in the first wiring region so as not to overlap with a region of the bending portion, a length of the first via in the first direction is longer than a length of the first via in the second direction, and both ends of the first via in the second direction are overlapped with both ends of the first wiring region in the second direction.