Patent ID: 7903446
Filing Date: 2011-03-08
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: word lines; bit lines; plate lines; sub-bit lines connected to the bit lines; ferroelectric capacitors each including a ferroelectric substance between two electrodes; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line or functioning as the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and a plurality of memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors of the memory cells are connected to the plate lines, the other electrode of the ferroelectric capacitor of each of the memory cells is connected to one of the sub-bit lines, a source and a drain of the block selection transistor in each memory cell block are connected to one of the sub-bit lines and one of the bit lines, respectively, a source of the reset transistor in each memory cell block is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and a plurality of the memory cell blocks configure a memory cell array, wherein during a standby period when a data read operation or a data write operation is not performed, the cell transistors are in an on state, the reset transistors are in an on state, and the block selection transistors are in an off state, and in a memory cell block selected from the memory cell blocks during a data read operation or a data write operation, the reset transistor in the selected memory cell block is in an off state, the block selection transistor in the selected memory cell block is in an on state, and the cell transistor of a selected one of the memory cells in the selected memory cell block is in an on state.