Patent ID: 6658446
Filing Date: 2003-12-02
Classification: G06F

Abstract:
Chainable adder receiving three bits A, B, C to give two complementary sum outputs (SO, SO*) and two complementary carry outputs (CO, CO*) comprising:a first stage having three differential pairs P1, P2, P3 each receiving a respective bit A, B, C and its complement A*, B*, C*, the three pairs having common output arms and being each powered by an identical current I, the output arms each comprising three resistors R1, R2, R3 and R4, R5, R6 in series connected to a reference potential (M), these resistors defining three intermediate nodes A1, A2, A3 in a first arm of the output arms, B1, B2, B3 in a second arm of the output arms, the carry outputs being taken at the nodes A2 and B2, a second stage comprising three other differential pairs P4, P5, P6 whose inputs are connected to the nodes A1 and B3 for the pair P4, A2 and B2 for the pair P5 and A3 and B1 for the pair P6, the pairs P4 and P6 each having a common arm with the pair P5 and an arm that is not common, the sum outputs of the adder stage being each constituted by a combination, according to an â€œORâ€  function, of logic states appearing respectively on the non-common arm of one of the pairs P4 and P6 and on the common arm of the other pair.