Patent ID: 6178139
Filing Date: 2001-01-23
Classification: G11C

Abstract:
A semiconductor memory device comprising:a controlling means to control the timing of operating a memory section and supplying an address to said memory section in response to an external command;an address outputting means to generate an address output using an external address input to be outputted to said memory section in accordance with a controlling signal fed from said controlling means; anda column control means to start outputting a write operation controlling signal and a read operation controlling signal to be fed to said memory section in response to an operation instructing signal given by said controlling means;whereby said controlling signal comprises a first controlling signal after a first period following an inputting of a read command, and a second controlling signal after a second period following an inputting of a write command and whereby said operation instructing signal to be fed to said column control means is generated in accordance with said first and second controlling signals; andsaid address outputting means delays an input address by said first and second periods and outputs an address delayed bN, said first period as a read address in accordance with said first controlling signal and said address delayed by said second period as a write address in accordance with said second controlling signal.