Patent ID: 9030893
Filing Date: 2015-05-12
Classification: G11C

Abstract:
1. A memory circuit, comprising: a memory bit cell circuit including a bit cell core, a local write bitline, a local write bitline bar, and a local power supply node for providing power to the bit cell core; a memory cell supply capacitor configured to capacitively load the local power supply node; a write assist driver circuit, the write assist driver circuit including: a head switch configured to couple the local power supply node to a global power supply node; a first switch configured to couple the local power supply node to the local write bitline responsive to a write bit to be written to the bit cell core having a logic high value; and a second switch configured to couple the local power node to the local write bitline bar responsive to the write bit to be written to the bit cell core having a logic low value, and wherein a capacitance for the memory cell supply capacitor is greater than a distributed capacitance for either of the local write bitline or the local write bitline bar.