Patent ID: 6628679
Filing Date: 2003-09-30
Classification: H04J

Abstract:
A time domain multiplexing method for multiplexing N input signals into a single output signal, N being an integer greater than 1, comprising:respectively receiving N input signals and N clocks and storing said N input signals in N respective latches in accordance with said N respective clocks; sequentially storing outputs of said N latches in N circular buffers in accordance with said N respective clocks; respectively outputting outputs from said N circular buffers into a multiplexer in accordance with N respective system clocks; selectively outputting one of said respective outputs of said N circular buffers to an output latch in accordance with a multiplexer clock input, said output latch latching said output of said multiplexer in accordance with another system clock having a frequency which is N times that of said N input clocks, an output of said output latch providing a time domain multiplexed signal corresponding to said N input signals; and a divider for outputting an output clock in response to said another system clock.