Patent ID: 7940066
Filing Date: 2011-05-10
Classification: G01R,G11C

Abstract:
1. A method for self-testing the phase relationship between a data signal and a data strobe signal at a double data rate (DDR) memory interface comprising: A. selecting a test mode input; B. providing a data strobe signal; C. providing a first clock signal to a delay magnitude generator; wherein the delay magnitude generator generates a second clock signal and a phase control input in the form of a 8-bit code value which corresponds to a magnitude of delay needed for phase shifting the data strobe signal; D. generating an internal data strobe input signal and a corresponding phase shifted data strobe output signal from the second clock signal and the phase control input; E. measuring a phase difference between the internal data strobe input signal and the corresponding phase shifted data strobe output signal; and F. making a pass or fail decision based on the measured phase difference.