Patent ID: 8778752
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A method for designing a semiconductor device comprising: arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging a pattern of a tensile stress film; arranging at least one pattern of a compressive stress film on a region including the first active region so as to be surrounded on a region including the second active region by the tensile stress film and have a projective portion at a portion where the at least one compressive stress film is contact with the tensile stress film; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.