Patent ID: 8558320
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, each disposed on a surface of a semiconductor substrate, the second semiconductor structure between the first and the third semiconductor structures, and arranged proximately to each of the first and third semiconductor structures, a first space defined between the first and the second semiconductor structures, and a second space defined between the second and the third semiconductor structures; a first and second plurality of conductive structures, each disposed on the surface of the semiconductor substrate, the first and second plurality of conductive structures distributed in the first and second spaces, respectively, at least a first one of the first plurality of conductive structures placed closer to the first semiconductor structure than to the second semiconductor structure, and at least a second one of the first plurality of conductive structures placed closer to the second semiconductor structure than to the first semiconductor structure, wherein a first group of the first plurality of conductive structures has a first offset from a line of symmetry between the first and second semiconductor structures, and a second group of the first plurality of conductive structures has a second offset from the line of symmetry, the first and second offsets substantially canceling out, the second plurality of conductive structures having an asymmetric pattern that mirrors a pattern of the first plurality of conductive structures.