Patent ID: 6335634
Filing Date: 2002-01-01
Classification: H03K

Abstract:
A digital processing system comprising:processing circuitry; a memory coupled to said processing circuitry; a programmable logic integrated circuit device comprising: a two-dimensional array of intersecting rows and columns of programmable logic super-regions, each of said super-regions including a plurality of programmable logic regions; a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows for conveying signals between the logic super-regions; a plurality of vertical inter-super-region interconnection conductors associated with each of said columns for conveying signals between the logic super-regions; a plurality of horizontal inter-region interconnection conductors that are associated with each of the logic regions for conveying signals between the logic regions; and a plurality of first programmable interconnection circuitries, each of which is connected to at least two of said programmable logic regions and to at least some of the horizontal inter-super-region interconnection conductors and vertical inter-super-region interconnection conductors, each first programmable interconnection circuit selectively routing signals from the at least two programmable logic regions to which that programmable interconnection circuit is connected and from the horizontal and vertical inter-super-region interconnection conductors to which that programmable interconnection circuit is connected to selected horizontal inter-region interconnection conductors, the programmable logic integrated circuit device being coupled to the processing circuitry and the memory.