Patent ID: 7580301
Filing Date: 2009-08-25
Classification: G06F

Abstract:
1. A memory control circuit, comprising: a phase detection module, for detecting a phase difference between a data strobe signal and a clock signal; a control module, coupled to the phase detection module, for generating a set of control signals correspond to the phase difference, wherein the set of control signals correspond to the phase difference; a latch module, for latching write data carried by a data signal according to rising/falling edges of the data strobe signal; an odd/even data separator, coupled to the latch module, for performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and an adjustable delay line module, coupled to the odd/even data separator and the control module, for adjusting the delay of the odd/even data carried by the data separation signal according to the set of control signals, wherein the delay amount of the odd/even data corresponds to the set of control signals.