Patent ID: 8850381
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A computer-implemented method of transforming a plurality of state elements of a circuit design to be programmed into a hardware functional verification system, comprising: receiving in a memory of the computer a circuit design having a plurality of user state elements configured to operate using a plurality of user clocks, each user clock having a user clock frequency; selecting a set of user state elements from the plurality of user state elements, one or more of the user state elements of the set of user state elements having a highest user clock frequency; selecting a global clock frequency for a global clock to be distributed within the functional verification system, wherein the global clock frequency is at least twice the highest user clock frequency; and transforming each user state element of the set of user state elements into a transformed user state element comprising one or more state elements, each state element configured to receive the global clock, each transformed user state element configured to receive the same inputs as its corresponding user state element, and each transformed user state element to perform the function of the corresponding user state element at the user clock frequency when the transformed user state element is programmed into the functional verification system.