Patent ID: 6157996
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A processor for executing a computer instruction, comprising:a machine specific register (MSR), wherein said MSR includes a predicated execution field;an instruction decoder adapted to receive said computer instruction and produce a decoded instruction in response thereto, wherein said decoder is coupled to said MSR and further wherein said decoder is configured to search said computer instruction for predicated execution information upon detecting an appropriate setting in said predicated execution field and wherein said decoder is further configured to include, upon detecting said predicated execution information in said computer instruction, conditional execution information in said decoded instruction;a first execution unit configured to receive and execute said decoded instruction, wherein said first execution unit is coupled to said MSR and configured to detect and evaluate said conditional execution information in said decoded instruction in response to detecting said appropriate setting in said predicated execution field of said MSR and wherein said first execution unit is configured to execute said decoded instruction only if a condition represented by said conditional execution information is true.