Patent ID: 6166965
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first power supply terminal for receiving a first power supply voltage;a second power supply terminal for receiving a second power supply voltage lower than said first power supply voltage;a data bus;a data bus charging circuit, connected between said first power supply terminal, for charging said data bus;a data bus discharging circuit, connected between said data bus and said second power supply terminal, for discharging said data bus in accordance with a cell read data signal;an output terminal;a push-pull type output circuit formed by a first N-channel MOS transistor connected between said first power supply terminal and said output terminal and a second N-channel MOS transistor connected between said output terminal and said second power supply terminal; anda step-up circuit, connected between said data bus and a gate of said first N-channel MOS transistor, for generating a step-up voltage higher than said first power supply voltage in accordance with a voltage at said data bus, said step-up voltage being applied to the gate of said first N-channel MOS transistor, said second N-channel MOS transistor being controlled by the voltage at said data bus.