Patent ID: 8332572
Filing Date: 2012-12-11
Classification: G06F,Y02D

Abstract:
1. A memory system, comprising: a controller configured to regulate read and write access to dynamic random access memory (DRAM) and one or more FLASH memory devices employed for random access memory applications; a DRAM buffer component configured to provide temporary storage for data stored in the one or more FLASH memory devices wherein a size of the DRAM buffer component is adjusted based on data requirements of the random access memory application; an eviction component configured to evict the data stored in the one or more FLASH memory devices to the DRAM buffer component in response to a replacement algorithm based on a write activity log; and a wear leveling component that remaps data from heavily used areas of the one or more FLASH memory devices to lightly used areas using the DRAM buffer component to provide sector swapping, wherein the DRAM buffer component is not visible to a main memory.