Patent ID: 7100024
Filing Date: 2006-08-29
Classification: G06F

Abstract:
1. An apparatus for generating early status flags to enable early execution of a conditional instruction in a pipeline microprocessor having architected status flags, the apparatus comprising: a storage element, for accumulating early status flags corresponding to the architected status flags; and logic, coupled to said storage element, configured to update said early status flags in said storage element in response to early results of instructions preceding the conditional instruction, wherein said logic invalidates said early status flags if at least one of said early results of said instructions that modify said early status flags is invalid, thereby enabling, if said early status flags are valid, execution of the conditional instruction based on said early status flags prior to the microprocessor updating the architected status flags in response to final results generated for said preceding instructions, wherein said logic is further configured to copy said architected status flags to said early status flags and validate said early status flags if the microprocessor pipeline is flushed.