Patent ID: 8835316
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method for manufacturing a transistor, comprising: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously; wherein the step of forming the semiconductor spacer surrounding the primary spacer and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other further comprises: forming an etch-stop layer on the surfaces of the source/drain regions and the primary spacer; forming a semiconductor layer on a surface of the etch-stop layer; etching the semiconductor layer to form the semiconductor spacer surrounding the primary spacer; removing the ends of the semiconductor spacer in the width direction of the gate by etching to avoid electrical conduction between the source/drain regions; and removing an exposed portion of the etch-stop layer.