Patent ID: 6307420
Filing Date: 2001-10-23
Classification: H03K

Abstract:
A circuit for overcoming a voltage loss in an NMOS transistor, comprising:a first NMOS transistor, having an input terminal coupled to receive an input voltage, a gate coupled to receive a ramp voltage, and an output terminal for providing an output voltage, the NMOS transistor providing a varying portion of the input voltage to the output terminal in response to variations in the ramp voltage;a control circuit coupled to receive the ramp voltage, for providing an activation voltage after the ramp voltage reaches a predetermined voltage, the control circuit comprising:a second PMOS transistor having an input terminal coupled to receive the input voltage, a gate coupled to receive the ramp voltage, and an output coupled to the gate of the first PMOS transistor, the second PMOS transistor providing the input voltage to the gate of the first PMOS transistor before the ramp voltage reaches the predetermined voltage and not providing the input voltage to the gate of the first PMOS transistor after the ramp voltage reaches the predetermined voltage;a clamping circuit for providing the activation voltage; anda second NMOS transistor having an input terminal coupled to the gate of the first PMOS transistor, a gate coupled to receive the ramping voltage, and an output coupled to the clamping circuit, the second NMOS transistor preventing the activation voltage from reaching the gate of the first PMOS transistor before the ramp voltage reaches the predetermined voltage and providing the activation voltage to the gate of the first PMOS transistor after the ramp voltage reaches the predetermined voltage; anda first PMOS transistor, having an input terminal coupled to receive the input voltage, a gate coupled to the control circuit, and an output terminal coupled to the output terminal of the NMOS transistor for providing an output voltage, the PMOS transistor providing the input voltage to the output terminal in response to presence of the activation voltage at its gate.