Patent ID: 6597611
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A read circuit on a semiconductor comprising:a) a precharge input; b) a first switch, the gate of the first switch coupled to the precharge input, the source of the firs coupled to a voltage source, the drain of the first switch coupled to a local bitline; c) a first delay element, the input of the first delay element coupled to the precharge input; d) a second delay element, the input of the second delay element coupled to the output of the first delay element; e) a second switch, the gate of the second switch coupled to the output of the second delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to a global bitline; f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source; g) a fourth switch, the gate of the fourth switch coupled to the output of the first delay element, the source of the fourth switch coupled to ground; h) a fifth switch, the gate of the fifth switch coupled to the/bitline , the source of the fifth switch coupled to the drain of the third switch, the drain of the fifth switch coupled to the drain of the fourth switch; and i) a sixth switch, the gate of the sixth switch coupled to the drain of the fifth switch, the drain of the sixth switch coupled to the global bitline, the source of the sixth switch coupled to ground.