Patent ID: 8299520
Filing Date: 2012-10-30
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of at least three auxiliary gate electrodes; an auxiliary gate insulating layer on the plurality of at least three auxiliary gate electrodes; a continuous semiconductor layer crossing the plurality of at least three auxiliary gate electrodes, wherein the auxiliary gate insulating layer is between the continuous semiconductor layer and the plurality of at least three auxiliary gate electrodes; a plurality of primary gate electrodes on the continuous semiconductor layer so that the continuous semiconductor layer is between the plurality of primary gate electrodes and the plurality of auxiliary gate electrodes, wherein each of the plurality of primary gate electrodes is arranged on portions of the continuous semiconductor layer between respective adjacent ones of the plurality of auxiliary gate electrodes; a tunnel insulating layer comprising a tunnel insulating material between at least one of the plurality of primary gate electrodes and the continuous semiconductor layer; a charge storage layer comprising a charge storage material on the tunnel insulating layer, wherein the charge storage layer is between the at least one of the plurality of primary gate electrodes and the tunnel insulating layer, and wherein the tunnel insulating material and the charge storage material comprise different materials; and a blocking insulating layer comprising a blocking insulating material on the charge storage layer, wherein the blocking insulating layer is between the at least one of the plurality of primary gate electrodes and the charge storage layer, and wherein the charge storage material and the blocking insulating material comprise different materials; wherein each of the plurality of auxiliary gate electrodes is configured to induce a respective field effect type source/drain region in the continuous semiconductor layer between respective adjacent ones of the primary gate electrodes; and wherein a space between the continuous semiconductor layer and each of the plurality of at least three auxiliary gate electrodes is free of the charge storage material.