Patent ID: 9087784
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A method of fabricating a complementary metal oxide semiconductor structure comprising: providing a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET device region of a semiconductor structure and a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET device region of said semiconductor substrate, wherein said plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion comprises from 5 atomic % to 12 atomic % N forming a gate electrode layer atop both said plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion and said pFET threshold voltage adjusted high k gate dielectric layer portion; and forming an nFET gate stack in said nFET device region and a pFET gate stack in said pFET device region.