Patent ID: 8841712
Filing Date: 2014-09-23
Classification: A61B,C12Q,G01N,G01R,H01L

Abstract:
1. A method of fabricating a nano-pillar transistor, comprising: providing a polymer coating upon a silicon substrate; using electron beam lithography to fabricate a mask pattern in the polymer coating; depositing an alumina film upon the mask pattern; creating a hard-etch mask by using a solvent to remove a portion of the alumina film and a portion of the polymer coating; using the hard-etch mask for executing a first etching procedure to create a plurality of nano-pillars; executing a second etching procedure for reducing a diameter of each of the plurality of nano-pillars, wherein the plurality of nano-pillars having the reduced diameter constitutes a plurality of gates of an array of nano-pillar transistors; using an ion beam procedure to introduce dopants for fabricating each of a source region and a drain region adjacent to each of the plurality of gates; applying electron beam annealing of the dopants; using one of an ion milling procedure or a reactive ion etching procedure to remove deposited alumina film from a top portion of each of the plurality of gates; applying metallization upon each of the plurality of gates and upon each of the source region and the drain region adjacent to each of the plurality of gates; and depositing alternating metal stacks between each of the metallized plurality of gates, wherein the alternating metal stacks mimic a hydrophilic-hydrophobic-hydrophilic structure of a cellular membrane.