Patent ID: 9012918
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first gate electrode on an insulating surface; a second gate electrode on the insulating surface; a first gate insulating layer over the first gate electrode and the second gate electrode; a first oxide semiconductor layer and a second oxide semiconductor layer each comprising indium, gallium, and zinc over the first gate insulating layer, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is a non-single-crystal semiconductor; a first electrode layer and a second electrode layer over and in contact with the first oxide semiconductor layer, wherein one of the first electrode layer and the second electrode layer is electrically connected to the second oxide semiconductor layer and the second gate electrode; a third electrode layer over and in contact with the second oxide semiconductor layer; a second gate insulating layer over the first oxide semiconductor layer, the second oxide semiconductor layer, the first electrode layer, the second electrode layer and the third electrode layer; a third gate electrode overlapping with the first oxide semiconductor layer with the second gate insulating layer interposed therebetween; and a fourth gate electrode overlapping with the second oxide semiconductor layer with the second gate insulating layer interposed therebetween, wherein the second gate insulating layer comprises a first insulating layer and a second insulating layer over the first insulating layer, wherein the second insulating layer comprises one compound selected from the group consisting of silicon nitride, silicon oxynitride, and silicon nitride oxide, wherein the first oxide semiconductor layer includes a region with a small thickness compared to a region of the first oxide semiconductor layer which overlaps with the first electrode layer or the second electrode layer, wherein the second oxide semiconductor layer includes a region with a small thickness compared to a region of the second oxide semiconductor layer which overlaps with the third electrode layer, wherein both the first gate electrode and the third gate electrode extend beyond side edges of the first oxide semiconductor layer in a channel width direction of the first oxide semiconductor layer, and wherein both the second gate electrode and the fourth gate electrode extend beyond side edges of the second oxide semiconductor layer in a channel width direction of the second oxide semiconductor layer.