Patent ID: 7978113
Filing Date: 2011-07-12
Classification: H03M

Abstract:
1. A circuit comprising: an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate, the first digital values having a first bit-width, the analog-to-digital digital converter having a noise floor that is substantially flat specified spectrum; an interpolator configured to receive the first digital values and to generate second digital values at a second sampling rate higher than the first sampling rate, the second digital values having a second bit-width equal to or greater than the first bit-width, the interpolator having a noise floor that is substantially flat in a first portion of the specified spectrum and that is substantially flat in a second portion of the specified spectrum; and a digital filter configured to receive the second digital values and to perform bit-width reduction in a recoverable manner to generate third digital values, the third digital values having a third bit-width less than the first and second bit-widths, the digital filter having a noise floor that is substantially flat in the first portion of the specified spectrum and that rises in the second portion of the specified spectrum.