Patent ID: 8304912
Filing Date: 2012-11-06
Classification: H01L

Abstract:
1. A field effect transistor (FET) comprising: a substrate; a buried oxide (BOX) layer over said substrate; a silicon on insulator (SOI) layer over said BOX layer; a shallow trench isolation (STI) region over said BOX layer; a first gate structure on said SOI layer; a second gate structure on said STI region; and a landing pad comprising epitaxially-grown material including a pair of flanged ends attached to said second gate structure, wherein said pair of flanged ends having a width greater than a width of said second gate structure, wherein a width of said landing pad is greater than a width of said second gate structure, wherein the structure of said second gate structure is discontinuous with the structure of said landing pad, wherein said pair of flanged ends are overlapping said second gate structure, and wherein said pair of flanged ends abuts said second gate structure.