Patent ID: 6424047
Filing Date: 2002-07-23
Classification: H01L

Abstract:
An integrated circuit package comprising:a laminate core having a top surface and a bottom surface; a die pad positioned on said top surface of said laminate, said die pad being covered with a first solder resistant material except for at least one location about the perimeter of said die pad, said at least one location providing a metal bonding location; a conductive trace on top of said laminate core, said conductive trace being completely about said die pad, said conductive trace being substantially covered with a second solder resistant material except for at least two discrete wire bonding locations on said conductive trace, wherein said at least two wire bonding locations are minimized to a size just large enough to bond a wire thereto; an encapsulation compound on top of said die pad, said lamination core, said conductive trace, said first solder resistant material, and said second solder resistant material; said encapsulation compound being in contact with said metal bonding location at said at least one location, said encapsulation compound being in contact with said conductive trace only at each of said at least one wire bonding location.