Patent ID: 6226215
Filing Date: 2001-05-01
Classification: G11C

Abstract:
In a semiconductor memory device comprising:a unit memory cell;a first line connecting means responsive to a first bit line separating signal for connecting or disconnecting bit lines within the unit memory cell region and bit lines within a sense amplifier region;a second line connecting means responsive to a second bit line separating signal for connecting or disconnecting bit lines within an other unit memory cell region and bit lines within the sense amplifier region;a first precharging means for equalizing and precharging the bit lines within the sense amplifier region under a control by a first precharging control signal;a bit line sense amplifier connected between the bit lines within the sense amplifier region for performing a bit line sensing operation under a control by sense amplifier control signals; anda data bus line connecting means responsive to a column selecting signal for connecting or disconnecting the bit lines within the sense amplifier region and data bus lines being characterized in that:said semiconductor memory device further includes a second precharging means for equalizing and precharging said bit lines within the unit memory cell region under a control by a second precharging control signal;wherein said first and second bit line separating signals are generated from a bit line separating signal generating means in accordance with a bank selecting signal and a sensing generating signal;said first bit line precharging control signal is generated from a first precharging control means in accordance with said bank selecting signal and said first and second bit line separating signals; andsaid second bit line precharging control signal is generated from a second precharging control means in accordance with said bank selecting signal and a /CAS signal.