Patent ID: 9143121
Filing Date: 2015-09-22
Classification: H03K

Abstract:
1. A method comprising: receiving an input clock signal at a programmable buffer; filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, the voltage level indicating a duty cycle of the output signal; comparing the voltage level of the filtered signal to a reference voltage to generate a comparison signal; in response to a value of a clocked enable signal at a calibration finite state machine, generating a first digital code at the calibration finite state machine based on the comparison signal and based on at least one other digital code provided to the programmable buffer; and selectively activating a first set of digital logic of the programmable buffer based on a logic level of the input clock signal and based on the first digital code from the calibration finite state machine to change a charging rate of a node to adjust the duty cycle of the output signal of the programmable buffer.