Patent ID: 7940544
Filing Date: 2011-05-10
Classification: G11C,H01L,Y10T

Abstract:
1. An improvement to a memory system having a hierarchical bitline structure that includes a first global write line configured to carry a first global write signal and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the first global write line includes first and third traces and the second global write line includes second and fourth traces, wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer, wherein the improvement comprises: at least one of the first and third traces having a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias; at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap; wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width.