Patent ID: 6178542
Filing Date: 2001-01-23
Classification: G06F,Y02D

Abstract:
A method for designing the architecture of an embedded system, comprising:(a) a pre-processing phase comprising the step of parsing one or more aperiodic task graphs, one or more system/task constraints, and a resource library for the embedded system; and(b) a synthesis phase, following the pre-processing phase, comprising the steps of allocating one or more groups of one or more tasks in the aperiodic task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the aperiodic tasks graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, wherein, during the synthesis phase, the possible allocations are selected based on one or more quality of architecture metrics, wherein the one or more quality of architecture metrics comprise a resource utilization index (RUI) based on levels of utilization of the one or more PEs and the one or more communication links.