Patent ID: 7309892
Filing Date: 2007-12-18
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor element comprising: a memory array including a plurality of memory elements, the plurality of memory elements being arranged in a shape of a matrix; wherein each of the plurality of memory elements includes: wherein the gate electrodes of the plurality of memory elements arranged in a first direction are connected to each other, wherein edges of the plurality of memory elements arranged in a second direction across the first direction are connected to each other, wherein a distance between the carrier confinement region and the gate electrode is larger than a distance between the carrier confinement region and the channel, wherein a total capacitance Ctt around the carrier confinement region satisfies the condition where k is Boltzmann's constant, T is the room temperature in degrees Kelvin and q is the charge of an electron.