Patent ID: 8140765
Filing Date: 2012-03-20
Classification: G06F

Abstract:
1. A method comprising: sending, by a processor element, a plurality of requests for memory operations to a cache memory, the cache memory including first and second cache banks, the memory operations including load operations and store operations, each load and store operation exhibiting a respective size requirement; arbitrating, by an arbitration mechanism, among the plurality of requests for memory operations to select a particular load operation and a particular store operation for access to the cache memory; arbitrating, by the arbitration mechanism, in a first arbitration stage among the load operation requests in the, plurality of requests for memory operations to provide the particular load operation for access to the cache memory; arbitrating, by the arbitration mechanism, in the first arbitration stage among store requests, to provide the particular store operation for access to the cache memory; arbitrating by the arbitration mechanism, in the first arbitration stage among read claim state machine requests, cast out state machine requests and snoop requests to determine a cache arbiter arbitration result; arbitrating, by the arbitration mechanism, in a second arbitration stage between the selected store operation and the cache arbiter arbitration result to select a second stage arbitration result; commencing, by the arbitration mechanism, the particular load operation on the first cache bank during a first cache cycle; commencing, by the arbitration mechanism, the particular store operation on the second cache bank during a second cache cycle that follows the first cache cycle; and performing, by the first and second cache banks, the particular load operation and the particular store operation substantially simultaneously.