Patent ID: 8895334
Filing Date: 2014-11-25
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor array substrate, comprising: a first patterning process, in which a pattern of an active layer which is formed by a semiconductor layer and patterns of a source electrode and a drain electrode, which are separated from each other and are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of an insulating layer is formed on the transparent substrate subjected to the first patterning process, the pattern of the insulating layer comprising a contact via hole exposing the source electrode; and a third patterning process, in which a pattern of a pixel electrode, which is formed by a transparent conductive layer, and a pattern of a gate electrode, which is formed by a second metal layer, are formed on the transparent substrate subjected to the second patterning process, the pixel electrode being connected to the source electrode through the contact via hole.