Patent ID: 6020633
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A combination of integrated circuit packages comprising:an FPGA package comprising:an FPGA chip;a printed circuit board carrier having:a first electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the first electrical conductor at an upper surface of the printed circuit board carrier;a second electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the second electrical conductor at the upper surface of the printed circuit board carrier;a third electrical conductor extending through the printed circuit board carrier;a fourth electrical conductor extending through the printed circuit board carrier, the FPGA chip being connected to the fourth electrical conductor at the upper surface of the printed circuit board carrier;a first connector element connected to the second electrical conductor at a lower surface of the printed circuit board carrier, the first connector element being formed to couple the printed circuit board carrier to a printed circuit board;a second connector element connected to the third electrical conductor at the lower surface of the printed circuit board carrier, the second connector element being formed to couple the printed circuit board carrier to the printed circuit board; anda third connector element connected to the fourth electrical conductor at the lower surface of the printed circuit board carrier, the third connector element being formed to couple the printed circuit board carrier to the printed circuit board; anda PROM package comprising:a PROM chip, separate from the FPGA chip, wherein the PROM chip is connected to the first electrical conductor, the third electrical conductor and the fourth electrical conductor at the upper surface of the printed circuit board carrier.