Patent ID: 9196623
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor process for forming special pattern features, comprising: providing a substrate having a target layer and a hard mask layer on said target layer; forming a patterned material layer on said hard mask layer, wherein said patterned material layer is provided with a plurality of feature units, each said plurality of feature units comprises a plurality of small core bodies spaced-apart from each other by a first interval and a plurality of large core bodies at two opposite sides of said plurality of small core bodies and are spaced-apart from each other by a second interval, wherein a one of said plurality of large core bodies at a first one of said two opposite sides is spaced-apart from an adjacent one of said plurality of small core bodies by said first interval, and another one of said plurality of large core bodies at a second one of said two opposite sides is spaced-apart from another adjacent one of said plurality of small core bodies by said second interval, wherein said first interval is smaller than said second interval; forming a spacer material layer conformally on said hard mask layer, on said plurality of small core bodies and on said plurality of large core bodies, wherein said spacer material layer is provided with a plurality of recesses, each of said plurality of recesses is located within each respective first interval and within each respective second interval; filling up said plurality of recesses with a filling material so as to form a plurality of filling bodies; using said plurality of filling bodies as a first mask to perform a first etching process for removing exposed said spacer material layer so as to form a plurality of small filling bodies and a plurality of large filling bodies, wherein each respective said first interval is filled with said plurality of small filling bodies and wherein each respective said second interval is filled with said plurality of large filling bodies; using said plurality of small core bodies and said plurality of small filling bodies as a second mask to perform a second etching process for patterning said hard mask layer into a plurality of small hard mask bodies spaced-apart from each other, and simultaneously using said plurality of large core bodies and said plurality of large filling bodies as a third mask for patterning said hard mask layer into a plurality of large hard mask bodies, wherein said plurality of large hard mask bodies are at two opposite sides of said plurality of small hard mask bodies; forming a photoresist layer on said plurality of large hard mask bodies at said two opposite sides of said plurality of small hard mask bodies; and using said plurality of small hard mask bodies, said plurality of large hard mask bodies and said photoresist layer as a fourth mask to perform a third etching process for patterning said target layer into said special pattern features.