Patent ID: 7921311
Filing Date: 2011-04-05
Classification: H03M

Abstract:
1. A device comprising: a processor; an external button alternately configurable in an unpressed state and a pressed state; and current drain mitigation circuitry coupled to the external button and a corresponding input of the processor; wherein the current drain mitigation circuitry is configured to connect the input of the processor to a first potential when the external button is in the unpressed state and to connect the input of the processor to a second potential different than the first potential when the external button is in the pressed state, thereby limiting current drain arising from the external button being stuck in the pressed state; and wherein the current drain mitigation circuitry comprises a capacitive element coupled between the input of the processor and a third potential, the capacitive element being connected between the first potential and the third potential when the external button is in the unpressed state and the capacitive element being connected between the second potential and the third potential when the external button is in the pressed state.