Patent ID: 6468919
Filing Date: 2002-10-22
Classification: H01L

Abstract:
A method of making a local interconnect in an embedded memory, the method comprising:providing a semiconductor wafer in which the surface of the silicon substrate has both a defined memory array area and a periphery circuit area; separately forming a plurality of gates in both the memory array area and the periphery circuit area, and forming lightly doped drains (LDD) adjacent to each gate; forming a silicon nitride layer, a first dielectric layer, and a first photoresist layer on the surface of the semiconductor wafer, respectively, as well as covering the surface of the gate; performing a photo-etching-process (PEP) to define a plurality of landing vias and multiple patterns of the local interconnect in the first photoresist layer; etching the first dielectric layer using the pattern of the first photoresist layer as a hard mask, to form a plurality of landing via holes in the first dielectric layer in the memory array area, as well as a plurality of local interconnect holes in the first dielectric layer in the periphery circuit area; filling an electrical conducting layer in each landing via and local interconnect hole to form the landing vias and local interconnects; removing the first dielectric layer and a portion of the silicon nitride layer in the periphery circuit area by performing a first etching process to form a spacer on either side of each gate in the periphery circuit area; and performing a salicide process to form a metal silicide layer on the top surface of the landing via in the memory array area and on the surface of each gate and on the local interconnect in the periphery circuit area.