Patent ID: 7657729
Filing Date: 2010-02-02
Classification: G06F

Abstract:
1. A data processing system comprising: a processor; a memory hierarchy coupled to the processor and having at least one lower level storage device; a prefetch engine (PE) associated with the processor and which includes: a plurality of history tables, each of which is utilized to track a set of different stride patterns for received requests; and logic for enabling simultaneous tracking of multiple different stride patterns for accessing the storage device using the plurality of history tables, wherein said plurality of history tables are ordered for sequential access based on a first check of simple stride patterns at a first history table and a second check of more complicated stride patterns at a second of subsequent history tables; said logic further comprises logic for: parsing a received address for a first index corresponding to the first history table, wherein a plurality of indices is provided within the received address and each index in the plurality of indices corresponds to a history table of the plurality of history tables; parsing the received address for subsequent indices; and enabling ordered access to said plurality of history tables using said indices, wherein said plurality of history tables are accessed in a preset order to reduce interference between the different stride patterns, wherein said logic for enabling ordered access further comprises logic for: determining at the first history table whether a received address fits a first stride pattern of the first history table; and when the address fits the first stride pattern of the first history table, identifying the address as belonging to a stream having that first stride pattern and initiating a prefetch stream and when an address does not fit the first stride pattern of the first history table, said logic further comprises logic for: forwarding the address to the second history table within the preset order of history tables, said second history table being next in sequence relative to said first history table; checking the second history table for a match of its second stride pattern to the address; and when no match of the second stride pattern is found at the second history table, iteratively forwarding the address to the next sequential history table(s) to be checked against the stride pattern(s) of the next sequential history table(s) until a last history table is reached within the preset order.