Patent ID: 7519642
Filing Date: 2009-04-14
Classification: G06F,H03M

Abstract:
1. An averaging circuit comprising: a plurality of cell arrays, each cell array comprising a plurality of cells, wherein each cell is configured to hold a single bit value, and wherein each cell array is configured to shift bit values from an input cell through the plurality of cells in the array to an output cell; a plurality of counters, wherein one of the plurality of counters is coupled to the output cell of each cell array and each counter has an input a plurality of outputs; and a plurality of logic circuits disposed in one-to-one correspondence to the plurality of counters, such that each of the plurality of counters has a single corresponding logic circuit, wherein each logic circuit has inputs that receive the plurality of outputs of the corresponding counter and generates an output of a single bit position having a value that is based on the values of its inputs.