Patent ID: 7715513
Filing Date: 2010-05-11
Classification: H04L

Abstract:
1. A data synchronization apparatus, comprising: a FIFO buffer for receiving and storing a plurality of data and providing a FIFO adjustment signal according to the number of the data stored in the FIFO buffer, wherein the data stored in the FIFO buffer are sent out to an external device at a clock rate derived from a master clock signal; a frequency counter for receiving the master clock signal and a timer tick signal, counting the number of cycles of the master clock signal in a cycle of the timer tick signal, and providing a counter adjustment signal according to the number of the counting; a control circuit for providing a PLL adjustment signal according to the FIFO adjustment signal and the counter adjustment signal; and a PLL for providing the master clock signal and adjusting the frequency of the master clock signal in response to the PLL adjustment signal.