Patent ID: 6240487
Filing Date: 2001-05-29
Classification: G06F

Abstract:
A method within a computer system of efficient transfer of data to and from a processor cache that includes a plurality of interleaved subarrays, said method comprising the steps of:concurrently processing multiple processor requests for data and castouts utilizing said plurality of interleaved subarrays, wherein multiple of said plurality of interleaved subarrays each processes a single one of said multiple processor requests utilizing a respective reload buffer and store-back buffer;in response to a request that misses at said processor cache, loading data into an integrated cache reload buffer associated with a subarray among said plurality of interleaved subarrays;transferring said data to said subarray in a subsequent processor cycle;in response to a castout from said subarray, placing castout data into an integrated store-back buffer also associated with said subarray;forwarding said castout data from said integrated store-back buffer to a memory location of said computer system in a subsequent processor cycle; andutilizing a plurality of vertically interconnected multiplexers, multiplexing the integrated cache store-back buffer with at least one other cache store-back buffer to create a first common output path and, multiplexing the first common output path with at least one other store-back buffer to create a second common output path.