Patent ID: 6258677
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of fabricating a transistor, comprising the steps of:providing a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between;selectively growing epitaxial silicon over said active region to form an SEG region;forming a dummy gate over said SEG region;selectively growing raised epitaxial silicon layers over said SEG region adjacent said dummy gate;removing said dummy gate to expose interior side walls of said raised epitaxial silicon layers;forming sidewall spacers on said exposed interior side walls of said raised epitaxial silicon layers;growing a gate oxide layer over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers;depositing a polysilicon layer over the silicon semiconductor structure;planarizing said polysilicon layer to form a gate conductor over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; andremoving said sidewall spacers.