Patent ID: 9111597
Filing Date: 2015-08-18
Classification: G11C

Abstract:
1. A memory device comprising: an array of memory cells in an array level, the array of memory cells having sides that define a perimeter; an x-decoder and a y-decoder in a device level, one or both of the x-decoder and the y-decoder being disposed at least partly within a cylinder defined by the perimeter; a first plurality of inter-level conductive lines connecting the x-decoder and the y-decoder in the device level to bit lines and word lines in the array level, the first inter-level conductive lines having portions that extend from outside of the cylinder to inside of the cylinder to make contact in the array level; a plurality of bonding pads in a pad level, the pad level being separate from the device level and the array level, the plurality of bonding pads at least partly disposed within the cylinder; and a second plurality of inter-level conductive lines coupled between the plurality of bonding pads and the device level, a portion of the second plurality of inter-level conductive lines extending from outside of the cylinder to inside of the cylinder to make contact in the pad level, wherein: the portions of the x-decoder each have a corresponding x-decoder width and x-decoder length, the portions of the y-decoder each have a corresponding y-decoder width and y-decoder length; and including: