Patent ID: 8089811
Filing Date: 2012-01-03
Classification: G11C,H01L

Abstract:
1. A flash memory device comprising a first memory cell string comprising a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line; and a second memory cell string comprising a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line, wherein the first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and wherein the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages; and wherein the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string have threshold voltages greater than a predetermined voltage and wherein the second dummy memory cell of the first memory cell string and the first dummy memory cell of the second memory cell string have threshold voltages less than the predetermined voltage.