Patent ID: 8837251
Filing Date: 2014-09-16
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first memory array including a plurality of first word lines, one of a plurality of first local bit lines wired in a direction crossing the plurality of first word lines, a plurality of first memory cells arranged at intersections of the plurality of first word lines and the first local bit line, and a first bit line driver connected to the first local bit line; a second memory array including a plurality of second word lines, one of a plurality of first local bit lines wired in a direction crossing the plurality of second word lines, a plurality of second memory cells arranged at intersections of the plurality of second word lines and the second local bit line, and a second bit driver connected to the second local bit line; a global bit line provided to be shared by the first local bit line and the second local bit line; and a sense amplifier connected to the global bit line, wherein information read from one of the plurality of first memory cells or one of the plurality of second memory cells is inputted to the sense amplifier through the global bit line, wherein when programming information to one of the plurality of first memory cells, the first bit line driver is activated and the second bit line driver is deactivated, wherein when programming information to one of the plurality of second memory cells, the second bit line driver is activated and the first bit line driver is deactivated, wherein the first bit line driver and the second bit line driver are each individually connected to a corresponding one of the first local bit lines and the second bit lines, respectively, wherein the first local bit line and the second local bit line are both connected to the sense amplifier via the global bit line in common.