Patent ID: 6122198
Filing Date: 2000-09-19
Classification: G11C

Abstract:
A method of erase verifying and overerase verifying an array of flash memory cells, the method comprising:(a) erase verifying a memory cell in a column and a row;(b) if the memory cell is undererased applying an erase pulse to the array of flash memory cells;(c) if the memory cell is properly erased erase verifying a next memory cell;(d) repeating steps (a) through (c) until all memory cells in the array of flash memory cells verify as erased;(e) overerase verifying a memory cell in a column and a row;(f) if the memory cell is overerased applying an overerase correction pulse to the column in which the memory cell is located;(g) if the memory cell is properly erased overerase verifying a next memory cell;(h) repeating steps (e) through (g) until all memory cells in the array of flash memory cells overerase verify; and(i) repeating steps (a) through (c) until all memory cells in the array of flash memory cells verify as erased.