Patent ID: 6031757
Filing Date: 2000-02-29
Classification: G11C

Abstract:
An integrated circuit memory, comprising:an array of non-volatile erasable and programmable memory cells, including a plurality of sectors;a plurality of control inputs for receiving a set of control signals;address inputs for receiving address signals;data input/outputs for transferring data into and out of the array;command logic, coupled to the plurality of control inputs, and to at least one of the address inputs and the data input/outputs, which detects command sequences at the plurality of control inputs and the at least one of the address inputs and the data input/outputs, indicating operations for the array, including a program operation to program data in the array, a sector erase operation to erase a sector of the array, a read operation to read data in the array, and a sector lock operation to set a sector lock signal for at least one sector in the array;sector protect logic coupled to the command logic, including non-volatile, sector lock memory which stores the sector lock signal for at least one sector in the array indicating a protect status for a corresponding sector in the array; which inhibits the sector erase and program operations in a particular sector in response to a set sector lock signal corresponding to the particular sector and to a first state of control signals in the set of control signals; anderase, program and read circuits responsive to the command logic and the sector protect logic to execute the sector erase, program and read operations, and to execute the sector lock operation.