Patent ID: 7884656
Filing Date: 2011-02-08
Classification: H03L

Abstract:
1. A phase locked loop (PLL), comprising: a type 1 PLL including a phase detector operable to produce a phase error signal indicative of a difference in phase between said reference signal and said feedback signal, a single pole loop filter operable to filter said current pulse or said phase error signal to produce a control voltage, a voltage controlled oscillator operable to produce an oscillation based upon said control voltage and a frequency divider coupled to receive said oscillation and operable to divide said oscillation by a divide ratio to produce a feedback signal; a frequency detector including a frequency counter operable to produce a frequency error signal indicative of a difference in frequency between the reference signal and the feedback signal and a charge pump operable to generate a current pulse proportional to said frequency error signal and to provide said current pulse to said single pole loop filter; and logic for switching between said phase detector and said frequency detector based on said frequency error signal.