Patent ID: 6813184
Filing Date: 2004-11-02
Classification: G11C

Abstract:
A nonvolatile memory, including a cell array of a plurality of memory cells arranged in a matrix of rows and columns, being conductive in operation modes of programming, reading, copy-back programming, and erasing, the memory comprising:a clock generator for creating a clock signal operable in the operation modes; an address generator for creating column addresses in response to the clock signal; a page buffer circuit including a plurality of page buffers corresponding to the columns, each page buffer including main and cache latches; a column selection circuit for selecting a part of the page buffers and for connecting the selected page buffers to data lines corresponding to the selected page buffers; a data loading circuit for putting external program data bits into the cache latches of the selected page buffers; and a control circuit structured to control the data loading circuit in response to the column addresses, in which a pass data bit is loaded in the cache latch of a selected page buffer connected to a defective column, instead of a program data bit of the defective column, when one of the column addresses designates the defective column during the programming operation mode.