Patent ID: 7889106
Filing Date: 2011-02-15
Classification: G05F,H03M

Abstract:
1. A digital-to-analog conversion circuit comprising: a first MOS transistor having a gate, drain and source; an operational amplifier that has an inverted input node, non-inverted input node and output node and in which the inverted input node is supplied with a reference voltage and the non-inverted input node and output node are respectively connected to the drain and gate of the first MOS transistor; a first resistor connected between a first power source voltage node and the drain of the first MOS transistor; a plurality of second MOS transistors having gates, drains and sources, the gates being connected to the gate of the first MOS transistor and the second MOS transistors configuring a plurality of current mirror pairs together with the first MOS transistor; a first switched capacitor circuit connected between the source of the first MOS transistor and a second power source voltage node; a plurality of second switched capacitor circuits connected between the sources of the plurality of second MOS transistors and the second power source voltage node; a second resistor having one end and the other end, the one end being connected to the first power source voltage node and the other end being connected to a first analog voltage output node; a third resistor having one end and the other end, the one end being connected to the first power source voltage node and the other end being connected to a second analog voltage output node; and a plurality of switching circuits that are respectively connected between the first and second analog voltage output nodes and the drains of the plurality of second MOS transistors and permit currents flowing through the plurality of second MOS transistors to flow through one of the first and second analog voltage output nodes that are selectively switched based on plural-bit digital signals.