Patent ID: 8533572
Filing Date: 2013-09-10
Classification: G06F

Abstract:
1. An apparatus comprising: a first cache; a first error correction code (ECC) logic to use a first ECC scheme for the first cache; a second cache; a second ECC logic to use a second, different ECC scheme for the second cache, wherein the second ECC logic provides a higher level of protection than the first ECC logic; an interconnect coupled with the first cache and the second cache; and logic to transmit data and also check bits corresponding to the data over the interconnect, in which the check bits are to be used by the first ECC logic that is to use the first ECC scheme and also by the second ECC logic that is to use the second, different ECC scheme, wherein both the first and second ECC logic are to use the check bits that are to be transmitted over the interconnect, wherein the first ECC logic is to generate the check bits using the data, wherein the second ECC logic comprises a partial encoder unit having a first portion that is capable of generating a set of bits identical in value to the check bits using the data and a second portion that is capable of generating additional check bits using the data, and wherein the apparatus is operable to reduce power to the first portion of the partial encoder without reducing power to the second portion of the partial encoder.