Patent ID: 8645795
Filing Date: 2014-02-04
Classification: G06F,G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array that includes a plurality of memory cells each including a variable resistive element which has a variable resistor sandwiched between a first electrode and a second electrode and stores information by shifting an electric resistance of the variable resistor between a plurality of states by applying a voltage pulse between the first electrode and the second electrode; an input/output buffer that receives write data in units of bits the number of which is set in advance, and that outputs read data which is read from the memory cell array; and a memory control unit that includes a write control unit which controls a write process to the memory cell array, a read control unit which controls a read process to the memory cell array, and an ECC control unit which performs an error correction code generation process of generating an error correction code of a predetermined system and an error correction process, the memory cell array including a predetermined number of databanks that store data, and an ECC bank that stores test data in the error correction code which is generated by the error correction code generation process, wherein upon receiving a write request to the memory cell array, the input/output buffer outputs the write data received, to the write control unit and the ECC control unit, the write control unit generates divided data by dividing the write data into a predetermined number of data, and performs a data write process of writing the divided data to each of the databanks, based on a write address which is assigned by the write request, the ECC control unit generates a first error correction code by performing the error correction code generation process to either the write data or each of the divided data, in parallel with the data write process in the write control unit, and transfers first test data in the first error correction code to the write control unit, and the write control unit receives the first test data from the ECC control unit, and performs a code write process of writing the first test data into the ECC bank.