Patent ID: 7208753
Filing Date: 2007-04-24
Classification: B82Y,H01L

Abstract:
1. A transistor comprising: a bottom dielectric layer; a first layer on at least a portion of the bottom dielectric layer and having a first bandgap defining a maximum valance energy level below the first bandgap and above the Fermi energy of the first layer; a second layer on at least a portion of the first layer and having a second bandgap defining a minimum conduction energy level above the second bandgap; wherein the second layer comprises a material having a bulk bandgap when the material is in bulk form; wherein the second layer has a thickness that is less than a maximum thickness, such that the second bandgap is larger than the bulk bandgap, and such that the minimum conduction energy level is within the first bandgap; and wherein the maximum valance energy level and the Fermi energy are within the second bandgap; a top dielectric layer on at least a portion of the second layer; wherein at least one of the bottom dielectric layer and the top dielectric layer is partially p-doped; wherein the first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer; and wherein the first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer; and a gate electrode on a portion of the top dielectric layer over a portion of the hole wire; wherein the gate electrode divides the top dielectric layer into a source contact and a drain contact; wherein the gate electrode comprising a metal layer and an oxide layer.