Patent ID: 6510545
Filing Date: 2003-01-21
Classification: G06F,H01L,H05K

Abstract:
A multi-layer circuit comprising:a first layer of circuits having a first plurality of signal wires aligned in a first direction in a first plane and a first plurality of shielding wires, wherein each of said shielding wires is aligned in said first direction in said first plane and is adjacent at least one of said first plurality of signal wires; a second layer of circuits having a second plurality of signal wires aligned in a second direction substantially orthogonal to said first direction in said second plane substantially parallel to said first plane and a second plurality of shielding wires wherein each of said shielding wires substantially aligned in said second direction in said second plane and is adjacent at least one of said second plurality of signal wires; and a third layer of circuits having a third plurality of signal wires substantially aligned in said first direction in a third plane substantially parallel to said first plane and a third plurality of shielding wires wherein each of said third plurality of shielding wires is substantially aligned in said first direction in said third plane and is adjacent at least one of said third plurality of signal wires, and wherein said second plane is between said first plane and said third plane.