Patent ID: 8598949
Filing Date: 2013-12-03
Classification: H03K

Abstract:
1. A electronic circuit, comprising: a state retention power gating (SRPG) circuit having a functional mode and a state retention mode, said SRPG circuit storing state information when in the state retention mode; a first power grid coupling to the SRPG circuit for providing power from a first power source to the SRPG circuit when the SRPG circuit is in a functional mode; wherein the first power source is arranged to avoid supplying power to the first power grid when the SRPG circuit is in the state retention mode; a second circuit; a second power grid coupling to the second circuit for providing power from a second power source to the second circuit independent from the mode of the SRPG circuit; a switching circuit; a third power grid coupling the SRPG circuit to the switching circuit for providing power received from said switching circuit to the SRPG circuit; and wherein the switching circuit is arranged to couple the third power grid to the first power grid when the SRPG is in the functional mode and to couple the third power grid to the second power grid when the SRPG is in the state retention mode; wherein the electronic circuit further comprising a controller connected to the switching circuit, the SRPG circuit and the first power source, which controller is arranged to generate a control signal that is indicative of a desired operational mode of the SRPG circuit, the desired operational mode being selected from the state retention mode and the functional mode, and to output the control signal to the switching circuit, the SRPG circuit and the first power source.