Patent ID: 6656794
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device, the manufacturing method comprising the steps of:(a) providing a semiconductor substrate, which includes a semiconductor layer, a first insulating layer formed on the semiconductor layer, a first conductive layer formed on the first insulating layer, and a stopper layer formed on the first conductive layer; (b) patterning the stopper layer and the first conductive layer in the memory area; (c) forming control gates as side walls on both side faces of the patterned first conductive layer via an oxide nitride oxide (ONO) membrane in the memory area; (d) etching out the stopper layer in the logic circuit area; (e) patterning the first conductive layer in the logic circuit area to form a gate electrode of an insulated gate field effect transistor; (f) forming a second insulating layer in both the memory area and the logic circuit area; and (g) polishing the second insulating layer to expose the stopper layer in the memory area, wherein the step (d) performs over-etching to remove an upper portion of the first conductive layer, simultaneously with removal of the stopper layer.