Patent ID: 8080868
Filing Date: 2011-12-20
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a wiring board having a first surface provided with an external connection terminal, and a second surface provided with a chip mounting section and connection pads arranged on a first pad region along a first long side and a second pad region along a second long side; a first chip, arranged to the chip mounting section of the wiring board, having first electrode pads arranged along a long side which is located near the first pad region; a second chip, stacked on the first chip so as to expose the first electrode pads of the first chip, having second electrode pads arranged along a long side which is located near the second pad region; first metal wires electrically connecting the connection pads arranged on the first pad region and the first electrode pads of the first chip; second metal wires electrically connecting the connection pads arranged on the second pad region and the second electrode pads of the second chip; and a sealing resin layer formed on the second surface of the wiring board to seal the first and second chips together with the first and second metal wires, wherein the first chip has a power source terminal arranged at a corner portion of the first chip away from the first electrode pads.