Patent ID: 8630114
Filing Date: 2014-01-14
Classification: G11C,H01L

Abstract:
1. A memory device, comprising: an integrated circuit substrate; a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks being ridge-shaped and including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions; a plurality of word lines arranged orthogonally over and being conformal with the plurality of stacks; a plurality of memory elements between surfaces of the plurality of stacks and the plurality of word lines; a plurality of bit line structures coupled to multiple locations along each of the semiconductor material strips of the plurality of stacks; and a plurality of source line structures coupled to multiple locations along each of the semiconductor material strips of the plurality of stacks, wherein the plurality of bit line structures and the plurality of source line structures are between adjacent ones of the plurality of word lines.