Patent ID: 6200848
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of fabricating a self-aligned contact, wherein a substrate having a memory region and a logic region is provided, and metal oxide semiconductors (MOS) are respectively formed in the memory region and in the logic region, comprising the steps of:forming a defined dielectric layer on the substrate;forming a first contact hole in the dielectric layer in the memory region, and simultaneously forming a second contact hole in the logic region until the substrate is exposed;forming a first silicide layer over the first contact hole and a second silicide layer over the second contact hole, respectively, to couple electrically the first silicide layer and the second silicide layer to the substrate, wherein portions of the first silicide layer and the second silicide layer respectively extend to the surface of the dielectric layer neighboring the first contact hole and the second contact hole;forming a defined inter-layer dielectric layer over the substrate;forming a first via in the logic region to expose the first silicide layer and a second via in the memory region until the second silicide layer is exposed; andforming a first metal plug in the first via and a second metal plug in the second via, respectively, to coupled electrically the first silicide layer and the second silicide layer.