Patent ID: 6566924
Filing Date: 2003-05-20
Classification: G06F,H03L

Abstract:
A semiconductor integrated circuit comprising:a flip flop connected to a delay path, said flip flop having a flip flop clock input; a first up-counter connected to said flip flop, said first up-counter having a first up-counter output; a second up-counter connected to said flip flop and said first up-counter output; said second up-counter having a second up-counter output; and an on-purpose delay element connected to said second up-counter output, said on-purpose delay element having a clock input and a clock output, said clock output being connected to a latch and said flip flop clock input, and said on-purpose delay element being operable to receive a clock signal on said clock input and transmit a delayed clock signal to said latch and said flip flop clock input from said clock output, when clock skew for said latch fails to satisfy a timing constraint for said latch.