Patent ID: 9147746
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A method for fabricating an MOS transistor, comprising: providing a semiconductor substrate; forming a metal gate structure on the semiconductor substrate, the metal gate structure including a sidewall spacer; forming a source region and a drain region in the semiconductor substrate at both sides of the metal gate structure; forming a contact-etch-stop layer on the source region, the drain region and the metal gate structure; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure; forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop layer left on the bottom of the first opening covering the semiconductor substrate and the drain region within the first opening but without exposing the semiconductor substrate and any of the drain region, wherein a height of the portion of the sidewall spacer and the contact-etch-stop layer left on the bottom of the first opening is in a range of approximately 50Å-300Å; forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and contact-etch-stop layer left on the bottom of the first opening to expose the semiconductor substrate and the drain region on the bottom of the first opening; and forming a first conductive via connecting with the metal gate structure and the drain region in the first contact hole.