Patent ID: 6282583
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A method of synchronizing a plurality of processing elements at a barrier, defined as a point within an algorithm where processors executing an algorithm wait until all other processor executing the algorithm are also waiting at that point, said plurality of processing elements being connected to a plurality of buses, wherein groups of said plurality of processing elements each share access to a corresponding one of the plurality of busses and gain access to the corresponding one of the plurality of bus through a bus protocol, the method comprising the steps of:synchronizing the processing elements on ones of said plurality of buses at a said barrier, said synchronizing being relative to the other processing elements on said ones of said plurality of buses; andsynchronizing said plurality of buses relative to one another to permit simultaneous access to a system memory by at least one of the plurality of processing elements on ones of said buses and at least one of the plurality of processing elements on other ones of said buses.