Patent ID: 7667500
Filing Date: 2010-02-23
Classification: H03K

Abstract:
1. A method of suppressing a plurality of undesirable glitches on an input signal in an integrated circuit, the method comprising: generating the input signal; distributing the input signal for the integrated circuit, wherein the input signal in the integrated circuit includes a plurality of transitions and the undesirable glitches, each undesirable glitch including a rising and falling transition through a threshold of the input signal; detecting a first one of the transitions on the input signal; providing, responsive to the first transition, a first value as an output signal; generating a delay period in response to the first transition; ignoring the rising and falling transitions of at least one of the undesirable glitches on the input signal when the rising and falling transitions occur during the delay period after the first transition; detecting a second one of the transitions on the input signal; and providing, responsive to the second transition, a second value as the output signal when the second transition occurs after the delay period after the first transition, wherein the second value is different from the first value, wherein the input signal comprises an input clock signal, and the output signal comprises an output clock signal; and wherein the generating of the delay period includes measuring a frequency of the input clock signal and varying the delay period in response to the frequency of the input clock signal.