Patent ID: 6687163
Filing Date: 2004-02-03
Classification: G11C

Abstract:
Semiconductor memory arrangement having a plurality of memory sectors, the storage locations in each memory sector being connectable to a global bit line via a local bit line, and having a plurality of sense amplifiers, each sense amplifier being connectable via a data bit to one of the global bit lines, wherein the sense amplifiers are combined into a plurality of groups of sense amplifiers, the sense amplifiers in each group being connectable to a corresponding global bit line via a data bus associated with the given group, wherein the data bus number i is a data bus comprising mi bits and the group of sense amplifiers associated with data bus number i comprises mi sense amplifiers, the individual data buses and the individual groups of sense amplifiers being so designed, to allow a total of N bits to be read out from the semiconductor memory arrangement, that &Sum;i=1n&it;â€ƒ&it;mi=Nis true, where n is the number of data buses, i.e. the number of groups of sense amplifiers.