Patent ID: 7969167
Filing Date: 2011-06-28
Classification: G01D,G01P

Abstract:
1. A capacitance-to-voltage interface circuit comprising: a capacitive sensing circuit; an amplification circuit adapted for selective coupling to the capacitive sensing circuit; a capacitor bank comprising a plurality of binary-weighted capacitors, wherein each capacitor in the capacitor bank has its first conductor coupled to a common capacitor node of the capacitor bank, and each capacitor in the capacitor bank has its second conductor selectively coupled to either analog ground, a respective offset voltage, zero volts, or an upper reference voltage; and a switching architecture associated with and coupled to the capacitive sensing circuit, the amplification circuit, and the capacitor bank; wherein the switching architecture selectively couples the amplification circuit to the capacitive sensing circuit, and wherein the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in an amplification phase during which the capacitor bank is utilized for offsetting a capacitance of the amplification circuit, and for operation in an analog-to-digital conversion phase during which the capacitor bank is utilized in a successive approximation register.