Patent ID: 7262080
Filing Date: 2007-08-28
Classification: H01L

Abstract:
1. A method of manufacturing a stacked package, comprising preparing a first package having a plurality of first inner solder balls and a first semiconductor chip formed on an upper surface of a first substrate, a plurality of first outer solder balls formed on a lower surface of the first substrate, wherein the plurality of first inner solder balls and the chip are molded by a first epoxy molding compound, the plurality of first inner solder balls having exposed contact portions, the first semiconductor chip having an active surface facing the upper surface of the first substrate and a surface opposing the active surface, and the surface opposing the active surface of the first semiconductor chip and the plurality of first inner solder balls are at the same height; preparing a second package having a plurality of second outer solder balls formed on a lower surface of a second substrate, a second semiconductor chip formed on an upper surface of the second substrate, the second semiconductor chip having an active surface facing the upper surface of the second substrate, a surface opposing the active surface, the second semiconductor chip being molded by a second epoxy molding compound; stacking the second package on the first package by electrically connecting the plurality of first inner solder balls of the first substrate and the plurality of second outer solder balls; and reflowing the first package and the second package.