Patent ID: 6121808
Filing Date: 2000-09-19
Classification: H03K,H03L

Abstract:
A delay interpolation circuit comprising:a phase interpolator calibrator that takes adjacent coarse phase signals from a voltage controlled oscillator (VCO) and uses closed loop feedback to create a reference current that is used to bias a digital-to-analog converter DAC such that the full range of the DAC causes a current controlled delay cell to span a delay equal to the phase difference between adjacent coarse phase signals in a linear manner;a delay interpolator that delays a clock signal output received from a phase multiplexer by an integer multiple N of a predefined phase delay, clock signal output delay being calibrated by the phase interpolator calibrator;a delay adjuster connected to the delay interpolator for providing the value of N to the delay interpolator;a delay selector that responds to a phase difference signal corresponding to the phase difference between an incoming data signal and a reference signal by providing corresponding first and second control signals, the first control signal being provided to the delay adjuster for use in determining the value of N; anda coarse phase selector that responds to the second control signal by providing a coarse phase select signal to the phase multiplexer, the coarse phase select signal causing the phase multiplexer to select the clock signal from among a plurality of coarse phase-separated clock signals provided as inputs to the phase multiplexer.