Patent ID: 6876657
Filing Date: 2005-04-05
Classification: H04L

Abstract:
1. A system for router packet control and ordering comprising: a packet forwarding engine containing a plurality of fast data paths each interconnected with an input port and an output port; a processing block interconnected with said input ports of said packet forwarding engine through a plurality of rate matching queues; an ingress application specific integrated circuit (ASIC) containing a packet ordering block, said packet ordering block interconnected with said output ports of said packet forwarding engine through a plurality of reorder queues within said ingress ASIC; and a packet data random access memory (RAM) interconnected with said ingress ASIC, wherein said packet forwarding engine contains an exception processor, such that said fast data path bypasses said exception processor and such that said fast data path is interconnected with said exception processor through an exception data path.