Patent ID: 7502267
Filing Date: 2009-03-10
Classification: G11C

Abstract:
1. A method for wafer-level testing of serial flash memory devices, the method comprising: providing a memory tester operable in a clock frequency range from 30 to 100 MHz; providing a semiconductor wafer comprising a first plurality of serial flash memory devices, each of the first plurality of serial flash memory devices including a plurality of bonding pads for accessing internal circuits of the memory devices; selecting a second plurality of serial flash memory devices from the first plurality of serial flash memory devices; subjecting one or more of the second plurality of serial flash memory devices to a first clock signal from the memory tester; receiving a command signal at a bonding pad from the plurality of bonding pads from one of the second plurality of serial flash memory devices for activating a high-clock-frequency test mode; generating a second clock signal in the memory device in response to the first clock signal, the second clock signal being characterized by a second clock frequency which is a multiple of the first clock frequency; and testing the second plurality of memory devices at the second clock frequency.