Patent ID: 7868949
Filing Date: 2011-01-11
Classification: H03L,H04N

Abstract:
1. A circuit arrangement having at least one phase locked loop comprising: at least one phase detector for detecting phase information of at least one analog input signal following the arrival of at least one rising edge and/or falling edge of at least one analog input signal; at least one loop filter to which the output signal which is output by the phase detector is be fed, for determining at least one increment; at least one ramp oscillator to which the increment which is output by the loop filter is be fed, characterized in that the phase locked loop comprises at least one time-to-digital converter to which at least one system clock is fed, for digitizing the input signal in particular the phase of the input signal; wherein the phase detector is fed the output signal, including additional phase information, of the time-to-digital converter and also at least a first output signal in particular at least one status signal, of the ramp oscillator; and at least one frequency detector is fed at least a second output signal in particular at least one overflow pulse of the ramp oscillator and outputs frequency information to the loop filter which is assigned to at least one frequency locked loop.