Patent ID: 6055373
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A digital processing system comprising:a first processor bus;at least one central processing unit connected to said first processor bus;an I/O bus providing for the connection of at least one I/O device to said digital processing system;a first system memory;a first dual-ported memory controller connected to said first system memory, said first dual-ported memory controller having a first port connected to said first processor bus to manage transactions between said at least one central processor unit and said first system memory, and a second port connected to said I/O bus to manage transactions with said I/O bus;a second processor bus;at least one digital signal processor connected to said second processor bus;a second system memory; anda second dual-ported memory controller connected to said second system memory, said second dual-ported memory controller having a first port connected to said second processor bus to manage transactions between said at least one digital signal processor and said second system memory, and a second port connected to said I/O bus to manage transactions with said I/O bus.