Patent ID: 7935553
Filing Date: 2011-05-03
Classification: H01L

Abstract:
1. A method of making a semiconductor device, comprising: forming a first photoresist layer over an underlying layer; patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer; etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features; removing the first photoresist pattern; forming a sacrificial filler material over the plurality of first spaced apart features and in spaces between the plurality of first spaced apart features after the step of removing the first photoresist pattern; planarizing the filler material after the step of forming the filler material to expose upper surfaces of the plurality of first spaced apart features such that the filler material remains in the spaces between the plurality of first spaced apart features after the step of planarizing; and forming a second photoresist layer over the plurality of first spaced apart features and over the filler material which remains in the spaces between the plurality of first spaced apart features after the step of planarizing; patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features; etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain; removing the second photoresist pattern; and selectively removing the filler material which remains in the spaces between the spaced apart edge portions of the plurality of first spaced apart features, after the step of removing the second photoresist pattern; and etching the underlying layer using the plurality of spaced apart edge portions as a mask to form a plurality of pillar devices; wherein the plurality of pillar devices comprise a plurality of nonvolatile memory cells, each cell comprising a pillar diode steering element and a resistivity switching element.