Patent ID: 6801419
Filing Date: 2004-10-05
Classification: G05F

Abstract:
An overcurrent protection circuit for a voltage regulator, comprising: an output driver transistor for supplying an output current to a load; a first PMOS sense transistor having a gate connected to an output of an error amplifier of the voltage regulator and a source connected to an input terminal of the voltage regulator for detecting the output current supplied to the load and outputting a signal for controlling the output driver transistor to limit the output current; a first resistor having a first end and a second end, the second end being connected to a ground terminal; a first NMOS transistor having a gate connected to the first end of the first resistor; a second resistor having a first end connected to a drain of the first NMOS transistor and a second end connected to the input terminal of the voltage regulator; a PMOS transistor having a gate connected to the first end of the second resistor, a source connected to the input terminal of the voltage regulator, and a drain connected to the output of the error amplifier of the voltage regulator; a second PMOS sense transistor having a gate connected to the output of the error amplifier of the voltage regulator and a source connected to the input terminal of the voltage regulator; a first PMOS level shifter having a source connected to a drain of the first PMOS sense transistor and a drain connected to the first end of the first resistor and the gate of the first NMOS transistor; a second NMOS transistor having a source connected to the ground terminal; a second PMOS level shifter having a source connected to a drain of the second PMOS sense transistor and a drain connected to a gate and a drain of the second NMOS transistor; a third NMOS transistor having a drain connected to gates of the first PMOS level shifter and the second PMOS level shifter, a gate connected to the gate and the drain of the second NMOS transistor, and a source connected to the ground terminal; and a third PMOS level shifter having a gate and a drain connected to a drain of the third NMOS transistor and a source connected to the output terminal of the voltage regulator; wherein operating states of the output driver transistor and the first sense transistor are always the same during operation of the voltage regulator.