Patent ID: 6194937
Filing Date: 2001-02-27
Classification: H03K

Abstract:
A synchronous delay circuit system comprising:an input buffer having a first delay time and receiving an external clock;a dummy delay circuit, coupled to receive an output signal from said input buffer, having a delay time equal to a sum of said first delay time and a second delay time;a first delay circuit array including a predetermined number of delay circuits having a predetermined delay time, for measuring a time difference of a constant period from an output of said dummy delay circuit;a second delay circuit array including a predetermined number of delay circuits having a predetermined delay time, for reproducing the measured time difference and to output the reproduced time difference;a clock driver, coupled to receive said reproduced time difference, having said second delay time and outputting an internal clock;a delay time control means for controlling the traveling speed of a pulse or a signal edge progressing in said first delay circuit array and in said second delay circuit array, thereby to control an overall predetermined delay time of said first and second delay circuit arrays; anda system status measuring means, coupled to said delay time control means, for outputting a system status measuring signal indicative of the result obtained by measuring the status of the system, said delay time control means responding to said system status measuring signal to control said traveling speed.