Patent ID: 8607172
Filing Date: 2013-12-10
Classification: G06F,H01L

Abstract:
1. A method of designing an integrated circuit, the method comprising: deploying an active area in a first standard cell; routing at least one gate electrode overlapping the active area in the first standard cell; routing at least one metallic line structure overlapping the active area in the first standard cell, the at least one metallic line structure being substantially parallel to the gate electrode; routing, by using a computer, a first power rail that is substantially orthogonal to the at least one metallic line structure in the first standard cell, the first power rail overlapping the at least one metallic line structure, wherein the first power rail has a flat edge that is adjacent to the at least one metallic line structure; and deploying a first connection plug at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.