Patent ID: 8949511
Filing Date: 2015-02-03
Classification: G06F

Abstract:
1. A flash memory package comprising: a flash memory controller; a first data bus coupled to the flash memory controller; a second data bus coupled to the flash memory controller; multiple third data buses; multiple fourth data buses; multiple first flash memory chips, each of the multiple first flash memory chips coupled to one of the multiple third data buses; multiple second flash memory chips, each of the multiple second flash memory chips coupled to one of the multiple fourth data buses; a first switch coupled to the first data bus and selectively coupled to any one of the multiple third data buses; a second switch coupled to the second data bus and selectively coupled to any one of the multiple fourth data buses; and a switching signal line coupled to the flash memory controller and the first switch, wherein the first switch is configured to be coupled directly to the second switch for sending a switching signal using the switching signal line, so that the flash memory controller accesses, substantially in parallel, the one of the multiple first flash memory chips and the one of the multiple second flash memory chips by supplying one switching signal to both the first switch and the second switch using the switching signal line.