Patent ID: 6175939
Filing Date: 2001-01-16
Classification: G01R

Abstract:
An apparatus for performing tests on integrated circuits, each integrated circuit having a plurality of terminals, wherein each of said tests is organized into successive test cycles, the apparatus comprising a plurality of tester channels, wherein each tester channel comprises:data generation means for generating a sequence of control data values during each of said tests, each control data value defining a test activity to be carried out at an IC terminal during a corresponding test cycle; andtesting means for carrying out the test activity defined by each generated control data value during its corresponding test cycle,wherein test activities defined by said control data values include communicating with said IC terminal via a digital signal and communicating with said IC terminal via an analog signal,wherein said test activities defined by said control data values include generating and sending a test signal to an IC terminal, wherein said test signal is a digital signal during test cycles of some of said tests and an analog test signal during test cycles of others of said tests, andwherein said testing means comprises:digital-to-analog conversion (DAC) means for producing a first output signal of magnitude controlled by each control data value produced by said data generation means, andmeans for adjustably processing said first output in response to each control data value to produce said test signal.