Patent ID: 7547584
Filing Date: 2009-06-16
Classification: H01L

Abstract:
1. A method for reducing charging damage to integrated circuits during semiconductor manufacturing, comprising: providing a semiconductor substrate comprising thereon a number of integrated circuit dies, said integrated circuit dies being separated from each other by scribe lanes surrounding each said integrated circuit die, wherein said semiconductor substrate comprises thereon a dielectric layer; forming a mask over said dielectric layer, said mask comprising an interconnect opening and a dummy, non-interconnect opening, wherein said interconnect opening and said dummy, non-interconnect opening both are formed within each said integrated circuit die; performing a plasma etching process to etch said dielectric layer through said interconnect opening and said dummy, non-interconnect openings of said mask, thereby forming an interconnect recessed trench and a dummy recessed trench in said dielectric layer; and filling said interconnect recessed trench and said dummy recessed trench with conductive materials to form an interconnect feature and a dummy, non-interconnect feature, wherein said interconnect feature electrically connects to an underlying conductive layer, while said dummy, non-interconnect feature is floating or grounded to said semiconductor substrate; wherein said dummy, non-interconnect opening increases an in-die shunt path current flow during said plasma etching process, thereby reducing charge damage to said integrated circuit dies.