Patent ID: 7260092
Filing Date: 2007-08-21
Classification: H04J,H04Q

Abstract:
1. A time-slot interchanger for interchanging the order of subframes of data within an input data frame comprising: a global frame clock; an interchange random access memory receiving the input data frame, out of alignment with the global frame clock, at an input; a write address generator which addresses the interchange random access memory to write subframes, out of alignment with the global frame clock, in a received order, wherein the write address generator generates the write address from a count of a local frame counter synchronized to the input data frame; a global frame counter comprising (a) a delay block configured to receive the global frame clock and present a start of frame signal and (b) a counter circuit configured to generate a count in response to the start of frame signal and a byte clock, wherein the delay block delays the global frame clock by a predetermined number of byte clocks and the count comprises (i) a subframe field, (ii) a column field, (iii) a column-group field and (iv) a row field; and a read address generator which addresses the interchange random access memory to read subframes in interchanged order and aligned to the global frame clock, wherein the read address generator transforms the count of the global frame counter to generate the read address.