Patent ID: 8779795
Filing Date: 2014-07-15
Classification: H01L

Abstract:
1. A semiconductor chip mountable over a desired one of a first package having N-number (N is a natural number) of first terminals and a second package having M-number (M is an integer larger than N) of second terminals, the semiconductor chip comprising N-number of first pads and (M−N)-number of second pads, wherein, in a case where the semiconductor chip is mounted over the first package, the N-number of first pads are respectively coupled to the N-number of first terminals via N-number of bonding wires, and in a case where the semiconductor chip is mounted over the second package, the N-number of first pads and the (M−N)-number of second pads are respectively coupled to the M-number of second terminals via M-number of bonding wires, wherein a selected second pad of the (M−N)-number of second pads is divided into first and second electrodes insulated from each other, and wherein the first and second electrodes are arranged at a predetermined interval therebetween, and when a corresponding second pad is coupled to the corresponding second terminal via the bonding wire, short by an end part of the bonding wire occurs, the semiconductor chip further comprising an internal circuit operating as a first semiconductor device having the N-number of first terminals in a case where the first and second electrodes are insulated from each other and operating as a second semiconductor device having the M-number of second terminals in a case where the first and second electrodes are shorted therebetween.