Patent ID: 6691238
Filing Date: 2004-02-10
Classification: G06F

Abstract:
A computer system comprising:a processor and a main memory unit; a control element that instructs the processor and the main memory unit to enter a sleeping state; a disable element to disable wake events from waking up the system when the disable element is in a waking disabled state, wherein the disable element also has a waking enabled state; a front panel switch operable to generate a wake event during the sleeping state; a wake signal line driven by the front panel switch; an operating system that disables recognition of all wake events during the sleeping state other than wake events appearing on the wake signal line; at least one hardware component other than the front panel switch that is operable to generate a wake event during the sleeping state; and a wake circuit that places the wake event from said hardware component onto the wake signal line if both the processor is in the sleeping state and the disable element is in the waking enabled state, wherein the disable element comprises a disable signal line, and wherein the disable signal line is connected to a BIOS component.