Patent ID: 8830111
Filing Date: 2014-09-09
Classification: G04F

Abstract:
1. A method for clockless conversion of time interval to digital word consisting in a detection of the beginning and of the end of the time interval by the use of the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and delivered by the use of a current source while the portion of electric charge is accumulated in a sampling capacitor, or in the sampling capacitor and in a capacitor having the highest capacitance value in an array of redistribution, which is connected to the sampling capacitor in parallel, and then consisting in the realization of the process of accumulated electric charge redistribution in the array of redistribution in a known way by means of a control module by changes of states of signals from relevant control outputs, while the array of redistribution comprises an array of on-off switches, of change-over switches and of capacitors such that a capacitance value of each capacitor of a given index is twice as high as a capacitance value of a capacitor of a previous index, and also consisting in the assignment of relevant values to bits of the digital word by means of the control module characterized in that after termination of accumulation of electric charge in the sampling capacitor (C n ), or in the sampling capacitor (C n ) and in the capacitor (C n−1 ) having the highest capacitance value in the array of redistribution which is connected to the sampling capacitor (C n ) in parallel, and after detection of the beginning of the next time interval (T x+1 ) by means of the control module (CM), electric charge is delivered by the use of the current source and accumulated in the additional sampling capacitor (C nA ), and next the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) is realized and relevant values are assigned to bits (b n−1 , b n−2 , b 1 , b 0 ) in the digital word by means of the control module (CM) while accumulation of electric charge in the additional sampling capacitor (C nA ) and the process of redistribution of electric charge accumulated in the additional sampling capacitor (C nA ) and assignment of relevant values to bits (b n−1 , b n−2 , b 1 , b 0 ) in the digital word are realized such as for the sampling capacitor (C n ).