Patent ID: 6204117
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method of forming a capacitor, comprising the steps of:providing a semiconductor substrate having a semiconductor body formed thereon;forming a first insulating layer above said substrate and overlaying said semiconductor body;patterning said first insulating layer to define a contact hole for said capacitor;depositing an amorphous silicon layer as a first conductive layer over said first insulating layer and filling up said contact hole;forming a silicon oxynitride layer on said amorphous silicon layer to serve as photo bottom anti-reflective coating (BARC) and etching hard mask for capacitor patterns;patterning said silicon oxynitride layer and said amorphous silicon layer to form a lower capacitor electrode;removing said silicon oxynitride layer to expose the entire upper surface of said lower capacitor electrode, through a wet etching method utilizing phosphoric acid (H.sub.3 PO.sub.4) solution at temperature about 150.degree. C.;forming a selective hemispherical gram (s-HSG) silicon layer as a second conductive layer over the entire exposed surface of said lower capacitor electrode;forming a second insulating layer along a surface of the resulting structure and over said second conductive layer; andforming a third conductive layer over said second insulating layer serve as an upper capacitor electrode.