Patent ID: 7189612
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. A method for manufacturing a ferroelectric memory, comprising the steps of: forming a transistor in one region on a semiconductor substrate; forming a conductive layer in another region on the semiconductor substrate; forming a first interlayer insulating film on the semiconductor substrate including the transistor and the conductive layer; forming a first plug connected to the transistor and a second plug connected to the conductive layer through the first interlayer insulating film; forming a capacitor lower electrode on the first interlayer insulating film so as to be connected to the first plug and a connection pad on the first interlayer insulating film so as to be connected to the second plug; forming a capacitor insulative film made of a ferroelectric film on the capacitor lower electrode so as to extend over and span a space between the capacitor lower electrode and the connection pad; forming an opening in a portion of the capacitor insulative film that is above the second plug; forming a capacitor upper electrode on the capacitor insulative film including the opening so as to be electrically connected to the connection pad via the opening; and forming a wiring so as to be electrically connected to the capacitor upper electrode via the conductive layer and the second plug, wherein the step of forming the opening is performed before patterning an insulating film to be the capacitor insulative film; and the step of forming the capacitor upper electrode includes the step of simultaneously patterning the insulative film to be the capacitor insulative film and a conductive film to be capacitor upper electrode.