Patent ID: 7184509
Filing Date: 2007-02-27
Classification: H03K,H03L

Abstract:
1. A delay locked loop circuit having a duty cycle corrector, the delay locked loop circuit comprising: a phase detector that detects a phase difference between an external clock signal and feedback internal clock signals and generates up-signals and down-signals corresponding to the phase difference; a first control circuit that, in response to the up-signals and the down-signals, generates first control signals for coarse locking of the phase difference between the external clock signal and the feedback internal clock signals and generates second control signals for fine locking of the phase difference; a second control circuit that, in response to the up-signals and the down-signals, generates third control signals for coarse duty error correction of the external clock signal and generates fourth control signals for fine duty error correction of the external clock signal; and a delay line unit that includes a plurality of delay cells connected in series, delays the external clock signal through the delay cells, selects output signals of first delay cells from the plurality of delay cells in response to some of the first control signals, selects output signals of second delay cells from the plurality of delay cells in response to others of the first control signals, and selects output signals of third delay cells from the plurality of delay cells in response to the third control signals.