Patent ID: 6292093
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A comparator network for deriving a first binary output level in response to first and second like ordered binary bits of first and second binary bytes or words having the same value and for deriving a second binary output level in response to any of the first and second like ordered binary bits of the first and second binary bytes or words having differing values, the comparator network includinga load;a power supply terminal; andfor each of the like ordered bits a comparator circuit having: first and second signal input terminals for being respectively responsive to the first and second binary input bits, first and second transistors respectively having first and second variable impedance paths and first and second control electrodes, the impedances of the first and second paths being respectively controlled by binary levels applied to the first and second control electrodes; the first variable impedance path and the load being connected in series between the first input signal terminal and the power supply terminal; the second variable impedance path and the load being connected in series between the second input signal terminal and the power supply terminal; the connections of the first and second variable impedance paths, the load and the power supply terminal being such that current can flow between the first and second signal input terminals and the power supply terminal via the first and second variable impedance paths and a common terminal for the first and second variable impedance paths, the first control electrode being connected to respond to the second binary signal at the second signal input terminal, the second control electrode being connected to respond to the first binary signal at the first signal input terminal, the connections, transistors, load and common terminal being arranged so that (1) in response to the first and second binary input bits having: (a) the same first values the variable impedances of the first and second transistors are sufficiently low that the first values of the first and second bits are coupled through the variable impedances of the first and second transistors to the common terminal and (b) the same second values the variable impedances of the first and second transistors are sufficiently high that the values of the first and second bits are de-coupled from the common terminal whereby the common terminal is substantially at the voltage of the power supply terminal, the power supply terminal being at a voltage approximately equal to the voltage of the first and second bits as coupled through the first and second transistors to the common terminal so the first binary output level is derived at the common terminal and (2) in response to the first and second input signals having differing values (a) the transistor having its variable impedance path connected to the input signal terminal responsive to the binary bit having the first value has a sufficiently high impedance path to decouple the binary bit having the first value from the common terminal, and (b) the transistor having its variable impedance path connected to the input signal terminal responsive to the binary bit having the second value has a sufficiently low impedance path to couple the binary bit having the second value to the common terminal so the second binary output level is derived at the common terminal, each of the comparators being connected to the first and second signal input terminals so as to be simultaneously responsive to a different pair of binary bits, the variable impedance paths of the transistors of each of the comparators being connected for selectively providing a current path between the common terminal and the signal input terminal associated with each of the binary bits, and an impedance connected between the common terminal and the variable impedance paths of each comparator circuit, each of the impedances being arranged for preventing the common terminal from being at the first binary output level in response to any of the comparator circuits causing the common terminal to be at the second binary level.