Patent ID: 6018183
Filing Date: 2000-01-25
Classification: H01L

Abstract:
A structure of an electrostatic discharge protective circuit for SRAM, in which at least one MOS transistor formed on a semiconductor substrate is coupled between an input port and an internal circuit, and an input bonding pad is coupled to said input port and said internal circuit, comprising:a drain of said MOS transistor;a gate of said MOS transistor;a source of said MOS transistor connected to said gate via a polysilicon layer which is coupled to a potential line, wherein said source is not deeper than said drain;a dielectric layer formed on said drain, said gate and said source;a metal layer formed on said dielectric layer, wherein the metal layer covers substantially whole upper surface of the dielectric layer and does not directly contacts the semiconductor substrate, and said input bonding pad is formed on and directly connected to said metal layer and located directly over the top of said MOS transistor; anda via connecting said drain to said metal layer.