Patent ID: 6133111
Filing Date: 2000-10-17
Classification: G03F,H01L

Abstract:
A method of making a semiconductor structure including a photo alignment target built with an integrated circuit transistor, the integrated circuit transistor have drain, gate, and source regions and being isolated by at least one field oxide region, the semiconductor structure comprising the steps of:depositing a first dielectric layer on the field oxide region;defining at least one opening in the first dielectric layer located above the field oxide having a depth more than the overall thickness of the first dielectric layer but less than the thickness of field oxide and first dielectric layer combined;depositing a first conductive layer over the opening of the first dielectric layer conforming to the opening forming a depression therein, the first conductive layer having a planar top surface; anddepositing a second conductive layer over the planar surface of the first metal layer and conforming to the opening, to provide a topography change recognizable by an alignment apparatus.