Patent ID: 6723657
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A method for fabricating a gate stack above a substrate section covered by a gate oxide layer, in very large scale integrated semiconductor memories, which comprises the following steps:a) applying a polysilicon layer above the gate oxide layer; b) applying a silicon nitride layer above the polysilicon layer as a mask layer for a subsequent damascene process; c) selectively etching an opening, with a side wall and a base, into the silicon nitride layer, down to the polysilicon layer, in the substrate section; d) covering the silicon nitride layer, including the side wall and the base of the opening, with a Ti or Co layer; e) converting the Ti or Co at the base of the opening into a silicide section through a conditioning process; f) removing unsilicided Ti or Co; g) forming a covering layer entirely over the substrate section, covering the silicon nitride layer and filling the opening above the silicide section; h) removing the covering layer down to the silicon nitride layer, while retaining the covering layer in the opening; i) selectively etching the silicon nitride layer down to the polysilicon layer, leaving a gate stack formed of TiSi2 or CoSi2 and a section of the covering layer remaining above the TiSi2 or CoSi2, in the opening; j) selectively etching the polysilicon layer down to the gate oxide, with the gate stack functioning as a hard mask; and k) applying a spacer wall around a periphery of the gate stack.