Patent ID: 8996899
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A processor, comprising: a plurality of processor cores including a first processor core and a second processor core that is coupled to the first processor core, both the first and second processor cores comprising respective instruction decoding circuitry, instruction execution engine circuitry, clock modification circuitry and voltage modification circuitry; a first power control logic within or otherwise associated with the first processor core and a second power control logic within or otherwise associated with the second processor core; and wherein the first power control logic is to control power consumption of the first processor core in response to a combination of detected activity and power consumption of the first processor core and independently of any detected activity and power consumption of the second processor core, wherein the first power control logic is to control at least one of the clock modification circuitry and the voltage modification circuitry of the first processor core to control the first processor core power consumption.