Patent ID: 9077452
Filing Date: 2015-07-07
Classification: H04B,H04L

Abstract:
1. An apparatus comprising: a first set of signal pins configured to plug into an enhanced Small Form-Factor Pluggable (SFP+) transceiver module capable of sending and receiving signals at a data rate of ten gigabits per second (10G); a second set of signal pins configured to plug into an enhanced Quad SFP+ (QSFP+) host port capable of sending and receiving signals at a data rate of forty gigabits per second (40G) from a QSFP+ transceiver module; a retimer unit that is configured to modify a 10G signal of a first electrical signal standard associated with the SFP+ transceiver module to a 10G signal of a second electrical signal standard associated with the QSFP+ transceiver module and to modify a 10G signal of the second electrical signal standard to a 10G signal of the first electrical signal standard, wherein the second set of signal pins comprises four signal path pairs and the retimer unit is configured to interface with one of the four signal path pairs; a plurality of terminator units configured to terminate signal transmission along the signal path pairs that are not interfaced with the retimer unit; and a microcontroller manager configured to modify management signals of a first management signal standard associated with the SFP+ transceiver module to management signals of a second management signal standard associated with the QSFP+ transceiver module.