Patent ID: 6534817
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A contactless channel write/erase flash memory cell comprising:a multi-level substrate; a tunnel oxide layer formed on the multi-level substrate; a first ion doped region as a drain located in said substrate; a floating gate formed above said substrate and next to said first ion doped region; a second ion doped region formed in the surrounding area of said first ion doped region; a third ion doped region formed under said floating gate and being in contact with said second ion doped region; a fourth ion doped region as a source located in said substrate and being in contact with said third ion doped region; two isolating oxide layers formed over said first ion doped region and said fourth ion doped region; a dielectric layer formed on said floating gate and said isolating oxide layer; and a control gate formed over said floating gate and said isolating oxide layer; wherein said floating gate comprises a first floating gate formed above said third ion doped region between said two isolating oxide layers, and a second floating gate that is short-circuited with said first floating gate, formed above said first floating gate and partially covering said two isolating oxide layers.