Patent ID: 6571352
Filing Date: 2003-05-27
Classification: G11C

Abstract:
A semiconductor memory circuit comprising:a primary array; a redundant array having a redundant row; data path circuitry coupled to said primary array and said redundant array for writing data to and reading data from said primary array and said redundant array; a first set of non-volatile elements for storing a block repair configuration; routing circuitry coupled to said first set of non-volatile elements to be configured by said block repair configuration to output a selected ratio of received row address bits to received column address bits; a second set of non-volatile elements for storing a portion of an address of a defective cell of said primary array; and comparison circuitry coupled to said second set of non-volatile elements, said redundant array, said data path circuitry, and said routing circuitry for comparing row and column address bits output by said routing circuitry with said stored portion of said defective cell address and, when a match occurs, for implementing a block repair of said defective cell by activating said redundant row in said redundant array and directing said data path circuitry to write data to, or read data from, said activated redundant row instead of said primary array.