Patent ID: 6226219
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A semiconductor memory, comprising:a plurality of memory banks divisible into a first group of memory banks and a second group of memory banks, each of said memory banks includinga memory cell field in which a multiplicity of memory cells are arranged in a matrix;an address decoder connected to said memory cells for selecting a row in the matrix of memory cells;input devices for supplying an address with a number of address bits and defining a selection of a respective row in one of said memory cells by actuating said address decoder;a first memory bank decoder having an input side connected to receive a first portion of the address bits and a first enable signal, and an output side connected to said first group of memory banks, said first memory bank decoder outputting a respective bank selection signal for each said memory bank in said first group, for selecting one of said memory banks in said first group;a second memory bank decoder constructed substantially identically to said first memory bank decoder and connected to said second group of memory banks, said second memory bank decoder having an input side connected to receive the first portion of the address bits and a second enable signal, and an output side outputting a respective bank selection signal for each said memory bank in said second group, for selecting on of said memory banks in said second group; anda predecoder having a logic circuit, an input side connected to receive a second portion of the address bits and a further enable signal, and an output side outputting the first and second enable signals as mutually complementary signals.