Patent ID: 6818512
Filing Date: 2004-11-16
Classification: G11C,H01L

Abstract:
A method of forming a multi-bit flash cell comprising the steps of:providing a semiconductor substrate having active and passive regions defined; forming a first dielectric layer over said substrate; forming a first polysilicon layer over said first dielectric layer; forming a plurality of floating gates comprising said first polysilicon layer, wherein said plurality of floating gates are spaced apart by a plurality of openings over said first dielectric layer; forming a second dielectric layer over said plurality of floating gates, including said plurality of openings; forming a second polysilicon layer over said second dielectric layer; forming a plurality of control gates comprising said second polysilicon layer over said second dielectric layer over said plurality of floating gates; forming a third dielectric layer over said plurality of control gates; forming a fourth dielectric layer over the inside walls of said plurality of openings; forming a third polysilicon layer over first of said plurality of openings to form a first bit line over said substrate, and over last of said plurality of openings to form a second bit line over said substrate; forming a fifth dielectric layer over said first bit line and over said second bit line; and forming a fourth polysilicon layer over said fifth dielectric layer, including over said plurality of openings, to form a word line contacting select gates on said semiconductor substrate.