Patent ID: 6448101
Filing Date: 2002-09-10
Classification: H01L,Y10S

Abstract:
A method of integrating a photodiode and a complementary metal-oxide semiconductor (CMOS) transistor with a non-volatile memory (NVM) on a semiconductor substrate, the semiconductor substrate comprising a photo sensor region for forming the photodiode, a periphery circuit region for forming the CMOS transistor, and a memory cell region for forming the non-volatile memory cell, the method comprising:performing a first ion implantation process to form a first doped area within the semiconductor substrate in the periphery circuit region, the photo sensor region and the memory cell region; performing a second ion implantation process to form a second doped area within the semiconductor substrate in the periphery circuit region; patterning a plurality of active areas on the surface of the semiconductor substrate and forming an insulating layer on opposite sides of each active area; forming an oxide-nitride-oxide (ONO) dielectric layer on the surface of the semiconductor substrate; performing a third ion implantation process to form a third doped area on the first doped area in the photo sensor region, and form a fourth doped area on the first doped area in the memory cell region; removing the ONO dielectric layer in the photo sensor region and the periphery circuit region, and removing the ONO dielectric layer on the surface of the fourth doped area in the memory cell region; performing a thermal oxidation process to grow a protection oxide layer on the third doped area, a gate oxide layer on the first and the second doped areas in the periphery circuit region, and a field oxide layer on the fourth doped area; forming a gate on the gate oxide layer and the field oxide layer in each active area; and forming a source and a drain adjacent to the gate in the periphery circuit.