Patent ID: 6487176
Filing Date: 2002-11-26
Classification: H04L,H04Q

Abstract:
A measuring method for data communications networks using ATM cells, the ATM cells having 53 eight-bit width data words with 47 of the 53 data words being payload data from originally synchronous digital data strings, a cell-by-cell reading out of the payload data being possible so as to be fed consecutively as burst data to a data test receiver, the data test receiver being able to ascertain a correct or corrupted receipt of transmitted data, the method comprising:receiving parallel data together with a first block clock pulse of 19.44 Mbit/s and a cell starting pulse in an ATM cell evaluation circuit; extracting the payload data of each ATM cell and feeding the payload data to data inputs of a memory; reading the 47 data words of the payload data of each ATM cell one after another into the memory using a timed write signal, the write signal being fed by the ATM cell evaluation circuit to the memory, the memory having a write signal input for the write signal; starting a clock-pulse burst generator as a function of a filling level of the memory, the clock-pulse burst generator being timed by a second block clock pulse so as to produce a first clock-pulse burst, a second clock-pulse burst and a third clock-pulse burst; reading out the 47 data words of the payload data using the first clock-pulse burst, the 47 data words being read out one after another out of the memory and being fed to parallel inputs of a parallel-to-serial converter; supplying the parallel-to-serial converter at a load input for shift/load signals with a specific number of load pulses and supplying the parallel-to-serial converter at a clock-pulse input with clock pulses, the clock pulses and the load pulses being produced by the second and third clock-pulse bursts; and relaying the payload data from a serial output of the parallel-to-serial converter to a burst-data output in a rhythm of the clock pulses.