Patent ID: 7191342
Filing Date: 2007-03-13
Classification: G06F,H04L

Abstract:
1. A programmable logic device comprising: an array of configuration memory, the array including a plurality of physical memory frames; a frame buffer connected to the physical memory frames and adapted to store a series of configuration data frames in corresponding ones of the physical memory frames; a configuration access port adapted to receive composite data frames, each composite data frame including at least one encrypted configuration data bit associated with a first sub-design comprising a proprietary portion and at least one unencrypted configuration data bit associated with a second sub-design comprising an application specific portion; and a selective decryptor having an input node connected to the configuration access port and an output node connected to the frame buffer, wherein the selective decryptor is adapted to decrypt the encrypted configuration data bit to create a decrypted configuration data bit and to convey the unencrypted configuration data bit and the decrypted configuration data bit to the frame buffer.