Patent ID: 6412059
Filing Date: 2002-06-25
Classification: G06F,Y02D

Abstract:
A cache memory control method for reading information requested by a processor from a cache memory or a main memory of a data processing device and supplying the information to said processor, said data processing device including tag memories for storing tags constituting addresses corresponding to information stored in said cache memory, a first buffer for temporarily storing a tag read out from said tag memories, a second buffer for temporarily storing an information read out from said main memory and a third buffer for temporarily storing an address of an information temporarily stored in said second buffer, said cache memory control method comprising the steps of:a first step of reading the information from said cache memory or said second buffer and supplying the information to said processor when an address supplied from said processor and corresponding to the information requested by said processor or a tag constituting the address is coincident with an address temporarily stored in said third buffer or a tag temporarily stored in said first buffer, or reading the tag constituting the address supplied from said processor from said tag memories and temporarily storing the tag in said first buffer when the address supplied from said processor and corresponding to the information requested by said processor or the tag constituting the address is not coincident with the address temporarily stored in said third buffer or the tag temporarily stored in said first buffer; and a second step of reading the information from said cache memory and supplying the information to said processor when the tag constituting the address supplied from said processor is coincident with the tag temporarily stored in said first buffer or reading the information from said main memory on the basis of the address supplied from said processor, temporarily storing the information in said second buffer and in said cache memory and temporarily storing addresses temporarily stored in said third and second buffers when the tag constituting the address supplied from said processor is not coincident with the tag temporarily stored in said first buffer.