Patent ID: 6512685
Filing Date: 2003-01-28
Classification: G11C

Abstract:
A content addressable memory (CAM) circuit comprising:a plurality of CAM cells, each CAM cell including: a memory cell having a storage node for storing a first data value transmitted on a bit line in response to a control signal transmitted on a word line during a write operation, a logic portion including a comparator for receiving the first data value from the memory cell and a second data value transmitted on a data line during a compare operation during which an applied data value is compared with a plurality of data values stored by the plurality of CAM cells, wherein the comparator opens a path between a match line and a discharge line when the first data value fails to match the second data value; means for controlling the memory cell of a selected CAM cell of the plurality of CAM cells such that the storage node of the memory cell is selectively coupled to a first operating voltage during the write operation; and means for controlling the logic portions of the plurality of CAM cells such that the match lines are coupled to a second operating voltage before the compare operation, wherein the first operating voltage is greater than the second operating voltage.