Patent ID: 7320926
Filing Date: 2008-01-22
Classification: H01L

Abstract:
1. A method for fabricating a n+ to n+ capacitor, comprising: providing a stop layer on a substrate; etching a plurality of trenches through said stop layer and into said substrate; depositing a first layer over said stop layer and filling said trenches wherein said first layer comprises a dielectric material having a first dielectric constant; planarizing said first layer to said stop layer leaving said first layer within said trenches; thereafter removing said first layer from a subset of said trenches; depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant; planarizing said second layer to said stop layer leaving said second layer within said subset of trenches; and forming n+ junctions on either side of one of said subset of trenches, wherein said one of said subset of trenches forms a capacitor dielectric of said n+ to n+ capacitor.