Patent ID: 7924863
Filing Date: 2011-04-12
Classification: H04L

Abstract:
1. A device, comprising: multiple MAC-PHY circuits coupled to a first interface that is controlled by a first controller; a first shared memory unit coupled to the first interface; multiple shared layer-two processors; a data transfer monitor adapted to monitor a progress of provision of data to the first shared memory unit; a first double data rate (DDR) controller, coupled between the first shared memory unit and a DDR memory unit; wherein at least one MAC-PHY circuit is adapted to store a data chunk of a large data packet; wherein the first controller is adapted to control a provision of data chunks from the multiple MAC-PHY circuits via the first interface to the first shared memory unit; wherein the shared layer-two processors are adapted to perform data chunk processing operations and data packet processing operations, based upon the progress of provision of data to the first shared memory unit; and wherein the DDR controller is adapted to provide data chunks from the first shared memory unit to the DDR memory unit.