Patent ID: 8339167
Filing Date: 2012-12-25
Classification: G11C,H03L

Abstract:
1. A synchronizing circuit, comprising: a first signal path; a second signal path; a trim circuit including first and second adjustable delay circuits configured to selectively add adjustable delay to either the first signal path or the second signal path, wherein each of the adjustable delay has a range from an intrinsic delay to a maximum delay; and a trim decoder coupled to the trim circuit and being configured to provide first and second trim control signals to the first and second adjustable delay circuits respectively, the trim decoder being programmed so that one of the first and second trim control signals sets its respective adjustable delay at substantially the intrinsic delay of the respective delay circuit while the other of the first and second trim control signals sets its respective adjustable delay to a delay that is less than the maximum delay of the respective delay circuit.