Patent ID: 7728621
Filing Date: 2010-06-01
Classification: H03K

Abstract:
1. A leakage reduction circuit, comprising: a virtual ground node; a plurality of leaking transistors coupled between the virtual ground node and a power supply node; a first NMOS transistor coupled between the virtual ground node and a ground node, the first NMOS transistor having its gate driven by an enable signal asserted during normal operation of the plurality of leaking transistors; a second NMOS transistor having a drain to the virtual ground node, the second NMOS transistor having its gate driven by a standby signal asserted during a standby mode for the plurality of leaking transistors; and a native NMOS transistor coupled between a source of the second NMOS transistor and the ground node, the native NMOS transistor having a gate driven by the virtual ground node, wherein the first NMOS transistor is sized so as to supply a necessary current during normal operation and wherein the second NMOS transistor is smaller than the first NMOS transistor such that a voltage for the virtual ground node raises above ground to reduce leakage by the plurality of leaking transistors during the standby mode.