Patent ID: 6173243
Filing Date: 2001-01-09
Classification: G06F

Abstract:
A system for memory incoherent verification of functionality of an HDL design of a computer system component configured to interface between a first bus and a second bus, said system being executable by a computer system having a memory and a CPU, said system comprising:a simulated model of said HDL design of said computer system component which receives a memory read stimulus on a simulation of said first bus and responds with a memory read transaction according to said HDL design on a simulation of said second bus;a transaction checker stored in said memory and coupled to receive information relating to bus cycles corresponding to said memory read transaction initiated on said simulation of said second bus by said simulated model of said HDL design of said computer system component in response to said memory read stimulus; anda stimulus file stored in said memory which specifies said memory read stimulus be applied to said simulation of said first bus,wherein said transaction checker is configured to verify said bus cycles corresponding to said memory read transaction of said HDL design of said computer system component independently of a status of a memory write stimulus from said stimulus file.