Patent ID: 6329677
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A field effect transistor comprising:a semiconductor lamination structure having a principal surface;a gate electrode disposed on the principal surface and forming a Schottky contact with the principal surface;a source electrode disposed on the principal surface on one side of said gate electrode and having an ohmic contact with the principal surface;a drain electrode disposed on the principal surface on another side of said gate electrode and having an ohmic contact with the principal surface;a source region disposed in said semiconductor lamination structure under said source electrode and forming a current deriving region;a drain region disposed in said semiconductor lamination structure under said drain electrode and forming a current deriving region;a channel layer disposed in said semiconductor lamination structure spaced apart from the principal surface and disposed to be connected to said source and drain regions;a barrier layer disposed in said semiconductor lamination structure between said channel layer and the principal surface and having a conduction band edge energy higher than a conduction band edge energy of said channel layer;a source impurity doped region formed in said barrier layer and said channel layer continuously with said source regions on the one side of said gate electrode, a carrier density in said barrier layer being lower than a carrier density in said channel layer, in the source impurity doped region; anda drain impurity doped region formed in said barrier layer and said channel layer continuously with said drain region on said another side of said gate electrode, a carrier density in said barrier layer being lower than a carrier density in said channel layer, in the drain impurity doped region,wherein a carrier density distribution of said source impurity doped region in a depth direction is higher than a carrier density distribution of part of said drain impurity doped region.