Patent ID: 6849903
Filing Date: 2005-02-01
Classification: H01L,H03K,Y10S

Abstract:
1. A semiconductor integrated circuit, manufactured by forming wiring on a bulk chip comprising a plurality of basic cells arranged in an array, wherein: said basic cells comprise first, second, third and fourth P-channel MOS transistors, and first and second N-channel MOS transistors; said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed; said third P-channel MOS transistor and said fourth P-channel MOS transistor are juxtaposed; said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed; the gates of each of said transistors are parallel to each other; the gate of said first P-channel MOS transistor and the gate of said third P-channel MOS transistor are connected in a line; the gate of said second P-channel MOS transistor and the gate of said fourth P-channel MOS transistor are connected in a line; the gate of said third P-channel MOS transistor and the gate of said first N-channel MOS transistor are provided in a line; the gate of said fourth P-channel MOS transistor and the gate or said second N-channel MOS transistor are provided in a line; and, the gate width W