Patent ID: 9029203
Filing Date: 2015-05-12
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor package, comprising: forming on a substrate a metal layer with patterned trenches; forming a plurality of traces and connection pads in the patterned trenches, wherein a thickness of each of the traces and connection pads is greater than a depth of each of the patterned trenches; forming an insulating layer for encapsulating the traces and connection pads on the metal layer in a manner that bottom surfaces of the connection pads are exposed from the insulating layer; removing a portion of the substrate and the metal layer, so as for the traces and connection pads to be exposed and protruded from the insulating layer; attaching a semiconductor chip to the traces by a plurality of bumps; and forming an encapsulant on the insulating layer for encapsulating the semiconductor chip, the bumps, the traces and the connection pads.