Patent ID: 6314563
Filing Date: 2001-11-06
Classification: G06F,Y10S

Abstract:
A computer system configured by computer instructions to operate as a compiler/interpreter that:A) in response to electrical signals representing source code that calls for allocation of an object on which thread execution can be synchronized, produces electrical signals representing object code that directs a processor to allocate to the object an object structure that includes a lock-word field of which a synchronization-state field is a part; andB) in response to electrical signals representing source code that calls for a synchronizing execution thread to lock the object, produces electrical signals representing object code that directs the processor in some circumstances to:i) perform on the object's lock-word field an atomic lock compare-and-swap operation that:a) is successful, performing a lock operation by replacing prereplacement contents of the object's lock-word field with a lock word in which the synchronization-state field contains a synchronization-state code indicating that the object is locked and not meta-locked without first placing a meta-lock-indicating synchronization code in the synchronization-state field, only if the synchronization-state field in the pre-replacement lock-word-field contents indicate that the object is neither synchronized on nor meta-locked; andb) is otherwise unsuccessful and does not replace the pre-replacement contents of the object's synchronization-state field; andii) if the lock compare-and-swap operation is unsuccessful:a) perform a meta-lock-acquisition operation by replacing pre-replacement contents of the object's lock-word field with a lock word in which the synchronization-state field contains a synchronization-state code indicating that the object is meta-locked; andb) thereafter perform a lock operation on the object.