Patent ID: 6284608
Filing Date: 2001-09-04
Classification: H01L

Abstract:
A method of making an n-channel Silicon on Insulator (SOI) transistor comprising:making a trench isolation thus defining the body region of the transistor;delivering a deep p-type and a shallow n-type implant to the body region through an insulating layer formed over the body region;forming a gate over the body region and separated therefrom by a gate oxide;forming spacers and liners over the body region and adjacent said gate;implanting the body region with n-type dopants to form source and drain regions separated from each other by a channel;removing the spacer and performing a tilted channel implant to form p-type regions adjacent each of the source and drain regions and disposed along the channel;delivering a shallow p-type implant after removing the spacers; and delivering a deep p-type implant.