Patent ID: 6329706
Filing Date: 2001-12-11
Classification: H01L

Abstract:
A semiconductor package comprising:a leadframe including inner lead, outer lead, and a chip pad, the outer leads being correspondingly connected to the inner leads of the leadframe, extending out of the semiconductor package, the chip pad having a first surface on which a chip is mounted, and a second surface which is opposite to the first surface and is partially exposed to the outside of the semiconductor package;a chip mounted on the first surface of the chip pad and sealed by epoxy;gold wires for connecting bonding pads of the chip to corresponding inner leads of the leadframe; andan epoxy mold compound (EMC) covering the first surface of the chip pad and inner leads, but exposing a portion of the second surface of the chip pad;wherein the chip pad of the leadframe comprises:at least two swaged portions formed along edges of the chip pad of the leadframe;a first narrow and long groove formed on the first surface of the chip pad of the leadframe;a second narrow and long groove formed on the second surface of the chip pad of the leadframe along the edge thereof, not to be covered with the EMC; andat least one slot formed in the chip pad of the leadframe.