Patent ID: 7149914
Filing Date: 2006-12-12
Classification: H03L,H04L

Abstract:
1. Circuitry operative in two modes for providing a dynamically adjustable bandwidth comprising: a phase frequency detector receiving as input a clock signal and having a signal output; a phase detector receiving as input a clock data recovery (CDR) signal and having a signal output; a charge pump having a pump input coupled to the signal output of the phase frequency detector during a first of the two modes, and coupled to the signal output of the phase detector during a second of the two modes, and having a pump output; a loop filter having a filter input coupled to the pump output of the charge pump and having a filter output; a voltage controlled oscillator having an oscillator input coupled to the filter output of the loop filter and having an oscillator output; a divider circuit having a divider input coupled to the oscillator output of the voltage controlled oscillator and having a divider output that feeds back to the input of the phase frequency detector; and control circuitry that receives as input at least one control signal and is operative to dynamically adjust a setting in at least one of the charge pump, the loop filter, the voltage controlled oscillator, and the divider circuit while the circuitry is processing data.