Patent ID: 7785945
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A method for fabricating a PMOS transistor, comprising: forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer to form an asymmetrically etched polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant to form an asymmetrically etched doped polysilicon layer; diffusing the dopant in the asymmetrically etched doped polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched doped polysilicon layer to form a planarized polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which defines a region to be formed with a gate of the PMOS transistor, over the gate metal layer; patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer to form a gate stack; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.