Patent ID: 6326825
Filing Date: 2001-12-04
Classification: H03L

Abstract:
A time delay system using an accurate clock signal for calibration, the time delay system comprising:means for generating an inaccurate clock signal, the frequency of the inaccurate clock signal being lower than the frequency of the accurate clock signal;first means for counting a number of cycles of the accurate clock signal that occur during a predetermined portion of the inaccurate clock signal;means for calculating a desired number of cycles of the inaccurate clock signal representing a desired time delay using the number of cycles of the accurate clock signal from the first counting means, the number of periods in the predetermined portion of the inaccurate clock signal, the period of the accurate clock signal, and the desired time delay;second means for counting the desired number of cycles of the inaccurate clock signal; andmeans for indicating that the desired number of cycles of the inaccurate clock signal have occurred, whereby the desired time delay has elapsed.