Patent ID: 6773967
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method of forming an antifuse based interconnect structure having an amorphous Si antifuse with SiN sidewalls spacers, comprising the steps of:a) providing active elements in a semiconductor substrate; said active elements in said semiconductor substrate, are MOSFET devices, configured in a gate array pattern; b) forming a first interconnect structure, contacting said active element, in said semiconductor substrate; c) depositing an insulator layer, on said first interconnect structure; d) forming a via hole in said insulator layer, exposing top surface of said first interconnect structure; e) forming a metal plug in said via hole; f) forming an antifuse, contacting said metal plug; said antifuse comprised of amorphous silicon; g) forming antifuse spaces on the sidewalls of said antifuse; said antifuse spacers are composed of silicon nitride; h) forming a metal layer over said antifuse spacers and said antifuse; and i) patterning by etching said metal layer to form a second interconnect structure, contacting said antifuse layer whereby said antifuse spacers protect said anti-fuse from the etching of said metal layer.