Patent ID: 6380063
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising the steps of:providing a substrate, having at least one shallow trench isolation therein, and a gate stack thereon; forming a gate and a dielectric isolation on the surface of the substrate; forming a non-conductive sidewall spacer on each side of the gate and dielectric isolation; forming at least two diffusion regions within the substrate; removing a portion of the gate; depositing a silicide-forming layer over the surface of the semiconductor device; depositing a conductive layer over the silicide-forming layer; providing at least one interconnect within the conductive layer thereby electrically connecting the diffusion regions within the device; planarizing the surface of the device to expose the dielectric isolation and spacers; and annealing the substrate to form a silicide layer between the conductive layer and each gate and diffusion region.