Patent ID: 8072397
Filing Date: 2011-12-06
Classification: G09G

Abstract:
1. A display apparatus comprising: a pixel unit in which pixels are arranged in a matrix pattern; and a driving circuit for driving the pixel unit, wherein each of the pixels includes wherein the driving circuit outputs the writing signal, the driving pulse signal, and the control signal, sequentially sets the signal level of the signal line to a signal level corresponding to the gray-scale level of each pixel connected to the signal line with the period of a second fixed potential in between, sequentially repeats cyclical setting of first to fifth periods and drives the pixel unit, in the first period, sets the first and fourth transistors to an off state and sets the third transistor to an on state in response to the writing signal, the driving pulse signal, and the control signal, and drives the self-light-emitting element by using the second transistor on the basis of an electric current value in accordance with a gate-source voltage resulting from a potential across the ends of the signal level holding capacitor so as to cause the self-light-emitting element to emit light, in the second period, sets the third transistor to an off state so as to cause the self-light-emitting element to stop light emission in response to the driving pulse signal, in the third period, sets the fourth transistor to an on state in response to the control signal in order to set the other end of the signal level holding capacitor to the first fixed potential, sets the first transistor to an on state in response to the writing signal, and sets one end of the signal level holding capacitor to the second fixed potential, in the fourth period, during the period of time in which the second fixed potential is repeated a plurality of times in the signal line, sets the first transistor and the fourth transistor to an on state and an off state in response to the writing signal and the control signal, respectively, and during the period of time in which the signal level of the signal line is set to the second fixed potential, sets the third transistor to an on state in response to the driving pulse signal so as to set the potential difference across the ends of the signal level holding capacitor to a voltage approximately equal to a threshold voltage of the second transistor, and in the fifth period, in response to the writing signal, sets the first transistor from an on state to an off state, and sets the signal level of the signal line in one end of the signal level holding capacitor.