Patent ID: 8866527
Filing Date: 2014-10-21
Classification: H03K

Abstract:
1. Circuitry, comprising: first and second flip-flops operable as part of a scan chain in a scan mode and operable in a normal operational mode, wherein each of the first and second flip-flops comprises: control circuitry operable to generate first control signals for the master level-sensitive latch and the slave level-sensitive latch of the first and second flip-flops during the scan mode and operable to generate second control signals for the master level-sensitive latch and the slave level-sensitive latch of the first and second flip-flops during the normal operational mode, wherein the second control signals are different than the first control signals, wherein the first controls signals comprise a first clock signal and a second clock signal that is delayed version of the first clock signal, wherein the master level-sensitive latch of the first flip-flop is operable to receive the first clock signal at a first point in time, wherein the master level-sensitive latch of the second flip-flop is operable to receive the first clock signal at a second point in time that occurs a clock skew delay following the first point in time, wherein the slave level-sensitive latch of the first flip-flop is operable to receive the second clock signal that is delayed with respect to the first clock signal by a delay period that is greater than the clock skew delay.