Patent ID: 7876763
Filing Date: 2011-01-25
Classification: H04L,Y02D

Abstract:
1. An apparatus, comprising: one or more processing elements and memory; wherein said one or more processing elements are configured to implement a pipeline scheduler comprising a root scheduler and one or more layers of schedulers, each of said one or more layers including at least one scheduler, each scheduler of said one or more layers of schedulers configured to communicate selected scheduled items to its parent scheduler in the pipeline scheduler for each of a plurality of different scheduling categories; wherein said each scheduler of the pipeline scheduler is configured to simultaneously store, independently from said other schedulers in the pipeline scheduler, items of each of the plurality of different scheduling categories for, and received from, each of said particular scheduler's immediate children schedulers within the pipeline scheduler if any or from each immediate external source coupled to said particular scheduler if any, and to schedule the sending of said items of said different scheduling categories currently maintained to its parent scheduler or external scheduler client based on priorities corresponding to the different scheduling categories of said items currently stored; wherein the plurality of different scheduling categories includes a higher-priority scheduling category and a lower-priority scheduling category; and wherein said storing of items of each of the plurality of different scheduling categories corresponding to multiple scheduling lanes allows items of the higher-priority scheduling category not to be blocked by, or wait behind, items of the lower-priority scheduling category from a same children scheduler; and wherein once an item of said items of the plurality of different scheduling categories is said stored in a specific scheduler of said one or more layers of schedulers, it remains in the specific scheduler until it is selected and said communicated to its parent scheduler.