Patent ID: 6194886
Filing Date: 2001-02-27
Classification: G05F

Abstract:
An Early voltage and beta compensated cascode current mirror comprising:a cascode current mirror having an input stage responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current; anda compensation circuit, responsive to the cascode current mirror, having a first compensation stage, a second compensation stage and a bootstrapping buffer, the first compensation stage, in response to a change in the output voltage, impressing an equal change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base modulation effects in the output stage, the bootstrapping buffer, in response to the change in voltage, impressing an equal change in voltage on the first compensation stage to prevent errors from base current modulation in the first compensation stage, the first and second compensation stages further providing base currents to the cascode current mirror for cancelling base current errors in the output current induced by the cascode current mirror.