Patent ID: 6208186
Filing Date: 2001-03-27
Classification: H03K

Abstract:
A differential signal generator comprising:a memory element having a true node and a complementary node;a first switch responsive to a first control input, the first switch configured to conditionally couple the true node of the memory element to a first reference voltage;a second switch responsive to a second control input, the second switch configured to conditionally couple the complementary node of the memory element to the first reference voltage; andan input node coupled to the first control input and the second control input, such that when an input signal on the input node transitions from a first state to a second state, one of the first and second switches opens, and the other of the first and second switches closes;wherein the memory element comprises a latch having a pair of cross-coupled inverters, each of the pair of cross-coupled inverters including a PFET having a first drive strength, and an NFET having a second drive strength, wherein the first drive strength is not equal to the second drive strength.