Patent ID: 6403461
Filing Date: 2002-06-11
Classification: H01L

Abstract:
A method of forming a low dielectric constant (low k) layer, on a semiconductor substrate, comprising the steps of:providing a conductive structure on said semiconductor substrate; depositing a silicon nitride layer on said conductive structure; forming dual damascene type openings in a composite insulator layer and in said silicon nitride layer with said composite insulator layer overlying said silicon nitride layer, said damascene type openings exposing portions of said conductive structure with each of dual damascene type openings comprised of a wide trench opening and an underlying narrow via opening, said wide trench opening being in a second insulator layer of said composite insulator layer and said narrow via opening being in a first insulator layer of said composite insulator layer and said silicon nitride layer; forming dual damascene metal structures in said dual damascene type openings; removing said composite insulator layer, exposing said silicon nitride layer located between said dual damascene metal structures; depositing said low k layer thereby filling a narrow first space located between side top portions of said dual damascene metal structures and partially filling a second wide space located between side bottom portions of said dual damascene metal structures, leaving an air gap in partially filled wide second space; and removing said low k layer from top surface of said dual damascene metal structures resulting in said low k layer located between said dual damascene metal structures with said air gap located in a bottom portion of said low k layer and in said second wide space between said bottom side portions of said dual damascene metal structures.