Patent ID: 8138524
Filing Date: 2012-03-20
Classification: G11C,H01L

Abstract:
1. An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type; first and second regions formed in the substrate and having a second conductivity type, wherein the first and second regions are spaced apart from each other with a channel region formed in the substrate therebetween, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region; an electrically conductive floating gate having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from the channel region first portion for controlling a conductivity thereof, wherein the floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge; a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portion, and a second portion that extends up and over and is insulated from the floating gate first portion; and an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity thereof.