Patent ID: 8710595
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a substrate including a chip region; a plurality of dielectric films formed over the substrate; seal rings formed in a peripheral part of a chip region, the seal rings including a first seal ring and a second seal ring, the first seal ring surrounding the second seal ring, the first seal ring and the second seal ring both provided through at least one of the plurality of dielectric films in the peripheral part of the chip region; an interconnect formed in the plurality of dielectric films in the chip region; a first dielectric film included in the plurality of dielectric films and being in contact with an upper surface of the interconnect; a first opening provided in the first dielectric film and formed on the first seal ring; a second opening provided in the first dielectric film and formed on the second seal ring; a third opening provided in the first dielectric film and formed on the interconnect; a first cap layer disposed in the first opening and being in contact with the first seal ring; a second cap layer disposed in the second opening and being in contact with the second seal ring; and a pad electrode disposed in the third opening and being in contact with the interconnect, wherein the plurality of dielectric films includes a second dielectric film and a third dielectric film, both of the second and third dielectric films are formed between the substrate and the first dielectric film, at least one of the first and second seal rings includes one or more first seal vias in the second dielectric film and one or more second seal vias in the third dielectric film, the second dielectric film is formed between the substrate and the third dielectric film, and a length of one of the second seal vias is larger than a length of one of the first seal vias.