Patent ID: 6822316
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A semiconductor device, comprising:a semiconductor die; and an electronic circuit located on a top surface of said die; and a first interconnect structure also located on said top surface of said die, said first interconnect structure being coupled to said electronic circuit and being characterized by first nodes having a first feature size; a second interconnect structure located on a bottom surface of said die, said second interconnect structure being characterized by second nodes having a second feature size, said second feature size being at least twice that of said first feature size; said first interconnect structure and said second interconnect structure being coupled through conductive lines located in a plurality of vias extending from said top surface through said die to said bottom surface; wherein said second nodes are physically distributed in a contact area of said bottom surface which overlaps with portions of said electronic circuit on said top surface, so that said contact area is not exclusively in edge areas of said semiconductor die surrounding said electronic circuit.