Patent ID: 6137735
Filing Date: 2000-10-24
Classification: G11C

Abstract:
A semiconductor memory device comprising:a) a plurality of blocks each containing memory elements arranged in rows and columns, the memory elements being activated by applying column and row address signals to respective columns and rows, and the blocks being selectively activated by a block selection signal;b) A normal column driver for enabling at least one normal column in response to a decoded memory address signal received at an input thereof;c) a redundant column driver selectable for enabling at least one redundant column, in response to a redundant column address signal received at an input thereof;d) switch means responsive to said redundant column address signal for selectively enabling the redundant column driver and for disabling the normal column driver associated with the defective normal column; ande) a redundancy decoder for generating said redundant column address signal in response to a programmed defective memory address and said block selection signal, whereby the redundant column may replace a defective column in any one of said blocks.