Patent ID: 6153922
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor chip including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate,a plurality of leads each including an inner lead portion having a first region, and an inner lead portion having a second region and an outer lead portion formed integrally with said inner lead portions,bonding wires electrically connecting said external terminals and the first regions and the second regions of said inner lead portions, respectively, anda resin member for sealing said semiconductor chip, said inner lead portions and said bonding wires,wherein the first regions and the second regions of said inner lead portions are arranged over the major face of said semiconductor chip,wherein the first regions of said inner lead portions are arranged at predetermined spacings between said major face and said inner leads,wherein the portions of the inner leads arranged over said major face are thinner than the other portions of said inner leads, andwherein the inner leads arranged over said major face are fixed at their leading end portions to the major face of said semiconductor chip through an insulating film,wherein the first regions of said inner lead portions are signal leads whereas said second regions are fixed potential leads.