Patent ID: 6300244
Filing Date: 2001-10-09
Classification: C23C,H01L

Abstract:
A method of manufacturing a semiconductor device by filling at least one of a via-hole and a trench in an insulator layer having said at least one of the via-hole and the trench on a semiconductor substrate with a conductor through plating, the method comprising the steps of:forming a barrier layer made of any one of an inorganic compound and a high melting point metal on inner surfaces of said at least one of the via-hole and the trench; thentreating said semiconductor substrate with a treating solution containing a complex forming agent;immersing said semiconductor substrate into an electroless solution for electroless plating a metal, and at the same time bringing a member made of the same metal as the metal formed by said electroless plating in contact with said electroless solution; andelectrically connecting said member to said barrier layer, said member being connected to said barrier layer by connecting a wire between said member and said barrier layer for performing said filling through said electroless plating.