Patent ID: 7368767
Filing Date: 2008-05-06
Classification: G06F,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device comprising: a circuit section which is formed by arranging cell columns, each having standard cells arranged in a first direction, in a second direction crossing the first direction, the cell columns including, first standard cells each of which has a first and a second terminal to which a power supply voltage and the ground potential are applied, a third and a fourth terminal to which a well potential fixing potential is applied, and a transistor circuit to which the first and second terminals supply power and the third and fourth terminals apply a back gate bias, and second standard cells which fill up empty regions in the cell columns and apply the well potential fixing potential to the third and fourth terminals of the first standard cells, the second standard cells being spacer cells or filler cells, each of the spacer cells or filler cells having a first and a second power supply line provided at two sides facing each other and extending in the first direction, a first well region of a first-conductivity type formed in a semiconductor substrate under the first power supply line, a second well region of a second-conductivity type formed in the semiconductor substrate under the second power supply line, a first sub-region of the first-conductivity type formed in the first well region, and a second sub-region of the second-conductivity type formed in the second well region and includes no logic circuit.