Patent ID: 6587529
Filing Date: 2003-07-01
Classification: G11B

Abstract:
A method for estimating phase error when processing a digitized signal in a timing recovery circuit operable in a system associated with a memory and also incorporating a phase detector having an input and an output, comprising:a) employing timing gradient circuits, one of said timing gradient circuits being a native gradient circuit and another of said timing gradient circuits being a non-native gradient circuit, each of said timing gradient circuits implementing a different phase error transfer characteristic; b) normalizing, if necessary, each of said timing gradient circuits; and c) estimating a phase adjustment operation; wherein, if said native timing gradient circuit has a timing instance closer to zero phase error than said non-native timing gradient circuit, then an adjustment value, x, a number associated with said native timing gradient circuit, is inputted to the timing recovery circuit, andwherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180Â° is added to said value x.