Patent ID: 7738312
Filing Date: 2010-06-15
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each formed on an insulating film, each of the memory cells including (i) a first transistor for storing information by a voltage at a body region and having a first conduction node receiving a fixed voltage, and second and third conduction nodes isolated from said first conduction node by said body region, (ii) a second transistor having a fourth conduction node connected to said second conduction node of said first transistor, and (iii) a third transistor having a fifth conduction node connected to the third conduction node of said first transistor; a plurality of first word lines, arranged corresponding to the memory cell rows, each connected to control electrodes of the second transistors of the memory cells in a corresponding row; a plurality of second word lines, arranged corresponding to the memory cell rows, each connected to control electrodes of the third transistors of the memory cells in a corresponding row; a plurality of charge lines, arranged corresponding to said memory cell rows, each connected to control electrodes of the first transistors of the memory cells in a corresponding row; a plurality of first bit lines, arranged corresponding to said memory cell columns, respectively, each connected to sixth conduction nodes of the second transistors of the memory cells in a corresponding column; and a plurality of second bit lines, arranged corresponding to said memory cell columns, respectively, each connected to seventh conduction nodes of the third transistors of the memory cells in a corresponding column.