Patent ID: 6815346
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A method of forming a reinforcement structure for a semiconductor device having multilayer wiring levels with at least some of said wiring levels employing a low-k dielectric insulating material there between, said method comprising the steps of:depositing a layer of insulating material on a semiconductor substrate; forming a first plurality of conductive pads interconnected by conductive lines in said layer of insulating material at the first wiring level while at the same time forming first level active device metallurgy; forming a layer of low-k dielectric insulating material on said first wiring level; forming in said low-k dielectric material a plurality of groups of conductive vias with respective ones of said groups in contact with respective ones of said plurality of conductive pads so that one group is in contact with each pad of said plurality of conductive pads, said plurality of groups of conductive vias formed while at the same time forming active device conductive vias; forming a second corresponding plurality of conductive pads interconnected by conductive lines at the second wiring level while at the same time forming second level active device metallurgy; repeating the foregoing steps to form successive pluralities of groups of conductive vias in successive layers of low-k dielectric insulating material between respective ones of successive pluralities of conductive pads in said successive layers of low-k dielectric insulating material at successive wiring levels to the uppermost wiring level thereby forming a mesh-like structure to provide vertical and horizontal reinforcement during formation of active device metallurgy.