Patent ID: 6887739
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor package, comprising: (a) providing a plurality of semiconductor chips and a wiring substrate, each of said plurality of semiconductor chips having an integrated circuit and bonding pads formed on a main surface thereof, said wiring substrate having a periphery and a first surface, a second surface opposed to said first surface and a plurality of conductive layers, said wiring substrate having a plurality of chip mounting areas at said first surface in a plane view, said plurality of chip mounting areas being arranged in a matrix formation of a rectangular shape having opposed longer sides and opposed shorter sides; (b) mounting said plurality of semiconductor chips on said plurality of chip mounting areas of said first surface of said wiring substrate respectively; (c) electrically connecting said bonding pads of said semiconductor chips with corresponding conductive layers of said plurality of conductive layers, by a plurality of bonding wires; (d) sealing said plurality of semiconductor chips, said plurality of bonding wires and said first surface of said wiring substrate including said plurality of chip mounting areas by a resin member, said sealing being performed by a transfer molding such that said resin member is provided from one of the longer sides of the rectangular shape toward the other of the longer sides of the rectangular shape of the matrix formation, via plural flow gates positioned at the periphery of the wiring substrate; (e) forming a plurality of bump electrodes on said second surface of said wiring substrate so as to electrically connect with said plurality of conductive layers of said wiring substrate; and (f) after (e), dividing said wiring substrate into plural parts each including a corresponding chip mounting area of said plurality of chip mounting areas, thereby to form a plurality of semiconductor packages each including one of said plural parts of said wiring substrate, one of said plurality of semiconductor chips, ones of said plurality of bonding wires and a part of said resin member.