Patent ID: 9009639
Filing Date: 2015-04-14
Classification: G06F

Abstract:
1. A method of designing an integrated circuit (IC), the method comprising: placing a first cell and a second cell into a design layout of the IC, wherein the second cell is a mirror of the first cell, and wherein each of the first cell and the second cell contains a device selected from the group consisting of a resistor, a capacitor, and an inductor; dividing the device of the first cell into a first plurality of segments; dividing the device of the second cell into a second plurality of segments; forming a third device of a third cell by connecting a first portion of the first plurality of segments with a first portion of the second plurality of segments; and forming a fourth device of a fourth cell by connecting a second portion of the first plurality of segments with a second portion of the second plurality of segments, and wherein at least one of: the dividing of the device of the first cell, the dividing of the device of the second cell, the forming of the third device, or the forming of the fourth device is performed by a computing system.