Patent ID: 6100727
Filing Date: 2000-08-08
Classification: H03K

Abstract:
A dynamic driving circuit supplied with a clock signal having logic high and logic low levels which determine a precharge period and an evaluation period, respectively, and supplied with a data signal, said dynamic driving circuit comprising:a control unit supplied with said clock signal and said data signal and which produces a control signal in response thereto; anda signal line driver which produces, in response to said control signal received from said control unit, an output signal which drives a signal line, said signal line driver having a high level driver which causes said output signal to have said logic high level and a low level driver which causes said output signal to have said logic low level, said signal line driver actuating only one of said high level driver and said low level driver during said evaluation period;wherein said control unit produces said control signal so that said output signal of said signal line driver has said logic high level in said precharge period regardless of the value of said data signal and that said output signal of said signal line driver has said logic high level in said evaluation period when said data signal has said logic high level in said evaluation period.