Patent ID: 8146087
Filing Date: 2012-03-27
Classification: G06F

Abstract:
1. A computer-implemented method comprising: loading a first job initiated by a first partition onto a first hardware thread, the first partition including a first subset of processor resources; loading a second job initiated by a second partition onto a second hardware thread, the second partition including a second subset of processor resources; translating a first concatenated virtual address into a first system-wide real address, wherein the first concatenated virtual address includes a first virtual page identifier and a first partition identifier, the first partition identifier identifying the first partition; translating a second concatenated virtual address into a second system-wide real address, wherein the second concatenated virtual address includes a second virtual page identifier and a second partition identifier, the second partition identifier identifying the second partition; and simultaneously executing the first job on the first hardware thread using the first system-wide real address and the second job on the second hardware thread using the second system-wide real address, wherein the first hardware thread and the second hardware thread are co-located on a processor.