Patent ID: 7557023
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A semiconductor structure fabrication method, comprising: providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer, wherein the gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region, and wherein the semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer; forming a resist layer on the gate dielectric layer and the gate electrode region; and removing a cap portion of the resist layer directly above the gate electrode region in the reference direction without removing any portion of the resist layer not directly above the gate electrode region in the reference direction, wherein, before said removing the cap portion is performed, the resist layer including the cap portion comprises a first material, wherein said removing the cap portion comprises: wherein said changing the first material of the cap portion to the second material comprises sending protons through the cap portion resulting in the first material of the cap portion becoming the second material, wherein the semiconductor structure further includes a proton-generating region on the gate electrode region such that after said forming the resist layer is performed, the proton-generating region is sandwiched between the gate electrode region and the resist layer, wherein said sending the protons through the cap portion comprises: