Patent ID: 7868352
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A two-terminal semiconductor switching device comprising: a P+ layer of semiconductor material having essentially parallel first and second major surfaces; a plurality of N+ regions distributed in the P+ layer and passing through the P+ layer between the first and second major surfaces thereof; a metallization layer disposed on the first surface of the P+ layer and on a surface portion of each of the N+ regions; a N− layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the N− layer being disposed proximate the second major surface of the P+ layer; a P layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the P layer being disposed contiguous to the second major surface of the N− layer to form a blocking junction; a N+ layer of semiconductor material having essentially parallel first and second major surfaces, the first major surface of the N+ layer being disposed proximate the second major surface of the P layer; a plurality of P+ regions distributed in the N+ layer and passing through the N+ layer between the first and second major surfaces thereof; a metallization layer disposed on the second surface of the N+ layer and on a surface portion of each of the P+ regions; and a N layer of semiconductor material disposed between the P+ layer and the N− layer for providing a field stop.