Patent ID: 9178060
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate having interior bottom surfaces delimiting bottoms of a pair of recesses spaced apart from each other in the substrate, and interior sidewall surfaces delimiting sides of the recesses; a pair of impurity regions each occupying a respective one of the recesses such that the impurities regions are also spaced apart from each other in the substrate; and a gate electrode disposed on the substrate at a location between the impurity regions in a first direction, wherein each of the impurity regions includes a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer, the first epitaxial layer is disposed on the interior bottom and sidewall surfaces of the substrate which delimit a respective one of the recesses, occupies only part of the respective recess, and is a stack of a plurality of first sub-epitaxial layers and at least one second sub-epitaxial layer, each said second sub-epitaxial layer being disposed on a respective said first sub-epitaxial layer such that the first and second sub-epitaxial layers are alternately disposed in the stack, each of the first and second sub-epitaxial layers is a layer extending along the interior bottom surface and interior sidewall surfaces which delimit the respective recess such that each of the first and second sub-epitaxial layers has a bottom portion on the interior bottom surface and side portions on the interior sidewall surfaces delimiting the respective recess, and a concentration of an impurity in material constituting each of the first sub-epitaxial layers is less than a concentration of an impurity in material constituting each said at least one second sub-epitaxial layer.