Patent ID: 6396707
Filing Date: 2002-05-28
Classification: H01L,H05K

Abstract:
A ball grid array package comprising:a substrate having a first surface, and a second surface; a chip disposed on the second surface; an insulating material that is disposed on the second surface for encapsulating the chip; a plurality of ball pads disposed on the first surface, each of the ball pads has a side wall, and a plurality of conducting traces are placed between each two adjacent ball pads, wherein each of the ball pads is stripe-shaped with a length and a width that is smaller than the length so that the number of conductive traces between each two adjacent striped ball pads is increased; and a solder mask disposed on the first surface and having an opening, wherein the solder mask covers a portion of the ball pad and the opening exposes a portion of the side wall of the ball pads.