Patent ID: 7321651
Filing Date: 2008-01-22
Classification: G06F

Abstract:
1. A high frequency circuit for generating an error detection state and correction of code patterns running at full speed, comprising: a shadow register means having a plurality of pattern inputs and a plurality of shadow register outputs; a serial/parallel shift register having a plurality of inputs, wherein each input of the plurality of inputs is at least connected to at least one shadow register outputs, and wherein the serial/parallel shift register is at least configured to be selectively programmable to alternate between a serial mode and a parallel mode; a plurality of comparators each having a pair of inputs, wherein each input of each comparator is at least configured to be coupled to an output of the serial/parallel shift register; at least one logic gate that is at least configured to receive an output from each comparator of the plurality of comparators; and output circuitry that is at least configured to receive an output of the logic gate to generate a signal that is functionally related to the error detection state.