Patent ID: 6208685
Filing Date: 2001-03-27
Classification: H03H

Abstract:
A matched filter comprising:a shift register having a plurality of cascaded delay elements, a first stage of said delay elements receiving a spread spectrum signal, said delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof;a coincidence degree calculating circuit for calculating degrees of coincidence between said parallel signal and a pseudorandom noise;a plurality of capacitors each having one end supplied with a first reference potential;a plurality of first switching elements each connected between said output of corresponding one of said delay elements and other end of corresponding one of said capacitors;a common conductor;a plurality of second switching elements connected between said other end of corresponding one of said capacitors and said common conductor; anda resetting switching element with its one end connected to said common conductor and its other end supplied with a second reference potential;wherein said capacitors comprises:a plurality of first capacitor elements each with its one end supplied with said first reference potential, other end thereof being said other end of corresponding one of said capacitors;a plurality of second capacitor elements each with its one end supplied with a third reference potential; anda plurality of third switching elements each connected between said other end of corresponding one of said first capacitor elements and its other end of corresponding one of said second capacitor elements,wherein when one of a first group consisting of said first switching elements and said resetting switching element, and a second group consisting of said second switching elements is on, the other thereof is off, substantially, andwherein said third switching elements are controlled by weight data.