Patent ID: 8709899
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A method of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising: depositing a masking layer on an n-well region implanted on a substrate; patterning the masking layer to define an area; forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region; filling the first trench with a conductive material; depositing a layer of oxide over the area; etching out at least a portion of the layer of oxide to expose a portion of the conductive material; removing the conductive material from the exposed portion to form a second trench; and filling the second trench with an oxide to form an asymmetric gate of the vertical LDMOS transistor.