Patent ID: 6075738
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array having a plurality of memory cells each including a control gate electrode, a source, a drain and a floating gate electrode, wherein a data value of a memory cell is determined in accordance with an amount of charge stored in the floating gate electrode;a control circuit for controlling voltages applied to the control gate electrode, the source and the drain of at least one memory cell such that a charge which is greater than a charge amount corresponding to a desired data value is stored in the floating gate electrode first, and then drained therefrom in a data write mode; anda write data determining circuit for checking an amount of charge remaining in the floating gate electrode after stored charge in the floating gate electrode is drained, and disabling a write operation on at least one memory cell when the amount of charge remaining in the floating gate electrode reaches the charge amount corresponding to the desired data value.