Patent ID: 9104533
Filing Date: 2015-08-11
Classification: G06F

Abstract:
1. A voltage and timing calibration method used in a memory system, wherein the memory system comprises a memory controller, at least one memory buffer connected to the memory controller in a communication manner, and at least one memory chip unit connected to the memory buffer in a communication manner, the method at least comprising: 1) the memory controller adjusting timing and voltages of the memory controller and voltages of the memory buffer according to first data returned by the memory buffer, the first data corresponding to a timing and a voltage at a memory controller side of the memory buffer, to implement calibration of the timing and the voltage between the memory controller and the memory controller side of the memory buffer; and 2) according to second data read from the memory chip unit by the memory buffer undergone the calibration of the timing and the voltage at the memory controller side based on timing and voltages at a memory chip side of the memory buffer, the memory controller adjusting (i) the timing and the voltage at the memory chip side of the memory buffer, and (ii) the voltage of the memory chip unit, to implement calibration of the timing and the voltages between the memory chip side of the memory buffer and the memory chip unit connected thereto in a communication manner.