Patent ID: 8242601
Filing Date: 2012-08-14
Classification: H01L

Abstract:
1. A semiconductor chip comprising: a silicon substrate; a MOS device in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said silicon substrate and said first metal layer, wherein said second metal layer comprises electroplated copper, wherein said second metal layer comprises a first contact pad, a second contact pad and a third contact pad that are aligned in a first line; a dielectric layer between said first and second metal layers; a passivation layer on said second metal layer and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over said first contact pad, wherein a second opening in said passivation layer is over said second contact pad, and wherein a third opening in said passivation layer is over said third contact pad; a patterned metal layer on said first, second and third contact pads and over said passivation layer, wherein said patterned metal layer comprises a fourth contact pad on said first contact pad, wherein said fourth contact pad is connected to said first contact pad through said first opening, a fifth contact pad connected to said second contact pad through said second opening, wherein said fifth contact pad is not vertically over said second contact pad, and a sixth contact pad on said third contact pad, wherein said sixth contact pad is connected to said third contact pad through said third opening; a first metal bump on said fourth contact pad and vertically over said first contact pad; a second metal bump on said fifth contact pad and not vertically over said second contact pad; and a third metal bump on said sixth contact pad and vertically over said third contact pad, wherein said third metal bump comprises a single metal layer, having a height between 8 and 50 micrometers, contacting said sixth contact pad, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line.