Patent ID: 7033904
Filing Date: 2006-04-25
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the step of forming, on a layered structure of a first insulation film including a first conductor pattern and a second insulation film formed on said first insulation film and including a second conductor pattern, a third conductor pattern, said method comprising the steps of: measuring a first alignment error between said first conductor pattern and said second conductor pattern; measuring a second alignment error between said second conductor pattern and said third conductor pattern, patterning said third conductor pattern on said insulation film by an etching process, measuring a third alignment error between said third conductor pattern and said first conductor pattern by monitoring said third conductor pattern and an alignment mark included in said first insulation film; and obtaining a corrected alignment error in which said second alignment error is corrected based on said first and third alignment errors.