Patent ID: 7051062
Filing Date: 2006-05-23
Classification: G06F

Abstract:
1. Apparatus for determining a value and an overflow status of an addition of at least three n-bit data inputs, wherein n is an integer, the apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of said first output, said second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n; at least two electronic-circuits, operatively associated with said first adder and said second adder; said first adder, said second adder and said at least two electronic-circuits are constructed and designed to obtain the value and the overflow status of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.