Patent ID: 9147750
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A process for fabricating at least one transistor comprising an active semiconductor region on or in a substrate, said active semiconductor region comprising a source region, a drain region, and a channel region covered with a gate, the process comprising: producing a primary etching mask on a surface of said active semiconductor region, said primary etching mask containing at least one primary aperture of dimensions L depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains, said first and second polymer domains having dimensions L removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures distributed in the second direction Y; etching said active semiconductor region through said secondary apertures in order to define nanoscale self-aligned semiconductor features of dimensions L producing said gate on a surface of said nanoscale self-aligned semiconductor features, wherein the transistor is configured to flow a current between the source region and the drain region in the first direction X.