Patent ID: 6524913
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of fabricating a non-volatile memory, comprising the steps of:providing a substrate; forming a charge-trapping layer on the substrate; forming a plurality of bar-like conductive layers on the charge-trapping layer; forming a plurality of buried bit-lines in the substrate between the bar-like conductive layers; forming a plurality of high-K spacers on the side-walls of the bar-like conductive layers; forming a plurality of gates on the bar-like conductive layers; and forming a plurality of word-lines over the substrate to electrically connect with the gates, wherein each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer; and a material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.