Patent ID: 7605087
Filing Date: 2009-10-20
Classification: H01L

Abstract:
1. A method of forming a semiconductor device, comprising: forming an interlayer dielectric on a substrate; forming a mold layer on the interlayer dielectric; forming a guide opening that penetrates the mold layer; forming a di-block polymer layer in the guide opening, the di-block polymer layer comprising a plurality of first polymer blocks and a plurality of second polymer blocks; dividing the di-block polymer layer into a first phase to which the first polymer blocks are bound and a second phase to which the second polymer blocks are bound; removing the second phase so that at least part of the first phase remains in place, wherein the remaining first phase defines at least part of a pore in the guide opening; etching the interlayer dielectric exposed beneath the pore to form an opening; removing the remaining the first phase; forming a conductive layer on the mold layer and in the opening; and planarizing the conductive layer and the mold layer to expose the interlaver dielectric and to form an electrode in the opening.