Patent ID: 6560732
Filing Date: 2003-05-06
Classification: G11C

Abstract:
An operating method for an integrated memory having a writeable security memory cell for storing a security information item, word lines, bit lines crossing over the word lines, and writeable memory cells for storing data and disposed at crossover points between the word lines and the bit lines, which comprises performing the following steps in an event of a write/read access:reading out the security information item stored in the writeable security memory cell before performing the write/read access to a respective memory cell of the writeable memory cells; generating an error signal if the security information item read out has a first logic state; carrying out an access to the respective memory cell if the security information item read out has a second logic state; and performing a write access to the writeable security memory cell, in which a new security information item to be stored, which has the second logic state, is fed to the writeable security memory cell.