Patent ID: 7846790
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming an isolation layer defining first and second active regions in a semiconductor substrate, and forming a first recessed region between the isolation layer and an upper edge portion of the first active region and a second recessed region between the isolation layer and an upper edge portion of the second active region; forming a passivation layer on the semiconductor substrate having the isolation layer, the passivation layer filling the first second recessed regions; carrying out a first patterning process of etching the passivation layer on the first active region to form a first opening exposing the first active region, and forming a first passivation pattern in the first recessed region by the first patterning process, wherein the first passivation pattern is formed between a sidewall of the isolation layer and a sidewall of an upper edge portion of the first active region; forming a first dielectric layer in the exposed first active region; carrying out a second patterning process of etching the passivation layer on the second active region to form a second opening exposing the second active region, and forming a second passivation pattern in the second recessed region by the second patterning process, wherein the second passivation pattern is formed between a sidewall of the isolation layer and a sidewall of an upper edge portion of the second active region; and forming a second dielectric layer in the exposed second active region.