Patent ID: 6115255
Filing Date: 2000-09-05
Classification: H01L

Abstract:
A power hybrid integrated circuit, comprising a double-side metallized dielectric board (1) with a topological metallization pattern (2) on the face side thereof and with at least one mounting pad (3) located in a recess (4) of the face side of the board (1) on a heat sink (5) which is essentially a system of blind holes (6) in the bottom of the recess (4), filled with a heat conducting material (10), the board (1) is joined with its back side to a heat conducting base (7), a naked electronic chip (9) is placed on and fixed to the mounting pad (3) in the recess (4) so that the face surface of the chip (9) is coplanar with the topological metallization pattern (2), CHARACTERIZED in that the holes (6) of the heat sink (5) in the bottom of the recess (4) are blind, the remained thickness of the bottom of said blind holes (6) is from 1 to 999 .mu.m, and spaces between the chip (9) and the side walls of the recess (4) are filled at least partially with the heat conducting material (10).