Patent ID: 8436471
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A semiconductor package, comprising: a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to only cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip leaving another part of the surface of the semiconductor chip exposed to an outside of the semiconductor package, wherein the resin part contacts and covers the circuit forming surface of the semiconductor chip, wherein the wiring structure being electrically connected to the semiconductor chip is formed on the surface of the resin part opposite to a contact surface contacting the circuit forming surface, wherein the semiconductor chip includes an electrode and a bump formed on the electrode, wherein the bump is exposed from the surface of the resin part, wherein the wiring structure is formed by laminating an insulation layer and a wiring layer, wherein the insulation layer is formed by covering the surface of the resin part, wherein the insulation layer has a via hole, from which the bump of the semiconductor chip is exposed for electrical connection, wherein the wiring layer is arranged on the insulation layer, and a via conductor of the wiring layer is provided inside the via hole for connecting the wiring layer to the bump.