Patent ID: 8130189
Filing Date: 2012-03-06
Classification: G09G,G11C

Abstract:
1. A gate driving device for Thin Film Transistor liquid crystal display, characterized in comprising: a plurality of sequentially connected shift registers, directly deposited on an array substrate; each of said shift registers including: first, second, third, and fourth field effect transistors, a capacitor, and an ON voltage timing signal input terminal, a clock signal input terminal and a low voltage input terminal; the ON voltage timing signal input terminal being connected with a drain of the first field effect transistor, a gate of the first field effect transistor being connected with a drain of the first field effect transistor, the clock signal input terminal being connected with a drain of the third field effect transistor, the capacitor being connected between a source and a gate of the third field effect transistor, a drain and a source of the fourth field effect transistor being connected with the source of the third field effect transistor and the low voltage input terminal, respectively, a source and a drain of the second field effect transistor being connected with the source of the first field effect transistor and the low voltage input terminal, respectively; a output terminal of each of said shift registers except for a first shift register and a last shift register being connected with a gate of the fourth field effect transistor of a previous shift register and the ON voltage timing signal input terminal of a next shift register; a output terminal of the last shift register being connected with a gate of the fourth field effect transistor of a previous shift register and a gate of the second field effect transistor of said last shift register, a output terminal of the first shift register being connected with the ON voltage timing signal input terminal of a next shift register; the clock signal input terminal of the shift registers with odd sequence numbers inputting a clock signal, the clock signal input terminal of the shift registers with even sequence numbers inputting a clock inverted signal.