Patent ID: 6097206
Filing Date: 2000-08-01
Classification: G01R,G11C

Abstract:
A memory testing apparatus comprising:a pattern generator for outputting at least an address pattern data and a test pattern data;a waveform generator for converting the address pattern data and the test pattern data outputted from said pattern generator into an address pattern signal and a test pattern signal each having a real waveform;means for applying the address pattern signal and the test pattern signal outputted from said waveform generator to a memory under test;a ROM expected value memory for outputting a ROM expected value pattern data in a ROM testing mode;a first logical comparator for logically comparing a data read out of the memory under test with an expected value pattern data outputted from said pattern generator in a RAM testing mode;a second logical comparator for logically comparing a result of the logical comparison in said first logical comparator with a data outputted from said ROM expected value memory; anda failure analysis memory having the same address area as that of the memory under test for storing a failure data outputted from said second logical comparator at the same address as that of a memory cell in the memory under test where a failure has occurred,said memory testing apparatus being characterized in that in the RAM testing mode, fixed data all bits of which have the same logic are outputted from said ROM expected value memory to be supplied to said second logical comparator, and in the ROM testing mode, fixed data all bits of which have the same logic are outputted from said pattern generator to be supplied to said first logical comparator.