Patent ID: 8472515
Filing Date: 2013-06-25
Classification: H03K,H03L,H04L

Abstract:
1. A phase detection and decision feedback equalization (PDDFE) circuit, comprising: a first latch and a second latch coupled to an input of the PDDFE circuit, the first latch being enabled by a clock signal, and the second latch being enabled by a complement of the clock signal; a third latch coupled in series to an output of the first latch in a master-slave configuration, wherein the third latch is enabled by a complement of the clock signal and is configured to produce a first demultiplexed signal; a fourth latch coupled in series to an output of the second latch in a master-slave configuration, wherein the fourth latch is enabled by the clock signal and is configured to produce a second demultiplexed signal; a fifth latch coupled to an output of the third latch in a master-slave configuration, wherein the fifth latch is enabled by the clock signal; a sixth latch coupled to an output of the fourth latch in a master-slave configuration, wherein the sixth latch is enabled by the complement of the clock signal; a first feedback circuit configured to provide a signal output from the first latch and a first feedback signal derived from the second demultiplexed signal to an input of the third latch, and further configured to provide a third feedback signal derived from a signal output from the fifth latch to the input of the third latch; and a second feedback circuit configured to provide a signal output from the second latch and a second feedback signal derived from the first demultiplexed signal to an input of the fourth latch, and further configured to provide a fourth feedback signal derived from a signal output from the sixth latch to the input of the fourth latch.