Patent ID: 6097057
Filing Date: 2000-08-01
Classification: H01L

Abstract:
A memory cell for EEPROM devices, formed in a portion of a semiconductor material substrate having a first conductivity type, said memory cell comprising:a gate oxide region defined over a portion of the semiconductor material and including a thin tunnel oxide region;source and drain regions having a second conductivity type extending to the sides of the gate oxide region;a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region;a channel region defined between the region of electric continuity and the source region; andan implanted region of the first conductivity type being formed laterally and beneath the gate oxide region and incorporating the channel region, said implanted region increases dopant levels in the portion of the semiconductor material substrate, the implanted region completely overlaps the region of electric continuity and has decreased thickness relative thereto.