Patent ID: 6472901
Filing Date: 2002-10-29
Classification: G01R,Y10T

Abstract:
A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising:providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon; providing a substrate with conductive pads deposited on a surface thereof for flip-chip attachment to said interconnection bumps of said one or more IC dice; providing a plurality of probes for contacting said substrate; positioning said one or more IC dice on said surface of said substrate with said interconnection bumps of said one or more IC dice in conductive contact with said conductive pads of said substrate to form said flip-chip semiconductor assembly; contacting said substrate with said plurality of probes; while said substrate is in contact with said plurality of probes and said one or more IC dice are positioned on said surface of said substrate, and before sealing of said one or more IC dice, electrically testing said flip-chip semiconductor assembly using said plurality of probes; repairing said flip-chip semiconductor assembly if it fails said electrical testing, said repairing comprising at least one of: repairing one or more defective circuit traces on said substrate; and repairing one or more defective conductive pads on said substrate; speed grading said flip-chip semiconductor assembly; and sealing said one or more IC dice of said flip-chip semiconductor assembly.