Patent ID: 6977901
Filing Date: 2005-12-20
Classification: H04L

Abstract:
1. A packet transmission/reception processor coupled to a CPU, the processor comprising: a link core circuit for receiving a packet externally delivered through a bus; a packet processing controller for processing the packet received by the link core circuit, generating a packet to be transmitted in response to the received packet, and supplying the packet to be transmitted to the link core circuit; and a packet processing control timer for clocking how much time has passed since the packet was received by the link core circuit and for generating a signal when the time passed reaches a predetermined amount of time, wherein the link core circuit sends out the packet to be transmitted, supplied from the packet processing controller, by way of the bus, and responsive to the signal supplied from the packet processing control timer, the packet processing controller stops processing the received packet, generates another packet to be transmitted in response to the received packet and restarts processing the received packet.