Patent ID: 8183879
Filing Date: 2012-05-22
Classification: G01R,H01L

Abstract:
1. A measuring arrangement comprising: at least one semiconductor component having a semiconductor substrate, at least one doped region in the semiconductor substrate adjoining a top side of the semiconductor substrate in planar fashion, an insulation layer on the top side of the semiconductor substrate adjoining the doped region, a gate connection layer on the insulation layer and a dangling bond defect in the interface between the insulation layer and the semiconductor substrate caused by a lattice constant mismatch between the semiconductor substrate and the insulation layer; a voltage source connected to the gate connection layer by a first connection and to a reference potential by a second connection and operable to apply a first voltage to the gate connection layer which causes a free mobile charge carrier to be bound in the defect and apply a second voltage to the gate connection layer which causes the defect to liberate the free mobile charge carrier; and a measuring unit having at least a first and a second input and an output, the first input being connected to the semiconductor substrate, the second input being connected to the doped region and the output operable to provide a measured value that is proportional to the number of dangling bond defects in the interface between the insulation layer and the semiconductor substrate.