Patent ID: 7033944
Filing Date: 2006-04-25
Classification: H01L

Abstract:
1. A dual damascene process comprising: forming a bottom layer on a semiconductor substrate; forming an interlayer dielectric layer on the bottom layer; patterning the interlayer dielectric layer to form a trench; filling the trench with a conductive material to form the bottom interconnection; sequentially forming a first etch stopping layer, a bottom intermetal dielectric layer, a second etch stopping layer and an upper intermetal dielectric layer on an entire surface of the semiconductor substrate having the bottom interconnection; successively patterning the upper intermetal dielectric layer, the second etch stopping layer, and the bottom intermetal dielectric layer by using a first etch recipe to form a first recessed region exposing a predetermined region of the first etch stopping layer; forming a bottom-protecting layer having a planarized surface on the upper intermetal dielectric layer and in the first recessed region; successively patterning the bottom protecting layer and the upper intermetal dielectric layer by using a second etch recipe to form a second recessed region being overlapped with the first recessed region and having a wider width than the first recessed region; selectively removing the bottom protecting layer to expose the predetermined region of the first etch stopping layer; and removing the first etch stopping layer exposed by at least the first recessed region to expose the bottom interconnection, wherein the second etch recipe uses an etch gas that makes an etch selectivity of the upper intermetal dielectric layer with respect to the bottom protecting layer to be about 0.5 to about 1.5.