Patent ID: 8018773
Filing Date: 2011-09-13
Classification: G11C,H01L

Abstract:
1. A non-volatile memory device comprising: an array of non-volatile memory cells arranged in a plurality of rows and columns, with each memory cell having a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source; said array having a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side; a plurality of columns of reference memory cells embedded in said memory array, with a plurality of reference cells in each row of said array of non-volatile memory cells, substantially evenly spaced apart from one another; each of said reference memory cells, substantially the same as the non-volatile memory cells, and having a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source and a low voltage terminal for connection to a low voltage source; a high voltage decoder positioned on said first side, and having a plurality of high voltage lines, with each high voltage line connected to the high voltage terminal of the memory cells and reference cells in the same row; a low voltage row decoder positioned on said second side, and having a plurality of low voltage lines, with each low voltage line connected to the low voltage terminal of the memory cells and reference cells in the same row; a plurality of sense amplifiers positioned on said third side, with each sense amplifier connected to the bit terminal of one column of non-volatile memory cells and to the bit terminal of a column of reference memory cells; wherein each of said non-volatile memory cells comprises a first region of a first conductivity type in a substrate of a second conductivity type, a second region of the first conductivity type spaced apart from the first region forming a channel region therebetween, a floating gate positioned over a portion of the channel region and insulated therefrom and adjacent to the first region, a control gate positioned over another portion of the channel region, and insulated therefrom, and adjacent to the floating gate and insulated therefrom, a top gate positioned over the floating gate, insulated therefrom, and an erase gate positioned over the first region, insulated therefrom, and adjacent to the floating gate; and wherein the bit terminal is said second region, the control gate and the top gate are said low voltage terminals, and the erase gate and top gate and the first region are the high voltage terminals.