Patent ID: 7484196
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A method, in a data processing system, for simulating asynchronous clock nets in an integrated circuit model, comprising: receiving the integrated circuit model; transforming at least one clock net in the integrated circuit model to include clock skewing logic, wherein the clock skewing logic introduces delay into the at least one clock net to thereby skew a phase of the at least one clock net with respect to another clock net in the integrated circuit model; simulating the integrated circuit model having the transformed at least one clock net, wherein the clock skewing logic comprises a delay counter and a plurality of latches, coupled to the delay counter, and provided in series, each latch introducing an additional delay amount to an input clock signal, wherein an output of a particular latch in the plurality of latches is selected as a clock output signal based on an incrementing of the delay counter with each enablement of the clock skewing logic, and wherein the clock skewing logic simulates an asynchronous operation of the at least one clock net with respect to the another clock net during the simulation of the integrated circuit model; and generating an output indicative of an operation of the integrated circuit model during the simulation.