Patent ID: 6072234
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A three-dimensional stack of two or more neo-chip layers of equal total layer area, the stack comprising:a first neo-chip layer having a first total layer area, the first neo-chip layer comprising a first die that is tested, the first die being embedded in a first dielectric material having a first encapsulating area, the first die having a first die area and containing a first circuitry for performing a first function, the first die area and the first encapsulating area combining to form the first total layer area; anda second neo-chip layer having a second total layer area equal to the first total layer area, the second neo-chip layer comprising a second die that is tested, the second die being embedded in a second dielectric material having a second encapsulating area different from the first encapsulating area, the second die having a second die area different from the first die area and containing a second circuitry for performing a second function different from the first function, the second die area and the second encapsulating area combining to form the second total layer area.