Patent ID: 7752529
Filing Date: 2010-07-06
Classification: H03M

Abstract:
1. An apparatus, comprising: a circuitry for performing both: the circuitry includes a plurality of XOR (exclusive OR) logic gates, implemented in an array arrangement such that each XOR gate of the plurality of XOR gates corresponds to a non-zero element of the LDPC matrix, and a plurality of MUXs (multiplexors) that is operable to modify the connectivity of a subset of the plurality of XOR gates that corresponds to at least one column of the LDPC matrix that is employed to generate the parity bit; a select signal is operable to select a first connectivity of each MUX when the circuitry using the LDPC matrix performs encoding of the first information bit to form the first LDPC coded signal; and the select signal is operable to select a second connectivity of each MUX when the circuitry using the LDPC matrix performs decoding processing on the second LDPC coded signal.