Patent ID: 6528978
Filing Date: 2003-03-04
Classification: G05F,Y10S

Abstract:
A reference voltage generating circuit comprising:a first current generating means connected between a power supply voltage and a ground voltage for generating a bias current that increases in response to increases in temperature; a second current generating means connected between the power supply voltage and a reference voltage generating terminal for generating a mirrored current of the bias current; and a load connected between the reference voltage generating terminal and the ground voltage for generating a reference voltage that increases in response to increases in temperature regardless of increases in the power supply voltage, wherein the load includes: a first resistor, first and second NMOS transistors connected serially between the reference voltage generating terminal and the ground voltage, for receiving the reference voltage at a gate of the first NMOS transistor and for receiving the power supply voltage at a gate of the second NMOS transistor; and a first PMOS transistor and a third NMOS transistor connected serially between the reference voltage generating terminal and the ground voltage, for receiving a voltage of a common node of the first resistor and the first NMOS transistor at a gate of the first PMOS transistor and the reference voltage at a gate of the third NMOS transistor.