Patent ID: 8759192
Filing Date: 2014-06-24
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device comprising: forming a first interlayer insulating film over a semiconductor substrate; forming a capacitor recess and a first via hole in the first interlayer insulating film by etching the first interlayer insulating film using as a mask a first resist pattern which has first openings at positions of the capacitor recess and the first via hole, a bottom of the capacitor recess and a bottom of the first via hole reaching to a bottom surface of the first interlayer insulating film; removing the first resist pattern after forming the first via hole and the capacitor recess; after removing the first resist pattern, forming a protective member in the first via hole and the capacitor recess, covering the bottom of the first via hole and the bottom of the capacitor recess; after forming the protective member, forming a second resist pattern which has a second opening over the first interlayer insulating film; after forming the second resist pattern, forming a first wiring trench in the first interlayer insulating film by etching the first interlayer insulating film partway in depth direction thereof using the second resist pattern as a mask, a depth of the first wiring trench being shallower than the first via hole and the capacitor recess, the second opening corresponding to the first wiring trench; removing the second resist pattern and the protective member after forming the first wiring trench; forming a lower conductive film in the capacitor recess, in the first wiring trench and in the via hole, an upper surface of the lower conductive film located on a part of a bottom of the capacitor recess being lower than the upper surface of the first interlayer insulating film; forming a dielectric film over the lower conductive film; forming an upper conductive film over the dielectric film; removing the lower conductive film, the dielectric film and the upper conductive film disposed above the upper surface of the first interlayer insulating film to pattern a lower electrode, a capacitor dielectric film and an upper electrode of a capacitor in the capacitor recess, the lower electrode, the capacitor dielectric film and the upper electrode being formed of a portion of the lower conductive film, a portion of the dielectric film and a portion of the upper conductive film respectively.