Patent ID: 6441433
Filing Date: 2002-08-27
Classification: H01L

Abstract:
A transistor device formed on a semiconductor substrate having active regions defined by isolation trenches, the device comprising:a gate defining a channel interposed between a source and a drain formed within one of the active regions of the semiconductor substrate wherein the source and the drain include main source and drain regions and source and drain extension regions; and a multi-thickness silicide layer formed on the main source and drain regions and the source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the multi-thickness silicide layer which is formed on the main source and drain regions; wherein the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer interposed between an active layer and a main semiconductor substrate and wherein the active regions are further defined by the BOX layer wherein a portion of the multi-thickness silicide layer which is formed on polysilicon regions of the main source and drain regions is thicker than the portion of the multi-thickness silicide layer which is formed on main junction regions of the main source and drain regions.