Patent ID: 6445208
Filing Date: 2002-09-03
Classification: G01R

Abstract:
A semiconductor test system for testing a semiconductor device by supplying a test signal to a semiconductor device under test and evaluating a resultant response output of the device under test, comprising:a test signal generating means for generating a test signal to the device under test based on event data prepared in advance; a pin electronics provided between the test signal generating means and the device under test and having a driver which provides the test signal to the device under test with predetermined amplitude and a comparator which compares a response output of the device under test with a predetermined reference voltage; and a power source current measurement unit provided either inside or outside of the pin electronics for measuring a power source current of the device under test; wherein the power source current measurement unit is comprised of: a DA converter for generating a source voltage which is supplied to a device under test based on a digital signal received; an operational amplifier for forming a negative feedback loop and supplying the source voltage from the DA converter to a power pin of the device under test thereby flowing a power source current to the power pin through a current measurement resistor whose resistance is known; a voltage amplifier for amplifying a voltage representing the power source current supplied to the device under test; an integration circuit formed of an operational amplifier provided with an integration capacitor and a switch for open/close the integration capacitor for integrating an output signal of the voltage amplifier for a predetermined integration time in such a way that the output signal is continuously accumulated during the integration time; and an AD converter for converting an output signal of the integration circuit to a digital signal after the integration time.