Patent ID: 6462596
Filing Date: 2002-10-08
Classification: H03K

Abstract:
A static, double-edge triggered flip-flop comprising:an input terminal; an output terminal; a first switch passing data from the input terminal to a first intermediate node on a clock signal; a first data loop connected between said first intermediate node and said output terminal, wherein said fist data loop includes: (a) a first forward path having a clocked inverter which operates based on a complementary clock signal; (b) a shared path connected to an output of said first forward pat; and (c) a first feedback path connected from an output of said shared path to an input of said first forward path; and a second switch passing data from the input terminal to a second intermediate node on said complementary clock signal second data loop connected between said second intermediate node and said output terminal, wherein said second data loop includes: (a) a second forward pat having a clocked inverter which operates based on said clock signal; (b) said shared path connected to an output of said second forward pat; and (c) a second feedback path connected from an output of said shared path to an input of said second forward path, wherein said shared path of said first and second data loops includes an inverter for inverting data output from the clocked inverters in said first and second for paths.