Patent ID: 7725647
Filing Date: 2010-05-25
Classification: G06F

Abstract:
1. A memory arrangement, comprising: an interface configured to transmit data in the form of data packets according to a predefined protocol; at least two memory banks, each memory bank including at least one memory cell; at least two memory bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks; at least two data packet processing devices configured to encode and/or decode the data packets, wherein the at least two data packet processing devices are assigned to different memory bank access devices; and two temporary storage devices configured to temporary store data, wherein a first of the temporary storage devices is arranged in an area extending from a center between a first of the memory bank access devices and a second of the memory bank access devices in a direction of the first memory bank access device, and a second of the temporary storage devices is arranged in an area extending from the center between the first memory bank access device and the second memory bank access device in a direction of the second memory bank access device.