Patent ID: 6660577
Filing Date: 2003-12-09
Classification: H01L

Abstract:
A method for fabricating metal gates in deep sub-micron CMOS devices comprising the steps of:providing a pre-processed silicon substrate having an active area on a top surface, said active area comprises a PMOS and an NMOS; depositing a gate dielectric layer on said active area of the silicon substrate; blanket depositing a transition metal nitride on said top surface of the substrate; patterning said transition metal nitride to cover said gate dielectric layer only; depositing and patterning a cap layer on top of said PMOS; annealing said substrate by a rapid thermal process (RTP) at a temperature between about 300Â° C. and about 700Â° C., whereby nitrogen evaporates away from said transition metal nitride that is not shielded by said cap layer such that only a transition metal covers said NMOS; and removing said cap layer from top of said PMOS.