Patent ID: 6436755
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method for fabricating a dynamic random access memory (DRAM) cell, comprising the steps of:sequentially forming an oxide film and a doped polysilicon layer on a first silicon substrate having a first conductivity type; patterning the polysilicon layer to form a plate electrode; forming an insulating layer on the first silicon substrate including the plate electrode; bonding a second silicon substrate to the insulating layer; removing the first silicon substrate by a selected thickness through a chemical mechanical polishing process to form a thin silicon layer; forming an isolation film in the silicon layer to define an active region; forming a gate on the active region of the silicon layer and a source and a drain regions in the silicon layer by doping impurities of a second conductivity type in the silicon layer so as to induce a channel in the silicon layer, thereby forming a metal oxide semiconductor transistor, wherein the source and the drain regions are formed in the silicon layer to be spaced in a selected distance from an interface surface between the oxide film and the silicon layer; and forming a purge region by doping impurities of the first conductivity type in the silicon layer.