Patent ID: 7400204
Filing Date: 2008-07-15
Classification: H03D,H03L

Abstract:
1. A method comprising: detecting a phase difference between a first and second signal received by a phase detector; supplying a charge that corresponds to the phase difference using a phase difference to charge conversion that is substantially linear and nonzero in a phase error region that includes a phase error transition region around a phase error of zero having both negative and positive phase error values; making dual determinations, q1 and q2, offset from each other, of an appropriate charge for a given phase error between the first and second signal; supplying as a total charge pump output a charge value representing a combination of q1 and q2, thereby providing a phase error to charge conversion that is substantially linear in the phase error transition region; delaying a first and second output of the phase detector circuit respectively supplying an UP and DOWN signal to the charge pump circuit and supplying as additional outputs of the phase detector circuit a delayed UP signal (UP_DLY) and a delayed DOWN signal (DN_DLY); and resetting the outputs of the phase detector using the delayed UP and the delayed DOWN signals.