Patent ID: 6483337
Filing Date: 2002-11-19
Classification: G01R

Abstract:
A method of testing a semiconductor structure for latchup characteristics comprising:imposing currents of increasing levels on a semiconductor structure; measuring current changes in the semiconductor structure due to the imposition of such increasing levels of current; noting when an imposition of a level of current on the semiconductor structure results in a corresponding current change in the structure which is not substantially linearly proportional to the level of current imposed thereon; halting the imposition of current of increasing levels on the semiconductor structure when a corresponding current change in the semiconductor structure which is not substantially linearly proportional to the level of current imposed thereon is noted; imposing increasing levels of current on a second semiconductor structure; measuring current change in the second semiconductor structure due to the imposition of such increasing levels of current thereon; noting when an imposition of a level of current on the second semiconductor structure results in a corresponding current changes in the second semiconductor structure which in not substantially linearly proportional to the level of current imposed thereon; and halting the imposition of current of increasing levels on the second semiconductor structure when a corresponding current change in the second semiconductor structure which is not substantially linearly proportional to the level of current imposed thereon is noted.