Patent ID: 6647525
Filing Date: 2003-11-11
Classification: G01R

Abstract:
An electronics testing circuit, comprising:a tested circuit including testing cells and a first transceiver coupled to the cells, the first transceiver operable to transmit signals received from the testing cells and to receive signals transmitted for the cells; a second transceiver operable to receive signals from the first transceiver and send signals to the first transceiver; a testing device coupled to said second transceiver and operable to send signals to the second transceiver for the testing cells and receive signals from the testing cells; a translation circuit coupled between the testing circuit and the second transceiver, the translation circuit including a multiplexer, and wherein the signals sent from the testing device are multiple and the multiplexer is operable to generate a single signal from the multiple signals, and the tested circuit includes a demultiplexer operable to generate the multiple signals sent from the testing device from the single signal.