Patent ID: 6376315
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method of manufacturing one or more trench DMOS transistors comprising:providing a substrate of a first conductivity type, forming an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate; forming a region of a second conductivity type within an upper portion of said epitaxial layer; forming A plurality of trenches within said epitaxial layer, said trenches defining one or more body regions within said region of second conductivity type, forming a first insulating layer that lines said trenches; providing a conductive region within said trenches adjacent to the first insulating layer lining said trenches; removing a portion of said first insulating layer along at least upper sidewalls of said trenches such that portions of said body regions are exposed along said upper sidewalls; oxidizing at least said exposed portions of said body regions to form an oxide layer, said oxidizing step resulting in regions of reduced majority carrier concentration within said body regions adjacent said oxide layer; and forming a plurality of source regions of said first conductivity type within upper portions of said body regions adjacent said trenches, said source regions being adjacent said regions of reduced majority carrier concentration within said body regions.