Patent ID: 7462925
Filing Date: 2008-12-09
Classification: H01L

Abstract:
1. A chip stacking structure, comprising: a leadframe having a plurality of leads disposed at a periphery thereof, each lead having a lead inner portion and a lead outer portion, each lead inner portion having a first surface and a second surface, each lead inner portion having a lead via, the lead via extending from the first surface to the second surface; a first chip stack comprising at least one chip, each chip in the first stack having an active surface, a back surface, a plurality of first bonding pads having bonding walls and being disposed on the active surface, and a plurality of first chip via having inner walls with insulating material and extending from first bonding pads through the chip to the back surface; a second chip stack comprising at least one chip, each chip in the second stack having an active surface, a back surface, a plurality of second bonding pads having bonding walls and being disposed on the active surface, and a plurality of second chip via having inner walls with insulating material and extending from second bonding pads through the chip to the back surface; and conducting material within the first chip via, the lead via, and the second chip via, the conducting material electrically connecting first bonding pads to first surfaces of lead inner portions and electrically connecting second bonding pads to second surfaces of lead inner portions.