Patent ID: 6700160
Filing Date: 2004-03-02
Classification: H01L

Abstract:
A semiconductor MOS transistor, comprising:a substrate of a first type; a first well defined on said substrate, said first well being of a second type; a second well defined in said first well, said second well being of said first type; a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor; a second well defined in said first well, said second well being of said first type; a third well defined in said second well, said third well being of said second type, a surface portion of said second well located between said first well and said third well forming a channel region of said semiconductor MOS transistor; a channel compensating implant (CCI) defined in said first well and in a portion of said channel region of said second well to decouple said channel region from said second well; a thin gate oxide formed over the channel region of said second well, said channel compensating implant being adjacent to said thin ate oxide; and a gate terminal defined over said thin gate oxide.