Patent ID: 6223198
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A microprocessor comprisinga first means for multiplying a first multiplier operand and a first multiplicand operand; anda second means for multiplying a second multiplier operand and a second multiplicand operand;wherein said first and second means for multiplying are coupled together and are configured to perform at least two types of multiplication, wherein said first type of multiplication is vector multiplication and is performed when said first and second multiplicand operands each comprise different components of a vector multiplicand operand and said first and second multiplier operands each comprise different components of a vector multiplier operand,wherein said first and second means for multiplying generate a preliminary result in redundant form, and wherein said microprocessor further comprises:an overflow logic means for generating a first non-redundant form result based on said preliminary result, wherein said overflow logic means generates said first non-redundant form result assuming an overflow will occur;a non-overflow logic means for generating a second non-redundant form result based on said preliminary result, wherein said non-overflow logic means generates said second non-redundant form result assuming that no overflow will occur; anda selection means for selecting either said first or second result as a final result.