Patent ID: 8188536
Filing Date: 2012-05-29
Classification: H01L

Abstract:
1. A memory device, comprising. a substrate; a plurality of conductive layers disposed on the substrate, wherein the bottom of each conductive layer is not lower than the entire surface of the substrate; a composite dielectric layer disposed on the substrate and covering the conductive layers, the composite dielectric layer comprising a charge trapping layer that covers the conductive layers; a plurality of gates, disposed on the composite dielectric layer and across the conductive layers, and used as word lines, wherein a bottom of each gate is higher than the entire surface of the substrate; an insulating layer disposed between each conductive layer and the substrate; and a plurality of doped regions disposed in the substrate under ends of the conductive layers, wherein the two doped regions under the ends of two neighboring conductive layers are respectively disposed at one end of one of the two conductive layers and at an opposite end of the other of the two conductive layers, and each doped region includes a lightly doped region partially under a corresponding conductive layer, and a heavily doped region connected with the lightly doped region.