Patent ID: 6055553
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A 64-bit precision digital circuit for computing e.sup.x.sbsp.0 comprising:(a) a master circuit capable of iteratively and sequentially computing the remainders x.sub.i 's, wherein said x.sub.i 's are computed by first setting x.sub.0 =x.sub.0 ; and, in general x.sub.i+1 is computed as follows:i. compute D.sub.i, defined to be x.sub.i -ln(1+2.sup.-i), where ln is defined to be the natural log rounded up to keep only 9 significant figures;ii. if D.sub.i .gtoreq.0 then tentatively set =D.sub.i ; also let the boolean flag s.sub.i be 1; else tentatively set =x.sub.i, and let s.sub.i be 0;iii. if i+1.notident.0(mod 8) then let the final value of be the same as its tentative value; else let k=-7, and compute x'.sub.k, x'.sub.k+1, . . . , x'.sub.i+1, defined as follows: x'.sub.k =x.sub.k ; then for j.gtoreq.k, let x'.sub.j+1 =x'.sub.j -ln(1+s.sub.j 2.sup.-j); can now be computed as follows: compute D', which is defined as x'.sub.i+1 -ln(1+2.sup.-i); if D'.gtoreq.0 then set =D', else set =x'.sub.i+1 ;(b) a slave circuit capable of iteratively and sequentially computing the quantities y.sub.i 's, wherein said y.sub.i 's are defined by letting y.sub.0 =constant, and for i>0,y.sub.i+1 =y.sub.i b.sub.i, b.sub.i =1+s.sub.i 2.sup.-i.