Patent ID: 8988949
Filing Date: 2015-03-24
Classification: G11C

Abstract:
1. A header circuit for controlling a supply voltage for a cell, comprising: a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor, the first pull-up PMOS transistor comprising a first gate, a first source, and a first drain; a pull-up control unit configured to control biasing for the first gate of the first pull-UP PMOS transistor based on a shut down signal, a bank select signal, and a write mux signal, the shut down signal corresponding to a first logic state when a header circuit is to be in a shutdown mode and corresponding to a second logic state when the header circuit is to be in a non-shutdown mode; and a second pull-down PMOS transistor, the second pull-down PMOS transistor comprising a second gate, a second source, and a second drain, the first drain of the first pull-up PMOS transistor coupled to the second source of the second pull-down PMOS transistor and a supply voltage line for a cell.