Patent ID: 8773916
Filing Date: 2014-07-08
Classification: G11C

Abstract:
1. A nonvolatile memory device, comprising: a memory cell array including a plurality of memory cells connected to word lines and bit lines; a voltage generator configured to generate a program voltage and verify voltages; an address decoder configured to apply the program voltage during a programming operation to a selected word line among the word lines in response to an address and to apply the verify voltages to the selected word line during each one of a number of verifying operations; a plurality of page buffers connected to the bit lines and configured to store data to be programmed to memory cells connected to the selected word line during the programming operation and to store data read from the memory cells during each of the verifying operations; and control logic configured to control the voltage generator, the address decoder and the plurality of page buffers to sequentially executes a number of program loops, each program loop including the programming operation and one of a number of verifying operations, wherein a 2 -step verification operation differentiating between slow memory cells and fast memory cells among the memory cells in relation to a target program state is selected by the control logic for a given program loop when a number of previously executed program loops does not exceed a predetermined programming interval threshold, and a 1 -step verification operation differentiating the target program state is selected by the control logic for the given program loop when the number of previously executed program loops exceeds the predetermined programming interval threshold.