Patent ID: 7443762
Filing Date: 2008-10-28
Classification: G11C

Abstract:
1. A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprising: a controllable first FIFO clocked by a data strobe write clock control signal (WDQS signal) and storing write data on the basis of one or more successive write commands; a controllable second FIFO clocked by an internal clock signal and storing, for a write operation, only addresses associated with valid write data of said write data stored in said first FIFO; and a first control circuit for controlling said first FIFO; said first control circuit being clocked by said WDQS signal and utilizing said WDQS signal to generate an input pointer indicating at what location in said first FIFO said write data are to be buffer-stored.