Patent ID: 6498377
Filing Date: 2002-12-24
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a substrate having a source region, a drain region, and a channel region formed therebetween; a first oxide layer formed over the channel region; a nitride layer formed over the first oxide layer; a second oxide layer formed over the nitride layer; a gate structure formed over the second oxide layer, wherein a region in the substrate underneath the gate structure excludes one of the source and drain regions; and at least one sidewall spacer formed over the nitride layer and contiguous with the gate structure, wherein the at least one sidewall spacer has a dielectric constant value sufficient to form an inversion region in a substrate region underneath the sidewall spacer to connect the region beneath the sidewall spacer with the channel, source and drain regions, and wherein electron charges are stored in portions of the nitride layer underneath the at least one sidewall spacer.