Patent ID: 6680543
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A semiconductor integrated circuit, comprising:a bonding pad; a semiconductor substrate electrically insulated from the bonding pad and having a first region and a second region defined in a surface of the semiconductor substrate facing the bonding pad with the second region (a) at least partially surrounding the first region only in a plane parallel to a surface of the semiconductor substrate facing the bonding pad, wherein a part of the first region is not surrounded by the second region and said part corresponds to a fan-shaped area, and (b) defined such that substantially no portion of the second region is directly under the bonding pad; and only the first region is under the bonding pad; and setting means for setting the second region of the semiconductor substrate substantially at an equipotential; the setting means includes a conductive section having a plurality of basic cells arranged in an array; and said semiconductor integrated circuit further comprises a low resistance layer in said semiconductor substrate.