Patent ID: 7949803
Filing Date: 2011-05-24
Classification: G06F

Abstract:
1. A memory hub, comprising: an upstream transmission port configured to transmit a digital signal; an upstream reception port configured to receive a digital signal; a downstream transmission port configured to transmit a digital signal; a downstream reception port configured to receive a digital signal; a downstream request routing circuit coupled to the downstream reception port, the local memory port and the downstream transmission port, the downstream request routing circuit being configured to determine whether the memory request is directed to a local memory device or whether the memory request is directed to a downstream memory device, the downstream request routing circuit further being configured to couple the digital signal received by the downstream reception port to the local memory port responsive to a determination that the memory request is directed to a local memory device and to couple the digital signal received by the downstream reception port to the downstream transmission port responsive to a determination that the memory request is directed to a downstream memory device; a bypass circuit coupled to a local memory port, the upstream transmission port and the upstream reception port, the bypass circuit being configured to selectively couple the upstream transmission port to the local memory port or to the upstream reception port; and a breakpoint circuit coupled to the bypass circuit configured to identify a breakpoint in a digital signal received from either the local memory port or the upstream reception port, the breakpoint circuit being configured to be responsive to the identification to couple a control signal to the bypass circuit to initiate a switch between the upstream reception port and the local memory port.