Patent ID: 6072354
Filing Date: 2000-06-06
Classification: H03K

Abstract:
A semiconductor device comprising an internal circuit and a first outputting circuit for outputting a signal from said internal circuit, wherein said first outputting circuit includes:a first transistor of p-type and a second transistor of n-type which are connected in series between a first potential and a second potential which is lower than the first potential;an output node connected to the coupling node of the first and second transistors;a first boosting circuit for generating a third potential which is lower than the second potential and supplying the third potential to the gate of the first transistor in response to a signal from said internal circuit; anda second boosting circuit for generating a fourth potential which is higher than the first potential and supplying the fourth potential to the gate of the second transistor in response to a signal from said internal circuit, wherein the first boosting circuit includes:a first input node;a first output node coupled to the gate of the first transistors;a first inverter having an input coupled to the first input node;a third transistor of p-type having a source coupled to the first potential, a gate coupled to the output of the first inverter, and a drain coupled to the first output node;a fourth transistor of n-type having a drain coupled to the first output node and a gate coupled to the output of the first inverter;a first boosting capacitor having a first electrode coupled to the first input node and a second electrode coupled to the source of the fourth transistor; anda fifth transistor of p-type having a source coupled to the source of the fourth transistor, a drain coupled to the second potential, and a gate coupled to the second potential, and wherein the second boosting circuit includes:a second input node;a second output node coupled to the gate of the second transistors;a second inverter having an input coupled to the second input node;a second boosting capacitor having a third electrode coupled to the output node of the second inverter and a fourth electrode;a sixth transistor of n-type having a drain coupled to the first potential, a gate coupled to the first potential, and a source coupled to the fourth electrode;a seventh transistor of p-type having a source coupled to the fourth electrode, a gate coupled to the second input node, and a drain coupled to the second output rode; andan eighth transistor of n-type having a drain coupled to the second output node, a gate coupled to the second input node, and a source coupled to the second potential.