Patent ID: 6345363
Filing Date: 2002-02-05
Classification: G06F,Y02D

Abstract:
An apparatus including a core circuit for implementing a microprocessor core with reduced power consumption, said core circuit comprising:plurality of data buses, configured to transmit a plurality of operands; a plurality of operand storage circuits, coupled to said plurality of data buses, said plurality of operand storage circuits configured to receive a plurality of sets of load commands and in accordance therewith load selected ones of said plurality of operands, and configured to output said loaded plurality of operands; a plurality of operating circuits, coupled to said plurality of operand storage circuits, said plurality of operating circuits configured to receive said plurality of operands and in accordance therewith generate a plurality of result signals, wherein each set of said plurality of sets of load commands is associated with one of said plurality of operating circuits; and a control circuit, coupled to said plurality of operand storage circuits and said plurality of operating circuits, said control circuit configured to selectively generate said plurality of sets of load commands, wherein said selected ones of said plurality of operands comprise operands not previously stored in said plurality of operand storage circuits, wherein power is conserved by loading only said selected ones of said plurality of operands.