Patent ID: 8072820
Filing Date: 2011-12-06
Classification: G11C

Abstract:
1. A memory device, comprising: a multiplexer having a first set of terminals, a second set of terminals, a third set of terminals and a control terminal, the multiplexer being operable to couple the first set of terminals to the second set of terminals responsive to a signal applied to the control terminal having a first logic level, the multiplexer further being operable to couple the first set of terminals to the third set of terminals responsive to the signal applied to the control terminal having a second logic level that is different from the first logic level; a control logic unit coupled to the second set of terminals; an address decoder; an array of memory cells; and an I/O control unit coupled to the third set of terminals, the I/O control unit being operable to couple the third set of terminals to either the address decoder or the array of memory cells.