Patent ID: 6785780
Filing Date: 2004-08-31
Classification: G06F,G11C

Abstract:
A memory module comprising:a memory interface having a data bus, an address bus, and a control bus adapted to interface with a computer system data bus, a computer system address bus and a computer system control bus, the system data bus having a first data width; a program memory coupled to the data bus and address bus of the memory interface, the program memory being structured to store data representative of instructions on the data bus responsive to a first set of addresses on the computer system address bus; a program memory controller coupled to the program memory and structured to transfer instructions from the program memory; and a plurality of memory/processing units each of which includes a processor coupled to a system memory via a memory/processing data bus having a second data width greater than the first data width, the processor being coupled to the controller to have access through the controller to instructions stored in the program memory and being further coupled to the system memory to allow the processor to access the system memory, the system memory further being coupled to the computer system data bus and the computer system address bus to allow the system memory to be accessed through the computer system data bus and the computer system address bus responsive to a second set of addresses on the computer system address bus, at least some of the addresses in the second set being different from the addresses in the first set.