Patent ID: 8670264
Filing Date: 2014-03-11
Classification: G11C

Abstract:
1. A memory array organized into rows and columns of resistive elements, the memory array comprising: a first pair of access transistors coupled to each other and a first and second word lines; a first resistive element coupled to the first pair of access transistors and to a first sense line; a second pair of access transistors coupled to each other and a third and fourth word lines; a second resistive element coupled to the second pair of access transistors and to the first sense line; a first pair of reference access transistors coupled to each other and the first and second word lines; a first reference resistive element coupled to the first pair of reference access transistors and to a second sense line; a second pair of reference access transistors coupled to each other and the third and fourth word lines; a second reference resistive element coupled to the second pair of reference access transistors and to the first sense line, wherein the first resistive element is written to while the second resistive element is read.