Patent ID: 6327642
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A memory system comprising:a first interface circuit for coupling the memory system to one or more external memory masters, wherein the first interface circuit receives address and data information from the memory masters;a first bus coupled to the interface circuit for receiving address and data information from the first interface circuit;a main memory array including a plurality of memory banks;a second bus coupled to the main memory array, wherein the second bus receives data values read from the main memory array;a bus bypass circuit which couples the first bus to the second bus;a plurality of cache memory arrays connected in parallel between the first bus and the second bus, wherein each of the cache memory arrays receives data information from the first bus and the second bus;a plurality of cache address arrays connected in parallel between the first bus and the second bus, wherein each of the cache address arrays receives address information from the first bus, each of the cache address arrays further being coupled to a corresponding one of the cache memory arrays, wherein each cache address array and corresponding cache memory array form a virtual cache channel which is independently addressable by the one or more memory masters and which accesses any of the plurality of memory banks of the main memory array.