Patent ID: 6156604
Filing Date: 2000-12-05
Classification: H01L

Abstract:
A method of fabricating a memory array, the method comprising the steps of:forming a number of access transistors, each access transistor formed in a pillar of semiconductor material that extends outwardly from a substrate wherein the access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon;forming a trench capacitor for each access transistor, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor;forming a number of word lines, each along a side of one of the pillars, that interconnect the gates of a number of access transistors to form a row of the array, each word line disposed in a trench that separates adjacent rows of access transistors; andforming a number of bit lines that interconnect second source/drain regions of selected access transistors so as to form a number of columns of the array.