Patent ID: 7060539
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A method of fabricating an FET device comprising the steps of: forming a semiconductor structure comprising a source region, a drain region over a horizontal surface of a substrate comprising an insulating material; forming a channel structure over the horizontal surface of the substrate connecting between the drain region and the source region, with the channel structure comprising a horizontally oriented, planar fin composed of a semiconductor material, with the planar fin being formed above a vertical fin, with the vertical fin being composed of a material selected from the group consisting of a semiconductor material and an insulating material, with the planar fin and the vertical fin having a T-shaped cross-section, the vertical fin having a proximal edge and a distal edge, with the proximal edge in contact with the horizontal surface of the substrate and with the planar fin in contact with the distal edge of the vertical fin; forming a gate dielectric layer over exposed surfaces of the channel structure; and forming a gate electrode straddling the channel gate dielectric and the channel structure.