Patent ID: 8717081
Filing Date: 2014-05-06
Classification: H03K

Abstract:
1. A non-overlapping clock generator, comprising: a first set of N pulse-generating modules connected in series, each of the N pulse-generating modules having an input node, an enabling node, and an output node, N being an integer larger than 1, the input node of one pulse-generating module coupled to the output node of another pulse-generating module among the pulse-generating modules; an enabling module for providing enabling signals to the respective enabling nodes; wherein, for each pulse-generating module, when an input signal at the input node is at a high voltage level, the enabling module triggers, after a delay caused by at least one semiconductor switch, the input signal at the input node to turn to a low voltage level, so that an output signal at the output node is pulled to the high voltage level accordingly; and a reset module for resetting one of the input nodes to the high voltage level and resetting the other input nodes to the low voltage level.