Patent ID: 6087190
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A method of manufacturing a plurality of integrated circuit devices including memory, the memory including an array of memory cells having characteristics determined by results of a test, the array including a plurality of rows and a plurality of columns selected by addresses; comprising:providing a test column of memory cells in the devices, said memory cells in the test column being selected by a portion of the addresses which identifies a row in the array;executing the test for a particular device in the plurality of integrated circuit devices to determine the characteristic for the particular device, mapping the results of the test to a given row in the array associated with the test to produce a characteristic code address for the particular device, enabling access to the test column for the particular device, and writing, in response to the characteristic code address, a bit in a memory cell in the test column in the given row of the particular device; andreading the test column in the particular device to classify the particular device according to the characteristic.