Patent ID: 9019771
Filing Date: 2015-04-28
Classification: G11C

Abstract:
1. A method of operating memory cells within an array of dielectric charge trapping memory cells, the array of dielectric charge trapping memory cells including a plurality of bit lines BL(i), for i between 0 and N, and a plurality of word lines WL(j), for j between 1 and M, the array including a plurality of columns of memory cells and a plurality of rows of memory cells, each column being disposed between bit line BL(i) and bit line BL(i+1), and each row R(j) of the memory cells being coupled to a corresponding word line WL(j), and wherein a memory cell in the array has a first charge trapping site adjacent to the bit line BL(i+1) and a second charge trapping site adjacent to the BL(i), comprising: writing a data value in a logical cell for a selected column address A reading a data value for a selected column address A