Patent ID: 8692597
Filing Date: 2014-04-08
Classification: H03L

Abstract:
1. An integer-N phase-locked loop clock generator, where N is a positive integer, comprising: a reference clock; a first phase generator for generating N first phase signals from a signal from the reference clock; a voltage controlled oscillator; a clock divider for dividing down a signal from the voltage controlled oscillator; a second phase generator for generating N second phase signals from the divided down voltage controlled oscillator signal; a mapper configured to receive N phase pairs and output the N phase pairs as M phase pairs, where M is a positive integer greater than N, each of the N phase pairs comprising a respective one of the N first phase signals generated by the first phase generator and a respective one of the N second phase signals generated by the second phase generator; M phase frequency detectors, each phase frequency detector configured to receive a respective one of the M phase pairs, and to generate a pulse signal based on a comparison of the first phase signal with the second phase signal of the respective received phase pair; M charge pumps, each charge pump configured to receive the pulse signal generated by a respective one of the M phase frequency detectors and to generate a control current based on the received pulse signal; and a loop filter for receiving the control current from each of the M charge pumps and for controlling the voltage controlled oscillator based on the received control currents.