Patent ID: 7986567
Filing Date: 2011-07-26
Classification: G11C

Abstract:
1. A buffering system for reading data from embedded non-Flash vertically stacked non-volatile memory, comprising: a silicon substrate including a logic layer having circuitry fabricated on the logic layer, the circuitry including a plurality of read buffers, each read buffer electrically coupled with the partition selector and a control signal from the NOR-type interface, each read buffer having an output electrically coupled with the multiplexor circuit; and a plurality of memory planes in direct contact with and fabricated directly above the silicon substrate, each memory plane including at least one re-writeable non-volatile two-terminal cross-point memory array embedded therein and having a plurality of first conductive array lines electrically coupled with the array line driver and a plurality of second conductive array lines electrically coupled with the partition selector.