Patent ID: 7057277
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. A chip package structure, comprising: a carrier; a chip, having an active surface with a plurality of bumps thereon, wherein the chip is bonded and electrically connected to the carrier in a flip-chip banding process; a heat sink, set over the chip, wherein the heat sink has a surface area greater than the chip and is unconnected to the carrier; a plurality of standoff components, disposed over the heat sink and in a peripheral area of the chip package structure, wherein the standoff components have a spherical shape; and an encapsulating material layer, filling a bonding gap between the chip and the carrier and covering the heat sink and the carrier, wherein a top surface of the encapsulating material layer is higher than that of the heat sink and the encapsulating material layer is formed in a simultaneous molding process.