Patent ID: 6239017
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A method of fabricating conductive wiring and a contact hole on a semiconductor substrate comprising:forming a first insulation layer, comprising an undoped silicon oxide, on said semiconductor substrate;forming a second insulation layer, comprising a ternary doped silicon oxide, on said first insulation layer;forming a third insulation layer, comprising an undoped silicon oxide, on said second insulation layer;forming an opening in said third insulation layer at a first location where said contact hole is desired, said opening penetrating through said third insulation layer;forming a trench in said third insulation layer at a second location where said wiring is desired while simultaneously extending said opening through said second insulation layer and through said first insulation layer wherein said trench is wider than and entirely inclusive of said opening;heating the three insulation layers to a temperature below the flow temperature of the second insulation layer for a period of time sufficient to only soften and partially reflow said second insulation layer at the edges of the contact opening, thus forming a tapered contact opening in said second insulation layer;depositing a conductive material on said third insulation layer, in said trench, and in said opening so that said conductive material completely fills said trench and said opening; andremoving by CMP said conductive material from the surface of said third insulation layer.