Patent ID: 6166444
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A cascade-type chip module, comprising:a laminate substrate having a plurality of contacts;a plurality of chips on the laminate substrate such that each of the chips comprises:a plurality of bonding pads;a first insulating layer over the substrate and exposing the bonding pads;a redistribution layer having a first region and a second region on the first insulating layer, wherein the redistribution layer is coupled with the bonding pads; anda plurality of bump contacts over the redistribution layer coupling with the redistribution layer, in which a layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrial to the layout of the bump contacts coupling with the second region of the redistribution layer, and each of the bump contacts at the first region is coupled with a corresponding bump contact at the second region through the redistribution layer;wherein the chips are divided into a first group and a second group, the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group, and chips are coupled to each other by bumps; andtwo film carriers respectively coupling the first group of chips and the second group of chips with the contacts.