Patent ID: 7236422
Filing Date: 2007-06-26
Classification: G09G

Abstract:
1. A driver circuit which, arranged in the peripheral part of an image display device, supplies in parallel a plurality of analog voltages corresponding to digital signals entered serially, comprising: first and second DA converters which convert said digital signals, in accordance with more significant bits thereof, into analog voltages; a voltage divider which, arranged in the gap between said first and second DA converters, divides the output voltages of said first and second DA converters in accordance with less significant bits of said digital signals; and a shift register which generates trigger signals in synchronism with said digital signals, wherein: said voltage divider comprises decoders, memory elements arrayed in two-dimensional matrixes, and a plurality of resistive wirings; and said memory elements are so configured as to store decoded signals generated by said decoders in synchronism with said trigger signals, and selectively supply, in accordance with the decoded signals stored by said memory elements, the divided voltages which derive from said first and second DA converters and are generated on said resistive wirings.