Patent ID: 6681277
Filing Date: 2004-01-20
Classification: H04N

Abstract:
A data processing apparatus comprising:a bus for which a band-guaranteed cycle capable of transferring stream data in real time by assigning a predetermined reserved band for each cycle time, is defined; a plurality of nodes connected to the bus and capable of sending/receiving the stream data using the band-guaranteed cycle; means having a first bus access mode for transferring data in synchronization with one of rising and falling edges of a clock and a second bus access mode for transferring data in synchronization with each of the rising and falling edges of the clock, for setting a sender node for sending the stream data and a receiver node for receiving the stream data from the sender node, into one of the first and second bus access modes to perform a transfer of stream data using the band-guaranteed cycle; and means for supplying channel numbers assigned to the sender node and the receiver node to said bus to start the transfer of the stream data from the sender node to the receiver node.