Patent ID: 6321303
Filing Date: 2001-11-20
Classification: G06F

Abstract:
A cache system comprising:a cache memory coupled to a load/store unit of a central processing unit;a buffer unit coupled to the cache memory, the buffer unit comprised of a plurality of buffer unit entries suitable for temporarily storing operations generated by the central processing unit, wherein each buffer unit entry includes a single-bit transaction type field indicative of whether the corresponding transaction requires data via said system bus;a bus transaction queue coupled to the buffer unit, wherein the bus transaction queue includes a plurality of entries wherein each bus transaction queue entry includes a pointer to one of the plurality of buffer unit entries; andwherein the buffer unit, in response to a first operation initiated by the load/store unit, is configured to buffer the first operation in a corresponding entry of the buffer unit and queue a first transaction in a first entry of the bus transaction queue, wherein said bus transaction queue is further configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event occurring after the queuing of the first transaction.