Patent ID: 8131942
Filing Date: 2012-03-06
Classification: G06F,Y02D

Abstract:
1. Apparatus for processing data comprising: a memory; at least one processor coupled to said memory and responsive to program instructions to perform data processing operations; and a cache memory coupled to said memory and to said processor; wherein said cache memory has validity data and control data associated therewith, said validity data specifying if cached data is valid data and said control data specifying how access to cached data is controlled, and said cache memory is responsive to one or more program instructions executed by one of said at least one processors to modify said control data, wherein said at least one processor has one of a plurality of access states associated therewith; said memory has at least one controlled region accessible to one of said at least one processor having an authorised access state and non-accessible to one of said at least one of said processor not having said authorised access state; said control data including an access field marking cached data as either controlled data cached from a controlled region of said memory or not controlled data not cached from a controlled region of said memory, cached data marked as controlled data within said cache memory accessible to one of said at least one processor having said authorised access state and being non-accessible to one of said at least one processor not having said authorised access state, wherein said at least one processor comprises a processor having a secure state and a non-secure state, said memory having at least one secure region accessible to said processor when operating in said secure state and non-accessible to said processor when operating in said non-secure state; and said access field is a security flag marking cached data as either secure data cached from a secure region of said memory or non-secure data cached from a non-secure region of said memory, cached data marked as secure data within said cache memory being accessible to said processor when operating in said secure state and non-accessible to said processor when operating in said non-secure state; wherein said cache memory, in response to program instructions executed by said processor, setting said security flag associated with cached data cached within said cache memory without flushing and reloading the cached data, said processor being unable to set said security flag when operating in said non-secure state.