Patent ID: 6157986
Filing Date: 2000-12-05
Classification: G06F

Abstract:
A cache having fast linear tag validation comprising:a data array configured to store a plurality of cache lines;a linear tag array configured to store a plurality of linear tags with corresponding linear tag valid bits, wherein each linear tag corresponds to one cache line stored within the data array;a physical tag array configured to store physical tags corresponding to the contents of the data array; anda translation lookaside buffer configured to store linear to physical address translations, wherein the data array, the linear tag array, the physical tag array and the translation lookaside buffer are each coupled to receive a portion of a requested address, wherein the linear tag array is configured to compare a first portion of the requested address with each of the plurality of stored linear tags and validate all linear tags that correspond to the first portion of the requested address, wherein the linear tag array further comprises a content addressable memory configured to receive and compare a portion of the requested address with each of the plurality of stored linear tags in parallel, wherein the content addressable memory is configured to validate all linear tags in parallel that correspond to the first portion of the requested address.