Patent ID: 7101758
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. A method for forming triple polysilicon split gate electrodes in an EEPROM flash memory array comprising the steps of: providing a gate structure comprising a gate dielectric formed over a semiconductor substrate, an overlying first polysilicon electrode and an overlying first dielectric insulating layer; forming a first polysilicon layer over the gate structure; etching back the first polysilicon layer through a portion of the first polysilicon layer thickness according to a first dry etching process to partially smooth the first polysilicon layer topography; forming a second dielectric insulating layer over the first polysilicon layer; forming a second polysilicon layer over the second dielectric insulating layer; and, then lithographically patterning and dry etching according to respective sequential dry etching processes through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.