Patent ID: 8370409
Filing Date: 2013-02-05
Classification: G06F

Abstract:
1. A computer system comprising: a recoding circuit that receives two N-bit input operands (A, B) having a bit width of N as an input, wherein the recoding circuit recodes the two N-bit input operands (A, B) to two M-bit output operands (A′, B′) having a reduced bit width of M; wherein the recoding circuit detects special saturation cases of the N-bit input operands; wherein the recoding of the two N-bit input operands (A, B) to the two M-bit output operands (A′, B′) is performed by adding portions of the two N-bit input operands (A, B) together, and wherein based on a result of the addition and one or more bits of the two N-bit input operands (A, B) the two M-bit output operands (A′, B′) are computed; wherein the recoding is performed by sign extending the two N-bit input operands (A, B) by one bit and adding (N−M+1) most significant bits (MSB) of the sign extended inputs together; wherein two MSB of the M-bit output operands (A′, B′) are computed based on MSB of the two N-bit input operands (A, B) and the result of the addition, and wherein M−2 least significant bits (LSB) of the two M-bit output operands (A′, B′) are set to M−2 LSB of the two N-bit input operands (A, B); wherein a control signal is detected based on the two MSB of the N-bit input operands (A, B) and provided to a saturation circuit, and wherein the control signal is used to revert a saturation direction in the saturation logic; the recoding circuit providing an output comprising the two M-bit output operands (A′, B′); and wherein the two M-bit output operands (A′, B′) are coupled to an M-bit adder followed by saturation to M bits, wherein the two M-bit output operands (A′, B′) provide an M-bit result equal to another M-bit result of an N-bit modulo addition of the two N-bit input operands (A, B) followed by a saturation to M bits.