Patent ID: 8442107
Filing Date: 2013-05-14
Classification: H04N

Abstract:
1. A memory mapping apparatus in a video decoder/encoder, comprising: a dividing unit dividing picture data into macroblocks and dividing each of the macroblocks into partitions having a size of accessible data in a one-time address request in a burst mode, each macroblock being a unit of encoding; a storage unit comprising at least two memory banks, each of the memory banks being independently accessible; a memory allocation unit allocating adjacent partitions to different memory banks; and a memory controller transmitting addresses of to-be accessed data to respective memory banks sequentially for a latency before the data is accessed, wherein after transmitting the addresses, the data in each of the memory banks is accessed sequentially without an additional latency, wherein the size of accessible data is dynamically determined based on an encoding scheme of the picture data.