Patent ID: 8533535
Filing Date: 2013-09-10
Classification: G06F

Abstract:
1. A memory system comprising: A memory controller comprising: a command generator configured to generate commands; a first counter configured to count a first number of commands in response to a clock signal; a first register configured to store the first number of commands counted; and a first interface configured to interface with a memory device including transmitting the commands, the first number of commands counted, address, and transmitting and receiving data; the memory device comprising: a second interface configured to interface with the memory controller including receiving the commands, the first number of commands counted, the address and the data from the memory controller; a second counter configured to count a second number of commands received in response to the clock signal; and a second register configured to store the second number of commands received, wherein the second interface is further configured to transmit the second number of commands received to the memory controller.