Patent ID: 6395598
Filing Date: 2002-05-28
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:a) preparing a device prototype including: an MIS transistor formed in an active region of a semiconductor substrate; and a trench isolation structure formed in an isolation region of the semiconductor substrate, where a stepped portion is formed between the respective upper surfaces of the active region and the trench isolation structure, with the step on the upper surface of the trench isolation structure lower than that of the active region, and at least part of source/drain regions of the MIS transistor is exposed on a side of the stepped portion; b) after the step a), depositing an insulating film as etch stop layer over the semiconductor substrate including the device prototype; c) depositing an interlevel dielectric film over the insulating film; d) with the insulating film as etch stop layer, etching a portion of the interlevel dielectric film that covers across the upper region of a part of the source/drain regions and the upper region of a part of the trench isolation structure that resides beside the part of the source/drain regions, thereby forming an opening in the interlevel dielectric film; e) etching anisotropically part of the insulating film that is exposed on the bottom of the opening formed in the interlevel dielectric film, thereby forming an insulating sidewall spacer out of the insulating film on the side of the stepped portion and partially exposing the upper surface of the source/drain regions; and f) forming an electrode that comes into contact with the source/drain regions through the opening formed in the interlevel dielectric film.