Patent ID: 8772920
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A chip package, comprising: a group of semiconductor dies arranged in a plank stack in an x direction, wherein a plane of a given semiconductor die is defined by a z direction and a y direction, wherein the semiconductor dies include first electrical pads proximate to edges of the semiconductor dies, wherein the edges of the semiconductor dies define a face of the plank stack, wherein surfaces of the semiconductor dies are defined by the z direction and the y direction, and wherein the surfaces of the semiconductor dies include negative features recessed below the surfaces; positive features mechanically coupled to the negative features on adjacent semiconductor dies, thereby aligning the semiconductor dies in the plank stack; and an interposer plate electrically coupled to the semiconductor dies along the x direction, wherein a plane of the interposer plate is defined by the x direction and the y direction; wherein the electrical coupling to the semiconductor dies is between the first electrical pads, second electrical pads proximate to a surface of the interposer plate along the x direction, and an intervening conductive material between the first electrical pads and the second electrical pads.