Patent ID: 7844938
Filing Date: 2010-11-30
Classification: G03F,G06F

Abstract:
1. A method for performing a data correction on a hierarchical integrated circuit layout accommodating a long range critical dimension (CD) variation caused by a process in manufacturing an integrated circuit based on the layout, the method comprising: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges using a computer; super-imposing multiple regions of the CD compensation map having a compensation amount falling into a compensation range over respective target layers based on the respective compensation ranges to generate multiple target shapes; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the multiple target shapes separately from the data corrected layout to generate multiple data corrected target shapes; and combining the data corrected layout and the multiple data corrected target shapes based on the CD compensation map.