Patent ID: 6674303
Filing Date: 2004-01-06
Classification: H03K

Abstract:
An I/O circuit for use in conjunction with a pin of an integrated circuit, comprising:a first buffer providing a first output signal on said pin; a second buffer receiving a first input signal from said pin; a first terminal coupled to receive a second input signal from a first neighboring I/O circuit; a second terminal coupled to provide a second output signal to a second neighboring I/O circuit; a first multiplexer selecting from a first group of signals to provide a first data signal, said first group of signals including said second input signal; a first flip-flop receiving said first data signal to provide an output value to be output by said first buffer as said first output signal and to be output at said second terminal as said second output signal; a second multiplexer selecting from a second group of signals to provide a second data signal, said second group of signals including said first input signal and said second output signal; and a second flip-flop receiving said second data signal to provide a received data signal, said received data signal being included in said first group of signals.