Patent ID: 6405269
Filing Date: 2002-06-11
Classification: G06F,G11C

Abstract:
A first-in first-out (FIFO) memory system, comprising:a memory having a plurality of locations each having an address, a write address port for receiving a sequence of write address values during write operations, and a read address port for receiving a sequence of read address values during read operations; and a comparator circuit for detecting an empty condition of the memory by comparing a write address value with first and second read address values, the comparator circuit comprising: first and second logic circuits for respectively generating first and second logic signals, the first logic signal having a value determined by comparing a first bit of the first read address value and a first bit of the write address value, and the second logic signal having a value determined by comparing a first bit of the second read address value and the first bit of the write address value, a first mode control multiplexer having a first input terminal connected to receive the first logic signal, and a second input terminal connected to receive the second logic signal, a first carry chain multiplexer having a select input terminal connected to an output terminal of the first mode control multiplexer, a first input terminal connected to a first source maintained at a first logic level, and a second input terminal connected to a second source maintained at a second logic level, and a register for storing an EMPTY control signal; wherein a data input terminal of the register is coupled to an output terminal of the first carry chain multiplexer, and an output terminal of the register is connected to a select terminal of the first mode control multiplexer.