Patent ID: 8603894
Filing Date: 2013-12-10
Classification: H01L

Abstract:
1. A method for forming a complementary metal-oxide semiconductor (CMOS) structure with equal proximity of source/drain (SD) stressors to channels of adjacent N-type and P-type field effect transistors (FETs) formed on a substrate comprising: forming a stacked spacer on the N-type FET and the P-type FET, the stacked spacer comprising a stack comprising a top nitride layer, an oxide layer, and a lower nitride layer, wherein the lower nitride layer determines the proximity of the SD stressors to the channel for the N-type and P-type FETs; forming a first photoresist on the CMOS structure which covers the N-type FET and exposes the P-type FET; implanting ions in an exposed portion of the top nitride layer of the P-type FET; etching, selectively, an exposed portion of the top nitride layer and a portion of the oxide layer below the exposed portion of the top nitride layer such that the top nitride layer and the oxide layer are completely removed from the sidewalls of a gate electrode of the P-type FET; removing the first photoresist to expose the portion of the stacked spacer on the N-type FET; forming a first nitride spacer on sidewalls of the gate electrode of the P-type FET; by removing remaining portions of the lower nitride layer of the stacked spacer on the P-type FET; forming the SD stressors of the P-type FET on opposite sides of the gate electrode, wherein a distance between the SD stressors and the P-type FET is controlled by the first nitride spacer; depositing a dielectric layer over the CMOS structure; forming a second photoresist on the CMOS structure which covers the P-type FET and exposes the N-type FET; implanting ions in an exposed portion of the top nitride layer of the N-type FET; etching, selectively, an exposed portion of the top nitride layer and a portion of the oxide layer below the exposed portion of the top nitride layer such that the top nitride layer and the oxide layer are completely removed from the sidewalls of a gate electrode of the N-type FET; removing the second photoresist to expose the portion of the stacked spacer on the P-type FET; forming a second nitride spacer on sidewalls of the gate electrode of the N-type FET by removing remaining portions of the lower nitride layer of the stacked spacer on the N-type FET; forming the SD stressors of the N-type FET on opposite sides of the gate electrode, wherein a distance between the SD stressors and the N-type FET is controlled by the second nitride spacer; and removing the dielectric layer.