Patent ID: 6615324
Filing Date: 2003-09-02
Classification: G06F

Abstract:
A protected memory, comprising:an address input for receiving an address; a memory space of addressable memory locations, each having an associated address and each for storage of information therein as stored information, said memory space having a restricted area and a user area, wherein addressing of one of said addressable locations therein results in the output of stored information therefrom in response to the receipt of an associated address on said address input, at least one of said addressable memory locations in said user area having an executable instruction stored therein; a logic device for determining if a received address on said address input corresponds to an attempt to access an addressable location in the restricted area for output of information therefrom as the result of execution of a program instruction from said user area by an external processor; and an inhibit device for inhibiting access to information stored in said addressable locations if a positive determination is made by said logic device that the execution of a program instruction from said user area will result in access of information in said restricted area for the purpose of outputting of the contents of said addressable locations in said restricted area, but launching of an executable instruction in said restricted area from an executable instruction in said user area is allowed.