Patent ID: 6912663
Filing Date: 2005-06-28
Classification: G06F

Abstract:
1. A computer comprising: a processor; a memory having a memory address space, the memory address space comprising a stored program, the stored program including a power-on-self-test (POST); a first input device operatively connected to the processor; an adapter read-only-memory (ROM) located in certain blocks of the memory address space; a control associated with the POST for preventing an input from the first input device during the POST to prevent user inputs from entering the memory; a security signature in the adapter ROM for identifying if the first input device may temporarily accept a user input; a ROM security routine for determining if user input is required and further including a test for user authorization; an indicator stored in the memory for permitting a user input during at least a portion of the POST, with the processor responding to the indicator and allowing a user input at the input device during POST by at least temporarily overriding the control preventing a user input during the POST if the user successfully satisfies the authorization test; and a second input device operatively connected to a Universal Serial Bus (USB) port in the computer, wherein the second input device is selectively locked out during the POST, and wherein the second input device being selectively locked out is dependent on the first input device being prevented from inputting a signal during the POST.