Patent ID: 7491999
Filing Date: 2009-02-17
Classification: G11C,H01L

Abstract:
1. A process of fabricating a non-volatile memory cell array, comprising: forming strips of electrically conductive material across a semiconductor substrate with a layer of dielectric therebetween, the conductive material strips being elongated in a first direction across the substrate and being spaced apart in a second direction, wherein the first and second directions are orthogonal with each other, etching trenches into the substrate between at least every other one of the conductive strips, said trenches being defined by positions of the conductive strips and having lengths extending in the first direction, thereafter implanting ions along the lengths of the trenches to form elongated sources and drains in said trenches, thereafter separating the strips of conductive material into individual floating gates, thereby forming a two-dimensional array of floating gates, forming a first plurality of elongated gates extending across the array of floating gates in the first direction that extend into the trenches crossed by them, and forming a second plurality of elongated gates.