Patent ID: 6605517
Filing Date: 2003-08-12
Classification: H01L

Abstract:
A method for reducing nitride residue from a silicon wafer during semiconductor fabrication, the wafer including a nitride mask defining active regions and isolation regions wherein the isolation regions are formed by trenches, the method comprising the steps of:(a) performing an optimized oxide deposition process wherein a temperature gradient of a CVD chamber is improved by performing the steps of; (i) placing at least one silicon wafer into the chamber on a quartz boat having a slot size of at least approximately 6 mm, and (ii) centering the quartz boat in approximately a center of the chamber so that at least one wafer is located in a center section of the chamber such that when oxide gas is injected onto the wafer, an oxide layer having a substantially uniform thickness is formed on the wafer; and (b) performing an optimized polishing process on the oxide wherein the oxide is polished down to approximately a level of the nitride, such that more of the oxide is removed from an edge area of the wafer than a center area; and (c) stripping the nitride from the wafer wherein because all of the oxide has been removed, substantially all of the nitride is removed from the thereby minimizing nitride residue.