Patent ID: 7649990
Filing Date: 2010-01-19
Classification: H04L

Abstract:
1. An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word, the apparatus comprising: a plurality of rotational registers coupled to a read bus to receive and store data, one of said rotational registers arranged to receive the input data; data stores coupled to the read bus for initialization of some of said plurality of rotational registers according to whether the SHA-1 or MD5 algorithm is used, said data stores including fixed data relating to SHA-1 and MD5 operation; a plurality of dedicated combinatorial logic circuits having inputs coupled to the read bus and outputs coupled to a write bus and arranged to perform logic operations on data stored in selected ones of said plurality of registers and to output to the write bus; a plurality of temporary data storage registers having inputs coupled to the write bus and outputs coupled to the read bus, an output of one of the temporary data storage registers comprising an output of the apparatus for the fixed length output word; and a control circuit arranged to combine a master clock signal and a control signal and to generate individually gated clock signals only for each active register.