Patent ID: 6775795
Filing Date: 2004-08-10
Classification: G11C

Abstract:
A method for testing a SDRAM memory installed as a main memory in a PC and containing manufacturer defined internal test modes that are implementable in the SDRAM memory, the method which comprises the steps of:a) storing, in machine code, at least one command sequence suitable for activating and carrying out at least one of the internal test modes, in an additional memory being separate from the main memory; b) activating the machine code in the PC and switching-off a cache memory of the PC; c) changing a central processing unit (CPU) in the PC to an UNREAL mode resulting in data segmentation in the main memory being cancelled; d) setting in the PC, predetermined settings of a PC chip set for an activation sequence of an internal test mode; e) selecting a desired test mode of the internal test modes available in the SDPAM memory for analyzing the SDPAM memory on a user-defined basis and making a read access to the additional memory for carrying out the command sequence for activation of the desired test mode; f) activating the desired test mode by a specific sequence of commands and addresses being supplied from a memory controller in the PC to the SDRAM memory in the PC, the specific sequence of commands being controlled by the command sequence stored in the additional memory; and g) recording test results by documenting a number of faults occurring while performing the desired test mode.