Patent ID: 9054122
Filing Date: 2015-06-09
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a first region and a second region; a groove formed in the semiconductor substrate; a first insulating film embedded in the groove; a first MISFET formed in the first region and including a gate electrode; a second insulating film formed over the first and second regions so as to cover the first MISFET; and a first metal pattern and a second metal pattern formed over the second insulating film which is formed over the second region, wherein the first metal pattern comprises one electrode of a first capacitance element, wherein the second metal pattern comprises another electrode of the first capacitance element, wherein a plurality of first conductive patterns is formed over the first insulating film which is formed in the second region, wherein the first conductive patterns are in a same layer as the gate electrode, wherein the first conductive patterns do not function as part of a MISFET, and wherein, in a plan view, each of the first conductive patterns is disposed below the first capacitance element so as not to overlap the first metal pattern and the second metal pattern.