Patent ID: 6563345
Filing Date: 2003-05-13
Classification: H03K

Abstract:
An electronic logic circuit comprising:a dynamic circuit portion and a static circuit portion, each having a first voltage potential connection, a second voltage potential connection, at least one respective logic signal input, a respective clock input, and a respective output node; each circuit portion including an evaluation section switchingly connected between said respective output node and said second voltage potential connection, and a respective pre-charge transistor; each said pre-charge transistor having a respective source, drain, and gate; said pre-charge transistor of said dynamic circuit portion switchingly connecting said first voltage potential connection to said respective output node; said pre-charge transistor of said static circuit portion switchingly connecting said second voltage potential connection to said respective output node; respective gates of said pre-charge transistors being adapted to receive complementary clock signals; said static circuit portion further including a pull-up device operatively connected between said first voltage potential connection and said respective output node; said respective output node of said dynamic circuit portion operatively connected to said logic signal input of said static circuit portion.