Patent ID: 8325512
Filing Date: 2012-12-04
Classification: G11C

Abstract:
1. An SRAM writing system comprising: a dummy replica writing circuit corresponding to at least a dummy replica write bit-line, driving a level transition of the dummy replica write bit-line; a negative pulse controller coupled to the dummy replica write bit-line, generating a negative pulse control signal according to level of the dummy replica write bit-line; and at least a normal writing circuit, each normal writing circuit corresponding to at least a normal write bit-line and comprising: a write driver with a bias node; the write driver connecting the corresponding normal write bit-line to level of the bias node for driving a level transition of the corresponding normal write bit-line; and a negative pulse supplier coupled to the bias node, alternately connecting the bias node to one of an operation voltage and a negative pulse voltage according to level of the negative pulse control signal; wherein the operation voltage and the negative pulse voltage are different.