Patent ID: 6377077
Filing Date: 2002-04-23
Classification: G06F,H03K

Abstract:
A clock supply circuit for supplying clock signals to a data transfer circuit, comprising:a plurality of stages of cascade-connected data signal input/output circuits and wherein said plurality of stages of data signal input/output circuits from a data signal input stage to a data signal output stage are divided into a plurality of groups, each including predetermined stages of said data signal input/output circuits; wherein said clock supply circuit has a plurality of stages of buffers connected in series, said clock supply circuit supplying a clock signal, which is one of a plurality of clock signals derived from any one of said plurality of stages of buffers on the basis of an input clock signal and which is derived via a more number of stages of buffers, to a data signal input/output circuit belonging to a group nearer said data signal input stage of said plurality of stages of data signal input/output circuits out of said plurality of groups; wherein said clock signal is propagated in a reverse direction of the data signal; and wherein said plurality of clock signals have phase differences with respect to each other based on the input clock signal and include a most phase-advanced clock signal and a most phase-lagged signal, and the phase difference between the most phase-advanced clock signal and the most phase-lagged signal is less than one period of said input clock signal.