Patent ID: 7663861
Filing Date: 2010-02-16
Classification: H01G,H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a first insulation film provided on the semiconductor substrate; a capacitance lower electrode provided on the first insulation film; a capacitance insulation film provided on the capacitance lower electrode; a capacitance upper electrode provided on the capacitance insulation film; an interlayer insulation film with its flattened upper surface provided on the first insulation film so as to cover the capacitance lower electrode, the capacitance insulation film and the capacitance upper electrode; a first connection plug embedded in the interlayer insulation film and connected to the capacitance upper electrode; a first wiring layer embedded in the interlayer insulation film and connected to the capacitance lower electrode; a second wiring layer embedded in the interlayer insulation film; a second insulation film provided on the interlayer insulation film; a first opening penetrating through the second insulation film and reaching the first connection plug; a second opening penetrating through the second insulation film and reaching the second wiring layer; and a wiring pull-out portion provided on the second insulation film so as to fill the first and second openings and connect the first connection plug and the second wiring layer to each other, wherein the capacitance lower electrode, the capacitance insulation film and the capacitance upper electrode constitute an MIM capacitance element, and the capacitance upper electrode is electrically connected to the second wiring layer via the first connection plug and the wiring pull-out portion.