Patent ID: 9088399
Filing Date: 2015-07-21
Classification: G01R,H04L

Abstract:
1. A transceiver circuit, comprising: an input terminal and an output terminal; a transmitter circuit having an output coupled to the output terminal, the transmitter including a phase interpolation circuit, a phase locked loop (PLL) circuit, and an emphasis circuit; a receiver circuit having an input coupled to the input terminal; a loopback path configured to provide a signal transmitted by the transmitter circuit on the output terminal to the input of the receiver circuit; and a test control circuit configured and arranged to introduce jitter in the signal transmitted by the transmitter circuit when the test control circuit is operating in a self-test mode but not when the test control circuit is operating in a non-test mode, wherein the test control circuit is configured and arranged to introduce the jitter in the signal by adjusting one or more parameters of each of the phase interpolation circuit, the PLL circuit, and the emphasis circuit.