Patent ID: 6363011
Filing Date: 2002-03-26
Classification: G11C

Abstract:
A bistable non-volatile latch adapted to store a binary data state in a non-volatile manner during a program operation, and to assume one of two stable states in response to a recall operation that corresponds to said data state, comprising:a first circuit having a first node for receiving a first logic input signal, a second node from which a first logic output signal is delivered, a third node for receiving a first supply voltage, and a fourth node for receiving a second supply voltage, including: circuitry for generating said first logic output signal to represent a binary logic state complementary to the binary logic state represented by said first logic input signal; and a first current path including a non-volatile element to set an impedance of said first current path, having a first end connected to said second node; and a second circuit having a fifth node for receiving a second logic input signal, a sixth node from which a second logic output signal is delivered, a seventh node for receiving said first power signal voltage, an eighth node for receiving a third supply voltage, including: circuitry for generating said second logic output signal to represent a binary logic state complementary to the binary logic state represented by said second logic input signal; and a second current path including a non-volatile element to set an impedance of said second current path, having a first end connected to said sixth node; second ends of said first and second current paths being connected to receive signals during said recall operation to cause said latch to assume said one of said two stable states in dependence upon said impedance set by said non-volatile elements; and circuitry for connecting said first and second circuits into a bistable configuration.