Patent ID: 6529438
Filing Date: 2003-03-04
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines each of which is connected to a predetermined number of memory cells in the row direction; a plurality of common electric power sources lines each of which is provided for each predetermined number of rows in order to make connection with the current paths of the memory cells on said each predetermined number of rows in a row direction; a plurality of row selection lines connected respectively to said respective word lines for selecting a row; row address decoders for selecting said row selection lines; and a selection circuit connected between said common electric power source lines and an electric power source respectively and capable of selecting a first group of said common electric power source lines in order to connect the common electric power source line as selected with the electric power source and disconnect the remaining common electric power source lines from the electric power source as a second group of said common electric power source lines in the case that switching to a test mode is indicated by an operation mode switching signal which is used to switch between a normal operation mode and a test mode, and for connecting all of said common electric power source lines with the electric power source in the case that the operation mode switching signal indicates switching to the normal operation mode; wherein said selection circuit is capable of repeating said selection of said common electric power source line(s) between either group of the common electric power source lines having been previously selected until said any one of said common electric power source lines is finally selected in said test mode.