Patent ID: 6501685
Filing Date: 2002-12-31
Classification: G11C,H01L

Abstract:
A channel write/erase flash memory cell comprising:a first well region of a first conductivity type; a second well region of a second conductivity type formed above the first well region; a third well region of the first conductivity type formed above the second well region; a first oxide layer formed on the third well region; a stacked gate formed partially over the first oxide layer; a doping region of the first conductivity type acting as a drain formed next to the stacked gate and under the first oxide layer; a shallow doping region of second conductivity type formed under the stacked gate and next to the doping region of first conductivity type; and a deep doping region of second conductivity type formed underneath the doping region of first conductivity type and being contiguous with the shallow doping region of second conductivity type.