Patent ID: 6209020
Filing Date: 2001-03-27
Classification: G06F

Abstract:
An execution pipeline having a plurality of stages concurrently executing a plurality of processes, the execution pipeline comprising:a first memory cell located within a first stage and coupled to a first register;a second memory cell located within the first stage and coupled to the first register;a first selector located within the first stage and coupled to the first memory cell and the second memory cell, the first selector selecting one of the first memory cell and the second memory cell to provide data input to the first register;a third memory cell located within a second stage and coupled to a second register;a fourth memory cell located within the second stage and coupled to the second register; anda second selector located within the second stage and coupled to the third memory cell and the fourth memory cell, the second selector selecting one of the third memory cell and the fourth memory cell to provide data input to the second register.