Patent ID: 8227711
Filing Date: 2012-07-24
Classification: H01L,H05K,Y10T

Abstract:
1. A coreless packaging substrate, comprising: a substrate body comprising an auxiliary dielectric layer having a first surface and an opposing second surface, an inner wiring disposed on the second surface, and a built-up structure disposed on the second surface and the inner wiring, wherein the built-up structure comprises at least a dielectric layer, a wiring layer disposed on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer to electrically connect to the wiring layer, a portion of the conductive vias electrically connect the wiring layer and the inner wiring, and the outmost wiring layer of the built-up structure has a plurality of conductive pads; and a plurality of conductive bumps comprising metal pillars each having a first end and an opposing second end and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer to electrically connect to the inner wiring, and the first ends of the metal pillars and the solder layer protrude from the first surface of the auxiliary dielectric layer.