Patent ID: 9153584
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A device, comprising: a first channel region formed in a first portion of a substrate, the first channel region being doped with a dopant of a first type of conductivity; a second channel region formed in a second portion of the substrate, the second channel region being doped with a dopant of a second type of conductivity; a gate insulating layer and a dielectric capping layer formed on the first channel region and on the second channel region, the dielectric capping layer comprising a material selected from the group consisting of aluminium oxide, dysprosium oxide, lanthanum oxide, and scandium oxide; a first metal gate region formed to be spaced with regard to the first channel region by the gate insulating layer and the dielectric capping layer; and a second metal gate region formed to be spaced with regard to the second channel region by the gate insulating layer and the dielectric capping layer; wherein one of the first metal gate region and the second metal gate region comprises an ion implantation, the ion implantation comprising at least one material selected from the group consisting of ytterbium and yttrium, wherein one of the first metal gate region and the second metal gate region is free of the ion implantation, wherein the one of the first metal gate region and the second metal gate region which comprises the ion implantation relates to a n-type field effect transistor, and wherein the one of the first metal gate region and the second metal gate region which is free of the ion implantation relates to a p-type field effect transistor.