Patent ID: 6269384
Filing Date: 2001-07-31
Classification: G06F

Abstract:
A processor configured to process data including graphics data, the processor comprising:an instruction cache configured to receive and store instructions,a multiplier configured to receive and execute at least a subset of the instructions from the instruction cache, wherein the multiplier is configured to process the graphics data according to the received instructions, wherein the multiplier is configured to generate a redundant-form product as part of the processing, wherein the multiplier includes:a first path comprising one or more adders, wherein said first path is configured to receive and reduce said redundant-form product to generate a first non-redundant-form product assuming no overflow will occur;a second path comprising one or more adders, wherein said second path is configured to receive and reduce said redundant-form product to generate a second non-redundant-form product assuming an overflow will occur; anda multiplexer coupled to said first path and said second path, wherein said multiplexer is configured to select between said first non-redundant-form product and said second non-redundant-form product,and wherein the processor is configured to output the processed graphics data for display.