Patent ID: 7149265
Filing Date: 2006-12-12
Classification: H04H,H04L

Abstract:
1. A method of regenerating a timing signal from an encoded digital signal having a data clock frequency R b in a receiver using a predetermined sample rate F s , wherein a data clock period 1/R b is not an integer multiple of a predetermined sample period 1/F s , said method comprising the steps of: generating input pulse signals in response to said encoded digital signal; accumulating each of said input pulse signals in a predetermined delay element to store an accumulated value in said predetermined delay element, said predetermined delay element being in a delay loop including N delay elements, each delay element storing a respective accumulated value; circulating said accumulated values within said delay loop by shifting at each of said sample periods according to a predetermined shift sequence, said predetermined shift sequence including a plurality of single shifts and at least one other shift size to provide a number of shifts N+δ during a cycle of N sample periods, where δ is the difference between each different shift size in the cycle and a shift of one; generating a synchronization pulse in response to said accumulated values and a predetermined threshold; operating a counter to output said timing signal in response to said predetermined sample rate F resetting said counter in response to said synchronization pulse.