Patent ID: 6867130
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of polysilicon gate electrodes, each having an upper surface and side surfaces, over an upper surface of a silicon substrate with a gate dielectric layer therebetween, the gate electrodes being spaced apart by a gap therebetween; forming source/drain regions in the upper surface of the substrate on opposite sides of each gale electrode with a channel region therebetween; forming a metal silicide layer, having a first thickness, on the upper surface of the gate electrodes and on the source/drain regions; depositing a first dielectric layer over the substrate filling the gaps and extending above the metal silicide layers on the gate electrodes; etching back the first dielectric layer to selectively expose the metal silicide layers on the upper surface of the gate electrodes and to expose side surfaces of the gate electrodes under the first metal silicide layers, but not the metal silicide layers on the source/drain regions; and increasing the first thickness of the metal silicide layers on the gate electrodes to form second metal silicide layers on the gate electrodes having a second thickness greater than the first thickness by resilicidizing the gate electrodes, thereby forming metal silicide on the exposed side surfaces of the gate electrodes such that the second metal silicide layers are mushroom shaped.