Patent ID: 6804151
Filing Date: 2004-10-12
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device, comprising:a virtual-ground memory array which includes a plurality of word lines and a plurality of bit lines; a row decoder which selectively activates one of said word lines; a column decoder which applies a sense potential to one of said bit lines, and couples all the remaining ones of said bit lines to a ground potential; and a sense amplifier which compares an electric current running through said one of said bit lines with a first reference current and a second reference current so as to sense a data state of two memory cells that are connected to said one of said word lines and share said one of said bit lines, the sensed data state including a first state in which both of the two memory cells are â€œ0â€ , a second state in which both of the two memory cells are â€œ1â€ , and a third state in which one of the two memory cells is â€œ1â€  and another of the two memory cells is â€œ0â€ .