Patent ID: 6054877
Filing Date: 2000-04-25
Classification: H03K

Abstract:
A low power multiplexer apparatus that provides output data signal transitions only for valid input data signals comprising a pass gate multiplexer and latch circuit responsive to a group of n input data signals from at least one data signal source,at least one logic circuit responsive to a first, slow select binary input signal and a second, fast select binary input signal, said at least one logic circuit providing an output gating signal when said first and second binary input signals are present in the same binary state, said pass gate multiplexer and latch circuit including at least one group of n gate devices, each gate device connected to a separate data signal of said group of n input data signals from said at least one data signal source, said n gate devices also connected to said output gating signal of said at least one logic circuit wherein said n gate devices are gated and pass said n data signals in response to an output gating signal from said at least one logic circuit upon the occurrence of said first and second binary input signals being in the same binary state.