Patent ID: 8652968
Filing Date: 2014-02-18
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: sequentially forming a first mask layer and a second mask layer on a target layer; forming first lines on the second mask layer; forming a first planarization layer on the second mask layer to cover the first lines, the first planarization layer having a flat top surface; forming a third mask layer on the first planarization layer; forming second lines on the third mask layer, the second lines crossing over the first lines; etching the third mask layer and the first planarization layer, using the second lines as an etch mask, to form third mask line patterns from the third mask layer and first planarization lines from the first planarization layer, and to partially expose the first lines and the second mask layer; etching the second mask layer using the first and second lines as an etch mask to form a second mask pattern from the second mask layer having a mesh pattern; forming a second planarization layer to cover the second mask pattern, the second planarization layer having a flat top surface; performing a planarization etching process on the second planarization layer to an extent at least to remove the third mask line patterns and form second planarization lines from the second planarization layer between the first planarization lines; removing the first and second planarization lines to expose sidewalls of the first lines and the second mask pattern; etching the first mask layer using the second mask pattern as an etch mask to form a first mask pattern, the first mask pattern having a mesh pattern; and etching the target layer using the first mask pattern as an etch mask to form contact holes.