Patent ID: 8586986
Filing Date: 2013-11-19
Classification: G02F,H01L

Abstract:
1. A pixel structure, comprising: a light-shielding layer, disposed on a substrate; a flat layer, covering the light-shielding layer; a channel layer, disposed on the flat layer and located above the light-shielding layer; a source and a drain, partially covering two sides of the channel layer and electrically connected to the channel layer, respectively; a data line and a first pad, disposed on the flat layer, wherein the data line is connected between the source and the first pad; a gate dielectric layer, covering the channel layer, the source and the data line, and exposing the drain and the first pad; a gate, disposed on the gate dielectric layer and located above the channel layer; a scan line and a second pad, disposed on the gate dielectric layer, wherein the scan line is connected between the gate and the second pad; a patterned protection layer, covering the gate and the scan line, and exposing the drain, the first pad and the second pad, wherein widths of the gate and the scan line are substantially smaller than a width of the protection layer and the patterned protection layer does not in contact with the sidewall of the gate; and a patterned transparent conductive layer, including a pixel electrode, a first retain portion and a second retain portion, the patterned transparent conductive layer being substantially aligned to the patterned protection layer, and not being covered by the patterned protection layer, wherein the pixel electrode is electrically connected to the drain, and the first and second retain portions are located on the first pad and the second pad, respectively.