Patent ID: 7033895
Filing Date: 2006-04-25
Classification: H01L

Abstract:
1. A method of fabricating a metal-oxide semiconductor (MOS) transistor having an elevated source/drain structure, comprising: forming a gate dielectric on an active region of a semiconductor substrate and forming a gate electrode on the gate dielectric; forming a first gate spacer on lateral side surfaces of the gate electrode; following formation of the first gate spacer, forming a first epi-layer on the semiconductor substrate; ion-implanting a dopant in the first epi-laver and in the semiconductor substrate to form a source/drain extension region in the semiconductor substrate after forming the first epi-layer; following formation of the source/drain extension region, forming a second gate spacer on lateral side surfaces of the first gate spacer; following formation of the second gate spacer, forming a second epi-layer on the first epi-layer; and ion implanting a dopant in the second epi-layer, in the first epi-layer and in the semiconductor substrate to form a deep source/drain region below the source drain extension region in the semiconductor substrate after forming the second epi-layer.