Patent ID: 6021075
Filing Date: 2000-02-01
Classification: G11C

Abstract:
A semiconductor memory circuit having shift redundancy circuits comprises:a plurality of memory cell arrays;a redundancy memory cell array to be substituted, when any one of said memory cell arrays is defective, for said defective memory cell array;a plurality of write/read circuits for writing and reading data to and from said memory cell arrays;a redundancy write/read circuit for writing and reading data to and from said redundancy memory cell array;a plurality of shift redundancy circuits each connected to two of said write/read circuits and said redundancy write/read circuit, said shift redundancy circuits allowing one of signals output from said two circuits to pass through;a plurality of fuse elements connected to each other in series, one of said fuse elements being connected between one of said shift redundancy circuits and a power supply potential, and the others of said fuse elements being respectively connected between two of said shift redundancy circuits;a program circuit connected to one of said fuse elements disposed at an end portion opposite to said fuse element connected to said power supply potential, said program circuit selectively outputting a power supply potential or a ground potential; anda plurality of cut fuse detecting circuits for individually detecting whether said fuse elements are cut or not and for controlling each of said write/read circuits and said redundancy write/read circuit in an activated state or an inactivated state, based on a result of the detection.