Patent ID: 6775339
Filing Date: 2004-08-10
Classification: G06F

Abstract:
A system for synchronous communication comprising:a system clock; a capture clock having a first and second phase, wherein the capture clock operates at a frequency at least two times slower than the system clock; a synchronizing clock, wherein the synchronizing clock operates at the same frequency as the capture clock; and a first and a second module, wherein the first module comprises: one or more data output nodes for transmitting data; and a clock output node for transmitting the capture clock signal; and wherein the second module comprises: a plurality of data input nodes for receiving data transmitted by the data output nodes of the first module; a capture clock input node for receiving the capture clock from the clock output node of the first module; and a receive circuit for synchronizing the data with the system clock, wherein the receive circuit comprises: a first memory device connected to a first data input node and operating on the first phase of the capture clock; a second memory device connected to the first data input node and operating on the second phase of the capture clock; and a multiplexor connected to the first and second memory devices, wherein the multiplexor selects between the first and second memory devices as a function of the synchronizing clock.