Patent ID: 6518670
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A semiconductor device including interconnected conductor lines comprising:a plurality of lower conductor lines formed on a lower level each having a top surface, a plurality of resistive studs having sidewalls, lower ends and upper ends, each resistive stud being formed over the top surface of a lower conductor line in electrical and mechanical contact therewith at the lower end thereof, a plurality of intermediate conductor lines formed laterally between the resistive studs, with each intermediate conductor line being separated from each adjacent stud by a capacitor dielectric layer, a plurality of the upper conductor lines formed on an upper level each having a lower surface in contact with the upper end of a corresponding one of the resistive studs, and dielectric material formed about the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the lower conductor lines and the upper conductor lines.