Patent ID: 6223282
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A circuit for controlling execution of a loop in a digital signal processing chip, wherein a counter register stores a number of loop executions of the loop to be executed, the circuit comprising:a least significant bit state detection unit to output an effective signal of a predetermined level according to a state of a least significant bit of the counter register and a state of a first or second signal, wherein said least significant bit state detection unitdetects the state of each bit in the counter register to which the number of loop executions is loaded, andoutputs the effective signal according to the state of the first or second signal when every bit other than the least significant bit is zero as a result of detecting the state of each bit in the counter register to which the number of loop executions is loaded;a conditional clock output unit toreceive a clock signal and the first and second signals, andoutput the clock signal when the first or second signal is effective; andan ending condition signal output unit to output the effective signal from said least significant bit state detection unit when the clock signal output from said conditional clock output unit is effective.