Patent ID: 6323702
Filing Date: 2001-11-27
Classification: B29C,B29L,Y10S,Y10T

Abstract:
A signal line drive circuit, comprising:a primary signal line that extends continuously from a first end to a second end thereof and provides a first series resistive path between the first and second ends that is not interrupted by an active electronic device;a first driver having a first input and a first output, the first input receiving an input signal;a second driver having a second input connected to the first output of said first driver and a second output connected to the first end of said primary signal line;a third driver having a third input and a third output, the third output being connected to said primary signal line at an intermediate point between the first and second ends; anda secondary signal line that extends from the first output of said first driver to the third input of said third driver and provides a second series resistive path therebetween that is not interrupted by an active electronic device; andwherein a total RC delay time constant associated with said secondary signal line is smaller than a total RC delay time constant associated with a first portion of said primary signal line that extends from the first end to the intermediate point;wherein the second input of said second driver is electrically connected to the first output of said first driver by said secondary signal line;wherein said second driver and said third driver each have one inverter therein or have an equal number of inverters therein; andwherein a pull-up signal provided by said third driver arrives earlier at the intermediate point than a pull-up signal provided by said second driver during a pull-up time interval when said primary signal line is being driven from a logic 0 potential to a logic 1 potential by both said second and third drivers.