Patent ID: 8004042
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A static random access memory (SRAM) cell comprising: a first pull-down transistor; a first pull-up transistor; a first pass-gate transistor; a second pull-down transistor; a second pull-up transistor; a second pass-gate transistor, wherein active areas of the transistors are disposed in a substrate, and wherein longitudinal axes of the active areas of the transistors are all parallel; a first linear intra-cell connection electrically coupling the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor, wherein all outer edges of a first top surface of the first linear intra-cell connection form one first rectangle of the first top surface, the first top surface being parallel to a substrate top surface, wherein a longitudinal axis of the first top surface aligns with the gate electrode of the second pull-down transistor and the gate electrode of the second pull-up transistor; and a second linear intra-cell connection electrically coupling the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor, wherein all outer edges of a second top surface of the second linear intra-cell connection form one second rectangle of the second top surface, the second top surface being parallel with the substrate top surface, wherein a longitudinal axis of the second top surface aligns with the gate electrode of the first pull-down transistor and the gate electrode of the first pull-up transistor.