Patent ID: 8647954
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A method for forming a semiconductor device, the method comprising the steps of: providing a transistor comprising a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region; depositing a metal layer over both the source/drain region and a portion of the extension region which is not covered by the dielectric spacer such that metal from the metal layer diffuses into the source/drain region and the portion of the extension region to form, without a thermal anneal, a silicide intermix layer having a thickness no greater than 3 nm; removing metal, from the metal layer, that has not diffused into the source/drain region and the portion of the extension region; depositing dielectric material over the silicide intermix layer on top of the source/drain region; creating a contact opening through the dielectric material, wherein the contact opening extends at least as far as the silicide intermix layer over the source/drain region; and forming a silicide contact at the bottom of the contact opening.