Patent ID: 6734058
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising the steps of:forming an insulating layer and a nitride layer sequentially on a semiconductor substrate; selectively removing said insulating layer and said nitride layer, to form a first contact; forming a silicon layer on the structure including the first contact hole, the silicon layer is formed by epitaxial growth manner; forming a trench through selective removal of said silicon layer; forming a source region in said semiconductor substrate and a drain region on an upper part of said silicon layer, after the removal of the nitride layer; forming a gate oxide layer and gate sequentially at the side walls of the trench; forming a planarization layer on the resultant structure to fill the trench; forming a second contact hole that exposes said gate, said drain region, and said source region by selective patterning the resultant structure; and forming plugs in said exposed second contact hole.