Patent ID: 8673731
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method of fabricating a complementary metal-oxide semiconductor (CMOS) device, comprising the steps of: providing a semiconductor-on-insulator (SOI) wafer comprising a SOI layer over a buried oxide (BOX); forming active areas in the SOI layer in which field-effect transistor (FET) devices will be formed; forming a patterned dielectric on the wafer having trenches therein present over the active areas in which gate stacks for the FET devices will be formed, wherein at least a first given one of the gate stacks having at least one first length and corresponding to at least a first given one of the FET devices will be formed in at least a first given one of the trenches and at least a second given one of the gate stacks having at least one second length and corresponding to at least a second given one of the FET devices will be formed in at least a second given one of the trenches, and wherein portions of the SOI layer are exposed at a bottom of each of the trenches; forming an interfacial oxide on the portions of the SOI layer exposed at the bottom of each of the trenches; and into each of the trenches, (i) depositing a conformal gate dielectric layer so as to line the trenches, wherein the conformal gate dielectric layer deposited into each of the trenches comprises a high-k dielectric material (ii) depositing a conformal gate metal layer on the conformal gate dielectric layer, and (iii) depositing a conformal workfunction setting metal layer, that is configured to act as a doping source to change a workfunction of the gate stacks, on the conformal gate metal layer to form the gate stacks of the FET devices, wherein one or more of an amount of the conformal gate metal layer and an amount of the conformal workfunction setting metal layer deposited into a given one of the trenches varies proportionally to a length of the gate stacks since the trenches provide, based on the length of the gate stacks, different size gaps for the conformal gate metal layer and the conformal workfunction setting metal layer to fill in, and wherein variations in the amount of the conformal workfunction setting metal layer in the gate stacks alters a threshold voltage of the FET devices, and thus by having the gate stacks with the at least one first length and the at least one second length the amount of the conformal workfunction setting metal layer is varied by having the different size gaps for the conformal workfunction setting metal layer to fill in as a function of the length of the gate stacks so as to configure the at least a first given one of the FET devices to have a threshold voltage that is different from a threshold voltage of the at least a second given one of the FET devices.