Patent ID: 7376017
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. A flash memory device comprising: a memory cell array having memory cells arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage during a program operation; and a row selector circuit that receives the program voltage, the dielectric breakdown prevention voltage, and the pass voltage and selects one of the rows in response to a row address, wherein the dielectric breakdown prevention voltage is lower than the program voltage and higher than the pass voltage; and the row selector circuit drives the selected row with the program voltage, drives at least one row adjacent the selected row with the dielectric breakdown prevention voltage and drives remaining rows with the pass voltage, and wherein, during a first time period of the program operation, before a second time period when the program voltage is applied to the selected row, one of the dielectric breakdown prevention voltage and the pass voltage is applied to the selected row.