Patent ID: 6574147
Filing Date: 2003-06-03
Classification: G11C

Abstract:
A method for controlling programming of an electrically erasable and programmable nonvolatile memory having a plurality of memory cells, row and column decoders, an address buffer, and a bit line controller including a sense/latch circuit and a data I/O buffer, the method comprising:supplying address signals to said address buffer to define at least one selected memory cell in said plurality of memory cells; supplying to said bit line controller programming data which corresponds to write data to be written in said selected memory cell; latching the programming data in the sense/latch circuit; writing the write data into the selected memory cell based on the programming data stored in the sense/latch circuit; reading the written data of said selected memory cell by resetting the sense/latch circuit to be operated as a sense circuit, the latched data being kept latched by a capacitance of the bit line and verifying whether or not the data is successfully written based on a threshold voltage of the selected memory cell; performing a logic operation with respect to the read data and said programming data latched in the sense/latch circuit to determine if the selected memory cell is insufficiently written or successfully written; if an insufficiently written memory cell is found, maintaining the programming data stored in the sense/latch circuit and if a sufficiently written memory cell is found, modifying the programming data stored in the sense/latch circuit; and rewriting the write data into the selected memory cell by performing the writing step by a predetermined number of times.