Patent ID: 7202726
Filing Date: 2007-04-10
Classification: H03H,H03K,H03L

Abstract:
1. An apparatus comprising: (a) a first transistor comprising a gate, a source, and a drain; (b) a second transistor comprising a gate, a source, and a drain, wherein said drain of said second transistor is electrically shorted to said source of said second transistor, and wherein said drain of said first transistor is electrically connected to said drain of said second transistor; (c) a third transistor comprising a gate, a source, and a drain, wherein said source of said third transistor is electrically shorted to said drain of said third transistor, and wherein said gate of said third transistor is electrically connected to said gate of said second transistor; (d) a fourth transistor comprising a gate, a source, and a drain; (e) a fifth transistor comprising a gate, a source, and a drain, wherein said source of said fifth transistor is electrically connected to said source of said second transistor, and wherein said drain of said fifth transistor is electrically connected to a first power supply terminal; and (f) a resistor comprising a first terminal and a second terminal, wherein said first terminal of said resistor is electrically connected to said gate of said fifth transistor, and wherein said second terminal of said resistor is connected to a second power supply terminal; wherein said drain of said fourth transistor is electrically connected to said drain of said third transistor; and wherein said source of said fourth transistor is electrically connected to said source of said first transistor.