Patent ID: 6611570
Filing Date: 2003-08-26
Classification: H03C,H03D,H04B

Abstract:
A CMOS programmable digital intermediate frequency receiver, comprising:a programmable memory receiving and storing a first value representative of a programmable parameter k and a second value representative of programmable parameter N; a clock generator coupled to the programmable memory, the clock generator generating a first clock signal having a first frequency, fl, a second clock signal having a second frequency approximately equal to fl/k, and a third clock signal having a third frequency approximately equal to fl/N; a sigma delta converter sampling an analog input signal having an intermediate frequency using the first clock signal to generate a first set of digital signals; a digital downconverter mixing down the first set of digital signals using the second clock signal to generate a second set of digital signals; and a decimation filter network filtering the second set of digital signals using the third clock signal to generate a third set of digital signals.