Patent ID: 7589367
Filing Date: 2009-09-15
Classification: G11C,H01L

Abstract:
1. A line layout structure in a semiconductor memory device having a collection of signal lines comprising a global word line, a local word line, a global bit line, and a local bit line, wherein all of the signal lines in the collection of signal lines are disposed as conductive layers among at least three conductive layers, wherein two signal lines selected from the collection of signal lines are together disposed in parallel at one of the conductive layers, and two signal lines other than the two signal lines selected from the collection of signal lines are disposed in parallel at different conductive layers other than the one conductive layer; and the global word line and global bit line are arranged orthogonal to one another, wherein a memory cell of the semiconductor memory device includes a diode formed on an active region, and a variable resistant element connected to the diode the local bit line is disposed at a first conductive layer as a lowermost layer among the conductive layers, extends lengthwise in a first direction, and is coupled with the variable resistant element of the memory cell, the local word line is disposed at a second conductive layer among the conductive layers above the first conductive layer, extends lengthwise in a second direction orthogonal to the first direction, and is coupled with the active region, the global word line is disposed at the second conductive layer, and extends in parallel with and spaced apart from the local word line, and the global bit line is disposed at a third conductive layer among the conductive layers above the second conductive layer, and extends lengthwise in the first direction.