Patent ID: 9053799
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. An integrated circuit comprising: a plurality of memory wrappers, each memory wrapper comprising a memory block with a fuse register and a bypass register, the bypass register having a bypass data that is configured to indicate a defective memory wrapper of the plurality of memory wrappers; a fuseROM controller coupled to the plurality of memory wrappers; a memory bypass chain configured to link the bypass registers in the plurality of memory wrappers with the fuseROM controller, wherein the fuseROM controller is configured to load the bypass data in the memory bypass chain; and a memory data chain configured to link the fuse registers in the plurality of memory wrappers with the fuseROM controller, wherein the memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.