Patent ID: 7208378
Filing Date: 2007-04-24
Classification: H01L,Y10S

Abstract:
1. A method for manufacturing a semiconductor device, comprising: defining a first voltage region, a second voltage region, and a third voltage region on a substrate, the first, second, and third voltage regions being configured to handle first, second, and third voltage levels, respectively, that are different from each other; forming a first insulation layer overlying the first, second, and third voltage regions; forming a second insulation layer overlying the first insulation layer; patterning the second insulation layer to expose a portion of the second insulation layer overlying the first voltage region; removing the exposed portion of the first insulation layer using a wet etch process; forming a first gate dielectric layer overlying the first voltage region; removing portions of the second insulation layer and the first insulation layer overlying the second and third voltage regions; selectively implanting impurities into the third voltage region while preventing the impurities from being provided in the second voltage region; and forming a second gate dielectric layer overlying the second voltage region and a third gate dielectric layer overlying the third voltage region simultaneously, the second gate dielectric layer being thicker than the third gate dielectric layer.