Patent ID: 8879347
Filing Date: 2014-11-04
Classification: G11C

Abstract:
1. A flash memory device, comprising: a flash memory, having a voltage source pin and a first ready/busy pin, wherein the voltage source pin is coupled to a voltage source; a controller, having a second read/busy pin, wherein the second ready/busy pin is coupled to the first ready/busy pin, and when the flash memory processes a first write command, the flash memory sets the voltage of the first ready/busy pin to be equal to a specific level; and a power failure handling circuit, coupled between the voltage source and the second ready/busy pin, detecting whether the level of the voltage source has been kept at a predetermined level, and setting the level of the second ready/busy pin to be the specific level to prevent the controller from sending a second write command to the flash memory when the level of the voltage source is lower than the predetermined level.