Patent ID: 6436754
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of forming MOSFET semiconductor devices on a semiconductor substrate using a selective salicide process for application in the fabrication of CMOS, complementary MOS transistors, comprising:forming a semiconductor silicon substrata having field oxide regions for MOSPZT device isolation; forming for gate oxide and polysilicon late structures on both n-channel and p-channel devices; thermally oxidizing said polysilicon gate structures to form silicon oxide on polysilicon gate structures; depositing a first conformal silicon nitride layer over said substrate; masking and anisotropically reactive ion etching (RIE) said silicon nitride layer to form gate sidewall spacers on said polysilicon gate structures; patterning source/drain regions whereby said polysilicon gates are self-aligned; forming by implantation source/drain regions associated with said polysilicon gate and sidewall spacer structures; removing said silicon nitride sidewall spacers; depositing a second conformal silicon nitride layer over said substrate; forming a salicide blockout mask over memory devices, while exposing logic FET devices using said second conformal silicon nitride layer; etching anisotropically said second silicon nitride to form second sidewall spacers on said logic devices; removing said salicide blockout mask; applying a salicide process of metal deposition and forming self-aligned silicide structures on exposed said logic FET devices, whereby there is formed low resistance lines and contacts on polysilicon gates and source/drain regions, while silicide formation is blocked on memory FET devices, by said second silicon nitride layer.