Patent ID: 8194532
Filing Date: 2012-06-05
Classification: G06F,H04L

Abstract:
1. A circuit for performing mixed-radix discrete Fourier transform on a frame of size N, comprising: a fast Fourier transform processor block; a memory block having an input coupled to an output of the fast Fourier transform processor block by means of a first circuit path, and an output coupled to an input of the fast Fourier transform processor block; and a radix-2 butterfly circuit having first and second inputs coupled to the memory block by means of respective second and third circuit paths, and first and second outputs coupled to the memory block; wherein the memory block and fast Fourier transform processor block are configured to wherein the radix-2 butterfly circuit is configured to perform radix-2 summation of two of the sub-transforms concurrently with fast Fourier transform of one of the sub-frames.