Patent ID: 6798013
Filing Date: 2004-09-28
Classification: G11C,H01L

Abstract:
A memory cell having a vertically integrated transistor comprising:a substrate having a trench and comprising each of a first and second doped region located at the surface of the substrate and being coincident with the top of the trench; each of a first and second sidewall spacer disposed within the trench such that each of the first and second sidewall spacers is coincident to the bottom of the trench and one of the first and second doped regions; a first oxide layer disposed within the trench and arranged to provide a barrier between each of the spacers and each of the doped regions and such that a portion of the first oxide layer covers the bottom of the trench; and a second oxide layer disposed within the trench such that each of the first and second sidewall spacers and the portion of the first oxide layer covering the bottom of the trench is covered by the second oxide layer.