Patent ID: 6489804
Filing Date: 2002-12-03
Classification: H03K

Abstract:
A method for coupling logic blocks, said method comprising:providing a first logic block, said first logic block comprising a first low voltage device comprised of low threshold transistors; providing a second logic block, said second logic block comprising a second low voltage device comprised of low threshold transistors, wherein; said low threshold transistors comprising said first and second devices have an unbiased threshold voltage with a magnitude of less than 300 millivolts; supplying a first supply voltage to said first and second logic blocks; supplying a second supply voltage to said first and second logic blocks, wherein; a voltage differential between said first supply voltage and said second supply voltage is less than about 400 millivolts; providing a transmission unit, said transmission unit comprising: a low threshold NFET pass transistor coupled between said first logic block and said second logic block; and a low threshold PFET pass transistor coupled between said first logic block and said second logic block, in parallel with said low threshold NFET pass transistor; supplying a third supply voltage to a gate of said low threshold NFET pass transistor to overdrive said low threshold NFET pass transistor, wherein; said third supply voltage is less than 2.0 volts when said low threshold NFET pass transistor is overdriven on, further wherein; said third supply voltage is greater than âˆ’500 millivolts when said low threshold NFET pass transistor is overdriven off; and supplying a fourth supply voltage to a gate of said low threshold PFET pass transistor to overdrive said low threshold PFET pass transistor, wherein; said fourth supply voltage is greater than âˆ’2.0 volts when said low threshold PFET pass transistor is overdriven on, further wherein; said fourth supply voltage is less than 500 millivolts when said low threshold PFET pass transistor is overdriven off.