Patent ID: 7620821
Filing Date: 2009-11-17
Classification: G06F

Abstract:
1. A processor, comprising: instruction execution logic configured to execute instructions specified by a user of the processor, wherein the instructions are compliant with a general-purpose instruction set architecture; and a cryptographic functional unit configured to implement a plurality of cryptographic operations, and further configured to process said cryptographic operations independently of said instruction execution logic, wherein said cryptographic operations include a block cipher operation configured to operate on cipher state, wherein the cipher state includes a plurality of rows and a plurality of columns; wherein at least some particular ones of said cryptographic operations correspondingly represent fundamental units of work, wherein each fundamental unit of work is capable of being individually scheduled for processing by said cryptographic functional unit, such that to implement a given cryptographic algorithm that is supported by said processor, said cryptographic functional unit is configured to schedule multiple ones of said cryptographic operations for processing; wherein to process said block cipher operation, said cryptographic functional unit is configured to perform said block cipher operation on said cipher state, wherein a maximum number of columns that said cryptographic functional unit is operable to concurrently process is fewer than all of said columns of said cipher state, such that said cryptographic functional unit is operable to process said cipher state in portions over multiple distinct cycles of operation; wherein a subset of said instructions are executable to cause individual ones of said particular cryptographic operations, including said block cipher operation, to be processed by said cryptographic functional unit, such that said individual ones of said particular cryptographic operations are each capable of being separately invoked by said user via said instructions.