Patent ID: 6088829
Filing Date: 2000-07-11
Classification: G06F

Abstract:
A synchronous data transfer system, comprising:a first node for storing data; anda second node for controlling said first node,wherein said second node and said first node are connected to an address buffer, a command bus, a control bus, a clock bus and a data bus, respectively;wherein said first node includes at least one address buffer and at least one synchronous memory;wherein at least one of said address buffers incorporates a phase-locked loop circuit;wherein said address bus, said command bus, said control bus and said clock bus are connected to said synchronous memory by way of a logic circuit provided at least in said address buffer of said first node;wherein said data bus is connected from said second node directly to said synchronous memory;wherein said synchronous memory includes redundant code generating means for generating an error checking and correction code; andwherein said synchronous memory responds to reception of a read command from said address bus, said command bus and said control bus to thereby output the error checking and correction redundant code generated by said redundant code generating means after having outputted the data read out.