Patent ID: 8893100
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. A method of optimizing return address translation in a dynamic code translator comprising: receiving a function call from subject code designed for a first machine having a first hardware environment; compiling an isoblock including at least target code and compatibility information wherein the target code is designed for a second machine having a second hardware environment which is different from the first hardware environment and the target code includes a subfunction corresponding to the function call; planting in the target code a trampoline instruction set having a plurality of branch instructions which return a true subject return address conditioned on an isostate of the isoblock stored in an isostate register; and inserting in the target code instructions which write an address of the trampoline instruction set to a target return address stack of the second machine, instructions which write an address from the subject code directly following the function call to a subject return address register, and instructions which write the isostate of the isoblock to the isostate register when a computed subject return address matches an entry in the subject return address register.