Patent ID: 6925621
Filing Date: 2005-08-02
Classification: G06F

Abstract:
1. A circuit design system, comprising: a network coupled to a plurality of data storage devices, the data storage devices containing a knowledge base that defines an integrated circuit design; a computer coupled to the network, the computer including logic for receiving information defining an integrated circuit representation from the plurality of data storage devices; and a memory element associated with the computer, the memory element configured to store logic, the logic configured to generate one or more static-timing scripts that reflect a plurality of timing models responsive to one or more sentry registers inserted along conductors that traverse a boundary of a functional block within the circuit design and the expected signal timing behavior of a signal that traverses the conductor, the logic further configured to generate a static timing run script and structured timing data, wherein the static timing scripts, the static timing run script, and the structured timing data are forwarded to a static timing engine for execution.