Patent ID: 8084316
Filing Date: 2011-12-27
Classification: H01L

Abstract:
1. A method of fabricating a single transistor floating-body DRAM device, comprising: forming a body layer on a semiconductor substrate having a buried insulating layer therein, the buried insulating layer being buried beneath the body layer and disposed between the body layer and the semiconductor substrate; forming a source region by implanting impurity ions of a first conductivity type into a lower region of the body layer; implanting impurity ions of a second conductivity type into a region of the body layer disposed on the source region, the second conductivity type being different from the first conductivity type; forming a drain region by implanting impurity ions of the first conductivity type into an upper region of the body layer; forming a body layer pattern by patterning the body layer having the source and drain regions such that the buried insulating layer is exposed; forming first and second floating bodies by patterning the body layer pattern; forming a gate insulating layer on sidewalls of the first and second floating bodies and on a top surface of the source region, the gate insulating layer being spaced apart from the buried insulating layer; and forming a gate electrode between the first and second floating bodies, such that the gate insulating layer surrounds both sidewalls and a bottom surface of the gate electrode.