Patent ID: 7259067
Filing Date: 2007-08-21
Classification: H01L

Abstract:
1. A method for manufacturing a flash memory device, comprising: forming a tunnel oxide layer and a first conductive layer on a semiconductor substrate and then performing a shallow trench isolation process to form an isolation structure that defines a first region and a second region; forming a second conductive layer on the entire structure and then patterning the second conductive layer and the first conductive layer to form a floating gate pattern; forming a dielectric layer, a third conductive layer, a fourth conductive layer and a hard mask layer on the entire structure and then patterning the hard mask layer; and forming a control gate and a floating gate by performing an etching process from the fourth conductive layer to the first conductive layer in a single etch apparatus using the hard mask layer as a mask; wherein the etching process comprises the steps of: