Patent ID: 6083793
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method to fabricate nonvolatile memory, the method comprising the steps of:forming a pad oxide on a substrate;forming a pad nitride on said pad oxide;forming a lightly doping drain (LDD) in said substrate;etching back said pad nitride, said pad oxide and said substrate to form a trench;forming a nitride layer on said pad nitride to fill into the trench;etching back said nitride layer to form spacers on sidewalls of the trench;etching back said substrate to form a subtrench in the trench;depositing a polysilicon layer to refill said trench region and cover on a surface of said nitride layer;etching back said polysilicon to remove said polysilicon layer on a surface of said nitride to form a pillar;removing said pad nitride and said nitride;removing said pad oxide;forming a tunnel oxide to cover said pillar, said trench region and said substrate;forming a floating gate that is in the trench region and is extended to the top of the trench;forming an inter-poly oxide on said floating gate;forming a control gate on said inter-poly oxide;forming spacers of said floating gate said inter-poly oxide and said control gate;forming source/drain regions in said substrate;depositing an oxide on the surface of the substrate; andforming a metal contact on said source/drain region.