Patent ID: 6035366
Filing Date: 2000-03-07
Classification: G06F

Abstract:
A computer architecture comprising:a plurality of computer components;a packet switch bank; anda plurality of packet interfaces, each packet interface connecting a corresponding one of the computer components to the packet switch bank,wherein the computer components communicate via the packet switch bank through the plurality of packet interfaces,wherein the packet switch bank comprises a plurality of packet switches and a packet switch controller connected to each of the plurality of packet switches, wherein the packet switch controller controls each packet switch to be coupled to specific ones of the computer components at respective predetermined times during a fixed time frame,wherein the packet switch bank further comprises a plurality of queues between the packet switches and the computer components, andwherein each queue is affiliated with a corresponding packet switch, such that the packet switch controller allocates queues affiliated with a given packet switch to interfaces between the given packet switch and the specific ones of the computer components coupled to the given packet switch.