Patent ID: 8159069
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A method for forming a metal line structure of a semiconductor device, comprising the steps of: forming a lower metal line on a semiconductor substrate; forming an insulation layer having a metal line forming region on the resultant semiconductor substrate, wherein the metal line forming region exposes at least a portion of the lower metal line; forming a WN forming a wetting layer on the W—N—B ternary layer, the wetting layer comprising one of a Ti layer and a TiN layer; annealing the resultant semiconductor substrate which is formed with the wetting layer, such that a Ti—N—B ternary layer is formed by transforming a lower portion of the wetting layer, wherein the Ti—N—B ternary layer, the WN forming an upper metal line on the wetting layer to fill the metal line forming region.