Patent ID: 7234036
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A method for operating a non-volatile memory system that includes a NAND flash memory array having a plurality of physical blocks, each physical block comprised of a plurality of memory cells arranged in a plurality of pages, each memory cell capable of storing more than one bit of data, so that partial writes of pages in the physical blocks are not allowed, the method comprising the steps of: associating a first physical block in the flash memory array with a logical block; writing data associated with the logical block, and a first update index value, to at least one page in the first physical block; then associating a second physical block with the logical block; and writing data associated with the logical block, and a second update index value, to at least one page in the second physical block, the second update index value indicating that the second physical block is more newly associated with the logical block than is the first physical block.