Patent ID: 9170776
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A method performed by a vector-based digital signal processor for evaluating a non-linear logarithm function for an input vector, x, said method comprising: obtaining one or more logarithm software instructions that implement said non-linear logarithm function; in response to at least one of said obtained logarithm software instructions, invoking at least one hardware functional unit that implements said one or more logarithm software instructions to perform the following steps in hardware for each component of said input vector, x, to produce a corresponding component of an output vector, wherein said input vector, x, comprises a plurality of said components and wherein said vector-based digital signal processor processes said plurality of components substantially simultaneously: decomposing each component of said input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in said input vector, x; obtaining a value from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor based on said second part, q; computing an epsilon term, E, using the expression evaluating an expression Log: (1+ε) using a polynomial approximation; and determining said logarithm function for said input vector, x, by summing said values of N, and Log 2 (1+ε) to produce said corresponding component of said output vector, wherein a predefined software instruction keyword for said non-linear logarithm function is part of an instruction set of said vector-based digital signal processor.