Patent ID: 6677630
Filing Date: 2004-01-13
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a first semiconductor region formed in a surface region of a semiconductor substrate; a second semiconductor region formed separately from said first semiconductor region in said surface region of said semiconductor substrate; a gate insulating film formed on a portion of said semiconductor substrate which is arranged between said first and second semiconductor regions; a gate electrode formed on said gate insulating film; an interlayer insulating film formed on said semiconductor substrate to cover said first semiconductor region, second semiconductor region and gate electrode; first and second lower electrodes formed on said interlayer insulating film; a first contact plug formed in said interlayer insulating film and in contact with said first lower electrode, said first contact plug being electrically connected to said first semiconductor region; a second contact plug formed separately from said first contact plug and in contact with said second lower electrode in said interlayer insulating film, said second contact plug being electrically connected to said first semiconductor region; a first ferroelectric film formed on said first lower electrode; a first upper electrode formed on said first ferroelectric film; a second ferroelectric film formed on said second lower electrode; and a second upper electrode formed on said second ferroelectric film.