Patent ID: 8760928
Filing Date: 2014-06-24
Classification: G11C,H01L

Abstract:
1. A memory comprising: a plurality of sensing nodes and reference nodes; a plurality of strings of memory cells, each string in the plurality being arranged for connection between a corresponding sensing node and a corresponding reference node in the plurality of sensing nodes and reference nodes, and including a string select switch to selectively connect the string to the corresponding sensing node and a ground select switch to selectively connect the string to the corresponding reference node; a plurality of word lines, at least one string select line and a ground select line, word lines in the plurality of word lines coupled to corresponding memory cells in the plurality of strings, the at least one string select line coupled to corresponding string select switches in the plurality of strings and the ground select line coupled to corresponding ground select switches in the plurality of strings; and logic and circuitry coupled to the plurality of word lines to apply a bias arrangement including: