Patent ID: 6762453
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A programmable memory transistor comprising:a semiconductor substrate; an insulated gate field effect transistor on the substrate, the insulated gate field effect transistor comprising a source region in a surface of the substrate, a drain region in the surface of the substrate, a channel in the surface of the substrate and between the source and drain regions, a gate insulator overlying the channel, and a first floating gate on the gate insulator; a capacitor structure on the substrate, the capacitor structure comprising a lightly-doped well of a first conductivity type in the surface of the substrate, a heavily-doped contact diffusion of the first conductivity type in the lightly-doped well, an injecting diffusion of a second conductivity type in the lightly-doped well and spaced apart from the contact diffusion so as to define therebetween a surface region of the lightly-doped well, a control gate insulator overlying the surface region of the lightly-doped well, a second floating gate on the control gate insulator, and a conductor in ohmic contact with the lightly-doped well through the contact diffusion and in further contact with the lightly-doped well through the injecting diffusion; and means for electrically connecting the first and second floating gates to maintain the first and second floating gates at the same potential; wherein the second floating gate is capacitively coupled to the lightly-doped well through the control gate insulator so as to define a control gate for the first floating gate whereby a sufficient voltage can be applied to the lightly-doped well to cause ejection of electrons from the source region of the insulated gate field effect transistor and trapping some of the ejected electrons in the first floating gate.