Patent ID: 9196736
Filing Date: 2015-11-24
Classification: G02F,H01L

Abstract:
1. An array substrate, comprising a plurality of pixel regions arranged in a two-dimensional matrix, gate lines extending along a row direction of the two-dimensional matrix and data lines extending along a column direction of the two-dimensional matrix, each pixel region including a pixel electrode, wherein the array substrate further comprises at least one common electrode line, and the common electrode line is disposed to be parallel to the data lines, wherein each common electrode line is disposed between two adjacent columns of pixel regions, wherein each common electrode line does not overlap with the pixel electrode, and wherein each pixel region further comprises a thin film transistor as a switching element, the thin film transistor including a gate electrode, a source electrode and a drain electrode, the gate electrode is connected to a corresponding gate line, the source electrode is connected to a corresponding data line, and the drain electrode is connected to the pixel electrode; and the common electrode line is formed in the same layer as that of the data lines and the source/drain electrodes.