Patent ID: 8842549
Filing Date: 2014-09-23
Classification: H04L,H04W

Abstract:
1. An apparatus including circuitry for facilitating testing of multiple data packet signal transceivers, comprising: signal routing circuitry responsive to an incoming data packet signal and one or more control signals by providing a plurality of outgoing data packet signals for a plurality of data packet signal transceivers, wherein each one of said plurality of outgoing data packet signals corresponds to said incoming data packet signal and includes one or more sequential data packets with a data packet signal characteristic; confirmation signal detection circuitry responsive to successful and unsuccessful receptions of respective ones of a plurality of confirmation signals from said plurality of data packet signal transceivers by providing one or more status signals indicative of said successful and unsuccessful confirmation signal receptions, wherein each one of said plurality of confirmation signals is indicative of a successful reception of a valid data packet by a corresponding one of said plurality of data packet signal transceivers; and control circuitry coupled to said signal routing circuitry and said confirmation signal detection circuitry, and responsive to said one or more status signals by providing said one or more control signals, wherein