Patent ID: 6437443
Filing Date: 2002-08-20
Classification: H01L,Y10T

Abstract:
An electronic structure having layers of insulating material as intralevel or interlevel dielectrics in a wiring structure comprising:a pre-processed semiconducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which formed of a multiphase material, said multiphase material comprises a first phase consisting essentially of Si, C, O and H, and at least a second phase dispersed in said first phase, said at least a second phase consisting essentially of C, H and a multiplicity of nanometer-sized pores, said multiphase material having a dielectric constant of not more than 3.2, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, and a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material comprising said multiphase material, said third layer of insulating material being in intimate contact with said second layer of insulating material.