Patent ID: 6404064
Filing Date: 2002-06-11
Classification: H01L,H05K,Y02P

Abstract:
A flip-chip bonding structure on a substrate for flip-chip application, which comprises:a solder mask having an opening shaped with an opposite pair of parallel straight edges including a first straight edge and a second straight edge; the location of the solder mask opening being subjected to deviation within a statistically-determined maximum positional deviation; and an electrically-conductive layer which is predefined to have an exposed portion uncovered by the solder mask to serve as solder-bump pad and a pair of oppositely-adjoined unexposed portions including a first unexposed portion and a second unexposed portion covered by the solder mask to serve as electrically-conductive traces; wherein, the solder-bump pad includes: a first exposed parallelogram area adjoining the first straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; a second exposed parallelogram area adjoining the second straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; and an intermediate area between the first exposed parallelogram area and the second exposed parallelogram area; and wherein the electrically-conductive traces include: a first unexposed parallelogram area contiguous to the first exposed parallelogram area and adjoining the first straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask; and a second unexposed parallelogram area contiguous to the second exposed parallelogram area and adjoining the second straight edge of the solder mask opening, with an extent within the maximum positional deviation of the solder mask.