Patent ID: 7517736
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A method of forming a semiconductor interconnect structure comprising: providing a structure comprising a lower interlevel dielectric having at least one metal line embedded therein, a first dielectric cap having an opening exposing a surface of the at least one metal line located on said lower interlevel dielectric, and an upper interlevel dielectric on said first dielectric cap, said upper interlevel dielectric having an opened area vertically aligned with said opening of said first dielectric cap; oxidizing said exposed surface of said at least one metal line, and exposed sidewalls of said first dielectric cap and said upper interlevel dielectric; providing a planarizing dielectric material to said structure, said planarizing dielectric material filling said opened area; providing a line opening in an upper portion of the upper interlevel dielectric by selectively removing portions of the planarizing dielectric material, the oxidized surface of the interlevel dielectric and the upper interlevel dielectric; removing remaining planarizing dielectric material within said opened area; removing any remaining oxidized surface of the interlevel dielectric and said first dielectric cap as well as the oxidized surface of the metal line whereby a via opening and an anchoring recessed area are formed; providing a liner covering portions of the remaining metal line within said anchoring recessed area; and filling said at least one line opening, said at least one via opening and said anchoring recessed area with a conductive material.