Patent ID: 8471319
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; an element isolation region that is defined in the semiconductor substrate and that has an element isolation insulating film formed therein; an active region defined in the semiconductor substrate which is delineated by the element isolation region; a gate insulating film formed in the active region; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region above a sidewall portion of the charge storage layer, and a third region above an upper surface portion of the charge storage layer, the interelectrode insulating film including a stack of an upper silicon oxide film, a middle silicon nitride film, and a lower silicon oxide film; and a control gate electrode formed above the interelectrode insulating film; wherein the middle silicon nitride film is thinner in the third region than in the second region and the upper silicon oxide film is thicker in the third region than in the second region.