Patent ID: 7068533
Filing Date: 2006-06-27
Classification: G11C

Abstract:
1. A configuration of resistive memory cells comprising: a plurality of first current lines; a plurality of second current lines; a plurality of third current lines; a plurality of resistive memory cells being disposed in a memory matrix form between the first and second current lines, the first current lines defining the columns of the memory matrix, while the second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of the first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of the selection transistors being connected to a multiplicity of the resistive memory cells of a row of the memory matrix, the drain-source paths of different selection transistors being connected to a fourth current line, the gates of the selection transistors of a row of the memory matrix form being connected to one of the third current lines; and a control circuit configured to sense a resistance of a selected memory cell by: