Patent ID: 7106615
Filing Date: 2006-09-12
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory cell block that is provided at an intersection between a first bit line and a first word line group and has one end connected to the first bit line and the other end connected to a common node, the first memory cell block including a plurality of series-connected unit cells; a second memory cell block that is provided at an intersection between a second bit line, which is complementary to the first bit line, and a second word line group and has one end connected to the second bit line and the other end connected to the common node, the second memory cell block including a plurality of series-connected unit cells; a plate line that is connected to the common node; and a plate line drive circuit that is connected to the plate, the plate line drive circuit setting the plate line in a floating state when data restore is executed in the unit cell; wherein when data restore is executed in a selected one of the unit cells, a potential corresponding to the first bit line is applied to one end of the selected unit cell and a complementary potential corresponding to the second bit line is applied to the other end of the selected unit cell via the common node.