Patent ID: 6268246
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method for fabricating a memory cell, comprising:forming a first access line for a storage node, the first access line including a first terminal and a second terminal;forming a first dielectric layer over the first access line and first and second terminals;forming a conductive plug through the first dielectric layer and contacting the second terminal;forming a second dielectric layer on the first dielectric layer and plug;forming an opening through the first and second dielectric layers to the first terminal;forming a second access line on the second dielectric layer plus filling the opening;forming a third dielectric layer on the second access line and second dielectric layer;forming a second opening through the second and third dielectric layers to the plug;forming a conductive layer on the third dielectric plus filling the second opening to contact the plug;patterning the conductive layer to form the bottom electrode of a capacitor; andforming a capacitor dielectric plus top electrode on the bottom electrode.