Patent ID: 7842999
Filing Date: 2010-11-30
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a cell array region in which memory cells are laid out in a plurality of rows and columns, each of the memory cells including a cell transistor, an interlayer insulating film covering the cell transistor, a storage node contact piercing through the interlayer insulating film and connected at one end to the cell transistor, and a memory element provided over the interlayer insulating film and connected to the other end of the storage node contact; and a word line connection region provided adjacent to the cell array region, the cell transistor of each of the memory cells comprising a silicon pillar formed substantially perpendicularly to a main surface of a substrate, first and second diffusion layers provided respectively at a lower part and an upper part of the silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, the second diffusion layer being connected to the storage node contact, the word line connection region comprising a plurality of dummy silicon pillars formed substantially perpendicularly to the main surface of the substrate and arranged in at least one column, and a plurality of dummy gate electrodes covering a side surface of an associated one of the dummy silicon pillars via a dummy gate insulation film, the gate electrodes of the cell transistors belonging to a same row being merged with each other to provide a plurality of word lines correspondingly to the rows, each of the dummy gate electrodes connected to an associated one of the word lines; and the semiconductor memory device further comprising a plurality of auxiliary word lines formed in the cell array region, each of the auxiliary word lines buried in the interlayer insulating film and in contact with an associated one of the dummy gate electrodes so that each of the auxiliary word line is electrically connected to an associated one of the word lines through the associated one of the dummy gate electrodes.