Patent ID: 6353634
Filing Date: 2002-03-05
Classification: H04N

Abstract:
Apparatus for decoding a serial video data stream having at least one header, said apparatus comprising:a programmed gate array for receiving said serial video data stream and an external clock signal; said programmed gate array detecting said at least one header, said programmed gate array converting said serial video data stream into a plurality of video data words having first, second, third and fourth data bytes whenever said programmed gate array detects said at least one header; said programmed gate array generating a write signal and first, second, third and fourth byte enable signals whenever said programmed gate array detects said at least one header; a video decoder connected to said programmed gate array to receive said write signal, said first, second, third and fourth byte enable signals and said first, second, third and fourth data bytes of each of said plurality of video data words; said video decoder having said first, second, third and fourth data bytes of each of said plurality of video data words written therein in response to said write signal and said first, second, third and fourth byte enable signals; said video decoder decompressing said first, second, third and fourth data bytes of each of said plurality of video data words using a decompression algorithm having a bi-orthogonal (7, 9) wavelet transform to generate a plurality of decoded video data words representing a video image; and a microcontroller connected to said video decoder, said microcontroller initializing said video decoder allowing said video decoder to decompress said first, second, third and fourth data bytes of each of said plurality of video data words using said decompression algorithm, said microcontroller initializing said video decoder when power is supplied to said video decoder.