Patent ID: 7249242
Filing Date: 2007-07-24
Classification: G06F,Y02D

Abstract:
1. A computational unit in an adaptable computing engine, wherein the computational unit includes a clock signal for determining a processor cycle, the computational unit comprising one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs; at least one pipeline register coupled between the bus and at the input of least one functional unit input; a control signal for selectively causing the at least one pipeline register to hold a data value from the bus for more than one processor cycle at the input of the at least one functional unit, the data value being obtainable at the input at a start of a next processor cycle upon being needed; a coupling of a pair of pipeline registers such that the pair of registers is responsive to a control signal value; and control circuitry for setting the pair of pipeline registers into predetermined states based on the control signal value.