Patent ID: 6216257
Filing Date: 2001-04-10
Classification: G06F,H03K

Abstract:
A method for configuring an FPGA device having plural variable grain blocks (VGB's) each including wedged-together, fine grained, function-imrDlementingq constructs and overlapping coarse grained, function-implementing constructs, and the FPGA device further having diversified VGB interconnect resources, wherein said diversified VGB interconnect resources include: non-global, maximum length lines; short-haul, general interconnect lines that sean a distance of at least two VGB's: and intermediate length lines that are shorter than the non-global, maximum length lines but lonaer than said short-haul, general interconnect lines and the FPGA device further having for each VGB local feedback lines which are each dedicated to providing intraconnect within the respective VGB; said configuring method comprising:(a) mapping synthesis definitions to fit within the fine or coarse arained constructs of the variable grain blocks (VGB's) of the FPGA device; and(b) rearranging the mapped constructs to increase nucleated function development within the VGB's, as opposed to maximizing cascaded function development through use of multiple ones of the VGB's and use of said intermediate lenath lines or maximum length lines for the same function development, said increase of nucleated function development operating to reduce utilization of said VGB interconnect due to cascaded development of functions through multiple VGB's.