Patent ID: 7575977
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit (IC) on a substrate such that the including a lateral double-diffused metal-oxide-silicon (LDMOS) device having a first polycrystalline silicon (polysilicon) gate structure, a P-channel metal-oxide-silicon (PMOS) device having a second polysilicon gate structure, and an N-channel metal-oxide-silicon (NMOS) device having a third polysilicon gate structure, wherein the method comprises: forming a polysilicon layer over the substrate such that the polysilicon layer has a substantially uniform thickness; forming a first mask on the polysilicon layer, and subsequently etching the polysilicon layer though openings defined in the first mask to form the second and third polysilicon gate structures, and to define a first side edge of the first polysilicon gate structure; forming a second mask over the second and third polysilicon gate structures, and over a portion of the first polysilicon gate structure, and subsequently etching the first polysilicon gate structure though an opening defined in the second mask to define a second edge of the first polysilicon gate structure; and implanting a dopant into the substrate through the opening in the second mask using a high energy implant process to form a deep implant region adjacent to said second edge of the third polysilicon gate structure such that a depth of said deep implant region is greater than said thickness of said polysilicon layer.