Patent ID: 6489201
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A method for fabricating a non-volatile memory device, the method comprising the steps of:i) depositing an insulating interlayer of oxide on a semiconductor substrate on which a plurality of active areas defined by a field area extend in a first direction and a plurality of word lines extending in a second direction are formed on the active areas; ii) forming a plurality of bit line contact holes for exposing first regions of the active areas by etching the insulating interlayer; iii) depositing a polysilicon layer and etching-back the polysilicon layer thereby forming bit line plugs in the bit line contact holes; iv) performing a first cleaning process using a first etchant having a similar etching rate with respect to polysilicon and oxide thereby removing a damaged layer which is created on a surface of the insulating interlayer when the etch back process is carried out with respect to the polysilicon layer; v) sequentially depositing an etching stop layer and a bit line insulating layer; vi) etching the etching stop layer and the bit line insulating layer to form a plurality of bit line insulating layer patterns and etching stop layer patterns which extend in the first direction and defining a bit line wiring area between adjacent bit line insulating layer patterns; vii) forming a plurality of metal contact holes for exposing second regions of the active areas by etching the insulating interlayer; viii) performing a second cleaning process using a second etchant, thereby removing a native oxide layer from a surface of the bit line plug; and ix) depositing a metal layer on the resulting structure and removing the metal layer until the bit line insulating layer pattern is exposed using a chemical mechanical polishing process, at the same time, forming a metal wiring for filling the metal contact hole.