Patent ID: 6148314
Filing Date: 2000-11-14
Classification: G06F

Abstract:
Apparatus for performing a floating point addition in which a first operand is added to a second operand, said apparatus comprising:an alignment-shifter for floating-point-significance-aligning said first operand to generate an aligned first operand;an adder having a first-adder-input and a second-adder-input for adding said aligned first operand input to said first-adder-input to said second operand input to said second-adder-input to generate a sum;a normalizer for normalizing said sum to generate a normalized sum;a rounding-increment-determination-circuit for generating a rounding signal indicating whether or not said normalized sum should be subject to a rounding-increment; andan incrementer responsive to said round signal for incrementing said normalized sum to generate a rounded sum; whereinwhen performing a succeeding floating point addition that uses as one input operand a result of said floating point addition, said normalized sum is fed back as said second operand to said second-adder-input and said rounding signal is used to generate a carry-in input to said adder such that said adder gives effect to any rounding-increment for said normalized sum.