Patent ID: 6421813
Filing Date: 2002-07-16
Classification: G06F

Abstract:
A method for selectively providing visibility and control over components within a programmable logic circuit during testing of the programmable logic circuit, comprising:receiving a specifier for a memory element to be accessed during testing of the programmable logic circuit, the memory element residing within a design specifying logic to be programmed into the programmable logic circuit, modifying the design so that the memory element is accessible through I/O pins on the programmable logic circuit; receiving a specifier for a breakpoint condition within the programmable logic circuit, the specifier indicating when execution of the programmable logic circuit is to be stopped during the testing; modifying the design so that the programmable logic circuit is stopped when the breakpoint condition occurs during the testing; programming the modified design into the programmable logic circuit; testing the programmable logic circuit by operating the programmable logic circuit, and accessing the memory element during the testing.