Patent ID: 6124181
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A method for manufacturing a bipolar transistor, comprising:forming a first insulating layer on a semiconductor substrate of a first conductivity type;forming a first polycrystalline silicon layer of a second conductivity type on said first insulating layer;forming a second insulating layer on said first polycrystalline silicon layer;patterning said second insulating layer and said first polycrystalline silicon layer to form an opening within said second insulating layer and said first polycrystalline silicon layer;overetching said first insulating layer by using said second insulating layer and said first polycrystalline silicon layer as a mask after said opening is formed;forming a second polycrystalline silicon layer on a exposed entire surface of said semiconductor substrate, said first and second insulating layers and said first polycrystalline silicon layer after said first insulating layer is overetched;performing an oxidizing process upon said second polycrystalline silicon layer except for a part of said second polycrystalline silicon layer under said first polycrystalline silicon layer;removing an oxidized part of said second polycrystalline silicon layer by a wet etching process;implanting impurities of said second conductivity type into said semiconductor substrate to form a base region within said semiconductor substrate after the oxidized part of said second polycrystalline silicon layer is removed;forming a sidewall insulating layer on a sidewall of said first and second polycrystalline silicon layers after said base region is formed;forming a third polycrystalline silicon layer of said first conductivity type on said base region of said semiconductor substrate after said sidewall layer is formed; andcarrying out an annealing operation, so that impurities of said second conductivity type are diffused from said first polycrystalline silicon layer via said second polycrystalline silicon layer into said semiconductor substrate to form a graft base region within said semiconductor substrate and impurities of said first conductivity type are diffused from said third polycrystalline silicon layer into said base region of said semiconductor substrate to form an emitter region within said base region.