Patent ID: 9093303
Filing Date: 2015-07-28
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a semiconductor substrate; a plurality of p-channel metal oxide semiconductor (PMOS) gate structures disposed proximate to each other on said semiconductor substrate, each of said PMOS gate structures comprising: a plurality of n-channel metal oxide semiconductor (NMOS) gate structures disposed on proximate to each other on said semiconductor substrate, each of said NMOS gate structures comprising: sloped contact etch stop layer (CESL) spacers disposed on lateral surfaces of said gate offset spacers of said PMOS gate structures and on lateral surfaces of said gate offset spacers of said NMOS gate structures, said sloped CESL spacers having a height of ¼ to ¾ of a height of said PMOS gate structures and said NMOS gate structures; a first CESL disposed over said PMOS gate structures and said sloped CESL spacers on said lateral surfaces of said gate offset spacers of said PMOS gate structures and not disposed over said NMOS gate structures, said first CESL comprising silicon nitride, said first CESL being free of reentrant surface profiles between said PMOS gate structures; and a pre-metal dielectric (PMD) layer disposed over said first CESL.