Patent ID: 6664859
Filing Date: 2003-12-16
Classification: H03L,H04L

Abstract:
An apparatus comprising a phase-lock-loop state machine for generating a digital clock signal, the phase-lock-loop state machine comprising:a first state for serving as an entry point after a reset and for generating a first clock signal; a second state for generating a second clock signal; a third state for generating the second clock signal; a fourth state for generating the first clock signal; a fifth state for generating the first clock signal; a transition from the first state to the second state on a first control signal; a transition from the first state to the fifth state on a second control signal; a transition from the second state to the third state on the first control signal; a transition from the second state to the fifth state on the second control signal; a transition from the third to the fourth state on the first control signal; a transition from the third state to the fifth state on the second control signal; a transition from the fourth state to the first state on the first control signal; a transition from the fourth state to the fifth state on the second control signal; and a transition from the fifth state to the first state on the first control signal; wherein transitions between the states occur at a predetermined frequency.