Patent ID: 7346818
Filing Date: 2008-03-18
Classification: G06F,G11C

Abstract:
1. A memory system, comprising: a first memory having addressable memory locations configured to store data; a second memory having memory locations configured to store hash codes and decompressed addresses for addressable memory locations of the first memory a third memory having addressable memory locations configured to store data; and a control circuit coupled to the first, second and third memories, the control circuit configured to generate a first hash code from a requested address to a memory location in the first memory and compare the first hash code to hash codes for decompressed addresses stored in the second memory, the control circuit further configured to determine whether an address stored in the second memory corresponds to the requested address in response to the first hash code matching a hash code for a decompressed address and access a memory location in the third memory in response to an address stored in the second memory corresponding to the requested address.