Patent ID: 6509235
Filing Date: 2003-01-21
Classification: H01L

Abstract:
A method for making an embedded memory metal oxide semiconductor (MOS), the method comprising:providing a semiconductor wafer, with a memory array area and a periphery circuits region defined on the surface of the silicon substrate of the semiconductor wafer; forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer; performing a first ion implantation process in the undoped polysilicon layer in the memory array area so as to transform the undoped polysilicon layer in the memory array area to a doped polysilicon layer; forming a protective layer and a first photoresist layer on the surface of the semiconductor wafer, respectively; performing a first photolithographic process so as to define a plurality of gate patterns in the first photoresist layer in the memory array area; applying the patterns in the first photoresist layer as a hard mask for etching the protective layer in the memory array area down to the surface of the doped polysilicon; removing the first photoresist layer; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second photolithographic process so as to define a plurality of gate patterns in the second photoresist layer in the periphery circuits region; applying the patterns in the second photoresist layer and the protective layer remaining on the surface of the doped polysilicon layer as a hard mask to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area down to the surface of the first dielectric layer, so as to simultaneously form a gate of each MOS in the periphery circuits region and in the memory array area; performing a second ion implantation process so as to form lightly doped drains (LDD) of each MOS on the semiconductor wafer; removing the second photoresist layer; forming a silicon nitride layer and a second dielectric layer, respectively, on the surface of the semiconductor wafer and covering the surfaces of each gate; performing an etching process for removing part of the second dielectric layer and the silicon nitride layer so as to form a spacer located on either side of the gate in the periphery circuits region; and performing a third ion implantation process so as to form the source and drain of each MOS in the periphery circuits region, and performing an ion implantation process to the undoped polysilicon layer in the gate of each MOS in the periphery circuits region at the same time.