Patent ID: 8278157
Filing Date: 2012-10-02
Classification: H01L

Abstract:
1. A method for fabricating an array substrate, comprising: forming a first metal layer over a substrate; patterning the first metal layer by a first photolithography, forming a gate line, a gate electrode connected to the gate line, and a pad over the substrate; forming an insulating layer, a semiconductor layer, and an ohmic contact layer over the substrate, covering the gate line, the gate electrode and the pad; and patterning the ohmic contact layer, the semiconductor layer, and portions of the insulating layer by a second photolithography, forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad, wherein the semiconductor structure comprises a patterned insulating layer substantially covering the gate electrode, a patterned semiconductor layer and a patterned ohmic contact layer, and a top surface of the substrate not covered by the gate line, the gate electrode, and the pad is covered by the patterned insulating layer, and wherein the second photolithography comprises: forming a resist layer over the ohmic layer; patterning the resist layer by a photolithography using a mask having an opaque area, a transparent area, and a partially light-transmittive area, to form an opening in the resist layer substantially relative to the partially light-transmittive area, a first portion with a first thickness in the resist layer substantially relative to the opaque area, and a second portion with a second thickness in the resist layer substantially relative to the partially transparent area, wherein the first thickness is greater than the second thickness, the transparent area substantially aligns to the pad, the opaque area substantially aligns to the gate electrode, and the partially light-transmittive area substantially aligns to an area other than the pad and the gate electrode; performing a first etching, using the first resist portion and the second portion of the resist layer as etching masks, to remove the ohmic contact layer exposed by the opening, the semiconductor layer and the insulating layer underlying the semiconductor layer and stopping on the pad; performing a second etching to the first and second portions of the resist layers, leaving the first portion of the resist layer with a reduced thickness substantially over the gate electrode and portions of the ohmic contact layer not exposed by the first portion of the resist layer with a reduced thickness; performing a third etching to etch the ohmic contact layer exposed by the first portion of the resist layer and the semiconductor layer thereunder; and removing the first portion of the resist layer with a reduced thickness to leave a semiconductor structure and a pad exposed by the opening, wherein the semiconductor structure comprises the insulating substantially covering the gate electrode, the patterned semiconductor layer, and the patterned ohmic contact layer.