Patent ID: 6032249
Filing Date: 2000-02-29
Classification: G06F

Abstract:
A system for providing direct execution of a serializing instruction in a processor, the processor including execution logic having a pipeline for executing a nonserializing instruction, the execution logic including a floating-point execution unit, the nonserializing instruction being a floating-point instruction, the system comprising:separate logic, different from the execution logic, for executing a serializing instruction, the serializing instruction being a floating point status and control register (FPSCR) instruction, the separate logic being FPSCR execution logic; andan instruction queue, coupled directly to the separate logic and to the execution logic, for storing both the serializing instruction and the nonserializing instruction, recognizing the serializing instruction and the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic so that the serializing instruction is executed without the serializing instruction being provided to the pipeline of the execution logic.