Patent ID: 6037226
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method of fabricating a nonvolatile semiconductor memory device comprising a matrix of memory cells on a substrate of a first conductivity type, the matrix having a row direction and a column direction, the method comprising the steps of:forming a plurality of common source regions of a second conductivity type in the column direction within the substrate, thereby defining a plurality of intermediate regions in the column direction within the substrate between pairs of adjacent common source regions;forming an insulating film on the substrate;forming a plurality of alternating, contiguous insulating and first conductive strips in the column direction on the insulating film, each first conductive strip being located on and extending to a first side of each common source region;depositing a second conductive layer over the substrate;selectively etching the second conductive layer, the insulating strips, and the first conductive strips to form a plurality of second conductive strips, etched insulating strips, and etched first conductive strips, respectively, in the column direction, each etched first conductive strip being located on the insulating film to the first side of each common source region, each etched insulating strip being located on the insulating film above and to a second side of each common source region and being contiguous to the etched first conductive strip on the insulating film to the first side of the common source region, thereby exposing a plurality of said intermediate regions in the column direction on the insulating film;forming, using the second conductive strips as a mask, a plurality of drain regions of the second conductivity type in the column direction within the substrate, a drain region between members of each pair of adjacent common source regions;forming a dielectric layer on exposed surfaces of the second conductive strips and also on exposed surfaces of the etched first conductive strips;depositing a third conductive layer over the substrate on the dielectric layer and exposed portions of the substrate;selectively etching the third conductive layer to form a plurality of control gates in the row direction on the dielectric layer on each of a plurality of second conductive strips; andetching, using the control gates as a mask, the first conductive strips, the insulating strips, and the second conductive strips to form a plurality of first floating gates, insulating islands, and second floating gates, respectively, remaining below each control gate.