Patent ID: 9118398
Filing Date: 2015-08-25
Classification: H03K,H04B

Abstract:
1. A switch comprising: a first device, a first NMOS FET, a second device, a second NMOS FET, a receiver enabling node, a transmitter enabling node, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a voltage source, a first capacitor and a second capacitor; wherein a first terminal of the first device is connected to a transmitter port, a second terminal of the first device is connected to a receiver enabling node via the first resistor, a third terminal of the first device is connected to ground via the first capacitor, a fourth terminal of the first device is connected to ground via the second resistor, the third terminal of the first device is further connected to the voltage source via the ninth resistor; a drain of the first NMOS FET is connected to an antenna port, a gate of the first NMOS FET is connected to a transmitter enabling node via the third resistor, a source of the first NMOS FET is connected to the transmitter port, a body of the first NMOS FET is connected to ground via the fourth resistor; a first terminal of the second device is connected to the antenna port, a second terminal of the second device is connected to the receiver enabling node via the fifth resistor, a third terminal of the second device is connected to a receiver port, a fourth terminal of the second device is connected to ground via the sixth resistor; a drain of the second NMOS FET is connected to the receiver port, a gate of the second NMOS FET is connected to the transmitter enabling node via the seventh resistor, a source of the second NMOS FET is connected to ground via the second capacitor, a body of the second NMOS FET is connected to ground via the eighth resistor, the source of the second NMOS FET is further connected to the voltage source via the tenth resistor.