Patent ID: 8051273
Filing Date: 2011-11-01
Classification: G06F

Abstract:
1. A mixed mode parallel processor system comprising: a plurality of processing units, each processing unit including a plurality of processing elements, the processing units including: at least one instruction stream selector in association with the processing elements belonging to the processing unit; at least one control circuit performing, for the plurality of processing elements in each of the processing units, instruction cache control and instruction sequence control; and a memory and register resources; wherein in MIMD mode operation, the control circuit in the processing unit uses the memory and the register resources of at least one processing element as an instruction cache or as a tag storage area of an instruction cache of the processing unit, respectively; the at least one processing element operating as a hardware element needed for issuing a MIMD instruction; the instruction stream selector uses, under control by the control circuit, the memory of the at least one processing element as an instruction cache, and selects an instruction as read out from the instruction cache; the instruction selected by the instruction stream selector is supplied to at least one of the remaining processing elements in the processing unit; the at least one of the remaining processing elements operating as a data path for carrying out arithmetic/logic processing as specified by the instruction.