Patent ID: 6018808
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A system for testing a plurality of hardware interrupt service routines for a microprocessor prior to the completion of a power-on, self-test (POST) program for the microprocessor, set in a read-only memory (ROM) of the microprocessor, the system incorporating a read/writable memory formed in the same semiconductor chip as the microprocessor and ordinarily inoperative during the POST, the system comprising:(a) a diagnostic interrupt vector table set in the read/writable memory, the table comprising a plurality of interrupt vectors corresponding to a plurality of hardware interrupt routines, and a physical address for each of the interrupt vectors corresponding to the address of a diagnostic interrupt service routine for that interrupt vector;(b) means for selecting one of a plurality of devices and for causing the selected device to initiate an interrupt signal;(c) circuitry for transmitting the interrupt signal to the microprocessor for recognition and storage of the interrupt signal;(d) means for accessing the read/writable memory for the interrupt signal and reading out the corresponding physical address; and(e) means for performing the diagnostic interrupt service routine.