Patent ID: 7442985
Filing Date: 2008-10-28
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor layer including an element region and an element isolating region for separating said element region; a first conductive layer formed within said element region with an insulating film interposed therebetween; a second conductive layer formed on said first conductive layer within said element region, said second conductive layer formed on said first conductive layer extending into said element isolating region, and said second conductive layer including a first section formed on said first conductive layer and a second section formed within said element isolating region; a third conductive layer formed on said second conductive layer and exposing at least one part of a surface of said second section; and a contact region electrically connected to an exposed surface of said second section, wherein a resistance element comprising said second conductive layer is formed within said element isolating region.