Patent ID: 6157250
Filing Date: 2000-12-05
Classification: G06F,H05K

Abstract:
A method of minimizing clock jitter in a clock driver disposed on a printed circuit board, said method comprising:providing a clock driver;electrically isolating a region on the printed circuit board through zoning or moating;placing said clock driver in said region;providing a local ground having less than 100 mV, peak-to-peak, of noise to said region;grounding said clock driver to said local ground;providing a local power source having less than 100 mV, peak-to-peak, of noise to said region; andsupplying said clock driver with power from said local power source, wherein said local power source is obtained from a general power supply of said board by filtering said general power supply with a multi-stage decoupling capacitor scheme having less than 1 nH of total parasitic inductance.