Patent ID: 7805553
Filing Date: 2010-09-28
Classification: G06F

Abstract:
1. An integrated circuit device comprising: at least one common transceiver macrocell that transfers data through a serial bus and has a circuit necessary for host operation and a circuit necessary for device operation, the common transceiver macrocell including: an analog front-end circuit including a circuit that transmits and receives data through the serial bus; and a logic circuit, the logic circuit including: a parallel/serial conversion circuit that converts parallel data from an external circuit of the common transceiver macrocell into serial data; a first parallel interface that serves as an interface between the external circuit and the parallel/serial conversion circuit; a sampling clock generation circuit that generates a sampling clock signal for sampling serial data received through the serial bus; a serial/parallel conversion circuit that converts serial data received through the serial bus into parallel data; and a second parallel interface that serves as an interface between the serial/parallel conversion circuit and the external circuit, the analog front-end circuit including: a first transfer mode transmitter circuit that transmits data through the serial bus in a first transfer mode; a second transfer mode transmitter circuit that transmits data through the serial bus in a second transfer mode that is higher in speed than the first transfer mode; a third transfer mode transmitter circuit that transmits data through the serial bus in a third transfer mode that is higher in speed than the second transfer mode; a first single-ended receiver circuit connected with a first signal line of differential data signal lines making up the serial bus; a second single-ended receiver circuit connected with a second signal line of the differential data signal lines; a second transfer mode receiver circuit that receives data through the serial bus in the second transfer mode; a third transfer mode receiver circuit that receives data through the serial bus in the third transfer mode; a first detection circuit that detects whether data of the differential data signal lines is valid or invalid; a second detection circuit that detects disconnection of the serial bus; a pull-up circuit for pulling up the first signal line of the differential data signal lines; a first pull-down circuit for pulling down the first signal line of the differential data signal lines; and a second pull-down circuit for pulling down the second signal line of the differential data signal lines.