Patent ID: 6153462
Filing Date: 2000-11-28
Classification: H01L

Abstract:
A method for manufacturing a capacitor applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon an etching stop layer, comprising steps of:a) forming a sacrificial layer over said etching stop layer;b) partially removing said sacrificial layer, said etching stop layer, and said dielectric layer to form a contact window;c) forming a first conducting layer over said sacrificial layer and in said contact window;d) partially removing said first conducting layer and said sacrificial layer to expose a portion of said sacrificial layer and retain a portion of said first conducting layer;e) forming a second conducting layer on top and sidewalls of said portion of said first conducting layer and said portion of said sacrificial layer;f) partially removing said second conducting layer while retaining a portion of said second conducting layer alongside said portion of said first conducting layer and said portion of said sacrificial layer, and removing said portion of said sacrificial layer to expose said etching stop layer;g) forming a conducting material-adhering layer on surfaces of said portions of said first and second conducting layers, and said exposed etching stop layer; andh) forming a rugged conducting layer over said conducting material-adhering layer and then removing said rugged conducting layer on top of said first and second conducting layers and on sidewalls of said second conducting layer to form said conducting material-adhering layer with a rough top surface, while retaining a portion of said rugged conducting layer under said portions of said first and second conducting layers, wherein said retained portions of said first and second conducting layers, said conducting material-adhering layer with said rough top surface, and said portion of said rugged conducting layer construct a capacitor plate.