Patent ID: 6864143
Filing Date: 2005-03-08
Classification: H01L

Abstract:
1. A method of forming a salicided gate electrode on the surface of a substrate, comprising the steps of: providing a silicon semiconductor substrate; defining active regions in a surface of said substrate whereby said active regions are defined by regions of field insulation in said surface of said substrate; growing a layer of gate oxide over said surface of said substrate; depositing a layer of polysilicon over the surface of said layer of gate oxide; patterning and etching said layer of polysilicon and said layer of gate oxide thereby forming a first gate electrode structure; implanting LDD regions in said surface of said substrate whereby said LDD regions are self-aligned with said first gate electrode structure; creating gate spacers whereby said gate spacers contain a first gate spacer layer overlying the sidewalls of said first gate electrode structure and a second gate spacer layer overlying said first gate spacer layer whereby said first gate spacer layer contains silicon oxide whereby furthermore said second gate spacer layer contains silicon nitride thereby creating an intermediately completed gate electrode structure; performing source and drain implants into the surface of said substrate whereby said source and drain implants are self-aligned with said intermediately completed gate electrode structure; depositing a layer of cobalt over the surface of said substrate thereby including the surface of said intermediately completed gate electrode structure; saliciding said layer of cobalt thereby creating reacted and unreacted layers of cobalt on the surface of said substrate thereby including the surface of said intermediately completed gate electrode structure; removing said unreacted cobalt from the surface of said substrate thereby including the surface of said intermediately completed gate electrode structure thereby creating salicided contact regions for said intermediately completed gate electrode structure, thereby including removing said second gate spacer layer from said intermediately completed gate electrode structure, using a warm H depositing a layer of Inter Level Dielectric (ILD) over the surface of said substrate thereby including the surface of said second gate electrode structure; creating contact openings in said layer of ILD whereby said contact openings overlay and align with said salicided contact regions; depositing a layer of metal over the surface of said layer of ILD thereby including said openings created in said layer of ILD; planarizing said layer of deposited metal; and patterning and etching said deposited layer of metal.