Patent ID: 7411247
Filing Date: 2008-08-12
Classification: G11C,H01L

Abstract:
1. A twin MONOS memory embedded in a CMOS device comprising: a memory area and a CMOS area separated by isolation regions in a substrate; a deep N-well in said memory area; polysilicon word gates having polysilicon control gates on sidewalls of said word gates having an oxide layer therebetween and not having an oxide-nitride-oxide (ONO) layer therebetween and having an ONO layer underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage in said memory area; raised polysilicon diffusions in said memory area between each two of said control gates and separated from said control gates by an oxide layer; word lines overlying and crossing said word gates; polysilicon CMOS gates in said CMOS area; source and drain regions in said substrate adjacent to said gates in said CMOS area and in said memory area wherein said source and drain regions in said memory area are underlying and directly contacting said raised polysilicon diffusions; diffusion contacts through a dielectric layer overlying said gates to said raised diffusions at an end of every other raised diffusion alternating in a memory block; control gate contacts through a dielectric layer overlying said gates on an extension of said diffusion contacts or between diffusion contacts; and word gate contacts at ends of said word lines alternately to complete said Twin MONOS memory device.