Patent ID: 7345340
Filing Date: 2008-03-18
Classification: H01L,H02M,Y02B

Abstract:
1. A semiconductor integrated circuit having an LDMOS transistor formed over a first conductivity type semiconductor substrate, the LDMOS transistor comprising: a second conductivity type first well region formed in the first conductivity type semiconductor substrate; a first conductivity type second well region formed in the first well region; a second conductivity type third well region formed in the second well region; a drain region formed in the second well region; a source region formed in the third well region; a gate electrode between the drain region and the source region; an insulating layer formed between the gate electrode and the drain region, wherein the first conductivity type refers to P type and the second conductivity type refers to N type, and the LDMOS transistor is of the P-channel type; and a level shift circuit which uses the P-channel LDMOS transistor, the level shift circuit comprising: wherein the P-channel clamping MOS transistors are the LDMOS transistors; wherein the pair of load MOS transistors are cross-coupled, with the gate electrode of one load MOS transistor coupled with the drain electrode of the other load MOS transistor and the gate electrode of the other load MOS transistor coupled with the drain electrode of the one load MOS transistor; and wherein, in response to a differential input supplied to the pair of differential input MOS transistors, a signal which is level-shifted with respect to the amplitude of the differential input is outputted from the source electrodes of the pair of clamping MOS transistors.