Patent ID: 6836877
Filing Date: 2004-12-28
Classification: G06F

Abstract:
A method of generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, said method comprising the steps of:causing a logic synthesis tool to generate a generic netlist from the RTL code description; identifying hardware elements in the generic netlist; determining key pins for each of said identified hardware elements; extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements; and generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist, wherein said script includes instructions to cause the logic synthesis tool to: apply bottom-up synthesis to modules and sub-modules of the IC design, apply top-down characterization to modules and sub-modules of the IC design, and repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.