Patent ID: 7907693
Filing Date: 2011-03-15
Classification: G11C,H03K,H04L

Abstract:
1. A semiconductor device included within a parallel interface system, comprising: a reference clock transmitting block generating a reference clock signal; a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals; and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate phase-controlled sampling clock signals for the respective plurality of first transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode, wherein the per-pin deskew block,