Patent ID: 6963108
Filing Date: 2005-11-08
Classification: H01L

Abstract:
1. A memory cell, comprising: a semiconductor substrate having at least one trench formed in a surface thereof; a recessed channel region of a first conductivity type semiconductor formed in the semiconductor substrate below each trench; a source region and a drain region both of a second conductivity type semiconductor formed in the semiconductor substrate on opposing sides of each trench, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench; a gate dielectric layer formed on the semiconductor substrate, said gate dielectric layer being formed along the bottom and sidewalls of the trench; and a control gate formed over the gate dielectric layer above the recessed channel region, wherein an upper surface of the control gate is substantially at the same level as an upper surface of the gate dielectric layer over the source and drain, and wherein the bottom of the source region and the bottom of the drain region are at a depth from a surface of the semiconductor substrate of about 40 percent to 60 percent of the depth of the floor of the trench from the surface of the semiconductor substrate.