Patent ID: 6552573
Filing Date: 2003-04-22
Classification: H03K

Abstract:
A reduced-leakage current dynamic circuit having an active mode and a standby mode and including transistors having a standard threshold voltage and transistors having a low threshold voltage lower than the standard threshold voltage, comprising:a logic circuit coupled between an internal output node and ground, the logic circuit comprising a plurality of logic transistors each having the low threshold voltage, the logic circuit conditionally coupling the internal output node to the reference dependent upon logic signals received by the plurality of logic transistors; a pre-charge transistor coupled to the internal output node and a pre-charge voltage, the pre-charge transistor having the standard threshold voltage, the pre-charge transistor receiving a clock signal, the clock signal in the active mode alternating between a first voltage causing the pre-charge transistor to couple the internal node of the pre-charge voltage and a second voltage causing the pre-charge transistor to isolate the internal node from the pre-charge voltage, the clock signal in the standby mode maintaining the second voltage isolating the internal node from the pre-charge voltage; and a standby transistor coupled between the internal output node and ground the standby transistor the standby transistor receiving a standby signal, the standby signal in the active move causing the standby transistor to isolate the internal output node from ground, the standby signal in the active mode causing the standby transistor to couple the internal output node to ground.