Patent ID: 8121543
Filing Date: 2012-02-21
Classification: G06F,G06K,Y02D

Abstract:
1. An apparatus, comprising: secure transaction circuitry having a first power state and a second power state, the secure transaction circuitry being configured, when in the second power state, to perform a transaction, using a transceiver, with a further apparatus; memory circuitry, different from the secure transaction circuitry, having power states; and a memory controller, different from the secure transaction circuitry, configured to control writing of data to the memory circuitry and reading of data from the memory circuitry, wherein the memory controller is configured to detect a first electrical signal provided by the transceiver and configured, in response to detecting the first electrical signal, to control the secure transaction circuitry to switch from being in the first power state to being in the second power state, without changing a power state of the memory circuitry.