Patent ID: 6720969
Filing Date: 2004-04-13
Classification: G06F,G06T,G09G,Y02D

Abstract:
A graphics system comprising:a memory configured to receive and store graphics data, wherein the memory comprises, a RAM configured to store the graphics data, a level two cache memory connected to the RAM, and a level one cache memory connected to the level two cache memory; an array of registers configured to store dirty tag bits, wherein the dirty tag bits indicate the status of the graphics data in the level one cache, wherein the status indicates whether the graphics data is modified or unmodified; and a memory request processor connected to the memory and to the array of registers, wherein the memory request processor controls the transfer of graphics data from the level one cache to the level two cache according to the dirty tag bits; a request preprocessor configured to receive requests for graphics data accesses to the memory, wherein the request preprocessor transforms the requests into memory commands according to stored tags indicating contents of the cache memories, and wherein the memory commands comprise cache commands and pixel commands; a cache queue connected to the request preprocessor and to the memory request processor, wherein the cache queue stores the cache commands and delivers the cache commands to the memory request processor on a first-in-first-out basis, wherein the memory request processor asserts memory control signals to direct page fetches from the RAM to the level two cache and block fetches from the level two cache to the level one cache in response to the cache commands; a pixel queue connected to the request preprocessor, wherein the pixel queue stores the pixel commands and outputs the pixel commands on a first-in-first-out basis; and a pixel request processor connected to the pixel queue, wherein the pixel request processor controls the transfer of graphics data into and out of the level one cache according to the pixel commands.