Patent ID: 8198931
Filing Date: 2012-06-12
Classification: H03K

Abstract:
1. A delay chain, comprising: a data delay rail having a plurality of interconnected stages, each stage including an inverter of a first size; a data complement delay rail having a plurality of interconnected stages, each stage including an inverter of the first size; and a plurality of cross-coupled inverter pairs interconnecting the data delay rail and the data complement delay rail, each cross-coupled inverter pair comprising a first inverter and a second inverter, each of a second size; wherein each first inverter includes an input connected to a data stage in the data delay rail and an output connected to a stage in the data complement delay rail that is forward of the data stage; wherein each second inverter includes an input connected to a data complement stage in the data complement delay rail and an output connected to a stage in the data delay rail that is forward of the data complement stage; wherein the inverters of the second size are larger than the inverters of the first size.