Patent ID: 6792571
Filing Date: 2004-09-14
Classification: H03M

Abstract:
A Viterbi detector for use in a partial response maximum likelihood (PRML) signal processing apparatus, the PRML signal processing apparatus including a partial response (PR) equalizer, the PR equalizer outputting a PR equalizer output signal serially, the Viterbi detector used for receiving the PR equalizer output signal, wherein the PR equalizer operates at a first frequency and the Viterbi detector operates at a second frequency, and the Viterbi detector is capable of performing Viterbi detection according to PR equalizations with a plurality of sets of parameters in the PR equalizer, the Viterbi detector comprising:an input buffer for receiving the PR equalizer output signal, and selectively outputting the PR equalizer output signal serially or in parallel, according to the first frequency and the second frequency; a branch metric calculation unit for receiving the PR equalizer output signal outputted by the input buffer and receiving a reference level value stored in a reference level register so as to obtain a plurality of branch metrics; an add-compare-select (ACS) circuit for receiving the branch metrics and calculating a plurality of path metrics, and obtaining a plurality of path control signals; a path memory unit comprising a detection sequence switch, the path memory unit being for receiving the path control signals, using an output bit value stored in a storage unit as an input to the detection sequence switch, and outputting a Viterbi detector output signal; and a clock buffer for generating a clock signal at the second frequency and outputting the clock signal at the second frequency to the branch metric calculation unit, the ACS circuit, and the path memory unit; wherein the detector sequence switch is operative according to a union trellis diagram relation, the union trellis diagram relation is obtained by combining trellis diagram relations associated with the PR equalizations with the sets of parameters in the PR equalizer and setting the PR equalizer and the Viterbi detector operating at the first frequency and the second frequency respectively, the union trellis diagram relation indicates a plurality of sets of output bits and a plurality of sets of reference levels which are associated with the PR equalizations with the sets of parameters respectively, the output bits are stored in the storage unit, the reference levels are stored in the reference level register, and according to the first, second frequencies, and the PR equalization with the set of parameters, the storage unit and the reference level register output the output bit value and the reference level value respectively.