Patent ID: 7064373
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A vertical memory cell array containing at least one vertical memory cell, the memory cell comprising: a storage capacitor formed in a deep trench in a semiconductor substrate and containing an inner electrode arranged in the deep trench; a selection transistor formed essentially between the substrate surface of the semiconductor substrate and an upper edge of the inner electrode; a lower source/drain region in the selection transistor connected to the inner electrode and an upper source/drain region; a selection transistor gate electrode formed, at least in segments, as segments of an addressing line arranged in active trenches that extend from the substrate surface to below the upper edge of the inner electrode and insulate adjacent memory cells from one another; and an auxiliary structure extending essentially from a bottom of an active trench as far as the upper edge of the inner electrode, wherein the addressing line is formed in the region between the substrate surface and the upper edge of the auxiliary structure.