Patent ID: 6448817
Filing Date: 2002-09-10
Classification: G06F,H03K

Abstract:
An article of manufacture for simulating a logic device that processes an n-bit word having a selected bit and (nâˆ’1) non-selected bits, comprising:computer program code for causing a computer to generate a pre-charge voltage; computer program code for causing said computer to evaluate a logic state of the selected bit using a first convention and logic states of the non-selected bits using a second convention, including (a) computer program code for causing said computer to evaluate a voltage of the selected bit, and a voltage of each of the non-selected bits, and (b) computer program code for causing said computer to discharge said pre-charge voltage if the selected bit is a first voltage and each of the non-selected bits is a second voltage, whereby the discharge of the pre-charge voltage indicates an all-zero scenario; and a computer usable medium configured to store said computer program codes.