Patent ID: 6081476
Filing Date: 2000-06-27
Classification: G11C,H01L

Abstract:
A clock-synchronized read only memory comprising a memory cell and a mode register for setting an operation mode, the clock-synchronized read only memory outputting data stored in the memory cell in the operation mode set in the mode register and in synchronization with a clock signal,wherein contents of the mode register are set when the data is written to the memory cell, the contents defining the operation mode, and wherein the operation mode is defined by burst length, wrap type and CAS latency,and wherein the mode register includes a MOS transistor having a channel region, andthe contents which are set in the mode register are written by selectively implanting ions of an impurity into the channel region of the MOS transistor, the impurity having a different conductivity type from a conductivity type of the channel region of the MOS transistor.