Patent ID: 7310260
Filing Date: 2007-12-18
Classification: G06F

Abstract:
1. A data register comprising: a data input; a data output; a Write_Select input; a Write_Valid input; a Read_Select input; a Read_Valid input; wherein said Write_Select input is a first control input effective for selectively placing said data register in a write mode of operation in response to a first logic signal if said Write_Valid input is actuated, and said data register disregards said Write_Select input if said Write_Valid input is not actuated; wherein said Read_Select input is a second control input effective for placing said data register in a read mode of operation in response to a second logic signal if said Read_Valid input is actuated, and said data register disregards said Read_Select input if said Read_Valid input is not; and wherein when in said write mode, said data register latches in new data applied to said data input upon the removal of said first logic signal from said Write Select input.