Patent ID: 7514360
Filing Date: 2009-04-07
Classification: H01L

Abstract:
1. A method for fabricating a CMOS semiconductor device structure comprising gate electrodes, said method comprising: providing a dielectric layer on a substrate; depositing a hafnium nitride layer on said dielectric layer wherein an atomic ratio of Nitrogen and Hafnium of said hafnium nitride layer is adjusted to adjust the work-function of said gate electrodes wherein said atomic ratio of nitrogen to hafnium remains greater than one, wherein said depositing of said hafnium nitride layer comprises flowing Nitrogen and Argon atoms into a chamber simultaneously wherein said chamber contains said substrate and a hafnium target; depositing a capping layer on said hafnium nitride layer; patterning said hafnium nitride layer and said capping layer and said dielectric layer to form said CMOS gate electrodes; and forming source and drain regions within said substrate adjacent to said CMOS gate electrodes.