Patent ID: 7126398
Filing Date: 2006-10-24
Classification: H03K

Abstract:
1. An apparatus, comprising: a first circuit comprising a static logic level output; and a second circuit coupled to the first circuit to drive the first circuit, the second circuit comprising a latch, wherein the latch comprises a first inverter and a second inverter each having an input and an output, wherein the input of the first inverter and the output of the second inverter are coupled to a first output node of the latch, and wherein the input of the second inverter and the output of the first inverter are coupled to a second output node of the latch, wherein the first circuit comprises a NOR gate having a first input directly coupled to the first output node of the latch and a second input directly coupled to the second output node of the latch, and wherein the NOR gate has a static logic zero output.