Patent ID: 6689644
Filing Date: 2004-02-10
Classification: G11C

Abstract:
A process for fabricating a memory array comprising:(a) forming a first layer of conductive material; (b) forming a set of second layers for defining memory elements on the first layer; (c) patterning the set of second layers into a plurality of parallel, spaced-apart strips; (d) etching the first layer in alignment with the strips formed from the set of second layers; (e) forming a third layer of conductive material on the strips formed from the set of second layers; (f) forming a set of fourth layers for defining memory elements of the second level; (g) patterning the set of fourth layers into a plurality of parallel, spaced-apart strips, the strips formed from the set of fourth layers running generally perpendicular to the strips formed from the first layer; (h) etching the third layer and the strips formed from the set of second layers in alignment with the strips formed from the set of fourth layers; said set of second layers comprising a first anti-fuse layer, said set of fourth layers comprising a second anti-fuse layer, said anti-fuse layers each positioned between a respective pair of diode components that form a diode only after the respective anti-fuse layer is disrupted.