Patent ID: 6687889
Filing Date: 2004-02-03
Classification: G06F

Abstract:
A method for analyzing clock skew in a hierarchical clock tree comprising one or more parent blocks each having one or more child blocks, said method comprising:obtaining one or more child block tags associated with respective child block nodes in said at least one child block; extracting one or more child block network subcircuits, each said child subcircuit comprising a child subcircuit input node and one or more child subcircuit endpoint nodes; for each said one or more child block network subcircuits, determining a time delay between said child subcircuit input node and each of said one or more child subcircuit endpoint nodes; obtaining one or more parent tags associated with respective parent block nodes in said at least one parent block; extracting one or more parent block network subcircuits, each said parent subcircuit comprising a parent subcircuit input node and one or more parent subcircuit endpoint nodes; for each said one or more parent block network subcircuits, determining a time delay between said parent subcircuit input node and each of said one or more parent subcircuit endpoint nodes; obtaining a map of said parent block tags to respective ones of said child block tags; connecting said respective parent block nodes associated with said one or more parent tags to said respective child block nodes associated with said one or more child tags mapped to said respective one or more parent tags; for each of said parent block subcircuits, determining said accumulated time delay between said parent subcircuit input node and each of said one or more child subcircuit endpoint nodes of child subcircuits connected to said parent subcircuit, taking into account said associated child subcircuit time delay and said respective parent subcircuit time delay associated with said parent block.