Patent ID: 6256229
Filing Date: 2001-07-03
Classification: G11C

Abstract:
A memory system comprising:an array of memory cells;a memory controller which controls memory programming operations of the memory system;a programming voltage node configured to receive a first programming voltage;a voltage detection circuit, operably coupled to the programming voltage node and the memory controller, said voltage detection circuit comprising a voltage divider circuit switchable between a first state and a second state, with the voltage divider circuit being configured to produce, when in the first state, a first intermediate voltage at a first node when the first programming voltage is at a first level, a second intermediate voltage at a second node when the first programming voltage is at a second level and a third intermediate voltage at a third node when the first programming voltage is at a third level and with the voltage divider circuit being configured to produce, when in the second state, the first intermediate voltage at the first node when the first programming voltage is at a fourth level, the second intermediate voltage at the second node when the first programming voltage is at a fifth level, and the third intermediate voltage at the third node when the first programming voltage is at a sixth level, with the first voltage level being greater than the fourth voltage level; and said voltage detection circuit further comprising control circuitry, operably coupled to the first node of the voltage divider circuit, said control circuitry being configured to enable the memory controller to initiate a memory program operation when the first programming voltage exceeds the first level and to cause the memory controller to terminate an initiated program operation when the first programming voltage drops below the fourth level.