Patent ID: 8438320
Filing Date: 2013-05-07
Classification: G06F

Abstract:
1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores, comprising: two or more memory channels that make up a first aggregate target of the target IP cores, and the two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores; two or more configurable address tiling functions to transform an incoming address of data requested in a request to a target memory IP core to determine what physical addresses in a bank of memories will service this request; chopping logic configured to chop individual burst requests that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more resulting chopped burst transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target; and address decoding logic that is configured to implement a distribution of requests from the chopped burst transactions to the two or more memory channels making up the first aggregate target, where the address decoding logic implements a channel-selection hash function to enable requests from a first chopped burst transaction to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the first aggregate target.