Patent ID: 9042383
Filing Date: 2015-05-26
Classification: H04L

Abstract:
1. A network interface controller (NIC) for a host computer, comprising: a bus interface communicatively coupled to a memory within the host computer; and circuitry configured to: receive a fabric packet and a network packet from the memory via the bus interface to be transmitted to at least one external device; slice the fabric packet into at least one fabric cell; and queue and schedule the at least one fabric cell and the network packet for transmission of the at least one fabric cell and the network packet over a switch fabric and a packet network, respectively, to the at least one external device, wherein the circuitry comprises: an ingress packet processor configured to define at least one virtual output queue (VOQ) in the memory and map at least one destination endpoint to the at least one VOQ; and an ingress traffic manager configured to queue and de-queue the at least one fabric cell and the network packet in the at least one VOQ, wherein the circuitry is: configured to receive at least one egress fabric cell from the switch fabric and an egress network packet from the packet network and map the at least one egress fabric cell and the egress network packet to at least one egress queue, and configured to manage the at least one egress queue.