Patent ID: 7091890
Filing Date: 2006-08-15
Classification: H03K,H03M,H04L

Abstract:
1. A serializer-deserializer instantiated in configurable logic of an integrated circuit, comprising: an output serializer-deserializer portion instantiated in a portion of the configurable logic, the output serializer-deserializer portion including a first data port; an input serializer-deserializer portion instantiated in another portion of the configurable logic, the input serializer-deserializer portion including a second data port; an input/output pad coupled to the output serializer-deserializer portion via an output buffer and coupled to the input serializer-deserializer portion; the output serializer-deserializer portion configured to receive first parallel data via the first data port, to convert the first parallel data to first serial data and to output via the output buffer and the input/output pad the first serial data; and the input serializer-deserializer portion configured to receive second serial data via the input/output pad, to convert the second serial data to second parallel data and to output via the second data port the second parallel data; wherein the input serializer-deserializer portion comprises a serial to parallel converter for providing the second parallel data; and wherein the input serializer-deserializer portion comprises a delay chain coupled to receive the second serial data and configured to delay the second serial data provided to the serial to parallel converter.