Patent ID: 6539471
Filing Date: 2003-03-25
Classification: G06F

Abstract:
A method of processing instructions in an out-of-order processor having a set of architectural registers readable and writable by the instructions, the method comprising:predicting a direction of an execution path among certain of the instructions; determining a set of the certain instructions in the predicted path that do not employ the output of any other instructions in the same path; forming a block of instructions from at least some of the instructions in the set; copying the architectural registers specified in the block of instructions to respective separate registers; replacing the register specifications in the block of instructions to specify the separate registers rather than the architectural registers themselves; after replacing all the register specifications, determining an improved execution order among all the instructions in the block so as to increase performance of the processor; executing the instructions in the improved order; determining that the predicted execution path direction is valid; and after determining that the direction is valid, writing at least some of the separate registers to respective ones of the architectural registers.