Patent ID: 6144069
Filing Date: 2000-11-07
Classification: H01L

Abstract:
An LDMOS transistor, said transistor comprising:a substrate having a first conductivity type;a first high-voltage tank having a second conductivity type opposite that of said first conductivity type formed in a face of said substrate;a second high-voltage tank having said first conductivity type formed adjacent to and in contact with said first high-voltage tank, such that a major portion of the second high-voltage tank is not within the first high-voltage tank;a first low-voltage tank having said second conductivity type formed within a face of said first high-voltage tank, such that at least one trench isolation region is included within said first low-voltage tank;a second low-voltage tank having said first conductivity type formed within said second high-voltage tank, such that a channel region exists between said second low-voltage tank and said first low-voltage tank;a conductivity gate having portions formed over a portion of said first high-voltage tank, said second high-voltage tank, said first low-voltage tank, and said second low-voltage tank, and insulatively disposed thereon; anda first source/drain region in said first low-voltage tank and a second source/drain region in said second low-voltage tank adjacent opposite ends of said gate structure in said substrate.