Patent ID: 8015338
Filing Date: 2011-09-06
Classification: G06F,H05K

Abstract:
1. A memory system comprising: connector pins including a plurality of data pins, a command pin, and a power signal pin, such that only one of the data pins is configured to receive data in a first operation mode, and the plurality of data pins are configured to receive data in a second operation mode; a set of registers including a first register and a second register, the set of registers being connected to the connector pins; and a controller which outputs the operation mode information to one of the connector pins in response to a first command, provides the operation voltage information to the command pin to transmit the operation voltage information in response to a second command, and sets the operation mode of the memory system into one of the first and second operation modes stored in the first register in response to a third command received via a command pin; wherein the command pin is configured to receive the first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes; one of the connector pins is configured to transmit the operation mode information in response to the first command; the command pin is configured to receive the second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the memory system; one of the connector pins is configured to transmit the operation voltage information in response to the second command; the command pin is configured to receive the third command for setting an operation mode of the memory system into one of the first and second operation modes; the first register storing own operation mode information of the memory system, the own operation mode information including bus width information which indicates one of the first and second operation modes such that, in the first operation mode, the system receives data using one of the data pins and, in the second mode, the system receives data using four of the data pins; and the second register storing operation voltage information concerning an operation voltage of the memory system.