Patent ID: 6108775
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A microprocessor operable in a multitasking mode, comprising:at least one execution unit for executing instructions according to first and second tasks, wherein said first and second tasks are first and second program types, respectively, executed by said microprocessor;a memory for storing at least one instruction associated with said first task and at least one instruction associated with a second task and comprising portions associated with each of said first and second tasks; anda fetch unit, for addressing said memory to retrieve instruction codes corresponding to said first and second tasks for execution by the execution unit, comprising:a branch history circuit, for storing a sequence of results of branching instructions executed by the execution unit;pattern history circuitry, comprising;a plurality of task specific pattern history tables coupled to the branch history circuit, each of said task specific pattern history tables having a plurality of indexed prediction code entries corresponding to said specific task, and each having an output for presenting the contents of one of the prediction code entries corresponding to a branch history field from the branch history circuit;an addressing circuit for selecting an address for an instruction to be fetched; andcircuitry, coupled to the pattern history circuitry and to the memory, for modifying the prediction information responsive to a task switch from the first task to the second task.