Patent ID: 8935491
Filing Date: 2015-01-13
Classification: G06F

Abstract:
1. A hardware logic control system for an array of processing cores shared among a set of software programs, the system including: a collection of fast-access memories, with each memory in the collection dedicated to its associated instance of the programs; a subsystem for updating contents of the fast-access memories based on control by the program instance associated with each given fast-access memory of the collection and indicating whether the contents of any given memory in the collection are updated, with such contents indicated as updated when they are ready for execution of the associated program instance; a controller for allocating the cores among the programs at least in part based on numbers of such instances of individual programs of said set that have their dedicated fast-access memories indicated as updated by the subsystem; and a subsystem for assigning, for any given program among said set for which the allocating yielded at least one core for an upcoming core allocation period (CAP), from instances of the given program, specific instances for execution on those of the cores that were allocated to the given program for that CAP, wherein the assigning involves: producing an execution priority ordered list of instances of the given program that is used in selecting a subset, up to all, of the instances for execution on the upcoming CAP, through classifying the instances into groups that include, in their descending selection priority order: (1) instances that are not waiting for either arrival of input data or completion of memory content transfers to update their fast-access memories; (2) instances that have input data to be processed but are waiting for completion of memory content transfers between their slow-access and fast-access memories, or instances whose fast-access memory contents are ready for resuming their execution but who are waiting for input data to process; and (3) any remaining ones of the instances.