Patent ID: 6127707
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A semiconductor device comprising:a layer of silicon;a first region of said silicon layer having n-type dopants in a certain concentration, said first region being located at the surface of said layer of silicon so as to constitute an n-type region of silicon at said surface;a second region of said silicon layer having p-type dopants in a certain concentration, said second region being located at the surface of said layer of silicon so as to constitute a p-type region of silicon at said surface, the p-type region of silicon being laterally offset from the n-type region of silicon;a third region of said silicon laver extending vertically in-between said p-type region and said n-type region and thereby spacing said p-type region and said n-type region laterally from one another, the highest of said concentrations of dopants of said p-type and n-type regions being greater than that of said third region; anda silicide layer extending directly on the first, second and third regions of silicon, the silicide layer electrically conductively connecting the first and second regions.