Patent ID: 6308312
Filing Date: 2001-10-23
Classification: H03K

Abstract:
A method of controlling leakage current within an integrated circuit comprising the steps of:determining whether a current carrying device within the integrated circuit is susceptible to exhibiting an unacceptable level of leakage current;responsive to said determination, adjusting the threshold voltage of the current carrying device to reduce the current carrying capacity of the device if the device is susceptible to exhibiting an unacceptable amount of leakage current by reducing the current carrying capability of a source resistance transistor connected in series with the current carrying device by connecting a control gate of the source resistance transistor to a first predetermined voltage level; andconnecting the control gate of the source resistance transistor to a second predetermined voltage level to allow the source resistance transistor to conduct a full measure of current if the current carrying device is not susceptible to exhibiting an unacceptable level of leakage current.