Patent ID: 7459755
Filing Date: 2008-12-02
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor layer; a first control gate electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, wherein a first voltage applied on the first control gate forms a first depletion region in the semiconductor layer opposite the first control gate, and a second control gate and a third control gate each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface, wherein the second and third control gates are offset from the first control gate such that, when a second voltage is applied to the second and third control gates, depletion regions are formed opposite the second and third control gates, respectively, such that each of the depletion regions opposite the second and third control gates overlaps the first depletion region; wherein the semiconductor device is provided adjacent a second semiconductor device configured substantially the same as the semiconductor device, and wherein the depletion region of the second control gate overlaps the depletion region of the first control gate of the second semiconductor device.