Patent ID: 6780707
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A method for forming a semiconductor device on a semiconductor substrate, the method comprising:(a) forming isolation layers that define a memory cell area and a peripheral circuit area on the semiconductor substrate and isolate each area; (b) forming a first conductive type transistor in the memory cell area and a first conductive type transistor and a second conductive type transistor in the peripheral circuit area, each transistor including source/drain regions, a gate electrode having sidewall spacers, and a first etch stopping layer; (c) forming an interlayer insulating layer overlying the first and second conductive type transistors; (d) exposing the source/drain regions of the first conductive type transistor in the memory cell area and the peripheral circuit area by etching the interlayer insulating layer; (e) forming first conductive type polysilicon layers on the exposed source/drain regions of the first conductive type transistors; (f) thereafter, exposing the source/drain regions of the second conductive type transistor in the peripheral circuit area by etching the interlayer insulating layer; and (g) forming second conductive type polysilicon layer on the exposed source/drain regions of the second conductive type transistor; and (h) concurrently forming contact pads on the source/drain regions in the memory cell area and the source/drain regions in the peripheral circuit area.