Patent ID: 8151013
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. A storage system coupled to a host computer, comprising: a host interface package comprising a request transfer unit and a management information; a disk interface package providing a plurality of logical storage devices to the host computer; a plurality of micro processor packages, each of the plurality of micro processor packages comprising a micro processor and a local memory storing first control information regarding a logical storage device within the plurality of logical storage devices having input and output processing handled by the micro processor if the micro processor package is handling input and output processing for at least one of the plurality of logical storage devices; a shared memory; and a disk drive; wherein the host interface package, the disk interface package, the plurality of micro processor packages, and the shared memory are coupled to each other; wherein the disk interface package is coupled to the disk drive, wherein the management information comprises an identifier for the each of the plurality of micro processor packages having the first control information stored in the local memory; wherein the shared memory stores second control information comprising control information about each of the plurality of logical storage devices and a lock for each of the plurality of logical storage devices, the lock storing the identifier for the each of the plurality of micro processor packages; wherein if an I/O request is received for a target logical storage device within the plurality of logical storage devices, the request transfer unit refers to the management information and transfers the I/O request to a corresponding first micro processor package within the each of the plurality of processor packages having the first control information regarding the target logical storage device, and wherein if a request is received for changing the handling of the target logical storage device from the first micro processor package to a second micro processor package within the plurality of micro processor packages,