Patent ID: 6333671
Filing Date: 2001-12-25
Classification: G11C

Abstract:
A method for reducing a leakage current on a semiconductor in a sleep mode, comprising the steps of:placing the semiconductor in the sleep mode;providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip, said internal supply voltage being lesser in quantity than said external supply voltage;supplying said external supply voltage to a reference circuit which reduces said supply voltage and outputs therefrom a reference voltage;supplying said reference voltage to a regulator, wherein said regulator attempts to match said reference voltage and outputs therefrom said internal supply voltage;wherein said reference circuit reduces said reference voltage when the semiconductor enters the sleep mode from an activated mode and returns said reference voltage to said activated mode level when the semiconductor returns to said activated mode;reducing the current flow to one or more diodes in said reference circuit when the semiconductor enters the sleep mode from said activated mode; andincreasing the current flow to said one or more diodes when the semiconductor reenters said activated mode from the sleep mode.