Patent ID: 7691704
Filing Date: 2010-04-06
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor substrate formed with a semiconductor device; sequentially forming a first interlayer insulating film and a second interlayer insulating film over the semiconductor substrate; etching the first interlayer insulating film and the second interlayer insulating film to form a plurality of trenches and a plurality of holes; simultaneously forming a lower line and a lower electrode by filling a metal material in the trenches and the holes; laminating a dielectric film and a third interlayer insulating film over the second interlayer insulating film; forming a plurality of vias holes and openings etching the third interlayer insulating film using a mask; filling a gap-fill film in the via holes and in the openings; etching the third insulating film and the gap-fill film in regions where the via holes are arranged, using a mask for defining a line region, to form a plurality of trenches; removing the gap-fill film and the dielectric film in regions exposed through the trenches, while removing the gap-fill film from the openings; and filling a metal material in the trenches and the via holes, and in the openings, planarizing the filled metal, to form a plurality of vias holes and an upper line connected to the lower line in the trenches and the via holes, and simultaneously forming a plurality of upper electrodes over the dielectric film in the openings.