Patent ID: 8972769
Filing Date: 2015-03-03
Classification: G06F,Y02D

Abstract:
1. A data processing apparatus including a plurality of data processing units communicably connected in a ring pattern and configured to process data according to input operation clocks in order, the data processing apparatus comprising: a processor for executing process steps, and a memory storing process steps executed by the processor, where the process steps cause the processor to function as: a measuring unit configured to measure response times of said plurality of data processing units in case that the operation clocks of a common frequency are supplied to said plurality of data processing circuits; a calculation unit configured to calculate frequency-to-response time ratios for respective data processing units, based on the response times measured by said measuring unit; a determination unit configured to determine a data processing unit with minimum frequency-to-response time ratio based on the frequency-to-response time ratios calculated by said calculation unit; and a controller configured to control each frequency of the operation clocks to be supplied to each data processing unit based on the minimum frequency-to-response time ratio.