Patent ID: 7362141
Filing Date: 2008-04-22
Classification: H03K

Abstract:
1. A logic device with low electromagnetic interference, comprising: a current mirror circuit, which is connected to a high potential and provides a first fixed current through a node; a digital logic gate, which provides a corresponding digital logic function; a voltage-limited circuit, which comprises a PMOS transistor and an NMOS transistor in a diode-connected form and is connected to the current mirror circuit and the digital logic gate via said node, and limits the voltage of node to a first fixed voltage in order to provide the first fixed voltage to the digital logic gate to thereby reduce an output voltage swing of the digital logic gate; and a current-limited circuit, which is connected to the current mirror circuit and the digital logic gate through the node in order to provide a second fixed current to the digital logic gate to thus reduce a transient current of the digital logic gate; wherein an electromagnetic interface (EMI) caused by switching of the digital logic gate is reduced by decreasing the output voltage swing and the transient current.