Patent ID: 6639326
Filing Date: 2003-10-28
Classification: H01L,Y10S

Abstract:
A full complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell comprising:first and second active regions formed in a semiconductor substrate, the first active region having an approximate â€œTâ€  shape; a word line traversing first and second areas of the second active region; first and second gate electrodes arranged to be perpendicular to the word line, wherein the first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively; a power line electrically connected to a first common source region and arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode; a ground line electrically connected to a second common source region and arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode; and first and second bit lines arranged to be perpendicular to the word line and parallel to each other.