Patent ID: 7898813
Filing Date: 2011-03-01
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a wiring board including a first main surface which has an element mounting portion, connection pads and a wiring layer, and a second main surface which is on an opposite of the first main surface; a first semiconductor memory element which is mounted on the element mounting portion of the wiring board and has first electrode pads; a second semiconductor memory element which is stacked on the first semiconductor memory element and has second electrode pads; metal wires which electrically connect the connection pads of the wiring board and the first and second electrode pads of the first and second semiconductor memory elements; and a sealing resin layer which is formed on the first main surface of the wiring board to seal the first and second semiconductor memory elements together with the metal wires, wherein the first main surface of the wiring board has a convex portion on the wiring layer, and the first semiconductor memory element is adhered to the first main surface of the wiring board via an adhesive layer, wherein the first semiconductor memory element has a thickness greater than that of the second semiconductor memory element, and wherein a sloped face is formed on ends of the wiring board and the sealing resin layer so that the first main surface of the wiring board is larger than the second main surface of the wiring board and an upper surface of the sealing resin layer is larger than the first main surface of the wiring board, and a side portion of the sealing resin layer is composed of a face perpendicular to the upper surface and the sloped face.