Patent ID: 7053441
Filing Date: 2006-05-30
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a column direction and a row direction, wherein the memory cell array further includes: a plurality of source line diffusion layers each of which is formed by connecting part of the memory cells in the row direction; a plurality of bitline diffusion layers; a plurality of isolation regions each of which divides one of the bitline diffusion layers; and a plurality of word gate common connection sections; wherein each of the memory cells includes one of the source line diffusion layers, one of the bitline diffusion layers, a channel region disposed between the source line diffusion layer and the bitline diffusion layer, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region; wherein each of the bitline diffusion layers is disposed between two of the word gates which are adjacent to each other in the column direction; wherein each of the word gate common connection sections is disposed above at least one of the isolation regions and connects the two adjacent word gates; and wherein a plurality of word gate wiring layers are formed above the word gate common connection sections, each of the word gate wiring layers is connected to at least one word gate interconnection which is connected to one of the word gate common connection sections.