Patent ID: 8169255
Filing Date: 2012-05-01
Classification: G05F

Abstract:
1. An offset cancellation current mirror comprising: a first current mirror comprising a first reference current input terminal, a first reference current output terminal, a first corresponding current input terminal, a first corresponding current output terminal, a first transistor, a second transistor, a first switch, a second switch, a first capacitor and a second capacitor, the first switch being connected between a gate of the first transistor and a drain of the first transistor, the second switch being connected between a gate of the second transistor and a drain of the second transistor, the first capacitor being connected between the drain of the first transistor and the gate of the second transistor, the second capacitor being connected between the gate of the first transistor and the drain of the first transistor, the source of the first transistor and the drain of the first transistor being connected to the first reference current input terminal and the first reference current output terminal respectively, and the source of the second transistor and the drain of the second transistor being connected to the first corresponding current input terminal and the first corresponding current output terminal respectively; a third switch comprising a first lower access point and a first upper access point connected to the first reference current output terminal; a fourth switch comprising a second lower access point and a second upper access point connected to the first corresponding current output terminal; a first resistor being connected between the first lower access point of the third switch and a grounding terminal; a second resistor being connected between the second lower access point of the fourth switch and the grounding terminal; a fifth switch comprising a third lower access point and a third upper access point connected to the first reference current output terminal; a sixth switch comprising a fourth lower access point and a fourth upper access point connected to the first corresponding current output terminal; and a second current mirror comprising a second reference current input terminal, a second reference current output terminal, a second corresponding current input terminal, a second corresponding current output terminal, a third transistor and a fourth transistor, a gate of the third transistor being connected to a gate of the fourth transistor and a drain of the third transistor, the second reference current input terminal being connected to a source of the third transistor and the third lower access point of the fifth switch, the second corresponding current input terminal being connected to a source of the fourth transistor and the fourth lower access point of the sixth switch.