Patent ID: 7739480
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A method of obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, the method comprising: providing a vector in a vector register file; and embedding a location identifier of the scalar value within the vector in bits comprising the mixed vector and scalar instruction, wherein the mixed vector and scalar instruction is defined according to an instruction format, the instruction format comprising an op code, a first source vector register address, a second source vector register address, a destination vector register address, and at least one dedicated position bit that indicates the location of the scalar value within one of the vector registers, and further comprising: defining the mixed scalar and vector instruction such that the at least one dedicated position bit is provided in a bit format of the instruction which provides the location identifier of the scalar value within the vector, and embedding the location identifier in the op code provided in the instruction.