Patent ID: 6369602
Filing Date: 2002-04-09
Classification: G01R,Y10T

Abstract:
A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising:providing at least one integrated circuit (IC) die, each IC die having interconnection bumps on a surface; providing a substrate having conductive pads deposited on a surface thereof for flip-chip attachment to said interconnection bumps of said at least one IC die; providing a plurality of probes for contacting said substrate; positioning said interconnection bumps in conductive contact with said conductive pads of said substrate to form said flip-chip semiconductor assembly; contacting said substrate with said plurality of probes; electrically testing said flip-chip semiconductor assembly using said plurality of probes; repairing said flip-chip semiconductor assembly and retesting if said flip-chip semiconductor assembly fails said electrical testing; speed grading said flip-chip semiconductor assembly; and sealing said at least one IC die to said flip-chip semiconductor assembly.