Patent ID: 6240010
Filing Date: 2001-05-29
Classification: G11C,H01L

Abstract:
A semiconductor memory cell comprising:(1) a first transistor for readout, having a first conductivity type, and having source/drain regions, a semi-conductive channel forming region which is in contact with the source/drain regions and spaces out the source/drain regions, and a gate capacitively coupled with the channel forming region,(2) a second transistor for switching, having a second conductivity type, and having source/drain regions, a semi-conductive channel forming region which is in contact with the source/drain regions and spaces out the source/drain regions, and a gate capacitively coupled with the channel forming region, and(3) an MIS type diode for retaining information, wherein:one source/drain region of the first transistor corresponds to the channel forming region of the second transistor,one source/drain region of the second transistor corresponds to the channel forming region of the first transistor, andone end of the MIS type diode is formed of an extending portion of the channel forming region of the first transistor, the other end of the MIS type diode is formed of an electrode composed of an electrically conductive material, and the electrode is connected to a line having a predetermined potential.