Patent ID: 7417469
Filing Date: 2008-08-26
Classification: G01R,G11C

Abstract:
1. A method for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits, said method comprising: coupling an automatic self-adaptive keeper to a Local Bitline (LBL) of an N-way register; coupling a dummy cell to the LBL, wherein the dummy cell is similarly configured to one way of the N-way register file: connecting a stage one current mirror (CM detecting current leakage from the N-way register file on the LBL using the dummy cell, wherein the dummy cell matches the leakage current detected on the LBL; reducing the leakage current effects by providing optimally controlled compensation current from the automatic self adaptive keeper; wherein the automatic self adaptive keeper comprises: a stage two current mirror (CM wherein the stage two current mirror operates in combination with the stage one current mirror to provide a two-stage current mirror; a feedback transistor connected at its drain to the LBL and at its source to the stage two current mirror; and a feedback (clock-controlled) NAND gate having a first input terminal that is connected to the LBL and a second input that is coupled to a delayed clock input, which is a delayed version of an input clock signal, wherein the feedback NAND gate further provides a NAND output that is connected to a gate terminal of the feedback transistor.