Patent ID: 6167416
Filing Date: 2000-12-26
Classification: G06F

Abstract:
In an integrated circuit device comprising a memory resource and a plurality of circuit stages, each one of said stages including a plurality of RADIX-2 elements, a method of efficient simultaneous operation of the RADIX-2 elements to enable a Fast Fourier Transform (FFT) calculation, the method comprising the steps of:dividing the memory resource into a plurality ""P"" of memory partitions;designating a selected circuit stage as a critical stage;assigning at least two of said memory partitions to each of the plurality of RADIX-2 elements utilized in a first stage, and repeating said assigning step for each stage up to but not including said critical stage; andassigning a single memory partition to each of the plurality of RADIX-2 elements utilized in said critical stage;said RADIX-2 elements utilized in said pre-critical stages each accessing said at least two of said memory partitions, thereby simultaneously operating a plurality of RADIX-2 elements to enable an FFT calculation;wherein P/2 RADIX-2 elements are utilized in said first stage and each said pre-critical stage.