Patent ID: 6434071
Filing Date: 2002-08-13
Classification: G11C

Abstract:
A precharge circuit configured for reading a data bit from a memory having at least two local bit lines, the precharge circuit comprising:a first precharge transistor connectable to a voltage source and a first local bit line of the memory for precharging the first local bit line, when the first precharge transistor is turned on; a first keeper transistor connectable to the voltage source and the first local bit line for keeping the first local bit line precharged, even after the first precharge transistor is turned off; a second precharge transistor connectable to the voltage source and a second local bit line of the memory for precharging the second local bit line, when the second precharge transistor is turned on; a second keeper transistor connectable to the voltage source and the second local bit line for keeping the second local bit line precharged, even after the second precharge transistor is turned off; and a NAND gate connectable to the first and second local bit lines for receiving the data bit from the memory, and connected to the first and second keeper transistors for switching the first and second keeper transistors.