Patent ID: 6482697
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of patterning a conductive layer buried in an inter-layer insulator, said method comprising the steps of:forming a dummy layer over a conductive layer; selectively forming a resist pattern over said dummy layer; carrying out an anisotropic etching process for patterning said dummy layer and said conductive layer by use of said resist pattern as a mask; removing said resist pattern; forming an inter-layer insulator so that said dummy layer and said conductive layer are completely buried within said inter-layer insulator; carrying out a first planarization process for polishing said inter-layer insulator; and carrying out a second planarization process for selectively etching said inter-layer insulator, so that at least a top portion of said dummy layer is etched; removing said dummy layer; carrying out a third planarization process for selectively etching said inter-layer insulator, so that a planarized surface of said inter-layer insulator is leveled to a planarized surface of said conductive layer, wherein said dummy layer has a higher etching selectivity to said inter-layer insulator than nitride.