Patent ID: 7188301
Filing Date: 2007-03-06
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: a top interleaver operably coupled to interleave at least some input bits of a plurality of input bits; a top constituent trellis encoder, communicatively coupled to the top interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the top interleaver; a bottom interleaver that is also operably coupled to interleave at least some input bits of the plurality of input bits; a bottom constituent trellis encoder, communicatively coupled to the bottom interleaver and operable to receive interleaved bits there from, that is operable to encode at least some input bits of the plurality of input bits that have been interleaved by the bottom interleaver; a multiplexor (MUX) that alternatively selects encoded bits that are output from the top constituent trellis encoder and the bottom constituent trellis encoder to produce multiplexed bits that are arranged in an order corresponding to the alternative selecting of encoded bits that are output from the top constituent trellis encoder and encoded bits that are output from the bottom constituent trellis encoder; a puncturing functional block that punctures a first plurality of bits of the multiplexed bits to produce a first encoded symbol and punctures a second plurality of bits of the multiplexed bits to produce a second encoded symbol; and a symbol mapper that maps the first encoded symbol according to a first rate control and the second encoded symbol according to a second rate control.