Patent ID: 6734720
Filing Date: 2004-05-11
Classification: H03F

Abstract:
An operational amplifier circuit comprising:an amplifier portion for receiving a non-inverting input and an inverting input and providing an amplified output in response to the differential between said non-inverting input and said inverting input; and a push-pull amplifier for providing a final output in response to said amplified output, said push-pull amplifier including: an NPN output transistor having its collector connected to a higher-potential conductor; a PNP output transistor having its collector connected to a lower-potential conductor; two serially connected resistors that are connected between emitters of said NPN and PNP output transistors, a node between said resistors serving as an output of the operational amplifier circuit; a PNP driving transistor having its base coupled with said amplified output and its emitter connected to a base of said NPN output transistor, a collector of said PNP driver transistor being connected to said lower-potential conductor; a first current source connected between said higher-potential conductor and an emitter of said PNP driving transistor; an NPN driving transistor having its base coupled with said amplified output and its emitter connected to a base of said PNP output transistor, a collector of said NPN driver transistor being connected to said higher-potential conductor; a second current source connected between said lower-potential conductor and an emitter of said NPN driving transistor; and a current reducing circuit for reducing a through current flowing through said NPN and PNP output transistors, wherein said current reducing circuit comprises; a first resistor inserted between said higher-potential conductor and said first current source; a second resistor inserted between said second current source and said lower-potential conductor; an NPN transistor which is so connected with said NPN output transistor as to constitute a first current mirror and which has its emitter connected to a node between said second current source and said second resistor; and a PNP transistor which is so connected with said PNP output transistor as to constitute a second current mirror and which has its emitter connected to a node between said first resistor and said first current source.