Patent ID: 6274441
Filing Date: 2001-08-14
Classification: H01L

Abstract:
A method of fabricating a MOSFET device for a DRAM cell on a P-type semiconductor substrate including a halo implant region in said MOSFET device, comprising:providing a semiconductor substrate, a gate insulator layer over said semiconductor substrate, a conductor layer comprising polysilicon, an overlying silicide layer over said conductor layer, and an insulating cap over said silicide layer;patterning and etching said silicide layer and said insulating cap to expose a portion of the polysilicon conductor layer;providing insulating spacers comprising spacer material along sides of the patterned silicide layer and insulating cap;etching the resulting exposed portion of the polysilicon conductor layer;implanting node and bitline N-type diffusion regions to a first concentration;patterning a photoresist layer to protect the node diffusion region and expose the bitline diffusion region;etching resulting exposed spacer material from the side of said silicide layer and insulting cap;implanting a P-type impurity halo implant into the resulting exposed bitline diffusion region; andstripping the photoresist layer and providing an insulting spacer comprising spacer material along the exposed side of said silicide layer and insulting cap.