Patent ID: 6834327
Filing Date: 2004-12-21
Classification: G06F

Abstract:
A unified tag subsystem for a multilevel cache memory system having an upper level and a lower level of cache data memory, the tag subsystem having at least a processor port for receiving a cache line address comprising a tag index portion, and a high order part, the unified tag subsystem comprising:a unified tag memory coupled to be addressed by the tag index portion of the cache line address, the tag memory comprising at least one way-specific address tag, at least one upper level valid flag, and at least one way-specific lower level flag; at least one first comparator coupled to compare the high order part with the at least one way-specific address tag and detect a match; a lower level hit logic coupled to determine a lower level cache hit when the at least one first comparator detects a match, and the lower level flag of the tag memory indicates a valid entry in the lower cache; and an upper level hit logic coupled to determine a higher level cache hit when the at least one first comparator detects a match, and a high level valid flag of the tag memory is in a valid state.