Patent ID: 8934301
Filing Date: 2015-01-13
Classification: G06F,G11C

Abstract:
1. In a memory system including a memory controller controlling a nonvolatile memory device having a memory cell array of multi-level memory cells (MLC), wherein the memory system includes an error correcting circuit (ECC) generating parity data capable of correcting “Q” erroneous bits in read data retrieved from the memory device, where Q is a natural number, a correction method, comprising: retrieving first read data from a plurality of the MLC commonly coupled to a word line in response to a read command; determining whether or not the first read data is correctable in view of first parity data generated by the ECC from the first read data; upon determining that the first read data is not correctable, reading second read data from the plurality of the MLC and obtaining error information for the second read data in view of second parity data generated by the ECC from the second read data; comparing error information obtained for the first read data with the error information for the second read data; and modifying at least one erroneous bit in the first read data based on said comparison of the error information for the second read data and the error information for the first read data.