Patent ID: 7127691
Filing Date: 2006-10-24
Classification: G01R,G06F

Abstract:
1. A computer-implemented method for manufacturing test generation, comprising: determining inputs and outputs of a first logic block of a digital logic design, the first logic block not yet having logic designed that internally connects the inputs and the outputs within the first logic block; creating an output file for the first logic block including inserting scanable logic within the at least one logic block, the scanable logic internally connecting the inputs and the outputs to permit the first logic block to be testable, wherein the scanable logic inserted into the first logic block comprise a latch for each non-clock input pin and each non-clock output pin; and scanable latches for signals of the first logic block being fed or feeding other logic block of the digital logic design; and testing a second logic block coupled to the inputs or the outputs of the first logic block utilizing the output file to determine manufacturing test structure violations associated with the second logic block or the first logic block.