Patent ID: 7087958
Filing Date: 2006-08-08
Classification: H01L

Abstract:
1. A trenched DMOS device having a termination structure, the trenched DMOS device comprising: a silicon substrate of a first conductive type, having a first epitaxial layer of the first conductive type and a second epitaxial layer of a second conductive type formed thereon; a DMOS trench, formed in the first epitaxial layer and the second epitaxial layer; a first trench, formed in the first epitaxial layer and the second epitaxial layer disposed close to an edge of the second epitaxial layer, the first trench to be utilized as a main portion of the termination structure having a bottom disposed in the first epitaxial layer; a second trench disposed between the DMOS trench and the first trench, the second trench having another bottom disposed in the second epitaxial layer adjacent to a region of the second conductive type; a gate oxide layer on the DMOS trench and the first trench, the gate oxide layer having extended portions covering an upper surface of the second epitaxial layer adjacent the DMOS trench and of the second epitaxial layer adjacent the first trench; a first polysilicon layer, formed in the DMOS trench; a second polysilicon layer, formed over the gate oxide layer in the first trench, having another extended portion covering the upper surface of the second epitaxial layer adjacent the first trench, the second polysilicon layer having an opening to expose the gate oxide layer disposed at the bottom of the first trench to split the second polysilicon layer into two discrete parts; an isolation layer, formed on the first polysilicon layer in the DMOS trench and extended portions of the gate oxide layer adjacent the DMOS trench, on the second polysilicon layer, and on the gate oxide layer over the second epitaxial layer at the bottom of the first trench, the isolation layer having a first contact window to expose the second polysilicon layer over the second epitaxial layer and a second contact window to expose the second trench; and a source metal contact layer, formed over the isolation layer and filling both the first contact window and the second contact window, having a connection with a source of the DMOS device and further having an edge beside the first contact window.