Patent ID: 6184078
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method for fabricating a capacitor for a high density dynamic random access memory (DRAM) device on a semiconductor substrate having a buried contact pad formed thereon within a first insulator layer, comprising:forming a second insulator layer on the first insulator layer, including on the buried contact pad;forming a third insulator layer on the second insulator layer;forming an etching stopper layer on the third insulator layer;sequentially forming a fourth insulator layer and a first polysilicon layer on the etching stopper layer;forming a masking layer on the first polysilicon layer to define a storage node;sequentially etching the first polysilicon layer and the fourth insulator layer, using the masking layer as a first mask, until the etching stopper layer is exposed, to form a top via hole;forming a sidewall spacer on an interior sidewall of the top via hole;removing the masking layer;etching the etching stopper layer and the second and third insulator layers, using a combination of the first polysilicon layer and the sidewall spacer as a second mask, until the buried contact pad is exposed, to form a bottom via hole beneath the top via hole; depositing a second polysilicon layer to fill the bottom and top via holes;planarizing the first polysilicon layer until the fourth insulator layer is exposed; andetching the fourth insulator layer to form the storage node of said capacitor.