Patent ID: 6606673
Filing Date: 2003-08-12
Classification: G06F,G09G

Abstract:
A direct memory access transfer apparatus, in which pieces of pixel data are transferred between a sender's memory, to which the accessing of pieces of pixel data is possible at one time, a receiver's memory to which the accessing of pieces of pixel data is possible at one time, comprising:a group of transfer parameter registers for storing a plurality of parameters required to transfer pieces of pixel data both the sender's memory and the receiver's memory; a sender-memory control unit for producing a plurality of two-dimensional readout addresses of the sender's memory according to the parameters stored in the group of transfer parameter registers and reading out pieces of pixel data corresponding to pixels arranged on a plurality of lateral lines of a rectangular area from the sender's memory according to the two-dimensional readout addresses of the sender's memory; a data transforming unit for performing a sub-sampling for the pieces of pixel data of each lateral line read out from the sender's memory by the sender-memory control unit at a sample ratio of n:1 (n is an integral number higher than 1) and outputting pieces of sub-sampled pixel data corresponding to each lateral line; a receiver-memory control unit for producing a plurality of two-dimensional write addresses of the receiver's memory according to the parameters stored in the group of transfer parameter registers and write the pieces of sub-sampled pixel data of the lateral lines produced by the data transforming unit in the two-dimensional write addresses of the receiver's memory; and a timing control unit for controlling a processing timing of the sender-memory control unit, a processing timing of the data transforming unit and a processing timing of the receiver-memory control unit.