Patent ID: 6476652
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising:a delay model for delaying an external clock signal to generate a delayed clock signal; a signal generation means, responsive to the external clock signal and the delayed clock signal, for generating control signals, an internal clock signal, and a delayed internal clock signal; a first delay means, responsive to the control signals, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means has a first amount of delay time; and a second delay means, responsive to the control signals, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has a second amount of delay time, the second amount of delay time being shorter than the first amount of delay time, wherein the signal generating means includes: a control means, response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signals include a shift signal, a replication signal and a replication enable signal; a first oscillation means, responsive to the internal clock signal and the delayed internal clock signal, for generating a measurement oscillating signal; and a second oscillation means, responsive to the replication signal and the replication enable signal, for generating a replication oscillating signal.