Patent ID: 6240020
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A method of bitline shielding for a precharging scheme for a flash memory device comprising:a flash memory device including a plurality of core cell blocks and a plurality of page buffers, each of said core cell blocks containing a plurality of flash memory cells, each of said plurality of page buffers in communication with a fraction of said plurality of core cell blocks via a unique bitline of a plurality of bitlines, said bitlines containing a first set of bitlines and a second set of bitlines and arranged such that at least one of said second set of bitlines disposed between each of said first set of bitlines, the method comprising:charging said first set of said bitlines to a first preset voltage during a first portion of a precharge cycle;charging said second set of said bitlines to a second preset voltage during a second portion of said precharge cycle, said second portion of said precharge cycle concurrent with a fraction of and not greater than said first portion of said precharge cycle; andevaluating a logic state of at least one of said flash memory cells during said precharge cycle after each of said first set of bitlines has attained said first preset voltage, each of said at least one of said flash memory cells connected with a unique bitline contained in said first set of bitlines.