Patent ID: 6697931
Filing Date: 2004-02-24
Classification: G06F

Abstract:
A computer system including a microprocessor on a single integrated circuit chip having on-chip circuitry comprising a CPU with a plurality of registers and at least one other module, said integrated circuit chip further comprising a communication bus providing a parallel communication path between said CPU and said at least one other module, said at least one other module having logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said at least one other module being operable to receive the packets and respond thereto independently of operation of the CPU, wherein said digital data packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination, said integrated circuit chip further comprising an external communication port connected to said bus, said external communication port having an internal signal connection to said bus and having translation circuitry and an external signal connection, said internal signal connection having an internal parallel format for said digital data packets including said control bits, said external signal connection having an external parallel format for said digital signal packets including said control bits, said external parallel format having a lesser bit width than said internal parallel format, and said translation circuitry to effect translating of digital signal packets between said internal and external formats, wherein said translating provides a one-to one correspondence between data of said internal and external formats, said external communication port being operable independently of operation of said CPU.