Patent ID: 6671844
Filing Date: 2003-12-30
Classification: G11C

Abstract:
A method of simultaneously testing multiple DUT's using a single test site in a memory tester, the method comprising the steps of:(a) contacting the multiple DUT's with probes corresponding to channels within the single test site; (b) associating a collection of channels with each DUT in the multiplicity thereof; (c) defining for each channel a primary format for applying transmit vectors and interpreting receive vectors, each channel's primary format for use initially and in the absence of detected errors for that channel, and also an alternate format for applying transmit vectors and interpreting receive vectors, each channel's alternate format for use subsequent to there being detected selected error criteria for that channel; (d) generating with a test program a sequence of transmit vectors and expected receive vectors and applying the transmit vectors to the channels associated with all DUT's in the multiplicity thereof, each channel using the primary format associated therewith; (e) comparing a receive vector actually received from the DUT with an expected receive vector and determining that a channel is a non-comparing channel; (f) pursuant to step (b) and in response to step (e), generating an indication that the DUT within the multiplicity thereof, and with which the non-comparing channel is associated, has met selected error criteria and is to be disabled; and (g) subsequent to step (f), using for the non-comparing channel the alternate format associated with that non-comparing channel.