Patent ID: 6489822
Filing Date: 2002-12-03
Classification: G11C,H03L

Abstract:
A delay locked loop for use in a semiconductor memory device, which comprises:a delay means for delaying a clock signal fed hereto to produce a time delayed signal; a comparing means for comparing the time delayed signal from the delay means and a reference signal, determining from the comparison whether an increase or decrease of the time delay is to be requested, and producing a corresponding add request or subtract request signal; and a delay control means for counting add request and subtract request signals and providing a control signal to the delay means after the count of add request or subtract request signals reaches a predetermined value, the control signal causing he delay means to increase or decrease the time delay, wherein the delay control means includes: an addition/subtraction determination means, responsive to the add request and subtract request signals from the comparing means, for generating the control signal that causes the delay means to increase or decease the time delay; and a reset signal generation means for producing a reset signal for initializing the addition/subtraction determination means upon providing the control signal to the delay means.