Patent ID: 8543767
Filing Date: 2013-09-24
Classification: G06F

Abstract:
1. A computer system comprising: a memory; a first core having a first cache and configured to process an application; a coherency bus connecting the first core to the memory and to a second core, the coherency bus configured to make visible to a cache controller of the second core a sequence of addresses of the application that miss the first cache in the first core; an input queue mapped to the memory for storing, by the cache controller, the sequence of addresses; instructions, stored in the second core, for generating prefetch addresses from the input queue; instructions, stored in the second core, for issuing prefetch requests to the memory for the prefetch addresses; instructions, stored in the second core, for storing the prefetch addresses in an output queue mapped to the memory; and instructions, stored in the second core for providing, responsive to a request by the first core for an address corresponding to a prefetch address, prefetch data associated with the prefetch address to a second cache in the second core, wherein the first core retrieves the prefetch data from the second cache via the coherency bus.