Patent ID: 7257786
Filing Date: 2007-08-14
Classification: G06F

Abstract:
1. A computing environment comprising a computer program, the computer program for solving constraints during functional verification of a representation of an electronic design of an integrated circuit (IC), the computer program comprising the following steps when executed by a data processing system: selecting a first set of block-related constraints, from a first set of constraints, according to a first block; identifying a first set of non-block-related constraints, from the first set of constraints, not selected for the first set of block-related constraints; conjoining the first set of block-related constraints to produce a first solution generator; existentially quantifying the first block from the first solution generator to produce a first new constraint; computing a union of the first new constraint and the first set of non-block-related constraints to produce a second set of constraints; selecting a second set of block-related constraints, from the second set of constraints, according to a second block; conjoining the second set of block-related constraints to produce a second solution generator; solving the second solution generator; and solving the first solution generator using a second result of solving the second solution generator.