Patent ID: 8089101
Filing Date: 2012-01-03
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a gate electrode level region that forms part of an overall gate electrode level of the integrated circuit, the gate electrode level region including at least three linear-shaped conductive structures each formed to extend lengthwise in a first direction, the at least three linear-shaped conductive structures positioned in a side-by-side spaced apart manner, wherein side-by-side ones of the at least three linear-shaped conductive structures are spaced apart from each other in a second direction perpendicular to the first direction in accordance with a substantially equal centerline-to-centerline pitch as measured in the second direction, and wherein at least two side-by-side ones of the at least three linear-shaped conductive structures are electrically connected to each other through one or more conductive structures formed within a level of the integrated circuit other than the gate electrode level.