Patent ID: 7684256
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A flash memory device comprising: a first memory group having a plurality of memory strings; a second memory group having the same structure as that of the first memory group; and a page buffer group having the same number of page buffers as the number of the memory strings of the first memory group or the number of memory strings of the second memory group, wherein one memory string of the first memory group and one memory string of the second memory group are oppositely connected to a corresponding page buffer of the page buffer group; a plurality of first switching elements respectively connected to the plurality of memory strings in the first memory group, wherein the first switching elements are configured to supply a power supply voltage to the plurality of the memory strings in the first memory group according to a first signal; a plurality of second switching elements connected between the page buffer group and the plurality of memory strings in the first memory group, wherein the second switching elements are configured to turned on or off in response to a second signal; a plurality of third switching elements respectively connected to the plurality of memory strings in the second memory group, wherein the third switching elements are configured to supply the power supply voltage to the plurality of memory strings in the second memory group according to a third signal; and a plurality of fourth switching elements connected between the page buffer group and the plurality of memory strings in the second memory group, wherein the fourth switching elements are configured to turned on or off in response to a fourth signal.