Patent ID: 6856558
Filing Date: 2005-02-15
Classification: H03H,H03K

Abstract:
1. An integrated circuit system, comprising: a first integrated circuit chip that is configured to generate data and strobe signals at outputs thereof; and a second integrated circuit chip that receives the data and strobe signals and latches a buffered version of the data signal in-sync with leading edges of a pair of complementary strobe signals that are derived from a delayed timing signal, said second integrated circuit chip having a delay device therein that comprises a digital delay line having a plurality of injection ports, said digital delay line configured to generate the delayed timing signal by adding at least a percent-of-clock period delay to a timing signal that is derived from the strobe signal and accepted at an enabled one of the plurality of injection ports of the digital delay line, and further configured to be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports.