Patent ID: 6365932
Filing Date: 2002-04-02
Classification: H01L

Abstract:
A power MOS transistor comprising:a buried semiconductor layer of a first conductivity type; a surface side semiconductor layer of the first conductivity type, formed on the buried semiconductor layer, and having an impurity concentration lower than that of the buried semiconductor layer; a channel region of a second conductivity type, defined in a surface portion of the surface side semiconductor layer; a source region of the first conductivity type, formed in a surface portion of the channel region; a gate electrode disposed on at least a part of the channel region in the surface side semiconductor layer with a gate insulation film interposed therebetween; a deep drain region of the first conductivity type, formed in at least the surface of the surface side semiconductor layer; and a base region of the second conductivity type, formed in the surface portion of the surface side semiconductor layer to partly overlap with the deep drain region, the base region being connected to a source side to define a surge bypassing diode between the source side and a drain side.