Patent ID: 8174908
Filing Date: 2012-05-08
Classification: G11C

Abstract:
1. A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, the method comprising: storing a first bit data to be programmed in a multi level cell of a first latching circuit in the page buffer; transmitting the first bit data stored in the first latching circuit to a second latching circuit in the page buffer; programming the first bit data stored in the first latching circuit to the multi level cell; verifying the programming of the first bit data through a first node or a second node in the second latching circuit in accordance with a verifying voltage; storing a second bit data to be programmed in the multi level cell of the first latching circuit when the verifying of the programming of the first bit data passes; reading the first bit data stored in the multi level cell and inverting the read data from the multi level cell and storing the inverted data for the verifying operation in the second latching circuit; programming the second data stored in the first latching circuit to the multi level cell; and verifying the programming of the second bit data through the first node or the second node in the second latching circuit in accordance with a verifying voltage.