Patent ID: 8933739
Filing Date: 2015-01-13
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: a first clock signal transmission line configured to transmit a clock signal; a second clock signal transmission line configured to transmit a complementary clock signal of the clock signal; a clock amplifier circuit configured to output the clock signal and the complementary clock signal after amplifying signal levels thereof; a clock level adjustment circuit configured to supply the clock signal and the complementary clock signal to succeeding clock signal transmission lines after reducing amplitudes thereof amplified in the clock amplifier circuit; a first data transmission line configured to transmit data; a second data transmission line configured to transmit complementary data of the data; a data amplifier circuit configured to amplify and output the data and the complementary data; and a data level adjustment circuit configured to supply the data and the complementary data to succeeding data transmission lines after reducing amplitudes thereof amplified in the data amplifier circuit.