Patent ID: 6753215
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, the method comprising the steps of:(a) forming a gate dielectric layer on a semiconductor layer; (b) forming a first conductive layer having a specified pattern on the gate dielectric layer; (c) forming sidewall insulation layers on side walls of the first conductive layer; (d) forming a source region and a drain region in the semiconductor layer; (e) depositing a first insulation layer that covers the first conductive layer and the sidewall insulation layers, the first insulation layer comprising a material different from that of the sidewall insulation layers; (f) planarizing the first insulation layer until an upper surface of the first conductive layer is exposed; (g) removing a part of the first conductive layer between the sidewall insulation layers in a manner that the gate dielectric layer is not exposed to thereby form a recessed section on the first conductive layer between the sidewall insulation layers; (h) partially filling the recessed section between the sidewall insulation layers with a second conductive layer to form a gate electrode that includes at least the first conductive layer and the second conductive layer; (i) forming a second insulation layer that fills the recessed section between the sidewall insulation layers on the second conductive layer, the second insulation layer comprising a material different from that of the first insulation layer; j) etching the first insulation layer to form a first through hole that reaches the source region or the drain region; and (k) forming a first contact layer in the first through hole.