Patent ID: 6314106
Filing Date: 2001-11-06
Classification: H04L

Abstract:
In a data switching system having a plurality of switching controllers for exchanging data units over a backplane, at least one controller having an interface for transmitting data on the backplane and an interface having a plurality of ports for receiving data off the backplane in parallel from all transmitting interfaces, wherein at least one port is assigned a different clock cycle within a repetitive timing cycle for initiating the release of a data unit to a queue, and wherein at least one data unit must pass a filtering check and a watermark check to receive queueing clearance, a method for conducting receive processing, comprising:sequencing the data units for conducting the filtering check;conducting the filtering check on the data units in accordance with the sequence;conducting the watermark check on the data units;filtering the data units which fail the filtering check;delaying the data units which pass the filtering check and fail the watermark check, until the watermark check is passed; andqueueing the data units which pass the filtering check and the watermark check,wherein the step of sequencing the data units comprises:(a) determining the ports on which the data units were received;(b) determining the current clock cycle within a repetitive timing cycle;(c) from the determinations in (a) and (b), assigning a priority to at least one data unit as a function of the number of clock cycles the data unit's port would have to wait before initiating the release of the data unit in the event queueing clearance for the data unit were received; and(d) sequencing the data units in accordance with their assigned priorities, andwherein a data unit is assigned the lowest priority if the number of clock cycles the data unit's port would have to wait exceeds a threshold number, and wherein data units assigned the same priority are sequenced in accordance with their ports.