Patent ID: 7663515
Filing Date: 2010-02-16
Classification: H04L

Abstract:
1. A high-speed serial interface circuit comprising: a data receiver circuit that receives differential-signal serial data transferred through differential data signal lines, and outputs received serial data; a clock signal receiver circuit that receives differential clock signals transferred through differential clock signal lines, and outputs a received clock signal; a logic circuit block that includes at least a serial/parallel conversion circuit, the serial/parallel conversion circuit sampling the received serial data from the data receiver circuit based on a sampling clock signal generated using the received clock signal from the clock signal receiver circuit, and converting the sampled received serial data into parallel data; a free-running clock signal generation circuit that generates a free-running clock signal, and outputs the generated free-running clock signal; a clock signal detection circuit that compares the received clock signal from the clock signal receiver circuit with the free-running clock signal from the free-running clock signal generation circuit to detect whether or not the clock signals are transferred through the differential clock signal lines; and an output mask circuit that masks an output signal from the logic circuit block to prevent the output signal from being transmitted to a circuit in a subsequent stage when the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines.