Patent ID: 8208234
Filing Date: 2012-06-26
Classification: H01L,H02H,H03K

Abstract:
1. A circuit with ESD protection for a switching regulator, comprising: a non-overlap circuit, having a first output terminal and a second output terminal, the first output terminal outputting a signal of default A and the second output terminal outputting a signal of default B; a power P-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the first output terminal of the non-overlap circuit and receiving the signal of default A outputted from the first output terminal of the non-overlap circuit; a diode, electrically connected to the source terminal and the drain terminal of the power P-type MOS device, used for providing a pathway for an electrostatic discharge; a digital logic AND gate, having two input terminals and a output terminal, one of the input terminals electrically connected to the second output terminal of the non-overlap circuit and receiving the signal of default B from the second output terminal of the non-overlap circuit, the other one of the input terminals receiving a EN signal, the output terminal providing a output signal of the digital logic AND gate; a power N-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the output terminal of the digital logic gate of AND gate and receiving the output signal of the digital logic AND gate, the drain terminal electrically connected to the drain terminal of the power P-type MOS device, the source terminal electrically connected to a ground; a Lx pin, electrically connected to the drain terminal of the power P-type MOS device and the drain terminal of the power N-type MOS device, used for outputting a converted voltage; and an ESD protection cell, having two terminals, one terminal electrically connected to the drain terminal of the power P-type MOS device and the other terminal electrically connected to the ground, used for protecting the power P-type MOS device and the power N-type MOS device while the electrostatic discharge appears.