Patent ID: 8009473
Filing Date: 2011-08-30
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array comprising a cell array having a plurality of cell blocks, each cell block comprising source lines, word lines and overlapping word lines arranged in the same direction, bit lines arranged in a direction perpendicular to the word lines, and a plurality of memory cells having a corresponding plurality of floating bodies, wherein adjacent memory cells of the plurality of memory cells, which are adjacent in a bit line direction, share source regions or drain regions to form common source regions or common drain regions, respectively, the source regions being arranged in a word line direction and connected to corresponding source lines, and the drain regions being arranged in the bit line direction and connected to corresponding bit lines, wherein gates of the memory cells are arranged in the word line direction and are connected to form the word lines, wherein the word lines are formed at a word line layer, the source lines are formed at a source line layer over the word line layer to be insulated from the word lines, the bit lines are formed at a bit line layer over the source line layer to be insulated from the word lines and the source lines, and the overlapping word lines are formed at an overlapping word line layer over the bit line layer and overlap the word lines in a word line direction.