Patent ID: 6407462
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A semiconductor die having an active region in a first substantially square section having four edges, the first substantially square section defining two diagonal lines, the die comprising:a first plurality of solder bump pads on the active surface arranged in the form of a grid comprising a plurality of rows and a plurality of columns, wherein the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows, wherein the plurality of columns are separated by a distance D, and wherein each of a first group of solder bump pads in a first row is separated from an adjacent solder bump pad in the first row by a distance 2D such that the first group of solder bump pads is disposed along a first plurality of columns, and wherein each of a second group of solder bump pads in a second row, which is adjacent to the first row, is separated from an adjacent solder bump pad by the distance 2D such that the second group of solder bump pads is disposed along a second plurality of columns, wherein each of the second plurality of columns is adjacent to, and in between, two of the first plurality of columns; and a plurality of core solder bumps corresponding to core power and core ground disposed within a second substantially square section centered within the first substantially square section and defined by four edges aligned substantially parallel to the four edges of the first substantially square section, the core solder bumps arranged in a grid with rows and columns separated from each other by a distance 2D.