Patent ID: 6656807
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A method of fabricating a semiconductor device comprising the steps of:forming first and second regions of a first conductivity type in a substrate of a second conductivity type; forming a grooved gate having at least a length formed in a groove located in said substrate between said first and second regions; said grooved gate having sidewall portions and a bottom portion, wherein said bottom portion is connected to said sidewall portions by bottom corners, and a channel located in said substrate along said entire groove length including along said groove gated sidewall and said bottom portions; and forming a doped region of said first conductivity type in said channel at said bottom portion and said bottom corners of said grooved gate where Vt within said channel at said bottom portion and bottom corners is substantially less than Vt within said channel at said sidewall portions, such that said sidewall portions predominantly control electric current through the device, wherein said first and second regions of the first conductivity type comprise a source and drain region that abut a portion of said channel, and said channel has a center region between the source and drain, and the doped region of said first conductivity type extends across a portion of the center region but does not extend to the source and drain.