Patent ID: 6630368
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising:providing a substrate body having at least adjacent first and second chip mounting regions on a surface thereof, and further having a dicing line between the first and second chip mounting regions; forming a first plurality of inner electrodes aligned along a first side of the first chip mounting region; forming a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; forming an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connected wiring portions, and wherein at least a first part of said interconnect wiring pattern extends obliquely across the dicing line along a first direction and at least a second part of said interconnect wiring pattern extends obliquely across the dicing line along a second direction different than the first direction, so that the first and second parts of said interconnect wiring pattern intersect each other at the dicing line; and dicing the substrate body and the interconnect wiring pattern along the dicing line.