Patent ID: 6704759
Filing Date: 2004-03-09
Classification: G06T

Abstract:
A method of compression and decompression of an input signal in a digital device comprising the steps of:receiving the input signal and a control signal at a processor engine having a pre-processor, a post-processor, and a distributed arithmetic processor; configuring the processor engine to function in a predetermined way in response to receipt of the control signal; pre-processing the input signal to establish a pre-processed signal upon receipt of the input signal at the pre-processor; processing the pre-processed signal with the distributed arithmetic processor upon receipt of the pre-processed signal to establish a processed signal; post-processing the processed signal to establish a post-processed signal; transmitting the post-processed signal from the processor engine; and wherein the step of configuring the processor engine further comprises the step of enabling the distributed arithmetic unit to selectively function in one of a DCT mode, an IDCT mode, and a FIR filter mode.