Patent ID: 6642598
Filing Date: 2003-11-04
Classification: H01L,Y10S

Abstract:
A semiconductor device having a plurality of function macro formation regions on the principal face of a semiconductor substrate, the plurality of said function macro formation regions include at least a first function macro formation region where a first function macro is formed and a second function macro formation region where a second function macro different from said first function macro is formed, each of said function macro formation regions has an element formation region where an element is formed, a plurality of dummy semiconductor regions where no element is formed and isolation trenches which isolate mutually between said element formation region and the plurality of dummy semiconductor regions, said dummy semiconductor regions in said function macro formation region have mutually identical plane shape and identical area, and the area of the first dummy semiconductor region included in said first function macro formation region and the area of the second dummy semiconductor region included in said second function macro formation region are different.