Patent ID: 6448852
Filing Date: 2002-09-10
Classification: H01L,H03F,H04R

Abstract:
A compact integrated circuit transient voltage multiplier for increasing the voltage of input pulses, comprising:a plurality of switching transistors; at least one capacitor comprising a silicon dioxide dielectric layer less than about 200 Angstroms in thickness sandwiched between a conductive polysilicon layer and an n-type doped surface region disposed in a conductive p-substrate region; and electrical connections between said transistors and said capacitors; wherein said switching transistors charge said capacitors to a voltage value substantially below the tunneling voltage of said dielectric layer and said capacitors are biased so that said n-type doped surface region forms a reverse-biased varactor diode with the p-substrate, said switching transistors acting so that the voltage of the input pulses is increased by a voltage contribution from each said capacitor.