Patent ID: 7870429
Filing Date: 2011-01-11
Classification: G01R,G06F

Abstract:
1. A control apparatus comprising: an operator including a pair of processor cores connected to a boundary scan bus, and adapted to mutually diagnose opponent processor cores in between; a memory configured to store therein data and programs to be executed by the operator; an I/O interface configured for input and output signals to be processed for associated processes in the operator; and a normal bus configured for normal connections among the operator, the memory, and the I/O interface, wherein a boundary scan test to be performed to the second generalized processor core, through the boundary scan bus, by and from the first intra-processor circuit having the first boundary scan control program sampled therefor, and a boundary scan test to be performed to the first generalized processor core, through the boundary scan bus, by and from the second intra-processor circuit having the second boundary scan control program sampled therefor, depending on a diagnosis request command received from the first intra-processor circuit, through the normal bus, in accordance with a setting of the control pattern.