Patent ID: 6815990
Filing Date: 2004-11-09
Classification: H03L

Abstract:
An integrated circuit device, comprising:at least one delay element; and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal and is further configured to block at least one periodic adjustment of the delay of the at least one delay element in response to detecting an excessive jitter of the first clock signal, said control circuit comprising: a phase detector that is configured to generate an up/down control signal in response to a feedback clock signal and the first clock signal; a phase window detection circuit that is configured to generate an active out-of-window signal in response to detecting an excessive phase difference between the feedback clock signal and the first clock signal; and an abrupt jitter decision circuit that is configured to generate an active halt signal in response to the active out-of-window signal. said abrupt jitter decision circuit comprising a first flip-flop having an input electrically coupled to an output of said chase window detection circuit, a second flip-flop, and an isolation circuit electrically coupled between an output of said first flip-flop and an input of said second flip-flop.