Patent ID: 6397273
Filing Date: 2002-05-28
Classification: G06F

Abstract:
A mechanism for use in a pipeline of a host-storage system interface to global memory, said mechanism processing information as data and control information, said mechanism comprising:a data assembler/disassembler; at least one protocol engine receiving information going to said global memory and stripping control information from said information, said protocol engine receiving data from said global memory and adding control information thereto; first data FIFOs receiving data from said protocol engine and transferring said data on a write operation to said global memory; second data FIFOs receiving data on a read operation from global memory and transferring said data to said protocol engine; an enhanced parity mechanism operable to generate a pseudo-random number for said data element such that parity accompanying data transferred from said first data FIFO is exclusive-ORed with LFSR (Linear Feedback Shift Register) data generated by enhanced parity circuitry in said assembler/disassembler to effectively check parity for the data; and at least one dual port RAM receiving said control information from said protocol engine on a write operation to said global memory.