Patent ID: 8897064
Filing Date: 2014-11-25
Classification: G11C

Abstract:
1. A monolithic three-dimensional integrated circuit, comprising: a three-dimensional memory array including a first layer of memory cells and a second layer of memory cells, the first layer of memory cells includes a first memory cell, the second layer of memory cells includes a second memory cell, the first memory cell is located above the second memory cell, the second memory cell is located above a substrate, the first memory cell and the second memory cell are formed above the substrate without any intervening substrates between the first memory cell and the second memory cell; and supporting circuitry in communication with the three-dimensional memory array, the supporting circuitry generates a plurality of bit line voltage options associated with a programming operation, the supporting circuitry determines a state associated with the first memory cell and determines an upper current threshold based on the state, the supporting circuitry selects a first bit line voltage of the plurality of bit line voltage options based on whether an output current associated with the first memory cell is greater than the upper current threshold, the supporting circuitry causes the programming operation to be performed to the first memory cell, the first bit line voltage is applied to the first memory cell during the programming operation.