Patent ID: 6534810
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A semiconductor memory device, comprising:an active matrix formed on a semiconductor substrate, the active matrix comprising a transistor formed on the semiconductor substrate and isolation regions for isolating the transistor, the transistor comprising a gate insulator formed on the semiconductor substrate, a gate electrode formed on the gate insulator and two diffusion regions positioned on opposite sides of the gate electrode; a first metal pattern including a leading pad connected to the transistor and extended over an isolation region and a bit line, wherein the bit line is electrically connected to one of the diffusion region and the leading pad electrically connected to the other diffusion region; a capacitor, the capacitor being positioned above and generally vertically aligned with the transistor; a barrier layer formed on the capacitor; and a second metal pattern, the second metal pattern being connected to the capacitor and the leading pad, thereby forming an electrical connection between the capacitor and the transistor.