Patent ID: 6069037
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method of manufacturing embedded DRAM, comprising the steps of:providing a semiconductor substrate having a field oxide layer and a first gate oxide layer thereon, wherein the semiconductor substrate includes a memory circuit region and a logic circuit region;forming a first polysilicon layer and an etching barrier layer over the semiconductor substrate;removing the etching barrier layer, the first polysilicon layer and the first gate oxide layer above the memory circuit region;forming a second gate oxide layer over substrate in the memory circuit region;forming a second polysilicon layer, a tungsten silicide layer and a silicon nitride layer above the second gate oxide layer and the etching barrier layer;forming a memory gate pattern and a logic gate pattern over the substrate structure;removing a portion of the silicon nitride layer, the tungsten silicide layer and the second polysilicon layer to expose the etching barrier layer in the logic circuit region and the second gate oxide layer in the memory circuit region forming a memory gate structure;removing a portion of the etching barrier layer and the first polysilicon layer to expose the first gate oxide layer using the silicon nitride layer, tungsten silicide layer and second polysilicon layer above the logic circuit region as a hard mask;removing the etching barrier layer above the first polysilicon layer;forming spacers on the sidewalls of the first polysilicon layer and the sidewalls of the memory gate structure;forming a first source/drain region in the substrate on each side of the memory gate structure, and forming a second source/drain region in the substrate on each side of the first polysilicon layer; andforming a self-aligned silicide layer over the first polysilicon layer and the second source/drain regions, wherein the first polysilicon layer and the self-aligned silicide layers together constitute a logic gate.