Patent ID: 7609573
Filing Date: 2009-10-27
Classification: G11C

Abstract:
1. An application specific integrated circuit (ASIC) device comprising a DRAM, the DRAM comprising: a) a plurality of memory arrays including: b) a plurality of strips of bit line sense amplifiers electrically connected to said bit lines; c) a plurality of data bus lines extending in the second direction; d) a plurality of selection circuitries, each said plurality of selection circuitries configured to connect a sense amplifier associated with a bit line of a respective one of said groups of bit lines to a respective one of said plurality of data bus lines that is adjacent the respective one of the groups; and e) a plurality of data bus read amplifiers electrically connected to said data bus lines and configured to facilitate transmission of first data to outputs of said DRAM, and said DRAM is embedded within the ASIC device.