Patent ID: 7969251
Filing Date: 2011-06-28
Classification: H03K,H03L

Abstract:
1. An apparatus coupled to receive an input signal and supply as an output a divided signal corresponding to the input signal divided by a number having an integer portion and a fractional portion (M/N), where M and N are integers and M <N, the apparatus comprising: a fractional-N divider generating an output signal according to a divider control signal; a first circuit including a first delta sigma modulator configured to supply, during a clock cycle of the first and a second circuit, a first divider control signal to the fractional-N divider as the divider control signal and a first fractional signal to a phase interpolator circuit, the first fractional signal corresponding to an error in the output signal of the fractional-N divider that corresponds to the first divider control signal; and the second circuit including a second delta sigma modulator configured to supply, during the clock cycle of the first and second circuit, a second divider control signal to the fractional-N divider as the divider control signal and a second fractional signal to the phase interpolator circuit, the second fractional signal corresponding to an error in the output signal of the fractional-N divider that corresponds to the second divider control signal.