Patent ID: 6348382
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A method for making an integrated circuit having a low voltage device and a high voltage device, comprising the steps of:providing a semiconductor substrate, then; patterning said semiconductor substrate into a low voltage portion and a high voltage portion, creating a first layer of gate oxide over the surface of said high voltage portion of said substrate, furthermore creating a second layer of gate oxide over the surface of said low voltage portion of said substrate, furthermore creating at least one High Voltage polysilicon gate structure over said first layer of gate oxide and at least one Low Voltage polysilicon gate structure over said second layer of gate oxide, said at least one High Voltage polysilicon gate structure and said at least one Low Voltage polysilicon gate structure having a channel length in the micron or sub-micron region, then; diffusing an impurity concentration into said high voltage portion, creating a High Voltage Lightly Doped Diffusion (HVLDD) region in the surface of said substrate self-aligned with said at least one High Voltage polysilicon gate structure, then; simultaneously annealing said high voltage portion and said low voltage portion, creating a layer of gate anneal oxide over the surface of said high voltage portion and said low voltage portion, including the exposed surface of said first layer of gate oxide and said second layer of gate oxide, thereby reducing gate etch damage and providing gate sidewall protection for said at least one High Voltage polysilicon gate structure and said at least one Low Voltage polysilicon gate structure, thereby furthermore forming junctions between said High Voltage Lightly Doped Diffusion (HVLDD) region in the surface of said substrate and the underlying silicon of the substrate; and then diffusing an impurity concentration into said low voltage portion, creating a Low Voltage Lightly Doped Diffusion (LVLDD) region in the surface of said substrate self-aligned with said at least one Low Voltage polysilicon gate structure, assuring device operational requirements for said at least one Low Voltage polysilicon gate structure while maintaining high breakdown voltage requirements for said at least one High Voltage polysilicon gate structure.