Patent ID: 6404250
Filing Date: 2002-06-11
Classification: G01R,G11C,H03L

Abstract:
A semiconductor body comprising:a first portion comprising a memory system; and a second portion comprising a programmable clock and test command signal generator comprising: a programmable clock signal generator comprising a clock input terminal and an output terminal, the programmable clock signal generator being designed to generate at the output terminal thereof a clock output signal having a frequency which is a selective predetermined multiple of an external clock signal applied to the clock input terminal; a counter having an input coupled to the output terminal of the programmable clock signal generator and at least one output terminal, the counter being designed to generate at the at least one output terminal thereof a cyclical binary count comprising a number of counts corresponding to the multiple of the frequency of the external clock output signal generated by the programmable clock signal generator; and a programmable look-up memory comprising memory locations for storing separate commands useful for testing predetermined sections of the memory system, the programmable look-up memory comprising (a) at least one first input terminal coupled to receive the cyclical binary count from the counter, (b) a plurality of second input terminals coupled to receive remotely generated encoded binary address input signals which are combined with the binary count from the counter to access predetermined memory locations in the look-up memory, and (c) at least one output terminal coupled to predetermined inputs of the memory system such that testing of the memory system is accomplished at the speed of the output clock signal from the programmable clock signal generator.