Patent ID: 6545525
Filing Date: 2003-04-08
Classification: G05F,G11C,H01L,H02M,H03K

Abstract:
A semiconductor device comprising:an interface circuit, which interfaces with an exterior of said semiconductor device, arranged to receive a first supply voltage and including a first transistor having a first threshold voltage; a logic circuit arranged to receive a second supply voltage which is lower than said first supply voltage, and including a second transistor having a second threshold voltage lower than said first threshold voltage, said second threshold voltage being effected by a substrate voltage of the logic circuit, wherein the substrate voltage of the logic circuit is derived from the first supply voltage; and a first memory array including static memory cells each including a third transistor having a third threshold voltage higher than said second threshold voltage, and arranged to receive a third supply voltage corresponding to said third threshold voltage and to the operation speed of the third transistor, said third threshold voltage being effected by a substrate voltage of the first memory array, wherein the substrate voltage of the first memory array is derived from the first supply voltage; wherein said third supply voltage is higher than said second supply voltage.