Patent ID: 6658578
Filing Date: 2003-12-02
Classification: G06F,G06K

Abstract:
A digital system comprising a programmable processor with variable instruction length, wherein the processor comprises:an instruction buffer unit, a program flow control unit with a decode mechanism, an address/data flow unit, a data computation unit, dual multiply-accumulate blocks, with multiple interconnecting busses connected there between and to a memory interface unit, the memory interface unit connected in parallel to a data memory and an instruction memory; wherein the instruction buffer is operable to buffer single and compound instructions pending execution thereof; wherein the decode mechanism is operable to decode instructions from the instruction buffer, including compound instructions and soft dual memory instruction; wherein the program flow control unit is operable to conditionally execute an instruction decoded by the decode mechanism or to repeatedly execute an instruction or sequence of instruction decoded by the decode mechanism; wherein the address/data flow unit is operable to perform bit field processing and to perform various addressing modes, including circular buffer addressing; wherein the processor further comprises a multistage execution pipeline connected to the program flow control unit, the execution pipeline having pipeline protection features; an emulation and code debugging facility with support for cache analysis, cache benchmarking, and cache coherence management connected to the program flow control unit, to the address/data unit, and to the data computation unit; and wherein various functional modules can be separately powered down to conserve power.