Patent ID: 6594802
Filing Date: 2003-07-15
Classification: G01R

Abstract:
An access controller for accessing an electronic circuit, comprising:a scan input terminal; a scan output terminal; a parallel access bus communicably coupleable to at least one functional I/O of the electronic circuit; an address bus communicably coupleable to at least one address input of the electronic circuit; a parallel control bus communicably coupleable to at least one control input of the electronic circuit; at least one data register having a serial input coupled to the scan input terminal for scanning input data into the data register, a plurality of data terminals coupled to the parallel access bus for providing in parallel the input data to the functional I/O and for receiving in parallel output data from the functional I/O of the electronic circuit, and a serial output coupled to the scan output terminal for scanning the output data out of the data register; at least one address register having a serial input coupled to the scan input terminal for scanning at least one address sequence into the address register, the address register being configured to provide in parallel the address sequence to the address input of the electronic circuit over the address bus; and a protocol generator coupled to the parallel control bus, the protocol generator including at least one control register for providing in parallel at least one functional control sequence to the control input of the electronic circuit over the parallel control bus, wherein the data register, the address register, and the protocol generator are configured to operate substantially concurrently to enable testing, debugging, or programmable configuration of the electronic circuit.