Patent ID: 7643330
Filing Date: 2010-01-05
Classification: G11C

Abstract:
1. A two-port static random access memory (SRAM) circuit, comprising: control logic configured to receive a reference clock signal and to transmit a read address, a write address and a read-write select signal; a shared address decoder configured to receive the read address, the write address and the read-write select signal from the control logic and to multiplex the read address and the write address using the read-write select signal such that only one word line signal is asserted at a time; a single-port memory array configured to receive the asserted word line signal from the shared address decoder; and a read/write input/output unit configured to read data from and write data to the single-port memory array, wherein the control logic is further configured to transmit the read address and the write address and initiate a bit line pre-charge only once within a period of the reference clock signal, and the shared address decoder is further configured to assert a read word line and a write word line within a period of the reference clock signal to perform one read operation and one write operation in the period of the reference clock signal.