Patent ID: 6230256
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A data processing system comprising:a processor bus comprising:a set of processor data lines, wherein:the set of processor data lines comprises:a first integer number of data lines; anda processor responsively coupled to the processor bus comprising:a first means for decoding a first set of instructions received over the set of processor data lines, wherein:the first set of instructions each contains a second integer number of significant bits,a third integer number of bits equals the difference between the first integer number and the second integer number,the first integer number is greater than the second integer number, andthe third integer number of bits are ignored during instruction decode; anda first means for performing fixed point arithmetic operations in response to instruction decode by the first decoding means on a first set of fixed point operands received over the set of processor data lines, wherein:each of the first set of fixed point operands contains the second integer number of bits, andthe third integer number of bits received over the set of processor data lines are ignored during fixed point arithmetic operations.