Patent ID: 7071112
Filing Date: 2006-07-04
Classification: H01L

Abstract:
1. A method of forming a dual damascene structure during the fabrication of an integrated circuit comprising: a) forming a via through at least one insulator layer; b) depositing a bottom-antireflective-coating material into said via and onto the field regions adjacent said via; c) depositing a photoresist on said bottom-antireflective-coating material; d) patterning said photoresist above said via in the form of a trench, exposing thereby one or more regions of said bottom-antireflective-coating material; e) directionally etching said bottom-antireflective-coating material to a level partially filling said via and such that the upper surface of said bottom-antireflective-coating material is convex; and f) etching a trench through said at least one insulator layer to a depth less than the depth of said via.