Patent ID: 8661393
Filing Date: 2014-02-25
Classification: G06F

Abstract:
1. An integrated circuit design method, comprising: accessing a standard cell library including a plurality of standard cells, wherein a standard cell comprises a data structure indicative of a layout of a plurality of physical elements defining the standard cell; determining, from the standard cell library, a first boundary library including a first boundary structure corresponding to each of the plurality of standard cells, wherein the first boundary structure indicates a layout of a first boundary region of the corresponding standard cell; responsive to identifying multiple first boundary structures in the first boundary library sharing a common layout, merging, by a data processing system, the multiple first boundary structures into a common boundary structure to produce a reduced first boundary library; checking, by the data processing system, local placement context for the standard cell library by checking local placement context for boundary structure pairs comprising a first boundary structure from the reduced first boundary library and a second boundary structure from a second boundary library corresponding to a second boundary region of the standard cells; and responsive to an exception raised by the local placement context checking of a first boundary structure pair: