Patent ID: 6043123
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A process for fabricating an integrated circuit memory comprising:in a semiconductor substrate of first conductivity type having a surface, forming a first well region of second conductivity opposite to the conductivity of the first conductivity type, the first well region having a periphery;forming, within the periphery of the first well region, and adjacent the surface, a second well region, the second well region of first conductivity type;forming, also within the periphery of the first well region, a first contact region spaced apart from the second well region, the first contact region being of second conductivity type and being more conductive than the first well;establishing a first insulating layer of a first thickness on the surface of the substrate;establishing a second insulating layer of a second thickness different from the thickness of the first thickness on the surface of the substrate;establishing a second insulating layer of a third thickness different from the thickness of the first and second thickness on the surface of the substrate;depositing a first conductive layer on the first insulating layer to provide a floating gate and on the second insulating layer to provide a first remote gate, the floating gate and the first remote gate being disposed above the surface of the substrate and electrically isolated therefrom;establishing a fourth insulating layer on the surface of the first conductive layer; anddepositing a second conductive layer on the fourth insulating layer to provide a control gate disposed above the floating gate and electrically isolated therefrom and on the third insulating layer to provide a second remote gate.