Patent ID: 8214703
Filing Date: 2012-07-03
Classification: G06F

Abstract:
1. A multicore processor comprising: at least a first core and a second core, the first core and the second core each comprising a first logic block and a second logic block; a first data input coupled to a first scan chain associated with the first logic block in the first core and a second scan chain associated with the second logic block in the second core; a second data input, different than the first data input, coupled to a third scan chain associated with the second logic block in the first core and a fourth scan chain associated with the second logic block in the second core; and a first multiplexer including at least a first input and a second input, the first input coupled with a data output of the first scan chain and the second input coupled with a data output of the second scan chain; a second multiplexer including at least a first input and a second input, the first input coupled with a data output of the third scan chain and the second input coupled with a data output of the fourth scan chain, wherein the first and second multiplexers further include an output that couples to one or more pins on a package of the processor and a select signal that couples to the one or more pins on the package of the processor; and wherein the first data input and the second data input couples to the one or more pins on the package of the processor.