Patent ID: 9153478
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A method of forming a target pattern for an integrated circuit, the method comprising: forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer, the first layout including a first subset of the target pattern; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, the second layout including a second subset of the target pattern and a cut pattern for the first subset; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features; wherein the target pattern is formed with the first layout and the second layout.