Patent ID: 6194276
Filing Date: 2001-02-27
Classification: H01L

Abstract:
A method for making a semiconductor static random access memory cell array for a semiconductor memory, the method comprising:forming a static memory cell having first and second storage nodes formed on first and second active regions formed in a substrate, and further having first and second transfer transistors coupled between the first and second storage nodes and first and second sense nodes, all respectively, each transfer transistor having a transfer gate formed from a polysilicon layer to selectively couple the storage node to a respective sense node;forming oxide isolation regions in the substrate adjacent to the first and second active regions; andforming active gate isolation structures on the substrate disposed in between the first and second data storage nodes, the active gate isolation structures biased to a first voltage to prevent a conduction channel from forming under the active gate isolation structures,wherein the active gate isolation structures are formed from the same polysilicon layer as the transfer gates of the first and second transfer transistor.