Patent ID: 6359316
Filing Date: 2002-03-19
Classification: H01L

Abstract:
In a CMOS device having complementary sets of P-channel and N-channel transistors, first transistors each comprising a first gate and an N-type diffusion region, and second transistors each comprising a second gate and a P-type diffusion region, the improvement being a first latch-up inhibitor P+ tap region adjacent to said first gate and in direct contact with said N-type diffusion region, and a second latch-up inhibitor N+ tap region adjacent said second gate and said P-type diffusion region,wherein there is no source or drain region intervening between said first latch-up inhibitor P+ tap region and said first gate, along the shortest path between said first latch-up inhibitor P+ tap region and said first gate, and there is no source or drain region intervening between said second latch-up inhibitor N+ tap region and said second gate, along the shortest path between said second latch-up inhibitor N+ tap region and said second gate.