Patent ID: 8041847
Filing Date: 2011-10-18
Classification: G06F,Y02D

Abstract:
1. A method of scheduling Direct Memory Access (DMA) operations in a NAND memory environment, the method comprising: providing blocks in a first DMA chain, each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer of the pair of pointers pointing to a command structure to be executed or a data structure to be moved, a second pointer of the pair of pointers pointing to a next block in the first DMA chain; using a DMA engine to process successive operations in the first DMA chain, wherein the DMA engine tracks whether a conditional operation has already been executed by checking a consumption semaphore included in the corresponding conditional block; tracking time remaining in an interval for processing the first DMA chain; maintaining a second DMA chain of conditional blocks, each conditional block corresponding to a conditional operation and containing an estimate of time needed to complete processing the conditional operation; and executing a given conditional operation from the second DMA chain if the remaining time in the interval for processing the first DMA chain is greater than the estimated time to complete processing of the given conditional operation.