Patent ID: 6514778
Filing Date: 2003-02-04
Classification: H01L

Abstract:
A method for measuring an effective channel length during a capacitance-voltage (C-V) method, said method comprising:providing a first device comprising a first gate electrode, a first source and a first drain, a second device comprising a second gate electrode, a second source and a second drain, wherein said first gate electrode has a gate length L and a gate width W1, said second gate electrode has a gate length L and a gate width W2; applying a negative fixed voltage to said first gate electrode and said second gate electrode; measuring an accumulation capacitance per unit width of said first device Cacc1 and an accumulation capacitance per unit width of said second device Cacc2, wherein said Cacc1 and said Cacc2 are expressed as a first equation and a second equation, Cacc1=2Ã—Cov+2Ã—Cf+(Coff/W1) â€ƒCacc2=2Ã—Cov+2Ã—Cf+(Coff/W2)whereCov is a gate-to-drain overlap capacitance per unit width, Cf is a fringing capacitance per unit width, Coff is a deviation capacitance from a measuring apparatus; and solving said first equation and said second equation to obtain said Cov and said Coff.