Patent ID: 9196495
Filing Date: 2015-11-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate comprising a groove; a bit line that is formed on both sides of the groove in the semiconductor substrate and acts as a source and a drain, the bit line has a different conductivity type than the semiconductor substrate; a pocket implantation region that has a similar conductivity type as the semiconductor substrate and has a dopant concentration higher than that of the semiconductor substrate, the pocket implantation region and the bit line form a PN junction, the bit line is located on a part of the pocket implantation region, side surfaces of the lower half of the groove are free of the pocket implantation region; a bottom insulating membrane that is formed on and contacts a side surface of the groove; and a charge accumulation layer that is formed on and contacts a side surface of the bottom insulating membrane.