Patent ID: 6812046
Filing Date: 2004-11-02
Classification: G06F,H01L,H04B

Abstract:
A method for electronically aligning pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling, comprising:measuring an alignment between a first chip and a second chip; wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip; wherein the transmitter pads are located in the highest metal layer of the first chip; and wherein the receiver pads are located in the highest metal layer of the second chip; using the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip; and selectively routing data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.