Patent ID: 6516390
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A data storage system, comprising:a cache; a first front-end circuit that operates as an interface between the cache and a first host; a second front-end circuit that operates as an interface between the cache and a second host; a first storage device; a second storage device; a first back-end circuit that operates as an interface between the cache and the first storage device; and a second back-end circuit that operates as an interface between the cache and the second storage device, wherein the first front-end circuit and the first back-end circuit reside on a first circuit board, wherein the second front-end circuit and the second back-end circuit reside on a second circuit board; a buffer circuit interconnected between the first front-end circuit and the first back-end circuit and that resides on the first circuit board to provide a direct data pathway between the first front-end circuit and the first back-end circuit that circumvents the cache, the buffer circuit being configured to carry data elements between the first front-end circuit and the first back-end circuit.