Patent ID: 6350693
Filing Date: 2002-02-26
Classification: C09G,H01L,Y10S

Abstract:
A method of fabricating a planarized structure on a semiconductor substrate, wherein a second material is embedded in a first material, the method comprising the following steps:providing a semiconductor substrate having a layer of first material deposited thereon and into which are etched contact openings; providing a layer of second material above the layer of first material and within the contact openings; chemical-mechanical polishing the layer of second material to the layer of first material by a two-step process, the first CMP step comprising chemical-mechanical polishing using a first polishing slurry which is selective to said second material; and further chemical-mechanical polishing the layer of second material by a second CMP step comprising chemical-mechanical polishing using a second polishing slurry which polishes both the second material and the first material.