Patent ID: 8812919
Filing Date: 2014-08-19
Classification: G01R,G06F,G11C,H04B,H04L

Abstract:
1. An integrated circuit, comprising: circuitry to generate a repeating pattern signal during a test mode; a receiver to serially receive a signal via at least one electrical conductor from a transmitter, the signal comprising a data signal during a normal mode and a repeating test pattern during the test mode; circuitry to change during the test mode at least one parameter affecting reception of the signal from the transmitter, such that the repeating test pattern from the transmitter is received using alternate values of the at least one parameter; and circuitry to compare the repeating pattern signal generated by the circuitry to generate with the repeating test pattern serially received by the receiver during the test mode, to generate a comparison output; where the circuitry to generate the repeating pattern signal during the test mode is independent of any circuitry used to generate the repeating test pattern received from the transmitter.