Patent ID: 8316212
Filing Date: 2012-11-20
Classification: G06F

Abstract:
1. An address translation unit comprising: a memory configured to store a plurality of translations in a set associative configuration comprising at least a first way and a second way, wherein the memory is statically partitioned into a first portion and a second portion, wherein the first way in the first portion is dedicated to storing translations corresponding to a first video processing unit, and wherein the second way in the first portion is dedicated to storing translations corresponding to a second video processing unit, and wherein the second portion is used to store translations corresponding to other units that use the address translation unit; and a control unit coupled to the memory, wherein the control unit is configured to allocate a location in the memory store a translation in response to a miss in the memory for a first request, and wherein the control unit is configured to allocate the location responsive to a source of the first request, and wherein the control unit is configured to perform a table walk in a set of translation tables stored in memory to locate a translation for the first request, and wherein the control unit is configured to cause the memory to store the translation in the location allocated in response to the miss, and wherein the control unit is configured to supply a physical address from the location in response to a subsequent virtual address input to the memory that hits in the location, wherein the first way of the first portion is dedicated to read requests from the first video processing unit, wherein the control unit is configured to allocate the location in the first way of the first portion responsive to the first request being a read request from the first video processing unit.