Patent ID: 8188959
Filing Date: 2012-05-29
Classification: G09G

Abstract:
1. A liquid crystal display, comprising: a frame buffer configured for doubling a frame rate of inputted signals by converting each frame into a first sub-frame and a second sub-frame; a frame rate conversion circuit configured for reducing a bit number of signals received from the frame buffer, the frame rate conversion circuit comprising: a first look up table configured for converting a gray level of one of the frames into a first predetermined gray level corresponding to the first sub-frame converted from said one frame, the first predetermined gray level corresponding to first signals with the reduced bit number; and a second look up table configured for converting the gray level of said one frame into a second predetermined gray level corresponding the second sub-frame converted from said one frame, the second predetermined gray level corresponding to second signals with the reduced bit number; a data divider; and a data driver; wherein the data divider is configured for receiving the first and second signals with the reduced bit number from the frame rate conversion circuit, and outputting third signals with a frequency being half of a frequency of the first signals and fourth signals with a frequency being half of a frequency of the second signals to the data driver; and the data driver is configured for driving the liquid crystal display to display images according to the third and fourth signals received from the data divider.