Patent ID: 7432153
Filing Date: 2008-10-07
Classification: H01L

Abstract:
1. A method of fabricating a direct-tunneling semiconductor memory device, comprising the steps of: forming a tunneling insulation film on a semiconductor substrate; forming a floating gate electrode on said tunneling insulation film; forming a dielectric film on a sidewall surface of said floating gate electrode; forming a conductor pattern constituting a part of a control gate electrode on said sidewall surface of said floating gate electrode via said dielectric film; forming an insulation pattern so as to cover said floating gate electrode including said conductor pattern and so as to expose a part of said semiconductor substrate forming a device isolation region; etching said semiconductor substrate while using said insulation pattern as a mask to form a device isolation trench; depositing a device isolation insulation film on said semiconductor substrate so as to fill said device isolation trench and so as to cover said floating gate electrode and said conductor pattern; etching back said device isolation insulation film until said conductor pattern is exposed; and forming another conductor pattern on said insulation film constituting said control gate electrode such that said another conductor pattern makes contact with said conductor pattern.