Patent ID: 8797708
Filing Date: 2014-08-05
Classification: H01L

Abstract:
1. A monolithic ceramic electronic component comprising: a ceramic base element including a plurality of stacked ceramic layers and outer surfaces defined by first and second principal surfaces opposed to each other, first and second lateral surfaces opposed to each other, and first and second end surfaces opposed to each other; first inner electrodes disposed inside the ceramic base element and each including a first opposing portion and a first lead-out portion led out from the first opposing portion to the outer surface of the ceramic base element; second inner electrodes disposed inside the ceramic base element and each including a second opposing portion, which is opposed to the first opposing portion with the ceramic layer interposed therebetween, and a second lead-out portion led out from the second opposing portion to the outer surface of the ceramic base element; a first outer electrode disposed on the outer surface of the ceramic base element and including a plated film that directly covers an exposed portion of the first lead-out portion; and a second outer electrode disposed on the outer surface of the ceramic base element, electrically connected to the exposed portion of the second lead-out portion, and connected to a different potential from that of the first outer electrode; wherein an extending direction of an interconnection between the first and second principal surfaces is defined as a height direction; a region where the first inner electrodes and the second inner electrodes are present in the height direction is defined as an inner layer portion; and a region where the first inner electrodes and the second inner electrodes are both not present in the height direction is defined as an outer layer portion; the outer layer portion includes: outer-layer dummy conductors are arranged in the outer layer portion such that the outer-layer dummy conductors are each led out to the outer surface of the ceramic base element in overlapped relation to the first lead-out portion when the ceramic base element is viewed through projection in the height direction, the outer-layer dummy conductors including exposed portions directly covered with the plated film of the first outer electrode; two or more outer-layer dummy conductors are successively arranged at predetermined intervals in the height direction to define a plurality of outer-layer dummy groups in at least one of the first outer layer portion and the second outer layer portion; and an interval between adjacent outer-layer dummy conductors within each of the plurality of outer-layer dummy groups is d and an interval between adjacent outer-layer dummy groups of the plurality of outer-layer dummy groups in the at least one of the first outer layer portion and the second outer layer portion is g, and g is greater than d.