Patent ID: 6172557
Filing Date: 2001-01-09
Classification: G01R,G04F,H03D,H03K

Abstract:
A pulse converting circuit for converting an inputted pulse signal to a divided-frequency pulse signal having either of rising and falling edges in accordance with both the rising and falling edges of said inputted pulse signal, comprising:a signal generating circuit for generating a clock signal;a counter for counting the clock signal outputted from said signal generating circuit; anda synchronous circuit for receiving said inputted pulse signal, causing an output signal to shift from one of logic levels to the other logic level and initializing the count value of said counter with the rising and falling timings of said inputted pulse signal, and causing said output signal to shift from said other logic level to said one of logic levels when the count value of said counter reaches a predetermined value,the output signal of said synchronous circuit being outputted as said divided-frequency pulse signal.