Patent ID: 6526106
Filing Date: 2003-02-25
Classification: H04L

Abstract:
A synchronous circuit controller transmits a first N-bit (N being an integer) parallel data signal output in synchronization with a first clock in a first phase to a second synchronous circuit latching the first signal in synchronization with a second clock in a second phase by adjusting a phase difference between said first and second phases, and outputting a second data signal in synchronization with said second clock, said controller comprising:a delay section for delaying said first data signal by M times (M being an integer) in a step of predetermined amount of delay, and outputting corresponding first to M-th delay data; a latch section for latching each of said first data signal and first to M-th delay data in synchronization with said second clock, and outputting a data latch signal and first to M-th delay latch signals; a comparator circuit for comparing said data latch signal and said first to M-th delay latch signals with each other in the ascending order of the amount of delay, detecting matching or non-matching between signals to be compared, and outputting first to M-th comparison signals corresponding to respective comparison results; and a selector circuit for selecting one of said data latch signal and said first to (M-1)-th delay latch signals in response to control of said first to M-th comparison signals as said second data signal, wherein said second clock is independent of said first clock.