Patent ID: 6828192
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method for fabricating a semiconductor memory having a trench capacitor and a selection transistor, which comprises the steps of:providing a substrate having a substrate surface with a trench formed therein, the trench having an upper region; forming an insulation collar in the upper region on a sidewall of the trench; depositing a dielectric layer functioning as a capacitor dielectric on the insulation collar; providing a conductive trench filling in the trench; sinking the conductive trench filling into the trench to a first sinking depth; removing the dielectric layer from the insulation collar in a region above the first sinking depth; sinking the conductive trench filling into the trench to a second sinking depth; uncovering the substrate at the sidewall of the trench above the conductive trench filling resulting in an uncovered sidewall; growing an epitaxial layer on the uncovered sidewall of the trench; forming an intermediate layer on the epitaxial layer; introducing a dopant into the epitaxial layer; and completing the trench capacitor and the selection transistor.