Patent ID: 6162680
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method for forming a capacitor, said method comprising the steps of:providing a semiconductor structure having a bottom dielectric layer thereon and a node contact within said bottom dielectric layer;forming a multi-layer structure on said bottom dielectric layer and said node contact, said multi-layer structure being provided to have etching selectivity in etching neighboring layers in said multi-layer structure;forming a top dielectric layer on said multi-layer structure;defining a first opening in said top dielectric layer down to a top area of said multi-layer structure;after defining said first opening, consecutively defining a second opening in said multi-layer structure under said first opening down to said node contact and said bottom dielectric layer;performing a wet etch through said second opening to form at least two lateral openings in said multi-layer structure;forming a first conductive layer conformably on said top dielectric layer, on sidewalls of said first opening and said second opening, and filled within said at least two lateral openings;forming a filling layer on said substrate;planarizing a top surface of said substrate to said top dielectric layer;removing said filling layer, said top dielectric layer, and said multi-layer structure to leave a first electrode having lateral fins and upwardly extended members atop said lateral fins on said substrate;forming an inter-electrode dielectric layer on said first electrode; andforming a second conductive layer on said inter-electrode dielectric layer.