Patent ID: 6064733
Filing Date: 2000-05-16
Classification: H04B

Abstract:
In an apparatus for echo cancelling on a four-wire path in which a receive clock and a transmit clock are asynchronous with each other, the apparatus comprising:a frame aligner circuit which writes a receive input signal at a timing of a receive clock and reads it out at a timing of a transmit clock to absorb an accumulation of a slip between timings of said receive clock and said transmit clock, and transmits a data slip recognition signal indicating a generation of a data slip of said receive input signal when the slip exceeds a maximum capacity as a result of an accumulation of the timings; andan echo canceller which receives said receive input signal as a reference input signal, estimates an echo component included in said receive input signal to remove the echo component when said data slip recognition signal output at the time of the generation of the data slip of said receive input signal is input thereto, and thereby cancels an echo signal at the time of the generation of the data slip from a transmit input signal.