Patent ID: 7219320
Filing Date: 2007-05-15
Classification: G06F

Abstract:
1. A timing analysis apparatus for performing timing analysis of a semiconductor integrated circuit based on inputted circuit information, comprising: a first timing analysis unit performing timing analysis in a target path which is an analysis target in the semiconductor integrated circuit by accumulating a variation in delay time of each gate in the target path, based on circuit information; a determination unit determining whether previously specified timing conditions are satisfied or not based on a result of the timing analysis supplied from said first timing analysis unit; a coefficient arithmetically operating unit calculating variation coefficients of delay time in the target path with the variation in the delay time of each gate being cancelled out in accordance with a number of gate stages in the target path only when it is determined that the timing conditions are not satisfied in said determination unit; and a second timing analysis unit performing timing analysis in the target path based on the circuit information and the variation coefficients calculated by said coefficient arithmetically operating unit.