Patent ID: 7454721
Filing Date: 2008-11-18
Classification: G06F

Abstract:
1. A method of optimizing a layout of an integrated circuit design, the method comprising the steps of: scanning a layout; assigning optimization variables to objects in the layout; creating an objective function equation that represents minimum design ground rules and manufacturer's recommended design ground rules in the layout; allocating a set of minimum design ground rules a highest weighting in the objective function equation; allocating a set of manufacturer's recommended design ground rules a logarithmic weighting in the objective function equation; and optimizing the layout according to the manufacturer's recommended design ground rules and minimum design ground rules weighted values; wherein the step of allocating a logarithmic weighting to the manufacturer's recommended design ground rules comprises the step of: assigning a logarithmic weighting to each of the manufacturer's recommended design ground rules; and wherein the step of optimizing the layout based on the manufacturer's recommended ground rules and minimum design ground rules weighted values includes the step of: allocating a logarithmic weighting to a first group of manufacturer's recommended design ground rules and allocating a logarithmic weighting to a second group of manufacturer's recommended design ground rules such that a sum of a specified number of weighted values of the second group that are added together is less than a weighted value of a single member of the first group, and such that a sum of a specified number of weighted values from the first group that are added together is less than a weighted value of a single member of a group corresponding to the minimum design ground rules.