Patent ID: 8307320
Filing Date: 2012-11-06
Classification: H03K

Abstract:
1. A pulse delay circuit on a programmable logic device, comprising: a plurality of delay units; a plurality of logic cells in each of a plurality of cell strings in which an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string; wherein each of delay units is arranged in one logic cell of the programmable logic device such that the delay units are placed in the logic cells of a single specific cell string included in the cell strings, and the delay units are connected in a ring shape such that a first part of the delay units, consecutively aligned in a connection order of the delay units, is placed along an aligning direction of the logic cells of the specific cell string and a second part of the delay units, consecutively aligned in the connection order, is placed along a direction opposite to the aligning direction.