Patent ID: 7457156
Filing Date: 2008-11-25
Classification: G11C

Abstract:
1. A depletion mode NAND architecture floating gate memory cell string comprising: a NAND architecture floating gate memory cell memory string formed on a substrate having a plurality of depletion mode floating gate memory cells are coupled in a source to drain coupled arrangement in a serial string, wherein the plurality of depletion mode floating gate memory cells have a native UV erased threshold voltage (UV-Vth) that is negative and where a pre-existing channel of carriers is formed in the depletion mode floating gate memory cells of the depletion mode NAND architecture floating gate memory cell string in a depletion channel; wherein the depletion mode NAND architecture floating gate memory cell string is adapted to program a selected floating gate memory cell by applying a floating gate programming voltage on a control gate of the selected floating gate memory cell and applying a program voltage or a program-inhibit voltage that is selectively coupled to the pre-existing depletion channel in the depletion mode NAND architecture floating gate memory cell string.