Patent ID: 7982301
Filing Date: 2011-07-19
Classification: H01L,H03G

Abstract:
1. A semiconductor device comprising: a semiconductor chip including a main surface, a back surface opposite to the main surface, a plurality of pads arranged over the main surface, and a plurality of low noise amplifiers arranged over the main surface, the plurality of the pads including a first pad and a second pad, the plurality of the low noise amplifiers including a first low noise amplifier and a second low noise amplifier for amplifying an inputted signal, the first pad and the second pad being electrically connected to the first low noise amplifier and the second low noise amplifier, respectively; a wiring substrate including a main surface, a back surface opposite to the main surface, a plurality of bonding electrodes arranged over a peripheral portion of the main surface of the wiring substrate, the plurality of the bonding electrodes including a first bonding electrode, a second bonding electrode, a first GND bonding electrode, a second GND bonding electrode, and a third GND bonding electrode; and a plurality of external terminals arranged over the back surface of the wiring substrate and being electrically connected to the plurality of the bonding electrodes; wherein the semiconductor chip is mounted over the main surface of the wiring substrate, and the first pad and the second pad of the semiconductor chip are electrically connected the first bonding electrode and the second bonding electrode of the wiring substrate with a first conductive wire and a second conductive wire, respectively, wherein the first bonding electrode and the second bonding electrode are disposed between the first GND bonding electrode and the second GND bonding electrode, and the third GND bonding electrode is disposed between the first bonding electrode and the second bonding electrode, wherein the wiring substrate further includes a first conductor pattern and a second conductor pattern which are disposed over the main surface thereof, wherein the first conductor pattern electrically connects the first GND bonding electrode and the second GND bonding electrode to each other such that the first conductor pattern surrounds the first and second bonding electrodes in a plan view, and wherein the second conductor pattern electrically connects the first conductor pattern and the third GND bonding electrode to each other such that the second conductor pattern is arranged between the first bonding electrode and the second bonding electrode in the plan view.