Patent ID: 6771729
Filing Date: 2004-08-03
Classification: H03L,H04L

Abstract:
A clock recovery circuit, which generates a recovery clock signal that continuously maintains a fixed phase to an input data signal, comprising:a frequency-divider, which frequency-divides a first clock signal by a selectable frequency division factor into a resulting second clock signal; and a charge pump, which outputs a selectable amount of VCO control electric current, wherein said selectable amount of VCO control electric current is selected in conformity with said selectable frequency-division factor, wherein said charge pump is comprised of a plurality of sub-charge pumps, wherein number of said plurality of sub-charge pumps that are allowed to work simultaneously is decided in conformity with said selectable frequency-division factor, and wherein the number of said plurality of sub-charge pumps that are allowed to work simultaneously is low when a low value is selected for said selectable frequency-division factor; otherwise number of said sub-charge pumps (9) that are allowed to work simultaneously is high when a high value is selected for said selectable frequency-division factor.