Patent ID: 6542410
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device in which floating-gate field-effect transistors that respectively have a control gate, a floating-gate, a drain and a source and are able to electrically write and erase information are arranged in a matrix form on a substrate or a well with a plurality of row lines connected to the control gates of the floating-gate field-effect transistors arranged in a direction of row and with a plurality of column lines connected to the drains of the floating-gate field-effect transistors arranged in a direction of column and in which the floating-gate field-effect transistors that constitute a block have their sources connected to a common source line, whereinthe floating-gate field-effect transistors, which belong to an erase object division to be subjected to batch erase, are divided into n (positive integer) regions, and comprising: for each erase object division, an erase frequency storage means for storing an erase frequency of the erase object division; an address setting means for setting addresses of regions which belongs to the erase object division and in which pre-erase write is executed on the basis of storage contents of the erase frequency storage means; a flag means for storing flag information that represents the erase frequency reaching n every time the erase frequency of the erase object division reaches n; and an erase frequency resetting means for resetting the storage contents of the erase frequency storage means when the flag information is stored in the flag means.