Patent ID: 6503840
Filing Date: 2003-01-07
Classification: H01L

Abstract:
A process for forming metal-filled openings in low k dielectric material of an integrated circuit structure which comprises:a) forming a composite layer of dielectric material over the integrated circuit structure, comprising a barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a capping layer of dielectric material over the layer of low k dielectric material; b) forming one or more openings in said composite layer through a mask over said integrated circuit structure by: i) forming a photoresist mask over said capping layer of dielectric material; ii) baking said photoresist mask in the presence of UV light; and iii) etching said composite layer through said photoresist mask; c) optionally densifying the newly exposed surfaces of said low k dielectric material; d) removing said resist mask using a plasma formed from a non-oxidizing gas; e) cleaning said exposed surfaces of said low k dielectric material to remove etch residues; f) annealing said low k dielectric material in a furnace to degasify said exposed surfaces of said low k dielectric material; g) cleaning said integrated circuit structure in an RF cleaning chamber; and h) filling said openings in said low k dielectric material by: i) depositing over said surfaces of said etched openings a first layer of an electrically conductive material capable of adhering to said etched surfaces; ii) forming a barrier layer of electrically conductive material over said first layer of electrically conductive material; and iii) then filling said openings with an electrically conductive metal filler material.