Patent ID: 6563507
Filing Date: 2003-05-13
Classification: G06T

Abstract:
A storage circuit control device comprising:means for storing in a storage circuit two-dimensional image data including pixel data indicating color of a plurality of pixels arrayed in matrix fashion; an address generating means for combining n bits of data making up a U address of a two-dimensional address (U, V) (wherein n is an integer of 1 or greater) and m bits of data making up a V address of said two-dimensional address (U, V) (wherein m is an integer of 1 or greater), to generate an (n+m) bit one-dimensional address; and a data accessing means for accessing said storage circuit using said generated one-dimensional address; wherein storage to said storage circuit is performed such that unit blocks, including said plurality of pixel data to be simultaneously accessed, are stipulated, and stored in said storage circuit so that a plurality of unit blocks making up said two-dimensional image data are continuously positioned within a one-dimensional address space within said storage circuit and the plurality of pixel data within each of the unit blocks are continuously positioned within the one-dimensional address space; wherein in the event that said integer n and said integer m are equal; and wherein k is an integer expressed by (nâˆ’1)and wherein said U address is represented by the n bits of (U[nâˆ’1], . . . , U[k], . . . , U[0]); and wherein said V address is represented by the n bits of (V[nâˆ’1], . . . , V[k], . . . , V[0]); said address generating means combines each of the bit data U[nâˆ’1], . . . , U[k], . . . , U[0] of said U address with each of the bit data V[nâˆ’1], . . . , V[k], . . . , V[0] of said V address, thereby generating 2n bits of one-dimensional addresses (V[nâˆ’1], U[nâˆ’1], . . . , V[k], U[k], . . . , V[0], U[0]).