Patent ID: 8558778
Filing Date: 2013-10-15
Classification: G09G

Abstract:
1. A shift register comprising a plurality of unit circuits connected in series, each of the plurality of unit circuits including an input terminal and an output terminal, the shift register sequentially transferring a start signal supplied to the input terminal of a first one of the unit circuits in synchronization with a clock signal and an inverted clock signal whose phases are opposite to each other, each of the plurality of unit circuits including: a first control terminal to which the clock signal is supplied; a second control terminal to which the inverted clock signal is supplied; a third control terminal to which an output signal output from the output terminal of a subsequent unit circuit is supplied; a power supply terminal to which a power supply potential is supplied; a first transistor disposed between the first control terminal and the output terminal; a second transistor disposed between the output terminal and the power supply terminal and connected at a gate of the second transistor to the second control terminal; a first capacitor disposed between the output terminal and a gate of the first transistor; and a controller that supplies the start signal or the output signal of a previous unit circuit supplied through the input terminal to the gate of the first transistor so as to connect the first control terminal to the output terminal, and that supplies the output signal of the subsequent unit circuit input to the third control terminal to control a potential applied to the gate of the first transistor to switch the first transistor from on to off at a controlled time later than a time at which the output signal of the subsequent unit circuit is supplied to the third control terminal so as to connect the first control terminal and the power supply terminal to the output terminal, wherein the controller includes: