Patent ID: 7053470
Filing Date: 2006-05-30
Classification: G11C,H01L

Abstract:
1. A packaged system with a repairable embedded memory comprising: a multi-chip package having external pins for connecting to an external printed-circuit board (PCB); an embedded memory die packaged within the multi-chip package and electrically connected to a first subset of the external pins; an embedded memory array on the embedded memory die, the embedded memory array losing data when power is removed from the packaged system; a non-volatile memory die packaged within the multi-chip package and electrically connected to a second subset of the external pins; a persistent repair memory within the non-volatile memory die, the persistent repair memory retaining repair data when power is removed from the packaged system; a volatile repair memory within the embedded memory die, the volatile repair memory receiving repair data originally stored in the persistent repair memory after power-up, but the volatile repair memory losing the repair data when power is removed from the packaged system; and a repair controller, coupled to read and use the repair data from the volatile repair memory to repair defective memory locations within the embedded memory array, whereby defective memory locations in the embedded memory die are repaired using repair data stored in the persistent repair memory that is packaged in a same multi-chip package with the embedded memory die.