Patent ID: 8980746
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method for forming copper filled through silicon via features in a silicon wafer, comprising: etching through silicon vias in the silicon wafer; forming an insulation layer within the through silicon vias; forming a barrier layer within the through silicon vias; depositing an oxide free silicon, germanium, or SiGe adhesion layer over the barrier layer; depositing a seed layer over the oxide free silicon, germanium, or SiGe adhesion layer; annealing a stack comprising the insulation layer, the barrier layer, the oxide free silicon, germanium or SiGe adhesion layer and the seed layer; filling the through silicon vias with copper or copper alloy; and annealing a stack comprising the insulation layer, the barrier layer, the oxide free silicon, germanium or SiGe adhesion layer, the seed layer and the copper or copper alloy.