Patent ID: 6233716
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A memory system comprising:a plurality of first components configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits, and wherein each bit of said data block is assigned to one of said plurality of first components;a plurality of second components configured to transfer the bits of said data block, wherein each bit of said data block is assigned to one of said plurality of second components;an error detection circuit coupled to said first components and said second components;wherein said data bits and said check bits are grouped to form a plurality of logical groups, and wherein each logical group includes at most one bit assigned to a given one of said plurality of first components and at most one bit assigned to a given one of said plurality of second components;wherein said error detection circuit is configured to:generate one or more check bits of a given one of said logical groups from data bits of the given one of said logical groups;verify the accuracy of the data bits of the given one of said logical groups using the check bits of the given one of said logical groups; andwherein numbers of bits in each of said logical groups are selected to optimize a ratio of a number of said check bits to a number of said data bits.