Patent ID: 6930945
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a cell array having a plurality of memory cells, each of said memory cells including: an address holding circuit for receiving and holding an address signal supplied from an outside of said semiconductor memory device; a first determination circuit for comparing a refresh address with a row address, selected according to a control signal commanding a read/write operation, between row addresses of a read address signal and a write address signal held in said address holding circuit to determine whether the refresh address matches the selected row address or not; and a control unit for performing control so that when a mismatch is detected as a result of the determination by said first determination circuit, the read or write operation and a refresh operation are performed in parallel, wherein the read or write operation is performed using the word line and the bit line for one of said read and write systems for the memory cell selected by the read or write address signal, while the refresh operation is performed using the word line and the bit line for the other of said read and write systems for the memory cell selected by the refresh address signal and a sense amplifier for the other of said read and write systems, and when the match is detected as the result of the determination by said first determination circuit, the refresh operation is inhibited and the read or write operation using the word line and the bit line for said one of said read and write systems for the memory cell selected by the read or write address signal is performed.