Patent ID: 6327685
Filing Date: 2001-12-04
Classification: G01R

Abstract:
A logic built in self test method for testing combinational logic, including the steps of:connecting a plurality of master-slave latches in a scan chain where an output of each latch is coupled to an input to the next latch in the chain;connecting outputs of the combinational logic to respective inputs of the latches in the chain;connecting an output of each even latch in the chain to an input of a next successive even latch in the chain through a gated input;connecting an output of each odd latch in the chain to an input of the next successive odd latch in the chain through a gated input;feeding back an output of at least one latch in the chain to an input of a prior latch in the chain to configure a distributed LFSR and/or MISR function;coupling a first phase clock to said even latches in said chain to operate each even latch as a linear feedback shift register/multiple input signature register combination;coupling a second phase clock to said odd latches in said chain to operate each odd latch as linear feedback shift register/multiple input signature register combination.