Patent ID: 7010722
Filing Date: 2006-03-07
Classification: G06F

Abstract:
1. A debug system for symmetrical multiprocessor systems including plural central processor units, each central processor unit including a test access port, said debug system comprising: a first test signal multiplexer receiving external test input signals and debug slave signals, said first test signal multiplexer directly coupling external test input signals to input lines of the test access port of a single user selected debug master central processor unit and coupling debug slave signals to at least one non-selected debug slave central processor unit thereby causing said at least one non-selected debug slave central processor unit to operate in a slave mode; and a second test signal multiplexer having a plurality of inputs, each input directly coupled to an output line of the test access port of a corresponding one of said plural central processing units, and having an output supplying an external test output signal, said second test signal multiplexer coupling said output line of said single selected debug master central processor to output.