Patent ID: 7222219
Filing Date: 2007-05-22
Classification: G06F

Abstract:
1. A memory control method for a computer system including a central processing unit, an interrupt controller and a memory, the central processing unit executing pipeline processing, in which a plurality of instruction processing cycles is executed at timing overlapping partly by dividing a processing function to be executed upon reading an instruction from the memory into a plurality of stages and by executing different stages of the plurality of stages in parallel, the interrupt controller outputting an interrupt signal to the central processing unit in response to an interrupt request applied thereto and setting an interrupt vector number corresponding to the interrupt request in an internal register thereof, and the memory storing at least an interrupt address table, in which are arranged a plurality of programs and an interrupt process routine to be executed by the central processing unit and a head address of the interrupt process routine, the memory having an access time longer than an operation time required for the central processing unit to execute each of the plurality of stages, the memory control method comprising: identifying an address as an object of a next access to a memory by a central processing unit based on at least any of data, an address and a control signal transferred via a data bus, an address bus and a control line connected to the central processing unit; and supplying a pre-reading address, which is an identified address, to the memory in place of the address supplied via the address bus during a period until at least the central processing unit starts accessing the memory.