Patent ID: 6122711
Filing Date: 2000-09-19
Classification: G06F

Abstract:
An improvement to the coherency cache architecture of a data processing system including at least a selected cache and a remote cache and a main memory, with the caches including means for addressing at least an overlapped portion of the main memory; the system including coherency means with indicator means in each cache for indicating the modified data in each cache, and for indicating valid data in each cache, the improvement comprising: flush means using the modified indicator for selecting data to be transferred, and for sending lines from the selected cache back to the remote cache such that the selected cache lines can be flushed from one cache back to main memory prior to a local cache being removed from the system, where the data processing system's coherency indicator means includes tag means associated with each cache for storing tag addresses of stored data, with the indicators of modified and valid processor being associated with the respective tag address, said flush means further having means for sequentially checking all tag addresses, selecting the addresses of data to be transferred using the associated indicators, and using the selected tag addresses to send data from the local cache to the remote cache as each tag address is sequentially checked.