Patent ID: 6993071
Filing Date: 2006-01-31
Classification: H04L

Abstract:
1. In a feedback equalizer device implementing a filter unit performing convolution operations between filter coefficients and one of a plurality of first discrete digital level values for generating a filter output, a multiplier device for multiplying a first discrete digital level value with a filter coefficient for said convolution operation, said multiplier device comprising: a decoder device for receiving and decoding an encoded, first discrete digital level value to be multiplied with a filter coefficient, and implementing logic for generating control signals according to said first digital level value; a first sub-multiplication circuit receiving said filter coefficient and implementing logic for multiplying said filter coefficient by a negative value in accordance with a first set of control signals and generating a first intermediate multiplication result therefrom; a second sub-multiplication circuit receiving said first intermediate multiplication result and implementing logic for multiplying said first intermediate result by a positive value or zero (0) in accordance with a second set of control signals and generating a second intermediate result therefrom; a third sub-multiplication circuit for shifting bits to effect a multiplication of one of said first or second intermediate result with a discrete digital value different than any of said first plurality of discrete digital level values, and generating a third intermediate result; and an accumulator device for adding the results of said third and the other of said first or second intermediate results to obtain a final multiplication result.