Patent ID: 7328315
Filing Date: 2008-02-05
Classification: G06F

Abstract:
1. In a data processing system having a memory control device including at least two mirrored memory ports, a system for processing read requests comprising: a memory controller that generates and processes signals for reading and writing data from and to a system memory that employs memory mirroring in which a first set of memory modules is mirrored by a corresponding second set of memory modules, said memory controller including a memory access control module that controls reading and writing between said memory controller and said first and second set of memory modules, said memory access control module receiving read and write requests on a system interconnect; a memory bus comprising a pair of memory ports that communicatively couple said memory controller with said first and second set of memory modules; said memory controller further including a pair of port interface modules for respectively interfacing each of said pair of memory ports with said memory access control module, each of said pair of port interface modules comprising: a central data buffer coupled to said memory bus, said central data buffer storing data for pending read and write requests issued onto said memory bus; an error detection module coupled to said central data buffer, said error detection module containing logic for detecting uncorrectable errors in data returned by execution of read requests; wherein said memory access control module includes a read scheduler module that issues read requests only to a specified one of said pair of memory ports; and wherein said conflict queue module includes logic for, responsive to receiving an uncorrectable error signal from said error detection module indicating an uncorrectable error resulting from a read request issued to the specified memory port, issuing the read request to the other of the pair of memory ports prior to reporting a read request status to said read request buffer and holding the corresponding read request during said issuing of the read request to the other of the pair of memory ports prior to said reporting the read request status to said read request buffer.