Patent ID: 6529199
Filing Date: 2003-03-04
Classification: G09G

Abstract:
A pipelined bubble squeezer for sorting n indication bits which are input in parallel into continuous logic 1's and/or continuous logic 0's, said pipelined bubble squeezer comprising an interconnection network of nÃ—n cells, said interconnection network comprising a 0-th buffering stage composed of n buffering cells numbered as from R0 to R(nâˆ’1), and first to (nâˆ’1)th multiplexing stages composed of nÃ—(nâˆ’1) multiplexing cells numbered as R0 to R(nâˆ’1), each one of said plurality of buffering cells including a buffer, each one of said plurality of multiplexing cells including a multiplexer, the logic value of selecting signals (valid 0Ëœvalid (nâˆ’1)) of said multiplexers being determined by the following equations:valid 0=the logic value of the upper input of R0 multiplexer valid 1=the logic value of the upper input of R1 multiplexer AND valid 0valid 2=the logic value of the upper input of R2 multiplexer AND valid 1. . . valid (nâˆ’1)=the logic value of the upper input of R(nâˆ’1) multiplexer AND valid (nâˆ’2) wherein valid 0 is the selecting signal of R0 multiplexer of row 0, valid 1 is the selecting signal of R1 multiplexer of row 1, valid 2 is the selecting signal of R2 multiplexer of row 2, valid (nâˆ’1) is the selecting signal of R(nâˆ’1) multiplexer of row (nâˆ’1); if one of the selecting signals of said multiplexers is logic 1, then the upper input of said multiplexer is selected; otherwise, the lower input of said multiplexer is selected.