Patent ID: 7692457
Filing Date: 2010-04-06
Classification: G06F

Abstract:
1. A method, comprising: driving a first clock domain signal on a first clock tree, using one or more drivers that produce a first jitter level within the first clock domain signal, from a phase locked loop (PLL) to a first clock domain drop off circuit; driving a second clock domain signal on a second clock tree, using one or more drivers that produce a second jitter level within the second clock domain signal, from the PLL to a second drop off point, wherein the second jitter level is smaller than the first jitter level; detecting any phase misalignment between the first clock domain signal transmitted from the first clock domain drop off circuit and the second clock domain signal transmitted from the second clock domain drop off circuit; and aligning the phases of the first clock domain signal and the second clock domain signal when a phase misalignment is detected.