Patent ID: 6209078
Filing Date: 2001-03-27
Classification: G06F

Abstract:
A hardware accelerator which comprises:an input port; andtwo or more functional units, wherein each functional unit includes:a first input multiplexer coupled to the input port to receive an first N bit word;a second input multiplexer coupled to the input port to receive a second N bit word different than the first N bit word;a third input multiplexer;a fourth input multiplexer;an N.times.N bit multiplier coupled to the first and second input multiplexers to receive the first and second N bit words and configured to multiply the first and second N bit words to produce a most significant N bit word and a least significant N bit word;a first bypass multiplexer coupled to the multiplier to receive the most significant N bit word and coupled to the first input multiplexer to receive the first N bit word, and further configured to provide a first selected N bit word;a second bypass multiplexer coupled to the multiplier to receive the least significant N bit word and coupled to the second input multiplexer to receive the second N bit word, and further configured to provide a second selected N bit word;a 2N bit arithmetic logic unit (ALU) coupled to the first and second bypass multiplexers to receive a first 2N bit operand, and coupled to the third and fourth input multiplexers to receive a second 2N bit operand, wherein the ALU is configured to operate on the first and second 2N bit operands to produce a most significant N bit result word and a least significant N bit result word;a first register bank coupled to the ALU to receive the most significant N bit result word, and configured to provide a third N bit word to the third input multiplexer and a fourth input word to the fourth multiplexer; anda second register bank coupled to the ALU to receive the least significant N bit result word, and configured to provide a fifth N bit word to the third input multiplexer and a sixth N bit word to the fourth input multiplexer.