Patent ID: 6381190
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of banks, each of which includes a memory cell array and a sense amplifier section; a plurality of channel memories; a data control circuit; a first bus provided between said plurality of banks and said plurality of channel memories; a second bus provided between said plurality of channel memories and said data control circuit; and a third bus between said plurality of banks and said data control circuit, and wherein said data control circuit outputs write data to said sense amplifier section of a specified one of said plurality of banks via said third bus in a direct write access mode, inputs read data from said sense amplifier section of a specified one of said plurality of banks via said third bus in a direct read access mode, outputs write data to said sense amplifier section of a specified one of said plurality of banks via said second bus, a specified one of said plurality of channel memories and said first bus in an indirect write access mode, and inputs read data from said sense amplifier section of a specified one of said plurality of banks via said first bus, a specified one of said plurality of channel memories and said second bus in an indirect read access mode.