Patent ID: 6252445
Filing Date: 2001-06-26
Classification: G04F,G04G

Abstract:
A circuit for generating a time-stamp for a trigger signal, comprising:clock circuit including an oscillator that generates an oscillator signal and a circuit that generates updates of a time value in response to the oscillator signal;latch circuit coupled to receive the time value from the clock circuit, the latch circuit obtaining a latched time value by latching the time value in response to the trigger signal;delay line coupled to receive the trigger signal, the delay line generating a set of tap signals by successively delaying the trigger signal such that the trigger signal and the tap signals are spaced in time by a set of predetermined sub-intervals of a period of the oscillator signal;a set of correction latches corresponding to the tap signals, each correction latch coupled to receive a portion of the time value from the counter, each correction latch obtaining a captured time value by latching the portion of the time value in response to the corresponding tap signal;means for determining a correction value by examining a pattern in the time value and the captured time values;means for applying the correction value to the latched time value.