Patent ID: 6836153
Filing Date: 2004-12-28
Classification: H03L

Abstract:
A digital delay lock loop circuit comprising:a delayed reference clock circuit to receive a reference clock signal and to generate a delayed reference clock signal having a first minimum time delay with respect to the reference clock signal, wherein the delayed reference clock signal has first and second edges in each clock cycle; a delayed system clock circuit to receive a system clock signal and to generate a delayed system clock signal having a second minimum time delay with reference to the reference clock signal, wherein the second minimum time delay is about half the first minimum time delay, wherein the delayed system clock signal has first and second edges in each clock cycle; a phase detector circuit, comprising: a first edge detector circuit having first and second inputs to receive the reference and delayed system clock signals, respectively, and to output a first signal based on order of arrival of the received first and second edges of the reference and delayed system clock signals in each clock cycle; a second edge detector circuit having first and second inputs to receive the delayed reference and delayed system clock signals, respectively, and to output a second signal based on order of arrival of the received first and second edges of the delayed reference and delayed system clock signals in each clock cycle; a logic circuit to receive the first and second signals from the first and second edge detector circuits, respectively, and to output a logic signal based on the received signals; and a compensation circuit to receive the system clock signal and the logic signal and to substantially synchronize the received system clock signal to the reference clock signal by compensating the system clock signal as a function of the received logic signal.