Patent ID: 8448110
Filing Date: 2013-05-21
Classification: G06F,Y02P

Abstract:
1. A method to reduce timing performance parameter variation in an integrated circuit by design alteration, said method comprising: receiving an initial circuit design into a computerized device, said initial circuit design comprising a path having a source at one end, at least a sink at an opposite end, and multiple circuit elements between said source and said sink; evaluating, by said computerized device, timing performance parameter sensitivities of a timing performance parameter to manufacturing variations of each of said multiple circuit elements to identify how much each circuit element will increase or decrease said timing performance parameter of said path for each change in each manufacturing variable associated with manufacturing said multiple circuit elements; and altering, by said computerized device, said multiple circuit elements within said path until positive circuit elements of said multiple circuit elements that produce positive changes to said timing performance parameter for a given manufacturing variable change approximately equals, in magnitude, negative circuit elements of said multiple circuit elements that produce negative changes to said timing performance parameter for said given manufacturing variable change so that said negative changes to said timing performance parameter effectively cancel out said positive changes to said timing performance parameter, to produce an altered circuit design.