Patent ID: 7099228
Filing Date: 2006-08-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a clock generator for delaying an input clock for a predetermined time to generate a delay clock, and dividing the input clock to output a first division signal and a second division signal having an opposite phase to that of the first division signal; a latch unit for latching an input signal buffered synchronously with respect to the delay clock for a predetermined time; a first command processing means comprising a plurality of command processing blocks connected in parallel for latching and amplifying an output signal applied from the latch unit synchronously with respect to the first division signal and the second division signal; a second command processing means comprising a plurality of bank control blocks connected in parallel for generating a control signal to control row and column paths in response to an output signal applied from the first command processing means synchronously with respect to the first division signal and the second division signal; and a selection unit for selecting one of output signals from the second command processing means in response to the first division signal and the second division signal.