Patent ID: 8984254
Filing Date: 2015-03-17
Classification: G06F,Y02D

Abstract:
1. A method of operating a processor, comprising: translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number, associated with a first multi-bit translation lookaside buffer way and a first multi-bit translation lookaside buffer index, in the translation lookaside buffer; translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number, associated with a second multi-bit translation lookaside buffer way and a second multi-bit translation lookaside buffer index, in the translation lookaside buffer; and determining that the first and second virtual addresses point to a same physical address in memory and reference same data by determining the first multi-bit translation lookaside buffer way is equal to the second multi-bit translation lookaside buffer way and the first multi-bit translation lookaside buffer index is equal to the second multi-bit translation lookaside buffer index.