Patent ID: 7476928
Filing Date: 2009-01-13
Classification: H01L

Abstract:
1. A flash memory device comprising: at least one active region in a semiconductor substrate; a string-selection gate line that crosses over the active region; a ground-selection gate line that crosses over the active region; a plurality of wordlines that cross over the active region between the string-selection gate line and the ground-selection gate line; a common source region in the active region at a first side of the ground-selection gate line; and a first source spacer that crosses over a first top edge region of the common source region and a second source spacer that crosses over a second lop edge region of the common source region; a source line between the first source spacer and the second source spacer that is electrically connected to the common source region, wherein a height of a top surface of the source line above the semiconductor substrate is less than or equal to a height of a top surface of the ground-selection gate line above the semiconductor substrate wherein the width of an upper portion of the source line is less than a distance between an outside wall of the first source spacer and an outside wall of the second source spacer, and greater than a minimum width between an inside wall of the first source spacer and an inside wall of the second source spacer.