Patent ID: 9026888
Filing Date: 2015-05-05
Classification: G06F,H03M

Abstract:
1. A memory controller comprising: memory access logic to service one or more write requests, including the memory access logic to: wherein the memory controller comprises encoder logic, responsive to the one or more write requests, to: the memory access logic further to service one or more read requests, including the memory access logic to retrieve from the one or more memory devices first data of the first data block, second data of the second data block, the first error correction code and the second error correction code; and wherein, responsive to the one or more read requests, the error detection logic further to generate a third result based on the retrieved first data and the first metadata value stored at the first location to perform a first error detection analysis with the third result, wherein the first error detection analysis is based on the retrieved first error correction code, to generate a first signal which indicates whether an error is indicated by the first error detection analysis, to generate a fourth result based on the retrieved second data and the first metadata value stored at the first location, to perform a second error detection analysis with the fourth result, wherein the second error detection analysis is based on the retrieved second error correction code, and to generate a second signal which indicates whether an error is indicated by the second error detection analysis.