Patent ID: 6594195
Filing Date: 2003-07-15
Classification: G11C

Abstract:
A high-density, low-power, semiconductor memory product comprising:a memory array formed on a unitary semiconductor substrate, the memory array including a plurality of rows of memory cells, each row of memory cells coupled to a corresponding wordline for accessing the row by assertion of the corresponding wordline; a row address decoder arranged for receiving a row address and including means for simultaneously asserting a corresponding unique pair of the wordlines in response to each received valid row address, so that a single valid row address simultaneously accesses two rows of memory cells in the memory array; and means for differentially storing a bit of data across a pair of memory cells, each one of the pair of memory cells being within a different respective row of the array, and the two different rows together corresponding to one of the unique pairs of wordlines asserted by the row address decoder responsive to a valid row address.