Patent ID: 6876031
Filing Date: 2005-04-05
Classification: G11C,H01L

Abstract:
1. A semiconductor device having at least one transistor, the device comprising: a substrate having a channel region defined thereon; a first insulating layer disposed over said channel region and over at last a portion of said substrate; a floating gate having at least a substantial portion thereof disposed over said channel region and separated therefrom by said fist insulating layer, said floating gate having at least two side walls and a top surface; a second insulating layer disposed over said side walls and over said top surface of said floating gate; a control gate having a first portion disposed over a portion of said channel region and being separated therefrom by said second insulating layer, a second portion formed over a first one of said side walls and a third portion formed over at least a first portion of said top surface of said floating gate and being separated from said floating gate by said second insulating layer, said second portion having a surface substantially parallel to and opposing said first side wall; an erase gate formed over a second one of said side walls and over at least a second portion of said top surface of said floating gate and being separated from said second one of said side walls and said portion of said top surface of said floating gate by said second insulating layer; a drain region formed in a portion of said substrate proximate said first portion of the control gate; and a source region formed in a portion of said substrate proximate said erase gate, said source region having a substantial portion thereof underneath said floating gate; wherein during an erase operation with the drain region, the source region and the control gate connected to ground, and a relatively high potential applied to the erase gate, stored electrons are removed from the floating gate to the erase gate through the Fowler-Nordheim tunneling process.