Patent ID: 8787061
Filing Date: 2014-07-22
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate; memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adj acent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, a gate of the first memory cell being electrically connected to a gate of the second memory cell; and bit lines disposed above the memory units, the bit lines extending in a third direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, the third direction being different from both the first direction and the second direction, and the third direction being parallel to the semiconductor substrate, wherein a first pitch is larger than a second pitch, the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between the first bit line and the second bit line.