Patent ID: 6608346
Filing Date: 2003-08-19
Classification: H01L

Abstract:
An information handling system, comprising:a memory device, wherein the memory device comprises: a number of floating gate tunneling oxide (FLOTOX) transistors, wherein each FLOTOX transistor comprises: a substrate, the substrate having a source region, a drain region, and a body region separating the source region and the drain region; a tunnel oxide layer formed on the body region; a shallow trench isolation region having walls that form an edge in the body region; a floating gate having an edge and a top surface and formed on the tunnel oxide layer, wherein the edge of the floating gate is aligned with the edge of the body region and wherein the top surface is non-uniform; an insulator layer formed on the floating gate; and a control gate formed on the insulator layer; a number of wordlines, wherein each wordline couples to the control gate for a number of the FLOTOX transistors; a number of bitlines, wherein each bitline couples to the drain region for a number of the FLOTOX transistors; a number of sense amplifiers, wherein each sense amplifier couples to a select number of the number of bitlines; and a number of sourcelines, wherein each sourceline couples to a source region for a number of FLOTOX transistors; a processor; a bus, wherein the bus couples the memory device to the processor; and wherein a surface area of at least one of the number of FLOTOX transistors is less than 0.4 &mgr;m2.