Patent ID: 8198713
Filing Date: 2012-06-12
Classification: H01L

Abstract:
1. A semiconductor wafer structure, comprising: a semiconductor wafer including active areas on a top side and having a back side that opposes the top side; and a solid spacer layer configured to be singulated into spacers that provide spacing between semiconductor dice in stacked die packages, wherein the solid spacer layer is attached to and directly contacts the back side of the semiconductor wafer, and the solid spacer layer is patterned to include open areas configured to be situated over bond pads of semiconductor die from at least one other semiconductor wafer in the stacked die packages and patterned to include other open areas configured to be situated over at least one of an active element, a MEM system, a sensor, or a light emitting element of the semiconductor die from the at least one other semiconductor wafer in the stacked die packages, wherein the solid spacer layer includes different patterns corresponding to different full semiconductor die from the at least one other semiconductor wafer.