Patent ID: 6693041
Filing Date: 2004-02-17
Classification: H01L

Abstract:
A method of forming isolations in a semiconductor substrate comprising:(a) providing a silicon substrate; (b) forming a plurality of adjacent trenches leaving adjacent segments of said silicon substrate between each of said plurality of adjacent trenches; (c) depositing an oxidation barrier layer in said plurality of adjacent trenches; (d) recessing a portion of said oxidation barrier layer in each of said plurality of adjacent trenches to expose at least a portion of said adjacent segments of said silicon substrate; (e) etching said exposed portions of said adjacent segments of said silicon substrate to form a plurality of thin sections of said exposed adjacent segments of said silicon substrate between each of said plurality of adjacent trenches; and (f) merging said thin sections of said exposed adjacent segments of said silicon substrate at least along a first row of selected ones of said plurality of adjacent trenches to form a self-aligned shallow trench isolation.