Patent ID: 7295477
Filing Date: 2007-11-13
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a wordline; a first bitline; a second bitline; a third bitline; a first memory cell and a second memory cell, the first memory cell coupled to the wordline, the first bitline and the second bitline, the second memory cell coupled to the wordline, the first bitline and the third bitline, wherein each memory cell stores a first bit and a second bit; a programming unit coupled to the wordline, the first bitline, the second bitline and the third bitline, the programming unit causing the application of a first programming potential to the wordline and a third programming potential to the second and third bitlines while applying a second programming potential to the first bitline in order to program the first bit of the second memory cell and the second bit of the first memory cell.