Patent ID: 8732367
Filing Date: 2014-05-20
Classification: G06F

Abstract:
1. A bus host controller coupled to a first terminal device via a bus, the bus host controller comprising: a timing module generating a start-of-frame (SOF) packet transferring request according to a frame period, and capable of calculating whether a remaining time in the frame period is enough for transferring a data packet; and an arbitration module coupled to the timing module and receiving a data packet transferring request, wherein if the first terminal device is a non-periodic device, the arbitration module places a higher priority on the data packet transferring request than the SOF packet transferring request, such that when the SOF packet transferring request and the data packet transferring request collide, an SOF packet corresponding to the colliding SOF packet transferring request is reserved and delayed to be transferred after a data packet corresponding to the colliding data packet transferring request.