Patent ID: 7482224
Filing Date: 2009-01-27
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor integrated circuit device, comprising: providing an integrated circuit substrate having an SRAM cell region, a flash memory cell region, and a logic circuit region; forming an isolation layer in a predetermined region of the substrate to define an SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively; and forming an SRAM cell gate pattern, a flash memory cell gate pattern and a logic gate pattern crossing over the SRAM cell active region, the flash memory cell active region and the logic transistor active region, respectively, wherein the SRAM cell gate pattern is formed to have a main SRAM cell gate electrode and a dummy SRAM cell gate electrode which are sequentially stacked, the flash memory cell gate pattern is formed to have a control gate electrode crossing over the flash memory cell active region as well as a floating gate interposed between the control gate electrode and the flash memory cell active region, and the logic gate pattern is formed to have a main logic gate electrode and a dummy logic gate electrode which are sequentially stacked, and wherein the main SRAM cell gate electrode and the main logic gate electrode are formed from a same material layer as the floating gate, and the dummy SRAM cell gate electrode and the dummy logic gate electrode are formed from a same material layer as the control gate electrode.