Patent ID: 6177313
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, comprising:on a semiconductor substrate, defining respective active areas for transistors of ROM cells, electrically erasable non-volatile memory cells, and low- and high-voltage transistors;depositing a layer of gate oxide over said active areas;depositing a polysilicon layer over the gate oxide layer;masking, and then etching, the polysilicon layer to define respective gate regions of the low-voltage transistors;masking the polysilicon layer to cover a first group of the transistors of the ROM cells while leaving exposed a second group of the transistors of the ROM cells, and implanting a first dopant species in the the polysilicon layer at gate regions of the exposed transistors;removing the mask from the polysilicon layer, and implanting a second dopant species in the polysilicon layer at gate regions of the first group of transistors; andmasking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors and non-volatile memory cell transistors.