Patent ID: 8850456
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A system comprising: a first node including at least one multi-core processor having a plurality of cores, wherein each core can execute a process; and a memory coupled to the at least one multi-core processor, wherein the memory includes instructions that enable the system to automatically determine a minimum number of fabrics and virtual channels to be activated to handle pending connection requests and data transfer requests, to prevent processing of new connection requests and data transfer requests outside of a predetermined communication pattern, and to update a count of expected connections when a first spin count to control activity of a progress engine reaches a predetermined value, to thereafter set the first spin count to an initial value, update a count of expected reads when a second spin count to control activity of the progress engine reaches the predetermined value, and thereafter set the second spin count to the initial value, and to cause the first spin count and the second spin count to be set to a maximum value to reduce querying of the first and second fabrics and associated virtual channels.