Patent ID: 6047336
Filing Date: 2000-04-04
Classification: G06F

Abstract:
A system for transferring data between a processor memory and a slave device comprising:first control means connected to the memory and the slave device for operating the memory and transferring data between the memory and the slave device;second control means connected to the first means and to the slave device;means in the slave device for sending a request (DMAR) signal for a data transfer cycle to the second control means;said second control means in response to the DMAR sending a request for a data transfer cycle to the first control means;said first control means in response to the request from the second control means effecting the requested transfer between the memory and the slave device and acknowledging the same to the second means; andsaid second means in response to the acknowledgement from the first means sending an acknowledgement to the slave indicating completion of the data transfer cycle and speculatively requesting another data transfer cycle from the first means and following initiation of the speculative transfer cycle aborting the speculative transfer cycle if the slave device has not requested another data transfer cycle.