Patent ID: 9224753
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A semiconductor memory device, comprising: a substrate; a stack on the substrate, the stack including insulating patterns and gate electrodes alternately and repeatedly stacked on each other; and vertical channel structures penetrating the insulating patterns and the gate electrodes, each of the gate electrodes including first and second gate conductive layers, each of the gate electrodes including a first region between an outer side of the stack and the vertical channel structures and a second region between the vertical channel structures, the first gate conductive layer in the first region being adjacent to the vertical channel structures and including a truncated end portion, the second gate conductive layer in the first region having a portion that is adjacent to the vertical channel structures and is covered by the first gate conductive layer, the second gate conductive layer in the first region having an opposite portion, that is adjacent to the outer side of the stack and is not covered by the first gate conductive layer, the first gate conductive layer in the second region being extended to continuously cover top, bottom, and side surfaces of the second gate conductive layer in the second region.