Patent ID: 6079024
Filing Date: 2000-06-20
Classification: G06F,Y02D

Abstract:
A bus interface unit coupled to a data transfer bus comprising:a first buffer coupled to said data transfer bus, configured to receive data from a device coupled to said data transfer bus and to store said data for retrieval by a processing core;a second buffer coupled to said data transfer bus, configured to receive data from said processing core and store said data for retrieval by a device coupled to said data transfer bus;a clock unit coupled to said data transfer bus, said first buffer and said second buffer, wherein said clock unit is configured to output a first clock signal to said first data buffer and a second clock signal to said second data buffer, to selectively disable said first clock signal when said first buffer is inactive, to selectively disable said second clock signal when said second buffer is inactive, to selectively enable said first clock signal when said first buffer is active, and to selectively enable said second clock signal when said second buffer is active.