Patent ID: 6184121
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method in which a multilayer microelectronic interconnect structure is fabricated byapplying a double layer thickness of a thermally stable and easily processable first dielectric material on a semiconductor wafer, said first dielectric material having a top layer and a lower layer;patterning and etching trenches for wiring tracks on said top layer and vias in said lower layer of said first dielectric material;depositing a thin electrically conductive barrier/adhesion layer in said trenches and vias and overfilling said trenches and vias with a thick conductive wiring layer metal;planarizing said wiring layer metal by etching or polishing to achieve a coplanar inlaid structure of conductors and vias embedded as metal features in said first dielectric material;repeating the above process until a requisite number of wiring levels in said interconnect structure are fabricated;removing said first dielectric material from all areas of said wafer not directly covered by said conductors by means of an etching process while leaving said first dielectric material intact under said metal features;optionally applying a thin conformal passivation layer to cap and protect the exposed metal features;annealing the etched structure at an elevated temperature in a reducing atmosphere to mitigate any plasma process induced damage;laminating a thin taut insulating cover layer to the top surface of the passivated metal features;optionally depositing a thin insulating environmental barrier layer on top of said cover layer;etching terminal vias in said optional insulating environmental barrier layer, insulating cover layer and said thin conformal passivation layer to provide access for terminal pad contacts; anddepositing and patterning terminal metal pads at said via locations to complete said interconnect structure.