Patent ID: 6470429
Filing Date: 2002-10-22
Classification: G06F

Abstract:
An apparatus for identifying non-cacheable requests to main memory in a computer system with multiple processors, comprising:a memory cache coupled to a first bridge unit; a main memory coupled to said first bridge unit; a processor coupled to said first bridge unit, said processor transmitting requests for data to the main memory, wherein said first bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in a plurality of processor caches in the computer system; and a cache coherence directory coupled to said cache coherence controller, said cache coherence directory including the addresses of data stored in each of the processor caches and the state of the data, wherein said first bridge unit identifies requests for data to main memory as cacheable or non-cacheable, and said first bridge unit requests the cache coherence controller to bypass the cache coherence directory lookup for non-cacheable data.