Patent ID: 8917280
Filing Date: 2014-12-23
Classification: G09G

Abstract:
1. An apparatus for controlling display device, comprising: an image data buffer including a buffer memory, the image data buffer receiving input data including a plurality of groups of pixel data each representing values of a group of pixels that constitutes each of a plurality of lines that, in turn, constitutes each of a plurality of frames, in an order of the frames and further in an order of the lines in each of the frames, and writing the groups of pixel data in the buffer memory in synchronous with a first clock signal, a differential value calculation circuit that calculates, in each of the plurality of frames, a differential value between a number of cycles of a second clock signal during a period of a specified number of cycles of the first clock signal and an expected value thereof: and a read control circuit, that: commands, in each of the first and following ones of the frames, the buffer memory to read and output to the display device, in each of the assigned periods, corresponding one of the groups of pixel data in synchronous with the second clock signal, wherein the differential value is corrected, based upon both a number of lines in the entire respective frame and a number of lines in a valid data area, to reflect an amount of change in latency in the respective frame for which the differential value is calculated.