Patent ID: 6941414
Filing Date: 2005-09-06
Classification: G06F,G11C

Abstract:
1. A high speed DRAM, comprising: a DRAM memory; a cache memory comprising a single port SRAM; a read register coupled between the cache memory and the DRAM memory, for transferring data from the cache memory to the DRAM memory; a write register coupled between the DRAM memory and the cache memory, for transferring data from the DRAM memory to the cache memory; a first bi-directional data bus set coupled between the memory and both the read register and the write register to perform pipeline memory operations, wherein data flows through the bi-directional bus in a first direction from the cache memory to the read register, and data flows through the bi-directional bus in a second opposite direction from the write register to the cache memory, such that opposite direction data flows share the same bi-directional data bus in different cycles; a second data bus set coupled between the read register and the DRAM memory; a third data bus set coupled between the DRAM memory and the write register.