Patent ID: 7881422
Filing Date: 2011-02-01
Classification: H03K

Abstract:
1. A frequency divider circuit comprising: a counter configured to receive a clock input signal and a divisor, the divisor having an odd value, the counter repetitively counting clock cycles of the clock input signal up to the divisor to generate a count; a control circuit configured to receive the count, the divisor, and the clock input signal, the control circuit generating one or more control signals to control a state of a clock output signal of the frequency divider circuit; and a half cycle adjust circuit configured to receive the clock input signal and the one or more control signals from the control circuit and provide an additional one-half cycle adjustment of at least one of the control signals to control the clock output signal, wherein the clock output signal transitions to a first state in response to a first transition of at least one of the control signals between the first state and a second state, and wherein the clock output signal transitions to the second state one-half of a cycle of the clock input signal after a second transition of at least one of the control signals between the first state and the second state.