Patent ID: 8124973
Filing Date: 2012-02-28
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: a semiconductor film over an insulating surface; a gate insulating film over the semiconductor film; a first conductive layer and a first capacitor wiring over the gate insulating film; a second conductive layer over the first conductive layer; a second capacitor wiring over the first capacitor wiring; a first insulating layer over the second conductive layer and the second capacitor wiring; a second insulating layer over the first insulating layer, the second insulating layer having a first contact hole over the second capacitor wiring; a first wiring in the first contact hole and over a part of the second insulating layer; a third insulating layer over the first wiring and the second insulating layer; and a second wiring over the third insulating layer, in a second hole formed in the third insulating layer and in a third contact hole formed in the first, second and third insulating layers, wherein the semiconductor film includes: wherein an end portion of the first conductive layer extends beyond an end portion of the second conductive layer, wherein the LDD regions overlap the first conductive layer with the gate insulating film interposed therebetween, wherein the second conductive layer has a tapered shape in an end portion of the second conductive layer in cross section, wherein the first conductive layer comprises at least a first element selected from the group consisting of Ta, W, Ti, Mo, Al, and Cu and the second conductive layer comprises at least a second element selected from the group consisting of Ta, W, Ti, Mo, Al, and Cu, wherein the first element is different from the second element, wherein an element in the first capacitor wiring is a same as the first element and an element in the second capacitor wiring is a same as the second element, and wherein the semiconductor film and the second capacitor wiring are electrically connected to each other via the first wiring and the second wiring.