Patent ID: 6700425
Filing Date: 2004-03-02
Classification: H03K

Abstract:
A multi-phase clock generator, comprising:a master-slave flip flop that is configured to generate a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency, said master-slave flip-flop comprising: a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs, said master stage comprising: a master differential amplifier circuit that is responsive to the first one of the first pair of clock signals and comprises a first pair of input transistors; and a master pair of cross-coupled logic gates that each have an input electrically connected to a current carrying terminal of a respective one of the first pair of input transistors; and a slave stage that is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled to the first pair of differential inputs.