Patent ID: 7944734
Filing Date: 2011-05-17
Classification: G11C

Abstract:
1. A nonvolatile static random access memory (SRAM) device, comprising: a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device; and a single port coupled to the SRAM cell, the single port comprising a pair of pass gates, the pair of magnetic spin transfer devices and a pair of bitlines; wherein the pair of bitlines is configured for read and write operations of the SRAM cell during power on conditions, and wherein the pair of bitlines also serves as a programming node.