Patent ID: 9048824
Filing Date: 2015-06-02
Classification: G11C,H03K,H04L

Abstract:
1. A method, comprising: for a driver comprising a plurality of parallel transistor segments each comprised of a pull-up transistor and a pull-down transistor, where, a percentage of the parallel transistor segments impose logic-low de-emphasis by having a respective pull-up transistor enabled while said driver is driving a logic level low with a respective pull-down transistor of the other transistor segments and impose logic-high de-emphasis by having a respective pull-down transistor enabled while said driver is driving a logic level high with a respective pull-up transistor of the other transistor segments, training the driver as follows: stepping respective transistor drive strength of the percentage of segments in a respective small increment to a new respective drive strength to adjust the logic-low and logic-high de-emphasis with fine granularity; adjusting respective transistor drive strength of the other segments while the percentage of segments are enabled to set the driver's impedance to a desired value; repeating the stepping and the adjusting until a desired logic-low de-emphasis, a desired logic-high de-emphasis and a desired driver impedance are achieved.