Patent ID: 8013650
Filing Date: 2011-09-06
Classification: H03K

Abstract:
1. A phase adjustment circuit for adjusting phases of a plurality of input signals, the circuit comprising: first to nth two-phase adjustment circuits, where n is a natural number, wherein an mth two-phase adjustment circuit, where m indicates an integer from 1 to n, includes: a first input terminal into which a 2m−1th signal is input; a second input terminal into which a 2mth signal is input; a first output terminal from which the 2m−1th signal after phase adjustment is output; a second output terminal from which the 2mth signal after phase adjustment is output; a first logic circuit for receiving the 2m−1th and 2mth signals from the first and second input terminals and generating a signal whose logic changes in a predetermined manner when either the 2m−1th or 2mth signal goes to a certain logic level; a second logic circuit for receiving the 2m−1th and 2mth signals from the first and second input terminals and generating a signal whose logic changes in the predetermined manner when the 2m−1th and 2mth signals both go to the certain logic level; a first delay circuit having a signal delay equal to that of the second logic circuit and configured to output to the first output terminal a signal obtained by delaying the signal generated by the first logic circuit; and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to output to the second output terminal a signal obtained by delaying the signal generated by the second logic circuit.