Patent ID: 6668344
Filing Date: 2003-12-23
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of memory blocks, each having a plurality of memory cells provided at intersecting points of a plurality of bit lines, a first spare bit line, and a second spare bit line which cross a plurality of word lines; a plurality of column selection lines, each provided for one of the plurality of bit lines of the plurality of memory blocks; a first spare column selection line provided for the first spare bit line of the plurality of memory blocks; a second spare column selection line provided for the second spare bit line of the plurality of memory blocks; and a redundancy circuit having a first input node to which an access address including a first access information for designating one of the plurality of memory blocks and a second access information for designating one of the plurality of column selection lines is supplied, a defect address storing circuit for storing a plurality of defect addresses, a first output node which is coupled to the first spare column selection line to make the first spare column selection line active when the access address coincides with one of the plurality of defect addresses, and a second output node connected to the second spare column selection line to make the second spare selection line active when the access address coincides with another one of the plurality of defect addresses, wherein the defect address storing circuit further includes: a first storage set which is provided to determine selection of the first spare column selection line, for storing a first information to designate one of the plurality of column selection lines related to a first defect; a second storage set which is provided to determine selection of the second spare column selection line, for storing a second information to designate one of the plurality of column selection lines related to a second defect; a third storage set for storing a third information for designating a first memory block as one of the plurality of memory blocks related to the first defect and a fourth information for designating a second memory block as one of the plurality of memory blocks related to the second defect, wherein the third storage set has: a plurality of first storage elements for storing addresses of independent memory blocks which are different from each other in the first and second memory blocks; and a plurality of second storage elements for storing the number of duplex selection of addresses which are repeated in the independent memory blocks.