Patent ID: 6677782
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A semiconductor logic circuit comprising:a first load provided between a first power source terminal and a first node and controlled by a control signal and a second load provided with said first power source terminal and a second node and controlled by said control signal; a logic circuit for input provided between said first node and a third node for electrically connecting said first node and said third node according to an input signal; a field effect transistor for reference paths, the source and the drain of which are provided between said second node and said third node and the gate of which is connected to said first node; and an activation circuit provided between said third node and a second power source terminal and controlled by said control signal; wherein: a reset circuit for reducing the pulse length of a signal output from said semiconductor logic circuit is provided, wherein: said reset circuit is composed of at least either of a first or second reset circuit: a first reset circuit provided between said first node and said logic circuit for input, one terminal of which is connected to said first node and the other terminal of which is connected to said logic circuit for input for reducing the pulse length of said first node by a first reset signal; and a second reset circuit provided between said second node and said field effect transistor for reference, one terminal of which is connected to said second node, the other terminal of which is connected to said field effect transistor for reference for reducing the pulse length at said second node by a second reset signal; and the gate of said field effect transistor for reference is connected to the other terminal of said first reset circuit or said first node.