Patent ID: 6743979
Filing Date: 2004-06-01
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate with circuitry formed therein, the substrate having a peripheral edge, a top most electrically conductive layer, an underlying electrically conductive layer, electrically conductive outer bonding pads disposed in an outer ring adjacent the peripheral edge of the substrate, the outer bonding pads formed within the top most electrically conductive layer, the outer bonding pads having a first width, electrically conductive inner bonding pads disposed in an inner ring interior to and concentric with the outer ring of bonding pads, the inner bonding pads formed within the top most electrically conductive layer, the inner bonding pads having a second width, electrically conductive inner connectors adapted to electrically connect the inner bonding pads to the circuitry, the inner connectors formed within the underlying electrically conductive layer, the inner connectors having a third width that is less than the second width of the inner bonding pads, thereby defining a gap having a fourth width between the inner connectors, and electrically conductive outer connectors adapted to electrically connect the outer bonding pads to the circuitry, the outer connectors formed within the underlying electrically conductive layer, the outer connectors having a fifth width that is less than the fourth width of the gap between the inner connectors.