Patent ID: 7870414
Filing Date: 2011-01-11
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a delay-locked loop (DLL) for compensating for a skew between an external clock and an internal clock, and outputting a delay-locked loop (DLL) clock; an oscillation unit for providing a reference clock; a selection unit for selecting either the DLL clock or the reference clock according to a selection signal enabled in a test mode, and providing a selected clock as an input clock; and a clock tree circuit for adjusting a duty cycle of the input clock, wherein when the reference clock is input as the input clock by the selection unit, the clock tree circuit adjusts a duty cycle of the reference clock by an adjustment ratio set such that the reference clock output by the clock tree circuit has a predetermined duty cycle, when the DLL clock is input as the input clock by the selection unit, the clock tree circuit adjusts a duty cycle of the DLL clock by applying the adjustment ratio to the DLL clock, and when the DLL clock is input as the input clock by the selection unit, and the DLL clock output by the clock tree circuit does not have the predetermined duty cycle, the DLL adjusts the duty cycle of the DLL clock.