Patent ID: 6700166
Filing Date: 2004-03-02
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells for storing data, wherein each memory cell includes a first inverter section including first and second transistors, said first and second transistors being respectively connected between first and second voltages and a first storage node and having opposite conductivity types, a second inverter section including third and fourth transistors, said third and fourth transistors being respectively connected between said first and second voltages and a second storage node and having opposite conductivity types, a fifth transistor for connecting a first signal line to said first storage node, a sixth transistor for connecting a second signal line complementary to said first signal line to said second storage node, a first gate line having a laminated structure of a first metal layer and a first polysilicon layer, for electrically coupling gates of said first and second transistors to said second storage node through a contact resistance between said first metal layer and said first polysilicon layer, and a second gate line having a laminated structure of a second metal layer and a second polysilicon layer, for electrically coupling gates of said third and fourth transistors to said first storage node through a contact resistance between said second metal layer and said second polysilicon layer.