Patent ID: 6441687
Filing Date: 2002-08-27
Classification: H03F

Abstract:
A bias voltage generating circuit operable to generate a bias voltage at an output node, the bias voltage generating circuit comprising:a first transistor having a base terminal coupled to the output node and an emitter terminal coupled to ground; a first resistance having a first terminal coupled to a supply voltage node, the first resistance having a second terminal coupled to a collector terminal of the first transistor; a second transistor having an emitter terminal coupled to the collector terminal of the first transistor, the second transistor having a base terminal connected to the collector terminal of the second transistor; and a second resistance having a first terminal coupled to the supply voltage node, the second resistance having a second terminal coupled to a collector terminal of the second transistor; a third transistor having a base terminal coupled to the base terminal of the second transistor, the third transistor having a collector terminal coupled to the supply voltage node, the third transistor having an emitter terminal coupled to the output node.