Patent ID: 6704842
Filing Date: 2004-03-09
Classification: G06F

Abstract:
A multi-processor computer system comprising:a plurality of memory units; a plurality of memory and coherence controllers operatively connected to the plurality of memory units; a plurality of caches operatively connected to the plurality of memory and coherence controllers; a plurality of processors operatively connected to the plurality of caches; a plurality of nodes, each of the plurality of nodes formed from a group consisting of at least one of the plurality of memory units, memory and coherence controllers, caches, processors, and a combination thereof; a communication switch connected to the plurality of nodes; a coherence directory connected to each of the plurality of memory and coherence controllers for maintaining coherence information for the memory units in the plurality of nodes connected to the communication switch; and a proactive speculative mechanism for proactively transferring data between the plurality of caches, the proactive speculative mechanism includes a proactive speculative forwarding mechanism for proactively providing data forwarding between the plurality of caches and a history compiler for proactively providing data forwarding between the plurality of caches based on history information wherein the history compiler for proactively providing data forwarding between the plurality of caches is based on history information regarding previous proactive speculative forwarding.