Patent ID: 6587504
Filing Date: 2003-07-01
Classification: H03H,H04L

Abstract:
An adaptive equalizer comprising:a filter processing unit including a plurality of cascaded processing stages provided corresponding to taps, each of said processing stages including (i) a first multiplier for multiplying an input signal by a corresponding tap coefficient, (ii) a delay stage for delaying an output signal of a preceding processing stage, and (iii) an adder for adding an output signal of said delay stage with an output signal of said first multiplier to provide an addition result to a next stage, the processing stage at a first stage including a multiplier for multiplying said input signal by a corresponding tap coefficient to provide a resultant signal to a subsequent processing stage at a next stage; and a tap coefficient set circuit for setting the tap coefficients according to an error between an output signal of said filter processing unit and a reference signal, said tap coefficient set circuit including a coefficient correction stage of a same structure provided corresponding to each tap coefficient and having a transfer function given by a product of the transfer function of an all pole filter and a transfer function of an all zero filter.