Patent ID: 6133130
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method for fabricating an embedded dynamic random access memory (DRAM) with a self-aligned silicide technology, in which the embedded DRAM is fabricated on a silicon substrate having a first metal-oxide semiconductor (MOS) transistor in a logic device region and a second MOS transistor in a memory device region, and the logic device region and the memory device region are separated by an isolation structure, wherein each of the MOS transistors has a gate including polysilicon and an interchangeable source/drain region on each side of the gate in the substrate, the method comprising:forming an insulating layer on the interchangeable source/drain regions of the second MOS transistor; andforming a self-aligned silicide (Salicide) layer over the exposed substrate at least on the exposed gates of the first and second MOS transistors and the interchangeable source/drain regions of the first MOS transistor.