Patent ID: 6573771
Filing Date: 2003-06-03
Classification: H03L

Abstract:
A clock synchronization circuit receiving an external clock signal, the clock synchronization comprising:a clock synchronization control means for outputting a normal delay clock signal by delaying the external clock signal for a predetermined time, and outputting an additional delay clock signal by delaying the normal delay clock signal; a phase mixing means for mixing phases of the normal delay clock signal and the additional delay clock signal from the clock synchronization control means, and outputting an internal clock signal; a control means for controlling the operation of the phase mixing means, and determining a phase of the internal clock signal; a shift register for controlling a delay time of the clock synchronization means; and a phase detecting means for comparing a phase of the external clock signal with a phase of the internal clock signal, and controlling the shift register to equalize the phases of the external clock signal and the internal clock signal.