Patent ID: 8669158
Filing Date: 2014-03-11
Classification: H01L

Abstract:
1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising: in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first thermally-grown oxygen-containing layer, a select gate of a first material, and a first dielectric layer, wherein the select gate is on the first thermally-grown oxygen-containing layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the select gate, and the first dielectric layer has a first opening in which the select gate is present in the first opening; in a logic region, forming over the semiconductor substrate a second thermally-grown oxygen-containing layer and a dummy gate of the first material and, after forming the first thermally-grown oxygen-containing layer and the select gate, forming a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the dummy gate is on the second thermally-grown oxygen-containing layer, a top surface of the second dielectric layer is substantially aligned with a top surface of the dummy gate, and the second dielectric layer has a second opening in which the dummy gate is present in the second opening; replacing the second thermally-grown oxygen-containing layer with a high-k gate dielectric and the dummy gate with a metal gate; forming a hard mask over the NVM region and the logic region; removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region, wherein the forming the hard mask is performed prior to the removing the first dielectric layer; forming a charge storage layer over the NVM region including over the select gate; forming a conductive layer over the charge storage layer; etching the conductive layer to form a control gate; and etching the charge storage layer to leave a remaining portion of the charge storage layer aligned to the control gate.