Patent ID: 6495478
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method for forming upon a semiconductor substrate within an integrated circuit microelectronics fabrication a low dielectric constant dielectric layer comprising:providing a semiconductor substrate; forming over the semiconductor substrate a patterned microelectronics conductive layer; forming over the semiconductor substrate and covering the patterned microelectronics layer a blanket first dielectric layer formed employing an organic polymer spin-on-polymer (SOP) low dielectric constant dielectric material whose dielectric constant is from about 2.5 to about 3.0; annealing the blanket first dielectric layer for a first time interval at a first temperature of about 400 degrees centigrade; forming a via contact hole dielectric etching mask layer upon the first dielectric layer; forming a blanket second dielectric layer over the semiconductor substrate; annealing the blanket second dielectric layer for a second time interval at a second temperature lower than the first annealing temperature of the blanket first dielectric layer; forming a via contact hole etching mask layer upon the blanket second dielectric layer and etching a via hole pattern through the blanket second and first dielectric layers to form a through via hole pattern to the patterned microelectronics conductor layer; and forming a conductive barrier layer and via stud patterned upper conductor layer upon and within the semiconductor substrate.