Patent ID: 8392929
Filing Date: 2013-03-05
Classification: G06F

Abstract:
1. In a computing system having a plurality of microprocessors each with the ability to access shared data from a system memory, a computer-implemented method that controls a microprocessor design for a transactional memory system that enables local buffering of write transactions at a first microprocessor while also monitoring conflicting write transactions at other microprocessors, in order to detect race conditions when threads processing on the first and one or more other microprocessors attempt to write conflicting states for shared data from system memory, the computer-implemented method comprising: at a first microprocessor initiating isolation hardware triggered by software running at the first microprocessor that acquires a software lock so that thereafter memory writes are buffered internal to the first microprocessor, and memory reads are monitored to detect if another microprocessor reads or writes to the memory location being monitored; establishing a level one data cache at the first microprocessor, the level one data cache comprising; a data column for caching data retrieved and operated upon by a thread executing at the first microprocessor; and a tag column which has a first portion for storing a physical address for the data retrieved and operated upon by the thread executing at the first microprocessor, and a second portion for storing at least the following indicators relating to the data retrieved and operated upon by the thread executing at the first microprocessor: (i) a read monitor (RM) indicator that determines if the data retrieved and operated upon by the thread executing at the first microprocessor is written to by another thread executing at another microprocessor; (ii) a write monitor (WM) indicator that determines if the data retrieved and operated upon by the thread executing at the first microprocessor is read by or written to by another thread executing at another microprocessor; and (iii) a buffer (BUF) indicator that indicates whether the data retrieved from the level one data cache and operated upon by the thread executing at the first microprocessor is taken out of cache coherence; at a transactional status (TS) register of a thread executing at the first microprocessor, accumulating events based on the status of the RM, WM and BUF indicators stored in said second portion of the tag column so that loss of RM, loss of WM and/or loss of BUF will be indicated in the transactional status register if such occurs; and at a transactional condition (TC) register of the thread executing at the first microprocessor, accumulating events that define abort actions that are to occur in the event of the loss of RM, WM and/or BUF status for the data retrieved and operated upon by said thread executing at the first microprocessor, where any abort action will implement a hardware control transfer to a software abort handler; and determining, while isolated by the isolation hardware, that the level one data cache is out of resources and as a result, automatically selecting at least a portion of the data from the level one data cache and committing the selected portion of data to main system memory, thus freeing up the level one data cache without dooming or aborting memory isolation mode of the thread running at the first microprocessor, the portion of selected data committed to main memory no longer being isolated with respect to new reads and writes until such isolation is re-established.