Patent ID: 7945764
Filing Date: 2011-05-17
Classification: G06F,Y02D

Abstract:
1. A circuit arrangement, comprising: a double clocked vector execution unit configured to be clocked in a first mode by a first clock signal, and to be clocked in a second mode by a second clock signal that has a clock rate that is twice that of the first clock signal, the double clocked vector execution unit including first and second issue ports, wherein the double clocked vector execution unit is configured to, during each clock cycle, alternate between initiating execution of an instruction received from the first issue port and initiating execution of an instruction received from the second issue port; a multithreaded issue unit coupled to the first and second issue ports and responsive to the first clock signal, the multithreaded issue unit configured to receive instructions from a plurality of threads, the multithreaded issue unit further configured in the first mode to issue one instruction from among the plurality of threads per cycle of the first clock signal to at least one of the first and second issue ports such that the double clocked vector execution unit initiates execution of one instruction per cycle of the first clock signal, and further configured in a second mode to issue two separate instructions from among the plurality of threads to the first and second issue ports per cycle of the first clock signal such that the double clocked vector execution unit initiates execution of two instructions per cycle of the first clock signal.