Patent ID: 6222467
Filing Date: 2001-04-24
Classification: H04N

Abstract:
A bitstream decoding apparatus for performing a decoding operation within a single clock cycle which includes a bitstream decoder for decoding a bitstream input from a storing unit, a control logic for controlling the function of the bitstream decoder, and a video processor for converting the decoded bitstream into displayable pixel values, wherein the bitstream decoder comprises:a shifter for shifting a prescribed bitstream according to an input of a bitstream to be shifted, and for providing a shifted output;a variable length decoder for decoding the shifted output from the shifter into symbol and code referring to a code book to provide variable length decoded output;a fixed length decoder for extracting bits from the most significant bits of a symbol, to the extent prescribed by the control logic, from the output of the shifter to position the extracted bits as the least significant bits of the symbol;a zero-run & AC decoder for receiving the shifted output of the shifter and the variable length decoded output of the variable length decoder as an input to calculate zero-run and AC coefficient in the event that an escape code exists and to calculate AC coefficient using zero-run and AC level decoded by the variable length decoder in the event that an escape code does not exist and to provide an output;a first multiplexer for selecting the outputs from the variable length decoder, the fixed length decoder, and the zero-run & AC decoder according to the control of the control logic;a second multiplexer for selecting a bitstream to be shifted among a variable length bitstream input from the variable length decoder, a fixed length bitstream input from the control logic, and a 24-bit bitstream if an escape code of AC exists; anda first comparator for comparing the bitstream to be shifted selected from the second multiplexer with a predetermined bitstream to generate a read signal for application to the storing unit.