Patent ID: 6384623
Filing Date: 2002-05-07
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit having an active mode and a stand-by mode, comprising:a plurality of first lines, each of which extends in a first direction; a plurality of second lines, each of which is arranged to intersect with said first lines; and a plurality of circuits, each of which is coupled to a corresponding one of said first lines, respectively, and each of which includes a first logic circuit and a second logic circuit; wherein outputs of said first logic circuits are controlled to be at a first level in the stand-by mode and wherein outputs of said second logic circuits are controlled to a second level; wherein said first logic circuit is connected to a first operating point through a source/drain path of a first MOS transistor; wherein said second logic circuit is connected to a second operating point through a source/drain path of a second MOS transistor; and wherein said second MOS transistor receives a signal to reduce leak current flowing through said second logic circuit in the stand-by mode.