Patent ID: 6346747
Filing Date: 2002-02-12
Classification: C23C,H01L,Y10S

Abstract:
An electronic structure having layer of insulating material as an intralevel or interlevel dielectric in a back-end-of-the-line wiring structure comprising:a pre-processed semi-conducting substrate having a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material which comprises diamond-like carbon, said second layer of insulating material being in intimate contact with said first layer of insulating material, said first region of conductor being in electrical communication with said first region of metal, a second region of conductor being in electrical communication with said first region of conductor and being embedded in a third layer of insulating material comprising diamond-like carbon, said third layer of insulating material being in intimate contact with said second layer of insulating material, a dielectric RIE hard mask/polish stop layer on top of said second layer of insulating material, and a dielectric diffusion barrier layer for stopping Cu diffusion on top of and contiguous to said RIE hard mask/dielectric polish stop layer.