Patent ID: 6897540
Filing Date: 2005-05-24
Classification: H01L

Abstract:
1. An integrated circuit comprising: a) a semiconductive substrate; b) a layer of dielectric material over the substrate, the dielectric material layer having a base surface and a raised surface, the raised surface being raised out from the base surface and having at least one beveled edge with a bevel less than or equal to about 45° and a step parallel to the base surface; c) a pair of spaced, adjacent, chemical reaction or diffusion barrier material lines with a spaced, adjacent portion of the pair of barrier material lines extending over the same at least one beveled edge from the base surface to the step of the raised surface, wherein the spaced pair of barrier material lines are substantially void of residual shorting stringers extending therebetween; and d) a pair of spaced, adjacent, conductive material lines over the pair of barrier material lines, the conductive material lines laterally coextending with the barrier material lines at least within a region directly over the at least one beveled edge.