Patent ID: 6806901
Filing Date: 2004-10-19
Classification: H04N

Abstract:
A processing circuit for processing the output of a charge coupled device (CCD), said processing circuit comprising a plurality of stages, a first stage contained in said plurality of stages comprising:a first digital to analog converter (DAC) generating a first voltage in response to receiving a first digital value; a correlation double sampler (CDS) receiving an input signal via a first sampling capacitor, wherein said input signal comprises said output of said CCD; a first feedback capacitor coupled in parallel to said CDS; and a first DAC capacitor coupled to said first DAC, said first DAC capacitor being charged by said first voltage, a second terminal of said first DAC capacitor being coupled to said first feedback capacitor, wherein the output of said CDS contains an amplified component of said input signal less an amplified component of said first voltage, wherein the ratio of capacitances of said first sampling capacitor and said first DAC capacitor is maintained a constant.