Patent ID: 6245627
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of fabricating a load resistor for an SRAM, adapted for a semiconductor substrate and at least having a buried contact and a first polysilicon layer formed on a portion of the buried contact, comprising:providing an inter-layer dielectric layer on the semiconductor substrate;forming an opening within the inter-layer dielectric layer to expose the first polysilicon layer;forming a doped poly via in the opening to form a load resistor, wherein the resistivity of the load resistor depends on a dosage of dopants in the doped poly via;forming a contact window in the inter-layer dielectric layer, wherein the contact window exposes a portion of the substrate;forming a contact to fill the contact window; andforming a patterned metallic interconnect on the inter-layer dielectric layer, wherein the patterned metallic interconnect respectively covers the doped poly via and the contact and the doped poly via and the contact are electrically coupled with each other.