Patent ID: 8872303
Filing Date: 2014-10-28
Classification: H01L

Abstract:
1. An integrated circuit chip pad comprising: a main pad portion comprising a plurality of stacked metal features in a plurality of interconnect metal layers of the IC, each one of the plurality of interconnect metal layers having a sole continuous one of the plurality of stacked metal features in the main pad portion, the plurality of stacked metal features being coupled together through arrays of main stacking vias; and a ring pad portion comprising a plurality of stacked metal rings in the plurality of interconnect metal layers of the IC, the plurality of stacked metal rings being coupled together through ring stacking vias, wherein each one of the plurality of stacked metal rings at least partially surrounds a respective one of the plurality of stacked metal features, wherein the main pad portion is coupled to the ring pad portion through one or more bridges in an upper conductive layer, and wherein the main pad portion is coupled to an overlying pad bonding surface, wherein the one or more bridges are separated from the pad bonding surface.