Patent ID: 7437697
Filing Date: 2008-10-14
Classification: G06F

Abstract:
1. A method for determining criticality probability of an edge of a timing graph of a circuit, comprising: forming a directed acyclic timing graph corresponding to a circuit being timed; performing statistical timing of the circuit; for each edge of interest, defining a cutset that divides the timing graph into a plurality of parts; wherein a first part of the plurality of parts includes a source node of the timing graph and a second part of the plurality of parts includes a sink node of the timing graph; determining an edge slack for each edge in the cutset; computing a statistical maximum of all edge slacks in the cutset; inferring edge criticality probabilities of each edge from the statistical maximum; and wherein an early mode statistical edge slack is a statistical sum of an early mode source node statistical arrival time, a negative of an early mode sink node statistical required arrival time, and an early mode delay of the edge.