Patent ID: 6306744
Filing Date: 2001-10-23
Classification: H01L

Abstract:
A method for making an integrated circuit comprising the steps of:providing a first voltage source;providing a substrate;forming integrated circuitry in selected first portions of the substrate;forming a plurality of first conductive power bus tiers on the substrate wherein each of the first conductive power bus tiers are electrically coupled in parallel to the first voltage source;forming a plurality of filter capacitors in selected second portions of the substrate, wherein the filter capacitors comprise a first plate and a second plate which are separated by a capacitor dielectric and the first plate forms a bus strap coupling to each of the plurality of first conductive power bus tiers;forming a third plate formed in a common plane with the first plate and separated from the second plate by a capacitor dielectric;providing a second voltage source;forming a plurality of second conductive power bus tiers on the substrate wherein each of the second conductive power bus tiers are electrically coupled in parallel to the second voltage source and the third plate forms a bus strap coupling to each of the plurality of second conductive power bus tiers.