Patent ID: 9224702
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A three-dimension (3D) integrated circuit (IC) package comprising: a package substrate having a surface, and at least one integrated circuit (IC) chip and at least one transient voltage suppressor (TVS) chip are arranged on said surface and electrically connected with each other, and said IC chip is independent from said TVS chip; a plurality of conduction plugs arranged in said TVS chip; a plurality of first conduction bumps arranged on conduction areas of said surface and respectively arranged under said conduction plugs, and said TVS chip is electrically connected with said conduction areas through said first conduction bumps and said conduction plugs; and a plurality of second conduction bumps respectively arranged on said conduction plugs, and said IC chip is electrically connected with said conduction areas and said TVS chip through said first and second conduction bumps and said conduction plugs, and said TVS chip further comprises: a P-type semiconductor substrate, and said conduction plugs are arranged in said P-type semiconductor substrate; a P-type well arranged in said P-type semiconductor substrate and having a first P-type heavily-doped area and a first N-type heavily-doped area; and an N-type well arranged in said P-type semiconductor substrate and having a second P-type heavily-doped area and a second N-type heavily-doped area, and said conduction plugs, said P-type well and said N-type well are independent to each other.