Patent ID: 6169968
Filing Date: 2001-01-02
Classification: G06F

Abstract:
An apparatus for estimating a performance of an integrated circuit in design at a register transfer level, comprising: an estimation library for storing estimation models used for estimating performances of respective elements representing said integrated circuit at the register transfer level; a driver library for storing driver models of modeled relationships between driving abilities and areas of drivers for driving a line; and trade-off estimation means for estimating a performance of a target integrated circuit at the register transfer level represented by using connections between said elements which satisfies a predetermined constraint, by applying said estimation models stored in said estimation library to respective elements of said target integrated circuit and by changing application of said driver models stored in said driver library if necessary, wherein said trade-off estimation means includes: an area priority estimation part for estimating a minimum area of said target integrated circuit and a delay time of each register-to-register path attained when said target integrated circuit has said minimum area; a timing analysis part for determining whether or not delay time of each register-to-register path of said target integrated circuit satisfies a timing constraint given to said target integrated circuit; a performance candidate list generation part for generating, with regard to each element on a register-to-register path whose delay time does not satisfy the timing constraint, a performance candidate list in which performance candidates are enumerated, by changing the application of said driver models; and a performance candidate selection part for selecting, with regard to each element on said register-to-register path, a performance candidate from said performance candidate list generated by said performance candidate list generation part so that the delay time of said register-to-register path satisfies the timing constraint and an increase in an area of said target integrated circuit is minimized, and for estimating the area of said target integrated circuit and the delay time of said register-to-register path attained by applying said selected performance candidate.