Patent ID: 6043118
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A method of fabricating a semiconductor memory circuit device having an array of memory cells arranged in matrix form, each of said memory cells including a first MISFET having a gate, a source and a drain and an information storing capacitor having first and second electrodes and a dielectric film formed between the first and second electrodes, and the device also having peripheral circuitry constituted by a plurality of second MISFETs, each second MISFET having a gate, a source and drain, comprising the steps of:(a) providing a semiconductor substrate having a first region for forming said memory cells and a second region for forming said peripheral circuitry;(b) forming said first MISFET in said first region and forming the second MISFET in said second region;(c) forming a first insulating film over said first and second MISFETs, said first insulating film having a first through-hole, defined by a sidewall of the first insulating film, in said first region, and a part of said sidewall being arranged above said gate electrode of said first MISFET;(d) forming said first electrode, said dielectric film and said second electrode in said first through-hole and along said sidewall of said first through-hole;(e) forming a second insulating film over said first insulating film in said first region and in said second region;(f) forming a second through-hole in said first and second insulating films in said second region; and(g) forming a first conductive film on said second insulating film in said first region and in said second region; and(h) patterning said first conductive film so as to form a first wiring in said first region and a second wiring in said second region,wherein said second electrode extends over said first insulating film in said first region.