Patent ID: 6735753
Filing Date: 2004-05-11
Classification: G06F

Abstract:
A method of fabricating a semiconductor device comprising the steps of:(a) positioning a plurality of first metal interconnection patterns, a plurality of first via patterns and a plurality of second metal interconnection patterns in such a way that each of antenna ratios of the first metal patterns, the first via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio; (b) broadening a width of each of the first metal patterns by a minimum line width of the first metal patterns; (c) connecting the broadened first metal patterns at a first area where a distance between the broadened first metal patterns is smaller than a minimum size of the first via patterns; (d) after the step (c), extracting a second area where the first metal patterns and the second metal patterns do not exist; (e) placing a plurality of additional first via patterns each having a minimum size with a minimum pitch in the second area; and (f) deleting the additional first via pattern which do not meet a minimum allowable distance between the first metal patterns and the first via patterns positioned in the step (a).