Patent ID: 8843698
Filing Date: 2014-09-23
Classification: G06F,G11C

Abstract:
1. Flash memory apparatus including: a plurality of memory portions, and a controller operative to: reserve for data retention purposes, for at least a first duration of time, only certain memory portions from among said plurality of memory portions; allocate data, during said first duration of time, only to said certain memory portions, thereby to define at least one of the plurality of memory portions other than to said certain portions as a retired memory portion for said first duration of time; determine to copy data from a certain memory portion of said certain memory portions to a retired memory portion based upon a relationship between an effective cycle count of the certain memory portion and an effective cycle count of the retired memory portion; wherein an effective cycle count of any memory portion is responsive to a number of erase-write cycles that the memory portion has undergone and to an effective duration of time the memory portion had available to recover from erase-write cycles it has undergone; wherein the effective duration of time the memory portion had available to recover is a function of a length of a time period the memory portion had available to recover from the erase-write cycles that the memory portion has undergone and a temperature of the memory portion during the time period; and copy the data from the certain memory portion to the retired memory portion.