Patent ID: 7262993
Filing Date: 2007-08-28
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a first capacitor, one end of the first capacitor being connected to a floating node; a detection transistor, a gate electrode of the detection transistor being connected to the floating node; a second capacitor, one end of the second capacitor being connected to the floating node, and the other end of the second capacitor being connected to a drain of the detection transistor; and an auxiliary capacitor, one end of the auxiliary capacitor being connected to the floating node, wherein, at least during write operation, a control gate voltage is supplied to the other end of the first capacitor, a control drain voltage is supplied to the other end of the second capacitor, and a capacitance ratio correction voltage which is higher than a voltage of the floating node is supplied to the other end of the auxiliary capacitor.