Patent ID: 6734485
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A vertical DRAM cell structure, comprising:a semiconductor substrate of a first conductivity type having an active region and two first-type shallow-trench-isolation (STI) regions, wherein said active region is located between said two first-type STI regions; a DRAM cell comprising a trench region, a trench isolation region, and a common-drain region being formed on said semiconductor substrate, wherein said trench region being located between said common-drain region and said trench isolation region comprises a deep-trench region being located in said active region and said trench isolation region comprises a second-type STI region outside of said deep-trench region being located in said active region; said two first-type STI regions comprising two first-type raised field-oxide layers; said second-type STI region comprising a second-type raised field-oxide layers; said deep-trench region comprising: a trench capacitor being formed in a lower portion of a deep trench, a collar-oxide layer together with a capacitor-node connector being formed in a middle portion of said deep trench, and a vertical transistor region being formed in an upper portion of said deep trench; said trench capacitor comprising an upper capacitor node being formed over a capacitor-dielectric layer and said capacitor-dielectric layer being formed over a lower capacitor node in said semiconductor substrate; said vertical transistor region comprising a gate-dielectric layer over a portion of a sidewall of said deep trench together with a conductive-gate node being formed over an isolation silicon-dioxide node, said isolation silicon-dioxide node being formed over a source conductive node, and said source conductive node being formed over said capacitor-node connector and said collar-oxide layer, wherein said conductive-gate node, said isolation silicon-dioxide node, said source conductive node, and said capacitor-node connector are patterned by a first sidewall dielectric spacer being formed over an outer sidewall of said common-drain region; and said common-drain region being located in a side portion of said trench region comprising: a common-drain diffusion region of a second conductivity type being formed in an upper surface portion of said semiconductor substrate of said active region, a fourth sidewall dielectric spacer being formed over an outer sidewall of said trench region, and a flat bed located outside of said fourth sidewall dielectric spacer being formed by said common-drain diffusion region in said active region and two first-type fifth raised field-oxide layers in said two first-type STI regions, wherein said active region under said common-drain diffusion region comprises a deep implant region of said first conductivity type being formed in said semiconductor substrate near a middle portion outside of said gate-dielectric layer, a common-source diffusion region of said second conductivity type being formed in said semiconductor substrate near an outside portion of said source conductive node, and a deeper implant region of said first conductivity type being formed in said semiconductor substrate near a middle portion outside of said collar-oxide layer.