Patent ID: 6661686
Filing Date: 2003-12-09
Classification: G11C

Abstract:
A content addressable memory (CAM) architecture comprising:a CAM array including a plurality of rows of CAM cells to compare, in a first compare operation, comparand data with data stored in the rows and output match results on a plurality of match signal lines; a timed storage circuit having data inputs coupled to the match signal lines and an enable input; and a dynamic timing generator circuit including a first compare circuit to perform a second compare operation to generate an enable signal coupled to the enable input to enable the timed storage circuit to capture the match results, wherein the dynamic timing generator circuit further comprises: a match comparison timing circuit including the first compare circuit and having an output to assert a first signal indicative of when the match results indicate that the comparand data matches the data stored in at least one of the rows of CAM cells of the CAM array; a mis-match comparison timing circuit including a second compare circuit and having an output to assert a second signal indicative of when the match results indicate that the comparand data mismatches the data stored in at least another one of the rows of CAM cells of the CAM array; and a select circuit having inputs coupled to receive the first and second signals, and having an output to provide the enable signal.