Patent ID: 7116146
Filing Date: 2006-10-03
Classification: H03L

Abstract:
1. A digital DLL device that provides a delay to an input clock signal so as to equally divide a clock cycle T into N parts (N being an integer), the digital DLL device comprising: N first variable delay sections each of which is formed of an arbitrary number of unit delay buffers connected in series with one another; N second variable delay sections each of which is connected with the last stage of said first variable delay sections, each of said second variable delay sections being formed of an arbitrary number of unit delay buffers connected in series with one another; a phase comparison section that makes a compare between the phase of said input clock signal and the phase of an output signal which is said input signal having been delayed while passing through all said first and second variable delay sections, and outputs a result of said comparison; and a delay control section that calculates a total number of unit delay buffers S required based on said phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of said first variable delay sections, sets a remainder R of S divided by N to be a total number of unit delay buffers for said second variable delay sections, and allocates R to said second variable delay sections, respectively.