Patent ID: 6870211
Filing Date: 2005-03-22
Classification: H01L

Abstract:
1. An integrated circuit comprising: a substrate having a single-crystal semiconductor region defining a major surface of said substrate; a plurality of first transistors having conduction channels disposed in a memory cell array region of said semiconductor region; a plurality of second transistors having conduction channels disposed in an external region of said semiconductor region outside of said memory cell array region; a dielectric region covering said first transistors and said second transistors, said dielectric region having a plurality of troughs, each said trough having a pair of vertical sidewalls, each said sidewall extending substantially in a single plane to said substrate; a plurality of bitline contacts disposed in said troughs, said bitline contacts including a plurality of conductive vias extending in a vertical direction normal to said major surface to contact said first transistors; a plurality of horizontally extending bitlines disposed in said troughs and conductively connected to said conductive vias, said bitlines extending over said memory cell array region in a horizontal direction substantially parallel to said major surface; and metallic conductive lines interconnecting said bitlines to said second transistors, said conductive lines differing from said bitlines in a patterned characteristic including at least one of horizontal width, vertical thickness, and placement relative to said bitlines.