Patent ID: 6529546
Filing Date: 2003-03-04
Classification: H04B

Abstract:
An improvement for aquiring synchronization to a chip-sequence signal having, a plurality of chips, embedded in a spread-spectrum signal, comprising:a set of M shift registers, where M is a number of shift registers, with each shift register for storing a replica or delayed replica of the chip-sequence signal, with each shift register having a plurality of taps corresponding to the plurality of chips, respectively; a plurality of comparators, connected to the plurality of taps of the set of M shift registers, respectively, for comparing, with a delay of 1/M chip duration per shift register of the set of M shift registers, the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal stored in said shift register, thereby generating for the plurality of taps of said shift register a plurality of compared values at said plurality of comparators, respectively, and thereby generating for each comparator from a sequence of comparisons, a multiplicity of compared values; a plurality of counters, connected to the plurality of comparators, respectively, for up and down counting, from each comparator, a respective multiplicity of compared values, respectively, appearing at an output of a respective comparator of said plurality of comparators, thereby generating a plurality of totals, respectively, at outputs of the plurality of counters; and selecting means, coupled to said plurality of counters, for selecting a value from the plurality of totals.