Patent ID: 6504437
Filing Date: 2003-01-07
Classification: H03L

Abstract:
A method for controlling a phase-lock loop (PLL) circuit for providing an output signal having a desired output frequency, said PLL circuit comprising a loop filter providing a first loop bandwidth, said PLL circuit receiving a reference signal having a reference frequency, said method comprising the steps of:(a) achieving lock between said reference signal and said output signal with said PLL circuit, said PLL circuit operating within constraints of said first loop bandwidth, wherein said PLL circuit comprises fractional-N division; (b) providing a second loop bandwidth, wherein said second loop bandwidth is more narrow than said first loop bandwidth; (c) providing integer-N division to said PLL circuit; and (d) achieving lock between said reference signal and said output signal with said PLL circuit, said PLL circuit operating within constraints of said second loop bandwidth.