Patent ID: 7345602
Filing Date: 2008-03-18
Classification: H03M

Abstract:
1. A pre-emphasis circuit comprising: a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output; a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data; a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter; said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter, wherein said second serial data is delayed by one clock period from said first serial data.