Patent ID: 7328295
Filing Date: 2008-02-05
Classification: G06F

Abstract:
1. An interrupt controller system comprising a plurality of interrupt controllers coupled in a daisy chain arrangement in order to prioritize interrupt requests generated by a plurality of interrupt sources, multiple ones of said plurality of interrupt controllers each including: an interrupt source interface for receiving interrupt requests generated by an associated plurality of interrupt sources; a daisy chain interface for receiving a single daisy chain interrupt request output by a further interrupt controller of said plurality of interrupt controllers lower in the daisy chain arrangement based on an additional plurality of interrupt requests generated by an additional plurality of interrupt sources, the daisy chain interface including a priority input for receiving a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request; prioritization logic for receiving the daisy chain priority signal and for applying predetermined prioritization criteria to determine a highest priority interrupt request selected from the daisy chain interrupt request and the interrupt requests generated by the associated plurality of interrupt sources, the prioritization logic including a priority encoder for determining an initial highest priority interrupt request selected from the interrupt requests generated by the associated plurality of interrupt sources, and determination logic for determining the highest priority interrupt request selected from the initial highest priority interrupt request and the daisy chain interrupt request; and an output interface for outputting the highest priority interrupt request, the output interface including a priority output for providing an output priority signal indicating a priority associated with the highest priority interrupt request, wherein a first of said multiple interrupt controllers is a final interrupt controller in the daisy chain arrangement, wherein the output interface of the final interrupt controller is configured for coupling to a processor used to process the highest priority interrupt request, and wherein the output interface of another of said multiple interrupt controllers is configured for coupling to a further interrupt controller of said plurality of interrupt controllers higher in the daisy chain arrangement.