Patent ID: 6430723
Filing Date: 2002-08-06
Classification: G11B,H03M

Abstract:
An error correcting device comprising:a receiving circuit for receiving data in a unit of a block; an error correcting circuit for detecting and correcting an error in the data received by the receiving circuit so as to provide error-corrected data; a transmission circuit for transmitting the error-corrected data; and a storage device having two areas each having a storage capacity corresponding to at least one block of the data, wherein the receiving circuit writes received data alternatively onto a first of the two areas of the storage device, said first of the two areas initially serving as a received data area and in the alternate writing serving as a corrected data area, the error correcting circuit corrects every one block of received data written onto a second of the two areas of the storage device, said second of the two areas initially serving as the corrected data area and in the alternate writing serving as the received data area, the transmission circuit reads the error-corrected data from a transmission data area corresponding to the received data area of the storage device to transmit the error-corrected data, when a first address refers to an address where the transmission circuit previously read the error-corrected data and a second address refers to an address where the transmission circuit reads the error-corrected data, the first and second addresses both belonging to a same one of the two areas of the storage device, the receiving circuit writes the data received by the receiving circuit into the first address of the same one of the two areas of the storage device while the transmission circuit is reading the error corrected data from the second address of the same one of the two areas of the storage device, and the error correcting circuit concurrently corrects an error in data stored in an other one of the two areas of the storage device.