Patent ID: 7839758
Filing Date: 2010-11-23
Classification: H04B

Abstract:
1. A system, comprising an echo canceller, having at least one portion operating in an analog domain and at least one portion operating in a digital domain, to generate a first digital echo estimate signal with a least mean square (LMS) unit in response to receiving a digital error signal based upon an incoming signal; the echo canceller comprises, an interpolation filter unit to receive the first digital echo estimate signal and to generate a second digital echo estimate signal having a suppressed echo estimate beyond a first clocking frequency, the interpolation filter unit to operate in the digital domain at the first clocking frequency without oversampling; and a digital-to-analog converter (DAC), coupled to the interpolation unit, to receive the second digital echo estimate signal with the suppressed echo estimate beyond the first clocking frequency and generate an analog echo estimate signal without oversampling in order to reduce an echo signal from the incoming signal using the analog echo estimate signal.