Patent ID: 8963313
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A method of integrating a semiconductor component with a layered substrate comprising: forming a cavity in a layered substrate, the layered substrate includes a first dielectric layer disposed over a second grounding layer of the layered substrate such that the second grounding layer defines the cavity bottom; disposing at least one electrical trace on a top surface of the first dielectric layer; disposing a semiconductor component in the cavity such that a top surface of at least one electrical contact on the semiconductor component is substantially coplanar with a top surface of the at least one electrical trace on the first dielectric layer of the layered substrate; forming a gap between the semiconductor component and the at least one cavity formed in the first dielectric layer of the layered substrate; disposing a gap fill material in said gap such that a top surface of the gap fill material is substantially coplanar with a top surface of the semiconductor component and a top surface of the first dielectric layer; disposing an electrical interconnect across the top surface of the dielectric gap fill material and between the at least one electrical contact on the semiconductor component and the at least one electrical trace on the first dielectric layer; and wherein dielectric properties of the dielectric gap fill material substantially match the dielectric properties of the first dielectric layer, the dielectric gap fill material thereby providing a continuous, low loss, micro-strip interconnection between the semiconductor component and the first dielectric layer, the interconnection providing no discontinuity in dielectric properties across the gap between the semiconductor component and the first dielectric layer.