Patent ID: 6791162
Filing Date: 2004-09-14
Classification: B81B,H01L,Y10S

Abstract:
A chip, comprising:a row of a plurality of unit cells, wherein said row extends in a first direction, wherein each said unit cell in said row is of the same configuration and comprises: first and second sides that are spaced along said first direction, wherein said first and second sides define a pair of opposite sides of said unit cell; a plurality of first electrical traces that extend between said first and second sides; and a plurality of second electrical traces that extend from any of said first and second sides and terminate at an interior locale prior to reaching the other of said first and second sides, wherein each said first electrical trace at said first side and one of either another said first electrical trace at said second side or one said second electrical trace at said second side are disposed along a common reference line that is parallel with said first direction, wherein each said second electrical trace at said first side and one of said first electrical traces at said second side are disposed along a common reference line that is parallel with said first direction, wherein each said second electrical trace at said second side and one of said first electrical traces at said first side are disposed along a common reference line that is parallel with said first direction, and wherein: said plurality of unit cells comprises first and second units cells that are disposed on first and second ends of said row, wherein said first side of said first unit cell is on a first perimeter region of said chip, and wherein said second side of said second unit cell is on a second perimeter region of said chip; each adjacent pair of said unit cells in said row are disposed in abutting relation such that said first side of one said unit cell abuts said second side of another said unit cell and are electrically interconnected; each said first electrical trace of each said unit cell is electrically interconnected with either one said first electrical trace or one said second electrical trace of an adjacent said unit cell, and wherein each said second electrical trace of each said unit cell that does not terminate at either of said first side of said first unit cell or said second side of said second unit cell is electrically interconnected with a first electrical trace of an adjacent said unit cell; and each said second electrical trace is accessible from either said first side of said first unit cell or said second side of said second unit cell.