Patent ID: 7861022
Filing Date: 2010-12-28
Classification: G06F

Abstract:
1. An apparatus for livelock resolution in a data processing system, wherein the processing system comprises a bus, a primary processing element, and a plurality of support processing elements, the apparatus comprising: detection logic that detects a livelock condition responsive to a timeout condition in at least one of a plurality of bus units, wherein the detection logic signals an attention to a control processor responsive to presence of a livelock condition, wherein responsive to the attention, the control processor sets status information to perform one or more actions to attempt to correct a potential livelock condition, and wherein the status information comprises a livelock resolution signal; and activation logic that engages quiescing of at least a subset of the primary processing element and the plurality of support processing elements responsive to a livelock resolution signal from the control processor, a quiesce signal from the control processor, or a throttle signal from the control processor.