Patent ID: 6188630
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first pair of data lines and a second pair of data lines;a plurality of first and second column-selection signal lines for transferring a plurality of column-selection signals;a block selection signal line for transferring a block selection signal;a first memory block includinga plurality of memory cells,a plurality of word lines connected to the memory cells,a plurality of a pairs of bit lines, each of which is connected to the memory, cells,a plurality of column switch circuits each of which is connected to one of the first column-selection signal lines, one of the pairs of the bit lines and the first pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the first pair of data lines in response to the column selection signal, anda control circuit connected to said block selection signal line, the control circuit enabling said first memory block in response to the block selection signal;a second memory block includinga plurality of memory cells,a plurality of word lines connected to the memory cells,a plurality of pairs of bit lines, each of which is connected to the memory, cells,a plurality of column switch circuits each of which is connected to one of the first column-selection signal lines, one of the pairs of the bit lines and the second pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the second pair of data lines in response to the column selection signal, anda control circuit connected to said block selection signal line, the control circuit enabling said second memory block in response to the block selection signal;a third memory block includinga plurality of memory cells,a plurality of word lines connected to the memory cells,a plurality of pairs of bit lines, each of which is connected to the memory, cells,a plurality of column switch circuits each of which is connected to one of the second column-selection signal lines, one of the pairs of the bit lines and the first pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the first pair of data lines in response to the column selection signal, anda control circuit connected to said block selection signal line, the control circuit enable said third memory block in response to the block selection signal; anda fourth memory block includinga plurality of memory cells,a plurality of word lines connected to the memory cells,a plurality of pairs of bit lines, each of which is connected to the memory, cells,a plurality of column switch circuits each of which is connected to one of the second column-selection signal lines, one of the pairs of bit lines and the second pair of data lines, the column switch circuit transferring data on the pairs of it lines to the second pair of data lines in response to the column selection signal, anda control circuit connected to said block selection signal line, the control circuit enabling said fourth memory block in response to the block selection signal.