Patent ID: 6360298
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A load/store instruction control circuit of a microprocessor which is able to access a cache memory storing a portion of data stored to an external memory or read out from the external memory, comprising:load/store same line misses detecting means for detecting that a load instruction for a no-write allocate area storing data directly to a lower layer memory in a cache hierarchy initiates a cache-miss, and a subsequent store instruction initiates the cache-miss for the same cache line as the preceding load instruction, when a non-blocking cache that a pipeline process of a microprocessor does not stop even if the cache-miss of load/store instructions occurs is implemented; temporary storing means for temporarily storing a store-data by said subsequent store instruction when the same cache line miss by said load/store same line miss detecting means is detected, and load/store control means for storing to a corresponding cache line the store-data stored to said temporary storing means during a refill process for the cache line by the preceding load instruction or after the refill process.