Patent ID: 6452835
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A semiconductor structure for long-term learning comprising:a pâˆ’ type region disposed within a semiconductor substrate; an nâˆ’ type well region disposed within said pâˆ’ type region; a first p+ type region disposed within said nâˆ’ type well region; a second p+ type region disposed within said nâˆ’ type well region; a floating gate disposed over a channel region and separated from said channel region by a first insulating layer, said channel region disposed in said first nâˆ’ type well region between said first p+ type region and said second p+type region; a tunneling junction region disposed adjacent to a portion of said floating gate, said tunneling junction region including a first conductive region separated from said floating gate by an insulating material; a second insulating layer disposed over said floating gate; and a second conductive region disposed over said second insulating layer and capacitively coupled to said floating gate; means for selectively causing electrons to inject from said channel region through said first insulating layer onto said floating gate; and means for selectively causing electrons to tunnel from said floating gate through said tunneling junction region.