Patent ID: 7812757
Filing Date: 2010-10-12
Classification: H03M

Abstract:
1. A hybrid analog-to-digital converter (ADC) comprising: a first charge-sharing line; a plurality of first switches; a first array of capacitors having weighted capacitance values, wherein first array capacitors in the first array connect to the first charge-sharing line and to the plurality of first switches; a first analog input having an analog input voltage, a plurality of first digital values; wherein the plurality of first switches connect the first analog input to the first array of capacitors during a sampling phase; wherein the plurality of first switches connect the first digital values to the first array of capacitors during a conversion phase after the sampling phase; a sub-voltage capacitor array comprising: a comparator that receives the first compare voltage and compares the first compare voltage to a second comparator input to generate a compare output; and control logic for adjusting the first digital value to the plurality of switches during a first sequence of compare operations, and for examining the compare output from the comparator stage during the first sequence of compare operations to determine a first digital value that approximately represents the analog input voltage; the control logic further for adjusting the first digital sub-value and the second digital sub-value during a final sequence of compare operations after the first sequence of compare operations is completed, and for examining the compare output from the comparator stage during the final sequence of compare operations to determine a final digital value that represents the analog input voltage more precisely than the first digital value; wherein the final digital value comprises the first digital value as most-significant-bits (MSBs) and the first digital sub-value and the second digital sub-value as least-significant-bits (LSBs); whereby the final digital value is generated with MSBs generated from the first array of capacitors having weighted capacitance values that sample the first analog input, and with LSBs generated from the first and second sub-sampling capacitors and coupled through the first coupling capacitor that do not sample the first analog input.