Patent ID: 6961264
Filing Date: 2005-11-01
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a semiconductor substrate comprising a first region extending along an edge and a second region surrounded by the first region; a plurality of memory cell arrays provided in the second region, and comprising a plurality of cells having an MTJ element; a plurality of gate transistors provided in the first region, and having a current path having a first terminal connected with a bit line, which is a signal read path from the cells, and a second terminal opposite to the first terminal; a plurality of data buses connected with a same number of the second terminals; a connection control circuit provided in the first region, and connected with an end of the data buses, and connecting selected two of the data buses to first and second output terminals, respectively; and an amplifier circuit provided in the first region, and amplifying a potential difference in accordance with signals outputted from the first and second output terminals.