Patent ID: 7742325
Filing Date: 2010-06-22
Classification: G11C,H01L

Abstract:
1. A memory cell, comprising: first and second access transistors, wherein the first access transistor is connected to a word line and connected between a first bit line and a first data node, and wherein the second access transistor is connected to the word line and connected between a second bit line and a second data node; first and second pull-up transistors, wherein the first pull-up transistor is connected to a first power supply point and to the first data node, and wherein the second pull-up transistor is connected to the first power supply point and the second data node; first and second pull-down transistors, wherein the first pull-down transistor is connected to a second power supply point and to the first data node, and wherein the second pull-down transistor is connected to the second power supply point and to the second data node; wherein the memory cell can perform a read operation, a write operation, or reside in an idle state; wherein during a read operation the first and second pull-up transistors, the first and second pull-down transistors, and the first and second access transistors receive a forward bias voltage; and wherein during a write operation the first and second pull-up transistors receive a zero or reverse bias voltage, wherein receiving a zero or reverse bias voltage at the first and second pull-up transistors comprises zero or reverse biasing a well region of the first and second pull-up transistors to a voltage at the first power supply point and wherein the first and second pull-down transistors and the first and second access transistors receive a forward bias voltage.