Patent ID: 6628133
Filing Date: 2003-09-30
Classification: G01R,H01L,H05K,Y10T

Abstract:
A method of testing integrated circuitry comprising:providing a substrate comprising integrated circuitry to be tested, the circuitry substrate having a plurality of exposed conductive bumps in electrical connection with the integrated circuitry; engaging at least one of the conductive bumps with an opening of a conductive receptacle at least partially formed in a surface of a test substrate; after the engaging, heating at least a portion of the receptacle to a temperature greater than 125Â° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductive bump effective to deform the engaged bump to be received more fully within the receptacle than initially so received by the engaging; testing the bumped circuit through the engaged bump deformed within the receptacle; and after the testing, removing the engaged bump from the receptacle.