Patent ID: 8750338
Filing Date: 2014-06-10
Classification: H04J,H04L

Abstract:
1. A high speed bit stream data conversion circuit comprising: a plurality of data conversion circuits configured to receive a first plurality of bit streams at a first bit rate and to produce at least one second bit stream at a second bit rate; a plurality of symmetrical data circuit pathways configured to transport the first plurality of bit streams to the plurality of data conversion circuits, wherein transmission time for each of the first plurality of bit streams is substantially equal; and a clock distribution circuit that receives a data clock signal configured to substantially symmetrically distribute the data clock signal to the plurality of data conversion circuits along a plurality of substantially symmetrical clock circuit pathways, wherein the plurality of substantially symmetrical clock circuit pathways is oriented along a bisection of the plurality of symmetrical data circuit pathways that extend outward from the bisection such that clock transmission time is substantially equal for each of the substantially symmetrical branch pairs, each of the substantially symmetrical branch pairs correspondingly couple to each of the plurality of data conversion circuits.