Patent ID: 6188608
Filing Date: 2001-02-13
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:first and second word lines;first and second bit lines, each said bit line intersecting with both of the first and second word lines;first and second memory cell blocks, each of the first and second memory cell blocks including at least one memory cell connected to the first word line;third and fourth memory cell blocks, each of the third and fourth memory cell blocks including at least one memory cell connected to the second word line;first connection means for connecting the first bit line to the first memory cell block responsive to a first control signal;second connection means for connecting the second bit line to the second memory cell block responsive to a second control signal;third connection means for connecting the first bit line to the third memory cell block responsive to a third control signal;fourth connection means for connecting the second bit line to the fourth memory cell block responsive to a fourth control signal; andan amplifier for inputting or outputting data through the first and second bit lines,wherein each said memory cell block includes at least one dummy cell.