Patent ID: 7522426
Filing Date: 2009-04-21
Classification: H05K

Abstract:
1. A storage controller comprising a plurality of logical boards and a backplane for connecting signal lines between the logical boards and supplying power to the logical boards, wherein the backplane comprises a first signal connector for connecting signals of the logical boards connected to an upper level of the backplane, a second signal connector for connecting signals of the logical boards connected to a lower level of the backplane, a first power source connector for supplying power to the logical boards connected to the upper level of the backplane, and a second power source connector for supplying power to the logical boards connected to the lower level of the backplane, wherein the first power source connector is formed at one end of the backplane and the second power source connector is formed at the other end of the backplane, wherein each of the logical boards has a third power source connector disposed at one end thereof and a fourth power source connector disposed at the other end thereof, wherein one of the logical boards is disposed at the upper level of the backplane and is supplied with power by way of a connection between the third power source connector of said one of the logical boards and the first power source connector, wherein another one of the logical boards is disposed at the lower level of the backplane and is supplied with power by way of a connection between the fourth power source connector of said another one of the logical boards and the second power source connector, wherein the logical board further comprises a plurality of ports to be connected to host interfaces, the logical board receives from the backplane a position signal indicating whether the logical board is connected to the upper level of the backplane or the lower level of the backplane, and logical port numbers of the ports are changed in such a manner that the alignment of the logical port numbers of the ports of the logical boards connected to the upper level of the backplane and the alignment of the logical port numbers of the ports of the logical boards connected to the lower level of the backplane match.