Patent ID: 7475170
Filing Date: 2009-01-06
Classification: G06F

Abstract:
1. A data transfer device adapted to transfer data between a memory bus, being connected in such a manner as to be capable of communicating request, write data and read data as a packet respectively in communication with a memory, equipped with a request signal line, a write data signal line and a read data signal line and an input/output bus equipped with a transmission signal line and a reception signal line through which the transmission data and the reception data are transmitted to or received from an input/output apparatus respectively as a packet including transmission data and transmission address of the transmission data and a packet including reception data and reception address of the reception data, comprising: an input/output reception buffer capable of storing the reception data received from the input/output apparatus through the reception signal line; an input/output transmission buffer capable of storing the transmission data transmitted to the input/output apparatus through the transmission signal line; a write data buffer capable of storing the write data to be transmitted to the memory through the write data signal line; a read data buffer capable of storing the read data received from the memory through the read data signal line; a control information table having a plurality of entries formed corresponding to the access to the memory; a write data buffer storing process section that stores the reception data stored in the input/output reception buffer in the write data buffer; a write data transmission section that transmits the reception data stored in the write data buffer to the memory as the write data through the write data signal line; a read data buffer storing process section that stores the read data received from the memory in the read data buffer; an input/output transmission buffer storing process section that reads out the read data stored in the read data buffer and stores the data as the transmission data along with the transmission address of the transmission data into the input/output transmission buffer; and a control section that controls the access to the memory made by the write data transmission section and the read data buffer storing section based on the control information table.