Patent ID: 8483003
Filing Date: 2013-07-09
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of word lines; a plurality of complementary bit lines; a plurality of static memory cells disposed correspondingly to the word lines and the complementary bit lines; an address decoder that decodes address signals to produce complementary bit line select signals; a write circuit that feeds a write signal to each memory cell from a complementary bit line selected by a complementary bit line select signal; a plurality of power supply lines that feed a power supply voltage to each group of memory cells which use the complementary bit lines in common; a plurality of power switches, each being disposed for each power supply line corresponding to a complementary bit line selected by a complementary bit line select signal for use in common at least, and being so arranged as to be put in an ON state when an unselected level is indicated by the complementary bit line select signal concerned or in an OFF state when a selected level is indicated thereby; and a plurality of short-circuit switches, each being disposed for providing coupling between an output node of each power switch and an output node of at least one of the other power switches, and being so arranged as to be put in an OFF state in response to a write operation instruction from the write circuit or in an ON state in response to a write non-operation instruction therefrom, where the output nodes of the power switches to be coupled mutually are arranged to correspond to complementary bit lines selected by different complementary bit line select signals at least.