Patent ID: 6639856
Filing Date: 2003-10-28
Classification: G11C

Abstract:
A memory chip, comprising:a plurality of memory cells; an address circuit connected to address lines for supplying an address to said memory cells via selection lines for activating respective said memory cells; said address circuit, upon receiving an address on the address lines, activating a prescribed memory cell via said selection lines, to enable a data item to be read from or to be written to said memory cell; standby memory cells connected to said address circuit via further selection lines; a first address memory connected to said address circuit for storing addresses for faulty memory cells; said address circuit comparing a prescribed address with the addresses in said first address memory and, if the prescribed address is held in said first address memory, activating a respective said standby memory cell instead of said faulty memory cell; a test circuit connected to said address circuit, and outputting a signal to the address circuit in a test mode; and if the signal is present and an address for a faulty memory cell is applied, said address circuit activating said faulty memory cell instead of the respective said standby memory cell.