Patent ID: 8566763
Filing Date: 2013-10-22
Classification: G06F,H03K

Abstract:
1. A logic circuit design method in which a computer device performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit, the logic circuit design method comprising the step of: performing, by the computer device, optimization processing for decreasing the number of gate stages in a critical path in the series path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal, wherein in the case where a polarity matching inverter for positive logic can be disposed in a final stage of a combinational circuit coupled to a positive-logic input terminal of the first sequential circuit, the computer device deletes the polarity matching inverter and replaces the first sequential circuit with the fourth sequential circuit in the optimization processing in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal.