Patent ID: 6304509
Filing Date: 2001-10-16
Classification: G11C

Abstract:
A semiconductor storage unit comprising:a plurality of bank blocks including a plurality of banks that are adjacent to each other and have a memory cell array including a plurality of memory cells placed in a matrix form, a plurality of global I/O lines provided in parallel to an arranging direction of said banks and in common therewith for conveying data read out from any of the memory cells in the memory cell array configuring said plurality of banks, or data to be written in any individual one of the plurality of memory cells, a plurality of I/O amplifiers connected to individual ones of the plurality of global I/O lines for amplifying data conveyed by corresponding ones of the plurality of global I/O lines, or data to be conveyed from an individual global I/O line to a corresponding global I/O line, and a plurality of column decoders provided in common with said plurality of banks for respectively outputting a plurality of column selection switches for setting selected ones of a plurality of bit lines corresponding to the memory cell array configuring any one of the plurality of banks at the selected state; anda plurality of bank selective circuits, provided in common with banks configuring the corresponding bank block for each of said bank blocks which create a column decoder activation signal for activating the corresponding column decoder on the basis of at least one multi-bit bank address signal for selecting any individual one of all banks configuring said bank blocks and an I/O amplifier activation signal for activating at least a corresponding one of the plurality of I/O amplifiers.