Patent ID: 8549447
Filing Date: 2013-10-01
Classification: G06F,H01L,H03K

Abstract:
1. A method for enabling a computer system to create an integrated circuit (IC) design with multiple I/O regions comprising at least one outer I/O region and one inner I/O region, the method comprising: providing a plurality of interconnect macros describing electronic circuits, the interconnect macros on a tangible computer readable media readable by the computer system, the interconnect macros providing at least one lateral power or ground path for laterally connecting power or ground signals in an I/O region, said interconnect macros also providing at least one interconnect signal path for connecting signals between or through I/O regions; providing a set of I/O macros describing electronic circuits, the I/O macros and readable by the computer system; so that the computer system is able to place one or more of the set I/O macros into at least one outer I/O region and one inner I/O region; so that the computer system is able to place at least one interconnect macro in at least one inner I/O region: and wherein a macro is a descriptor of a cell of an integrated circuit and wherein the set of I/O macros includes filler macros with lateral connections between abutting I/O macros; and the set of interconnect macros comprising one or more interconnect macros with at least one flow-through filler portion having a width roughly equal to the width of a filler macro and containing lateral and transverse connections and at least one inter-region portion that lies between outer I/O region macros and inner I/O region macros and that routes signals from the edge of an inner I/O region around to transverse connections in a flow-through filler portion.