Patent ID: 8151275
Filing Date: 2012-04-03
Classification: G06F

Abstract:
1. An information processing apparatus including: a physical processor; a memory; a control OS execution unit that implements a control OS, the control OS performing a process of associating a plurality of logical processors with the physical processor through time-sharing; and one or more guest OS execution units that each implement a respective guest OS, the respective guest OS assigned a designated logical processor among the plurality of logical processors, wherein each of the guest OS execution units are configured to execute data processing such that a memory-mapped I/O (MMIO) register of the physical processor is used in an active state where the physical processor is allocated to the designated logical processor corresponding to the respective guest OS of each of the guest OS execution units, wherein the control OS execution unit is configured to store in the memory copy information of the MMIO register corresponding to the designated logical processor corresponding to the respective guest OS of each of the guest OS execution units, both in the active state where the physical processor is allocated to said logical processor and in an inactive state where no physical processor is allocated to said logical processor, wherein, both in the active state and inactive state of the designated logical processor corresponding to the respective guest OS, the guest OS execution unit reads data in the MMIO register by reading the data from the copy information stored in the memory without accessing the MMIO register via the control OS, and wherein the guest OS execution unit is configured to access the copy information of the MMIO register stored in memory via a guest OS programming interface (GOI) set by the control OS.