Patent ID: 6671197
Filing Date: 2003-12-30
Classification: G11C

Abstract:
A memory device comprising:an array of memory cells, when in use, each of which to store a charge representing a binary digit of data, a plurality of data lines connected to the array of memory cells, wherein each memory cell is connected to a pair of data lines, each data line to apply a voltage to a particular memory cell to enable the particular memory cell to store the charge, and each data line to receive the voltage applied by the particular memory cell to read the binary digit of data stored in the particular memory cell; a plurality of read/write lines connected to the array of memory cells to selectively connect the array of memory cells to the plurality of data lines to apply the voltage to the memory cells or receive the voltage from the memory cells; a plurality of control lines connected to the array of memory cells to control configuration of the memory cells, wherein the memory cells are arranged such that the plurality of control lines configure the memory cells to provide a capacitance to which the data lines can apply the voltage and to configure the memory cells to maintain the charge stored in each memory cell by virtue of a power supply; and a plurality of inverted read/write lines connected to the array of memory cells to selectively connect the array of memory cells to the plurality of data lines such that the pair of data lines are reversed.