Patent ID: 7696579
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A CMOS device having standard and low voltage threshold gates for both PMOS and NMOS transistors fabricated by the process comprising: forming a P-type well in a substrate defining a standard voltage threshold NMOS region; forming an N-type well in said substrate defining a standard voltage threshold PMOS region; forming a P-type well in said substrate defining a low voltage threshold NMOS region; forming an N-type well in said substrate defining a low voltage threshold PMOS region; implanting a P-type impurity into said substrate, wherein said P-type impurity into said standard voltage NMOS region; implanting an N-type impurity into said substrate, wherein said N-type impurity into said standard voltage PMOS region; forming a polysilicon gate stack over in the regions of said substrate defining said standard voltage NMOS region, said standard voltage PMOS region, said low voltage NMOS region, and said low voltage PMOS region; doping said polysilicon gate stacks over said standard voltage NMOS region and said low voltage NMOS region with an N-type impurity; doping said polysilicon gate stacks over said standard voltage PMOS region and said low voltage PMOS region with a P-type impurity; and forming lightly doped drain regions about each of said gate stacks that are self-aligned with the gate stacks.