Patent ID: 6012141
Filing Date: 2000-01-04
Classification: G06F

Abstract:
Apparatus for detecting and executing program instruction traps in a superscalar processor operating on a plurality of pipelined instructions, said apparatus comprising:a fetch means for fetching consecutive instructions from an instruction cache and a main memory,an instruction FIFO memory for storing fetched instructions from said fetch means, andan instruction decode means for removing instructions from said FIFO memory in accordance with the relative ages of instructions stored in said FIFO memory, said decode means examining said instructions removed from said FIFO memory for trapping conditions, and flushing from said FIFO memory all younger instructions in response to identification of a trap in an instruction, anda plurality of state registers coupled to the decode means for indicating the operating state of the processor and wherein certain instructions in a sequence of instructions modify said state registers,said decode means examining said instructions for modifying said state registers and performing a specified trap action by blocking the issuance of younger instructions until a state register modifying instruction has been executed, the state register being locked and inaccessible until updated by execution of the instruction.