Patent ID: 7247903
Filing Date: 2007-07-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a memory cell transistor having first and second regions selectively formed in said semiconductor substrate; a peripheral transistor having a third region selectively formed in said semiconductor substrate; first, second and third silicide layers formed in direct contact with said first, second and third regions, respectively; a first insulating layer covering said semiconductor substrate and said first, second and third suicide layers; a bit line formed on said first insulating layer; a first conductive layer made of a metal and embedded into said first insulating layer to form an electrical path between said bit line and said first silicide layer; a second insulating layer covering said bit line and said first insulating layer; a capacitor formed on said second insulating layer; said capacitor having a lower electrode made of a metal, an upper electrode made of a metal and a dielectric layer sandwiched between said lower and upper electrodes; a second conductive layer made of a metal and embedded into said first and second insulating layers to form an electrical path between said lower electrode of said capacitor and said second silicide layer; a third insulating layer covering said capacitor and said second insulating layer; a third conductive layer made of a metal and formed in said first, second and third insulating layers in contact with said third suicide layer; and a wiring layer formed on said third insulating layer in contact with said third conductive layer, wherein said third conductive layer is elongated straightly without a bend between said third suicide layer and said wiring layer, wherein said first insulating layer comprises first and second insulating films, said first conductive layer being embedded into said first insulating film in contact with said first suicide layer, said bit line being in electrical contact with said first conductive layer through a hole formed in said second insulating film, said second conductive layer including first and second conductive plugs said first conductive plug being embedded into said first insulating film, said second conductive plug being embedded into said second insulating film and said second insulating layer, and wherein said third conductive layer comprises third, fourth and fifth conductive plugs, said third conductive plug being embedded into said first insulating film, said fourth conductive plug being embedded into said second insulating film and said second insulating layer, and said fifth conductive plug embedded into said third insulating layer.