Patent ID: 8766963
Filing Date: 2014-07-01
Classification: G09G

Abstract:
1. An OLED display device comprising: a plurality of pixels each having a light emitting device and a pixel circuit for driving the light emitting device, wherein the pixel circuit includes; a driving transistor for driving the light emitting device, a first switching transistor for supplying a data voltage from a data line to a first node in response to a first scan signal from a first scan line, a second switching transistor for connecting the driving transistor to a power line in a diode structure in response to the first scan signal from the first scan line, a third switching transistor for supplying a reference voltage from a reference voltage supply line to the first node in response to a light emission control signal from a light emission control line, a fourth switching transistor for connecting the driving transistor to the light emitting device in response to the light emission control signal from the light emission control line, a fifth switching transistor for connecting the fourth switching transistor to the reference voltage supply line in response to a second scan signal from a second scan line, a storage capacitor connected between the first node and a second node connected to a gate electrode of the driving transistor for having a differential voltage of the first and second nodes charged thereto and maintaining thereby, and a boost capacitor connected to the first scan line and the second node, for boosting a voltage at the second node in response to a variation amount of the first scan signal, wherein: a scan period in which the first and second scan signals are supplied includes an initializing period and a sampling period, the second node is initialized toward the reference voltage via the second, fourth, fifth switching transistors in the initializing period, and the first node has the data voltage and the reference voltage supplied thereto through the first and third switching transistors, the second node samples a differential voltage of the driving voltage from the power line and a threshold voltage of the driving transistor via the driving transistor and the second switching transistor in the sampling period, and in a boosting period in succession to the scan period, the second switching transistor is turned off, and the second node is boosted according to a variation amount of the first scan signal and a combined ratio {Cb/(Cb+Cst)} of the storage capacitor Cst and the boost capacitor Cb.