Patent ID: 7005335
Filing Date: 2006-02-28
Classification: H01L

Abstract:
1. A method for fabricating a nanoscopic transistor, comprising the steps of: a) providing a semiconductor substrate; b) forming a thin oxide layer on the semiconductor substrate; c) applying a first layer of resist; d) patterning the first layer of resist using imprint lithography to form a first pattern aligned along a first direction; e) applying a first ion-masking material over the first pattern, and selectively lifting off the first ion-masking material to leave a first ion mask defined by the first pattern, the first ion mask being suitable to form a gate; f) forming first doped regions an the semiconductor substrate by implanting a suitable first dopant selectively in accordance with the first ion mask; g) applying a second layer of resist and patterning the second layer of resist using imprint lithography to form a second pattern aligned along a second direction; h) applying a second ion-masking material over the second pattern, and selectively lifting off the second ion-masking material to leave a second ion mask defined by the second pattern; and i) forming second doped regions in the semiconductor substrate by implanting a suitable second dopant selectively in accordance with the second ion mask.