Patent ID: 6637013
Filing Date: 2003-10-21
Classification: G06F

Abstract:
A method for eliminating design rule check (DRC) errors detected by a design verification tool in a set of design data, the method comprising:(a) creating a first rules file for a design verification tool, the first rules file being designed to attach a specific property type of specific error; (b) processing a set of design data with the design verification tool to produce first verification results using the first rules file, the first verification results used as an input layer, the design data including geometric data describing an integrated circuit design to be verified; (c) determining if the input layer contains a DRC error; (d) if a DRC error is detected in the input layer, creating supplemental geometries responsive to the attached specific property to resolve the detected DRC error, the supplemental geometries used as a supplemental layer; (e) creating a second rules file for the design verification tool for the supplemental layer; (f) processing the input layer and the supplemental layer using the second rules file to produce second verification results to form an output layer; and (g) deleting all geometries from the input layer and changing all geometries in the output layer back to the input layer.