Patent ID: 8006210
Filing Date: 2011-08-23
Classification: G06F

Abstract:
1. A logic design method, comprising: transforming, by a processor of a computer system, a gate G into a logic block, said gate G including an input stage and an output stage, wherein inputs of the input stage are input signals to the gate G from respective input locations from which the input signals respectively originate, and wherein outputs of the output stage are output signals from the gate G to respective output locations to which the output signals are respectively sent, wherein the input signals are divided into M input groups of input signals and the respective input locations, wherein the output signal are divided into N output groups of output signals and the respective output locations, and wherein M and N are each a positive integer such that M is at least 2; wherein said transforming comprises replacing the gate G by (i) M input gates in the input stage corresponding to the M input groups and (ii) N output gates in the output stage corresponding to the N output groups, wherein each input gate of the M input gates is placed in a vicinity of the input locations of the corresponding input group and is configured to receive input signals from the respective input locations of the corresponding input group, and wherein each output gate of the N output gates is placed in a vicinity of the output locations of the corresponding output group and is configured to send output signals to the respective output locations of the corresponding output group.