Patent ID: 6351780
Filing Date: 2002-02-26
Classification: G06F

Abstract:
In a network controller for receiving data frames having an internal memory buffer for holding the data frames received from a network for processing by a host processor, and a direct memory access (DMA) circuit transferring received data frames into a system memory, a buffer manager comprising:a held frame monitor responsive to said memory buffer for monitoring the data frames loaded into said memory buffer and unloaded from said memory buffer; decision logic responsive to said held frame monitor for automatically engaging said DMA circuit to unload the data frames from said memory buffer when overflow of said memory buffer is anticipated; a loader responsive to received data frames for generating frame storage addresses to write the received data frames into said memory buffer; an unloader responsive to said buffer for generating addresses to allow DMA unloading of the data frames from said memory buffer; and a host interface responsive to said host processor for generating addresses to allow said host processor to read data frames from said memory buffer.