Patent ID: 8760942
Filing Date: 2014-06-24
Classification: G11C

Abstract:
1. A resistive memory device comprising: a memory cell array including a plurality of resistive memory cells arranged in accordance with a plurality of local bit lines, and each being respectively connected to one of a plurality of global bit lines and a plurality of word lines; and a write driver that selectively supplies current to the plurality of resistive memory cells corresponding to the plurality of local bit lines, via the plurality of global bit lines, wherein the memory cell array comprises: a plurality of first switches that connect the plurality of word lines to a ground line in response to a first switch control signal, and a plurality of second switches that connect the plurality of global bit lines to the plurality of local bit lines corresponding to the plurality of global bit lines in response to a second switch control signal, wherein opposing first and second ends of the plurality of resistive memory cells connected between the write driver and the ground line are disconnected from the write driver and the ground line in response to the first and second switch control signals.