Patent ID: 6559048
Filing Date: 2003-05-06
Classification: H01L

Abstract:
A process for forming vias in one or more layers of dielectric material, including at least one layer of low k carbon-containing silicon oxide dielectric material comprising the reaction product of methyl silane and hydrogen peroxide, on an integrated circuit structure which suppresses subsequent via poisoning which comprises:a) first forming a via resist mask with one or more openings over the upper surface of said layer of low k dielectric material; b) then heat treating said resist mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on said one or more openings in said heat treated resist mask; c) then etching said layer of low k dielectric material through said one or more openings in said heat treated resist mask to form one or more vias in said layer of low k dielectric material with a smooth inwardly sloped sidewall; whereby the resulting erosion of such a resist mask, during said subsequent etch step to form said one or more vias in said layer of low k dielectric material through said heat treated resist mask, imparts a tapered or sloped sidewall geometry to said one or more vias formed in said layer of low k dielectric material to thereby suppress via poisoning during subsequent filling of said one or more vias.