Patent ID: 8318605
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit on a semiconductor wafer, comprising: forming a thin film device structure on the wafer including semiconductor elements, said semiconductor elements comprising sources, drains and gates of transistors; covering said thin film device structure with a doped glass layer comprising silicon, oxygen and at least one of boron or phosphorus; forming openings through said doped glass layer to expose, at bottoms of respective openings, a surface of respective ones of said semiconductor elements comprising the sources, drains and gates of the transistors; performing an etch step by generating a plasma from a process gas comprising fluorine species and hydrogen species and exposing said wafer to by-products of said plasma; converting boron and/or phosphorus materials separated from silicon near the surface of said doped glass layer to gas phase compounds.