Patent ID: 7941682
Filing Date: 2011-05-10
Classification: G06F,Y02D

Abstract:
1. A system on chip, comprising: a hardware module including at least one of a microcontroller, a microprocessor, a DSP core, a memory, a timing source, a peripheral, and an external interface to have a real time counter module isolated from the rest of the hardware module using at least one of a plurality of voltage level shifting cells and a plurality of voltage island cells; a software module associated with the real time counter module to generate at least one control signal to at least one device external to the system on chip during a sleep mode of the system on chip to communicate with the at least one device, wherein the sleep mode places any unused part of the system on chip in a non-operational mode to reduce the power consumption of the system on chip; a voltage regulator control counter of the real time counter module generates a wake-up signal to a voltage regulator of the system on chip to supply the rest of the hardware module with power based on at least one of a preprogrammed schedule and a response signal from an external device; and a device control counter of the real time counter module to generate the at least one control signal to access the at least one device to obtain the response signal, wherein the response signal includes at least an alarm signal generated by the at least one device.