Patent ID: 8202802
Filing Date: 2012-06-19
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising the steps of: forming a film to be processed on a substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; etching the film to be processed by using the third pattern formed on the hard mask layer to form a first wiring pattern and a second wiring pattern; forming an interlayer insulating film on the film to be processed; and forming a first and a second contact holes bringing the first wiring pattern and the second wiring pattern respectively into connection to the interlayer film.