Patent ID: 7939394
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A method of fabricating trenches within an integrated circuit device, comprising: forming a plurality of trenches in a substrate to a first depth, wherein the plurality of trenches includes first isolation trenches having a width less than some nominal value and second isolation trenches having a width greater than the nominal value; forming a first dielectric layer overlying the substrate to fill the first isolation trenches and to leave open the second isolation trenches; removing a portion of the first dielectric layer to expose portions of the underlying substrate at bottoms of the second isolation trenches while leaving the first isolation trenches filled; removing exposed portions of the underlying substrate to extend the second isolation trenches to a second depth; and forming a second dielectric layer overlying the substrate to fill the second isolation trenches; wherein the first dielectric layer and the second dielectric layer comprise the same dielectric material.