Patent ID: 6893900
Filing Date: 2005-05-17
Classification: H01L

Abstract:
1. A method of making an integrated circuit chip package, comprising the steps of: a) forming a leadframe to include: b) chemically etching the leadframe, a reentrant portion being disposed within at least portions of each of the peripheral die pad and tab side surfaces as a result of the etching of the leadframe; c) placing an integrated circuit die upon the first die pad surface of the die pad; d) electrically connecting the integrated circuit die to the first tab surface of each of the tabs; e) applying an encapsulant material to the frame, the integrated circuit die, the first die pad surface of the die pad, the first tab surface of each of the tabs, and into the reentrant portions of the peripheral die pad and tab side surfaces, without covering the second surface of each of the tabs; f) hardening the encapsulant material; and g) singulating the encapsulated frame so that the die pad and the tabs are severed from the frame, the second surface of each of the tabs being exposed within the package.