Patent ID: 6751194
Filing Date: 2004-06-15
Classification: H04J,H04L

Abstract:
A packet multiplexer, comprising:an input processing means for setting an output time limit value in each of a first input packet and a second input packet and for measuring the sizes of said first and second input packets and converting the measurements to values in terms of processing times corresponding to these sizes, said output time limit values of each of said first and second input packets reflecting corresponding delay time limit values for each of said first and second input packets; a first storing means for storing the first and second input packets, a second storing means for storing the order in which the first and second input packets are to be output according to the order in which they are received; an attribute storing means for storing the output time limit values and sizes of the first and second input packets that are calculated by the input processing means; and a read controlling means for comparing the output time limit values and sizes that are stored in the attribute storing means for the first and second input packets and then selecting one of the first and second input packets to output so that the first and second input packets will be output in decreasing order of size within the range in which a scheduled output time of each of said first and second input packets will meet the corresponding delay time limit values.