Patent ID: 6720133
Filing Date: 2004-04-13
Classification: H01L,Y10S

Abstract:
A method of manufacturing an integrated circuit comprising:providing a semiconductor substrate having a charge-trapping material over a core region and a gate insulator material over a periphery region the semiconductor substrate having bitlines provided therein; depositing a wordline-gate material, a hard mask material, and a first photoresist material over the semiconductor substrate; patterning the first photoresist material and hard mask material over the core region and covering the periphery region; removing the first photoresist material; forming a wordline from the wordline-gate material in the core region; depositing an anti-reflective coating material and a second photoresist material over the semiconductor substrate, the anti-reflective coating material of a disposable material; patterning the second photoresist material, the anti-reflective coating material, and the hard mask material over the periphery region and covering the core region; removing the second photoresist material and the anti-reflective coating material; and forming a gate from the wordline-gate material in the periphery region.