Patent ID: 8255768
Filing Date: 2012-08-28
Classification: G11B,H03M

Abstract:
1. A low-density parity-check (LDPC) system selectively operating on data sequences of either a first size or of a second size greater than the first size, the system comprising: a detector configured to operate on blocks of bits of the second size, wherein data sequences of the first size are interlaced to form data sequences of the second size; an LDPC decoder configured to operate on blocks of bits of the second size; and a de-interlacer coupled between the detector and the LDPC decoder, the de-interlacer configured to convert a data sequence output by the detector into multiple data sequences prior to decoding by the LDPC decoder, wherein the LDPC decoder is configured to separately decode the multiple data sequences output by the de-interlacer, and wherein the LDPC system is configured to process data sequences stored in blocks of bits of either the first size or the second size with a single LDPC decoder configured to operate on blocks of bits of the second size.