Patent ID: 6407947
Filing Date: 2002-06-18
Classification: G11C

Abstract:
A method of erasing a flash memory device, comprising the steps of:(a) performing a pre-program operation in a selected sector having at least some cells; (b) adjusting a value in an address counter; (c) performing an erasure operation by applying an erasure pulse voltage of all of the cells; (d) verifying an erasure state of the cells on a per address unit basis; (e) performing a post programming operation if cells corresponding to a last address are erased; (f) if some cells are not erased, erasing all the cells; (g) determining whether a predetermined maximum number of erasure operations has been exceeded; (h) if the predetermined maximum number of the erasure operations has not been exceeded, determining a number of erased cells; (i) if the determined number of erased cells is below a predetermined minimum number of erased cells, increasing a pulse width of the erasure pulse voltage and repeating at least steps (c) through (g); (j) if the determined number of erased cells is more than a predetermined maximum number of erased cells, reducing the pulse width of the erasure pulse voltage and repeating at least steps (c) through (g); (k) if the determined number of erased cells is between the predetermined maximum number of erased cells and the predetermined minimum number of erased cells, repeating at least steps (c) through (g) without changing the width of the erasure pulse voltage; and (l) if the predetermined maximum number of erasure operations has been exceeded, determining that the flash memory device is defective.