Patent ID: 6388938
Filing Date: 2002-05-14
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second cell arrays, each of which has the same number of memory cells; first through (2nâˆ’1)-th (n&gE;1) output selection control circuits; first through (2nâˆ’1)-th output transistor circuits which are provided so as to correspond to said first through (2nâˆ’1)-th output selection control circuits, and each of which receives the output of a corresponding one of said output transistor circuits; and first through (4nâˆ’2)-th output signal lines, each of said first and second cell arrays being divided into k (k&gE;2) first through k-th section parts, each of which has 2nâˆ’1 first through (2nâˆ’1)-th output parts and at least one auxiliary input/output part, said i-th (i=1, . . . , nâˆ’1) output selection control part receiving the output of the (2iâˆ’1)-th input/output part of each of the first through k-th section parts of said first cell array via the (2iâˆ’1)-th output signal line, and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of said first cell array via the 2i-th output signal line, said n-th output selection control part receiving the output of the (2nâˆ’1)-th input/output part of each of the first through k-th section parts of said first cell array via the (2nâˆ’1)-th output signal line, and receiving the output of the auxiliary input/output part of each of said section parts of said first cell array via the 2n-th output signal line, and said (n+i)-th (i=1, . . . , nâˆ’1) output control circuit receiving the output of the (2iâˆ’1)-th input/output part of each of the first through k-th section parts of said second cell array via the (2n+2iâˆ’1)-th output signal line, and receiving the output of the 2i-th input/output part of each of the first through k-th section parts of said second cell array via the (2n+2i)-th output signal line.