Patent ID: 6380053
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method for producing a semiconductor device having:(a) a gate insulating layer formed on a surface of a semi-conductive layer, and a gate electrode formed on the gate insulating layer, the semi-conductive layer formed on an insulation layer formed on a support, (b) a channel-forming region formed in the semi-conductive layer immediately below the gate electrode, (c) source/drain regions formed in the semi-conductive layer, so as to sandwich the channel-forming region, and (d) extension regions, each of which is formed in a region of the semi-conductive layer positioned between each source/drain region and the channel-forming region and extends from each source/drain region, said method comprising the steps of: (A) forming the gate insulating layer on the surface of the semi-conductive layer, and then, forming the gate electrode on the gate insulating layer, (B) introducing an impurity in regions of the semi-conductive layer where the source/drain regions are to be formed, and then, carrying out heat treatment for activation of the introduced impurity, to form the source/drain regions in the semi-conductive layer such that a junction depth of the source/drain regions is determined by a thickness of the semi-conductive layer, and (C) introducing an impurity into at least regions of the semi-conductive layer where the extension regions are to be formed, and then, carrying out heat treatment for activation of the introduced impurity, to form the extension regions in the semi-conductive layer.