Patent ID: 6243777
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A control circuit for a first device that may be connected to a shared bus, comprising:a first logic circuit having a first input terminal connected to a first chip enable line and a second input terminal connected to a second chip enable line;a first flip-flop having a data input terminal connected to a first output terminal of the first logic circuit;a second flip-flop having a data input terminal connected to a second output terminal of the first logic circuit;a third flip-flop having a data input terminal connected to an output terminal of the second flip-flop;a second logic circuit having a first input terminal connected to an output terminal of the first flip-flop; anda fourth flip-flop having a data input terminal connected to an output terminal of the second logic circuit, and an output terminal connected to a transmitting circuit of the first device.