Patent ID: 6226703
Filing Date: 2001-05-01
Classification: G06F

Abstract:
A method of operating a computer system including at least two I/O busses, a first one of said I/O busses having a short timeout period, a second one of said I/O busses having a second timeout period which is longer than the first bus timeout period, the method comprising the steps of:receiving a read transaction from an I/O device coupled to the second bus;performing a write transaction in response to the read transaction to a memory address specified in said read transaction, wherein said write transaction is a masked write operation which is performed with all mask bits disabled to prevent contents of the memory location from being changedwaiting a period of time before starting said read transaction on the second bus while permitting a transaction on said first bus to occur; andafter said period of time performing said read transaction on said second bus to said memory address.