Patent ID: 6197650
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method for forming capacitor and interconnect, said method comprising:providing a substrate;forming a first dielectric layer on said substrate;planarizing surface of said first dielectric layer;forming a first gap and a second gap in said first dielectric layer, wherein said first gap corresponds an contact and said second gap corresponds a metal capacitor;forming a metal glue layer on said first dielectric layer;forming a first metal layer on said metal glue layer, said first metal layer completely filling both said first gap and said second gap;removing excess said first metal layer and excess said metal glue layer by chemical mechanical polish;forming a second dielectric layer on said first dielectric layer;annealing said second dielectric layer;defining part of said second dielectric layer, said part of said second dielectric layer corresponds said second gap;removing excess said second dielectric layer;forming a second metal layer on said first dielectric layer, said second metal layer also covering said second dielectric layer;defining part of said second metal layer, said part of said metal layer corresponds to both said first gap and said part of said second dielectric layer;removing excess said second metal layer;forming a third dielectric layer on said first dielectric layer, said third dielectric layer covering said second metal layer;planarizing surface of said third dielectric layer;forming a plurality of vias, said vias connects to said part of said second metal layer;forming a third metal layer on said third dielectric layer;defining part of said third metal layer that corresponds said vias; andremoving excess third metal layer.