Patent ID: 6618301
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A modular memory structure having adaptable redundancy circuitry, comprising:a plurality of main memory blocks to store data; a plurality of redundancy memory blocks to replace a defective memory block in the plurality of main memory blocks; a plurality of fuse sets to be programmed to generate replacement signals for the replacement of the defective memory block's positions on the plurality of main memory blocks with the plurality of corresponding redundancy memory blocks, wherein the plurality of fuse sets further comprises: a plurality of fuse-added elements to be programmed according to a fuse set enable signal input externally to generate the enable signals to enable respective defect memory replacement ranges; and replacement generation circuitry to receive and decode the output of the plurality of fuse-added elements and the enable signals of the plurality of enable fuse elements to determine a replacement signal for the replacement range of defective memory block with the redundancy memory block.