Patent ID: 6269017
Filing Date: 2001-07-31
Classification: G11C,H01L

Abstract:
A Mask Read-Only Memory (ROM), comprising: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cells by a set of select lines,wherein a first select line of the set of select lines is coupled to a first gate of a first transistor and a second gate of a second transistor, the first transistor is coupled to the first bank of memory cells, and the second transistor is coupled to the second bank of memory cells, andwherein the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column, andwherein a first terminal of the first transistor is coupled to the first bank of memory cells via a first sub-bit line, a second terminal of the first transistor is coupled to a bit line, a first terminal of the second transistor is coupled to the second bank of memory cells via a second sub-bit line, and a second terminal of the second transistor is coupled to the bit line.