Patent ID: 8431452
Filing Date: 2013-04-30
Classification: G02F,H01L

Abstract:
1. A method for manufacturing a liquid crystal display (LCD) array substrate comprising: step 1 of depositing a semiconductor layer, a doped semiconductor layer and a metal film for source and drain electrodes sequentially on a base substrate and then forming a data line, a source electrode, a drain electrode and a thin film transistor (TFT) channel region by a first patterning process; step 2 of depositing a first insulating film and a gate metal film sequentially on the substrate after the step 1 and then forming a gate line and a gate electrode by a second patterning process, wherein an insulating layer via hole is formed in the first insulating layer above the drain electrode, and the gate electrode is positioned above the TFT channel region, wherein the step 2 comprises: step 21 of depositing the first insulating layer on the substrate after step 1 and then depositing the gate metal film; step 22 of applying a first photoresist layer on the gate metal film; step 23 of performing an exposure and development process so that the first photoresist layer is formed into a completely removed region, a partially remained region and a completely remained region, wherein the region where the gate line and the gate electrode are to be formed corresponds to the completely remained region, the region where the insulating layer via hole is to be formed above the drain electrode corresponds to the completely removed region, and the remaining region on the substrate corresponds to the partially remained region; step 24 of performing a first etching process so that the gate metal film at a position corresponding to the insulating layer via hole is completely removed and the first insulating layer at this position is partially removed in the thickness direction; step 25 of performing an ashing process to completely remove the first photoresist layer in the partially remained region; step 26 of performing a second etching process to form the gate line and the gate electrode; and step 27 of performing a third etching process so that the first insulating layer at the position corresponding to the insulating layer via hole is completely removed and the drain electrode is exposed; step 3 of depositing a transparent conductive film on the substrate after the step 2 and then forming a pixel electrode by a third patterning process utilizing a second photoresist layer, wherein the pixel electrode is connected with the drain electrode through the insulating layer via hole; and step 4 of forming a second insulating layer on the substrate after the step 3 to cover the gate line and gate electrode.