Patent ID: 6724093
Filing Date: 2004-04-20
Classification: H01L

Abstract:
A semiconductor device comprising a semiconductor chip (10) encapsulated in an envelope of synthetic resin material (100), wherein an insulating layer (20) is present at one surface of the chip (10), a pattern (30) of conductive connections (31-39) is present on the insulating layer (20) and at windows (21) in the insulating layer, an over-layer (40) of substantially brittle insulating material is present on the pattern (30) of conductive connections, and a layer pattern (50) is formed of ductile metal to cover at least most of the surface area of the over-layer (40) of insulating material to provide an interface with the synthetic resin material (100) that reduces stress between the insulating material and the synthetic resin material during thermal cycling of the semiconductor device, and wherein the ductile metal layer pattern (50) comprises distinct parts (50a, 50b, 50c, 50d, etc.) that are electrically isolated and spaced from each other on the over-layer (40), the ductile metal of layer pattern (50) is sufficiently ductile as to deform laterally on the over-layer (40) during thermal cycling of the semiconductor device, and the spacing (21) of the electrically-isolated parts (50a, 50b, 50c, 50d, etc.) is sufficient to avoid a short circuit between the electrically-isolated parts as a result of the lateral deformation.