Patent ID: 9171598
Filing Date: 2015-10-27
Classification: G11C

Abstract:
1. A memory system, comprising: a cell array including a unit cell array, said unit cell array containing plural first lines, plural second lines intersecting said plural first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to said memory cell via said first line and said second line, wherein an access-targeted memory cell of said plural memory cells is defined as an access cell, a first line connected to said access cell of said plural first lines is defined as an access first line and other first lines as non-access first lines, said access circuit includes two first line drivers each operative to alternately control said first lines on alternate lines, one first line driver for controlling said access first line of said two first line drivers is defined as an access-side first line driver and the other first line driver as a non-access-side first line driver, said access-side first line driver and said non-access-side first line driver being arranged across said unit cell array from each other, and said access circuit, on writing data in said access cell, uses said non-access-side first line driver to electrically connect said non-access first line adjacent to said access first line to a first potential power supply via a diode-connected transistor.