Patent ID: 8489962
Filing Date: 2013-07-16
Classification: H03M

Abstract:
1. An LDPC decoder for iteratively decoding an LDPC code on a Galois Field where the code is represented by a predetermined M×N parity check matrix H comprising a plurality of sub-matrices where each sub-matrix is either a zero-matrix or a matrix with a same number of non-zero elements in each row and column; the LDPC decoder being based on a Log-Likelihood Ratio Belief-Propagation algorithm, hereinafter referred to a LLR-BP algorithm, representing passing symbol messages λ nm from a respective symbol-node n (0<=n<N) to a connected check-node m (0<=m<M) and passing check node messages Λ mn from a respective check-node m to a connected symbol-node n; connections between symbol nodes and check nodes being defined by the parity check matrix H; the LDPC decoder comprising: a first memory for storing, for each symbol node, a representation of a respective symbol value of a corresponding symbol of the LDPC code; a second memory for storing a representation of the respective check node messages Λ first computation means for computing, for a next iteration, symbol messages λ a shuffler for receiving from the first computation means symbol messages arranged in a first sequence and supplying the symbol message in a different sequence in dependence on a position of non-zero elements in a corresponding sub-matrix; second computation means (DP-O, DP-I, DP-DI) for computing, in accordance with the LLR-BP algorithm, check node messages and for storing a representation of the computed check node messages in the second memory; the computation being in dependence on symbol messages received from the shuffler by the respective check node; and third computation means for updating the representation of the symbol values in the first memory in dependence on output of the first and second computing means.