Patent ID: 7728411
Filing Date: 2010-06-01
Classification: H01L

Abstract:
1. In a chip-on-lead semiconductor package having a semiconductor die affixed to a leadframe without a leadframe die paddle, a method of reducing capacitance and/or inductance, comprising the steps of: (a) affixing a spacer layer in the form of one of a polyimide tape or a dielectric film to a first surface of the leadframe; (b) affixing the semiconductor die to the spacer layer using an adhesive layer separate from the spacer layer; (c) affixing a rigid member, separate from the leadframe, first spacer layer and adhesive layer, to a second surface of the leadframe, the second surface of the leadframe being opposite the first surface of the leadframe; and (d) encapsulating the semiconductor package within mold compound with the spacer layer and semiconductor die rigid member and portions of the leadframe completely encapsulated within the mold compound.