Patent ID: 8093930
Filing Date: 2012-01-10
Classification: H03L

Abstract:
1. A frequency divider comprising: a phase selection circuit that switches between a plurality of phase-separated signals in response to a fractional control signal to generate a second clock signal; a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the fractional control signal providing when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal; and a plurality of high-speed prescalers that receive a plurality of high-frequency phase-separated signals having an identical frequency and generate the plurality of phase-separated clock signals that are at a lower frequency based on the transition control signal from the counter, the plurality of high-speed prescalers being coupled to provide the plurality of phase-separated clock signals to the phase selection circuit, wherein: the plurality of high-speed prescalers further includes: wherein the first, the second, and the third prescalers and the counter are set to count a reduced number of cycles “N” to adjust a time period of the divided signal, where N is an integer greater than or equal to 1; and wherein a divide-by-N+⅓ function is achieved by switching between the first clock signal, the second clock signal, and the third clock signal in turn after the reduced number of cycles of one of the plurality of high-frequency signals.