Patent ID: 6577534
Filing Date: 2003-06-10
Classification: G11C

Abstract:
A non-volatile semiconductor memory device which executes data writing, reading and erasing using a block including a plurality of sectors having a plurality of memory cells and being arranged in a row direction as a control unit, comprising:a memory cell array having a data area including a plurality of said blocks; a sector selecting circuit receiving a row address signal for designating each of a plurality of sectors included in said data area, selecting an alternate non-defective sector as an alternative to a defective sector when said row address signal designates the defective sector, and selecting said defective sector corresponding to said alternate non-defective sector when said row address signal designates said alternate non-defective sector; and a sector activation circuit for activating a sector selected by said sector selecting circuit, and for activating a sector which is made non-selective by said sector selecting circuit, said alternate non-defective sector being provided in at least one block in accordance with the number of said defective sectors.