Patent ID: 9098637
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A computer-implemented method for verifying a digital design using a computing device comprising: determining one or more tests associated with verifying the digital design; generating, using the computing device, a verification result by performing one or more verification runs on the digital design; merging coverage data generated by the one or more verification runs; ranking the one or more tests based upon, at least in part, a first verification run having a first rank configuration and a second verification run having a second rank configuration, wherein the first and second rank configurations differ, wherein ranking includes performing system-level and block-level tests concurrently and wherein ranking includes ranking the system-level and block-level tests together to determine at least one overlapping test, wherein each rank configuration is user configurable and includes rank element information, metrics cost information, and best “n” run information, wherein metrics cost information is based upon, at least in part, at least one of CPU time and simulation time; and determining an optimized run order based upon, at least in part, the ranking.