Patent ID: 6472692
Filing Date: 2002-10-29
Classification: H01L

Abstract:
The semiconductor device comprising:a first region having a first conductivity type; a second region having a second conductivity type, said second region being formed on top of said first region; a third region having said first conductivity type, said third region being formed on top of said second region; and a fourth region having said second conductivity type, said fourth region being formed on top of said third region; said second region being comprised of a depletion-layer forming auxiliary layer having a short lifetime and formed in the vicinity of said third region; a tail-current suppression layer having a shorter lifetime than that of said depletion-layer forming auxiliary layer and formed in the vicinity of said first region; and a depletion-layer forming suppression layer having a longer lifetime than that of said depletion-layer forming auxiliary layer and formed between said depletion-layer forming auxiliary layer and said tail-current suppression layer, wherein lifetime of said depletion-layer forming suppression layer is formed in such a manner that lifetime on said third region side is shorter than that on said first region side.