Patent ID: 9098491
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A data-transfer subsystem configured to enable data transfer through direct memory access (DMA) between a host memory and any of one or more flash memory modules supportable by the subsystem, the subsystem comprising: a DMA controller for at least transferring data to and from the host memory; a flash-memory controller for at least transferring data to and from any of the one or more flash memory modules; a data buffer coupled to the DMA controller and the flash-memory controller, for buffering data transferred between the DMA controller and the flash-memory controller; a status-register group accessible by the DMA controller and the flash-memory controller, for storing a current status of the data buffer, the current status being related to the data transfer; and a command storing unit configured to: wherein each of the command packages further includes: wherein the DMA controller and the flash-memory controller are configured such that the DMA controller and the flash-memory controller are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer's process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit.