Patent ID: 8810028
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. An integrated circuit package comprising: a package substrate having an array of top electrical contacts disposed on its top surface, and an array of bottom electrical contacts disposed on its bottom surface; a semiconductor die disposed on the package substrate, the semiconductor die having an array of die electrical contacts disposed on its bottom surface, wherein the die electrical contacts are bonded to the package substrate top electrical contacts by a first ball grid array, and wherein a perimeter of the semiconductor die is spaced inwardly from a perimeter of the package substrate such that a perimeter region of the package substrate is not covered by the semiconductor die; a lid having a planar main body disposed on the semiconductor die, and having legs located at corners of the main body disposed on corners of the perimeter region of the package substrate, wherein each of the legs has a non-planar, multi-faceted bottom surface that is divided into a plurality of portions, each of the plurality of portions having a plurality of planes which is not parallel with the main body and extends from an outer edge of the leg toward a center of the leg, wherein the plurality of portions are formed at adjacent side portions of the leg at a corner of the perimeter region of the package substrate, the legs forming openings between adjacent legs on each side of the integrated circuit package and extending from the main body to the package substrate, and wherein a perimeter of the lid main body extends over sides of the perimeter region between the corners of the perimeter region; an inelastic adhesive mechanically attaching the non-planar, multi-faceted bottom surface of each lid leg to the perimeter region of the package substrate; and a thermal interface material disposed between and thermally coupling a bottom surface of the lid main body and a top surface of the semiconductor die.