Patent ID: 6734573
Filing Date: 2004-05-11
Classification: G11C,H01L

Abstract:
A semiconductor memory comprising:a semiconductor substrate; and a memory cell formed in said semiconductor substrate, wherein said memory cell includes: a first inverter having a first input terminal and a first output terminal, said first inverter further having at least one MISFET of a first conductivity type as a first driver transistor, said at least one MISFET having a main terminal connected to said first output terminal; a second inverter having a second input terminal connected to said first output terminal and a second output terminal connected to said first input terminal, said second inverter further having at least one MISFET of said first conductivity type as a second driver transistor, said at least one MISFET having a main terminal connected to said second output terminal; a first access transistor formed by a MISFET of said first conductivity type having a main terminal connected to said first output terminal; and a second access transistor formed by a MISFET of said first conductivity type having a main terminal connected to said second output terminal, said semiconductor substrate includes first to third wells of a second conductivity type opposite to said first conductivity type, said first to third wells are not in contact with one another, said first and second access transistors are both formed in said first well, said first driver transistor is formed in said second well, and said second driver transistor is formed in said third well.