Patent ID: 6930916
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A driver for a memory array, comprising: an enable circuit providing an enable signal; a pull down transistor having its gate connected to the enable signal, to ground an output node when the enable signal is disabled; a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor; an inverter connected between the enable circuit output and the pass transistor; a second pull down transistor connected between ground and the gate of the pass transistor; a series connection of two inverters connected between the output of the first inverter and the gate of the second pull down transistor; and a second p-type transistor connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.