Patent ID: 6117732
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A method of forming a memory device, on a semiconductor substrate, comprising the steps of:providing a first doped region, and a second doped region, in areas of said semiconductor substrate, not occupied by insulator isolation regions;forming a first opening, in a first insulator layer, exposing a portion of the top surface of said first doped region;forming a tunnel oxide layer, on the portion of the top surface of said first doped region, exposed in said first opening in said first insulator layer;forming a polysilicon floating gate structure, completely overlying said tunnel oxide layer, and overlying a portion of said first insulator layer;depositing a second insulator layer;forming a second opening, in said second insulator layer, exposing a portion of the top surface of said polysilicon floating gate structure;forming a thin dielectric layer on the surface of said second insulator layer, and on the portion of the top surface of said polysilicon floating gate structure, exposed in said second opening;forming a third opening in said thin dielectric layer, in said second insulator layer, and in said first insulator layer, exposing a portion of the top surface of said second doped region; andforming a metal structure, with a first portion of said metal structure, overlying and contacting, the portion of said second doped region, exposed in said third opening, and with a second portion, of said metal structure, overlying the portion of said thin dielectric layer, in a region in which said thin dielectric layer resides on the top surface of said polysilicon floating gate structure.