Patent ID: 6400544
Filing Date: 2002-06-04
Classification: H02M,H03K

Abstract:
A clocked switch with current limiting comprising:first and second transistors of the same conductivity type, each having first and second terminals and a control terminal, the conduction through each transistor being responsive to the voltage between the control terminal and the first terminal of the respective transistor, the first terminals of the first and second transistors being coupled together, the control terminals of the first and second transistors being coupled together; a capacitor; a first circuit coupled to the second transistor and the capacitor, the first circuit changing the charge on the capacitor at a rate responsive to the current through the second transistor; a second circuit coupled to the capacitor to controllably set the voltage on the capacitor to a predetermined value responsive to a reset signal; a clock generator coupled to the control terminal of the first transistor and to the second circuit, the clock generator providing a clock signal to the control terminal of the first transistor to successively turn the transistor on and off in normal operation, and providing a reset signal to the second circuit to set the voltage on the capacitor to the predetermined value when the first transistor is turned off; and, a third circuit coupled to the capacitor and a reference voltage to cause the first transistor to turn off earlier than in normal operation responsive to a comparison of the voltage on the capacitor to the reference voltage indicative of an overload condition in the time integral of the current through the first transistor.