Patent ID: 6374392
Filing Date: 2002-04-16
Classification: G01R

Abstract:
A semiconductor test system for testing a semiconductor device, comprising:a waveform memory for storing edge data which defines edges of a test signal waveform to be supplied to a semiconductor device under test based on a test program; a timing generator for generating timing data and a timing pulse for each test cycle, the timing pulse being a time reference of the test cycle and the timing data indicating a delay time relative to the timing pulse, the timing data being produced and stored in the timing generator based on the test program; a wave formatter for generating a set signal and a reset signal for producing the test signal waveform in response to the timing data and the timing pulse from the timing generator; and a virtual timing generator provided between the waveform memory and the timing generator for detecting a relationship between previous edge data and current edge data from the waveform memory corresponding to each of the set signal and the reset signal and removing the current edge data when the current edge data is the same as the previous edge data and allocating the current edge data to a time position where there is an actual change of edge in the test signal waveform; wherein a type of edge in the edge data is reversed between a set edge and a reset edge when the virtual timing generator shifts the current edge data to the time position of the actual change in the test signal waveform.