Patent ID: 6800919
Filing Date: 2004-10-05
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a first, second and third functional areas parted each other by a boundary region on the semiconductor substrate; a memory block formed in the first functional area, and including a plurality of memory cells recording information and a redundancy memory cell, the redundancy memory cell being substituted for at least one memory cell of the plurality of memory cells and recording information in place of the memory cell, the memory block having a function of writing information to and reading information from the memory cell, no fuse being provided in the memory block; a functional circuit block formed in the second functional area, and connected with the memory block via an interconnection line; a program interconnection block formed in the third functional area, the program interconnection block being provided on the substrate so that it does not overlap with the interconnection line on a plane of the substrate and including a program interconnection section which forms a program forming a signal path so that a defective memory cell can be substituted by the redundancy memory cell; and a data transfer section extending over from the program interconnection block to the memory block, and transferring program information relevant to the program of the program interconnection section to the memory block.