Patent ID: 7793192
Filing Date: 2010-09-07
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device comprising: a non-volatile memory including a data error detecting/correcting circuit and memory area consisting of a plurality of physical blocks that is minimum erase unit of data and in which data writing unit is smaller than the minimum erase unit; and a memory controller for controlling write and read of data in said non-volatile memory, including an error correcting circuit having higher error correcting ability than that of said error detecting/correcting circuit in said non-volatile memory, wherein when said memory controller transfers and writes data recorded in a predetermined physical block in said non-volatile memory to a physical block different from said predetermined physical block, said memory controller controls processing so that said error detecting/correcting circuit detects existence or nonexistence of error in transferred data, determines whether error correction is possible when error exists, corrects data recorded in said predetermined physical block when error correction is possible, controls processing to transfer data to said error correcting circuit in said memory controller when error correction is impossible, and controls processing so that said error correcting circuit in said memory controller corrects the error in the transferred data of said predetermined physical block.