Patent ID: 7952409
Filing Date: 2011-05-31
Classification: H03K,H03L

Abstract:
1. A clock generation circuit that generates and outputs a plurality of clocks that have a different delay time relative to an external clock, the clock generation circuit comprising: a first generation unit that generates, by causing the external clock to pass through a first delay element, a first clock that has a first delay time depending on a propagation delay time of the first delay element relative to the external clock, and outputs the generated first clock; a second generation unit that generates, by causing the external clock to pass through a second delay element, a second clock that has a second delay time depending on a propagation delay time of the second delay element relative to the external clock, and outputs the generated second clock; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of the first delay element, and correlates with the propagation delay time of the second delay element, generates a control signal for controlling the third delay elements such that a total of propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock, and controls the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay times of the third delay elements using the control signal.