Patent ID: 6581019
Filing Date: 2003-06-17
Classification: G01R,G06F

Abstract:
A computer system comprising:a data processor fabricated on an integrated circuit; a system bus; a set of peripherals, said set including memory, said memory storing an application program and a test program, said peripheral set including a first peripheral; a multiplexer having a first multiplexer input, a second multiplexer input, a multiplexer output, and a multiplexer control input, said first peripheral being connected either to said first multiplexer input or to said multiplexer output; a remote functional module being coupled to the other of said first multiplexer input and said multiplexer output; a test register having an input coupled to said system bus, said test register having an output coupled to said second multiplexer input, said test register being addressable by said processor during execution of the test program, the test register having a width greater than a width of the second multiplexer input; and test-mode control means for selecting said second multiplexer input only in response to execution of said test program by said processor and not in response to execution of said application program by said processor, said remote functional module being disconnected from the system bus during execution of the application program and coupled to the system bus through at least one intervening peripheral device during execution of the test program.