Patent ID: 8200902
Filing Date: 2012-06-12
Classification: G06F,Y02D

Abstract:
1. A cache device for use in a data processing apparatus to store data values for access by an associated master device, each data value having an associated memory location in a memory device, the memory device being arranged as a plurality of blocks of memory locations, each block having to be activated before any data value stored in that block can be accessed, the cache device comprising: a cache storage having a plurality of cache lines for storing said data values; allocation circuitry, responsive to a data value to be allocated into the cache storage, to determine which cache line of said plurality of cache lines to store said data value into, the cache storage providing more than one cache line in which the data value can be stored, and the allocation circuitry employing an allocation policy to determine one of said more than one cache line as a selected cache line for storing of said data value; eviction circuitry, responsive to an indication of said selected cache line, to evict any data value currently stored in said selected cache line, whereby the evicted data value is written into the memory device at the associated memory location if that evicted data value is more up to date than the data value already stored in the memory device at the associated memory location; and regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern; upon detection of the occurrence of said sequence of accesses by the regular access detection circuitry, said allocation policy employed by the allocation circuitry being altered to increase a likelihood that when an evicted data value output by the eviction circuitry is written to the memory device, the associated memory location resides within an already activated block of memory locations.