Patent ID: 6489662
Filing Date: 2002-12-03
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising: a semiconductor substrate having a silicon-on-insulator (SOI) region and a bulk region; a fuse element for adjusting an analog characteristic of the semiconductor integrated circuit device and comprised of a monocrystal silicon layer formed in the SOI region of the semiconductor substrate; a laser trimming positioning pattern formed in the SOI region of the semiconductor substrate for facilitating trimming of the fuse element, the laser trimming positioning pattern having a high light reflectivity region and a low light reflectivity region comprised of a high light reflectivity film formed of the monocrystal silicon layer; a high speed MOS transistor of a complete depletion type formed in the SOI region of the semiconductor substrate; a high withstand voltage type MOS transistor formed in the bulk region of the semiconductor substrate and electrically connected to the high speed MOS transistor; an electrostatic discharge (ESD) protection element disposed in the bulk region of the semiconductor substrate; and a bleeder resistor comprised of a plurality of resistors disposed in the SOI region of the semiconductor substrate.