Patent ID: 6316809
Filing Date: 2001-11-13
Classification: H01L

Abstract:
An improved silicon MOS transistor integrated circuit comprising a plurality of digital MOS transistor devices and a plurality of analog MOS transistor devices, each of said MOS transistor devices having an MOS gate with a gate threshold voltage V.sub.t and an MOS channel beneath the MOS gate, said digital MOS transistor devices having a channel length equal to L, and said analog MOS transistor devices having a channel length greater than L, each of said analog MOS transistors having:(a) a silicon substrate, said silicon substrate having a first conductivity type,(b) a gate dielectric on said silicon substrate,(c) a polysilicon gate on said gate dielectric,(d) a lightly doped drain (LDD) region in said silicon substrate, said LDD region extending beneath said polysilicon gate by distance x,(e) a depletion control implant region of said first conductivity type in said silicon substrate, said depletion control implant region extending beneath said polysilicon gate by distance y, where y>x and having an impurity level that changes the gate threshold voltage V.sub.t by less than 50 mV,(f) sidewall spacers on said silicon gate,(g) source and drain regions in said silicon substrate,(h) electrical contacts to said gate source and drain, and(i) means for applying an analog signal to said silicon gate.