Patent ID: 6201760
Filing Date: 2001-03-13
Classification: G11C

Abstract:
A double data rate (DDR) synchronous dynamic random access memory (SDRAM), comprising:a memory cell core circuit for simultaneously accessing two memory cells and prefetching data stored in the two memory cells, wherein the two memory cells include first and second memory cells, the first and second memory cells storing first and second bit data, respectively;a signal generating means for generating signals to synchronize the first and second bit data with rising and falling edges of a clock and control an issue order of the first and second bit data, said signal generating means including a count signal generating means for generating a first count signal at the rising edge of the clock and a second count signal at the falling edge of the clock of a single clock cycle, said count signal generating means for activating one of the first and second count signals in response to a first control signal and outputting the activated signal; anda pipeline latch means for latching the first and second bit data prefetched by said memory cell core circuit and issuing the first and second bit data in response to the activated signal output by said signal generating means.