Patent ID: 6134144
Filing Date: 2000-10-17
Classification: G11C,H01L

Abstract:
An electrically erasable and programmable read only memory array, said array comprising:an array of memory cells, each memory cell comprising a single floating gate memory transistor having a plurality of terminals, said array of memory cells arranged in a plurality of rows and a plurality of columns;a plurality of word lines connected to said plurality of rows of memory cells of said array with a word line connected to the memory cells in the same row;a row decoder positioned adjacent one side of said array and connected to said plurality of word lines for receiving an address signal and for supplying a low voltage signal to said plurality of word lines in response thereto;a plurality of first programming lines connected to said plurality of rows of memory cells of said array;a plurality of second programming lines connected to said plurality of rows of memory cells of said array, with a first programming line and a second programming line connected to the memory cells in the same row;said plurality of first and second programming lines are parallel to but spaced apart from said plurality of word lines and extending only to said row decoder; anda high voltage generating circuit, having address decoding circuitry therein, positioned adjacent another side of said array, opposite said one side, and connected to said plurality of first and second programming lines for receiving said address signal and for supplying a high voltage signal to said plurality of first and second programming lines in response thereto, with a first programming line connected to a row of memory cells and a second programming line connected to the same row of memory cells sharing the same address decoding circuitry.