Patent ID: 6694448
Filing Date: 2004-02-17
Classification: G11C

Abstract:
A fuse-controlled, row-redundancy control system for a SRAM with global word lines that includes a plurality of local word lines, comprising:a defective-row multi-bit storage array of static circuits, each of which static circuits is programmed to store one of the address bits of a global word line for a predetermined defective row of the SRAM and each of which static circuits includes a single fuse that is blown to indicate a first state of the one of the address bits and that is not blown to indicate a second state of the one address bit; a comparator that compares respective address bits of the global word line for the predetermined defective row of the SRAM with corresponding address bits of global word line signals received by the SRAM; wherein the comparator includes a fuseless exclusive-logic circuit that compares each bit of the global word line signals received by the SRAM to corresponding ones of the address bits of the global word lines for the predetermined defective row of the SRAM; and wherein the comparator provides a RFLAG control signal that indicates that the stored address bits of the global word lines for the defective row of the SRAM match the respective received global word line bits for the SRAM; and wherein the RFLAG control signal also disables a global word line corresponding to the defective row of the SRAM and enables a redundant global word line for a redundant SRAM row so that the redundant SRAM row is substituted for the defective row of the SRAM.