Patent ID: 8010881
Filing Date: 2011-08-30
Classification: H03M,H04L

Abstract:
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a plurality of memories; a plurality of bit engines such that each bit engine within the plurality of bit engines is operable to be coupled to at least one memory of the plurality of memories; a plurality of check engines such that each check engine within the plurality of check engines is operable to be coupled to at least one memory of the plurality of memories; and a plurality of multiplexers (MUXs) that is operable to: the plurality of memories includes a predetermined number of memories corresponding to a plurality of non-null sub-matrices within a plurality of LDPC matrices that corresponds to a plurality of LDPC codes; the decoder is operable to decode the first LDPC coded signal corresponding to a first LDPC matrix of the plurality of LDPC matrices thereby generating a best estimate of a bit encoded within the first LDPC coded signal; and the decoder is operable to decode the second LDPC coded signal corresponding to a second LDPC matrix of the plurality of LDPC matrices thereby generating a best estimate of a bit encoded within the second LDPC coded signal.