Patent ID: 6765415
Filing Date: 2004-07-20
Classification: H03K

Abstract:
A cascaded chain of clocked full-rail differential logic circuits with shut-off comprising:a first clocked full-rail differential logic circuit with shut-off, said first clocked full-rail differential logic circuit with shut-off comprising: a first clocked full-rail differential logic circuit with shut-off clock input terminal; at least one first clocked full-rail differential logic circuit with shut-off data input terminal; and at least one first clocked full-rail differential logic circuit with shut-off data output terminal; a second clocked full-rail differential logic circuit with shut-off, said second clocked full-rail differential logic circuit with shut-off comprising: a second clocked full-rail differential logic circuit with shut-off clock input terminal; at least one second clocked full-rail differential logic circuit with shut-off data input terminal; and at least one second clocked full-rail differential logic circuit with shut-off data output terminal; a first clock signal coupled to said first clocked full-rail differential logic circuit with shut-off first clock input terminal; a second clock signal coupled to said second clocked full-rail differential logic circuit with shut-off first clock input terminal, wherein; said at least one first clocked full-rail differential logic circuit with shut-off data output terminal is coupled to said at least one second clocked full-rail differential logic circuit with shut-off data input terminal, further wherein; said second clock signal is delayed with respect to said first clock signal by a predetermined delay time.