Patent ID: 7035079
Filing Date: 2006-04-25
Classification: H01G

Abstract:
1. A multilayered chip capacitor, comprising: a capacitor body formed by stacking a plurality of dielectric layers; pluralities of first and second internal electrodes formed on each of the dielectric layers; at least one first external terminal and at least one second external terminal formed on at least one of a top surface and a bottom surface of the capacitor body; and at least one first conductive via hole and at least one second conductive via hole formed in the capacitor body in a stacking direction of the capacitor body to be connected to the first and second external terminals, wherein the first and second internal electrodes formed on the same dielectric layer are spaced apart from each other, and the first and second internal electrodes formed on the stacked dielectric layers overlap with each other with one dielectric layer interposed therebetween, each of the first and second internal electrodes having at least one lead-out portion at positions where the first and second internal electrodes overlap with other first and second internal electrodes formed on a vertically adjacent dielectric layer, the at least one first conductive via hole is formed through the lead-out portions of the first internal electrodes while being electrically insulated from the second internal electrodes, and the at least one second conductive via hole is formed through the lead-out portions of the second internal electrodes while being electrically insulated from the first internal electrodes.