Patent ID: 7474116
Filing Date: 2009-01-06
Classification: H03K

Abstract:
1. A latch circuit comprising a first inverter circuit having two input terminals and two output terminals, wherein only when logic signals having the same logic level are input to the two input terminals, inverted signals of the logic signals are output from the two output terminals, the latch circuit comprising: a feedback circuit including the first inverter circuit; a first input circuit for inputting signals having a logic level opposite to input signals, input to the latch circuit, to the input terminals of the first inverter circuit in synchronization with a clock signal; and a second input circuit for inputting signals having the same logic level as the input signals, input to the latch circuit, to the output terminals of the first inverter circuit in synchronization with a clock signal; wherein, in the feedback circuit, positive feedback is applied from the output terminals of the first inverter circuit to the corresponding input terminals of the first inverter circuit.