Patent ID: 6801462
Filing Date: 2004-10-05
Classification: G11C,H01L

Abstract:
A test device for detecting alignment of deep trench capacitors and word lines in DRAM devices, wherein the test device is disposed in a scribe line region of a wafer, the scribe line region having a plurality of pairs of memory cells, each having two deep trench capacitors deposed at two ends of an active area, two word lines disposed above the active area, and a bit line contact disposed between the two word lines and electrically coupled to the active area, the test device comprising:parallel first and second bar-type deep trenches capacitors disposed in the scribe line region; wherein the first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells adjacent to the first active area respectively, and are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively; a first transistor having a source coupled to the first bar-type deep trench capacitor; a second transistor having a source coupled to the second bar-type deep trench capacitor; and a first bit line contact electrically coupled to drains of the first and second transistors.