Patent ID: 6564310
Filing Date: 2003-05-13
Classification: G06F,G06K,Y02D

Abstract:
A data transfer circuit for transferring data read from a buffer memory to a recording head, comprising:an address setting circuit for setting a read start address in one column to be recorded by the recording head for the buffer memory; an offset setter arranged to set a predetermined offset for the buffer memory, said offset setter arranged to set a predetermined offset for the buffer memory, the offset indicating a difference between the read start address in the one column and a read address in an adjacent column adjacent to the one column; an address creator, arranged to create a predetermined number of consecutive read addresses to be supplied for reading from the buffer memory using the read start address as a read reference address in the one column; and an arithmetic logic calculator, arranged to calculate a new read reference address in the adjacent column, after said address creator has created consecutive read addresses using the read start address as a reference address, in accordance with the offset relative to the read start address so as to provide the new read reference address to said address creator for creating further read addresses, wherein said offset setter is arranged to set the offset to a larger value than the address corresponding to the number of the recording elements, and said address creator is arranged to create the consecutive read addresses corresponding to the number of the recording elements as the predetermined number.