Patent ID: 7233066
Filing Date: 2007-06-19
Classification: H01L,H05K

Abstract:
1. A multilayer wiring substrate comprising: first and third levels of a metal layer, each of said first and third levels of the metal layer being defined by first and second surfaces opposing to each other and third and fourth surfaces opposing to each other; a first insulator layer intervening between said first and third levels of the metal layer, said first level of the metal layer being partially embedded in said first insulator layer such that the second, third and fourth surfaces of said first level of the metal layer are in contact with said first insulator layer while the first surface of said first level of the metal layer forms a substantially flat plane with a surface of said first insulator layer, said third level of the metal layer being formed on said first insulator layer such that the first surface of said third level of the metal layer is in contact with the first insulator layer and the second, third and fourth surfaces of said third level of the metal layer are free from being in contact with the first insulator layer; a second level of a metal layer embedded into said first insulator layer between said first and third levels of the metal layer; a second insulator layer formed to cover said substantially flat plane, said second insulator layer having a first opening to expose a part of the first surface of said first level of the metal layer, said part of the first surface of said first level of the metal layer thereby forming a first metal pad; a third insulator layer formed to cover the second, third and fourth surfaces of said third level of the metal layer and a part of said first insulator layer, said third insulator layer having a second opening to expose a part of the second surfaces of said third level of the metal layer, said part of the second surface of said third level of the metal layer thereby forming a second metal pad.