Patent ID: 6727118
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A method for forming a chip-on-chip module structure, comprising:providing a first semiconductor chip, said first semiconductor chip comprising a first wiring layer and a first electrically conductive substrate, wherein the first wiring layer is within a first portion of the first semiconductor chip, wherein the first electrically conductive substrate is within a second portion of the first semiconductor chip, wherein a bounding surface of the first portion of the first semiconductor chip is coplanar with a first exterior surface of the first semiconductor chip, wherein a bounding surface of the second portion of the first semiconductor chip is coplanar with a second exterior surface of the first semiconductor chip, wherein the bounding surface of the second portion of the first semiconductor chip is electrically coupled to a supply voltage VDD by a first electrically conductive path disposed between the supply voltage VDD and the surface of the second portion of the first semiconductor chip, and wherein the first electrically conductive path does not pass through any portion of the first semiconductor chip; and providing a second semiconductor chip, said second semiconductor chip comprising a second wiring layer and a second electrically conductive substrate, wherein the second wiring layer is within a first portion of the second semiconductor chip, wherein the second electrically conductive substrate is within a second portion of the second semiconductor chip, wherein a bounding surface of the first portion of the second semiconductor chip is coplanar with a first exterior surface of the second semiconductor chip, and wherein a bounding surface of the second portion of the second semiconductor chip is coplanar with a second exterior surface of the second semiconductor chip, wherein the bounding surface of the second portion of the second semiconductor chip is electrically coupled to a ground voltage GND by a second electrically conductive path disposed between the ground voltage GND and the surface of the second portion of the second semiconductor chip, and wherein the second electrically conductive path does not pass through any portion of the second semiconductor chip; and disposing an interconnection layer between the first semiconductor chip and the second semiconductor chip, wherein the interconnection layer electrically couples the first semiconductor chip to the second semiconductor chip, and wherein the supply voltage VDD and the around voltage GND collectively provide power to the first and second semiconductor chips.