Patent ID: 6291259
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A method of fabricating a stackable chip package, comprising:forming a supporting member having a plurality of conductive patterns therein;forming a plurality of first conductive traces on a first surface of the supporting member such that respective ones of the first conductive traces are electrically coupled to corresponding ones of the conductive patterns;attaching a plurality of second conductive traces to a first surface of a chip wherein connecting portions of the second conductive traces are located over the first surface of the chip;attaching a second surface of the chip to a second surface of the supporting member such that connecting portions of the first conductive traces are located below the second surface of chip;attaching respective ones of the second conductive traces to corresponding chip pads of the chip; andattaching respective ones of the second conductive traces to corresponding ones of the conductive patterns in the supporting member.