Patent ID: 7027276
Filing Date: 2006-04-11
Classification: H01L,H02H

Abstract:
1. An electrostatic discharge (ESD) protection circuit comprising: a stacked NMOS transistor pair coupled between a pad and a negative voltage supply with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply; a first voltage divider providing reduced voltage from a high voltage positive power supply to a gate of the first transistor; a first diode string coupled between the gates of the first and second transistors; a second diode string with its anode end coupled to the pad; an inverter with a source of a PMOS transistor thereof, coupled to a cathode end of the second diode string and with its NMOS transistor coupled to the negative power supply, along with an output node of the inverter being coupled to a gate of the second transistor; and a RC circuit coupled to an input node of the inverter, wherein an ESD current travels through the stacked NMOS transistor pair for dissipation.