Patent ID: 6734479
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A semiconductor integrated circuit device having a memory cell, which includes a first MIS.FET and a capacitance element, and a second MIS.FET, comprising:(a) a semiconductor substrate whose surface includes a first semiconductor region of first conductivity type, and a second semiconductor region of the first conductivity type in a region different from said first semiconductor region; (b) third semiconductor regions of second conductivity type which are formed in said first semiconductor region, and which function as a source and a drain of said first MIS.FET, respectively; (c) a first conductor layer which lies on a part of said semiconductor substrate between said third semiconductor regions, and which functions as a gate of said first MIS.FET; (d) fourth semiconductor regions of the second conductivity type which are formed in said second semiconductor region, and which function as a source and a drain of said second MIS.FET, respectively; and (e) a second conductor layer which lies on a part of said semiconductor substrate between said fourth semiconductor regions, and which functions as a gate of said second MIS.FET; wherein said first conductor layer has a stacked structure which includes a first polysilicon film of said first conductivity type, and a first film comprising metal, while said second conductor layer has a stacked structure which includes a second polysilicon film of said second conductivity type, and a second film comprising metal.