Patent ID: 7484187
Filing Date: 2009-01-27
Classification: G06F

Abstract:
1. A method comprising: given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of said device into logic which feeds said device, extracting at least one data independent case; and clock-gating said device with said at least one data independent case; also comprising: eliminating said feedback loop if said function F depends only on Q with a positive polarity; wherein said eliminating comprises: generating a gating function G for said device which generates a 1 when the output of function F is defined to have a value of 1 or 0; ANDing gating function G and a clock signal to generate said clock gating function to said device; and generating a data input function H for said device which passes a 1 when original function F is defined to be a 1, a 0 when original function is defined to be a 0 and any value for all other cases; wherein said first step of generating comprises: creating a binary decision diagram (BDD) for said circuit with a variable representing said output Q as the last variable in said BDD; creating a binary decision diagram (BDD) for said gating function G by replacing all Q nodes with a 0 node and by replacing all leaf nodes with a 1 node; and wherein said second step of generating comprises: creating a BDD for said data function H by replacing all positive Q nodes with a don't care node.