Patent ID: 6967659
Filing Date: 2005-11-22
Classification: G06T,H04N

Abstract:
1. Image processing circuitry, comprising: a two-dimensional image pipeline having a plurality of stages including a first stage and a last stage that is operable to process two dimensional image data to generate successive two-dimensional image frames for display in a two-dimensional image space; a three-dimensional image pipeline having a plurality of stages including a first stage and a last stage that is operable to process three-dimensional image data to render successive three-dimensional image frames for display in a two-dimensional image space; and dual mode sub-processing circuitry, associated with each of said two-dimensional image pipeline and said three-dimensional image pipelines, that is operable in a selected one of a two-dimensional mode and a three-dimensional mode, wherein when in said two-dimensional mode said dual mode sub-processing circuitry performs motion compensation operations associated with said two-dimensional image pipeline at an intermediate stage thereof and wherein when in said three-dimensional mode said dual mode sub-processing circuitry performs rasterization operations associated with said three-dimensional image pipeline at an intermediate stage thereof.