Patent ID: 6033950
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method of forming an integrated circuit having a capacitor and PMOS devices fabricated on the same wafer comprising:providing a layer of gate silicon oxide over the surface of a semiconductor substrate;depositing a first polysilicon layer overlying said gate silicon oxide layer;etching away said first polysilicon layer and said gate oxide layer where they are not covered by a mask to provide a PMOS gate electrode in a first region of said wafer and a bottom plate electrode for said capacitor in a second region of said wafer;depositing a capacitor dielectric layer over the surface of said wafer;depositing a composite polysilicon layer overlying said capacitor dielectric layer wherein said composite polysilicon layer comprises a lower doped polysilicon layer and an upper undoped polysilicon layer; andetching away said composite polysilicon layer and said capacitor dielectric layer where they are not covered by a mask to leave said capacitor dielectric layer and said composite polysilicon layer overlying said bottom plate electrode wherein said composite polysilicon layer forms the top plate electrode of said capacitor to complete the formation of said integrated circuit having a capacitor and PMOS devices fabricated on said same wafer.