Patent ID: 6627540
Filing Date: 2003-09-30
Classification: H01L

Abstract:
A method for forming a dual damascene structure in a semiconductor device, the method comprising:depositing an insulating structure layer including a via level insulating layer, a trench level insulating layer over the via level insulating layer, an etch stopper formed on the trench level insulating layer, a buffer insulating layer formed on the etch stopper and a hard mask layer over the buffer insulating layer on a semiconductor substrate on which an underlying layer including a contact plug is formed, the hard mask layer including a first hard mask sublayer and a second hard mask sublayer formed over the first mask sublayer; after the first and second hard mask sublayers are formed, patterning the second hard mask sublayer to have a first opening having a first width; patterning the first hard mask sublayer to have a second opening having a second width; forming a via hole on the via level insulating layer using the first hard mask sublayer as a mask during formation of the via hole, extending the via hole through the via level insulating layer; and forming a trench connected to the via extended hole in the insulating structure layer using the second hard mask sublayer as a mask during formation of the trench wherein the buffer insulating layer is removed when the trench is formed; wherein a predetermined upper portion of the insulating structure layer and the hard mask layer are removed when the trench and the via hole are formed.