Patent ID: 8482443
Filing Date: 2013-07-09
Classification: H03M

Abstract:
1. A clock timing adjustment device, comprising: a power detection unit configured to receive input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detect powers of the input signals, and output a control signal corresponding to a clock time difference where the power is minimized; and a timing adjustment unit configured to receive a reference clock and the control signal and output the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal, wherein the power detection unit comprises: a differentiator configured to differentiate the input signals and output differentiated values; an absolute value accumulator configured to receive the differentiated values, accumulate absolute values of the differentiated values, and output accumulated values corresponding to the clock time differences; and a controller configured to receive the accumulated values, initialize the absolute value accumulator, and output a control signal corresponding to the clock time difference where the accumulated value is minimized.