Patent ID: 7594095
Filing Date: 2009-09-22
Classification: G06F

Abstract:
1. A processor comprising: a processing core configured to concurrently execute a plurality of threads arranged in a plurality of single-instruction, multiple-data (SIMD) groups, wherein the processing core is configured to execute a first SIMD group comprising a vertex data group of threads executing a vertex shader program and a second SIMD group comprising a pixel data group of threads executing a pixel shader program, each SIMD group including up to a maximum number (P) of threads, where P is at least two, wherein each of the threads in a same one of the SIMD groups executes a same program on different input data, the same program comprising a sequence of instructions; wherein the processing core includes issue logic configured to select one of the SIMD groups and to issue one of the instructions of the same program in parallel for execution in parallel by all of the threads of the selected one of the SIMD groups; and core interface logic coupled to the processing core and configured to initiate execution by the processing core of one or more SIMD groups, the core interface logic including: