Patent ID: 7754551
Filing Date: 2010-07-13
Classification: H01L

Abstract:
1. A method for making very low V t metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions, characterized in that the method uses a low-temperature shallow junction process to lower the interface reaction of CMOSFETs under fabrication processes, which temperature is lower than 900° C., including the steps as follows: A. Apply high-κ gate dielectric deposition, post-deposition anneal, and dual metal-gates deposition; B. Apply gate patterning, wherein self-aligned Ga or Ni/Ga with top capping layer was deposited for p-MOS, followed by 550˜900° C. RTA solid-phase diffusion (SPD); C. For n-MOS, self-aligned H