Patent ID: 6160860
Filing Date: 2000-12-12
Classification: H03L,H04L

Abstract:
A phase-locked loop (PLL) circuit for generating an oscillator output signal, said oscillator output signal having a frequency, comprising:at least one data sampler for sampling adjacent data bits, D.sub.X and D.sub.Y, of an incoming data signal, said incoming data signal having a phase;an edge detector for sampling an edge, E, of said incoming data signal between said two adjacent data bits, D.sub.X and D.sub.Y ;current generating means for producing a first current when said sampled adjacent data bits, D.sub.X and D.sub.Y, and said sampled edge value, E, between said adjacent bits produce a measured sequence value of binary ""101"" or ""010,"" wherein said first current is produced until said measured sequence value indicates the frequency of said oscillator output signal becomes too high, upon which a second current of opposite polarity to said first current is produced;a loop filter having an input and an output, the input being connected to said current generating means and the output producing a filtered current signal; anda governable oscillator having a control terminal and an output, the control terminal being connected to the filtered current signal and the oscillator output being the output of the loop, said oscillator output tracking the phase of the incoming data signal.