Patent ID: 6710664
Filing Date: 2004-03-23
Classification: H03L

Abstract:
A circuit for coarse tuning a fractional-N synthesizer comprising:a) a first divider adapted to further divide a divided reference signal derived from the reference frequency of a phase lock loop (PLL) by a factor M to provide an average reference signal; b) a second divider adapted to further divide a divided controlled oscillator (CO) signal by the factor M to provide an average CO signal wherein the divided reference signal and the divided CO signal are approximately equal when a CO is operating at a desired frequency and the divided CO signal is derived from fractional-N division of the output of the CO for the PLL; and c) tuning logic adapted to compare a frequency of the average reference signal and the frequency of the average CO signal and provide a CO control signal to select a tuning curve for the CO based thereon to effect coarse tuning of the CO.