Patent ID: 6230300
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A computer operable method for optimizing a tree depth of an H-tree network for distributing a clock signal to elements of a semiconductor integrated circuit, comprising the steps of:(a) entering parameters into the computer;(b) defining a short circuit current component PS, cell internal switching current component PI, and switching current of interconnect capacitance component PW of power consumption of the H-tree network with equations employing a tree depth m as a variable;(c) defining power consumption F of the H-tree network as the sum of the components PS, PI, and PW;(d) finding an optimum tree depth that minimizes the power consumption F; and(e) designing the H-tree network by applying the optimum tree depth,wherein the step (d) differentiates the power consumption F with respect to the tree depth m as .differential.F/.differential.m and finds the tree depth that minimizes the power consumption F by solving the following equation:.differential.F/.differential.m=0 andwherein the power consumption F of the H-tree network with the optimum tree depth is reduced as compared to the H-tree network prior to optimizing the tree depth.