Patent ID: 8015428
Filing Date: 2011-09-06
Classification: G06F

Abstract:
1. A processing device, comprising: a CPU; a first interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device; a first control circuit for the first interface; a clock generation circuit that generates a clock; a second interface for performing data transfer with the external terminal device by using an internal clock generated by the clock generation circuit; a second control circuit for the second interface; and a clock control circuit that switches a system clock used by at least the CPU in the processing device between the external clock and the internal clock in accordance with either one of the first and second interfaces used by the processing device in data transfer with the external terminal device, wherein, when the system clock is switched between the external clock and the internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation, and an external terminal complying with ISO 7816-2, wherein the first interface is an interface for performing data transfer complying with ISO 7816-3, and the second interface is an interface for performing USB transfer complying with ISO 7816-12.