Patent ID: 6879537
Filing Date: 2005-04-12
Classification: G11C

Abstract:
1. A semiconductor memory device having a plurality of operation modes, including: a first cycle generation circuit for generating timing pulses of a first cycle; a second cycle generation circuit for generating timing pulses of a second cycle which is shorter than said first cycle; an internal voltage generation circuit for generating a predetermined internal voltage upon receiving inputs of said timing pulses from said first or second cycle generation circuit; a timing pulse switching circuit for selecting said timing pulses from said second cycle generation circuit and supplying said selected timing pulses to said internal voltage generation circuit when said semiconductor memory device is transitioned from a first operation mode to a second operation mode in said plurality of operation modes; and a control circuit for outputting first, second and third control signals in accordance with an operation mode selecting signal which selects a single operation mode in said plurality of operation modes. wherein said first and second cycle generation circuits are controlled in operation and non-operation independently in accordance with said first and second control signals, respectively, wherein said timing pulse switching circuit selects said timing pulses of either one of said first and second cycle generation circuits in accordance with said third control signal, and wherein said control circuit includes a counter circuit for counting said timing pulses outputted from said second cycle generation circuit, and outputting said third control signal when a counted value becomes a previously set value.