Patent ID: 6445636
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A dynamic random access memory (â€œDRAMâ€ ), comprising:a first array of memory cells; a second array of memory cells; an address circuit to receive an address and being structured to access locations in the first and second arrays corresponding to the address; a data path circuit structured to couple data between a data terminal and the first and second arrays; a control circuit to receive memory commands and being structured to generate control signals corresponding to the memory commands to access the first and second arrays; and a refresh circuit coupled to the control circuit and the first and second arrays, the refresh circuit being structured to refresh the memory cells in either the first array or the second array, the refresh circuit being structured to cause write data to be temporarily stored in a write buffer responsive to a write memory access when either the first or second arrays is being refreshed, to determine when the refresh is completed, and to transfer the data from the write buffer to the array that was being refreshed after the refresh has been completed.