Patent ID: 6960505
Filing Date: 2005-11-01
Classification: H01L,Y10S

Abstract:
1. A method for manufacturing a memory cell circuit, which comprises the steps: providing a body selected from the group consisting of a semiconductor body and a layer of semiconductor material forming the body; providing a series of layers on the body, the series of layers including a first oxide layer, a memory layer disposed above the first oxide layer and intended for storing charge carriers, and a second oxide layer disposed above the memory layer; forming an auxiliary layer on top of the series of layers; removing the auxiliary layer with an exception of a part over a region of an intended channel region so that a remaining part of the auxiliary layer has sufficiently steep edges; forming spacers on two mutually opposing edges of the auxiliary layer; using the spacers as masks and introducing a doping material into the body for forming a source region and a drain region with a channel region disposed between the source region and the drain region; removing the remaining part of the auxiliary layer; removing parts of the second oxide layer applied to the memory layer and parts of the memory layer which have been left free by the spacers; removing the spacers; forming a dielectric layer which covers at least the channel region and edges of the memory layer; and applying a conductor track which runs over the channel region.