Patent ID: 7404168
Filing Date: 2008-07-22
Classification: G06F

Abstract:
1. A method for placing cells of a netlist, comprising the steps of: receiving said netlist, said netlist describing a circuit to be fabricated on a semiconductor chip, said netlist specifying a particular group of cells and wire connections between said cells; receiving a specification of a placement area describing a plurality of sites on said semiconductor chip where said cells may reside, wherein a circuit density of a ratio of total cell area to total available site area is up to one hundred percent; performing a coarse placement process which assigns initial locations to said cells; performing a detailed placement process that assigns a final location to each of said cells by optimizing a cost function dependent on sites in pairs of rows, thereby allowing swapping of cells between said pairs of rows based on said cost function, wherein each cell location is aligned with a valid site boundary, no two cells are overlapping, and each cell is assigned to a group of legal sites so that said each cell can be placed on said legal sites without violating constraints set forth in said specification of said placement area.