Patent ID: 6438671
Filing Date: 2002-08-20
Classification: G06F

Abstract:
A computer processing apparatus for supporting a computer system divisible into a plurality of logical partitions, each partition having a respective portion of the real address space of said computer system, said computer processing apparatus comprising:effective address generating logic, said effective address generating logic generating effective addresses to be accessed, wherein at least some of said effective addresses generated by said effective address generating logic are base real addresses; at least one state register for recording processor operating parameters, said at least one state register including a mode designator, said mode designator designating an operating mode; real address partitioning logic, said real address partitioning logic modifying one or more high order bits of said base real address to generate a partitioned real address when said base real address is associated with a first operating mode, said partitioned real address lying within the portion of the real address space of said computer system of a logical partition associated with said computer processing apparatus, and said real address partitioning logic not modifying said one or more high order bits of said base real address when said base real address is associated with a second operating mode.