Patent ID: 7904774
Filing Date: 2011-03-08
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising; A. combinational logic having parallel inputs for receiving stimulus data and parallel outputs for outputting response data, B. parallel scan paths each having parallel outputs coupled to at least some of the parallel inputs of the combinational logic, parallel inputs coupled to at least some of the parallel outputs of the combinational logic, a serial input for inputting stimulus data and a serial output for outputting response data, C. a decompressor circuit having a serial input, control inputs, and parallel outputs, each of said parallel outputs being coupled to a unique one of said parallel scan path serial inputs, D. a compressor circuit having a serial output and parallel inputs, each of said parallel inputs being coupled to a unique one of said parallel scan path serial outputs, E. a test access port having first and a second interfaces, F. a test channel interface circuit having first and a second interfaces,