Patent ID: 8373225
Filing Date: 2013-02-12
Classification: H01L

Abstract:
1. A Method for manufacturing a super-junction trench MOSFET comprising the steps of: growing an epitaxial layer of a first conductivity type upon a substrate of the first conductivity type, wherein said epitaxial layer has a lower doping concentration than said substrate; forming a block layer onto a top surface of said epitaxial layer; applying a trench mask on said block layer; forming a plurality of gate trenches, and mesas between adjacent gate trenches in said epitaxial layer by etching through open regions in said block layer; keeping said block layer substantially covering said mesas after formation of said gate trenches to block sequential angle ion implantation into top surfaces of said mesas; carrying out an angle Ion Implantation of a second conductivity type dopant into said mesas through said open regions in said block layer to form a plurality of first doped column regions in said mesas; carrying out an angle Ion Implantation of said first conductivity type dopant into said mesas through said open regions in said block layer to form a plurality of second doped column regions adjacent to the sidewalls of said gate trenches and in parallel with said first doped column regions; removing said block layer after formation of said first and second doped column regions; forming a thick oxide layer along inner surfaces of said gate trenches by thermal oxide growth of oxide deposition; depositing a first doped poly-silicon layer filling said gate trenches to serve as source electrodes; etching back said source electrodes from the top surface of said epitaxial layer; etching back said thick oxide layer from an upper portion of said gate trenches; forming a thin oxide layer as a gate oxide covering a top surface of said thick oxide layer, along upper inner surfaces of said gate trenches and along sidewalls of said source electrodes above the top surface of said thick oxide layer; depositing a second doped poly-silicon layer filling the upper portion of said gate trenches to serve as split gate electrodes; etching back said split gate electrodes by CMP (Chemical Mechanical Polishing) or plasma etch; carrying out a body implantation of the second conductivity type dopant and a step of body diffusion to form body regions; applying a source mask onto the top surface of said epitaxial layer; and carrying out a source implantation of the first conductivity type dopant and a source diffusion to form source regions; forming a contact interlayer; forming a plurality of trenched source-body contacts penetrating through said contact interlayer, said source regions and extending into said body regions; and forming body contact doped regions of the second conductivity type in said body regions and surrounding at least bottoms of said trenched source-body contacts, said body contact doped regions having a heavier doping concentration than said body regions.