Patent ID: 7355893
Filing Date: 2008-04-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: an n-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region; and a gate electrode formed over the charge storage layer; a power supply circuit formed on the semiconductor substrate and connected to the first diffused region, the power supply circuit, pumping a voltage supplied from an outside power supply and outputting the pumped voltage; and writing means which, upon writing to the n-channel memory cell transistor, applies a ground voltage to the second diffused region, and applies a negative voltage supplied from the power supply circuit to the first diffused region to thereby flow current between the first diffused region and the second diffused region and to store charges in the charge storage layer.