Patent ID: 8441947
Filing Date: 2013-05-14
Classification: H04L,H04W

Abstract:
1. A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels, the packet controller comprising: a plurality of inputs to receive a respective plurality of data packet start signals from a plurality of transceivers, each of the plurality of data packet start signals being indicative of a start of reception of a data packet by a respective one of the plurality of transceivers on a respective one of the plurality of communication channels; a clock source to supply a periodic clock signal; a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of data packet start signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process a respective data packet start signal independently of every other one of the plurality of processing modules; an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels; and a mode selection input to receive a selection signal from a processor to select between at least a receive mode and a control mode of operation of the packet controller, wherein: