Patent ID: 6052523
Filing Date: 2000-04-18
Classification: G06F

Abstract:
A transient analysis method during circuit simulation that prevents an occurrence of a forced quit error due to a time step falling outside a domain treatable by a computer, said method comprising the steps of:calculating, via a processor, a predetermined variable at a calculation point t.sub.n on a time axis;determining a next calculation point t.sub.n+1 by predicting a change in the variable based on the values of the variable prior to and at t.sub.n ;judging whether a time step (t.sub.n+1 -t.sub.n), which is a time step between the calculation points t.sub.n+1 and t.sub.n, falls within a domain treatable by a computer; andadjusting the position of a previously set calculation point when the time step was judged not to fall within the domain;wherein upon adjustment of the calculation point, each step described above is performed again, and a value of the variable at the calculation point t.sub.n+1 is then calculated so as to avoid the error, andwherein each step described above is performed on a computer.