Patent ID: 8710620
Filing Date: 2014-04-29
Classification: H01L

Abstract:
1. A method of manufacturing a super-junction semiconductor device, the method comprising: growing by epitaxy a first sub-layer on a substrate layer; implanting impurities of a first conductivity type in first sections of a first surface of the first sub-layer using an aligned low divergence ion implant process, wherein a main beam direction deviates from a main crystal direction, along which channeling of implant ions occurs, by at most 1 degree and a main beam incidence angle divergence is at most ±0.5 degree; growing by epitaxy a second sub-layer on the first sub-layer; and implanting impurities of the first conductivity type in sections of a first surface of the second sub-layer in a projection of the first sections along the main crystal direction using the aligned low divergence ion implant process; wherein a tilt of at most 1 degree between the main beam direction and the main crystal direction, along which channeling of implant ions occurs, and the main beam incidence angle divergence of at most ±0.5 degree are achieved for at least 80% of an area of a wafer including the substrate layer.