Patent ID: 8510705
Filing Date: 2013-08-13
Classification: G06F

Abstract:
1. A computer-based method for checking stub lengths of via stubs of a printed circuit board (PCB) layout, the method comprising: displaying a check interface by using a computer; selecting signal transmission lines from a currently run PCB layout according to input through the check interface by using the computer; receiving a reference stub length input through the check interface by using the computer; determining the actual stub length of each via stub of each via each selected signal transmission line connected to according to an information file corresponding to the currently run PCB layout by using the computer; and determining that a design of one via stub satisfies the design standards by using the computer, if the actual stub length of the one stub via is less than or equal to the reference length, determining that a design of one via stub does not satisfy the design standards by using the computer, if the actual stub length of the one via stub is greater than the reference stub length, and determining that the via the via stub of which is not designed to satisfy the design standards is a to-be-checked via by using the computer.