Patent ID: 7576396
Filing Date: 2009-08-18
Classification: H01L

Abstract:
1. An integrated circuit comprising: a substrate; a first FET formed on said substrate, said first FET comprising a first terminal coupleable to a load, a second terminal and a control terminal, said second terminal being connected to said substrate; said substrate comprising a parasitic body diode coupled between said first FET first terminal and said substrate, said body diode becoming conductive when a reverse voltage across said first FET first terminal and said substrate is at least a first diode forward voltage; and a first voltage detector formed on said substrate, said first voltage detector having a first input coupled to said first FET first terminal, a second input coupled to said substrate, and an output coupled to said first FET control terminal, said first voltage detector being responsive to a reverse voltage level at said first FET first terminal less than said first diode forward voltage to turn said first FET on for the duration of a reverse voltage having at least said reverse voltage level, whereby said parasitic body diode is prevented from injecting current into said substrate.