Patent ID: 9209764
Filing Date: 2015-12-08
Classification: G11C,H03F

Abstract:
1. An integrated circuit comprising: a first P-type metal oxide semiconductor (PMOS) transistor configured to be connected between a first power supply voltage terminal and a first node and to provide current in response to a self-bias signal; a self-biased differential amplifier configured to be connected between the first node and a second node, to compare an input signal with a reference voltage, to provide the self-bias signal to a self-biasing node, and to output an output signal through an output node; and a first N-type metal oxide semiconductor (NMOS) transistor configured to be connected between the second node and a second power supply voltage terminal and to sink current at the second node in response to the self-bias signal, wherein the self-biased differential amplifier comprises: a plurality of PMOS transistors connected in parallel between the first node and the self-biasing node; a plurality of NMOS transistors connected in parallel between the second node and the self-biasing node; and a swing stabilizing block configured to be connected between an input node to which the input signal is applied and the self-biasing node, to convert the input signal, and to provide the converted input signal to the self-biasing node.