Patent ID: 6025229
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method for manufacturing flash memory having at least a semiconductor substrate, a tunneling oxide layer formed above the semiconductor substrate, a floating gate formed above the tunneling oxide layer, an inner dielectric layer formed above the floating gate and a control gate formed above the inner dielectric layer, comprising the steps of(a) coating a photoresist layer over the substrate, and then using the photoresist layer as a mask, performing a first ion implantation to implant ions into a portion of the substrate followed by a thermal operation for driving in the implanted ions to form a drain region in a portion of the substrate;(b) forming polysilicon spacers on the sidewalls of the control gate, the inner dielectric layer and the floating gate; and(c) performing a second ion implantation to implant ions into a portion of the substrate to form a source region; wherein after step (a) but before step (b), further includes growing an oxide layer over the substrate.