Patent ID: 6414532
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A gate ground circuit for I/O electrostatic discharge (ESD), comprising:a substrate comprising a P-well and an N-well, said P-well having N+ doped active areas; at least one driver circuit deposited in said P-well, said driver circuit having one or more inputs and an output, said output coupled to an I/O pad, said driver circuit in communication with a voltage supply and a reference potential, said driver circuit used to apply signals to said one or more inputs; at least one ESD protection circuit deposited in said P-well, said ESD protection circuit in communication with said voltage supply and said reference potential, said ESD protection circuit further coupled to said I/O pad, said ESD protection circuit providing protection from ESD; at least one Vcc/Vss protection circuit deposited in said P-well, said Vcc/Vss protection circuit in communication with said voltage supply and said reference potential, said Vcc/Vss protection circuit comprising an NMOS transistor and resistive means, the gate of said NMOS transistor and one end of said resistive means having a common terminal T, the other end of said resistive means coupled to said reference potential, said Vcc/Vss protection circuit providing further protection from said ESD voltages by causing said NMOS transistor to go into controlled conduction; and at least one clamping circuit coupled between said I/O pad and said terminal T, where, upon receiving an ESD, said clamping circuit pulls down to said reference potential a gate of one of said MOS transistors in said driver circuit and in said ESD protection circuit, thus improving the tolerance of said gate ground circuit to ESD through uniform ESD current distribution in said driver circuit and ESD protection circuit.