Patent ID: 8202744
Filing Date: 2012-06-19
Classification: H01L

Abstract:
1. A wafer TSV (through silicon via) forming method comprising: arranging a wafer having a front surface that has a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition means, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; performing a first etching on the back surface of the wafer in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition means, thereby forming etching holes with middle depth; and performing a second etching in an isotropic manner on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.