Patent ID: 6734067
Filing Date: 2004-05-11
Classification: H01L

Abstract:
A method of manufacturing a semiconductor storage device comprising the steps of:(a) forming first and second diffusion layers working as source/drain regions in a semiconductor substrate; (b) forming an insulating film for isolation on an area including a part of said first diffusion layer and a part of said second diffusion layer after the step (a); (c) forming an isolation insulating film by patterning said insulating film for isolation; (d) forming first and second lower contact holes respectively reaching said first and second diffusion layers by patterning said insulating film for isolation after, before or simultaneously with the step (c); (e) forming a first insulating film on said semiconductor substrate in an area surrounded with said isolation insulating film after the step (c); (f) forming a first conductive film, a second insulating film, a second conductive film and a third insulating film successively on said first insulating film after the step (e); (g) forming a gate upper insulating film, a control gate electrode and a capacitor dielectric film by patterning said third insulating film, said second conductive film and said second insulating film after the step (f); (h) forming an insulator sidewall on side faces of said capacitor dielectric film, said control gate electrode and said gate upper insulating film after the step (g); (i) forming a floating gate electrode by removing said first conductive film through etching by using said insulator sidewall as a mask after the step (h); (j) forming a tunneling insulating film on a side face of said floating gate electrode after the step (i); (k) forming an erase gate electrode opposing said floating gate electrode with said tunneling insulating film sandwiched therebetween after the step (j); and (l) forming first and second contact members filled in said first and second lower contact holes; (m) forming an interlayer insulating film on said semiconductor substrate after the steps (d) and (l); (n) forming first and second upper contact holes in said interlayer insulating film respectively reaching said first and second lower contact holes; and (o) forming a metal interconnect layer filled in said first and second upper contact holes.