Patent ID: 8883592
Filing Date: 2014-11-11
Classification: H01L

Abstract:
1. A non-volatile memory cell comprising: a substantially single crystalline semiconductor substrate of a first conductivity type; a first region of a second conductivity type along a surface of the substrate; a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region; a channel region between the first region and the second region in the substrate along the surface thereof; said channel region having a first portion and a second portion, with the first portion adjacent to the first region; a word line having a bottom and a side, with the bottom spaced apart from the first portion of the channel region; said word line comprising a polysilicon portion and a metal portion with the metal portion along the bottom of the word line closest to the first portion of the channel region; a high K dielectric insulator between the bottom of the word line and the first portion of the channel region; a floating gate spaced apart from the second portion of the channel region and spaced apart and adjacent to the word line; a coupling gate spaced apart from the floating gate and spaced apart and adjacent to the word line; and an erase gate spaced apart from the second region, said erase gate adjacent to and spaced apart from the coupling gate and the floating gate; wherein said metal portion of said word line extends along the side of the word line and is between the polysilicon portion and the floating gate and the coupling gate; wherein said high K dielectric insulator extends along the side of the word line and is between the metal portion and the floating gate and the coupling gate.