Patent ID: 7107301
Filing Date: 2006-09-12
Classification: H03H,H03K

Abstract:
1. A digital signal processing device for processing an input signal, the digital signal processing device comprising: delay generation circuitry, the delay generation circuitry including an input for receiving the input signal and a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith, the delay generation circuitry including a zero delay signal path and at least one nonzero delay signal path associated therewith; and processing circuitry coupled to the delay generation circuitry, the processing circuitry being operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.