Patent ID: 6512244
Filing Date: 2003-01-28
Classification: H01L

Abstract:
A semiconductor-on-insulator (SOI) device, comprising:an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween, the active layer having isolation regions defining an active region, and a source region, a drain region and a body region disposed therebetween being formed in the active region; a gate disposed on the semiconductor layer above the body region, the gate being operatively arranged with the source, drain and body regions to form a transistor; and wherein the body region includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having a doping concentration that is greater than a doping concentration of an upper portion of the body region and the abrupt region having opposite P-type or N-type doping as the source and drain regions and wherein the upper portion of the body region has a doping concentration of about 1Ã—1017 atoms/cm3 to about 5Ã—1018 atoms/cm3 and the abrupt region has a doping concentration of about 1Ã—1019 atoms/cm3 to about 1Ã—1020 atoms/cm3.