Patent ID: 9209077
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method of fabricating an interconnect structure for an integrated circuit, the method comprising: forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate, the first hardmask layer comprising a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating; forming a second hardmask layer above the first hardmask layer, the second hardmask layer comprising a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction; and using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer, the etching comprising removing a portion of the one or more sacrificial materials.