Patent ID: 6287968
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method of manufacturing a semiconductor wafer, the method comprising:forming a partially completed semiconductor wafer having at least one trench formed in a layer of interlayer dielectric;forming a conformal barrier layer on a surface of the interlayer dielectric including walls of the at least one trench;forming a conformal seed layer on the barrier layer;forming a layer of photoresist on the conformal seed layer;patterning and developing the layer of photoresist exposing portions of the conformal seed layer;etching away the exposed portions of the conformal seed layer and the underlying conformal barrier layer thereby negating a requirement for a chemical mechanical polishing process;removing the layer of photoresist from the at least one trench; andfilling the at least one trench with the conductive material by a method selected from the group of electroplating and electroless plating, wherein a top surface of the conductive material is substantially planar with the surface of the interlayer dielectric thereby negating a requirement for a chemical mechanical polishing process to remove excess conductive material.