Patent ID: 6782459
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A method for transferring data from a first timing domain to a second timing domain, the method comprising the steps of:selecting a first mode value when a time delay between the first and second domains is within a first range; selecting a second mode value when the time delay is within a second range; sending a clock signal from the first timing domain to an asynchronous memory device, the clock signal having a first transition from a first logic state to a second logic state of the clock signal; responsive to the first transition of the clock signal, receiving from the memory device a first data signal and a first timing signal; capturing in the second timing domain a first word of the first data signal responsive to a first transition in the first timing signal from a first logic state to a second logic state of the first timing signal; when the first mode value is selected, transferring the first word from the second timing domain to the first timing domain at a second transition of the clock signal from the first logic state to the second logic state; and when the second mode value is selected, transferring the first word from the second timing domain to the first timing domain at a third transition of the clock signal from the second logic state to the first logic state, where the third transition is subsequent to the second transition.