Patent ID: 7551479
Filing Date: 2009-06-23
Classification: G11C

Abstract:
1. A reference fail bit verification circuit, comprising: a fail bit counter which counts a number of fail bits in response to a fail check signal to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to detecting the first reference fail bit and the second reference fail bit, respectively, wherein the first reference fail number and the second reference fail number are different, and the fail check signal is generated as a pulse upon detection of a fail bit; and a bit verification block which generates a reference bit verification signal that is activated in response to a transition of the first counting signal and the second counting signal, wherein the reference bit verification signal is activated in response to at least one of the activation of the first counting signal in a first mode, and the activation of the second counting signal in a second mode.