Patent ID: 7399399
Filing Date: 2008-07-15
Classification: H01L,H05K,Y10T

Abstract:
1. A method for manufacturing a semiconductor package substrate, comprising: providing a circuit board having a circuit layer disposed on at least one surface thereof, wherein said circuit board having at least one free area, wherein said circuit layer having a plurality of electrically connecting pads distributed on the periphery of said free area; forming a conductive layer on the surfaces of said circuit board and said circuit layer thereon; forming a first resist layer on said conductive layer, and forming an opening on the surface of said first resist layer to expose said conductive layer overlaying said electrically connecting pads of said circuit layer and said free area; removing said conductive layer exposed through said opening of said first resist layer to expose said electrically connecting pads and said free area; forming a second resist layer on said first resist layer, said electrically connecting pads and said free area respectively, forming an opening in said second resist layer to expose said electrically connecting pads and said free area, and covering remnants exposed on the periphery of said opening of said first resist layer as a result of the removal of said conductive layer; electroplating a metal protecting layer on the surfaces of said electrically connecting pads exposed in said opening of said second resist layer; removing said first and second resist layers and said conductive layer clad in said first resist layer; and removing said free area to form a cavity penetrating said circuit board.