Patent ID: 9111814
Filing Date: 2015-08-18
Classification: G02F,H01L

Abstract:
1. A method for manufacturing an array substrate, comprising a step to form conductive layer patterns and insulation layer patterns on a base substrate, wherein the conductive layer patterns at least comprise a gate line, a gate electrode, an active layer, a source electrode, a drain electrode, a data line and a pixel electrode, wherein the gate line does not overlap with the gate electrode; and wherein forming of the gate line, the gate electrode, and the pixel electrode comprises: sequentially forming a transparent conductive thin film and a gate metal thin film on the base substrate; applying photoresist on the gate metal thin film; exposing with a double-tone mask plate and developing the photoresist to form a photoresist pattern comprising a photoresist-retained region, a photoresist-partially-retained region and a photoresist-removed region, wherein a photoresist thickness of the photoresist-retained region is larger than that in the photoresist-partially-retained region, the photoresist of the photoresist-retained region merely covers a region for forming the gate line, the photoresist of the photoresist-partially-retained region covers a region for forming the gate electrode and the pixel electrode, and the photoresist-removed region is other regions; conducting a first etching to remove the gate metal thin film and the transparent conductive thin film in the photoresist-removed region to form the gate line; ashing to remove the photoresist by the photoresist thickness in the photoresist-partially-retained region; conducting a second etching to remove the gate metal thin film exposed in the photoresist-partially-retained region to form the gate electrode and the pixel electrode; and removing the remaining photoresist.