Patent ID: 9159413
Filing Date: 2015-10-13
Classification: G11C,H01L

Abstract:
1. An integrated circuit comprising: a semiconductor substrate; a first dielectric layer overlying the substrate; an adjustable resistor overlying the first dielectric layer, a resistance of the adjustable resistor being representative of a value of digital data stored in the adjustable resistor; a heating element adjacent the adjustable resistor and writing digital data to the adjustable resistor; a second dielectric layer between the adjustable resistor and the heating element; a bit line in ohmic electrical connection with both the adjustable resistor and the heating element and providing the value of the digital data during a data read cycle of the adjustable resistor; a word line in ohmic electrical connection with the adjustable resistor; and a heater line in ohmic electrical connection with the heating element, the heater line being different from the word line and the bit line.