Patent ID: 6815248
Filing Date: 2004-11-09
Classification: B82Y,G11C,H01F,H01L

Abstract:
A method of fabricating a resistive semiconductor memory device, comprising:providing a workpiece; forming a first inter-level dielectric over the workpiece; disposing a plurality of first conductive lines within the first inter-level dielectric; forming a seed layer over the first conductive lines by depositing a material selected from the group consisting of WN and TaN; forming a first magnetic layer over the seed layer; forming a tunnel barrier layer over the first magnetic layer; depositing a second magnetic layer over the tunnel barrier layer; depositing a cap layer over the second magnetic layer; depositing a hard mask material over the cap layer; patterning the hard mask material to form a hard mask; using the patterned hard mask to pattern the cap layer, second magnetic layer, and tunnel barrier layer to form a plurality of tunnel junctions; and patterning the first magnetic layer with a different pattern than that of the second magnetic layer.