Patent ID: 7076771
Filing Date: 2006-07-11
Classification: G06F

Abstract:
1. Apparatus for processing data, said apparatus comprising: (i) a processor core; (ii) a main memory operable to store instruction words and data words; (iii) a data store operable to store words from said main memory accessed by a data store port of said processor core; (iv) an instruction store operable to store words from said main memory accessed by an instruction store port of said processor core; and (v) an instruction interpreter operable to read instruction words from said instruction store; wherein (vi) said instruction interpreter is operable to modify a slow form instruction within said instruction store to a fast form instruction of one or more possible fast form instructions and to write said fast form instruction to said data store, said slow form instruction and said fast form instruction having a common functionality when executed by said interpreter; and (vii) said instruction interpreter is operable upon reading a slow form instruction from said instruction store to check for a corresponding fast form instruction within said data store and, if said fast form instruction is present within said data store, then to execute said fast form instruction instead of said slow form instruction.