Patent ID: 7105417
Filing Date: 2006-09-12
Classification: H01L

Abstract:
1. A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming sequentially a lower electrode and a dielectric layer having a high dielectric constant on a semiconductor substrate which has gone through predetermined processes; forming a first metal layer as a type of flat board on the dielectric layer; forming a poly-silicon layer on the first metal layer; patterning the poly-silicon layer and the first metal layer; forming a second metal layer covering the patterned poly-silicon layer and first metal layer and the semiconductor substrate, wherein a side wall of the patterned first metal layer is electrically connected to the second metal layer such that the patterned poly-silicon layer is surrounded by the patterned first metal layer and the patterned second metal layer; and patterning the second metal layer to thereby form an upper electrode constituted with the patterned second metal layer, the patterned poly-silicon layer, and the patterned first metal layer.