Patent ID: 6992916
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. A semiconductor memory device having a pair of bit lines and at least one word line comprising: a first inverter having an output as a first memory node, wherein the first inverter includes a first MOS transistor of a first conductive type and a second MOS transistor of a second conductive type being different from the first conductive type; a second inverter having another output as a second memory node, wherein the second inverter includes a third MOS transistor of the first conductive type and a fourth MOS transistor of the second conductive type, wherein the second memory node is coupled to an input of the first inverter through a first resistor, wherein the first memory node is coupled to an input of the second inverter through a second resistor, wherein each of the first resistor and the second resistor is formed by having a gate structure for each of the first and second inverters, wherein the gate structure includes a layer of silicide material on a selective portion and includes another portion that is substantially void of the silicide material; and a pair of access transistors, each coupled to one of the pair of bit lines, the at least one word line and one of the memory nodes, wherein the first resistor is prepared by coating the layer of the silicide material on the selective portion of the gate structure of the first and second MOS transistors, and connecting the another portion of the gate structure that is substantially void of the silicide material to the drain of the third MOS transistor and the drain of the fourth MOS transistor.