Patent ID: 7457836
Filing Date: 2008-11-25
Classification: H03H,H03M

Abstract:
1. A bi-quad filter circuit, comprising: an input for receiving an input signal; at least one binary rate multiplier (BRM) configured to receive and convert the input signal to a binary rate signal; an output for outputting the binary rate signal; a first BRM of said at least one binary rate multiplier, configured to receive an input signal and to output a binary rate signal; a first integrator configured to receive an output from the first BRM and output a first integrated signal; a second BRM of said at least one binary rate multiplier, configured to receive the first integrated signal from the first integrator and to output a second binary rate signal; a second integrator configured to receive the second binary rate signal from the second BRM and to output a second integrated signal; a third BRM of said at least one binary rate multiplier, configured to receive the second integrated signal from the second integrator, and to output a third binary rate signal, wherein the second integrator is configured to receive the third binary rate signal from the third BRM and to process it with the second binary rate signal from the second BRM; and a fourth BRM of said at least one binary rate multiplier, configured to receive the second integrated signal from the second integrator, and to output a fourth binary rate signal, wherein the first integrator is configured to receive the fourth binary rate signal from the fourth BRM and to process it with the first binary rate signal from the first BRM.