Patent ID: 6538277
Filing Date: 2003-03-25
Classification: H01L

Abstract:
A split-gate flash memory cell comprising:providing a semiconductor substrate having active and passive regions defined; a shallow trench isolation formed in said substrate; a floating gate structure further comprising a first polysilicon layer, an oxide layer on top, which in turn is covered by a silicon nitride layer formed on said substrate; a novel poly-tip formed of said floating gate structure, said poly-tip having a thickness between about 80 to 100 Ã¥; a hot temperature oxide (HTO) layer covering said floating gate structure, including said poly-tip; a control gate formed over said HTO layer serving as inter-dielectric poly; oxide spacers formed over sidewalls of said floating gate and said control gate; a self-aligned source line formed in said substrate; source and drain regions in said substrate; and a metal plug in a contact hole contacting said source region.