Patent ID: 7734897
Filing Date: 2010-06-08
Classification: G06F

Abstract:
1. A superscalar data processing apparatus having a plurality of execution threads, each execution thread being operable to process a sequence of operations including at least one memory access operation, the superscalar data processing apparatus comprising: a plurality of execution pipelines operable to execute the operations; issue logic operable to allocate each operation to one of said execution pipelines for execution by that execution pipeline; at least two of said execution pipelines being memory access capable pipelines which are capable of executing memory access operations, each memory access capable pipeline being associated with only a subset of said plurality of execution threads for the purpose of executing memory access operations, said subset is less than all of said plurality of execution threads; the issue logic being operable, for each execution thread, to allocate any memory access operations of an execution thread to an associated memory access capable pipeline.