Patent ID: 7730286
Filing Date: 2010-06-01
Classification: G06F

Abstract:
1. An apparatus comprising: a multi-resource processor including execution logic to speculatively execute a second transaction nested within a first transaction; a memory associated with the processor to hold a first set of values from a first set memory locations of the shared memory to be speculatively modified during execution of the first transaction, and a second set of values from a second set of memory locations of the shared memory to be speculatively modified during execution of the second transaction, wherein the memory is further to hold in a stack to include a reference to second abort handler code associated with the second transaction stacked on a reference to first abort handler code associated with the first transaction; a hardware monitor determine if an invalidating access to the second set of memory locations occurs during a pendancy of the second transaction; wherein the processor is to pop the reference to the second abort handler code off the stack in response to the hardware monitor determining an invalidating access to the second set of memory locations occurred during the pendancy of the second transaction and execute the second abort handler code to restore the second set of values back to the second set of memory locations.