Patent ID: 6184712
Filing Date: 2001-02-06
Classification: H03K

Abstract:
A lookup table circuit, comprising:a decoder for generating a plurality of read address signals and a plurality of write address signals in response to a first set of input signals;a logic/memory array including:a plurality of programmable elements arranged in rows and columns, each programmable element including a latch for storing a bit value, a first write transistor, an inverter, and a read transistor,a plurality of write word lines for transmitting write address signals generated by the decoder, the plurality of write word lines including a first write word line connected to a gate of the first write transistor of a first programmable element,a plurality of write bit lines including a first write bit line connected to the first write transistor of the first programmable element such that a bit value transmitted on the first write bit line is written to the latch of the first programmable element in response to a first write address signal transmitted on the first write word line,a plurality of read word lines for transmitting read address signals generated by the decoder, the plurality of read word lines including a first read word line connected to a gate of the read transistor of the first programmable element, anda plurality of read bit lines including a first read bit line connected to the read transistor of the first programmable element such that a bit value stored in the latch of the first programmable element is transmitted through the inverter and the read transistor of the first programmable element onto the first read bit line in response to a first read address signal transmitted on the first read word line; anda multiplexing circuit connected to the plurality of read bit lines for passing a bit value transmitted on one of the plurality of read bit lines in response to a second set of input signals,wherein the decoder comprises:a first input terminal for receiving a first input signal;a second input terminal for receiving a second input signal;a write control terminal for receiving a write control signal;a first logic gate for generating the first write address signal in response to the first and second input signals and the write control signal; anda second logic gate for generating the first read address signal in response to the first and second input signals.