Patent ID: 6285056
Filing Date: 2001-09-04
Classification: H01L

Abstract:
An MOS gated semiconductor device comprising a substrate having a surface, source and drain regions in said substrate at said surface separated by a channel region, said channel and said drain regions adjoining one another at a p-n junction, there being, during operation of said device, a path for current from said source region through said channel region and past first and second successive points in said drain region spaced at respectively greater first and second distances from said p-n junction, said drain region containing dopant atoms of both conductivity types providing a net quantity of fixed charges, the net concentration of said fixed charges being a minimum at said junction and rising continuously with increasing distance from said junction to said first point such that, upon the onset of an avalanching condition caused by the reverse biasing of said p-n junction. a depletion laver spreads into said drain region a maximum distance from said p-n junction past said first point to said second point, where, from said first point towards said second point, a uniform concentration of net fixed charges is present, and said first distance of said first point from said p-n junction is at least 50% of said second distance of said second point from said p-n junction.