Patent ID: 7231537
Filing Date: 2007-06-12
Classification: G11C

Abstract:
1. A fast data access circuit having an input clock signal and an input data burst signal comprising a plurality of data bits, the input clock signal having a frequency, the circuit comprising: a mode/configuration register for generating a mode control signal in response to a loaded configuration word comprising at least one mode control bit and at least one clock frequency selection bit that is set in response to the input clock signal frequency; a clock delay circuit coupled to the input clock signal and the mode/configuration register, the clock delay circuit providing, in response to the at least one clock frequency selection bit, a selectable time delay to the input clock signal to produce a delayed clock signal such that the time delay is smaller for higher input clock signal frequencies; a multiplexing circuit having a first input coupled to the input clock signal and a second input coupled to the delayed clock signal, the multiplexing circuit outputting a selected clock signal in response to the mode control signal; control logic for generating a plurality of register control signals in response to the selected clock signal; and a data first-in-first-out register, coupled to the control logic and the input data burst signal, for outputting each of the plurality of data bits at a rate selectable by the plurality of register control signals.