Patent ID: 6937532
Filing Date: 2005-08-30
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a memory cell array including a plurality of memory cell rows and at least one redundant memory cell row for repairing a defective memory cell row of the memory cell rows that includes a defective memory cell, each of the memory cell rows comprising a plurality of memory cells arranged in a row direction, and the at least one redundant memory cell row comprising a plurality of redundant memory cells arranged in the row direction; a redundancy repair signal generator for generating a redundancy repair signal that indicates an address of the defective memory cell row; and a row decoder for receiving a row address signal that indicates a memory cell row including a memory cell to be accessed and selecting the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator; wherein the redundancy repair signal generator is located opposite to the row decoder with the memory cell array sandwiched between the row decoder and the redundancy repair signal generator.