Patent ID: 8638592
Filing Date: 2014-01-28
Classification: G11C,H01L,Y10T

Abstract:
1. A multi-port SRAM comprising: a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line; a second set of bit lines including a second true bit line and a second complementary bit line; a data node and a complementary data node; a first set of pass transistors including a first true pass transistor and a first complementary pass transistor, the first true pass transistor for coupling the first true bit line to the data node in response to an assertion of a first word line and the first complementary pass transistor for coupling the first complementary bit line to the complementary data node in response to an assertion of the first word line; a second set of pass transistors including a second true pass transistor and a second complementary pass transistor, the second true pass transistor for coupling the second true bit line to the data node in response to an assertion of a second word line and the second complementary pass transistor for coupling the second complementary bit line to the complementary data node in response to an assertion of the second word line; a first pull up transistor including a first current terminal coupled to a first voltage terminal, a second current terminal coupled to the data node, and a control terminal coupled to the complementary data node; a second pull up transistor including a first current terminal coupled to the first voltage terminal, a second current terminal coupled to the complementary data node, and a control terminal coupled to the data node; a first pull down transistor including a first current terminal coupled to a second voltage terminal, a second current terminal coupled to the data node, and a control terminal coupled to the complementary data node; and a second pull down transistor including a first current terminal coupled to the second voltage terminal, a second current terminal coupled to the complementary data node, and a control terminal coupled to the data node; wherein the first true pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor; wherein the first complementary pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor; wherein the second true pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor; wherein the second complementary pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor; and wherein the second true pass transistor is located in a first active region, the first pull down transistor is located in a second active region, and first pull up transistor is located in a third active region, wherein the second active region is located between the first active region and the third active region on a substrate.