Patent ID: 6104627
Filing Date: 2000-08-15
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor chip having first through fourth sides;a first interconnection disposed along the first side of said semiconductor chip and supplied with a source potential level or a ground potential level;a second interconnection disposed along the second side opposed to the first side and supplied with the source potential level or the ground potential level; anda plurality of sub-array regions disposed between said first interconnection and said second interconnection, said each sub-array region including a plurality of memory cells and a plurality of sense amplifiers respectively connected to said memory cells, said memory cells and said sense amplifiers being disposed in each of said sub-array regions,said sense amplifiers disposed in one of said sub-array regions being activated in response to the potential level supplied to said first interconnection,said sense amplifiers disposed in another one of said sub-array regions being activated substantially simultaneously with said sense amplifiers disposed in said one of said sub-array regions in response to the potential level supplied to said second interconnection.