Patent ID: 6747307
Filing Date: 2004-06-08
Classification: H01L

Abstract:
A combined transistor and capacitor structure comprising:a transistor having a plurality of alternating source and drain regions formed in a substrate of semiconductor material; and a capacitor formed over the transistor, the capacitor having: at least first and second levels of electrically conductive parallel lines, the lines of the levels arranged in vertical rows, the lines in each of the rows being substantially parallel; at least one via connecting the first and second levels of lines in each of the rows thereby forming a parallel array of vertical capacitor plates; and a dielectric material disposed between the vertical plates of the array; wherein the vertical array of capacitor plates are electrically connected to the plurality of alternating source and drain regions of the transistor, the source and drain regions forming opposing nodes of the capacitor, thereby electrically interdigitating the vertical array of capacitor plates.