Patent ID: 8952547
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A contact structure of a MOS transistor comprising: a first contact and a second contact formed within and substantially co-planar with a first dielectric layer on a semiconductor substrate, wherein said first contact directly contacts a source region of said MOS transistor and the second contact directly contacts a drain region of said MOS transistor, wherein a first length of the first contact is larger than a first width of the first contact, and wherein a second length of the second contact is larger than a second width of the second contact; a third contact formed within and substantially co-planar with a second dielectric layer formed over the first dielectric layer, said third contact directly contacting said first contact, wherein a third length of the third contact is smaller than a third width of the third contact; a fourth contact formed within and substantially co-planar with the second dielectric layer, said fourth contact directly contacting said second contact, wherein a fourth length of the fourth contact is about equal to a fourth width of the fourth contact; and a fifth contact formed within and substantially co-planar with the second dielectric layer, said fifth contact directly contacting a gate region of said MOS transistor, wherein a fifth length of the fifth contact is about equal to a fifth width of the fifth contact; wherein the lengths of the contacts are in a direction parallel to a channel width direction of the MOS transistor and the widths of the contacts are in a direction perpendicular to the channel width direction of the MOS transistor, wherein the first length of the first contact is larger than the third length of the third contact.