Patent ID: 6085302
Filing Date: 2000-07-04
Classification: G06F

Abstract:
A superscalar microprocessor comprising:a plurality of segment registers configured to store a plurality of segment base addresses;a plurality of decode units configured to concurrently decode a plurality of instructions, wherein each of said plurality of decode units is configured to detect a displacement within a respective one of said plurality of instructions, and wherein said each of said plurality of decode units is configured to determine which one of said plurality of segment registers comprises a selected segment register identified by said respective one of said plurality of instructions;a first plurality of reservation stations, wherein each one of said first plurality of reservation stations is coupled to a respective one of said plurality of decode units and to said plurality of segment registers, and wherein said first plurality of reservation stations are each configured to generate a first sum comprising said displacement and one of said plurality of segment base addresses, and wherein said one of said plurality of segment base addresses is stored in said selected segment register;a plurality of address generation units, wherein each one of said plurality of address generation units is coupled to a respective one of said first plurality of reservation stations, and wherein said plurality of address generation units are each configured to generate a linear address comprising a second sum of said first sum and at least one register operand identified by said respective one of said plurality of instructions; anda load/store unit coupled to said plurality of address generation units, wherein said load/store unit is configured to perform a memory operation upon receipt of said linear address from said plurality of address generation units.