Patent ID: 7543113
Filing Date: 2009-06-02
Classification: G06F

Abstract:
1. A cache memory system capable of adaptively accommodating various memory line sizes, comprising: cache memory having sets of ways; and cache logic configured to transmit a read request in response to a cache miss, the read request having an address identifying a memory line to be retrieved from external memory in response to the read request and to be transmitted to the cache logic, the memory line identified by the address representing only a portion of a way line for a single set, the cache logic configured to select one of the ways for storing the memory line based on which portion of the way line is represented by the memory line identified by the address, the cache logic further configured to store, in the selected way, the memory line identified by the address, wherein the cache logic is capable of operating in at least a first mode of operation and a second mode of operation, the cache logic configured to receive a first plurality of memory lines if operating in the first mode of operation and to receive a second plurality of memory lines if operating in the second mode of operation, each of the first plurality of memory lines having a first size and each of the second plurality of memory lines having a second size different than the first size, wherein the cache logic is configured such that each of the first plurality of memory lines is assigned to and fully associative within a respective one of the sets identified by the address, and wherein the cache logic is configured such that each of the second plurality of memory lines is assigned to and partially associative within a respective one of the sets identified by the address.