Patent ID: 8949649
Filing Date: 2015-02-03
Classification: G09G,H03M,H04L

Abstract:
1. A signal processing apparatus comprising: an input block configured to receive a predetermined number of items of data and a first enable signal, wherein the first enable signal has an active state in an interval where data is valid in synchronization with a first clock; a count block configured to count, with a second clock faster than said first clock being a reference, a number of clock signals in an interval where said first enable signal is inactive; an enable signal control block configured to set a second enable signal to an active state for a predetermined number of clock signals of said second clock, and set said second enable signal to an inactive state for said number of clock signals counted by said count block; an enable signal output block configured to output said second enable signal; and a data output block configured to output said predetermined number of items of data in synchronization with said second clock in an interval where said second enable signal is active.