Patent ID: 8990749
Filing Date: 2015-03-24
Classification: G06F

Abstract:
1. A computer-implemented method of scheduling memory built-in-self-test (MBIST) for an integrated circuit having a plurality of memory devices, comprising: (a) assigning a weight to each scheduling parameter of a plurality of scheduling parameters associated with MBIST circuitry of the integrated circuit, wherein the MBIST circuitry is to be fabricated on an integrated circuit substrate together with an integrated circuit design having a plurality of memory devices to be tested by the MBIST circuitry; (b) calculating an estimate for each scheduling parameter of the plurality of scheduling parameters using a compact model, wherein the compact model models a relationship between the plurality of scheduling parameters and a plurality of memory factors associated with each memory device of the plurality of memory devices, wherein the compact model is formulated from test data of a plurality of test memory devices, and wherein each memory device factor influences one or more scheduling parameters of the plurality of scheduling parameters; (c) applying the weights to the plurality of estimated scheduling parameters; (d) varying a schedule to generate a cost function that depends on the plurality of scheduling parameters, wherein the schedule defines the order for testing the plurality of memory devices during MBIST of the fabricated integrated circuit; and (e) minimizing the cost function using an optimization technique to generate an optimized schedule for testing the plurality of memory devices during MBIST of the fabricated integrated circuit.