Patent ID: 6785758
Filing Date: 2004-08-31
Classification: G06F

Abstract:
A bus interface unit capable of transferring machine specific register (MSR) requests between a plurality of bus devices, said bus interface unit comprising:a plurality of input ports capable of receiving incoming MSR requests from said plurality of bus devices; a plurality of output ports capable of transmitting data to said plurality of bus devices; and a controller capable of reading N routing bits associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in said N routing bits to a first designated value, wherein said controller, in response to a determination that said first ID value does not equal said first designated value: 1) realigns said N routing bits such that remaining ones of the N-M bits outside said predetermined M-bit field are moved into said predetermined M-bit field and 2) transmits said realigned N routing bits via a first one of said plurality of output ports identified by said first ID value.