Patent ID: 9159738
Filing Date: 2015-10-13
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells each having a first transistor element composed of an insulated gate FET, a second transistor element composed of an oxide semiconductor insulated gate FET, and a capacitive element are arranged at least in a column direction, wherein each of the memory cells includes a memory node formed at a connection point of a gate electrode of the first transistor element, a source electrode of the second transistor element, and one end of the capacitive element, and a control node formed at a connection point of a drain electrode of the first transistor element and a drain electrode of the second transistor element, each of the memory cells arranged in respective rows belonging to the same column includes the control node connected to a first control line shared in the same column and extending in the column direction, the first transistor element having a source electrode connected to a data signal line shared in the same column and extending in the column direction, the second transistor element having a gate electrode connected individually to a first selection line, and the capacitive element having the other end connected individually to a second selection line, a switching element having one end connected to the first control line, and the other end connected to a voltage supply line is provided with respect to each first control line, and the switching element is turned on to drive the first control line in an initialization operation to initialize a voltage state of the memory node, and in a reading operation to read the voltage state of the memory node, and turned off to set the first control line to a floating state in a writing operation to write a memory voltage in the memory node.