Patent ID: 9213523
Filing Date: 2015-12-15
Classification: G06F

Abstract:
1. A machine implemented method comprising: checking in an executable thread portion a floating-point (FP) addition operation to determine if a first source operand of the FP addition operation is a product of a FP multiplication operation; and if the first source operand is determined to be said product and said FP addition and multiplication operations are of the same precision, then replacing that FP addition operation with a double-rounded combined FP multiply-add operation and marking the FP multiplication operation as fused; and executing the double-rounded combined FP multiply-add operation as part of the executable thread portion instead of the FP multiplication operation and the FP addition operation; checking in the executable thread portion a fused FP multiplication operation to determine if its product is to be used by another operation; and if a product of the fused FP multiplication operation is determined not to be used by any other operation, then removing the fused FP multiplication operation.