Patent ID: 6208354
Filing Date: 2001-03-27
Classification: H04N

Abstract:
A video graphics circuit that efficiently utilizes memory bandwidth, the video graphics circuit comprising:a memory, wherein the memory includes a portion allocated to storing graphics information, wherein the portion allocated to storing graphics information is greater than an amount of memory sufficient to store graphics information to be displayed as a single image in a portion of a display, wherein excess memory of the portion allocated to storing graphics information is divided into an array, and wherein the array contains a plurality of pre-rendered graphics images for future display; anda display overlay engine operably coupled to the memory, wherein the display overlay engine fetches one of the plurality of pre-renderd graphics images from the array to produce a fetched pre-rendered graphics image and blends the fetched pre-rendered graphics image with at least one additional display data source to produce a display output signal to be provided to the display.