Patent ID: 6215192
Filing Date: 2001-04-10
Classification: H01L

Abstract:
An integrated circuit package mounted in a substantially parallel plane with respect to a surface of a substrate comprising a first integrated circuit chip and a second integrated circuit chip having a same function,wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus,the integrated circuit package further comprising:a plurality of pins connected to the common bus, anda plurality of pads respectively connected to the plurality of pins,wherein the plurality of pins includes first pins corresponding to the first integrated circuit chip,the plurality of pads includes first pads corresponding to the first integrated circuit chip,each distance between a first point at which each one of the first pins is connected to the common bus and a second point at which each one of the first pins is respectively connected to each one of the first pads is substantially equal to each other such distance, andthe plurality of pins are disposed so as to reduce dead spaces of the integrated circuit package.