Patent ID: 7518203
Filing Date: 2009-04-14
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a) a semiconductor substrate with a front side and a back side, b) a source region arranged on the front side of the semiconductor substrate, c) a drain region arranged on the front side of the semiconductor substrate, d) an external gate region arranged on the front side of the semiconductor substrate that serves to control a conduction channel located underneath the external gate region, e) an inner gate region for collecting free charge carriers that are generated in the semiconductor substrate, wherein the inner gate region is arranged in the semiconductor substrate at least partially below the external gate region in order to control the conduction channel from below as a function of the accumulated charge carriers, f) a clear contact for removing the accumulated charge carriers from the inner gate region, g) a drain-clear region that can be selectively controlled as an auxiliary clear contact or as a drain, said drain-clear region being arranged on the front side of the semiconductor substrate, and h) an additional barrier contact that is arranged on the front side of the semiconductor substrate in a lateral direction between the external gate region and the drain clear region in order to build up a controllable potential barrier between the inner gate region and the clear contact that prevents the charge carriers accumulated in the inner gate region from being removed by suction from the clear contact.