Patent ID: 8441274
Filing Date: 2013-05-14
Classification: G01R,H01L

Abstract:
1. A manufacturing method of manufacturing a wafer unit for testing provided with a plurality of test circuits that are for testing a plurality of semiconductor chips formed on a semiconductor wafer, the method comprising: forming the plurality of test circuits on a circuit wafer coupled to pads of the circuit water; forming, on a predetermined surface of a connection wafer, a plurality of circuit pads to be electrically connected to the plurality of test circuits by the pads of the circuit wafer; forming, on a rear surface of the connection wafer opposing the predetermined surface, a plurality of wafer pads to be electrically connected to the plurality of semiconductor chips; forming a plurality of long via holes extending through the connection wafer between the circuit pads and wafer pads; and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads, wherein: the plurality of wafer pads of the connection wafer are formed at a pad interval different from a pad interval of the plurality of circuit pads; the manufacturing method further comprising: