Patent ID: 8866260
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a chip having an external contact pad exposed to accept a connection to an external device, the chip having one or more intermetal dielectric layers and one or more metallization layers disposed within the one or more intermetal dielectric layers, the external contact pad disposed over a topmost metallization layer of the one or more metallization layers; one or more decoupling metal-insulator-metal (MIM) capacitors aligned directly under the external contact pad, the one or more decoupling MIM capacitors being non-planar capacitors; an insulating layer disposed over topmost surfaces of the one or more decoupling MIM capacitors and under the external contact pad; and one or more vias disposed in the insulating layer and electrically coupling the external contact pad to at least one of the one or more decoupling MIM capacitors.