Patent ID: 7577818
Filing Date: 2009-08-18
Classification: G06F

Abstract:
1. An address-generating arrangement for a microprocessor comprising: a base address-generating unit including a plurality of base registers and at least one base arithmetic unit having an address output, said address output including a first address, wherein said first address is a complete address having width equal to the width of an address register useable in program execution; an address-generating expansion unit having an address bus output, said address bus output including a second address that includes an address extension, wherein said second address is another complete address having width equal to the width of the address register useable in program execution; and an interface for selectively connecting one of said address output and said address bus output to one of said plurality of base registers in said base address-generating unit, wherein said base address-generating unit and said address-generating expansion unit are configured to substantially independently generate complete addresses namely said first and second addressees useable in microprocessor program execution, respectively.