Patent ID: 6709925
Filing Date: 2004-03-23
Classification: H01L

Abstract:
A method for manufacturing a split-gate flash memory cell, the method comprising the steps of:(a) providing a substrate; (b) forming a tunnel oxide layer over the substrate; (c) forming a tip type peak floating gate layer of conducting material over a portion of said tunnel oxide layer, wherein said tip type peak floating gate layer includes a tip and an angle of said tip is substantially less than 90 degrees; (d) forming an inter-gate insulating layer over said tip type peak floating gate layer wherein said inter-gate insulating layer generally follows a topology of said tip type peak floating gate layer; (e) forming a control gate layer of conducting material over said inter-gate insulating layer, wherein said control gate layer generally follows a topology of said inter-gate insulating layer and said tip type peak floating gate layer; (f) patterning a gate electrode and etching down said control gate layer, said inter-gate insulating layer, said tip type peak floating gate layer, and said tunnel oxide layer; (g) defining a source and a drain adjoining the tunnel oxide region by using a self-align technique.