Patent ID: 7913210
Filing Date: 2011-03-22
Classification: G06F

Abstract:
1. A method of circuit design comprising: using a computer system in determining sequential slack associated with a respective register in a circuit design; wherein the act of determining includes obtaining a limit upon clock cycle duration applicable to the circuit design; wherein the act of determining further includes determining as the sequential slack, an amount of delay that is not greater than each individual maximal limit of delay for each individual structural cycle of which the respective register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration; using the determined sequential slack to evaluate a first design choice involving a structural cycle in the circuit design in which the register is a constituent; using a computer system in determining a critical cycle delay within the circuit design; and selecting a second design choice in the circuit design that decreases the critical cycle delay within the circuit design.