Patent ID: 6674797
Filing Date: 2004-01-06
Classification: H04N

Abstract:
Apparatus for use in an encoder to ensure integrity of a hypothetical decoder buffer of a video buffer verifier comprising:a source of a video encoding bit rate; an encoder buffer including a second bit content; a video encoder having a bit rate controller including a model buffer having a first bit content, said model buffer being representative of said hypothetical decoder buffer and said first bit content of said model buffer being representative of an inferred bit content of said hypothetical decoder buffer, said video encoder having a variable encoding bit rate and generates a representation of a delay interval between encoding a video frame and decoding said video frame; a transmission controller responsive to a control signal for controllably inhibiting transmission of bits from said encoder buffer; and a control signal generator for generating said control signal in accordance with a prescribed relationship dependent on said video encoding bit rate, said first bit content and said second bit content for generating said control signal, said control signal generator including a first generator which is response to said variable video encoding bit rate and said delay interval for generating a representation of a number of bits drained from said encoder buffer during a prescribed interval and an excess bits generator responsive said instantaneous video encoding bit rate, said representation of bits drained, said first bit content and said second bit content to generate said control signal, and said representation of bits drained being determined in accordance with &Integral;t-eeDt&it;video_rate&it;(Ï„)&it;â€ƒ&it;&dd;Ï„=drainIntegral,where video rate(&tgr;) is the instantaneous video encoding bit rate, eeD in said delay interval and drainIntegral is the representation of bits drained.