Patent ID: 8984367
Filing Date: 2015-03-17
Classification: G06F,G11C,H03K

Abstract:
1. A method for operating an integrated circuit that includes a memory array comprising a plurality of memory elements and associated address lines and data lines, wherein a first set of memory elements in the memory array is coupled to a first address line and a second set of memory elements in the memory array is coupled to a second address line that is different from the first address line, the method comprising: detecting errors in the first and second sets of memory elements using a first circuit, wherein the first circuit includes first and second trees of logic gates; in response to detecting errors with the first circuit, locating and correcting the detected errors in the first and second sets of memory elements with a second circuit, wherein the second circuit locates and corrects the detected errors in the first and second sets of memory elements within a first time period, wherein the first circuit detects the errors in the first and second sets of memory elements within a second time period, and wherein the first time period is longer than the second time period; and receiving data bits from the first set of memory elements with the first tree of logic gates while receiving data bits from the second set of memory elements with the second tree of logic gates.