Patent ID: 6549449
Filing Date: 2003-04-15
Classification: G11C

Abstract:
A semiconductor memory device comprising:a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a capacitor whose one end is connected to a plate line, a plurality of word lines, and a plurality of bit lines constituting a pair of bit lines connected to a sense amplifier; and a control circuit which controls the semiconductor memory circuit to set the bit lines to a high level to write â€œ1â€  data into the memory cells regardless of a logic level of data to be written, in a state where a potential of a gate of the cell transistor of each memory cell is raised from a first potential of a standby time to a second potential of an active time, and thereafter to set the bit lines to a low level to write â€œ0â€  data into the memory cells with â€œ0â€  data to be written, in a state where the potential of the gate of the cell transistor is changed to a third potential higher than the first potential and lower than the second potential.