Patent ID: 7248122
Filing Date: 2007-07-24
Classification: G06F,H03M

Abstract:
1. A clock circuit for outputting serial data bits defining a data word, the clock circuit comprising: an oscillator with an output and a control signal input, wherein the output carries bit clock pulses with a frequency responsive to the control signal input, and wherein the oscillator is designed to start a frequency higher than a previously set level, the set level being higher than that necessary to preserve the output data bit integrity; a comparator that compares the clock frequency with the set level and outputs a responsive control signal to the oscillator control signal input, wherein, if the clock frequency is higher than the set level, the responsive control slows the clock frequency, and if the clock frequency is lower than the set level, the responsive control signal speed up the clock frequency; and means for preventing a bit clock pulse from occurring and for ensuring that there is a data bit transition during the missing clock pulse time, wherein the combination of the missing bit clock pulse and the data bit transition defines a data word.