Patent ID: 9134776
Filing Date: 2015-09-15
Classification: G06F

Abstract:
1. A device comprising: a platform controller hub PCH comprising a reset control pin and a disable control pin; a basic input/output system BIOS chip, connected to the PCH, to control the PCH to send a low logic level from the reset control pin to the reset pin to reset a Ethernet controller during booting of the device; a timing adjusting circuit; and the Ethernet controller, comprising a reset pin and a disable pin, the reset pin connected to the reset control pin via the timing adjusting circuit, and the disable pin connected to the disable control pin via the timing adjusting circuit; wherein the PCH is further controlled to send a low logic level from the disable control pin to the disable pin to disable the Ethernet controller during booting of the device, and the timing adjusting circuit is configured to delay the low logic level, which makes the low logic level of the disable pin come later than the high logic level of the reset pin.