Patent ID: 7830165
Filing Date: 2010-11-09
Classification: G01R

Abstract:
1. A method for testing an integrated circuit for potential latchup sites, comprising: applying a power supply voltage and a programming voltage to the integrated circuit; monitoring a power supply current and programming voltage current flowing through the integrated circuit; monitoring the power supply voltage and the programming voltage; applying a radiation beam to at least one area of the integrated circuit; scanning the radiation beam through the integrated circuit; adjusting a scanning resolution of the radiation beam on the integrated circuit by adjusting a spot size of the radiation on the integrated circuit; adjusting a moving speed of the radiation beam on the integrated circuit after adjusting the spot size of the radiation; detecting an occurrence of a latchup at the radiation spot by detecting a change in the programming voltage current through the integrated circuit upon applying the radiation beam; and recording a location of the radiation spot on the integrated circuit when the programming voltage current changes.