Patent ID: 8859388
Filing Date: 2014-10-14
Classification: H01L

Abstract:
1. A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device, the method comprising: forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; forming a sealing layer in the sealing recess over the STI fill, wherein the sealing layer comprises a high-k (HK) material; forming an oxide fill over the sealing layer; planarizing a top surface of the oxide fill such that the top surface of the oxide fill is level with a top surface of a pad nitride layer, wherein the pad nitride layer is located on top of a pad oxide layer, the pad oxide layer being located on a top surface of the substrate, wherein a portion of the sealing layer is formed on top of the pad nitride layer, and wherein planarizing the top surface of the oxide fill removes the portion of the sealing layer that is located on top of the pad nitride layer; after planarizing the top surface of the oxide fill, removing a wing portion of the sealing layer, the wing portion of the sealing layer being located between the oxide fill and the pad nitride layer; removing the pad nitride layer after removing the wing portion of the sealing layer; and removing the pad oxide layer and the oxide fill after removing the pad nitride layer.