Patent ID: 7061785
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A semiconductor device comprising: a memory chip including first bonding pads for address arranged along a first side of the memory chip, and second bonding pads for data arranged along a second side which faces the first side in an opposed manner; a package substrate including first bonding leads arranged along a first side of the package substrate corresponding to the first side of the memory chip, and second bonding leads arranged along a second side of the package substrate corresponding to the second side of the memory chip; a semiconductor chip including third bonding pads arranged along a first side thereof, an address output circuit, fourth bonding pads arranged along a second side thereof which faces the first side in an opposed manner, a data input/output circuit which serves for memory access, and a signal processing circuit having a data processing function, wherein the first and third bonding pads are connected in common to the first bonding leads of the package substrate and the second and fourth bonding pads are connected in common to the second bonding leads of the package substrate, and wherein the memory chip and the semiconductor chip are mounted on the package substrate in a stacked structure.