Patent ID: 6115443
Filing Date: 2000-09-05
Classification: G06G,H03L

Abstract:
A programmable frequency following device capable of generating an output frequency which is a user-programmable multiple of an input frequency, which comprises:a frequency divider for dividing the input frequency by a predetermined divisor;a frequency counter for counting the output frequency of the programmable frequency following device, the frequency counter being reset to 0 after reaching a cycle time of the output frequency from the frequency divider;a programmable frequency comparator for comparing the output count from the frequency counter with a user-programmable reference value at the time before the frequency counter is reset to 0 in such a manner that if the output count is greater than the reference value, the programmable frequency comparator generates an up-trigger signal; if the output count is less than the reference value, the programmable frequency comparator generates a down-trigger signal;if the output count is equal to the reference value, the programmable frequency comparator generates a lock signal;an up-down counter which is capable of increasing its count in response to the up-trigger signal from the programmable frequency comparator, decreasing its count in response to the down-trigger signal from the programmable frequency comparator, and locking its count at current value in response to the lock signal from the programmable frequency comparator; anda DCO whose output frequency is inversely proportional to the output count from the up-down counter, and whose output frequency serves as the output frequency of the programmable frequency following device.