Patent ID: 7120891
Filing Date: 2006-10-10
Classification: G06F,H01L,H03K

Abstract:
1. A master slice semiconductor integrated circuit, comprising: at least two wiring layers for wiring; and a plurality of clock buffers connected by clock wirings in a form of a clock tree having at least two cascaded stages to distribute clock signals to a plurality of sequential circuits; wherein each of said clock wirings among said plurality of clock buffers comprises a wiring layer switching portion which switches a clock wiring from a lower wiring layer of said at least two wiring layers to an upper wiring layer of said at least two wiring layers and then switches said clock wiring from said upper wiring layer to said lower wiring layer; wherein said wiring layer switching portion comprises: wherein said upper wiring layer is a wiring layer for customized wirings, and said lower wiring layer is a wiring layer for fixed wirings.