Patent ID: 6684302
Filing Date: 2004-01-27
Classification: G06F

Abstract:
Data processing apparatus comprising:(i) a memory circuit; (ii) a data bus coupled to said memory circuit; (iii) a plurality of bus master circuits coupled to said data bus for issuing memory access requests to said memory circuit via said data bus; (iv) a bus arbitration circuit for controlling in accordance with a hierarchy of bus master priorities which bus master is granted priority in gaining use of said data bus when more two or more bus masters issue temporally overlapping memory access requests; wherein (v) said bus arbitration circuit is responsive to a determination of latency of pending memory access requests calculated in dependence upon a current state of said memory circuit to re-arbitrate priority in gaining use of said data bus between bus masters such that a first bus master circuit having a first pending memory access request and a lower position in said hierarchy than a second bus master circuit having a second pending memory access request may gain use of said data bus ahead of said second bus master circuit if said first memory access request has a lower latency than said second memory access request.