Patent ID: 8846449
Filing Date: 2014-09-30
Classification: H01L

Abstract:
1. A three-dimensional integrated circuit including a first semiconductor chip and a second semiconductor chip that are layered on each other, wherein each of the first and second semiconductor chips includes a load layer and a plurality of wiring layers that are layered on each other, at least one of the first and second semiconductor chips includes an insulation layer for insulating the first and second semiconductor chips from each other at an interface therebetween, each of (i) a wiring layer closest to the interface among the wiring layers of the first semiconductor chip and (ii) a wiring layer closest to the interface among the wiring layers of the second semiconductor chip includes a power conductor area and a ground conductor area, a layout of the power conductor area and the ground conductor area in the wiring layer of the first semiconductor chip is the same as a layout of the power conductor area and the ground conductor area in the wiring layer of the second semiconductor chip, and the power conductor area in the wiring layer of the first semiconductor chip at least partially faces the ground conductor area in the wiring layer of the second semiconductor chip with the insulation layer therebetween.