Patent ID: 6144077
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A semiconductor device comprising:a first conductivity type semiconductor substrate;a second conductivity type collector region formed up to a position of a first depth from a major surface of said semiconductor substrate;a first conductivity type base region formed up to a position of a second depth, being smaller than said first depth, from said major surface of said semiconductor substrate; andan emitter region provided with a first impurity layer having a second conductivity type impurity concentration peak on a position of a third depth, being smaller than said second depth, from said major surface of said semiconductor substrate and a second impurity layer having a second conductivity type impurity concentration peak on a position between said second and third depths and being formed to be enclosed with said first impurity layer, wherein said base region is formed by a source/drain region of a MOS transistor.