Patent ID: 6490672
Filing Date: 2002-12-03
Classification: G06F

Abstract:
In a system for computing a fast Fourier transform having a data memory for storing data values and a coefficient memory for storing coefficient values, a circuit for addressing the data memory comprising:a multiplexer having an output for addressing the data memory, a first input of the multiplexer defining a data memory read address and a second input of the multiplexer defining a data memory write address; a write FIFO disposed in communication with the second input of the multiplexer, the write FIFO having an input that is connected to the first input of the multiplexer; a pointer register that is configured to contain and output an address value for the data memory; a control circuit that is configured to load a value into the pointer register; a second multiplexer having an output that is in communication with an input of the pointer register, the second multiplexer having a first input that is in communication with the control circuit; and a modulo adder having an output that is disposed in communication with a second input of the second multiplexer.