Patent ID: 6023177
Filing Date: 2000-02-08
Classification: G11C

Abstract:
A semiconductor memory device for providing a burst mode control signal, the semiconductor device comprising:a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal;a plurality of transition registers for respectively changing said driving signal in synchronization with a first edge of a clock signal to generate changed driving signals; anda second logic circuit for generating said burst mode control signal generated by a logical combination of said changed driving signals in response to an externally input read latency control signal, where the second logic circuit activates the burst mode control signal in a first cycle of the clock signal responsive to a first logic level of the read latency control signal and activates the burst mode control signal in a second cycle of the clock signal responsive to a second logic level of the read latency control signal; anda third logic circuit for providing a reset signal which initializes said plurality of transition registers when said write and read control signal is changed to the first logic level and said chip enable signal is changed to a second logic level.