Patent ID: 6175526
Filing Date: 2001-01-16
Classification: G11C

Abstract:
A trap and delay pulse generator for a synchronous dynamic random access memory (SDRAM) comprising:an input stage for receiving a externally generated signal triggered off of a high speed clock pulse;a delay path coupled to the input stage for receiving and delaying the externally generated signal;an enable circuit coupled to the delay path for receiving and passing through the externally generated signal when the SDRAM performs a READ function;a latch circuit having a delay element coupled to the enable circuit for receiving, latching and delaying the externally generated signal provided by the enable circuit, wherein delay of the externally generated signal ensures the SDRAM has developed signal levels for a READ function before initiation of the READ function; anda one-shot pulse generator coupled to the latch for receiving the latched externally generated signal and generating an output pulse for initiation of the READ function.