Patent ID: 8937309
Filing Date: 2015-01-20
Classification: H01L

Abstract:
1. A semiconductor die assembly, comprising: a base semiconductor die having conductive elements protruding from a surface; a single stack of semiconductor dice of common lateral dimensions and of lesser lateral dimensions than lateral dimensions of the base semiconductor die on an opposing surface of the base semiconductor die, an uppermost die of the single stack having an active surface facing the base semiconductor die and having no conductive through vias; at least partially exposed ends of conductive through vias on the surface of the base semiconductor die; conductive elements aligned with conductive through vias of semiconductor dice of the assembly vertically connecting all of the semiconductor dice of the assembly, aligned with and the at least partially exposed conductive through via ends on the surface of the base semiconductor die and operably coupling semiconductor dice of the single stack to the base semiconductor die; a non-conductive material located around the conductive elements and between adjacent semiconductor dice of the assembly and substantially filling spaces between adjacent semiconductor dice of the assembly, between a lowermost semiconductor die of the single stack and the base semiconductor die and extending to a lateral periphery of the single stack of semiconductor dice; an encapsulant material different from the non-conductive material extending peripherally about the semiconductor dice of common lateral dimensions, in physical contact with the opposing surface of the base semiconductor die and in only peripheral physical contact with the semiconductor dice of the single stack and with the non-conductive material; a carrier substrate comprising external connections on a surface; one of a logic die and a system on a chip die mounted to an opposing surface of the carrier substrate, operably coupled to the external connections of the carrier substrate, and to the base semiconductor die through the conductive elements protruding therefrom; and another encapsulant material in physical contact with an uppermost surface of the uppermost semiconductor die of the single stack, in physical contact with sides of the encapsulant material and sides of the base semiconductor die, a portion of an opposing surface of the base semiconductor die, sides of the one of the logic die and the system on a chip die, and a portion of the opposing surface of the carrier substrate surrounding the one of the logic die and the system on a chip die.