Patent ID: 6562671
Filing Date: 2003-05-13
Classification: G02F,H01L

Abstract:
A method of manufacturing a semiconductor device comprising:laminating a semiconductor layer, a gate insulating film, a first layer gate electrode film, and a second layer gate electrode film over a transparent insulating substrate in order from a side near the transparent insulating substrate; forming a resist pattern for gate electrode formation over the substrate with the laminated structure; performing dry etching using the resist pattern as a mask to form a first shaped gate electrode comprising a first layer gate electrode and a second layer gate electrode; ion-implanting an impurity of one conductivity type to form a first impurity region in the semiconductor layer corresponding to an outside of the first shaped gate electrode; performing additional etching using the resist pattern present on the first shaped gate electrode as a mask to form a second shaped gate electrode in which the first layer gate electrode has a longer size in a channel direction than the second layer gate electrode; performing rear surface exposure using the first layer gate electrode of the second shaped gate electrode as a mask to form a negative resist pattern in a self alignment; ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a second impurity region in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the second shaped gate electrode; removing the negative resist pattern; and ion-implanting an impurity of a conductivity type identical to the one conductivity type to form a third impurity region in the semiconductor layer corresponding to an outside of the second shaped gate electrode.