Patent ID: 7785940
Filing Date: 2010-08-31
Classification: G02F,H01L

Abstract:
1. A method of fabricating a TFT array substrate comprising: forming a gate line, a gate electrode, a common electrode and a pad electrode on a substrate; sequentially depositing a gate insulation layer, a silicon layer and a metal layer on an entire surface of the substrate including the gate line; forming an open area in the pad electrode; forming a semiconductor layer, data line and source/drain electrodes by patterning the silicon layer and the metal layer; forming a pixel electrode connected with the drain electrode and a transparent conductive layer connected with the pad electrode by depositing and patterning a transparent conductive material on the substrate including the data line, and simultaneously defining a channel region by separating the source and drain electrodes from each other, and forming a passivation layer over the substrate, wherein an O wherein the gate and data lines are formed substantially perpendicular to one another to define a sub-pixel, wherein the gate insulation layer in the open area of the sub-pixel is removed to expose the common electrode when forming the open area in the pad electrode, before forming the pixel electrode, wherein the passivation layer is removed from the open area of the sub-pixel and pad electrode, whereby the pixel electrode and the transparent conductive layer are exposed to an outside.