Patent ID: 8463589
Filing Date: 2013-06-11
Classification: G06F

Abstract:
1. A method of transforming a transformable virtual processor model to a user virtual processor model to simulate a user target processor, the method comprising: receiving a transformable virtual processor model, the transformable virtual processor model configured to perform, on a host processor system, a behavior and timing accurate simulation of a seed target processor, the transformable virtual processor model having a transformable instruction set and a transformable pipeline; receiving one or more user-provided descriptions of the user target processor, wherein the one or more user-provided descriptions includes a description of a new instruction, including a description of an opcode pattern for a decoder part of the user virtual processor model to select the new instruction, a description of behavior for a functionality of the new instruction, and a description of timing of the new instruction; and transforming the received transformable virtual processor model to the user virtual processor model, wherein the user virtual processor model is configured to perform, on the host processor system, a behavior and timing accurate simulation of the user target processor according to the user-provided descriptions by performing at least one of: