Patent ID: 7979861
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A multi-processor system with a plurality of unit processors, comprising: an interrupt priority setting section that accepts an interrupt request output from a peripheral device and that sets priority to the interrupt request in accordance with details of the interrupt request; a to-be-allocated unit processor setting section that sets a first interrupt request which is executable on any of the plurality of unit processors, or a second interrupt request which is executable on a specified unit processor out of the plurality of unit processors, to the interrupt request output from the interrupt priority setting section; a first interrupt request priority judging section that determines whether any of the plurality of unit processors are in HALT, and if none of the plurality of unit processors are in HALT, compares a priority of the first interrupt request and a priority of an interrupt request currently being executed on all the unit processors, and that judges whether the first interrupt request has a higher priority than the interrupt currently being executed on any of the plurality of unit processors; a second interrupt request priority judging section that compares a priority of the second interrupt request and a priority of an interrupt request currently being executed on the specified unit processor, and that judges whether the second interrupt request has a higher priority than the interrupt request currently being executed on the specified unit processor; and a unit processor selecting section that selects a unit processor to which the first interrupt request is allocated based on the judgment of the first interrupt priority judging section, or selects a unit processor to which the second interrupt request is allocated based on the judgment of the second interrupt request priority judging section.