Patent ID: 7313212
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. A shift register which is an n-th shift register of a shift register chain, the n-th shift register comprising: a first multiplexer, wherein the first multiplexer selects and outputs one of output data of an (n−1)-th shift register or output data of an (n+1)-th shift register in response to a direction control signal; a second multiplexer, wherein the second multiplexer selects and outputs one of the output data of the (n−1)-th shift register or the output data of the (n+1)-th shift register in response to the direction control signal; and a latch block, wherein the latch block stores output data of the second multiplexer in response to a clock signal, a reset signal and output data of the first multiplexer, and outputs the stored data, and wherein n is a positive integer.