Patent ID: 6023568
Filing Date: 2000-02-08
Classification: G06F

Abstract:
A model of a digital circuit, said model in a memory of a data processing system, the digital circuit having a first latch, a second latch and a third latch, a first clock pin of said first latch, a second clock pin of said second latch, a third clock pin of said third latch, and a clock signal driving said first clock pin, said second clock pin, and said third clock pin, said model comprising:a model clock signal;a first model latch representing said first latch of said digital circuit and said second latch of said digital circuit;a first model clock pin of said first model latch driven by said model clock signal;a second model latch representing said third latch of said digital circuit; anda second model clock pin of said second model latch driven by said model clock signal.