Patent ID: 6404363
Filing Date: 2002-06-11
Classification: G11B,H03L,H04L

Abstract:
A digital clock recovery circuit for recovering a system clock signal locked to a received analog signal, comprising:an analog-to-digital (A/D) converter and asymmetry corrector which converts the received analog signal into digital data, and provides corrected digital data that is corrected by a binarization level wherein the binarization level traces a center value of the received analog signal; a frequency error detector which detects a frequency error from the corrected digital data; a phase error detector which detects a phase error from the corrected digital data; a digital low pass filter (LPF) which provides a control voltage using the frequency error and the phase error; and a clock generator which generates the system clock signal whose frequency and phase are varied according to the control voltage, and provides the system clock signal as driving clock signals for the asymmetry corrector, the frequency error detector, the phase error detector, and the digital LPF.