Patent ID: 6332181
Filing Date: 2001-12-18
Classification: G06F

Abstract:
A method of handling a cache error in a computer system, comprising the steps of:constructing an interrupt service for suspending current operations of a processor of the computer system upon the occurrence of a defined condition other than a cache error, said constructing step including the step of defining a data storage interrupt service having an associated data storage interrupt handler;detecting an error in a cache associated with the processor;reporting the error to the processor using the interrupt service, said reporting step including the steps of generating a data storage interrupt, and using a data storage interrupt status register to indicate that the data storage interrupt is a result of the error; andin response to said data storage interrupt, synchronizing a context of said processor, wherein said synchronization is comprises:halting instruction dispatching;completing instructions already in execution in the processor in respective categories in which the instructions were initiated, to a point at which the instructions have reported any exceptions they will cause; and have already completed execution, and no instruction subsequent to the next-to-complete instruction has begun execution.