Patent ID: 6600360
Filing Date: 2003-07-29
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a main circuit including a plurality of areas, each of the areas including at least one MOS transistor; a substrate bias controlling circuit used for controlling a substrate bias voltage to be applied to a well of said MOS transistor of each of the areas; a standby controlling circuit used for switching a state of said semiconductor integrated circuit between at least two states of active and standby by controlling said substrate bias controlling circuit, said active state allowing a first subthreshold leakage current to flow in said main circuit and said standby state allowing a second subthreshold leakage current less than the first subthreshold leakage current to flow in said main circuit; and a plurality of substrate driving MOS transistors used for driving the substrate bias voltage in the active state, a source-drain path of each substrate driving MOS transistor being between a source and a well of said MOS transistor of each of the areas and a gate potential of said substrate driving MOS transistors being controlled by said substrate bias controlling circuit; wherein the substrate bias voltage is shallowly controlled in the active state and the substrate bias voltage is deeply controlled in the standby state, the substrate bias voltage in the active state is applied through the source-drain paths of said substrate driving MOS transistors and the substrate bias voltage in the standby state is applied from said substrate bias controlling circuit.