Patent ID: 6175907
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A microprocessor for calculating a square root of an operand, the microprocessor having a plurality of square root instructions, each of which specifies a square root calculation precision, the square root calculation precision specifying the number of significand bits to be provided in the square root, the microprocessor comprising:translation logic, configured to receive the plurality of square root instructions, and to provide a plurality of prescribed-precision machine instructions, said plurality of prescribed-precision machine instructions directing the microprocessor to calculate no more than the number of significand bits according to the square root calculation precision specified by the plurality of square root instructions; andexecution logic, coupled to said translation logic, configured to receive said plurality of prescribed-precision machine instructions, and configured to calculate the number of significand bits for the square root of the operand according to the square root calculation precision;wherein at least one of the plurality of square root instructions specifies the square root calculation precision such that less significand bits are calculated in the square root than are provided in the operand.