Patent ID: 6472706
Filing Date: 2002-10-29
Classification: H01L

Abstract:
A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) comprising, in said substrate, a source region (6), a drain region (7) and a channel region (10) between said source (6) and drain (7) regions, and comprising, on top of said substrate, a floating gate (9) separated from said channel region (10) by a floating gate insulating layer, a select gate (11) disposed above said floating gate and separated from said channel region by a select gate insulating layer (8), and a control gate (5) separated from said floating gate (9) by a control gate insulating layer, wherein said control gate (5) is produced as a sidewall spacer and said floating gate is a non-conducting charge trapping dielectic layer (9), and wherein the non-volatile memory cell has a surface area less than or equal to 4F2.