Patent ID: 7999571
Filing Date: 2011-08-16
Classification: G05B,G11C

Abstract:
1. An integrated circuit including a non-Flash non-volatile state machine, comprising: a silicon semiconductor substrate including circuitry fabricated in a logic plane of the silicon semiconductor substrate, the circuitry including at least one memory plane in direct contact with and fabricated directly above the silicon semiconductor substrate, the at least one memory plane including wherein the non-volatile re-writable memory Includes at least one two-terminal cross-point array, each two-terminal cross-point array Including a plurality of first conductive array lines, a plurality of second conductive array lines arranged orthogonally to the plurality of first conductive array lines, and a plurality of the two-terminal resistivity-sensitive memory elements, each two-terminal resistivity-sensitive memory element is positioned between a cross-point of a unique pair of first and second conductive array lines and is electrically in series with Its respective pair of first and second conductive array lines, and wherein each two-terminal resistivity-sensitive memory element is electrically coupled with the select array through Its respective pair of first and second conductive array lines.