Patent ID: 6297086
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A process of fabricating a trench capacitor semiconductor memory structure comprising the steps of:(a) providing an intermediate trench capacitor structure comprising a trench storage capacitor formed within a semiconductor substrate or wafer and a patterned gate region formed on said substrate or wafer, wherein said trench storage capacitor comprises at least a lower region having a temperature sensitive material situated between a bottom electrode and a top electrode and a doped polysilicon region formed on said top electrode;(b) forming source/drain regions in said semiconductor substrate or wafer in areas adjacent to said patterned gate region;(c) annealing the structure of step (b) using an excimer laser under conditions effective to activate the source/drain regions without substantially degrading the temperature sensitive material in said lower region of said storage capacitor and to cause substantial outdiffusion of dopant from said doped polysilicon region thereby forming a strap outdiffusion region in said substrate adjacent to said trench storage capacitor;(d) forming an insulating layer over said structure of step (c);(e) planarizing said insulating layer; and(f) forming borderless diffusion contacts on said semiconductor substrate or wafer.