Patent ID: 8041930
Filing Date: 2011-10-18
Classification: G06F

Abstract:
1. A data processing apparatus, comprising: processing logic operable to perform data processing operations; a register bank operable to store data associated with the processing logic, the register bank having at least one register group, each register group comprising a plurality of register sets; the processing logic having an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic, said single execution thread associated with said second operating state requiring more architectural state than is required for any independent execution thread associated with said first operating state; and control logic operable to control how the register sets of each register group are used dependent on the operating state associated with that register group, wherein each register group comprises a pair of register sets, wherein in the second operating state the processing logic is selectively operable in either a secure domain or a non-secure domain and a first register set of the associated pair of register sets contains a first subset of registers that are used when operating in the secure domain or the non-secure domain and a second subset of registers that are only used when operating in one of the secure or non-secure domains, wherein, when the processing logic is operating in the other one of the secure or the non-secure domains that does not use said second subset of registers, a number of registers in a second register set of that associated pair of register sets are used instead of the second subset of registers.