Patent ID: 7005347
Filing Date: 2006-02-28
Classification: H01L,Y10S

Abstract:
1. A process of fabricating an MIS device, the device comprising an active region and a termination region, comprising: forming a trench mask over the surface of a semiconductor substrate, the substrate being doped with a material of a first conductivity type, the trench mask having an aperture defining the location of a termination trench to be formed; etching through the aperture in the trench mask to form a termination trench in the substrate; removing the trench mask; forming a first nonconductive layer on a wall of the termination trench; depositing a layer of a conductive gate material into the termination trench, the conductive gate material overflowing the surface of the substrate outside the termination trench; etching the gate material without a mask such that a top surface of the gate material in the termination trench is reduced to a level below the surface of the substrate; depositing a second nonconductive layer over the surface of the substrate; forming a contact mask over the second nonconductive layer, the contact mask having a gate contact aperture; etching the second nonconductive layer through the gate contact aperture in the contact mask to form a gate contact aperture in the second nonconductive layer; removing the contact mask; and depositing a second conductive layer over the second nonconductive layer, the second conductive layer extending through the gate contact aperture to make contact with the conductive gate material in the termination trench wherein said process does not include a mask for etching a portion of an oxide layer to form a field oxide region in the termination region.