Patent ID: 6349401
Filing Date: 2002-02-19
Classification: G06F,H01L

Abstract:
A semiconductor integrated circuit comprising:components formed in a semiconductor substrate; a plurality of interlayer dielectric films and a plurality, of interconnection layers, said interlayer dielectric films and said interconnection layers being formed in alternating manner over said semiconductor substrate; and plugging members of a conductive material which are filled in a plurality of connecting windows each including at least one connecting hole formed through said interlayer dielectric film; wherein: said plugging member provides interconnection between interconnection lines which belong in different interconnection layers or interconnection between an interconnection line which belongs in an interconnection layer and a component; and the total opening area of each said connecting window and the plane form of each said interconnection line are set such that each of zones, of a permissible current ratio, said zones resulting from division according to a specific parameter including at least one of: an electric current direction, an electric current waveform, an interconnection line material, a plugging member material, an interconnection line length, an interconnection line width, an interconnection line area, an interconnection line, capacity, an interconnection line thickness, and an overlap margin at an interconnection line-plugging member interface, has a common total connecting window opening area and a common interconnection line plane.