Patent ID: 6051466
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A method of making a semiconductor memory device having a plurality of memory cells disposed in a matrix of rows and columns, said method comprising the steps of:forming a field shield element isolation structure on a surface of a semiconductor substrate of a first conductivity type so as to define a plurality of element regions electrically isolated from one another;forming two gate electrode wirings serving as word lines extending parallelly in a column direction in one of said element regions on the surface of said semiconductor substrate with a gate insulating film interposed between each of said gate electrode wirings and said substrate such that the surface of said substrate is exposed at a first region between said two gate electrode wirings and at a pair of second regions between each of said two gate electrode wirings and a portion of said element isolation structure for defining said one of said element regions;covering an upper surface of each of said gate electrode wirings with a cap insulating film and side surfaces of each of said gate electrodes with sidewall insulating films, and forming a polycrystalline silicon film doped with an impurity of a second conductivity type different from said first conductivity type on an entire surface of said substrate;patterning said polycrystalline silicon film to form at least a first pad polycrystalline silicon film being in contact with the surface of said substrate at said first region, and forming a pair of second pad polycrystalline silicon films at said second regions, respectively, being in contact with the surface of said substrate at the pair of said second regions, respectively, each of said second pad polycrystalline silicon films being formed into a shape having an extension portion extending on an upper surface of the portion of said element isolation structure adjacent to one of said second regions;forming an interlayer insulating film over the entire surface of said substrate;diffusing impurities of said second conductivity type from said first pad polycrystalline silicon film and said pair of said second pad polycrystalline silicon films into portions of the surface of said substrate exposed at said first region and the pair of said second regions thereby forming a first impurity diffusion layer and a pair of second impurity diffusion layers, respectively;forming a bit line extending in the row direction on said interlayer insulating film so as to pass immediately above said first pad polycrystalline silicon film, and connecting said bit line to said first pad polycrystalline silicon film through a first opening formed in said interlayer insulating film;covering an upper surface of said bit line by a cap insulating film and side surfaces of said bit line with sidewall insulating films;forming a pair of second openings reaching the respective extension portions of the pair of said second pad polycrystalline silicon films, respectively, through said interlayer insulating film, and forming a lower electrode of a capacitor connected to each of said second pad polycrystalline films through one of said second openings and extending over said cap insulating film formed on said bit line;forming a capacitor insulating film on said lower electrode of said capacitor; andforming an upper electrode of said capacitor facing said lower electrode on said capacitor insulating film.