Patent ID: 6781859
Filing Date: 2004-08-24
Classification: G06F,G11C

Abstract:
A computer comprising:a printed circuit board; a memory controller mounted on said printed circuit board; a bus switch mounted on said printed circuit board; a first data bus connecting said memory controller and said bus switch; a plurality of memory devices including at least a first and a second memory device mounted on said printed circuit board; and a second data bus connecting said bus switch to said first memory device and a third data bus connecting said bus switch to said second memory device, wherein said bus switch is configured to couple said first data bus to said second data bus during memory accesses directed to said first memory device, and wherein said bus switch is configured to couple said first data bus to said third data bus during memory accesses directed to said second memory device, wherein the bus switch is operated so as to control the parasitic capacitance on at least the second and third data busses.