Patent ID: 6255172
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method of manufacturing an electrically erasable non-volatile memory, suitable for use on a substrate, comprising the steps of:forming a tunnel oxide layer on the substrate;forming a first conductive layer and a silicon oxide/silicon nitride/silicon oxide layer in order on the tunnel oxide layer;patterning the silicon oxide/silicon nitride/silicon oxide layer and the first conductive layer in order, the residual conductive layer serving as a floating gate;forming a first oxide layer on the sidewalls of the floating gate;forming a silicon nitride spacer on the sidewalls of the first oxide layer;forming a second oxide layer above the substrate;performing an oxidation reaction to form a third oxide layer on the substrate on both sides of the silicon nitride layer;forming a patterned second conductive layer thereby to form a control gate and a select transistor gate which are electrically coupled to each other, wherein the control gate is located on the second oxide layer above the floating gate, and the select transistor gate is located on the third oxide layer on both sides of the floating gate;removing the exposed part of the third oxide layer to thereby form a gate oxide under the select transistor gate; andperforming ion implantation on the substrate to form source/drain regions in the substrate on both sides of the gate oxide layer.