Patent ID: 6512406
Filing Date: 2003-01-28
Classification: H03K

Abstract:
An apparatus, comprising:a latch circuit having an input of a first inverter coupled to an output of a second inverter at a first node, and, an input of said second inverter coupled to an output of said first inverter at a second node, said latch circuit at a first stable state when said first node is at a first voltage and said second node is at second voltage, said latch circuit at a second stable state when said first node is at said second voltage and said second node is at said first voltage, said latch circuit having a metastable state that is approached as said first and said second nodes approach a third voltage between said first and second voltages, said first and second inverters each having a transistor with a back gate bias node that receives a back gate bias voltage, said back gate bias voltage provided by a logic circuit in response to an input applied to said latch circuit, wherein said back gate bias voltage increases the gain of said transistors so as to avoid said metastable state as a result of said input being applied to said latch circuit, said input being a data signal value and a clock signal value that could have been transitioned to such that the transition to said data signal value was sufficiently proximate to the transition to said clock signal value so as to cause said metastable state, said latch circuit designed to latch a value of said data signal on a said clock signal transition.