Patent ID: 7684258
Filing Date: 2010-03-23
Classification: G11C

Abstract:
1. A semiconductor memory, comprising: a memory cell array having memory cells, and a word line and a bit line connected to the memory cells; an address input circuit that sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal; and a data input/output circuit that inputs/outputs data via a data terminal and masks at least either of write data to said memory cells and read data from said memory cells in accordance with logic of said first data mask signal, wherein said address input circuit receives a portion of bits of said first address signal and remaining bits of said first address signal in synchronization with adjacent transition edges of said clock signal, and receives said second address signal and said first data mask signal in synchronization with adjacent transition edges of said clock signal.