Patent ID: 6987411
Filing Date: 2006-01-17
Classification: G06F,H03K,H04L

Abstract:
1. A clock controlling circuit comprising: a first timing averaging circuit for receiving two clocks from a certain position on a forward route of a first clock propagation path, and from a position on a return route corresponding to said position on said forward route, and for outputting a first signal with a delay time corresponding to a time obtained on division of a timing difference of said two clocks into two equal portions, respectively; a second clock propagation path for receiving at one end said first signal output from said first timing averaging circuit and direction-reversing the first signal; and a second timing averaging circuit for receiving two clocks, including a first clock from a certain first position on a forward route of said second clock propagation path, and a second clock from a second position on a return route corresponding to the first position on said forward route, and for outputting a second signal with a delay time corresponding to a time obtained on division of a timing difference of said two clocks into two equal portions.