Patent ID: 6649457
Filing Date: 2003-11-18
Classification: H01L,Y10S

Abstract:
A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer having a layer of top silicon formed thereon, comprising:growing a gate oxide layer on the top silicon layer; depositing a first layer of material on the gate oxide layer; removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region; forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer, including growing a layer of oxide by thermal oxidation about the first layer of material, the oxide layer and the top silicon layer; depositing a layer of oxide by CVD over the structure; and etching the oxide to the level of the first layer of material, leaving a sidewall; depositing a second layer of material over the first layer of material and the insulating cup; etching the first layer of material and the second layer of material to form a gate electrode; implanting ions to form a source region and a drain region; passivating the structure; and metallizing the structure.