Patent ID: 7834660
Filing Date: 2010-11-16
Classification: G05B,G11C

Abstract:
1. An integrated circuit (IC) comprising: a logic plane fabricated on a semiconductor substrate, the logic plane including memory logic; a first memory plane in contact with and fabricated directly above the semiconductor substrate, the first memory plane is positioned above the logic plane and is electrically connected with the memory logic, the first memory plane including a non-volatile memory, the non-volatile memory including a plurality of two-terminal resistivity-sensitive memory elements operative to implement a next state logic of a state machine, each two-terminal resistivity-sensitive memory element including an electrolytic tunnel barrier in contact with a mixed valence conductive oxide that includes mobile oxygen ions and is operative to store non-volatile data as a plurality of conductivity profiles, a state register electrically connected with the non-volatile memory and operative to store a state of the state machine in the plurality of two-terminal resistivity-sensitive memory elements; and a second memory plane positioned above the logic plane and electrically connected with the memory logic, the second memory plane including a second non-volatile memory, the second non-volatile memory also including another plurality of the two-terminal resistivity-sensitive memory elements operative to implement an output logic of the state machine.