Patent ID: 6200839
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of forming a transistor device, comprising:forming a gate over a first semiconductive material to define a channel region within the first semiconductive material, the gate having a pair of opposing sidewall edges;forming at least one electrically conductive sidewall spacer over at least one of the sidewall edges of the gate, the providing the spacer comprising:providing an amorphous second semiconductive material layer over the gate;anisotropically etching the second semiconductive material layer to form opposing sidewall spacers laterally adjacent the gate; andconverting the amorphous layer to polycrystalline form after deposition of the amorphous layer; andafter providing the sidewall spacer, subjecting the first semiconductive material to conductivity doping effective to form an electrically conductive source region and an electrically conductive drain region proximate the channel region.