Patent ID: 7388275
Filing Date: 2008-06-17
Classification: H01L

Abstract:
1. An electronic package, comprising: a conductive trace layer having a first side and a second side, the conductive trace layer being patterned to define a plurality of interconnect pads; a dielectric substrate mounted on the first side of the conductive trace layer; a capacitor including a first conductive layer, a second conductive layer and a layer of dielectric material disposed between the first and the second conductive layers, the first conductive layer mounted adjacent to the second side of the conductive trace layer; a plurality of interconnect regions extending through the first conductive layer and the dielectric material layer of the capacitor; an interconnect member connected between each of the conductive layers of the capacitor and a corresponding set of the interconnect pads, the first conductive layer of the capacitor being electrically connected to a first set of the interconnect pads and the second conductive layer of the capacitor being electrically connected to a second set of the interconnect pads, the interconnect members corresponding to the second set of interconnect pads extending through one of the interconnect regions; an electrically conductive stiffening member mounted adjacent to the second conductive layer of the capacitor; and a device receiving region extending through the dielectric substrate, the conductive trace layer and the capacitor, and further comprising an electronic device mounted in the device receiving region on the stiffening member; wherein the electronic device includes a plurality of bonding pads, and further comprises a first wire electrically connected between a first one of the bonding pads and the first conductive layer of the capacitor, and a second wire electrically connected between a second one of the bonding pads and the second conductive layer of the capacitor.