Patent ID: 6093588
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A process for the fabrication of a high-voltage MOSFET transistor on a layer of monocrystaline silicon which comprises the operations of:forming a first region and a second region of the same conductivity type functioning, respectively, as source region and drain region separated by a region of opposite conductivity which includes a channel zone delimited by the front surface of the silicon layer, the second region forming with this region of opposite conductivity a junction delimited by the said front surface;forming in the said second region a doped region delimited by the front surface;forming a relatively thick insulating element of silicon dioxide on the front surface of the silicon layer between the channel zone and the doped region;forming a relatively thin layer of silicon dioxide on the front surface over the channel zone functioning as gate dielectric;forming a layer of electroconductive material over the relatively thin layer of silicon dioxide and over the relatively thick insulating element of silicon dioxide, functioning as gate electrode and field electrode for the said junction;forming electrical connection means with the first region, the doped region and the strip of electroconductive material to form, respectively, the source terminals, drain terminals and gate terminals of the transistor, characterized in that the formation of the relatively thick insulating element of silicon dioxide envisages the following operations;forming a land of relatively thick silicon dioxide over the front surface of the silicon layer;forming a layer of electroconductive material which extends at least over the land;selectively removing the layer of electroconductive material in such a way as to expose a part of the land and to obtain the said strip to form the gate electrode and field electrode; andperforming a selective anisotropic etching of the silicon dioxide of the land utilizing the layer of electroconductive material as mask to expose the front surface and in that the formation of the doped region includes the introduction of doping material into the silicon layer through the part of the front surface exposed with the said selective anisotropic etching.