Patent ID: 8456922
Filing Date: 2013-06-04
Classification: G11C

Abstract:
1. A method for erasing selected memory cells in a flash memory device comprising: biasing a p-well connected to a plurality of floating gate memory cell transistors to a positive well bias voltage; biasing a selected main word line to a negative word line voltage and biasing a plurality of unselected main word lines to a positive word line voltage; and selecting a plurality of word line drivers connected to respective main word lines to pass the negative word line voltage on the selected main word line to at least one selected local word line connected to gate terminals of selected ones of the floating gate memory cell transistors, and to pass the positive word line voltage on the unselected main word lines to a plurality of unselected local word lines connected to gate terminals of unselected ones of the floating gate memory cell transistors, wherein the difference between the positive well bias voltage and the negative word line voltage is sufficient to erase the selected memory cells.