Patent ID: 8446191
Filing Date: 2013-05-21
Classification: H03L

Abstract:
1. A phase locked loop (PLL) device comprising: a digital to analog converter (DAC) configured to receive a digital input signal and configured to generate an analog current signal based on the digital input signal, the DAC comprising a current source output stage for providing the analog current signal; an analog integrator coupled to the DAC and configured to integrate the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO) to generate an analog output signal; a digital differentiator coupled to the DAC and configured to output the digital input signal as a result of differentiating a digital loop signal from control circuitry to at least partially compensate for the integration of the analog current signal by the analog integrator; a phase accumulator responsive to the VCO and configured to generate an integer phase signal based on the analog output signal; a time to digital converter (TDC) responsive to the VCO and configured to generate a digital fractional phase signal based on the analog output signal; and a feedback path coupled to the VCO and configured to provide a feedback signal to the control circuitry, the feedback signal based on a combination of the integer phase signal and the digital fractional phase signal.