Patent ID: 6829173
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines arranged in the direction of rows; a plurality of bit lines arranged in the direction of columns; a plurality of memory cells arranged in the row direction and in the column direction and each having at least one storage area for storing data therein; and a write circuit for writing multiple data into said plurality of memory cells, said plurality of memory cells arranged in said row direction being connected in series and having respective gates connected to a word line placed in said row direction, said plurality of bit lines being connected correspondingly to said plurality of memory cells, said plurality of memory cells each for storing one of at least three values of the data according to the amount of charge held in said storage area, and said write circuit including a bit line selection circuit for selecting a plurality of bit lines connected to memory cells to be written, and a potential supply circuit for supplying a plurality of predetermined potentials according to a combination of said multiple data to said plurality of selected bit lines, said potential supply circuit for supplying a predetermined first potential to bit lines included in said plurality of selected bit lines and connected to respective drains of said memory cells to be written, and supplying a predetermined second potential determined according to the combination of said multiple data to bit lines included in said plurality of selected bit lines and connected to respective sources of said memory cells to be written.