Patent ID: 6249150
Filing Date: 2001-06-19
Classification: G06F,H03K,H03L

Abstract:
A clock signal generator circuit provided with an inverting delaying means for inverting and delaying a main clock signal externally given to generate an AND logic signal of said main clock signal and an inverted delay signal thereof, for generating a sub-clock signal which transfers from a first level to a second level in synchronization with a transfer of said main clock signal from said first level to said second level and also transfers from said second level to said first level in synchronization with another transfer of said main clock signal from said second level to said first level,wherein a holding means is provided for holding said main clock signal, after transferred from said first level, at said second level for at least a time more than a delay time by said inverted delay means, andwherein said holding means is provided with a reset means for transferring said inverted delay signal outputted from said inverting delaying means from said second level to said first level for compulsory returning to an initial state.