Patent ID: 6118305
Filing Date: 2000-09-12
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising a plurality of logic circuits, each of said logic circuits having both at least a first field effect transistor with a first gate connected to a first constant voltage line applied with a ground potential and at least a second field effect transistor with a second gate connected to a second constant voltage line applied with a positive voltage potential;wherein said first gates of at least two of said plurality of logic circuits are commonly connected through a first interconnection structure to a first resistor which is connected to said first constant voltage line;wherein said second gates of at least two of said plurality of logic circuits are also commonly connected through a second interconnection structure to a second resistor which is connected to said second constant voltage line;wherein the first resistor comprises:a first p-type well disposed within an n-type semiconductor substrate;a first n-type well disposed within the first p-type well;a second p-type well disposed within the first p-type well so that the second p-type well is separated from the first n-type well, the second p-type well having an impurity concentration higher than an impurity concentration of the first p-type well; andfirst, second, and third electrodes, the first and third electrodes being electrically connected to the first n-type well, the second electrode being electrically connected to the second p-type well, the first and third electrodes being electrically connected to the first constant voltage line, the second electrode being electrically connected to the first interconnection structure, so that a predetermined electrical resistance is provided between the first constant voltage and the first interconnection structure;wherein a diode is formed between the first p-type well and the first n-type well, the first n-type well acting as a cathode and the first p-type well acting as an anode of the diode;wherein the second resistor comprises:a second n-type well disposed with a p-type semiconductor substrate;a third p-type well disposed within the second n-type well;a third n-type well disposed within the second n-type well so that the third n-type well is separated from the third p-type well, the third n-type well having an impurity concentration higher than an impurity concentration; of the second n-type well; andfourth, fifth, and sixth electrodes, the fourth and sixth electrodes being electrically connected to the third p-type well, the fifth electrode being electrically connected to the third n-type well, the fourth and sixth electrodes being electrically connected to the second constant voltage line, the fifth electrode being electrically connected to the second interconnection structurewherein a diode is formed between the second n-type well and the third p-type well, the second n-type well acting as a cathode and the third p-type well acting as an anode of the diode.