Patent ID: 8890146
Filing Date: 2014-11-18
Classification: G02F,G09G,H01L

Abstract:
1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; and a fourth transistor, wherein a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring, wherein a gate of the second transistor is electrically connected to a third wiring, a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to a gate of the first transistor, wherein a gate of the third transistor is electrically connected to a fourth wiring, a first terminal of the third transistor is electrically connected to a fifth wiring, and a second terminal of the third transistor is electrically connected to the second wiring, wherein a gate of the fourth transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the fifth wiring, and a second terminal of the fourth transistor is electrically connected to the gate of the first transistor, wherein a channel width of the first transistor is larger than a channel width of the second transistor, and wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region.