Patent ID: 6871266
Filing Date: 2005-03-22
Classification: G06F

Abstract:
1. A method of operating a cache memory arranged between a processor and a main memory of a computer, wherein, when the processer requests an item from main memory using an address in main memory for said item and that item is not held in the cache memory, said item is fetched from the main memory and loaded into one of a plurality of addressable storage locations in the cache memory, the addressable storage locations being arranged as a set of cache partitions and wherein each address includes a multi-bit partition selector identifying into which cache partition the item may be loaded so that one of said cache partitions is allocated to said item in dependence on the address of said item in main memory, said partition selector defining a number of cache partitions into which the cache is divisible, wherein the number of cache partitions is alterable during operation of the cache.