Patent ID: 6218235
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a memory device formation region and a logic device formation region on a semiconductor substrate, comprising the steps of:forming first and second gate electrodes on said semiconductor substrate in said memory device formation region and forming a third gate electrode on said semiconductor substrate in said logic device formation region;forming first source/drain regions in said semiconductor substrate on both sides of said first and second gate electrodes and forming second source/drain regions in said semiconductor substrate on both sides of said third gate electrode;forming a first insulating film on an entire surface of said semiconductor substrate to cover said first, second and third gate electrodes;performing anisotropic etching on said first insulating film formed in said logic device formation region to leave a first protection insulating film covering said first and second gate electrodes in said memory device formation region, and forming a sidewall insulating film on a side wall of said third gate electrode;forming a second insulating film to cover said entire surface of said semiconductor substrate including said first, second and third gate electrodes, said protection insulating film, and sidewall insulating film;selectively performing wet etching on said second insulating film in said memory device region to form a salicide protection film in said logic device formation region;forming a refractory metal silicide film on said second source/drain region exposing said semiconductor substrate in said logic device formation region;forming an interlayer insulating film to cover said entire surface of said semiconductor substrate; andetching said interlayer insulating film and said first protection insulating film in said memory device formation region to form a contact hole leading to said first source/drain region of said semiconductor substrate in a self-aligning manner such that a second protection insulating film is left on upper surfaces and side walls of said first and second gate electrodes.