Patent ID: 7217581
Filing Date: 2007-05-15
Classification: G03F,H01L

Abstract:
1. A method of determining process misalignment during manufacturing of an integrated circuit having a first conductive layer, the method comprising: patterning the first conductive layer to form a first finger-shaped structure and a second finger-shaped structure; forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer; patterning the second conductive layer to form a third finger-shaped structure and a fourth finger-shaped structure respectively partially overlapping the first finger-shaped structure in a first direction and the second finger-shaped structure in a second direction by a predetermined overlap width (W), the first direction being opposite to the second direction; measuring an electrical characteristic across the first conductive layer and the second conductive layer to determine whether the second conductive layer is shifted during a patterning process.