Patent ID: 7840781
Filing Date: 2010-11-23
Classification: G06F

Abstract:
1. A circuit arrangement for profiling a target system, comprising: a first uni-directional, point-to-point bus having a single input port and a single output port; a first target processor having a trace port coupled to the input port of the first bus, wherein the first target processor is configured to execute a plurality of instructions one or more times, and to provide state data of the first target processor at the trace port and to the input port of the first bus; a second uni-directional, point-to-point bus having a single input port and a single output port, wherein the input port of the second bus is coupled to the trace port of the first processor; a profile circuit arrangement coupled to the output port of the first bus; and a memory coupled to the profile circuit arrangement, wherein the memory includes first and second memories having respective data and address ports; and wherein the profile circuit arrangement includes first and second profile core circuits respectively coupled to the output ports of the first and second buses, and respectively coupled to the first and second memories, each of the first and second profile circuits configured to read data from the respective first and second buses on different clock cycles and write the data to the respective memories.