Patent ID: 6518110
Filing Date: 2003-02-11
Classification: G11C,H01L

Abstract:
A method of fabricating a memory cell of a flash memory device comprising the steps of:(a) establishing a substrate formed of a semicondcutor material; (b) forming a layered structure on a surface of said substrate, said layered structure including an SiN layer overlaying a pad oxide layer; (c) forming in said substrate at least a pair of field oxide portions spaced one from the other; (d) selectively etching said layered structure to define pad oxide portion and an SiN portion extending between said field oxide portions; (e) forming on said substrate about said SiN portion a gate oxide layer; (f) forming over said gate oxide layer a first poly-silicon layer; (g) selectively etching said first poly-silicon layer to define a substantially annular floating gate disposed about said SiN portion; (h) removing said SiN and pad oxide portions to expose a portion of said substrate surface; (i) forming over said floating gate and said exposed portion of said substrate surface a first oxide film; (j) forming over said first oxide film an SiN film; (k) partially removing said SiN film to define an injection point over said floating gate; (l) forming a second poly-silicon layer to extend over at least a portion of said SiN film and said first oxide film; (m) etching said second poly-silicon layer to define a control gate extending over said injection point; (n) forming by ion implantation in said substrate source and drain regions; and, (o) forming a conductive contact window coupled to said drain.