Patent ID: 7478224
Filing Date: 2009-01-13
Classification: G06F

Abstract:
1. A microprocessor for executing byte-compiled stack machine code as hardware, the microprocessor comprising: a processor core with an associated processor control unit configurable to execute a first set of stack machine instructions in the processor core when in a stack machine state and to execute both native instructions and a second set of stack machine instructions as native microcode in the processor core when in a native processor state, the processor control unit responsive to processor state control information contained in a system status register that designates the processor state at any given time; a register file in a data path of the processor core and including a plurality of register elements, the register file accessible by the processor control unit by means of register addresses specified by either stack machine or native microcode instructions; a stack machine operand stack pointer register that contains information pointing to a register element in the register file which is the current top of a stack machine operand stack; and a register remap unit for each register access port of the register file and coupled to the processor control unit to receive instruction-specified register addresses therefrom and coupled to the register access ports to supply physical address values of register elements in the register file therefore such that whenever a remap bit in the system status register is set, the physical address value supplied by the register remap unit is a specified maximum value of the operand stack pointer register minus a current register number value contained in the operand stack pointer register.