Patent ID: 7024498
Filing Date: 2006-04-04
Classification: H04L

Abstract:
1. An apparatus for receiving a packet, which includes a plurality of data units, the apparatus comprising: an inspection logic circuit for accumulatively computing an error checking value based on a redundancy bit included in each of the plurality of data units by analyzing each of the plurality of data units of the packet as soon as each of the plurality of data units separately arrives at the inspection logic circuit and generating control signals, which are an error-off signal and an error-on signal, according to comparison of the accumulatively computed error checking value and a cyclic redundancy check CRC calculated at a transmitter included in the packet when the last data unit of the packet arrives; a multiplexer for receiving data units and distributing the received data units as soon as the data units separately arrive at the multiplexer; and a plurality of first in and first out FIFO memories for receiving each of the plurality of data units from the multiplexer, storing each of the plurality of data units in corresponding FIFO memories and deleting or completing storing data units of a corresponding packet according to the control signals from the inspection logic circuit.