Patent ID: 6465310
Filing Date: 2002-10-15
Classification: H01L

Abstract:
A method for forming a self aligned contact pad in a semiconductor device comprising:forming a plurality of spaced apart gate electrode structures on a semiconductor substrate, wherein each of said gate electrode structures comprises a gate electrode layer, a gate capping layer thereon and a gate sidewall spacer; forming an insulating layer over said substrate and on said gate electrode structures to completely fill spaces between said gate electrode structures; using a contact pad formation mask and etching said insulating layer to form a plurality of openings exposing simultaneously a plurality of contact regions of said substrate; filling said openings with a conductive material that has an etching selectivity with respect to said gate capping layer; etching back said conductive material and said insulating layer until a top surface of said gate capping layer is exposed and forming a plurality of contact pads to be electrically connected to said corresponding contact regions of said substrate and electrically isolated from each other; and wherein said etching back is carried out on said gate capping layer to have an etching selectivity with respect to said conductive material at the end of said etching back process.