Patent ID: 7176730
Filing Date: 2007-02-13
Classification: H03L

Abstract:
1. An adjustment system for adjusting a phase/frequency detecting device in a phase locked loop, the phase/frequency detecting device comparing a target clock signal which is generated from the phase locked loop with a predetermined reference clock signal, and outputting a set of control signals to further control the target clock signal to synchronize with the reference clock signal, the set of control signals comprising a first control signal and a second control signal, the adjustment system comprising: a) a reset module comprising: b) a switch module for counting the first reset signal and the second reset signal outputted by the reset module, and switching the phase/frequency detecting device between a normal mode and a glitch protection mode when a predetermined switch condition is met; wherein, when the phase/frequency detecting device is under the glitch protection mode, and the predetermined reset condition set by the reset module is met, the reset module outputs the first reset signal and the second reset signal and then resets the phase/frequency detecting device.