Patent ID: 6828827
Filing Date: 2004-12-07
Classification: G11C,H03K

Abstract:
A complementary input dynamic logic circuit for evaluating a complex logic function, comprising:a plurality of complementary input dynamic logic circuits, each for determining a complementary AND function for a corresponding one of a plurality of sets of AND terms and for indicating said complementary AND function via a corresponding one of a plurality of preliminary evaluation nodes; a plurality of P-channel devices coupled in series between a source voltage and an output evaluation node, each having a gate coupled to a corresponding one of said plurality of preliminary evaluation nodes; an inverter/driver having an input receiving a clock signal and an output providing and inverted clock signal; and a plurality of N-channel pass devices, coupled in parallel between said output evaluation node and said inverter/driver, each having a gate coupled to a corresponding one of said plurality of preliminary evaluation nodes.