Patent ID: 7979642
Filing Date: 2011-07-12
Classification: G06F

Abstract:
1. A data processing apparatus comprising: processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread; at least one storage unit shared between the multiple program threads and comprising multiple entries, each entry for storing a storage item for reference by the processing circuitry when executing said program threads, each storage item being either a high priority storage item associated with said at least one high priority program thread or a lower priority storage item associated with said at least one lower priority program thread; history storage for retaining a history field for each of a plurality of blocks of the storage unit, each block comprising one or more of said entries; and control circuitry for, on detection of an evicted high priority storage item being evicted from an entry of the storage unit as a result of allocation to that entry of an allocated lower priority storage item, populating the history field for the block containing that entry with an indication of the evicted high priority storage item, and the control circuitry being further for performing, when an allocated high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry, and on detection of a match condition said control circuitry setting a lock indication associated with said selected entry to inhibit further eviction of said allocated high priority storage item.