Patent ID: 7304513
Filing Date: 2007-12-04
Classification: H03K

Abstract:
1. A programmable frequency divider comprising: a clock-preprocessor circuit for processing an input clock and blocking one cycle in a case of odd frequency division; a divide-by-two circuit coupled to an output of the clock-pre-processor circuit, the divide-by-two circuit dividing an input frequency to half its value; a plurality of bit-cells connected in series, the clock of a first of the bit-cells being coupled to an output of the divide-by-two circuit; a logic detection circuit that receives an input from each of the bit-cells and from the divide-by-two circuit; a first synchronizing element coupled to an output of the logic detection circuit, the first synchronizing element generating a synchronized divider output; an additional synchronizing element coupled to the output of the logic detection circuit, the additional synchronizing element receiving its clock from the output of the divide-by-two circuit and generating a special synchronized load output; and a plurality of combinational logic blocks that receive the load output and generate load signals for the bit-cells for detecting the state of all stages.