Patent ID: 6069044
Filing Date: 2000-05-30
Classification: H01L

Abstract:
A method for fabricating an ultra-short channel transistor in a semiconductor substrate with self-aligned silicide contact, said method comprising the steps of:forming a gate oxide layer on said substrate;forming a first silicon layer over said gate oxide layer;forming a first dielectric layer over said first silicon layer;forming a photoresist layer over said first dielectric layer;patterning said photoresist layer to define a gate region;performing an etching process to said photoresist layer to narrow a size of said gate region;etching portions of said first dielectric layer by using a residual photoresist layer as a mask;etching said first silicon layer by using said residual photoresist layer and said residual first dielectric layer as a mask;removing said residual photoresist layer;forming a second dielectric layer over said residual first dielectric layer and said substrate;etching said second dielectric layer to form side-wall spacers to serve as an ion diffusion source;removing said residual first dielectric layer;forming a metal layer on the surface of said side-wall spacers, said residual first silicon layer, and said substrate;performing an ion implantation through said substrate to form first doped regions to serve as source and drain regions of said transistor; andperforming a first thermal annealing to form metal silicide layer on the surface of said substrate and on the top surface of said residual first silicon layer.