Patent ID: 8006165
Filing Date: 2011-08-23
Classification: G06F,G11C

Abstract:
1. A memory controller which is connectable to a memory and controls the memory, comprising: a buffer to which data, which is to be transferred to the memory, is input; an ECC parity generating unit which generates an ECC parity in units of a predetermined data length from the data which is to be transferred to the memory; and a memory interface which adds the generated ECC parity in units of the predetermined data length, and delivers the data with the ECC parity to the memory, wherein when a data length of the data which is to be transferred to the memory is less than the predetermined data length, the ECC parity generating unit regards data of a part that is short of the predetermined data length as “0”, and generates the ECC parity from the data of less than the predetermined data length, wherein the ECC parity generating unit generates a parity from inverted data which is obtained by inverting the data of less than the predetermined data length, and delivers an inverted parity, which is obtained by inverting the generated parity, to the memory interface, and the memory interface adds the inverted parity to at least the data of less than the predetermined data length, and delivers the data with the inverted parity to the memory.