Patent ID: 6128247
Filing Date: 2000-10-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array including a plurality of memory cells, each memory cell being connected to a word line and a data line so as to write or read data;a row decoder for decoding row address data for designating a word line so as to write or read data to or from a target memory cell, connected to the designated word line, in the memory cell array;a column decoder for decoding column address data for designating a data line so as to select the data line to which the target memory cell is connected;a sense amplifier for amplifying a signal which transmits the data read out from the target memory cell; anda column decoder control section for outputting an operation enabling signal for making the column decoder operable to the column decoder, andwherein when the data is read out, the column decoder control section determines the output timing of the operation enabling signal according to a determination of whether a sufficient RAS (row address strobe) access time is obtained, where the RAS access time is the period from the falling time of the RAS, a control signal for determining the timing of confirming the row address data, to the time when the data is output from the target memory cell.