Patent ID: 6034389
Filing Date: 2000-03-07
Classification: H01L,Y10S

Abstract:
A 4F-square memory device comprising:a substrate;an array of cells having pillars formed on said substrate, said pillars being arranged in rows and columns, each of said pillars extending upward and having an upper region doped with a first type of impurity, a middle region doped with a second type of impurity, and a lower region doped with said first type of impurity, said middle region being between said upper and lower regions, being continuous with said substrate and being of the same dopant concentration and material as said substrate;a gate region formed on at least one sidewall of said each pillar over said middle region to control the resistance between said upper and lower regions; anda trench capacitor formed around each of said pillars in trenches separating said pillars, said trenches being arranged in rows and columns, each of said trench capacitors having a storage electrode, a dielectric layer lining said trenches, and a plate electrode formed in said trenches over said dielectric layer, wherein said lower region acts as said storage electrode of said trench capacitor.