Patent ID: 8429580
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A method comprising: providing a reference integrated circuit (IC) design version including a reference logic block having control logic and datapath logic; creating a plurality of modified IC design versions, each including a modified logic block that corresponds to the reference logic block and that includes one or more modifications relative to the reference logic block, wherein the one or more modifications increase in computational complexity from one version to a next version; decomposing the reference logic block and each of the modified logic blocks into a datapath logic block and a control logic block; and performing by a processor, verifying sequential equivalence of logic between each modified IC design version and a next modified IC design version having a greater modification computational complexity, beginning with the reference IC design version and a first modified IC design version having a least modification computational complexity; wherein the modified logic block within each IC design version is at a same level of hierarchy as the modified logic block in the next IC design version.