Patent ID: 6080652
Filing Date: 2000-06-27
Classification: H01L,Y10S

Abstract:
A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of:a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring;b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer;c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on said relationship and said measuremental result;d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having said desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a second region on said another semiconductor substrate, where an isolated wiring is to be formed as an upper level wiring;e) forming an interlayer insulating layer with a planarizing function to cover said lower level wirings; andf) forming an upper level wirings on said interlayer insulating layer in said first and second regions.