Patent ID: 7432753
Filing Date: 2008-10-07
Classification: H03K

Abstract:
1. A delay circuit comprising: a common delay circuit having an input terminal and an output terminal; N input-side circuits (N is an integer greater than or equal to 2), each of which includes an input buffer having first and second input terminals and first and second output terminals and includes a switching circuit having an input terminal, an output terminal and a control terminal, in which the first output terminal of the input buffer is coupled to the input terminal of the switching circuit, the second output terminal of the input buffer is coupled to the control terminal of the switching circuit, and the output terminal of the switching circuit is coupled to the input terminal of said common delay circuit; and N output-side circuits, each of which includes a switching circuit having an input terminal coupled to the output terminal of said common delay circuit, an output terminal, and a control terminal coupled to the second output terminal of the input buffer, and includes an output buffer having an input terminal coupled to the output terminal of the switching circuit and having an output terminal coupled to the second input terminal of the input buffer, wherein a transmission signal is input from outside to the first input terminal of the first input buffer, and the output terminals of the first to (N-1) -th output buffers are coupled respectively to the second input terminals of the first to (N-1) -th input buffers and to the first input terminals of the second to N-th input buffers.