Patent ID: 6342423
Filing Date: 2002-01-29
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:(a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of said substrate, said layer stack comprising: i. a thin gate insulating layer in contact with said substrate surface; and ii. a gate electrode layer formed on said gate insulating layer, said layer stack comprising a pair of opposing side surfaces and a top surface; (b) forming insulative, tapered sidewall spacers of on each of said pair of opposing side surfaces, said insulative spacers comprising a material which is readily etched in its as-deposited, undensified state but difficult-to-etch in its annealed, densified state; (c) selectively introducing dopant impurities of a second, opposite conductivity type into exposed portions of said substrate surface adjacent said sidewall spacers to form a pair of spaced-apart, heavily-doped regions in said substrate; (d) removing the as-deposited, undensified sidewall spacers by etching; (e) treating said pair of spaced-apart heavily-doped regions to form a pair of heavily-doped source/drain junction regions in said substrate at a predetermined depth below said substrate surface, each of said heavily-doped source/drain junction regions being laterally spaced from a respective proximal edge of said gate insulating layer by a distance substantially equal to the width of the lower ends of said sidewall spacers; (f) selectively introducing second, opposite conductivity type dopant impurities into exposed portions of said substrates surface intermediate said gate insulating layer and said heavily-doped source/drain junction regions to form lightly- or moderately-doped extension regions; and (g) treating said lightly- or moderately-doped source/drain extension regions to form a pair of shallow-depth, lightly- or moderately-doped source/drain extensions in said substrate, each of said shallow-depth, lightly- or moderately-doped source/ drain extension extending from a proximal edge of a respective source/drain junction region to beneath a respective proximal edge of said gate insulating layer.