Patent ID: 8431995
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. A method of forming a Field Effect Transistor (FET) device, the method comprising: forming a layer of silicon on a buried oxide layer of a substrate, the layer of silicon including a p-type doped region and an n-type doped region; forming a gate stack on a portion of the p-type doped region, the gate stack having sidewalls and a top surface; forming a native oxide layer over the n-type doped region, the sidewalls and the top surface of the gate stack, and exposed portions of the p-type doped region; forming a dielectric layer over the native oxide layer on the sidewalls and top surface of the gate stack; patterning a photoresist over the n-type doped region and a portion of the spacer material arranged over a portion of the gate stack; etching to remove an exposed portion of the native oxide layer and a portion of the p-type doped region to form a first recess partially defined by the p-type doped region adjacent the gate stack, the first recess having sidewalls and a bottom surface through a portion of the silicon containing region, wherein the etching is performed at a pressure greater than or equal to 10 mT, a bias power of 0 W, and a source power less than or equal to 1 kW; passivating the bottom surface of the first recess to form a passivating layer; etching a sidewall of the first recess in the silicon containing region for a predetermined lateral distance underneath the native oxide layer; removing the passivating layer in the first recess; and etching the bottom surface of the first recess to a target vertical etch depth.