Patent ID: 7038291
Filing Date: 2006-05-02
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate; a memory cell having a first channel and a first gate insulating film formed on the semiconductor substrate, the first gate insulating film comprising multiple layer films including a charge storage layer; first shallow trench isolation regions formed in trenches provided in the semiconductor substrate, the memory cell being sandwiched between the first shallow trench isolation regions; a transistor having a second channel and a second gate insulating film formed on the semiconductor substrate; and second shallow trench isolation regions formed in trenches provided in the semiconductor substrate, the transistor being sandwiched between the second shallow trench isolation regions; wherein the first shallow trench isolation regions have first concave portions on upper ends thereof; wherein the second shallow trench isolation regions have second concave portions on upper ends thereof; wherein an entire extent of the first concave portions are formed above the charge storage layer, wherein a film thickness of the first gate insulating film at a central portion of the first channel and at portions contacting with the first shallow trench isolation regions are equal, wherein a film thickness of the second gate insulating film at a central portion of the second channel and at portions contacting with the second shallow trench isolation regions are equal, and wherein heights, from a surface of the semiconductor substrate, of upper surfaces of the first shallow trench isolation regions are higher than heights, from the surface of the semiconductor substrate, of upper surfaces of the second shallow trench isolation regions.