Patent ID: 6818980
Filing Date: 2004-11-16
Classification: H01L

Abstract:
An integrated circuit package comprising:a substrate having conductive traces therein, the substrate including a cavity therein; a first semiconductor die mounted in a die-down configuration to a first surface of said substrate such that said first semiconductor die spans said cavity; a second semiconductor die mounted to a backside of said first semiconductor die; a first plurality of wire bonds electrically connecting said first semiconductor die to portions of said conductive traces of said substrate; a second plurality of wire bonds connecting said second semiconductor die to other portions of said conductive traces of said substrate; an encapsulant encapsulating said second plurality of wire bonds and covering at least a portion of said first surface of said substrate and said second semiconductor die; a ball grid array disposed on a second surface of said substrate, bumps of said ball grid array being connected with said conductive traces; a second encapsulant, encapsulating said first plurality of wire bonds; and a dummy silicon die disposed on said second semiconductor die.