Patent ID: 6356218
Filing Date: 2002-03-12
Classification: H03M

Abstract:
A direct-current (DC) offset nullification circuit comprising:a summing circuit connected to receive an input signal and a DC offset compensation signal, the summing circuit generating an output signal corresponding to a sum of the received input signal and the DC offset compensation signal; an integrator circuit configured to receive the output signal from the summing circuit; a reference voltage source; a comparator connected to an output of the integrator circuit and to the reference voltage source, the comparator generating a binary output based on a comparison of a signal from the integrator circuit and the reference voltage source; and a circuit connected to supply the DC offset compensation signal to the summing circuit, the circuit increasing or decreasing the supplied DC offset compensation signal based on the binary output of the comparator; wherein the reference voltage is used to judge whether the output of the integrator circuit is positive or negative.