Patent ID: 6809971
Filing Date: 2004-10-26
Classification: G11C

Abstract:
In a memory component including a dummy cell with a dummy bit line and a plurality of wordlines, the memory component having a memory component capacitance and memory component operational characteristics, including dummy bitline capacitance of the dummy bitline, a method of implementing a diffusion replica delay circuit comprising:a. coupling a diffusion replica capacitor to the dummy bit line and one wordline of the plurality of wordlines, coupling the diffusion replica capacitor to the memory component, storing in the diffusion replica capacitor a predetermined replica charge representative of the dummy bitline capacitance, and matching the diffusion replica capacitance of the diffusion replica capacitor to the dummy bitline capacitance, and b. coupling a diffusion replica transistor with the diffusion replica capacitor, and coupling the diffusion replica transistor between the diffusion replica capacitor and a charge sink, the transistor being disposed to control the magnitude of the predetermined replica charge.