Patent ID: 7983086
Filing Date: 2011-07-19
Classification: G11C

Abstract:
1. A NAND flash memory using a programming scheme programming a memory cell transistor from a source line side, the NAND flash memory comprising: a first selection gate transistor comprising a first end connected to the source line; a second selection gate transistor comprising a first end connected to a bit line; and a plurality of memory cell transistors connected in series between a second end of the first selection gate transistor and a second end of the second selection gate transistor, data being able to be programmed into each of the memory cell transistors by applying a voltage to a control gate thereof, controlling a charge quantity of a floating gate thereof, and changing a threshold voltage, and in an erase state each of the memory cell transistors being set equal to a first threshold voltage being the lowest threshold voltage, wherein at time of programming operation using the programming scheme, in a state in which the first selection gate transistor and the second selection gate transistor are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to the source line side of a first memory cell transistor selected from among the plurality of the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the plurality of the memory cell transistors to turn on the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage applied the third voltage to a control gate of the first memory cell transistor.