Patent ID: 6297112
Filing Date: 2001-10-02
Classification: H01L,Y10S

Abstract:
A method of forming a MOS transistor that is used as a PMOS transistor or an NMOS transistor on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate and a gate positioned on the silicon substrate, the method comprising:performing a first deposition process to form a protection layer of uniform thickness of silicon nitride on the semiconductor wafer to cover the surface of the gate;performing a second deposition process to form a silicon oxide layer of uniform thickness on the protection layer;performing a first ion implantation process to form a first ion implantation layer with a first predetermined thickness around the gate on the silicon substrate;performing an RCA cleaning process to remove impurities on the semiconductor wafer;forming a spacer positioned around the gate; andperforming a second ion implantation process to form a second ion implantation layer with a second predetermined thickness around the gate on the silicon substrate, the second ion implantation layer being used as a source or drain (S/D) of the MOS transistor;wherein the protection layer is used both to prevent dopants in the first ion implantation layer from diffusing into the silicon oxide layer so as to prevent a decrease in the concentration of the ions in the first ion implantation layer, and to prevent oxygen ions in the silicon oxide layer from diffusing into the first implantation layer or the second ion implantation layer during the first and the second ion implantation processes.