Patent ID: 8410835
Filing Date: 2013-04-02
Classification: H03L

Abstract:
1. A leakage tolerant phase locked loop (PLL) circuit device, the PLL circuit device comprising: a primary loop configured to generate a feedback signal having a phase that substantially matches a phase of a reference signal, wherein the primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and a feedback divider, wherein the VCO is configured to generate a VCO output signal; the feedback divider configured to generate the feedback signal based on the VCO output signal, wherein the phase detector is configured to generate one of a first error-frequency-increase signal and a first error-frequency-decrease signal based on a determination of the phase difference between the feedback signal and the reference signal; a secondary correction circuit configured to generate a secondary error-frequency signal wherein the secondary correction circuit includes an error generator; and a secondary correction circuit divider that is configured to generate a divided VCO output signal based on the VCO output signal, wherein the error generator is configured to generate the secondary error-frequency signal in response to detecting a particular edge of the divided VCO output signal, wherein the primary loop is configured to control, based on at least one of the first error-frequency-increase signal, the first error-frequency-decrease signal, and the secondary error-frequency signal, a frequency adjustment provided by the VCO to the VCO output signal.