Patent ID: 6187620
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A method for forming an integrated circuit, comprising:forming first and second gate conductors dielectrically spaced above a semiconductor substrate;forming spacers laterally adjacent sidewalls of the first and second gate conductors;reducing a lateral width of each of the spacers to form residual spacers adjacent sidewalls of the first and second gate conductors;implanting a p-type impurity distribution into the semiconductor substrate on either side of the second gate conductor to form p-type junction regions; andimplanting multiple n-type impurity distributions into the semiconductor substrate on either side of the first gate conductor to form graded n-type junction regions, wherein said n-type junction regions comprise more implanted impurity distributions than do said p-type junction regions and wherein the last n-type impurity distribution into the semiconductor substrate is masked by the first gate conductor absent any spacers.