Patent ID: 8788550
Filing Date: 2014-07-22
Classification: G06F,H03K

Abstract:
1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB's) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising: a K-input look-up table (LUT) (“K-LUT”), the K-LUT arranged to receive the plurality of binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two stages of the plurality of stages of the arithmetic combination of the plurality of binary input signals; an input line network including a network of input lines, the network of input lines arranged to receive a plurality of representative input signals from the PLD routing architecture that represent the plurality of binary input signals and to provide the plurality of binary input signals to the K-LUT, the input line network being configured to provide at least a first one of the plurality of binary input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal, which differs from the first carry-in signal, to the second K-LUT portion in a second state; and an output line network including a network of output lines, the network of output lines arranged to receive, from the K-LUT, output signals that represent the binary result signals and to provide the network of output signals to the PLD routing architecture.