Patent ID: 6080206
Filing Date: 2000-06-27
Classification: G06F

Abstract:
A method of laying out interconnections employed in an LSI logic circuit having a pluralitu of logic elements within a preset regiion of an LSI chip, the plurality of logic elements being respectively activated in synchronism with at least one predetermined signal through one or more drive elements, said method comprising:dividing the region into a plurality of subregions;setting, within the individual subregions, the number of drive elements to be interposed between an input position of the signal to the respective subregions and a transfer position of the signal to the logic elements within the region;setting drive elements, for sypplying the predetermined signal between the subregions, by grouping the subregions based on the number of driving elements in the respective subregions wherein said drive elements are set between subregions with the same number of driving elements or between subregions with the closest number of driving elements;wiring between the drive elements, which are operable to supply the at least one predetermined signal, using predetermined wiring regions; andsetting wiring between the drive elements set in the subregions using the layout of the respective drive elements in the individual subregions and the set wiring regions.