Patent ID: 6711075
Filing Date: 2004-03-23
Classification: G11C

Abstract:
A semiconductor chip comprising:a memory circuit including a memory matrix; and a test circuit inputting a signal for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal of a semiconductor chip, and outputting a response signal for responding to this input signal, and judging electric connection/non-connection between a needle connected to said test apparatus at said burn-in and a terminal of said semiconductor chip, wherein said test circuit is comprised of a test clock terminal for inputting a test clock signal, a first and second test control terminals for inputting a test control signal, a test input/output terminal for inputting and outputting test input/output data, a first power terminal supplying with a first power supply voltage, and a second power terminal supplying with a second power supply voltage, and wherein said test circuit synchronizes the test clock signal being input from said test clock terminal to be controlled in accordance with a combination of the test control signals being input from said first and second test control terminals, and has a shift register for shifting test command data being input from said test input/output terminal and a decoder for decoding data of this shift register, such that operation of a test mode is initiated in accordance with a current status flag and a concurrent status flag being output from said decoder.