Patent ID: 6774488
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A memory device with low leakage and low contact resistance plugs, comprising:a silicon substrate; multiple transistors formed on the silicon substrate, a gate of each of the transistors protruding out of the silicon substrate, having a multiple layer structure, and being surrounded by a spacer layer, with concave contacts being formed between adjacent gates, wherein each concave contact has two opposite sidewalls and a bottom where a joint is defined between the concave contact and the silicon substrate; and multiple double layer plugs each of which has a height, is filled with one of the concave contact and is composed of an outer polysilicon layer, a middle barrier layer and an inner tungsten layer, wherein the outer polysilicon layer is formed on the two opposite side walls and the bottom to form a polysilicon concave notch having inner sides with a thin film formed on each inner side as the middle barrier layer, and then the polysilicon concave notch is filled with the inner tungsten layer; wherein the height of each double layer plug is equal to that of the transistor gate.