Patent ID: 8122303
Filing Date: 2012-02-21
Classification: G06F

Abstract:
1. A data structure applied for a first sector and a second sector which are two neighboring sectors in a block of a flash memory, said data structure comprising: a first data area, located at said first sector, for storing a first data; a second data area, located at said second sector, for storing a second data; a first spare area, located at said first sector, for storing a first logic block address information and a first redundant code; and a second spare area, located at said second sector, for storing a second logic block address information and a second redundant code; wherein, said first logic block address information and said second logic block address information are concatenated to form a logic block address of said block, and said first redundant code and said second redundant code are derived respectively from said first data and said second data encoded with a 6-bit error correcting code (ECC) scheme.