Patent ID: 6501110
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory cell comprising;(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type, (2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and (3) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions, the semiconductor memory cell having; (a) a semi-conductive first region having a second conductivity type, (b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type, (c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region, (d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type, (e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and (f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region and is shared by the first and second transistors, wherein: (A-1) one source/drain region of the first transistor is formed of a surface region of the second region, (A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region, (A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region, (B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor, (B-2) the other source/drain region of the second transistor is formed of the third region, (B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor, (C-1) the gate portions of the junction-field-effect transistor are formed of the fifth region and a portion of the first region which portion is opposed to the fifth region, (C-2) the channel region of the junction-field-effect transistor is formed of a portion of the fourth region which portion is interposed between the fifth region and said portion of the first region, (C-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the fourth region which surface region extends from one end of the channel region of the junction-field-effect transistor and forms the other source/drain region of the first transistor, (C-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the fourth region which portion extends from the other end of the channel region of the junction-field-effect transistor, (D) the gate region is connected to a first line for memory cell selection, (E) the third region is connected to a write-in information setting line, (F) the fourth region is connected to a second line, and (G) the fifth region is connected to a third line, and further wherein: the second region and the fourth region at least in the areas thereof where the second region and the fourth region are bridged by the gate region are substantially mirror images of each other with respect to the center of the gate region, and wherein the fifth region is connected to the write-in information setting line in place of being connected to the third line.