Patent ID: 6310491
Filing Date: 2001-10-30
Classification: H03K

Abstract:
A sequential logic circuit comprising:a latch circuit having an input terminal to which an input signal is applied, an output terminal from which an output signal is derived, a set terminal to which a set signal is applied, and a reset terminal to which a reset signal is applied;said latch circuit having an active mode where a latch function is operable and a sleep mode where said latch function is inoperable, one of which is alternatively selected;said output signal being set to have a specific set state by said set signal having a specific logic level applied to said set terminal in said active mode; andsaid output signal being reset to have a specific reset state by said reset signal having a specific logic level applied to said reset terminal in said active mode;wherein said sequential logic circuit includes a means for preventing said set and reset signal from being applied to said set and reset terminal in said sleep mode, respectively, thereby avoiding loss of information latched in said latch circuit prior to transition to said sleep mode from said active mode.