Patent ID: 6449202
Filing Date: 2002-09-10
Classification: G11C

Abstract:
A direct sensing circuit for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation, comprising:a bitline precharge circuit for precharging the bitline to a bitline precharge voltage prior to the data read operation; a data line precharge circuit for precharging the data line to a data line precharge voltage prior to the data read operation; a pFET device having its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and having its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device; an nFET device having its gate coupled to the sense node to detect and amplify the signal level thereof, and having its drain coupled to the data line, such that when sensing a low data signal the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline and to pull down the precharged data line, and when sensing a high data signal, the pFET device and the nFET device remain inactivated and the data line remains at its precharge high voltage.