Patent ID: 6353257
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A semiconductor package configuration, which comprises:a lead frame having a die-pad portion and a lead portion; a semiconductor chip mounted on the die-pad portion of the lead frame; a set of bonding wires for electrically coupling the semiconductor chip to the lead frame; an encapsulation body having a centrally-hollowed portion, for encapsulating the semiconductor chip; and a lid for covering the opening of the centrally-hollowed portion of the encapsulation body; wherein the die-pad portion of the lead frame is formed with a shouldered portion at the edge thereof, while the lead portion of the lead frame is formed with a recessed portion at the point where the inner wall of the centrally-hollowed portion of the encapsulation body is located; the shoulder portion and the recessed portion being used to help prevent flash of a molding material being used in the forming of the encapsulation process during manufacture of the semiconductor package configuration.