Patent ID: 6225849
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A boost level clamping circuit for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device which is power supply and process corner independent, said clamping circuit comprising:a plurality of parallel-connected clamp stage means connected to said boosted wordline voltage from said booster circuit;said plurality of clamp stage means including at least first clamp stage means for clamping said boosted wordline voltage only when it reaches a first predetermined level, second clamp stage means for clamping said boosted wordline voltage only when it reaches a second predetermined level which is higher than said first predetermined level, and third clamp stage means for clamping said boosted wordline voltage only when it reaches a third predetermined level which is higher than said second predetermined level;each of said first, second and third clamp stage means being formed of:(a) sampling means for sampling said boosted wordline voltage;(b) comparator means for comparing a sampled voltage level of said boosted wordline voltage and a reference voltage level and for generating a low logic signal when said sampled voltage level is greater than said reference voltage level;(c) pulse generator means responsive to said low logic signal for generating a clamp pulse; and(d) pull-down means responsive to said clamp pulse for pulling down said boosted wordline voltage so as to prevent over-boosting of a wordline connected thereto.