Patent ID: 6649464
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device having a via contact and a MIM capacitor, the method comprising:forming first and second portions of a first metal layer a distance apart in trenches formed in a first interlayer insulating layer; forming a second interlayer insulating layer covering the first portion of the first metal layer in a via contact region, the second interlayer insulating layer having an opening that exposes the second portion of the first metal layer in a capacitor region; forming a dielectric layer on the exposed second portion of the first metal layer; forming a second metal layer over the dielectric layer to fill the opening in the capacitor region; after filling the opening with the second metal layer, forming a via contact hole in the second interlayer insulating layer to expose the first portion of the first metal layer; forming a third metal layer in the via contact hole; forming a third interlayer insulating layer overlying the second interlayer insulating layer, second metal layer, and the third metal layer; forming contact holes in the third interlayer insulating layer to expose the second metal layer and the third metal layer; and forming a fourth metal layer in the contact holes.