Patent ID: 6718431
Filing Date: 2004-04-06
Classification: G06F,G11C

Abstract:
A dynamic random access memory device, comprising:a dynamic memory core having a plurality of banks of memory cells arranged in rows and columns; a plurality of external connections; interface circuitry coupled to said plurality of external connections and said memory core, said interface circuitry configured to transfer data in the form of data packets on said external connections, a separate data packet capable of being transferred during each interval of a series of adjacent time intervals, said interface circuitry configured to receive row operation information and column operation information, wherein row operation information specifies one or more banks in said memory core to be opened with a row at which column operations are to occur, wherein column operation information specifies a data transfer for a particular column and an open bank in said memory core, said interface circuitry configured to perform column operations on said memory core at a particular column and open bank in response to column operation information, a data packet having a minimum size equal to a number of bits transferred in a column operation on a memory core; and wherein said memory core has a sufficient number of memory banks to sustain a transfer of data packets on said external connections in each of said series of adjacent time intervals, when a sequence of column operation information is received which specifies data transfers at any column in any open bank, any one bank having column operations at different rows separated by at least a row cycle time.