Patent ID: 8867685
Filing Date: 2014-10-21
Classification: H03L

Abstract:
1. A delay-locked loop, comprising: a first delay line; a second delay line; a first phase detector coupled to outputs of the first and second delay lines, the first phase detector including an UP output and a DOWN output; a second phase detector coupled to inverted outputs of the first and second delay lines, the second phase detector including an UP output and a DOWN output; a first charge pump coupled to the first phase detector so that the UP output of the first phase detector is coupled to a first charge pump input of the first charge pump and so that the DOWN output of the first phase detector is coupled to a second charge pump input of the first charge pump, where the first charge pump is configured to pump charge via a charge pump output of the first charge pump based on a bias condition and on levels at the first charge pump input of the first charge pump and the second charge pump input of the first charge pump; and a second charge pump coupled to the second phase detector so that the UP output of the second phase detector is coupled to a first charge pump input of the second charge pump and so that the DOWN output of the second phase detector is coupled to a second charge pump input of the second charge pump, where the second charge pump is configured to pump charge via a charge pump output of the second charge pump based on a bias condition and on levels at the first charge pump input of the second charge pump and the second charge pump input of the second charge pump.