Patent ID: 9158679
Filing Date: 2015-10-13
Classification: G06F,G11C

Abstract:
1. A memory module comprising: an address buffer; a data buffer comprising a controller interface and a memory interface, wherein the controller interface is a strobe-based interface and the memory interface is a strobe-less interface; and a plurality of dynamic random-access memory (DRAM) devices coupled to the address buffer and coupled to the data buffer via the memory interface, wherein the address buffer is configured to generate a timing reference signal based on a reference clock received at the address buffer and to forward the timing reference signal to the data buffer and to the plurality of DRAM devices for one or more transactions between the data buffer and the plurality of DRAM devices via the memory interface using the timing reference signal, wherein the data buffer is configured to communicate data to and from a memory controller on the controller interface using strobe signals and to communicate the data to and from the plurality of DRAM devices on the memory interface using the timing reference signal.