Patent ID: 7626670
Filing Date: 2009-12-01
Classification: G09G

Abstract:
1. A thin film transistor array panel, comprising: a plurality of gate lines; a plurality of data lines intersecting the gate lines; a plurality of switching elements respectively connected to the gate lines and the data lines; a plurality of pixel electrodes respectively connected to the switching elements; at least one test line disposed near end portions of the gate lines or the data lines; an insulating layer covering the gate lines, the data lines, and the switching elements, and having a plurality of first contact holes exposing the end portions of the gate lines or the data lines and a plurality of second contact holes exposing the at least one test line; at least one auxiliary test line formed on the insulating layer; and a plurality of conductive layers commonly connected to each other through the at least one auxiliary test line, wherein the conductive layers connect the at least one test line to the gate lines or the data lines via the first and the second contact holes.