Patent ID: 9023719
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A method of fabricating a memory device, comprising: forming a first gate insulating layer over a major surface of a semiconductor substrate; forming a select gate electrode over the first gate insulating layer; etching the select gate electrode to the first gate insulating layer through a mask to form an opening having sidewalls and a bottom surface, wherein the select gate electrode forms at least a portion of the sidewalls and the first gate insulating layer forms the bottom surface; forming a second gate insulating layer on the sidewalls of the opening; forming a sacrificial spacer layer over the second gate insulating layer on at least the sidewalls of the opening; etching the first gate insulating layer over the bottom surface of the opening to expose the semiconductor substrate while the sacrificial spacer layer protects the second gate insulating layer on the sidewalls of the opening; removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening; and forming a protrusion comprising a semiconductor material within the opening and contacting the semiconductor substrate, the protrusion having a top surface substantially parallel to the major surface of the substrate, a first side surface and a second side surface opposite the first side surface and the second gate insulating layer is located between the conductive select gate electrode and the first and second side surfaces of the protrusion.