Patent ID: 6384632
Filing Date: 2002-05-07
Classification: H03K

Abstract:
A buffer circuit comprising:a data input terminal to which a data signal is input; an enabling terminal to which an enabling signal is input; an output terminal from which output data are output; a first power source terminal to which high potential voltage is supplied; a second power source terminal to which low potential voltage lower than said high potential voltage is supplied; a first N-channel transistor that is connected between said output terminal and said second power source terminal; a common bulk P-channel transistors group that comprises a first, a second, a third, a fourth and a fifth transistors formed on a common bulk region, wherein the first P-channel transistor that is connected between said first power source terminal and said output terminal, the second P-channel transistor that is formed between said output terminal and one node and comprises a gate electrode connected to said first power source terminal, the third P-channel transistor that comprises a first current terminal connected to said output terminal, a second current terminal connected to a gate electrode of said first P-channel transistor, and a gate electrode connected to said first power source terminal, the fourth P-channel transistor that is formed between said first power source terminal and said gate electrode of said first P-channel transistor and comprises a gate electrode of which is supplied an inverted signal of the enabling signal, and the fifth P-channel transistor that comprises a drain electrode connected to said bulk region, a source electrode connected to said first power source terminal and a gate electrode connected to said one node; a second N-channel transistor that is formed between said one node and said second power source terminal and comprises a gate electrode supplied an inverted signal of an enabling signal; and a logic circuit that inputs an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor when status of said enabling signal is in one state, or inputs a signal keeping said first P-channel transistor turned off to the gate electrode of said first P-channel transistor when the status of said enabling signal is in another state.