Patent ID: 6650591
Filing Date: 2003-11-18
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates; and wherein the memory cell array region includes: a plurality of control gate lines formed by connecting, in the first direction, each of the control gates of the memory cells in each column arranged in the first direction; and sub-control gate lines extending in the first direction in an upper layer of the control gate lines, the number of the sub-control gate lines being half the number of the control gate lines, and wherein each two control gate lines adjacent across the boundaries between the memory cells arranged in the second direction are connected in common with one sub-control gate line.