Patent ID: 9195579
Filing Date: 2015-11-24
Classification: G06F

Abstract:
1. A memory system, comprising: a central processing unit (CPU); a nonvolatile flash memory electrically coupled in the memory system to communicate with said CPU; and a main memory configured to swap an incoming code page read from a nonvolatile non-flash memory for a target code page therein, in response to a first command issued by said CPU; wherein said main memory is configured to swap the target code page in said main memory to said nonvolatile flash memory in the event a page capacity of said main memory is at a threshold capacity; and wherein said main memory includes a page table configured to maintain refault bit values therein, which indicate for each of a plurality of code pages stored in said main memory how many times the corresponding code pages have been discarded from said main memory without being written into said nonvolatile flash memory.