Patent ID: 9183082
Filing Date: 2015-11-10
Classification: G06F,G11C

Abstract:
1. A circuit comprising: a first one-time programmable (OTP) element; a second OTP element; error detection circuitry coupled to receive a first representation of data from the first OTP element and to receive a second representation of the data from the second OTP element; and output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on the second representation of the data from the second OTP element, wherein the output of the error detection circuitry includes a first flag indicating whether any uncorrectable errors are detected in the first representation of the data and a second flag indicating whether any uncorrectable errors are detected in the second representation of the data, and wherein the output circuitry generates a selection signal having a first value when the first flag is de-asserted and having a second value when the first flag is asserted and the second flag is de-asserted.