Patent ID: 7813211
Filing Date: 2010-10-12
Classification: G11C

Abstract:
1. A semiconductor memory device having read and write operations, comprising: a number of banks, each including a plurality of memory cells; a data-group transmission line configured to transfer data inputted to the semiconductor memory device to the memory cell and transfer data outputted from the memory cells to the outside of the semiconductor memory device; and a command-group transmission line configured to transfer a command-group signal, inputted to the semiconductor memory device, to the memory cells, wherein the command-group transmission line is further configured to selectively delay the command-group signal for a predetermined write delay time in the write operation and for a predetermined read delay time in the read operation, and the write delay time is longer than the read delay time, wherein the command-group transmission line is further configured to generate a discrimination signal enabled during the write operation, increase a delay of the command-group signal when the discrimination signal is enabled, and decrease the delay of the command-group signal when the discrimination signal is disabled.