Patent ID: 6460143
Filing Date: 2002-10-01
Classification: G06F,Y02D

Abstract:
A computer system, comprising:a memory for storing at least instructions; a microprocessor for processing the instructions stored in said memory; a peripheral bus; a bus host controller for managing data transfer over said peripheral bus, said bus host controller having an operational mode and a shut-down mode, the shut-down node providing power savings; and a wakeup circuit operatively connected to said peripheral bus, said wakeup circuit operates to detect bus events on said peripheral bus when said bus host controller is in the shut-down mode and to initiate awakening of said bus host controller to the operational mode when bus events have been detected, wherein said wakeup circuit couples to first and second data lines of said USB bus, and wherein said peripheral bus is a USB bus, and wherein said bus host controller is a USB bus host controller.