Patent ID: 9100004
Filing Date: 2015-08-04
Classification: H03K

Abstract:
1. An input buffer system, comprising: first inverter stage circuitry configured to switch at a first switching speed based on a first reference current and a second switching speed based on a second reference current; wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed; second inverter stage circuitry configured to invert an output of the first inverter stage circuitry, the second inverter stage circuitry configured to switch at a third switching speed based on a third reference current and a fourth switching speed based on a fourth reference current; wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed; and hysteresis circuitry, coupled to the first inverter stage circuitry, configured to control a switch transition threshold of the input digital signal by the first inverter stage circuitry so that the Low to High switch transition threshold is greater than a High to Low switch transition threshold.