Patent ID: 7812424
Filing Date: 2010-10-12
Classification: G06F,H01L

Abstract:
1. A semiconductor chip comprising: an inner region, the inner region comprising active circuitry; a periphery region that includes no active circuitry; an inner capacitor plate disposed within the periphery region adjacent the inner region, wherein the inner capacitor plate is electrically connected to a voltage node in the active circuitry; and an outer capacitor plate disposed between the inner capacitor plate and a chip edge, wherein the outer capacitor plate is electrically connected to a different voltage node in the active circuitry, wherein the outer capacitor plate is capacitively coupled to the inner capacitor plate, wherein the outer capacitor plate and the inner capacitor plate do not overlap and are laterally separated, wherein the outer capacitor plate comprises first vias adjacent a first edge of the outer capacitor plate and second vias adjacent an opposite second edge of the outer capacitor plate, the second vias being conductively coupled to the first vias, and wherein only the first vias are capacitively coupled to the inner capacitor plate.