Patent ID: 7949916
Filing Date: 2011-05-24
Classification: G01R

Abstract:
1. Scan chain circuitry comprising a plurality of scan chain cells, each scan chain cell comprising: a register having an input and an output; a first logic circuit having an input, having an output coupled to the input of the register, and having a scan enable control input operable to receive a scan enable signal to place the plurality of scan chain cells in the scan chain circuitry in scan mode; a second logic circuit having a first input operable to receive a signal from an associated logic block, a second input operable to receive a register output signal, and a third input operable to receive a test enable signal, wherein the second logic circuit has an output that is coupled to the input of the first logic circuit; and a path operable to convey the register output signal to the second input from a register in a preceding one of the scan chain cells in the scan chain circuitry.