Patent ID: 8999810
Filing Date: 2015-04-07
Classification: H01L

Abstract:
1. A method of manufacturing a stacked package comprising the steps of: aligning saw lanes of a first wafer with saw lanes of a second wafer such that the saw lanes of the first wafer are positioned above the saw lanes of the second wafer, each of the first and second wafers having first and second microelectronic elements adjacent to and separated by a first saw lane of the saw lanes in a direction transverse to the first saw lane, each of the first and second microelectronic elements of each of the first and second wafers having at least a first trace extending therefrom towards the saw lanes; exposing at least the first traces of each of the first and second microelectronic elements of each of the first and second wafers by at least partially cutting through the aligned first saw lane of the first wafer and second wafer; and forming a lead in contact with at least the exposed first traces of each of the first and second microelectronic elements of each of the first and second wafers; and severing the first and second wafers to form first and second individual stacked packages, each of the first and second individual stacked packages including portions of each of the first and second wafers, such that a first portion of the lead is in contact with and in electrical communication with the first traces of each of the first and second wafers of the first individual stacked package and a second portion of the lead is in contact with and in electrical communication with the first traces of each of the first and second wafers of the second individual stacked package.