Patent ID: 7362636
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair and amplifies a potential difference of a memory cell formed on said bit line pair; a back bias generating circuit which generates a back bias voltage to be applied to said first NMOS transistors in a state in which a predetermined current is flowing through a second NMOS transistor having approximately the same operating characteristic as that of said first NMOS transistors, and performs a feedback control in response to a threshold voltage of said second NMOS transistor so as to decrease an absolute value of said back bias voltage as said threshold voltage increases and to increase said absolute value of said back bias voltage as said threshold voltage decreases; and control means which performs control in a sensing operation of said sense amplifier such that said pair of first NMOS transistors operates previously and after a lapse of a predetermined time said pair of first PMOS transistors operates.