Patent ID: 7876627
Filing Date: 2011-01-25
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at respective intersections of the plurality of word lines and the plurality of data lines, and a respective sense amplifier circuit connected to each of a plurality of data line pairs of the plurality of the data lines, wherein the sense amplifier circuit has a first MISFET pair, a second MISFET pair, and a third MISFET pair, the first and second MISFET pairs are of a first conduction type and the third MISFET pair is of a second conduction type which is opposite to the first conduction type, a gate of one of the first MISFET pair and one of the data line pairs, which is included in the plurality of data lines and is provided corresponding to a drain of the other of the first MISFET pair, are connected with each other, a gate of one of the second MISFET pair and a drain of the other of the second MISFET pair are connected with each other, a gate of one of the third MISFET pair and a drain of the other of the third MISFET pair are connected with each other, the first MISFET pair includes a first transistor having the first conduction type and a second transistor having the first conduction type, the drain of the first transistor is connected with the source of a fourth MISFET having the first conduction type, the drain of the second transistor is connected with the source of a fifth MISFET having the first conduction type, drains of the fourth and fifth MISFETs are connected to the data line pair, respectively, gates and drains of the second MISFET pair and the third MISFET pair are connected to respective data lines of the data line pair, the first MISFET pair is so composed as to reduce an offset of the threshold voltage in comparison with the second MISFET pair, while one of the plurality of word lines is being activated, the fourth MISFET and the fifth MISFET turn to an on-state, and a first voltage is supplied to sources of the first MISFET pair and the second MISFET pair, and a second voltage different from the first voltage is supplied to sources of the third MISFET pair.