Patent ID: 8102728
Filing Date: 2012-01-24
Classification: G11C

Abstract:
1. A memory array comprising: one or more memory cells coupled to a first bit line and a second bit line that is a complement of the first bit line, the one or more memory cells comprising transistors having a first nominal threshold voltage; and bit line control circuitry coupled to the first bit line and the second bit line, wherein the bit line control circuitry comprises at least one transistor having a second nominal threshold voltage that is less than the first nominal threshold voltage; wherein the bit line control circuitry and the one or more memory cells are powered by a first power supply voltage during use, and wherein the bit line control circuitry comprises a bit line driver circuit configured to drive write data on the first bit line and the second bit line for a write operation, and wherein the bit line driver circuit comprises the at least one transistor having the second nominal threshold voltage, and wherein a gate of the at least one transistor is coupled to receive a data bit to be written to the one of the memory cells, and wherein the bit line driver circuit comprises a second transistor in series with the at least one transistor and having a gate coupled to receive a write enable for the memory array, wherein the second transistor has the first nominal threshold voltage.