Patent ID: 7310011
Filing Date: 2007-12-18
Classification: G06F,H03K,H03L

Abstract:
1. A clock signal adjuster circuit, comprising: a first distribution circuit distributing a reference clock signal as a first distributed clock signal to an integrated circuit; an n-th distribution circuit finally distributing a n-th distributed clock signal, which is sequentially distributed via a second distribution circuit to an (n−1)-th distribution circuit which are configured hierarchically between the first distribution circuit and the n-th distribution circuit, to each area of the integrated circuit; a delay circuit delaying the reference clock signal as a delayed reference clock signal for a designated time period; a phase difference detector circuit detecting a phase difference between phases of the delayed reference clock signal and the n-th distributed clock signal distributed to said each area; and a phase difference adjustment circuit adjusting the phase of the n-th distributed clock signal distributed to said each area based on the phase difference detected by the phase difference detector circuit, wherein said phase difference adjustment circuit adjusts the phase of the n-th distributed clock signal at a location of the n-th distribution circuit.