Patent ID: 6486713
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A buffer circuit comprising:a first input node for receiving a digital signal; a controllable buffer circuit coupled to the first input node responsive to an enable signal, the controllable buffer circuit providing an output signal in response to the digital signal when the enable signal is in a first state, and the controllable buffer circuit being disabled when the enable signal is in a second state, said buffer circuit having a bias node; and a pulser circuit coupled to said bias node for providing a pulse signal to said bias node in response to said enable signal switching to said first state, wherein said pulser circuit comprises a first and second transistor connected in series between said bias node and a source of potential, said first transistor directly receiving said enable signal at a gate thereof, said second transistor receiving said enable signal at a gate thereof after it passes through at least a delay element.