Patent ID: 6134650
Filing Date: 2000-10-17
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache configured to store a cache line which includes a plurality of instructions, wherein said plurality of instructions are microcode or fastpath instructions, and wherein said instruction cache is configured to store predecode data identifying each of said plurality of instructions as either microcode or fastpath instructions;a microcode unit configured to parse microcode instructions into one or more fastpath instructions and dispatch said fastpath instructions into an instruction processing pipeline; andan instruction scan unit coupled between said instruction cache and said microcode unit and configured to: (i) predict that a first scanned instruction of said plurality of instructions is a microcode instruction prior to scanning said predecode data corresponding to said plurality of instructions and to convey said first scanned instruction to said microcode unit in response to predicting that said first scanned instruction is said microcode instruction, and (ii) verify that said first scanned instruction is a microcode instruction by scanning said predecode data, wherein if said first scanned instruction is not a microcode instruction, said instruction scan unit is configured to convey a signal to said microcode unit to invalidate said first scanned instruction.