Patent ID: 6020232
Filing Date: 2000-02-01
Classification: H01L

Abstract:
An integrated circuit process comprising:providing a semiconductor substrate;forming a gate dielectric on an upper surface of said semiconductor substrate;forming first and second conductive gates on said gate dielectric such that said first conductive gate is displaced over a first transistor region of said semiconductor substrate and said second conductive gate is displaced over a second transistor region of said semiconductor substrate;introducing a lightly doped impurity distribution into said second transistor region of said semiconductor substrate such that said lightly doped impurity distribution is substantially contained within first and second lightly doped impurity regions laterally displaced on either side of a channel region of said second transistor region and wherein a lateral dimension of said channel region of said second transistor region is approximately equal to a lateral dimension of said second conductive gate;introducing a first source impurity distribution into a first source region of said first transistor region, wherein said first source region is laterally displaced from a channel region of said first transistor region, and further wherein a channel boundary of said first source region is approximately coincident with a second sidewall of said first conductive gate; andintroducing a detached impurity distribution into said semiconductor substrate such that said detached impurity distribution is substantially contained within first and second pairs of detached source/drain regions, wherein respective pairs of said detached source/drain regions are laterally displaced on either side of channel regions within corresponding transistor regions of the semiconductor substrate and further wherein interior boundaries of said detached source/drain regions are laterally displaced a source/drain displacement from respective sidewalls of respective conductive gates.