Patent ID: 9065433
Filing Date: 2015-06-23
Classification: H03K

Abstract:
1. A capacitor charging circuit with reduced sub-threshold transistor leakage current, the circuit comprising: an input node; an output node; a control node; first and second series connected primary field effect transistors, each of the primary transistors having a gate electrode coupled to the control node, and wherein the first primary transistor is coupled between the input node and the output node and the second primary transistor is coupled between the output node and a leakage current reduction node; and first and second series connected leakage current reduction field effect transistors, each of the leakage current reduction transistors having a gate electrode coupled to the control node, and wherein the first leakage current reduction transistor is coupled between a power supply line and the leakage current reduction node and the second leakage current reduction transistor is coupled between the leakage current reduction node and a ground line, wherein, in operation, when a control signal at the control node is at a first voltage level, the first primary transistor and the first leakage current reduction transistor are in a conductive state and the second primary transistor and the second leakage current reduction transistor are in a non-conductive state, wherein, in operation, the first voltage level is substantially at a ground potential and the second voltage level is substantially at a potential of the power supply line, and wherein when the control signal is at the first voltage level, the first leakage current reduction transistor connects a source of the second primary transistor to the power supply line, thereby resulting in a gate to source voltage between the gate and source terminals of the second primary transistor that is greater than and opposite to a threshold voltage of the second primary transistor.