Patent ID: 6510474
Filing Date: 2003-01-21
Classification: G06F

Abstract:
In a memory controller arranged to control access of a memory device having a number of logical banks by a requesting device, a method of increasing data bandwidth by reordering incoming memory commands from the requesting device to the memory device in order to avoid gaps between commands while maintaining the original incoming memory command order from the requesting device at the memory device, comprising:receiving the incoming memory commands at the memory controller; calculating a best position in a command queue for each new incoming command by a restriction block coupled to the command queue that imposes time constraints on selected commands relative to other commands directed at the same logical bank of the memory device, wherein the best position is a position that minimizes an overall delay; reordering the incoming memory commands in the command queue based upon the best position; storing the incoming memory commands in their respective original order in a first register; issuing the re-ordered memory commands to the device; storing a sequence of data in a first data queue representative of the order in which the data corresponding to the re-ordered memory commands will be received from the memory device; storing requested data from the memory device in a second data queue based upon the sequence in the first data queue; and sending the requested data to the requesting device based upon the order stored in the first register such that the requested data is sent in the same order as the incoming memory commands in the first register.