Patent ID: 8847649
Filing Date: 2014-09-30
Classification: G06F,H03K,H03L

Abstract:
1. A circuit of adjusting system clock in low voltage detection, comprising: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal that is input to the clock generator according to a detected voltage level of a supply voltage, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system, when the detected voltage level is lower than a predetermined first threshold value, the low voltage reset circuit generates the adjustment signal, and wherein the low voltage reset circuit also generates a reset signal that is input to the at least one circuit when the detected voltage level is lower than a predetermined second threshold value, such that the at least one circuit in the system is reset to a predetermined value, wherein the predetermined first threshold value is greater than the predetermined second threshold value.