Patent ID: 9103885
Filing Date: 2015-08-11
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. input pads and output pads; B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad; C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; and D. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, a scan data output, and a scan control input coupled to the scan control lead.