Patent ID: 7234042
Filing Date: 2007-06-19
Classification: G06F

Abstract:
1. A system to process very long instruction words (VLIWs), the system comprising: a decode unit to decode an instruction of a VLIW received during an instruction fetch, wherein all instructions of the VLIW have the same predetermined instruction bit length; and first and second processing channels, each processing channel including a plurality of functional units, at least one of the functional units of each processing channel being a data processing unit and at least one other of the functional units of each processing channel being a memory access unit; wherein the decode unit is operable to determine whether the instruction defines a single operation or two independent operations based on at least one identification bit at at least one predetermined bit location in the instruction and to control the first and second processing channels based on the determination; wherein the decode unit is operable to identify certain combinations of the two independent operations based on the at least one identification bit; and wherein a first combination denotes two data processing operations, a second combination denotes two memory access operations, a third combination denotes a data processing operation and a memory access operation, and a fourth combination denotes a long instruction.