Patent ID: 6430727
Filing Date: 2002-08-06
Classification: G06F

Abstract:
A single chip integrated circuit device comprising:an on-chip CPU comprising fetch and execute circuitry for fetching and executing instructions from a memory, and an address register for holding an address in memory of a next instruction to be executed; a bus connected to the CPU for permitting the CPU to access said memory; a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes, the breakpoint range unit having comparison logic operative to compare the contents of the address register with each of the lower and upper breakpoint addresses and to issue a breakpoint signal when the address held in the address register is equal to the lower breakpoint address or between the lower and upper breakpoint addresses; on-chip control logic connected to receive the breakpoint signal and arranged to interrupt the normal operation of the CPU when the breakpoint signal is received, wherein the comparison logic further comprises inverse state logic for setting an inverse state indicator to cause generation of the breakpoint signal outside the address range defined by the upper and lower breakpoint address and wherein the breakpoint range unit comprises circuitry for inhibiting generation of the breakpoint signal for said next instruction on resumption of normal operation of the CPU after it has been interrupted.