Patent ID: 9201659
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A method for a multi-core computing device to offload portions of an input code from a first processor for execution on an auxiliary processor when the portions are automatically determined to be well-suited for the auxiliary processor, comprising: generating a graph-based intermediate representation of the input code, wherein the graph-based intermediate representation of the input code contains directed acyclic graphs (DAGs); comparing each node or combination of nodes to one or more patterns in a predefined grammar, wherein each pattern is a DAG pattern and is associated with a cost metric; identifying a set of patterns that partially cover the graph-based intermediate representation of the input code based on the comparisons of each node or the combination of nodes to the one or more patterns in the predefined grammar; and offloading from the first processor to the auxiliary processor segments of the input code associated with a combination of grammar patterns of the identified set of patterns having a cumulative effect that is better than cumulative effects of other combinations of the identified set of patterns and that is within a predefined cost threshold for the auxiliary processor, wherein the one or more patterns in the predefined grammar are known to be well suited for the auxiliary processor.