Patent ID: 8547750
Filing Date: 2013-10-01
Classification: G11C

Abstract:
1. A memory device, comprising: an adjacent pair of strings of memory cells, each comprising a memory cell to store user data and two or more dummy memory cells; and an adjacent pair of data lines that are electrically isolated from each other, wherein one data line of the adjacent pair of data lines is selectively coupled to one string of memory cells of the adjacent pair of strings of memory cells and the other data line of the adjacent pair of data lines is selectively coupled to the other string of memory cells of the adjacent pair of strings of memory cells; wherein a first dummy memory cell of the one string of memory cells of the adjacent pair of strings of memory cells has a control gate commonly coupled to a control gate of a first dummy memory cell of the other string of memory cells of the adjacent pair of strings of memory cells; wherein a second dummy memory cell of the one string of memory cells has a control gate commonly coupled to a control gate of a second dummy memory cell of the other string of memory cells; wherein the first dummy memory cell of the one string of memory cells has a threshold voltage greater than a threshold voltage of the first dummy memory cell of the other string of memory cells; and wherein the second dummy memory cell of the one string of memory cells has a threshold voltage less than a threshold voltage of the second dummy memory cell of the other string of memory cells.