Patent ID: 6791309
Filing Date: 2004-09-14
Classification: H03G,H04N

Abstract:
A limiter circuit comprising:a first differential amplifier to a first input terminal of which an input signal is applied; a first transistor to a base of which an output of the first differential amplifier is applied; a first feedback path connected between an emitter of the first transistor and a second input terminal of the first differential amplifier; a first current source connected to the emitter of the first transistor; a second differential amplifier to a first input terminal of which a bias voltage is applied; a second transistor to a base of which an output of the second differential amplifier is applied; a second feedback path connected between an emitter of the second transistor and a second input terminal of the second differential amplifier; a second current source connected to the emitter of the second transistor; and a resistance connected between the emitter of the first transistor and the emitter of the second transistor.