Patent ID: 6627527
Filing Date: 2003-09-30
Classification: H01L,Y10S

Abstract:
A method of forming metal silicide layer on a semiconductor substrate, comprising the steps of:providing a conductive gate structure on an underlying gate insulator layer, with insulator spacers located on the sides of the conductive gate structure, and with source/drain regions in portions of the semiconductor substrate not covered by the conductive gate structure or by the insulator spacers; forming a metal layer; performing a first anneal procedure at a first temperature to form a first metal silicide layer on said source/drain region and on the top surface of said conductive gate structure, while said metal layer located on said insulator spacers remains unreacted; selectively removing said unreacted metal layer from said insulator spacers; performing a second anneal procedure in a vacuum at a second temperature, with said second temperature lower than said first temperature; and performing a third anneal procedure at a third temperature, with said third temperature equal to, or greater than said first temperature, converting said first metal silicide layer to a second metal silicide layer, wherein said second metal silicide layer is comprised with a lower sheet resistance than said first metal silicide layer.