Patent ID: 6438052
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A semiconductor memory device fabricated on a semiconductor substrate, comprising:a plurality of memory cells arranged in a first area of a major surface of said semiconductor substrate in a certain geometric pattern for storing binary data bits in a readable and rewritable manner; a plurality of dummy cells having a capacitance, said plurality of dummy cells arranged in second areas of said major surface contiguous to said first area so as to render said certain geometric pattern continued from said first area to said second areas; electric circuits associated with said plurality of memory cells so as to write binary data bits into and read out said binary data bits therefrom; and an internal power source distributing an internal power voltage to said electric circuits, and connected to at least selected ones of said plurality of dummy cells so as to couple at least a part of said capacitance to said internal power source, thereby compensating voltage provided by said internal power source to said electrical circuits.