Patent ID: 7268615
Filing Date: 2007-09-11
Classification: H03H,H04N

Abstract:
1. A trap filter, comprising: a delay circuit for delaying an input signal and outputting a delay signal; wherein the delay circuit comprises: an adder circuit for adding the input signal and the delay signal; and a shift register for controlling a charge and discharge voltage of the sampling capacitor by sequentially outputting control signals to the read-in switch elements and the read-out switch elements, wherein the delay circuit further comprises n (n is an integer of 3 or more) stages of switched capacitors and the shift register comprises n+1 stages of flip-flops, wherein an output terminal of an initial stage flip-flop of the shift register is connected to a control terminal of the read-out switch element that is connected to an initial stage switched capacitor of the delay circuit, and wherein load dummy elements having loads equivalent to the read-in switch element and the read-out switch element are connected to the output terminals of the initial stage and final stage of the shift register, respectively.