Patent ID: 6737879
Filing Date: 2004-05-18
Classification: G01R

Abstract:
A method of wafer level testing, comprising:disposing a wafer onto a chuck such that a first major surface of the wafer is adjacent the chuck; disposing an anisotropic conductor onto a second major surface of the wafer, the second major surface of the wafer having a plurality of integrated circuits formed thereon, each of the integrated circuits having a plurality of pads; disposing a first major surface of a translator plate onto the anisotropic conductor, such that an electrical pathway is established between at least one of the plurality of pads of each of at least two of the plurality of integrated circuits, and corresponding electrical contact pads on a second major surface of the translator plate; electrically coupling the corresponding electrical contact pads to a first tester; and applying electrical signals from the first tester to the at least two integrated circuits.