Patent ID: 6807121
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A semiconductor memory device having a memory cell array that is constituted by a plurality of mats that are each provided with normal word lines and redundant word lines, said semiconductor memory device comprising:an X-system control circuit for, upon input of a refresh command instructing a refresh operation, generating and outputting a refresh activation signal that indicates the start of a refresh operation, outputting a redundancy non-access signal for preventing replacement by redundant word lines when refreshing normal word lines, and outputting a redundancy access signal for preventing activation of normal word lines when refreshing redundant word lines; a refresh counter for, upon input of a refresh activation signal from said X-system control circuit, successively generating and outputting addresses for selecting two normal word lines that do not belong to the same mat with each input of a refresh activation signal, and, after having generated addresses for selecting all normal word lines, successively generating addresses for selecting two redundant word lines that do not belong to the same mat with each input of a refresh activation signal and outputting these generated addresses as refresh addresses; a remedy circuit for activating a normal word line selection signal for enabling selection of normal word lines when said redundancy non-access signal is active, and activating a redundant word line selection signal for enabling selection of redundant word lines when said redundancy access signal is active; and an X-decoder for simultaneously activating two normal word lines instructed by said refresh addresses when said normal word line selection signal is active, and simultaneously activating two redundant word lines that are instructed by said refresh addresses when said redundant word line selection signal is active.