Patent ID: 6434588
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A n-bit binary counter with low power consumption comprising:a first adder section for adding a â€œ1â€  to a lower-order m-bit component of an n-bit input signal and producing a carry signal when the lower-order m-bit component is all 1's, said n-bit input signal having the lower-order m-bit component and a higher-order (nâˆ’m)-bit component; a second adder section for adding the carry signal to the higher-order (nâˆ’m)bit component; a first register for storing output of the first adder section in response to a first clock signal; a second register for storing output of the second adder section in response to a second clock signal; and means for receiving the first clock signal and the carry signal, and producing the second clock signal when the carry signal is generated from the first adder section, wherein the n-bit input signal is composed of outputs of the first and second register sections.