Patent ID: 6297106
Filing Date: 2001-10-02
Classification: H01L

Abstract:
A method for forming localized regions of low dielectric constant, K, (where K=<3.5) oxide in gate to drain overlap regions, for the purpose of reducing overlap capacitance, comprising the steps of:(a) forming a first oxide layer over a semiconductor substrate;(b) patterning and etching out said first oxide layer in order to define an eventual gate region;(c) depositing or growing a thin low dielectric constant, K, gate oxide on the silicon surface, corresponding to said eventual gate region;(d) forming one or more inverted spacers on the side walls of said etched out gate region within said first oxide layer;(e) removing that portion of said low K gate oxide, which is not protected by said spacers, thereby exposing the underlying silicon surface while still allowing localized regions of said low K gate oxide to remain under said spacers;(f) growing a conventional thermal gate oxide on said exposed silicon surface, in order to complete the creation of a gate oxide layer with a graded dielectric constant; and(g) subsequent formation of a conventional polysilicon gate structure, along with the formation of conventional source-drain contacts as well as implanted LDD regions and implanted N+ source-drain regions.