Patent ID: 6228726
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method of fabricating an integrated circuit semiconductor device with improved latchup protection on a semiconductor substrate whose surface has a first layer of pad oxide on top of which is a first layer of Si.sub.3 N.sub.4 comprising:defining with a first patterning element isolation structure areas on said semiconductor substrate surrounding and electrically isolating active device areas, said device areas being a PMOS device area and a NMOS device area;etching a shallow opening in said semiconductor substrate for an isolation structure;removing said first patterning element;providing a second oxide layer on the bottom and side walls of said open isolation structure;providing a second patterning element covering said PMOS device area to the center of said open isolation structure;implanting first ions into said semiconductor substrate to form a doped region under the bottom of said NMOS side of said open isolation structure;removing said second patterning element from said PMOS device area;providing a third patterning element covering said NMOS device area to the center of said open isolation structure;implanting second ions into said semiconductor substrate to form a doped region under the bottom of said PMOS side of said open isolation structure;removing third patterning element from said NMOS device area;filling said open isolation structure with a dielectric;completing the fabrication of said semiconductor device.