Patent ID: 6143621
Filing Date: 2000-11-07
Classification: H01L,Y10S

Abstract:
A method for determining overlay error during the manufacture of integrated circuits, comprising:providing a semiconductor wafer having a partially completed integrated circuit and a topmost first conductive layer;patterning and etching said first conductive layer to form a first pattern of subcomponents for the integrated circuits;as part of said first pattern, including a square having vertical and horizontal sides;depositing a dielectric layer over said first conductive layer;depositing a second conductive layer on the dielectric layer;patterning and etching said second conductive layer to form a second pattern of subcomponents for the integrated circuits;as part of said second pattern, forming four capacitor plates, each of which further comprises a contact area and a capacitor area;locating two of said capacitor plates whereby their contact areas are outside opposing vertical sides of the square and their capacitor areas extend inwards, overlapping said vertical sides by a first amount that is the same for both plates under conditions of exact alignment between the first and second patterns;locating the other two capacitor plates whereby their contact areas are outside opposing horizontal sides of the square and their capacitor areas extend inwards, overlapping said horizontal sides by a second amount that is the same for both plates under conditions of exact alignment between the first and second patterns;measuring the capacitance between each capacitor plate and the square; anddetermining the overlay error from the differences in capacitance value between opposing capacitor plates.