Patent ID: 9041569
Filing Date: 2015-05-26
Classification: H03M

Abstract:
1. A successive approximation register (SAR) analog-to-digital converter (ADC) comprising: an SAR comparator circuit including first and second inputs, a control input, and first and second outputs, the SAR comparator circuit including a plurality of capacitors coupled to the first and second inputs and including a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage; and a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator circuit, the calibration circuit including a signal generator to provide a control signal configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages provide a calibration signal to the SAR comparator circuit, the calibration circuit configured to calibrate the SAR comparator circuit based on corresponding output signals at the first and second outputs, the calibration circuit further including an error computation unit coupled to the first and second outputs and configured to determine a sign of an error associated with the output signals.