Patent ID: 6424193
Filing Date: 2002-07-23
Classification: H03L

Abstract:
A phase-locked loop (PLL) circuit for synchronizing frequencies of a first clock signal and a second clock signal, comprising:a first phase comparator circuit for comparing phases of a first clock signal having the first frequency and a feedback signal and for generating a control voltage corresponding to a phase difference between said first clock signal and said feedback signal, the first frequency being one of a quantity M of frequencies, where M is a positive integer; a second phase comparator circuit for comparing phases of the second clock signal having a second frequency and an output clock signal and for generating a differential signal indicative of a phase difference between said second clock signal and said output clock signal; a counter for counting data in response to the differential signal of said second phase comparator, the data having a maximum value controlled by the first frequency of the first clock signal; a decoder for decoding N-bit switching control signals from said data of said counter; and a voltage controlled delay line for generating said feedback signal in response to said first clock signal after said first clock signal is delayed while said control voltage is applied to a voltage controlled delay line; wherein said voltage controlled delay line includes N delay stages, which are connected in series corresponding to each bit of said N-bit switching control signals, and generates said output clock signal in response to a signal from a delay stage corresponding to said switching control signals.