Patent ID: 6030867
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A method of making an integrated circuit device, comprising:providing a transfer FET having a gate electrode and a source/drain region and providing a wiring line spaced from the gate electrode;depositing a dielectric layer over the transfer FET and the wiring line;etching the dielectric layer to expose a surface of the source/drain region, portions of the dielectric layer remaining over the gate electrode and the wiring line;depositing and patterning a first conductive layer to form a conductive pad in contact with the source/drain region, edges of the conductive pad being positioned over the gate electrode and the wiring line;depositing and planarizing an insulating layer over the first conductive layer, the insulating layer being deposited to a sufficient thickness so that a surface of the planarized insulating layer extends above the edge of the conductive pad over the gate electrode;after forming the planarized insulating layer, forming an opening in the planarized insulating layer extending from the surface of the planarized insulating layer to expose a surface of the conductive pad, edges of the opening being positioned on the surface of the conductive pad;after forming the opening, providing a second conductive layer to fill the opening in the planarized insulating layer, the second conductive layer being in contact with the exposed surface of the conductive pad;providing an etching mask over the second conductive layer and etching through the second conductive layer to form a patterned second conductive layer and to expose the surface of the planarized insulating layer, the patterned second conductive layer serving as a bottom capacitor electrode;providing a capacitor dielectric layer over the patterned second conductive layer; andproviding an upper capacitor electrode over the capacitor dielectric layer.