Patent ID: 7475311
Filing Date: 2009-01-06
Classification: G01R

Abstract:
1. A system and method for identifying at-speed errors in a device under test comprising: target logic within the device under test; and logic built-in serf-test (LBIST) circuitry coupled to the target logic, wherein the LBIST circuitry is configured to perform one or more test loops, wherein in each test loop, the LBIST circuit is configured to propagate an input bit pattern through the target logic and capture resulting output bit patterns at a normal operating speed of the target logic and at a test speed which is less than the normal operating speed of the target logic; wherein the LBIST circuitry includes a first multiple-input signature register (MISR) configured to store signatures corresponding to the output bit patterns generated at the normal operating speed and a second MISR configured to store signatures corresponding to the output bit patterns generated at the test speed; and wherein the LBIST circuitry is configured to detect differences between the output bit pattern corresponding to the normal operating speed and the output bit pattern corresponding to the test speed.