Patent ID: 6140238
Filing Date: 2000-10-31
Classification: H01L

Abstract:
A method of forming a conductive via between a lower copper interconnect layer and an upper copper interconnect layer in a semiconductor device structure, the method comprising:forming a lower conductive diffusion barrier layer on an underlying layer as part of the semiconductor device structure;forming a first copper layer on the lower diffusion barrier layer;forming an etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper;forming a second copper layer on the etch stop layer;forming a layer hardmask material on the second copper layer;patterning the layer of hardmask material to define a patterned hardmask;using the patterned hardmask to etch the second copper layer, the etch stop layer, the first copper layer and the lower diffusion barrier layer to form a patterned metal stack and to expose portions of the underlying layer;forming a layer of dielectric diffusion barrier material over the patterned metal stack;forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack;planarizing the first dielectric layer to expose an upper surface of the second copper layer;etching regions of the second copper layer using the etch stop layer as an etch stop, thereby defining spaced-apart copper via pillars;forming a second dielectric diffusion barrier layer over the copper via pillars;forming a second dielectric layer such that the second dielectric layer fills gaps between the copper via pillars;planarizing the second dielectric layer to expose an upper surface of the copper via pillars; andforming a patterned upper copper interconnect layer overlying the exposed copper via pillars, whereby the copper via pillars form vias between the lower copper interconnect layer and the upper copper interconnect layer.