Patent ID: 6766346
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A method for using a multiplier circuit of predetermined operand register size to compute an intermediate result in squaring large numbers, wherein the number exceeds the operand register size of the multiplier, said method comprising the steps of:(a) representing said number to be squared as a vector of binary digits; (b) grouping said vector into successive segments each having a length of said predetermined operand size; (c) loading said multiplier a first segment value and a second segment value to generate a first product value; (d) loading said multiplier with said first segment value to derive a second product value; (e) accumulating performing a right shift on a second product value to generate a halved second product value; (f) accumulating said first product value with said halved second product value to generate an accumulated value; and (g) doubling said accumulated value to generate said intermediate result.