Patent ID: 8832533
Filing Date: 2014-09-09
Classification: H03M,H04L

Abstract:
1. A data receiving circuit comprising: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and to store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first number of bits stored in the memory, a second number of bits stored in the memory, a third number of bits stored in the memory and a fourth number of bits in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, and the fourth number corresponding to the soft decision information of the second data, wherein the memory control circuit varies one of the first number, the second number, the third number, and the fourth number based on information indicating a validity or an invalidity of a transport-stream output and a number of diversity combinations.