Patent ID: 6184907
Filing Date: 2001-02-06
Classification: G06T,G09G

Abstract:
A graphics system for processing data generated by a host processor and for providing said data to a display device comprising:a first frame buffer having an r-bit wide data access port, where r is a positive integer, for storing video data generated by an application program executed on said host processor;a second buffer comprising:a RAM array for periodic storage of a portion of the video data stored in said frame buffer, and for periodic transmission of scan line data to said display device, said second buffer generating a read request control signal when at least one storage location therein is vacant;a control logic for generating a read strobe control signal and a mode select control signal in response to a display control signal from said display device from said display device;first and second address pointers for generating first and second read addresses respectively in response to the read strobe control signal; andan address selector for selecting one of the first and second read addresses and providing the selected address to said RAM array in response to the mode select control signal;a controller for controlling read and write operations of said frame buffer and said second buffer in response to the read request control signal from said second buffer; anda scan interpolator for vertically interpolating said scan line data transmitted from said second buffer, with respect to a predetermined number of scan lines on the display device.