Patent ID: 6524906
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method for planarizing simultaneously an oxide and a polysilicon layer in the fabrication of an integrated circuit device comprising:providing semiconductor device structures in and on a semiconductor substrate; depositing an oxide layer overlying said semiconductor device structures; depositing a silicon nitride layer overlying said oxide layer; etching a contact opening through said silicon nitride layer and said oxide layer to one of said semiconductor device structures; depositing a polysilicon layer overlying said silicon nitride layer and within said contact opening; polishing said polysilicon layer using an oxide slurry until said silicon nitride layer is contacted; and overpolishing said polysilicon layer, said silicon nitride layer, and said oxide layer in a timed polish using same said oxide slurry to remove said silicon nitride layer and planarize said oxide layer to complete said simultaneous planarization of said oxide and said polysilicon layers in the fabrication of said integrated circuit device.