Patent ID: 8790969
Filing Date: 2014-07-29
Classification: H01L

Abstract:
1. A method comprising: separating a semiconductor substrate layer into a first active region and second active region; defining a first gate structure of a first transistor over the first active region and a second gate structure of a second transistor over the second active region; masking a surface of the semiconductor substrate layer at the first active region and leaving the surface of the semiconductor substrate layer at the second active region unmasked; implanting a p-type dopant into the unmasked second active region; removing the masking from the surface of the first active region to reveal a non p-type doped surface region of the semiconductor substrate layer; baking the semiconductor substrate layer in a manner which will selectively passivate a surface of the semiconductor substrate layer, wherein baking comprises baking at a temperature which is below a temperature such that passivation is achieved in the first active region that is non p-type doped and passivation is not achieved in the second active region that is p-type doped; and performing a deposition on the surface of the semiconductor substrate layer in the absence of a mask which results in selective epitaxial semiconductor material growth over the passivated non p-type doped first active region to support elevated source and drain regions adjacent the first gate structure and wherein growth is suppressed over the not passivated second active region to support source and drain regions adjacent the second gate structure which are thinner than the elevated source and drain regions.