Patent ID: 8076711
Filing Date: 2011-12-13
Classification: H01L

Abstract:
1. A semiconductor device including a plurality of memory cells which are isolated by an element isolation insulating film and are arranged along a channel width direction, each of the memory cells comprising: a floating gate electrode which is formed on a semiconductor substrate with a tunnel insulating film interposed therebetween and has an upper region and a lower region wider in the channel width direction than the upper region, the whole sidewall of the lower region being in contact with the element isolation insulating film; an interelectrode insulating film which continuously covers an upper surface of the upper region, a sidewall of the upper region and an upper surface of the lower region, of the floating gate electrode; and a control gate electrode which is formed on the floating gate electrode with the interelectrode insulating film interposed therebetween, wherein the interelectrode insulating film which covers the sidewall of the upper region is formed across an interface between the lower region and the element isolation insulating film, and a part of a lower portion of the interelectrode insulating film which covers the sidewall of the upper region is formed between the sidewall of the upper region and the element isolation insulating film, and wherein the control gate electrode is commonly used for the plurality of the memory cells which are arranged along the channel width direction, and a portion of the control gate electrode is buried between the floating gate electrodes opposing each other in the channel width direction, and at least the buried portion of the control gate electrode is made of a semiconductor containing a dopant impurity.