Patent ID: 7818527
Filing Date: 2010-10-19
Classification: G06F,G11C

Abstract:
1. An electronic circuit comprising: a memory controller having a first address port and a first data port that are distinct from each other; and a wrapper circuit coupled to the memory controller and configured to interface the memory controller to one of a first memory or a second memory according to a select signal, wherein the wrapper circuit interfaces between the memory controller and the first memory when the select signal indicates the memory controller desires to control the first memory, the first memory having a second address port and a second data port that are not distinct from each other, wherein the wrapper circuit interfaces between the memory controller and the second memory when the select signal indicates the memory controller desires to control the second memory, the second memory having a third address port and a third data port that are distinct from each other, wherein the wrapper circuit comprises: a select circuit configured to multiplex write data and an address received from the memory controller, and configured to output a selected one of the write data and the address selected according to a first internal control signal; and an input/output buffer configured to receive the selected one of the write data and the address to provide the selected one of the write data or the address to the first memory, and configured to receive read data from the first memory and to pass the received read data to the memory controller; and a control signal processing circuit configured to receive control signals from the memory controller to generate the first internal control signal, wherein the control signal processing circuit includes a timing control circuit configured to control a timing between a selection of the address and a selection of the write data, and a timing of control signals for controlling the first memory, the timing circuit including at least one flip-flop synchronized to a falling edge of a clock, wherein the control signal processing circuit receives a first control signal, a second control signal, a third control signal, a fourth control signal, and the address from the memory controller, and wherein the at least one flip-flop receives the fourth control signal, the third control signal, the address, and a second internal control signal, and the second internal control signal is based on the first control signal, the second control signal, and the fourth control signal.