Patent ID: 6716691
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method of fabricating a CMOS having self-aligned shallow trench isolation, comprising:preparing a silicon substrate, including forming well structures therein to provide an active area; forming a gate stack, including forming a gate insulation layer; depositing a layer of first polysilicon to a thickness TP1Â±&Dgr;TP1, where TP1 is the desired thickness of the first polysilicon layer and &Dgr;TP1 is the variation of the thickness of the first polysilicon layer; trenching the substrate by shallow trench isolation to form a trench having a depth XSTIÂ±&Dgr;XSTI, where XSTI is the desired depth of the trench and &Dgr;XSTI is the variation of the depth of the trench; filling the trench with oxide to form a field oxide to a depth of TOXÂ±&Dgr;TOX, where TOX is the desired thickness and of the oxide &Dgr;TOX is the variation of the thickness of the oxide; depositing a second layer of polysilicon to a thickness TP2Â±&Dgr;TP2, where TP2 is the desired thickness of the second polysilicon layer and &Dgr;Tp2 is the variation of the thickness of the second polysilicon layer, and wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer, and wherein TP2âˆ’&Dgr;TP2+TOXâˆ’&Dgr;TOX>XSTI+&Dgr;XSTI+TP1+&Dgr;TP1; depositing a sacrificial oxide layer having a thickness of at least 1.5Ã— that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.