Patent ID: 6441866
Filing Date: 2002-08-27
Classification: H04N

Abstract:
In a video edge enhancement circuit comprising first and second delay lines coupled in series, the input signal to the edge enhancement circuit being delayed for a first time period by the first delay line to produce a primed first delayed signal, the primed first delayed signal being delayed for an additional time period by the second delay line to produce a second delayed signal, the edge enhancement circuit further comprising first and second amplifiers with inverting and noninverting inputs, the inverting input of the first amplifier receiving the input signal of the edge enhancement circuit, the inverting input of the second amplifier receiving the second delayed signal from the second delay line, the outputs of the first and second amplifiers being combined to produce a video output with edge enhancement of the transitions in the input signal;the improvement comprising biasing circuitry coupled between the output of the first delay line and the noninverting inputs of the first and second amplifiers, the biasing circuitry producing a non-primed first delayed signal and acting to suppress background noise from the input signal by suppressing low amplitude transitions from the input signal.