Patent ID: 8367494
Filing Date: 2013-02-05
Classification: H01L

Abstract:
1. A method of fabricating an electrical fuse and a field effect transistor having a metal gate, comprising: (a) removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, the active semiconductor region including a source region and a drain region adjacent edges of the first opening; and (b) forming a fuse element filling the second opening, the fuse element having one or more layers of conductive material each being a metal or a conductive compound of a metal; and (c) after step (b), depositing one or more metal layers onto a dielectric layer overlying the active semiconductor region within the first opening, the one or more metal layers including a gate metal layer having a workfunction selected so as to function as a metal gate of a field effect transistor (“FET”) including the metal gate and the active semiconductor region, wherein step (b) includes filling the first and second openings with the conductive material, then removing the conductive material from the first opening selectively relative to an interface layer overlying the active semiconductor region before performing step (c).