Patent ID: 6538867
Filing Date: 2003-03-25
Classification: H03K

Abstract:
An overvoltage tolerant bus switch for regulating the transfer of a logic signal between a first node and a second node, wherein the logic signal may be transferred from the first node to the second or from the second node to the first, the bus switch powered by a high-potential power rail and a low-potential power rail, the bus switch activated by an enable signal at an enable signal node, the bus switch comprising:a. a MOS transfer transistor having a gate coupled to the enable signal node, a source coupled to the first node, and a drain coupled to the second node; b. an arbitration circuit having a first input coupled to the first node, a second input coupled to the second node, a third input coupled to the high-potential power rail, said arbitration circuit having an output; and c. a pseudo high-potential power rail coupled to said output of said arbitration circuit and to a bulk region of said transfer transistor, wherein said arbitration circuit supplies said pseudo high-potential power rail a potential that is the highest of the potentials associated with the first node, the second node, and the high-potential power rail.