Patent ID: 6351791
Filing Date: 2002-02-26
Classification: G06F

Abstract:
A circuit arrangement for maintaining coherence between a plurality of snooper devices coupled to one another over a shared memory interface, the circuit arrangement comprising:(a) snoop logic associated with the plurality of snooper devices and configured to generate a plurality of local response signals in response to an access request for a selected memory address, each local response signal associated with the state of the selected memory address in a snooper device among the plurality of snooper devices, and the snoop logic further configured to generate a retry signal as the local response signal for a selected snooper device among the plurality of snooper devices when the snoop logic is unable to determine the state of the selected memory address in the selected snooper device; and (b) response collection logic, coupled to receive the plurality of local response signals generated by the snoop logic, the response collection logic configured to generate a prioritized response signal representative of a highest priority local response signal among the plurality of local response signals, and the response collection logic further configured to disregard any extraneous retry signal when generating the prioritized response signal.