Patent ID: 8629557
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A structure, comprising: a semiconductor wafer having an array of integrated circuit chips, each integrated circuit chip of said array of integrated circuit chips having an array of chip pedestals having respective chip solder columns on top surfaces of said chip pedestals, said pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to said first direction; and at least one monitor structure disposed in different regions of said semiconductor wafer from said integrated circuit chips, said monitor structure comprising at least a first pedestal and a first solder column on a top surface of said first pedestal and a second pedestal and a second solder column on a top surface of said second pedestal, said first and said second pedestals spaced apart a third distance, said third distance less than said first distance and said second distance.