Patent ID: 6104233
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of testing an input circuit, for a semiconductor device, that detects a level of an input signal V.sub.in by comparing the input signal V.sub.in with a reference signal V.sub.ref, said input circuit comprising a semiconductor material of a first conductivity type, a first region of a second conductivity type opposite the first conductivity type in a surface portion of said semiconductor material, a second region of the first conductivity type in said first region, and a third region of the first conductivity type in said first region, said method comprising the steps of:applying the input signal V.sub.in to said second region, wherein V.sub.in is negative;applying the reference signal V.sub.ref to said third region; andapplying to said first region a potential which is lower and has a greater magnitude than the potential of the input signal V.sub.in thereby preventing an injection of carriers generated at a junction between said first and second regions into said third region.