Patent ID: 7675157
Filing Date: 2010-03-09
Classification: H01L

Abstract:
1. A thermally enhanced integrated circuit package comprising: a thermally and/or electrically conductive substrate; a die attach material formed on the thermally and/or electrically conductive substrate; a semiconductor die having a first surface, a plurality of side surfaces, and a second surface opposing the first surface, wherein the first surface is adjacent to the die attach material; a plurality of die connectors in electrical communication with a plurality of die pads provided on the second surface of the semiconductor die; an encapsulant layer characterized by a first encapsulant surface positioned adjacent to the thermally and/or electrically conductive substrate and a second encapsulant surface opposing the first surface, wherein the encapsulant layer is a single unitary material continuously disposed to surround the plurality of side surfaces of the semiconductor die and is positioned over a portion of the second surface of the semiconductor die; and a routing layer formed on the second encapsulant surface of the encapsulant layer.