Patent ID: 7181709
Filing Date: 2007-02-20
Classification: G06F

Abstract:
1. A clock delay adjusting method of a semiconductor chip including hierarchical blocks, each hierarchical block including at least one clock input circuit which synchronously operates with a clock, wherein a plurality of source points for adjusting a clock delay is provided in order to synchronize a value of the clock delay from each of the source points of each of the hierarchical blocks to clock input circuits, respectively, in accordance with circuit design conditions of the hierarchical blocks, and area terminals are provided in the source points, respectively, and a clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top, a clock delay between the hierarchical blocks is adjusted, and at least one of the hierarchical blocks has a plurality of area terminals, and wiring length to the clock input terminal from one of the plurality of area terminals is equal to that from another area terminal.