Patent ID: 7738614
Filing Date: 2010-06-15
Classification: H04L

Abstract:
1. A decision timing synchronous circuit comprising: logical operation means for performing a logical operation based on a binary signal of a received modulated signal and a cyclic signal repeated regularly in a predetermined cycle; serial-to-parallel conversion means for receiving an operational output from the logical operation means and for sampling the operational output with predetermined sampling timing within one inversion cycle of the cyclic signal and then delivering the sampled value as a parallel signal value; correlation filter means having a plurality of digital filters providing output signal values for allowing each parallel signal value output from the serial-to-parallel conversion means to pass separately therethrough; maximum difference detection means for detecting a maximum difference in a period of timing during which a difference between a maximum value and a minimum value of each of the output signal values is equal to or greater than a threshold value, within one inversion cycle of the cyclic signal as a fundamental cycle based on each output signal value having passed through each of the digital filters of the correlation filter means; inversion timing detection means for determining a polarity of each of the output signal values having passed through each of the digital filters of the correlation filter means to detect polarity inversion timing; and decision timing determination means for determining the timing detected by the inversion timing detection means as decision timing, when the maximum difference is detected by the maximum difference detection means.