Patent ID: 8199578
Filing Date: 2012-06-12
Classification: G11C,H01L

Abstract:
1. A single-polysilicon layer non-volatile memory, comprising: a plurality of memory cell rows, disposed on a substrate to form a memory cell array, each of the memory cell rows comprising a plurality of memory cells connected in series, and each of the memory cells comprising: a plurality of program lines, respectively coupled to the program gates of the memory cells of a same row; a plurality of control lines, respectively coupled to the control gates of the memory cells of a same column; and a plurality of erase lines, respectively formed by a well region under each of the memory cell rows, an isolation structure, disposed in the substrate to define a first active region, a second active region and a third active region, and the floating gate crossing the first active region, the second active region and the third active region, wherein a source region and a drain region of the floating gate transistor are respectively disposed in the first active region of the substrate located at two sides of the floating gate, the program gate is disposed in the second active region, the control gate is disposed in the third active region, the floating gate transistor is a P-channel transistor, and the program gate and the control gate are respectively an N-type well region.