Patent ID: 8199040
Filing Date: 2012-06-12
Classification: H03M

Abstract:
1. A ΔΣ analog-to-digital convertor comprising: first and second amplifiers, each comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; an input node; first to fourth capacitors; a comparator that generates an output logical value based on a conversion voltage generated according to a charge amount accumulated in the fourth capacitor; a first switch connected between the input node and the inverting input terminal of the first amplifier, the first switch being configured to switch between a conductive state and a cut-off state; a second switch connected between the input node and the output terminal of the first amplifier, the second switch being configured to switch between a conductive state and a cut-off state; a third switch connected between the input node and one end of the first capacitor, the third switch being configured to switch between a conductive state and a cut-off state; a fourth switch connected between another end of the first capacitor and a first reference voltage node, the fourth switch being configured to switch between a conductive state and a cut-off state, and a first reference voltage being supplied through the first reference voltage node; a fifth switch connected between one end of the second capacitor and the inverting input terminal of the second amplifier, the fifth switch being configured to switch between a conductive state and a cut-off state; a sixth switch connected between another end of the second capacitor and the output terminal of the second amplifier, the sixth switch being configured to switch between a conductive state and a cut-off state; a seventh switch connected between one end of the third capacitor and the output terminal of the second amplifier, the seventh switch being configured to switch between a conductive state and a cut-off state; an eighth switch connected between another end of the third capacitor and the first reference voltage node, the eighth switch being configured to switch between a conductive state and a cut-off state; a ninth switch connected between one end of the fourth capacitor and the first reference voltage node, the ninth switch being configured to switch between a conductive state and a cut-off state; a tenth switch connected between the another end of the first capacitor and the inverting input terminal of the first amplifier, the tenth switch being configured to switch between a conductive state and a cut-off state; an eleventh switch connected between the inverting input terminal of the first amplifier and the one end of the second capacitor, the eleventh switch being configured to switch between a conductive state and a cut-off state; a twelfth switch connected between the another end of the second capacitor and the output terminal of the first amplifier, the twelfth switch being configured to switch between a conductive state and a cut-off state; a thirteenth switch connected between the another end of the third capacitor and the inverting input terminal of the second amplifier, the thirteenth switch being configured to switch between a conductive state and a cut-off state; a fourteenth switch connected between the inverting input terminal of the second amplifier and the one end of the fourth capacitor, the fourteenth switch being configured to switch between a conductive state and a cut-off state; a fifteenth switch connected between another end of the fourth capacitor and the output terminal of the second amplifier, the fifteenth switch being configured to switch between a conductive state and a cut-off state; the sixteenth switch connected between either the third or the forth voltage node and one end of the first capacitor, or connected between neither the third nor the forth voltage node and one end of the first capacitor, and a third reference voltage being supplied through the third reference voltage node and a fourth reference voltage being supplied through the fourth reference voltage node; and the seventeenth switch connected between either the third or the forth voltage node and one end of the third capacitor, or connected between neither the third nor the forth voltage node and one end of the third capacitor, and a third reference voltage being supplied through the third reference voltage node and a fourth reference voltage being supplied through the fourth reference voltage node.