Patent ID: 6218283
Filing Date: 2001-04-17
Classification: H01L

Abstract:
A method of fabricating a multi-layered wiring system of a semiconductor device, the method comprising the steps of:forming first and second conductive layers on a semiconductor substrate having a first insulation layer;forming an anti-reflective layer in the structure of Ti/TiN deposition layer by means of a sputter device having a collimator on the second conductive layer;selectively etching predetermined portions of the anti-reflective layer, the second conductive layer and the first conductive layer to expose predetermined portions of the first insulation layer to form a metal wire, the metal wire having the deposition structure of the anti-reflective layer/the second conductive layer/the first conductive layer;forming a second insulation layer;forming a via hole by dry-etching predetermined portions of the second insulation layer and the anti-reflective layer to expose predetermined portions of the surface of the metal wire and forming a tapered portion of the anti-reflective layer remaining substantially along the edges of the via hole and substantially near a bottom surface thereof;performing a wet etching process to remove polymer components from the via hole;performing an RF sputter etching process to remove oxide from the metal wire and the tapered portion of the anti-reflective layer;forming a conductive plug inside the via hole;forming a third conductive layer of Ti on the conductive plug and a second insulation layer;forming a fourth conductive layer from the group consisting of Al alloy and Cu alloy on top of the third conductive layer;forming a second anti-reflective layer comprising Ti and TiN deposition layers; andforming a second metal wire that has the second anti-reflective layer at the upper portion thereof and the third conductive layer at the lower portion thereof.