Patent ID: 6201411
Filing Date: 2001-03-13
Classification: H01L,H03K

Abstract:
An integrated circuit, comprising:an internal power bus;a ring of I/O cells;a plurality of logic blocks substantially surrounded by the ring of I/O cells; andan interconnect structure for coupling selected ones of the logic blocks together, wherein each of the logic blocks comprises:a digital logic element that draws a spike of supply current during switching, the spike of supply current having a magnitude A; andmeans for receiving energy from the internal power bus, for storing that energy in a parallel plate capacitor above the digital logic element, and for supplying that energy to the digital logic element in the form of a spike of supply current during the switching of the digital logic element, the spike of supply current supplied by the means for receiving energy having a magnitude B, wherein magnitude B is at least half as great as magnitude A.