Patent ID: 6737296
Filing Date: 2004-05-18
Classification: H01L,Y10T

Abstract:
In a method of forming a wire-bond package arrangement including a substrate; at least one semiconductor chip mounted on said substrate; and at least one each of a power loop comprising a strip and pad, a ground bus and a signal loop comprising a strip and pad at the height of the substrate surfaces mounting said at least one chip being operatively connected to circuitry on said chip by wires; said at least one power loop comprising a voltage bus, the interstitial pattern of said voltage and ground buses enabling the provision of a single row of wire-bond connections on the substrate to simulate a single ring, the improvement comprising:a) locating said at least one power loop and ground bus being located in an interstitial pattern on the surface of said substrate; b) having a first wire extending in a vertical height between the surface of the substrate and the surface of said chip, said wire commonly interconnecting said interstitial pattern formed by said at least one power loop and ground bus with circuitry on said chip; and c) extending a second wire in a vertical loop spaced above said first vertical wire loop and interconnecting circuitry on said chip with said at least one signal loop.