Patent ID: 6682986
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A method of forming a shallow trench isolation of a semiconductor device, comprising:providing a semiconductor substrate including a field region and an active region; forming a first insulating layer and a mask layer on the active region that expose the field region of the substrate; etching the exposed field region of the substrate to form a shallow trench; wet-etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench using a pull-back process; forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; forming a third insulating layer as covering the liner layer and filling the shallow trench; etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; removing a remaining portion of the mask layer; and removing a remaining portion of the first insulating layer.