Patent ID: 9196316
Filing Date: 2015-11-24
Classification: G11C,H01L,H03K

Abstract:
1. An integrated circuit package, comprising: a first die comprising at least one power pad disposed between a first chip-enable pad and a second chip-enable pad, wherein the first chip-enable pad is bonded to an external pin of the package, and the second chip-enable pad is not connected to an external pin of the package and is left floating; and a first chip-enable input buffer circuit coupled to the first chip-enable pad and a second chip-enable input buffer circuit coupled to the second chip-enable pad, wherein the first chip-enable input buffer circuit is configured to be enabled at power-up of the integrated circuit package and the second chip-enable input buffer circuit is configured to be disabled at power-up of the integrated circuit package; a first latch to be cleared before the integrated circuit package is powered up and to be set when the first chip enable pad is driven to a predetermined logic level by an external source; a first weak driver to hold the first chip enable input pad at an inverse of the predetermined logic level when the first latch is clear; a second latch to be cleared before the integrated circuit package is powered up and to be set if the second chip enable input pad is driven to the predetermined logic level by the external source; and a second weak driver to hold the second chip enable input pad at the inverse of the predetermined logic level when the second latch is clear; logic to enable an electronic memory on the integrated circuit package only if the first chip enable input pad is at the inverse of the predetermined logic level and the second chip enable input pad is active.