Patent ID: 6828206
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A method for fabricating a semiconductor device, comprising:providing a semiconductor substrate which has a silicon region located on an insulating layer formed in the semiconductor substrate; forming a metal layer on the silicon region of the semiconductor substrate; performing a first rapid thermal annealing on the semiconductor substrate to form first-reacted silicide regions; forming a supplemental silicon layer on the first-reacted silicide regions; doping an impurity into the supplemental silicon layer; and performing a second rapid thermal annealing to convert the first-reacted silicide regions into second-reacted silicide regions, by reaction of the supplemental silicon layer with the first-reacted silicide regions, the semiconductor device including a p-channel MOS transistor having p-type source and drain diffusion layers, and including an n-channel MOS transistor having n-type source and drain diffusion layers, said doping comprising doping the impurity into the supplemental silicon layer so that only the supplemental silicon layer formed over the p-channel MOS transistor is doped, or so that only the supplemental silicon layer formed over the n-channel MOS transistor is doped, and a thickness of the silicon region is in a range of 50-100 nm.