Patent ID: 6165825
Filing Date: 2000-12-26
Classification: H01L

Abstract:
A method for producing a semiconductor device including a MISFET of a first conductivity type and a MISFET of a second conductivity type, the method comprising:a first step of forming, on a semiconductor substrate having a semiconductor region, an element-isolating insulating layer for dividing said semiconductor region into a first-conductivity-type MISFET forming region and a second-conductivity-type MISFET forming region;a second step of forming a protective insulating layer on a surface of said semiconductor substrate;a third step of forming, on said protective insulating layer, a first resist layer having an opening above at least a part of said first-conductivity-type MISFET forming region;a fourth step of implanting, from above said protective insulating layer, additive impurity ions into said semiconductor substrate at least once by using said first resist layer as a mask;a fifth step of performing etching by using said first resist layer as a mask, until a portion of said protective insulating layer, which is exposed through said opening of said first resist layer, is removed after the fourth step has been performed;a sixth step of removing said first resist layer after the fifth step has been performed;a seventh step of forming, on said substrate, a second resist layer having an opening above said second-conductivity-type MISFET forming region, after the sixth step has been performed;an eighth step of implanting, from above said protective insulating layer, additive impurity ions into said semiconductor substrate at least once by using said second resist layer as a mask;a ninth step of performing etching by using said second resist layer as a mask, until a portion of said protective insulating layer, which is exposed through said opening of said second resist layer, is removed after the eighth step has been performed; anda tenth step of removing said second resist layer after the ninth stop has been performed.