Patent ID: 6388498
Filing Date: 2002-05-14
Classification: H01L,H03M

Abstract:
A semiconductor device including one semiconductor chip, comprising:first, second and third high potential power supply terminals formed on said semiconductor chip and receiving power supply voltages applied from an exterior to the semiconductor chip; first, second and third low potential power supply terminals formed on said semiconductor chip and receiving power supply potentials respectively lower than potentials of said first, second and third high potential power supply terminals applied from an exterior to the semiconductor chip; a first internal circuit supplied with operating power supply voltages from said first high potential power supply terminal and said first low potential power supply terminal; a second internal circuit supplied with operating power supply voltages from said second high potential power supply terminal and said second low potential power supply terminal; and an interface circuit supplied with operating power supply voltages from said third high potential power supply terminal and said third low potential power supply terminal, receiving a first signal from said first internal circuit and outputting a second signal to said second internal circuit, said second signal being a digital signal having a high level and a low level respectively corresponding to the potentials received by said third high and low potential power supply terminals.