Patent ID: 7157353
Filing Date: 2007-01-02
Classification: B33Y,H01L

Abstract:
1. A method for fabricating semiconductor components comprising: providing a plurality of semiconductor dice on a substrate having a first side, a second side, and a plurality of die contacts on the first side; forming a polymer layer on the first side having a plurality of first slots in a criss cross pattern between the dice; forming an etch mask on the second side having a plurality of second slots aligned with the first slots; forming a plurality of terminal contacts on the polymer layer in electrical communication with the die contacts; anisotropically etching the substrate from the first side and the second side at a same time forming first grooves in the first side aligned with the first slots and second grooves in the second side aligned with the second slots for a time period sufficient to singulate the substrate and separate the dice into a plurality of chip scale components.