Patent ID: 6580307
Filing Date: 2003-06-17
Classification: H01L,H03K

Abstract:
A level shift circuit for shifting an input voltage to an output voltage comprising:a first complementary metal oxide semiconductor (CMOS) transistor formed on a first p-substrate for providing a reference, the first CMOS transistor having a first PMOS transistor and a first NMOS transistor; a second CMOS transistor formed on a second p-substrate for providing a reference, the second CMOS transistor having a second PMOS transistor and a second NMOS transistor, a gate electrode of the first PMOS of the first CMOS being connected to a gate electrode of the second PMOS of the second CMOS; a third PMOS and a fourth PMOS, a source electrode of the third PMOS and a source electrode of the fourth PMOS being connected to a power supply, a gate electrode of the third PMOS being connected to a source electrode of the second PMOS of the second CMOS, a gate electrode of the fourth PMOS being connected to a source electrode of the first PMOS of the first CMOS, a drain electrode of the third PMOS being connected to a source electrode of the first PMOS of the first CMOS, a drain electrode of the fourth PMOS being connected to a source electrode of the second PMOS of the second CMOS; and a third NMOS having a drain electrode, being connected to the second source electrode of the second NMOS of the second CMOS, a gate electrode being connected to the first source electrode of the first NMOS of the first CMOS, and a source electrode being grounded.