Patent ID: 6441664
Filing Date: 2002-08-27
Classification: H03L,H04L

Abstract:
A signal phase adjustment circuit, comprising:a clock phase modification circuit to modify a phase of an input clock signal and to output a phase modified clock signal; an input signal adjustment circuit to receive an input data signal and to transmit the data signal, and which operates based on the phase modified clock signal output from the clock phase modification circuit; a reception determination unit to determine a reception status of the data signal transmitted from the input signal adjustment circuit based on a pre-set fixed pattern signal and the data signal transmitted from the input signal adjustment circuit; and a control unit to control an amount of phase modification of the clock phase modification circuit based on the determination results of the reception determination unit, wherein the control unit determines an amount of phase modification from upper and lower limits of an amount of phase modification of a region, among stable phase regions, having a continuous region width of a specified value or more.