Patent ID: 6538287
Filing Date: 2003-03-25
Classification: H01L

Abstract:
Embedded dynamic random access memory (DRAM) circuits with logic integrated semiconductor circuits comprised of:a semiconductor substrate having logic regions and memory regions with device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; P-doped wells and deep N-doped wells in said memory regions' device areas; polysilicon capacitor bottom electrodes on and electrically contacting said device areas in said memory regions; N-doped wells and P-doped wells in said device areas of said logic regions; a single conformal dielectric layer as a gate oxide for FETs and as an interelectrode dielectric layer over said capacitor bottom electrodes; a patterned conformal second polysilicon layer for gate electrodes for said FETs and for capacitor top electrodes over said capacitor bottom electrodes to provide DRAM capacitors; lightly doped source/drain areas in said substrate adjacent to said FET gate electrodes; sidewall spacers on sidewalls of said gate electrodes; source/drain contact areas in said substrate adjacent to said sidewall spacers; a silicide on said gate electrodes and said source/drain contact areas to provide a salicide FET structure; a planarized insulating layer on said salicide FET structures and said DRAM capacitors; and, said insulating layer having contact openings for electrical contacts to said substrate; a multilevel of metal interconnections to complete said logic integrated semiconductor circuits with said embedded DRAM circuits.