Patent ID: 6579778
Filing Date: 2003-06-17
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, which method comprises:forming a memory core region on a semiconductor substrate as a plurality of substantially parallel, substantially rectangular rows of field oxide separated at a first portion of each row by a source region and at a second portion of each row by a channel region adjacent to the source region; forming the field oxide by shallow trench isolation; forming a polysilicon floating gate above each channel region; etching to remove the first portion of each row and expose a portion of the substrate corresponding to the first portion; forming a protective dielectric spacer on a sidewall of each floating gate, the protective spacers extending onto each source region; ion implanting impurities into the source regions and the exposed portions of the substrate corresponding to the first portion of each row to form a layer of the impurities; and simultaneously forming a metal silicide layer on the source regions and the exposed portions of the substrate corresponding to the first portion of each row to form a continuous conductor and on a contact area of a bit line.