Patent ID: 8762641
Filing Date: 2014-06-24
Classification: G06F,Y02D

Abstract:
1. A method executed by a processor for accessing a cache, wherein the cache comprises a tag array, a data array and a valid array, the method comprising: setting all entries in the valid array to a first array value; before all valid array entries are validated, establishing a valid control register for the cache, the valid control register indicating whether all valid array entries are validated; setting the valid control register to a first control value before all valid array entries are validated; monitoring the valid array entries on an entry-by-entry basis while the processor is executing a program and setting the valid control register to a second control value when it is determined that all valid array entries are validated; after the second control value is set, if, after the valid array entry has been set to the second array value, the data array entry subsequently becomes invalid,