Patent ID: 8839070
Filing Date: 2014-09-16
Classification: H03M,H04L

Abstract:
1. An error correction apparatus including a plurality of error correction circuits connected in series, each of the plurality of error correction circuits comprising: a calculator circuit that calculates a reliability of a codeword indicating a probability of occurrence of correction errors of the codeword; a determination circuit that compares the reliability calculated by the calculator circuit with a threshold value, and determines in accordance with comparison results whether an error correction circuit at a present stage among the plurality of error correction circuits is to correct the codeword; and a corrector circuit that corrects the codeword in accordance with determination results of the determination circuit, wherein each of the error correction circuits correct the codeword when the determination results of the determining circuit indicate that the error correction circuit at the present stage is to correct the codeword, the determination circuit in an error correction circuit at a subsequent stage among the plurality of error correction circuits determines whether the error correcting circuit at the subsequent stage is to correct the codeword when the determination results of the determination circuit indicate that the error correction circuit at the present stage is not to correct the codeword, wherein the calculator circuit calculates the reliability of the codeword in accordance with information of an order of an error polynomial of the codeword and a number of roots of the error polynomial, and information of a correlation relationship between the codeword as a correction target and another codeword that intersect the correction target codeword at a correction location of the codeword as the correction target, the determination circuit in each of the plurality of error correction circuits determines whether to redo the correction of the codeword corrected by an error correction circuit at a preceding stage among the plurality of error correction circuits in accordance with the comparison results, and the corrector circuit redoes the correction of the codeword in accordance with the determination results, and the determination circuit in each of the plurality of error correction circuits determines whether to redo the correction of the codeword corrected by the error corrector at the preceding stage in accordance with information of the error polynomial and the information of the reliability of the codeword transmitted from the error corrector at the preceding stage.