Patent ID: 8143718
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate including a first surface and a second surface corresponding to a back surface with respect to the first surface and having first through electrodes which extend through the first surface and the second surface; a semiconductor chip over the first surface of the semiconductor substrate, the semiconductor chip is comprised of a same material as the semiconductor substrate and has a circuit element electrically connected to the first through electrodes; a stress relaxing section including first conductors over the second surface of the semiconductor substrate and electrically connected to the first through electrodes of the semiconductor substrate and having flexibility, the stress relaxing section including a first insulator over the second surface of the semiconductor substrate so as to cover the side surfaces of the first conductors and the second surface of the semiconductor substrate, and having elasticity, the first conductors have columnar shape; external connecting terminals over the stress relaxing section and connected to the first conductors respectively, wherein each of the first conductors of the stress relaxing section has a third surface opposite to the second surface of the semiconductor substrate and electrically connected to a corresponding first through electrode, a fourth surface corresponding to a back surface with respect to the third surface and connected to a corresponding external connecting terminal, and a side surface that connects the third surface and the fourth surface, wherein the semiconductor substrate, the semiconductor chip and the stress relaxing section are configured together as a semiconductor package, wherein the semiconductor package is on a circuit board with the stress relaxing section facing the circuit board, a linear expansion coefficient of the circuit board being different than a linear expansion coefficient of the semiconductor substrate, and wherein a planar size of the stress relaxing section and a planar size of the semiconductor substrate are the same; and conductive films over the second surface of the semiconductor substrate, the conductive films each having a first portion connected to a corresponding first through electrode of the semiconductor substrate and a second portion connected to the third surface of a corresponding first conductor.