Patent ID: 8860389
Filing Date: 2014-10-14
Classification: G05F

Abstract:
1. A fast load transient response circuit in an LDO regulator, comprising: a feedback loop that senses a load transient; a first driver having an output impedance equal to R/k and a second driver having an output impedance of R/(1−k) where R is an output impedance necessary to drive a first larger and second smaller pass transistors, and k/R+(1−k)/R=1/R, where k is the constant, having a value greater than zero and less than one, both drivers being responsive to a feedback signal from the feedback loop; and the first pass transistor having a channel width equal to n*W and the second pass transistor having a channel width equal to (1−n) W where W is a channel width required to meet a dropout requirement with sources and drains being coupled to each other and wherein n*W+(1−n)W=W where n is a constant, having a value greater than zero and less than one and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver, both the pass transistors operating at the same time, wherein a width of a channel to a length of the channel ratio of the first pass transistor is different than that of the second pass transistor such that k is greater than n, the second pass transistor reacting faster than the first pass transistor to a load transient.