Patent ID: 6212603
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A processor that prefetches and executes instructions in a pipelined manner, the processor being associated with a first cache and comprising:an instruction cache that stores instructions yet to be executed;an instruction pointer that selects one of a plurality of incoming addresses for fetching instructions;an instruction streaming buffer (ISB) that stores instructions returned from the first cache before the instructions are written into the instruction cache;a way multiplexer coupled to the instruction cache that outputs an instruction selected by the instruction pointer;a bypass path that provides the instruction to the way multiplexer from a plurality of bypass sources other than the instruction cache before the instruction is written into the instruction cache responsive to a demand request, the bypass sources including the ISB; anda request address buffer (RAB) that registers physical and virtual addresses associated with an instruction of a miss request by the processor to the first cache, each entry of the RAB having an identification (ID) that is sent to the first cache as part of the miss request along with an indicator that determines fetch priority of the miss request, the ID being returned to the RAB from the first cache to read out the physical and virtual addresses corresponding to the instruction of the miss request, the physical and virtual addresses being read out from the RAB into the ISB.