Patent ID: 6785173
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array for storing data information; an address buffer circuit for receiving an external address in response to a test clock signal; means for generating a test period signal synchronized with an external clock signal in a test operation mode; means for generating a test clock signal in response to the test period signal during a half cycle of the external clock signal, the test clock signal having a shorter cycle than that of the external clock signal; means for generating test data in response to the test clock signal; means for writing the test data in an area of the memory cell array addressed by the external address in each cycle of the test clock signal; means for reading the test data from the area of the memory cell array in each cycle of the test clock signal and outputting the read-out data to data lines; and means for receiving data bits on the data lines and determining whether the data bits thereon have the same value, wherein the means for receiving the data bits outputs an external flag signal as a determination result.