Patent ID: 6638850
Filing Date: 2003-10-28
Classification: H01L

Abstract:
A method of fabricating a semiconductor integrated circuit device, comprising the steps of:(a) preparing a semiconductor substrate having a semiconductor layer having a main surface; (b) forming an insulating film over said main surface of said semiconductor layer; (c) etching said insulating film and said semiconductor layer to form a connecting hole; (d) etching said insulating film to enlarge the connecting hole in said insulating film; (e) forming a conductive film in said connecting hole; prior to said step (d), introducing impurities through said connecting hole to form a high-concentration region in said semiconductor substrate, wherein said semiconductor layer has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type formed below the first semiconductor region, said connecting hole extends to said second semiconductor region, and said conductive film is electrically connected with said first semiconductor region, in said connecting hole, at the main surface of said semiconductor layer and at a wall surface of said semiconductor layer in said connecting hole; and further comprising the step, prior to said step (d), of introducing impurities through said connecting hole to form, in said second semiconductor region, a third semiconductor region of the second conductivity type having an impurity concentration higher than that of said second semiconductor region.