Patent ID: 7697641
Filing Date: 2010-04-13
Classification: H04B,H04L

Abstract:
1. A parallel-processing demodulator for processing an input signal to be received in a modem or communication system, the demodulator comprising parallel processing circuitry; wherein said parallel processing circuitry comprises a plurality of circuit blocks arranged in a parallel array of signal-processing branches for concurrent processing of different portions of the input signal, one portion of said parallel processing circuitry in each of said branches being a matched filter, a second portion of said parallel processing circuitry in each of said branches being digital down-conversion circuitry, and a further portion of said parallel processing circuitry in each of said branches being a parallel fractional interpolator, the digital down-conversion circuitry and the parallel fractional interpolator being serially connected to the matched filter; said demodulator further includes means for distributing said different signal portions to the circuit blocks; said demodulator further comprises reference circuitry having plural numerically controlled oscillators for applying time reference signals and phase reference signals for driving circuit blocks of the parallel processing circuitry, such that the time reference signals drive the matched filter and the parallel fractional interpolator via one of said numerically controlled oscillators, and the phase reference signals drive the digital down-conversion circuitry via a second of said numerically controlled oscillators; and said parallel processing circuitry is constructed in programmable form for processing signals having different characteristics of modulation and coding.