Patent ID: 6549570
Filing Date: 2003-04-15
Classification: H04L,H04M

Abstract:
An apparatus comprising:a communications line interface which can be operatively coupled to a communications line; and a frequency detection circuit operatively coupled to said interface and having an output, said frequency detection circuit being operable to detect through said interface an occurrence of each of a plurality of predetermined frequencies on said communications line and to provide to said output an indication of each said frequency which has been detected, wherein said frequency detection circuit includes: a plurality of phase locked loops, each said phase locked loop having an input coupled to said interface, having an output, and being operable to detect a respective one of said frequencies; and a plurality of memory devices, each said memory device having an input coupled to said output of a respective one of said phase locked loops, being operable to store the output of said phase locked loop connected thereto, and each said memory device having an output; wherein said interface includes a first coupling part which can be operatively coupled to the communications line, a second coupling part which can be operatively coupled to the communications line, and an amplifier having an input operatively coupled to said first and second coupling parts, and having an output coupled to said input of each said phase locked loop; further including a reset circuit, said reset circuit including a manually operable reset input portion and said reset circuit being operable to reset each said memory device in response to manual operation of reset input portion; wherein said manually operable reset input portion includes a manually operable switch, and wherein said reset circuit includes a conditioning circuit, said conditioning circuit having an input coupled to said switch and having an output coupled to a reset input of each said memory device, said conditioning circuit being operable to debounce said switch; wherein said frequency detection circuit further includes a plurality of pull-up resistors, each said pull-up resistor having a first end coupled to a voltage source and having a second end, and includes a plurality of frequency selection circuits, each said phase locked loop having a further input operatively coupled to a respective one of said frequency selection circuits, said frequency selection circuits being operable to determine which of said predetermined frequencies each said phase locked loop detects, and said output of each said phase locked loop being an open collector output coupled to said second end of a respective one of said pull-up resistors, wherein each said phase locked loop outputs a first voltage level when detecting the predetermined frequency associated therewith and outputs a second voltage level when detecting a frequency other than the predetermined frequency associated therewith, wherein said memory devices are flip-flops, each said flip-flop having a set input coupled to said output of a respective one of said phase locked loops, having a reset input which is said input coupled to said output of said conditioning circuit, and having an output coupled to said input of a respective one of said drivers, wherein said reset switch is a single pole, single throw momentary switch, and wherein said first coupling part and said second coupling part are both industry standard connectors.