Patent ID: 6103622
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of forming low resistance silicide for a mixed mode, analog/digital device comprising the steps of:providing a substrate having gate oxide and field oxide regions;depositing a first polysilicon layer over said substrate;patterning said first polysilicon layer to form a gate of an FET device and first electrode of a dual layer capacitor;forming oxide spacers adjacent to sidewalls of said gate and first electrode;forming source/drain regions in said substrate;depositing interpolysilicon oxide (IPO) over said substrate;depositing a second polysilicon layer over said IPO;patterning said second polysilicon layer to form a second electrode of said dual layer capacitor and a polysilicon resistor;depositing a capacitor protective oxide (CPO) over said dual layer capacitor and said polysilicon resistor;forming a CPO mask with a window over said FET device area and a region to protect said dual layer capacitor and said polysilicon resistor;etching said CPO and said IPO through said window to expose said FET device area;removing said CPO mask;depositing metal over said FET device area;performing silicidation of said metal over said FET device area;removing unreacted portions of said metal;depositing an interlevel dielectric; andperforming process steps to complete the fabrication of said mixed mode device.