Patent ID: 6665696
Filing Date: 2003-12-16
Classification: G06F,H03H

Abstract:
A method for implementing a one-clock-cycle-per-tap delayed adaptive least-mean-square filter in a programmable digital signal processor operating in clock cycles, the programmable digital signal processor including first and second multiply-accumulator units, the filter acquiring a new data sample each frame of a time sequence of frames, the method comprising for each clock cycle:reading a coefficient from a coefficient buffer; reading from a data buffer a first data sample corresponding to the coefficient; reading from the data buffer a second data sample acquired during the frame immediately preceding the frame in which the first data sample was acquired; reading an error term calculated during a previous frame from a buffer; multiplying the coefficient and the first data sample and accumulating the product in the first multiply-accumulate unit to form an output of a finite impulse response (FIR) filter; updating the coefficient by multiplying the second data sample and the error term, then adding to the coefficient the product of the second data sample and the error term, in the second multiply-accumulator; and writing the immediately preceding coefficient to the coefficient buffer.