Patent ID: 9007812
Filing Date: 2015-04-14
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a first cell array comprising first memory cells; a second cell array comprising second memory cells; first word lines electrically connected to only the first cell array between the first cell array and the second cell array; second word lines electrically connected to only the second cell array between the first cell array and the second cell array; a word line driver circuit electrically connected to the first word lines and to the second word lines; first bit lines electrically connected to only the first cell array between the first cell array and the second cell array; second bit lines electrically connected to only the second cell array between the first cell array and the second cell array; a first bit line driver circuit electrically connected to the first bit lines; and a second bit line driver circuit electrically connected to the second bit lines, wherein the first cell array and the second cell array overlap the first bit line driver circuit and the second bit line driver circuit, respectively, and wherein any one of the word line driver circuit, the first bit line driver circuit, and the second bit line driver circuit includes a transistor having a channel formation region in polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium.