Patent ID: 8108818
Filing Date: 2012-01-31
Classification: G06F

Abstract:
1. A method, performed by a processor executing non-transitory computer usable program code, for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net, comprising: calculating by the processer an off-path-point that represents all other off-path sinks in the net; projecting an intersect from the off-path-point to the source-to-sink path; estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of said all other off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay, wherein calculating a delay contribution based on delay of the source-to-sink path and delay of said art other off-path sinks comprises: calculating the delay contribution according to the formula