Patent ID: 7219205
Filing Date: 2007-05-15
Classification: G11C

Abstract:
1. A memory controller comprising: a first circuit to capture a first bit of data in response to a rising edge of a strobe signal; a second circuit to capture a second bit of data in response to a falling edge of the strobe signal; a first register circuit, coupled with the first circuit, to sample the first bit of data from the first circuit in response to a clock signal, the first register circuit being adjustable to select which transition of the clock signal is used to sample the first bit of data from the first circuit, wherein the first register circuit comprises: a second register circuit, coupled with the second circuit, to sample the second bit of data from the second circuit in response to the clock signal, the second register circuit being adjustable to select which transition of the clock signal is used to sample the second bit of data from the second circuit.