Patent ID: 7313649
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. A flash memory having a program verify function, comprising: a flash memory array including memory cells, a word line, and a bit line shared by memory cells neighboring each other in a direction of the word line; a write buffer functioning as a buffer for write data to the flash memory array; a neighbor cell buffer having a capacity which is larger than or equal to that of the write buffer; and a control circuit executing a program verify process with respect to the flash memory array, wherein the control circuit writes the input write data to the write buffer, the control circuit executes a logical operation based on the write data and data read from the flash memory array, and writes an obtained result as neighbor cell data to the neighbor cell buffer, the control circuit executes a verify process between the write data and the flash memory array and executes a verify process between the neighbor cell data and the flash memory array, and the control circuit applies a program pulse to a memory cell corresponding to a bit at which the verify process has failed.