Patent ID: 6711228
Filing Date: 2004-03-23
Classification: G11B,H03L

Abstract:
A multi-rate clock generator for generating clocks in accordance with a plurality of reproduced channel data rates, comprising:a reproduction means for reproducing recorded digital data at a plurality of channel data rates which are n/m (n and m are positive integers) of a predetermined basic channel rate; a clock generation means for generating a first clock corresponding to the basic frequency of the basic channel rate of which the oscillation frequency is variable; an n/m division means for n/m division of said first clock in accordance with the channel data rate of said reproduction means so as to output a second clock; an A/D conversion means for converting an input signal inputted from said reproduction means to a digital signal with said second clock; a phase error detection means for detecting a phase shift between the output of said A/D conversion means and said second clock based on the output of said A/D conversion means so as to output a phase error signal; and a digital filter means for processing said phase error signal with said second clock, wherein said clock generation means, said division means, said phase error detection means and said digital filter means form a PLL means by controlling the oscillation frequency of said clock generation means with the output signal of said digital filter means.