Patent ID: 6204129
Filing Date: 2001-03-20
Classification: H01L

Abstract:
A method for forming a semiconductor device, comprising:providing a substrate on which a high-voltage MOS and a low-voltage MOS transistor region are defined;forming a plurality of field oxides on said substrate, one of said field oxides being spaced from another of said field oxide by one of the MOS transistor regions;depositing a polysilicon layer over said high-voltage MOS and low-voltage MOS transistor regions;depositing a first dielectric layer over said polysilicon layer of said high-voltage MOS and low-voltage MOS transistor regions;forming a first photoresist layer over said first dielectric layer, wherein said first photoresist layer is defined and etched to form gates of high-voltage MOS and low-voltage MOS transistor;using a second photoresist layer as a mask above low-voltage MOS transistor regions, and firstly implanting the substrate of said high-voltage MOS transistor region to form first conductivity-type grade therein;removing said second photoresist layer of the low-voltage MOS transistor region;forming a plurality of spacers on sidewall of said gates of the high-voltage MOS and low-voltage MOS transistor;forming a second dielectric layer on said substrate of the high-voltage MOS and the low-voltage MOS transistor;forming a third photoresist layer having a first pattern on said the high-voltage MOS transistor and a second pattern on said low-voltage MOS transistor, wherein etching a portion of said first dielectric layer and said second dielectric layer is performed until top surface of said polysilicon layer and said grade is exposed by using said third photoresist layer as a hard mask;implanting second conductivity type ions inside said grade of high-voltage MOS transistor and inside the substrate of the low-voltage MOS transistor using said third photoresist layer as a mask;removing the third photoresist layer; andsputtering said exposed polysilicon layer and said grade to form silicide region.