Patent ID: 6121082
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A method for fabricating landing pads for DRAM cells, said method comprising the steps of:providing a semiconductor substrate, which are formed thereon with isolation regions separating periphery transistor region from a defined DRAM region, said defined DRAM region consisting of stack gates and sources/drain regions, said periphery transistor region, said isolation regions, and said DRAM region being overlay with a dielectric layer;patterning said first dielectric layer so that said defined DRAM region are exposed with said sources/drain regions, nitride caps of said stack gates and nitride spacers of said stack gates;forming a conductive layer on all resulting surfaces of said defined DRAM region, said isolation regions and said periphery transistor region;forming a photoresist pattern on said conductive layer of said defined DRAM region to define a plurality of photoresist openings over said each of nitride cap of said stack gates;forming a polymer layer on said photoresist pattern and said conductive layer of said periphery transistor region, said polymer layer being conformally formed on said photoresist openings so as to form a smaller polymer opening within each of said photoresist openings;performing an anisotropic polymer etching so that polymer spacers are formed in each of said photoresist opening and a portion of said polymer layer on said conductive layer of said periphery transistor region are removed;performing an anisotropic conductive layer etching using said polymer spacers as a mask and using said capping layer as a stopping layer so that said conductive layer are separated into a plurality of landing pads on said defined DRAM region.