Patent ID: 7409468
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. An apparatus comprising: a descriptor table—said apparatus for controlling flow of data between first and second data processing systems via a memory, said descriptor table for storing a plurality of descriptors for access by the first and second data processing systems, said first processing system comprises a plurality of host computer systems interconnected to a plurality of attached devices by an intervening network architecture, said network architecture comprises a plurality of data communications switches, said host computer system and the attached devices each forming a node in a data processing network, each host computer system comprising a plurality of central processing units and a memory interconnected by a PCI bus architecture; a network adapter also connected to the bus architecture for communicating data between the host computer system and other nodes in the data processing network via the network architecture; and descriptor logic for generating the descriptors for storage in the descriptor table, the descriptors including a branch descriptor comprising a link to another descriptor in the table, wherein: wherein the descriptors generated by the descriptor logic comprise a frame descriptor defining a data packet to be communicated between a location in the memory and the second data processing system, and a pointer descriptor identifying the location in the memory; wherein the memory is implemented by a combination of SRAM and SDRAM, said chip including a memory subsystem of the adapter comprises a first and a second memory, a data cache and an instruction cache associated with a TX processor, and a second data cache and second instruction cache associated with an RX processor, three levels of memory having respective sizes and associated access times, such that the memory subsystem facilitates: convenient access to instruction and data by both the TX processor and the RX processor; scaleability; and sharing of resources between the TX processor and the RX processor in the interests of reducing manufacturing costs, and wherein the descriptor table is stored in the memory of the first data processing system.