Patent ID: 6741257
Filing Date: 2004-05-25
Classification: G06F,G09G

Abstract:
A graphics engine comprising:a command first-in-first-out FIFO for storing entries written by a host, the entries being commands and data to the graphics engine from the host, the entries including a first entry that is an index value, and a plurality of data entries, the first entry being written to an address of the command FIFO; an index register, written with the index value from the first entry; a selector, coupled to the index register, for selecting a multi-bit mapping field from the index register, wherein the index value contains a plurality of multi-bit mapping fields each capable of indicating a different register in a bank of programmable registers; a decoder, coupled to receive the multi-bit mapping field selected by the selector from the index register, for decoding the multi-bit mapping field to indicate a selected register in the bank of programmable registers; and a switching bus, coupled to transfer one of the plurality of data entries from the command FIFO to the selected register to write a data value to the selected register; wherein the plurality of data entries from the command FIFO are written to several different selected registers in the bank of programmable registers by the selector selecting different multi-bit mapping fields from the index register and the decoder decoding different multi-bit mapping fields to cause the switching bus to write the data entries to the several different selected registers, whereby the multi-bit mapping fields in the index register are selected and decoded to write data values to the several different selected registers in the bank of programmable registers.