Patent ID: 6584531
Filing Date: 2003-06-24
Classification: G06F

Abstract:
A method of arbitrating access to a memory having a plurality of banks, the method comprising:(a) arbitrating with a plurality of processors, wherein each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle; (b) receiving any memory access requests from all of the data ports with the each of the processors, wherein each memory access request is associated with one of the memory banks; and (c) with each of the processors, selectively granting the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle, wherein selectively granting comprises defining a priority sequence through the plurality of data ports, whereby priority rotates from one of the data ports to a next subsequent one of the data ports in the sequence with each arbitration cycle.