Patent ID: 6445226
Filing Date: 2002-09-03
Classification: H03K

Abstract:
An output circuit comprising:a three-state buffer circuit having a pull-up side transistor and a pull-down side transistor connected in series between an external power supply potential and a grounding voltage; an output terminal connected to a node between the pull-up side transistor and the pull-down side transistor buffer circuit; a first level shift circuitry connected to a gate of the pull-up side transistor, the first level shift circuitry converting a voltage of an input signal from an internal power supply potential lower than the external power supply potential to the external power supply potential; a second level shift circuitry connected to a gate of the pull-down side transistor, the second level shift circuitry converting a voltage of a data signal from the internal power supply potential to the external power supply potential; a signal change detecting circuit for detecting a change of the input signal; and a delay circuitry for delaying an output signal of this signal change detecting circuit to output to the first and second level shift circuitry a signal for controlling an output of an output circuit to be active or inactive, wherein, when the control signal is in a first state, either one of the pull-up side transistor and pull-down side transistor is turned OFF, causing the output terminal to enter a high impedance, and when the control signal is in a second state, a signal according to â€œhighâ€  or â€œlowâ€  of the data signal is outputted to the output terminal.