Patent ID: 6370557
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A processing apparatus for calculating â€œ(Aâˆ’B)Ã—Câ€  where the bit data A is constituted by the n-bit data of Ai (i=0, 1, . . . nâˆ’1), the bit data B is constituted by the n-bit data of Bi (i=0, 1, . . . nâˆ’1), and the bit data C is constituted by the n-bit data of Cj (j=0, 1, . . . nâˆ’1), said processing apparatus comprising:a bit data selecting means for receiving as input the bit data Ai, Bi, and Cj, and outputting the bit data Ai when Cj equals to a first logical value or the bit data Bi when data Cj equals to a second logical value in response to data Cj with respect to all combinations of the natural numbers i and j; and, an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.