Patent ID: 8719532
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A data controlling method performed in a memory apparatus, the method comprising: receiving, by a first buffer and a second buffer, a control signal output from a main controller, the control signal comprising an address of a source memory among a plurality of first non-volatile memories that share a first local bus and an address of a target memory among a plurality of second non-volatile memories that share a second local bus, the first buffer connected to the first local bus, the second buffer connected to the second local bus; buffering, by the first buffer, data stored in the source memory among the plurality of first non-volatile memories via the first local bus according to the control signal; and transmitting, by the first buffer, the buffered data to the target memory over a data bus shared by the main controller, the first buffer, and the second buffer, wherein the first local bus is connected to all the first non-volatile memories and a first sub-controller within a first memory module, and the first sub-controller is for controlling the first non-volatile memories; wherein the second local bus is connected to all the second non-volatile memories and a second sub-controller within a second memory module, and the second sub-controller is for controlling the second non-volatile memories.