Patent ID: 8785247
Filing Date: 2014-07-22
Classification: B81B,H01L

Abstract:
1. A method for forming a chip package, comprising: providing a substrate having a first surface and a second surface, wherein a plurality of device regions are formed in the substrate, and the device regions are separated from each other by a plurality of predetermined scribe lines; forming a passivation layer on the first surface of the substrate; forming a polymer planar layer on the passivation layer; patterning the polymer planar layer to form a plurality of patterned polymer planar layers, wherein the patterned polymer planar layers are located on a corresponding one of the device regions, respectively; disposing a package substrate on the first surface of the substrate; disposing a spacer layer between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a plurality of cavities on the substrate, and each of the patterned polymer planar layers does not extends to any one of the predetermined scribe lines, respectively; and dicing the substrate and the package substrate along the predetermined scribe lines to form a plurality of separate chip packages.