Patent ID: 6091625
Filing Date: 2000-07-18
Classification: G11C

Abstract:
An integrated memory, comprising:a cell array having bit lines and word lines;writable memory cells disposed in said cell array;a data line pair;a first differential sense amplifier having connections connected to said data line pair, said first differential sense amplifier reading information from one of said memory cells over said data line pair during a read access operation in order to amplify the information subsequently, and said first sense amplifier writing information to one of said memory cells over said data line pair during a write access operation, said data line pair transferring the information as differential signals, and said first sense amplifier temporarily storing the information during every write access operation;a switching unit having a switching state, said switching unit connecting said data line pair to said connections of said first sense amplifier, for interchanging lines of said data line pair in relation to said connections of said first sense amplifier depending on said switching state of said switching unit; andsaid switching state of said switching unit changing at least once during said write access operation, so that the information to be written is written to a relevant one of said memory cells by said first sense amplifier initially in noninverted form and then in inverted form.