Patent ID: 6646950
Filing Date: 2003-11-11
Classification: G11C

Abstract:
Addressing circuitry for a flash memory laid out in an array of memory blocks and powered by a power supply having a power supply voltage and a ground voltage, each block comprising an array of core cells, and each row of core cells being addressed by a respective local word line, the flash memory having an external address input and an address transition detection signal which pulses in response to a change of value at the external address input, said addressing circuitry comprising:a source of boost voltage being at the power supply voltage during a pulse of the address transition detection signal and rising to a boost voltage from the power supply voltage following a pulse of the address transition detection signal; a global xdecoder that receives the power supply voltage, the source of boost voltage, the ground voltage, and the address transition detection signal, and that drives a pair of positive and negative global word lines; a vertical xdecoder that receives the power supply voltage, the source of boost voltage, the ground voltage, and the address transition detection signal, and that drives a plurality of vertical word lines; and a local word line driver that drives a respective local word line to address a respective row of core cells, the local word line driver having a first n-channel transistor and a second n-channel transistor and receiving a respective vertical word line as an input, the first n-channel transistor having a drain terminal coupled to the respective vertical word line, a gate terminal coupled to the positive global word line, and a source terminal coupled to the respective local word line, the second n-channel transistor having a drain terminal coupled to the respective local word line, a gate terminal coupled to the negative global word line, and a source terminal coupled to the ground voltage; wherein, when the row of core cells is addressed in response to a pulse of the address transition detection signal, said global xdecoder forces the negative global word line toward the power supply voltage during said pulse so that the respective local word line is pulled toward the ground voltage by the second n-channel transistor, and thereafter in response to the end of said pulse said global xdecoder forces the positive and negative global word lines toward the boost voltage and ground voltage, respectively, causing the voltage on the gate terminal of the first n-channel transistor to be raised and causing the respective local word line to be decoupled from the ground voltage, and wherein said vertical xdecoder is responsive to the end of said pulse of the address transition detection signal and forces the respective vertical word line toward the boost voltage after a delay period from the end of said pulse, thereby raising the voltages of the drain terminal of the first n-channel transistor and the respective local word line and boosting the gate voltage of the first n-channel transistor.