Patent ID: 6493251
Filing Date: 2002-12-10
Classification: G11C

Abstract:
A ferroelectric memory device comprising:a memory cell array including: a plurality of unit cells each having a cell transistor and a ferroelectric capacitor, a source and a drain of the cell transistor being connected to both ends of the ferroelectric capacitor, and a gate of the cell transistor being connected to a word line; and a plurality of cell blocks each having a first terminal, a second terminal, and the unit cells series-connected between said first terminal and said second-terminal, said first terminal being connected to a bit line via a block selecting transistor, and said second terminal being connected to a plate line; a sense amplifier for sensing and amplifying a signal read from the ferroelectric capacitor of the unit cell to the bit line; a plate line driving circuit for driving the plate line; and an offset voltage applying circuit for, when data is read and before said sense amplifier is activated, applying to said bit line different offset voltages in accordance with positions of the selected unit cells in the cell block, wherein said offset voltage applying circuit applies a higher offset voltage to the bit line, to which a selected unit cell is connected, when said selected unit cell is more distant from the bit line than a predetermined unit cell.