Patent ID: 7519934
Filing Date: 2009-04-14
Classification: G06F

Abstract:
1. A computer implemented method for designing a semiconductor integrated circuit, comprising: extracting through wiring tracks that linearly pass through horizontally each of area priority cells, which are included in a first layout data and designed to reduce the area thereof, and yield priority cells designed to increase yield from horizontal wiring tracks; generating second layout data from the first layout data by replacing the area priority cells with the yield priority cells; investigating an overlap between the yield priority cell which replaced the area priority cell and a cell adjacent to the yield priority cell; moving at least one of the yield priority cells and an adjacent cell to resolve the overlap when the overlap occurs; and calculating a ratio of a number of intersections between the horizontal wiring tracks and vertical wiring tracks at which through wiring cannot be laid to a number of all of the intersections defined in semiconductor integrated circuit, based on the second layout data and information of the through wiring tracks, the through wiring linearly passing through the yield priority cell and the area priority cell without overlapping a terminal region that electrically connects any of the yield priority cell and the area priority cell to wirings; wherein the ratio is provided for storage or output.