Patent ID: 6074916
Filing Date: 2000-06-13
Classification: G11C,H01L

Abstract:
A fabrication process for an integrated circuit according to a CMOS technology for low power consumption applications, the integrated circuit comprising a first array of floating gate FLASH-EPROM memory cells and at least a second array of floating gate EEPROM memory cells, the method comprising the steps of:forming a first dielectric layer of gate oxide of independently optimized thickness onto active areas for the FLASH-EPROM memory cells;depositing, doping, masking and patterning a polysilicon layer of a first level defining floating gates of said FLASH-EPROM memory cells and control gates of said EEPROM memory cells in a first direction, the control gates of said EEPROM memory cells being above a field oxide adjacent to the active areas thereof;forming a dielectric layer of interpoly isolation;removing said dielectric layer of interpoly isolation and polysilicon of the first level in areas external to said first and second arrays;forming a pre-layer of gate oxide in the active areas of said EEPROM memory cells and of first transistors of a circuit external to said first and second arrays destined to function at a relatively high voltage;defining a tunneling window in the active area of each EEPROM memory cell and removing said pre-layer of gate oxide therefrom;growing a tunnel oxide layer in said tunneling window and simultaneously incrementing a thickness of said pre-layer of gate oxide and forming a gate oxide layer in the active areas of second transistors of a circuit external to said first and second arrays destined to function at a relatively low voltage;depositing, doping, masking and patterning a polysilicon layer of a second level defining floating and select gates of said EEPROM memory cells, the control gates of said FLASH-EPROM memory cells and the gates of said transistors of the external circuit;masking and etching, in self-alignment to the control gates, said layer of polysilicon of first level for completing definition of the floating gates of said FLASH-EPROM memory cells; andperforming an additional masking and implantation step, in a zone of the active area of said EEPROM memory cells including said tunnel window, before forming said first dielectric layer of gate oxide.