Patent ID: 8248867
Filing Date: 2012-08-21
Classification: G11C

Abstract:
1. A memory array system having a plurality of memory cells each being connected to a read word line and a write word line and peripheral circuits for reading and writing to the plurality of memory cells, each memory cell comprising: A. a storage element for storing a logical state of the memory cell powered at a reduced voltage during functional operations and during stand-by mode; B. a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array, the read access circuit being enabled and configured to read the logic state of the storage element in response to a read signal on the read word line; and C. a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell wherein the reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell, the reduced voltage is determined by a difference between an array source supply voltage (VDDAR) and an array sink supply voltage (VSSAR) and the peripheral voltage is determined by a difference between a peripheral source supply voltage (VDDP) and a peripheral sink supply voltage (VSSP) and the read access circuit is supplied by a read sink supply voltage (VSSRD).