Patent ID: 7541234
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. A method of fabricating integrated circuit transistors comprising: forming on an integrated circuit substrate, a first active area including a first insulated gate thereon and a second active area including a second insulated gate thereon; sequentially blanket forming on both the first and second active areas, a nitride stress-generating layer, a carbon-containing layer, an etch stop layer and a photoresist layer; selectively removing the photoresist layer from the etch stop layer on the second active area to expose the etch stop layer on the second active area while retaining at least some of the photoresist layer on the etch stop layer on the first active area; removing the etch stop layer that is exposed on the second active area; etching the photoresist layer on the first active area to expose the etch stop layer on the first active area while simultaneously etching the carbon-containing layer on the second active area to expose the nitride stress-generating layer on the second active area; removing the etch stop layer that is exposed on the first active area to expose the carbon-containing layer on the first active area; removing the nitride stress-generating layer that is exposed on the second active area; implanting dopants into the second active area to form source/drain regions in the second active area while simultaneously blocking implantation of the dopants into the nitride stress-generating layer on the first active area by the carbon-containing layer on the first active area; removing the carbon-containing layer from the nitride stress-generating layer on the first active area; annealing to memorize stress in the first active area that is generated by the nitride stress-generating layer thereon; and removing the nitride stress-generating layer from the first active area.