Patent ID: 7642841
Filing Date: 2010-01-05
Classification: H03F

Abstract:
1. A voltage-insensitive bias circuit, comprising: a first bipolar transistor comprising a first base, a first collector and a first emitter, the first base being connected to a first reference node, the first collector being connected to a power voltage node, the first emitter providing a first bias output to a second circuit, the first bias output being appreciably insensitive to voltage fluctuations of the voltage power node; a reference resistor connected between the power voltage node and the first reference node; and a second bipolar transistor comprising a second base, a second collector and a second emitter, the second base being connected to the first reference node, the second emitter being coupled to a ground node via a first diode, the second collector being coupled to a third bipolar transistor, the third bipolar transistor comprising a third base, a third collector and a third emitter, the third emitter being coupled to ground via a third resistor, the third collector being coupled to the power voltage node via a fourth resistor and to the second collector via a fifth resistor.