Patent ID: 6188269
Filing Date: 2001-02-13
Classification: G05F

Abstract:
A circuit that generates a bias voltage for an output stage having an idling point at which an idling current is produced when an input signal equals a DC voltage and a bias input equals said bias voltage, comprising:a first current source that produces a first current which is proportional to said idling current;a transistor that passes a first current amount that includes at least a portion of said first current, that controls said first current amount being passed in response to an input voltage, and that passes said first current amount equal to said first current when said input voltage is equal to said DC voltage;a current mirror that has a current mirror output which passes a second current amount including at least a portion of a second current, and that controls said second current amount being passed in response to a subcircuit current;a second current source that produces said second current which is proportional to said idling current and that causes said input voltage to change in response to said second current amount being passed by said current mirror; anda complementary subcircuit that has a first input that is controlled by said input voltage, a second input that is responsive to whether said transistor is passing said first current amount equal to said first current, and an output that produces said subcircuit current in an amount that is responsive to said first input and said second input of said subcircuit, such that when said subcircuit produces said subcircuit current that causes said current mirror to pass said second current amount equal to said second current and said input voltage equals said DC voltage, said bias voltage is present at said second input.