Patent ID: 9213487
Filing Date: 2015-12-15
Classification: G06F,G11C,Y02D

Abstract:
1. A memory interface, comprising: a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels; a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels; and a plurality of flip-flops located in close proximity to the plurality of receivers, wherein each of the flip-flops is configured to capture data from an output of a respective one of the plurality of receivers; wherein the plurality of receivers and the plurality of flip-flops are all grouped together into a receiver subsystem that is located away from the plurality of transmitters, the plurality of transmitters span a first distance, the receiver subsystem spans a second distance, and the first distance is at least five times longer than the second distance.