Patent ID: 7071756
Filing Date: 2006-07-04
Classification: G06F,H03K

Abstract:
1. A clock control circuit in an integrated circuit for providing a clock signal to a clock tree, comprising: a first plurality of multiplexers configured to select a first plurality of outputs from input clock signals; a second plurality of multiplexers coupled to the first plurality of multiplexers and configured to select a second plurality of outputs from the first plurality of outputs; a plurality of loop back signal lines configured to feed back the second plurality of outputs to at least part of the input clock signals of the first plurality of multiplexers; a plurality of signal lines of the clock tree coupled to the second plurality of outputs; and a plurality of current driver circuits coupled between the second plurality of outputs and the plurality of signal lines of the clock tree, wherein the signal lines of the clock tree are differential signal lines, and wherein the plurality of current driver circuits are configured to convert rail-to-rail differential signals to small signal differential signals.