Patent ID: 6480874
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A power saving adding and subtracting unit for adding and subtracting a constant from an operand, the power saving adding and subtracting unit is adapted to receive the operand and the constant and perform a selected operation out of adding operation and subtracting operation, the power saving adding and subtracting unit comprising:a detect and invert logic, for receiving a first portion of the operand; checking whether the selected operation can be performed by inverting at least one bit of the first portion of the operand, responsive to the constant; wherein if the answer is YES, disabling the multi-bit adder and subtractor and generating a first portion of a result by inverting at least one bit of the portion of the operand, responsive to the constant; a multi-bit adder and subtractor unit for generating a second result by performing the selected operation; and a selection means for selecting the second result when the adder and subtractor is enabled, and for selecting a first result comprising from a second portion of the operand that was not sent to the detect and invert logic and the first portion of the first result when the selected operation is performed by inverting at least one bit of the first portion of the operand responsive to the constant.