Patent ID: 8991043
Filing Date: 2015-03-31
Classification: H05K,Y10T

Abstract:
1. A manufacturing method of a circuit board structure, comprising: compressing a first dielectric layer and a first copper foil layer located on the first dielectric layer onto a first patterned circuit layer of a core circuit structure, and compressing a second dielectric layer and a second copper foil layer located on the second dielectric layer onto a second patterned circuit layer of the core circuit structure, wherein the first patterned circuit layer and the second patterned circuit layer are respectively located on two opposite sides of the core circuit structure; forming at least one first blind via extending from the first copper foil layer to the first patterned circuit layer, and forming at least one second blind via extending from the second copper foil layer to the second patterned circuit layer, wherein the first blind via and the second blind via respectively expose parts of the first patterned circuit layer and the second patterned circuit layer; forming a first plating seed layer on the first copper foil layer and in the first blind via, and forming a second plating seed layer on the second copper foil layer and in the second blind via, wherein the first plating seed layer and the second plating seed layer respectively cover an inner wall of the first blind via and an inner wall of the second blind via; forming a first conductive blind via structure and a second conductive blind via structure in the first blind via and the second blind via respectively, wherein the first conductive blind via structure and the second conductive blind via structure are respectively aligned with the first plating seed layer located on the first copper foil layer and the second plating seed layer located on the second copper foil layer; forming a third patterned circuit layer and a fourth patterned circuit layer on the first plating seed layer and the second plating seed layer respectively, wherein the third patterned circuit layer and the fourth patterned circuit layer are electrically connected to the first patterned circuit layer and the second patterned circuit layer respectively through the first conductive blind via structure and the second conductive blind via structure; forming a first surface passivation layer and a second surface passivation layer on the third patterned circuit layer and the fourth patterned circuit layer respectively; using the first surface passivation layer and the second surface passivation layer as an etching mask to remove a part of the first plating seed layer and a part of the first copper foil layer below the first plating seed layer and a part of the second plating seed layer and a part of the second copper foil layer below the second plating seed layer that are exposed out of the third patterned circuit layer and the fourth patterned circuit layer, to expose the first dielectric layer and the second dielectric layer; and removing a part of the first surface passivation layer and a part of the second surface passivation layer, to expose a part of the third patterned circuit layer and a part of the fourth patterned circuit layer.