Patent ID: 8605485
Filing Date: 2013-12-10
Classification: G11C

Abstract:
1. A non-volatile semiconductor storage device comprising: a plurality of first lines; a plurality of second lines that intersect the plurality of first lines; a plurality of non-volatile memory cells arranged at positions where the plurality of first lines and the plurality of second lines intersect; and a control unit that controls the plurality of non-volatile memory cells through the plurality of first lines and the plurality of second lines; wherein a variable resistor element and a rectifier element are connected in series in each of the plurality of non-volatile memory cells; and the control unit multiple-selects first lines for every N lines from the plurality of first lines, N being an integer greater than or equal to one, and sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing, makes the multiple-selected first lines be in a floating state at a second timing after the first timing, and selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing, wherein at the first timing, among the plurality of first lines, the control unit collectively fixes potentials of the non-selected first lines adjacent to the multiple-selected first lines to the non-selection potential, and does not fix potentials of the non-selected first lines not adjacent to the multiple-selected first lines.