Patent ID: 6867118
Filing Date: 2005-03-15
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor memory including a semiconductor substrate having a memory region and a logic region isolated from each other by an isolation insulating film, a plurality of memory transistors provided in the form of a matrix in said memory region of said semiconductor substrate and a logic transistor provided in said logic region, comprising the steps of: forming, in said memory region, impurity diffusion layers working as source and drain regions of some memory transistors arranged along a bit line direction out of said plurality of memory transistors as a common impurity diffusion layer extending along the bit line direction; forming a memory gate insulating film in said memory region and a logic gate insulating film in said logic region; depositing a silicon-containing film on said memory gate insulating film and said logic gate insulating film; patterning said silicon-containing film in said memory region, whereby forming gate electrodes of some memory transistors arranged along a word line direction out of said plurality of memory transistors as a common gate electrode extending along the word line direction, and patterning said silicon-containing film in said logic region, whereby forming a gate electrode of said logic transistor; forming a sidewall insulating film on a side face of said gate electrode of said logic transistor; forming, in said logic region, impurity diffusion layers working as source and drain regions of said logic transistor; forming a first insulating film in said memory region and said logic region and forming a second insulating film directly on said first insulating film from a different material from said first insulating film; successively etching said second insulating film and said first insulating film in said memory region, whereby exposing top faces of said gate electrodes of said plurality of memory transistors and whereby forming, from said first insulating film, an inter-gate insulating film having a top face at a level lower than a top face of said gate electrodes between adjacent gate electrodes of said plurality of memory transistors; successively etching said second insulating film and said first insulating film in said logic region, whereby exposing top faces of said gate electrode and said impurity diffusion layers of said logic transistor; and forming a silicide layer on said gate electrodes of said plurality of memory transistors, on said gate electrode of said logic transistor and on portions of top faces, exposed from said sidewall insulating film, of said impurity diffusion layers of said logic transistor.