Patent ID: 9088271
Filing Date: 2015-07-21
Classification: H03K

Abstract:
1. A dual-port positive level sensitive data retention latch comprising: a first clocked inverter configured to receive a first data bit (D a dual-port latch configured to receive the data output (QN) of the first clocked inverter, a second data bit (D wherein the dual-port latch comprises: a first tri-state inverter, the first tri-state inverter having a data input, a first control input, a second control input and a data output wherein the data input of the first tri-state inverter is electrically connected to the data output (QN), the first control input of the first tri-state inventer is electrically connected to the first latch control signal (SS), and the second control input of the first tri-state inverter is connected to the second latch control signal (SSN); a second tri-state inverter, the second tri-state inverter having a data input, a first control input, a second control input and a data output wherein the data input of the second tri-state inverter is electrically connected to the second data bit (D a second clocked inverter, the second clocked inverter having a data input, a first control input, a second control input, a third control input and a data output wherein the data input of the second clocked inverter is electrically connected to the data outputs of the first and second tri-state inverters, the first control input of the second clocked inverter is electrically connected to the first clock signal (CKT), the second control input of the second clocked inverter is connected to the second clock signal (CLKZ), the third control input of the second clocked inverter is electrically connected to the retention mode control signal (RET), and the output of the second clocked inverter is electrically connected to the input of the first tri-state inverter.