Patent ID: 8037376
Filing Date: 2011-10-11
Classification: G11C

Abstract:
1. An on-chip failure analysis circuit for analyzing a memory, the circuit comprising: a built-in self test unit configured to test the memory; a failure detection unit configured to detect a failure of memory output of the memory; a fail data storage unit configured to store fail data comprising location of the failure; a repair analysis circuit configured to analyze necessity of redundancy allocation and redundancy allocation result, based on the numbers of spare columns and spare rows of the memory, to generate the fail data to be written in the fail data storage unit, the fail data comprising the redundancy allocation result; a fault diagnosis circuit configured to make a determination of a type of the failure emerging on the memory or a combination of the types of the failures according to the number of failures and an upper limit of the number of failures to write the fail data comprising the determination result in the fail data storage unit; and an analysis result output unit configured to output the redundancy allocation result.