Patent ID: 9166622
Filing Date: 2015-10-20
Classification: G06F,H03M

Abstract:
1. A system, comprising: a first interleaver memory, the first interleaver memory configured for receiving a plurality of user bits, the first interleaver memory further configured for interleaving a first set of user bits included in the plurality of user bits, the first interleaver memory further configured for outputting the interleaved user bits, the first interleaver memory further configured for outputting a second set of user bits included in the plurality of user bits; an encoder, the encoder configured for being communicatively coupled with the first interleaver memory, the encoder further configured for being communicatively coupled with a second interleaver memory, the encoder further configured for receiving the interleaved user bits, the encoder further configured with a plurality of barrel shifter circuits, the plurality of barrel shifter circuits configured for generating parity bits based on the received interleaved user bits, the encoder further configured for directing the parity bits to the second interleaver memory, the second interleaver memory configured for interleaving the parity bits and for outputting the interleaved parity bits; and a multiplexer, the multiplexer configured for being communicatively coupled with the first interleaver memory, the multiplexer further configured for being communicatively coupled with the encoder, the multiplexer further configured for receiving the second set of user bits output from the first interleaver memory, the multiplexer further configured for receiving the interleaved parity bits output from the second interleaver memory, the multiplexer further configured for multiplexing the interleaved parity bits and the second set of user bits to form a multiplexer output, the multiplexer further configured for writing the multiplexer output to a storage means.