Patent ID: 7337372
Filing Date: 2008-02-26
Classification: G06F,Y02D

Abstract:
1. A processor comprising: a cache having a plurality of hit lines; and a selector to provide a data during a clock cycle from a plurality of memory locations associated with the plurality of hit lines in the cache; a multi-hit detection circuit coupled to the hit lines to detect multiple hits in the cache during the clock cycle based on hit signals on the hit lines, the multi-hit detection circuit comprising a NAND gate having pull-down transistor pairs coupled to the hit lines to pull an output node of the NAND gate low if two different hit signals include a hit; and an error flag generated by an inverter output coupled to the output node of the NAND gate in the multi-hit detection circuit during the clock cycle, the error flag to indicate that the data provided during the clock cycle is invalid if multiple cache hits are detected, the error flag to indicate that the data provided during the clock cycle is valid if a single cache hit is detected.