Patent ID: 6314536
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A memory testing apparatus in which a test pattern signal is applied to a memory under test from a pattern generator, a response output from the memory under test is compared with an expected value pattern from the pattern generator in a logical comparator, every time the comparison result indicates a disaccord, a failure data is stored in a failure memory,said memory testing apparatus further comprising:a burst address producing circuit for outputting two address signals in one test period by computing operation using an address signal first supplied to the burst address producing circuit from the pattern generator, in the case that a memory under test operates in burst mode and adopts double data rate system, and supplying them to the failure memory as burst address signals, said two address signals generated in one test period being address signals in the first half and in the latter half of the one test period respectively and being different from each other.