Patent ID: 6525360
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A semiconductor device comprising:an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed; a gate electrode wiring; a bit line; and element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line, the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor, and the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring in a top view.