Patent ID: 6566202
Filing Date: 2003-05-20
Classification: H01L

Abstract:
A method for manufacturing an integrated circuit formed in a substrate of semiconductor material wherein the integrated circuit includes at least two vertical MOS transistors, the method comprising the steps of:forming an insulating layer of insulating material on a surface of the substrate; applying a conductive layer over the insulating layer; forming at least one trench in the substrate wherein the insulating layer and the conductive layer are correspondingly structured; forming a gate dielectric at first and second sidewalls of the trench; providing an insulating material along a floor of the trench; forming a first source/drain region of a first MOS transistor along an upper region of the first sidewall of the trench; forming a first source/drain region of a second MOS transistor along an upper region of the second sidewall of the trench wherein the first source/drain region of the second MOS transistor lies opposite the first source/drain region of the first MOS transistor; forming a second source/drain region as part of both the first MOS transistor and the second MOS transistor wherein the second source/drain region adjoins the floor of the trench; forming a first gate electrode of the first MOS transistor along the first sidewall of the trench; and forming a second gate electrode of the second MOS transistor along the second sidewall of the trench, wherein the second and first gate electrodes are not electrically connected and respectively contact parts of the conductive layer.