Patent ID: 7092279
Filing Date: 2006-08-15
Classification: G11C,H01L

Abstract:
1. A memory, having N ports, comprising: an array of plural bit-cells organized as plural columns and plural rows; plural word-lines aligned with said plural rows, each of said plural word-lines electrically coupled to a discrete fraction of all of that portion of said plural bit-cells that lie along the corresponding one of said plural rows, and wherein each of said plural rows has N times the inverse of said fraction of said plural word-lines aligned therewith; plural bit-lines aligned with said plural columns, each of said plural bit-lines electrically coupled to all of that portion of said plural bit-cells that lie along at least a single corresponding one of said plural columns; wherein at least a first one of said plural bit-lines is electrically coupled to all of said plural bit-cells that lie along an integer multiple of N number of said plural columns, and coupled such that every one of said plural bit-cells, that lie along any given row of said plural bit-cells that are coupled to said first bit-line, is coupled to N unique ones of said plural word-lines, and plural conductive elements aligned in parallel with said plural bit-lines along a substantial portion of the length of said plural bit lines, said plural conductive elements interspersed with said plural bit lines such that no two of said plural bit lines that are simultaneously accessed during a memory read or write operation are adjacent to one another over a substantial portion of their respective lengths.