Patent ID: 6074567
Filing Date: 2000-06-13
Classification: H01L,H05K,Y10S

Abstract:
A method for producing a semiconductor package comprising a laminate of a plurality of resinous substrates having a cavity for accommodating a semiconductor element, through-holes and circuit patterns; the through-holes and some of the circuit patterns being coated with a plated nickel/gold coating; said method comprising the following steps of:(a) a step for producing an inner circuit board, wherein a resinous substrate clad with a metallic foil is bored to have an opening for forming the cavity and subjected to an etching treatment to form inner circuit patterns on the surface thereof;(b) a step for forming the laminate by sandwiching a plurality of the inner circuit boards between a pair of outer circuit boards having no opening, thereby forming a sealed cavity;(c) a first plating step including first forming bores for the through-holes and then applying a plated copper coating to the inner wall of the through-hole and the metallic foil covering the outer surface of the outer circuit board;(d) a step for applying a plated nickel coating to at least the through-holes;(e) a step for forming outer circuit patterns on the outer surface of the outer circuit board by etching the metallic foil and the plated copper coating on the outer surface of the outer circuit board;(f) a step for opening the cavity by providing an opening in at least one of the outer circuit boards corresponding to the opening of the inner circuit board; and(g) a second plating step for applying a plated nickel coating and a plated gold coating to the inner circuit patterns, the through-holes, and the outer circuit patterns.