Patent ID: 6160807
Filing Date: 2000-12-12
Classification: H04Q

Abstract:
A time slot interchange having a time division multiplexed signal input port and a time division multiplexed signal output port, for interchanging time division multiplexed data channels, comprising:a data channel memory, coupled to the time division multiplexed signal input port;a channel circuit, having a write address output, the write address output connected to the data channel memory;a signal processing circuit, having a channel input coupled to the data channel memory, a gain input, and an output coupled to the time division multiplexed signal output port; anda connection memory, including a unique read channel field comprising a read address portion and a gain value portion for each data channel to be output by the time slot interchange network, the connection memory having an input connected to the write address output of the channel circuit, a read address output connected to the data channel memory, and a gain value output connected to the gain input of the signal processing circuit.