Patent ID: 6175520
Filing Date: 2001-01-16
Classification: H03M

Abstract:
A non-volatile memory device, comprisinga plurality of memory cell arrays, each memory cell array including a plurality of electrically programmable non-volatile memory cells arranged in rows and columns, each memory cell having a terminal for receiving a programming voltage in a programming mode to place the non-volatile memory in a first state, the terminals of memory cells in the same column within an array being commonly coupled to at least one bit line;a selector associated with each array, each said selector coupling a bit line of its associated array to a data line;a primary voltage supply circuit for selectively providing the programming voltage to the data line in the programming mode;at least one secondary voltage supply circuit associated with the data line, the secondary voltage supply circuit providing the programming voltage to the data line in conjunction with said primary voltage supply circuit providing the programming voltage to the data line.