Patent ID: 6577146
Filing Date: 2003-06-10
Classification: G01R

Abstract:
A method of burning-in at least one I/C chip package in a test fixture which has a socket to receive at least one I/C chip package and a heat sink relatively movable into and out of contact with said I/C chip package, and a power source to provide power to said at least one I/C chip package and wherein the I/C chip package has a maximum power supplied during testing and a maximum temperature to which the chip can be heated during testing, comprising the steps of: determining the maximum allowable thermal resistance (TR) of an interface between the I/C chip package and the heat sink at said maximum power Level and said maximum temperature value; contacting the I/C chip package with said heat sink to create a thermal interface; applying power (w) to said I/C chip package at a known level below said maximum power level; measuring the temperature of said chip (TC) and the temperature of said heat sink (THS) and from said known level of power (w) and the measured chip temperature (TC) and the measured temperature of said heat sink (THS), calculating the actual thermal resistance (TR) of said interface; and continuing said burn-in if and only if said actual thermal resistance of said interface is equal to or less than said maximum allowable thermal resistance of said interface at each chip heat sink interface.