Patent ID: 6773978
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method of fabricating a transistor gate in a semiconductor device, comprising:forming a gate oxide layer over a channel region of a substrate; forming and pattering a polysilicon gate over the channel region, the polysilicon gate extending between a bottom surface overlying the gate oxide and a top surface; forming a metal layer over the substrate, at least a portion of the metal layer overlying the top surface of the polysilicon gate, wherein the metal layer does not contact a source/drain region associated with the device; and performing a single anneal to react the polysilicon with the portion of the metal layer to form a conductive second phase metal silicide gate extending from the bottom surface to the top surface, wherein forming the metal layer comprises forming a cobalt layer overlying the top surface of the polysilicon gate, and wherein forming the cobalt layer comprises depositing cobalt over the top surface of the polysilicon gate to a thickness of about 250 Ã¥ or more and about 350 Ã¥ or less, and wherein performing the anneal comprises performing the rapid thermal anneal at a temperature of about 700 degrees C. in an atmosphere comprising N2 for about 10 seconds or more and about 60 seconds or less to provide a substantially uniform work function at the bottom surface of the gate, and further comprising covering a portion of the substrate overlying at least one source/drain region prior to forming the cobalt layer to prevent silicidation of the covered portion of the substrate while performing the anneal.