Patent ID: 7602657
Filing Date: 2009-10-13
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory cell and a second memory cell each of which includes an electrically floating body region and stores data in accordance with the number of majority carriers in the body region, the first memory cell and the second memory cell storing data with opposite polarities; a first isolation transistor which has one terminal serving as a first node connected to the first memory cell and the other terminal serving as a second node; a second isolation transistor which has one terminal serving as a third node connected to the second memory cell and the other terminal serving as a fourth node; a first amplification transistor of a first conductivity type, which has one terminal connected to the first node and a gate electrode connected to the third node; a second amplification transistor of the first conductivity type, which has one terminal connected to the third node, the other terminal connected to the other terminal of the first amplification transistor, and a gate electrode connected to the first node; a third amplification transistor of a second conductivity type, which has one terminal connected to the second node and a gate electrode connected to the fourth node; a fourth amplification transistor of the second conductivity type, which has one terminal connected to the fourth node, the other terminal connected to the other terminal of the third amplification transistor, and a gate electrode connected to the second node; and an equalizing transistor which is connected between the first node and the third node.