Patent ID: 8581325
Filing Date: 2013-11-12
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate; a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions; a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively; a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of insulator films formed on the bottom and the side walls of the plurality of trenches; a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layers along the second direction in a stripe shape; a plurality of air gaps formed between the plurality of insulator films filled in the plurality of trenches and the plurality of inter poly insulator films; and a plurality of control gate electrodes formed on the plurality of inter poly insulator films, wherein an upper surface of the plurality of insulator films is directly contacted to the plurality of inter poly insulator films, and an upper border of the plurality of air gaps is located at a lower position than the upper surface of the plurality of the charge accumulation layers and at a higher position than the upper surface of the plurality of the tunnel insulator films.