Patent ID: 6333866
Filing Date: 2001-12-25
Classification: G11C,H01L

Abstract:
A semiconductor device, comprising:a plurality of like unit circuits formed in a semiconductor substrate;a plurality amplifier circuits arranged into at least a group of first amplifier circuits and a group of second amplifier circuits, each amplifier circuit having a first input and a second input;a plurality of higher order conductive segments, includinga plurality of first higher order conductive segments arranged in series between the first input of one of the first amplifier circuits and the first input of an associated second amplifier circuit, anda second higher order conductive segment associated with each first higher order conductive segment, the second higher order conductive segments being arranged in series between the second input of the first amplifier circuit and the second input of the associated second amplifier circuit,a plurality of lower order conductive segments coupled to the unit circuits, the lower order conductive segments being arranged into lower group pairs, each lower group pair includinga plurality of first lower order conductive segments, anda plurality of second lower order conductive segments;a plurality of reconnector circuits, each disposed between two first higher order conductive segments and two associated second higher order conductive segments, each reconnector circuit includinga first reconnector controllable impedance path coupled between the two first higher order conductive segments,a second reconnector controllable impedance path coupled between the associated two second higher order conductive segments,a first switch controllable impedance path coupled between the one of the two first higher order conductive segments and an associated first lower order conductive segment,a second switch controllable impedance path coupled between the other of the two first higher order conductive segments and another associated first lower order conductive segment,a third switch controllable impedance path coupled between the one of the two second higher order conductive segments and an associated second lower order conductive segment, anda fourth switch controllable impedance path coupled between the other of the two second higher order conductive segments and another associated first lower order conductive segment.