Patent ID: 6573545
Filing Date: 2003-06-03
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor substrate; a plurality of bit lines buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate, the bit lines arranged in parallel with one another; a plurality of word lines formed on the semiconductor substrate such that the word lines cross the bit lines and are isolated therefrom; and a plurality of vertical access transistors formed at individual memory cells where the bit lines and the word lines intersect, each vertical access transistor comprising a first source/drain region, a body region including a vertical channel region, and a second source/drain region, which are formed sequentially overlying one of the bit lines, the vertical access transistor contacting a gate insulation layer formed on one side of sidewalls of the word lines, the body regions being connected to one another.