Patent ID: 7279945
Filing Date: 2007-10-09
Classification: G11B,H03L

Abstract:
1. A phase locked loop (PLL) generating a phase locked signal and adjusting a frequency of the phase locked signal according to an incoming signal having periodic frames, the PLL comprising: an oscillator for generating the phased locked signal; a frequency detection module electrically coupled to the oscillator for detecting two regular patterns within two different frames of the incoming signal, calculating a number of periods of the phase locked signal corresponding to a distance between the two regular patterns, and controlling the oscillator to adjust the frequency of the phase locked loop signal according to the number of periods; a frequency detector for calculating a difference in frequency between the incoming signal and the phase locked loop signal, and further for controlling the oscillator to adjust the frequency of the phase locked loop signal according to the difference in frequency; and a multiplexor coupled to the frequency detector, the frequency detection module, and the oscillator, the multiplexor for selecting one of the frequency detector or the frequency detection module to control the oscillator to adjust the frequency of the phase locked loop signal; wherein the multiplexor first selects the frequency detector to control the oscillator to adjust the frequency of the phase locked loop signal, and then selects the frequency detection module to control the oscillator to adjust the frequency of the phase locked loop signal if the PLL has not entered into a locked state after a predetermined time.