Patent ID: 6140854
Filing Date: 2000-10-31
Classification: G06F,H03L

Abstract:
An integrated circuit which provides an output clock signal synchronized to an internal clock signal which operates the integrated circuit, comprising:a clock generator circuit having an input for receiving the internal clock signal, and first and second outputs for respectively providing first and second clock signals having first and second frequencies, respectively, said first frequency being an integer multiple greater than or equal to one of said second frequency, wherein said clock generator circuit comprises an analog phase locked loop;a clock shifting circuit having first and second inputs respectively coupled to said first and second outputs of said clock generator circuit, a first output for providing a shifted clock signal, and a second output for providing a reference clock signal, wherein said clock shifting circuit divides said first input by a predetermined divide ratio to provide a divided clock signal and selectively delays said divided clock signal by a selected delay time to provide said shifted clock signal, and provides said reference clock signal by dividing said second input by a divide ratio;wherein said clock shifting circuit comprises:a register for storing a control bit and providing an output thereof responsive to a logic state of said control bit; anda multiplexer having true and complement input terminals each receiving said first clock signal, a control input terminal coupled to said output of said register, and an output terminal for providing said shifted clock signal; anda delay locked loop having a reference clock input for receiving said second clock signal, a feedback clock input for receiving a feedback clock signal, a clock input for receiving the shifted clock signal, and a clock output for providing the output clock signal, wherein the delay locked loop delays the shifted clock signal by a variable delay time proportional to a phase difference between the reference clock signal and the feedback clock signal.