Patent ID: 6803917
Filing Date: 2004-10-12
Classification: G06T,G09G,G11C,H04N

Abstract:
A checkerboard buffer, comprising:a video source providing pixel data for pixels in a frame; a video destination; a first memory; a second memory; a third memory; a fourth memory; a first address multiplexor connected to the first memory; a second address multiplexor connected to the second memory; a third address multiplexor connected to the third memory; a fourth address multiplexor connected to the fourth memory a four-by-four switch connected to the first memory, the second memory, the third memory, and the fourth memory, having a first data input, a second data input, a first data output and a second data output, where the four-by-four switch switches with each frame between providing pixel data to the first memory and the second memory while receiving pixel data from the third memory and the fourth memory, and receiving pixel data from the first memory and the second memory while providing pixel data to the third memory and the fourth memory; a source address bus connected to the video source, the first address multiplexor, the second address multiplexor, the third address multiplexor, and the fourth address multiplexor; a first destination address bus connected to the video destination, the first address multiplexor, and the third address multiplexor; a second destination address bus connected to the video destination, the second address multiplexor, and the fourth address multiplexor; a first data switch connected to the video source and the four-by-four switch, where the first data switch switches which data input of the four-by-four switch to provide which pixel data for two pixels with each horizontal row of pixels; and a second data switch connected to the video destination and the four-by-four switch, where the second data switch switches the order pixel data from the data outputs of the four-by-four switch is provided to the video destination with each vertical column of pixels.