Patent ID: 6754738
Filing Date: 2004-06-22
Classification: G06F

Abstract:
An apparatus comprising:a processor handling an I/O request in an I/O operation; main storage controlled by said processor for storing data; one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation; a time-of-day (TOD) register for containing a TOD value; a clock for containing a current TOD value; a summary register having a first condition when any one of said devices requests an I/O operation and a second condition when no devices have an outstanding I/O request, each device having an outstanding I/O request setting said summary register to its first condition only when said summary register is in said second condition, said device further placing the current TOD value in said TOD register only when changing the summary register from its second condition to its first condition; a checking program for determining if a specified time delay has been exceeded between the value in said TOD register and the current TOD for each requested I/O operation, said checking program driving an interrupt to said processor when the specified time delay has been exceeded.