Patent ID: 7480833
Filing Date: 2009-01-20
Classification: G06F

Abstract:
1. A method of pre-detecting a hardware hang in a processor, the method comprising: maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts of a hang limit; initiating a trace capture in response to detecting said pre-hang condition by defining a wrap-back address space such that, during a compression mode, trace data is stored circularly in the wrap-back address space and, upon exiting the compression mode, a write address is established for further trace data such that trace data prior to exiting compression mode is maintained, wherein the write address is established by retrieving a jump-to address outside of the wrap-back address space and writing the further trace data to the jump-to address space, wherein the compression mode utilizes a respective plurality of functional units in the processor, each of the respective plurality of functional units sending a corresponding signal to a centralized trace control logic indicative of whether or not a functional unit of the respective plurality of functional units is idle, and if the centralized trace control logic determines that all of the respective plurality of functional units are idle, then the centralized trace control logic stops the trace; and detecting a hang condition if said count equals said hang limit.