Patent ID: 9116815
Filing Date: 2015-08-25
Classification: G06F

Abstract:
1. A method, comprising: selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting at least one cache miss to at least one first address, wherein the sequence of relative addresses is determined relative to said at least one first address; issuing a prefetch request for data from a first memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream of a plurality of prefetch streams accessed prefetched data associated with said one of the sequence of relative addresses, each of the plurality of prefetch streams comprising a different sequence of addresses; and blocking a prefetch request for data from a second memory address indicated by another relative address of the sequence of relative addresses when less than a threshold number of separate ones of the plurality of prefetch streams accessed data associated with said another relative address of the sequence of relative addresses.