Patent ID: 6265762
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A semiconductor device comprising:a supporting body;a semiconductor chip mounted on one surface of said supporting body, said semiconductor chip having an integrated circuit and bonding pads formed on a main surface thereof, said main surface of said semiconductor chip having a quadrilateral shape, said bonding pads being disposed along four sides of said main surface of said semiconductor chip;a plurality of leads each having an inner lead and an outer lead which is continuous with said inner lead, tips of said inner leads being disposed on said one surface of said supporting body to surround said semiconductor chip along the four sides thereof and being fixed to said one surface of said supporting body via an insulating adhesive layer;a plurality of bonding wires electrically connecting said bonding pads with the tips of said inner leads; anda resin body sealing said semiconductor chip, said inner leads, said plurality of bonding wires and said supporting body, said resin body having a quadrilateral shape, said outer leads protruding outwardly from four sides of said resin body which are opposed to said four sides of said semiconductor chip;wherein a largest pitch of the tips of the inner leads of two adjacent leads respectively protruding from two adjacent sides of said resin body in each of four corners of said resin body is less than twice a smallest pitch with respect to pitches of the respective tips of said inner leads surrounding said semiconductor chip, and a pitch between adjacent bonding pads increases in a direction of a corner of the four sides; andwherein a relationship (L)<2.times.(W1)+(W2) exists where (L) is an allowable largest lead spacing at points of adjacent inner leads, (W1) is a smallest inner lead Pitch and (W2) is a smallest inner lead width.