Patent ID: 6288932
Filing Date: 2001-09-11
Classification: G11C

Abstract:
A dynamic flip-flop circuit comprising:a first latch having a first input lead, a second input lead, and an output lead, said first latch including a first shutoff circuit, said first shutoff circuit including a first nand gate, a first inverter, and a first n-channel transistor, said first nand gate having a first input lead and a second input lead, said first input lead coupled to an output lead of a second latch, and said second input lead coupled to a compare enable line, said first inverter having an input lead and an output lead, said input lead coupled to said output lead of said first nand gate, and said first n-channel transistor having a first lead coupled to said output lead of said first inverter and a second lead coupled to said output lead of said first latch; andsaid second latch having an input lead and an output lead, said second latch further including a second shutoff circuit, said second shutoff circuit including a second nand gate, a second inverter, and a second n-channel transistor, said second nand gate having a first input lead and a second input lead, said first input lead coupled to said output lead of said first latch, and said second input lead coupled to said compare enable line, said second inverter having an input lead and an output lead, said input lead coupled to said output lead of said second nand gate, and said second n-channel transistor having a first lead coupled to said output lead of said second inverter and a second lead coupled to said output lead of said second latch.