Patent ID: 6324628
Filing Date: 2001-11-27
Classification: G06F

Abstract:
A system comprising:an external memory; anda closed device, coupled to said external memory, wherein said closed device includes:a processor coupled to said external memory;an internal memory coupled to said processor, wherein said internal memory is not accessible except access through predefined input and output ports that are internal to said closed device;a select control circuit coupled to said processor and configured to select said external memory as primary memory in response to assertion of an external control signal and to select said internal memory as primary memory in response to a deassertion of said external control signal;an internal data bus, coupled with said select control circuit, said processor, and said internal memory, said internal data bus residing solely within said closed device with no external access; andan external data bus, coupled with said select control circuit and said external memory, configured to transport data between said select control circuit and said external memory.