Patent ID: 6383903
Filing Date: 2002-05-07
Classification: H01L

Abstract:
A method for forming a partial salicide, said method comprises:providing a wafer, wherein said wafer comprises a substrate and said substrate comprises a first region and a second region; forming a first oxide layer on said substrate; forming a silicon layer on said first oxide layer; forming a nitride layer on said silicon layer; removing said partial silicon layer and said partial nitride layer to form a plural first gates and a plural first diffusion regions in said first region and to form a plural second gates and a plural second diffusion regions in a second region of said wafer, wherein said plural first diffusion regions are located on a side of said plural first gates and said plural second diffusion regions are located on a side of said plural second gates; forming a second oxide layer on said plural first diffusion regions, said plural first gates, said plural second diffusion regions, and said plural second gates; removing said partial second oxide layer to show said nitride layer on a top of said plural first gates and a top of said plural second gates; removing said nitride layer to show said silicon layer on said top of said plural first gates and said top of said plural second gates; forming a mask layer on said plural second gates and said second oxide layer which are in said second region; removing said partial second oxide layer to form a spacer on a sidewall of said plural first gates and to show said first oxide layer on said plural first diffusion regions; forming a source/drain region in said plural first diffusion regions; forming a metal layer on said plural first gates, said plural first diffusion regions, said second oxide layer, and said plural second gates; proceeding a rapid thermal process to form a silicide layer on said plural first gates, said plural first diffusion regions, and said plural second gates; and removing said metal layer.