Patent ID: 9065644
Filing Date: 2015-06-23
Classification: H04B,H04L,H04W

Abstract:
1. An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising: a first transmitter configured to send first data at a data rate to a second receiver in a second IC; a first receiver configured to receive second data at the data rate from a second transmitter in the second IC; wherein a first link is coupled to the first transmitter, the first receiver, the second transmitter, and the second receiver to form a first bidirectional link, wherein a second link is coupled to the first transmitter, the first receiver, the second transmitter, and the second receiver to form a second bidirectional link, wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate, and wherein the IC is configured to transfer the first data and the second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce link speed of the first link and the second link without reducing throughput of a lane pair comprising the first link and the second link.