Patent ID: 8593327
Filing Date: 2013-11-26
Classification: H03M,H04N

Abstract:
1. An A/D conversion circuit comprising: a reference signal generation unit that generates a reference signal increasing or decreasing through time; a comparison unit that compares an analog signal to be subjected to A/D conversion with the reference signal, and completes a comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal; a delay circuit that includes a plurality of delay elements connected to one another to delay a pulse signal, and outputs a lower phase signal being configured with output signals from the plurality of delay elements; a latch unit that latches a second lower phase signal at a second timing at which the comparison process for a second analog signal is completed after latching a first lower phase signal at a first timing at which the comparison process for a first analog signal is completed; an arithmetic unit that generates a second lower count signal in response to the second lower phase signal held by the latch unit after generating a first lower count signal in response to the first lower phase signal held by the latch unit; a lower counter that is configured with a first binary counter that acquires a first lower count value by performing counting using the first lower count signal as a count clock and inverts values of bits constituting the first lower count value, and then acquires a second lower count value by performing counting using the second lower count signal as a count clock and outputs an upper count clock based on a flag bit of the second lower count value; an upper counter that is configured with a second binary counter that acquires a first upper count value by performing counting using one output signal, which constitutes the first lower phase signal output from the delay circuit, as a count clock and inverts values of each bits constituting the first upper count value, and then acquires a second upper count value by performing counting using one output signal, which constitutes the second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on the upper count clock; and a modification unit that modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched, wherein digital data corresponding to a difference between the first analog signal and the second analog signal is acquired.