Patent ID: 8202740
Filing Date: 2012-06-19
Classification: G01R,H01L

Abstract:
1. A testing method of a semiconductor device obtained by integrally configuring a first semiconductor device and a second semiconductor device and having a coupling means for coupling together corresponding terminals, wherein the first semiconductor device includes a first memory circuit, wherein the second semiconductor device include a second memory circuit, a signal processing circuit performing signal processing operation according to a program, an interface circuit that can be coupled with the first memory circuit, and an interface circuit for user debugging, and wherein the semiconductor device is mounted over a board for testing having an oscillation circuit generating a clock signal equivalent to the actual operation of the semiconductor device and the clock signal is supplied thereto, the testing method comprising: a first operation of writing a test program for conducting a performance test on the first memory circuit from a tester to the second memory circuit of the second semiconductor device through the interface circuit for user debugging; a second operation of conducting a performance test on the first memory circuit according to the written test program in correspondence with the clock signal in the signal processing circuit; and a third operation of outputting the result of failure/no-failure determination in the second operation to the tester.