Patent ID: 6282634
Filing Date: 2001-08-28
Classification: G06F

Abstract:
An apparatus for processing data, said apparatus comprising:a register bank having a plurality of registers, each register operable as either a vector register or a scalar register; andinstruction decoding and execution logic for decoding data processing instructions, at least one of said data processing instructions having at least an operation specifying code specifying an operation for execution and a first register specifying field specifying a first register within said register bank; whereinsaid instruction decoding and execution logic executes an operation using a given register as either a scalar register or a vector register, execution with said given register being a scalar register comprising executing said operation once upon an operand stored in said given register and execution with said given register being a vector register comprising executing said operation a plurality of times upon operands stored within a predetermined sequence of registers of said register bank selected in dependence upon a register specifying field for said given register; andsaid instruction decoding and execution logic is responsive to said first register specifying field and is independent of said operation specifying code to determine whether said operation is to be executed using said first register as either a vector register or a scalar register.