Patent ID: 7948023
Filing Date: 2011-05-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate; a nonvolatile memory cell array including a first MOS transistor having a first gate formed on the semiconductor substrate, the first gate being a layered gate structure having a first gate insulating film, a first gate electrode film, a second gate insulating film, a second gate electrode film and a third gate electrode film, a source and a drain formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate, and an opening being formed in the second gate insulating film and the second gate electrode film, and the third gate electrode film being connected to the first gate electrode film at the opening; and a logic circuit including a plurality of second MOS transistors having a second gate formed on the semiconductor substrate, the second gate being a layered gate structure having a third gate insulating film, the second gate electrode film and the third gate electrode film, and the source and the drain formed in the semiconductor substrate to interpose the surface region of the semiconductor substrate beneath the second gate, wherein each of the second MOS transistors includes one of the third gate insulating film of a first thickness, the third gate insulating film of a second thickness and the third gate insulating film of a third thickness.