Patent ID: 6771162
Filing Date: 2004-08-03
Classification: H03K

Abstract:
A crosspoint switch for receiving N input signals and for producing M output signals in response to the input signals, wherein M and N are integers greater than 2, the crosspoint switch comprising:N input lines, each receiving a separate one of said input signals; M output lines, each conveying a separate one of said output signals; and a switch cell array having N rows of switch cells and M columns of switch cells, wherein each input line conveys its received input signal to each switch cell of a corresponding one of said row N rows of switch cells, wherein each output line is connected to each switch cell of a corresponding one of said M columns of switch cells, and wherein each switch cell of said plurality of switch cells comprises: a memory cell for storing control data, and a tristate buffer having a control input linked to said memory cell such that the control data stored in the memory cell selects whether the tristate buffer operates in one of active and inactive modes, wherein when operating in said active mode said tristate buffer drives the output signal appearing on the switch cell's corresponding output line to a state determined in response to a state of the input signal conveyed on the switch cell's corresponding input line, and wherein when operating in said inactive mode, said tristate buffer refrains from driving the output signal to any state, wherein the tristate buffer within each switch cell comprises: a first voltage source; a second voltage source; a first pMOS transistor (Q5) having a source terminal tied to said first voltage source, having a drain terminal tied to the output line corresponding to the switch cell, and having a gate terminal; a second pMOS transistor (Q7) having a source terminal tied to said first voltage source, having a drain terminal tied to the gate terminal of said first PMOS transistor, and having a gate terminal linked to the memory cell within said switch cell such that the control data stored in said memory cell controls a first voltage at that gate terminal, a first nMOS transistor (Q6) having a source terminal tied to said second voltage source, having a drain terminal tied to the output line corresponding to the switch cell, and having a gate terminal; a second nMOS transistor (Q8) having a source terminal tied to said second voltage source, having a drain terminal tied to the gate terminal of said first nMOS transistor, and having a gate terminal linked to the memory cell within said switch cell such that the control data stored in said memory cell controls a voltage at that gate terminal; a first pass gate (46) connected between the input line corresponding to said switch cell and the gate terminal of said first pMOS transistor; and a second pass gate (48) connected between the input line corresponding to said switch cell and the gate terminal of said first nMOS transistor, wherein the control data in the memory cell places the tristate buffer in its active mode by turning on said first and second pass gates, and places the tristate buffer in its inactive mode by turning off the first and second pass gates.