Patent ID: 6181751
Filing Date: 2001-01-30
Classification: H03D,H04L

Abstract:
A multi-stage detection system in a digital demodulator, comprising:first-stage detection means for detecting an input signal;second-stage detection means for receiving outputs from said first-stage detection means; andthird-stage detection means for receiving outputs from said second-stage detection means,said first-stage detection means including:a first delay for delaying the input signal by one sampling period;a first adder for adding the input signal to an output from said first delay;a first detector for detecting an output from said first adder, said first detector comprising:a fourth adder for adding the output from said first adder to a constant .pi./4;a fifth adder for adding the output from said first adder to a constant 3.pi./4;a sixth adder for adding the output from said first adder to a constant -.pi./4;a seventh adder for adding the output from said first adder to a constant -3.pi./4;a first absolute circuit for calculating a phase error of an output from said fourth adder;a second absolute circuit for calculating a phase error of an output from said fifth adder;a third absolute circuit for calculating a phase error of an output from said sixth adder;a fourth absolute circuit for calculating a phase error of an output from said seventh adder; anda comparison circuit for comparing outputs from said first to fourth absolute circuits;a second delay for delaying the output from said first delay by one sampling period;a second adder for adding the input signal to an output from said second delay;a second detector for detecting an output from said second adder;a third delay for delaying the output from said second delay by one sampling period;a third adder for adding the input signal to an output from said third delay; anda third detector for detecting an output from said third adder.