Patent ID: 6683814
Filing Date: 2004-01-27
Classification: G11C

Abstract:
A memory device, comprising:a plurality of banks of memory arrays, each of the memory arrays containing a plurality of sub-arrays arranged in rows and columns, each of the sub-arrays containing a plurality of memory cells arranged in rows and columns; a row address decoder coupled to receive a row address signal and to enable a corresponding row of memory cells in one of the sub-arrays of one of the banks; a column address decoder coupled to receive a column address signal and to enable a corresponding column of memory cells in one of the sub-arrays of one of the banks; a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands; and a read data path, comprising: P*M storage devices each operable to store a respective bits of data received from each of P corresponding columns of sub-arrays; a first bus having M*L/2 bits coupled to P*M/2 of the storage devices; a second bus having M*L/2 bits coupled to P*M/2 of the storage devices; a first set of L/2 parallel-to-serial converters coupled to the first bus, each of the parallel-to-serial converters in the first set having M input terminals coupled to receive M respective bits from the first bus, the parallel-to-serial converters in the first set having respective serial output terminals coupled to a first set of L/2 respective data bus terminals, each of the L/2 parallel-to-serial converters in the first set being operable in the first operating mode to receive from the storage device through the first bus 2L/P sets of parallel data each containing M*P/L bits and apply L/2 bursts each containing 2M bits to respective data bus terminals in the first set; and a second set of L/2 parallel-to-serial converters coupled to the first and second buses, each of the parallel-to-serial converters in the second set having M input terminals coupled to receive M respective bits from the first bus and M respective bits from the second bus, the parallel-to-serial converters in the second set having respective serial output terminals coupled to a second set of L/2 respective data bus terminals, each of the L/2 parallel-to-serial converters in the second set being operable in the first operating mode to receive from the storage device through the second bus 2L/P sets of parallel data each containing M*P/L bits and to apply L/2 bursts each containing 2M bits to respective data bus terminals in the second set, each of the L/2 parallel-to-serial converters in the second set being operable in a second mode to receive from the storage device through the first and second buses L/P sets of parallel data containing 2M*P/L bits and to apply L/2 bursts each containing 2M bits to respective data bus terminals in the second set.