Patent ID: 9012967
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. An embedded memory, comprising: a substrate comprising first transistors in a cell array region and second transistors in a periphery region; an etch stop layer disposed on tops of gate electrodes of the first and second transistors; a first dielectric layer, embedding first and second conductive plugs electrically connecting the first transistors therein, overlying the etch stop layer; a second dielectric layer, overlying the first dielectric layer and comprising a plurality of capacitor openings exposing the first conductive plugs and a top of the first dielectric layer; a plurality of capacitors at least partially embedded in the capacitor openings, wherein the capacitors comprise a plurality of bottom plates respectively disposed in the capacitor openings and directly contacting the first conductive plugs, a capacitor dielectric layer overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layer, wherein the top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors, and wherein the capacitor dielectric layer is entirely above the first and second transistors; and a plurality of first dielectric spacers respectively disposed on sidewalls of the top plate in the capacitor openings.