Patent ID: 9069719
Filing Date: 2015-06-30
Classification: G06F,G11C

Abstract:
1. A smart memory system comprising: a memory comprising one or more memory arrays; a memory processor; a common memory bus configured to provide an asynchronous handshaking interface between the one or more memory arrays and the memory processor to provide verification of read and write operation success or failures; and a non-volatile error retention memory configured to receive address information from the memory processor relating to memory locations exhibiting errors, wherein said memory processor is configured to perform one or more error-correction processes on the memory locations whose addresses are stored in the non-volatile error retention memory; the smart memory system further comprising: control logic configured to receive at least one of a read signal or a write signal; and an address line configured to receive a memory address, wherein the control logic is configured to cause a first transition of a logic state of an acknowledgment signal responsive to the memory address.