Patent ID: 6173428
Filing Date: 2001-01-09
Classification: G01R

Abstract:
An apparatus for level sensitive scan designs, comprising:level sensitive scan design test logic including at least one serial scan test path; anda test access port controller operable in a system test mode under control of a test clock for controlling serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after a system test under control of the test clock, the test access port controller further operable in a fabrication test mode and including clock logic for providing a system clock for controlling the serial shifting of input test data into the test access port controller and level sensitive scan design test logic and for controlling the serial shifting of resulting output test data out of the test access port controller and level sensitive scan design test logic under control of the system clock;wherein the test access port controller and the level sensitive scan design logic are operated under test clock control for at least one test clock cycle, and wherein after said at least one test clock cycle resulting output data is serially shifted out of the test access port controller logic means and the level sensitive scan design logic under system clock control.