Patent ID: 6292014
Filing Date: 2001-09-18
Classification: H04L

Abstract:
An output buffer circuit for transmitting digital signals over a transmission line, comprising:an output stage, said output stage including a first impedance circuit connected to provide a first impedance between a first node for supplying an upper supply potential and an output terminal for connection with said transmission line in accordance with a first impedance control signal;said output stage further including a second impedance circuit connected to provide a second impedance between a second node for supplying a lower supply potential and said output terminal in accordance with a second impedance control signal;a control circuit, said control circuit adapted to receive a digital data input signal and further to generate said first and second impedance control signals in accordance with said digital data input signal; andsaid control circuit further adapted to generate said first and second impedance control signals such that (i) an impedance ratio between said first impedance generated by said first impedance circuit and said second impedance generated by said second impedance circuit takes one of at least three different predetermined values in accordance with a present state and a history of said digital data input signal and (ii) the sum of conductance provided by said first impedance circuit and conductance provided by said second impedance circuit is independent from said generated impedance ratios.