Patent ID: 6326221
Filing Date: 2001-12-04
Classification: H01J

Abstract:
A method for manufacturing a field emitter array on an SOI wafer, comprising the steps of:forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer;making a buffer oxide layer on the doped silicon layer;making a stripe pattern of silicon nitride on the buffer oxide layer;etching the buffer oxide layer using the stripe pattern as a mask;etching the doped silicon layer anisotropically using the stripe pattern as a mask;making a minute mask pattern of silicon nitride on the buffer oxide layer by patterning the stripe pattern of silicon nitride;selectively oxidizing the upper part of the doped silicon layer to form an oxide layer except on the portions under the mask pattern;etching away the mask pattern of silicon nitride and the buffer oxide layer deposited under the mask pattern;etching away the exposed doped silicon layer for making gate holes of undercut shape;forming metal layers in the SOI wafer and the bottom of the gate holes by evaporating a metallic evaporant downwardly and vertically against the surface of the SOI wafer; andforming field emitter tips on the metal layer in the gate holes.