Patent ID: 6505296
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A computer system comprising:memory storing a program, an interruption handler, and an interruption vector table, wherein the program has instructions including a trampoline check instruction and a special handler for handling an interruption, wherein the interruption vector table includes an interruption vector not shared with other interruptions for supplying information related to the interruption; and a processor for executing the program and the interruption handler, wherein the processor includes an instruction pointer indicating a memory location of a current executing instruction, an interruption control register, and an interruption vector address register which specifies a location of the interruption vector table in the memory, wherein the processor executes the trampoline check instruction which tests a condition and if the condition is true, causes the interruption and supplies an address displacement to the interruption control register, wherein the interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of the special handler, wherein the restart point is equal to a sum of the address displacement in the interruption control register and a value of the instruction pointer at the time of the interruption.