Patent ID: 6781412
Filing Date: 2004-08-24
Classification: G06F

Abstract:
An incrementer comprising a plurality of half adder circuits each adding a carry-in bit to an input bit to generate an output bit and a carry-out bit, said plurality of half adder circuits being connected in cascade in regard to said carry-in and carry-out bits, each of said half adder circuits other than one for the least significant digit comprising:a transfer gate, having a data input and a data output, turned on when said input bit is active, said data input receiving said carry-in bit; a transistor, having a current channel connected between a power supply potential and said data output, a logic value of said power supply potential being equal to that of said carry-in bit in an inactive state, turned on when said input bit being inactive; and a logic circuit, generating said output bit which is active when either said input bit or said carry-in bit is active; wherein said carry-out bit is on said data output.