Patent ID: 8824227
Filing Date: 2014-09-02
Classification: G11C

Abstract:
1. A parallel test circuit of a semiconductor memory apparatus, comprising: a memory bank which includes first and second sub banks having test global lines—and sharing a global line, wherein, when a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line with data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad, wherein the first and second sub banks are both enabled during the test mode, wherein the global line and the test global line of the second sub bank respectively comprise a plurality of lines, and the parallel test circuit further comprises: wherein the compression unit outputs an activated compression signal when the data loaded in the global lines are equal to the data loaded in the test global lines of the second sub bank.