Patent ID: 8953730
Filing Date: 2015-02-10
Classification: G04F,H03L,H03M

Abstract:
1. A phase locked loop (PLL) comprising: a phase difference detector configured to receive a reference frequency and a divider frequency, the phase difference detector configured to output a phase difference signal; a code generator configured to receive the reference frequency and the phase difference signal, the code generator configured to output a coarse tuning signal and a reset signal; a digital loop filter configured to receive the phase difference signal, the digital loop filter configured to output a fine tuning signal; a voltage control oscillator configured to receive the coarse tuning signal and the fine tuning signal, the voltage control oscillator configured to output an output frequency; a divider configured to receive the reset signal, a divider number control signal and a feedback from the output frequency, the divider configured to output the divider frequency; and a delta-sigma modulator configured to receive a divisor ratio and the reset signal.