Patent ID: 6233671
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A method comprising:receiving a single full-width macro instruction specifying at least two logical registers, wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements;responsive to the single full-width macro instruction, dividing the single full-width macro instruction into at least two partial-width micro instructions that each operate on a portion of the corresponding data elements of the first and second packed data operands by generating a first and second partial-width micro instruction corresponding to the single full-width macro instruction;independently accessing a first and second plurality of the corresponding data elements from the first and second logical registers in response to the first and second partial-width micro instruction, respectively; andresponsive to the first and second partial-width micro instructions, independently performing an operation specified by the single full-width macro instruction on the first and second plurality of the corresponding data elements from said first and second packed data operands, respectively, at different times using the same partial-width circuitry to independently generate a first and second plurality of resulting data elements, wherein the first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.