Patent ID: 6429135
Filing Date: 2002-08-06
Classification: H01L

Abstract:
A method of reducing stress between a nitride silicon spacer and a substrate on a semiconductor wafer, the semiconductor wafer comprising the substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around the gate and the cap layer, the method comprising:forming a dielectric layer on the semiconductor wafer, wherein the dielectric layer covers the gate, and the dielectric layer is made of the same material as the silicon oxide spacer; performing a chemical mechanical polishing (CMP) process to align a top surface of the dielectric layer with a top surface of the cap layer; performing an etching back process to remove portions of the dielectric layer and portions of the silicon oxide spacer; and forming the silicon nitride spacer around the cap layer, wherein the silicon nitride spacer is positioned on the surface of the dielectric layer to reduce stress between the nitride silicon spacer and the substrate.