Patent ID: 8982033
Filing Date: 2015-03-17
Classification: G09G,G11C

Abstract:
1. A display device, comprising: a first portion including unit register circuits cascaded in m stages, where m is an integer which is equal to or larger than 3, for outputting an output pulse P a second portion for outputting n-phase clock pulses to the respective stages of the first portion, where n is an integer which is equal to or larger than 3, in sequence in the forward direction in forward shift operation of the first portion and in the reverse direction in backward shift operation; and a third portion for outputting a forward direction trigger signal at the start of the forward shift operation and outputting a reverse direction trigger signal at the start of the backward shift operation, the unit register circuit in a k-th stage including forward and reverse direction set nodes, forward and reverse direction reset nodes, a set circuit for setting a reference point of the unit register circuit to a first potential when a set signal is input to one of the set nodes, a reset circuit for setting the reference point to a second potential when a reset signal is input to one of the reset nodes, and an output circuit for bootstrapping the reference point and outputting the output pulse P where variables given as αf, αb, βf, and βb are natural numbers which satisfy both αf<βb<n and αb<βf<n, the set circuit in the k-th stage being input the output pulse P the reset circuit in the k-th stage being input the output pulse P the forward direction trigger signal being input to the forward direction reset node in each of (m−βf+1)th to m-th stages as the reset signal, and the reverse direction trigger signal being input to the reverse direction reset node in each of first to βb-th stages as the reset signal.