Patent ID: 6841824
Filing Date: 2005-01-11
Classification: H01L

Abstract:
1. An integrated circuit with logic and/or linear transistors and memory devices comprising: a region of logic and/or linear devices comprising field effect transistors, each including a source spaced from a drain, a channel between the source and drain, a control gate including an insulating layer over the channel an a gate electrode on the insulating layer for controlling the electric field in the channel, and a logic and/or linear device sidewall insulating layer on the sides of the gate electrode to separate it from adjacent transistors; a region of memory devices including electrically programmable memory transistors each comprising a source spaced from a drain, a channel between the source and drain, a control gate including an insulating layer over the channel and a first electrode on the insulating layer for controlling the electric field in the channel, a dielectric layer over the control gate, a second electrode on the dielectric layer for applying a voltage to the transistor to store or remove a charge in the dielectric layer, and a memory device sidewall insulating layer on the sides of the first and second electrodes to reduce the electric field in the substrate generate by the charge stored in the dielectric layer over the control gate and to separate adjacent memory devices from each other, wherein the memory device sidewall insulating layer is thicker than the logic and/or linear device sidewall insulating layer.