Patent ID: 6030878
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A method of fabricating a capacitor comprising the steps of:providing a substrate having a transistor thereon, wherein the transistor includes a source/drain region;forming a dielectric layer on the substrate, wherein the dielectric layer has an contact hole formed therein to exposed the source/drain region;forming a first conductive layer over the substrate to fill the contact hole and to electrically couple with the source/drain region through the contact hole;forming an isolation layer on the first conductive layer;patterning the isolation layer and the first conductive layer to form a patterned isolation layer and a raised region above the contact hole, wherein the raised region is a portion of the first conductive layer, the patterned isolation layer is located on the raised region, and the planar area of the raised region and the patterned isolation layer are the same;forming a first spacer on a sidewall of the patterned isolation layer and the raised region;removing the patterned isolation layer;using the first spacer as a mask and performing a first etching step to remove a portion of the first patterned conductive layer to form a first sidewall and a second sidewall of the first patterned conductive layer;removing the first spacer;forming a second spacer on the first sidewall and a third spacer on the second sidewall;using the second spacer and the third spacer as masks and the dielectric layer as etching stop layer and performing a second etching step to remove a portion of the first patterned conductive layer to from a second conductive layer, wherein the second patterned conductive layer is used as a storage electrode;removing the second spacer and the third spacer; andforming a dielectric film and a second conductive layer in sequence over the substrate.