Patent ID: 7276940
Filing Date: 2007-10-02
Classification: H03F,H03K

Abstract:
1. A method comprising: buffering a plurality of separate input voltages respectively through each of a plurality of input stages, each input stage comprising electrically-parallel branches of a first transistor connected in series with a second transistor, and a third transistor connected in series with a fourth transistor, said second and fourth transistors being of an inverse type to that of said first and third transistors, a gate interconnection electrically connecting gates of said first and second transistors to one another receiving the respective input voltage, and an intermediate electrical connection connecting all of the gates of said third and fourth transistors, an intermediate point between said first and second transistors and an intermediate point between said third and fourth transistors to one another generating a respective buffered voltage, wherein said first and third transistors have width-to-length ratios which are substantially equal to one another, and said second and fourth transistors have width-to-length ratios which are substantially equal to one another; enabling a selected one of said input stages comprising applying an enabling signal to a switch coupled to all of the transistors in said selected input stage; disabling said input stages other than said selected input stage comprising applying a disable signal to each of a plurality of additional switches, each additional switch being coupled to all of the transistors in one of the input stages other than said selected input stage; and buffering said buffered voltage of said selected input stage into an output voltage through an output stage comprising electrically-parallel branches of a first transistor connected in series with a second transistor, and a third transistor connected in series with a fourth transistor, said second and fourth transistors being of an inverse type to that of said first and third transistors, a gate interconnection electrically connecting gates of said first and second transistors to one another receiving said buffered voltage of said selected input stage, and an intermediate electrical connection connecting all of the gates of said third and fourth transistors, an intermediate point between said first and second transistors and an intermediate point between said third and fourth transistors to one another generating said output voltage, wherein said first and third transistors have width-to-length ratios which are substantially equal to one another, and said second and fourth transistors have width-to-length ratios which are substantially equal to one another.