Patent ID: 8207583
Filing Date: 2012-06-26
Classification: H01L

Abstract:
1. A memory device comprising: a substrate having an array portion and a logic portion; a plurality of semiconductor structures that are recessed in the array portion of the substrate, wherein a top surface of each of the plurality of semiconductor structures is co-planar with a top surface of the substrate, each of the plurality of semiconductor structures include a channel portion that is contiguous with the substrate array portion, wherein the channel portion is between two gate segments and below the top surface of the substrate, each of the plurality of semiconductor structures occupies an area of the substrate array portion between about 4F 2 and about 8F 2 , wherein F is the minimum resolvable feature size formable using a photolithographic technique that is used to define features of the semiconductor structures, the area of the substrate array portion having a length dimension that is equal to a width dimension and the plurality of semiconductor structures form a pattern having a first pitch; and a plurality of transistor devices formed over the logic portion of the substrate, wherein each of the plurality of transistor devices include a gate oxide layer, a gate layer, and sidewall spacer structures, wherein there is no dielectric layer above the gate layer between the sidewall spacer structures, and wherein the plurality of transistor devices are formed in a layer that is above the plurality of semiconductor structures and wherein the plurality of transistor devices form a pattern having a second pitch that is at least two times the first pitch.