Patent ID: 6261637
Filing Date: 2001-07-17
Classification: C23C,H01L

Abstract:
A process for the selective electroless metal plating of Ti, W, Ti/W alloy, aluminum or aluminum alloy metal layer used in the fabrication of a silicon integrated circuit wafer coated with a layer of a dielectric material comprising:forming a desired circuit pattern in the dielectric layer on the wafer in the form of vias or other openings which extend through the dielectric layer to the silicon layer;depositing the metal layer on the silicon layer in the via or in the other opening;activating the metal layer of the wafer by contacting the wafer with an activation solution which solution removes metal layer oxides and/or etches the metal layer surface which activation solution is either acid or alkaline and comprises a complexing agent to form a complex with metal which may be removed during the activation step;sensitizing the activated metal layer of the wafer by contacting the wafer with an alkaline sensitizing solution composition comprising a sensitizing metal non-ammonia nitrogen complex to sensitize the metal layer; andelectrolessly metal plating the sensitized metal layer of the wafer by contacting the wafer with an electroless metal plating solution wherein the metal is plated on the sensitized metal layer with no substantial plating on other areas of the wafer.