Patent ID: 8654588
Filing Date: 2014-02-18
Classification: G11C

Abstract:
1. An operating method of a semiconductor memory device, comprising: erasing all memory cells of a selected cell block; performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block; performing a first verify operation using a first voltage level lower than a target voltage level of the soft program operation; performing a second verify operation using the target voltage level; setting voltages of bit lines by supplying a soft program permission voltage to bit lines coupled to memory cells having threshold voltages lower than the first voltage level, a soft program suppression voltage to bit lines coupled to memory cells having threshold voltages between the first voltage level and the target voltage level, and a soft program inhibition voltage to bit lines coupled to memory cells having threshold voltages equal to or greater the target voltage level in response to the first and second verify operations; and repeating the soft program operation, the first verify operation, the second verify operation, and an operation of setting the voltages of bit lines while raising the soft program pulse gradually until the threshold voltages of all the erased memory cells reach the target voltage level.