Patent ID: 6311260
Filing Date: 2001-10-30
Classification: G06F

Abstract:
A method of operating a processing system comprising a processor for processing program instructions and data, including a memory system comprising a relatively slow main memory and a relatively fast cache memory, wherein items which are frequently and actively used are transferred from the main memory to the cache memory for storage while they are being actively used, and items which are no longer actively used are removed from the cache memory to make room for newly actively used items comprising, equipping the processor with a prefetch unit which sends a sequence of prefetch addresses to the main memory to obtain and bring items to the cache memory earlier than the processor would request them and thereby reduce the idle time that the processor would otherwise experience, encoding each instruction with a hint field which controls the prefetch unit, wherein the information in the hint field enables the prefetch unit to detect both fixed and variable offsets to a base address in strided and linked structured data, and utilizes the detected fixed and variable offsets relative to a new base address to generate the sequence of prefetch addresses.