Patent ID: 7823159
Filing Date: 2010-10-26
Classification: G06F

Abstract:
1. A computing system comprising: one or more processing elements; a memory having a first interface for connecting to a host processor and a second interface, the memory being divided into a plurality of logical partitions, at least one partition being a system partition that contains information that describes a particular task out of a number of tasks including a state of the task; and a multi-task controller (MTC) that includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit, each unit coupled to the other units, wherein the processing elements and the scheduler unit, the data flow unit, the executive unit, and the resource manager unit each reside in one of several clock domains, said clock domains being synchronous to each other and separated in time by multiples of one-half of a clock period, said multiple being odd for units having a higher frequency of use and even for units having a lower frequency of use; and wherein the number of said one or more processing elements and the number of tasks are independent of each other.