Patent ID: 6772379
Filing Date: 2004-08-03
Classification: G11C

Abstract:
An apparatus for verifying data retention in a non-volatile memory comprising:a multiplexer; a shift register, said multiplexer and said shift register being coupled so that the data of said non-volatile memory are input to said multiplexer, the output of which is input to said shift register; a logical circuitry coupled to the multiplexer and shift register which by suitable commands controls the transfer of data from said multiplexer to said shift register, the loading of data, and the shifting of output data in said shift register; means for applying a thermal stress to said nonvolatile memory; means for applying suitable commands to control the transfer of data from said multiplexer to said shift register, the loading of data and the shifting of output data in said shift register after thermal stress is applied to the nonvolatile memory; and comparing means for comparing data values prior to the thermal stress to data values after the thermal stress.