Patent ID: 7592670
Filing Date: 2009-09-22
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, each fin active region having a silicon-on-insulator (SOI) substrate including a first insulation layer, an N-type substrate, a second insulation layer, and a P-type substrate; an input metal line contacting gates of the PMOS transistor and NMOS transistor; a power supply voltage metal line contacting four channel active regions of the PMOS transistor; a contact metal line contacting two channel active regions of the NMOS transistor; and an output metal line contacting four channel active regions of the PMOS transistor and the NMOS transistor.