Patent ID: 8937624
Filing Date: 2015-01-20
Classification: G06F

Abstract:
1. An apparatus for translating a memory access address, the apparatus comprising: an address allocating unit to classify a plurality of pixels included in an input image based on a tile unit and to allocate a memory address to each of a plurality of tiles, wherein each of the plurality of tiles includes pixel information associated with the plurality of pixels included in the input image; an address generating unit to generate a new memory address for each successive tile among the plurality of tiles based on a corresponding memory address allocated to each of the plurality of tiles, the new memory address being configured to enable the successive tiles to be stored in different memory banks, wherein the address generating unit generates new memory addresses by performing a logical operation on a bit indicating a Y coordinate address of a tile and a bit indicating an X coordinate address of the tile in the corresponding memory address allocated to each of the plurality of tiles; and a memory controller to store each of the successive tiles in a corresponding new memory address.