Patent ID: 6782452
Filing Date: 2004-08-24
Classification: G06F

Abstract:
Apparatus for processing data, said apparatus comprising:a processor core operable to generate a data access request to a target data item having a target memory address; a cache memory having a plurality of cache lines, each cache line storing a plurality of data items associated with an address value, said cache memory being operable such that: (i) if said target data item is stored within said cache memory, then said cache memory is operable to service said data access request; and (ii) if said target data item is not stored within said cache memory, then said cache memory triggers a cache line fill operation whereby a plurality of new data items including said target data item are fetched from a main memory and written into a victim cache line among said plurality of cache lines replacing any old data items previously stored in said victim cache line; and a cache controller responsive to one or more status bits associated with said victim cache line to be operable during a cache line fill operation to permit data access requests to those data items stored within said victim cache line associated with a current address value for said victim cache line, wherein said one or more status bits include at least one cache line status bit for each cache line indicating whether a line fill operation is pending for that cache line.