Patent ID: 6018817
Filing Date: 2000-01-25
Classification: G06F,H03M

Abstract:
An apparatus for providing error detection and error correction in a computer system which may include a pre-existing error control mechanism, said apparatus capable of detecting and correcting errors in one or more bits within a data word, said apparatus comprising:a check bit generator capable of coupling to said computer system and capable of coupling to one or more memory devices, said check bit generator receiving from said computer system said data word having data bits and residual check bits, the residual check bits being provided by the pre-existing error control mechanism in the computer system, said check bit generator including selection means for selecting among a plurality of operating modes and utilizing a selected operating mode for generating a plurality of new error correction check bits based upon the data bits and the residual check bits in the data word, wherein said generated new error correction check bits are appended to said data word if said data word is to be stored in said memory devices;an error detection circuit including means for selecting among a plurality of operating modes and utilizing a selected operating mode for determining whether the one or more bit errors are present within said data word, said error detection circuit capable of coupling to said one or more memory devices for receiving said stored data word with said appended new error correction check bits; andan error correction circuit coupled to said error detection circuit and capable of coupling to said one or more memory devices for receiving said stored data words said error correction circuit for correcting the one or more bit errors in the data word detected by said error detection circuit, said error correction circuit capable of coupling to said computer system for providing said corrected data word to said computer system.