Patent ID: 8513728
Filing Date: 2013-08-20
Classification: H01L

Abstract:
1. An array of non-volatile memory cells comprising: a semiconductor substrate of a first conductivity type having a top surface; a plurality of spaced apart first regions of a second conductivity type in said substrate along the top surface, each first region extending in a row direction; a plurality of spaced apart second regions of the second conductivity type, in said substrate along the top surface, each second region spaced apart from an associated first region in a column direction, perpendicular to the row direction; a plurality of spaced apart channel regions, with each channel region between a second region and its associated first region in the column direction; each of said channel regions having a first portion and a second portion; a plurality of spaced apart word line gates extending in the row direction, with each word line gate positioned over and insulated from the first portion of a plurality of channel regions, with each first portion of channel region immediately adjacent to the second region; a plurality of spaced apart floating gates, each floating gate positioned over the second portion of the channel region and insulated therefrom; a plurality of spaced apart coupling gates extending in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates; a plurality of spaced apart metal strapping lines extending in the row direction, with each metal strapping line associated with and overlying a coupling gate, with a metal strapping line in a first row electrically connected to the associated underlying coupling gate in a plurality of first locations, and a metal strapping line in a row immediately adjacent to the first row electrically connected to the associated underlying coupling gate in a plurality of second locations, with said first locations and said second locations not in the same column; and a plurality of spaced apart erase gates, extending in said row direction, with each erase gate positioned over a first region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate.