Patent ID: 8102348
Filing Date: 2012-01-24
Classification: G02F,G09G

Abstract:
1. An in-plane switching mode liquid crystal display device, comprising: first and second substrates; a gate line on the first substrate; a data line crossing the gate line defining a unit pixel region on the first substrate; a thin film transistor at the crossing of the gate line and the data line on the first substrate; a pixel electrode line in parallel with the data line on the first substrate; a plurality of pixel electrodes extended from the pixel electrode line on the first substrate; a common electrode line adjacent to a data line of a neighboring pixel, the common electrode line being parallel with the data line on the first substrate; a plurality of common electrodes protruded from the common electrode line and alternately arranged in parallel with the plurality of pixel electrodes on the first substrate to generate an in-plane electric field substantially parallel to the surface of the first substrate; a common line traversing a central portion of the unit pixel region in a direction perpendicular to the data line and supplying a common signal to the common electrodes, wherein a second common electrode line extended from the common line is substantially overlapped with the common electrode line and electrically connected to the common electrode line; a first metal layer and a second metal layer parallel to the data line; a third metal layer connecting the thin film transistor and the pixel electrode; an alignment film on the first substrate, the alignment film having a rubbing direction perpendicular to the data line and the common electrode line and oblique from the pixel electrodes and the common electrodes in a predetermined angle; and a liquid crystal layer between the first and second substrates, wherein the common line overlaps the pixel electrode line to form a storage capacitor, wherein a length of the common electrode line is substantially the same as a length of the second common electrode line, and wherein the plurality of the common electrodes are connected to the common electrode line within the unit pixel region, wherein the pixel electrode is disposed with a tilt angle within a range of about 0°˜45° in a direction perpendicular to the second common line, wherein the first metal layer and the second metal layer are respectively overlapped with the pixel electrode line and the common electrode line to form a storage capacitor, width of the first metal layer and the second metal layer being larger than that of the pixel electrode line and the common electrode line so that the whole area of pixel electrode line and the common electrode line are respectively overlapped with the first metal layer and the second metal layer, wherein the third metal layer is parallel to the gate line to be overlapped with the pixel electrode, the third metal layer is extended from the thin film transistor and contacted to the pixel electrode through a first contact hole.