Patent ID: 7974051
Filing Date: 2011-07-05
Classification: H01L

Abstract:
1. An integrated circuit device comprising: a first circuit block; a second circuit block that operates using a power supply system differing from that of the first circuit block; and an interface circuit provided between the first circuit block and the second circuit block, the first circuit block operating using a first high-potential power supply and a first low-potential power supply; the second circuit block operating using a second high-potential power supply and a second low-potential power supply; the interface circuit including at least either a first buffer circuit or a second buffer circuit; the first buffer circuit including: a first output buffer that buffers a signal from the first circuit block and outputs the buffered signal to a first signal path, the first output buffer operating using the first high-potential power supply and the first low-potential power supply; a first input buffer that buffers a signal transmitted from the first output buffer through the first signal path and supplies the buffered signal to the second circuit block, the first input buffer operating using the second high-potential power supply and the second low-potential power supply; a first PN diode provided between the first signal path and the second high-potential power supply; a second PN diode provided between the first signal path and the second low-potential power supply; and a first electrostatic discharge protection resistor that is provided in the first signal path and formed by an impurity region; and the second buffer circuit including: a second output buffer that buffers a signal from the second circuit block and outputs the buffered signal to a second signal path, the second output buffer operating using the second high-potential power supply and the second low-potential power supply; a second input buffer that buffers a signal transmitted from the second output buffer through the second signal path and supplies the buffered signal to the first circuit block, the second input buffer operating using the first high-potential power supply and the first low-potential power supply; a third PN diode provided between the second signal path and the first high-potential power supply; a fourth PN diode provided between the second signal path and the first low-potential power supply; and a second electrostatic discharge protection resistor that is provided in the second signal path and formed by an impurity region, the second circuit block being a circuit block that includes a circuit formed by connecting a plurality of basic cells through wires; each of the plurality of basic cells including circuit elements that include at least: a first-conductivity-type well region; a second-conductivity-type well region; a second-conductivity-type diffusion layer provided in the first-conductivity-type well region; a first-conductivity-type diffusion layer provided in the second-conductivity-type well region; and at least one gate electrode layer; and each of the first PN diode, the second PN diode, and the first electrostatic discharge protection resistor included in the first buffer circuit being formed using at least one circuit element among the circuit elements included in each of the plurality of basic cells for the second circuit block.