Patent ID: 7786463
Filing Date: 2010-08-31
Classification: G11C,H01L

Abstract:
1. A multi-bit memory unit, comprising: a substrate including a source region and a drain region; an insulating layer over the substrate; a first solid electrolyte cell over the insulating layer, the first solid electrolyte cell having a capacitance that is controllable between at least two states and proximate the source region; a second solid electrolyte cell over the insulating layer, the second solid electrolyte cell having a capacitance that is controllable between at least two states and proximate the drain region; an insulating element that isolates the first solid electrolyte cell from the second solid electrolyte cell; a first anode electrically coupled to the first solid electrolyte cell; a second anode electrically coupled to the second solid electrolyte cell; and a gate contact layer over the substrate and between the source region and drain region and in direct electrical connection with the first anode and the second anode, the gate contact layer electrically coupled to a voltage source.