Patent ID: 6891754
Filing Date: 2005-05-10
Classification: G11C

Abstract:
1. A method of programming in a nonvolatile semiconductor memory which has a plurality of memory cell strings connected to a plurality of bid ines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines, the method comprising the steps of: applying a first voltage to a first one of the bitlines and a second voltage to a second one of the bitlines during a part of the first bitline setup period, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers during the remaining of the first bitline setup period; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage during a second bitline setup period following the first setup period; and applying a fourth voltage to a wordline after substantially inhibiting current into the first and second bitlines during a program period, wherein the third voltage to the first bitline is maintained during the program period.