Patent ID: 7563677
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A method of forming a recessed gate electrode structure, the method comprising: etching a semiconductor substrate to form a first recess and a second recess in communication with the first recess, the second recess being larger than the first recess; forming a gate dielectric layer on a surface of the substrate and on an inner surface of the first and second recesses; forming a first preliminary polysilicon layer on the gate dielectric layer to fill the first and second recesses, the first preliminary polysilicon layer being doped with impurities at a fourth impurity density and defining a void therein; forming a second preliminary polysilicon layer on the first preliminary polysilicon layer, the second preliminary polysilicon layer being doped with the impurities at a fifth impurity density lower than the fourth impurity density; and performing a heat treatment to diffuse impurities contained within the first and second preliminary polysilicon layers to convert the first and second preliminary polysilicon layers into a first polysilicon layer in the first recess doped with the impurities at a first impurity density, a second polysilicon layer in the second recess doped with the impurities at a second impurity density higher than the first impurity density and a third polysilicon layer on the gate dielectric layer and the first polysilicon layer, the third polysilicon layer being doped with the impurities at a third impurity density lower than the first impurity density, wherein the impurities within the second polysilicon layer at the second impurity density substantially prevent migration of the void.