Patent ID: 6553528
Filing Date: 2003-04-22
Classification: G01R,G11C

Abstract:
A test circuit for a semiconductor integrated circuit, comprising:a plurality of comparison means for comparing test results transferred from an object circuit for operational test of said semiconductor integrated circuit with expected data that have been prepared in advance; a plurality of control means for generating a control signal that indicates whether or not said test results are outputted based on comparison results transferred from each of said plurality of comparison means; and a plurality of selection means for selecting a part of said test results based on said control signal transferred from said plurality of control means; wherein each of said plurality of comparison means, said plurality of control means, and said plurality of selection means are incorporated in said test circuit and each operate on a predetermined number of outputs from a total number of outputs from an object circuit and each of said plurality of control means generates said control signal based on said comparison result that indicates only when said test results are not equal to said expected data to make test time short, and outputs said generated control signal to said corresponding selection means in order to output said test results including information about where mismatch of output occurs to the outside.