Patent ID: 6828545
Filing Date: 2004-12-07
Classification: H01L

Abstract:
A hybrid microelectronic array structure comprising:a microelectronic integrated circuit array comprising an array of microelectronic integrated circuits, each of the microelectronic integrated circuits comprising a first supported-structure interconnect location and a second supported-structure interconnect location; a supported array comprising an array of supported islands with each supported island having at least one supported element therein, there being at least one supported element for each of the microelectronic integrated circuits, each of the supported elements comprising a first region and a second region, wherein the first region of each of the supported islands is physically discontinuous from the first region of each of the other supported islands, and the second region of each of the supported islands is physically discontinuous from the second region of each of the other supported islands; and a bump interconnect structure extending between each of the microelectronic integrated circuits and its respective supported element, each bump interconnect structure comprising a first bump interconnect extending from the first supported-structure interconnect location of each of the microelectronic integrated circuits to the first region of its respective supported element, and a second bump interconnect extending from the second supported-structure interconnect location of each of the microelectronic integrated circuits to the second region of its respective supported element.