Patent ID: 6177316
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method for fabricating a memory structure comprising:forming a metal barrier layer on a core area of a memory structure; andthereafter, performing a contact implantation process on said memory structure to reduce impurity outdiffusion,said contact implantation process including depositing an N+ implant resist strip, said N+ implant including phosphorous ions implanted into said metal barrier layer,said ions in a concentration of between about 8.times.10.sup.14 ion/cm.sup.2 and 2.times.10.sup.15 ion/cm.sup.2, and implanted to a depth of between about 250 and 1000 .ANG. below the surface of the metal barrier layer with a tilt of 0 degrees and a twist of 35 degrees.