Patent ID: 6922372
Filing Date: 2005-07-26
Classification: G11C

Abstract:
1. A semiconductor memory device for performing input/output of data in synchronization with an external clock signal, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a clock generating circuit generating an internal clock signal by delaying said external clock signal by a predetermined delay amount; and a data output circuit providing a data signal read from said memory cell array to an output node in synchronization with said internal clock signal, wherein said data output circuit includes: each of said plurality of first current drive portions forms a current path between the voltage corresponding to said first level and said output node in accordance with said drive power switch signal received on the corresponding control node, each of said plurality of second current drive portions forms a current path between the voltage corresponding to said second level and said output node in accordance with said drive power switch signal received on the corresponding control node, and said clock generating circuit includes: