Patent ID: 8673543
Filing Date: 2014-03-18
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a wiring pattern on a semiconductor substrate, including steps of: preparing an exposure mask having an opening part in a region corresponding to the wiring pattern; forming a hard coating film of a hard coating material on the semiconductor substrate; applying a positive resist onto the hard coating film; exposing the positive resist using the exposure mask; forming a resist pattern by developing the positive resist to remove an exposed part; patterning the hard coating film using the resist pattern; removing the resist pattern; sequentially embedding an insulation film and a wiring pattern in an opening part of the hard coating film; and removing the hard coating film, wherein the step of exposing the positive resist employs EUV light, and wherein the exposure mask is a reflective type of mask having a reflecting surface for reflecting the exposure light in the region corresponding to the wiring pattern, and an absorbing surface for absorbing the exposure light in a region other than the above region, wherein the area occupied by the reflecting surface of the exposure mask is less than 20% with respect to the total region area of the exposure mask, and wherein a flare level of the exposure aligner used for exposure is equal to or higher than 3% and lower than 8%.