Patent ID: 6806131
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A process for manufacturing a DMOS transistor (100) with a semiconductor body (5), which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type, and a first well region (20) of a first conductivity type enclosing the source region (10), and a second well region (19) of a second conductivity type enclosing the drain region, wherein the first well region (20) and the second well region (19) are separated by a body region (18) of a first conductivity type, and a gate region (35) is formed on the surface of the surface layer of the semiconductor body (5), which gate region extends from the source region across the first well region (20),said method comprising: starting on the surface of the semiconductor body (5), forming a trench-shaped structure in the surface layer, such that the trench-shaped structure includes a floor region, source-end side wall extending from the floor region to the surface on a first side of the trench-shaped structure proximate to the source region, and a drain-end side wall on a second side of the trench-shaped structure proximate to the drain region, wherein at least one of the side walls slopes non-perpendicularly relative to the surface so that the trench-shaped structure has a tapering cross-section with a greater width at the surface than at the floor region; producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure; producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure; producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure; and forming, in the surface layer, the source region and the drain region of the second conductivity type, the first well region of the first conductivity type enclosing the source region, and the second well region of the second conductivity type enclosing the drain region, with the body region of the first conductivity type being between and separating the first and second well regions, and forming the gate region the surface of the surface layer so that the gate region extends from the source region over the first well region.