Patent ID: 7049883
Filing Date: 2006-05-23
Classification: G01L,H03H

Abstract:
1. A low-pass filter for detecting voltage variations of an input signal supplied to an input terminal thereof and producing and output signal indicative of said voltage variations, said low-pass filter including a switched capacitor circuit having clock signal generating circuit for generating a first clock pulse signal and a second clock pulse signal of mutually identical frequency and differing phase, first, second and third capacitors, a first plurality of switching elements each controlled by said first clock pulse signal, and a second plurality of switching elements each controlled by said second clock signal, an operational amplifier for producing said output signal from an output terminal thereof, a first capacitor selectively connectable between said low-pass filter input terminal and an input terminal of said operational amplifier via respective ones of said first and second pluralities of switching elements, a second capacitor selectively connectable between an input terminal of said operational amplifier and said output terminal of said operational amplifier via respective ones of said second plurality of switching elements, a third capacitor connected between said input terminal and output terminal of said operational amplifier, said low-pass filter configured to operate successively in: a first condition in which said first clock pulse signal is at an active level whereby each of said first plurality of switching elements is held in a conducting status and said second clock pulse signal is at an inactive level whereby each of said second plurality of switching elements is held in a non-conducting status, with said first capacitor being thereby charged to a voltage of said input signal, said second capacitor being discharged to a voltage of zero, and no charging or discharging of said third capacitor is performed, a second condition, in which each of said first clock pulse signal and second clock pulse signal is at said inactive level, whereby no charging or discharging of said first, second or third capacitors is performed, a third condition in which said first clock pulse signal is at said inactive level and said second clock pulse signal is at said active level, whereby each of said second plurality of switching elements is held in a conducting status and said second and third capacitors thereby become connected in parallel with one another, said first capacitor is discharged to a voltage of zero, and a discharge current from said first capacitor acts to charge said second and third capacitors, and a fourth condition in which each of said first clock pulse signal and second clock pulse signal is at said inactive level, whereby no charging or discharging of said first, second or third capacitors is performed, with said first condition being subsequently returned to; wherein said clock signal generating circuit comprises means for controlling said first and second pulse signals to set a duration of each interval of the second condition at a value whereby a decrease of stored charge in said first capacitor occurring within said interval, expressed as a percentage decrease with respect to an amount of said stored charge at commencement of said interval, is predetermined to be substantially equal to a maximum permissible amount of error of DC gain of said low-pass filter, with said error being no greater than 3 percent of a predetermined value of said DC gain, said duration extending between a transition of said first clock pulse signal from said active level to said inactive level and an immediately succeeding transition of said second clock pulse signal from said inactive level to said active level.