Patent ID: 7218554
Filing Date: 2007-05-15
Classification: G11C

Abstract:
1. A method of using a non-volatile memory that includes a substrate, a gate, a charge-trapping layer between the substrate and the gate, and a first and a second doped regions as source/drain regions, comprising: (a) performing a plurality of write/erase cycles to the non-volatile memory with electron-injection/hole-injection, while hard-to-erase electrons are accumulated in a specific portion of the charge-trapping layer during the write/erase cycles; and (b) measuring an erase-state threshold voltage (Vt) of the non-volatile memory to determine whether a difference between the erase-state Vt and an initial erase-state Vt of the non-volatile memory exceeds a predetermined value or not; and (c) going to step (a) if the difference does not exceed the predetermined value, or performing a refresh step that utilizes band-to-band tunneling hot hole (BTBTHH) effect to inject holes into the specific portion of the charge-trapping layer to annihilate the hard-to-erase electrons and then going to step (a) if the difference exceeds the predetermined value.