Patent ID: 7752578
Filing Date: 2010-07-06
Classification: G06F

Abstract:
1. A method for placement of gate-level circuit components in an integrated circuit, the integrated circuit comprising a plurality of rows of circuit blocks, each row of circuit blocks comprising a plurality of sub-rows of circuit blocks, the method comprising: identifying a first sub-row of the integrated circuit comprising a bus and a first instance of a gate-level circuit component; identifying at least one candidate operation to apply to the first sub-row, wherein the candidate operation affects a placement of a circuit block or a component in the first sub-row; computing a first metric to evaluate each of said at least one candidate operation when applied to the first sub-row; and implementing one of said at least one candidate operation based on the computed first metric, wherein at least one or more of the identifying steps, the computing or the implementing steps are carried out by a computer.