Patent ID: 6057575
Filing Date: 2000-05-02
Classification: G11C,H01L

Abstract:
An electrically erasable and programmable read only memory cell comprising:a semiconductor substrate having a first region and a second region, with a channel therebetween, with said second region having a greater dopant concentration than said first region;a select gate over said substrate and insulated therefrom and extending over a first portion of said channel;a floating gate having a first edge, and a second edge with a first portion over said select gate and insulated therefrom, and a second portion insulated from said substrate and extending over a second portion of said channel and over a portion of said second region and lies between said select gate and said second region; anda control gate over said floating gate and insulated therefrom, and having a first edge and a second edge aligned with the first edge and the second edge of said floating gate.