Patent ID: 7684278
Filing Date: 2010-03-23
Classification: G06F

Abstract:
1. Apparatus for providing first in first out (FIFO) memories in an integrated circuit, comprising: a block random access memory (BRAM) circuit embedded in the integrated circuit, the BRAM circuit having at least one port responsive to a respective at least one BRAM clock signal; FIFO logic configured to implement a plurality of FIFOs in the BRAM circuit, the FIFO logic having a plurality of output interfaces; and multiplexer logic configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal, each of the at least one BRAM clock signal having at least twice the frequency of a respective one of the at least one FIFO clock signal.