Patent ID: 7577037
Filing Date: 2009-08-18
Classification: G06F,G11C,Y02D

Abstract:
1. A non-volatile memory device, including: an array of memory cells, each capable of storing at least N bits of data, where N is an integer greater than one; and a set of read/write circuits connected to the array for operating on a group of memory cells of said array in parallel, each read/write circuit having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, wherein, in a write process, the read/write circuits can store a first, N-bit set of data for a first group of memory cells in N data latches in each of the corresponding sets of data latches and write the first set of data into said first group of memory cells, wherein the writing includes alternating program and verify phases, and wherein once the group of memory cells have been programmed past one or more but less than all of the verify levels, one or more of the N data latches in each of the corresponding groups of data latches is released prior to completing said writing, and wherein the read/write circuits can transfer a second set of data into the released data latches prior to completing said writing.