Patent ID: 6065033
Filing Date: 2000-05-16
Classification: G06F

Abstract:
An apparatus for summing a plurality of columns of binary bits to produce a plurality of partial sum and carry bits, the bits of a particular column being of the same orders of magnitude and the bits of different columns differing in order of magnitude, comprising:a full adder, the full adder receiving three bits of the particular column as first input to produce a first sum bit and a first carry bit as output;a half adder receiving two bits of the particular column as second input to produce a second sum bit and a second carry bit as output, the half and full adders being configured as a plurality of interconnecting column adders, each column adder summing bits of the input of at least one column and generating a partial sum and carry bit, each column adder having a plurality of stages; anda plurality of conductors for interconnecting the stages of each column adder with other stages in the same column adder and with stages in other column adders,wherein the half adder is used in the particular column when the particular column has two remainder bits after dividing the number of bits in the particular column by three, and an adjacent column having bits with a lower order of magnitude has more bits than the particular column.