Patent ID: 6369622
Filing Date: 2002-04-09
Classification: H03B

Abstract:
A clock doubler circuit, comprising:(a) a phase shifter network for receiving an input clock signal at an input node and for generating first and second phase-shifted clock signals which are 90Â° apart and which have the same frequency as the input clock signal, wherein the input clock signal does not contain higher order harmonics; (b) first and second voltage limiters for receiving the first and second phase-shifted clock signals, respectively, and for generating first and second squared clock signals, respectively, which are 90Â° apart and which have the same frequency as the input clock signal, wherein a respective threshold of each of said voltage limiters is approximately equal to an output common-mode voltage of said phase shifter network; and (c) a combiner for combining the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.