Patent ID: 6965535
Filing Date: 2005-11-15
Classification: G11C

Abstract:
1. An integrated semiconductor memory comprising: a memory cell array subdivided into individual cell blocks; primary sense amplifiers (SA), coupled to a bit line (BL) of a respective cell block and connected to a local data line (LDQ) common to the primary sense amplifiers by means of a respective CSL switch assigned to the primary sense amplifier in response to a CSL signal fed to said switch; and a main data line (MDQ), which has, per cell block, an MDQ/LDQ switch arrangement for connecting the main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal, wherein a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal applied to it with the MDQ/LDQ switch signal of this cell block and thereby activates the CLS switches for connecting the primary sense amplifiers (SA) assigned thereto to the common local data line (LDQ) only in cell blocks in which a word line has been activated.