Patent ID: 8339850
Filing Date: 2012-12-25
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cells arranged in rows and columns, said each memory cell including: a memory transistor having a floating gate formed over a substrate region, and a memory gate disposed over the floating gate; an assist gate transistor having an assist gate disposed adjacent to the floating gate and the memory gate and coupled in series to the memory transistor; and an embedded erase gate formed in a surface of a device isolation region formed in the surface of the substrate region, said each memory cell storing therein data on a nonvolatile basis according to an amount of an electrical charge accumulated in the floating gate; a plurality of memory gate lines disposed corresponding to the respective rows of the memory cells and coupled to their corresponding memory gates of the memory cells in the corresponding rows; a plurality of assist gate lines disposed corresponding to the respective rows of the memory cells and coupled to their corresponding assist gates in the corresponding rows; a plurality of embedded erase gate wirings disposed corresponding to the respective columns of the memory cells and coupled to their corresponding embedded erase gates in the corresponding columns; a plurality of source lines disposed corresponding to the respective columns of the memory cells and coupled to their corresponding first conduction nodes of the memory transistors of the memory cells in the corresponding columns; a plurality of bit lines disposed corresponding to the respective columns of the memory cells and coupled to their corresponding second conduction nodes of the assist gate transistors of the memory cells in the corresponding columns; and a control circuit which controls an operation designated to each memory cell designated in accordance with an operation mode instruction and an address signal, wherein the control circuit includes: an erase controller which, when an erase operation is designated, designates voltages supplied to the source line, the memory gate line and the embedded erase gate wiring for each selected memory cell and controls the erase operation; and a read controller which designates voltages necessary for reading, supplied to the assist gate line and the bit line for the selected memory cell and controls a read operation, wherein the erase controller and the read controller are respectively capable of operation in parallel, wherein said semiconductor device includes: a voltage generator which generates a designated voltage in accordance with a voltage selection signal outputted from each of the erase controller and the read controller; an erase circuit which transfers the erase voltage outputted from the voltage generator to the embedded erase gate wiring of each selected memory cell; and a read circuit which supplies the read voltage outputted from the voltage generator to each selected memory cell to read out data stored in the selected memory cell, and wherein the read circuit is operation-controlled by the control circuit so as to read the stored data during application of the erase voltage by the erase circuit.