Patent ID: 7135906
Filing Date: 2006-11-14
Classification: H03K,H03L

Abstract:
1. A delay circuit comprising: a first delay line circuit having a plurality of stages of delay units; a second delay line circuit having a plurality of stages of delay units; a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit; said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal; the delay unit of each stage of said second delay line circuit, including a logic circuit receiving an output signal of the transfer circuit associated with the delay unit and an output signal of a preceding stage and outputting the result of logical operation of the input signals to a following stage, one of a plurality of the transfer circuits, receiving respective outputs of odd-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal; one of a plurality of transfer circuits, receiving respective outputs of even-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal; and the rise timing and the fall timing of an output signal of said second delay line circuit are variably set with respect to the rising and fall of the signal supplied to said first delay line circuit.