Patent ID: 9047935
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A read timing generation circuit, comprising: an address transition detection unit, an address triggering and decision unit, an ATD timing generation unit and a following-stage timing generation unit, wherein the address transition detection unit has input terminals receiving in parallel a plurality of bits of an address, and is adapted to generate a corresponding set of response pulses; the address triggering and decision unit has input terminals connected in parallel to output terminals of the address transition detection unit, and is adapted to generate a single trigger and decision signal; the ATD timing generation unit has an input terminal receiving the trigger and decision signal, and is adapted to generate an address transition detection signal; the following-stage timing generation unit has an input terminal receiving the address transition detection signal, and is adapted to generate subsequent control signals, the address transition detection unit comprises a plurality of address transition detection branches, each of which comprises a first NOT gate, a second NOT gate and a first XNOR gate; and in each of the address transition detection branches, an input terminal of the first NOT gate receives one of the plurality of bits of the address, an output terminal of the first NOT gate is connected to an input terminal of the first XNOR gate via the second NOT gate; the other input terminal of the first XNOR gate is connected to the bit of the address; and an output terminal of the first XNOR gate outputs a response pulse corresponding to the bit of the address.