Patent ID: 8451160
Filing Date: 2013-05-28
Classification: H03M

Abstract:
1. A pipeline analog to digital converter, comprising: a first passive sampling circuit that includes an input terminal coupled to an analog input signal, wherein the first passive sampling circuit outputs a first sample voltage that is responsive to the analog input signal; a second passive sampling circuit that includes an input terminal coupled to the analog input signal, wherein the second passive sampling circuit outputs a second sample voltage that is responsive to the analog input signal; wherein the first passive sampling circuit and the second passive sampling circuit are clocked such that the first sample voltage and the second sample voltage are time-interleaved; and a multiplying analog to digital converter (MADC) circuit that receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate an output voltage; wherein the first passive sampling circuit receives the analog input signal when a first sample clock signal is in a logic high state, and wherein the second passive sampling circuit receives the analog input signal when a second sample clock signal is in a logic high state; and wherein the (MADC) receives the first sample voltage when a first hold clock signal is in a logic high state, and wherein the (MADC) receives the second sample voltage when a second hold clock signal is in a logic high state.