Patent ID: 9201654
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A processor comprising: a branch instruction history table (BHT) storing initial direction predictions for conditional branch instructions stored in an instruction cache, each direction prediction being one of taken and not taken; a branch instruction target address cache (BTAC) storing, for any conditional branch instructions previously predicted as taken, target addresses and override bits, said branch instruction history table (BHT) and said branch instruction target address cache (BTAC) each being indexed by instruction cache addresses; an instruction fetch address register essentially simultaneously submitting a specific address for a specific instruction in said instruction cache to said instruction cache, said branch instruction history table (BHT) and said branch instruction target address cache (BTAC) such that reading of said branch instruction history table (BHT), said branch instruction target address cache (BTAC) and said instruction cache occurs in parallel during a same clock cycle, a direction predictor in communication with said branch instruction history table (BHT) and said branch instruction target address cache (BTAC), said direction predictor performing the following: