Patent ID: 6819578
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A content addressable memory device comprising:a first plurality of match lines; a second plurality of bit lines; a third plurality of memory cells, each memory cell of said third plurality coupled to at least one of said bit lines and to at least one of said match lines; and a fourth plurality of match line drivers, each driver of said plurality having an input node and an output node, said respective input node of each driver of said plurality of match line drivers being coupled to a respective one match line of said plurality of match lines, each said output node adapted to output a match line output voltage, said match line output voltage adapted to assume an instantaneous value in a range between a first reference potential and second potential, said match line output voltage taken with respect to said reference potential, each bit line of said plurality of bit lines adapted to assume an instantaneous voltage within a range between said first reference potential and a third potential, said third potential being closer to said reference potential than said second potential.