Patent ID: 7446379
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A transistor, comprising: a source and a drain disposed in first and second recesses defined in a top surface of a workpiece, said first and second recesses having a first width and a first depth, the source and drain being separated by a channel region, wherein the source and drain each consisting essentially of a dopant-bearing metal region filling said recess of the workpiece to a thickness no greater than said first depth, and a doped region disposed in the workpiece adjacent each dopant-bearing metal region, each of said dopant-bearing metal regions comprising an edge; a gate dielectric comprising sidewalls, said gate dielectric disposed over the channel region; a gate comprising sidewalls disposed over the gate dielectric, said gate sidewalls substantially aligned with said gate dielectric side walls; a first spacer having outside sidewalls said first spacer disposed over the sidewalls of the gate dielectric, such that said outside sidewalls of said first spacer are substantially aligned with said edges of said dopant-bearing metal region; and a second spacer disposed abutting the outside sidewalls of the first spacer, said second spacer having a width less than said first width.