Patent ID: 6430197
Filing Date: 2002-08-06
Classification: H04J,H04L,H04Q

Abstract:
In an asynchronous transfer mode (ATM) system having a plurality of physical layer devices for transmitting ATM cells at low speed and an ATM layer device for transmitting ATM cells at high speed, an ATM cell multiplexing/demultiplexing apparatus comprising:a decoding/demultiplexing unit for extracting routing information from the header of each said ATM cell transmitted from the ATM layer device and demultiplexing the ATM cell according to the routing information extracted into the plurality of physical layer devices; an ATM cell multiplexing unit for multiplexing the ATM cells transmitted from the plurality of physical layer devices into the ATM layer device; a receiving routing unit for inserting routing information within a header of each said ATM cell multiplexed by the ATM cell multiplexing unit; and a micro bus interface unit for interfacing the ATM layer 20 device and the plurality of physical layer devices with respect to system operation and management information and transmitting an interrupt signal of each physical layer device to the ATM layer device; the receiving routing unit comprises: a D-flip-flop for buffering a signal for indicating a first byte of each ATM cell received within the ATM layer device according to a clock provided when the ATM layer device receives a cell; first to fourth AND gates for performing each AND operation with respect to an output signal of the D-flip-flop and respective multiplexing control signals generated by a decoder in the ATM cell multiplexing unit; first to fourth OR gates for selectively performing each OR operation with respect to respective specified bits in a header of each cell multiplexed by the ATM cell multiplexing unit and respective output signals of the first to fourth AND gates and generating the routing information for indicating a physical layer device which has transmitted the multiplexed cell as a result of the OR operation.