Patent ID: 7126384
Filing Date: 2006-10-24
Classification: G01R

Abstract:
1. A peak detection circuit with double peak detection stages, comprising: an analog peak detector for receiving an analog input signal, detecting a peak value of the analog input signal periodically with a first duration of time, and outputting an analog peak signal; an analog-to-digital convertor for receiving the analog peak signal, and converting the analog peak signal into a digital signal in accordance with a sampling clock having a duration of time substantially equal to the first duration of time; and a digital peak detector for receiving the digital signal, detecting a peak value of the digital signal periodically with a second duration of time longer than the first duration of time, and outputting a digital peak signal; wherein the analog peak detector comprising: a first detector for receiving the analog input signal, operating when a first control signal is enabled, and outputting a first peak signal; a second detector for receiving the analog input signal, operating when a second control signal is enabled, and outputting a second peak signal; and a multiplexer for receiving the first peak signal and the second peak signal, and selecting the first peak signal or the second peak signal to be output as the analog peak signal according to a selection signal.