Patent ID: 6674142
Filing Date: 2004-01-06
Classification: B82Y,H01L

Abstract:
A semiconductor memory device, comprising:first memory elements to store a first state or a second state according to a change in resistance value, each of said first memory elements comprising one terminal and another terminal, said first memory elements arranged in parallel with each other; a first wiring connected with said one terminal of each of said first memory elements, said first wiring being used commonly to the first memory elements, the first wiring comprising a first terminal and a second terminal; a second wiring formed in parallel with said first wiring and connected with said other terminal of each of said first memory elements, said second wiring being used commonly to the first memory elements, the second wiring comprising a third terminal corresponding in position to the first terminal and a fourth terminal corresponding in position to the second terminal; a constant-voltage generating circuit connected to the first terminal of the first wiring; and a switching element connected to the fourth terminal of the second wiring, wherein said first state or said second state stored in one memory element selected from said first memory elements is read out by delivering an electric current from one of said first and second wirings via said one memory element selected from said first memory elements to the other of said first and second wirings.