Patent ID: 6222773
Filing Date: 2001-04-24
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a plurality of word lines;a plurality of bit lines;at least one source line;a plurality of nonvolatile memory cells each of which includes a gate electrode, drain electrode and source electrode and in each of which the gate electrode is connected to a corresponding one of said plurality of word lines, the drain electrode is connected to a corresponding one of said plurality of bit lines and the source electrode is connected to said source line;a row decoder for selecting one of said plurality of word lines at the time of data programming;a cell selection circuit connected to the bit lines, and for simultaneously selecting any number of bit lines from said plurality of bit lines, said cell selection circuit including a column decoder and column gates; andprogramming circuit for increasing the number of programming bits with the progress of programming when data of a plurality of bits is programmed into a plurality of memory cells which are simultaneously selected by said cell selection circuit, the programming circuit connected to the column gates.