Patent ID: 6609145
Filing Date: 2003-08-19
Classification: G06F

Abstract:
A computer system, comprising:a bus; a host memory controller coupled to the bus; a host memory coupled to the host memory controller for storing command prioritization code; a bus master coupled to the bus; a resource coupled to the bus master; and a host processor coupled to the bus for executing the command prioritization code to perform the steps of: detecting a priority command indicating a priority level of a background command for the resource by the bus master; converting the priority level into a pause duration indicative of a time to delay a foreground command for the resource by the host processor and a pause interval indicating a number of foreground commands out of a predetermined number of foreground commands to process before delay of the foreground command; determining if the foreground command is to be delayed based on the pause interval; and delaying the foreground command for the pause duration if the foreground command is to be delayed.