Patent ID: 8082423
Filing Date: 2011-12-20
Classification: G06F

Abstract:
1. A computer implemented method for a distributed flush mechanism, the method comprising: receiving an instruction in a first execution unit of a plurality of execution units, wherein every execution unit of the plurality of execution units is configured to issue control signals and generate a flush vector directly to every other execution unit of the plurality of execution units, wherein each bit in the flush vector is indicative of all of a thread value, a slot value, and a type value, wherein the thread value indicates an origination thread from which the instruction originated, wherein the thread value indicates one or more threads, wherein the slot value indicates one of an older instruction plus a younger instruction when the slot value is a first slot value and indicates only a younger instruction when the slot value is a second slot value, wherein the type value indicates an instruction type, wherein the type value indicates the instruction completes execution and the refetch should start at a next instruction when the type value is a first type value and indicates the instruction did not complete execution and the instruction must be refetched when the type value is a second type value, wherein each execution unit controls a corresponding one of a plurality of local register files, wherein each execution unit is associated with a corresponding one of a plurality of registers, wherein each of the plurality of registers is selected from one of a general purpose register, a floating point register, a special purpose register, a vector multi-media register, or a conditional register, and wherein each execution unit in the plurality of execution units is one of a load/store unit, a branch unit, a completion unit, a floating point unit, a fixed point unit, or a vector multi-media unit; determining, before completing execution of the instruction, if the instruction causes an instruction flush, wherein a cause of the instruction flush is an exception; in response to a determination that the instruction causes the instruction flush, issuing the flush vector from the first execution unit directly to all other execution units of the plurality of execution units and issuing a control signal from the first execution unit to block all register updates in the local register file corresponding to the first execution unit; in response to the issuing the flush vector from the first execution unit directly to all other execution units of the plurality of execution units, issuing a control signal from all other execution units of the plurality of execution units to their corresponding local register files in order to block register updates, wherein the control signal comprises the flush vector, wherein a central collection point is not required to re-distribute the flush vector to the plurality of execution units, wherein a load/store unit receives the flush vector and blocks a general purpose register in the plurality of registers from being updated, and wherein a branch unit receives the flush vector and blocks a conditional register in the plurality of registers from being updated; flushing younger instructions based on the flush vector; and blocking all register updates in the plurality of registers.