Patent ID: 7533243
Filing Date: 2009-05-12
Classification: G06F

Abstract:
1. A VLIW (Very Long Instruction Word) processor that decodes and executes an instruction that has at least two operation fields, of which a first operation field only includes one operation code without any operands and a second operation field includes a combination of one operation code and at least one operand used in an operation indicated by the second operation field, the VLIW processor comprising: first decoding unit configured to decode the operation code in the first operation field; first execution unit configured to execute an operation indicated by the operation code in the first operation field in accordance with a decoding result of the first decoding unit; second decoding unit configured to decode the operation code in the second operation field; and second execution unit configured to execute the operation indicated by the operation code in the second operation field on data which is indicated by the operands in the second operation field, in accordance with a decoding result of the second decoding unit.