Patent ID: 6046624
Filing Date: 2000-04-04
Classification: G05F

Abstract:
An internal power signal generating circuit for a semiconductor memory device comprising:a driver for reducing the voltage of an external power signal responsive to a bias signal, thereby generating an internal power signal, the driver having an input terminal for receiving the bias signal, a power terminal for receiving the external power signal, and an output terminal for transmitting the internal power signal; anda feedback loop coupled to the driver for generating the bias signal responsive to the internal power signal and a reference signal;wherein the feedback loop reduces the rate at which the bias signal changes;wherein the feedback loop includes:a comparator having a first input terminal coupled to the output terminal of the driver to receive the internal power signal, a second input terminal coupled to receive a reference signal, and an output terminal for transmitting a comparison signal; anda bias circuit having an input terminal coupled to the output terminal of the comparator for receiving the comparison signal, and an output node coupled to the input terminal of the driver; andwherein the bias circuit includes:a pair of transistors arranged in a push-pull configuration to generate the bias signal, each transistor having an input terminal coupled to receive the comparison signal and an output terminal coupled to the output node of the bias circuit;a third transistor coupled in series with the pair of transistors; anda voltage divider having an input terminal coupled to the input terminal of one of the pair of transistors and an output terminal coupled to an input terminal of the third transistor.