Patent ID: 6518103
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for fabricating a NROM, comprising the steps of:providing a substrate that has a charge trapping layer formed thereon; forming sequentially a bottom anti-reflective layer (BARC) and a photoresist pattern on the charge trapping layer; conducting an etching process to remove an exposed bottom anti-reflective layer and an exposed charge trapping layer with the photoresist pattern as a mask, the etching process being conducted in an etching chamber equipped with a source power supply and a bias power supply, while a power ratio of the source power supply to the bias power supply ranges from 1.5 to 3; forming a buried drain in the exposed substrate; removing the photoresist pattern and the bottom anti-reflective coating; forming an insulating layer on the buried drain; forming a conductive layer on the substrate to cover the charge trapping layer and the insulating layer; and patterning the conductive layer to form a plurality of gate structures.