Patent ID: 9003122
Filing Date: 2015-04-07
Classification: G06F,H03K,H03M,Y02D

Abstract:
1. A data processing system comprising: a central processing unit executing program instructions to manipulate data; a first level data cache connected to said central processing unit temporarily storing in a plurality of first cache lines data for manipulation by said central processing unit; a second level memory connected to said first level cache including second level cache temporarily storing in a plurality of second cache lines data for manipulation by said central processing unit and a second level local memory directly addressable by said central processing unit; and a direct memory access unit connected to said central processing unit controlling data transfer, said direct memory access unit operating under control of said central processing unit to control data transfers including transferring data into and out of said second level local memory; a first level cache controller connected to said first level cache capable controlling data transfers into and out of said first level cache including said first level cache controller enabling a write of said snoop write data into a corresponding entry in said first victim buffer when said victim comparator detects a match between a snoop write address and a first victim address in said victim buffer; a second level memory controller connected to said first level cache controller and said second level cache controlling data transfers into and out of said second level cache, said second level cache controller including said second level memory controller enabling a write of said direct memory access write data into a corresponding entry in said second victim buffer if said second victim comparator detects a match between a direct memory access write address and a second victim address in said second victim buffer and enabling a snoop write to said first level cache controller if said second victim comparator does not detect a match between a direct memory access write address and a second victim address in said second victim buffer.