Patent ID: 8665928
Filing Date: 2014-03-04
Classification: H04L

Abstract:
1. A circuit for generating an output clock signal synchronized to an input clock signal, comprising: a reference clock port configured to receive a reference clock signal; a crystal oscillator coupled to the reference clock port and configured to generate the reference clock signal, the reference clock signal having a fixed crystal frequency; a phase-locked loop coupled to the reference clock port and configured to generate, from the reference clock signal, at least one reference phase having the reference frequency, and align a first division of the reference clock signal by a first integer and a second division of the at least one reference phase by a second integer; wherein the phase-locked loop is further configured to align the first and second divisions at a synchronization frequency that nominally equals the fixed crystal frequency divided by the first integer and the reference frequency divided by the second integer; a phase interpolator coupled to the reference clock port and configured to generate the output clock signal that, as a function of a variable control value, is an interpolation between two of a plurality of reference phases; wherein the plurality of reference phases are generated from the at least one reference phase and from the reference clock signal and have a reference frequency; and a phase controller coupled to the phase interpolator and configured to generate the variable control value providing a phase rotation rate, wherein an output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate; and wherein the output frequency matches an input frequency of the input clock signal.