Patent ID: 8924694
Filing Date: 2014-12-30
Classification: G06F,H04L

Abstract:
1. A packet modification system comprising: a packet slicer to receive a complete packet at the packet modification system and slice the complete packet into a plurality of packet portions; a transmit-in-data buffer to receive and store the plurality of packet portions from the packet slicer; the transmit-in-data buffer to pass, in parallel, the plurality of packet portions to a modification engine of the packet modification system; a packet modification engine to effect a modification to one or more of the plurality of packet portions via a programmable processor core coupled with the packet modification engine by implementing at least the following operational stages at the programmable processor core: wherein the data fetch stage follows the first, second, third, and fourth pointers to retrieve the data specified for use in completing the modification to the one or more packet portions via the programmable processor core; and a packet assembler to re-assemble the plurality of packet portions, including the one or more packet portions having been modified, into a modified complete packet for egress transmission from the packet modification system.