Patent ID: 7342530
Filing Date: 2008-03-11
Classification: H03M

Abstract:
1. A successive approximation analog/digital converter converting an analog input signal into a digital output value by means of a plurality of successive conversion cycles, comprising: at least one first input for injecting an analog input signal; a controllable capacitive network which is connected downstream of the first input and which is divided into at least two capacitive subnetworks; at least two parallel-connected and parallel-operating comparators for defining a number of comparator thresholds which number corresponds to the number of parallel comparators; wherein the comparators are respectively connected downstream of one of the capacitive subnetworks and wherein the comparators output a corresponding number of digital intermediate signals on the basis of the comparisons in the comparators; a register set by the intermediate signals; wherein the register buffer-stores digital intermediate values for the respective intermediate signals and wherein the register produces control signals for actuating the capacitive subnetworks in response to the content of the intermediate signals; and a control circuit which produces a further control signal, which can be used to short circuit at least two of the capacitive subnetworks at the end of an analog/digital conversion and to read out the total electrical charge of the shorted capacitive subnetworks via the comparators.