Patent ID: 8629467
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first metal base plate having a first top surface, and a first bottom surface opposite the first top surface; a second metal base plate having a second top surface, and a second bottom surface opposite the second top surface; a first semiconductor chip including a first IGBT and having a first obverse surface, a first reverse surface opposite the first obverse surface, a first emitter electrode and a first gate electrode of the first IGBT formed over the first obverse surface, and a first collector electrode of the first IGBT formed over the first reverse surface; a second semiconductor chip including a second IGBT and having a second obverse surface, a second reverse surface opposite the second obverse surface, a second emitter electrode and a second gate electrode of the second IGBT formed over the second obverse surface, and a second collector electrode of the second IGBT formed over the second reverse surface; a third semiconductor chip including a first diode and having a third obverse surface, a third reverse surface opposite the third obverse surface, a first anode electrode of the first diode formed over the third obverse surface, and a first cathode electrode of the first diode formed over the third reverse surface; a fourth semiconductor chip including a second diode and having a fourth obverse surface, a fourth reverse surface opposite the fourth obverse surface, a second anode electrode of the second diode formed over the fourth obverse surface, and a second cathode electrode of the second diode formed over the fourth reverse surface; a plurality of leads electrically connected to the first, second, third, and fourth semiconductor chips, respectively; a plurality of metal conductors electrically connected to the first, second, third, and fourth semiconductor chips, respectively; and a sealing body sealing the first, second, third, and fourth semiconductor chips, parts of the plurality of leads, and the plurality of metal conductors, wherein the plurality of leads are projected from one lateral side of the sealing body, wherein the first and third semiconductor chips are mounted over the first top surface of the first metal base plate such that the first reverse surface of the first semiconductor chip and the third reverse surface of the third semiconductor chip face the first top surface of the first metal base plate, and the first collector electrode of the first semiconductor chip and the first cathode electrode of the third semiconductor chip are electrically connected to each other via the first metal base plate, wherein the second and fourth semiconductor chips are mounted over the second top surface of the second metal base plate such that the second reverse surface of the second semiconductor chip and the fourth reverse surface of the fourth semiconductor chip face the second top surface of the second metal base plate, and the second collector electrode of the second semiconductor chip and the second cathode electrode of the fourth semiconductor chip are electrically connected to each other via the second metal base plate, wherein a first lead is electrically connected to the first emitter electrode of the first semiconductor chip and the first anode electrode of the third semiconductor chip via a first metal conductor, and electrically connected to the second collector electrode of the second semiconductor chip and the second cathode electrode of the fourth semiconductor chip, wherein a second lead is electrically connected to the first collector electrode of the first semiconductor chip and the first cathode electrode of the third semiconductor chip, wherein a third lead is electrically connected to the second emitter electrode of the second semiconductor chip and the second anode electrode of the fourth semiconductor chip via a second metal conductor, wherein a fourth lead is electrically connected to the first gate electrode of the first semiconductor chip via a third metal conductor, and wherein a fifth lead is electrically connected to the second gate electrode of the second semiconductor chip via a fourth metal conductor.