Patent ID: 6072794
Filing Date: 2000-06-06
Classification: H04J,H04L

Abstract:
A trunk interface unit for interfacing with a digital trunk of a PSTN in the RAS for connecting the PSTN to a different network, comprising:a plurality of line card slots;a plurality of E1 line cards inserted into said line card slots, for extracting and outputting a clock from bit streams received thereinto, generating a link state signal on E1 trunks, and arranging E1 frames according to an E1 system clock, thereby providing an interface of the E1 trunks;a plurality of T1 line cards inserted into said line card slots, for extracting and outputting a clock from bit streams received thereinto, generating a link state signal on T1 trunks, and arranging T1 frames according to a T1 system clock, thereby providing an interface of the T1 trunks;a clock selector for selecting a clock among the clocks outputted from said line cards according to a first control signal, and providing the selected clock as a reference clock;a PLL for generating a main system clock synchronized with a frequency-divided reference clock;a frequency-divider for frequency-dividing the reference clock and the main system clock, providing the frequency-divided reference clock to said PLL, and generating a plurality of system clocks including the E1 system clock from the frequency-divided main system clock;a clock converter for converting the E1 system clock outputted from the frequency-divider into the T1 system clock and providing one of the E1 and T1 system clocks to said E1 or T1 line cards, according to a second control signal;a digital switch for generating forward register data of a seized channel by switching time slots, transmitting PCM data received through each trunk to a modem unit, and transmitting the PCM data received from the modem unit and backward register data to a corresponding channel of said line cards, according to a first control data;an R2 signaling part for decoding the forward register data received from said digital switch according to an R2 signaling protocol, generating the backward register data according to a second control data, and providing the generated backward register data to said digital switch; anda processor for generating and providing the first control signal to said clock selector by discriminating a link state from the link state signals, generating and providing the second control signal to said clock converter by discriminating the kind of said line cards inserted into said line card slots, performing a control sequence corresponding to the discriminated line cards, generating and providing the first control data for the time slots switching to said digital switch, and generating and exchanging the second control data for the R2 signaling with said R2 signaling part.