Patent ID: 6645822
Filing Date: 2003-11-11
Classification: B82Y,G11C,H01L

Abstract:
A method for manufacturing a semiconductor circuit system having a plurality of memory cells in which at least one circuit element is disposed substantially in a crossing area of at least two conductor elements and between the conductor elements, which comprises:forming at least one substrate region with a surface region having an upper side; forming at least one first conductor element and at least one second conductor element substantially on the surface region, the first conductor element and the second conductor element having at least one crossing area, the first conductor element having a first side facing away from the substrate region, and the second conductor element having a second side facing the substrate region; forming at least one circuit element substantially in the crossing area and between the first side and the second side; structuring the circuit element at least partially simultaneously with a structuring of at least one of the first and second conductor elements in a first etching step for the first conductor elements and a respective first part of the circuit element; executing the first etching step in substeps including: a first etching substep, in which: the respective first part of the circuit element is structured up to a surface of a first metallic layer for the first conductor element; and subsequently resulting edge regions of the first part of the circuit element are passivated through oxide deposition using a spacer technique; and a second etching substep, in which the first conductor element is respectively structured up to the upper side of the substrate region to produce a substantially common, flush, vertically extending edge of the first conductor element and the passivation.