Patent ID: 7199644
Filing Date: 2007-04-03
Classification: G05F

Abstract:
1. A bias circuit which generates a bias voltage, comprising: a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first ON-state resistance; a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor; a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal; and a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the first and second control signals turn ON the first and second MOS transistors before the voltage generator outputs the bias voltage, and wherein the first control signal turns ON the first MOS transistor and the second control signal turns OFF the second MOS transistor after the voltage generator outputs the bias voltage.