Patent ID: 6072241
Filing Date: 2000-06-06
Classification: H01L

Abstract:
A semiconductor device having a first area of a high pattern density and a second area of a low pattern density, the high pattern density being higher than the low pattern density, comprising:a semiconductor substrate having the first and the second areas;a gate insulating film formed on said semiconductor substrate;a first gate electrode structure formed on said gate insulating film in the first area;a second gate electrode structure formed on said gate insulating film in the second area;a first laminated insulating film including first and second insulating films, said first insulating film being formed over said semiconductor substrate and covering an upper and side surfaces of said first gate electrode structure, and said second insulating film being formed on said first insulating film and having etching characteristics different from said first insulating film;a second laminated insulating film including third and fourth insulating films, said third and fourth insulating films covering side surfaces of said second electrode structure and being formed by the same processes as said first and second insulating films;first and second pairs of source/drain regions formed in said semiconductor substrate on both sides of said first and second gate electrode structures;an interlayer insulating film formed on the substrate, and covering said first and second laminated insulating films;a first contact hole formed through said interlayer insulating film and said first laminated insulating film, the inner wall of said first contact hole being defined by the first insulating film formed on the side surfaces of said first gate electrode structure and reaching one of said first pair of source/drain regions;a second contact hole formed through said interlayer insulating film, said second contact hole passing a side of said second laminated insulating layer and reaching at least one of said second pair of source/drain regions; andfirst and second source/drain electrodes embedded in said first and second contact holes,wherein said interlayer insulating film does not exist between said first source/drain electrode in said first contact hole and said first gate electrode structure.