Patent ID: 6030548
Filing Date: 2000-02-29
Classification: H01L,Y10S

Abstract:
A semiconductor memory device having two driver transistors, two access transistors and two load transistors formed on a main surface of a semiconductor substrate corresponding to a memory cell region, said semiconductor memory device comprising:a first conductivity type transistor forming said driver transistors and said access transistors,a second conductivity type transistor forming said load transistors, anda polycide layer including a first polysilicon layer forming gate electrodes of said transistors and a second polysilicon layer and a metal silicide layer thereon for connecting a first active region of said first conductivity type transistor and a second active region of said second conductivity type transistor,wherein said metal silicide layer of said polycide layer is in direct contact with said first and second active regions, and said polysilicon layer of said polycide layer does not directly contact with said first and second active regions, andsaid polycide layer forms a power supply wiring.