Patent ID: 6175263
Filing Date: 2001-01-16
Classification: G05F

Abstract:
A back bias generator for a semiconductor device having a triple well structure, comprising:an oscillator for generating a clock signal;a well bias generator coupled to the oscillator for generating a well bias signal in response to the clock signal;a power-supply voltage generator for generating a power-supply voltage;a logic gate coupled to the power-supply voltage generator and the oscillator for generating an oscillating logic signal responsive to the power supply voltage and the clock signal;a pumping circuit coupled between the logic gate and a node for generating a pumping voltage at the node in response to the oscillating logic signal; anda transfer transistor having a first electrode coupled to the node, a bulk coupled to the well bias generator to receive the well bias signal, and a gate and second electrode coupled together, for generating a back bias signal at the second electrode.