Patent ID: 6025254
Filing Date: 2000-02-15
Classification: H01L

Abstract:
A method of forming a low resistance gate electrode structure comprising:forming an insulating layer on a semiconductor substrate;forming a gate electrode over the insulating layer, the gate electrode having sidewall spacers; implanting impurities to form a source region and a drain region;depositing a first conductive material over the substrate;reacting the conductive material to form silicided source and drain regions, and a silicide layer having a first thickness on the gate electrode;depositing a low dielectric constant sacrificial layer over the substrate; removing an uppermost portion of the sacrificial layer until the suicide layer is exposed;depositing a second conductive material over both the sacrificial layer and the silicide layer;forming a silicide layer having a second thickness;removing the unreacted conductive material; and removing the remaining low dielectric constant sacrificial layer.