Patent ID: 6077737
Filing Date: 2000-06-20
Classification: H01L

Abstract:
A process for fabricating a semiconductor memory device having nitride/oxide dielectric layers on a substrate, comprising the steps of:forming one or more field oxide regions on said substrate to define one or more active regions;forming on each said active region a MOSFET comprising a gate oxide layer, a first poly-Si gate electrode layer, and a top dielectric layer;forming a contact window in said top dielectric layer of said MOSFET;forming a second poly-Si layer filling said contact window and covering portions of said top dielectric layer of said MOSFET;patterning said second poly-Si layer to form a bottom electrode of a capacitor;removing oxide from the surface of said poly-Si bottom electrode via a pre-cleaning process;further removing said surface oxide and generating an oxidation-resistant surface region on said poly-Si bottom electrode using an inductive coupled plasma (ICP);depositing a silicon nitride dielectric layer on said ICP-treated poly-Si bottom electrode;forming a silicon oxide dielectric layer on said nitride dielectric layer;depositing a third poly-Si layer on said oxide dielectric layer; andpatterning said third poly-Si layer to form a top electrode of said capacitor.