Patent ID: 6587066
Filing Date: 2003-07-01
Classification: H03M

Abstract:
A method of sampling an input signal in a charge redistribution circuit including a capacitor array comprising N number of capacitors, a selected capacitor M having a weight relative to a total capacitance of the array of Â½M, where M is an integer from 1 to Nâˆ’1, the method comprising the steps of:setting a common mode voltage VCM to approximately (1-Â½M)VDD, where VDD is a supply voltage; coupling top plates of the plurality of capacitors of the array to the common mode voltage; sampling an input signal onto bottom plates of the capacitors, the input signal having a voltage swing between approximately zero volts and VDD; coupling the bottom plate capacitor M to a high reference voltage VREF approximating VDD and the bottom plates of remaining capacitors of the array to a low reference voltage; comparing a top plate voltage at the top plates of the capacitors against a reference voltage of Â½MVDD; and if top plate voltage is above the reference voltage of Â½MVDD, coupling capacitor M and capacitor M+1 to the low reference voltage.