Patent ID: 6629218
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A memory controller comprising:a data buffer having a plurality of data buffer entries; a queue having a plurality of queue entries, each of the plurality of queue entries configured to store a memory request and a pointer to one of the plurality of data buffer entries assigned to the memory request; a control circuit coupled to the queue and the data buffer, wherein the control circuit is configured to assign a first queue entry of the plurality of queue entries and a first data buffer entry of the plurality of data buffer entries to a first memory request, and wherein the control circuit is configured to cause the first queue entry to store a first pointer to the first data buffer entry; and a channel control circuit configured to interface to a memory, the channel control circuit coupled to receive the first memory request and the first pointer from the queue, wherein the channel control circuit is configured to acknowledge the first memory request by returning the first pointer to the queue.