Patent ID: 6750870
Filing Date: 2004-06-15
Classification: G06F

Abstract:
A computer system, comprising:a system processor to generate graphics data; a system memory operably coupled to the system processor, the system memory comprising a plurality of addressable storage locations, wherein the graphics data are stored in some of the plurality of addressable storage locations in the system memory; a graphics controller to generate video display data from the graphics data for display on a video display; a core logic chipset operably coupled to the system processor, to the system memory, and to the graphics controller; and a graphics address remapping table (GART) comprising a plurality of GART entries, each of the plurality of GART entries comprising an address pointer to a corresponding addressable storage location of the graphics data in the system memory, wherein each of the plurality of GART entries comprises a plurality of bits, wherein the number of the plurality of bits of each of the plurality of GART entries is based on an addressing capability of the graphics controller, and wherein the core logic chipset uses the plurality of GART entries for remapping the graphics data into an graphics device address space for use by the graphics controller in generating the video display data.