Patent ID: 7930360
Filing Date: 2011-04-19
Classification: G06F,G06Q,H04L

Abstract:
1. A secure processing unit, the secure processing unit including: an internal memory unit; a processor including a memory management unit and a plurality of security registers, the memory management unit further including a level-one page table, the level-one page table including a plurality of level-one page table entries, wherein the level-one page table entries each correspond to at least one level-two page table, and wherein the level-one page table entries each contain a predefined attribute, the predefined attribute being operable to indicate to the memory management unit whether entries in a corresponding level-two page table may designate certain predefined memory regions; tamper detection and response logic; an interface to external systems or components; one or more buses for connecting the internal memory unit, the processor, the tamper detection and response logic, and the interface to external systems and components; and a tamper-resistant housing.