Patent ID: 6018171
Filing Date: 2000-01-25
Classification: G11C,H01L,Y10S

Abstract:
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate, comprising:forming a silicon device area for the FEM gate unit;implanting doping impurities of a first type in the silicon device area to form a conductive channel of a first type for use as a gate junction region;implanting doping impurities of a second type over the device area to form a conductive layer of a second type;depositing an FEM gate unit over the conductive channel of the second type, including depositing a lower metal layer, a FE layer and an upper metal layer, wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance ""D"" from the edges of a source junction region and a drain junction region, where ""D"" is between about 50 nm and 300 nm;depositing an insulating structure over the FEM gate unit; andimplanting doping impurities of a third type in the silicon device area on either side of the gate junction region to form a conductive channel of a third type for use as a source junction region and a drain junction region, wherein the conductive channel of the second type extends into the drain junction region.