Patent ID: 8058674
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A reduced gate to first channel terminal capacitance JFET device, comprising: a) a substrate having a first conduction type; b) an upper layer disposed over the substrate and having a second, opposite, conduction type; c) a region formed in the upper layer and separating the upper layer into two sections including section one and section two, the region having the first conduction type; d) a gate disposed in section one of the upper layer and separated from the substrate by the upper layer, the gate having the first conduction type; e) a first channel terminal disposed in section one of the upper layer and having the second conduction type; and f) a gate pad disposed over section two of the upper layer and electrically coupled to the gate, and electrically isolated from the first channel terminal and the upper layer.