Patent ID: 6275081
Filing Date: 2001-08-14
Classification: G01R

Abstract:
A scan flop circuit, comprising:a sub-scan flop circuit, the subscan flop circuit includes a multiplexer and a flip flop circuit;a data terminal D being connected to the sub-scan flop circuit;a first logic gate being configured to receive a scan input terminal SI and a clock gate terminal G, the first logic gate having a first logic gate output that is connected to the sub-scan flop circuit;a scan enable terminal SE being connected to the sub-scan flip circuit;a latch circuit being configured to receive the clock gate terminal G;a second logic gate being configured to receive the scan enable terminal SE and an output of the latch circuit, the output of the latched circuit being a latched version of the clock gate terminal G, the second logic gate having a second logic gate output;a third logic gate being configured to receive a clock terminal CLK and the second logic gate output, the third logic gate having a third logic gate output being connected to the sub-scan flop circuit; andan output Q and a complementary output /Q.