Patent ID: 6320227
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a semiconductor layer including a cell region and a peripheral region;a first insulating layer formed over a lower surface of the semiconductor layer and having first and second contact holes exposing the semiconductor layer in the cell region and the semiconductor layer in the peripheral region, respectively;first isolation layers formed in the semiconductor layer of the cell region;second isolation layers formed in the semiconductor layer of the peripheral region to define a device formation region in the peripheral region;a pair of trench layers formed to define a device formation region in the semiconductor layer of the cell region and formed in the semiconductor layer between the first isolation layers to be spaced from the lower surface of the semiconductor layer;a cell transistor formed in the device formation region between the trench layers in the cell region, the cell transistor including a first gate having a first gate oxide formed over an upper surface of the semiconductor layer in the device formation region of the cell region, first source and drain regions formed in the device formation region of the cell region at the both sides of the first gate and a channel region defined in the device formation region between the first source and drain regions;a driving transistor formed in the device formation region of the peripheral region, the driving transistor including a second gate having a second gate oxide formed over an upper surface of the semiconductor layer in the device formation region of the peripheral region, second source and drain regions formed in the device formation region of the peripheral region at the both sides of the second gate, and a channel region defined in the device formation region between the second source and drain regions;impurity regions for well pick-up formed in the upper surface of the semiconductor layer adjacent to the cell transistor;a capacitor formed over the first insulating layer in the cell region, the capacitor including a storage node formed over the first insulating layer to be contacted with the first source region of the cell transistor through the first contact hole and a dielectric film and a plate node formed over the storage node;a dummy pattern formed over the first insulating layer in the peripheral region, the dummy pattern including a first doped polysilicon layer, a second insulating layer and a second doped polysilicon layer, the first doped polysilicon being contacted with the channel region of the driving transistor through the second contact hole;a third contact hole formed in the semiconductor layer and the first insulating layer in the peripheral region;a conduction layer formed within the third contact hole to be contacted with the first doped polysilicon layer;a third insulating layer formed over the plate node of the capacitor in the cell region and over the second doped polysilicon layer of the dummy pattern in the peripheral region; anda base substrate bonded on the third insulating layer.