Patent ID: 6099581
Filing Date: 2000-08-08
Classification: G06F

Abstract:
A method of a computer aided design system of performing a layout process of an integrated circuit using predetermined logic design and predetermined connection data, said connection data being changeable by an operator, said method comprising the steps of:(a) providing a database comprising a data structure the data structure including:a net data table comprising connection data,a pattern data table,a parasitic element data table comprising parasitic element data,a delay time data table comprising signal delay times,first association data associating the net data table with the pattern data table,second association data associating the pattern data table with the parasitic element data table, andthird association data associating the parasitic element data table with the delay time data table;(b) generating layout data using the connection data;(c) storing the layout data in the pattern data table;(d) extracting parasitic elements from the layout data to generate the parasitic element data;(e) storing the parasitic element data in the parasitic element data table;(f) computing signal delay times of the parasitic elements to generate delay time data;(g) storing the computed delay time data in the delay time data table;(h) generating new layout data using new connection data when said connection data is changed by said operator;(i) replacing the layout data stored in the pattern data table with said new layout data;(j) extracting parasitic elements from the new layout data to generate new parasitic element data;(k) replacing the parasitic element data stored in the parasitic element data table with said new parasitic element data;(l) computing signal delay times of the new parasitic elements to generate new delay time data;(m) replacing the delay time data stored in the delay time data table with said new delay time data;(n) repeating steps (h) through (m) each time the connection data is changed by said operator;(o) comparing the signal delay times to respective predetermined boundary values of the connection data;(p) interactively correcting the layout data if any critical nets are outside of their respective bounds;(q) updating the layout data stored in the pattern data table with the updated layout data; and(r) repeating steps (h) through (q) until no signal delay times are outside of their respective predetermined boundary values.