Patent ID: 8050136
Filing Date: 2011-11-01
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device, comprising: a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller; a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein the second data clock as received by the data clock input unit is intended to be an inverse of the first data clock, a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit; and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.