Patent ID: 6067260
Filing Date: 2000-05-23
Classification: G11C

Abstract:
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with an external clock signal, comprising:a memory cell array having a plurality of memory cells arranged in a matrix, said memory cell array including:a plurality of regular memory cell blocks; anda plurality of redundant memory cell blocks provided corresponding to every first plurality of said regular memory cell blocks, each for replacing a defective memory cell in the corresponding first plurality of regular memory cell blocks;an address bus provided common to said plurality of regular memory cell blocks and said redundant memory cell blocks to transmit said address signal;a plurality of first column select circuits provided corresponding to said regular memory cell blocks to select a memory cell column in a corresponding regular memory cell block according to said address signal from said address bus;a plurality of second column select circuits provided corresponding to said redundant memory cell blocks to select a memory cell column in a corresponding redundant memory cell block according to said address signal from said address bus,both of said first and second column select circuits being rendered active according to selection of said corresponding regular memory cell block and said corresponding redundant memory cell block on a basis of said address signal;a plurality of first input/output line pairs provided corresponding to said regular memory cell blocks to transmit data read out from a selected memory cell in a selected regular memory cell block;a plurality of second input/output line pairs provided corresponding to said redundant memory cell blocks to transmit data read out from a selected memory cell in a selected redundant memory cell block;a global data bus provided common to said plurality of regular memory cell blocks and said redundant memory cell blocks to transmit data to be output;a plurality of data transmitting circuits each selectively transmitting to said global data bus one of data from said corresponding regular memory cell block and said corresponding redundant memory cell block; anda plurality of judging circuits each controlling data selection of one of said data transmitting circuits according to which of said corresponding regular memory cell block and said corresponding redundant memory cell block is selected on a basis of preset defective address information.