Patent ID: 6903013
Filing Date: 2005-06-07
Classification: H01L

Abstract:
1. A method to deposit a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in the fabrication of interconnects and inductors, comprising the following steps: (a) providing a first insulating layer, overlying a semiconductor substrate with a passivating, etch stop layer thereon; (b) providing a second insulating layer overlying said first insulating layer; (c) forming trench and channel or tunnel openings in the insulating layers; (d) depositing a first copper barrier layer overlying said insulating layers, by atomic layer deposition; (e) depositing a copper seed layer overlying said first copper barrier layer, by atomic layer deposition using precursors of copper compound A, copper(II)-hexafluoroacetyacetonate or copper(thd) (f) performing electroless copper plating copper on said copper seed layer filling trench and channel or tunnel openings with an excess of copper; (g) removing said excess of copper and planarizing back the excess copper by chemical mechanical polishing; (h) depositing a second copper barrier layer overlying the copper, thus completing the fabrication of inlaid copper interconnects and inductors.