Patent ID: 8652899
Filing Date: 2014-02-18
Classification: G02F,H01L

Abstract:
1. A method of fabricating a pixel structure, comprising: providing a substrate; forming a gate and a patterned electrode on the substrate; forming a first insulating layer on the gate, the patterned electrode and the substrate, and forming a common electrode on the first insulating layer; forming a second insulating layer on the first insulating layer and the common electrode, and forming a semiconductor channel layer on the second insulating layer; forming a second through hole in the second insulating layer, and forming a first through hole in the first insulating layer via the second through hole to expose a part of the patterned electrode; forming a source and a drain on the semiconductor channel layer and the second insulating layer, and the drain comprising a first portion and a second portion, the first portion of the drain being connected to the second portion of the drain, the first portion of the drain being electrically connected to the patterned electrode via the first through hole and the second through hole, the second portion of the drain extending onto the common electrode, wherein the patterned electrode and the common electrode partially overlap and are coupled with each other to form a first storage capacitor, and the second portion of the drain and the common electrode partially overlap and are coupled with each other to form a second storage capacitor; forming a passivation layer on the second insulating layer, the semiconductor channel layer, the source, and the drain; forming a third through hole in the passivation layer to expose a part of the drain; and forming a pixel electrode, and the pixel electrode being electrically connected to the drain via the third through hole.