Patent ID: 7797140
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. A method performed by computer, for reducing the computational complexity and overcoming numerical instability, resulting in faster computation times and less storage space for RLC (Resistor-Inductor-Capacitor) interconnect model-order reduction by performing adjoint networks operations, comprising: i) establishing an MNA (modified nodal analysis) expression of an original system of a RLC circuit; ii) creating a matrix A and a vector R from the MNA expression as a base vector for subspace expansion, wherein the matrix A is obtained through A =−(s iii) executing a block Lanczos algorithm between an expansion vector and a system dynamic differences of Krylov subspace to yield first biorthogonal base V iv) establishing an adjoint MNA expression: wherein system moments are represented as X v) creating an equivalent transformation matrix U using the first biorthogonal base V vi) obtaining a reduced order MNA matrix utilizing the equivalent transformation matrix U by a model-order reduction with a one sided projection; vii) obtaining a frequency response waveshape from the reduced order MNA matrix; and viii) outputting the frequency response waveshape by the computer, wherein