Patent ID: 6391714
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for fabricating a capacitor of a semiconductor memory device having a dielectric layer between a lower electrode and an upper electrode, said method comprising:after formation of a transistor on a semiconductor substrate, forming a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode; after formation of an opening for exposing a part of an impurity diffusion region of said transistor by etching a part of said first and second interlayer insulation layers, forming a spacer having at least an upper surface within said opening; after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate on which said spacer is formed, performing a planarization process until a part of the upper surface of the spacer is exposed; and after removal of the exposed spacer, forming the dielectric layer and a conductive layer for the upper electrode of the capacitor, in sequence.