Patent ID: 8589707
Filing Date: 2013-11-19
Classification: G06F,Y02D

Abstract:
1. A system comprising a device for optimizing consumption of electrical power in the system, the system comprising: a processor block; a processing load level monitor coupled to said processor block through a kernel and a multimedia driver; and an operating frequency and/or voltage adjustor coupled to the output of said load level monitor and to the processor block; wherein the frequency and/or voltage adjustor comprises a clock manager; wherein the clock manager comprises a transition manager for determining the required frequency and/or voltage changes, a policy manager for ensuring smooth transition during frequency and/or voltage changes, and a resource manager for scaling the voltage and/or frequency; wherein the resource manager changes the voltage and/or frequency by changing the voltage, followed by changing the frequency in the case that changes in the frequency are to be implemented; and wherein changing the frequency comprises changing the system to a slow mode, changing a Phase Locked Loop (PLL) frequency register, and changing the system to a normal mode.