Patent ID: 6842883
Filing Date: 2005-01-11
Classification: G01R,G06F

Abstract:
1. A process of testing an IC design described in HDL code in conjunction with a hardware simulator and a co-verification tool on a workstation, wherein the co-verification tool provides both firmware control of the IC design via a modeled processor bus, and test stimuli of the IC design via a modeled system interface that is either an industry standard or a proprietary interface, the process comprising steps of: a) operating the co-verification tool in the workstation to execute IC firmware associated with the IC design; b) operating the IC design through the modeled processor bus using the executed IC firmware; and c) operating the co-verification tool in the workstation to supply test stimuli through the modeled system interface to the IC design, the test stimuli being compatible to the industry standard or proprietary interface and the IC design being responsive to the test stimuli to provide responses to the workstation so that the workstation is used to analyze the responses of the IC design.