Patent ID: 8943239
Filing Date: 2015-01-27
Classification: G06F

Abstract:
1. An apparatus comprising: a register file comprising a first register to store a signature and a second register to store a memory address; a first-in-first-out (FIFO) buffer having an output; control logic to load characters into the FIFO buffer where the first character loaded into the FIFO buffer has a first address equal to the memory address stored in the second register; a tapped delay line coupled to the output of the FIFO buffer, the tapped delay line comprising one or more delay elements having respective one or more delayed outputs; a multiplexer coupled to the control logic to multiplex the output of the FIFO buffer and said one or more delayed outputs from the tapped delay line; a plurality of compression engines coupled to the multiplexer, the control logic to load a first character string from the FIFO buffer into the compression engines, the compression engines to generate a first signature corresponding to the first character string; a comparator to compare the first signature with the signature stored in the first register; wherein the control logic loads a second character string from the FIFO buffer into the compression engines provided the comparator indicates that the first signature does not match the signature stored in the first register.