Patent ID: 8093681
Filing Date: 2012-01-10
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, a first transfer MISFET and a second transfer MISFET, the first n-channel MISFET and the second n-channel MISFET each having a gate electrode formed over a semiconductor substrate, and a source region and a drain region formed in the semiconductor substrate such that a first silicide layer and a second silicide layer are formed over the drain region of the first n-channel MISFET and the drain region of the second n-channel MISFET, respectively, the first p-channel MISFET and the second p-channel MISFET each having a gate electrode formed over the semiconductor substrate, and a source region and a drain region formed in the semiconductor substrate such that a first selective growth layer and a second selective growth layer are formed over the source region of the first p-channel MISFET and the source region of the second p-channel MISFET, respectively, and such that a third silicide layer and a fourth silicide layer are formed over the first selective growth layer and the second selective growth layer, respectively; a first insulating film formed over the MISFETs; a first conductive film and a second conductive film formed on the first insulating film and comprised of a different conductive layer from the gate electrodes of the MISFETs, the first conductive film electrically connected to the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET, the gate electrode of the second n-channel MISFET, the gate electrode of the second p-channel MISFET, and one of the source region and the drain region of the first transfer MISFET, the second conductive film electrically connected to the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET, the gate electrode of the first n-channel MISFET, the gate electrode of the first p-channel MISFET, and one of the source region and the drain region of the second transfer MISFET; a second insulating film formed over the first conductive film and the second conductive film; a power source line formed over the second insulating film and electrically connected to the source region of the first p-channel MISFET and the source region of the second p-channel MISFET; and a reference voltage line formed over the second insulating film, formed with the same level layer as the power source line and electrically connected to the source region of the first n-channel MISFET and the source region of the second n-channel MISFET.