Patent ID: 6169421
Filing Date: 2001-01-02
Classification: H03K

Abstract:
A CMOS (complementary metal oxide semiconductor) buffer for connection to a first voltage source and a second voltage source and including an input connection and an output node, comprising: a CMOS inverter with an input connected to the input connection and an output; a first CMOS branch circuit connected to the output for delaying a signal by a first amount of time or a second amount of time; a second CMOS branch circuit connected to the output for delaying the signal by the second amount of time when the first CMOS branch circuit delays the signal by the first amount of time and for delaying the signal by the first amount time when the first CMOS branch circuit delays the signal for the second amount of time; and a CMOS output device including a first MOS transistor connected to the first CMOS branch circuit and to the output node and a second MOS transistor connected to the second CMOS branch circuit and to the output node.