Patent ID: 6516377
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A self-configuring modular electronic system comprising:a data and address bus having a plurality of lines, one or more selected lines of the data and address bus having an identification signal applied thereto at a predetermined time; a plurality of bus terminals, each identification signal being routed from a previous bus terminal to a subsequent bus terminal; a plurality of addressable modules connected to an common reset line, each module having a series of module lines, one respective module line of each module being electrically connected to an assigned one of the bus lines at the bus terminal, each module determining the respective bus terminal from the identification signal, said bus having n select bus lines provided for identification purposes and more than 2n modules connected thereto to be identified; and an arithmetic device arranged between each of two successive bus terminals for performing an arithmetical operation with the identification signal, said identification signal being successively fed to the first 2n modules at a first reset signal level and changed by the arithmetic devices assigned to the first 2n modules, subsequent arithmetic devices initially routing the identification signal unchanged, the first 2nâˆ’1 modules storing the values received with the identification signal and a first additional value that is common to the first 2nâˆ’1 modules when the reset signal level changes and all modules that follow the 2nâˆ’1 module subsequently storing a second additional value that differs from the first value, said identification signal being then also successively fed to subsequent modules that follow the 2n module and changed by the arithmetic devices assigned to the subsequent modules that follow the 2n module, the values fed to the subsequent modules with the identification signal being stored.