Patent ID: 6413815
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconcuctor wafer simultaneously, the semiconductor wafer comprising a first dielectric layer, at least a first conductive layer and at least a bottom electrode of the MIM capacitor disposed in the first dielectric layer, the surface of the first conductive layer and the bottom electrode of the MIM capacitor covered by a barrier layer, the method comprising:forming a second dielectric layer on the surface of the barrier layer; forming a stop layer on the surface of the second dielectric layer; forming a third dielectric layer on the surface of the stop layer, wherein the second dielectric layer, the stop layer and the third dielectric layer forms a sandwiched structure; forming a first photoresist layer on the surface of the third dielectric layer, the first photoresist layer exposes the regions for forming the runner and the top electrode of the MIM capacitor in the third dielectric layer; etching the third dielectric layer not covered by the first photoresist layer down to the stop layer anisotropicaly so as to form a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor respectively; removing the first photoresist layer completely; forming a second photoresist layer on the surface of the semiconductor wafer, the second photoresist layer covers the region outside the opening; etching the stop layer and the second dielectric layer at the bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode of the MIM capacitor in the third dielectric layer, the stop layer and the second dielectric layer; removing the second photoresist layer completely; forming a third photoresist layer on the surface of the semiconductor wafer, the third photoresist layer forms a contact opening in the trench; etching the stop layer, the second dielectric layer and the barrier layer via the contact opening down to the surface of the first conductive layer so as to form a contact hole in the stop layer, the second dielectric layer and the barrier layer; and removing the third photoresist layer.