Patent ID: 6725442
Filing Date: 2004-04-20
Classification: G01R

Abstract:
A method of defining an interconnect-challenging sequence of unique sequencer states for testing the operability of a plurality of under-test, programmable interconnect resources (IRUT's) where said IRUT's are used to feedback a previously stored, sequencer state to inputs of a programmable sequencer for thereby producing, if the under-test IRUT's are in operative rather than defective condition, a next expected state of the programmable sequencer, said method comprising:(a) organizing the expected sequence of unique sequencer states so as to avoid toggling a first challenging signal applied to a corresponding first of the under-test IRUT's only at a relatively low toggling frequency and to simultaneously avoid toggling a second challenging signal applied to a corresponding second of the under-test IRUT's only a substantially higher toggling frequency.