Patent ID: 9054215
Filing Date: 2015-06-09
Classification: B82Y,H01L

Abstract:
1. A method of forming a nanowire transistor on a substrate, the method comprising: lithographically patterning a guide opening of a first diameter in a mask layer disposed over a source/drain semiconductor layer of the transistor; depositing a directed self-assembly (DSA) material into the guide opening; segregating the DSA material into an interior polymer region completely surrounded by an exterior polymer region within the guide opening by baking and/or curing; defining a semiconductor channel region of the transistor within the guide opening by removing one of the interior and exterior polymer regions selectively to the other, wherein the channel region diameter and spacing from an edge of the guide opening are both defined by the DSA segregation; removing the other of the interior and exterior polymer regions; depositing a gate dielectric over the semiconductor channel region; and surrounding the semiconductor channel region with an annular gate electrode having an outer diameter self-aligned to the guide opening.