Patent ID: 6121087
Filing Date: 2000-09-19
Classification: H01L

Abstract:
A process for fabricating memory cells, low voltage CMOS transistors, and high voltage CMOS transistors on a substrate, wherein each memory cell includes a control gate, a word gate and a floating gate, comprising the steps of:(a) forming a first oxide layer on the substrate surface;(b) depositing a first polysilicon layer on the first oxide layer;(c) etching the first polysilicon layer to define word gates, floating gates, and low voltage CMOS transistor gates;(d) forming a second oxide layer over the substrate surface, wherein the second oxide layer is thicker than the first oxide layer;(e) depositing a second polysilicon layer on the second oxide layer; and(f) etching the second polysilicon layer to define high voltage CMOS transistor gates and control gates, wherein each control gate is above and overlaps one of the floating gates.