Patent ID: 8941224
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A package structure of a chip and a substrate, comprising: a thin chip substrate having a first circuit metal layer, a second circuit metal layer, bonding pads and a dielectric layer, wherein the first circuit metal layer is inlaid into the dielectric layer to cooperatively define a co-plane exposed from the dielectric layer, the dielectric layer having a plurality of holes with respect to the first circuit metal layer, the second circuit metal layer being formed on the dielectric layer to fill up the holes to be connected electrically to the first circuit metal layer, the bonding pads connected to the first circuit metal layer being formed on the co-plane; a stabilizing material layer provided on two sides of the co-plane to define a receiving space, wherein the stabilizing material layer includes a stabilizing layer formed on an adhesive layer with the adhesive layer disposed between the stabilizing layer and the co-plane; a chip having pins, each soldered with a respective one of the bonding pads; and a filling material injected into the receiving space under the chip to fasten the pins of the chip and the bonding pads, wherein the package structure has a total thickness ranging from 300 to 850 μm; wherein the stabilizing layer has a top higher than the chip.