Patent ID: 8633540
Filing Date: 2014-01-21
Classification: H01L

Abstract:
1. A transistor having a gate located over a channel region recessed into a semiconductor substrate, comprising: a source/drain including a heavily doped region adjacent said channel region; another source/drain having a lightly doped region adjacent an opposing side of said channel region; an oppositely doped well under said channel region said heavily doped region of said source/drain and said lightly doped region of said another source/drain; and a channel extension, within said oppositely doped well, under at least a portion of said channel region and extending under at least a portion of said heavily doped region of said source/drain and said lightly doped region of said another source/drain, wherein said channel extension extends under said portion of said lightly doped region of said another source/drain by a channel extension length.