Patent ID: 7737932
Filing Date: 2010-06-15
Classification: G09G

Abstract:
1. A drive circuit for driving a display device in which a plurality of scanning lines and a plurality of data lines are arranged in matrix fashion, said drive circuit comprising: a first data latch circuit that holds image data corresponding to one line from given image data; a second data latch circuit that holds image data held in the first data latch circuit; a decoding circuit that decodes the image data held in the second data latch circuit; a gradation amplifier circuit comprising a plurality of gradation amplifiers that amplify or buffer, and output, a respective plurality of gradation voltages; a gradation voltage selection circuit that selects gradation voltages that are necessary for display from the plurality of gradation voltages that are output from the gradation amplifier circuit, and outputs these selected gradation voltages to an output circuit; a decision circuit that decides on a use/non-use of gradations based on receiving and selectively using image data that are output from the first data latch circuit to said second data latch circuit, the image data that are output from the second data latch circuit, or the image data that are output from the decoding circuit; and an enabling/disabling circuit that selectively disables operation of the gradation amplifiers corresponding to gradations that are decided as not to be used, using decision results output from the decision circuit, wherein the decision circuit comprises: wherein the decision result data is obtained in the shift register by repeating, while varying the counter value in a prescribed range, the operations in which corresponding gradation data in respective plurality of comparator circuits is compared with a count value delivered from the reference counter, this comparison result is input to a corresponding OR circuit, the OR circuit takes an OR of the comparison result and the output from OR circuits of the comparator circuits connected in cascade, and outputs an OR obtained over the plurality of comparator circuits to the shift register.