Patent ID: 7236025
Filing Date: 2007-06-26
Classification: H03L

Abstract:
1. A PLL circuit comprising: a phase/frequency detection circuit for detecting a phase difference and frequency difference between a reference clock that is received as input from an outside and a clock that is generated by the PLL circuit, and for generating and supplying as output a phase/frequency amplification signal and a phase/frequency attenuation signal having pulse widths that accord with the phase difference and frequency difference as well as complementary signals of these signals; a charge pump bias circuit for receiving a reference bias voltage as input and generating and supplying as output a first charging current bias voltage and a first discharging current bias voltage; a charge pump circuit for supplying charging current in accordance with said first charging current bias voltage, supplying discharging current in accordance with the first discharging current bias voltage, and generating and supplying as output a PLL control voltage; a voltage-controlled oscillation circuit for receiving said PLL control voltage and generating a clock; and a frequency-dividing circuit for dividing the clock that is supplied as output by said voltage-controlled oscillation circuit to generate a feedback clock and supplying the feedback clock as output to said phase/frequency detection circuit; wherein: said PLL circuit is further provided with a correction voltage generation circuit for generating and supplying as output a correction voltage for correcting said PLL control voltage; said charge pump bias circuit receives the correction voltage that is supplied as output by said correction voltage generation circuit to regulate the discharging current and generate and supply as output a second discharging current bias voltage; said PLL circuit is further provided with: a first capacitor that is provided between said charge pump circuit and said voltage-controlled oscillation circuit; and a replica charge pump circuit provided with a second capacitor in which charging/discharging is carried out in accordance with output; said replica charge pump circuit supplying charging current to said second capacitor during the time interval in which both said first charging current bias voltage is received as input and the complementary signal of said phase/frequency amplification signal is low level, and during the time interval in which both said second discharging current bias voltage is received as input and said phase/frequency amplification signal is high level, supplying discharging current to said second capacitor, and generating a reference voltage in which these currents are combined, and supplying this reference voltage as output to said correction voltage generation circuit; said charge pump circuit: supplies charging current to said first capacitor during the time interval in which both said first charging current bias voltage is received as input and the complementary signal of said phase/frequency amplification signal is low level; and during the time interval in which both said second discharging current bias voltage is received as input and said phase/frequency attenuation signal is high level, supplies discharging current to said first capacitor, generates a PLL control voltage in which these currents are combined, and supplies this PLL control voltage as output to said voltage-controlled oscillation circuit and said correction voltage generation circuit; and said correction voltage generation circuit: compares said PLL control voltage and said reference voltage, generates a differential voltage as correction voltage, and supplies the correction voltage as output to said charge pump bias circuit.