Patent ID: 6708261
Filing Date: 2004-03-16
Classification: H03K

Abstract:
An integrated circuit device, comprising:an internal clock generator that is configured to generate an internal clock signal in-sync with an external clock signal received by the integrated circuit device; a multi-stage data buffer that is configured to receive the external and internal clock signals and non-clock data generated external to the integrated circuit device, said multi-stage data buffer comprising first and second storage devices that are electrically connected together in series and configured so that the data is loaded into the first storage device in-sync with the external clock signal, which is received by the first storage device, and then passed and loaded into the second storage device in-sync with the internal clock signal, which is received by the second storage device; and a level-shifting inverter that is configured to pass the data generated external to the integrated circuit device to an input of the first storage device, and is responsive to a control signal that enables a pull-up path of the level-shifting inverter when active.