Patent ID: 7595649
Filing Date: 2009-09-29
Classification: G01R

Abstract:
1. A method of estimating the source or drain series resistance of a MOS transistor comprising the steps of: providing an MOS transistor, comprising: applying a voltage to said gate node relative to said substrate node to bias the MOS transistor into accumulation; applying a current to said source node; measuring a potential difference between said source node and said drain node; incrementing said current applied to said source node; repeating the last two steps for a plurality of iterations to obtain a plurality of current and potential difference values; estimating a slope of said current and potential difference values, using a subset of said current values and said potential difference values, wherein said current values are used as independent variable values and said potential difference values are used as dependent variable values, and wherein current values and potential difference values in said subset are substantially linear; and assigning said slope to a value of resistance for said source node.