Patent ID: 8570807
Filing Date: 2013-10-29
Classification: G11C

Abstract:
1. A method of operating a NAND architecture non-volatile memory device, comprising: placing a precharge voltage on one or more first bit lines and one or more second bit lines; coupling the one or more first bit lines to one or more selected NAND strings, wherein one or more control gates of one or more unselected memory cells of each selected NAND string are driven by a read pass voltage, and where a control gate of a selected memory cell is driven by a read voltage; coupling the one or more second bit lines to one or more reference NAND strings, wherein one or more control gates of one or more unselected memory cells of each reference NAND string are driven by a read pass voltage, and where a control gate of a reference memory cell is driven by a read voltage; and sensing the difference between a voltage level of each of the one or more first bit lines and a voltage level of each of the one or more second bit lines to determine a threshold voltage level of the selected non-volatile memory cells of each selected NAND string; wherein the NAND architecture non-volatile memory device is a single level cell (SLC) memory device and where the one or more unselected memory cells of each of the one or more reference NAND strings are programmed and the reference memory cell of each of the one or more reference NAND strings is erased.