Patent ID: 8250308
Filing Date: 2012-08-21
Classification: G06F

Abstract:
1. A method for a cache coherency protocol with built in avoidance for conflicting responses in a multi-node system, the method comprising: initiating a processor request to a shared level of cache in a requesting node of the plurality of nodes; broadcasting the processor request to a plurality of remote nodes when the processor request encounters a local cache miss at the requesting node; performing a directory search of a cache of each of the plurality of remote nodes to determine a state of a target line's address in each of the plurality of remote nodes and an associated ownership state of said target line's address; receiving, at the requesting node, partial responses from each of the plurality of remote nodes, the partial responses including the ownership state of the target line from each of the plurality of remote nodes; performing, in the requesting node, a consistency check on the partial responses, the consistency check determining if there are any inconsistencies in the partial responses; broadcasting the combined response from the requesting node to each of the plurality of remote nodes; protecting the target line address by setting a pending bit at each of the plurality of remote nodes responsive to determining that at least one of the received partial response is a hit response; sourcing data from a respective remote cache during a fetch operation, and forwarding the data to the requesting node while protecting the data, responsive to determining that the directory search indicates an Intervention Master (IM) or a Target Memory Node on a remote node; sourcing the data from the requesting node during a store operation, and protecting the data while forwarding the data to the Intervention Master (IM) or the Target Memory node after coherency has been established in the multi-node system; and receiving a final response from each of the plurality of remote nodes and returning a completion response to the requesting processor, responsive to determining the completion of the cache coherent operations.