Patent ID: 6743693
Filing Date: 2004-06-01
Classification: H01L

Abstract:
A method of manufacturing a semiconductor memory comprising a memory cell array forming region and a peripheral circuit forming region adjacent to said memory cell array forming region, said method comprising the steps of:(a) forming an insulation layer in said memory cell array forming region and said peripheral circuit forming region; (b) forming a plurality of openings in said insulation layer in said memory cell array forming region and forming a trench in said insulation layer at a border between said memory cell array forming region and said peripheral circuit forming region; (c) forming a lower electrode of a capacitor on a surface of each of said plurality of openings; (d) after said step (c), filling said trench with a resist and forming said resist on said insulation layer in said peripheral circuit forming region; and (e) selectively etching said insulation layer using said resist as a mask, wherein said step (b) includes the steps of: (b-1) preparing a photomask provided with a mask pattern including a plurality of first patterns corresponding to said plurality of openings, arranged at a predetermined pitch, a first dummy pattern aligned linearly with said plurality of first patterns at said predetermined pitch from the most adjacent one of said plurality of first patterns, and a second pattern corresponding to said trench; (b-2) forming a photoresist on said insulation layer; (b-3) exposing said photoresist using said photomask to transfer said mask pattern to said photoresist; (b-4) developing said photoresist, after said step (b-3); and (b-5) etching said insulation layer using said photoresist as a mask to form said plurality of openings and said trench, after said step (b-4), and said first dummy pattern is not transferred to said photoresist in said step (b-3).