Patent ID: 6162670
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method for fabricating a data-storage capacitor for a DRAM device constructed on a semiconductor substrate which is already formed with a FET having a gate and a pair of source/drain regions, comprising the steps of:forming a first insulating layer over the substrate;forming a second insulating layer over the first insulating layer;removing a selected part of the second insulating layer that is laid directly above a selected one of the source/drain regions of the FET to form a first opening in the second insulating layer;forming a third insulating layer over the second insulating layer;performing a selective etching process on the third insulating layer to form a second opening in the third insulating layer, with the etching process also acting on the part of the first insulating layer that is uncovered by the second insulating layer to thereby form a contact hole in the first insulating layer which exposes the selected one of the source/drain regions of the FET, wherein the second opening is directly above the contact hole;forming a conductive layer over the third insulating layer, the conductive layer filling the contact hole in the first insulating layer but not filling the second opening in the third insulating layer;forming a fourth insulating layer over the conductive layer, the fourth insulating layer filling the second opening in the third insulating layer;removing part of the fourth insulating layer and the conductive layer until the surface of the third insulating layer is exposed;removing a surface part of the fourth insulating layer and the third insulating layer until reaching a predefined depth into the fourth insulating layer and the third insulting layer to allow an upper part of the conductive layer to be exposed above a substantially planar upper insulating surface;forming conductive sidewall spacers on the exposed part of the conductive layer;removing the third insulating layer and the fourth insulating layer entirely; the combined structure of the conductive layer and the conductive sidewall spacers serving as a bottom electrode;forming a dielectric layer over the bottom electrode; andforming a top electrode over the dielectric layer, wherein the top electrode, the dielectric layer, and the bottom electrode in combination constitute the intended data storage capacitor for the DRAM device.