Patent ID: 6300195
Filing Date: 2001-10-09
Classification: H01L

Abstract:
A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least one matrix of floating gate memory cells, the matrix being formed on a semiconductor substrate with a plurality of continuous bit lines extending in parallel across the substrate, the process comprising:forming an oxide layer on the semiconductor substrate;forming a stack structure over the semiconductor substrate, the stack structure including a first conductor layer, a first dielectric layer, and a second conductor layer;depositing a second dielectric layer over the stack structure;using a polysilicon mask of a first direction to define and etch the stack structure into a plurality of parallel stack strips which delimit a first dimension of floating gate regions of the floating gate memory cells, and into a plurality of parallel openings located between the parallel stack strips, respectively;implanting a dopant into the semiconductor substrate underlying at least one of the plurality of parallel openings to form at least one of the plurality of continuous bit lines; andfilling the at least one of the plurality of parallel openings with an energy-reactive material to protect the at least one of the plurality of continuous bit lines.