Patent ID: 6295622
Filing Date: 2001-09-25
Classification: G01R

Abstract:
A number transformer, comprising:a clocked pseudorandom pattern generator that produces a first n-bit binary number,at least one clocked updatable device that produces a second n-bit binary number wherein the ratio of ones to zeros within each said second n-bit binary number equals a preselected ratio;n multiplexers,each mutiplexer receives exactly one bit from each said clocked updatable device, wherein each said exactly one bit received by each said multiplexer occupies the same bit position within said second n-bit binary number produced by each clocked updatable device,a select signal coupled to each said multiplexer, said select signal selects one specific second n-bit binary number produced by one specific clocked updatable device and causes each said multiplexer to output the bit value of said second n-bit binary number, andn AND gates, each said AND gate receives exactly one bit from said pseudorandom pattern generator output and the bit that occupies the same bit position from said multiplexer, said n AND gates collectively output a third n-bit binary number having a ratio of ones to zeros that is either equal to or less than the ratio of ones to zeros within said one specific second n-bit binary number selected by said select signal.