Patent ID: 6650160
Filing Date: 2003-11-18
Classification: H03K,H03L

Abstract:
A method of generating a two step variable length delay, said method comprising:passing an input clock signal through a plurality of serially-interconnected delay elements, each said delay element having a delay time interval dtc, thereby generating a corresponding plurality of delayed signals; switchably selecting a set of m (where m is an integer greater than 2) of said plurality of delayed signals, said selected m delayed signals being a first to an mth coarse adjustment delay signals, an nth coarse adjustment delay signal leading an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (mâˆ’1) or less); generating 2m fine adjustment delay signals from said first to mth coarse adjustment delay signals, a jth fine adjustment delay signal leading a (j+1)th fine adjustment delay signal in a phase by a time interval dtcâ€², said time interval dtcâ€² being finer than said time interval dtc, said generating achieved by: amplifying said first to mth coarse adjustment delay signals; for each n, mixing waveforms of said nth and said (n+1)th coarse adjustment delay signals; and mixing waveforms of said mth and said first coarse adjustment delay signals; and outputting one of said 2m fine adjustment delay signals to be a selected variable length delay output signal.