Patent ID: 6812145
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A method of reducing plasma-induced charging damage in a dielectric trench etch process for a dual damascene semiconductor structure, said method comprising the following steps, in the order stated:(a) providing a semiconductor structure comprising from bottom to top (1) a semiconductor substrate (2) a conductor embedded in said substrate, having an upper portion of said conductor contacted at its sidewall by a first layer of dielectric material, an upper surface of said conductor and an upper surface of said first dielectric layer being covered by an etch stop layer, (3) a second layer of dielectric material overlying said etch stop layer, (4) a dielectric hardmask layer overlying said second layer of dielectric material, (5) a contact opening extending downward from a top surface of said dielectric hardmask layer, and through said second dielectric layer, said contact opening comprising a sidewall extending downward through said second dielectric layer, and ending at said etch stop layer, which provides a floor of said contact opening; (b) depositing upon an exposed upper surface of said second dielectric layer, and upon said sidewall of said contact opening, and upon said floor of said contact opening, a continuous layer of a protective conductive material; (c) applying a layer of photoresist material; (d) patterning said layer of photoresist material in a manner defining the location for plasma etching of a trench in an upper surface of said dielectric hardmask layer, immediately over and communicating with said contact opening; (e) anisotropically plasma etching said trench downward and through said dielectric hardmask layer, and downward into, but not through, said second dielectric layer, to a nominal trench depth; (f) removing said photoresist layer which remains, if any, following said etching of said trench; (g) anisotropically plasma etching away said protective conductive layer, if any, which remains upon said dielectric hardmask layer or upon said floor of said contact opening, and a portion of said etch stop layer which is exposed through said contact opening, but not said protective layer which remains upon said sidewall of said contact opening; and (h) anisotropically plasma etching away any of said etch stop layer material remaining on the floor of said contact opening after completion of step (g), thereby exposing a surface of said conductor embedded in said semiconductor substrate.