Patent ID: 6285079
Filing Date: 2001-09-04
Classification: H01L,H05K

Abstract:
A semiconductor device comprising:a semiconductor chip in which circuit elements are formed on the major surface thereof, said semiconductor chip being provided with chip electrodes on the major surface thereof;an insulating substrate having a major surface to face a motherboard and a reverse surface to receive said semiconductor chip;signal electrodes arranged in a grid array on the major surface of said insulating substrate, said signal electrodes being electrically connected to said chip electrodes of said semiconductor chip;shielding electrodes arranged on a marginal area of the major surface of said insulating substrate to surround said signal electrodes;a stress alleviation film disposed between a marginal portion of the major surface of said semiconductor chip and a marginal portion of the reverse surface of said insulating substrate;sealing material hermetically sealing a clearance between the major surface of said semiconductor chip and the reverse surface of said insulating substrate; anda package hermetically housing said sealed semiconductor chip, stress alleviation film, and insulating substrate,wherein said signal and shielding electrodes provided on the major surface of said insulating substrate may be connected to electrodes of a motherboard.