Patent ID: 6747318
Filing Date: 2004-06-08
Classification: H01L

Abstract:
An integrated circuit fabricated on a semiconductor substrate and having at least two devices, each of the devices having a different effective gate oxide thickness, the circuit comprising:a first device having a first gate disposed on a first gate dielectric layer, the first gate dielectric layer having a first thickness and a first effective gate oxide thickness and disposed on the semiconductor substrate; and a second device having a second gate disposed on a second gate dielectric layer having the first thickness and the first effective gate oxide thickness, the second gate dielectric layer fabricated on the semiconductor substrate, the second device comprising: a buried channel implanted below the second gate dielectric layer in a second region of the substrate, the buried channel being doped with a predetermined dopant of a first conductivity type and the second region having a second conductivity type, the buried channel having a peak concentration of the predetermined dopant positioned at a selected level in the second region below the gate dielectric layer to cause the substrate portions above the selected level to act as a supplemental gate dielectric layer when the second channel is biased with respect to the substrate and the buried channel is partially depleted of charge carriers, to increase the effective gate oxide thickness of the second device, wherein the level is selected so that the effective gate oxide thickness of the second device is a predetermined value greater than the first effective gate oxide thickness.