Patent ID: 6773989
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising the steps of:a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having an upper portion and a lower portion wherein the upper portion has a greater width than that of the lower portion; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the wider upper portion of the first trench that is disposed over the second layer of insulation material and the first layer of conductive material; e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.