Patent ID: 8654559
Filing Date: 2014-02-18
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a variable resistance element in which electrodes are supported at both ends of a variable resistor, a resistance state specified by a current-voltage characteristic between the electrodes transitions between two or more different resistance states by applying electrical stress between the electrodes at the both ends, and one of the resistance states after the transition is used for storing information; a circuit that applies a reforming voltage pulse to a memory cell including the variable resistance element whose resistance characteristic for at least one of the resistance states has been varied after an application of a write voltage pulse a plurality of times, in order to recover the resistance characteristic to be in an initial state of corresponding one of the resistance states, the reforming voltage pulse being different from any of the write voltage pulses that cause each of the resistance states of the variable resistance element to transition to a different state; a memory cell array having a plurality of memory cells, each including the variable resistance element, arranged in a row direction and a column direction respectively; a memory cell selecting circuit that selects one or a plurality of memory cells to which a memory operation is to be performed from among the memory cells in the memory cell array by controlling a voltage to be applied to each of the memory cells; a write voltage application circuit that generates the write voltage pulse and applies the write voltage pulse via the memory cell selecting circuit to the memory cells to be written selected by the memory cell selecting circuit; a reforming voltage application circuit that generates at least one reforming voltage pulse corresponding to any one of the write voltage pulses, and applies the reforming voltage pulse via the memory cell selecting circuit to the memory cells to be reformed selected by the memory cell selecting circuit; and a reading circuit that detects current flowing through the variable resistance element of each of the memory cells, wherein the write voltage application circuit applies any one of a first write voltage pulse and a second write voltage pulse to the memory cells to be written via the memory cell selecting circuit, the first write voltage pulse causing the resistance state of the variable resistance element to transition from a high resistance state to a low resistance state, and the second write voltage pulse causing the resistance state of the variable resistance element to transition from the low resistance state to the high resistance state; and the reforming voltage application circuit applies at least any one of a first reforming voltage pulse corresponding to the first write voltage pulse and a second reforming voltage pulse corresponding to the second write voltage pulse, to the memory cells to be reformed.