Patent ID: 6207581
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method of fabricating a node contact hole on a semiconductor substrate, said method comprising:forming a first interpoly dielectric (IPD1) layer over a semiconductor structure;forming a landing pad in said first interpoly dielectric layer;forming a polycide bit line on said first interpoly dielectric layer;forming a second interpoly dielectric (IPD2) layer on said polycide bit line, said landing pad, and said first interpoly dielectric layer;forming a defined photoresist layer on said second interpoly dielectric layer, said defined photoresist layer defining a node contact pattern;firstly etching a portion of said second interpoly dielectric layer using said defined photoresist layer as a mask;removing said defined photoresist layer;depositing a insulating layer on said second interpoly dielectric layer;depositing a polysilicon layer on said insulating layer;etching back said polysilicon layer to expose said insulating layer;secondly etching a portion of said second interpoly dielectric layer to expose said land pad, using said polysilicon layer as a hard mask;removing said polysilicon layer on said insulating layer;removing said insulating layer on said second interpoly dielectric layer; andforming said node contact hole in said second interpoly dielectric layer, said node contact hole having a critical dimension.