Patent ID: 6339813
Filing Date: 2002-01-15
Classification: G06F

Abstract:
A computer memory system including a processor device having associated system memory storage, said computer memory system comprising:a cache memory array device having a plurality of cache lines, each said cache line having a plurality of sub-cache line sectors for storing data; a cache directory device, associated with said cache memory array device, comprising entries for storing address tag information associated with the data stored in said cache memory array; a cache line write back system, associated with said cache memory array, for performing a cache line fill operation by requesting and removing existing cache line data and replacing removed data with different data via a cache line write back operation, and updating said directory device with new address tag information; and a cache memory access system for enabling access to said data by said processing device, said cache memory access system including: a plurality of sub-cache line state vectors, each state vector corresponding to an associated sub-cache line sector within a cache line and indicating a state of data at said associated sub-cache line sector; and control means for receiving said address tag information and said plurality of sub-cache line state vectors and determining whether data requested by either one of said processing device and said cache line write back system is stored in said cache memory array and available for use by said one of said processing device and said cache line write back system, wherein said requested data is provided to one of said processing device and said cache line write back system when said cache line is not completely filled or emptied and wherein said cache memory access system enabling data to be simultaneously written to said sub-cache line sectors and data at said sub-cache line sectors to be read by one of said cache line write back system and said processor device or both.