Patent ID: 7781282
Filing Date: 2010-08-24
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a gate pattern having first and second sidewalls on either side of the gate pattern facing each other on a substrate; forming a lightly doped drain region adjacent the first sidewall and disposed on an opposite side of the second sidewall within the substrate; forming an insulating spacer covering the first sidewall; forming a highly doped drain region adjacent to the first sidewall and disposed on an opposite side of the second sidewall within the substrate; forming a corner protection pattern adjacent the highly doped drain region and the insulating spacer and contacting a sidewall of the insulating spacer; forming a gate metal silicide layer on a top surface of the gate pattern; forming a source/drain metal silicide layer on a top surface of the highly doped drain region, where the gate metal silicide layer and source/drain metal silicide layer are formed prior to forming the corner protection pattern; after forming the highly doped drain region, forming an etch stop layer to cover the gate pattern, the insulating spacer, the corner protection pattern, and the highly doped drain region; forming an inter-layer dielectric on the substrate; and forming a contact hole penetrating the inter-layer dielectric, wherein forming the contact hole includes, wherein the etch stop layer remains except on a portion of the formed contact hole, and wherein the highly doped drain region is self-aligned outside of the insulating spacer.