Patent ID: 9122630
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A host controller which is connected to a memory device through an interface, accesses a system memory, and is controlled by a CPU executing a host driver, wherein each of first, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors, the host controller comprising: a register set which is configured to store a part of information in the third descriptor; a command controller which is configured to issue a command to the memory device according to the information stored in the register set; and a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors into the host controller, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors, wherein the first descriptor includes a plurality of pointers with attributes, each of the pointers of the first descriptor indicates a leading region of the third descriptor, the third descriptor includes command issue information and attributes, the fourth descriptor includes a number of DMA execution information and attributes, wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end or during a DMA data transfer, wherein the third descriptors includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks, wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory, and wherein the DMA unit includes: a system address controller configured to control addresses of the system memory pointing data and each descriptor, and a data buffer, wherein the data in the system memory is read to the data buffer in accordance with the fourth descriptor, and the data in the data buffer is transferred to the memory device in accordance with the third descriptor when the data is written into the memory device, and the data in the memory device is read to the data buffer in accordance with the third descriptor, and the data in the data buffer is transferred to the system memory in accordance with the fourth descriptor when the data is read from the memory device.