Patent ID: 6617622
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor chip having a padless central portion; first to fourth memory cell arrays formed in said semiconductor chip; a first peripheral circuit arranged between said first and second memory cell arrays, said first peripheral circuit including a first bus line group; a second peripheral circuit arranged between said third and fourth memory cell arrays, said second peripheral circuit including a second bus line group; a first column decoder disposed between said first memory cell array and said first peripheral circuit; a second column decoder disposed between said second memory cell array and said first peripheral circuit; a third column decoder disposed between said third memory cell array and said second peripheral circuit; a fourth column decoder disposed between said fourth memory cell array and said second peripheral circuit; a first pad group comprising spaced apart pads arranged between said first and third memory cell arrays in a first row having a regular pitch, wherein said row of said first pad group is adjacent to rind extends away from said padless central portion of said semiconductor chip; a second pad group comprising spaced apart pads arranged between said first and third memory cell arrays in a second row having a regular pitch, wherein said row of said second pad group is adjacent to and extends away from said padless central portion of said semiconductor chip, the pads of said second pad group being offset from the pads of said first pad group; a third pad group comprising spaced apart pads arranged between said second and fourth memory cell arrays in third row having a regular pitch, wherein said row of said third pad group is adjacent to and extends away from said padless central portion of said semiconductor chip; a fourth pad group comprising spaced apart pads arranged between said second and fourth memory cell array in a fourth row having a regular pitch, wherein said row of said fourth pad group is adjacent to and extends away from said padless central portion of said semiconductor chip, the pads of said fourth pad group being offset from the pads of said third pad group; a third peripheral circuit arranged between said first pad group and said first memory cell array, said third peripheral circuit including a third bus line group; a fourth peripheral circuit arranged between said third pad group and said second memory cell array, said fourth peripheral circuit including a fourth bus line group; a fifth peripheral circuit arranged between said second pad group and said third memory cell array, said fifth peripheral circuit including a fifth bus line group; a sixth peripheral circuit arranged between said fourth pad group and said fourth memory cell array, said sixth peripheral circuit including a sixth bus line group; a first row decoder disposed between said third peripheral circuit and said first memory cell array; a second row decoder disposed between said fourth peripheral circuit and said second memory cell array; a third row decoder disposed between said fifth peripheral circuit and said third memory cell array; a fourth row decoder disposed between said sixth peripheral circuit and said fourth memory cell array; and a center circuit arranged in said padless central portion of said semiconductor chip, said padless central portion being bounded by said first to fourth pad groups and said first to sixth peripheral circuits.