Patent ID: 7400178
Filing Date: 2008-07-15
Classification: G06F,H03K

Abstract:
1. A data output clock selection circuit comprising: a combinational logic circuit configured to receive a first signal pair, and in response, provide a reset control signal that is deactivated when both signals of the first signal pair have a first predetermined logic state, and provide a reset control signal that is activated when the signals of the first signal pair have complementary logic states; a first sequential logic circuit configured to receive the reset control signal, a control clock signal and a fixed signal, and in response provide a preliminary clock select signal; a second sequential logic circuit configured to receive the reset control signal, the control clock signal and the preliminary clock select signal, and in response, provide a clock select signal; a multiplexer coupled to receive the first signal pair, a second signal pair, and the clock select signal, the multiplexer being configured to route the first or second signal pair to clock a data output circuit in response to the clock select signal.