Patent ID: 8963754
Filing Date: 2015-02-24
Classification: H03M

Abstract:
1. A circuit for digitizing a sum of at least one first input signal and a plurality of second input signals comprising: a passive adder circuit implemented with a first capacitor array and arranged for performing a summation of the plurality of second input signals and for outputting a summation signal; a second capacitor array arranged for sampling the at least one first input signal, wherein at least one of the first capacitor array or the second capacitor array includes a scaling capacitor arranged for scaling down the summation signal or the at least one first input signal, respectively, so that the summation signal and the at least one first input signal are in the same voltage range; a comparator arranged for comparing the summation signal applied at a first comparator input terminal with a signal applied at a second comparator input terminal, the signal at the second comparator input terminal being derived from the at least one first input signal and having an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input terminal is indicative of the sum of the at least one first input signal and the plurality of second input signals, the comparator further arranged for producing a comparator output signal based on the sum of the at least one first input signal and the plurality of second input signals; and a control logic block for determining a multi-bit representation of the sum from the comparator output signal.