Patent ID: 7023926
Filing Date: 2006-04-04
Classification: H04N

Abstract:
1. A stream converting apparatus for converting a first format data stream into a second format data stream, said first format data stream being obtained by packetizing a first level data stream to generate a second level data stream and further multiplexing said second level data stream, the apparatus comprising: a stream extracting circuit extracting said second level data stream from said first format data stream; an error detecting circuit connected to an output of said stream extracting circuit and detecting an error included in said second level data stream output from said stream extracting circuit; a data correcting circuit connected to said error detecting circuit and correcting the error detected by said error detecting circuit to generate a proper-form second level data stream; and a multiplexer connected to an output of said data correcting circuit and multiplexing said second level data stream corrected by said data correcting circuit to generate said second format data stream; wherein said second level data stream is arranged in packets including packet headers, and said packet header includes system clock information associated with data, and said error detecting circuit includes a separating circuit separating and extracting said second level data stream from said first format data stream, and a clock error detecting circuit connected to an output of said separating circuit and detecting the error included in said second level data stream from a transition of said system clock information in the packet header of each packet in said second level data stream extracted by said separating circuit; and wherein said data correcting circuit includes a packet type determination circuit determining a packet type of each packet of said second level data stream that is determined to include the error by said clock error detecting circuit, a system clock information estimating circuit estimating the system clock information associated with each packet of said second level data stream that is determined to include said error, and a dummy data inserting circuit generating and inserting to the data stream a dummy packet including dummy data having the system clock information estimated by said system clock information estimating circuit and of the packet type determined by said packet type determination circuit.