Patent ID: 8120520
Filing Date: 2012-02-21
Classification: H03M

Abstract:
1. A successive approximation analog/digital converter comprising: a sample & hold part sampling and holding an intensity of an analog input signal by using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal held by the sample & hold part with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal sampled by the sample & hold part with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of a most significant bit (MSB) of a digital value to be converted according to the comparison result of the second comparator, determining values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the comparison voltages by using the estimated digital values and the reference voltage.