Patent ID: 7964948
Filing Date: 2011-06-21
Classification: H01L

Abstract:
1. A chip stack, comprising: a first chip and a second chip stacked on the first chip, each of the first and second chips including, a substrate having an active surface and an inactive surface opposite to the active surface, an internal circuit in the substrate, an input/output (I/O) chip pad on the active surface and connected to the internal circuit through an I/O buffer, and an I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring, the I/O connection pad being electrically between the I/O buffer and the internal circuit; and a redistributed I/O chip pad layer on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad, wherein the I/O connection pads of the first chip and the second chip are electrically connected to each other by an electrical connecting part.