Patent ID: 7479912
Filing Date: 2009-01-20
Classification: G06F,H04W,Y02D

Abstract:
1. A low-power data conversion system for converting a serial digital data input signal to an analog output signal, comprising: (a) a digital processor, the digital processor generating the serial digital data input signal in a burst mode; (b) a serial interface circuit for converting the serial digital data input signal from serial format into parallel format, the digital processor being in a high power mode while generating the serial digital data input signal in the burst mode, the digital processor being in a low power mode during at least some of the time during which the digital processor is not generating the serial digital data input signal; (c) a FIFO (first in, first out) system for receiving and temporarily storing a predetermined number of samples of the parallel format digital data input signal, the samples having a first sample rate; (d) an audio DAC coupled to receive the samples having a second sample rate and convert them to the analog output signal; and (e) a clock generation system which establishes timing of various clock signals for the serial interface circuit, the FIFO system, and the audio DAC, the first sample rate being established by a predetermined ratio between an external reference clock rate and the first sample rate.