Patent ID: 6753599
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A stack structure comprising a lower package and an upper package, the upper package stacked above the lower package, each package respectively comprising:a lead frame having a die pad and a plurality of leads disposed around the die pad; at least one semiconductor integrated circuit chip attached to the die pad; and a molding part for encapsulating the lead frame and the chip, wherein the molding part includes an upper molding portion having a first width; a lower molding portion having a second width smaller than the first width such that the lower surfaces of a portion of the leads are exposed while the upper surfaces of the portion of the leads are covered by the upper molding portion, the upper molding portion disposed above the lead frame and the lower molding portion disposed below the lead frame, the exposed portion of the leads located outside the lower molding portion; projections formed on the upper molding portion; and recesses formed in the lower molding portion, each of the projections corresponding to a respective one of the recesses in position and shape, and the leads extend from a side surface of the upper molding portion and bend upward and away from the upper molding portion, wherein the packages are stacked by engaging the projections of the lower package with the recesses of the upper package, and the bending parts of the leads of the semiconductor packages are interconnected with a conductive adhesives, wherein the plurality of leads each comprise an inner lead and an outer lead, the outer lead extending from the side surface of the upper molding portion, the outer lead having an upper end and a lower end, and wherein the upper end of the outer lead of the lower package is connected to the lower end of the outer lead of the upper package.