Patent ID: 6587396
Filing Date: 2003-07-01
Classification: H01L

Abstract:
A structure of a horizontal surrounding gate (HSG) flash memory cell, comprising:a substrate comprising an isolation region, a channel region, and a trench located on the isolation region formed on the substrate, wherein the size of the isolation region is larger than the size of the channel region, and the channel region is all covered by the isolation region; a source and a drain, wherein the source and the drain are located beside two sides of the channel region respectively; a plurality of spacers, wherein the spacers are located beside a sidewall of the trench and on the isolation region; a crystallized semiconductor film located on a portion of the spacers, wherein the crystallized semiconductor film is connected with the source and the drain respectively; an oxide layer surrounding and encompassing the crystallized semiconductor film; a floating gate, wherein the oxide layer is surrounded and encompassed by a portion of the floating gate, and the spacers, the isolation region, and the trench are covered by an other portion of the floating gate; a dielectric layer, wherein the portion of the floating gate is surrounded and encompassed by a portion of the dielectric layer, and the other portion of the floating gate is covered by an other portion of the dielectric layer; and a control gate, wherein the portion of the dielectric layer is surrounded and encompassed by the control gate, and the other portion of the dielectric layer is covered by the control gate.