Patent ID: 6219292
Filing Date: 2001-04-17
Classification: G11C

Abstract:
A semiconductor memory device for reducing system power consumption during a refresh operation by performing a consecutive refresh operation in a burst method, comprising:a memory cell array having a plurality of memory cells storing data;a command decoder for outputting a refresh command controlling a refresh operation according to a chip selection signal, a row address strobe signal, a column address strobe signal, and a write enable signal;a mode register set for programming a number of the refresh operations to be consecutively performed, said number of the refresh operations being consecutively performed according to a burst method without externally consecutively supplying a refresh signal for every refresh operation, thereby reducing power consumption;a burst counter for counting the number of the refresh operations according to the output signal from the mode register set;a first timing signal generating unit for generating an internal refresh enable signal for an inside refresh operation according to the output signal from the command decorder;an internal refresh signal generating unit for outputting a previously-set number of internal refresh signals according to the output signal from the first timing signal generating unit;a NOR gate for NORing the output signal from the command decoder and the output signal from the internal refresh signal generating unit;a second timing signal generating unit for outputting a refresh enable signal for the inside refresh operation according to the output signal from the NOR gate;a pulse generating unit for generating a pulse signal disabling the refresh enable signal by using the output signal from the second timing signal generating unit, and supplying it to the second timing signal generating unit;a counter for outputting an internal address performing the refresh operation according to the output signal from the NOR gate;an address buffer for receiving an external address;a multiplexer for outputting the internal address outputted by the counter during the refresh operation, and selectively outputting the external address inputted to the address buffer during the refresh operation; anda word line driving unit for driving the word line of the memory cell array according to the address which is selectively outputted by the multiplexer.