Patent ID: 7696048
Filing Date: 2010-04-13
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a first gate and a second gate in a first region and a second region of a semiconductor substrate, respectively; sequentially forming first, second, and third layers of a first, second, and third insulating material, respectively, to cover the first gate and the second gate; anisotropically etching the third layer using the second layer as an etch stop to form a spacer first pattern of the third layer; selectively exposing and anisotropically etching a portion of the second layer over the second region to form a spacer second pattern of the second layer on a side portion of the second gate; etching another portion of the second layer to form a spacer third pattern of the second layer over the first region while forming a recessed spacer second pattern by recessing the spacer second pattern; and forming a first spacer and a second spacer by selectively etching the spacer first pattern and an exposed portion of the first layer, wherein the first spacer comprises a portion of the first layer and the spacer third pattern similar in height to the first gate, and the second spacer comprises a portion of the first layer recessed to expose a side surface of an upper portion of the second gate and the recessed spacer second pattern, the second spacer being lower than the first spacer.