Patent ID: 7012024
Filing Date: 2006-03-14
Classification: H01L

Abstract:
1. A method of forming a semiconductor memory device having a transistor comprising: providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon; forming a polysilicon layer on the oxide layer; forming a trench isolation material over the polysilicon layer; forming a patterned photoresist having an opening therein over the trench isolation material; etching a trench into the trench isolation material through the opening and exposing a portion of the underlying polysilicon layer; growing epitaxial silicon into the bottom of the trench on the exposed portion of the underlying polysilicon layer; depositing a metal layer along the sidewalls of the trench and on the epitaxial silicon; performing a first anneal on the semiconductor assembly to cause the metal layer to react with the epitaxial silicon to form metal silicide; removing any un-reacted metal layer; performing a second anneal step to continue the formation of metal silicide; depositing an isolation capping material into the trench and over the metal silicide; removing the lateral component of the isolation capping material; etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide; implanting conductive dopants into the conductive silicon substrate to form self-aligned lightly doped source/drain regions of the transistor; forming transistor gate sidewall isolation spacers; and implanting conductive dopants into the conductive silicon substrate to form source/drain regions of the transistor.