Patent ID: 8466923
Filing Date: 2013-06-18
Classification: G06T,G09G

Abstract:
1. A method of controlling an operation of writing data to a graphic memory having a first memory area separated from a second memory area, the method comprising: latching first input data in response to a first clock signal; and writing the first input data to the first memory area in response to a second clock signal while simultaneously writing second input data received after the first input data to the second memory area, wherein the graphic memory is included in a display driver integrated circuit, wherein the first input data and the second input data are from a same column of input data stream, wherein the first memory area is apportioned into a first memory upper subblock having upper columns and a first memory lower subblock having lower columns, and the second memory area is apportioned into a second memory upper subblock having upper columns and a second memory lower subblock having lower columns, and wherein the first input data is written to an upper column of the first memory area and simultaneously the second input data is written to a lower column of the second memory area.