Patent ID: 7564084
Filing Date: 2009-07-21
Classification: H01L

Abstract:
1. A dynamic random access memory (DRAM) device comprising: a semiconductor substrate having a cell array field; pillar-shaped active patterns extended from the semiconductor substrate on the cell array field, each of the pillar-shaped active patterns including a source region contacting with the semiconductor substrate, a drain region formed over the source region, and a channel region interposed between the source and drain regions; bit lines arranged on the pillar-shaped active patterns, connecting the drain regions with each other along a direction; word lines interposed among the pillar-shaped active patterns, intersecting the bit lines; and gate insulation films interposed between the word lines and the pillar-shaped active patterns, wherein two word lines disposed at both sidewalls of one of the pillar-shaped active patterns are electrically separated from each other.