Patent ID: 6215140
Filing Date: 2001-04-10
Classification: H01L

Abstract:
An electrically programmable, non-volatile memory cell configuration, comprising:a semiconductor substrate of a first conductivity type having a trench with at least one side wall formed therein;at least one first address line running along said side wall of said trench in said substrate, and at least one second address line in said substrate crossing said first address line at a spaced distance therefrom;a memory cell substantially between said first address line and said second address line at least partially in said semiconductor substrate, said memory cell having at least one first doped region of a second conductivity type forming a direct junction between said first and second conductivity types, said direct junction allowing an electrical current flow between said first address line and said second address line in said semiconductor substrate to be limited unidirectionally; andat least one intermediate layer on said semiconductor substrate between said first address line and said second address line forming a part of said memory cell.