Patent ID: 7741704
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A method for providing an interference interlock between leadframe features and a molding compound in a packaged semiconductor device, the method comprising: exposing at least one predetermined surface area of the leadframe to an etching process that produces an etched recess with a recessed wall that extends from a top wall toward a bottom wall, wherein the recessed wall being delimited by a step wall generally perpendicular and adjacent to the recessed wall, and wherein the step wall being at least partially undercut by etching to form a curve from the top wall to the recess wall that is substantially concave in shape; and in a subsequent molding step, contacting both the recessed wall and the step wall by and embedding the recessed wall and the step wall in the molding compound; wherein multiple similar semiconductor devices are simultaneously packaged on a common leadframe, and the multiple packaged semiconductor devices are separated into individual devices by cutting through the cured molding compound and common leadframe along predetermined separation lines; wherein at least one of the separation lines extends through an etched recess in the leadframe.