Patent ID: 6301145
Filing Date: 2001-10-09
Classification: G11C

Abstract:
A ferroelectric memory, comprising:a first bit line,a second bit line,a first word line,a second word line,a plurality of plate lines,a first cell string having a first node electrode, a first path transistor connected between said first bit line and said first node electrode and held in a conductive state or a nonconductive state according to a voltage supplied to said first word line, and a plurality of ferroelectric capacitors with one electrodes commonly connected to said first node electrode and the other electrodes connected to plate lines different from each other,a second cell string having a second node electrode, a second path transistor connected between said second bit line and said second node electrode and held in the conductive state or the nonconductive state according to the voltage supplied to said second word line, and a plurality of ferroelectric capacitors with one electrodes commonly connected to said second node electrode and the other electrodes connected to plate lines different from each other, anda means for simultaneously selecting said first word line and second word line, making them hold said first path transistor and second path transistor in a conductive state in parallel, and storing one bit in a pair of ferroelectric capacitors in said first and second cell strings sharing a plate line as electrodes.