Patent ID: 8156458
Filing Date: 2012-04-10
Classification: G06F

Abstract:
1. A method, comprising: generating, by a computing system, a representation of an integrated circuit design; inserting a first 1×N building block into the representation; and creating a relationship between the first 1×N building block and a second 1×N building block, wherein the first 1×N building block and the second 1×N building block are logically equivalent, and wherein the relationship enables the first 1×N building block to inherit attributes of the second 1×N building block and enables the first 1×N building block to comprise attributes which differ from attributes of the second 1×N building block, and wherein the representation comprises the first 1×N building block and the second 1×N building block, and wherein the representation comprises one of a behavioral representation, a logical representation, and a physical design representation of the integrated circuit design, and wherein the attributes which differ comprise one of drive-strength, Vt-hybridization, voltage-island, overhead cell type, and bit width; and determining the logical equivalency of the first 1×N building block and the second 1×N building block via a call of a 1×N compiler to an equivalency-checker tool, wherein the creating the relationship comprises comparing the representation with a uniquification list of the second 1×N building block to determine the logical equivalency.