Patent ID: 7739422
Filing Date: 2010-06-15
Classification: G06F

Abstract:
1. A data processing system comprising: a memory comprising physical address space; a Direct Memory Access (DMA) controller; an operating system (OS) kernel that controls access to the memory and communicates with the DMA controller to complete virtual-to-real memory access; a device driver associated with the OS kernel, said device driver comprising logic which: implements application programming interfaces (APIs) that enable the device driver to allocate a specific, contiguous Input/Output (IO) DMA address space to an adapter/IO device during initial program launch (IPL), wherein the allocated contiguous IO DMA address space is later utilized to perform DMA mapping operations associated with that IO device, without incurring the latency of a search for contiguous DMA address space when the DMA address space is later required by the IO device; and issues, during the IPL of the adapter/IO device, a first API call with a first API command to reserve a contiguous IO DMA address space for the adapter/IO device, wherein said first API call includes a size of the contiguous IS DMA address space requested; and calling a second API to map virtual memory address space to the contiguous IO DMA address space requested by the device driver during the IPL, wherein the start IO DMA address and size of the contiguous IO DMA address space are maintained by the device driver; wherein the APIs comprise: wherein said APIs: (a) enable the device driver of the adapter/IO device to perform its own IO DMA address mapping; and (b) enable substantial reduction of IO DMA address fragmentation and reduces latency for performing DMA address mapping requiring contiguous IO DMA address space.