Patent ID: 6645779
Filing Date: 2003-11-11
Classification: H01L

Abstract:
A ferroelectric random access memory (FeRAM) device comprising:a semiconductor substrate; a transistor having a gate insulating film, a gate electrode and a source/drain region that are formed in the semiconductor substrate; a first interlayer insulating film formed over the transistor; a plug buried in a contact hole exposing the source/drain region of the transistor through a selective etching process of the first interlayer insulating film; a first oxidation barrier film formed on the plug and the first interlayer insulating film; a lateral oxidation barrier film formed on sidewalls of the first oxidation barrier film and a portion of the first interlayer insulating film in order to prevent oxygen from diffusion into interface therebetween, wherein the lateral oxidation barrier film includes a second oxidation barrier film formed on sidewalls of the first oxidation barrier film and on a portion of the first interlayer insulating film, and a third oxidation barrier film formed on the second oxidation barrier film; a bottom electrode formed on the first oxidation barrier film, the second barrier film and the lateral oxidation barrier film; a ferroelectric thin film formed on the bottom electrode; and a top electrode formed on the ferroelectric thin film.