Patent ID: 6768362
Filing Date: 2004-07-27
Classification: H03L

Abstract:
An apparatus comprising:a first circuit configured to generate a second reference signal in response to (i) a first reference signal and (ii) a timing signal, wherein (a) a frequency and a phase of said second reference signal are (i) adjusted in response to said first reference signal and (ii) held when said first reference signal is lost and (b) said first reference signal comprises an external timing signal, wherein said first circuit comprises a digitally controlled reference loop circuit, comprising (i) a control circuit configured to generate a control signal in response to said first and second reference signals and (ii) an oscillator configured to generate said second reference signal in response to said control signal and said timing signal, wherein said control signal is held when said first reference signal is lost; a second circuit configured to generate one or more output signals in response to said second reference signal and one of said one or more output signals, wherein said one or more output signals have a controlled and/or substantially zero delay with respect to said first reference signal.