Patent ID: 6657285
Filing Date: 2003-12-02
Classification: H01L

Abstract:
A semiconductor anti-interference enclosing on the periphery of a partial circuit inside an integrated circuit comprising:a complementary metal oxide semiconductor (CMOS) structure connecting with two metal bands, one joining a Vcc positive voltage and the other joining GND, called a Vcc metal band and a GND metal band; through a contact hole, the Vcc metal band connects with the first metal band; the GND metal band also connects with the first metal band through a contact hole; the first metal band joined with Vcc further connects with a next P+ layer and a Nâˆ’ layer to form a source and a drain; the first metal band joined with GND further connects with a next poly layer through a contact hole to form a gate; an N Well is the bottom layer of the abovementioned structure and the lowest bottom layer thereof is a Pâˆ’ silicon bottom layer; wherein, through the PNP structure, the main feature is to use a parasitic capacitance formed between the source and the drain of the poly layer, the positive value P+ layer and the negative Nâˆ’ layer to generate an electromagnetic anti-interference function; wherein, the connection of the N Well and the PNP structure forcefully prevent a noisy signal current generated from the inner circuit from passing a higher voltage layer and make it discharge through a GND end with lower voltage to achieve the anti-interference function.