Patent ID: 9041093
Filing Date: 2015-05-26
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a stacking structure having a plurality of conductive layers and a plurality of insulation layers, the plurality of conductive layers and the plurality of insulation layers being stacked alternately and extending in two dimensions, the plurality of conductive layers including a memory transistor region and a contact region arranged in a first direction, the contact region being arranged in end parts of the plurality of conductive layers, the end parts of the plurality of conductive layers in the contact region collectively being formed in a step shape in a second direction perpendicular to the first direction, and both edges of the plurality of conductive layers in the memory transistor region in the second direction being aligned respectively; a semiconductor column arranged in the stacking structure, the semiconductor column extending in a third direction perpendicular to the first and second directions in the stacking structure; and memory portions arranged between the semiconductor column and each of the plurality of conductive layers.