Patent ID: 8887171
Filing Date: 2014-11-11
Classification: G06F,Y02D

Abstract:
1. An apparatus comprising: a plurality of N processor cores; a prediction mechanism to determine predicted future activity of the plurality of processor cores for a future interval, wherein the predicted future activity is based at least on a first residency of a first aggregate idle-activity pattern for the future interval from a subset of 2 a core hopping mechanism to determine if the predicted residency of the aggregate idle-activity pattern for the plurality of cores for the future interval is greater than a residency threshold and, responsive to a core hop request, perform the core hop in response to determining the predicted residency of the aggregate idle-activity pattern for the future interval is greater than the residency threshold and not perform the core hop in response to determining the predicted residency of the aggregate idle-activity pattern for the future interval is not greater than the residency threshold.