Patent ID: 6066985
Filing Date: 2000-05-23
Classification: H03F

Abstract:
An analog buffer, comprising:an input stage comprising a plurality of input MOS transistors for receiving an electrical input signal, a first node where a first electrical control signal is generated, and a second node where a second electrical control signal is generated; anda push-pull output stage comprising an output node where an electrical output signal is generated and a plurality of groups of MOS transistors including a first group of MOS transistors, a second group of MOS transistors, a third group of MOS transistors and a fourth group of MOS transistors, wherein said first group of MOS transistors is responsive to the first electrical control signal to increase the output signal in response to an increase in the input signal, wherein said second group of MOS transistors is responsive to the second electrical control signal to decrease the output signal in response to a decrease in the input signal, wherein said third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input voltage signal range and wherein said fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input voltage signal range.