Patent ID: 6716739
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A method or forming bumps on a silicon wafer having an active surface with a passivation layer and a plurality of bonding pads thereon such that the passivation layer exposes the banding pads, the method comprising the steps of:forming an adhesion layer over the active surface of the wafer, the adhesion layer covering both the bonding pads and the passivation layer, forming a barrier layer over the adhesion layer; forming a wettable layer over the barrier layer; conducting a first photolithography process to from a plurality of photoresist blocks on the wettable layer; conducting a first etching operation to remove the wettable layer and the barrier layer so that only the residual wettable layer and barrier layer underneath the photoresist blocks remain; after conducting the first etching operation, removing the photoresist blocks; after removing the photoresist blocks, conducting a second photolithography process to form a photoresist layer over the adhesion layer, wherein the photoresist layer has a plurality of openings that expose the wettable layer and the adhesion layer around the barrier layer; after conducting the second photolithography process, conducting a metal-filling operation to farm a solder material inside the openings of the photoresist layer, wherein the solder material covers the wettable layer and the adhesion layer around the barrier layer; after conducting the metal-filling operation, removing the photoresist layer; after removing the photoresist layer, conducting a first reflow operation to transform the solder material into a plurality of solder balls having a hemispherical profile, and the solder balls retracting onto the upper surface of the wettable layer without extending onto the adhesion layer; after conducting the first reflow operation, conducting a second etching operation to remove a portion of the adhesion layer so that only residual adhesion layer underneath the barrier layer is retained and the passivation layer on the wafer is exposed to the outside; and conducting a second reflow operation.