Patent ID: 6185674
Filing Date: 2001-02-06
Classification: G06F

Abstract:
A method of generating an address of the next instruction to be completed in a computer processing unit, the method comprising the steps of:for each instruction dispatched for execution,generating an identifier that identifies the instruction;adding an entry to a first table, wherein said entry of said first table comprises said identifier and a completion status field bit that indicates if the corresponding instruction is complete;if the instruction is a branch instruction, adding an entry to a second table, wherein said entry of said second table comprises said identifier, a target address of the instruction and a resolution status field that indicates at least if the instruction has been resolved taken or has been resolved not taken;updating the completion status field of entries of said first table corresponding to completed instructions;updating the resolution status field of entries of said second table according to resolution of branch instructions; andin each machine cycle, controlling a program counter to generate the address of the next instruction to be completed according to said entries of said first table and said second table, wherein the following steps are performed in a given machine cycle,reading out at least one entry from said first table; andfor each entry read from said first table whose completion status field indicates the associated instruction is completed, accessing said second table with the associated identifier of the entry to thereby determine said address of the next instruction to be completed in said computer processing unit.