Patent ID: 6728130
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A dense memory cell comprising:two access transistors, each having a gate tied to a wordline input, a first one of the access transistors having a drain and source coupled between a bit line and an output node; two storage transistors, a first one having a drain and source coupled between the output line and a power signal and a gate couple to an output bar node, the second one having a drain and source coupled between the output bar node and the power rail, and a gate coupled to the output node; and a control circuit generating a tracking voltage coupled to the wordline, the track voltage for adjusting the voltage on the wordline during an idle state to ensure that leakage current through the two access transistors exceeds the leakage through the two storage transistors where the output node to which it is coupled is at VDD.