Patent ID: 6829322
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A shift-register unit, comprising:a first transistor having a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal; a second transistor having a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to an initial shift-register unit; a third transistor having a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal; and a fourth transistor having a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.