Patent ID: 6069509
Filing Date: 2000-05-30
Classification: H03K

Abstract:
An output stage comprising an input terminal (IP) for receiving an input signal (V.sub.i); an output terminal (OP) for delivering an output signal (V.sub.o) in response to the input signal (V.sub.i); a first (1) and a second (2) supply terminal for receiving a supply voltage (SV); a field effect transistor (Q1) comprising a gate (GN), and a main current path between a source and a drain coupled between the first supply terminal (1) and the output terminal (OP); and slewing control means (SCM) for reducing the speed of voltage change at the gate (GN) of the field effect transistor (Q1) for reducing the speed of current change through the main current path of the field effect transistor (Q1) when the output signal (V.sub.o) changes from a first steady state (FST) via a transition area (TRE) to a second steady state (SST), characterized in that the slewing control means (SCM) comprises first means for reducing the gate-source voltage V(GN) of the field effect transistor (Q1) in at least part of the transition area (TRE) when the field effect transistor (Q1) changes from a non-conducting state to a conducting state and thus causes the output signal (V.sub.o) to be changed from the first steady state (FST), via the transition area (TRE), to the second steady state (SST).