Patent ID: 6519844
Filing Date: 2003-02-18
Classification: H01L,Y10T

Abstract:
A process for manufacturing an integrated circuit package, comprising:(a) providing a substrate having an upper surface and an air space above the upper surface; (b) forming a plurality of electrically conductive vias through the upper surface of the substrate and extending at least partially through the substrate, where at least a portion of the plurality of vias extend completely through the substrate; (c) providing fluid communication between the plurality of vias and the air space thereabove; (d) attaching an integrated circuit die to the upper surface of the substrate over at least a portion of the plurality of vias, while leaving a gap between the die and the upper surface of the substrate; and (e) flowing molding compound at least into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the plurality of vias and the air space, thereby urging air trapped between the molding compound and the upper surface of the substrate to flow into the plurality of vias, and venting any air bubbles trapped between the molding compound and the upper surface of the substrate through the at least a portion of the plurality of vias which extend completely through the substrate.