Patent ID: 9069688
Filing Date: 2015-06-30
Classification: G06F

Abstract:
1. A method of operating a non-volatile memory system, the non-volatile memory system including a controller circuit having a memory interface, a memory circuit having an array of non-volatile memory cells and a controller interface, and a bus structure connected to the memory interface of the controller circuit and to the controller interface of the memory circuit for the transfer of data and commands therebetween, wherein the memory system can tolerate a first, non-zero amount of accumulated data error from when a unit of data is transferred from the controller to be written to the memory array until the unit of data is received at the controller after subsequently being read back from the memory array, the method comprising: allotting by the controller circuit of a first, non-zero portion of the first amount of accumulated data error to the transfer of data between the controller circuit and the memory circuit via the bus structure, the remainder of the first amount of accumulated data error being allotted to write, storage, and read of data on the memory circuit; and setting by the controller circuit of the transfer characteristics between the controller circuit and the memory circuit to operate to allow up to the first portion of the first amount of accumulated data error.