Patent ID: 6768521
Filing Date: 2004-07-27
Classification: G02F,H01L

Abstract:
A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising the steps of:forming by a first photolithography process a gate wire, including a gate line, a gate electrode connected to the gate line and a gate pad that receives an external gate signal, on an insulating substrate; depositing sequentially a gate insulating layer covering the gate wire, a semiconductor layer, an ohmic contact layer, and a first conductive layer; patterning by a second photolithography process, the first conductive layer to form a data wire including a data line intersecting the gate line, a source electrode connected to the data line and extended over the gate electrode, a drain electrode located opposite to the source electrode with respect to the gate electrode and a data pad that receives an external data signal; removing portions of the ohmic contact layer not covered by the data wire; depositing a protection layer; patterning by a third photolithography process, the protection layer to form a first contact hole exposing the drain electrode, along with the semiconductor layer and the gate insulating layer; depositing a second conductive layer; and patterning the second conductive layer to form a pixel electrode connected to the drain electrode through the first contact hole of the protection layer.