Patent ID: 7932606
Filing Date: 2011-04-26
Classification: H01L

Abstract:
1. A semiconductor integrated circuit device, comprising: (a) a first interconnect made of a first metal film and formed over a main surface of a semiconductor substrate; (b) a first interlayer insulating film formed over the first interconnect; (c) a first via hole formed in the first interlayer insulating film and connected to the first interconnect; (d) a first interconnect trench formed in the first interlayer insulating film in a region including a region in which the first via hole has been formed; (e) a second interconnect formed by filling a second metal film in the first interconnect trench and the first via hole; (f) a third interconnect made of a third metal film and formed over the second interconnect and the first interlayer insulating film; (g) a second interlayer insulating film formed over the third interconnect; (h) a second via hole formed in the second interlayer insulating film and connected to the third interconnect; (i) a second interconnect trench formed in the second interlayer insulating film in a region including a region in which the second via hole has been formed; and (j) a fourth interconnect formed by filling a fourth metal film in the second interconnect trench and the second via hole, wherein the second interlayer insulating film is thicker than the first interlayer insulating film, wherein a first etching stopper film is formed in the second interlayer insulating film, wherein a bottom of the second interconnect trench is arranged near the stopper film, wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench, wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film, wherein a diameter of the second via hole is greater than a diameter of the first via hole, wherein the first interlayer insulating film has a first barrier insulating film which prevents diffusion of copper, the first barrier insulating film being in contact with a surface of the first interconnect and including silicon, carbon and nitrogen, wherein the second interlayer insulating film has a second barrier insulating film which prevents diffusion of copper, the second barrier insulating film being in contact with a surface of the third interconnect and including silicon, carbon, and nitrogen, wherein the first etching stopper film includes silicon and nitrogen, and wherein dielectric constants of the first and second barrier insulating films are less than a dielectric constant of the first etching stopper film.