Patent ID: 7692986
Filing Date: 2010-04-06
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell having a field effect transistor of a floating body type, and a capacitor for storing a data charge; a bit line to which one of the source and the drain of the field effect transistor is connected; a precharging device for performing precharge control of the bit line so that the bit line has a predetermined precharge voltage; a sense amplifier for amplifying and storing the potential of the bit line, which is set in accordance with the data charge read from the memory cell; a switching device, provided between the bit line and the sense amplifier, for performing selective connection therebetween; and a control part for controlling the precharging device, the sense amplifier, and the switching device, wherein except for each period for performing data reading or writing, the control part makes the precharging device perform the precharge control of the bit line and makes the switching device disconnect the bit line and the sense amplifier from each other.