Patent ID: 7839613
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection circuit for protecting an internal circuit of a semiconductor, the ESD protection circuit being installed between an input/output pad and an input buffer including a first NMOS transistor, the ESD protection circuit comprising: a first electrostatic protection unit connected to a power source supply pad, wherein the first electrostatic protection unit discharges an ESD current into a power source supply voltage pad and a ground voltage supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit; a driver driven by the first driving voltage, wherein the driver generates a second driving voltage by an ESD current; and a second electrostatic protection unit for discharging the introduced ESD current into the ground voltage supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced, wherein the driver includes a PMOS transistor having a source and a substrate directly connected to the input/output pad and a gate connected to the power source supply pad.