Patent ID: 6496414
Filing Date: 2002-12-17
Classification: G11C

Abstract:
A nonvolatile semiconductor memory comprising:a plurality of nonvolatile memory cells connected in series via input/output nodes; a word line connected to control gates of said memory cells; a plurality of bit lines connected to said input/output nodes, respectively; a plurality of switches connected to said bit lines, respectively; four bit line pairs each consisting of two of said bit lines respectively positioned on the outsides of four successive memory cells among said memory cells; four data lines Connected to said bit line pairs via said switches, respectively; a switching control circuit for turning on said switches corresponding to five of said input/output nodes adjacent to each other in a read operation, said five of said input/output nodes including said input/output nodes of two of said memory cells for data to be read from simultaneously; a first sense amplifier and a second sense amplifier for amplifying said data read out from said two memory cells respectively; and a switching circuit for respectively connecting said first and second sense amplifiers to two of said data lines, and for connecting supply nodes of a first voltage and a second voltage to the remaining two of said data lines, respectively.