Patent ID: 7057427
Filing Date: 2006-06-06
Classification: H03K

Abstract:
1. A power on reset circuit that generates a reset signal, comprising: a detector that receives a supply voltage and generates a detect signal when the supply voltage exceeds a predetermined voltage value; an oscillator circuit that generates a clock output signal; a counter, connected to the detector and the oscillator circuit, wherein when the detect signal is one of high and low, the counter counts cycles of the clock output signal and generates a first counter output signal at a first predetermined count value and a second counter output signal at a second predetermined count value; and a latch circuit, connected to the counter and the detector and receiving the first counter output signal, the second counter output signal, and the detect signal, wherein when the counter reaches the first predetermined count value, the latch circuit activates the reset signal, and when the counter reaches the second predetermined count value, the latch circuit activates a power down signal that is provided to the detector and the oscillator circuit.