Patent ID: 6207497
Filing Date: 2001-03-27
Classification: H01L

Abstract:
A method for fabricating a DRAM cell, the method comprising:providing a substrate;depositing a blanket first dielectric layer over the substrate;forming a first photoresist layer over said first dielectric layer, wherein said first photoresist layer is defined and etched to form a contact opening in the first dielectric layer;forming a first conductive layer to fill said contact opening, and performing an etching process to remove a portion of said first conductive layer to form a node contact;depositing a second conductive layer over said first dielectric layer and the node contact;forming a second photoresist layer over said second conductive layer, wherein said second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor;forming a hemispherical silicon grain (HSG) over and on a sidewall of said second conductive layer;treating said hemispherical silicon grain (HSG) layer by rapid thermal nitration (RTN);depositing a conformal second dielectric layer over said hemispherical silicon grain (HSG) and said first dielectric layer after rapid thermal nitration (RTN); andforming a blanket third conductive layer over said substrate to serve as the upper electrode of the capacitor.