Patent ID: 6072725
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A method of erasing a floating gate capacitor of a circuit comprising the floating gate capacitor and a voltage regulator, the floating gate capacitor having a first plate comprising a source, a drain, and a channel region of a floating gate transistor commonly connected at a well node, and a second plate comprising a control gate of the floating gate transistor; the voltage regulator comprising a first capacitor having a first plate coupled to the control gate and a second plate coupled to a voltage to be regulated, and a comparator having a first input coupled between the control gate and the first plate of the first capacitor and a second input connected to a reference voltage, which method comprises:applying a potential to the gate of a first pass transistor, coupled between the control gate and ground, greater than or equal to a threshold voltage of the first pass transistor, to connect the control gate to ground;applying a capacitor erase signal to the gate of a second pass transistor, coupled between the well node and ground, to turn off the second pass transistor and isolate the well node from ground;applying the capacitor erase signal to an erase voltage pass circuit connected to the gate of a third pass transistor, coupled between the well node and an erase voltage source, to control the third pass transistor to apply an erase voltage to the well node to erase the floating gate capacitor; andapplying the capacitor erase signal to the gate of a fourth pass transistor, coupled between the second plate of the first capacitor and the reference voltage.