Patent ID: 6060904
Filing Date: 2000-05-09
Classification: H03K

Abstract:
A level shifter circuit having an input terminal supplied with an input signal having a low level, a switching terminal supplied with a switching signal, an inverting output terminal for outputting an inverted output signal having inverse phase with the input signal, a non-inverting output terminal for outputting a non-inverted output signal having in phase with the input signal, a power supply terminal supplied with a power supply voltage, and a variable voltage terminal supplied with a level shift variable voltage for varying the low level of the input signal from a zero voltage to a predetermined negative voltage, said level shifter circuit being for carrying out level conversion operation on the input signal in response to the switching signal, said level shifter circuit shifting a low level of the inverted output signal and the non-inverted output signal into the level shift variable voltage when the switching signal indicates a level shift, wherein said level shifter circuit comprises:an inverter, connected to the input terminal, for inverting the input signal, said inverter having an output terminal for producing an inverted input signal;a first P-channel transistor having a source electrode connected to the power supply terminal, a gate electrode connected to the input terminal, and a drain electrode;a second P-channel transistor having a source electrode connected to the power supply terminal, a gate electrode connected to the output terminal of said inverter, and a drain electrode;a first N-channel transistor having a source electrode connected to the variable voltage terminal, a drain electrode connected to a first node, and a gate electrode connected to a second node;a second N-channel transistor having a source electrode connected to the variable voltage terminal, a drain electrode connected to the second node, and a gate electrode connected to the first node;first breakdown preventing means, connected between the drain electrode of said first P-channel transistor and the inverting output terminal, for preventing said first P-channel transistor from breaking down;second breakdown preventing means, connected between the drain electrode of said second P-channel transistor and the non-inverting output terminal, for preventing said second P-channel transistor from breaking down;first gate destruction preventing means, connected to the first node, the switching terminal, and the inverting output terminal, for preventing the gate electrode of said first N-channel transistor from destroying;second gate destruction preventing means, connected to the second node, the switching terminal, and the non-inverting output terminal, for preventing the gate electrode of said second N-channel transistor from destroying;accelerating means, connected between the first and the second nodes and the switching terminal, for accelerating a switching speed for signals;first node potential fixing means, connected to the input terminal, the switching terminal, and the first node, for fixing a potential of the first node; andsecond node potential fixing means, connected to the output terminal of said inverter, the switching terminal, and the second node, for fixing a potential of the second node.