Patent ID: 6366978
Filing Date: 2002-04-02
Classification: G06F,G11C

Abstract:
Apparatus for processing data having a cache memory, said cache memory comprising:(i) a plurality of content addressable storage rows, each content addressable storage row containing a plurality of content addressable bit storage cells and serving to store a content addressable data word; (ii) a plurality of bit lines connecting corresponding content addressable bit storage cells in different content addressable storage rows such that an input data word on said plurality of bit lines is compared in parallel with the contents of each connected content addressable storage row; (iii) a plurality of hit lines, each content addressable storage row having an associated hit line upon which a hit signal is asserted if said input data word matches a content addressable data word stored within said content addressable storage row; (iv) a plurality of cache data rows each storing a row of cache data, said content addressable memory serving to store address data to identify memory addresses for corresponding rows of cache data such that a hit signal generated on a hit line in said content addressable memory enables access to a corresponding cache data row within said cache memory; and (v) an index decoder for decoding an index value to generate a select signal for selecting a content addressable storage row and a victim cache data row for replacement within said cache memory; wherein (vi) said select signal is passed to said cache data row via a corresponding one of said hit lines.