Patent ID: 7380063
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. A system comprising: a single level cache comprising a collection of functional portions all operating at a same speed, each functional portion capable of being disabled independently of the other functional portions and capable of being flushed independently of the other functional portions in the collection so that an available size of the single level cache is variable; a processor capable of transitioning between a higher power state and a lower power state, where more power is consumed by the processor in the higher power state than in the lower power state; a cache controller to control flushing and disabling of the functional portions of the single level cache; an abort input to the cache controller to receive an abort signal indicating that a flushing of the single level cache is to be aborted; an indicator storage to store an indication of where in the single level cache flushing has been aborted; and a counter to identify an initial time in a flush when aborting of a flush is not allowed, wherein the processor is capable of generating a signal indicative of a transition from the higher power state to the lower power state, and the cache controller is to flush and disable a first functional portion of the single level cache in response to the signal indicative of the transition.