Patent ID: 8427223
Filing Date: 2013-04-23
Classification: H03K

Abstract:
1. A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising: an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node; a load circuit coupled with the input stage, the load circuit being operative to at least temporarily store a signal on at least one of the first and second nodes which is indicative of a logical state of the input signal; at least a first output stage connected with the load circuit at the second node and being operative to generate an output signal of the voltage level translator circuit which is indicative of a logical state of the input signal; and a compensation circuit connected with the first output stage and being operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node; wherein the compensation circuit comprises a first PMOS transistor having a first source/drain connected with a first output of the voltage level translator circuit, a second source/drain adapted for connection with the voltage return of the voltage level translator circuit, and a gate connected with the first node of the load circuit.