Patent ID: 6271569
Filing Date: 2001-08-07
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising:a plurality of memory cells, each of said memory cells comprising:a first interconnection layer formed on a semiconductor substrate, and including a high-resistance interconnection portion and a storage node portion, said high-resistance interconnection portion comprised of separate first and second portions, said first interconnection layer further including a power supply interconnection portion comprised of separate first and second portions respectively connected to the first and second portions of said high resistance interconnection portion;a GND interconnection layer formed on said first interconnection layer with a dielectric film therebetween, whereinsaid storage node portion of said first interconnection layer, said GND interconnection layer and said dielectric film form a capacitor element, andsaid first interconnection layer is arranged symmetrically around a center of said memory cell; anda second interconnection layer including a gate electrode, formed on said semiconductor substrate and located under said first interconnection layer; and whereinmemory cells formed next to each other in a direction of a word line have the same planar layout,the first portion of the high resistance interconnection portion of one memory cell, the first portion of the high resistance interconnection of another memory cell adjacent the one memory cell, and the first portion of the power supply interconnection connected to these first portions of the high resistance interconnection portion form a closed end area surrounded at three sides thereof,said first interconnection layer includes a lower layer in contact with said semiconductor substrate and said second interconnection layer, and an upper layer formed on said lower layer, andsaid GND interconnection layer covers side surfaces of said lower and upper layers with said dielectric film therebetween, andthe closed end area has an opening divided into two parts by the second portion of the high resistance interconnection portion of the one memory cell.