Patent ID: 6782460
Filing Date: 2004-08-24
Classification: G06F

Abstract:
A pipelined memory controller for use in a memory system having a memory device connected to the memory controller, the memory controller comprising:a first pipeline stage, comprising, a bank state module configured to generate a memory bank state for a target memory bank in the memory device, the target memory bank corresponding to a memory access request; and stall logic coupled to the bank state module, the stall logic configured to receive the memory access request and the memory bank state for the target memory bank, to detect stall conditions for the memory access request, and in response to the detected stall conditions, to output stall commands; and a second pipeline stage, comprising, a command sequencer configured to receive the memory access request and the stall commands and, in response thereto, to generate sequenced control commands for accessing the memory device, and a timing coordinator configured to receive the sequenced control commands from the command sequencer, to time the sequenced control commands to satisfy memory system timing requirements, and to generate timed and sequenced control commands for transmission to the memory device.