Patent ID: 6406962
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method of forming a FET comprising:providing a substrate having a pad layer thereover, said pad layer having a plurality of etch stop layers periodically therethrough; forming a plurality of openings adapted to connect with a plurality of contacts having varying dimensions wherein selected ones of said plurality of openings traverse through said pad layers and said plurality of etch stop layers, while still others of said plurality of openings traverse through said pad layer stopping at a selected one of said plurality of etch stop layers; forming a vertical channel in one of said selected ones of said plurality of openings traversing through said pad layers and said plurality of etch stop layers; forming first and second gates in said vertical channel; and connecting said plurality of contacts to said substrate whereby at least one of said contacts connects to said vertical channel, while at least one of said contacts connects to one of said selected ones of said plurality of openings traverse through said pad layers and said plurality of etch stop layers, while still other contacts connect to said first and second gates, thereby providing a vertical gate FET having the plurality of contacts with varying depths.