Patent ID: 6912666
Filing Date: 2005-06-28
Classification: G06F,G11C,H03L

Abstract:
1. A memory device, comprising: a plurality of memory cells; circuits, clocked by a local clock signal, for writing information into and reading information out of said memory cells; and a dual locked loop for locking said local clock signal to an external reference signal, comprising: a first locked loop for establishing a phase relationship between said local clock signal and said reference signal; and a second locked loop responsive to said first locked loop and comprising: a delay line having a first portion providing a variable amount of delay substantially independently of process, temperature and voltage variations and a second portion in series with said first portion and providing a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said local clock signal being available at said output of said delay line.