Patent ID: 6806915
Filing Date: 2004-10-19
Classification: H04L,H04N

Abstract:
An equalizer comprisingan extraction circuit adapted for receiving a digital data stream input and extracting an added echo cancellation reference signal from the digital data stream transmitted over a transmission path so that said digital data stream has the echo cancellation reference signal substantially removed therefrom; a microprocessor coupled to the extraction circuit for calculating filter coefficients from the extracted echo cancellation reference signal; and a filter receiving the digital data stream at an input thereof and coupled to the microprocessor for receiving the filter coefficients and substantially canceling echo interference from the digital data stream using the filter coefficients; wherein the echo cancellation reference signal is non-cyclic, has a substantially flat frequency response within the bandwidth of the transmission path, has a large plurality of amplitude peaks over a time interval, and has proportionally shorter tails relative to the large plurality of amplitude peaks; wherein the echo cancellation reference signal is of a class of signals substantially defined by: f&it;(t)=12&it;Ï€&it;&Integral;0Î©&it;[A&it;â€ƒ&it;cos&it;(b&it;â€ƒ&it;Ï‰2)+j&it;â€ƒ&it;A&it;â€ƒ&it;sin&it;(b&it;â€ƒ&it;Ï‰2)]&it;&ee;jÏ‰&it;â€ƒ&it;t&it;â€ƒ&it;&dd;Ï‰+12&it;Ï€&it;&Integral;-Î©0&it;[A&it;â€ƒ&it;cos&it;(-b&it;â€ƒ&it;Ï‰2)+j&it;â€ƒ&it;A&it;â€ƒ&it;sin&it;(-b&it;â€ƒ&it;Ï‰2)]&it;&ee;jÏ‰&it;â€ƒ&it;t&it;â€ƒ&it;&dd;Ï‰A, b and &OHgr; being real numbers.