Patent ID: 8891212
Filing Date: 2014-11-18
Classification: H01L,H02H,H03K,Y10T

Abstract:
1. A circuit for protecting an integrated circuit from an electrostatic discharge (ESD) event, the circuit comprising: a trigger circuit including a first resistor and a capacitor coupled in series with the resistor; a semiconductor-controlled rectifier coupled to the trigger circuit, the semiconductor-controlled rectifier having an anode and a cathode; a signal pad coupled to the anode or the cathode of the semiconductor-controlled rectifier and the integrated circuit at a first node; and a first diode having a first terminal coupled to the first node and a second terminal coupled to the first resistor of the trigger circuit at a second node, wherein the first diode is configured to isolate the signal pad from the trigger circuit when the integrated circuit is powered, and the first diode is configured to couple the signal pad to the trigger circuit in response to the ESD event and when the integrated circuit is unpowered.