Patent ID: 6898118
Filing Date: 2005-05-24
Classification: G11C

Abstract:
1. A nonvolatile memory apparatus comprising: a control circuit; a plurality of terminals including a clock terminal, a command terminal and an other terminal; a converter circuit; and a plurality of nonvolatile memory cells, wherein said clock terminal receives a clock signal, wherein said command terminal receives commands which comprise a read command and a program command, wherein said control circuit reads out operation steps from a program memory for controlling an operation of said received command by executing said operation steps, wherein in an operation in response to said read command received from said command terminal, said control circuit controls, based on operation steps corresponding to said read command, reading data in parallel from ones of said nonvolatile memory cells, converting parallel type data to serial type data by said converter circuit, and serially outputting data via said other terminal except said command terminal in response to said clock signal, and wherein in an operation in response to said program command received from said command terminal, said control circuit controls, based on operation steps corresponding to said program command, serially receiving data via said other terminal except said command terminal in response to said clock signal, converting serial type data to parallel type data by said converter circuit, and writing data in parallel to ones of said nonvolatile memory cells.