Patent ID: 7702061
Filing Date: 2010-04-20
Classification: H03K

Abstract:
1. A multi-bit counter, comprising: a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals; at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells; a reload signal being input into the asynchronous base counter cells; a clock signal being input into the asynchronous base counter cells; and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal; further wherein the asynchronous base counter cells comprise: a first flip-flop operably coupled to a second flip-flop; a circuit for building a count reload function operably coupled to the first and second flip-flop; and an output circuit operably coupled to the first and second flip-flop, the output circuit providing an output signal from one of the plurality of asynchronous base counter cells to a subsequent one of the plurality of asynchronous base counter cells.