Patent ID: 8809990
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate comprising a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and comprising a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and comprising a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode, a pair of second spacer layers disposed at both sides of the second gate electrode, wherein the second gate insulating layer extends from a space between the second gate electrode and the second active region to a space between the second gate electrode and the second spacer layer, and an interfacial oxide layer is formed between the second gate insulating layer and the pair of second spacer layer, wherein the second source/drain region has a smaller thickness than a thickness of the first source/drain region, and wherein a width of the first active region in a direction in which the first gate electrode extends, is greater than a width of the second active region in a direction in which the second gate electrode extends.