Patent ID: 7903454
Filing Date: 2011-03-08
Classification: G11C

Abstract:
1. An integrated circuit comprising a plurality of thermal selectable memory cells, each memory cell being coupled to a conductive line, the conductive line comprising a first portion for applying a heating current, and a second portion for applying a programming current, the integrated circuit being configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other, wherein a first end of the conductive line is coupled to a first area set to a first potential, and wherein a second end of the conductive line is coupled via a switch to a second area set to a second potential, wherein the first potential and the second potential are fixed potentials, further comprising a potential controlling unit is coupled between the second area and the switch, wherein the potential controlling unit controls a potential drop between the second area and the second end of the conductive line such that the potential of the second end of the conductive line is controlled to a third potential.