Patent ID: 9106227
Filing Date: 2015-08-11
Classification: H01F,H01G,H01L,H03H,H03J,H03K,H03M

Abstract:
1. A circuit coupled between a first terminal and a second terminal, comprising: a plurality of stacked elements, the stacked elements proceeding from a first element of the stacked elements, closest the first terminal and farthest from the second terminal to an n-th element of the stacked elements farthest from the first terminal and closest to the second terminal, a plurality of compensating capacitors associated with the stacked elements, wherein: nodes between the elements exhibit parasitic capacitances, the first terminal is a terminal through which a voltage source is coupled to the circuit; the stacked elements comprise a first set of elements close to the first terminal and far from the second terminal and a second set of elements far from the first terminal and close to the second terminal, the compensating capacitors comprise a first set of compensating capacitors associated with the first set of elements and a second set of compensating capacitors associated with the second set of elements, the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first element of the first set of elements, the second capacitor of the first set of capacitors being located in parallel with a series of the first element and a second element of the first set of elements, the third capacitor of the first set of capacitors being located in parallel with a series of the first element, the second element and a third element of the first set of elements and so on, the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first element of the second set of elements, the second capacitor of the second set of capacitors being located in parallel with a series of the first element and a second element of the second set of elements, the third capacitor of the second set of capacitors being located in parallel with a series of the first element, the second element and a third element of the second set of elements and so on, and a combination of elements of the stacked elements, parasitic capacitances and compensating capacitors at each node provides a compensated capacitance value for that node, the compensated capacitances values of the nodes being symmetric with respect to a central node of the nodes.