Patent ID: 9190129
Filing Date: 2015-11-17
Classification: G06F,G11C,H04L

Abstract:
1. A method for preamble release training in a double data-rate memory device interface, comprising: generating a first signal in response to an initiation of a read operation, the first signal delayed from the initiation of the read operation by one or more clock cycles plus a fine delay of less than one clock cycle provided by an adjustable delay circuit; providing the first signal to a data strobe parking circuit, wherein the first signal is generated in response to an output of a state machine; generating a second signal in response to the initiation of the read operation, the second signal delayed by the adjustable delay circuit, wherein the second signal is generated in response to the output of the state machine; receiving a data strobe signal associated with incoming data during the read operation; comparing an edge of the second signal with an edge of the data strobe signal associated with incoming data during the read operation; and adjusting the adjustable delay circuit in response to a result of comparing the edge of the second signal with the edge of the data strobe signal, wherein the adjustable delay circuit receives a delay input from a first delay register to generate the first signal and receives the delay input from a second delay register to generate the second signal, and wherein adjusting the adjustable delay comprises the state machine producing an adjustment output signal and then selecting one of incrementing and decrementing a first value stored in the first delay register and a second value stored in the second delay register based in part on a state of the adjustment output signal.