Patent ID: 6651148
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A memory controller for controlling memory transactions to and from a memory device in response to memory requests from requestor modules, said memory controller comprising:at least one arbiter for receiving and processing said memory requests, each memory request being received from a corresponding requestor module; a controller module for issuing at least memory read transactions to said memory device in response to signals from said at least one arbiter; an address memory means for receiving the addresses of said requestor modules initiating said memory read transactions in the order that said controller module issued said memory read transactions to said memory device, and for issuing said addresses in said order; and a data dispatcher for receiving data from said controller module in response to said memory read transactions, for receiving a next address in said order from said address memory means, and for passing data associated with each memory read transaction to said corresponding requestor module, wherein said next address is used by said data dispatcher to identify said corresponding requestor module.