Patent ID: 6137718
Filing Date: 2000-10-24
Classification: G11C,H01L

Abstract:
A method for operating a memory cell arrangement, comprising the steps of:providing memory cells having MOS transistors;providing said MOS transistors with a gate dielectric including a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer;providing the first silicon oxide layer and the second silicon oxide layer each with a thickness of at least 3 nm;using multi-value logic with more than two logic values to store information;applying a respective quantity of charge assigned to the respective logic value to the gate dielectric by Fowler-Nordheim tunneling for writing a respective logic value of the more than two logic values to one of the memory cells; andstoring the respective quantity of charge in the gate dielectric, said quantity of charge effects a threshold voltage level of the MOS transistor which is assigned to the respective logic value.