Patent ID: 6083821
Filing Date: 2000-07-04
Classification: H01L

Abstract:
A method of forming an integrated circuit comprising a first conductive line, a second conductive line and a barrier connecting the conductive lines and partially defining a cavity therebetween, the method comprising the acts of:forming a layer of conductive material on a wafer;forming a layer of photoresist over the conductive layer;etching the layers of conductive and photoresist materials to form the first conductive line and the second conductive line, each the line having a section of photoresist disposed thereon, each combination of conductive line and photoresist section having generally vertical surfaces;disposing a side wall film on the generally vertical surfaces;heating the wafer until the photoresist sections laterally deform causing two generally adjacent sidewall films to form the barrier;removing the photoresist layer without substantially removing the sidewall film; andforming a layer of dielectric material over the conductive lines and the barrier.