Patent ID: 7518424
Filing Date: 2009-04-14
Classification: H03K

Abstract:
1. An output circuit comprising: a first output transistor and a second output transistor coupled in series; an input node coupled to gates of the first output transistor and the second output transistor; an output node coupled to a common node of the first output transistor and the second output transistor; a first slew rate control circuit coupled between the first output transistor and a first power supply terminal, and configured to provide a first variable resistance in response to a first bias signal from a first bias circuit, the first slew rate control circuit further comprising a first control transistor and a second control transistor coupled in parallel, a gate of the first control transistor coupled to the first output transistor, a gate of the second control transistor coupled to receive the first bias signal; and a second slew rate control circuit coupled between the second output transistor and a second power supply terminal, and configured to provide a second variable resistance in response to a second bias signal from a second bias circuit, the second slew rate control circuit further comprising a third control transistor and a fourth control transistor coupled in parallel, a gate of the third control transistor coupled to the second output transistor, a gate of the fourth control transistor coupled to receive the second bias signal; wherein the first bias circuit comprises a first bias operational amplifier and the second bias circuit comprises a second bias operational amplifier.