Patent ID: 6717835
Filing Date: 2004-04-06
Classification: G11C,H01L

Abstract:
A semiconductor device comprising:a plurality of word lines, a plurality of data lines, and a plurality of DRAM memory cells; a plurality of sense amplifiers coupled to said plurality of data lines and each receiving operating voltage from first and second nodes; a first line connected to said first nodes; a second line connected to said second nodes; first drive means for coupling said first line with a first potential; and second drive means for coupling said second line with a second potential; wherein each of said plurality of sense amplifiers includes a first NMISFET pair arranged in a cross-coupled form and a second PMISFET pair arranged in a cross-coupled form, wherein said first drive means sets up a connection between the first potential and said first line at a first impedance in a first operation mode and a connection between the first potential and said first line at a second impedance higher than the first impedance in a second operation mode, wherein said second drive means sets up a connection between the second potential and said second line at a third impedance in the first operation mode and a connection between the second potential and said second line at a fourth impedance higher than the third impedance in the second operation mode, wherein said first drive means includes a first NMISFET and a first PMISFET disposed in parallel between said first line and the first potential, and wherein said second drive means includes a second NMISFET and a second PMISFET disposed in parallel between said second line and the second potential.