Patent ID: 6255990
Filing Date: 2001-07-03
Classification: H01Q

Abstract:
A processor for an array antenna having a plurality of antenna elements arranged as a number of row positions equal to M and a number of column positions equal to N, for receiving an incident beam signal, the processor comprising:a plurality of frequency translation circuits operatively coupled to the antenna elements and shifting the incident beam signal to one of a plurality of column intermediate frequencies;M row processing circuits, said row processing circuits being responsive to signals from said frequency translation circuits associated with elements in corresponding M rows of the array, each row processing circuit imparting a delay in accordance with the corresponding row position;a summing circuit operatively coupled to each of the M row processing circuits and providing a row signal in response thereto;a column processing circuit, the column processing circuit receiving the row signal, partitioning the row signal into N column signals in accordance with said column intermediate frequencies, the column processing circuit imparting a delay on the N column signals and shifting the N column signals to a common frequency; anda second summing circuit receiving the N common frequency column signals and providing a received signal output signal representing the incident beam signal.