Patent ID: 6477672
Filing Date: 2002-11-05
Classification: G11C

Abstract:
A memory testing apparatus for testing a non-volatile memory that includes a plurality of memory blocks each including a plurality of memory cells in which stored data can be electrically erased in one or more of the blocks and rewritten, said memory testing apparatus comprising:a pattern generator; a failure analysis memory; and a first bad block memory having its storage areas the number of which corresponds to the number of blocks that a memory under test has;and wherein the memory-testing apparatus operates in an initial test mode in which a constant logical value is written in memory cells of each of all the blocks of the memory under test, the written logical value is read out, a decision is rendered whether a memory cell is defective according to whether the read-out logical value is in disaccord with the written logical value, failure data is written into the failure analysis memory for memory cells that are decided to be defective, each block having even one memory cell the read-out logical value from which is in disaccord with the written logical value is detected as a failure block, and bad block data representing said failure blocks are stored in a storage area of said first bad block memory corresponding to said failure blocks.