Patent ID: 8522081
Filing Date: 2013-08-27
Classification: G06F

Abstract:
1. A microcomputer, comprising: a CPU including a program counter which updates and stores an address of an instruction of a program to be executed next when an instruction of the program is executed, the CPU configured to execute instructions of the program of which addresses stored in the program counter in order; a program counter expected value register which stores an expected value of an address to be stored in the program counter; a first comparator which compares the address stored in the program counter with the expected value stored in the program counter expected value register; and a detection time counter which counts a detection time, wherein when the CPU executes a failure detection program, the CPU causes the program counter expected value register to store the expected value of the address which is stored in the program counter after the detection time passes from the start of execution of the failure detection program, and causes the detection time counter to start counting of the detection time, and wherein when the detection time counter finishes counting of the detection time, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.