Patent ID: 9224462
Filing Date: 2015-12-29
Classification: G11C

Abstract:
1. A resistive memory device comprising: a memory cell array including resistive memory cells connected to word lines and bit lines and arranged in memory blocks; a row selector connected to the word lines; a column selector connected to the bit lines; an address decoder configured to decode a row address and a column address of an input address, transfer the decoded row address to the row selector, and transfer the decoded column address to the column selector; a write driver and sense amplifier block connected to the bit lines via the column selector; and a control logic configured to control the row selector, the column selector, and the write driver and sense amplifier block during an erase operation to simultaneously erase resistive memory cells connected to at least one selected word line included in an erase unit, wherein the erase unit includes fewer word lines than are included in a memory block, wherein the control logic is further configured during the erase operation to control the row selector to apply a first voltage to the at least one selected word line while controlling the column selector to bias at least one bit line such that current flows via the resistive memory cells connected to the at least one selected word line, and wherein the control logic is further configured to control the column selector to apply a second voltage less than the first voltage to the at least one bit line.