Patent ID: 7769577
Filing Date: 2010-08-03
Classification: G06F

Abstract:
1. A hardware simulation system comprising: a hardware accelerator; a simulation model in the hardware accelerator; a single partition of latches logic and combinational logic in the simulation model, wherein the latches logic comprises latch memory elements and the combinational logic comprises combinational logic memory elements, wherein the combinational logic memory elements comprise transparent latches and write before read arrays; hardware to support a combinational logic only cycle of the simulation model, where the combinational only cycle prevents updates to the latch memory elements while running a simulation that processes both the latches and the combinational logic, wherein in the hardware to support the combinational logic only cycle comprises an array of function units with a special function selection circuit comprising a multiplexer that allows the latches to retain the pervious value for the combinational logic only cycle by selecting a special function and providing the special function to the function unit; and hardware to support a latch only cycle, where the latch only cycle prevents updates to the combinational logic memory elements while running the simulation that processes both latches and combinational logic.