Patent ID: 6438037
Filing Date: 2002-08-20
Classification: G11C

Abstract:
A method for compacting a threshold voltage distribution for a non-volatile semiconductor memory design having a plurality of memory cells each having a programmable threshold voltage, the method comprising the acts of:(a) erasing the plurality of memory cells wherein memory cells are set to have a threshold voltage not greater than a first erase-verify voltage, the memory cells collectively have a threshold voltage distribution centered substantially about a threshold voltage for a typical memory cell; (b) selectively soft-programming the plurality of memory cells wherein the threshold voltage for fast-erase memory cells having a threshold voltage not greater than a selected reference voltage are set to a threshold voltage not less than the selected reference voltage, the selected reference voltage less than the erase-verify voltage; and (c) subsequent to selectively soft-programming, erasing the plurality of memory cells wherein memory cells are set to have a threshold voltage not greater than a second erase-verify voltage.