Patent ID: 6396755
Filing Date: 2002-05-28
Classification: G11C

Abstract:
A memory configuration, comprising:an integrated memory having a memory cell array with memory cells, column lines, and row lines; said memory cells being connected to respective ones of said row lines for selecting one of said memory cells and being connected to respective ones of said column lines for one of reading and writing a data signal; a row access controller operatively connected to said memory cell array, said row access controller activating one of said row lines for selecting one of said memory cells, and said row access controller controlling a precharging operation for precharging one of said row lines; a control unit having a first input, a second input, a third input, and an output; a first terminal for providing a decoded precharge command initiating a triggering of a precharging operation of one of said row lines, said first terminal being connected said first input of said control unit; a second terminal for providing a signal indicating that one of a read operation and a write operation for a data signal has been finished, said second terminal being connected said second input of said control unit; a third terminal for providing a signal containing information about a time interval during which an activated one of said row lines is activated, said third terminal being connected to said third input of said control unit; and said output of said control unit being connected to said row access controller and outputting an output signal for triggering a precharging operation of one of said row lines.