Patent ID: 6635532
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method for fabricating a NOR flash memory device, the method comprising:forming adjacent isolation layers that define an active region therebetween within a semiconductor substrate; forming a floating gate pattern overlying the active region; sequentially forming an inter-gate dielectric film and a control gate film, overlying the floating gate pattern; sequentially patterning the control gate film, the inter-gate dielectric film, and the floating gate pattern, thereby forming a plurality of word lines extending across the active region, the word lines each having sidewalls; forming a photo resist pattern exposing the active region and the isolation layers along one sidewall of the word line; etching the exposed active region, using the photo resist pattern, the word lines, and the exposed isolation layers as an etch mask; removing the exposed isolation layers, using the photo resist pattern and the word lines as an etch mask, to form a common source line region; and removing the photo resist pattern; and implanting impurities in the common source line region, thereby forming a common source line made of an impurity diffusion layer.