Patent ID: 9106859
Filing Date: 2015-08-11
Classification: H04N

Abstract:
1. A solid-state image pickup device comprising: an imaging unit in which a plurality of pixels each including a photoelectric conversion element for converting a light signal to an electric signal are disposed in a matrix, and signals of pixels in a selected row are output via a plurality of vertical read lines disposed for columns while sequentially scanning the pixels row by row; and a plurality of converters provided in correspondence with the vertical read lines, wherein each of the converters has a retention node for retaining a signal of a pixel which is output via a corresponding vertical read line and converts the signal retained by the retention node to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages, wherein, in the first conversion stage, each of the converters determines a value of one or plural upper bits including the most significant bit of the digital value by comparing the voltage at the retention node with a reference voltage while changing the voltage at the retention node by a predetermined voltage step, wherein, in the i-th conversion stage (2≦i≦N−1), each of the converters determines a value of one or plural bits subsequent to the bit determined in the (i−1)th stage by comparing the voltage at the retention node with the reference voltage while changing the voltage at the retention node by a voltage step smaller than the voltage step in the (i−1)th conversion stage, and wherein, in the N-th conversion stage, each of the converters determines a value of bits subsequent to the bit determined in the (N−1)th conversion stage to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range obtained by adding an overrange to the range, wherein each of the converters includes: wherein a plurality of capacitive elements coupled to the retention node include first to M-th (M: integer of two or larger) capacitive elements corresponding to the (N−1) conversion stage,