Patent ID: 6421757
Filing Date: 2002-07-16
Classification: G11C

Abstract:
An apparatus for programming flash memory cells in a microcontroller-based electronic device, said apparatus comprising:a state machine for controlling, in response to a command from a microcontroller, a sequence of operations for programming a plurality of said flash memory cells; a high voltage charge pump for generating a high voltage signal to be applied to selected ones of said flash memory cells during programming; a high voltage regulator for regulating said high voltage signal to a lower amplitude voltage for use during verification of the programming of said flash memory cells; a decoder for selection of said flash memory cells to be programmed and verified; a decoder for providing parallel loading of said high voltage signal onto selected ones of said flash memory cells during erasing of said flash memory cells, and to verify erasing of said flash memory cells on a column by column basis within a flash memory; a dedicated clock for controlling timing operations associated with the programming of said flash memory; and a timer circuit for controlling a window of time for at least one of said sequence of operations, wherein said timer circuit further comprises: a program setup timer for controlling an amount of time required for said charge pump to generate said high voltage signal, said program setup timer responsive to a first input signal from said state machine such that a charge pump setup time period is timed, and further configured to provide a first output signal to said state machine to indicate that said charge pump high voltage signal has ramped up to a desired high voltage level; a program timer for controlling an amount of time said high voltage signal is applied to said flash memory cells during programming, said program timer responsive to a second input signal from said state machine such that a programming time period is timed, and further configured to provide a second output signal to said state machine to indicate that said programming of said flash memory cell is complete; and a program verify setup timer for controlling an amount of time for verifying a successful programming sequence for said flash memory cells, said program verify setup timer responsive to a third input signal from said state machine such that a verify setup time period is timed, and further configured to provide a third output signal to said state machine to indicate completion of said successful programming sequence for said flash memory cells, wherein said state machine reprograms only those of said flash memory cells not correctly programed after verification of all of said flash memory cells wherein said state machine controls a sequence for erasing said flash memory.