Patent ID: 6339823
Filing Date: 2002-01-15
Classification: G06F

Abstract:
In an MMX-type computer architecture having a dual MMX and FP register file configuration, a method of ensuring coherency between said MMX and FP register files during the execution of MMX and FP instructions, first registers comprising one register file, second registers comprising the other register file, said first registers having one-to-one correspondence with said second registers, said method comprising:indicating the occurrence of write operations to said first registers; detecting an instruction boundary event; and upon detecting an instruction boundary event: disabling write operations to those of said second registers whose corresponding first registers have not been indicated as having been written to; and for each register of said first registers: reading data out of said each register; and writing said data to a corresponding register of said second registers, whereby said corresponding register is write-enabled only if said each register has been indicated as having been written to.