Patent ID: 6314021
Filing Date: 2001-11-06
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order;a plurality of memory cell transistors arranged in a matrix, each having a source region and a drain region which are formed away from each other in a main surface of said semiconductor layer, a first gate electrode formed on a body region between said source region and said drain region with an insulating film interposed therebetween, and a second gate electrode formed on said first gate electrode with an insulating film interposed therebetween;an isolation insulating film formed between adjacent ones of said plurality of memory cell transistors in a row direction perpendicular to a direction in which said source region and said drain region of each of said plurality of memory cell transistors are aligned in said main surface of said semiconductor layer, having a bottom surface which does not reach said insulating layer; andan impurity introduction region formed between said source regions included in adjacent ones of said plurality of memory cell transistors in said row direction in said semiconductor layer, having the same conductivity type as said source region has.