Patent ID: 6289021
Filing Date: 2001-09-11
Classification: H04L

Abstract:
An interconnect apparatus, comprising:a plurality of nodes; anda plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include:a plurality of J+1 levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level L.sub.0 to a highest level L.sub.J, the interconnect structure receiving a plurality of multiple bit messages unsorted through a plurality of input ports and transmitting the multiple bit messages, an individual message M of the plurality of messages being self-routing and moving through nodes using wormhole routing in which only a portion of the multiple-bits of a message are in transit between two nodes, the multiple-bit message extending among multiple nodes, the individual message M moving in a plurality of ways including four ways which are sufficient for the message M to exit the interconnect structure through an output port designated by the message M, the four ways being:(1) the message M enters a node in the interconnect structure from a device external to the interconnect structure, the message M designating one or more designated output ports;(2) the message M moves through a node in the interconnect structure without buffering to a designated output port;(3) the message M moves through a node on a level L.sub.k of the interconnect structure without buffering to a different node on the same level L.sub.k ; and(4) the message M moves through a node on a level L.sub.k of the interconnect structure without buffering to a node on a level L.sub.i nearer in the hierarchy to the destination level L.sub.0 than the level L.sub.k.