Patent ID: 6512852
Filing Date: 2003-01-28
Classification: H04N

Abstract:
An apparatus for properly concatenating a plurality of words from a bitstream, comprising:a bit selector; a first register coupled to a first input of said bit selector and configured to hold a previous data word; a second register coupled to a second input of said bit selector and configured to hold a next data word; a third register configured to store start bit information and coupled to a third input of said bit selector; a fourth register configured to store remainder bit information; a storage unit coupled to an output of said bit selector and configured to store a decode table; a first subtractor coupled to an output of said storage unit and an output of said third register, and provides a start point for a further next data word, wherein said output of said storage unit provides length information; and a second subtractor coupled to an output of said storage unit and an output of said fourth register, and provides a remainder point for a further next data word, wherein said bit selector is capable of selecting at least one bit from each of said first and said second registers.