Patent ID: 6330296
Filing Date: 2001-12-11
Classification: H03L

Abstract:
A delay-locked loop, comprising:a phase frequency detector, the phase frequency detector including a state machine having a first input for receiving a reference signal and a second input for receiving a feedback signal, wherein the phase frequency detector resets the state machine in response to a rising edge of a lagging signal between the reference signal and the feedback signal;a charge pump coupled to the phase frequency detector;a loop filter coupled to the charge pump and the phase frequency detector;delay line means coupled to the charge pump and the loop filter, the delay line means providing the feedback signal to the phase frequency detector; andmonitor means coupled to the phase frequency detector, the charge pump and the loop filter, the monitor means for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the phase frequency detector to enter a pump-down mode until the feedback signal is aligned with the reference signal.