Patent ID: 8994117
Filing Date: 2015-03-31
Classification: H01L

Abstract:
1. A moat isolation structure on a semiconductor chip having a P− substrate and an N+ epitaxial grown layer covering the entire P− substrate, and a circuit layer above the N+ epitaxial grown layer, the moat isolation structure comprising: the circuit layer having patterned P− regions in which circuits are formed, the circuit layer further comprising shallow trench isolation (STI) areas to isolate the patterned P− regions, a first moat comprising a first N+ epitaxial region in the N+ epitaxial grown layer and a first patterned P− region over the first N+ epitaxial region, the first N+ epitaxial region electrically isolated from a second N+epitaxial region in the N+epitaxial grown layer by a first deep trench that extends through the circuit layer, the N+epitaxial grown layer, and extending into the P- substrate, the first deep trench further comprising a conductor at least partially surrounded by a dielectric, the first deep trench surrounding a perimeter of the first moat, the first N+ epitaxial region connected to a first supply voltage; a second moat comprising a third N+ epitaxial region in the N+ epitaxial grown layer and a second patterned P− region over the third N+ epitaxial region, the third N+ epitaxial region isolated from the second N+ epitaxial region in the N+epitaxial grown layer by a second deep trench that extends through the circuit layer, the N+ epitaxial grown layer, and extending into the P− substrate, the second deep trench further comprising a conductor at least partially surrounded by a dielectric, the second deep trench surrounding a perimeter of the second moat, the second moat surrounding the first moat except for a DC path in the second N+ epitaxial region extending from the first deep trench to an area outside of the second moat.