Patent ID: 8837219
Filing Date: 2014-09-16
Classification: G11C,H01L

Abstract:
1. A programming method for use in memory, each memory cell of a plurality of memory cells of the memory comprising a well having a first conductivity type, source and drain regions of a second conductivity type opposite the first conductivity type, a storage layer, and a gate, the plurality of memory cells being arranged in a matrix with drain regions in the same column electrically connected to the same bit line, gates in the same row electrically connected to the same word line, and source regions in the same column connected to the same source line, the method comprising: applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells; applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell; applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell; and applying a substrate voltage to the plurality of memory cells.