Patent ID: 9158412
Filing Date: 2015-10-13
Classification: G06F,G09G

Abstract:
1. A display device comprising: a pixel portion comprising a first region and a second region; a first gate driver; a second gate driver; a first source driver; and a second source driver, wherein the first region comprises a first pixel, the first pixel comprising: wherein the second region comprises a second pixel, the second pixel comprising: wherein the first source driver and the second source driver are configured to concurrently perform reading operation on the first pixel and the second pixel, respectively, wherein the first gate driver is electrically connected to a gate of the first transistor and a gate of the fifth transistor, wherein the second gate driver is electrically connected to a gate of the fourth transistor and a gate of the eighth transistor, wherein the first source driver is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor, wherein the second source driver is electrically connected to one of a source and a drain of the fifth transistor and one of a source and a drain of the eighth transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor element and the first display element, wherein the other of the source and the drain of the fifth transistor is electrically connected to the second capacitor element and the second display element, wherein the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein a gate of the third transistor is electrically connected to a first end the first photoelectric conversion element and a second end of the first photoelectric conversion element is electrically connected to a ground, wherein a gate of the seventh transistor is electrically connected to a first end the second photoelectric conversion element and a second end of the second photoelectric conversion element is electrically connected to the ground, wherein one of a source and a drain of the second transistor is electrically connected to the first end of the first photoelectric conversion element and a gate of the second transistor is electrically connected to a control line, wherein one of a source and a drain of the sixth transistor is electrically connected to the first end of the second photoelectric conversion element and a gate of the sixth transistor is electrically connected to the control line, wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line, wherein the other of the source and the drain of the third transistor is electrically connected to the power supply line, wherein the other of the source and the drain of the sixth transistor is electrically connected to the power supply line, and wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line.