Patent ID: 7213087
Filing Date: 2007-05-01
Classification: H04L

Abstract:
1. A multi-processor computer system, comprising: a plurality of processors, each processor coupled to at least one memory cache, one cache control unit, and one interprocessor router; and a memory coupled to each processor, each memory managed by a memory controller configured to accept memory requests from the plurality of processors; wherein the memory requests from a local processor are delivered to the memory controller by the cache control unit and wherein memory requests from other processors are delivered to the memory controller by the interprocessor router and wherein the memory controller allocates the memory requests from the plurality of processors in a shared buffer using a credit-based allocation scheme in which the memory controller automatically returns a credit if a number of filled spaces in the shared buffer is below a threshold, and returns credits in a round-robin manner if a number of filled spaces in the shared buffer exceeds the threshold, wherein a number of credits assigned to the interprocessor router and the cache control unit is based, at least in part, on round-trip times required to transmit credits between the interprocessor router and the buffer and between the cache control unit and the buffer.