Patent ID: 6871343
Filing Date: 2005-03-22
Classification: G06F

Abstract:
1. A central processing apparatus for assigning instructions of a program to a plurality of buffers each connected to one of a plurality of execution units, the plurality of execution units each executing the instructions by accessing a memory and a global register, wherein the program comprises a plurality of instruction sequences, each instruction sequence comprises a plurality of instructions not executable in parallel because of data dependency, wherein an instruction sequence speculatively executable is located before an instruction sequence not speculatively executable, the plurality of instruction sequences are aligned in correspondence with each of the plurality of buffers, a task number representing the instruction sequence and a corresponding buffer is assigned to each instruction, a condition instruction is replaced by a commit instruction, the commit instruction includes a condition, task numbers to be accepted if the condition is not satisfied and task numbers to be rejected if the condition is satisfied, the central processing apparatus, comprising: a task window number generator configured to assign a task window number to a plurality of instruction sequences in a task window, the commit instruction being at the end of the task window; an assignment unit configured to assign each instruction of aligned instruction sequences to each of the plurality of buffers by referring to the task number; a register update unit configured to update data in a register number accessed by a particular instruction sequence in a task window if the particular instruction sequence is accepted by the commit instruction in the task window; and a memory update unit configured to update data in a memory address accessed by a particular instruction sequence in a task window if the particular instruction sequence is accepted by the commit instruction in the task window.