Patent ID: 8726060
Filing Date: 2014-05-13
Classification: G06F,H03K

Abstract:
1. A semiconductor integrated circuit for transmitting and receiving a plurality of data signals in a source-synchronous scheme using an internal bus, comprising: a memory interface block; at least one read data adjustment circuit; at least one functional block; at least one write data adjustment circuit; and at least one selector circuit, wherein read data is transmitted from the memory interface block to the read data adjustment circuit serially connected thereto, and is transferred from each of the read data adjustment circuits to the corresponding functional block, write data is transferred from the plurality of functional blocks to the write data adjustment circuit, and is transmitted from the write data adjustment circuit serially connected thereto to the memory interface block, and the selector circuit selects either a clock signal from the functional block or a clock signal arranged side by side with a data signal from the write data adjustment circuit, the selected clock signal being output to the memory interface block or the write data adjustment circuit in a succeeding stage.