Patent ID: 8275267
Filing Date: 2012-09-25
Classification: H04B

Abstract:
1. An apparatus, comprising: a first switch configured to receive first and second groups of bits; a second switch configured to receive third and fourth groups of bits; a first Fourier transform circuit, the first switch being configured to selectively supply the first group of bits to the first Fourier transform circuit, the first Fourier transform circuit being configured to generate first frequency domain data in response to the first groups of bits; a second Fourier transform circuit, the second switch being configured to selectively supply the third group of bits to the second Fourier transform circuit, the second Fourier transform circuit being configured to generate second frequency domain data in response to the third groups of bits; a first Hermetian transpose circuit configured to generate a first conjugate of the first frequency domain data, the first conjugate of the first frequency domain data constituting first conjugate data; a second Hermetian transpose circuit configured to generate a second conjugate of the second frequency domain data, the second conjugate of the second frequency domain data constituting second conjugate data; and a filter circuit configured to receive the first and second conjugate data.