Patent ID: 6876087
Filing Date: 2005-04-05
Classification: H01L

Abstract:
1. A structure of a chip scale package (CSP) on a printed circuit board, comprising: a chip, having a chip thickness and a plurality of exposed bonding pads; a leadframe, including a heat dissipating part and a plurality of leads that radiate from the heat dissipating part, each of the leads extending from an inner lead portion having a first thickness proximate to the heat dissipating part and an outer lead portion having a second thickness greater than the first thickness, wherein a difference of the first thickness and the second thickness is slightly greater than the chip thickness; an adhesive layer, used to adhere the chip to the heat dissipating part; a first connecting material layer, used to allow the bonding pads to electrically connect to the inner lead portion when the chip is adhered to the heat dissipating part; an encapsulant, encapsulating the chip in the leadframe, wherein the dissipating part has an exposed surface opposite to the chip, wherein the exposed surface of the heat dissipating part and a surface of the loads have the same level, wherein a surface of the chip opposite to the heat dissipating part is exposed and is substantially at a same surface level with the outer lead portion; and a circuit board; and a second connecting material layer, located on the outer lead with the second thickness, used to allow the outer lead portion to be electrically contact with the circuit board, wherein the heat dissipating part remained exposed.