Patent ID: 6682976
Filing Date: 2004-01-27
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory device comprising:forming an isolation layer over a semiconductor substrate having a stacked gate region and a diffusion region, the isolation layer formed adjacent the diffusion region of the semiconductor substrate; forming a gate oxide layer over the stacked gate region; forming a first conductive layer over the isolation layer, the gate oxide layer and the diffusion region; forming a nitride layer over the first conductive layer, the nitride layer having an opening at the isolation layer; forming an oxide region in the first conductive layer using the nitride layer as a mask; removing the nitride layer and the oxide region; forming an interelectrode dielectric layer over the first conductive layer; forming a second conductive layer over the interelectrode dielectric layer; removing the second conductive layer over the diffusion region; removing the interelectrode dielectric layer over the diffusion region; removing the first conductive layer over the diffusion region; and forming a diffusion layer in the semiconductor substrate of the diffusion region.