Patent ID: 8026135
Filing Date: 2011-09-27
Classification: H01L

Abstract:
1. A process of forming an integrated circuit (IC) containing a metal oxide semiconductor (MOS) transistor further containing lightly doped drain (LDD) diffused regions, comprising the steps of: forming an LDD source dielectric layer on a top surface of a well and an MOS gate formed on a top surface of an MOS gate dielectric layer formed on said top surface of said well; forming an LDD implanted region in a top region of said LDD source dielectric layer by a process of implanting an LDD set of dopant atoms into said LDD source dielectric layer such that less than 10 percent of said LDD dopant atoms pass through said LDD source dielectric layer into said well; and forming said LDD diffused regions by a process of heating said IC such that a portion of said LDD dopant atoms diffuse from said LDD implanted region into top regions of said well adjacent to said MOS gate.