Patent ID: 8181132
Filing Date: 2012-05-15
Classification: G06F

Abstract:
1. A method comprising: simulating by one or more computer systems a larger circuit, as compared to one or more reduced circuits, to assign one or more values to one or more latch variables associated with the larger circuit; generating by the one or more computer systems the one or more reduced circuits from the larger circuit according to the one or more values assigned to the one or more latch variables; generating by the one or more computer systems a transition relation (TR) for each reduced circuit; and generating by the one or more computer systems an initial state set for one or more instances of validation on the one or more reduced circuits according to the TRs, wherein: simulating by the one or more computer systems the larger circuit comprises: generating by the one or more computer systems the one or more reduced circuits comprises: generating by the one or more computer systems the initial states for the one or more instances of validation on the one or more reduced circuits comprises: