Patent ID: 6316801
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate having an active region having a diffusion region;a multilevel interconnection structure on said semiconductor substrate, said multilevel interconnection structure comprising at least first level and second level interconnections isolated from each other by an inter-layer insulator and electrically connected to each other through a via plug in a via hole formed in said inter-layer insulator, said first level interconnection being electrically connected to said diffusion region through a first contact plug, said first contact plug being in a first contact hole formed in a further inter-layer insulator isolating said first level interconnection from said diffusion region; anda capacitive element comprising a bottom electrode that is isolated from said multilevel interconnection structure by a yet further inter-layer insulator,said bottom electrode being electrically connected to said second level interconnection by a second contact plug in a second contact hole through the yet further inter-layer insulator.