Patent ID: 6154385
Filing Date: 2000-11-28
Classification: G11C

Abstract:
A semiconductor memory comprising:(a) a plurality of sub-arrays each of which includes a plurality of cells arranged in a matrix;(b) at least one word line connected to gates of cells arranged in a first direction among said cells;(c) at least one bit line for providing a data-writing signal to one of electrodes of cells arranged in a second direction among said cells, said second direction being perpendicular to said first direction;(d) at least one ground line for reading data out of the other of said electrodes of cells arranged in said second direction;(e) a plurality of sense-amplifiers associated with each of said sub-arrays for providing a sense-amplifying current to said bit line;(f) a plurality of row buffers connected to all of said sub-arrays for retaining data of a cell selected by said word line;wherein each of said sense-amplifiers is comprised of first and second sense-amplifiers positioned at opposite sides of each of said sub-arrays;wherein said row buffers are comprised of first row buffers for retaining data written into said sub-arrays through said first sense-amplifiers and data input thereinto from said sub-arrays through said first sense-amplifiers and second row buffers for retaining data written into said sub-arrays through said second sense-amplifiers and data input thereinto from said sub-arrays through said second sense-amplifiers; anddata transmission through said first and second row buffers being carried out in a time-sharing manner.