Patent ID: 9224655
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method, comprising: forming a sacrificial sidewall spacer adjacent to a gate structure of each of a P-type transistor and an N-type transistor, wherein a material of said sacrificial sidewall spacer has an etch selectivity relative to a material of a gate cap layer formed above said gate structure of each of said P-type and N-type transistors; forming a masking layer that covers said P-type transistor and exposes at least said gate cap layer of said N-type transistor; performing a first etching process through said masking layer to selectively remove a portion of said gate cap of said N-type transistor relative to said sacrificial sidewall spacer of said N-type transistor so as to thereby define a reduced thickness gate cap layer for said N-type transistor; removing said masking layer; performing a common second etching process on said P-type transistor and said N type transistor to selectively remove said gate cap layer of said P-type transistor and the reduced thickness gate cap layer of said N-type transistor relative to said sacrificial sidewall spacer of said respective P-type and N-type transistors.