Patent ID: 7486562
Filing Date: 2009-02-03
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array including a bit line connected to memory cells operative to store first logic data and second logic data smaller in cell current than said first logic data; and a sense amp circuit connected to said bit line to detect data in said memory cell, wherein said sense amp circuit includes a sense node connected via a first switching element to a current source load, a sense PMOS transistor having a gate connected to said sense node and a source connected via a second switching element to a power source terminal, a data latch connected to a drain of said sense PMOS transistor, a clamp NMOS transistor connected between said current source load and said bit line via a current limit NMOS transistor to clamp a bit line voltage and amplify said bit line voltage to transmit it to said sense node, and a third switching element serially connected to said current source load and on/off-controlled in response to data held in said data latch, wherein data is read from a selected memory cell in at least two read cycles with different control voltages applied to a gate of said clamp NMOS transistor.