Patent ID: 8558598
Filing Date: 2013-10-15
Classification: H03K,H05B

Abstract:
1. A phase shift generating circuit for receiving a pulse width modulated pulse train signal having a first frequency and a first clock signal having a second frequency with the second frequency greater than the first frequency, said circuit comprising: an edge detection circuit for receiving the pulse train signal and the first clock signal and for outputting a leading edge signal in response to the leading edge of the pulse train signal, and a trailing edge signal in response to the trailing edge of the pulse train signal; a circuit for receiving a signal representing an integer N and the first clock signal and for generating a second clock signal having a second frequency, wherein said second frequency is the first frequency divided by the integer N; a pulse counter for receiving the leading edge signal or the trailing edge signal and the second clock signal to store a digital number corresponding to a period of the pulse train signal; a first timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of set signals with each set signal generated from each pulse of the first clock signal and provided on a different set output line; a second timer circuit for receiving the first clock signal and the digital number and for outputting a plurality of reset signals with each reset signal generated from each pulse of the first clock signal and provided on a different reset output line; N storages, each storage having a set input for receiving one of said plurality of set signals and a reset input for receiving one of said plurality of reset signals, and an output; a first latch for storing the digital number corresponding to a period of the pulse train signal from the pulse counter, and having a first output, supplied to the first timer circuit, with said first latch triggered by said trailing edge signal; and a second latch for storing the digital number corresponding to a period of the pulse train signal from the first latch, and having a second output, supplied to the second timer circuit, with said second latch triggered by said leading edge signal; wherein the output of said N storages is N output signals with each output signal having a time phase delay with the commencement of the plurality of output signals distributed over a period of the pulse train signal.