Patent ID: 6495442
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A method of forming a post passivation interconnection, comprising:forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming one or more ESD circuits formed in and on said semiconductor substrate; a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin.