Patent ID: 6097095
Filing Date: 2000-08-01
Classification: H01L

Abstract:
An integrated circuit structure which comprises:(a) a substrate;(b) a layer of a second dielectric material positioned on the substrate;(c) a plurality of spaced apart metal contacts on the layer of the second dielectric material, which metal contacts have side walls;(d) a space between adjacent metal contact side walls, each space being filled with the second dielectric material;(e) at least one ledge of a first dielectric material on top of at least one second dielectric material filled space and which ledge is attached to adjacent side walls such that each ledge eitheri) fully spans the width of the filled space between adjacent side walls; orii) partially spans the width of the filled space between adjacent side walls, and the area between adjacent ledges is filled with second dielectric material;a top surface of each of the metal contacts, a top surface of the ledges and a top surface of any filled areas between adjacent ledges being at a common level;(f) an additional layer of the second dielectric material on at least some of the metal contacts, at least one of the ledges and optionally the filled areas between adjacent ledges;(g) at least one via extending through the additional layer of the second dielectric material and extending to the top surface of at least one metal contact and optionally at least one of the ledges;wherein the first dielectric material and the second dielectric material have substantially different etch resistance properties.