Patent ID: 9208851
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A Dynamic Random Access Memory (DRAM) device having a hierarchical bit line architecture, the DRAM device comprising: a plurality of main word lines extending in a first direction, each of the main word lines connected to the output of a respective main word line driver of a plurality of main word line drivers; a plurality of main switch control lines extending in the first direction, each of the main switch control lines connected to the output of a respective main switch driver of a plurality of main switch drivers; a plurality of global bit lines extending in a second direction orthogonal to the first direction, each of the global bit lines connected to a sense amplifier; a plurality of sub-word lines corresponding to each of the main word lines extending in the first direction, each of the sub-word lines connected to the output of a corresponding sub-word driver having an input connected to a corresponding main word line; a plurality of local switch control lines corresponding to each of the main switch control lines extending in the first direction, each of the local switch control lines connected to the output of a corresponding local switch driver having an input connected to a corresponding main switch control line; and a plurality of local bit lines corresponding to each of the global bit lines extending in the second direction, each of the local bit lines selectively connected to a corresponding global bit line through a corresponding hierarchical switch controlled by a corresponding local switch control line, and wherein the main word line drivers and the main switch drivers each have a multi-stage inverter output portion and an input portion, and the output portions of the main word line drivers and the main switch drivers are substantially identical circuits.