Patent ID: 8399963
Filing Date: 2013-03-19
Classification: H01L

Abstract:
1. A chip package, comprising: a semiconductor substrate having at least a contact pad region, at least a device region, and a remained scribe region located at a periphery of the semiconductor substrate; a signal contact pad structure and an EMI ground pad structure disposed on the contact pad region; a first opening and a second opening penetrating into the semiconductor substrate to expose the signal contact pad structure and the EMI ground pad structure, respectively; a first conducting layer and a second conducting layer located in the first opening and the second opening and electrically connected to the signal contact pad structure and the EMI ground pad structure, respectively, wherein the first conducting layer and the signal contact pad structure are separated from a periphery of the remained scribe region by an interval, and wherein a portion of the second conducting layer and/or a portion of the EMI ground pad structure extend(s) to the periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect to the second conducting layer and/or the EMI ground pad structure.