Patent ID: 6261903
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method for forming an integrated circuit device, said integrated circuit comprising a flash memory cell, said method comprising:forming a tunnel dielectric layer overlying a surface of a semiconductor substrate;forming a floating gate layer overlying the tunnel dielectric layer, the gate layer having an edge defined thereon;forming a sidewall spacer extending along and on the edge and extending beyond the edge, the sidewall spacer comprising a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge, said sidewall spacer having an outer surface opposite said edge, wherein the sidewall spacer is made of substantially the same material as the floating gate layer;forming a dielectric layer over said sidewall spacer and over said floating gate; andforming a control gate layer over said dielectric layer, but not over said outer surface.