Patent ID: 8143156
Filing Date: 2012-03-27
Classification: H01L

Abstract:
1. A method of forming an integrated semiconductor device, comprising the steps of: (a) defining a plurality of strips of a first material on a layer formed on a substrate, the plurality of strips including sidewalls substantially orthogonal to the layer formed on the substrate; (b) depositing a second material on each pair of sidewalls of the plurality of sidewalls; (c) etching the second material to define a first set of spacers on sidewalls of the plurality of strips, gaps being defined between spacers of adjacent strips of the plurality of strips; (d) depositing a third material over the plurality of strips and first set of spacers, and in the gaps between spacers; (e) polishing down the third material, the strips and the first set of spacers to define a planar surface; (f) etching the plurality of strips and third material in the gaps to expose sidewalls on the first set of spacers, the sidewalls of the first set of spacers being substantially orthogonal to the layer formed on the substrate; (g) depositing a fourth material on the sidewalls of the first set of spacers; (h) etching the fourth material to define a second set of spacers on the sidewalls of the first set of spacers; and (i) etching the first set of spacers to leave the second set of spacers, the second set of spacers forming a mask for defining elements in a layer beneath the second set of spacers.