Patent ID: 7475295
Filing Date: 2009-01-06
Classification: G06F

Abstract:
1. A watchdog component affiliated with a host system that has a processor and a timer mechanism generating periodic clock outputs, the watchdog component comprising: an N-bit counter that is capable of counting up to a maximum value and counting down to a minimum value, said N-bit counter having a bit that is a most significant bit (MSB); a first output signal bus transmitting a first output signal for triggering a reset of a host system; a second output signal bus transmitting a second output signal for signaling a value of the MSB to the host system; a first input signal bus transmitting a first input signal that indicates whether the counter is to count up or down, said first input signal representing the received input and being generated based on the value of the MSB; a microprocessor with processing logic having code executing thereon for performing the function of directing a count of the watchdog component away from a closest end point of the counter values towards the opposite end point of counter values, wherein a first end point is a maximum counter value and a second, opposing end point is a minimum counter value, whereby generation of false keep-alive pulses while the system is in a hung state are substantially eliminated, said code executing on the processing logic to provide: