Patent ID: 7509440
Filing Date: 2009-03-24
Classification: G05B,Y02P

Abstract:
1. A programmable controller comprising a CPU unit, a communication unit and peripheral units connected together through an internal bus; wherein said communication unit has a bus master function of obtaining an access right to said internal bus and releasing said access right; said communication unit has a cache memory for recording IO data stored in said peripheral units, said cache memory being divided into partitions corresponding to said peripheral units, update check and IO refresh of said cache memory being executed in units of said divided partitions; and said communication unit comprises update judging means for judging, when a message is received thereby, whether IO data stored in the peripheral unit specified by said message are updated or not, and responding means for creating response data based on the IO data stored in said peripheral unit stored in said cache memory, if said IO data are not updated, and accessing said peripheral unit by obtaining the access right to said internal bus, if said IO data are updated, to obtain said updated IO data and to create response data based on said obtained IO data.