Patent ID: 7723775
Filing Date: 2010-05-25
Classification: H01L

Abstract:
1. A NAND flash memory device, comprising: a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity; a plurality of word lines extending in a second direction on the first well, the second direction being perpendicular to the first direction, intersection regions of the active regions and the word lines defining memory cells; first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other by a predetermined distance along the first direction to define an intermediate region between the first and second dummy word lines, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V; and at least one contact in at least one of the plurality of active region, the at least one contact being positioned in the intermediate region between the first and second dummy word lines and being adapted to apply a well bias voltage to the first well.