Patent ID: 6707653
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A circuit for protecting a semiconductor integrated circuit coupled to a first node, comprising:a semiconductor substrate of a second conductivity type which is opposite a first conductivity type; a well region of the first conductivity type formed in the semiconductor substrate; a first region of the second conductivity type formed in the well region and directly electrically coupled to the first node; a second region of the first conductivity type formed at a boundary between the well region and the semiconductor substrate so as to overlap both the well region and the semiconductor substrate, wherein the second region is directly electrically coupled to the first node; a third region of the first conductivity type formed in the semiconductor substrate spaced from and adjacent to the second region outside the well region; a gate electrode formed over the semiconductor substrate between the second region and the third region, wherein the gate electrode is electrically connected to a second node; a fourth region of the second conductivity type formed in the semiconductor substrate spaced from the well region on an opposite side of the well region from the second region, wherein the fourth region is electrically connected to the second node; a fifth region of the first conductivity type which is electrically connected to the second node and which is formed in the semiconductor substrate spaced from and between the well region and the fourth region; and a sixth region of the second conductivity type which is electrically connected to the third region and which is formed in the semiconductor substrate spaced from and between the fifth region and the well region; wherein a dopant concentration of the first, fourth and sixth regions is greater than that of semiconductor substrate, and a dopant concentration of the second, third and fifth regions is greater than that of the well region.