Patent ID: 6351425
Filing Date: 2002-02-26
Classification: G11C

Abstract:
An antifuse circuit formed on a semiconductor substrate in which a plurality of semiconductor devices are fabricated, the antifuse circuit comprising:an antifuse formed on the substrate; a bias circuit formed on the substrate, the bias circuit being structured respond to an activation signal to selectively apply a voltage having a first polarity to a first terminal of the antifuse; an output circuit formed on the substrate, the output circuit structured to couple to an output terminal a voltage indicative of a voltage on the first terminal of the antifuse when the voltage having a first polarity is being applied to the first terminal of the antifuse; a conductive programming path formed on the substrate, the conductive programming path extending from the second terminal of the antifuse to a conductive programming pad and being isolated from the substrate and from all of the semiconductor devices, the conductive programming path being structured to couple a programming voltage having a second polarity different from the first polarity from the programming pad to the second terminal of the antifuse.