Patent ID: 6563177
Filing Date: 2003-05-13
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor memory device including first and second access transistors, first and second drive transistors, and first and second load resistors, a first cell node having a first terminal of the first access transistor, a gate electrode of the second drive transistor and a terminal of the first load resistor connected thereto in common, and a second cell node having a first terminal of the second access transistor, a gate electrode of the first drive transistor and a terminal of the second load resistor connected thereto in common, the semiconductor memory device comprising:a trench formed in a semiconductor substrate and having at least two walls including a first wall and a second wall; and the first drive transistor including a source region and a drain region formed at a depth on the first wall and the second drive transistor including a source region and a drain region formed at a depth on the second wall of the trench, and the gate electrode of the first drive transistor formed on the first wall and the gate electrode of the second drive transistor formed on the second wall of the trench.