Patent ID: 9036330
Filing Date: 2015-05-19
Classification: H01G,H05K,Y10T

Abstract:
1. A method for fabricating a multilayer chip capacitor assembly, the method comprising: providing the multilayer chip capacitor; selecting a first portion of the first outer electrodes to be directly connected to a power source among the first outer electrodes of the multilayer chip capacitor and excluding a second portion of the first outer electrodes from being directly connected to the power source, in order to obtain a desired equivalent series resistance (ESR); selecting a portion of second outer electrodes to be connected to a power source among the second outer electrodes of the multilayer chip capacitor in order to obtain the desired ESR; and mounting the multilayer chip capacitor on a printed circuit board (PCB) such that only the selected first and second outer electrodes are connected with power source lines provided on the PCB, wherein: the multilayer chip capacitor comprises: the plurality of first and second inner electrodes are connected to two of the first and second outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on locations of the outer electrodes connected to the first and second inner electrodes, and at least one of two outer electrodes connected to inner electrodes of each group is different from an outer electrode connected to inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected to at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.