Patent ID: 8362570
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method for making complementary p and n MOSFET transistors, with metal Schottky source and drain electrodes arranged on a semiconductor substrate, the source and drain electrodes of each transistor being connected by a channel controlled by a gate electrode, the method comprising: selecting the substrate from the group consisting of: solid silicon, silicon on insulator, and silicon on nothing; making the source and drain electrodes from a single silicide for both the p and n transistors, arranged on the semiconductor substrate; segregating first impurities from groups II and III of the periodic table, at the interface between the silicide and the channel of the p transistor, to make source and drain electrodes of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, to make source and drain electrodes of the n transistor, the complementary p transistor being masked, wherein the segregation of the first and second impurities is performed by an implantation to silicide, and the first and second impurities are segregated at the interface between the silicide and the channel through an activation by annealing at a temperature below 700° C.