Patent ID: 9147700
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A manufacturing method of an array substrate, comprising: providing a substrate; forming a first conducive layer on the substrate; performing a first photolithography process on the first conductive layer to form a gate electrode, a transparent conductive layer, a pad electrode, and a pixel electrode on the substrate; a first patterned photoresist is formed on the first conductive layer; wherein the first photolithography process comprises removing the first conductive layer and the transparent conductive layer uncovered by the first patterned photoresist, for forming the gate electrode, the pad electrode and the pixel electrode and at least partially exposing the pad electrode; forming a gate insulating layer to cover the substrate and the gate electrode; performing a second photolithography process to form a patterned semiconductor layer, a patterned etching stop layer, and a patterned hard mask layer, on the gate insulating layer, wherein the second photolithography process comprises: forming a semiconductor layer, an etching stop layer, a hard mask layer, on the gate insulating layer successively, and forming a second patterned photoresist on the etching stop layer; removing the etching stop layer uncovered by the second patterned photoresist; and removing the second patterned photoresist from the pixel electrode; removing the semiconductor layer uncovered by the second patterned photoresist for forming the patterned semiconductor layer on the gate insulating layer; and etching the second patterned photoresist and the etching stop layer for forming the patterned etching stop layer on the patterned semiconductor layer; and performing a third photolithography process to form a second conductive layer to cover the patterned hard mask layer, a portion of the first conductive layer, and forming an isolation layer on the second conductive layer; wherein the third photolithographic process comprises removing the second conductive layer uncovered by the isolation layer by an etching process to form a source and a drain electrode; wherein the first conductive layer on the pixel electrode is etched simultaneously in the step of etching the second conductive layer so as to at least partially expose the pixel electrode.