Patent ID: 6087821
Filing Date: 2000-07-11
Classification: G05F

Abstract:
A reference-voltage generating circuit, comprising:a depletion-type n-channel MOS transistor, the gate of said depletion-type n-channel MOS transistor being connected to its source and the bias of said depletion-type n-channel MOS transistor being set to such a condition that said depletion-type n-channel MOS transistor operates in the saturation region so as to act as a constant-current source and generate a first constant current;a first enhancement-type p-channel MOS transistor, the gate and drain of said first enhancement-type p-channel MOS transistor being connected to one another, said first enhancement-type p-channel MOS transistor being connected between a power-supply line and said depletion-type n-channel MOS transistor;a second enhancement-type p-channel MOS transistor, connected to said power-supply line to which said first enhancement-type p-channel MOS transistor is also connected, constituting a current-mirror circuit together with said first enhancement-type p-channel MOS transistor and mirroring said first constant current;a first enhancement-type n-channel MOS transistor, connected between the drain of said second enhancement-type p-channel MOS transistor and ground;a first resistance element, connected between the gate of said first enhancement-type n-channel MOS transistor and the ground;a second enhancement-type n-channel MOS transistor, constituting a source-follower circuit together with said first resistance element, and controlling generation of a second constant current in said first resistance element in accordance with activation of said first enhancement-type n-channel MOS transistor;a first reference-voltage output terminal, connected to the connection point between said first resistance element and the source of said second enhancement-type n-channel MOS transistor, for outputting a first reference voltage;a second resistance element, connected between said power-supply line and the drain of said second enhancement-type n-channel MOS transistor; anda second reference-voltage output terminal, connected to the connection point between said second resistance element and the drain of said second enhancement-type n-channel MOS transistor, for outputting a second reference voltage.