Patent ID: 8631208
Filing Date: 2014-01-14
Classification: G06F

Abstract:
1. A method comprising: receiving a memory request from a peripheral device corresponding to an intellectual property (IP) block of a system on a chip (SoC) coupled to a downstream side of an input/output (IO) interconnect of the SoC coupled between the IP block and a coherent interconnect of the SoC; accessing a first buffer of the IO interconnect to determine if an entry corresponding to an address of the memory request is present therein, the first buffer including a plurality of entries each to store a coherency indicator to indicate whether data associated with the memory request is to be handled in a coherent or non-coherent manner; and if so, obtaining a coherency indicator from the entry and sending the memory request and the coherency indicator to the coherent interconnect coupled to an upstream side of the IO interconnect, wherein the memory request received from the IP block does not include an indication of whether the memory request is to be handled in the coherent or non-coherent manner.