Patent ID: 6177842
Filing Date: 2001-01-23
Classification: H03L,Y10S

Abstract:
A phase lock detection circuit, comprising:a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto, said phase detection circuit comprising:a first delay circuit configured to receive the first input signal and operative to produce a delayed first input signal therefrom;a logic gate electrically coupled to said first delay circuit and operative to produce a window signal at an output thereof, the window signal representing a logic ANDing of the first input signal and the delayed first input signal;a second delay circuit configured to receive the second input signal and operative to produce a delayed second input signal therefrom; anda flip-flop circuit, electrically coupled to said logic gate and to said second delay circuit, said flip-flop circuit receiving the window signal at a data input thereof and receiving the delayed second input signal at a clock input thereof and producing a phase detect signal therefrom that has a logic state corresponding to the logic state of the window signal at a transition of the delayed second input signal; anda stabilized phase lock indication circuit, electrically coupled to said phase detection circuit, that produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval.