Patent ID: 7064032
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method for fanning at least one non-volatile memory cell, comprising: (a) forming a first oxide layer, an electron trapping layer, a second oxide layer, a first electrically conductive layer, and a dielectric layer on a surface of a substrate in that order; (b) patterning the dielectric layer and the first electrically conductive layer, thereby forming at least one component stack; (c) depositing a third oxide layer over and beside the at least one component stack; (d) removing a portion of an upper section of the third oxide layer opposite the second oxide layer such that an upper portion of the dielectric layer is exposed through the third oxide layer; (e) removing the dielectric layer and a remaining portion of the upper section of the third oxide layer such that an elevation of an upper surface of the third oxide layer above the surface of the substrate is substantially equal to an elevation of an upper surface of the patterned first electrically conductive layer; and (f) forming a second electrically conductive layer over upper surfaces of the patterned first electrically conductive layer and the third oxide layer.