Patent ID: 9023698
Filing Date: 2015-05-05
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor structure, comprising: forming a pFET stack and an nFET stack on a substrate; forming first source/drain regions at the substrate adjacent respective opposing sides of the pFET stack; growing a first layer of material at the first source/drain regions associated with the pFET stack, wherein after the growing, the first layer of material has a lattice structure that matches a lattice structure of a first underlying portion of the substrate to create a compressive state within a pFET channel; forming second source/drain regions at the substrate adjacent respective opposing sides of the nFET stack, wherein forming the first and second source/drain regions comprises: growing a second layer of material at the second source/drain regions associated with the nFET stack, wherein after the growing, the second layer of material has a lattice structure that matches a lattice structure of a second underlying portion of the substrate to create a tensile state within an nFET channel.