Patent ID: 6732224
Filing Date: 2004-05-04
Classification: G09G,G11C,H04B

Abstract:
A system for transferring streams of data comprising:A. A memory device including: i. a random access memory array storing a word of data at each of plural addressable locations; ii. a data port having a number of data terminals conducting the streams of data, the data terminals being coupled to data buffers so that the streams of data occur asynchronously with the operation of the memory array and the data buffers coupling the data to the memory array; and iii. an address port having a number of address terminals less than the number of data terminals, the number of address terminals coupling to an address sequencer receiving address control data including an initial random access address and the address sequencer coupling a series of addresses to the memory array starting with the initial random access address for transferring data to and from the memory array, the address port including a control data buffer coupled to the number of address terminals and coupled to the address sequencer, the control data buffer receiving address control data signals from the number of address terminals for controlling the addresses produced from the address sequencer; B. a processor supplying the address control data to the memory device; and C. a number of conductors equal to the number of address terminals coupling the address control data from the processor to the memory device and connecting to the address terminals.