Patent ID: 8572544
Filing Date: 2013-10-29
Classification: G06F

Abstract:
1. A method to manage power in a custom integrated circuit (IC) design with a code profile, comprising: a. receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; wherein the instruction contain instruction scheduler to made aware of power usage through the data model and see the true cost of scheduling instruction execution to get high performance with minimal hot spots on the chip; wherein the instruction scheduler is power aware in that the instruction scheduler use predicted hot spot information and map this information to virtual resource constraints so that standard off-the-shelf instruction scheduler can become power aware; wherein a data model associates an instruction's steady state probability of execution to a topology of an execution path b. creating from the data model sub-regions of a layout and for each sub-region determining a collection of intersecting execution paths yielding one or more execution path probabilities to determine a sub-region weight; c. applying sub-region weight distributions to estimate power hot-spot locations; and d. synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.