Patent ID: 7064375
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a first memory cell having a first gate electrode, a first diffusion layer and a second diffusion layer, the first and second diffusion layers arranged in a semiconductor substrate to be adjacent to the first gate electrode; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a first bit line connected to the second contact layer and arranged above the first gate electrode of the first memory cell; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the third and fourth diffusion layers arranged in a semiconductor substrate to be adjacent to the second gate electrode, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; a third contact layer connected to the third diffusion layer of the second memory cell; a fourth contact layer connected to the third contact layer; a second bit line connected to the fourth contact layer, arranged above the second gate electrode of the second memory cell, and arranged parallel to the first bit line; an element isolation insulating layer formed in an upper portion of the semiconductor substrate and arranged between the first and second memory cells; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer, the conductive layer formed to be contact with the element isolation insulating layer that is arranged between the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell.