Patent ID: 9189173
Filing Date: 2015-11-17
Classification: G06F

Abstract:
1. A memory system comprising: first and second memory chips, each of which includes a memory cell array and a buffer, each of the first and second memory chips reads out read data from the memory cell array to the buffer when a first command is received, and outputs one-Nth of the read data from the buffer when a second command is received; and a memory controller connected to the first and second memory chips via wirings through which the read data outputted from the first and second memory chips is transferred, the memory controller being configured to output the first command and thereafter outputs N pieces of second commands to the first and second memory chips, and to receive the read data from the first and second memory chips, first read-time being required to read out the read data from the memory cell array to the buffer, and second read-time being required to transfer each of the one-Nth of the read data from the buffer to the memory controller, wherein in a case where the memory controller reads out first read data from the first memory chip and thereafter reads out second read data from the second memory chip, the memory controller outputs the first command to the first memory chip, and then outputs M pieces of the second commands to the first memory chip, after which the memory controller outputs the first command to the second memory chip, and then outputs (N−M) pieces of the second commands to the first memory chip, a relation of (N−M−1)×(the second time)<the first time<=(N−M)×(the second time) being satisfied.