Patent ID: 8929133
Filing Date: 2015-01-06
Classification: G11C,H01L

Abstract:
1. A memory array comprising: a semiconductor-on-insulator (SOI) substrate; a first set of lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate, the first set of lateral BJTs forming a first inverter having a first output terminal configured to invert a first input signal at a first input terminal; and a second set of lateral BJTs fabricated on the SOI substrate, the second set of lateral BJTs forming a second inverter having a second output terminal configured to invert a second input signal at a second input terminal, the second inverter is cross coupled to the first inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal; a read circuit configured to output the binary state of the second output terminal, the read circuit including (a) a high impedance read input electrically coupled to the second output terminal, (b) a read enable input electrically coupled to a read word line, and (c) a read output electrically coupled to a read bit line; and a power supply configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral BJTs and the second set of lateral BJTs, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage; wherein the first set of lateral BJTs and the second set of lateral BJT each includes: