Patent ID: 9130597
Filing Date: 2015-09-08
Classification: G06F,H03M

Abstract:
1. A method of performing error correction on a set of serial bits comprising 2 N bits of serial data followed by one bit of checksum followed by N bits of error correction data, wherein N is a positive integer, the method comprising: shifting the bits of serial data into a shift register; using an exclusive-OR of the checksum with a generated checksum of all the bits of serial data residing in the shift register to set or clear a corresponding number of bits in a circular shift register (CSR); successively, for each of the N bits of error correction data, applying an exclusive-OR of each bit of error correction data with a corresponding generated bit of error correction data to a shift of the CSR to halve a number of set bits within the CSR; and exclusive-ORing the bits of serial data residing in the shift register with the corresponding bits residing in the CSR to correct the bits of serial data.