Patent ID: 6303502
Filing Date: 2001-10-16
Classification: H01L

Abstract:
A method of fabricating a one-transistor memory, comprising the steps of:preparing a single crystal silicon substrate;forming a device area on the substrate;growing a gate oxide layer on the surface of the substrate;depositing a bottom electrode structure on the gate oxide layer;implanting ions to form a source region and a drain region and activating the implanted ions;spin coating the structure with a first ferroelectric layer having a thickness of between about 5 nm and 100 nm;depositing a second ferroelectric layer to a thickness of between about 50 nm and 300 nmannealing the structure to provide a c-axis ferroelectric orientation;etching the structure to remove excess ferroelectric material;depositing a protective layer;depositing a layer of silicon oxide; andmetallizing the structure.