Patent ID: 8164199
Filing Date: 2012-04-24
Classification: H01L

Abstract:
1. A die stack comprising: a bottom die; a top die stacked on the bottom die; and a floating metal layer disposed upon the bottom die, the floating metal layer being electrically isolated from the bottom die by insulating material, wherein the floating metal layer acts as an electrically conductive die pad for the top die and as a bond pad for conductive interconnections, and wherein both the bottom die and the top die are discrete semiconductor devices, and wherein the bottom die is a first MOSFET having a source on its top and a drain on its bottom, wherein the floating metal layer is isolated from said source of said first MOSFET by insulating material, and the top die is a second MOSFET having a source disposed upon one side and a drain disposed on a side opposite to said one side and contacting said floating metal layer.