Patent ID: 8775842
Filing Date: 2014-07-08
Classification: G09G

Abstract:
1. A memory device comprising: a memory array in which a plurality of memory cells are arranged in a matrix manner; a row driver for driving each of a plurality of rows of the memory array; a column driver for driving each of a plurality of columns of the memory array, the column driver being capable of supplying, by use of one of a plurality of discrete levels, to each of the plurality of the memory cells, one of a plurality of logical levels to be retained by the memory cell; a first power source for supplying a first potential level; a second power source for supplying a second potential level; a third power source for supplying a potential which is higher than a highest potential of the plurality of discrete levels; and a fourth power source for supplying a potential which is lower than a lowest potential of the plurality of discrete levels, the first potential level and the second potential level being used to supply the plurality of discrete levels, the first power source and the second power source being capable of, in combination with each other, carrying out a first operation mode in which the column driver supplies the one of the plurality of discrete levels to the memory cell so as to cause the memory cell to retain the one of the plurality of logical levels, in a case where the first operation mode is carried out, the first power source and the second power source being caused to be in operation, and at least one of the third power source and the fourth power source being stopped from being in operation.