Patent ID: 6349240
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A semiconductor device manufacturing system comprising:a manufacturing line which manufactures a wafer with a plurality of semiconductor chips provided therein in a grid-like arrangement by a predetermined manufacturing device; a wafer tester which tests said semiconductor chips for electric characteristics thereof; a position information writing device which writes into each semiconductor chip information of chip position on said wafer; a wafer test information storage device which stores a first test result outputted from said wafer tester and said chip position information on said wafer that is associated with said first test result; a package assembling device which divides said wafer into respective ones of said semiconductor chips to produce semiconductor devices each sealed in a package; a product tester which tests each semiconductor device for its electric characteristics; a chip position detecting device which detects position information of said semiconductor device on said wafer after said semiconductor device has been sealed in a package; a product test information storage device which stores a second test result outputted from said product tester and said information of chip position on said wafer which that is detected by said chip position detecting device and is associated with said second test result; and a failure distribution mapping device which maps the distribution of failures corresponding to a wafer by combining position information of those chips determined to be faulty by said wafer tester and position information of those chips determined to be faulty by said product tester, based on said first test result, said second test result and said information of chip position; wherein a cause of failures is determined based on said distribution of failures.