Patent ID: 6524910
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of fabricating groups of gate structures on a semiconductor substrate, featuring a first group of gate structures comprised with a first silicon dioxide gate insulator layer, and featuring a second group of gate structures comprised with a second silicon dioxide gate insulator layer, with said first silicon dioxide gate insulator layer thinner than said second silicon dioxide gate insulator layer, comprising the steps of:forming a composite silicon nitride layer, on a first portion of said semiconductor substrate, with said composite silicon nitride layer comprised of a first silicon nitride layer, underlying a second silicon nitride layer, while a second portion of said semiconductor substrate is covered by said second silicon nitride layer; performing an oxidation procedure to form said first silicon dioxide gate insulator layer, on said first portion of said semiconductor substrate, underlying said composite silicon nitride layer, and simultaneously forming said second silicon dioxide gate insulator layer, on said second portion of said semiconductor substrate, underlying said second silicon nitride layer; depositing a polysilicon layer; and patterning of said polysilicon layer, said composite silicon nitride layer, and said first silicon dioxide gate insulator layer to form said first group of said gate structures, on said first portion of said semiconductor substrate, and simultaneously patterning of said polysilicon layer, said second silicon nitride layer, and said second silicon dioxide gate insulator layer to from said second group of said gate structures, on said second portion of said semiconductor substrate.