Patent ID: 6198308
Filing Date: 2001-03-06
Classification: H03K

Abstract:
A buffer circuit having an input node and an output node, the circuit comprising:a. an input branch including a first input section with an output and with an input coupled to the input node, and a second input section with an output and with an input coupled to the input node, wherein said first input section has a first switching potential threshold and said second input section has a second switching potential threshold, and wherein said first switching potential threshold is not equal to said second switching potential threshold;b. a logic circuit having a first input coupled to said output of said first input section, a second input coupled to said output of said second input section and an output;c. a first input controller coupled between said output of said first input section and the output node, wherein said first input controller is coupled to said logic circuit such that said logic circuit enables operation of said first input controller;d. a second input controller coupled between said second input section and the output node, wherein said second input controller is coupled to said logic circuit such that said logic circuit enables operation of said second input controller; ande. a latch device coupled between said logic circuit and said first input controller and between said logic circuit and said second input controller.