Patent ID: 6728829
Filing Date: 2004-04-27
Classification: G09G,G11C,H04B

Abstract:
A process of synchronously reading data from a dynamic random access memory array formed on a chip, the array including plural array data leads carrying parallel data signals from the array and parallel array address leads carrying parallel address signals to the array, one data signal representing one data bit and one address signal representing one address bit, the array being organized in plural addressable locations with each location containing one data word of plural data bits and each location being randomly addressable by the address signals for reading one word of data bits from each addressed location to the array data leads, the process comprising:A. applying a clock signal to the chip, the clock signal being formed of rising and falling edges regularly spaced in time and being continuous during operation of the device; B. applying parallel address signals to address terminals on the chip in plural groups separated in time and at the same time as applying the continuous clock to the chip to address a random location in the array; C. latching each group of parallel address signals as they are applied to the chip; D. producing a sequence of address signals starting from the latched address signals addressing the random location in the array; E. applying the sequence of address signals to the array address leads to address locations in the array from which the parallel data signals are to be read; F. conveying the read, parallel data signals from the array data leads; and G. applying the parallel data signals to data output terminals on the chip synchronous with the clock signal, each set of parallel data signals representing one data word.