Patent ID: 7373624
Filing Date: 2008-05-13
Classification: G06F

Abstract:
1. A method for performing verification, said method comprising: receiving a design including one or more targets, one or more constraints, one or more registers and one or more inputs; computing a first function of one of said one or more targets over said one or more registers and said one or more inputs; computing a second function of one or more of said one or more constraints over said one or more registers and said one or more inputs; existentially quantifying said inputs of said first function and said second function; performing a bounded analysis to determine if said one of said one or more targets may be hit while adhering to said constraints; existentially quantifying a preimage of said inputs of said first function and said inputs of said second function to create a synthesizable preimage; simplifying said synthesizable preimage; synthesizing said synthesizable preimage to create an enlarged target; and performing verification of said enlarged target.