Patent ID: 9147577
Filing Date: 2015-09-29
Classification: H01L

Abstract:
1. A method for forming a floating gate transistor, comprising: forming a polysilicon layer over a gate dielectric layer disposed on a semiconductor substrate; defining a gate region for a floating gate transistor; disposing a layer over said polysilicon layer that includes opposed edge features that extend into said gate region; etching to remove a partial thickness of said polysilicon layer in a central section of said gate region using said edge features; removing said polysilicon layer from areas other than said gate region thereby producing a floating gate from said polysilicon layer in said gate region, said floating gate including upwardly extending fins disposed at opposed lateral edges and a recessed central portion interposed therebetween; forming a floating gate oxide over said floating gate including over said recessed central portion and said fins; and forming a control gate at least partially over said floating gate oxide.