Patent ID: 9053787
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A crosspoint nonvolatile memory device comprising: a plurality of word lines parallel to each other on a first plane; a plurality of bit lines parallel to each other on a second plane parallel to the first plane, the bit lines three-dimensionally crossing the word lines; a crosspoint memory cell array including memory cells arranged in rows and columns at respective three-dimensional crosspoints between the word lines and the bit lines, each of the memory cells including a variable resistance element changeable between two resistance states which are a first resistance state and a second resistance state that has a lower resistance value than a resistance value of the first resistance state; a word line selector that selects a word line from the word lines; a bit line selector that selects a bit line from the bit lines; a writing circuit that supplies a writing current or a writing voltage to change a resistance state of a variable resistance element in a selected memory cell, the selected memory cell being selected by selecting the bit line by the bit line selector and selecting the word line by the word line selector; a sense amplification circuit that supplies a load current to the selected memory cell to read the resistance state of the variable resistance element in the selected memory cell; and a control circuit that controls the sense amplification circuit and the writing circuit, wherein, in the crosspoint memory cell array, (A) at least one memory cell including a variable resistance element in the second resistance state among one or more memory cells connected to the bit line selected by the bit line selector except the selected memory cell is determined as at least one first memory cell, and (B) at least one memory cell including a variable resistance element in the second resistance state among one or more memory cells connected to the word line selected by the word line selector except the selected memory cell is determined as at least one second memory cell, and the control circuit changes the value of the at least one of (a) the writing current or the writing voltage and (b) the load current, in proportion to the total number of one or more memory cells including a variable resistance element in the second resistance state among one or more memory cells each located at a crosspoint between a word line connected to a corresponding one of the at least one first memory cell and a bit line connected to a corresponding one of the at least one second memory cell.