Patent ID: 7241635
Filing Date: 2007-07-10
Classification: H01L

Abstract:
1. A method for binning semi-custom ASIC devices including the steps of: fabricating a boat of partially completed generic base wafers lacking customizing masking layers applied during fabrication process to customize said wafers for a particular application, wherein processing steps are applied in the same timeframe to the generic base wafers in said boat; and taking at least one wafer from said boat of partially completed generic base wafers; and completing the fabrication process for said at least one wafer taken from said boat of partially completed generic base wafers where the customizing masking layers implement a design requiring the least restrictive bin relative to a parameter being considered; and testing said at least one wafer after completion of the fabrication process to determine which bin it corresponds to relative to the parameter being considered, wherein the testing of said wafer taken from the boat is done prior to completion of the fabrication process for the remaining partially completed wafers in said boat; and assigning the remaining un-customized and un-tested wafers in said boat of partially completed generic base wafers to a specific wafer bin according to the test results for said at least one wafer; and saving the remaining wafers in said boat of partially completed generic base wafers for use at a later time with designs that require parameters supported by the remaining wafers in said boat of partially completed generic base wafers.