Patent ID: 7494932
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method for forming a mask on an integrated electronic circuit, comprising the following steps: a) forming at least one open cavity in a substrate of the circuit, said substrate being reflective for radiation of a lithography process and the cavity opening onto a substantially planar surface of the substrate; b) heating the substrate so as to close off the cavity by deformation of the substrate, creating a depression in the surface of the substrate aligned with the closed cavity, along a direction perpendicular to the substrate surface; c) at least partly filling the depression in the substrate surface with a portion of a material selected so that said portion attenuates a radiation reflected by the substrate; d) forming a lithography resist layer on the circuit on top of the substrate surface; e) exposing the lithography resist layer to a primary radiation flux that corresponds to an amount of radiation below the development threshold of the lithography resist layer and determined so that an amount of radiation corresponding to the sum of said primary flux and a secondary flux obtained by reflection of said primary flux on the substrate outside said portion is above the development threshold of the lithography resist layer; and f) developing the lithography resist layer so as to obtain a mask having an edge that corresponds to an outline of the depression in the substrate surface.