Patent ID: 6190977
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of:forming a gate insulator layer over said semiconductor substrate;forming a first silicon layer over said gate insulator layer;forming an first dielectric layer over said first silicon layer;removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region;doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region;forming an undoped spacer structure on sidewalls of said gate region;forming a second silicon layer on said semiconductor substrate;removing said first dielectric layer;doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure;forming a metal layer over said semiconductor substrate;performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer; andremoving unreacted portion of said metal layer.