Patent ID: 6013946
Filing Date: 2000-01-11
Classification: H01L

Abstract:
A semiconductor chip assembly comprising:a semiconductor chip including a plurality of input/output pads on a surface thereof wherein said input/output pads are on an interior portion of said surface of said semiconductor chip;an insulating layer on said surface of said semiconductor chip wherein said input/output pads are exposed adjacent said insulating layer wherein said insulating layer has an opening therein exposing said input/output pads;a plurality of conductive traces on said insulating layer opposite said semiconductor chip wherein each of said conductive traces corresponds to a respective one of said input/output pads;a plurality of bonding wires wherein each of said bonding wires corresponds to a respective one of said input/output pads and one of said conductive traces, and wherein each of said bonding wires is bonded at a first end to said respective input/output pad and at a second end to said respective conductive trace;a dam on said insulating layer opposite said semiconductor chip and around said opening wherein each of said conductive traces extends under said dam to a portion of said insulating layer outside said dam;a sealing lid on said dam wherein said sealing lid covers said opening, said bonding wires, and said input/output pads;at least one tie bar extending from said dam; anda rail connected to said tie bar.