Patent ID: 8988120
Filing Date: 2015-03-24
Classification: H03B

Abstract:
1. A frequency multiplier, comprising: a first output end; a second output end; a first impedance module, having one end coupled to a first predetermined potential level and one other end coupled to the first output end; a second impedance module, having one end coupled to a second predetermined potential level and one other end coupled to the second output end; a first path, coupled between the first output end and the second output end; a second path, coupled between the first output end and the second output end; wherein the first path and the second path receive an input signal and an inverted input signal, respectively; wherein the first path comprises a first first-type transistor, which has a first end coupled to the first output end, a second end, and a control end for receiving the input signal, the first path further comprises a first second-type transistor, which has a first end coupled to the second end of the first first-type transistor, a second end coupled to the second output end, and a control end for receiving the inverted input signal; wherein the second path comprises a second first-type transistor, which has a first end coupled to the first output end, a second end, and a control end for receiving the inverted input signal, the second path further comprises a second second-type transistor, which has a first end coupled to the second end of the second first-type transistor, a second end coupled to the second output end, and a control end for receiving the input signal; and wherein a phase of the inverted input signal is inverse to a phase of the input signal, and the first path and the second path are conducted or non-conducted according to the input signal and the inverted input signal; when the first path is conducted, a first current flows from the first impedance module and passes along the first path to the second impedance module, so that the first impedance module generates a first output signal at the first output end and the second impedance module generates a second output signal at the second output end; when the second path is conducted, a second current flows from the first impedance module and passes along the second path to the second impedance module, so that the first impedance module generates a third output signal at the first output end and the second impedance module generates a fourth output signal at the second output end; the first path and the second path are not conducted simultaneously, and a frequency of a first combination signal generated from combining the first output signal and the third output signal and a frequency of a second combination signal generated from combining the second output signal and the fourth output signal are N times of a frequency of the input signal, where N is a positive rational number.