Patent ID: 6441438
Filing Date: 2002-08-27
Classification: H01L

Abstract:
ESD protection device formed on a substrate connected between a junction of an input/output pad and internal circuitry and a reference voltage source to prevent damage to said internal circuitry during application of an ESD voltage source to said input/output pad by conducting an ESD current from said ESD voltage source to said reference voltage source, whereby said ESD protection device comprises:at least one source region of a material of a first conductivity type implanted into the surface of the substrate at a first distance and connected to the reference voltage source; at least one drain region of the material of the first conductivity type implanted into the surface the substrate at a second distance from each other and between the plurality of source region, at a third distance from the source regions and connected to the junction of the input/output pad and the internal circuitry; at least one gate electrode formed by the deposition of a conductive material upon an insulating material formed at the surface of the substrate above a channel region that is between each of the source regions and the drain regions and connected to the reference voltage source, whereby each gate electrode has a uniformly variable length and thus the channel region has a uniformly variable length; at least one parasitic bipolar transistors, each parasitic bipolar transistor having a collector that is a portion of one of the drain regions, an emitter that is a portion of one of the source regions adjacent to said one drain region, and a base that is a portion of the channel region between said one drain region and said one source region, whereby said ESD current is distributed uniformly over said channel region; and at least one parasitic resistor formed of a bulk resistance of said substrate and connected from the bases of said parasitic transistors connected to the reference voltage source.