Patent ID: 6275419
Filing Date: 2001-08-14
Classification: G11C,H01L

Abstract:
A method of operating a memory which comprises a plurality of word lines, and a plurality of EEPROM memory cells, each cell uniquely associated with one word line and one bit line, each memory cell having a floating gate electrode, a steering electrode, and an erase electrode, said method comprising the steps of:selecting one or more of said memory cells along a row;controlling the magnitude of a steering voltage applied to said steering electrodes of said selected one or more memory cells, on a cell by cell basis;establishing erase potentials on said selected one or more memory cells, thereby removing charge from said floating gates of said selected one or more memory cells,wherein the magnitude of electron removal from each floating gate is established on a cell by cell basis by the magnitude of the steering potential applied to its associated steering electrode.