Patent ID: 7663225
Filing Date: 2010-02-16
Classification: H01F,H01G,H05K,Y10S,Y10T

Abstract:
1. A method for manufacturing electronic components, in which conductive pattern layers are laminated to each other with insulating layers provided therebetween to form an integrated laminate, the method comprising the steps of: alternately laminating the insulating layers and conductive pattern layers including conductive patterns which are formed at intervals therebetween in layer surface directions to form a laminate in which laminate portions of electronic component-forming conductive patterns are collectively formed; applying a force to the laminate in a lamination direction to form an integrated laminate; after the force is applied to the laminate in the lamination direction to form the integrated laminate, cutting the laminate along cutting lines provided along boundaries of the laminate portions of the electronic component-forming conductive patterns so as to separate electronic components from each other; forming at least one removal dummy pattern in at least one of the conductive pattern layers which are to be laminated to each other before one of the insulating layers is provided on a surface of said at least one of the conductive pattern layers, the at least one removal dummy pattern having a size that allows it to be disposed within a cutting-removal region which is a region to be cut and removed by the step of cutting the laminate; forming at least one floating dummy pattern in at least one of the conductive pattern layers of the laminate portions of the electronic component-forming conductive patterns so as to be disposed in the vicinity of an outside of the cutting-removal region at an interval therefrom before one of the insulating layers is formed by lamination on a surface of said at least one conductive pattern layer, the at least one floating dummy pattern not being electrically connected to the electronic component-forming conductive patterns; and the at least one removal dummy pattern is not exposed at end surfaces of separated electronic components.