Patent ID: 7696766
Filing Date: 2010-04-13
Classification: G01R

Abstract:
1. A semiconductor device test structure, the semiconductor device test structure comprising: a printed circuit board; a space transformation layer having a first major surface and a second major surface, the first major surface being on an opposing surface from the second major surface, the first major surface having a first set of contacts facing the printed circuit board, the second major surface having a second set of contacts with a first pitch; compressible connectors electrically coupling electrical contacts on the printed circuit board to the first set of contacts on the space transformation layer, the space transformation layer being movable relative to the printed circuit board while maintaining an electrical connection between the electrical contacts on the printed circuit board and the first set of contacts on the space transformation layer via the compressible connectors; and a substrate located over the space transformation layer, a plurality of contact tips with a second pitch smaller than the first pitch, the plurality of contact tips located on the substrate, wherein each contact tip is electrically coupled to respective ones of the second set of contacts.