Patent ID: 6650265
Filing Date: 2003-11-18
Classification: H03M

Abstract:
A current mode segmented DAC having a maximum resolution N and capable of operating at a first resolution and at a second resolution, the second resolution being less than the first resolution, comprising:a first segment of the current mode segmented DAC receiving M input bits, the first segment including one or more current sources, selected ones of the current sources capable of being selectively disabled in response to a control signal; a second segment of the current mode segmented DAC receiving L input bits, where L>Nâˆ’M, the second segment including one or more current sources, selected one of the current sources capable of being selectively disabled in response to a control signal; and a control circuit providing the control signals to disable the current sources of the first and second segments of the current mode segmented DAC, wherein when the current mode segmented DAC operates in the second resolution, the control circuit disables one or more of the current sources in the first segment.