Patent ID: 8392806
Filing Date: 2013-03-05
Classification: H03M

Abstract:
1. A method of determining positions of one or more error bits, the method comprising: receiving a BCH codeword at input circuitry of a decoder device; establishing a threshold number of correctable bits; determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes, the one or more syndromes being twice a maximum number of correctable bits in the received BCH codeword; when the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, determining the value of each coefficient in a scaled error locator polynomial by performing a non-iterative, closed-form solution on the scaled error locator polynomial, the scaled error locator polynomial being an original error locator polynomial scaled by a constant scale factor, the constant scale factor being determined according to the value of each of the one or more syndromes; and having determined the value of each coefficient in the scaled error locator polynomial, obtaining one or more roots of the scaled error locator polynomial, each of the one or more roots indicating a position of an error bit, wherein