Patent ID: 7960279
Filing Date: 2011-06-14
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising the steps of: forming a first insulating film on underlayer wiring on a semiconductor substrate; forming a second insulating film on said first insulating film; forming a third insulating film on said second insulating film; dry-etching said third, second, and first insulating films to form an opening reaching said underlayer wiring; forming a barrier metal film on the inner surface of said opening and on said third insulating film; forming a conductive layer on said barrier metal film such that said opening is buried under said conductive layer; removing said conductive layer, said barrier metal film, said third insulating film, and a portion of said second insulating film by use of a chemical mechanical polishing technique such that said conductive layer and said barrier metal film still remain in said opening so as to form upper layer wiring electrically connected to said underlayer wiring; and applying a reducing plasma treatment to the exposed surface of said second insulating film and the exposed surface of said conductive layer; wherein said second insulating film forming step includes forming an insulating film under a pressure of 500 Pa or less by use of a plasma CVD technique using alkylalkoxysilane and a nonoxidizing gas as material gases, said alkylalkoxysilane being represented by the following formula: where: R and R′ each represent CH 3 ; w, x, and z denote positive integers; y denotes 0 or a positive integer; and (w/x)=2.