Patent ID: 6307588
Filing Date: 2001-10-23
Classification: G06T

Abstract:
A system for processing a group of image pixel data comprising:a plurality of random access memories, each of the memories having addresses that are arranged identically to each other, each of the random access memories storing the group of image pixel data at the identical addresses, wherein each of the addresses is constructed and arranged to store an image pixel data of the group of image pixel data;an image processor that generates address values for accessing the group of image pixel data over a multi-bit address line and that manipulates the group of image pixel data;an address expander interconnected with the multi-bit address line, the address expander being constructed and arranged to convert a selected address in each of the memories into a plurality of related addresses in each of the memories, related image pixel data from the group of image pixel data being stored at the plurality of related addresses, a selected image pixel data from the group of image pixel data being stored at the selected address, and each of the related addresses being located at a predetermined offset relative to the selected address; anda plurality of address expander address lines that transmit the plurality of related addresses to each of the plurality of random access memories so that the processor accesses each of the plurality of related image pixel data over the multi-bit data line.