Patent ID: 6737322
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device including a non-volatile memory device, and a resistance element including a resistance conductive layer, the method comprising the steps of:forming a first dielectric layer above a semiconductor layer; forming a first conductive layer above the first dielectric layer; forming a second dielectric layer above a portion of the first conductive layer that becomes the resistance conductive layer; forming a stopper layer above the first conductive layer and the second dielectric layer; patterning the stopper layer and the first conductive layer to form a gate layer; patterning the stopper layer, the second dielectric layer and the first conductive layer to form the resistance conductive layer; forming sidewall control gates through an ONO film on both side surfaces of the gate layer; forming a third dielectric layer above the gate layer and the resistance conductive layer; polishing the third dielectric layer such that the stopper layer is exposed; removing the stopper layer; forming a second conductive layer above the gate layer and the resistance conductive layer; patterning the second conductive layer to form a word line; and patterning the gate layer to form a word gate.