Patent ID: 7494854
Filing Date: 2009-02-24
Classification: H01L

Abstract:
1. A method comprising: forming a semiconductor substrate that includes a first well and a second well; forming a deep well in the substrate that physically isolates the substrate from at least the second well; forming a first doped region in the second well, wherein the first well, the second well, and the first doped region are configured to form a parasitic bipolar junction transistor (BJT); forming a second doped region in the substrate for receiving an electrostatic discharge (ESD), wherein the second doped region comprises a contact to the first well; forming an isolation region between the first doped region and the second doped region, wherein the isolation region electrically isolates the first doped region from the second doped region; and forming an ESD detection circuit connected to the second well for detecting the ESD, the ESD detection circuit for providing a trigger current or a trigger voltage to the second doped region to trigger the BJT to discharge the ESD.