Patent ID: 6087698
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A semiconductor device comprising:a silicon-on-insulator (SOI) substrate having an underlying layer formed by a first insulation layer and a semiconductor layer on said underlying layer;a plurality of island semiconductor layers formed by selectively dividing said semiconductor layer;source and drain regions formed in each of said island semiconductor layers;a plurality of gate insulation layers superposed on said island semiconductor layers, respectively;a plurality of first gate electrodes superposed on said gate insulation layers, respectively, and each arranged between said source and drain regions;a second insulation layer formed on said first insulation layer and surrounding a plurality of laminate structures each made up of one of said island semiconductor layers, one of said gate insulation layers and one of said first gate electrodes, said second insulation layer being flush with each of said first gate electrodes and thicker than a laminate layer made up of one of said island semiconductor layers and one of said gate insulation layers; anda second gate electrode formed over both said one of said first gate electrodes and said second insulation layer;wherein said one of said island semiconductor layers, said one of said gate insulation layers and said one of said first gate electrodes, which make up each said laminate structures, have a same width.