Patent ID: 7382027
Filing Date: 2008-06-03
Classification: H01L

Abstract:
1. A MOSFET device structure comprising: a semiconductor substrate having device elements comprising isolation structures, a gate structure comprising a gate, sidewall passivation around the gate, and source and drain with lightly and heavily doped regions; a first dielectric layer formed over said semiconductor substrate, said first dielectric layer located adjacent a lower portion of said gate structure, wherein a top surface of the first dielectric layer is located below a top surface of the gate structure; a second dielectric etch-stop layer pattern formed over said first dielectric layer, wherein said second dielectric etch-stop layer pattern is located adjacent an upper portion of said gate structure, wherein the second dielectric etch-stop layer directly covers an upper portion of the sidewall passivation to act as an etch-stop for the sidewall passivation; a third dielectric layer formed over and in contact with the first dielectric layer and second dielectric etch-stop layer; and a contact disposed in the third dielectric layer, the contact contacting said gate structure.