Patent ID: 7294880
Filing Date: 2007-11-13
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of first memory cells connected in series between a first node and a second node; a first line connected to the first node; and a second line connected to the second node, wherein each of the plurality of first memory cells includes a first gate electrode formed above a semiconductor substrate as a word line, a second gate electrode formed above the semiconductor substrate as an auxiliary gate, and a plurality of first charge storage regions formed between the first gate electrode and the semiconductor substrate, wherein the first gate electrodes and the second gate electrodes of the plurality of first memory cells connected in series between the first node and the second node are arranged alternately with each other and in parallel with one another, a plurality of second memory cells connected in series between a third node and a fourth node; a third line connected to the third node; and a fourth line connected to the fourth node, wherein each of the plurality of second memory cells includes a third gate electrode formed above the semiconductor substrate, a fourth gate electrode formed above the semiconductor substrate and a plurality of second charge storage regions formed between the third gate electrode and the semiconductor substrate, wherein each of the third gate electrodes of the plurality of second memory cells is connected to corresponding one of the first gate electrodes of the plurality of first memory cells, and wherein each of the fourth gate electrodes of the plurality of second memory cells is connected to corresponding one of the second gate electrodes of the plurality of first memory cells.