Patent ID: 7146538
Filing Date: 2006-12-05
Classification: G06F

Abstract:
1. A bus interface module (“BIM”) connectable to a debug bus comprising a plurality of bus segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising: logic for receiving data from a previous BIM; logic for receiving data from local logic associated with the BIM; and logic for rearranging the previous BIM data with local logic data in a chunk-by-chunk controllable manner and transmitting the rearranged data to a next BIM, wherein the data received from a previous BIM and the data received from local logic are logically subdivided into individually-manipulable data blocks, the logic for rearranging comprising logic for moving data received from the previous BIM in a first block position to a second block position, further wherein the logic for moving data comprises N N×1 multiplexors, each input of the N N×1 multiplexors operating to accept one block of the data received from a previous BIM.