Patent ID: 7262643
Filing Date: 2007-08-28
Classification: H03K

Abstract:
1. A semiconductor integrated circuit comprising: an output circuit including a plurality of output MOSFETs whose source-drain paths are connected in parallel between an output node of said output circuit and a ground potential node, said output MOSFETs connected in parallel being divided into a plurality of groups, and said plurality of groups being respectively divided into a plurality of subgroups; a first control circuit that, from among the plurality of output MOSFETs, selects a number of output MOSFETS to be turned ON to control output impedance and forms selection signals; a second control circuit that controls a slew rate by controlling a drive signal of the output MOSFETs that are turned ON and forms timing signals; and a plurality of output prebuffers each of which is coupled to each of said output MOSFETs, wherein said output MOSFETs are of an n-type MOSFET, wherein said plurality of output prebuffers receive each of said selection signals, said timing signals and data signals to be outputted, and drives each of said plurality of output MOSFETs, and wherein said first control circuit controls output impedance and said second control circuit controls a slew rate, and wherein said first control circuit and said second control circuit perform their respective control independently.