Patent ID: 7682945
Filing Date: 2010-03-23
Classification: H01L,Y10S

Abstract:
1. A method of producing a memory device comprising: providing an interlevel dielectric layer including a conductive stud having a first width; forming a stack comprising a metal layer atop the conductive stud, and a first insulating layer overlying the metal layer; forming a second insulating layer atop the stack and the interlevel dielectric layer; planarizing the second insulating layer until an upper surface of the first insulating layer is exposed, wherein an upper surface of the second insulating layer is coplanar with the upper surface of the first insulating layer; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying a substantially anisotropic etch step to the conformal insulating layer to produce an opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.