Patent ID: 6324100
Filing Date: 2001-11-27
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a semiconductor substrate having a P-type conductivity region electrically separated from a peripheral circuit; anda stacked gate memory cell having a control gate, a charge storing layer, a source, and a drain, said stacked gate memory cell being formed in said P-type conductivity region, whereina gate potential greater than a potential of the semiconductor substrate is applied to the control gate of the stacked gate memory cell in a data write mode to write data in the stacked gate memory cell,a source potential between the gate potential and the substrate potential is applied to the source of the stacked gate memory cell in the data write mode,a drain potential between the gate potential and the substrate potential is applied to the drain of the stacked gate memory cell in the data write mode, anda channel potential is applied to a channel of the stacked gate memory cell in the data write mode to write data in the stacked gate memory cell.