Patent ID: 8995174
Filing Date: 2015-03-31
Classification: G11C,H01L,H03K

Abstract:
1. A semiconductor device comprising: a first NAND gate comprising a first input terminal, a second input terminal, and an output terminal; a second NAND gate comprising a first input terminal, a second input terminal, and an output terminal; a switch comprising a first terminal and a second terminal; a transistor comprising a first terminal, a second terminal, and a gate; and a capacitor comprising a first terminal and a second terminal, wherein the output terminal of the first NAND gate is electrically connected to the first terminal of the switch, wherein the second terminal of the switch is electrically connected to the first input terminal of the second NAND gate, wherein the output terminal of the second NAND gate is electrically connected to the first input terminal of the first NAND gate and the first terminal of the transistor, wherein the second terminal of the transistor is electrically connected to the first terminal of the capacitor, and wherein the transistor comprises a channel formation region comprising an oxide semiconductor.