Patent ID: 7345910
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A semiconductor device having a memory unit that does not require a refresh operation, comprising: memory circuits for storing data, arranged in a matrix form; first signal lines for reading said data from said memory circuits; second signal lines for transferring a signal that controls connection between said memory circuits and said first signal lines; a sense amplifier circuit for reading and determining data by detecting a potential change or a current change in said first signal lines; and mitigating means for mitigating said potential change or said current change in said first signal lines during a period in which said sense amplifier circuit is being activated, wherein each of said memory circuits comprises a first inverter and a second inverter that constitute an inverter latch for storing said data, and said mitigating means comprises a potential control circuit, being arranged between GND and source terminals of NMOSs that constitute said first and second inverters and controlling connection between said source terminal and said GND based on an activating signal for said sense amplifier circuit.