Patent ID: 6295617
Filing Date: 2001-09-25
Classification: G06F,G11C

Abstract:
A testing method of a semiconductor memory device which comprises a memory section composed of a data cell array and an error correction code cell array for memorizing a data set and a normal error correction code, respectively, and which carries out error correction with the normal error correction code corresponding to said data set and having correction ability to correct a predetermined number of errors, comprising the steps of:storing data sets and test data sets into the data cell array and the error correction code cell array, respectively;preparing a register;storing in the register a test error correction code as an error correction code for a combination of each data set and each test data set corresponding to each data set, the test error correction code having test correction ability equal to the correction ability of the normal error correction code, the test error correction code being different from the normal error correction code;checking with the test error correction code whether or not the number of hard errors in the entirety of the memory section of the semiconductor memory device exceeds the correction ability of the normal error correction code; andjudging that the semiconductor memory device is normal when the errors occurring in the entirety of the memory section do not exceed the correction ability.