Patent ID: 6798693
Filing Date: 2004-09-28
Classification: G11C,H01L

Abstract:
A programmable read only memory cell useful in a memory array having select and access lines, the memory cell comprising:a MOS field effect transistor having a gate, a gate dielectric underlying the gate, and first and second doped semiconductor regions underlying both the gate dielectric and the gate in a spaced apart relationship to define a channel region therebetween; a MOS data storage element having a conductive structure, an ultra-thin dielectric underlying the conductive structure, and a first doped semiconductor region underlying both the ultra-thin dielectric and the conductive structure, the first doped semiconductor region of the MOS data storage element being coupled to the first doped semiconductor region of the MOS field effect transistor; a select line segment coupled to the gate of the MOS field effect transistor; a first access line segment coupled to the second doped semiconductor region of the MOS field effect transistor; and a second access line segment coupled to the conductive structure of the MOS data storage element.