Patent ID: 6166975
Filing Date: 2000-12-26
Classification: G11C

Abstract:
A semiconductor memory device, comprising:dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data;word lines each connecting the dynamic memory cells in one row of said array;bit lines each connecting the dynamic memory cells in one column of said array;pads to which receiving external address signals are applied;address amplifying circuits responsive to the external address signals applied to the pads for generating first internal address signals selecting a first number of said word lines in a normal operation mode;a control circuit responsive to a voltage stress test control signal for generating second internal address signals for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first number;word line selecting circuits responsive to the first and second internal address signals for outputting word line selecting signals;a word line driving voltage source; andword line driving circuits each coupled between corresponding ones of said word lines and said word line selecting circuits and responsive to the word line selecting signals for driving selected word lines, each of said word line driving circuits including:a first MOS transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word line selecting circuits, and a control terminal coupled to a power supply potential;a second MOS transistor of a second conductivity type opposite the first conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to a second current terminal of said first transistor;a third MOS transistor of the first conductivity type having a first current terminal coupled to the corresponding ones of said word lines, a second current terminal coupled to a ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits; anda fourth MOS transistor of the second conductivity type having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to said control terminal of said second transistor, and a control terminal coupled to the corresponding one of said word lines.