Patent ID: 7444560
Filing Date: 2008-10-28
Classification: G01R,G11C

Abstract:
1. A test clocking scheme comprising: a memory device; functional logic connected to the memory device; test logic connected to the memory device; a functional clock for driving the functional logic and the memory; and a test clock for driving the test logic and memory, wherein the test clock and the functional clock are separate such that the test logic is driveable by said test clock without said functional logic being driven by said test clock, wherein the scheme is configured such that a value of said test clock does not affect a value of said functional clock, wherein the scheme is configured such that the value of said functional clock does not affect the value of said test clock, wherein the scheme is configured such that the test clock and the functional clock are separate such that said functional logic is driveable by said functional clock without said test logic being driven by said functional clock, wherein the scheme is configured such that the functional clock and test clock can be shut off independently from each other such that the functional logic and memory are driven by said functional clock without said test logic having to be driven by said functional clock, and said test logic and memory are driven by said test clock without said functional logic having to be driven by said test clock.