Patent ID: 8868879
Filing Date: 2014-10-21
Classification: G06F,G11C

Abstract:
1. A system on chip comprising: a volatile random access memory; a read-only memory; and a processor configured to, during a development phase of the system on chip, read program code from the volatile random access memory and execute the program code, wherein the program code is developed during the development phase until a completed version of the program code is reached, wherein the processor is configured to, during an operational phase of the system on chip subsequent to the development phase, (i) read the completed version of the program code from the read-only memory, (ii) execute the completed version of the program code, and (iii) cache data in the volatile random access memory, and wherein the processor is configured to, during the operational phase and in response to an improvement to the completed version of the program code being developed, (i) read program code corresponding to the improvement from the volatile random access memory, and (ii) read remaining portions of the completed version of the program code from the read-only memory.