Patent ID: 6773930
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A method of forming an FeRAM integrated circuit, comprising:forming a transistor in a semiconductor substrate; forming an interlayer dielectric layer over the transistor; forming a conductive contact in the dielectric layer down to a portion of the transistor; forming a TiAlON diffusion barrier layer over the interlayer dielectric layer; forming a bottom electrode layer, a ferroelectric dielectric layer, and a top electrode layer over the TiAlON diffusion barrier layer; etching the top electrode layer, the ferroelectric dielectric layer and the bottom electrode layer to define an FeRAM capacitor stack; and etching a portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack, wherein oxygen within the TiAlON diffusion barrier layer substantially prevents a lateral etching thereof, thereby substantially preventing an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack.