Patent ID: 6759885
Filing Date: 2004-07-06
Classification: G06F,H03K

Abstract:
A clock analyzer comprising:a delay circuit having: an input port for receiving a reference clock signal from a clock source having a predetermined clock period; a plurality of functionally identical delay cells, each delay cell generating an approximately identical delay period of an input clock signal; and a plurality of output ports, each output port connected to the input port through a predetermined number of the delay cells for generating a delayed clock signal from the reference clock signal; at least one comparator circuit each having two input ports and one selection line as an output port wherein the two input ports of each comparator circuit are connected to the input port and one unique output port of the delay circuit, and each comparator circuit compares the reference clock signal to the delayed clock signal from the corresponding unique output port of the delay circuit and generates a selection signal on the selection line when the delayed clock signal overlaps the reference clock signal; and a clock shaping circuit for accepting a master clock signal having the predetermined clock period and generating the reference clock signal that has a duty cycle differing from the duty cycle of the master clock signal, the clock shaping circuit comprising at least one of the functionally identical delay cells; wherein the delay period of each of the delay cells is approximately determined by identifying the specific output port of the delay circuit which generates the selection signal.