Patent ID: 7049215
Filing Date: 2006-05-23
Classification: G02F,H01L

Abstract:
1. A method for fabricating a thin film transistor (TFT) array substrate, comprising: providing a substrate; forming a plurality of scan lines and a plurality of gates electrically connected to said scan lines on the substrate; simultaneously forming a plurality of first bonding pads and a plurality of second bonding pads over two edges of the substrate, wherein said first bonding pads are electrically connected with said scan lines; forming a gate dielectric layer over the substrate, for covering said scan lines, said gates, said first bonding pads and said second bonding pads; forming a plurality of channel layers over said gate dielectric layers of each of said gates; forming an ohm contact layers on each of said channel layers; forming a source and a drain on each of the said contact layers; forming a data line electrically connecting to each of said sources on the gate dielectric layers, wherein a terminal of each of said data lines is extended to each of the second bonding pads, and wherein said gates, each of said channel layers and each of said sources and each of said drain constitute a of thin film transistor; forming a mask layer over said gate dielectric layers, wherein said mask layer is disposed over areas corresponding to said first bonding pads and said second bonding pads; forming a cover layer over said substrate; forming a patterned photoresist layer over said cover layer, wherein said photoresist layer partially covering over said two edges of the substrate, wherein said photoresist layer comprises a plurality of first openings, a plurality of second openings and a plurality of third openings, wherein said drains are exposed within said first openings, said data lines are exposed within said second openings, and said second bonding pads are exposed within said third openings; performing an etching process by using the photoresist layer as an etching mask for removing portions of said cover layer and portions of said gate dielectric layers that are not covered by the photoresist layer and exposing a portion of said second bonding pads that are not covered by said photoresist layer; and forming an electrode material layer over said photoresist layer to form a plurality of pixel electrodes over said photoresist layer, wherein said electrode material layer fills in each of said first openings, said second openings and said third openings, and wherein said drains are electrically connected with said pixel electrodes via the first openings, said data lines are electrically connected with said second bonding pads via said second openings, said third openings and said electrode material layer.