Patent ID: 6504744
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:a memory cell array portion including a plurality of memory cells arranged in rows and columns, a plurality of normal word lines provided corresponding to a plurality of rows, a plurality of bit lines provided corresponding to a plurality of columns, and a spare word line provided for substituting for a defective normal word line of said plurality of normal word lines; a test circuit including a dummy word line and a drive circuit operating to amplify a voltage level of said plurality of bit lines corresponding to an activated dummy word line; a decision circuit referring to an address input, to determine whether or not to substitute a selected normal word line with said spare word line; and a select drive circuit operating in a test mode to selectively drive said dummy word line rather than said plurality of normal word lines and said spare word line, and operating in a mode other than said test mode to refer to a decision of said decision circuit to selectively drive a corresponding normal word line or a corresponding spare word line.