Patent ID: 8316200
Filing Date: 2012-11-20
Classification: G06F,Y02D

Abstract:
1. A microcomputer comprising: a flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; a flash controller that controls access to the flash memory; and an arbiter that is connected to a plurality of buses including a data bus and an instruction bus, the arbiter arbitrating between the plurality of buses and allowing one of the plurality of buses to access the flash memory, the arbiter generating bus identification information that identifies whether the allowed bus is the data bus or the instruction bus, and transmitting the bus identification information to the flash protection section, the flash controller including a flash protection section that performs a protection process relating to access to the given area of the flash memory based on the protection information and the bus identification information, and the flash protection section determining whether or not a read access is an instruction read access based on the bus identification information, performing the protection process when the read access is not the instruction read access, and performing access to the given area without the protection process when the read access is the instruction read access.