Patent ID: 6239624
Filing Date: 2001-05-29
Classification: G11C,H03K

Abstract:
A low-power sense amplifier for a memory, comprising:a differential amplifier for sensing and amplifying a weak voltage signal of a bit line connected to a memory cell, said differential amplifier having bias means transistors defining a load resistor component required for driving said differential amplifier;a latch amplifier for storing data inputted thereto and being operated by an output signal of said differential amplifier, andcutoff means for turning off said bias means transistors when there is a first logic state signal among the output signals of said latch amplifier, said cutoff means having two transistors and an inverter, said transistors having gates connected to outputs of said differential amplifiers, drains connected to outputs of said latch amplifier, and sources connected as input to said inverter, said inverter having an output connected to said bias means transistors.