Patent ID: 8723600
Filing Date: 2014-05-13
Classification: G05F,H03F

Abstract:
1. A circuit operable to use a MOS device in a triode mode of operation comprising, a biasing circuit; and a MOS device having a drain terminal, a source terminal, and a gate terminal, and being coupled to the biasing circuit, the source terminal having associated therewith a potential, the drain terminal having associated therewith a potential, and the gate terminal having associated therewith a potential, the drain and the source terminals having associated there between a resistance, wherein the biasing circuit couples the drain and source terminals of the MOS device to the gate terminal of the MOS device, and further wherein the biasing circuit couples a DC potential to the gate terminal of the MOS device to adjust the resistance between the source and drain terminals of the MOS device, wherein the resistance between the source and drain terminals is a non-linear function of voltage potentials at the source and drain terminals, the biasing circuit being operable to reduce the non-linearity of the resistance between the drain and source terminals by modulating the potential at the gate terminal of the MOS device by a combination of source and drain terminal potentials.