Patent ID: 7215031
Filing Date: 2007-05-08
Classification: H01L

Abstract:
1. A multi chip package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled by wire bonding to a first wire bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled by wire bonding to a second wire bonding pad on the second semiconductor chip, wherein at least the first bonding wire is a coated wire, which comprises a conductive core and an outer insulation coating, at least the first wire bonding pad is a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer of nickel (Ni) formed on the base pad; and a second conductive layer of gold (Au) formed on the first conductive layer.