Patent ID: 6343072
Filing Date: 2002-01-29
Classification: H04L

Abstract:
A router, includingat least one port disposed for receiving packets; at least one port disposed for transmitting packets; and processing circuits integrated into a single monolithic integrated circuit, said processing circuits including circuits for accessing a shared memory, said circuits including (a) circuits disposed for copying packets between at least one region of said shared memory and said processing circuits, and (b) circuits disposed for performing packet lookup in at least one region of said shared memory, said packet lookup being responsive to packet headers of said packets wherein said circuits disposed for copying packets comprise first circuits for receiving packet information in a serial format and converting said packet information into a parallel format and second circuits for receiving said packet information in a parallel format and converting said packet information into a serial format, and wherein said circuits for accessing said shared memory include circuits disposed for multiplexing and prioritizing requests for copying incoming packets to said shared memory, requests for copying outgoing packets from said shared memory, and requests for performing packet lookup.