Patent ID: 9208833
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A method comprising: controlling a first select transistor and a second select transistor during a memory operation of obtaining information stored in a memory cell of a first memory cell string and a second memory cell of a second memory cell string of a device, such that the first select transistor is turned on during a first time interval, and such that the second select transistor is turned on during a second time interval, the first select transistor coupled between a data line and the first memory cell string, the second select transistor coupled between the data line and the second memory cell string, each of the first and second memory cell strings including memory cells located in different levels of the device; and applying a signal having a level greater than ground potential to an access line coupled to the first and second memory cell strings during the memory operation of obtaining information stored in the first and second memory cell strings without resetting the signal during the memory operation of obtaining information stored in the first and second memory cell strings, wherein the data line is not precharged between the first and second time intervals.