Patent ID: 6804193
Filing Date: 2004-10-12
Classification: G06F

Abstract:
A multiprocessor system having a plurality of processor modules coupled together via a backplane, comprising:a first processor module having a first processor and a switch with a plurality of I/O ports and a plurality of communication paths coupled to the I/O ports of said switch, said switch being operable to route data packets formatted according to an Ethernet MAC protocol; a second processor module having a second processor and a first communication device that is operable to communicate with said switch via a first communication path on the backplane; and a third processor module having a third processor and a second communication device that is operable to communicate with said switch via a second communication path on the backplane; and wherein the switch is operable to route Ethernet MAC protocol data packets from one of said first, second or third processors to another of said first, second or third processors.