Patent ID: 6466077
Filing Date: 2002-10-15
Classification: G05F

Abstract:
A semiconductor integrated circuit device, comprising:a main circuit, comprised of a CMOS circuit, and being operative upon receiving a clock signal; a speed monitor circuit, comprised of a CMOS circuit, and for generating a speed signal therefrom; and a substrate bias controller for supplying substrate bias voltage to semiconductor areas where P-channel type MOSFETs and N-channel type MOSFETs are formed so as to construct said CMOS circuits of said main circuit and said speed monitor circuit, respectively, wherein: said substrate bias voltages are generated so that a frequency of said clock signal coincides with a delay time of said speed monitor circuit, so that said main circuit operates in synchronism with said clock signal, and, wherein speed of operation of said main circuit comprises at least two of a low speed, a middle speed, a high speed or a speed for standby.