Patent ID: 7361565
Filing Date: 2008-04-22
Classification: H01L

Abstract:
1. A method of forming a metal gate in a semiconductor device, comprising: forming a gate insulation pattern and a dummy gate pattern on a substrate; forming an insulation interlayer on the dummy gate pattern such that the dummy gate pattern is covered with the insulation interlayer; polishing the insulation interlayer to expose a top surface of the dummy gate pattern; selectively removing the dummy gate pattern to form a trench on the substrate, the trench exposing the gate insulation pattern; forming a gate spacer on an inner sidewall of the trench and on a portion of the gate insulation pattern to reduce a width of the exposed gate insulation pattern; filling the trench with a metal to form a metal layer on the exposed gate insulation pattern; and polishing the metal layer such that the metal remains in the trench.