Patent ID: 6288941
Filing Date: 2001-09-11
Classification: G11C

Abstract:
An electrically erasable semiconductor nonvolatile memory device comprising:a plurality of nonvolatile memory cells formed in a semiconductor substrate and arranged in an array of rows and columns, each of said memory cells including a field-effect transistor element having a floating gate, a control gate and drain and source regions;word line conductors extending in a first direction substantially parallel with said rows; anddata line conductors extending in a second direction substantially parallel with said columns, the control gates and drain regions of said memory cells being connected with said word line and data line conductors, respectively, to form said array, said word line conductors and said data line conductors being responsive to a row decoder and a column decoder, respectively, and said array of nonvolatile memory cells consisting of a plurality of memory blocks,wherein each of said memory blocks includes at least one word line conductor and the memory cells connected thereto and a common source conductor, each common source conductor being connected to a corresponding one of plural erasing circuits and being connected to apply an erasing voltage, independently of said row decoder, to the source regions of the field-effect transistor elements of the memory cells in a corresponding one of said memory blocks and extending in said first direction substantially parallel with said word line conductors, each common source conductor belonging to a respective one of said memory blocks and serving, in an erasing operation, as a path for electrons to be extracted from the floating gates of the field-effect transistor elements of the memory cells in the memory block with which the common source conductor corresponds to, and each word line conductor belonging to a respective one of said memory blocks, andwherein simultaneous erasure of the memory cells connected to said at least one word line in a selected memory block is effected by providing a potential difference between that of said common source conductor, supplied with the erasing voltage, and each word line, supplied with a predetermined voltage, corresponding to that memory block and keeping said data line conductors from being supplied with a power potential, in an erase mode.