Patent ID: 9136872
Filing Date: 2015-09-15
Classification: H03M

Abstract:
1. A memory system, comprising: an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after reading out data from the first memory array and data read out from the second memory array according to a second method, wherein the ECC engine is configured to perform the first method and the second method in response to a control signal having at least a first logic level, and an error correcting capability of the second method is greater than an error correcting capability of the first method; and an ECC control unit configured to generate the control signal at the first logic level if a value indicating a deterioration state of the first memory array is less than a first reference value, the first logic level of the control signal corresponding to a flag indicating to which of the first memory array and the second memory array memory array data is to be programmed; and if the value indicating the deterioration state of the first memory array is greater than a second reference value, then the ECC control unit is configured to generate the control signal at a second logic level different from the first logic level, and in response to the second logic level of the control signal, the ECC engine sets the second method to be the same as the first method.