Patent ID: 6316962
Filing Date: 2001-11-13
Classification: G06F,H03K

Abstract:
A reversible adiabatic logic circuit comprising:a forward logic function circuit driven by a first clock among power supply clocks having at least 8 phases during a time period, the forward logic function circuit for computing a forward logic function of a complementary dual rail using one or more NMOS transistors and determining the charging path of an output node;a reverse logic function circuit driven by a second clock, at least 2 phases behind the first clock, the reverse logic function circuit for computing a reverse logic function of the complementary dual rail using one or more NMOS transistors and determining the discharging path of the output node; anda compensation circuit for compensating a decrease in the swing of the output node due to threshold voltages of the NMOS transistors in the forward logic function circuit and the reverse logic function circuit.