Patent ID: 6391669
Filing Date: 2002-05-21
Classification: H01L,H05K,Y10T

Abstract:
A method of non-destructively electrically testing the integrity of a multilayer electrical device; said method comprising:(a) locating a first electrical test structure at one surface of said multilayer device; and (b) locating a second electrical test structure at an opposite surface of said multilayer device, having said second electrical test structure in electrical communication with said first electrical test structure, whereby application of an electrical potential between said first and second electrical test structures facilitates detection and assessment of potential electrical interface failure sites in said multilayer device; at least two spaced vias extend through said multilayer device between said one and said opposite surfaces; said first electrical test structure comprising a first test pad electrically communicating with a first said via at said one surface and a second test pad electrically communicating with a second said via at said one surface; and said second electrical test structure comprising a test pad in common electrical communication with said first and second vias at said opposite surface of said multilayer electrical device; said vias each comprising a via stack extending through said multilayer electrical device, and means for subjecting said device to thermal cycling stressing the interfaces of the layers of said device for detection of potentially latent defects tending to produce electrical opens and failure of the device.