Patent ID: 7085972
Filing Date: 2006-08-01
Classification: G11C

Abstract:
1. System for testing a group of functionally independent memories and for replacing failing memory words of said group of functionally independent memories by redundant memory words, comprising: (a) a redundancy means including at least one array of redundant memory words and address registers connected to said at least one array of redundant memory words for storing and retrieving addresses of failing memory words; (b) a test means including a test data output, a test address output, and a read/write output for providing test data, test addresses and read/write signals to each memory of said group of functionally independent memories; (c) a group of first multiplexers for respectively either connecting said test data output, said test address output, and said read/write output of said test means or a respective functional data/address/read/write input to a respective data/address/read/write input of an associated memory and to a respective data/address/read/write input of said at least one array of redundant memory words; and (d) a group of second multiplexers for respectively either connecting a respective memory data output of an associated memory or a respective redundancy data output of said at least one array of redundant memory words to a data output of a respective second multiplexer, wherein said data output of each second multiplexer is connectable to a data input of said test means for receiving data from each memory of said group of functionally independent memories.