Patent ID: 7388908
Filing Date: 2008-06-17
Classification: H04L

Abstract:
1. A system comprising: an electronic device formed on a first semiconductor substrate; an external device formed on a second semiconductor substrate; an inter-chip high-speed bus wire trace, wherein the inter-chip high-speed bus wire trace electrically couples an output pad of the first semiconductor substrate to an input pad of the second semiconductor substrate; a 1-bit sampling circuit coupled to the input pad and operative to convert an analog signal received on the input pad to a stream of 1-bit digital sample values wherein the 1-bit sampling circuit produces its stream of 1-bit digital sample values at a specified sampling rate; and an equalizer that processes the stream of 1-bit digital sample values using a feed forward filter channel that includes a multiplier free adder-based circuit that combines a set of equalizer coefficients with one or more of the 1-bit digital sample values to produce a recovered signal sequence, wherein the recovered signal sequence has a reduced sample rate that is at least two times less than the specified sampling rate, wherein the equalizer is characterized in that its coefficients are selected to reduce a measure of a residual error signal.