Patent ID: 7444487
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A semiconductor apparatus comprising a processor core for performing computation, an external bus interface unit for connecting to an external bus, a memory interface unit for controlling access to a local memory, and an internal bus that interconnects the processor core, the external bus interface unit, and the memory interface unit, the external bus interface unit comprising: an access control unit for receiving an access request conveyed through the external bus, an access judging unit connected to the access control unit for judging whether the access request is to be honored or rejected, and an access judging control unit for updating the contents of the access judging unit as requested by the processor core, wherein upon receiving the access request conveyed through the external bus, the access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit, an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.