Patent ID: 9076505
Filing Date: 2015-07-07
Classification: G11C,H01L

Abstract:
1. A memory device comprising: a driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver circuit, and a second word line driver circuit; a first memory cell array including a first bit line and a first word line; a second memory cell array including a second bit line and a second word line; a third memory cell array including a third bit line and the second word line; and a fourth memory cell array including a fourth bit line and the first word line with the first memory cell array, wherein: each of the first to fourth memory cell arrays overlaps with the driver circuit, the first bit line driver circuit and the second bit line driver circuit are diagonally opposite to each other in the driver circuit, the first word line driver circuit and the second word line driver circuit are diagonally opposite to each other in driver circuit, the first and second bit line driver circuits and the first and second word line driver circuits are arranged so that in data writing, a signal is transmitted across the first bit line driver circuit toward a boundary between the first word line driver circuit and the first bit line driver circuit, a signal is transmitted across the second bit line driver circuit toward a boundary between the second word line driver circuit and the second bit line driver circuit, a signal is transmitted across the first word line driver circuit toward a boundary between the first bit line driver circuit and the first word line driver circuit, and a signal is transmitted across the second word line driver circuit toward a boundary between the second bit line driver circuit and the second word line driver circuit, the first word line is electrically connected to the second word line driver circuit via a connection point provided along a boundary between the first memory cell array and the fourth memory cell array, the second word line is electrically connected to the first word line driver circuit via a connection point provided along a boundary between the second memory cell array and the third memory cell array, the first bit line and the second bit line are electrically connected to the first bit line driver circuit via connection points provided along a boundary between the first memory cell array and the second memory cell array, and the third bit line and the fourth bit line are electrically connected to the second bit line driver circuit via connection points provided along a boundary between the third memory cell array and the fourth memory cell array.