Patent ID: 8928060
Filing Date: 2015-01-06
Classification: H01L

Abstract:
1. A memory device comprising: a first pair of split gate flash memory cells disposed over a semiconductor body, and respectively comprising a stacked gate laterally separated in a first direction from an erase gate by a spacer, a first shared common source region disposed in the semiconductor body at a first location between the stacked gates of the first pair of split gate flash memory cells, wherein the erase gates of the first pair of split gate flash memory cells comprise separate erase gates disposed over opposing sides of the first shared common source region; and a first contact vertically extending between the erase gates of the first pair of split gate flash memory cells to the first shared common source region; a second pair of split gate flash memory cells disposed apart from the first pair of split gate flash memory cells in a second direction perpendicular to the first direction, and respectively comprising a stacked gate laterally separated in the first direction from an erase gate by a spacer; a second shared common source region disposed in the semiconductor body at a second location between the stacked gates of the second pair of split gate flash memory cells, wherein the erase gates of the second pair of split gate flash memory cells comprise separate erase gates disposed over opposing sides of the second shared common source; a second contact vertically extending between the erase gates of the second pair of split gate flash memory cells to the second shared common source region; and a conductive layer disposed over the semiconductor body that couples the first contact to the second contact of the split gate flash memory cells.