Patent ID: 9086451
Filing Date: 2015-07-21
Classification: G01R

Abstract:
1. A semiconductor integrated circuit comprising: a circuit-under-test; a test access port corresponding to a JTAG interface; a test access port controller performing control functions of JTAG based on signals from the test access port; a built-in self-test circuit conducting a test on the circuit-under-test under control of the test access port controller; a power-on self-test circuit interposed between an external pin group corresponding to the test access port and the test access port controller and conducting a power-on self test on the circuit-under-test; and a pattern generation circuit capable of generating test patterns used to self-diagnose the circuit-under-test, wherein the power-on self-test circuit includes: a selection circuit selecting an output of the pattern generation circuit, instead of the external pin group corresponding to the test access port, when a self-diagnosis execution signal is asserted to supply a test pattern generated by the pattern generation circuit to the built-in self-test circuit; and a comparator circuit comparing a test result of the circuit-under-test from the built-in self-test circuit with an expected value generated by the pattern generation circuit.