Patent ID: 8730718
Filing Date: 2014-05-20
Classification: G11C,H01L

Abstract:
1. A memory array for an integrated circuit comprising a plurality of memory cells, each of the memory cells comprising: a plurality of diffusion regions in a substrate including a first diffusion region and a second diffusion region; a material capable of holding a logic state; and first and second access transistors coupled to the material, the first and second access transistors to access the logic state of the material, the first and second access transistors being independently selectable by two word lines of a plurality of word lines parallel to a first dimension, wherein the first access transistor includes a channel terminal sharing the first diffusion region with a first additional access transistor of a second memory cell of the memory cells, and the second access transistor includes a channel terminal sharing the second diffusion region with a second additional access transistor of a third memory cell of the memory cells.