Patent ID: 6026042
Filing Date: 2000-02-15
Classification: G11C

Abstract:
A memory circuit comprising:an array of memory cells having rows and columns;at least one word line connected to a row of memory cells;a plurality of first digit lines associated with each said word line, each of said digit lines being connected to a column of memory cells;a decoder for generating an activate signal for said word line, said activate signal having a propagation time from a front edge to a back edge of said word line;a plurality of sense amplifiers respectively connected to said digit lines;a dummy tracking word line for propagating a tracking signal, said tracking signal being generated in response to generation of said activate signal and tracking said propagation time of said activate signal, said dummy tracking word line having multiple taps, each tap being coupled to at least one sense amplifier, said taps sequentially activating said sense amplifiers in accordance with said tracking signal propagation along said dummy tracking word line.