Patent ID: 7596175
Filing Date: 2009-09-29
Classification: H04L

Abstract:
1. A receiver comprising: a sampler having a plurality of sampler input terminals, including at least one sampler data terminal to receive an input data stream, a sampler clock terminal to receive a clock signal, and a sampler voltage reference terminal to receive a reference voltage; and at least one sampler output terminal; wherein the sampler is adapted to sample the input data stream according to the clock signal and with respect to the reference voltage to produce a sampled data stream on the at least one sampler output terminal; a multiplexer having a first multiplexer input terminal connected to the at least one sampler output terminal; a second multiplexer input terminal connected to a source of expected data; and a multiplexer output terminal adapted to provide alternatively one of the sampled data stream and the expected data; and a feedback circuit having a plurality of delay elements operatively connected to the multiplexer output terminal, each delay element to provide at least one historical bit from the sampled data stream or from the expected data source from the multiplexer; and a plurality of data-weighting circuits, each data-weighting circuit connected between one of the plurality of delay elements and at least one of the plurality of sampler input terminals and adapted to provide a weighted feedback based on the at least one historical bit from the corresponding delay element.