Patent ID: 6230114
Filing Date: 2001-05-08
Classification: G06F

Abstract:
A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a pipeline, and an accompanying user program to be executed on the target processor, the design system comprising:a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; andan interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator,wherein the processor simulator includes a mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry,wherein the analyzed version of the user program is obtained by decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects, such that executing the analyzed version of the user program produces timing information incorporating target processor instruction timing and pipeline effects.