Patent ID: 6199126
Filing Date: 2001-03-06
Classification: G06F

Abstract:
A data processing system comprising:a processor for executing program instructions, having an address output for issuing addresses to first address locations and an instruction input for receiving uncompressed program instructions;a memory having an address input and an output, storing variably sized blocks of compressed program instructions which have been formed from fixed size blocks of uncompressed program instructions, the variably sized blocks of compressed program instructions being stored at second address locations in the memory;an index table coupled to the address output of the processor and coupled to the address input of the memory, having a map for causing a translation of the first address location addresses received from the processor, into the second address location addresses output to the memory;a decode table having an input coupled to the output of the memory and having an output, including a map for decoding the variably sized blocks of compressed program instructions received from the memory, into the fixed size blocks of uncompressed program instructions; andan instruction buffer having an input coupled to the decode table and an output coupled to the instruction input of the processor, the instruction buffer receiving the fixed size blocks of uncompressed program instructions from the decode table;whereby instructions already present in the instruction buffer can be passed to the processor with a shorter delay from the time of request by the processor than other instructions that must be fetched from the memory as part of a block of compressed program instructions.