Patent ID: 6150073
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A degradation-free, low-permissivity dielectric patterning process for damascene, the process comprising:providing a substrate, wherein the substrate has a dielectric layer and a via plug formed on it;forming an inter-metal dielectric layer on the dielectric layer, wherein the inter-metal dielectric layer has a thickness;forming an insulating layer on the inter-metal dielectric layer for protecting the inter-metal dielectric layer from being damaged by a photoresist removal process and a post-chemical mechanical polishing cleaning process, wherein the insulating layer has a thickness and the insulating layer is thinner than the inter-metal dielectric layer;forming a hard mask layer on the insulating layer, wherein the hard mask layer has a thickness;forming and patterning a photoresist layer on the hard mask layer to expose a portion of the hard mask layer;performing an etching process on the hard mask layer until the insulating layer is exposed to form a shallow trench;performing oxygen plasma ashing and wet chemical cleaning to remove the photoresist layer;performing an etching process on the insulating layer and the inter-metal dielectric layer by using the hard mask layer as a mask to form a metal line trench and expose the via plug;forming a glue/barrier layer conformal to the metal line trench and the hard mask layer;forming a metal layer on the glue/barrier layer to fill the metal line trench;performing chemical mechanical polishing on the metal layer to expose the insulating layer and form a metal line in the shallow trench, wherein the metal line is electrically connected to the via plug; andperforming post-chemical mechanical polishing cleaning.