Patent ID: 7882461
Filing Date: 2011-02-01
Classification: G06F

Abstract:
1. A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design, the method comprising: identifying, with one or more processors associated with one or more computer systems, a plurality of blocks in the synthesized netlist as idle candidate blocks; determining, for each idle candidate block, a disable candidate function with the one or more processors associated with one or more computer systems which causes a corresponding sequential element in the idle candidate block to be in an idle state; generating, with the one or more processors associated with one or more computer systems, a bipartite graph comprising a first set, a second set, and a plurality of edges, the first set including each of the disable candidate functions, the second set including each of the corresponding sequential elements; and selecting, with the one or more processors associated with one or more computer systems, a subset of the disable candidate functions to be implemented with clock gates in a clock gating structure optimized for power savings, the selected subset enabling an optimal power savings in the IC design.