Patent ID: 6784814
Filing Date: 2004-08-31
Classification: H03M

Abstract:
A method of correcting error in a multiple stage analog to digital converter over a plurality of clock cycles, the method comprising:providing a digital signal from a first stage of the multiple stage analog to digital converter based on an input signal to the first stage of the multiple stage analog to digital converter; providing an analog signal from the first stage of the multiple stage analog to digital converter based on the first stage digital signal; subtracting the analog signal provided by the first stage of the multiple stage analog to digital converter from the input signal resulting in a first stage analog residue signal; amplifying the resultant first stage analog residue signal and applying the amplified first stage analog residue signal to a second stage of one or more subsequent stages of the multiple stage analog to digital converter; providing a first stage digital residue signal from the one or more subsequent stages based on the amplified first stage analog-residue signal applied thereto; continuously, over the plurality of clock cycles, averaging the first stage digital residue signal with a pseudorandom sequence resulting in an averaged first stage digital residue correction signal; subtracting the averaged first stage digital residue correction signal from a sum of the first stage digital residue signal and the first stage digital signal of the multiple stage analog to digital converter for use in providing a non-linearity corrected digital output signal; and continuously, over the plurality of clock cycles, averaging the non-linearity corrected digital output signal to correct for gain error.