Patent ID: 8995839
Filing Date: 2015-03-31
Classification: G06F,H03M,H04B

Abstract:
1. A gearbox integrated circuit (IC) comprising: a first electrical interface having N input terminals for inputting N electrical data signals having a data rate of X gigabits per second (Gbps) and N output terminals for outputting N electrical data signals having a data rate of X Gbps, wherein N is a positive integer that is equal to or greater than two and X is a positive number that is equal to or greater than one; phase-alignment circuitry for phase-aligning pairs of the N inputted electrical data signals to produce N/2 pairs of phase-aligned electrical data signals; first rate conversion circuitry that receives the N/2 phase-aligned pairs of electrical data signals and converts each of the N/2 phase-aligned pairs into a serialized electrical data signal having a data rate of 2X Gbps; a second electrical interface having N/2 output terminals and N/2 input terminals, the serialized 2X Gbps electrical data signals being outputted from the gearbox IC via the N/2 output terminals of the second electrical interface; and second rate conversion circuitry that receives N/2 2X Gbps electrical data signals inputted to the gearbox IC via the N/2 input terminals of the second electrical interface and that converts the N/2 2X Gbps electrical data signals into N electrical data signals having a data rate of X Gbps that are outputted from the gearbox IC via the N output terminals of the first electrical interface.