Patent ID: 6587005
Filing Date: 2003-07-01
Classification: H03L

Abstract:
A phase locked loop (PLL) circuit comprising:a reference frequency generator for generating a reference frequency signal having a reference frequency; a voltage controlled oscillator (VCO) including first and second variable capacitances, said VCO oscillating at an oscillation frequency based on said first and second variable capacitances; a first frequency divider for dividing said oscillation frequency by a first number to output a first frequency signal; a phase comparator for comparing a phase of said first frequency signal against a phase of said reference frequency signal to output a comparison result signal; a tune signal generation section for receiving said comparison result signal to output a tune signal, said tune signal controlling said first variable capacitance; and a frequency control unit for generating a control signal controlling said second variable capacitances; said frequency control unit detecting a deviation of said oscillation frequency from a normal oscillation frequency based on said tune signal, said first number and said reference frequency, said frequency control unit correcting said control signal based on said detected deviation.