Patent ID: 6138210
Filing Date: 2000-10-24
Classification: G06F

Abstract:
A memory circuit for storing a plurality of method frames, each of said method frames containing a plurality of frame components, said memory circuit comprising:a first stack configured to store a first frame component of a first method frame, wherein said first method frame is included in said plurality of method frames, and a second frame component of a second method frame, wherein said second method frame also is included in said plurality of method frames,wherein said first frame component of said first method frame has a first characteristic with respect to said first method frame; anda second stack configured to store a second frame component of said first method frame and a first frame component of said second method frame,wherein said first frame component of said second method frame has a first characteristic with respect to said second method frame; andsaid first characteristic with respect to said first method frame and said first characteristic with respect to said second method frame are a same characteristic.