Patent ID: 7092289
Filing Date: 2006-08-15
Classification: G11C

Abstract:
1. A flash memory, comprising: a flash memory array, including: a content addressable memory array coupled to the redundancy information block of the plurality of array planes to receive therefrom the defect addresses, and also being coupled to receive a logical signal from an external device for comparison with the defect addresses stored in the content addressable memory array; a memory array coupled to the redundancy information block of the plurality of array planes to receive therefrom the substitute addresses, and also having word lines coupled to respective match lines of the content addressable memory array, wherein in response to activation of one of the match lines, the memory array outputs a substitute address signal representing one of the substitute addresses stored in a row corresponding to the activated match line; and multiplexing circuitry connected to select between the logical address signal and the substitute address signal as a physical address signal, the multiplexing circuitry providing the physical address signal for selection of a memory cell being accessed.