Patent ID: 6141675
Filing Date: 2000-10-31
Classification: G06F,G06T

Abstract:
A method of compiling instructions for a processor, said processor being a very-long-instruction-word processor, wherein said processor comprises:a plurality of input registers, each respective one thereof being capable of supplying a respective one of a plurality of input data of M bits wide; anda destination register capable of storing output data of M bits wide; andwherein the method comprises:determining a set of operations for being executed in parallel by the processor on the plurality of input data, the set of operations include at least one multimedia-specific operation;determining that at least a specific one of the input data comprises specific multiple operand data, each N bits wide, wherein N is smaller than M;determining that the specific multiple operand data be supplied via a specific one of the input registers; anddetermining that a result per operation involving any of the N bit wide operand data be stored in the destination register as an N bit wide output data.