Patent ID: 8455308
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, said method comprising the steps of: forming a shallow trench isolation layer around a semiconductor substrate; growing a first epitaxial layer on said semiconductor substrate; growing a second epitaxial layer on said first epitaxial layer; forming a gate on said second epitaxial layer; forming a spacer disposed around said gate and on said second epitaxial layer; recessing said semiconductor substrate, first epitaxial layer and second epitaxial layer; removing at least a portion of said first epitaxial layer to create a void between said substrate and said second epitaxial layer; filling said void with a dielectric material; etching back at least a portion of said dielectric material; growing a semiconductor layer around said dielectric material; forming a source and drain junction within said semiconductor layer; and forming an extension to said gate wherein said extension is surrounded by said spacer.