Patent ID: 6815231
Filing Date: 2004-11-09
Classification: G11C,H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:forming nonvolatile semiconductor memories whose memory cells have respectively a double-layer gate structure having a floating gate and a control gate on a semiconductor wafer; selecting a plurality of memory cells for test; applying, for a first period of time, a predetermined voltage to the control gate electrode of each of said memory cells for test in a pulsed manner or a DC manner for continuous write operations without erase operations; measuring a first memory threshold voltage of the floating gate electrode of each of said memory cells for test; leaving said memory cells for test as is with no applied voltage during a second period of time; measuring a second memory threshold voltage of the floating gate electrode of each of said memory cells for test so as to obtain a memory threshold voltage variation from the first memory threshold voltage after said second period of time; determining, for each of said memory cells for test that has not obtained a saturated threshold voltage, a lower limit of the memory threshold voltage, the lower limit of the memory threshold voltage being derived from measurements of said second memory threshold voltage which have an approximately zero memory threshold voltage variation; measuring the first memory threshold voltage of respective memory cells having said double-layer gate structure formed on manufactured semiconductor wafers in a manufacturing process; and judging semiconductor wafers carrying memory cells whose measured first threshold voltages are not lower than said lower limit of memory threshold voltage to be nondefective.