Patent ID: 6093619
Filing Date: 2000-07-25
Classification: H01L

Abstract:
A method of forming a contact in the fabrication of an integrated circuit device comprising:providing a pad oxide layer over the surface of a semiconductor substrate;depositing a first silicon nitride layer over said pad oxide layer;etching an opening in said first silicon nitride and said pad oxide layers where they are not covered by a mask;etching into said semiconductor substrate underlying said opening to form a shallow trench;depositing an oxide material over the surface of said first silicon nitride layer and within said shallow trench;planarizing said oxide material to said surface of said first silicon nitride layer wherein said oxide material forms a shallow trench isolation (STI) region;removing said first silicon nitride layer whereby said STI protrudes above said pad oxide layer;removing said pad oxide layer whereby the corners of said STI above said semiconductor substrate are also removed;forming a sacrificial oxide layer on the surface of said semiconductor substrate;depositing a second silicon nitride layer overlying said sacrificial oxide layer;etching away said second silicon nitride layer to leave silicon nitride spacers filling in and rounding said corners of said STI;thereafter removing said sacrificial oxide layer;forming a gate electrode on the surface of said semiconductor substrate adjacent to said STI;forming a source/drain region in said semiconductor substrate adjacent to said gate electrode and adjacent to said STI;covering said gate electrode and said STI with an insulating layer;etching an opening through said insulating layer to said source/drain region wherein said silicon nitride spacer at said corner of said STI prevents etching of said STI; andfilling said opening with a conducting layer to complete said formation of said contact in said fabrication of said integrated circuit device.