Patent ID: 6137297
Filing Date: 2000-10-24
Classification: G01R,Y10T

Abstract:
An interface between terminals on an integrated circuit testing device and corresponding terminals on an integrated circuit to be tested and having a predetermined pattern of test access pads, comprisinga printed circuit board,a first plurality of conducting paths on said printed circuit board having test device ends configured for contacting ones of the terminals on the integrated circuit testing device and opposing ends,a floppy substrate,a second plurality of conducting paths on said floppy substrate having printed circuit board ends disposed for contact with ones of said opposing ends of said first plurality of conducting paths and having opposing ends,a self supporting diaphragm,a third plurality of conducting paths on said self supporting diaphragm having floppy substrate ends disposed for contact with ones of said opposing ends of said second plurality of conducting paths and having opposing ends,probe members extending from said self supporting diaphragm in a pattern corresponding to the predetermined pattern of test access pads and being connected to ones of said third plurality of conducting paths opposing ends, andresilient adhesive means extending between said printed circuit board and said self supporting diaphragm.