Patent ID: 7969169
Filing Date: 2011-06-28
Classification: G01R,H01L

Abstract:
1. A semiconductor integrated circuit wafer comprising: a plurality of semiconductor integrated circuit regions each of which includes a semiconductor integrated circuit formed thereon; a scribe region which separates said semiconductor integrated circuit regions adjacent to each other; a build in self test (BIST) circuit which is provided in said scribe region to inspect said semiconductor integrated circuit; a connection wiring which is formed ranging from said scribe region to said semiconductor integrated circuit region and connects said semiconductor integrated circuit and said BIST circuit; a BIST switching signal input pad which is provided in said semiconductor integrated circuit region; and a BIST switching circuit which is provided in said semiconductor integrated circuit region and is driven by a driving signal input from said BIST switching signal input pad, said BIST switching circuit including: an input-output pad which connects with said semiconductor integrated circuit through a circuit wiring; and a switch element which is provided at a middle position of said circuit wiring and is driven by said driving signal input from said BIST switching signal input pad.