Patent ID: 6243297
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A semiconductor storage device, comprising:a plurality of word lines;a plurality of first control lines;a plurality of second control lines;a memory cell array that has a plurality of memory cells, each of said plurality of memory cells comprising a control gate, a drain terminal and a source terminal, wherein said control gate is connected to a respective one of said word lines, wherein said drain terminal is connected to a respective one of said first control lines, and wherein said source terminal is connected to a respective one of said second control lines;a word line drive circuit that drives said word lines;a write control circuit that drives said first control lines;a data write circuit that drives said second control lines when data is being written into a respective one of said memory cells; anda delay circuit that discharges the voltage on said second control lines after the voltage on said first control lines is discharged to a predetermined threshold level when said data writing is finished.