Patent ID: 6961338
Filing Date: 2005-11-01
Classification: H04N

Abstract:
1. A demultiplexer for separating desired packets for output from an input digital data which has different format packets multiplexed in a given manner, comprising: a data input for receiving the input digital data; a shift register for storing and transferring the input digital data received at the data input; a group of registers for extracting and storing headers of the packets from the input digital data stored in the shift register; a calculating unit for analyzing the headers of the packets stored in the group of registers; an output destination determining unit for determining a destination of the packets from a packet identifier which is contained in the headers of the packets stored in the group of registers; a separator arranged responsive to a result of the calculating action of the calculating unit and an output of the output destination determining unit for separating the desired packets from the input digital data received from the shift register; a command memory for storing micro-codes provided for processing each multiplexing format including at least a digital video broadcasting (DVB) format, a digital satellite system (DSS) format, and a digital versatile disc (DVD) format; a counter for determining execution addresses of the micro-codes stored in the command memory; a controller for controlling the shift register, group of registers, output destination determining unit, calculating unit, and a system clock controller in accordance with the micro-codes read out from the command memory by the execution addresses determined by the counter; and said system clock controller extracting timing data from the input digital data stored in the shift register and controlling the system clock with the timing data.