Patent ID: 8929115
Filing Date: 2015-01-06
Classification: G11C,H01L

Abstract:
1. A content addressable memory (CAM), comprising: a plurality of CAM cells arranged in an array including columns and rows; each CAM cell comprising a first SRAM cell, a second SRAM cell and a comparator circuit, the first and second SRAM cells having a horizontal topology layout with a longer side edge and a shorter side edge; a plurality of match lines, each match line extending across the array and coupled to plural CAM cells, each match line oriented in a first direction that is parallel to the shorter side edge of the horizontal topology for the first and second SRAM cells in said plural CAM cells; a plurality of bit lines, each bit line extending across the array and coupled to plural CAM cells, each bit line oriented in a second direction that is both perpendicular to the first direction and parallel to the longer side edge of the horizontal topology layout for the first and second SRAM cells in said plural CAM cells; wherein the plurality of bit lines comprise: