Patent ID: 6522585
Filing Date: 2003-02-18
Classification: G11C

Abstract:
A method of treating erased memory cells in a non-volatile memory having a plurality of memory cells forming a virtual ground array comprised of one or more rows of said cells, each of said memory cells capable of storing a plurality of data states and comprising a first source/drain region and a second source/drain region, wherein the source/drain regions are connected to bit lines perpendicular to said rows, the method comprising:sensing the presence of a memory cell from said plurality of memory cells erased to a state other than one of said plurality of data states; and subsequent to sensing the presence of said memory cell erased to a state other than one of said plurality of data states, simultaneously performing a soft programming operation on a pair of memory cells consisting of said memory cell erased to a state other than one of said plurality of data states and the memory cell with which said memory cell erased to a state other than one of said plurality of data states shares a bit line to which both of said pair of memory cells have their respective second source/drain region connected.