Patent ID: 6657243
Filing Date: 2003-12-02
Classification: H01L,Y10S

Abstract:
A semiconductor device, comprising:an SRAM section which includes a plurality of memory cells, wherein each of the memory cells comprises: a first well of a primary conductivity type, a second well of a secondary conductivity type, a first load transistor and a second load transistor, a first driver transistor and a second driver transistor, a first access transistor and a second access transistor, wherein the first and second load transistors are located on the first well, wherein the first and second driver transistors and the first and second access transistors are located on the second well; and a third well of the primary conductivity type, wherein a bottom section of the third well is located at a position deeper than bottom sections of the first and second wells, wherein the third well is connected to the first well in each of the memory cells, wherein: each of the memory cells has first and second gate-gate electrode layeres, first and second drain-drain connecting layers, and first and second drain-gate connecting layers; the first gate-gate electrode layer includes gate electrodes of the first load transistor and the first driver transistor; the second gate-gate electrode layer includes gate electrodes of the second load transistor and the second driver transistor; the first drain-drain connecting layer connects a drain of the first load transistor with a drain of the first driver transistor; the second drain-drain connecting layer connects a drain of the second load transistor with a drain of the second driver transistor; the first and second gate-gate electrode layers are located between the first and second drain-drain connecting layers; the first drain-gate connecting layer connects the first drain-drain connecting layer with the second gate-gate electrode layer; the second drain-gate connecting layer connects the second drain-drain connecting layer with the first gate-gate electrode layer; and each of the drain-gate connecting layers, the drain-drain connecting layers, and the gate-gate electrode layers is located in different layers.