Patent ID: 7263101
Filing Date: 2007-08-28
Classification: H04L

Abstract:
1. A host digital terminal (HDT) for performing backbone functions to a subscriber access network, while the network side of the host digital terminal is connected to a plurality of data transfer networks and the other side of the host digital terminal is connected to a plurality of optical network units (ONUs), said host digital terminal comprising: a host digital terminal switching/clock unit (HSCU) for outputting an asynchronous transfer mode (ATM) signal, after an asynchronous transfer mode (ATM) serial signal is converted into an ATM parallel signal, an ATM switching is performed according to transmission information of the ATM parallel signal, and the ATM parallel signal is re-converted into the ATM serial signal, and for outputting a synchronous transfer mode (STM) signal, after the STM dependent signal is received, and a virtual channel (VC) cross connection is performed; an ATM network interface unit (ANIU), connected to the data transfer network, for receiving a signal transmitted from the data transfer network, extracting an ATM signal from the transmitted signal, performing an inverse-multiplexing and each of ANIU cell processes to the extracted ATM signal, converting the extracted ATM signal to the ATM serial signal, and transmitting the ATM serial signal to the HSCU, sequentially; a host digital terminal metwork interface unit (HNIU), connected to plurality of optical network units (ONUs), for converting the ATM serial signal transmitted from the host digital terminal switching/clock unit (HSCU) to the ATM parallel signal, performing a multiplexing and each of host digital terminal cell processes to the ATM parallel signal, transmitting the ATM parallel signal to the connected ONUs, sequentially; a host digital terminal main control unit (HMCU) for performing control management functions for controlling mutual interactions among the units of the host digital terminal and data flows; and a shelf comprising a common bus to exchange all of data among the units, each one of the units being plugged in the shelf; the common bus including: