Patent ID: 7986754
Filing Date: 2011-07-26
Classification: H03L

Abstract:
1. An apparatus comprising: a first circuit configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value, wherein said seed value is selected in response to a first control signal; a second circuit configured to generate a second control signal in response to said demodulated signal and a first clock signal; and a third circuit configured to generate said first control signal in response to (i) said second control signal, (ii) a compensation signal, (iii) said first control signal, (iv) a carrier signal, and (v) a second clock signal, wherein (a) generation of said first control signal comprises adding said second control signal, said compensation signal, said carrier signal and a latched version of said first control signal, (b) generation of said latched version of said first control signal comprises sampling said first control signal in response to said second clock signal, and (c) said compensation signal is used to maintain a frequency of said demodulated signal independently of variation in frequency of said second clock signal.