Patent ID: 7180769
Filing Date: 2007-02-20
Classification: G11C

Abstract:
1. A method to improve a segment of a segmented word line array, comprising: providing a current source-and-sink that drives, and is driven by, parallel source and return lines respectively; providing read and write word lines that are orthogonal to said source and return lines; providing a number of bit lines that are parallel to said source and return lines and disposing each bit line to pass directly over a memory element having a bottom electrode, whereby said segment contains said number of corresponding memory elements; providing one isolation transistor for each one of said memory elements, each isolation transistor having a first source, a first gate, and a first drain; connecting each first source to its corresponding bottom electrode; connecting each first gate to said read word line; connecting each first drain to ground; providing a word line selection transistor having a second source, a second gate, and a second drain; connecting said second source to said source line; connecting said second gate to said write word line; and connecting said second drain to said return line through a line that passes directly over all of said corresponding memory elements prior to contacting said return line, thereby isolating said segment from any loading by any other segment of said array.