Patent ID: 7098511
Filing Date: 2006-08-29
Classification: H01L

Abstract:
1. An ESD protection circuit applied to an IC with power-down-mode operation, comprising: an input circuit, which comprises: an output circuit, which comprises: an ESD bus line connected to the source and the gate of said input PMOS and still connected to the source of said output PMOS, the source of said control PMOS, and said pre-driver circuit, wherein said pre-driver circuit is coupled to said ESD bus line instead of said VDD power line for obtaining power so as to prevent leakage current induced from said pre-driver circuit to said VDD power line; a first ESD clamp circuit connected between said VSS power line and said ESD bus line; a diode forward connected between said VDD power line and said ESD bus line to avoid leakage current induced from said input pad to said VDD power line via said input PMOS when said VDD power line is grounded under power-down-mode operation, and still to avoid positive voltage at said input pad charging to said VDD power line through said input PMOS when said VDD power line is floating under power-down-mode operation.