Patent ID: 6297674
Filing Date: 2001-10-02
Classification: G11C,H01L,H03K

Abstract:
A semiconductor integrated circuit comprising:a first p-channel FET having a gate controlled by a first input and having a source-drain path between a first operating potential point and a first node;a first n-channel FET having a gate controlled by a second input and having a source-drain path between said first node and a second node;a second n-channel FET having a source-drain path between said second node and a second operating potential point;a third n-channel FET having a source-drain path between said second node and a third operating potential point;a second p-channel FET having a gate controlled by said first input and having a source-drain path between a third node and a fourth node;a third p-channel FET having a source-drain path between said first operating potential point and said third node;a fourth p-channel FET having a source-drain path between a fourth operating potential point and said third node;a fourth n-channel FET having a source-drain path between said fourth node and said second operating potential point;a fifth p-channel FET having a gate controlled by said fourth node and having a source-drain path between said first operating potential point and a fifth node;a fifth n-channel FET having a gate controlled by said first node and having a source-drain path between said fifth node and said second operating potential point;a sixth p-channel FET having a gate controlled by said fifth node and having a source-drain path between said first operating potential point and a sixth node; anda sixth n-channel FET having a gate controlled by said fifth node and having a source-drain path between said sixth node and said second operating potential point;wherein a gate of said second n-channel FET is controlled by said sixth node;wherein a gate of said third n-channel FET is controlled by said fifth node;wherein a gate of said third p-channel FET is controlled by said sixth node; andwherein a gate of said fourth p-channel FET is controlled by said fifth node.