Patent ID: 7402499
Filing Date: 2008-07-22
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a gate insulating film, a gate electrode film and a stopper film on a semiconductor substrate sequentially; etching the stopper film, the gate electrode film, the gate insulating film and the semiconductor substrate, thereby forming a first element isolation trench having a first opening width and a second element isolation trench having a second opening width larger than the first opening width; burying an element isolation insulating film in the first element isolation trench so that the insulating film in the trench has a void formed in an upper part thereof; polishing the element isolation insulating film by a chemical mechanical polishing (CMP) process until an upper surface of the stopper film is reached, thereby opening the void; filling a coating type oxide film so that the film is buried in the void; and polishing the coating type oxide film by a chemical mechanical polishing (CMP) process until the upper surface of the stopper film is reached.