Patent ID: 6828852
Filing Date: 2004-12-07
Classification: G11C

Abstract:
An integrated circuit structure comprising:a signal wire; a first active shield line adjacent to, but removed from, said signal wire; a second active shield line adjacent to, but removed from, said signal wire a dynamic flip-flop having an output terminal connected to said signal wire wherein said dynamic flip-flop drives a pulse on said signal wire and said dynamic flip-flop has a clock-to-Q time delay characteristic; a first buffer having an output terminal connected to said first active shield line and an input terminal connected to a clock line wherein said first buffer has about said clock-to-Q time delay characteristic so that said first buffer asserts a signal on said first active shield line substantially simultaneous with said pulse; and a second buffer having an output terminal connected to said second active shield line and an input terminal connected to said clock line wherein said second buffer has about said clock-to-Q time delay characteristic so that said second buffer asserts a signal on said second active shield line substantially simultaneous with said pulse.