Patent ID: 6606700
Filing Date: 2003-08-12
Classification: G06F

Abstract:
An electronic circuit, characterized in that it includes:(a) a register file having first through third inputs and first through sixth outputs; (b) a first shifter receiving the first output of the register file; (c) a first multiplier receiving the second and third outputs of the register file and having an output; (d) a second multiplier receiving the fourth and fifth outputs of the register file and having an output; (e) a second shifter receiving the output of the first multiplier and having an output; (f) a third shifter receiving the output of the second multiplier and having an output; (g) a rounding multiplexer receiving the output of the first shifter and having an output; (h) a first adder receiving, at a first input, the output of the second shifter and having an output; (i) a first externally-controlled multiplexer receiving either a zero or the output of the third shifter, and applying an output to a second input of the first adder; (j) a second adder receiving the outputs of the rounding multiplexer and the first adder, and having an output which is fed back to the first input of the register file; (k) a third adder receiving the outputs of the third shifter and the sixth register output, and having an output which is fed back to the second input of the register file; (l) a first input storage element receiving the third output of the register file; (m) a second externally-controlled multiplexer receiving the output of the first input storage element, and the third output of the register file; (n) a third externally-controlled multiplexer receiving the second and fifth outputs of the register file; (o) a third multiplier receiving the outputs of the second and third externally-controlled multiplexers; (p) a fourth shifter receiving the output of the third multiplier; (q) a fourth adder receiving, at a first input, the output of the fourth shifter; (r) a first output storage element receiving the output of the fourth adder, the output of the first output storage element being applied to a second input of the fourth adder; (s) a fourth externally-controlled multiplexer receiving the output of the first input storage element and the fourth output of the register file; (t) a second input storage element receiving the output of the fourth externally-controlled multiplexer; (u) a fifth externally-controlled multiplexer receiving the output of the second input storage element and the fourth output of the register file; (v) a fourth multiplier receiving the output of the fifth externally-controlled multiplexer and the second output of the register file; (w) a fifth shifter receiving the output of the fourth multiplier; (x) a fifth adder receiving, at a first input, the output of the fifth shifter; (y) a second output storage element receiving the output of the fifth adder, the output of the first output storage element being applied to a first input of a sixth externally-controlled multiplexer, the sixth externally-controlled multiplexer, receiving the output of the fourth shifter at a second input, and the output of the sixth externally-controlled multiplexer being applied to a second input of the fifth adder.