Patent ID: 7668003
Filing Date: 2010-02-23
Classification: G11C,H01L

Abstract:
1. A memory circuit comprising: a memory cell comprising: a memory cell capacitor electrically connected to ground and a memory cell transistor, wherein said memory cell capacitor exhibits a first capacitance, and wherein said memory cell transistor is adapted to electrically connect said memory cell capacitor to a first bit line when a first word line is active; a reference cell comprising: two reference cell capacitors connected in series and electrically connected to a reference plate and a reference cell transistor, wherein said two reference cell capacitors connected in series exhibit a second capacitance that is approximately one half said first capacitance, wherein said reference cell transistor is adapted to electrically connect said two reference cell capacitors connected in series to a second bit line when a second word line is active, and wherein said reference plate is adapted to apply a first voltage to said reference cell capacitors, when said first word line and said second word line are inactive, and further to apply a second voltage level different from said first voltage level to said two reference cell capacitors, when said first word line is active; a precharge circuit adapted to precharge said first bit line and said second bit line to said first voltage level, when said first word line and said second word line are inactive; and a sense amplifier adapted to detect a potential difference between said first bit line and said second bit line, during a read operation, when said first word line and said second word line are active.