Patent ID: 6958935
Filing Date: 2005-10-25
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device including a plurality of data I/O pins, comprising: a memory cell array divided into a plurality of blocks; a data rate option selector for generating a data rate control signal according to a predetermined speed option; a block selector for generating a plurality of block selection signals to select a block of the memory cell array in response to a predetermined block selection address from column addresses introduced through the I/O pins and the data rate control signal; a column selection circuit for selecting a data line in response to a predetermined column selection address from the column addresses, the block selection signals and the data rate control signal and for outputting data of the memory cell array to the selected data line; and a data I/O controller for selecting a data line to input data to, or output data from, the column selection circuit in response to the block selection signals and the data rate control signal.