Patent ID: 6172529
Filing Date: 2001-01-09
Classification: H03K

Abstract:
A compound domino logic circuit, comprising:a first section and a second section of logic devices arranged in a parallel configuration, wherein each of said two sections includes:a precharge transistor connected to a first reference voltage, wherein said precharge transistor receives a clock input signal;one or more input transistors coupled between said precharge transistor and a second reference voltage, wherein each of said one or more input transistors receives a signal input; andan output node connected to said precharge transistor and at least one of said input transistors;an output logic gate connected to each of said output nodes of said first and second sections of logic devices to yield a signal output, wherein said output logic gate includes a plurality of transistors connected in series; andan adjustment transistor connected to a node between said plurality of transistors directly to said second reference voltage such that charges placed at said node between said plurality of transistors are removed when said adjustment transistor is turned on, wherein a gate of said adjustment transistor is connected to a signal for turning on said adjustment transistor, wherein said signal for turning on said adjustment transistor is an inverse of said clock input signal.