Patent ID: 6661707
Filing Date: 2003-12-09
Classification: G11C

Abstract:
In a NAND-type flash memory device having bitlines, wordlines, and memory strings, each string composed of memory cells serially connected between a string select transistor coupled to one of the bitlines and a ground select transistor coupled to a source line, in which the wordlines are each connected to gates of the memory cells,a method of programming one of the memory cells that is defined by a selected one of the wordlines and a selected one of the bitlines, the method comprising: applying a first voltage to a first group of wordlines that includes at least one of the wordlines other than the selected wordline; then applying a predetermined bitline voltage to at least one of the bitlines other than the selected one of the bitlines; and then applying a second voltage different from the first voltage to a second group of wordlines that includes at least one of the wordlines other than the selected wordline; and applying a third voltage different from the first voltage and different from the second voltage to the selected wordline concurrently with applying the second voltage to the second group of wordlines.