Patent ID: 6975551
Filing Date: 2005-12-13
Classification: G11C,H01L

Abstract:
1. A semiconductor storage device comprising: a memory section that performs refresh operations; a power supply/interruption circuit having a function of supplying or interrupting electric power to the memory section; and a terminal for receiving signals from an external clock circuit which generates timings of the refresh operations, wherein the memory section has operation modes of: an active mode for performing at least one operation out of a write operation, an erase operation and a read operation in response to a request from an external logic circuit, and for performing a refresh operation during a period in which none of those operations is performed; and a standby mode for performing none of a write operation, an erase operation and a read operation based on a request from the external logic circuit but performing refresh operations alone, and wherein while the memory section is in the standby mode, the power supply/interruption circuit supplies electric power to the memory section only during periods in which a refresh operation is performed in synchronization with a timing of the refresh operation generated by the external clock circuit, and interrupts power supply to the memory section during periods in which the refresh operation is not performed.