Patent ID: 6316316
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for forming a memory cell, said method comprising the steps of:providing a semiconductor substrate with an isolation region formed upon said semiconductor substrate, said semiconductor substrate having a pad oxide layer and a first nitride layer formed over said semiconductor substrate, said pad oxide layer formed on a region not covered by said isolation region on said semiconductor substrate, and said first nitride layer formed over said pad oxide layer;removing a portion of said first nitride layer and of said pad oxide layer to define a gate region;forming a first oxide layer on a region not covered by said gate region and said isolation region on said semiconductor substrate;forming a sidewall structure on said gate region;doping said semiconductor substrate with first type dopants;performing a first thermal process to form a second oxide layer on a region not covered by said sidewall structure, said gate region, and said isolation region, and to drive in said first type dopants;removing said sidewall structure and said first nitride layer;removing said first oxide layer to expose a portion of said substrate under said first oxide layer;forming silicon grains on said pad oxide layer, said portion of said substrate, and said second oxide layer;etching said portions of said substrate to leave a rugged surface on said portion of said substrate;performing a second thermal process to form a tunnel oxide layer on said rugged surface;forming a first conductive layer over said semiconductor substrate;removing a portion of said first conductive layer to define a floating gate;forming a dielectric layer over said semiconductor substrate; andforming a second conductive layer over said semiconductor substrate.