Patent ID: 6324109
Filing Date: 2001-11-27
Classification: G11C

Abstract:
A semiconductor storage device having:a plurality of memory cells arranged in a matrix form,word lines for activating the memory cells of an identical row of the plurality of memory cells,bit lines connected to one terminal of the memory cells of an identical column of the plurality of memory cells andvirtual GND lines connected to the other terminal of the memory cells of an identical column of the plurality of memory cells, the semiconductor storage device comprising:a sense amplifier that holds and amplifies a signal representing a potential difference between a potential of a reference line and a potential of the bit line connected to the column of selected memory cells upon completion of turn on of the word line in a read operation; andprecharge potential supply circuits that supply a precharge potential to all the bit lines and the virtual GND lines at a power supply start time and supply a precharge potential to the bit line and virtual GND line of the column of the memory cells that have been selected, after completion of a period during which the bit line connected to the column of the selected memory cell is sensed by the memory cells in the read operation.