Patent ID: 7444567
Filing Date: 2008-10-28
Classification: G01R,G06F

Abstract:
1. A unified test controller for testing or diagnosing a plurality of clock domains in a scan-based integrated circuit in selected self-test or scan-test mode, the unified test controller having a global scan enable (GSE) signal and a test clock, and each domain controlled by one system clock; said unified test controller comprising: (a) a capture clock generator for generating an ordered sequence of capture clocks (CCKs) in response to said global scan enable (GSE) signal and said test clock; and (b) a plurality of domain clock generators, each domain clock generator for generating a scan enable (SE) signal and a scan clock (SCK) for controlling one said clock domain, in response to said global scan enable (GSE) signal, said system clock, and a corresponding one of said capture clocks (CCKs).