Patent ID: 8320198
Filing Date: 2012-11-27
Classification: G11C

Abstract:
1. A random access memory cell, comprising: a first double gate access transistor and a second double gate access transistor respectively arranged between a first bit line and a first storage node, and between a second bit line and a second storage node; a word line connected to a first gate electrode of the first access transistor and to a first gate electrode of the second access transistor; a first double gate load transistor and a second double gate load transistor; a first double gate driver transistor and a second double gate driver transistor; wherein a reference potential is applied to the second gate of the load or driver transistors; and further comprising a polarization device configured to apply a given variable potential to at least one source or drain electrode of each of the load or driver transistors, the given potential VCELL applied during write phases of the cell being configured to be different from the reference potential and so as to produce a lower drive current of the load or driver transistors during write phases than when the given potential VCELL and the reference potential are equal.