Patent ID: 6177309
Filing Date: 2001-01-23
Classification: H01L

Abstract:
A method of forming an integrated circuit capacitor, comprising the steps of:forming an insulating layer on a surface of a semiconductor substrate;patterning the insulating layer to define an opening therein that has a constricted neck when viewed orthogonal to the surface of the insulating layer;depositing a conductive layer onto the insulating layer and into the opening so that the conductive layer conforms to a shape of the opening outside the constricted neck but fills the opening at a first location adjacent the constricted neck;planarizing the conductive layer to expose the insulating layer and define a lower capacitor electrode having dual annular sections therein that are joined together at the first location;forming a capacitor dielectric layer on the lower capacitor electrode; andforming an upper capacitor electrode that extends opposite the lower capacitor electrode, on the dielectric layer.