Patent ID: 6323675
Filing Date: 2001-11-27
Classification: H04L

Abstract:
An active termination circuit for terminating a signal traversing on a transmission line in a tri-state mode, comprising:a tri-state output buffer;a bottom clamping transistor coupled to GND and said tri-state output buffer having a bottom clamping transistor control node arranged for clamping said signal at about GND;a bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage, wherein the bottom threshold reference transistor provides a first bias voltage to said bottom clamping transistor control node that biases said bottom clamping transistor control node at about a first threshold voltage above GND, said first threshold voltage representing a threshold voltage of said bottom clamping transistor;a top clamping transistor coupled to VDD and said tri-state output buffer having a top clamping transistor control node arranged for clamping said signal at about VDD; anda top threshold reference transistor coupled to a second reference voltage supply configured to supply a second reference voltage, wherein said top threshold reference transistor provides a second bias voltage to said top clamping transistor control node that biases said top clamping transistor control node at about a second threshold voltage from VDD, said second threshold voltage representing a top clamping transistor threshold voltage.