Patent ID: 6401143
Filing Date: 2002-06-04
Classification: G06F,H04N

Abstract:
A direct memory access controller, coupled to an image processing unit, a data compression unit and FIFO, for storing digital data in a memory and retrieving digital data from memory, comprising:a compression and decompression bus control logic unit; a bypass interface; a data selector; a computing unit instructing the data selector to select the routing of digital data by way of the bypass interface or by way of the FIFO controlled by the compression and decompression bus control logic unit; a data packer receiving the selected digital data from the data selector and packing the digital data into words; a write DMA master receives the words of digital data from the data packer and places the words into blocks of digital data and stores the blocks of digital data in the memory; a read DMA master retrieves blocks of digital data from memory; a bus control logic reading digital data from the read DMA master and writing the digital data to the image processing unit, wherein the image processing unit outputs the processed digital data to one of the FIFO, ITU G3/G4 and JPEG as directed by the computing unit and the processed digital data is subsequently routed as directed by the computing unit and subsequently stored in the memory by the write DMA master.