Patent ID: 6012157
Filing Date: 2000-01-04
Classification: G01R,G06F,G11C

Abstract:
A method of verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory, each portion of said RAM memory having one or more possible states, each state representing a discrete period in time, the method comprising:introducing known fault data into a RAM system model, said known fault data comprising one or more records, each of said records containing a first field having mask values and a second field having fault severity information, said fault severity information indicating the state at which the faults should appear;simulating the performance of the RAM memory and the RAM BIST controller through the user of a RAM system model, said RAM system model keeping track of the state of each byte in said RAM memory by tracking the number of times said byte has been accessed; andcomparing the results of said RAM system model with said known fault data.