Patent ID: 9153502
Filing Date: 2015-10-06
Classification: G01R,H01L

Abstract:
1. A semiconductor chip testing method comprising the steps of: (a) testing the electrical characteristics of each semiconductor chip of a plurality of semiconductor chips formed on a predetermined number of wafers, wherein each wafer of the predetermined number of wafers includes a same number of semiconductor chips located at same positions within each wafer, and each semiconductor chip of each wafer having a wafer address corresponding to the respective position on the respective wafer; (b) determining by a processor whether each semiconductor chip is non-defective or defective according to the tested electrical characteristics; (c) automatically calculating, by the processor, for each individual wafer address, a percentage of semiconductor chips that are defective at each individual wafer address according to the determination of the processor; (d) automatically changing, by the processor, a determination result about a semiconductor chip determined in step (b) as non-defective to defective when the semiconductor chip is located at a wafer address at which the percentage calculated in step (c) is equal to or greater than a predetermined threshold thereby to increase semiconductor chip reliability; and (e) storing, when said semiconductor chips are tested in the form of chips, each of said semiconductor chips into a tray in the order in which said semiconductor chips are determined, and storing said semiconductor chips into said tray again based on said determination results about said semiconductor chips.