Patent ID: 6316982
Filing Date: 2001-11-13
Classification: G06F

Abstract:
A digital clock signal generator capable of generating an output clock signal having a frequency f.sub.O derived from a reference clock signal having a frequency f.sub.R, such that ##EQU11##is satisfied, wherein M and N are integers, comprising:means for generating from said reference clock signal at least one intermediate clock signal having a frequency f.sub.X, such that ##EQU12##wherein X is an integer close in value to N/M, wherein X is expressed as the fraction P/M, wherein P is an integer; andmeans for providing a predetermined number of phase corrections of a predetermined magnitude, said magnitude having a predetermined time relationship to the period of said reference clock signal, to said intermediate clock signal at predetermined times such that over M periods of said reference clock signal .vertline.P-N.vertline. corrections of said predetermined magnitude to said intermediate clock signal are effectively made in the appropriate phase direction so as to derive said output clock signal such that the average frequency of said output clock signal over time is f.sub.O.