Patent ID: 8402195
Filing Date: 2013-03-19
Classification: G06F,H04L

Abstract:
1. A storage system comprising: a storage device in which data that is to be read or written from a higher-level device is stored; a plurality of memories in which either write-targeted data received from the higher-level device or read-targeted data read out from the storage device is temporarily stored; a first-interface device, which is coupled to the higher-level device, and which controls input/output of data to/from the higher-level device; a second-interface device, which is coupled to the storage device, and which controls input/output of data to/from the storage device; a plurality of third-interface devices, which are coupled to the plurality of memories, and which control the input/output of data to/from the plurality of memories; a plurality of processors, each of which controls data transfer between the first-interface device and said memory and/or between the second-interface device and said memory in accordance with controlling any one or more of the first-through third-interface devices; and a plurality of root ports, where each of the root ports is coupled to any one of the plurality of processors, and is linked to one of the first through third-interface devices, which is controlled by the respectively coupled processor, wherein the plurality of root ports include a first root port, a second root port, a third root port and a fourth root port, the plurality of memories include a first-memory and a second-memory, the plurality of processors include a first processor and a second processor, the plurality of third-interface devices include a first third-interface device that is coupled to the first-memory, and a second third-interface device that is coupled to the second-memory, the first root port is linked to the first-interface device, the first third-interface device and the second third-interface device, and coupled to the first processor, the second root port is linked to the second-interface device and the first third-interface device, but not linked to the second third-interface, and coupled to the first processor, the third root port is linked to the first-interface device, the first third-interface device and the second third-interface device, and coupled to the second processor, the fourth root port is linked to the second-interface device and the second third-interface device, but not linked to the first third-interface, and coupled to the second processor, the first-interface device has a function unit for controlling the input/output of data accessible from the first root port and a function unit for controlling the input/output of data accessible from the third root port, the second interface device has a function unit for controlling the input/output of data accessible from the second root port and a function unit for controlling the input/output of data accessible from the fourth root port, the first third-interface device has a function unit for controlling the input/output of data accessible from the first root port, a function unit for controlling the input/output of data accessible from the second root port and a function unit for controlling the input/output of data accessible from the third root port, the second third-interface device has a function unit for controlling the input/output of data accessible from the first root port, a function unit for controlling the input/output of data accessible from the third root port and a function unit for controlling the input/output of data accessible from the fourth root port, the first-processor transfers to the first third-interface device and the second third-interface device write data received by the first interface device, the second-processor transfers to the first third-interface device and the second third-interface device write data received by the first interface device, the first third-interface device stores the write data in the first-memory with the corresponding function unit, the second third-interface device stores the write data in the second-memory with the corresponding function unit, the first-processor transfers the write data stored in the first-memory to the second interface device, and the second-processor transfers the write data stored in the second-memory to the second interface device.