Patent ID: 6294731
Filing Date: 2001-09-25
Classification: H01L,H05K

Abstract:
A multichip electronic packaging structure, comprising:a) a planar substrate having an upper surface, a lower surface and a predetermined coefficient of thermal expansion;b) an array of flexible, electrically conductive interconnect members perforating said substrate and extending from said lower surface thereof, a predetermined portion of said extending, flexible interconnect members being surrounded by a dielectric material thereby forming a core, the distal ends of said flexible interconnect members furthest from said lower surface of said substrate being exposed;c) a shell in contact with said lower surface of said substrate and surrounding the perimeter of said core;d) a planar interconnection layer having an upper surface and a lower surface, said lower surface of said interconnection layer being electrically communicative with said array of interconnect members and affixed to said upper surface of said substrate; ande) at least one device electrically and mechanically connected to said upper surface of said interconnection layer;whereby said exposed ends form a compliant, conductive, demountable interface adapted for connecting said at least one electrical device to an external substrate.