Patent ID: 8930600
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A protecting circuit for a basic input output system (BIOS) chip of a computer, comprising: a platform controller hub (PCH) comprising a first pin and a second pin, wherein the first pin outputs a low level first signal, and the second pin outputs a high level second signal, in response to the computer being powered off; the first pin outputs a high level third signal, and the second pin outputs a high level second signal, in response to the computer being in a power-on self-test state; an inverting circuit connected to the PCH, to receive the first or third signal, and outputs an inverted signal with a level contrary to the level of the first or third signal; a BIOS socket to connect the BIOS chip, the BIOS socket comprising a write protection pin; and a controlling circuit connected between the inverting circuit and the BIOS socket, the controlling circuit comprising a trigger and a first buffer gate chip, wherein the trigger is to receive the first or third signal and the inverted signal, and outputs a control signal based on the first or third signal and the inverted signal to the first buffer gate chip, the first signal bus buffer gate chip is to receive the second signal to control the first signal bus buffer gate chip to be turned on, and outputs a process signal to the write protection pin of the BIOS socket; wherein the inverting circuit outputs a high level inverted signal, the first buffer gate chip outputs a high level process signal, to enable the BIOS chip to be in a state of writable, in response to the PCH outputting the low level first signal and the high level second signal; the inverting circuit outputs the low level inverted signal, the first buffer gate chip outputs the low level process signal, to enable the BIOS chip to be in a state of write-protection, in response to the PCH outputting the third high level signal and the high level second signal.