Patent ID: 8432004
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. An integrated circuit comprising an asymmetric segmented transistor, the asymmetric segmented transistor comprising: an active region disposed at a surface of a semiconductor body; a source region and a drain region disposed within the active region; a floating source/drain region disposed within the active region; a first channel region having a first doping type disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width; a second channel region having the first doping type disposed in the active region between the drain region and the floating source/drain region, the second channel region having a second length and a second width different from the first width; a first gate dielectric overlying the first channel region; a second gate dielectric overlying the second channel region; a first gate line overlying the first gate dielectric; and a second gate line overlying the second gate dielectric, wherein the first gate line and second gate line are directly electrically coupled.