Patent ID: 6505269
Filing Date: 2003-01-07
Classification: G06F

Abstract:
A dynamic address mapping method for eliminating contention to a memory resource of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine, the method comprising the steps of:providing a bank select mode that enables logical-to-physical address mapping operations by a first processor to select a bank of the memory resource storing a first data structure having short entries, each short entry comprising data accessible by the first processor at a particular location of the bank; and providing a stream mode that enables logical-to-physical address mapping operations by a second processor to select a bank from among a plurality of banks of the memory resource storing a second data structure having long entries, each long entry comprising data accessible by the second processor at a plurality of locations among the plurality of banks, wherein the bank select and stream modes are simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing particular memory locations as well as a plurality of memory locations within the memory resource.