Patent ID: 6642745
Filing Date: 2003-11-04
Classification: H03K

Abstract:
A semiconductor circuit comprising:a first stage block including a plurality of first stage dynamic circuits and configured to output a predischarged result of the respective first stage dynamic circuits to blocks cascade connected to later stages, each of the first stage dynamic circuit includes predischarge elements connected respectively to dynamic nodes of the respective first stage dynamic circuits to predischarge the dynamic nodes, configured such that the dynamic nodes of the respective first stage dynamic circuits are precharged with a predetermined cycle; a predischarge signal generating circuit configured to generate a predischarge signal to actuate the respective predischarge elements before precharge timing of the respective dynamic nodes of the respective first stage dynamic circuits; and at least more than one next stage blocks including a plurality of next stage dynamic circuits and configured to output predischarge results of the respective next stage dynamic circuits sequentially to blocks cascade connected to later stages, each of the next stage dynamic circuit configured to input the predischarge result of the previous block so as to predischarge dynamic nodes of the respective next stage dynamic circuits, configured such that the dynamic nodes of the respective next stage dynamic circuits are precharged with a predetermined cycle.