Patent ID: 7188233
Filing Date: 2007-03-06
Classification: G06F

Abstract:
1. A system for performing floating point arithmetic operations, the system comprising: a plurality of stages making up a pipeline, the stages including a first stage and a last stage; a register file adapted for receiving a store instruction for input to the pipeline, wherein the data associated with the store instruction is dependent on a previous operation still in the pipeline; a store register adapted for outputting the data associated with the store instruction to memory; and a control unit including instructions for: inputting the store instruction into the pipeline and providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation; and inputting the store instruction into the pipeline and providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.