Patent ID: 6424649
Filing Date: 2002-07-23
Classification: H04J,H04L

Abstract:
A switch, comprising:a clock signal source for generating a first clock signal; at least one input interface element, said at least one input interface element having a parallel input port for receiving data cells and a serial transmitter coupled to said input port by a first parallel to serial converter, and transmitting said data cells by serial transmission; a cross connect receiving serial data from said at least one input interface element at a first serial to parallel converter, said cross connect having a cross bar switch receiving parallel data from the first serial to parallel converter, and said cross connect having a second parallel to serial converter receiving parallel data from the cross bar switch and transmitting the data by serial transmission; at least one output interface element receiving said serial data, transmitted by said cross connect, at a second serial to parallel converter and an output port receiving parallel data from said second serial to parallel converter and transmitting parallel data; means for generating a second clock signal in response to the first clock signal, said second clock signal for synchronizing said first serial to parallel converter to said first clock signal; means for generating a third clock signal in response to the first clock signal, said third clock signal for synchronizing said first parallel to serial converter to said first clock signal; means for generating a fourth clock signal in response to the first clock signal, said fourth clock signal for synchronizing said second parallel to serial converter to said first clock signal; and, means for generating a fifth clock signal in response to the first clock signal, said fifth clock signal for synchronizing said second serial to parallel converter to said first clock signal.