Patent ID: 7368941
Filing Date: 2008-05-06
Classification: H03K

Abstract:
1. A dedicated logic cell, comprising: a first logic and routing cell, comprising a first configurable logic function (LL) having at least one input and at least one output; a control logic function (LC) having at least one input and at least one output, the at least one input of the control logic function coupled to the at least one output of the first configurable logic function; and a first sequential logic function (LS) having at least one input and at least one output, the at least one input of the first sequential logic function coupled to the at least one output of the control logic function; a second logic and routing cell, coupled to the first logic and routing cell, comprising a second configurable logic function (LL) having at least one input and at least one output; a dedicated logic function (LD) having at least one input and at least one output, the at least one input of the dedicated logic function coupled to the at least one output of the second configurable logic function; and a second sequential logic function (LS) having at least one input and at least one output, the least one input of the second sequential logic function coupled to the at least one output of the control logic function; wherein the combination of the first configurable logic function, the control logic function, the first sequential logic function, and the dedicated logic function performs an N-input accumulator with loadable data, addsub control, synchronous clear, synchronous set, asynchronous clear, and data enable.