Patent ID: 7282952
Filing Date: 2007-10-16
Classification: G09G

Abstract:
1. A level shift circuit comprising: a capacitor element that has one terminal to which a logic input signal having a first logic amplitude is input; a logic output circuit that includes a first logic inverting circuit having a first logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element; and a second logic inverting circuit having a second logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element, and that inverts a logic output signal having a second logic amplitude when output polarities of the first logic inverting circuit and the second logic inverting circuit coincide with each other; and a third logic inverting circuit whose input and output terminals are connected to the other terminal of the capacitor element and that has a third logic inversion level with respect to the input terminal thereof connected to the other terminal of the capacitor element, wherein the first logic inversion level is set to be higher than the third logic inversion level, and the second logic inversion level is set to be lower than the third logic inversion level.