Patent ID: 6359310
Filing Date: 2002-03-19
Classification: H01L,Y10S

Abstract:
An electrical device comprising:a semiconductor substrate having a top surface; a gate region over the semiconductor substrate, wherein the gate region has a bottom surface that is parallel to the top surface of the semiconductor substrate; a source/drain region for the gate region and situated within the semiconductor substrate, wherein the source/drain region has: a first portion that extends from a top surface of the semiconductor substrate to a depth of less than about 1000 angstroms and has a concentration of greater than 1Ã—1019 dopant atoms per cm3, wherein said first portion does not underlap the bottom surface of the gate region that is parallel to the top surface of the semiconductor substrate; and a second portion that extends from the first portion an additional depth of about 250 angstroms to about 750 angstroms and has a concentration less than about 1Ã—1019 dopant atoms per cm3, wherein said second portion underlaps the bottom surface of the gate region that is parallel to the top surface of the semiconductor substrate.