Patent ID: 8664668
Filing Date: 2014-03-04
Classification: B41J,H01L

Abstract:
1. A combined semiconductor apparatus comprising: a substrate having an integrated circuit; a planarized region being a planarized layer disposed on a surface of the substrate, wherein an upper surface of the planarized layer has been subjected to a planarizing process; a planarized metal layer disposed on the upper surface of the planarized region, wherein an upper surface of the planarized metal layer has been subjected to a planarizing process to be a planar surface; a plurality of semiconductor thin films bonded to the upper surface of the planarized metal layer so as to be arranged at regular intervals, each of the semiconductor thin films having a thickness of 10 μm or less, each of the semiconductor thin films being made of compound semiconductor selected from the group consisting of Al a plurality of thin metal interconnecting layers extending from upper surfaces of the semiconductor thin films to an upper surface of the integrated circuit respectively, such that an upper layer of each of the semiconductor thin films has an exposed part that is uncovered by the thin metal interconnecting layer.