Patent ID: 6911156
Filing Date: 2005-06-28
Classification: G11C,H01L,Y10T

Abstract:
1. A method for fabricating a magnetic memory element structure, the method comprising the steps of: providing a dielectric layer having a conducting via formed therein; forming a first magnetic layer overlying said dielectric layer and in electrical communication with said conducting via; forming a tunnel barrier layer overlying said first magnetic layer; forming a second magnetic layer overlying said tunnel barrier layer, depositing a first conductive layer overlying said second magnetic layer; depositing a first masking layer overlying said first conductive layer and patterning said first masking layer; using said patterned first masking layer, etching said first conductive layer, said etching causing said first conductive layer to have a plurality of sidewalls, said etching further exposing a portion of said second magnetic layer; transforming said exposed portion of said second magnetic layer to form an insulative inactive portion and an active portion of said second magnetic layer, said active portion comprising a portion of a magnetic tunnel junction element and said insulative inactive portion comprising an insulator; forming a sidewall spacer adjacent at least one of said plurality of sidewalls of said first conductive layer, and forming a masking tab that overlies a portion of said patterned first masking layer and a portion of said magnetic tunnel junction element and that laterally extends from said magnetic tunnel junction element to said conducting via and overlies at least a portion of said conducting via.