Patent ID: 6373320
Filing Date: 2002-04-16
Classification: H03F

Abstract:
A circuit configuration for transistor operating point stabilization, comprising:a first transistor with an emitter, a base, a collector and an operating point to be stabilized, said emitter connected to a first supply potential; a second transistor with an emitter, a base and a collector, said collector coupled to said base of said first transistor and said emitter coupled to said collector of said first transistor; a first resistor having one terminal connected to a second supply potential and another terminal connected to both said collector of said first transistor and said emitter of said second transistor; a current-limiting element connected between said base of said second transistor and the first supply potential; a third transistor with an emitter, a base and a collector, said emitter connected to the second supply potential and said collector connected to said base of said second transistor; a second resistor connected between a reference potential and said base of said third transistor; and a third resistor connected between said base and said collector of said third transistor.