Patent ID: 8553444
Filing Date: 2013-10-08
Classification: G11C,H01L

Abstract:
1. A variable resistance nonvolatile storage device comprising: a semiconductor substrate; a variable resistance element including: a first electrode; a second electrode; and a variable resistance layer which is provided between said first and second electrodes and in contact with said first and second electrodes and which has a resistance value that reversibly varies based on voltage signals each of which has a different polarity and is applied between said first and second electrodes; and an N-type MOS transistor formed on a main surface of said semiconductor substrate, said N-type MOS transistor including: a first N-type diffusion layer region; a gate; and a second N-type diffusion layer region formed on a side of said gate opposite said first N-type diffusion layer region, wherein said variable resistance layer includes: a first region which is in contact with said first electrode and contains a first oxygen-deficient transition metal oxide having a composition MO wherein said first N-type diffusion layer region of said N-type MOS transistor is connected with said first electrode included in said variable resistance element to form a memory cell so that a substrate bias effect in said N-type MOS transistor is smaller when one of the voltage signals having a polarity that causes a resistance change to high resistance state in said variable resistance layer is applied to said N-type MOS transistor and said variable resistance element, than when another one of the voltage signals having a polarity that causes a resistance change to low resistance state in said variable resistance layer is applied to said N-type MOS transistor and said variable resistance element, and wherein the first region of the variable resistance layer and the first electrode of the variable resistance element are each connected between the first N-type diffusion layer region and the second region of the variable resistance layer.