Patent ID: 6992512
Filing Date: 2006-01-31
Classification: G11C

Abstract:
1. A CMOS output buffer circuit for providing first and second output signals in response to an input signal, comprising: a first PMOS transistor; a first NMOS transistor, wherein the first NMOS transistor and the first PMOS transistor are configured as a first inverter cell that is responsive to the input signal; a first current-limiting cell that is coupled between a supply node and a source of the first PMOS transistor such that an operating current associated with the first inverter cell is limited; a second PMOS transistor; a second NMOS transistor, wherein the second NMOS transistor and the second PMOS transistor are configured as a second inverter cell that is responsive to the output of the first inverter cell; a second current-limiting cell that is coupled between the supply node and a source of the second PMOS transistor such that an operating current associated with the second inverter cell is limited; a third PMOS transistor; a third NMOS transistor, wherein the third NMOS transistor and the third PMOS transistor are configured as a third inverter cell that is responsive to the input signal; a third current-limiting cell that is coupled between another supply node and a source of the third NMOS transistor such that an operating current associated with the third inverter cell is limited; a fourth PMOS transistor; a fourth NMOS transistor, wherein the fourth NMOS transistor and the fourth PMOS transistor are configured as a fourth inverter cell that is responsive to the output of the third inverter cell; and a fourth current-limiting cell that is coupled between the other supply node and a source of the fourth NMOS transistor such that an operating current associated with the fourth inverter cell is limited, wherein the first inverter cell is arranged to provide a first inverter output signal such that a voltage swing of the first inverter output signal is less than a rail-to-rail voltage and wherein the second inverter cell is arranged to provide a second inverter output signal such that a voltage swing of the second inverter output signal corresponds to the rail-to-rail voltage.