Patent ID: 7106616
Filing Date: 2006-09-12
Classification: G11C

Abstract:
1. A ferroelectric memory comprising: a memory cell array formed by arraying memory cell units in a matrix, each memory cell unit having ferroelectric memory cells in one row and a plurality of columns; a plurality of word lines provided one for each row of the memory cell units, each word line being commonly connected to the ferroelectric memory cells in the same row; a plurality of plate lines provided one for each memory cell unit, each plate line being commonly connected to the ferroelectric memory cells in the same memory cell unit; a plurality of plate-enable signal lines provided one for each column of the memory cell units; a plurality of bit lines provided one for each column of the ferroelectric memory cells, each bit line being commonly connected to the ferroelectric memory cells in the same column; a word line driver for activating only the word line corresponding to a selected memory cell unit, of the plurality of word lines; a plurality of plate-enable control circuits provided one for each column of memory cell units, for activating only the plate-enable signal line corresponding to the selected memory cell unit, of the plurality of plate-enable signal lines; and a plurality of plate line drivers provided one for each column of the memory cell units, the plate line drivers supplying either one of an activation potential and a non-activation potential to the plate line corresponding to the activated word line in accordance with a potential of the plate-enable signal line and supplying the non-activation potential to plate lines corresponding to the non-activated word lines.