Patent ID: 6617232
Filing Date: 2003-09-09
Classification: H01L

Abstract:
A method of forming a wiring of a semiconductor device, comprising:forming a first insulation layer having a hole or a first trench filled with a conductive material on a semiconductor substrate; sequentially forming a first etch stop layer including a non-oxide based insulating material having carbon or a carbon compound and a second insulation layer including an oxide based insulating material on the first insulation layer; forming a third insulation layer including the oxide based insulating material on the second insulation layer; forming a capping layer including a non-carbonic oxide based insulating material on the third insulation layer; forming a via hole by etching predetermined portions of the capping layer, the third insulation layer and the second insulation layer in such a manner that a part of the first etch stop layer corresponding to an upper portion of the hole or the first trench filled with conductive material is exposed; forming a photoresist pattern on the capping layer having the via hole so as to form a linear trench including the via hole; partially etching the capping layer using the photoresist pattern as an etching mask, the capping layer being reacted with an etching gas used for etching the capping layer to form a polymer layer on the first etch stop layer for protecting the first etch stop layer; forming a second trench by sequentially etching the remaining capping layer and the third insulation layer using the photoresist pattern as an etching mask; removing the photoresist pattern and the polymer layer; removing the first etch stop layer exposed at a lower portion of the via hole; and filling a resulting structure with a conductive material.