Patent ID: 6819153
Filing Date: 2004-11-16
Classification: H03L,H04N

Abstract:
A semiconductor device comprising:an external clock input means for receiving an external clock that is a clock to be synchronized; N stages of delay elements each delaying the external clock by 1/N clock (N is an integer that is two or larger); a phase comparison means for comparing a phase of a clock that has been delayed by the N stages of the delay elements with a phase of the external clock which is one clock late, and detecting a phase difference; a control means for controlling respective delays of the delay elements on the basis of the phase difference detected by the phase comparison means; a reference signal input terminal for receiving a reference signal which is different from the external clock; and a selection means for selecting one of delayed clocks which are generated by the N stages of the delay elements, respectively, and shifted in phase with each other by 1/N clock, the selected delayed clock having a change point that is closest to a change point of the reference signal and outputting the selected clock as a synchronous clock.