Patent ID: 6301264
Filing Date: 2001-10-09
Classification: G06F,H03M

Abstract:
A data conversion circuit for converting an N-bit data stream to an M-bit data stream, the data conversion circuit comprising:a first-in-first-out (FIFO) memory device having a plurality of N-bit memory locations and receiving as an input consecutive N-bit sets of data from the N-bit data stream, wherein the FIFO memory device is adapted to store each consecutively received N-bit set of data in consecutive ones of the plurality of N-bit memory locations;a write pointer generator generating information identifying a next available of the plurality of N-bit memory locations at which a next N-bit set of data is to be stored;a first read pointer generator generating information identifying a first of the plurality of N-bit memory locations containing a first portion of a first M-bit set of data in the M-bit data stream; anda second read pointer generator generating information identifying a second of the plurality of N-bit memory locations containing a last portion of the first M-bit set of data in the M-bit data stream, wherein the FIFO memory device provides as an output the first M-bit set of data in the M-bit data stream, and wherein the first M-bit set of data in the M-bit data stream includes each of the plurality of N-bit memory locations between and including the first of the plurality of N-bit memory locations identified by the first read pointer generator and the second of the plurality of N-bit memory locations identified by the second read pointer generator.