Patent ID: 7328382
Filing Date: 2008-02-05
Classification: G06F,G11C

Abstract:
1. An architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, N being a positive integer greater than 1, said architecture comprising: N groups of data ports, each of said N groups of data ports comprising: N BISR_SUBMOD modules for connecting to said N memory instances via said N groups of data ports, each of said N BISR_SUBMOD modules including a flip-flop, a first mux and a second mux, wherein each of said N BISR_SUBMOD modules is connected to a corresponding group of data ports of said N groups of data ports; and a CLK_IN input port and a BISR_IN input port for setting configuration of said memory BISR controller, said CLK_IN input port being connected to clock inputs of all N flip-flops of said memory BISR controller, said BISR_IN input port being connected to data input of a first flip-flop of said N flip-flops, and output of a K-th flip-flop of said N flip-flops being connected to input of a (K+1)-th flip-flop of said N flip-flops, K=1, 2, . . . , N-1, wherein when at least one of said N memory instances is defective, said memory BISR controller reconfigures connections among said N memory instances to use at least one other memory instance instead of said at least one of said memory instances.