Patent ID: 9110142
Filing Date: 2015-08-18
Classification: G01R,H01L

Abstract:
1. An integrated circuit comprising: a first input interconnect configured to receive an input signal; a first test enable interconnect configured to receive a test enable signal; a controller for performing testing of the integrated circuit based on values that correspond to the input signal; an input port; a first multiplexer coupled to the first input interconnect, the controller, and the input port, and controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the controller in response to assertion of the test enable signal; a first test data out interconnect configured to produce test output data; a second test data out interconnect configured to receive remotely-produced test output data; a register configured to store an indication that the integrated circuit is or is not in a boundary scan pass-through mode; a second multiplexer coupled to the first test data out interconnect, and controllable to pass first test output data produced by the integrated circuit to the first test data out interconnect to be produced as the test output data when the integrated circuit is not in the boundary scan pass-through mode; and a third multiplexer coupled to the second test data out interconnect and to the second multiplexer, and controllable to pass the remotely-produced test output data to the second multiplexer to be produced as the test output data on the first test data out interconnect when the integrated circuit is in the boundary scan pass-through mode.