Patent ID: 6259639
Filing Date: 2001-07-10
Classification: G06F,G11C

Abstract:
A semiconductor integrated circuit device comprising:a memory cell means having a normal port via which a normal read/write operation is performed, and a test port intended for tests, via which data can be read out of said memory cell means;a data latch means for temporarily latching write data, which is written into said memory cell means by way of the normal port;a comparator means for reading the data, which has been written into said memory cell means by way of the normal port, from said memory cell means by way of the test port, and for comparing the read data with the original write data latched by said data latch means;a redundant means for latching the write data to take the place of said memory cell means when said comparator means detects a mismatch between the data read by said comparator means and the write data latched by said data latch means; andan address holding means for holding information on an address identifying a location of said memory cell means into which the write data has been written when said comparator means detects a mismatch between the data read by said comparator means and the write data.