Patent ID: 6618320
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A semiconductor memory device, having first and second DDR-DRAMS, in a package, that output data with a fixed phase at the leading edge and trailing edge of a clock, the data input/output lines of the first and the second DDR-DRAMs being connected commonly, comprising:a clock generation circuit that generates, from an external clock, a first clock having the same frequency and phase as the external clock and a second clock having the same frequency as the external clock but being a quarter phase shifted, supplies the first clock to the first DDR-DRAM as a clock, and supplies the second clock to the second DDR-DRAM as a clock; a data output portion, in the first DDR-DRAM, that outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first clock and brings a data output circuit into a high impedance state for other time periods; and a data output portion, in the second DDR-DRAM, that outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the second clock and brings a data output circuit into a high impedance state for other time periods.