Patent ID: 6753235
Filing Date: 2004-06-22
Classification: H01L

Abstract:
A method of manufacturing a CMOS TFT, comprising:forming first and second semiconductor layers on an insulating substrate using a first mask, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; forming first spacers on both side wall portions of the first gate electrode and the first capping layer; ion-implanting a first conductive-type high-density impurity into the first semiconductor layer using the first spacers and the first gate electrode as a mask to form first high-density source and drain regions; etching a portion of the first metal layer and a portion of the second insulating layer over the second region of the substrate using a third mask to form a second gate electrode and a second capping layer; and ion-implanting a second conductive-type high density impurity into the second semiconductor layer using the third mask to form second high-density source and drain regions.