Patent ID: 6858490
Filing Date: 2005-02-22
Classification: H01L

Abstract:
1. A method for manufacturing a merged DRAM with logic (MDL) device, the method comprising the steps of: a) forming an oxide layer and a nitride layer one by one on a semiconductor substrate; b) forming a hole for exposing the substrate through patterning the nitride layer and the oxide layer; c) growing a silicon epitaxial layer on a portion of the substrate exposed by the hole and an adjacent portion of the nitride layer so that a facet is formed on the surface of the nitride layer; d) growing a thermal oxide layer on the grown silicon epitaxial layer; e) wet etching the thermal oxide layer so that only a growing portion thereof is left on the facet of the silicon epitaxial layer; f) repeating steps of c), d) and e) a predetermined number of times; g) removing the thermal oxide layer left on the facets of the repeatedly grown silicon epitaxial layers; h) serially forming a gate oxide layer and a gate conductive layer on the resulting substrate from step g); and i) forming a gate through patterning the gate conductive layer and the gate oxide layer, and forming a capacitor as well, comprising a storage node consisting of the substrate and the silicon epitaxial layer repeatedly grown as to leave a facet of the silicon epitaxial layer, a dielectric layer consisting of the gate oxide layer, and a plate node consisting of the gate conductive layer.