Patent ID: 6037204
Filing Date: 2000-03-14
Classification: H01L

Abstract:
A method for forming contacts to p- and n-channel self-aligned polysilicon gate MOSFETs comprising:(a) providing a silicon wafer having at least one p-channel self aligned polysilicon gate MOSFET and at least one n-channel self-aligned polysilicon gate MOSFET formed within and upon its surface, said at least one p-channel self aligned polysilicon gate MOSFET and said at least one n-channel self-aligned polysilicon gate MOSFET having impurity doped source/drain active areas and polysilicon gate electrodes with adjacent insulative sidewall spacers;(b) Implanting silicon atoms into said silicon wafer thereby forming amorphous regions on said source/drain areas and said gate electrodes;(c) implanting arsenic atoms into said amorphous regions thereby forming arsenic doped regions and wherein said arsenic doped regions lie within said amorphous regions;(d) depositing a metal layer on said silicon wafer;(e) depositing a protective layer over said metal layer;(f) performing a first thermal anneal of said silicon wafer whereby a portion of said metal layer reacts with said polysilicon layer to form a silicide;(g) etching said wafer with an aqueous etchant thereby removing said protective layer and residual said metal layer;(h) performing a second thermal anneal of said silicon wafer;(i) depositing an insulative layer over said silicon wafer;(j) etching contact openings in said insulative layer; and(k) depositing a conductive material into said openings thereby forming contacts.