Patent ID: 9035472
Filing Date: 2015-05-19
Classification: H01L,H05K

Abstract:
1. A semiconductor device comprising: a semiconductor chip having a front surface over which a plurality of electrode pads is formed, and a back surface opposite to the front surface; and a wiring board having a chip mounting surface over which the semiconductor chip is mounted, a mounting surface opposite to the chip mounting surface, a plurality of first pads arranged over the chip mounting surface and electrically connected with the electrode pads of the semiconductor chip, a plurality of lands arranged over the mounting surface in a matrix form and electrically connected with the first pads, a first conductor pattern arranged in a position of the mounting surface overlapped by the semiconductor chip in a thickness direction, and a first insulating layer covering the mounting surface, wherein the first insulating layer has a plurality of first apertures formed such that a part of each of the lands is exposed, and a plurality of second apertures formed such that a plurality of portions of the first conductor pattern is exposed, wherein the first conductor pattern has a plurality of first conductor apertures, wherein a second insulating layer disposed over the first conductor pattern is exposed from the first conductor apertures, wherein outlines of the second apertures and the first conductor apertures overlap with each other, in a plan view, respectively, and wherein first straight lines pass through a center of a first region overlapped by the semiconductor chip in a thickness direction over the mounting surface and a center of each of the second apertures, and the first conductor pattern is disposed at a first intersection adjacent the center of the first region, of intersections of the first straight lines and each second aperture, and one of the first conductor apertures is disposed at a second intersection remote from the center of the first region, of the intersections.