Patent ID: 7047515
Filing Date: 2006-05-16
Classification: G06F,H05K

Abstract:
1. A method of determining locations for placing bypass capacitors for controlling the signal integrity of a signal routed from a first device to a second device via an interconnecting signal trace on a multi-layer printed circuit board, the printed circuit board including at least a first layer, a second layer, a third layer, and a fourth layer, the method comprising: analyzing the routing of the interconnecting signal trace; and determining a location for a bypass capacitor based upon routing of the interconnecting signal trace in the third layer adjacent to the fourth layer, where the first layer powers the first and second devices, the second layer serves as a voltage reference plane for the first and second devices, the third layer serves as a routing layer for the interconnecting signal trace, and the fourth layer serves as an impedance control plane for the interconnecting signal trace but not powering nor serving as the voltage reference plane for the first and second devices, the location of the bypass capacitor decided in accordance with frequency and waveform characteristics of the interconnecting signal and required signal integrity.