Patent ID: 9209181
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method, comprising: forming an N-active region and a P-active region in a semiconductor substrate; forming a first masking layer that covers said P-active region while leaving an area above said N-active region un-masked; with said first masking layer in position, forming a layer of silicon-carbon on an upper surface of said N-active region; removing said first masking layer; performing a common deposition process to form a first portion of a layer of a first semiconductor material on said layer of silicon-carbon and a second portion of said first semiconductor material on an upper surface of said P-active region; forming a second masking layer that covers said N-active region while leaving an area above said P-active region un-masked; with said second masking layer in position, forming a layer of a second semiconductor material on said second portion of said first semiconductor material; removing said second masking layer; forming an N-type transistor in and above said N-active region; and forming a P-type transistor in and above said P-active region.