Patent ID: 7773676
Filing Date: 2010-08-10
Classification: H04N

Abstract:
1. A video decoding system, comprising: a video decoder configured to receive a compressed bit stream via an internal memory bus and restore the compressed bit stream to an interlaced scanned video signal by performing VLD (variable length decoding), IQ (inverse quantization), IDCT (inverted discrete cosine transform), and MC (motion compensation) on the compressed bit stream; an external memory configured to store decoded video data in a memory map constructed in a field or frame structure or output data stored for MC via an external data bus when storing the decoded video data or outputting the stored data; a memory access controller configured to rearrange data of an MB (macro-block) of the interlaced scanned video signal in the external memory so that the data of the MB are stored in or read out from the external memory on a field or frame basis; and a memory arbiter configured to receive a request for permission to access the memory from the memory access controller and determine whether to permit the memory access controller to use the external data bus, wherein, the video decoder, the memory access controller and the memory arbiter are formed in a single chip, and the memory access controller is connected between the memory arbiter and the video decoder, and wherein the memory access controller comprises: a write FIFO block configured with an at least 2-step pipeline structure to store the decoded video data; an MB write controller configured to rearrange pixels of Y and CbCr signals in one MB decoded at the video decoder by top fields and by bottom fields, store the rearranged pixels in the write FIFO block, and then store the rearranged pixels in the external memory in the form of a DDR SDRAM; a read FIFO block configured with an at least 3-step pipeline structure to store data read out from the DDR SDRAM-type external memory; and an MB read controller configured to generate read/write addresses of a read FIFO block and a DDR SDRAM read address so as to read out data of a column pair from the DDR SDRAM-type external memory and store the read-out data in the read FIFO block.