Patent ID: 6100592
Filing Date: 2000-08-08
Classification: H01L

Abstract:
An integrated circuit, comprising:a substrate having a plurality of adjoining gates with top and sidewall surfaces;a nitride cap positioned in covering electrically insulating relation over and against each of the top surfaces of the respective gates, and wherein each nitride cap has an outwardly facing surface;electrically insulative sidewall spacers positioned in covering electrically insulating relation over and against the sidewall surfaces of the respective gates, and wherein each of the sidewall spacers have an outwardly facing surface, and wherein a contact opening is defined between the outwardly facing surfaces of the sidewall spacers of the adjoining gates;a layer of silicon positioned in the contact opening and filling a portion of the contact opening, and wherein the layer of silicon has an outwardly facing surface having a given surface area and which is substantially planar and which is located elevationally inwardly relative to the outwardly facing surface of nitride caps; anda silicide layer positioned against, and in covering relation relative to, the outwardly facing surface of the silicon layer, and in partial covering relation relative to the nitride caps of the adjoining gates, and wherein the silicide layer completely fills the remaining portion of the contact opening and has an inwardly facing surface area which is located elevationally outwardly of the top surface of each of the gates, and elevationally inwardly with respect to the top surface of the nitride caps, and a top surface which forms a contact landing pad which has a given surface area, and wherein the surface area of the contact landing pad is greater than the outwardly facing surface area of the layer of silicon.