Patent ID: 8542552
Filing Date: 2013-09-24
Classification: G11C,H03L

Abstract:
1. A DLL circuit comprising: a delay chain, in which delay elements are arranged into a plurality of stages numbered from 1 to N (N a positive integer) connected in series, that is configured to generate delay clocks having mutually different delay amounts from each other with respect to a reference clock; a plurality of phase comparators, each receiving the reference clock individually and each receiving respectively a clock from a corresponding stage of the delay elements, wherein the clocks received by the comparators from the delay elements are from mutually different stages among the plurality of stages of the delay elements; and a controller that simultaneously receives comparison results from the plurality of phase comparators, determines the stage number that generates the clock of which a phase is synchronized with a phase of the reference clock from among the plurality of stages of the delay elements, and selects a stage from among the plurality of stages of the delay elements based on the determined stage number so that a delay clock among said delay clocks having a demanded delay amount with respect to the reference clock is output.