Patent ID: 6197613
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method for forming a wafer level package comprising the steps of:providing a silicon wafer having a multiplicity of IC dies formed on a top surface, each of said multiplicity of IC dies having at least one first I/O pad formed in a first insulating layer,forming at least one via plug of a first conductive metal substantially exposed on said at least one first I/O pad,coating a layer of second insulating material of sufficient elasticity on said top surface of the wafer with a top surface of said at least one via plug substantially exposed from said second insulating material layer,depositing a second conductive metal layer on top of said second insulating material layer,forming at least one metal trace with a first end electrically communicating with said at least one via plug and a second end extending away from said first end,depositing a third insulating material layer on top of said at least one metal trace,defining and exposing at least one second I/O pad at said second end of said at least one metal trace, andforming at least one solder ball on said at least one second I/O pad.