Patent ID: 8110854
Filing Date: 2012-02-07
Classification: G06F,H01L

Abstract:
1. An integrated circuit, comprising: a gate electrode level region that includes at least three linear-shaped conductive structures that each form a gate electrode of a transistor of a first transistor type and a gate electrode of a transistor of a second transistor type, the gate electrode level region including at least two linear-shaped conductive structures that respectively form gate electrodes of adjacently positioned transistors of the first transistor type that are formed in part by a first shared diffusion region of a first diffusion type, the gate electrode level region including at least two linear-shaped conductive structures that respectively form gate electrodes of adjacently positioned transistors of the second transistor type that are formed in part by a first shared diffusion region of a second diffusion type, wherein each linear-shaped conductive structure within the gate electrode level region is formed to extend lengthwise in a first direction; and a plurality of interconnect levels each including a number of conductive interconnect structures, wherein the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type through conductive interconnect structures within at least two of the plurality of interconnect levels.