Patent ID: 6360311
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A processing device including:a processing unit, memory for storing instructions for the processing unit; and a read unit for reading instructions from the memory in a logic sequence and for applying the instructions to the processing unit so as to be executed in the logic sequence; wherein the memory comprises a plurality of independently addressable memory banks, logically successive instructions being stored in different memory banks; and the read unit is arranged to read a number of instructions from different memory banks in parallel, so that the second instruction is readable each time that the processing unit starts to execute the first instruction, the second instruction logically succeeding the first instruction, the second instruction being read from the memory banks at that instant that the processing unit start to execute the first instruction, reading of the second instruction being along a second pathway parallel to a first pathway along which the first instruction was read, the reading of the second instruction also being a second one of the memory banks distinct from a first one of the memory banks, the first one of the memory banks being a source of the first instruction; wherein the processing unit is arranged to execute inter alia a branch instruction, after which the processing unit should continue with the execution of either a branch target instruction or an instruction which logically succeeds the branch instruction, depending on the satisfying of a condition to be evaluated, and the read unit is further arranged to i. buffer instructions in a pipeline unit, between the reading from the memory and applying to the processing unit, ii. detect the branch instruction in the pipeline unit, iii. start reading, in response to the detection of the branch instruction and in parallel with the reading of one or more instructions which logically succeed the branch instruction, the branch target instruction from a further memory bank, provided that the further memory bank does not store any of the one or more instructions which logically succeed the branch instructions, and iv. apply, after execution of the branch instruction and in dependence on the satisfying of the condition, either the branch target instruction and instructions which logically succeed it or the instruction which logically succeeds the branch instruction and instructions which logically succeed it to the processing unit.