Patent ID: 6543039
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A method of designing an integrated circuit, comprising:a first step of sequentially reading design cell data about design cells among pieces of integrated circuit design layout data stored in storage section; a second step of, with reference to the design cell data and a predetermined cell division judging criterion, dividing into divided cells the design cell among the design cells which exceeds the cell division judging criterion, converting the design cell data into internal cell data about an internal cell consisting of the divided cell and the design cell other than the divided cell, storing the internal cell data in an internal format file created in said storage section, and recording information for identifying the respective internal cells and a quantity of the data comprising data size or data area contained in each internal cell in an internal cell identification number table created in said storage section, a third step of repeating said first step and said second step till said first and second steps are completed with respect to all pieces of design cell data; a fourth step of creating a plurality of unit groups by combining the internal cells so that the quantity of the data becomes approximates to a predetermined reference data quantity with reference to the quantity of the data contained in each internal cell which is registered in the internal cell identification number table, and registering information for identifying the respective unit groups in a unit group table created in said storage section; and a fifth step of processing the internal cell data stored in the internal format file under parallel processing control per unit group with reference to the internal cell identification number table and the unit group.