Patent ID: 7859038
Filing Date: 2010-12-28
Classification: H01L

Abstract:
1. A semiconductor device comprising: an element region; a semiconductor portion; an array of semiconductor regions including a protruding first semiconductor region extending in a first direction and a plurality of protruding second semiconductor regions extending in the first direction, the first semiconductor region and the second semiconductor regions being periodically arranged in a second direction, the first semiconductor region making up a semiconductor region located at the shortest distance from the semiconductor portion in the second direction, in the element region; a first isolation region formed between the semiconductor portion and the first semiconductor region; second isolation regions formed between the adjacent first and second semiconductor regions and between the adjacent second semiconductor regions, the second isolation regions being narrower than the first isolation region in the second direction; a liner film formed on an inner wall of trench making up each of the first and the second isolation regions; an SOD region formed on the liner film in the trench making up each of the first and the second isolation regions; a gate electrode including buried portions buried in intermediate portions of the first and the second semiconductor regions in the first direction, and an extending portion coupling the buried portions together and extending over the intermediate portion of each of the first and the second semiconductor regions in the second direction; a gate insulating film formed in contact with the buried portion of the gate electrode buried in the second semiconductor region; and a source region and a drain region formed in the second semiconductor region on both sides sandwiching the buried portion of the gate electrode in the first direction, wherein the second semiconductor region, the gate electrode, the gate insulating film, and the source and the drain regions make up a field effect transistor, and the buried portion of the gate electrode in the first semiconductor region is narrower than the buried portion of the gate electrode in the second semiconductor region in the second direction.