Patent ID: 6603446
Filing Date: 2003-08-05
Classification: G09G

Abstract:
A plasma display device having a display panel with first and second electrodes arranged in parallel with one another, and third electrodes arranged orthogonally to the first and second electrodes, discharge cells being selected with a scanning signal and an addressing signal to be applied to the second and third electrodes, the selected cells being caused to sustain discharge by applying sustaining discharge signals to the first and second electrodes respectively, sustaining discharge signals that are mutually out of phase being applied alternately to adjoining ones of the first electrodes and adjoining ones of the second electrodes, whereby first display cells, being defined between second electrodes and first electrodes on one side of the second electrodes, and second display cells, being defined between second electrodes and first electrodes on the other side of the second electrodes are interlaced, where the first display cells and second display cells are allowed alternately and repeatedly to glow for display, said plasma display device comprising a drive circuit driving the second electrodes in said plasma display device, said drive circuit comprising:a first drive circuit outputting a pulsating voltage to be applied in common to odd-numbered ones of the second electrodes; a second drive circuit outputting a pulsating voltage to be applied in common to even-numbered ones of the second electrodes; and a plurality of third circuits, associated with the second electrodes, applying the pulsating voltages output from said first drive circuit and said second drive circuit to the second electrodes, and applying the scanning signal selectively to the second electrodes, said plurality of third circuits comprising: a plurality of third odd circuits connected to the odd-numbered ones of the second electrodes, and a plurality of third even circuits connected to the even-numbered ones of the second electrodes, wherein said third odd circuits are integrated into one or more chips, and said third even circuits are integrated into one or more chips that are different from the one or more chips into which said third odd circuits are integrated.