Patent ID: 6107979
Filing Date: 2000-08-22
Classification: G09G,H04N

Abstract:
A monolithic programmable format pixel array device, comprising:a plurality of pixels forming a pixel array, said array having m rows of pixels and n columns of pixels formed upon a monolithic substrate;row address circuitry coupled to each of said rows of pixels for selectively and concurrently addressing said m rows of pixels, said row address circuitry including circuitry to select and control a subset of less than m said pixel rows and place the non-selected pixel rows in an inoperative state, said row address circuitry comprising a row decoder circuit providing a decoded output as a function of signals provided to an address input and a mapper responsive to said decoded output and having a function input, said mapper controlling which m pixel rows are addressed as a function of said decoded output from a given address input as a function of said function input to said mapper; andcolumn data load circuitry coupled to said n columns of pixels for loading data to predetermined ones of said columns.