Patent ID: 7403577
Filing Date: 2008-07-22
Classification: H03H,H04L

Abstract:
1. A system for receiving a complex signal comprising K channelized input signals and for respectively providing K channelized output signals, the system comprising, an input commutator for sampling the complex signal at a sampling rate of fs modulo M for decimating the complex signal by a decimation factor M to provide M sampled outputs, a bank of M filter blocks for respectively filtering the M sampled outputs and for respectively generating β filtered outputs as (β)×(M) filtered outputs, a bank of β FFT processors for transforming the (β)×(M) filter outputs into (β)×(K) transformed outputs, and a subsystem for processing the (β)×(K) transformed outputs into the K channelized output signals wherein, M is an integer, K is an integer, β is an integer, β is greater than one, K is greater than M, β is equal to K divided by the greatest common divider of K and M, and The FFT processors are K-point FFT processors.