Patent ID: 8865542
Filing Date: 2014-10-21
Classification: H01L

Abstract:
1. A method of forming an integrated circuit structure at a semiconducting surface of a body, the method comprising the steps of: etching a trench at a selected location of the surface; forming a dummy gate dielectric layer over the surface; then depositing a dummy gate polysilicon layer over the surface and into the trench; etching selected portions of the dummy gate polysilicon layer to define at least one dummy gate electrode overlying the dummy gate dielectric layer at a selected location of the surface, leaving a portion of the dummy gate polysilicon layer extending into the trench after the etching step; forming source/drain regions of a conductivity type opposite to the conductivity type of the surface, the source/drain regions disposed on opposite sides of the dummy gate electrode; forming a first interlevel dielectric layer at locations of the surface other than the locations of the at least one dummy gate electrode; removing the dummy gate electrode, leaving a portion of the dummy gate polysilicon layer extending into the trench after the removing step; depositing a high-k dielectric layer overall; then depositing a metal gate layer overall, the first metal gate layer comprising a metal or metal compound; and then planarizing the structure to remove the metal gate layer from top surfaces of the first interlevel dielectric layer.