Patent ID: 9224488
Filing Date: 2015-12-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array in which memory cells arranged at positions where bit lines and word lines cross each other are arranged on a semiconductor substrate; a sense amplifier configured to read data stored in one of the memory cells via the bit line in a read operation; a hookup region comprising a transfer transistor arranged between the memory cell array and the sense amplifier, one end of a current path of the transfer transistor being connected to a first interconnect formed between the semiconductor substrate and the bit line, the other end of the current path of the transfer transistor being connected to the sense amplifier; a guard ring region arranged between the memory cell array and the hookup region and enclosing the memory cell array, the guard ring region including a cell guard ring providing potential to the semiconductor substrate; a first contact plug arranged to overlap the guard ring region, the first contact plug electrically connecting the bit line to the first interconnect; a second interconnect formed between the semiconductor substrate and the first interconnect in the guard ring region, the second interconnect providing the potential to the cell guard ring; a third interconnect arranged in a same interconnect layer as the first interconnect and having the potential provided to the cell guard ring; and a second contact plug arranged between the second interconnect and the third interconnect and electrically connecting the second interconnect and the third interconnect.