Patent ID: 7341933
Filing Date: 2008-03-11
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: providing a capped polysilicon gate electrode over a substrate, the capped polysilicon gate electrode including: gate sidewalls, each sidewall comprising a first oxide layer, an offset nitride spacer, a cap oxide layer, a L-shaped nitride spacer and an oxide spacer, and a buffer layer located between a polysilicon gate electrode layer and a protective layer; forming source/drain regions in the substrate proximate the capped polysilicon gate electrode; removing the protective layer by a first etch process, wherein a first etchant used in the first etch process is selective to the buffer layer; removing the buffer layer by a second etch process, wherein a second etchant used in the second etch is selective to the polysilicon gate electrode including the gate sidewalls; and siliciding the polysilicon gate electrode layer to form a silicided gate electrode.