Patent ID: 7084017
Filing Date: 2006-08-01
Classification: G02F

Abstract:
1. Method for manufacturing a thin film transistor array substrate comprising steps of: after depositing a first metallic thin film on an insulating substrate, a first photolithography and etching step for forming a gate line; depositing a gate insulating film, a semiconductor film, an ohmic contact film and a second metallic thin film; a second photolithography step for forming a resist pattern of a source line, a source electrode, and a drain electrode; forming a region of said resist pattern serving as a semiconductor active layer in the thin film transistor in such a manner that thickness of said resist pattern in at least said region serving as a semiconductor active layer is smaller than that in said source line, said source electrode and said drain electrode in the second photolithography process after depositing a second metallic film; etching said second metallic film to form the source line, the source electrode and the drain electrode; removing the resist in the region serving as a semiconductor active layer and etching said second metallic film to remove said second metallic film on said region serving as a semiconductor active layer, removing said ohmic contact film on said region serving as a semiconductor active layer; a third photolithography and etching step of patterning the gate insulating film for forming a contact hole extending to the gate line; depositing a conducting film; and a fourth photolithography and etching step of forming a pixel electrode in such a manner that said pixel electrode is connected with said drain electrode.