Patent ID: 7239635
Filing Date: 2007-07-03
Classification: H04L

Abstract:
1. Apparatus for implementing frame header alterations on multiple concurrent frames comprising: a plurality of frame data alteration engines, each of said plurality of frame data alteration engines including a command decoder and an associated data aligner; a command buffer arbiter sequentially receiving frame alteration commands coupled to said plurality of frame data alteration engines, and said command buffer arbiter sequentially selecting one of said frame data alteration engines for each of said sequentially received frame alteration commands; each said command decoder receiving and decoding frame alteration commands and providing frame alignment commands and alteration instructions; and each said associated data aligner receiving frame data and coupled to said associated command decoder receiving said frame alignment commands; each said associated data aligner selectively latching data bytes of said received frame data responsive to said received frame alignment commands and sequentially providing an aligned frame data output of said predefined number of bytes; and an alteration engine coupled to said plurality of frame data alteration engines receiving said sequentially provided aligned frame data output of said predefined number of bytes and said alteration instructions from a selected one of said plurality of frame data alteration engines and, said alteration engine providing sequential altered frame data responsive to said received alteration instructions.