Patent ID: 6066177
Filing Date: 2000-05-23
Classification: G06F

Abstract:
A method of calculating a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for said logic circuit resulting from first and second power-source voltages being applied to said logic circuit, said method comprising the steps of:designating, as a power-source voltage coefficient, a ratio of said second power-source voltage to said first power-source voltage;designating, as a current coefficient, a ratio of a drain saturation current in said FET when said first power-source voltage is applied thereto to a drain saturation current in said FET when said second power-source voltage is applied thereto;calculating a first delay time, the first delay time being a delay time for said logic circuit when said first power-source voltage is applied theretocalculating a product of said first delay time, said power-source voltage coefficient, and said current coefficient; anddesignating the result of said product as a second delay time which is a delay time for said logic circuit when said second power-source voltage is applied thereto.