Patent ID: 9086450
Filing Date: 2015-07-21
Classification: G01R,H03K

Abstract:
1. A capacitor measurement circuit for measuring a capacitance of a test capacitor, the capacitor measurement circuit comprising: a first NMOS transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second NMOS transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; a current-measuring device configured to measure a first charging current and a second charging current of the test capacitor, wherein the first and the second charging currents flow to the test capacitor in opposite directions; a first PMOS transistor comprising a source coupled to the current-measuring device, and a drain coupled to a drain of the first NMOS transistor; a second PMOS transistor comprising a source coupled to the current-measuring device, and a drain coupled to a drain of the second NMOS transistor; and a control circuit configured to provide first non-overlay clock-cycle signals to gates of the first PMOS transistor and the first NMOS transistor, and second non-overlay clock-cycle signals to gates of the second PMOS transistor and the second NMOS transistor, wherein the first non-overlay clock-cycle signals are configured to turn on at most one of the first PMOS transistor and the first NMOS transistor, and the second non-overlay clock-cycle signals are configured to turn on at most one of the second PMOS transistor and the second NMOS transistor.