Patent ID: 6345008
Filing Date: 2002-02-05
Classification: G06F

Abstract:
A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D, the system comprising:a reprogrammable offset generator configured to determine a FIFO memory read address (RA) associated with a current FIFO read clock pulse and a FIFO memory write address (WA) associated with a current FIFO write clock pulse and further configured to receive a first programmable binary offset number (N) and a second programmable binary offset number (M) and therefrom update a first binary FIFO status flag signal when (WAâˆ’RA) is greater than N and update a second binary FIFO status flag signal when (WAâˆ’RA) is at least (Dâˆ’M), the reprogrammable offset generator further configured to convert [WA+(Dâˆ’Nâˆ’1)] to a first gray code offset signal and (WA+M) to a second gray code offset signal; and a flag generator in communication with the offset generator, the flag generator having a first input configured to receive the first gray code offset signal, a second input configured to receive the second gray code offset signal, a third input configured to receive the first binary FIFO status flag signal, and a fourth input configured to receive the second binary FIFO status flag signal, and further having a first binary status flag output (PAE) and a second binary status flag output (PAF), wherein the flag generator is responsive to the first gray code offset signal, the second gray code offset signal, the first binary FIFO status flag signal, and the second binary FIFO status flag signal such that PAE and PAF can be continuously updated in response to newly programmed binary offset number values for N and M following FIFO read or write operations.