Patent ID: 8081499
Filing Date: 2011-12-20
Classification: G11C,H01L

Abstract:
1. A semiconductor integrated circuit including an n-channel field-effect transistor having a gate insulating structure and a gate conductor stacked sequentially in an order mentioned on an n-type source region, an n-type drain region and a p-type substrate region, said n-channel field-effect transistor having electric characteristics, in a graph having an axis of ordinate standing for an absolute value of a drain current and an axis of abscissas standing for a potential difference voltage between the gate conductor and the p-type substrate region, such that a first graphic curve exhibiting dependency of the absolute value of the drain current on the potential difference voltage between the gate conductor and the p-type substrate, which is the potential of the gate conductor relative to the p-type substrate region, draws a first non-hysteresis curve or a first hysteresis curve that is a pseudo non-hysteresis curve when the potential difference voltage between the gate conductor and the p-type substrate region falls between a first voltage and a second voltage and, when the potential difference voltage between the gate conductor and the p-type substrate region falls between a third voltage and a fourth voltage, draws a second hysteresis curve, wherein said drain current is an electric current flowing into the n-type drain region from an external conductor that is connected to the n-type drain region when the n-type drain region is given a positive voltage relative to the n-type source region by the external conductor; in said first non-hysteresis curve, the first graphic curve obtained by increasing the potential difference voltage between the gate conductor and the p-type substrate region from the first voltage to the second voltage because the absolute value of the drain current generated when the second voltage is given is larger than that of the drain current generated when the first voltage is given, meaning that a resistance between the drain and the source is small, coincides with a second graphic curve obtained when the voltage is decreased from the second voltage to the first voltage; in said first hysteresis, the first and second graphic curves approximate but fail to coincide with each other; and in said second hysteresis curve, and a third graphic curve obtained when the potential difference voltage between the gate conductor and the p-type substrate region is increased from the third voltage to the fourth voltage does not coincide with a fourth graphic curve obtained when the voltage is decreased from the fourth voltage to the third voltage, and said semiconductor integrated circuit utilizing both the characteristics of the first non-hysteresis curve or the first hysteresis curve and the second hysteresis curve.