Patent ID: 7190019
Filing Date: 2007-03-13
Classification: H01L

Abstract:
1. An integrated circuit comprising: a first feature having a top surface having a first edge positioned higher than an adjacent area which is adjacent to the first edge; a second feature at least a portion of which overlies the first feature so as to overlie the first edge and the adjacent area, wherein the second feature is a conductive feature, wherein in top view the second feature has a first edge which is part of a lateral boundary of the second feature on a first side of the second feature, and a second edge which is part of the lateral boundary of the second feature on a second side of the second feature, the second side being opposite to the first side, wherein in top view the second edge runs along the first edge of the first feature, the second edge overlying said adjacent area and being laterally spaced from the first edge of the first feature, the first edge of the first feature being positioned between the first and second edges of the second feature in top view, wherein in top view the second feature has a narrower portion and a wider portion laterally adjacent to the narrower portion, wherein in top view the first and second edges of the second feature provide lateral boundary edges to each of the wider and narrower portions, wherein in top view the distance between the first and second edges of the second feature is smaller in the narrower portion than in the wider portion, at least a part of the wider portion overlying the first feature and the first edge; a dielectric overlying the second feature and having an opening over the wider portion of the second feature; a third feature overlying the dielectric and electrically contacting the second feature through the opening.