Patent ID: 7046556
Filing Date: 2006-05-16
Classification: G11C,H01L

Abstract:
1. An operation method for a twin MONOS memory comprising: polysilicon control gates on a substrate having an oxide-nitride-oxide (ONO) layer underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage; memory diffusions within said substrate between each two of said control gates wherein said memory diffusions are connected to adjacent diffusions alternately by a local wiring overlying said substrate; and metal bit lines crossing said control gates and isolated by shallow trench isolation (STI) lines to complete said Twin MONOS memory device wherein said operation method comprises programming by electron ejection and erasing by electron injection comprising: programming a selected memory cell by applying a high voltage to said control gate and a low voltage on a channel region underlying said control gate to eject electrons from said nitride portion of said ONO layer underlying said control gate through said top oxide portion of said ONO layer underlying said control gate; and erasing all memory cells by injecting electrons into said nitride portion of said ONO layer through said top oxide portion of said ONO layer.