Patent ID: 7961494
Filing Date: 2011-06-14
Classification: G11C,Y10T

Abstract:
1. A memory device comprising: a cross-point memory array comprising a plurality of array lines of a first type and a plurality of array lines of a second type, and a plurality of two-terminal memory cells each coupled between an associated array line of the first type and an associated array line of the second type; wherein each memory cell comprises a first bi-stable resistive element, a second bi-stable resistive element, and a current-steering device coupled together in series; wherein each bi-stable resistive element is settable from a high to a low resistance value, and resettable from a low to a high resistance value; wherein the first bi-stable resistive element, when in its high resistance state, is settable to its low resistance state by the passage of a set current therethrough, and when in its low resistance state, is resettable to its high resistance state by the passage of a reset current therethrough; wherein the second bi-stable resistive element, when in its high resistance state, is settable to its low resistance state by the passage of a set current therethrough, and when in its low resistance state, is resettable to its high resistance state by the passage of a reset current therethrough; and wherein the set current and reset current of the first bi-stable resistive element are both greater than the set current and reset current of the second bi-stable resistive element.