Patent ID: 9202561
Filing Date: 2015-12-01
Classification: G11C

Abstract:
1. A resistive memory device, comprising: a two-dimensional array of resistive memory cells for storing memory data (“data memory cells”), each resistive memory cell being accessed by a word line, a bit line and a source line, resistive memory cells sharing a common word line forming a row of the array and resistive memory cells sharing a common bit line and a common source line forming a column of the array, the data memory cell providing a cell current indicative of a programmed resistance of the data memory cell in response to being selected for access, the cell current having a first current value associated with a low resistance state and having a second current value associated with a high resistance state; a reference current generation circuit for providing a reference current, the reference current generation circuit comprising: a sense amplifier configured to sense a difference between the reference current and the cell current of a selected data memory cell and to generate an output signal indicative of the current difference, the output signal being indicative of the programmed resistance of the selected data memory cell storing memory data.