Patent ID: 7893700
Filing Date: 2011-02-22
Classification: G01R

Abstract:
1. A process of testing a plurality of semiconductor dies on a semiconductor wafer utilizing a tester configured to test the dies in groups, the process comprising: controlling as a logical whole provision of first test signals through a plurality of first communications channels to first probes organized into a plurality of N first probe die groups each configured to contact a different one of the dies of the wafer, wherein one of the first communications channels is a first common communications channel connected to probes in X of the N first probe die groups but not to probes in Y of the N first probe die groups, wherein X is at least two and Y is at least one; and controlling as a logical whole provision of second test signals through a plurality of second communications channels to second probes organized into a plurality of second probe die groups each configured to contact a different one of the dies of the wafer, wherein one of the second communications channels is a second common communications channel connected to probes in all of the second probe die groups and probes in each of the Y of the first probe die groups; wherein the first communications channels comprise a plurality of first dedicated communications channels each connected to one or more of the first probes in only one of the first probe die groups; and wherein the second communications channels comprise a plurality of second dedicated communications channels each connected to one or more of the second probes in only one of the second probe die groups.