Patent ID: 6268265
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A trench isolation method for fabricating a semiconductor integrated circuit comprising the steps of:forming a mask pattern exposing a predetermined area of a semiconductor substrate on the semiconductor substrate;etching using the mask pattern as an etching mask, thereby forming a trench at the predetermined area;forming a thermal oxide film on the sidewall and bottom of the trench;applying a flowable oxide such that the flowable oxide fills the trench, overflows onto the mask pattern, and forms a flowable oxide film thereon;etching a surface of the flowable oxide film until the mask pattern is exposed, thereby forming a flowable oxide film pattern;removing the exposed mask pattern to thereby form recessed grooves at the upper edges of the flowable oxide film pattern and expose active regions around the trench;thermally annealing the flowable oxide film pattern to thereby form an isolation film having a round surface without the grooves; andforming a gate oxide layer on the exposed active regions and gate electrodes on the gate oxide layer sequentially, wherein each gate electrode extends over the edge of the isolation film.