Patent ID: 8946037
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A method of forming an integrated circuit, the method comprising: forming an auxiliary layer over a substrate; forming at least one auxiliary region by patterning the auxiliary layer and removing material of the auxiliary layer; forming a first spacer element in a region in which material of the auxiliary layer has been removed; doping a first connection region having a first doping type of a transistor, the first spacer element and the auxiliary region serving as a mask; covering the first connection region with a covering material, wherein the covering material is a first insulating material; removing material of the auxiliary region; forming a second spacer element in a region in which material of the auxiliary region has been removed, wherein the second spacer element is a second insulating material; and doping a second connection region having a second doping type of the transistor, the first doping type being opposite the second doping type, the second spacer element and the covering material serving as a mask, wherein the first connection region and the second connection region form input/output nodes of a tunnel transistor.