Patent ID: 7115906
Filing Date: 2006-10-03
Classification: G02F,H01L

Abstract:
1. A thin film transistor array, comprising: a substrate; a plurality of scan lines disposed over the substrate; a plurality of data lines disposed over the substrate, wherein the substrate is defined into a plurality of pixel areas by the scan lines and the data lines; a plurality of thin film transistors driver by the scan lines and the data lines, wherein each thin film transistor is disposed in one of the pixel areas correspondingly; an etching stop layer disposed over the scan lines, wherein the etching stop layer has a plurality of openings; and a plurality of pixel electrodes, each pixel electrode is disposed in one of the pixel areas and is electrically connected to one of the thin film transistors correspondingly, wherein a portion of each pixel electrode is coupled to one of the scan lines through one of the openings to form a storage capacitor.