Patent ID: 6570454
Filing Date: 2003-05-27
Classification: H03L,H04J

Abstract:
A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, comprising:an acquisition phase locked loop (PLL) for each input, each said acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from said phase comparator, said first DCO of said acquisition PLL being in a feedback loop to supply an input to said phase comparator and said second DCO of said acquisition PLL having a control input to introduce a phase offset therein relative to said first DCO of said acquisition PLL and providing an output for said acquisition PLL; an output PLL having a phase comparator selectively connectable to the output of each of said acquisition PLLs, said output PLL having a first DCO providing an output for said circuit and a second DCO in a feedback loop providing a feedback signal to said phase comparator of said output PLL, said second DCO of said output PLL having a control input to introduce a phase offset therein relative to said first DCO of said output PLL; and a control unit for setting the phase of the second DCO of said acquisition circuit and the second DCO of said output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.