Patent ID: 7217995
Filing Date: 2007-05-15
Classification: H01L

Abstract:
1. A chip stacking structure, comprising: a leadframe having a plurality of leads disposed at a periphery thereof, each lead having a lead inner portion and a lead outer portion, each lead inner portion having a first surface, a second surface and lead via extending between the first surface and the second surface; a first chip stack comprising at least one chip, each chip in the first stack having an active surface, a back surface, a plurality of first bonding pads having bonding walls and being disposed on the active surface, and a plurality of first chip via having inner walls comprising insulating material and being at least partially formed by the bonding walls of the first bonding pads, the first chip via extending from the bonding walls of the first bonding pads through the chip to the back surface; a second chip stack comprising at least one chip, each chip in the second stack having an active surface, a back surface, a plurality of second bonding pads having bonding walls and being disposed on the active surface, and a plurality of second chip via having inner walls comprising insulating material and being at least partially formed by the bonding walls of the second bonding pads, the second chip via extending from the bonding walls of the second bonding pads through the chip to the back surface; and a conducting material formed to extend within and between the first chip via and lead via, and to extend within and between the second chip via and lead via, the conducting material electrically connecting bonding walls of first bonding pads to first surfaces of lead inner portions and electrically connecting bonding walls of second bonding pads to second surfaces of lead inner portions.