Patent ID: 6043131
Filing Date: 2000-03-28
Classification: H01L

Abstract:
A method of forming a capacitor for a DRAM over a bitline, the method comprising the steps of:forming a first polysilicon layer over said bitline;forming a TEOS layer over said first polysilicon layer,patterning and etching an opening through said TEOS layer;depositing a second polysilicon layer;etching back said second polysilicon layer and the first polysilicon layer to form sidewall spacers in said opening;using the first polysilicon layer and said sidewall spacers as a mask, etching through to said bitline to form a via and thereby also removing said TEOS layer;depositing a third polysilicon layer;patterning and etching the third polysilicon layer to form a bottom storage node of the capacitor; andforming a dielectric layer and a top conductive layer over the bottom storage node.