Patent ID: 7797618
Filing Date: 2010-09-14
Classification: H03M

Abstract:
1. An integrated circuit capable of conducting a decoding operation on a received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, having a constraint K, and having 2 M code states, where M is equal to K−1, the received sequence received according to a symbol rate associated with the encoded message sequence, the integrated circuit comprising: 2 a track buffer track buffer including 2 a voting unit configured to be capable of generating a decision bit based on the contents of the 2 wherein each of the 2 wherein the two path metric output lines in each of the 2 wherein the two path feedback lines in each of the 2 wherein the decoding operation includes a maximum a posteriori (MAP) decoding operation.