Patent ID: 8994397
Filing Date: 2015-03-31
Classification: G01R,H01L

Abstract:
1. A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a semiconductor die having topside bond pads wire-bonded by bond wires to said plurality of pins, and secured to said thermal pad, comprising: providing a leadframe sheet including a plurality of said packaged DUTs including support members that connect to said packaged DUTs, wherein said thermal pads are shorted to one another through said support members, and wherein said leadframe sheet is trimmed for electrically isolating said plurality of pins from one another; wire bonding at least one thermal pad to a leadframe grounding pin; electrically contacting active pins of said plurality of pins with a contactor; and automatically testing to identify shorts between said active pins and said thermal pads.