Patent ID: 8653878
Filing Date: 2014-02-18
Classification: H03K

Abstract:
1. A voltage switch circuit, comprising: an output circuit comprising a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor has a source terminal and a body terminal connected to a high voltage source, a drain terminal connected to an inverted output terminal of the voltage switch circuit, and a gate terminal connected to an output terminal of the voltage switch circuit, wherein the second PMOS transistor has a source terminal and a body terminal connected to the high voltage source, a drain terminal connected to the output terminal of the voltage switch circuit, and a gate terminal connected to the inverted output terminal of the voltage switch circuit; a first voltage-drop controlling circuit comprising a third PMOS transistor and a fourth PMOS transistor, wherein the third PMOS transistor has a body terminal connected to the high voltage source, a source terminal connected to the inverted output terminal, a drain terminal connected to a node e, and a gate terminal connected to a reference voltage source, wherein the fourth PMOS transistor has a body terminal connected to the high voltage source, a source terminal connected to the output terminal, a drain terminal connected to a node f, and a gate terminal connected to the reference voltage source; a second voltage-drop controlling circuit comprising a first NMOS transistor, a second NMOS transistor, a first bias voltage controlling circuit, and a second bias voltage controlling circuit, wherein the first NMOS transistor has a drain terminal connected to the node e and a control terminal of the first bias voltage controlling circuit, a gate terminal connected to an output terminal of the first bias voltage controlling circuit, and a body terminal and a source terminal connected to a node c, wherein the second NMOS transistor has a drain terminal connected to the node f and a control terminal of the second bias voltage controlling circuit, a gate terminal connected to an output terminal of the second bias voltage controlling circuit, and a body terminal and a source terminal connected to a node d; a third voltage-drop controlling circuit comprising a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a drain terminal connected to the node c, a gate terminal connected to a logic voltage source, and a body terminal and a source terminal connected to a node a, wherein the fourth NMOS transistor has drain terminal connected to the node d, a gate terminal connected to the logic voltage source, and a body terminal and a source terminal connected to a node b; and an input circuit comprising a fifth NMOS transistor, a sixth NMOS transistor, a third bias voltage controlling circuit, and a fourth bias voltage controlling circuit, wherein the fifth NMOS transistor has a drain terminal connected to the node a and an output terminal of the third bias voltage controlling circuit, a gate terminal connected to an input terminal of the voltage switch circuit, and a body terminal and a source terminal connected to a ground terminal, wherein the sixth NMOS transistor has a drain terminal connected to the node b and an output terminal of the fourth bias voltage controlling circuit, a gate terminal connected to an inverted input terminal of the voltage switch circuit, and a body terminal and a source terminal connected to the ground terminal.