Patent ID: 6331471
Filing Date: 2001-12-18
Classification: H01L

Abstract:
A method for forming integrated circuits, comprising:providing a substrate including a first part and a second part;forming a first dielectric layer (11) on said first part and on said second part of said substrate;defining a first conductor layer (12), serving as lower electrode of the capacitor, on said first dielectric layer (11) on said first part;forming a second dielectric layer (13) on said first conductor layer (12);forming a second conductor layer (14), serving as upper electrode of the capacitor, on said second dielectric layer (12);forming a third dielectric layer (15) on said second conductor layer (14) and on said first dielectric layer (11) on said second part;forming a fourth dielectric layer (16) on said third dielectric layer (15);forming a photoresist, wherein a pattern region is formed over said second part, on said fourth dielectric layer (16);etching said third and fourth dielectric layers (15)(16) over said second part;stripping said photoresist;forming a fifth dielectric layer (18) on said fourth dielectric layer (16) over both said first and said second parts; andremoving said fifth dielectric layer (18) till said fourth dielectric layer (16) being exposed.