Patent ID: 7657859
Filing Date: 2010-02-02
Classification: G06F

Abstract:
1. A method comprising: designing, by a computer, initial wiring routes for an integrated circuit design, wherein said designing establishes initial wiring widths and spacings and further establishes initial shapes and locations of said wiring routes and wherein said designing satisfies at least routing congestion constraints; computing, by said computer, an initial critical area of said integrated circuit design based on said initial wiring routes, critical area comprising a mathematical measure of the sensitivity of said integrated circuit design to random shorts and opens; adjusting, by said computer, said initial wiring widths and spacings in said initial wiring routes to produce modified wiring routes, wherein said modified wiring routes maintain said initial shapes and locations of said initial wiring routes such that topological relationships in said initial wiring routes and said modified wiring routes are the same; and performing, by said computer, an optimization process on said modified wiring routes that selects a final wiring route having a reduced critical area relative to said initial critical area such that said final wiring route produces an optimized yield.