Patent ID: 6618293
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A non-volatile memory device comprising:a plurality of memory arrays, each memory array having a plurality of blocks of flash memory cells, the flash memory cells in each block are arranged in rows; a controller to control memory operations to the memory arrays, the controller adapted to perform a first stage of erase pulses on a block of memory cells in erasing a predetermined number of rows in the block, wherein the controller counts the number of pulses needed to reach the predetermined number of rows erased in the first stage and the controller is further adapted to perform a second stage of erase pulses on the block to be erased such that a maximum number of erase pulses used by the controller in the second stage is a fraction of the number of erase pulses used in the first stage; and a register array comprising a plurality of register memory cells, wherein the controller stores data in each register memory cell that is associated with a row of memory cells in each block of memory cells to track rows of memory cells in blocks verified as being erased.