Patent ID: 8443030
Filing Date: 2013-05-14
Classification: G06F

Abstract:
1. A logic circuit for processing a floating point multiply-accumulate (FMAC) instruction, the logic circuit comprising: a register file; a hazard-checking block configured to detect whether the FMAC instruction contains a potential hazard that can cause a potential error in execution of the FMAC instruction due to data dependency; a multiplier configured to (i) receive an operand S a reorder buffer configured to store and reorder entries corresponding to a plurality of FMAC instructions, including the FMAC instruction; an adder configured to (i) add the resultant operand St and an operand Sd, and (ii) in response to adding the resultant operand St and the operand Sd, produce another resultant operand that represents a result of the FMAC instruction; a plurality of Sd paths comprising (i) a first Sd path from the register file to provide the operand Sd to the adder, (ii) a second Sd path from the adder to provide the operand Sd to the adder, (iii) a third Sd path from the reorder buffer to provide the operand Sd to the adder, and (iv) a fourth Sd path from a register buffer of the adder to provide the operand Sd to the adder; and a control unit configured to select a Sd path, from the plurality of Sd paths, to provide the operand Sd to the adder, wherein the control unit is further configured to