Patent ID: 7742355
Filing Date: 2010-06-22
Classification: G11C

Abstract:
1. A dynamic memory comprising: a plurality of memory cells; a refresh controller adapted to refresh all of the memory cells at a first rate and refresh a subset of the memory cells at a second rate; wherein the second rate is greater than the first rate; wherein the refresh controller is further adapted, for all the memory cells in the dynamic memory and at the second rate, to: 1) generate a refresh address, 2) read a value in a marker memory addressed using the refresh address, and 3) selectively refresh, depending on the read value, memory cells addressed using the refresh address; and wherein the memory cells are organized into a number of rows and a number of columns addressed by corresponding row and column addresses, the memory cells in a row are refreshed at substantially the same time, the refresh address is a row address, and the number of values in the marker memory is equal to the number of rows.