Patent ID: 6049855
Filing Date: 2000-04-11
Classification: G06F

Abstract:
A computer system comprising:first and second RAM modules for storing digital information, the first and second modules each including first and second sections, the first sections having logical addresses interleaved according to a first interleaving scheme and the second sections having logical addresses interleaved according to a second interleaving scheme; andfirst and second system controllers coupled to the first and second RAM modules, respectively, the first system controller having a first address decoder that allocates to the first RAM module a first set of addresses interleaved according to said first interleaving scheme in the first section and interleaved according to said second interleaving scheme in the second section, and the second system controller having a second address decoder that allocates to the second RAM module a second set of addresses interleaved according to said first interleaving scheme in the first section and interleaved according to said second interleaving scheme in the second section, the second set of addresses having no addresses in common with the first set of addresses, wherein said first interleaving scheme is different from said second interleaving scheme and wherein said first and second interleaving schemes are selected among word-by-word, cache line by cache line, block-by-block, and page-by-page interleaving schemes.