Patent ID: 8082398
Filing Date: 2011-12-20
Classification: G06F

Abstract:
1. A data processor comprising: a central processing unit performing instructions; a memory storing instructions and data; and a buffer maintaining part of instructions and data stored in the memory, wherein the central processing unit has a register, into which an intended value is set in accordance with execution of an instruction, and executes a specified instruction that generates an effective address of data by adding an offset to a value set to the register, wherein the buffer includes: wherein the instruction cache includes: wherein the address generator circuit generates an instruction prefetch address corresponding to an address of a line next to a line address latched by the line address latch, acquires a cache line address of a data cache corresponding to an offset designated by the specified instruction contained in an instruction stream latched by the line instruction latch, sequentially maintains cached line addresses, and adds a value of the register to a maintained cache line address to output a data prefetch address.