Patent ID: 6260134
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A predecode unit comprising:a decode circuit configured to decode a fixed number of instruction bytes in a clock cycle and to output a plurality of instruction length vectors, wherein each instruction length vector corresponds to a particular instruction byte and represents a length of a potential instruction assuming that the potential instruction starts at the particular instruction byte;a prefix find circuit configured to receive said fixed number of instruction bytes and to identify which of said fixed number of instruction bytes are possible prefixes by comparing the value of each instruction byte with a set of possible prefix byte values, wherein the prefix find circuit is configured to prospectively identify instruction bytes that are not prefix bytes as prefixes if the instruction bytes have values that are in the set of possible prefix byte values;a prefix accumulator circuit coupled to said decode circuit and said prefix find circuit and configured to output a plurality of position length vectors which identify an instruction length for potential start bytes, wherein said position length vectors are based on said instruction length vectors and are adjusted by said identified prefixes; anda tree circuit coupled to said prefix accumulation circuit and configured to generate and output a plurality of start bits based on the position length vectors from the prefix accumulator circuit and start byte information stored in the tree circuit from previously decoded instruction bytes, wherein said start bits identify one or more start bytes within said fixed number of instruction bytes.