Patent ID: 9012330
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A method for performing a double patterning process of a semiconductor structure, comprising the following steps: depositing a first, a second and a third layer on a substrate sequentially from bottom to top, wherein the second and the third layer have very selective etching rates from one another; depositing a first photoresist layer on the third layer, trimming the resist into a first pre-pattern; depositing a first oxide layer; etching the deposited first oxide layer into spacers on each side of the resist; stripping the resist fully, thereby obtaining a first patterned mask made of the remaining spacers; etching said first pattern into the third layer with selectivity to the second layer below to thereby forming a patterned third layer, wherein the second layer act as an etch stop layer; after etching said first pattern into the third layer, depositing a second photoresist layer on the patterned third layer; trimming the resist into a cross pre-pattern; depositing a second oxide layer; etching the deposited second oxide layer into spacers on each side of the patterned resist; stripping the second photoresist layer fully, thereby obtaining a second patterned mask made of the remaining spacers; performing an etching process with selectivity to the spacers and to the patterned third layer to etch the second layer and first layer, thereby achieving a final cross pattern of contact holes in the second layer and the first layer; and after forming the final cross pattern of contact holes in the second layer and the first layer, etching away the remaining oxide spacers and the patterned third layer, thereby obtaining a final contact printing mask.