Patent ID: 7839715
Filing Date: 2010-11-23
Classification: H03K,H03M

Abstract:
1. A method of separating an early clock pulse and a late clock pulse into two different latches, comprising: generating said early clock pulse through a bit line; in response to said early clock pulse rising, sending a first data waveform to a fourth data waveform; in response to a third data waveform rising, turning off an early precharge; in response to said turning off of said early precharge and in response to a fifth data waveform dropping, rising an eighth data waveform if said first data waveform equals a value of 1; in response to a sixth data waveform rising, opening a first pulse latch; beginning a falling period of said early data pulse; in response to said sixth data waveform falling, closing said first pulse latch; after said closing of said first pulse latch and in response to said third data waveform falling, turning on said early precharge; in response to said turning on of said early precharge, rising said fifth data waveform; generating said late clock pulse through said bit line; in response to said late clock pulse rising, sending a second data waveform to said fourth data waveform; in response to said third data waveform rising, turning off a late precharge; in response to said turning off of said late precharge and in response to said fifth data waveform dropping, rising a ninth data waveform if said second data waveform equals a value of 1; in response a seventh data waveform rising, opening a second pulse latch; beginning a falling period of said late clock pulse; in response to said seventh data waveform falling, closing said second pulse latch; after said closing of said second pulse latch and in response to said third data waveform falling, turning on said late precharge; and in response to said turning on of said late precharge, rising said fifth data waveform.