Patent ID: 6849483
Filing Date: 2005-02-01
Classification: H01L

Abstract:
1. A method of forming a semiconductor device having a control gate, a source region, and a drain region comprising the steps of: (a) providing a substrate having a first type of conductivity; (b) forming a channel between the source and drain region for carrying said charge carriers between the source and drain regions, said channel being doped in two separate operations such that: wherein said second type of conductivity is opposite to said first type of conductivity; wherein as a result of said first channel doping operation and said second channel doping operation said channel region as formed has a net first type of conductivity; (c) forming a charge trapping region that has in interface with said channel, said charge trapping region having charge trapping sites which temporarily trap charge carriers along said interface and permit the device to operate with a negative differential resistance characteristic; and wherein said charge trapping sites are derived at least in part from said first channel impurities forming a charge trap distribution that is substantially concentrated at said interface.