Patent ID: 6038644
Filing Date: 2000-03-14
Classification: G06F

Abstract:
A multiprocessor system comprising:a plurality of processor units each including at least one processor;at least one memory unit shared by said plurality of processor units;a cache memory provided in correspondence to each processor unit;a logic provided in correspondence to each processor unit and responsive to a memory access request therefrom for generating a first cache coherent processing request related to a first memory address designated by said memory access request;a caching status memory provided in correspondence to each processor unit for storing a processor unit caching status for discriminating whether each of said plurality of processor units holds data belonging to each of a plurality of memory areas belonging to said memory unit;a destination information generation logic provided in correspondence to each processor unit for generating destination information designating part of said plurality of processor units which hold at least one data belonging to a first memory area to which said first memory address belongs; andan interconnection network for connecting said plurality of processor units and said memory unit, said interconnection network comprising a parallel transfer network for transferring said first cache coherent processing request to said part of said plurality of processor units in response to said destination information.