Patent ID: 6049245
Filing Date: 2000-04-11
Classification: G11C

Abstract:
A power reduction circuit, comprising:a first switching device that couples a first operating voltage terminal and a second operating voltage terminal, wherein the first switching device is controlled by a first signal;a second switching device that couples a third operating voltage terminal and a fourth operating voltage terminal, wherein the second switching device is controlled by a second signal;a signal transfer gate logic that couples the second and the fourth operating voltage terminals to selectively output one of second and fourth operating voltages;a first voltage drop device that couples the first and the second operating voltage terminals, wherein the first voltage drop device is selectively activated based on first and second operating modes, and wherein the first voltage drop device has a first prescribed turn-on resistance; anda second voltage drop device that couples the third and the fourth operating voltage terminals, wherein the second voltage drop device is selectively activated based on the first and the second operating modes, and wherein the second voltage drop device has a second prescribed turn-on resistance.