Patent ID: 6823402
Filing Date: 2004-11-23
Classification: G06F,H04L

Abstract:
A data processing system comprising:a plurality of digital signal processor subsystems, each including a first peripheral direct memory access unit; a high level data link controller coupled to the first peripheral direct memory access unit, the high level data link controller including; a processor for processing received signal packets; a memory unit for storing processed data signal groups; and channel block unit, the channel block unit selecting one of a plurality of control signals, the selected control signal determined by the address signal group of a received packet signal group, each control signal corresponding to a one the plurality of digital signal processor subsystems; and a second peripheral direct memory access unit including; a plurality of buffer storage units, each buffer storage unit coupled to a one of the peripheral first direct memory access units; and a switch unit responsive to a selected control signal from the channel block unit for coupling the memory unit to a buffer storage unit, the buffer storage unit and the selected control signal corresponding to digital signal processor subsystem.