Patent ID: 8803578
Filing Date: 2014-08-12
Classification: H03K

Abstract:
1. A pulse width adjusting circuit comprising: a pulse delaying circuit for inputting an inputted pulse signal and for outputting a plurality of different delayed pulse signals; a transmission gate for inputting the inputted pulse signal and controlling the passage of the inputted pulse signal in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals; a pulse width setting circuit connected to the transmission gate for setting a pulse width of an outputted pulse signal generated on the basis of the inputted pulse signal passing through the transmission gate; and wherein the pulse delaying circuit is an even number of four or more inverters connected in series, three different delayed pulse signals are outputted from the first, second and third inverters counting from the output end, and the two delayed pulse signals outputted from the first and second inverters are applied, respectively, to the first gate and second gate of the transmission gate.