Patent ID: 6584016
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A structure comprising:an array of non-volatile memory cells arranged along rows and columns, each memory cell having a drain region spaced apart from a source region to form a channel region therebetween, the drain region having a greater depth than the source region, each memory cell further having a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline; a plurality of data lines, each data line being coupled to the drain region of at least a portion of a column of cells; a plurality of source lines, each source line being coupled to a source region of a plurality of cells along at least a portion of a row of cells; and wherein injection of hot electrons from a portion of the channel region near the source region to the floating gate is induced in a selected memory cell in the array by applying a first voltage to a selected data line to which the drain of the selected memory cell is coupled, a second positive voltage to a word line to which the selected gate of the selected memory cell is coupled, and a third positive voltage to a source line to which the source of the selected memory cell is coupled, wherein said injection of hot electrons increases a threshold voltage of the selected cell.