Patent ID: 6034432
Filing Date: 2000-03-07
Classification: H01L,Y10S

Abstract:
A semiconductor memory including a plurality of memory cells of a static type including a pair of thin film transistors which become load elements, and a pair of drive transistors, comprising:a first wiring layer formed of metal and becoming a power line;a thin-film second wiring layer provided below said first wiring layer, said second wiring layer being formed of a first polycrystalline silicon and becoming source, drain and channel regions of said thin film transistors, and a power supplying line to said memory cells;a first insulating layer between said first and second wiring layers and having a first contact hole for connecting said first and second wiring layers;a third wiring layer which is provided below said second wiring layer and which becomes an etching stopper layer for the prevention of penetration in said first contact hole forming area, said third wiring layer being formed of a second polycrystalline silicon; anda second insulating layer between said second and third wiring layers and having a second contact hole which is provided below said first contact hole, and which directly connects said second wiring layer and said third wiring layer;wherein first conductivity-type impurities are introduced into said second wiring layer, and wherein said etching stopper layer formed by said third wiring layer is non-doped at least in said first contact hole forming area and wherein second conductivity-type impurities which differ from said first conductivity-type impurities in polarity are introduced into said third wiring layer in an area of said memory cells and said first conductivity-type impurities are diffused from said second wiring layer to said non-doped area of said etching stopper layer.