Patent ID: 6107658
Filing Date: 2000-08-22
Classification: G11C,H01L

Abstract:
A voltage control method for a writing process in a non-volatile semiconductor memory device including a plurality of NAND strings, each having a plurality of electrically erasable programmable memory cells connected in series, and a selection gate transistor connected to an end on a bit line side of the NAND string, the method comprising the steps of:applying a first predetermined voltage from a first bit line to a selected NAND string, and applying a program inhibit voltage from a second bit line to a non-selected NAND string which shares control gate electrodes with the selected NAND string;setting a gate voltage of the selection gate transistor to a predetermined potential; andshifting a control gate voltage of a selected memory cell in the selected NAND string to a first potential, shifting a control gate voltage of at least one of the memory cells adjacent to the selected memory cell and located on both sides of the selected memory cell to a second potential, and shifting a control gate voltage of each memory cell in the selected NAND string, other than the selected memory cell and the adjacent memory cells located on both sides of the selected memory cell, to a third potential, wherein the first potential is greater than third potential which is greater than second potential which is greater than 0.