Patent ID: 8941267
Filing Date: 2015-01-27
Classification: H02J

Abstract:
1. A bi-phase data signal decoding method used in a high-power induction-type power supply system consisting of a supplying-end module and a receiving-end module for decoding a data code of a data signal, comprising steps of: (a) set a built-in forward phase comparator and a built-in reverse phase comparator of a supplying-end microprocessor of the supplying-end module to initialize interruption data analysis and to clear register data; (b) wait for an interruption triggering; (c) determine whether or not the interruption triggered, and then proceed to step (e) when positive or step (d) when negative; (d) determine whether or not a maximum data length counter is overflow, and then return to step (a) when positive or step (b) when negative; (e) judge a phase to be a forward phase or a reverse phase, and then proceed to step (f) when the forward phase is judged, or step (g) when the reverse phase is judged; (f) a first trigger is judged to be a forward phase, thus, set to turn off reverse phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (f) to be a forward phase triggering until that a new setting is made, and then proceed to step (h); (g) the first trigger is judged to be a reverse phase, thus set to turn off forward phase interruption triggering and to drive the maximum data length counter to start counting for enabling every interruption triggered during a time period of step (g) to be a reverse phase triggering until that a new setting is made, and then proceed to step (h); (h) check a signal length to be in match with a set length or not, and then proceed to step (i) when positive or step (j) when negative; (i) the signal length is checked in match with the set length, thus, set bit data and then proceed to step (k); (j) the signal length is checked not in match with the set length, thus, a signal is determined to be a noise, and then clear existing data and re-set to return to step (a); (k) check whether or not a set number of bits has been received, and then proceed to step (l) when negative or step (m) when positive; (l) receiving of the set number of bits is not completed, thus, wait for a next interruption triggering and then return to step (c); (m) the set number of bits has been completely received, thus, set data into a data register, and then initialize a built-in data analysis program and then run step (n) and step (a) synchronously; (n) end data receiving.