Patent ID: 7939423
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A method for manufacturing a non-volatile semiconductor memory device structure, comprising: forming element isolation/insulation films that partition element-forming regions and selecting gate areas in a semiconductor substrate; dividing and separating a plurality of floating gates, wherein the process comprising: forming a field oxide film by a shallow trench isolation(STI) method for dividing the semiconductor substrate into an active region and a non-active region; applying a mask Recess (RCS) to cover the element-forming regions before removing a STI pad nitride in the shallow trench isolation(STI) method, and thereby performing an additional oxide etch for recessing the field oxide film in the select gate areas; removing the mask RCS and the STI pad nitride; depositing a first gate insulating film and a floating gate material in sequence on the semiconductor substrate; applying a chemical mechanical polish(CMP) process to both the element-forming regions and select gate areas for dividing the floating gate material into isolated floating gates in the element-forming regions, wherein the floating gate material in the select gate areas is continuous; forming a second gate insulating film on said isolated floating gates and said floating gate material; forming control gates on said isolated floating gates and said floating gate material via said second gate insulating film; and self-aligning source and drain diffusion layers with said control gates.