Patent ID: 6261923
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of forming shallow trench isolation in the fabrication of an integrated circuit device comprising:depositing a pad oxide layer on the surface of a semiconductor substrate;depositing a first nitride layer overlying said pad oxide layer;etching through said first nitride layer and said pad oxide layer where they are not covered by a mask to provide openings wherein the surface of said semiconductor substrate is exposed wherein there is at least one wide opening and at least one narrow opening;etching a narrow trench into said semiconductor substrate where it is exposed within said narrow opening and etching a wide trench into said semiconductor substrate where it is exposed within said wide opening;depositing an oxide layer overlying said first nitride layer and filling said narrow trench and said wide trench wherein said narrow trench is completely filled and wherein there is formed a trough over said wide trench;depositing a second nitride layer over said oxide layer;polishing away said second nitride layer with a polish stop at said oxide layer whereby said second nitride layer is removed except where it lies within said trough;etching back said oxide layer where it is not covered by said second nitride layer using CHF.sub.3, CF.sub.4, and O.sub.2 chemistry wherein said oxide layer is planarized except where said oxide layer underlies said second nitride layer;removing said second nitride layer within said trough whereby oxide horns forming said trough extend vertically upward from said planarized oxide surface;thereafter polishing away said oxide layer with a polish stop at said first nitride layer whereby said oxide horns are removed; andremoving said first nitride layer and said pad oxide layer completing said formation of said shallow trench isolation in said fabrication of said integrated circuit device.