Patent ID: 6798067
Filing Date: 2004-09-28
Classification: H01L

Abstract:
An integrated circuit chip comprising a metal layer structure having at least three substantially horizontal metal layers and a plurality of substantially vertical via holes; each of said metal layers comprising at least one metal line; each of said via holes electrically connecting a metal line of one metal layer with a metal line of another metal layer; the integrated circuit chip further comprising a first tap located in a first one of said metal layers and a second and third tap located in a second one of said metal layers; the metal lines and via holes forming a signal path electrically connecting said first tap with said second tap; the metal lines in each metal layer being arranged in a respective first one of at least two predefined configurations; said at least two predefined configurations comprising for each metal layer a second predefined configuration arranging the metal lines in said metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path electrically connecting said first tap with said third tap.