Patent ID: 9214209
Filing Date: 2015-12-15
Classification: G11C,H03K

Abstract:
1. A semiconductor device, comprising: N (N is an integer equal to two or more) number of address lines; N number of data lines; and a plurality of storage sections, each of the storage sections including: wherein the N number of address lines of one storage section are respectively connected to the data lines of the N number of other storage sections, and the N number of data lines of one storage section are respectively connected to the address lines of the N number of other storage sections, wherein the address decoder includes a row decoder and a column decoder, wherein the row decoder decodes an address inputted from the M (M is an integer equal to five or less) number of address lines, and outputs the word selection signal to the word line, and wherein the column decoder decodes an address inputted from the L (L is an integer of N−5) number of address lines and outputs a data selection signal which selects the N number of data lines outputted from the plurality of storage elements.