Patent ID: 6038386
Filing Date: 2000-03-14
Classification: G06F

Abstract:
A method for controlling power consumption of a programmable logic device, the programmable logic device including a plurality of resources that are programmable to implement a user-defined logic function, each resource being programmable to operate in either a high power mode or a low power mode, the method comprising the steps of:placing and routing the user-defined logic function such that a plurality of paths of the logic function are assigned to associated resources of the programmable logic device;identifying a group of said resources associated with at least one path of the logic function which is constrained by a user-defined timing specification;identifying a sub-group of resources from said group which, when operated in the low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of said at least one path; andsetting the plurality of resources such that the sub-group of resources operate in the low power mode, and a remainder of said resources of the group operate in the high power mode.