Patent ID: 8003301
Filing Date: 2011-08-23
Classification: G03F

Abstract:
1. A manufacturing method for a semiconductor device, wherein said semiconductor device comprises in the same layer: an isolated patterned area arranged with low density where intervals between adjacent areas are relatively wide; and periodically patterned areas arranged with high density where intervals between adjacent areas are relatively narrow, wherein said isolated patterned area includes first and second sides, the first and second sides are adjacent to each other and form a corner portion of an external angle of less than 180-degrees, said manufacturing method comprises the steps of: (a) exposing regions corresponding to a first divided pattern and first thinned out patterns formed by using a first mask having a first mask pattern, the first divided pattern includes said first side and is obtained by dividing said isolated patterned area, and the first thinned out patterns are obtained by thinning out said periodically patterned areas; and (b) exposing regions corresponding to a second divided pattern and second thinned out patterns formed by using a second mask having a second mask pattern, the second divided pattern includes said second side and is obtained by dividing said isolated patterned area, and the second thinned out patterns are obtained by thinning out said periodically patterned areas, wherein said first mask pattern and said second mask pattern have a region which overlaps in the vicinity of a divided portion, wherein the isolated patterned area is an active pattern, a part of the active pattern is formed by the first mask pattern, a part of the active pattern is formed by the second mask pattern, and the region which overlaps in the vicinity of the divided portion is masked in common through exposure to light by using the first and second mask patterns.