Patent ID: 7786568
Filing Date: 2010-08-31
Classification: H01L

Abstract:
1. A semiconductor package primarily comprising: a substrate having an internal surface, an external surface, a depression formed in the internal surface, and a slot penetrating from the external surface to the depression; a first chip partially embedded in the depression and protruding from the internal surface of the substrate, wherein the first chip has a first active surface, a first back surface, and a plurality of sides between the first active surface and the first back surface; a chip-bonding adhesive formed inside the depression to adhere the first chip, wherein the chip-bonding adhesive is confined in the depression in a manner to fill a plurality of gaps between the sides of the first chip and a plurality of inwalls around the depression to partially cover the sides of the first chip; a plurality of first bonding wires passing through the slot to electrically connect the first chip to the substrate; an encapsulant formed on the internal surface of the substrate and in the slot to encapsulate the first chip and the first bonding wires; and a plurality of external terminals disposed on the external surface of the substrate.