Patent ID: 8527847
Filing Date: 2013-09-03
Classification: B23B,H03M,Y10T

Abstract:
1. A channel switching signal generating circuit comprising: an iterative decoding count output unit that outputs an iterative decoding count indicating the number of times of iterative execution of a predetermined error correcting operation; a channel switching condition determining means for determining unit that determines whether a channel switching condition is met, on the basis of the iterative decoding count output from said iterative decoding count output unit; a switch signal output unit that outputs a switch signal indicating channel switching, when said channel switching condition determining unit determines that the channel switching condition is met; and a maximum value signal output unit that outputs an iterative decoding count maximum value signal indicating that the iterative decoding count has reached a predetermined maximum value, wherein said channel switching condition determining unit determines whether an occurrence probability at which said maximum value signal output unit outputs the iterative decoding count maximum value signal is higher than a predetermined value, and determines that the channel switching condition is met, when determining that the occurrence probability of the iterative decoding count maximum value signal is higher than the predetermined value.