Patent ID: 7551152
Filing Date: 2009-06-23
Classification: G09G

Abstract:
1. A display including pixel circuits that are each formed at an intersection between a signal line and a scan line so that the pixel circuits are disposed in a matrix, each of the pixel circuits comprising: a first transistor of which gate is coupled to the scan line, one of a source and a drain of the first transistor being coupled to the signal line; a second transistor of which gate is supplied with a bias voltage, one of a source and a drain of the second transistor being coupled to a positive voltage supply; a third transistor of which gate is coupled to the other of the source and the drain of the first transistor, the third transistor being coupled to the other of the source and the drain of the second transistor; a capacitor of which one end is coupled to the other of the source and the drain of the first transistor, the other end of the capacitor being supplied with a ramp signal that increases and decreases with time; and an organic electro-luminescence thin film that is driven to emit light by the first, second and third transistors and the capacitor, wherein,