Patent ID: 6294422
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method for forming a semiconductor device which has a first area in which a plurality of first MOS transistors are formed and arranged with a first distance between gate electrodes in a channel length direction, and a second area in which a plurality of second MOS transistors having diffusion layers of impurity concentration higher than that of said first MOS transistors are formed and arranged with a second distance between gate electrodes longer than the first distance between the gate electrodes in the channel length direction, comprising the steps of:forming a conductive film on said first and second areas;selectively etching said conductive film on said first area to form and arrange a plurality of first gate electrodes with the first distance between said gate electrodes;selectively doping impurity into said first area between said first gate electrodes to form first diffusion layers;forming first gate side-wall insulating films on the side walls of said first gate electrodes;selectively etching said conductive film on said second area to form and arrange a plurality of second gate electrodes with the second distance between the gate electrodes;selectively doping impurity into said second area between said second gate electrodes to form second diffusion layers;forming second gate side-wall insulating films which are formed thicker than said first gate side-wall insulating films and formed of the same type of film as that of said first gate side-wall insulating films on the side walls of said second gate electrodes; andselectively doping impurity into portions of said second diffusion layers which are not covered with said second gate side-wall insulating films to form third diffusion layers.