Patent ID: 6381550
Filing Date: 2002-04-30
Classification: G11C

Abstract:
A method of utilizing fast chip erase to screen endurance rejects during testing of a Flash memory device, wherein the Flash memory device is divided into multiple sectors, the method comprising:(a) selecting at least two sectors from the multiple sectors; (b) determining if all cells in the at least two sectors are programmed; (c) programming the cells that are not programmed; (d) repeating steps (b) and (c) until all cells in the at least two sectors are programmed or until a first predetermined time is exceeded at which time the testing of the Flash memory device is terminated; (e) determining if all cells in the at least two sectors are erased when all cells in the at least two sectors are programmed; (f) erasing all the cells in the at least two sectors if there are cells that are not erased in the at least two sectors; (g) determining if there are overerased cells in the at least two sectors at the completion of step (f); (h) go to step (e) until all cells in the at least two sectors are erased then go to step (i) or until a second predetermined time is exceeded at which time the testing of the Flash memory device is terminated; (i) correcting overerased cells in the at least two sectors if overerased cells are detected during step (g); (j) go to step (e) until the cells in the at least two sectors are erased with no overerased cells then go to step (k) or until a third predetermined time is exceeded at which time the testing of the Flash memory device is terminated; and (k) monitoring a total time from step (f) until the completion of step (i) and terminating the testing if the total time in this step (k) exceeds a fourth predetermined time.