Patent ID: 7061005
Filing Date: 2006-06-13
Classification: H01L

Abstract:
1. A phase-change random access memory device comprising: a first insulation layer formed on a semiconductor substrate including a predetermined bottom structure, the first insulation layer having first contact holes for exposing a predetermined portion of the semiconductor substrate and a second contact hole for exposing a predetermined portion of the semiconductor substrate formed between the first contact holes; conductive plugs for filling the first contact holes; a bit line formed on the first insulation layer in order to fill the second contact hole; a second insulation layer formed on the first insulation layer including the bit line; a top electrode, a phase-change layer pattern, and a hard mask layer, which are sequentially formed on a predetermined portion of the second insulation layer; a third insulation layer formed on the second insulation layer so as to cover both sidewalls of the top electrode, the phase-change layer pattern and the hard mask layer, while exposing an upper surface of the hard mask layer; third contact holes formed in the third and second insulation layers so as to expose the conductive plugs; fourth contact holes formed between the hard mask layer and the third insulation layer so as to expose both surfaces of the phase-change layer pattern; first and second bottom electrode contacts for filling the third and fourth contact holes, respectively; and bottom electrodes formed on the third insulation layer such that the bottom electrodes are connected to the first and second bottom electrode contacts, respectively.