Patent ID: 8149035
Filing Date: 2012-04-03
Classification: H03L

Abstract:
1. A phase locked loop (PLL) having two or more outputs, the PLL comprising: a voltage controller oscillator (VCO) that outputs an output signal having a first frequency at an output terminal; a first frequency divider electrically coupled to the output terminal creating a first divided output signal having a first divided output frequency; a shifter circuit having a shifter circuit input electrically coupled to the output terminal and a shifter circuit output, the shifter circuit also including an activation input that receives an activation signal, the shifter circuit causing at least one pulse of the output signal to be suppressed at the shifter output upon receipt of the activation signal; and a second frequency divider electrically coupled to the shifter circuit output creating a second divided output signal based on the shifter circuit output and having a second divided output frequency; wherein the first divided output frequency is less than the first frequency and greater than or equal to the second divided output frequency.