Patent ID: 6639424
Filing Date: 2003-10-28
Classification: H03K

Abstract:
A level shifting logic circuit, comprising:a pair of logic gates each having an output and configured such that only one output of said pair is applied at a tune to a respective one of a pair of output switching circuits coupled to receive said outputs of said logic gates; a pair of inputs, which transition in a first voltage range, to control said logic gates to produce a third output which transitions in a second voltage range, in response to the switching of said output switching circuits; wherein said output switching circuits include first and second driving transistors, said first driving transistor being a p-channel transistor, and said second driving transistor being an n-channel transistor, said first and second driving transistors being serially connected with the series connection providing said third output; and a pair of series connected holder transistors coupled between first and second voltages which define said second voltage range, the series connection point of said holder transistors being connected to said third output.