Patent ID: 6801073
Filing Date: 2004-10-05
Classification: H03K

Abstract:
A delay circuit comprising:an input switching device for receiving an input signal and outputting an intermediate signal; a first limiting device controlled by said intermediate signal and coupled to said input switching device for limiting speed of falling edge transitions from said input signal through said input switching device; a second limiting device controlled by said intermediate signal and coupled to said input switching device for limiting speed of rising edge transitions from said input signal through said input switching device; an RC network for receiving said intermediate signal and outputting a delayed intermediate signal; an output switching device for receiving said delayed intermediate signal and outputting an output signal; a first bypass device coupled to said first limiting device and said output signal for bypassing said first limiting device and presetting said intermediate signal; and a second bypass device coupled to said second limiting device and said output signal for bypassing said second limiting device and resetting said intermediate signal.