Patent ID: 6456992
Filing Date: 2002-09-24
Classification: G06N

Abstract:
A semiconductor arithmetic circuit, comprising:an inverter circuit group comprising a plurality of inverter circuits each respectively having at least a first input gate and a second input gate; said plurality of inverter circuits comprising at least one neuron MOS transistor each respectively having a semiconductor region of one conductivity type disposed on a substrate, a source region and a drain region each of an opposite conductivity type to said one conductivity type and being disposed on said semiconductor region, and a floating gate electrode in an electrically floating state; means for applying a variably selective input signal to the first input gate of at least a respective one of said plurality of inverter circuits; and a logical operation circuit having at least one input and an output, said logical operation circuit being operative to receive output signals from said plurality of inverter circuits and to provide an output signal at the output thereof, the output signal from said logical operation circuit being operatively applied to the second input gate of each respective one of said plurality of inverter circuits; wherein said semiconductor arithmetic circuit being selectively configurable to enable the identification of a particular one of said plurality of inverter circuits to which is being applied an input signal having a voltage value which satisfies a selected relative value ranking criteria involving a comparison with the voltage values respectively associated with each other input signal being applied to other ones of said plurality of inverter circuits and wherein the identification of said particular one inverter circuit occurring by the formation of a feedback oscillation loop includes said logical operation circuit and said particular one inverter circuit.