Patent ID: 6744272
Filing Date: 2004-06-01
Classification: G11C

Abstract:
A test circuit adapted to interface between a tester and a circuit to be tested, the tester outputting a clock signal at a clock frequency, said test circuit comprising:a) a frequency multiplication circuit adapted to receive the clock signal from the tester and produce a high-frequency clock signal, said high-frequency clock signal equivalent to the clock signal multiplied by a frequency multiplication factor; b) a control signal input bus for receiving various external control signals for the circuit to be tested from the tester, where each control signal is received in parallel from the tester via a plurality of control lines whose number is respectively equal to the frequency multiplication factor; c) a parallel/serial converter which is clocked with the high-frequency clock signal, said parallel/serial converted connected to the control signal input bus and is adapted to output each control signal to the circuit to be tested via a control line of a control signal output bus; and d) a decoder circuit adapted to clock with the high-frequency clock signal and further adapted to produce internal control signals for the test circuit on the basis of the control signals which are on the control signal input bus.