Patent ID: 6730556
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A method of forming an integrated circuit device comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type that is complementary to the first conductivity type, the method comprising the steps of:forming a first gate stack, the first transistor comprising the first gate stack; forming a second gate stack, the second transistor comprising the second gate stack; implanting a first drain extension region at a first distance relative to the first gate stack, self-aligned to a thickness of insulating material including a first oxide layer, a nitride layer, and a second oxide layer along a sidewall of the first gate stack; the first transistor comprising the first drain extension region; implanting a second drain extension region at a second distance relative to the second gate stack, self-aligned to a thickness of insulating material including the first oxide layer, and the nitride layer along a sidewall of the second gate stack; the second transistor comprising the second drain extension region; and the thickness of the insulating material along the sidewall of the first gate stack being larger than the thickness of the insulating material along the sidewall of the second gate stack, and the first distance being greater than the second distance.