Patent ID: 6326695
Filing Date: 2001-12-04
Classification: G11C,H01L

Abstract:
A twisted bit line structure for an integrated memory circuit, comprising:a pair of untwisted bit line trace segments, associated with an untwisted bit line;a first pair of twisted bit line trace segments located adjacent and substantially parallel to the pair of untwisted bit line trace segments, the first pair of twisted bit line trace segments being collinear with one another;a second pair of twisted bit line trace segments located adjacent and substantially parallel to the first pair of twisted bit line trace segments, the second pair of twisted bit line trace segments being collinear with one another;an untwisted bit line interconnection between said untwisted bit line segments, said untwisted bit line interconnection being contained on a different level from a level on which the untwisted bit line trace segments are contained; andtwisted bit line connections, each connected between one of the first pair of twisted bit line trace segments and one of the second pair of twisted bit line trace segments, the twisted bit line connections located away from the untwisted bit line interconnection so as not to pass over or under the untwisted bit line interconnection.