Patent ID: 7354835
Filing Date: 2008-04-08
Classification: H01L

Abstract:
1. A method of fabricating a CMOS transistor comprising: (a) providing a semiconductor substrate including active regions of first and second conductivity type MOS transistors respectively; (b) respectively forming gate insulating layers and gate electrodes of the first and second conductivity type MOS transistors on each of the active regions; (c) implanting first conductivity type impurity ions into the active region of the first conductivity type MOS transistor using the gate electrode of the first conductivity type MOS transistor as an ion implantation mask, and implanting second conductivity type impurity ions and amorphous ions into the active region of the second conductivity type MOS transistor using the gate electrode of the second conductivity type MOS transistor as an ion implantation mask to amorphize the active region of the second conductivity type MOS transistor; (d) forming spacers at sidewalls of the gate electrodes; (e) etching the active regions exposed by the gate electrodes and the spacers to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth in the active region of the second conductivity type MOS transistor, the second depth being greater than the first depth; (f) performing selective epitaxial growth on the first and second recessed regions to form an elevated epitaxial layer filling the first recessed region and extending to a level above an upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region; and (g) respectively forming first and second conductivity type junction regions in the elevated epitaxial layer and the recessed epitaxial layer.