Patent ID: 6696872
Filing Date: 2004-02-24
Classification: G06F,H03L,Y10S

Abstract:
A delay locked loop for a semiconductor device, comprising:a phase detector, wherein the phase detector receives a reference clock signal and a feedback clock signal and provides, as a function of the reference clock signal and the feedback clock signal, a delay control signal; a delay circuit in communication with the phase detector, wherein the delay circuit receives the reference clock signal and the delay control signal and provides, as a function of the reference clock signal and the delay control signal, a delayed clock signal; an off chip driver in communication with the delay circuit, wherein the off chip driver selectively receives one of the delayed clock signal and a data output signal and provides, as a function of the delayed clock signal, an interim feedback clock signal; a receiver in communication with the phase detector and the off chip driver, wherein the receiver receives the interim feedback clock signal and provides, as a function of the interim feedback clock signal, the feedback clock signal.