Patent ID: 7554831
Filing Date: 2009-06-30
Classification: G11C

Abstract:
1. An integrated circuit device, comprising a read only memory matrix, comprising cells organized in columns with associated bit lines and rows with associated word lines, the matrix comprising data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells; a differential sense amplifier having a first input, a second input, and a control input for controlling activation and deactivation of amplification by the sense amplifier; a coupling circuit coupled between the bit lines and the first input, for controllably permitting charge sharing between a selectable one of the bit lines and the first input; a reference circuit coupled to the second input and arranged to controllably activate driving of a reference voltage at the second input; a timing circuit arranged to signal operation in a first phase, when the word lines have selected a row of the matrix, followed by a second phase, the timing circuit controlling the coupling circuit to permit charge sharing between the input and the selectable one of the bit lines in the first phase, and the timing circuit in the second phase controlling the coupling circuit to prevent said charge sharing, making the reference circuit deactivate driving the reference voltage, and activating amplification by the differential sense amplifier only when said charge sharing has been prevented and said driving has been deactivated.