Patent ID: 6391703
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method of forming an integrated circuit on a silicon substrate having a substrate top surface, including a logic portion and an embedded DRAM portion and comprising the steps of:forming a set of trench capacitors in a set of memory cell locations in said embedded DRAM portion, said set of trench capacitors each having a center electrode and an oxide collar disposed between said center electrode and a pass transistor associated therewith; forming a set of STI in both said logic portion and said embedded DRAM portion; simultaneously forming a set of transistor gate stacks on said silicon substrate, including gate oxide, gate electrode and sidewalls, in both said logic portion and said embedded DRAM portion; simultaneously etching said silicon substrate, selective to dielectric, outside said transistor gate stacks in both said logic portion and said embedded DRAM portion, whereby source/drain locations in said silicon substrate are recessed in a set of source-drain recesses; simultaneously filling said set of source-drain recesses outside said transistor gate stacks in both said logic portion and said embedded DRAM portion with an isolation dielectric, whereby said set of source-drain recesses in said set of source/drain locations in said silicon substrate are filled with said isolation dielectric; recessing said isolation dielectric in said set of source-drain recesses such that a residual layer of dielectric remains in said set of source-drain recesses, thereby exposing said center electrode; depositing and forming a layer of conductive material in said set of source/drain recesses, whereby transistors in said logic portion form sources and drains isolated from said substrate by said residual layer and transistors in said DRAM portion simultaneously form a conductive strap between said transistor body and said center electrode.