Patent ID: 6853059
Filing Date: 2005-02-08
Classification: H01L

Abstract:
1. A packaged semiconductor, comprising: a semiconductor chip having an upper surface, a perimeter and a bottom surface; a plurality of input bond pads and output bond pads on said upper surface along said perimeter electrically connected to said semiconductor chip; a leadframe having a chip paddle, said chip paddle having a top surface, a half-etched section, and a bottom surface, said chip paddle being bonded to said semiconductor chip by an adhesive, said leadframe having a plurality of tie bars, said plurality of tie bars being connected to said corners of said chip paddle, said plurality of tie bars externally extending from said chip paddle, said leadframe having a plurality of dam bars; a plurality of leads connected to said leadframe; a plurality of wires electrically connected to said plurality of leads and said semiconductor chip; and encapsulation material encapsulating said semiconductor chip, said plurality of conductive wires, said chip paddle, and said plurality of internal leads to form a package body; wherein said chip paddle has a plurality of through-holes in said half-etched section of said chip paddle for increasing the bonding strength of said encapsulation material in said package body.