Patent ID: 7118976
Filing Date: 2006-10-10
Classification: H01L

Abstract:
1. A method for fabricating a MOSFET in a semiconductor device, comprising: forming an isolation layer on a semiconductor substrate and forming a capping layer thereon; forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selective epitaxial growth; forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially; forming a spacer dielectric layer on sidewalls of said gate electrode and patterning said gate dielectric layer by using said gate electrode and said spacer dielectric layer as a mask, after the gate electrode is formed; forming a source/drain plug spaced apart from the both sides of said gate electrode on said epitaxial active region by another selective epitaxial growth; forming a source/drain by a donant diffusion from said source/drain plug into said epitaxial active region on which said source/drain plug is formed; removing said spacer dielectric layer and a portion of said gate dielectric layer, after said source/drain is formed; forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.