Patent ID: 6208275
Filing Date: 2001-03-27
Classification: H03M

Abstract:
A concatenator having a node N into which is transmitted in sequence a series of n-bit bytes, to each of which n-bit bytes is appended a particular one of a predetermined number of position bytes, comprising:an array of a predetermined number of XOR gates, equal in number to said predetermined number of position bytes, first input connections of each of which are connected in parallel to a position buffer into which said position bytes are to be sequentially transmitted;an array of switches SW equal in number to said predetermined number of XOR gates, n-bit input channels of each of which are connected in parallel to an input buffer, wherein each of said n-bit bytes is to be sequentially transmitted into said input buffer in synchrony with said transmission into said position buffer of that one said position byte that is appended to each of said n-bit bytes;an array of reference buffers, equal in number to said predetermined number of XOR gates, and having output lines connected to second input connections of said XOR gates;an array of n-bit buffers, equal in number to said predetermined number of XOR gates, each of said n-bit buffers being connected through respective n-bit channels to an output of respective ones of said switches SW; andtriggering means that cause a common reading of said array of n-bit buffers upon reception into said concatenator of a number of n-bit bytes equal to said pre-selected number of XOR gates.