Patent ID: 7352625
Filing Date: 2008-04-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a first select gate line which is provided along a first direction, a gate electrode of a first select transistor being connected to the first select gate line; a second select gate line which is provided along the first direction, a gate electrode of a second select transistor being connected to the second select gate line; and a plurality of word lines which are provided between the first select gate line and the second select gate line along the first direction, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is a word line adjacent to the first select gate line is read, voltages of the word lines are increased after a voltage of the first select gate line is increased and a voltage of the second select gate line is increased after the voltages of the word lines are increased, and when data in a memory cell connected to a second adjacent word line which is a word line adjacent to the second select gate line is read, the voltages of the word lines are increased after the voltage of the second gate line is increased and a voltage of the first select gate line is increased after the voltages of the word lines are increased.