Patent ID: 6208562
Filing Date: 2001-03-27
Classification: G11C

Abstract:
A memory configuration, comprising:a digital memory that includes:memory cells;at least one data line for writing data to said memory cells and for reading data from said memory cells;address lines for addressing said memory cells; anda switching unit having an active state in which said switching unit inverts a signal on a line selected from the group consisting of said data line and said address lines, said switching unit having an inactive state in which said switching unit leaves the signal unchanged,said active state and said inactive state defining states; said digital memory having a first operating mode, in which said switching unit is in the same one of said states for writing data to said memory cells and for reading data from said memory cells; andsaid digital memory having a second operating mode, in which said switching unit is in one of said states for writing data to said memory cells and is in another one of said states for reading data from said memory cells.