Patent ID: 8460976
Filing Date: 2013-06-11
Classification: H01L

Abstract:
1. A manufacturing method of SOI high-voltage power devices, comprising: (A) forming a first oxide layer in a section on a surface of the SOI substrate, which comprises a bottom layer, an buried oxide layer, and a top silicon successively, to reduce the thickness of the top silicon in the corresponding section of the SOI substrate; (B) removing the first oxide layer to expose the corresponding part of the top silicon under the first oxide layer, to form a depressed area in the corresponding section of an upper surface of the SOI substrate; (C) forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); (D) performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed, wherein the P-type region and the N-type region are a drain region and a source region of the high-voltage power device respectively; (E) forming a third oxide layer by deposition on a drift region of the structure where the P-type and the N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and (F) forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device.