Patent ID: 7485911
Filing Date: 2009-02-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region; at least one channel trench disposed in the cell region of the semiconductor substrate; at least one first capacitor trench disposed in the first peripheral circuit region of the semiconductor substrate and at least one second capacitor trench disposed in the second peripheral circuit region of the semiconductor substrate; a gate electrode disposed in the cell region of the semiconductor substrate and filling the channel trench; a first upper electrode disposed in the first peripheral circuit region of the semiconductor substrate and filling at least the first capacitor trench; a second upper electrode disposed in the second peripheral circuit region of the semiconductor substrate and filling at least the at least one second capacitor trench; a gate dielectric layer interposed between the channel trench and the gate electrode; a first dielectric layer interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode, and having the same thickness as the gate dielectric layer; a second dielectric layer interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode, and having a different thickness from the first dielectric layer; and a source region and a drain region disposed in the semiconductor substrate of the cell region at both sides of the gate electrode, respectively.