Patent ID: 6235623
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method of forming integrated circuit contact holes, comprising the steps of:forming on an integrated circuit substrate, a first conductive pattern, a first interlayer insulating film on the first conductive pattern, a second conductive pattern on the first interlayer insulating film opposite the first conductive pattern and a second interlayer insulating film on the second conductive pattern opposite the first interlayer insulating film;forming a blocking layer pattern on the second interlayer insulating film opposite the second conductive pattern that overlies, is of same pattern as and is at least as wide as, the second conductive pattern; andselectively etching the first and second interlayer insulating films relative to the blocking layer pattern and the second conductive pattern to form a plurality of contact holes that expose the first conductive pattern.