Patent ID: 6621431
Filing Date: 2003-09-16
Classification: H03M

Abstract:
An analog-to-digital converter circuit arrangement comprising:an analog-to-digital converter configured to convert an analog input signal (x(t)) into a corresponding digital output signal (y(k)) during a normal operation; control circuitry configured to calibrate the analog-to-digital converter during a calibration operation, wherein conversion of the analog input signal (x(t)) into the digital output signal (y(k)) during normal operation is interrupted for the calibration operation; a digital interpolation unit configured to obtain and emit a scanning value of the digital output signal (y(k)) corresponding to a momentary analog input signal (x(t)) by interpolating adjacent scanning values of the digital output signal (y(k)) adjacent to the scanning value during the calibration operation; and a digital delay circuit configured to compensate a group delay time of the digital interpolation unit and emit the digital output signal during normal operation of the analog-to-digital converter.