Patent ID: 6163048
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A non-volatile semiconductor device comprising:a semiconductor substrate;data transmission bit lines arranged on said substrate;a memory cell section including a plurality of memory units, each connected on a first end to one of said bit lines and on a second end to a common reference node, at least one said memory unit comprising addressable memory transistors, each of said memory transistors having a source, node a drain, node a gate, and a charge storage layer that has programmable memory states that produce a first depletion threshold voltage of magnitude less than a magnitude of a supply voltage when the memory transistor is programmed and a different threshold voltage when the memory transistor is erased;and at least one timer circuit to generate an output logic signal to request a data refresh operation no later than when charge stored on charge storage layers associated therewith can no longer be detected, said timer circuit comprising a transistor timing element having a source, a drain, a gate, and a charge storage layer that has programmable memory states.