Patent ID: 9218513
Filing Date: 2015-12-22
Classification: G06G,H03D

Abstract:
1. A mixer having input nodes for receiving signals to be mixed, and comprising at least one gate arranged to selectively couple an input node of the mixer to an output node, the gate being arranged to be driven by a sampling clock signal, the gate comprising at least one FET having a gate node and a source node, the mixer having circuitry for applying a voltage between the gate and source nodes of the at least one FET in the on state, which voltage is independent of signals at the mixer input nodes, the mixer further having first and second supply rails comprising a positive rail and a reference rail, and providing, in use, first and second supply rail voltages, wherein the circuitry is configured to apply a voltage substantially equal to the sum of the voltage at the input node and the positive supply rail minus a common mode voltage to the gate node of the at least one FET.