Patent ID: 7861026
Filing Date: 2010-12-28
Classification: G06F

Abstract:
1. A signal relay device for connecting an integrated circuit (IC) to an external memory controller, the external memory controller connecting with an external memory, the IC comprising one or more function modules and one or more memory blocks, and the signal relay device comprising a bus arbiter and a burst access engine connected to the bus arbiter, wherein: the signal relay device uses the bus arbiter to grant ownership of a bus based on an arbitration mechanism; a hosting function memory transmits a command signal and a corresponding internal memory address signal to the burst access engine via the arbiter; and the burst access engine uses a burst access finite state machine (FSM) to exchange signals with the bus arbiter and the external memory controller, and uses four first in first out (FIFO) queues to store different information related to the command signal and the internal memory address signal.