Patent ID: 8504799
Filing Date: 2013-08-06
Classification: G06F

Abstract:
1. A read only memory (ROM) data patch circuit for replacing ROM data stored in N modified ROM data blocks with patch data stored in N random access memory (RAM) patch blocks based on patch information, N being a natural number, the ROM data patch circuit comprising: a data patch detecting unit configured to generate N offset select signals and an address select signal, the N offset select signals indicating which selected block among the N modified ROM data blocks a read ROM address belongs to; a RAM address generating unit configured to generate a read RAM address corresponding to the read ROM address based on the N offset select signals and N offset signals, the N offset signals indicating a difference between an address of a corresponding selected block and an address of a of the patch blocks; and an address selecting unit configured to output one of the read ROM address and the read RAM address based on the address select signal, wherein the patch information comprises N start addresses of the N modified ROM data blocks, N data block lengths, N offsets and a patch enable signal for controlling a patch operation, each of the N offsets representing each difference between an address of the modified ROM data block and an address of the corresponding RAM patch block.