Patent ID: 6060360
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate comprising an N-well doped with a first, N-type of dopant, by the steps comprising:forming a tunnel oxide layer over said substrate,then forming a floating gate electrode layer comprising a polysilicon layer over said tunnel oxide layer and then doping said floating gate electrode layer with said first, N-type of dopant,then forming an interelectrode dielectric layer over said floating gate electrode,then forming a control gate electrode layer including a layer composed of polysilicon over said interelectrode dielectric layer and then counterdoping said control gate electrode with an opposite, P-type of dopant,then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer and, said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, andthen performing an ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite, P-type of source/drain dopant symmetrically self-aligned with said gate electrode stack,whereby said source region and said drain region are self-aligned with said gate electrode stack.