Patent ID: 6807100
Filing Date: 2004-10-19
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:first and second electrically rewritable nonvolatile semiconductor memory cells; and a write control circuit, which supplies a plurality of programming pulses simultaneously to the first and second memory cells, the write control circuit supplies: a first pre-programming pulse simultaneously to the first and second memory cells independently of the write statuses thereof; a second pre-programming pulse, after the supply of the first pre-programming pulse, simultaneously to the first and second memory cells independently of the write statuses thereof, the second pre-programming pulse having a potential higher than the first pre-programming pulse by a first potential difference; and staircase programming pulses, after the supply of the second pre-programming pulse, simultaneously to the first and second memory cells, the staircase programming pulses having an initial voltage lower than the second pre-programming pulse and increasing the voltage at a rate of a second potential difference per pulse, the second potential difference being smaller than the first potential difference.