Patent ID: 8797434
Filing Date: 2014-08-05
Classification: H01L,H04N

Abstract:
1. A CMOS image sensor including an array of unit pixels, each unit pixel being connected to a first output signal line and a second output signal line which are arranged in each column of the array, wherein the unit pixel comprises: a photodiode; a first processing unit connected to the photodiode, that amplifies a first floating diffusion voltage formed by being provided with electrons accumulated in the photodiode during a first exposure integration time and outputs the amplified voltage to the first output signal line; a second processing unit connected to the photodiode, that amplifies a second floating diffusion voltage formed by being provided with electrons accumulated in the photodiode during a second exposure integration time which is separated from the first exposure integration time and outputs the amplified voltage to the second output signal line; and an erasing transfer gate transistor arranged between the photodiode and a power supply voltage, the erasing transfer gate transistor is kept turned off during both first and second exposure integration times wherein electrons accumulate in the photodiode, otherwise the erasing transfer gate transistor discharges electrons accumulated in the photodiode, so as to reset the photodiode; wherein the electrons are transferred to and stored in the first floating diffusion before beginning the second exposure integration and then the electrons again accumulate in the photodiode and are transferred to and stored in the second floating diffusion.