Patent ID: 6281046
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method of forming an integrated circuit chip package on a wafer level, comprising:providing a silicon wafer having a plurality of bonding pads disposed on a first surface thereof;depositing a conductive material on the plurality of bonding pads;depositing an underfill-flux material on the first surface of the wafer;securing an interposer substrate, composed of a dielectric material and a plurality of metallized traces, to the layer of underfill-flux material to form a wafer/interposer assembly, the interposer substrate including a plurality of metallized through-holes which are aligned to the plurality of bonding pads and including a plurality of openings on a surface of the interposer substrate over the plurality of metallized traces;forming an electrical connection between the plurality of through-holes and the plurality of bonding pads;attaching a plurality of I/O interconnects through the plurality of openings to the metallized traces of the interposer substrate; anddicing the wafer/interposer assembly into a plurality of individual integrated circuit chip packages.