Patent ID: 6792554
Filing Date: 2004-09-14
Classification: G06F,H03L

Abstract:
A method of controlling a clock signal comprising the steps of:outputting a system clock signal utilizing a system clock generator that is in a first clock domain; providing a clock control signal from a storage device that is coupled to said system clock generator utilizing distribution logic, said storage device being in a second clock domain, said first and second clock domains differing by a time delay introduced by said distribution logic; synchronously and deterministically transferring said clock control signal from said second clock domain to said first clock domain utilizing signal transfer logic that includes a plurality of interconnected memory storage circuits, said clock control signal being received within said signal transfer logic which outputs an adjusted clock control signal; and outputting a controlled clock signal that is controlled by said adjusted clock control signal, said controlled clock signal having a deterministic number and size of clock pulses.