Patent ID: 6915369
Filing Date: 2005-07-05
Classification: G06F,G09G,H04N

Abstract:
1. A data transfer apparatus that comprises: a first group of bus lines configured to transfer data bits between a first processing device and a corresponding first memory module; a second group of bus lines configured to transfer data bits between a second processing device and a corresponding second memory module; a group of cross-bus lines configured to transfer data bits between the fist group of bus lines and the second group of bus lines via bus bridges; and a memory management unit configured to receive memory access requests from the first and second processing devices and to responsively configure the bus bridges to steer address and data signals accordingly; wherein each group of bus lines includes two unidirectional bit lines for each data bit, and wherein the bus bridges include a multiplexer for each outgoing bit line that selects from three other incoming bit lines.