Patent ID: 8154503
Filing Date: 2012-04-10
Classification: G09G

Abstract:
1. A source driver for driving a display having a plurality of pixels spatially arranged in a matrix form, and a plurality of data lines, each data line being associated with pixels of a corresponding pixel column, comprising: (a) a first pair of switches, a second pair of switches, and a third pair of switches, controlled by a control signal; (b) a first level shifter having a first input for receiving an input data, a second input for receiving a power supply voltage, a third input for receiving a first middle voltage, and an output for outputting a first level-shifted signal of the input data; (c) a second level shifter having a first input for receiving the input data, a second input for receiving a second middle voltage, a third input for receiving a ground voltage, and an output for outputting a second level-shifted signal of the input data; (d) a first digital-to-analog converter with a positive polarity (PDAC) having a first input electrically coupled to the output of the first level shifter for receiving the first level-shifted signal therefrom, a second input for receiving the power supply voltage, a third input for receiving the first middle voltage, a fourth input for receiving a Gamma voltage, and an output for outputting a first converted signal; (e) a second digital-to-analog converter with a negative polarity (NDAC) having a first input electrically coupled to the output of the second level shifter for receiving the second level-shifted signal therefrom, a second input for receiving the second middle voltage, a third input for receiving the ground voltage, a fourth input for receiving the Gamma voltage, and an output for outputting a second converted signal; (f) a first analog circuit having a first input electrically coupled to the output of the PDAC and the output of the NDAC through one of the first pair of switch for receiving the first converted signal from the PDAC or the second converted signal from the NDAC, a second input for receiving the power supply voltage, a third input for receiving the ground voltage, and an output for outputting a first amplified signal; (g) a second analog circuit having a first input electrically coupled to the output of the PDAC and the output of the NDAC through the other of the first pair of switch for receiving the first converted signal from the PDAC or the second converted signal from the NDAC, a second input for receiving the power supply voltage, a third input for receiving the ground voltage, and an output for outputting a second amplified signal; (h) a first output stage with a positive polarity having a first input electrically coupled to the output of the first analog circuit and the output of the second analog circuit through one of the second pair of switch for receiving the first amplified signal from the first analog circuit or the second amplified signal from the second analog circuit, a second input for receiving the power supply voltage, a third input for receiving the first middle voltage, and an output for outputting a first data signal; and (i) a second output stage with a negative polarity having a first input electrically coupled to the output of the first analog circuit and the output of the second analog circuit through the other of the second pair of switch for receiving the first amplified signal from the first analog circuit or the second amplified signal from the second analog circuit, a second input for receiving the second middle voltage, a third input for receiving the ground voltage, and an output for outputting a second data signal,  wherein each odd data line of the plurality of data line are electrically coupled to the output of the first output stage and the output of the second output stage through one of the third pair of switch for receiving the first data signal from the first output stage or the second data signal from the second output stage;  wherein each even data line of the plurality of data line are electrically coupled to the output of the first output stage and the output of the second output stage through the other of the third pair of switch for receiving the first data signal from the first output stage or the second data signal from the second output stage; and  wherein the third pair of switches is configured such that each odd data line of the plurality of data line receives one of the first and second data signals, while each even data line of the plurality of data line receives the other of the first and second data signals, and vice versa.