Patent ID: 6476424
Filing Date: 2002-11-05
Classification: H01L,Y10S

Abstract:
A semiconductor memory device comprising a plurality of memory cells, each memory cell having a drive transistor, a word transistor and an active region of a conductive type, the drive transistor and the word transistor being provided next to each other in the active region, wherein a relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by (DT.W/WT.W)/(WT.L/DT.L)=0.93 and wherein the channel width of the drive transistors is equal to the channel width of the word transistors while the channel length of the word transistor is larger than the channel length of the drive transistors.