Patent ID: 8983790
Filing Date: 2015-03-17
Classification: G01R,G06F,G11C

Abstract:
1. A system for gathering data for debugging a circuit-under-test, comprising: a trigger-and-capture circuit coupled to the circuit-under-test for receiving a plurality of signals from the circuit-under-test, wherein the trigger-and-capture circuit is configured to assert a trigger signal in response to one or more of the plurality of signals matching a trigger condition; a data selector coupled to receive from the trigger-and-capture circuit the trigger signal and a plurality of subsets of the plurality of signals from the circuit under test, the data selector configured to increment an occurrence count value in response to assertion of the trigger signal, and further configured to select and output data of one of the plurality of subsets of signals in response to the value of the occurrence count; a data compressor coupled to the trigger-and-capture circuit and configured to loss-lessly compress the plurality of signals into compressed data; a direct memory access (DMA) controller coupled to the data compressor and configured to generate a plurality of write requests for writing the compressed data to a memory integrated circuit (IC) die and a plurality of read requests for reading the compressed data from the memory IC die; and a memory controller coupled to the DMA controller and configured to perform the pluralities of write and read requests.