Patent ID: 7566658
Filing Date: 2009-07-28
Classification: H01L

Abstract:
1. A method comprising: forming sequentially an etch stop layer, a first silane layer, an insulating layer and a second silane layer over a semiconductor substrate; etching selectively the first silane layer, the insulating layer and the second silane layer to form at least a first via hole and a second via hole; depositing a filler to bury the first via hole and the second via hole; forming a first etching mask over the second silane layer to expose the first via hole; using the first etching mask, forming a first trench by etching the second silane layer, the insulating layer and the filler, the first trench connecting at a first predetermined depth to the first via hole; forming a second etching mask over the second silane layer to expose the second via hole; using the second etching mask, forming a second trench by etching the second silane layer, the insulating layer and the filler, the second trench connecting at a second predetermined depth to the second via hole, wherein the second predetermined depth of the second trench is different from the first predetermined depth of the first trench; removing the filler remaining in the first via hole and the second via hole; removing the etch stop layer exposed at the bottom of the first and second via holes; and forming metal interconnections to fill the via holes and the trenches.