Patent ID: 7736969
Filing Date: 2010-06-15
Classification: H01L,Y10S

Abstract:
1. A method of forming a memory cell, comprising the steps of: providing a semiconductor substrate; providing at least one vertical transistor within the substrate, wherein the at least one vertical transistor has first, second and third doped regions; forming a bit line below a surface of the substrate and in connection with the first doped region of the at least one vertical transistor, the forming of the bit line comprising forming a metal-comprising layer below the surface of the substrate and adjacent the first doped region followed by annealing of the metal-comprising layer; forming a word line on sidewalls of the at least one vertical transistor so that the word line and the bit line form an angle of about ninety degrees relative to each other; and providing a capacitive structure in electrical connection with the third doped region of the at least one vertical transistor.