Patent ID: 6495891
Filing Date: 2002-12-17
Classification: H01L

Abstract:
A semiconductor device comprising:source and drain regions spaced apart from each other in a semiconductor layer; a gate insulating film formed on a surface of the semiconductor layer between the source and drain regions; a gate electrode formed on the gate insulating film, said gate insulating film being interposed between the semiconductor layer and the gate electrode; and a channel region, formed in contact with at least a portion of the gate insulating film, including a region where carriers move between the source and drain regions, an impurity concentration of said channel region being higher at an end portion of a surface depletion layer, formed of a MIS structure comprising the gate electrode, the gate insulating film and the semiconductor layer, than at an interface between the semiconductor layer and the gate insulating film; wherein the impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.