Patent ID: 6441662
Filing Date: 2002-08-27
Classification: H03L

Abstract:
A DLL circuit comprising:a control clock generation circuit generating a first control clock according to a reference clock and a second control clock having a phase difference with respect to set first control clock; a phase comparator comparing a phase of a delay clock with the phase of the reference clock; a filter providing a control signal applied with weight corresponding to a comparison result of said phase comparator; a counter control circuit driven in synchronization with said first control clock to generate a counter control signal according to said control signal; a counter driven in synchronization with said second control clock to count up/down according to said counter control signal, providing first and second addresses and a smallest address signal that is rendered active when said first and second addresses take the smallest values, and sets the address to the smallest value at a reset signal; a first delay circuit generating first and second signals having a phase difference of a predetermined amount according to said reference clock, and generating a fine adjustment clock whose phase is present between the phase of said first signal and the phase of said second signal according to said generated first and second signals and said first address; and a second delay circuit delaying said fine adjustment clock by an integral multiple of said predetermined amount to output said delay clock according to said second address; said counter control circuit providing a counter control signal rendered active to force said counter to count up when said reset signal is input, or when an activated smallest address signal and an output signal of said filter that causes said counter to count down are input.