Patent ID: 6887769
Filing Date: 2005-05-03
Classification: H01L

Abstract:
1. A three-dimensional (3-D) integrated chip system, comprising: a first wafer including one or more integrated circuit (IC) devices, a first plurality of metallic bonding pads deposited via an interlevel dielectric (ILD) for wafer-to-wafer bonding and electrical interconnection, the first plurality of metallic bonding pads having a variety of heights, and an ILD recess surrounding the first plurality of metallic bonding pads deposited via the ILD; and a second wafer including one or more integrated circuit (IC) devices, a second plurality of metallic bonding pads deposited via an interlevel dielectric (ILD) for wafer-to-wafer bonding and electrical interconnection, the second plurality of metallic bonding pads having a variety of heights, and an ILD recess surrounding the second plurality of metallic bonding pads deposited via the ILD, wherein the first plurality of metallic bonding pads is bonded to the second plurality of metallic bonding pads to establish electrical connections between active IC devices on the adjacent wafers, wherein the ILD is a high-temperature deformable dielectric used to allow the bonding areas to be self-leveling to facilitate the bonding of wafers having bonding pads of a variety of heights, wherein the high-temperature deformable dielectric is SILK which exhibits a glass transition near 450° C. while the metallic bonding pads exhibit a bonding temperature of about 400° C., and wherein the ILD recesses are created by a Chemical Mechanical Polish (CMP) or by selectively etching the ILD surrounding the metallic bonding pads deposited via the ILD.