Patent ID: 6839729
Filing Date: 2005-01-04
Classification: G06F

Abstract:
1. A method comprising: calculating, via a static initial sum adder, an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal; concurrent with calculating initial sums, generating, via domino initial carry-out logic, an initial carry-out signal for each initial sum previously calculated by the static initial sum adder; calculating, via a static intermediate sum adder, an intermediate sum for each group of M-initial sums according to a respective initial carry-out value of each initial sum calculated by the static initial sum adder; concurrent with calculating intermediate sums, generating, via domino intermediate carry-out logic, an intermediate carry-out signal for each intermediate sum generated by the static intermediate sum adder; and calculating a final sum value from the calculated intermediate sums according to a respective intermediate carry-out of each intermediate sum previously calculated by the static intermediate sum adder.