Patent ID: 8578117
Filing Date: 2013-11-05
Classification: G06F

Abstract:
1. A circuit comprising: a file comprising a plurality of read ports and a plurality of write ports, the file to store entries; a processor pipeline comprising a plurality of stages, each stage having a corresponding write port, the file to store write-back stage data indicating which write port is to write to a given entry; at least one WTR comparator configured to: compare a read index indexing an entry in the file requested to be read and a write index corresponding to a selected write port, wherein the write-back stage data indicates the selected write port as writing to the entry; generate a WTR comparator output indicating whether the write index matches the read index; and a read data output selector configured to selectively generate a read data output of either write data to the file or read data from the file, based on the WTR comparator output.