Patent ID: 6795003
Filing Date: 2004-09-21
Classification: G06F,H03M

Abstract:
A data shuffler apparatus for shuffling input bits comprising:a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a 2-bit vector {x0â€², x1â€²} such that Current StateNext StateVectorof Bit ShufflerInput Bitsof Bit Shuffler{x0â€², x1â€²}S0 (0)x0 = x1S0 (0){x0, x1}S0 (0)x0 â‰  x1S1 (1){x1, x0}S1 (1)x0 = x1S1 (1){x0, x1}S1 (1)x0 â‰  x1S0 (0){x0, x1}â€ƒand a number of 1's at x0â€² over time is within a predetermined number of 1's at x1â€²; and two 2-bit vector shufflers each inputting two of the 2-bit vectors {x0â€², x1â€²} and outputting 4-bit vectors each corresponding to a combination of two vectors {x0â€², x1â€²}, such that the 2-bit vector shufflers operate on the vectors {x0â€², x1â€²} in the same manner as the bit shufflers operate on the bits x0 and x1, wherein the current state of the bit shufflers is updated based on a previous state of the 4-bit vector shufflers.