Patent ID: 7528642
Filing Date: 2009-05-05
Classification: G06F

Abstract:
1. A semiconductor integrated circuit device comprising: a semiconductor substrate having a first area and a second area; a plurality of counters one of which is provided in the first area and the second area and which cyclically count a same value at a same timing in synchronism with a first clock signal and output a counter signal as a result of counting; a first clock circuit provided in the first area, supplied with a first counter signal from the one of the counters in the first area and outputting a second clock signal having a phase which becomes zero every time the first counter signal counts n times (n being a natural number); a first circuit provided in the first area and operating in synchronism with the second clock signal; a second clock circuit provided in the second area, supplied with a second counter signal from the one of the counters in the second area and outputting a third clock signal having a phase which becomes zero every time the second counter signal counts m times (m being a natural number different from n); and a second circuit provided in the second area, operating in synchronism with the third clock signal and supplying the first circuit with data when the first and second counter signals have a value equal to a common multiple of n and m.