Patent ID: 6370492
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A method of fault simulation comprising the steps of:(a) partitioning an original design representation of an integrated circuit into at least one software-modeled design element and at least one hardware-modeled design element; (b) performing a logic simulation on the original design representation with an input test pattern to generate a corresponding output test pattern for the at least one software-modeled design element; (c) replacing the at least one software-modeled design element in the original design representation with the corresponding output test pattern to generate a modified design representation for a hardware accelerator; (d) seeding a first set of possible faults within the modified design representation wherein faults masked by replacing the at least one software-modeled design element in the original design representation are excluded from the first set of possible faults; (e) performing a fault simulation of the modified design representation for the first set of possible faults in the hardware accelerator to generate results for a first fault simulation pass; (f) seeding a second set of possible faults in the original design representation wherein the second set of possible faults consists of the faults excluded in step (d); (g) performing a fault simulation of the original design representation for the second set of possible faults in both software and the hardware accelerator to generate results for a second fault simulation pass; and (h) combining the results of the first fault simulation pass with the results of the second fault simulation pass to generate an aggregate fault simulation coverage of the original design representation.