Patent ID: 7036003
Filing Date: 2006-04-25
Classification: G06F

Abstract:
1. An instruction processing device provided with an instruction fetch pipeline and an instruction execution pipeline and performing an instruction fetch and an instruction execution by way of an out-of-order system, comprising: a storage circuit storing a combination of address mode information of a fetched instruction and an instruction address of the fetched instruction, after an instruction fetch request is issued in the instruction fetch pipeline and before the fetched instruction is decoded in a decoding cycle of the instruction execution pipeline when the instruction fetch pipeline and the instruction execution pipeline operate by way of the out-of-order system, the address mode information indicating a size of an address space for the fetched instruction and used for a mask process of another instruction address; a branch instruction control circuit controlling a branch instruction using the address mode information stored in the storage circuit after the fetched instruction is decoded in the decoding cycle if the fetched instruction is the branch instruction; and a transfer circuit transferring the address mode information stored in the storage circuit to the branch instruction control circuit when the branch instruction is executed in an execution cycle of the instruction execution pipeline, the branch instruction control circuit controlling the branch instruction using the address mode information transferred thereto, as branch address mode information of a branch destination of the branch instruction if the branch instruction is not accompanied by an address mode change.