Patent ID: 7161576
Filing Date: 2007-01-09
Classification: G09G

Abstract:
1. A display device provided with a display panel having a plurality of display elements, which are arranged in a matrix form, and a drain driver which supplies gradation voltage corresponding to an image and a gate driver which scans lines of the display panel for supplying the gradation voltage, comprising: a timing control circuit for generating clocks used when the driver scans the lines of the display panel for multiple lines adjacent to each other, such that the image data and the blanking data can be displayed in arbitrary display elements within the one frame period, wherein: said display panel is formed into one screen, said gate driver performs multiple times scanning for each one line in said one frame period in accordance with one of a clock, and said drain driver supplies gradation voltages corresponding to the blanking data to the display elements in response to one scanning among the multiple times scanning, in accordance with one of the clocks, and supplies gradation voltages corresponding to the video data to the display elements in response to a another scanning among said multiple times scanning, in accordance with one of the clocks.