Patent ID: 6757852
Filing Date: 2004-06-29
Classification: G11C

Abstract:
A memory with redundancy comprising:one or more arrays of memory cells, each of the one or more arrays having one or more columns of redundant memory cells; a redundancy address comparator coupled to each of the one or more arrays of memory cells, the redundancy address comparator receiving an address which is compared to a predetermined value to determine if redundancy is to be selected within the memory, the redundancy address comparator asserting a redundant column select signal for use in selecting a redundant memory column in lieu of a normal memory column when redundancy is to be activated; and logic circuitry coupled to the redundancy address comparator for receiving the redundant column select signal, the logic circuitry selecting redundant data in response to receiving the redundant column select signal and generating a de-select feedback signal to the address comparator which de-asserts the column select signal.