Patent ID: 6197630
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of fabricating a narrow bit line structure on a semiconductor substrate, said method comprising:forming a interpoly dielectric layer over a metal-oxide-semiconductor field effect transistor (MOSFET);forming a landing pad in said interpoly dielectric layer;forming a first polysilicon layer on said interpoly dielectric layer and said landing pad;forming a metal silicide layer on said first polysilicon layer;forming a insulating layer on said metal silicide layer;forming a second polysilicon layer on said insulating layer;forming a defined photoresist layer on said second polysilicon layer;etching a portion of said second polysilicon layer using said defined photoresist layer as a mask;removing said defined photoresist layer;forming a polysilicon spacer in said second polysilicon layer sidewall and on said insulating layer;depositing a dielectric layer on said second polysilicon layer, said polysilicon spacer, and said insulating layer;etching back said dielectric layer to expose said second polysilicon layer;etching said second polysilicon layer, said polysilicon spacer, a portion of said insulating layer, a portion of said metal silicide layer, and a portion of said first polysilicon layer to expose said interpoly dielectric layer, using said dielectric layer as a hard mask;removing said dielectric layer on said insulating layer; andforming said narrow bit line structure over said landing pad, said narrow bit line structure having a critical dimension.