Patent ID: 6065090
Filing Date: 2000-05-16
Classification: G11C

Abstract:
A memory device comprising:a matrix array of memory cells arranged in rows and columns, each of said memory cells being uniquely addressable by a combination of a cell row address and a cell column address;a plurality of memory blocks subdividing said matrix array, each of said plurality of memory blocks comprising a sub-array of said memory cells and being uniquely addressable by a combination of a block row address and a block column address, said block row address consisting of a first plurality of most significant bits of the row address of the memory cells contained within said block, and said block column address consisting of a second plurality of most significant bits of the column address of the memory cells contained within said block;storage means adapted to store addresses of faulty memory cells in said matrix array;an addressable substitute memory comprising substitute memory cells for substituting for said faulty memory cells; andcomparator means responsive to a selected one of a first combination of a block row address and a cell column address only and a second combination of a cell row address and a block column address only, to select a faulty memory cell from the memory array for substitution by a memory cell from said substitute memory.