Patent ID: 8780624
Filing Date: 2014-07-15
Classification: G11C,H01L

Abstract:
1. A memory array, comprising: a plurality of memory cells; a plurality of paralleled bit lines formed on a semiconductor substrate, and a plurality of word lines perpendicular to the bit lines, wherein each bit line is connected to a source and a drain of adjacent memory cells; a part of a word line between adjacent bit lines is connected to a gate of a memory cell; wherein, wherein during a reading operation to the second memory bit cell, reading voltages applied to the word line, the first control gate, the second control gate, the bit line connected to the source and the bit line connected to the drain are from 0.5 V to 5 V, from 0 V to 6 V, from 0 V to 3 V, from 0.8 V to 3 V and from 0 V to 0.5 V, respectively.