Patent ID: 6518595
Filing Date: 2003-02-11
Classification: G11C

Abstract:
A semiconductor memory device for generating a memory cell address during a refresh operation, comprising:a controller for generating a refresh signal in response to an auto-refresh signal and a self-refresh signal; a bank counter for generating a bank selection signal and a bank count signal that are used in selecting a bank in response to the refresh signal; a bank selector for generating a first and a second bank enable signal that are used to selectively enabling each bank in response to the bank selection signal and the bank count signal; a refresh counter controller for generating a counter active signal in response to the bank selection signal and the refresh signal; and a refresh counter for generating a row address signal that is used to access the memory cell in response to the counter active signal, wherein the bank selector includes: a delay for delaying the bank count signal; a first NAND gate for performing a NAND operation on the bank selection signal and the output of the delay to form the first bank enable signal; an inverter for inverting the output of the delay; and a second NAND gate for performing a NAND operation on the bank selection signal and the output of the inverter to form the second bank enable signal.