Patent ID: 6463524
Filing Date: 2002-10-08
Classification: G06F

Abstract:
A method in a processor for issuing multiple store instructions incrementally, said method comprising the steps of:storing each of said multiple store instructions in a single issue queue instruction slot, wherein each of said single instruction slots includes an address operand field containing an address operand, a data operand field containing a data operand, an instruction load/store valid field, and an instruction fixed-point valid field; multiplexing, from among said issue queue instruction slots, the contents of said address operand fields to select an address operand of one of said multiple store instructions in accordance with the contents of said instruction load/store valid fields; issuing said selected address operand within an address generation sub-instruction to a load/store unit for execution; multiplexing, from among said issue queue instruction slots, the contents of said data operand fields to select a data operand of one of said multiple store instructions in accordance with the contents of said instruction fixed-point valid fields; and issuing said selected data operand within a data generation sub-instruction to a fixed-point unit for execution.