Patent ID: 8032819
Filing Date: 2011-10-04
Classification: G06F,H03K

Abstract:
1. A 5-3 compressor circuit for Carry-Save Adder (CSA) which receives four input signals and a lower-digit carry-out input, and computes addition bits, carry bits, and carry-out bits, comprising: four first-stage Exclusive-OR (EOR) circuits, which receive said four input signals and complementary signals of said four input signals, perform Exclusive-OR (EOR) computation of two input signals, and output two Exclusive-OR (EOR) outputs and complementary signals of said two Exclusive-OR (EOR) outputs; two second-stage Exclusive-OR (EOR) circuits, which receive the outputs of said four first-stage Exclusive-OR (EOR) circuits, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs, and output one Exclusive-OR (EOR) output and the complementary signal of said Exclusive-OR (EOR) output; a third-stage Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits and said carry-out bits, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs and said carry-out bits, and outputs addition bits; a carry output Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits, said carry-out bits, and one of said four input signals, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs, said carry-out bits, and said one input signal, and outputs carry bits; and two carry-out Exclusive-OR (EOR) circuits, which receive the outputs of said two first-stage Exclusive-OR (EOR) circuits and two complementary signals of said input signals, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs and said two complementary signals, and output said carry-out bits and the complementary signals thereof.