Patent ID: 6169736
Filing Date: 2001-01-02
Classification: H04L,H04Q

Abstract:
Interfacing device (INT) to be coupled between an incoming channel (IC) and an outgoing channel (OC) and to be used to extract M outgoing sets of bits (OS1, OS2, . . . , OSM) out of N incoming sets of bits (IS1, IS2, . . . , ISN) received on said incoming channel (IC), M being an integer number smaller than N, said interfacing device (INT) comprising: a. incoming register means (IR) provided to temporarily store said N incoming sets of bits (IS1, IS2, . . . , ISN); and b. selection means (SEL) coupled between said incoming register means (IR) and said outgoing channel (OC), and provided to select M incoming sets of bits out of said N incoming sets of bits (IS1, IS2, . . . , ISN) and to route said M incoming sets of bits to said outgoing channel (OC) to thereby produce said M outgoing sets of bits (OS1, OS2, . . . , OSM), characterised in that said selection means (SEL) further comprises: c. a multiplexing unit (MUX) including M multiplexers (MUX1, MUX2, . . . , MUXM), each multiplexer having a control input, N-M+1 input terminals adapted to sink N-M+1 incoming sets of bits out of said N incoming sets of bits (IS1, IS2, . . . , ISN), and one output terminal adapted to source one of said N-M+1 incoming sets of bits under control of a control signal applied to said control input; and d. a control unit (CTRL) adapted to generate for said each multiplexer, said control signal and to apply said control signal via an output terminal of said control unit (CTRL) to said control input of said each multiplexer.