Patent ID: 6405285
Filing Date: 2002-06-11
Classification: G06F

Abstract:
A cache system, comprising:at least an upper level cache array and a lower level cache array; a first bus for coupling the cache system to a processor; a second bus separate from the first bus that couples the lower level cache array and the upper level cache array; and a cache controller that, responsive to receipt of a load request from the processor, determines whether the load request has missed in the upper level cache array, and if so, causes the cache system to return a requested value to the processor using the first bus and causes a cache line containing the requested value to be supplied to the upper level cache array utilizing the second bus, wherein said first bus comprises an interconnection from at least said lower level cache to said processor and wherein said second bus comprises an interconnection from at least said lower level cache to said upper level cache that is disjoint from the first bus, and wherein the cache line is returned to the upper level cache via the second bus without using the first bus.