Patent ID: 7205602
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A structure to improve the coupling ratio of top gate to floating gate in flash memory cells, comprising: parallel active regions, surrounded by isolation regions, over a semiconductor region of a substrate, said isolation regions having a portion within and a portion above said semiconductor region, and where the semiconductor region under said active regions is doped in the vicinity of the surface to adjust the threshold voltage; insulator spacers disposed against the sidewalls of the portion of said isolation regions that are above said semiconductor region and that taper so they are wider near said semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to said semiconductor region; conductive floating gates spaced along said active regions and electrically isolated from each other, separated from said semiconductor region by a floating gate insulator layer and disposed between insulator spacers, wherein a portion of each conductive floating gate overlaps said isolation regions, said portion of said conductive floating gate overlapping said isolation regions has a top surface and sidewalls above said isolation regions, and said sidewalls are substantially perpendicular to said top surface; and top gates comprised of conductive stripes perpendicular to said active regions, disposed over floating gates from which they are separated by a top gate insulator layer.