Patent ID: 6153468
Filing Date: 2000-11-28
Classification: G11C,H01L

Abstract:
A method of forming a logic array for a decoder, the method comprising:forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between a pillar and the substrate;forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;forming a gate dielectric on at least a portion of the side surface of one of the pillars;forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between common pillars;forming an intergate dielectric, interposed between the floating gates and the control lines;forming an intergate dielectric, interposed between the two control lines between the common pillars;forming a plurality of address input lines, each address input line interconnecting one of the control lines;forming at least one first source and drain interconnection line interconnecting one of the first source and drain regions; andforming a plurality of data lines, each data line interconnecting one of the second source and drain regions.