Patent ID: 6504776
Filing Date: 2003-01-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:first and second bit lines constructing a folded bit-line pair; a memory cell connected to said second bit line; an equalizer connected to said first and second bit lines, and precharging said first and second bit lines; first and second sense nodes; a sense amplifier connected to said first and second sense nodes; a first switch circuit connected between said first bit line and said first sense node; a second switch circuit connected between said second bit line and said second sense node; and a control circuit controlling said equalizer and said first and second switch circuits, wherein said equalizer includes: a first potential supplying circuit supplying a predetermined potential to said first bit line; and a second potential supplying circuit supplying said predetermined potential to said second bit line, wherein during a period between time when said equalizer finishes to precharge said first and second bit lines and time when said sense amplifier finishes operation, said control circuit making said first switch circuit off while allowing said second switch circuit to remain on, and controlling said first potential supplying circuit supply said predetermined potential to said first bit line.