Patent ID: 6154079
Filing Date: 2000-11-28
Classification: G06F,G11C,H03K

Abstract:
A negative delay circuit comprising:a variable delay unit having a plurality of unit delay stages for delaying a first clock signal, each unit delay stage being coupled to a clock signal line by a switch in response to a switch control signal;a negative delay circuit (NDC) array coupled to the clock signal line for receiving an output of the variable delay unit and outputting a locked enable signal; anda switch control unit for detecting a locking fail signal from the NDC array and outputting a corresponding switch control signal to the delay variable unit such that corresponding unit delay stages are coupled to the clock signal line, wherein said NDC array comprises:a delay unit that sequentially delays the output from said variable delay unit to generate a plurality of delayed signals; anda selector that selects one of said plurality of delayed signals when a transiting edge of the output from said variable delay unit is between two transiting edges of two delayed signals from said plurality of delayed signals by a prescribed time period.