Patent ID: 7528479
Filing Date: 2009-05-05
Classification: H05K

Abstract:
1. A multilayer substrate for a digital tuner comprising: a first component layer; a first co-existing layer below the first component layer; a second co-existing layer below the first co-existing layer; and a second component layer below the second co-existing layer; the first component layer, the first co-existing layer, the second co-existing layer, and the second component layer have a first area and a second area; the first area is proximal to one of a left and a right of a center line of the multilayer substrate; the second area is proximal to another of the left and the right of the center line of the multiplayer substrate; the first area of the first co-existing layer is positioned under the first area of the first component layer; the first area of the second co-existing layer is positioned under the first area of the first co-existing layer; the first area of the second component layer is positioned under the first area of the second co-existing layer; the second area of the first co-existing layer is positioned under the second area of the first component layer; the second area of the second co-existing layer is positioned under the second area of the first co-existing layer; the second area of the second component layer is positioned under the second area of the second co-existing layer; the first component layer mounts a first LSI-IC and predetermined electronic components on an exterior facing surface of the first area of the first component layer; the first co-existing layer forms a first ground pattern region having a ground pattern on the first area of the first co-existing layer and forms a first power source pattern region having a power source pattern on the second area of the first co-existing layer; the second co-existing layer forms a second power source pattern region having a power source pattern on the first area of the second co-existing layer and forms a second ground pattern region having a ground pattern on the second area of the second co-existing layer; the second component layer mounts a second LSI-IC and predetermined electronic components on an exterior facing surface of the second area of the second component layer; the first power source pattern region and the second power source pattern region are respectively formed by line patterns of a predetermined width on the second area of the first co-existing layer and the first area of the second co-existing layer; the line patterns in the first power source pattern region connect with the second component layer via a predetermined number of vias; the line patters in the second power source pattern region connect with the first component layer via a predetermined number of vias, the first ground pattern region and the second ground pattern region are respectively provided with patterns formed over substantially the entire surface of the first area of the first co-existing layer and the second area of the second co-existing layer; the first ground pattern region is connected with the first component layer by a larger number of vias than the number of vias for connecting the second power source pattern region and the first component layer; the second ground pattern region is connected with the second component layer by a larger number of vias than the number of vias for connecting the first power source pattern region and the second component layer, and the first power source pattern region and the second power source pattern region have respectively formed therein a plurality small pattern regions for supplying power sources of a plurality of kinds of voltage levels.