Patent ID: 8332546
Filing Date: 2012-12-11
Classification: G06F

Abstract:
1. An apparatus comprising: a processor configured to (i) generate a first signal conveying a new one of a plurality of tasks to a memory and (ii) generate a second signal that causes a task counter to increment to indicate that said new task is scheduled, wherein said second signal is generated after said new task is stored in said memory; and a direct memory access controller configured to (i) execute said new task to transfer data between a plurality of memory locations in response to an absence of a predetermined value in said task counter, (ii) decrement said task counter in response to said executing of said new task, and (iii) wait to receive a next of said tasks in response to said task counter having said predetermined value; and wherein said processor is further configured to asynchronously increment said task counter to indicate that an additional one of said tasks is scheduled without monitoring said execution of said new task.