Patent ID: 6904473
Filing Date: 2005-06-07
Classification: G06F,Y10S

Abstract:
1. A direct memory access controller for facilitating transfer of data from a source memory to a destination memory via a destination bus, said direct memory access controller comprising: a source memory controller constructed and arranged to transmit instructions to the source memory to allow data corresponding to at least a portion of each of a plurality of sub-blocks of data to be read from the source memory; a destination bus control constructed and arranged to provide a connection to the destination bus; a filter having at least one filter criterion and being constructed and arranged to receive the data read from the source memory, to determine by comparison whether the received data includes matched data matching the filter criterion, and to output a result of the comparison; and a data pipeline for storing the received data being compared by said filter and constructed and arranged to output data from the data stored in said data pipeline to the destination memory in accordance with the result of the comparison made by the filter.