Patent ID: 7351652
Filing Date: 2008-04-01
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate on which a plurality of transistors has been defined; forming a wiring pattern over the transistors, the wiring pattern being coupled to at least one transistor; depositing an Inter Layer Dielectric (ILD) film over the wiring pattern; defining a first contact hole in the ILD film, the first contact hole exposing a portion of the wiring pattern; forming a lower metal layer including a first barrier metal layer, a first metal layer, and a second barrier metal layer, the lower metal layer contacting the wiring pattern via the first contact hole; forming a contact hole stop conduction layer over the lower metal layer; patterning the contact hole stop conduction layer and the lower metal layer to define one or more through-holes; depositing an Inter Metal Dielectric (IMD) film over the contact hole stop conduction layer, the IMD film filling the one or more through-holes; etching a selected portion of the IMD film using a first etch step, the first etch stop substantially exposing the contact hole stop conduction layer and removing a portion of the contact hole stop conduction layer, thereby providing the contact hole stop conduction layer with a reduced thickness; etching the contact hole stop conduction layer of the reduced thickness using a second etch step until the second barrier metal layer is exposed, so that a second contact hole is defined; forming a contact plug within the second contact hole, the contact plug contacting an upper surface of the lower metal layer; and forming an upper metal layer over the contact plug and the IMD film, the upper metal layer contacting an upper surface of the contact plug.