Patent ID: 8893068
Filing Date: 2014-11-18
Classification: G06F

Abstract:
1. A method for generating a simulation model for a circuit design, said method comprising: extracting a plurality of design properties associated with the circuit design, wherein the plurality of design properties includes an input/output (I/O) buffer setting extracted from a first netlist of the circuit design; generating a second netlist for the circuit design based on the plurality of design properties, with a second plurality of settings, wherein the second plurality of settings includes an operating temperature and a voltage range; simulating the second netlist through a processor to generate a plurality of simulation data; sampling the plurality of simulation data; and generating a simulation model for the circuit design based on the simulating of the second netlist and based on the sampling the plurality of simulation data, wherein the simulation model is a model simulating a plurality of I/O buffer behaviors of the circuit design.