Patent ID: 7343456
Filing Date: 2008-03-11
Classification: G06F

Abstract:
1. A node comprising: a processor coupled to an interconnect which is internal to a local node, wherein the processor is configured to maintain an indication of whether or not a modification of data at a first address has been detected by the processor after a load-linked (LL) instruction is executed by the processor on the interconnect to the first address, wherein when the indication is in a first state to indicate that the modification has been detected, a store conditional (SC) instruction associated with the LL instruction and executed by the processor is prevented from completing successfully, and wherein when the indication is in a second state to indicate that no modification has been detected, the SC instruction is allowed to be completed by the processor; and a memory bridge coupled to the interconnect of the local node and to a plurality of remote nodes via a connection external to the local node, in which the memory bridge communicates with the remote nodes and operates as an agent for the remote nodes on the interconnect to maintain coherency between the processor and the remote nodes, wherein the memory bridge is configured to initiate a first transaction on the interconnect in response to receiving an access command from one or more of the remote nodes to access the first address; wherein when the processor is allowed to complete the LL instruction and the associated SC instruction, the memory bridge is to send a kill command to the remote node or nodes to terminate the access to the first address by the remote node or nodes, but when the processor is prevented from executing the SC instruction due to the memory bridge winning access to the first address to cause the modification, the memory bridge is to identify and notify a remote node winning the access to modify the first address and to send a kill command to other remote node or nodes that failed in winning the access.