Patent ID: 6091149
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A multilevel interconnect structure comprising:a semiconductor substrate;a barrier layer arranged on said semiconductor substrate;a spaced set of first interconnect conductors arranged in a first plane upon said barrier layer, said first interconnect conductors separated from one another by a first intralevel dielectric comprised of air;a plurality of vertically oriented interconnect pillars extending upward from said first interconnect conductors, said interconnect pillars comprising a conductive material;a spaced set of second interconnect conductors arranged upon a second plane vertically displaced above and substantially parallel to said first plane, said second interconnect conductors supported in said second plane by upper ends of said plurality of interconnect pillars whereby an interlevel dielectric between said first interconnect conductors and said second interconnect conductors comprises air; anda plurality of vertically oriented support pillars extending upward from said barrier layer to a lower surface of said second interconnect conductors.