Patent ID: 6363516
Filing Date: 2002-03-26
Classification: G06F

Abstract:
A method for designing an integrated circuit which contains a plurality of signal lines in close proximity, such that capacitive coupling among the signal lines is operable to induce crosstalk on at least one of the signal lines, wherein the integrated circuit has at least a first module having instantiations of one or more cells, the method for designing comprising the step of:extracting parasitic data representative of the module in a hierarchical manner from a trial layout of the integrated circuit; wherein the step of extracting comprises the steps of: extracting first intracellular parasitic data representative of a first cell only once, regardless of the number of times the first cell is instantiated in the integrated circuit; cutting out a first portion of intercell signal lines that are routed over a first instance of the first cell by specifying a first area in the trial layout corresponding to the first instance of the first cell such that the first portion of intercell signal lines within the first area can be processed apart from a remaining portion of the intercell signal lines; extracting over the cell routing (OCR) parasitic data of the first portion of intercell signal lines with reference to the first instance of the first cell; cutting out a second portion of intercell signal lines that are routed over a second instance of the first cell by specifying a second area in the trial layout corresponding to the first instance of the second cell such that the second portion of intercell lines within the second area can be processed apart from a remaining portion of the intercell signal lines; and extracting OCR parasitic data of the second portion of intercell signal lines with reference to the second instance of the first cell.