Patent ID: 6088806
Filing Date: 2000-07-11
Classification: G06F,Y02D

Abstract:
An integrated circuit including:A) a plurality of modules, each of which includes at least one operational circuit timed by a respective separate main clock signal associated therewith;B) a separate monitor circuit respectively associated with each module and receiving a respective monitor clock signal by which its operation is timed, the monitor circuit generating an idle signal associated with each operational circuit included in the module with which it is associated when that operational circuit's main clock signal can safely be discontinued and responding to a request signal applied thereto by determining whether its monitor clock can safely be discontinued and generating an acknowledge signal when it can;C) a clock circuit that generates the main and monitor clock signals; andD) a power-control circuit responsive to each said idle signal to suppress application of the respective main clock signal to the operational circuit with which that idle signal is associated, the power-control circuit being operable to apply a request signal to each monitor circuit and further being responsive to each said acknowledgment signal to suppress application of the respective monitor clock signal to the monitor circuit by which the acknowledgment signal was generated.