Patent ID: 8138611
Filing Date: 2012-03-20
Classification: H01L

Abstract:
1. A semiconductor device comprising: (a) a substrate having a main surface, a plurality of bonding leads formed on the main surface, and a back surface opposing to the main surface, wherein a planar shape of the main surface of the substrate is a rectangular shape having a first side, and a second side opposing to the first side, and wherein the plurality of bonding leads have a plurality of first bonding leads arranged along the first side, a plurality of second bonding leads arranged along the first side and arranged between the first side and the plurality of first bonding leads, and a plurality of third bonding leads arranged along the second side; (b) a first semiconductor chip having a first main surface, a plurality of first electrode pads formed on the first main surface, a plurality of second electrode pads formed on the first main surface, and a first back surface opposing to the first main surface, and mounted on the main surface of the substrate such that the first semiconductor chip is arranged between the plurality of first bonding leads and the plurality of third bonding leads in a plan view, wherein a planar shape of the first main surface of the first semiconductor chip is a rectangular shape having a third side adjacent to the first side of the substrate, and a fourth side opposing to the third side, wherein the plurality of first electrode pads are arranged along the third side of the first semiconductor chip, and wherein the plurality of second electrode pads are arranged along the fourth side of the first semiconductor chip; (c) a second semiconductor chip having a second main surface, a plurality of third electrode pads formed on the second main surface, a plurality of fourth electrode pads formed on the second main surface, and a second back surface opposing to the second main surface, and mounted on the first main surface of the first semiconductor chip such that the second back surface of the second semiconductor chip faces to the first main surface of the first semiconductor chip, wherein a planar shape of the second main surface of the second semiconductor chip is a rectangular shape having a fifth side next to the third side of the first semiconductor chip, and a sixth side opposing to the fifth side, wherein the plurality of third electrode pads are arranged along the fifth side of the second semiconductor chip, and wherein the plurality of fourth electrode pads are arranged along the sixth side of the second semiconductor chip; (d) a plurality of first wires electrically connecting the plurality of first electrode pads with the plurality of first bonding leads, respectively; (e) a plurality of second wires electrically connecting the plurality of third electrode pads with the plurality of second bonding leads, respectively; (f) a plurality of third wires electrically connecting the plurality of second electrode pads with the plurality of third bonding leads, respectively; (g) a plurality of fourth wires electrically connecting the plurality of fourth electrode pads with the plurality of second electrode pads, respectively; and (h) a sealing body sealing the first semiconductor chip, the second semiconductor chip, the plurality of first wires, the plurality of second wires, the plurality of third wires, and the plurality of fourth wires; wherein a distance between the first side of the substrate and the third side of the first semiconductor chip is larger than that between the second side of the substrate and the fourth side of the first semiconductor chip; and wherein a central portion of each of the first and second semiconductor chips is shifted more toward the second side of the substrate from a central portion between the plurality of second bonding leads and the plurality of third bonding leads than the first side of the substrate in a plan view.