Patent ID: 6601118
Filing Date: 2003-07-29
Classification: G06F

Abstract:
A bridge circuit in a computer system for providing data transfers between a processor and a plurality of peripheral devices comprising:a plurality of address buffers in communication with the processor and a minimum of one peripheral device; a plurality of data buffers in communication with the processor and the minimum of one peripheral device; an input address arbiter configured to control data flow between the processor and the plurality of address buffers; an input data arbiter configured to control data flow from the processor to the plurality of data buffers; and an output data arbiter configured to control data flow from the plurality of data buffers to the processor and to the minimum of one peripheral device; wherein each of the plurality of address buffers operates as a matched pair with a one of the plurality of data buffers such that an address stored in a first address buffer is associated with data held in a corresponding first data buffer; and wherein concurrent data flow between the processor and at least one of the plurality of peripheral devices operates through the plurality of data buffers.