Patent ID: 6363459
Filing Date: 2002-03-26
Classification: G06F,H01R,Y02D

Abstract:
A microprocessor device, comprising:a central processing unit for converting instructions stored in a program memory into arithmetic and/or logical combinations for controlling various components of the microprocessor device; a data and/or control line bus connected to said central processing unit for transmitting data and for selectively accessing CPU-internal and peripheral-bound special function registers associated with said central processing unit; a coherent memory block random access type memory cells connected to said central processing unit through said data and/or control line bus, said memory block including a dedicated address decoder and bus driver circuit, and having a first, arbitrarily accessible memory area and a second, peripheral-independent and directly addressable memory area; and an enable device connected to said memory block for selectively disabling and enabling an output of data contents from said second memory area onto said data and/or control line bus.