Patent ID: 7119571
Filing Date: 2006-10-10
Classification: G01R,H01L

Abstract:
1. A test structure for determining the reliability of conductive lines formed in a semiconductor substrate, comprising: a conductive line formed in a first metal layer of the semiconductor substrate; one or more thermal stress-inducing test pads formed in a second metal layer of the semiconductor substrate, wherein each of the test pads is wider in at least two dimensions than a line width of the conductive line and is adapted to stress the conductive line to which the test pad is attached during thermal cycling; one or more vias electrically and mechanically coupling the one or more test pads to the conductive line; a plurality of probe contact pads electrically coupled to the conductive line at different locations, allowing the measurement of at least one of line resistance of the conductive line or the resistance across one or more of the vias; and one or more dielectric materials disposed between the metal layers.