Patent ID: 7544557
Filing Date: 2009-06-09
Classification: H01L

Abstract:
1. A method for fabricating a complimentary complementary metal-oxide-semiconductor integrated circuit (CMOS IC) device on a substrate having an upper surface, wherein the method comprises: forming a first well region and a second well region in the substrate such that a first peripheral isolation structure is formed around the first well region and a second peripheral isolation structure is formed around the second well region; simultaneously forming a Schottky diode on the first well region and a field effect transistor (FET) in the second well region, wherein the Schottky diode includes a Schottky barrier structure and a backside contact structure formed on the upper surface over first and second doped regions of the substrate, respectively, and an isolation structure formed on the upper surface and located between the Schottky barrier and backside contact structures over a third doped region of the substrate, wherein the FET includes first and second terminal structures formed on the upper surface of the substrate over fifth and sixth doped regions disposed in the second well region of the substrate, respectively, and a gate structure formed on the upper surface of the substrate and located between the first and second terminal structures, and wherein simultaneously forming the Schottky diode and the FET comprises depositing a layer of polycrystalline silicon over the upper surface of the substrate, and then etching the layer of polycrystalline silicon such that a first portion of said layer is located over the third doped region and forms a first polycrystalline silicon structure of the isolation structure of the Schottky diode, and such that a second portion of said layer is located over the second well region and forms a second polycrystalline silicon structure of the gate structure of the FET.