Patent ID: 7266759
Filing Date: 2007-09-04
Classification: G06F,G11C,H03M

Abstract:
1. A semiconductor integrated circuit device comprising: K memory cell arrays (K is a natural number larger than 1) each having a normal data storing portion which stores data used for normal data writing and normal data readout operations, and a parity data storing portion which stores parity data used for an error checking and correcting operation for readout data read out from the normal data storing portion; K error checking and correcting circuits, each of which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency; and an I/O buffer which outputs readout data subjected to the error checking and correcting operation by use of the K error checking and correcting circuits after elapse of the read latency, wherein each of the K error checking and correcting circuits performs an error checking and correcting operation for readout data of (M×N)/K bits (where M is a natural number larger than 1 and N is a natural number larger than 0) read out from the normal data storing portion at burst data read time during the read latency in a case where burst length is set to M and the number of I/Os is set to N, and wherein each of the K error checking and correcting circuits separately transfers data of (M×N)/K bits subjected to the error checking and correcting operation to the I/O buffer for every N bits and one of the error checking and correcting circuits which has finished M/K data transfer operations performs an error checking and correcting operation for readout data of L×N bits (where L is a natural number larger than 0) following on the (M×N)/K bits after elapse of the read latency while a different one of the error checking and correcting circuits is transferring data (where L×N≦(M×N)/K) in a case where burst length is set to (M+L).