Patent ID: 6812772
Filing Date: 2004-11-02
Classification: H03K

Abstract:
A circuit arrangement comprising:a series circuit of IGDTs, each IGDT including between an anode and a cathode a four-layer semiconductor substrate, the substrate having an anodal outer p-doped anode layer, a two-part, n-doped base layer with integrated n-type buffer, a p-doped base layer and a cathodal outer n-doped cathode layer, each IGDT including two gates controllable via low-inductance gate terminals, a first a first one of the two gates being provided on the cathode side, and a second one of the two gates being provided on the anode side, a plurality of gate drivers comprising two control units for driving respective gates, each gate driver being configured to generate gate currents with a rate of rise greater than 20 amperes/microsecond/cmsi2, and a plurality of units for supplying energy to the gate drivers, wherein a first one of the control units of a first one of the gate drivers drives the first gate of a first one of the IGDTs, and a second one of the control units of the first one of the gate drivers drives the second gate of a second one of the IGDTs connected to the cathode of the first one of the IGDTs on the anode side.