Patent ID: 7939910
Filing Date: 2011-05-10
Classification: H01L

Abstract:
1. A semiconductor chip capacitance circuit, comprising: a vertical-native capacitor comprising a plurality of vertical-native capacitor metal layers parallel to each other and vertically aligned above and parallel to a planar front-end-of-line semiconductor base substrate, adjacent layers of the vertical-native capacitor metal layers structurally and electrically separated by electrically-insulating dielectric material layers; each of the vertical-native capacitor metal layers comprising a plurality of positive port metal plates in an alternating horizontal parallel relationship with a plurality of negative port metal plates and in an alternating vertical parallel relationship to a plurality of negative port metal plates of an adjacent vertical-native capacitor metal layer; first and second asymmetrical rectangular metal-insulator-metal capacitors within at least one of the dielectric material layers in a lateral rectangular array parallel to and spaced from the semiconductor base substrate; the first asymmetrical metal-insulator-metal capacitor having a first planar rectangular metal bottom plate parallel to and spaced a bottom plate distance from the semiconductor base substrate and projecting a first bottom plate footprint vertically relative to the semiconductor base substrate, and a first planar rectangular metal top plate above and parallel to the first metal bottom plate and separated from the first bottom plate by the dielectric material, the first planar rectangular metal top plate parallel to and spaced a top plate distance from the semiconductor base substrate that is greater than the bottom plate distance, the first rectangular top plate smaller than the first rectangular bottom top plate and aligned to fit entirely within the first bottom plate footprint relative to the semiconductor base substrate and to expose a first bottom plate remainder upper lateral connector surface vertically within the first bottom plate footprint to a one of a vertical-native capacitor positive port metal plate horizontally alternating with a negative port metal plate located above the first bottom plate and above the at least one dielectric material layer; the second asymmetrical metal-insulator-metal capacitor having a second planar rectangular metal bottom plate parallel to and spaced the bottom plate distance from the semiconductor base substrate and projecting a second bottom plate footprint vertically relative to the semiconductor base substrate and electrically connected to the first asymmetrical metal-insulator-metal capacitor top plate, and a second planar rectangular metal top plate above and parallel to the second metal bottom plate and separated from the second bottom plate by the dielectric material and electrically connected to the first asymmetrical metal-insulator-metal capacitor bottom plate, the second planar rectangular metal top plate parallel to and spaced the top plate distance from the semiconductor base substrate, the second rectangular top plate smaller than the second rectangular bottom top plate and aligned to fit entirely within the second bottom plate footprint relative to the semiconductor base substrate; a first bottom plate port contact vertically within the dielectric material layer and within the first bottom plate footprint that electrically connects the exposed first bottom plate remainder upper lateral connector surface to the one vertical-native capacitor metal plate located vertically above the first bottom plate; and a first top plate port contact vertically within the at least one dielectric material layer and within the first bottom plate footprint that electrically connects the first top plate to an other of the of horizontally alternating vertical-native capacitor positive port metal plate and negative port metal plate located vertically above the first top plate and the at least one dielectric material layer.