Patent ID: 8560931
Filing Date: 2013-10-15
Classification: G06F,G11C,H03M

Abstract:
1. A method of operating a solid-state memory in an integrated circuit, the memory comprised of random-access memory cells, each biased by a power supply voltage at a first bias voltage during normal operation, comprising: receiving a retention mode signal indicating entry into a retention mode; responsive to the retention mode signal, reading payload data corresponding to the contents of a first plurality of the memory cells in a first retention domain of the memory; generating a code word corresponding to the payload data, the code word having a number of bits in the code word greater than the number of memory cells in the first plurality of memory cells; storing at least a portion of the code word in a second plurality of memory cells in the integrated circuit; then reducing the bias to memory cells in the first retention domain to a voltage below the first bias voltage; then receiving a normal operation mode signal indicating entry into a normal operation mode; responsive to the normal operation mode signal, increasing the bias to the memory cells in the first retention domain; reading the contents of the first and second pluralities of memory cells; decoding the read contents of the first and second plurality of memory cells to recover payload data from the read contents; and storing the recovered payload data in the first plurality of memory cells.