Patent ID: 8940645
Filing Date: 2015-01-27
Classification: B82Y,H01L

Abstract:
1. A method of fabricating a memory device, comprising: subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in the substrate, wherein the channel comprises polysilicon; forming a multi-layer charge storing layer overlying the tunnel oxide layer, the multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a stoichiometric composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a stoichiometric composition of the second layer results in it being trap dense; and subjecting the substrate to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer.