Patent ID: 6188235
Filing Date: 2001-02-13
Classification: G01R

Abstract:
A test method for verifying that pins of an integrated circuit (IC) are properly connected comprisingin a first step, temporarily connecting a first signal pin (O) of the IC to ground, applying a base voltage (B) to a ground pin (GND) of the IC, the base voltage having a magnitude suitable for turning on a transistor of the IC (D2, D1), applying a collector voltage (C) to a second signal pin (I) of the IC, and,with these connections, measuring collector current, and simultaneously measuring an additional voltage appearing at a supply voltage pin (V.sub.cc) of the IC;in a second step, removing the collector voltage and applying the same ground and base voltages as in the first step connected to the same pins (O, I) as in the first step, applying a voltage equal to the previously measured additional voltage to the supply voltage pin (V.sub.cc), andmeasuring an additional current flowing to the supply voltage pin;and in a third step, determining a corrected collector current from the difference between the measured collector current and the measured additional current, and evaluating whether the magnitude of the corrected collector current indicates proper connection of the transistor.