Patent ID: 8772914
Filing Date: 2014-07-08
Classification: H01L

Abstract:
1. A semiconductor device comprising: a chip mounting portion comprising a first upper surface that is an upper surface of the chip mounting portion and a first lower surface that is a lower surface of the chip mounting portion opposite to the first upper surface; a first chip comprising a first multilayer interconnect layer and a first inductor formed in the first multilayer interconnect layer; and a second chip comprising a second multilayer interconnect layer and a second inductor formed in the second multilayer interconnect layer, wherein the first chip comprises a rectangular first front surface comprising a first terminal formed thereon and a first back surface opposite to the first front surface, wherein the first chip is mounted over the chip mounting portion such that the first upper surface of the chip mounting portion is faced with the first back surface of the first chip, wherein the second chip comprises a rectangular second front surface comprising a second terminal formed thereon and a second back surface opposite to the second front surface, wherein the second chip is mounted over the first chip such that the first front surface of the first chip is faced with the second front surface of the second chip, wherein the first inductor and the second inductor are disposed such that the first inductor and the second inductor are overlapped with each other as viewed from a direction perpendicular to the first upper surface of the chip mounting portion, and wherein the second front surface of the second chip comprises an extension region that does not overlap with the first upper surface of the chip mounting portion as viewed from a direction perpendicular to the first upper surface of the chip mounting portion.