Patent ID: 6323073
Filing Date: 2001-11-27
Classification: H01L

Abstract:
A method for forming doped regions on a silicon on insulator (SOI) device, the SOI device positioned on a substrate, the SOI device comprising a first dielectric layer, a silicon layer positioned on the first dielectric layer, and a shallow trench isolation (STI) structure in the silicon layer passing through to the first dielectric layer, the method comprising:performing a first thermal diffusion process to drive dopants into a first region of the silicon layer so as to form a first conductive type doped region;performing a second thermal diffusion process to drive dopants into a second region of the silicon layer so as to form a second conductive type doped region; andgrowing an epitaxy layer on the surface of the silicon layer;wherein the dopants in the doped regions diffuse into the epitaxy layer, and the doping concentration distribution in the epitaxy layer and the silicon layer presents a Super Steep Retrograde (SSR) distribution curve 90 as to improve the electrical performance of the MOS transistor.