Patent ID: 6347356
Filing Date: 2002-02-12
Classification: G11C

Abstract:
A burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode, comprising:a plurality of holding means for latching and holding a corresponding number of address signals; at least one inverting means receiving one address signal of said address signals for supplying an inverted address signal to a corresponding holding means of said plurality of holding means; and a decoding means receiving outputs of said plurality of holding means for selectively activating one of a plurality of burst length discrimination signals determined by a combination of logical values of said address signals, said decoding means activating a burst length discrimination signal indicating a burst length other than a full page when the outputs of all said plurality of holding means are all in a high state and when the outputs of all said plurality of holding means are all in a low state, wherein when the outputs of all said plurality of holding means are all in a high state and when the outputs of all said plurality of holding means are all in a low state said decoding means never selects the burst length discrimination signal indicative of the full page.