Patent ID: 8969161
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: forming an active region configured in or over a substrate to include a first conductive-type first deep well and a second conductive-type second deep well that form a junction therebetween; forming a first conductive-type first impurity region in the first conductive-type first deep well; forming a device isolation layer in the substrate; forming a gate insulation layer over the substrate; forming a gate electrode extending over the junction and over a portion of the first conductive-type first deep well and a portion of the second conductive-type second deep well; and forming a first conductive-type pickup region and a second conductive-type source region on the first conductive-type first impurity region on one side of the gate electrode and a second conductive-type drain region in the second conductive-type second deep well on another side of the gate electrode, wherein the first conductive-type first impurity region extends toward the junction in such a manner forming a overlap region in which the first conductive-type first impurity region overlaps with a portion of the gate electrode and encompasses the second conductive-type source region, the first conductive-type pickup region, and at least a portion of the device isolation layer being disposed between the second conductive-type source region and the first conductive-type pickup region.