Patent ID: 7397265
Filing Date: 2008-07-08
Classification: G01R

Abstract:
1. An MOS transistor characteristic detection apparatus for detecting whether or not a first MOS transistor in a target circuit is operated in a saturated region, the apparatus comprising: a replica signal generation circuit for generating a replica signal capable of minimizing, if being received by the target circuit, a drain voltage of the first MOS transistor; a replica circuit for receiving the replica signal, the replica circuit being a replica of the target circuit and including a second MOS transistor corresponding to the first MOS transistor; a first voltage buffer for receiving a drain voltage of the first MOS transistor; a second voltage buffer for receiving a drain voltage of the second MOS transistor; a first MOS transistor group including at least one MOS transistor which has the same characteristics as those of the first MOS transistor and in which the same voltages as voltages applied to a gate and a source of the first MOS transistor are applied to a gate and a source, respectively, and an output voltage of the first voltage buffer is applied to a drain; a second MOS transistor group including at least one MOS transistor which has the same characteristics as those of the first MOS transistor and in which the same voltages as voltages applied to a gate and a source of the first MOS transistor are applied to a gate and a source, respectively, and an output voltage of the second voltage buffer is applied to a drain; and a comparison circuit for comparing respective sizes of a first current flowing through the first MOS transistor group and a second current flowing through the second MOS transistor group.