Patent ID: 8129246
Filing Date: 2012-03-06
Classification: H01L

Abstract:
1. A method of forming high threshold voltage transistors and low threshold voltage transistors, comprising: providing a semiconductor substrate with an upper surface and isolation structures separating a plurality of regions; forming a first gate dielectric layer on the upper surface of the semiconductor substrate in a first region; forming a second gate dielectric layer on the upper surface of the semiconductor substrate in a second region; forming a first conductive gate layer on the first gate dielectric layer; forming a second conductive gate layer on the second gate dielectric layer; forming a contiguous layer containing carbon in the semiconductor substrate beneath said first conductive gate layer; forming two layers containing carbon in the semiconductor substrate positioned on either side of the second conductive gate layer thereby forming a gap; forming a first SSRW in the semiconductor substrate beneath the contiguous layer containing carbon such that said contiguous carbon layer inhibits the diffusion of dopants towards the upper surface of the substrate beneath the first gate dielectric layer; and forming a second SSRW in the semiconductor substrate beneath the gap such that dopants can diffuse towards the upper surface of the substrate beneath the second gate dielectric layer.