Patent ID: 7002388
Filing Date: 2006-02-21
Classification: G11C,H03K

Abstract:
1. A method of driving a nonvolatile flip-flop circuit, the nonvolatile flip-flop circuit comprising: a first clocked inverter to which a data signal is input; a ferroelectric gate transistor in which a gate is connected to an output terminal of the first clocked inverter, and a source and a body are connected electrically; a second clocked inverter which is connected in parallel to the ferroelectric gate transistor; a first switching element, one end of which is connected to the gate of the ferroelectric gate transistor and the other end of which is connected to a low potential line; a second switching element, one end of which is connected to the source of the ferroelectric gate transistor and the other end of which is connected to the low potential line; a third clocked inverter which is connected to a drain of the ferroelectric gate transistor; a third switching element, one end of which is connected to an input terminal of the third clocked inverter and the other end of which is connected to a power supply; and a fourth switching element, one end of which is connected to the input terminal of the third clocked inverter and the other end of which is connected to the power supply; wherein an output signal is output via an output terminal of the third clocked inverter; the driving method comprising the following steps of: a data hold step of holding the data signal utilizing polarization of a ferroelectric material of the ferroelectric gate transistor when the data signal is input while the first clocked inverter, the second clocked inverter, and the third switching element are turned on and the first switching element, the second switching element, and the third clocked inverter are turned off; and a data output step of outputting the output signal based on the held data signal placing the first clocked inverter, the second clocked inverter, and the third switching element in the OFF state and placing the first switching element, the second switching element, and the third clocked inverter in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor.