Patent ID: 6576513
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method of forming a NAND-type flash memory device, comprising the steps of:forming parallel device isolation layers to define a plurality of parallel active regions on a substrate; forming a gate electrode profile in which a gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer are stacked sequentially on the active regions; patterning the gate electrode profile to form a plurality of gate line sets having a string select line, a plurality of wordlines, and a ground select line, the gate line sets being vertical to the active regions to define a height above the active regions; and carrying out a tilted ion implantation, using the gate line sets as ion implantation masks, wherein the step of carrying out a tilted ion implantation occurs at a tilted angle, said tilted angle being sufficient to carry out the tilted ion implantation only to an active region adjacent to an opposite sidewall of the wordline out of both sidewalls of the string select line, and to an active region adjacent to an opposite sidewall of the wordline out of both sidewalls of the ground select line.