Patent ID: 8520776
Filing Date: 2013-08-27
Classification: H04L

Abstract:
1. A data recovery system for processing a high speed differential data signal that is subject to distortions and a clock signal into a digital signal, comprising: analog front end (AFE) circuitry having adjustable parameters for processing the differential data signal into a preprocessed data signal having reduced distortion; an oversampling circuit providing a digital representation of the preprocessed data signal; a training function circuit including a length detection circuit to determine the run length of contiguous “1” or “0” samples in the digital representation, for estimating a quality of the digital representation of the preprocessed data signal, and adjusting the parameters of the AFE circuitry to improve the quality of the digital representation of the preprocessed data signal; and a bit extractor circuit for generating the digital signal from the digital representation of the preprocessed data signal; wherein the differential data signal input to the AFE circuitry comprises a first data signal of positive polarity and a second data signal, complementary to the first data signal, of negative polarity.