Patent ID: 8153493
Filing Date: 2012-04-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a first and second fin on the substrate, wherein a space interposes the first and second fin; forming an isolation structure in the space, wherein the forming the isolation structure includes filling the space with isolating material that abuts the lateral sides of each of the first and second fins adjacent the top surface of each of the first and second fins forming a planar surface, wherein the planar surface includes a top surface of the isolation structure and a top surface of the first and second fin; forming a gate structure on the planar surface including the top surface of the isolation structure, the top surface of the first fin, and the top surface of the second fin, wherein the gate structure includes a top-channel only gate structure; removing portions of the isolation structure, wherein the removed portions of the isolation structure provide recesses adjacent an end region of the first and second fin; and forming a source or drain region in the recesses.