Patent ID: 8996940
Filing Date: 2015-03-31
Classification: G01R,H03K

Abstract:
1. A semiconductor integrated circuit comprising: N input terminals, wherein N is an integer equal to or more than 1; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops, wherein R is an integer equal to or more than 1; a selector section configured to select N selected flip-flops from said plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to said N input terminals are respectively output to said N output terminals by said N selected flip-flops; and an error detection section configured to generate said reconfiguration information at a test mode, wherein at said test mode, said N flip-flops form a scan chain and a scan data is input to said scan chain, wherein a flip-flop whose output is fixed to 0 or 1 is an error flip-flop, and wherein said error detection section detects said error flip-flop included in said N flip-flops based on scan input data respectively input to said N flip-flops and scan output data respectively output from said N flip-flops at said test mode and further generates said reconfiguration information excluding said detected error flip-flop from said N selected flip-flops.