Patent ID: 6591372
Filing Date: 2003-07-08
Classification: G06F

Abstract:
A method for determining a length of a feedback path of a phase lock loop chip mounted on a computer board to establish timing of clock pulses at a clock input pin of a computer chip mounted on said board, comprising:connecting an edge pin of said computer board to a clock input pin of said phase lock loop chip by a connecting pathway having a first length, said edge pin of said computer board receiving clock signals from a clock line connected to a system clock for a computer in which said computer board is mounted; connecting a clock output pin of said phase lock loop chip to a computer chip clock input pin by a second conducting pathway having a second length, said second conducting pathway to conduct clock pulses from said clock output pin of said phase lock loop chip to said clock input pin of said computer chip; and determining said length of said phase lock loop feedback path in response to both said first length and said second length to achieve a Desired Delay, said Desired Delay being a delay time interval which is desired between an arrival time of a clock pulse at said edge pin of said computer board and an arrival time of a corresponding clock pulse at said clock input pin of said computer chip.