Patent ID: 6815755
Filing Date: 2004-11-09
Classification: H01L

Abstract:
Semiconductor device comprising on a single substrate at least one memory cell, at least one high voltage transistor, and at least one logic transistor;the at least one memory cell comprising a floating gate, a tunnel oxide layer between the floating gate and the substrate, a control gate, and a control oxide layer between the control gate and the floating gate; the at least one high voltage transistor comprising a high voltage transistor gate and a high voltage transistor gate oxide between the high voltage transistor gate and the substrate, the high voltage transistor gate oxide comprising a first gate oxide layer on the substrate and a second gate oxide layer directly on top of the first gate oxide layer, wherein the second gate oxide layer and the control oxide layer of the memory cell have a same or substantially same predetermined thickness, the at least one logic transistor comprising a logic transistor gate and a logic transistor gate oxide between the logic transistor gate and the substrate, wherein the logic gate comprises a first gate layer on top of the logic transistor gate oxide and a second gate layer directly on top of said first gate layer, and wherein the first gate layer and the floating gate of the memory cell have a same or substantially predetermined thickness and a same or substantially same predetermined doping concentration, wherein the tunnel oxide layer of the memory cell, the first gate oxide layer of the high voltage transistor, and the logic transistor gate oxide have a same or substantially same predetermined first thickness.