Patent ID: 7992117
Filing Date: 2011-08-02
Classification: G06F,Y02P

Abstract:
1. A system for designing layouts for integrated circuits, comprising: an input device configured to receive at least one input pertaining to a circuit design of at least one integrated circuit (IC) object; and logic configured to define, based on the input, a tiling unit to be tiled for generating at least a portion of a layout design for the IC object, the tiling unit representing segments of devices that define the IC object, wherein the segments represented by the tiling unit do not have a common centroid, the logic configured to tile the tiling unit to automatically generate a plurality of tiled arrays that form the portion of the layout design for the IC object such that the devices of the IC object have a common centroid, each of the tiled arrays formed by a respective tiling of the tiling unit, wherein the logic, by tiling the tiling unit, is configured to generate a plurality of tiled arrays that form at least a first portion of the layout design, each of the tiled arrays having a respective segment order, wherein the respective segment order of each of the tiled arrays is different than the segment order of an adjacent one of the tiled arrays.