Patent ID: 6311309
Filing Date: 2001-10-30
Classification: G01R,G06F,G06Q,Y10S

Abstract:
A method for simulating a portion of a circuit design, the method comprising:generating a plurality of design files each corresponding to one of a plurality of design entities in circuit design wherein the plurality of design entities includes fully specified design entities which are sufficiently specified to enable generations of netlists for simulation and partially specified design entities which require further specification for generation of netlists for simulation;selecting a subset of the design entities from among the fully specified and partially specified design entities in the circuit design, the subset of the design entities corresponding to the portion of the circuit design and including at least one of the partially specified design entities;in response to selecting the subset of the design entities, generating a netlist under software control directly from selected ones of the design files associated with the subset of the design entities, any design file associated with the at least one partially specified design entities being affirmatively excluded from generation of the netlist; andsimulating the portion of the circuit design using the generated netlist.