Patent ID: 6334136
Filing Date: 2001-12-25
Classification: G06F,G11C,H03K

Abstract:
An apparatus that performs an arithmetic operation on two N-nary operands including a 1-of-P first operand and a 1-of-Q second operand, comprising:a sum/bypass logic that performs an arithmetic operation on one or more groupings of two or more bits of the 1-of-P first operand and one or more groupings of two or more bits of the 1-of-Q second operand to generate an intermediate sum and an HPG indicator;a control logic, coupled to said sum/bypass logic, that selects one or more said groupings of two or more bits of the 1-of-P first operand and one or more said groupings of two or more bits of the 1-of-Q second operand for said arithmetic operation;an HPG logic, coupled to said sum/bypass logic, that generates a block HPG indicator; anda result logic, coupled to said HPG logic, that generates a 1-of-R final result, wherein said 1-of-R final result comprises said intermediate sum, and wherein said final result further comprises additional bits of said second operand when said intermediate sum comprises bits than said second operand, such that said final result and said second operand comprise an equal number of bits, said additional bits of said second operand being selected according to said control logic.