Patent ID: 6680867
Filing Date: 2004-01-20
Classification: G11C

Abstract:
A semiconductor device comprising:a plurality of first memory cells for storing either one of first information and second information arranged at points of intersection between a plurality of word lines and a first data line; a plurality of second memory cells for storing either one of the first information and the second information, arranged at points of intersection between said plurality of word lines and a second data line; a plurality of first dummy cells for storing the first information, arrange at points of intersection between said plurality of word lines and a first dummy data line; a plurality of second dummy cells for storing the second information, arranged at points of intersection between said plurality of word lines and a second dummy data line; a first multiplexer coupled between said first and second data lines and a first potential; and a second multiplexer coupled between said first and second dummy data lines and the first potential, wherein when said plurality of first and second memory cells are not selected, said first multiplexer connects the first potential and said first and second data lines and said second multiplexer connects the first potential and said first and second dummy data lines.