Patent ID: 8588329
Filing Date: 2013-11-19
Classification: H03L,H04L

Abstract:
1. A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first sigma-delta modulator configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; a second sigma-delta modulator configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; the phase-locked loop having: a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output data of the first sigma-delta modulator; and a second mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value not dependent on the output data of the first sigma-delta modulator, but by a value dependent on the output data of the second sigma-delta modulator, wherein the input signals by which the first and second sigma-delta modulators are clocked are independent of the output of the oscillator.