Patent ID: 7584440
Filing Date: 2009-09-01
Classification: G06F

Abstract:
1. A method for tuning a circuit, comprising: receiving a description of the circuit; selecting a design point of the circuit for evaluation using a sizing tool, wherein the design point comprises a design of the circuit that meets a set of predefined design specifications, and wherein the circuit comprises a group of circuit devices; receiving a set of tuning information for the group of circuit devices, wherein the set of tuning information includes tuning ranges and corresponding increments applicable within the tuning ranges; tuning the group of circuit devices using the set of tuning information to create a group of tuned circuit devices; creating an updated layout of the group of tuned circuit devices using a layout tool; creating estimated parasitic information of the group of tuned circuit devices using the updated layout; and verifying by a computer the design point meets design goals of the circuit using the estimated parasitic information of the updated layout.