Patent ID: 6261891
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A method of forming a passivation layer of DRAM (dynamic random access memory) on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, and two adjacent gates positioned on the surface of the semiconductor water, each gate comprising a silicon oxide layer serving as a gate oxide layer and positioned on the silicon substrate, a polysilicon layer positioned on the surface of the silicon oxide layer serving as a conductive layer, a silicide layer positioned on the surface of the polysilicon layer to reduce the resistance of the conductive layer, and a spacer on each of two opposite walls, the method comprising:forming a first silicon-oxygen-nitride layer of predetermined thickness on the semiconductor wafer wherein the first silicon-oxygen-nitride layer is used as a diffusion barrier layer;forming a second silicon-oxygen-nitride layer of predetermined thickness on the first silicon-oxygen-nitride layer wherein the second silicon-oxygen-nitride layer is used as an etching layer;forming a BPSG (borophosphosilicate glass) layer uniformly on the second silicon-oxygen-nitride to planarize the surface of the semiconductor wafer wherein the BPSG layer is used as a dielectric layer;wherein the first silicon-oxygen-nitride layer is used to prevent diffusion of boron and phosphorous form the BPSG layer into the silicon substrate, the first and the second silicon-oxygen-nitride layers together constitute the passivation layer of the DRAM.