Patent ID: 8266194
Filing Date: 2012-09-11
Classification: G06F

Abstract:
1. A system, comprising: a feedback shift-register having: a clock operationally connected to the feedback shift-register, the clock being operative to control the movement of the bits along the stages; a bit generator having an output, the bit generator being operative to generate a plurality of random/pseudo-random bits for outputting via the output of the bit generator, the bit generator being operative such that the output of the bit generator is biased according to a state of the stages of the feedback shift-register; a main XOR logic gate having a first and second input and an output, the output of the bit generator being operationally connected to the first input of the main XOR logic gate, the output of the non-linear feedback sub-system being operationally connected to the second input of the main XOR logic gate, the output of the main XOR logic gate being operationally connected to the input of the first stage of the feedback shift-register; and a scheduler having an input operationally connected to the main XOR logic gate or the feedback shift-register, the scheduler being operative to schedule a plurality of wait-states according to data received by the input of the scheduler.