Patent ID: 6168986
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A method of forming a structure on a substrate assembly, the method comprising: providing a vertical edge within a substrate assembly; forming a region of insulating material immediately adjacent to and in contact with the vertical edge in the substrate assembly, said substrate assembly defining a plane; etching a hole into the region of insulating material at the vertical edge; and filling at least a portion of the hole with a volume of electrically conductive material within the region of insulating material, the volume of electrically conductive material being situated in contact with the vertical edge, the region of electrically conductive material making a planar interface in contact with the vertical edge, said planar interface extending orthogonally to the plane of the substrate assembly; forming a dielectric material over the region of insulating material, said dielectric material having a top surface thereon; and forming a semiconductor device extending above a contact with the volume of electrically conductive material to terminate in an upper portion that has an outer surface that is in contact with and perpendicular to the top surface of the dielectric material over the region of the insulating material, the semiconductor device being in electrical communication with the vertical edge through the volume of electrically conductive material.