Patent ID: 7868390
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A strained-silicon CMOS transistor, comprising: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed above the first transistor and a portion of the isolation structure; a second etching stop layer, disposed only on the first stress layer; a second stress layer, disposed above the second transistor, wherein the end of the second stress layer and the end of the first stress layer comprise a gap therebetween and the second stress layer is disposed only on a portion of the second active region; and a third etching stop layer disposed only on the second transistor, the second stress layer, and the first etching stop layer of the second transistor.