Patent ID: 7971176
Filing Date: 2011-06-28
Classification: G01R

Abstract:
1. A method, comprising: a processor of a computer determining one or more paths of a circuit to be tested, each path of said one or more paths independently comprising one or more nets; selecting a set of quantitative, geometric or parametric features of said nets, said circuit having one or more pattern input points and one or more pattern observation points connected by said nets, each of said nets defined by an input point and all fan out paths to (i) input points of other nets of said nets or (ii) to said pattern observation points, each net of said nets comprising one or more connected segments; selecting a unit of measure for each feature of said set of features; assigning a weight to each said segment of said nets based on a number of said unit of measure of said feature in each segment of each fan out path of each of said nets; and said processor generating a set of test patterns based on said weights assigned to each segment of each fan out path of each of said nets of said circuit.