Patent ID: 6615388
Filing Date: 2003-09-02
Classification: H03M

Abstract:
A path memory for a Viterbi decoder, comprising:path selecting circuitry for producing a plurality of control signals from path select command signals generated by said Viterbi decoder a clock T interval earlier than reference clock timing and from two path select command signals which are generated by said Viterbi decoder a 2T interval earlier than the reference clock timing corresponding to two possible states separated from each other by a predetermined distance; and a matrix array of memory cells arranged in a plurality of rows, said memory cells being divided into a first array of odd-numbered columns and a second array of even-numbered columns, each row of said first-array memory cells being responsive to a corresponding one of said control signals for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing, each row of said second-array memory cells being responsive to a corresponding one of said control signals for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing, said first and second arrays alternately operating at 2T-intervals.