Patent ID: 8194451
Filing Date: 2012-06-05
Classification: G11C,H01L

Abstract:
1. A semiconductor memory cell comprising: a substrate having a top surface, said substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface; a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface; a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type; a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; a gate positioned between said first and second regions and above said top surface; and a nonvolatile memory configured to store data upon transfer from said body region.