Patent ID: 9094026
Filing Date: 2015-07-28
Classification: H03L

Abstract:
1. A digital phase-locked loop (DPLL) device with automatic frequency range selection, comprising: a multiband voltage-controlled oscillator (VCO) module comprising a frequency converter configured to connect with the VCO signal and to output a phase signal derived from the VCO signal by Q-dividing the VCO frequency, wherein Q is a non-zero division factor; a time-to-digital converter comprising a first input to receive a reference phase signal from a reference clock, and a second input to receive the phase signal outputted by the frequency converter, and an output to deliver a digital PLL-error signal; a digital loop filter comprising a digital-to-analog converter connected at an input to the VCO-loop output of the digital loop filter, and connected at an output to the analog input of the multiband VCO module, to produce the VCO-control voltage based on the digital VCO-control signal; wherein the digital loop filter further has a DCO-loop output suitable for delivering the code value based on a filtering of the digital PLL-error signal as received at the input of the digital loop filter; and wherein the DPLL device further comprises at least one frequency range selection operation where the VCO-control voltage is maintained at fixed voltage value and the code value varies until the lock condition is met; and an analog VCO-tuning operation where a final code value corresponding to the meeting of the lock condition is maintained at the digital input of the multiband VCO module and the digital VCO-control signal varies so as to maintain the lock condition.