Patent ID: 6781889
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A method of operating a semiconductor memory, which comprises:providing a semiconductor memory with: a memory cell, array having memory cells for selectively storing a first logic value and a second logic value, word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines; a decoder for simultaneously selecting one or a plurality of the word lines; a voltage generator connected to the bit lines, for applying a predetermined voltage level to the bit lines; carrying out a potential equalization of in each case two bit lines; subsequently bringing the bit lines to a level representing the first logic value, subsequently selecting only a portion of the word lines drivably connected to the word line decoder, subsequently bringing the bit lines to a level representing the second logic value, and subsequently selecting another portion of the word lines drivably connected to the word line decoder; and subsequently selecting a multiplicity of the word lines and writing the levels applied to the bit lines into the memory cells connected to the selected word lines.