Patent ID: 7764545
Filing Date: 2010-07-27
Classification: G11C

Abstract:
1. An address replacing circuit, comprising: a sub-bank region selecting unit configured to allow a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column addresses in accordance with operation modes; a first column region activating unit configured to generate a first column region activating address and a second column region activating address from the first bit of the column address; a second column region activating unit configured to generate a third column region activating address and a fourth column region activating address from the second bit of the column address; and a column region selecting unit configured to allow at least one of first to fourth column regions of the first sub-bank region and first to fourth column regions of the second sub-bank region to be selectively activated, in response to the first to fourth column region activating addresses; wherein the row address correspond to an address that is not defined by the JEDEC (Joint Electron Device Engineering Council) international standard.