Patent ID: 6260116
Filing Date: 2001-07-10
Classification: G06F

Abstract:
In a processor system employing a cache memory for storing instruction addresses a system for prefetching data from storage and storing the data in the cache memory for use by an executing program comprising:first means responsive to sequential program instruction addresses for detecting when a program has entered a processing loop and has completed at least one pass through the processing loop and providing an enabling signal indicative thereof, the first means including:first counting means for accumulating a count of sequential numerical instruction addresses and providing an output indicative thereof;second arithmetic means for examining sequential instruction addresses and providing a first predetermined output when the instruction addresses are sequential and a second output when they are not sequential; and,third logic means responsive to the first counting and second arithmetic means for providing enabling signals when their outputs have a predetermined relation;second means responsive to the enabling signals from the first means for determining a requirement for additional data and prefetching the required data; and,third means for monitoring the operation of the program to detect termination of loop processing and for terminating the prefetch of data from storage.