Patent ID: 6501670
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory comprising:an array region having at least two sub-arrays separated by an area for sub-wordline drivers, each sub-array having a plurality of memory cells arranged along horizontally extending rows and vertically extending columns; an address decoder configured to generate a decoded signal for selecting a plurality of memory cells in a memory access; an input/output (I/O) block configured to transfer data corresponding to the selected memory cells into and out of the semiconductor memory; a first timing circuit configured to generate a first timing signal; a second timing circuit configured to receive the first timing signal and in response generate a strobe signal coupled to the I/O block; and a global data bus configured to carry the data between the I/O block and the sub-arrays, wherein the global data bus is routed vertically outside the sub-wordline drivers area and an interconnect line for carrying the first timing signal is routed through the sub-wordline drivers area so that in the memory access a time delay from when the decoded signal is generated to when the data arrives at an input terminal of the I/O block is substantially the same as a time delay from when the first timing signal is generated to when the strobe signal is generated.