Patent ID: 6023771
Filing Date: 2000-02-08
Classification: G06F

Abstract:
An information processing apparatus, comprising:2n+1 clock oscillators, n being a positive integer;2n+1 clock buses each connected respectively to one of said 2n+1 clock oscillators for distributing clocks outputted from said 2n+1 clock oscillators;2n+1 counters each connected respectively to one of said 2n+1 clock buses for individually counting the clocks outputted from said clock oscillators;a clock selection instructing circuit for comparing outputs of said 2n+1 counters and outputting an instruction to select an output of that one of said clock oscillators which is connected to that one of said 2n+1 counters which indicates a middle value;a timing instructing circuit for outputting an instruction to instruct for a timing at which said clock selection instructing circuit should compare values of said 2n+1 counters and reset said 2n+1 counters;a plurality of modules for receiving the clocks from individual ones of said 2n+1 clock buses; anda clock selecting circuit provided in each of said modules for selecting one of the clocks inputted thereto from said 2n+1 clock buses in accordance with the instruction from said clock selection instructing circuit and distributing the selected clock to a logic circuit in the module.