Patent ID: 6154510
Filing Date: 2000-11-28
Classification: H03L,H04L

Abstract:
A symbol synchronizer for recovering symbol timing in a digital communication receiver which receives an analog signal configured as a stream of symbols from a channel which distorts said analog signal, said symbol synchronizer comprising:a clock generator for generating a clock signal that defines symbol timing;a converter, coupled to said clock generator, for converting said analog signal into a complex digital data stream having a complex sample for each symbol interval;a phase processor, coupled to said converter, for identifying clock adjustment opportunities in response to phase relationships exhibited by said complex samples;a magnitude processor, coupled to said converter, said phase processor and said clock generator, for generating a phase error estimate signal that adjusts said symbol timing defined by said clock signal in response to magnitude relationships exhibited by said complex samples, said phase error estimate signal being updated in synchronism with said identified clock adjustment opportunities; anda phase error offset generator, coupled to said magnitude processor, for adjusting said phase error estimate signal to cause a phase locked loop which includes said clock generator, said converter and said magnitude processor to achieve a locked condition in the presence of distortion in said analog signal.