Patent ID: 6181542
Filing Date: 2001-01-30
Classification: H01L,H03K

Abstract:
A dual power supply interface buffer circuit formed on a semiconduct or substrate to prevent damage to said interface buffer circuit connected at an interface of circuits having a high power supply voltage source and circuits having a low power supply voltage source, comprising:an input terminal connected to the circuits having the low power supply voltage source to transfer signals from said circuits having the low power supply voltage,an output terminal connected to the circuits having the high power supply voltage source to transfer signals to said circuits having the high power supply voltage source, whereby a voltage level at said output terminal is generated by a ground bounce and a termination mismatch reflection;a predriver circuit having:a first MOS transistor of a first conductivity type having a gate connected to the input terminal, and a source connected to a substrate biasing voltage, source, and;a second MOS transistor of a second conductivity type having a gate connected to the input terminal, and a source connected to low power supply voltage source;an interface driver circuit having:a first MOS driver transistor of the first conductivity type having a gate connected to drains of the second MOS transistor of the predriver circuit, a source connected to the substrate biasing voltage source, and a drain connected to the output terminal, and;a second MOS driver transistor of the second conductivity type having a gate connected to the drains of the second transistors of the predriver circuit, a source connected to an input/output power supply voltage source, and a drain connected to the output terminal;an interface driver protection circuit comprising:an inverter circuit having an input connected to the gates of the first and second MOS driver transistors of the interface driver circuit and an output;a third MOS transistor of the first conductivity type having a gate connected to the input of the inverter circuit, a source connected to a drain of the first MOS transistor of the predriver circuit, and a drain connected to the drain of the second MOS transistor of the predriver circuit; anda coupling capacitor connected between the drain of the first MOS driver transistor and the gate of the first MOS driver transistor, such that when a voltage level at the drain of first MOS driver transistor that approaches that of the high power supply voltage source, a voltage level at said gate of the first MOS driver transistor causes the output inverter circuit to assume a voltage level that will turn off the third MOS transistor capturing said voltage level at said drain of the third MOS transistor to prevent damage to said first and second MOS driver transistors.