Patent ID: 6359810
Filing Date: 2002-03-19
Classification: G11C

Abstract:
In a flash memory array organized in a plurality of rows and columns having a word line associated with each row of the array and a bit line associated with each column of the array, the memory including a plurality of memory cells, each memory cell associated with one row line and one column line of the array and including a transistor having a control gate coupled to the one of the row lines with which it is associated, a floating gate, a source coupled to a common source node for the memory array, and a drain coupled to the one of the bit lines with which it is associated, a method for performing an erase operation on one row of the array comprising:applying a negative voltage to the row line associated with the row to be erased; applying a positive bias voltage to the row lines in the array associated with rows other than said row to be erased; and applying a positive voltage more positive than said positive bias voltage to each bit line in the array, wherein the difference between said negative voltage and said positive voltage is of a magnitude sufficient to cause electrons to tunnel from said floating gate and wherein the difference between positive bias voltage and said positive voltage is of a magnitude such that said floating gate is less susceptible to tunneling.