Patent ID: 8219604
Filing Date: 2012-07-10
Classification: G06F

Abstract:
1. A method for implementing a decimal floating point adder, the method comprising: receiving a first operand at a first input register; receiving a second operand at a second input register; calculating a sum of one or more corresponding digits from the first operand and the second operand, the calculating performed by a plurality of adder blocks during a first clock cycle, wherein output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits; storing the sums of the corresponding digits in an intermediate result register during the first clock cycle; storing the carry out indicators in a carry chain during the first clock cycle; incrementing each of the sums in the intermediate result register by one during a second clock cycle; selecting between each of the sums and the sums incremented by one, wherein input to the selecting includes the carry chain, the selecting occurs during the second clock cycle, and the output from the selecting includes a final sum of the first operand and the second operand; and storing the final sum in an output register.