Patent ID: 7945811
Filing Date: 2011-05-17
Classification: G06F

Abstract:
1. A data processing apparatus comprising: a plurality of functional elements responsive to one or more input values and a clock signal to produce at least one output value, at least some of said functional elements being arranged to form at least one compound functional unit, each compound functional unit having at least two evaluation stages and each evaluation stage comprising at least one of said functional elements with output values from functional elements in an evaluation stage being forwarded to a next evaluation stage; wherein at least one functional element within at least one compound functional unit is an error detecting functional element having error detecting circuitry for detecting a change in at least one of an input value and an output value of said error detecting functional element between a first sampling time and a second sampling time and error recovery circuitry for performing an error recovery operation if said change is detected by said error detecting circuitry, the interval between said first sampling time and said second sampling time being shorter than one clock cycle of said clock signal; and said data processing apparatus further comprises input flow controlling circuitry for controlling the flow of input values into said at least one compound functional unit such that input values for the functional elements in the first of said at least two evaluation stages of said at least one compound functional unit are changed at most every second clock cycle.