Patent ID: 7719909
Filing Date: 2010-05-18
Classification: G11C

Abstract:
1. A write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line (WL) being coupled to all the memory cells in a column of the memory block and a continuous bit-line (BL) being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising: a first and a second sense amplifier adjacent to each other and belonging to the same memory block; a first switching device coupled between a first node of the first sense amplifier and a first power supply, the first switching device being controlled by a first signal; a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal; and a MOS transistor coupled between the first node and a first local bit-line, the MOS transistor being controlled by a global bit-line, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.