Patent ID: 8850380
Filing Date: 2014-09-30
Classification: G06F

Abstract:
1. A method comprising: defining a correlation between at least two parameters, wherein at least one parameter of the at least two parameters is from a first chip of a three-dimensional integrated chip stack and at least one parameter of the at least two parameters is from a second chip of the three-dimensional integrated chip stack; generating a covariance matrix based on the at least two parameters; calculating a new parameter or new parameter set using the covariance matrix; performing statistical static timing analysis (SSTA) such that the new parameter or the new parameter set is propagated into the SSTA; and determining whether timing targets for the three-dimensional integrated chip stack are achieved, wherein at least the generating the covariance matrix is performed using a processor; the correlation between the at least two parameters is determined based on a manufacturing sorting plan that includes a set correlation requirement between the first chip and the second chip; and the covariance matrix is indicative of the correlated at least two parameters and the set correlation requirement between the first chip and the second chip.