Patent ID: 8332200
Filing Date: 2012-12-11
Classification: G06G

Abstract:
1. A method for generating phase noise in a system with a phase-locked loop (PLL) while the system is simulated in time domain, comprising: modelling a simulator with a processor of a computer, wherein the simulator comprises simulation blocks, the simulation blocks correspond to blocks of the system, each of the simulation blocks has a predefined phase vector whose elements are injected consecutively at a trigger event; and classifying, with the processor, the simulation blocks, wherein each of the simulation blocks is classified as a master element block, a semi-master element block, or a slave element block, the simulation blocks having exactly one master element block; wherein an element selection of each predefined noise vector is steered from the master element block, the semi-master element block is self-triggered and determines its own injection frequency rate, and is reset-steered and aligned with the master element block as a capturing data phase starts, and the slave element block is directly steered with the master element block, wherein the blocks of the system with the PLL comprise the PLL, a frequency divider, and a crystal oscillator, wherein, the PLL comprises a phase-frequency detection and charge pump circuit (PFD/CP) block, and a low pass filter, and a controlled oscillator, the simulation block corresponding to the controlled oscillator is the master element block, the simulation blocks corresponding to the crystal oscillator, the frequency divider, and the PFD/CP block are the semi-master element blocks, and the simulation block corresponding to the low pass filter is the slave element block.