Patent ID: 6819169
Filing Date: 2004-11-16
Classification: H04L

Abstract:
Isolation interface with a capacitive barrier, comprisingat the input end of the capacitive barrier an input circuit (A1) with differential outputs for a first and a second logical output signals U1o+ and U1oâˆ’, respectively, that are replicas of a transmitted input signal Ui and are complementary to one another, a first barrier capacitor (C+) and a second barrier capacitor (Câˆ’) for the first and second logical signals U1o+ and U1oâˆ’, respectively, at the output end of the capacitive barrier, an output circuit (A2) with inputs for a first logical input signal U2i+ and a second logical input signal U2iâˆ’, respectively, that are complementary to one another, and the output circuit (A2) comprises a first voltage comparator (Co+) and a second voltage comparator (Coâˆ’), and characterized in that in the input circuit (A1) a first integrating unit (R1, C1)+ and a second integrating unit (R1, C1)âˆ’ are provided, across which the first logical output signal U1o+ and the second logical output signal U1oâˆ’, respectively, passed and by means of whose time constants the slope rates of the edges of the signals U1oÂ± or the rising and falling-off times of the signals U1oÂ± were adjusted, and that to an output terminal of the first barrier capacitor (C+) and of the second barrier capacitor (Câˆ’) on the one hand and to a common potential terminal of the output circuit (A2) on the other hand, such a first resistor (R+) and a second resistor (Râˆ’) are connected that the time constant of a first differentiating unit (C+, R+) made of the first barrier capacitor (C+) and of the first resistor (R+) and the time constant of the second differentiating unit (Câˆ’, Râˆ’) made of the second barrier capacitor (Câˆ’) and of the second resistor (Râˆ’) are shorter than the rising and falling-off times of the logical output signals U1o+ and U1oâˆ’ being the replicas of the transmitted input signal Ui.