Patent ID: 7126197
Filing Date: 2006-10-24
Classification: H01L

Abstract:
1. A method of forming a power MOSFET comprising a substrate of a first conductivity type and a body region of a second conductivity type, including the steps of: forming a gate region of a pre-determined pattern and with a plurality of gate elements partially covering the substrate, said gate elements having a stepped cross-sectional profile comprising a thicker portion and a thinner portion, said thicker portion being adapted to substantially prevent passage of impurities therethrough into the substrate during an impurities implantation step, said thinner portion being adapted to allow partial passage of impurities therethrough during the impurities implantation step, and implanting impurities into the substrate from the gate region side of the substrate to form a body region of the second conductivity type, wherein, after said impurities implantation step, a step-profiled body region, comprising a thinner shallow body region underneath said gate elements and a thicker deep body region in the portion of said substrate not covered by said gate region and not masked by other blocking means, is formed in the substrate with impurities also present underneath pre-determined regions of said gate elements, wherein the thickness of said thinner shallow body region does not exceed 2.0 μm.