Patent ID: 7408213
Filing Date: 2008-08-05
Classification: H01L

Abstract:
1. A ferroelectric memory device, comprising: a semiconductor substrate, on which are provided a plurality of elements, each said element including a memory cell element and a plurality of logic circuit elements; a lower insulating film provided on said semiconductor substrate; a ferroelectric capacitor structure provided on said lower insulating film, and being formed by layering, in order, a lower electrode, a ferroelectric layer, and an upper electrode; an upper insulating film, which covers said lower insulating film and said ferroelectric capacitor structure; a wiring layer, which extends over said upper insulating film, and is electrically connected to said ferroelectric capacitor structure, said memory cell element, and said logic circuit elements; and, a barrier film which directly and without interruption covers a side face and an upper face of said wiring layer, and directly and without interruption covers an upper face of said upper insulating film.