Patent ID: 7466785
Filing Date: 2008-12-16
Classification: H03L,H04L

Abstract:
1. A Phase Locked Loop comprising a frequency detector including a balanced quadricorrelator, the balanced quadricorrelator comprising: a first pair of double edge clocked bi-stable circuits coupled to a first multiplexer, the first pair of double edge clocked bi-stable circuits to provide a first signal; a second pair of double edge clocked bi-stable circuits coupled to a second multiplexer, the second pair of double edge clocked bi-stable circuits supplied by the mutually quadrature phase shifted signals to provide a second signal, wherein the first and the second multiplexers are controlled by a control signal having the same bit-rate as the incoming signal; a third pair of double edge clock bi-stable circuits coupled to a third multiplexer supplied by the first signal; a fourth pair of double edge clock bi-stable circuits coupled to a fourth multiplexer supplied by the second signal; and wherein the first and second pair of double edge clocked bi-stable circuits are supplied by mutually quadrature phase shifted signals respectively to provide the first signal and the second signal, wherein the first and second signals are indicative for a phase difference between the incoming signal and mutually quadrature phase shifted signals.