Patent ID: 7715472
Filing Date: 2010-05-11
Classification: H04L

Abstract:
1. An equalization circuit for correcting unknown phase offsets of a received data stream having a subset of phase correction symbols, wherein a phase of the subset of phase correction symbols is offset from a phase of a transmitted data stream by an unknown amount, comprising: a feed forward equalizer (FFE) data register including multiple stages, wherein an output of each stage of the FFE data register is multiplied by a respective equalizer coefficient to produce weighted outputs of the FFE data register; a first adder, wherein the first adder is configured to sum the weighted outputs of the FFE data register to produce an equalized output; a coefficient update module coupled to the FFE data register, wherein the coefficient update module is configured to receive the phase correction symbols as an input and to update the equalizer coefficients based on the phase correction symbols; a phase alignment module coupled to the coefficient update module and the first adder, wherein the phase alignment module is configured to estimate the unknown phase offsets in the phase correction symbols and to adjust the phase correction symbols based upon the estimate of the unknown phase offsets; and a delay line coupled to the FFE data register and the coefficient update module.