Patent ID: 6801465
Filing Date: 2004-10-05
Classification: G11C

Abstract:
A random access memory, comprising:a) a plurality of storage cells; b) a first bit line and a second bit line coupled to each of said plurality of storage cells, said first and second bit lines designed: 1) to not be equalized while said first bit line receives a first supply current and while said second bit line receives a second supply current, said first supply current supplying leakage current drawn from said first bit line by one or more of said storage cells, said second supply current supplying leakage current drawn by one or more of said storage cells; 2) to be equalized to help prepare said first and second bit lines for a read of one of said storage cells, said first bit line receiving said first supply current and said second bit line receiving said second supply current while said first and second bit lines are said equalized; and 3) to develop a differential signal while one of said storage cells is being read, said first bit line receiving said first supply current and said second bit line receiving said second supply current while said first and second bit lines are said developing a differential signal.