Patent ID: 8350329
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. An electrostatic discharge (ESD) protection device for an integrated circuit, comprising: a buried layer of a first polarity type formed in a substrate of a second polarity type; a well region of the second polarity type formed above the buried layer; a field effect transistor (FET) of the first polarity type formed within the well region; an inner pair of shallow wells of the first polarity type, disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer; and an outer pair of deep wells of the first polarity type, extending down to the top of the buried layer, such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type; and one or more substrate contacts to the well region, disposed between the inner pair of shallow wells and the outer pair of deep wells.