Patent ID: 8697584
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing layer above a first transistor formed above a substrate, said first stress-inducing layer generating a first type of stress; forming a second stress-inducing layer above a second transistor, said second stress-inducing layer generating a second type of stress other than said first type of stress; forming a third dielectric layer above said first and second transistors and in direct contact with said first and second stress-inducing layers, said third dielectric layer having an internal stress level above said first transistor that is less than that of said first and second stress-inducing layers; forming an interlayer dielectric material above said first and second transistors; and forming contact openings in said interlayer dielectric material by using said third dielectric layer as an etch stop material for the etching of said interlayer dielectric material.