Patent ID: 6452807
Filing Date: 2002-09-17
Classification: G01R,H01L

Abstract:
A test interposer for a ball grid array package, comprising:a substantially planar structure including a plurality of bond pads arranged in a grid array on a first surface thereof, each bond pad of said plurality being in substantial alignment with a corresponding bond pad of a semiconductor device to be assembled with the test interposer; a plurality of electrically conductive vias extending through a central region of said substantially planar structure, each electrically conductive via of said plurality being configured to communicate with a corresponding bond pad of said semiconductor device and a corresponding contact of a carrier substrate between which the test interposer is configured to be assembled; at least one electrically conductive trace carried by said substantially planar structure and extending from at least one electrically conductive via of said plurality toward an imperforate peripheral region of said substantially planar structure; and at least one test pad through which at least one electrical characteristic of said semiconductor device is determinable when said semiconductor device is connected to said carrier substrate, said at least one test pad being disposed on said imperforate peripheral region and in electrical communication with said at least one electrically conductive trace, said at least one test pad configured to be contacted by a probe of a test apparatus.