Patent ID: 6504869
Filing Date: 2003-01-07
Classification: H03H

Abstract:
A signal processor comprising:an digitizer that oversamples said signal using an oversampling clock whose frequency is a multiple of a nominal baud rate of said signal, and outputs a digitized signal sample stream and a delayed version of said digitized signal sample stream; respective finite impulse response (FIR) filter stages which filter said digitized signal sample stream and said delayed version of said digitized signal sample stream; a linear interpolator coupled to receive FIR-filtered samples A and delayed FIR-filtered samples B of said signal at a time determined by contents of an oversampling clock signal divider, and thereby effectively decimate said samples by the ratio of said oversampling clock to said baud clock; a digital phase locked loop coupled to receive a timing error signal from a timing recovery path for said signal; and a loop filter coupled to a comparator which controllably modifies a modulo N up/down counter that controls coupling of said samples to said interpolator by said oversampling clock signal divider, so that, at baud time, decimated FIR filter samples A and B are subjected to a linear interpolation operator A+(Bâˆ’A)*n/N, where n is a count value of said up/down counter of the number of times said comparator has modified said modulo N up/down counter.