Patent ID: 6363520
Filing Date: 2002-03-26
Classification: G01R

Abstract:
A method of producing a synthesizable RT-Level specification having testability enhancement from a staring RT-Level specification representative of a circuit to be designed, for input to a synthesis tool to generate a gate-level circuit, the method comprising the steps of:(a) performing testability analysis on a Directed Acyclic Graph, formed by the transformation of an Intermediate Format representation of said starting RT-Level specification by computing and propagating Testability Measures (TMs) forward and backward through statements of said Directed Acyclic Graph including computing a Combinational Controllability, defined as the probability that a signal has a predetermined value, and a Combinational Observability, defined as the probability that a signal change on a line, l, will result in a signal change on an output, s, and, for a specification having multiple output modules, computing the Observability of a line relative to each output and computing an overall Observability O(l) of line l given by maxs; (b) identifying the bits of each signal and/or variable, obtained in step (a), on which faults are hard to detect; and (c) adding test point statements into said specification at the RT-Level to improve testability of said circuit to be designed.