Patent ID: 7010652
Filing Date: 2006-03-07
Classification: G11C

Abstract:
1. A computer system comprising: a plurality of memory segments, each of the plurality of memory segments having a first channel coupled to one or more first memory devices comprising a first memory capacity and a second channel coupled to one or more second memory devices comprising a second memory capacity different than the first memory capacity; a memory controlling system coupled to each of the plurality of memory segments via a respective bus segment, the memory controlling system being adapted to simultaneously write data on each of the first channel of each of the plurality of memory segments in response to a first command and the second channels of each of the plurality of memory segments in response to a second command; and a host/data controller coupled to the memory controlling system, the host/data controller determining the memory capacity coupled to each of the first and second channels of the respective plurality of memory segments, selecting a smallest memory capacity common to each of the first and second channels of the plurality of memory segments, and designating the smallest common memory capacity as an interleaving region on each of the one or more first and second memory devices for each of the plurality of memory segments, wherein the interleaving region on each of the one or more first and second memory devices may be accessed simultaneously.