Patent ID: 8958549
Filing Date: 2015-02-17
Classification: H04L

Abstract:
1. A countermeasure method in an integrated circuit, comprising: introducing a first datum into a first input of a first input register; reading the first datum from the first input register using a first logic circuit; prior to the introducing and reading, introducing a first random datum into the first input of the first input register; reading the first random datum from the first input register by the first logic circuit prior to introducing the first datum into the first input register; ciphering the first random datum and the first datum within the first logic circuit via at least one logic function having the first random datum and the first datum as inputs; introducing a first output datum generated by the first logic circuit from the first random datum into a first input of a second input register; introducing a second output datum generated by the first logic circuit from the first datum into the first input of the second input register; and feeding the first random datum back to a second input of the second input register.