Patent ID: 6195298
Filing Date: 2001-02-27
Classification: G11C

Abstract:
A semiconductor integrated circuit compriisng:a bit line pair;a memory cell connected to said bit line pair;a sense amplifier amplifying a potential difference between bit lines of said bit line pair caused by reading data from said memory cell; andsense amplifier drive means for supplying to said sense amplifier a largest voltage to be charged in said memory cell while said sense amplifier is activated, said sense amplifier drive means includinga first internal power supply node connected to said sense amplifier,first voltage supply means connected to said first internal power supply node for generating a first voltage not depending on an external power supply voltage and higher than said largest voltage and for supplying said first voltage to said first internal power supply node when said first voltage supply means receives a first activation signal,second voltage supply means connected to said first internal power supply node for generating and supplying said largest voltage to said first internal power supply node,a decoupling capacitance connected to said first internal power supply node and charged to attain said first voltage while said sense amplifier is inactivated, andcontrol means for supplying said first activation signal to said first voltage supply means while said sense amplifier is inactivated.