Patent ID: 6982582
Filing Date: 2006-01-03
Classification: H03K

Abstract:
1. A comparator comprising: a first input transistor with a first terminal, a second terminal and a gate terminal, wherein the gate terminal is in communication with a first input and the first terminal of the first input transistor is in communication with a first reference voltage via a first electrical path, the first electrical path including a first current source and a resistor to generate a hysteresis offset; a second input transistor with a first terminal, a second terminal and a gate terminal, wherein the gate terminal is in communication with a second input and the first terminal of the second input transistor is in communication with the first reference voltage via a second electrical path; a third transistor having a first terminal, a second terminal and a gate terminal, wherein the gate terminal communicates with said second terminal of said first input transistor; a capacitor that communicates with said gate of said third transistor; and an output setting toward the first reference voltage when a first signal at the first input exceeds the hysteresis offset or a second reference voltage when the first signal at the first input does not exceed the hysteresis offset.