Patent ID: 6693468
Filing Date: 2004-02-17
Classification: H03L

Abstract:
A fractional sequence generator comprisinga first n-bit accumulator, A1, for adding a fractional multi-bit input word to a previously accumulated total to provide a new n-bit total, N1, and a carry-out signal, CO1, when said N1 overflows said n-bit accumulator, an ordered plurality of additional n-bit accumulators, Aj, j=2, 3, . . . , K, each Aj adding an n-bit input word to a previously accumulated total to provide a respective new n-bit total, Nj, and a respective carry-out signal COj when said, Nj overflows said Aj, A2 receiving said N1 as an input word, and each Aj, j>1 receiving Njâˆ’1 as an input word, and a recombination network comprising an adder providing an output equal to the sum of weighted increments and decrements, each increment and decrement associated with a respective selectively delayed one of said COj, and a plurality of delay elements for selectively delaying said COj, COK experiencing Kâˆ’1 units of delay, COj, j