Patent ID: 6433392
Filing Date: 2002-08-13
Classification: H01L

Abstract:
An integrated circuit, comprising:(a) a silicon substrate; (b) first and second p-well regions with first and second doping profiles (doping concentration as a function of distance) in a direction perpendicular to and extending from a surface of said substrate, said first p-well region containing an NMOS device, said second p-well region containing an ESD protection device; and (c) an n-well region, said n-well region with a third doping profile in said direction, said n-well containing a PMOS device, wherein said second doping profile is the difference of said first doping profile and said third doping profile near said surface. (a) said first profile is characterized by implants of dopants of p type at energy levels E1, E2, . . . , and En where n is an integer greater than or equal to 2; (b) said third profile is characterized by implants of dopants of n type at energy levels F1, F2, . . . , and Fm where m is an integer greater than or equal to 2; and (c) said second profile is characterized by implants of dopants of p type at said energy levels E1, E2, . . . , and En plus implants of dopants of n type at energy levels F1, F2, . . . , and Fm.