Patent ID: 7135761
Filing Date: 2006-11-14
Classification: H01L

Abstract:
1. A power semiconductor package, comprising: a leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a third terminal; a power semiconductor die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a second current carrying electrode and a second metalized region defining a control electrode are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the first current carrying electrode; a clip coupled to the first metalized region defining the second current carrying electrode and to the at least one second terminal such that it is electrically coupled to the second current carrying electrode; and a ribbon bond coupling the control electrode to a third terminal, wherein the ribbon bond comprises a rectangular shaped conductor having a width greater than its thickness, and wherein the control electrode has an area less than or equal to approximately three times the width by three times the thickness.