Patent ID: 6451701
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A method for forming reliable ohmic silicide contacts to a substrate between closely spaced electrically conducting lines having insulating sidewall spacers comprising the steps of:providing a semiconductor substrate having device areas; forming a gate oxide layer on said device areas; depositing a conducting layer on said substrate; patterning said conducting layer to form said closely spaced electrically conducting lines; depositing a conformal silicon oxide insulating layer and anisotropically plasma etching to form sidewall spacers on said closely spaced conducting lines, wherein the etch rate of said plasma etching is inadvertently reduced between said closely spaced conducting lines resulting in an unwanted residual silicon oxide in spaces between said closely spaced conducting lines; implanting ions in surface of said substrate thereby amorphizing said residual silicon oxide to increase the etch rate of said residual silicon oxide; wet etching to completely remove said residual silicon oxide having said increased etch rate, and removing said gate oxide to said substrate, without overetching other portions of said silicon oxide of said sidewall spacers; forming silicide contacts on said substrate adjacent to said sidewall spacers.