Patent ID: 8008955
Filing Date: 2011-08-30
Classification: H03L

Abstract:
1. A semiconductor device comprising: a voltage-controlled oscillator outputting an output clock signal; N pieces (N is a natural number equal to or more than 2) of control circuit sections being inputted a reference clock signal and the output clock signal; an adder adding output signals outputted from each of the N pieces of control circuit sections; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein the control circuit section comprises: wherein the setting information related to the frequency division ratio is N pieces of data which are cycled and supplied in a sequence in synchronization with the frequency-divided clock signal outputted from the variable frequency divider to which the setting information is supplied and in which the frequency division ratio of the variable frequency divider is fluctuated by synchronizing a frequency division ratio set by each data with the frequency-divided clock signal so that an average frequency division ratio may include a decimal fraction, and wherein the setting information having N pieces of data is supplied to the respective variable frequency divider of the control circuit section with initial values thereof made different from one another.