Patent ID: 7949854
Filing Date: 2011-05-24
Classification: G06F

Abstract:
1. An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequences of operations, based on one or more sequences of instructions, to an execution circuit of the processor, where the instruction processing circuit comprises a trace builder circuit operable to: receive at least a portion of a sequence of operations of a first type and to generate, based thereon and for optimizing operations thereof using a first optimization technique, a sequence of operations of a second type for storing in a cache circuit, wherein the at least a portion of the sequence of operations of the first type represents a portion of a sequence of instructions, wherein the portion of the sequence of instructions includes at most one control transfer instruction that, when present, ends the portion of the sequence of instructions; receive, from the cache circuit, sets of at least two sequences of operations and to generate, based thereon and for optimizing operations thereof using a second optimization technique, a plurality of sequences of operations of a third type, wherein a sequence of operations of the third type comprises one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, wherein the another sequence of operations of the third type is generated by the trace builder circuit for storing in the cache circuit; and retrieve the sequence of operations of the second type and the another sequence of operations of the third type from the cache circuit for generating the sequence of operations of the third type, wherein the first optimization technique and the second optimization technique comprise reordering of operations, removal of operations, removal of dependencies between operations, and grouping of operations.