Patent ID: 7739428
Filing Date: 2010-06-15
Classification: H04L

Abstract:
1. A memory control apparatus that controls data transfer between a plurality of devices and a memory, comprising: a parameter-recognizable portion having a parameter whose values are externally recognizable, said parameter serving as a basis for determining an order of priorities indicating which of said plurality of devices should be given a right to perform said data transfer; and a priority order setting portion that sets said order of priorities on the basis of the values of said parameter, wherein said parameter-recognizable portion includes a plurality of buffers that are assigned to said plurality of devices, said parameter is information about the amounts of data remaining respectively in said plurality of buffers, and said priority order setting portion receives a data transfer request signal from said plurality of devices, and on the basis of an urgency notice signal that is sent separately from said data transfer request signal based on the amounts of data remaining respectively in said plurality of buffers, said priority order setting portion sets an order of priorities of a data transfer performed by the device that is sending said urgency notice signal.