Patent ID: 9053756
Filing Date: 2015-06-09
Classification: G11C

Abstract:
1. A memory device, comprising: a plurality of re-writeable non-volatile two-terminal memory devices in electrical communication with a memory bus, each memory device including at least one memory layer including a plurality of memory elements having exactly two terminals and configured in at least one two-terminal cross-point array, each memory element is configured to store data associated with resistance values, and a silicon substrate including circuitry fabricated on a logic layer of the silicon substrate and at least a portion of the circuitry electrically coupled with the at least one two-terminal cross-point array and configured to perform data operations on one or more of the plurality of memory elements, wherein the at least one memory layer is in contact with and is fabricated directly above the silicon substrate; at least one preservation circuit in electrical communication with the at least one two-terminal cross-point array and operative to perform preservation operations on one or more of the plurality of memory elements and configured to, in response to a trigger signal, restore the resistance values to represent the data; and at least one trigger circuit electrically coupled with the at least one preservation circuit and configured to detect a triggering event and generate the trigger signal.