Patent ID: 7363554
Filing Date: 2008-04-22
Classification: G11C

Abstract:
1. A content addressable memory comprising: a content addressable memory cell array including a plurality of content addressable memory cells; a priority encoder for testing the content addressable memory cell array to determine if there is an error in the content addressable memory cell array by comparing search data fed to the memory cell array with data stored in the plurality of content addressable memory cells; and a shift register unit, operable in response to a clock signal fed thereto, for transmitting first through m-th independent test data to the priority encoder for independently testing the priority encoder to determine if there is an error in the priority encoder, wherein logic levels of the first through m-th independent test data from the shift register unit are sequentially changed in synchronization with the clock signal and fed to the priority encoder without being written to the memory cell array, whereby the priority encoder generates outputs in response to the first through m-th independent test data.