Patent ID: 8647950
Filing Date: 2014-02-11
Classification: H01L

Abstract:
1. A method of fabricating a vertical gate region in a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising: depositing a first masking layer on an n-well region implanted on a substrate; patterning the first masking layer to define an area; depositing a second masking layer over the area; etching through the second masking layer in a first portion of the area to expose the n-well region; etching the exposed n-well region to form a first trench such that the first trench extends from a surface of the n-well region to a first depth in the n-well region; filling the first trench with an oxide; etching through the second masking layer in a second portion of the area to expose the n-well region; forming a second trench in the n-well such that the second trench abuts the first trench and extends from the surface of the n-well region to a second depth in the n-well region, the second depth being less than the first depth; and forming an asymmetric vertical gate of the LDMOS transistor by filling the second trench with a conductive material.