Patent ID: 6265296
Filing Date: 2001-07-24
Classification: H01L

Abstract:
A method of forming self-aligned contacts on a semiconductor substrate using a hard mask, which comprises the steps of:providing a semiconductor substrate;forming a gate oxide layer on said semiconductor substrate; forming a gate electrode layer on said gate oxide layer;forming a gate electrode protecting layer on said gate electrode layer; patterning said gate electrode protecting layer and said gate electrode layer, thereby forming gate electrode structures having vertical sidewalls;forming first doped regions in portions of said semiconductor substrate adjacent to said gate electrode structures;forming insulating sidewall spacers on said sidewalls of said gate electrode structures;forming second doped regions in portions of said semiconductor adjacent to said sidewall spacers;forming a blanket insulating layer on said semiconductor substrate;forming a hard mask having openings on said blanket insulating layer, said openings overlaying said first doped regions, said second doped regions and part of said gate electrode structure wherein said hard mask has a thickness generally between 1000 and 2000 angstroms (.ANG.);etching said blanket insulating layer to said gate electrode protecting layer through said openings;etching said blanker insulating layer to expose said second doped regions using said gate electrode protecting layer and said insulating sidewall spacers as the mask, thereby forming said self-aligned contactswherein said hard mask is composed of a material consisting of polysilicon, silicon nitride, aluminum oxide, silicon oxynitride and titanium nitride.