Patent ID: 7964966
Filing Date: 2011-06-21
Classification: H01L

Abstract:
1. A semiconductor interconnect structure comprising: a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the at least one conductively filled via is in contact with an exposed surface of the at least one conductive feature of the lower interconnect level by a gouging feature, and wherein the at least one conductively filled line includes a trench diffusion barrier and a combined trench and via diffusion barrier separating the at least one conductively filled line from an upper portion of the second dielectric material, while the at least one conductively filled via includes only the combined trench and via diffusion barrier separating a lower portion of the at least one conductively filled via from the second dielectric material, and wherein the combined trench and via diffusion barrier is also positioned at the gouging feature between a lower portion of the at least one conductively filled via and the at least one conductive feature embedded in the first dielectric material, wherein the combined trench and via diffusion barrier comprises TaN, Ta, Ti, TiN, RuTa, RuTaN, W, Ru, Co, Rh, Ir or any combination thereof.