Patent ID: 6677783
Filing Date: 2004-01-13
Classification: H03K

Abstract:
A circuit comprising:one or more domino logic stages; a first wide-pulsed clock generator to provide a first wide-pulsed clock signal to control evaluation of the one or more domino logic stages in response to receiving a two-phase input clock signal, the first wide-pulsed clock signal to have a pulse width that tracks a phase width of the input clock signal over a first frequency range, the first frequency range extending at least from a predetermined fraction of a nominal clock frequency to an upper frequency limit for the circuit; wherein, the first wide-pulsed clock generator comprises a chopper circuit having a relatively long inverting delay path, and wherein the inverting delay path includes a plurality of inverters, the inverters including devices that are sized such that a transition of the input clock signal in a first direction is communicated through the inverting delay path faster than a transition of the input clock signal in an opposite direction.