Patent ID: 6636066
Filing Date: 2003-10-21
Classification: G01R

Abstract:
A semiconductor integrated circuit comprising:a plurality of output buffers each comprising a P-channel transistor and an N-channel transistor, a drain of the P-channel transistor and a drain of the N-channel transistor commonly bonded to an external output terminal; a control circuit which, in measuring the resistance value of the plurality of output buffers, selects one output buffer and brings the P-channel transistor and the N-channel transistor provided in the selected output buffer to an ON state while bringing the external output terminals of the remaining output buffers to a high-impedance state; and a first source of a first constant voltage at which the N-channel transistors operate in an unsaturated region, said first source being selectively connected to gates of the N-channel transistors; a second source of a second constant voltage at which the P-channel transistors operate in an unsaturated region, said second source being selectively connected to gates of the P-channel transistor.