Patent ID: 7436915
Filing Date: 2008-10-14
Classification: H04B

Abstract:
1. An FIR (Finite Impulse Response) filter of a DS-CDMA (Direct Sequence Code Division Multiple Access) UWB (Ultra Wide-Band) modem transmitter, the FIR filter using a symbol clock as an internal operation clock and comprising: a pair of plural upper/lower LUTs (Look-Up Tables) in which pulse-shaped LUT resultant values are pre-stored; a plurality of adders for adding the upper/lower LUT resultant values, respectively, and an LUT control device for wherein the LUT control device comprises: a plurality of complement conversion units, connected to the upper and lower LUTs, respectively, for converting the upper or lower LUT values outputted by the upper/lower LUTs into the 2's complements; a plurality of first switches, connected to the upper LUTs and output terminals of the complement conversion units that match the upper LUTs, respectively, for switching paths of the respective output terminals; a plurality of second switches, connected to the lower LUTs and the output terminals of the complement conversion units that match the lower LUTs, respectively, for switching paths of the respective output terminals; a plurality of third switches, connected between the first switches and the corresponding adders, respectively, for connecting the corresponding first switches to the corresponding adders, respectively, or disconnecting the corresponding first switches from the corresponding adders, respectively, and passing the resultant value of “0” to the corresponding adders; a plurality of fourth switches, connected between the second switches and the corresponding adders, respectively, for connecting the corresponding second switches to the corresponding adders, respectively, or disconnecting the corresponding second switches from the corresponding adders, respectively, and passing the resultant value of “0” to the corresponding adders; a first data discrimination unit for discriminating whether the 6-bit data values corresponding to the upper three chips H first switching control units for controlling the third and fourth switches to provide the resultant value of “0” to all the adders if the first data discrimination unit discriminates that the data values corresponding to the upper three chips H a second data discrimination unit for discriminating whether the upper/lower data values belong to the first group or the second group if the first data discrimination unit discriminates that the data values corresponding to the upper three chips H second switching control units for connecting the corresponding upper or lower LUTs to the corresponding adders through the first and second switches, respectively, if the second data discrimination unit discriminates that the data values corresponding to the upper three chips H a LUT address mapper for calculating LUT memory values using the data values and then performing a mapping of the calculated LUT memory values onto the corresponding LUTs to provide the resultant values by phases of the corresponding upper/lower LUTs to the corresponding adders, respectively, if the first data discrimination unit discriminates that the data values corresponding to the upper three chips H