Patent ID: 8521982
Filing Date: 2013-08-27
Classification: G06F

Abstract:
1. A method of data processing in a processing unit including a processor core, an upper level cache memory, and a lower level cache memory, the method comprising: in response to receiving, from the processor core, a load-type request at a lower level cache memory, allocating an entry among a plurality of entries in a request queue of a core interface unit (CIU) in the lower level cache memory to the load-type request; the CIU detecting contention for at least one of one or more resources between the load-type request and another memory access request in the processing unit; in response to detecting contention for at least one of the one or more resources, the CIU suspending issuance of the load-type request from the entry of the request queue until the contention is resolved; in response to the contention being between the load-type request and a store queue entry: in response to removal of the contention, terminating tracking of the specific RC machine if the contention was between the load-type request and a store queue entry and issuing the load-type request from the request queue for processing by the lower level cache memory.