Patent ID: 9105343
Filing Date: 2015-08-11
Classification: G11C

Abstract:
1. A method for detecting individual resistance states of a plurality of memory elements coupled in series in a memory device, each of the plurality of memory elements having a resistance state and can be switched from a first resistance level to a second resistance level by a write input no lower than a write threshold, the method comprising the steps of: sequentially writing at least one of the plurality of memory elements from the resistance state thereof to the second resistance level in order of ascending write threshold; ascertaining whether each of the at least one of the plurality of memory elements has switched from the first resistance level to the second resistance level; concluding the resistance state of the each of the at least one of the plurality of memory elements is in the first resistance level if the each of the at least one of the plurality of memory elements has switched; and concluding the resistance state of the each of the at least one of the plurality of memory elements is in the second resistance level if the each of the at least one of the plurality of memory elements has not switched.