Patent ID: 7091091
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A method for manufacturing an integrated circuit comprising one or more nonvolatile memory cells, each memory cell comprising at least one conductive floating gate, the method comprising: (1) forming a first dielectric on a semiconductor substrate; (2) forming a first layer on the first dielectric, the first layer to provide a first portion of each said floating gate; (3) removing portions of the first layer, the first dielectric, and the semiconductor substrate, to form one or more trenches in the semiconductor substrate, the one or more trenches being to provide isolation between active areas of the integrated circuit, the one or more trenches comprising one or more first edges, each first edge being an edge of an active area of a nonvolatile memory cell, wherein at a conclusion of this operation (3) the first dielectric is spaced from the one or more first edges; (4) forming a second dielectric in and over the one or more trenches adjacent to the first portions of the floating gates, wherein forming the second dielectric comprises thermally oxidizing the semiconductor substrate; (5) removing first portions of the second dielectric in first regions which are adjacent to the first edges of the trenches and are also adjacent to sidewalls of the first portions of the floating gates; (6) forming a second layer on the first layer to provide second portions of the floating gates, wherein the second portions of the floating gates extend into the first regions; wherein the operation (3) comprises: (3A) patterning the first layer, the first dielectric, and the semiconductor substrate, to form the trenches; and (3B) after the patterning operation, etching the first dielectric at the first edges of the trenches selectively to the semiconductor substrate, to remove portions of the first dielectric under the edges of the first layer at the first edges of the trenches; wherein at a conclusion of the etching of the first dielectric in the operation (3B), the semiconductor substrate has a first geometry at the first edges, the first geometry being defined by the semiconductor substrate's surface at the first edges; wherein the thermal oxidation of the semiconductor substrate in the operation (4) begins when the semiconductor substrate has the first geometry at the first edges, and the thermal oxidation in the operation (4) changes the first geometry to round the first edges of the trenches or to cause the first edges of the trenches to become more rounded.