Patent ID: 7982313
Filing Date: 2011-07-19
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a first plurality of circuit elements and a second plurality of circuit elements formed in and above a device substrate comprising a semiconductor material; a metallization system formed above said first and second pluralities of circuit elements, wherein said metallization system comprises one or more metallization layers and a final contact layer adapted to connect to a package substrate; a stress relaxation region provided at least in said metallization system, wherein said stress relaxation region defines a first sub-area of said metallization system formed above said first plurality of circuit elements and separates said first sub-area from at least a second sub-area of said metallization system formed above said second plurality of circuit elements; and a metal line portion formed in at least one of said one or more metallization layers, wherein said metal line portion extends across said stress relaxation region from said first sub-area to said second sub-area so as to electrically connect at least one of said first plurality of circuit elements below said first sub-area and at least one of said second plurality of circuit elements below said second sub-area.