Patent ID: 7444540
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A system for memory mirroring, comprising: a mirror memory having a memory fully buffered controller, the memory fully buffered controller being configured to facilitate access to a plurality of memories in the mirror memory by a central processing unit (CPU); a primary memory link interface in the memory fully buffered controller configured to couple to a primary memory; where the memory fully buffered controller further comprises: first error logic configured to detect whether a first data error exists in a first data output from the primary memory, the first error logic comprising logic that attempts to correct the first data error if detected; second error logic configured to detect whether a second data error exists in a second data output from the mirror memory, the second error logic further comprises logic that attempts to correct the second data error if detected; and selection logic that selects one of the first data output or the second data output to be applied to the CPU, where the selection logic further comprises logic that selects an uncorrected one of the first and second data outputs to be applied to the CPU if one of the first and second data outputs has been corrected by one of the first and second error logic, respectively.