Patent ID: 7430238
Filing Date: 2008-09-30
Classification: H04N

Abstract:
1. A video decoding system configured with a multi-stage shared pipeline architecture for carrying out the H.264 CABAC and CALVC entropy decoding processes in Main Profile and High Profile, comprising: a first stage for grouping macro block properties into 4×4 sub blocks; a second stage for performing separation of coefficients and run level pairs; a third stage for performing run level pair decoding; a fourth stage for performing 4×4 block zigzag transform, DC/AC coefficient merging, and motion vector prediction; a fifth stage for performing 8×8 transforms in the High Profile, and is skipped in the Main Profile; a fractional interpolation block and in-line loop filter (FIB/ILF) memory interfaced to the fifth stage via a 128-bit bus, wherein for every macro block, there are 18 data beats of 128 bits that contain macro block properties and expanded motion vector information of luma and chroma for forward and backward reference; a DSP macro block header/data memory interfaced to the fifth stage via the 128-bit bus, wherein for every 16×16 macro block, the DSP macro block header/data memory has 1 data beat of 128 bits for a header that includes information for macro block properties and 48 data beats of 128 bits for coefficients; and a dual channel write memory interfaced to the fifth stage via the 128-bit bus, wherein write channel