Patent ID: 8400604
Filing Date: 2013-03-19
Classification: G02F

Abstract:
1. An array substrate for an IPS-mode LCD device, comprising: a substrate having a switching region and a pixel region; a gate line on the substrate; a gate electrode formed in the switching region and extending from the gate line; first and second common lines in one pixel region, each of the first and second common lines substantially parallel to the gate line and separated from the gate line; a common connection line being disposed outside of the pixel region and connecting the first and second common lines, the common connection line being positioned at the same layer as the first and second common lines and the gate line; one common line pad electrode for applying a common voltage to the first and second common lines; first and second common electrodes extending from each of the first and second common lines into the pixel region and separated from each other; a gate insulating layer on the gate line, each of the first and second common lines and the first and second common electrodes, wherein the gate insulating layer has a common line contact hole exposing one of the first and second common lines; a data line crossing the gate line to define the pixel region on the gate insulating layer; a semiconductor layer corresponding to the gate electrode on the gate insulating layer; a source electrode and a drain electrode separated from each other on the semiconductor layer, wherein the source electrode extends from the data line; a plurality of pixel electrodes between the first and second common electrodes, wherein the plurality of pixel electrodes are separated from each other and substantially parallel to the first and second common electrodes, and each of the plurality of pixel electrodes extends from the drain electrode; and a plurality of third common electrodes formed on the gate insulating layer, wherein the plurality of third common electrodes are connected to the one of the first and second common lines through the common line contact hole and alternately arranged with the plurality of pixel electrodes, wherein the data line, the plurality of pixel electrodes and the plurality of third common electrodes are formed on a same layer and with a same material as one another, and the data line, the plurality of pixel electrodes and the plurality of third common electrodes are formed of an opaque metallic material.