Patent ID: 6191986
Filing Date: 2001-02-20
Classification: G11C

Abstract:
A memory device with redundancy arrays, comprising:a plurality of row word lines, selected by a plurality of row address signals which include a first and a second row address signal, and other row address signals;a plurality of column selective lines, selected by a plurality of column address signals;a memory bank with a first block and a second block separately driven by different logic values of the first row address signal; anda plurality of pairs of odd arrays and even arrays and a plurality of spare rows and spare columns corresponding to the odd arrays and the even arrays, located in the first block and the second block, wherein the odd arrays and the even arrays are separately driven by different logic values of the second row address signal, and the other row address signals are used to select the row word lines located in the odd arrays or the even arrays;wherein, when a selected row word lines is a defective row, it will be replaced by one of the spare rows, and if a selected column selective line is a defective column, it will be replaced by one of the spare columns.