Patent ID: 6433377
Filing Date: 2002-08-13
Classification: G11C,H01L

Abstract:
A chain RAM, comprising:a bit line; a plate line; a memory cell array having a plurality of memory cells connected in series between the bit line and plate line, wherein each memory cell comprises: (1) a first ferroelectric capacitor having upper and lower electrodes, between which a ferroelectric layer is provided; (2) a second ferroelectric capacitor having upper and lower electrodes, between which a ferroelectric layer is provided; and (3) a transistor connected to the upper and lower electrodes of the first and second ferroelectric capacitors, wherein the upper electrode of the first ferroelectric capacitor is connected to the lower electrode of the second ferroelectric capacitor, and the lower electrode of the first ferroelectric capacitor is connected to the upper electrode of the second ferroelectric capacitor in a complimentary manner.