Patent ID: 9214579
Filing Date: 2015-12-15
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor structure, the manufacturing method comprising: (a) providing a wafer structure having a silicon substrate and a protection layer, wherein an electrical pad on the protection layer is exposed through a concave region of the silicon substrate; (b) forming an isolation layer on a sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer; (c) forming a redistribution layer on the isolation layer and the electrical pad; (d) forming a passivation layer on the redistribution layer; (e) patterning the passivation layer to form a first opening and a second opening therein, thereby exposing the redistribution layer on the surface of the silicon substrate through the first opening and exposing the redistribution layer on the electrical pad and the sidewall through the second opening; (f) forming a first conductive layer on the redistribution layer that is exposed through the first opening and a second conductive layer on the redistribution layer that is exposed through the second opening; and (g) arranging a conductive structure in the first opening, thereby enabling the conductive structure to electrically contact the first conductive layer.