Patent ID: 8931082
Filing Date: 2015-01-06
Classification: G06F

Abstract:
1. A computing system, comprising: a memory storage device comprising a secured portion; a host processor communicably coupled to the memory storage device, the host processor configured to receive requests from a client device to access data in the secured portion of the memory storage device; a first security central processing unit (SCPU) comprising a security processor configured to execute functions of a first security level comprising verification of identity of the client device; a second SCPU communicably coupled with the first SCPU and communicably coupled with the host processor, the second SCPU comprising a security processor configured to execute functions of a second security level less secure than the first security level and more secure than a level of security of functions executed by the host processor, the functions of the second security level comprisinq decryption of the data requested by the client device from the memory storage device; peripheral devices configured to operate in response to instructions from the security processor of the second SCPU; and the host processor being configured to transmit the decrypted data to the client device, wherein the host processor is disallowed access to the decrypted data until decrypted by the second SCPU.