Patent ID: 6717624
Filing Date: 2004-04-06
Classification: H04N

Abstract:
A line memory comprising:first and second memories respectively having a memory capacity which is half of a memory capacity required to store all pieces of dot data of one line; read address producing means for producing a read address signal to be used to read out the dot data for each dot; write address producing means for producing a write address signal to be used to write the dot data for each dot; and a memory access signal producing unit for performing, for each time-period of a reading-out or a writing-in, both the production of an address signal, which specifies an address of the first memory or the second memory, and a read enable signal, which is used to alternately read out dot data of a preceding line stored in the first memory or the second memory, according to the read address signal produced by the read address producing means and the production of an address signal, which specifies an address of the second memory or the first memory, and a write enable signal, which is used to alternately write dot data of a current line stored in the second memory or the first memory, according to the write address signal produced by the write address producing means, wherein both the reading-out of the dot data of the preceding line stored in the first memory or the second memory and the writing-in of the dot data of the current line to the second memory or the first memory are performed in the same time-period.