Patent ID: 6620690
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of fabricating a flash memory device, comprising:forming a conductive layer and an oxidation-blocking layer on a stepped pattern, including a floating gate pattern and an inter-gate insulating layer pattern, such that the conductive layer and the oxidation-blocking layer conform to said stepped pattern; forming a photoresist layer on the oxidation-blocking layer, whereby the photoresist layer has an upper surface situated above the oxidation-blocking layer; dissolving a portion of the photoresist layer, without having photo-exposed the photoresist layer, until the upper surface thereof is situated below the upper surface of that part of the oxidation-blocking layer disposed directly above the stepped pattern, and thereby forming a photoresist pattern that exposes part of the oxidation-blocking layer, said dissolving comprising soaking the photoresist layer in a developing solution; removing the part of the oxidation-blocking layer exposed by the photoresist pattern to form an oxidation-blocking layer pattern that exposes that part of the conductive layer disposed directly above the stepped pattern; removing the photoresist pattern; oxidizing the surface of the conductive layer exposed by the oxidation-blocking layer pattern to thereby form a hard mask defining a control gate; subsequently removing the oxidation-blocking layer pattern; etching the conductive layer using the hard mask as an etch mask to thereby form a control gate; and subsequently removing the hard mask.