Patent ID: 7304346
Filing Date: 2007-12-04
Classification: H01L

Abstract:
1. A flash memory cell transistor comprising: a p-well region and a n-well region which are divided by an isolation oxide film on a silicon substrate; a nMOS region comprising a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film; and a pMOS region comprising a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having electron traps and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.