Patent ID: 6776893
Filing Date: 2004-08-17
Classification: C25D,H05K

Abstract:
A method for electrolytic copper filling interconnect features in semiconductor integrated circuit devices, the method comprising:immersing a semiconductor integrated circuit substrate having via and trench interconnect features in an electrolytic solution containing a) copper in an amount sufficient to electrodeposit copper onto the substrate, b) a bath soluble organic divalent sulfur compound corresponding to the formula: R1â€”(S)nRXO3Mâ€ƒâ€ƒ(I) wherein:M is hydrogen, alkali metal or ammonium as needed to satisfy the valence; X is S or P; R is an alkylene or cyclic alkylene group of 1 to 8 carbon atoms, an aromatic hydrocarbon or an aliphatic aromatic hydrocarbon of 6 to 12 carbon atoms; n is 1 to 6; and R1 is MO3XR wherein M, X and R are as defined above, and c) a bath soluble polyether compound selected from the group consisting of block copolymers of polyoxyethylene and polyoxypropylene, a polyoxyethylene or polyoxypropylene derivative of a polyhydric alcohol and a mixed polyoxyethylene and polyoxypropylene derivative of a polyhydric alcohol; and supplying current to the electrolytic solution to fill copper into the via and trench interconnect features and thereby yield a semiconductor integrated circuit substrate with copper-filled via and trench interconnect features.