Patent ID: 6479838
Filing Date: 2002-11-12
Classification: H01L

Abstract:
A thin film transistor formed on an insulating substrate, comprising:a channel region comprising a high melting point region composing a first semiconductor; a source region in contact with the high melting point region of the channel region, the source region comprising a first low melting point region comprising a second semiconductor having a melting point lower than that of the first semiconductor, and the source region containing a first dopant; a source electrode electrically connected to the high melting point region of the channel region via the first low melting point region of the source region; a drain region being spaced apart from the source region and in contact with the high melting point region of the channel region, the drain region comprising a second low melting point region comprising a third semiconductor having a melting point lower than that of the first semiconductor, and the drain region containing a second dopant; a drain electrode electrically connected to the high melting point region of the channel region via the low melting point region of the drain region; and a gate electrode electrically insulated from the channel region, the source electrode, and the drain electrode, the gate electrode controlling an electric field applied to the channel region.