Patent ID: 8737112
Filing Date: 2014-05-27
Classification: G11C

Abstract:
1. A resistive memory device comprising: a memory cell array arranging resistive memory cells according to a plurality of word lines and a plurality of bit lines, wherein a first group of resistive memory cells is connected between the plurality of bit lines and a first plate and a second group of resistive memory cells is connected between the plurality of bit lines and a second plate; a first initialization pad that receives a first initialization voltage from an initialization device external to the resistive memory device and provides the first initialization voltage to the first plate during an initialization operation; a second initialization pad that receives a second initialization voltage from the initialization device and provides the second initialization voltage to the second plate during the initialization operation, wherein the first and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.