Patent ID: 6678195
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory blocks each having a plurality of normal memory cells; a plurality of spare memory blocks provided corresponding to said plurality of memory blocks each for repairing a defective normal memory cell in a corresponding memory block; a plurality of local data buses provided corresponding to said plurality of memory blocks each for transferring data with a corresponding memory block; a plurality of spare local data buses provided corresponding to said plurality of spare memory blocks each for transferring data with a corresponding spare memory block; a global data bus provided in common to said plurality of memory blocks and selectively coupled with a local data bus provided corresponding to a memory block including a selected normal memory cell; and a spare global data bus provided in common to said plurality of spare memory blocks and coupled simultaneously and selectively with a spare local data bus provided corresponding to k spare memory blocks including a spare memory block including a selected spare memory cell, said k being an integer no less than two.