Patent ID: 6617892
Filing Date: 2003-09-09
Classification: H04L

Abstract:
An interconnect system comprising:interconnects; quasi-static drivers to transmit interconnect signals on the interconnects, the quasi-static drivers including inputs to receive a clock signal and respective data-in signals, and wherein the interconnect signals are pre-discharged when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals, and wherein the drivers include a pFET pull-up device and an nFET pull-up device to selectively pull the interconnect signals high wherein the drivers transmit the interconnect signals that have a high voltage equal to a power supply voltage minus a threshold voltage of the nFET device and wherein the system further includes body bias voltage circuitry to control the threshold voltage of the nFET device; and receivers connected to respective ones of the interconnects.