Patent ID: 6816955
Filing Date: 2004-11-09
Classification: G06F,G11C

Abstract:
An apparatus for providing arbitration for a dual-port memory comprising:a first bus coupled to a first port of said dual-port memory and configured to present write data and one or more write control signals to said dual-port memory; a second bus (i) coupled to a second port of said dual-port memory and (ii) configured to present read data from said dual-port memory to a first input of a multiplexer circuit; a third bus configured to present said write data to a second input of said multiplexer circuit, wherein said third bus is separate from said dual-port memory and said apparatus is configured to present said write data (i) as an input to said dual-port memory and (ii) as an output from said multiplexer during contention between simultaneous read and write operations; a logic circuit (a) configured to control said contention between simultaneous read and write operations and (b) comprising (i) a write interface logic configured to generate a write address signal and a write enable signal according to a comparison between a system clock and a write clock, (ii) a read interface logic configured to generate a read address signal and a read enable signal according to a comparison between said system clock and a read clock and (iii) a read/write contention circuit coupled between said write interface logic and said read interface logic; and said dual-port memory is configured to store and retrieve data in response to said one or more write control signals and one or more read control signals from said logic circuit.