Patent ID: 7676653
Filing Date: 2010-03-09
Classification: G06F

Abstract:
1. A decode unit for decoding instructions in a processor, the decode unit comprising opcode decoding logic, operand decoding logic, and a sixteen-bit input; wherein the opcode decoding logic is operable to determine an opcode using five bits of the sixteen-bit input, there thus being eleven other bits of the sixteen-bit input, and the operand decoding logic is operable to determine three four-bit operand elements from the eleven other bits of the sixteen-bit input, the three four-bit operand elements each having one of twelve possible binary values; and the operand decoding logic is operable to decode a non-verbatim encoded group of said eleven other bits of the sixteen-bit input to determine a first part of each of the three four-bit operand elements, and to read verbatim a verbatim group of said eleven other bits of the sixteen-bit input to determine a second part of each of the three four-bit operand elements.