Patent ID: 6541998
Filing Date: 2003-04-01
Classification: H04L

Abstract:
A circuit comprising:a first transistor having (i) a first drain node configured to be coupled to a conductor, (ii) a first source node configured to be coupled to a first reference voltage, and (iii) a first gate node; a second transistor having (i) a second drain node configured to be coupled to said conductor, (ii) a second source node configured to be coupled to a second reference voltage, and (iii) a second gate node; a third transistor having (i) a third gate node coupled to a third drain node and (ii) a third source node coupled to said first gate node to bias said first gate node; a fourth transistor having (i) a fourth gate node coupled to a fourth drain node and (ii) a fourth source node coupled to said second gate node to bias said second gate node; a fifth transistor (i) in series with said first transistor, (ii) configured to conduct in response to a first control signal in an enable state and (iii) configured to not conduct in response to said first control signal in a disable state; and a sixth transistor (i) in series with said second transistor, (ii) configured to conduct in response to a second control signal in said enable state and (iii) configured to not conduct in response to said second control signal in said disable state.