Patent ID: 7590891
Filing Date: 2009-09-15
Classification: G06F

Abstract:
1. A debugging circuit, comprising: a central processing unit that executes a predetermined program and generates a control signal when executing the predetermined program; a control register, included in the central processing unit, that receives debug data that is used to debug the predetermined program; a mode judgment circuit, coupled to the central processing unit, that generates a mode judgment signal when a reset of the central processing unit has been canceled and the control register has not received the debug data, wherein the mode judgment signal indicates that the central processing unit is preparing to debug the predetermined program; a monitoring circuit, coupled to the central processing unit and the mode judgment circuit, that generates a monitoring signal based on the control signal and the mode judgment signal, wherein the monitoring signal is indicative of an attempt by the central processing unit to execute the predetermined program during the debugging preparation; a selection circuit, coupled to the monitoring circuit and the central processing unit, that prevents the central processing unit from executing the predetermined program during the debugging preparation, responsive to the monitoring signal; a memory circuit that stores an instruction code which corresponds to the predetermined program; an input-output circuit that receives an external instruction code; and a data bus coupled to the selection circuit, the memory circuit and the input-output circuit, wherein one of the instruction code and the external instruction code is transferred along the data bus, responsive to the control signal, wherein the data bus includes a data bus control signal line along which the control signal is transferred, and wherein the control signal controls the transferring of the one of the instruction code and the external instruction code along the data bus, and wherein the selection circuit is coupled to the data bus control signal line to receive the control signal and turns the data bus control signal line to an idle state so that the central processing unit is prevented from executing the predetermined program during the debugging preparation.