Patent ID: 6881992
Filing Date: 2005-04-19
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a substrate layer of a first dopant type; a doped well region provided within said substrate layer, said doped well region being of a second dopant type; a transistor formed by a source, a drain, and a gate located between said source and drain; said source of said transistor being provided within said doped well region, said source of said transistor being of said second dopant type and of a dopant concentration greater than a dopant concentration of said doped well region; and an oxide layer formed directly on said substrate layer, said doped well region, and said source of said transistor; said oxide layer having a varying height such that a height of said oxide layer associated with said doped well region is thicker than a height of said oxide layer associated with said source of said transistor; said oxide layer including a step region, said step region being located where said height of said oxide layer transitions from said height associated with said doped well region to said height associated with said source of said transistor; said oxide layer having a constant height across a perimeter of said doped well region that forms a depletion region with said substrate when a reverse bias voltage is applied across said substrate layer and said doped well region.