Patent ID: 6553542
Filing Date: 2003-04-22
Classification: G06F

Abstract:
A computerized system for minimizing electrostatic discharge (ESD) and latch-up sensitivities in a semiconductor circuit design, comprising:an input data generator operable to generate information describing circuit layout, technology rules, process results, and ESD rules; a device extractor, coupled to said input data generator, operable to extract netlist, locations and parasitic substrate resistance data, as analyzed by said rules; a verification data base, coupled to said device extractor, operable to store said netlist, locations list and resistance list into said verification database; a translator, coupled to said verification data base, operable to generate said netlist, locations list and resistance list in a specific format from said verification database; an output data generator, coupled to said translator, operable to create netlists and location lists of parasitic, ESD- and latch-up-sensitive elements, said lists expressed in specific formats or displays.