Patent ID: 8335895
Filing Date: 2012-12-18
Classification: G06F

Abstract:
1. A system comprising: a memory control unit connected to a first memory device and a second memory device via a command/address bus and at least a portion of a data bus having an upper half and a lower half; the first memory device being operable according to a first bit organization or a second organization, and including a mode register set (MRS) that receives an externally applied code; and the second memory device being operable according to the first bit organization; wherein the memory control unit being configured to communicate data with at least one of the first and second memory devices via the upper half when the first and second memory devices are operated according to the first bit organization, or to communicate data with the first memory device via the lower half and the upper half of a data bus when the first memory device is operated according to the second bit organization.