Patent ID: 6750696
Filing Date: 2004-06-15
Classification: G05F

Abstract:
A level conversion circuit converting a first signal having one level at a reference potential and the other level at a first potential higher than said reference potential into a second signal having one level at said reference potential and the other level at a second potential higher than said first potential, to output the converted signal to an output node, comprising:a load circuit connected between a line of said second potential and said output node; a first N-type transistor having a drain connected to said output node, a source connected to a line of said reference potential, and a gate receiving said first signal; and a bias potential generation circuit having at least one transistor rendered conductive/non-conductive in response to said first signal and generating a bias potential higher than said reference potential and at most said first potential, to apply the bias potential to a backgate of said first N-type transistor, in response to said first signal being set at said first potential.