Patent ID: 6374325
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A content addressable memory (CAM) system, comprising:a CAM array of CAM cells, said CAM array having a number of rows and a number of data words on each row; an address decoder, coupled to said CAM array by a number of row select lines, said address decoder operable to selectively activate certain of said rows in accordance with a row address signal; a bit line controller, coupled to said CAM array by a number of bit line pairs, said bit line controller operable to selectively activate certain data words on said selectively activated rows in accordance with a column address signal; each of said CAM cells operable to store data to, compare data with and retrieve data from said selectively activated data words on said selectively activated rows, said CAM cells further operable to generate signals on a number of match lines to indicate results of said comparison; a priority encoder, coupled to said CAM array by a number of match lines, said priority encoder operable to generate an output row address in accordance with a highest priority matching row in said CAM array as indicated by said match lines.