Patent ID: 6868483
Filing Date: 2005-03-15
Classification: G06F

Abstract:
1. A multiprocessor data processing system comprising: a main memory; at least first and second shared caches coupled to said main memory by a system bus; at least first, second, third and fourth processors having respective first, second, third and fourth private caches, said first and second private caches being coupled to said first shared cache and to one another via a first internal bus, and said third and fourth private caches being coupled to said second shared cache and to one another via a second internal bus; a gate control flag incorporated into each of said first, second, third and fourth processors; a gateword stored in said main memory, said gateword governing access to common code/data shared by processes running in at least three of said processors; a gateword CLOSE command, the execution of which by a first processor establishes ownership of the gateword and prevents other processors from accessing the code/data guarded thereby until said first processor has completed its use thereof; a gateword OPEN command executed by said first processor after it has completed use of the guarded code/data, said gateword OPEN command: broadcasting a gateword interrupt to set the gateword control flag in each of said first, second, third, and fourth processors, delaying long enough to ensure that the gateword control flags have all been set, writing an OPEN value into the gateword, and flushing the shared cache of the executing processor to force the gateword to main memory; and at least one gateword access command executed by a requesting processor to: check the requesting processor's gate control flag, if the requesting processor's gate control flag is set, enter a fixed time delay, and continue normal instruction execution after completion of the fixed time delay.