Patent ID: 7869293
Filing Date: 2011-01-11
Classification: G11C

Abstract:
1. A scannable input/output circuit for a memory device comprising: a sense amplifier receiving one or more bitlines, the sense amplifier comprising a first latch circuit functioning as a scan input circuit when the memory device is operated in a scan mode; and a second latch circuit coupled to the sense amplifier, the second latch circuit producing an output based on data transmitted over the bitlines; a multiplexer coupled to the sense amplifier; a clock circuit coupled to the one or more bitlines; and a test pattern receive circuit synchronized with the clock circuit, and configured to receive test commands comprising a read pre-charge cycle triggered off of a rising edge of a clock signal generated by the clock circuit, a read command following the read-precharge cycle, a write-precharge cycle triggered off of a falling edge of the clock signal, and a write command following the write pre-charge cycle.