Patent ID: 7225379
Filing Date: 2007-05-29
Classification: G01R,G11C

Abstract:
1. A test circuit comprising: a register circuit, into which data is written after data is cleared in compliance with a reset instruction executed by a reset signal, the register circuit holding the written data until a reset instruction is executed by a subsequent reset signal; a first circuit which receives a signal for selecting a test mode to be applied for testing a circuit to be tested, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a second circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a third circuit which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance of the circuit to be tested in accordance with the test pattern and the data output from the circuit to be tested.