Patent ID: 7958340
Filing Date: 2011-06-07
Classification: G06F

Abstract:
1. A method of software pipelining on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.