Patent ID: 6766434
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A method for operating a second level Translation Lookaside Buffer (TLB) in a Symmetric Multiprocessor (SMP) system having multiple processors comprising the steps of:using a respective plurality of processor-dedicated memory areas uniquely dedicated to each of said multiple processors for storing virtual address data and an origin pointer in order to locate an absolute address associated with said virtual address data, using a common memory area shared between said processors for storing at least said absolute address data associated with a virtual address stored in any of said plurality of processor-dedicated memory areas, and defining a TLB hit on a virtual address applied by any of said processors by; checking if subaddress data of said applied virtual address match with respective subaddress data stored in said common memory area, and checking if the respective entries of the processor memory area and the common memory area are valid.