Patent ID: 6103573
Filing Date: 2000-08-15
Classification: H01L

Abstract:
A method of making a non-volatile memory on a semiconductor substrate, comprising:forming elongated source and drain diffusions in the substrate to be spaced apart in a first direction across the substrate and having lengths extending in the second direction across the substrate, said first and second directions being orthogonal with each other,forming an array of floating gates from a first layer of conductive gate material, said array including a plurality of rows that extend in the first direction across the substrate and are spaced apart in the second direction, the rows forming memory cells between adjacent source and drain diffusions that individually include two floating gates capacitively coupled with the substrate through gate dielectric layers over first and second channel regions positioned adjacent the opposing diffusions with a third channel region therebetween,forming from a second layer of conductive gate material a plurality of elongated steering gates having lengths extending in the second direction and being positioned in the first direction to overlay adjacent floating gates of adjacent memory cells and a diffusion therebetween while providing spaces between the steering gates in the first direction over the third channel regions, andforming over the floating and steering gates from a third layer of conductive gate material a plurality of elongated select gates having lengths extending in the first direction along the rows of memory cells and being capacitively coupled with the substrate in the third channel region of the individual cells.