Patent ID: 6764880
Filing Date: 2004-07-20
Classification: H01L

Abstract:
A fabrication method of a semiconductor package, comprising the steps of:preparing a lead frame having a plurality of leads, each of the leads being formed at an inner end thereof with a protruding portion that is dimensioned smaller in thickness than the rest part of the lead, wherein the protruding portion has at least a first surface and a second surface opposed to the first surface, and at least a first bonding region is defined on the first surface and staggered in position with a second bonding region formed on the second surface; preparing at least a first semiconductor chip and a second semiconductor chip, and electrically connecting the second semiconductor chip to the second bonding regions by a plurality of conductive elements, wherein the second semiconductor chip is mounted on the first semiconductor chip; placing the lead frame mounted with the first and second semiconductor chips into a jig, and forming a plurality of bonding wires for electrically connecting the first semiconductor chip to the first bonding regions; and forming an encapsulant for encapsulating the first and second semiconductor chips, the bonding wires and the conductive elements.