Patent ID: 6486691
Filing Date: 2002-11-26
Classification: G01R

Abstract:
A tester for testing a semiconductor IC circuit having multiple pins comprising:pattern generating means for generating a test pattern; a plurality of test signal generating means each for generating a test signal to output to a different input pin of the multiple pins of the semiconductor IC circuit, on the basis of the test pattern output from the pattern generating means according to a test period signal; and timing signal generating means, connected to the plurality of test signal generating means, for supplying timing signals either to one of the test signal generating means or to more than one test signal generating means, said timing signal generating means including first and second timing selectors for sending the timing signals to at least one of said test signal generating means, wherein one or more input pins are tested, and wherein said timing signal generating means generating the test period signal and outputting said test period signal to said pattern generating means.