Patent ID: 9026854
Filing Date: 2015-05-05
Classification: G06F,G11C

Abstract:
1. A method of performing a self-test on a memory device in a test mode, the memory device comprising a memory controller coupled to a flash memory, the memory controller including a host interface, the method comprising: generating a first signal; sending the first signal from a test unit of the host interface through a universal flash storage (UFS) link layer of the host interface to a transmitting unit in a UFS physical layer of the host interface to be transmitted to a receiving unit in the UFS physical layer; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.