Patent ID: 8322020
Filing Date: 2012-12-04
Classification: G01R,H05K,Y10T

Abstract:
1. A method for remanufacturing a semiconductor test probe card space transformer to decrease pitch spacing of a controlled collapse chip connection (C4) contact test pad, the method comprising: providing a space transformer having a substrate and a plurality of first test contacts disposed on a first side of the substrate for performing Device Under Test (DUT) electrical tests, the first test contacts defining a first pitch spacing between the contacts, the first test contacts including first input/output pads and first ground pads; depositing a metal ground plane layer on the first side of the substrate; depositing a first dielectric layer on the ground plane layer; patterning the first dielectric layer to form recesses therein; filling at least some of the recesses with a conductive metal to form a plurality of redistribution leads; and forming a plurality of second test contacts defining a second pitch spacing between the contacts being smaller than the first pitch spacing, at least some of the second test contacts being connected to some of the first test contacts via the redistribution leads.