Patent ID: 8791447
Filing Date: 2014-07-29
Classification: G11C,H01L

Abstract:
1. A method of forming an array of vertically stacked tiers of nonvolatile memory cells, comprising: forming horizontally oriented and laterally overlapping first, second, and third lines within individual tiers of a plurality of vertically stacked tiers; the first and third lines being current conductive and of different composition, the second lines being received between the first and third lines and being of material different in composition from that of the first and third lines; forming pairs of vertically extending and longitudinally aligned first openings through the plurality of tiers on laterally opposing sides of the first, second, and third lines within the individual tiers; laterally etching through the second and third lines selectively relative to the first lines between the respective pairs of first openings to form longitudinally spaced masses which extend vertically relative to the first lines, the masses respectively comprising material of the former second and third lines; forming vertically extending second openings through the plurality of tiers forming programmable material or select device material in current conductive connection with the current conductive material of individual of the masses within individual of the tiers; and forming current conductive material within the second openings in current conductive connection with said programmable material or select device material.