Patent ID: 6033958
Filing Date: 2000-03-07
Classification: H01L

Abstract:
A method of forming dual voltage metal-oxide-semiconductors, comprising the steps of:providing a substrate having a first device region and a second device region defined by an isolation structure;forming a first gate oxide layer having a first thickness, a first polysilicon layer, and a silicon nitride layer sequentially on the substrate;patterning the silicon nitride layer, the first polysilicon layer, and the first gate oxide layer to expose the second device region;thermally oxidizing a surface of the second device region to form a second gate oxide layer with a second thickness different from the first thickness, wherein the second gate oxide layer is not formed over the first device region;removing the silicon nitride layer to expose the first polysilicon layer;forming a second polysilicon layer covering at least the second gate oxide layer;patterning the first and the second polysilicon layer to form a first gate on the first gate oxide layer and a second gate on the second gate oxide layer; andforming a source/drain region in the first device region and the second device region, respectively.