Patent ID: 7215574
Filing Date: 2007-05-08
Classification: G11C

Abstract:
1. In a non-volatile memory having an array of memory storage units, each unit having a charge storage unit between a control gate and a channel region defined by a source and a drain, a method of programming in parallel a page of memory storage units having a common word line interconnecting their control gates, comprising: (a) applying a first predetermined voltage to the drain of each memory storage unit slated to be program-inhibited in the page; (b) applying a second predetermined voltage to the drain of each memory storage unit slated to be programmed in the page, the second predetermined voltage for a memory storage unit to be programmed being a function of how many neighbors are program-inhibited memory storage units in order to compensate for perturbation of any program-inhibited neighbors; (c) applying a programming voltage to the word line in order to program in parallel the memory storage units of the page.