Patent ID: 6611857
Filing Date: 2003-08-26
Classification: G06F,Y02D

Abstract:
A multiplier, comprising:an encoder operable to receive a first and second encoder input; a hierarchy of compressors coupled to the encoder, the compressors operable to receive a first number of inputs and to generate a second number of outputs, the second number less than the first number; a bit detector operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range and operable to deactivate a subset of the compressors when the bit detector determines that the first encoder input is in the reduced precision range; and a switch coupled to a specified one of the compressors, the switch operable to redirect the path of one of the outputs for the specified compressor such that the subset of the compressors is removed from the path when the bit detector determines that the first encoder input is in the reduced precision range.