Patent ID: 8530326
Filing Date: 2013-09-10
Classification: H01L

Abstract:
1. A method of semiconductor device fabrication, comprising: forming a plurality of gate structures in a first portion of a substrate; forming a first metal gate structure in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region; forming a plurality of dummy gate structures in the second portion of the substrate, wherein the plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region, wherein the plurality of dummy structures have a top surface that is substantially planar with a top surface of the plurality of gate structures, and wherein a first polishing stopper covers at least 5% of a pattern density of the second portion of the substrate; forming a monitor pad in a third portion of the substrate, wherein the monitor pad includes a plurality of layers disposed in a stack, wherein the monitor pad includes at least two layers that have a same composition as at least two layers of the plurality of gate structures in the first portion of a substrate; using the monitor pad to monitor a plurality of processing steps during the fabrication including at least one of monitoring a thickness of a deposited material and monitoring a planarization process; forming an alignment mark in a third portion of the substrate; and using the alignment mark to align a photomask and the semiconductor substrate during a photolithography process.