Patent ID: 7101743
Filing Date: 2006-09-05
Classification: H01L

Abstract:
1. A method for forming elevated source/drain regions comprising the steps of: a) forming a gate structure over a substrate; said substrate comprised of silicon; b) forming a polysilicon layer over said gate structure and said substrate to form a polysilicon/Si interface between said polysilicon layer and said substrate; source/drain areas are adjacent to said gate structure in said polysilicon layer and said substrate; c) performing a poly/Si interface amorphization implant to amorphize at least the polysilicon/Si interface in the source/drain areas and to form amorphous regions; d) annealing said substrate to crystallize said amorphous regions and said polysilicon layer over said amorphous region to form elevated silicon regions; e) forming elevated source/drain regions in said elevated silicon regions f) forming silicide regions on said elevated silicon regions.