Patent ID: 9171978
Filing Date: 2015-10-27
Classification: H01L,Y02E,Y02P

Abstract:
1. A method for producing an epitaxial wafer, the method comprising: a step of growing an epitaxial layer structure on a III-V semiconductor substrate, the epitaxial layer structure including a III-Vsemiconductor multiple-quantum well and a III-V semiconductor surface layer, wherein the step of growing the epitaxial layer structure on the substrate is performed such that a lattice mismatch Δω of the multiple-quantum well with respect to the substrate satisfies a range of −0.13%≦Δω<0% or 0% <Δω≦+0.13%, the range having a center displaced from zero, and an X-ray rocking curve in a zero-order diffraction peak derived from the multiple-quantum well has a full width at half maximum of 30 seconds or less, wherein the substrate is an InP substrate and the multiple-quantum well is an InGaAS/GaAsSb type-II multiple-quantum well, wherein the multiple-quantum well includes 50 or more pairs of quantum wells, wherein the epitaxial layer structure is grown by metal-organic vapor phase epitaxy at a growth temperature of 400° C. or more and 500° C. or less.