Patent ID: 8995445
Filing Date: 2015-03-31
Classification: H04L

Abstract:
1. A system for resequencing per flow data packets received by at least one destination egress adapter comprising: a plurality of output registers with each register dynamically assigned to store received data packets from one of a plurality of flows, wherein each of the output registers further comprises: a packet sequence number and a packet buffer identifier for an in-process data packet; and a valid-bit latch to set an active/not active status that indicates if the in-process data packet is already output; means for allocating a temporary storage location in a packet buffer to each received data packet; means using predefined parameters, for pointing to an output register previously assigned to receive data packets from a corresponding flow; and means coupled to the allocating means and to the pointing means for determining if each received data packet is the next in sequence of the corresponding flow, by comparing the packet sequence number (PSN) of said each received data packet to the last packet sequence number (PSNc,PSNh) used by the pointed output register and scheduling means coupled to the determination means for selecting one of the in-process data packets to be output, wherein the scheduling means is coupled to each of the valid-bit latches to select one valid-bit latch having an active status.