Patent ID: 7629248
Filing Date: 2009-12-08
Classification: H01L

Abstract:
1. A method for forming a multi-layered metal line in a semiconductor device, comprising the steps of: forming an insulation layer on a semiconductor substrate with a lower metal line formed thereon; etching the insulation layer to form a damascene pattern exposing the lower metal line and defining an upper metal line forming region; recessing the exposed portion of the lower metal line; forming a glue layer on a surface of the recessed portion of the lower metal line; forming a first diffusion barrier on the glue layer to fill the recessed portion of the lower metal line; forming a second diffusion barrier on the first diffusion barrier and the glue layer; forming a third diffusion barrier on the second diffusion barrier and on a surface of the damascene pattern; and forming an upper metal line on the third diffusion barrier to fill the damascene pattern.