Patent ID: 8169061
Filing Date: 2012-05-01
Classification: H01L

Abstract:
1. A chip-stacked package structure with leadframe having bus bar, comprising: a leadframe, composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein said die pad is provided between said plurality of inner leads arranged in rows facing each other and vertically distant from said plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, said offset chip-stacked structure being set on said die pad and electrically connected to said plurality of inner leads arranged in rows facing each other; an encapsulant, covering said offset chip-stacked structure and said leadframe, said plurality of outer leads extending out of said encapsulant; and wherein said leadframe comprises at least a bus bar provided between said plurality of inner leads arranged in rows facing each other and said die pad, said bus bar being vertically distant from said plurality of inner leads and said die pad ; wherein said each chip comprising: a chip body having a bonding area located close to one side edge of the body, a plurality of first pads being formed inside the bonding area and a plurality of second pads being formed outside the bonding area; a first passivation layer provided on said body with a plurality of first openings formed on the first passivation layer to expose said plurality of first pads and said plurality of second pads; a redistribution layer formed with a plurality of third pads inside the bonding area being provided on said first passivation layer for establishing connection between said plurality of second pads and said third pads; and a second passivation layer provided to cover said redistribution layer with a plurality of second openings formed on said second passivation layer to expose said plurality of first pads and said plurality of third pads.