Patent ID: 6842811
Filing Date: 2005-01-11
Classification: G06F,Y02D

Abstract:
1. A method of providing a hierarchy of interrupts for a plurality of processor interrupt modes comprising the steps of: establishing a plurality of processor mode programs at different priority modes of operation including; (1) user mode programs at a lowest priority; (2) system mode programs; (3) non-maskable interrupt (NMI) mode programs; and (4) debug mode programs at a highest priority; and utilizing a hierarchy of: (1) general purpose interrupts (GPI) and system call interrupts (SYSCALL) at a user mode; (2) non-maskable interrupts at the user and a system mode; and (3) debug interrupts (DBI) at the user, the system and a non-maskable interrupt mode to automatically cause transitions between the modes of operation.