Patent ID: 6201735
Filing Date: 2001-03-13
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory comprising:a plurality of memory arrays, each including a plurality of memory cells disposed in a matrix having rows and columns; anda voltage generator,wherein each of said plurality of memory cells is a one-transistor type memory cell including a source region and a drain region disposed in a portion of a semiconductor substrate in a mutually spaced-apart relationship, a gate insulating film having a substantially uniform film thickness from the surface of said source region to the surface of said drain region, a floating gate electrode formed on said gate insulating film, and a control gate formed on said floating gate electrode through an intermediate insulating film,wherein drain regions of ones in said plurality of memory cells in an individual column are coupled to a data line associate with that column in each of said plurality of memory cell arrays,wherein control gates of ones in said plurality of memory cells in an individual row are coupled to a word line associated with that row in each of said plurality of memory cell arrays,wherein ones of said plurality of memory cells are programmed with data and are erased with data, by using a tunneling mechanism, by applying thereto a voltage generated from said voltage generator, andwherein the number of ones in said plurality of memory cells to be simultaneously programmed is equal to the number of ones in said plurality of memory cells to be simultaneously erased.