Patent ID: 6054884
Filing Date: 2000-04-25
Classification: H03K

Abstract:
A delay circuit having N outputs where N.gtoreq.2, comprising:N outputs each coupled to a common input through N-1 serially connected unit delay cells, where for each output there are P unit delay cells having a unit delay of t.sub.P0 and N-1-P unit delay cells having a unit delay of t.sub.P1, the N outputs being ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.P1 -t.sub.P0, wherein the difference t.sub.P1 -t.sub.P0 may be smaller than either t.sub.P1 or t.sub.P0 and P goes in succession from N-1 to 0 in unit steps wherein each value of P corresponds to only one of said N outputs.