Patent ID: 8074144
Filing Date: 2011-12-06
Classification: G06F,G11C

Abstract:
1. A semiconductor storage device comprising: a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections of the word lines and the bit lines; a plurality of data lines reading normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line; a plurality of parity data lines reading parity data from a second area in the memory cell array, the second area being different from the first area, the parity data being used for an error correction of the normal data stored in the memory cell; a first determination circuit that compares the normal data read from the data lines and their expectation values, respectively, and determines whether the data and the expectation values coincide, respectively; and a second determination circuit that compares the parity data read from the parity data lines and their expectation values, respectively, and determines whether the data and the expectation values coincide, respectively, the second determination circuit comprising a selection circuit that selectively outputs a part of determination results of the second determination circuit and shuts off a remaining one of the determination results.