Patent ID: 7897440
Filing Date: 2011-03-01
Classification: G11C,H01L

Abstract:
1. A method of fabricating a thyristor-based memory comprising: forming a plurality of semiconductor posts in upright positions as an array of rows and columns over a substrate, wherein the rows of the array are formed with a respective distance therebetween having a first magnitude in a range of at least equal to a diameter of the semiconductor posts to less than three times the diameter, and wherein the columns of the array are formed with a respective distance therebetween having a second magnitude up to the diameter; wherein the forming of the semiconductor posts includes forming at least one post thereof by: patterning mask material over the substrate to provide protected regions thereof by which to define the semiconductor posts; wherein the patterning comprises using at least one of phase shift photolithography and optical proximity correction to form the protected regions with a width greater along a lateral direction parallel to a row of the rows than that along a longitudinal direction at least substantially perpendicular to the row.