Patent ID: 6252803
Filing Date: 2001-06-26
Classification: G11C

Abstract:
A method of erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:(a) applying an erase pulse to the plurality of memory cells;(b) overerase verifying the plurality of memory cells to determine if there are overerased memory cells in the plurality of memory cells;(c) applying an overerase correction pulse to a bitline to which an overerased memory cell is attached;(d) repeating steps (b) and (c) until all of the plurality of memory cells verify as not being overerased;(e) erase verifying the plurality of memory cells to determine if there are undererased memory cells in the plurality of memory cells;(f) applying another erase pulse to the plurality of memory cells if there are undererased memory cells in the plurality of memory cells;(g) repeating steps (b) through (f) until all of the plurality of memory cells verify as not being undererased;(h) soft program verifying the plurality of memory cells to determine if there are memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value; and(i) applying a soft programming pulse to those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.