Patent ID: 6507065
Filing Date: 2003-01-14
Classification: H01L,Y10S

Abstract:
A memory structure, comprising:a semiconductor substrate; a contact plug; a storage node formed over the semiconductor substrate, the storage node comprising a layer of polysilicon on a surface of silicon-containing material, the layer of polysilicon comprising at least one of HSG polysilicon and CSG polysilicon, the silicon-containing material being in contact with said contact plug, and the silicon-containing material having an ion concentration that is in a range from about 1Ã—1015 ions per cm3 of silicon-containing material to about 1Ã—1022 ions per cm3 of silicon-containing material, wherein said ion concentration presents an ion concentration gradient in said silicon-containing material, said storage node comprising: a base in contact with said contact plug; and a free-standing wall extending from said base and having opposing nonplanar surfaces, wherein said free-standing wall has a shape that is partly determined by said ion concentration gradient; a dielectric layer upon said storage node; and an electrically conductive cell plate upon said dielectric layer.