Patent ID: 7030438
Filing Date: 2006-04-18
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a sense amplifier; a memory array having a plurality of DRAM memory cells, a plurality of word lines and a plurality of data lines; a plurality of first drivers coupled to a plurality of first word lines, the plurality of first word lines being included in said plurality of word lines; a plurality of second drivers coupled to a plurality of second word lines, the plurality of second word lines being included in said plurality of word lines; a first line coupled to the plurality of first drivers and arranged to supply a first potential to the plurality of first drivers; and a second line coupled to the plurality of second drivers and arranged to supply the first potential to the plurality of second drivers; wherein said plurality of first drivers are formed on a first side of a substantially rectangular area where said memory array is formed, wherein said plurality of second drivers are formed on a second side of said substantially rectangular area, wherein said plurality of word lines cross a pair of data lines, said pair of data lines being two of said plurality of data lines which are coupled to said sense amplifier, wherein first and second DRAM memory cells are located between said pair of data lines and coupled to said plurality of first word lines, the first and second DRAM memory cells being included in said plurality of DRAM memory cells, wherein said first DRAM memory cells are coupled to one of said pair of data lines, wherein said second DRAM memory cells are coupled to the other of said pair of data lines, and wherein each of the plurality of memory cells is coupled to a corresponding one of the plurality of data lines via an oval contact.