Patent ID: 7356666
Filing Date: 2008-04-08
Classification: G06F

Abstract:
1. An information processing system comprising: a first processor having a first local memory; a second processor having a second local memory; a third processor having a third local memory; a shared memory shared by the first to third processors, the shared memory and the first to third local memories being mapped in a real address space; means for mapping one of the second local memory and the third local memory in part of an effective address space of a first thread executed by the first processor, said one of the second local memory and the third local memory being the local memory of a corresponding one of the second processor and the third processor, which executes a second thread interacting with the first thread, the second thread holding thread context including contents of said one of the second local memory and the third local memory, the first thread accessing said one of the second local memory and the third local memory via said part of the effective address space of the first thread to interact with the second thread; and means for mapping the other of the second local memory and the third local memory in said part of the effective address space of the first thread instead of said one of the second local memory and the third local memory when a processor that executes the second thread is changed from said one of the second processor and the third processor to the other of the second processor and the third processor, the first thread accessing the other of the second local memory and the third local memory via said part of the effective address space of the first thread to interact with the second thread.