Patent ID: 8105962
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A method, comprising: forming a first stress-inducing dielectric layer above a P-channel transistor and an N-channel transistor; selectively removing a portion of said first stress-inducing layer from above said P-channel transistor; forming a second stress-inducing dielectric layer above said P-channel transistor and said N-channel transistor; selectively removing a portion of said second stress-inducing layer from above said N-channel transistor; forming a dielectric buffer layer above said first stress-inducing dielectric layer by a non-plasma assisted first deposition process prior to selectively removing said portion of said first stress-inducing layer from above said P-channel transistor; forming an etch control layer on said first stress inducing layer prior to forming said second stress inducing layer, and wherein selectively removing said portion of the second stress inducing layer comprises performing an etch process and using said etch control layer to determine an endpoint of said etch process; and depositing an interlayer dielectric material by performing a plasma enhanced chemical vapor deposition process.