Patent ID: 8745433
Filing Date: 2014-06-03
Classification: B41J,G06K

Abstract:
1. A memory device comprising: a memory unit; a memory control unit that controls an access of the memory unit; a control unit that performs a communication process with a host device; a data terminal; a reset terminal; and a clock terminal, wherein the control unit outputs a response signal for reporting the connection of a memory device in an m-th clock cycle corresponding to ID information of the memory device among a first clock cycle and an n-th clock cycle of clocks input to the clock terminal, to the host device through the data terminal, wherein m is at least an integer of 1≦m≦n and n is an integer of 2 or more; wherein the control unit includes a mode determining unit that determines whether an operation mode is a normal communication mode or a connection detection mode, and a response unit that issues an instruction to output the response signal, and wherein when the mode determining unit determines that the operation mode is the connection detection mode, the response unit issues the instruction to output the response signal in the m-th clock cycle.