Patent ID: 7117469
Filing Date: 2006-10-03
Classification: G06F

Abstract:
1. A method of generating a padring layout design for a chip design, comprising: (a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design; (b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, each slot describing placement of at least one of a pad metal, an I/O cell, and a standard cell within the one or more areas; (c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone; (d) placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with the I/O cell; and (e) performing said step d) using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.