Patent ID: 6825877
Filing Date: 2004-11-30
Classification: H04N

Abstract:
A time delay integration circuit for acquiring a number n of samples per dwell, comprising:a plurality of first capacitors; a plurality of imaging sensor unit cell inputs controllably coupled respectively to the first capacitors; a plurality of groups of n second capacitors; a plurality n of charge transfer paths comprising a plurality of transfer gates coupled in series through a plurality of path segments, the path segments of the charge transfer paths being coupled in succession to, alternately, one of the first capacitors and to respective second capacitors in one of the groups of second capacitors; a first phase clock node and a second phase clock node, wherein each of the first capacitors is coupled to the second phase clock node and each of the second capacitors is coupled the first phase clock node; and a plurality n of path control signal nodes, a first transfer control signal node, and a second transfer control signal node, wherein the transfer gates of each of the charge transfer paths are coupled to a respective one of the path control signal nodes, and adjacent transfer gates in the charge transfer paths are respectively coupled to the first transfer control signal node and to the second transfer control signal node.