Patent ID: 8790988
Filing Date: 2014-07-29
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a device isolation pattern in regions of a substrate corresponding to a first region and a passive element region of the substrate, wherein the device isolation pattern delimits an active region of the substrate within the first region; forming a recess in an upper surface of the device isolation pattern in the passive element region to such a depth that a bottom surface of the recess is located below a plane coincident with an upper surface of the active region; forming a contiguous dummy layer that extends on the active region and on the bottom surface of the recess of the device isolation pattern; forming both a dummy pattern on the active region and a passive circuit element on the bottom surface of the recess, wherein the forming of both the dummy pattern and the passive circuit element comprises patterning the dummy layer to leave portions thereof the active region and on the passive element region, respectively; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer has a planar upper surface substantially coplanar with the upper surface of the dummy pattern and which is disposed above the passive circuit element in the passive element region; removing the dummy pattern to form an opening through the interlayer dielectric layer that exposes part of the active region while the planar upper surface of the interlayer dielectric layer remains disposed above the passive circuit element in the passive element region; and forming a gate electrode in the opening.