Patent ID: 7315596
Filing Date: 2008-01-01
Classification: H03L,H04L

Abstract:
1. A clock recovery device comprising: a data rate input; an input data sampler that obtains samples of a serial data stream; an early/late voting logic that identifies early and late operation for a set of bit times of the serial data stream from the obtained samples; a finite state machine operable to receive the data rate input for bandwidth control of the finite state machine and the early and late operation indication, and select two clock phases from identified operations of the voting logic and generates interpolator control signals to selectively mix these two clock phases; a phase interpolator operable to select a clock phase output that is generated from the two selected clock phases received from a clock input, wherein the phase interpolator selects the clock phase output based on the interpolator control signals from the finite state machine; and a programmable divider that divides the clock phase output of the phase interpolator based on the received data rate to program the device to operate at one of a plurality of clock and data rates, bandwidths, or tracking capabilities.