Patent ID: 8145844
Filing Date: 2012-03-27
Classification: G06F

Abstract:
1. A memory controller comprising: a write data cache having a plurality of write cache lines respectively storing write data to be written to a memory; a read data cache separate from said write data cache and having a plurality of read cache lines respectively storing read data read from said memory; and coherency circuitry coupled to said write data cache and said read data cache and responsive to access requests to said memory to manage coherency between said write data, said read data and data stored within said memory, wherein said coherency circuitry is responsive to an ordering in time of a plurality of write access requests corresponding to respective write cache lines and a received read access request for read-target data to control return of said read-target data to include corresponding portions of write data stored within said write data cache and temporally preceding said read access request and not to include any corresponding portions of write data stored within said write data cache and temporally succeeding said read access request, and to control return of any other portions of said read-target data from one or more of said read data cache and said memory.