Patent ID: 7184333
Filing Date: 2007-02-27
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a plurality of real memory cells arranged in a matrix; a plurality of real signal lines connected respectively to a plurality of real memory cell rows each of which is formed of the real memory cells arranged in one direction; a first dummy signal line wired along said real signal lines on an outside of a region in which said real memory cells are arranged; first dummy memory cells connected to said first dummy signal line, having a same shape and characteristic as those of said real memory cells, being adjacent to said real memory cells, and to which a predetermined logical level is writable during a test mode; a plurality of second real signal lines each connected to a memory cell row configured of real memory cells and the first dummy memory cell aligned in a direction orthogonal to said one direction: a voltage setting circuit setting said first dummy signal line to a first voltage to keep said first dummy memory cells in a non-written state during a normal operation mode, and setting said first dummy signal line to a second voltage to write test data onto said first dummy memory cells during the test mode; and decoders selecting said first real signal lines and said second real signal lines, respectively, to access to said real memory cells and said first dummy memory cells.