Patent ID: 8380779
Filing Date: 2013-02-19
Classification: G06F

Abstract:
1. A circuit comprising: an input to receive a first operand, the first operand including a first plurality of bits; an input to receive a second operand, the second operand including a second plurality of bits; a first circuit for providing a length indication; and a logic circuit for providing an indication of a match between a logical sum of the first operand and the second operand with a set of bits of a third operand, wherein a length of the set of bits is determined by the length indication, wherein the logic circuit generates the indication of the match by performing a plurality of bit logic operations, wherein each of the plurality of bit logic operations includes a logic operation on a bit of the first operand of a corresponding bit location, a bit of a second operand of the corresponding bit location, and a bit of the third operand of the corresponding bit location to generate a result and comparing the result with a carry indication generated from a logic operation on bits including bits of an immediately less significant bit location from the corresponding bit location, wherein each of the bit logic operations of the plurality of bit logic operations is performed for a different corresponding bit location of a plurality of bit locations, and wherein each of the plurality of bit logic operations performed by the logic circuit generates a bit result of a plurality of bit results, the logic circuit masks the plurality of bit results as per the length indication.