Patent ID: 6215839
Filing Date: 2001-04-10
Classification: H03K

Abstract:
A low jitter fractional divider with low circuit speed constraint, comprising:a divider for dividing the frequency of an input first clock signal by an integer number c to obtain a second clock signal;a fractional divider for dividing said frequency of said second clock signal by a fraction number b/a to obtain an output voltage signal;a compensation circuit for receiving said output voltage signal to generate an output clock signal with relatively low jitter, said compensation circuit comprising:an adjust buffer for generating an adjust signal based on said output voltage signal and a feedback of said output clock signal, wherein said adjust buffer has a value which is decreased when said output voltage signal asserts a pulse until reaching a predetermined minimum value, and which is increased when said output clock signal asserts a pulse until reaching a predetermined maximum value; anda down-counter driven by said first clock signal to perform a counting operation for generating said output clock signal, wherein said down-counter is loaded with a count value determined by said c, a, and b, based on said adjust signal and the feedback of said output clock signal when a zero value is reached in said down-counter, thereby adjusting said output clock signal to reduce jitter.