Patent ID: 6597624
Filing Date: 2003-07-22
Classification: G11C

Abstract:
A semiconductor memory device of a hierarchical word line structure having main word lines and sub word lines, a plurality of sub word lines being arranged for the main word line, comprising:a decoding circuit for generating a sub decode first signal for specifying one of the sub word lines arranged in correspondence to the main word line in accordance with an address signal; a first driving circuit receiving a first voltage as an operation power supply voltage and generating a first sub decode signal in accordance with said sub decode first signal; a second driving circuit receiving a second voltage as an operation power supply voltage and generating an internal sub decode signal in accordance with said sub decode first signal; and a gate circuit for receiving said second voltage as an operation power supply voltage and generating a second sub decode signal complementary to said first sub decode signal in accordance with output signals of the first and second driving circuits, one of said plurality of sub word lines arranged corresponding to the main word line being designated in accordance with the first and second sub decode signals.