Patent ID: 6037887
Filing Date: 2000-03-14
Classification: H03M

Abstract:
A programmable gain delta sigma analog-to-digital converter, comprising in combination:(a) first and second analog input terminals receiving a differential analog input voltage therebetween;(b) first and second charge summing conductors;(c) a first integrator including an amplifier and a first integrating capacitor coupled between a first input of the amplifier and a first output of the amplifier and a second integrating capacitor coupled between a second input of the amplifier and a second output of the amplifier;(d) a first capacitive switching circuit including first and second input sampling capacitors, first sampling switch circuitry coupled to charge the first and second input sampling capacitors according to voltages on the first and second analog input terminals, and first transfer switch circuitry coupled to the first and second input sampling capacitors and the first and second charge summing conductors to transfer charge between the first input sampling capacitor and the first integrating capacitor and to transfer charge between the second sampling capacitor and the second integrating capacitor;(e) a comparator having first and second inputs coupled to the first and second outputs, respectively, of the amplifier, the comparator also having an output;(f) a digital filter coupled to receive a stream of digital pulses produced by the comparator and adapted to produce a digital number that precisely represents the differential analog input voltage in response to the stream of digital pulses;(g) a second capacitive switching circuit including a plurality of substantially equal reference sampling capacitors, second sampling switch circuitry selectively coupling a feedback reference voltage to the reference sampling capacitors, respectively, to selectively charge them, and second transfer switch circuitry selectively coupling the reference sampling capacitors of the second capacitive switching circuits, respectively, to transfer charge between selectively coupled reference sampling capacitors of the second capacitive switching circuit and the first integrating capacitor;(h) a third capacitive switching circuit including a plurality of reference sampling capacitors, third sampling switch circuitry selectively coupling the feedback reference voltage to the reference sampling capacitors, respectively, of the third capacitive switching circuit to selectively charge them, and third transfer switch circuitry selectively coupling the reference sampling capacitors, respectively, of the third capacitive switching circuit to transfer charge between selectively coupled reference sampling capacitors of the third capacitive switching circuit and the second integrating capacitor; and(i) programmable gain control circuitry responsive to a gain signal coupled to the output of the comparator and adapted to cause the first and second capacitive switching circuits to sample the differential analog input voltage and the feedback reference voltage, respectively, at the same rate and selectively couple the reference sampling capacitors of the first and second capacitive switching circuits to the first and second integrating capacitors and to the feedback reference voltage to effectuate transfer of sampled charge between the first and second sampling capacitors and the first and second integrating capacitors so that the amount of sampled feedback reference charge in each transfer relative to the amount of sampled input charge in each transfer is inversely proportional to a selected gain represented by the gain signal.