Patent ID: 6639298
Filing Date: 2003-10-28
Classification: H01L

Abstract:
An integrated circuit inductor structure comprising:a semiconductor substrate having a plurality of insulating layers and a plurality of metallization layers therebetween; a plurality of first conductive strips disposed in a first metallization layer of said semiconductor substrate; a first stack of conductive vias in electrical connection with a first end of each one of the plurality of first conductive strips; a second stack of conductive vias in electrical connection with a second end of each one of the plurality of first conductive strips; and a plurality of second conductive strips disposed in a second metallization layer of said semiconductor substrate, wherein one of the plurality of second conductive strips spans and interconnects two consecutive first conductive strips through the first and the second stack of conductive vias, and wherein each one of the plurality of second conductive strips has a first end in electrical connection with an upper surface of the first stack of conductive vias and a second end in electrical connection with an upper surface of the second stack of conductive vias for interconnecting the two consecutive first conductive strips, wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening metallization layers therebetween.