Patent ID: 6667507
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A semiconductor memory device comprising:a semiconductor substrate; an element isolation region provided in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region; a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region; a second gate electrode provided on the first gate electrode with a first insulation film interposed therebetween, the second gate electrode having a first portion provided on the first gate electrode with the first insulation film interposed therebetween and a second portion extending on the element isolating insulation film, the second portion having a thickness different from that of the first portion; and a resistance element provided on the element isolation region, the resistance element and the second gate electrode being formed of a same material, and the resistance element and the second portion of the second gate electrode having a substantially a same thickness, the resistance element not extending on the element region.