Patent ID: 6482703
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method of fabricating an HV-I/O ESD MOS device, comprising the steps of:a) providing a structure having a first device region, a second device region and an HV-I/O ESD MOS device region; b) forming: i) a first device gate oxide layer within the first device region; ii) a second device gate oxide layer within the I/O HV device region; and iii) an HV-I/O ESD MOS device gate oxide layer within the HV-I/O ESD MOS device region; the first device gate oxide layer being thinner than the I/O HV device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer;c) forming: i) a first device gate upon the first device gate oxide layer; ii) a second device gate upon the I/O HV device gate oxide layer; and iii) an HV-I/O ESD MOS device gate upon the HV-I/O ESD MOS device gate oxide layer; the first device gate and the first device gate oxide layer having exposed side walls, the I/O HV device gate and the I/O HV device gate oxide layer having exposed side walls, and the HV-I/O ESD MOS device gate and the HV-I/O ESD MOS device gate oxide layer having exposed side walls;d) forming an LV-LDD mask over the I/O HV device gate and the structure within the I/O HV device region; e) performing an LV-LDD implant into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants; f) removing the LV-LDD mask; g) forming an HV-LDD mask over the first device gate and the structure within the first device region; h) performing an HV-LDD implant into the structure adjacent the I/O HV device gate and the HV-I/O ESD MOS device gate to form I/O HV device HV-LDD implants and HV-I/O ESD MOS device HV-LDD implants; i) removing the HV-LDD mask; j) forming spacers over the exposed side walls of: i) the first device gate and the first device gate oxide layer; ii) the I/O HV device gate and the I/O HV device gate oxide layer; and iii) the HV-I/O ESD MOS device gate and the HV-I/O ESD MOS device gate oxide layer; and k) forming source/drain regions within the structure adjacent: i) the first device sidewall spacers; ii) the I/O HV device sidewall spacers; and iii) the HV-I/O ESD MOS device sidewall spacers to complete fabrication of a first device, a second device and the HV-I/O ESD MOS device.