Patent ID: 7106651
Filing Date: 2006-09-12
Classification: G11C

Abstract:
1. A semiconductor memory device for reading and outputting a plurality of stored data pieces at a time, comprising: an auxiliary cell array concatenated with word lines of a memory cell array on the increasing side of bit lines of said memory cell array and for storing data at a first bit-line address on a next word-line address to a bit-line address located within a predetermined range of bits from said first bit-line address in said memory cell array; and an address driver for reading data out of said auxiliary cell array if said data pieces to be read at a time ranges from a last bit-line address of said memory cell array to a first bit-line address on the next word-line address therein or from a first bit-line address on the next word-line address to a last bit-line address on the previous word-line address in said memory cell array.