Patent ID: 6832276
Filing Date: 2004-12-14
Classification: G06F,Y02D

Abstract:
An information processing apparatus connected with a host computer through an ATA or ATAPI bus characterized in that said information processing apparatus comprises:a state control unit for controlling the operation of said information processing apparatus; an interface processing unit for carrying out interface processing on a signal exchanged with said host computer through said ATA or ATAPI bus; a clock generator for supplying a clock signal to said state control unit and said interface processing unit; a power supplying means for supplying power to said state control unit, said interface processing unit and said clock generator, wherein when no data is exchanged with said host computer through said ATA or ATAPI bus for at least a predetermined period of time, said state control unit drives said clock generator to supply a clock signal having a frequency lower than that of a normal clock signal only to said state control unit itself, and drives said power supplying means to supply power only to said state control unit itself and said clock generator in order to control the operation of said information processing apparatus to transit to a half halted state; and a reset signal supply means for passing on a received reset signal output by said host computer to make a request for termination of said half halted state to said state control unit directly from said ATA or ATAPI bus without passing through said interface processing unit when said state control unit controls the operation of said information processing apparatus to transit to said half halted state, wherein said state control unit restores the operation of said information processing apparatus from said half halted state to a normal state in accordance with said reset signal.