Patent ID: 8399925
Filing Date: 2013-03-19
Classification: H01L

Abstract:
1. A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) for terminating an active area semiconductor device being located along the top surface of a bulk semiconductor layer (BSL) having a proximal bulk semiconductor wall (PBSW) separating the TSMEC from the active area semiconductor device, the TSMEC comprises an oxide-filled large deep trench (OFLDT) being bounded by the PBSW and a distal bulk semiconductor wall (DBSW) wherein the OFLDT further comprises: a large deep oxide trench of trench size (TCS) and trench depth (TCD) into the BSL; a plurality of embedded capacitive structures (EBCS) located inside the large deep oxide trench and sequentially placed between the PBSW and the DBSW for spatially spreading a device voltage there across; the plurality of EBCS are made up of a corresponding set of interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT; the central portion of each OXC further embeds a bulk semiconductor finger (BSF) emanating from the BSL beneath the OFLDT so as to form a plurality of 3-way interleaved EBCS with the BSL material, the OXC material and the EPSR material; the closest EPSR neighbor of the PBSW is electrically connected to a top electrode; the second closest EPSR neighbor of the PBSW is electrically connected to the PBSW; and each of the following EPSR neighbors is electrically connected to its second closest proximal BSF neighbor.