Patent ID: 7064366
Filing Date: 2006-06-20
Classification: G11C,H01L

Abstract:
1. A ferroelectric memory device comprising: an integrated circuit substrate; a bottom interlayer dielectric layer on the integrated circuit substrate; a plurality of ferroelectric capacitors arranged in a row and column relationship on the bottom interlayer dielectric layer; a top interlayer dielectric layer disposed on a surface of the integrated circuit substrate including the plurality of ferroelectric capacitors, the top interlayer dielectric layer including via holes disposed on and associated with ones of the ferroelectric capacitors; a plate electrode formed in the top interlayer dielectric layer, the plate electrode extending into respective ones of the via holes to contact top surfaces of at least two neighboring ones of the plurality of ferroelectric capacitors; and a hydrogen barrier layer pattern interposed between the ferroelectric capacitors and the top interlayer dielectric layer and extending along sidewalls of the ferroelectric capacitors and an edge portion of the top surfaces of the ferroelectric capacitors, the via holes of the top interlayer dielectric layer extending through the hydrogen barrier layer to expose the top surfaces of the ferroelectric capacitors.