Patent ID: 9197228
Filing Date: 2015-11-24
Classification: H03B,H03K,H03L

Abstract:
1. A circuit comprising: an oscillator configured to generate an oscillating signal (Fvco); a frequency divider communicatively coupled to the oscillator and configured to generate a divided signal (Fvco/N) by dividing a frequency of the oscillating signal by a denominator (N1); a comparator communicatively coupled to the oscillator and the frequency divider and configured to: obtain a first count of the divided signal within a predetermined time and a second count of a reference signal within the predetermined time; compare the first count with the second count, and generate a comparison result according to the first count and the second count; wherein the oscillator is further configured to adjust the frequency of the oscillating signal according to the comparison result; wherein the oscillator comprises a first inductor communicatively coupled to a first capacitor array, wherein the first capacitor array is configured to: wherein the first capacitor array comprises a plurality of individually switched capacitors, wherein a capacitance of a first capacitor is less than the sum of capacitances of all the other capacitors that are less than the first capacitor and the capacitance of a least significant bit of the first capacitor array.