Patent ID: 6791134
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a first transistor disposed on a memory cell region; a second transistor disposed on a peripheral circuit region; a first dielectric film disposed on said memory cell region and said peripheral circuit region; a second dielectric film different from said first dielectric film, disposed on said first dielectric film; a capacitor storage electrode which is connected to a region of said first transistor by a plug formed in a crown shape, wherein said capacitor storage electrode is formed in a concave portion through said first dielectric film and said second dielectric film; a capacitor dielectric film formed on an inner surface of said capacitor storage electrode and a part of an outer surface of said capacitor storage electrode and on a part of said first dielectric film, wherein said capacitor dielectric film formed on said first dielectric film is located higher than said capacitor dielectric film formed on a bottom of said crown shape of said capacitor storage electrode; and a capacitor plate electrode formed on said capacitor dielectric film.