Patent ID: 7544549
Filing Date: 2009-06-09
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device configured as a MOS field effect transistor provided with a source region and a drain region formed by activating, through anneal, a first dopant of other conduction type ion-implanted in a device forming area of one conduction type provided in a semiconductor layer formed over an insulator, and a body region corresponding to the device forming area between the source region and the drain region, said method comprising the steps of, prior to the ion-implantation of the first dopant, (a) performing ion implantation of Ar in a boundary region between the source and drain regions to be formed, which corresponds to a region lying in a predeterminate area for forming the body region; and (b) performing high-temperature anneal for partly recovering crystal defects produced by the ion implantation of the Ar at a temperature higher than the anneal for activation of the first dopant, wherein the high-temperature anneal is carried out at a high-temperature anneal holding temperature that ranges from 1050° C. to 1100° C., and the anneal for activation of the first dopant is carried out at an anneal holding temperature that ranges from 950° C. to 975° C.