Patent ID: 8726113
Filing Date: 2014-05-13
Classification: G01R,G06F

Abstract:
1. A circuit, comprising: a memory; a ring generator, the ring generator being configured to generate and output ring generator output signals, the ring generator output signals being based at least in part on (a) one or more input values applied to the ring generator from the memory and (b) a previous state of the ring generator; a shadow register, the shadow register being configured to capture the ring generator output signals in response to a shadow register control signal and to generate shadow register output signals; a phase shifter, the phase shifter being configured to receive the shadow register output signals and to generate phase shifter output signals, the phase shifter output signals comprising phase shifted versions of the shadow register output signals; and one or more gates configured to receive one or more of the phase shifter output signals, the one or more gates being further configured to selectively mask test response values as they are loaded into a compactor based on the one or more of the phase shifter output signals.