Patent ID: 6319418
Filing Date: 2001-11-20
Classification: H05K

Abstract:
A method for creating interconnect wires in successive layers of Printed Circuit Boards, comprising the steps of:providing a first layer of a partially completed PCB circuit board;depositing a first layer of metal over the surface of said first layer of said partially completed PCB;patterning and etching said first layer of metal thereby forming a first interconnect pattern of said PCB;plating said first interconnect pattern thereby creating the first interconnect layer of metal of said PCB whereby hereafter said first interconnect layer is referred to as the preceding interconnect layer;providing a following layer of a partially completed PCB circuit board whereby said following layer of partially completed PCB board follows said preceding interconnect layer in the sequence of the creation of said PCB;depositing a following layer of metal over the surface of said following layer of said partially completed PCB;patterning and etching said following layer of metal thereby forming a following interconnect pattern on the surface of said following layer of said PCB;plating said following interconnect pattern on the surface of said following interconnect layer thereby creating a following interconnect layer of metal on the surface of said following layer of said PCB;repeating the process of creating additional layers of said partially completed PCB by repeating the above processing steps starting with said step of providing a following layer of a partially completed PCB circuit board and ending with said step of plating said interconnect pattern on the surface of said following layer said repetition to occur a number of times that equals the required layers to be contained within said PCB minus one thereby completing the creation of said PCB; andseparating said completed PCB into individual PCB units.