Patent ID: 7984209
Filing Date: 2011-07-19
Classification: G06F

Abstract:
1. A method of operating First-In-First-Out (FIFO) memory circuitry on an integrated circuit, the FIFO memory circuitry being used for interfacing data between a write clock rate that the data had when received by the integrated circuit and a read clock rate at which the data will be further processed by the integrated circuit, the method comprising: determining which of the write clock rate and the read clock rate is faster; if the read clock rate is faster, then shifting a baseline of the FIFO memory circuitry toward a full position of that circuitry; if the write clock rate is faster, then shifting a baseline of the FIFO memory circuitry toward an empty position of that circuitry; and proceeding to normal rate match operation such that only a capacity of the FIFO memory circuitry on one side of the baseline is provided for storing the data being interfaced.