Patent ID: 7489173
Filing Date: 2009-02-10
Classification: H03K,H03L

Abstract:
1. A method for providing a duty cycle adjusted signal, comprising: providing a first sample clock signal; providing a second sample clock signal; generating a first phase signal and a second phase signal responsive to the first sample clock signal, the first phase signal being out of phase with respect to the second phase signal; generating a combined signal, the combined signal having a duty cycle associated with the first phase signal and the second phase signal in combination; clocking a first counter to provide a first count, the first counter clocked with the second sample clock signal; clocking a second counter to provide a second count, the second counter clocked with the second sample clock signal; periodically activating and deactivating the first counter responsive to the combined signal to affect the first count; maintaining the second counter in an active state for counting; and dividing the first count from the first counter with the second count from the second counter to obtain the duty cycle associated with the combined signal.