Patent ID: 6111810
Filing Date: 2000-08-29
Classification: G11C

Abstract:
A circuit connection structure of at least a multi-bit pre-fetch address generator circuit to at least an access path of a synchronous memory device, said at least an access path including at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from said at least a command decoder,wherein said at least a multi-bit pre-fetch address generator circuit is connected to said at least a follower circuit element in parallel to said at least a command decoder, so that said at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of said command signal, whereby said at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of said command signal from said at least a command decoder to said at least a follower circuit element.