Patent ID: 7380182
Filing Date: 2008-05-27
Classification: G11C

Abstract:
1. An apparatus for testing an integrated circuit having a write circuit for outputting a data signal and an associated data sampling signal which have a chronological relationship with one another and a read circuit for receiving the data signal and the associated data sampling signal, the apparatus comprising: a setting circuit for setting a chronological offset between the data signal and the associated data sampling signal which are received by the read circuit, wherein the setting circuit is a component of the integrated circuit; an external test device for supplying an external standardization data signal and an external standardization data sampling signal to the integrated circuit, wherein the data signal and the associated data sampling signal are replaced by the external standardization data signal and an external standardization data sampling signal in a test mode; and a comparator device for comparing data read-in by the read circuit and a provided data from at least one of the data signal and external standardization signal, wherein a fault signal is generated by the comparator device when the read-in data differs from the provided data.