Patent ID: 6279099
Filing Date: 2001-08-21
Classification: G06T

Abstract:
A microprocessor comprising:an instruction fetch and dispatch unit;a plurality of execution units, includingan integer execution unit,a floating-point execution unit, wherein said floating point execution unit comprises first and second floating point execution units, each separately coupled to said instruction fetch and dispatch unit, and each containing at least one specialized graphics execution circuit, anda plurality of graphics execution circuits added to said floating-point execution unit;a first register file coupled to said integer unit; anda second register file coupled to said floating-point execution unit;wherein said first floating-point execution unit includes an ALU, and said second floating-point execution unit includes a multiplier; andwherein said specialized graphics circuit in said second floating-point execution unit further comprises a pixel distance computation circuit configured to calculate and accumulate the difference between multiple pairs of pixels, said pixel distance computation circuit and said multiplier being configured in parallel such that only one can receive a decoded instruction from said fetch and dispatch unit in a given clock cycle.