Patent ID: 6028806
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A semiconductor memory comprising:address circuitry configured to receive memory addresses and to output corresponding section signals, global isolation signals, and global phase signals;local isolation circuitry coupled to the address circuitry and configured to output local isolation signals in accordance with the section signals and the global isolation signals;circuitry coupled to the address circuitry and the local isolation circuitry and configured to output local phase signals in response to the global phase signals and the local isolation signals;a memory array having rows and columns;row accessing circuitry coupled to the address circuitry, the local phase signal outputting circuitry and the memory array the row accessing circuitry configured to activate rows in the array selected in accordance with the memory addresses and in response to the local phase signals; andcolumn accessing circuitry coupled to the address circuitry, the local isolation circuitry and the memory array, the column accessing circuitry configured to access columns in the array selected in accordance with the memory addresses and in response to the local isolation signals.