Patent ID: 6372616
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method of manufacturing an electrical interconnection of a semiconductor device, comprising:forming an interlayer dielectric layer on a semiconductor substrate; forming a contact hole in the interlayer dielectric layer; filling the contact hole with an organic material to thereby form an erosion protecting plug of the organic material within the contact hole; forming a photoresist pattern on the interlayer dielectric layer and which pattern exposes the erosion protecting plug and a portion of the interlayer dielectric layer extending linearly from an area directly adjacent the erosion protecting plug; while the organic material is present within the contact hole, etching the portion of the interlayer dielectric layer exposed by the photoresist pattern to form a recess which is contiguous with the contact hole, whereby the erosion protecting plug inhibits the etching of a portion of the interlayer dielectric layer which defines the edge of the contact hole; subsequently removing the erosion protecting plug and the photoresist pattern; and subsequently filling the recess and the contact hole with conductive material to form a conductive line.