Patent ID: 8526221
Filing Date: 2013-09-03
Classification: G11C

Abstract:
1. A semiconductor integrated circuit (IC), comprising: a first circuit area for operating at a low voltage level (LVL); and a second circuit area for operating at a high voltage level (HVL), said first and second circuit areas comprising two vertically stacked backend patterned metal layers that are separated from each other by an inter-metallic dielectric (IMD), said two metal layers and said IMD forming a combination and having corresponding physical dimensions for operating at said LVL, said first circuit area using a first portion of said combination for operating at said LVL and said second circuit area using a second portion of said combination for routing at said HVL, said two metal layers in said second portion being interconnected through said IMD by at least one via hole, for withstanding said HVL.