Patent ID: 8248281
Filing Date: 2012-08-21
Classification: H03M

Abstract:
1. A method for compensating a linearity error of a dual digital-to-analog converter, comprising: receiving a digital data signal, comprising a plurality of bits, the digital data signal indicating a voltage signal to be generated, said plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit; applying a high-bit-array to a first digital-to-analog converter, said high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal; using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the lowest bit of the digital data signal, wherein the manipulation of the at least a part of the low-bit-array comprises: