Patent ID: 7489189
Filing Date: 2009-02-10
Classification: H03F

Abstract:
1. A power amplifier circuit comprising a power transistor unit generating an output signal based on a predetermined pulse-width modulated signal, wherein the power transistor unit comprises: first through n-th pull-up transistors connected in parallel between a first power supply node and an output node and responding to first through n-th PMOS input signals, respectively, where “n” is an integer greater than 1; and first through n-th pull-down transistors connected in parallel between the output node and a second power supply node and responding to first through n-th NMOS input signals, respectively, the first through n-th PMOS input signals are based on the pulse-width modulated signal and have different delay times, respectively, and the first through n-th NMOS input signals are based on the pulse-width modulated signal and have different delay times, respectively; and a delay circuit unit sequentially driving the plurality of transistors with a predetermined time delay based on the pulse-width modulated signal.