Patent ID: 8196011
Filing Date: 2012-06-05
Classification: G06F

Abstract:
1. An error detection and correction circuit which encodes input data having an integral multiple of 8 bits and stores the encoded data in a storage, and decodes original information from a reproduction signal of the storage, comprising: means for dividing the input data into symbols in units of b bits where b is an integer of 5 to 7; first encoding means for adding an error detecting and correcting code of a symbol unit to the data divided into symbols; second encoding means for adding a number of check bits for detecting an error based on a difference between the data divided into symbols configured of a multiple of b bits and the input data having the integral multiple of 8 bits; means for recording the data added with the error detecting and correcting code in the storage; decoding means for performing error detection and correction in units of symbols to data of the reproduction signal read from the storage, by using the error detecting and correcting code; and checking means for checking presence of an error in the data corrected in the decoding means, by using the check bits.