Patent ID: 8658051
Filing Date: 2014-02-25
Classification: H01L

Abstract:
1. A method of improving lithography resolution on a semiconductor, consisting of the sequential steps of: (1) providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; (2) patterning the photoresist layer to form an opening with a dimension so as to partially reveal the first etching layer with an area covered by the photoresist layer, wherein the dimension is at least three times larger than that of the covered area; (3) implanting a first ion into the revealed first etching layer to form a first doped area; and (4) implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent of the second doped area, wherein all of the above-mentioned steps are performed at an initial photolithographic stage.