Patent ID: 8735885
Filing Date: 2014-05-27
Classification: G11C,H01L

Abstract:
1. A memory device comprising: an antifuse memory element comprising: a first driver circuit which writes a first data to the antifuse memory element being in a first state so that a potential of the first electrode is higher than a potential of the second electrode, whereby the antifuse memory element being in a second state is obtained, and a second driver circuit which writes a second data to the antifuse memory element being in the first state so that a potential of the second electrode is higher than a potential of the first electrode, whereby the antifuse memory element being in a third state is obtained, and wherein R wherein the antifuse memory element being in the first state is an initial state, wherein at least a part of the silicon layer of the antifuse memory element being in the second state is a silicide layer, and wherein the first electrode and the second electrode of the antifuse memory element being in the third state are shorted.