Patent ID: 7868425
Filing Date: 2011-01-11
Classification: H01L

Abstract:
1. A semiconductor device including an MISFET, comprising: (a) a silicon-germanium layer formed over a semiconductor substrate; (b) a strained silicon layer formed over the silicon-germanium layer; (c) a gate insulating film formed over the strained silicon layer; (d) a gate electrode formed over the gate insulating film; and (e) a source region and a drain region; wherein the strained silicon layer is thicker than a critical film thickness at which misfit dislocations occur and the misfit dislocations exist on an interface between the strained silicon layer and silicon-germanium layer, wherein the source region is formed in the strained silicon layer but not formed in the silicon-germanium layer, and the drain region is formed in both the strained silicon layer and the silicon-germanium layer so that said source region and said drain region are not symmetric.