Patent ID: 6885078
Filing Date: 2005-04-26
Classification: H01L,Y10S

Abstract:
1. An integrated circuit having a plurality of circuits formed on a common substrate that are isolated by isolation regions in said common substrate between said circuits, said integrated circuit made by the process of: masking predetermined locations of said common substrate that are aligned with said isolation regions with a material that is capable of masking high energy ions; irradiating said common substrate with said high energy ions such that said high energy ions have an energy level sufficient to implant said high energy ions in embedded regions of said common substrate that have a lower resistance than said common substrate and that are substantially aligned with unmasked portions of said common substrate that are substantially aligned with said circuits so that said isolation regions having a higher resistance than said common substrate are formed in said common substrate between said embedded regions and said embedded regions are buried in said common substrate so that currents injected into said common substrate by said circuits preferentially flow to a ground potential rather than through said isolation region.