Patent ID: 6396318
Filing Date: 2002-05-28
Classification: H03K

Abstract:
A clock frequency multiplier circuit for outputting a frequency-multiplied clock, comprising:a frequency dividing circuit for frequency-dividing a clock signal, generating and outputting a multiphase clock; a clock period sensing circuit to which the clock signal is input; a plurality of timing dividing circuits (interpolators) for outputting timing signals obtaining by dividing differences between input timings of the multiphase clock; and multiplexer circuits for multiplexing outputs of said plurality of timing dividing circuits (interpolators); wherein said clock period sensing circuit comprises: a plurality of parallel connected delay sensing circuits having slightly overlapping operating ranges and different centers of operation, wherein said clock signal is passed through said plurality of delay sensing circuits, and a period of the clock signal is sensed and a control signal is outputted which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.