Patent ID: 6436759
Filing Date: 2002-08-20
Classification: H01L,Y10S

Abstract:
A method for fabricating a metal oxide semiconductor (MOS) transistor of an embedded memory, the method comprising:providing a semiconductor wafer with both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer; forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer; performing a first ion implantation process on the polysilicon layer in the memory array area so as to transform the polysilicon layer in the memory array area into a doped polysilicon layer; etching the doped polysilicon layer to a predetermined thickness; forming a silicide layer, a protection layer, and a photoresist layer, respectively, on the surface of the semiconductor wafer; performing a photolithographic process so as to define a plurality of gate patterns in the photoresist layer; using the gate patterns in the photoresist layer as a hard mask to etch the protection layer, the silicide layer, the undoped polysilicon layer, the doped polysilicon layer, and the dielectric layer down to the surface underlying the dielectric layer; performing a second ion implantation process to form a lightly doped drain (LDD) of each MOS transistor; removing the photoresist layer; forming a silicon nitride layer on the surface of the semiconductor wafer to cover the surface of each gate; performing an etching process to remove portions of the silicon nitride layer so as to form a spacer on either side of each gate; and performing a third ion implantation process to form a source and a drain in the periphery circuit region.