Patent ID: 6448840
Filing Date: 2002-09-10
Classification: H01L,H03K

Abstract:
An adaptive bias generator comprising:a matched circuit having a clock input node, a clock output node, and a bias input node; a phase comparator having a first input node coupled to the clock output node of the matched circuit, a second input node coupled to the clock input node of the matched circuit, and an output node; a digital-to-analog converter responsive to an error value on the output node of the phase comparator, the digital-to-analog converter having an output node coupled to the bias input node of the matched circuit; a body bias generator coupled between the output node of the phase comparator and the digital-to-analog converter, the body bias generator being configured to map the error value to at least one bias value, wherein the digital-to-analog converter is responsive to the at least one bias value; and a memory configured to receive and to store the at least one bias value.