Patent ID: 8827165
Filing Date: 2014-09-09
Classification: G11C

Abstract:
1. An integrated circuit including a plurality of integrated circuit output pads, the integrated circuit output pads including an alarm integrated circuit output pad and a test mode integrated circuit output pad, comprising: a tamper detection circuit operable to generate a tamper alarm signal; and first circuitry coupled to receive the tamper alarm signal from the tamper detection circuit and operable, responsive to a test mode signal indicative of whether the integrated circuit is operating in a test mode, to selectively couple the tamper alarm signal to one of the plurality of integrated circuit output pads depending on a logic state of said test mode signal; wherein the selective coupling is operable, when the test mode signal has a first logic state indicating that the integrated circuit is not operating in test mode, to couple the received tamper alarm signal for output from the integrated circuit at the alarm integrated circuit output pad; and wherein the selective coupling is further operable, when the test mode signal has a second logic state indicates that the integrated circuit is operating in test mode, to couple the received tamper alarm signal for output from the integrated circuit at the test mode integrated circuit output pad.