Patent ID: 6191044
Filing Date: 2001-02-20
Classification: H01L

Abstract:
A method for manufacturing an MOS structure on a semiconductor substrate, comprising the steps of:forming a gate dielectric layer over the semiconductor substrate;forming a polysilicon layer over said gate dielectric layer;forming a first mask layer over said polysilicon layer;patterning and etching said first mask layer to form a first gate mask;anisotropically etching said polysilicon layer using said first gate mask to form a polysilicon gate, wherein said polysilicon gate includes a gate part and a sidewall part with a re-entrant profile;implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form a shallow extension junctions in the semiconductor substrate around said polysilicon gate, said implanting also performed through said sidewall part to form said shallow extension junction with a graded doping profile under said sidewall part; andremoving the gate dielectric layer except under said gate part of said polysilicon gate.