Patent ID: 6295563
Filing Date: 2001-09-25
Classification: H03L,H04J

Abstract:
A data transport system for regulating the transfer rate of incoming serial digital data and headers, received from a remote transmitter at an original clock rate, F.sub.o, to a FIFO register after removal of headers comprising:(a) means to load said incoming serial digital data without headers into a FIFO register at an incoming frequency rate of I.sub.f which was set to clock said incoming digital data and headers and wherein the frequency rate I.sub.f is the expanded rate of F.sub.o plus headers, said means to load including:(a1) means to strip said incoming serial digital data of its header-bytes and only permit said incoming digital data to be loaded into said FIFO register;(b) means to generate an output frequency data rate F.sub.r for said FIFO register which will continuously match the remotely transmitted original digital data clocking frequency rate F.sub.o so that said FIFO will maintain itself at a HALF-FULL status condition during normal operation.