Patent ID: 6462789
Filing Date: 2002-10-08
Classification: H04N

Abstract:
A video encoding circuit, comprising:a first input terminal for receiving a data signal; a second input terminal for receiving a clock signal that has a frequency corresponding to that of the data signal; a third input terminal coupled for receiving a reference clock signal that is used with the clock signal to generate a phase correction value for a video subcarrier signal supplied at an output terminal of the video encoding circuit; a detector circuit having a first input for receiving the clock signal, a second input for receiving the reference clock signal, and an output for supplying a data value that corresponds to a number of transitions of the reference clock signal between transitions of the clock signal; a generator having a first input coupled to an output of the detector circuit and providing a phase increment value based on the data value; and an accumulator having an input coupled for receiving the phase increment value and an output for providing a portion of the phase correction value.