Patent ID: 7935997
Filing Date: 2011-05-03
Classification: H01L

Abstract:
1. A memory device, comprising: a substrate having a memory cell array area and a peripheral circuitry area, wherein said memory cell array area comprises at least one polysilicon plug; an insulating layer provided over said substrate; at least one periphery contact defined in material layers over said substrate at said periphery circuitry area of said substrate, wherein said material layers is at least said insulating layer, said peripheral contact having a low resistance metal film layer provided over a portion of said insulating layer, along bottom and opposing sidewall edges of the periphery contact and forming metal silicide in contact with said substrate; and at least one memory cell array contact defined in said material layers over said substrate at said memory cell array area of said substrate, and having a metal mode film layer in direct physical contact with said at least one polysilicon plug the metal mode film layer being over and in direct contact with the low resistance metal film layer in the peripheral circuitry area; and a tungsten nitride layer provided on and in physical contact with said metal mode film layer such that said tungsten nitride layer inhibits formation of metal silicide on said at least one polysilicon plug.