Patent ID: 8629009
Filing Date: 2014-01-14
Classification: H01L

Abstract:
1. A method of forming a memory device comprising: providing a semiconductor substrate comprising a first portion and a second portion; forming a layered gate stack atop the semiconductor substrate, the layered gate stack comprising a high-k gate dielectric layer located atop the semiconductor substrate and a metal electrode layer atop the high-k gate dielectric layer; patterning the metal electrode layer stopping on the high-k gate dielectric layer to provide a first metal gate electrode present in the first portion of the semiconductor substrate, and a second metal gate electrode present in the second portion of the semiconductor substrate; forming at least one spacer on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric that is not beneath the first metal gate electrode, the second metal gate electrode, and the at least one spacer is exposed; and etching the remaining portion of the high-k gate dielectric layer to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode, wherein forming the at least one spacer comprises depositing a dielectric material, and anisotropically etching the dielectric material such that the width of the at least one spacer defines the portion of the first high-k gate dielectric that extends beyond the sidewall of the first metal gate electrode.