Patent ID: 8949538
Filing Date: 2015-02-03
Classification: G06F,G11C

Abstract:
1. An interface device comprising: a control circuit to control first exchanged information between a first bus and a second bus; a first sequencer to control second exchanged information between the second bus and the interface device; a second sequencer to control third exchanged information between memory channels and the interface device, wherein the interface device is coupled to a plurality of memory dice over the memory channels; and a cache control circuit to control fourth exchanged information between the first bus and the memory channels, wherein the control circuit is configured to control the interface device to determine if the first, second, and/or third exchanged information is located in the plurality of memory dice and/or a solid state disk and to select which of the plurality of memory dice or the solid state disk has a shortest latency to obtain the first, second, and/or third exchanged information.