Patent ID: 6589712
Filing Date: 2003-07-08
Classification: H01L,Y10S

Abstract:
A method for forming a passivation coating on a semiconductor wafer comprising:forming a first dielectric layer on said semiconductor wafer, said semiconductor wafer comprising a first area and a second area, said first area comprising a fuse, a semiconductor device, and an oxide layer, said oxide layer comprising a fuse window, said fuse being at the bottom of said fuse window, said second area comprising a bonding pad, said bonding pad comprising a metal layer; patterning and etching said first dielectric layer to expose said fuse window and said metal layer according to a first photomask; forming a second dielectric layer on said first dielectric layer, said fuse window, and said metal layer; forming a third dielectric layer made of polyimide on said second dielectric layer, wherein said polyimide is a negative photoresist having a thickness of about 5 microns; patterning said third dielectric layer by exposing said third dielectric layer through a second photomask using a photolithographic tool, to form a polyimide pattern exposing a portion of said second dielectric layer; and etching said exposed portion of said second dielectric layer to form a spacer on a side wall of said fuse and said fuse window, and to expose said metal layer, said second dielectric layer being etched by an anisotropic etching step using said polyimide pattern as a mask, said passivation coating on said semiconductor wafer being thus fabricated by etching said first dielectric layer, said second dielectric layer, and said third dielectric layer according to said first photomask and said second photomask.