Patent ID: 6797569
Filing Date: 2004-09-28
Classification: H01L

Abstract:
A method for forming a planarized field effect transistor (FET), the method comprising:defining an active semiconductor region upon a substrate, said active semiconductor region further comprising a pair of mesa regions therein; defining a source region within a top surface of one of said pair of mesa regions; defining a drain region within a top surface of the other of said pair of mesa regions; depositing a gate material between said pair of mesa regions; and planarizing said gate material, thereby forming a gate; wherein a top surface of said gate is substantially planar with said source and drain regions; and wherein said active semiconductor region is formed by: forming an insulating layer upon said substrate; forming a pair of window openings within said insulating layer; and growing an epitaxial layer over said insulating layer and said pair of window openings; wherein said pair of mesa regions are formed aver said pair of window openings.