Patent ID: 9123827
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit comprising: providing a gate electrode structure overlying a semiconductor substrate and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls; forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers; etching a portion of the planarizing carbon-based polymer layer to expose a top portion of the gate electrode structure and an upper portion of the sidewall spacers, the upper portion of the sidewall spacers being adjacent to sidewalls of an upper portion of the gate electrode structure; etching the upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure; etching a remaining portion of the planarizing carbon-based polymer layer so as to expose a remaining portion of the sidewall spacers; depositing a silicide-forming material over the top portion of the gate electrode structure, the sidewalls of the upper portion of the gate electrode structure, and the remaining portion of the sidewall spacers; and annealing the silicide-forming material to form a fully silicided gate electrode structure.