Patent ID: 7533317
Filing Date: 2009-05-12
Classification: G01R,H03M,H04J,H04L

Abstract:
1. A method of characterizing jitter sensitivity in a serializer/deserializer (SERDES) circuit having built-in self test (BIST) capabilities, the method comprising: providing a clock and data recovery (CDR) circuit coupled to said SERDES circuit that generates recovered clock and data from an incoming serial data stream; generating from a deserializer circuit connected to said CDR circuit corresponding data (Parallel Data Out) and clock (DES clock) in a parallel format; generating BIST patterns from a programmable pattern generator; receiving either the BIST patterns or input data (Parallel Data In) in a parallel format on a data input of a serializer circuit and generating a serial data stream from an external clock (SER clock) on a clock input of the serializer circuit; adding a perturbation delay to said serial data stream to produce a perturbed serial data stream; outputting either the serial data stream or the perturbed serial data stream in a loop back to the CDR circuit; and detecting a start-of-frame pattern using a dedicated signal (FD).