Patent ID: 7197099
Filing Date: 2007-03-27
Classification: H03L

Abstract:
1. A delay circuit comprising: a clock generator circuit; and a delay section; said clock generator circuit including a variable delay circuit delaying input clock and generating output clock to be supplied to an internal circuit, a phase comparator performing a phase comparison between said input clock and said output clock, and a delay control circuit outputting a control voltage for adjusting a delay amount of said variable delay circuit in response to a result of said phase comparison of said phase comparator; said delay section delaying an input signal for a prescribed period in accordance with said control voltage of said delay control circuit and for outputting the delayed input signal, said variable delay circuit and said delay section each including a plurality of delay units formed of identical circuit elements, a unit delay amount of each of said delay units changing in accordance with said control voltage, and said delay control circuit including a clamp circuit for fixing lower limit of said control voltage to a reference voltage, wherein said clamp circuit includes; a comparator for comparing said control voltage and said reference voltage; and a drive transistor for providing a current to an output node of said control voltage to drive said control voltage at least to said reference voltage in response to a comparison result signal from said comparator.