Patent ID: 6850092
Filing Date: 2005-02-01
Classification: G06F

Abstract:
1. A FIFO circuit which interfaces the transmission of data items between a sender subsystem operating under a first time domain and a receiver subsystem operating under a second time domain, wherein the first time domain and the second time domain are different and at least one of the time domains operates according to a clock signal, the FIFO circuit comprising: a put interface configured to operate according to the first time domain comprising a put data bus to transmit a data item from the sender subsystem and a put data request input to receive a put request from the sender subsystem to enqueue the data item from the put data bus; a get interface configured to operate according to the second time domain comprising a get data bus to transmit the data item to the receiver subsystem and a get data request input to receive a get request from the sender subsystem to dequeue the data item to the get data bus; and an array of cells, each cell comprising: