Patent ID: 6703298
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of fabricating a non-volatile memory transistor having two isolated floating gate regions, the method comprising:forming a gate dielectric layer over a semiconductor substrate; forming a floating gate layer over the gate dielectric layer; forming a disposable layer over the floating gate layer; patterning the disposable layer to form a disposable mask region; forming a first sidewall spacer and a second sidewall spacer adjacent to the disposable mask region; implanting source and drain regions in the semiconductor substrate, using the disposable mask region and the first and second sidewall spacers as an implant mask; then removing the disposable mask region; then removing portions of the floating gate layer that are not covered by the first and second sidewall spacers, thereby forming a first floating gate region under the first sidewall spacer, and a second floating gate region under the second sidewall spacer.