Patent ID: 8400207
Filing Date: 2013-03-19
Classification: G09G,H03K

Abstract:
1. A level shift circuit comprising: an input terminal supplied with an input signal that is to be level-shifted; an output terminal at which an output signal is outputted; a first power supply terminal supplied with a first voltage; a second power supply terminal supplied with a second voltage; first to third transistors connected in series between the first power supply terminal and the second power supply terminal; fourth and fifth transistors connected in series between the first power supply terminal and the second power supply terminal; and a first delay circuit having an input connected to a connection node of the fourth and fifth transistors to deliver a delayed signal having a phase reversed to a phase of a signal received at the input thereof; the connection node of the fourth and fifth transistors being connected to the output terminal, a control terminal of one of the second and third transistors and a control terminal of the first transistor being connected in common to an output of the first delay circuit, the input signal of an amplitude range between third and fourth voltages applied to the input terminal being supplied to a control terminal of the other of the second and third transistors, a connection node of the first transistor and the second transistor being connected to a control terminal of the fourth transistor, a complementary signal of the input signal being supplied to a control terminal of the fifth transistor, the first and fourth transistors being of a first conductivity type and the second, third, and fifth transistors being of a second conductivity type, the level shift circuit further comprising a first voltage holding circuit that controls to hold a voltage at a connection node, at which the connection node of the first and second transistors and the control terminal of the fourth transistor are connected together, to the first voltage, a high/low relationship of the second voltage with respect to the first voltage being equal to a high/low relationship of the fourth voltage with respect to the third voltage, and the input signal whose amplitude range is between the third and fourth voltages having a lower amplitude than the output signal whose amplitude range is between the first and second voltages.