Patent ID: 6163860
Filing Date: 2000-12-19
Classification: G11C

Abstract:
A semiconductor device having a plurality of primary circuit elements addressable based on an external address word, wherein some of the primary circuit elements can be defective, the semiconductor device comprising:a plurality of fuse banks for storing addresses of defective circuit elements in the plurality of primary circuit elements;at least one comparison circuit coupled to receive the external address word and the stored addresses of the plurality of fuse banks, the comparison circuit comparing the external address word to the stored addresses and outputting a match signal if the external address word and one of the stored addresses correlate;at least one switching circuit coupled between the comparison circuit and the plurality of fuse banks, the switching circuit selecting one of the plurality of fuse banks to couple to the comparison circuit based on the external address word;a plurality of redundant circuit elements, each of which corresponds to one of the fuse banks, the plurality of redundant circuit elements capable of substituting for defective circuit elements in the plurality of primary circuit elements; andcontrol and addressing circuitry coupled to the comparison circuit and the plurality of primary and redundant circuit elements, the control and addressing circuitry receiving the match signal and accessing a one of the redundant memory elements that corresponds to the one fuse bank selected by the switching circuit.