Patent ID: 9198293
Filing Date: 2015-11-24
Classification: H01L,H05K

Abstract:
1. A package substrate core configured to carry and connect with at least one semiconductor die, the package substrate core comprising: a plurality of dielectric layers to form a multilayer core; a conductive bottom pattern on a bottom surface of the multilayer core; a conductive top pattern on a top surface of the multilayer core to connect with the die; at least one elongated via, the via having a depth through each layer of the multilayer core, the via being elongated to have a length in each layer that is greater than its width in the respective layer so that it does not have a circular cross-section and is an electrical isolation shield through the multilayer core for other conductive vias, each elongated via containing a conductor and each elongated via connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias, wherein the at least one elongated via comprises four layers of vias, the isolation shield having a height and a width through the multilayer core when the layers are laminated together and a curve to form a semi-circle through the layers of the multilayer core.