Patent ID: 6629268
Filing Date: 2003-09-30
Classification: G06F

Abstract:
A processing system comprising:one or more processing units including a particular processing unit, said particular processing unit including instruction execution circuitry, an internal cache coupled to said instruction execution circuitry, and an internal bus coupled to said internal cache, wherein said internal cache stores information and supplies said information to said instruction execution circuitry for processing; a memory system employing a cache coherency protocol to manage coherency with said internal cache; a service processor for managing said processing system; a test port coupling said particular processing unit to said service processor; and an interface means, coupled to said test port and to said internal bus, for generating a transaction on said internal bus of said particular processing unit in response to said test port receiving a first command from said service processor, and further for returning a result of said transaction to said service processor, wherein said transaction specifies an address corresponding to a storage location within said internal cache, and wherein said internal cache, responsive to receiving said transaction via said internal bus, updates a coherency state indicator associated with said storage location and transmits a communication associated with said address to said memory system in accordance with said coherency protocol.