Patent ID: 6275440
Filing Date: 2001-08-14
Classification: G11C,H03K

Abstract:
A semiconductor memory comprising:a plurality of memory cells;a first circuit block, separate from said plurality of memory cells, including a plurality of MOSFETs;a second circuit block, separate from said plurality of memory cells, including a plurality of MOSFETS;a first circuit which reduces a subthreshold leakage current of said plurality of MOSFETs of said first circuit block; anda second circuit which reduces a subthreshold leakage current of said plurality of MOSFETs of said second circuit block,wherein said first circuit includes a first terminal connected to said first circuit block, a second terminal supplied with a first voltage and a first switch, constructed to reduce a subthreshold leakage current, coupled between said first terminal and said second terminal,wherein said second circuit includes a third terminal connected to said second circuit block, a fourth terminal supplied with said first voltage and a second switch, constructed to reduce a subthreshold leakage current, coupled between said third terminal and said fourth terminal,wherein said first switch is controlled by a first control signal, andwherein said second switch is controlled by a second control signal which is different from said first control signal.