Patent ID: 7321132
Filing Date: 2008-01-22
Classification: H01L

Abstract:
1. A multi-layer structure for use in the fabrication of integrated circuit devices, comprising: a buffer layer on a substrate; a channel layer on said buffer layer; a spacer layer on said channel layer; a first Schottky layer on said spacer layer; a second Schottky layer overlying said first Schottky layer; a third Schottky layer overlying said second Schottky layer; a contact layer overlying said third Schottky layer; said structure having defined therein: a first etch-stop intermediate said first Schottky layer and said second Schottky layer; a second etch-stop intermediate said second Schottky layer and said third Schottky layer; and a third etch-stop intermediate said contact layer and said third Schottky layer.