Patent ID: 6583646
Filing Date: 2003-06-24
Classification: H03K

Abstract:
A programmable logic integrated circuit comprising:a plurality of logic array blocks; a plurality of programmable interconnect lines, programmably coupled to the plurality of logic array blocks; and at least one high-voltage-tolerant interface circuit block, programmably coupled to at least one of the plurality of programmable interconnect lines, comprising: a first pull-up device coupled between a first supply voltage and an I/O pad; a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device; a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the pull-up device is coupled to the first control electrode of the first pull-up device; a first pull-down device coupled between the first control electrode of the first pull-up device and a third supply voltage; a second pull-down device coupled between the output pad and the third supply voltage; and a first pass device coupled between an input signal line and the second control electrode of the second pull-up device.