Patent ID: 6197627
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of fabricating a MOS device, comprising the steps of:forming a semiconductor layer patterned in a plurality of islands for forming an n-channel semiconductor device and a p-channel semiconductor device by forming a photosensitive resin on a surface of the semiconductor layer formed on an SOI substrate consisting of a supporting substrate, an insulation film, and the semiconductor layer, and by etching the semiconductor layer using the photosensitive resin as a mask for etching;forming a first boundary film on a surface of respective islands of the semiconductor layer by oxidizing the semiconductor layer in an oxidizing atmosphere;removing the first boundary film from the surface of the islands of the semiconductor layer for forming the n-channel semiconductor device by etching;forming a second boundary film, thinner in thickness than the first boundary film, on the surface of the island of the semiconductor layer for forming the n-channel semiconductor device by oxidizing the semiconductor layer in an oxidizing atmosphere;doping the island of the semiconductor layer for forming the n-channel semiconductor device with a p-type impurity for forming a channel doped layer;doping the island of the semiconductor layer for forming the p-channel semiconductor device with an n-type impurity for forming a channel doped layer;forming a gate oxide film in a channel forming region of the p-channel semiconductor device and the n-channel semiconductor device by etching the first boundary film and the second boundary film using the photosensitive resin as an etching mask such that the first boundary film and the second boundary film are left intact on a sidewall surface of respective islands of the semiconductor layer, facing boundary regions, and on a part of a top surface thereof, and by oxidizing the semiconductor layer in an oxidizing atmosphere;forming a gate electrode for the respective semiconductor devices by forming a gate electrode material on an entire surface of the SOI substrate including the surface of respective islands of the semiconductor layer, and by etching the gate electrode material;forming an n-type heavily doped layer in regions for forming a source and a drain of the island of the semiconductor layer for forming the n-channel semiconductor device using a photosensitive resin as a mask for ion implantation;forming a p-type heavily doped layer in regions for forming a source and a drain of the island of the semiconductor layer for forming the p-channel semiconductor device using a photosensitive resin as a mask for ion implantation;activating impurities contained in the n-type heavily doped layer and the p-type heavily doped layer, by applying thermal treatment;forming an interlayer dielectric film consisting mainly of a silicon dioxide film on the entire surface of the SOI substrate;forming a plurality of contact holes in the interlayer dielectric film by hot etching; andforming interconnections for connection with the gate electrode, the source, and the drain of the n-channel semiconductor device and the p-channel semiconductor device, respectively, through each of the contact holes.