Patent ID: 8525301
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A semiconductor device fabricated by a method that comprises acts of: depositing a set of extrinsic layers on a substrate; removing a portion of the extrinsic layers and substrate to create a well having an intrinsic portion and an extrinsic portion, where the intrinsic portion is configured for receiving a layered intrinsic semiconductor device, and wherein in removing the portion of the extrinsic layers and substrate to create the well, the well is created to have vertically, outwardly tapering walls; and forming a layered intrinsic semiconductor device in the intrinsic portion of the well, wherein the layered intrinsic semiconductor device includes a type of layer selected from a group comprising an intrinsic collector layer, an intrinsic base layer, and an intrinsic sub-collector layer, and wherein in forming the layered intrinsic semiconductor device, at least one of the intrinsic collector layer, intrinsic base layer, and intrinsic sub-collector layer is formed to having vertically, outwardly tapering walls, and where the extrinsic layers include a type of layer selected from a group comprising an extrinsic collector layer, an extrinsic base layer, and an extrinsic sub-collector layer, such that a type of layer of the intrinsic semiconductor device is connected to a same type of layer of the extrinsic layers, and wherein the intrinsic base layer has a thickness that is different than a thickness of the extrinsic base layer.