Patent ID: 7994005
Filing Date: 2011-08-09
Classification: H01L

Abstract:
1. A method for manufacturing a high-mobility vertical trenched DMOS comprising: a) forming an N-type epitaxial (N-epi layer on top of an N+ substrate; b) forming a trench mask on top of the N-epi layer c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench; d) filling the trench with a conductive material to form a gate; e) forming SiGe region proximate to the gate on a sidewall of the trench but not on a bottom of the trench or a surface of the N-epi laver, wherein the SiGe region is configured to increase a mobility of charge carriers in a channel region, wherein forming the SiGe region comprises: forming an oxide spacer on the trench sidewall; isotropically etching a portion of the N-epi layer at a bottom of the trench; selectively growing an N-type SiGe region on the portion of the N-epi layer that was isotropically etched; etching the oxide spacer and the trench mask; and forming a gate oxide layer on the N-type SiGe on the sidewall of the trench; and f) forming a P-body layer on the surface of the N-epi layer.