Patent ID: 6480059
Filing Date: 2002-11-12
Classification: G06F,H01L,H03L

Abstract:
An apparatus comprising:a first circuit and a different second circuit, each circuit comprising a plurality of transistor devices formed on a substrate; a first connection line between the plurality of transistor devices of the first circuit to carry a first signal; a second connection line between the plurality of transistor devices of the second circuit to carry a second signal synchronous with the first signal, wherein each of the first and second circuits comprises a plurality of transistor devices, at least one transistor device of each of the first and second circuits having a gate over a portion of an active area of the substrate, the gate having a gate width, Wg, measured across a width of the active area of a substrate, and at least a first leg and a second leg of a width, Wl, wherein Wl is equal to Wg, divided by the number of legs, n, wherein the distance between the first leg and the second leg is a multiple, m, of the target dimension of Wg, wherein m is determined to minimize a line proximity effect.