Patent ID: 6223328
Filing Date: 2001-04-24
Classification: G06F

Abstract:
A wire processing method for processing a wiring of clock nets connecting between two receivers on a clock distributing circuit of a clock synchronous circuit in which a clock is to be propagated from an external clock source to the two receivers along opposite routes of the wiring via a tapping point with a minimal delay difference, said method comprising the steps of:(a) dividing the wiring into three or more series segments by two or more dividing points in such a manner that each segment is substantially uniform in impedance per unit length along its entire length, the impedance per unit length of each segment being different from that of any adjacent segment;(b) obtaining a delay time of the clock from one dividing point at one end of each said segment to one receiver as a first delay time, a delay time of the clock from said one dividing point to the other receiver as a second delay time, a delay time of the clock from the other driving point at the other end of each said segment to said one receiver as a third delay time, and a delay time of the clock from said other dividing point to said other receiver an a fourth delay time;(c) comparing said first delay time with said second delay time to obtain a first delay difference and also comparing said third delay time with said fourth delay time to obtain a second delay difference, and determining, among said segments, one segment in which the sign of a resultant value of subtraction of said first delay difference from said second delay difference is inverted from positive to negative or vice versa, as an equal delay segment on which the tapping point is to be located; and(d) determining an equal delay branch point in said equal delay segment as the tapping point via which the external clock source is to be connected to the wiring.