Patent ID: 8389990
Filing Date: 2013-03-05
Classification: H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a substrate; first wires of a stripe shape which are formed on the substrate; a first interlayer insulating layer formed over the first wires; first memory cell holes formed in the first interlayer insulating layer on the first wires; first resistance variable layers which are connected to the first wires via the first memory cell holes, respectively; first non-ohmic elements formed on the first resistance variable layers, respectively; second wires of a stripe shape which are formed on the first interlayer insulating layer such that the second wires respectively cross the first wires to be perpendicular to the first wires; a second interlayer insulating layer formed over the second wires; a third interlayer insulating layer formed over the second interlayer insulating layer; second memory cell holes penetrating the second interlayer insulating layer and the third insulating layer on the second wires; second resistance variable layers connected to the second wires via the second memory holes, respectively; second non-ohmic elements formed on the second resistance variable layers, respectively; third wires of a stripe shape which are formed on the third interlayer insulating layer such that the third wires respectively cross the second wires so as to be perpendicular to the second wires; a fourth interlayer insulating layer formed over the third wires; and upper wires formed on the fourth interlayer insulating layer; wherein each of the second wires has a plurality of layers including at least a portion of the first non-ohmic element and has an electrically-conductive layer in an uppermost layer of the second wire and a semiconductor layer or an insulator layer which is a portion of the first non-ohmic element in a lowermost layer of the second wire, and each of the third wires has a plurality of layers including at least a portion of the second non-ohmic element and has an electrically-conductive layer in an uppermost layer of the third wire and a semiconductor layer or an insulator layer which is a portion of the second non-ohmic element in a lowermost layer of the third wire; wherein the uppermost layer of each of the second wires is connected to the upper wire via a stacked contact including a second contact penetrating the second interlayer insulating layer and the third contact penetrating the third interlayer insulating layer and the fourth interlayer insulating layer, the second contact and the third contact being stacked together; and wherein the uppermost layer of each of the third wires is connected to the upper wire via a fourth contact penetrating the fourth interlayer insulating layer.