Patent ID: 6432778
Filing Date: 2002-08-13
Classification: H01L,Y10S

Abstract:
A method of forming a system on chip (SOC) comprising read only memory (ROM) and nitride read only memory(NROM) established with nitride read only memory, the SOC comprising a substrate having a memory area and a periphery area, the memory area comprising a nitride read only memory area and a read only memory area, the read only memory area comprising a low threshold voltage (low Vt) device area and a high threshold voltage (high Vt) device area, the method comprising:forming a plurality of isolators on the surface of the substrate to isolate the periphery area, the nitride read only memory area and the read only memory area, and to define an active area of each device; forming an ONO (bottom oxide-nitride-top oxide) dielectric layer composed of a bottom oxide layer, a silicon nitride layer, and a top oxide layer, the ONO dielectric layer disposed on the surface of the substrate; forming a first photoresist layer on the ONO dielectric layer and performing a first photolithography process to define a plurality of bit lines; performing a first etching process utilizing the first photoresist layer as a mask to remove the ONO dielectric layer not covered by the first photoresist layer; performing a first ion implantation process to form a plurality of N-type dopant areas in the substrate and form each bit line in the memory area; removing the first photoresist layer; performing a second etching process to remove the ONO dielectric layer in the periphery area; performing a second ion implantation process to adjust a threshold voltage of a transistor in the periphery area; performing a third etching process to remove the ONO dielectric layer in the read only memory area; performing a thermal oxidation process to form a buried drain oxide layer atop each bit line, and to form a gate oxide layer for the low threshold voltage device, for the high threshold voltage device in the read only memory area, and for the periphery transistor in the periphery area; forming a polysilicon layer and a second photoresist layer to define a plurality of word lines in the memory area and a plurality of gates of periphery transistors in the periphery area by utilizing a second photolithography process; performing a fourth etching process to remove the polysilicon layer not covered by the second photoresist layer and to simultaneously form each word line in the memory area, the gate of each periphery transistor in the periphery area and at least one nitride read only memory in the nitride read only memory area, and to form a low threshold voltage (low Vth) device in the low threshold voltage device area and a high threshold voltage (high Vth) device in the high threshold voltage device area; performing a third ion implantation process to adjust a threshold voltage of the high threshold voltage device; and removing the second photoresist layer.