Patent ID: 7051264
Filing Date: 2006-05-23
Classification: G06F

Abstract:
1. A semiconductor memory device comprising: a memory array configured to store data values and corresponding error correction code values; a first register configured to store a first write data value and a corresponding first write address value during a first write access to the memory array; an error correction code (ECC) generator configured to receive the first write data value from the first register, and in response, generate a first ECC value during the first write access to the memory array, the ECC generator being configured to provide the first ECC value as long as the first write data value is stored in the first register; means for outputting the first write data value and the first ECC value during a read access if a read address value associated with the read access matches the first write address value stored in the first register; and means for writing the first write data value and the first ECC value to a location in the memory array associated with the first write address value during a second write access.