Patent ID: 7143303
Filing Date: 2006-11-28
Classification: G06F,G11C

Abstract:
1. A circuit for compensating for a skew between an output data signal and an external clock signal, the circuit comprising: a phase detector (PD) for detecting a phase difference between the output data signal and the external clock signal and for generating an up signal or a down signal depending on the detected phase difference; an up-down counter enabled by a calibration signal that directs a compensation of the skew, for generating an offset code in response to the up signal or the down signal; a delay locked loop (DLL) circuit for receiving the offset code in response to the calibration signal and for generating first and second clock signals having first and second phase differences, respectively, from the external clock signal; and an output driver (OD) for generating the output data signal in response to the first clock signal.