Patent ID: 6368912
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of fabricating a horizontal isolation structure between a vertical transistor and a deep trench capacitor, comprising:providing a substrate having a pad oxide layer and a silicon nitride layer in turn thereon and a deep trench therein, wherein the deep trench has a deep trench capacitor on the bottom and an upper sidewall portion of the deep trench is exposed; forming an insulating layer on the substrate and partially filling the deep trench, wherein the thickness of the insulating layer on the sidewall of the deep trench is thinner than that of the insulating layer on the deep trench capacitor and the substrate; removing the insulating layer on the sidewall of the deep trench to transform the insulating layer into a first insulating layer on the silicon nitride is layer and a second insulating layer on the deep trench capacitor; forming a protection layer on the second insulating layer; using wet etching to remove the silicon nitride layer and simultaneously peeling the first insulating layer; implanting ions into the substrate to form a doped region surrounding the deep trench; removing the pad oxide layer; removing the protection layer; forming a gate oxide layer on the exposed surface of the substrate; forming a conductive layer on the gate oxide layer and in the deep trench; forming a shallow trench isolation in the substrate, and the shallow trench isolation partially overlapping the deep trench; and patterning the conductive layer to form a gate over the deep trench.