Patent ID: 8957701
Filing Date: 2015-02-17
Classification: H03K

Abstract:
1. An integrated circuit comprising an array in which a plurality of unit cells each having a predetermined shape are arranged in a matrix, wherein: each unit cell includes a logic reconfiguration element, a memory element for determining a logic of the logic reconfiguration element, a plurality of input terminals connected to the logic reconfiguration element, and a plurality of output terminals connected to the logic reconfiguration element; in the unit cells of the matrix, the unit cells in each row is displaced by a predetermined pitch to constitute to the array; electrical connections between the unit cells constituting the array have the following structures: (1) an input terminal of one unit cell is electrically connected to an output terminal of a first adjacent unit cell that is arranged adjacent to the one unit cell in a column direction and that is displaced with respect to the one unit cell by the predetermined pitch in a row direction; (2) another input terminal of the one unit cell is electrically connected to an output terminal of a second adjacent unit cell that is arranged adjacent to the one unit cell in the row direction; and (3) the connection defined in said (1) and the connection defined in said (2) are applied to the unit cells of the array other than said one unit cell.