Patent ID: 7814487
Filing Date: 2010-10-12
Classification: G06F

Abstract:
1. A multithreaded processor device, comprising: a first program thread; a second program thread; wherein the second program thread is execution linked to the first program thread in a lock step manner; and a stall controller linked to the first program thread and the second program thread wherein the stall controller is operative to perform a no operation instruction on the first program thread during each clock cycle in which the second program thread experiences a stall event in order to keep the first program thread execution linked to the second program thread and is operative to perform a no operation instruction on the second program thread during each clock cycle in which the first program thread experiences a stall event in order to keep the second program thread execution linked to the first program thread; wherein the first program thread comprises a first portion of a program having a plurality of very long instruction words (VLIWs) and the second program thread comprises a second portion of the program having a plurality of VLIWs, and wherein the program having a plurality of VLIWs is divided to form the first and second portions of the program.