Patent ID: 8465657
Filing Date: 2013-06-18
Classification: B24B,H01L,Y10T

Abstract:
1. A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer, having a top surface; etching an opening extending through said release layer and into said dielectric layer such that, within said dielectric layer, said opening has a deep first portion and a shallow second portion above and wider than said deep first portion and further such that edges of said release layer at said opening extend laterally over said shallow second portion, said etching comprising isotropically etching said dielectric layer to form said shallow second portion; lining said opening with a liner; filling said opening with a conductor, said lining and said filling resulting in a conductive interconnect line in said shallow second portion and a conductive via in said deep first portion, said conductive interconnect line having lined corners adjacent said top surface of said dielectric layer; polishing said liner and said conductor off of said release layer; and removing said release layer using a process other than chemical mechanical processing such that any trace amounts of said liner and said conductor that remain on said release layer after said polishing are completely removed as said release layer is removed.