Patent ID: 6819726
Filing Date: 2004-11-16
Classification: H03L

Abstract:
A dynamic phase alignment circuit comprising:a delay circuit connected to a derived clock tree connected to a clock generator (CG), said delay circuit including a logic circuit capable of delaying clock signals; a detecting circuit portion connected to said delay circuit and to a reference clock tree (RCT), the RCT being connected to a reference clock generator (RCG), said detecting circuit portion being configured for detecting the phase difference between a first clock signal output from said delayed circuit and a second clock signal output from said reference clock tree, wherein the detection circuit is at least configured to have a plurality of logic gates, and wherein at least one logic gate of the plurality of logic gates is at least configured to receive feedback from an output of the detection circuit as a function of a signal that is enabled by a clock pulse received from a clock generator tree; and a correcting circuit portion connected to said detecting circuit portion and to said CG, and configured for correcting the phase of said first clock signal by incrementally realigning the phase of said first clock signal to the phase of said second clock signal until said alignment is achieved.