Patent ID: 6346847
Filing Date: 2002-02-12
Classification: G01R

Abstract:
An integrated circuit comprising:a plurality of pins including a first access pin and a second access pin; and a trimming circuit comprising a memory and a regulation circuit for modifying said memory, said regulation circuit comprising an error amplifier having a first input for receiving an internal voltage reference, and a second input connected to the second access pin for receiving an output voltage from a portion of the integrated circuit to be trimmed, said error amplifier for comparing the output voltage with the internal voltage reference, a comparator having a first input connected to an output of said error amplifier and to the first access pin, a first switch connected between the output of said error amplifier and the first input of said comparator, a second comparator having a first input connected to the second access pin, and an output connected to said first switch for control thereof, a second switch connected to the output of said error amplifier and to the first access pin, a serial interface connected to said second switch for receiving via the first access pin data for trimming the portion of the integrated circuit, and a control logic circuit connected to said serial interface for controlling the trimming based upon the received data.