Patent ID: 6812718
Filing Date: 2004-11-02
Classification: G01R

Abstract:
A system for connection to at least one integrated circuit device on a wafer, comprising:a system board having a bottom surface and a top surface, and a plurality of electrical conductors extending between said bottom surface and said top surface; a substrate having a probe surface and a connector surface, said probe surface having a plurality of spring probe contact tips for connection to said at least one integrated circuit device, and a plurality of electrical connections extending through said substrate between each of said plurality of said spring probe contact tips and said connector surface; a plurality of electrically conductive connections between each of said plurality of electrical connections on said connector surface of said substrate and each of said electrical conductors on said bottom surface of said system board; at least one interface module comprising a first planar region at a first end and a second planar region which extends from said first end to a second end opposite said first end, each of said at least one interface module comprising a plurality of electrically conductive pads on said first planar region, an interconnection link at said second end, and at least one electrical connection extending from at least one of said electrically conductive pads to said interconnection link; and means for holding each of said at least one interface module in relation to said system board, such that said plurality of electrically conductive pads on said first planar region contact at least one of said plurality of electrical conductors on said top surface of said system board, and wherein said second planar region of said interface module extends away from said system board.