Patent ID: 7158070
Filing Date: 2007-01-02
Classification: H03M

Abstract:
1. An analog-to-digital converter comprising: a successive-approximation register(SAR); a comparator having an output coupled to a first input of the successive-approximation register; a first switch coupled to a first input of the comparator and an analog-ground source; a second switch coupled to a second input of the comparator and the analog-ground source; a first digital-to-analog converter having a first input coupled to a first output of the successive-approximation register, and a second input coupled to a second output of the successive-approximation register; a second digital-to-analog converter having an output coupled to the first input of the comparator; a third digital-to-analog converter having a first input coupled to the second output of the successive-approximation register, and a second input coupled to a third output of the successive-approximation register; a third switch coupled to a first reference voltage source, a first output of the first digital-to-analog converter, and a third input of the third digital-to-analog converter; a fourth switch coupled to a second reference voltage source, a second output of the first digital-to-analog converter, and a fourth input of the third digital-to-analog converter; a fifth switch coupled to an output of the third digital-to-analog converter, and the second input of the comparator; and a sixth switch coupled to the second output of the first digital-to-analog converter, the second reference voltage source, an analog input source, and the fifth switch.