Patent ID: 6509852
Filing Date: 2003-01-21
Classification: H03M

Abstract:
An analog-to-digital converter configured with gain calibration to reduce gain errors, said analog-to-digital converter comprising:a modulator configured for receiving an analog input signal comprising a positive input signal and a negative input signal during an operation mode, and a calibration reference signal during a calibration mode, said modulator comprising: an input sampling circuit comprising a plurality of input sampling branches configured in a parallel arrangement to receive and sample said calibration reference signal, wherein each of said plurality of input sampling branches is configured to sample a whole charge of said calibration reference signal during said calibration mode; a modulator components section configured for generating and processing a series of sampled analog signals; a digital filter configured for receiving a series of sampled analog signals and converting said sampled analog samples into representative digital signals; and an error correction section configured for correcting any gain errors occurring during operation of said analog-to-digital converter and for providing a digital output signal, and wherein said series of sampled analog signals are averaged within said digital filter to facilitate the computation of a gain calibration coefficient.