Patent ID: 7592648
Filing Date: 2009-09-22
Classification: H01L

Abstract:
1. An integrated circuit arrangement comprising: a NPN transistor containing an n-doped emitter region, a p-doped base region and an n-doped collector region; a PNP transistor containing a p-doped emitter region, an n-doped base region and a p-doped collector region; and an insulating layer on semiconductor material, the insulating layer having a first cutout defining a space, the base region of the PNP transistor being arranged below the space defined by the first cutout; electrically conductive material of an emitter connection region of the PNP transistor is arranged in the space defined by the cutout; the electrically conductive material connected to the emitter region of the PNP transistor; the first cutout at least one of (1) delimiting the width of the electrical contact between the emitter connection region and the emitter region of the PNP transistor or (2) adjoining the emitter connection region; the electrically conductive material at least one of (1) overlapping the insulating layer or (2) adjoining the insulating layer outside the first cutout; and a second cutout defining a second space, and being formed within the insulating layer, the base region of the NPN transistor being located substantially within the second space defined by the second cutout.