Patent ID: 7599214
Filing Date: 2009-10-06
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, arranged in rows and columns, each memory cell including a pair of load transistor elements of a second conductivity type formed in a first substrate region of a first conductivity type, each load transistor having a first conduction node coupled to a power supply node to which a first power supply voltage is supplied through a first power supply line, and drive transistor elements of the first conductivity type formed in respective second substrate regions of the second conductivity type arranged on opposite sides of the first substrate region of the first conductivity type, the drive transistors being connected so as to form a flip-flop with the load transistor elements and having first conduction nodes connected together to receive a second power supply voltage; access transistor elements of the first conductivity type formed in respective second substrate regions of the second conductivity type arranged on opposite sides of the first substrate region of the first conductivity type, second power supply lines provided to respective memory cell columns for supplying the second power supply voltage to the drive transistor elements in the plurality of memory cells, each second power supply line continuously extending in a column direction of the memory cell array, and crossing over the first substrate region of each memory cell in a corresponding memory cell column to connect together the first conduction nodes of the drive transistor elements; a plurality of word lines, provided corresponding to the respective memory cell rows, each connecting to a gate electrode of the access transistor on a corresponding row; and a plurality of bit lines, provided corresponding to the respective memory cell columns, each connecting to a second conduction node of the access transistor on a corresponding column, wherein said second power supply lines provided to the respective memory cell columns are isolated from each other.