Patent ID: 6476749
Filing Date: 2002-11-05
Classification: H03M

Abstract:
An analog-to-digital converter for converting an analog input signal (u(t)) having a frequency up to a predetermined maximum frequency (Fmax) to a digital output signal (x(n)) having a predetermined output sampling rate (Fs) equal to at least double the maximum frequency (Fmax), the analog-to-digital converter comprising:(i) a plurality of analog narrowband filters (F0-FMâˆ’1; FL,FH,FP) for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X0-XMâˆ’1; XL,XH,XP), each narrowband filter having a passband, the sum of the gains of the narrowband filters at any frequency within an operating frequency band of the plurality of narrowband filters being substantially unity; (ii) a corresponding plurality of sample-and-hold devices (SH0-SHMâˆ’1; SHL,SHH,SHP) clocked by a plurality of clock signals (&phgr;0-&phgr;Mâˆ’1), respectively, each of the plurality of clock signals having a frequency at least double the bandwidth of the corresponding narrowband filter; and (iii) a plurality of quantizers (Q0-QMâˆ’1; QL,QH,QP) each connected to a respective one of the sample-and-hold devices (SH0-SHMâˆ’1; SHL,SHH,SHP) and operable to provide a digitized value of each sample held by the corresponding sample-and-hold device; (iv) sampling and summing means (12,R0-RMâˆ’1; 121,122,14; 12,141,142; RL,RH,RP) for sampling and summing the outputs of the quantizers to produce said digital output signal (x(n)), the sampling being carried out sequentially at the predetermined sampling rate (Fs) in response to an output clock signal (CLK), the frequencies and phase-relationships of the plurality of clock signals (&phgr;0-&phgr;Mâˆ’1) being such that each sample point of the output clock signal coincides with a sample point of one of the plurality of clock signals.