Patent ID: 6650148
Filing Date: 2003-11-18
Classification: G11C

Abstract:
A sense amplifier circuit for sensing data fed to a data input terminal thereof and operating on the data according to a pre-charge signal, a latching signal and a sense enable signal, the sense amplifier circuit comprising:a first transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal is electrically coupled to a voltage source and the gate terminal is electrically connected to a pre-charge signal terminal; a second transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the second conductive terminal of the second transistor is electrically coupled to the data input terminal, with a signal from the data input terminal and the sense enable signal being processed in a NOR logic operation producing an output to apply to the gate terminal of the second transistor, and the first conductive terminal of the second transistor is electrically coupled to the second conductive terminal of the first transistor; a third transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the third transistor is electrically coupled to the voltage source, and the second conductive terminal of the third transistor is electrically connected to the gate terminal of the third transistor; a fourth transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the fourth transistor is electrically connected to the second conductive terminal of the third transistor, and the gate terminal of the fourth transistor is electrically coupled to the pre-charge signal terminal; a fifth transistor having a first conductive terminal, a second conductive terminal and a gate terminal, wherein the first conductive terminal of the fifth transistor is electrically coupled to the second conductive terminal of the fourth transistor, the second conductive terminal of the fifth transistor is electrically coupled to the data input terminal and the output from a NOR gate is applied to the gate terminal of the fifth transistor; and a latching circuit having an input terminal and an output terminal, wherein the input terminal is electrically coupled to the second conductive terminal of the fourth transistor for receiving a first output value and outputting a corresponding second output value within a preset period.