Patent ID: 8503186
Filing Date: 2013-08-06
Classification: H01L

Abstract:
1. A system-in package comprising: a carrier; a first chip over said carrier, wherein said first chip comprises a first semiconductor substrate having a thickness between 1 and 50 micrometers, a first metal layer under a bottom surface of said first semiconductor substrate, and a dielectric layer under said bottom surface of said first semiconductor substrate and over said first metal layer; a second chip over said carrier, wherein said second chip comprises a second semiconductor substrate, wherein said second semiconductor substrate has a top surface substantially coplanar with a top surface of said first semiconductor substrate, wherein said second chip is separated from said first chip; a gap filling material disposed in a gap between said first chip and said second chip; a first metal plug in said first chip, wherein said first metal plug passes through said first semiconductor substrate and said dielectric layer and contacts said first metal layer; a first insulating material enclosing said first metal plug, wherein said first insulating material is enclosed by said first semiconductor substrate; a first dielectric structure on said top surface of said first semiconductor substrate, on said top surface of said second semiconductor substrate, and on said gap filling material; a first metal interconnect in said first dielectric structure and over said first chip, wherein said first metal interconnect is connected to said first metal plug; a third chip over said first dielectric structure and over said first metal interconnect, wherein said third chip comprises a third semiconductor substrate having a thickness between 1 and 50 micrometers; a second metal plug in said third chip, wherein said second metal plug passes through said third chip and contacts said first metal interconnect; a second insulating material enclosing said second metal plug, wherein said second insulating material is enclosed by said third semiconductor substrate; a second dielectric structure on a top surface of said third semiconductor substrate; and a second metal interconnect in said second dielectric structure and over said third chip, wherein said second metal interconnect is connected to said second metal plug.