Patent ID: 6675284
Filing Date: 2004-01-06
Classification: G06F

Abstract:
An integrated circuit comprising:a) a serial data input pin and a serial data output pin; b) on-chip functional circuitry comprising at least two processing cores, each processing core associated with a respective communication channel; c) a data adaptor that is in communication with the processing cores by the respective communication channels and is connectable to the input and output pins, the data adaptor comprising: i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry; ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which said parallel data and control signals were received; iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits; iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits.