Patent ID: 6562651
Filing Date: 2003-05-13
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, the method comprising:forming an insulated wiring pattern on a semiconductor substrate; forming a lower interlayer insulating layer on said wiring pattern; forming a hard mask on said lower interlayer insulating layer; forming self-aligned contact holes to expose said substrate thereunder by partially etching said lower interlayer insulating layer using said hard mask as an etch mask; performing a surface treatment which includes isotropically etching sidewalls of said lower interlayer insulating layer exposed through said self-aligned contact holes; conformably forming a first conductive layer over said substrate; anisotropically etching said first conductive layer which transforms sidewalls of said first conductive layer in said self-aligned contact holes to have a positive slope; and forming a second conductive layer over said substrate which fills said self-aligned contact holes.