Patent ID: 6051889
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A semiconductor device comprising:a substrate having a first principal surface, said substrate carrying first wiring patterns on a first principal surface;a semiconductor chip having a second principal surface, said semiconductor chip carrying second wiring patterns on said second principal surface, said semiconductor chip being disposed on said substrate such that said second principal surface faces said first principal surface; anda conductor connecting one of said first wiring patterns and one of said second wiring patterns electrically and mechanically;said second wiring patterns including a power conductor pattern and at least one other wiring pattern;wherein said at least one other wiring pattern faces said first principal surface at a predetermined distance, and a distance between said power conductor pattern and said first principal surface, in an area in correspondence to said power conductor pattern where said power conductor pattern is not electrically connected to said first principal surface, is larger than said predetermined distance,said substrate being formed with a groove on said first principal surface thereof in correspondence to said power conductor pattern, said groove extending along said power conductor pattern.