Patent ID: 6316352
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method of fabricating a bottom electrode, comprising:providing a substrate having a first conductive layer therein;forming a first dielectric layer over the substrate;forming a plurality of bit lines over the first dielectric layer;forming a conformal liner layer over the first dielectric layer to cover the plurality of bit lines;forming a second dielectric layer over the conformal liner layer;forming an opening in the second dielectric layer, wherein the opening exposes the conformal liner layer between the bit lines and on portions of the bit lines;forming a conductive spacer on a sidewall of the opening, such that only a portion of the conformal liner layer between the bit lines is exposed by the spacer, while remaining at least the conformal liner layer lying on the whole bit lines;removing the conformal liner layer which is not covered by the spacer and the second dielectric layer and is exposed by the spacer to expose the underlying first dielectric layer;removing the first dielectric layer exposed by the conductive spacer to form a node contact opening in the first dielectric layer, wherein the node contact opening exposes the first conductive layer; andforming a second conductive layer in the node contact opening.