Patent ID: 8030650
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A plurality of pixel structures arranged in an array substrate, each pixel structure comprising: at least two scan lines formed on a substrate; at least two data lines formed on the substrate and substantially intersecting the at least two scan lines, respectively, so as to form at least one region; at least one thin film transistor disposed in the at least one region and electrically connected to one of the at least two scan lines and one of the at least two data lines; at least one passivation layer disposed on the substrate and covering the at least one region, the at least two data lines, and the at least one thin film transistor, and having at least one opening; at least one defect detection pattern disposed in the at least one region and penetrating through the at least one passivation layer to expose the substrate, wherein the at least one defect detection pattern includes at least one hole or at least one groove; and at least one pixel electrode disposed on the at least one passivation layer and electrically connected to the at least one thin film transistor via the at least one opening, and extending to the substrate via the at least one defect detection pattern, wherein, at least one of the plurality of the pixel structures comprises a residue remained between the at least one passivation layer and the substrate and exposed in the at least one defect detection pattern, the at least one pixel electrode contacts with the residue via the at least one defect detection pattern.