Patent ID: 6790706
Filing Date: 2004-09-14
Classification: H01L

Abstract:
A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising:supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate; positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads; depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips; singulating the substrate to obtain a plurality of separated semiconductor packages, wherein singulating the substrate further comprises thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate, and dicing the thinned substrate to form a plurality of separated semiconductor packages; and depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads.