Patent ID: 8351283
Filing Date: 2013-01-08
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a memory cell array in which a plurality of memory cells are arranged; a first buffer for fetching a first clock signal; a second buffer for fetching a second clock signal which is different from the first clock signal; a first circuit that fetches various signals used for writing/reading data to/from the memory cell array synchronously with a first internal clock signal; a second circuit that outputs data read from the memory cell array synchronously with a second internal clock signal; a first DLL circuit that generates the first internal clock signal by delaying the first clock signal so as to reduce a phase difference between the first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit; and a second DLL circuit that generates the second internal clock signal by delaying the second clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit.