Patent ID: 7215573
Filing Date: 2007-05-08
Classification: G11C

Abstract:
1. A memory array comprising: a plurality of memory cells, arranged in a plurality of rows and columns, wherein each cell has at least four terminals; a plurality of column lines with each column line connected to a first terminal of cells in a different column; a plurality of first row lines, with each first row line connected to a second terminal of cells in a different row; a plurality of second row lines, with each second row line connected to a third terminal of cells in a different row; a plurality of third row lines with each third row line connected to a fourth terminal of cells in a different row; a column decoder connected to said plurality of column lines; a first row decoder connected to said plurality of first row lines; a second row decoder connected to said plurality of second row lines; a third row decoder connected to said plurality of third row lines; wherein during an operation of a selected cell, said column decoder selects one of said plurality of column lines, said one column line selected is connected to the first terminal of the selected cell; said first row decoder selects one of said plurality of first row lines, said one first row line selected is connected to the second terminal of the selected cell; said second row decoder selects a first plurality of second row lines, one of said first plurality of second row lines is connected to the third terminal of the selected cell; said third row decoder selects a second plurality of third row lines, one of said second plurality of third row lines is connected to the fourth terminal of the selected cell; and wherein the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected.