Patent ID: 6625082
Filing Date: 2003-09-23
Classification: G11C

Abstract:
A memory system comprising:A. a memory chip; B. a plurality of main banks arranged on aid memory chip, for storing and outputting multi-bit data in synchronism with a lock signal, independently of one another, each composed of a plurality of sub-bank, each of which comprises: a. a plurality of memory-cell block, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder located at a first end of every column of memory cells and connected to said column electing lines; c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers located at a second end of every column of memory cells; e. a cell-array controller located at he first end of every row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region provided on side memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, on the one hand, and said data input/output region, on the other; E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.