Patent ID: 6501406
Filing Date: 2002-12-31
Classification: H03H

Abstract:
A digital decimation filter including:a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits; a set of cascaded derivative stages for receiving said first signal and generating therefrom an output signal comprised of bit words including a second number of bits, said second number of bits being smaller than said first number of bits; and a bit discarding unit located downstream of said set of cascaded integrator stages and upstream of said set of cascaded derivative stages for discarding a given number of least significant bits from the bit words of said first signal before said first signal is received by said set of cascaded derivative stages, said given number being defined as the difference between said first and said second number of bits, wherein each of the cascaded integrator stages of the digital decimation operates on a first word length corresponding to the first number of bits and each of the cascaded derivative stages of the digital decimation filter operates on a second word length corresponding to the second number of bits.