Patent ID: 6286062
Filing Date: 2001-09-04
Classification: G06F

Abstract:
A memory system comprising:a memory controller;a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;a plurality of M memory devices wherein each memory device internally contains a data in and a data out buffer and contains a column decoder and a row decoder;a command buffer connected between the command and address bus and the plurality of memory devices, the command buffer receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices, wherein the command buffer is shared by the plurality of M memory devices; anda data buffer connected between the plurality of M memory devices and the bidirectional data bus, the data buffer receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of M memory devices for a write operation, the data buffer receiving and latching the data information from the plurality of M memory devices and driving the data information to the bidirectional data bus for a read operation, wherein the data buffer is shared by the plurality of M memory devices.