Patent ID: 6785182
Filing Date: 2004-08-31
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a memory cell array region in which a plurality of nonvolatile memory cells are arranged, each of the nonvolatile memory cells including a control gate; and a control gate voltage generation section which generates a voltage driving the control gate of each of the nonvolatile memory cells in the memory cell array region, wherein the control gate voltage generation section includes: a booster circuit which generates a plurality of voltages; and a voltage control circuit which includes a plurality of voltage output terminals, the voltage control circuit switching and outputting the voltages from the booster circuit to the voltage output terminals in accordance with a selection state of the nonvolatile memory cells, and wherein the voltage control circuit outputs a maximum voltage among the voltages to the voltage output terminals commonly during a pre-drive period which is a period before the voltages are outputted from the voltage output terminals.