Patent ID: 7920642
Filing Date: 2011-04-05
Classification: H03D

Abstract:
1. An integrated circuit comprising: a first filter; a second filter; an oscillator having a plurality of outputs, where the plurality of outputs includes pairs of signals in quadrature and where each pair of the signals are shifted in phase from one another; a first plurality of mixers, each of the first plurality of mixers coupled to the first filter and further coupled to one of the plurality of outputs from the oscillator; and a second plurality of mixers, each of the second plurality of mixers coupled to the second filter and further coupled to one of the plurality of outputs from the oscillator; and a first and a second plurality of registers coupled to at least one mixer of the first plurality of mixers and at least one mixer of the second plurality of mixers, wherein the first plurality of registers is configured to receive the most significant bits from a plurality of outputs from the first and the second plurality of mixers and the second plurality of registers is configured to receive the least significant bits from the plurality of outputs from the first and the second plurality of mixers.