Patent ID: 9224476
Filing Date: 2015-12-29
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first NAND string including a plurality of memory cells and first and second select memory cells whose source and drain are serially connected, a second NAND string including a plurality of memory cells and third and fourth select memory cells whose source and drain are serially connected, the third select memory cell being selected at the same time as the first select memory cell and having a threshold voltage different from a threshold voltage of the first select memory cell and the fourth select memory cell being selected at the same time as the second select memory cell and having a threshold voltage different from a threshold voltage of the second select memory cell, a bit line arranged in correspondence to the first and second NAND strings, a first source line connected to the second NAND string, a second source line connected to the first NAND string, and a plurality of word lines that select plural memory cells arranged in a row direction from among the plurality of memory cells, wherein data is written in a first memory cell of the first NAND string selected by the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell at write time, and wherein data is verified for the first memory cell of the first NAND string selected, then data is verified for the second memory cell of the second NAND string, data is verified for the third memory cell of the first NAND string and finally data is verified for the fourth memory cell of the second NAND string at verify time.