Patent ID: 7984279
Filing Date: 2011-07-19
Classification: G06F

Abstract:
1. A method of processing branch history information comprising: identifying a branch instruction in a first pipeline stage prior to a decode stage; at a mux, selecting branch history information associated with the branch instruction, wherein the mux is configured to receive the branch history information associated with the branch instruction prior to the decode stage and to receive corrected branch history information from a branch correction logic circuit; shifting the branch history information of the branch instruction into a first register, wherein the first register comprises a working global history register, wherein the working global history register stores branch history information for a plurality of previously processed branch instructions, and wherein the branch history information for the plurality of previously processed branch instructions comprises prediction values and resolution values of recently processed conditional branch instructions and branch directions of recently processed unconditional branch instructions; confirming the branch instruction in the decode stage; shifting the branch history information of the branch instruction into a second register during the decode stage, wherein the second register comprises a global history register that stores the branch history information for the plurality of previously processed branch instructions; wherein the contents of the second register mirror contents of the first register after the branch instruction is decoded by the decode stage and wherein an output of the mux is sent to an address hashing logic circuit to determine an address index for an entry in a branch history table; and when a misprediction occurs, the branch correction logic circuit restores the branch history information in both said first and second registers to correct the branch history information at the same time it provides the correct branch history information to the mux.