Patent ID: 8471751
Filing Date: 2013-06-25
Classification: H03M

Abstract:
1. An apparatus, comprising: a first analog-to-digital converter (ADC) configured to receive an analog input signal and to convert the analog input signal into a first digital signal, the first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal, wherein the first ADC comprises a successive approximation register (SAR) and is configured to produce a residual voltage corresponding to a difference in value between the analog input signal and the first digital signal; and a second ADC coupled to the first ADC and configured to receive the residual voltage and to convert the residual voltage into a second digital signal, the second digital signal corresponding to a least-significant-bits (LSB) portion of the digital output signal, wherein the second ADC comprises a time-to-digital converter (TDC), and wherein the digital output signal is a digital representation of the analog input signal.