Patent ID: 8975754
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A chip package, comprising: a substrate having a first surface, a second surface and a side, wherein the first surface and the second surface are substantially parallel, and wherein the side is on a plane which is at an angle relative to a plane of the first surface, wherein the angle is between zero and 90 degrees; first electrical pads disposed on the first surface; second electrical pads disposed on the side; and through-substrate vias (TSVs) electrically coupling the first electrical pads and the second electrical pads, wherein a given TSV electrically couples a given one of the first electrical pads and a given one of the second electrical pads; wherein the second electrical pads are configured to electrically couple to a set of semiconductor dies arranged in a stack in a direction which is substantially perpendicular to the first surface; and wherein the semiconductor dies in the set of semiconductor dies are offset from each other in a horizontal direction in the plane of the first surface so that one side of the stack defines a stepped terrace.