Patent ID: 6360305
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A method for optimizing memory requests to a computer memory wherein said computer memory comprises a memory controller and at least one chip select coupled to said memory controller, said chip select comprising first and second banks and further wherein said memory requests comprise a first request, where said first request is directed to said first bank, said method comprising the steps of:sending said first request to said memory controller; determining that said first request has been accepted by said memory controller; determining that said first request is an eight quadword access; determining that said first request is a page hit; determining that said first request is a page miss; determining that said second bank is active; generating a pre-charge operation to said second bank one clock cycle after said first request has been accepted by said main memory when said second bank is active and when said second bank is different from said first bank and when said first request is an eight quadword request and a page hit; and generating a pre-charge operation to said second bank one clock cycle after said first request has been accepted by said main memory when said second bank is active and when said second bank is different from said first bank and when said first request is an eight quadword request and a page miss.