Patent ID: 8775707
Filing Date: 2014-07-08
Classification: G06F

Abstract:
1. A single wire bus architecture comprising: a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a delay unit having two capacitors that are alternately charged by a fixed current so that a charging voltage on the capacitors is used to determine points where the single wire bus is activated and sampled; and a communication protocol implemented over the single wire bus for communication between the master device and the at least one slave device; wherein the communication protocol employs the use of a continuous clock signal and bi-directional data transmission within each clock cycle for communication between the master device and the at least one slave device; wherein the bus is in a tri-state period during bi-directional data transmission in which one of the master device or the at least one slave device can pull down or leave the clock signal unchanged to signal a data value; and wherein timing between the continuous clock signal and the bi-directional data is defined by leading and trailing edges of each clock cycle.