Patent ID: 6281058
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A method of forming a memory device comprising:providing a structure on a semiconductor substrate, the structure comprising a memory array region having a plurality of memory array gate areas and a plurality of memory storage nodes and a periphery region comprising a plurality of periphery gate areas, the structure having a layer of a dielectric material and a layer of conductive material thereon, and wherein the periphery gate areas comprise a first peripheral region and a second peripheral region for the formation of first and second conductivity type CMOS field effect transistors;after providing the structure, removing portions of the conductive layer and the dielectric layer;doping the semiconductor substrate with a first dopant to form source and drain regions associated with each gate of the memory array region; anddoping the substrate with a second dopant to form source and drain areas associated with each of the gates in the periphery region, the steps of removing and the doping with the first and second dopants being performed with not more than two masking steps.