Patent ID: 6341086
Filing Date: 2002-01-22
Classification: G11C

Abstract:
A semiconductor memory circuit comprising:a sense amplifier amplifying data read out from a memory cell; a first data storing circuit for temporally storing and outputting the data from said sense amplifier in response to a latch signal, said first data storing circuit erasing the stored data in response to a first clear signal; a first determination circuit coupled to said first data storing circuit for determining whether said first data storing circuit stores the data, said first determination circuit outputting a first determination signal representing the determination; an output data bus; a first transfer circuit coupled to said first data storing circuit, said first determination circuit and said output data bus, said first transfer circuit transferring the data output from said first data storing circuit to said output data bus in response to the first determination signal; a first clear signal generation circuit coupled to said first determination circuit and said first data storing circuit for generating the first clear signal in response to the first determination signal; a second data storing circuit for temporally storing and outputting the data output from said first data storing circuit in response to the latch signal, said second data storing circuit erasing the stored data in response to a second clear signal; a second determination circuit coupled to said second data storing circuit for determining whether said second data storing circuit stores the data, said second determination circuit outputting a second determination signal representing the determination; a second transfer circuit coupled to said second data storing circuit, said second determination circuit and said output data bus, said second transfer circuit transferring the data output from said second data storing circuit to said data bus in response to the second determination signal; and a second clear signal generation circuit coupled to said second determination circuit and said second data storing circuit for generating the second clear signal in response to the second determination signal.