Patent ID: 7602646
Filing Date: 2009-10-13
Classification: G11C

Abstract:
1. A method for evaluating an embedded EPROM in an integrated circuit, the method comprising: applying predetermined voltages to a plurality of floating-gate cells of the embedded EPROM, whereby a floating gate of each of said plurality of floating-gate cells is subjected to a predetermined programming/unprogramming potential; after de-asserting the predetermined voltages, coupling a control gate of each said of said floating-gate cells to a predetermined test bias voltage, and coupling an output terminal of each of said floating-gate cells to a logic circuit, whereby each said of said floating-gate cells transmits an output signal to said logic circuit in response to said predetermined test bias voltage, wherein the logic circuit includes means for generating a single-bit cell test result signal having a first logic value when all of said plurality of floating-gate cells store a predetermined programmed/unprogrammed charge, and for generating said single-bit cell test result signal having a second logic value when one or more of said plurality of floating-gate cells fails to store said predetermined programmed/unprogrammed charge; and transmitting said single-bit cell test result signal out of said integrated circuit to an external test system.