Patent ID: 8286021
Filing Date: 2012-10-09
Classification: G06F,G11C

Abstract:
1. A flash memory package, comprising: a nonvolatile memory cell array; a clock signal input package terminal configured to receive a clock signal from a source external to the flash memory package; an input package terminal configured to receive from the source external to the flash memory package a signal designating a data input mode; a plurality of data input/output package terminals, each of the data input/output package terminals being configured to receive from the source external to the flash memory package data, an address and a command; and a data input/output buffer circuit that is electrically connected to the clock signal input package terminal and to the plurality of data input/output package terminals, wherein the signal designating the data input mode is a first logic level signal, and wherein the data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output package terminals in synchronization with rising and falling edges of the clock signal that is applied to the clock signal input package terminal while the input package terminal configured to receive the signal designating the data input mode is maintained at the first logic level at least throughout a period of data being input to the flash memory package.