Patent ID: 6549038
Filing Date: 2003-04-15
Classification: H03K

Abstract:
A method of clocking a multilevel logic circuit, each level of the multilevel logic circuit having inverting dynamic logic gates only, each inverting dynamic logic gate implementing an arbitrary inverting logic function, each inverting dynamic logic gate driving the output to the value of the logic function when triggered by a clock signal, each inverting dynamic logic gate having all inputs and an output fully pre-charged to VDD (logic â€œ1â€ ), the method comprising:determining a gate optimum clock arrival time for each inverting dynamic logic gate by trying all possible gate clock arrival times and choosing the gate clock arrival time that yields a minimum delay for each inverting dynamic logic gate; determining a level optimum clock arrival time for each level by determining the maximum clock arrival time, over all gate arrival times, for all inverting dynamic logic gates in a level; determining a multilevel logic circuit optimum delay by sequentially determining level optimum clock arrival times for each level in the multilevel logic circuit; applying to each inverting dynamic logic gate in a given level, a clock signal at the level optimum clock arrival time for that level.