Patent ID: 8442154
Filing Date: 2013-05-14
Classification: H03G,H04B,H04L,H04W,Y02D

Abstract:
1. An architecture for a channel-sensitive power control, the architecture comprising: a receiver front end operable to receive and process an incoming signal from a communication channel in a plurality of circuits to generate a digital signal, thereby enabling an estimation of a communication channel quality, signal characteristics and an error rate; a signal strength detector operable to receive one or more signals from the plurality of circuits, the signal strength detector being operable to sense a signal strength of each of the one or more signals to generate signal strength information; and a receiver back end operable to estimate one or more receive signal factors based on the signal strength information, and operable to map the one or more receive signal factors to control signals for optimizing power consumption of receiver front end, the receiver back end comprising: