Patent ID: 6324097
Filing Date: 2001-11-27
Classification: G11C,H01L

Abstract:
A single poly non-volatile memory structure, which comprises:a semiconductor substrate having a first and second active areas divided by an isolation region;a control gate embedded in the first active area and doped with impurities;a first floating gate formed upon the control gate;a second floating gate formed upon the second active area;a first doped region and second doped region formed at opposite two sides of the second floating gate in the second active area to establish a channel between the first doped region and the second doped region; anda floating gate line connecting between the first floating gate and the second floating gate for allowing the first floating gate and the second floating gate in a same potential when the first floating gate generates the potential for responding to the voltage level of the control gate, thereby driving electrons ejecting from the first doped region and trapped into the second floating gate.