Patent ID: 7486319
Filing Date: 2009-02-03
Classification: G11C,H03L

Abstract:
1. A signal generating circuit for generating an output signal, comprising: a delay-locked loop for generating a plurality of delay signals obtained by delaying a reference signal by predetermined time intervals; a selecting circuit for selecting, in accordance with a rising edge designation signal for designating a rise time and a falling edge designation signal for designating a fall time, a first delay signal rising at the rise time designated by the rising edge designation signal and a second delay signal rising at the fall time designated by the falling edge designation signal, from among the plurality of delay signals; a phase relationship detecting circuit for detecting the phase relationship between the first delay signal and the second delay signal, and generating a selection signal based on the detected phase relationship; and a generating circuit including two or more arithmetic circuits, for selecting one of the two or more arithmetic circuits based on the selection signal, and for outputting the output signal rising at the designated rise time and falling at the designated fall time by performing arithmetic processing using the selected one of the arithmetic circuits.