Patent ID: 6909623
Filing Date: 2005-06-21
Classification: G11C

Abstract:
1. A content addressable memory cell comprising: a first bit line; a second bit line; a pair of transistors arranged to store a first bit of data at a first point and a second bit of data that is the complement of the first bit of data at a second point; a first transistor coupled to the first bit line and the first point; a second transistor coupled to the second bit line and the second point; a word line coupled to the first transistor and second transistor, the word line carrying a voltage changed in accordance with process parameters to allow current conduction of the first and second transistors that compensates for leakage by the pair of transistors; a match transistor switchable to a first state in response to a first predetermined relationship between the first and second bits and third and fourth bits transmitted on the first bit line and the second bit line and switchable to a second state in response to a second predetermined relationship between the first and second bits arid the third and fourth bits; a third transistor coupling the first bit line, first point and match transistor; and a fourth transistor coupling the second bit line second point and match transistor.