Patent ID: 6528835
Filing Date: 2003-03-04
Classification: H01L

Abstract:
An integrated memory structure, comprising:a peripheral portion, comprising transistors having doped regions at a semiconducting surface of the structure, and having gate structures disposed near the semiconducting surface; an array portion, comprising; transistors having doped regions at a semiconducting surface of the structure, and having gate structures disposed near the semiconducting surface; and storage capacitors, having first and second plates and a capacitor dielectric, disposed above the transistors; an interlevel dielectric layer disposed over the gate structures and doped regions in both the periphery portion and the array portion, the interlevel dielectric layer having contact openings therethrough over selected locations of the doped regions in both the periphery portion and the array portion; and an interconnect layer, disposed above the interlevel dielectric layer and into the contact openings, in electrical contact with the doped regions in both the periphery portion and the array portion, the interconnect layer being disposed between the gate structures and the storage capacitors in the array portion, and, in both the periphery portion and the array portion, consisting essentially of a material having the properties of stability when subjected to temperatures above a temperature used in the formation of the storage capacitors, and being substantially a barrier to diffusion of dopant from the doped regions.