Patent ID: 6266280
Filing Date: 2001-07-24
Classification: G11C

Abstract:
In a method of programming a NOR-type flash memory which comprises a memory cell array composed of a plurality of memory cells, each of said memory cells having a transistor including a multi-layer stacked gate, a drain and a source, a method of programming a nonvolatile semiconductor device at low power, comprising the step of programming information in a selected one of said memory cells by applying a high voltage to said gate of said selected memory cell to induce a strong electric field from a semiconductor substrate, applying a ground voltage to said drain of said selected cell, allowing said source of said selected cell to float, and applying a desired voltage to said drains of nonselected ones of said memory cells not to program said nonselected memory cells, said desired voltage having approximately half the level of said high voltage applied to said gate of said selected memory cell.