Patent ID: 9171828
Filing Date: 2015-10-27
Classification: H01L,H02M

Abstract:
1. A method for fabricating a power supply system comprising: providing a leadframe having leads and a pad with a first and a second surface, the first surface having a portion recessed with a depth and an outline suitable for attaching semiconductor chips; attaching a driver-and-control chip on the second surface of the pad; connecting the terminals of the driver-and-control chip to respective leads using bonding wires; encapsulating the driver-and-control chip, the bonding wires, and the second pad surface in a packaging compound, while leaving the first pad surface un-encapsulated; then attaching a first field-effect transistor (FET) chip with its drain terminal to the recessed portion of the first pad surface so that the source and gate terminals of the first FET chip are co-planar with the un-recessed portion of the first pad surface; and attaching a second FET chip with its source terminal to the recessed portion of the first pad surface so that the drain and gate terminals of the second FET chip are co-planar with the un-recessed portion of the first pad surface.