Patent ID: 8586468
Filing Date: 2013-11-19
Classification: B82Y,H01L

Abstract:
1. A method for interconnecting a plurality of semiconductor chips, comprising: forming at least one via through the thickness of at least a first one of the semiconductor chips; vertically stacking the first semiconductor chip over a second semiconductor chip such that a bottom of the via is exposed to a conductive interconnect region of the second semiconductor chip; forming a catalyst layer at the bottom of the via, said catalyst layer being electrically interconnected to a conductive interconnect region of the second semiconductor chip; filling the via with a carbon nanotube conductor; forming a contact metal pad on a top surface of the carbon nanotube conductor, said contact metal pad thermally isolated from a conductive interconnect region of the first semiconductor chip; annealing an interface defined by the top surface of the carbon nanotube conductor and the contact metal pad; wiring the contact metal pad and the conductive interconnect region of the first semiconductor chip after said annealing step; and further comprising the step of using an oxygen plasma process to remove excess nanotube material from the top surface of the first semiconductor chip, wherein said step of using an oxygen plasma process forms a recess in a top surface of the nanotube material.