Patent ID: 6380024
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method of fabricating a static random access memory, (SRAM), cell on a semiconductor substrate, comprising the steps of:forming gate structures on an underlying gate insulator layer; forming buried contact structures on first portions of said semiconductor substrate; forming N type lightly doped source/drain regions in second portions of said semiconductor substrate in a region to be used for NMOS devices of said SRAM cell; forming P type lightly doped source/drain regions in third portions of said semiconductor substrate in a region to be used for PMOS devices of said SRAM cell; forming insulator spacers on the sides of said gate structures and on the sides of said buried contact structures; performing a first heavily doped ion implantation procedure; to form N type heavily doped source/drain regions in said second portions of said semiconductor substrate; to form N type buried contact structures, in regions in which said buried contact structures reside in said NMOS region of said SRAM cell; and to form N type polysilicon gate structures in an area in which said gate structures resides in said NMOS region of said SRAM cell; performing a second heavily doped ion implantation procedure; to form P type heavily doped source/drain regions in said third portions of said semiconductor substrate; to form P type buried contact structures in regions in which said buried contact structures reside in said PMOS regions of said SRAM cell; and to form P type polysilicon gate structures in an area in which said gate structures reside in said PMOS region of said SRAM cell; performing an anneal procedure to create N type buried contact regions underlying said N type buried contact structures and to create P type buried contact structures underlying said P type buried contact structures; forming a metal silicide layer; on dual gate structures, comprised of said N type polysilicon gate structures and of said P type polysilicon gate structures; on said N type buried contact structures and on said P type buried contact structures; on said N type heavily doped source/drain regions and on said P type heavily doped source/drain regions; forming contact hole openings in an interlevel dielectric layer exposing portions of said metal silicide layer with said contact hole openings; overlying a portion of said N type heavily doped source/drain regions; overlying a portion of said P type heavily doped source/drain regions; overlying portions of said dual gate structure; and overlying portions of said N type buried contact structure and said P type, buried contact structure; forming metal plug structures in said contact hole openings; and forming metal interconnect structures overlying and contacting metal plug structures.