Patent ID: 6362501
Filing Date: 2002-03-26
Classification: H01L

Abstract:
A DRAM cell array, comprising:a semiconductor substrate having a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from each other; a plurality of transistors each having a gate electrode formed on the active regions, and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions of the plurality of transistors, and having a lower electrode and an upper electrode; a plurality of transistors each having a gate electrode formed on the active regions, and a source and drain region formed in the substrate at both sides of the gate electrodes; a plurality of capacitors connected to one of the source and drain regions of the plurality of transistors, and having a lower electrode and an upper electrode; a plurality of bit lines connected to one of the source and drain regions of the plurality of transistors and arranged in parallel with each other; and a plurality of word lines having first word lines and second word lines arranged in parallel with one another and in a direction perpendicular to a direction in which the bit lines are arranged, wherein the first word lines are connected to the gate electrodes of neighboring transistors and the second word lines are connected to insulating gate electrodes arranged on the substrate between neighboring transistors.