Patent ID: 8021918
Filing Date: 2011-09-20
Classification: H01L

Abstract:
1. A method for fabricating an integrated circuit chip, comprising: providing a silicon substrate, an ESD circuit in or over said silicon substrate, an internal circuit in or over said silicon substrate, wherein said internal circuit comprises an NMOS transistor, with a ratio of a physical channel width of said NMOS transistor to a physical channel length of said NMOS transistor ranging from 0.1 to 20, a dielectric structure over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric structure, wherein said first interconnecting structure is connected to said ESD circuit, a first metal interconnect over said silicon substrate, wherein said first metal interconnect is connected to said ESD circuit through said first interconnecting structure, a second interconnecting structure over said silicon substrate and in said dielectric structure, wherein said second interconnecting structure is connected to said internal circuit, a second metal interconnect over said silicon substrate, wherein said second metal interconnect is connected to said internal circuit through said second interconnecting structure, and a passivation layer over said dielectric structure, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is a bottom of said second opening; and forming a third interconnecting structure over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said third interconnecting structure, where said ESD circuit is connected to said internal circuit through, in sequence, said first interconnecting structure, said first metal interconnect, said third interconnecting structure, said second metal interconnect and said second interconnecting structure, wherein said forming said third interconnecting structure comprises forming a first patterned circuit layer using a first process and a forming second patterned circuit layer using a second process, wherein said first process comprises forming a first metal layer, forming a first photoresist layer over said first metal layer, wherein a third opening in said first photoresist layer exposes a first region of said first metal layer, forming a second metal layer over said first region and in said third opening, removing said first photoresist layer, and removing said first metal layer not under said second metal layer, and wherein said second process comprises forming a third metal layer, forming a second photoresist layer over said third metal layer, wherein a fourth opening in said second photoresist layer exposes a second region said third metal layer, forming a fourth metal layer over said second region and in said fourth opening removing said second photoresist layer, forming a third photoresist layer over said fourth metal layer, an opening in said third photoresist layer exposes a third region of said fourth metal layer, forming a fifth metal layer over said third region and in said fifth opening, removing said third photoresist layer, and removing said third metal layer not under said fourth metal layer.