Patent ID: 6804725
Filing Date: 2004-10-12
Classification: G01R

Abstract:
An integrated circuit comprising:A. a substrate; B. a test data input pin, a test data output pin, a test mode select input pin, and a test clock input pin, all formed on the substrate; C. a first set of functional circuits formed on the substrate; D. a second set of functional circuits formed on the substrate; E. a first scan path formed on the substrate and connected to the first set of functional circuits; F. a second scan path formed on the substrate and connected to the second set of functional circuits; G. a first test access port formed on the substrate, the first test access port being connected to the first scan path, the test data input pin, and the test clock input pin, the first test access port having a test mode select input lead and a test data out lead; H. a second test access port formed on the substrate, the second test access port being connected to the second scan path, the test data input pin, and the test clock input pin, the second test access port having a test mode select input lead a test data out lead; I. a linking module formed on the substrate, the linking module having a test data input lead connected to the test data input pin, a serial data out lead, a test mode select lead connected to the test mode select input pin, and a test clock input lead connected to the test clock input pin, the linking module including: i. a shift register having serial data leads connected in series between the test data input lead and the test data output lead, parallel output leads and a control input lead; ii. a decode circuit having parallel input leads connected to the parallel output leads of the shift register and having output leads; iii. an update register having parallel input leads connected to the parallel output leads of the decode circuit, first and second enable output leads, first and second test access port data select output leads, and a control input lead; and iv. a state machine having a test clock input connected to the test clock input lead and a test mode select input connected to the test mode select input lead, the state machine having a first control output lead connected to the control input lead of the shift register, a second control output lead connected to the control input lead of the update register, and a third control output lead; J. a first gating circuit formed on the substrate, the first gating circuit having a first input connected to the test mode select input pin, a second input connected to the first enable output lead, and an output connected to the test mode select input lead of the first test access port; K. a second gating circuit formed on the substrate, the second gating circuit having a first input connected to the test mode select input pin, a second input connected to the second enable output lead, and an output connected to the test mode select input lead of the second test access port; and L. multiplexer circuits formed on the substrate and selectively coupling the serial data out leads of the first and second access ports and the linking module to the serial data output pin, the multiplexer circuits having a linking module data select input lead connected to the third control output lead and first and second test access port data select input leads connected to the first and second test access port data select output leads.