Patent ID: 6195883
Filing Date: 2001-03-06
Classification: B32B,H05K,Y10T

Abstract:
A method of producing fine-line circuitry on a printed circuit board having a planar surface and at least one filled plated through hole, said method comprising the steps of:(a) drilling at least one hole through a dielectric substrate, said hole defining a surface;(b) depositing a seed layer on planar surface of said dielectric substrate and on said surface defined by said hole;(c) depositing electrically conductive plating on said planar surface of said dielectric substrate and on said surface defined by said hole to form a subcomposite;(d) filling said hole with a filler composition;(e) etching said subcomposite to partially remove said electrically conductive layer to thereby reduce the thickness of said electrically conductive layer;(f) removing residual amounts of said filler composition on said subcomposite;(g) etching said subcomposite to completely remove said electrically conductive layer;(h) depositing a seed activator on the surface of said subcomposite including said filler composition;(i) covering said subcomposite with a photoresist and exposing and developing said photoresist to reveal selected areas of said subcomposite including the filler composition;(j) additively plating electrical circuitry on said selected areas of said subcomposite including circuitry on said filler composition electrically connected to the electrically conductive plating on the surface defined by the hole; and(k) wherein said etching of said electrically conductive layer in step (e) reduces the thickness to a minimum thickness of about 0.2 mil.