Patent ID: 8963337
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A semiconductor wafer assembly for processing substrates comprising: a support wafer; a thin target wafer bonded to said support wafer using a double-sided release tape disposed therebetween, said release tape having a release temperature at which said bond between the support wafer and the thin target wafer is released; and a platen upon which the support wafer is disposed, the platen having a diameter smaller than a diameter of the support wafer to shield the platen from an ion beam directed at the thin target wafer during an ion implantation process; wherein the release tape has a surface area, the thin target wafer has a surface area, and the platen has a surface area, the release tape surface area being smaller than the thin target wafer surface area by a first amount, the surface area of the platen being smaller than the surface area of the thin target wafer by a second amount, and the first amount being proportional to the second amount to shield the release tape from an ion beam directed at the thin target wafer during the ion implantation process.