Patent ID: 6127866
Filing Date: 2000-10-03
Classification: G11C,H03L

Abstract:
A circuit, comprising:a receiver for receiving an input train of pulses; anda delay-locked-loop coupled to an output of the receiver, the delay-locked-loop comprising:a pulse generator responsive to the received input train of pulses produced at the output of the receiver for producing first pulses in response to leading edges of the received input train of pulses and second pulses in response to trailing edges of the received input train of pulses, the leading edges of the first pulses having the same edge type as the leading edges of the second pulses;a logic network for combining the first pulses and the second pulses into a composite input signal comprising the first and second pulses with the leading edges of the first pulses maintaining the same edge type;a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a time delayselected in accordance with the first pulses, second pulses and one of the first train of pulses and the second train of pulses in the composite output train of pulses.