Patent ID: 6718465
Filing Date: 2004-04-06
Classification: G06F

Abstract:
A reconfigurable process for performing matrix multiplication based upon square recursive decomposition of partial product matrices and dynamic reconfiguration of basic multipliers and adders, said process steps comprising:a) providing an array of multipliers physically organized so that the output of said multipliers is grouped in a sequence of locations forming a local square; b) dynamically reconfiguring an input network which routes input from a set of fixed ports into a fixed permutation network in row-major and/or column-major order, according to a control input of an array of simple reconfigurable switches; c) recursively building from said local square an NÃ—N bit multiplier by applying local processing recursively for larger calculations; d) providing at least one array of adders, each said adder array comprising a right adder, adding four n-bit numbers and a left adder, adding a single (n/2)-bit number with three carry bits from the right adder; e) dynamically reconfiguring an output network from said multiplier array to said adder array(s) to appropriately interpret products of said multipliers, according to a control input from an array of simple reconfigurable switches; and f) pipelining the output from the adder arrays.