Patent ID: 8183070
Filing Date: 2012-05-22
Classification: G02F,G03F,H01L

Abstract:
1. A method of fabricating a data line on an array substrate for a liquid crystal display device, the method comprising: forming on a substrate a gate insulating layer, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, and a metallic material layer; forming an initial photoresist (PR) pattern on the metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern, wherein the impurity-doped amorphous silicon layer is exposed between the data line and the metallic material pattern after performing the first ashing process, wherein the first ashed PR pattern on the data line has a smaller width than the data line; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process using the data line as an etching mask to form first and second patterns under the data line; etching a portion of the metallic material pattern to form a source electrode and a drain electrode on the substrate; removing the first ashed PR pattern; forming a passivation layer on the source electrode, the drain electrode and the data line; and forming a pixel electrode on the passivation layer.