Patent ID: 6150844
Filing Date: 2000-11-21
Classification: H03K

Abstract:
An output stage for an electronic circuit with a high voltage tolerance, the output stage comprising:an output buffer including a complementary transistor pair having a pull-up P-channel MOS transistor and a pull-down N-channel MOS transistor with the transistors being connected together to form an output stage output terminal, the pull-up P-channel MOS transistor having a control terminal; anda switch having a switch input coupled to the output stage output terminal, and a switch output coupled to the control terminal of the pull-up P-channel MOS transistor to drive the output stage into a tristate condition wherein the switch has a switching threshold voltage, Vs, such that Vcc<Vs<(Vcc+min), wherein Vcc is a supply voltage, wherein Vtp is a threshold voltage of a P-channel transistor, and wherein V.gamma. is a threshold voltage of a drain-bulk junction.