Patent ID: 6828627
Filing Date: 2004-12-07
Classification: G11C,H01L

Abstract:
A semiconductor device comprisinga semiconductor substrate; an element region and an element isolation region formed on said semiconductor substrate; a plurality of memory cell transistors formed on said element region, each of said plurality of memory cell transistors including a gate insulating film formed on the element region in the semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode, said plurality of memory cell transistors being connected in series between a source line terminal and a bit line terminal to share the diffused layer between adjacent memory cell transistors; an inter-film including a first and second part contacting a top and side faces of each of said memory cell transistors respectively, the first part and the second part being continuous; and a barrier insulating film formed on at least the second part of the inter-film, wherein a distance between a side face of the gate electrode and the barrier insulating film is larger than a thickness of the gate insulating film.