Patent ID: 8140314
Filing Date: 2012-03-20
Classification: G06F

Abstract:
1. A method for running samples in a hardware assisted simulator including a bus functional model, said bus functional model including a cycle-count feedback register enabling binary-convergence to achieve optimal bus-operation performance in a logic simulation environment, comprising the steps of: counting on a software readable feedback register a first number of samples F taken by said bus functional model from said hardware assisted simulator in execution of a first transaction on said bus functional model; storing a last actual sampling value S given to said hardware assisted simulator for said first transaction; encoding in a command register bus cycles for execution in a second transaction; applying a binary convergence algorithm to generate a new sampling value Snew for said second transaction based on said last sampling value given to said hardware assisted simulator and said last actual sampling value taken by said bus functional model for said first transaction; resetting said software readable feedback register; setting a status flag to start said second transaction on said bus functional model; counting in said software readable feedback register the number of sampling values taken by said bus functional model in executing said second transaction; and resetting said status flag to end said second transaction.