Patent ID: 8271738
Filing Date: 2012-09-18
Classification: G06F

Abstract:
1. An apparatus for executing a cache-inhibited write in a symmetric multi-processor having a fabric bus, a chip base address range, and a chip identifier, the apparatus comprising: a display alter coupled to the fabric bus of the symmetric multi-processor for determining that a cache inhibited base address range of the cache-inhibited write matches the chip base address range, the display alter having (i) a means for snooping for a cache inhibited command on the fabric bus, wherein the cache inhibited command is a command for which cache is inhibited and has a cache inhibited base address range and a cache inhibited identifier of the cache inhibited command, (ii) a means for determining that the cache inhibited command is an external scan communications command, and (iii) a means for setting a busy latch; a means for transmitting a support chip address of a support chip connected to a given processor of the symmetric multi-processor and a command type to an external scan communication unit for forwarding the support chip address to a master field replaceable unit support interface; a means for determining that the command type is a write; the external scan communication unit comprising a means for forwarding write data and a write data valid signal to the master field replaceable unit support interface; means for directing the write data to a parallel scan communication unit in response to determining that a parallel scan communication directive is in a support chip field replaceable unit support interface port select; and a means for clearing the busy latch.