Patent ID: 8995191
Filing Date: 2015-03-31
Classification: G06F,G11C

Abstract:
1. A memory device comprising: an array of memory cells, each memory cell being coupled to an associated pair of bit lines; read control circuitry configured during a read operation to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines; sense amplifier circuitry coupled to the bit lines and configured during the read operation to determine the data value stored in each addressed memory cell by evaluation of a pair of signals that develop on the associated pair of bit lines during the read operation in dependence on the data value stored in that addressed memory cell; the sense amplifier circuitry being configured in a speculative read mode of operation to evaluate the pair of signals on the associated pair of bit lines for each addressed memory cell after a speculative read time period that is not guaranteed to be sufficient for the pair of signals to have developed to a degree necessary for the sense amplifier circuitry to correctly determine the data value stored in each addressed memory cell; and error detection circuitry configured, in said speculative read mode of operation, to capture the pair of signals on the associated pair of bit lines for each addressed memory cell and to apply an error detection operation to determine if the pair of signals had not developed to the degree necessary for the sense amplifier circuitry to correctly determine the data value stored in each addressed memory cell, and if so to assert an error signal.