Patent ID: 8406036
Filing Date: 2013-03-26
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a semiconductor substrate; first lines stacked on the semiconductor substrate and arranged parallel with one another; second lines formed to intersect the first lines and arranged parallel with one another; a memory cell array including memory cells provided at intersections of the first lines and the second lines and each including a variable resistance element; a first control circuit provided on a portion of the semiconductor substrate that is in a first region located immediately under the memory cell array, and connected to ends of the first lines to select and drive the first lines; a second control circuit provided on a portion of the semiconductor substrate that is in a second region adjoining the first region, and connected to one end portion of the second lines via first wiring contacts respectively; and dummy lines formed in a same wiring layer in which the first lines are formed, such that the dummy lines intersect the second lines in a region above the second control circuit, and that the first wiring contacts are provided between the dummy lines in a region above the second control circuit, the first control circuit being configured to apply a first voltage to a selected one of the first lines such that a first potential difference is applied to a selected memory cell provided at the intersection of the selected first line and a selected one of the second lines, and apply, to the dummy lines, a second voltage having such a voltage value by which a second potential difference smaller than the first potential difference is applied to the memory cells provided at intersections of the selected second line and the dummy lines, and the second control circuit being configured to apply a third voltage having a larger voltage value than that of the first voltage to the selected second line.