Patent ID: 6262923
Filing Date: 2001-07-17
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of ordinary memory cells;means for activating said ordinary memory cells in response to addresses applied from an external source;a plurality of redundant memory cells, wherein each of s aid redundant memorycells provides seven terminals, one of the seven terminals is connected to a subword line selecting circuit through an inverter for providing a redundant replacement selecting signals;first storage mans for storing an address of a defective memory cell among said ordinary memory cells;comparing means for comparing the addresses applied from the external source and the address of the detective memory cell with each other, wherein the number of bits to be compared by said comparing means is variable;second storage means for storing the number of bits to be compared by said comparing means or the number of bits not to be compared by said comparing means;means for activating a redundant memory cell in response to an output from said comparing means and/or preventing the ordinary memory cells from being activated;first transfer means for transferring stored data of said second storage means to said means for activating a redundant memory cell based on the output from said comparing means;said comparing means comprising means for comparing all or part of bits of the addresses applied from the external source and the stored address of the defective memory cell with each other; anda plurality of divided memory cell arrays which are independently operable according to address signals applied from the external sources, each of said memory cell arrays having said plurality of redundant memory cells.