Patent ID: 8951864
Filing Date: 2015-02-10
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: providing a substrate; forming a storage element over the substrate; forming a control gate over the storage element; forming a dielectric capping layer over the control gate such that the dielectric capping layer physically contacts the control gate, the capping layer extends from a first dielectric sidewall spacer to a second dielectric sidewall spacer; forming a high-k dielectric layer over, and a portion of the top surface of the substrate; forming a metal select gate over the high-k dielectric layer and adjacent to the storage element and the control gate, wherein the metal select gate extends from the second dielectric sidewall spacer to a third dielectric sidewall spacer; and planarizing the dielectric capping layer, the metal select gate, the first dielectric sidewall spacer, the second dielectric sidewall spacer, and the third dielectric sidewall spacer such that a topmost surface of the dielectric capping layer, a topmost surface of the metal select gate, a topmost surface of the first dielectric sidewall spacer, a topmost surface of the second sidewall spacer, and a topmost surface of the third sidewall spacer are substantially coplanar.