Patent ID: 8957474
Filing Date: 2015-02-17
Classification: H01L

Abstract:
1. A MOS transistor, comprising: an active pattern including a plurality of protruding patterns including a semiconductor material and arranged in parallel, and a connecting portion for forming a trench portion between the protruding patterns and connecting bottom portions of the protruding patterns with each other; a gate insulating layer provided on a surface of the active pattern; a gate pattern provided on the gate insulating layer and disposed to cover a first face on a plane of neighboring two protruding patterns and a first sidewall of the connecting portion connected to the first face, an upper surface of the gate pattern being lower than an upper surface of the protruding patterns, a bottom surface of the gate pattern being lower than a bottom surface of the trench portion between the protruding patterns; and impurity regions provided at portions of the protruding patterns disposed higher than the gate pattern, the MOS transistor further comprising: an additional gate pattern to provide an additional MOS transistor, the additional gate pattern being provided on the gate insulating layer and disposed to cover a second face on another plane of the neighboring two protruding patterns and a second sidewall of the connecting portion connected to the second face, an upper surface of the additional gate pattern being lower than the upper surface of the protruding patterns, a bottom surface of the additional gate pattern being lower than the bottom surface of the trench portion between the protruding patterns, wherein three protruding patterns arranged in parallel are included in one active pattern, and the gate pattern and the additional gate pattern use a central one of the three protruding patterns as a common active region.