Patent ID: 6957322
Filing Date: 2005-10-18
Classification: G06F

Abstract:
1. A microcode instruction unit, comprising: a microcode memory including a plurality of entries configured to store microcode instructions; a decoder coupled to said microcode memory and configured to sequentially decode microcode addresses within a first portion of a microcode address space to select corresponding entries of said microcode memory, wherein said decoder is further configured to sparsely decode microcode addresses within a second portion of said microcode address space to select corresponding entries of said microcode memory, wherein said first and second portions of said microcode address space do not overlap, and wherein the number of unique microcode addresses within said microcode address space is larger than the number of entries of said microcode memory; and a microcode entry point unit configured to receive complex instructions and provide a respective microcode entry point address to said decoder for each complex instruction, wherein respective microcode entry point addresses corresponding to a first and a second complex instruction fall within said sparsely-decoded second portion of said microcode address space; wherein one or more microcode instructions included within an entry corresponding to the respective microcode entry point address of said first complex instruction are sufficient to implement said first complex instruction without reference to another entry within said microcode memory; wherein an entry corresponding to the respective microcode entry point address of said second complex instruction includes a jump microcode instruction configured to reference an entry within said sequentially-decoded first portion of said microcode address space.