Patent ID: 6404291
Filing Date: 2002-06-11
Classification: H03K,H03L

Abstract:
A phase locked loop (PLL) frequency synthesizer comprising:a composite phase frequency detection (CPFD) having a CPFD output; a loop filter having a voltage output; a voltage controlled oscillator (VCO) having a frequency output; and a divider having a divider output, the divider output having an active pulse with a first fixed width and an inactive pulse with a second width; wherein the CPFD is coupled to receive the divider output; the CPFD is coupled to receive a reference signal from a reference signal generator; the loop filter is coupled to receive the CPFD output; the VCO is coupled to receive the voltage output, said voltage output controllably affecting the frequency output; the divider is coupled to receive the frequency output; the loop filter generates the voltage output based on the CPFD output; the CFPD output indicates a phase difference between the divider output and the reference signal; and the frequency output has a frequency that is a multiple of the frequency of the divider output.