Patent ID: 6180459
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method for fabricating flash memory device, the method comprising:forming a tunnel oxide layer on a semiconductor substrate;forming a first polysilicon layer on the tunnel oxide layer;forming a mask layer on the first polysilicon layer;patterning the substrate, the tunnel oxide layer, the first polysilicon layer, and the mask layer to form a trench in the substrate;filling the trench with a shallow trench isolation (STI) structure;removing the mask layer;sequentially forming a dielectric layer and a second polysilicon layer over the substrate so that the STI structure and the first polysilicon layer are covered;patterning the second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer, wherein the second polysilicon layer is patterned to form a remaining strip-like structure serving as a control gate, and the first polysilicon layer is patterned to form floating gates, a portion of the substrate other than the remaining strip-like structure is exposed, and the remaining strip-like structure lays continuously and unbroken across the floating gates and the substrate; andperforming an ion implantation process to form an interchangeable source/drain region in the substrate at the exposed portion after forming the control gate and the floating gates, wherein a source line is automatically formed.