Patent ID: 6197646
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device which comprises the steps of:forming an insulated gate structure on a p-type active region of a silicon substrate, said insulated gate structure having a gate length of about 0.3 .mu.m or less and side wall insulating regions;implanting arsenic ions in source/drain regions on opposite sides of said insulated gate electrode structure on said substrate at a dose less than 5.times.10.sup.15 cm.sup.-2 ;activating the implanted arsenic to form doped source/drain regions having a junction depth of 0.1 .mu.m or less;forming a laminated layer of a Co film having a thickness in a range of 5 to 15 nm and a TiN film covering the Co film, on the surface of said substrate, covering said doped source/drain regions;heating said substrate to let said co film react with an underlying Si region of the doped source/drain regions for proceeding with silicidation and form Co-containing spikes which project and allow leak current to flow across the junction;removing said TiN film;removing unreacted Co film; andheating said substrate to further proceed silicidation and let the Co-containing spikes shrink or extinguish.