Patent ID: 6122654
Filing Date: 2000-09-19
Classification: G06G

Abstract:
A complex multiplication circuit for multiplying an input signal having a real portion x and an imaginary portion by a multiplier having a real portion a and an imaginary portion b comprising:(i) a first multiplier for multiplying said read portion of said input signal by an addition of said real and imaginary portions of said multiplier;(ii) a second multiplier by multiplying said imaginary portion of said input signal by a difference between said real and imaginary portions of said multiplier;(iii) a first adder for adding said real and imaginary portions of said input signal, said first adder comprising a capacitive coupling having two capacitances outputs of which are connected to a common output terminal for receiving said real and imaginary portions of said input signal;(iv) a third multiplier for multiplying an output of said first adder by said imaginary portion b of said multiplier;(v) a second adder for calculating a difference between an output of said first multiplier and said an output of said third multiplier; and(vi) a third adder for adding an output of said second multiplier and said output of said third multiplier.