Patent ID: 6372556
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method for fabricating a semiconductor device having a fuse, comprising the steps of:forming a first interlevel insulating layer on a semiconductor substrate having a first metal wire; forming a second metal wire on the first interlevel insulating layer; forming a second interlevel insulating layer on the first interlevel insulating layer; forming a hole and a grooved portion for exposing a surface of the second metal wire embedded in the second interlevel insulating layer by selectively etching out a first predetermined region and a second predetermined region of the second interlevel insulating layer, respectively; forming a conductive plug in the hole and a heat blocking layer in the grooved portion from a metal; forming a third metal wire on the second interlevel insulating layer for connecting with the conductive plug; forming a third interlevel insulating layer on the second interlevel insulating layer; simultaneously forming a fuse pattern in a deposition structure of a fuse metal layer and a wiring metal layer on the third interlevel insulating layer; and forming a fourth metal wire for connection with a lateral edge of the fuse pattern.