Patent ID: 9208848
Filing Date: 2015-12-08
Classification: G11C

Abstract:
1. A semiconductor storage device comprising: a first storage area including a plurality of memory cells each including a resistance change element which stores data; a second storage area including a plurality of memory cells each including a resistance change element which stores data; a sub memory cell array including the first storage area and the second storage area: a memory cell array including a plurality of sub memory cell arrays arranged along a column direction and a row direction; a third storage area which stores store redundancy information and to supply the redundancy information to the sub memory cell array; and a control circuit which stores control an access operation to the memory cell array, wherein when performing an access operation to the first storage area of at least one sub memory cell array belonging to a first row, and to at least one second storage area belonging to a second row, the control circuit performs the access operation to the second storage area of a sub memory cell array belonging to a desired column and to the second row, based on the redundancy information of the third storage area.