Patent ID: 6292924
Filing Date: 2001-09-18
Classification: G06F

Abstract:
A method of calculating a circuit delay for a specified circuit, said method comprising steps of:obtaining a timing graph for the specified circuit, the timing graph including original nodes and original edges;identifying a false path in the timing graph, the false path being a path whose delay should not be considered in a determination of the circuit delay;identifying a sequence of original nodes and original edges in the timing graph that define the false path;adding duplicate nodes to the timing graph, wherein each duplicate node is a duplicate of one of the original nodes in said sequence;replacing an original edge that connects a first original node to a second original node in the sequence with a replacement edge that connects the first original node to the duplicate node that corresponds to the second original node; andcalculating the circuit delay for the specified circuit using the timing graph as modified by said adding and replacing steps.