Patent ID: 6611796
Filing Date: 2003-08-26
Classification: G06F

Abstract:
A digital system having an emulation device, wherein the emulation device comprises:a plurality of the memory blocks; and a processor core connected to the plurality of memory blocks, such that the processor core is operable to execute instructions fetched from the plurality of memory blocks and to transfer data to the plurality of memory blocks each memory block comprising: at least a first address bus input and a second address bus input coupled to the processor core for simultaneously receiving at least two addresses from the processor core; a separate address decoding circuit connected to each one of the address bus inputs, each of the address decoding circuits operable to determine if a received address is assigned to the memory block; arbitration circuitry coupled to the address decoding circuits operable to select the address of the highest priority type request; memory circuitry coupled to the address buses, operable to transfer data on a selected one of two or more data buses in response to the selected address; and control circuitry connected to the address decoding circuitry operable to establish a linked mode and also an unlinked mode, such that in the unlinked mode the arbitration circuitry of a first one of the plurality of memory blocks is operable to select an address received on the first address bus and arbitration circuitry of a second one of the plurality of memory blocks is operable to simultaneously select an address received on the second address bus, but such that in the linked mode the arbitration circuitry of the first memory block and the second memory block both select a same address on only one of the address buses at a time.