Patent ID: 9219487
Filing Date: 2015-12-22
Classification: G01S,H03C,H03L

Abstract:
1. An RF transceiver circuit, comprising: a phase-locked-loop (PLL) including a fractional-N multi-modulus divider, the PLL operating in accordance with a PLL clock frequency and generating a frequency modulated RF output signal; a modulator configured to generate a sequence of division ratios dependent on a set of modulation parameters, the modulator operating in accordance with a system clock frequency, which is lower than the PLL clock frequency; and a sample rate conversion unit coupled between the modulator and the fractional-N multi-modulus divider, the sample rate conversion unit being configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency, wherein the sample rate conversion unit interpolates the sequence of division ratios by an interpolation factor corresponding to the ratio between the PLL clock frequency and the system clock frequency.