Patent ID: 8404496
Filing Date: 2013-03-26
Classification: G01R,H01L,Y10T

Abstract:
1. A method of testing semiconductor devices, comprising the steps of: forming a redistribution layer on the semiconductor devices in a wafer state; forming a seal resin layer on the redistribution layer so as to encapsulate the semiconductor devices; forming grooves in the seal resin layer along scribe lines by removing portions of the seal resin after encapsulating the semiconductor devices by the seal resin layer, the grooves extending through the seal resin layer so that an entire bottom of each of the grooves reaches the wafer and the wafer surface is exposed in the entire bottom of each of the grooves; performing a test on the semiconductor devices in the wafer state while recognizing the wafer exposed at an intersection of the grooves as a reference position; and separating the wafer into individual semiconductor devices by cutting the wafer along the scribe lines, wherein the forming grooves includes forming the grooves by a dicing saw to have a depth exceeding a thickness of the seal resin layer.