Patent ID: 8650512
Filing Date: 2014-02-11
Classification: G06F,Y02P

Abstract:
1. A computer-implemented method for providing an elastic modulus map of an integrated circuit (IC) chip of a chip/device package, said method comprising: loading, by a computer, design data for said IC chip that includes x, y, z coordinates of design elements within each back-end-of line (BEOL) layer of a plurality of BEOL layers, said design elements comprising any of a metal fill, a metal line, and a metal via, and dielectric juxtaposed to said design elements; mapping, by said computer, one of a plurality of uniform tessellated grids onto each of said BEOL layers, each of said plurality of uniform tessellated grids comprising shapes related to feature sizes of said design elements in each of said BEOL layers, said shapes of each of said uniform tessellated grids and said feature sizes of said design elements decreasing from a topmost BEOL layer to a bottom most BEOL layer; determining, by said computer, a metal area and a dielectric area for each of said shapes of each of said plurality of uniform tessellated grids for each of said BEOL layers, based on said design data for any portion of any of said design elements located in each of said shapes; determining, by said computer, for each of said shapes of each one of said uniform tessellated grids for each of said BEOL layers, an equivalent spring constant related to a first spring constant based on said metal area, a first elastic modulus of said metal, and a metal thickness from said design data, and a second spring constant based on said dielectric area, a second elastic modulus of said dielectric, and a dielectric thickness from said design data; accumulating, by said computer, each equivalent spring constant from each of said shapes of each of said uniform tessellated grids for each of said BEOL layers of said IC chip that is located beneath a shape of a topmost uniform tessellated grid, to provide a combined spring constant for each of said shapes of said topmost uniform tessellated grid; and mapping, by said computer, each of said combined spring constants from each of said shapes of said topmost uniform tessellated grid, to provide said elastic modulus map of said IC chip of said chip/device package.