Patent ID: 8586461
Filing Date: 2013-11-19
Classification: H03D,H04B,H04L,H04N

Abstract:
1. A system comprising: a local oscillator circuit operable to provide a frequency agile system clock signal, wherein the local oscillator circuit is further operable to simultaneously provide a frequency agile sampling rate clock signal having a different frequency than a frequency of the frequency agile system clock signal; a digital processing circuit operable to provide digital signal processing using the frequency agile system clock signal; a plurality of digital processing parameters for use in the digital signal processing, wherein different digital processing parameters are associated with different system clock frequencies of the frequency agile system clock signal; and an analog to digital converter operable to provide conversion of an analog signal to a digital signal using the frequency agile sampling rate clock signal, wherein an output of the analog to digital converter is coupled to the digital signal processor to provide the digital signal to the digital processing circuit for signal processing.