Patent ID: 6055587
Filing Date: 2000-04-25
Classification: G06F

Abstract:
In an integrated circuit, configured for connection to an SCSI bus, whereon digital data information is transferred between initiator and target SCSI devices in accord with a data transfer protocol over terminated transmission lines, digital data information being received by the integrated circuit over a data bus portion in sequential byte fashion, each byte occurring within sequential, equally spaced-apart timing windows defined by successive, like-going transition edges of a timing strobe signal, the integrated circuit comprising:a strobe input, connected to receive the timing strobe signal, the timing strobe signal defining a first transition edge and a second, opposite-going transition edge;a plurality of data inputs connected to receive digital data information from the data bus portion, the data inputs further connected to respective ones of a corresponding plurality of data latches; anda digital timing filter, operatively responsive to the first transition edge of the timing strobe signal, the digital timing filter providing a latch strobe signal to the data latches whereby digital data is latched into the integrated circuit, the digital timing filter including timing circuitry operatively responsive to the first transition edge of the timing strobe signal for defining a strobe masking period during which any further transitions of the timing strobe signal are masked until the next occurrence of a like-going transition edge, such that the contents of the data latches are protected.