Patent ID: 9224708
Filing Date: 2015-12-29
Classification: H01L

Abstract:
1. A method for producing at least one interconnection pad on a conducting element comprising an upper face and a side wall, the method being executed from a substrate at least an upper face of which is electrically insulating, the conducting element extending through a portion of the substrate, the method comprising the sequence of the following steps: a step of embossing the conducting element, so configured as to form a protrusion of the conducting element that protrudes beyond the upper face of the substrate; a step of forming, above the upper face of the substrate, a stack of layers comprising successively at least one electrically conducting layer and one electrically resistive layer, with said electrically resistive layer having a higher resistivity than that of the electrically conducting layer; a step of partially removing the electrically resistive layer, so configured as to expose at least a top portion of the at least one electrically conducting layer, said portion being positioned above the protrusion of the conducting element, said step comprising polishing said electrically resistive layer, while preserving said electrically resistive layer around the exposed top portion of the at least one electrically conducting layer; and a step of electrolytic growth from said exposed top portion of the at least one electrically conducting layer, said exposed top portion being configured to seed said electrolytic growth, so as to form said at least one interconnection pad on said conducting element.