Patent ID: 6510507
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A method of causing an event, comprising the steps of:providing an address, having an upper bit portion and a lower bit portion; comparing said upper bit portion of said address against one or more reference registers for yielding one or more â€œmatch-high'sâ€ ; locating said lower bit portion of said address within a memory look-up table for yielding one or more â€œmatch-lowsâ€ ; causing the event upon the occurrence of both the â€œmatch-highâ€  and â€œmatch-lowâ€  being true; wherein said lower bit portion indicates a word address in said look-up table; wherein said address has N bits, said word address has P bits and wherein said one or more reference registers comprises P particular reference registers; and wherein one of said P particular reference registers correspond to one of said bits of said P bit word address.