Patent ID: 8458634
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A computer implemented method for latch clustering with proximity to local clock buffers, the computer implemented method comprising: clustering, using a processor and a memory, a plurality of latches into a first plurality of groups in an integrated circuit, wherein the plurality of latches are clustered using a clustering algorithm; determining a number of groups in the first plurality of groups of clustered latches; adding a plurality of local clock buffers (LCBs) where a number of added LCBs in the plurality of local clock buffers is the same as the number of groups in the first plurality of groups of clustered latches; determining a cluster radius for a subset of the first plurality of groups of clustered latches, a group in the subset having a cluster radius that is a maximum cluster radius in the subset; and reclustering the plurality of latches into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one, wherein reclustering the plurality of latches into the second plurality of groups is further responsive to the number of groups in the first plurality of groups of clustered latches being equal to or less than a maximum number of LCBs.