Patent ID: 6147008
Filing Date: 2000-11-14
Classification: H01L,Y10S

Abstract:
A method of controlling gate oxide thickness in the fabrication of semiconductor devices, comprising the steps of:providing a semiconductor substrate;forming a layer of sacrificial oxide on the surface of said semiconductor substrate;depositing a first layer over the surface of said layer of sacrificial oxide;patterning and etching said first layer thereby creating an opening in said first layer said opening to extend to the surface of said layer of sacrificial oxide;performing an ion implant into the surface of said semiconductor substrate whereby said ion implant aligns with said opening in said first layer;removing said first layer from the surface of said layer of sacrificial oxide;depositing a second layer over the surface of said layer of sacrificial oxide;patterning and etching said second layer thereby creating an opening in said second layer said opening to include and expand beyond the area of said sacrificial oxide that overlies said ion implant;removing said sacrificial oxide from the surface of said semiconductor substrate in accordance with said opening in said second layer thereby creating a patterned layer of sacrificial oxide thereby furthermore exposing the surface of said substrate underneath said opening;removing said second layer from the surface of said layer of sacrificial oxide thereby exposing the surface of said patterned layer of sacrificial oxide;reducing the thickness of said patterned layer of sacrificial oxide a measurable amount; andblanket growing a second layer of oxide over said patterned layer of sacrificial oxide thereby including said exposed surface of said substrate.