Patent ID: 7981737
Filing Date: 2011-07-19
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor array panel, comprising: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer, a buffer layer, and a metal layer on the gate line; patterning the metal layer and the buffer layer by photolithography to form a data line including a source electrode and a drain electrode, and a mold layer pattern; forming a passivation layer having a contact hole exposing the drain electrode on the data line and the drain electrode; forming a transparent conductive layer connected to the drain electrode through the contact hole on the passivation layer; patterning the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by photolithography to form a pixel electrode and a through-hole exposing the mold layer pattern; etching the exposed mold layer pattern through the through-hole to form a mold layer having an opening connected to the through-hole; and filling a semiconductor in the opening through the through-hole.