Patent ID: 8759896
Filing Date: 2014-06-24
Classification: H01L

Abstract:
1. A non-volatile semiconductor memory comprising: a semiconductor substrate having a source region, a drain region, and a channel region located between the source region and the drain region; and a gate multi-layer formed on the channel region and obtained by sequentially stacking the following: a first insulating layer that is formed on the channel region; a charge accumulation layer that is formed of an oxide dielectric film, at least one of titanium (Ti), zirconium (Zr) and hafnium (Hf) which is present as a base material in the oxide dielectric film is substituted by at least one of W, Mo, Cr, Mn and Fe which is introduced as an additive substance; a second insulating layer; and a memory gate electrode, wherein an area density of the substance W, Mo, Cr, Mn or Fe introduced into the oxide dielectric film falls within a range of 1×10