Patent ID: 6791132
Filing Date: 2004-09-14
Classification: G11C,H01L,Y10S

Abstract:
A semiconductor integrated circuit device comprising:(a) a first memory array area which includes a plurality of first memory cells and first data lines which are formed on a first layer and connected with said first memory cells; (b) a second memory array area which includes a plurality of second memory cells and second data lines which are formed on said first layer and connected with said second memory cells; (c) a sense amplifier area which includes sense amplifiers; (d) a first connecting located between said first memory array area and said sense amplifier area; and (e) a second connecting area located between said second memory array area and said sense amplifier area, wherein aid semiconductor integrated circuit device further includes; (f) first lines which are formed on a second layer different from said first layer and connected with said first data lines in said first connecting area; and (g) second lines which are formed on said second layer and connected with said second data lines in said second connecting area, said sense amplifiers being connected between said first lines and said second lines and adapted to amplify voltage differences between said first lines end said second lines.