Patent ID: 6713395
Filing Date: 2004-03-30
Classification: H01L

Abstract:
A method of patterning metal layers of a semiconductor wafer, the method comprising:depositing a first conductive layer over a substrate; depositing an insulating layer over the first conductive layer; depositing a second conductive layer over the insulating layer; depositing a first layer of resist over the second conductive layer; patterning the first layer of resist with a first pattern; developing said patterned first layer of resist; removing portions of said first layer of resist according to said first pattern to expose portions of said second conductive layer; depositing a second layer of resist over remaining portions of the first layer of resist and exposed portions of said second conductive layer; patterning the second layer of resist with a second pattern; developing said patterned second layer of resist; stripping portions of said second layer of resist according to said second pattern; and etching the first conductive layer according to the first pattern and the second conductive layer according to the second pattern in a single etching process.