Patent ID: 8751880
Filing Date: 2014-06-10
Classification: H04L

Abstract:
1. An apparatus for calculating timing margin in a clock and data recovery (CDR) system, comprising: a first data latch configured to sample a digital signal in accordance with a sampling clock signal to provide an estimated digital sequence; a second data latch configured to identify edge transitions of the digital signal in accordance with the sampling clock signal to provide an edge sequence; a phase detector configured to compare the estimated digital sequence and the edge sequence to provide an error signal; a summer configured to combine the error signal and a jitter signal to provide a sampling clock signal phase control; a jitter signal stressor configured to provide the jitter signal in response to a jitter signal stressor control; a phase controller configured to adjust a phase of the sampling clock signal in response to the sampling clock signal phase control; and an evaluator module configured to compare the estimated digital sequence with the digital signal and to cause an increase in the jitter signal until a number of bit errors generated by the first data latch is greater than or equal to a threshold value.