Patent ID: 8429586
Filing Date: 2013-04-23
Classification: G06F,H01L,H03K

Abstract:
1. A circuit architecture comprising an arrangement of transistors configured for formation of at least one of logic circuitry and memory circuitry depending upon a layout of variable overlying layers, wherein the arrangement of transistors comprises: a first pair of gate lines spanning above an n-type diffusion region and two distinct p-type diffusion regions, wherein a width of one of the two p-type diffusion regions is smaller than a width of the other of the two p-type diffusion regions, a second pair of gate lines dividedly arranged in parallel and on opposing sides of the first pair of gate lines, wherein the second pair of gate lines span above portions of the other p-type diffusion region, and a set of four gate lines arranged in parallel with the first pair of gate lines, wherein the set of four gate lines span above extensions of the n-type diffusion region respectively arranged near opposing corners of the n-type diffusion region, wherein the extensions comprise smaller widths than a portion of the n-type diffusion region below the first pair of gate lines.