Patent ID: 7617494
Filing Date: 2009-11-10
Classification: G06F

Abstract:
1. A process for executing programs on at least one processor having a given instruction set architecture, the process comprising the operations of: compiling the program to be executed and translating said program into native instructions of said instruction set architecture, organizing the instructions deriving from the translation of said program into respective bundles arranged in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by said at least one processor, each bundle having a determined priority for execution by said at least one processor; separating said bundles of instructions into respective sub-bundles by detecting a value of a binary symbol encoded in one of the instructions deriving from the translation of the program to be executed of the respective bundle, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions that can be executed both before and in parallel with respect to the instructions belonging to said next bundle of said order, it being possible for at least said second set of instructions to be a null set; defining a sequence of execution of the instructions of said sub-bundles in successive operating cycles of said at least one processor based on said determined priority carried by a designated number of bits encoded into each instruction, while preventing, in assigning each sub-bundle to an operating cycle of the processor, simultaneous assignment, to the same operating cycle, of two sub-bundles corresponding to instructions belonging to a first set of two successive bundles of said order; and executing said instructions on at least one said processor respecting said execution sequence.