Patent ID: 6598199
Filing Date: 2003-07-22
Classification: G06F

Abstract:
A server device comprising:a memory array having: a plurality of first narrow data path memory devices coupled to respective first narrow data path channels, at least one of the plurality of first narrow data path memory devices storing and transferring a respective mutually exclusive group of the bits of a data word over its respective first narrow data path channel in parallel with the other first narrow data path memory devices; and a second narrow data path memory device coupled to a respective second narrow data path channel, said second narrow data path memory device storing and transferring error correction data used in detecting and correcting errors in the data stored in said plurality of first narrow data path memory devices; and a memory interface chipset, said memory interface chipset generating the error correction data and controlling the transfer of data to and from said first narrow data path memory devices and the transfer of error correction data to and from said second narrow data path memory device.