Patent ID: 6947806
Filing Date: 2005-09-20
Classification: G05B

Abstract:
1. A method for determining yield loss of process steps for semiconductor wafers having a plurality of dies, the method comprising: inspecting the dies of the semiconductor wafers to determine a defect type and a defect count for each the defect type; electrical testing the dies of the semiconductor wafers to determine a fail die and a pass die, wherein each of the fail die having single defector or a plurality of defects is indicated as a hit; determining a defect calibrated factor for eliminating defect count excursions in a yield control table for the semiconductor wafers, wherein the defect calibrated factor is based on a difference between a ratio of the hits to a quantity of the dies with defects and a ratio of a quantity of the fail dies without defects to a quantity of the pass dies without defects; weighting a hit ratio with a function of the defect counts of the defect type, wherein the hit ratio is ratio of the hits of the defect type to the defect counts of the defect type; determining a yield impact contribution for each of the defect types, wherein the yield impact contribution is based on a calibrated ratio of the weighted hit ratio for each of the defect types to a sum of the weighted hit ratio for all of the defect types; determining a kill ratio for each of the defect types, wherein the kill ratio is based on a yield impact calibrated factor for the defect types, a total quantity of the defect counts, an average defect density of the defect types, and a die area; and determining a yield loss for each of the defect types, wherein the yield loss is based on the kill ratio for the defect type, the average defect density of the defect type, the die area, and the yield impact calibrated factor.