Patent ID: 6618299
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a default array block comprising a default array and sense amplifier; a row redundant array block, independent of the default array, comprising row redundant arrays for compensating for a deficiency in a row direction; a column redundant array block, independent of the default array, comprising column redundant arrays for compensating for deficiency in a column direction; a controller for generating a first control signal that is commonly applied to the default array, row redundant array block, and column redundant array block; and a redundant calculation circuit, responsive to the first control signal and an address signal, for generating a second control signal to the row and column redundant array blocks and to determine whether a redundant array is accessed, and for generating a third control signal to disable the sense amplifier of the default array during a redundant array access.