Patent ID: 9130549
Filing Date: 2015-09-08
Classification: H03K

Abstract:
1. A flip flop circuit comprising: a master latch comprising a master storage element, a first data leg, and a second data leg, the first and second data legs coupled to the master storage element, and clock selection logic coupled to the first and second data legs, the clock selection logic having a select input for selecting between the first and second data legs; and a slave latch coupled to the master latch, the slave latch including a slave storage element, wherein the clock selection logic comprises first and second NOR gates, the first and second NOR gates each sharing and receiving a single clock input, the first NOR gate receiving the select input, the second NOR gate receiving an inverse of the select input, the first NOR gate generating a first clock output which enables a first data output of the first data leg to a first node of the master storage element, and the second NOR gate generating a second clock output which enables a second data output of the second data leg to the first node of the master storage element.