Patent ID: 9219160
Filing Date: 2015-12-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first insulating layer; an oxide semiconductor layer over and in contact with the first insulating layer; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a gate electrode adjacent to the oxide semiconductor layer; and a second insulating layer over and in contact with the oxide semiconductor layer, wherein the first insulating layer includes silicon and oxygen, wherein the oxide semiconductor layer includes a first region in contact with the first insulating layer, wherein a thickness of the first region is 5 nm, wherein a concentration of silicon in the first region is lower than or equal to 1.0 at. %, wherein the second insulating layer includes silicon and oxygen, wherein the oxide semiconductor layer includes a second region in contact with the second insulating layer, wherein a thickness of the second region is 5 nm, wherein a concentration of silicon in the second region is higher than 1.0 at. %, wherein the oxide semiconductor layer includes a third region between the first region and the second region, and wherein a concentration of silicon in the third region is lower than the concentration of silicon in the first region.