Patent ID: 6917994
Filing Date: 2005-07-12
Classification: G06F

Abstract:
1. An interface for managing exchange of information between a bus system and a memory during reading, according to a communication protocol, the interface comprising: input/output terminals configured to be connected to said system bus; a protocol-decoding unit configured to receive from said input/output terminals commands and information for managing reading and configured to generate a wait-code enabling signal; a wait-state generating unit connected to said protocol-decoding unit and configured to supply wait codes to said first input/output terminals upon reception of said wait-code enabling signal; and a wait-state disabling circuit configured to generate an end-of-waiting control signal to be supplied to said wait-state generator upon reception of a read-state signal from said memory, said wait-state generating unit configured to supply an end-of-waiting code to said input/output terminals upon reception of said end-of-waiting control signal.