Patent ID: 6350658
Filing Date: 2002-02-26
Classification: H01L,Y10S

Abstract:
A method for realizing alignment marks on a semiconductor device during a manufacturing process including at least a Chemical Mechanical Polishing process step, the method including the following steps:forming alignment marks on a portion of a semiconductor substrate; masking said portion during a further deposition step of a first conductive layer covered by a first dielectric layer having a top surface; depositing a first conformal metal layer directly on said first dielectric layer and over said portion; depositing a second dielectric layer directly on said first metal layer, said second dielectric layer having a thickness; performing a CMP process step to planarize said second dielectric layer; wherein the first dielectric layer has a thickness high enough that the second dielectric layer covers said alignment marks portion under the level of the first dielectric top surface thereby preventing the CWP process step to planarize said portion.