Patent ID: 6781898
Filing Date: 2004-08-24
Classification: G11C

Abstract:
A process of repairing defects in linked list memories, said process comprising:selecting one of a group of said linked list memories and an additional memory, as a defect marking memory; detecting faults in rows of said defect marking memory; storing row addresses having at least one fault in defect address registers; when at least one fault in the rows of said defect marking memory is detected; detecting faults in rows of other linked list memories, where said other linked list memories are said linked list memories other than said defect marking memory; and storing a marking code for each row address of said other linked list memories in said defect marking memory, where a particular marking code indicates whether a particular row address has at least one fault; wherein said defect address registers and said defect marking memory are searched when addresses of the linked list memories are linked and row addresses indicated as having at least one fault are skipped in the linking process.