Patent ID: 6630378
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A method of forming stacked capacitor storage electrodes over a bit line extending over field effect transistors having been provided in a memory cell area of a semiconductor memory device, said method comprising the steps of:entirely forming a first insulation film which extends over and directly contacts doped sidewalls of gate electrodes of said field effect transistors and within apertures defined between said gate electrodes of said field effect transistors; planarization of a surface of said first insulation film so that said first insulation film has a first planarized surface, where said gate electrodes of said field effect transistors are buried in said first insulation film; electively forming at least a bit line contact hold in said first insulation film extending within said apertures defined between said gate electrodes to show a surface of one of source and drain regions of said field effect transistors; selectively forming at least a bit line which extends over said first planarized surface of said first insulation film and within said bit line contact hole; entirely forming a second insulation film which extends over said bit line and over said first insulation film; planarization of a surface of said second insulation film so that said second insulation film has a second planarized surface, where said bit line is buried in said second insulation film; selectively forming at least a stacked capacitor storage electrode contact hole in said first and second insulation films to show a surface of the opposite one of said source and drain regions of said field effect transistors; entirely forming a first conductive film which extends over said second planarized surface of said second insulation film and within said stacked capacitor storage electrode contact hole so that said first conductive film is made into contact with said opposite one of said source and drain regions; and subjecting said first conductive film to an anisotropic etching to selectively remove part of said first conductive film which extends only over said second planarized surface of said second insulation film except both in the vicinity of and within said stacked capacitor storage electrode contact hole to pattern stacked capacitor storage electrodes, wherein said step of forming said first insulation film further comprises the steps of: entirely forming a silicon oxide film which extends over said gate electrodes and within apertures defined between said gate electrodes; forming a silicon nitride film over said silicon oxide film; forming an impurity doped silicate glass film over said silicon nitride film; and planarization of a surface of said impurity doped silicate glass film.