Patent ID: 6061348
Filing Date: 2000-05-09
Classification: H04L

Abstract:
A data processing system comprising:a time division multiplexed (TDM) data bus;a plurality of system components coupled to the TDM data bus;a memory that stores a table of allocation entries, each allocation entry corresponding to a respective bandwidth unit (BU) in a transmission cycle of the TDM bus and each allocation entry indicating which one of the plurality of system components, if any, is to be allocated the corresponding bandwidth unit (BU), wherein each BU comprises a contiguous block of TDM timeslots; andan allocation control circuit coupled to the system components and the memory, the allocation control circuit accessing the allocation table and allocating BUs to the system components on a BU-by-BU basis so that the allocation control circuit operates at a slower speed than the TDM data bus.