Patent ID: 6747503
Filing Date: 2004-06-08
Classification: H03K

Abstract:
A transmission gate circuit comprising:a first transistor coupled between a first terminal and a second terminal; a second transistor coupled between the first terminal and the second terminal; and a control circuit configured to monitor voltages on the first terminal and on a first voltage source, wherein the control circuit is configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistor off during power off conditions, wherein the control circuit further comprises a will bias circuit configured to bias a first bias circuit, wherein the first bias circuit comprises: a third transistor and a fourth transistor coupled in parallel between a first control node and the gate of the first transistor; a fifth transistor coupled between the source of the third transistor and the first terminal, the fifth transistor having a gate coupled to the gate of the third transistor; a sixth transistor coupled between gate of the fourth transistor and the first terminal, the sixth transistor having a gate coupled to the first voltage source; a seventh transistor coupled between the gate of the fourth transistor and a second voltage source, the seventh transistor having a gate coupled to the first voltage source; and an eighth transistor coupled between the second voltage source and a common well node.