Patent ID: 9082710
Filing Date: 2015-07-14
Classification: H01L

Abstract:
1. A chip packaging substrate, comprising: a flexible substrate, having a first surface and a second surface opposite to the first surface, the first surface having a user area for a chip to be mounted thereon and a test pad area configured thereon, wherein the test pad area is adjacent to the user area, and the user area is defined by a cutting line which serves as a boundary between the user area and the test pad area; a plurality of test pads, configured in the test pad area and arranged in at least three rows, wherein the at least three rows are divided into an innermost row, at least one middle row, and an outermost row from nearest to farthest from the user area; and a plurality of leads, at least formed on the user area, wherein one end of each lead is electrically connected to the chip, the other end of each lead extends toward the test pad area and is connected to the corresponding test pad, and the leads have at least one first lead comprising: a first section, configured on the first surface, wherein a first end of the first section is electrically connected to the chip, and a second end opposite to the first end of the first section extends into the test pad area; and a second section, configured on the second surface and entirely situated within a range of test pad area projects on the second surface, wherein one end of the second section penetrates the flexible substrate to connect with the second end of the first section and the other end of the second section penetrates the flexible substrate to connect with the corresponding test pad which is arranged in the at least one middle row.