Patent ID: 6136646
Filing Date: 2000-10-24
Classification: H01L

Abstract:
A method for manufacturing dynamic random access memory (DRAM) capacitor, comprising the steps of:providing a substrate having a plurality of gate terminals thereon, a source region in the substrate on one side of the gate terminal and a drain region in the substrate on the other side of the gate terminal, a first insulation layer having a plurality of first plugs and a plurality of second plugs above the substrate, and each first plug is electrically connected to one of the source regions while each second plug is electrically connected to one of the drain regions;forming a second insulation layer over the substrate;forming a plurality of openings in the second insulation layer, each of the opening exposing the first plug;forming a planarized first conductive layer that fills the openings and covers the second insulation layer;forming a first buffer layer over the first conductive layer;forming a third insulation layer over the buffer layer;patterning the third insulation layer, the first buffer layer and the first conductive layer to form a plurality of stacked bit lines, each stacked bit line further includes a plurality of bit line contact located above and electrically connected to the first plug;forming a second buffer layer over the sidewalls of the first conductive layer;forming spacers on the sidewalls of the stacked bit lines such that spacers near the bit line contact of every pair of neighboring bit lines are linked;forming a planarized fourth insulation layer over the substrate;removing a portion of the fourth insulation layer and the second insulation layer to form a plurality of node contact openings that expose the respective second plugs, using third insulation layer, the spacers and the second plugs as stopping points;forming a conformal second insulation layer over the fourth insulation layer and the interior sidewalls of the node contact openings;removing a top layer of the second conductive layer lying above the fourth insulation layer;forming a dielectric layer over the second conductive layer; andforming a conformal third conductive layer over the dielectric layer and around the node contact openings above the fourth insulation layer.