Patent ID: 8988141
Filing Date: 2015-03-24
Classification: G05F,H02M

Abstract:
1. A port current control arrangement, comprising: a current source arranged to generate a reference current of at least one predetermined value; an on-chip reference resistor exhibiting a reference resistance, an end of said on-chip reference resistor coupled to said current source, said generated reference current arranged to produce a reference voltage across said on-chip reference resistor; an on-chip sense resistor exhibiting a sense resistance, a port current arranged to flow through said on-chip sense resistor and produce a sense voltage across said on-chip sense resistor, wherein the sense resistance exhibits a predetermined relationship with the reference resistance; a current control circuit, a first input of said current control circuit arranged to receive said produced reference voltage and a second input of said current control circuit arranged to receive said produced sense voltage, wherein said current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage; and a current measuring circuitry comprising: