Patent ID: 6118345
Filing Date: 2000-09-12
Classification: H03L,Y10S

Abstract:
A method of locking in a phase-locked loop (PLL) around a YIG-tuned oscillator whose frequency is guided into the PLL capture range by means of a frequency-control loop provided with a frequency discriminator, with the frequency-control loop being able to be switched off after the PLL has locked in, wherein:, with a predetermined change in frequency, the frequency of the YIG-tuned oscillator (1) is preset by a microprocessor (17) that changes the coil current (I.sub.SP) of the primary tuning coil (13) of the YIG-tuned oscillator (1) stepwise in an iterative capture routine until the capture range (.DELTA.FM) of the switched-on frequency-control loop, which is shifted with the coil current (I.sub.SP) includes the new operating frequency (f.sub.SOLL), whereupon the switched-on frequency-control loop pulls the oscillator frequency into the PLL capture range, and the PLL locks into the new operating frequency (f.sub.SOLL); and the microprocessor (17) interrupts the capture routine if the PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (f.sub.SOLL) has been locked in.