Patent ID: 6737308
Filing Date: 2004-05-18
Classification: H01L

Abstract:
A method of fabricating a semiconductor to provide LDD-type source/drain regions, comprising:forming at least one gate pattern in insulated relationship to a semiconductor substrate; implanting low-concentration impurity ions to form source/drain regions within the semiconductor substrate on both sides of the gate pattern; forming a second spacer layer conformal to the surface of the semiconductor substrate and the gate pattern, wherein the second spacer layer extends over the source/drain regions; forming a first spacer on the second spacer layer and along the sidewalls of the gate pattern; forming a high-concentration implant regions into the source/drain regions using at least the gate pattern and the first spacer as ion-implantation masks; removing the first spacer; after removing the first spacer, anisotropically etching the second spacer layer to expose portions of at least source/drain regions and to concurrently form second spacers on sidewalls of the gate pattern; and stacking and thermally treating a metal over the exposed portions of substrate as defined by the second spacers.