Patent ID: 8043921
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A method of removing silicon nitride over semiconductors for forming shallow junctions, comprising: forming a gate stack on a substrate having a semiconductor surface, wherein a surface dielectric layer is on said semiconductor surface; forming sidewall spacers along sidewalls of said gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions within active areas of said semiconductor surface, wherein at least one of said sidewall spacers, said LDD regions and said S/D regions include an exposed silicon nitride layer, wherein a residual portion of said surface dielectric layer remains after said forming said sidewall spacers; removing said residual portion of said surface dielectric layer; forming a protective dielectric layer directly on said LDD regions or said S/D regions that is 0.8 nm to 8 nm; ion implanting said LDD regions to form lightly doped sources/drains or said S/D regions to form sources/drains using said sidewall spacers as implant masks, and selectively removing said exposed silicon nitride layer, wherein said protective dielectric layer protects said LDD regions or said S/D regions from dopant loss due to etching during said selectively removing.