Patent ID: 6613633
Filing Date: 2003-09-02
Classification: H01L

Abstract:
A method for fabricating a high power semiconductor device comprising the steps of:forming a second conductive type well within a first conductive type semiconductor substrate; forming a first conductive type drift region within the well; forming a field oxide layer on a portion of the drift region other than an active region; forming a gate electrode on the well, on a junction where the drift region and the well are contacted, and on the field oxide layer; forming a first insulation layer on an upper surface and on a side surface of the gate electrode; forming a field plate on the field oxide layer including an edge portion and further extendedly on the gate electrode; simultaneously forming a drain aligning with the edge of the field plate within the drift region and a source region aligning with the edge of the gate electrode within the well; forming a second insulation layer on a whole resultant structure as obtained in the drain region and source region forming step; forming a contact hole by etching the second insulation layer so as for the source region and the drain region to be exposed, respectively; and forming a source electrode and a drain electrode by filling the contact hole with a conductive layer.