Patent ID: 8607006
Filing Date: 2013-12-10
Classification: G06F

Abstract:
1. Interconnect circuitry for a data processing apparatus, said interconnect circuitry being configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry, in response to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, is configured to not allow reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said barrier transaction request in said stream of transaction requests and to delay transmission along said at least one path of said at least some transaction requests while allowing other transaction requests to proceed; wherein said barrier transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained, said interconnect circuitry further comprising barrier management circuitry, wherein said control circuitry is configured to duplicate barrier transactions at a divergent node at an entry to a reconvergent region and to provide said duplicated barrier transactions with a reconvergent indicator; and said barrier management circuitry is responsive to detecting said duplicated barrier transactions exiting said reconvergent region to remove said reconvergent indicator and to merge at least some of said duplicated barrier transactions.