Patent ID: 7650545
Filing Date: 2010-01-19
Classification: G01R

Abstract:
1. A reconfigurable system-on-chip, comprising: a first core having an output line; a reconfigurable logic core (RLC) having an input line and an output line, with the output line of the first core being electrically coupled, via a first switch, to the input line of the RLC; a first multiplexer having first and second inputs and an output, wherein: a second core having an input line electrically coupled to the output of the first multiplexer; a second multiplexer having first and second inputs and an output, wherein: a configuration memory that controls (i) the first multiplexer to selectively couple the input line of the second core to one of the output line of the first core and the output line of the RLC and (ii) the second multiplexer to selectively couple the input line of the first core to one of the output line of the second core and the output line of the RLC.