Patent ID: 6475908
Filing Date: 2002-11-05
Classification: H01L

Abstract:
A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising:providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a gate dielectric layer overlying said semiconductor substrate in each of said active areas; depositing a metal layer overlying said gate dielectric layer; implanting silicon ions into said metal layer in said first active area to form an implanted metal layer and siliciding said implanted metal layer to form a metal silicide layer; and thereafter patterning said metal layer and said metal silicide layer to form a metal gate in said second active area and a metal silicide gate in said first active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.