Patent ID: 8097491
Filing Date: 2012-01-17
Classification: H01L

Abstract:
1. A fabrication method of a chip structure having a redistribution layer, comprising the steps of: providing a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; forming a first passivation layer on the active surface and the electrode pads and forming in the first passivation layer a plurality of first openings for exposing the electrode pads, respectively; forming the redistribution layer on the first passivation layer, wherein the redistribution layer has a plurality of wiring units, each of which comprises a conductive pad, a conductive via formed in one of the first openings, and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and forming a second passivation layer to cover the first passivation layer and the redistribution layer in a manner that the second passiviation layer is filled in the at least a first through opening of the conductive trace of each of the wiring units, and forming a plurality of second openings in the second passivation layer for exposing the conductive pad of each of the wiring units, wherein the step of forming the redistribution layer further comprises the steps of: