Patent ID: 6829737
Filing Date: 2004-12-07
Classification: G01R,G11C

Abstract:
An integrated circuit comprising:at least one send/receive location configured to receive a test signal comprising at least one bit of data and to transmit in response thereto a signal comprising at least one bit of data; a comparator circuit configured to perform a comparison between the signal transmitted by the at least one send/receive location in response to the test signal and a signal expected to be transmitted by the at least one send/receive location in response to the test signal if the integrated circuit is functioning correctly; a test latch connected to the comparator circuit and configured to be set to a latched value representing a result of the comparison; at least one nonvolatile memory element configured to store at least one of at least two different logic states; and a set logic circuit configured to receive as inputs the latched value and a set signal and configured to set the at least one nonvolatile memory element to the at least one of the at least two different logic states when the set signal is received and the test latch is set to a predetermined latched value.