Patent ID: 6762611
Filing Date: 2004-07-13
Classification: G01R,G11C

Abstract:
A probe card configuration for testing a plurality of integrated circuits in parallel, the probe card configuration comprising:a test system having electrical signal lines; a carrier board for receiving said electrical signal lines of said test system, said carrier board defining a plane; a carrier mounted to said carrier board forming an interspace between said carrier and said carrier board; contact-making needles for producing electrical connections with contact areas on the integrate circuits to be tested, said contact-making needles for connection to said electrical signal lines of said test system to produce signal paths between said test system and the integrated circuits to be tested, said contact-making needle being disposed on said carrier; and a plurality of active modules configured on said carrier board, each one of said plurality of said active modules being assigned to one of the integrated circuits to be tested in parallel, each one of said plurality of said active modules being inserted into ones of the signal paths that are between said test system and the assigned one of the integrated circuits to be tested; at least two of said plurality of said active modules being disposed within said interspace overlapping each other vertically, at least one of said plurality of said active modules being disposed on said carrier.