Patent ID: 8294839
Filing Date: 2012-10-23
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel, comprising: an insulating substrate; a gate line disposed on the insulating substrate; a data wire comprising a drain electrode and a data line disposed on the gate insulating layer and crossing the gate line; a passivation layer covering the gate line and the data line and a pixel electrode disposed on the passivation layer; wherein the gate insulating layer has a first opening, and the passivation layer has a second opening and a contact hole, the first opening and the second opening being disposed over a first area of the insulating substrate and the contact hole being disposed over a second area of the insulating substrate that is different from the first area of the insulating substrate, wherein the second opening exposes the first opening, wherein the first opening and the second opening are located in an area ranging from an edge of the pixel electrode to an edge of the gate line or the data line adjacent to the edge of the pixel electrode, and wherein the contact hole exposes a portion of the drain electrode.