Patent ID: 6235604
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method for manufacturing a capacitor applied to a memory unit including a substrate having a dielectric layer formed thereon, and an etching stop layer formed on said dielectric layer, comprising steps of:a) forming a sacrificial layer over said etching stop layer;b) partially removing said sacrificial layer, said etching stop layer, and said dielectric layer to form a contact window;c) forming a first conducting layer over said sacrificial layer and in said contact window;d) partially removing said first conducting layer and said sacrificial layer using anisotropic etching to expose a portion of said sacrificial layer and retain a portion of said first conducting layer;e) forming a second conducting layer over top surfaces and sidewalls of said portion of said first conducting layer and said portion of said sacrificial layer; andf) partially removing said second conducting layer while retaining a portion of said second conducting layer alongside said portion of said first conducting layer and said portion of said sacrificial layer such that said portion of said first conducting layer and said portion of said second conducting layer alongside said portion of said first conducting layer form a flat upper surface, and removing said portion of said sacrificial layer to expose said etching stop layer, wherein said portion of said first conducting layer and said portion of said second conducting layer serve as a capacitor plate.