Patent ID: 7484138
Filing Date: 2009-01-27
Classification: G11C

Abstract:
1. A system for improving reliability of a memory device, comprising: one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows; at least one built-in-self-test (BIST) unit coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard; and at least one built-in-self-repair (BISR) unit coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard, wherein the BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.