Patent ID: 7268030
Filing Date: 2007-09-11
Classification: H01L

Abstract:
1. A method of forming a semiconductor construction, comprising: providing a first semiconductor material, the first semiconductor material having at least one p-type doped region therein; forming a transistor gate over the first semiconductor material; forming n-type doped source/drain regions extending downwardly into the first semiconductor material from adjacent the gate; forming a second semiconductive semiconductor material over the gate; the second semiconductor material having at least one n-type doped region and having p-type doped source/drain regions therein; the p-type doped source/drain regions extending upwardly from adjacent the gate and into the second semiconductor material, the p-type doped source/drain regions not extending entirely through the second semiconductor material; the n-type doped source/drain regions and transistor gate together forming an NFET device, and the p-type doped source/drain regions and transistor gate together forming a PFET device stacked over the NFET device; and forming an n-type doped third semiconductor material extending from one of the n-type source/drain regions to an n-type doped region of the second semiconductive material.