Patent ID: 6021421
Filing Date: 2000-02-01
Classification: G06F

Abstract:
In a digital signal processing device of the type including an execution section having components including(i) at least one processor,(ii) at least one arithmetic logic unit,(iii) a first memory for holding an enhanced set of execution instructions,(iv) a second memory for holding data,(v) a clock generator outputting clock signals to the processor and the arithmetic logic unit, and(vi) at least one computational unit, being controllable by the instructions from the processor, having a computational unit input port for receiving data and a computational unit output port for outputting data;the improvement comprising enhanced digital signal (EDSP) processing comprising:(a) all of the components of the execution section are included in a single-die integrated circuit;(b) the single-die integrated circuit includes at least one internal communication bus interconnecting the components of the execution section for exchange of data or instructions therebetween;(c) the computational unit comprises hardware elements including at least one multiplexer, at least one IIR filter, and at least one FIR filter, and interconnections among the hardware elements, whereby the computational unit is configurable into various specific configurations of the computational unit hardware elements, the computational unit being configurable via instructions from the processor;(d) the first memory includes at least one first execution instruction causing the processor to run the execution section in a correlator processing mode whereinthe computational unit accepts data from at least one of the components of the execution section, correlates the data, and sends the data to at least one of the components of the execution section via the internal communication bus;(e) the first memory includes at least one second execution instruction causing the processor to run the execution section in a filter processing mode whereinthe computational unit acts as a stand-alone filter processing input data received from the input port and outputting processed data from the output port;(f) whereby the computational unit is switchable between the correlator processing mode and the filter processing mode according to the instructions from the processor.