Patent ID: 6627947
Filing Date: 2003-09-30
Classification: G11C,H01L

Abstract:
A memory cell array, comprising:an array control gate region; a first two-transistor EEPROM programming cell comprising: a first transistor having a first active region source coupled to a first product term ground voltage, a control gate coupled to a first word line voltage, and a second active region; a second transistor sharing said second active region with said first transistor and including a third active region coupled to a first product term voltage; a first common floating gate having a first portion overlying a channel between said second active region and said third active region, and a second portion overlying said array control gate region; a second two-transistor EEPROM cell sharing said array control gate region and including: a third transistor having a fourth active region coupled to a second product term ground voltage, a control gate coupled to a second word line voltage, and a fifth active region; and a fourth transistor sharing said fifth active region with said third transistor and further having a sixth active region coupled to a second product term voltage.