Patent ID: 6378047
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A set-associative cache memory system for use in communication with a computer processor and main memory and adapted to efficiently invalidate data stored in the cache data memory of the system comprising:a cache data memory; a cache tag memory configured to store the address and status of all data stored in said cache data memory; a counter in communication with said cache tag memory for serially outputting all the addresses to be invalidated in said cache tag memory; a plurality of parallel first logic circuits in communication with said cache tag memory and configured to generate a signal indicating whether each selected invalidate address from said counter contains modified and valid data; a priority encoder responsive to said plurality of first logic circuits for generating an encode signal used for selecting an address to act upon first among said all the addresses; a multiplexer responsive to said encode signal for selecting on the address to be output as a write back address to said main memory; a decode circuit for decoding said encode signal and outputting a decoded signal; and a synchronization circuit in communication with said cache tag memory responsive to an invalidate request for generating Write Enable signal that allows invalidation of each address within the cache tag memory.