Patent ID: 7212434
Filing Date: 2007-05-01
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: memory cells which include memory cell transistors, each of the transistors having a floating gate and a control gate; a memory cell array in which the memory cells are arranged in a matrix; bit lines each of which connects in common the drains of the memory cell transistors in a same column electrically; word lines each of which connects in common the control gates of the memory cell transistors in a same row; latch circuits which are provided for the bit lines in a one-to-one correspondence and which hold write data; a voltage generator which generates a negative voltage and a positive voltage; first row decoders which are provided for the word lines in a one-to-one correspondence and which apply the positive voltage generated by the voltage generator to the word lines in a write operation and in an erase operation; second row decoders which are provided for the word lines in a one-to-one correspondence and which apply the negative voltage generated by the voltage generator to the word lines in a write operation and in an erase operation; first isolating transistors which are provided for the word lines in a one-to-one correspondence and which switch between the first row decoders and the word lines; second isolating transistors which are provided for the word lines in a one-to-one correspondence and which switch between the second row decoders and the word lines; a first well region of a first conductivity type which is formed at the surface of a semiconductor substrate; a second well region of the first conductivity type which is formed at the surface of the semiconductor substrate and which is isolated from the first well region; a third well region of a second conductivity type which is formed at the surface of the first well region; and a fourth well region of the second conductivity type which is formed at the surface of the second well region, wherein the first isolating transistor is a MOS transistor of the second conductivity type formed on the first well region, a part of the first row decoder is formed on the first well region, the second isolating transistor is a MOS transistor of the first conductivity type formed on the fourth well region, a part of the second row decoder is formed on the fourth well region, and the memory cell array is formed on the third well region.