Patent ID: 7825887
Filing Date: 2010-11-02
Classification: G09G,G11C

Abstract:
1. A gate driver comprising: a plurality of stages for supplying input clock pulses to associated gate lines of a liquid crystal panel, respectively; a gate-driving integrated circuit for dividing the stages into m stage groups each including n stages, and supplying n phase-different clock pulses to each of the stage groups; and an output controller that controls which of the plurality of stage groups generate an output signal, wherein m is a natural number greater than or equal to 2, wherein n is a natural number greater than or equal to 2, wherein the output controller controls the plurality of stages such that the stages sequentially output clock pulses in an order from an uppermost stream of one of the stage groups to a lowermost stream of one of the stage groups; wherein the output controller outputs m phase-different control voltages, and supplies each of the control voltages to the stages of an associated one of the stage groups, to control outputs from the plurality of stages; wherein each control voltage is maintained in a high state for an overall output enable period of the stages of the stage group receiving the control voltage, and is maintained in a low state for a period other than the output enable period; wherein: a k-th one of the clock pulses supplied to each stage group is supplied to an input terminal of a k-th one of the stages included in the stage group, and to an enable terminal of a “k+1”-th one of the stages included in the stage group; a last clock pulse supplied to an input terminal of a last one of the stages in each stage group is also supplied to an enable terminal of a first one of the stages in the stage group next to the stage group including the last stage receiving the last clock pulse; and a start pulse is externally supplied to an enable terminal of a first one of the stages in a first one of the stage groups, wherein k is a natural number greater than or equal to 2; wherein the control voltage supplied to the stages in an associated one of the stage groups is maintained in a high state for enable periods, during which clock pulses are supplied to enable terminals of the stages in the associated stage group, respectively, and for an enable period, during which a clock pulse is supplied to an enable terminal of a first one of the stages in the stage group next to the associated stage group; and wherein the control voltage is maintained in a low state for a period other than the enable periods.