Patent ID: 8332683
Filing Date: 2012-12-11
Classification: G06F,G06T,G09G,G11C

Abstract:
1. A data processing device disposed on a single chip, comprising: a data processing unit adapted to access to an external volatile memory in synchronism with a clock signal and adapted to access to an external non-volatile memory, and adapted to provide control information; and a bus control unit adapted to provide address signals to address terminals of the external volatile memory and adapted to provide data signals to data terminals of the external volatile memory, and adapted to provide first control signals to terminals of the external volatile memory in synchronism with the clock signal, and adapted to provide second control signals to terminals of the external non-volatile memory, wherein the bus control unit is adapted to control an access to the external volatile memory depending on the control information from the data processing unit, and wherein the bus control unit is adapted to decide an access address for the non-volatile memory, and the bus control unit makes a memory cycle of the access to the external non-volatile memory longer than to the external volatile memory.