Patent ID: 6180489
Filing Date: 2001-01-30
Classification: H01L

Abstract:
A method of planarizing the surface of an integrated circuit device comprising:depositing a first nitride layer on the surface of a semiconductor substrate;etching a plurality of isolation trenches through said first nitride layer into said semiconductor substrate wherein there is at least one wide trench and at least one narrow trench;depositing a first oxide layer over said first nitride layer and within said isolation trenches wherein said first oxide layer fills said isolation trenches;depositing a capping nitride layer overlying said first oxide layer;depositing a second oxide layer overlying said capping nitride layer;polishing away said second oxide layer until said first oxide layer is exposed wherein said second oxide layer and said capping nitride layer are left only within said wide trench;dry etching away said first and second oxide layers with an etch stop on said capping nitride layer within said wide trench and said first nitride layer;thereafter overetching said first oxide layer to leave the top surface of said first oxide layer just above the bottom surface of said first nitride layer and said capping nitride layer within said wide trench; andremoving said capping nitride layer and said first nitride layer completing said planarization of said surface of said integrated circuit device.