Patent ID: 6111325
Filing Date: 2000-08-29
Classification: H01L,Y10S

Abstract:
A gettering region within an Si semiconductor material wafer comprising:a first region comprising a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type;a second-type conductivity implant region entirely contained within the first region, the second-type conductivity implant region comprising a second-type conductivity enhancing dopant, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant;a silicon implant region having a peak silicon implant concentration depth located within the second-type conductivity implant region, the silicon implant region defining a metals gettering damage region entirely contained within the second-type conductivity implant region; andan electrical bias applied to the second-type conductivity implant region relative to the first region.