Patent ID: 6759910
Filing Date: 2004-07-06
Classification: H03L

Abstract:
A phase locked loop (PLL) frequency synthesizer comprising:a primary phase locked loop circuit having a voltage controlled oscillator (VCO) circuit and a programmable divider circuit for establishing a voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency; a secondary phase locked loop circuit operatively connected to the primary phased lock loop circuit, and operative for receiving and isolating an external reference signal used for the primary phase locked loop circuit, and including an oscillator for generating a voltage controlled, clean reference signal wherein said secondary phase locked loop circuit filters and synchronizes the clean reference signal with the external reference signal for producing the reference signal output to the primary phase locked loop circuit; a printed wiring board on which the primary and secondary phase locked loops are positioned; a plurality of isolation vias that isolate any circuit component of the primary and secondary phase locked loop circuits; and a housing that is matched as to its coefficient of thermal expansion with the printed wiring board and comprising a support member on which the printed wiring board is mounted.