Patent ID: 6544888
Filing Date: 2003-04-08
Classification: H01L

Abstract:
A method of fabricating an integrated circuit device, having at least one type of semiconductor device and at least one gate contact contained therein, said method comprising:providing a plurality of raised contact windows and at least one gate connector in a semiconductor substrate; creating contact holes in said substrate by integrated etching of said substrate; amorphizing a surface of said substrate, including said contact windows; selectively depositing hemispherical grain layers within and on the bottoms of said amorphized contact windows; forming a salicidation layer on said amophized contact windows by salicidation with tungsten; implanting ions in said contact holes to optimize doping conditions for a type of semiconductor device being fabricated at said contact holes; annealing said contact holes, whereby shallow junction contacts with low contact resistance and high doping concentration are formed in said contact holes; performing a dedicated gate electrode etch and stop on top of a metal gate; and performing a metal line process.