Patent ID: 7564259
Filing Date: 2009-07-21
Classification: H03K

Abstract:
1. A digital circuit having a dynamically controllable power consumption level, comprising: a plurality of interconnected digital logic blocks; a first power supply distribution bus for supplying a first power supply voltage; a second power supply distribution bus for supplying a second power supply voltage having a magnitude lower than that of said first power supply voltage; a plurality of selectors having at least one switching circuit corresponding to each of said plurality of digital logic blocks; and a control circuit having outputs coupled to each of said switching circuits for setting said dynamically controllable power consumption level by setting a state of said plurality of selectors, wherein said plurality of digital logic blocks comprises a plurality of redundant pairs of digital logic blocks, one of each pair connected to said first power supply distribution bus and the other connected to said second power supply distribution bus, and wherein said plurality of selectors includes a selector corresponding to each redundant pair for selecting between an outputs of a first and second one of said redundant pair, and wherein said control circuit adjusts said dynamically selectable level of power consumption by setting combinations of active digital logic blocks by selecting one active digital logic block from each of said redundant pairs.