Patent ID: 8980705
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method for fabricating a MOS transistor, comprising: providing a semiconductor substrate; forming a ploy silicon dummy gate structure having a high-K gate dielectric layer on the semiconductor substrate, a high-K gate dielectric protection layer containing nitrogen on the high-K gate dielectric layer and a poly silicon dummy gate on the high-K gate dielectric protection layer on the semiconductor substrate; forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure; removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen; performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate; and forming a metal gate structure in the trench.