Patent ID: 6160268
Filing Date: 2000-12-12
Classification: G02F,H01L

Abstract:
A semiconductor device including at least a bottom-gate n-channel TFT, comprising:a gate electrode being formed on an insulating surface;a semiconductor island being formed over the gate electrode having a gate insulating film interposed therebetween;a source region, a drain region and a channel forming region being formed between the source and drain region, each of the source, drain and channel forming regions being formed in the semiconductor island;a buffer layer being formed over the semiconductor island,wherein an impurity element is intentionally introduced into the channel forming region, said impurity element being for controlling a threshold voltage of the bottom-gate n-channel TFT,wherein a first portion of the channel forming region is defined in the vicinity of a surface on a side farther from the insulating surface, while a second portion of the channel region is defined in the vicinity of an interface between the channel forming region and the gate insulating film,wherein a concentration of the impurity element in the channel forming region decreases from the first portion to the second portion of the channel forming region.