Patent ID: 8809968
Filing Date: 2014-08-19
Classification: H01L

Abstract:
1. A semiconductor layer structure comprising a substrate, a buffer layer deposited onto the substrate, and an active semiconductor layer stack deposited onto the buffer layer, wherein the active semiconductor layer stack includes a layer formed as a channel by depositing a barrier layer, and contacts deposited onto the barrier layer, wherein the semiconductor layer structure is designed to permanently or temporarily prevent or limit, at least in a first direction, a lateral flow of current from one of the contacts to one of the other contacts through the layer if a potential of the one of the contacts deviates from another potential of the other of the contacts by less than a breakdown voltage threshold, wherein; a potential of the substrate corresponds to the other potential, and in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating argon ions that are selectively implanted into the substrate such that the isolating argon ions are in just one region of the substrate said just one region of the substrate with isolating argon ions implanted being laterally adjacent to a substrate region without isolating argon, wherein charge can dissipate from the one contact through the buffer layer towards said substrate region without isolating argon ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating argon ions is located underneath the one contact.