Patent ID: 6242974
Filing Date: 2001-06-05
Classification: G01K

Abstract:
A circuit comprisingan op-amp having at least two input terminals and at least one output terminal, said op-amp exhibiting a characteristic input offset voltage, V.sub.OSI, at said input terminals,at least one feedback network having an input terminal and an output terminal, said input terminal of each said feedback network connected to a respective output terminal of said op-amp,a self-calibration circuit having at least two input terminals and two output terminals, said self-calibration circuit receiving input signals and having at least one input terminal connected to an output terminal of at least one of said feedback networks, said output terminals of said self-calibration circuit being connected to respective ones of said input terminals of said op-amp, said self-calibration network comprising a substantially similar switched capacitor network connected between each of said input terminals of said self-calibration network and said inputs of said op-amp for sampling said V.sub.OSI during an auto-zero mode of operation and for storing said sampled V.sub.OSI for use in nulling said V.sub.OSI at said inputs of said op-amp during a normal mode of operation.