Patent ID: 6694395
Filing Date: 2004-02-17
Classification: G06F

Abstract:
An information processing device allowing continued operation of a plurality of input/output processors even if a common control unit controlling said plurality of input/output processors becomes inactive, comprising:a plurality of input/output processors, wherein each of said plurality of input/output processors controls a plurality of input/output devices; at least two common control units, wherein each of said at least two common control units controls some or all of said plurality of input/output processors; and a system control unit controlling an instruction processor, a main memory, and said at least two common control units; wherein each of said input/output processor includes a first information path to connect to a first common control unit of said at least two common control units and a second information path to connect to a second common control unit of said at least two common control units, and wherein during normal operation said plurality of input/output processors are divided into a first input/output processors group controlled by said first common control unit via said first information path and a second input/output processors group controlled by said second common control unit via said second information path, and when said first common control unit becomes inactive said first input/output processors group are controlled by said second common control unit via said second information path.