Patent ID: 7417452
Filing Date: 2008-08-26
Classification: H03K

Abstract:
1. An integrated circuit comprising: an input/output (IO) bank comprising a first buffer coupled to a first pin and a second buffer coupled to a second pin, wherein a first on-chip termination (OCT) calibration code controls on-chip termination impedances in the first and the second buffers, and the IO bank is configured to adjust the first OCT calibration code provided to the first buffer independently of the first OCT calibration code provided to the second buffer to generate different on-chip termination impedances in the first and the second buffers, wherein the first OCT calibration code controls the on-chip termination impedances of pull-up transistors in the first and the second buffers, a second on-chip termination calibration code controls on-chip termination impedances of pull-down transistors in the first and the second buffers, and the IO bank is configured to adjust the second OCT calibration code provided to the first buffer independently of the second OCT calibration code provided to the second buffer.