Patent ID: 6216220
Filing Date: 2001-04-10
Classification: G06F

Abstract:
A method for processing instructions in a data processing system having an active thread block, a ready thread block, and a waiting thread block, and an instruction execution block, so as to contemporaneously process a plurality of active threads, the method comprising:combining instructions issued from plural active threads into one new instruction group, each active thread having a plurality of instructions, and the issued instructions being used as subinstructions in the combined one instruction group;processing the combined one new instruction by the instruction execution block, and tracing contexts relating to active threads which provide the respective subinstructions by using multiple program counters; andcontext-switching only the context of a thread among the active threads which provides a long latency subinstruction among the subinstructions to be executed, the context switching being performed by the program counter tracing said context and comprising moving a thread having a long latency subinstruction to the waiting thread block, followed by the replacement of the long latency subinstruction by an instruction from another thread in the ready thread block into said combined instruction group to be processed by the instruction execution block.