Patent ID: 6891900
Filing Date: 2005-05-10
Classification: H04L

Abstract:
1. A demodulating circuit for demodulating a pulse signal including runs of identical ‘1’ or ‘0’ symbols, comprising: a differentiating circuit for detecting voltage changes at rising and falling transitions of the pulse signal and outputting a differentiated signal responsive to the voltage changes; and a hysteresis comparator for comparing the differentiated signal with a first reference voltage according to a predetermined upper threshold voltage higher than the first reference voltage and a predetermined lower threshold voltage lower than the first reference voltage, thereby generating a demodulated signal that maintains a first logic level when the differentiated signal is above the upper threshold voltage, maintains a second logic level when the differentiated signal is below the lower threshold level, and maintains an existing one of the first and second logic levels without changing when the differentiate voltage is between the upper threshold voltage and the lower threshold voltage, wherein: the hysteresis comparator comprises a comparator element having an inverting input terminal for receiving the first reference voltage, a non-inverting input terminal for receiving the differentiated signal, and an output terminal for output of the demodulated signal, a first resistance element coupling the output terminal of the comparator element to the non-inverting input terminal of the comparator element, and a second resistance element coupling the first reference voltage to the non-inverting input terminal of the comparator element; and the differentiating circuit comprises a differentiating capacitor coupling the pulse signal to the non-inverting input terminal of the comparator element, and a compound resistance for charging and discharging the differentiating capacitor, the compound resistance including the first resistance element and the second resistance element.