Patent ID: 6765826
Filing Date: 2004-07-20
Classification: G06F,G11C

Abstract:
An electronic assembly, in combination with a target system and a test location, the electronic assembly comprising:at least one non-volatile memory device having a write protection feature and a controllable write protection terminal for activating and deactivating the write protection feature; at least one additional semiconductor device; a terminal device including at least one pair of supply terminals for supplying said non-volatile memory device and at least one third supply terminal for supplying said additional semiconductor device when the electronic assembly is being operated in the target system; a first signal path; and a switching configuration connecting said write protect terminal of said non-volatile memory device to said third supply terminal over said first signal path; said third supply terminal providing a potential for activating the write protection feature when the electronic assembly is being operated in the target system; and the write protection feature being deactivatable when the electronic assembly is being operated at the test location.