Patent ID: 6507800
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A method for classifying a semiconductor wafer according to a failure signature, the method comprising the steps of:providing a plurality of wafers having circuit patterns formed thereon; testing each wafer of said plurality of wafers to obtain a set of training test values, said set of training test values indicative of the characteristics of the failure signature; selecting a first group of wafers from said plurality of wafers, each wafer of said first group of wafers having the failure signature; generating a first mean value vector from said set of training test values associated with said first group of wafers; selecting a second group of wafers from said plurality of wafers, each wafer of said second group of wafers not having the failure signature; generating a second mean value vector from said set of training test values associated with said second group of wafers; generating a variance matrix from said set of training test values; generating a set of coefficients for a discriminant function from said first mean value vector, said second mean value vector, and said variance matrix; providing the semiconductor wafer; testing the semiconductor wafer to obtain a set of test values; generating a discriminant value by using said set of test values as input to said discriminant function; and identifying the semiconductor wafer as having the failure signature when said discriminant value is not less than a threshold value.