Patent ID: 7298640
Filing Date: 2007-11-20
Classification: G11C,H01L

Abstract:
1. An electronic memory comprising a plurality of memory cells, each memory cell including: a switch; a resistive memory element connected in parallel with said switch, said resistive memory element capable of existing in one of a plurality of resistive states, each resistive state representing a different data state; and a memory write and read circuit selectably coupled to said resistive memory element and capable of writing a data state to said resistive memory element and reading the data state; wherein said plurality of memory cells are arranged in a row/column configuration, each row/column configuration including a plurality of said resistive memory elements connected in series and a plurality of said switches connected in series, each of said switches associated with one of said resistive memory elements; and said memory further comprising a source of a programming voltage and a row/column selection transistor connected between said source of the programming voltage and said row/column of memory cells.