Patent ID: 7314815
Filing Date: 2008-01-01
Classification: G11C,H01L

Abstract:
1. A method of fabricating a semiconductor structure, comprising: providing a first electrically conductive type semiconductor substrate; forming a second electrically conductive type doping region, a first electrically conductive type second doping layer, a first electrically conductive type first doping layer and a second electrically conductive type first doping layer sequentially in the first electrically conductive type semiconductor substrate; patterning the first electrically conductive type semiconductor substrate to form a linear-shape first electrically conductive type second doping layer, a block-shape first electrically conductive type first doping layer and a block-shape second electrically conductive type first doping layer; performing an etching operation to produce a sharp edge at the top section of the block-shape second electrically conductive type first doping layer; forming an anti-fuse layer over the first electrically conductive type semiconductor substrate; forming an etching stop layer over the anti-fuse layer; forming an inter-layer insulating layer over the etching stop layer; patterning the inter-layer insulating layer to form a trench that exposes a portion of the etching stop layer and crosses over the linear-shape second electrically conductive type first doping layer; removing etching stop layer exposed by the trench; and forming a electrically conductive layer inside the trench.