Patent ID: 7653764
Filing Date: 2010-01-26
Classification: G06F

Abstract:
1. A fault-tolerant computer comprising: a pair of duplicate systems; each of said duplicate systems comprising: a Central Processing Unit (CPU) subsystem for controlling access to a CPU and a storage unit; and an Input Output (IO) subsystem for controlling data which are input to said IO subsystem from an external circuit and data output from said IO subsystem to the external circuit; wherein said CPU subsystems of the duplicate systems operate identically to each other based on a common internal clock according to a lock-step system, and said IO subsystems of the duplicate systems are connected to each other through a cross link; wherein said CPU subsystem receives data sent from said IO subsystem, and when the amount of the received data reaches a first threshold value, said CPU subsystem sends a first signal to said IO subsystem, and when the amount of the received data reaches a second threshold value greater than said first threshold value, said CPU subsystem sends a second signal to said IO subsystem; said IO subsystem comprising: an IO interface (IO I/F) controller to stop sending data to said CPU subsystem when said IO I/F controller receives said first signal and said second signal; and a flow controller for sending said second signal to the IO I/F controller of the paired IO subsystem through said cross link after said flow controller receives said second signal.