Patent ID: 6426243
Filing Date: 2002-07-30
Classification: H01L

Abstract:
A method of forming dynamic random access memory circuitry comprising:forming an array of word lines over a semiconductive substrate; forming a substantially planar dielectric well forming layer over the word lines; etching at least one well into the well forming layer which defines a dynamic random access memory array area within the well and dynamic random access peripheral circuitry area laterally outward of well, the well having a substantially planar base; depositing a dielectric etch stop layer over the well forming layer laterally outward of and to within the well to less than completely fill the well; forming a dielectric storage node forming layer over the etch stop layer laterally outward of and to within the well to overfill the well; etching an array of capacitor storage node openings within the well through the storage node forming layer, through the etch stop layer and into the well forming layer over storage node contact locations; depositing a capacitor storage node layer over the storage node forming layer to within the capacitor storage node openings to less than completely fill the capacitor storage node openings; removing the capacitor storage node layer from outwardly of the storage node forming layer effective to form capacitor storage node containers within the capacitor storage node openings in electrical connection with the storage node contact locations, the capacitor storage node containers having top surfaces received elevationally proximate an outermost surface of the dielectric etch stop layer; after forming the capacitor storage node containers, etching the capacitor storage node forming layer using the dielectric etch stop layer as an etch stop and exposing lateral outer container surface area of the capacitor containers; forming a capacitor dielectric layer and a cell electrode layer over the capacitor storage node containers including the outer container surface area of the capacitor containers; and forming the dynamic random access peripheral memory circuitry laterally outward of the well.