Patent ID: 6201298
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A semiconductor device comprising:a single-layer wiring tape including a plurality of external terminals disposed upon one surface thereof and an integrated circuit element adhered to the other surface thereof;a printed circuit board having a planar metal pattern, and serving as a frame member adhered to said wiring tape to surround at least a side face of said integrated circuit element; andwiring patterns disposed upon said wiring tape being formed to connect at least one of either a power electrode or a ground electrode on said integrated circuit element to said planar metal pattern of the printed circuit board, and to connect said planar metal pattern of the printed circuit board to respectively at least one of either an external power terminal or an external ground terminal on said wiring tape; andsaid wiring patterns of said wiring tape further connecting a signal electrode on said integrated circuit to an external signal terminal of said plurality of external terminals on said wiring tape.