Patent ID: 7239651
Filing Date: 2007-07-03
Classification: H03L,H04J

Abstract:
1. A desynchronizer for a SONET demapper, comprising: a) a data FIFO for storing data for a plurality of channels; b) a plurality of digital phase locked loops coupled to said FIFO for reading data out of said FIFO, said plurality of digital phase locked loops being implemented with shared circuitry for generating FIFO read addresses and a plurality of divide-by counters for outputting data, said divide-by counters selectively coupled, one at a time, to said shared circuitry in response to a clock signal, wherein said read addresses include a used tributary unit which allows for multicasting; c) a depth calculator for determining a FIFO depth of each of said channels, said depth calculator being selectively coupled, one at a time, to said divide-by counters in response to a clock signal, wherein said depth calculator includes a first subtracter coupled to a read pointer and an effective write pointer, wherein said effective write pointer is the difference between a write pointer and a leak depth.