Patent ID: 6449692
Filing Date: 2002-09-10
Classification: G06F,G09G

Abstract:
A computer system, comprising:a central processing unit; a memory hierarchy, comprising: a first cache memory operable to store non-pixel information, wherein the non-pixel information is accessible for processing by the central processing unit; and a second cache memory, higher in the memory hierarchy than the first cache memory, and having a number of storage locations and operable to store non-pixel information and pixel data; cache control circuitry for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data; a video controller for operating under a plurality of video modes; and wherein the cache control circuitry for dynamically apportioning the number of storage locations dynamically apportions the number of storage locations in response to a currently selected one of the plurality of video modes.