Patent ID: 9183951
Filing Date: 2015-11-10
Classification: G11C

Abstract:
1. A resistance change memory comprising: a memory cell array in which memory cells comprising resistive storage elements and cell transistors are arrayed, the memory cells being connected to bit lines and source lines, the cell transistors being connected to word lines; an address counter which outputs an address signal to select a bit line, a source line, and a word line; a word line driver which drives the word line; a power supply circuit which generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation; and a write driver configured to apply the stress voltage to the memory cells connected between the bit lines and the source lines, wherein the address counter selects a first word line from the word lines, and the word line driver drives the first word line, the address counter selects a first bit line and a first source line from the bit lines and the source lines, the write driver applies the stress voltage across the first bit line and the first source line to pass a stress current through the memory cell selected by the first word line, the address counter is incremented to select a second word line from the word lines, and the word line driver drives the second word line, the address counter is incremented to select a second bit line and a second source line from the bit lines and the source lines, and the write driver applies the stress voltage across the second bit line and the second source line to pass a stress current through the memory cell selected by the second word line.