Patent ID: 7228470
Filing Date: 2007-06-05
Classification: G11C

Abstract:
1. A semiconductor testing circuit for performing a test of a semiconductor storage device, comprising: a plurality of counters which designate a plurality of different portions of an address signal used in at least one of a write operation and a read operation of the semiconductor storage device, said at least one of a write operation and a read operation comprising the test of the semiconductor storage device, each of the plurality of different portions comprising one bit or a plurality of successive bits; and a switching circuit which selectively outputs counter-control signals for individually controlling operations of said plurality of counters, where each of said counter-control signals is one of a common counter-control signal commonly used for said plurality of counters and the most significant bit of one of said plurality of portions outputted from a first one of said plurality of counters other than a second one of said plurality of counters for which said each of said counter-control signals is outputted.