Patent ID: 7535057
Filing Date: 2009-05-19
Classification: H01L

Abstract:
1. A transistor structure comprising: a lateral DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the drift region having a conductivity type, the DMOS transistor being built on a substrate having a conductivity type opposite to that of the drift region; and at least one pair of parallel opposing floating trenches, wherein a controllable current path exists in-between opposing floating trenches in the drift region, each floating trench comprising a conductive or semiconductor material that has no external electrical contact, the conductive or semiconductor material extending into the substrate and being insulated from any surrounding material by a dielectric, the trenches having a length dimension running along the drift region between the source and drain, the gate having a width dimension running along the body region, the gate width dimension being substantially perpendicular to the length of the opposing floating trenches, wherein an operating bias voltage applied to the drain capacitively couples a potential to the opposing floating trenches through the drift region and the substrate, the opposing floating trenches being arranged so that the potential coupled to the opposing floating trenches causes a first lateral depletion region to extend from a first one of the opposing floating trenches toward an opposing second one of the opposing floating trenches, and causes a second lateral depletion region to extend from the second one of the opposing floating trenches toward the first one of the opposing floating trenches, such that the first lateral depletion region and the second lateral depletion region merge in the drift region at a certain drain bias.