Patent ID: 7940554
Filing Date: 2011-05-10
Classification: G11C

Abstract:
1. A method of biasing a nonvolatile memory array, the nonvolatile memory array comprising a first plurality of Y lines, a second plurality of Y lines, a plurality of X lines, a first plurality of two terminal memory cells and a second plurality of two terminal memory cells, wherein each of the first plurality of memory cells is coupled to one of the first plurality of Y lines and one of the plurality of X lines and each of the second plurality of memory cells is coupled to one of the second plurality of Y lines and one of the plurality of X lines, the method comprising: driving substantially all of the first plurality and second plurality of Y lines to a Y line unselect voltage; and driving at least one selected Y line of the first plurality of Y lines to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.