Patent ID: 8361867
Filing Date: 2013-01-29
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: providing a substrate having a semiconductor surface layer, the substrate having a stressor layer positioned at a depth within the substrate and positioned adjacent the semiconductor surface layer, the buried stressor layer provided in a stressed state in comparison to the semiconductor surface layer; forming a field effect transistor on the semiconductor surface layer, the field effect transistor comprising source and drain regions and a gate structure; forming a pre-metal dielectric layer over the field effect transistor; etching openings in the pre-metal dielectric layer and etching to expose contact portions of the substrate on either side of the gate structure; etching into the substrate within the openings in the pre-metal dielectric, the etching proceeding to sufficient depth so that the stressor layer induces stress in the semiconductor surface layer to provide longitudinal stress to the upper semiconductor layer in a channel region of the field effect transistor through edge relaxation; and forming electrical contacts to the source and drain regions with the contacts formed at least partially within the substrate.