Patent ID: 6458659
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method of fabricating a non-volatile memory device integrated in a semiconductor substrate which include at least one matrix of non-volatile memory cells, each comprising at least one floating-gate MOS transistor having, a respective gate electrode, and the memory device including control circuitry associated with said at least one matrix and comprising MOS transistors having respective gate electrodes, the method comprising:forming said gate electrodes above the substrate; depositing a first dielectric layer onto a surface of the substrate exposed by forming said gate electrodes; etching back said first dielectric layer without use of an etch mask to form isolating spacers on side walls of said gate electrodes of said memory cells; depositing a second dielectric layer onto a surface of the substrate exposed by etching back said first dielectric layer, the depositing of the second dielectric layer to such a degree that at least a portion of the first dielectric layer is thicker than an adjacent portion of the second dielectric layer; overlying said at least one memory matrix with a protective layer; and etching back said second dielectric layer to form isolating spacers on side walls of said gate electrodes of said MOS transistors in said control circuitry.