Patent ID: 8649420
Filing Date: 2014-02-11
Classification: G06F

Abstract:
1. A data-processing module, for handling a command serial signal, capable of being connected in series so as to form a cascading data-transmitting system, the data-processing module comprising: a command register; a data register; a first-in-first-out (FIFO) buffering circuit, for transmitting and temporarily storing the command serial signal according to a clock signal; and a logic-determining circuit, for determining if a first section of the command serial signal is a predetermined command according to a first bit, a second bit, and a third bit of the first section of the command serial signal temporarily stored in the FIFO buffering circuit; wherein the first bit is adjacent to the second bit, and the second bit is adjacent to the third bit; wherein when the first, the second, and the third bits conform to a data type, the logic-determining circuit determines the first section is the predetermined command, and the logic-determining circuit controls the command register or the data register to store data transmitted by a second section of the command serial signal.