Patent ID: 7420843
Filing Date: 2008-09-02
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a NAND cell unit with a plurality of memory cells that are electrically rewritable and non-volatile, and that are connected in series; a source line coupled to a first end of the NAND cell unit; and a bit line coupled to a second end of the NAND cell unit, wherein the NAND cell unit is biased in a data write mode as follows: a write voltage Vpgm is applied to a control gate of a selected memory cell in the NAND cell unit; a channel-isolating voltage is applied to control gates of a plurality of non-selected memory cells disposed on the source line side of the selected memory cell at a plurality of intervals of memory cells; and a write medium voltage Vm lower than Vpgm is applied to control gates of the non-selected memory cells that are between said non-selected memory cells to which the channel-isolating voltage is applied.