Patent ID: 7796225
Filing Date: 2010-09-14
Classification: G02F

Abstract:
1. A method of fabricating an array substrate for an IPS-mode LCD device, comprising: forming a gate line, a gate electrode, a first common line, and first and second common electrodes on a substrate having a switching region and a pixel region using a first mask process, wherein the gate electrode extends from the gate line and is formed in the switching region, the first common line is substantially parallel to the gate line, and the first and second common electrodes extend from the first common line into the pixel region; sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer on the gate line, the gate electrode, and the first and second common electrodes; forming a common line contact hole in the gate insulating layer, an active layer and an impurity-doped amorphous silicon pattern by patterning the gate insulating layer, the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer using a second mask process, wherein the common line contact hole exposes the first common line, the active layer corresponds to the gate electrode on the gate insulating layer and the impurity-doped amorphous silicon pattern has a same shape as the active layer on the active layer; and forming a data line, a source electrode, a drain electrode, a plurality of pixel electrodes and a plurality of third common electrodes on the gate insulating layer, the active layer and the impurity-doped amorphous silicon pattern using a third mask process, wherein the data line crosses the gate line to define the pixel region, the source electrode extends from the data line and contacts the impurity-doped amorphous silicon pattern, and the drain electrode is separated from the source electrode and contacts the impurity-doped amorphous silicon pattern, wherein the plurality of pixel electrodes are separated from each other and substantially parallel to the first and second common electrodes, and each of the plurality of pixel electrodes extends from the drain electrode and each of the plurality of electrodes extends from the drain electrode, and wherein the plurality of third common electrodes contact the first common line through the common line contact hole and are alternately arranged with the plurality of pixel electrodes.