Patent ID: 6940135
Filing Date: 2005-09-06
Classification: H01L

Abstract:
1. A method for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings, the method comprising: forming well regions using an implant process on semiconductor substrate; forming a first patterned mask overlying the semiconductor substrate; forming a plurality of buried implant regions through the first patterned mask, the first patterned mask being formed overlying the semiconductor substrate, each of the buried implant regions including a source region and a drain region formed between a channel region for each respective memory cell region, the memory cell region being one of a plurality of memory cell regions; forming pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions, each of the pocket regions including a first pocket region defined between the channel region and source region and a second pocket region defined between the channel region and the drain region for each memory cell region; and programming one or more selected memory cell regions using implantation of respective one or more selected channel regions; and forming a word line overlying the channel region of each of the memory cell region.