Patent ID: 6249845
Filing Date: 2001-06-19
Classification: G06F

Abstract:
A method for operating a cache within a computer system including a processor, an L1 cache, and an L2 cache, wherein said L1 cache is at a higher level than said L2 cache, wherein said L2 cache has a predetermined coherency granule size within a data array, wherein said coherency granule has a plurality of MESI bits, and wherein said method comprises the steps of:determining whether or not a miss has occurred in said L1 cache;in response to determining that a cache miss has occurred in said L1 cache, determining a state of a target sector and a state of an alternate sector within said coherency granule in said L2 cache; andperforming a cache control instruction in conformity with said state of said target sector and said alternate sector within said coherency granule, such that said cache control instruction selectively performs a different operation on said alternate sector than is performed for said target sector.