Patent ID: 6680254
Filing Date: 2004-01-20
Classification: H01L

Abstract:
A method of fabricating a bit line contact plug of a memory cell, comprisingproviding a semiconductor substrate having a transistor, comprising at least one diffusion region, formed thereon and overlaid by an insulating layer; forming a first masking layer on said insulating layer; patterning said first masking layer and said insulating layer to form a first trench, said first trench being located above the diffusion region; forming a second masking layer to fill said first trench; forming a hole by removing a portion of said second masking layer; forming a bit line contact window by removing a portion of said insulating layer right beneath said hole until a surface of said diffusion region is exposed; forming a bit line contact plug by filling said bit line contact window with a first conductive layer; removing a residual portion of said second masking layer after forming said bit line contact plug, to form a second trench; removing said first masking layer after removing said residual portion of said second masking layer; and forming a bit line by filling said second trench with a second conductive layer.