Patent ID: 7872921
Filing Date: 2011-01-18
Classification: G11C

Abstract:
1. A method for verifying erase of pages of non-volatile memory array having n blocks, each block having m pages of memory cells, each of n and m being a positive integer, one or more pages being selected in a selected block, each block having a plurality of strings of memory cells on a substrate and m wordlines across the strings, each wordline being operably connected to a respective one of the m pages of memory cells, the method comprising: connecting each of the strings to a common source line voltage; and selecting a level of the common source line voltage from a plurality of voltage levels dependent on a number of the of selected word lines; applying a select verify voltage to each wordline corresponding to the selected one or more pages for causing each memory cell of the selected one or more pages to conduct only if erased; applying an unselect verify voltage to each wordline corresponding to the unselected pages for causing each memory cell of the unselected pages to conduct regardless of a respective state of each memory cell of the unselected pages; and sensing a state of each string for verifying erase of each memory cell of each selected wordline.