Patent ID: 8854877
Filing Date: 2014-10-07
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device having a memory cell array arranged in matrix form, comprising: a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; an information holding part which holds information that indicates an one of a plurality of operation modes of said memory cell array; and a mode setting part which is adapted to select said one of the plurality of operation modes by fixing a logical value of at least one bit of a first bit and a second bit of said address signal in accordance with the information held by said information holding part, and supplying said address signal, on which fixing of the logical value is effected, to said decoder thereby to use said one of a plurality of operation modes, said first bit of said address signal carrying information for selecting one of a drain terminal side and a source terminal side of a plurality of memory cells of said memory cell array, and said second bit of said address signal carrying information for selecting one of a plurality of word lines of said memory cell array.