Patent ID: 8980723
Filing Date: 2015-03-17
Classification: H01L

Abstract:
1. A method of forming an integrated circuit comprising the steps: forming a first layer of interconnect; depositing a first etch stop layer with a first thickness on said first layer of interconnect; depositing a first ILD layer on said first etch stop layer; forming a device conductive layer on said first ILD layer; depositing a second etch stop layer with a second thickness on said device conductive layer where said second thickness is approximately equal to said first thickness plus an additional thickness that is approximately equal to the difference in a depth of a via formed in said ILD to said first layer of interconnect and a depth of a via formed in said ILD to said device times a ratio of an etch rate of said etch stop layer in a plasma ILD via etch and an etch rate of said ILD in said plasma ILD via etch; forming a device pattern; etching said second etch stop layer; etching said device material; depositing a second ILD layer on said device and planarizing said ILD layer; forming a via pattern on said second ILD layer with a first via over said first layer of interconnect and a second via over said device; etching said ILD layer with said plasma ILD via etch until said first via reaches said first etch stop layer; and etching said first etch stop layer and said second etch stop layer with a plasma etch stop etch.