Patent ID: 7952119
Filing Date: 2011-05-31
Classification: G06F,H01L

Abstract:
1. A layout of an integrated circuit device, comprising: a diffusion level layout portion including a number of diffusion region layout shapes to be formed within a portion of a substrate; a gate electrode level layout portion defined to pattern conductive features within a gate electrode level over the portion of the substrate corresponding to the diffusion level layout portion, the gate electrode level layout portion including three or more linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other, wherein each of the three or more linear-shaped layout features within the gate electrode level layout portion is positioned beside another of the three or more linear-shaped layout features within the gate electrode level layout portion according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein each of the three or more linear-shaped layout features within the gate electrode level layout portion is defined to have a substantially equal length as measured in the first direction, and wherein some of the three or more linear-shaped layout features within the gate electrode level layout portion are defined to include one or more gate electrode portions which extend over one or more of the number of diffusion region layout shapes to form respective transistor devices, and wherein at least one of the three or more linear-shaped layout features forms gate electrodes of two or more transistor devices including at least two different transistor device types.