Patent ID: 6564300
Filing Date: 2003-05-13
Classification: G06F

Abstract:
A memory access control system for controlling a memory access operation suitable for use between a central processing unit (CPU) and a memory unit, wherein the CPU can issue a read request for reading data from the memory unit and issue a level 1 (L1) cache write-back signal after a predetermined time to indicate that a write back operation is desired, the memory access control system comprising:a mode-switching unit coupled to the CPU for issuing a mode-switch signal indicative of a read operation mode in response to the L1 write-back signal; a CPU interface coupled to the CPU and the mode-switching unit, for receiving the read request and the mode-switch signal, the CPU interface being responsive to the mode-switch signal for issuing a read-stop signal to abandon a currently accessed data from the memory unit; and a memory control unit coupled between the CPU interface and the memory unit for reading data from the memory unit according to the read request, the memory unit being responsive to the read-stop signal for writing data from the CPU into the memory unit according to the read request after abandoning the currently accessed data.