Patent ID: 6822891
Filing Date: 2004-11-23
Classification: G11C

Abstract:
A ferroelectric memory device comprising:a memory cell array having a plurality of memory cells arranged in a matrix form, each of the memory cells including a cell transistor and a ferroelectric capacitor, one of source and drain regions of the cell transistor being electerically connected to a corresponding one of a plurality of bit lines, a gate of the cell transistor being electrically connected to a corresponding one of a plurality of word lines, the other one of the source and drain regions of the cell transistor being electrically connected to one electrode of the ferroelectric capacitor, the other electrode of the ferroelectric capacitor being electrically connected to a corresponding one of a plurality of plate lines; a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array, and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array, the first dummy bit line having the same width as the bit line, and not electrically connected to a data line which transmits data; and a first dummy memory cell electrically connected to the first dummy bit line and including a cell transistor and a ferroelectric capacitor.