Patent ID: 6014728
Filing Date: 2000-01-11
Classification: G06F

Abstract:
A multiprocessing computer system comprising:a plurality of processing units;a system memory accessible by each of said plurality of processing units; anda plurality of cache memory subsystems, wherein a separate cache memory subsystem is operatively coupled between a respective processing unit and said system memory, and wherein each of said cache memory subsystems is operable in a write-through write mode and a copy-back write mode, and wherein each of said plurality of cache memory subsystems includes:a storage array containing a plurality of blocks;a plurality of cache block status fields, wherein each of said plurality of cache block status fields corresponds to an individual block in said storage array;a translation lookaside buffer configured to identify a page of addressed information and including a TLB write policy field associated with said page of addressed information, said TLB write policy field capable of being set in a first TLB write policy state associated with said write-through write mode and in a second TLB write policy state associated with said copy-back write mode;one or more write policy pins capable of being placed in a first write policy pin state associated with said write-through write mode and in a second write policy pin state associated with said copy-back write mode; anda cache control unit for controlling a transfer of data when a write hit operation to a particular block in said storage array occurs, wherein said cache control unit is configured to effectuate said transfer of data in either said write-through write mode or in said copy-back write mode depending upon a state of a cache block status field corresponding to said particular block, and wherein said cache control unit is further configured such that said state of said cache block status field can be set according to at least a state of said one or more write policy pins and according to said TLB write policy field.