Patent ID: 9118313
Filing Date: 2015-08-25
Classification: G11C,H03K

Abstract:
1. A semiconductor memory device comprising: a termination resistance calibration circuit configured to calibrate a first termination resistance of a data output driver of the semiconductor memory device, wherein the termination resistance calibration circuit comprises: a first self-adjustment logic configured to determine whether a value of an upper bit string of a first calibration code is equal to or greater than a first upper critical value with respect to the first calibration code, or is equal to or less than a first lower critical value with respect to the first calibration code, in response to a first calibration start signal, and to generate a first adjustment signal for adjusting a value of the first termination resistance of the data output driver based on the determination result of the first self-adjustment logic, wherein the first lower critical value is less than the first upper critical value; and a first resistance calibration logic configured to provide the upper bit string of the first calibration code to the first self-adjustment logic, and to generate a first updated calibration code by performing a first calibration calculation based on the first calibration code and a first comparison signal generated according to a result of comparing a reference voltage and a voltage of a first comparison target node, wherein the first updated calibration code calibrates the first termination resistance of the data output driver, after the value of the first termination resistance of the data output driver is adjusted by the first adjustment signal.