Patent ID: 7005346
Filing Date: 2006-02-28
Classification: H01L

Abstract:
1. A method for fabricating a memory cell of a memory cell array in a semiconductor memory, in which a capacitor with one electrode as memory cell node and a second electrode as common counterelectrode of the memory cell array is formed in a semiconductor substrate and a field-effect transistor (FET) is produced above the capacitor, which transistor is connected to the memory cell node of the capacitor, to a word line and to a bit line, the method comprising: etching two first trenches in the semiconductor substrate, the two trenches running parallel to one another and having a first depth, wherein a web is formed between the two trenches, the web being made of the material of the semiconductor substrate and including two long sides that run perpendicularly to the substrate surface, wherein the web is connected at least indirectly to the semiconductor substrate at narrow sides located between the long sides; severing the web at its underside such that the web is separated from the semiconductor substrate; providing the web with a closed dielectric at its two long sides and at its underside; filling the first trenches with a semiconductor material; forming a field effect transistor (FET) at a top side of the web or above the web such that the FET is connected to the web at a memory node; forming a word line and a bit line such that the word line and the bit line are each contact-connected with the FET.