Patent ID: 8471600
Filing Date: 2013-06-25
Classification: H03K

Abstract:
1. A circuit arrangement, comprising: a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode, the transistor configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and to be activated or deactivated by a respective signal at the gate electrode; a gate control unit connected to the gate electrode and configured to deactivate the transistor or to prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state; and a monitoring unit configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs shortly after the load current crosses zero while the transistor is deactivated or activation is prevented by the gate control unit, and wherein the monitoring unit is further configured to generate a signal which forces the transistor to turn on when the monitoring unit detects the sudden rise of the collector-emitter voltage.