Patent ID: 6821873
Filing Date: 2004-11-23
Classification: H01L

Abstract:
A method for fabricating an integrated circuit, comprising the following steps performed in order:depositing a high-&kgr; gate dielectric over a surface of a semiconductor body, wherein said high-&kgr; gate dielectric comprises a material selected from the group consisting of MN, MO, MON, MSiO, MSiN, MSiON, MAIO, MAIN, MAION, MAISiO, MAISIN, or MAISiON, where M is Zr, Hf, La, Y, Gd, Eu, Pr, or Ce; performing a first anneal in a non-oxidizing inert ambient to densify the high-&kgr; gate dielectric; and performing a second anneal in an oxidizing ambient.