Patent ID: 6255683
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A memory cell for use in a dynamic random access memory of the kind that uses a transistor and a storage capacitor in a semiconductor body comprising:a relatively deep trench with substantially, vertical side walls that includes a deep portion that is filled with doped polysilicon, that is insulated from the semiconductor body by a dielectric layer and that serves as the storage node of the memory cell, the polysilicon fill also including an oxide layer at its top; anda transistor that includes a drain region that is part of the semiconductor body and a source region that lies in the semiconductor body along a sidewall at top of the polysilicon fill of the deeper portion of the trench, and a channel region extending between the source and drain regions along the top surface of the semiconductor body and along a sidewall of the deep trench that includes vertical and horizontal portions, and a doped silicon gate conductor that fills the upper portion of the trench and is electrically insulated from the doped polysilicon in the deeper portion of the trench both by a dielectric layer that was formed at the top of the polysilicon fill in the deeper portion of the trench and a dielectric layer that was formed as part of the gate dielectric of the transistor.