Patent ID: 8604840
Filing Date: 2013-12-10
Classification: H03L

Abstract:
1. An apparatus comprising: a phase frequency detector configured to receive a reference signal of frequency fref on a first line, receive a divider feedback signal (Div) of frequency fdiv on a second line, receive a VCO output signal of frequency fvco on a third line, and output an up current control signal (Up) and a down current control signal (Down), wherein the up current control signal comprises a sequence of up current control pulses, wherein the down current control signal comprises a sequence of down current control pulses, and wherein the phase frequency detector comprises: a charge pump circuit configured to receive the up current control signal and the down current control signal and to output a charge pump output current signal (Icp); a loop filter configured to receive a sum of the charge pump output current signal (Icp) and a down modification signal (ΔI) and to output a control signal (Vctl); a divider configured to receive the VCO output signal on a fourth line and to output the divider feedback signal (Div) to the phase frequency detector on the second line; a voltage controlled oscillator (VCO) configured to receive the control signal (Vctl), to output the VCO output signal to the phase frequency detector on the third line, and to output the VCO output signal to the divider on the fourth line; and a down modification signal generating circuit configured to receive an instantaneous quantization error signal (ei) and to output the down modification signal (ΔI).