Patent ID: 7992060
Filing Date: 2011-08-02
Classification: G06F,G11C

Abstract:
1. A memory device comprising: a memory array organized into at least first, second, third and fourth blocks, wherein the blocks are organized into at least a first block group and a second block group, wherein the first block group includes at least the first and second blocks, wherein the second block group includes at least the third and fourth blocks, wherein the first block has an identifier that uniquely identifies the first block within the first block group and that matches an identifier that uniquely identifies the third block within the second block group, and wherein the second block has an identifier that uniquely identifies the second block within the first block group and that matches an identifier that uniquely identifies the fourth block within the second block group, wherein each of the first, second, third, and fourth blocks is associated with a respective status indication, and whether each of the first, second, third, and fourth blocks is determined to be defective or not determined to be defective is based on the respective status indication; and wherein the first block is configured to be grouped with the third block for purposes of a memory operation if the first and third blocks are not determined to be defective, and the second block is configured to be grouped with the third block for purposes of the memory operation if the first block is determined to be defective and the third block is not determined to be defective.