Patent ID: 8909899
Filing Date: 2014-12-09
Classification: G06F

Abstract:
1. A computer program product for emulating execution of a perform frame management function (PFMF) machine instruction in a processor having a native instruction set architecture (ISA), the processor, configured to translate a virtual address into a translated address of a block of main storage in a computer system of a machine architecture having a hierarchy of translation tables used for translation of said virtual address, said block of main storage having an associated storage key separate and distinct from any of said translation tables, said PFMF machine instruction defined for said machine architecture other than the native ISA, the computer program product comprising: a tangible storage medium readable by said computer system, said computer readable medium storing instructions for performing a method for executing the PFMF machine instruction, the method comprising: executing said predetermined software routine, the execution comprising: obtaining, by the processor, a frame size code and frame management information (FMI) from a first general register specified by said PFMF machine instruction, wherein said frame management information comprises a FMI key field comprising an FMI reference bit, an FMI change bit, and five FMI access-protection bits, the five access protection bits comprising four FMI access-control (ACC) bits and a FMI fetch protection bit; and based on said frame size code designating a large block of main storage, wherein said large block of main storage consists of an absolute addressed contiguous first plurality of sub-blocks of main storage, setting, by a processor, one or more bits of each corresponding storage key of each of a second plurality of said contiguous first plurality of sub-blocks of main storage with values of corresponding bits of said FMI key field, said second plurality determined by said operand absolute address of said initial sub-block of main storage.