Patent ID: 8804889
Filing Date: 2014-08-12
Classification: H04L

Abstract:
1. A receiver having: a data slicer having an output, a signal input coupled to an input of the receiver, and a clock input; and a clock generator coupled to the input of the receiver; wherein the clock generator comprises: a first slicer having an output, a signal input coupled to the input of the receiver, and a clock input; a second slicer having an output, a signal input coupled to the input of the receiver, and a clock input; a first clock and data recovery circuit coupled to the output of the first slicer and configured to generate a first phase value at an output; a second clock and data recovery circuit coupled to the output of the second slicer and configured to generate a second phase value at an output; a phase averaging circuit configured to compute an average of the first phase value and the second phase value and generate an average phase value at an output; a first phase shifter configured to generate a first transition sampling clock having a phase determined by the first phase value; a second phase shifter configured to generate a second transition sampling clock having a phase determined by the second phase value; a third phase shifter configured to generate a data sampling clock having a phase determined by the average phase value; wherein the clock input of the data slicer is adapted to receive the data sampling clock, the clock input of the first slicer is adapted to receive the first transition sampling clock, and the clock input of the second slicer is adapted to receive the second transition sampling clock.