Patent ID: 6829171
Filing Date: 2004-12-07
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a plurality of non-volatile memory cells, arranged in rows and columns, each storing data in a non-volatile manner and including an insulated gate transistor having a threshold voltage set according to stored data, said threshold voltage having at least a first state corresponding to a data at a first logical level and a second state corresponding to data at a second logical level; a plurality of bit lines provided corresponding to the memory cell columns, and connected to the memory cells on corresponding columns; read current generating circuitry for supplying a current to a bit line of a selected column, in data reading; reference current generating circuitry for generating a reference current, said reference current, with respect to a read current flowing from said read current generating circuitry into the bit line of the selected column, having a magnitude of an average of a first read current corresponding to a current flowing through said bit line of the selected column from said read current generating circuitry when a memory cell in said first state is selected and a second read current corresponding to a current flowing through said bit line of the selected column from said read current generating circuitry when a memory cell in said second state is selected; comparison circuitry, coupled to said read current generating circuitry and said reference current generating circuitry, for comparing the reference current from said reference current generating circuitry with a residual current except a current flowing into the bit line on the selected column in the current generated from said read current generating circuitry to generate an output signal corresponding to a result of comparison, the first and second read currents each corresponding to a residual current except the current flowing through the selected memory cell in the current generated by said read current generating circuitry; and internal read circuitry for generating internal read data according to the output signal of said comparison circuitry.