Patent ID: 6703273
Filing Date: 2004-03-09
Classification: H01L

Abstract:
A method of fabricating trench capacitor structures for a dynamic random access memory (DRAM) cell, comprising the steps of:forming deep, wide diameter trench openings in a first semiconductor structure; forming a buried plate region in an area of said first semiconductor structure encompassing said deep, wide diameter trench openings; forming a node dielectric layer on exposed surfaces of said deep, wide diameter trench openings; forming a conductive storage node plate structure in said deep, wide diameter trench openings resulting in deep, wide diameter trench capacitor structures in a top portion of said first semiconductor substrate, with each deep, wide diameter capacitor structure comprised of said storage node plate structure, of said node dielectric layer, and of said buried plate region; forming a splitting anneal region in a top portion of a second semiconductor substrate; bonding a second semiconductor substrate to said first semiconductor substrate, at a temperature between about 800 to 900Â° C., for a time between about 10 to 15 mm., in an inert ambient, with said top portion of said second semiconductor substrate bonded to top surface of said first semiconductor substrate; performing a chemical mechanical polishing procedure to remove bottom portion of said second semiconductor substrate, terminating at said splitting implant region, resulting in a thinned second semiconductor substrate, overlying said top surface of said first semiconductor substrate; forming narrow diameter trench structures in first portions of said thinned second semiconductor substrate, overlying and contacting top portions of said deep, wide diameter capacitor structures, wherein said narrow diameter trench structures comprise truncated collar silicon dioxide spacers; and forming DRAM transfer gate transistor elements in said second portions of said thinned second semiconductor substrate.