Patent ID: 8209490
Filing Date: 2012-06-26
Classification: G06F

Abstract:
1. A method for maintain cache coherency comprising: receiving, with a shared cache, a write request referencing a block from a requesting processor core of the plurality of processor cores on a processor, wherein the plurality of processor cores each include a private cache, and wherein the plurality of cores and the shared cache are connected by a ring interconnect; generating a single message, with the shared cache, in response to receiving the write request; delivering an invalidation part of the single message to at least the second processor core; delivering a write-acknowledgement part of the single message only to the requesting processor core; invalidating the block in the private cache included in the second processor core in response to the second processor core receiving the invalidation part of the single message; and write-acknowledging the write request for the requesting processor core in response to the requesting processor core receiving the write-acknowledgment part of the single message transmitted on the ring interconnect.