Patent ID: 6433634
Filing Date: 2002-08-13
Classification: H03F

Abstract:
An electronic circuit for providing a desired common mode voltage to a differential output of an amplifier stage (AMPSTG), which differential output comprises a first output terminal (1) and a second output terminal (2), comprising a supply terminal (VSS); a first field effect transistor (T1) with a source coupled to the supply terminal (VSS); a second field effect transistor (T2) with a source coupled to the supply terminal (VSS); a third field effect transistor (T3) with a source coupled to the supply terminal (VSS) and with a gate coupled so as to receive a reference voltage (VCM); a first cascode circuit (CSC1) with a first main current electrode coupled to a drain of the first field effect transistor (T1), with a second main current electrode coupled to a gate of the first field effect transistor (T1) and to the first output terminal (1), and with a control electrode; a second cascode circuit (CSC2) with a first main current electrode coupled to a drain of the second field effect transistor (T2) and to the drain of the first field effect transistor (T1), with a second main current electrode coupled to a gate of the second field effect transistor (T2) and to the second output terminal (2), and with a control electrode coupled to the control electrode of the first cascode circuit (CSC1); a third cascode circuit (CSC3) with a first main current electrode coupled to a drain of the third field effect transistor (T3), with a second main current electrode coupled to the control electrode of the first cascode circuit (CSC1), and with a control electrode coupled to the control electrode of the first cascode circuit (CSC1); and current means (I) for providing a current through the third field effect transistor (T3) and the third cascode circuit (CSC3), characterized in that the electronic circuit further comprises: a fourth field effect transistor (T4) with a source coupled to the first supply terminal (VSS); a fourth cascode circuit (CSC4) with a first main current electrode coupled to a drain of the fourth field effect transistor (T4), with a second main current electrode coupled to a gate of the fourth field effect transistor (T4), and with a control electrode coupled to the control electrode of the first cascode circuit (CSC1); further current means (IF) for supplying a current through the fourth field effect transistor (T4) and the fourth cascode circuit (CSC4); and voltage-generating means (VGMNS) coupled in series between the further current means (IF) and the second main current electrode of the fourth cascode circuit (CSC4), and in that the gate of the third field effect transistor (T3) is coupled to the voltage-generating means (VGMNS) for receiving the reference voltage (VCM), and in that the first (T1), the second (T2), and the third (T3) field effect transistor are dimensioned such that they have approximately the same current densities, and in that the fourth field effect transistor (T4) is dimensioned such that it has a current density which is a factor N smaller than said current densities, said factor N being approximately equal to the ratio of the nominal current to the minimum current through the first field effect transistor (T1).