Patent ID: 6539048
Filing Date: 2003-03-25
Classification: H03H,H04B

Abstract:
A matched filter, comprising:an n-stage delay line for storing data samples; an enable circuit having outputs for enabling the storage, in a sequential manner, of individual ones of said data samples into individual stages of said n-stage delay line; an m-stage coefficient register for storing coefficient data, wherein adjacent stages of said coefficient register are serially coupled together for shifting coefficient data from stage to stage; a plurality of combining circuits individual ones of which have inputs coupled to outputs of one of said delay stages and one of said coefficient register stages for combining said outputs together, and circuitry, responsive to a control signal, for changing said n-stage delay line to a p-stage delay line and for changing said m-stage coefficient register to a q-stage coefficient register, where psaid delay line is coupled together in a ring configuration, and where said circuitry is operable to both increase and decrease the size of the ring in response to said control signal.