Patent ID: 8455930
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate comprising a major surface; a gate stack comprising a sidewall over the substrate; a spacer over the substrate adjoining the sidewall of the gate stack, wherein the spacer comprises a bottom surface having an outer point that is farthest from the gate stack; an isolation structure in the substrate on one side of the gate stack having an outer edge closest to the spacer; and a strained material below the major surface of the substrate disposed between the spacer and the isolation structure comprising an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate, wherein the transition plane intersects the outer point and extends downward to the outer edge of the isolation structure, and a cross-sectional area of the lower portion is greater than a cross-sectional area of the upper portion, wherein the upper portion comprises a first facet adjacent to the spacer, wherein an acute angle of the first facet to the major surface of the substrate is less than the acute angle of the transition plane to the major surface of the substrate.