Patent ID: 8880966
Filing Date: 2014-11-04
Classification: G01R,G06F

Abstract:
1. A process of operating a state machine having an IN signal input, a Reset input, a Clock input, a Power On Reset input, a Master Reset output, and a Controller Enable output, comprising: A. entering a Set Master Reset Low & Poll IN state in response to a signal on one of the Reset input and the Power On Reset input; B. outputting a low signal on the Master Reset output while the state machine is in the Set Master Reset Low & Poll IN state; C. maintain the state machine in the Set Master Reset Low & Poll IN state while the IN input is a high signal; D. transitioning the state machine from the Set Master Reset Low & Poll IN state to a first POLL IN state when the IN input goes from a high signal to a low signal; E. transitioning the state machine from the first POLL IN state to a second POLL IN state when the IN input goes to a low signal and transitioning the state machine from the first POLL IN state to the Set Master Reset Low & Poll IN state when the IN goes to a high signal; F. transitioning the state machine from the second POLL IN state to a third POLL IN state when the IN input goes to a high signal and transitioning the state machine from the second POLL IN state to the Set Master Reset Low & Poll IN state when the IN goes to a low signal; G. transitioning the state machine from the third POLL IN state to a Set Master Reset & Controller Enable High state when the IN input goes to a high signal and transitioning the state machine from the third POLL IN state to the Set Master Reset Low & Poll IN state when the IN goes to a low signal; and H. setting the Master Reset output to a high signal and setting the Controller Enable output to a high signal while the state machine is in the Set Master Reset & Controller Enable High state.