Patent ID: 6183615
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A transport system for wafer processing comprising:a plurality of housings connected in series to define a wafer processing line;a track extending through the housings along the processing line;a plurality of isolation valves, each isolation valve located between two adjacently situated housings and operable to open and close to permit and to prevent, respectively, access between adjacently situated housings along the track, the isolation valves also operable to isolate any housing from a housing located adjacent thereto, and the isolation valves dividing the track into a plurality of discontinuous track segments, with one track segment per housing;a wafer carrier mounted on wheels which engage the track, thereby making the carrier movable along the track through the housings at a predetermined vertical position above the track, the carrier adapted to hold a plurality of wafers;a plurality of carrier magnets attached to the carrier and oriented along the length thereof and substantially parallel with the track;a plurality of magnetic drive units located outside of the housings and arranged substantially parallel with the track, each unit associated with one of the housings and the track segment associated therewith, and including means for imposing at least one magnetic field within the respective housing to magnetically couple with the carrier magnets when the carrier is located therein, each unit being operable to move the imposed magnetic fields along the track to magnetically translate the carrier through the respective housing along the respective track segment via the wheels, so that the carrier moves on the wheels through each housing without a mechanical coupling between the respective drive unit located outside the housing and the carrier located inside the housing; anda controller operatively connected to the isolation valves and the magnetic drive units to open and close the valves and to move the imposed magnetic fields to translate the carrier along the wafer processing line according to a predetermined sequence, the wafer carrier remaining at the predetermined vertical position during translation and when at rest in the housings.