Patent ID: 6282557
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number, comprising:a partial product generation module for generating a set of partial products of said first binary number and said second binary number;a partial product reduction module, connected to said partial product generation module, for combining said set of partial products with said third binary number to produce a redundant Sum and a redundant Carry, wherein said partial product reduction module includesmeans for complementing a most significant bit of each of said plurality of partial products;means for complementing a most significant bit of said third binary number;means for adding said set of partial products with complemented most significant bits, said third binary number with complemented most significant bit, and a most significant bit of said third binary number to produce said redundant Sum and said redundant Carry; andan adder for adding said redundant Sum and said redundant Carry to yield a Sum Total.