Patent ID: 6700423
Filing Date: 2004-03-02
Classification: H01S,H03K,H04B,H04L

Abstract:
A pulse width control circuit for controlling pulse width of an input signal based on pulse width control information, and generating an output signal for driving a light emitting element, comprising:a rise/fall control section controlling at least one of a rise time and a fall time of said input signal according to a bit rate of said input signal; a waveform shaping section shaping a signal output from said rise/fall control section, to generate said output signal; and a control signal generating section generating a control signal controlling an operation of said rise/fall control section based on said pulse width control information wherein said rise/fall control section comprises: current source controlled in accordance with the control signal from said control signal generating section; a bit detection element detecting a level of each bit indicated by said input signal; and an integrating element determining rise and fall time constants of said input signal based on a current supplied from said current source and detection results from said bit detection element, wherein said current source includes: a first current source having one terminal applied with a power source voltage, a current value thereof being controlled in accordance with the control signal from said control signal generating section; and a second current source having one terminal grounded, a current value thereof being controlled in accordance with the control signal from said control signal generating section; wherein said bit detection element includes: a P-channel MOSFET having a gate terminal applied with said input signal, a source terminal applied with the power source voltage, and a drain terminal connected to the other terminal of said second current source; and an N-channel MOSFET having a gate terminal applied with said input signal, a source terminal grounded, and a drain terminal connected to the other terminal of said first current source; and wherein said integrating circuit includes: a first P-channel MOSFET having a drain terminal and a gate terminal each connected to the other terminal of said second current source, and a source terminal applied with the power source voltage; a first N-channel MOSFET having a drain terminal and a gate terminal each connected to the other terminal of said first current source, and a source terminal grounded; a second P-channel MOSFET having a gate terminal connected to the other terminal of said second current source, a source terminal applied with the power source voltage, and a drain terminal connected to an output terminal of said rise/fall control section; and a second N-channel MOSFET having a gate terminal connected to the other terminal of said first current source, a source terminal grounded, and a drain terminal connected to the output terminal of said rise/fall control section.