Patent ID: 8458403
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. A cache system to compare memory transactions while facilitating checkpointing and rollback, the system comprising: at least two processor cores each including at least one cache operating in write-through mode; at least two checkpoint caches operating in write-back mode and communicatively coupled to respective ones of the at least two cache operating in write-through mode in the at least two processor cores; a comparison/checkpoint logic communicatively coupled to the at least two checkpoint caches, wherein the comparison/checkpoint logic compares memory transactions stored in the at least two checkpoint caches responsive to an initiation of a checkpointing; and a main memory communicatively coupled to at least one of the at least two checkpoint caches, wherein, if the memory transactions stored in the at least two checkpoint caches match, the checkpoint cache communicatively coupled to the main memory writes back all dirty cache lines to the main memory, and wherein, if memory transactions stored in the at least two checkpoint caches do not match, a rollback is initiated for the at least two processor cores and all dirty cache lines are invalidated.