Patent ID: 6070212
Filing Date: 2000-05-30
Classification: G06F

Abstract:
A bus arbiter, which is connected to a CPU via a CPU data bus and a CPU address bus, a DMA (direct memory access) controller via a DMA data bus and a DMA address bus, and at least two DRAMs via a DRAM address bus and respective DRAM DATA buses, and the CPU being connected to a ROM via the CPU data bus and the CPU address bus, said bus arbiter comprising:arbitration means for arbitrating access requests to the DRAMs from the CPU and the DMA controller so as to allow one of the access requests;check means for checking a value of a predetermined bit portion in an address of each access request transmitted via the CPU address bus or the DMA address bus;determination means for determining whether the address of the access request falls within an address area of a first one of the DRAMs or an address area of the ROM based on the value checked by said check means; andcontrol means for accessing to the first one of the DRAMs and refreshing a second one of the DRAMs, simultaneously, when said determination means determines the address of the access request falls within the address area of the first one of the DRAMs, and refreshing all the DRAMs while the CPU accesses to the ROM when said determination means determines the address of the access request falls within the address area of the ROM.