Patent ID: 7777268
Filing Date: 2010-08-17
Classification: G11C,H01L

Abstract:
1. A dual-gate memory cell, comprising: a memory device having a gate electrode, a charge-storing layer and a channel region that is provided on a first surface of a non-crystalline semiconductor layer, wherein the memory device is adapted for reading by applying a predetermined voltage to the gate electrode of the memory device and measuring a current in the channel region, wherein the memory device having a composite dielectric layer comprising silicon oxide and silicon nitride materials; an access device having a channel region provided on a second surface of the non-crystalline semiconductor layer, wherein the non-crystalline semiconductor layer has a thickness such that a sensitivity parameter between the access device and the memo device is less than 0.8 and wherein the sensitivity parameter being the magnitude of the ratio of the change in the access gate threshold voltage and an applied voltage on the memory device.