Patent ID: 7290071
Filing Date: 2007-10-30
Classification: H04L

Abstract:
1. A processor comprising: a plurality of input ports; memory circuitry for storing data blocks associated with protocol data units and received by the processor at the input ports; and controller circuitry coupled to the memory circuitry and operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor; wherein a discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular protocol data unit is discarded; wherein one or more additional data blocks received at the given input port for the particular protocol data unit are discarded based at least in part on the discarded data block indicator; and wherein the controller circuitry is operative to maintain separate discarded data block indicators for respective ones of the plurality of input ports.