Patent ID: 8470671
Filing Date: 2013-06-25
Classification: H01L

Abstract:
1. A method of manufacturing a 3-D vertical memory, comprising: providing a substrate having a sacrificial bottom layer; forming a multilayer structure composed of a plurality of alternatively stacked insulating intermediate layers and sacrificial intermediate layers; dividing said multilayer structure into a first multilayer structure and a second multilayer structure; forming an insulating layer encompassing said first multilayer structure and said second multilayer structure; forming a plurality of first through holes penetrating through said first multilayer structures and said second multilayer structures; removing said sacrificial intermediate layers in said first multilayer structure and said second multilayer structure to form a plurality intermediate spaces; forming metal layers in said intermediate spaces and said first through holes; removing a portion of said metal layers to form a plurality of second through holes penetrating through said first multilayer structure and said second multilayer structure; removing said sacrificial bottom layer to form an empty bottom space; and forming interconnected channel structures in said second through holes and said bottom space.