Patent ID: 6590226
Filing Date: 2003-07-08
Classification: G02F,H01L

Abstract:
A thin film transistor substrate for a liquid crystal display, comprising:gate wiring fanned on an insulation substrate and including a gale electrode and a gate pad; a gate insulation layer covering said gate wiring; a semiconductor layer formed over said gate insulation layer; a source electrode and a drain electrode both overlying said semiconductor layer and said gate insulation layer; data wiring formed over said gate insulation layer and including a data pad, wherein the data pad includes a flat edge portion in contact with said gate insulation layer and a protruding central portion; a pad auxiliary layer formed on and in contact with said gate insulation layer, wherein a top surface and a side surface of said pad auxiliary layer are covered by the protruding central portion of the data pad; a protection layer formed over said data wiring and said gate insulation layer, and having a first contact hole exposing a portion of the gate pad and a second contact hole exposing the protruding central portion of said data pad, wherein said protection layer covers a portion of said flat edge portion of said data pad so as to form a gap between said protection layer and the protruding central portion of the data pad; and an auxiliary pad formed on and in contact with a top surface of the protruding central portion of the data pad and a top surface of said protection layer, wherein a lower portion of said auxiliary pad fills the gap, wherein the data pad, said source electrode and the drain electrode are formed from a same conductive layer.