Patent ID: 6316317
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for manufacturing a nonvolatile semiconductor memory device including a plurality of memory cells each formed by one selection transistor and one memory transistor connected in series, comprising the steps of:forming a photoresist pattern on a silicon substrate in a memory transistor forming area;implanting first impurity ions for suppressing the rate of oxide grown on said silicon substrate using said photoresist pattern as a mask;removing said photoresist pattern after said first impurity ions are implanted;thermally growing a silicon oxide layer on said silicon substrate so that said silicon oxide layer is thinner in a selection transistor forming area than in said memory transistor forming area, after said photoresist pattern is removed;forming a first conductive layer on said silicon oxide layer;forming an insulating layer on said first conductive layer;forming a second conductive layer on said insulating layer; andpatterning said second conductive layer, said insulating layer and said first conductive layer,a threshold voltage of said memory transistor being adjusted independently of a threshold voltage of said selection transistor.