Patent ID: 7315067
Filing Date: 2008-01-01
Classification: H01L

Abstract:
1. A high-voltage n-channel MOSFET, comprising: a native p− doped substrate having no p− well; a first n+ doped source region disposed in said substrate; a source terminal coupled to said first n+ doped region; an n− well disposed in said substrate; a second n+ doped drain region disposed in said n− well; a drain terminal coupled to said second n+ doped region; a channel region disposed between said source region and said drain region; a p+ doped region disposed in said substrate; a body terminal coupled to said p+ doped region; a p− substrate/n− well junction region disposed at the interface of said p− substrate and said n− well; a dielectric layer disposed over said channel region; a first isolator disposed in said n− well, said isolator including a dielectric material that is in contact with said dielectric layer; a second isolator disposed at least partially in said n− well, said second isolator including a dielectric material and isolating said second n+ region from said p+ region; and a gate disposed over said dielectric layer and a portion of said first isolator, said gate comprising at least a first region of p+ doped semiconductor material and a second region of a different material contiguous with said first region of p+ doped semiconductor material.