Patent ID: 6218260
Filing Date: 2001-04-17
Classification: H01L,Y10S

Abstract:
A method of forming an integrated circuit capacitor, comprising the steps of:forming a conductive layer pattern on a semiconductor substrate;forming a hemispherical grain (HSG) silicon surface layer having first conductivity type dopants therein, on the conductive layer pattern;forming a dielectric layer comprising tantalum oxide on the HSG silicon surface layer, by:forming a first tantalum oxide layer on the HSG silicon surface layer;densifying the first tantalum oxide layer by exposing the first tantalum oxide layer to ultra-violet radiation in an ozone ambient;forming a second tantalum oxide layer on the first tantalum oxide layer; and thendensifying the second tantalum oxide layer by exposing the second tantalum oxide layer to oxygen;forming an electrode on the dielectric layer, opposite the HSG silicon surface layer.