Patent ID: 7233000
Filing Date: 2007-06-19
Classification: B81B,B81C,G01F,G01K

Abstract:
1. A silicon processing method, comprising: (a) providing a silicon substrate comprising a top side, a bottom side, and a bulk region; (b) forming an ohmic contact anode on the bottom side of the silicon substrate; (c) forming a masking layer comprising a bilayer of silicon dioxide and polycrystalline silicon on the top side of the silicon substrate and then patterning the masking layer, thereby exposing a portion of the top side of the silicon substrate; (d) forming a sealed microchannel by performing an electrochemical process the electrochemical process comprising: (e) after step (d), depositing a thin dielectric isolation layer on the top side of the silicon substrate; (f) performing a first deposition process, comprising: (g) performing a second deposition process, comprising: (h) depositing a passivation layer above the top side of the semiconductor substrate, wherein the passivation layer is selected from the group consisting of an insulating layer, a silicon oxide layer, a silicon nitride layer, and a polyimide layer.