Patent ID: 6556491
Filing Date: 2003-04-29
Classification: G11C,H01L

Abstract:
A semiconductor storage device comprising:a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells disposed at intersections of said word lines and said bit lines, respectively, each of said memory cells including: a capacitor; and a transistor having a drain coupled to a respective one of said bit lines, a source coupled to said capacitor, and a gate coupled to a respective one of said word lines; a plurality of sense amplifiers coupled to said pairs of said bit lines, respectively, said sense amplifiers amplifying voltages between said pairs of said bit lines, respectively; a plurality of bit line pre-charge circuits disposed at said pairs of said bit lines, respectively, said bit line pre-charge circuits pre-charging and equalizing the voltages of said pairs of said bit lines amplified by said sense amplifiers, respectively; word line deactivating means for deactivating at least one of said word lines in an operation mode other than an ordinary operation mode; bit line pair potential fixing means for setting voltages of at least one of said pairs of said bit lines to the same logic level in the operation mode other than the ordinary operation mode; and sense amplifier deactivating means for deactivating a sense amplifier of said sense amplifiers, said sense amplifier being coupled to said one of said pairs of said bit lines set at the same logic level in the operation mode other than the ordinary operation mode.