Patent ID: 7764100
Filing Date: 2010-07-27
Classification: H03K

Abstract:
1. A flip-flop type DFLOP circuit for an Externally Asynchronous-Internally Clocked (EAIC) system that generates a ready signal, the DFLOP circuit comprising a resolver, the resolver including: a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal; and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller, wherein the resolver further comprises an inversion unit configured to invert a signal on the output node of the signal transmission controller, and wherein the inversion unit is configured to invert a signal output from the signal transmission controller in response to a second level of the internal clock signal, and invert a signal precharged by the precharge unit in response to a first level of the internal clock signal.