Patent ID: 6818949
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A semiconductor device having a MISFET in a first region of a semiconductor substrate and a gate wiring in a second region of the semiconductor substrate, comprising:the semiconductor substrate of n type conductivity; a first semiconductor layer of n type conductivity serving as a drain of the MISFET, formed over the semiconductor substrate; a second semiconductor layer of p type conductivity serving as a channel forming region of the MISFET, formed over the first semiconductor layer; a third semiconductor layer of n type conductivity serving as a source of the MISFET, formed over the second semiconductor layer; a first trench reaching from a top surface of the third semiconductor layer to the first semiconductor layer in the first region; a gate insulating film of the MISFET formed inside the first trench; a gate electrode of the MISFET formed on the fate insulating film; a second trench formed in the second region; a gate wiring formed in the second trench and outside the second trench in the second region; wherein the gate electrode and gate wiring are electrically connected; an upper portion of the gate insulating film is located over the top surface of the third semiconductor layer; an upper portion of the gate electrode is located on the upper portion of the gate insulating film; an insulating film is formed in the second region; and the gate wiring outside the second trench is formed on the insulating film.