Patent ID: 8136000
Filing Date: 2012-03-13
Classification: G01R

Abstract:
1. A method of testing a memory chip of a multi-chip memory package, comprising: receiving a first external signal at a controller integrated on the memory chip to select the memory chip for testing; activating a test mode of the controller in response to receiving the first external signal; mapping external signal lines coupled to the controller to signal lines of the memory chip selected for testing in response to activating the test mode of the controller; receiving a second external signal at controllers integrated on each of the remaining memory chips of the multi-chip memory package; at least restricting communication between external signal lines coupled to the controllers integrated on each of remaining memory chips and each of the remaining memory chips in response to receiving the second external signal at the controllers integrated on each of the remaining memory chips; deactivating the test mode of the controller integrated on the memory chip selected for testing; and restoring communication between the external signal lines coupled to the controllers integrated on each of the remaining memory chips and each of the remaining memory chips to that which occurs during normal operation of the controllers integrated on each of the remaining memory chips; wherein each controller is configured to provide address and/or data signals to its respective memory chip during normal operation of that controller.