Patent ID: 6704222
Filing Date: 2004-03-09
Classification: G11C,H01L

Abstract:
A non-volatile memory system, comprising:a two-dimensional array of memory cells formed on a semiconductor substrate including: source and drain regions connected in bit lines extending in a first direction across the substrate, two charge storage elements and a select transistor therebetween being positioned between adjacent source and drain regions as individual memory cells extending in rows across the substrate in a second direction, the first and second directions being perpendicular to each other, control lines extending in the first direction across charge storage elements of the memory cells with capacitive coupling therewith, and word lines extending in tpe second direction along rows of memory cells to provide control gates of the memory cell select transistors along the rows, a supply of programming voltages simultaneously connectable to the bit, control and word lines of a selected plurality of memory cells along an addressed row in order to program a charge state of each of the two charge storage elements thereof into one of more than two states according to data being stored, and a supply of reading voltages simultaneously connectable to the bit, control and word lines of a selected plurality of memory cells along an addressed row in order to read a programmed one of more than two charge states of the individual charge storage elements thereof, thereby to read more than two bits of data per memory cell.