Patent ID: 8643017
Filing Date: 2014-02-04
Classification: G02F,H01L

Abstract:
1. An active device array substrate, comprising: a substrate; a first patterned conductive layer disposed on the substrate, the first patterned conductive layer comprising a plurality of scan lines, a plurality of gates connected with the scan lines, and a plurality of strip floating shielding patterns; a dielectric layer disposed on the substrate to cover the first patterned conductive layer, the dielectric layer having a plurality of first contact holes, and each of the first contact holes exposing a portion of the scan lines, respectively; a second patterned conductive layer disposed on the dielectric layer, the second patterned conductive layer comprising a plurality of data lines, a plurality of sources connected with the data lines, a plurality of drains, and a plurality of strip capacitance electrodes, wherein each of the strip capacitance electrodes is electrically connected with one of the scan lines through one of the first contact holes; a passivation layer disposed on the dielectric layer to cover the second patterned conductive layer, the passivation layer having a plurality of second contact holes, each of the second contact holes exposing one of the drains respectively; and a plurality of pixel electrodes disposed on the passivation layer, wherein each of the pixel electrodes is electrically connected with one of the drains through one of the second contact holes, respectively.