Patent ID: 7144770
Filing Date: 2006-12-05
Classification: H01L

Abstract:
1. Method for fabricating a memory cell, having the following steps of: a) providing a substrate, b) patterning the substrate by etching a trench-type depression into the substrate, c) producing a barrier layer in the trench-type depression of the substrate in such a way that the barrier layer covers an inner area of the trench-type depression only in a collar region forming an upper region of the trench-type depression; d) growing grain elements on the inner areas of the trench-type depression, the surfaces of the grain elements together with the inner areas of the trench-type depression forming areas of a first electrode of the memory cell and grain elements being etched back in the collar region; e) depositing a dielectric layer on the surfaces of the grain elements and the inner areas of the trench-type depression; and f) depositing a conduction layer on the dielectric layer, the conduction layer forming a second electrode of the memory cell; wherein step d) of growing the grain elements on the inner areas of the trench-type depression comprises the following two substeps of: