Patent ID: 6124191
Filing Date: 2000-09-26
Classification: H01L

Abstract:
A process for forming a MOS transistor on a silicon substrate, comprising:forming a gate;insulating an upper surface of the gate with an insulator which includes a first dielectric material;covering the substrate with a layer of silicon dioxide;anisotropically etching the silicon dioxide to form sidewall spacers on the gate;depositing a layer of perfluorocyclobutane (PFCB) organic polymer over the substrate;etching an opening to the substrate through the layer of PFCB organic polymer with an etchant that etches the layer of PFCB organic polymer at a rate at least 10 times faster than the etchant etches the layer of silicon dioxide and the first dielectric material, wherein portions of the spacers and the first dielectric material are exposed during the step of etching.