Patent ID: 9106575
Filing Date: 2015-08-11
Classification: G06F,H04L

Abstract:
1. An integrated circuit, comprising: a de-multiplexer circuit configured to receive information via a common set of pads; first control logic, selectively coupled to the de-multiplexer circuit, configured to decode at least some of the information based on a first serial-interface technique; and second control logic, selectively coupled to the de-multiplexer circuit, configured to decode at least some of the information based on a second serial-interface technique, wherein, during a first operating mode, the de-multiplexer circuit is configured to selectively couple the information to the first control logic, and wherein, during a second operating mode, the de-multiplexer circuit is configured to selectively couple a first portion of the information to the first control logic and a second portion of the information to the second control logic.