Patent ID: 6720219
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A method for forming a split gate flash memory, comprising:providing a substrate having a pad oxide layer and a pad nitride layer thereon; forming a trench in the substrate, the pad oxide layer and the pad nitride layer; implanting first type dopants in the bottom of the trench to form a drain in the substrate; forming a first oxide layer on the bottom and sidewall of the trench; forming a first polysilicon layer on the sidewall of the trench, to serve as a floating gate; conformally forming a second oxide layer in the trench covering the first polysilicon layer and the first oxide layer; removing the pad nitride layer to expose the pad oxide layer; removing the pad oxide layer to expose the substrate; conformally forming a third oxide layer on the substrate and the second oxide layer; conformally forming a second polysilicon layer on the third oxide layer; conformally forming a first nitride layer on the second polysilicon layer; forming a fourth oxide layer on the first nitride layer; removing a part of the fourth oxide layer by CMP using the first nitride layer as a stop layer to expose a top, approximately horizontal surface of the first nitride layer; etching the first nitride layer to expose a top, approximately horizontal surface of the second polysilicon layer; removing the other part of the fourth oxide layer; forming a fifth oxide layer on the top surface of the second polysilicon layer; removing the first nitride layer and the second polysilicon layer not protected by the fifth oxide layer to expose the third oxide layer, thereby defining the second polysilicon layer to function as a control gate; implanting first type dopants in the substrate to form a source outside the trench; forming a dielectric layer on the third oxide layer, the fifth oxide layer and the control gate; and forming a bit line on the dielectric layer connecting to the drain.