Patent ID: 8446777
Filing Date: 2013-05-21
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a memory cell array, the memory cell array comprising a memory string including a plurality of memory cells connected in series, a first select transistor connected to one end of the memory string, a second select transistor connected to the other end of the memory string, a bit line connected to the memory string via the first select transistor, a source line connected to the memory string via the second select transistor, and word lines connected to control gate electrodes of the memory cells, respectively; and a control unit being configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation, the erase operation being an operation of applying an erase voltage to the memory cells for data erase, the erase verify operation being an operation of determining whether the data erase is completed, the step-up operation being an operation of raising the erase voltage by a first step-up value when the data erase is not completed, the control unit being configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, a number of erase voltage applications is more than a first number and less than a second number (the first number<the second number) and the control unit being configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.