Patent ID: 7323946
Filing Date: 2008-01-29
Classification: H03D,H03L,Y10S

Abstract:
1. A Phase Locked Loop (PLL), comprising: an extended lock detect circuit to monitor extended loss of lock, the extended lock detect circuit, in operation, monitoring a reference clock signal and a feedback clock signal and generating an extended lock detect signal when the reference clock and feedback clock signals are not synchronized for a first predetermined time; and a fast lock detect circuit to monitor temporary loss of lock due to transient events, the fast lock detect circuit, in operation, monitoring the reference clock and feedback clock signals and generating a fast lock detect signal when the reference clock and feedback clock signals are out of phase for a transient amount of time. a phase alignment detect circuit comprising (i) an XOR logic gate and (ii) a first filter, having a first resistor coupled to a first capacitor, wherein the phase alignment detect circuit generates a phase alignment detect signal when the reference clock and feedback clock signals have a phase difference greater than a predetermined phase, and wherein the predetermined phase depends on a resistance value associated with the first resistor and a capacitance value associated with the first capacitor.