Patent ID: 6911383
Filing Date: 2005-06-28
Classification: H01L

Abstract:
1. A method of forming an integrated semiconductor circuit comprising the steps of: providing a silicon-on-insulator structure comprising at least a top semiconductor layer located on a buried insulating layer, said top semiconductor layer having at least one patterned hard mask located in a FinFET region of the structure and at least one patterned hard mask located in a FET region of the structure; protecting the FET region and trimming the at least one patterned hard mask in said FinFET region, wherein each trimmed patterned hard mask in said FinFET region has a horizontal surface whose width is less than the width of that of each patterned hard mask in said FET region; etching exposed portions of the top semiconductor that are not protected with said hard masks stopping on said buried insulating layer, said etching defining a FinFET active device region and a FET active device region, said FinFET active device region being perpendicular to the FET active device region; protecting the FinFET active device region and thinning the FET active device region so that the FET device region has a height that is less than the height of the FinFET active device region; forming a gate dielectric on each exposed vertical surface of the FinFET active device region, while farming a gate dielectric on an exposed horizontal surface of the FET device region; and forming a patterned gate electrode on each exposed surface of the gate dielectric.