Patent ID: 8199596
Filing Date: 2012-06-12
Classification: G11C,H01L

Abstract:
1. A semiconductor device, comprising: a memory array having a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of data lines, a plurality of sense amplifier circuits having a first MISFET pair of a first conductivity type in which a gate of one MISFET of the first pair is directly connected to a drain of the other MISFET of the first pair, a second MISFET pair of the first conductivity type in which a gate of one MISFET of the second pair is directly connected to a drain of the other MISFET of the second pair, and a third MISFET pair of a second conductivity type in which a gate of one MISFET of the third pair is directly connected to a drain of the other MISFET of the third pair, a first source line connected to sources of the first MISFET pair, a second source line connected to sources of the second MISFET pair, a third source line connected to sources of the third MISFET pair, a first driving circuit to drive the first source line, a second driving circuit to drive the second source line, and a third driving circuit to drive the third source line, wherein in each of the plurality of sense amplifier circuits has: a drain of one MISFET in the first MISFET pair, a drain of one MISFET in the second MISFET pair, and a drain of one of MISFET in the third MISFET pair connected to one of the plurality of data lines, the drain of the other MISFET in the first MISFET pair, the drain of the other MISFET in the second MISFET pair, and the drain of the other MISFET in the third MISFET pair connected to another one of the plurality of data lines, channel lengths of MISFETs in the first MISFET pair are longer than channel lengths of MISFETs in the second MISFET pair, or channel widths of MISFETs in the first MISFET pair are wider than channel widths of MISFETs in the second MISFET pair, the second MISFET pair is arranged between the first MISFET pair and the third MISFET pair, and the first driving circuit, the second driving circuit, and the third driving circuit are dispersedly arranged between the second MISFET pair and the third MISFET pair.