Patent ID: 7398515
Filing Date: 2008-07-08
Classification: G06F

Abstract:
1. A method for ordered commands verification testing of a multiprocessor computer system comprising multiple parallel processor threads, comprising: providing at least one rule for forming a legal ordered sequence of semaphore test commands; forming a plurality of buckets of semaphore commands each comprising a plurality of the commands arranged in different sequentially ordered command sequences legal under the at least one rule; randomly selecting, ordering and combining a plurality of the buckets in a sequential bucket test combination having a test sequential order, the sequential bucket test combination having an ordered composite test command sequence, wherein an order of any of the buckets relative to another of the buckets within the test sequential order may be changed within the test sequential order, the test sequential order legal under the at least one rule and thereby generating a predictable result when executed by the threads; a semaphore manager sequentially distributing at least one of the composite test sequence commands to a first plurality of the processor threads in a first thread distribution; and observing the performance of each of the first plurality of threads in response to the distributed test commands.