Patent ID: 7619285
Filing Date: 2009-11-17
Classification: H01L

Abstract:
1. A CMOS transistor comprising: a semiconductor substrate; a first conductivity type MOS transistor which includes a gate insulating layer and a gate electrode stacked on the semiconductor substrate, and elevated source and drain regions which abut a channel region in the semiconductor substrate below the gate insulating layer and which are formed by elevated epitaxial layers, each including a first epitaxial layer formed in a first recess of the semiconductor substrate and a second epitaxial layer formed on the first epitaxial layer and extending to a level that is above an upper surface of the semiconductor substrate; and a second conductivity type MOS transistor which includes a gate insulating layer and a gate electrode stacked on the semiconductor substrate, and recessed source and drain regions which abut a channel region in the semiconductor substrate below the gate insulating layer and which are formed by recessed epitaxial layers, each including a first epitaxial layer formed in a second recess of the semiconductor substrate and a second epitaxial layer formed in the second recess on the first epitaxial layer; wherein the gate electrode of the first conductivity type MOS transistor is electrically connected to the gate electrode of the second conductivity type MOS transistor; and one of the source and drain regions of the first conductivity type MOS transistor is electrically connected to a corresponding one of the source and drain regions of the second conductivity type MOS transistor.