Patent ID: 8443017
Filing Date: 2013-05-14
Classification: G06F,G10L,G11B

Abstract:
1. A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit, the digital data processor comprising: an weighted addition circuit that is operable to perform weighted addition on at least the input signal and a signal being time-shifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit that is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit that is operable to attach a predetermined bits to an LSB side of the input signal to generate an intermediate signal of M bits; and an addition circuit that is operable to perform addition of the intermediate signal and the processed input signal so as to generate the M-bit output signal.