Patent ID: 6940129
Filing Date: 2005-09-06
Classification: H01L

Abstract:
1. A double gate MOS transistor comprising: a substrate active region defined in a semiconductor substrate; a transistor active region located over the substrate active region and overlapped with the substrate active region; at least one semiconductor pillar penetrating the transistor active region and being in contact with the substrate active region, the at least one semiconductor pillar supporting the transistor active region so that the transistor active region is spaced apart from the substrate active region; at least one bottom gate electrode substantially filling a space between the transistor active region and the substrate active region, the at least one bottom gate electrode being insulated from the substrate active region, the transistor active region and the semiconductor pillar; and at least one top gate electrode crossing over the transistor active region, and having at least one end that is in contact with a sidewall of the at least one bottom gate electrode, the at least one top gate electrode overlapping with the bottom gate electrode and being insulated from the transistor active region.