Patent ID: 6391704
Filing Date: 2002-05-21
Classification: H01L

Abstract:
A method for manufacturing an MDL semiconductor device including a DRAM device and a logic device on a semiconductor substrate having a DRAM device region and a logic device region comprising:forming a gate insulating layer and a gate conductive layer on a semiconductor substrate; forming first and second gate conductive layer patterns in first and second MOS regions, respectively, in a logic device region of the semiconductor substrate; forming first and second gate spacers on sidewalls of the first and second gate conductive layer patterns; injecting impurity ions of a first conductivity type onto the exposed first gate conductive layer pattern and the semiconductor substrate using a first mask layer pattern which exposes the first MOS region; injecting impurity ions of a second conductivity type onto the exposed gate conductive layer of the DRAM device region, the second gate conductive layer pattern of the logic device region, and the semiconductor substrate using a second mask layer pattern which exposes the DRAM device region and the second MOS region; forming a nitride layer which covers the gate conductive layer of the DRAM device, and covers the first and second gate conductive layers of the logic device region, the first and second gate spacers, and the exposed semiconductor substrate; forming gate conductive stacks, in which the gate conductive layer pattern of the DRAM device region and the nitride layer pattern are sequentially deposited using a third mask layer pattern which exposes parts of the nitride layer in the DRAM device region; forming gate spacers on the sidewalls of the gate conductive layer stacks of the DRAM device region; and forming self-aligned contact pads inter-insulated between the gate spacers of the DRAM device region.