Patent ID: 7471579
Filing Date: 2008-12-30
Classification: G11C

Abstract:
1. A semiconductor memory comprising: a plurality of main bit line pairs each composed of a main bit line and a complementary main bit line; a plurality of sub bit line pairs each composed of a sub bit line and a complementary sub bit line and respectively corresponding to said plurality of main bit line pairs; a plurality of word lines disposed to intersect said plurality of sub bit line pairs; memory cells disposed on intersecting points between said sub bit line and each of said word lines and between said complementary sub bit line and each of said word lines; a sub bit line hierarchical switch disposed correspondingly to each sub bit line between said sub bit line and a main bit line corresponding to said sub bit line; a complementary sub bit line hierarchical switch disposed correspondingly to each complementary sub bit line between said complementary sub bit line and a complementary main bit line corresponding to said complementary sub bit line; and a hierarchical switch control unit for turning off all of said sub bit line hierarchical switch and said complementary sub bit line hierarchical switch when a given signal is input.