Patent ID: 6127718
Filing Date: 2000-10-03
Classification: H01L

Abstract:
A semiconductor device comprising first and second device isolation regions formed by filling an insulator in isolation trenches of a semiconductor substrate and by performing flattening, and a well boundary perpendicular to a bottom surface of the first device isolation region and extending along a lengthwise direction of the first device isolation region, whereinan end of the second device isolation region in a lengthwise direction thereof obliquely intersects the lengthwise direction of the first device isolation region, at an intermediate portion of the first device isolation region,there are provided first, second, and third device regions isolated by the first and second device isolation regions,the first device region is adjacent to the first device isolation region and is arranged along the lengthwise direction of the first device isolation region in a first conductive type well,the second and third device regions are adjacent to the first device isolation region and is arranged along the lengthwise direction of the first device isolation region in a second conductive type well with the second device isolation region inserted therebetween,the second and third device regions are arranged such that a line intersecting the first device isolation region and extended from the first device region in a direction perpendicular to the well boundary passes at least one of the second and third device regions,at least one of a field effect transistor having a second conductive type channel and a bipolar transistor having a second conductive type collector is formed in the first device region, andat least one of a field effect transistor having a first conductive type channel or a bipolar transistor having a first conductive type collector is formed in the second and third device regions.