Patent ID: 9064799
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method comprising: forming a first plurality of fingers over an active area of a semiconductor substrate that is disposed in an area surrounded by a shallow trench isolation region, each of the first plurality of fingers having a respective length that extends in a direction that is parallel to width direction of the active area, the first plurality of fingers forming at least one gate of at least one transistor having a source and a drain formed by a portion of the active area; forming a first dummy polysilicon structure over a portion of the active area such that at least a portion of the first dummy polysilicon structure is disposed between an outer one of the first plurality of fingers and a first innermost edge of the shallow trench isolation region; and forming a second dummy polysilicon structure over the semiconductor substrate such that the second dummy polysilicon structure disposed between the first dummy polysilicon structure and a first edge of the semiconductor substrate.