Patent ID: 6898104
Filing Date: 2005-05-24
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory cell array having a plurality of memory cells; a first bit line connected to the memory cells and applied with a voltage read from each of the memory cells; a second bit line complementary to the first bit line, the second bit line being supplied with a reference voltage; a reference voltage generating circuit which generates the reference voltage, the reference voltage having temperature dependence which compensates a change in the voltage, read to the first bit line, due to temperature; and a sense amplifier which compares the voltage, read to the first bit line, with the reference voltage supplied to the second bit line, and amplifies the difference between the voltage and the reference voltage, wherein the reference voltage generating circuit controls the reference voltage of the sense amplifier so as to have a positive temperature dependency between a midpoint between an upper limit of distribution of “0” data and a lower limit of distribution of “1” data at a low temperature and a midpoint between the upper limit and the lower limit at a high temperature that is higher than the low temperature.