Patent ID: 6140950
Filing Date: 2000-10-31
Classification: H03M

Abstract:
A subtractor/integrator circuit that generates at an output node an output signal proportional to the sum of (a) an input signal multiplied by a predetermined scale factor N/M and (b) a reference signal, the subtractor/integrator circuit comprising:an input signal node to which the input signal is applied;a reference signal node to which the reference signal is applied;a bias signal node to which a bias signal is applied;an output circuit coupled to the bias signal node, the output circuit having an output coupled to the output node;N+M switched-capacitor circuits coupled to the input signal node, the reference signal node, the bias signal node and the output circuit; andcontrol circuitry coupled to the N+M switched capacitor circuits, the control circuitry causing each of the N+M switched capacitor circuits to sample the input signal a first predetermined number of times and to sample the reference signal a second predetermined number of times, wherein the ratio of the first predetermined number to the second predetermined number equals the scale factor N/M.