Patent ID: 7091608
Filing Date: 2006-08-15
Classification: H01L

Abstract:
1. A chip package, comprising: a package substrate with a first surface, a second surface and a slot penetrating the package substrate; a first patterned conductive layer disposed on the first surface of the package substrate, wherein the first patterned conductive layer has at least a signal terminal and at least a non-signal terminal, and the non-signal terminal is disposed around the slot; a second patterned conductive layer disposed on the second surface of the package substrate and around the slot; a conductive wall disposed on the inner surface of the slot, wherein the conductive wall connects the non-signal terminal of the first patterned conductive layer with the second patterned conductive layer; a chip disposed on the second surface of the package substrate to cover the slot, wherein the chip has at least a signal pad and at least a first non-signal pad, and the first non-signal pad is electrically connected to the second patterned conductive layer and the second patterned conductive layer is electrically connected to the non-signal terminal of the first patterned conductive layer through the conductive wall, and the slot in the package substrate exposes the signal pad; and at least a first conductive wire passing through the slot such that one end of the first conductive wire is connected to the signal pad and the other end of the conductive wire is connected to the signal terminal of the first patterned conductive layer.