Patent ID: 6850457
Filing Date: 2005-02-01
Classification: G11C

Abstract:
1. A circuit for remapping a specific row address bit to a specific column address bit, comprising: a first latch coupled to receive the specific row address bit, the latch being operable to store the specific row address bit responsive to a row address store signal and to then output the stored row address bit; a second latch coupled to receive a first set of column address bits and the specific column address bit, the latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and a selector operable to select either the specific column address bit output from the first latch or the specific column address bit output from the second latch, the selected address bit being combined with the column address bits in the first set.