Patent ID: 6423589
Filing Date: 2002-07-23
Classification: H01L

Abstract:
A CMOS integrated circuit fabricating method comprising the steps of:forming an NMOS transistor and a PMOS transistor in an integrated circuit substrate, the NMOS transistor and the PMOS transistor each including a gate, and a source/drain on opposing sides of the gate; forming an insulating layer on the integrated circuit substrate, the insulating layer including a contact hole therein, the contact hole exposing a portion of one of the source/drains; forming a compensating region through the contact hole into the one of the source/drains, the compensating region being of opposite conductivity from the one of the source/drains and being configured to shield the one of the one of the source/drains from an adjacent well in the integrated circuit substrate having a same conductivity type as the one of the source/drains.