Patent ID: 6937081
Filing Date: 2005-08-30
Classification: H03K,H03L

Abstract:
1. A delay producing method which uses first-stage to N th stage delay elements connected in series to each other and which, when a clock signal is inputted to a first delay stage node of said first-stage delay element, said delay producing method produces the clock signal through the first delay stage node and delayed signals outputted through second to (N+1) th delay stage nodes of the second through the N th delay elements, respectively, said delay producing method for producing an even clock signal and an odd clock signal comprising: using a first-stage selector and second-stage to (N+1) using, as one of inputs given to each of said first-stage selector to (N+1) using, as the other of inputs given to each of said first-stage selector and the second-stage to (N+1)