Patent ID: 8958252
Filing Date: 2015-02-17
Classification: G11C

Abstract:
1. A signal processing circuit comprising: an arithmetic portion; a memory; and a control portion configured to control the arithmetic portion and the memory, wherein the control portion includes a first memory circuit and a second memory circuit for storing data held in the first memory circuit, wherein the second memory circuit includes a first transistor and a first capacitor, wherein a first electrode of the first capacitor is electrically connected to a first node which is set in a floating state when the first transistor is turned off, wherein the memory includes a plurality of third memory circuits arranged in matrix, wherein the plurality of third memory circuits each includes a second transistor and a second capacitor, wherein a first electrode of the second capacitor is electrically connected to a second node which is set in a floating state when the second transistor is turned off, and wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer.