Patent ID: 8068362
Filing Date: 2011-11-29
Classification: G11C

Abstract:
1. A non-volatile semiconductor memory device comprising: a non-volatile memory cell array for storing at least two bits including a least significant bit (LSB) and a most significant bit (MSB) by using different threshold voltages in each of memory cells of the memory cell array; a control circuit for controlling a data reading operation to the memory cell array; and a buck circuit; wherein when the memory cells coupled to a first word line perform the data reading operation, the memory cells coupled to a second word line adjacent to the first word line are examined to determine whether a writing operation of the MSB is performed; wherein if the writing operation of the MSB is performed, the buck circuit reduces a pre-charge voltage of a bit line performing a data reading operation to the memory cells coupled to the first word line by a predetermined voltage for canceling out the raising of threshold voltages caused by coupling effect between gates of storage nodes in the memory cells coupled to two adjacent word lines.