Patent ID: 8373495
Filing Date: 2013-02-12
Classification: H03K

Abstract:
1. An apparatus comprising: a first pin; a second pin; a first MOS transistor that receives a first control signal at its gate; a current mirror that is coupled to the drain of the first MOS transistor; a second MOS transistor that is coupled to the current mirror at its source; a pass circuit that is coupled between the first and second pins, wherein the pass circuit is coupled to the current mirror so as to receive a bias voltage, and wherein the pass circuit is coupled to the gate of the second MOS transistor so as to receive a control voltage, and wherein the pass circuit includes: a fifth MOS transistor that is coupled to the gate of the second MOS transistor at its drain and that receives a second control signal at is gate; and a sixth MOS transistor that is coupled to the current mirror so as to receive the bias voltage at its drain and that receives the second control signal at is gate.