Patent ID: 6850449
Filing Date: 2005-02-01
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a sense amplifier; first and second word lines; first and second bit lines coupled to said sense amplifier; a first memory cell coupled to said first word line and said first bit line; and a second memory cell coupled to said second word line and said second bit line; wherein, in a normal mode, the first and second word lines are assigned separate addresses from each other, and data access operation is performed in the first and second memory cells separately; whereas in a partial mode, the first and second word lines are assigned the same address to maintain one bit data in the first and second memory cells; wherein, in order to copy a data in the first memory cell into the second memory cell, based on a switching from the normal mode to the partial mode, the second word line is activated in a precharge period for the first and second bit lines, so that a precharge voltage is written into the second memory cell; then, the first word line is activated; and then, the sense amplifier is activated to amplify a differential voltage between the first and second bit lines to store said data stored in said first memory cell into said second memory cell.