Patent ID: 8458464
Filing Date: 2013-06-04
Classification: G06F

Abstract:
1. An apparatus comprising: memory; non-volatile memory; a cache memory; a processor coupled with the cache memory, the processor comprising: logic to cause the processor to enter a first mode by transferring a nub loader into an isolated area of the memory, copying a processor nub from the non-volatile memory to the isolated area of the memory, and verifying and placing a representation of the processor nub into hardware protected memory, in response to a first instruction, wherein the first mode is to be indicated by a first mode bit, and wherein the first mode corresponds to a different security level than a normal mode of the processor, and wherein in the first mode a first program is to control access to a secure portion of the cache memory using a translation look-aside buffer; a flash interface to communicate with a flash memory; a universal serial bus (USB) interface to communicate with a USB device; and a boot read only memory (ROM) to store a boot code.