Patent ID: 6766500
Filing Date: 2004-07-20
Classification: G06F

Abstract:
A method for placing circuit elements on an integrated circuit, the method comprising:a) synthesizing a high level description of a circuit to produce a circuit design; b) placing cells of said circuit design by use of one of b1) non-direct timing driven processes, and b2) direct timing driven processes; c) routing wiring to connect said cells, thereby generating a layout; d) modifying cell area allocations in said layout, if necessary to relieve congestion; e) performing a post-layout synthesis optimization with said cells; and f) providing and incremental placement of said cells, wherein one of b1 and b2) is performed during a pass including c), d), e), and f), wherein b1) is performed during a first pass, and wherein b2) is performed during any subsequent pass.