Patent ID: 6187660
Filing Date: 2001-02-13
Classification: H01L,Y10S

Abstract:
A method for isolating a conducting layer in an integrated circuit structure, said method comprising:depositing a first dielectric layer upon a substrate;depositing an electrically conducting layer on said first dielectric layer;forming a first opening extending through said first dielectric layer and said electrically conducting layer to said substrate, said first opening having a sidewall defined by edges of said first dielectric layer and said electrically conducting layer;depositing a second dielectric layer on said electrically conducting layer and in said opening, with a first portion of said second dielectric layer deposited on said electrically conducting layer and a second portion deposited in said first opening, said second portion covering at least some of said sidewall of said first opening;forming a secondary opening extending through said second portion of said second dielectric layer to said substrate to expose a portion of said substrate within said first opening; andforming a third opening extending through said first portion of said second dielectric layer to said electrically conducting layer to expose a portion of said electrically conducting layer.