Patent ID: 7087461
Filing Date: 2006-08-08
Classification: H01L

Abstract:
1. A process for making a plurality of leadless semiconductor packages, comprising the steps of: providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement, a plurality of dambars between the units, and a first metal layer formed on the upper surface of the lead frame, each unit of the lead frame including a die pad and a plurality of leads each having a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion; attaching a plurality of chips onto the die pads of the lead frame, wherein each of the chips has a plurality of bonding pads on an active surface thereof; electrically coupling each lead of the lead frame to two different bonding pads of one of the chips such that the first portion of each lead is electrically connected to one bonding pad and the second portion of each lead is electrically connected to the other bonding pad; encapsulating the chips against the upper surface of the lead frame to form a molded product; selectively plating a second metal layer on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product wherein the second metal layer is not provided on the third portions of the leads; selectively etching away the third portion of each lead of the lead frame such that the first portion and the second portion are electrically isolated from each other; and conducting a singulation step to obtain the leadless semiconductor packages.