Patent ID: 8086766
Filing Date: 2011-12-27
Classification: G06F

Abstract:
1. A system for receiving messages in a parallel computing device having a plurality of nodes, each node having multiple processor units and an associated memory operatively connected therewith via an interconnect device, said messaging system comprising at each node: a plurality of receiver devices for receiving message packets from a network, a network reception queue associated with a receiver device, each network reception queue adapted to buffer said received packet, a reception control unit for receiving information from a processor at a node for handling of packets received over a network; and, a plurality of DMA engine units, each unit operatively connected with the reception control unit and configured to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a reception memory FIFO (rmFIFO) of the associated memory based on said information, said control unit implementing logic to determine whether any prior received packet for that reception memory FIFO is still in a process of being stored in said associated memory by another DMA engine unit of said plurality, and prevent said one DMA engine unit to indicate completion of storing said current packet until all prior received packets associated with that reception memory FIFO are completely stored by said other DMA engine units, wherein multiple packets destined to a single rmFIFO are transferred and stored in parallel to predetermined locations in said associated memory.