Patent ID: 6046626
Filing Date: 2000-04-04
Classification: H02M

Abstract:
A booster circuit comprising:a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal;a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a first clock signal;a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the first clock signal;a capacitor having a first terminal connected to the second node and a second terminal supplied with a second clock signal having an inverse phase of the first clock signal;a fourth MOS transistor of the first channel type having a drain terminal connected to the second node, a source terminal connected to a fourth node through which an output voltage is obtained, and a gate terminal;a fifth MOS transistor of the first channel type having a source terminal connected to the fourth node, a drain terminal connected to the gate terminal of the fourth MOS transistor, and a gate terminal connected to the second node; anda sixth MOS transistor of the second channel type having a drain terminal connected to the drain terminal of the fifth MOS transistor, a source terminal connected to the third node, and a gate terminal supplied with the second clock signal.