Patent ID: 7439567
Filing Date: 2008-10-21
Classification: G11C,H01L

Abstract:
1. A non-volatile memory array with a plurality of memory transistors having X-Y alignment on a semiconductor substrate comprising: a plurality of spaced apart, parallel, conductive, word line stripes over a substrate extending in the X-direction; a plurality of spaced apart pairs of conductive floating gate members beneath each of the word lines but above the substrate, with pairs of floating gate members beneath different word lines having regions aligned in the X-direction, the pairs of floating gate members associated with a tunnel window region with each pair of floating gate members aligned such that tunnel window regions of a pair of floating gate members are in a single tunnel window stripe extending in the Y-direction under the pair of floating gate members, the plurality of pairs of floating gate members having a plurality of corresponding spaced apart, parallel tunnel window stripes; and a plurality of spaced apart, parallel, conductive source/drain stripes running under pairs of conductive floating gate members within the substrate, each source/drain stripe electrically shared by adjacent floating gate members; whereby two adjacent source/drain stripes and one word line are electrically selected to write and to erase at least one conductive floating gate member acting as a single non-volatile memory transistor corresponding to a single X-Y location, with a plurality of such transistors at different X,Y locations constituting a memory array.