Patent ID: 6452824
Filing Date: 2002-09-17
Classification: G11C

Abstract:
A semiconductor device comprising:first and second memory cell regions, each having first and second bit lines and first and second word lines arranged in common the first and second memory cell regions, the first word line being arranged substantially orthogonal to the first and second bit lines and the second word line being arranged above and substantially in parallel to the first word line, a plurality of memory cells being connected to the first and second bit lines and the first word line; a first contact region which is arranged between the first and second memory cell regions and in which the first word line arranged in common in the first and second memory cell regions is connected to the second word line arranged above and in parallel to the first word line; third and fourth memory cell regions, each having third and fourth bit lines and third and fourth word lines arranged in common in the third and fourth memory cell regions, the third word line being arranged substantially orthogonal to the third and fourth bit lines and the fourth word line being arranged above and substantially in parallel to the third word line, a plurality of memory cells being connected to the third and fourth bit lines and the third word line; a second contact region which is arranged between the third and fourth memory cell regions and in which the third word line arranged in common in the third and fourth memory cell regions is connected to the fourth word line arranged above and in parallel to the fourth word line; first and second sense amplifier regions each having a sense amplifier circuit, the first sense amplifier region being arranged between the first and third memory cell regions and the second sense amplifier region being arranged between the second and fourth memory cell regions; an open space arranged between the first and second sense amplifier regions and between the first and second contact regions and having a switch circuit; a first data line arranged in parallel to the first and third word lines and selectively connected to one of the first bit line arranged in the first memory cell region and the third bit line arranged in the third memory cell region; and a second data line arranged orthogonal to the first data line, the second data line being selectively connected to the first data line by the switch circuit formed in the open space.