Patent ID: 6016270
Filing Date: 2000-01-18
Classification: G11C

Abstract:
Flash EEPROM circuitry that includes a flash memory cell array that is subdivided into a plurality of array blocks, and wherein each array block includes a plurality of flash memory cells, the flash EEPROM circuitry comprising:an address bus connected to each array block for providing address information to the array blocks;erase/reprogram operation circuitry connected to said address bus, the erase/reprogram operation circuitry being responsive to erase/reprogram operation address information provided on said address bus, the erase/reprogram operation address information identifying a first array block in which an erase/reprogram operation is to be performed, by performing the erase/reprogram operation in the first array block;read operation circuitry connected to said address bus, the read operation circuitry being responsive to read operation address information provided on said address bus during performance of the erase/reprogram operation in the first array block, the read operation address information identifying a second array block in which a read operation is to be performed, by performing the read operation in the second array block simultaneously with the erase/reprogram operation being performed in the first array block.