Patent ID: 7589554
Filing Date: 2009-09-15
Classification: G11C

Abstract:
1. An input/output interface circuit of an integrated circuit, comprising: a plurality of transistor pairs; an input/output terminal being connected to a connection point of each transistor pair of the plurality of transistor pairs; and a controller controlling switching of each transistor of the plurality of transistor pairs to constitute an output buffer in output mode and a termination circuit in input mode, and controlling output impedance of the output buffer and load impedance of the termination circuit to be a predetermined value, wherein said plurality of transistor pairs constitute a driver including a primary driver and a secondary driver, and the controller comprises a drive controller controlling switching of each transistor of the driver, and an impedance controller outputting an impedance control signal to the drive controller which generates a control signal for controlling said secondary driver and for controlling impedance of the driver based on a reference resistance, wherein said primary driver is controlled other than by said impedance controller, and wherein said drive controller comprises a first NAND gate having as an input an inverted output signal from said integrated circuit and an output enable signal, and a second NAND gate having as an input said output signal from said integrated circuit and said output enable signal, said primary driver comprising a transistor pair including a first transistor which is controlled by an inverted output of said first NAND gate, and a second transistor which is controlled by an output of said second NAND gate.