Patent ID: 7465639
Filing Date: 2008-12-16
Classification: H01L

Abstract:
1. A method for fabricating a silicon on insulator (SOI) device comprising a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer, the method comprising the steps of: forming a dielectric isolation region extending through the monocrystalline silicon layer; etching an opening extending through the dielectric isolation region and the buried insulator region to expose a portion of the silicon substrate; doping a portion of the silicon substrate exposed through the opening with a conductivity determining dopant of a first conductivity type; doping a portion of the monocrystalline silicon layer with impurity dopants of a second conductivity type to form a first plate of a capacitor; forming an insulator layer overlying the portion of the monocrystalline silicon layer; forming a conductive electrode overlying the insulator layer to form a second plate of the capacitor; coupling a first bus to the first plate of the capacitor and to the doped portion of the silicon substrate; and coupling a second bus to the second plate of the capacitor.