Patent ID: 6800557
Filing Date: 2004-10-05
Classification: G09G,H01L,Y10S

Abstract:
A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:(a) forming an insulating film over a first major surface of a wafer; (b) forming a wiring groove in the insulating film by patterning the insulating film; (c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove; (d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method with a first polishing pad so as to leave the metal layer in the wiring groove; (e) after step (d), performing pre-cleaning of the first major surface of the wafer by rubbing the first major surface of the wafer with a second polishing pad provided with a liquid chemical or cleaning water; (f) after step (e), transferring the wafer to a post cleaning portion of a single wafer processing apparatus; (g) after step (f), performing scrub or brush cleaning of the first major surface of the wafer with a liquid chemical; and then (h) making the first major surface of the wafer dry, wherein steps (d) to (h) are performed in the single wafer processing apparatus, which has light shielding structure keeping an illuminance of the inside of the apparatus at 100 lux or less, and step (f) includes the substep of: (i) keeping the first major surface of the wafer wet with a water shower.