Patent ID: 6340973
Filing Date: 2002-01-22
Classification: G06F,G11C

Abstract:
A memory control unit for controlling a synchronous memory composed of a plurality of banks for reading and writing data using a clock, said memory control unit comprising:a transfer-target device operable to output commands for data reading and data writing; an address generating device operable to receive the commands, generate and output previously-determined control signals in accordance with the commands, and output a transfer size of read data in one bank of the plurality of banks to which processing is to be performed; a command generating device operable to generate and output the clock, receive the control signals, generate and output previously-determined control commands in accordance with the control signals, and thereby control the synchronous memory; a counter operable to count a number of times of issuing read commands by said command generating device, and receive the transfer size to subtract a burst length from the transfer size with each count; and a data processing device operable to receive the control commands, and mediate data transfer between said transfer-target device and the synchronous memory in accordance with the control commands; wherein said counter, when the transfer size after the subtraction becomes not more than the burst length, notifying said command generating device of the fact, and in response to the notification, said command generating device issuing a next read command as a read command with precharge for automatically performing precharge processing after the read processing is terminated.