Patent ID: 6112022
Filing Date: 2000-08-29
Classification: G06F

Abstract:
A method for simulating timing and signal characteristics at a pin of a circuit design including a plurality of input pins, a plurality of output pins, one or more clock pins, and a plurality of interconnected circuit components connected to said input/output/clock pins and having a plurality of identifiable nodes, comprising the steps of:defining a circuit pattern the position or positions of which is to be located in said circuit design;identifying the one or more locations where said circuit pattern resides in said circuit design;tracing from an input/output/clock pin of said circuit design to one or more of the identified circuit pattern locations to identify a particular interconnecting sub-circuit;extracting and storing a description of said interconnecting sub-circuit;assigning user specified parameters to said description of said interconnecting subcircuit; andsimulating the sub-circuit using said description to generate a signal having the timing and signal characteristics of the signal generated by said circuit design at said pin.