Patent ID: 9158541
Filing Date: 2015-10-13
Classification: G06F

Abstract:
1. A processor that implements an instruction set architecture that aliases architected registers having different sizes, comprising: a physical register file comprising a plurality of physical registers configured to store data; and a register renamer distinct from the physical register file that, during operation, renames architected registers to corresponding physical registers, wherein the register renamer is organized into independently accessible even and odd banks, wherein the even bank and the odd bank each include a respective plurality of entries; wherein to rename a first architected register of a first size, the register renamer, during operation, stores an identifier of a first one of a pair of physical registers within an entry selected from the even bank, and stores an identifier of a second one of the pair of physical registers within an entry selected from the odd bank; wherein to rename a second architected register of a second size that is smaller than the first size, the register renamer, during operation, stores an identifier of one of the physical registers within an entry selected from either the even bank or the odd bank.