Patent ID: 6330200
Filing Date: 2001-12-11
Classification: G11C

Abstract:
A synchronous semiconductor memory device, comprising:a first terminal group receiving as inputs a first data group in a normal operation mode and receiving as inputs said first data group and a second data group time divisionally in accordance with an external clock in a test mode;a second terminal group receiving as inputs the second data group in the normal operation mode;a first internal circuit operating in accordance with said first data group;a second internal circuit operating in accordance with said second data group; anda test control circuit receiving said first data group from said first data terminal group and outputting the first data group to said first internal circuit and receiving said second data group from said second data terminal group and outputting the second data group to the second internal circuit, in the normal operation mode, and receiving said first and second data groups from said first input terminal group and outputting the first data group and the second data group to said first internal circuit and said second internal circuit, respectively, in the test mode.