Patent ID: 7499312
Filing Date: 2009-03-03
Classification: G11C

Abstract:
1. An SRAM memory array comprising: a plurality of memory cells, each of said plurality of memory cells further comprising: a device, each of said plurality of memory cells having seven of said device; a first storage node; a second storage node; and a first local bit line; said first storage node and said second storage node store true and complement of data and are constructed with six of said device forming a cross-coupled flip-flop cell, one of said device being configured as a first read-pass device, said second storage node is connected to said first read-pass device, said first read-pass device passes the state of said second storage node to said first local bit line effectuating single ended sensing, said first read-pass device gate is connected to a first read word line, wherein said device is a transistor, nFET, or pFET; a first global bit line, one of said device configured as a first read-head nFET for selectively discharging to ground a previously precharged said first global bit line effectuating passing by way of said first read-head nFET the inverse of a first signal on said first local bit line to said first global bit line, said first local bit line is connected to 1 or more other said plurality of memory cells, said first global bit line passing said first signal to a first sense amplifier.