Patent ID: 6438042
Filing Date: 2002-08-20
Classification: G11C,H01L

Abstract:
A semiconductor memory device comprising:a memory cell array having a first bitline, a second bitline parallel with the first bitline, and memory cells coupled to the first and second bitlines, a sense amplifier circuit for sensing a potential difference between the first and second bitlines; a first isolation transistor for electrically connecting/isolating the first bitline to/from the sense amplifier circuit, the first isolation transistor having a source region, a drain region, and a gate; a second isolation transistor for electrically connecting/isolating the second bitline to/from the sense amplifier circuit, the second isolation transistor having a source region, a drain region, and a gate; and a MOS transistor having a source region that coincides with the source region of one of the first and second isolation transistors.