Patent ID: 6544829
Filing Date: 2003-04-08
Classification: H01L

Abstract:
In a CMOS process flow, a method of fabricating a substantially completely silicided polysilicon gate electrode, the improvement comprising the steps of:a) forming a hard mask material on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer and a well region disposed between isolation structures, b) removing portions of the hard mask material to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, and leave exposed second portions of the unpatterned polysilicon layer and the gate oxide layer, c) exposing the integrated circuit substrate to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, to define source drain regions in the well region, d) removing the exposed second portions of the unpatterned polysilicon layer to define polysilicon gate electrode precursors under the gate electrode masks, e) removing the gate electrode masks from the polysilicon gate electrode precursors, f) depositing a metal layer over the polysilicon gate electrode precursors and the source drain regions, and g) annealing the integrated circuit substrate to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, and also to form silicide contacts in the source drain regions.