Patent ID: 6518141
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for manufacturing an RF integrated circuit comprising the steps of:(a1) forming an insulating layer on a silicon wafer, and selectively etching the insulating layer to form a plurality of windows that expose the silicon wafer; (b1) forming an epitaxial silicon layer over an entire surface of the insulating layer by an epitaxial growth method using portions of the silicon wafer exposed through the windows, and planarizing the epitaxial silicon layer; (c1) selectively etching the epitaxial silicon layer to realize a plurality of epitaxial silicon layers, in which the epitaxial silicon layers of each window region are separated; (d1) forming semiconductor elements on the epitaxial silicon layers; (e1) forming a PMD layer on the epitaxial silicon layers, and selectively etching the PMD layer to form contact holes for exposing portions of electrodes of the semiconductor elements; (f1) providing metal plugs in the contact holes, and forming and patterning a metal film to realize a first metal wiring layer; (g1) forming an IMD layer over the first metal wiring layer, and selectively etching the IMD layer such that portions of the first metal wiring layer are exposed to form via holes; (h1) providing metal plugs in the via holes to form vias, and forming and patterning a metal film on the IMD layer to form a second metal wiring layer; and (i1) forming a capping layer on the second metal wiring layer, and removing the silicon wafer.