Patent ID: 8933745
Filing Date: 2015-01-13
Classification: H03D,H03H

Abstract:
1. A transconductance enhanced passive frequency mixer, comprising a transconductance stage with enhanced transconductance, a passive frequency mixing switch pair, and an output transresistance amplifier, wherein, the transconductance stage employs a pre-amplified transconductance enhancement structure with enhanced transconductance and converts input RF voltage into RF currents, which is frequency mixed via a dual balanced frequency mixing switch pair, and then converted into IF voltage output via a transconductance enhanced load output stage after frequency mixing; a transconductance/amplifier stage, a frequency mixer stage, a bias circuit, and a load output stage; the transconductance/amplifier stage comprises P-channel metal oxide field-effect transistors (hereinafter referred to as PMOS transistors) PM 0 and PM 1 , and N-channel metal oxide field-effect transistors (hereinafter referred to as NMOS transistors) NM 0 and NM 1 , and cross-coupled capacitor and LC resonant circuits; the bias voltages of PM 0 and PM 1 are obtained from bias voltage 1 via resisters R 0 and R 1 respectively; circuit components L 0 , C 2 , C 3 , and C 4 are used to enhance transconductance; the RF currents output from the transconductance stage are led out between resisters R 2 and R 4 and between resisters R 3 and R 5 respectively; the currents are coupled to the frequency mixing switch stage via circuit components C 5 and C 6 respectively; in the mixer stage, PMOS transistors PM 2 -PM 5 being used as a core circuit, and the frequency mixing results are outputted from the drain electrodes of PMOS transistors PM 2 and PM 5 , wherein, the drain electrodes of PMOS transistors PM 2 and PM 4 are short connected, and the drain electrodes of PMOS transistors PM 3 and PM 5 are short connected; the load output stage mainly comprises PMOS transistors PM 6 -PM 15 and NMOS transistors NM 2 -NM 3 ; PM 6 , PM 7 , PM 10 , PM 11 , NM 2 , and NM 3 constitute the first stage differential amplification circuit of the load output stage, and the bias of NM 2 and NM 3 is provided by bias voltage 2 ; the electrodes are outputted from the drain terminals of PM 6 and PM 7 , and connected to a second stage of differential source follower constituted by PM 8 , PM 9 , PM 12 , and PM 13 ; then, the signals are outputted from the drain electrodes of PM 12 and PM 13 , and connected to a third stage of differential common-source amplification circuit constituted by PM 14 , PM 15 , R 6 , and R 7 ; finally, IF signals are outputted from the drain terminals of PM 14 and PM 15 ; the upper plates of capacitors C 0 and C 1 are connected to the positive input signal terminal and negative input signal terminal respectively; the lower plate of C 0 is connected to the gate electrode of PM 0 ; the lower plate of C 1 is connected to the gate electrode of PM 1 ; the upper plate of capacitor C 2 is connected to the drain terminal of PM 0 , the upper plate of capacitor C 3 is connected to the drain terminal of PM 1 , the lower plate of C 2 is connected to the lower plate of C 4 , the lower plate of C 3 is connected to the upper plate of C 4 , the upper plate of C 4 is connected to the positive terminal of L 0 , the lower plate of C 4 is connected to the negative terminal of L 0 , the positive terminal of L 0 and the upper plate of C 4 are connected to the gate electrode of NM 1 , and the negative terminal of L 0 and the lower plate of C 4 are connected to the gate electrode of NM 0 ; the source electrodes of PM 0 and PM 1 are connected to the supply voltage, the positive terminal of resistor R 0 is connected to the gate electrode of PM 0 , the negative terminal of R 0 is connected to the positive terminal of resistor R 1 , and the negative terminal of R 1 is connected to the gate electrode of PM 1 ; the positive terminal of resistor R 2 is connected to the drain terminal of PM 0 , the negative terminal of R 2 is connected to the positive terminal of R 4 , and the negative terminal of R 4 is connected to the drain electrode of NM 0 ; the positive terminal of resistor R 3 is connected to the drain terminal of PM 1 , the negative terminal of R 3 is connected to the positive terminal of R 5 , and the negative terminal of R 5 is connected to the drain electrode of NM 1 ; the source electrodes of NM 0 and NM 1 are grounded; the upper plate of RF coupling capacitor C 5 is connected to the negative terminal of R 2 and positive terminal of R 4 , the upper plate of RF coupling capacitor C 6 is connected to the negative terminal of R 3 and positive terminal of R 5 , the lower plate of C 5 is connected to the source electrodes of PM 2 and PM 3 , and the lower plate of C 6 is connected to the source electrodes of PM 4 and PM 5 ; the positive terminal of local oscillator signal is connected to the gate electrodes of PM 3 and PM 4 , and the negative terminal of local oscillator signal is connected to the gate electrodes of PM 2 and PM 5 ; the drain electrodes of PM 2 and PM 4 are connected to the upper plate of C 7 , and the drain electrodes of PM 3 and PM 5 are connected to the lower plate of C 7 ; the positive output of the switch stage (i.e., the upper plate of C 7 ) is connected to the source electrode of PM 6 and drain electrode of PM 10 in the load stage, the negative output of the switch stage (i.e., the lower plate of C 7 ) is connected to the source electrode of PM 7 and drain electrode of PM 11 in the load stage; the gate electrodes of PM 6 and PM 7 are connected to bias voltage 4 for bias; the drain electrode of PM 6 is connected to the drain electrode of NM 2 and gate electrode of PM 8 ; the drain electrode of PM 7 is connected to the drain electrode of NM 3 and gate electrode of PM 9 ; the drain electrodes of PM 8 and PM 9 are grounded, forming a source follower; the source electrodes of NM 2 and NM 3 are grounded, and the gate electrodes of NM 2 and NM 3 are connected to bias voltage 2 for bias; the source electrodes of PM 10 -PM 15 are connected to the supply voltage; the source electrode of PM 8 is connected to the drain electrode of PM 12 and gate electrode of PM 14 ; the source electrode of PM 9 is connected to the drain electrode of PM 13 and gate electrode of PM 15 ; the drain electrode of PM 14 serves as the positive terminal of output voltage and is connected to the positive terminal of resistor R 7 , and the negative terminal of R 7 is grounded; the drain electrode of PM 15 serves as the negative terminal of output voltage and is connected to the positive terminal of resistor R 8 , and the negative terminal of R 8 is grounded.