Patent ID: 9143135
Filing Date: 2015-09-22
Classification: H03K

Abstract:
1. A fractional frequency divider circuit comprising: a first frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N (each of N and CTS is an integer); a clock addition circuit configured to add one clock to an output of the first frequency divider circuit; a counter that counts the number of cycles of the output of the first frequency divider circuit by a carry of the first frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the first frequency divider circuit as an output clock when the match is not detected.