Patent ID: 6291255
Filing Date: 2001-09-18
Classification: H01L

Abstract:
A method for fabricating a TFT (Thin Film Transistor) comprising:forming a first conductive layer on a transparent substrate;patterning said first conductive layer to form a first conductive pattern on said transparent substrate;forming a first insulating layer on said first conductive pattern and said exposed transparent substrate;forming a second conductive layer on said first insulating layer;patterning said second conductive layer to form a second conductive pattern on said first insulating layer, said second conductive pattern being positioned over the first conductive pattern;forming a second insulating layer on said second conductive pattern and said exposed first insulating layer;forming a third insulating layer on said second insulating layer;baking said first conductive pattern, said first insulating layer, said second conductive pattern, said second insulating layer, and said third insulating layer;etching a portion of said third insulating layer, a portion of said second insulating layer, and a portion of said first insulating layer to form a first contact hole and a second contact hole in said third insulating layer, said second insulating layer, and said first insulating layer as well as to expose a first portion of said first conductive pattern and a second portion of said first conductive pattern, said first contact hole and said second contact hole being positioned at both ends of said first conductive pattern;forming a third conductive layer in said first contact hole, in said second contact hole, and said third insulating layer;patterning said third conductive layer to form a source conductive pattern and a drain conductive pattern on said third insulating layer; andetching said third insulating layer using said source conductive pattern and said drain conductive pattern as a mask until said second insulating layer is exposed to form said TFT on a TFT panel, said second conductive pattern being a gate of said TFT, said source conductive pattern and drain conductive pattern being source and drain of said TFT, transmittance of said TFT panel after etching said third insulating layer being larger than transmittance of said TFT panel before etching said third insulating layer.