Patent ID: 6088413
Filing Date: 2000-07-11
Classification: H04J

Abstract:
An apparatus for use in a desynchronizer for controlling jitter in the output of the desynchronizer, the desynchronizer for extracting a lower rate signal S.sub.L from an input higher rate signal S.sub.H, both signals organized as successive frames of data, each frame of the higher rate signal providing for justification opportunities, the higher rate signal including an overhead part and a payload part of each frame, the overhead part of each frame indicating use of justification opportunities in the frame, the desynchronizer including a bit buffer and a means for causing the bit buffer to write to its internal memory all bits of the lower rate signal S.sub.L and only bits of the lower rate signal S.sub.L, thereby causing a certain buffer fill of the bit buffer, the buffer fill decreasing as bits of the S.sub.L signal are caused to be read out of the bit buffer, and the desynchronizer further including a means for providing use of justification opportunities in each S.sub.H frame based on encoding in the overhead part of the S.sub.H frame, the apparatus for controlling jitter comprising:a) a phase detector responsive to signals provided by the bit buffer useful in determining the buffer fill, for providing an indication of the buffer fill;b) a leak circuit and a digitally-controlled oscillator (DCO), the leak circuit responsive to a signal for each frame of the higher rate signal indicating justification use in the frame, the leak circuit for providing a phase-adjust command, the DCO responsive to the phase-adjust command and providing as a DCO output signal pulses used for clocking data out of the bit buffer at a rate that depends on the phase-adjust command;wherein the leak circuit determines an average incoming justification bit rate based on the signals indicating justification use and received in a sliding time window and then determines a corresponding leak interval indicating how long to wait to issue a next phase-adjust command; wherein the DCO has a means for clocking at a rate M f.sub.L substantially greater than the rate f.sub.L of the lower rate signal S.sub.L ; wherein the leak circuit waits until the preceding leak interval has expired before sending the next phase-adjust command to the DCO; and wherein in response to a phase-adjust command the DCO adjusts the phase of its output signal by a predetermined fraction of the period of the lower rate signal S.sub.L specified in terms of the rate M f.sub.L of the means for clocking the DCO.