Patent ID: 6356327
Filing Date: 2002-03-12
Classification: G02F

Abstract:
A process for forming a pixel array comprising the steps of:forming a first dielectric layer over a lower interconnect metallization layer; forming a second dielectric layer over the first dielectric layer; patterning a window photoresist mask over the second dielectric layer, the window photoresist mask masking a pixel region and exposing an inter-pixel region; creating a window in the second dielectric layer by etching inter-pixel regions to stop on the first dielectric layer; removing the window photoresist mask; forming a reflective metal layer over the second dielectric layer and within the window; removing the reflective metal layer outside of the window; forming a third dielectric layer over the reflective metal layer and the second dielectric layer; forming a via by etching through the third dielectric layer, the second dielectric layer, and the first dielectric layer to stop on the interconnect metallization layer; filling the via with electrically conducting material; and forming a pixel electrode within the pixel region.