Patent ID: 6522584
Filing Date: 2003-02-18
Classification: G11C

Abstract:
A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage comprising at least one gate voltage pulse; and applying the gate voltage for a period of time corresponding to a selected threshold voltage for the memory cell corresponding to a selected one of the programming states, wherein each selected threshold voltage corresponds to a different period of time.