Patent ID: 6200902
Filing Date: 2001-03-13
Classification: H01L

Abstract:
A method of forming a semiconductor device, comprising:forming first and second floating gates apart from each other over a flash memory cell portion of a semiconductor substrate;forming first and second control gates apart from each other over said first and second floating gates respectively;forming first and second insulating film apart from each other on said first and second control gate;forming side walls formed on side surfaces of said first and second floating gates, said first and second control gates, and said first and second insulating films, thereby forming a groove between both said first floating gate, said first control gate and said first insulating film and both said second floating gate, said second control gate and said second insulating film;forming a gate insulating film on a peripheral portion of said semiconductor substrate;forming a silicon layer on said gate insulating film and on said first and second insulating films while burying said groove;forming a first resist pattern on said silicon layer over portions of said first and second insulating films so as not to cover over said groove and a second resist pattern on said silicon layer over said gate insulating film, said first and second resist pattern including carbon;etching said silicon layer with using said first and second resist patterns as masks by using a gas including Cl.sub.2 /HBr until said gate insulating film is exposed, at that time, forming an etched particulate resist layer on a surface of said silicon layer in said groove;etching said etched particulate resist layer by using a gas including Cl.sub.2 /HBr/O.sub.2 ; andetching said silicon layer in said groove with said first and second resist patterns as masks by using a gas including HBr/O.sub.2.