Patent ID: 9225303
Filing Date: 2015-12-29
Classification: H03F

Abstract:
1. An output circuit for an amplifier, comprising: a first power node for coupling to a positive power supply; a second power node for coupling to a negative power supply, an output node; first and second PMOS transistors connected in series between the first power node and the output node; first and second NMOS transistors connected in series between the output node and the second power node; a first input terminal coupled to a gate of the first PMOS transistor; a second input terminal coupled to a gate of the first NMOS transistor; a voltage divider coupled between the output node and a ground node GND, the voltage divider including first and second resistors which are connected at a first node; a first source follower including a third PMOS transistor, the third PMOS transistor having a gate coupled to the first node and a source coupled to a gate of the second NMOS transistor; and a second source follower including a third NMOS transistor, the third NMOS transistor having a gate coupled to the first node and a source coupled to a gate of the second PMOS transistor.