Patent ID: 7817761
Filing Date: 2010-10-19
Classification: G01R,H03L

Abstract:
1. An integrated circuit having at least a first mode of operation and a second mode of operation, the integrated circuit comprising: a variable delay circuit configured to generate at least one delayed clock signal based, at least in part, on a first clock signal and a first control signal; and a control circuit configured to generate a count value based, at least in part, on a second input signal and a second control signal; wherein during the first mode of operation, the first clock signal is a first version of the at least one delayed clock signal, wherein during the first mode of operation, at least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of the frequency characteristic of the at least one delayed clock signal, wherein during the first mode of operation, the integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.