Patent ID: 7679135
Filing Date: 2010-03-16
Classification: H01L

Abstract:
1. A semiconductor device comprising: a source region, a drain region, and a fin that connects the source region to the drain region; a gate electrode having a substantially planar surface overlying the fin and positioned between the drain region and the source region; a first set of spacers positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region, the first set of spacers comprising a first surface, a second surface opposite the first surface, and a top surface connecting the first surface and the second surface, wherein the top surface is covered by the gate electrode; and a second set of spacers positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers, wherein at least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode.