Patent ID: 7647479
Filing Date: 2010-01-12
Classification: G06F

Abstract:
1. An apparatus, for adding instruction level non-temporal access control features to a corresponding instruction that is stored in a computer readable storage, the corresponding instruction being part of an existing instruction set, the apparatus comprising: an escape tag, for reception by a translation unit, and for indicating that accompanying parts of the corresponding instruction prescribe a memory reference, wherein said escape tag is a first opcode within the existing instruction set; a non-temporal access specifier, coupled to said escape tag and being one of said accompanying parts, for prescribing that a non-temporal access be employed to perform said memory reference, wherein said non-temporal access directs a microprocessor to preclude caching of data corresponding to said memory reference; and an extended execution unit, coupled to said translation unit, for executing said memory reference via said non-temporal access; wherein said translation unit translates said escape tag and said accompanying parts into corresponding micro instructions that direct said extended execution unit to perform said memory reference via said non-temporal access.