Patent ID: 6668031
Filing Date: 2003-12-23
Classification: G11C,H04L

Abstract:
In an integrated circuit, a synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal, said synchronized data circuit employing voltage signals having a reduced voltage level, said data signal and said timing signal having a first voltage level higher than said reduced voltage level, comprising:a timing driver circuit arranged to receive said timing signal, said timing driver circuit outputting a reduced voltage timing signal having said reduced voltage level; a data driver circuit arranged to receive said data signal and said timing signal, said data driver outputting a reduced voltage clocked data signal having said reduced voltage level; and a data clocking circuit coupled to said timing driver circuit and said data driver circuit, said data clocking circuit being arranged to receive said reduced voltage timing signal and said reduced voltage clocked data signal, said data clocking circuit outputting a synchronized capture data signal having said first voltage level higher than said reduced voltage level.