Patent ID: 6107155
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A method for fabricating stacked capacitors for memory devices comprising the steps of:providing a semiconductor substrate having device areas with semiconductor devices;forming a planar first insulating layer over said device areas on said substrate;selectively etching first openings for capacitor node contacts in said first insulating layer to said device areas;depositing a conductively doped first polysilicon layer to fill said first openings, and etching back said first polysilicon layer to form polysilicon plugs in said first openings;depositing a blanket etch-stop layer on said first insulating layer and over said polysilicon plugs in said first openings and over the sidewalls of any exposed said first insulating layer when said polysilicon plugs are overetched;depositing a second insulating layer on said etch-stop layer;selectively etching second openings, over and wider than said first openings, in said second insulating layer and in said etch-stop layer to said polysilicon plugs;depositing a conformal second polysilicon layer over and in said second openings and contacting said polysilicon plugs;polishing back said second polysilicon layer to said second insulating layer to form bottom electrodes in said second openings;isotropically etching said second insulating layer selectively to said etch-stop layer to leave free-standing said bottom electrodes, while said etch-stop layer on said sidewalls of said first insulating layer protect said first insulating layer from etching when said second openings are misaligned to said first openings;depositing an interelectrode dielectric layer on said bottom electrodes;depositing and patterning a third polysilicon layer to form top electrodes and completing said stacked capacitors.