Patent ID: 7622352
Filing Date: 2009-11-24
Classification: H01L

Abstract:
1. A method for preparing a transistor having a multi-step gate structure, comprising the steps of: forming a semiconductor substrate having a multi-step structure, including: forming a mask layer covering a predetermined portion of the semiconductor substrate; etching the semiconductor substrate using the mask layer as a first etching mask to form a first depression; forming a first spacer on a sidewall of the first depression; etching the semiconductor substrate using the mask layer and the first spacer as a second etching mask to form a second depression; and removing the mask layer and the first spacer; performing a thermal oxidation process to form a gate oxide layer covering the entire surface of the multi-step structure; forming a conductive layer on the gate oxide layer; removing a portion of the conductive layer to form a multi-step gate on the gate oxide layer, wherein the gate oxide layer under the multi-step gate is continuous; and wherein at least one first implanting process is performed before the forming of the gate oxide layer to implant nitrogen-containing dopants into a portion of the semiconductor substrate under the multi-step structure so as to control the thickness of the gate oxide layer by inhibiting the reaction rate of the thermal oxidation process to form the gate oxide layer.