Patent ID: 7541252
Filing Date: 2009-06-02
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, comprising: forming a conductive layer on a semiconductor substrate; forming an insulating layer on the conductive layer; patterning the insulating layer and the conductive layer to form a plurality of stacked structures separated by isolations trenches, wherein each of the stacked structures includes a patterned portion of the conductive layer which defines a word line and a corresponding patterned portion of the insulating layer stacked on the word line; forming an isolation layer that fills the isolation trenches; forming a cell contact hole in each of the patterned portions of the insulating layer such that the cell contact hole is self-aligned between the isolation trenches and with a corresponding word line so as to expose the corresponding word line; and forming a cell diode in the cell contact hole.