Patent ID: 8674677
Filing Date: 2014-03-18
Classification: H01L,H02M

Abstract:
1. A semiconductor integrated circuit, comprising: a current mirror having a predetermined input-output ratio and including a first transistor having a transistor element configured to receive an input current and a second transistor having two or more transistor elements configured to output an output current; and an output transistor configured to generate a reference voltage according to the output current of the current mirror, wherein a value of the output current is N times greater than a value of the input current, with N being a positive integer greater than one, wherein the one or more transistor elements of the second transistor have one or more collector layer regions having substantially a same total surface area in a surface pattern layout, and wherein a total surface area of a collector layer region of the transistor element of the first transistor in a surface pattern layout is N times greater than the total surface area of each of the collector layer regions of the second transistor in a surface pattern layout.