Patent ID: 7505520
Filing Date: 2009-03-17
Classification: H04L

Abstract:
1. A communication system comprising a first device including a circuitry for generating a first digital signal at a signal frequency and a transmitting circuit connected to said circuitry and having a first equalizer for producing a transmitting signal containing high frequency signal components over said signal frequency; a transmission line connected at one end thereof to said transmitting circuit for propagating said transmitting signal to the other end thereof, and causing said high frequency signal components to be attenuated more seriously than a signal component at said signal frequency; and a second device including a receiving circuit having a second equalizer connected to said other end of said transmission line and amplifying at least said high frequency signal components for restoring said transmitting signal to a waveform close to an original waveform of said first digital signal, a judging circuit for producing a second digital signal from parts of said waveform, and an equalization controller connected to said second equalizer for automatically optimizing the total amount of equalization carried out by both of said first and second equalizers, said second equalizer includes a first amplifier supplied with said transmitting signal, a high pass filter supplied with said transmitting signal, a second amplifier supplied with an output signal of said high pass filter and an adder supplied with output signals of said first and second amplifiers for imparting said waveform to said transmitting signal, each of said first and second amplifiers has an amplification stage implemented by CMOS inverters and a gain controlling stage connected to said amplification stage and implemented by CMOS components, said gain controlling stage has a series combination of first and second p-channel enhancement type field effect transistors connected between a first source of constant voltage and a common drain node, a series combination of first and second n-channel enhancement type field effect transistors connected between said common drain node and a second source of constant voltage different in potential level from said first source of constant voltage, a p-channel enhancement type field effect transistor connected in parallel to the first p-channel enhancement type field effect transistor and having a gate electrode applied with a first control voltage and an n-channel enhancement type field effect transistor connected in parallel to the second n-channel enhancement type field effect transistor and having a gate electrode applied with a second control voltage, and an output signal of said amplification stage is supplied to gate electrodes of said first and second p-channel enhancement type field effect transistors and gate electrodes of said first and second n-channel enhancement type field effect transistors.