Patent ID: 6236249
Filing Date: 2001-05-22
Classification: H03K

Abstract:
A power-on reset circuit for an integrated circuit comprising:a reset circuit for generating a reset signal at a first logic state until a power supply voltage has reached a predetermined level; anda delay circuit coupled to the reset circuit for generating a delay signal responsive to the reset signal;wherein the reset circuit generates the reset signal at a second logic state in response to the delay signal;wherein said reset circuit comprises:a reference signal generator for generating a reference signal;a voltage detector coupled to the reference signal generator for generating a start-up signal responsive to the power supply voltage; anda reset signal generator coupled to the reference signal generator and the voltage detector for generating the reset signal in response to the reference signal and the start-up signal; andwherein said reset signal generator comprises:a differential comparator for generating the reset signal at the first logic state while the start-up signal is lower than or equal to the reference signal; anda clamp circuit coupled to the differential comparator for clamping the reset signal to the second logic state in response to the delay signal.