Patent ID: 7219118
Filing Date: 2007-05-15
Classification: G06F

Abstract:
1. A method of adding two or more sets of two N bit binary numbers with an M bit adder, where M is equal to K*N, K being an integer greater than or equal to two, comprising: providing each of the two or more sets of two N bit binary numbers to adjacent sets of N inputs of the M bit adder; inhibiting a carry data path, from each N bit portion of the M bit adder corresponding to each set of two N bit binary numbers, to the next adjacent N bit portion of the M bit adder, by providing a gating signal to a logical gate, along with a kill signal from a next least significant bit path in the adder, such that a predetermined state of the gating signal causes the kill signal to be propagated to the next more significant bit path of the adder, so as to isolate a contiguous N bit data path through the M bit adder corresponding to each of the two or more sets of two N bit binary numbers; and for each of the two N bit binary numbers, receiving a sum at an output portion of the adder, wherein the output portion of the adder is defined by the data path associated with the two N bit binary numbers.