Patent ID: 6420915
Filing Date: 2002-07-16
Classification: H03L,H04L

Abstract:
A system for preventing timing errors, comprising:a first latch configured to receive a data signal and a clock signal, said first latch configured to latch a value of said data signal in response to a transition of said clock signal; a second latch configured to receive said data signal and said clock signal, said second latch configured to latch a value of said data signal in response to said clock signal transition; a third latch configured to receive said data signal and said clock signal, said third latch configured to latch a value of said data signal in response to said clock signal transition; a first delay mechanism coupled to said first latch, said first delay mechanism configured to delay a transition of said data signal before said data signal transition is received by said first latch such that said first latch receives said data signal transition after said third latch receives said data signal transition; a second delay mechanism coupled to said second latch, said second delay mechanism configured to delay said data signal transition before said data signal transition is received by said second latch such that said second latch receives said data signal transition after said first latch receives said data signal transition; and a feedback mechanism configured to receive said latched values, said feedback mechanism configured to transmit a feedback signal based on said latched values, said feedback signal indicative of whether said first, second, and third latches latched the same logical value of said data signal in response to said clock signal transition.