Patent ID: 8014186
Filing Date: 2011-09-06
Classification: G11C

Abstract:
1. A ferroelectric memory device comprising: a plurality of memory banks configured to include a memory cell array composed of a ferroelectric memory; a cache bank configured to be bus-connected with the memory banks, and for copying data stored in the memory banks; and a memory bank/cache control sequencer for accessing and refreshing to the memory banks and the cache bank, wherein a random access control to the ferroelectric memory is possible during each memory cycle without delay of refresh operation, and wherein the ferroelectric memory includes: a plurality of bit lines placed at a column direction; a plurality of word lines which intersects perpendicularly with the bit lines and are placed at a row direction; a plurality of plate lines which intersects perpendicularly with the bit lines and are placed at a row direction; a bit line control line which intersects perpendicularly with the bit lines and is placed at a row direction; a ferroelectric capacitor placed at an intersection of a plurality of the bit lines, a plurality of the word lines, and the plate line, an electrode of one side of the ferroelectric capacitor being connected to the plate line; a ferroelectric memory cell composed of a memory cell transistor by which one side of one of a source and a drain is connected to the electrode of another side of the ferroelectric capacitor, another side of one of the source and the drain is connected to the bit line, and a gate is connected to the word line; a load capacitor placed at an intersection of a plurality of the bit lines and the bit line control line, an electrode of one side of the load capacitor being connected to ground potential; and a load capacitor adjustment cell composed of a load capacitor adjustment transistor by which one side of one of a source and a drain is connected to the electrode of another side of the load capacitor, another side of one of the source and the drain is connected to the bit line, and a gate is connected to the bit line control line.