Patent ID: 8069302
Filing Date: 2011-11-29
Classification: G06F,G11C

Abstract:
1. A flash memory storage system comprising: a memory array containing a plurality of memory cells; and a controller for controlling said memory array by dedicating a first group of memory cells from among said plurality of memory cells to store a first number of bits per cell and dedicating a second group of memory cells from among said plurality of memory cells to store a second number of bits per cell, wherein said second number is greater than said first number, and said first group of memory cells and said second group of memory cells are disjoint; and said controller applying a first wear leveling technique only within said first group of memory cells separately from said memory cells of said second group of memory cells, so as to evenly distribute wear of said first group of memory cells within themselves independent of wear of said second group of memory cell; and wherein a ratio between a number of said memory cells of said second group of memory cells and a number of said memory cells of said first group of memory cells is set to equal a ratio between an endurance of said first group of memory cells and an endurance of said second group of memory cells multiplied by a ratio between said first number of bits and said second number of bits.