Patent ID: 6480967
Filing Date: 2002-11-12
Classification: G06F

Abstract:
A processing system comprising:at least one processing module that is responsive to a module-clock signal and to a reset signal, wherein the processing module is initialized to an initial state in response to an assertion of the reset signal, and performs a processing function in dependence upon a de-assertion of the reset signal, a clock module that provides the module-clock signal in dependence upon a master-clock signal and an assertion of a clock-enable signal, a controller that provides the assertion of the clock-enable signal in dependence upon a reset command, and a reset module that provides the assertion of the reset signal in response to the reset command and provides the de-assertion of the reset signal in response to a de-assertion of the clock-enable signal, wherein the controller provides the de-assertion of the clock-enable signal after a number of cycles of the master-clock signal.