Patent ID: 7208794
Filing Date: 2007-04-24
Classification: G11C,H01L,Y10S

Abstract:
1. A semiconductor memory having a plurality of memory cells, wherein each memory cell comprises: a first conductively doped contact region, a second conductively doped contact region and a channel region which is arranged between the latter, these regions being formed in a web-like rib made of semiconductor material, and arranged one behind the other in this sequence in the longitudinal direction of the rib, wherein the rib has, at least in a section in the channel region running perpendicularly with respect to the longitudinal direction of the rib, an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite; a memory layer which is configured for programming the memory cell and is arranged on the upper side of the rib spaced apart by a first insulator layer, wherein the memory layer projects in the normal direction of the one rib side face over at least one of the rib side faces so that the one rib side face and the upper side of the rib form an injection edge for injecting charge carriers from the channel region into the memory layer; and at least one gate electrode which is spaced apart from the one rib side face by a second insulator layer, and from the memory layer by a third insulator layer, wherein the gate electrode is electrically insulated from the channel region and is configured to control its electrical conductivity; wherein the second insulating layer has a greater layer thickness than the third insulator layer.