Patent ID: 6541328
Filing Date: 2003-04-01
Classification: H01L

Abstract:
A method of fabricating a complementary metal oxide semiconductor (CMOS) transistor having p-type (PMOS) and n-type (NMOS) transistors comprising:providing a semiconductor substrate; forming gate electrodes on the semiconductor substrate in PMOS and NMOS regions of the substrate corresponding respectively to PMOS and NMOS transistors; forming a middle temperature oxide (MTO) layer on a top portion and side walls of the gate electrodes and on the semiconductor substrate in the PMOS and NMOS regions; forming an insulating layer on the MTO layer; forming spacers adjacent the insulating layer at both side walls of the gate electrodes; selectively removing the insulating layer such that portions of the insulating layer remain between the spacers and MTO layer; and in each of the PMOS and NMOS regions: forming first impurity regions having a first density on both sides of the spacers in the semiconductor substrate under the MTO layer; removing the spacers; and following removal of the spacers, forming second impurity regions having a second density that is lower than the first density on both sides of the gate electrodes in the semiconductor substrate.