Patent ID: 6345380
Filing Date: 2002-02-05
Classification: H03K

Abstract:
A method for reducing inductance between a plurality of integrated circuit chips, each of said chips having a first on-chip power supply and a second on-chip power supply, a functional circuit block coupled to an induction reduction circuit, a first of set of I/O circuits coupled to a first plurality of input/output points and a second of set of I/O circuits coupled to a second plurality of input/output points and said induction reduction circuit comprising the steps of:connecting the first on-chip power supply, connected to a first integrated circuit of said plurality of integrated circuit chips, to the first on-chip power supply connected to selected ones of the remaining plurality of integrated circuit chips; connecting the second on-chip power supply, connected to said first integrated circuit of said plurality of integrated circuit chips, to the second on-chip power supply connected to selected ones of the remaining plurality of integrated circuit chips; activating a selected fist set of I/O circuits on a selected one of said plurality of integrated circuit chips, maintaining the second set of I/O circuits on selected ones of said plurality of integrated circuit chips In an inactive state, and activating said induction reduction circuits on each chip of said plurality of integrated circuit chips having a second set of I/O circuits maintained in an inactive state to connect he plurality of I/O points coupled to the activated first set of I/O circuits on said selected one of said plurality of chips to the plurality of I/O points coupled to said inactive second set of I/O circuits on each of said chips.