Patent ID: 8937494
Filing Date: 2015-01-20
Classification: G01R,H03K

Abstract:
1. A method for detecting a rising transition and a falling transition of an internal signal of an integrated circuit, the method comprising: receiving by a delay line the internal signal of the integrated circuit, wherein the delay line comprises first to Nth delay elements in series, N is an integer greater than 1, the first delay element receives the internal signal; passing signals from the delay line through first latches, wherein inputs of respective ones of the first latches connect to an input of the first delay element, between two adjacent ones of the delay elements, and an output of the Nth delay elements; passing signals from the respective ones of the first latches through respective ones of first to Nth groups of logic gates, wherein each of the first to Nth groups comprises an AND gate and a NOR gate, wherein first inputs of the logic gates in the first to Nth groups connect to outputs of the respective ones of the first latches so as to detect signals at inputs of the first to Nth delay elements, respectively, wherein second inputs of the logic gates in the first to Nth groups connect to the outputs the respective ones of the first latches so as to detect signals at outputs of the first to Nth delay elements, respectively; and determining the rising transition and the falling transition based on output signals of the AND gate and the NOR gate, wherein, in odd numbered groups of the logic gates, the AND gate detects the rising transition and the NOR gate detects the falling transition, wherein, in even numbered groups of the logic gates, the AND gate detects the falling transition and the NOR gate detects the rising transition.