Patent ID: 7142671
Filing Date: 2006-11-28
Classification: H04L

Abstract:
1. A cryptography engine for performing cryptographic operations on an initial input data bit sequence, the initial input data bit sequence having a right portion and a left portion, the cryptographic engine comprising: a key scheduler configured to provide keys for cryptographic operations; two-level multiplexer circuitry including a first and a second expansion logic, wherein the first expansion logic is configured to expand a first bit sequence having a first size to an expanded first bit sequence having a second size greater than the first size, the first bit sequence corresponding to the right portion of the initial input data bit sequence; permutation logic coupled to the second expansion logic, the permutation logic configured to alter a second bit sequence corresponding to the right portion of the output bit sequence for the previous cryptographic round; a substitution box (SBox) configured to transform a third bit sequence to a fourth bit sequence, wherein the right portion of the output bit sequence for the current cryptographic round is the exclusive OR of the output of the third 2-1 multiplexer and the fourth bit sequence and the left portion of the output bit sequence for the current cryptographic round is the output of the fourth 2-1 multiplexer, and wherein the two-level multiplexer is configured to swap the left portion of the output bit sequence of a previous cryptographic round with the right portion of the output bit sequence of the previous cryptographic round.