Patent ID: 8312332
Filing Date: 2012-11-13
Classification: G01R,G11C

Abstract:
1. A test apparatus for an electrical circuit to be tested, the test apparatus comprising: a test input signal generator configured to generate a test input signal of word width N; terminals that connect to inputs and outputs of an electrical circuit to be tested, wherein the electrical circuit to be tested includes N digital test inputs and M digital test outputs, the terminals that connect to the test inputs are connected to receive the test input signal, and the electrical circuit is driven such that the electrical circuit outputs data with a macro clock cycle T of period L as a test response; a compactor including M inputs that are connected to the outputs of the electrical circuit to receive the test response; wherein the compactor is configured to compact the test response with a micro clock cycle t of period l and to output the test response as a data word of width m, where m is smaller than M and the period L is at least twice as large as the period l; and an evaluating device that is configured to: in response to the evaluating device determining by a comparison that errors are present in the output signals of the compactor, use the further part of the output signals of the compactor for diagnostic analysis of the errors.