Patent ID: 7506091
Filing Date: 2009-03-17
Classification: G06F

Abstract:
1. An interrupt controller comprising: a plurality of priority registers each configured to store a priority value associated with one or more interrupt signals of a plurality of interrupt signals; a priority register accessing circuit configured to provide access to priority values stored within said plurality of priority registers; and a prioritising circuit configured, when multiple interrupt signals are asserted, to prioritise between said multiple interrupt signals in dependence upon respective priority values as stored in said plurality of priority registers; wherein said priority register accessing circuit is responsive to an access request received from a first priority value manager to apply a first mapping between priority values as accessed by said first priority value manager and priority values as stored in said plurality of priority registers; and said priority register accessing circuit is responsive to an access request received from a second priority value manager to apply a second mapping between priority values as accessed by said second priority value manager and priority values as stored in said plurality of priority registers, said second mapping being different to said first mapping.