Patent ID: 8553447
Filing Date: 2013-10-08
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: one or more main bit lines; one or more power supply lines; four or more word lines; and two or more cells, wherein each of the cells includes a sub bit line, a selection transistor, a reading transistor, and two or more memory cells, wherein a drain of the selection transistor and a drain of the reading transistor are connected to one of the main bit lines, wherein a gate of the reading transistor is connected to the sub bit line, wherein a source of the reading transistor is connected to one of the power supply lines, wherein each of the memory cells includes a transistor and a capacitor, wherein the capacitance of the capacitor is 1 fF or less, and wherein a gate of the transistor of one of the memory cells is connected to one of the word lines.