Patent ID: 6242940
Filing Date: 2001-06-05
Classification: G11C

Abstract:
A data input buffer circuit, comprising:a first basic circuit which includes a first NOR-gate for NORing a first control signal and a first data signal, a first inverter for inverting an output of the first NOR-gate, a first data maintaining unit for maintaining an enabled state of a first data control signal which is an output of the first inverter, and a first data transition detection unit for detecting a transition of the first data control signal and outputting a first data transition detection signal;second through n-th basic circuits constructed similarly with the first basic circuit for receiving second through n-th data signals and outputting second through n-th input data signals;a data transition detection signal summing unit for summing first through n-th data transition detection signals from the first through n-th data transition detection units; anda first delay unit for delaying an output of the data transition detection signal summing unit for a certain time and outputting a second control signal.