Patent ID: 8402423
Filing Date: 2013-03-19
Classification: G06F

Abstract:
1. A computing device for verifying a printed circuit board (PCB) layout, the computing device comprising: at least one processor; a storage device that stores a PCB simulation file and a layout design specification of the PCB, the PCB comprising a plurality of signal lines and switching voltage regulator nodes (SVRNs); and one or more modules stored in the storage system and executable by the at least one processor, the one or more modules comprising: a PCB layout simulating module that displays a PCB image on a display device according to the PCB simulation file, and sets a minimum distance between each switching voltage regulator node (SVRN) and any signal line around the SVRN; a signal source selection module that selects an SVRN to be checked from the PCB image, and searches all signal lines around the SVRN from the PCB image; a signal line verifying module that calculates a layout distance between the selected SVRN and each of the searched signal lines, and determines whether the layout distance is greater than the minimum distance; and a layout modifying module that generates a graphical window interface on the display device, and automatically positions the graphical window interface on the signal line whose layout distance is equal to or less than the minimum distance, and modifies a layout of the positioned signal line to satisfy the layout design specification by increasing the layout distance to make sure that the layout distance is greater than the minimum distance.