Patent ID: 6924874
Filing Date: 2005-08-02
Classification: H01L

Abstract:
1. A method of fabricating a liquid crystal display (LCD), the method comprising the steps of: providing an insulation substrate, a pixel array area and a periphery circuit area defined on the insulation substrate; forming a polysilicon layer on a surface of the insulation substrate; performing a first photo-etching-process (PEP-1) to remove portions of the polysilicon layer to respectively form a first active area in the pixel array area and a second active area in the periphery circuit area, a source region, a drain region, a channel region, and a predetermined region for a bottom storage electrode being comprised in the first active area, a source region, a drain region, and a predetermined region for a channel region being comprised in the second active area; forming a first mask on a surface of the entire structure by performing a second photo-etching-process (PEP-2) to define the channel region in the first active area and the channel region in the second active area; performing a first ion implantation process by utilizing the first mask as a mask; removing the first mask; forming a second mask on the surface of the entire structure by performing a third photo-etching-process (PEP-3) to define the source region, the drain region, and the bottom storage electrode in the first active area and the source region and the drain region in the second active area; performing a second ion implantation process by utilizing the second mask as a mask to form a source electrode and a drain electrode in the first active area and in the second active area respectively and to dope the bottom storage electrode with dopants simultaneously; removing the second mask; forming a first isolation layer on the surface of the entire structure; forming a metal layer on a surface of the first isolation layer, the first isolation layer and the metal layer covering the first active area, the second active area, and the bottom storage electrode; performing a fourth photo-etching-process (PEP-4) to remove portions of the metal layer to form a gate insulating layer, a gate electrode, a capacitor dielectric layer, and a top storage electrode in the pixel array area and a gate insulating layer and a gate electrode in the periphery circuit area; forming a third mask on the surface of the entire structure by performing a fifth photo-etching-process (PEP-5) to define a thin film transistor region; performing a third ion implantation process by utilizing the third mask as a mask to form a source electrode and a drain electrode in the periphery circuit area; removing the third mask; forming a second isolation layer on the surface of the entire structure, the second isolation layer covering each gate electrode and the top storage electrode; performing a sixth photo-etching-process (PEP-6) to remove portions of the second isolation layer to form a first contact hole extending to the top surface of each source electrode and each drain electrode; forming a first conductive layer on a surface of the second isolation layer to fill up the first contact hole; performing a seventh photo-etching-process (PEP-7) to remove portions of the first conductive layer to form a source wire and a drain wire in the pixel array area and the periphery circuit area respectively, the source wire and the drain wire being electrically connected to the source electrode and the drain electrode through the first contact hole respectively; and forming a third isolation layer on the surface of the entire structure, the third isolation layer covering the second isolation layer, the source wire, and the drain wire.