Patent ID: 9190176
Filing Date: 2015-11-17
Classification: G11C

Abstract:
1. A memory device comprising: a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array; a first main transfer unit configured to be enabled when the first column address indicates only one or more normal columns of the first main memory array and transfer data between the outside and the first main page buffer array; and a second main transfer unit configured to be enabled when the second column address indicates only one or more normal columns of the second main memory array and transfer data between the outside and the second main page buffer array, wherein the redundancy page buffer array comprises a plurality of page buffers, wherein each of the page buffers is connected to the first redundancy bus when the first column address corresponds to itself, and connected to the second redundancy bus when the second column address corresponds to itself.