Patent ID: 6775170
Filing Date: 2004-08-10
Classification: G11C

Abstract:
A semiconductor memory device comprising:a signal line for propagating an operation signal related to the operation of the semiconductor memory device; a complementary signal line for propagating a complementary signal of the operation signal; a plurality of read column select lines parallel to the signal line and the complementary signal line, respectively and operable to transmit a read column select signal, which controls transfer of a data signal of a bit line to a data line; and a plurality of write column select lines parallel to the signal line and the complementary signal line and interposed between the read column select lines and the two signal lines, the write column select lines operable to transmit a write column select signal, which controls transfer of the data signal of the data line to the bit line; the write column select lines to be maintained at a predetermined logic level, respectively, during a read operation to shield the signal line and the complementary signal line from transitions of the read column select signal.