Patent ID: 8593177
Filing Date: 2013-11-26
Classification: G06F

Abstract:
1. An integrated circuit comprising: a clock-tree comprising a plurality of clock buffers; a plurality of clocked storage elements each having a clock input terminal connected to one of the plurality of clock buffers and a weight; a plurality of logic circuits, each logic circuit associated with two of the plurality of clocked storage elements and characterized as having a logic depth, the weight of each clocked storage element being based upon each of the plurality of logic circuits associated therewith; the plurality of clocked storage elements comprising a first clocked storage element having a highest weight of the plurality of clocked storage elements, wherein the first clocked storage element is adjacent to and interacts with a second clocked storage element of the plurality of clocked storage elements via one of the plurality of logic circuits; wherein the weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith; and wherein a first one of the plurality of clock buffers provides a common clock signal to the first and second clocked storage elements.