Patent ID: 6411561
Filing Date: 2002-06-25
Classification: G11C,H01L

Abstract:
An operation method of a semiconductor device, said semiconductor device including a dynamic random access memory (DRAM) having a plurality of memory banks, reading/writing being conducted in said dynamic random access memory (DRAM) by a command synchronized to a clock, said operation method comprising the steps of:assigning said plurality of memory banks to a first memory block and a second memory block having an identical memory capacity, and conducting assignment of access to said semiconductor device so as to generate a first interval and a second interval alternately; in said first interval, executing a read/write command directed to said DRAM on said first memory block, and executing preferentially refresh operation on said second memory block; in said second interval, executing a read/write command directed to said DRAM on said second memory block, and executing preferentially refresh operation on said first memory block; wherein in said first interval, said second memory block executes refresh operation preferentially, and if a write command has been issued to said first memory block, said second memory block then executes a command for writing identical data into a corresponding address of said second memory block; and in said second interval, said first memory block executes refresh operation preferentially, and if a write command has been issued to said second memory block, said first memory block then executes a command for writing identical data into a corresponding address of said first memory block.