Patent ID: 8473541
Filing Date: 2013-06-25
Classification: G06F

Abstract:
1. An M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit, the M-bit adder comprising: M adder cells arranged in R rows including a first row and R−1 subsequent rows, each row subsequent to the first row having more adder cells than a preceding row, wherein each row of adder cells includes a least significant adder cell and at least one subsequent adder cell, wherein each adder cell is configured to receive wherein each adder cell subsequent to the least significant adder cell within each row subsequent to the first row is configured to receive wherein each adder cell within a row subsequent to the first row is configured to generate a first conditional carry-out bit C wherein each adder cell subsequent to the least significant adder cell within each row further comprises: first and second passgates receiving the first and second conditional carry-in bits C first and second inverters coupled to the first and second passgates, wherein the respective adder cell is configured to generate the first conditional carry-out bit C wherein alternate adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits C wherein intervening adder cells subsequent to the least significant adder cell within each row are configured to invert and propagate the first and second conditional carry-in bits C