Patent ID: 6510529
Filing Date: 2003-01-21
Classification: G06F

Abstract:
A computer system comprising:a first computer; a first bus switch coupled to the first computer; a data bus coupled to the first computer via the first bus switch; a second computer; a second bus switch coupled to the second computer, the data bus being coupled to the second computer through the second bus switch; a monitor system coupled to the first computer, to the first bus switch, and to the second bus switch, the monitor system comprising a watchdog timer coupled to a switch over circuit, wherein a watchdog timeout period exceeds a period between executions of a reset code, the reset code being included in software executing on the first computer, wherein a reset signal is generated in response to execution of the reset code, thereby resetting the watchdog timer prior to the watchdog timeout period, and wherein upon a failure in the first computer the reset code is not executed, and therefore the reset signal is not generated, thereby not resetting the watchdog timer prior to the watchdog timeout period, wherein the watchdog timer generates a switch over signal in the event the watchdog timeout period is reached before the watchdog timer is reset.