Patent ID: 7459739
Filing Date: 2008-12-02
Classification: G11C,H01L

Abstract:
1. A memory array comprising: a first plurality of memory devices, each device comprising: a substrate; a first memory layer having a first memory structure formed on the substrate, wherein the first memory layer further includes a first plurality of electrodes in electrical contact with an underside of the first memory structure, wherein the first memory structure is configured to store a first logic state therein by selective magnetization of the first memory structure; and at least a second memory layer having a second memory structure formed above the substrate in a manner so as to overlie the first memory layer, wherein the second memory layer further includes a second plurality of electrodes in separate electrical contact with an underside of the second memory structure, wherein the second memory structure is configured to store a second logic state therein by selective magnetization of the second memory structure, and wherein the second memory layer increases the storage density of the array; and a plurality of word lines interposed between the first and second memory layers and insulated from the first and second memory structures, each word line arranged to extend proximate to the first and the second memory structures such that application of current to the word lines can alter a magnetic state of the first and the second memory structures.