Patent ID: 7888675
Filing Date: 2011-02-15
Classification: G02F,H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate line formed on the substrate; a gate insulating layer formed on the substrate; a semiconductor layer formed on the substrate; a data line formed on the semiconductor layer and having a source electrode; a drain electrode formed on the semiconductor layer and disposed opposite the source electrode; and a pixel electrode connected to the drain electrode, wherein the data line includes a first conducting film including Mo, a second conducting film including Al formed on the first conducting film, and a third film including Mo formed on the second conducting film, wherein the semiconductor layer includes a first portion having substantially the same planar shape as the data line and the drain electrode and a second portion disposed and exposing between the source electrode and the drain electrode, and wherein the second portion includes Cl atoms of 3.0 to 20 at %.