Patent ID: 6121813
Filing Date: 2000-09-19
Classification: H03K

Abstract:
A delay circuit having an input terminal for receiving pulse signals and an output terminal for outputting delayed pulse signals, comprising:a first inverter for inverting a pulse signal received from the input terminal;an integrating circuit, having a resistor and a first capacitor, for integrating the pulse signal received from the first inverter;a second capacitor connected to a power supply voltage and the first capacitor; anda second inverter for inverting a signal outputted by the integrating circuit and the second capacitor when the signal has a voltage which is higher or lower than a predetermined threshold value;wherein a ratio of the capacitances of said first and second capacitors has a relationship with the predetermined threshold value, such that noise present in the power supply voltage does not affect operation of said second inverter;wherein the second inverter includes an n-channel CMOS transistor and a p-channel CMOS transistor;wherein said transistors are arranged so that the gates of the n-channel transistor and the p-channel transistor are connected to the first and second capacitors, respectively, the source of the p-channel transistor is connected to the power supply, and the drains of the transistors are connected to the output terminal;wherein the predetermined threshold value is a threshold value of the second inverter and has a value equal to P/a, where P is a power supply voltage and a is a constant of 1 or greater; anda capacity ratio C2/C1 of said second capacitor C1 and said first capacitor C2 equals a value a-1.