Patent ID: 8504964
Filing Date: 2013-08-06
Classification: G06F

Abstract:
1. A through-hole layout apparatus comprising: an extractor, implemented by a processor, configured to extract a plurality of through-holes interconnecting an upper layer wiring and a lower layer wiring from design data for a semiconductor integrated circuit; a calculator, implemented by the processor, configured to calculate, for each of the plurality of through-holes extracted by said extractor, a layout density of through-holes in a corresponding predetermined region centered on each of said though-holes, respectively; a selector, implemented by the processor, configured to select a target through-hole among said plurality through-holes extracted by the extractor, where said layout density calculated by said calculator for the target through-hole is lower than a predetermined value; and a through-hole adder, implemented by the processor, configured to determine, for the target through-hole selected by the selector, a first given position in the corresponding predetermined region centered on said target through-hole as a placement position at which a through-hole is to be added and adding a through-hole at said placement position on said design data.