Patent ID: 7355460
Filing Date: 2008-04-08
Classification: G06F,H03K

Abstract:
1. A method for locally generating a ratio clock on a chip, comprising: generating a global clock signal having a global clock cycle; providing a centralized state machine, the centralized state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter; providing the control signal to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle; providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.