Patent ID: 6574691
Filing Date: 2003-06-03
Classification: G06F

Abstract:
An apparatus for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential, comprising:an interface adaptor circuit coupled between the processor and the bus, operative as a burst order translator between the processor and the bus, and having a bridge configured to connect together the processor and the bus and operative to translate processor burst operations into operations supported by the bus, the bridge having a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit; wherein the bridge is operative to enable compatibility between the processor interface and the bus interface such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus and wherein the bridge comprises a write FIFO and a read FIFO.