Patent ID: 7783817
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A weakly-ordered processing system, comprising: a plurality of slave devices; at least one master device configured to direct data transfer bus transactions to one or more of the slave devices; and a bus interconnect configured to implement data transfer bus transactions between master and slave devices, and further configured to direct an execution synchronization bus transaction to one or more of the slave devices that are not globally observable in response to an execution synchronization bus transaction request from the at least one master device; wherein the bus interconnect includes a logical global observability register comprising a plurality of bits, each bit corresponding to a particular slave device and indicating whether the particular slave device maintains global observability; wherein the logical global observability register comprises one or more physical registers set by system software during system initialization; and wherein the system software polls configuration registers in the slave devices to ascertain their global observability.