Patent ID: 6320816
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A memory device, comprising:a memory array having a plurality of memory cells arranged in addressable rows and columns;an addressing decode circuit for producing a first decode signal in response to a first portion of an address signal and a second decode signal in response to a second portion of the address signal;a first latching circuit for latching the first decode signal to produce a first latched decode signal;a second latching circuit for latching the second decode signal to produce a second latched decode signal;a first coupling circuit for producing a first column select signal in response to the first latched decode signal and an enable signal;a second coupling circuit for producing a second column select signal in response to the second latched decode signal and the first column select signal; anda column select circuit for activating a column of the memory array in response to the second column select signal.