Patent ID: 6319768
Filing Date: 2001-11-20
Classification: H01L

Abstract:
A method for fabricating a capacitor in a DRAM cell, comprising the steps of:forming a plurality of wordlines each having a first cap insulating film on a semiconductor substrate;forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of each of the wordlines;forming first sidewall insulating films at the both sides of said each of the wordlines;forming first plugs for contacting either capacitor nodes or bitlines on each of the source/drain impurity regions;forming an interlayer insulating film on the semiconductor substrate and forming a contact hole therein to the first plugs for contacting the bitlines;forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plugs, and having a second cap insulating film;forming second sidewall insulating films at both sides of each of the bitlines and selectively removing the interlayer insulating film to expose surfaces of the first plugs;forming second plugs on the first plugs for contacting the capacitor nodes;removing the second cap insulating film to a required depth;forming capacitor storage electrodes on the second plugs and the second sidewall insulating films, wherein the capacitor storage electrodes are formed by sputtering a conductive layer on an entire surface of the semiconductor substrate and anisotropically etching the conductive layer to remove the conductive layer on the second cap insulating films; andforming a dielectric film and a plate electrode on the semiconductor substrate.