Patent ID: 6650168
Filing Date: 2003-11-18
Classification: H03K

Abstract:
A level-shifting circuit comprising:a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor wherein the gates of both said NMOS transistors are coupled to a low voltage input signal, and wherein the drain of said first NMOS transistor is coupled to the source of said first zero threshold NMOS transistor; a second cascaded switch comprising a second NMOS transistor and a second zero threshold NMOS transistor wherein the gates of both said NMOS transistors are coupled to an inversion of said low voltage input signal, and wherein the drain of said second NMOS transistor is coupled to the source of said second zero threshold NMOS transistor; and a cross-coupled pull-up comprising a first PMOS transistor and a second PMOS transistor wherein the sources of both said PMOS transistors are coupled to a high voltage supply, wherein the gate of said second PMOS transistor and the drain of said first PMOS transistor are coupled to the drain of said first zero threshold NMOS transistor to form an inverted output, and wherein the gate of said first PMOS transistor and the drain of said second PMOS transistor are coupled to the drain of said second zero threshold NMOS transistor to form a non-inverted output.