Patent ID: 6524909
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A self-aligned process of fabricating source lines of an ETOX flash memory, comprising the steps of:providing a substrate; forming a plurality of parallel device isolation lines in the substrate; forming a plurality of parallel stacked gates above the substrate, wherein the stacked gates are perpendicular to the device isolation lines; forming a first insulation layer on top of each stacked gate, wherein the first insulation comprises a silicon oxide layer; forming a plurality of silicon oxide spacers on sidewalls of the stacked gates; forming at least one source array in the substrate between neighboring stacked gates, wherein the source array is parallel to the stacked gates and has a plurality of source-doped regions separately positioned between device isolation lines; forming a second insulation layer over the substrate, wherein the second insulation layer comprises a borophosphosilicate glass layer; forming an opening in the second insulation layer to expose the device isolation region and the source-doped region cross-over by the source array, wherein the opening is formed by etching the second insulation layer with a gaseous hydrofluoric acid (HF); and forming a source line inside the opening.