Patent ID: 7768319
Filing Date: 2010-08-03
Classification: H03K

Abstract:
1. An integrated circuit comprising: a processor; a first gate having a first input lead, a second input lead, and an output lead; a first logic element having an input lead and an output lead, the input lead of the first logic element being coupled to the first input lead of the first gate; an RC network having an input lead and an output lead, wherein the RC network has a processor-programmable RC time constant, and wherein the input lead of the RC network is coupled to the output lead of the first logic element; a hysteresis logic element having an input lead and an output lead, wherein the input lead of the hysteresis logic element is coupled to the output lead of the RC network, and wherein the output lead of the hysteresis logic element is coupled to the second input lead of the first gate; a transistor having a drain, a source and a transistor gate, wherein the drain is coupled to the input lead of the hysteresis logic element, wherein the source is coupled to a supply voltage conductor, and wherein the transistor gate is coupled to the first input lead of the first gate; and a latch having a first input lead, a second input lead, and an output lead, wherein the first input lead of the latch is coupled to receive a signal output from the first gate.