Patent ID: 6838774
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. An integrated circuit wafer comprising: a wafer comprising a substrate comprising a wafer material, said substrate having first and second surfaces said first surface having a circuit layer comprising integrated circuit elements constructed thereon; a plurality of vias extending a first distance from said first surface of said substrate into said substrate, said vias comprising a stop layer comprising a stop material that is more resistant to chemical/mechanical polishing (CMP) than said wafer material, said vias being filled with an electrically conducting material forming a conducting plug extending from said top surface of said substrate into said substrate, said plug having a top portion proximate to said first surface and bottom portion, said top portion having a cross-sectional area that is greater than that of said bottom portion of said plug, wherein said top portion of said plug comprises a recessed region sized to receive an end of a bottom portion of one of said plugs from a second one of said integrated circuit wafers.