Patent ID: 6258695
Filing Date: 2001-07-10
Classification: H01L

Abstract:
A method of relieving extrinsic stress in a patterned semiconductor comprising the steps of:forming a pad passivation layer on a semiconductor layer;etching a pattern in said pad passivation layer;implanting carbon into said pad passivation layer and into said semiconductor layer at said etched passivation layer pattern; andforming features defined by said etched pad passivation layer pattern,wherein the semiconductor layer is a silicon wafer and the pattern is a shallow trench isolation pattern, said method comprising before the step of implanting carbon the steps of:etching said silicon wafer through said defined shallow trench isolation pattern, trenches being formed to a predetermined depth and having said shallow trench isolation pattern; andforming an oxide layer in said trenches,wherein the carbon is implanted into said silicon wafer in said trenches.