Patent ID: 6337278
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method for forming an electrical contact from the gate to the source or drain of an integrated circuit transistor, said integrated circuit transistor comprising a pair of substantially coplanar spaced apart source and drain regions formed in the substrate of said integrated circuit and having a gate terminal insulatedly disposed between said source and drain regions overlying said substrate, said gate terminal having a first insulating layer overlying said gate terminal, said source and drain regions bounded by said gate terminal and isolation regions, said method comprising:forming a non-conformal layer overlying said integrated circuit, said non-conformal layer having a first thickness overlying said first insulating layer and a second greater thickness overlying said source, drain and isolation regions; forming a first photoresist layer overlying an upper surface of said integrated circuit; forming an opening in said first photoresist layer overlying at least a portion of said gate terminal and a portion of said source and drain regions and a portion of said isolation region; etching said non-conformal layer exposed by said opening in said first photoresist layer to an extent to expose said first insulating layer but to not expose said source and drain and isolation regions; etching said exposed first insulating layer to create an exposed region of said gate terminal; removing said first photoresist and non-conformal layer; forming a conformal etch stop layer over said integrated circuit; forming a second insulating layer over said integrated circuit; forming a second photoresist layer overlying an upper surface of said integrated circuit; forming another opening in said second photoresist layer overlying at least a portion of said exposed region of said gate terminal and a portion of said source and drain region and a portion of said isolation region; etching said second insulating layer exposed by said another opening in said second photoresist layer while leaving said etch stop layer substantially unetched; removing said second photoresist layer; etching said etch stop layer exposed by said etching of said second insulating layer; and depositing a conductive layer thereby connecting said gate terminal to one of said source or drain regions.