Patent ID: 8853674
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A tunneling field effect transistor structure, comprising: a substrate; a plurality of convex structures formed on the substrate, wherein every two adjacent convex structures are separated by a predetermined cavity less than 30 nm in width, the plurality of convex structures comprise a plurality of sets, and each set comprises more than two convex structures; a plurality of floated films formed on tops of the plurality of convex structures, wherein each floated film corresponds to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set is formed as a channel region, and regions of each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region, wherein the source region comprises a heavily doped p-type region, the channel region is a weakly doped p-type region, a weakly doped n-type region or an intrinsic region, the drain region is a heavily doped n-type region, and the tunneling field effect transistor structure further comprises a first region which is a heavily doped n-type region formed between the source region and the channel region, wherein a width of the first region in a direction from the source region to the drain region is less than 5 nm; or wherein the source region comprises a heavily doped n-type region, the channel region is a weakly doped n-type region, a weakly doped p-type region or an intrinsic region, the drain region is a heavily doped p-type region, and the tunneling field effect transistor structure further comprises a second region which is a heavily doped p-type region formed between the source region and the channel region, wherein a width of the second region in a direction from the source region to the drain region is less than 5 nm.