Patent ID: 6589830
Filing Date: 2003-07-08
Classification: H01L

Abstract:
A process for forming a power semiconductor device with reduced input capacitance and improved switching speed, said process comprising:providing a semiconductor substrate comprising a layer of n-doped epitaxially grown silicon; forming a thick oxide layer on an upper surface of said epitaxial layer; patterning said thick oxide layer, thereby forming a narrow terraced gate oxide region on said upper surface of said epitaxial layer, said narrow terraced gate oxide region having a top surface and two side surfaces; forming a gate oxide layer on said upper surface of said epitaxial layer; depositing a layer of polysilicon on said narrow terraced gate oxide region and said gate oxide layer; anisotropically etching said polysilicon layer, thereby forming tapered polysilicon spacers abutting each of said two side surfaces of said narrow terraced gate oxide region; implanting a p-type dopant through said gate oxide layer and a tapered portion of said polysilicon spacers, and driving said p-type dopant in said epitaxial layer, thereby forming p-well regions in said epitaxial layer at its upper surface; and forming a source mask on said epitaxial layer upper surface, implanting an n-type dopant through said gate oxide layer and a tapered portion of said polysilicon spacers, and driving said n-type dopant in said P-well regions, thereby forming N+ source regions in said P-well regions.