Patent ID: 9136360
Filing Date: 2015-09-15
Classification: H01L

Abstract:
1. A method for forming a memory structure, the method comprising: forming a charge storage layer over a semiconductor substrate; forming a first control gate layer over the charge storage layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material, wherein the second control gate layer is in physical contact with the patterned first control gate layer; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein: the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the first and second control gate electrodes, forming a first select gate electrode adjacent a sidewall of the first control gate electrode and a second select gate electrode adjacent a sidewall of the second control gate electrode, wherein the insulating material is between the first and second select gate electrodes.