Patent ID: 6314507
Filing Date: 2001-11-06
Classification: G06F

Abstract:
An Address Generation Unit (AGU) for a processor having a data memory addressable having X and Y operands stored therein and a program decoder, the AGU being operably connected to the data memory and the program decoder, the AGU comprising:alu means for generating addresses of the X and Y operands and including a first and second alu (Arithmethic Logic Unit), a first and second triplet of registers with the fiqrst triplet of registers being operably associated with the first alu and the second triplet of registers being operably associated with the second alu, each of the first and second alu comprising a first stage comprising (Distributed Binary Look-Ahead Carry) adder having an A input, a B input, a carry input connected to receive a first control signal, and a summation output, the first stage further including a means for by passing the first DBLC adder, and selection means for selecting either the summation output or the means for by passing the first DBLC adder as a first output; a second stage that is in parallel with the first stage and including a Carry Sum Adder (csa) having a (csa) A input, a (csa) B input, a (csa) Carry input, a (csa) sum output and a (csa) carry output, a second DBLC adder having a second A inpjut connected to the (csa) carry output, a second B input connected to the (csa) sum output, asecond carry input connected to receive a second control signal, and a second summation output which produces a second output and output selection means for selecting under the control of a third control signal either the first output or the second output as a result; an arithmetic selection means under the control of a fourth control signal for selecting either a first arithmetic or a second arithmetic method of generating the result;control signal means for generating the first, second, third and fourth control signals; andconversion means for converting the result from the first and second alus into the X and Y operands.