Patent ID: 9142625
Filing Date: 2015-09-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a source region, a drain region, and a drain extension region formed in the substrate; and an insulation layer adjacent to the drain extension region, wherein a gate layer and a field plate are formed within the insulation layer, the field plate includes a polysilicon layer, a via, and a metal layer, wherein the field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region, wherein the field plate includes a polysilicon layer enclosed in the insulation layer, a metal layer exposed at the surface of the insulation layer, and a via connecting the polysilicon layer and the metal layer and enclosed in the insulation layer.