Patent ID: 7293151
Filing Date: 2007-11-06
Classification: G06F,G11C

Abstract:
1. A method for transferring data in a memory system comprising: a) storing an internal data packet that is to be transferred, in a buffer storage device, wherein the internal data packet has a packet depth of a first predetermined number of data records, the data to be transferred from at least one individual data record thereof, including a first data record; b) transferring, between the control device and a first set of memory chips, the data to be transferred from the remaining data records, including those of a second and additional data records; c) transferring, between the control device and a second set of memory chips, a second predetermined number of the data of the at least one individual data record that are buffer stored in the buffer storage device, wherein the second predetermined number corresponds to a data width of an internal data bus coupled to the second set of memory chips; d) transferring, between the control device and the second set of memory chips, the data from at least one individual data record that were buffer stored in the buffer storage device but not yet transferred at the completion of step c); and e) repeating steps a)-d) for further internal data packets until data of the respective at least one individual data record, in particular data of the respective first data record, have been transferred into all the memory cells of the second set of memory chips, wherein the memory system is connectable to an external data bus transferring external data packets with data, wherein the data of said internal data packets is identical to the data of said external data packets, and wherein the number of transfer steps required for transferring the data of the at least one individual data record that were buffer stored in the buffer storage device but not yet transferred upon completion of step d) is determined from the quotient of a data width of a bus coupled to the first set of memory chips divided by the number of data records and further divided by the data width of a bus coupled to the second set of memory chips.