Patent ID: 7089431
Filing Date: 2006-08-08
Classification: G06F,Y02D

Abstract:
1. A data processing system comprising: at least one first data processing unit operable to perform preprocessing and output preprocessed data; at least one second data processing unit operable to perform data processing on the preprocessed data and output processing result data; at least one third data processing unit operable to perform postprocessing on the processing result data; a switch operable to switch between a path by which the preprocessed data are output as input data for said second data processing unit, and a path by which the preprocessed data are output to a bypass line; a selector operable to select between and output either the processing resulting data or data output from the bypass line; a bypass unit operable to transfer the preprocessed data input from said first data processing unit to one of said second data processing unit and said third data processing unit; a control unit operable to control said bypass unit; a voltage regulating device operable to supply a power supply voltage to said second data processing unit; a clock generating device operable to supply a clock to said second data processing unit; a power supply interrupting unit operable to interrupt the power supply voltage supplied to said second data processing unit in accordance with a first instruction from said control unit; and a clock interrupting unit operable to interrupt the clock supplied to said second data processing unit in accordance with a second instruction from said control unit; wherein in a case where processing of the preprocessed data by said second data processing unit is not required, said bypass unit is operable to transfer the input preprocessed data to said third data processing unit in accordance with a third instruction from said control unit, and wherein in a case where processing of the preprocessed data by said second data processing unit is not required, said control unit is operable to stop said second data processing unit by interrupting at least one of the power supply voltage and the clock.