Patent ID: 7612586
Filing Date: 2009-11-03
Classification: G11C

Abstract:
1. A low noise analog sampling circuit comprising a transistor coupled to a first feedback loop and to a second feedback loop; wherein during a first operational phase, the first feedback loop is closed such as to affect a state of the transistor in response to an analog input signal; wherein at an end of the first operational phase the first feedback loop is opened and introduces a first noise; wherein during a second operational phase the second feedback loop provides the transistor a feedback signal that is responsive to an amplified error signal; wherein the error signal represents a difference between (i) a sampled signal representative of a state of the transistor short period before the first feedback loop is opened and (ii) a signal representative of a current state of the transistor; wherein at an end of the second operational phase the second feedback loop is opened and introduces a second noise that is attenuated by multiple capacitors of the second feedback loop such as to provide an attenuated second noise that substantially smaller than the first noise; wherein during another operational phase the transistor outputs an output signal responsive to the analog input signal and to the attenuated second noise; and wherein during the first operational phase the second feedback loop is closed and an amplifier of the second feedback loop is set to a non-amplifying state.