Patent ID: 6100161
Filing Date: 2000-08-08
Classification: H01L

Abstract:
A method of fabricating a transistor, comprising the steps of:providing a silicon semiconductor substrate having a pad oxide portion within an active area;depositing a polysilicon layer over said silicon semiconductor substrate and over said pad oxide portion;depositing a pad oxide layer over said polysilicon layer;forming shallow isolation trench regions on either side of said active area;removing said pad oxide layer;etching and removing said polysilicon layer over said pad oxide portion leaving polysilicon portions between said pad oxide portion and said shallow isolation trench regions;replacing said pad oxide portion with a gate oxide portion;forming a gate conductor, having exposed side walls, over said gate oxide portion and between said polysilicon portions;forming sidewall spacers on said exposed side walls of said gate conductor; said sidewall spacers contacting said polysilicon portions;forming source/drain regions in said active area under said sidewall spacers and said polysilicon portions; andforming a salicide portion over said gate conductor and salicide portions over said polysilicon portions;whereby said formation of said salicide layers over said polysilicon portions consumes a portion of said polysilicon portions leaving the remainder of said polysilicon portions to form shallow source/drain junctions underneath said polysilicon portion salicide portions.