Patent ID: 6629161
Filing Date: 2003-09-30
Classification: G06T

Abstract:
A data processing system comprising:a plurality of data processing modules for performing a series of data processing, wherein each of the plurality of data processing modules processes data; a bus connected to each of the plurality of data processing modules; a memory controller for writing the data processed by each of the plurality of data processing modules into a memory via the bus, and for reading out the written data from the memory via the bus; a DMA controller for determining operation of each of the plurality of data processing modules, and outputting an address to the memory controller, the data processed by said data processing module being written at the address and the DMA controller including a data parallel processing control section; wherein: the plurality of data processing modules includes first and second data processing modules, and the second data processing module is subsequent to the first data processing module in the series of processing; and the DMA controller has a coordinate counter for managing the address, and according to a value of the coordinate counter, the DMA controller controls the first and second data processing modules so that the second data processing module starts data processing before the first data processing module completes data processing.