Patent ID: 6035364
Filing Date: 2000-03-07
Classification: G06F,H04N

Abstract:
A computer chip which performs data transfers using selected data lines of an on-chip bus, comprising:an on-chip bus comprised on said chip comprising a plurality of data lines, wherein each of said data lines is operable to carry a data bit;one or more transmitters comprised on said chip coupled to said on-chip bus operable for transmitting data on said on-chip bus;one or more receivers comprised on said chip coupled to said on-chip bus operable for receiving data transferred on said on-chip bus;wherein each of said one or more transmitters includes bit transfer logic which operatively couples to said on-chip bus, wherein said bit transfer logic for each transmitter operates to selectively assign data streams on selected ones of said data lines comprising said on-chip bus;wherein the selected ones of said data lines comprising the on-chip bus includes less than all of said data lines; andwherein each of said one or more receivers includes bit receive logic operable to receive said assigned data streams on said selected ones of said data lines comprising said on-chip bus.