Patent ID: 7788452
Filing Date: 2010-08-31
Classification: G06F

Abstract:
1. A digital data processing system, comprising: a memory; at least one processor having at least one associated cache for temporarily caching data from said memory; at least one device having a device cache, said device cache having a fixed number of slots for caching data, said fixed number being greater than one, each slot caching a cache line of data; and a cache coherency mechanism, said cache coherency mechanism including a cache line state directory structure, said cache coherency mechanism selectively determining whether to send cache line invalidation messages to said at least one device using state information in said cache line state directory structure, wherein at least a portion of said cache line state directory structure associated with said at least one device contains exactly said fixed number of cache line entries, each entry having a fixed correspondence to a unique respective one of said fixed number of slots for caching data of said device cache.