Patent ID: 7573765
Filing Date: 2009-08-11
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: an internal address generation circuit which generates an internal signal based on input address data; a first internal address control signal generation part which generates a first internal address control signal and includes a function for fixing said first internal address control signal at a predetermined level with the elapse of a fixed period of time; a second internal address control signal generation part which generates a second internal address control signal according to an input of a predetermined command, said second internal address control signal instructing said internal address generation circuit to generate said internal address signal based on said address data; and an internal address control signal selection circuit which selects according to an input test mode signal either said first internal address control signal or said second internal address control signal, said internal address control signal selection circuit also including an OR gate transistor which transmits to said internal address generation circuit, and at the time of a test mode said internal address control signal selection circuit selects said second internal address control signal and transmits to said internal address generation circuit.