Patent ID: 6226212
Filing Date: 2001-05-01
Classification: G11C

Abstract:
A simultaneous erasure type nonvolatile semiconductor memory device comprising:a semiconductor substrate;a plurality of memory cells formed over said semiconductor substrate and each including a control gate and a floating gate;a plurality of word lines coupled to the control gates of said plural memory cells;a plurality of data lines including a plurality of odd data lines and a plurality of even data lines and formed of a first metal wiring layer extending in a predetermined direction;a select transistor formed over said semiconductor substrate for coupling said plural memory cells and said plural data lines selectively;a control signal line fed with a control signal (SiDU/D) for controlling said select transistor, extending in a direction perpendicular to said predetermined direction, and formed of a second metal wiring layer different from said first metal wiring layer;a plurality of sense amplifiers including a plurality of odd sense amplifiers respectively coupled to said plural odd data lines and a plurality of even sense amplifiers respectively coupled to said plural even data lines;a plurality of transistors (Qd2, Qs0, Qs0', Qs1 and Qs1') for setting said even data lines to a predetermined potential when said odd sense amplifiers are activated whereas said even sense amplifiers are inactivated, and for setting said plural odd data lines to a predetermined potential when said even sense amplifiers are activated whereas said odd sense amplifiers are inactivated;a first power supply circuit for supplying said odd sense amplifiers with their operating voltage; anda second power supply circuit for supplying said even sense amplifiers with their operating voltage,wherein said first power supply circuit includes first and second output transistors having source/drain paths coupled to said odd sense amplifiers, and said second output transistor is selectively brought into an active state after said first output transistor is brought into an active state, andwherein said second power supply circuit includes third and fourth output transistors having source/drain paths coupled to said even sense amplifiers, and said fourth output transistor is selectively brought into an active state after said third output transistor is brought into an active state.