Patent ID: 6372619
Filing Date: 2002-04-16
Classification: H01L

Abstract:
A method for fabricating wafer level chip scale package (CSP) with discrete package encapsulation comprising the steps of:providing a pre-processed wafer having a first plurality of bond pads formed on top and a passivation layer formed in-between the pads; depositing a first conductive metal layer for I/O redistribution on top of said passivation layer and said first plurality of bond pads; depositing a first photoresist (PR) material forming a first PR layer on top of said first conductive metal layer; patterning said first PR layer to form a second plurality of trench openings each adapted to separate two IC chips and a third plurality of via openings each exposing said first conductive metal layer; depositing a second photoresist material and filling said second plurality of trench openings; filling said third plurality of via openings with a second conductive metal forming a third plurality of vias; removing said first PR material without disturbing said second PR material; lithographically forming I/O redistribution lines from said first conductive metal layer; forming an encapsulant layer on top of said I/O redistribution lines and embedding said second PR material and said third plurality of vias; planarizing said encapsulant layer exposing top surfaces of said second PR material and said third plurality of vias; removing said second PR material forming a second plurality of trench openings dividing said IC chips into discrete packages; removing said first conductive metal layer in said second plurality of trench openings; and attaching a third plurality of solder balls on top of said third plurality of vias.