Patent ID: 6400021
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A wafer level package comprising:a semiconductor chip; a plurality of bond pads formed on a surface of the semiconductor chip; a lower dielectric layer formed on the surface of the semiconductor chip, the lower dielectric layer having vias and grooves, wherein the vias expose the bond pads and the grooves are disposed at a position spaced a predetermined distance from the vias; a metal pattern deposited on a surface of the lower dielectric layer, a surface of the vias, and a surface of the grooves; an upper dielectric layer formed on the lower dielectric layer and the metal pattern, the the upper dielectric layer comprising ball lands through which a portion of the metal pattern deposited on a surface of the grooves is exposed; an upper bump metal pattern formed on the portion of the metal pattern exposed at the ball lands and sidewalls of the upper dielectric layer; and a solder ball formed on the under bump metal pattern formed on the ball lands, the solder ball being electrically connected to the metal pattern deposited on the grooves.