Patent ID: 6384659
Filing Date: 2002-05-07
Classification: G06F

Abstract:
An IC (Integrated Circuit) including internal circuitry to which a multiphase clock is distributed, said IC comprises:a plurality of 1/n clock, main wiring drivers each including frequency dividing means for dividing a frequency of an input clock by n (n being a positive integer) to thereby output a 1/n clock and drive means for delivering said 1/n clock to a corresponding 1/n clock main wiring; a plurality of normal clock, main wiring drivers each including delay means for delaying an input clock to thereby output a normal clock and drive means for delivering said normal clock to a corresponding normal clock main wiring; a clock distributing circuit including lock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing said clock distributed to each of said plurality of 1/n clock, main wiring drivers and said plurality of normal clock, main wiring drivers; a wiring wiring outputs of all of said plurality of repeat buffers; a wiring wiring outputs of all of said plurality of 1/n clock, main wiring drivers; and a wiring wiring outputs of all of said plurality of normal clock, main wiring drivers.