Patent ID: 6032174
Filing Date: 2000-02-29
Classification: G06F

Abstract:
System for processing of data comprising a central processor system comprising at least one signal processor (SPU) for processing and administration of signals which comprises a cooperation buffer (JBU), wherein the signal processor (SPU) cooperates with at least one execution processor (IPU.sub.i:i=1, . . . n) comprising a multiport register memory (RM) wherein the system further comprises a system memory (SM), characterized in,that at least one program level (THL, BAL) comprises at least two identical register sets in the register memory (RM) which comprises at least one signal input port (A), a signal output port (B) and a data access port (C) wherein signal data transports between the signal processor (SPU) and the execution processor(s) (IPU.sub.i) are carried out by the signal processor (SPU) wherein signal data is transferred to the memory (RM) of the execution processor (IPU.sub.i) during execution by the execution processor (IPU.sub.i) and in that when switching from a job using data from a first register set to another job using data from another register set, the register sets are switched so that consecutive program executions by the execution processor (IPU.sub.i) can be done directly without any intermediate signal data transports.