Patent ID: 7092466
Filing Date: 2006-08-15
Classification: H03L,H04L

Abstract:
1. A deserializer for deserializing a high data rate bit stream to extract a set of bits, the deserializer comprising: a data sampler that oversamples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream; a serial to parallel converter coupled to the data sampler that converts the serial group of samples into a parallel group of samples, wherein the parallel group of samples corresponds to the set of bits, at least one bit preceding the set of bits, and at least one bit subsequent to the set of bits; a windowing block coupled to the serial to parallel converter that includes a plurality of overlapping sampling windows, wherein each overlapping sampling window receives a plurality of samples that correspond to a respective target bit and adjacent bits and produces a single bit output, wherein each single bit output represents a corresponding one of the set of bits; and a phase error detection block coupled to the windowing block that detects errors in the alignment of the overlapping sampling windows of the windowing block and that directs the windowing block to adjust operation of the plurality of overlapping sampling windows to produce the single bit outputs.