Patent ID: 6724328
Filing Date: 2004-04-20
Classification: H03M,H04L

Abstract:
A method of aligning a boundary between bytes of a deserialized serial data signal that has been input into a programmable logic device, said programmable logic device having a serial data interface with a plurality of channels, and having a programmable logic core, said method comprising:receiving a respective serial data signal on each respective channel of said serial data interface; for each said channel, deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal; transmitting said deserialized data signal with said initial candidate byte boundary from each said channel of said serial data interface to said programmable logic core; processing said deserialized signal with said initial candidate byte boundary on each said channel in said programmable logic core to validate each said initial candidate byte boundary; and sending a respective byte alignment error signal from said programmable logic core to a respective channel of said serial data interface when said candidate boundary on said respective channel is determined to be invalid.