Patent ID: 6373760
Filing Date: 2002-04-16
Classification: G11C

Abstract:
A static type semiconductor memory device including a plurality of memory cells arranged in plural rows and plural columns, a word line provided corresponding to each row, and a pair of bit lines provided corresponding to each column, and adopting a redundancy system in which a defective row or column is replaced with a spare row or column, said static type semiconductor memory device comprising:a first switching element which is provided corresponding to each word line and which is connected between the corresponding word line and a line of a reference potential for setting the corresponding memory cells to be in a non-activated state by becoming electrically conducted when the corresponding word line is not selected; a power source line having two ends which is provided corresponding to each row or column and whose one end is connected to a power source node of each memory cell in the corresponding row or column; a second switching element which is provided corresponding to each power source line and which is connected between the other end of the corresponding power source line and a line of a power source potential, said second switching element having a predetermined conduction resistance value larger than a conduction resistance value of said first switching element; and a program circuit which is provided corresponding to each row or column and which includes a fuse that is blown when the corresponding row or column is defective, said program circuit letting said second switching element become electrically non-conducted according as the fuse is blown.