Patent ID: 6812781
Filing Date: 2004-11-02
Classification: G09G,H03F

Abstract:
A differential amplifier comprising:a first differential amplifier circuit having a first differential pair and operating based on a common input voltage; a second differential amplifier circuit having a second differential pair and operating based on the common input voltage; a first current mirror circuit provided in the first differential amplifier circuit and formed from a first transistor of a primary conductive type and a second transistor of the primary conductive type; a second current mirror circuit provided in the second differential amplifier circuit and formed from a first transistor of a secondary conductive type and a second transistor of the secondary conductive type; a third transistor of the primary conductive type having a gate connected to a first output line of the first differential amplifier circuit; and a third transistor of the secondary conductive type connected in series to the third transistor of the primary conductive type and having a gate connected to a second output line of the second differential amplifier circuit, wherein at least one of the first differential pair and the second differential pair is formed from a pair of transistors having a driving ability difference therebetween, wherein a third output line connected between the third transistor of the primary conductive type and the third transistor of the second conductive type outputs an output voltage, and the first, the second and the third output lines are shorted together, wherein the first differential amplifier circuit includes: a fourth transistor of the secondary conductive type connected in series to the first transistor of the primary conductive type and the common input voltage is applied to a gate of the fourth transistor of the secondary conductive type; and a fifth transistor of the secondary conductive type connected in series to the second transistor of the primary conductive type and having a driving ability different from the fourth transistor of the secondary type, wherein the fourth transistor of the secondary conductive type and the fifth transistor of the secondary conductive type form the first differential pair, and the first output line is connected to a gate of the fifth transistor of the secondary conductive type through a first oscillation prevention capacitor and to the third output line through the first oscillation prevention capacitor and a first static electricity protection resistor.