Patent ID: 8108850
Filing Date: 2012-01-31
Classification: G06F,Y02D

Abstract:
1. A power-aware compiling method by a compiler, operating through a CPU and a RAM in a computer, and rescheduling compiled machine codes output in achieving power-aware compiling comprising the following steps: establishing a control flow graph and a data flow graph of an application program; dividing said control flow graph into a plurality of basic blocks according to the usage of functional units used by said application program; analyzing said control flow graph and said data flow graph, establishing a power model of said application program based on the analysis, and assigning each of said functional units with one power mode according to the power model; determining whether idle and identical said functional units are independent between the identical and idle functional units; if independent, program codes of said idle and identical functional units are merged into a new basic block; turning off said idle and identical functional units; assigning an appropriate power mode to said new basic block; and merging said plurality of basic blocks with identical power modes.