Patent ID: 6343040
Filing Date: 2002-01-29
Classification: G11C

Abstract:
An auto precharge control signal generation circuit of a semiconductor memory device, the circuit comprising:output enable means that is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal in an active period of a column bank address signal; delay means that generates a 1 clock delay signal by delaying the active period of the column bank address signal by 1 clock cycle, and generates the 1 clock delay signal having a longer active period, including a non-active period between a previous column bank address signal and a present column bank address signal, in the event the burst length is 1; and assembly means that generates an auto precharge control signal by combining the column bank address signal and the 1 clock delay signal in response to the output enable signal, in order to perform an auto precharge operation after delaying 2 clock cycles from the input time point of the last data generated in response to a continuous auto precharge burst write command.