Patent ID: 6204110
Filing Date: 2001-03-20
Classification: H01L,Y10S

Abstract:
A semiconductor processing method of forming an SRAM comprising:providing a first pull down transistor having a gate, a source and a drain;providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor;providing a Vcc node;forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node;forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; andthe forming of at least one of the first and second resistors comprising:forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors;forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an outer surface and comprising a second insulative material; andforming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductor material defining the at least one of the first and second resistors.