Patent ID: 6437428
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A semiconductor device comprising:a base substrate comprised of film and having a first surface and a second surface that is opposed to said first surface; a plurality of electric conductor layers formed on said first surface of said base substrate; a semiconductor chip mounted through an adhesive material on said first surface of said base substrate and arranged over said plurality of electric conductor layers, said semiconductor chip having a plurality of semiconductor elements and a plurality of external terminals formed on its main surface; a plurality of insulation layers formed between said electric conductor layers and said semiconductor chip; a plurality of bonding wires to which said external terminals and said electric conductor layers are electrically connected, respectively; a plurality of bump electrodes arranged on said second surface and electrically connected with said electric conductor layers, and a resin member sealing said semiconductor chip, said electric conductor layers and said bonding wires; wherein said insulation layers are separated from each other in a plane view in an area on which said semiconductor chip is mounted, and wherein the semiconductor device further comprises a plurality of electric conductor layers for plating formed at the peripheral area of said semiconductor chip, wherein each of said electric conductor layers for plating extends continuous with one of said electric conductor layers and reaches to a side of said base substrate; and a plurality of insulation layers formed over said first surface of said base substrate and at said peripheral area of said semiconductor chip, so as to cover said plurality of electric conductor layers for plating.