Patent ID: 6452266
Filing Date: 2002-09-17
Classification: H01L

Abstract:
A semiconductor device comprising four chips each having on its surface a memory circuit and a plurality of pads including a plurality of address pads for use in inputting address signals of said memory circuit along with a plurality of input/output pads for inputting and outputting input/output data and also having a pair of long sides and a pair of short sides, a substrate supporting thereon said four chips and having on its surface a plurality of pads including address pads and input/output pads as electrically connected to respective ones of the address pads and input/output pads of said four chips, and a plurality of external terminals being electrically connected to the address pads and input/output pads on said substrate and including address terminals and input/output terminals as provided on a bottom surface of said substrate,said four chips are each such that said input/output pads are of Ã—16 input/output bit configuration, corresponding pads in respective plurality of address pads of each of said four chips are connected in common to said address terminals of said external terminals, and the plurality of input/output pads of each of said four chips are connected to said input/output terminals of said external terminals in a way independent per each chip and are thus caused by said four chips to have Ã—64 input/output bit configuration, wherein said substrate is of a polygonal shape having a pair of long sides and a pair of short sides, said substrate has a multilayered wiring lead structure with electrical leads of a plurality of layers, said four chips are laid out into a matrix of two rows in a direction along the short sides of said substrate and two columns in a long side direction, address pads of chips laid out in the short side direction of said substrate are electrically connected together by a first lead layer extending in the short side direction of said substrate, and address pads of chips laid out in the long side direction of said substrate are electrically connected together by a second lead layer being different from said first lead layer and extending in the long side direction of said substrate.