Patent ID: 6611465
Filing Date: 2003-08-26
Classification: G11C

Abstract:
In a memory component including a dummy cell with a dummy bit line and a plurality of wordlines, the memory component having a memory component capacitance and memory component operational characteristics, including dummy bitline capacitance of the dummy bitline, a diffusion replica delay circuit, comprising:a. a diffusion replica capacitor coupled to the dummy bit line and one wordline of the plurality of wordlines, coupled to the memory component, and capable of storing a predetermined replica charge representative of the dummy bitline capacitance, the diffusion replica capacitance of the diffusion replica capacitor being substantially matched to the dummy bitline capacitance, and b. a diffusion replica transistor coupled with the diffusion replica transistor, coupled with the diffusion replica capacitor, and coupled between the diffusion replica capacitor and a charge sink, the transistor being disposed to control the magnitude of the predetermined replica charge.