Patent ID: 7800946
Filing Date: 2010-09-21
Classification: G11C

Abstract:
1. A flash memory device comprising: a plurality of memory cell blocks including strings, each string including a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor; a control unit for generating a block select signal in response to an address signal and for generating an operation control signal in response to a command signal; a program speed calculation unit for determining a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells, wherein the initial program voltage is applied in a program operation of an increment step pulse programming (ISPP) method; a voltage generator for generating operating voltages including the initial program voltage according to the operation control signal, wherein a level of the initial program voltage is determined by the program speed calculation unit; and a block select unit that transfers the operating voltages to a memory cell block corresponding to the block select signal.