Patent ID: 6169507
Filing Date: 2001-01-02
Classification: H03M

Abstract:
A sigma-delta modulator comprising: at least two integrating stages connected together; a first comparator connected to an output of a last integrating stage of said at least two integrating stages, said first comparator generating a signal having a first logic level when an input signal is positive and generating a signal having a second logic value when the input signal is negative, regardless of an absolute value of the input signal; a second comparator having an input connected in common to an input of said first comparator, said second comparator generating an output signal having a positive logic value when the input signal is positive and generating an output signal having a negative logic value when the input signal is negative, and the output signal having an increasing logic level when the input signal exceeds one or more predefined thresholds of increasing value; a filter connected to an output of said second comparator; and an adder connected to an output of said filter and between the last integrating stage of said at least two integrating stages and said first comparator, said filter and said second comparator forming a feedback path with said adder for adding a feedback signal filtered by said filter to the output signal provided by the last integrating stage.