Patent ID: 8093932
Filing Date: 2012-01-10
Classification: H03K

Abstract:
1. A power-on reset signal generation circuit of a semiconductor memory apparatus, comprising: an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal, wherein the level detection voltage dividing unit comprises: wherein the band gap voltage level detector comprises: wherein the level detecting part is configured to be applied with the band gap voltage to its positive power supply terminal and enable the drop detection signal when the drop voltage is higher than a target level.