Patent ID: 8206603
Filing Date: 2012-06-26
Classification: B82Y,C23F,H01L,Y10S

Abstract:
1. A method of forming a plurality of transistor gate constructions, comprising: forming a first gate dielectric over a semiconductor substrate; forming a charge retaining layer comprising nanodots over the first gate dielectric, the nanodots comprising a late transition metal; forming second gate dielectric over the nanodot-comprising layer; forming conductive control gate material over the second gate dielectric; etching the conductive control gate material and the second gate dielectric to expose the first gate dielectric through the nanodot-comprising charge retaining layer and form a plurality of transistor gate constructions over the semiconductor substrate which respectively comprise the first gate dielectric, the charge retaining layer comprising nanodots, the second dielectric, and the conductive control gate material; exposing nanodots of the nanodot-comprising layer that are received between the plurality of transistor gate constructions to a gas comprising PF after the exposing, etching remaining of the nanodots that are received between the plurality of transistor gate constructions with an aqueous solution comprising NH