Patent ID: 7065728
Filing Date: 2006-06-20
Classification: G06F

Abstract:
1. A method for placing a plurality of electrostatic discharge (ESD) protection devices within an integrated circuit design, said method comprising: defining a region within said integrated circuit design; generating a list of ESD-susceptible circuits located within said defined region; determining a preferred location for placing an ESD protection device within said region; placing said ESD protection device at said determined preferred location; determining whether or not any ESD-susceptible circuit within said list of ESD-susceptible circuits is protected by the placement of said ESD protection device; and generating a set of all ESD-susceptible circuits with said integrated circuit design and associating said set of all ESD-susceptible circuits with said ESD protection device if all ESD-susceptible circuits within said list of ESD-susceptible circuits are protected by the placement of said ESD protection device.