Patent ID: 6981096
Filing Date: 2005-12-27
Classification: G06F

Abstract:
1. An architecture for a first and second level memory hierarchy comprising: a first data storage array to serve the first level memory hierarchy (L a second data storage array to serve the second level memory hierarchy (L wherein said first data storage array is smaller and has a same organization and set-associativity with respect to said second data storage array; a single address translation directory to serve the directory requirements of the first and second level memory hierarchy in a single directory satisfying the organization requirements of both said first and second level memory hierarchy; said single address translation directory providing an apparent set-associativity of the first level memory hierarchy to be the same as that of the second level memory hierarchy; and said single directory employs a set of address decoders and compare circuits for performing address translation of both the first and second level memory hierarchy; and wherein said translation directory is comprised of islands, each of said islands includes a number of blocks equal to that in said first level memory hierarchy, each said island having one set of address decoders and sensing circuits which are used for both a first and second level translation and replacement lookup and wherein the single directory is comprised of a plurality of islands, each of said islands includes a number of blocks equal to that in the first level memory hierarchy, and all of the islands share common compare circuits for both the first and second memory hierarchy and where the number of compares necessary regardless of said first level hierarchy is equal to the set-associativity of said second level hierarchy; achieve a smaller size; and whereby said (L