Patent ID: 6055657
Filing Date: 2000-04-25
Classification: G01R

Abstract:
A test board connected to a tester for testing a plurality of integrated circuit (IC) devices, each IC device having a plurality of output terminals, the terminals comprising at least one merged data output terminal, the test board comprising:a plurality of sockets to which the corresponding plurality of IC devices are inserted;a plurality of input/output (I/O) pins connected to the tester;mode selection signal pins connected to the tester for selecting an operational mode of the IC devices, the operation mode being one of a merged data output test mode and a standard test mode;control signal pins connected to the tester for controlling functions of the IC devices;wiring patterns for electrically connecting the output terminals of each of the IC devices and the I/O pins, wherein the at least one merged data output terminal of the IC device containing merged output data of the IC device is sequentially connected to the I/O pins when the IC devices are operated in the merged data output test mode, and wherein the output data terminals containing standard output data of the IC devices are sequentially connected to the I/O pins when the IC devices are operated in the standard test mode; andscan signal pins connected to the tester for selectively enabling the IC devices inserted in the sockets.