Patent ID: 6716749
Filing Date: 2004-04-06
Classification: H01L

Abstract:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of:(a) forming a first interconnection groove in a first silicon oxide based interlayer insulating film over a first main surface of a wafer; (b) forming a first barrier metal film over the first silicon oxide based interlayer insulating film both outside and inside the first interconnection groove; (c) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove; (d) removing both the first interconnection metal film and the first barrier metal film outside the first interconnection groove by chemical mechanical polishing; and thereafter (e) performing cleaning of upper surfaces of both the first silicon oxide based interlayer insulating film and the first interconnection metal film with liquid containing organic acid; and thereafter (f) performing ammonia plasma treatment said upper surfaces so as to reduce and nitride said upper surfaces; and thereafter (g) forming a silicon-containing copper diffusion barrier insulating film over the first main surface by plasma CVD with a silane based mixed gas.