Patent ID: 8106439
Filing Date: 2012-01-31
Classification: H01L

Abstract:
1. A method of manufacturing a fin-type field effect transistor, said method comprising: providing a semiconductor on insulator wafer comprising a substrate, an insulator layer on said substrate and a semiconductor layer on said insulator layer; etching said semiconductor layer so as to form, on said insulator layer, a source region, a drain region, and a semiconductor fin that extends from said source region to said drain region without extending laterally beyond said source region and said drain region; forming a gate conductor adjacent said semiconductor fin between said source region and said drain region, wherein said semiconductor fin and said gate conductor are formed such that a first resistance of a first portion of said semiconductor fin between said source region and said gate conductor is less than a second resistance of a second portion of said semiconductor fin between said gate conductor and said drain region and such that a first capacitance between said source region and said gate conductor is greater than a second capacitance between said gate conductor and said drain region, wherein said gate conductor is formed adjacent to said semiconductor fin such that said gate conductor is closer to said source region than said drain region, and wherein said gate conductor is formed adjacent to said semiconductor fin equidistance between said source region and said drain region; and adjusting dimensions of said first portion and said second portion to vary said first resistance and said second resistance.