Patent ID: 9153454
Filing Date: 2015-10-06
Classification: H01L

Abstract:
1. A method of fabricating a high voltage device, comprising: providing a substrate having a dielectric layer, a conductive layer and a photoresist layer disposed on the substrate from bottom to top; patterning the photoresist layer to form a patterned photoresist layer having a first width; performing a first patterning step to pattern the conductive layer and the dielectric layer by taking the patterned photoresist layer as a first mask; forming two lightly doped source/drain regions in the substrate at two sides of the conductive layer by implanting dopants into the substrate, and wherein dopants penetrate the dielectric layer before entering the substrate; after forming the lightly doped source/drain regions, shrinking the first width of the patterned photoresist layer to a second width; performing a second patterning step to pattern the conductive layer and the dielectric layer by taking the shrunk photoresist layer as a second mask so as to form the dielectric layer into a step profile; and removing the shrunk photoresist layer.