Patent ID: 9062378
Filing Date: 2015-06-23
Classification: C23C,H01L

Abstract:
1. A process for the production of an electrically conductive structure, comprising: (i) electrolessly depositing a first layer comprising at least one on at least one of a catalytically activated semiconductor layer and a catalytically activated insulating layer, (ii) depositing a copper interconnect on the first layer, and (iii) electrolessly depositing a second layer comprising at least one alloy on the copper interconnect, wherein the first layer is a diffusion barrier, and the second layer is an encapsulation barrier, to form an electrically conductive structure comprising (1) at least one of the catalytically activated semiconductor layer and the catalytically activated insulating layer, (2) the first layer, (3) the copper interconnect, and (4) the second layer, wherein the first layer and the second layer are adjacent the copper interconnect, and wherein an alloy in at least one of the first layer and the second layer comprises Mo, Re or W in an amount of from 2 to 25 at-% as a refractory metal which increases the thermal stability of the barrier layer, and wherein during the electroless depositing of the first layer a concentration of Mo in an electroless plating solution is 3×10