Patent ID: 6444493
Filing Date: 2002-09-03
Classification: H01L

Abstract:
A method for vertically integrating active circuit planes, comprising the following steps:providing a first substrate comprising at least one integrated circuit in a first main surface thereof and further comprising connecting areas for the integrated circuit as well as outer connecting areas on said first main surface; providing a second substrate comprising at least one integrated circuit in a first main surface thereof and further comprising connecting areas for the integrated circuit as well as open or openable areas on said first main surface; joining the first main surfaces of said first and second substrates in such a way that the connecting areas of the first substrate are connected to those of the second substrate in an electrically conductive manner, and in such a way that the outer connecting areas of the first substrate are in alignment with the open or openable areas of the second substrate; thinning the second substrate; and exposing the outer connecting areas through the open or openable areas.