Patent ID: 6744833
Filing Date: 2004-06-01
Classification: G06F,H04L

Abstract:
An apparatus for resynchronizing data between two modules sharing a common clock comprising:means for storing a plurality of copies of the data in a first one of the modules in response to the common clock; a counter having the common clock as an input and providing a clock signal to each location in the storing means in a recirculating manner so that the plurality of copies are stored on a recirculating basis in response to the common clock; means in a second one of the modules for selecting one of the copies from the storing means; and means for generating a select signal for the selecting means in response to a delayed version of the common clock so that the copy selected from the storing means is assured to be in a stable state, the copies being selected in turn on a recirculating basis; whereby the data in the second module is resynchronized.