Patent ID: 8205186
Filing Date: 2012-06-19
Classification: G06F

Abstract:
1. A method comprising: synthesizing, placing, and routing a netlist to create an integrated circuit design in a target architecture; selecting at least one first signal from a set of available signals by determining signals in the netlist that correlate to a signal in a hardware description language (HDL) and that represents an identical function in the netlist as in the HDL for instrumentation; selecting at least one second signal from the set of available signals for instrumentation, wherein the at least one second signal is marked as reserved for instrumentation at a later time; adding at least one first extra circuit element to the integrated circuit design in the target architecture for instrumentation for said at least one first signal, wherein said at least one first extra circuit element is utilized in instrumenting said at least one first signal; and adding at least one second extra circuit element to the integrated circuit design in the target architecture for instrumentation, wherein said at least one second extra circuit element is different from said at least one first extra circuit element, wherein said at least one second extra circuit element is not utilized in instrumenting any signal, and marked to prevent from being optimized away, wherein said at least one second extra circuit element is designed to be connected to the at least one second signal other than the first signal, wherein the at least one second extra circuit element is instrumented concurrently with the at least one first extra circuit element, and wherein the selecting and adding are performed on a representation of the circuit design in the target architecture, the representation being stored in a memory of a data processing system which includes a processor which performs the selecting and adding.