Patent ID: 6061822
Filing Date: 2000-05-09
Classification: G06F

Abstract:
An IDE controller comprising:an IDE interface having a primary channel for transmitting primary data received from a primary device and a secondary channel for transmitting secondary data received from a secondary device;a primary CRC circuit, coupled to the primary channel, for receiving the primary data, performing an operation on the primary data and generating primary CRC values;a secondary CRC circuit, coupled to the secondary channel, for receiving the secondary data, performing an operation on the secondary data and generating secondary CRC values, wherein the primary data and the secondary data are transmitted from the IDE interface to their respective CRC circuits concurrently;a compare circuit, coupled to the primary CRC circuit and to the secondary CRC circuit, for concurrently comparing the primary CRC values with the secondary CRC values and generating compare values; anda synchronization circuit operably coupled to the compare circuit and configured to synchronize the comparison of the primary CRC value and the secondary CRC value.