Patent ID: 7050334
Filing Date: 2006-05-23
Classification: G11C

Abstract:
1. A program control circuit for controlling the programming of a memory cell within a flash memory device, the flash memory device including an array of memory cells wherein each memory cell is connected to a word line, a bit line, and a source line and may be programmed by supplying a program current to a corresponding bit line, the program control circuit comprising: a level sensing control portion that is selectively enabled or disabled in response to a first program control signal, that, when enabled, outputs a voltage control signal reflecting a comparison of a bit line voltage applied to the memory cell and a reference voltage; a switching control portion that outputs a switching bias signal in response to the voltage control signal and a second program control signal; a current sink that provides a predetermined current to a ground voltage in response to a reference bias signal; and a switching circuit connected between the bit line and the current sink, the switching circuit being selectively enabled or disabled in response to the switching bias signal.