Patent ID: 8132045
Filing Date: 2012-03-06
Classification: G06F,G11C

Abstract:
1. A method of recovering data to be written to a memory array that stores one or more bits per cell under the control of a memory controller, comprising: receiving a first portion of data from a host into a memory associated with the memory controller; sending the first portion of data from the memory associated with the memory controller to an on-chip cache that is on a same chip as the memory array, wherein the first portion of data is stored as a safe copy in a safe buffer of the on-chip buffer cache and stored as a target copy in a target buffer of the on-chip cache, wherein the target buffer is configured to write data that is received into such target buffer into the memory array; prior to confirming that the first portion of data is written to the memory array, sending a signal to the host indicating that the memory of the memory controller can receive more data and subsequently receiving a second portion of data from the host into the memory associated with the memory controller; maintaining the safe copy of the first data portion in the on-chip cache until writing of the first portion of data to the memory array is confirmed as successful; and when the writing of the first portion of data from the target buffer to the memory array is unsuccessful, then recovering the first portion of data from the safe copy in the on-chip cache and writing the first portion of data to an alternative location in the memory array.