Patent ID: 7376009
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array which is configured to have a plurality of memory cells arranged in a matrix, each of said plurality of memory cells being connected to a word line and a bit line and being capable of storing 4 values; and a control circuit which controls the potentials of the word line and bit line according to input data and writes data into the memory cell, wherein the control circuit, in a first write operation, changes the threshold voltage of the memory cell from a first threshold voltage to either the first threshold voltage or a second threshold voltage (the first threshold voltage<the second threshold voltage), and in a second write operation, changes the threshold voltage of the memory cell to either the first threshold voltage or a third threshold voltage (the first threshold voltage<the third threshold voltage) if the threshold voltage of the memory cell is the first threshold voltage, and to either a fourth threshold voltage (the second threshold voltage<=the fourth threshold voltage) or a fifth threshold voltage (the fourth threshold voltage<the fifth threshold voltage) if the threshold voltage of the memory cell is the second threshold voltage, and which, in the first and second write operations, raises a program voltage in increments of ΔVpgm and carries out a write operation by repeating a program and verify operation, ΔVpgm in the first write operation being larger than ΔVpgm in the second write operation.