Patent ID: 6101127
Filing Date: 2000-08-08
Classification: G11C

Abstract:
An operating voltage selection circuit for a non-volatile semiconductor memory device, comprising:means for reading at least one one-time programmable non-volatile memory cell, the means for reading suitable to generate a first signal which indicates a requested type of operating voltage of the non-volatile memory device, wherein the first signal depends on the programmed or non-programmed state of the at least one one-time programmable non-volatile memory cell;a memory enabling circuit, comprising an enabling inverter and a circuit for modifying a switching threshold of the enabling inverter as a function of the first signal;an output circuit, connected to output terminals of the non-volatile semiconductor memory device, comprising an output inverter and a circuit for modifying an output current of the output inverter as a function of the first signal; anda circuit for the internal synchronization of the non-volatile semiconductor memory device, comprising one or more sets of transistors, each set of transistors being connected in a series/parallel configuration, and operating to delay the first signal by a predetermined amount in order for the one or more sets of transistors to generate one or more second signals for internally synchronizing the non-volatile semiconductor memory device.