Patent ID: 6573762
Filing Date: 2003-06-03
Classification: G06G

Abstract:
An analog pulse processor implemented as an integrated circuit comprising:a charge amplifier adapted to receive a charge pulse signal from a detector and to provide an ac amplified output voltage from the charge pulse signal when the charge pulse signal is above an adjustable threshold dc voltage level that is slightly above a constant reference dc voltage level, the adjustable threshold dc voltage level and the constant reference dc voltage level being supplied by a voltage reference source; a shaping amplifier that ac amplifies and filters the ac amplified output voltage of the charge amplifier and provides an output; a peak detector circuit that receives the output of the shaping amplifier and charges a peak sensing capacitor to a voltage level proportional to the strength of the charge pulse signal from the detector; a comparator that receives the adjustable threshold dc voltage level and the voltage level of the peak sensing capacitor and provides an enable pile-up rejection output signal when the charge pulse signal is above the adjustable threshold dc voltage level, and further provides sample ready and reset signals; a pile-up rejection circuit that receives the enable pile-up rejection output signal and provides a pile-up rejection output which is directed to a gain control input of the shaping amplifier or to an electronic switch located between the peak detector circuit and the peak sensing capacitor to disable charging of the peak sensing capacitor for a period of time sufficient for the processor to complete the processing of a single charge pulse signal from the detector once a first such charge pulse signal has been entered into the peak sensing capacitor without interference from an overlapping following another charge pulse signal; a buffer amplifier that receives the voltage level from the peak sensing capacitor and provides a peak hold output signal; and a ladder bias circuit that receives a low ladder voltage and a high ladder voltage from the voltage reference source and further receives an enable ladder bias signal from the comparator and provides a low ladder bias voltage output and a high ladder bias voltage output when the charge pulse signal is above the adjustable threshold dc voltage level.