Patent ID: 8679903
Filing Date: 2014-03-25
Classification: H01L

Abstract:
1. A method of fabricating a vertical insulated gate transistor on a semiconductor substrate, the method comprising the steps of: forming a horizontal isolation region in the semiconductor substrate, the horizontal isolation region separating and electrically isolating an upper portion of the semiconductor substrate from a lower portion of the semiconductor substrate; forming a vertical semiconductor pillar with one or more flanks and a cavity, the pillar resting on the upper portion of the semiconductor substrate; and forming a dielectrically isolated gate, the gate including an internal portion within the cavity and an external portion resting on the flanks of the pillar and on the upper portion of the semiconductor substrate, wherein the step of forming the gate includes coating one or more internal walls of the cavity with an isolating layer and filling the cavity with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks of the pillar, and to form two connecting semiconductor regions extending between a source region and a drain region of the transistor.