Patent ID: 7840727
Filing Date: 2010-11-23
Classification: G06F,Y02D

Abstract:
1. A converter circuit comprising: a register that receives plural items of data serially and that samples the received data so as to output plural items of the sampled data in parallel; a selector that receives said plural items of the sampled data output from said register and that selects one of said plural items of the sampled data in accordance with a control signal; a circuit that generates said control signal supplied to said selector so that said plural items of the sampled data are serially output from said selector in a particular sequence corresponding to a sequence in which said plural items of data have been serially received by said register; a first counter that generates a control signal for said register to sample said plural items of data serially; and a second counter that generates said control signal for said selector, wherein: said first counter is operated by a first clock signal; and said second counter is operated by a second clock signal different from said first clock signal; wherein a change-over of clocking from said first clock signal to said second clock signal to operate said second counter is performed.