Patent ID: 6630379
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A process for forming a memory cell structure, the process comprising:forming a deep trench having a plurality of side walls in a planar semiconductor substrate; forming a storage capacitor at the bottom of the deep trench; forming a vertical transistor extending down at least one side wall of the deep trench above the storage capacitor, the transistor having a source diffusion extending in the plane of the substrate adjacent the deep trench; forming an isolation extending down at least one other sidewall of the deep trench opposite the vertical transistor; forming shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends; forming a gate conductor extending within the deep trench; forming a wordline extending over the deep trench and connected to the gate conductor; and forming a bitline extending above the surface plane of the substrate having a contact to the source diffusion between the shallow trench isolation regions.