Patent ID: 6404679
Filing Date: 2002-06-11
Classification: G11C

Abstract:
An integrated circuit for a memory including a plurality of bit lines, a plurality of word lines which intersect the plurality of bit lines, and a plurality of floating-gate transistors at intersections of the plurality of word lines and the plurality of bit lines, each floating-gate transistor maintaining an electrical state representing a stored piece of data, the integrated circuit comprising:at least one comparator to compare a current flowing through a selected bit line of the plurality of bit lines with a reference current; a voltage generator that generates an increasing bias voltage to a gate of at least one floating-gate transistor when the current flowing through the selected bit line is less than the reference current, and that generates a constant bias voltage to the gate of the at least one floating-gate transistor when the current flowing through the selected bit line is more than the reference current; and a decoder that outputs digital information representing the stored piece of data by decoding a value of the bias voltage.