Patent ID: 6539467
Filing Date: 2003-03-25
Classification: G06F

Abstract:
A digital system, comprising;a microprocessor having at least a first load/store unit and a second load/store unit; a memory subsystem having at least first memory port connected to the first load/store unit and a second memory port connected to the second load/store unit; address generation circuitry in the first load/store unit having a first address output connected to the first memory port and a second address output selectively connected to the second memory port, the address generation circuitry operable to provide a first address on the first address output and a second address on the second address output; and an extraction circuit connected to the first memory port, wherein the extraction circuit is operable to provide a first non-aligned data item to the first load/store unit extracted from a first data item accessed in response to the first address and from a second data item accessed in response to the second address.