Patent ID: 6288593
Filing Date: 2001-09-11
Classification: H03K

Abstract:
A CMOS digital electronic circuit comprising:a first section adapted to transmit one of N input signals;a second section selectively configurable in either a first or a second configuration, wherein the second section is adapted to receive the signal transmitted by the first section and one or more control signals, and to output either an inverse of the signal transmitted by the first section or a logical 0 when in the first configuration, or to output either an inverse of the signal transmitted by the first section or a logical 1 when in the second configuration, the output in either configuration being responsive to the one or more control signals, and wherein the second section includes no more than six transistors;wherein the first section comprises an N:1 multiplexer having a multiplexer output node;wherein the second section includes:a second section output node,a first P-channel transistor having a drain, a source connected to VDD, and a gate connected to a first control signal node,a second P-channel transistor having a drain, a source connected to the drain of the first P-channel transistor, and a gate connected to a second control signal node,a third P-channel transistor having a source, a drain connected to the second section output node, and a gate connected to the multiplexer output node,a first N-channel transistor having a drain, a source connected to Ground, and a gate connected to the first control signal node,a second N-channel transistor having a drain, a source connected to the drain of the first N-channel transistor, and a gate connected to the second control signal node, anda third N-channel transistor having a source, a drain connected to the second section output node, and a gate corrected to the multiplexer output node, andwherein the second section is configurable in either the first or second configurations by selectively interconnecting the transistors.