Patent ID: 7709967
Filing Date: 2010-05-04
Classification: H01L

Abstract:
1. An integrated circuit, comprising: a dielectric layer having a bottom surface disposed over a semiconductor substrate; a wire comprising a metal filled trench filled with a layer of metal in said dielectric layer, said metal filled trench extending from a top surface of said dielectric layer toward said bottom surface of said dielectric layer; a set of metal fill shapes filled with said layer of metal in said dielectric layer, said set of metal fill shapes extending from a top surface of said dielectric layer toward said bottom surface of said dielectric layer, said metal fill shapes not contacting said wire; and a plurality of dielectric pedestals disposed in said wire, said dielectric pedestals filled with said dielectric layer, said dielectric pedestals extending from a top surface of said metal filled trench to a bottom surface of said metal filled trench, said dielectric pedestals arranged in an offset-grid of rows and columns, wherein dielectric pedestals in different rows are displaced in a column wise direction from each other.