Patent ID: 6898105
Filing Date: 2005-05-24
Classification: G11C

Abstract:
1. A ferroelectric non-volatile memory device, comprising at least a memory cell including: first and second capacitors each having one electrode connected with one electrode of the other capacitor; at a connection node; and a MIS-FET having a gate electrode connected with the connection node of said first and second capacitors and a source region connected with another electrode of said second capacitor, said gate electrode being formed as a floating gate, wherein one of said first and second capacitors is a ferroelectric capacitor, another one of said first and second capacitors is a paraelectric capacitor, and said one electrode of said capacitor is integrally formed with said gate electrode so as to overlap a part of said source region excluding a boundary between a channel region and said source region of said MIS-FET, and said another electrode of said second capacitor is made of said source region.