Patent ID: 6133755
Filing Date: 2000-10-17
Classification: H03K

Abstract:
An I/O buffer for a data transmission bus for the transmission of a high-frequency and low-swing data signal, comprising:an I/O pad for receiving the data signal from the data transmission bus;an output transistor, wherein a first end is connected to the I/O pad and a second end is connected to the ground, the output transistor is switched to the non-conducting state when the I/O buffer operates in an input mode and to the conducting state when the I/O buffer operates in an output mode;a signal level detector for generating a level-indicating signal of a first logic state if the data signal is higher in magnitude than a reference voltage and a second logic state if the data signal is lower in magnitude than the reference voltage;a resistance regulator, responsive to the level-indicating signal, for generating a resistance-adjusting signal; anda variable-resistance device, wherein a first end is connected to a system voltage equal in magnitude to the high-voltage logic state of the data signal and a second end is connected to the I/O pad; wherein the variable-resistance device can be switched between a low resistance value and a near-infinity resistance value in response to the resistance-adjusting signal from the resistance regulator, in such a manner that the variable-resistance device is switched to the low resistance value having equal potential at both ends of the variable-resistance device when the data signal is greater in magnitude than the reference voltage, and to the near-infinity resistance value when the data signal is lower in magnitude than the reference voltage.