Patent ID: 8043923
Filing Date: 2011-10-25
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, comprising: forming a gate electrode on a semiconductor substrate, the gate electrode having opposing side walls; forming an offset spacer layer on the side walls of the gate electrode and on an upper surface of the semiconductor substrate; forming spacers on the side walls of the offset spacer layer; doping impurities into the semiconductor substrate on opposing sides of the spacers to form highly doped impurity regions having a first concentration of doping impurities in the semiconductor substrate; selectively removing the spacers to expose portions of the semiconductor substrate between the highly doped impurity regions and the gate electrode; anisotropically etching the offset spacer layer to form an offset spacer; and forming lightly doped impurity regions in the exposed portions of the semiconductor substrate between the highly doped impurity regions and the gate electrode, the lightly doped impurity regions having a second concentration of impurities that is lower than the first concentration of impurities.