Patent ID: 6730969
Filing Date: 2004-05-04
Classification: H01L

Abstract:
A transistor formed in a semiconductor material of a first conductivity type, the semiconductor material having an upper surface and a dopant concentration, the transistor comprising:a first region of a second conductivity type formed in the semiconductor material, the first region having an upper surface; a second region of the second conductivity type formed in the semiconductor material a distance apart from the first region, the second region having an upper surface; a first channel region of the semiconductor material located between the first region and the second region, the first channel region having an upper surface; a third region of the second conductivity type formed in the semiconductor material a distance apart from the first region and the second region, the third region having an upper surface; a second channel region of the semiconductor material located between the second region and the third region, the second channel region having an upper surface, an active region being defined by the first region, the second region, the third region, the first channel region, and the second channel region, the active region having an upper surface; a fourth region of the second conductivity type formed in the semiconductor material a distance apart from the active region, the fourth region having an upper surface that surrounds the upper surface of the active region; a third channel region of the semiconductor material located between the fourth region and the active region; a gap region of the semiconductor material, the gap region having an upper surface, the upper surface of the gap region adjoining the upper surface of the fourth region; a field oxide region formed in the semiconductor material, the field oxide region surrounding the upper surface of the fourth region, being spaced apart from the fourth region, and adjoining the gap region; a first gate formed over the first channel region, the second channel region, and the third channel region, the first gate having an extension section; and a second gate formed over the gap region, the second gate having ends, the extension section of the first gate extending out between the ends of the second gate.