Patent ID: 6061823
Filing Date: 2000-05-09
Classification: H03M,H04L

Abstract:
An error correcting/decoding apparatus comprising:a demodulator for demodulating received data and also generating a soft-decision estimate according to the received data;a Viterbi decoder for decoding the demodulated received data to a bit sequence with the Viterbi algorithm according to the soft-decision estimate generated by said demodulator;a CRC means for checking the existence of any error by executing CRC on a bit sequence decoded by said Viterbi decoder and outputting the bit sequence, when no error is detected, as decoded data; anda bit inverter for executing bit inversion for said bit sequence, when any error is detected by said CRC means, and outputting the bit sequence having been subjected to bit inversion to said CRC means for the inverted bit sequence to be subjected to CRC.