Patent ID: 6233667
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A method for translating a virtual address into a physical address in a computer system, comprising:receiving the virtual address during an execution or a fetch of a program instruction;determining if the virtual address is in an upper portion or a lower portion of a virtual address space;if the virtual address is in the lower portion of the virtual address space,adding the virtual address to a first base address to produce the physical address, andcomparing the virtual address against an upper bound,if the virtual address has a larger value than the upper bound, indicating that the access is illegal; andif the virtual address is in the upper portion of the virtual address space,adding the virtual address to a second base address to produce the physical address, andcomparing the virtual address against a lower bound,if the virtual address has a lower value than the lower bound, indicating that the access is illegal,wherein the method is performed within a memory management unit that is integrated into a microprocessor chip.