Patent ID: 6337230
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:(a) preparing an SOI substrate having a multilayer structure with a semiconductor substrate, an insulating layer, and a semiconductor layer stacked in this order; (b) forming a first element isolation insulation film in an upper surface of said semiconductor layer to a predetermined depth that does not reach an upper surface of said insulating layer, in an element isolation region of said SOI substrate; (c) forming a gate insulation film on said upper surface of said semiconductor layer in an element forming region of said SOI substrate; (d) forming a gate electrode on said gate insulation film and said first element isolation insulation film; (e) forming an interlayer insulation film on said gate electrode and said first element isolation insulation film; (f) selectively forming a contact hole in an upper surface of said interlayer insulation film, extending through said first element isolation insulation film to said upper surface of said semiconductor layer, in said element isolation region of said SOI substrate, said contact hole being in contact with said gate electrode on said first element isolation insulation film; and (g) filling said contact hole with a conductor.