Patent ID: 7428283
Filing Date: 2008-09-23
Classification: H04L

Abstract:
1. A serial data receiver comprising: an input buffer for receiving and storing a serial data signal output from a transmitting end; a clock buffer for receiving and storing a reference clock signal output from the transmitting end; a clock generator for generating a plurality of overclock signals based on the reference clock signal; a data sampler for oversampling the received serial data based on the plurality of overclock signals; and a position detector for comparing values sampled by the respective overclock signals and outputting the most effective value as a data value that corresponds to the reference clock signal while considering a transition position of a data bit, wherein the position detector is performed in such a way that: in the case where values output from right and left overclocks of a current reference clock are identical with each other, an output value of the left or right overclock is output as an effective value if there is transition of the data bit between the left overclock and a previous reference clock, or between the right overclock and a next reference clock, and an output value of the current reference clock is output as an effective data value if there is no transition therebetween; and in the case where the values output from the right and left overclocks of the current reference clock are not identical with each other, an output value of the left overclock is output as an effective data value if there is transition of the data bit only between the left overclock and the left reference clock, an output value of the right overclock is output as an effective value if there is transition of the data bit only between the right overclock and the next reference clock, and the output value of the current reference clock is output as an effective value if there is no transition of the data bit.