Patent ID: 9063717
Filing Date: 2015-06-23
Classification: G06F,G06Q,H02J

Abstract:
1. A power supply apparatus comprising: a switching circuit configured to receive a drive signal and to output a switching signal on the basis of the drive signal; a first piezoelectric transformer and a second piezoelectric transformer each configured to receive the switching signal and to change an output in accordance with a frequency of the drive signal, wherein the first and second piezoelectric transformers have respective resonance frequencies that are different from each other; an output converter configured to detect the output and to output a feedback signal proportional to an output level; a drive-signal generator configured to receive an N-bit division ratio, to divide a reference clock based on the received N-bit division ratio, and to output the drive signal with an average cycle proportional to the N-bit division ratio; a comparator configured to compare a target data value of a predetermined bit width with a feedback data value of the predetermined bit width obtained by an analog-to-digital conversion of the feedback signal, and to output a comparative output in accordance with a result of the comparison; a selector configured to output a selection signal indicating which one of the first and second piezoelectric transformers is selected to be controlled; a data memory configured to hold preset data in each address, wherein the data memory is configured to store preset data for the first and second piezoelectric transformers at first and second addresses, respectively; an arithmetic unit configured to update successively the N-bit division ratio at every step whose processing timing is managed by a timer, by adding or subtracting the preset data read from the data memory to or from the N-bit division ratio in accordance with the comparative output; and at least two systems each including the switching circuit, the first and second piezoelectric transformers, the output converter, the drive-signal generator, the comparator, and the arithmetic unit, wherein the arithmetic unit is configured to perform an arithmetic operation to make the feedback data value approach the target data value by a negative feedback control, the arithmetic operation using, as the preset data, data read from an address specified by data with a predetermined bit width of M, with M<N, extracted from the successively updated N-bit division ratio, wherein the arithmetic unit is configured, when the first piezoelectric transformer is selected to be controlled, to read the preset data from the first address in the data memory and to perform an arithmetic operation, and configured, when the second piezoelectric transformer is selected to be controlled, to read the preset data from the second address in the data memory different from the first address and to perform an arithmetic operation, wherein the data memory is a single data memory configured to be shared by the at least two systems, and wherein the at least two systems are configured to alternatively act with sharing the single data memory at the processing timings created by the timer repeatedly and successively from one system to another.