Patent ID: 6406964
Filing Date: 2002-06-18
Classification: H01L

Abstract:
A method, comprising:providing a substrate, said substrate being doped with a first type of dopant material; forming a transistor above said substrate in an active area of said substrate as defined by an isolation structure, said transistor comprised of a gate electrode; performing a source/drain extension implant process at an angle that is approximately perpendicular to a surface of said substrate, said source/drain extension implant process being performed with a dopant material that is of an opposite type to said first type of dopant material; performing a source/drain implant process at an angle that is approximately perpendicular to a surface of said substrate, said source/drain implant process being performed with a dopant material that is of an opposite type to said first type of dopant material; performing at least two angled ion implant processes on said transistor with a dopant material that is of an opposite type to said first type of dopant material; and performing at least one anneal process.