Patent ID: 7864592
Filing Date: 2011-01-04
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array which includes blocks, each block having a NAND string which includes memory cells connected in series; and a control circuit including decoders which select one of the blocks, the decoders corresponding to the blocks respectively; wherein each of the decoders is comprised of a FET string which includes FETs connected in series; a first FET which is connected between a first end of the FET string and a first power supply terminal; a second FET which is connected between a second end of the FET string and a second power supply terminal; a third FET which is connected between the second end of the FET string and the second power supply terminal; and an inverter which is connected between the second end of the FET string and a gate electrode of the third FET, wherein a row address signal inputs to gate electrodes of the FETs of the FET string, and wherein the row address signal inputs to the gate electrodes of the FETs after turning the second FET on, and before turning the first FET on and turning the second FET off.