Patent ID: 8150648
Filing Date: 2012-04-03
Classification: G01R

Abstract:
1. A timing generator adapted to receive test pattern data to be supplied to a device under test and rate data for setting the period of the test pattern data, and control the timing of outputting the test pattern data to the device under test according to the rate data, comprising: a delay setting data generator operative to receive the rate data and generate delay setting data; and a variable delay circuit operative to delay the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay, wherein the rate data comprises first rate data designating the period of the test pattern data with a precision determined by the unit amount of delay and second rate data designating the period of the test pattern data with a precision higher than that determined by the unit amount of delay, and the delay setting data generator is operative to output a first value and a second value in a time division manner at a ratio determined by the second rate data, the first value being determined by the first rate data and the second value being determined by the first rate data and different from the first value, wherein, the delay setting data generator further comprises an integrator operable to integrate the first rate data at intervals defined by a first clock, given that division of the data output from the integrator by a reference value determined by the period of the first clock produces a quotient α and a remainder β, where α and β denote integers, the delay setting data generator sets the first value and the second value to values determined by the remainder β, and the timing generator delays the test pattern data by a total of α periods of the first clock.