Patent ID: 7556984
Filing Date: 2009-07-07
Classification: H01L

Abstract:
1. A package method for a chip, comprising steps in an order of: providing a substrate with at least one adhesive layer and at least one conductive layer subsequently thereon; forming a patterned layer on the conductive layer and a film on a bottom surface of the substrate; filling at least one metal layer into the patterned layer; removing the patterned layer and the film; removing portions of the conductive layer and the adhesive layer to form a plurality of trenches through the conductive layer and the adhesive layer on the substrate, wherein the trenches divide the metal layer into a plurality of chip supporters and conductive nodes isolated from each another; forming at least one chip on each of the chip supporter, a plurality of chips electrically coupled to the conductive nodes, respectively; forming a molding compound on the substrate to encapsulate the conductive layer, the metal layer and the chips; removing the substrate; and dicing with each of chip or chipset as a unit to form a plurality of package structures of the chip.