Patent ID: 7917568
Filing Date: 2011-03-29
Classification: G06F

Abstract:
1. An x86 architecture microprocessor having an x87 floating-point unit (FPU) with an x87 register stack, comprising: an instruction decoder, configured to decode an x87 fused multiply-add (FMA) instruction of the microprocessor instruction set, wherein said FMA instruction implicitly specifies first and second operands as stored in first and second registers of the register stack, said first and second registers being the top two registers of the register stack, and a third operand, explicitly specified in the instruction as stored in a third register of the register stack; a multiplier, coupled to the register stack, configured to multiply said first and second operands to generate a product, in response to said FMA instruction; and an adder, coupled to said multiplier, configured to add said third operand to said product to generate a result, in response to said FMA instruction.