Patent ID: 6975025
Filing Date: 2005-12-13
Classification: H01L

Abstract:
1. A semiconductor chip package, comprising: a lower structure having an upper surface; a wall extending from the lower structure upper surface to define a cavity within the wall, the cavity having a contact area on the upper surface of the lower structure, the wall including a first insulating layer on the lower structure upper surface, a metal layer on the first insulating layer, and a second insulating layer on the metal layer; a plurality of electrical conductors extending from the contact area to contact points elsewhere in the semiconductor chip package; a first semiconductor chip positioned on the contact area, the first semiconductor chip including a plurality of components and having a perimeter surface and a lower surface, the lower surface having a plurality of electrical contacts thereon connecting to the components, the first semiconductor chip being positioned within the cavity with an isolation area therearound between the perimeter surface and the wall and with individual ones of the electrical contacts coupled to respective ones of the plurality of electrical conductors; and an electrically non-conducting underfill material within the isolation area to enclose and isolate the cavity contact area.