Patent ID: 6490207
Filing Date: 2002-12-03
Classification: G11C,H03K,H03L

Abstract:
A variable delay circuit for a delay-locked loop, comprising:an input terminal; an output terminal; a first buffer having a first input coupled to the input terminal and a first buffer output; a first capacitor; a second capacitor; a precharge circuit coupled to the first and second capacitors, the precharge circuit being operable to preset the charge of the first and second capacitors, and a first isolation switch coupled between the first buffer output and the first capacitor and between the first buffer output and the second capacitor, the first isolation switch having a first switching input and being responsive to a selection signal at the first switching input to selectively couple the first buffer output to the first capacitor to change the voltage on the first capacitor by altering the charge of the first capacitor and to selectively couple the first buffer output to the second capacitor to change the voltage on the second capacitor by altering the charge of the second capacitor; and a second buffer having a second buffer input coupled to the first buffer output and a second buffer output coupled to the output terminal, the second buffer switching state when the voltage applied to the second buffer input reaches a first predetermined value responsive to the voltage on each capacitor coupled through the first isolation switch changing to a second predetermined value.