Patent ID: 6232793
Filing Date: 2001-05-15
Classification: H01L,H03K

Abstract:
A semiconductor device comprising:a first power line;a primary second power line;a secondary second power line;a logic circuit receiving potentials from said first power line and said secondary second power line used for two logic levels of an output signal, the logic circuit including(i) a first nMOS-FET coupled to said secondary second power line and (ii) a second nMOS-FET coupled to a gate of said first nMOS-FET, said second nMOS-FET having a backgate connected to said primary second power line;a first FET coupled between said primary second power line and said secondary second power line, having a backgate receiving a potential at most the potential of said secondary second power line in a standby state, and rendered nonconductive in the standby state; anda bias switching circuit applying a bias potential to a backgate of the first nMOS-FET, the bias potential in an active state being higher than the bias potential in the standby state.