Patent ID: 7449763
Filing Date: 2008-11-11
Classification: H01L,Y10S

Abstract:
1. A cell of a nonvolatile memory device, comprising: a plurality of trench isolation layers in parallel with each other on a predetermined region of a semiconductor substrate and defining a plurality of active regions; the trench isolation layer having sidewalls that project over the semiconductor substrate; and a tunnel oxide layer, a floating gate and a gate interlayer dielectric layer that are sequentially stacked between the trench isolation layers, wherein the gate interlayer dielectric layer includes at least one high k-dielectric layer whose dielectric constant is higher than that of a silicon nitride layer, wherein the tunnel oxide layer, the floating gate and the gate interlayer dielectric layer have sidewalls that are self-aligned to the adjacent trench isolation layers, and wherein the self-aligned sidewall of the gate interlayer dielectric layer connects an uppermost surface of the gate interlayer dielectric layer with a lowermost surface of the gate interlayer dielectric layer.