Patent ID: 6368947
Filing Date: 2002-04-09
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit, comprising:forming at least a portion of a gate structure including a polysilicon gate conductor and a cap layer, the gate structure being disposed on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous region near the top surface of the substrate; first doping the substrate for drain and source extensions; providing oxide spacers, the spacers abutting the gate conductor; providing a second amorphization implant, the second amorphization implant creating a deep, second amorphous region in the substrate; second doping the substrate to form deep source and drain regions; removing the cap layer to expose the polysilicon gate conductor; and thermally annealing the substrate to melt the first amorphous region, the second amorphous region and a portion of the gate conductor.