Patent ID: 7176074
Filing Date: 2007-02-13
Classification: H01L,Y10S

Abstract:
1. A manufacturing method of thin film transistor array substrate, comprising: providing a substrate, a plurality of first poly-silicon islands, a plurality of second poly-silicon islands, a plurality of third poly-silicon islands, a gate insulating layer, a plurality of first gates, a plurality of second gates, a plurality of third gates, and a first passivation layer having been formed on the substrate, wherein the substrate has a peripheral region and an array region, the first poly-silicon islands and the second poly-silicon islands are disposed on the peripheral region, and the third poly-silicon islands are disposed on the array region, the gate insulating layer covers the first poly-silicon islands, the second poly-silicon islands, and the third poly-silicon islands, the first gates, the second gates, and the third gates are respectively disposed on the gate insulating layer over the first poly-silicon islands, the second poly-silicon islands, and the third poly-silicon islands, the first passivation layer covers the first gates, the second gates, and the third gates, and a second source/drain has been formed in each of the second poly-silicon islands, a third source/drain has been formed in each of the third poly-silicon islands, the second poly-silicon islands and the third poly-silicon islands have been implanted with ions; forming a third patterned photoresist layer on the first passivation layer by using a third half-tone mask, wherein the third patterned photoresist layer exposes portions of the first passivation layer on the first poly-silicon islands; performing a first ion implantation process with the third patterned photoresist layer as mask to form a first source/drain in each of the first poly-silicon islands, wherein a first channel region is between the first source/drain; removing a portion of the thickness of the third patterned photoresist layer to expose portions of the first passivation layer on the second poly-silicon islands and the third poly-silicon islands; removing portions of the first passivation layer and the gate insulating layer with the third patterned photoresist layer as mask to expose portions of each of the first sources/drains, portions of each of the second sources/drains, and portions of each of the third sources/drains and to form a first patterned passivation layer; removing the third patterned photoresist layer; forming a plurality of first source/drain conductive layers, a plurality of second source/drain conductive layers, and a plurality of third source/drain conductive layers on the first patterned passivation layer, wherein the first source/drain conductive layers are electrically connected to the first sources/drains respectively, the second source/drain conductive layers are electrically connected to the second sources/drains respectively, and the third source/drain conductive layers are electrically connected to the third sources/drains respectively; forming a second patterned passivation layer on the first patterned passivation layer, wherein the second patterned passivation layer exposes portions of each of the third source/drain conductive layers; and forming a plurality of pixel electrodes on the second patterned passivation layer, wherein each of the pixel electrodes is electrically connected to the corresponding third source/drain conductive layers.