Patent ID: 7221726
Filing Date: 2007-05-22
Classification: H03L

Abstract:
1. An arrangement for generating a decoder clock signal for decoding a data signal which is available together with a clock signal and a data word signal signalizing data words, both of which signals may each have different frequencies, the arrangement comprising: a phase control circuit which receives the clock signal and supplies the decoder clock signal from its output, and which comprises at least one adjustable divider which is preferably arranged at the input of the phase control circuit and whose division ratio is adjustable, and a detector which determines at least the ratio between the frequency of the clock signal and the frequency of the data word signal and adjusts, in dependence upon this frequency ratio, the division ratio in the adjustable divider in such a way that the frequency of the decoder clock signal has a fixed, predetermined frequency ratio with respect to the frequency of the data word signal in the case of all possibly occurring frequency ratios between the clock signal and the data word signal.