Patent ID: 7479450
Filing Date: 2009-01-20
Classification: H01L

Abstract:
1. A method for fabricating a chip, comprising: providing a silicon substrate, an ESD circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said ESD circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said first internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a third interconnecting structure over said silicon substrate, wherein said ESD circuit is connected to said first internal circuit though, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.