Patent ID: 8416599
Filing Date: 2013-04-09
Classification: H01L

Abstract:
1. A method of fabricating a Metal Oxide Semiconductor (MOS) Field Effect Transistor having a trench isolation region comprising: forming the trench isolation region in a predetermined portion of a semiconductor substrate to define an active region; forming a first insulating layer pattern that covers at least a boundary of the trench isolation region and the active region and exposes a portion of the active region including a channel region of the transistor; forming a second insulating layer on at least a portion of the first insulating layer pattern and the exposed portion of the active region including the channel region; and forming a gate electrode on at least substantially an entire surface of the semiconductor substrate where the second insulating layer and the first insulating layer pattern have been formed and wherein the gate electrode crosses over the boundary of the trench isolation region and the active region.