Patent ID: 9098300
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. An apparatus comprising: a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the platform independent code to be executed regardless of characteristics of a platform including a processor of the processor manufacturer, the SIC including an embedded processor logic to initialize the processor and at least one communication link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of an original equipment manufacturer (OEM), wherein the SIC is included in the non-volatile storage, the non-volatile storage including OEM basic input/output system (BIOS), the OEM BIOS dependent on the characteristics of the platform, and a plurality of SIC versions, each associated with a corresponding SIC data module, wherein an initial program loader (IPL) is to select one of the plurality of SIC versions and SIC data modules to launch.