Patent ID: 6635535
Filing Date: 2003-10-21
Classification: H01L

Abstract:
A method for manufacturing a power semiconductor device comprising the steps of:forming a gate trench mask with open and closed regions on the surface of a semiconductor substrate; removing semiconductor material from areas exposed by the open regions of the trench mask to form a plurality of gate trenches and leaving at least a portion of the gate mask on the surface adjacent the trench openings for protecting potential source regions; forming a gate oxide layer on the sidewalls of the trenches; depositing a layer of semiconductor material on the substrate, over the residual gate mask and in the trenches; removing the deposited semiconductor material from the surface of the semiconductor substrate and the residual gate mask and leaving enough semiconductor material in the trenches to substantially fill the trenches; with the gate trench mask in place, implanting the substrate and the semiconductor material in the trenches with dopants to form highly doped source regions and conductive gate electrodes; removing gate trench mask to expose the surface of the semiconductor substrate and to recess the level of semiconductor material in the trenches; depositing a metal layer over the substrate; reacting the metal layer with the substrate to form a thin layer of silicide on source regions and the surface of the gate electrodes in the trenches; depositing a layer of insulating material on the substrate; forming vias in the deposited layer of insulating material where the vias expose only portions of the silicided source regions and only portions of the silicided gate electrodes; and depositing a conductive layer over the surface of the substrate and in the vias to form electrical contacts to the silicided sources and gates.