Patent ID: 8697567
Filing Date: 2014-04-15
Classification: H01L

Abstract:
1. A method for implementing decoupling capacitors within a DRAM TSV stack comprising: providing first and second semiconductor chips, each including a DRAM formed with a plurality of TSVs extending through the DRAM and filled with a conducting material; depositing a first glass layer providing an insulator disposed on a top of the DRAM and a second glass layer providing an insulator disposed on a bottom of the DRAM; depositing a first metal layer providing a conductor disposed on said first glass layer and a second metal layer providing a conductor disposed on said second glass layer; etching an opening in said first and second metal layers and said first and second glass layers through to respective TSVs; providing a respective solder ball on respective TSVs to connect said first and second semiconductor chips in the DRAM TSV stack; respectively connecting said first and second metal layers to at least one said TSV by one said respective solder ball and connecting said first and second metal layers to a voltage source; and inserting a dielectric disposed between said first and second metal layers in the DRAM TSV stack to complete the decoupling capacitor.