Patent ID: 6818474
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method for manufacturing a stacked chip package comprising the steps of:attaching a first substrate having a first center window on a first semiconductor chip having a first backside and a first front side having first bonding pads arranged on the center part, wherein the first bonding pads substantially corresponds with the first center window; forming a first bonding wires connecting the first bonding pads of the first semiconductor chip and the first substrate; attaching a second substrate having a second center window on a second semiconductor chip having a second backside and a second front side having second bonding pads arranged on the center part, wherein the second bonding pads substantially corresponds with the second center window; forming a second bonding wires connecting the second bonding pads of the second semiconductor chip and the second substrate; attaching the first backside directly on the second backside; forming a third bonding wire connecting the first and the second substrates; forming a molding body overlaying the first, the second and the third bonding wires; and adhering a conductive ball to the first substrate.