Patent ID: 6938132
Filing Date: 2005-08-30
Classification: G06F

Abstract:
1. A co-processor for interfacing a microcontroller to an external memory, the co-processor comprising: a first bus, coupled to the microcontroller, for carrying from the microcontroller to the co-processor, a command identifying at least an instruction to change data in the external memory, an address of the data in the external memory, and an identifier of a task that issues the instruction, the first bus comprising an instruction bus for carrying the instruction, an address bus for carrying the address, and a task identifier bus for carrying the identifier; an execution unit comprising an arithmetic logic unit, the execution unit being coupled to the first bus through the command buffer, wherein the execution unit performs a sequence of acts in an atomic manner to execute at least the instruction identified in the command, and wherein the sequence of acts includes decoding at least the instruction; a command buffer, coupled to the first bus, to hold the command temporarily if the execution unit is processing a previous command; a second bus, coupled to the external memory, for transmitting to the external memory, the address and the data to be stored at the address in the external memory; an address-data buffer coupled to the execution unit and capable of locally storing changed data obtained from the arithmetic logic unit by execution of said instruction from the first bus; wherein the address-data buffer includes a number of storage elements greater than or equal to the number of clock cycles of latency of the external memory; a third bus, coupled to the external memory, for receiving from the external memory, the address and the data held at the address in the external memory; a comparator coupled to each of the third bus and the address-data buffer to generate a select signal indicative of a most current version of the data; a multiplexer coupled to each of the third bus and the address-data buffer, to selectively pass to the arithmetic logic unit the most current version of the data, in response to the select signal from the comparator; and a fourth bus, coupled to the microcontroller, for carrying to the microcontroller from the co-processor, the identifier of the task and said changed data.