Patent ID: 8518828
Filing Date: 2013-08-27
Classification: H01L

Abstract:
1. A semiconductor device fabrication method comprising steps of: stacking a first layer, a second layer, a third layer, and a fourth layer in this order on a substrate; processing the fourth layer into a first mask layer having a first pattern of stripes extending in a first direction; processing the third layer using the first mask layer into a first sacrifice layer having the first pattern; forming a fifth layer to cover at least the first sacrifice layer; thinning the fifth layer so that the fifth layer remains on side walls of the first sacrifice layer; removing the first sacrifice layer to form a first side wall layer having a second pattern of stripes extending in the first direction; processing the second layer using the first side wall layer into a second mask layer having the second pattern; forming a sixth layer by a coating process using a liquid source in a liquid state thereby to bury the second mask layer, the sixth layer having a substantially flat upper surface; forming a seventh layer directly on the sixth layer; processing the seventh layer into a third mask layer having a third pattern of stripes extending in a second direction intersecting the first direction; processing the sixth layer using the third mask layer into a second sacrifice layer having the third pattern; forming an eighth layer to cover at least the second sacrifice layer; thinning the eighth layer so that the eighth layer remains on side walls of the second sacrifice layer; completely removing the entire second sacrifice layer to form a second side wall layer having a fourth pattern of stripes extending in the second direction; and processing the second mask layer using the second side wall layer into a fourth mask layer having dots arrayed in the first and the second directions.