Patent ID: 6770931
Filing Date: 2004-08-03
Classification: H01L

Abstract:
A nonvolatile semiconductor memory device comprising:a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower stages; a first insulating film formed on the semiconductor substrate so as to cover up the stepped portion; a floating gate electrode formed on the first insulating film so as to cover up the stepped portion; a control gate electrode formed on the floating gate electrode with the second insulating film interposed therebetween, the control gate electrode being capacitively coupled to the floating gate electrode; a source region formed in an area of the first surface region opposite to the stepped portion relative to the floating gate electrode; a drain region formed in an area of the second surface region underlying the floating gate electrode; and a depletion control layer formed in the semiconductor substrate to extend from a position located under the first surface region and at a distance from an upper corner of the stepped portion toward a lower corner of the stepped portion and adjoining the drain region without reaching the step side region and the first surface region, the depletion control layer being composed of a heavily doped impurity region of a conductivity type opposite to a conductivity type of the drain region.