Patent ID: 9204532
Filing Date: 2015-12-01
Classification: G02F,H05K

Abstract:
1. A fanout line structure of an array substrate, comprising: first fanout lines arranged on a fanout area of the array substrate; and second fanout lines arranged on the fanout area of the array substrate; wherein a second conducting film is arranged at a bottom of the second fanout line, a second capacitor is formed between the second conducting film and a first conducting film of the second fanout line; capacitance value of the second capacitor is dependent on an overlapping area between the second conducting film and the first conducting film; wherein width of the second conducting film is constant, and length of each of the second conducting films arranged at the bottom of different lengths of second fanout lines is different; wherein the length of the second conducting film arranged at the bottom of the second fanout line is L wherein L