Patent ID: 8377755
Filing Date: 2013-02-19
Classification: H01L

Abstract:
1. A method for manufacturing a SOI high voltage power chip, having a high voltage power device and a number of low voltage devices, the method comprises: (a) providing a SOI substrate having a bottom layer, a top silicon layer, and a buried oxide layer in between; (b) forming a cave and trenches simultaneously in the top silicon layer of the SOI substrate; (c) filling oxide in the cave; (d) forming isolation regions near the high voltage power device by oxidizing the full surfaces of the trenches, filling oxide in the oxidized trenches, and forming oxide isolation regions to separate low voltage devices at the same time; (e) forming drain regions, source regions, gate regions for the high voltage power device, and the number of low voltage devices by processes including doping, implantation, or depositing; (f) depositing an oxide layer overlapping the SOI substrate which comprises the drain regions, the source regions, and the gate regions; and (g) forming metal structures respectively connecting to the drain regions, source regions, and gate regions.