Patent ID: 7763945
Filing Date: 2010-07-27
Classification: H01L

Abstract:
1. A semiconductor device pair comprising: a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric and a lowermost interfacial layer formed between the high-K gate dielectric and the semiconductor substrate, wherein the lowermost interfacial layer physically contacts the semiconductor substrate and the high-K gate dielectric; and a plurality of oxygen-free offset spacer portions adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer physically contacting the either side of the respective first and second gate structures, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.