Patent ID: 8173505
Filing Date: 2012-05-08
Classification: B82Y,H01L

Abstract:
1. A method for forming a semiconductor structure, the method comprising: forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer of gate material; forming an opening through the hard mask layer and the first layer of gate material; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer, wherein a thickness of the second layer of gate material is at least as great as a total thickness of the first layer of gate material and the hard mask layer; removing a portion of the second layer of gate material and a portion of the charge storage layer which overlie the hard mask layer, wherein the removing uses the hard mask layer as a stopping layer, and wherein a second portion of the second layer of gate material remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion of the second layer of gate material within the opening, wherein the patterned masking layer defines a first bitcell, a second bitcell, and a gate of a logic transistor; forming the first bitcell and the second bitcell using the patterned masking layer, wherein each of the first bitcell and the second bitcell comprises a select gate made from the first layer of gate material and a control gate made from the second layer of gate material; and forming the gate of the logic transistor using the patterned masking layer, wherein the gate of the logic transistor is made from the first layer of gate material.