Patent ID: 8399953
Filing Date: 2013-03-19
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an element isolation insulating film dividing an upper layer portion of the semiconductor substrate into a plurality of first active regions; a first source layer and a first drain layer being of a second conductivity type and formed spaced with respect to each other in an upper portion of each of the plurality of the first active regions; a first gate electrode provided in a region directly above a first channel region in the semiconductor substrate located between the first source layer and the first drain layer; a first gate insulating film provided between the semiconductor substrate and the first gate electrode; a first punch-through stopper layer of the first conductivity type formed in a region of the first active region directly below the first source layer; a second punch-through stopper layer of the first conductivity type formed in a region of the first active region directly below the first drain layer; a well of the first conductivity type formed in an upper layer portion of the semiconductor substrate, an upper layer portion of the well being divided into a plurality of second active regions by the element isolation insulating film; a second source layer and a second drain layer being formed spaced with respect to each other in an upper portion of each of the plurality of second active regions; a second gate electrode provided in a region directly above a second channel region in the semiconductor substrate located between the second source layer and the second drain layer; and a second gate insulating film provided between the semiconductor substrate and the second gate electrode, the first punch-through stopper layer and the second punch-through stopper layer each having an effective impurity concentration higher than the semiconductor substrate, the first punch-through stopper layer and the first source layer being separated in the first channel region, the second punch-through stopper layer and the first drain layer being separated in the first channel region, a first transistor including the first source layer, the first drain layer, the first gate insulating film, and the first gate electrode being formed in each of the first active regions, a second transistor including the second source layer, the second drain layer, the second gate insulating film, and the second gate electrode being formed in each of the second active regions, a width of the second gate electrode of the second transistor being smaller than a width of the first gate electrode of the first transistor, the second gate insulating film of the second transistor being thinner than the first gate insulating film of the first transistor, and a concentration of the first conductivity type impurity in the second active regions below the second source layer and second drain layer being lower than that of the first source layer and the first drain layer in the first active regions at the same position as the first and second punch-through stopper layers.