Patent ID: 6812518
Filing Date: 2004-11-02
Classification: H01L

Abstract:
A transistor comprising:a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other; a first insulation layer formed on a top of the projection; a pair of source/drain regions formed on a surface of said semiconductor substrate at both sides of the projection; second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall; a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and said source/drain regions via respective second insulation layers; third insulation layers each being formed on one of said floating gates; and a control gate facing said pair of floating gates via said third insulation layers and facing the top of the projection via said first insulation layer; the projection having a root portion formed to virtually connect said source/drain regions with a straight line, the root portion being higher in concentration of the one conductivity type of impurity than a remaining portion of the projection.