Patent ID: 6569718
Filing Date: 2003-05-27
Classification: H01L

Abstract:
A method of producing a top gate thin-film transistor, comprising the steps of:forming an amorphous silicon layer (12) over an insulating substrate (2); forming an insulated gate structure (14) over the amorphous silicon layer having gate insulator layers (14a, 14b, 14c) and an upper gate conductor (16) directly over the gate insulator layers, the gate conductor being patterned to be narrower than a spacing to be provided between source and drain electrode contacts (6, 8) to the amorphous silicon layer; laser annealing areas of the amorphous silicon layer not shielded by the gate conductor, through all of the gate insulator layers, to form polysilicon portions, wherein the gate insulator layers are formed as first and second gate insulator layers (14a, 14b) of first refractive index, and a third insulator layer (14c) of second, lower, refractive index overlying both said first and second gate insulator layers (14a, 14b) and in contact with said second insulator layer (14b).