Patent ID: 6617907
Filing Date: 2003-09-09
Classification: G11C,H03K

Abstract:
A voltage translator supplying either an operation voltage from an operation voltage source or a low voltage from a low voltage source to a word line, in response to a decode signal, comprising:an inverter generating a logical selection signal based on said decode signal; a first NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with said word line, and a gate electrode connected with the output terminal of said inverter; a first PMOS type transistor including a source electrode connected with said operation voltage source, and a drain electrode connected with said word line; a second PMOS type transistor including a source electrode connected with the operation voltage source, and a drain electrode connected with the gate of said first PMOS type transistor; a second NMOS type transistor including the source electrode connected with the gate electrode of said second PMOS type transistor, a drain electrode connected with said operation voltage source, and a gate electrode connected with said word line; a third PMOS type transistor including a source electrode connected with the gate electrode of said second PMOS type transistor and also with the source electrode of said third NMOS transistor, a drain electrode connected with said word line, and a gate electrode connected with the gate electrode of said first PMOS type transistor; and a third NMOS type transistor including a source electrode connected with said low voltage source, a drain electrode connected with the gate electrode of said second PMOS type transistor, and a gate electrode connected with the output terminal of said inverter.