Patent ID: 6747904
Filing Date: 2004-06-08
Classification: G11C

Abstract:
A leakage control circuit for a random access memory having word line drivers, bit lines, word lines, and memory cells, wherein the word line drivers are coupled to a second voltage, have inputs for receiving a control signal, and have outputs coupled to corresponding word lines, the memory cells have storage capacitors and MOS transistors, and the gates of the MOS transistors are coupled to corresponding word lines, the leakage control circuit comprising:a differential amplifier having a first input, a second input, and an output, wherein the first input receives a first reference voltage, and the second input receives a second reference voltage; a first divider receiving a first voltage to generating the first reference voltage; a second divider receiving a first voltage to generating the second reference voltage; MOS transistors having drains, gates, and sources, wherein drains of the MOS transistors are coupled to the first input of the differential amplifier, and the MOS transistors are fabricated by the same process as the MOS transistors in the memory cells; and a charge pump having an enable terminal and an output, wherein the enable terminal of the charge pump is coupled to the output of the differential amplifier, and the output of the charge pump generates the second voltage and is coupled to the gates of the MOS transistors.