Patent ID: 7176051
Filing Date: 2007-02-13
Classification: H01L

Abstract:
1. A method of reducing charging damage to integrated circuits during semiconductor manufacturing, comprising: providing a semiconductor substrate comprising thereon a number of integrated circuit dies, said integrated circuit dies being separated from each other by scribe lanes surrounding each said integrated circuit die, wherein each said integrated circuit die comprises thereon at least a first device region, a second device region and a trench isolation dummy region; forming a first implant mask over said semiconductor wafer, said first implant mask covering said second device region and said trench isolation dummy region, while exposing said semiconductor substrate within said first device region; implanting dopant species into exposed semiconductor substrate within said first device region to form first doping regions therein; stripping said first implant mask; forming a second implant mask over said semiconductor wafer, said second implant mask covering said first device region, while exposing said semiconductor substrate within said second device region and a plurality of trench dummy features of said trench isolation dummy region; and implanting dopant species into exposed said semiconductor substrate within said second device region to form second doping regions therein.