Patent ID: 6127264
Filing Date: 2000-10-03
Classification: H01L,Y10S

Abstract:
A method for forming a multilevel interconnect structure, comprising:providing a semiconductor topography;depositing a dielectric upon said topography;removing portions of said dielectric to said topography to form at least one trench spaced from at least one via;depositing a plug material across said dielectric and into said trench and said via;removing said plug material from an upper surface of said dielectric to form a lower portion of a first interconnect line within said trench and a contact within said via;depositing a conductive material across the upper surface of said dielectric and across said lower portion and said contact; andselectively removing said conductive material to form an upper portion of the first interconnect line that is substantially collinear with said lower portion and to form a second interconnect line over said contact.