Patent ID: 6159821
Filing Date: 2000-12-12
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit device comprising:providing a pad oxide layer over the surface of a silicon semiconductor substrate;depositing a sacrificial oxide layer overlying said pad oxide layer;depositing a nitride layer overlying said sacrificial oxide layer;etching a plurality of isolation trenches through said nitride, sacrificial oxide, and said pad oxide layers into said semiconductor substrate;depositing an oxide layer over said nitride layer and within said isolation trenches;polishing away said oxide layer wherein said substrate is planarized;etching back said nitride and oxide layers using an etching recipe that has a lower etching rate for said silicon substrate as compared with the etching rate of said nitride and oxide layers, and has a higher etching rate for the said nitride layer as compared with the said oxide layer whereby said nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and whereby the corners of said trench isolation areas are rounded; andcompleting the fabrication of said integrated circuit device.