Patent ID: 7872934
Filing Date: 2011-01-18
Classification: G11C

Abstract:
1. A semiconductor device comprising: a memory circuit including a memory cell array in which a plurality of memory cells into which “0” and “1” of binary data can be written are arranged; a first writing circuit which writes one of “0” and “1” of binary data into one of the plurality of memory cells included in the memory circuit; a second writing circuit which writes the other of “0” and “1” of binary data into one of the plurality of memory cells included in the memory circuit; and a reading circuit which reads binary data which is written into one of the plurality of memory cells included in the memory circuit, wherein each of the plurality of memory cells has an antifuse in one state selected from “a first state” which is an initial state, “a second state” which is obtained by applying a first voltage to the antifuse in “the first state” by the first writing circuit, or “a third state” which is obtained by applying a second voltage to an antifuse in “the first state” by the second writing circuit; wherein “the second state” or “the third state” of the antifuse corresponds to “0” or “1” of binary data; wherein a direction of applying the first voltage to the antifuse is different from a direction of applying the second voltage to the antifuse; wherein a state of the antifuse in “the second state” is not changed to “the third state” or “the first state”; and wherein a state of the antifuse in “the third state” is not changed to “the second state” or “the first state”.