Patent ID: 7859897
Filing Date: 2010-12-28
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor layer; a source layer and a drain layer within the semiconductor layer; an electrically floating body region provided between the source layer and the drain layer in the semiconductor layer and accumulating or releasing electric charges to store logical data; a first gate dielectric film provided on a first surface of the body region; a first gate electrode provided on the first surface via the first gate dielectric film; a second gate dielectric film provided on a second surface of the body region different from the first surface; a second gate electrode provided on the second surface via the second gate dielectric film; a driver applying a potential to the source layer; and a sense amplifier reading or writing the logical data from or in a memory cell including the source layer, drain layer, and body region, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source layer and the drain layer and lower than the other of the potentials of the source layer and the drain layer so that electric charges flow in the body region, and a potential of the second gate electrode is set to be higher as an absolute value than those of potentials of the source layer, drain layer, and first gate electrode so that electric charges flow from the body region, and in the data holding state, the memory cell is kept in a stationary state that a first amount of the electric charges flowing in the body region per unit time is substantially the same as a second amount of the electric charges flowing from the body region per unit time.