Patent ID: 9063902
Filing Date: 2015-06-23
Classification: G06F,G11C

Abstract:
1. A method for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system comprising: selectively providing a data register used for the DRAM repair in a selected one of a plurality of DRAM modules of system DRAM, a memory controller, and a memory buffer coupled between the plurality of DRAM modules and the memory controller; configuring said data register to map to any address, responsive to a configured address being detected, performing writes to or reads from the data register for the configured address; performing writes to the data register includes receiving a write request, a write address, and write data, sending the write address and write data to the system DRAM, and comparing a write address with a valid address of the data register, and responsive to a matching valid address and write address, setting a match signal, and writing data and Error Correcting Code (ECC) to the data register; and sending reads to both the DRAM modules of system DRAM and said data register and returning data from said data register responsive to a read address matching a valid address in said data register simultaneously with returning data from DRAM modules of system DRAM to preserve timings.