Patent ID: 6757761
Filing Date: 2004-06-29
Classification: G06F,G06T

Abstract:
A multi-processor system for signal processing comprising:a plurality of processor cores, each processor core having a local processor, at least two shareable local memory banks, a communications bus interface, and a set of buffers disposed between said local processor, communications bus, and local memory banks which provides a cacheless data path between said local memory banks and said communications bus and said local processor; a plurality of point-to-point communication busses disposed between each of said communications bus interfaces in pairs such that each processor core may directly access at least one bank of local memory for another processor core; and control logic associated with said local memory banks for controlling said sets of buffers such that, at any given time and selectable under software control by one or more of said processors, each local processor is provided uncontended and unarbitrated access to at least one local memory bank within its processor core while uncontended and unarbitrated access to another local memory bank is allowed by another processor of another processor core via one of said point-to-point communication busses, thereby preventing simultaneous attempts by a local processor to access the same memory bank as a processor from another processor core and avoiding contention and arbitration delays in accessing data in said memory banks.