Patent ID: 8373636
Filing Date: 2013-02-12
Classification: G02F,G09G,H05K

Abstract:
1. A liquid crystal display device comprising: a liquid crystal panel assembled by bonding one of substrates having pixels each being arranged at an intersection between each of a plurality of drain lines and each of a plurality of gate lines intersecting said drain lines, to the other of said substrates having color filters; a plurality of drain drivers directly mounted to a periphery of said one substrate in an extending direction of said gate lines, for applying gray scale voltage signals to said pixels so arranged as to correspond to predetermined groups of said plurality of drain lines on the basis of display data signals; a plurality of gate drivers directly mounted to a periphery of said one substrate in an extending direction of said drain lines, for applying scanning voltage signals to said pixels arranged along said drain lines; drain data lines directly formed on said one substrate, for serially transferring in series said display data signals, said gray scale voltage signals and various high-speed and low-speed clock signals inclusive of pixel clock signals between said drain drivers; gate data lines directly formed directly on said one substrate, for serially transferring in series said scanning voltage signals and said scanning clock signals between said gate driver, and gate driver power supply lines; and a flexible printed substrate formed of a drain driver power supply line section and an interface wiring section, wherein said drain driver power supply line section has only drain driver power supply lines formed thereon along an outer periphery of said drain drivers on said one substrate, and said interface wiring section is arranged at an end of said drain driver power supply line section close to an area at which said gate drivers are arranged and has an extension of said drain driver power supply lines, drain data connecting lines connected to said drain data lines, gate data connecting lines connected to said gate data lines and gate driver power supply connecting lines connected to said gate driver power supply lines.