Patent ID: 7327599
Filing Date: 2008-02-05
Classification: G11C

Abstract:
1. A semiconductor memory device including a memory cell comprising: first and second inverters each having an output terminal that is mutually connected to an input terminal of said other first or second inverter; a first selection transistor controlling a connection of the output terminal of said first inverter to a bit line; and a second selection transistor controlling a connection of the output terminal of said second inverter to another bit line; wherein said first inverter includes a first load transistor connected to a power source and a first drive transistor connected to the power source via said first load transistor and switched over in its ON/OFF-states, wherein a common terminal between said first load transistor and said first drive transistor forms the output terminal of said first inverter, and a connection terminal connecting a gate of said first load transistor to a gate of said first drive transistor forms the input terminal of said first inverter, wherein said second inverter includes a second load transistor connected to the power source and a second drive transistor connected to the power source via said second load transistor and switched over in its ON/OFF-states, wherein a common terminal between said second load transistor and said second drive transistor forms the output terminal of said second inverter, and a connection terminal connecting a gate of said second load transistor to a gate of said second drive transistor forms the input terminal of said second inverter, wherein when said first inverter is switched ON, said second inverter is switched OFF, and, when said second inverter is switched ON, said first inverter is switched OFF, thus functioning as said memory cell, wherein when writing data to said memory cell, said first selection transistor and said second selection transistor are switched ON thereby to input the data to said second inverter as well as to said first inverter, and, when reading the data from said memory cell, said first selection transistor is switched ON, the data is read from said first inverter while said second selection transistor is switched OFF, and wherein a ratio of a driving current quantity that is outputted in the ON-state of said first drive transistor to a driving current quantity that is outputted in the ON-state of said first selection transistor, is larger than a first predetermined value.