Patent ID: 6519743
Filing Date: 2003-02-11
Classification: G06F

Abstract:
A method for converting a logic design into a logic representation based upon cells of a target library; the method comprising the steps of:a) converting said logic design into a plurality of Boolean zones; b) partitioning the Boolean zones into a set of interconnected logic cones and buffer trees; c) sorting the logic cones in a forward breadth first search order and tiling the logic cones one after another; d) selecting that part of each such logic cone having a slack which is the worst; e) in each logic cone sorting all possible children nodes to form a pile of nodes in decreasing order of their associated slack; f) expanding a first expandable node on the pile of sorted children nodes; g) resorting the pile of nodes; and h) iteratively expanding and resorting until said representation is achieved.