Patent ID: 8570808
Filing Date: 2013-10-29
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory device comprising: a three-dimensional memory cell array including a plurality of memory cells arranged in a plurality memory cell array layers stacked on a substrate, such that a plurality of words lines extends across the plurality of memory cell array layers from a lowest memory cell array layer closest to the substrate to a highest memory cell array layer farthest from the substrate; a voltage generator circuit that generates a first voltage signal and a second voltage signal; and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line among the plurality of word lines and the second voltage signal to an unselected word line among the plurality of word lines, wherein the selected word line and the unselected word line have different resistances, the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time, and during the defined period of time the voltage generator circuit increases the first voltage signal and the second voltage signal from a first level to a second level.