Patent ID: 6245688
Filing Date: 2001-06-12
Classification: H01L

Abstract:
A method of fabricating an inter-level dielectric layer, comprising the steps of:preparing a semiconductor substrate having electrical elements thereon and therein;depositing a dielectric layer containing boron and phosphorous on said substrate;exposing said dielectric layer to a controlled environment, said exposing said substrate in a controlled environment is exposing said substrate in an open environment to an element selected from the group consisting of dry air and dry Ar and dry N.sub.2 and any other inert gas, under atmospheric pressure and ambient temperature, said exposing not extending beyond 5 minutes after said depositing a dielectric layer, said exposing occurring immediately after said depositing a dielectric layer,incurring a delay, said delay not exceeding 20 hours; andperforming a reflow process on said dielectric layer.