Patent ID: 7002198
Filing Date: 2006-02-21
Classification: G11C,H01L

Abstract:
1. A memory cell, comprising: a conductively-doped polysilicon layer having a first conductivity type formed overlying a substrate having the first conductivity type; a ferroelectric transistor formed overlying the polysilicon layer, wherein the transistor has a control gate, a ferroelectric layer interposed between the polysilicon layer and the control gate, a first source/drain region having the first conductivity type formed in the polysilicon layer, a second source/drain region having the first conductivity type formed in the polysilicon layer, and a channel having the first conductivity type formed in the polysilicon layer interposed between the first and second source/drain regions; and a well region having a second conductivity type opposite the first conductivity type, wherein the well region is interposed between the second source/drain region and the substrate.