Patent ID: 8078851
Filing Date: 2011-12-13
Classification: G06F

Abstract:
1. A method for recovering a global history shift register (GHSR) of an instruction pipeline of a processor, the method comprising: providing a branch recovery table (BRT); adding a record to the BRT according to each of a plurality of branch instructions when said branch instruction enters a predetermined stage of the instruction pipeline; providing a timer for keeping a timing value according to a clock signal of the instruction pipeline wherein each of the records comprises a timestamp and the timestamp is the timing value outputted from the timer when the corresponding branch instruction enters the predetermined stage; determining a removal range of the BRT according to a condition which triggers a pipeline flush of the instruction pipeline; removing all records in the removal range; and recovering the GHSR of the instruction pipeline according to the removed records, wherein if the pipeline flush is triggered by an exception occurring at an exception stage of the instruction pipeline, the removal range is determined by: subtracting a number of the predetermined stage from a number of the exception stage and taking the result as a distance; and subtracting the distance from a present timing value of the timer and taking the result as a time limit, wherein the removal range comprises all records whose timestamps are greater than the time limit.