Patent ID: 7807540
Filing Date: 2010-10-05
Classification: H01L

Abstract:
1. A method of making an integrated circuit including a back end capacitor, the method comprising: forming a first dielectric layer over a semiconductor substrate including over an active device; forming and patterning a first layer of resistive material over the first dielectric layer; forming a second dielectric layer over the first dielectric layer and over the patterned first layer of resistive material; forming and patterning a second layer of resistive material over the second dielectric layer; forming a third dielectric layer over the second dielectric layer and over the patterned second layer of resistive material; selectively etching the third, second and first dielectric layers to provide at least one first contact opening down to the active device and a second contact opening down to a patterned lower plate region of one of the patterned first and second layers of resistive material; forming a first layer of conductive material over the third dielectric layer and within the at least one first and second contact openings; and patterning the first layer of conductive material to define first conductors for providing electrical contact to the active device through the at least one first contact opening, and to the patterned lower plate region through the second contact opening; whereby the steps are conducted so that a capacitor is formed having a lower plate defined by the patterned lower plate region and an upper plate defined by a patterned upper plate region of one of the patterned second layer of resistive material or the patterned first layer of conductive material.