Patent ID: 6027979
Filing Date: 2000-02-22
Classification: H01L

Abstract:
A method for fabricating a portion of an integrated circuit device, comprising the steps of:forming a gate electrode on a semiconductor substrate with a gate insulating layer therebetween;then prior to performing a lightly doped drain implant, forming a masking layer over the substrate, the masking layer having an opening where the gate electrode crosses an active area of the substrate to define a field effect transistor, the opening of the masking layer exposing only portions of the active area adjacent the gate electrode and not the remaining portions of the active area;performing a lightly doped drain implant of impurities having a second conductivity type and a halo implant of impurities having a first conductivity type into the substrate through the opening in the masking layer so that the remaining portions of the active area do not receive either the halo implant or the light doped drain implant; andafter the halo implant performing step, removing the first masking layer, forming sidewall spacers alongside the gate electrode, and forming heavily doped source and drain regions in the substrate in the exposed and remaining portions of the active area adjacent the gate electrode.