Patent ID: 9183150
Filing Date: 2015-11-10
Classification: G06F

Abstract:
1. A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and at least two second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via a corresponding one of the at least two second interfaces, the logic operatively coupled to the first and second interfaces, the method comprising: receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative; wherein at least two of the N≧2 non-cooperative processors are different from one another with respect to a virtual memory interface having different physical page sizes with respect to one another; and wherein the interfaces comprise both hardware connections and software to interpret control signals.