Patent ID: 8022847
Filing Date: 2011-09-20
Classification: G11B

Abstract:
1. A signal processing device, comprising: a first offset unit configured to provide a DC offset by high-speed operation according to an offset control signal to a reproduced signal input to absorb drastic DC offset; a second offset unit configured to provide a DC offset by low-speed operation according to an offset control signal to the reproduced signal input to absorb offset of the reproduced signal having asymmetry; an A/D converter configured to provide an output from the first offset unit or an output from the second offset unit as an input signal, and to analog-to-digital convert the input signal by sampling the input signal with a clock having a predetermined clock period T and output sampling data; a peak detector configured to receive an output from the A/D converter, and perform peak detection with a clock having a period that is m times (m being a positive integer) of the clock period T; a bottom detector configured to receive an output from the A/D converter, and perform bottom detection with a clock having a period that is n times (n being a positive integer) of the clock period T; an offset detector configured to receive an output from the peak detector and an output from the bottom detector, calculate a signal offset in the input signal to the A/D converter and output an offset information signal; and a controller configured to exclusively control the offset controls provided by the first and second offset units according to the offset information signal outputted from the offset detector; a gate signal generator configured to generate a gate signal; and a storage unit configured to store information regarding a control signal outputted from the controller, wherein the controller exclusively controls the offset control operations performed by the first and second offset units according to the offset information signal and the gate signal, a hold information to be input to the controller is controlled by the gate signal outputted from the gate signal generator and the first offset controller instantaneously absorbs the drastic DC offset by using the hold information stored in the storing unit, and the offset in the input signal to the A/D converter is kept approximately constant independently of a local variation in the reproduced signal.