Patent ID: 7052967
Filing Date: 2006-05-30
Classification: H01L

Abstract:
1. A method for fabricating a capacitor array of a semiconductor device having a plurality of capacitors, the method comprising: forming an insulating layer having a low dielectric constant over a semiconductor substrate; forming an etching stop layer over the insulating layer; forming a plurality of openings that expose a top surface of the semiconductor substrate at predetermined intervals by patterning the insulating layer and the etching stop layer; forming a lower electrode conductive layer over the etching stop layer and in the plurality of openings; removing a part of the lower electrode conductive layer to expose a surface of the etching stop layer, thereby forming a plurality of lower electrodes that are insulated from each other by the insulating layer; forming one or more air gaps between the plurality of lower electrodes by performing a heat treatment process at a predetermined temperature to remove the insulating layer from between the plurality of lower electrodes; forming a dielectric layer over the lower electrodes; and forming an upper electrode over the dielectric layer.