Patent ID: 7119420
Filing Date: 2006-10-10
Classification: H01L

Abstract:
1. A chip packaging structure adapted to reduce electromagnetic interference, comprising a chip having a plurality of electrical contacts provided on one side thereof, and a leadframe having a plurality of leads that are arranged in a predetermined manner and provided at one side with a protrusion each for electrically connecting to external elements; said chip packaging structure being characterized in that said leadframe are fixedly attached to the side of said chip having said electrical contacts provided thereon, such that said protrusions on said leads of said leadframe are located closer to lateral outer sides of said leadframe; that said leads are connected at respective inner ends to said electrical contacts on said chip via lead wires; that an adhesive layer is applied to one side of said leadframe having said protrusions provided thereon to thereby adhere a conducting layer in the form of a sheet to said leadframe with said protrusions on said leads downward extended through multiple rows of through holes formed on said conducting layer corresponding to said protrusions on said leads; and that at least one of said electrical contacts on said chip is electrically connected to said conducting layer.