Patent ID: 6671678
Filing Date: 2003-12-30
Classification: G06F,G06N

Abstract:
A multi-value states multi-functional arithmetic apparatus, characterized by: said apparatus is comprised of a gating array, which is made of gating devices based on the structure of n rowsÃ—m columns, each gating device has at least two input pins and at least one output pin, one of the input pins of each of the gating devices on the same row is connected to each other as a row input contact, the other input pin of each of the gating devices on the same column is connected to each other as a column input contact, variable input value statesâ€”weightâ€”exist between the row input contacts, similarly, variable input value statesâ€”weightâ€”exist between the column input contacts, and, there is a correspondence relationship between the input value state of each gating device and its position in the array, the value of the input value state of the row input contact shall be in the range of 0 to (nâˆ’1), while the value of the input value state of the column input contact shall be in the range of 0 to (mâˆ’1), Each output pin of that gating device also has an output value state, an arithmetic relationship exists between the output value state of each gating device and its input value state based on the self organization principle model of the integer cluster, the output pins of those gating devices with the same operational output value state are connected together via an isolating circuit as an output contact, the output value state of the output contact shall be within the range of 0 to (n+mâˆ’1); while the output of the output value state is determined via gating of the gating device, wherein n>1 and m>1.