Patent ID: 9214980
Filing Date: 2015-12-15
Classification: H03D,H04B

Abstract:
1. A high-frequency signal processor circuitry provided with a first operation mode and a second operation mode, the high-frequency signal processor circuit comprising: a test signal generating circuit that generates a test signal having a first frequency component and a second frequency component; a first switch that transmits a signal received as a first signal at an antenna in the first operation mode and transmits the test signal as the first signal in the second operation mode; a first mixer circuit A that includes a differential circuit capable of correcting a differential balance within a specified variable range and uses a first local signal A′ to down-convert the first signal into a second signal A″ having a frequency band lower than the first signal; a first mixer circuit B that includes a differential circuit capable of correcting a differential balance within a specified variable range and uses a first local signal B′ to down-convert the first signal into a second signal B″, the first local signal B′ having a phase 90° different from the first local signal A′; a phase detection portion that, in the second operation mode, extracts a third signal A′″ from the second signal A″, the third signal A′″ having a frequency component equivalent to a difference between the first frequency component and the second frequency component, extracts a third signal B′″ from the second signal B″, the third signal B′″ having a frequency component equivalent to the difference between the first frequency component and the second frequency component, and detects a phase for the third signal A′″ and a phase for the third signal B″′; and a control portion that changes the differential balance for the first mixer circuit A according to a result from the phase detection portion detecting a phase for the third signal A′″ and changes the differential balance for the first mixer circuit B according to a result from the phase detection portion detecting a phase for the third signal B′″, wherein the first mixer circuit A operates in the first operation mode while the differential balance for the first mixer circuit A is set to a first correction value CVA within a variable range, wherein the first mixer circuit B operates in the first operation mode while the differential balance for the first mixer circuit B is set to a first correction value CVB within a variable range, wherein the control portion performs a first process, a second process, and a third process in the second operation mode, wherein the first process varies the differential balance for the first mixer circuit A and concurrently searches for a first transition point TPA that allows a phase for the third signal A′″ to transition by approximately 180° before and after varying the differential balance within a minimum fluctuation range, wherein the second process varies the differential balance for the first mixer circuit B and concurrently searches for a first transition point TPB that allows a phase for the third signal B′″ to transition by approximately 180° before and after varying the differential balance within a minimum fluctuation range, and wherein the third process supplies the first mixer circuit A with the differential balance corresponding to the first transition point TPA as the first correction value CVA and supplies the first mixer circuit B with the differential balance corresponding to the first transition point TPB as the first correction value CVB.