Patent ID: 8856500
Filing Date: 2014-10-07
Classification: G06F

Abstract:
1. A data processing device, comprising: a functional unit for executing instructions from a memory, an address output for supplying target addresses of instructions to the memory; and a program flow control unit configured to determine the target addresses for supply to the address output, the program flow control unit being configured to introduce address steps of position dependent size and/or direction between target addresses of instructions at logically successive positions in the program, at least part of the address steps not corresponding to instruction size, wherein a sequence of successive original instruction addresses is assigned to a set of respective target addresses, with successive address steps between the target addresses to which the successive original instruction addresses are mapped, the target addresses of the set lying in a plurality of non-overlapping address ranges, the mapping filling at least half of each of the ranges with instructions, the successive address steps comprising first address steps within at least a first one of the ranges and, between said first address steps, second address steps within at least a second one of the ranges; and wherein the program flow control unit is configured to generate the address steps of mutually opposite sign between target addresses of logically successive instructions with equal frequency.