Patent ID: 7210338
Filing Date: 2007-05-01
Classification: F15B,F16H,F16K

Abstract:
1. A valve testing device having an integrated purge circuit, comprising: at least one valve receptacle for receiving a valve to be tested; a purge port connected to said at least one valve receptacle; a test port and an exhaust port connected to said at least one valve receptacle, said test port and said exhaust port prevented from communication; a source of pressurized fluid connected to both said purge port and said test port by a fluid directing means; and a flow rate measuring means for measuring the flow rate of fluid through said valve; wherein placement of said fluid directing means in a first position causes a purging of said valve by directing pressurized fluid through said valve in a direction opposite to its normal direction of flow through said valve when said valve is in use; and wherein placement of said fluid directing means in a second position causes pressurized fluid to travel through said test port and through said valve in a normal direction to said flow rate measuring means.