Patent ID: 7757862
Filing Date: 2010-07-20
Classification: H01L

Abstract:
1. A semiconductor chip housing tray that houses a plurality of semiconductor chips and is stackable in a plurality of stages with at least an upper housing tray and a lower housing tray that are each substantially identical to the semiconductor chip housing tray, the semiconductor chip housing tray comprising: a base plate defining an upper surface and an under surface opposite the upper surface; a plurality of upper surface protruding parts disposed on the upper surface of the base plate, which divide the upper surface of the base plate into a plurality of first semiconductor chip housing areas; a plurality of under surface protruding parts disposed on the under surface of the base plate, which divide the under surface of the base plate into a plurality of second semiconductor chip housing areas, wherein each of the first semiconductor chip housing areas have a first margin width with respect to a semiconductor chip of the plurality of semiconductor chips and each of the second semiconductor chip housing areas have a second margin width with respect to the semiconductor chip that is greater than the first margin width, the first margin width being a distance between an edge of the semiconductor chip and an edge of a corresponding first semiconductor housing area when the semiconductor chip is centered within the first semiconductor housing area and the second margin width being a distance between an edge of the semiconductor chip and an edge of a corresponding second semiconductor housing area when the semiconductor chip is centered within the second semiconductor housing area, wherein, when the semiconductor chip housing tray is stacked with the lower housing tray, the plurality of second semiconductor chip housing areas overlap corresponding first semiconductor chip housing areas of the lower housing tray, and wherein, when the semiconductor chip housing tray is stacked with the upper housing tray, the plurality of first semiconductor chip housing areas overlap corresponding second semiconductor chip housing areas of the upper housing tray; wherein, when the semiconductor chip housing tray is stacked with the lower housing tray, a bottom surface of a first under surface protruding part of the under surface protruding parts does not face a top surface of a first upper surface protruding part of the upper surface protruding parts of the lower housing tray; wherein, when the semiconductor chip housing tray is stacked with the upper housing tray, a top surface of a first upper surface protruding part of the upper surface protruding parts does not face a bottom surface a first under surface protruding part of the under surface protruding parts of the upper housing tray; wherein, when the semiconductor chip housing tray is stacked with both the upper housing tray and the lower housing tray, each of a distance between the bottom surface of the first under surface protruding part of the under surface protruding parts of the upper housing tray and an upper surface of the semiconductor chip housing tray, and a distance between the top surface of the first upper surface protruding part of the upper surface protruding parts of the lower housing tray and an under surface of the semiconductor chip housing tray is smaller than a thickness of each of the plurality of semiconductor chips; wherein, a bottom surface of a second under surface protruding part contacts a top surface of a second upper surface protruding part of the lower housing tray; wherein a sum of a height of the second under surface protruding part of the upper housing tray and a height of the second upper surface protruding part is equal to the height of each of the first under surface protruding part and the first upper surface protruding part; and wherein, each of a height of the first under surface protruding part and a height of the upper surface protruding part is larger than the thickness of each of the plurality of semiconductor chips.