Patent ID: 6268287
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method of forming metal lines in the fabrication of an integrated circuit comprising:providing an insulating layer on a semiconductor substrate;depositing a first barrier metal layer overlying said insulating layer;depositing a metal layer overlying said barrier metal layer;depositing a second barrier metal layer overlying said metal layer;depositing a composite hard mask layer overlying said second barrier metal layer;forming a photoresist mask overlying said composite hard mask layer having openings where openings are to be made within said metal layer;first partially etching away said composite hard mask layer where it is not covered by said photoresist mask;second overetching away most of said composite hard mask layer not covered by said photoresist mask leaving a patterned hard mask and a portion of said hard mask layer within said openings whereby a polymer is formed within said openings;removing said photoresist mask;thereafter removing said polymer;thereafter third etching away said metal layer and said first and second barrier metal layers not covered by said patterned hard mask to form said metal lines wherein said hard mask layer within said openings is also removed; andcompleting said fabrication of said integrated circuit.