Patent ID: 8010593
Filing Date: 2011-08-30
Classification: G06F,Y02D

Abstract:
1. An adaptable computing engine comprising: a plurality of configurable computing nodes on an integrated circuit, each configurable computing node having a plurality of computational elements coupled to an interconnection network to exchange data to and from the nodes, the node being configurable to perform a task by changing the interconnections between the plurality of computational elements via the interconnection network; a plurality of hardware node wrappers, each of the plurality of hardware node wrappers corresponding to one of the plurality of computing nodes, each of the node wrappers providing an interface between the computing node and the node interconnection network, each node wrapper comprising a hardware task manager having hardware to schedule a task to be performed by the computing node, configure the computing node to perform the task and control the flow of data to and from the computing node by assigning ports on the node to perform the task; and wherein the node interconnection network to allow the exchange of configuration information to and from the computing nodes, the node wrapper to read the configuration information to configure the corresponding computing node to perform a first function and the node wrapper to read the configuration information to reconfigure the corresponding computing node to perform a second function.