Patent ID: 8124426
Filing Date: 2012-02-28
Classification: H01L,Y10S

Abstract:
1. A method for forming a memory device, the method comprising: forming a bottom wiring layer; forming a plurality of tunnel junctions (TJs) and tunnel junction vias (TJVs) contacting the bottom wiring layer; forming a top wiring layer contacting the plurality of TJs and the plurality of TJVs; electrically addressing the plurality of TJVs separately from the plurality of TJs; and subjecting the plurality of TJVs to a voltage configured to cause short-circuit breakdown of the plurality of TJVs, wherein the separate electrical addressing of the TJVs and the TJs causes the TJs to not be subjected to the voltage; wherein the plurality of TJVs are formed such that the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs.