Patent ID: 8828812
Filing Date: 2014-09-09
Classification: H01L

Abstract:
1. A preparation method of a silicon (Si)/germanium (Ge) heterojunction Tunnel Field Effect Transistor (TFET) comprising steps of: Step 1: providing a Silicon On Insulator (SOI) substrate having top Si, a buried oxide layer and a back substrate, forming a silicon germanium (SiGe) layer and a surface Si layer successively on the top Si, and etching off peripheral parts of the SiGe layer and the surface Si layer according to a preset size, so as to form a mesa structure stacked by the SiGe layer and the surface Si layer on the surface of the top Si; Step 2: forming a SiO Step 3: performing oxidizing and annealing on the mesa structure to oxidize the surface Si layer and gradually oxidize the SiGe layer and the top Si, so that Ge in the SiGe layer is longitudinally diffused toward the top Si and gradually concentrated, and is laterally diffused in the top Si to form a Ge/Si heterojunction structure with a gradient Ge content, so as to prepare a SiGe or Ge region; Step 4: removing the Si Step 5: manufacturing a gate, and manufacturing a source region and a drain region using a self-aligned process, wherein the source region is located in the SiGe or Ge region, the drain region is located in the Si region, and the gate covers both a part of the SiGe or Ge region and a part of the Si region.