Patent ID: 6667635
Filing Date: 2003-12-23
Classification: H03K

Abstract:
A lookup table (LUT) in a low-voltage field programmable gate array (FPGA) configurable with a configuration bitstream, comprising:N LUT input terminals, where N is an integer; N inverters, each having an input terminal coupled to an associated one of the LUT input terminals and further having an output terminal; a LUT output terminal; a plurality of memory cells storing values from the configuration bitstream, each memory cell having an output terminal; and a plurality of CMOS pass gates coupled between the output terminal of each memory cell and the LUT output terminal, wherein a path between each memory cell and the LUT output terminal traverses N of the CMOS pass gates, each CMOS pass gate on a given path having a first gate terminal coupled to a different one of the LUT input terminals and a second gate terminal coupled to the output terminal of the associated inverter.