Patent ID: 6259494
Filing Date: 2001-07-10
Classification: G02F

Abstract:
An integrated thin film transistor matrix substrate comprising:an insulated substrate;a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on said insulated substrate, each of said accumulated capacitance bus lines extending parallel to and between a pair of said gate bus lines;a plurality of auxiliary capacitance electrodes extending from said accumulated capacitance bus lines;a first insulated film provided on said gate, accumulated capacitance bus lines and said auxiliary capacitance electrodes;a plurality of operating films formed on said first insulated film;a plurality of thin film transistors corresponding to said operating films provided on said operating films, each of said gate bus lines electrically connecting at least two of said thin film transistors;a plurality of parallel drain bus lines provided substantially perpendicular to said gate and accumulated capacitance bus lines on said first insulated film, each of said drain bus line electrically connecting at least two of said thin film transistors;a second insulated film provided on said thin film transistors and said drain bus lines, said second insulated film having an opening over each of said thin film transistors;a plurality of pixel electrodes provided on said second insulated film, each of said pixel electrodes being electrically connected to a corresponding one of said transistors via said opening; andat least a first and a second overlapping region formed along each of said plurality of auxiliary capacitance electrodes and overlapping with a corresponding one of said plurality of drain bus lines.