Patent ID: 8686755
Filing Date: 2014-04-01
Classification: G06F,G11C,Y02D

Abstract:
1. A system, comprising: a single data rate (“SDR”) clock coupled to an SDR logic core and clocking the SDR logic core at either one of a rising edge or a falling edge of the SDR clock; a clock enable control; and an SDR clock gate coupled to the SDR clock, and configured to transition an output state of the SDR clock gate on a triggering edge of the SDR clock when the clock enable control is enabled producing a double data rate (“DDR”) clock running at half of the frequency of the SDR clock, and to hold the output state of the SDR clock gate when the clock enable control is disabled, wherein the DDR clock is coupled to a DDR logic core and clocks the DDR logic core at both a rising edge and a falling edge of the DDR clock.