Patent ID: 6255977
Filing Date: 2001-07-03
Classification: H03M

Abstract:
Sigma-delta D-A converter (100, 200, 300) with N stages, in which the nth stage, where n=1, 2, 3 . . . N, comprises a first adder (10) which adds a use signal x(k) (12) with an error signal err.sub.n (k-1) to an input signal e.sub.n (k) (14), a quantizer (16) which quantizes the input signal e.sub.n (k) (14) to an output signal y.sub.n (k) (18) according to a predetermined quantization function, and a second adder (20) which adds the input signal e.sub.n (k) (14) with the inverted output signal y.sub.n (k) to x.sub.n (k) (21), and supplies it to a delay device (22) which sends the signal x.sub.n (k) (21) to the first adder (10) as an error signal err.sub.n (k-1) with a delay by a clock period, characterized in that an amount reducer (24) is provided between the second adder (20) and the delay device (22), which amount reducer (24) leaves the signal x.sub.n (k) (21) unchanged when x.sub.n (k)=0 and otherwise lowers the amount .vertline.x.sub.n (k).vertline. of the signal x.sub.n (k) (21) by at least a smallest representable numerical unit, wherein the quantization function of the quantizer (16) of the nth stage of the sigma-delta D-A converter (100, 200, 300) is expressed as follows: ##EQU15##