Patent ID: 8407532
Filing Date: 2013-03-26
Classification: G01R,G06F,G16Z

Abstract:
1. A test apparatus that tests a device under test, comprising: a test unit that sends and receives signals to and from the device under test; and a control apparatus that controls the test unit, wherein the control apparatus includes: a first buffer and a second buffer that buffer packets including access requests to the test unit; a data output section that, (i) during normal operation, generates normal operation packets including identification information identifying that the packets are for normal operation, and buffers, in the first buffer, the normal operation packets to be sent from the control apparatus to the test unit and, (ii) when an error occurs, generates error occurrence packets including identification information identifying that the packets are for an error occurring situation, and buffers, in the second buffer, the error occurrence packets to be sent from the control apparatus to the test unit; and a transmitting section that, during normal operation, sequentially transmits the normal operation packets in the first buffer to the test unit and, when an error occurs, sequentially transmits the error occurrence packets in the second buffer to the test unit.