Patent ID: 6540927
Filing Date: 2003-04-01
Classification: H01L,Y10S,Y10T

Abstract:
A method of producing a semiconductor packaging part which includes pits covered with plating layers for connecting terminals of semiconductor chips to external terminals, said method comprising the steps of:(a) providing a thin metal sheet having a plurality of pairs of first aligned holes located along respective edges of said sheet at predetermined intervals in a lengthwise direction of said sheet and a plurality of pairs of second aligned holes located inwardly of respective pairs of said first aligned holes, (b) providing a frame with part pattern which can be positioned over one surface of said metal sheet, (c) positioning a first resist layer on said one surface of said metal sheet within said pairs of first holes and so as to cover said pairs of second holes, (d) positioning said frame with part pattern over said one surface of said metal sheet and said first resist layer so as to be accurately positioned relative to said pairs of first holes, (e) transferring said part pattern to said first resist layer, (f) removing said frame with part pattern from a position over said one surface of said metal sheet, (g) etching said metal sheet with first resist layer thereon to form pits in said metal sheet based on said part pattern in said first resist layer and to remove side edges of said metal sheet, including said pairs of first sprocket holes, laterally of said first resist layer, (h) removing said first resist layer, (i) positioning a second resist layer on said one surface of said metal sheet and within said pairs of second holes, (j) repositioning said frame with part pattern over said one surface of said metal sheet so as to be accurately positioned relative to said second pairs of holes, (k) transferring said part pattern to said second resist layer, and (l) forming plating layers on surfaces of said pits based on said part pattern in said second resist layer.