Patent ID: 7800132
Filing Date: 2010-09-21
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semi-insulating substrate; a channel layer disposed above the semi-insulating substrate; a barrier layer disposed over the channel layer, the barrier layer inducing a 2-DEG layer at an interface between the barrier layer and the channel layer; source and drain regions disposed above the barrier layer to form a low resistivity connection through the barrier layer to the 2-DEG layer; a T-gate disposed between the source and drain regions and above the barrier layer; a first field plate disposed above a portion of the T-gate; a second field plate disposed above the barrier layer and in a vicinity of the T-gate; and a dielectric layer coating a portion of the barrier layer between the source region and the T-gate and between the drain region and the T-gate, and the T-gate, wherein the first and second field plates are disposed on the dielectric layer.