Patent ID: 6800515
Filing Date: 2004-10-05
Classification: H01L

Abstract:
A method for manufacturing, in a first region of a semiconductor wafer, DRAM cells each including a MOS control transistor and a capacitor and, in a second region of the wafer, MOS transistors, the first and second regions being covered with a protection layer and with a first insulating layer, including the steps of:etching at the level of the first region first openings to expose the source or drain regions of the control transistors; filling the first openings with a first conductive material; re-etching the first conductive material down to part of the depth of the first openings; depositing at the level of the first and second regions a second insulating layer; etching at the level of the first region second openings and at the level of the second region third openings exposing source or drain regions of the transistors; and filling the second and third openings with a second conductive material; depositing at the level of the first and second regions a third insulating layer; etching at the level of the first region fourth openings exposing the first conductive material of the first openings, and extending over gates of adjacent control transistors; forming the capacitors at the level of the fourth openings; and etching at the level of the first and second regions fifth openings respectively joining the second openings and the third openings; and filling the fifth openings of the second conductive material to form vias.