Patent ID: 7741695
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor substrate of p-type; a semiconductor layer of n-type formed on said semiconductor substrate; and a first impurity region of said p-type formed in said semiconductor layer, extending from an upper surface of said semiconductor layer to an interface between said semiconductor layer and said semiconductor substrate to surround a part of said semiconductor layer, said first impurity region having a higher impurity concentration than said semiconductor layer, said part of said semiconductor layer including: a first region sandwiched by said first impurity region so that said first impurity region contacts said first region from both sides of said first region in a first direction parallel to said upper surface of said semiconductor layer, a second region located apart from said first region and electrically connected to an electrode located directly above said second region, and a third region located between said first region and said second region to come in contact with said first region and said second region, said third region being sandwiched by said first impurity region so that said first impurity region contacts said third region from both sides of said third region in a second direction parallel to said upper surface of said semiconductor layer and said first direction, in plan view, said first region, said third region and said second region being arranged along a direction parallel to said upper surface of said semiconductor layer and perpendicular to said first direction and said second direction in this order, said semiconductor device further comprising: a first buried impurity region of said n-type formed at an interface between said first region and said semiconductor substrate, said first buried impurity region having a higher impurity concentration than said semiconductor layer; and a semiconductor element formed in said semiconductor layer above said first buried impurity region, wherein a capacity element is electrically connected to said first region, and in plan view, a width of said third region in said second direction is narrower than a width of said first region in said first direction.