Patent ID: 6473835
Filing Date: 2002-10-29
Classification: G06F

Abstract:
A computer system comprising:at least one central processor unit; a main memory; a first cache at a first cache level for use by said at least one central processing unit, said first cache comprising a translation lookaside buffer (TLB) and a first cache memory array; and a second cache at a second cache level for use by said at least one central processing unit, said second cache level being higher than said first cache level, said second cache comprising a second cache memory array and second cache control logic, said second cache memory array being an array of n columns and m rows, wherein a first portion of said second cache memory array having nâˆ’p of said n columns is used for storing data and a second portion of said second cache memory array having p of said n columns is used for storing pairs of virtual address portions and real address portions for at least some data in the first portion of said second cache memory array, wherein (nâˆ’2)&gE;p&gE;1, said first and second portions of the second cache memory array being disjoint; wherein said second cache control logic receives at least a portion of a virtual address generated by said central processor unit and receives output of said translation lookaside buffer comprising at least a portion of a real address corresponding to said virtual address; wherein if a virtual address generated by said central processor unit is contained in said translation lookaside buffer, said second level cache control logic selects an entry in said first portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit and said output of said translation lookaside buffer; wherein if a virtual address generated by said central processor unit is not contained in said translation lookaside buffer, said second level cache control logic selects an entry in said second portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit to obtain an address pair comprising a virtual address portion and a real address portion, and subsequently selects an entry in said first portion of said second cache memory array using said at least a portion of a virtual address generated by said central processor unit and said real address portion obtained from said second portion of said second cache memory array.