Patent ID: 8422272
Filing Date: 2013-04-16
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a first line; a second line; a third line; a fourth line; and a memory cell comprising a first transistor, a second transistor and a capacitor, wherein the first transistor is a p-channel transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other to form a node where charge is held, wherein the first line, one of the first source electrode and the first drain electrode, and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein the second line and the other of the first source electrode and the first drain electrode are electrically connected to each other, wherein the third line and the second gate electrode are electrically connected to each other, and wherein the fourth line and the other electrode of the capacitor are electrically connected to each other.