Patent ID: 9123774
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A semiconductor device comprising: a gate electrode crossing over a semiconductor fin disposed on a substrate; a gate dielectric layer disposed between the gate electrode and the semiconductor fin; a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode; impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode; a first interlayer dielectric layer covering a surface of the substrate, except for the gate electrode; first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions; and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap interposed between the gate electrode and the impurity regions; wherein the gate electrode comprises a lower gate part having a constant width and an upper gate part having a width that gradually decreases from the lower gate part, wherein the air gap is formed between a lower portion of the lower gate part and the impurity regions, and wherein the second interlayer dielectric layer is formed between an upper portion of the lower part and the impurity regions.