Patent ID: 6133797
Filing Date: 2000-10-17
Classification: H03L

Abstract:
A correction circuit, comprising a detector circuit that includes:first and second latches having commonly coupled clock terminals for receiving the first input signal, where an input of the first latch is coupled to a first conductor terminal for receiving a first operating potential and an output of the first latch is coupled to an input of the second latch;third and fourth latches having commonly coupled clock terminals for receiving the second input signal, where an input of the third latch is coupled to the first conductor terminal for receiving the first operating potential and an output of the third latch is coupled to an input of the fourth latch;a logic gate having a first input coupled to an output of the second latch, a second input coupled to an output of the fourth latch, and an output that provides the output signal; andfirst and second current sources serially connected between the first conductor terminal and a second conductor terminal, where the first current source has a control terminal coupled to the output of the first latch, the second current source has a control terminal coupled to the output of the third latch, and an output of the first and second current sources supplies an analog signal.