Patent ID: 6108738
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A multiple bus master PCI (peripheral component interconnect) bus system within an integrated circuit, comprising:an integrated circuit fabricated onto a semiconductor die;an internal PCI bus built into said integrated circuit, said internal PCI bus adapted to transmit data signals thereon;a plurality of PCI agents built into said integrated circuit, each of said plurality of PCI agents for performing a function, each of said plurality of PCI agents coupled to said internal PCI bus, said internal PCI bus and said plurality of PCI agents built into said integrated circuit on said semiconductor die to form a high performance device, wherein at least one of said plurality of PCI agents is a pre-existing PCI agent with respect to said high performance device; anda parity generator circuit built into said integrated circuit, said parity generator circuit adapted to respond to parity generation and checking signals from at least one of said plurality of PCI agents.