Patent ID: 8502317
Filing Date: 2013-08-06
Classification: H03K

Abstract:
1. A level shifter circuit for converting a first input signal in the voltage domain of a first power supply into an output signal in the voltage domain of a second power supply, comprising: (a) a first PMOS transistor, with a source coupled to the second power supply and a gate connected to a complementary output node; (b) a second PMOS transistor, with a source coupled to the second power supply and a gate coupled to the output node; (c) a first HV PMOS transistor, with a source coupled to the output node and a gate coupled to a bias voltage; (d) a second HV PMOS transistor, with a source coupled to complementary output node and a gate coupled to a bias voltage; (e) a first HV NMOS transistor, with a drain coupled to the drain of the first HV PMOS transistor, a gate coupled to the first input signal, and source coupled to a ground terminal; and (f) a second HV NMOS transistor, with a drain coupled to the drain of the second HV PMOS transistor, a gate coupled to the complement of the first input signal, and source coupled to the ground terminal.