Patent ID: 7522145
Filing Date: 2009-04-21
Classification: G02F,G09G,G11C

Abstract:
1. A liquid crystal display apparatus comprising: a plurality of pixel electrodes arranged on a display region of a substrate in a matrix form, the pixel electrodes having a plurality of column lines and a plurality of row lines; a plurality of amorphous silicon thin film transistors, each having a first current electrode connected to a corresponding one of the plurality of pixel electrodes; a plurality of data lines, each being connected to second current electrodes of the thin film transistors; a plurality of first gate lines, each being connected to gate electrodes of odd numbered thin film transistors which are coupled to one of the plurality of row lines; a plurality of second gate lines, each being connected to gate electrodes of even numbered thin film transistors which are coupled to the one of the plurality of row lines; a data driving circuit for driving the data lines; at least two gate driving circuits having a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit is connected to the plurality of first gate lines and the second gate driving circuit is connected to the plurality of second gate lines, and wherein the first and second gate driving circuits comprise amorphous silicon thin film transistors and are formed in a peripheral region on the substrate; and a plurality of signal lines arranged on the substrate and carrying a first clock signal, a second clock signal, a first power source voltage, a second power source voltage and a start signal, wherein: the first and second gate driving circuits drive the row lines of the pixel electrodes in a zigzag form; each of the first and second gate driving circuits comprises a plurality of shift registers and sequentially selects the plurality of gate lines in accordance with output signals of respective shift registers; and an output signal of a shift register of the first gate driving circuit is supplied as a start signal to a shift register of the second gate driving circuit, wherein each of the first and second gate driving circuits comprises a plurality of stages and sequentially selects the plurality of gate lines in accordance with output signals of respective stages while the first gate driving circuit is supplied with the first clock signal and the second gate driving circuit is supplied with the second clock signal having a phase inverted with that of the first clock signal, and a stage comprises: an input terminal connected with a previous gate line; an output terminal connected with a corresponding gate line; a clock terminal for receiving a corresponding clock signal; a pull-up circuit connected between the clock terminal and output terminal; a pull-up driving circuit connected to an input node of the pull-up circuit wherein the pull-up driving circuit comprises a capacitor connected to the input node of the pull-up circuit and the output terminal; a control terminal connected with a next gate line; a pull-down circuit connected between the output terminal and the first power source voltage for allowing the corresponding gate line to pull down to the first power source voltage during a turn-on state; a pull-down driving circuit connected to an input node of the pull-down circuit for turning off the pull-down circuit in response to a preceding edge of the input signal and for turning on the pull-down circuit in response to a preceding edge of a control signal; and a floating blocking circuit connected between the input node of the pull-down circuit and the second power source voltage for constantly connecting the second power source voltage to the input node of the pull-down circuit to prevent the input node of the pull-down circuit from being floated, wherein the pull-up circuit pulls up the corresponding gate line during a duty period of the clock signal during the turn-on state, and the pull-up driving circuit turns on the pull-up circuit in response to a preceding edge of an input signal supplied to the input terminal and for turning off the pull-up circuit in response to a preceding edge of the control signal supplied to the control terminal.