Patent ID: 6289065
Filing Date: 2001-09-11
Classification: G06F

Abstract:
A status register for a FIFO which has N levels and holds data en route from a SENDER to a RECEIVER, comprising:a) a FIFO FULL indicating system, including:i) a first plurality of D-type flip-flops, one corresponding to each level of said FIFO;ii) first synchronization means for synchronizing an output signal of each of said D-type flip-flops in said first plurality of D-type flip-flops with a first clock signal; andiii) first logic means for indicating when the outputs of all of said first synchronization means are set;b) a FIFO EMPTY indicating system, including:i) a second plurality of D-type flip-flops, one corresponding to each level of said FIFO;ii) second synchronization means for synchronizing an output signal of each of said D-type flip-flops in said second plurality of D-type flip-flops with a second clock signal; andiii) second logic means for indicating when the outputs of all of said second synchronization means are set;c) means for toggling the corresponding D-type flip-flop in the first plurality of D-type flip-flops as each level of said FIFO is loaded with data; andd) means for toggling the corresponding D-type flip-flop in the second plurality of D-type flip-flops as each level of said FIFO is read;e) wherein said first logic means outputs a signal indicative of whether said FIFO is full and said second logic means outputs a signal indicative of whether said FIFO is empty.