Patent ID: 8990760
Filing Date: 2015-03-24
Classification: G01R,G06F

Abstract:
1. A method of cell-aware fault model generation, executed by at least one processor of a computer, comprising: receiving a transistor-level netlist and defects of interest for a cell; performing, at least one processor of a computer, analog one-cycle fault simulations based on the transistor-level netlist to identify type one detectable defects and type two detectable defects in the defects of interest; determining calculated two-cycle detection conditions for the type two detectable defects based on results of the analog one-cycle fault simulations for the type two detectable defects; performing analog two-cycle fault simulations based on the transistor-level netlist and the defects of interest, the type one detectable defects and the type two detectable defects to determine type three detectable defects and simulated two-cycle detection conditions for the type three detectable defects; generating two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects based on the calculated two-cycle detection conditions and the simulated two-cycle detection conditions; and storing the two-cycle cell-aware fault models for two-cycle testing of the type two detectable defects and the type three detectable defects.