Patent ID: 6910096
Filing Date: 2005-06-21
Classification: G09G,G11C,H04B

Abstract:
1. A synchronous dynamic random access memory device comprising: A. a single chip integrated circuit; B. a dynamic random access memory array formed on the chip, the array including plural array data leads carrying parallel data signals to the array and parallel array address leads carrying parallel address signals to the array, one data signal representing one data bit and one address signal representing one address bit, the array being organized in plural addressable locations with each location being randomly addressable by the address signals for writing one word of data bits from the array data leads to each addressed location; C. a clock signal terminal formed on the chip for receiving a clock signal formed of rising and falling edges regularly spaced in time, the clock signal being continuous during operation of the device; D. plural address terminals formed on the chip and receiving parallel address signals from external the chip, the received address signals occurring in plural groups separated in time and being received at the same time as the clock, terminal receives the continuous clock signal; E. plural registers formed on the chip and having address inputs coupled to the plural address terminals, the plural registers including a first address register having a first control input lead receiving a first control input signal for latching a first group of address signals, a second address register having a second control input lead receiving a second control signal for latching a second group of address signals, and a third address register for latching a third group of address signals; F. an address sequencer coupled between at least the third address register and the array address leads and coupled to the clock signal terminal, the address sequencer receiving the address signals from at least the third address register and providing address signals to the array address leads to access addressable locations in the array, the address sequencer sequencing through addresses starting from the address of the random location in the array received from at least the third address register; G. a command decoder formed on the chip and having a plurality of control inputs coupled to the address terminals, a first control output coupled to the first control input lead, and a second control output coupled to the second control input lead, the command decoder generating a first control signal on the first control output in response to a first set of control signals received on the control inputs, and generating a second control signal on the second control output in response to a second set of control signals received on the control inputs; and H. a data port formed on the chip and connecting with the array data leads and the clock signal terminal, the data port including: