Patent ID: 7871885
Filing Date: 2011-01-18
Classification: H01L,Y10S

Abstract:
1. A method comprising: forming a plurality of gate patterns, comprising a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate, over a semiconductor substrate; forming a compound spacer layer having a stack comprising a first oxide layer, a nitride layer, and a second oxide layer over a side wall of the gate pattern; forming at least one source/drain area in the semiconductor substrate at both sides of the gate pattern; coating a photoresist film over the semiconductor substrate; forming a scum between the gate patterns by exposing and developing the photoresist film; removing the second oxide layer; removing the scum; forming an interlayer insulating layer over the semiconductor substrate; forming a contact hole between the gate patterns by patterning the interlayer insulating layer; and forming a contact plug in the contact hole.