Patent ID: 6046900
Filing Date: 2000-04-04
Classification: H01H

Abstract:
A solenoid driver circuit adapted for use with a digital magnetic latching valve, said digital magnetic latching valve having a first solenoid coil and a second solenoid coil, said solenoid driver circuit comprising:signal generating means for receiving an externally generated position one/position two logic signal, said signal generating means responsive to said externally generated position one/position two logic signal generating a clock signal having a plurality of clock pulses and a gate voltage signal having a plurality of gate voltage pulses;Flip-Flop means for receiving said externally generated position one/position two logic signal and said clock signal, said Flip-Flop means, responsive to each of said plurality of clock pulses of said clock signal, delaying and then passing said externally generated position one/position two logic signal through said Flip-Flop means to a Q output of said Flip-Flop means to provide a delayed position one/position two logic signal;a relay having a relay coil and first, second, third and fourth relay contacts, the first and third relay contacts of said relay being connected to said first solenoid coil, the second and fourth relay contacts of said relay being connected to said second solenoid coil;first transistor means connected to the Q output of said Flip-Flop means to receive said delayed position one/position two logic signal, said first transistor means being connected to the relay coil of said relay, said first transistor means energizing the relay coil of said relay whenever said delayed position one/position two logic signal is at a first logic state;second transistor means for receiving said gate voltage signal, each of said plurality of gate voltage pulses turning on said second transistor means;said first, second, third and fourth relay contacts of said relay being toggled whenever said relay coil is energized to provide an electrical circuit which alternately has a predetermined resistance value coupled to only one of said first and second solenoid coils to reduce current flow to a predetermined amperage level through said one of said first and second solenoid coils having said predetermined resistance value coupled thereto;said second transistor means energizing said first solenoid coil and said second solenoid coil whenever second transistor means is turned on.