Patent ID: 6611855
Filing Date: 2003-08-26
Classification: H04W

Abstract:
A channelizer applied with a modified fast convolution algorithm, said channelizer comprising:an overlap block generator for forming blocks of data from a stream of digital data received from an analog-to-digital converter; an N-point Discrete Fourier Transform (DFT) processor that receives the data blocks from the overlap block generator and performs an N-point DFT on the data blocks; a block selection module that receives the processed data blocks from the DFT processor, and sequentially selects and forwards portions of the blocks for further processing, each of said forwarded portions comprising data blocks associated with a single channel at a time and an indication of the associated channel; and a plurality of pipelined processing modules that receives the forwarded portions of single-channel data blocks from the block selection module, and sequentially processes the data blocks in each of the pipelined processing modules, each of the pipelined processing modules being associated with a memory for storing parameters defined for a plurality of different channels, and each pipelined processing module including: means for retrieving the stored parameters for each portion of data blocks based upon the indication of the channel associated with each received portion of data blocks; means for processing each portion of data blocks in accordance with the retrieved parameters; and means for transferring processed data blocks to a next pipelined processing module in the plurality of modules; whereby, each of the pipelined processing modules retrieves the defined parameters for the data blocks received, processes the data blocks independently from any processing being simultaneously performed by other pipelined modules, and forwards the processed data blocks to the next pipelined processing module, thereby enabling the channelizer to dynamically adapt to different channel parameters with a single pipeline of processing modules.