Patent ID: 8404581
Filing Date: 2013-03-26
Classification: H01L

Abstract:
1. A method of fabricating an integrated circuit device, the method comprising: providing a substrate having an inter-layer dielectric (ILD) layer and an overlying capping layer formed thereon; forming a patterned hard mask layer on the capping layer and the ILD layer, wherein the patterned hard mask layer has a first opening defined by a first sidewall of the hard mask layer and a second sidewall of the hard mask layer; forming a layer overlying the patterned hard mask layer; patterning the layer to form a second opening, the second opening defined by a third sidewall of the layer and a fourth sidewall of the layer, wherein each of the first, second, third and fourth sidewalls are horizontally positioned at different points over the substrate; performing a first etch process, wherein the first etch includes etching the capping layer and the ILD layer, wherein the etch process includes forming a via hole in the ILD layer wherein a width of the via hole is defined by the third sidewall of the layer and the second sidewall of the patterned hard mask layer; performing a second etch process, after the first etch process, wherein the second etch process includes etching the patterned hard mask layer, using the patterned layer as a masking element, to form an etched hard mask layer, wherein the etching the patterned hard mask layer increases a width of the first opening in the patterned hard mask layer thereby providing a third opening, the third opening defined by the first sidewall and a fifth sidewall of the etched hard mask layer; and using the etched hard mask layer as a masking element to etch a fourth opening in the capping layer and a trench in the ILD layer, wherein the trench is contiguous with the via hole, wherein the fourth opening and the trench widths are defined by the first sidewall and the fifth sidewall of the etched hard mask layer.