Patent ID: 6894922
Filing Date: 2005-05-17
Classification: G11C

Abstract:
1. A memory device comprising: a plurality of normal memory cells; a plurality of spare memory cells used instead of a defective memory cell when said defective memory exists in said plurality of normal memory cells; a plurality of bit lines used for reading data from said plurality of normal memory cells; a read amplifying circuit reading data from said plurality of normal memory cells and said plurality of spare memory cells; a plurality of data lines for connecting said plurality of bit lines to said read amplifying circuit; and a connecting circuit forming parts of paths connecting said plurality of data lines to said plurality of normal memory cells and said plurality of spare memory cells so as to substantially equalize load capacitance of said plurality of data lines, wherein said connecting circuit not only connects a first selected bit line among said plurality of bit lines to be selected according to a first input address to a first data line among said plurality of data lines, but also forms parts of paths that connect a part of said plurality of spare memory cells to be selected according to said first input address to a second data line different from said first data line among said plurality of data lines, and also not only connects a second selected bit line among said plurality of bit lines to be selected according to a second input address to said second data line, but also forms parts of paths that connect a part of said plurality of spare memory cells to be selected according to said second input address to said first data line.