Patent ID: 8432348
Filing Date: 2013-04-30
Classification: G09G,H03K

Abstract:
1. A data signal loading circuit comprising: a first comparator which receives a first clock signal and a reverse-phase signal of the first clock signal, and outputs a second clock signal and a second reverse-phase clock signal, the second clock signal being in phase with the first clock signal, and the second reverse-phase clock signal having a reverse phase of the first clock signal; a second comparator having a non-inverting input terminal which receives the second clock signal and an inverting input terminal which receives the second reverse-phase clock signal; a third comparator having an inverting input terminal which receives the second clock signal and a non-inverting input terminal which receives the second reverse-phase signal; a fourth comparator which receives a data signal and a reverse-phase data signal having a reverse phase of the data signal, and which outputs a second data signal and a second reverse-phase data signal, the second data signal being in phase with the data signal, and the second reverse-phase data signal having a reverse phase of the data signal; a fifth comparator having a non-inverting input terminal which receives the second data signal and an inverting input terminal which receives the second reverse-phase data signal; a first latch circuit which loads a signal outputted from said fifth comparator, in accordance with a signal outputted from said second comparator; and a second latch circuit which loads the signal outputted from said fifth comparator, in accordance with a signal outputted from said third comparator.