Patent ID: 6885956
Filing Date: 2005-04-26
Classification: G11C

Abstract:
1. A semiconductor test apparatus which tests as a device under test a memory device whose memory area is divided into a plurality of blocks, comprising: a pattern generation block which generates a waveform control signal and an expected pattern signal as well as an address signal specifying a write address in the memory device; a waveform formatter/timing generator which outputs a test pattern signal whose waveform is formatted by the waveform control signal, and also outputs a write enable signal which enables writing of the test pattern signal into the test memory; a logic comparator which compares an output signal outputted from the memory device in response to the input test pattern signal with an expected pattern signal, detects a failure cell based on the expected pattern signal and the response output signal and outputs a fail signal, and also outputs an inhibit signal which instructs inhibition of writing into a memory area which is tested after the failure cell in a block in which the failure cell is detected; a failure analysis memory which stores the failure information at an address indicated by the address signal, and outputs a mask signal which instructs inhibition of writing into a block in which a failure cell is detected in advance; and an output controller which stops output of the write enable signal to the memory device when one or both of the inhibit signal and the mask signal are inputted, wherein the pattern generation block outputs a release signal which cancels the write inhibit instruction based on the inhibit signal and on the mask signal, and the output controller outputs the write enable signal when the release signal is inputted even if one or both of the inhibit signal and the mask signal are inputted.