Patent ID: 6104225
Filing Date: 2000-08-15
Classification: G11C,H03K,H03L

Abstract:
A semiconductor device supplied with first and second external clocks 180.degree. degrees out of phase with each other, from an external source, comprising:a first clock input circuit including a first 0.degree. phase adjusting circuit, supplied with said first external clock for outputting a first internal clock;a second clock input circuit including a second 0.degree. phase adjusting circuit, supplied with said second external clock for outputting a second internal clock;an internal circuit supplied with said first and second internal clocks;wherein said first 0.degree. phase adjusting circuit adjusts said first internal clock to be in phase with said first external clock; andwherein said second 0.degree. phase adjusting circuit adjusts said second internal clock to be in phase with said second external clock.