Patent ID: 8448124
Filing Date: 2013-05-21
Classification: G06F

Abstract:
1. A method, in a data processing system, for layout modification for performance, the method comprising: receiving an integrated circuit design; performing static timing analysis using a static timing analysis tool on the integrated circuit design; marking each gate in the integrated circuit design that is part of a hold critical path as hold critical; marking each gate in the integrated circuit design that is part of a setup critical path and not part of a hold critical path as setup critical; for each given gate marked as hold critical, performing layout modification on each given transistor in the given gate to degrade performance of the given transistor; for a first transistor in a first gate marked as setup critical, determining whether performing a layout modification to increase performance of the first transistor results in increasing performance for a second transistor in a second gate marked as hold critical; and responsive to a determination that performing the layout modification to increase performance of the first transistor does not result in increasing performance of the second transistor, performing the layout modification to increase performance of the first transistor.