Patent ID: 8697239
Filing Date: 2014-04-15
Classification: B24B,B24D,C08G,C08K,Y10T

Abstract:
1. A polishing pad suitable for polishing patterned semiconductor substrates containing at least one of copper, dielectric, barrier and tungsten, the polishing pad comprising a polymeric matrix, the polymeric matrix consisting of a polyurethane reaction product consisting of a polyol blend, a polyamine or polyamine mixture and toluene diisocyanate, the polyol blend being a mixture of 15 to 77 weight percent total polypropylene glycol and polytetramethylene ether glycol and the mixture of polypropylene glycol and polytetrarnethylene ether glycol having a weight ratio of the polypropylene glycol. to the polytetramethylene ether glycol from a 20 to 1 ratio to a 1 to 20 ratio, the polyamine or polyamine mixture being 8 to 50 weight percent in a liquid mixture, and the toluene diisocyanate being 20 to 30 weight percent total toluene diisocyanate monomer or partially reacted toluene diisocyanate monomer, all based on the total weight of the polymeric matrix.