Patent ID: 8476133
Filing Date: 2013-07-02
Classification: H01L

Abstract:
1. A method of manufacturing a trench transistor comprising: forming a first trench; forming a second trench, the first trench and the second trench defining a semiconductor mesa therebetween, a height of the semiconductor mesa defining a depth of the first trench and a depth of the second trench, the semiconductor mesa being of a first conductivity type; lining the first trench and the second trench with a gate dielectric material; substantially filling the gate dielectric-lined first trench and the gate dielectric-lined second trench with a conductive material, the conductive material forming a gate electrode of the trench transistor; forming a doped well in the semiconductor mesa, the doped well having a depth that is less than the depth of the first trench and less than the depth of the second trench, the doped well being of a second conductivity type that is opposite the first conductivity type; forming a source region within the doped well, the source region having a depth that is less than the depth of the doped well, the source region being of the first conductivity type; and forming a heavy body structure within the doped well, the heavy body structure including a region of the second conductivity type, a dopant of the second conductivity type in the region of the second conductivity type having a peak concentration at a peak concentration depth, the peak concentration depth being greater than the depth of the source region and less than the depth of the doped well.