Patent ID: 6486560
Filing Date: 2002-11-26
Classification: H01L

Abstract:
A semiconductor device having a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cuâ€”Ca/Cu) interconnect structure for reducing electromigration therein, comprising:a semiconductor substrate, the substrate having at least one via formed therein; and a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cuâ€”Ca/Cu) interconnect structure, said interconnect structure comprising: a Cu seed layer deposited in the at least one via; a contaminant-reduced calcium-doped copper (Cuâ€”Ca) alloy surface deposited on the Cu seed layer; and at least one Cu interconnect line deposited in the at least one via and over the contaminant-reduced Cuâ€”Ca alloy surface, the Cu seed layer comprising a plating treatment using a chemical solution for forming a Cuâ€”Caâ€”X conformal layer on the Cu seed layer, X comprising at least one contaminant, and the Cuâ€”Caâ€”X conformal layer comprising an annealing treatment for forming the contaminant-reduced Cuâ€”Ca alloy surface on the Cu seed layer and for facilitating forming the virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cuâ€”Ca/Cu) interconnect structure.