Patent ID: 9006742
Filing Date: 2015-04-14
Classification: H01L

Abstract:
1. A thin film transistor array panel comprising: a substrate; a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer; a first electrode disposed on the substrate; a gate insulating layer disposed on the gate conductor and the first electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; a passivation layer disposed on the source electrode and the drain electrode; and a second electrode disposed on the passivation layer, wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material, and wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO), and wherein the upper layer of the gate conductor comprises copper or a copper alloy.