Patent ID: 7141471
Filing Date: 2006-11-28
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a first conductive film over a semiconductor substrate and then forming a first insulating film made of a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film over said first conductive film; (b) performing etching of said first conductive film and said first insulating film, thereby forming a first gate electrodes in a first region of said semiconductor substrate and forming a second gate electrode in a second region of said semiconductor substrate; (c) forming a first MISFET having said first gate electrode in the first region of said semiconductor substrate; (d) forming a second insulating film made of a silicon nitride film over said first and second gate electrodes and said semiconductor substrate, and forming a third insulating film made of a silicon oxide film over said second insulating film; (e) forming a first sidewall insulating film comprised of said second and third insulating films on a sidewall of said second gate electrode, and then, forming a second MISFET having said second gate electrode in the second region of said semiconductor substrate; (f) forming a fourth insulating film made of a silicon oxide film over said third insulating film, and then, planarizing the upper surface of said fourth insulating film; (g) performing etching of said fourth, third, and second insulating films in the first region of said semiconductor substrate, thereby forming first openings above a source and drain of said first MISFET; (h) forming second sidewall insulating films made of a silicon oxide film on sidewalls of said first openings; (i) filling a second conductor layer into said first openings; (j) forming a fifth insulating film made of a silicon nitride film over said first and second MISFETs, and forming a sixth insulating film made of a silicon oxide film over said fifth insulating film; (k) forming second openings in said sixth and fifth insulating films so as to be located at positions above one of the source and drain of said first MISFET, thereby exposing said second conductor layer at the bottom of said second openings; and (l) filling a third conductor layer into said second openings so as to be electrically connected to said second conductor layers in said second openings, wherein said step (h) includes the steps of: (h-1) forming said silicon oxide film over said fourth insulating film and in said first openings; and (h-2) performing anisotropic etching of said silicon oxide film, thereby forming said second sidewall insulating films made of said silicon oxide film on the respective sidewalls of said first openings, wherein third openings are formed above the source and drain of said second MISFET when forming said second openings in said step (k), and a fourth conductor layer is filled into said third openings when filling the third conductor layer into said second openings in said step (l), and wherein, after said step (l), the method further comprises the step of: (m) over said sixth insulating film, forming a first wiring electrically connected to said third conductor layer in said second opening and forming a second wiring electrically connected to said fourth conductor layer in said third openings.