Patent ID: 6060911
Filing Date: 2000-05-09
Classification: H01L

Abstract:
A circuit arrangement comprising:at least first, second, third and fourth transistors;each of the transistors being a vertical MOS transistors;the first transistor and the fourth transistor being complementary to the second transistor and to the third transistor;the first transistor and the fourth transistor connected in series and between a first voltage terminal and an output voltage terminal;the second transistor and the third transistor connected in parallel and between the output voltage terminal and a second voltage terminal;a gate electrode of the third transistor and a gate electrode of the fourth transistor connected with a first input voltage terminal;a gate electrode of the first transistor and a gate electrode of the second transistor connected with a second input voltage terminal;at least first, second, third and fourth layer structures, the layer structures having channel layers of the transistors and at least one source/drain region of each transistor;the layer structures having edges to which the channel layers are adjacent, and that are provided, at least in a region of the channel layers, with a gate dielectric to which the gate electrodes of the transistors are adjacent;the channel layer of the first transistor and the channel layer of the fourth transistor being located at a common level;the channel layer of the second transistor and the channel layer of the third transistor being located at a common level;the channel layer of the first transistor and the channel layer of the second transistor being located at different levels.