Patent ID: 6249560
Filing Date: 2001-06-19
Classification: H03L

Abstract:
A PLL circuit comprising:voltage control oscillation means for generating and outputting a signal of a frequency corresponding to an input control voltage;frequency dividing means triggered by any of a rising edge and falling edge of an output signal of said voltage control oscillation means, for dividing said output signal of said voltage control oscillation means;a flip-flop connected to an inverter, said flip-flop triggered by one, that is not used as a trigger of said frequency dividing means, of said rising edge and falling edge of said output signal of said voltage control oscillation means for receiving and outputting said output signal of said frequency dividing means;reference clock generation means for generating a reference clock of reference frequency; andphase comparison means for outputting a voltage corresponding to a phase difference between an output signal of said flip-flop and said reference clock.