Patent ID: 8281101
Filing Date: 2012-10-02
Classification: G11C

Abstract:
1. A method for improved access to a Dynamic Random Access Memory (DRAM), the method comprising: issuing a write Column Address Strobe (CAS) address to the DRAM to latch a valid write CAS address for accessing the DRAM; asserting a set of write data values to be stored in a first set of DRAM locations corresponding to the write CAS address; issuing a read CAS address to the DRAM to indicate a valid read CAS address, after asserting the write CAS address and prior to asserting the set of write data values; and receiving a set of read data values from a second set of DRAM locations corresponding to the read CAS address, after asserting the set of write data values; and wherein issuing the read CAS address to the DRAM occurs at least 4 clock cycles after receiving an external write CAS signal corresponding to the write CAS address and occurs no later than a particular clock cycle when a last write data value of the set of write data values to be stored is buffered.