Patent ID: 7339235
Filing Date: 2008-03-04
Classification: B82Y,H01L

Abstract:
1. A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the first or second impurity regions have dot patterns.