Patent ID: 6075734
Filing Date: 2000-06-13
Classification: G11C

Abstract:
A multi-bit integrated circuit memory device comprising:a word line;a bit line;a memory cell arranged at an intersection of the word line and the bit line;a bit line precharge circuit responsive to a bit line precharge signal, for providing the bit line with a predetermined current during respective bit line precharge and sensing periods of a multi-bit data read operation;a bit line pass transistor having a gate and connected between the bit line precharge circuit and the bit line, for transferring the current from the bit line precharge circuit onto the bit line; anda bias voltage supplying circuit for supplying the gate of the bit line pass transistor with a bias voltage during the data reading operation, wherein the bias voltage supplying circuit reduces a voltage level on the gate of the bit line pass transistor during a bit line discharge period of a read-out interval of a multi-bit read operation.