Patent ID: 6366493
Filing Date: 2002-04-02
Classification: G11C,H01L

Abstract:
A four-transistors SRAM cell, comprising:a first word line terminal which is coupled to a first word line; a second word line terminal which is coupled to second word line, wherein said first word line terminal and said second word line terminal are controlled separately; a first bit line terminal which is coupled to a first bit-line; a second bit line terminal which is coupled to a second bit-line; a first transistor, wherein the gate of said first transistor is coupled to said first word line terminal and the source of said first transistor is coupled to said first bit line terminal; a second transistor, wherein the gate of said second transistor is coupled to said second word line terminal and the source of said second transistor is coupled to said second bit line terminal; a third transistor, wherein the source of said third transistor is coupled to the drain of said first transistor and the gate of said third transistor is coupled to the drain of said second transistor; and a fourth transistor, wherein the source of said fourth transistor is coupled to the drain of said second transistor and the gate of said fourth transistor is coupled to the drain of said first transistor.