Patent ID: 6546530
Filing Date: 2003-04-08
Classification: G01R,H03K

Abstract:
Circuitry in an integrated circuit for linearly delaying a signal comprising:a plurality of control signals; a fine delay element coupled to at least one of said plurality of control signals, wherein said fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of said signal, at least one course delay element coupled to said fine delay element, wherein said at least one course delay element is coupled to at least one of said plurality of control signals, wherein said at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of said signal; wherein said fine delay element and said at least one course delay element are configured to provide linear delay steps; and wherein said logic circuitry of said fine delay element and said at least one course delay element each comprise a plurality of transmission gates, a plurality of inverters and at least one dummy load.