Patent ID: 6066558
Filing Date: 2000-05-23
Classification: H01L

Abstract:
A multilevel interconnection forming method for a semiconductor device, comprising steps of:depositing a metal film containing aluminum on an insulating film of a substrate and patterning the metal film, to form a wiring layer of a first layer;forming an interlayer dielectric film forming part of the first layer, on an entire surface of the substrate, such that the interlayer dielectric film covers an upper surface of the wiring layer;forming a hole at a position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer;selectively depositing and filling aluminum into the hole by a CVD method at a processing temperature of 250.degree. C. or lower, such that the aluminum is filled at a volume ratio equal to or larger than 50% and smaller than 100% with respect to the hole;forming a foundation metal film on an entire upper surface of an interlayer dielectric film including the hole filled with thin aluminum at a processing temperature of 100.degree. C. or lower, to have a thickness within a range between 10 .ANG. and 400 .ANG.;forming a metal layer containing aluminum, on the foundation metal film at a processing temperature of 250.degree. C. or lower;making the metal layer flow into the hole by reflowing, to completely fill the hole and to planarize the surface of the metal layer; andsubjecting the metal layer to patterning, to form a wiring layer of a second layer, after the surface of the metal layer is planarized by the reflowing.