Patent ID: 8093104
Filing Date: 2012-01-10
Classification: H01L

Abstract:
1. A multi-chip stacking method to reduce voids between stacked chips comprising: providing a substrate having a top surface and a plurality of bonding fingers; disposing a first chip on the substrate by an adhesive, wherein the first chip has a first active surface, a first back surface, and a plurality of first bonding pads disposed on the first active surface, the adhesive adheres the first back surface of the first chip to the top surface of the substrate; thermally curing the adhesive; forming a plurality of first bonding wires by wire-bonding to electrically connect the first bonding pads to the bonding fingers; disposing the second chip on the first active surface of the first chip by a FOW adhesive, wherein the second chip has a second active surface, a second back surface, and a plurality of second bonding pads disposed on the second active surface, wherein the FOW adhesive is formed on an dielectric layer attached onto the second back surface of the second chip, and the FOW adhesive encapsulates a plurality of loop-height sections of the first bonding wires above the first active surface and is attached to the first active surface of the first chip; and placing the substrate inside a pressure oven and thermally curing the FOW adhesive with exerted pressures to provide a positive pressure greater than one atm exerted on the FOW adhesive to reduce bubbles trapped inside the FOW adhesive.