Patent ID: 6907586
Filing Date: 2005-06-14
Classification: G06F

Abstract:
1. A method of integrated circuit design comprising steps of: a) providing a design of an integrated circuit; b) calculating a crosstalk overhead for each path between register pairs in said design; c) identifying paths between register pairs having a path delay exceeding a specified acceptable maximum path delay; and d) redesigning any identified paths between register pairs such that redesigned paths have a path delay less than said maximum path delay wherein said crosstalk overhead in calculated in stop b) using a stochastic model comprising steps of: i) providing a plurality of completed integrated circuit designs for analysis; ii) selecting one of said completed integrated circuit designs; iii) selecting a metal wiring layer of said selected completed integrated circuit design; iv) finding a net crosstalk maximum length for said selected metal wiring layer; v) repeating steps iii) and iv) until each metal wiring layer of said selected completed integrated circuit design is analyzed; vi) repeating steps ii) through v) until each completed integrated circuit design has been analyzed, results of said analysis being stored for subsequent analysis; and vii) building said stochastic model, said stochastic model being a net crosstalk maximum length model.