Patent ID: 6278635
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the source/drain area via a gate insulating film, and a control gate formed on said floating gate via an interlayer insulating film, the method comprising steps of:applying a predetermined positive voltage to a bit line connected to said drain area and a word line connected to said control gate, injecting an electron to said floating gate, and writing data to a selected memory cell;applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to said semiconductor substrate or said source area, discharging the electron accumulated in said floating gate of said selected memory cell, and performing data erasing; andafter the data erasing, applying the predetermined positive voltage necessary for injecting the electron to said floating gate from a channel area in the vicinity of said source area to said common source line, and performing write-back of said memory cell erased excessively.