Patent ID: 8173532
Filing Date: 2012-05-08
Classification: H01L,Y10S

Abstract:
1. A semiconductor structure fabrication method, comprising: providing a semiconductor structure which includes a semiconductor substrate, wherein the semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, and wherein the semiconductor substrate further includes a first semiconductor body region and a second semiconductor body region; depositing a silicone nitride layer consisting of silicon nitride on and in direct physical contact with the semiconductor substrate; patterning the silicon nitride layer resulting in formation of a first gate divider region and a second gate divider region on top of the semiconductor substrate, wherein the first gate divider region and the second gate divider region each consists of silicon nitride and is in direct physical contact with a shallow trench isolation (STI) region in the semiconductor substrate, and wherein said patterning the silicon nitride layer has removed silicon nitride of the silicon nitride layer such that a surrounding ambient separates the first gate divider region and the second gate divider region from each other; after said patterning the silicon nitride layer, forming a gate electrode layer on top of the semiconductor substrate, wherein the first gate divider region and the second gate divider region are each in direct physical contact with the gate electrode layer; and after said forming the gate electrode layer, patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region being formed.