Patent ID: 6762094
Filing Date: 2004-07-13
Classification: B82Y,G03F,H01L,Y10S,Y10T

Abstract:
A method for forming nanoscale semiconductor junctions comprising:creating an epitaxial semiconducting layer including a dopant of a first polarity formed on a semiconductor substrate having a dopant of a second polarity; creating an imprint layer on said epitaxial semiconducting layer; urging a nanoimprinter toward said imprint layer; removing selective portions of said epitaxial semiconducting layer forming an epitaxial semiconducting structure having an area with at least one lateral dimension less than about 75 nanometers; creating a dielectric layer over said epitaxial semiconducting structure; planarizing said dielectric layer to substantially the same thickness as said epitaxial semiconducting structure; creating a polycrystalline semiconducting layer including a dopant of said second polarity over said epitaxial semiconducting layer and said dielectric layer; removing selective portions of said polycrystalline semiconducting layer, and forming a polycrystalline semiconducting structure having an area with at least one lateral dimension less than about 75 nanometers.