Patent ID: 7205635
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A wafer scale semiconductor integrated circuit structure comprising: a semiconductor wafer that is subdivided into a plurality of integrated circuit die regions, each integrated circuit die region including an integrated circuit structure that is formed on an upper surface of the semiconductor wafer and that includes a plurality of spaced-apart conductive die bond pads arranged in a pattern; a unitary, substantially planar solid glass sheet having substantially the same size as the semiconductor wafer and having a plurality of prefabricated holes formed therethrough from an upper surface of the solid glass sheet to a lower surface of the solid glass sheet, the prefabricated holes being formed to provide a plurality of hole patterns, each hole pattern corresponding to a pattern of die bond pads formed in a corresponding integrated circuit die region of the semiconductor wafer, each prefabricated hole formed in the solid glass sheet having an associated conductive bond pad formed on the upper surface of the solid glass sheet; adhesive material disposed between the upper surface of the semiconductor wafer and the lower surface of the solid glass sheet to affix the solid glass sheet to the semiconductor wafer such that each hole pattern in the solid glass sheet is associated with a corresponding pattern of die bond pads; for each conductive bond pad formed on the upper surface of the solid glass sheet, conductive material formed in electrical contact with said conductive bond pad and extended through the associated hole in the solid glass sheet and into electrical contact with the associated die bond pad; a trench matrix formed through the glass sheet, the adhesive material and into the upper surface of semiconductor wafer to extend around the perimeter of each integrated circuit die region; and hermetic material deposited in the trench matrix to form a hermetic seal over the interface between the glass sheet, the adhesive material and each integrated circuit die region.