Patent ID: 7639059
Filing Date: 2009-12-29
Classification: H03K

Abstract:
1. A reference voltage buffer circuit ( 20 ) comprising: a first transistor (M a second transistor (M first and second resistors (R a first boost circuit for generating a positive boosted voltage (Vdd a second boost circuit for generating a negative boosted voltage (Vss third and fourth transistors (M a first error amplifier having a non-inverting input terminal coupled to receive a first reference voltage (Vrp fifth and sixth transistors (M a second error amplifier having a non-inverting input terminal coupled to receive a second reference voltage (Vrn wherein the fourth and sixth transistors generate the first and second control voltages respectively for the first and second transistors and the third transistor and the fifth transistors are biased to supply current to the first current handling terminals of the fourth and sixth transistors, respectively, to maintain the first and second control voltages.