Patent ID: 8440569
Filing Date: 2013-05-14
Classification: H01L

Abstract:
1. A method of semiconductor device fabrication, comprising: depositing a layer of a first material onto a substrate; using a single mask during a single mask process to pattern the layer to form a first pattern defining a wide space feature and a narrow space feature in the same mask layer, the narrow space feature defining a line of a semiconductor device and the wide space feature defining a logic device component of the semiconductor device, the wide space feature and the narrow space feature being defined by adjacent shapes in the first pattern; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern that define the narrow space feature and the wide space feature, the spacer material thereby forming the narrow space feature and the wide space feature; depositing additional first material onto the substrate after said etching; and planarizing a surface of the device after said additional depositing.