Patent ID: 9164769
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A reconfigurable array comprising: a processing core including a plurality of processing elements that each have a respective local register file, the processing core configured to execute instructions in a first execution mode and a second execution mode; a central register file configured to store data related to the instructions; and a controller configured to control conversion between the first execution mode and the second execution mode of the processing core, and copy data to be used in the second execution mode from among the data stored in the central register file to the local register files, in response to a request for conversion from the first execution mode to the second execution mode, wherein the controller is configured to analyze a data flow graph representing an execution sequence of the instructions to detect the data to be used in the second execution mode, wherein in the first execution mode, the processing core is configured to read data in the central register file using at least one of the plurality of processing elements and to execute the instructions using the data from the central register files, and in the second execution mode, the processing core is configured to read data in the local register file using at least one of the plurality of processing elements and to execute the instructions using the data from the local register file.