Patent ID: 6728912
Filing Date: 2004-04-27
Classification: G11C

Abstract:
A method for testing SOI technology memory circuits for weak SOI cells comprising the steps of:causing a selected circuit of an integrated SOI memory array circuit having a plurality of memory cells, each memory cell having a word select path and a bit select path to activate a reset path test circuit having a word select path and a bit select path which provide independent timed paths and having a pass gate multiplexer and a clock to reset the circuits being tested at the end of each clock cycle to test the SOI memory array memory cells by selectively changing signals passing through said reset path test circuit to provide for a memory cell being tested a wordline pulse width signal for a word select path with a reduced time while bit path select and write signals for said memory cell being tested turn off at normal times to stress the write margin of said memory cell being tested.