Patent ID: 7877524
Filing Date: 2011-01-25
Classification: G06F

Abstract:
1. A direct memory access (DMA) system, comprising at least one physical memory space for storing a fragmented physical buffer comprising arbitrarily aligned and arbitrarily sized memory fragments defined by a scatter/gather list (SGL); a DMA master to create a DMA descriptor requesting transfer of data to or from the fragmented physical buffer, the fragmented physical buffer being represented as a contiguous logical address space wherein each of the fragments is mapped to contiguous logical offset addresses; a DMA engine to process the DMA descriptor, and associated with logical to physical address translation logic to determine a physical address corresponding to a logical offset address of one of a fragments by accessing an SGL element associated with the fragment to determine a physical start address for the fragment, and offsetting the physical start address by the logical offset address less the length of preceding fragments listed in the SGL.