Patent ID: 7732264
Filing Date: 2010-06-08
Classification: H01L,Y10S

Abstract:
1. A fabrication method of a thin film transistor (TFT) array substrate, comprising: forming a first conductive layer on a substrate; performing a first mask process to pattern the first conductive layer, thereby forming a contact pad, a gate line, a gate electrode and a lower electrode of a capacitor; forming a stack covering the substrate, the contact pad, the gate line, the gate electrode and the lower electrode of the capacitor, wherein the stack includes a gate dielectric layer, a semiconductor layer and an ohmic contact layer; performing a second mask process to pattern the stack, thereby exposing the substrate and forming a first opening exposing the contact pad; forming a first transparent conductive layer covering the substrate, the stack and the exposed contact pad; forming a second conductive layer covering the first transparent conductive layer; performing a third mask process to form a data line perpendicular to the gate line, source and drain regions overlying the gate electrode, a pixel electrode in a pixel area of the substrate, an upper electrode of the capacitor overlying the lower electrode of the capacitor, a contact pad electrode overlying the contact pad, and a second opening exposing the semiconductor layer and separating the source and drain regions, wherein the drain region is electrically connected to the pixel electrode, the source region is electrically connected to the data line, and the upper electrode of the capacitor is electrically connected to the pixel electrode, wherein the third mask process comprises: forming a passivation layer covering the overall substrate; and performing a laser ablation process to pattern the passivation layer, thereby forming third and fourth openings exposing a portion of the first transparent conductive layer.