Patent ID: 6072744
Filing Date: 2000-06-06
Classification: G11C

Abstract:
A memory device having a first group to a fourth group of internal data pads being arranged according to a pin configuration of a package, comprising:a first bank;a second bank adjacent to the first bank;a third bank facing with the first bank;a fourth bank facing with the second bank; the first to fourth banks having a first to fourth block, respectively, and the position of blocks are the same in the respective banks;a first to fourth sets of data bus lines downwardly arranged in turn from the first and second bank at an area between the first and the second bank and the third and the fourth bank;the first set of data bus lines extended from the first block of the first bank to the first block of the second bank and arranged in order to share data input/output to/from the first block of the first to the fourth bank, respectively;the second set of data bus lines extended from the second block of the first bank to the second block of the second bank and arranged in order to share data input/output to/from the second block of the first to the fourth bank, respectively;the third set of data bus lines extended from the third block of the first bank to the third block of the second bank and arranged in order to share data input/output to/from the third block of the first to the fourth bank, respectively; andthe fourth set of data bus lines extended from the fourth block of the first bank to the fourth block of the second bank and arranged in order to share data input/output to/from the fourth block of the first to the fourth bank, respectively.