Patent ID: 9170969
Filing Date: 2015-10-27
Classification: G06F

Abstract:
1. A device comprising: a processor; a plurality of management data input/output (MDIO)/management data clock (MDC) interfaces to which the processor are not directly connected; a plurality of Ethernet physical sublayer (PHY) devices, one or more Ethernet PHY devices of the Ethernet PHY devices connected to each MDIO/MDC interface, each Ethernet PHY device to provide PHY register data directly onto the MDIO/MDC interface to which the Ethernet PHY device is connected; a plurality of MDIO/MDC controllers separate from the processor, each MDIO/MDC controller connected to and to poll a corresponding MDIO/MDC interface of the MDIO/MDC interfaces to receive the PHY register data from the one or more Ethernet PHY devices connected to the corresponding MDIO/MDC interface; a memory to which the MDIO/MDC controllers are to store portions of the PHY register data received from the Ethernet PHY devices; and an interface separate from the MDIO/MDC interfaces and connecting the memory to the processor, the processor accessing the portions of the PHY register data stored to the memory to retrieve the PHY register data without having to poll the Ethernet PHY devices itself via the MDIO/MDC interfaces, wherein the MDIO/MDC controllers are indirectly and not directly connected to the processor, via the MDIO/MDC controllers being directly connected to the memory, the memory being directly connected to the interface, and the interface being directly connected to the processor, and wherein each MDIO/MDC controller is to, responsive to receiving the PHY register data from the one or more Ethernet PHY devices connected to the corresponding MDIO/MDC interface, extract management information regarding the one or more Ethernet PHY devices from the PHY register data, and is to store the management information on the memory as the portions of the PHY register data.