Patent ID: 6757763
Filing Date: 2004-06-29
Classification: G06F

Abstract:
A bus interface system for interfacing between a first bus and a second bus, comprising:a transmit multiplexer coupled to the first bus; a plurality of transmit channels multiplexed by the transmit multiplexer to transmit data to said first bus, said plurality of transmit channels each including a transmit block having at least one dedicated transmit FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus; a receive multiplexer coupled to the first bus; and a plurality of receive channels multiplexed by the receive multiplexer to receive data from said first bus, said plurality of receive channels each including a receive block having at least one dedicated receive FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus; wherein at least one of said transmit block and receive block includes a control state machine.