Patent ID: 9092023
Filing Date: 2015-07-28
Classification: G05B

Abstract:
1. An industrial controller comprising: a multicore electronic computer having a first processor, a second processor, a first cache, and a second cache, wherein the first cache corresponds to the first processor and the second cache corresponds to the second processor; a dedicated communication interface between and accessible only by the first processor and the second processor; a shared electronic memory loadable into the first cache and the second cache for access by the first and second processors; and a steering circuit for monitoring memory access attempts of the first cache by the first processor, wherein: the steering circuit determines whether each memory access attempt corresponds to a predefined portion of the shared electronic memory and when the memory access attempt corresponds to the predefined portion of the shared electronic memory, the steering circuit connects the first processor to the second cache, the first processor interrupts execution of the second processor via the dedicated communication interface prior to initiating a memory access attempt within the predefined portion of the shared electronic memory, and the first processor restarts execution of the second processor via the dedicated communication interface after the first processor accesses the second cache.