Patent ID: 8301829
Filing Date: 2012-10-30
Classification: G06F

Abstract:
1. A flash memory device comprising: a flash memory including a first plurality of pages, each page being divided into a first main region and a first spare region; a buffer memory for temporarily storing data to be written in the flash memory or data to be read from the flash memory, the buffer memory including a second plurality of pages being divided into a second main region and a second spare region; a register configured to store an address of the flash memory, an address of the buffer memory, and an operation command of the flash memory and the buffer memory; and a control circuit including a buffer controller configured to control read or write operations of the buffer memory, and a decoder to map an address applied from the buffer controller, wherein the decoder separates an address input to the buffer memory into the second main region and the second spare region, the control circuit configured to (a) convert a control signal, an address and data from a host into an internal signal for operating the flash memory device, (b) map an address from the host to a mapped address of the buffer memory, in response to the internal signal, the addresses stored in the register, and the operation command stored in the register, and (c) control data stored in the mapped address of the buffer memory to be stored in the flash memory or control control the data of the flash memory to be stored in the mapped address of the buffer memory, wherein the first main region and the second main region have a first capacity and the first spare region and the second spare region have a second capacity, the first capacity being greater than the second capacity, and each page in the flash memory and in the buffer memory having equal capacity.