Patent ID: 6335644
Filing Date: 2002-01-01
Classification: H03L

Abstract:
A method for synthesizing a clock signal, said clock signal being locked to a reference clock signal having a reference clock signal frequency, said method using a further clock signal operating at a further clock signal frequency higher than said reference clock signal frequency, wherein the method comprises the steps of:dividing the reference clock signal frequency by a division factor and obtaining a divided clock signal having a divided clock signal frequency; comparing said divided clock signal frequency with said further clock signal frequency and obtaining a measured value of the reference clock signal frequency, said further clock signal being asynchronous with respect to the reference clock signal and having a much higher frequency with respect to said divided clock signal; comparing said measured value with a nominal value; obtaining a correction value as a function of the measured value and storing said correction value; and controlling a digital controlled oscillator that outputs the synthesized clock signal in accordance with said correction value.