Patent ID: 7783692
Filing Date: 2010-08-24
Classification: G06F

Abstract:
1. A method comprising: receiving, in a processor core, data to be shifted, wherein the data includes a first plurality of bits; receiving a shift count value including a second plurality of bits, wherein the shift count value represents a number of bit positions the data is to be shifted; receiving an indication of a direction the data is to be shifted; determining, by way of circuitry within the processor core, a bit position of a flag bit within the first plurality of bits based on the shift count value and the direction, wherein, when the data is to be shifted in a leftward direction, the bit position of the flag bit is determined by inverting the second plurality of bits of the shift count and adding a value of binary 1, and wherein, when the data is to be shifted a rightward direction, the bit position of the flag bit is determined by subtracting a value of binary 1 from the shift count value; and outputting the flag bit.