Patent ID: 7243274
Filing Date: 2007-07-10
Classification: G11C

Abstract:
1. A semiconductor device comprising first and second memory chips and a logic chip having a logic circuit that controls said first and second memory chips mounted in a single package, wherein said logic circuit includes: an external terminal for receiving an external signal to access the memory cells of said first and second memory chips; a test starting terminal for receiving a test starting signal activated when one of said first and second memory chips is tested and inactivated when said first and second memory chips are normally operated; an access signal generator for receiving the external signal supplied to the external terminal in order to access the memory cell of the first memory chip, and for converting said received external signal to a memory access signal in order to match the external signal with the interface of said first memory chip; and a first selector for selecting said external signal, the external signal being a test signal, during the activation of said test starting signal, for selecting said memory access signal during the inactivation of said test starting signal, and for outputting the selected signal to said first memory chip.