Patent ID: 7174426
Filing Date: 2007-02-06
Classification: G06F

Abstract:
1. A method for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments and is accessed by a plurality of competing requests via a number of commonly used input address registers, wherein a cache segment model is utilized for reflecting the cache use by said competing requests, wherein cache memory requests are processed by a processing pipe and wherein each cache-request, before entering the processing pipe, is checked whether the segments of the cache memory are available at the cycle they are needed, said method comprising the steps of: a) marking a segment model cell as busy with storing, when a store-request targeting to a cache segment corresponding to said model cell has received pipe access; b) blocking off from pipe access a fetch-request targeting to a segment model cell, which is marked busy with a store-operation; and c) blocking off a store-request from pipe access, if at least one fetch-request, which was blocked off from pipe access according to step b), is waiting for pipe access.