Patent ID: 6620663
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of fabricating an RF lateral MOS device, comprising the steps of:providing a substrate having a gate oxide layer formed thereover; forming a first layer of polysilicon over the gate oxide layer; forming a second layer of material over the polysilicon layer; patterning the polysilicon and the second layer of material to form a gate having exposed sidewalls, the gate having a lower patterned polysilicon layer and an upper patterned second material layer; forming sidewall spacers on the exposed sidewalls of the gate; forming a source/drain contacts adjacent to the sidewall spacers; removing the upper patterned second material layer of the gate to form a cavity above the patterned polysilicon layer and between the sidewall spacers; forming a source trench through the gate oxide layer and into the substrate adjacent the gate; forming a blanket conductive layer over the substrate; and planarizing the blanket conductive layer to simultaneously form: a) a plug within the cavity; b) a source plug portion within the source trench; and c) a drain plug portion overlying the drain region.