Patent ID: 6777801
Filing Date: 2004-08-17
Classification: H01L

Abstract:
A semiconductor device comprising:a first semiconductor chip having memory cells in a predetermined area of a surface of the first semiconductor chip; and a second semiconductor chip having a size smaller than the first semiconductor chip, the first semiconductor chip including a plurality of first pad electrodes and a plurality of second pad electrodes placed over the surface of the first semiconductor chip, the first and second pad electrodes being respectively electrically connected to a circuit provided in the first semiconductor chip, the second semiconductor chip including a plurality of third pad electrodes, the third pad electrodes being respectively electrically connected to another circuit provided in the second semiconductor chip, wherein each of the first pad electrodes are used for external connection, each of the second pad electrodes are electrically connected to corresponding ones of the third pad electrodes via wires, and wherein the second semiconductor chip is placed on the first semiconductor chip above the predetermined area to cover the predetermined area.