Patent ID: 6263098
Filing Date: 2001-07-17
Classification: G01R,G06F

Abstract:
A method for determining the functionality of circuitry contained in an IC module from images presented across the module on a plurality of planar layers that are consecutively exposed by etching, with each exposed layer being individually imaged prior to the subsequent layer being etched, comprising the steps of:mounting the circuitry on a moveable table with its exposed layer registered relative to table movement and to a signal generating microscope;moving the table relative to the microscope in fixed step increments;imaging an incremental portion of the layer with the microscope at each table step;time integrating the image signal of each incremental portion of the layer to improve the signal-to-noise ratio;storing the time integrated image signal for each incremental portion of the layer;compiling the stored time integrated image signals of the incremental portions to derive a pixel representation for the total image displayed on the layer;segmenting the pixel representation into blocks which are configured to represent the formations of various materials on the layer;storing the block configurations for each layer;compiling the block configurations for all of the layers in their order of etching to derive a comprehensive mask description of the circuitry;generating a netlist from the comprehensive mask description, which includes all the components in the circuitry and the interconnections existing therebetween;compiling the determination of functionality from conventional combinations of the components on the netlist; andtranslating the determination of functionality into a desired language.