Patent ID: 6399435
Filing Date: 2002-06-04
Classification: H01L

Abstract:
A method for fabricating a DRAM memory cell having a trench capacitor, which comprises the steps of:producing a first trench in a first zone of a first conductivity type, coating the surface of the first trench with a first insulator layer and filling the first trench with a conductive material of a second conductivity type, the first zone and the conductive material in the first trench being highly doped; arranging a second zone of the first conductivity type on the first zone, so that the first trench is covered; producing a region of the second conductivity type in the second zone by diffusion of dopant from the conductive material in the first trench; etching adjacent regions next to the first trench, so that semiconductor material is removed proceeding from the surface of the second zone right into the first zone; filling the adjacent regions with an insulator material, so that an insulator region is produced between adjacent trenches; producing bit lines made of the conductive material of the second conductivity type and drain zones for selection transistors on the surface of the second zone; producing the selection transistor in a second trench in the second zone above the first trench in the first zone; and producing word lines made of the conductive material on the uncovered surface of the second zone.