Patent ID: 6625076
Filing Date: 2003-09-23
Classification: G11C

Abstract:
A circuit configuration for evaluating an information content of a magnetoresistive random access memory (MRAM) memory cell, the circuit configuration comprising:a ground terminal; a line connected to the MRAM memory cell; a first component selected from the group consisting of a resistor and a transistor connected as a diode, said first component having a first terminal connected to said ground terminal and a second terminal; a second component selected from the group consisting of a resistor and a transistor connected as a diode, said second component having a first terminal connected to said ground terminal and a second terminal, said first component and said second component being dimensioned differently from each other in order to obtain an asymmetry between said first and second components; a first circuit branch having a first switch with a first terminal and a second terminal, said first terminal of said first switch connected to first component; a second circuit branch having a second switch with a first terminal and a second terminal, said first terminal of said second switch connected to said second component; a third switch having a first terminal connected to said line and a second terminal connected to said second terminal of said first component; a fourth switch having a first terminal connected to said line and a second terminal connected to said second terminal of said second component; an evaluation unit connected to said second terminal of said first switch and to said second terminal of said second switch; a first capacitor connected between said second terminal of said first switch and said ground terminal, said first capacitor functioning as a first buffer store for storing a first value measured from the MRAM memory cell and the first value being selected from the group consisting of a first current value and a first voltage value corresponding to the first current value, and after the first value is buffered stored, the MRAM memory cell is sub-sequently subjected to a programming operation; and a second capacitor connected between said second terminal of said second switch and said ground terminal, said second capacitor functioning as a second buffer store for storing a second value measured from the MRAM memory cell and the second value being selected from the group consisting of a second current value and a second voltage value corresponding to the second current value, the first value and the second value then being compared with one another in said evaluation unit.