Patent ID: 6294449
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method of forming an integrated circuit comprising the steps of:preparing a substrate;forming a set of transistors including at least one transistor pair separated by a contact region on said substrate, said transistors containing a gate, source sidewalls, drain sidewalls and a cap layer;depositing a dielectric layer over said transistors;etching a contact aperture through said dielectric layer between said pair of transistors, stopping on said cap layer, whereby a remainder portion of said dielectric layer and of said cap layer remains in said aperture and a shoulder portion of said cap layer is exposed on facing shoulders of said transistor pair;removing said exposed shoulder portion of said cap layer, thereby exposing a shoulder portion of said gate;removing said remainder portion of said dielectric;oxidizing said shoulder portion of said gate;removing said remainder portion of said cap layer and a corresponding amount of gate oxide beneath said remainder portion of said cap layer, thereby exposing said substrate in said contact region;forming a contact in said contact aperture; andcompleting said integrated circuit.