Patent ID: 8984459
Filing Date: 2015-03-17
Classification: G06F,Y02P

Abstract:
1. A method performed by a computer for comparing a first layout with a second layout, comprising: receiving, by an input device of a computer, a first input corresponding to a first layout of an integrated circuit (IC), wherein the first layout comprises a first basic layout element; receiving, by the input device of the computer, a second input corresponding to a second layout of the IC, wherein the second layout comprises a second basic layout element; forming, by a processor of the computer, a first trace of the first basic layout element, and a second trace of the second basic layout element, wherein the first trace is a first description that uniquely identifies the first basic layout element and its location, and the second trace is a second description that uniquely identifies the second basic layout element and its location; generating, by the processor of the computer, a first trace signature using at least a hashed trace value of the first trace and a circumference of the first basic layout element, the first trace signature identifying the first basic layout element; generating, by the processor of the computer, a first input signature from at least the first trace signature, the first input signature identifying the first input; generating, by the processor of the computer, a second trace signature using at least a hashed trace value of the second trace and a circumference of the second basic layout element, the second trace signature identifying the second basic layout element; generating, by the processor of the computer, a second input signature from at least the second trace signature, the second input signature identifying the second input; comparing, by the processor of the computer, the first input signature and the second input signature to determine whether the first layout is same as the second layout; and producing, by an output device of the computer, an output.