Patent ID: 8953402
Filing Date: 2015-02-10
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a plurality of sense amplifiers, each of the sense amplifiers amplifying a difference in potential between a pair of bit lines, the sense amplifiers having a plurality of first transistors and a plurality of second transistors, the first transistors being formed in a first sense amplifier region and the second transistors being formed in a second amplifier region; a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of the sense amplifier drivers having a first driver transistor and a second driver transistor, the first driver transistor having a different conductivity type from the second driver transistor, the first driver transistor and the second driver transistor being alternately arranged in a first direction (Y direction) between the first sense amplifier region and the second sense amplifier region, and an element separation boundary arranged between the first driver transistor and the second driver transistor, wherein the first driver transistor is formed in a first region between the first sense amplifier region and the second sense amplifier region, wherein the second driver transistor is formed in a second region across a third region from the first region, wherein in the third region, the element separation boundary is arranged in a second direction (X direction) which is different from the first direction.