Patent ID: 6518737
Filing Date: 2003-02-11
Classification: G05F

Abstract:
A low dropout voltage regulator comprising:a first operational transconductance amplifier (OTA) 102 having an inverting input 16, a non-inverting input 20 and an output 21, the inverting input being coupled to a voltage reference circuit 14, the non-inverting input being coupled to a feedback network R1 R2, the first OTA being configured to operate as an error amplifier; a second OTA 104 having an inverting input 23, a non-inverting input 21 and an output 23, the non-inverting input being coupled to the output of the first OTA, the output of the second OTA being coupled to the inverting input of the second OTA to form a voltage follower; a power p-channel metal oxide semiconductor (PMOS) transistor 24 having a source terminal 12, a drain terminal 26 and a gate terminal 23, the source terminal being coupled to an input voltage terminal 12, the gate terminal being coupled to the output of the second OTA, the drain terminal being coupled to an output voltage terminal 26; and the feedback network comprising a first resistor R1, a second resistor R2 and a frequency C1 compensation capacitor, the first and second resistors being coupled in series between the output voltage terminal and a ground terminal 28, the non-inverting input of the first OTA being coupled to a first node N1 between the first and second resistors, the compensation capacitor being coupled in parallel with the first resistor, wherein the first OTA and second OTA are configured for wide-band, and low-power operation, being without any internal frequency compensation capacitors, whereby the frequency compensation is a non-Miller approach, and when a low-value, low intrinsic equivalent series resistance (ESR) load capacitor is coupled to the output voltage terminal, a behavior close to a single-pole loop, deliver a step and almost undershoot and overshoot-free load transient response, is obtained.