Patent ID: 6534355
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method of manufacturing a nonvolatile memory semiconductor device having, on one and the same substrate, a flash memory area where a memory-transistor and a select-transistor are formed and a logic area where an adjacent circuit transistor is formed; which, at least, comprises the steps of:(1) growing an Nâˆ’-type first polysilicon upon a semiconductor substrate on which an element isolation region and an oxide film are formed; (2) removing the first polysilicon overlying the element isolation region as well as the logic area by etching; (3) growing a first insulating film over the entire surface so as to cover the remaining first polysilicon; (4) removing, at least, the first insulating film in the logic area; (5) growing a second polysilicon as well as a nitride, film over the entire surface; (6) forming a resist pattern at the positions where electrodes of the memory-transistor and the adjacent circuit transistor are to be formed and, then, with said pattern used as a mask, carrying out etching of the nitride film and the second polysilicon; (7) removing the resist pattern, and thereafter forming another resist pattern at the position where an electrode of the select-transistor is to be formed as well as on the entire surface of the logic area, and, then, with said nitride film used as a mask for the memory-transistor and said pattern, for the select-transistor, carrying out etching of the first insulating film and the first polysilicon; (8) removing said nitride film as well as said resist pattern, and thereafter, concurrently with forming source-drain regions, applying ion implantation to the second polysilicon which is to serve as a control gate of the memory-transistor and as a gate electrode of the adjacent circuit transistor in the logic area and to the first polysilicon which is to serve as a gate electrode of the select-transistor; and (9) removing, by means of isotropic etching, the oxide film lying on the substrate surface other than the parts thereof underlying every transistor, to the level where the substrate surface is exposed.