Patent ID: 6323930
Filing Date: 2001-11-27
Classification: G02F,G09G,H01L

Abstract:
A liquid crystal display device, comprising:a first glass substrate;a liquid crystal display panel formed on one surface of said first glass substrate, said liquid crystal display panel including a second glass substrate over said one surface of said first glass substrate and a liquid crystal layer between said first and second glass substrates;a semiconductor chip for controlling said liquid crystal display panel, disposed on said first glass substrate, said semiconductor chip having an integrated circuit and a plurality of external terminals formed in a main surface thereof, said integrated circuit of said semiconductor chip having a plurality of operation modes and including a first circuit for determining an operation mode from among said plurality of operation modes, said plurality of external terminals comprising:input terminals for receiving input signals from an external device;output terminals for providing output signals to said liquid display panel;a first fixed potential terminal for providing an operating potential to said integrated circuit of said semiconductor chip;a second fixed potential terminal electrically connected to said first fixed potential terminal via a wiring layer formed in said main surface of said semiconductor chip; anda mode terminal electrically connected to said first circuit of said integrated circuit of said semiconductor chip, said first circuit determining said operation mode from among said plurality of operation modes in response to a voltage level inputted to said mode terminal; anda plurality of conductive layers formed on said one surface of said first glass substrate, said plurality of conductive layers comprising:first conductive layers electrically connecting said input terminals of said semiconductor chip and said external device;second conductive layers electrically connecting said output terminals of said semiconductor chip and said liquid crystal display panel;a third conductive layer being connected to said first fixed potential terminal and providing said operating potential to said first fixed potential terminal; anda fourth conductive layer electrically connecting said second fixed potential terminal and said mode terminal of said semiconductor chip;wherein said semiconductor chip is mounted on said first glass substrate such that said main surface of said semiconductor chip is faced to said one surface of said first glass substrate and said external terminals of said semiconductor chip are electrically connected to corresponding conductive layers via bump electrodes; andwherein said second fixed potential terminal of said semiconductor chip is arranged at the vicinity of said mode terminal and provides said voltage level to said mode terminal through said fourth conductive layer.