Patent ID: 9071233
Filing Date: 2015-06-30
Classification: H03K

Abstract:
1. A flip-flop circuit comprising: a clocked pull-up component comprising: a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant when a clock signal is at a second level; comprising: a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value, and with the slave complement storage node communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock signal is at the first level, so that the slave complement storage node retains a previous value; comprising: