Patent ID: 6232759
Filing Date: 2001-05-15
Classification: G01R

Abstract:
An integrated circuit (IC) tester for testing an IC having a plurality of terminals by supplying test signals (V.sub.OUT) to said terminals and by monitoring IC output signals (DUTOUT) produced at said terminals, the IC tester comprising:a plurality of tester channels (CH1-CHM) each corresponding to a separate one of said IC terminals, each tester channel comprising:means (18,24) for generating a sequence of waveform data words (DATA) having multiple bits (D1-DN); anda digital-to-analog converter (DAC) for receiving said sequence of waveform data words and for producing one of said test signals in response thereto, wherein said DAC comprises:a plurality of DAC units (U1-UN), each receiving a separate bit of each said waveform data word and each generating a separate first ramp signal (I1SRC-INSRC) that ramps linearly between differing first and second magnitudes in response to a change in state of said separate bit;output stage means (38) producing said one of said test signals in response to a combination of all first ramp signals produced by said plurality of ramp generators; andmeans (15,92) for delivering said one of said test signals to an IC terminal corresponding to the tester channel.