Patent ID: 6323508
Filing Date: 2001-11-27
Classification: H01L

Abstract:
An insulated gate type semiconductor device, comprising:a semiconductor base body having an upper main surface and a lower main surface,the semiconductor base body having,a first semiconductor layer of a first conductivity type,a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, anda third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,said semiconductor base body having a trench arranged along said upper main surface and formed from said upper main surface to said first semiconductor layer, said trench including at least as a part thereof a plurality of trenches arranged substantially in a stripe form,said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches,said insulated gate type semiconductor device further comprising,a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, anda second main electrode electrically connected to said lower main surface,said first main electrode being electrically connected to said upper main surface in a first region defined substantially in a zonal form along said trenches in said upper main surface interposed between adjacent said trenches,said third semiconductor layer being exposed in a second region and third regions defined in said upper main surface interposed between adjacent said trenches,said third regions being defined substantially in zonal forms without discontinuance adjacently to an inside of adjacent said trenches and along the same, andsaid second region being selectively defined in a part of a region interposed between adjacent said third regions, andsaid insulated gate type semiconductor device further comprising,overcurrent protection means for limiting a magnitude of a main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, anda shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>m.times.Jpr.times..rho. pn.times.Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to a rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and ratio resistance .rho. pn of said second semiconductor layer right under said third semiconductor layer.