Patent ID: 7428661
Filing Date: 2008-09-23
Classification: G06F

Abstract:
1. A test and debug processor, comprising: a. a JTAG-bus controller capable of controlling JTAG states and signals, commanding JTAG state changes and initiating JTAG instruction scans and JTAG data scans; b. a JTAG port coupled to said JTAG-bus controller enabling said JTAG-bus controller to attach to, control and access electronic devices; c. means to access a memory structure capable of storing instructions executable by said processor; and, d. an instruction decoding unit connected to said JTAG-bus controller capable of receiving, fetching or requesting instructions from said memory structure and of forwarding said instructions for execution to said JTAG-bus controller; wherein said processor instructions specify functions to be executed by the attached JTAG-bus controller; said processor instructions are directly executable by said JTAG-bus controller as read from the memory structure without the need to use any additional components to interpret such instructions prior to forwarding them to the JTAG-bus controller.