Patent ID: 7707328
Filing Date: 2010-04-27
Classification: G06F

Abstract:
1. A memory access control circuit of controlling access of a data processing device to a memory, wherein the memory is a synchronous memory having a plurality of memory banks capable of being operated independently, and data can be burst-transferred in accordance with a clock signal, the memory access control circuit comprising: a burst transfer length unit transfer request dividing section of receiving a data transfer request with respect to the memory from the data processing device, and dividing the received data transfer request into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time, and the data to be burst-transferred at a time is within a single memory bank; a transfer request assembling section of assembling the plurality of data transfer requests divided by the burst transfer length unit transfer request dividing section into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank, so that access is always performed from a fixed memory bank; and a data transfer control section of controlling data transfer between the memory and the data processing device based on one of the new data transfer requests assembled in the transfer request assembling section.