Patent ID: 8352533
Filing Date: 2013-01-08
Classification: G06F

Abstract:
1. A semiconductor integrated circuit comprising: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks to input data of a first bit width and perform computation; a first network to connect the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks to input data of a second bit width different from the first bit width and perform computation; a second network connected to outputs of the plurality of second logic blocks; and a third network to connect a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner, wherein the third network connects a carry bit output of a computing unit included in one second logic block of the plurality of second logic blocks to an input of a computing unit included in another second logic block.