Patent ID: 8185072
Filing Date: 2012-05-22
Classification: H04L,Y02D

Abstract:
1. An input/output controller component comprising: a logic to define and monitor a plurality of states to control a power state for a squelch receiver for an interconnect link, the logic to power down the squelch receiver in response to a state of the interconnect link; a masking logic to mask an output of the squelch receiver utilized in the interconnect link, wherein a time during which the output of the squelch receiver is masked is based at least in part on an actual link state, where, for the actual link state, a maximum permissible latency for unmasking of the output of the squelch receiver is different for different states and is inversely proportional to a polling rate corresponding to a receiver state; and a plurality of counters used to define various timeout conditions for the plurality of states that control the power state of the interconnect link.