Patent ID: 7427561
Filing Date: 2008-09-23
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device, comprising: forming a gate electrode on a semiconductor substrate by interposing a gate insulation layer; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer using one of physical vapor deposition and chemical vapor deposition; performing an annealing process upon the semiconductor substrate to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer left unreacted with the gate electrode and the semiconductor substrate; wherein the forming of the metal layer, the plasma treatment, the forming of the capping material layer, and the annealing process are performed in the same chamber via an in-situ process.