Patent ID: 7094663
Filing Date: 2006-08-22
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device comprising: forming a device isolation layer for defining a device region and a high concentration impurity diffused region acting as a substrate/well potential take-out region; forming a gate electrode on a surface of the substrate within the device region; implanting ions in the device region and the high concentration impurity diffused region with the device isolation layers and the gate electrode being as implantation mask; depositing low resistance layer at least on the upper surface of the high concentration impurity diffused region, this low resistance layer acting as a shield during operation; depositing an inter-layer insulating film; and forming a first interconnection connected to the gate electrode and a second interconnection connected to the high concentration impurity diffused region on the said inter-layer insulating film, at least the first interconnection being disposed so that it runs above the high concentration impurity diffused region.