Patent ID: 6064106
Filing Date: 2000-05-16
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate;an element forming region in said semiconductor substrate;two element isolation regions in said semiconductor substrate;two trenches located on sides of said element forming region, for electrically separating said element forming region from said element isolation regions;a first insulation film formed on a surface of said trenches;a conductive material filled in said trenches;a second insulation film for element isolation extending on said trenches and said element isolation regions and not extending onto said element forming region; anda transistor formed in said element forming region, the transistor including:a base region including an inner base region and an outer base region, an emitter region, and a collector region, each formed in the semiconductor substrate, the emitter region being in contact with a side edge portion of said second insulation film;a base contact layer, an emitter contact layer and a collector contact layer formed on said outer base region, said emitter region and said collector region, respectively, wherein said outer base region is formed in a self alignment manner with the collector contact layer and the emitter contact layer, and said base contact layer is in a self alignment manner with insulation films formed on side walls of the collector contact layer and the emitter contact layer; anda base electrode layer, an emitter electrode layer, and a collector electrode layer formed on said base contact layer, said emitter contact layer, and said collector contact layer, respectively.