Patent ID: 8520403
Filing Date: 2013-08-27
Classification: H01L,H05K

Abstract:
1. A multi-layer semiconductor element package structure, comprising: a substrate unit having at least one top substrate, at east one middle substrate and at least one bottom substrate; an insulated unit having at least one first insulated layer filled between the at least one top substrate and the at least one middle substrate and at least one second insulated layer filled between the at least one middle substrate and the at least one bottom substrate; a one-way conduction unit having a plurality of one-way conduction elements electrically disposed between the at least one top substrate and the at least one middle substrate and enclosed by the at least one first insulated layer; and a protection unit having at least one protection element with anti surge current or anti surge voltage function electrically disposed between the at least one middle substrate and the at least one bottom substrate and enclosed by the at least one second insulated layer; wherein the at least one top substrate has a plurality of first half holes formed on a lateral side thereof, the at least one first insulated layer has a plurality of second half holes formed on a lateral side thereof and corresponding to the first half holes, the at least one middle substrate has a plurality of third half holes formed on a lateral side thereof and corresponding to the second half holes, the at least one second insulated layer has a plurality of fourth half holes formed on a lateral side thereof and corresponding to the third half holes, and the at least one bottom substrate has a plurality of fifth half holes formed on a lateral side thereof and corresponding to the fourth half holes.