Patent ID: 6622154
Filing Date: 2003-09-16
Classification: G06F

Abstract:
A partial product generator cell suitable for hardware implementation of multipliers having three multiplier bits and two multiplicand bits, comprising:(a) a first multiplexor having two data inputs, a control input, and an output, a first data input being connected to a first multiplier bit and said control input being connected to a second multiplier bit; (b) a second multiplexor having two data inputs, a control input, and an output, said data inputs being connected to a first multiplicand bit and a second multiplicand bit; (c) a third multiplexor having two data inputs, a control input, and an output, said control input being connected to a third multiplier bit; (d) a AND gate having two input leads and an output lead, wherein a first input lead is connected to said first multiplier bit and a second input lead is connected to said second multiplier bit; (e) a NAND gate having two input leads and an output lead, said output lead being connected to a first data input of said third multiplexor; (f) a two input two stack AOI gate having a first, second, third, and fourth input leads, and an output lead, said first input lead being connected to said output lead of said AND gate, said second input lead being connected to a first multiplicand input bit, said fourth input lead being connected to a second multiplicand bit, and said output lead being connected to a second data input of said third multiplexor; (g) a first inverter having an input lead connected to said first multiplier bit and an output lead connected to a second data input of said first multiplexor; (h) a second inverter having an input lead connected to said output of said first multiplexor and an output lead connected to said third input lead of said two input two stack AOI gate; (i) a third inverter having an input lead connected to said output lead of said AND gate and an output lead connected to a first input lead of said NAND gate; (j) a fourth inverter having an input lead connected to said output of said second multiplexor and an output lead connected to a second input lead of said NAND gate; and (k) a fifth inverter having an input lead and an output lead, wherein said input lead is connected to said output of said third multiplexor.