Patent ID: 9223753
Filing Date: 2015-12-29
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a register file including a plurality of floating point registers, the register file including an output; a plurality of operand inputs configured to receive floating point operands from the register file, each floating point operand received by each operand input configured with an exponent field and a significand field, with the significand field including a first portion and a second portion; a floating point execution unit coupled to the plurality of operand inputs and configured to process floating point operands received by the plurality of operand inputs during execution of floating point instructions, wherein the floating point execution unit is configured to execute a first floating point instruction for which a first plurality of floating point operands have been received by the plurality of operand inputs by using data stored in the exponent field of each of the first plurality of floating point operands as an exponent and by concatenating data stored in the first and second portions of the significand field of each of the first plurality of floating point operands for use as a significand, and wherein the floating point execution unit is configured to execute a second floating point instruction for which a second plurality of floating point operands have been received by the plurality of operand inputs by concatenating data stored in the exponent field and the first portion of the significand field of each of the second plurality of floating point operands for use as an exponent and by using data stored in the second portion of the significand field of each of the second plurality of floating point operands as a significand, wherein the first and second pluralities of floating point operands include a same number of bits; and shift logic including at least one multiplexer coupled between the output of the register file and the plurality of operand inputs to receive the floating point operands from the register file, the shift logic configured to, for the second floating point instruction, shift data stored in the second portion of the significand field of each of the plurality of second floating point operands in parallel and control the at least one multiplexer to output the shifted data to the plurality of operand inputs during execution of the second floating point instruction, and for the first floating point instruction, control the at least one multiplexer to bypass shifting of data stored in the second portion of the significand field of each of the plurality of first floating point operands in parallel during execution of the first floating point instruction, and wherein the shift logic is unclocked such that the second plurality of floating point operands are communicated by the shift logic from the register file to the plurality of operand inputs during execution of the second floating point instruction without any additional clock cycles relative to the communication of the first plurality of floating point operands from the register file to the plurality of operand inputs during execution of the first floating point instruction.