Patent ID: 6047393
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A memory testing apparatus including a pattern generator for supplying a test signal having a predetermined pattern to a memory under test, a direct current test unit for measuring a voltage appearing at a terminal of said memory under test or a current flowing through the terminal of said memory under test, and a controller for controlling operations of those pattern generator and the direct current test unit, said pattern generator comprising:hold time setting means for setting a time duration of a hold mode in which said pattern generator is maintained in a state that a test signal of one pattern is kept being generated from said pattern generator;hold mode control means for controlling said pattern generator in the hold mode; anddirect current test start command generating means for supplying a direct current test start command to said direct current test unit in a state that said hold mode control means has controlled said pattern generator in the hold mode,said direct current test unit comprising:decision means for determining whether or not a voltage value or a current value measured by said direct current test unit coincides with a reference value; anda failure analysis memory for storing therein a result of failure decision determined by said decision means representing that the measured voltage value or current value does not coincide with the reference value.