Patent ID: 7224636
Filing Date: 2007-05-29
Classification: G11C

Abstract:
1. A semiconductor memory module comprising: a plurality of memory chips arranged next to one another in an row; a memory controller device; and a module-internal clock, command/address and data bus that transfers a clock signal, command and address signals and also data signals from the memory controller device to the memory chips and data signals from the memory chips to die memory controller device and that has respective clock, command/address and data signal lines; wherein the clock signal lines further comprise two differential clock signal lines each having first and second ends, the first ends of which are coupled to the memory controller device and the second ends configured such that a clock signal propagated on the two differential clock signals lines from their first ends in one direction is reflected at their second ends and returns the opposite direction to the first ends of the two differential clock signal lines, and wherein the memory chips synchronize write data with the clock signal running from the memory controller device to the second ends of the clock signal line during a write operation and wherein the memory chips output read data synchronously with the clock signal reflected back from the second ends of the clock signal lines.