Patent ID: 7292079
Filing Date: 2007-11-06
Classification: H03K,H03L

Abstract:
1. A circuit for delaying an input signal comprising: a first and a second high-threshold capacitor-coupling trigger, which receive an input signal at an input terminal of the trigger, and outputs an output signal at an output terminal of the trigger according to the input signal, each comprising: a first inversion-mode PMOS capacitor, the gate being coupled to the other terminal of the first capacitor, for control the delay time of the output signal in response to a control voltage; a second inversion-mode PMOS capacitor the gate being coupled to the other terminal of the second capacitor, for control the delay time of the output signal in response to a control voltage; a first inverter, the input terminal and the output terminal of the first inverter being coupled to the output terminal of the first high-threshold capacitor-coupling trigger and the output terminal of the second high-threshold capacitor-coupling trigger respectively; and a second inverter, the input terminal and the output terminal of the second inverter being coupled to the output terminal of the second high-threshold capacitor-coupling trigger and the output terminal of the first high-threshold capacitor-coupling trigger respectively.