Patent ID: 8881076
Filing Date: 2014-11-04
Classification: G06F

Abstract:
1. A computerized software implemented method for identifying instances of digital drivers that are in a contention configuration which creates multiple conflicting current paths with respect to power or ground nets in a specification of an electronic circuit design of a netlist of a complex integrated circuit chip comprising a plurality of nets and electrically interconnected transistors, said method comprising: obtaining said electronic circuit design in a computer readable form; using at least one computer processor to perform the steps of: automatically determining which of said transistors are configured as digital drivers; for at each net comprised of a plurality of digital drivers for which an analysis is desired, performing a logic expansion to create an expanding logic tree representation of a previous level of predecessor circuit portions that drive a state of each digital driver of said plurality of digital drivers, and determining if any states of predecessor nodes in the previous level of the predecessor circuit portions are simultaneously to create a pull up path to said power net and a pull down path to said ground net, thereby indicating a potential contention configuration; repeating said logic expansion for the next previous levels of the predecessor circuit portions, seeking logical conflicts within the expanding logic tree representation, until it can be determined that either no predecessor circuit portion can cause said potential contention configuration, or until a predecessor circuit portion that does cause said potential contention configuration is identified; and if such predecessor circuit portion that does cause said potential contention configuration is identified, reporting an identity of each digital driver in said predecessor circuit portion as a potential contention digital driver.