Patent ID: 7564281
Filing Date: 2009-07-21
Classification: H03L

Abstract:
1. A phase locked loop circuit including: a phase frequency detector receiving a frequency divided signal and an input clock signal with a reference frequency and detecting the difference in phase and frequency between the input clock signal and the frequency divided signal and then outputting a phase difference signal; a charge pump outputting an output current in response to the phase difference signal; a loop filter generating a control voltage in response to the phase difference signal; a voltage controlled oscillator generating a voltage controlled clock signal with a voltage controlled frequency in response to the control voltage; a multi-modulus divider receiving the voltage controlled clock signal and then generating the frequency divided signal and an output clock signal with an output frequency, wherein a first divisor can be selected from a plurality of divisors provided by the multi-modulus divider to achieve a relation that the voltage controlled frequency divided by the first divisor equals the output frequency; and a decision unit receiving the phase difference signal and the control voltage and determining to select a second divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.