Patent ID: 8442100
Filing Date: 2013-05-14
Classification: H04B,H04L

Abstract:
1. An apparatus, comprising: a transmitter embedded in a package and configured to transmit digital signals having a first logic level and a second logic level higher than the first logic level; a transmitter control block embedded in the package and coupled to the transmitter and configured to selectively provide synchronization signals or digital data signals to the transmitter for transmission; a receiver embedded in the package and configured to receive signals transmitted by the transmitter; a receiver control block embedded in the package and coupled to the receiver, the receiver control block configured to synchronize the receiver with the transmitter using synchronization signals received by the receiver from the transmitter, to memorize synchronization in a storage element and to hold synchronization while the transmitter is transmitting data signals; and a galvanically isolated interface embedded in the package and coupled between the transmitter and the receiver, said transmitter and interface being configured to form a two-level isolated digital channel, wherein the transmitter control block is configured to provide a synchronization signal to the transmitter to transmit to the receiver during a determined synchronization period and to provide a digital data signal, the digital data signal being representative of a bit sequence of a determined length, to the transmitter to transmit during a determined data sequence transmission period after synchronization of the transmitter and receiver.