Patent ID: 6516422
Filing Date: 2003-02-04
Classification: G06F

Abstract:
A computer system, comprising:switching logic coupled to receive a first clock signal and a second clock signal, wherein said second clock signal is synchronous with said first clock signal, wherein said switching logic is configured to select either said first clock signal or said second clock signal as a local clock signal, wherein said switching logic is further configured to monitor said first clock signal for a failure, wherein if said failure of said first clock signal is detected by said switching logic, said switching logic is further configured to accept said second clock signal as said local clock signal in place of said first clock signal; one or more local clock loads that operate according to said local clock signal; a first clock source coupled to said switching logic and to said system controller, wherein said first clock source is configured to provide said first clock signal; and a second clock source coupled to said switching logic and to said system controller, wherein said second clock source is configured to provide said second clock signal, wherein said second clock source includes: a phase detector coupled to receive said first clock signal and said second clock signal, wherein said phase detector is configured to output an output signal indicative of a difference between said first clock signal and said second clock signal, a loop filter coupled to receive said output signal indicative of said difference, wherein said loop filter is configured to output a first control signal, a voltage controlled oscillator (VCO) coupled to receive said first control signal, wherein said VCO is configured to output said second clock signal in phase with said first clock signal, and a switch coupled to selectively cause either the first control signal or a fixed reference voltage to be provided to the VCO.