Patent ID: 7114038
Filing Date: 2006-09-26
Classification: G06F,Y02D

Abstract:
1. A computer system, comprising: a processor comprising a cache, a first bus interface and a second bus interface; a controller to snoop the cache via the first bus interface during a first mode of operation and to snoop the cache via the second bus interface during a second mode of operation, the second mode of operation being a lower power mode than the first mode of operation, and the first bus interface to be powered down during the second mode of operation, the first bus interface is coupled to the controller via a first bus, the first bus is a parallel bus, and the second bus is a serial bus having a single data line, the first bus being wider than the second bus, the first bus to consume more power during the first mode of operation than the second bus consumes during the second mode of operation; and a main memory and a peripheral device, the peripheral device to request an access of the main memory via the controller.