Patent ID: 9087600
Filing Date: 2015-07-21
Classification: G11C

Abstract:
1. A method of programming a memory, comprising: storing data to be programmed to levels within a first plurality of levels in a first plurality of latches; inhibiting programming of cells to be programmed to levels within a second plurality of levels by storing inhibit data in a second plurality of latches; programming cells to the levels within the first plurality of levels using a first set of program pulses having programming voltages within a first programming voltage range; storing data to be programmed to the levels within the second plurality of levels in the second plurality of latches; inhibiting programming of the cells that were programmed to the levels within the first plurality of levels by storing inhibit data in the first plurality of latches; and programming cells to the levels within the second plurality of levels using a second set of program pulses having programming voltages within a second programming voltage range; wherein the first programming voltage range overlaps the second programming voltage range.