Patent ID: 8670261
Filing Date: 2014-03-11
Classification: G11C,H01L

Abstract:
1. A microelectronic structure, comprising: active elements defining a memory storage array; address input contacts for receipt of address information specifying locations within the storage array; and data contacts configured for transferring data at least one of from the storage array or to the storage array, the structure having a first surface and first and second peripheral edges each extending away from the first surface and being opposite from one another, and the structure having terminals exposed at the first surface, the terminals including first terminals and the structure being configured to provide address information received at the first terminals to the address input contacts, each of at least some of the first terminals having a signal assignment including information to be transferred to one or more of the address input contacts, the first terminals disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein signal assignments of the first terminals disposed on the first side are symmetric about the theoretical plane with the signal assignments of the first terminals disposed on the second side, the terminals further including second terminals coupled with the data contacts and exposed at the first surface, a first portion of the second terminals disposed between the first terminals and the first peripheral edge and a second portion of the second terminals being disposed between the first terminals and the second peripheral edge.