Patent ID: 6064704
Filing Date: 2000-05-16
Classification: H03K

Abstract:
A digital pulse filtering circuit for filtering a composite signal, which comprises:clock means for generating a periodic clock signal;a first D-type flip-flop, which is clocked by the clock signal and takes the composite signal as input, for generating a first sampled signal which takes on the current voltage level of the composite signal at the appearance of each rising edge in the clock signal and remains at that voltage level until the appearance of the next rising edge in the clock signal;a second D-type flip-flop, which is clocked by an inverted version of the clock signal and takes the composite signal as input, for generating a second sampled signal which takes on the current voltage level of the composite signal at the appearance of each falling edge in the clock signal and remains at that voltage level until the appearance of the next falling edge in the clock signal;a detection circuit, receiving the first and second sampled signals as inputs, for generating a filtered version of the composite signal in such a manner that:when the first and second sampled signals are both at a high voltage level, the output signal from said detection circuit is at a high voltage level;when the first and second sampled signals are both at a low voltage level, the output signal from said detection circuit is at a low voltage level; andwhen the first and second sampled signals are unequal in voltage level, the output signal from said detection circuit remains unchanged.