Patent ID: 9019491
Filing Date: 2015-04-28
Classification: G01B,G01N

Abstract:
1. A dual-sided Moiré wafer analysis system, comprising: a wafer support operable for positioning a silicon wafer to be analyzed; a first screen configured to project a Moiré pattern from the first screen toward a first side of the wafer in multiple fringe acquisition iterations, wherein each fringe acquisition iteration comprises projecting the Moiré pattern across the first side of the wafer from a different rotational angle with respect to the first side of the wafer; a first detector for acquiring multiple fringe patterns for the first side of the wafer, each fringe pattern reflected from the first side of the wafer during a corresponding fringe acquisition iteration of the first side of the wafer; a computer system operable for computing multiple slope maps for the first side of the wafer, each slope map for the first side of the wafer computed based on a corresponding fringe pattern for the first side of the wafer; wherein the computer system is further operable for integrating the multiple slope maps for the first side of the wafer to construct a height map for the first side of the wafer; a second screen configured to project a Moiré pattern from the second screen toward a second side of the wafer in multiple fringe acquisition iterations, wherein each fringe acquisition iteration comprises projecting the Moiré pattern across the second side of the wafer from a different rotational angle with respect to the second side of the wafer; a second detector for recording multiple fringe patterns for the second side of the wafer, each fringe pattern reflected from the second side of the wafer during a corresponding fringe acquisition iteration of the second side of the wafer; wherein the computer system is further operable for computing multiple slope maps for the second side of the wafer, each slope map for the second side of the wafer computed based on a corresponding fringe pattern for the second side of the wafer; wherein the computer system is further operable for integrating the multiple slope maps for the second side of the wafer to construct a height map for the second side of the wafer; and wherein the computer system is further operable for creating a thickness variation map for the wafer from the height maps for the first and second sides of the wafer.