Patent ID: 7114115
Filing Date: 2006-09-26
Classification: G11B

Abstract:
1. A data reproducing controller for controlling reproduction of recording data, wherein the recording data is in sectors with each sector including a predetermined number of rows of scrambled data with each row having a predetermined number of bytes, a first error correction code added to each row of the scrambled data, a second correction code added to the predetermined number of rows of scrambled data, the data reproducing controller comprising: a first error correction circuit for performing a first error correction process on the scrambled data in units of rows in accordance with the first error correction code; a descrambling circuit for performing a descrambling process on the scrambled data that has undergone the first error correction process to generate descrambled data; a counter for counting the scrambled data in units of rows; and a determination circuit for detecting a timing at which the second error correction code is provided to the descrambling circuit from the count value and for inactivating the descrambling process when the second error correction code is provided to the descrambling circuit.