Patent ID: 6147510
Filing Date: 2000-11-14
Classification: H03K,Y10T

Abstract:
An integrated circuit comprising:buffer circuitry for providing an output signal, the buffer circuitry comprising a tri-stateable buffer;a first terminal for receiving the output signal coupled to the buffer circuitry;a contention detection circuit coupled to the buffer circuitry, the contention detection circuit comprising a first power supply terminal and a second power supply terminal, the contention detection circuit further comprising circuitry for detecting a predetermined voltage differential between the first power supply terminal and the second power supply terminal, wherein the contention detection circuit provides a contention tri-state control signal to the buffer circuitry, the contention tri-state control signal having a first logic value and a second logic value, and wherein the tri-stateable buffer is tri-stated when the buffer circuitry receives the contention tri-state control signal having the first logic value, wherein the buffer circuitry receives the contention tri-state control signal having the first logic value when the first terminal provides power to the buffer circuitry and the contention detection circuit, and wherein the tri-stateable buffer is tri-stated by the contention tri-state control signal when the predetermined voltage differential is detected.