Patent ID: 8664994
Filing Date: 2014-03-04
Classification: H03H

Abstract:
1. A system to generate a predetermined fractional period delay in an integrated circuit comprising: a controllable delay line block with a predefined number of taps to generate a predetermined delayed output for an input clock, wherein said predefined number of taps of the said delay line block are adjusted to a value determined by a closed loop controller action; a sampling block to sample the input clock and the delayed output to generate sub-sampled signals corresponding to the input and delayed output signals; a delay measurement unit (DMU) to process the sub-sampled signals to generate required parameters for closing the loop; and a delay control unit to receive the required parameters from the DMU and predefined user input data to estimate delay between the input and the output, generate tap values, and adjust the taps of the controllable delay line using said tap values to generate the predetermined time delay.