Patent ID: 6108763
Filing Date: 2000-08-22
Classification: G06F

Abstract:
A processing array comprising:a plurality of processing elements; anda bidirectional interconnection network disposed to directly connect all of adjacent neighboring processing elements for each of said plurality of processing elements for carrying data messages between any of the adjacent neighboring processing elements,wherein each of said processing elements of said plurality of processing elements comprises:a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element over the interconnection network to another processing element among said plurality of processing elements; anda parity checking circuit for checking parity of a second data message as it is received by that processing element over the interconnection network, said parity checking and parity generating circuits being separate from each other and enabling that processing element to generate parity for the first data message being sent by that processing element while simultaneously checking parity of the second message being received by that processing element.