Patent ID: 7858402
Filing Date: 2010-12-28
Classification: G01R,H01L

Abstract:
1. An integrated circuit package, comprising: an integrated circuit chip; a substrate having a first layer and a second layer separated by at least one electrically isolating layer; a first electrically conductive trace; a second electrically conductive trace, the first and second electrically conductive traces being contained in a common layer of the substrate and being routed in the common layer in parallel with the electrically isolating layer; and a solder mask layer that substantially covers the first layer; wherein the first layer includes a plurality of electrically conductive features; wherein the second layer is a ground layer that includes a first electrically conductive region and a second electrically conductive region, the first and second electrically conductive regions being electrically isolated from each other; wherein the first electrically conductive region is coupled to a first ground signal of the chip, and the second electrically conductive region is coupled to a second ground signal of the chip; wherein the first electrically conductive trace is coupled to the first electrically conductive region and the second electrically conductive trace is coupled to the second electrically conductive region, and a portion of the first electrically conductive trace is proximate to a portion of the second electrically conductive trace, the first and second electrically conductive traces being configured to be selectively electrically coupled together to electrically couple together the first and second ground signals; wherein the first and second electrically conductive traces are in the first layer; and wherein the solder mask layer has an opening that overlaps the portion of the first electrically conductive trace and the portion of the second electrically conductive trace.