Patent ID: 6501188
Filing Date: 2002-12-31
Classification: G03F,H01L,Y10S

Abstract:
A method for improving alignment to underlying topography in a semiconductor device structure during an alignment step comprising:providing a reflective, non-planar surface on a semiconductor device or assembly; forming an insulator layer over the reflective, non-planar surface and forming a second layer over a base planar-surfaced layer, the base planar-surfaced layer and the second layer having a first index of refraction, wherein the insulator layer is boro-phospho-silicate glass; forming a corrective layer over the second layer, the corrective layer having an intermediate index of refraction; and forming a process layer over the corrective layer, the process layer having a second index of refraction, wherein the intermediate index of refraction lies between the first index of refraction and the second index of refraction.