Patent ID: 7461364
Filing Date: 2008-12-02
Classification: G06F

Abstract:
1. A computer-implemented method for analyzing relative positioning of a structure, the method comprising: receiving a request to determine relative positions for one or more specific locations of entities within an Integrated Circuit (IC) design structure, the request comprising a list of bits and hierarchy information for each bit; determining locations within a design hierarchy based on the request to determine relative positions by determining design hierarchy locations with respect to an enclosing group within the hierarchy for each of the bits; comparing the determined locations with the one or more specific locations of the request by comparing known bit numbers within the design hierarchy to the bits of the request; generating a list of relative positions based on bits of the request that matched known bit numbers within the determined design hierarchy; receiving a request to determine specific locations associated with one or more relative positions of an IC design structure, the request comprising a list of user-defined ranges and hierarchy information for each user-defined range; determining locations within a design hierarchy based on the request to determine specific locations by determining design hierarchy locations with respect to an enclosing group within the hierarchy for elements of each of the user-defined ranges; determining specific locations for each relative position in the request to determine specific locations; and generating a list of the determined specific locations for each relative position.