Patent ID: 6881672
Filing Date: 2005-04-19
Classification: H01L

Abstract:
1. A method for forming a semiconductor apparatus comprising the steps of: forming an N+ diffusion and a P+ diffusion; forming a polysilicon line, the polysilicon line having a P+ region and an N+ region, the polysilicon line having an N+/P+ junction area wherein said junction area comprises the area where the P+ region of the polysilicon line and the N+ region of the polysilicon line abut each other; and, selectively forming a silicide strap over a portion of a top surface of the N+ region and the P+ region and extending across the junction area, wherein the silicide strap forms an electrical connection between the P+ region of the polysilicon line and the N+ region of the polysilicon line, and wherein the portion of the top surface of the N+ region and the P+ region does not comprise an entire top surface of the N+ region and the P+ region; and selectively preventing the formation of silicide on the N+ diffusion and the P+ diffusion.