Patent ID: 6337262
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method for forming self-aligned T-top gate electrode structures over active and over Shallow Trench Isolation (STI) regions of a substrate, comprising the steps of:providing a substrate having a surface, the surface of said substrate having undergone preliminary processing; depositing a thin layer nitride over the surface of said pre-processed substrate, said thin layer of nitride having a surface; depositing a layer of TEOS over the surface of said thin layer of nitride, said layer of TEOS having a surface; patterning and etching said layer of TEOS down to the surface of said thin layer of nitride, creating openings in said layer of TEOS, said openings being aligned with said active and Shallow Trench Isolation (STI) regions on the surface of said substrate where said self-aligned T-top gate electrode structures need to be created; depositing a thin layer of nitride over the surface of said patterned layer of TEOS, including said openings created in said layer of TEOS; etching said layer of nitride, forming gate spacers on sidewalls of said openings created in said layer of TEOS; creating self-aligned T-top gate electrode structures having a surface by depositing a sequence of layers of materials that constitute gate electrodes, removing any excess depositions from the surface of said layer of TEOS; and removing said patterned layer of TEOS, completing creation of said self-aligned T-top gate electrode structures.