Patent ID: 6853603
Filing Date: 2005-02-08
Classification: G11C

Abstract:
1. An apparatus including a programmable logic device, said programmable logic device comprising: a memory that stores configuration information and user defined information, wherein said memory selectively operates according to a first power state and a second power state, wherein said second power state is a lower power consumption state than said first power state; and a control circuit, coupled to said memory, that controls access to said memory with a power selection signal, wherein said first power state corresponds to accessing said memory at a first rate and said second power state corresponds to accessing said memory at a second rate, wherein during configuration of said programmable logic device, said control circuit controls said memory to output said configuration information at said first rate, and wherein during normal operation of said programmable logic device, said control circuit controls said memory to selectively access said user defined information at one of said first rate and said second rate in accordance with said power selection signal, wherein said second rate is lower than said first rate.