Patent ID: 7089135
Filing Date: 2006-08-08
Classification: G01R

Abstract:
1. A method for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment, comprising the following steps of: storing event data derived directly from simulation of design data for an intended IC in the EDA environment in an event memory, the event data for each event being formed with event timing data indicating a time length from a previous event and event type data indicating a type of event; generating test vectors based on the event data from the event memory where waveform of each vector is determined by the event type data and a timing of the waveform is determined by accumulating the timing data of previous events; and supplying the test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings; wherein the event data is obtained from VCD (Value Change Dump) which are timed event values produced by executing the logic simulation without conversion or translation.