Patent ID: 7205637
Filing Date: 2007-04-17
Classification: H01L

Abstract:
1. A semiconductor device comprising: a semiconductor chip; a guard ring which is formed by part of an uppermost interconnection layer in a multilevel interconnection that is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers, the guard ring being arranged adjacent to each corner of the semiconductor chip; a first conductive member which is buried in a first contact hole formed in the low-permittivity insulating layer below the guard ring, and contacts the guard ring; an alignment mark which is formed by part of the uppermost interconnection layer in the multilevel interconnection, and arranged near at least one corner of the semiconductor chip; and a second conductive member which is buried in a second contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.