Patent ID: 7936327
Filing Date: 2011-05-03
Classification: G09G

Abstract:
1. A driving circuit comprising: a plurality of parallel gate lines; a plurality of parallel data lines orthogonal to the gate lines; a plurality of pixel electrodes; a plurality of thin film transistors, each of the thin film transistors positioned near a crossing of a corresponding gate line and a corresponding data line, each of the thin film transistors comprising a gate electrode coupled to the corresponding gate line, a source electrode coupled to the corresponding data line, and a drain electrode coupled to a corresponding one of the pixel electrodes; a plurality of gate driving circuits for driving the gate lines; a plurality of data driving circuits for driving the data lines; and a compensative unit having a first input terminal, a second input terminal, and a plurality of output terminals coupled to the data driving circuits, respectively; wherein the first and second input terminals are coupled to two nodes of one of the gate lines, the two nodes are coupled to two gate electrodes of two of the thin film transistors respectively connected to a selected two of the data driving circuits, and the compensative unit outputs a plurality of compensative voltages for compensating data voltage signals outputted by the data driving circuits, according to delays of two scanning signals received from the first and second input terminals, respectively, wherein the two nodes are a node “ where V where t