Patent ID: 6819729
Filing Date: 2004-11-16
Classification: H03K,H03L

Abstract:
An apparatus for generating a digital PLL pulse, comprising:a delay-chain section having a plurality of delay elements coupled in serial to form a plurality of delayed clock signals, delayed states of which are different relative to each other in respect to reference clock signals; a synchronized-signal detecting section to select a plurality of delayed clock signals out of said delayed clock signals formed by said delay-chain section, and to output synchronizing information being equivalent to a number of delay stages for one period based on said selected delayed clock signals; a pulse forming section to form an output pulse having a desired pulse width and a desired timing by selecting a desired delayed clock signal out of said delayed clock signals formed by said delay-chain section, based on said synchronizing information outputted by said synchronized-signal detecting section and pulse forming information for forming a desired pulse; a feedback section to receive a feedback pulse returned from an external device as a result of loading said output pulse onto said external device, and to detect a phase difference between said feedback pulse and said output pulse; and a correcting section to correct a timing of said output pulse formed by said pulse forming section in response to said phase difference detected by said feedback section.