Patent ID: 9118460
Filing Date: 2015-08-25
Classification: H03L,H03M,H04L

Abstract:
1. A clock and data recovery circuit, comprising: an analog-to-digital converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to modulate the first clock signal and thereby obtain a second clock signal having a second frequency, and inputs the second clock signal as the operation clock signal to the analog-to-digital converter; a phase detector that detects a second phase included in the output signal of the analog-to-digital converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase detected by the phase detector, and the third phase output from the filter; an adder that adds the first phase and the third phase obtained by the filter to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the analog-to-digital converter using the fourth phase obtained by the adder, wherein in the filtering process, the filter obtains the third phase that minimizes a phase difference between the second phase and the fourth phase.