Patent ID: 7880214
Filing Date: 2011-02-01
Classification: H01L

Abstract:
1. A nonvolatile semiconductor storage device comprising a plurality of cells organized within one or more erase block units, each cell comprising: a select gate provided in a first region on a substrate via a first insulator film; a floating gate provided in a second region adjacent to said first region via a second insulator film; a diffused region adjacent to said second region and provided in a third region on a surface of said substrate; and a control gate provided on said floating gate via a third insulator film, wherein all cells within an erase block unit can be selectively erased as a unit by applying a first voltage to the select gates located within said erase block and a second voltage applied to the control gates of said erase block unit, so that electrons are extracted from floating gates of said cells when an erase operation is performed, wherein select gates in an erase block unit are formed in a plurality of comb-like shapes in which, when viewed from a direction of a normal line to a plane, a plurality of comb teeth extend from a common line of the comb-like shape, wherein the comb teeth of a first select gate comb-like shape are arranged in gaps between the comb teeth of a second select gate comb-like shape at a predetermined spacing, and wherein the comb teeth of the first select gate comb-like shape extend to both sides of the common line of the first select gate comb-like shape and the comb teeth of the second select gate comb-like shape extend to both sides of the common line of the second select gate comb-like shape, in a direction orthogonal to the common line.