Patent ID: 6745358
Filing Date: 2004-06-01
Classification: G01R

Abstract:
A method for increasing a fault coverage of an integrated circuit having a predetermined functionality, the method comprising the steps of:providing an integrated circuit layout on a substrate including functional units, free space and a first netlist, providing a fault grading report output for the integrated circuit layout including a number of unobserved faults and identified undetected nodes, providing a priority task list for the integrated circuit layout of key undetected nodes from the identified undetected nodes, selecting key undetected nodes of the integrated circuit layout to be covered with logic functions, selecting multi-unit sites of the integrated circuit layout in the free space adjacent the key undetected nodes to provide a locations list for the logic functions for connection to the key undetected nodes, and generating a second netlist for the integrated circuit layout including the locations list for the logic functions.