Patent ID: 6049490
Filing Date: 2000-04-11
Classification: G11C

Abstract:
A decoded signal comparison circuit comprising:a plurality of decoders, each decoding address signals input in units of at least two bits, said address signals having bits which are input time-sequentially;a first register group including a plurality of first registers respectively provided for outputs from said plurality of decoders, each first register temporarily storing an output from the corresponding decoder;a second register group including a plurality of second registers respectively provided for the first registers of the first register group, each second register temporarily storing an output from the corresponding first register;a plurality of bit signal comparison circuits for comparing a pair of 1-bit signals input thereto, the pair of 1-bit signals consisting of the outputs from the first register of the first register group and the second register of the second register group, each bit signal comparison circuit being activated by one of the pair of 1-bit signals which is output from one of the first and second registers, said plurality of bit signal comparison circuits corresponding in number to pairs of first and second registers;a plurality of wired OR circuits respectively provided for said plurality of decoders, for obtaining a logical OR of signals output from said plurality of bit signal comparison circuits; anda global comparison circuit for detecting coincidence/non-coincidence of signals output from said plurality of wired OR circuits.