Patent ID: 6686242
Filing Date: 2004-02-03
Classification: H01L

Abstract:
A method for producing a memory cell array, said method comprising the following steps:a) providing a layer structure which comprises a silicon substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers, said sequence of said storage medium layers being an oxide-nitride-oxide layer sequence, and said gate region layer being of a polycrystalline silicon; b) producing bit line recesses in said gate region layer, said bit line recesses extending down to the storage medium layer; c) producing insulating spacer layers on lateral surfaces of said bit line recesses; d) removing the sequence of storage medium layers fully or partly in the area of the bit line recesses; e) executing a source/drain implantation in the area of said bit line recesses; f) removing the sequence of storage medium layers completely in the area of the bit line recesses, if said sequence of storage medium layers was not removed completely in step d); g) producing metallizations on the areas subjected to the source/drain implantation, so as to produce metallic bit lines, said metallizations being insulated from the gate region layer by the insulating spacer layers; h) filling the bit line recesses remaining after the production of the metallic bit lines with an insulating material; and i) producing word lines which extend substantially at right angles to said bit lines and which are each connected to a plurality of gate regions, said gate regions being produced when the word lines are being produced, by means of suitable patterning of the remaining parts of the gate region layer.