Patent ID: 6145044
Filing Date: 2000-11-07
Classification: G06F

Abstract:
A bus bridge controlling communication between a first bus and a second bus, the bus bridge comprising:a buffer memory;a transaction forward controller controlling a first transaction forward process for, when a first transaction including an address of a target device connected to the second bus is issued on the first bus,a) transmitting correspondingly stored data to the first bus when the address is stored in said buffer memory, andb) issuing a second transaction, corresponding to the first transaction, on the second bus, transmitting a control signal to the first bus to release the first bus, and receiving target data from the target device and holding the target data in said buffer memory for a time-out period if the address of the target device has not been stored in said buffer memory;judgment means for determining whether a second transaction forward process is necessary to avoid errors in the target data transferred to the first bus; andbus release restriction means for restricting transmission of the control signal for releasing the first bus, to the first bus by said transaction forward controller, when said judgment means determines that a second transaction forward process is necessary.