Patent ID: 6316362
Filing Date: 2001-11-13
Classification: H01L

Abstract:
A method for manufacturing a semiconductor including the steps of:forming a gate electrode layer made of polysilicon or amorphous silicon overlaying a semiconductor substrate;forming a gate electrode by etching said gate electrode layer;forming a side wall on a side surface of said gate electrode;consecutively ion-implanting and thermally treating said gate electrode and a surface portion of said semiconductor substrate to form the gate electrode as an N-type or P-type gate electrode and to form the surface portion as a diffused layer;forming a metal silicide layer on said N-type or P-type gate electrode and said diffused layer;wherein said gate electrode and said diffused layer having a surface impurity concentration between 1.times.10.sup.21 atoms/cm.sup.3 and 1.times.10.sup.22 atoms/cm.sup.3 are formed in the ion-implantation step.