Patent ID: 6204537
Filing Date: 2001-03-20
Classification: H01L

Abstract:
An integrated circuit device comprising:an integrated circuit pad;an internal integrated circuit conductively coupled to said integrated circuit pad so as to define a primary electrical path from said integrated circuit pad to said internal integrated circuit; andan ESD protection circuit conductively coupled to said integrated circuit pad so as to define a secondary electrical path from said integrated circuit pad to said ESD protection circuit, said ESD protection circuit comprising a semiconductor structure arranged to definea doped silicon substrate;a drain region formed in said silicon substrate, wherein said drain region is conductively coupled to said integrated circuit pad via said secondary electrical path,a source region formed in said silicon substrate, wherein said source region is conductively coupled to a relatively low electrical potential,an electrically insulating region formed in said silicon substrate between said drain region and said source region, anda gate structure conductively coupled to a relatively low electrical potential, whereinsaid gate structure is arranged to define an incipient inversion layer in said drain region, wherein said incipient inversion layer is defined upon application of a relatively high electrical potential to said integrated circuit pad, andsaid gate structure and said electrically insulating region are arranged to define an active gate region limited to extend from said drain region to said electrically insulating region.