Patent ID: 6631484
Filing Date: 2003-10-07
Classification: G06F

Abstract:
An interface unit adapted to bidirectionally interconnect a first device and a second device, the interface unit comprising:a first port adapted to connect to said first device so as to receive data packets from said first device and so as to transmit data packets to said first device; a second port adapted to connect to said second device so as to receive data packets from said second device and so as to transmit data packets to said second device; first FIFO storage; second FIFO storage; buffer storage; first port-receiving means responsive to said first port receiving a first data packet of a first characteristic and operable to store said first data packet of said first characteristic in a tail end location of said first FIFO storage, and responsive to said first port receiving a second data packet of a second characteristic and operable to store said second data packet of said second characteristic in said buffer storage and to store a corresponding buffer address in said tail end location of said first FIFO storage; first means responsive to a head end location of said first FIFO storage containing said first data packet of said first characteristic for fetching and processing said first data packet of said first characteristic, and responsive to said head end location of said first FIFO storage containing said corresponding buffer address for fetching said second data packet of said second characteristic from said buffer storage and processing said second data packet of said second characteristic; second port-receiving means responsive to said second port-receiving a third data packet of said first characteristic and operable to store said third data packet of said first characteristic in a tail end location of said second FIFO storage, and responsive to said second port receiving a fourth data packet of said second characteristic and operable to store said fourth data packet of said second characteristic in said buffer storage and to store a corresponding buffer address in said tail end location of said second FIFO storage; and second means responsive to a head end location of said second FIFO storage containing said third data packet of said first characteristic for fetching and processing said third data packet of said first characteristic, and responsive to said head end location of said second FIFO storage containing said corresponding buffer address for fetching said fourth data packet of said first characteristic from said buffer storage and processing said fourth data packet of said first characteristic.