Patent ID: 6233717
Filing Date: 2001-05-15
Classification: G06F,G11C

Abstract:
A multi-bit memory device, comprising:a plurality of memory cells, each of the memory cells operative to take on more than two data states;a plurality of sense amplifiers, operatively associated with the plurality of memory cells, that sense data states of the plurality of memory cells and generate data bits therefrom;a plurality of data latches, respective groups of which store data bits generated by respective ones of the plurality of sense amplifiers such that respective ones of the groups of data latches store respective multi-bit values representing respective data states; andmeans, operatively associated with the plurality of data latches, for checking data bits stored by a first subset of the plurality data latches corresponding to a first bit position of the stored multi-bit values and then checking data bits stored by a second subset of the plurality of data latches corresponding to a second bit position of the stored multi-bit values.