Patent ID: 6253333
Filing Date: 2001-06-26
Classification: G01R

Abstract:
An apparatus for automatically adjusting a synchronous timing clock signal for controlling data storage and retrieval operations in a time critical memory circuit interfaced with a memory control device, said control device and said time critical memory circuit operating at a required system clock rate specified for said control device, said apparatus comprising:(a) means for providing address, data, and control signals for input to said time critical memory circuit and for accessing data actually stored in said time critical circuit;(b) means for receiving data output signals of said time critical memory device based on previously input address, data, and control signals;(c) means for determining a timing condition of said time critical memory circuit and said control device in accordance with said received data output signals; and,(d) means for automatically adjusting arrival of an edge of said synchronous timing clock signal in accordance with a determined timing condition, said means iteratively adjusting said synchronous timing clock signal in time with respect to the input of said address and data signals in said time critical memory circuit to thereby alter data setup and hold time of said time critical memory device for both memory read and write operations until a desired timing condition is met, said adjusted synchronous timing signal being thereafter input to said time critical memory device for continued operations at said required system rate to thereby preserve system integrity.