Patent ID: 6790305
Filing Date: 2004-09-14
Classification: H01L,H05K,Y10S,Y10T

Abstract:
A method for producing small pitch z-axis interconnections in built-up layers of dielectric materials for electronic packages; comprising the steps of:providing at least two superimposed layers of said dielectric materials; applying a protective layer comprising a copper foil to respectively each of the external surfaces of said superimposed dielectric material layers; partially curing said dielectric material layers so as to bond said dielectric layers to each other; removing said protective copper foil layers from the external surfaces of said dielectric material layers; applying further protective layers selected from the group of materials consisting of polyester and polyvinylidene fluoride, to the external surfaces of said partially cured dielectric material layers; forming at least one via in said superimposed dielectric material and in said further protective layers; and removing said further protective layers from the surfaces of said dielectric material layers to provide relaminatable surfaces on said dielectric material layers facilitating lamination to diverse substrates.