Patent ID: 7543210
Filing Date: 2009-06-02
Classification: G01R

Abstract:
1. A semiconductor device, comprising: a clock buffer for generating an internal clock signal in response to a clock signal and a complementary clock signal in a first mode and generating the internal clock signal in response to the clock signal and a reference voltage in a second mode; first and second circuits for respectively generating first and second signals which have a constant phase and pulse width; a margin control signal generating circuit for generating a margin control signal having a varied phase and pulse width in response to the complementary clock signal and the reference voltage; a margin control circuit for receiving the second signal and the margin control signal, and transmitting the second signal in the first mode and transmitting the margin control signal in the second mode; and a third circuit for generating a third signal in response to the first and second signals in the first mode and generating the third signal in response to the first signal and the margin control signal in the second mode.