Patent ID: 8631371
Filing Date: 2014-01-14
Classification: G06F

Abstract:
1. A computer-implemented method for modeling parasitic capacitance associated with a diffusion region of a silicon-on-insulator (SOI) device, said method comprising: analyzing, by a computer, an integrated circuit design layout to at least identify side edges of said diffusion region that are capacitively coupled to adjacent conductive structures and determine distances from each of said side edges to said adjacent conductive structures, said analyzing further comprising identifying any corners where two of said side edges intersect; developing, by said computer, a formula for determining parasitic capacitance between said diffusion region and a substrate below said diffusion region, said formula having a perimeter component comprising at least a side edge component that is based on said distances and a corner component, said corner component being equal to zero when none of said side edges intersect; and using said formula to determine said parasitic capacitance.