Patent ID: 7051225
Filing Date: 2006-05-23
Classification: G11C

Abstract:
1. A memory system comprising a chip set and a module that includes a phase locked loop circuit, a register and a memory device, wherein said chip set supplies a first clock signal (CLK) and a command/address signal (termed CA signal) for said memory device to said module; said phase locked loop circuit receives said first clock output from said chip set to output a second clock signal (CLKd) supplied to said memory device at least; said register receives a third clock signal (CLKr) output from said phase locked loop circuit or said chip set to latch the CA signal output from said chip set to output the latched CA signal as a CA signal to be supplied to said memory device; and said memory device receives said second clock signal (CLKd) to latch the CA signal output from said register based on said second clock signal (CLKd), wherein the timings of the clock signals, input to respective clock input sections of said phase locked loop circuit, said memory device and the register are matched to one another, and wherein said register includes: a flip-flop for determining the output timing of said CA signal based on an internal clock signal (intCLK) generated from said third clock signal (CLKr) supplied to said register; and timing controlling means for temporally advancing the timing of the internal clock signal (intCLK) supplied to said flip-flop with respect to the timing of said third clock signal (CLKr) at the input section of said register by the sum of delay time since the internal clock signal (intCLK) are input to said flip-flop until the register outputs the CA signal and the delay time since the register outputs said CA signal until said CA signal reaches said memory device, said timing controlling means controlling an output timing of the CA signal from said register so that setup time margin and hold time margin of the CA signal with respect to said second clock signal in said memory device are equal to each other.