Patent ID: 6529435
Filing Date: 2003-03-04
Classification: G11C

Abstract:
A semiconductor memory device in which subblocks each constituted by one or two or more memory cells are arranged in matrix form, comprising:an address input circuit for receiving an input address; a readout circuit for reading out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via said address input circuit; and a refresh circuit for refreshing at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by said readout circuit; wherein the subblock group from which data is read out by said readout circuit includes a subblock storing parity data for restoring data, and said semiconductor memory device further comprises a data restoration circuit for restoring data of a subblock where the subblock group from which data is read out by said readout circuit intersects with the subblock group which is refreshed by said refresh circuit, based on the parity data and data of other subblocks.