Patent ID: 7480357
Filing Date: 2009-01-20
Classification: G06F,H04L

Abstract:
1. A system for effectuating the transfer of data blocks having intervals across a clock boundary between a first clock domain and a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, wherein N/M>1, comprising: a first circuit portion for providing said data blocks to a second circuit portion; a synchronizer controller disposed between said first and second clock domains for providing at least one dead cycle control signal to said second circuit portion, wherein said at least one dead cycle control signal is indicative of the location of at least one dead cycle between said first and second clock signal; and control logic associated with said second circuit portion for generating data transfer control signals responsive to said at least one dead cycle control signal, said data transfer control signals for controlling said second circuit portion whereby said data blocks are transmitted as contiguous data blocks relative to said at least one dead cycle, wherein said control logic is operable to generate data transfer control signals for transferring multi-channeled packet data, each channel's data blocks being interleaved with data blocks of other channels.