Patent ID: 8203898
Filing Date: 2012-06-19
Classification: G11C

Abstract:
1. An integrated circuit comprising: a control circuit configured to generate a first control signal to a memory circuit in the integrated circuit; and the memory circuit coupled to receive the first control signal, the memory circuit having a plurality of bit lines used to input data to the memory circuit and output data from the memory circuit, wherein the memory circuit is configured to float the plurality of bit lines responsive to an assertion of the first control signal received by the memory circuit, and wherein the memory circuit comprises a plurality of precharge circuits coupled to the plurality of bit lines and configured to precharge the plurality of bit lines, and wherein the memory circuit is configured to precharge the plurality of bit lines responsive to a deassertion of the first control signal, and wherein the memory circuit is configured to stagger an activation of the plurality of precharge circuits responsive to a deassertion of the first control signal.