Patent ID: 6310596
Filing Date: 2001-10-30
Classification: G09G,G11C

Abstract:
A serial access memory, comprising:a first memory cell array including a plurality of memory cells each storing data therein, and a plurality of first word lines for applying respective first selection signals to the respective memory cells;a second memory cell array including a plurality of memory cells each storing data therein, and a plurality of second word lines for applying respective second selection signals to the respective memory cells;a first data register, coupled to the first memory cell array, for latching the data transferred from the first memory cell array;a second data register, coupled to the second memory cell array, for latching the data transferred from the second memory cell array;a first address decoder, connected to the first memory cell array, for outputting the first selection signals selectively to the first word lines, so as to select any of the first word lines in response to first address data applied to said first address decoder;a second address decoder, connected to the second memory cell array, for outputting the second selection signals selectively to the second word lines, so as to select any of the second word lines in response to second address data applied to said second address decoder; anda control circuit, receiving address data that includes a most significant bit, the address data having a first portion which specifies addresses less than a predetermined address value and a second portion which specifies addresses equal to or greater than the predetermined address value, for converting the most significant bit of the address data to a predetermined bit value, applying the first portion of the address data, including the predetermined bit value, to the first address decoder as the first address data at a time that the data is transferred from the first and second memory cell arrays respectively to the first and second registers, and simultaneously applying the second portion of the address data, including the predetermined bit value, to the second address decoder as the second address data.