Patent ID: 8881090
Filing Date: 2014-11-04
Classification: G06F

Abstract:
1. A method for fabricating an integrated circuit, the method comprising: providing an integrated circuit design using a library of components defined in a native technology and having an associated reduced technological version; and fabricating the integrated circuit on a substrate, in the reduced technological version including at least a first dimensional compensation applied to a reduced channel length and to a reduced channel width for each transistor originating from a minimum transistor defined in the native technology by an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology, so as to obtain each transistor with a channel length equal, within a given tolerance, to the initial channel length and a channel width equal, within a given tolerance, to the initial channel width; wherein each transistor comprises an electrically active region within the substrate and a gate region including an electrically active gate region above of the electrically active region, and the first dimensional compensation applied to the reduced channel length comprises a widening of a reduced electrically active gate region, and the first dimensional compensation applied to the reduced channel width comprises a widening of a reduced portion of the electrically active region below the electrically active gate region.