Patent ID: 6584023
Filing Date: 2003-06-24
Classification: G11C

Abstract:
A system for implementing a column redundancy scheme for arrays with controls that span multiple data bits, said system comprising:an array of data bits for receiving data inputs; a spare data bit; a field control input line; circuitry to separate a field control signal from said field control input line into one or more individual control signals for activating a corresponding data bit in said array or for input into a multiplexor; circuitry to steer around a defective data bit in said array including: a field control signal multiplexor corresponding to each said field control signal; a spare control signal multiplexor to activate said spare data bit; a data multiplexor corresponding to each said data bit in said array; and a spare data multiplexor to steer one of said data inputs to said spare data bit; and programmable logic in communication with said field control signal multiplexor, said spare control signal multiplexor, said data multiplexor and said spare data multiplexor to cause said steer around to take place in response to detecting a defective data bit in said array of data bits.