Patent ID: 7627730
Filing Date: 2009-12-01
Classification: G06F,Y02D

Abstract:
1. A system comprising: a memory controller; a first register, wherein the first register is configured to store a first operating context, wherein the first operating context comprises a first set of timing parameters of the memory controller; and a second register, wherein the second register is configured to store a second operating context, wherein the second operating context comprises a second set of timing parameters of the memory controller, wherein the first and the second set of timing parameters each control a number of cycles required to execute instructions, such that the number of cycles is programmed to a desired number so that a time to complete a cycle is a desired time, wherein the memory controller is configured to use the second register while the first set of timing parameters are being modified in the first register, and wherein the first operating context is stored for a first operating frequency, wherein the second operating context is stored for a second operating frequency, and wherein the second operating frequency is lower than the first operating frequency.