Patent ID: 7900127
Filing Date: 2011-03-01
Classification: H03M,H04L

Abstract:
1. An apparatus, comprising: an input that receives an LDPC (Low Density Parity Check) coded signal; and an LDPC decoder that employs an LDPC matrix to decode the LDPC coded signal to make an estimate of an information bit encoded therein; and wherein: the LDPC matrix, composed of a plurality of sub-matrices each having a common size, is partitioned into a left hand side matrix and a right hand side matrix; each sub-matrix column of the left hand side matrix includes at least a first predetermined number of all zero-valued sub-matrices; each sub-matrix column of the left hand side matrix includes at most a second predetermined number of CSI (Cyclic Shifted Identity) sub-matrices; and each sub-matrix within the right hand side matrix is an all zero-valued sub-matrix except those sub-matrices identified below in (a) and (b):