Patent ID: 6029963
Filing Date: 2000-02-29
Classification: H01L

Abstract:
A semiconductor memory device, comprising:(a) a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type;(b) a cell array well of the first conductivity type formed on said deep well;(c) an isolation well of the second conductivity type formed around said cell array well and contiguous with said deep well so as to isolate said cell array well from said semiconductor substrate;(d) a circuit element, for driving a cell array, formed in said isolation well;(e) a memory cell and a second conductivity type channel element of a sense amplifier circuit formed in said cell array well on one side thereof;(f) a first conductivity type channel element of said sense amplifier circuit formed in said isolation well on one side thereof;(g) another second conductivity type channel element of another sense amplifier circuit formed in said cell array well on another side thereof; and(h) another first conductivity type channel element of said another sense amplifier circuit formed in said isolation well on another side thereof;wherein an arrangement of said first conductivity type channel element and said second conductivity type channel element on said one side is reversed to an arrangement of said another first conductivity type channel element and said another second conductivity type channel element on said another side.