Patent ID: 8042083
Filing Date: 2011-10-18
Classification: G06F

Abstract:
1. A method of FPGA rewiring of a circuit by using a computer, comprising: mapping the circuit into a first circuit, wherein the first circuit is logically represented with a plurality of look-up tables; rewiring the first circuit to obtain a second circuit, wherein a mapping area of the second circuit is less than that of the first circuit; mapping the second circuit into a third circuit, wherein the third circuit is logically represented with less look-up tables than the first circuit; and routing the third circuit to generate a FPGA architecture file related to the circuit, wherein the circuit is able to be re-constructed based on, at least in part, the generated file, and wherein the rewiring of the first circuit comprising: identifying a plurality of transformations in the first circuit, wherein each of the transformations comprises an alternative wire and a target wire; ranking all the identified transformations; checking the ranked transformations sequentially to determine transformations which will reduce the mapping area of the first circuit; and replacing each of the target wires with respective alternative wires in each of the determined transformations to generate the second circuit, wherein the method is, at least in part, performed using a computer.