Patent ID: 6518123
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method for fabricating a split gate field effect transistor (FET) device comprising:providing a semiconductor substrate having formed therein a pair of isolation regions which bounds a pair of opposite sides of an active region of the semiconductor substrate; forming upon the active region of the semiconductor substrate a tunneling dielectric layer; forming upon the tunneling dielectric layer and spanning over the pair of isolation regions an annular shaped floating gate electrode defining a central open annular region; forming upon the floating gate electrode an inter-gate electrode dielectric layer; forming upon the inter-gate electrode dielectric layer and filling the central open annular region a control gate electrode; and forming into the semiconductor substrate adjacent a pair of opposite edges of the floating gate electrode not bounded by the pair of isolation regions a pair of source/drain regions, wherein the annular shaped floating gate electrode is formed with a spacer shaped cross-section having a tip at its upper outer periphery.