Patent ID: 7392446
Filing Date: 2008-06-24
Classification: G01R

Abstract:
1. A system for testing an integrated circuit having programmable logic, the system comprising: a first output pad and a second output pad of the integrated circuit coupled to a common node to couple a test channel to the first output pad and the second output pad via the common node, the first output pad coupled to an output port of a first tri-state buffer, the second output pad coupled to an output port of a second tri-state buffer; an output port of a first register coupled to a control port of the first tri-state buffer and to an input port of a second register; an output port of the second register coupled to a control port of the second tri-state buffer and to an input port of a third register; an output port of the third register coupled to an input port of the first register; the first register and the second register coupled to receive a set signal to put the first register and the second register in a first state; the third register coupled to receive an inverted version of the set signal to put the third register in a second state; and the first register, the second register, and the third register coupled to receive a first clock signal.