Patent ID: 8572416
Filing Date: 2013-10-29
Classification: G06F,Y02D

Abstract:
1. A processing device comprising: a plurality of first processors; a plurality of second processors; a first chipset in communication with the plurality of first processors via a first bus; and a second chipset in communication with the first chipset via a second bus, wherein the second chipset is directly connected to the plurality of second processors, wherein the first chipset and the second chipset are connected between (i) the plurality of first processors and (ii) a first non-volatile memory and a second non-volatile memory, wherein the second chipset is connected between (i) the plurality of second processors and (ii) the first non-volatile memory and the second non-volatile memory, wherein the plurality of first processors are configured to access the first non-volatile memory during a first power mode, and wherein the plurality of second processors are configured to access the second non-volatile memory during a second power mode that is different than the first power mode.