Patent ID: 6724221
Filing Date: 2004-04-20
Classification: H03K

Abstract:
Circuitry having exclusive-OR and latch functionality, comprising:timing circuitry having a memory for storing a state and its complement, and having first and second timing circuitry portions, each of the portions being operable to receive at least one timing signal and being coupled to respective first and second nodes of the memory for timing pulling up and pulling down of the memory nodes; and logic circuitry having logic circuitry portions, wherein each of the logic circuitry portions are operable to receive at least first and second data signals and each has a conditionally conducting path, coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions, for controlling pulling up and pulling down the respective memory nodes responsive to the following conditions: i) the first data signal being asserted and the second data signal being de asserted or ii) the first data signal being de asserted and the second data signal being asserted.