Patent ID: 7530045
Filing Date: 2009-05-05
Classification: G06F

Abstract:
1. A computer-implemented method of creating device-partitions for placing a circuit design on a target device, the method comprising: subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition separated by a design-cutline using a graph-based partitioning technique; subdividing at least a portion of the target device into at least a first device-partition and a second device-partition separated by a device-cutline, wherein the first device-partition and the second device-partition correspond to physical regions on the target device for placing the first design-partition and the second design-partition, and wherein the target device is a programmable logic device comprising a number of pre-fabricated wires per unit length; determining a design-cutset corresponding to the design-cutline, wherein the design-cutset specifies a number of wires that cross the design-cutline within the circuit design; calculating a measure of required wire-bandwidth for the design-cutline according to the design-cutset; and increasing a length of the device-cutline according to the measure of required wire-bandwidth, thereby altering a perimeter of the first device-partition and perimeter of the second device-partition and increasing a number of available sites along the device-cutline within the first device-partition and the second device-partition, wherein a measure of wire-bandwidth of the device-cutline is proportional to length of the device-cutline and depends upon the number of pre-fabricated wires per unit length; and wherein increasing the length of the device-cutline further comprises changing a shape of the device-cutline according to a device-cutline shape selected from a plurality of device-cutline shapes, wherein different ones of the plurality of device-cutline shapes have different lengths and corresponding wire-bandwidths.