Patent ID: 7978548
Filing Date: 2011-07-12
Classification: G11C

Abstract:
1. A block decoding circuit of a semiconductor memory device, the block decoding circuit comprising: a plurality of block decoders, each of the plurality of block decoders being configured to decode a received block selection address and generate a first output signal corresponding to the received block selection address; a plurality of repair address check circuits, each of the plurality of repair address check circuits being configured to generate a second output signal based on whether the received block selection address and a word line selection address are repair addresses; a dummy repair address check circuit configured to generate a control signal in response to the received block selection address and the word line selection address; and a block selection signal generation circuit configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address check circuit, and the second output signals from the plurality of repair address check circuits.