Patent ID: 7714625
Filing Date: 2010-05-11
Classification: H03L

Abstract:
1. A circuit for reducing a re-lock time of a phase locked loop (PLL) comprising: a pattern generator adapted to generate serialized data signals; a capture control voltage module using the serialized data signals for capturing a control voltage when said PLL is in a lock mode; a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage when the PLL is turned on from a powered off state; a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances connected between a reference voltage and a ground voltage; a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage; and a timer module operatively coupled to the force control voltage module for turning off said force control voltage module after a pre-defined number of input cycles.