Patent ID: 6534361
Filing Date: 2003-03-18
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, Comprising:forming gate structures on a semiconductor substrate; forming a first dielectric layer covering the gate structures; forming a bit line on the first dielectric layer; forming a second dielectric layer covering the bit line; forming a buried contact through the second dielectric layer and the first dielectric layer in the region between adjacent ones of the gate structures, the buried contact being electrically connected to the semiconductor substrate; forming a third dielectric layer on the second dielectric layer; forming a lower electrode of a capacitor by patterning the third dielectric layer and forming an opening aligned with and exposing the buried contact, depositing an electrode material within the opening, and patterning the electrode material to form a lower electrode being electrically connected to the buried contact; forming and patterning, sequentially on the lower electrode, a dielectric layer and an upper electrode layer of the capacitor; forming a fourth dielectric layer covering the resulting capacitor; forming a plurality of contact holes through the fourth, third, second and first, dielectric layers to respectively expose the upper electrode layer, the bit line, the conductive pattern of one of the gate structures, and the semiconductor substrate, by selectively etching the fourth dielectric layer and the third, second, and first dielectric layers; and forming a plurality of metal contacts by filling the plurality of contact holes with a conductive material, the metal contacts being electrically connected to the upper electrode layer, the bit line, the conductive pattern of one of the gate structures, and the semiconductor substrate, wherein the forming of the plurality of contact holes comprises forming lower contact hole regions and upper contact hole regions, and before forming the third dielectric layer, the lower contact hole regions are formed by selectively etching the second dielectric layer and first dielectric layer to expose the bit line, the conductive pattern of one of the gate structures, and the semiconductor substrate, and wherein during the forming of the third dielectric layer, the third dielectric layer is formed of a material having discrete step coverage characteristics which cause voids to form within the plurality of lower contact hole regions while depositing the third dielectric layer over the second dielectric layer.