Patent ID: 6310821
Filing Date: 2001-10-30
Classification: G11C

Abstract:
A semiconductor device comprising:a memory cell array having a plurality of memory cells arranged in rows and columns;a specification section for receiving an address signal and designating a memory cell in said memory cell array;a data input/output section for inputuing data into a memory cell selected by said specification section and outputting the data from the memory cell selected by said specification section;a counting section for receiving a clock signal and counting a number of clock cycles of said clock signal; anda control section for receiving an output signal of said counting section and a first control signal, for outputting a plurality of said data in synchronism with said clock signal after said first control signal is asserted, a beginning of an output of said data being determined by an output signal of said counting section;wherein, whenever said first control signal is transitioned, said control section outputs from said data input/output section data of the number of clock cycles determined according to the output signal from said counting section and, output of said plurality of data is interrupted and data of another new group selected by said specification section is continuously output from said data input/output section.