Patent ID: 6925424
Filing Date: 2005-08-02
Classification: G06F

Abstract:
1. A method for counting performance events for a computing system, wherein the system includes i) a processor having a set of on-chip performance monitoring counter registers and ii) system memory, the method comprising the steps of: a) incrementing an N-bit value in one of the performance monitoring counter registers responsive to occurrences of a monitored event for a first processing thread so that the N-bit value provides a measured value for the event in association with the thread; b) merging the N-bit value of the counter register for the first processing thread into an N+M-bit value in an accumulator in system memory, wherein the merging is responsive to a switch from the first thread to a second thread; and c) restoring the N-bit value for the first thread to the counter register from the accumulator responsive to a switch back to the first thread, wherein despite any thread switches the restoring maintains a value in the counter register for the first thread that is coherent relative to a previous value in the counter register for the first thread and the merging of the N-bit value into the accumulator maintains a coherent value for the larger, N+M-bit accumulated value.