Patent ID: 7376006
Filing Date: 2008-05-20
Classification: G11C

Abstract:
1. A nonvolatile memory array, comprising: a plurality of bit lines and word lines; and a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array, at least one of the memory cells comprising: a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a corresponding first one of the bit lines; and a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a corresponding second one of the bit lines, and the gate connecting to a corresponding one of the word lines; wherein storing a logic state of the memory cell comprises applying an electrical current through the storage element; and wherein a logic state of the bipolar programmable storage element is written by substantially concurrently applying a logic high voltage potential to the word line, applying a logic high voltage potential to one of the first and second bit lines, and applying a logic low voltage potential to another of the first and second bit lines, a polarity of a voltage potential across the first and second bit lines being indicative of the logic state to be written into the memory cell.