Patent ID: 8380914
Filing Date: 2013-02-19
Classification: G11C

Abstract:
1. A method of providing extended memory addressing in a compatible manner, the method comprising: in a serial flash memory device in which both addresses and data are communicated serially, initially entering a default addressing mode corresponding to a standard upon power-up for conformity with the standard, wherein addressing with the default addressing mode permits addressing of only a subset of memory locations of the serial flash memory device, wherein the subset of memory locations is smaller than the total memory locations; performing read and write memory operations at the serial flash memory device using the default addressing mode when no command for an extended addressing mode is received; entering the extended addressing mode and performing read and write memory operations at the serial flash memory device using the extended addressing mode comprising an extended number of address bits providing access to a set of memory locations larger than and including the subset of memory locations at least in part in response to receiving an address length configuration command code from a processor; and serially receiving addresses for the read and write memory operations from the processor.