Patent ID: 7339592
Filing Date: 2008-03-04
Classification: G06F

Abstract:
1. A method of simulating a single multiport memory using a plurality of single port memories providing registers for storing operands for execution by one of a plurality of threads, and allocating the registers into memory banks, each of the banks being associated with at least one of the threads, comprising: determining a number of registers allocated for a first one of the threads; allocating the number of registers for the thread to locations in at least one memory bank of a set of memory banks configured to simulate the single multiported memory; assigning the registers so that the first and second threads are enabled to process the same program instruction without the corresponding operands specified by the same program instruction being stored in the same bank; repeating the determining and allocating steps for a second one of the threads; reading a first operand specified by a program instruction within the second thread from a register within the set of memory banks into a first associated collector; reading a second operand specified by the program instruction within the first thread from a register within the set of memory banks into a second associated collector; and dispatching the program instruction, the first operand, and the second operand from each of the first and second associated collectors to the first and second threads for execution so that the speed of execution of each of the threads is not reduced by use of the lower port count memories.