Patent ID: 8699273
Filing Date: 2014-04-15
Classification: G11C

Abstract:
1. A method comprising: providing a target memory cell for a write operation in a non-volatile memory array; driving a first bitline coupled to a first source/drain terminal of the target memory cell to a first voltage during the write operation; driving a second bitline coupled to a second source/drain terminal of the target memory cell to a second voltage during the write operation; and driving a third bitline coupled to a first source/drain terminal of an untargeted neighbor memory cell in the nonvolatile memory array to a third voltage during the write operation of the target memory cell; wherein the second voltage comprises a first predetermined waveform and the third voltage comprises a second predetermined waveform, the first and second predetermined waveforms being offset from each other by a predetermined voltage difference; wherein the predetermined voltage difference is less than a minimum voltage difference to enable a write operation at the untargeted neighbor memory cell.