Patent ID: 8190852
Filing Date: 2012-05-29
Classification: G06F

Abstract:
1. A virtualization system comprising: a plurality of sections, each section of the plurality of sections including a processing circuit, wherein a first section of the plurality of sections is configured to store first mapping information, and a second section of the plurality of sections is configured to store second mapping information, each of the first and second mapping information including a relationship between first volume identification information, which is used by a computer system to access a virtual volume in the virtualization system, and second volume identification information for identifying a first logical volume of a first storage device, the first storage device having a first disk controller and a plurality of first disk drives related to the first logical volume, the relationship being used for transferring data, which is sent from the computer system and is related to the first volume identification information, to the first logical volume, wherein the virtualization system receives the data, which is sent from the computer system and is related to the first volume identification information, during a data transfer phase in which data stored in the first logical volume is transferred to a second logical volume of a second storage device, the second storage device having a second disk controller and a plurality of second disk drives related to the second logical volume, and wherein the data received during the data transfer phase is adapted to be written to the second logical volume, wherein the virtualization system changes the relationship and transfers the data, which is sent from the computer system and is related to the first volume identification information, to the second logical volume, the changed relationship relating the first volume identification information to third volume identification information for identifying the second logical volume, and wherein the plurality of sections are a plurality of port sections comprising the processing circuit and an interface control part, the interface control part being configured to be coupled to at least one of the computer system and the first and second storage devices.