Patent ID: 9048160
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method of fabricating a thin-film transistor, the method comprising: providing a substrate; forming an active layer over a surface of the substrate; forming a dielectric layer on the active layer; patterning the dielectric layer using a first mask, including exposing regions of the active layer, the patterned dielectric layer comprising a continuous patterned dielectric segment, the dielectric segment comprising a first patterned dielectric portion and a second patterned dielectric portion, the first patterned dielectric portion defining a thin-film transistor region on the active layer and the second patterned dielectric portion defining a gate pad region thereon; forming a conductive layer on the exposed regions of the active layer, on the first patterned dielectric portion, and on the second patterned dielectric portion; patterning the conductive layer and the exposed regions of the active layer using a second mask, including exposing parts of the first patterned dielectric portion and removing some of the exposed regions of the active layer to expose the substrate, the patterned conductive layer comprising a first continuous patterned conductive portion on a first section of the active layer, a second continuous patterned conductive portion on a second section of the active layer, and a third continuous patterned conductive portion on both the first and the second patterned dielectric portions, the first, second, and third continuous patterned conductive portions spaced apart from each other and each overlapping a different part of the first patterned dielectric portion; forming a passivation layer on the substrate, on the patterned conductive layer, and on the exposed parts of the first patterned dielectric portion; and patterning the passivation layer using a third mask, including forming windows through the passivation layer, a first one of the windows exposing a section of the first patterned conductive portion, a second one of the windows exposing a section of the second patterned conductive portion, and a third one of the windows exposing a section of the third patterned conductive portion.