Patent ID: 6859917
Filing Date: 2005-02-22
Classification: H03K

Abstract:
1. A method of designing a semiconductor integrated circuit by using a first logic gate and a second logic gate in which substrate potentials of MIS transistors of the same conduction type are equal to each other, comprising: a first step of determining whether a signal propagation delay time of a signal path in a logic circuit designed by using the first logic gate using, as an operation power source, a first pair of potentials having a relatively small potential difference achieves a target time; and a second step of replacing one or a plurality of said first logic gates included in a signal path having a signal propagation delay time which does not achieve the target time in said first step with a said second logic gate using, as an operation power source, a second pair of potentials having a relatively large potential difference, wherein the first and second logic gates each include portions of a first pair of potential lines that supplies the first pair of potentials, portions of a second pair of potential lines that supplies the second pair of potentials, and portions of a third pair of potential line supplies the substrate potentials.