Patent ID: 6091087
Filing Date: 2000-07-18
Classification: H01L

Abstract:
An insulated gate thyristor comprising;a first-conductivity-type base layer;first and second second-conductivity-type base regions formed in selected areas of a surface layer of a first major surface of said first-conductivity-type base layer, said first second-conductivity-type base region including a second-conductivity-type well region;a first-conductivity-type source region formed in a selected area of a surface layer of said first second-conductivity-type base region;a first-conductivity-type emitter region formed in a selected area of a surface layer of said second second-conductivity-type base region;a gate electrode formed through a gate insulating film on a surface of said first second-conductivity-type base region, an exposed portion of said first-conductivity-type base layer, and a surface of said second second-conductivity-type base region, which surfaces and exposed portion are interposed between said first-conductivity-type source region and said first-conductivity-type emitter region;a first main electrode that contacts both an exposed portion of said first second-conductivity-type base layer and said first-conductivity-type source region;a second-conductivity-type emitter layer formed on a second surface of said first-conductivity-type base layer;a second main electrode that contacts said second-conductivity-type emitter layer; andan insulating film covering entire areas of surfaces of said second second-conductivity-type base region and said first-conductivity-type emitter region; whereinsaid second second-conductivity-type base region has a diffusion depth that is smaller than a larger one of diffusion depths of said first second-conductivity-type base region and said second-conductivity-type well region.