Patent ID: 7254668
Filing Date: 2007-08-07
Classification: G06F

Abstract:
1. A memory system comprising: a non-volatile memory, the non-volatile memory including a first physical block, the first physical block including a plurality of physical pages, the plurality of physical pages being grouped into a plurality of physical groups, wherein each physical group of the plurality of physical group includes two or more physical pages; code devices for mapping a first logical block to the first physical block, the first logical block corresponding to a plurality of logical pages grouped into a plurality of logical groups, each logical group of the plurality of logical groups including two or more logical pages; code devices for writing input data into a first physical page included in a first physical group of the first physical block responsive to the input data being associated with a first logical page in a first logical group of the first logical block; wherein the code devices for writing input data are also for writing input data into a first physical page included in a second physical group responsive to then receiving input data associated with a first logical page in a second logical group of the first logical block, and for writing input data into a second physical page in a third physical group of the first physical block responsive to then receiving input data associated with a second logical page in the first logical group; and further comprising: