Patent ID: 6336207
Filing Date: 2002-01-01
Classification: G06F

Abstract:
A LSI layout designing method comprising the steps of:arranging cells in parallel to one another based on circuit design information and routing the cells so as to form a block layout; interchanging a cell in question included in the block layout with a substitute cell so as to satisfy required specifications, the block layout including a plurality of cell rows arranged in parallel to each other, wherein in the interchanging step, the cell in question is interchanged with the substitute cell by using a stretchable cell library as a cell library comprising a set of cells to be arranged, wherein cells in the stretchable cell library, which have equivalent logic and different levels of drivability, being provided with such a cell layout that widths and terminal positions of the cells are equal to each other in a cell arrangement direction on each said cell row, and wherein cell arrangement and routing is not performed after said cell interchange step.