Patent ID: 6472727
Filing Date: 2002-10-29
Classification: H01L,Y10T

Abstract:
A semiconductor device comprising:a semiconductor chip having a rectangular main surface bounded by first and second sides extending in a first direction, and by third and fourth sides extending in a second direction, perpendicular to said first direction, and having a row of external terminals, extended in the first direction, formed on the main surface; a first array of bump electrodes formed between the row of external terminals and the first side of the main surface, in a plan view of the main surface; a second array of bump electrodes formed between the row of external terminals and the second side of the main surface, in the plan view of the main surface; an elastic layer including a first portion and a second portion, wherein the first portion of the elastic layer is interposed between the first array of bump electrodes and the main surface of the semiconductor chip, and the second portion of the elastic layer is interposed between the second array of bump electrodes and the main surface of the semiconductor chip; first wirings, formed on the first portion of the elastic layer, electrically connecting the first array of bump electrodes with the row of external terminals; and second wirings, formed on the second portion of the elastic layer, electrically connecting the second array of bump electrodes with the row of external terminal, wherein the first portion of the elastic layer covers a continuous area over a part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said first portion are extended in the first direction, the first end is located between the first array of bump electrodes and the row of external terminals, in the plan view, and the second end is opened, and wherein the second portion of the elastic layer covers a continuous area over another part of the main surface of the chip and is bounded, in the second direction, by first and second ends thereof, the first and second ends of said second portion are extended in the first direction, the first end thereof is located between the second array of bump electrodes and the row of external terminals, in the plan view, and the second end thereof is opened.