Patent ID: 6048738
Filing Date: 2000-04-11
Classification: G11C,H01L

Abstract:
A method of forming a semiconductor memory device on a silicon substrate, comprising:implanting doping impurities of a first conductivity type in the silicon substrate to form a conductive channel of a first conductivity type for use as a gate region;forming a MOS capacitor on the conductive channel of the first conductivity type, said MOS capacitor having a predetermined surface area;depositing an FEM capacitor over the MOS capacitor to form a stacked gate unit, including depositing a lower metal layer on said MOS capacitor, said lower metal layer providing a lower electrode of said FEM capacitor and an upper electrode of said MOS capacitor;depositing a FE layer, and an upper metal layer to complete said FEM capacitor, the surface area of said FEM capacitor being less than said predetermined surface area of said MOS capacitor, whereby said stacked gate unit is in the form of an offset gate;implanting doping impurities of a second conductivity type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second conductivity type for use as a source junction region and a drain junction region; anddepositing an insulating structure about the FEM gate unit.