Patent ID: 8263470
Filing Date: 2012-09-11
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor, the method comprising: forming a first bipolar transistor including an emitter region, a base region, and a collector region on a semiconductor substrate; forming a second bipolar transistor including an emitter region, a base region, and a collector region on the semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region configured to establish an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, contact holes for establishing contact with each of those regions, the contact holes including contact holes to the emitter region, the collector region, and the base region, respectively; and embedding a conductive member in the contact holes; wherein at least one of the contact holes to the at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor, on which the dummy layer is formed, is formed with a shallower contact depth than the contact hole of at least one region of the emitter region, the base region, or the collector region of the first bipolar transistor.