Patent ID: 7852645
Filing Date: 2010-12-14
Classification: H02J,Y02B,Y04S

Abstract:
1. A circuit for reducing power consumption in a power transformer during low-load and no-load conditions, the circuit comprising: a first solid state switching device coupled to an input of the power transformer, said first solid state switching device being configured to disengage said power transformer from a power source upon detecting said no-load and low-load conditions on said power transformer; a second solid state switching device coupled to an output of said power transformer a rectifier coupled to an output of said power transformer, said rectifier being configured to rectify an output voltage of said power transformer; a super capacitor coupled in parallel to an output of said rectifier , said super capacitor being configured to store energy during a load condition and further being configured to provide energy during said low-load and no-load conditions; a voltage sense module coupled to said super capacitor and configured to monitor continuously a voltage on said super capacitor and to output a first control signal upon detecting a low voltage condition on said super capacitor; a current sense module coupled to an output of said power transformer, said current sense module being configured to detect a load on said power transformer and to output a second control signal upon detecting said load condition, and a control circuit configured to receive said first control signal from said voltage sense module and to receive said second control signal from said current sense module and to output a close switch signal to said first and second solid state switching devices in response to receiving said first and second control signals; wherein the voltage sense module and the current sense module receive power from the super capacitor.