Patent ID: 8995214
Filing Date: 2015-03-31
Classification: G06F,G11C

Abstract:
1. A nonvolatile semiconductor memory comprising: a memory cell array; a temporary storage area which temporarily stores data in a read/write operation to the memory cell array; and a control circuit which controls a transfer of the data in the temporary storage area, wherein the temporary storage area comprises: a first data bus; a second data bus; a clamp FET connected between the first data bus and the second data bus; a first precharge FET connected between the first data bus and a first potential; a second precharge FET connected between the second data bus and the first potential; a first storage area connected to the first data bus; and a second storage area connected to the second data bus, wherein the control circuit is configured to: generate a first precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, by turning the clamp FET and the first precharge FET on and turning the second precharge FET off, when the data is transferred from the second storage area to the first storage area; change the first data bus and the second data bus from the first precharge state to a first floating state by turning the first precharge FET off; output the data from the second storage area to the second data bus with the first floating state; and input the data from the first data bus with the first floating state to the first storage area.