Patent ID: 8765572
Filing Date: 2014-07-01
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth, wherein portions of the first insulating layer formed at sidewalls of the gate patterns are spaced apart by a first distance; etching the first insulating layer such that the portions of the first insulating layer formed at the sidewalls of the gate patterns are spaced apart by a second distance larger than the first distance, wherein the etched portion of first insulating layer having the second spaced apart distance is closer to the substrate than the etched portion having the first spaced apart distance; and forming a second insulating layer on the gate patterns and the first insulating layer, wherein a low-dielectric-constant material is formed between the gate patterns.