Patent ID: 6018621
Filing Date: 2000-01-25
Classification: G06F

Abstract:
A method for optimizing the design a logic network, comprising the steps of:a) identifying, by a computer system analyzing an initial network design, logic gates of certain types within the initial network design;b) converting, by the computer system, any gates of other types to the certain types of gates;c) identifying, by the computer system in response to reconvergent fanout nodes in the network, each such node defining a loop having two branches which diverge at the node and converge thereafter, a region in the converted network for optimization;d) selecting within the region, by the computer system, some of the inverting gates of at least one of the certain types for moving to the network inputs;e) selecting within the region, by the computer system, others of the inverting gates of the at least one certain type for moving to the network outputs.