Patent ID: 8107746
Filing Date: 2012-01-31
Classification: H04N

Abstract:
1. An image processor decoding plural sets of data included in plural blocks, each of the blocks including plural sets of data, each set of the data including upper data in an upper digit range and lower data in a lower digit range, the image processor receiving data stream including a group of upper data of a first block, a group of lower data of the first block and a group of upper data of a second block aligned in this order, the image processor comprising: a first processing unit including a plurality of decoding units and decoding a group of upper data; a second processing unit decoding a group of lower data; and a selecting unit selecting one of the plurality of decoding units, wherein the plurality of decoding units perform decoding of the group of upper data of the second block, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of lower data of the first block by the second processing unit, and the selecting unit selects, from the plurality of decoding units, one decoding unit with a start position of decoding being set at a position immediately following an end position of the group of lower data of the first block, based on a result of decoding of the group of lower data of the first block by the second processing unit.