Patent ID: 6898109
Filing Date: 2005-05-24
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines extending in a direction intersecting the word lines; a plurality of dynamic memory cells each disposed at an intersection of the word lines and the bit lines and having a transfer gate and a capacitor, the transfer gate composed of a MOS transistor, one end of the transfer gate in the dynamic memory cell being connected to one of the bit lines, the other end being connected to a storage node of the capacitor and a gate of the MOS transistor being connected to one of the word lines; and a first wiring pattern for shielding disposed in each space between adjacent bit lines of the plurality of bit lines, the first wiring pattern extending parallel to the adjacent bit lines and formed in the same wiring layer as that of the adjacent bit lines.