Patent ID: 6087199
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method, comprising:providing a carrier substrate including a plurality of surface projections having sloping sidewalls;providing a plurality of chips having bottom faces forming surface depressions with beveled edges matching and being in conformal juxtaposition with the sloping sidewalls, the plurality of chips also forming top faces at sides opposite the bottom faces, portions of at least two of the top faces lying substantially in at least two planes separated by a minimum distance (D) in a range of 0.0 .mu.m<D.ltoreq.2 .mu.m, at least two of the chips being separated by a gap (G) having a minimum spacing in a range of 1 .mu.m<G.ltoreq.100 .mu.m, andproviding at least one metallic interconnect disposed over the portions and the gap.