Patent ID: 8060756
Filing Date: 2011-11-15
Classification: G06F

Abstract:
1. An address encryption/decryption system for address encryption and address decryption within a electronic system, comprising a memory subsystem, the address encryption/decryption system comprising: (a) at least one electronic scrambler device in a write data path of the memory subsystem, the electronic scrambler device being adapted for encrypting physical memory addresses generated within the electronic system to produce encrypted physical memory addresses according to which data will be located in the memory subsystem of the electronic system during operations that write to the memory subsystem, and (b) at least one separate electronic descrambler device in a read data path of the memory subsystem, the electronic descrambler device being adapted for decrypting the encrypted physical memory addresses upon request from the electronic system for the data associated with the corresponding unencrypted physical memory addresses, thereby allowing retrieval of the data during operations that read from the memory subsystem, whereby the physical location of data in the memory subsystem is hidden from other subsystems of the electronic system, and such data is therefore unretrievable in coherent form by the other subsystems or by intruders who have gained access to and control over the other subsystems, whether over a network or by unauthorized local intrusion, unless the decryption has been performed.