Patent ID: 7217628
Filing Date: 2007-05-15
Classification: H01L

Abstract:
1. A method of fabricating complementary bipolar vertical NPN and PNP transistor structure in a wafer, having an NPN collector, base, and emitter region, and a PNP collector, base, and emitter region, said method comprising: forming a p-well and an n-region subcollector in said wafer along isolation trenches; implanting p+ and n+ collector reach through implants; applying a silicon germanium LTE layer and PNP base mask layer, wherein said silicon germanium LTE layer is formed on said p-well and said n-subcollector; forming a first photoresist mask to protect said p+ collector reach through implant, said n+ collector reach through implant, and said isolation trenches during implanting; implanting an n-type PNP base/collector within said silicon germanium LTE layer; patterning a barrier oxide etch stop layer over said silicon germanium LTE layer including patterning an opening in said etch stop layer over a PNP base/collector region and a portion of said etch stop layer over said NPN base/collector region; growing a p+ polysilicon or p+ silicon layer over said etch stop layer; depositing a barrier oxide layer on said p+ polysilicon or p+ silicon layer; patterning and etching said barrier oxide layer over said NPN base/collector layer; depositing an n+ polysilicon layer or n+ silicon layer over said barrier oxide layer; patterning and etching said n+ polysilicon or n+ silicon layer; forming a second photoresist mask over said barrier oxide layer and unprotected portions of said p+ polysilicon layer or p+ silicon layer, and removing portions of said oxide layer by etching to said etch stop layer; forming a nitride spacer on sides of said PNP base and emitter and said NPN base and emitter; forming a mask over said PNP base and emitter, said NPN base and emitter, and a portion of said silicon germanium LTE layer up to said isolation trenches; removing unprotected portions of said silicon germanium LTE layer and said etch stop layer by a etch process; removing said etch stop layer to expose said silicon germanium LTE layer in all remaining areas except where said PNP and NPN bases and emitters reside; patterning said structure with a third photoresist mask over said isolation trenches; implanting exposed regions for an n+ region for said PNP extrinsic base; and depositing contacts for collectors, bases, and emitters of said PNP and NPN structures.