Patent ID: 7913202
Filing Date: 2011-03-22
Classification: G11C

Abstract:
1. A design structure embodied in a machine readable medium for designing, manufacturing, and testing a 3-D chip, the design structure comprising data representing features of a 3-D semiconductor integrated circuit device including a core structure, at least one I/O layer, said at least one I/O layer being layered with said core structure, and a vertical bus connecting said core layer and said I/O layer, said at least one I/O layer including and at least one, which, when said design structure is applied to a design process embodied in a computer, provides synthesis of a netlist, a translation of a netlist into another design structure which resides on a computer readable medium in a data format suitable for exchange of layout data of integrated circuits or provides control signals for controlling automated apparatus for carrying out a process for manufacture, repair or testing of said 3-D semiconductor integrated circuit device.