Patent ID: 6378060
Filing Date: 2002-04-23
Classification: G06F

Abstract:
A cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2n-bit input source word to be switched into any bit position of a 2m-bit output destination word and (2) provides the ability to set-to-zero any bit in said 2m-bit output destination word, said cross-bar circuit comprising:a switch circuit comprising 2m 2n:1 multiplexor circuits, wherein each of said 2n:1 multiplexor circuits (a) has a unique n-bit index input, one disable input, and a 2n-bit wide source input, (b) receives (i) an n-bit index at said n-bit index input, (ii) a disable bit at said disable input, and (iii) said 2n-bit input source word at said 2n-bit wide source input, and (c) decodes said n-bit index either (i) to select and output as an output destination bit one bit from said 2n-bit input source word if said disable bit has a logic low value or (ii) outputs a logic low as said output destination bit if said disable bit has a logic high value; a cache memory that (a) has 2m cache datapath inputs and 2m cache index inputs, (b) receives (i) said datapath information on said 2m cache datapath inputs and (ii) 2m n-bit indexes on said 2m cache index inputs, (c) provides a first set of said n-bit indexes for said switch circuit, and (d) comprises a small tightly coupled memory array that stores p entries of 2m n-bit indexes for said switch circuit, said cache memory being logically coupled to said switch circuit; and a control circuit that (a) has a plurality of control inputs, (b) receives said partially-decoded instruction information on said plurality of control inputs, (c) provides a second set of said n-bit indexes for said switch circuit, and (d) provides said disable bits for said switch circuit, said control circuit being logically coupled to said switch circuit and to said cache memory.