Patent ID: 6577674
Filing Date: 2003-06-10
Classification: H04B,H04L

Abstract:
A channel compensator for use in a receiver of a direct sequence code division multiple access (DS-CDMA) communication system for compensating for a phase change and a residual frequency offset of received input signals propagated along different paths and received at said receiver, wherein the system has a predetermined process gain and a corresponding chip rate determined by the processing gain, said channel compensator comprising:a first integrator for sampling said received input signals at said chip rate, for periodically accumulating said received input signals sampled by said first integrator for a predetermined time, and for multiplying the accumulated received input signals by said predetermined process gain to produce output signal in chip unit; a shift means having a plurality of shift registers for shifting and assigning said output signal from said first integrator to said shift registers; and, a second integrator for periodically integrating for said predetermined time the output data generated from said plurality of shift registers.