Patent ID: 6078621
Filing Date: 2000-06-20
Classification: H03H,H03M

Abstract:
A signal processor for 1-bit signals, comprising an nth order (where n is greater than or equal to 1) Delta Sigma Modulator (DSM) havinga first input for receiving a first 1-bit signal,a second input for receiving a second 1-bit signal,a quantizer for requantizing a p bit signal to 1-bit form the requantized signal being the output signal of the processor,a plurality of signal combiners includinga first combiner for forming an integral of an additive combination of the product of the first signal and a first coefficient and of the product of the second signal and a second coefficient and of the product of the output signal and a third coefficient,at least one intermediate combiner for forming an integral of an additive combination of the product of the first signal and a first coefficient and of the product of the second signal and a second coefficient and of the product of the output signal and a third coefficient and of the integral of the preceding stage, anda final combiner for forming an additive combination of the product of the first signal and a first coefficient and of the product of the second signal and a second coefficient and of the integral of the preceding stage to form the said p bit signal which is requantized by the quantizer.