Patent ID: 6107763
Filing Date: 2000-08-22
Classification: H02P

Abstract:
A synchronizing circuit for phase switchings of a multiphase brushless motor according to a profile stored in a form of N number of digital samples, and being selectively switchable to an open loop or closed loop mode of operation, comprising:sensing means for sensing an instantaneous position of rotor of the motor and generating a synchronizing pulse responsive thereto;a frequency divider for a master clock signal outputting a derived clock signal having a period divided by an N factor;a first resettable counter receiving the derived clock signal;a second resettable counter receiving the master clock signal;a third resettable counter having an output for pointing to one of the stored N number of digital samples;a first register having a reset input, the first register storing an output of said first resettable counter responsive to a synchronizing pulse from said sensing means received on the reset input;a comparator comparing the output of said first register with contents of the second resettable counter and generating a reset pulse for said second resettable counter when the compared information is equal and for generating an incrementing pulse for the third resettable counter;a programming register storing programmed data;a demultiplexer for receiving an output from said programming register;a multiplexer connected to said demultiplexer and said first resettable counter for selectively providing one of an output of said demultiplexer and an output of said first resettable counter to an input of said first register; anda forced synchronizing pulse generating circuit enabled by a logic command for generating a forced synchronizing pulse responsive to receiving a pulse from said third resettable counter when said third resettable counter reaches a value N-1, said forced synchronizing pulse forcausing a loading of data from said programming register into said first register during open loop mode operation,causing a resetting of said first resettable counter, andcausing said multiplexer to selectively provide one of the output of said demultiplexer and the output of said first resettable counter to the input of said first register.