Patent ID: 6279071
Filing Date: 2001-08-21
Classification: G11C

Abstract:
A random access memory comprising:a column counter responsive to an external address for producing a column address;a command decoder responsive to an external command for producing at least one of a column decode enable signal and a write enable signal;an address decoder responsive to the column address and column decode enable signal for producing a decoded column address signal used to select a column line, the address decoder having a column address latch for latching the decoded column address signal to prevent the decoded column address signal from being modified when the column address changes; anda write driver supplied with an input data signal representing data to be written in a selected memory cell and responsive to the write enable signal, the write driver having a first data latch controlled by the write enable signal for latching the input data signal and a second data latch coupled to said first data latch for latching a first data signal supplied from said first data latch.