Patent ID: 6524902
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of manufacturing a CMOS semiconductor device comprising the steps of:forming a gate insulating layer on a substrate; forming a SiGe layer having Ge content of more than 20% on said gate insulating layer; forming a silicon layer on said SiGe layer; forming an ion implantation mask on said silicon layer to cover at least one PMOS transistor region; performing a n-type impurity ion implantation process on at least one NMOS transistor region of said substrate having said ion implantation mask; performing a diffusion and annealing process on said substrate in which n-type impurities are implanted to diffuse germanium into the silicon layer in the NMOS transistor region such that a desired germanium dopant profile is produced in the SiGe layer and the silicon layer in the NMOS transistor region, while germanium is substantially prevented from diffusing into the silicon layer in the PMOS transistor region; and forming a gate pattern for PMOS and NMOS transistors by patterning said silicon layer and said SiGe layer.