Patent ID: 7657767
Filing Date: 2010-02-02
Classification: G06F,G11C,Y02D

Abstract:
1. An apparatus comprising: a sleep and shut-off circuit coupled between a virtual supply terminal and a first physical supply terminal to reduce leakage from a cache sub-array when the cache sub-array is disabled in a shut-off mode, the shut-off mode being different than a sleep mode, the cache sub-array being coupled between the virtual supply terminal and a second physical supply terminal; and an active circuit coupled to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode; wherein the sleep and shut-off circuit comprises: a plurality of transistors of a transistor type coupled in parallel having different sizes to provide variable reduced power consumption according to the standby mode; and a control circuit coupled to the plurality of transistors to selectively turn off the transistors providing the variable reduced power consumption.