Patent ID: 8868989
Filing Date: 2014-10-21
Classification: G01R,G06F

Abstract:
1. A system for testing an error detection circuit by injecting a fault into the error detection circuit, wherein the error detection circuit receives first and second output signals generated by first and second processors, the system comprising: an inverter for receiving an input signal and generating an inverted input signal; a first logic gate for receiving test mode and fault injection mode signals and generating an input selection signal based on the test mode and fault injection mode signals; and a mux having a first input terminal that receives one of the input signal and a scan input signal, a second input terminal connected to the inverter and receiving the inverted input signal, a select input terminal connected to the first logic gate and receiving the input selection signal, and an output terminal for providing one of the input signal, scan input signal and inverted input signal, wherein the mux output terminal is connected to the second processor and the second processor generates the second output signal based on one of the input and inverted input signals, and the first processor generates the first output signal based on the input signal, and wherein the error detection circuit receives and compares the first and second output signals from the first and second processors, and generates an error signal based on a result of the comparison.