Patent ID: 7432189
Filing Date: 2008-10-07
Classification: H01J,H01L

Abstract:
1. A method for reducing capacitances between semiconductor device wirings, comprising: forming a sacrificial layer over a dielectric layer; etching a plurality of features into the sacrificial layer and dielectric layer; filling the features with a filler material; removing the sacrificial layer, so that parts of the filler material remain exposed above a surface of the dielectric layer, wherein spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer, wherein the spaces have widths; shrinking the widths of the spaces between the parts of the filler material with a shrink sidewall deposition; etching gaps into the dielectric layer through the shrink sidewall deposition; and removing the filler material and shrink sidewall deposition.