Patent ID: 9018988
Filing Date: 2015-04-28
Classification: H03K,H03L

Abstract:
1. A method comprising: providing a first predetermined plurality of first dual modulus division stages, each first dual modulus division stage according to a first design supporting frequency division of a signal applied to it by proceeding through a sequence of states relating to the modulus division selected; providing a second predetermined plurality of second dual modulus division stages, each second dual modulus division stage according to a second design supporting frequency division of a signal applied to it by proceeding through a sequence of states relating to the modulus division selected and providing a separate occurrence indication for each occurrence of at least first and second predetermined state in the sequence of states; providing a range determination circuit for receiving a plurality of power series coefficients relating to a division factor and generating in dependence upon at least the plurality of coefficients a range signal for each second dual modulus division stage of the second predetermined plurality of second dual modulus division stages, the range signal at least one of freezing and unfreezing the second predetermined dual modulus division stage of the plurality of second dual modulus division stages; providing between adjacent pairs of the second dual modulus division stage of the plurality of second dual modulus division stages a first logic circuit for receiving at least a predetermined coefficient of the plurality of power series coefficients and a modulus output of the second dual modulus division stage of the adjacent pair dividing the output of the other second dual modulus division stage of the adjacent pair to generate a modulus input to the other second dual modulus division stage of the adjacent pair; providing a clock activation circuit for receiving a plurality of powers relating to a division factor and generating in dependence upon at least the plurality of powers a clock activation signal for each second dual modulus division stage of the second predetermined plurality of second dual modulus division stages except the last second dual modulus division stage of the second predetermined plurality of second dual modulus division stages; providing between the adjacent pairs of the second dual modulus division stage of the plurality of second dual modulus division stages a second logic circuit for receiving at least a predetermined clock activation signal, the indication of an occurrence of the first predetermined state from the second dual modulus division stage of the adjacent pair dividing the output of the other second dual modulus division stage of the adjacent pair, and the indication of an occurrence of the second predetermined state from the other second dual modulus division stage of the adjacent pair to generate a clock decision of a plurality of clock decisions; and providing a clock division circuit receiving the plurality of clock decisions to generate a control signal for at least an external circuit.