Patent ID: 6304501
Filing Date: 2001-10-16
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a memory cell array including a plurality of normal memory cells arranged in rows and columns and a plurality of spare memory cells for repairing a defect of said normal memory cells;a plurality of data buses for transmitting data input to said memory cell array;a plurality of normal data lines for transmitting said data to and from said normal memory cells;a plurality of spare data lines for transmitting said data to and from said spare memory cells;a redundant repair unit for accessing to at least one of said spare memory cells to perform a repair operation in response to a selection of said defect,said redundant repair unit connecting predetermined M (M: natural number) said spare data lines to M said data buses in place of M said normal data lines corresponding to said defect in said repair operation,said redundant repair unit further accessing said at least one of said spare memory cells in response to an externally input instruction.