Patent ID: 6049124
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A semiconductor package which includes:a package substrate of an organic material having a coefficient of thermal expansion of at least 15 ppm/.degree. C., the package substrate having a plurality of contact pads;a semiconductor chip having a coefficient of thermal expansion which is at least 2.7 ppm/.degree. C. less than the coefficient of thermal expansion of the package substrate, a backside with a beveled edge on at least two sides thereof, and a frontside with a beveled edge, the frontside having a plurality of solder connections thereon, the semiconductor chip being located on the package substrate with the solder connections contacting the contact pads and electrically coupling the semiconductor chip to the package substrate; andan epoxy located between the semiconductor chip and the package substrate around the solder connections, the epoxy bonding the semiconductor chip to the package substrate, the epoxy further being located about a periphery of the semiconductor chip and at least partially covering the beveled edge on the frontside, and the beveled edge on the backside, the epoxy having a coefficient of thermal expansion which is similar to a coefficient of thermal expansion of the solder connections, the semiconductor package being capable of being heated to about 120.degree. C. for about 30 minutes and then to about 150.degree. C. for about 3 hours, and then being cooled to room temperature without defects propagating from the edge of the backside and without the semiconductor chip delaminating from the package substrate.