Patent ID: 6930923
Filing Date: 2005-08-16
Classification: G11C

Abstract:
1. A non-volatile memory comprising: a plurality of memory blocks, each of the memory blocks comprising a plurality of word lines, each of the word lines being electrically connected to a plurality of memory cells; a first decoder for decoding a memory address to generate a plurality of first decoding signals; a second decoder for decoding the memory address to generate a plurality of second decoding signals; and a row driver for driving a predetermined word line to approach a predetermined voltage level, the row driver comprising: a plurality of word line drivers electrically connected to the first decoder and the second decoder, each of the word line drivers comprising: a plurality of driving units, each of the driving units being electrically connected to a word line; and a memory block selector electrically connected to the driving units for turning on the driving units according to the first decoding signals; and a driving voltage output circuit electrically connected to the driving units for determining a plurality of driving voltages according to the second decoding signals without using the first decoding signals, and outputting a predetermined driving voltage to drive the predetermined word line to approach the predetermined voltage level when a driving unit connected to the predetermined word line is turned on to electrically connect the predetermined word line and the driving voltage output circuit.