Patent ID: 8050124
Filing Date: 2011-11-01
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of memory cells; a plurality of bit lines each coupled to corresponding ones of the memory cells; a first sense amplifier having a first terminal, the first sense amplifier charging the first terminal at a first voltage during a first precharge period, the voltage on the first terminal being converted from the first voltage to a first converted voltage responsive to a voltage of a first selected one of the bit lines during a first conversion period, and amplifying the first converted voltage of the first terminal during a first amplification period; and a second sense amplifier having a second terminal, the second sense amplifier charging the second terminal at a second voltage during a second precharge period, the voltage on the second terminal being converted from the second voltage to a second converted voltage responsive to a voltage of a second selected one of the bit lines during a second conversion period, and amplifying the second converted voltage of the second terminal during a second amplification period; the first amplification period being overlapped at least with the second precharge period, wherein the first amplification period is further overlapped with the second amplification period, wherein the memory cells include variable resistance elements, respectively.