Patent ID: 6515519
Filing Date: 2003-02-04
Classification: G06F,H03L,Y02D

Abstract:
A semiconductor integrated circuit device comprising:an internal circuit, and a phase-locked loop circuit to receive a reference clock signal and to output a first output clock signal, a frequency of the first output clock signal being a multiple of a frequency of the reference clock signal, and a delay-locked loop circuit to receive said reference clock signal and to output a second output clock signal, a frequency of the second output clock signal being a fraction of a frequency of the reference clock signal; wherein said phase-locked loop circuit takes a longer clock-settling time to generate the first output clock signal after starting operation than said delay-locked loop circuit takes to generate said second output clock signal after starting operation, wherein in case that said phase-locked loop circuit supplies the first output clock signal to said internal circuit, said internal circuit is provided in one of a first state, a second state, and a third state such that: in said first state, said phase-locked loop circuit operates and said first output clock signal is supplied to said internal circuit, in said second state, said phase-locked loop circuit operates and said first output clock signal is not supplied to said internal circuit, and in said third state, said phase-locked loop circuit does not operate, and wherein in case that said delay-locked loop circuit supplies the second output clock signal to said internal circuit, said internal circuit is provided in one of a fourth state and a fifth state such that: in said fourth state, said delay-locked loop circuit operates and said second output clock signal is supplied to said internal circuit, in said fifth state, said delay-locked loop circuit does not operate.