Patent ID: 6492198
Filing Date: 2002-12-10
Classification: H01L

Abstract:
A method for fabricating semiconductor devices, said method comprising:(A) providing a semiconductor wafer, said wafer including a semiconductor substrate, a passivation formed thereon, and a plurality of chip pads exposed through openings in the passivation; (B) forming a first polymer layer on the passivation; (C) forming first under barrier metal (UBM) layers on the chip pads and the first polymer layer; (D) forming a copper redistribution pattern on the first UBM layers, said copper redistribution pattern being electrically connected to the chip pads; (E) forming a barrier metal on the copper redistribution pattern; (F) removing a portion of the first UBM layers, said portion of the first UBM layers being exposed by the copper redistribution pattern; (G) forming a second polymer layer on the first polymer layer and the copper redistribution pattern; and (H) forming a plurality of external connecting electrodes on a portion of the copper redistribution pattern, said portion of the copper redistribution pattern being exposed by the second polymer layer.