Patent ID: 6531779
Filing Date: 2003-03-11
Classification: H01L

Abstract:
A multi-layer interconnection structure in a semiconductor device comprising:a substrate; a first interlayer dielectric film overlying said substrate; a plurality of first interconnects embedded in said first interlayer dielectric film and having a first orientation in a plan view, each of said plurality of first interconnects having a top surface substantially flush with a top surface of said first interlayer dielectric film; a second interlayer dielectric film formed on said first interlayer dielectric film and on said plurality of first interconnects; a third interlayer dielectric film formed on said second interlayer dielectric film; and a plurality of second interconnects embedded in at least said third interlayer dielectric film and having a second orientation in said plan view that crosses said first orientation, a portion of said plurality of second interconnects having a uniform thickness and a remaining portion of said plurality of second interconnects having a nonuniform thickness.