Patent ID: 6882571
Filing Date: 2005-04-19
Classification: G11C,H01L

Abstract:
1. A method for operating a memory cell in an integrated circuit, the memory cell comprising an n-type well region in a semiconductor substrate, a first p-type region and a second p-type region formed in the n-type well region, an oxide layer formed over a channel region in the n-type well region between the first p-type region and the second p-type region, a polysilicon layer formed over the oxide layer, and a metal silicide layer formed over the doped polysilicon layer, the polysilicon layer comprising a fusible section formed over the channel region, a first contact pad and a second contact pad formed on either side of the fusible section, the method comprising the steps of: programming the memory cell by applying a programming voltage across the metal silicide layer to heat the doped polysilicon layer and cause carrier activation and dopant atom penetration through the oxide layer; and reading the memory cell.