Patent ID: 8044892
Filing Date: 2011-10-25
Classification: G09G

Abstract:
1. A circuit for controlling a matrix display formed of light-emitting diodes distributed in lines and columns, capable of successively selecting lines of the matrix display and, for each line of a set of selected lines, of selecting columns to turn on the light-emitting diodes of said line and of said selected columns, the voltage of each selected column settling at an operating voltage, said circuit being further capable, before selection of each line from said set of lines, of precharging at least said columns to be selected to a precharge voltage, and comprising a device for adjusting the precharge voltage comprising: a measurement circuit configured, on each selection of a line from said set of lines, to measure a maximum operating voltage among the operating voltages of said selected columns, the measurement circuit being configured to measure the maximum operating voltage independently of the presence of an open or short-circuited light-emitting diode in the selected line; a storage circuit configured, on each selection of a line from said set of lines, to store only a single measured value of the maximum operating voltage; an adjustment circuit configured, after each selection of a line from said set of lines, to adjust the precharge voltage of all the selected columns of the line based on the single stored value of the maximum operating voltage; and a current mirror comprising a reference branch and several duplication branches connected to a bias voltage, each duplication branch being connected to a column, the reference branch being connected to a source of a reference current, wherein each branch of the current mirror comprises a field-effect PMOS-type duplication transistor having its source connected to the bias voltage, the gates of the transistors of each branch being connected together, the drain and the gate of the transistor of the reference branch being connected to the reference current source, the drains of the transistors of the duplication branches being connected to the columns, and wherein the measurement circuit comprises, for each column, a field-effect PMOS-type protection transistor having its source connected to the bias voltage and having its gate connected to the drain of the duplication transistor and a field-effect NMOS-type measurement transistor having its drain connected to the protection transistor and having its gate connected to the column, the sources of the measurement transistors being connected to a measurement point.