Patent ID: 8719751
Filing Date: 2014-05-06
Classification: G06F

Abstract:
1. A method for analyzing simultaneous switching noise (SSN) in a circuit design tool, comprising: selecting a metric; executing simulations based on a circuit design for a plurality of victim-aggressor combinations associated with the metric; generating multiple waveforms for each one of the victim-aggressor combinations; collapsing the multiple waveforms to a plurality of single profile waveforms, one profile waveform being generated for each one of the victim-aggressor combinations, wherein the collapsing incorporates one of a minimum for each relevant one of the multiple waveforms at each time point or a maximum for each relevant one of the multiple waveforms at each time point, for the single profile waveform; identifying a worst case profile waveform from the plurality of single profile waveforms; simulating the circuit design with the worst case profile waveform; performing switching window SSN analysis of the circuit design with a common uncertainty removal utilizing one of the single profile waveforms, wherein the performing comprises: determining one of a maximum voltage noise or a minimum voltage noise induced on the victim, wherein at least one method operation is executed through a processor.