Patent ID: 6252419
Filing Date: 2001-06-26
Classification: H03L

Abstract:
An LVDS input interface for a programmable logic device, said programmable logic device having a plurality of signal conductors, said LVDS interface comprising:a pair of input terminals for accepting an input LVDS signal;an LVDS differential input driver for converting said input LVDS signal into a data signal comprising a serial stream of data bits;a number of shift registers, said number of shift registers having a shift register input for accepting said serial stream of data bits, each of said shift registers having a shift register output;a number of second registers, each register in said number of second registers having an input coupled to one of said shift register outputs and having a registered output coupled to one of said signal conductors; andan input phase-locked loop circuit for generating first and second input clock signals having first and second input clock rates, said first input clock rate being a multiple of said second input clock rate, said multiple being equal to said number; wherein:said first input clock signal controls shifting of said serial stream of data bits into said first shift registers; andsaid second input clock signal controls registration of said data bits from said inputs of said second registers to said outputs of said second registers; whereby:on each one cycle of said second clock signal:an existing set of said number of data bits previously applied by said shift register outputs to said inputs of said second registers are registered to said outputs of said second registers for conduction onto said signal conductors; andsaid first input clock signal goes through said number of cycles, clocking a new set of said number of data bits into said shift registers, whence they are conducted to said inputs of said second registers.