Patent ID: 7032101
Filing Date: 2006-04-18
Classification: G06F

Abstract:
1. In a processor, an apparatus for issuing instructions, wherein said processor has a memory, a decoding unit, and an execution unit, said apparatus comprising: a classification logic adapted for prioritizing instructions in relation to one another and sorting said instructions in a number of priority categories, wherein said instructions come from said memory and are being decoded in said decoding unit prior of reaching said classification logic, and wherein said instructions sorted in said number of priority categories by said classification logic comprise cloned instructions; a plurality of instruction queues, wherein said queues contain said instructions in decoded form, wherein said plurality of said queues matches said number of said priority categories, and wherein each of said queues adapted to receive only one of said priority categories of said instructions from said classification logic, whereby said queues having same priority categories as said instructions, and wherein said cloned instructions and corresponding unmodified instructions from which said cloned instructions have been derived are found in different ones of said queues; and an issue logic to dispatch said instructions for execution in said execution unit of said processor, wherein said issue logic is operably coupled to said plurality of instruction queues and is selecting from which of said queues to dispatch said instructions for execution, wherein said issue logic has been designed to be cognizant of said priority categories of said queues.