Patent ID: 6147340
Filing Date: 2000-11-14
Classification: H04N

Abstract:
A background suppression circuit suitable for use with a focal plane readout unit cell, comprising:an integrating capacitor arranged to receive a first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,a transistor having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse at least once per integration period, said transistor reducing the quantity of charge stored on said capacitor when said skimming pulse is received, anda pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to turn said transistor on,said reduction of stored charge enabling an increased quantity of said first current to be integrated during said integration period when said first current would otherwise exceed the charge capacity of said capacitor.