Patent ID: 6073252
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A data processing system having a central processing unit (CPU), the data processing system comprising:a first memory having N equal size blocks, where N is an integer, each of the N equal size blocks comprising a plurality of memory locations; anda first control unit coupled to the CPU and the first memory, the first control unit comprising:a first register having a plurality of fields, each of the plurality of fields having a patch protect bit, each of the plurality of fields having a first access control bit;a block decode unit coupled to the CPU, the block decode unit receiving address information from the CPU and determining a first block within the N equal size blocks corresponding to the address information, the first block having a corresponding field in the first register;an access control unit coupled to the first register, the access control unit receiving an identification of the first block from the block decode unit, and in response to receiving the identification of the first block the access control unit selecting the corresponding field in the first register, the access control unit selectively providing an access error indicator based on the status of the first access control bit; anda patch detect unit coupled to the first register and the block decode unit, the patch detect unit receiving the identification of the first block from the block decode unit, and in response to the identification of the first block the patch detect unit selecting the corresponding field in the first register;wherein the patch detect unit provides an exception signal to the central processing unit if the patch protect bit in the corresponding field is asserted.