Patent ID: 8728888
Filing Date: 2014-05-20
Classification: H01L

Abstract:
1. A manufacturing method of a semiconductor storage device, the device comprising: a plurality of memory cells; and a selection gate transistor provided on each end of a memory cell array including the memory cells, the method comprising: depositing a gate electrode material of the memory cells and of the selection gate transistor above a semiconductor substrate; depositing a hard mask material on the gate electrode material; forming first mandrels on the hard mask material in a region of the memory cell array, and forming a second mandrel on the hard mask material in a region of the selection gate transistor; forming first sidewall masks on side surfaces of the respective first mandrels in order to form the first sidewall masks into patterns of gate electrodes of the memory cells, and forming a second sidewall mask on a side surface of the second mandrel in order to form the second sidewall mask on a part of a gate electrode of the selection gate transistor; removing an upper portion of the second mandrel in order to expose an upper side surface of the second sidewall mask; embedding a sacrificial film in a gap between the first sidewall masks adjacent to each other, and forming a sacrificial spacer on the upper side surface of the second sidewall mask; forming a resist film covering the second mandrel, an outer edge of the resist film being located in a region between one of the first mandrels closest to the second mandrel and the sacrificial spacer; removing the first mandrels by using the resist film as a mask; and removing the sacrificial film and the sacrificial spacer.