Patent ID: 6281544
Filing Date: 2001-08-28
Classification: H01L

Abstract:
A semiconductor device on a semiconductor substrate that has a buried metallic layer, comprising:a polysilicon layer across the top of the semiconductor substrate;a drain region in the semiconductor substrate on one side of the polysilicon layer;a trench isolation structure in the semiconductor substrate for insulating from neighboring devices;a buried metallic layer in the semiconductor substrate such that the buried metallic layer is located within a portion of the trench isolation structure close to the upper surface of the substrate;a common source region within the semiconductor substrate, wherein the common source region is located on the other side of the first polysilicon layer just opposite the drain region such that the common source region at least includes a source region and a buried metallic layer alternately linked together; andan interconnect structure above the polysilicon layer and the trench isolation structure, wherein the interconnect structure is coupled electrically with the common source region through a contact window.