Patent ID: 9013390
Filing Date: 2015-04-21
Classification: G09G,G11C

Abstract:
1. A gate driver, comprising: a plurality of stages to output a plurality of gate signals, the plurality of stages coupled to each other, each stage including: a node driver to output a first voltage or a second voltage to a first node in response to a first input signal or a second input signal; a pull-up circuit to pull up an output terminal to a logic high level in response to a voltage of the first node; a node controller to output an on-voltage to a second node in response to a first clock signal received from a third node or a second clock signal received from a fourth node; a first node stabilizer to stabilize the first node to an off-voltage in response to a voltage of the second node; and a pull-down circuit to pull down the output terminal to a logic low level in response to the voltage of the second node or the second input signal, wherein each stage includes: a third node stabilizer to stabilize the third node to the off-voltage in response to the voltage of the first node; and a fourth node stabilizer to stabilize the fourth node to the off-voltage in response to a voltage of the third node or the voltage of the first node.