Patent ID: 8984255
Filing Date: 2015-03-17
Classification: G06F

Abstract:
1. A data processing device comprising: a first processing unit; a second processing unit; a page table of a memory shared by the first and second processing units; a first translation look-aside buffer (TLB) hierarchy configured to store selected address translations of the page table for use by the first processing unit; a second TLB hierarchy configured to store selected address translations of the page table for use by the second processing unit; the processing device configured to probe the second TLB hierarchy for an address translation requested by the first processing unit upon a condition that the requested address translation was not found in the first TLB hierarchy; and the processing device configured to probe the first TLB hierarchy for an address translation requested by the second processing unit upon a condition that the address translation requested by the second processing unit was not found in the second TLB hierarchy.