Patent ID: 7865668
Filing Date: 2011-01-04
Classification: G06F

Abstract:
1. A method for two-sided, dynamic cache injection control, comprising: receiving a request for an input/output (I/O) transaction at an input/output (I/O) adapter, the I/O adapter performing: generating the I/O transaction, the I/O transaction including an ID field and a requested address; looking up the requested address in a cache translation table stored in the I/O adapter, the cache translation table including mappings between addresses and corresponding address space identifiers (ASIDs) for a storage location; entering an ASID in the ID field of the I/O transaction when, in response to the look up, the requested address is present in the cache translation table, the entered ASID mapped to the requested address; sending the I/O transaction including the ASID in the ID field to a device comprising one of an input/output (I/O) hub and a system chipset, the device performing: looking up the ASID in a table stored on the device; and injecting the requested address and corresponding data from the I/O transaction into a cache hierarchy of a processor complex when, in response to the look up in the table, the ASID is present in the table, indicating that the address space corresponding to the ASID is actively running on a processor in the processor complex; wherein the ASIDs are dynamically determined and set in the I/O adapter and the device during execution of an application in the processor complex.