Patent ID: 6459119
Filing Date: 2002-10-01
Classification: G11C,H01L

Abstract:
A floating gate memory, comprising a plurality of blocks of floating gate transistor cells, each of said plurality of blocks including a plurality of subarrays of floating gate transistor cells, each of said plurality of subarrays of floating gate transistor cells including:a first plurality of floating gate transistor cells; a first drain diffusion bit line coupled to said first plurality of floating gate transistor cells; a first plurality of contacts coupled to said first drain diffusion deadline; a first nonglobal conductor coupled to said first plurality of contacts; a source diffusion bit line coupled to said first plurality of floating gate transistor cells; a second plurality of contacts coupled to said source diffusion bit line; a second nonglobal conductor coupled to said second plurality of contacts; a second plurality of floating gate transistor cells coupled to said source diffusion bit line; a second drain diffusion bit line coupled to said second plurality of floating gate transistor cells; a third plurality of contacts coupled to said second drain diffusion bit line; and a third nonglobal conductor coupled to said third plurality of contacts.