Patent ID: 7833849
Filing Date: 2010-11-16
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: providing a semiconductor substrate including at least one pFET device region and at least one nFET device region; forming a sacrificial layer on an upper surface of said semiconductor substrate in the at least one nFET device region, while leaving the semiconductor substrate in the at least one pFET device region exposed; forming a pFET gate dielectric on the exposed semiconductor substrate in the at least one pFET device region, but not in the at least one nFET device region; forming a Si-containing electrode having a first thickness in both device regions, wherein a first portion of said Si-containing electrode is located on an upper surface of the sacrificial layer in the at least one nFET device region and a second portion of said Si-containing electrode is located on an upper surface of the pFET gate dielectric in the at least one pFET device region; thinning the Si-containing electrode in both device regions to a second thickness, wherein said second thickness is about ½ less than the first thickness; removing the thinned first portion of the Si-containing electrode and the sacrificial layer from the at least one nFET device region exposing a portion of the semiconductor substrate, while maintaining the thinned second portion of the Si-containing electrode in the at least one pFET device region; forming an nFET dielectric stack on the exposed portion of the semiconductor substrate in the at least one nFET device region, but not in the at least one pFET device region; forming a first metal layer in both device regions, wherein a first portion of the first metal layer in the at least one nFET device region is located on an upper surface of the nFET dielectric stack, and a second portion of the first metal layer in the at least one pFET device region is located on an upper surface of the thinned second portion of the Si-containing electrode; forming a gate electrode atop the first metal layer in both device regions; and patterning to provide at least one nFET gate stack in the at least one nFET device region, and at least one pFET gate stack in the at least one pFET device region, said at least one nFET gate stack comprising, from bottom to top, a patterned portion of the nFET dielectric stack, a patterned first portion of the first metal layer, and a patterned first portion of the gate electrode, and said at least one pFET gate stack comprising, from bottom to top, a patterned portion of the pFET gate dielectric, a patterned second portion of the thinned Si-containing electrode, a patterned second portion of the first metal layer, and a patterned second portion of the gate electrode.