Patent ID: 8122408
Filing Date: 2012-02-21
Classification: G06F

Abstract:
1. A circuit verification method executed by a computer, comprising: (a) inputting design data relating to a design of a circuit to be verified and a library relating to operation of the circuit to be verified, the library including a logic information concerning the circuit to be verified and a timing information concerning the circuit to be verified; (b) setting a fixed logic value for a predetermined node in the circuit to be verified as an initial value; (c) tracing the design data from the node for which the fixed logic value is set to select a next-stage circuit block to which the fixed logic value is to be propagated; (d) propagating the fixed logic value from an input to an output in the circuit block selected at step (c); (e) determining whether or not executable fixed logic value propagation has been completed in all circuit blocks and repeating steps (c) and (d) until the propagation has been completed; and (f) if the executable fixed logic value propagation has been completed in all circuit blocks, then executing verification, as performed by a processor on the computer, of the entire circuit to be verified by using results of the fixed logical value propagation performed by a logic information propagating unit and a timing information propagating unit, wherein step (d) comprises: