Patent ID: 6538487
Filing Date: 2003-03-25
Classification: H03K

Abstract:
An electrical circuit for receiving an input signal having a voltage, and producing an output signal, the circuit comprising:(a) a plurality of inverters, each inverter including an enhancement-type FET and a depletion-type FET, the drain of the depletion-type FET being connected to a power source, the gate and source of the depletion-type FET being directly connected to each other and to the drain of the enhancement-type FET, the source of the enhancement-type FET being connected to ground, each inverter having an inverter input at the gate of the enhancement-type FET, an inverter output at the drain of the enhancement-type FET, and a logic threshold value, each inverter inverting and amplifying the voltage at its input to provide an inverted and amplified voltage at its output, the inverters being serially connected together in a cascade; (b) a feedback impedance, connecting the output of the last inverter in the cascade to the input of the first inverter in the cascade; and (c) switching means connected between the input and output of the first inverter in the cascade for supplying a compensation current to the input of the first inverter when a voltage difference between the input and output of the first inverter exceeds a predetermined value, the compensation current compensating a disparity between the logic threshold value of the first inverter and the voltage of the input signal due to an outflow of current.