Patent ID: 7213173
Filing Date: 2007-05-01
Classification: G06F

Abstract:
1. A computer system comprising: a central processing unit having at least one first signal pin; an integrated circuit device having at least one hardware strapping pin coupled to the first signal pin of the central processing unit; an external device coupled to the computer system and having a second signal pin; the hardware strapping pin of the integrated circuit device being a multiplexing pin that generates a hardware strapping signal to first signal pin of the central processing unit to perform a hardware strapping operation at the time when the system is being powered on and, after the hardware strapping is completed, is connectable to the second signal pin of the external device; and a hardware strapping fault prevention circuit coupled between the hardware strapping pin of the integrated circuit device and the second signal pin of the external device to isolate the second signal pin of the external device from the first signal pin of the central processing unit at the time when the computer system is being powered on.