Patent ID: 9043192
Filing Date: 2015-05-26
Classification: G06F

Abstract:
1. A modeling method comprising: accessing, by a computer from a memory, a design for a field effect transistor, said field effect transistor comprising: constructing, by said computer and based on said design, a resistive network to define all resistive elements within said gate structure, said resistive elements comprising: determining, by said computer and based on said resistive network, a total resistance associated with said gate structure, said total resistance being based on resistance contributions from said first resistive elements, said second resistive elements and said at least one third resistive element, and each resistance contribution of each resistive element being based on a resistance value of said resistive element, a square of a first fraction of current from said semiconductor fins entering said resistive element, a square of a second fraction of said current from said semiconductor fins exiting said resistive element and a production of said first fraction and said second fraction, said first fraction and said fraction depending upon what portion of said current from said semiconductor fins flows through each gate contact and upon a location of said resistive element within said resistive network relative to each gate contact.