Patent ID: 6160861
Filing Date: 2000-12-12
Classification: H03C,H03L

Abstract:
A phase-locked-loop, comprising:a phase/frequency detector having an input responsive to a reference clock, a second input, and an output;a first charge pump having an input coupled to the output of the phase/frequency detector, and an output;a second charge pump having an input coupled to the output of the phase/frequency detector, and an output;a feed forward compensation circuit having an input coupled to the output of the first charge pump, and an output;an integrator having an input coupled to the output of the second charge pump output, a first output and a second output;a main current controlled oscillator having an input coupled to the output of the feed forward compensation circuit and the first output of the integrator, and an output coupled to the second input of the phase/frequency detector;a reference current controlled oscillator having an input coupled to the second output of the integrator, and an output;a frequency to current circuit having an input coupled to the output of the reference current controlled oscillator, and an output;a current digital to analog converter having a reference input coupled to the output of the frequency to current circuit, an output coupled to the input of the main current controlled oscillator, and a digital input; anda shift register having an input responsive to the reference clock and an output coupled to the digital input of the current digital to analog converter.