Patent ID: 6133769
Filing Date: 2000-10-17
Classification: H03L

Abstract:
A phase locked loop, comprising:a phase locking circuit comprising a phase detector having inputs capable of receiving an input clock signal and a feedback signal, and outputs capable of outputting an up signal and a down signal in dependence upon a phase difference between the input clock signal and the feedback signal; anda phase lock detector, having inputs coupled to the phase detector, capable of detecting a difference between the up and down signals and in response generating a phase lock indicator signal in dependence upon whether the difference between the up and down signals is within a predetermined threshold difference, the phase lock detector comprising:an XOR gate having inputs coupled to receive the up and down signals, capable of generating a pulse signal representing a difference between the up and down signals; anda filter, coupled to the XOR gate, capable of filtering out the pulse signal if the pulse signal has a pulse width narrower than a predetermined threshold pulse width representing the predetermined threshold difference between the up and down signals.