Patent ID: 7056787
Filing Date: 2006-06-06
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device for simultaneously forming a wire structure and a capacitor, comprising: providing a substrate having a first conductive layer and a second conductive layer formed thereon; forming a first dielectric layer over the substrate; forming an etching stop layer on the first dielectric layer; patterning the etching stop layer to form a first opening located above the first conductive layer and a second opening located above the second conductive layer; forming a second dielectric layer over the substrate; removing a portion of the second dielectric layer and the first dielectric layer to form a first trench exposing the first conductive layer; forming a capacitor dielectric layer over the substrate; forming a patterned mask layer on the capacitor dielectric layer, wherein the patterned mask layer possesses a third opening located above the second conductive layer; removing a portion of the capacitor dielectric layer, a portion of the second dielectric layer and a portion of the first dielectric layer exposed by the third opening to form a fourth opening exposing the second conductive layer; removing the patterned mask layer; forming a third conductive layer over the substrate; and removing a portion of the third conductive layer, wherein the portion of the third conductive layer is not located in the first trench and the fourth opening.