Patent ID: 6187665
Filing Date: 2001-02-13
Classification: H01L

Abstract:
A process for passivating traps within a semiconductor structure of a semiconductor device, comprising the steps of:(a) providing a semiconductor structure comprising a semiconductor substrate including a surface having an oxide film formed thereon;(b) after step (a), annealing the structure in an environment including deuterium;(c) after step (b), forming a barrier film over at least the oxide film, the barrier film at least indirectly encapsulating the oxide film and being impervious to deuterium, the barrier film chosen from the group consisting of titanium, titanium nitride, tungsten, tungsten nitride, tantalum, and tantalum nitride,(d) after step (c), sintering at a sintering temperature greater than about 700.degree. C., and(e) after step (d), further annealing the structure at a further anneal temperature being less than the sintering temperature.