Patent ID: 6809985
Filing Date: 2004-10-26
Classification: G11C,H01L,H03K

Abstract:
A programmable logic array, comprising:a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein the non-volatile memory cells each include: a metal oxide semiconductor field effect transistor (MOSFET); a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and an electrical contact that couples the stacked capacitor to a gate of the MOSFET.