Patent ID: 8862966
Filing Date: 2014-10-14
Classification: G06F

Abstract:
1. A method for adjusting write timing in a memory device, the method comprising: determining a first result from an error detection function performed on data bits transferred from a processing device to the memory device; transmitting the data bits on a data bus to the memory device; determining a second result from the error detection function performed on corresponding data bits received by the memory device; comparing the first result to the second result to determine write timing window with a first timing boundary and a second timing boundary for a signal on the data bus and a write clock signal, wherein if the first and second results do not match each other, adjusting a phase difference between the signal on the data bus and the write clock signal based on the first and second timing boundaries of the write timing window, wherein the memory device recovers the signal on the data bus based on the adjusted phase difference.