Patent ID: 7831752
Filing Date: 2010-11-09
Classification: G06F,H04L,H04N,Y02D

Abstract:
1. A device comprising: a physical processor coupled with a physical memory configured for autonomously performing general computation and input/output operations; at least one communication means for two way communication with other external devices over a communications link; an interoperability engine executing interoperability instructions and running on the processor, the interoperability engine comprises logic for executing the instructions of an executable application package which encapsulates all that is needed to carry out the purpose of the interoperability application on the device, or the other external device, or a combination of the device and the other external device, to carry out an intended purpose; and wherein the interoperability instructions include a set of instructions used to represent the code portions of an executable application package which are executed by the engine and the interoperability instruction set including instructions to enhance the speed of operations, carry out interoperability methodologies, and expose the capabilities and content of the devices to each other including instructions for exposing and for enabling access to and use of unique capabilities and content of devices to other device even when the other devices have no prior knowledge of the unique capabilities and content.