Patent ID: 6025738
Filing Date: 2000-02-15
Classification: H03K

Abstract:
A buffer circuit for receiving an input signal at a buffer input terminal and providing an output signal at a buffer output terminal, said buffer circuit comprising:a first pulse generator arranged for receiving said input signal, said first pulse generator being responsive to a rising edge of said input signal for providing a first pulse signal;a second pulse generator arranged for receiving said input signal, said second pulse generator being responsive to a falling edge of said input signal for providing a second pulse signal;a first gain chain circuit connected to said first pulse generator;a first output switching device connected to said first gain chain circuit, said first output switching device being responsive to said first pulse signal for connecting said buffer output terminal to a first voltage level;a second gain chain circuit connected to said second pulse generator;a second output switching device connected to said second gain chain circuit, said second output switching device being responsive to said second pulse signal for connecting said buffer output terminal to a second voltage level; anda holding circuit connected between said buffer input terminal and said buffer output terminal.