Patent ID: 8938651
Filing Date: 2015-01-20
Classification: G01R,G06F

Abstract:
1. A system on a chip comprising: A. a communications link including a serial test data in lead, a serial test data out lead, and an override output lead; B. a port coupled to the communications link including the serial test data in lead, the serial test data out lead, and the override output lead, the port having a chip serial test data in output, a chip serial test data out input, a select output lead, and an override input; C. a first component separate from the port, the first component including an embedded TAP controller, the first component having a test data input coupled to the chip serial test data in output and a component serial test data output; and D. multiplexer circuitry having a first input coupled to the chip serial test data in output, a second input coupled to the component serial test data output, an output, and a control input coupled to the select output lead.