Patent ID: 8101970
Filing Date: 2012-01-24
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a P type semiconductor substrate; an N-well, positioned in the P type semiconductor substrate; a first P+ diffusion region and a second P+ diffusion region, positioned in the N-well; a Schottky diode, positioned in the N-well, for coupled to an input signal; a first N+ diffusion region and a second N+ diffusion region, positioned in the N-well, for coupled to a voltage source, respectively; a third P+ diffusion region and a fourth P+ diffusion region, positioned in the P type semiconductor substrate; a first insulation layer, positioned between the first N+ diffusion region and the third P+ diffusion region; a second insulation layer, positioned between the second N+ diffusion region and the fourth P+ diffusion region; a first parasitic bipolar junction transistor (BJT), having an emitter, a base, and a collector, wherein the emitter of the first parasitic BJT is formed by the first P+ diffusion region, the base of the first parasitic BJT is formed by the N-well connected to the first N+ diffusion region, and the collector of the first parasitic BJT is formed by the P type semiconductor substrate connected to the third P+ diffusion region; and a second parasitic BJT, having an emitter, a base, and a collector, wherein the emitter of the second parasitic BJT is formed by the second P+ diffusion region, the base of the second parasitic BJT is formed by the N-well connected to the second N+ diffusion region, and the collector of the second parasitic BJT is formed by the P type semiconductor substrate connected to the fourth P+ diffusion region; wherein when a voltage level of the input signal is higher than a voltage level of the voltage source, the Schottky diode conducts charges to make the first parasitic BJT and the second parasitic BJT not conducted.