Patent ID: 8946702
Filing Date: 2015-02-03
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first gate electrode layer over an insulating surface; a first insulating layer over the first gate electrode layer; oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers; a source electrode layer and a drain electrode layer over and in contact with the second oxide semiconductor layer; a second insulating layer over and in contact with the source electrode layer, the drain electrode layer, and an upper surface of the second oxide semiconductor layer between the source electrode layer and the drain electrode layer; and a second gate electrode layer overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers, wherein a region of the second oxide semiconductor layer in contact with the second insulating layer has a smaller thickness than a region of the second oxide semiconductor layer in contact with the source electrode layer and a region of the second oxide semiconductor layer in contact with the drain electrode layer.