Patent ID: 6469561
Filing Date: 2002-10-22
Classification: G01R

Abstract:
A rectifying integrator for an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, the rectifying integrator comprising:at least one integrator; a first line of integration connected to said at least one integrator for integrating a portion of the input signal that exceeds the voltage reference, said first line of integration comprising a first hold capacitor coupled in cascade to said at least one integrator; a second line of integration connected to said at least one integrator for integrating a portion of the input signal that remains below the voltage reference, said second line of integration comprising a second hold capacitor coupled in cascade to said at least one integrator; and an adder output stage for generating an output signal equal to a difference between voltages existing on said first and second hold capacitors.