Patent ID: 7768079
Filing Date: 2010-08-03
Classification: H01L,Y10S

Abstract:
1. A transistor, comprising: a high-k gate dielectric layer on a semiconductor substrate; a transition layer of silicon dioxide between the high-k gate dielectric layer and the substrate; a gate electrode layer on the high-k gate dielectric layer, wherein the high-k gate dielectric layer and the gate electrode layer are patterned to form a gate stack having a top, a first side, and a second side; and a high-k metal oxide dielectric layer on a top surface of the substrate and the first and second sides of the patterned gate stack, the high-k metal oxide dielectric layer on a source and a drain formed in the top surface of the substrate, the high-k metal oxide dielectric layer having a thickness in the range of about 10 to 30 angstroms.