Patent ID: 6035385
Filing Date: 2000-03-07
Classification: G06F,G06N

Abstract:
A circuit, comprising:a microprocessor;a fuzzy logic microprocessor;a program memory associated with the microprocessor;a memory unit associated with the fuzzy logic microprocessor for storing rules for use by the fuzzy logic microprocessor; anda loading circuit configured to enable loading of the memory unit associated with the fuzzy logic microprocessor with said rules upon start-up of the circuit;wherein said loading circuit comprises:a counter,an OR gate, inputs of said OR gate being connected to outputs of said counter;an AND gate, one input of said AND gate being connected to an output of said OR gate;a multiplexer, inputs of said multiplexer being connected to outputs of said counter and a control input of said multiplexer being connected to an output of said OR gate;a decoder associated with the program memory, an input to said decoder being connected to an output of said multiplexer.