Patent ID: 6507799
Filing Date: 2003-01-14
Classification: D06F

Abstract:
An apparatus for reducing microprocessor speed requirements in data acquisition applications comprising:a low pass filter having a variable cutoff frequency; an analog to digital converter in communication with the low pass filter; at least one microprocessor in communication with the analog to digital converter for receiving a first signal, the first signal representing a rate of rotation of a structure, the at least one microprocessor determining and providing a low pass filter cutoff frequency control signal to the low pass filter for controlling the variable cutoff frequency of the low pass filter, wherein said low pass filter cutoff frequency control signal is based on said rate of rotation of said structure; the low pass filter removing frequencies above the variable cutoff frequency from a second signal creating a filtered second signal; the filtered second signal being sampled by the analog to digital converter at a sampling rate creating a sampled second signal; and the sampled second signal being provided to one of the at least one microprocessor.