Patent ID: 6370612
Filing Date: 2002-04-09
Classification: G11C

Abstract:
A memory control system for optimizing a parameter value for a RAM cell array, said memory control system comprising:a memory controller storing an adaptive memory control program; and a central processing unit coupled to said RAM cell array and to said memory controller for executing said adaptive memory control program; said adaptive memory control program comprising instructions for: (a) initializing said parameter value to a first predetermined value, wherein said first predetermined value is a refresh period of said cell array; (b) generating a test bit pattern; (c) writing said test bit pattern into said cell array using said parameter value; (d) reading binary states of said cell array after a refresh cycle; (e) comparing said binary states of said cell array with said test pattern; and (f) adjusting said parameter value by: decreasing said parameter value when there is no match between said binary states of said cell array and said test pattern by setting an upper parameter limit equal to said parameter value, setting a lower parameter limit equal to a second predetermined value which is less than said parameter value and changing said parameter value to equal an average of said upper and lower parameter limits; increasing said parameter value when there is a match between said binary states of said cell array and said test pattern by setting said upper parameter limit equal to an upper value greater than said parameter value, setting said lower parameter equal to said parameter value and changing said parameter value to equal an average of said upper and lower parameter limits.