Patent ID: 8056043
Filing Date: 2011-11-08
Classification: G06F

Abstract:
1. An integrated circuit design system for modeling a capacitance (C 1 ) for a subject structure comprising a pair of long conductors surrounded by a dielectric material and supported by substrate, the surrounding dielectric material is a first dielectric with a first permittivity (∈ 1 ) and the substrate is a second dielectric with a second permittivity (∈ 2 ), the system comprising: a memory storage device; and a processor device connected to the memory storage device and adopted for performing a method to: obtain a known capacitance (C determine a reflection coefficient for the subject structure and said basis structure based on the first and second permittivities (∈ determine one of: a charge density function, or a uniform charge density approximation for said basis structure; determine one of: a mirror capacitance for said subject structure based on said charge density function, or an averaged mirror capacitance for said subject structure based on said uniform charge density approximation; and compute the capacitance of the subject structure based on the reflection coefficients and one of said mirror capacitance or the averaged mirror capacitance.