Patent ID: 7683478
Filing Date: 2010-03-23
Classification: H01L

Abstract:
1. A sealed microelectronic structure providing mechanical stress endurance, which comprises: a plurality of chips positioned on at least two wafers and the chips being electrically connected to a semiconductor structure, and the chips comprising outer edges; each chip including a continuous length of bonding material on a planar surface thereof defining a perimeter in spaced adjacency to the outer edge; at least one support column connected to each of the chips and positioned within the perimeter of each chip, and each support column extending outwardly such that when the at least two chips are positioned in overlapping relation to one another such that opposing support columns mate with each other or with an opposing planar surface area on the overlapping chip; a seal between the at least two chips resulting from the at least two chips being positioned in overlapping relation to one another such that the bonding material on each chip is in mating relation to each other whereby the seal is formed when the at least two chips are mated together resulting in a bonded chip structure; continuous bonding material being positioned along a perimeter adjacent to an outer edge of the wafer, and the at least two wafers being sealed together when the bonding material on each of the wafers is compressed on each other in mating relation and heated to form the seal; and the chips being electrically connected to their respective substrates and electrical connected to their respective wafers to form an electrical circuit on the chips and the wafers, and the support columns being electrically disconnected from the electrical circuit.