Patent ID: 9064729
Filing Date: 2015-06-23
Classification: H01L

Abstract:
1. A method for fabricating a junction-less transistor, comprising: providing a semiconductor substrate having a dielectric layer; forming a semiconductor layer on the semiconductor substrate, wherein the semiconductor layer includes a first heavily doped layer on the dielectric layer, a lightly doped layer on the first heavily doped layer and a second heavily doped layer on the lightly doped layer; etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and to expose side surfaces of a portion of the dielectric layer and to expose the semiconductor substrate at a bottom of the trenches; removing the portion of the dielectric layer between adjacent trenches to form a chamber connecting adjacent trenches under the portion of the semiconductor layer; forming a gate structure around the portion of the semiconductor layer defined by the chamber and the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure, wherein the first heavily doped layer, the lightly doped layer, and the second heavily doped layer of the portion of the semiconductor layer above the chamber provide a sandwich doping profile as a channel region of the junction-less transistor.