Patent ID: 6995436
Filing Date: 2006-02-07
Classification: G11C,H01L,Y10S

Abstract:
1. A nonvolatile semiconductor memory device comprising: a cell array in which memory cells are arranged in a row direction and a column direction, each of the memory cells comprising a first MOS transistor which is formed on a semiconductor substrate of a first conductivity type and has a current-carrying region of a second conductivity type and a gate electrode, a second MOS transistor which has a well of the second conductivity type serving as a control gate on the semiconductor substrate and has a current-carrying region of the first conductivity type and a gate electrode on the well, and a floating gate which is connected to the gate electrode of the first MOS transistor and the gate electrode of the second MOS transistor in a shared manner, each of the memory cells being capable of writing, reading, and erasing a carrier on the floating gate by applying a predetermined voltage to each terminal of the first MOS transistor and the second MOS transistor, wherein the cell array has a substrate contact region and a well contact region each arranged perpendicularly to a longitudinal direction of the floating gate, the substrate contact region and the well contact region being provided for applying potentials to the semiconductor substrate and the well of the second MOS transistor.