Patent ID: 6501674
Filing Date: 2002-12-31
Classification: G11C

Abstract:
A semiconductor memory comprising:a first sense amplifier which has a first terminal and a second terminal, compares an electric potential of said first terminal with an electric potential of said second terminal, and outputs an amplified voltage to each of said first and second terminals in accordance with a result of said comparison; a second sense amplifier which has a third terminal and a fourth terminal, compares an electric potential of said third terminal with an electric potential of said fourth terminal, and outputs an amplified voltage to each of said third and fourth terminals in accordance with a result of said comparison; a first bit line which is connected to said first terminal and belongs to a first area; a second bit line which is connected to said second terminal and belongs to a second area which does not overlap with said first area; a third bit line which is connected to said third terminal and belongs to said first area; a fourth bit line which is connected to said fourth terminal and belongs to said second area; a first memory cell which is connected to said first bit line and has a ferroelectric capacitor; a first dummy memory cell which is connected to said second bit line and has a ferroelectric capacitor polarized to a first direction; a second memory cell which is connected to said third bit line and has a ferroelectric capacitor; a second dummy memory cell which is connected to said fourth bit line and has a ferroelectric capacitor polarized to a second direction opposite to said first direction; and first short-circuit means which can short-circuit said second and fourth bit lines.