Patent ID: 6463548
Filing Date: 2002-10-08
Classification: G06F

Abstract:
An apparatus for ensuring functionality of a clocked circuit without limiting peak performance, comprising:a de-skewing device, coupled to a data signal that is generated by a driver device at a time that is indicated by an assertion of a first clock signal, said de-skewing device for buffering said data signal in response to a de-assertion of a mode select signal and for gating said data signal in response to an assertion of said mode select signal until a second clock signal is asserted; and a receiver device for receiving said data signal from said driver device via said de-skewing device, said receiver device latching said data signal in response to said assertion of said second clock signal, said receiver device being ensured of latching valid data from said data signal when said mode select signal is asserted, said mode select signal being asserted when a clock skew is detected between said first and second clock signals.