Patent ID: 7214579
Filing Date: 2007-05-08
Classification: G11C,H01L

Abstract:
1. Method for fabrication of a memory cell, for storing at least one bit, on a semiconductor substrate, comprising on said substrate a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate, said first and second floating gate stacks comprising a first gate oxide layer a floating gate, a control gate, an interpoly dielectric layer, a capping layer and side-wall spacers, said first gate oxide layer being located on said substrate, said floating gate being on top of said first gate oxide layer, said interpoly dielectric layer being on top of said floating gate, said control gate being on top of said interpoly dielectric layer, said capping layer being on top of said control gate, said memory cell further comprising source and drain contacts, said method of fabrication comprising: defining said first and second floating gate stacks in the same processing steps to have substantially equal heights; depositing a poly-Si layer over said first and second floating gate stacks, said poly-Si layer being deposited in between said first and second floating gate stacks in a thickness equal to or larger than the height of said first and second floating gate stacks; planarizing said poly-Si layer by chemical mechanical polishing to obtain a planarized poly-Si layer, using said capping layer of said first and second floating gate stacks as a polish stop layer; defining said intermediate access gate in said planarized poly-Si layer by a masking step with an access gate mask over said planarized poly-Si layer between said first and second floating gate stacks and an etching step for poly-Si.