Patent ID: 6630377
Filing Date: 2003-10-07
Classification: H01L

Abstract:
A method for making bipolar junction transistors integratable with CMOS FET structures comprising the steps of:providing a substrate having first and second device areas surrounded by trench isolation regions; forming first wells of a first type dopant for transistor collector contacts in said first device areas; forming second wells of a second type dopant in said second device areas adjacent to said first device areas for transistor base regions; forming third wells of said first type dopant under said first and second wells and under said trench isolation regions for transistor subcollectors; forming gate electrode masking elements over said transistor base regions to isolate transistor base contact regions from transistor emitter regions, while concurrently forming CMOS FET gate electrodes elsewhere on said substrate; forming first lightly doped drains of said first type dopant for said CMOS FETs and in said transistor emitter regions; forming second lightly doped drains of said second type dopant for said CMOS FETs and in said transistor base contact regions; forming sidewall spacers on said gate electrodes and on said gate electrode masking elements; forming source/drain areas of said first type dopant for said CMOS FETs, and concurrently forming emitters in said transistor emitter regions over and within said transistor base regions; forming source/drain areas of said second type dopant for said CMOS FETs, and concurrently forming base contacts in said base contact regions, said emitters separated from said base contact regions by said gate electrode masking elements.