Patent ID: 6781202
Filing Date: 2004-08-24
Classification: H01L

Abstract:
A semiconductor device in an insulated gate field-effect transistor in which a first pn junction is formed between a deep high-density impurity region doped with a second conduction type impurity and a semiconductor substrate including a first conduction type impurity region, said first conduction type impurity region having a predetermined principal surface, and in which a second pn junction is formed between a shallow high-density impurity region doped with the second conduction type impurity and said semiconductor substrate,wherein an intermediate region of the first conduction type impurity whose concentration is higher than that of said first conduction type impurity region of said semiconductor substrate is formed between said first conduction type impurity region of said semiconductor substrate and said deep second conduction type impurity region, and wherein the shallow high-density impurity region doped with the impurity of the second conduction type is projected to extend through at least a part of said intermediate region to the impurity region of the first conduction type in said semiconductor substrate.