Patent ID: 6219735
Filing Date: 2001-04-17
Classification: G06F

Abstract:
A module useable in an information processing system having a bus, and a plurality of modules connected to the bus, said module comprising:an acknowledge terminal adapted to output/receive an acknowledge report to/from an acknowledge bus line for transmitting exclusively the acknowledge report, the acknowledge bus line being coupled to the plurality of modules,a bus terminal adapted to output/receive an address and a data to/from the bus,wherein said module is adapted to acquire a bus mastership of the bus so that said module controls the bus for transfer of an address and data via the bus terminal to another module being a transfer destination, in synchronism with cycles of a clock which is common to all the modules,wherein said module is adapted to execute a transfer cycle for transferring either of the address or the data to the another module, and thereafter release the bus mastership,wherein said module is adapted to receive the acknowledge report for indicating receipt of at least one of the address and the data via the acknowledge terminal from the another module which receives the at least one of the address or the data from said module, said acknowledge report being in a predetermined number of cycles after the transfer cycle in which said module has released the bus mastership, and,wherein said module is adapted to confirm success of the transfer executed the predetermined number of cycles before the acknowledge report cycle, in accordance with the sent acknowledge report.