Patent ID: 8966309
Filing Date: 2015-02-24
Classification: G06F

Abstract:
1. Circuitry comprising: at least one element located within said circuitry and configured to hold an increasing count value; an encoder for receiving said increasing count value from a source of said increasing count value and configured to encode said increasing count value into encoded values, said encoded values each indicating an exponential amount to be applied to said count value held in said at least one element; and interconnect circuitry for receiving said encoded value and transmitting said encoded value to said at least one element; wherein said at least one element comprises a decoder for decoding said encoded values and for increasing said count value in dependence upon said exponential amount, wherein at least some of circuitry comprising synchronous circuitry clocked by a clock signal, said circuitry having different clock domains, such that at least a portion of said synchronous circuitry is clocked by a clock signal at a different frequency to another portion, said circuitry comprising a clock conversion circuitry arranged on said interconnect circuitry at a boundary between said differently clocked portions, said clock conversion circuitry comprising a data store configured to receive said encoded value from said interconnect circuitry operating in a first clock domain, to store said encoded value and to output said encoded value to said interconnect circuitry in a second clock domain.