Patent ID: 6810442
Filing Date: 2004-10-26
Classification: G06F

Abstract:
A memory mapping system for mapping at least one memory block from at least one logic device to at least one memory device in a reconfigurable hardware unit, the reconfigurable hardware unit including a conductive connector controller, at least one logic device for modeling at least a portion of a user design in hardware where a hardware model has at least one memory block and associated user memory interface, at least one memory device, a conductive connector subsystem coupling at least one logic device, at least one memory device, and the conductive connector controller, the memory mapping system comprising:a conductive connector driver coupled to the conductive connector subsystem; a memory block interface coupled to the conductive connector driver, the conductive connector subsystem, and the user memory interface to handle write/read memory access between at least one logic device and at least one memory device, wherein said at least one memory device storing the memory blocks associated with the hardware model; and an evaluation logic in each logic device coupled to the hardware model, the conductive connector driver, the memory block interface, and the conductive connector controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the conductive connector driver and the memory block interface.