Patent ID: 7400006
Filing Date: 2008-07-15
Classification: G11C,H01L

Abstract:
1. A conductive memory device comprising: a first layer of top conductive array lines, the top conductive array lines being arranged so that they do not come into direct contact with each other; a second layer of bottom conductive array lines, the bottom conductive array lines being arranged so that they do not come into direct contact with each other and so that they do not come into direct contact with any of the top conductive array lines; a plurality of top conductive electrodes, each top conductive electrode being in electrical communication with one of the top conductive array lines; and a plurality of bottom conductive electrodes, each bottom conductive electrode being in electrical communication with one of the bottom conductive array lines, wherein one top conductive array line from the first layer and one bottom conductive array line from the second layer define a unique pair of conductive array lines, across which a read current or a read voltage is indicative of stored data, a first write voltage applied across the unique pair is used to store a first data value, and a second write voltage applied across the unique pair is used to store a second data value, wherein at least one of the conductive electrodes functions as a barrier layer; and wherein at least one of the conductive electrodes includes a conductive oxide.