Patent ID: 7123176
Filing Date: 2006-10-17
Classification: G01R

Abstract:
1. A digital peak discriminator, comprising: (a) a peak register connected to receive a discrete pulse signal at its data input; (b) a subtractor connected to receive said discrete pulse signal at its adding input; (c) said peak register connected so that its output is an input to the subtracting input of said subtractor and is applied to the data inputs of maximum and minimum peak value latches; (d) the output of said subtractor is connected so that its output provides inputs to a comparator and to an exclusive OR gate; (e) said exclusive OR gate is connected so that its output is applied to the enable input of said peak register; (f) a noise threshold digital value is applied to one of the inputs of a data multiplexer and to the input of a negating and scaling unit, the ouput of which negating and scaling unit is applied to the other input of said data multiplexer; (g) said multiplexer is connected so that its output is an input to said comparator; (h) said comparator is connected so that its output is a data input to a flip-flop; (i) said flip-flop is connected so that its output is applied to the selecting input of said data multiplexer, to an input of said exclusive OR gate, and to the latching inputs of said maximum and minimum peak value latches, and provides a peak detect signal.