Patent ID: 6323051
Filing Date: 2001-11-27
Classification: G02F,H01L

Abstract:
A manufacturing method of a liquid crystal display having a matrix of thin film transistors, gate signal lines for controlling said thin film transistors and source signal lines for supplying data signals to said thin film transistors provided in such a manner so as to intersect with each other at right angles, pixel electrodes in communication with said source signal lines via said thin film transistors, and a liquid crystal material between said pixel electrodes and a counter electrode provided to oppose said pixel electrodes, the method comprising:effecting a first photo-etching after layering a first metal film and a second metal film sequentially on a substrate to form gate electrodes of said thin film transistors and gate signal lines and external outlet electrode portions of said gate signal lines;layering an insulating film, a high-resistance semiconductor film, and a low-resistance semiconductor film entirely on said substrate on which a pattern has been formed in said first photo-etching;effecting a second photo-etching on said low-resistance semiconductor film and high-resistance semiconductor film to form a semiconductor film patterns over said gate electrodes;layering a transparent conductive film, a third metal film, and a fourth metal film sequentially and entirely on said substrate on which said semiconductor film patterns from said second photo-etching have been formed;effecting third photo-etching on said fourth metal film, third metal film, transparent conductive film, and said low-resistance semiconductor film of said semiconductor film patterns so that to form said source signal lines, external outlet electrode portions of said source signal lines, source and drain electrodes of said transistors and pixel electrodes;forming a protection film entirely on said substrate on which said source and drain electrodes and pixel electrodes have been formed;effecting fourth photo-etching on said protection film and on said insulating film to let the external outlet electrode portions of said gate signal lines, the external outlet electrode portions of said source signal lines, and said pixel electrodes be exposed; andeffecting etching on said second metal film, third metal film and fourth metal film of the external outlet electrode portions of said gate signal lines, the external outlet electrode portions of said source signal lines, and said pixel electrodes, all of which are now exposed.