Patent ID: 8638577
Filing Date: 2014-01-28
Classification: H01L,H02M,H03K

Abstract:
1. A semiconductor device comprising: a first semiconductor chip including a high-side semiconductor switch; a second semiconductor chip including a low-side semiconductor switch; a third semiconductor chip including a high-side pre-driver configured to drive the high-side semiconductor switch and a low-side pre-driver configured to drive the low-side semiconductor switch; a first tab which is electrically connected to an input terminal and over which the first semiconductor chip is mounted; a second tab which is electrically connected to an output terminal and over which the second semiconductor chip is mounted; a third tab which is electrically connected to a logic ground terminal and over which the third semiconductor chip is mounted; and a power ground terminal which is different from the logic ground terminal and which is electrically independent of the logic ground terminal, wherein the first tab and a drain terminal of the first semiconductor chip are electrically connected, wherein the second tab and a source terminal of the first semiconductor chip are electrically connected, wherein the second tab and a drain terminal of the second semiconductor chip are electrically connected, wherein the power ground terminal and a source terminal of the second semiconductor chip are electrically connected, wherein a gate driving terminal of the high-side pre-driver of the third semiconductor chip is electrically connected to a gate of the high-side semiconductor switch of the first semiconductor chip via a first bonding wire, wherein a reference potential terminal of the high-side pre-driver of the third semiconductor chip is electrically connected to a source of the high-side semiconductor switch of the first semiconductor chip via a second bonding wire, wherein a gate driving terminal of the low-side pre-driver of the third semiconductor chip is electrically connected to a gate of the low-side semiconductor switch of the second semiconductor chip via a third bonding wire, and wherein a reference potential terminal of the low-side pre-driver of the third semiconductor chip is electrically connected to the third tab for the logic ground terminal via a fourth bonding wire to provide a reference potential to the low-side pre-driver of the third semiconductor chip independently of a ground potential of the power ground terminal to prevent a self-turn-on phenomenon, and wherein the first, second, and third semiconductor chips, a part of each of the first, second, and third tabs, and the first, second, and third bonding wires are packaged in one package.