Patent ID: 7345507
Filing Date: 2008-03-18
Classification: H03K

Abstract:
1. A programmable integrated circuit (IC), comprising: a plurality of columns of configurable circuits; wherein at least a first one of the columns includes a plurality of input/output (I/O) banks, each I/O bank including a plurality of I/O blocks, a plurality of the columns includes a plurality of rows of configurable logic blocks (CLBs), and a second one of the columns includes clock distribution circuitry coupled to the I/O blocks and configurable logic blocks; wherein a first plurality of the configurable circuits includes: a first plurality of adjacent ones of the I/O banks, a first plurality of adjacent ones of the rows of CLBs, and a first portion of the second column of clock distribution circuitry that is coupled to the first plurality of adjacent ones of the I/O banks and to the first plurality of adjacent ones of the rows of CLBs; wherein a second plurality of the configurable circuits includes: a second plurality of adjacent ones of the I/O banks, a second plurality of adjacent ones of the rows of CLBs, and a second portion of the second column of clock distribution circuitry that is coupled to the second plurality of adjacent ones of the I/O banks and to the second plurality of adjacent ones of the rows of CLBs; a selection code storage circuit coupled to the first and second pluralities of configurable circuits and storing a product selection code, wherein: a first value of the product selection code renders operational the first and second pluralities of configurable circuits, and a second value of the product selection code renders operational the first plurality of configurable circuits while rendering non-operational the second plurality of configurable circuits.