Patent ID: 6421284
Filing Date: 2002-07-16
Classification: G11C

Abstract:
A semiconductor device comprising:a first regular memory mat having a plurality of memory cells provided at the intersections of a plurality of first normal word lines, and a plurality of regular data lines; a redundant block including a first redundant line for making it possible to repair, when said first regular memory mat includes first and second defects ;and a repair decision circuit having a first row address storage circuit that can store first defect information in order to repair said first defect in a first replacement unit, a second row address storage circuit that can store second defect information in order to repair said second defect in a second replacement unit smaller than said first replacement unit, a first row address comparator that has a first input node connected to said first row address storage circuit, a second input node to which row address information is supplied, and a first output node for producing a first signal when said first defect information and said row address information coincide with each other, a second row address comparator that has a third input node connected to said second row address storage circuit, a fourth input node to which said row address information is supplied, and a second output node for producing a second signal when said second defect information and said row address information coincide with each other, and a selector connected to said first and second output nodes to produce a repair signal, wherein said selector produces said repair signal for relieving said first defect in said first replacement unit when said first signal is inputted, produces said repair signal for relieving said second defect in said second replacement unit when said second signal is inputted, and produces said repair signal for relieving said second defect in said second replacement unit when said first and second signals are inputted.