Patent ID: 6393066
Filing Date: 2002-05-21
Classification: H04J,H04L

Abstract:
A digital channelizer which divides an input bandwidth into at least some of N channels comprising:an analog to digital converter which encodes the input bandwidth into a serial digital data stream of data words; a demultiplexer, coupled to the analog to digital converter, which divides the serial digital data stream into parallel data streams of data words; a window presum having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; a cyclic shift, coupled to I output groups of data words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words which are shifted within the cyclic shift, each cyclic shift path comprising word shifting elements responsive to a group of data words with I equalling GCD(N,M) and each output group of cyclically shifted data words is repeatedly shifted through a number of cycles equal to N/GCD(N,M) with each cycle having a shift value defined by mM*modulo N, or âˆ’mM*modulo N wherein individual channels of the at least some of the N channels are decimated by a decimation factor of M and m is an index variable ranging from zero upward to positive integers; and a discrete Fourier transform apparatus having N inputs, coupled to the N outputs of the window presum, which performs a discrete Fourier transform on the N inputs to produce an output of at least some of the N channels; and wherein m is an index variable ranging from zero upward to positive integers, GCD(N,M) is a greatest common divisor and I, N and M are positive integers.