Patent ID: 6647536
Filing Date: 2003-11-11
Classification: G06F

Abstract:
An Integrated Circuit (IC) layout design method, said IC layout design method having a set of layout design programs and an initial layout database describing said an IC layout, said IC layout design method comprising the steps of:(a) organizing said set of layout design programs as executable program states, each of said program states generating program output data and program logic outputs and receiving program logic inputs and program input data, said program input data selected from said layout database; (b) coupling said executable program states with a program scheduler, said program scheduler receiving from each of said executable program states, said program logic outputs and program output data and generating and sending to each of said executable program states said program logic inputs and program input data, said program scheduler further receiving designer control signals and receiving data from said layout database and updating said layout database data in response to said designer control signals and said program logic outputs and said program output data; (c) starting execution of selected program states from said set of program states, concurrently, in response to said designer control signals and said program logic inputs; (d) completing said selected program states and starting additional program states unless stopped by said program scheduler in response to said program logic outputs; (e) determining if all program states in said set of program states have completed successfully, stopping said layout design if all programs have completed successfully and sending designer action data to a designer if all programs have not completed successfully; (f) correcting said layout database by said designer if all programs have not completed successfully; and (g) repeating said method steps (c)-(f) in response to one or more of said designer control signals wherein said designer control signals comprise a start Program Scheduler, set to execute in an Audit Mode in which all program states must complete error free, and a stop Program Scheduler.