Patent ID: 6249462
Filing Date: 2001-06-19
Classification: G11C

Abstract:
A data output circuit to output a data signal having two states of a high level and a low level, comprising:a buffer circuit setting a potential level of a data output node according to the potential levels of first and second nodes, said buffer circuit includinga pull up transistor electrically coupled between a first potential corresponding to said high level and said data output node, and which is an N type field effect transistor having a gate coupled to said first node,a pull down transistor electrically coupled between a second potential corresponding to said low level and said data output node, and which is an N type field effect transistor having a gate coupled to said second node;a high level data output control circuit providing to said first node a potential that can turn said pull up transistor on in a high level data output operation providing said high level to said data output node;a low level data output control circuit providing to said second node a potential that can turn said pull down transistor on in a low level data output operation providing said low level to said data output node; anda substrate potential switch circuit supplying a substrate potential to said pull up transistor, said substrate potential switch circuit supplying a first substrate potential in an operation other than said high level data output operation, and supplying a second substrate potential higher than said first substrate potential in said high level data output operation.