Patent ID: 7256614
Filing Date: 2007-08-14
Classification: H03K,H04L,Y10T

Abstract:
1. An integrated circuit, comprising: at most k number of functional blocks; a scalable switching network (SN) comprising: a first plurality of N sets of switches, wherein N is greater than one; a first port having M number of pins, wherein M is at most equal to (k×N); wherein the SN further comprises a first set of I number of conductors where I ranges between M and (k×N) and the I number of conductors are divided into N sets of Ij number of conductors for j={1 to N} where Ij is approximately equal to (I/N), wherein between (M−N+1) to M number of pins of the first port selectively couple to each of the N sets of the Ij number of conductors of the first set of I number of conductors through a respective set of switches of the first plurality of N sets of switches without requiring traversal of another conductor where the respective set of switches has X number of switches ranging between (M−N+1) and M; the SN further comprises a second plurality of N sets of switches and a second plurality of N number of ports, wherein each of the second plurality of N number of ports has at most k number of pins and k is at least equal to the largest Ij for j={1 to N}, wherein the Ij number of conductors of each of the N sets of the Ij number of conductors is configured to selectively couple to the at most k number of pins of a respective port of the second plurality of N number of ports through a respective set of switches of the second plurality of N sets of switches without requiring traversal of another conductor, wherein the respective set of switches has (Ij× at most k) number of switches; and wherein each of the at most k number of pins in each port of the second plurality of N number of ports is physically connected to a respective pin in the N number of pins of the at most k number of functional blocks.