Patent ID: 6988190
Filing Date: 2006-01-17
Classification: G06F

Abstract:
1. A method of executing instructions using an address trace cache in a branch prediction environment comprising the steps of: if a first routine of a plurality of routines composed of a first group of instructions is to be executed, storing an address corresponding to each instruction in the address trace cache according to an order of executed instructions; if a second routine of the plurality of routines composed of a second group of instructions is to be repeatedly executed, storing a routine start address in a first storing area of the address trace cache, storing a routine end address in a second storing area of the address trace cache, storing a current iteration count of the second routine representing a current number of executed iterations of the second routine in a third storing area of the address trace cache, and storing a total loop iteration count in a fourth storing area of the address trace cache; providing the address trace cache with a current loop iteration counter for counting the current iteration count when the second routine of repeated instructions is executed and the total loop iteration count for representing the total number of iterations of the second routine of repeated instructions; and incrementing the current iteration count for each executed iteration of the second routine, wherein when the current iteration count and the total loop iteration count representing the total number of iterations are identical, the second routine is finished, and a next routine composed of a next group of instructions to be repeatedly executed is initiated by addressing a start address in a next first storage area of the next routine, and wherein the address trace cache provides a first storing area, second storing area, third storing area, and fourth storing area for each routine composed of a group of instructions to be repeatedly executed.