Patent ID: 9098406
Filing Date: 2015-08-04
Classification: G06F

Abstract:
1. A method to manage addressable memory in a heterogeneous multicore chip on a computer, comprising: identifying a first data segment stored in a first addressable memory and a second data segment stored in a second addressable memory, wherein the first data segment is accessible from the first addressable memory via a first memory address, and wherein the second data segment is accessible from the second addressable memory via a second memory address; determining, based on distance locality, whether swapping the first data segment stored in the first addressable memory with the second data segment stored in the second addressable memory is suitable by: in response to determination that the swapping is suitable based on the benefit measure being determined to exceed the cost measure by the threshold amount, swapping the first data segment and the second data segment such that the first data segment is moved from the first addressable memory to the second addressable memory and such that the second data segment is moved from the second addressable memory to the first addressable memory, wherein the first data segment is accessible from the second addressable memory via the first memory address, and wherein the second data segment is accessible from the first addressable memory via the second memory address.