Patent ID: 8941162
Filing Date: 2015-01-27
Classification: H01L

Abstract:
1. A semiconductor device comprising: an active semiconductor region; a groove selectively formed to cross the active semiconductor region so that first and second portions sandwiching the groove are defined in the active semiconductor region; source and drain regions formed in the first and second portions, respectively; a word line partially filling the groove with an intervention of a gate insulating film between the word line and the groove; a buried insulating film filling the groove to cover the word line; a bit line elongated in a direction crossing the word line, the bit line including a portion that is formed over and electrically connected with one of the source and drain regions; a contact plug formed over and electrically connected with the other of the source and drain regions so that a gap is formed over the buried insulating film and between the contact plug and the portion of the bit line; a capacitor formed over and electrically connected with the contact plug; and first, second and third insulating films in the gap, the first insulating film being sandwiched between the second and third insulating films, the second insulating film being in contact with the portion of the bit line and penetrating through the first insulating film to contact the third insulating film, and the third insulating film contacting the contact plug and the first insulating film; wherein each of the buried insulating film and the second and third insulating films comprises a silicon nitride film, and wherein the first insulating film is different in material from the silicon nitride film.