Patent ID: 7636006
Filing Date: 2009-12-22
Classification: H01L,H03K

Abstract:
1. A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the supply and reference voltages, wherein the high voltage is higher than the supply voltage, the interface circuit comprising: a high-voltage N-channel MOS transistor having its gate intended to receive a control signal referenced to the reference voltage and having its source intended to be connected to the reference voltage, and a high-voltage PNP transistor having its base connected to the drain of the MOS transistor, having its emitter intended to receive the supply voltage, and having its collector intended to provide a voltage to the terminal, wherein when the terminal is at the high voltage, the high voltage PNP transistor protects the supply voltage from receiving the high voltage and the high voltage N-channel MOS transistor protects the control circuit from receiving the high voltage; wherein the high-voltage N-channel MOS transistor and the high-voltage PNP transistor are formed in a semiconductor substrate; wherein the high-voltage PNP transistor surrounds the high-voltage N-channel MOS transistor.