Patent ID: 6088776
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A memory circuit for processing a data signal, supplied from a counterpart station, into a processed signal supplied to a signal processing circuit, said memory circuit comprising:a first memory connected to said counterpart station which receives a write clock signal together with said data signal and which stores said data signal in response to said write clock signal;a first clock producing circuit, connected to said first memory, which produces a first clock signal that is synchronous with said write clock signal and has a transmission rate obtained by averaging that of said write clock signal, said first clock signal being supplied to said first memory to cause said first memory to output said data signal in response thereto; anda local processing circuit connected to said signal processing circuit, said first memory, and said first clock producing circuit, said local processing circuit receives said data signal from said first memory in response to said first clock signal and outputs said data signal at a second clock signal as said processed signal.