Patent ID: 6389095
Filing Date: 2002-05-14
Classification: H03K

Abstract:
An in-phase divide-by-three circuit, characterized in that it comprises:(a) a first data flip-flop (DFF) connected to receive, at a clock input, an in-phase input clock signal having an input frequency; (b) a second DFF connected to receive: (1) at a clock input, the in-phase input clock signal; and (2) at a data input, a slave output from the first DFF; (c) a NOR gate, connected: (1) to receive: (A) the slave output signal from the first DFF; and (B) a slave output signal from the second DFF; and (2) to apply a NOR output signal to a data input of the first DFF; and (d) an in-phase OR gate, connected to receive: (1) the slave output signal from the first DFF; and (2) a master output signal from the second DFF; whereby an output of the in-phase OR gate produces an output in-phase clock signal having an output frequency equal to one third of the input frequency.