Patent ID: 6016544
Filing Date: 2000-01-18
Classification: G06F

Abstract:
An apparatus for loading a stack segment register within a pipeline processor, the apparatus comprising:a translator, within a translate stage of the pipeline processor, for translating a first macro instruction into a first sequence of micro instructions, and a second macro instruction into a second sequence of micro instructions;a register file, connected to said translator, said register file further comprising a stack segment register, said stack segment register for storing a descriptor which indicates whether stack operations are of a first bit size or of a second bit size;stack address size logic, connected to said register file, and to said translator, for providing an indicator to said translator that current stack operations are of said first bit size or of said second bit size;stack size tracking logic, connected to said translator, and associated with said second sequence of micro instructions, following said first sequence of micro instructions in the pipeline processor, for tracking, in processing stages after said translate stage, whether stack operations were of said first bit size or of said second bit size at the time said second sequence of micro instructions were translated; anddetermination logic, connected to said stack size tracking logic, and to said stack address size logic, for determining whether said current stack operations and said tracked stack operations are both of said first bit size or of said second bit size, and if not of the same size, for providing a signal to the processor to ignore said second sequence of micro instructions, and to retranslate said second macro instruction using said indicator from said stack address size logic.