Patent ID: 6445642
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A double data rate synchronous DRAM (DDR-SDRM) comprising a memory cell array including a plurality of memory cells, an address signal processing section for receiving and processing an address signal for specifying an address of one of said memory cells, said address signal processing section operating in synchrony with a system clock signal, a data write section for receiving write data and writing the write data into said one of said memory cells in a write cycle, and a data read section for responding to said system clock signal to read data from said one of said memory cells in a read cycle to deliver read data, said data write section operating based on a data strobe signal transferred in synchrony with said write data to receive said write data from outside said DDR-SDRM and deliver said write data through I/O lines to said one of said memory cells.