Patent ID: 9163995
Filing Date: 2015-10-20
Classification: G01J,Y10T

Abstract:
1. Method of fabricating and assembling a plurality of tiles having pixel elements to form a large array, wherein the tiles have convex polygonal shapes, wherein each pixel element comprises an electrically active area and optically active area, and unit cell circuitry is associated with each pixel element, wherein the pixel elements are disposed on top of the unit cell circuitry, and wherein and some of the pixel elements are edge pixel elements disposed at the edges of tiles susceptible to damage, comprising: providing physical alignment features on side edges of the tiles, wherein the physical alignment features on a side edge of a given tile mate with the physical alignment features on a side edge of an adjacent tile in the array; and further comprising at least one of: making the unit cell circuitry smaller than the pixel element with which it is associated; locating the unit cell circuitry for edge pixel elements away from the edges of the tile; implementing an array of unit cell circuitry with a smaller pitch than the array of pixel elements; providing routing for a given unit cell circuitry which is located away from its associated the pixel element; making an electrically active area smaller than the pixel element; and locating the electrically active areas of edge pixel elements away from the edges of the tile; and further comprising: a pixel element disposed at an edge of the tile susceptible to damage is designed to have an edge damage tolerant (EDT) area along at least one edge of the pixel, and the EDT area occupies a fraction of the pixel width by an amount is selected from the group consisting of at least 1%, at least 2%, at least 5%, at least 10%, at least 25%, and the electrically active portion does not extend into the EDT area; and for pixel elements where the electrically active area is made smaller, maintaining the optically active area as large as possible, including up to the edges of the tile.