Patent ID: 6303454
Filing Date: 2001-10-16
Classification: G11C,H01L

Abstract:
The method of fabricating a snap-back flash EEPROM cell that is operated using a snap-back erase process comprising:(1) forming a gate structure on a substrate, said gate structure comprising a gate dielectric layer, a floating gate, intergate dielectric layer and a control gate; said gate structure having sidewalls;(2) forming a drain in said substrate adjacent to said gate structure by a masking and ion implant process; said drain is comprised of a first conductivity type dopant;(3) forming only a source side doped region adjacent to and under a portion of said gate structure a first distance by a masking and ion implant process; said side source doped region extending from the surface of said substrate to a depth below said surface of said substrate; said source side doped region is comprised of a first conductivity type dopant;(4) forming spacers on said sidewalls of said gate structure after forming said drain and said source side doped region;(5) forming a source overlapping portion of said side source doped region and adjacent to said spacers; said source formed by an masking and ion implant process; said side source doped region having a lower dopant concentration than said source; said source is comprised of a first conductivity type dopant;wherein no other doped regions are formed adjacent to said gate structure or said spacers;thereby forming a snap-back memory cell wherein said side source doped region is used to apply a high voltage to operate said snap-back flash EEPROM cell in a snap-back erase mode;wherein said snap-back erase mode comprises:a) applying a positive sine waveform voltage (Vs) to said source during an entire erase cycle;b) grounding said substrate during said entire erase cycle;c) grounding said drain during said entire erase cycle;d) simultaneously applying a negative voltage to said control gate device during said entire erase cycle; andwhereby said positive sine waveform voltage applied to said source reduces an electric field in said gate dielectric layer which reduces electron and hole trapping.