Patent ID: 8799715
Filing Date: 2014-08-05
Classification: G06F

Abstract:
1. An integrated circuit comprising: a central processing unit (CPU) complex comprising one or more processors; one or more component blocks coupled to the CPU complex, wherein the one or more component blocks are configured to implement one or more operational features of the integrated circuit other than a CPU feature; a plurality of local debug control units, wherein one of the plurality of local debug control units is included in the CPU complex and each other one of the plurality of local debug control units is included in a respective one of the one or more component blocks, wherein the plurality of local debug control units are configured to monitor for debug events in the corresponding CPU complex or component block; and a debug control unit coupled to the plurality of local debug control units in a ring, and wherein the plurality of local debug units are configured to transmit indications of detected debug events on the ring, and wherein a first local debug unit of the plurality of local debug units is coupled to receive an indication of a detected debug event from the ring and to trigger monitoring for another debug event responsive to receiving the indication of the detected debug event, and wherein the debug control unit is configured to monitor for detected debug events from the plurality of local debug control units, and wherein the debug control unit is configured to halt the CPU complex and the one or more component blocks responsive to detecting a specified one or more of the detected debug events.