Patent ID: 7310705
Filing Date: 2007-12-18
Classification: G06F

Abstract:
1. A multithread processor designed to carry out a plurality of threads, each having at least one instruction, in parallel through the use of one or more arithmetic units, comprising: a multithread control unit selectively switching a first thread among said plurality of threads to be executed by said arithmetic unit and for setting a thread identifier indicative of the first thread to which said instruction pertains; an instruction control unit setting an instruction identifier which specifies an instruction in the first thread; a plurality of caches arranged hierarchically and each made to retain data temporarily; and a cache control unit for managing writing/readout of said data in/from said plurality of caches, in a case in which a cache miss among the plurality of caches, in which the instruction to be executed by said arithmetic units does not exist in a first cache of said plurality of caches, occurs on a request related to said instruction in the first cache which is at the lowest place in the hierarchy, with respect to said request related to said cache miss, said cache control unit notifying said instruction identifier and said thread identifier, related to said instruction, to said multithread control unit, when a request related to said cache miss is issued from a second cache of said plurality of caches, which is at a higher place in the hierarchy than the first cache and in which said cache miss occurs, to the first cache, said cache control unit secures a storage area for storing data response from the first cache with respect to said request and sets a cache request identifier for specifying said storage area and, in a case in which said instruction is in the first thread and is a demand request which leads to the interchange of said data between a register for storing said data so that said arithmetic unit carries out arithmetic operations and an external storage unit in the exterior of said multithread processor, notifies said thread identifier, said cache request identifier and said instruction identifier, related to the instruction, to said multithread control unit, said multithread control unit making the switching of the first thread, which is in execution in said arithmetic unit, to a second thread based on said instruction identifier and said thread identifier notified from said cache control unit, and said cache control unit monitors an elapsed time after a prefetch request is issued to said external storage unit and, in a case in which said data to be accessed according to said instruction agrees with said data acquired from said external storage unit according to a preceding prefetch request and the elapsed time exceeds a predetermined period of time, said cache control unit does not notify said thread identifier, said cache request identifier and said instruction identifier, related to said instruction, to said multithread control unit.