Patent ID: 7882307
Filing Date: 2011-02-01
Classification: G06F,H04L

Abstract:
1. An apparatus, comprising: a plurality of processor cores, each comprising a computation unit and a memory; and an interconnection network to transmit data among the processor cores; with one or more of the memories each configured as a cache for storing cached data from memory external to the processor cores, and one or more of the processor cores configured to transmit a message over the interconnection network to access a cache of another processor core; and with at least some of the processor cores configured to operate in in the first mode, a set of multiple memory pages are cached in caches of multiple processor cores, with each memory page stored in a cache of at most one home processor core of the multiple processor cores, and a first home processor core that stores a first memory page is configured to access a cache line of the first memory page from its own cache, and processor cores other than the first home processor core are configured to access a cache line of the first memory page by transmitting a message over the interconnection network to access the cache of the first home processor core.