Patent ID: 6611938
Filing Date: 2003-08-26
Classification: G06F,G11C

Abstract:
A flash memory comprising:a memory sector with a plurality of flash memory cells; a command interface, which receives a write data input instruction from an external device, generates a write data input instruction signal, and receives a write instruction from the external device and generates a write instruction signal; a first signal buffer, which receives a write enable signal input from the external device; a control signal generation circuit, which is activated by the write instruction signal, and generates a control signal; a data input buffer, which is activated by the write data input instruction signal to receive a write data input from the external device in synchronization with the write enable signal; an error correction circuit, which is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal; an address buffer, which receives an address data input from the external device; an address signal generation circuit, which is activated by the write data input instruction signal to generate an address signal in a predetermined order based on the address data in synchronization with the write enable signal, and is activated by the write instruction signal to generate an address signal in a predetermined order in synchronization with the control signal; a plurality of data memory circuits, each of which is provided corresponding to each of said plurality of flash memory cells, and receives an allocated address signal, takes and temporarily memorizes the write data and the check data; and means to be activated by the write instruction signal, and to write the write data and the check data, which are temporarily memorized in said plurality of data memory circuits in said memory sector.