Patent ID: 9026762
Filing Date: 2015-05-05
Classification: G06F,G11C

Abstract:
1. A semiconductor system comprising: three or more memory chips; and a controller comprising first and second memory buffers configured to communicate with the three or more memory chips, wherein the first and second memory buffers alternately transmit data to sequentially communicate with the three or more memory chips, wherein if a programming fail occurs in one of the three or more memory chips, data which is not successfully programmed into one of the three or more memory chips due to the programming fail is transmitted to the controller, wherein, when the first and second memory buffers transmit data to one of the three or more memory chips, the first and second memory buffers are updated with new data, wherein each of the memory chips comprises a first latch configured to store data transmitted from one of the first and second memory buffers, and a second latch configured to receive and store data stored in the first latch and program the stored data therein into a memory cell, wherein when the programming fail occurs, the first latch does not receive new data from one of the first and second memory buffers, wherein, when the programming fail occurs, the second latch transmits the stored data therein to the first latch.