Patent ID: 6118729
Filing Date: 2000-09-12
Classification: G11C

Abstract:
A semiconductor integrated circuit device comprising:a memory cell array including at least first and second memory cell groups;at least first and second data lines;a data transfer circuit capable of at least respectively connecting memory cells included in said first and second memory cell groups to said first and second data line; anda data output circuit including at least first and second output transfer circuits and a read data line control circuit, said first output transfer circuit being adapted to transfer first output data sent to one of said first and second data lines at a first timing, said second output transfer circuit being adapted to transfer second output data lines at a second timing different from said first timing, said read data line control circuit capable of selectively connecting said first data line to one of said first and second output transfer circuits, and selectively connecting said second data line to one of said first and second output transfer circuits in accordance with an input address and a signal to designate one of an SDR scheme and a DDR scheme.