Patent ID: 6707705
Filing Date: 2004-03-16
Classification: G11C

Abstract:
An integrated memory chip with a dynamic memory, comprising:a memory cell array having bit lines and word lines; a control circuit connected to and controlling a memory access to said memory cell array; said control circuit having a clock input connected to receive a clock signal; wherein a plurality of individual actions, to be performed by said control circuit for a memory access, from an activation of one of said word lines to a precharging of said word lines, are controlled in synchronicity with the clock signal; said control circuit having a programmable unit for setting a defined number of clock cycles between at least two of the individual actions; and said memory cell array being one of a plurality of separate memory cell arrays and said programmable unit seting the defined number of clock cycles such that a cycle time for a word line access encompasses a number of clock periods of the clock signal corresponding to a number of said memory cell arrays.