Patent ID: 8335961
Filing Date: 2012-12-18
Classification: G06F,H03M

Abstract:
1. A method for providing error detection and correction after a failure of a memory component in a memory system, comprising: accessing a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X<R inner checkbits and R−X data bits, and C−2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits, which comprise the row-checkbits and the inner checkbits, are generated from the data bits to provide block-level detection and correction for a failed memory component; attempting to correct a column of the block from the failed memory component by using the checkbits and the data bits to produce a corrected column; regenerating row-parity bits and the inner checkbits for the block of data, wherein the block includes the corrected column; comparing the regenerated row-parity bits and inner checkbits with existing row-parity bits and inner checkbits; and if comparison indicates that there remains a double-bit error wherein both erroneous bits are in the same row and one is in the column associated with the failed component, flipping the erroneous bits to correct the double-bit error.