Patent ID: 6515986
Filing Date: 2003-02-04
Classification: H04Q

Abstract:
A method of switching frame-oriented serial data, which comprises:reading at least a first portion of the serial data into an input RAM via an interface; reading the data from the input RAM into a switching unit; controlling a read/write operation of the input RAM with a central controller; generating switching information with the central controller according to a switching algorithm, whereby the switching information is related to the data bit by bit and includes addresses of output lines of the interface; storing the switching algorithm in a switching RAM; controlling a switching unit with a control signal and controlling the switching information with the central controller; switching the data with the switching unit bit by bit to the output lines of the interface in accordance with the switching information; generating a starting address by an address mapping algorithm via a reading table from a number of a respective output lines; generating an intermediate data set from an offset address via a control data set, for taking into account different data rates; linking the intermediate data set and the starting address together, and transposing starting bits of the data set generated in the linking step, such that the switching information for the bits of one output line are distributed to non-cohesive cells of the switching RAM, so that in quasi-sequential processing of the switching RAM, the bits are read out of the input RAM in an order in which they are chronologically required for each output line; and outputting the data via the interface.