Patent ID: 6745275
Filing Date: 2004-06-01
Classification: G06F,G11C,H05K

Abstract:
A feedback system inside a computer capable of accommodating different memory module loading, a memory module having a loading pin and a simulating load with the simulating load connected to the loading pin, comprising:a plurality of memory module slots for plug-in of memory modules, wherein each memory module slot has a loading pin, and when a memory module is plugged into any one of the memory module slots, the loading pin of the memory module is also connected to the loading pin of the memory module slot; and a control chipset connected to the memory module slots, wherein the control chipset has a data strobe pin and a data strobe feedback pin, wherein the data strobe pin of the control chipset is first connected to the loading pin of any one of the memory module slots and then connected to the loading pins of the other memory module slots serially, the loading pin of the last memory module slot is connected to the data strobe feedback pin of the control chipset to form a signal feedback loop, and when memory modules are plugged into some or all of the memory module slots, the control chipset is able to utilize signals received from the data strobe feedback pin to emulate the delay caused by memory module loading at the memory slot and hence data can be accurately written to or read from the memory module, and wherein the data strobe pin of the control chipset is also used to transmit the data, and hence both data transmission and time adjustment are carried out via the signal feedback loop.