Patent ID: 8456004
Filing Date: 2013-06-04
Classification: H01L

Abstract:
1. A template wafer for small pitch flip-chip interconnect hybridization, comprising: a core Si wafer; a Ni layer on a front side of said Si wafer; an Al layer on said Ni layer on the front side; a layer on a backside of said Si wafer; an Al layer on said Ni layer on the backside; a nonconductive layer based on polytetrafluoroethylene up to a thickness of 20 microns as a top surface of said Al layer of said front side; and a nonconductive layer based on polytetrafluoroethylene on a back surface of said Al layer of said backside, wherein surface features are formed into said nonconductive layer of said front side, wherein said surface features are either etched or recessed down to expose said Ni layer on said front side to yield conductive features capable of indium plating to form indium bumps upon electroplating.