Patent ID: 9122578
Filing Date: 2015-09-01
Classification: G06F

Abstract:
1. A solid state memory for programming at least two data streams thereto, the solid state memory including: a target having at least two logical units, each logical unit having at least one page, wherein a page is programmed at one time, said target configured to store each of the at least two data streams in a different one of said at least two logical units to which a one of the at least two data streams is addressed; each logical unit including an internal buffer memory configured for temporarily storing the incoming data stream addressed to the associated one of the at least two logical units before the incoming data are programmed from the internal buffer memory associated with the logical unit to at least one page of the associated logical unit; and the internal buffer memory in each logical unit configured to be controlled to keep data which are not yet programmed to the associated logical unit when a switching operation to a different logical unit is performed; and said solid state memory including a controller unit for controlling the target and the at least two logical units, wherein the controller unit is configured: wherein the solid state memory is a NAND Flash device realized in accordance with an Open NAND Flash Interface (ONFI) specification, and wherein the states and commands defined herein comply with the ONFI specification.