Patent ID: 6162685
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method of fabricating a flash memory, said method comprising the steps of:providing a substrate having an oxide layer thereon;forming a first polysilicon layer with a first dielectric layer thereon extending along a first direction on said substrate;forming and patterning a second polysilicon layer on the first dielectric layer to form a plurality of controlling gates extending along a second direction of said substrate, wherein the first direction and the second direction are substantially perpendicular;patterning the first dielectric layer and the first polysilicon layer using the controlling gates as a mask, wherein the first polysilicon layer is patterned to form a plurality of floating gates, with the floating gates, the patterned first dielectric layer, and the controlling gates together forming a plurality of stacked gates;forming tunnel diffusion regions and doped regions alternatively between the stacked gates, wherein the tunneling diffusion regions extend towards parts of the substrate under the stacked gates and the doped regions have a lateral distance extending away from the stacked gates; andforming a second dielectric layer and a third polysilicon layer covering the stacked gates and extending along the first direction.