Patent ID: 7449382
Filing Date: 2008-11-11
Classification: H01L

Abstract:
1. A method of fabricating a memory device, comprising: providing a substrate; forming a plurality of pillars on the substrate, wherein each pillar has a plurality of epitaxial layers, a first sidewall and a second sidewall, and is sequentially defined to form a first source/drain region, a channel region, and a second source/drain region from a bottom of each pillar, a trench is disposed between the pillars, and the first source/drain region acts as a top electrode; forming a node dielectric layer on the first sidewall and the second sidewall, in a lower portion of the trench, and adjacent to the top electrode; forming a common bottom electrode in a lower portion of the trench and surrounded by the node dielectric layer; forming a first insulating layer on the common bottom electrode inside the trench; forming a double layer on the first sidewall and the second sidewall, above the first insulating layer, and inside the trench, wherein the double layer comprises a gate dielectric layer and a gate conductive layer; forming a second insulating layer in a space surrounded by the double layer inside the trench; removing a portion of the double layer on the first sidewall to form a plurality of slots on the first sidewall and a plurality of gate structures on the second sidewall; forming a third insulating layer in a lower portion of the slots; forming a body line on the third insulating layer inside the slots; and filling a fourth insulating layer into the slots.