Patent ID: 6130126
Filing Date: 2000-10-10
Classification: H01L

Abstract:
A method of fabricating a DRAM array comprising the steps of:providing a region of semiconductor material having a plurality of transistors disposed therein;providing a dielectric over said region of semiconductor material having a first isolating trench with sidewalls extending entirely through said dielectric and into said region of semiconductor material and surrounding said plurality of transistors and a plurality of second trenches with sidewalls extending into said dielectric, each said second trench associated with a different one of said transistors;conformally depositing a layer of silicon on the surface of said dielectric including the sidewalls of said plurality of trenches and the first isolation trench;removing said layer of silicon from said surface within said first isolating trench and at most partially into said plurality of second trenches;then removing said dielectric disposed within said first isolating trench; andcompleting fabrication of a capacitor in each of said second trenches.