Patent ID: 7301383
Filing Date: 2007-11-27
Classification: H03K

Abstract:
1. A circuit for controlling phase, comprising: a first node operative to provide a flow of a current responsive to a first clock signal; a first plurality of switch circuits coupled to said first node; a first plurality of current supply sources coupled to said first plurality of switch circuits, respectively; a second node operative to provide a flow of a current responsive to a second clock signal; second plurality of switch circuits coupled to said second node; and a second plurality of current supply sources coupled to said second plurality of switch circuits, respectively, wherein said first node and said second node are coupled to each other such as to combine the first clock signal and the second clock signal, at least one of said first plurality of current supply sources having a current supply amount different from a current supply amount of another one of said first plurality of current supply sources, and at least one of said second plurality of current supply sources having a current supply amount different from a current supply amount of another one of said second plurality of current supply; and wherein said first plurality of current supply sources and said second plurality of current supply sources are configured to have respective current supply amounts such that a third clock signal made by combining the first clock signal and the second clock signal has a phase change responding to a change in opening and closing of said first plurality of switch circuits and said second plurality of switch circuits, said third clock signal having a substantially constant amplitude despite said phase change.