Patent ID: 8555015
Filing Date: 2013-10-08
Classification: G06F,G09C,H04L

Abstract:
1. A secure microcontroller comprising: a memory that stores data; a processing unit that generates a plurality of commands; an access control, coupled to receive the plurality of commands, the access control having a plurality of privilege registers that define access rights to the data stored within the memory; a first privilege register, within the plurality of privilege registers, that defines a first set of access rights to a first portion of the data within the memory; a second privilege register, within the plurality of privilege registers, that defines a second set of access rights to a second portion of the data within the memory, the second portion being different than the first portion; and an exception handler, coupled to the access control, that interrupts an access command to the first portion of the data in response to the access command failing to meet the first set of access rights associated with the first portion of data; wherein the access rights relate to a plurality of user privilege levels for the secure microcontroller.