Patent ID: 7900107
Filing Date: 2011-03-01
Classification: G01R

Abstract:
1. A chip with internal comparison circuits, comprising: a scan chain group, having at least one scan chain, receiving test patterns from an external test machine and outputting scanned-out test patterns; a bi-directional output buffer group, coupled to the scan chain group and the test machine, under a first mode, the bi-directional output buffer group receiving the test patterns from the test machine, and under a second mode, the bi-directional output buffer group outputting the scanned-out test patterns from the scan chain group to the test machine; and a comparator group, coupled to the scan chain group and the bi-directional output buffer group, under the first mode, the comparator group receiving the test patterns from the test machine via the bi-directional output buffer group and receiving the scanned-out test patterns from the scan chain group to produce a comparison signal indicating whether the chip is passed or not Wherein the first mode is a high speed mode and the second mode is a normal speed mode.