Patent ID: 6943595
Filing Date: 2005-09-13
Classification: H03K,H04L

Abstract:
1. A synchronization circuit for receiving an input signal and a clock having a frequency which is equal to a transfer rate of the input signal, and synchronizing the input signal with the clock, said circuit comprising: a state detection circuit for receiving the input signal and the clock, and outputting a control signal according to the temporal relationship between a transition point of the input signal and an edge of the clock; a delay selection circuit for directly receiving the input signal and the control signal outputted from said state detection circuit, adding a delay to the input signal on the basis of the control signal, and outputting an output signal; and a latch circuit for receiving the clock and the output signal outputted from said delay selection circuit, synchronizing the output signal outputted from said delay selection circuit with the clock and outputting the synchronized signal.