Patent ID: 6028800
Filing Date: 2000-02-22
Classification: G11C

Abstract:
A semiconductor memory comprising:a pair of bit lines;a plurality of word lines;a plurality of memory cells each coupled to one of said pair of bit lines and one of said plurality of word lines;a sense amplifier including a pair of PMOS transistors and a pair of NMOS transistors, wherein each pair of transistors has sources coupled in common, drains coupled to said pair of bit lines, respectively, and gates cross-coupled to said drains, respectively;a first external pad for receiving one of a first external positive supply voltage and second external positive supply voltage, wherein the voltage value of said first external supply voltage is higher than that of said second external supply voltage;a second external pad for receiving a ground voltage;a switch PMOS transistor having a drain coupled to sources of said pair of PMOS transistors and a source coupled to said first external pad;a first drive transistor having a source-to-drain path provided between a gate of said switch PMOS transistor and said second external pad; anda second drive transistor having a source-to-drain path connected in parallel with said source-to-drain path of said first drive transistor;wherein one of said first and second drive transistors drives said switch PMOS transistor when said first external supply voltage is supplied to said first external pad; andwherein both of said first and second drive transistors drive said switch PMOS transistor when said second external supply voltage is supplied to said first external pad.