Patent ID: 6603158
Filing Date: 2003-08-05
Classification: H01L

Abstract:
A semiconductor integrated circuit comprising base cells arrayed in first and second directions perpendicular to each other, each base cell comprising:an N-type well; a plurality of P-type regions formed in said N-type well and arrayed in said second direction; a P-type well arranged adjacent to said N-type well in said first direction; a plurality of N-type regions formed in said P-type well and arrayed in said second direction; gate lines each extending in said-first direction with passing above a channel between adjacent two of said P-type regions and passing above a channel between adjacent two of said N-type regions, each of said gate lines not having a gate contact region on either end thereof; an N-type well contact region formed in said N-type well adjacent to a first directional end of one of said gate lines, said N-type well contact region being not along said gate lines; a P-type well contact region formed in said P-type well adjacent to an opposite first directional end of one of said gate lines, said P-type well contact region being not along said gate lines; an intra-cell interconnection formed in a first wiring layer; a first power supply line connected to said N-type well contact region with passing in said second direction, said first power supply line formed in a second wiring layer; and a second power supply line connected to said P-type well contact region with passing in said second direction, said second power supply line formed in said second wiring layer.