Patent ID: 6251710
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A method of forming an interconnect structure including a patterned anti-fuse dielectric layer formed on surface of a substrate, said method comprising the steps of:(a) forming an anti-fuse dielectric layer on a surface of a substrate, said substrate having a first level of electrically conductive features;(b) forming an interlevel dielectric layer on said anti-fuse dielectric layer;(c) forming vias in said interlevel dielectric layer exposing portions of said anti-fuse dielectric layer that overlay said first level of electrically conductive features;(d) forming a wire level mask on said interlevel dielectric layer, wherein at least one of said vias and a portion of said interlevel dielectric layer are left exposed;(e) etching exposed portions of said anti-fuse dielectric layer from said exposed vias, wherein during said etching a portion of said exposed interlevel dielectric layer is removed so as to form a space wherein a second level of electrically conductive features will be subsequently formed;(f) stripping said wire level mask; and(g) filling said vias including said spaces with a conductive material, whereby said second level of electrically conductive features is formed.