Patent ID: 6549477
Filing Date: 2003-04-15
Classification: G11C

Abstract:
A memory system comprising:a reference voltage generator operative to, when activated in response to an activation signal, ramp up to and provide a reference signal at a predetermined level; a control system operative to, when activated in response to the activation signal, control operations performed relative to at least one memory cell based on the reference signal; a wait system operative to provide a wait signal to the control system in connection with each operation to be performed relative to the at least one memory cell; wherein the control system delays performance of at least an initial operation relative the at least one memory cell by a first duration in response to an initial wait signal provided by the wait system during a given user mode, and the control system delays performance of subsequent operations relative the at least one memory cell in the given user mode by a second duration, which is less than the first duration, in response to subsequent wait signals provided by the wait system in the given user mode, whereby the delayed initial operation relative the at least one memory cell in the given user mode facilitates stabilization of the reference voltage prior to performing the delayed operation; a pump circuit operative to generate a boosted voltage greater than a supply voltage when the initial operation is one of a program operation and an erase operation in response to the control system; and a regulator circuit operative to receive the elevated voltage from the pump circuit and generate a controlled voltage signal based on the voltage and the reference signal, respectively, for application to the at least one memory cell.