Patent ID: 7650465
Filing Date: 2010-01-19
Classification: G06F,Y02D

Abstract:
1. A processor that implements load and store instructions, comprising: a cache that includes a plurality of datarams; a processor pipeline register that stores base address data bits and offset data bits; and a micro tag array, coupled to the cache and the processor pipeline register, wherein the micro tag array comprises: if first selected base address data bits stored in the processor pipeline register match base address data bits stored in the base register of the micro tag array, and if first selected offset data bits stored in the processor pipeline register match offset data bits stored in the offset register of the micro tag array, and if a second carry bit formed by an addition of second selected base address data bits stored in the processor pipeline register and second selected offset data bits stored in the processor pipeline register match the first carry, the micro tag array outputs an enable signal that enables a first dataram of the cache specified by way selection data bits stored in the way selection register of the micro tag array.