Patent ID: 6205463
Filing Date: 2001-03-20
Classification: G06F

Abstract:
An adder comprising:a first block in a first half of the adder to generate at least two sum bits and a section carry signal, the at least two sum bits and the section carry signal being generated in parallel;a second block in a second half of the adder to generate at least two additional sum bits, a corresponding block carry signal and corresponding group generate and group propagate signals of the block; anda third block in the second half of the adder to receive the section carry signal and the corresponding block carry signal, the third block including (i) a carry processor to process the section carry signal and to output a second block carry signal corresponding to the third block, and (ii) a sum selector to generate a sum bit from the corresponding group generate and group propagate signals, the second block carry signal and the sum bit being generated in parallel.