Patent ID: 6271692
Filing Date: 2001-08-07
Classification: G11C,H03K

Abstract:
A semiconductor integrated circuit which receives an input signal and a test signal, the input signal having a first potential level and a second potential level which is lower than the first potential level, and the test signal having a third potential level which is higher than the first potential level, the semiconductor integrated circuit comprising:an input terminal receiving the input signal and the test signal;a first potential source supplying the first potential level;a second potential source supplying the second potential level;a first PMOS transistor coupled between said input terminal and said first potential source, wherein said first PMOS transistor turns on when said input terminal is at a first voltage which is higher than the third potential level;a first NMOS transistor coupled between said input terminal and said second potential source, wherein said first NMOS transistor turns on when said input terminal is at a second voltage which is lower than the second potential level;an internal circuit coupled to said input terminal, said internal circuit operating in response to the input signal and being in a test mode in response to a test mode signal; anda voltage determining circuit coupled to said input terminal and said internal circuit, said voltage determining circuit outputting the test mode signal in response to the test signal.