Patent ID: 6458649
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A method of forming a capacitor-over-bit line memory cell comprising;forming a pair of spaced-apart word lines over a substrate having a substrate location therebetween with which electrical communication with a bit line is desired; forming conductive bit line material over the word lines and the substrate location; after forming the conductive bit line material, providing patterned bit line material by removing at least some of the conductive bit line material and outwardly exposing said substrate location; and forming conductive interconnect material over the substrate location and in electrical communication with both the substrate location and the patterned bit line material, wherein: the removing of the conductive bit line material comprises also exposing other substrate locations different from the substrate location between the pair of spaced-apart word lines with which electrical communication with a bit line is desired; and the forming of the conductive interconnect material comprises forming said conductive interconnect material over and in electrical communication with said other substrate locations.