Patent ID: 8793548
Filing Date: 2014-07-29
Classification: G01R,G06F

Abstract:
1. An integrated circuit comprising: an input pattern control circuit which counts a cycle number of an input pattern supplied to a test object circuit, and which stops supply of the input pattern and a first clock to the test object circuit when the cycle number of the input pattern coincides with a certain count number; and a scan control circuit which supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit based on a control signal from the input pattern control circuit, while the input pattern control circuit stops the supply of the input pattern, wherein the scan control circuit applies a second clock having a frequency accessible to the test object circuit from outside, to the test object circuit, for cycles corresponding to a length of the scan chain, after the input pattern control circuit stops the supply of the first clock to the test object circuit.