Patent ID: 8209463
Filing Date: 2012-06-26
Classification: G06F

Abstract:
1. A memory system, comprising: a controller that regulates read and write access to one or more FLASH memory devices employed for random access memory (RAM) applications, the controller communicates with the one or more FLASH memory devices over a first channel configured as a FLASH memory channel, wherein the controller is an application specific integrated circuit configured to occupy and communicate with an expansion memory slot of a computer, and wherein at least one FLASH memory device of the one or more FLASH memory devices is utilized as a main memory for the memory system; an address and data bus comprising the first channel configured as the FLASH memory channel and a second channel configured as a RAM channel; a buffer component comprising a RAM that communicates with the controller over a second channel configured as the RAM channel, and operates in conjunction with the controller to regulate read and write access to the one or more FLASH memory devices, wherein the buffer component is not visible to the main memory or an operating system architecture associated with the memory system; at least one of: a first expansion slot adapted with dual inline memory modules for additional RAM buffer capacity or a second expansion slot adapted with dual inline memory modules for additional FLASH memory capacity; a wear leveling component that employs the buffer component to remap a heavily used FLASH memory sector to a lightly used FLASH memory sector utilizing a FLASH sector table that delineates sectors of the one or more FLASH memory devices with a format comprising at least one of a FLASH sector number, a data valid bit, or a wear bit; and a victim page handling component that evicts one or more memory sectors from the buffer component to the one or more FLASH memory devices in response to occurrence of a conflict associated with the buffer component.