Patent ID: 6404036
Filing Date: 2002-06-11
Classification: G11C,H01L

Abstract:
A layout structure of an interconnection which feeds a fixed voltage level to a sense amplifier provided in a cell array block of a semiconductor memory device,wherein the interconnection selectively extends only on an inside of an outer edge of a second conductivity type outside well region provided along one peripheral side of a first conductivity type well region, in which the cell array block is provided; wherein the second conductivity type outside well region is free of any transistors for a sense amplifier bank; wherein a second conductivity type isolation well is provided, which defines a memory cell region, and a first side region of the second conductivity type isolation well has first conductivity type transistors for the sense amplifier bank, and the first side region of the second conductivity type isolation well is separated from the second conductivity type outside well region by a first conductivity type sub-well region of the first conductivity type well region, and the first conductivity type sub-well region is defined between the second conductivity type outside well region and the first side region of the second conductivity type isolation well, and the first conductivity type sub-well region has second conductivity type transistors for the sense amplifier bank; and wherein a second conductivity type deep well region extends on a bottom of the first conductivity type well region and also extends on a bottom the first conductivity type sub-well region, and a first side of the second conductivity type deep well region is terminated by the second conductivity type outside well region, and a bottom of the second conductivity type isolation well reaches the second conductivity type deep well region.