Patent ID: 7331029
Filing Date: 2008-02-12
Classification: G06F

Abstract:
1. A system for designing an integrated circuit, comprising: a) a wire model objects generator (“WMG”) for generating and inserting wire model objects (“WMOs”) into a schematic of said integrated circuit based on sizing and placement of components of said intergrated circuit; b) an early timing analyzer for performing an early timing analysis (“ETA”) on said schematic; and c) a central processor for causing said WMG to generate and insert said WMOs, and for generating and inserting new WMOs after re-sizing and/or re-placing said components, if said ETA fails, wherein the WMG comprises: a connectivity and placement data extractor for retrieving from a first schematic file connectivity and placement data; a geometry estimator (“GE”) for utilizing the retrieved connectivity and placement data to estimate a corresponding wire routing geometry for each signal in the integrated circuit, said wire routing geometry consists of one or more source and target points interconnected by line segments; a wire model embedder (“WME”) for deciding a number and type of WMOs each segment and “via” connection will be substituted with; and an insertion means for generating a second schematic file by inserting the WMOs into the schematic of said integrated circuit, said insertion means determines where to add intermediate nodes to the second schematic file to accommodate for cascading WMOs.