Patent ID: 6038165
Filing Date: 2000-03-14
Classification: G11C

Abstract:
A nonvolatile memory device in which data of two bits or more are stored in one memory cell by setting a threshold value of said memory cell to three or more stages and by changing a level of a word line to two or more stages to read said memory cell, comprising:a binary data register latching program data which includes a plurality of bits;a data transforming logic circuit executing a predetermined operation for the plurality of bits in the program data to transform the program data into multi-value data according to a combination in binary data represented by the plurality of bits;an inverse transforming logic circuit for transforming the multi-value data read out from said memory cell into the binary data represented by the plurality of bits;a memory array including a plurality of memory cells;a selection circuit selecting a memory cell from the memory array;a control circuit sequentially changing a program voltage to be supplied to the selected memory cell to program said multi-value data in the selected memory in a memory array; anda circuit coupled to the word line and sequentially changing a voltage to be supplied to the word line in a program verifying operation in which a threshold voltage is verified and in a reading operation in which data is read out from the memory cell, in a direction apart from the voltage which is set to the word line in an erasure operation in which a threshold voltage of the memory cell is changed to a predetermined value.