Patent ID: 6388484
Filing Date: 2002-05-14
Classification: H03K,H03L

Abstract:
A clock control circuit, comprising:a forward-pulse delay line which is configured by cascading delay elements in a first number of stages; a rearward-pulse delay line which is configured by cascading delay elements in a second number of stages; an input device for taking in a first clock signal and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal; a pulse generating device including a forward-pulse generating device for generating a forward pulse by delaying said second clock signal as much as second delay time; a control circuit, connected to said delay elements of said forward-pulse delay line and said rearward-pulse delay line, which controls a period of time for said forward pulse to propagate in said forward-pulse delay line, controls said forward-pulse delay line to be initialized, controls a rearward pulse to be produced in said rearward-pulse delay line and controls a period of time for said rearward-pulse to propagate in said rearward-pulse delay line; said pulse generating device generating a control pulse, which is synchronized with said second clock signal, using said second clock signal and forward pulse from said forward-pulse generating device, inputting said control pulse to said control circuit and controlling the operation of said control circuit; and an output device for outputting a third clock signal, which is synchronized with said first clock signal by delaying said rearward pulse outputted from said rearward-pulse delay line as much as third delay time.