Patent ID: 7965124
Filing Date: 2011-06-21
Classification: G06G,H03F

Abstract:
1. A switched-capacitor circuit, comprising: a fully differential amplifier, having a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal; a first adjustable feedback capacitor, having a first end coupled to the negative input terminal, and a second end coupled to the positive output terminal; a first switch, having a first end receiving a common mode potential, and a clock-control end receiving a first clock control signal; a second switch, having a first end coupled to the negative input terminal, a second end coupled to a second end of the first switch, and a clock-control end receiving a second clock control signal; a first twin sampling capacitor, having a first end coupled to the second end of the second switch, and a second end and a third end receiving a first positive input voltage relative to the common mode potential in response to a third clock control signal; a second adjustable feedback capacitor, having a first end coupled to the positive input terminal, and a second end coupled to the negative output terminal; a third switch, having a first end receiving the common mode potential, and a clock-control end receiving the first clock control signal; a fourth switch, having a first end coupled to the positive input terminal, a second end coupled to a second end of the third switch, and a clock-control end receiving the second clock control signal; a second twin sampling capacitor, having a first end coupled to the second end of the fourth switch, and a second end and a third end receiving a first negative input voltage relative to the common mode potential in response to the third clock control signal; a first switching unit, coupled to the second ends and the third ends of the first and the second twin sampling capacitors, the positive output terminal and the negative output terminal, for determining coupling relations respectively between the second ends and the third ends of the first and the second twin sampling capacitors and the positive output terminal and the negative output terminal in response to a fourth clock control signal; and an output switching unit, coupled to the positive output terminal and the negative output terminal, for outputting a differential output signal in response to the third clock control signal.