Patent ID: 8467664
Filing Date: 2013-06-18
Classification: G11B,H04N

Abstract:
1. A semiconductor integrator circuit for receiving a series of data including a main-view video stream, a sub-view video stream, and a graphics stream, and then performing video signal processing on the received data, wherein the main-view video stream used to provide a plurality of main-views of a plurality of stereoscopic video images, a decoded main-view video stream being presented on a main-view video plane; the sub-view video stream used to provide a plurality of sub-views of the plurality of stereoscopic video images, a decoded sub-view video stream being presented on a sub-view video plane; and the graphics stream used to provide a plurality of graphics images, a decoded graphics stream being presented on a graphics plane, wherein the sub-view video stream is multiplexed in a transport stream, a plurality of transport packets being formed from the transport stream, wherein each of the plurality of transport packets has information indicating whether the transport packet contains offset information, wherein the sub-view video stream includes the offset information, wherein a first shifted graphics plane and a second shifted graphics plane are formed based on the graphics plane on which the decoded graphics stream is presented and the offset information, wherein data formed from the main-view video plane on which the decoded main-view video stream is presented and data formed from the first shifted graphics plane are overlaid, and wherein data formed from the sub-view video plane on which the decoded sub-view video stream is presented and data formed from the second shifted graphics plane are overlaid, the semiconductor integrated circuit comprising: a main control unit operable to control the semiconductor integrated circuit; a stream processing unit operable to receive the series of data, temporarily store the series of data into a memory internal or external to the semiconductor integrated circuit, and then demultiplex the series of data into the picture data and the graphics data; a signal processing unit operable to decode the picture data and the graphics data; and an AV output unit operable to output the picture data decoded by the signal processing unit, wherein the stream processing unit comprises a switching unit operable to receive the series of data and switch storage location thereof between a first area and a second area in the memory, the main control unit controls the switching unit to store picture data belonging to the main-view data groups and the sub-view data groups in the first area and the second area, respectively, among the picture data decoded, data belonging to the main-view data groups is stored into a third area in the memory, the third area corresponding to a main-view video plane, among the picture data decoded, data belonging to the sub-view data groups is stored into a fourth area in the memory, the fourth area corresponding to a sub-view video plane, the graphics data decoded is stored into a fifth area in the memory, the fifth area corresponding to a graphics plane, the AV output unit comprises an image superimposing unit operable to superimpose one of the graphics data decoded and the picture data decoded on the other, the signal processing unit monitors TS priority flags of TS packets included in the series of data, and extracts the metadata, the image superimposing unit provides a positive offset and a negative offset for horizontal coordinates in the graphics plane to generate a pair of graphics planes according to offset information included in the metadata extracted by the signal processing unit, and then superimposes the pair of graphics planes separately on the main-view video plane and the sub-view video plane, and the AV output unit outputs the picture data decoded after the graphics data decoded is superimposed thereon.