Patent ID: 6420918
Filing Date: 2002-07-16
Classification: H03L,H04N

Abstract:
A phase locked loop, comprising:means for generating a clock signal; means requiring a control signal having a given bias voltage for controlling said clock signal generating means; an integrator for developing said control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to said given bias voltage; a first switch coupled to said first and second voltage sources and responsive to said clock signal for developing a regenerated clock signal having a peak to peak voltage determined by said voltage potential; and, a second switch responsive to said external synchronizing signal for periodically sampling portions of said regenerated clock signal and coupling said sampled portions to said integrator, said sampled portions charging and discharging said integrator to generate said control signal with a large enough magnitude to provide said given bias voltage, whereby said first and second switches form a phase detector for synchronizing said clock signal generating means to said external synchronizing signal.