Patent ID: 6239037
Filing Date: 2001-05-29
Classification: H01L

Abstract:
A self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which a plurality of active elements is provided extending along separate parallel lines, e.g., bit lines, including memory cells comprising gate regions formed by a second conducting layer, a dielectric interpoly layer and a third conducting layer, said gate regions being insulated from each other by at least one dielectric insulation film to form said architecture with said word lines being defined photolithographically by protective strips, the process comprising:etching with vertical profile for complete removal from the gate regions of the first conducting layer and the second conducting layer;subsequently etching the dielectric interpoly layer accompanied by a considerable erosion of the dielectric film of the insulation region in such a manner as to totally uncover the third conducting layer of the gate regions; andetching the third conducting layer after it is uncovered.