Patent ID: 7567481
Filing Date: 2009-07-28
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a sub-array comprising a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines arranged in a direction perpendicular to the plurality of bit lines, wherein the sub-array is arranged in a sub-array area; a plurality of sub-word line drivers divided into a plurality of groups and coupled to the plurality of word lines, wherein each of the plurality of groups includes a predetermined number of sub-word line drivers, wherein the plurality of sub-word line drivers is arranged in a word line driver area; a plurality of enable signal generators adapted to generate word line enable signals, wherein the pluralitv of enable signal generators are arranged in a signal generator area; a plurality of decoding signal generators adapted to generate decoding signals, wherein the plurality of decoding signal generators are arranged in the signal generator area; and, a plurality of inverted decoding signal generators adapted to generate inverted decoding signals, wherein: the word line enable signals and the decoding signals are communicated to the sub-word line drivers solely in a word line direction, and the word line driver area is located between the sub-array area and the signal generator area.