Patent ID: 7286391
Filing Date: 2007-10-23
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a plurality of memory cells arranged in matrix of rows and columns; a plurality of word lines arranged for each row of said plurality of memory cells; a plurality of bit line pairs arranged for each column of said plurality of memory cells, each of said plurality of memory cells including a data storage portion holding data, and a data write/read portion performing write/read of data to/from said data storage portion, and said data storage portion having first and second inverter circuits connected in common to each of a power supply line and a ground line arranged corresponding to respective columns of said plurality of memory cells; and a potential line level control circuit controlling a potential level of said power supply line to a power supply potential or to a first potential level lower than the power supply potential for each column in response to a level control signal set for each column, and controlling a potential level of said ground line to a ground potential or to a second potential level higher than the ground potential for each column in response to a level control signal set for each column.