Patent ID: 7049867
Filing Date: 2006-05-23
Classification: H03L

Abstract:
1. A PLL (Phase Locked Loop) circuit comprising: a voltage-controlled oscillator for varying an oscillating frequency depending on a control voltage, and outputting a clock as the oscillating frequency of N times (N is an arbitrary positive integer of 2 or more) as much as the frequency of a reference input signal in a phase locked state, the reference input signal including synchronizing signals generated within a predetermined time interval at periods including one first period, and plural second periods, each of the plural second periods being smaller than the first period; a differentiating circuit for inputting the reference input signal, and outputting a differentiated signal at timings of the synchronizing signals of the reference input signal; a first counter for counting the clock and outputting a first signal representing a count value thereof, said first counter being reset by the differentiated signal; a second counter for counting the clock and outputting a second signal representing a count value thereof; a reset pulse generating circuit for outputting a first reset pulse when the count value of said second counter reaches N; a phase comparator for receiving said first signal and said second signal and outputting a phase error signal that indicates phase difference between the first and second signals; a charge pump for outputting a charge or discharge current to a loop filter in response to said phase error signal; said loop filter for holding and outputting said control voltage and varying said control voltage by said charge or discharge current; and a discontinuous input detecting part for receiving the reference input signal, and outputting a second reset pulse upon receiving a synchronizing signal initially generated after the first period is elapsed from the timing when receiving a further synchronizing signal generated after the second period, wherein said second counter is reset to be a certain value in accordance with one of the first reset pulse and the second reset pulse.