Patent ID: 8860463
Filing Date: 2014-10-14
Classification: G06F,H03K

Abstract:
1. A fast dynamic register, comprising: a data block coupled between a first precharge node and a discharge node, wherein said data block receives at least one data input and evaluates by pulling said first precharge node to said discharge node when a clock node transitions from a first clock state to a second clock state; a precharge circuit that precharges both a second precharge node and said first precharge node high while said clock node is in said first clock state, that releases said first precharge node and pulls said discharge node low when said clock node transitions to said second clock state, and that discharges said second precharge node low when said first precharge node remains high after said clock node transitions to said second clock state; a transparent latch having a latch input coupled to said second precharge node and an output coupled a store node, wherein said transparent latch is transparent to pass a state of said second precharge node to said store node while said clock node is in said second clock state, and wherein said transparent latch latches said store node when said clock node is in said first clock state; and an output logic gate that drives an output node to a state based on states of said second precharge node and said store node.