Patent ID: 7074671
Filing Date: 2006-07-11
Classification: H01L

Abstract:
1. A method for forming a control gate electrode layer of a semiconductor device electrode in which a gate insulation layer, a polysilicon layer for a floating gate electrode, and an intergate dielectric layer are sequentially stacked on a semiconductor substrate, the method comprising: a) forming an amorphous silicon layer on the intergate dielectric layer; b) annealing the amorphous silicon to form a polysilicon layer; c) forming an amorphous silicon capping layer on the polysilicon layer; and d) forming a silicide layer on the capping layer, using dichlorosilane, wherein the silicide layer comprises tungsten silicide, and wherein forming the tungsten silicide layer comprises; supplying a first silane (SiH supplying a dichlorosilane (SiH purging the dichlorosilane (SiH supplying a second silane (SiH