Patent ID: 9099198
Filing Date: 2015-08-04
Classification: G11C

Abstract:
1. A semiconductor memory apparatus comprising: a memory block configured to include a plurality of memory cells to hold data; a precharge control unit configured to control precharging the memory cells; a row decoder configured to output a row selection signal identifying a row address of the memory cells; an integral circuit configured to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit configured to determine whether the integral value of the integral circuit is greater than or equal to the predetermined value, wherein the precharge control unit turns off precharging the memory cells when the determination unit determines that the integral value of the integral circuit is greater than or equal to the predetermined value.