Patent ID: 8390346
Filing Date: 2013-03-05
Classification: H04L

Abstract:
1. A system for synchronizing the operation of a circuit with a control signal comprising: a plurality of synchronization flip-flops operating in cascade for receiving as input a control signal to be synchronized and providing as output a corresponding control signal synchronized with a clock signal; and a circuit comprising a finite state machine cadenced with said clock signal having a plurality of state flip-flops for storing the current state of said finite state machine, and having at least one first state, wherein said finite state machine is configured for: remaining in said first state codified with a first bit sequence if said synchronized control signal has a first logic value, proceeding to a second state codified with a second bit sequence if said synchronized control signal has a second logic value, wherein said first bit sequence and said second bit sequence differ by the value of a single bit, and wherein a last synchronization flip-flop comprises a state flip-flop in which is stored said single bit.