Patent ID: 6069512
Filing Date: 2000-05-30
Classification: H03K

Abstract:
A switching circuit to latch a voltage at a node, the switching circuit comprising:a power supply circuit to provide a supply voltage;a CMOS inverter having an input terminal with a voltage responsive to the node voltage, having an output terminal, and comprising a first pMOSFET;a first nMOSFET having a gate with a logic level equal to the logic level of CMOS inverter output terminal;a second pMOSFET having a drain connected to the first nMOSFET drain;an inverter coupling the second pMOSFET gate to the node to provide at the gate of the second pMOSFET a logic level equal to the complement of the logic level of the node; anda bias circuit coupled to the power supply and the source of the first pMOSFET to raise the threshold voltage of the first pMOSFET compared to when the source and substrate of the first pMOSFET are at the supply voltage.