Patent ID: 8558349
Filing Date: 2013-10-15
Classification: H01L

Abstract:
1. A high voltage integrated circuit comprising: a P substrate; a deep N well, disposed in the P substrate, wherein a wall of the deep N well forms a high voltage junction barrier, wherein the deep N well extends from an upper-most surface of the P substrate; a control circuit, located an outside of the deep N well; a MOS circuit, located an inside of the deep N well, wherein the MOS circuit is within the deep N well with separation from other circuit; an insulating layer over the deep N well, extending from the inside of the deep N well to the outside of the deep N well; a first metal layer, disposed on the insulating layer over the high voltage junction barrier of the deep N well; a dielectric layer on the first metal layer with an end portion contacting on the insulating layer to fully insulate the first metal layer; and a second metal layer, disposed above and on the dielectric layer with an end portion on the insulating layer, so that the first metal layer and the dielectric layer are enclosed within the second metal layer; wherein the first metal layer, the second metal layer and the dielectric layer form a capacitor located above a periphery region of the deep N well without direct connection to the deep N well for feeding a control signal of the control circuit to the floating circuit, and wherein the deep N well forms the high voltage junction barrier isolating the control circuit from the floating circuit, wherein the floating circuit is within the deep N well without direct connection to the capacitor.