Patent ID: 6906365
Filing Date: 2005-06-14
Classification: H01L

Abstract:
1. A ferroelectric memory device comprising: a semiconductor substrate; a transistor including a source, a drain and a gate formed at a surface of said substrate; an insulating layer formed to cover said transistor; a ferroelectric capacitor having a laminated structure, including at least a lower electrode, a ferroelectric film, an upper electrode, and an upper protection electrode formed over said upper electrode; a barrier layer disposed on said upper protection electrode; an interlayer insulation layer formed on said upper protection electrode; and a wiring layer formed on said interlayer insulation layer to contact said upper protection electrode through a contact hole in said interlayer insulation layer, wherein said upper protection electrode contains at least one material selected from a group consisting of Ir and Ru and is directly formed on an entire upper surface of said upper electrode, and wherein said barrier layer comprises Si