Patent ID: 6347327
Filing Date: 2002-02-12
Classification: G06F

Abstract:
An apparatus that conditionally increments an operand, comprising:an operand comprising a plurality of dits that comprise two bits and a plurality of blocks that comprise four dits, said plurality of blocks comprises a least significant block and one or more higher blocks; an input 1-of-P increment selection signal, where P=2, that indicates whether said operand is to be incremented; a plurality of input 1-of-N operand signals, where N=4, each said input 1-of-N operand signal represents the value of one dit of said operand; a first N-NARY logic level that receives said input 1-of-P increment selection signal and said plurality of 1-of-N operand signals, said first N-NARY logic level increments the value of a first and second plurality of operand dits and determines whether incrementing said operand will cause a carry to propagate out of each one of said plurality of blocks; and a second N-NARY logic level that selects either the incremented value or the original value of said second plurality of operand dits and increments the value of a third plurality of operand dits if a carry propagates out of each block of lesser significance, said second level of logic produces a plurality of output 1-of-N result signals, where N=4, wherein each said output 1-of-N result signal represents the value of one dit of the result.