Patent ID: 8524559
Filing Date: 2013-09-03
Classification: H01L

Abstract:
1. A manufacturing method of a power transistor device, comprising: providing a substrate of a first conductive type; forming an epitaxial layer of a second conductive type different from said first conductive type on said substrate; forming a doped base region of said second conductive type in said epitaxial layer; forming at least one through hole in said epitaxial layer to expose said substrate; filling a first dopant source layer in said through hole, wherein said first dopant source layer comprises a plurality of dopants of said first conductive type; forming a first insulating layer on said first dopant source layer in said through hole; forming a gate structure on said first insulating layer; forming a second insulating layer on said gate structure; forming a second dopant source layer on said second insulating layer, wherein said second dopant source layer comprises a plurality of second dopants of said first conductive type; forming a doped source region in said doped base region; forming a doped drain region in said epitaxial layer; removing said second dopant source layer in said through hole; and forming a metal layer on said epitaxial layer and filling in said through hole.