Patent ID: 6694500
Filing Date: 2004-02-17
Classification: G01R,H01L

Abstract:
An arrangement for testing a design circuit pattern applied to a semiconductor wafer to comprise a circuit pattern having a plurality of circuits formed on the semiconductor wafer, wherein each of the circuits is designed for test according to an individual design condition as the object of measurement of electrical properties and evaluation, wherein the circuit pattern on the semiconductor wafer comprises a group of two or more test cells formed from the individual design conditions corresponding to respective ones of the plural circuits for the object of measurement of electrical properties and evaluation and having a switch or switches connected at one end or both ends thereof; a decoder for generating on/off signals to said switch or switches provided within the group of test cells for specifying an evaluated test cell chosen from the group of test cells for measurement of electrical properties and evaluation; one or more of address pads for providing an electrical signal specifying the evaluated test cell to the decoder; an input pad for providing an electrical input signal to the evaluated test cell; an output pad for receiving an electrical output signal from the evaluated test cell; one or more of contrastive evaluated test cells provided apart from the group of test cells; a contrastive evaluated input pad directly connected with one end of the contrastive evaluated test cell for inputting an electrical signal and provided for every one of the contrastive evaluated test cells; and a contrastive evaluated output pad directly connected with the other end of the contrastive evaluated test cell and provided for every one of the contrastive evaluated test cells to output an electrical signal.