Patent ID: 6181634
Filing Date: 2001-01-30
Classification: G11C

Abstract:
A multiple-port memory device comprising a memory cell array including a plurality of memory cells, an input circuit for responding to a write control signal to store a write data to one of said memory cells specified by a write address during a clock cycle of a system clock signal, an output circuit for responding to a read control signal to read a data from one of said memory cells specified by a read address during the same clock cycle, a coincidence detection section for generating a coincidence signal upon coincidence between the read address and the write address, a bypass circuit for responding to the coincidence signal to bypass the write data to said output circuit, and a timing circuit for responding to the coincidence signal to specify a timing between the write control signal and the read control signal, said timing being such that the read control signal leads with respect to the write control signal upon an absence of the coincidence signal and that the read control signal and the write control signal are generated substantially at the same time upon a presence of the coincidence signal.