Patent ID: 6542431
Filing Date: 2003-04-01
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory cell blocks, wherein each of the memory cell blocks includes a plurality of memory cells and a plurality of word lines connected to the memory cells; a plurality of row decoders connected to the plurality of memory cell blocks, wherein each of the row decoders selects one of the word lines in an associated one of the memory cell blocks; a plurality of sense amp groups connected to the plurality of row decoders, wherein each of the sense amp groups amplifies cell information read from the plurality of memory cells of an associated one of the memory cell blocks; a plurality of block control circuits connected to the plurality of memory cell blocks, wherein each of the block control circuits simultaneously selects multiple word lines in an associated one of the memory cell blocks and generates a sense amp control signal; and a plurality of sense amp drive circuits connected to the plurality of block control circuits and the plurality of sense amp groups, wherein each of the sense amp drive circuits selectively activates an associated one of the sense amp groups based on the sense amp control signal of the associated one of the block control circuits; wherein each of the block control circuits generates at least one reset signal and provides the reset signal to an associated one of the row decoders and to an associated one of the sense amp drive circuits, the reset signal being provided to the associated one of the row decoders so that the timing for selecting the word lines with the row decoders differs between each block, and the reset signal being provided to the associated one of the sense amp drive circuits so that inactivation of the plurality of sense amp groups differs between each block.