Patent ID: 7225311
Filing Date: 2007-05-29
Classification: G06F,G11C

Abstract:
1. A memory controller comprising: a first transmitter to output first and second write commands synchronously with respect to a timing signal, wherein: the first write command maintains a first phase relationship with a first transition of the timing signal and specifies a write operation of first data to a first memory device; and the second write command maintains a second phase relationship with a second transition of the timing signal and specifies a write operation of second data to a second memory device; a second transmitter to delay output of the first data to the first memory device using a first timing offset that is based on a difference between a time required for the timing signal to propagate to the first memory device and a time required for the first data to propagate to the first memory device; and a third transmitter to delay output of the second data to the second memory device using a second timing offset that is based on a difference between a time required for the timing signal to propagate to the second memory device and a time required for the second data to propagate to the second memory device, the time required for the timing signal to propagate to the first memory device being different from the time required for the timing signal to propagate to the second memory device, and the second timing offset being different from the first timing offset.