Patent ID: 6370630
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A data processor comprising:an X bit data bus operating at a first data rate, where X is the width of the data bus; a Y bit data bus operating at a second data rate, where Y is the width of the data bus and X is a multiple of Y, and the second data rate is the first data rate multiplied by the multiple; a Y bit data port coupled to the Y bit data bus, the Y bit data port to receive data from an external memory at the second data rate; a first processing unit coupled to the X bit data bus to receive X bits of data simultaneously; a memory controller coupled to the Y bit data bus and the X-bit data bus; a configuration control operably coupled to the memory controller via a configuration bus; and a input/output port operably coupled to the configuration control whereby configuration information may be provided to the memory controller via the configuration control.