Patent ID: 6327646
Filing Date: 2001-12-04
Classification: G06F

Abstract:
A content addressable memory comprising:a first input port to receive a signal indicative of [A].sub.n =(a.sub.n, a.sub.n-1, . . . , a.sub.1), where (a.sub.n, a.sub.n-1, . . . , a.sub.1) are n bits of an operand A;a second input port to receive a signal indicative of [B].sub.n =(b.sub.n, b.sub.n-1, . . . , b.sub.1), where (b.sub.n, b.sub.n-1, . . . , b.sub.1) are n bits of an operand B. where for i=1. . . n, b.sub.i has the same bit position in B that a.sub.i has in A; wherein [A].sub.n and [B].sub.n do not include the first bits, respectively, of A and B;memory cells to store a tag K.sub.n =(k.sub.n, k.sub.n-1, . . . , k.sub.1); anda fast adder-comparator to provide a word line signal indicative of whether [A+B].sub.n =K.sub.n, where [A+B].sub.n =(r.sub.n, r.sub.n-1, . . . , r.sub.1), where (r.sub.n, r .sub.n-1, . . . , r.sub.1) are n bits of (A+B), where for i=1. . . n, r.sub.i has the same bit position in (A+B) that a.sub.i and b.sub.i have in A and B, respectively.