Patent ID: 6411550
Filing Date: 2002-06-25
Classification: G11C

Abstract:
A semiconductor integrated-circuit device having a memory element and a sense amplifier circuit, comprising:an inverter amplifier comprising an inverter circuit and a first N-type MOS transistor for receiving, at a gate thereof, an output signal from the inverter circuit, wherein a drain of the first N-type MOS transistor is connected to an input of the inverter circuit; reference current generator means; a first P-type MOS transistor for receiving a signal from the reference current generator means and a second P-type MOS transistor which is connected in series with the first P-type MOS transistor and receives an output of the inverter amplifier at an input gate thereof; a third P-type MOS transistor connected in parallel with the first and second P-MOS transistors; and a second N-type MOS transistor for opening a current path to ground potential during a precharge operation.