Patent ID: 6552928
Filing Date: 2003-04-22
Classification: G11C

Abstract:
A write control circuit for a magnetic tunnel junction MRAM, comprising:a digit line including a first end electrically connected to a first write current source by a first write transistor having a gate controlled by a first write logic gate, and electrically connected to a first write current sink by a first sink transistor having a gate controlled by a first sink logic gate, a second end electrically connected to a second write current source by a second write transistor having a gate controlled by a second write logic gate, and electrically connected to a second write current sink by a second sink transistor having a gate controlled by a second sink logic gate, and a segment disposed in a first direction proximate to the magnetic tunnel junction MRAM; and a bit line including a third write current source electrically connected to a first end, a third write current sink electrically connected to a second end, and a segment, disposed in a second direction oriented approximately 90Â° to the first direction, proximate to the magnetic tunnel junction MRAM.