Patent ID: 8293605
Filing Date: 2012-10-23
Classification: H01L

Abstract:
1. A method for fabricating a CMOS integrated circuit comprising: epitaxially growing embedded silicon germanium in regions of a semiconductor substrate; forming SiGe-stressed source and drain regions in the embedded silicon germanium; forming non-SiGe-stressed source and drain regions in the semiconductor substrate; forming nickel silicide contacts in the SiGe-stressed source and drain regions and in the non-SiGe-stressed source and drain regions; depositing a tensile insulating layer overlying the nickel silicide contacts by a first process of plasma enhanced deposition prior to depositing a compressive insulating layer; removing a portion of the tensile insulating layer overlying the SiGe-stressed source and drain regions, leaving a remaining portion of the tensile insulating layer overlying all of the non-SiGe-stressed source and drain regions and thereafter curing the remaining portion; depositing the compressive insulating layer overlying the SiGe-stressed source and drain regions and the remaining portion of the tensile insulating layer by a second process of plasma enhanced deposition after curing the remaining portion of the tensile insulating layer; and removing a portion of the compressive insulating layer overlying the remaining portion of the tensile insulating layer.