Patent ID: 8479384
Filing Date: 2013-07-09
Classification: H01L,Y10T

Abstract:
1. A method for integrated circuit fabrication, the method comprising: depositing multiple layers over a substrate; patterning a first layer photolithographically to form original features in a first region and no features in a second region of the substrate; shrinking the original features to form shrunken features; extending a pattern having the shrunken features into at least one underlying layer; removing remaining portions of overlying layers from the at least one underlying layer to leave mandrels; blanket depositing spacer material on the mandrels; etching the spacer material to form spacers on the mandrels; removing the mandrels to leave a pattern of spacers pitch-reduced relative to the original features; blanket depositing a filler material on the spacer pattern; and planarizing the filler material using a protective coating deposited on the first region and the second region.