Patent ID: 6118722
Filing Date: 2000-09-12
Classification: G11C

Abstract:
An integrated circuit memory device comprising:a memory cell block including a memory cell array which has a plurality of odd and even numbered subword lines extending through said memory cell array;first word line decoding means disposed at a top side of said memory cell block, which receives a first row address and generates a plurality of first driving signals in response thereto;second word line decoding means disposed at a bottom side of said memory cell block, which receives said first row address and generates a plurality of second driving signals in response thereto;a row decoder which receives a second row address and generates a word line signal in response thereto;a first driver block including a first plurality of subword line drive circuits adjacent to said memory cell array, wherein each of said subword line drive circuits of said first plurality is connected to a respective odd numbered subword line of said memory cell array, and wherein said first plurality of subword line drive circuits drive said respective odd numbered subword lines responsive to odd numbered driving signals of said first and said second driving signals and said word line signal; anda second driver block including a second plurality of subword line drive circuits adjacent to said memory cell array opposite to said first driver block, wherein each of said subword line drive circuits of said second plurality is connected to a respective even numbered subword line of said memory cell array, and wherein said second plurality of subword line drive circuits drive said respective even numbered subword lines responsive to even numbered driving signals of the first and the second driving signals and said word line signal.