Patent ID: 6992674
Filing Date: 2006-01-31
Classification: G06T,G09G,G11C,H04N

Abstract:
1. A checkerboard buffer page system, comprising: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; at least two memory devices, each memory device having a plurality of memory pages including a plurality of memory locations, each memory location having an address, where data elements are stored in parallel to the memory devices and retrieved in parallel from the memory devices; and where each data element corresponds to an entry in one of a plurality of buffer pages, each buffer page having a plurality of entries along a first dimension corresponding to the first order and a plurality of entries along a second dimension corresponding to the second order, and at least one entry in each buffer page corresponds to a data element, where data elements are stored to the memory devices in the first order and retrieved from the memory devices in the second order, and where at least one memory page stores data elements in multiple locations according to the first order and stores data elements in multiple locations according to the second order, where at least two data elements that are consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements that are consecutive in the second order are retrieved in parallel from the memory devices, where a data element is pixel data corresponding to a pixel in a frame of pixels, the frame having horizontal rows of pixel and vertical columns of pixels, where the buffer pages are pixel pages, each pixel page having a plurality of pixel page rows and a plurality of pixel page columns, where addresses for storing and retrieving pixel data are generated using one or more counter variables, where counter variables include: