Patent ID: 6246623
Filing Date: 2001-06-12
Classification: G11C

Abstract:
A memory device comprising:at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;a column address circuit coupled to the address bus for selecting a column for a memory access that corresponds to a column address coupled to the column address circuit through the address bus;a control logic circuit having a plurality of inputs coupled to receive respective command signals, the control logic circuit being structured to generate a trigger signal in response to the command signals;at least one antifuse circuit, each antifuse circuit having an antifuse and being coupled to receive a read signal, each antifuse circuit being structured to generate a signal in response to the read signal;a timing antifuse in a timing circuit structured to provide a voltage to the timing circuit;a charging circuit in the timing circuit coupled to receive the trigger signal and structured to charge the timing antifuse in response to the trigger signal; anda voltage detection circuit in the timing circuit having an input coupled to the voltage from the timing antifuse and an output, the voltage detection circuit being structured to generate the read signal at the output in response to the trigger signal, the read signal having a duration corresponding to the time needed to charge the timing antifuse to a threshold voltage.