Patent ID: 8045373
Filing Date: 2011-10-25
Classification: G11C

Abstract:
1. A method for reducing disturbs in an array of memory cells, comprising: selecting a first row of the array of memory cells for a write operation, the first row comprising a first memory cell in a first column of the array of memory cells and a second memory cell in a second column of the array of memory cells, wherein the first memory cell connected between a first bit line and a first source line and the second memory cell connected between a second bit line and a second source line, wherein each of the memory cells includes a memory transistor and a pass transistor; connecting the first bit line to the first source line and the second bit line to the second source line, wherein the first source line is equipotential with the first bit line and the second source line is equipotential with the second bit line; and erasing the first row of the array of memory cells.