Patent ID: 7468299
Filing Date: 2008-12-23
Classification: H01L

Abstract:
1. A method comprising: providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and forming a gate above the charge-trapping layer, wherein the dielectric material is disposed in steps comprising: depositing a masking layer on a surface of the substrate; etching a pattern in the masking layer; and depositing the dielectric material in an area of the pattern in the masking layer.