Patent ID: 6677676
Filing Date: 2004-01-13
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; an embedded insulation film formed on one main surface of said semiconductor substrate; an integrated circuit fabricated in a first region on the surface of said embedded insulation film; an interlayer insulation film formed on said embedded insulation film so as to cover said integrated circuit; a wiring layer formed in said interlayer insulation film and supplying steady potential; a contact extending from said wiring layer to said semiconductor substrate by penetrating through a portion, outside the first region and on the surface of said embedded insulating film, said contact establishing electrical connection between said wiring layer and said semiconductor substrate; a plurality of electrode pads which are located outside the first region on the surface of said embedded insulation film and are arranged in a predetermined direction; a plurality of buffer circuits which are formed in a region between said plurality of electrode pads and the first region and arranged in said predetermined direction in such a way as to oppose the respective electrode pads; and a potential supply pad which is formed on the interlayer insulation film so as to be located outside the first region on the surface of said embedded insulation film and receives steady potential, wherein said potential supply pad is arranged in said predetermined direction together with said plurality of electrode pads, said wiring layer includes an opposing portion opposite to one of said plurality of buffer circuits arranged in said predetermined direction and said wiring layer connects said potential supply pad to said integrated circuit, and said contact is formed below the opposing portion of said wiring layer.