Patent ID: 7495588
Filing Date: 2009-02-24
Classification: H03M

Abstract:
1. A decoding apparatus for executing arithmetic decoding of input coded data by using a state variable representing a state of arithmetic decoding processing and a context variable representing a probability state of a symbol, comprising: a first memory unit which holds a first context variable; a second memory unit which holds a first state variable; a state variable calculation unit which calculates a second state variable based on the first context variable and the first state variable and determines a selection signal representing a symbol as a result of arithmetic decoding processing; a context variable calculation unit which calculates a second context variable based on the first context variable and the selection signal and updates contents of said first memory unit by the second context variable; and a re-normalization unit which calculates a third state variable by using the coded data and the second state variable and updates contents of said second memory unit by the third state variable, wherein the selection signal determined by said state variable calculation unit is used in processing of a succeeding stage without waiting for operations of said context variable calculation unit and said re-normalization unit.