Patent ID: 7622766
Filing Date: 2009-11-24
Classification: B82Y,G11C,H01L

Abstract:
1. A semiconductor memory device, comprising: a memory cell array having first memory cells, second memory cells, third memory cells and fourth memory cells; a first word line (W a second word line (W a third word line (W a fourth word line (W a first contact region where the first contact and the second contact are disposed; a second contact region where the third contact and the fourth contact are disposed; a first contact connected the first word line in the first contact region; a second contact connected the second word line in the first contact region; a third contact connected to the third word line in the second contact region; and a fourth contact connected to the fourth word line in the second contact region; wherein the memory cell array is disposed between the first contact region and the second contact region, wherein a distance from the first contact to the memory cell array in the first direction is different from that from the second contact to the memory cell array in the first direction, and wherein a distance from the third contact to the memory cell array in the first direction is different from that from the third contact to the memory cell array in the first direction.