Patent ID: 7577850
Filing Date: 2009-08-18
Classification: G06F

Abstract:
1. A method in a security application of a circuit, comprising the steps of: (A) generating said first identification value based on a plurality of semiconductor fabrication process variations; (B) generating a key by mapping a plurality of value variations of said first identification value into a single value to reduce a bit error rate of said first identification value, wherein said key is not available external to said security application; (C) generating an output signal of said circuit by one of (i) encoding and (ii) decoding an input signal in response to said key; (D) generating a second identification value (i) based on a second plurality of said semiconductor fabrication process variations and (ii) independent of said first identification value; (F) generate a tracking value by reducing a bit error rate of said second identification value while a control signal is deasserted; (F) presenting said tracking value external to said circuit while said control signal is said deasserted; and (G) presenting said key to said one of (i) said encoding and (ii) said decoding while said control signal is asserted.