Patent ID: 9178061
Filing Date: 2015-11-03
Classification: H01L

Abstract:
1. A method for fabricating a semiconductor device, the method comprising: providing a semiconductor-on-insulator substrate including a buried insulator layer; forming a semiconductor layer overlying the semiconductor-on-insulator substrate, the semiconductor layer being doped with a dopant of a first conductivity type; forming a gate structure located on the semiconductor layer, the gate structure comprising a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer, the gate structure including a first gate portion extending in a first direction, and a second gate portion extending from the first gate portion in a second direction, which is perpendicular to the first direction; forming a source extension region and a drain extension region in the semiconductor layer on opposite sides of the second gate portion of the gate structure, the source extension region and the drain extension region extending under the gate dielectric layer and the gate conductor layer, the source extension region and the drain extension region contacting the gate dielectric layer of the second gate portion, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type; after forming the source extension region and the drain extension region, forming a mask comprising a first open region, a second open region, and a blocking region, the first open region exposing a first portion of the semiconductor layer, the first portion of the semiconductor layer being located at an end of the semiconductor layer that is closest to the first gate portion of the gate structure, the second open region exposing a second portion of the semiconductor layer comprising the entire drain extension region, the blocking region being formed over and blocking a third portion of the semiconductor layer, the third portion of the semiconductor layer being located at an end of the semiconductor layer that is furthest from the first gate portion of the gate structure; after forming the mask, forming a deep drain region in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer; after forming the mask, forming a deep source region in the first portion of the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the mask preventing a deep source region from being formed within the third portion of the semiconductor layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type; after forming the deep drain region and the deep source region, removing the mask; forming a drain metal-semiconductor alloy contact located on an upper portion of the deep drain region and abutting the drain extension region; and forming a source metal-semiconductor alloy contact abutting the source extension region, wherein the deep source region is formed below and contacts a first portion of the source metal-semiconductor alloy contact, the deep source region is formed such that it is not located below and does not contact a second portion of the source metal-semiconductor alloy contact, the second portion of the source metal-semiconductor alloy contact being formed in the third portion of the semiconductor layer and located above and directly contacting a body portion of the semiconductor layer to form an internal body contact, the second portion of the source metal-semiconductor alloy contact is located at an end of the source metal-semiconductor alloy contact that is furthest from the first gate portion of the gate structure, a sidewall of the source extension region directly contacts both a sidewall of the second portion of the source metal-semiconductor alloy contact that is located above the body portion of the semiconductor layer, and a sidewall of the first portion of the source metal-semiconductor alloy contact that is located above the deep source region, and a doping concentration of the body portion of the semiconductor layer that directly contacts the second portion of the source metal-semiconductor alloy contact is the same as a doping concentration of the body portion of the semiconductor layer that directly contacts the second gate portion of the gate structure.