Patent ID: 7793072
Filing Date: 2010-09-07
Classification: G06F

Abstract:
1. A microprocessor, comprising: a vector unit to execute a vector instruction to perform a first operation on a first set of three operands and a second operation on a second set of three operands, said vector unit configured with three inputs, one for each of the three operands, which are received at the vector unit at approximately a same time; a vector register file having a primary register file and a secondary register file, each having a first register, a second register and a third register with the operands provided therein; a plurality of multiplexers each receiving a different first input from the primary register file and a different second input from the secondary register file, wherein the plurality of multiplexers select a single one of the first input and the second input as an output that is provided to one of two arithmetic units; wherein the vector instruction includes a first register field indicative of a first primary register in the primary register file and a first secondary register in the secondary register file, a second register field indicative of a second primary register in the primary register file and a second secondary register in the secondary register file, and a third register field indicative of a third primary register in the primary register file and a third secondary register in the secondary register file; and wherein the first set of operands includes a first operand selected from the first primary register or the first secondary register, a second operand selected from the second primary register or the second secondary register, and a third operand selected from the third primary register or the third secondary register, wherein the selection of the operands occurs at approximately a same time to provide an input of the three operands to the vector unit via the three inputs.