Patent ID: 6111426
Filing Date: 2000-08-29
Classification: G11C,H03K

Abstract:
An output buffer circuit for logic signals producing an output logic signal from an input logic signal, said output buffer circuit comprising:an input stage including a storage circuit capable of storing the logic state of the input signal when an updating command signal is received,an output stage to produce the output signal as a function of the logic state stored in the storage circuit, anda control circuit providing a first control signal to the input stage to control storage of the input signal, and a second control signal to the output stage to control outputting of the output signal, the control circuit being connected to receive the input signal and the output signal, the control circuit including a comparison circuit receiving the input signal and the output signal and outputting the first control signal when the input signal and the output signal have different states, the control circuit including a comparison delay circuit which delays output of the first control signal until a predetermined time after receipt of an input signal.