Patent ID: 7437137
Filing Date: 2008-10-14
Classification: H03K,H03L,H04L

Abstract:
1. A mixer control subcircuit, comprising: first and second power supply terminals; ADVANCE, DELAY, and /ADJUST digital state control terminals; BIASNLAG and BIASNLEAD analog state control terminals; a BIASN state output terminal; a BIASP node; a BIAS a first switched current-source comprising a first dual-gate transistor having a drain coupled to the BIASP node, a first gate coupled to the BIAS a second switched current-source comprising a second dual-gate transistor having a drain coupled to the BIASP node, a first gate coupled to the BIASNLEAD analog state control terminal, a second gate coupled to the DELAY digital state control terminal, and a source coupled to the first power supply terminal; a third switched current-source comprising a third dual-gate transistor having a drain coupled to the BIASP node, a first gate coupled to the BIASNLAG analog state control terminal, a second gate coupled to the ADVANCE digital state control terminal, and a source coupled to the first power supply terminal; a first transistor having a drain coupled to the BIASN state output terminal, a gate coupled to the BIASP node, and a source coupled to the second power supply terminal; a second transistor having a gate and a drain coupled to the BIASN state output terminal, and a source coupled to the first power supply terminal; and a third transistor having a drain coupled to the BIAS