Patent ID: 8258570
Filing Date: 2012-09-04
Classification: H01L

Abstract:
1. A semiconductor device comprising: a substrate; a first insulator formed in a first area of the substrate, and a second insulator formed in a second area of the substrate; a first transistor formed over a first device region surrounded by the first area, the first transistor comprising a second transistor formed over a second device region surrounded by the second area, the second transistor comprising a third insulator formed in a third area of the substrate; and a memory cell formed over a third device region surrounded by the third area, the memory cell further comprising wherein a first height of a top surface of the first insulator is less than a second height of a top surface of the second insulator, and wherein the first height of the top surface of the first insulator is less than a third height of a top surface of the third insulator.