Patent ID: 8349681
Filing Date: 2013-01-08
Classification: H01L

Abstract:
1. A monolithic three dimensional NAND string, comprising: a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; an interlevel insulating layer located between the first control gate electrode and the second control gate electrode; a blocking dielectric, the blocking dielectric comprising a plurality of blocking dielectric segments, wherein each of the plurality of blocking dielectric segments is located in contact with a respective one of the plurality of control gate electrodes; a plurality of discrete charge storage segments, wherein each of the plurality of discrete charge storage segments is located at least partially in contact with a respective blocking dielectric segment, and wherein the plurality of discrete charge storage segments comprise at least a first discrete charge storage segment located in the first device level and a second discrete charge storage segment located in the second device level; a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel; and at least a first conductive or semiconductor shielding wing located between the first discrete charge storage segment and the second discrete charge storage segment.