Patent ID: 7213183
Filing Date: 2007-05-01
Classification: G01R,G06F

Abstract:
1. An integrated circuit, comprising: a first function block having a control input; a second function block having a control input; a first multiplexer having an output operably coupled to the control input of the first function block, a data input, a test input, and a changeover input for switching between a normal mode of operation and a test mode of operation in the first function block; a second multiplexer having an output operably coupled to the control input of the second function block, a data input, a test input, and a changeover input for switching between a normal mode of operation and a test mode of operation in the second function block, a first test register having a serial data input connected to a serial bus, and an output coupled to the test input of the first multiplexer; a second test register having a serial data input connected to the serial bus, and an output coupled to the test input of the second multiplexer; and a control unit configured to couple the first test register and the second test register to the changeover inputs of the first and second multiplexers, respectively, for transferring data from the first test register to the control input of the first function block, and for transferring data from the second test register to the control input of the second function block based on a state of a mode-of-operation memory cell in the respective test register.