Patent ID: 6327187
Filing Date: 2001-12-04
Classification: G11C,H01L

Abstract:
A method for programming a memory cell formed in a semiconductor material of a first conductivity type, the memory cell comprising:a source region of a second conductivity type formed in the material;a drain region of the second conductivity type formed in the material;a channel region defined in the material between the source and drain regions, the channel region having a first region, a second region, and a third region;an isolation layer formed on the semiconductor material over the channel region, the isolation layer having a material with substantially more electron traps than hole traps;a first gate formed on the isolation layer over the first channel region;an isolation region formed on the isolation layer over the second channel region; anda second gate formed on the isolation layer over the third channel region;the method comprising the steps of:applying a programming voltage to the first gate;applying an intermediate voltage to the drain region;applying ground to the source region;applying a low positive voltage to the second gate; andapplying ground to the semiconductor material.