Patent ID: 6684284
Filing Date: 2004-01-27
Classification: G06F

Abstract:
A control chipset, comprising:a bus; a first control chip, comprising: a first data transceiver, coupled to the bus for receiving and transmitting data signals to complete read/write transactions; a read/write data queue, coupling to the first data transceiver for temporally storing data of the read/write transactions; a read/write transaction queue, coupling to the first data transceiver for temporally storing data lengths and addresses of data of the read/write transactions; a target controller, coupling to the read/write data queue and the read/write transaction queue, wherein the target controller send data to a target device according to read/write addresses stored in the read/write transaction queue and data stored in the read/write data queue corresponding to the first stored read/write transaction; then the first data transceiver asserts a read/write acknowledge signal; and the read/write addresses and the read/write data queue corresponding to the read/write addresses are released; and a second control chip, coupled to the bus, comprising: a read/write buffer size register, for memorizing a maximum number of data allowed in the read/write data queue; a read/write buffer counting register, for memorizing a maximum number of transactions allowed in the read/write transaction queue; a second data transceiver, coupling to the bus for receiving and transmitting data signals through the bus to complete the read/write transactions, and asserting a releasing buffer signal when receiving the read/write acknowledge signal; a read/write transaction generator, coupling to the second data transceiver for generating data length of the read/write transactions, the read/write addresses and data; a read/write recording circuit, coupling to the second data transceiver and the read/write transaction generator, for temporally storing data length of the read/write transactions, and calculating an usable data number of the read/write data queue and an allowable transaction number in the read/write transaction queue according to the releasing buffer signal; and a read/write comparator, coupling to the second data transceiver, the read/write buffer size register, the read/write buffer counting register and the read/write recording queue circuit, for informing the second data transceiver of data corresponding to a next read/write transaction.