Patent ID: 6649956
Filing Date: 2003-11-18
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising a semiconductor substrate having a surface and an array of memory cells each including a serial combination of a cell selecting transistor and a data storage capacitive element with first and second electrodes as insulatively laminated over each other, the cell selecting transistor including a metal insulator semiconductor field effect transistor (MISFET) having a source, a drain, and a gate electrode, comprising:at least first, second and third word lines arranged on the surface of the substrate in a first direction, the first word line being disposed between the second and third word lines, and each word line having a part forming the gate electrode of the memory cell selecting MISFET; and at least first and second bit lines arranged on the surface of the substrate in a second direction transverse to the first direction, wherein: a gap between the first and second word lines is equal a gap between the first and third word lines at a portion between the first and second bit lines; a width of the first, second and third word lines is larger than the gap between the first and second word lines at a portion between the first and second bit lines; and a width of the first and second bit lines is less than the gap between the first and second bit lines.