Patent ID: 7129881
Filing Date: 2006-10-31
Classification: H03M

Abstract:
1. A pipeline analog-to-digital converter comprising a number of comparator stages operating in accordance with a clock signal, each of said comparator stages comprising a comparator for comparing an input signal with a respective threshold signal and at least some of said comparator stages comprising a subtracter for generating a residue signal; the comparator stages being connected in series in such a way that the residue signal from a previous stage is used as input signal of a subsequent stage for comparison during the next clock period of the clock signal; wherein at least some of said comparator stages comprise a threshold generator for adjusting the threshold value of the related comparator in accordance with comparison results of previous comparator stages, and a programmable gain amplifier for amplifying the residue signal from the related stage in accordance with the comparison results of previous comparator stages.