Patent ID: 8103991
Filing Date: 2012-01-24
Classification: G06F

Abstract:
1. A method of designing a semiconductor integrated circuit, comprising: generating, by an arithmetic unit, electrical filter graphic data indicating a candidate portion for which a dimensional value of a layout pattern is permitted to deviate from a design value by taking account of an electrical characteristic, and electrical filter data indicating a permissible dimensional value in the candidate portion of the layout pattern by taking account of the electrical characteristic, by using circuit diagram data, a static timing analytical result obtained by verifying a timing of a circuit operation, and a result of a circuit simulation, and storing the electrical filter graphic data and the electrical filter data in a storage unit; generating, by the arithmetic unit, design data by using the electrical filter graphic data, and forming the layout pattern by using the design data; detecting, by the arithmetic unit, a lithography error by performing a lithography simulation on the layout pattern; determining, by the arithmetic unit, using the electrical filter database, whether the lithography error requires correction by taking account of the electrical characteristic; correcting, by the arithmetic unit, the layout pattern in response to determining that the lithography error requires correction; and outputting, by an output unit, a result of the correcting.