Patent ID: 6818509
Filing Date: 2004-11-16
Classification: H01L

Abstract:
A method of fabricating an electrically erasable programmable read only memory (EEPROM) comprising the steps of:forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer; sequentially forming a first conductive layer, an interlevel insulating layer and a second conductive layer on the tunnel insulating layer and on the gate insulating layer; patterning the second conductive layer, the interlevel insulating layer an the first conductive layer to define a sense transistor gate on the tunnel insulating layer and on the gate insulating layer, the sense transistor gate comprising a first portion of the first conductive layer, a first portion of the interlevel insulating layer and a first portion of the second conductive layer, and to further define a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, the select transistor gate comprising a second portion of the first conductive layer, a second portion of the interlevel insulating layer and a second portion of the second conductive layer; and simultaneously forming second, third and fourth doped regions in the integrated circuit substrate using the sense transistor gate and the select transistor gate as a mask, the second, third and fourth doped regions being spaced apart from each other, the second doped region extending from beneath the sense transistor gate to outside the sense transistor gate, the third doped region extending from beneath the select transistor gate to outside the select transistor gate, and the fourth doped region extending from the first doped region to beneath a select gate electrode of the select transistor gate simultaneously forming a fifth doped region within the second doped region outside the sense transistor gate and a sixth doped region within the third doped region outside the select transistor gate, using a photoresist pattern as a mask extending from outside the sense transistor gate to outside the select transistor gate.