Patent ID: 7689950
Filing Date: 2010-03-30
Classification: G01R,G11C

Abstract:
1. A design structure tangibly embodied in a computer-readable storage medium for designing, manufacturing, or testing a design, the design structure comprising: a testing circuit tangibly embodied in the computer-readable storage medium used in the design process, said testing circuit for testing a sense amplifier for an eFuse to determine whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse; said testing circuit including a sense amplifier signal control providing a first precharge signal applied to a first precharge device of the sense amplifier; said sense amplifier signal control providing a second precharge signal applied to a second precharge device of the sense amplifier; and said sense amplifier signal control selectively controlling said first and second precharge devices for providing a respective output resulting from both an unblown and a blown eFuse of the sense amplifier with the eFuse being unblown, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said testing circuit.