Patent ID: 8874999
Filing Date: 2014-10-28
Classification: H03L

Abstract:
1. An apparatus, comprising: a detector configured for at least one of phase or frequency detection and coupled to receive a first input signal and a second input signal to compare pulses of the first input signal and the second input signal against one another to provide a first error signal and a second error signal respectively representing a positive difference and a negative difference in phase or frequency between the first input signal and the second input signal; a pulse width determination block to receive the first error signal, the second error signal and a digital oscillating signal to output a first pulse width value and a second pulse width value respectively associated with the first error signal and the second error signal; a pulse width accumulator to accumulate the first pulse width value and the second pulse width value over a number of cycles of the digital oscillating signal to provide a first accumulated value and a second accumulated value over the number of cycles; and an error generator to provide an error value as a difference between the first accumulated value and the second accumulated value; wherein the error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.