Patent ID: 8451395
Filing Date: 2013-05-28
Classification: G02F,H01L

Abstract:
1. A thin-film transistor array substrate including a thin-film transistor, comprising: a gate line that is formed over a substrate and connected to a gate electrode of the thin-film transistor; a gate insulating layer that covers the gate electrode and the gate line; a source line that is formed above the gate insulating layer and connected to a source electrode of the thin-film transistor; a semiconductor layer that is formed on the gate insulating layer and placed in a substantially whole area below a drain electrode of the thin-film transistor, in a substantially whole area below the source electrode, in a substantially whole area below the source line and in a position opposite to the gate electrode; a pixel electrode that is formed directly on the drain electrode and electrically connected to the drain electrode; a transparent conductive pattern that is formed directly on the source electrode and the source line in the same layer as the pixel electrode; an interlayer insulating layer that covers the pixel electrode and the transparent conductive pattern; and a counter electrode that is formed on the interlayer insulating layer and generates a fringe electric field with the pixel electrode, wherein the pixel electrode and the transparent conductive pattern are placed on an inside of a pattern of the semiconductor layer when viewed from above in a position opposite to the gate electrode.