Patent ID: 7019355
Filing Date: 2006-03-28
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory, comprising: a plurality of memory cell columns, each of the memory cell column including a plurality of memory cell transistors, each having a floating gate, a control gate, and an inter-gate insulating film, the inter-gate insulating film is arranged between the floating gate and the control gate, the memory cell columns are arranged along a row direction; and a plurality of device isolation regions arranged at a constant pitch along the row direction, each of the device isolation regions is implemented by a striped pattern extending along the column direction, wherein the control gate is shared by the memory cell transistors arranged along the row direction, and the inter-gate insulating film is shared by the memory cell transistors arranged along the column direction and is separated from an adjacent inter-gate insulating film by one of the device isolation films.