Patent ID: 6017793
Filing Date: 2000-01-25
Classification: H01L

Abstract:
A method of forming non-volatile semiconductor memory device, whereinin a non-volatile semiconductor memory device of MOSFET configuration having a source and drain formed from a diffused impurity layer buried below an element-isolation oxide film and two-layer gate construction that includes a floating gate and a control gate;said method is a method of forming a memory cell from a data memory section having said two-layer gate construction and series select transistors formed between said control gate connected to said data memory section and exposed side wall portions of a semi-conductor substrate; the method comprising the steps of:processing by dry etching using photoresist a polycrystalline semiconductor film forming said floating gate and an underlying gate oxide film;forming said diffused impurity layer by cutting into said semiconductor substrate to a prescribed depth by dry etching and exposing side walls of said semiconductor substrate, followed by ion injection of impurities into said semiconductor substrate;forming an insulation film covering said diffused impurity layer, exposed side walls of said semiconductor substrate, said gate oxide film, said floating gate and a top surface of said floating gate; andforming a control gate polycrystalline film over and in contact with said insulation film;wherein impurities making up said diffused impurity layer are ion injected into said semiconductor substrate at an oblique angle to form said diffused impurity layer in the surface of said side wall at only one side of said floating gate, whereby one memory cell is formed that is constructed from one data memory section having two-layer gate construction that includes a floating gate and a control gate and one select transistor formed at said exposed side wall portions of said semiconductor substrate.