Patent ID: 7926016
Filing Date: 2011-04-12
Classification: G06F

Abstract:
1. A method of configuring a logic block of an integrated circuit during physical implementation of a circuit design, said method comprising: measuring slack for a port of the logic block, wherein the port is selectively registered, wherein the logic block comprises dedicated circuitry that performs a particular function, and wherein the logic block comprises at least one register that is selectively bypassed to facilitate selective registering of the port; identifying a first location of a register associated with the port as internal, wherein the register is implemented as the at least one register that is selectively bypassed, or external with respect to the logic block, wherein the register is implemented within fabric of the integrated circuit and the at least one register of the port is bypassed; moving, via a computer, the register associated with the port to a second location according to a relocation technique, wherein the second location is internal or external with respect to the logic block and different than the first location; determining whether slack for the port improves when the register associated with the port is moved to the second location as compared to the first location; and if the slack for the port improves when the register associated with the port is moved to the second location, accepting the second location of the register.