Patent ID: 6150228
Filing Date: 2000-11-21
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory device that has a plurality of static type memory cells which include two MOS driver transistors, which are formed on a semiconductor substrate, two MOS transfer transistors and two load elements, which are connected to the drains of said two MOS driver transistors, and a power supply line, which supplies a power supply voltage, said manufacturing method comprising steps of:(a) forming a field insulation layer onto the surface of said semiconductor substrate and then forming a gate insulation layer;(b) forming a first conductive layer and then etching a prescribed region so as to form said MOS driver transistors and said MOS transfer transistors;(c) forming a first interlayer insulation layer;(d) forming a second conductive layer and a silicon nitride layer over said first interlayer insulating layer and then etching said second conductive layer and said silicon nitride layer in a prescribed shape;(e) forming a second interlayer insulation layer thereover;(f) etching said second interlayer insulation layer over said silicon nitride layer to form a trench therein and etching said first and second interlayer insulation layers over a node portion; and(g) forming a third conductive layer and patterning a prescribed shape thereonto.