Patent ID: 6304500
Filing Date: 2001-10-16
Classification: G11C

Abstract:
An integrated circuit memory device comprising:a normal memory cell block including first and second normal columns;a redundancy memory cell block including a redundancy column;first and second normal data input and output lines that input data to and output data from the first and second normal columns, respectively;redundancy data input and output lines that input data to and output data from the redundancy column;first and second data transfer lines that input data to and output data from a memory cell;a first switch that connects the first data transfer line to the first normal data input and output line during a normal operation and that connects the first data transfer line to the redundancy data input and output lines during a redundancy operation; anda second switch that connects the second data transfer line to the second normal data input and output line during a normal operation and that connects the second data transfer line to the first normal data input and output line during the redundancy operation.