Patent ID: 7117458
Filing Date: 2006-10-03
Classification: G01R,G06F

Abstract:
1. A method for identifying netlist gates with specified functionality in a circuit design for use by a code coverage tool, said method comprising: limiting a search to gates with output which meets an intended criteria, creating and applying design elements to a smaller netlist in a synthesis tool to add one exclusive-nor gate (XNOR) into the smaller netlist for each an output signal which meets said intended criteria in a target signal set, and tying one input of said one XNOR to said output signal, tying an other input of said one XNOR to a new input added to the circuit design wherein there is one such new input for entire circuit design, and all said one XNORs are tied to this one such new input, tying the output of each said one XNOR to a new XNOR output signal created in the circuit design, wherein there is one said new XNOR output signal for each XNOR, identifying the new XNOR output signals by common prefix and a unique number for each XNOR, creating a VHDL netlist, bringing up said VHDL netlist in an event based simulator, running an event-based simulator repeatedly until all entries on a truth table for a specified function are filled, analyzing said new XNOR output signals from all said one XNORs to determine which of the said one XNOR gates have said specified function.