Patent ID: 6072944
Filing Date: 2000-06-06
Classification: G06F

Abstract:
A method for rapid development of ASIC chips utilizing distributed processing architecture comprising:a) designing a system of discrete components including a first host processor and at least one object oriented processor;b) providing a high level command language for communication between the first host processor and the at least one object oriented processor;c) coupling the first host processor to the at least one object oriented processor with a communications bus;d) programming the host processor with the high level command language to define a functionality of the system embodied as a first program;e) testing and debugging the system of discrete components;f) replicating the functionality of the at least one object oriented processor on an ASIC chip having an on-chip bus to which the replicated functionality is coupled;g) coupling one of the first host processor and a second host processor to the on-chip bus; andh) programming the host processor coupled to the on-chip bus with the first program.