Patent ID: 6285620
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A semiconductor device to repair failed memory cells by programming fuse memory cells, comprising:an address buffer, to receive an address information;a main memory array, comprising a plurality of main memory cells and coupled to the address buffer, so as to output a main memory cell address corresponding to the address information;a built-in self-test unit, storing an original address information of the main memory cells in the main memory cell array, and to output the original address information of the main memory cell corresponding to the address information;a data comparator, coupled to the main memory cell array and the built-in self-test unit to receive and compare the main memory cell address information and the original address information, and outputting an error address information when the main memory cell address information is not identical to the original address information;a fuse memory cell array, comprising a plurality of fuse memory cell array;an address programmer, to receive a voltage source and coupled to the address buffer and the data comparator, outputting a repair address information to the fuse memory cell array according to the address information and the error address information, so as to program the fuse memory cell corresponding to the repair address information; anda latch, coupled to the fuse memory cell array to latch the repair address information from the fuse memory cell array, and to output the repair address information to the main memory cell array to repair a corresponding failed memory cell in the main memory cell array.