Patent ID: 6400606
Filing Date: 2002-06-04
Classification: G11C

Abstract:
A sense amplifier circuit for a nonvolatile semiconductor memory device comprising:a memory cell transistor which has a drain coupled to a data line, a source coupled to a ground voltage, a floating gate, and a control gate coupled to a word line; a first PMOS transistor which has a source coupled to a power supply voltage, and a drain and a gate commonly coupled to the data line; a reference cell transistor which has a drain coupled to a reference line, a source coupled to the ground voltage, a floating gate, and a control gate coupled to a reference word line; a second PMOS transistor which has a source coupled to the power supply voltage, and a drain and a gate commonly coupled to the reference line; an NMOS transistor which has a drain coupled to the reference line, a gate coupled to a switch control signal, and a source; a resistor which has one end coupled to the source of the NMOS transistor and the other end coupled to the ground voltage; and a differential amplifier which has one input coupled to the data line, the other input coupled to the reference line, and an output for outputting either a high level or a low level according to potentials on the data line and the reference line.