Patent ID: 6046725
Filing Date: 2000-04-04
Classification: G09G

Abstract:
A dither circuit for reproducing multicolor data comprising:a latch for receiving 8 input data bits representing all R, G, B color information and a clock signal, and for separating the 8 input data bits into high 7 bits and a low bit;a frame rate generator for receiving a horizontal sync signal, a vertical sync signal and a clock signal, and for generating a frame rate bit, wherein the frame rate bit is toggled according to each cycle of the vertical sync signal;a frame rate controller for receiving the low bit from the latch and the frame rate bit from the frame rate generator, and for generating a frame data; andan adder for receiving the frame data from the frame rate controller and the high 7 bits from the latch, and for generating 7 output data bits.