Patent ID: 7089465
Filing Date: 2006-08-08
Classification: G11C

Abstract:
1. A multi-port memory device comprising a plurality of ports supporting a serial I/O interface, the plurality of ports including a transmission pad and a reception pad, the multi-port memory device comprising: a memory core; a control means for generating an internal command signal, an internal address and a control signal, which correspond to the command and are necessary for an operation of the memory core, using commands and addresses inputted to the plurality of ports in a packet form; and a mode selection means for combining signals applied to a plurality of mode selection pads and generating a test mode flag signal, wherein I/O data assigned to the transmission pad and the reception pad in a test mode in response to the test mode flag signal are exchanged with the memory core through the ports, and the command, the address and the control signal assigned to the transmission pad and the reception pad in the test mode are bypassed at the control means and provided to the memory core.