Patent ID: 8294653
Filing Date: 2012-10-23
Classification: G09G

Abstract:
1. A driving voltage output circuit having a plurality of high-side voltage followers and a plurality of low-side voltage followers, the high-side voltage followers outputting driving voltages equal to or greater than a reference potential and equal to or less than a high-side power supply potential, the low-side voltage followers outputting driving voltages equal to or greater than a low-side power supply potential and equal to or less than the reference potential, the driving voltages being supplied to column lines in a matrix display panel responsive to display data, each column line being periodically switched between receiving a driving voltage from one of the high-side voltage followers and receiving a driving voltage from one of the low-side voltage followers, each of the high-side voltage followers and each of the low-side voltage followers separately comprising: a differential input stage having an inverting input terminal, a non-inverting input terminal, a first transistor with a control terminal connected to the non-inverting input terminal, a second transistor with a control terminal connected to the inverting input terminal, and a first current mirror connected to controlled terminals of the first and second transistors to supply the second transistor with a current equal to a current conducted by the first transistor, the first and second transistors operating as a differential amplifier to generate a first potential at a node at which the first transistor and the first current mirror are interconnected and a second potential at a node at which the second transistor and the first current mirror are interconnected; a control stage including a potential generating circuit for generating a third potential responsive to a difference between the first potential and the second potential, a third transistor (MP an output stage including a first terminal, a second terminal, a third terminal, an output terminal connected to the inverting input terminal of the input stage and to one of the column lines, a fourth transistor with a control terminal receiving the first potential, a controlled terminal connected to the first terminal, and another controlled terminal connected to the output terminal, a fifth transistor with a control terminal receiving the fourth potential, a controlled terminal connected to the second terminal, and another controlled terminal connected to the output terminal, and a sixth transistor with a control terminal receiving the third potential, a controlled terminal connected to the third terminal, and another controlled terminal connected to the output terminal, the fourth and fifth transistors being of mutually identical channel types, the fourth and sixth transistors being of mutually opposite channel types, the second terminal supplying the reference potential; wherein in the high-side voltage followers the first terminal supplies the high-side power supply potential and the third terminal supplies the low-side power supply potential; and in the low-side voltage followers the first terminal supplies the low-side power supply potential and the third terminal supplies the high-side power supply potential.