Patent ID: 8017986
Filing Date: 2011-09-13
Classification: G11C,H01L

Abstract:
1. A semiconductor device comprising: a plurality of nonvolatile memory cells, each including wherein the first transistor section and the second transistor section are formed with an insulating region between gate electrodes thereof and adjacent to each other, wherein a channel region connected to channel regions of the first transistor section and the second transistor section is disposed below the insulating region, wherein the second transistor section has a bit line electrode connected to a bit line, and a control gate electrode connected to a control gate control line, wherein the first transistor section has a source line electrode connected to a source line, a memory gate electrode connected to a memory gate control line, and a charge storage region disposed directly below the memory gate electrode, wherein a gate insulating film of the second transistor section is lower than a gate insulating film of the first transistor section, and wherein a gate insulating film of a drive MOS transistor connected to the control gate control line is lower than a gate insulating film of the first transistor section.