Patent ID: 7683375
Filing Date: 2010-03-23
Classification: G02F,H01L

Abstract:
1. A thin-film transistor comprising: a gate layer, a gate insulating layer, a semiconductor layer, a drain layer, and a passivation layer that are formed one of on an insulating substrate and over said insulating substrate; and a conductive layer formed on the passivation layer, the conductive layer being connected to one of the gate layer and the drain layer by way of a contact hole penetrating at least the passivation layer, wherein the passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having an etch rate lower than an etch rate of the second sublayer, wherein the first sublayer is disposed closer to the insulating substrate than the second sublayer, wherein the second sublayer has a thickness equal to or less than a thickness of the conductive layer, wherein the passivation layer comprises silicon nitride (SiN), and wherein a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the second sublayer of the passivation layer comprising SiN is equal to or greater than 2.3 times as much as a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the first sublayer.