Patent ID: 6720618
Filing Date: 2004-04-13
Classification: H01L

Abstract:
A power MOSFET device comprising:a low resistance substrate of the first conductivity type; a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate; a base layer of the second conductivity type formed in a surface region of said high resistance epitaxial layer; a source region of the first conductivity type formed in a surface region of the base layer; an LDD layer of the first conductivity type formed in a surface region of said high resistance epitaxial layer at a position separated from said base layer by a predetermined distance; a gate insulating film formed to bridge said source region and an end of said LDD layer; a gate electrode formed on said gate insulating film; a sinker layer of the first conductivity type formed between the other end of said LDD layer and said low resistance substrate; and an extension layer of the second conductivity type formed between the lateral side of said base layer facing said LDD layer and being at least held in contact with said base layer.