Patent ID: 6775816
Filing Date: 2004-08-10
Classification: H01L

Abstract:
A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising:a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of said critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of said chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of said yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which selects a combination of the function blocks constituting the chip based on the information relating to the fabrication cost and the delivery time of the chip calculated by said cost delivery time information calculator.