Patent ID: 6504499
Filing Date: 2003-01-07
Classification: H03M

Abstract:
An analog-to-digital comprising:a resistor ladder comprising a plurality of resistors coupled in series; a differential analog data input having first and second analog data terminals; a plurality of comparators having one or more pairs of comparators that each include a first comparator and a second comparator, the first and second comparators having first and second analog data inputs, two reference voltage inputs, and an output, the second comparator having an inverted output, the first analog data input of each first comparator being coupled to the first analog data terminal and the corresponding first analog data input of each second comparator being coupled to the second analog data terminal, and the two reference voltage inputs being coupled to the resistor ladder such that the two reference voltage inputs of each comparator include a positive reference voltage input and a negative reference voltage input; and an encoder, coupled to the outputs of all of the plurality of comparators, that encodes signals at the outputs of the plurality of comparators into a digital signal, wherein for each and every comparator having an output coupled to the encoder, the positive reference voltage input is coupled to a point on the resistor ladder of relatively higher potential than its negative reference voltage input.