Patent ID: 6012120
Filing Date: 2000-01-04
Classification: G06F

Abstract:
A method for providing communication between a first external device coupled to a first external PCI bus and a second external device coupled to a second PCI bus, said first and second external PCI busses coupled to a multiprocessor computer system bus by a first PCI bridge device and a second PCI bridge device, respectively, said method comprising the steps of:forwarding a PCI address and an associated command to said first PCI bridge device;capturing said PCI address in a command and address path circuit included in said first PCI bridge device;comparing, by said command and address path circuit, said PCI address with a range of addresses to determine whether said PCI address should be mapped to a corresponding multiprocessor computer system bus address;determining, in response to a determination by said comparing step that said PCI address should be mapped, whether said PCI address should be mapped to said multiprocessor computer system bus address in a direct manner or in a scatter-gather manner;mapping said PCI address, by said first PCI bridge device, into said multiprocessor computer system bus address;issuing, by said first PCI bridge device, said multiprocessor computer system bus address and said associated command on said multiprocessor computer system bus;detecting, by said second PCI bridge device, said multiprocessor computer system bus address and said associated command;determining, by said second PCI bridge device, whether said multiprocessor computer system bus address corresponds to an address space associated with said second external device;translating, by said second PCI bridge device, said multiprocessor computer system bus address into said PCI address in response to a determination that said multiprocessor computer system bus address corresponds to said address space associated with said second external device; andissuing, by said second PCI bridge device, said PCI address and said associated command onto said second external PCI bus such that said first external device can communicate with said second external device.