Patent ID: 7483290
Filing Date: 2009-01-27
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device, comprising: a control circuit; an inverting circuit; and a plurality of memory units arranged in a matrix, each of the memory units including: a latch having a first node and a second node configured to be set to potentials responsive to latched data and inverse to each other; a plate line configured to be settable to a selected one of a first potential and a second potential; a first MIS transistor having one of source/drain nodes thereof coupled to the first node of the latch, another one of the source/drain nodes thereof coupled to the plate line, and a gate node thereof coupled to a word line; and a second MIS transistor having one of source/drain nodes thereof coupled to the second node of the latch, another one of the source/drain nodes thereof coupled to the plate line, and a gate node thereof coupled to the word line, wherein the control circuit is configured to perform an inverting operation that inverts the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.