Patent ID: 6831490
Filing Date: 2004-12-14
Classification: G06F

Abstract:
A clock synchronization circuit for generating an output clock signal that is substantially in synchronization with a reference clock signal when in an in-synchronizabon state with a phase difference between the two clock signals of less than a predetermined value, the clock synchronization circuit comprising:a programmable delay element coupled to the reference clock signal for introducing an adjustable delay in the reference clock signal to produce a delay-adjusted delayed output clock signal that becomes increasingly closer to being in synchronization with the reference clock signal; and a phase detector coupled to the reference clock signal and the delay-adjusted delayed output clock signal for detecting the phase difference between the two clock signals and for generating an in-synchronization signal when the in-synchronization state is reached, the phase detector comprising: a pulse generator that produces a pulse of variable width when the output clock signal approaches the in-synchronizaton state as the adjustable delay is increased; and a latch that is triggered by the pulse to generate the in-synchronization signal when the width of the pulse reaches a pulse width Z required to trigger the latch.