Patent ID: 7504686
Filing Date: 2009-03-17
Classification: H01L

Abstract:
1. A non-volatile memory cell array of conductive floating gates arranged in strings, each of the strings extends in a first direction, each string comprising at least four floating gates electrically connected in series by source/drain regions, the source/drain regions associated with a first of the strings electrically connect one floating gate to a next floating gate to form the first string, the source/drain regions of a given string are separated from the source/drain regions of adjacent strings by isolating elements, the floating gates individually comprise a first floating gate portion that has an upper surface and a lower surface both upper and lower surfaces being parallel to a surface of a substrate and a second floating gate portion that extends upward from a first region of the upper surface of the first floating gate portion, the second floating gate portion extends from the upper surface of the first floating gate portion such that a cross-section of the floating gate that is parallel to the first direction forms an inverted T shape.