Patent ID: 7330140
Filing Date: 2008-02-12
Classification: H03M

Abstract:
1. An interleaved ADC generating a plurality of digital codes representing an input signal, said interleaved ADC comprising: a plurality of converters, with each of said plurality of converters sampling said input signal at time points specified by a corresponding one of a plurality of sampling clocks to generate a subset of digital codes, wherein said plurality of sampling clocks operate at different phases, wherein each of said subset of digital codes is comprised in said plurality of digital codes, wherein a magnitude of each of said digital codes depends on a parameter value of the corresponding converter; a reference converter also sampling said input signal at time points specified by a reference clock and generating a plurality of reference values; and an estimation unit examining said plurality of reference values and said plurality of subset of digital codes generated by a first converter contained in said plurality of converters, and generating a correction factor to change said parameter value of said first converter.