Patent ID: 9223553
Filing Date: 2015-12-29
Classification: F01D,F02C,F05D,G06F,Y10T

Abstract:
1. An apparatus to validate translated guest code in a dynamic binary translator, comprising: a memory to store executable instructions that when executed by a processor causes: a translator to generate a first translation of guest code to execute on a host machine, the first translation of the guest code to facilitate creating a first translated guest code, and the translator to generate a second translation of the translated guest code to execute on the host machine; a translation versions manager to identify a first host machine state based on execution of a portion of the first translation, and the translation versions manager to identify a second host machine state based on execution of a portion of the second translation; and a validator to determine a state divergence status of the second translation based on a comparison between the first host machine state and the second host machine state; a chain optimizer to: