Patent ID: 7170432
Filing Date: 2007-01-30
Classification: H03M

Abstract:
1. An arrangement for generating addresses for interleaving/de-interleaving sequences including a given number (K) of items, the value of said given number of items (K) being within a given range of possible values, the arrangement comprising: a first memory unit having stored therein a plurality of records, each record being indicative of a respective set of interleaving/deinterleaving parameters for constructing a matrix for arranging said sequences and for affecting intra-row and inter-row permutation of said matrix to generate a permuted output matrix for generating said addresses, wherein said memory unit has a number of said records stored therein that is less than the number of values in said given range of possible values, and each said record in said memory unit is identified by a respective pointer; and a pointer retrieval circuit associated with said memory unit, said pointer retrieval circuit configured for generating for each value of said given number of items (K) in said given range a corresponding pointer pointing to a respective record in said memory unit.