Patent ID: 7035968
Filing Date: 2006-04-25
Classification: G11C,Y10S

Abstract:
1. A content addressable memory (CAM) device comprising: a first plurality of storage circuits to store an upper value; a second plurality of storage circuits to store a lower value; a plurality of compare circuits to determine if a first comparand value is within a range of values defined by the upper value and the lower value, wherein the upper value comprises a plurality of bits ordered from a most significant bit to a least significant bit, and wherein each of the plurality of compare circuits is adapted to receive a respective one of the plurality of bits and to compare the one of the plurality of bits to a respective bit within the first comparand value; and a match line, wherein a most significant compare circuit of the plurality of compare circuits is coupled to the match line, the most significant compare circuit including circuitry to affect a logical state of the match line if either (1) a most significant bit of the first comparand value is greater than the most significant bit of the upper value, or (2) the most significant bit of the first comparand is equal to the most significant bit of the upper value, and a result signal from a less significant compare circuit of the plurality of compare circuits indicates that the first comparand value minus the value represented by the most significant bit of the first comparand value is greater than the upper value minus the value represented by the most significant bit of the upper value.