Patent ID: 8368438
Filing Date: 2013-02-05
Classification: H03L

Abstract:
1. A phase locked loop circuit comprising: a selector that selects one of a plurality of clocks as an input clock; a first frequency divider that divides a frequency of the input clock; a second frequency divider that divides a frequency of a feedback clock; a phase difference detector that detects a phase difference between the clock divided by the first frequency divider and the clock divided by the second frequency divider; a first voltage controlled oscillator that comprises a first voltage holding circuit holding an input voltage according to the phase difference, the first voltage controlled oscillator generating a first intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in a normal mode, the first voltage controlled oscillator generating the first intermediate clock based on the input voltage held in the first voltage holding circuit in a holding mode; a second voltage controlled oscillator that comprises a second voltage holding circuit holding an input voltage according to the phase difference, the second voltage controlled oscillator generating a second intermediate clock based on the input voltage according to the phase difference detected by the phase difference detector in the normal mode, the second voltage controlled oscillator generating the second intermediate clock based on the input voltage held in the second voltage holding circuit in the holding mode; and a selection circuit that selects one of the first and second intermediate clocks, and outputs the selected clock as an output clock and the feedback clock, wherein the clock selected as the input clock is switched by the selector when the intermediate clock generated by the voltage controlled oscillator in the holding mode among the first and second intermediate clocks is output as the output clock and the intermediate clock generated by the voltage controlled oscillator in the normal mode is output as the feedback clock, and wherein the phase difference detector comprises: