Patent ID: 8239147
Filing Date: 2012-08-07
Classification: G01R,H04B,H04L,Y10T

Abstract:
1. A test apparatus that tests a device under test, comprising: a comparator that is electrically connected to a terminal of the device under test, and that detects a logic value of a response signal from the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the response signal occurring while the response signal travels from the terminal of the device under test to the comparator; a driver that supplies the generated correction signal to the comparator; an expected value pattern generator that generates an expected value pattern corresponding to a test pattern for testing the device under test; and a judging section that judges whether the logic value of the response signal detected by the comparator matches an expected value of the expected value pattern, wherein the correction signal generating section generates the correction signal based on the expected value pattern, the correction signal generating section generates the correction signal based on the correction pattern, which is obtained by delaying the expectation value pattern by one bit and inverting the delayed expectation value pattern, and the driver outputs the correction signal to have an amplitude smaller than an amplitude of the response signal.