Patent ID: 6455893
Filing Date: 2002-09-24
Classification: H01L

Abstract:
An MOS transistor with high voltage sustaining capability and low on-state resistance suitable for formation on a substrate with logic transistors, comprising:a substrate doped with charge carriers of the first conductivity type; drain and source regions configured in the substrate, doped with charge carriers of a second conductivity type opposed to the first conductivity type; a gate electrode arranged on the substrate in the region between the drain and the source region and comprising a drain-side end region; a drain extension region doped with charge carriers of the second conductivity type, connected with the drain region and extending below the drain-side end of the gate electrode said drain extension region being produced by an ion implantation process having at least one first implantation step, wherein the first implantation step is also used to configure active regions for logic transistors in the substrate; said drain extension region having a doping material concentration which increases with increasing depth from an upper surface of said transistor.