Patent ID: 8219731
Filing Date: 2012-07-10
Classification: G06F

Abstract:
1. A data processor comprising: a central processing unit which executes an instruction; a plurality of circuit modules used by the central processing unit; a first controller which outputs a request for interruption to the central processing unit in response to a generated event signal; and a second controller which outputs a start control signal to each circuit module in response to a generated event signal, wherein each circuit module can produce the event signal, wherein the second controller has a rewritable memory circuit, wherein the memory circuit is used to store event control information for determining a start control signal to be output in response to the event signal, wherein on receipt of a first event signal from a first one of said circuit modules, the second controller outputs a first start control signal for causing a second one of said circuit modules to perform a given operation, wherein on receipt of a second event signal produced in response to completion of a given operation from the second circuit module, the second controller outputs a second start control signal for causing a third one of said circuit modules to perform a given operation, and wherein on receipt of a third event signal produced in response to completion of a data given operation from the third circuit module, the first controller outputs the request for interruption to the central processing unit.