Patent ID: 9021237
Filing Date: 2015-04-28
Classification: G06F

Abstract:
1. A circuit arrangement, comprising: a plurality of hardware threads disposed in a plurality of processing cores, each processing core including a register file and at least one hardware thread among the plurality of hardware threads, the register file in each processing core including a plurality of local registers; and a variable transfer network coupled between the plurality of processing cores, the variable transfer network configured to communicate a variable between a source hardware thread in a source processing core among the plurality of processing cores and a destination hardware thread in a destination processing core among the plurality of processing cores; and a plurality of variable registers, each variable register allocated to an individual hardware thread among the plurality of hardware threads, wherein the variable transfer network is configured to communicate the variable to a variable register allocated to the source hardware thread in the destination processing core in response to the source hardware thread in the source processing core writing to the variable register allocated to the destination hardware thread in the source processing core.