Patent ID: 8125235
Filing Date: 2012-02-28
Classification: G01R,H03H

Abstract:
1. A test system comprising: a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer; at least one built-in self test (BIST) die formed separate from the set of DUT, the BIST die being connected to each DUT within the set through the signal buses for carrying out tests of each DUT; a probe array with a probe card including a set of probes for forming electrical contacts with the DUT via one or more pads on the BIST die, wherein the probe card includes at least one multiplexer; a test apparatus coupled to the probe card for sending test signals to the multiplexer of the probe card to select any DUT within the set, and for receiving output signals from the DUT for analysis through the multiplexer without repositioning the set of probes, the test apparatus comprises: a control device for analyzing the output signals from the DUT and for providing address signals to the probe card via an addressing bus, the probe card providing a plurality of physical connections to the BIST die for selecting one or more DUTs for testing based on the address signals; a set of testers coupled to the control device; and a set of matching modules configured to couple radio frequency (RF) signals between the probe card and the set of testers, wherein the probe array is directly coupled to the control device via an address bus to receive the address signals from the control device, and is further coupled to the control device via the matching modules and the testers to provide the RF signals from selected DUTs to the control device for analysis.