Patent ID: 6088276
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of memory blocks each including a plurality of memory cells arranged correspondingly to a plurality of rows and a plurality of columns, respectively, a plurality of word lines arranged correspondingly to said plurality of rows, and a plurality of bit line pairs arranged correspondingly to said plurality of columns;a plurality of global bit line pairs each arranged commonly to said bit line pairs in the corresponding columns of said plurality of memory blocks;a plurality of amplifier means arranged correspondingly to said plurality of global bit line pairs for amplifying potential differences of the corresponding global bit line pairs, respectively;a data I/O terminal; anda data I/O line for transmitting a data signal between said plurality of global bit line pairs and said data I/O terminal,each of said plurality of amplifier means including load means for supplying current to the corresponding global bit line pair in accordance with a potential on the corresponding global bit line pair, and a plurality of input means arranged correspondingly to the corresponding bit line pairs in each of said plurality of memory blocks, each of said plurality of input means receiving the current from the corresponding global bit line pair in accordance with a potential on the corresponding bit line pair.