Patent ID: 6759290
Filing Date: 2004-07-06
Classification: H01L

Abstract:
A method of stitching three resistive layers in a MONOS memory array to three conductive layers comprising:providing a MONOS memory array having said three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; andperiodically contacting each of said resistive layers by a respective upper conductive layer wherein said contacting is said stitching wherein said contacting comprises: periodically connecting said middle resistive layer to a bottom conductive layer overlying said top resistive layer; cutting said middle resistive layer to expose said bottom resistive layer; building a contact/via stack from said exposed bottom resistive layer to a top conductive layer; connecting cut ends of said middle resistive layer by contacting said ends of said middle resistive layer to a middle conductive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contact/via stack; and connecting said top resistive layer to said middle conductive layer.