Patent ID: 6125049
Filing Date: 2000-09-26
Classification: G06F,G11C

Abstract:
A control circuit coupled to an associated match line of a content addressable memory having a row of memory cells, each memory cell having one or more pass transistors cupled between the memory cell and a gate of an associated pull-down transistor coupled between the match line and ground potential, wherein during a compare operation the pull-down transistor pulls the match line to ground potential in response to a mismatch condition between a data bit stored in the memory cell and a comparand bit, the control circuit comprising:a weak pull-up transistor coupled between the match line and a supply voltage and having a gate tied to a predetermined potential so as to maintain the weak pull-up transistor in a conductive state, the weak pull-up transistor thereby slowly charging the match line prior to and during the compare operation; anda strong pull-up transistor coupled between the match line and the supply voltage and having a gate coupled to receive a pre-charge control signal, wherein prior to the compare operation the pre-charge control signal is in a first logic stateso that the strong pull-up transistor conducts and rapidly charges the match line, and wherein during the compare operation the pre-charge control signal is in a second logic state so that the strong pull-up transistor is non-conductive and thereby substantially reduces current flow between the supply voltage and ground potential during the mismatch condition.