Patent ID: 8797781
Filing Date: 2014-08-05
Classification: G11C

Abstract:
1. A semiconductor device comprising: a plurality of word lines extending in a first direction; a plurality of bit line pairs extending in a second direction intersecting the first direction; a plurality of memory cells arranged at crossing portions of the word lines and the bit line pair, and configured with a circuit including a first MIS transistor; a sense amplifier circuit operable to amplify a signal read from one of the memory cells through one of the bit line pair, in response to an enable signal; a control circuit operable to generate a first signal in response to an access instruction to the memory cells; and a timing adjusting circuit operable to receive the first signal inputted and to generate a second signal serving as an origin of the enable signal, by delaying the first signal, wherein the timing adjusting circuit comprises: a first wiring arranged collaterally with the bit line pair and operable to receive the first signal transmitted at one end and to output the second signal from the other end; and a load circuit including a plurality of second MIS transistors coupled to the first wiring.