Patent ID: 6175908
Filing Date: 2001-01-16
Classification: G06F

Abstract:
A microprocessor comprising:an instruction cache for storing a plurality of variable byte-length instructions;a predecode unit coupled to said instruction cache and configured to generate at least one predecode tag associated with at least one byte of an instruction, wherein said at least one predecode tag includes a start bit having a value indicative of whether said at least one byte is a starting byte of said instruction, an end bit having a value indicative of whether said at least one byte is an ending byte of said instruction, and a functional bit that conveys a meaning dependent upon said value of said start bit, wherein a state of said functional bit of a second byte of each of said plurality of variable byte-length instructions and a state of said end bit of a first byte of each of said plurality of variable byte-length instructions is indicative of whether or not said first byte of each of said variable byte-length instructions is a prefix byte;a plurality of decode units for decoding designated instructions which correspond to said plurality of variable byte-length instructions; andan instruction alignment unit coupled between said instruction cache and said plurality of decode units for providing decodable instructions to said plurality of decode units.