Patent ID: 6457148
Filing Date: 2002-09-24
Classification: G01R,G11C

Abstract:
A semiconductor device testing apparatus in which a test pattern signal is produced on the basis of test pattern data outputted from a pattern generator and is applied to a semiconductor device under test, and a response signal outputted from the semiconductor device under test is logically compared with an expected value signal outputted from said pattern generator, thereby to determine whether the semiconductor device under test is defective or not defective, and comprising a plurality of test circuit units each comparing a response signal from the semiconductor device under test with an expected value signal from the pattern generator, said plurality of test circuit units being sequentially operated within one cycle thereby effecting logical comparisons at high rate,each of the plurality of test circuit units comprising: a clock generator for generating a period signal representing an operating period of associated one test circuit unit; a delay setting register in which a latency N is set, said latency N being the number of cycles that an output of a semiconductor device under test is to be delayed; a pattern delay circuit connected to the output side of said delay setting register via a required number of data transmission lines and for delaying the expected value signal by a time interval obtained by multiplying numerical value data transmitted from the delay setting register by the operating period; clock control means connected to the output side of said delay setting register via a required number of data transmission lines and for selecting, in response to numerical value data transmitted from the delay setting register, one of plural timing setting values to supply the selected timing setting value to the clock generator, each of said plural timing setting values setting a timing of generation of the period signal generated from the clock generator; and means for logically comparing a response signal from the semiconductor device under test with an expected value signal from the pattern delay circuit.