Patent ID: 7400528
Filing Date: 2008-07-15
Classification: G11C

Abstract:
1. An integrated circuit having resistive memory cells in which the memory cells are capable of being put into a low-resistance or on state corresponding to a first logic state by application of a write pulse having a specific polarity and into a high-resistance or off state corresponding to a second logic state by application of an erase pulse having an opposite polarity, comprising: a circuit configured to compare a cell content read out from a resistive memory cell that is to be written to with data to be stored in the resistive memory cell, and to supply the erase pulse to the resistive memory cell, independent of the comparison by the circuit, in the event that the data to be stored corresponds to the second logic state, and to supply the write pulse for writing data corresponding to the first logic state in response to the comparison revealing that a logic value of the cell content read out differs from the data to be stored.