Patent ID: 9029936
Filing Date: 2015-05-12
Classification: H01L,Y10S

Abstract:
1. A memory device, comprising: a semiconductor channel; a tunnel dielectric layer located over the semiconductor channel; a first charge trap comprising a plurality of nanodots located over the tunnel dielectric layer, wherein each of the nanodots comprises a core including a metal or a metal alloy and at least some of the nanodots further comprise a silicon oxide shell encapsulating the respective core, wherein the respective core is vertically spaced from the tunnel dielectric layer by the respective silicon oxide shell, and wherein at least one of the nanodots comprises a metal oxide layer comprising an oxide of the metal or the metal alloy of the respective core and located on a surface of the respective core and encapsulated by the respective silicon oxide shell; a dielectric separation layer located over the nanodots; a second charge trap comprising a continuous metal layer located over the separation layer; a blocking dielectric located over the second charge trap; and a control gate located over the blocking dielectric.