Patent ID: 6822913
Filing Date: 2004-11-23
Classification: G06F,G11C

Abstract:
An integrated memory, comprising:a memory cell array including a plurality of memory cells; a read/write amplifier for evaluating and amplifying data signals being read out from or written to said plurality of memory cells of said memory cell array; and an error correction circuit connected to said read/write amplifier; said error correction circuit capable of being activated when reading out from or writing to said memory cell array; said error correction circuit for receiving and checking the data signals, being read out from or written to said memory cell array, for errors; said error correction circuit, upon detecting an erroneous data signal, correcting the erroneous data signal by inverting the erroneous data signal and outputting a corrected data signal; the integrated memory having a prefetch architecture utilized such that data of a first bit width from different areas of said memory cell array being fed in parallel from said memory cell array to said read/write amplifier and being successively output in units of a second bit width; and said error correction circuit checking and correcting the data in the units of the second bit width.