Patent ID: 6088279
Filing Date: 2000-07-11
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word line arranged in a first direction;a plurality of bit lines arranged in a second direction traverse to said first direction;a plurality memory cells provided at intersections of said plurality of word lines and said plurality of bit lines;a means receiving an address for specifying a predetermined memory cell among said plurality of memory cells;a dummy word line connected to said address receiving means and arranged in a same direction as said word line is arranged;a means driving said dummy word line, wherein when said dummy word line attains a predetermined potential, determination is made that said word line has attained a predetermined operating level and a predetermined process is applied to said memory cell;a means connected to said address receiving means, determining whether said dummy word line has attained said predetermined potential; anda loading means providing a larger load of said dummy word line than a load of said word line.