Patent ID: 8587336
Filing Date: 2013-11-19
Classification: H03K

Abstract:
1. A reconfigurable logic block comprising a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of said arithmetic circuit, wherein: said reconfigurable logic block comprises a plurality of hybrid cells including at least first and second hybrid cells, and each of said hybrid cells includes a memory and a plurality of logic gates and is capable of configuring one of a fine-grain cell and a coarse-grain cell; said first circuit includes said first hybrid cell, and is implemented as an adder circuit by changing a setting of an input node level of at least one of said logic gates of said first hybrid cell configured to said coarse-grain cell based on data stored in said memory of said first hybrid cell or a fixed voltage level; and said second circuit includes said second hybrid cell, and is implemented as a canonical form of logic circuit by changing a setting of an input node level of at least one of said logic gates of said second hybrid cell configured to said fine-grain cell based on data stored in said memory of said second hybrid cell or a fixed voltage level.