Patent ID: 6657880
Filing Date: 2003-12-02
Classification: G11C

Abstract:
A memory device having a pair of digit lines (BL & BLN) formed in a first and a second vertically-spaced horizontal connection layers for a column of memory cells, comprising:each of said digit lines having at least one vertical shift zone in which each digit line shifts between the first and the second vertically-spaced horizontal connection layers; each of said digit lines having at least one horizontal shift zone formed in the same one of the first and second vertically spaced connection layers, said horizontal shift zone keeping each digit line in the same connection layer; wherein the digit lines are vertically twisted so that the digit lines do not vertically overlie each other in the same vertical plane; whereby the digit lines of the pair are both vertically and horizontally offset with respect to each other so that one line is in one horizontal connection layer and in one vertical plane while the other line is in the other horizontal connection layer and in another vertical plane.