Patent ID: 6355533
Filing Date: 2002-03-12
Classification: H01L

Abstract:
A method for manufacturing a semiconductor device, comprising the steps of:a) preparing a semiconductor substrate comprising cell and peripheral areas; b) forming a gate structure in each of the cell and peripheral areas, the gate structure comprising a gate dielectric, gate electrode and mask pattern; c) forming a first side wall spacer on each side of each gate structure in the cell and peripheral areas; d) growing a single crystal silicon layer on exposed portions of the semiconductor substrate by selective epitaxial growth; e) sequentially forming a first insulating layer and a second insulating layers over the first insulating layer at least covering partially the substrate and the gate structure to form; Sequentially forming a second side wall spacer covering exposed portions of each first side wall spacer in the peripheral area and a third side wall spacer covering each second side wall spacer; d) conducting ion implantation on the semiconductor substrate in the peripheral area; e) removing the second insulating layer in the cell area and the third side wall spacer in the peripheral area; f) forming an interlayer insulating layer over the cell and peripheral areas; g) removing the interlayer insulating layer from the cell area, and the second insulating layer from the cell area except the top portion and first side walls of the gate structure in the cell area; h) forming a conductive layer over the cell area; and i) planarizing the conductive layer to expose the gate structure in the cell area to form a contact plug in the cell area.