Patent ID: 6518149
Filing Date: 2003-02-11
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, said method comprising:forming a first mask which exposes a cell array region and a peripheral circuit region of a semiconductor substrate, the cell array region and the peripheral circuit region having a same conductive MOS type; implementing a preceding ion implantation process in both the cell array region and the peripheral circuit region utilizing said first mask, the preceding ion implantation process having ion implantation parameters corresponding to first implantation design specifications of one of said cell array region and said peripheral circuit region; forming a second mask which shields said one of said cell array region and said peripheral circuit region and which exposes the other of said cell array region and said peripheral circuit region; and implementing a subsequent ion implantation process in said other of said cell array region and said peripheral circuit region utilizing said second mask, said subsequent ion implantation process having ion implantation parameters which compensate for a difference between the ion implantation parameters of said preceding implantation process and second implantation design specifications of said other of said cell array region and said peripheral circuit region.