Patent ID: 8254173
Filing Date: 2012-08-28
Classification: H01L

Abstract:
1. A NAND memory construction, comprising: dielectric regions extending into a semiconductor material, the semiconductor material comprising pillars extending upwardly between the dielectric regions; individual pillars having a pair of opposing vertically-extending sides along a cross-section, said opposing vertically-extending sides being a first side and a second side; electrically conductive interconnect lines along and directly against the dielectric regions, the interconnect lines extending primarily along a horizontal direction; first conductivity type regions within the semiconductor material pillars along the first sides of the individual pillars within the semiconductor material; the first conductivity type regions being directly against first portions of the dielectric regions; second conductivity type regions within the semiconductor material pillars along the second sides of the individual pillars; the second conductivity type regions being directly against second portions of the dielectric regions and directly contacting the interconnect lines; a plurality of vertical NAND strings over the pillars; and select devices selectively coupling the NAND strings with the interconnect lines, the select devices having vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions, the vertical channels having a pair of opposing vertically-extending sides along the cross-section, and having electrically conductive gate lines along said opposing sides and spaced from the vertical channels by gate dielectric material.