Patent ID: 7320054
Filing Date: 2008-01-15
Classification: G06F

Abstract:
1. A multiprocessor system comprising a common memory and a number of processors connected via a common bus, only one processor being allowed to access same data area of said common memory at a time, wherein: said common memory is provided with a number of data areas that store data mad with a control information area that stores control information indicating whether each of the data areas is in use; each processor is provided with a storage unit for storing same data and same control information as those stored in the common memory and with an access controller; the access controller of a processor that does not have access privilege monitors data and addresses that flow on the common bus, accepts, from the common bus, data written to said common memory and data lead from said common memory and stores this data in a memory area, which is designated by an address, of the storage unit within its own processor; and wherein when access to a prescribed data area in said common memory is requested by a host apparatus, the access controller of each processor reads control information corresponding to this data area in said storage unit, determines whether another processor is busy and, if another processor is busy, inputs result of the determination to the host apparatus without accessing said common memory.