Patent ID: 8430562
Filing Date: 2013-04-30
Classification: G01K

Abstract:
1. A method for evaluating temperature, the method comprises: setting a configuration of a configurable delay line out of multiple possible configurations of the configurable delay line; delaying a first input signal by a temperature sensitive delay line that comprises first type NMOS transistors and first type PMOS transistors; delaying a second input signal by the configurable delay line; wherein the configurable delay line comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of the first type NMOS transistors and the first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and the second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line; repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold; and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.