Patent ID: 6169302
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A virtual field effect transistor for determining a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and for determining a second parasitic capacitance component between said conductive gate region to a source local interconnect of said real field effect transistor, said virtual field effect transistor comprising: a virtual drain local interconnect fabricated on a dielectric, said virtual drain local interconnect having a size that is substantially equal to a size of said drain local interconnect of said real field effect transistor; a virtual source local interconnect fabricated on said dielectric, said virtual source local interconnect having a size that is substantially equal to a size of said source local interconnect of said real field effect transistor; a virtual conductive gate region fabricated on said dielectric, said virtual conductive gate region having a size that is substantially equal to a size of said conductive gate region of said real field effect transistor; and wherein positions of said virtual drain local interconnect, said virtual source local interconnect, and said virtual conductive gate region, relative to each other on said dielectric, are substantially same as positions of said drain local interconnect of said real field effect transistor, said source local interconnect of said real field effect transistor, and said conductive gate region of said real field effect transistor, relative to each other; and a virtual dielectric region fabricated on said dielectric to surround said virtual drain local interconnect, said virtual source local interconnect, and said virtual conductive gate region, and wherein said virtual dielectric region is substantially same as a dielectric region that surrounds said drain local interconnect of said real field effect transistor, said source local interconnect of said real field effect transistor, and said conductive gate region of said real field effect transistor; and wherein said first parasitic capacitance component between said conductive gate region of said real field effect transistor to said drain local interconnect of said real field effect transistor is a first capacitance measured between said virtual conductive gate region and said virtual drain local interconnect; and wherein said second parasitic capacitance component between said conductive gate region of said real field effect transistor to said source local interconnect of said real field effect transistor is a second capacitance measured between said virtual conductive gate region and said virtual source local interconnect.