Patent ID: 6735653
Filing Date: 2004-05-11
Classification: G06F,Y02D

Abstract:
A bus bandwidth consumption profiler for a computer system having a plurality of masters connected to a bus, and a bus arbiter coupled to the masters for outputting grant signals to the masters selected to own the bus, the profiler including:a plurality of master counters coupled to the bus arbiter and the plurality of masters, each master counter responding to a grant signal outputted to its corresponding master by counting bus cycles owned by the corresponding master; a plurality of shadow registers, each of the plurality of master counters having an associated shadow register coupled thereto; and a realtime counter for counting bus cycles between profile events, wherein the realtime counter responds to a profile event by providing to the system a total number of bus cycles counted since a prior profile event, and by resetting the total number of bus cycles counted to zero, and each master counter responds to the profile event by storing in the associated shadow register, for output to the system, the number of bus cycles owned by its corresponding master since a prior profile event, and by resetting the number of owned bus cycles to zero, and wherein values stored in the associated shadow registers do not change between profile events.