Patent ID: 6268243
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A method for fabricating DRAM cells, comprising the steps of:forming a trench within a semiconductor substrate using a stacked layer as a mask, said stacked layer composed of a silicon oxide film and a silicon nitride film formed in an active region of said semiconductor substrate;forming a first insulation layer on a bottom and sides of said trench;depositing a first conductive layer on whole surface of said semiconductor substrate including said trench;etching back said conductive layer to be recessed from a top surface of said semiconductor substrate and forming bit lines of said first conductive layer on said bottom of said trench in a direction of column;filling a second insulation layer in said trench;removing said stacked layer and a part of said second insulation layer to expose said semiconductor substrate in said active region and planarizing said semiconductor substrate simultaneously;forming a gate insulation layer on said semiconductor substrate;forming a gate structure of a second conductive layer on said gate insulation layer;forming a spacer of an insulation layer on said sides of said gate structure of said second conductive layer;forming source and drain regions on both sides of said gate structure of said second conductive layer;forming a third insulation layer on said semiconductor substrate;connecting said bit lines to a first one of said source and drain regions with a plug of a third conductive layer filled in a contact hole inside said third insulation layer and said second insulation layer; andforming a capacitor connected to a second one of said source and drain regions.