Patent ID: 6657462
Filing Date: 2003-12-02
Classification: G06F,H03K

Abstract:
A clock buffer circuit comprising:a precharge circuit configured to precharge a first node; a first transistor having a first terminal coupled to the first node, a second terminal coupled to a second node, and a first control terminal; a second transistor having a third terminal coupled to the first control terminal, a fourth terminal coupled to the second node, and a second control terminal coupled to receive a condition signal; and a third transistor having a fifth terminal coupled to the second node, a sixth terminal, and a third control terminal coupled to receive a clock signal; wherein the second transistor is activated responsive to the condition signal, and wherein the third transistor is configured to discharge the second node responsive to an assertion of the clock signal, and wherein a setup time of the condition signal to the second transistor is determined by a falling edge of a signal on the second node.