Patent ID: 6326260
Filing Date: 2001-12-04
Classification: H01L

Abstract:
A method of forming a gate conductor useful in a semiconductor memory device comprising the steps of:(a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array regions and support regions which may have different oxide thicknesses;(b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer;(c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon;(d) forming spacers on exposed sidewalls of said partially etched gate stack;(e) completing said mask open etching in said array regions by removing any exposed polysilicon, while not etching said layer of polysilicon in the support regions;(f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support regions;(g) selectively removing said spacers in said support regions of said structure;(h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support regions; and(i) performing a second oxidization step on said structure so as to form an array oxide layer and a support oxide layer, said array oxide layer having a thickness that is greater than the support oxide layer, said array oxide layer comprising oxide layers from said first and second oxidation steps.