Patent ID: 6202148
Filing Date: 2001-03-13
Classification: G06F

Abstract:
A commutator circuit comprising at least one data transposition circuit connected between a pair of data inputs and a pair of data outputs, the data transposition circuit including two 2-to-1 selector switches each having two inputs connected to respective ones of the pair of data inputs and a single output connected to a respective one of the pair of data outputs, and a delay element connected in series with one of the data inputs and/or one of the data outputs, the commutator circuit further comprising an input for synchronizing signals and means for deriving from the synchronizing signals a control signal for the selector switches, wherein the commutator circuit comprises a plurality of stages connected in series, each stage having a plurality of data inputs and a like plurality of data outputs with the data outputs of each stage except the last being connected in one-to-one correspondence to the data inputs of the next stage, and wherein each stage comprises a plurality of the said data transposition circuits each connected between a respective pair of the data inputs and a respective pair of the data outputs for that stage, the commutator circuit further comprising means associated with each stage for deriving from the synchronizing signals a control signal for the selector switches of that stage.