Patent ID: 8041912
Filing Date: 2011-10-18
Classification: G06F,G11C

Abstract:
1. A memory device comprising: a memory array containing a number of memory blocks, the memory blocks being configured to have independent access control; a status register coupled with the memory array, the status register including at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit; a status-register write-protect bit coupled with the status register for preventing a state change of the at least one protection bit; and a security register coupled with the memory array and the status register, the security register including at least one register-protection bit, the register-protection bit being programmable to a memory-protection state for preventing the state change in one of the status-register write-protect bit and the at least one protection bit of the status register, wherein the register-protection bit is configured to remain in the memory-protection state until a resetting of the memory device.