Patent ID: 8432027
Filing Date: 2013-04-30
Classification: H01L

Abstract:
1. An integrated circuit die stack comprising: a first integrated circuit die mounted upon a substrate, the first die comprising pass-through vias (‘PTVs’), each PTV comprising a conductive pathway through the first die with no connection to any circuitry on the first die; a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die, each TSV on the second die comprising a conductive pathway through the second die that is also connected to electronic circuitry on the second die; the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die; and an interface die mounted upon the substrate between the substrate and the first die splitting and connecting a same set of signal lines from the substrate to the PTVs on the first die and separately to TSVs on the first die.