Patent ID: 8415988
Filing Date: 2013-04-09
Classification: G06F,H03K

Abstract:
1. A circuit for producing a clocking signal for a capacitance clock input of a device, the circuit comprising: an output of a drive gate connected to an emitter of an NPN bi-polar transistor through a first coupling capacitor and connected to an emitter of a PNP bi-polar transistor through a second coupling capacitor, wherein the NPN bi-polar transistor and the PNP bi-polar transistor are connected in a common base configuration with collectors of the NPN and PNP bi-polar transistors connected together; a first DC voltage supply connected to a base of the PNP bi-polar transistor; a second DC voltage supply connected to a base of the NPN bi-polar transistor, wherein a signal produced by the first DC voltage supply is larger than a signal produced by the second DC voltage supply; a first diode connected in parallel with the base emitter of the PNP bi-polar transistor with an anode of the diode connected to the base of the PNP bi-polar transistor; a second diode connected in parallel with the base emitter of the NPN bi-polar transistor with a cathode of the diode connected to the base of the NPN bi-polar transistor; and a damping resistor connected between the collectors of the NPN and PNP bi-polar transistors and the capacitance clock input of the device.