Patent ID: 8030155
Filing Date: 2011-10-04
Classification: H01L

Abstract:
1. A method of forming an integrated circuit including a rectifying diode, comprising: forming a first semiconductor region of first conductivity type and of first dopant concentration for the diode of the substrate, commonly with forming at least one transistor well region on or in a semiconductor substrate; forming a plurality of second semiconductor regions of the first conductivity type at laterally spaced locations in the first semiconductor region and of a second dopant concentration greater than the first dopant concentration, commonly with forming at least one transistor source/drain region on or in the semiconductor substrate; forming a plurality of first conductive contacts to the first semiconductor region at locations intermediate ones of the laterally spaced locations; and forming a plurality of second conductive contacts respectively to the plurality of second semiconductor regions, laterally spaced from the conductive contacts to the first conductive region; wherein at least one of the first conductive contacts or second conductive contacts is formed commonly with forming a third conductive contact to at least one transistor gate or transistor source/drain region; wherein application of a forward bias to ones of the first and second conductive contacts relative to the others of the first and second conductive contacts will flow current in a current flow path that does not go through any layer buried relative the first semiconductor region.