Patent ID: 8331137
Filing Date: 2012-12-11
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: first and second conductive lines intersecting each other; a memory cell comprising a variable resistance element and a capacitor connected in series between the first and second conductive lines; and a control circuit applying one of first and second voltage pulses to the memory cell, wherein the capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses, wherein the control circuit makes the trailing edge waveforms of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value lower than the first resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.