Patent ID: 6188021
Filing Date: 2001-02-13
Classification: H01L,H05K

Abstract:
A packaged semiconductor device assembly, comprising:a semiconductor die;a leadframe including at least one lead having an upper surface, a lower surface, a plurality of edge surfaces, and a thickness, said at least one lead comprising:an inner end connected to said semiconductor die;an intermediate portion for connection to a first electrical apparatus; andan outer lead for connection to a second electrical apparatus; anda package enclosure enclosing said semiconductor die and the inner end of said at least one lead, said package enclosure having a top surface, a bottom surface, and a plurality of side surfaces, said lower surface of said intermediate portion of said at least one lead of said leadframe being coplanar with said bottom surface of said package enclosure for electrical connection to a lead of the first electrical apparatus, portions of the package enclosure located adjacent the plurality of edge surfaces of said intermediate portion of said at least one lead of said leadframe being excised forming excised portions exposing at least a portion of said plurality of edge surfaces of said at least one lead of said leadframe.