Patent ID: 7390710
Filing Date: 2008-06-24
Classification: H01L

Abstract:
1. A method of forming an isolation region in an integrated circuit device, comprising: defining an area for the isolation region in a silicon-containing substrate having a dielectric layer overlying the silicon-containing substrate, a silicon-containing layer overlying the dielectric layer and a hard mask layer overlying the silicon-containing layer; removing portions of the hard mask layer, the silicon-containing layer and the dielectric layer from the area for the isolation region, thereby exposing edges of the hard mask layer, silicon-containing layer and dielectric layer; forming a trench in the silicon-containing substrate in the area for the isolation region, thereby exposing sidewalls of the trench; forming layers of epitaxial silicon on the edges of the silicon-containing layer and the exposed sidewalls of the trench; oxidizing the layers of epitaxial silicon after forming the layers of epitaxial silicon; and filling the trench with a dielectric material.