Patent ID: 6487124
Filing Date: 2002-11-26
Classification: G11C

Abstract:
A nonvolatile semiconductor storage device having a plurality of nonvolatile memory cells arranged in a matrix form and bit lines and word lines connected to the nonvolatile memory cells, the nonvolatile memory cells adjoining in a direction in which the word lines extend sharing one bit line, the device comprising:a full bit precharge means for charging all the bit lines with electric charges; a selective discharge means for selectively discharging one or more adjoining bit lines that include either one of two bit lines connected to a selected nonvolatile memory cell; a selective precharge means for selectively applying a precharge voltage to any one of one or more bit lines adjacent to the other bit line of the two bit lines connected to the selected nonvolatile memory cell; a precharge control circuit for operating the full bit precharge means during full bit precharge for charging all the bit lines and operating the selective precharge means in a read operation; and a discharge control circuit for operating the selective discharge means in the read operation.