Patent ID: 7199472
Filing Date: 2007-04-03
Classification: H01L

Abstract:
1. A semiconductor device having a first circuit area inside a semiconductor chip and a plurality of wiring layers which are formed above a main surface of a semiconductor substrate, said wiring layers including a first wiring layer which is comprised of copper as a main element, with a plurality of first lines being formed thereof, and a second wiring layer which is an upmost wiring layer among said wiring layers and is comprised of aluminum as a main element, with a plurality of second lines being formed thereof, a first line of said first wiring layer being formed by a buried line, said second lines of said second wiring layer being made larger in thickness than said first lines of said first wiring layer which is immediately below said second wiring layer, said second lines of said second wiring layer having a plurality of external terminals, a plurality of first power lines surrounding said first circuit area, and a plurality of second power lines each of which is directly connected to an external terminal and a first power line.