Patent ID: 6370595
Filing Date: 2002-04-09
Classification: G06F

Abstract:
A method of addressing units (FU1, FU2, FU3) amongst a plurality of units having different addresses (ADD1, ADD2, ADD3) by means of a single address word (AW), the addresses and the address word being composed of address elements, wherein the method comprises in series the steps of:transmitting a tag word (TW) to the plurality of units, the tag word defining which address elements of the address word are significant (s) and which address elements of the address word are non-significant don't care values (x); addressing more than one of the address units from the single address word (AW) by associating the tag word (TW) with the address word (AW) so that significant elements of the address word match with address bits of more than one of the address units that have a same value, and non-significant elements of the address word match with address bits of more than one of the address units having a complementary value, said non-significant bits being set as don't care values, and comparing the address word and the addresses of the units, a unit being addressed if the significant elements of the address word match the corresponding elements of the unit's address.