Patent ID: 6198653
Filing Date: 2001-03-06
Classification: G11C

Abstract:
A ferroelectric memory comprising a plurality of memory cells arranged in rows and columns, in which each memory cell has a capacitor and a transistor, the capacitor has first and second opposed electrodes and a ferroelectric film disposed between the first and second electrodes and, stores and holds binary information by a polarization state of the ferroelectric film, and one of a source and a drain of the transistor is connected with the first electrode of the capacitor, the ferroelectric memory further comprising:a word line connected with a gate of the transistor of a memory cell;a bit line connected with the other of the source and the drain of the transistor of the memory cell and coupled to one input of a sense amplifier;a complementary bit line supplied with a reference voltage and coupled to the other input of the sense amplifier;a plate line connected with the second electrode of the capacitor of the memory cell; anda switching means through which the plate line is connected with the complementary bit line,wherein with the word line being active and the memory cell selected, data is written or rewritten to this memory cell by turning on the switching means and transferring a voltage of the complementary bit line to the plate line.