Patent ID: 6087218
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method for manufacturing a DRAM capacitor comprising the steps of:providing a semiconductor substrate having at least one MOS transistor formed thereon, wherein the MOS transistor has a gate that acts as a word line and source/drain terminals in the substrate on each side of the gate terminal, and a patterned polysilicon layer between two transistor gates acting as a bit line, said bit line being electrically coupled to one source/drain terminal of the MOS transistor;forming an insulating layer over the substrate, the word line and the bit line;forming a mask layer, a first oxide layer and a first polysilicon layer over the insulating layer;forming an opening in the first polysilicon layer located directly above a source/drain region;forming a second oxide layer over the first polysilicon layer and the opening, the second oxide layer forming a groove in the opening;using a self-aligned etching process, the second oxide layer, a portion of the mask layer, a portion of the first oxide layer and a portion of the insulating layer are etched to form a contact window in the insulting layer;depositing a second polysilicon layer over the first polysilicon layer and into the contact window forming electrical connection with the source/drain region;patterning the first polysilicon layer and the second polysilicon layer, then removing the first oxide layer, wherein the first polysilicon layer and the second polysilicon layer together act as a lower electrode of the capacitor; andforming a dielectric layer over the first and the second polysilicon layers, then forming a third polysilicon layer over the dielectric layer to act as an upper electrode of the capacitor.