Patent ID: 6678184
Filing Date: 2004-01-13
Classification: G11C

Abstract:
A content addressable memory circuit in a semiconductor substrate comprising:a match signal output having a logical state set to a first value; a compare circuit for comparing a stored data value to an input compare data value having an enable input, a match output coupled to the match signal output, a compare data input coupled to a compare data signal, and a stored data input, wherein if the enable input receives an enable true signal and the stored data input receives a stored data signal and the compare data false input receives a compare data signal then the logical state of the match signal output will change to a second value thereby indicating a no match; a first data storage device for storing a data value having first and second word lines, first and second bit lines, a stored data output, and a first conductive strip electrically coupling the stored data output to the stored data input of the compare circuit wherein the stored data output provides the stored data signal, wherein the first word line of the first data storage device is formed in a first conductive region and the second word line of the first data storage device is formed physically separate and distinct from the first conductive region in a second conductive region; and a second data storage device for storing an enable value having first and second word lines, first and second bit lines, an enable output, and a second conductive strip electrically coupling the enable output to the enable input of the compare circuit wherein the enable output provides the enable true signal.