Patent ID: 7973584
Filing Date: 2011-07-05
Classification: G01R,H03K

Abstract:
1. A waveform generator comprising: m variable delay circuits for setting, each of which is configured to provide a variable delay to a reference pulse signal in accordance with a set timing signal, where m is an integer of 2 or greater; m variable delay circuits for resetting, each of which is configured to provide a variable delay to the reference pulse signal in accordance with the reset timing signal; a flip-flop configured to be set by a multiplexed output signal from the m variable delay circuits for setting, and to be reset by a multiplexed output signal from the m variable delay circuits for resetting; and a waveform shaper configured to receive, at every predetermined cycle, a group of n pieces of timing setting data that include an arbitrary combination of a set timing signal indicating a positive edge timing of an output signal to be generated and a reset timing signal indicating a negative edge timing thereof, where n is an integer of 2 or greater, and configured to assign the group to the m variable delay circuits for setting and the m variable delay circuits for resetting, wherein the waveform shaper includes: a sort unit configured to sort n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data; an open processor configured to detect continuation of the set timing signals or continuation of the reset timing signals with reference to n pieces of the timing setting data thus sorted, and configured to invalidate one of the continuous set timing signals and one of the continuous reset timing signals; and an edge assigning unit configured to sequentially assign the set timing signals remaining without being invalidated to, among the m variable delay circuits for setting, the variable delay circuits for setting in the ascending order of the frequencies of use thereof by then, and configured to sequentially assign the reset timing signals remaining without being invalidated to, among the m variable delay circuits for resetting, the variable delay circuits for resetting in the ascending order of the frequencies of use thereof by then.