Patent ID: 7134058
Filing Date: 2006-11-07
Classification: G11C

Abstract:
1. A semiconductor integrated circuit comprising a plurality of combinational logic components, a memory and a testing arrangement to configure the memory prior to testing the combinational logic components using one or more scan chains, the testing arrangement comprising: a data generator internal to the integrated circuit to generate a selected bit pattern to write to the memory; a switching arrangement to selectively switch the memory input to receive data from the combinational logic components or from the data generator, wherein the switching arrangement and data generator are arranged for the data generator to input the selected bit pattern to the memory prior to testing the combinational logic components of the integrated circuit; and a testing circuit to test the combinational logic components, using a test pattern, after the data generator has input the selected bit pattern to the memory, wherein the testing arrangement includes a wrapper circuit and includes a control to selectively control the memory to output a predictable output if the test pattern is supplied to the combinational logic components after writing the selected bit pattern to the memory, wherein the combinational logic components and memory remain connected while testing the integrated circuit using the test pattern.