Patent ID: 7152192
Filing Date: 2006-12-19
Classification: G11C

Abstract:
1. An integrated circuit for accommodating the parallel testing of a plurality of memory blocks disposed therein, each memory block comprising data bit storage cells in an array of rows and columns, wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, said integrated circuit comprising: a first bus distributed in parallel to said plurality of memory blocks, said first bus comprising row address, data word and control lines which are brought out to first input/output (I/O) pins of the integrated circuit; a set of data word output lines coupled from each memory block of said plurality for reading out data words accessed therefrom; a data word comparator for each of said plurality memory blocks, each data word comparator comprising a latching bit comparator for each column of the corresponding memory block; a second bus distributed in parallel to the plurality of data word comparators, said second bus comprising data word lines which are brought out to second I/O pins of the integrated circuit; each of said latching bit comparators having one input coupled to a respectively corresponding data word output line of the corresponding memory block, another input coupled to a respectively corresponding data word line of the second bus, and an output for providing a column status bit; and comparator control lines distributed in parallel to said latching bit comparators and brought out to third I/O pins of the integrated circuit.