Patent ID: 7855141
Filing Date: 2010-12-21
Classification: H01L

Abstract:
1. A method of producing a semiconductor device including a plurality of wiring layers, comprising: forming a first interlayer-insulating film; forming a plurality of first grooves for wiring in the first interlayer-insulating film; forming a first wiring layer by filling metallic films in the first grooves for wiring; polishing and removing upper surfaces of the first wiring layer and the first interlayer-insulating film to flatten the upper surfaces thereof; forming a second interlayer-insulating film on flattened upper surfaces of the first wiring layer and the first interlayer-insulating film; forming a barrier insulating film on the second interlayer-insulating film; forming a third interlayer-insulating film on the barrier insulating film; etching the second interlayer-insulating film, the barrier insulating film, and the third interlayer-insulating film and removing a portion of the second interlayer-insulating film, the barrier insulating film, and the third interlayer-insulating film to provide a first contact hole and a second groove for wiring; forming a second wiring layer including a wiring and plug by filling metallic films in the first contact hole and the second groove for wiring; removing the third interlayer-insulating film to expose the barrier insulating film and the second interlayer-insulating film; depositing a fourth interlayer-insulating film on the barrier insulating film and the second interlayer-insulating film being exposed; performing a thermal process to the fourth interlayer-insulating film at a predetermined temperature to promote dehydrating polymerization and solvent evaporation to generate pores in the fourth interlayer-insulating film so as to form a porous insulating film; and polishing and removing an upper surface of the fourth interlayer-insulating film to flatten the upper surface thereof.