Patent ID: 7221611
Filing Date: 2007-05-22
Classification: G11C

Abstract:
1. A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, the semiconductor memory device comprising: a first power supply for supplying a first power source voltage; a second power supply for supplying a second power source voltage having a lower voltage level than the first power source voltage; a standard ground for providing a standard ground voltage; an elevated ground circuit for providing an elevated ground voltage having a higher voltage level than the standard ground voltage; a first power circuit, which is connected with the first power supply and the standard ground and which operates in response to the first power source voltage; and a second power circuit, which is connected with the second power supply and the elevated ground circuit and which operates in response to the second power source voltage.