Patent ID: 6777992
Filing Date: 2004-08-17
Classification: H03K

Abstract:
A flip-flop, comprising:an input value that provides a logic voltage indicating a logic state of the flip-flop; at least a first transistor connected to a clock signal generating circuit at a source or drain of the first transistor; at least a second transistor connected to a clock signal generating circuit at a source or drain of the second transistor; the clock signal generated by the clock signal generating circuit that is ramped or sinusoidal; and a latching circuit that latches a latch voltage value based on a first clock voltage at a first connection point and a second connection point, wherein the latch voltage is representative of the input value; wherein the first connection point is a source or drain of the first transistor that is opposite to the clock signal generating circuit; and wherein the second connection point is a source or drain of the second transistor that is opposite the clock signal generating circuit.