Patent ID: 7697353
Filing Date: 2010-04-13
Classification: G11C

Abstract:
1. A semiconductor device comprising: two or more memory cell blocks, each having a memory cell array of a plurality of memory cells; a plurality of control circuits, provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks; a plurality of input/output terminals for inputting the information to be written and for outputting the information to be read; a plurality of multiplexers, provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/output terminals; and a bidirectional transfer type buffer, connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits, wherein the bidirectional transfer type buffer comprises: a first transfer circuit for transferring information from one of the connection lines to the other of the connection lines; and a second transfer circuit for transferring information from the other of the connection lines to the one of the connection lines; an input terminal of the first transfer circuit and an output terminal of the second transfer circuit are connected at a first node; an output terminal of the first transfer circuit and an input terminal of the second transfer circuit are connected at a second node; the first node is connected to the one of the connection lines; and the second node is connected to the other of the connection lines.