Patent ID: 7293198
Filing Date: 2007-11-06
Classification: G06F

Abstract:
1. A data storage system, comprising: a first storage processor; a second storage processor; and a communications subsystem having (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit, the controller being configured to: wherein the controller of the communications subsystem includes: wherein the interfacing portion of the communications subsystem includes a first interface device coupled to the first storage processor, a second interface device coupled to the second storage processor, and a communications bus connecting the first and second interface devices together; wherein the controller of the communications subsystem further includes: wherein (i) the first interface device is disposed at one end of the communications bus and (ii) the second interface device is disposed at another end of the communications bus to form a communications pathway between the first and second storage processors; and wherein the controller, when enabling operation of the interfacing portion, is configured to: