Patent ID: 6754599
Filing Date: 2004-06-22
Classification: G06F

Abstract:
An integrated circuit comprising:a function clock circuit generating a function clock signal; an operation circuit connected to said function clock circuit operating in synchronism with said function clock; a trace trigger circuit connected to said function clock circuit and said operation circuit, said trace trigger circuit triggering trace of operation of said operation circuit upon detection of a predetermined condition within said operation circuit; a clock circuit including a reference clock input for receiving a reference clock signal, an controllable oscillator circuit generating an oscillator clock signal, a multiplexer having a first input connected to said function clock circuit for receiving said function clock signal, a second input connected to said reference clock input for receiving said reference clock signal, and an output, said multiplexer selecting at said output one of said function clock signal and said reference clock signal, a comparison circuit connected to said multiplexer controlling a frequency of said controllable oscillator circuit to achieve a frequency match between said clock signal selected by said multiplexer and said oscillator clock signal; a trace first-in-first-out buffer having an input connected to said function clock circuit and said operation circuit for storing trace data in synchronism with said function clock signal and an output connected to said controllable clock circuit for outputting trace data in synchronism with said oscillator clock signal; and a trace output port connected to said controllable clock circuit and said output of said trace first-in-first-out buffer outputting trace data in synchronism with said oscillator clock signal.