Patent ID: 6353647
Filing Date: 2002-03-05
Classification: H03L

Abstract:
Phase-locked loop arrangement for synchronizing an output signal of said phase-locked loop with an input reference signal, comprising:an output signal source for providing said output signal in response to a control signal, said output signal having a frequency that is dependent upon said control signal; phase detector means responsive to said input reference signal and said output signal for providing an error signal representative of the difference in phase between said input reference signal and said output signal; first feedback means connected from the output of the output signal source to an input of said phase detector means for applying, said output signal to said phase detector means; differentiating means responsive to said error signal for providing a differentiated signal representative of a discrete-time approximation of the time-derivative of said error signal; digital filter means responsive to said error signal and said differentiated signal for providing a digital control signal; a digital-to-analog converter responsive to said digital control signal for converting said digital control signal into said control signal; and means for controlling the signal contribution from said differentiating means such that lock-acquisition is performed in two different phases, a first initial frequency-locking phase at the beginning of lock-acquisition and a second main phase-locking phase, wherein said control signal means includes first means for gradually decreasing the signal contribution from said differentiating means from a first relatively high value to a second lower value during said first initial frequency-locking phase so that focus of the regulation is shifted from frequency locking to phase locking.