Patent ID: 8674726
Filing Date: 2014-03-18
Classification: H03K,H03L,H03M

Abstract:
1. An apparatus comprising: an integrated circuit (IC) having a power terminal connected to receive a power signal and having a decoding circuit, the decoding circuit including a signal-adjust circuit configured and arranged to generate a power-related adjustment signal in response to the power signal; at least one digital-input-signal pad configured and arranged for communicating digital signals between the integrated circuit and another circuit which is external to the integrated circuit; digital-input processing circuitry, within the IC and including binary logic circuitry, configured and arranged for receiving the digital signals from the digital-input-signal pad and for processing the received digital signals using the binary logic circuitry; and configuration circuitry configured and arranged for applying the power-related adjustment signal to signals received at the at least one digital-input-signal pad and, in response thereto, for detecting that the digital signals received at the at least one digital-input-signal pad convey information using a first group of a plurality of states of information and at least two additional states of information, wherefrom more than the plurality of states of information in the first group are decoded from the information conveyed over the at least one digital-input-signal pad.