Patent ID: 8281269
Filing Date: 2012-10-02
Classification: G06F

Abstract:
1. A computer-implemented method for designing a semiconductor integrated circuit device layout by dividing design data of an entire chip into hierarchically-arranged design data of a top block and design data of a plurality of lower-order blocks, the method comprising: performing by a processor a boundary simultaneous optimization process in which the layout of a timing path used for timing optimization is designed only at boundaries between the top block and the lower-order blocks, wherein the boundary-simultaneous optimization process is performed in a state in which circuits and signal lines belonging to a top block are temporarily arranged, and signal lines, the operation timing of circuits, and location and routing arrangements in the lower-order blocks are optimized, wherein, in order to couple a first signal line between the circuit belonging to the top block and a signal terminal belonging to one of the lower-order blocks, the boundary simultaneous optimization process is performed in a state where location information of the signal terminal is deleted before the first signal line is coupled, and wherein the boundary simultaneous optimization process is performed in a state where location information of the boundaries of the top block and the lower-order blocks is deleted.