Patent ID: 8003488
Filing Date: 2011-08-23
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor structure comprising: forming a pad layer on a semiconductor-on-insulator (SOI) substrate; forming at least two deep trenches in said pad layer and said SOI substrate; forming a conductive trench fill region in each of said at least two deep trenches, wherein said conductive trench fill region has an upper conductive surface that is recessed below a top surface of said SOI substrate and said forming said conductive trench fill region includes filling said at least two deep trenches with a conductive trench fill material; planarizing and recessing said conductive trench fill material to a first recess depth below a top surface of a buried insulator layer within said deep trench; filling said deep trench with another conductive trench fill material; and planarizing and recessing said another conductive trench fill material to a second recess depth below a top surface of said pad layer within said deep trench, wherein said second recess depth is less than said first recess depth; applying a planarization material layer on the upper conductive surface of said conductive trench fill region and said pad layer; applying a bottom anti-reflective coating (BARC) layer on said planarization material layer; applying a photoresist layer on said BARC layer; patterning and etching the photoresist layer, the BARC layer, and the planarization material layer to expose a portion of the pad layer between the at least two deep trenches, wherein a portion of at least the planarization material layer is present atop the upper conductive surface; removing the portion of said pad layer between the at least two deep trenches, wherein a top semiconductor portion between the at least two deep trenches of said SOI substrate is exposed, and a remaining portion of said pad layer includes a sidewall that is vertically coincident with, and is directly adjoined to, a sidewall of said deep trench, and wherein said top semiconductor portion laterally contacts another sidewall of said deep trench; removing said top semiconductor portion between the at least two deep trenches and exposing a top surface of a buried insulator layer of said SOI substrate; removing remaining portions of the photoresist layer, the BARC layer, and the planarization material layer; and forming a shallow isolation trench structure having a first portion directly on said top surface of said buried insulator layer and a second portion directly on the upper conductive surface of said conductive trench fill region, wherein said first portion and second portion of the shallow trench isolation structure are simultaneously formed.