Patent ID: 6436798
Filing Date: 2002-08-20
Classification: H01L

Abstract:
A method of fabricating a semiconductor structure comprising a substrate having an active region of a first conductivity type including a channel region and a non-channel region surrounding the channel region, at least a first trench and a second trench disposed in the channel region, the method comprising:forming a thin insulating layer over the said first and second trenches in the active region; wherein the thin insulating layer is conformal to the profile of said first and second trenches; forming a conductive layer to fill the trenches in the active region; patterning the conductive layer to form a gate electrode, wherein the gate electrode comprises a first vertical portion, a second vertical portion and a horizontal portion, with the first vertical portion being embedded inside the first trench, the second vertical portion being embedded inside the second trench, and the horizontal portion being disposed over the substrate and connecting said first and second vertical portions together; performing a first ion implantation with first ions to form a first doped region within the substrate at an upper corner adjacent to the first vertical portion of the gate electrode and a second doped region at an upper corner adjacent to the second vertical portion of the gate electrode; and performing a second ion implantation with second ions by using a mask, to form a deep source/drain region within the substrate, wherein the opening in said mask is wider than each of the first and second trenches and the deep source/drain region is formed at a depth deeper than the first and second trenches.