Patent ID: 6424566
Filing Date: 2002-07-23
Classification: G11C

Abstract:
A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within said memory cell, the method comprising:setting a target number T of programming pulses for programming each of said 2Nâˆ’1 vt levels of said memory cell; applying T*(2Nâˆ’1) programming pulses to said memory cell; determining when the highest one of the 2Nâˆ’1 vt levels is programmed; and if it is determined that the highest one of the 2Nâˆ’1 vt levels is programmed by a number M of programming pulses that is less than the target number T, then compensating the programming speed of those ones of said T*(2Nâˆ’1) number of programming pulses subsequent to said Mth programming pulse.