Patent ID: 6237083
Filing Date: 2001-05-22
Classification: G06F

Abstract:
A microprocessor comprising:a decode unit configured to decode instructions defined within an instruction set including a first type of instructions, a second type of instructions, and an empty state instruction, wherein said instruction set further defines that a first plurality of registers accessible via said first type of instructions and a second plurality of registers accessible via said second type of instructions are mapped onto a logical storage in which each of said first plurality of registers is assigned to a logical storage location to which a corresponding one of said second plurality of registers is assigned;a first register file including physical storage locations corresponding to said first plurality of registers;a second register file including physical storage locations corresponding to said second plurality of registers;a first execution unit coupled to said first register file, wherein said first execution unit is configured to execute instructions of said first type, and wherein said first execution unit is configured to read operands for said instructions of said first type from said first register file; anda second execution unit coupled to said second register file, wherein said second execution unit is configured to execute instructions of said second type, and wherein said second execution unit is configured to read operands for said instructions of said second type from said second register file;wherein said microprocessor is configured to inhibit a synchronization of said first register file and said second register file between an execution of said first instruction and an execution of said second instruction responsive to executing a first instruction sequence including a first instruction of said first type, said empty state instruction, and said second instruction of said second type.