Patent ID: 8433851
Filing Date: 2013-04-30
Classification: G06F

Abstract:
1. A data processing system comprising: at least one processor; a first level cache communicatively coupled to the at least one processor and divided into two or more cache slices based on an address hierarchy; and a second level cache communicatively connected to the first level cache, wherein said second level cache is divided into two or more second cache slices, wherein said two or more second cache slices are each at least two-way sectored, and wherein the sectors within each of the two or more second cache slices are allocated in a discontiguous manner according to the address hierarchy, such that a first sector is assigned to a first of the two or more second cache slices and a second sector, contiguous to the first sector, is assigned to a second of the two or more second cache slices, the second level cache further comprising a second level cache addressing protocol comprising cache-line address bit assignment logic that: