Patent ID: 8564092
Filing Date: 2013-10-22
Classification: H01L

Abstract:
1. A packaged circuit comprising: a substrate formed as an inductor; an electrically insulating frame structure arranged on a surface of the inductor substrate and defining an outer periphery at an outside portion of the frame and defining a chamber at an inner periphery at an inside portion of the frame, and with a frame attach surface opposite the surface of the inductor substrate and configured for attachment to a mounting structure; an integrated circuit die including an interconnect surface and a die attach pad (DAP) surface opposite the interconnect surface and configured for attachment to the mounting structure; an electrical interconnect structure including at least a first portion disposed within the chamber and at least a second portion extending outside the chamber; wherein the die is disposed in the chamber with the interconnect surface connected to the inductor substrate by the first portion of the electrical interconnect structure, and with the DAP located opposite inductor substrate; and a protective filler in the chamber encapsulating the die and at least the first portion of the interconnect structure, and exposing the DAP surface of the die and the frame attach surface for mounting to the mounting structure.