Patent ID: 6115294
Filing Date: 2000-09-05
Classification: G06F,G11C,H03K

Abstract:
A register cell that stores more than one bit of information, comprising:a first multiplexer configurable to select a first N-NARY input when said first multiplexer is in a first state, and to select a second N-NARY input when said first multiplexer is in a second state, and further configured to provide multi-bit storage data, said first N-NARY input being configured to receive multi-bit data from outside the cell;a word input configured to receive a word enable;a delay element configured to receive the multi-bit storage data and subsequently to provide the multi-bit storage data to said second N-NARY input of said first multiplexer; andan output element configured to receive the multi-bit storage data and, when selected by said word enable, to provide the multi-bit storage data to an output.