Patent ID: 7659128
Filing Date: 2010-02-09
Classification: B41J,H01L

Abstract:
1. A method of processing a silicon wafer, comprising: forming, on a silicon wafer having a (110) plane as its one surface, a break pattern including a plurality of through holes, each of which has a first (111) plane that is perpendicular to the (110) plane of the silicon wafer, a second (111) plane that is opposite to the first (111) plane, a third (111) plane that is perpendicular to the (110) plane and intersects the first (111) plane at an acute angle, and a fourth (111) plane that is opposite to the third (111) plane, is perpendicular to the (110) plane, and intersects the second (111) plane at an acute angle, using anisotropic etching; performing the anisotropic etching on the silicon wafer using a mask pattern having a predetermined shape to form, around the break pattern, a thin portion that has a smaller thickness than other portions of the silicon wafer; and dividing the silicon wafer into a plurality of silicon substrates along the break pattern, wherein the forming of the thin portion includes: forming a correction pattern that covers the edges of acute portions of each of the through holes in the silicon wafer so as to protrude from the edges by a predetermined width; and performing the anisotropic etching on the silicon wafer using the mask pattern including the correction pattern, thereby delaying the start of the etching of the edges of the acute portions in the silicon wafer.