Patent ID: 6373912
Filing Date: 2002-04-16
Classification: H03L

Abstract:
An apparatus, comprising:a first divider circuit adapted to receive an incoming signal and generate a reference signal, the reference signal being generated by dividing the incoming signal by m during a phase-lock initiation mode and dividing the incoming signal by n for a steady-state time period following the phase-lock initiation mode; a voltage-controlled oscillator adapted to provide an output signal; a second divider circuit adapted to receive the output signal and generate a feedback signal, the feedback signal being generated by dividing the output signal by x during the phase-lock initiation mode and dividing the output signal by y for a steady-state time period after the phase-lock initiation mode; and a phase detection circuit adapted to detect a phase difference between the reference signal and the feedback signal and to control the voltage-controlled oscillator so that the frequency of the output signal is substantially synchronized to the incoming signal.