Patent ID: 6197633
Filing Date: 2001-03-06
Classification: H01L

Abstract:
A method for producing an integrated semiconductor memory configuration having storage capacitors, which comprises:providing a semiconductor body having a main surface with contacts and a memory configuration with a plurality of memory cells, each one of the memory cells having a selection transistor electrically connected to a respective one of the contacts;depositing a plurality of alternating layers of an insulating material and an electrode plate onto the semiconductor body, the alternating layers disposed one above the other;providing each one of the electrode plates with a lug projecting in a direction of a respective one of the contacts;etching holes extending through the plurality of alternating layers of an insulating material and an electrode plate;etching a plurality of holes through the plurality of alternating layers down to the main surface of the semiconductor body, each respective one of the holes being etched over a respective one of the contacts;forming a plurality of contact plugs by filling the plurality of holes with conductive material, each contact plug being formed to electrically connect the lug of a respective electrode plate to a respective one of the contacts, and each of the contact plugs being formed with an upper end;depositing an insulating layer on the upper ends of the plurality of contact plugs;etching a trench extending through the plurality of alternating layers and being substantially perpendicular to the main surface of the semiconductor body;isotropically etching away part of the insulating material of the plurality of alternating layers while leaving the plurality of contact plugs surrounded by the insulating material and allowing the electrode plates to project into the trench;conformally depositing a dielectric layer on the electrode plates; andfilling the trench with at least one electrically conductive material to form a second electrode.