Patent ID: 8996760
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. A processor, comprising: a memory decoder to monitor a predetermined memory block allocated to a device in a memory accessible by the device, the memory decoder to detect a posted write transaction to the predetermined memory block by the device and to generate an emulated message signaled interrupt (MSI) signal for an MSI in response to poses write transaction; an interrupt controller to receive the emulated MSI signal from the memory decoder and in response to the emulated MSI signal, to obtain an interrupt vector from the predetermined memory bock, without receiving an MSI request from the device; and an execution unit to execute an interrupt service routine (ISR) associated with the interrupt vector to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction.