Patent ID: 6027761
Filing Date: 2000-02-22
Classification: H01L,Y10T

Abstract:
A method for manufacturing a capacitor applied to a memory unit including a substrate forming thereon a dielectric layer, comprising steps of:(a) forming a sacrificial layer over said dielectric layer;(b) partially removing said sacrificial layer and said dielectric layer to form a contact window;(c) forming a first conducting layer over said sacrificial layer and in said contact window;(d) partially removing said first conducting layer and said sacrificial layer to expose a portion of said sacrificial layer and retain a T-shaped portion of said first conducting layer;(e) forming a second conducting layer over said T-shaped portion of said first conducting layer and said portion of said sacrificial layer;(f) executing an anisotropic etching process to partially remove said second conducting layer while retaining a portion of said second conducting layer alongside said portion of said first conducting layer and said portion of said sacrificial layer, said portion of said second conducting layer extending towards said dielectric layer;(g) removing said portion of said sacrificial layer to expose said dielectric layer;(h) forming a third conducting layer over surfaces of said portion of said first conducting layer, said second conducting layer, and said dielectric layer; and(i) partially removing said third conducting layer while retaining a portion of said third conducting layer under said portion of said first conducting layer and said second conducting layer and on said dielectric layer, wherein said portion of said first conducting layer, said second conducting layer, and said portion of said third conducting layer serve as a capacitor plate.