Patent ID: 6542984
Filing Date: 2003-04-01
Classification: G06F

Abstract:
A scheduler comprising:an instruction buffer configured to store a plurality of instruction operations; a dependency buffer configured to store indications of dependencies between the plurality of instruction operations, the indications capable of identifying a dependency chain corresponding to a first instruction operation of the plurality of instruction operations, wherein the dependency chain: (i) includes one or more additional instruction operations in the plurality of instruction operations, wherein each of the additional instruction operations is subsequent to the first instruction operation in program order and is directly or indirectly dependent on the first instruction operation; and (ii) excludes a second instruction operation that is subsequent to the first instruction operation in program order but is not dependent on the first instruction operation; an issue pick circuit configured to select the plurality of instruction operations for issue; and a control circuit coupled to receive a signal indicating that the first instruction operation is to be reissued, wherein the control circuit is configured to cause a reissue of the first instruction operation and the additional instruction operations in the dependency chain but not to cause a reissue of the second instruction operation responsive to the signal.