Patent ID: 8476123
Filing Date: 2013-07-02
Classification: H01L

Abstract:
1. A method for manufacturing a thin film transistor array panel, the method comprising: forming a gate line comprising a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a first amorphous silicon layer, a second amorphous silicon layer, a first metal layer, and a second metal layer on the gate insulating layer; forming a photoresist pattern having a first portion and a second portion on the second metal layer, the thickness of the second portion being greater than the thickness of the first portion; forming a second metal pattern and a first metal pattern by respectively etching the second metal layer and the first metal layer using the photoresist pattern as a mask; processing the first metal pattern with SF forming an amorphous silicon pattern and a semiconductor pattern by respectively etching the second amorphous silicon layer and the first amorphous silicon layer using the photoresist pattern as a mask; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern using the second portion as a mask; forming a lower layer of the data wire and an ohmic contact, respectively, by etching the first metal pattern and the amorphous silicon pattern using the second portion as a mask; forming a passivation layer comprising a contact hole on the upper layer after removing the second portion; and forming a pixel electrode on the passivation layer, the pixel electrode being connected to the upper layer through the contact hole.