Patent ID: 6268293
Filing Date: 2001-07-31
Classification: H01L

Abstract:
A damascene method of forming metal lines on an integrated circuit chip, said method comprising:a) forming a plurality of trenches in a dielectric layer on the surface of a semiconductor wafer by flowing a mixture of gasses at a rate of 2-30 sccm of C.sub.4 F.sub.8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar over the wafer surface;b) measuring trench uniformity across said semiconductor wafer which exceeds a maximum variation;c) adjusting the flow conditions of said gasses within the aforestated range of rates to optimize the rate of flow of said gasses to form said trenches within said maximum variation;d) re-measuring trench uniformity across said semiconductor wafer below said maximum variation; ande) filling said trenches with metal only when said trench uniformity is measured below said maximum variation.