Patent ID: 6521973
Filing Date: 2003-02-18
Classification: H01L

Abstract:
A semiconductor device comprising a semiconductor body in and on which a power transistor and a suppression diode are integrated, wherein the power transistor has a current path between first and second regions that are adjacent to respective front and back surfaces of the body and that are connected to respective front and back metallisations, the body is mounted on a terminal connection area of the device via the back metallisation, a base region of opposite conductivity type is present between the first and second regions and forms a parasitic diode as a p-n junction with an adjacent first part of the second region, which first part has a lower conductivity-type-determining dopant concentration than an underlying second part of the second region, the suppression diode is formed in series with the second region of the power transistor and adjacent to the back surface of the body by a diode junction that is present between the back metallisation and the second part of the second region and that opposes the p-n junction between the second region and the base region so as to suppress reverse current flow in the transistor, and the second part of the second region is sufficiently thick as to prevent minority charge carriers injected into the second region by the diode junction from reaching the p-n junction with the base region;wherein a semiconductor layer is included on the back surface of the body, between the back surface and the back metallisation, and wherein the semiconductor layer has adjacent to the diode junction a conductivity-type-determining dopant concentration that is lower than the conductivity-type-determining dopant concentration of the first conductivity type of the second part of the second region; and wherein a first windowed insulating layer is present between the semiconductor layer and the second region, a second windowed insulating layer is present between the semiconductor layer and the back metallisation, the windows in the first and second insulating layers are laterally offset with respect to each other, and a p-n junction within the semiconductor layer extends across the thickness of the semiconductor layer where insulated by the first and second insulating layers.