Patent ID: 7525161
Filing Date: 2009-04-28
Classification: H01L

Abstract:
1. A device structure, comprising: at least one NMOS device and at least one PMOS device, wherein said NMOS device and said PMOS device are having their corresponding channel regions hosted in NMOS and PMOS portions of a Si based layer, wherein said Si based layer is epitaxially disposed over a SiGe support layer, thereby having an interface with said SiGe support layer; a second Si based material epitaxially interfacing with said NMOS portion of said Si based layer on each side of said NMOS channel region, wherein a source and a drain of said NMOS device comprise at least a portion of said second Si based material, wherein said interfacing of said second Si based material with said Si based layer is substantially perpendicular to said interface of said Si based layer and said SiGe support layer, wherein said second Si based material penetrates through said Si based layer and is epitaxially interfacing with said SiGe support layer, wherein said second Si based material has lower Ge concentration than said SiGe support layer; a second SiGe material epitaxially interfacing with said PMOS portion of said Si based layer on each side of said PMOS channel region, wherein a source and a drain of said PMOS device comprise at least a portion of said second SiGe material, wherein said interfacing of said second SiGe material with said Si based layer is substantially perpendicular to said interface of said Si based layer and SiGe support layer, wherein said second SiGe material penetrates through said Si based layer and is epitaxially interfacing with said SiGe support layer, wherein said second SiGe material has higher Ge concentration than said SiGe support layer; and wherein said Si based layer is SiGe with a Ge concentration of less than about 20%.