Patent ID: 6826743
Filing Date: 2004-11-30
Classification: G03F

Abstract:
A wafer overlay correction method for an exposure process in a semiconductor fabricating stepper, comprising:measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper; calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots; and providing the calculated overlay error correction value to the stepper to control an exposure process of a subsequent wafer lot. wherein the overlay error correction value is calculated using the following set of equations: X(k)=X_stepper(k)âˆ’Xâ€”ffwd(k)âˆ’Xâ€”kla(k)âˆ’X_bias(k) X_bias(k)=X_stepper(m)âˆ’Xâ€”ffwd(m)âˆ’Xâ€”kla(m)âˆ’x(m) x(k)=f[x(kâˆ’1),x(kâˆ’2),x(kâˆ’3), . . . ,x(kâˆ’m)]X_stepper(k)=Xâ€”ffwd(k)+X_bias(k)+x(k) wherein X(k) is a current overlay alignment value; X_stepper(k) is an overlay error correction value; X_ffwd(k) is a reference value for wafer alignment; X_kla(k) is an overlay-measured value; x(k) is an estimated value in a variation of equipment through an empirical characterization of input changes; and X_bias(k) is a weighted average value of the latest ten lots.