Patent ID: 9111784
Filing Date: 2015-08-18
Classification: B82Y,H01L

Abstract:
1. An integrated circuit (IC) comprising: a substrate having a metal-oxide-semiconductor (MOS) region; first gate, source and drain regions of a first device in the MOS region, wherein the first gate region has a first length; a first nanowire set disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a first feature in the first source region and a second feature in the first drain region; second gate, source and drain regions of a second device in the MOS region, wherein the second gate region has a second length; and a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a third feature in the second source region and a fourth feature in the second drain region, wherein the first diameter is different from the second diameter when the first length is different from the second length.