Patent ID: 8872555
Filing Date: 2014-10-28
Classification: H03K,H03L

Abstract:
1. A power-on reset circuit, comprising: a first impedance device and a first switch device, each of which is connected in series with each other and coupled between a power node and a first node, wherein a control terminal of the first switch device is coupled to the power node; a first capacitor, coupled between the first node and a reference ground; a second switch device, coupled between the first node and a connection node, wherein a control terminal of the second switch device is coupled to the power node; a third switch device, coupled between the connection node and the reference ground, wherein a control terminal of the third switch device is coupled to the power node; a fourth switch device, coupled between a second node and the reference ground, wherein a control terminal of the fourth switch device is coupled to the connection node; a second impedance device, coupled between the power node and the second node; a second capacitor, coupled between the second node and the reference ground; and a control circuit, coupled between the second node and a reset input terminal of a circuit device; wherein when the power node is supplied with electric power, the first switch device and the third switch device are turned on and the second switch device and the fourth switch device are turned off to allow the second capacitor to be charged with the electric power of the power node through the second impedance device, and the electric power of the power node charges the second capacitor to a predetermined voltage value, the control circuit outputs a reset signal;