Patent ID: 6687068
Filing Date: 2004-02-03
Classification: G11B

Abstract:
An apparatus for reproducing data, said apparatus comprising;an automatic gain control circuit for retaining the amplitude of a read signal read from a data recording medium at a predetermined amplitude; a zero cross detector for detecting a first intersection of an output signal outputted from the automatic gain control circuit and a predetermined threshold level; a phase-locked loop circuit for defining time cells having a period determined by the frequency of the output signal; a binarization circuit for generating binary data based on presence or absence of the first intersection in each time cell; a decoder for decoding the binary data; a differentiating circuit for second-order differentiating the output signal outputted from the automatic gain control circuit; an arithmetic circuit for determining a time difference between a second intersection of the signal from the differentiating circuit and a zero level, and the first intersection; a comparison circuit for comparing the determined time difference with a predetermined time to obtain a comparison value; and means responsive to the comparison circuit for controlling the setting of a rate of convergence for an error between the amplitude of the output signal from the automatic gain control circuit and the predetermined amplitude, and the setting of a rate of convergence between the frequency determined by the period of the time cell defined by the phase-locked loop circuit and the frequency of the output signal from the automatic gain control circuit, said means for controlling including: means for detecting an occurrence of offset of a read signal based on a comparison value obtained by said comparison circuit, said means for detecting an occurrence of offset including: means for storing comparison values obtained in previous n comparisons, where n is an integer of 1 or more, by said comparison circuit; and means for checking the number of those comparisons out of (n+1) comparisons including a current comparison and previous n comparisons which indicate that said time difference is longer than said predetermined time; means for detecting a convergence of offset of a read signal based on the comparison value obtained by the comparison circuit; and means for giving an instruction to control respective rates of convergence for errors in said automatic gain control circuit and said phase-locked loop circuit upon detection of the occurrence or the convergence of offset.