Patent ID: 6065034
Filing Date: 2000-05-16
Classification: G06F

Abstract:
A method of sign extending an m bit operand comprising the steps:inverting the m.sup.th most significant bit of the m bit operand to generate a sign inverted m bit operand;inputting the sign inverted m bit operand into m least significant first inputs of an n bit adder;inputting a (n-m) bit operand into the (n-m) most significant first inputs of the n bit adder, wherein each bit of the (n-m) bit operand represents a logical one;inputting an n bit operand into the second n inputs of the n bit adder, wherein the (m).sup.th most significant bit of the n bit operand represents logical one, and wherein the (n-m) most significant bits and the (m-1) least significant bits of the n bit operand represent logical zero;wherein the sign inverted m bit operand, the (n-m) bit operand, and the n bit operand are inputted into the n bit adder in parallel;generating an n bit output operand at n outputs of the n bit adder in response to inputting the sign inverted m bit operand, the (n-m) bit operand, and the n bit operand into the n bit adder;wherein the m least significant bits of the output operand logically equal the m bit operand, respectively, and wherein each of the (n-m) most significant bits of the output operand equal the m.sup.th most significant bit of the m bit operand.