Patent ID: 6066552
Filing Date: 2000-05-23
Classification: H01L,Y10S

Abstract:
A method of forming plugs between multiple semiconductor surface structures on a substrate, comprising:forming a first opening in a first isolation layer on the multiple semiconductor surface structures, wherein forming the first opening includes exposing portions of the multiple semiconductor surface structures, and includes exposing portions of the substrate between the multiple surface structures;depositing a first conductive material in the first opening to cover the multiple semiconductor surface structures, wherein the first conductive material is planarized stopping on the first isolation layer;forming a second isolation layer across the first conductive material;forming a second opening in the first conductive material in a source region on the substrate, wherein forming the second opening includes exposing portions of an adjacent pair of the multiple semiconductor surface structures;forming spacers on interior walls of the second opening, wherein forming the spacers includes separating the first conductive material into an inner plug, isolated beneath and between the adjacent pair, and a pair of outer plugs, wherein the outer plugs also cover portions of the adjacent pair;forming a second conductive material in the second opening, whereby the second conductive material is isolated from the outer plugs by the spacersforming a third isolation layer across the second isolation layer across the multiple semiconductor surface structures; andforming a first contact opening in a drain region, wherein forming the contact opening exposes a portion of one of the pair of outer plugs.