Patent ID: 9103880
Filing Date: 2015-08-11
Classification: G01R

Abstract:
1. An integrated programmable logic circuit comprising: a plurality of programmable logic circuits having internal circuit nodes; a plurality of flip flops, each flip flop having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node; a probe-data line; an address circuit coupled to address lines for selecting one of the internal circuit nodes; a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line; a data input path to the asynchronous data input line of each flip flop; a write-probe data input path to the asynchronous data input line of each flip flop; a write-probe enable line; and selection circuitry, responsive to the address circuit and the write-probe enable line, selectively coupling one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.