Patent ID: 7808841
Filing Date: 2010-10-05
Classification: G11C

Abstract:
1. A data output circuit for a semiconductor memory apparatus, comprising: a driver control signal generating unit comprising a plurality of control signal generating units, each of which is configured to generate a driver unit control signal in response to a test signal during a test, and to generate the driver unit control signal according to whether or not a fuse is cut after the test is completed; a first driver comprising a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node; a signal combining unit configured to generate a first driver control signal in response to the driver unit control signal and an enable signal; and a second driver comprising a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal and to output the driven second data signal to the output node, the number of driver units being two or more times as much as the number of driver units in the first driver, wherein a voltage level on the output node is the voltage level of an output signal.