Patent ID: 6091088
Filing Date: 2000-07-18
Classification: H01L

Abstract:
A macro cell having at least one group of transistors disposed along a column direction comprising:a plurality of gate electrodes disposed along a row direction, transverse to the column direction, each gate electrode being oriented in the column direction and including a first end portion located at an upper end, a second end portion located at a lower end opposite the upper end, and an effective width portion connecting said first end portion to said second end portion; andrespective source-drain areas disposed between effective width portions of an adjacent pair of said gate electrodes, each source-drain area having, along the column direction, a contact area having a contact for connection to a first layer wiring and a non-contact area having no contact, one source-drain area having, at the first end portion, said contact area and, at the second portion, said non-contact area, another source-drain area having a non-contact area at the first end portion and a contact area at the second end portion, said effective width portion of said gate electrode being bent at a boundary between one of said contact areas and one of said non-contact areas, wherein said effective width portions of an adjacent pair of said gate electrodes, where one of said non-contact areas is interposed between said adjacent pair of said gate electrodes, are separated by a distance smaller than a distance between said effective width portions of said adjacent pair of said gate electrodes where said contact areas are interposed between said adjacent pair of said gate electrodes and the distance between said effective width portions of said adjacent pair of said gate electrodes where said non-contact area is interposed between said pair of adjacent gate electrodes is equal to the distance between said first end portions of said gate electrodes and the distance between said effective width portions of said adjacent pair of said gate electrodes where said non-contact area is interposed between said pair of adjacent gate electrode is equal to a distance between said second end portions of said gate electrodes.