Patent ID: 6687769
Filing Date: 2004-02-03
Classification: G06F,Y02D

Abstract:
A serial peripheral interface device configured for providing a high performance buffering scheme for transmitting data to and receiving data from another peripheral device, said serial peripheral interface device comprising:an input/output control device for interfacing with the other peripheral device; and a single buffer having a transmit shift register, a receive shift register, a data register and a queuing arrangement, wherein said queuing arrangement comprises a pointer/counter arrangement and is configured to provide for the receiving of new data in said data register at substantially the same time as stored data is transmitted from said data register, wherein said queuing arrangement comprises: a write pointer configured to indicate a location in said single buffer where a CPU can write data to be transmitted; a read pointer configured to identify a location in said single buffer where any received data can be stored for reading by the CPU; and a shift pointer configured to identify a location for data to be transmitted and a location where the received data will be stored after shifting of any registers is completed.