Patent ID: 8853084
Filing Date: 2014-10-07
Classification: H01L

Abstract:
1. A method to provide an intermediate semiconductor device structure, comprising: providing a wafer comprising first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non-planar wafer surface topography due at least to a presence of the first dummy gate plugs, the wafer being comprised of a plurality of fin structures formed from a patterned portion of a semiconductor on insulator layer that is disposed upon and in contact with a surface of a dielectric layer, the plurality of fin structures each having a top surface disposed at a height (h) above the surface of the dielectric layer, where an individual one of the first dummy gate plugs is disposed upon the top surface of one of the plurality of fin structures, where the second dummy gate plugs terminate upon the surface of the dielectric layer, and where a top surface of the individual one of the first dummy gate plugs is disposed above a top surface of the second dummy gate plugs by at least the height (h); depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.