Patent ID: 6557062
Filing Date: 2003-04-29
Classification: G08C

Abstract:
A control bus for providing a communication interconnect path between a bus master and one or more bus slaves, wherein the bus master is coupled to a processor and each bus slave is coupled to a Radio Frequency (RF) device that operates without a free-running clock, the control bus comprising:a bi-directional data line coupled to the bus master and to the one or more bus slaves; a first clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the bus master when transmitting serial data to or receiving serial data from the one or more bus slaves via said bi-directional data line; and a second clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the one or more bus slaves when transmitting serial data to the bus master via said bi-directional data line.