Patent ID: 8429319
Filing Date: 2013-04-23
Classification: G11C

Abstract:
1. A multi-port memory device, comprising: a plurality of serial input/output (I/O) data pads; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for receiving first signals outputted from the ports, and transferring the first signals to the banks; a plurality of second data buses for receiving second signals outputted from the banks, and transferring the second signals to the ports; a plurality of switching units for connecting the first data buses with the second data buses one to one in response to a mode enable signal, to transfer the first signals outputted from each of the plurality of ports to the same respective port of origin via the connected first and second data buses, or to transfer the first signals outputted from the ports to the banks via the first data buses; and a plurality of output drivers configured to interrupt the transferring of the second signals from the banks to the second data buses in response to the mode enable signal, wherein each of the output drivers includes: a first inverter for inverting a device enable signal for enabling the multi-port memory device; a first ate performing a NOR operation on an output of the first inverter and the mode enable signal; a second inverter for inverting an output of the first logic gate; a third inserter for inverting cell data outputted from a corresponding one of the banks; a second logic gate for performing an OR operation on outputs of the second and third inverters; a pull-up transistor having a gate receiving an output of the second logic gate and a source-drain path between a source voltage terminal and an output node; a third logic gate for performing an AND operation on outputs of the first logic gate and the third inverter; and a pull-down transistor having a gate receiving an output of the third logic gate and a source-drain path between a ground voltage terminal and the output node.