Patent ID: 7755402
Filing Date: 2010-07-13
Classification: G06F,G11C

Abstract:
1. An apparatus, comprising: a first register to store a first delay value and a second register to store a second delay value; a first programmable delay circuit to position an edge of a first delayed data strobe signal corresponding to a first data strobe signal to substantially the middle of a valid data period of a data signal based at least in part on said first delay value, the first delayed data strobe signal to indicate latch timing for said data signal, wherein said valid data period excludes a falling edge and a rising edge of said data signal; a second programmable delay circuit to position an edge of a second delayed data strobe signal corresponding to a second data strobe signal to substantially the middle of said valid data period of said data signal based at least in part on said second delay value, the second delayed data strobe signal to further indicate latch timing for the data signal; a third delay circuit to position an edge of a third delayed data strobe signal corresponding to a complement of the first data strobe signal; and a fourth delay circuit to position an edge of a fourth delayed data strobe signal corresponding to a complement of the second data strobe signal.