Patent ID: 6754881
Filing Date: 2004-06-22
Classification: G06F

Abstract:
A network processor comprising:a plurality of standard cells, the plurality of standard cells comprising common logic; a plurality of FPGA cells, the plurality of FPGA cells comprising high risk logic; and a processor local bus (PLB) and two on-chip peripheral buses (OPBs) coupled to a portion of the standard cells and portion of the FPGA cells, wherein the FPGA cells coupled to the PLB comprise an accelerator function and a PLB master/slave function; wherein the FPGA cells coupled to one of the two OPBs are media interfaces; wherein the FPGA cells coupled to the other of the two OPBs are a GPIO preprocessor function and an OPB master/slave function; wherein the plurality of cells each can provide a specified function based upon field programming techniques to allow for customization of the network processor.