Patent ID: 9165105
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A computer-implemented method for design rule checking (DRC) during a static timing analysis (STA) of an integrated circuit (IC) design, comprising: analyzing cells with distorted waveforms in a cell library and generating both library-based waveforms and simulated waveforms for each cell type according to a plurality of parameters for said each cell type; constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps a waveform error to a hold time constraint error of each cell type in the cell library and is saved in a memory; identifying one or more cells in the IC design as risky for timing constraint violation(s) during the STA of the IC design according to the lookup table and; re-optimizing the identified risky cell(s) to reduce risk for the timing constraint violation(s) of the IC design.