Patent ID: 8597960
Filing Date: 2013-12-03
Classification: H01L

Abstract:
1. A method of forming a stacked semiconductor chip comprising: providing a first unit chip containing a first instance of a first chip component, a first instance of a second chip component, and a first metal interconnect structure, wherein said first chip component is a processor core, an execution unit of a processor core, or a functional logic unit of a semiconductor chip; providing a second unit chip containing a second instance of said first chip component, a second instance of said second chip component, and a second metal interconnect structure; and forming a first logically connected functional block containing said first instance of said first chip component and said second instance of said first chip component, and a second logically connected functional block containing said first instance of said second chip component and said second instance of said second chip component by stacking said first unit chip and said second unit chip, wherein a design layout of said second unit chip is substantially a mirror image of said first unit chip, wherein said second instance of said first chip component overlies said first instance of said first chip component and said second unit chip overlies said first unit chip, and said first unit chip and said second unit chip are bonded face to face, whereby a face of said first instance of said first chip component contacts a face of said second instance of said first chip component, and said first metal interconnect structure is in direct contact with said second metal interconnect structure, and wherein a selection circuit located in one of said first and second unit chips activates one of said first and second instances of said first chip component to provide functionality that is the same as functionality of a fully functional instance of said first chip component, and a control circuit located in one of said first and second unit chips determines, and activates, total available functionality of said first and second instances of said second chip component, wherein said total available functionality is enhanced over functionally of a fully functional instance of said second chip component, and is less than twice said functionality of said fully functional instance of said second chip component.