Patent ID: 6212621
Filing Date: 2001-04-03
Classification: G06F

Abstract:
A microprocessor configured to decode instructions out of program order comprising:an instruction cache configured to store instruction bytes, wherein said instruction cache is configured to receive a first fetch address and in response output a first group of instruction bytes corresponding to said first fetch address;a tag generator coupled to said instruction cache, wherein said tag generator is configured to generate a first fetch tag for said first group of instructions bytes; anda first decode unit coupled to said tag generator and said instruction cache, wherein said first decode unit is configured to receive said first fetch tag and said first group of instruction bytes, wherein said first decode unit is configured to decode said first group of instruction bytes into one or more instructions, wherein said first decode unit is configured to generate an instruction tag for each instruction, and wherein said instruction tags are indicative of the program order of said one or more instructions.