Patent ID: 6163192
Filing Date: 2000-12-19
Classification: H03K

Abstract:
A negative edge triggered flip-flop, comprising:a first set of nodes receiving data input signals;a second set of nodes receiving select input signals for selecting one data input signal of said data input signals as a selected data input signal;a clock node receiving a clock signal having a positive edge and a negative edge;an output node;a header circuit connected to said second set of nodes and to said clock node, said header circuit integrating said clock signal with said select input signals to generate at least one control signal; anda pulse generator circuit connected to said first set of nodes, said header circuit and said output node, said pulse generator circuit generating an output pulse on said output node in response to said at least one control signal and said selected data input signal, such that said output pulse is generated in response to said negative edge of said clock signal.