Patent ID: 6603413
Filing Date: 2003-08-05
Classification: H03M,H04N

Abstract:
A variable-length decoding apparatus for decoding encoded data, comprising:shift means for shifting out a code word and an additional bit corresponding to the code word of input encoded data for each cycle; a symbol memory for storing decoded data corresponding to a plurality of N code words contained in the input encoded data; first decode processing means for generating an address of said symbol memory, a code length, and an additional bit length for each of Nt code words fewer than the N code words of the code words input from said shift means; second decode processing means for generating a code length and an address of said symbol memory for each of the N code words; address select means for selecting one of the two addresses of said symbol memory input from said first and second decode processing means; first additional bit processing means for shifting bits of the output from said shift means to the left by the code length input from one of said first and second decode processing means; second additional bit processing means for shifting bits of the output from said first additional it processing means to the right by an amount corresponding to symbol data output from said symbol memory; and operation control means for outputting a shift amount to said shift means.