Patent ID: 6233641
Filing Date: 2001-05-15
Classification: G06F

Abstract:
A routing circuit for interconnecting a primary computer expansion bus and first and second secondary computer expansion busses for forwarding commands between the primary and secondary computer expansion busses, each command having an address, comprisinga multi-way switch interconnecting the primary bus and first and second secondary busses,a memory storing entries mapping each bus to at least one address range, anda control circuit, the control circuit controlling the multi-way switch to forward commands between the primary and secondary busses in response to the address of the command and entries stored in the memory, the control circuit:controlling the multi-way switch to forward a command received from the primary bus having an address within an address range mapped to a secondary bus, to that secondary bus,controlling the multi-way switch to forward a command received from a secondary bus having an address within an address range mapped to the primary bus, to the primary bus, andcontrolling the multi-way switch to forward a command received from the first secondary bus having an address within an address range mapped to the second secondary bus, to the second secondary bus, without use of the primary bus;whereby traffic and latency on the primary bus due to commands sent from one secondary bus to another, is reduced.