Patent ID: 8411509
Filing Date: 2013-04-02
Classification: G11C

Abstract:
1. A memory, comprising: a cell array, comprising a plurality of memory cell rows; a first word line driver, connected to a first operational voltage and receiving a first control signal; a first word line, comprising a start terminal directly connected to an output terminal of the first word line driver, wherein the first word line is electrically coupled to one of the memory cell rows and the first word line has an end terminal, the start terminal and the end terminal are not further connected to any other word line for selecting memory cells; and a first switch, comprising a first terminal directly connected to the end terminal of the first word line and a second terminal receiving the first operational voltage via a connection line, wherein the connection line is directly connected to a terminal of the first word line driver which receives the first operational voltage; wherein when the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage; and wherein when the first word line driver is controlled by the first control signal to stop charging up the first word line, the first switch is turned off such that the start terminal of the first word line is connected to ground through the first word line driver while the end terminal of the first word line is connected to ground only through the start terminal of the first word line.