Patent ID: 6133139
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A method of forming multilevel interconnection lines and via-plugs of high conductivity metallurgy on top of a planarized substrate, said method comprising the steps of:(a) on a substrate having at least one first electrically conductive feature surrounded by at least one layer of a first insulator, selectively removing a portion of said first insulator layer and exposing a portion of said first conductive feature,(b) depositing at least one second layer of insulation over said exposed portion of said first conductive feature and said first insulator layer,(c) selectively removing said second layer of insulation such that said exposed portion of said first conductive feature is again exposed and is substantially coplanar with said second layer of insulation,(d) depositing at least one third layer of insulation over said first conductive feature and said second insulation layer,(e) depositing at least one fourth layer of insulation over said third layer of insulation,(f) forming at least one first blind hole in said third and said fourth layer of insulation such that at least a portion of the surface of said first electrically conductive feature is exposed,(g) depositing at least one second electrically conductive feature in said at least one first blind hole, such that at least a portion of said second feature is in direct contact with at least a portion of said first feature,(h) depositing at least one fifth layer of insulation over said second electrically conductive feature and said fourth insulation layer,(i) forming at least one second blind hole in said fifth layer of insulation such that at least a portion of the surface of said second electrically conductive feature is exposed,(j) depositing at least one third electrically conductive feature in said at least one second blind hole, such that at least a portion of said third feature is in direct contact with at least a portion of said second feature, and thereby forming said multilevel interconnection lines and via-plugs of high conductivity metallurgy on top of a planarized substrate.