Patent ID: 9087836
Filing Date: 2015-07-21
Classification: H01L

Abstract:
1. A semiconductor structure, comprising: a conditioned semiconductor substrate, conditioned from a semiconductor substrate having a rough surface, obtained from a chemical mechanical polishing process in removing an oxide layer from the semiconductor substrate, the conditioned semiconductor substrate having a significantly smooth surface from a thermal annealing process to the rough surface using an inert gas consisting of argon, helium, and neon as a thermal annealing protective gas; a gate structure formed on the conditioned semiconductor substrate, wherein the gate structure includes: an insulating layer grown from the conditioned semiconductor substrate having the significantly smooth surface, wherein the insulating layer has reduced deformation or defects compared with an insulating layer formed on the semiconductor substrate having the rough surface, a high-K gate dielectric layer disposed on the insulating layer, a protective layer disposed on the high-K gate dielectric layer, wherein the protective layer consists of nitride thallium, nitride tungsten, and aluminum oxide, and is different from the high-K gate dielectric layer, and a gate electrode layer disposed on the protective layer; sidewalls covering sides of the gate structure; and source and drain regions formed in the conditioned semiconductor substrate on both adjacent sides of the gate structure.