Patent ID: 7064009
Filing Date: 2006-06-20
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor package, comprising the steps of: a) providing a substrate which has at least one land defining opposed top and bottom land surfaces, and a plurality of lead fingers disposed in spaced relation to the land, each of the lead fingers defining opposed top and bottom lead surfaces and an outer end; b) providing a semiconductor chip which has an active surface defining a central region and a peripheral region, and a plurality of connection pads disposed on the central and peripheral regions of the active surface; c) attaching the semiconductor chip to the substrate such that at least one of the connection pads is positioned over and in electrical communication with the land, and at least one of the connection pads is positioned over and in electrical communication with at least one of the lead fingers; and d) at least partially encapsulating the substrate and the semiconductor chip with a package body such that the bottom lead surfaces of the lead fingers are each substantially flush with a bottom surface of the body, and the outer end of each of the lead fingers is substantially flush with a respective one of multiple side surfaces defined by the body.