Patent ID: 6740560
Filing Date: 2004-05-25
Classification: H01L

Abstract:
A procedure for the manufacture or a bi-polar transistor, said procedure comprising the steps of:producing structured regions consisting of a collector region and an insulation region that surrounds the collector region, on a monocrystal substrate layer; producing a base layer and, by means of epitaxy, a cap layer over the collector region; depositing an insulation layer is deposited over the cap layer, the insulation layer being opened in an area of an effective emitter zone; and depositing and structuring a poly-Si or an &agr;-Si layer over the opened insulation layer for use as an emitter-doping agent source and as a contact layer; wherein, before the diffusion from the emitter-doping agent source, a doping profile is introduced into the cap layer, and the profile is low-doped on the base side with a maximum concentration of 5Ã—1016 cmâˆ’3 and highly doped on the emitter side thereof, and wherein the low-doped region of the cap layer has a thickness between 20 nm and 70 nm.