Patent ID: 6440289
Filing Date: 2002-08-27
Classification: C25D,H01L

Abstract:
A method of manufacturing a semiconductor device, comprising the steps of:providing a semiconductor with a dielectric layer formed thereon, wherein said dielectric layer overlays a region on said semiconductor; forming an opening in said dielectric layer, said opening defined by sidewalls of said dielectric layer and a bottom exposing a portion of said region on said semiconductor; depositing an initially deposited copper seed layer by a non-electrochemical deposition process over said dielectric layer and in said opening, including along said walls, said initially deposited copper seed layer formed to a thickness insufficient to fill said opening; depositing a secondarily deposited copper seed layer by an electrochemical deposition process over said initially deposited copper seed layer, said depositing performed initially at a very low rate and increased to a low rate, wherein plating at the very low deposition rate is continued until under a few hundred angstroms of said copper seed layer have been deposited and plating at the low rate is continued until the copper deposited on the sidewalls of said opening meets copper deposited on the bottom; and depositing copper material in contact with said secondarily deposited seed layer by a third process to substantially fill said opening.