Patent ID: 6816399
Filing Date: 2004-11-09
Classification: H01L

Abstract:
A semiconductor memory device comprising:a memory cell block which includes series connected memory cells each having a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain; a plurality of gate lines connected to gates of the cell transistors of the memory cell block, the gate lines having a width and being arranged at intervals; and a plurality of branch lines formed of a layer different from a layer of the gate lines, arranged parallel to the gate lines, and each connected to a corresponding one of the gate lines, the branch lines having a width and being arranged at intervals, a sum of the width of the branch lines and an interval between each pair of adjacent ones of the branch lines differing from a sum of the width of the gate lines and an interval between each pair of adjacent ones of the gate lines.