Patent ID: 8789004
Filing Date: 2014-07-22
Classification: G06F

Abstract:
1. A method of optimizing timing of an electronic design, the method comprising: receiving an electronic design comprising a plurality of connected standard cells; generating a timing report, using a processor, for the electronic design, wherein the timing report comprises one or more failed-timing paths and each failed-timing path comprises a plurality of cells; generating a megacell for said each failed-timing path, wherein the megacell and the failed-timing path perform a same function; determining a critical transistor count for the megacell, wherein the critical transistor count for the megacell includes at least a megacell stack number count; determining a critical transistor count for the failed-timing path, wherein the critical transistor count for the failed-timing path includes at least a failed-timing path stack number count; determining whether the megacell optimizes the failed-timing path using an optimizing constraint, wherein the optimizing constraint comprises a minimum reduction of the critical transistor count from the failed-timing path to the megacell, and a specified difference in the megacell stack number count and the failed-timing path stack number count; replacing the failed-timing path with the megacell when the megacell optimizes the failed-timing path, and, generating a violation-free layout for the megacell using a megacell netlist.