Patent ID: 7319607
Filing Date: 2008-01-15
Classification: G11C

Abstract:
1. A ferroelectric memory, comprising: a memory cell array having complementary first and second bit lines, a plurality of sets of a word line and a plate line provided to intersect the bit lines, and a ferroelectric capacitor connected between the first and second bit lines and a plate line via a transistor which is controlled to be turn on and off by a corresponding word line; a reset circuit which connects the first and second bit lines to ground potential while an equalizing signal is being applied; a precharge circuit which connects the first and second bit lines to a power supply potential while a precharge signal is being applied; a sense amp which amplifies the potential difference between the first and second bit lines to output signals at complementary first and second logic levels to the first and second bit lines, while an enable signal is being applied; driving control means which drives a relevant plate line according to an applied address signal when read or write access to the memory cell array is performed, and drives the corresponding word line after a predetermined time has elapsed; and timing control means which outputs the equalizing signal when there is no access, outputs the precharge signal while halting the equalizing signal when access is started, halts the precharge signal before the predetermined time elapses, outputs the equalizing signal with a predetermined pulse width after a fixed time has elapsed from the start of driving of the word line, and outputs the enable signal after the equalizing signal is halted.