Patent ID: 7656733
Filing Date: 2010-02-02
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines; a plurality of complementary bit lines; a plurality of static memory cells capable of holding data, provided at the intersections of the word lines and the complementary bit lines, each memory cell comprising a plurality of transistors interconnected; a plurality of first dummy cells, each comprising a plurality of transistors which are interconnected differently from the interconnections of the transistors in the static memory cells; a write dummy bit section in which a first dummy line and a second dummy line corresponding to the complementary bit lines are coupled to the first dummy cells, one voltage level is input to the first dummy line through MOSFETs in relation to write signal inputs to the static memory cells, the second dummy line precharged at the other voltage level through a write current path of the first dummy cells senses and outputs a signal change in accordance with the one voltage level input from the first dummy line; and a timing control circuit that generates a timing signal to deselect a word line selected by an output signal from the write dummy bit section.