Patent ID: 7002325
Filing Date: 2006-02-21
Classification: H02J,H02M

Abstract:
1. A clocked cascadable power regulator, comprising: synchronization logic that receives a clock signal and that asserts a digital output signal synchronized with said clock signal in response to assertion of a digital input signal; and PWM control logic that controls each PWM cycle in response to said digital input signal and an output control condition; and wherein said PWM control logic comprises PWM logic that initiates a PWM cycle in response to said digital input signal and that terminates said PWM cycle in response to a reset signal; and feedback sense logic, coupled to said PWM logic, that asserts said reset signal when said output control condition is met; and wherein said PWM control logic comprises a latch that sets in response to said digital input signal and that resets in response to said reset signal; gate control logic, coupled to said latch, that provides at least one PWM activation signal; and at least one driver amplifier, each responsive to said at least one PWM activation signal; and wherein said feedback sense logic comprises a sense amplifier that senses an output current condition and that asserts a sense signal; and a comparator that compares said sense signal with a feedback reference signal to determine said output control condition.