Patent ID: 7313741
Filing Date: 2007-12-25
Classification: G11C

Abstract:
1. An integrated semiconductor memory, comprising: a memory cell array including first and second memory cells configured to store first and second data records, respectively, the first data record having at least one datum with a first or second data value stored in the first memory cells, and the second data record having at least one datum with the first or second data value stored in the second memory cells; a combination circuit configured to generate a third data record from a combination of at least the first and second data records, the third data record having at least one datum with the first or second data value, wherein the combination circuit comprises: a first logic gate that generates a first output data record from the first data record and a fourth data record such that values of the first output data record match values of the second data record under error-free conditions; a second logic gate that generates a second output data record from the second data record and the first output data record, wherein the second output data record has a first value in response to the first output data record matching the second data record and has a second value in response to the first output data record differing from the second data record; a multiplexer configured to multiplex data of the second output data record to a plurality of multiplexer outputs; and a logic circuit including at least one logic gate that produces the third data record from data received from the multiplexer outputs; and at least one output terminal configured to receive the third data record from the combination circuit.