Patent ID: 6128246
Filing Date: 2000-10-03
Classification: G11C

Abstract:
A semiconductor memory device comprising:a plurality of word lines;a plurality of bit lines;a plurality of memory cells, each of said memory cells being coupled to a corresponding one of said word lines and being coupled to a corresponding one of said bit lines;a first node supplied with a first voltage level;a second node supplied with a second voltage level;a third node;a plurality of decoders, each of which is coupled among said second node, said third node, and a corresponding one of said word lines, and each of which selectively couples either one of said second node and said third node to said corresponding word line in response to an address signal;a write recovery signal generating circuit that generates a write recovery signal having an inactive state during a first time period at a beginning of a data write cycle, an active state during a second time period at an end of the data write cycle, and the inactive state during a third time period just after the second time period;a first voltage signal supply circuit, coupled to said first node and said third node, that couples said first node to said third node in response to the write recovery signal having the inactive state; anda second voltage signal supply circuit, coupled to said second node and said word lines, that couples said second node to said word lines according to the write recovery signal having the active state.