Patent ID: 6408363
Filing Date: 2002-06-18
Classification: G06F,Y02D

Abstract:
An apparatus for minimizing cache coherency check latency in an out of order instruction execution system having a plurality of processors, comprising:at least one cache coherency check mechanism associated with a first one of said plurality of processors, said at least one cache coherency check mechanism being configured to output a presence signal indicating that a first data line being requested by a second one of said plurality of processors is present in a cache memory associated with said first one of said plurality of processors; at least one pre-flush slot configured to, upon receipt of said presence signal, determine at least one additional data line to be pre-flushed from said cache memory associated with said first one of said plurality of processors to said second one of said plurality of processors, and a logic associated with said at least one pre-flush slot, said logic configured to provide an indication whether said at least one additional data line is already being flushed from said cache memory.