Patent ID: 6740937
Filing Date: 2004-05-25
Classification: H01L,H03K,Y10S

Abstract:
A semiconductor integrated circuit of a gate array having a plurality of basic cells arranged in an array, each of the basic cells comprising:first and second P-channel MOS transistors; and first and second N-channel MOS transistors, wherein said second P-channel MOS transistor and said first P-channel MOS transistor are juxtaposed, said second N-channel MOS transistor and said first N-channel MOS transistor are juxtaposed, gate electrodes of each of said transistors are parallel to each other, the gate electrode of said first P-channel MOS transistor and the gate electrode of said first N-channel MOS transistor are provided and connected together along a first straight line, the gate electrode of said second P-channel MOS transistor and the gate electrode of said second N-channel MOS transistor are provided and connected together along a second straight line, and a gate width W1 of said first P-channel MOS transistor and a gate width W4 of said first N-channel MOS transistor are set to a given ratio such that W1:W4=2:1.