Patent ID: 6650570
Filing Date: 2003-11-18
Classification: G11C

Abstract:
A non-volatile semiconductor memory device comprising:a memory cell array having a plurality of non-volatile memory cells; word lines, bit lines and source lines connected to said memory cells; a row decoder configured to select one of said word lines; a column decoder configured to select one of said bit lines; at least one reference cell; a read circuit configured to read data by applying a first voltage to said one of said word lines to compare a current flowing through said one of said bit lines with a current flowing through said reference cell; an erase circuit configured to erase said data by applying a voltage to at least two selected from said word lines, said bit lines, said source lines and a semiconductor region including said memory cells; first and second regulators; and an erase verify circuit configured to detect whether erasing has finished by applying an output voltage of said first regulator to said word lines of said memory cells to be erased, while applying an output voltage of said second regulator to a word line of said reference cell, thereby comparing a cell current of selected one of said memory cells with a cell current of said reference cell.