Patent ID: 7446003
Filing Date: 2008-11-04
Classification: H01L

Abstract:
1. A process for manufacturing a shielded power MOS lateral transistor on a semiconductor substrate which comprises a semiconductor region of a first type of conductivity, the process comprising the following steps of: forming, on said semiconductor region, at least one lateral MOS transistor which comprises a gate electrode projecting from said semiconductor region and insulated from said semiconductor region by an insulating layer, a source region comprising a first highly doped portion of a second type of conductivity aligned with said gate electrode and a drain region comprising a first lightly doped portion aligned with said gate electrode and a second highly doped portion included in said first lightly doped portion, both of the second type of conductivity; forming, on at least said first lightly doped portion, a protective layer of a first type of material; forming, on said whole lateral MOS transistor, a dielectric layer of a second type of material that is selectively etchable with respect to said first type of material; forming, in a single step, in said dielectric layer: filling in said first, second and third openings by a conductive layer so as to form respective drain and source contacts electrically connected respectively to said first and second highly doped portions, and one electrical shield substantially aligned with said protective layer.