Patent ID: 6524926
Filing Date: 2003-02-25
Classification: H01L

Abstract:
A method of forming a vertical metal-insulator-metal (VMIM) capacitor at least partially in an interlayer dielectric (ILD) layer between horizontal first and second metal interconnect layers in an integrated circuit (IC), the first metal interconnect layer being separated from a substrate of the IC by at least one dielectric layer, the method comprising the steps of:forming the second metal interconnect layer in a top side of the ILD layer; forming a first vertical capacitor plate of the VMIM capacitor at least partially in the second metal interconnect layer; forming a capacitor dielectric material onto a vertical sidewall of the first vertical capacitor plate; forming a second vertical capacitor plate adjacent to the capacitor dielectric material; forming the second metal interconnect layer and the first and second vertical capacitor plates by damascene metallization steps; and forming the second metal interconnect layer and the first vertical capacitor plate substantially concurrently.