Patent ID: 8952739
Filing Date: 2015-02-10
Classification: G01R,G11C,H03K

Abstract:
1. An input circuit comprising: a combination circuit that generates first and second internal signals according to first and second input signals, respectively; a first master latch circuit that selectively captures and holds a scan-in signal and the first internal signal generated by the combination circuit, and generates a first output signal and a first intermediate signal based on the signals thus captured and held; and a first slave latch circuit that selectively captures and holds the first intermediate signal generated by the first master latch circuit and the second internal signal generated by the combination circuit, and generates a second output signal and a scan-out signal based on the signals thus captured and held, wherein: the first master latch circuit captures the scan-in signal according to a first clock signal, the first master latch circuit captures the first internal signal according to a second clock signal, the first slave latch circuit captures the first intermediate signal according to a third clock signal, the first slave latch circuit captures the second internal signal according to a fourth clock signal, and the second clock signal and the fourth clock are different clocks.