Patent ID: 6658636
Filing Date: 2003-12-02
Classification: G06F

Abstract:
A method comprising:receiving a first and a second netlist of a first and a second function block of a circuit design; correspondingly partitioning said first and second netlists of said first and second function blocks into at least a first and a second partition, and a third and a fourth partition respectively for correspondingly determining placement of constituting elements of said first and second netlists on logic devices, with the first partition having a majority of the constituting elements of said first netlist, the second partition having a minority of the constituting elements of said first netlist, the third partition having a majority of the constituting elements of said second netlist, and the fourth partition having a minority of the constituting elements of said second netlist; merging said second and fourth partitions having minorities of the constituting elements of said first and second netlists to form a first composite partition of minority constituting elements of said first and second netlists of said first and second function blocks; and partitioning said first composite partition for jointly determining placement of these minority constituting elements of said first and second netlists of said first and second function blocks on logic devices.