Patent ID: 6493266
Filing Date: 2002-12-10
Classification: G11C

Abstract:
A system for preventing erased memory cells from exhibiting an erased cell threshold voltage below a predetermined level, comprising:a soft program control circuit configured to generate a soft program voltage pulse, a soft program core cell verification voltage, and a reference cell verification voltage having a value which is different from the soft program core cell verification voltage; a flash memory array of core cells operably coupled to core address control circuitry, bit/column control circuitry and word/row control circuitry, wherein the flash memory array is operable to generate a core cell verification current for a selected erased core cell, and wherein the soft program control circuit is operable to selectively apply the soft program voltage pulse to only the one selected core cell which is determined to have an erased core cell threshold voltage below the predetermined voltage; and a soft program verify control circuit configured to generate a reference current using the reference cell verification voltage, and compare the core cell verification current to the reference cell current.