Patent ID: 8935586
Filing Date: 2015-01-13
Classification: G01R

Abstract:
1. An integrated circuit structure comprising: a test controller; built-in self-test (BIST) controllers operatively connected to said test controller; and BIST engines operatively connected to said BIST controllers, said BIST engines being grouped into BIST domains, each BIST controller of said BIST controllers being connected to a single BIST domain of said BIST domains, each said BIST controller comprising: said BIST controllers comprising at least two BIST controllers connected to at least two BIST domains, respectively, and comprising corresponding registers containing different BIST controller-specific start count values, said test controller providing a start command simultaneously to all of said BIST controllers, said BIST controllers receiving said start command and, in response to said start command, simultaneously beginning countdowns, said countdowns being performed by said counter in each said BIST controller using said BIST controller-specific start count value contained in said register such that said countdowns differ in said at least two BIST controllers comprising said corresponding registers containing said different BIST controller-specific start count values, and each said BIST controller starting a test procedure in a corresponding BIST domain upon completion of a countdown by said BIST controller such that test procedures start at different times in said at least two BIST domains based on said different BIST controller-specific start count values.