Patent ID: 6051121
Filing Date: 2000-04-18
Classification: C23C,H01J

Abstract:
An apparatus for cleaning a surface on an in-process integrated circuit wafer, the apparatus comprising:a PVD deposition chamber;a target composed of a conducting material disposed in the PVD deposition chamber;a collimator disposed in the PVD deposition chamber;a wafer holder disposed in the PVD deposition chamber; andan electrical circuit including a first connection scheme, a second connection scheme, and a third connection scheme, wherein:said first connection scheme is in electrical communication with each of the target, the collimator, and the wafer holder;the first connection scheme is for applying a voltage bias to the target and to the wafer holder;said second connection scheme is in electrical communication with the first connection scheme and is for electrically isolating the collimator from the first connection scheme; andsaid third connection scheme is situated in the PVD deposition chamber and is for controlling the location of an ionization plasma with respect to the target and the wafer holder.