Patent ID: 8527915
Filing Date: 2013-09-03
Classification: G06F,H01L

Abstract:
1. A method comprising: receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying, by using a computer, an area of the integrated circuit that includes the doped feature layout for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout, wherein the portion of the doped feature layout defines a critical dimension of a resist layer used to form a doped region of the integrated circuit; wherein the modifying the portion of the doped feature layout that corresponds with the identified area of the integrated circuit is performed during an optical proximity correction process of the mask preparation process and modifying the portion of the doped feature layout includes modifying to reducing the critical dimension; wherein the identifying the area of the integrated circuit for device performance modification includes identifying a transistor for reducing a leakage current; and forming a doped region in a substrate of the integrated circuit using the mask fabricated according to the modified doped feature layout.