Patent ID: 6667214
Filing Date: 2003-12-23
Classification: H01L

Abstract:
A method for manufacturing a non-volatile semiconductor memory device including a first memory element in a first memory element region and a second memory element in a second memory element region, the method comprising:providing a semiconductor substrate including a first memory element region and the second memory element region; forming a third impurity diffusion layer in each of the first and second memory element regions, wherein an impurity concentration of the third impurity diffusion layer in the first memory element region is different from an impurity concentration of the third impurity diffusion layer in the second memory element region; forming a gate dielectric layer, a floating gate and a selective oxide dielectric layer in each of the first memory element region and the second memory element region; depositing a dielectric layer and depositing a conduction layer and patterning the dielectric layer and the conduction layer to form an intermediate dielectric layer and a control gate commonly shared by the first memory element and the second memory element; and forming first and second impurity diffusion layers in selected regions of the semiconductor substrate.