Patent ID: 7405958
Filing Date: 2008-07-29
Classification: G11C

Abstract:
1. A semiconductor memory device, comprising: a selective transistor (STr) type magnetic memory cell array including a plurality of STr type magnetic memory cells, at least one of said cells being arranged between a first bit line and a first word line and having a selective transistor for selectively reading out a data stored in the at least one Str type magnetic memory cell; a cross-point (XP) type magnetic memory cell array, said XP type magnetic memory cell array including a plurality of XP type magnetic memory cells, at least one of said XP type magnetic memory cells being arranged between a second bit line and a second word line and is capable of reading out a data stored in the at least one XP magnetic memory cell by using said second bit and word lines; a controller comprising a first decoder coupled to said STr type magnetic memory cell array to provide read or write operation and a second decoder coupled to said XP type magnetic memory cell array to provide read or write operation, wherein said controller is integrated in common in a single unitary body of a semiconductor substrate, wherein said memory cell arrays are formed on said body; and wherein said XP type magnetic memory cell array is laid over said STr type magnetic memory cell array.