Patent ID: 9164854
Filing Date: 2015-10-20
Classification: G06F

Abstract:
1. A computer implemented method for thread sparing between cores in a processor, the method comprising: determining, by a first core of the processor, that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold; sending, by the first core to a processor controller in the processor, a request to transfer the first thread to another core of the processor; based on receiving the request, selecting, by the processor controller, a second core from a plurality of cores of the processor to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread; transferring a last good architected state of the first thread from an error recovery logic of the first core to the second core; loading the last good architected state of the first thread by the idle thread on the second core; and resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread; wherein transferring the last good architected state of the first thread from the error recovery logic of the first core to the second core comprises: