Patent ID: 7355448
Filing Date: 2008-04-08
Classification: H03K

Abstract:
1. A semiconductor memory device comprising: an Off Chip Drive (OCD) control signal generator for decoding Extended Mode Register Set (EMRS) and addresses to generate a plurality of external strength control signals or an internal driving signal, wherein the external strength control signals are generated when the EMRS and the addresses are provided from an external device; a self control signal generator for detecting a level of a driving voltage to generate a plurality of internal strength control signals in response to the internal driving signal, wherein the internal strength control signals are generated when the external strength control signals are not generated; a control signal generator for generating a strength control signal in response to the external strength control signals or the internal strength control signals; and a data output driver for outputting data, the strength of the data output driver being controlled according to the strength control signal, wherein the self control signal generator includes: a level detecting unit for detecting the level of the driving voltage; a sampling unit for sampling a plurality of detection signals outputted from the level detecting unit in response to the internal driving signal; and a pulse generating unit for outputting sampling detection signals of the sampling unit as the internal strength control signals having pulse-type strength increase signals and strength decrease signals.