Patent ID: 7576003
Filing Date: 2009-08-18
Classification: H01L,Y10S

Abstract:
1. A method for forming a semiconductor device, comprising the steps of: providing a dielectric layer with at least one conductive interconnect partially embedded therein, wherein an upper surface of said at least one conductive interconnect is substantially co-planar with a surface of said dielectric; depositing a tensile capping layer on said dielectric layer and said at least one conductive interconnect, wherein said tensile capping layer contacts said at least one conductive interconnect; performing a plasma treatment on said tensile capping layer; removing a portion of said tensile capping layer from said dielectric layers, wherein said tensile capping layer remains in contact with said at least one conductive interconnect; depositing a compressive dielectric layer on said tensile capping layer and said dielectric layer; and removing said compressive dielectric layer from said tensile capping layer, wherein said compressive dielectric layer is formed on said dielectric layer and is adjacent to said tensile capping layer; wherein said tensile capping layer is a multiple deposition capping layer deposited on said dielectric layer and said at least one conductive interconnect by at least two sequential deposition and plasma treatment steps; wherein said tensile capping layer exerts a compressive stress at a surface of said conductive interconnect.