Patent ID: 6943071
Filing Date: 2005-09-13
Classification: H01L

Abstract:
1. A method of forming a nonvolatile memory cell comprising: forming a pair of spaced apart shallow trench isolation regions in a substrate, said shallow trench isolation regions defining an active region there between; forming a tunnel dielectric on said substrate active region; forming a floating gate material over said spaced apart shallow trench isolation regions and said tunnel dielectric; polishing said floating gate material until said floating gate material is substantially planar with the top surface of said spaced apart shallow trench isolation regions to form a floating gate with a substantially uniform height; forming a dielectric layer on said planarized floating gate material; forming a control gate on said dielectric; forming a source region and a drain region in said substrate active region on opposite sides of said floating gate; forming a common source rail in said substrate connected to said source region; and forming a contact on said drain region and on one of said shallow trench isolation regions.