Patent ID: 6819590
Filing Date: 2004-11-16
Classification: G11C

Abstract:
A semiconductor memory comprising a plurality memory elements, which are connected between at least two current terminals, and each of which comprises:at least one control terminal which switches a ON state and OFF state of a current path between said current terminals; and an information storage portion interposed between said current path and said control terminal to provide a threshold voltage which is a voltage of said control terminal when the ON state and OFF state of said current path are switched, wherein said information storage portion selectively stores electrically erasable and programmable discrete N-valued (N is an integer of not less than 2) data, said information storage portion provides, as the threshold voltage, first to Nth threshold voltages which are discrete in ascending order of voltage in correspondence with the N-valued data, all the first to Nth threshold voltages of said plurality of memory elements are higher than the lower one of voltages applied to said current terminals in data read, and a voltage higher than the Nth threshold voltage is applied to at least one control terminal of said plurality of memory elements in data read.