Patent ID: 6510492
Filing Date: 2003-01-21
Classification: G06F,G11C

Abstract:
A memory coupled to a bus, the memory comprising:at least one memory array; and a control circuit for controlling data transfer between the bus and the memory array, wherein the control circuit comprises a write buffer having an output port coupled to the memory array and an input port coupled to the bus, wherein the control circuit causes data to be transferred from the bus to the write buffer at a first data transfer rate, and from the write buffer to the memory array at a second data transfer rate which is faster than the first data transfer rate; wherein a first set of data values is transferred from the bus to the write buffer via the data input port and stored in the write buffer, until a second set of data values is transferred from the bus to the write buffer via the data input port, during which the first set of data values is transferred to the memory array via the data output port.