Patent ID: 6334200
Filing Date: 2001-12-25
Classification: G01R

Abstract:
An integrated circuit having a sequential circuit describable as a finite state machine, comprising a state register and combinational circuit, and controllable to a reset state by inputting a reset signal thereto, said integrated circuit comprising:a mode selection means enabling selection of a specific state transition mode for effecting state transitions different from the state transitions of the finite state machine;an invalid-state generation logic circuit for changing to all selectable invalid states and transition-resistant valid states on a state transition path when a specific state transition mode is selected by the mode selection means, based on a process forgenerating a set of test patterns by applying a specific test generation algorithm to the combinational circuit on an assumption that state register states are controllable and observable,determining all invalid states indicated by a test pattern part corresponding to a state register setting in each test pattern of a test pattern set,said invalid state being defined as any state expressible by the state register but not directly selectable from the reset state of the finite state machine;determining all transition-resistant valid states, defined as valid states where the transition sequence required to select that state exceeds a predefined length, or the processing time required to determine a transition sequence for selecting that state exceeds a predefined limit,said valid state being defined as any state directly selectable by the finite state machine from a reset state thereof, anddetermining a state transition path passing through all invalid states and transition-resistant valid states, anda primary observation output for externally observing each signal input to the state register as a signal indicating a value to which the state register is to be set.