Patent ID: 7345927
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. A semiconductor integrated circuit device comprising: a memory cell array including a plurality of word lines, a plurality of bit line pairs and memory cells arranged at intersections between the plurality of word lines and the plurality of bit line pairs; a plurality of sense amplifier line pairs respectively connected to the plurality of bit line pairs, the sense amplifier line pairs having a twist structure; a plurality of sense amplifier latch circuits which are respectively connected to the plurality of sense amplifier line pairs and each of which amplifies and holds data of the memory cell; sense amplifier driver circuits which respectively supply sense amplifier activation signals to the plurality of sense amplifier latch circuits, the sense amplifier driver circuit being provided for each of the plurality of sense amplifier latch circuits and supplying the sense amplifier activation signal to a corresponding one of the plurality of sense amplifier latch circuits, wherein transfer of write data to a selected sense amplifier line pair among the plurality of sense amplifier line pairs is started before the sense amplifier latch circuit is activated at data write time; bit line pair equalization circuits respectively provided for the plurality of bit line pairs; and sense amplifier line pair equalization circuits respectively provided for the plurality of sense amplifier line pairs; wherein each of the bit line pair equalization circuits and sense amplifier line pair equalization circuits includes a CMOS type transfer gate and potential of a bit line pair equalization control signal supplied to the bit line pair equalization circuits and potential of a sense amplifier line pair equalization control signal supplied to the sense amplifier line pair equalization circuits are set lower than potential used to drive the plurality of word lines.