Patent ID: 8711625
Filing Date: 2014-04-29
Classification: G11C

Abstract:
1. A method of operating a non-volatile memory circuit having an array of non-volatile memory cells formed along columns of multiple bits, the method comprising: organizing the columns to include a plurality of regular columns and one or more redundancy columns; performing a plurality of first column test operations to determine which columns are defective, each of the first column test operations including: wherein said first column test operations are performed by circuitry on the memory circuit and each of the first column test operations uses a different data pattern; recording addresses of any of the regular columns determined defective; for any of the regular columns determined defective, setting a latch associated therewith to a value indicating that the associated column is defective; subsequent to performing the first column test operations, performing a plurality of second column test operations on the regular columns determined defective to determine individual bits therein that are defective, each of the second column test operations including: wherein said second column test operations are performed by circuitry on the memory circuit and each of the second column test operations uses a different data pattern; and recording addresses of any of the individual bits of the columns determined defective that are determined defective in the column redundancy data table.