Patent ID: 8155049
Filing Date: 2012-04-10
Classification: H04B,H04L,H04W

Abstract:
1. A method, comprising: employing a processor that facilitates execution of computer executable instructions stored on a non-transitory computer readable storage medium to implement operations, comprising: receiving a first packet via a direct channel; receiving a second packet via a relay channel; receiving an indication in the second packet indicating that an interlink packet passed or failed a first packet error detection; forming an un-scaled log-likelihood ratio (LLR) including summing side information of the second packet and summing a channel value of the first packet; and decoding the first packet with the un-scaled LLR in response to the first packet failing to pass a second packet error detection, the indication indicating that the interlink packet failed to pass the first packet error detection and the second packet passing the second packet error detection.