Patent ID: 6058409
Filing Date: 2000-05-02
Classification: G06F

Abstract:
A computation apparatus comprising:a memory operative to store data in an ordered set;an input buffer operative to store data in a first ordered set and to accept such data in synchronism with a low-speed clock;an output buffer operative to store data in a second ordered set and to read out such data in synchronism with a low-speed clock;a computation unit for accepting selected elements of data and performing butterfly computations on these data in synchronism with a high-speed clock; andmeans for transferring data in synchronism with said high-speed clock;(i) from said input buffer to said memory or to said computation unit; and(ii) between said memory and said computation unit; and(iii) from said memory or from said computation unit to said output buffer,said transferring means being operative to reorder the data during transfer from said input buffer or during transfer to the output buffer, said input buffer being operative to accept the data in predetermined time sequence so that preselected elements of said data in said first ordered set are written into the input buffer first, said transferring means being operative to begin transferring said data from said input buffer by transferring said preselected elements of said data in said first ordered set before all of the data in said first ordered set has been written into said input buffer.