Patent ID: 6215720
Filing Date: 2001-04-10
Classification: G11C

Abstract:
A semiconductor memory device formed at a main surface of a semiconductor substrate, comprising:(a) eight memory blocks arranged in respective regions of three rows and three columns that said semiconductor substrate is divided into, excluding the region of the second row and the second column, each said memory block including:a plurality of word lines,a plurality of bit lines crossing said plurality of word lines, anda plurality of memory cells corresponding to respective crossings of said plurality of word lines and said plurality of bit lines, wherein said eight memory blocks are grouped into four groups of said memory blocks, each group comprising two neighboring memory blocks;(b) control means arranged at said region of the second row and the second column for providing a control signal to said eight memory blocks, said control means including:master control means arranged at the center of said control means for generating a reference signal by which said eight memory blocks operate accordingly, andfour local control means provided corresponding to said four groups of said memory blocks, respectively, and arranged at four corners of said region of the second row and the second column, each local control means receiving said reference signal to output said control signal to a corresponding one of said four groups of said memory blocks; and(c) a plurality of data buses provided respectively corresponding to said eight memory blocks, each transmitting data from/to a corresponding one of said eight memory blocks, said plurality of data buses including:a plurality of first data buses arranged at a boundary portion between the memory blocks at the first column and the memory blocks at the second column, anda plurality of second data buses arranged at a boundary portion between the memory blocks at the second column and the memory blocks at the third column.