Patent ID: 7409503
Filing Date: 2008-08-05
Classification: G06F

Abstract:
1. A multi-processor system that conforms to a cache coherency protocol, the system comprising: a processor having a processor pipeline that executes program instructions with data from a given speculative fill of at least two speculative fills that are provided to the processor from two or more other processors of the multi-processor system in response to a source request, wherein the at least two speculative fills have an undetermined coherency at a time the at least two speculative fills are provided in response to the source request; a first register file that retains register values associated with program instructions employing data from speculative fills; a second register file that retains register values associated with data from speculative fills that have been determined to be coherent; a log that retains executed register entries based on program instructions that write register values into registers associated with the first register file, the register values being written to the second register file if data of a speculative fill associated with the register values is determined to be coherent; and a backup system that initiates a backup to a processor execution backup point in the event that the given speculative fill is determined to be non-coherent, the backup system writes register values associated with executed register entries in the log into the second register file, until a point in the log indicated by the index is reached, the backup system flushing the remaining executed register entries from the log and copying the values of the second register file to the first register file.