Patent ID: 8628336
Filing Date: 2014-01-14
Classification: G01R,G06F

Abstract:
1. An apparatus for testing integrated circuits of a plurality of devices, comprising; at least one holder to hold the plurality of devices; a tester system having a plurality of output channels and an interconnection scheme to connect the channels to a plurality of contacts of the plurality of devices, the contacts being connected to the integrated circuits; a computer system having memory; a test program stored in the memory, the test program having a series of instructions written for testing one of the devices; a configuration file stored in the memory, the configuration file representing a relationship between the channels and the contacts of the plurality of devices; and a test application that utilizes the test program and the configuration file to provide signals in accordance with the series of instructions of the test program through the channels and the interconnection scheme to the contacts of the plurality of devices and the integrated circuits.