Patent ID: 7765448
Filing Date: 2010-07-27
Classification: G01R

Abstract:
1. An integrated circuit comprising: a test pattern input unit for inputting a test pattern into plural cells; a clock distributing unit for distributing a clock signal to the plural cells; a first cell of the plural cells that receives the clock signal distributed by the clock distributing unit; a second cell of the plural cells that receives the clock signal after the clock signal is received by the first cell; a data transfer unit for transferring a data signal from the first cell to the second cell; a clock transfer unit for distributing the clock signal to the first cell and the second cell and transferring the clock signal from the first cell to the second cell; and a failure detecting unit for inputting the test pattern into the plural cells from the test pattern input unit on the basis of the clock signal transferred from the clock transfer unit, and detecting failures of the plural cells on the basis of the results of the test pattern output from the plural cells.