Patent ID: 8533521
Filing Date: 2013-09-10
Classification: G06F

Abstract:
1. A memory device comprising: a nonvolatile semiconductor memory unit; a memory controller configured to perform control to receive a command signal, to send a response signal, and to send and receive a data signal, and a status signal in synchronization with a clock signal, wherein the memory controller controls receiving of the command signal and sending of the response signal through a command line from and to a host device to which the memory device is connected, controls sending and receiving of the data signal and the status signal through a data line to and from the host device, and controls receiving of the clock signal through a clock line from the host device; and a memory-side pattern signal storage unit configured to store first and second tuning pattern signals to be sent to the host device, the first and second tuning pattern signals being used by the host device to adjust a phase of the clock signal for use as a sampling clock signal; wherein: the first and second tuning pattern signals are pre-stored also in the host device; and the memory controller sends to the host device the first tuning pattern signal and the second tuning pattern signal, and a time period during which the first tuning pattern signal is sent and a time period during which the second tuning pattern signal is sent overlap each other.