Patent ID: 6282604
Filing Date: 2001-08-28
Classification: G06F

Abstract:
A memory controller for controlling a dynamic memory device having a plurality of banks of memory cells, comprising:a cache that stores a plurality of entries, each cache entry, when valid, storing information indicating whether a respective memory device bank to which the entry corresponds is open;bank status lookup logic, coupled to the cache, the bank status lookup logic configured to respond to a memory access request that includes an address, at least a portion of which identifies a bank of the memory device, by retrieving first information from an entry, if any, in the cache corresponding to the identified bank, and by also retrieving second information from entries, if any, in the cache for banks codependent with the identified bank; andcontrol signal generation circuitry coupled to bank status lookup logic, the control signal generation circuitry generating a sequence of memory access control signals in accordance with the first and second information.