Patent ID: 8466026
Filing Date: 2013-06-18
Classification: H01L

Abstract:
1. A method for manufacturing a semiconductor device having a first MOSFET with a high withstand voltage, a second MOSFET with a low withstand voltage, and a third MOSFET for electrostatic protection mounted on the same semiconductor substrate, comprising: defining a first region for forming the first MOSFET, and a second region for forming the second MOSFET, and a third region for forming the third MOSFET by forming element isolation regions in the semiconductor substrate; forming a well region for the first MOSFET, a first low concentration diffusion region in a predetermined surface portion of the well region for the first MOSFET, and a first gate electrode on the semiconductor substrate with a gate oxide film for a high voltage interposed therebetween, in the first region; forming a well region for the second MOSFET, a second low concentration diffusion region in a predetermined surface portion of the well region for the second MOSFET, and a second gate electrode on the semiconductor substrate with a gate oxide film for a low voltage interposed therebetween, in the second region; forming a well region for the third MOSFET, a third low concentration diffusion region in a predetermined surface portion of the well region for the third MOSFET, and a third gate electrode on the semiconductor substrate with a gate oxide film interposed therebetween, in the third region; forming a mask insulation film on a whole surface after the first to third gate electrodes and the first to third low concentration diffusion regions have been formed; forming a resist pattern so as to overlap a region from a part of an upper part of the first gate electrode to a part of an upper part of the first low concentration diffusion region in the first region, and overlap a region from a part of an upper part of the third gate electrode to a part of an upper part of the third low concentration diffusion region in the third region; etching the mask insulation film anisotropically using the resist pattern as a mask, to leave the mask insulation film in regions covered with the resist pattern in the first region and the third region, and in a side wall part of the second gate electrode in the second region; performing a high concentration ion implantation using the remaining mask insulation film and the first to third gate electrodes as masks, to form first to third high concentration diffusion regions in surfaces of the first to third low concentration diffusion regions uncovered with the mask insulation film, respectively, and to dope the first to third gate electrodes; forming a high melting point metal film on a whole surface and performing a heat treatment to form silicide layers on upper surfaces of the first to third high concentration diffusion regions, on upper surfaces of the first and the third gate electrodes uncovered with the mask insulation film, and on an upper surface of the second gate electrode; and selectively removing the unreacted high melting point metal film remaining on the mask insulation film and the element isolation regions; wherein the well region for the second MOSFET and the well region for the third MOSFET are formed in the same step, the second low concentration diffusion region for the second MOSFET and the third low concentration diffusion region for the third MOSFET are formed in the same step, and the gate oxide film for the second MOSFET and the gate oxide film for the third MOSFET are formed in the same step.