Patent ID: 9003352
Filing Date: 2015-04-07
Classification: G06F

Abstract:
1. A semiconductor integrated circuit design supporting apparatus configured to cooperate with a high level synthesis means for executing high level synthesis of analyzing a behavioral description, which describes a circuit behavior of an integrated circuit by high level language, to generate register transfer level (RTL) description, the semiconductor integrated circuit design supporting apparatus being further configured to optimize an inserting position and a number of inserting stages of flip-flops (FFs) to be inserted in the RTL description through the high level synthesis by utilizing, in cooperation with the high level synthesis means, a scheduling result including latency of each output pin of each module of the integrated circuit and information on delay between signal lines at each clock boundary inside the each module, the scheduling result being output as an intermediate result when the high level synthesis means performs the high level synthesis, the semiconductor integrated circuit design supporting apparatus having a computer with a central processor unit configured to provide parts comprising: a module analyzing part for extracting modules to be subjected to latency adjustment from the behavioral description; a latency provisionally adjusting part for calculating, as a number of stages of pre-optimization inserting FFs, a number of FFs required to be inserted for latency adjustment between the modules to be subjected to latency adjustment; an input latch FF determining part for extracting an input latch pin that is latched by an FF without interposing logic in a latter-stage module having, as an input, the FF that is required to be inserted, and calculating, as a number of stages of input latch FFs, a number of stages of input latch FFs that latch the input latch pin; a latency re-adjusting part for specifying, based on a relationship between the number of stages of pre-optimization inserting FFs, which is calculated by the latency provisionally adjusting part, and the number of stages of input latch FFs, which is calculated by the input latch FF determining part, the input latch FF and the FF that is required to be inserted, that cancel each other out, to thereby reduce a number of stages of FFs; and a high level synthesis repeating part for deleting, from the scheduling result, an FF specified to be reduced by the latency re-adjusting part so as to optimize the scheduling result, and then cooperating with the high level synthesis means again to generate the optimized RTL description based on the optimized scheduling result.