Patent ID: 8775701
Filing Date: 2014-07-08
Classification: G06F,G11C

Abstract:
1. A source synchronous capture unit on a receiving circuit comprising: a data register unit operable to synchronize data, arriving from a memory external to the receiving circuit, to an edge of a first clock, wherein the first clock is associated with the memory; a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal with the first clock to generate a synchronized write enable signal, wherein the write enable signal is generated in response to a read operation by the receiving circuit; and a second FIFO unit operable to store the data synchronized by the data register unit in response to the edge of the first clock and the synchronized write enable signal, wherein the second FIFO unit is operable to output the data in response to a second clock associated with the receiving circuit and a read enable signal.