Patent ID: 6065140
Filing Date: 2000-05-16
Classification: H03L

Abstract:
A method of determining a first integer divider value (R) and a second integer divider value (N) for a phase lock loop system given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an initial first integer divider (R.sub.0) value and an error limit (E.sub.L) comprising:A) initializing a first integer divider increment (r) equal to zero;B) computing a first constant (K) equal to a quotient of the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R);C) computing a second constant (L) equal to a product of the first constant (K) multiplied times the initial first integer divider (R.sub.0) value;D) computing the second integer divider value (N) equal to a sum of the second constant added to a product of the first constant multiplied times the first integer divider increment (r);E) testing to determine whether an error term (E) resulting from computation of the second integer divider value (N) is within the error limit (E.sub.L);F) selecting a different first integer divider increment (r) as the first integer divider increment (r) if the error term (E) is determined in step (E) to be within the specified error limit (E.sub.L); andG) repeating steps (D) and (E) as a loop after the different first integer divider increment (r) has been selected as the first integer divider increment (r) in step (F).