Patent ID: 7370299
Filing Date: 2008-05-06
Classification: G06F

Abstract:
1. A method for register transfer level power estimation in chip design, a chip being designed using a register transfer level code, the specification of the chip recording all functional input vector sets used to represent activities of the chip, each input vector set including input vectors in two consecutive clock cycles, the method comprising: (A) parsing all possible condition branches of conditional statements in the register transfer level code, and constructing a hierarchy tree to describe power modes that is inducible by each possible condition branch, the hierarchy tree having a plurality of levels and a plurality of nodes, each level being branchable into different nodes based on the conditional statements in the register transfer level code, the nodes branching last therefrom corresponding respectively to all the power modes of the chip; (B) selecting a plurality of representative input vector sets from input vector sets recorded in the chip specification for each of the power modes established in step (A) based on frequencies of occurrence of the power modes, a larger number of input vector sets being selected for those power modes that have a higher frequency of occurrence, and constructing corresponding linear characterization formulas based on the selected input vector sets; and (C) inspecting each of the input vector sets recorded in the chip specification one by one, calculating the power modes corresponding to the input vector sets through the hierarchy tree in step (A), calculating power values from the linear characterization formulas constructed in step (B) which correspond to the power modes, and obtaining an average of sums of the power values of the input vector sets to represent the average power consumed by the chip, wherein, in step (B), the linear characterization formulas are constructed based on a count of logic gates in a logic circuit and of output signals of registers of the chip which toggle as a result of switching of each of the input signals in the selected input vector set.