Patent ID: 6774676
Filing Date: 2004-08-10
Classification: H03K

Abstract:
A buffer having an input terminal and an output terminal, comprising:a first current source for producing an overall current; a first transistor that is configured to produce a first current in response to a first threshold voltage, wherein the first current is sourced from the overall current; a second transistor that is configured to produce a second current in response to a second threshold voltage, wherein the second current is sourced from the overall current and the second current is produced when an output voltage of the buffer is in a first logic state; a third transistor that is configured to produce a third current in response to a voltage at the input terminal, wherein the third current is sourced from the overall current; a fourth transistor that is configured to produce a fourth current in response to the voltage at the input terminal, wherein the fourth current is sourced from the overall current and the fourth current is produced when the output voltage of the buffer is in the first logic state; a current mirror that is configured to receive the first and second currents to produce a first grouped current at a first node, receive the third and fourth currents to produce a second grouped current at a second node, and reflect a selected one of the first and second grouped currents to produce a reflected current at a selected one of the first and second nodes, such that a voltage is produced at the selected node in response to the reflected current and the grouped current that is not reflected; and an output driver that is configured to produce the output voltage at the output terminal in response to the voltage produced at the selected node, wherein the output voltage has at least two logic states.