Patent ID: 8638792
Filing Date: 2014-01-28
Classification: G01R,G06F

Abstract:
1. A non-transitory machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method for debugging, the method comprising: compiling representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions of the source logic; compiling representation of a destination circuit including one or more destination subchannels associated with portions of destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to one of the portions of the destination logic; configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels; and configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous with the plurality of clock domains with the delay period, wherein the packet stream represents a trace of signal data from the portions of the source logic for the delay period, wherein the configuring of the switching logic comprises determining a capacity for the single queue to accommodate the trace of the signal data from the portions of the source logic for the delay period.