Patent ID: 9104635
Filing Date: 2015-08-11
Classification: G06F,G11C

Abstract:
1. A method comprising: determining, via a processor, a worst-case setup and hold time based on both a first load and a second load on a bus, wherein the worst-case setup and hold time is associated with (i) an amount of time a data signal is to be held steady before a clock event and (ii) an amount of time the data signal is to be held steady after the clock event, wherein the worst-case setup and hold time is further based on data stored in a BIOS; determining, via a memory controller, a time shift to apply to a first incoming bit pattern stream being transmitted to the first load, the incoming pattern stream being conveyed relative to a DLL associated with the first load and the second load wherein the time shift is based on the determined worst case setup and hold time, and wherein the first load and the second load are different loads on the bus; and transmitting a first time modulated incoming bit pattern stream to the first load on the bus based on the first determined time shift.