Patent ID: 7949928
Filing Date: 2011-05-24
Classification: G06F,G11C

Abstract:
1. A semiconductor memory device, comprising: a memory cell array having a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal; a mode setting circuit setting the first flag signal and a second flag signal based on whether a separate memory bank is used to store the parity data in the second memory banks; a parity data generation unit receiving normal write data during a write operation, generating parity data with respect to the normal write data in response to the second flag signal, and outputting the normal data and the parity data; and a data error detection and correction unit receiving normal read data and parity read data read from the memory cell array during a read operation, detecting errors of the normal read data in response to the second flag signal, correcting the normal read data when the errors are detected, and outputting the corrected read data.