Patent ID: 8111562
Filing Date: 2012-02-07
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells arranged in a matrix form at intersections of bit lines and word lines; a sense circuit which reads data the memory cells; a sequencer which receives control signals from outside; a first address register which receives an address from outside; and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer, the sequencer, in reading from the memory cells, reading a page n in accordance with the address stored in the second address register, then transferring an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reading data from an arbitrary page m in accordance with the address transferred to the second address register.