Patent ID: 8873296
Filing Date: 2014-10-28
Classification: G11C,H01L

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array including a first block, the first block including a plurality of first units, each of the plurality of first units including a plurality of first memory strings, each first memory string including a first memory cell, a second memory cell, a first selection transistor, and a second selection transistor, the first memory cell being electrically connected to the second memory cell in series, the first selection transistor being electrically connected to the first memory cell in series, the second selection transistor being electrically connected to the second memory cell in series, gates of the first memory cells in the first block being electrically connected, gates of the second memory cells in the first block being electrically connected; and a controller configured to perform an erase operation per the first unit.