Patent ID: 8976554
Filing Date: 2015-03-10
Classification: H02M

Abstract:
1. A system for control in fault-bypass of a cascaded multi-level inverter, the system comprising: a first plurality of first inverter leg cells connected in series for a first phase; a second plurality of second inverter leg cells connected in series for a second phase; a third plurality of third inverter leg cells connected in series for a third phase; and wherein the fault-bypass results in a difference in numbers between the first inverter leg cells in the first plurality and the second inverter leg cells in the second plurality being active; a processor configured to generate reference voltages, free of feedback, for active ones of the first, second, and third leg inverter cells, all of the active first inverter leg cells being operated with a first common one of the reference voltages, all of the active second inverter leg cells being operated with a second common one of the reference voltages, and all of the active third inverter leg cells being operated with a third common one of the reference voltages, the second common one of the reference voltages calculated using the difference as a variable in the calculation.