Patent ID: 6287960
Filing Date: 2001-09-11
Classification: H01L

Abstract:
A method for forming a semiconductor device comprising:forming an interlevel dielectric layer over a semiconductor device substrate;forming a first patterning layer over the interlevel dielectric layer;defining a first opening in the first patterning layer;forming a second patterning layer over the first patterning layer;defining a second opening in the second patterning layer, wherein the second opening exposes a portion of the first opening and a portion of the first patterning layer;removing a first portion of the interlevel dielectric that is exposed by the first opening;removing the portion of the first patterning layer exposed by the second opening; andremoving a second portion of the interlevel dielectric layer that is exposed by the second opening and a third portion of the interlevel dielectric layer defined by the first opening to define a dual inlaid opening in the interlevel dielectric layer; andremoving the second patterning layer and the first patterning layer.