Patent ID: 6133597
Filing Date: 2000-10-17
Classification: H01L

Abstract:
A semiconductor circuit comprising:a region of a first conductivity type;a first well of a second conductivity type adjacent the region, to be biased at a predetermined voltage;a second well of the first conductivity type in the first well;a transistor T1 having first and second electrodes of the second conductivity type, the second electrode being connected to a memory bitline, the region containing at least a portion of the second electrode and a portion of the first electrode, the first electrode also extending inside the first well;a voltage source connected to the first electrode, for providing the predetermined voltage to the first electrode in order to bias the first well, wherein the transistor T1 is turned on during normal operation to couple the predetermined voltage to the second electrode; andone or more transistors T2 having electrodes of the second conductivity type in the second well, each transistor T2 being a transistor of a memory cell and being connected to the bitline, wherein the transistor T1 is to charge the bitline to the predetermined voltage before accessing at least one memory cell.