Patent ID: 6469541
Filing Date: 2002-10-22
Classification: H03K

Abstract:
A digital CMOS circuit comprising:a first section having no more than eight CMOS transistors including two transmission gate pairs and two inverters and configured to receive digital input signals A and B, the first section adapted to produce an output Q if the logical values of signals A and B are equivalent, and to produce an output Qâ€² if the logical values of signals A and B are opposite, where Qâ€² is the inverse of Q; and a second section having no more than six CMOS transistors including a first P-channel transistor and a first N-channel transistor configured as a transmission gate pair, a second P-channel transistor and a second N-channel transistor configured as an inverter, a third P-channel transistor and a third N-channel transistor, where the second section is configured to receive the output of the first section and an input signal C, and where the second section is adapted to produce an output R if the logical values of the output of the first section and signal C are equivalent, and to produce an output Râ€² if the logical values of the output of the first section and signal C are opposite, where Râ€² is the inverse of R.