Patent ID: 7929361
Filing Date: 2011-04-19
Classification: G11C,H03L

Abstract:
1. A dynamic random access memory (DRAM) controller comprising: a read path circuit having a first input for receiving a memory data signal, a second input for receiving a memory data strobe signal, and an output for providing a processor data signal, wherein said read path circuit uses a shared delay locked loop (DLL) to receive said memory data signal; a write path circuit having a first input for receiving said processor data signal, a second input for receiving a processor clock signal, a first output for providing said memory data signal, and a second output for providing said memory data strobe signal, wherein said write path circuit uses said shared DLL to provide one of said memory data signal and said memory data strobe signal; and a controller for enabling said shared DLL for use by said read path circuit during a read cycle, and for enabling said shared DLL for use by said write path circuit during a write cycle.