Patent ID: 7243204
Filing Date: 2007-07-10
Classification: G06F

Abstract:
1. An integrated circuit chip, comprising: a processing component on the integrated circuit chip; a Level 1 (L1) cache and a Level 2 (L2) cache on the chip, which are arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having a predetermined address length; and first and second buses on the chip coupled between the processing component and the L1 cache, and third and fourth buses on the chip coupled between the L1 cache and the L2 cache, the first and third buses having bus widths smaller than m the processing component and the L1 and L2 caches comprising respective address bus expanders coupled to the first and third buses in order to compact at least some of the memory addresses for transmission over the first and third buses so that each of the at least some memory addresses is transmitted over the first and third buses in one bus cycle, wherein the L1 cache comprises a table for use in compaction of address fields that is shared by the address bus expanders coupled to the first and third buses.