Patent ID: 6381719
Filing Date: 2002-04-30
Classification: G01R

Abstract:
A system for reducing the clock skew sensitivity of a shift register comprising:a first cell, disposed at a first end of the shift register, the first cell having a clock input for receiving a clocked signal, a delay circuit for delaying the clocked signal, a clock output for transmitting a first delayed clocked signal, a test data input for receiving a test data signal, and a test data output for transmitting the test data signal; a second cell disposed at a second end of the shift register, the second cell having a clock input for receiving the first delayed clocked signal, a delay circuit for delaying the first delayed clocked signal, a clock output for transmitting a second delayed clocked signal, a test data input for receiving a test data signal, and a test data output for transmitting the test data signal; a control circuit for generating and transmitting the clocked signal to the first cell of the shift register, the control circuit having a test data input for receiving the test data signal transmitted by the first cell of the shift register.