Patent ID: 7187195
Filing Date: 2007-03-06
Classification: G01R,G11C

Abstract:
1. A compression test circuit of a memory device, comprising: a plurality of banks each comprising a plurality of bit line sense amplifiers for sensing and amplifying data in bit lines; a plurality of input/output amplifiers to amplify data which is amplified by the bit line sense amplifier and is loaded in input/output lines; a plurality of compression comparators for compressing and comparing data amplified by the plurality of input/output amplifiers in each bank; a plurality of global input/output drivers for driving each data amplified by the plurality of input/output amplifiers or for driving each of a plurality of comparison signals outputted from the plurality of compression comparators; a plurality of output drivers for driving data driven by the global input/output driving unit to an external pin; and an input/output amplification control unit for generating a plurality of first control signals to activate the plurality of input/output amplifiers in each bank at different timings in a test mode.