Patent ID: 6360291
Filing Date: 2002-03-19
Classification: G06F

Abstract:
A computer system, comprising:at least one host processor for executing a host operating system, said at least one host processor disposed on a host bus; an input/output (I/O) bus operably coupled to said host bus via a host-to-bus bridge, said I/O bus for propagating at least one of a FRAME signal, a GRANT signal, an IRDY signal and a clock signal associated therewith; a plurality of peripheral devices operably connected to said I/O bus, said plurality of peripheral devices for transferring data in I/O transactions; a dynamic device blocker module disposed on said I/O bus for rendering at least a portion of said plurality of peripheral devices hidden from said host operating system based on said at least one of a FRAME signal, a GRANT signal, an IRDY signal and a clock signal associated therewith; and an accelerator module disposed on said I/O bus for controlling said at least a portion of said plurality of peripheral devices.