Patent ID: 8420495
Filing Date: 2013-04-16
Classification: H01L

Abstract:
1. A manufacturing process for a collector and a buried layer of a bipolar transistor comprises, step 1: etching shallow trenches on a silicon substrate wherein depth of the trench is less than 2 μm; step 2: doping bottoms of the shallow trenches with an impurity by ion implantation; forming one or more doped regions in the silicon substrate near the bottom of the shallow trenches; step 3: filling a dielectric into the shallow trenches to form a shallow trench isolation (STI); step 4: annealing the silicon substrate with a predetermined temperature; linking the doped regions through lateral diffusion to form a pseudo buried layer, step 5: implanting an active region between the STIs and above the pseudo buried layer by one or more ion implantations to convert the active region into the collector, wherein a doping concentration of the collector is lower than that of the pseudo buried layer.