Patent ID: 8848142
Filing Date: 2014-09-30
Classification: G02F,H01L

Abstract:
1. An array substrate for a liquid crystal display device including a plurality of pixel regions, comprising: a p-type driving TFT, an n-type driving TFT and a switching TFT on a substrate that includes a display area and a non-display area, wherein the p-type and the n-type driving TFTs are in the non-display area and the switching TFT is in the display area; a gate insulating layer on the substrate that includes first, second and third semiconductor layers; first, second and third gate electrodes and a gate line connected to the third gate electrode on the gate insulating layer, wherein the first, second and third gate electrodes correspond to central portions of the first, second and third semiconductor layers; a first storage electrode in the display area and a second storage electrode over the first storage electrode, wherein the first and second storage electrodes form a storage capacitor with the gate insulating layer therebetween; an interlayer insulating layer on the substrate that includes the first, second and third gate electrodes, wherein the interlayer insulating layer has first, second and third contact holes that expose ohmic contact regions of the first, second and third semiconductor layers; first, second and third source electrodes and first, second and third drain electrodes and a data line on the interlayer insulating layer, wherein the data line is connected to the third source electrode and crosses the gate line to define a pixel region, wherein each of the first, second and third source electrodes and the first, second and third drain electrodes contacts each of the ohmic contact regions of the first, second and third semiconductor layers via each of the first to third contact holes; a passivation layer on the substrate that includes the first, second and third source electrodes and the first, second and third drain electrodes and the data line, wherein the passivation layer has a drain contact hole that exposes a portion of the third drain electrode; a pixel electrode on the passivation layer, wherein the pixel electrode connects to the third drain electrode via the drain contact hole; and a black matrix on the substrate that includes the pixel electrode, the pixel electrode having an overlapping portion that overlaps with the black matrix and a non-overlapping portion exposed from the black matrix and connected to the overlapping portion, wherein the overlapping portion of the pixel electrode is in direct contact with the black matrix and connected to the third drain electrode under the black matrix, the storage capacitor being disposed between the non-overlapping portion of the pixel electrode and the third drain electrode in a same pixel region, wherein the black matrix is in the non-display area and a non-pixel area of the display area, wherein the black matrix is formed on upper surfaces of the passivation layer and the pixel electrode, wherein the black matrix directly contacts a portion of the passivation layer between the pixel electrode and the data line and directly contacts an end portion of the pixel electrode, and wherein the black matrix completely covers the storage capacitor and the data line.