Patent ID: 6141718
Filing Date: 2000-10-31
Classification: G06F

Abstract:
A bridge for a multi-processor system, the bridge comprising a first processor bus interface for connection to an I/O bus of a first processing set, a second processor bus interface for connection to an I/O bus of a second processing set, a device bus interface for connection to a device bus, a bridge control mechanism configured to be operable to compare address and data phases of I/O accesses by the first and second processing sets, at least one dissimilar data register associated with each processing set, and a direct memory access mechanism operable to initiate a direct memory access operation to read from a corresponding location in each processing set into the associated dissimilar data register, the bridge control mechanism being configured to be operable during the direct memory access operation to disregard differences in the data for the dissimilar data direct memory access.