Patent ID: 6294423
Filing Date: 2001-09-25
Classification: H01L

Abstract:
A method for forming isolation trenches in semiconductor devices, comprising the steps of:forming, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size, the plurality of trenches having a same first depth wherein the trenches with the widths above the threshold size are formed in a memory array, and the trenches with the widths below the threshold size are formed in a support area;depositing a masking layer in the plurality of trenches, the masking layer including a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size;exposing a portion of the substrate at a bottom of the trenches with the widths above the threshold size by etching the masking layer over the plurality of trenches; andetching the plurality of trenches to extend the trenches with the widths above the threshold size to a different depth.