Patent ID: 6576515
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method of forming a transistor gate on a substrate having a gate dielectric layer above the substrate, a lower section floating gate above the gate dielectric layer, a source/drain terminal in the substrate on each side of the lower section of the floating gate and a first dielectric layer over the substrate with a via opening that exposes a portion of the lower section of the floating gate, comprising the step of:forming a conductive material over the first dielectric layer, wherein the conductive material completely fills the via opening; patterning the conductive material to form a first conductive layer, wherein the first conductive layer at least completely fills the via opening and the first conductive layer has slant external sidewalls; forming a mask material layer covering the first conductive layer; performing a planarization operation to remove a portion of the mask material layer and form a first etching mask layer, wherein the upper surface of the first conductive layer is also exposed alter the planarization operation; subsequently performing an anisotropic slant etching operation using the first etching mask layer as a mask on a top of the first conductive layer to form an opening with slant inner sidewalls in the first conductive layer, wherein the anisotropic etching operation etches at least 30% of the thickness of the conductive layer above the dielectric layer.