Patent ID: 9047980
Filing Date: 2015-06-02
Classification: G11C

Abstract:
1. A circuit, comprising: a first pass gate transistor driven by a bit line true associated with a static random access memory (SRAM) cell, the first pass gate transistor having a gate, a drain and a source; a second pass gate transistor driven by a bit line complement associated with the SRAM cell, the second pass gate transistor having a gate, a drain and a source; a first pull down transistor coupled to the first pass gate transistor, the first pull down transistor having a gate, a drain and a source; a second pull down transistor coupled to the second pass gate transistor, the second pull down transistor having a gate, a drain and a source; a data line true coupled to a first node coupling the first pull down transistor with the first pass gate transistor, wherein the data line true is isolated from the bit line true by the first pass gate transistor; a data line complement coupled to a second node coupling the second pull down transistor with the second pass gate transistor, wherein the data line complement is isolated from the bit line complement by the second pass gate transistor; and a differential to single ended signal converter that receives data from the data line true and the data line complement as input and generates a single output therefrom.