Patent ID: 9070746
Filing Date: 2015-06-30
Classification: H01L

Abstract:
1. A method for manufacturing a nonvolatile semiconductor memory device comprising: (a) forming a first stacked structure including a second insulating film provided on a semiconductor layer and a charge storage layer provided on the second insulating film; (b) forming a plurality of first trenches in the first stacked structure to form a plurality of first semiconductor regions, the second insulating film, and the charge storage layer, the plurality of first trenches extending in a first direction and being arranged in a direction crossing the first direction, the plurality of first semiconductor regions extending in the first direction and being arranged in a direction crossing the first direction, the second insulating film being provided on each of the plurality of first semiconductor regions and extending in the first direction, the charge storage layer being provided on the second insulating film and extending in the first direction; (c) forming an element isolation region in each of the plurality of first trenches in a manner, and a top of the charge storage layer and part of a side wall of the charge storage layer leading to the top are exposed in the manner; (d) forming a first insulating film on the top of the charge storage layer and on the part of the side wall of the charge storage layer; (e) forming a gate electrode layer on the first insulating film; (f) forming a plurality of second trenches in a second stacked structure including the gate electrode layer, the first insulating film, the charge storage layer, and the element isolation region to form a plurality of control gate electrodes, a select gate electrode, the charge storage layer, and the first insulating film, the plurality of second trenches extending in a second direction and being arranged in a direction crossing the second direction, the plurality of control gate electrodes extending in the second direction and being arranged in a direction crossing the second direction, the select gate electrode being aligned with the plurality of control gate electrodes, the charge storage layer being provided between each of the plurality of control gate electrodes and each of the plurality of first semiconductor regions, the first insulating film being provided between each of the plurality of control gate electrodes and the charge storage layer; (g) removing part of the element isolation region via the plurality of second trenches to form a space between adjacent ones of the plurality of first semiconductor regions in a direction crossing the first direction and to expose part of the charge storage layer and part of the first insulating film at the space between adjacent ones of the plurality of first semiconductor regions in the direction crossing the first direction; (h) forming a sacrifice layer in the space, in the plurality of second trenches, and on a side wall of the select gate electrode; (i) covering an upper side of the plurality of control gate electrodes, an upper side of the select gate electrode, and an upper side of the sacrifice layer with a first insulating layer; (j) forming an interlayer insulating film on the first insulating layer; (k) forming a hole extending from an upper surface of the interlayer insulating film to the sacrifice layer and to each of the plurality of first semiconductor regions; and (l) removing the sacrifice layer via the hole to form the space between adjacent ones of the plurality of first semiconductor regions, between adjacent ones of the plurality of control gate electrodes, and between a control gate electrode located on an outermost side out of the plurality of control gate electrodes and the select gate electrode, and to expose part of a side wall of the charge storage layer and part of the first insulating film at the space between adjacent ones of the plurality of first semiconductor regions.