Patent ID: 6184099
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of forming source/drain junctions within a substrate, said method comprising:forming active areas within said substrate, said active areas comprise NMOS regions and PMOS regions;forming gate electrodes on the surface of said substrate, said gate electrodes formed over said active areas;performing a blanket implant of a dopant of a first conductivity into said substrate, wherein said dopant of said first conductivity type is formed in the source/drain junctions of said active areas;depositing a layer of dielectric material and etching said layer to form sidewall spacers adjacent each opposite sidewall of said gate electrodes;forming a first mask on the surface of said substrate to expose only those active areas where it is desirable to introduce a dopant of a second conductivity type;performing a first masked implant of said dopant of said second conductivity type into the exposed active areas of said substrate, wherein said dopant of said second conductivity type is aligned with said sidewall spacers, and wherein said dopant of said second conductivity type overcompensates for said dopant of said first conductivity type; andperforming an annealing thermal cycle, wherein said annealing thermal cycle drives said dopant of said second conductivity type under said sidewall spacers to form a lightly doped drain region under said sidewall spacers wherein said dopant of said first conductivity type forms a lightly doped drain junction in said PMOS regions and a halo structure in said NMOS regions.