Patent ID: 6055600
Filing Date: 2000-04-25
Classification: G06F

Abstract:
A method, implemented in a computer system having a processor, for detecting and identifying a level-2 cache memory in said computer system, comprising the steps of:providing a level-2 cache memory having a plurality of memory modules thereon connected to said processor, wherein said memory modules contain information retrieval by said processor;connecting an ID Module having identification information stored therein for said plurality of memory modules to said level-2 cache in said computer system;accessing said ID Module by said processor using a plurality of parallel interface bits and returning said identification information therein to said processor;interpreting said identification information by said processor and comparing said identification information to a predetermined value indicating a need for access via a serial interface to determine the memory modules on said level-2 cache; andaccessing said ID module using said serial interface using a subset of said plurality of parallel interface bits to determine the memory modules on said level-2 cache when said predetermined value is detected by said processor.