Patent ID: 8947925
Filing Date: 2015-02-03
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: an array of memory cells formed on a substrate, each given memory cell including a resistive load element and a thyristor device that define a switchable current path through the resistive load element and the thyristor device of the given memory cell, wherein the resistive load element is realized from a phase change material that can be selectively programmed into one of a high resistive state and a low resistive state by current that flows through the switchable current path of the given memory cell, and wherein the state of the switchable current path of the given memory cell represents a volatile bit value stored by the given memory cell; at least one word line corresponding to a respective row of the array formed on the substrate, wherein a given word line is coupled to the switchable current path through the resistive load element and thyristor device of the memory cells for the corresponding row of the array in order to access the memory cells for the corresponding row of the array; and a plurality of bit lines corresponding to respective columns of the array formed on the substrate, wherein a given bit line is coupled to a modulation doped quantum well interface of the memory cells for the corresponding column of the array in order to detect the volatile bit values stored by the memory cells for the corresponding column of the array.