Patent ID: 8810552
Filing Date: 2014-08-19
Classification: G09G,G11C

Abstract:
1. A scan driver comprising a plurality of sequentially arranged scan driving blocks, each of the scan driving blocks comprising: a first transistor having a gate electrode coupled to a first node and configured to receive a clock signal input to a first clock signal input terminal, a first electrode configured to receive an output control signal, and a second electrode coupled to a first output terminal; a second transistor having a gate electrode coupled to a second node configured to receive an input signal transmitted according to a clock signal input to a second clock signal input terminal, a first electrode coupled to a third clock signal input terminal, and a second electrode coupled to the first output terminal; a third transistor having a gate electrode coupled to the first node, a first electrode configured to receive the output control signal, and a second electrode coupled to a second output terminal; and a fourth transistor having a gate electrode coupled to the second node, a first electrode coupled to the third clock signal input terminal, and a second electrode coupled to the second output terminal, wherein the first output terminal is coupled to a scan line, and the second output terminal is coupled to an input signal input terminal of a next scan driving block of the scan driving blocks.