Patent ID: 7002192
Filing Date: 2006-02-21
Classification: H01L

Abstract:
1. An area efficient asymmetric cellular CMOS array comprising: a first drain and a second drain having a first area and a second area, a first length and a second length in a first direction, and a third length and a fourth length in a second direction, respectively, and a first source and a second source arranged in association with the first and second drains in an array with a first to fourth channels each between one of the sources and one of the drains, the first source having a third area smaller than the first and second areas, a fifth length in the first direction smaller than the first length, and a sixth length in the second direction smaller than the third length, and the second source having a fourth area smaller than the first and second areas, a seventh length in the first direction smaller than the second length, and an eighth length in the second direction smaller than the fourth length; wherein the first channel between the first drain and the first source has a width smaller than or equal to the fifth length, the second channel between the first drain and the second source has a width smaller than or equal to the eighth length, the third channel between the second drain and the first source has a width smaller than or equal to the sixth length, and the fourth channel between the second drain and the second source has a width smaller than or equal to the seventh length.