Patent ID: 6574766
Filing Date: 2003-06-03
Classification: H03M,H04L

Abstract:
A turbo decoding apparatus for decoding a turbo code containing at least information to be decoded, a first error correcting code for the information, generated before an interleave operation on a transmitting side, and a second error correcting code for the information, generated after the interleave operation on the transmitting side, while interleaving and deinterleaving are repetitively carried out, comprisingan error correction decoding unit capable of effecting error correction decoding on the information based on either of the first and second error correcting codes and on a result of error correction decoding performed in a preceding stage; a memory unit, shared with the interleave and deinterleave operations, for interleaving and deinterleaving the result of error correction decodings supplied from the error correction decoding unit and for outputting results to the error correction decoding unit; and a memory control unit for controlling the order of writing/reading the result of error correction decoding operations into and from the memory unit, so that the interleave and deinterleave operations can be performed using the single memory unit; wherein the memory control unit includes: a first address generating unit for generating a series of addresses in a predetermined order for the memory unit; a second address generating unit for generating a series of addresses in an order which is different from that of the first address generating unit; an address selecting unit for selecting an output of one of the address generating units to generate a writing address for the memory unit and an output of the other of the address generating units to generate a reading address for the memory unit; an interleave mode determining unit for determining whether the error correcting code utilized in the error correction decoding unit is the first or second error correcting code; and an address selection control unit for controlling the address selecting unit in such a manner that if the interleave mode determining unit determines that the error correcting code is first error correcting code then one of the outputs of the address generating units is selected as the writing address while the other of the outputs of the address generating units is selected as the reading address, and if the interleave determining unit determines that the error correcting code is the second error correcting code then the other of the outputs of the address generating units is selected as the writing address while the one of the outputs of the address generating units is selected as the reading address.