Patent ID: 6523118
Filing Date: 2003-02-18
Classification: G06F

Abstract:
A computing system, comprising:a processor; a cache, coupled to the processor, the cache storing a plurality of cache lines, the processor utilizing data stored in the cache; a memory system, the memory system storing a plurality of blocks of encrypted data; and, a secure cache controller system, coupled to the memory system and the cache, the secure cache controller system being in addition to the processor, wherein when there is a miss of a first cache line of data in the cache and the first cache line of data resides in a first block of encrypted data within the memory system, the secure cache controller system fetches the first block of encrypted data, decrypts the first block of encrypted data and forwards the first cache line to the cache, wherein before the secure cache controller system fetches the first block of encrypted data, the secure cache controller system checks to see whether the first block has already been decrypted and is buffered within the secure cache controller system.