Patent ID: 6751705
Filing Date: 2004-06-15
Classification: G06F

Abstract:
A computer system comprising:a first processor, a first memory coupled to the first processor; a plurality of cache levels between the first processor and the first memory including a first cache level closer to the first processor and a second cache level closer to the first memory; a cache directory coupled to the second cache level and associated with the first memory; control circuitry operatively coupled to the second cache level, wherein based on the first processor performing a first memory access to the first memory, the control circuitry stores a first cache line from the first memory into the second cache level and a subset of the first cache line into the first cache level and maintains the cache directory, wherein the cache directory stores information regarding memory data that is cached, and after the first data in the first cache level is changed, the control circuitry moves the changed subset of the first cache line back to the first cache line in the second cache level and moves the changed first cache line to the first memory; a second processor; a second memory associated with the second processor, the second memory coupled to the first memory such that the first processor can access the second memory, wherein when the first processor performs a second memory access to the second memory, the control circuitry stores a second cache line from the second memory into the first cache level and a subset of the second cache line into the second cache level, and the control circuitry also purges the second data from the second cache level without purging the corresponding data from the first cache level, and replaces the purged second data with other data of a different memory address than the purged second data, and after the subset of the second cache line in the first cache level is changed, the control circuitry moves the changed subset of the second cache line back to the second cache line in the second cache level and moves the changed second cache line to the second memory.