Patent ID: 8502560
Filing Date: 2013-08-06
Classification: H03K

Abstract:
1. An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal, the output circuit comprising: an output pMOS transistor connected at a source thereof to a first power supply; an output nMOS transistor connected between a drain of the output pMOS transistor and ground; an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor; a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor; and a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor, wherein the first level shifter circuit includes: a first pMOS transistor connected at a source thereof to the first power supply; a first nMOS transistor connected between a drain of the first pMOS transistor and the ground, and connected at a gate thereof to a first logic terminal supplied with a first logic signal; a second pMOS transistor connected at a source thereof to the first power supply; a second nMOS transistor connected between a drain of the second pMOS transistor and the ground, and connected at a gate thereof to a second logic terminal supplied with a second logic signal which is obtained by inverting a logic of the first logic signal; a first control pMOS transistor connected at a source thereof to the first power supply, connected at a drain thereof to a drain of the second pMOS transistor, and connected at a gate thereof to a first control terminal supplied with a first output control signal based on the impedance control signal; and a first control nMOS transistor connected at a drain thereof to the gate of the second nMOS transistor, connected at a source to the ground, and connected at a gate thereof to a second control terminal supplied with a second output control signal based on the impedance control signal, the second level shifter circuit includes: a third pMOS transistor connected at a source to the first power supply; a third nMOS transistor connected between a drain of the third pMOS transistor and the ground, and connected at a gate thereof to a third logic terminal supplied with a third logic signal; a fourth pMOS transistor connected at a source thereof to the first power supply; a fourth nMOS transistor connected between a drain of the fourth pMOS transistor and the ground, and connected at a gate thereof to a fourth logic terminal supplied with a fourth logic signal which is obtained by inverting a logic of the third logic signal; a second control nMOS transistor connected at a source thereof to the ground, connected at a drain thereof to a drain of the fourth nMOS transistor, and connected at a gate thereof to a third control terminal supplied with the second output control signal; and a third control nMOS transistor connected at a drain thereof to the gate of the third nMOS transistor, connected at a source thereof to the ground, and connected at a gate thereof to a fourth control terminal supplied with the second output control signal.