Patent ID: 7884661
Filing Date: 2011-02-08
Classification: G11C,H03K

Abstract:
1. A clock generating circuit generating a clock signals (hereinafter “the clocks”) used for outputting a data signal to a data pin, the clock generating circuit comprising: a dividing portion dividing an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) by N and outputting 2N divided clock signals (hereinafter “the divided clocks”) having a 360/2N-dgree phase difference between each of the divided clocks; a clock generating portion performing a predetermined logical operations combining the divided clocks to generate N number of the clocks having a constant duty and the same period as the external clock, wherein N is an integer greater than 1, wherein the clock generating portion comprises: an amplifying portion comprising: a first inverter group generating a plurality of inverted divided clocks by inverting the plurality of divided clocks; and a second inverter group generating a plurality of delayed divided clocks by inverting the plurality of inverted divided clocks; and a coding portion generating an output clock by performing predetermined logical operations that combine the delayed and inverted divided clocks, wherein the coding portion comprises: a first clock output portion comprising: a first middle pulse generating portion that performs a NAND logical operation on the divided clocks in pairs to generate N first middle pulses, and a first pulse generating portion that performs a NAND combination on the N first middle pulses to generate a first clock, thereby generating the first clock that has the same period and phase as the external clock; and a second clock output portion comprising: a second middle pulse generating portion that performs a NAND combination on the divided clocks having a 360/2N-degree phase difference respectively from the signals inputted into the first middle pulse generating portion in pairs to generate N second middle pulses, and a second pulse generating portion that performs a NAND combination on the N second middle pulses to generate a second clock, thereby generating the second clock that has the same period as the external clock but a 180-degree phase difference.