Patent ID: 6091090
Filing Date: 2000-07-18
Classification: H01L

Abstract:
In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising:first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer;a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces;a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces;a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; anda plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.