Patent ID: 6038182
Filing Date: 2000-03-14
Classification: G11C

Abstract:
An integrated circuit memory device comprising:a plurality of input/output channels;an array of memory cells;a plurality of data input buffers, a respective one of which is responsive to a respective one of the plurality of input/output channels to buffer input data from the plurality of input/output channels;a write multiplexer that is connected between the plurality of input data buffers and the array of memory cells to transmit the buffered input data for writing in the array of memory cells in response to a plurality of control signals in a normal mode, the write multiplexer being responsive to a selected one of the plurality of the control signals in a test mode to transmit the buffered input data from one of the plurality of input data buffers that corresponds to the selected one of the plurality of control signals to the memory cell array;a plurality of data output buffers, a respective one of which buffers memory cell data that is read from the array of memory cells to the plurality of input/output channels;a read multiplexer that is responsive to the array of memory cells to transmit the memory cell data that is read from the array of memory cells to the plurality of data output buffers in response to the plurality of control signals in the normal mode, the read multiplexer being responsive to the selected one of the plurality of control signals in the test mode to transmit the memory cell data to one of the plurality of output data buffers that corresponds to the selected one of the plurality of control signals; anda comparator that receives the memory cell data that is read from the array of memory cells in the test mode and that provides comparison data to the read multiplexer.