Patent ID: 6031415
Filing Date: 2000-02-29
Classification: H03H,H04B

Abstract:
A matched filter circuit, comprising:a plurality of sampling and holding circuits, each circuit comprising:a switch connected to an input voltage and producing a switch output voltage;a first capacitance connected to the switch output voltage, and producing a first capacitance output;a first inverted amplifying portion having an odd number of stages of MOS inverters connected to the first capacitor output and producing a first inverted amplifying portion output;a first feedback capacitance connecting the first inverted amplifying portion output to a first inverted amplifying portion input; anda first multiplexer and a second multiplexer each selectively outputting one of the first inverted amplifying portion output and a reference voltage generated by a reference voltage generating circuit; anda first addition portion comprising:a plurality of second capacitances each corresponding to one of said sampling and holding circuits, each of said second capacitances connected to an output of said first multiplexer of one of said sample and holding circuits, and each of which producing a second capacitance output;a second inverted amplifying portion having an odd number of stages of MOS inverters, said second inverted amplifying portion being commonly connected to each second capacitance output, and producing a second inverter amplifying portion output;a second feedback capacitance connecting the second inverted amplifying portion output to a second inverted amplifying portion input; anda second addition portion comprising:a plurality of third capacitances each corresponding to one of said sampling and holding the circuits, each connected to an output of said second multiplexer of one of said sample and holding circuits, and each producing a third capacitance output;a third inverted amplifying portion having an odd number of stages of MOS inverters, said third inverted amplifying portion being commonly connected to each third capacitance output, and producing a third inverted amplifying portion output;a third feedback capacitance connecting the third inverted amplifying portion output to a third inverted amplifying portion input; anda subtraction portion for subtracting an output of said second addition portion from an output of said first addition portions;a control circuit for closing said switch in one of said sampling and holding circuits as well as opening said switch in other of said sample and holding circuits and for causing a selected one of said first and second multiplexers of each sampling and holding circuit to output the first inverted amplifying portion output and the other of said first and second multiplexers of each sample and holding circuit to output the reference voltage;a first multiplier register for holding a plurality of PN codes of a number equal to a number of said sampling and holding circuits, for inputting in parallel said PN codes to said control circuit, and for circularly shifting said held PN codes; anda second multiplier register having a data area corresponding to a data area of said first multiplier register, to which PN codes are serially inputted, each said data area of said second multiplier register being connected to said data area of said first multiplier register so that said PN code of each data area in said second multiplier is transferred to said data area of said first multiplier register.