Patent ID: 7022573
Filing Date: 2006-04-04
Classification: H01L

Abstract:
1. A method for fabricating a stacked gate vertical flash memory, comprising: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate; conformally forming an isolation layer on a bottom of the trench; forming a source conducting layer on the bottom of the trench, wherein the source conducting layer and the semiconductor substrate are separated by the isolation layer; conformally forming an ion doped polysilicon layer on a sidewall of the trench and the source conducting layer; annealing the ion doped polysilicon layer, wherein the dopant is driven in to the semiconductor substrate of the bottom of the trench to form a source area, the dopant is driven in the source conducting layer to form a common source area; etching the ion doped polysilicon layer to leave a remaining portion between the source area and the common source area; forming an insulating layer on the source conducting layer, wherein the source conducting layer and others formed thereon are separated by the insulating layer; sequentially forming a gate dielectric layer and a conducting spacer on the sidewall of the trench, wherein the conducting layer covers the gate dielectric layer as a floating gate, and a top portion of the conducting spacer is a tip; dopant implanting into the top of the conducting spacer to form a drain area on a side of the top of the conducting spacer in the semiconductor substrate; forming an inter-gate dielectric layer covering the conducting layer; and filling a control gate layer in the trench.