Patent ID: 6016000
Filing Date: 2000-01-18
Classification: H01L

Abstract:
A multi-level interconnect structure for a semiconductor integrated circuit chip on a semiconductor substrate comprising:a plurality of electrically conductive metallization levels, each of said metallization levels comprising a plurality of electrically conductive interconnect segments;a plurality of electrically conductive plugs for electrically connecting between various metallization levels and between said metallization levels and a plurality of semiconductor devices;a free-space medium occupying at least a substantial portion of the electrically insulating regions within said multi-level interconnect structure; andan electrically insulating top passivation overlayer for hermetic sealing of said multi-level interconnect structure and for protection of said integrated circuit chip, said top passivation overlayer also serving as a heat transfer medium for facilitating heat removal from said interconnect structure and providing additional mechanical support for said interconnect structure through contact with the top metallization level of said multi-level interconnect structure.