Patent ID: 7380097
Filing Date: 2008-05-27
Classification: G06F

Abstract:
1. An address conversion buffer controlling apparatus, constituted on a processor capable of executing a plurality of threads simultaneously on one core, comprising: an address conversion buffer that is controlled by the address conversion buffer controlling apparatus, and that includes a first memory area usable by one of the threads and a second memory area shared among all the threads; an entry registering unit that registers address conversion information in an entry of the address conversion buffer; a swap area control unit that provides control to allocate a part of the second memory area as a swap area of the first memory area; and a swap data transferring unit that transfers data in the swap area to the first memory area, based on thread switching executed by the processor, wherein the swap area control unit provides control to allocate the swap area in the second memory area for each thread that is simultaneously executable on the processor, and while registering the address conversion information in the first memory area, the entry registering unit also registers the address conversion information in the swap area corresponding to the thread being executed on the processor.