Patent ID: 6337245
Filing Date: 2002-01-08
Classification: H01L

Abstract:
A method for fabricating a flash memory device, comprising:forming a device isolation film over a predetermined region of a semiconductor substrate to define a plurality of active regions; forming a tunnel insulating film over the active regions; forming a plurality of floating gate patterns in parallel, such that they cross the device isolation film and the active regions, each of the plurality of floating gate patterns comprising a conductive layer pattern and a capping layer pattern that are sequentially stacked; forming a plurality of impurity regions of a different conductivity type from that of the semiconductor substrate in a portion of the active region between the plurality of floating gate patterns; forming an insulating film pattern to fill up regions between the plurality of floating gate patterns; forming a plurality of floating gates and isolated capping layers that are sequentially stacked over respective active regions by selectively etching a predetermined region of each floating gate pattern to expose a portion of the device isolation film beneath each floating gate pattern; exposing each floating gate by removing the isolated capping layers; forming an inter-gate dielectric film over the exposed floating gate and the exposed device isolation film; and forming a plurality of word lines over the inter-gate dielectric film, such that each word line crosses the device isolation film and the active regions.