Patent ID: 6168958
Filing Date: 2001-01-02
Classification: H01L

Abstract:
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness of about 100-500 .ANG. and a dielectric constant of at least 20; depositing a gate conductive layer on the high permittivity layer; etching selected portions of the gate conductive layer in a reaction chamber with a first etchant, including HBr and Cl.sub.2, wherein a first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness; purging the first etchant from the reaction chamber; introducing a second etchant, including CHF.sub.3 and Argon, into the reaction chamber for etching the high permittivity layer; etching selected portions of the high permittivity layer, whereby the high permittivity layer is reduced to a second thickness; and forming a second set of gate electrodes on the selected portions of the high permittivity layer having the second thickness.