Patent ID: 6620717
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of manufacturing an integrated circuit comprising:depositing a charge-trapping material over a semiconductor substrate; forming first and second bitlines in the semiconductor substrate; depositing a wordline material over the charge-trapping material; depositing a hard mask material over the wordline material; depositing a disposable anti-reflective coating material over the hard mask material; depositing a photoresist material over the disposable anti-reflective coating material; processing the photoresist material and the disposable anti-reflective coating material to form a patterned photoresist material and a patterned disposable anti-reflective coating material; processing the hard mask material using the patterned photoresist material and the patterned disposable anti-reflective coating material to form a patterned hard mask material; removing the patterned photoresist material; substantially simultaneously removing the patterned disposable anti-reflective coating material and processing the wordline material using the patterned hard mask material to form a wordline; and removing the patterned hard mask material.