Patent ID: 6706582
Filing Date: 2004-03-16
Classification: H01L

Abstract:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:(a) forming a well of a first conduction type on a main surface of a semiconductor substrate; (b) forming a gate electrode over said well; (c) introducing an impurity of a second conduction type into said well in the existence of said gate electrode to form a first semiconductor region of the second conduction type; (d) implanting an impurity of the first conduction type vertically with respect to the main surface of said semiconductor substrate so that the impurity of the first conduction type is introduced into said well thereby forming a second semiconductor region of the first conduction type at a lower portion of said first semiconductor region; (e) implanting an impurity of the first conduction type obliquely relative to the main surface of said semiconductor substrate so that the impurity of the first conduction type is introduced into said well thereby forming a third semiconductor region of the first conduction type between said first semiconductor region and said second semiconductor region; (f) after the step (e), forming a first insulating film on side walls of said gate electrode; and (g) introducing an impurity of the second conduction type into said well in the existence of said first insulating film to form a fourth semiconductor region of the second conduction type, so that MISFET is formed, wherein a dosage of the impurity introduced in the step (e) is larger than a dosage of the impurity introduced in the step (d).