Patent ID: 8255751
Filing Date: 2012-08-28
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. first core functional logic that includes wrapper circuitry, the first core functional logic having functional inputs, functional outputs, a first wrapper serial input, a first wrapper serial output, and first wrapper control inputs; B. first test controller circuitry having a serial output connected to the first wrapper serial input, a serial input connected to the first wrapper serial output, control outputs connected to the first wrapper control inputs, a scan input, and a scan output; C. second core functional logic that includes wrapper circuitry, the second core functional logic having functional inputs, functional outputs, a second wrapper serial input, a second wrapper serial output, and second wrapper control inputs; D. second test controller circuitry having a serial output connected to the second wrapper serial input, a serial input connected to the second wrapper serial output, control outputs connected to the second wrapper control inputs, a scan input, and a scan output; and E. scan router circuitry having a device scan in lead connected to the scan input of the first test controller, a device scan out lead selectively coupled to the scan output of the first and second test controller circuitry, a scan in output connected to the scan input of the second test controller circuitry and selectively connected to the scan output of the first test controller circuitry and the device scan in lead, and control leads.