Patent ID: 6292042
Filing Date: 2001-09-18
Classification: H03K

Abstract:
A phase splitter comprising:a first circuit to provide a first output signal with a phase defined by a phase of an input signal;a second circuit to provide a second output signal with a phase defined by inverting the phase of the input signal; andan inverter to invert the input signal and to supply an inverted input signal to the first and second circuits,wherein the first and second circuits each receive the input signal, the inverted input signal, a reference voltage, and a supply voltage,wherein the first circuit comprises:a first transmission gate having a PMOS transistor with a control terminal adapted to be applied with the input signal and an NMOS transistor with a control terminal adapted to be applied with a signal from the inverter, the first transmission gate selectively providing a high level signal;a second transmission gate having an NMOS transistor with a control terminal adapted to be applied with the input signal and a PMOS transistor with a control gate adapted to be applied with a signal from the inverter, the second transmission gate selectively providing a low level signal, andwherein the second circuit comprises:a third transmission gate having an NMOS transistor with a control terminal adapted to be applied with the input signal and a PMOS transistor with a control gate adapted to be applied with a signal from the inverter, the third transmission gate selectively providing a high level signal; and,a fourth transmission gate having a PMOS transistor with a control terminal adapted to be applied with the input signal and an NMOS transistor with a control gate adapted to be applied with a signal form the inverter, the fourth transmission gate selectively providing a low level signal, wherein, at a low level of the input signal, the fourth transmission gate is operative to provide a low level signal having a phase that is equal to the input signal, and the first transmission gate is operative to provide a high level signal having a phase that is inverted relative to the input signal.