Patent ID: 7795132
Filing Date: 2010-09-14
Classification: H01L

Abstract:
1. A process for fabricating a cross-point memory element for a memory array comprising: applying a first lithography step to a composite multilayer structure that includes a substrate, a dielectric multilayer, and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer and in the dielectric multilayer; applying a first sequence of etching and deposition steps to form a plurality of first conductors on an area of the substrate within the first channels; applying a sequence of deposition steps to fill the plurality of first channels with a dielectric material on the first conductor and form a second resist material layer on the dielectric material thereby forming a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; applying a second sequence of etching and deposition steps to form the plurality of second channels and a plurality of connectors that make electrical contact with segments of the plurality of first conductors exposed in the second channels; and applying a third sequence of etching and deposition steps to form a plurality of second conductors that contact the connectors within the plurality of second channels wherein the second resist material layer is a composite of multiple resist layers comprising: a first layer of organic resist material disposed over the dielectric material filling the plurality of first channels; a second layer of hard mask material disposed over the first layer of organic resist material; and a third layer of resist material disposed over the second layer of hard mask material.