Patent ID: 7256108
Filing Date: 2007-08-14
Classification: H01L

Abstract:
1. A method for reducing semiconductor die warpage comprising: securing an anti-warpage backgrinding tape to a first side of a semiconductor wafer; backgrinding a second side of the wafer; securing the second side of the wafer to dicing tape so that the anti-warpage backgrinding tape is exposed; forming an array of grooves through the anti-warpage backgrinding tape and through the wafer to create individual die structure comprising semiconductor die with anti-warpage tape elements on first sides of the semiconductor die, the first sides of the semiconductor die corresponding to the first side of the wafer; removing a chosen die structure from the dicing tape; adhering a second side of a chosen die of the chosen die structure to a substrate, the second side of the chosen die corresponding to the second side of the wafer; and removing the anti-warpage tape element from the adhered die.