Patent ID: 7134107
Filing Date: 2006-11-07
Classification: G06F

Abstract:
1. A method for determining detail of analysis in a circuit design, comprising: identifying pull-up driver transistors of at least one stage of the circuit design; identifying pull-down driver transistors of the stage; processing configuration commands associated with control signals of the pull-up and pull-down driver transistors to determine if the pull-up driver transistors and pull-down driver transistors are tied on or tied off; determining whether the stage is without drive fight and has zero switching current by determining whether any one of the following is true: (a) all pull-down driver transistors are tied off and all pull-up driver transistors are tied on, (b) all pull-down driver transistors are tied on and all pull-up driver transistors are tied off, (c) all pull-down driver transistors are tied off and all pull-up driver transistors are tied off, (d) all pull-up driver transistors are on or all pull-up driver transistors are off and there are no pull-down driver transistors, and (e) all pull-down driver transistors are on or all pull-down driver transistors are off and there are no pull-up driver transistors; and performing detailed analysis of the stage if the stage has drive fight or switching current.