Patent ID: 6735128
Filing Date: 2004-05-11
Classification: G11C

Abstract:
A data output driver of a semiconductor memory device, comprising:a register for receiving and storing a plurality of first parallel data in synchronization with a clock signal and for outputting a plurality of second parallel data; a controller for comparing a plurality of parallel data currently inputted to the register with a plurality of parallel data previously inputted to the register in response to a delayed clock signal obtained by delaying the clock signal for a predetermined time and calculating the number of data transitions based on the comparison result, and for generating a control signal according to the calculated number of data transitions; a clock signal delay part for delaying the clock signal according to a logic level of the control signal from the controller in order to generate a pair of corrected clock signals; a data selecting part for selectively outputting odd- or even-numbered data among the plurality of second parallel data; and an output driving part for buffering and outputting output data of the data selecting part.