Patent ID: 8302057
Filing Date: 2012-10-30
Classification: G06F,H01L

Abstract:
1. A semiconductor integrated circuit comprising: a region for a standard cell array, wherein: a plurality of cells for at least one cell function are located in the standard cell array, each of the plurality of cells includes an output signal driving section transistor configured to drive an output signal, a cell group includes some of the plurality of cells having the same cell function and different sizes of output signal driving section transistors, with respect to the transistor size in the output signal driving section of each of the plurality of cells, a specific size of a transistor layout device provided in the cell as a single device is defined as reference size X[l], θ indication according to the reference size X[l] defines p types of transistor layout devices distinguished by p types of sizes expressed by X[(l/2)·θ a first cell belongs to the cell group, the transistor size in the output signal driving section is equal to or greater than X[(l/2)·θ], based on the reference size X[l], and the transistor in the output signal driving section of the cell is laid out within the cell by repeatedly placing one or multiple ones of a transistor layout device selected from the p types of transistor layout devices in accordance with the first cell.