Patent ID: 7856577
Filing Date: 2010-12-21
Classification: G06F,G11C

Abstract:
1. A memory testing system for testing a plurality of memory locations in an electronic memory device, comprising: a programmable memory device integrated into said electronic memory device that receives and stores a first compiled memory testing program, and that receives and stores a second compiled memory testing program that is different from said first compiled memory testing program such that said programmable memory device is rewritten with said second compiled memory testing program; a processor in communication with said programmable memory device that reads and executes instructions from said first compiled testing program stored in said programmable memory device while said programmable memory device stores said first compiled memory testing program and that reads and executes instructions from said second compiled memory testing program when said programmable memory device is rewritten to store said second compiled memory testing program; and a command interpreter that receives data from said processor related to said first and said second compiled memory testing programs, that interprets said received data from said processor into commands to be executed during memory testing, and executes said commands to access and test memory locations in said plurality of memory locations of said electronic memory device.