Patent ID: 6618282
Filing Date: 2003-09-09
Classification: G11C

Abstract:
A ROM system for storing information in an array of bit cells, the system including:a substrate; a plurality of columns of bit cells; wherein the plurality of columns of bits cells includes a first column of bit cells, wherein a first bit cell in the first column of bit cells includes a first bit cell region disposed in the substrate, wherein a first transistor is disposed in the first bit cell region, wherein a second bit cell in the first column of bit cells includes a second bit cell region disposed in the substrate, wherein the second bit cell region consists of an isolating dielectric region; wherein the plurality of columns of bit cells includes a second column of bit cells, wherein a third bit cell of the second column of bit cells includes a third bit cell region disposed in the substrate, wherein the third bit cell region consists of an isolating dielectric region, wherein a fourth bit cell of the second column of bit cells includes a fourth bit cell region disposed in the substrate, wherein a second transistor is formed in the fourth bit cell region; a sensing circuit wherein the sensing circuit is coupled to the first column of bit cells, and to the second column of bit cells, wherein in response to a voltage applied the first bit cell the sensing circuit detects a current flow through the first transistor and outputs a first signal, wherein in response to a voltage applied to the second bit cell the sensing circuit detects an absence of current in the second bit cell, and outputs a second signal, wherein in response to a voltage applied to the third bit cell, the sensing circuit detects an absence of current flow in the third bit cell and outputs the first signal, wherein when a voltage is applied to the fourth bit cell the sensing circuit detects current flow through the second transistor and outputs the second signal.