Patent ID: 6622240
Filing Date: 2003-09-16
Classification: G06F

Abstract:
An apparatus that minimizes instruction gaps behind a branch instruction processed in a multistage pipelined processor that includes an instruction fetch unit that fetches instructions during one or more instruction fetch stages, one or more instruction decode stages, and one or more execution stages, comprising:a pre-branch instruction that corresponds to a branch instruction, said pre-branch instruction is placed a sufficient number of instructions ahead of said branch instruction to insure that said pre-branch instruction exits the decode stage of the pipeline at the same time that said branch instruction exits the first instruction fetch stage of said pipeline, said pre-branch instruction comprises a branch instruction and one or more bits that identify the pre-branch instruction as a pre-branch instruction, said pre-branch instruction is decoded by the processor and causes the instruction fetch unit either to begin fetching instructions at a branch target address or to continue fetching instructions along the main execution path.