Patent ID: 6285617
Filing Date: 2001-09-04
Classification: G11C

Abstract:
A semiconductor memory device starting a refresh operation in accordance with an order of activation of first and second control signals, comprising:a control circuit generating an internal control signal activated/inactivated in accordance with activation/inactivation of said second control signal, respectively, and designating start of said refresh operation in accordance with activation of said first control signal when both of said second control signal and said internal control signal are in an inactive state;a memory cell array having a plurality of memory cells arranged in a matrix, said memory cell array being divided into a plurality of row blocks in a row direction of said memory cells, each of said plurality of row blocks including a plurality of word lines arranged correspondingly to a plurality of memory cell rows; anda row selection circuit selecting one of said memory cell rows in each of said plurality of row blocks in accordance with an address signal, said row selection circuit being controlled by said control circuit for activating one of said plurality of word lines corresponding to the selected memory cell row in at least one of said plurality of row blocks during a normal reading/writing operation and activating one of said plurality of word lines corresponding to the selected memory cell row in each of a greater number of said row blocks during said refresh operation than during said normal reading/writing operation.