Patent ID: 8811069
Filing Date: 2014-08-19
Classification: G11C

Abstract:
1. A memory device comprising: a memory cell array; an access control circuit which accesses the memory cell array to perform a read operation or a write operation; a control signal generation circuit which generates a control signal for controlling an operation of the access control circuit; and a variable delay circuit which generates a delay signal DS by variably delaying a clock signal CK by amount of delay set according to an external digital code EXS including a plurality of bits, wherein the control signal generation circuit adjusts an activation timing of the control signal WLEN, PREN, SAEN and CCEN in response to the delay signal DS, wherein the access control circuit which comprises a sense amplifier (S/A) & write driver block functions as a write driver which writes data received through data I/O circuit to the memory cell array during the write operation and functions as an S/A which senses and amplifies data output from the memory cell array and transmits the data to the data I/O circuit during the read operations, wherein the external digital code EXS is input from outside of the memory device.