Patent ID: 6086627
Filing Date: 2000-07-11
Classification: G06F

Abstract:
An electrostatic discharge (ESD) verification system for a chip design comprising:identification means for identifying input output (I/O) pads, power and power return pads, I/O cells and electrostatic discharge (ESD) devices;means for creating a network including ESD dummy shapes, said ESD dummy shapes representing a shape of said ESD devices, said network comprising wires connecting I/O pads, said power and power return pads, and said I/O cells to said ESD dummy shapes;verification means for verifying that said wires in said network meets a minimum ESD protection criteria, said verification means further for applying a bias to said wires to remove said wires below a minimum constraint such that said wires appear as opens when checked by verification means indicating that a particular said I/O cell is not connected to one of said electrostatic discharge devices.