Patent ID: 7838910
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A memory device comprising: a semiconductor substrate; a plurality of wordlines on the semiconductor substrate; a ground select line on the semiconductor substrate on one side of the wordlines; a string select line on the semiconductor substrate on the other side of the wordlines, wherein the wordlines extend between the ground select line and the string select line wherein the both sides of each of the wordlines, the ground select line and the string select line have a pair of spacers selected from first and second spacers; the first spacer being disposed between the wordlines, between a first side of the ground select line and the wordline adjacent to the ground select line and between a first side of the string select line and the wordline adjacent to the string select line; the second spacer disposed on a second side of the ground select line and a second side of the string select line, wherein the first sides are the sides of the string or ground select line that face the adjacent wordline and the second spacer is opposite the first spacer, a common source line formed between the second spacers of two adjacent ground select lines; and a bitline contact formed between the second spacers of two adjacent string select lines, wherein the second spacer is formed of a different material from that of the first spacer, wherein the second spacer is absent from between the wordlines and the first spacer is absent from the second side of both the ground select line and the string select line.