Patent ID: 8547257
Filing Date: 2013-10-01
Classification: H03M

Abstract:
1. An analog-to-digital converter, comprising: a first analog-to-digital converter (ADC) stage, having an input receiving an analog input signal, and having a digital output, for generating a data word at the digital output corresponding to a sample of the analog input signal; a second ADC stage, having an input receiving the analog input signal, and having a digital output, for generating a data word at the digital output corresponding to a sample of the analog input signal and according to an error correction code; and decision logic, having a digital input coupled to the digital outputs of the first and second ADC stages, for decoding the data words from the first and second ADC stages into a decoded digital word responsive to the digital outputs of the first and second ADC stages, wherein the decision logic decodes the data words from the first and second ADC stages according to an error correction code to present, at an error output, an error word indicating errored bits in the digital data word presented by the first ADC stage; and further comprising: