Patent ID: 6380084
Filing Date: 2002-04-30
Classification: H01L

Abstract:
A method to form robust dual damascene interconnects by de-coupling via and connective line trench filling in the manufacture of an integrated circuit device comprising:providing a conductive layer overlying a semiconductor substrate; depositing a silicon nitride layer overlying said conductive layer; depositing a first dielectric layer overlying said silicon nitride layer; depositing a shielding layer overlying said first dielectric layer; patterning said shielding layer, said first dielectric layer, and said silicon nitride layer to form via trenches that expose a part of said conductive layer; depositing a first barrier layer overlying said conductive layer and lining said via trenches; filling said via trenches with a first copper layer; polishing down said first copper layer and said first barrier layer to complete vias; depositing a second barrier layer overlying said vias and said first dielectric layer; patterning said second barrier layer and said shielding layer to form via caps overlying said vias; depositing a second dielectric layer overlying said via caps and said first dielectric layer; depositing a capping layer overlying said second dielectric layer; patterning said capping layer and said second dielectric layer to form connective line trenches that expose a part of said via caps; depositing a third barrier layer overlying said capping and said via caps and lining said connective line trenches; anisotropically etching down said third barrier layer and said via caps to form barrier sidewall spacers lining said connective line trenches and to expose a part of said first copper layer; filling said connective line trenches with a second copper layer; and polishing down said second copper layer to complete connective lines for said dual damascene interconnects in the manufacture of said integrated circuit device.