Patent ID: 8754681
Filing Date: 2014-06-17
Classification: H03L

Abstract:
1. A system, comprising: a plurality of processor cores; a memory component; a content addressable memory; a first phase locked loop circuit to output a first clock output for the plurality of processor cores; a second phase locked loop circuit to output a second clock output for the memory component; a third phase locked loop circuit to output a third clock output for the content addressable memory; a plurality of first divider circuits coupled to the first phase locked loop circuit to frequency scale the first clock output for consumption by the plurality of processor cores, in which each processor core from the plurality of processor cores is associated with a dedicated first divider circuit; a second divider circuit coupled to the second phase locked loop circuit to frequency scale the second clock output for consumption by the memory component; and a plurality of third divider circuits coupled to the third phase locked loop circuit to frequency scale the third clock output, in which the content addressable memory is associated with a dedicated third divider circuit, wherein a first divider circuit, from among the plurality of first divider circuits the second divider circuit, or a third divider circuit from the plurality of third divider circuits, is implemented as a dynamic frequency selection divider, the dynamic frequency selection divider bein controlled by a counter.