Patent ID: 8874846
Filing Date: 2014-10-28
Classification: G06F

Abstract:
1. A method comprising: using a computer system to identify a region in a phase change memory, the region comprising a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a first current state of the memory cells to a desired state of the memory cells and a second expected value when a write operation changes a specified state of the memory cells to the desired state of the memory cells, wherein the second expected value is closer than the first expected value to a desired value of the write performance characteristic; setting the plurality of memory cells in the region to the specified state; and writing data into the plurality of memory cells responsive to the setting, wherein each of the memory cells consist of one of a SET state and a RESET state and wherein the desired state is selected to be either the RESET state or the SET state based on which state has a longer writer latency.