Patent ID: 7928949
Filing Date: 2011-04-19
Classification: G09G

Abstract:
1. A source driver of a display panel, comprising: a channel state signal generator for generating a first channel state signal that is at a first logic state for a time period depending on an adjustable state length data that is comprised of multiple bits stored into a register; and a plurality of first switches that are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is at the first logic state for charge share of the source lines, wherein the adjustable state length data is not a periodic signal used for generating the channel output signal, and wherein the adjustable state length data is not a periodic signal with pulses used for timing of said charge share, and wherein the time period during which the first channel state signal is at the first logic state is determined by the state length data, and is independent of time periods during which a load control signal is activated, and wherein said load control signal is activated during a part or an entirety of a blanking period when image data for determining said channel output signals is not latched by the source driver.