Patent ID: 6048766
Filing Date: 2000-04-11
Classification: H01L

Abstract:
A memory device fabrication method, comprising:forming a first polysilicon plate over a substrate;forming a dielectric stack over the first polysilicon plate, the dielectric stack including a relatively high permittivity layer disposed between two relatively low permittivity buffer layers; andforming a second polysilicon plate over the dielectric stack;wherein forming the dielectric stack includes:forming a first buffer layer over the first polysilicon plate;forming a second buffer layer over the first buffer layer, wherein the first and second buffer layers form one of the two relatively low permittivity layers;forming the relatively high permittivity layer over the second buffer layer;forming a third buffer layer over the relatively high permittivity layer; andforming a fourth buffer layer over the third buffer layer, wherein the third and fourth buffer layers form the other of the two relatively low permittivity layers;wherein the second polysilicon plate is formed over the fourth buffer layer.