Patent ID: 6650712
Filing Date: 2003-11-18
Classification: H04L

Abstract:
A receiver for receiving a FSK signal having a first frequency corresponding to a binary â€œ0â€  and a second frequency corresponding to a binary â€œ1â€ , the receiver comprising:a finite series of delay elements, each element having an input and an output terminal and being configured to introduce a predetermined delay interval corresponding to a sampling period of the received signal, and where the input terminal of a first element of the finite series of delay elements is coupled to an input terminal of the receiver; an arithmetic unit having a plurality of input terminals and an output terminal, where a first one of the plurality of input terminals is coupled to the input terminal of the first element of the finite series of delay elements and where each remaining one of the plurality of input terminals is coupled to the output terminal of a corresponding one of the delay elements, where the arithmetic unit is configured to generate a metric signal at the output terminal of the arithmetic unit using a phase independent equation; and an integration and decision unit having an input terminal coupled to the output terminal of the arithmetic unit, where the integration and decision unit is configured to compare the metric signal to a threshold value to obtain a binary sample and integrate multiple binary samples in a baud interval of the FSK signal in order to generate a binary data signal at an output terminal of the integration and decision unit.