Patent ID: 6353553
Filing Date: 2002-03-05
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a nonvolatile memory cell array including a plurality of memory cells; and a control circuit for controlling a write operation, a read operation and an erase operation for said plurality of memory cells, wherein said control circuit writes binary data or multivalued data in a memory cell subjected to writing in response to a write request and reads said binary data or said multivalued data in response to contents written in a memory cell subjected to reading in said read operation, and wherein said control circuit sets said memory cell subjected to writing in either a first state for erasing or an n-th state different from said first state when writing said binary data while setting said memory cell subjected to writing in any of n (at least three) different states in total ranging from said first state to said n-th state when writing said multivalued data.