Patent ID: 7251188
Filing Date: 2007-07-31
Classification: G06F

Abstract:
1. A memory access interface for connecting a memory to a micro-controller and a first circuitry, the micro-controller being capable of transmitting a first group address signals and a second group address signals, the micro-controller being capable of transmitting the first group address signals or accessing data signals via an address/data bus, the memory access interface comprising: an address holder for receiving the first group address signals on the address/data multiplexing bus and a first enable signal outputted from the micro-controller, and outputting the first group address signals when the first enable signal is enabled; and a multiplexer for receiving the first group address signals outputted from the address holder, the second group address signals outputted from the micro-controller, and third address signals outputted from the first circuitry, the multiplexer being controlled by a first control signal of the micro-controller for selectively outputting the first and second group address signals or outputting the third address signals to the memory; wherein the micro-controller and the first circuitry can access the data of the memory according to the first enable signal.