Patent ID: 6466081
Filing Date: 2002-10-15
Classification: G05F

Abstract:
A temperature stable bias circuit comprising:a first connection for a first voltage source; a second connection for a second voltage source having a lower potential than the first voltage source, an operational amplifier having a positive input, a negative input and an output; a first, N-channel, field effect transistor (FET) having a source, and having a gate and a drain connected together and to the positive input to supply a reference voltage at the positive input based on a reference current and a transistor temperature coefficient of the first FET; a second, N-channel, FET having a drain, having a source connected to the negative input, and having a gate connected to the output to provide the reference current; a load resistor having a first terminal connected to the negative input and to the source of the second FET and having a second terminal connected to the second connection to develop a load voltage across the resistor based on the reference current and in accordance with a resistor temperature coefficient; a third, N-channel, FET having a source connected to the second connection, having a gate connected to the gate and drain of the first FET to form a current mirror therewith, and having a drain; a fourth, P-channel, FET having a source connected to the first connection, having a drain connected to the positive input and to the drain and gate of the first FET, and having a gate; a fifth, P-channel, FET having a source connected to the first connection, and having a gate and a drain connected together and to the gate of the fourth FET and the drain of the second FET; a sixth, N-channel, FET having a drain connected to the first connection, having a gate connected to the drain of the third FET, and having a source connected to the drain of the fourth FET, the gate and drain of the first FET, and the positive input; a seventh, P-channel, FET having a source connected to the first connection and having a gate and a drain connected together and to the gate of the sixth FET and the drain of the third FET; and wherein the operational amplifier output varies to supply the reference current across the load resistor, developing the load voltage equal to the reference voltage for a range of temperatures in accordance with the transistor temperature coefficient and the resistor temperature coefficient.