Patent ID: 6501116
Filing Date: 2002-12-31
Classification: H01L

Abstract:
A semiconductor memory device, comprising:a memory array region constituted of a plurality of memory cells formed in matrix on a main surface of a semiconductor substrate, wherein each of said plurality of memory cells comprises: a reading MIS transistor having a source region and a drain region formed on the main surface of said semiconductor substrate, a channel forming region formed on the main surface of said semiconductor substrate between said source region and said drain region, and a first gate electrode formed above the main surface of said semiconductor substrate of said channel forming region via a first gate insulating film; and a writing MIS transistor having a source region, a channel forming region, and a drain region formed in a layered structure, which are arranged on the first gate electrode of said reading MIS transistor and extends in the vertical direction to the main surface of said semiconductor substrate, said writing MIS transistor also having a second gate electrode formed on a sidewall of said layered structure via a second gate insulating film, the first gate electrode of said reading MIS transistor has both end portions in the column direction, which terminate on an element isolation regions, and is formed so as to have a convex-shaped cross section in the column direction, a length of said layered structure in the column direction is shorter than that of said first gate electrode in the column direction, a first bit line electrically connected to the drain region of said writing MIS transistor is formed on said layered structure, and a second bit line electrically connected to either of the source region or the drain region of said reading MIS transistor is formed on said first bit line.