Patent ID: 6349052
Filing Date: 2002-02-19
Classification: H01L

Abstract:
A DRAM cell arrangement,having memory cells each comprising a transistor and a capacitor, in which a first substrate (1) with a depression (V) is provided, in which areas of the depression (V) are provided with a capacitor dielectric (KD) of the capacitor, in which the depression (V) is filled with a storage node (SP) of the capacitor, in which the transistor is arranged in a second substrate (2), in which a first source/drain region (S/D1) of the transistor adjoins at least a first surface (O1) of the second substrate (2), in which a second source/drain region (S/D2) of the transistor adjoins at least a second surface (O2), opposite to the first surface (O1), of the second substrate (2), in which the first substrate (1) and the second substrate (2) are connected to one another in such a way that an insulating layer (I) is arranged between them, which insulating layer adjoins the storage node (SP) and the second surface (O2) of the second substrate (2), in which the second substrate (2) has first trenches (G1), which isolate source/drain regions (S/D1, S/D2) of mutually adjacent transistors from one another and which each cut through the second substrate (2) and the insulating layer (I), in which at least one contact (K) is arranged in the insulating layer (I), which contact adjoins one of the first trenches (G1), the second source/drain region (S/D2) and the storage node (SP), in which bit lines (B) and word lines (W1) running transversely with respect thereto are provided, which are connected to the memory cells.