Patent ID: 6376320
Filing Date: 2002-04-23
Classification: H01L

Abstract:
A method for fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, the method including the steps of:A. forming a drain extension junction and a source extension junction in said active device area of said semiconductor substrate; B. forming spacers to cover said drain extension junction and said source extension junction and to cover sidewalls of said gate structure; C. forming a drain contact junction adjacent said drain extension junction and forming a source contact junction adjacent said source extension junction by implanting a contact junction dopant into exposed regions of said active device area of said semiconductor substrate; D. forming a hardmask dielectric material to cover a top surface of said gate structure; E. forming a drain silicide with said drain contact junction that is exposed and forming a source silicide with said source contact junction that is exposed, wherein said drain silicide and said source silicide have a first thickness and are comprised of a first silicide material; and wherein said hardmask dielectric material that covers said top surface of said gate structure prevents formation of silicide with said gate structure during formation of said drain silicide and said source silicide; F. depositing an encapsulating dielectric material, in a dielectric deposition process, to cover said drain silicide and said source silicide, and minimizing depth of said drain and source extension junctions by performing said dielectric deposition process at a temperature in a range of less than about 400Â° Celsius; G. etching away said hardmask dielectric material from said top surface of said gate structure to expose said top surface of said gate structure; and H. forming a gate silicide with said gate structure, wherein said gate silicide has a second thickness and is comprised of a second silicide material; and wherein said encapsulating dielectric material covering said drain silicide and said source silicide prevents further formation of said drain silicide and said source silicide during formation of said gate silicide; and wherein said first silicide material of said drain silicide and said source silicide is different from said second silicide material of said gate silicide, and wherein said first thickness of said drain silicide and said source silicide is less than said second thickness of said gate silicide.