Patent ID: 6806518
Filing Date: 2004-10-19
Classification: H01L

Abstract:
A NAND flash memory device comprising:a semiconductor substrate having a main memory cell array region and a dummy cell array region surrounding the main memory cell array region; a plurality of parallel main active regions arranged at the substrate in the main memory cell array region, the main active regions being extended to the substrate in the dummy cell array region; a dummy active region coupled to ends of the main active regions, the dummy active region crossing the main active regions; a plurality of common source lines crossing over the main active regions in the main memory cell array region; string selection lines crossing over the main active regions in the main memory cell array region, the string selection lines being arranged at both sides of the respective common source lines; ground selection lines crossing over the main active regions, the respective ground selection lines intervening between each of the main string selection lines and each of the common source lines; a plurality of parallel wordlines crossing over the main active regions, the wordlines intervening between respective string selection lines and respective ground selection lines; and at least one dummy wordline crossing over the main active regions in the dummy cell array region.