Patent ID: 7397135
Filing Date: 2008-07-08
Classification: H01L,Y10T

Abstract:
1. A semiconductor chip comprising: a silicon substrate; multiple transistors on said silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, a third metal interconnect over said silicon substrate and between said first and second metal interconnects, and a fourth metal interconnect over said silicon substrate and between said third and second metal interconnects, wherein said first, second, third and fourth metal interconnects are separated from one another by an insulating material, and wherein said first metallization structure comprises electroplated copper; a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure, over said dielectric layer and on said third and fourth metal interconnects, wherein said first, second, third and fourth metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip; a polymer layer on said passivation layer and over said third and fourth metal interconnects, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening through said passivation layer and through said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening through paid passivation layer and through said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and a second metallization structure on said polymer layer, over said passivation layer, over said third and fourth metal interconnects and over said first and second contact points, wherein said third and fourth metal interconnects are directly under said second metallization structure and are not connected to said second metallization structure through any opening through said polymer layer under said second metallization structure, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said second metallization structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.