Patent ID: 6353341
Filing Date: 2002-03-05
Classification: G01R

Abstract:
A circuit for disncriminating between a clock signal and signal interference on the clock signal, comprising:means for monitoring the clock signal to detect a transition from a first logic state to a second logic state; and means for ignoring subsequent transitions of the clock signal for a predetermined time period after detection of the first-mentioned transition, wherein the means for ignoring comprises a delay circuit and a logic circuit, the logic circuit comprising: a first logic gate having a first input terminal coupled to receive the clock signal, a second input terminal coupled to an output terminal of the delay circuit, and an output terminal coupled to provide an output clock signal; and a second logic gate having a first input terminal coupled to the output terminal of the delay circuit, a second input terminal coupled to receive an enable signal, and an output terminal coupled to a reset terminal of the means for monitoring.