Patent ID: 6240525
Filing Date: 2001-05-29
Classification: G11C

Abstract:
A structure for re-addressing memory locations between first and second partitioned sections of a memory, comprising:an address generator for generating an address corresponding to a memory cell within said first partitioned section of said memory in response to a request made by an associated CPU;a first register having an input port coupled to receive said address and having an output port, said first register storing information indicative of whether said memory cell is defective;a second register having an input port coupled to receive said address and having an output port, said second register storing cell address mappings between corresponding first and second partitioned sections of said memory; anda multiplexer having a first input terminal coupled to receive said address, a second input terminal coupled to said output terminal of said second register, a control terminal coupled to said output terminal of said first register, and an output terminal coupled to an address input line of said memory, said multiplexer forwarding either said address or one of said address mappings to said memory in response to said information indicative of whether said memory cell is defective.