Patent ID: 6335632
Filing Date: 2002-01-01
Classification: H04L

Abstract:
A CMOS terminator circuit for connection to a network carrying small logic level signals from a network's first circuit to a network's second circuit in which a network's input terminal connects the terminator circuit to the network's second circuit to act as a terminator on a data line passing data from said first circuit to said second circuit, comprising:a terminator reference circuit (30) coupled to a terminator input circuit (31) in said terminator, said terminator input circuit being coupled to said network input terminal for connecting the network's first circuit to the network's second circuit, said terminator reference circuit (30) generating two reference voltage levels, one first level voltage for a first node (14) and and a second level voltage for a second node of said terminator reference circuit, the first voltage level of said terminator reference circuit being at a level above a tuned reference voltage and the second voltage level of said terminator reference circuit being at a level below said tuned reference voltage, said the first voltage level and said second voltage level being supplied on separate paths from said first and second nodes respectively to a terminator input circuit (31) having a pair of coupled mirror devices for control of the logic level provided at said network's input terminal which connects said terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit, and said terminator reference circuit (30) including a control test circuit enabling a driver for said network's first circuit to be turned on to send out the data over the communication line, or for leakage test.