Patent ID: 9024853
Filing Date: 2015-05-05
Classification: G09G

Abstract:
1. A liquid crystal device drive circuit, comprising a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units, each of the pixel units comprising a thin-film transistor, a common electrode, a pixel electrode electrically connected to the thin-film transistor, a storage capacitor, and a timer switch, the pixel electrode being electrically connected to the thin-film transistor, the common electrode and the pixel electrode constituting a liquid crystal capacitor, the storage capacitor being connected in parallel to the liquid crystal capacitor, the thin-film transistor comprising a gate terminal and a source terminal, the gate terminal being electrically connected to the gate line via the timer switch, the thin-film transistor being electrically connected to the gate driver and the source driver respectively by means of the gate lines and the data lines; wherein the timer switch comprises an electrical switch and a timer, the electrical switch comprising first, second, and third pins, the timer having an end electrically connected to the gate line to receive a signal from the gate line for activation of the timer and another end electrically connected to the second pin to apply a signal to set and maintain the electrical switch in a closed condition for a predetermined period of time, the first pin being electrically connected to the gate line, the third pin being electrically connected to the gate terminal of the thin-film transistor; and wherein the gate lines comprise a rectangular gate signal, the gate rectangular signal controlling conduction or cutoff of the thin-film transistors, the rectangular gate signal comprising a plurality of high levels and a plurality of low levels, the plurality of high levels and the plurality of low levels being arranged in a predetermined manner, each of the high levels comprising first and second time intervals, which are supplied to each of the timer switches to allow the timer switch to be closed in the first time interval and open in the second time interval, where the first and second time intervals of each of the timer switches are determined individually and thus different for each of the timer switches.