Patent ID: 8212584
Filing Date: 2012-07-03
Classification: H01L,H03K

Abstract:
1. A FinFET majority gate comprising: at least three inputs; an output; a pull-up network having at least three P-FinFETs connected in series, each of the at least three P-FinFETs has a front gate and a back gate independently coupled to one of the at least three inputs or one of the complements of the at least three inputs, the pull-up network coupled to the output through one of the at least three P-FinFETs; and a pull-down network having at least three N-FinFETs connected in series, each of the at least three N-FinFETs has a front gate and a back gate independently coupled to one of the at least three inputs or one of the complements of the at least three inputs, the pull-down network coupled to the output through one of the at least three N-FinFETs.