Patent ID: 6115791
Filing Date: 2000-09-05
Classification: G06F

Abstract:
A computer system, comprising:a processor bus for carrying cycles, said processor bus including a plurality of lines for carrying signals indicating the type of cycle being carried on said processor bus;a microprocessor coupled to said processor bus, said microprocessor including an internal write-back cache, wherein said microprocessor executes a special flush acknowledge cycle indicating completion of flushing of said internal cache after completion of the flushing of said internal cache, said special flush acknowledge cycle being indicated by driving a particular signal set onto said plurality of cycle type lines of said processor bus; andan external cache coupled to said processor bus, said external cache including a clear input for invalidating the data in the external cache memory; anda controller coupled to said processor bus and said external cache for detecting said flush acknowledge cycle, and for providing a clear signal to said external cache clear input in response to said detection.