Patent ID: 7170785
Filing Date: 2007-01-30
Classification: G11C,H01L

Abstract:
1. A nonvolatile memory, comprising: a memory array including a plurality of columns, each column of the plurality of columns including a plurality of memory cells arranged in a series having a first end and a second end, each memory cell including: a first pass transistor coupled to the first end of the series; a second pass transistor coupled to the second end of the series; a bit line coupled to the first pass transistor and the second pass transistor; and a plurality of word lines coupled to the top dielectrics of the plurality of memory cells, each word line of the plurality of word lines acting as a gate for memory cells coupled to said each word line; and logic coupled to the plurality of memory cells, said logic turning on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of a memory cell of the plurality of memory cells, thereby selecting part of the charge trapping structure corresponding to the source region or the drain region, and said logic applying a first bias arrangement to determine a charge storage state of the selected part of the charge trapping structure.