Patent ID: 6046927
Filing Date: 2000-04-04
Classification: G11C

Abstract:
A nonvolatile semiconductor memory device comprising:a silicon-on-insulator substrate including a handling wafer, a first insulating layer and a semiconductor layer stacked in that order;a first conductive layer for use as a bit line formed at least partially in the first insulating layer, wherein a part of the first conductive layer is electrically coupled to the semiconductor layer;a source region formed in the semiconductor layer and electrically connected to the first conductive layer;a drain region formed in the semiconductor layer;a second insulating layer formed over the semiconductor layer and between the source and drain regions;a second conductive layer for use as both a lower electrode and a gate electrode formed over the second insulating layer and between the source and drain regions;a ferroelectric layer formed over the semiconductor layer, wherein the ferroelectric layer is formed over an entire cell array area; anda third conductive layer for use as an upper electrode formed over the ferroelectric layer,wherein writing to memory cells and erasing from memory cells are performed by causing a potential difference between the upper electrode and the semiconductor layer to reverse a polarization of the ferroelectric layer,wherein a single memory cell is formed by only one transistor, andwherein the third conductive layer is connected to a word line and the drain region is connected to a drive line.