Patent ID: 6031410
Filing Date: 2000-02-29
Classification: H03M

Abstract:
A multiplexor comprising a first latch having a data input receiving a first data signal and controlled by a control signal in such a manner that when said control signal is at a first logical level, an output of said first latch outputs the data received at said data input of said first latch, and when said control signal is at a second logical level opposite to said first logical level, said output of said first latch becomes a dynamic node holding a last value of said output of said first latch when said control signal was at said first logical level, and a second latch having a data input receiving a second data signal and controlled by said control signal in such a manner that when said control signal is at said second logical level, an output of said second latch outputs the data received at said data input of said second latch, and when said control signal is at said first logical level, said output of said second latch becomes a dynamic node holding a last value of said output of said second latch when said control signal was at said second logical level, said output of said first latch and said output of said second latch being connected to each other in a wired connection.