Patent ID: 6151681
Filing Date: 2000-11-21
Classification: G06F,Y02D

Abstract:
A power management method which comprises the steps of:(a) providing a system having a plurality of clock operated circuits, each of said clock operated circuits being operable in response to the receipt of clock signals, with a first subplurality of said clock operated circuits receiving an uninterrupted stream of clock signals from a first clock and thereby being uninterruptably operable and a second subplurality of said clock operated circuits receiving a normally off interruptible stream of clock signals from a second clock and being normally inoperable, wherein the first and second clocks are continuously synchronized in phase and have a common operating frequency;(b) sampling said system for the presence of data signals being input to said system;(c) sending said clock signals from said second clock to said second subplurality of circuits in response to the sampling the presence of data signals being input to said system to cause said second subplurality of circuits to be operable; and(d) transmitting said data signals to said second subplurality of circuits after a time delay equal to or greater than the expired time from said step of sampling to said step of sending.