Patent ID: 6134149
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A chip erase circuit for erasing an integrated non-volatile memory array circuit device having memory cells of the type susceptible to the generation of band-to-band currents during erase operation, comprising:(a) timer means in said device for initiating a first and a second period of time;(b) control means in said device, responsive to said timer means, for applying a first erase current having a first voltage to said non-volatile memory array for said first period of time said first voltage supplied from a source external to said device;(c) means for increasing said first voltage to a second voltage, higher than said first voltage in said device; and(c) wherein said control means is responsive to said timer means for applying a second erase current, less than said first erase current at said second voltage from said increasing means to said non-volatile memory array for said first and second period of time.