Patent ID: 7409612
Filing Date: 2008-08-05
Classification: G01R

Abstract:
1. An integrated circuit comprising: a core circuit; terminals for coupling the core circuit to circuitry external to the integrated circuit, a test data input and a test data output; a boundary scan chain comprising cells coupled between the test data input and output in a shift register structure, each cell also coupled between a respective one of the terminals and the core circuit, a test control circuit arranged to switch the boundary scan chain between a functional mode, in which the cells permit signal flow between the terminals and the core circuit, and a test mode, in which test data is shifted serially through the cells along the boundary scan chain and in which the cells intercept signal flow between the respective ones of the terminals and the core circuit, wherein the test control circuit is arranged to execute an instruction to switch the boundary scan chain to a further mode, in which further mode selectable first ones of the cells transport data serially along the boundary scan chain while selectable second ones of the cells write or read data that has been or will be transported through the first ones of the cells in the further mode to or from the terminals from or to the scan chain.