Patent ID: 7145806
Filing Date: 2006-12-05
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a plurality of word lines and a plurality of bit lines, which cross each other, and electrically rewritable and non-volatile memory cells disposed at crossings thereof; a read/write circuit configured to write data into a selected memory cell with applying a write voltage to a selected word line, and detect a discharge state of a selected bit line to read data of the selected memory cell after having precharged the selected bit line to a certain voltage; and a controller configured to control said read/write circuit to execute a write sequence by repeat of a write operation and a verify-read operation for the selected memory cell in such a way as to start a precharge operation of the selected bit line for the verify-read operation prior to the ending time of the write operation in the write sequence.