Patent ID: 6838866
Filing Date: 2005-01-04
Classification: H01L

Abstract:
1. A process for measuring a depth of a source and drain of a MOS transistor, wherein the MOS transistor is formed on a semiconducting substrate on which a trench capacitor is formed and wherein a buried strap is formed between the MOS transistor and the trench capacitor, the process comprising the following steps: measuring resistances of the buried strap at a plurality of different depths of the buried strap; establishing a curve correlating the resistances with the depths of the buried strap; obtaining slopes of the resistances to the depths of the buried strap for the curve; and obtaining a critical depth corresponding to a minimum resistance before the slopes of the resistances to the depths of the buried strap reaches to zero, wherein the critical depth is the depth of a source and drain of a MOS transistor.