Patent ID: 8963907
Filing Date: 2015-02-24
Classification: G09G

Abstract:
1. A driving method, for a pixel circuit, the driving method comprising: supplying, when the pixel circuit is operated in a data writing period, a first control signal to the control terminal of a first switch so as to turn on the first switch and supplying the first control signal to turn off the first switch when the pixel circuit is not in the data writing period; and supplying a second, a third and a fourth control signals to the control terminals of a second, third and fourth switches, respectively, so as to turn off the second, third and fourth switches at the same time in the entire data writing period and thereby configuring the control terminal of a driving transistor to receive the data voltage in the entire data writing period; wherein the pixel circuit comprising the first switch, the second switch, the third switch, the fourth switch, and the driving transistor, wherein the switches and the driving transistor each have a first terminal, a second terminal and a control terminal configured to control turn-on or turn-off between its associated first and second terminals; the first terminal of the first switch is configured to receive a data voltage; the second terminal of the first switch, the second terminal of the third switch and the control terminal of the driving transistor are configured to be electrically coupled to a first connecting node; the first terminal of the second switch is configured to receive a first power voltage; the first terminal of the fourth switch is configured to receive a second power voltage; the first terminal of the third switch is configured to receive a third power voltage; the second terminal of the fourth switch and the first terminal of the driving transistor are configured to be electrically coupled to each other; the second terminal of the second switch and the second terminal of the driving transistor are configured to be electrically coupled to each other; a first capacitor, wherein one terminal of the first capacitor is configured to be electrically coupled to the first connecting node; a second capacitor, wherein one terminal of the second capacitor is configured to receive the second power voltage; another terminal of the first capacitor, the second terminal of the driving transistor and another terminal of the second capacitor are configured to be electrically coupled together; the second terminal of the first switch, the second terminal of the third switch and the control terminal of the driving transistor are configured to directly connect to a first connecting node.