Patent ID: 8849220
Filing Date: 2014-09-30
Classification: G06F,Y10T

Abstract:
1. An electronic device comprising: a plurality of circuit boards including a front I/O adapter circuit board, a front galvanic isolation circuit board adjacent the front I/O adapter circuit board, a switching circuit board adjacent the front galvanic isolation circuit board, and a back I/O adapter circuit board adjacent the switching circuit board; data processing circuitry carried by each of said plurality of circuit boards, wherein the front I/O circuit board carries circuitry for adapting data signals inputted from multiple ports to the front I/O circuit board for output to the front galvanic isolation circuit board, the front galvanic isolation circuit board carries circuitry providing multi-port protection and impedance matching for the data signals received from the front I/O circuit board, the switching circuit board carries multi-port communications processing circuitry for routing data signals among multiple ports, and the back I/O adapter circuit board carries galvanic isolation circuitry for an output port; and a plurality of elongate connectors electrically and mechanically coupling said plurality of circuit boards in a stacked spaced relation defining a plurality of levels; said plurality of elongate connectors comprising pairs of parallel first and second elongate connectors between adjacent circuit boards, and with each pair of parallel first and second elongate connectors being rotationally offset in successive levels.