Patent ID: 8699338
Filing Date: 2014-04-15
Classification: G11B

Abstract:
1. A signal processing circuit that supports an adaptable time rate, the signal processing arrangement comprising: a signal data source configured to supply signal data of a stored signal that is defined relative to an original time base; a signal reproduction rate adapter coupled to the signal data source and configured to output samples of an adapted signal defined relative to both an adapted time base and the original time base, wherein any point in the stored signal has two associated time values according to both the adapted time base and the original time base; a signal rendering device; a delaying buffer between the signal reproduction rate adapter and the signal rendering device configured to pass the samples to the signal rendering device; a rate controller configured to signal commands to change said adaptable time rate; and a time converter coupled between the rate controller and a control input of the signal reproduction rate adapter, configured to accept the commands, wherein some of the commands are accepted, control the adaptable time rate used by the signal reproduction rate adapter based on a last preceding accepted command, store information for a predetermined number of the accepted commands, detect when an effect of the accepted commands emerges from the delaying buffer, and disable the acceptance of further commands when the information for said predetermined number of accepted commands is stored, until detection of the effect of the accepted commands for which the information is stored.