Patent ID: 6831858
Filing Date: 2004-12-14
Classification: G11C

Abstract:
A non-volatile semiconductor memory device, comprising:a plurality of memory cells capable of electrically writing and erasing data, the plurality of memory cells being arranged in a row direction and in a column direction, a control terminal of each of the plurality of memory cells being connected to one of a plurality of row lines provided in the row direction, and a drive terminal of each of the plurality of memory cells being connected to one of a plurality of column lines provided in the column direction; and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines, wherein: the voltage control section comprises a storing section and a voltage output section; the storing section stores a value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip; and the voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.