Patent ID: 6334164
Filing Date: 2001-12-25
Classification: G06F

Abstract:
An information processing system comprising:a processor bus, said processor bus transferring address and control signals;a processor coupled to said processor bus;a memory bus, said memory bus transferring data, address, and control signals;a main memory coupled to said memory bus;a system bus, said system bus transferring data, address, and control signals;a device coupled to said system bus; anda data transfer unit coupled to said processor bus, said memory bus and said system bus;wherein said data transfer unit causes a first cooperative operation of said processor bus and said memory bus in response to a request issued from said processor for a processor-main memory access, a second cooperative operation of said memory bus and said system bus in response to a direct memory access request issued from said device, and a third cooperative operation of said processor bus and said system bus in response to an access request issued from said processor or said device;wherein each of said processor bus, said memory bus, and said system bus has a data bus which transfers said data, an address bus which transfers said address, and a control bus which transfers said control signals; andwherein said data transfer unit includes a transfer circuit coupled to said data buses of said processor bus, said memory bus and said system bus, said data transfer circuit performs said transfers through said data buses, anda control circuit which controls said transfer circuit in accordance with said address provided from said processor via said address bus of said processor bus.