Patent ID: 8988118
Filing Date: 2015-03-24
Classification: H03K

Abstract:
1. An apparatus comprising: a first switching circuit configured to receive a differential data signal and a first bias voltage, wherein the first switching circuit is configured to convert the differential data signal to a first PMOS drive signal and a second PMOS drive signal for a first PMOS driver transistor and a second PMOS driver transistor, respectively, wherein the first switching circuit is configured to change a state of the first and second PMOS drive signals in response to a change in state of the data signal, wherein a first state of the first or second PMOS drive signal turns on the corresponding PMOS driver transistor and has a voltage level of the first bias voltage, wherein a second state of the first or second PMOS drive signal turns off the corresponding PMOS driver transistor, wherein the first switching circuit comprises a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, and a first enable switch, wherein sources of the first NMOS transistor and the second NMOS transistor are each electrically connected to a first node, wherein the first enable switch is configured to receive the first bias voltage and to selectively provide the first bias voltage to the first node, wherein a drain of the first NMOS transistor is electrically connected to a gate of the second NMOS transistor, wherein a drain of the second NMOS transistor is electrically connected to a gate of the first NMOS transistor, wherein the first switching circuit is configured to generate the first state of the PMOS drive signal via capacitive coupling and to generate the second state of the PMOS drive signal via a combination of capacitive coupling and turning on of at least one of the first NMOS transistor or the second NMOS transistor; a second switching circuit configured to receive the differential data signal and a second bias voltage, wherein the second switching circuit is configured to convert the differential data signal to a first NMOS drive signal and a second NMOS drive signal for a first NMOS driver transistor and a second NMOS driver transistor, wherein the second switching circuit is configured to change a state of the NMOS drive signal in response to a change in state of the data signal, wherein a first state of the first or second NMOS drive signal turns on the corresponding NMOS driver transistor and has a voltage level of the second bias voltage, and wherein a second state of the first or second NMOS drive signal turns off the corresponding NMOS driver transistor, wherein the second switching circuit comprises a third capacitor, a fourth capacitor, a first PMOS transistor, a second PMOS transistor, and a second enable switch, wherein sources of the first PMOS transistor and the second PMOS transistor are each electrically connected to a second node, wherein the second enable switch is configured to receive the second bias voltage and to selectively provide the second bias voltage to the second node, wherein a drain of the first PMOS transistor is electrically coupled to a gate of the second PMOS transistor, wherein a drain of the second PMOS transistor is electrically coupled to a gate of the first PMOS transistor, wherein the second switching circuit is configured to generate the first state of the NMOS drive signal via capacitive coupling and to generate the second state of the NMOS drive signal via a combination of capacitive coupling and turning on of at least one of the first PMOS transistor or the second PMOS transistor; a third PMOS transistor having a source, a gate, and a drain, wherein the source is coupled to a first power supply rail, wherein the drain is coupled to a node of the first PMOS drive signal; and a fourth PMOS transistor having a source, a gate, and a drain, wherein the source is coupled to a first power supply rail, wherein the drain is coupled to a node of the second PMOS drive signal; wherein the third PMOS transistor and the fourth PMOS transistor are configured to pull up the first PMOS drive signal and the second PMOS drive signal, respectively, for disabling of output drivers driven by the first PMOS drive signal and the second PMOS drive signal.