Patent ID: 8930860
Filing Date: 2015-01-06
Classification: G03F,G06F,H01L

Abstract:
1. A layout decomposition method, executed by a logic processor of a computing system, comprising: receiving a design layout by the logic processor; identifying a design rule for layout decomposition by the logic processor, comprising: generating a first mask with a first pattern and a second mask with a second pattern corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas, wherein the first pattern of the first mask is used to fabricate patterns of spacers for forming even-numbered features in the one of the dense areas, and the second pattern of the second mask is used to cut/block odd-numbered features of the even-numbered features and remove part of the odd-numbered features so as to fabricate the patterns of the features in the at least two of the areas with odd-numbered features.