Patent ID: 6434584
Filing Date: 2002-08-13
Classification: G06F

Abstract:
A digital signal processor comprising:a digital multiplier having two inputs and an output; a multiplier-register for holding a multiplicand word and connected to provide said multiplicand word to said input of said multiplier; a data memory for holding a first word-chain operand and connected to provide said first word-chain operand to said input of said multiplier; an arithmetic logic unit having an output, first input connected to said output of said multiplier and a second input; an accumulator for holding a second word-chain operand and connected to provide said second word-chain operand to said second input of said arithmetic logic unit, having an input connected to said output of said arithmetic logic unit; wherein said data memory holds the plurality N of digital words, said N words being stored therein with a least-significant-word thereof stored at an address location A and with a most-significant-word thereof stored at an address location A+Nâˆ’1; and wherein said accumulator holds the plurality M of digital words, said M words being stored therein with a least-significant-word thereof stored at an address location B and with a most-significant-word thereof stored at an address location B+Mâˆ’1.