Patent ID: 6184116
Filing Date: 2001-02-06
Classification: H01L

Abstract:
A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising:providing a dielectric stack on the surface of a semiconductor substrate;etching away said dielectric stack where it is not covered by a mask wherein remaining said dielectric stack has a width equal to the spacing between two of planned said gate electrodes;growing a gate oxide layer on the surface of said semiconductor substrate not covered by said dielectric stack;depositing a polysilicon layer overlying said gate oxide layer and said dielectric stack;etching back said polysilicon layer to leave spacers on the sidewalls of said dielectric stack;depositing a dielectric layer overlying said dielectric stack and said spacers;polishing back said dielectric layer whereby upper portions of said dielectric stack and said spacers are polished away; andremoving remaining said dielectric layer and said dielectric stack whereby said spacers remain forming said gate electrodes having said gate oxide layer thereunder to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.