Patent ID: 6087212
Filing Date: 2000-07-11
Classification: H01L

Abstract:
A method for manufacturing a semiconductor memory, comprising steps of:selectively forming a field insulator film on a surface of a P-type silicon substrate to confine a device formation region, forming a gate insulator film on said surface of said silicon substrate within said device formation region, forming on said gate insulator film a word line functioning as a gate electrode, and forming within said device formation region at least one pair of N.sup.+ source/drain regions in self alignment with said word line;forming a first interlayer insulator film to cover the surface of said silicon substrate, said field insulator film and said word line, forming a bit contact hole to penetrate through said first interlayer insulator film reaching to one of said at least one pair of N.sup.+ source/drain regions, and forming a bit line to extend over said first interlayer insulator film and to fill said bit contact hole so that said bit line is electrically connected to said one of said at least one pair of N.sup.+ source/drain regions;forming a second interlayer insulator film to cover the surface of said first interlayer insulator and said bit line, forming a titanium nitride film to cover a surface of said second interlayer insulator, forming a node contact hole to penetrate through said titanium nitride film and said second and first interlayer insulator films reaching to the other of said at least one pair of N.sup.+ source/drain regions;forming an N.sup.+ polysilicon film to cover a surface of said titanium nitride film and to fill said node contact hole, selectively forming a photoresist film pattern on said N.sup.+ polysilicon film, and conducting an anisotropic dry etching to said N.sup.+ polysilicon film using said photoresist film pattern as a mask, so as to form a silicon film pattern of said N.sup.+ polysilicon film;converting an exposed titanium nitride film into a titanium oxide film, so that a storage node electrode is formed of said silicon film pattern and said titanium nitride film remaining under said silicon film pattern, and is electrically connected to the other of said at least one pair of N.sup.+ source/drain regions; andforming a capacitor dielectric film to cover said storage node electrode, and forming a cell plate electrode to cover said capacitor dielectric film.