Patent ID: 6597199
Filing Date: 2003-07-22
Classification: H03K

Abstract:
A logic output buffer comprising:a P-channel output transistor coupled to an output of the buffer; an N-channel output transistor coupled in series with the P-channel output transistor and further to the buffer output; an additional output transistor coupled in parallel with either the P-channel output transistor or the N-channel output transistor and further to the buffer output; a control transistor coupled in series with the additional output transistor, wherein the control transistor enables the additional output transistor prior to falling transitions at the buffer output if the additional output transistor is an N-channel transistor coupled in parallel with the N-channel output transistor, and wherein the control transistor enables the additional output transistor prior to rising transitions at the buffer output if the additional output transistor is a P-channel transistor coupled in parallel with the P-channel output transistor; and a control circuit coupled to an input of the buffer and the control transistor and operative to provide a control signal for the control transistor.