Patent ID: 8299533
Filing Date: 2012-10-30
Classification: H01L

Abstract:
1. A device structure comprising: a first region of n-type semiconductor material; a second region of n-type semiconductor material; a first region of p-type semiconductor material, the first region of p-type semiconductor material stacked vertically between the first and second regions of n-type semiconductor material to form a vertical NPN bipolar transistor; a second region of p-type semiconductor material, the first and second regions of p-type semiconductor material stacked vertically relative to the second region of n-type semiconductor material to form a vertical PNP bipolar transistor; and an input/output (I/O) pad electrically connected to the first region of n-type semiconductor material and the first region of p-type semiconductor material, wherein the first region of p-type semiconductor material is shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor, the second region of n-type semiconductor material is shared between the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor, and the second region of n-type semiconductor material and the second region of p-type semiconductor material are configured to be electrically connected to a positive power supply voltage such that an electrostatic discharge (ESD) pulse of negative voltage at the I/O pad is directed through the first vertical NPN bipolar transistor and the first vertical PNP bipolar transistor to a power supply supplying the positive power supply voltage.