Patent ID: 7706188
Filing Date: 2010-04-27
Classification: G11C

Abstract:
1. A memory array having a NAND string coupled between a bitline and a sourceline precharged to a program inhibit voltage during a program operation for inhibiting programming of a selected memory cell, comprising: a string select transistor driven to a voltage level for coupling the program inhibit voltage of the bitline to all memory cells of the NAND string; lower memory cells between the selected memory cell and the sourceline driven to a first pass voltage in a first time period; upper memory cells between the selected memory cell and the bitline driven to a second pass voltage in the first time period for precharging the upper memory cell channels to a primary boosted voltage; and a selected memory cell driven from a third pass voltage in the first time period for precharging the selected memory cell channel to the primary boosted voltage, to a programming voltage greater than the first pass voltage in a second time period following the first time period.