Patent ID: 7655946
Filing Date: 2010-02-02
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. a first output die pad B. a second output die pad; C. core circuitry having a first core output lead and a second core output lead; D. a first tristate output buffer having an input connected to the first core output lead, a tristate input connected to a test enable lead, and a data output connected to the first output die pad; E. a second tristate output buffer having an input connected to the second core output lead, a tristate input, and a data output connected to the second output die pad; F. test circuitry having a core input lead connected to the first core output lead, a test enable input lead connected to the test enable lead, a compare strobe input lead, an expected data input lead connected to the first output die pad, a mask data input lead connected to the second output die pad, a scan input lead, a scan output lead, and a scan control input lead; and G. a gate having a first input connected to the test enable lead, a second input connected to a control lead, and an output connected to the tristate input of the second tristate output buffer.