Patent ID: 6020616
Filing Date: 2000-02-01
Classification: H01L

Abstract:
A network of on-chip capacitive structures for suppressing power supply inductive noise, comprising:a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions, the plurality of dummy active regions being separated from the plurality of active regions by at least a bloat distance; anda network of dummy polysilicon lines being configured to overlie selected dummy active regions, the network of dummy polysilicon lines having a predefined pattern that does not lie over the plurality of active regions, and the network of dummy polysilicon lines that overlie the selected dummy active regions functioning as dummy gates that substantially interconnects the plurality of dummy active regions;wherein the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.