Patent ID: 8193564
Filing Date: 2012-06-05
Classification: H01L

Abstract:
1. A silicon carbide semiconductor device comprising a plurality of MOSFETs arranged in a first direction and a plurality of deep layers, each of the plurality of MOSFETs including: a substrate made of silicon carbide, the substrate having a first conductivity type, the substrate having first and second opposing surfaces; a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate; a base region located on the drift layer, the base region made of silicon carbide and having a second conductivity type; a source region located on the base region, the source region made of silicon carbide, the source region having the first conductivity type and having an impurity concentration greater than the impurity concentration of the drift layer; a trench extending to a depth deeper than the source region and the base region and reaching the drift layer, the trench sandwiched by each of the base region and the source region, the trench provided along a second direction, the second direction intersecting with the first direction in a planar direction of the substrate; a gate insulating layer located on a surface of the trench; a gate electrode located on the gate insulating layer in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode located on the second surface of the substrate; and a body layer having a predetermined distance from a sidewall of the trench, the body layer located at a portion deeper than the source region, the body layer having the second conductivity type and having an impurity concentration greater than the impurity concentration of the base region, wherein the plurality of deep layers has a stripe shape formed in parallel with the planar direction of the substrate along the first direction, the plurality of deep layers is located under each base region in the plurality of MOSFETs, has a constant depth, and extends to a depth deeper than each trench in the plurality of MOSFETs, the plurality of deep layers has the second conductivity type, the plurality of deep layers intersects with each trench in the plurality of MOSFETs in a lattice pattern, and in each of the plurality of MOSFETs, an inversion channel is provided at a surface portion of the base region located on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.