Patent ID: 8780655
Filing Date: 2014-07-15
Classification: G06F,G11C

Abstract:
1. A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, the method comprising the steps of: putting said memory into a write levelling mode; incrementing an alignment delay applied to said data strobe signal until a transition point occurs at which a response of said memory to issuance of said data strobe signal transitions to an inverse state; performing an oversampling of said response of said memory over a selected interval following said transition point; repeating said steps of incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of said oversampling is in said inverse state; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of said clock signal, said identified clock cycle responsible for said transition point; and applying said selected alignment delay to said data strobe signal and applying a clock cycle selection to a data path in said system to match said identified clock cycle.