Patent ID: 6646480
Filing Date: 2003-11-11
Classification: G06F,H03L

Abstract:
A glitchless clock output circuit, which comprises:a selection circuit, which generates a plurality of select signals according to an input signal; a plurality of delay switching circuits, each of which receives the select signal and a corresponding delayed clock signal and generates a select enabling signal such that the transition of the select enabling signal is synchronized with the transition of the corresponding delayed clock signal; and an adaptive clock router circuit for selecting one of the delayed clock signals as a clock output signal according to a plurality of select enabling signals, wherein the delay switching circuit comprises: a first AND gate for receiving the delayed clock signal and the select enabling signal; a first OR gate for receiving the delayed clock signal and the select signal enabling; a second AND gate for receiving the select signal and the output of the first OR gate; and a second OR gate for receiving the outputs of the first and second AND gates and outputting the select enabling signal.