Patent ID: 6178532
Filing Date: 2001-01-23
Classification: G11C

Abstract:
An on-chip test circuit included in an integrated circuit memory device, the memory device including a memory-cell array having a plurality of memory cells arranged in rows and columns and a data terminal adapted to receive a data signal, the test circuit comprising:a test mode terminal adapted to receive a test mode signal;a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active;an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal; anda test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit at a first rate, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array at a second rate that is greater than the first rate, and operable in a third mode to activate the read test data signal and access data stored in the memory cells at a third rate that is greater than the first rate such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.