Patent ID: 6756622
Filing Date: 2004-06-29
Classification: H01L

Abstract:
A memory array on a substrate, comprising:multiple vertical pillars of single crystalline semiconductor material extending outwardly from the substrate, the pillars having multiple sides, each pillar including a pair of transistors in the same pillar, each of the transistors having a body region, a gate region and first and second source/drain regions, and wherein the second source/drain region of a first transistor comprises the gate for a second transistor, and wherein the first source/drain region of the second transistor comprises the body region of the first transistor, the pillars forming an array of rows and columns; a number of write wordlines, wherein each write wordline is coupled to the gates of the first transistors in a row of vertical pillars in the array; a number of write bit lines, wherein each write bit line is coupled to the first source/drain regions of the first transistors in a column of vertical pillars in the array; a charge storage node coupled to the second source/drain region of each first transistor in the array of vertical pillars; a number of read bit lines, wherein each read bit line is coupled to the first source/drain regions of the second transistors in a row of vertical pillars in the array; and a number of read wordlines, wherein each read wordline is coupled to the second source/drain regions of the second transistors in a column of vertical pillars in the array.