Patent ID: 7441170
Filing Date: 2008-10-21
Classification: G01R

Abstract:
1. An integrated circuit comprising: A. core circuitry having a periphery and having, extending beyond the periphery of the core circuitry, functional input leads, functional output leads, a test data input lead, a test data output lead, a test clock input lead, a test mode select input lead, an external register present input lead, an external test data output lead, an external test data input lead, and external register control output leads; and B. a scan circuitry external of the periphery of the core circuitry and connected to the functional input leads, the functional output leads, the external test data output lead, the external test data input lead, and the external register control output leads, the scan circuitry being free of test access port circuitry external of the periphery of the core circuitry.