Patent ID: 6175153
Filing Date: 2001-01-16
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor element having a circuit formation area and an electrode formation area on a main surface thereof;a first pad electrode and a second pad electrode formed in the electrode area on the main surface of said semiconductor element;a first insulation layer formed in the circuit formation area on the main surface of said semiconductor element;a first circuit pattern formed on a surface of said first insulation layer such that said first insulation layer is interposed between said semiconductor element and said first circuit pattern, said first circuit pattern being electrically connected to said first pad electrode;a second insulation layer formed on the first circuit pattern, said second insulation layer having a first through hole for exposing said first circuit pattern;a second circuit pattern formed on a surface of said second insulation layer such that said second insulation layer is interposed between said first circuit pattern and said second circuit pattern, said second circuit pattern electrically connected to said second pad electrode and having a second through hole for exposing said first circuit pattern;a first external electrode electrically connected to said second circuit pattern;a second external electrode electrically connected to said first circuit pattern through the first and second through holes; anda mold resin which seals said second circuit pattern.