Patent ID: 8306147
Filing Date: 2012-11-06
Classification: H03L,H04L

Abstract:
1. A 4× over-sampling data recovery system, comprising: a charge pump phase locked loop (PLL), for receiving a clock signal and generating a plurality of multiplicative clock signals according to the clock signal; a 4× over-sampler, for sampling a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times; a data regenerator for generating a (M+N)-bit signal according to sequentially combining two of the M-bit signals received; and a digital PLL, for dividing the (M+N)-bit signal into (N+1) groups of M-bit data and selecting a designated M-bit data from the (N+1) groups of M-bit data as a P-bit recovery data.