Patent ID: 6074943
Filing Date: 2000-06-13
Classification: H01L

Abstract:
A method of fabricating an integrated circuit structure, comprising the steps of:(a) providing a patterned electrically conductive layer having a first pair of opposing sidewall portions;(b) providing a first layer of dielectric material over said electrically conductive layer having a second pair of sidewall portions extending from said first pair of sidewall portions;(c) forming a layer of electrically conductive material onto said first and second pairs of sidewall portions to provide extensions of said electrically conductive material extending above the portion of said electrically conductive layer most closely adjacent to said first layer of dielectric material;(d) depositing a second layer of dielectric material over said first layer of dielectric material; and(e) forming a via extending through said first and second layers of dielectric material extending to said electrically conductive layer and, when misaligned, extending to said layer of electrically conductive material.