Patent ID: 6914844
Filing Date: 2005-07-05
Classification: G11C

Abstract:
1. A power down circuit for a semiconductor integrated circuit memory device operating from an external voltage source and having memory cells and peripheral circuits comprising: a transistor switch connected between the external voltage source and the memory cells and peripheral circuits; a generator for providing a control voltage of a first level different from the external voltage; a multiplexer receiving as one input said control voltage and as a second input the external voltage, said multiplexer having a selected output of one of said control voltage and said external voltage that is applied to a control electrode of said transistor switch; wherein said multiplexer is responsive to a power down control signal to selectively apply the external voltage to said transistor control electrode to block application of the external voltage to the device memory cells and peripheral circuits, and responsive to the absence of the power down control signal to apply said control voltage to said transistor switch control electrode and operate said transistor to apply the external voltage to the device memory cells and peripheral circuits for normal operation of the memory device.