Patent ID: 6335565
Filing Date: 2002-01-01
Classification: H01L

Abstract:
A semiconductor device comprising:an insulating base having a first surface and a second surface opposite to said first surface; a first semiconductor chip having a flash memory circuit and first connection terminals formed on a main surface of said first semiconductor chip, said first semiconductor chip being disposed on said first surface of said insulating base; a second semiconductor chip having a random access memory circuit and second connection terminals formed on a main surface of said second semiconductor chip, said second semiconductor chip being stacked on said first semiconductor chip; bump electrodes disposed on said second surface of said insulating base; first conductors electrically connecting said first connection terminals of said first semiconductor chip with said bump electrodes; second conductors electrically connecting said second connection terminals of said second semiconductor chip with said bump electrodes; and a mold resin sealing said first and second semiconductor chips.