Patent ID: 7542320
Filing Date: 2009-06-02
Classification: G11C,H01L

Abstract:
1. A semiconductor memory device comprising: a plurality of word lines arranged above a semiconductor substrate to extend in a row direction; a plurality of digit lines arranged above said semiconductor substrate to extend in a column direction orthogonal to said row direction; a power supply line arranged in parallel to said plurality of digit lines; and a plurality of memory cells formed on said semiconductor substrate at intersections of said plurality of word lines and said plurality of digit lines, each of said plurality of memory cells having a drain region and a source region; a linear conductive section arranged under said power supply line, wherein said power supply line is connected with said linear conductive section which is connected with said source regions of said plurality of memory cells, said drain regions of each of columns of said plurality of memory cells are connected with one of said plurality of digit lines, and said plurality of word lines function as gates of said plurality of memory cells.