Patent ID: 7394289
Filing Date: 2008-07-01
Classification: H03K

Abstract:
1. A field programmable gate array comprising: a plurality of programmable logic cells; at least one random access memory cluster that stores data; a read-data bus associated with each at least one random access memory cluster; a write-data bus associated with each at least one random access memory cluster; a read-address bus associated with each at least one random access memory cluster; a write-address bus associated with each at least one random access memory cluster; write-address control lines associated with each at least one random access memory cluster; read-address control lines associated with each at least one random access memory cluster; at least one random access memory control block that controls transmission of data to and from the at least one random access memory cluster, each at least one random access memory control block coupled to the read-data bus, the write-data bus, the read-address bus, the write-address bus, the write-address control lines, and the read-address control lines of the at least one random access memory clusters; at least one dedicated first-in/first-out memory logic component, each at least one dedicated first-in/first-out memory logic component coupled to the read-data bus, the write-data bus, the read-address bus, the write-address bus, the write-address control lines, and the read-address control lines; and dedicated programmable logic configured by programmable elements to grant control of the read-address bus, the write-address bus, the write-address control lines, and the read-address control lines to one of the at least one dedicated first-in/first-out memory logic component and the at least one random access memory control block to which the read-address bus, the write-address bus, the write-address control lines, and the read-address control lines are coupled.