Patent ID: 8997111
Filing Date: 2015-03-31
Classification: G06F

Abstract:
1. An electronic device, comprising: a processor configured to execute a plurality of processes; a memory device storing a configurator and a scheduler; wherein the configurator executed by the processor is configured to determine a time slice for each of the plurality of processes and a time slice switch between consecutive ones of the time slices, the configurator further determining a starting point for each time slice, wherein the scheduler executed by the processor is configured to generate a schedule including the time slices as a function of durations of each of the time slices, durations of each of the time slice switches, and the starting points of the time slices, the schedule including an order for each of the time slices for a respective one of the plurality of processes, and wherein, when performance of one of the time slice switches requires less time than the duration of the one of the time slice switches, the scheduler waits until the end of the duration before completing a context switch in order to guarantee a periodicity of the schedule; and wherein the duration of each of the time slice switches is determined in response to generating a worst case time latency and a time context switch worst case for one of the plurality of processes being executed during the respective time slice.