Patent ID: 8984189
Filing Date: 2015-03-17
Classification: G06F,G11C,H01L,H03M

Abstract:
1. A memory device comprising: a package substrate having a first side; a hybrid memory buffer chip attached to the first side of the package substrate, the hybrid memory buffer chip including high speed input/output (HSIO) logic to support a HSIO interface with a processor and packet processing logic to support a packet processing protocol on the HSIO interface, wherein the hybrid memory buffer chip is a partial hybrid memory buffer; and a plurality of memory tiles in each of a plurality of memory strata vertically stacked on the hybrid memory buffer chip, each memory tile including a memory array and tile input/output (IO) logic, the plurality of memory strata including a base memory stratum, the plurality of memory tiles of the base memory stratum including a first side and a second side, the second side being opposite to the first side, the first side being coupled with the plurality of memory tiles of another memory stratum of the plurality of memory strata and the second side facing the package substrate and the hybrid memory buffer chip; wherein a plurality of interconnect redistribution layer (RDL) lines are deposited on the second side of the plurality of memory tiles of the base memory stratum and wherein the plurality of RDL lines are electrically coupled with the hybrid memory buffer chip; wherein each memory tile of the base memory stratum is directly electrically coupled with the hybrid memory buffer chip via one or more lines of the plurality of RDL lines, the hybrid memory buffer chip is directly electrically coupled with the package substrate by one or more additional lines of the plurality of RDL lines, and each memory tile of the base memory stratum is directly electrically coupled with the package substrate; and wherein the hybrid memory buffer chip is electrically coupled with each of the plurality of memory tiles of the plurality of memory strata through a first plurality of through silicon vias of the plurality of memory strata, each of the plurality of RDL lines being coupled with a respective through silicon via of the first plurality of through silicon vias, and wherein the package substrate is electrically coupled with each of each of the plurality of memory tiles of the plurality of memory strata through a second plurality of through silicon vias.