Patent ID: 6144056
Filing Date: 2000-11-07
Classification: H01L

Abstract:
Dynamic random access memory circuitry comprising:a substrate having a substrate outer surface;a substrate memory array area and a substrate peripheral area spaced from the substrate memory array area;a plurality of spaced conductive lines disposed in the substrate memory array area and a plurality of spaced conductive lines disposed in the substrate peripheral area, a first two of the plurality of conductive lines disposed in the array area being adjacent one another and being jointly received over memory array substrate active area in at least a first cross section taken perpendicular to the first two lines, each of the first two conductive lines respectively having conductive material opposing sidewalls in the first cross section, a second two of the plurality of conductive lines disposed in the peripheral area being adjacent one another and being jointly received over peripheral substrate active area in at least a second cross section taken perpendicular to the second two lines, each of the second two conductive lines respectively having conductive material opposing sidewalls in the second cross section, the first two lines and the second two lines collectively having a common width in the first and second cross sections, the first two conductive lines in the array area being laterally spaced from one another a first distance in the first cross section, the second two conductive lines in the peripheral area being laterally spaced from one another in the second cross section a second distance which is greater than the first distance, each of the first two conductive lines in the array area in the first cross section having electrically insulative caps received thereover, the electrically insulative caps respectively having opposing sidewalls which are aligned with the respective conductive material opposing sidewalls of the first two conductive lines in the first cross section, each of the second two conductive lines in the second cross section being void of any electrically insulative caps received thereover which have opposing sidewalls which align with the respective conductive material opposing sidewalls of the second two conductive lines in the second cross section;the first two conductive lines and the second two conductive lines having respective total aggregate sidewalls which define respective line elevations relative to the substrate outer surface in the first and second cross sections, the elevations of the second two lines in the second cross section being less than the elevations of the first two lines in the first cross section;a first pair of insulative spacers received laterally over the total aggregate sidewalls of the first two conductive lines in the first cross section and having respective maximum lateral width dimensions, a second pair of insulative spacers received laterally over the total aggregate sidewalls of the second two conductive lines in the second cross section;the respective maximum lateral width dimensions of the first and second pairs of spacers in the respective first and second cross sections being substantially equal; anda plurality of storage capacitors operably disposed in the substrate memory array area.