Patent ID: 7444682
Filing Date: 2008-10-28
Classification: G06F

Abstract:
1. A security memory chip, comprising: a memory cell array of a single flash memory for executing flash-associated read, write and erase in the single flash memory, the memory cell array storing a plurality of contents, wherein the memory cell array comprises a protected-cell zone and a free-cell zone; a lock, the lock providing protection for contents stored in the protected-cell zone from access; a key capable of unlocking the lock; a mine stored in the memory cell array of the single flash memory as a portion of the plurality of contents for protecting against unauthorized readout, the mine triggering erasure of one or more readout-prohibited contents stored in the memory cell array when the mine is read, wherein the mine is randomly stored in the protected-cell zone; and a control logic that controls access to the plurality of contents.