Patent ID: 6787859
Filing Date: 2004-09-07
Classification: G11C

Abstract:
A semiconductor memory device comprising:eight memory blocks arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area; a first data bus having a plurality of data lines and linearly extending between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix; and a second data bus having a plurality of data lines and linearly extending between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix, wherein the eight memory blocks have a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus, wherein the first data bus is for the memory block associated with a lower data buffer and the second data bus is for the memory block associated with an upper data buffer, wherein the eight memory blocks have two groups each including four memory blocks associated with the lower data buffer or upper data buffer, the first group is positioned adjacent the first data bus and connected to the first data bus, and the second group is positioned adjacent the second data bus and connected to the second data bus.