Patent ID: 6448617
Filing Date: 2002-09-10
Classification: H01L

Abstract:
A semiconductor read-only memory configuration, comprising:a semiconductor substrate; a memory cell array located in said semiconductor substrate; a plurality of memory cells configured in said memory cell array, each one of said plurality of memory cells including a plurality of transistors; word lines made of polycrystalline silicon, said word lines running in a longitudinal direction, said word lines formed with ruptures located in said longitudinal direction after a first number of said plurality of said memory cells; metal tracks running parallel to said word lines for refreshing said word lines; an intermediate insulator isolating said word lines from said metal tracks; a plurality of substrate contacts, each one of said plurality of said substrate contacts located after a second number of said plurality of said memory cells for applying a reference-ground potential to said semiconductor substrate; and a plurality of intermediate cells periodically located in the longitudinal direction; each one of said plurality of said intermediate cells including a first intermediated cell half and a second intermediate cell half that are directly adjacent to one another perpendicularly to the longitudinal direction and that are alternately interchanged; said first intermediate cell half affecting a respective one of said ruptures of a respective one of said word lines and including a respective one of said plurality of said substrate contacts; and said second intermediate cell half refreshing said polycrystalline silicon of said respective one of said word lines.