Patent ID: 6445604
Filing Date: 2002-09-03
Classification: G11C

Abstract:
A channel driving circuit of virtual channel DRAM comprising:N channel block units respectively including first to fourth unit channels where L normal channel registers and M redundancy channel registers are connected through one local data bus transmitting read and write data; first to fourth I/O data bus connectors respectively connected between local data buses of the first to the fourth unit channels and the first to the fourth global data buses; and a channel controller for selectively controlling the normal channel registers and the redundancy channel registers of the first to the fourth channels; first to fourth data sense amp units respectively connected between the first to the fourth global data buses and a global read data bus, for sensing input data in a normal read operation and a redundancy operation; and first to fourth write driver units respectively connected between the first to the fourth global data buses and a global write data bus, for driving input data in a write operation.