Patent ID: 6538488
Filing Date: 2003-03-25
Classification: G06F,H03K

Abstract:
An apparatus comprising:a clock buffer circuit, having a clock input for receiving an initial clock pulse applied thereto and a clock output for transmitting a buffered clock pulse therethrough, and including: a first driver chain of serial arrangement of transistors coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level; a second driver chain of serial arrangement of transistors coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level; respective trigger circuits for each of the first and second driver chains; and a holder circuit operable to alternately hold an output signal at one of the high or low output voltage levels; and a feedback path that couples the clock output to the inputs of the respective trigger circuits to reset the trigger circuits.