Patent ID: 7017095
Filing Date: 2006-03-21
Classification: G01R

Abstract:
1. A method of testing a complex semiconductor device by transforming a functional pattern into a scan determinative pattern, consisting of the steps of: selecting a first semiconductor device having a plurality of storage latches concatenated in a scan chain that includes embedded circuit memories; performing a functional test, consisting of a selected number of test cycles, on said semiconductor device; identifying a failing latch in a logic circuit in the scan chain during the functional test; unloading the values of all the latches from the scan chain before the identified failing latch; generating a Load from the unloaded value of all the latches from the scan chain before the identified failing latch; selecting a second correctly operating semiconductor device having a plurality of storage latches concatenated in a scan chain identical to said first device; applying the generated Load as the first event of an LSSD deterministic pattern by using the same identical primary inputs and Clocks that produced the failure in said failing latch in said first semiconductor device to said second semiconductor correctly operating device using the bootstrapping technique; and unloading the output of said second semiconductor device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device, and diagnosing the failure using existing LSSD deterministic tools.