Patent ID: 6678832
Filing Date: 2004-01-13
Classification: G06F,H04N,Y02D

Abstract:
A memory controller for controlling a memory comprising:a control signal generating circuit for synchronizing input clock signal suspend command signal and clock signal supply command signal with a reference signal, and issuing them respectively as synchronized suspend command signal and synchronized supply command signal; a clock signal cutoff circuit for receiving said synchronized suspend command signal and suspending clock signal supply into said memory, and receiving said synchronized supply command signal to start clock signal supply into said memory; an operation command generating circuit for receiving said synchronized suspend command signal and synchronized supply command signal, and issuing operation commands to said memory; a power on sequence (POS) command generating circuit for issuing a POS command according to POS start signal from said control signal generating circuit; and a command selector for selecting one of said operation commands and said POS command and outputting the selected command to said memory, according to a select signal synchronized with one of said synchronized suspend command signal and said synchronized supply command signal.