Patent ID: 6314498
Filing Date: 2001-11-06
Classification: G06F

Abstract:
A method of maintaining cache coherency in a computer system having a plurality of processing units, each processing unit having a multi-level cache hierarchy, comprising the steps of:first loading a requested value into an upper level cache of a processing unit without loading it into any other cache of the computer system;first marking a cache line in the upper level cache as containing the value exclusive of all other caches of the computer system;evicting the value from the upper level cache;in response to said evicting step, second loading the value into a lower level cache of the processing unit;determining at the lower level cache that the cache line of the upper level cache contained the value exclusive of all other caches of the computer system; andin response to said determining step, second marking a cache line in the lower level cache as containing the value exclusive of all other caches in other processing units of the computer system.