Patent ID: 8427952
Filing Date: 2013-04-23
Classification: G06F

Abstract:
1. A microcode engine for processing packet data, the microcode engine comprising: a program memory comprising a plurality of instructions for processing a stream of received packet data, wherein each instruction includes a plurality of instruction fields; a plurality of execution hardware blocks responsive to the instructions to perform respective functions on the received packet data, each of the plurality of hardware blocks corresponding to a respective instruction field, wherein the plurality of execution hardware blocks comprise: instruction decode circuitry to read a current instruction from the program memory, to provide instruction fields of the current instruction to the corresponding execution hardware blocks for execution, to read, based on an output of the branched decision circuitry, a next instruction from the program memory, and to provide instruction fields of the next instruction to the corresponding execution hardware blocks for execution; a data stream receiver to directly receive a stream of data packets for processing, the stream of data packets comprising the received packet data, the data stream receiver providing the received packet data to the execution hardware blocks, synchronously with the provision of the instruction fields, based on an instruction of the plurality of instructions; and execution control circuitry to direct reads from the data stream receiver for applying one or more of the instructions stored in the program memory to a current data word of the received packet data, and to stall reads from the data stream receiver so as to apply both the current instruction and the next instruction to the current data word.