Patent ID: 6381625
Filing Date: 2002-04-30
Classification: G06F

Abstract:
A microprocessor capable of evaluating a constant power of an operand B in an iterative manner comprising:an initial estimate generator configured to receive said operand B and output an initial estimate Y02 of said operand B's reciprocal; a multiplier coupled to said initial estimate generator and configured to receive said operand B and said initial estimate Y02, wherein said multiplier is configured to form a product during a first iteration by multiplying said initial estimate and said operand, wherein said multiplier comprises: an overflow logic unit comprising a first plurality of inverters coupled to receive and invert selected bits from said product to form a first approximation of the quantity (2âˆ’Y02Ã—B), wherein said first approximation assumes an overflow has occurred during the formation of said product, wherein said overflow logic unit is configured to pad the most significant bit of said first approximation with a constant one to approximate the quantity (3âˆ’Y02Ã—B); a non-overflow logic unit comprising a second plurality of inverters coupled to receive and invert selected bits from said product to form a second approximation of the quantity (2âˆ’Y02Ã—B), wherein said second approximation assumes an overflow has not occurred during the formation of said product, wherein said non-overflow logic unit is configured to pad the most significant bit of said second approximation with a constant one to approximate the quantity (3âˆ’Y02Ã—B); and a multiplexer configured to select either said first or second approximations for output as an intermediate product; compression logic coupled to receive and compress said intermediate product in a loss-free manner; and a storage register coupled to said logic and configured to store said compressed intermediate product.