Patent ID: 6352892
Filing Date: 2002-03-05
Classification: H01L

Abstract:
A process of fabricating a trench capacitor semiconductor memory structure comprising the steps of:(a) providing a semiconductor structure comprising a semiconductor substrate or wafer having at least one storage trench region and a raised shallow trench isolation (STI) region adjacent to said storage trench, said structure having preformed layers of a partial gate conductor stack formed in said substrate or wafer which are spaced apart by said storage trench and raised STI regions; (b) forming a bottom electrode layer in said storage trench region; (c) forming a temperature sensitive high dielectric constant material on said bottom electrode layer and lining sidewalls of said storage trench region; (d) forming a top electrode over said temperature sensitive high dielectric constant material; (e) filling said storage trench region with polysilicon; (f) completing fabrication of a capacitor in said storage trench region; (g) forming a patterned gate conductor region from said preformed gate conductor stack layers; and (h) forming subsequent device connections so as to complete fabrication of a trench capacitor semiconductor memory cell.