Patent ID: 8916913
Filing Date: 2014-12-23
Classification: H01L

Abstract:
1. A high voltage PMOS, comprising: a P-type epitaxial layer; an N-type buried layer under the epitaxial layer; a P-type first low voltage well acting as a drain body region, wherein the first low voltage well is formed in the epitaxial layer; an N-type second low voltage well acting as a source body region, wherein the second low voltage well is formed in the epitaxial layer; an N-type high voltage well acting as a supporting body region, wherein the high voltage well is formed in the epitaxial layer, and wherein the second low voltage well is surrounded by the high voltage well, and further wherein the first low voltage well and the high voltage well are not adjacent and separated by the epitaxial layer; a P-type first highly doping region, wherein the first highly doping region is formed in the first low voltage well; a P-type second highly doping region, wherein the second highly doping region is formed in the second low voltage well; an N-type third highly doping region, wherein the third highly doping region is formed in the second low voltage well, and wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.