Patent ID: 8969935
Filing Date: 2015-03-03
Classification: H01L

Abstract:
1. A semiconductor memory device comprising: a semiconductor substrate having a first area; a plurality of cell transistors arranged on the first area of the semiconductor substrate; a plurality of cell capacitors, each of the cell capacitors including a lower electrode, an upper electrode covering the lower electrode, and a capacitor insulating film provided between the lower electrode and upper electrode, the lower electrode being electrically connected to an associated one of the cell transistors, the lower electrodes of the cell capacitors being stacked in a vertical direction so that each of the lower electrodes of the cell capacitors overlaps with other lower electrodes of other cell capacitors on the first area; a plurality of contact plugs each penetrating the lower electrodes and extending in the vertical direction, each of the contact plugs being electrically connected to an associated one of the cell transistors; and an insulating film provided between the contact plugs and the lower electrodes, wherein each of the contact plugs is electrically connected to an associated different one of the lower electrodes via an opening formed in the insulating film.