Patent ID: 7345937
Filing Date: 2008-03-18
Classification: G11C

Abstract:
1. An open digit line array architecture, comprising: a first plurality of sense amplifiers, each sense amplifier coupled to a first digit line of a first memory array and coupled to a second digit line of a second memory array; a second plurality of sense amplifiers, each sense amplifier coupled to a first digit line of the first memory array and coupled to a second digit line of a third memory array, each sense amplifier of the second plurality configured to drive the first digit line to a voltage level in response to a first activation signal; a third plurality of sense amplifiers, each sense amplifier coupled to a first digit line of the first memory array and coupled to a second digit line of the third memory array, each sense amplifier of the third plurality configured to drive the first digit line to the voltage level in response to a second activation signal; a common reference line; a first plurality of switches, each switch of the first plurality coupled to a respective one of the first digit lines coupled to the first plurality of sense amplifiers and further coupled to the common reference line, each switch of the first plurality configured to selectively couple the respective first digit line to the common reference line in response to a first control signal; a second plurality of switches, each switch of the second plurality coupled to a respective one of the first digit lines coupled to the second plurality of sense amplifiers and further coupled to the common reference line, each switch of the second plurality configured to selectively couple the respective first digit line to the common reference line in response to a second control signal; and a third plurality of switches, each switch of the third plurality coupled to a respective one of the first digit lines coupled to the third plurality of sense amplifiers and further coupled to the common reference line, each switch of the third plurality configured to selectively couple the respective first digit line to the common reference line in response to a third control signal.