Patent ID: 6525776
Filing Date: 2003-02-25
Classification: H04N

Abstract:
An information processing apparatus comprising:an address generation circuit for generating an address signal; a memory for storing an information signal containing a video signal in response to the address signal generated by the address generation circuit; first means for periodically updating the address signal generated by the address generation circuit; a compression processing circuit for reading out the information signal from the memory, and subjecting the read-out information signal to a compressively encoding process; second means for detecting a head of every frame represented by the information signal; third means for storing a state of the address signal generated by the address generation circuit which corresponds to the frame head detected by the second means; fourth means for detecting whether or not the information signal becomes discontinuous; fifth means for suspending operation of the first means and also operation of the compression processing circuit when the fourth means detects that the information signal becomes discontinuous; sixth means for detecting whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous; and seventh means for starting the updating of the address signal by the first means from the state stored by the third means when the sixth means detects that the information signal returns to its normally continuous state after the information signal becomes discontinuous.