Patent ID: 6433427
Filing Date: 2002-08-13
Classification: H01L

Abstract:
A wafer level package incorporating dual stress buffer layers for I/O redistribution comprising:a wafer having a multiplicity of IC dies formed on an active surface; each of said multiplicity of IC dies further comprises: a plurality of first I/O pads formed on a top surface insulated by a first dielectric layer deposited therein-between; a plurality of interconnects formed on said plurality of I/O pads for providing electrical communication with said pads; a first stress buffer layer formed of an elastic material embedding said plurality of interconnects while exposing a top surface of said plurality of interconnects; a second stress buffer layer formed of an elastic material on top of said first stress buffer layer without covering said exposed top surfaces of said plurality of interconnects; a plurality of metal traces formed on top of said first and second stress buffer layers each in electrical communication with one of said plurality of interconnects at a first end while a second end extends toward a center of said IC die; a second dielectric layer formed on top of said plurality of metal traces insulating the latter from each other while exposing a plurality of second I/O pads on each of said plurality of metal traces; and a plurality of solder balls formed on said plurality of second I/O pads arranged in an area array.