Patent ID: 7528045
Filing Date: 2009-05-05
Classification: H01L

Abstract:
1. A method for manufacturing a MOS transistor comprising steps of: providing a substrate having at least a gate structure having a hard mask layer and a cap layer formed thereon and a shallow trench isolation (STI); performing a first etching process to form recesses in the substrate respectively on two sides of the gate structure; performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, a seam being accordingly formed between the epitaxial silicon layer and the STI; performing a deposition process to deposit a dielectric layer on the substrate, the dielectric layer filling the seams; performing a second etching process to remove the dielectric layer except the seams, the hard mask layer, and the cap layer after the deposition process; and performing a self-aligned silicidation (salicide) process.