Patent ID: 8610214
Filing Date: 2013-12-17
Classification: H01L

Abstract:
1. A semiconductor device, comprising an ESD protection MOS transistor in a substrate and spaced apart from substrate contacts, the ESD protection MOS transistor comprising: a plurality of drain regions and a plurality of source regions disposed alternately; and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, thereby constitutes a unified structure; wherein the plurality of drain regions are electrically connected to an external connection terminal, wherein the plurality of source regions are electrically connected to a ground electric potential supplying line, and wherein each of the plurality of drain regions is provided with a salicide metal pattern on a surface of the substrate, such that a distance along the surface of the substrate between an edge of the salicide metal pattern and the gate electrode and a corresponding transistor resistance between a nearest contact hole and the gate electrode steadily decreases as a distance along the surface of the substrate from the salicide metal pattern to the substrate contacts of the ESD protection MOS transistor increases.