Patent ID: 7838361
Filing Date: 2010-11-23
Classification: H01L

Abstract:
1. A method for fabricating a recess gate in a semiconductor device, the method comprising: etching a silicon substrate to form a trench that defines an active region; forming a device isolation layer that gap-fills the trench; forming a hard mask layer over the silicon substrate and the device isolation laver, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer formed over the oxide layer, wherein the hard mask layer exposes a channel target region of the active region; forming a first recess region by performing a first etching process on the channel target region by using the hard mask layer as an etch barrier; removing the amorphous carbon layer; and forming a second recess region by performing a second etching process on the first recess region as exposed by said first etching and said removing the amorphous carbon layer by using the hard mask layer as an etch barrier, wherein the first and second recesses form a combined recess region with a dual profile, wherein the second etching is performed after removing the amorphous carbon layer.