Patent ID: 6266275
Filing Date: 2001-07-24
Classification: G11C

Abstract:
A method of program inhibiting a first multiword NAND type floating gate memory cell having a first series select transistor and a first source select transistor during a hot-electron programming operation or a Fowler/Nordheim tunnel-erase operation while programming a second multiword NAND type floating gate memory cell having a second series select transistor and a second source select transistor, the method comprising the steps of:providing a first voltage to a first series select gate of the first series select transistor;providing a second voltage to a first source select gate of the first source select transistor;providing a select voltage to a second series select gate of the second series select transistor; andproviding the select voltage to a second source select gate of the second source select transistor;wherein the first voltage is higher than the second voltage.