Patent ID: 6162679
Filing Date: 2000-12-19
Classification: H01L

Abstract:
A method of manufacturing dynamic random access memory (DRAM) capacitor, comprising the steps of:providing a substrate having a conductive region and an insulation layer thereon;forming a trench in the insulation layer to expose at least a part of the conductive region;forming a first conductive layer conformal to a surface profile of the insulation and the trench;forming a photoresist layer over the first conductive layer to completely fill the trench;removing a portion of the photoresist layer outside the trench region so that a top surface of the first conductive layer is exposed;performing an isotropic dry etching step, wherein the exposed first conductive layer is removed faster than the photoresist layer, and consequently a top surface of the insulation layer is at a distance higher than a top edge of the first conductive layer inside the trench;removing the remaining photoresist layer to expose the remaining first conductive layer inside the trench; andforming a dielectric layer and a second conductive layer over the first conductive layer.