Patent ID: 7519111
Filing Date: 2009-04-14
Classification: H03L

Abstract:
1. A method for providing timing signals for a Joint Test Action Group (JTAG) procedure in a processor test configuration, the method comprising: over-driving a time base of a system clock during a JTAG procedure with a signal having a frequency of a JTAG test clock (TCK) corresponding to a JTAG interface logic unit; and using the signal resulting from over-driving the time base to provide both a frequency of the system clock to a test circuit and a frequency of the JTAG test clock to the JTAG interface logic unit, wherein the frequency of the system clock and the frequency of the test clock are the same, wherein the JTAG interface logic unit is configured to receive a JTAG test mode select (TMS) signal, a JTAG test data input (TDI) signal, and a JTAG test reset (TRST) signal from an emulation unit, to receive the TCK signal from the time base, and to provide a JTAG test data output (TDO) signal to the emulation unit, wherein the JTAG interface logic unit is not configured to receive the TCK signal from the emulation unit.