Patent ID: 7113048
Filing Date: 2006-09-26
Classification: H03K,H03L

Abstract:
1. A ring oscillator comprising: first and second parallel logic circuit paths each having a series connection of a number N inverting logic gates numbered 1 through N each with first and second inputs and an output, wherein in each logic path the output of each inverting logic gate number P of the N inverting logic gates is coupled to the first input of a corresponding inverting logic gate number P+1 and the output of each inverting logic gate number N is coupled to the first input of each inverting logic gate number 1 and the output of each logic gate P of the first logic circuit path is coupled to the second input of a corresponding logic gate P of the second logic circuit path and the output of each logic gate P of the second logic circuit path is coupled to the second input of a corresponding logic gate P of the first logic circuit path, the first path generating a clock signal and the second path generating a substantially non-skewed complement of the clock signal, wherein a delay through each of the N inverting logic gates is variable in response to a control voltage, thereby enabling a frequency of the ring oscillator to be varied and the delay through each of the N inverting logic stages is varied by modifying a conductance of a coupling device providing the series connection of the N inverting logic gates in response to the control voltage.