Patent ID: 6576556
Filing Date: 2003-06-10
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a plurality of unit element regions, comprising:forming an etching stopper portion embedded in a semiconductor substrate for each unit element region, said etching stopper portion being located at a distance from a center of said unit element region; forming a first structure on a surface of said semiconductor substrate in said unit element region; forming at least one first etching hole in said first structure located between a center of said first structure and said etching stopper portion, said first etching hole penetrating said first structure and reaching said semiconductor substrate; forming a sacrificial layer on said first structure; forming at least one splicing pillar which penetrates said sacrificial layer and reaches said first structure; forming a second structure on said sacrificial layer; forming a second etching hole which penetrates said second structure, said splicing pillar, and said first structure, and reaches said semiconductor substrate, said second etching hole being aligned with a central axis of said splicing pillar; introducing an etching gas through said second etching hole and etching said semiconductor substrate, forming a hollow portion which has a largest depth directly beneath said splicing pillar, gradually becomes shallower toward said etching stopper portion, and has a smallest depth where the hollow portion is in contact with said etching stopper portion; and sequentially etching said sacrificial layer with said etching gas, supplied through said first etching hole from said hollow portion, concurrently with etching of said semiconductor substrate.