Patent ID: 8249737
Filing Date: 2012-08-21
Classification: H01L

Abstract:
1. A rapid thermal annealing method for a semiconductor device, comprising the steps of: establishing a ternary correspondence relationship among a device electrical parameter, an annealing temperature, and a Shallow Trench Isolation (STI) distribution density; deriving an STI distribution density in a specific area of the semiconductor device and a target STI distribution density; determining whether the STI distribution density in the specific area is larger than the target STI distribution density; if the STI distribution density in the specific area is larger than the target STI distribution density, adding a virtual structure in the specific area to make the STI distribution density in the specific area equal to the target STI distribution density; and deriving from the ternary correspondence relationship a target annealing temperature corresponding to the target STI distribution density and performing an annealing process with the annealing temperature on the semiconductor device to achieve a target electrical parameter; wherein the derivation of the STI distribution density in the specific area comprises the steps of: pre-dividing the semiconductor device into a plurality of repeated specific areas; detecting the active area distribution density A calculating the STI distribution density D