Patent ID: 6717447
Filing Date: 2004-04-06
Classification: H03K,H03L

Abstract:
A delay adjustment circuit for a semiconductor device, comprising:a difference-pulse generator, wherein the difference-pulse generator receives a system clock signal and a feedback clock signal and provides a difference-pulse signal that indicates a phase difference between the system clock signal and the feedback clock signal, and generates an interim clock signal that is selected from the group comprising the feedback clock signal and an inversion of the feedback clock signal; a delay control unit in communication with the difference-pulse generator, wherein the delay control unit receives the difference-pulse signal and provides a plurality of output signals that indicate the phase difference between the system clock signal and the interim clock signal; and a delay unit in communication with the difference-pulse generator and the delay control unit, wherein the delay unit receives the interim clock signal and the plurality of output signals, and provides an internal clock signal that is in phase with the system clock signal.