Patent ID: 6574590
Filing Date: 2003-06-03
Classification: G06F

Abstract:
In a processor including in-circuit emulation means comprising one or more scan chains of serially connected registers for access by an external host computer system, a method of carrying out a debug procedure comprising:the host computer system carrying out a debug procedure at a debug processing speed via said scan chains, and selectively interrupting said debug procedure for access to a peripheral or other memory mapped device; in response to said host computer system selectively interrupting said debug procedure, the host computer system writing via said scan chains into an area of memory of the processor a program for reading and/or writing data at a specified memory location for access to a said peripheral or other memory mapped device; and the host computer system configuring the processor to execute the program upon the host computer system exiting the debug procedure; the host computer system exiting the debug procedure causing the processor to execute the program at a full processor speed: and upon a completion of the execution of the program by the processor, the program causing the host computer system to reenter the debug procedure.