Patent ID: 6275891
Filing Date: 2001-08-14
Classification: G06F,G09G,H04N

Abstract:
A system which comprises:a traffic master;an array of memory modules, wherein each memory module is coupled to the traffic master by a data channel, wherein each data channel includes an address path and one or more data paths, wherein the data paths have a common number of data lines; andan array of processor units each coupled to the traffic master by a data bus to transfer data to and from the memory modules using a shared address space which spans the array of memory modules,wherein the traffic master includes:a processor interface port for each processor, wherein the processor interface port converts data bus signals into corresponding data channel signals, and also converts data channel signals into corresponding data bus signals;a router coupled to the processor interface ports to receive the data channel signals and configured to route the data channel signals to the memory modules, wherein the router is further configured to carry requested data channel signals from the memory modules to the processor interface ports;wherein the array of processor units includes at least one processor unit having a data bus with a number of data lines that exceeds said common number of data lines in the data paths,wherein said common number of data lines is the greatest common divisor (GCD) of the numbers of data lines for the data busses.