Patent ID: 8193847
Filing Date: 2012-06-05
Classification: H03K

Abstract:
1. A timing circuit configured to generate an output timing signal in dependence on an input timing signal, said timing circuit comprising: a plurality of circuit components, each circuit component configured to receive an input dependent on said input timing signal and to generate an output in dependence on said input, each circuit component configured to perform switching operations by switching an output level of said output in response to a transition of an input level of said input, wherein each circuit component exhibits a delay in switching said output level following said transition of said input level, said delay comprising a first delay associated with a first switching of said output level and a second delay associated with a second switching of said output level, said first switching being in an opposite direction to said second switching, and wherein said first delay and said second delay exhibit a change in magnitude as each circuit component repeatedly performs said switching operations, said change in magnitude being in opposite directions for said first delay and said second delay respectively; and said plurality of circuit components arranged such that a timing of said output timing signal is dependent on both said first delay and said second delay.