Patent ID: 7957185
Filing Date: 2011-06-07
Classification: G11C

Abstract:
1. In an array of nonvolatile memory cells, wherein each memory cell is accessible by a set of word lines and bit lines and is programmable to a current conducting threshold voltage that corresponds to one of multiple memory states, a method of sensing in parallel a group of the memory cells to be sensed, comprising: precharging the set of word lines for the memory cells of said group to a set of predetermined word line voltages; precharging the bit lines for the memory cells of said group each to a predetermined bit line voltage so as to allow a conduction current to flow in each of the memory cells depending on each memory state, said precharging bit lines being sustained over a duration at least after the set of predetermined word line voltages and each predetermined bit line voltage have stabilized; and sensing the memory cells in parallel to determine the state of each memory cells; wherein said precharging the set of word lines preempts said precharging of each bit line for the group of memory cells to be sensed so as to minimize said duration.