Patent ID: 8122407
Filing Date: 2012-02-21
Classification: G06K

Abstract:
1. A method for implementing pattern matching of integrated circuit features, the method comprising: computing, using a processing device, Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a user; receiving, by the processing device, one or more selected bisectors of the Voronoi computed reference configuration from the user, indicative of user identified salient regions of design shapes and/or corners to be searched, so as to define one or more search elements, wherein a search element comprises a given bisector and a pair of Voronoi edge regions bounded thereby; constructing, using the processing device, a search pattern from the one or more search elements defined from the reference configuration; examining, using the processing device, the search space for matching sequences with respect to the search pattern; and highlighting resulting matching patterns in the search space for the user.