Patent ID: 6150217
Filing Date: 2000-11-21
Classification: H01L,Y10S

Abstract:
A method of fabricating a DRAM capacitor, comprising:providing a substrate having a doped region;forming an insulating layer over the substrate where the insulating layer has a contact window to expose the doped region;forming a first conductive layer to fill the contact window;forming a silicon germanium layer on the first conductive layer;forming a segregated grained germanium in the silicon germanium layer on the first conductive layer and the silicon germanium layer being transformed into a silicon oxide layer on the first conductive layer;removing the silicon oxide layer;forming a multi-cylinder lower electrode by removing the first conductive layer to a depth using the segregated grained germanium as a mask;removing the segregated grained germanium;forming a capacitor dielectric layer on the multi-cylinder lower electrode; andforming a second conductive layer on the capacitor dielectric layer to serve as an upper electrode.