Patent ID: 6499811
Filing Date: 2002-12-31
Classification: G01R

Abstract:
An integrated circuit comprisinga monitoring block; and a monitored block that is monitored by the monitoring block, wherein the monitoring block and the monitored block are formed on one chip, and wherein a first power supply terminal for supplying a first voltage to the monitored block and a second power supply terminal for supplying a second voltage to the monitoring block are provided as different terminals, wherein the monitored block has a first reference voltage generating circuit which generates the first reference voltage on the basis of the first voltage supplied to the first power supply terminal; the monitoring block has a second reference voltage generating circuit which generates the second reference voltage on the basis of the voltage supplied to the second power supply terminal; the monitored block and the monitoring block are arranged as spatially separated blocks in the one chip; and the monitored block and the monitoring block are insulated and isolated in the one chip.