Patent ID: 6557068
Filing Date: 2003-04-29
Classification: G06F

Abstract:
A method of issuing commands and attributes in a computer system comprising a processor on a first bus, a random access memory on a second bus, a third bus implementing a Peripheral Component Interface protocol, operating on a series of clock cycles, and capable of implementing bus arbitration rules and bus width rules according to a registered Peripheral Component Interface protocol, a core logic chipset bridging the first, second, and third buses, and a PCI device on the third bus, said method comprising:providing a first portion of the third bus; issuing a first command on the first portion of the third bus on a first clock cycle of the third bus; on a second clock cycle immediately after the first clock cycle, issuing a second command on the first portion of the third bus; providing a second portion of the third bus; contemporaneous with the issuing of the second command, issuing an attribute on the second portion of the third bus.