Patent ID: 6912109
Filing Date: 2005-06-28
Classification: H01L

Abstract:
1. An Electrostatic Discharge (ESD) protection circuit that is connected between a first terminal and a second terminal of an Integrated Circuit (IC), whereby said ESD protection circuit has an objective to dissipate an electrostatic pulse that originates from an ESD source that is connected between said first terminal and said second terminal thereby protecting said IC from potential damage that can be caused by exposure of said IC to extreme values of voltage from said ESD source, whereby said ESD protection circuit comprises: an ESD pulse clamp means comprising a PMOS device for shunting said electrostatic pulse from said IC having a first port that is connected to said first terminal of said IC, a second port that is connected to said second terminal of said IC, and a third port; and an ESD pulse detection means having a first input port connected to said first terminal of said IC, a second input port connected to said second terminal of said IC, an output port that is connected to said third port of said ESD pulse clamp means, wherein said ESD pulse detection means comprises a voltage inverter directly controlling a gate electrode of said PMOS device, whereby in detecting a presence of said electrostatic pulse said ESD pulse detection means generates a voltage that triggers said ESD pulse clamp means thereby shunting said electrostatic pulse from said IC.