Patent ID: 8158463
Filing Date: 2012-04-17
Classification: H01L

Abstract:
1. A process for manufacturing a MOS device, comprising: forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure comprising an electrode region above said semiconductor layer; forming body regions, having a second type of conductivity, within said semiconductor layer laterally and partially underneath said insulated gate structure; forming source regions having said first type of conductivity within said body regions; and forming a first enrichment region in a surface portion of said semiconductor layer underneath said insulated gate structure, said first enrichment region having said first type of conductivity and being set at a distance from said body regions, wherein forming the first enrichment region comprises: defining a first enrichment window within said insulated gate structure; and introducing first dopant species of said first type of conductivity through, and in a way self-aligned to, said first enrichment window; further comprising: forming a plurality of MOS devices are formed in and on the semiconductor layer, and defining a body/source window adjacent each body and source region and between the insulated gate structures of adjacent MOS devices along a transverse direction, such that each body/source window has a dimension L wherein the ratio of L