Patent ID: 6314028
Filing Date: 2001-11-06
Classification: G11C

Abstract:
A semiconductor memory device comprising:a first sense power source voltage supply line;a second sense power source voltage supply line;a plurality of memory cells arranged in rows and columns;a plurality of bit line pairs, provided corresponding to the respective columns, each connecting to memory cells on a corresponding column;sense amplifier circuits, provided corresponding to the bit line pairs, each receiving operating power supply voltages from the first and second sense power source voltage supply lines to differentially amplify voltage of a corresponding bit line pair when activated;a sense power supply circuit for comparing a reference voltage with a voltage of said first sense power source voltage supply line and transferring charge between said first sense power source voltage supply line and a first power supply node according to a comparison result; anda level control circuit for monitoring an amount of charge transferred by said sense power supply circuit and transferring charge, of an amount corresponding to a monitored amount of charge, between said second sense power source voltage supply line and a second power supply node.