Patent ID: 8013633
Filing Date: 2011-09-06
Classification: H03K

Abstract:
1. A logic circuit comprising: a first level shifter comprising: a first NMOS transistor having a gate and drain coupled to a first supply voltage and a source coupled to a first node; and a second NMOS transistor coupled between the first node and a ground and having a gate to which a first input signal of the logic circuit is applied, the first supply voltage being higher than a high state of the first input signal and higher than a high state of an output signal from the logic circuit; a logic stage comprising: a third NMOS transistor coupled between a second supply voltage and a second node and having a gate coupled to the first node; and a fourth NMOS transistor coupled between the second node and the ground and having a gate to which the first input signal of the logic circuit is applied, wherein the output signal of the logic circuit is provided at the second node and the high state of the output signal corresponds to the second supply voltage; and a second level shifter comprising: a fifth NMOS transistor having a gate and a drain coupled to the first supply voltage and a source coupled to a third node; and a sixth NMOS transistor coupled between the third node and the ground and having a gate to which a second input signal of the logic circuit is applied, wherein the logic stage further comprises: a seventh NMOS transistor coupled between the second supply voltage and the second node and having a gate coupled to the third node; and an eighth NMOS transistor coupled between the second node and the ground and having a gate to which the second input signal of the logic circuit is applied.