Patent ID: 6150855
Filing Date: 2000-11-21
Classification: H03B,H03K,H03L

Abstract:
A frequency multiplier system comprising equally phase-shifted input signals of an identical frequency and a tree of gates, each of the Exclusive-OR type and each having two inputs and one output, said tree having at least three levels of gates including an input level of gates for receiving said phase-shifted input signals on respective inputs thereof, at least a first intermediate level of gates, said first intermediate level of gates receiving first output signals of the input level of gates on respective inputs thereof, which first output signals are a frequency multiple of said identical frequency of said phase-shifted input signals, and providing second output signals which are a frequency multiple of said phase-shifted input signals, and an output level of one gate coupled to the second output signals of said first intermediate level of gates and providing a third output signal which constitutes the output of said frequency multiplier system and which is a frequency multiple of said identical frequency of said phase-shifted input signals, at least one of said two inputs of each of said gates of said first intermediate level of gates receiving a respective one of said first output signals of the input level, and each of said phase-shifted input signals to said input level of gates flowing through an equal number of said gates to provide said third output signal of said frequency multiplier system,wherein said phase-shifted input signals are received from outputs of a phase-locked loop circuit (10) comprising a phase comparator (11) configured for receiving an input signal (CL) and a negative feedback signal (FB), the negative feedback signal being produced by a delay circuit (13) comprising an integral number (N) of delay elements (130-137) connected in series producing said outputs of said phase-locked loop and having successive delays from the input signal, which delays are commanded by the output signal of the comparator, andwherein said tree is arranged to assign equal propagation times between said phase-shifted input signals applied to said tree and the output signal of the tree.