Patent ID: 6969658
Filing Date: 2005-11-29
Classification: H01L

Abstract:
1. A method of forming an integrated circuit device, the method comprising: forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate; forming third and fourth spaced apart source/drain regions on the surface of the semiconductor substrate; forming a first gate insulating layer having a relatively uniform thickness on the semiconductor substrate extending between the first and second spaced apart source/drain regions; forming a second gate insulating layer on the semiconductor substrate extending between the third and fourth spaced apart source/drain regions; forming a first gate electrode on the first gate insulating layer such that the first gate insulating layer is between the semiconductor substrate and the first gate electrode; forming a second gate electrode on the second gate insulating layer such that the second gate insulating layer is between the semiconductor substrate and the second gate electrode; forming a spacer along a side wall of the first and second gate insulating layers and the first and second gate electrodes; providing a masking film on the entire surface of the third and fourth spaced apart source/drain regions while exposing the first and second source/drain regions; and then increasing a thickness of portions of the first gate insulating layer while maintaining the masking film and the spacer so that the first gate insulating layer has a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions and so that a thickness of the first gate insulating layer increases as it extends toward each of the source/drain regions.