Patent ID: 7521995
Filing Date: 2009-04-21
Classification: H03F

Abstract:
1. A power amplifier for amplifying an input signal and providing an amplified signal to a load at a summing node, wherein the load has a first impedance value, the power amplifier comprising: a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal, wherein the phase delayed signal is delayed by substantially a first predetermined degree of phase delay with respect to the undelayed signal; a carrier amplifier path amplifying the phase delayed signal and comprising a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and comprising a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides substantially the first predetermined degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier based on the designed characteristic impedance value, when the peaking amplifier is off.