Patent ID: 8987106
Filing Date: 2015-03-24
Classification: H01L

Abstract:
1. A semiconductor device manufacturing method comprising: forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask; forming a first spacer on a side wall portion on the first side of the gate electrode, and forming a second spacer at least on a side wall portion on a second side of the gate electrode; forming a high-concentration source region having higher impurity concentration than the low-concentration source region inside of the semiconductor substrate on the first side of the gate electrode so as to be separated from the gate electrode by a first distance, and forming a high-concentration drain region having higher impurity concentration than the low-concentration drain region inside of the semiconductor substrate on the second side of the gate electrode so as to be separated from the gate electrode by a second distance greater than the first distance, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode, the first spacer, and the second spacer as masks; and forming a first well having a first electric conductive-type so as to be separated from the drain impurity region.