Patent ID: 6446197
Filing Date: 2002-09-03
Classification: G06F

Abstract:
A processor comprising:a plurality of dedicated address registers for storing a plurality of different branch target addresses; and an instruction decoder decoding an instruction supplied thereto and providing control signals according to results of said decoding; and an execution unit responsive to the control signals and executing said instruction; wherein said instruction can include: 1) a first instruction including an operation code field defining a branch control operation; and an address field used for calculating a branch target address for a branch, and a first register selection field for specifying one of said plurality of dedicated address registers in which said branch target address is to be stored after it is calculated; and 2) a second instruction including an operation code field defining a branch operation, a second register selection field for specifying one of said plurality of dedicated address registers that stores said branch target address to be used for the branch operation, and a branch condition field for specifying a branch condition to be evaluated in determining whether said branch should be taken; wherein said second instruction includes a first length instruction n bits in length, and a second length instruction whose length is 2n bits; and wherein execution by the processor of said first instruction and said second instruction is arranged so as to reduce latency for handling said branch operation, and such that resolution of said branch condition is performed during execution of said second instruction; and further wherein the microprocessor operates with a first mode for executing said first length instruction and a second mode for executing said second length instruction.