Patent ID: 6034886
Filing Date: 2000-03-07
Classification: G11C

Abstract:
An SRAM memory array comprising:a plurality of word lines;a plurality of complementary pairs of data lines crossing the plurality of word lines;a plurality of SRAM memory cells each including a pair of cross-coupled inverters each of the plurality of SRAM memory cells formed at an intersection of a complementary pair of data lines and one of the word lines, each SRAM memory cell including data access circuitry coupled to one of the word lines and to the pair of complementary data lines; anda nonvolatile shadow memory cell including:a first shadow memory access FET having a gate coupled to a control line and a first electrode coupled to an output of one of the cross-coupled pair of inverters;a second shadow memory access FET having a gate coupled to the control line and a first electrode coupled to an output of another of the cross-coupled pair of inverters; anda pair of cross-coupled memory FETs each having a gate coupled to a drain of the other of the pair of cross-coupled memory FETs, each drain of the pair of cross-coupled memory FETs being coupled to a respective second electrode of one of the first and second shadow memory access FETs, the pair of cross-coupled memory FETs also including sources coupled to ground or to a negative supply voltage, each of the pair of cross-coupled memory FETs including nanocrystals of semiconductor material within a gate oxide to provide a nonvolatile memory function.