Patent ID: 8681565
Filing Date: 2014-03-25
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array including a reference cell, a plurality of core cells, and a third memory cell; a first main bit line for the reference cell; second main bit lines for the plurality of core cells; a third main bit line for the third memory cell, the third main bit line being disposed between the first main bit line and the second main bit lines; a first selection transistor which is disposed between a reference cell sub bit line connected to the reference cell and the first main bit line, and is configured to electrically connect the reference cell sub bit line to the first main bit line when in a conductive state, and to electrically disconnect the reference cell sub bit line from the first main bit line when in a non-conductive state; second selection transistors which are each disposed between one of the second main bit lines and one of core cell sub bit lines connected to the plurality of core cells, and are each configured to electrically connect the corresponding core cell sub bit line to the corresponding second main bit line when in the conductive state, and to electrically disconnect the corresponding core cell sub bit line from the corresponding second main bit line when in the non-conductive state; a third selection transistor which is provided between a third memory cell sub bit line connected to the third memory cell and the third main bit line, and is configured to electrically connect the third memory cell sub bit line to the third main bit line when in the conductive state, and to electrically disconnect the third memory cell sub bit line from the third main bit line when in the non-conductive state; a column decoder configured to perform gate control to set the first selection transistor, the second selection transistors, and the third selection transistor to the conductive state or the non-conductive state; and a shield grounding section capable of setting the third main bit line to ground potential, wherein the third selection transistor is connected to the column decoder, is electrically isolated from the first selection transistor and the second selection transistors, and is configured to be switched between the conductive and non-conductive states by the column decoder independently of the first selection transistor and the second selection transistors.