Patent ID: 6785169
Filing Date: 2004-08-31
Classification: G11C

Abstract:
A semiconductor device comprising:a first memory cell and a mirror memory cell, each of the memory cells being adapted to receive and store the same bit in response to a write operation and at least one of the memory cells being more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a bit error in which the stored bit changes from the second state into the first state; and a sense amplifier electrically coupled to the first and mirror memory cells and adapted to provide an output of a â€œ0â€  in response to a read current from the memory cells being less than the read current corresponding to approximately twice the read current corresponding to a single bit when the cell is on and to provide an output of a â€œ1â€  when said read current is egual to approximately twice a read current corresponding to a single bit when the cell is on.