Patent ID: 8037234
Filing Date: 2011-10-11
Classification: G06F,G11C

Abstract:
1. A multi-level flash device comprising: a smart storage switch which comprises: a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); a plurality of flash modules that include the assigned flash module, wherein a flash module comprises: a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected; wherein the raw-NAND flash memory chips in the plurality of flash module are non-volatile memory that retain data when power is disconnected; wherein the smart storage switch further comprises: a virtual buffer bridge, coupled between the smart storage transaction manager and the volatile memory buffer; a sector data buffer, in the volatile memory buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data; a Q-R pointer table, in the volatile memory buffer, for storing a quotient Q and a remainder R generated by division of a host address by L; wherein Q, R, and L are whole numbers; wherein R identifies one of the L locations in the sector data buffer, whereby address mapping is performed at two levels to access the raw-NAND flash memory chips.