Patent ID: 6724656
Filing Date: 2004-04-20
Classification: G11C

Abstract:
For an electrically alterable non-volatile multi-state memory device including a plurality of non-volatile multi-state memory cells, each of the multi-state memory cells including a memory FET having a storage structure, electrons being capable of being injected into the storage structure from a drain-source current path in each of the plurality of non-volatile multi-state memory cells, a method of operating the electrically alterable non-volatile multi-state semiconductor memory device, comprising:setting a parameter of at least one non-volatile multi-state memory cell of the plurality of non-volatile multi-state memory cells selectively among a plurality of states including at least a first state, a second state, a third state and a fourth state in accordance with information to be stored in the one non-volatile multi-state memory cell; generating read reference values for reading the first, second and third states; and reading the one non-volatile multi-state memory cell using the read reference values to evaluate the parameter of the one non-volatile multi-state memory cell, wherein the read reference values are values for a normal read operation in which the information stored in the one non-volatile multi-state memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes evaluating the parameter of the one non-volatile multi-state memory cell with a sense circuit using the read reference values, and wherein the plurality of non-volatile multi-state memory cells are arranged in a matrix of rows and columns disposed substantially in a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of memory FET's of the multi-state memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drain-source current paths of memory FET's of the multi-state memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, including a column select circuit and the sense circuit, is disposed at the second side of the rectangle.