Patent ID: 8225070
Filing Date: 2012-07-17
Classification: G06F

Abstract:
1. An information processing apparatus comprising: a main memory storing data in a plurality of blocks; and a processor connected to the main memory, the processor including: a cache memory that stores data fetched to the cache memory by reading the data out from the main memory block by block, each of the blocks including a plurality of sub blocks; an instruction processing unit that accesses a part of the data in the cache memory sub block by sub block; an entry holding unit that holds a plurality of entries including a plurality of block addresses indicative of blocks of data to be fetched to the cache memory, and access history information indicative of access to the blocks of data in the cache memory by the instruction processing unit, respectively, plural serial addresses being recorded to one entry in the entry holding unit, and each of units of the serial addresses being larger than a cache block in the cache memory; and a controller that determines whether to execute fetching of a block of data indicated by one of the entries in the entry holding unit and controls fetching of data from the main memory to the cache memory while the instruction processing unit accesses sub blocks of data in a block indicated by another of the entries immediately preceding the one of the entries, in accordance with an order of the accesses from the instruction processing unit to segments in the block indicated by the another of the entries and access history information associated with the one of the entries.