Patent ID: 7532051
Filing Date: 2009-05-12
Classification: G06F,Y02D

Abstract:
1. A time delay circuit in a battery protection chip for selecting either an internal delay signal or an external delay signal, comprising: a logic gate having two input terminals receiving, respectively, an inputting signal and said internal delay signal; a charge-discharge circuit having an input terminal for receiving said inputting signal, and having a first output terminal as a selecting terminal for said internal delay signal and said external delay signal selection, said first output terminal in series connected with an external capacitor to ground; one-clock-period timer coupled with said input terminal of said charge-discharge circuit; an inverse buffer serving as a threshold detector of said charge-discharge circuit; a RS latch having a R terminal connected with an output terminal of said one-clock-period timer, and having a S terminal connected with an output terminal of said inverse buffer; a 2-to-1 multiplexer (MUX 2:1) having two input terminals receiving, respectively, an output signal of said inverse buffer and an output signal of said logic gate by means of two output signals of said RS latch as control signals; and wherein when said external capacitor is discharged to lower than a threshold voltage of said inverse buffer within the runout time of said one-clock-period timer, said internal delay signal will be selected, otherwise, said external delay signal whose delay time depends on said external capacitor will be selected.