Patent ID: 7646082
Filing Date: 2010-01-12
Classification: H01L,H05K

Abstract:
1. A substrate for an integrated circuit package, comprising: a core comprising a dielectric layer with a pattern of large-diameter conductive vias extending therethrough from a top side to a bottom side thereof, wherein the large-diameter conductive vias include signal-bearing vias and voltage plane vias; a first top insulating layer disposed on the top side of the core; a top transmission line reference plane metal layer disposed on a top side of the first top insulating layer; a second top insulating layer disposed on a top side of the top transmission line reference plane metal layer; a top signal layer having conductive paths routed above tops of the voltage plane vias and connected through the first and second top insulating layer and the top transmission line reference plane metal layer to the top side of the signal bearing vias, wherein the top transmission line reference plane metal layer provides a reference plane for transmission lines formed by the conductive paths of the top signal layer, and wherein the top transmission line reference plane metal layer defines regions devoid of metal extending above substantially all of top area of the signal-bearing vias so that capacitive coupling between top ends of the signal-bearing vias and the top transmission line reference plane metal layer is substantially reduced.