Patent ID: 6346725
Filing Date: 2002-02-12
Classification: H01L,Y10S

Abstract:
A contact-less array of non-volatile memory cells, comprising:a row of pairs of stacks of first and second polysilicon layers over a silicon substrate, the first layer polysilicon being insulated from the substrate, and the second layer polysilicon being insulated from the first layer polysilicon; a drain region in the substrate between the two stacks in each pair of polysilicon stacks, the drain region being self-aligned to the edges of the two stacks; a source region in the substrate between two adjacent pairs of polysilicon stacks, the source region being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks, such that the source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located; a third layer of polysilicon over but insulated from the polysilicon stacks by an oxide-nitride-oxide (ONO) composite layer, the third layer of polysilicon forming a wordline in the array; and an ONO side-wall spacer adjacent to each edge of the stacks of polysilicon for insulating the side-walls of each polysilicon stack from the third layer polysilicon, wherein the distance between two adjacent pairs of polysilicon stacks is greater than the distance between the two stacks in each pair of polysilicon stacks.