Patent ID: 6601154
Filing Date: 2003-07-29
Classification: G06F,Y02D

Abstract:
A memory device comprising:a data array having a plurality of memory mats each comprising a plurality of word lines and bit lines having memory cells between the intersections, and a plurality of sense amplifiers coupled to said bit lines; an address array having a plurality of memory mats each comprising a plurality of word lines and bit lines having memory cells between the intersections, and a plurality of sense amplifiers coupled to said bit lines; a first control circuit to activate said data array and address array before performing a hit check on a read address based on a plurality of address information read from said address array, and to stop a data read operation against the mishit memory mats after performing said hit check; and a second control circuit to activate the sense amplifiers of one of said memory mats of said data array after performing a hit check on a read address based on a plurality of address information read from said address array.