Patent ID: 8470614
Filing Date: 2013-06-25
Classification: C23C,H01L

Abstract:
1. A process of forming an integrated circuit, comprising steps: disposing a wafer containing said integrated circuit in a dielectric deposition tool under a TEOS delivery showerhead of said dielectric deposition tool, said showerhead including: forming a layer of silicon dioxide on a top surface of said wafer by providing TEOS gas to said input port, so that: planarizing said silicon dioxide layer using a chemical mechanical polish (CMP) process, so that a thickness difference between an average thickness in said wafer outer annulus and an average thickness in said wafer core after completion of said CMP process is less than half a thickness difference between an average thickness in said wafer outer annulus and an average thickness in said wafer core after formation of said silicon dioxide layer and before said CMP process.