Patent ID: 8963346
Filing Date: 2015-02-24
Classification: H01L

Abstract:
1. A semiconductor device comprising: a first semiconductor wafer having a first plane surface, a second plane surface behind the first plane surface, and a first side surface sharing edges with the first plane surface and the second plane surface; and a second semiconductor wafer having a third plane surface, a fourth plane surface behind the third plane surface, and a second side surface sharing edges with the third plane surface and the fourth plane surface, wherein the first plane surface is contacted with the third plane surface, wherein the first semiconductor wafer has a plurality of first identification trenches, which represents a first property of the first semiconductor wafer, wherein the second semiconductor wafer has a plurality of second identification trenches, which represents a second property of the second semiconductor wafer, wherein each of the plurality of first identification trenches is opened to the first plane surface and to the first side surface, and has a first depth less than a first thickness of the first semiconductor wafer, wherein each of the plurality of second identification trenches is opened to the third plane surface and to the second side surface, and has a second depth less than a second thickness of the second semiconductor wafer, wherein, when the first property corresponds to the second property, the plurality of first identification trenches coincide with the plurality of second identification trenches.