Patent ID: 7067374
Filing Date: 2006-06-27
Classification: H01L

Abstract:
1. An integrated circuit structure comprising: a substrate having a first region and a second region, wherein said first region comprises at least two adjacent first semiconductor features and a region between said two adjacent first semiconductor features, and second region comprises a second semiconductor feature; a dielectric layer on an interior sidewall of said opening between first semiconductor features, and on a sidewall of said second semiconductor feature and over the portion of the substrate adjacent the sidewall of said second semiconductor feature; a stop layer in the first region over the dielectric layer on an interior sidewall of said opening between said two adjacent first semiconductor features, and in the second region on a sidewall of said second semiconductor feature and over a portion of the substrate adjacent the sidewall of said second semiconductor feature; a spacer on the surface of said stop layer in said second region; a patterned cover layer over the stop layer on an interior sidewall of said opening between said two adjacent first semiconductor features and over atleast part of the top surface of said second semiconductor feature, the surface of said spacer and the portion of the substrate adjacent the sidewall of said second semiconductor feature; and a silicide structure only in regions not covered by the patterned cover layer, and over at least part of the top surface of said first and second semiconductor features, and over a surface of the substrate in said region between said two adjacent first semiconductor features in the first region.