Patent ID: 7863122
Filing Date: 2011-01-04
Classification: H01L

Abstract:
1. A method, comprising: forming a mandrel layer on a top surface of a silicon substrate; forming an opening in said mandrel layer, a region of said top surface of said substrate exposed in said opening; filling said opening with silicon to form a silicon fin on said top surface of said silicon substrate followed by removing said mandrel layer; forming a gate dielectric on opposite sidewalls of said fin and said top surface of said substrate on opposite sides of said fin; forming a gate electrode over a channel region of said fin, said gate electrode in direct physical contact with said gate dielectric layer on said opposite sidewalls of said fin; after said forming said gate electrode, forming a protective dielectric layer on regions of said gate dielectric layer on said opposite sidewalls of said fin not protected by said gate electrode; forming a first source/drain in said fin on a first side of said channel region and forming a second source/drain in said fin on a second side of said channel region; after forming said first and second source/drains, removing said gate dielectric from said top surface of said silicon substrate where said gate dielectric is not protected by said gate electrode to expose regions of said substrate on opposite sides of said first and second source/drains; etching said exposed regions of said substrate to form trenches in said exposed regions of said substrate and to remove a portion of said substrate from under a portion of said fin to create a void communicating with said trenches, a pedestal region of said substrate under said channel region remaining to form a body contact to said fin; and filling said void and said trenches with a dielectric material.