Patent ID: 6413803
Filing Date: 2002-07-02
Classification: H01L

Abstract:
A method of forming a metal plug structure, on a semiconductor substrate, with the metal plug structure overlaying a portion of a dopant interface, located in a polysilicon dual gate structure, comprising the steps of:forming said polysilicon dual gate structure, on an underlying gate insulator lay and forming insulator spacers on the sides of said polysilicon dual gate structure, performing a first ion implantation procedure to create N type, heavily doped source/drain regions in a first region of said semiconductor substrate, and to form an N type region in a first portion of said polysilicon dual gate structure, which is located in said first region of said semiconductor substrate; performing a second ion implantation procedure to create P type, heavily doped source/drain regions in a second region of said semiconductor substrate, and to form a P type region in a second portion of said polysilicon dual gate structure, which is located in said second region of said semiconductor substrate; forming a metal silicide layer on the top surface of said polysilicon dual gate structure; depositing an insulator layer, forming an opening in said insulator layer to expose a portion of said metal silicide layer, in a region in which said metal silicide layer directly overlays said dopant interface, of said N type region, and said P type region, in said polysilicon dual gate structure; and forming said metal plug structure in said opening.