Patent ID: 8762916
Filing Date: 2014-06-24
Classification: G06F

Abstract:
1. A method, comprising: determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit; wherein the circuit design is specified in a high level programming language and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit; wherein each data transfer is an argument of the marked function specified in the high level programming language; characterizing each of the plurality of data transfers according to a ratio of size of the data transfer to computational time for a circuit block implementation of the marked function to process the data transfer; correlating each of the plurality of data transfers with resources of the target integrated circuit, at least in part, by determining a number of resources for use in implementing the data transfers according to the ratio for each data transfer; and generating a programmatic description of a data transfer network for the circuit design, wherein the data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.