Patent ID: 8822319
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. A method of manufacturing a non-volatile memory, comprising: providing a substrate comprising a memory cell region, a first periphery circuit region and a second periphery circuit region, the memory cell region comprising a select transistor region; forming a first gate dielectric layer on the substrate in the first periphery circuit region and the select transistor region, the first gate dielectric layer having a first thickness; removing a portion of the first gate dielectric layer on the select transistor region to form a second gate dielectric layer having a second thickness, wherein the second thickness is less than the first thickness; forming the first gate dielectric layer on the substrate of the second periphery circuit region in the step of forming the first gate dielectric layer on the substrate in the first periphery circuit region and the select transistor region; removing the first gate dielectric layer on the second periphery circuit region; and forming a third gate dielectric layer on the substrate on the second periphery circuit region, the third gate dielectric layer having a third thickness, wherein the third thickness is less than the second thickness.