Patent ID: 6232619
Filing Date: 2001-05-15
Classification: H01L

Abstract:
A test chip for measuring the concentration uniformity of an ion implanted dopant impurity in a semiconductor wafer comprising:(a) A plurality of arrays of self aligned gate MOSFETs formed on a semiconductor wafer having an ion implanted dopant impurity, wherein the channel lengths of said MOSFETs are aligned in a direction perpendicular to the direction of travel of an ion implantation beam; and(b) wherein each of said plurality of arrays further comprises a matrix of rows and columns of MOSFETs with a single channel length and a gate electrode spacing which is unique to each said matrix; and(c) wherein the MOSFETs in each row of said matrix of rows are formed over a common active area with gate electrodes extending across said common active area with a fixed center-to-center spacing between said gate electrodes being interconnected in a comb-like pattern terminating at a probe pad exterior to said matrix;(d) wherein the source/drain elements of said MOSFETs are formed in spaces between said gate electrodes said source/drain elements interconnected along the columns of said matrix by conductive contacts and metal interconnections terminating at probe pads exterior to said matrix; and(e) wherein the gate electrodes in each successive row of said matrix, are of the same said fixed center-to-center spacing as those in the preceding row and are offset along the channel direction from those of the preceding row to an extent that the right hand end of a MOSFET channel in the ith row of said matrix aligns with the left hand end of a MOSFET channel in the (i+1)th row of said matrix.