Patent ID: 6614856
Filing Date: 2003-09-02
Classification: H04L

Abstract:
A demodulator for extracting two signals modulated in phase quadrature from an intermediary frequency signal, including:two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the digital converted signal is substantially equal to half the clock frequency; two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, âˆ’1, 1, âˆ’1, 1 . . . at the rate of said clock; and switches arranged for, in a predetermined position, connecting two distinct signals to the two analog-to-digital converters, providing the same clock to the two converters, and continuously providing the two multipliers with value 1.