Patent ID: 7608910
Filing Date: 2009-10-27
Classification: H01L

Abstract:
1. A semiconductor device, comprising: a semiconductor substrate including at least one electrostatic discharge (ESD) protection device; at least one insulating layer disposed on the semiconductor substrate; a fuse part including a plurality of fuses and a fuse protecting layer disposed on the plurality of fuses, the fuse part being disposed on the first insulating layer; at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug; wherein the at least one metal interconnection line and a fuse opening are formed within the at least one insulating layer; a passivation layer disposed on an uppermost metal interconnection line of the at least one metal interconnection line, wherein the passivation layer exposes portions, adjacent to the fuse opening, of the uppermost metal interconnection line; and a device protective layer covering the exposed portions of the uppermost metal interconnection line, the passivation layer, an upper surface of the at least one insulating layer.