Patent ID: 6107657
Filing Date: 2000-08-22
Classification: H01L,Y10S

Abstract:
A semiconductor device comprising an integrated circuit and a capacitor formed on the integrated circuit,wherein the capacitor comprises a bottom electrode composed of a conductive layer formed on an insulating layer of the integrated circuit, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer,the top electrode and bottom electrode of the capacitor are connected with interconnections of the integrated circuit through contact holes provided in an interlayer insulating layer formed so as to cover the capacitor, anda passivation layer is formed to cover the interconnections, and the passivation layer is composed of a phospho-silicate layer and a non-doped silicate layer sequentially from the interconnection side.