Patent ID: 7595663
Filing Date: 2009-09-29
Classification: G11C,H04L

Abstract:
1. An interface circuit for use in a semiconductor device having a signal output mode in which a signal is supplied to the outside, a signal input mode in which a signal is received from the outside, and a signal no-supply mode in which a signal is not supplied from the outside and a signal is not supplied to the outside, the circuit comprising: a signal input/output terminal for receiving a signal from the outside in the signal input mode and a signal from the semiconductor device in the signal output mode; an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device; an output buffer gate circuit having an input terminal and an output terminal, the output terminal being connected to the signal input/output terminal, and having a signal output state in which a signal received at the input terminal is output, and a high-impedance state in which, even when a signal is received at the input terminal, the signal is not output; an output control circuit for causing the output buffer gate circuit to go to the signal output state in the signal output mode and in the signal no-supply mode, and the high-impedance state in the signal input mode, a level control circuit for outputting a first level signal in the signal output mode and a second level signal in the signal no-supply mode; and a logic circuit connected between the semiconductor device and the input terminal of the output buffer gate circuit and for outputting a signal having a predetermined potential level to the output buffer gate circuit when the first level signal is output from the level control circuit and a signal from the semiconductor device to the output buffer gate circuit when the second level signal is output from the level control circuit.