Patent ID: 7274604
Filing Date: 2007-09-25
Classification: G06F,G11C

Abstract:
1. A system comprising: a controller; and a memory device; a bus including a plurality of data lines for transferring input data and output data between the controller and the memory device, a plurality of write strobe lines for transferring timing information of the input data transferred from the controller to the memory device, and a plurality of read strobe lines for transferring timing information of the output data transferred from the memory device to the controller, wherein the memory device includes: a plurality of external terminals coupled to the bus; a memory array for storing data; an auxiliary circuit having auxiliary lines for carrying auxiliary information; and a transceiver circuit coupled to the memory array and the external terminals for transferring the input data and the output data between the memory array and the external terminals, the transceiver circuit also couples to the auxiliary circuit for transferring the auxiliary information from the external terminals to the auxiliary lines, wherein at least one of the external terminals is configured for serially transferring at least one bit of the input data with at least one bit of the auxiliary information.