Patent ID: 7668022
Filing Date: 2010-02-23
Classification: G11C

Abstract:
1. A device for generating clock signals in association with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board, the electronic device comprising: a data buffer for buffering data; a clock divider for dividing a first clock signal having a first clock frequency to generate a second clock signal having a second clock frequency, the second clock frequency being an integer multiple of the first clock frequency; a shift register coupled to receive the second clock signal as a data input signal; the shift register comprising a plurality flip-flops having clock inputs coupled to receive the first clock signal, and being further coupled so that a data output of a preceding flip-flop is coupled to a data input of a following flip-flop so as to shift the second clock signal through the shift register in response to the first clock signal, thereby generating a plurality of shifted clock signals at the respective data outputs of the plurality of flip-flops; and a multiplexer commonly coupled to the data outputs of the flip-flops for selecting a shifted clock signal to serve as an output clock signal for transmission of the buffered data to a memory device.