Patent ID: 8060854
Filing Date: 2011-11-15
Classification: H01L

Abstract:
1. A semiconductor device in which a first fixed potential line for supplying a first high-potential-side reference voltage, a second fixed potential line for supplying a second high-potential-side reference voltage, which is lower than the first high-potential-side reference voltage and a third fixed potential line for supplying a low-potential-side reference voltage are wired and where both a first element configured to operate upon receipt of the first high-potential-side reference voltage and the low-potential-side reference voltage and a second element configured to operate upon receipt of the second high-potential-side reference voltage and the low-potential-side reference voltage are provided, wherein a plurality of the third fixed potential lines are wired in parallel, wherein a group of high-potential-side fixed potential lines containing the first fixed potential line and the second fixed potential line are wired in a plurality at predetermined intervals in a direction perpendicular to the third fixed potential line, wherein, in a layout region, surrounded by a pair of adjacent third fixed potential lines and a pair of groups of adjacent high-potential-side fixed potential lines, where the first element or the second element is arranged, either one of the first fixed potential line and the second fixed potential line is wired between the pair of third fixed potential lines, and wherein in a layout region used for the second element, a second fixed potential line connecting a pair of second fixed potential lines contained respectively in a pair of groups of high-potential-side fixed potential lines that form the layout region is wired between a pair of third fixed potential lines that form the layout region.