Patent ID: 6958943
Filing Date: 2005-10-25
Classification: G11C

Abstract:
1. A programmable timing generator for an SRAM sense amplifier comprising in combination: a. a word line activation signal input terminal to said generator for receiving a word line activation signal; b. a sense amplifier enable signal output terminal, c. a programmable sense amplifier enable signal delay path coupled between said word line activation signal input terminal and said sense amplifier enable signal output terminal, including a plurality of delay element sets that may be alternatively inserted in said enable signal delay path in response to programmable inputs in order to adjust the timing of a leading edge of a sense amplifier enable signal in response to a leading edge of word line activation signal; d. a sense amplifier enable signal pulse width path coupled to said sense amplifier enable signal delay path in order to establish a trailing edge time of said sense amplifier enable signal; e. a sense amplifier reset path coupled to coupled to said sense amplifier enable signal delay path and to a sense amplifier reset output terminal, said sense amplifier reset path introducing a programmable variable delay between an a clock signal that initiates a leading edge of the reset signal at said reset signal output terminal and a trailing edge of the reset signal initiated from said enable signal delay path.