Patent ID: 6320800
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A semiconductor memory comprising:a memory cell array having electrically rewritable memory cells;a plurality of redundant column cell arrays for relieving a defective memory cell in said memory cell array;a decoding circuit for selecting a memory cell of said memory cell array;a plurality of sense amplifier circuits for detecting read data of said memory cell array and for latching write data;data input/output buffers provided between each of said sense amplifier circuits and a corresponding one of data input/output terminals;a defective address storing circuit for storing a defective address of said memory cell array, an input/output terminal to and from which data corresponding to said defective address are inputted and outputted, and a set number for identifying one of said plurality of redundant column cell arrays, which is to be substituted so as to correspond to said input/output terminal;a plurality of redundant sense amplifier circuits for detecting read data of said plurality of redundant column cell arrays and for latching write data;an address comparator circuit for outputting a coincidence detection signal when an input address is coincident with said defective address held in said defective address storing circuit; anda switching circuit which is controlled by said coincidence detection signal for selectively connecting one of said sense amplifier corresponding to said defective address in said plurality of sense amplifier circuits or one of said redundant sense amplifier circuits identified by said set number in said plurality of redundant sense amplifier circuit, to said data input/output buffer in place of one of said sense amplifier circuits corresponding to said defective address,wherein said switching circuit comprises a sense amplifier switching circuit, and a plurality of data switching circuits provided so as to correspond to said plurality of sense amplifier circuit;said sense amplifier switching circuit selectively connects one of said plurality of redundant sense amplifier circuits to said plurality of data switching circuits via one bus line; andsaid plurality of data switching circuit selectively connects one of a corresponding one of said sense amplifier circuits and said sense amplifier switching circuit to said data input/output buffer.