Patent ID: 9176741
Filing Date: 2015-11-03
Classification: G06F

Abstract:
1. A method, comprising: providing a microprocessor, the microprocessor including at least: dividing the inter-cluster second level stage into a plurality of segments; dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time; sequentially associating the first and second segments via one or more pointers; and responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, searching at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments, wherein the dividing, allocating, associating, and searching are implemented at least partially using at least one of (i) at least some hardware blocks of the provided microprocessor or (ii) at least some microcode of the provided microprocessor.