Patent ID: 7345299
Filing Date: 2008-03-18
Classification: H01L,Y10S

Abstract:
1. A semiconductor device comprising: a crystalline layer separated from a semiconductor substrate by a first insulative material; the crystalline layer being less than or equal to about 2000 Å thick and comprising silicon/germanium, with the silicon/germanium comprising from about 10 to about 60 atomic percent germanium; a floating charge trapping media over the crystalline layer, wherein the charge trapping media is a floating plate comprising silicon enriched oxide or silicon enriched nitride; a pair of source/drain regions proximate the charge trapping media and extending into the crystalline layer such that at least a portion of the source/drain regions are within the crystalline layer; the portion of the source/drain regions within the crystalline layer being contained within a single crystal of the silicon/germanium; a second insulative material over the charge trapping media, wherein the second insulative material comprises ONO or high k dielectric material; and a control gate over the second insulative material.