Patent ID: 6243851
Filing Date: 2001-06-05
Classification: G06F

Abstract:
A method for determining the placement of logic modules in an IC, the method comprising the steps of:specifying a first floorplanning algorithm for a first module instantiated in the IC, the first module having an associated first floorplanner using the first floorplanning algorithm;specifying a second floorplanning algorithm for a second module instantiated in the IC, the second module having an associated second floorplanner using the second floorplanning algorithm, where the second floorplanning algorithm is different from the first floorplanning algorithm;executing the first floorplanner according to the specified first floorplanning algorithm; andexecuting the second floorplanner according to the specified second algorithm concurrently with the execution of the first floorplanner, wherein during the concurrent execution the first floorplanner and the second floorplanner exchange information.