Patent ID: 8115235
Filing Date: 2012-02-14
Classification: B82Y,H01L

Abstract:
1. A transistor apparatus comprising: a buffer structure disposed above and on a semiconductive substrate: a bottom barrier structure disposed above and on the buffer structure, wherein the bottom barrier structure includes a InAlAs containing material of a bottom barrier layer and a modulation-doped, beryllium-containing silicon material halo layer; a quantum well structure disposed above and on the bottom barrier structure; a top barrier structure disposed above and on the quantum well structure; an etch-stop layer disposed above and on the top barrier structure; and a gate contact structure coupled to the quantum well structure, wherein the quantum-well structure includes an InGaAs quantum well layer, an InAlAs containing bottom spacer layer, and a InAlAs top spacer layer, and wherein the top barrier structure includes a silicon doping layer disposed above and on the quantum-well structure and an In 0.52 Al 0.48 As-containing top barrier layer disposed above and on the silicon doping layer.