Patent ID: 7019577
Filing Date: 2006-03-28
Classification: G06F,H03L

Abstract:
1. A clock generator comprising: a first circuit adapted to programmably receive an input signal, having a possible range of voltage levels and signal types, and modify a frequency of the input signal by a first programmable amount to generate a first input signal; a feedback loop circuit adapted to receive a feedback signal and modify a frequency of the feedback signal by a second programmable amount to generate a second input signal, wherein the feedback signal is selected from an internal feedback signal and an external feedback signal; a phase-locked loop circuit adapted to receive the first input signal and the second input signal and provide a first output signal; and a second circuit adapted to receive the first output signal and modify a frequency of the first output signal to generate a plurality of second output signals having programmable frequencies, wherein the first and second programmable amount and the programmable frequencies are determined by data stored in electrically erasable memory.