Patent ID: 6430586
Filing Date: 2002-08-06
Classification: G01R,G06F

Abstract:
A controllable bit stream generator for providing a random bit source with a desired probability comprising:a Linear Feedback Shift Register (LSFR) that generates a pseudo-random bit sequence; a variable probability conditioner coupled to said LSFR, which accepts said pseudo-random bit sequence and outputs a corresponding controlled output; means for transmitting said pseudo-random bit sequence from said LFSR to said variable probability conditioner; register means coupled to said variable probability conditioner, said register means including a number of latches and providing a control signal to said variable probability conditioner, wherein said number of latches contains control information and said control signal operates on said pseudo-random bit sequence to produce said corresponding controlled output, wherein further said control signal is utilized by said variable probability conditioner to select a percentage of time said controlled output is active; means, associated with said register means, for selecting an output sequence of said controlled output based on a predetermined and controllable percentage corresponding to a pre-selected percentage of time a bit from said output sequence should be active; and means for outputting said output sequence.