Patent ID: 8077623
Filing Date: 2011-12-13
Classification: G06F

Abstract:
1. A method for determining the routing for a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each of the plurality of signals having a respective source processor element and at least one destination processor element in the processor array, the method comprising: (i) identifying a signal from a plurality of unrouted signals to route; (ii) identifying a candidate route for the signal from the plurality of unrouted signals from the source processor element to the destination processor element, the candidate route using a first subset of switches comprising at least one switch in the network of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal from the plurality of unrouted signals to be routed through the first subset of switches; and (iv) attempting to route the signal from the plurality of unrouted signals using one of the offset values identified in step (iii), wherein each switch in the first subset of switches has an associated routing table that includes entries for each signal to be routed through said switch during the operation of the processor array, and each entry for said signal in the routing table comprises a rate of transfer for the signal that identifies how often the signal is repeated, the offset at which the signal is routed and/or the number of clock cycles required to complete the transfer, wherein step (iv) further comprises: attempting to route the signal from the plurality of unrouted signals using an offset value selected from the values identified in step (iii), such that fragmentation of the routing tables is minimised.