Patent ID: 8237266
Filing Date: 2012-08-07
Classification: H01L

Abstract:
1. An integrated circuit package comprising: a substrate including a plurality of attachment pads; a plurality of discrete components connected to the substrate forming a component layer parallel to and aligned with a surface area of the substrate; an integrated circuit die positioned adjacent to the component layer such that a face of the integrated circuit die is substantially parallel to the surface area of the substrate, wherein the face of the integrated circuit die is aligned with at least a portion of the component layer and at least one of the discrete components is in direct contact with the integrated circuit die to support the integrated circuit die at a first edge of the face of the integrated circuit die aligned with the component layer, wherein terminals of the integrated circuit die are connected to the substrate, wherein the plurality of attachment pads are positioned near edges of the face of the integrated circuit die, and wherein the at least one discrete component supports the integrated circuit die at or near a mid-point along one of the edges of the face of the integrated circuit die; and at least one spacer connected to the surface area of the substrate and to the integrated circuit die for supporting the integrated circuit die, wherein the at least one spacer supports the integrated circuit die at a second edge of the face of the integrated circuit die opposite the first edge, and wherein the spacer is configured to balance the integrated circuit die against the at least one discrete component.