Patent ID: 6515612
Filing Date: 2003-02-04
Classification: G11C,H03F,H03M

Abstract:
A circuit assembly, comprising:an integrator; a first capacitor having a first terminal that is coupled to a first node having a first potential during a first time interval and is coupled to a second node at a reference voltage during a second time interval that does not overlap the first time interval, the first capacitor having a second terminal that is coupled to a third node having a common potential during the first time interval and to the integrator during the second time interval, the first capacitor receiving a first charge component from the second node that is dependent on the first potential during the second time interval; and a second capacitor having a first terminal that is coupled to a fourth node having a second potential during the first time interval, the common potential being substantially midway between the first and second potentials, the second capacitor providing a second charge component that cancels the first charge component during the second interval.