Patent ID: 6320793
Filing Date: 2001-11-20
Classification: G11C

Abstract:
A nonvolatile memory device comprising:a plurality of memory cells;a plurality of data latch circuits;a control circuit; anda plurality of input/output terminals;wherein said control circuit receives a plurality of operation commands from outside said nonvolatile memory device and controls operations according to each operation command, said operation commands comprising a first read command, a first write command and a second write command,wherein in an operation of said first read command, said nonvolatile memory device receives said first read command and a first address information, said control circuit controls reading out data stored in memory cells corresponding to said address information and outputting said reading out data to outside via said plurality of input/output terminals,wherein in an operation of said first write command, said nonvolatile memory device receives said first write command, a first address information and write data, said control circuit controls setting said write data to said plurality of data latch circuits and storing said write data in said data latch circuits to ones of memory cells corresponding to said first address information, andwherein in an operation of said second write command, said nonvolatile memory device receives said second write command and a second address information different from said first address information, said control circuit controls storing said write data in said data latch circuits to memory cells corresponding to said second address information.