Patent ID: 8519761
Filing Date: 2013-08-27
Classification: H03K

Abstract:
1. A slew-rate control circuit for controlling slew rate of a clock signal that is input to a phase interpolator and generating a slew-rate controlled clock signal, the slew rate control circuit comprising: a first pulse measurement circuit operable to receive the clock signal and generate both a first reference voltage from a first clock pulse duration associated with an on-period of the received clock signal and a second reference voltage from a second clock pulse duration associated with an off-period of the received clock signal; a second pulse measurement circuit operable to generate a first voltage from a first pulse duration associated with a rise time of the generated slew-rate controlled clock signal and a second voltage from a second pulse duration associated with a fall time of the generated slew-rate controlled clock signal; and an adjustment circuit operable to generate a first adjustment voltage and a second adjustment voltage, the first adjustment voltage operable to control the rise time of the generated slew-rate controlled clock signal based on comparing the generated first reference voltage and the generated first voltage, and the second adjustment voltage operable to control the fall time of the generated slew-rate controlled clock signal based on comparing the generated second reference voltage and the generated second voltage.