Patent ID: 7209366
Filing Date: 2007-04-24
Classification: H01L,H05K

Abstract:
1. An apparatus, comprising: an integrated circuit (IC) package including a chip carrier and a chip mounted to the chip carrier; the chip carrier having a pair of opposed surfaces including a chip-facing surface adjacent to the chip and a land surface having a plurality of land-side contacts; a centrally located power delivery region and a peripherally located input-output (I/O) delivery region disposed in partially surrounding relationship to the power delivery region, with the power and I/O delivery regions extending from the chip-facing surface to at least the plurality of land-side contacts; a plurality of power and ground paths disposed in the power delivery region and a plurality of I/O signal paths disposed in the I/O delivery region; and wherein the chip carrier further includes a decoupling capacitor electrically coupled between the power and the ground paths and positioned in the power delivery region, with the decoupling capacitor being embedded in the chip carrier and positioned to divide the power delivery region into a first and a second power delivery zone.