Patent ID: 6272741
Filing Date: 2001-08-14
Classification: H01L,H01R,H05K,Y02P,Y10T

Abstract:
A method of fabricating a circuit board interconnect system, comprising the steps of:providing a generally planar carrier board;providing a plurality of electrically conductive pins, each pin having a head connected to a shaft, the head extending in a plurality of radial directions outward from the shaft;inserting the shafts of the pins through the carrier board so that the heads of the pins are adjacent an upper surface of the carrier board and so that the pins are arranged in a first grid array pattern;providing a generally planar circuit board;forming a plurality of electrically conductive pads on a lower surface of the circuit board, there being one conductive pad corresponding to each pin and the conductive pads being arranged in a second grid array pattern complementary to the first grid array pattern;placing a solder ball on top of each head of each pin;melting the solder balls so that each solder ball bonds to the head of a corresponding pin;allowing the solder balls to cool and solidify;positioning the carrier board and the circuit board in substantially parallel relationship with the upper surface of the carrier board opposing the lower surface of the circuit board and with the carrier board and the circuit board being a sufficiently close distance apart so that each of the solder balls physically contacts a corresponding conductive pad;re-melting the solder balls so that each solder ball bridges the close distance and bonds a corresponding conductive pad and an opposing pin head while wrapping around a side surface of the opposing pin head and retaining a substantially round shape; andallowing the solder balls to re-solidify;whereby each of the pins is permanently mechanically and electrically connected by a rounded solder connection to the corresponding conductive pad and fractures in the rounded solder connection due to straightening of the shafts of the pins, loads being exerted on the circuit board in a lateral direction or differential thermal expansion of the carrier board and the circuit board are less likely than in a conventional butt joint solder connection.