Patent ID: 6255182
Filing Date: 2001-07-03
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device, comprising:providing a semiconductor substrate;forming a gate dielectric layer over a device active region, the device active region having a width dimension and a length dimension;depositing a layer of gate electrode material on the gate dielectric layer;depositing a sacrificial layer over the layer of gate electrode material;patterning the sacrificial layer by photolithography and etching such that an edge of the patterned sacrificial layer extends along the width dimension of the device active region, said patterned sacrificial layer comprised of a plurality of sidewalls and wherein dimensions of the patterned sacrificial layer are higher than a radiation wavelength used for the photolithography;depositing a mask layer having a first thickness over the device active region and the patterned sacrificial layer, wherein the first thickness is less than the radiation wavelength;anisotropically etching the mask layer to form sidewall spacers on the side walls of the patterned sacrificial layer;selectively removing portions of the sidewall spacers to define a hard mask comprised of a portion of the sidewall spacers extending along the width dimension of the active area of the device; andanisotropically etching the gate electrode material using the hard mask to form a gate electrode having a length dimension less than the radiation wavelength and wherein the gate length is determined by the first thickness of said mask layer.