Patent ID: 8835223
Filing Date: 2014-09-16
Classification: H01L

Abstract:
1. A method of forming a stacked microelectronic assembly comprising the steps of: (a) juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element, wherein the first semiconductor element has a front surface remote from the major surface, an opening extending between the front and major surfaces thereof at least partly aligned with a surface of a conductive pad exposed at the front surface of the first semiconductor element, wherein the first conductive element is electrically connected to the conductive pad exposed at the front surface of the first semiconductor element through the opening in the first semiconductor element, wherein an interior surface of the opening of the first semiconductor element is lined with a dielectric layer; (b) forming an opening extending through the conductive pad exposed at the front surface of the second semiconductor element and through the first conductive element; and (c) forming a second electrically conductive element through the conductive pad exposed at the front surface of the second semiconductor element, the second conductive element extending at least within the opening in the conductive pad exposed at the front surface of the second semiconductor element and through a thickness of the second semiconductor element, the second conductive element electrically contacting the conductive pad exposed at the front surface of the second semiconductor element and the first conductive element.