Patent ID: 6762449
Filing Date: 2004-07-13
Classification: H01L

Abstract:
A semiconductor integrated circuit device comprising:a semiconductor substrate, wherein said semiconductor substrate, on a main surface thereof, comprises: a memory cell including a MISFET for selecting the memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction, a wiring trench which is formed in an insulating film formed over the MISFET for selecting the memory cell and extends in a second direction intersecting the first direction, a plug buried in a first contact hole formed in the insulating film at the bottom of the wiring trench. a bit line formed in the wiring trench and electrically connected to one of a pair of source and drain of the MISFET for selecting the memory cell via the plug, and a capacitor element for storing information formed over the bit line and electrically connected to the other of the pair of source and drain, wherein a second insulating film is formed over the inside wall of the wiring trench, the bit line is formed inside the second insulating film and the width of the bit line is substantially the same in the second direction and is smaller than the interval between the neighboring bit lines.