Patent ID: 6661694
Filing Date: 2003-12-09
Classification: G11C

Abstract:
A configuration for increasing a storage retention time and a storage security, comprising:a memory cell array having a cell array content, said memory cell array including a plurality of memory cells including a material having a hysteresis property, said memory cells having respective cell contents and being provided in rows and columns; a row decoder and a column decoder connected to said memory cell array for writing to said memory cells; an evaluation unit connected to said memory cell array, said evaluation unit being configured to evaluate the cell contents of said memory cells; a write-back register operatively connected to said evaluation unit, said write-back register being configured such that at least part of the cell array content can be written back N times into said write-back register, N being a number at least equal to one; and a write-back controller connected to said write-back register, said write-back controller controlling a rewriting of the at least part of the cell array content, which has been written back to said write-back register, to said memory cell array via said row decoder and said column decoder.