Patent ID: 6235596
Filing Date: 2001-05-22
Classification: H01L

Abstract:
A method for manufacturing a MOS device with multiple threshold voltages, the method comprising:providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, the top surface of the shallow trench isolation structure is higher than the surface of the substrate, and an active region which is surrounded by the shallow trench isolation structure is defined in the substrate;performing a first process of ion implantation on the substrate except a portion of the substrate under the shallow trench isolation structure;forming a first spacer on the sidewall of a portion of the shallow trench structure above the substrate in the active region;performing a second process of ion implantation on the substrate except a portion of the substrate under the shallow trench isolation structure and the first spacer; andforming a gate in the active region of the substrate, over every threshold-voltage doped region,whereby a pair of source/drain regions is formed beside the gate, andwhereby a MOS device including a gate and source/drain regions, which possess multiple threshold voltages is formed in the active region of the substrate.