Patent ID: 9214241
Filing Date: 2015-12-15
Classification: G11C

Abstract:
1. An erasing method for erasing a semiconductor memory device having a memory array, the memory array having an NAND string, the erasing method comprising: applying a predetermined electrical potential to a gate of a select transistor of the NAND string and applying the predetermined electrical potential to a word line of a memory cell of the NAND string; applying an erasing voltage to a substrate region having the NAND string at a first timing; and floating the gate of the select transistor at a second timing, wherein a fixed time interval is between the first timing and the second timing, and the second timing is later than the first timing, wherein a voltage of the gate of the select transistor is boosted to a first electrical potential due to capacitance coupling between the gate and the substrate region, and the first electrical potential is lower than the erasing voltage.