Patent ID: 9209291
Filing Date: 2015-12-08
Classification: H01L

Abstract:
1. A method of manufacturing a semiconductor device, the method comprising: forming a multilayered structure by alternately stacking first material layers and second material layers on a substrate, wherein the second material layers are formed in a word line region and in a select line region. the select line region being located above the word line region; forming etch stop patterns on the multilayered structure, wherein the etch stop patterns come into contact with an uppermost layer of the second material layers; forming channel holes by etching the multilayered structure using the etch stop patterns as an etch barrier; forming channel layers on surfaces of the channel holes; filling the channel holes and a space between the etch stop patterns with insulating layers; forming recessed regions between the etch stop patterns by recessing the insulating layers; forming impurity-doped layers inside the recessed regions; and forming an interlayer dielectric layer over the impurity-doped layers and the etch stop patterns.