Patent ID: 6703859
Filing Date: 2004-03-09
Classification: H03K

Abstract:
A programmable logic device comprising:a plurality of logic blocks for carrying out logical operation; lines for connecting the logic blocks to one another; line-changing means for changing the state of lines connecting the logic blocks to one another by programming; a clock net for supplying a clock signal for controlling an operation timing to each of the logic blocks, the clock net being provided independently of the lines, and one end of said clock net being a single channel of a clock supply line and the other end of said clock net being branched at a plurality of stages; and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of said plurality of logic blocks, which shifts from an active state to a non-active state, can be stopped from being supplied with the closing signal; wherein the clock control means is composed of a plurality of switching units, each provided just after a branched position at the plural respective stages on said clock net.