Patent ID: 6459147
Filing Date: 2002-10-01
Classification: H01L

Abstract:
A semiconductor package, comprising:a substrate having a top surface with central die-mounting region and a first set of apertures therethrough adjacent to the die-mounting region; a semiconductor die having a top surface and an opposite bottom surface mounted on the die-mounting region of the substrate; and, an electrically conductive strap that includes: a planar cover portion having a bottom surface attached to the top surface of the die with a first electrically conductive material, a down-set portion at an edge of the cover portion that transitions from the cover portion to the substrate, and an elongated flange portion at an edge of the down-set portion having a set of apertures therethrough corresponding to the first set of apertures in the substrate and a bottom surface attached to the substrate with a second electrically conductive material such that corresponding apertures in the substrate and the flange portion are in respective alignment with each other, and such that the material of the second electrically conductive material flows into each of the apertures and forms an interlocking key therein.