Patent ID: 7824951
Filing Date: 2010-11-02
Classification: G11C,H01L

Abstract:
1. A method of fabricating an integrated circuit having a memory, the method comprising: fabricating a first electrode within an insulator material such that the first electrode has a width in a first direction; depositing a layer of resistivity changing material adjacent the first electrode; depositing a low-k dielectric material adjacent the layer of resistivity changing material such that the low-k dielectric material thermally isolates the resistivity changing material; and fabricating a second electrode within an insulator material such that the second electrode has a width in the first direction, such that it is adjacent the resistivity changing material, and such that the low-k dielectric material contacts a portion of each of the first and second electrodes; wherein fabricating the first electrode includes fabricating such that there is more contact between the first electrode and the low-k dielectric material across the width of the first electrode then there is contact between the first electrode and the resistivity changing material across the width of the first electrode; and wherein fabricating the second electrode includes fabricating such that there is less contact between the second electrode and the low-k dielectric material across the of width of the first electrode then there is contact between the second electrode and the resistivity changing material across the width of the second electrode.