Patent ID: 6252298
Filing Date: 2001-06-26
Classification: H01L

Abstract:
A semiconductor chip package comprising:a semiconductor chip having an active surface, and a plurality of input/output (I/O) pads extending across central parts of said active surface;a flexible circuit board including an electrically non-conductive flexible tape having a top surface, a bottom surface, an outer periphery and a central opening therein, and a patterned circuit layer on the top surface of said flexible tape, said circuit layer having a plurality of circuit traces, bonding pads to which first ends of said circuit traces are connected, respectively, and land pads to which second ends of said circuit traces are connected, respectively, wherein said circuit traces, said bonding pads, and said land pads are positioned on the top surface of the flexible tape and within the outer periphery of the flexible tape, and wherein the active surface of said semiconductor chip faces the bottom surface of said flexible tape and the central opening of the flexible tape, with said I/O pads being exposed to the patterned circuit layer through said opening of said flexible tape;a protective layer disposed on the top surface of said flexible tape over said circuit traces, wherein said protective layer has a groove extending therein between said bonding pads and said land pads;a plurality of bonding wires extending between said I/O pads and said bonding pads through said central opening, each of said I/O pads being electrically connected to a respective one of said bonding pads by a respective one of said bonding wires;an encapsulant covering said I/O pads, said bonding pads, and said bonding wires; wherein said encapsulant is confined radially inward by said groove; anda plurality of terminals provided on and electrically connected to said land pads on the top surface of said flexible tape, each of the plurality of terminals providing an electrical connection leading from the semiconductor package.