Patent ID: 7312497
Filing Date: 2007-12-25
Classification: H01L

Abstract:
1. An integrated circuit comprising: a semiconductor substrate comprising a plurality of source/drain regions of nonvolatile memory cells and a plurality of channel regions of the nonvolatile memory cells; a plurality of first conductive gates of the nonvolatile memory cells, the first conductive gate of each memory cell overlying the memory cell's channel region; a plurality of conductive floating gates of the memory cells, each memory cell comprising two floating gates positioned over the memory cell's channel region on opposite sides of the memory cell's first conductive gate; a plurality of conductive gate lines providing second conductive gates for the memory cells, each memory cell having two second conductive gates overlying the memory cell's respective two floating gates and positioned on said respective opposite sides of the memory cell's first conductive gate, the first conductive gate's top surface being higher than the memory cell's second conductive gates; a dielectric overlying the floating gates and the second conductive gates and having a top surface which is higher than the first conductive gates, wherein for each memory cell, the dielectric has a contact opening for contacting the memory cell's first conductive gate, the contact opening overlying the memory cell's first conductive gate and at least one of the memory cell's second conductive gates, the contact opening having a bottom surface which extends laterally beyond the memory cell's first conductive gate over a top of the at least one of the second conductive gates, the contact opening's bottom surface being separated from the memory cell's second conductive gates by the dielectric; one or more conductive interconnect lines overlying the dielectric, each conductive line electrically contacting at least two of the first conductive gates through the respective contact openings.