Patent ID: 6727539
Filing Date: 2004-04-27
Classification: H01L

Abstract:
A semiconductor device including a dual workfunction support transistor and an embedded DRAM array free of a M0 first metal layer, the semiconductor device comprising:a support region comprising a gate structure, source and drain regions adjacent to the gate structure, and a suicide layer disposed on the source and drain regions, wherein the gate structure comprises a dielectric capping layer, a metal conductor and a polysilicon layer; an array region comprising a plurality of embedded DRAM cells, a bitline diffusion region electrically connecting adjacent DRAM cells, an array gate stack structure, a polysilicon layer, wherein the polysilicon layer includes a silicide surface; an isolation region, wherein the isolation region electrically separates the support region from the array region; and an interconnect structure disposed on the isolation region comprising a polysilicon layer and a silicide layer formed on the polysilicon layer, said interconnect structure further in contact with at least one diffusion region.