Patent ID: 7908578
Filing Date: 2011-03-15
Classification: G06F,H01L,Y02P

Abstract:
1. A method for designing a semiconductor chip having one or more functionally interfaced dynamic array sections, comprising: laying out a virtual grate for conductive features used to define a gate electrode level of a dynamic array section, the virtual grate defined by a framework of parallel lines defined at a substantially constant pitch; arranging one or more conductive features along a number of lines of the virtual grate, wherein some of the number of lines of the virtual grate have multiple conductive features arranged thereon; for each line of the virtual grate that has multiple conductive features arranged thereon, defining a gap between proximate ends of each pair of adjacent conductive features such that each gap is defined to maintain a substantially consistent separation between proximate ends of conductive features, and some of the conductive features being designed to define gate electrodes of transistor devices of the dynamic array section; defining each conductive feature to be devoid of a substantial change in direction, such that the conductive features remain substantially aligned to the framework of parallel lines of the virtual grate; and operating a computer to store a resulting arrangement of the conductive features of the dynamic array section as computer readable code on a computer readable storage medium.