Patent ID: 8975092
Filing Date: 2015-03-10
Classification: H01L

Abstract:
1. A method for controlling warpage of a semiconductor assembly comprising: determining a warpage profile of a chip coupled to and spaced apart from a substrate, the chip having a first surface facing the substrate, the warpage profile indicating stress imparted on the chip following a reflow operation; estimating a total warpage for the chip based on the warpage profile, the total warpage being based on a first gap between the chip and a substrate proximate the center of the chip and a second gap between the chip and the substrate proximate an edge of the chip; and based on whether the total warpage is greater than a pre-determined amount, disposing a back layer on the chip on a second surface substantially opposite from the first surface, the back layer having non-uniform thickness, where the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.