Patent ID: 7859291
Filing Date: 2010-12-28
Classification: G01R,H01L

Abstract:
1. A method comprising: providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer; and then forming a current flow path by applying a voltage to gates of the first and second MOS transistors to enable current flow through the drain via a channel from the source of the first MOS transistor to pass through the source of the second MOS transistor via a channel of the second MOS transistor; and then measuring a resistance between the sources of the first and second MOS transistors, wherein the voltage to the gate of the first MOS transistor is a first test voltage and the voltage applied to the gate of the second MOS transistor is a second test voltage, and wherein the first test voltage is equal to the second test voltage.