Patent ID: 9012966
Filing Date: 2015-04-21
Classification: H01L

Abstract:
1. A device, comprising: a semiconductor substrate; a first middle of line (MOL) conductive layer, comprising a first capacitor plate on the semiconductor substrate and covering at least a portion of a shallow trench isolation region in the semiconductor substrate; an insulator layer including a first portion on the first capacitor plate and a second portion on a first surface of each of a first set of local conductive interconnects to source and drain regions of the device, in which the first and second portions of the insulator layer are on a same layer and the insulator layer having a surface coplanar with a second surface of each of the first set of local conductive interconnects; a second MOL conductive layer, comprising a second capacitor plate on the insulator layer; a first interconnect coupled to the first capacitor plate; and a second interconnect coupled to the second capacitor plate.