Patent ID: 6446215
Filing Date: 2002-09-03
Classification: G06F,Y02D

Abstract:
A computer system comprising:an interface comprising one or more buses; a processor connected to the interface, the processor configured to transmit at least a first forwarded clock corresponding to at least one of the one or more buses; and a bus bridge connected to the interface, the bus bridge configured to transmit at least a second forwarded clock corresponding to at least one of the one or more buses; wherein the bus bridge is coupled to receive the first forwarded clock for capturing data transmitted by the processor, and wherein the processor is coupled to receive the second forwarded clock for capturing data transmitted by the bus bridge; and wherein the bus bridge is configured to use a first signal to indicate whether or not the processor is to be disconnected from the interface, and wherein the processor is configured to use a second signal to indicate whether or not the processor is to be disconnected from the interface, and wherein the processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected from the interface.