Patent ID: 6529427
Filing Date: 2003-03-04
Classification: G11C

Abstract:
A method of testing DRAM devices, said method to comprise:providing a DRAM device, said DRAM device containing a multiplicity of DRAM cells; selecting at least one first set of three DRAM cells from said DRAM devices; biasing said at least one first set of three DRAM cells, said biasing said at least one first set of three DRAM cells is providing one of ten different conditions of bias to the word lines of one of said three selected DRAM cells, said conditions of bias hereby referred to as bias 1 through and including bias 10, whereby it is assumed that all word lines contained within said at least one first set of three DRAM cells are biased at the same value of voltage, said three DRAM cells of said at least one set of three DRAM cells being referred to as cell 1 and cell 2 and cell 3; measuring at least one leakage current in said at least one first set of three DRAM cells; and calculating one or more leakage currents based on said measurements.