Patent ID: 6133054
Filing Date: 2000-10-17
Classification: G01R

Abstract:
A method for testing integrated circuits comprising:forming integrated circuits on a semiconductor device substrate, wherein the integrated circuits include an uppermost level of interconnects;forming a polyimide layer over the uppermost level of interconnects;forming a conductive layer over the polyimide layer,patterning the conductive layer to form conductive members, wherein a first conductive member electrically couples to a first electrical contact portion on a first integrated circuit, and wherein the first conductive member includes a first conductive lead portion and a first fuse portion, wherein the first fuse portion is positioned between the first conductive lead portion and the first electrical contact portion;applying a voltage to the first electrical contact portion via the first conductive member, wherein the first fuse portion is adapted to forming an electrical open between the first conductive lead portion and the first electrical contact portion if an amount of current flowing through the first fuse portion exceeds a predetermined threshold; andremoving at least a portion of the first conductive member.