Patent ID: 6172928
Filing Date: 2001-01-09
Classification: G11C

Abstract:
A semiconductor memory device having a normal mode and a power down mode, comprising:a plurality of memory cells arranged in rows and columns;a plurality of first word lines arranged in rows;a plurality of bit line pairs arranged in columns;a sense amplifier amplifying a data signal of said plurality of bit line pairs;an address buffer generating an internal address signal in response to an external address signal;a self refresh control circuit generating a refresh address signal in said power down mode;a row decoder generating a decode signal in response to said internal address signal in said normal mode, and generating the decode signal in response to said refresh address signal in said power down mode;a plurality of first word line drivers provided corresponding to said plurality of first word lines to activate the first word line in response to said decode signal;a first power supply supplying a power supply voltage to said sense amplifier, said address buffer, said self refresh control circuit, said row decoder, and said plurality of first word line drivers in said normal mode, and not supplying the power supply voltage to said sense amplifier, said address buffer, said self refresh control circuit, said row decoder, and said plurality of first word line drivers in said power down mode; anda second power supply supplying a power supply voltage to said sense amplifier, said self refresh control circuit, said row decoder and said plurality of first word line drivers in said power down mode, and not supplying the power supply voltage to said sense amplifier, said self refresh control circuit, said row decoder and said plurality of first word line drivers in said normal mode.