Patent ID: 6567324
Filing Date: 2003-05-20
Classification: G11C

Abstract:
A semiconductor memory device, comprising:n memory regions, each of said n memory regions including a normal memory region, and a replacement region operating in place of a partial region of said normal memory region when an operation failure is found in said partial region; n selecting circuits provided corresponding to said n memory regions respectively, and each selecting said replacement region instead of said partial region in accordance with selection information; n control buses transmitting said selection information to said n selecting circuits respectively; and a setting circuit holding, when specified information indicating said partial region is set, said specified information in a non-volatile manner, and comparing an input address signal with said specified information, and outputting said selection information, said setting circuit including m program sets setting m pieces of said specified information respectively, and m bus selecting and outputting circuits selecting one of said n control buses in accordance with outputs of said m program sets respectively, and outputting said selection information, said n being a natural number of at least 2, and said m being a natural number of at least 1.