Patent ID: 7614023
Filing Date: 2009-11-03
Classification: G06F

Abstract:
1. A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit, the method comprising executing instructions stored on a computer storage device that cause a processor to: retrieve a first capacitance value associated with an upper bound on the terminal capacitance and a second capacitance value associated with a lower bound on the terminal capacitance; perform a timing analysis of the digital circuit; determine a temporal overlap of a pulse edge of a terminal voltage associated with the terminal and of a pulse edge of a further terminal voltage associated with a further terminal of the cell; and determine an estimation value for the terminal capacitance based on results of the timing analysis, at least one of the first capacitance value and the second capacitance value, and the temporal overlap of the pulse edge of the terminal voltage and of the pulse edge of the further terminal voltage.