Patent ID: 6414538
Filing Date: 2002-07-02
Classification: G05F

Abstract:
A bias circuit integrated in a semiconductor chip and packaged in a semiconductor chip package, said bias circuit configured to provide stable bias currents in high speed transistor logic, wherein said bias circuit comprises:a bias voltage generator having a first supply input coupled to a first supply pin of the chip package, a bias voltage output, and a second supply input coupled to a second supply pin of the chip package; a low-pass filter having a filter input coupled to said bias voltage output, a first filter output, and a second filter output coupled to a third supply pin of the chip package; and a current source having a control input coupled to said first filter output, and a power supply input coupled to said third supply pin, wherein said low-pass filter is configured to reduce AC overshoot oscillations of a bias voltage generated by said bias voltage generator at said bias voltage output.