Patent ID: 6143602
Filing Date: 2000-11-07
Classification: H01L

Abstract:
A method of forming a integrated circuit memory device, comprising the steps of:forming a first electrically insulating layer on a semiconductor substrate containing active and inactive regions therein;forming a first contact hole in the first electrically insulating layer, to expose the active region;forming a first electrically conductive contact plug in the first contact hole and in contact with the active region;forming a second electrically insulating layer on the first electrically insulating layer and on the first electrically conductive contact plug, wherein the second electrically insulating layer comprises a first interdielectric layer, an intermediate insulating layer and a second interdielectric layer;forming a second contact hole in the second electrically insulating layer, to expose the first electrically conductive contact plug;forming a second electrically conductive contact plug in the second contact hole and in contact with the first electrically conductive contact plug;etching back the second interdielectric layer using the intermediate insulating layer as an etch stop layer to expose sidewalls of the second electrically conductive contact plug; andforming a capacitor electrode on the second electrically conductive contact plug and in contact with sidewalls thereof.