Patent ID: 6261916
Filing Date: 2001-07-17
Classification: H01L

Abstract:
A process for manufacturing multi-crystal silicon integrated resistors in MOS technology, comprising the steps of:forming a multi-crystal silicon layer on a single-crystal silicon body and insulated therefrom by insulating regions, including the steps of:depositing multi-crystal silicon on the insulating regions;first doping of said multi-crystal silicon;masking selective portions of said multi-crystal silicon with a doping mask; andsecond doping of said multi-crystal silicon, said selective portions having, after said second doping, a conductivity lower than adjacent portions of said multi-crystal silicon;forming masking regions on the multi-crystal silicon layer;forming a metal silicide layer on and in contact with said multi-crystal silicon layer so as to form a double conductive layer; andetching said double conductive layer to form gate regions, the masking regions being of material resistant to the etching of said double conductive layer, and the portions of said multi-crystal silicon layer masked by said masking regions thereby forming resistive regions that are isolated from the double conductive layer and having a resistivity greater than said gate regions.