Patent ID: 9224870
Filing Date: 2015-12-29
Classification: G02F,H01L

Abstract:
1. A semiconductor device comprising: a gate wiring layer, a source wiring layer, and a power supply line; a first transistor; a second transistor including a gate electrode, a source electrode, and a drain electrode; a capacitor including a first electrode and a second electrode; an insulating layer over the first transistor, the second transistor, and the capacitor; and a pixel electrode layer over the insulating layer, wherein the first transistor comprises: a drain electrode layer over the oxide insulating layer, the drain electrode layer electrically connected to the oxide semiconductor layer through the second contact hole of the oxide insulating layer; and wherein the source electrode layer of the first transistor overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween, wherein the drain electrode layer of the first transistor overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween, wherein the gate wiring layer includes the gate electrode layer of the first transistor, wherein the source wiring layer includes the source electrode layer of the first transistor, wherein the gate wiring layer intersects with the source wiring layer in a wiring intersection, wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer, wherein the drain electrode layer of the first transistor is electrically connected to the first electrode of the capacitor, wherein the drain electrode layer of the first transistor is electrically connected to the gate electrode of the second transistor, wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the power supply line, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the pixel electrode layer, and wherein the oxide insulating layer comprises silicon.