Patent ID: 7847414
Filing Date: 2010-12-07
Classification: H01L

Abstract:
1. A chip package structure, comprising: a first substrate having a plurality of first bonding pads, wherein the first bonding pads includes a plurality of bump pads and a plurality of wire bonding pads; a second substrate having a plurality of second bonding pads, the second substrate being disposed above the first substrate; a plurality of bumps disposed between the first substrate and the second substrate, wherein each of the bump pads is respectively electrically connected to one of the second bonding pads via one of the bumps; a first B-staged adhesive layer adhered on the first substrate; and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps, the first B-staged adhesive layer comprises a plurality of first B-staged adhesive pillars, and the second B-staged adhesive layer comprises a plurality of second B-staged adhesive pillars; a carrier; and a plurality of bonding wires, wherein the first substrate and the second substrate are disposed on the carrier, each of the bonding wires is electrically connected to the carrier through one of the wire bonding pads directly, and the bonding wires are not in contact with the bumps.