Patent ID: 8918589
Filing Date: 2014-12-23
Classification: G06F

Abstract:
1. A memory controller which controls access to a memory which stores image data and which is accessed in burst mode at a burst length of N that is an integer number of two of more, the memory including: the prefetch buffer including a first operating mode where the N-bit parallel data is prefetched from one of the plurality of banks and a second operating mode where N/2-bit parallel data is prefeteched from each of two banks belonging to different groups, said memory controller comprising: a command generation unit configured to generate a plurality of access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in the image data; and a command issuance unit configured to issue, to the memory, the plurality of access commands generated by said command generation unit, wherein said command generation unit includes wherein said command generation unit is configured to generate the plurality of access commands including a first access command and a second access command, in the case where the data to be accessed is continuous across two banks belonging to different groups, wherein the first access command is a command for accessing to a bank belonging to the first group, using a half of the prefetch buffer, wherein the second access command is a command for accessing to a bank belonging to the second group, using a remaining half of the prefetch buffer, the second access command sharing the prefetch buffer with the first access command, wherein said command generation unit is configured to generate a third access command, in the case where the data to be accessed belongs to one of the first group and the second group, and wherein the third access command is a command for accessing to a bank belonging to one of the first group and the second group, using all of the prefetch buffer.