Patent ID: 7084962
Filing Date: 2006-08-01
Classification: G03B,G03F

Abstract:
1. A method for detecting positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer, comprising: providing a semiconductor wafer with a substrate; transferring at least one multiple arrangement of a first test structure by photolithographic projection into at least one resist layer above the substrate, the first test structure having a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark; determining values of a first positioning error of the first circuit pattern relative to the first overlay marks and the first micropatterned alignment marks for each element of the at least one multiple arrangement; transferring at least one multiple arrangement of a second test structure by photolithographic projection into at least one resist layer above the substrate, the second test structure having a second circuit pattern, at least one second overlay mark, which can be used together with the first overlay mark for determining the overlay accuracy, and at least one second micropatterned alignment mark; determining values of a second positioning error of the second circuit patterns relative to the second overlay marks and the second micropatterned alignment marks for each element of the at least one multiple arrangement; determining a relative positioning error of the at least one resist layer from the first positioning error and the second positioning error for each element of the at least one multiple arrangement; and determining overlay accuracy within an image field of the projection apparatus as a function of the relative positioning errors determined each element of the at least one multiple arrangement.