Patent ID: 6620679
Filing Date: 2003-09-16
Classification: H01L

Abstract:
A method of fabricating a 1T RAM, comprising the steps of:providing a substrate having a core area, a 1T RAM cell area and an I/O area; forming a first poly gate over the substrate within the core area; the first poly gate having exposed side walls; forming respective pairs of capacitor plates and adjacent word lines over the substrate within the 1T RAM cell area to form node junctions between the respective capacitor plates and adjacent word lines and a bit line contact junction between the word lines; the capacitor plates and the word lines each having exposed side walls; forming a second poly gate over the substrate within the I/O area; the second poly gate having exposed side walls; forming first patterned masks over the substrate to expose: the core area; the bit line contact junction; and portions of the node junctions adjacent the word lines; performing a first implantation; performing a tilt implantation; removing the first patterned masks; forming second patterned masks over the substrate to expose: the I/O area and the 1T RAM cell area not within the bit line contact junction; performing a second implantation; forming sidewall spacers so that the adjacent sidewall spacers between the respective pairs of capacitor plates and word lines being nearly merged; and performing a third implantation.