Patent ID: 8437184
Filing Date: 2013-05-07
Classification: H01L

Abstract:
1. A method of controlling a vertical dual-gate dynamic random access memory which includes a bit line formed on a surface of a substrate, a plurality of pillars located on the bit line and spaced from each other, a plurality of trenches each of which being formed between any two of the plurality of pillars, a dielectric layer formed on a surface of the trench and a plurality of gates located in the trenches and spaced from the pillars by the dielectric layer, the pillars including a first pillar and a second pillar, the method comprising: providing a short circuit state to control a first gate and a second gate which are located at two sides of the first pillar to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar; providing a clearing state to control the first gate and the second gate to respectively have a clearing voltage to disconnect the electric connection between the drain and the source at the two ends of the first pillar, the clearing voltage having an absolute value smaller than that of the turn-on voltage; and providing a false broken circuit state to control the second gate and a third gate which are located at two sides of the second pillar to respectively have a turn-on voltage while the first gate is controlled to have a cut-off voltage so that a false broken circuit is formed between the drain and the source at the two ends of the first pillar, and electric connection is formed between a source and a drain at two ends of the second pillar.