Patent ID: 7945765
Filing Date: 2011-05-17
Classification: G06F

Abstract:
1. An electronic apparatus, comprising: a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands; and a shortening circuit respectively associated with each of at least one stage of said pipeline, to recognize one or more of input operands for said stage for which shortening has been predetermined as appropriate and to execute said shortening when appropriate, wherein, in each stage having said shortening circuit, data bits of the input operand are presented both to an operational circuit of said stage, for potential processing of the input operand by the operational circuit, and to the shortening circuit, for evaluation whether the input operand will permit shortening of that stage, wherein said input operand is precluded from shortening if a processing in a stage immediately following said stage would be disrupted by said passing to said following stage, wherein said input operand comprises a valid bit and said shortening is precluded by monitoring the valid bit of the input operand of said following stage.