Patent ID: 6260175
Filing Date: 2001-07-10
Classification: G06F

Abstract:
A method of designing an integrated circuit including at least one predefined and preverified core module and a custom logic circuit, said method comprising:predefining said core module with a first plurality of clock inputs, wherein each of said clock inputs of said core module is coupled to a first given number of clocked elements of said core module, and wherein said first given number is identical for each of said clock inputs of said core module;preverifying a proper operation of said core module;selecting said core module for incorporation within said integrated circuit from a library of a plurality of predefined and preverified core modules;defining said custom logic circuit with a second plurality of clock inputs, wherein each of said clock inputs of said custom logic circuit is coupled to a second given number of clocked elements of said custom logic circuit, wherein said second given number is identical for each of said clock inputs of said custom logic circuit, and wherein said second given number is an integer multiple of said first given number; andforming a chip-level balanced clock tree distribution network, wherein each clock input of said core module forms a leaf-level fan-out element within said chip-level balanced clock tree clock distribution network, wherein each clock input of said custom logic circuit forms an additional leaf-level fan-out element within said chip-level balanced clock tree clock distribution network, and wherein each of said clock inputs of said core module and each of said clock inputs of said custom logic circuit receive a clock signal conveyed from a clock distribution point.