Patent ID: 6944042
Filing Date: 2005-09-13
Classification: G11C

Abstract:
1. A memory cell for storing data in a semiconductor device, the memory cell comprising: a volatile portion adapted to store a binary volatile data state, wherein the volatile portion comprises first and second internal nodes: a non-volatile portion coupled with the volatile portion, the non-volatile portion being adapted to store two or more binary non-volatile data states, wherein the non-volatile portion comprises a plurality of first ferroelectric capacitors coupled with the first internal node of the volatile portion and a plurality of second ferroelectric capacitors coupled with the second internal node of the volatile portion: and a control circuit coupled with the volatile and non-volatile portions and providing a plurality of plateline signals to the non-volatile portion, wherein the non-volatile portion comprises a plurality of ferroelectric capacitor pairs, the ferroelectric capacitor pairs being individually operable to store a binary non-volatile data state and individually comprising one of the plurality of first ferroelectric capacitors and one of the plurality of second ferroelectric capacitors, and wherein the plateline signals are individually coupled with one of the ferroelectric capacitor pairs.