Patent ID: 7640155
Filing Date: 2009-12-29
Classification: G06F

Abstract:
1. A target interface system for interfacing a hardware emulation system and a target system, comprising: target interface logic that is distributed among a plurality of reconfigurable logic devices; a plurality of input/output connections that are in communication with the reconfigurable logic devices; and a memory structure that stores data for configuring said input/output connections via said target interface logic and that is divided into a plurality of hierarchical memory subspaces for organizing the configuration data, said hierarchical memory subspaces including a first memory subspace that stores dynamic configuration data for at least one first selected input/output connection with a configuration that is adjustable for each target interface cycle within an emulation cycle and a second memory subspace that stores static configuration data for at least one second selected input/output connection with a configuration that is fixed throughout the emulation cycle, wherein said hierarchical memory subspaces within said memory structure can be modified to implement a preselected memory hierarchy.