Patent ID: 6171951
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A dual damascene manufacturing method suitable for a substrate having a device structure, wherein the substrate has a first conductive layer formed thereon, the process comprising the steps of:forming a first dielectric layer over the substrate;forming a hard material layer having a first opening on the first dielectric layer, wherein the first opening exposes the first dielectric layer over the first conductive layer;forming a second dielectric layer on the hard material layer that covers the exposed first dielectric layer within the first opening;performing a first ion implanting step on the second dielectric layer;forming a hard mask layer having at least a second opening on the second dielectric layer, the second opening being aligned over the first conductive layer, wherein the second opening formed within the hard mask layer is broad at the top and narrow at the bottom;using the hard mask layer and the hard material layer as etching stop layers to etch the second dielectric layer and the first dielectric layer to connect the first opening and the second opening to form a third opening, wherein the third opening exposes the first conductive layer;performing at least a second ion implanting step on the second and first dielectric layers exposed within the third opening;forming a barrier layer in the third opening;forming a second conductive layer to fill the third opening, wherein the second conductive layer and the second dielectric layer have the same height.