Patent ID: 6507066
Filing Date: 2003-01-14
Classification: H01L

Abstract:
A Flash EEPROM memory device including a doped substrate composed of silicon semiconductor material having a gate electrode stack formed on the top surface of the substrate, a source region and a drain region formed in the surface of the doped substrate comprising:the gate electrode stack comprising a floating gate electrode, and a control gate formed over the top surface of the substrate, the source region and the drain region being located in the surface of the substrate, with the source region and the drain region being located aside from the gate electrode stack in overlapping relationship with the gate electrode stack, and a surface halo region formed only in the surface of the source region extending partially into the source region and surrounded by the source region and the halo region being juxtaposed with the gate electrode stack with a slight overlap in position of the halo region with the gate electrode stack, and the drain region being formed without a halo region, whereby the channel erase function can be performed with a similar bias condition to the source erase function.