Patent ID: 6134169
Filing Date: 2000-10-17
Classification: G11C

Abstract:
A semiconductor memory device, comprising:a plurality of memory cells;a plurality of word lines controlled by an output of a row decoder for selecting some of the plurality of memory cells;a plurality of bit line groups for transferring data read out from the memory cells which are simultaneously selected by each of the plurality of word lines;a plurality of first sense line groups connected respectively to the plurality of bit line groups via a first switch section;a plurality of second sense line groups connected respectively to the plurality of bit line groups via a second switch section;a plurality of first sense amplifiers connected respectively to the plurality of first sense line groups;a plurality of second sense amplifiers connected respectively to the plurality of second sense line groups;a plurality of third switch sections which are connected respectively to the plurality of first sense line groups and controlled by an output of a column decoder;a first common data line connected to the plurality of third switch sections;an input/output circuit connected to the first common data line for inputting/outputting data from/to an external unit; anda control circuit for controlling the plurality of third switch sections so as to transfer data latched by the plurality of first sense amplifiers to the input/output circuit via the first common data line, wherein:a read operation is performed by activating a first word line of the plurality of word lines, transferring data read out from the memory cells simultaneously selected by the first word line via the plurality of bit line groups, latching the data from the plurality of bit line groups in the plurality of first sense amplifiers via the first switch section, transferring data from one of the plurality of first sense amplifiers to the first common data line via one of the plurality of third switch sections, and outputting the data from the first common data line to an external unit; anda refresh operation is performed, simultaneously with the read operation, by activating a second word line of the plurality of word lines, and refreshing data read out from the memory cells simultaneously selected by the second word line using the plurality of second sense amplifiers via the second switch section.