Patent ID: 6141765
Filing Date: 2000-10-31
Classification: G06F,Y02D

Abstract:
A high speed interconnect system which permits the high speed operation of the bus without a free running clock and synchronization circuit to resynchronize local clocks to the data transmission between a data source and a data destination, the system comprising:a transmit strobe signal output drive circuit located in the data source connected to the bus, the transmit strobe signal output drive circuit comprising a generator for generating signal edges which are synchronous to transmitted command/data information from the data source;a receive strobe input circuit located in a data destination and coupled to the transmit strobe signal output drive circuit, the input circuit comprising means for latching the transmitted command/data information from the data source based on the received signal edges;wherein each data destination and each data source comprises means for communicating a bus grant signal and a bus request signal across a signal lines connecting each data source and each data destination to an arbitration circuit to obtain control of the bus and permit multiple bus request and grant signals over the bus to be active simultaneously; andmeans for providing simultaneous mesochronous and asynchronous signaling across a shared bus and to a common multi-ported memory.