Patent ID: 7797494
Filing Date: 2010-09-14
Classification: G06F

Abstract:
1. An arithmetic processor connected to a memory unit as an address translation table retaining a first address translation pair which is a pair of a first physical address at which data is retained and a first virtual address corresponding to the first physical address, the arithmetic processor comprising: a cache memory; an address translation buffer retaining a second address translation pair which is a pair of a second physical address indicating an address at which the first address translation pair is retained in said memory unit and a second virtual address corresponding to the second physical address, and being able to retain the first address translation pair; a first retrieval unit retrieving the first physical address from said address translation buffer by using the first virtual address; a second retrieval unit retrieving the second physical address from said address translation buffer by using the second virtual address corresponding one-to-one to the first virtual address; and a prefetch controller entering the first address translation pair of the first virtual address from said address translation table into said cache memory by using the second physical address retrieved by said second retrieval unit.