Patent ID: 9048872
Filing Date: 2015-06-02
Classification: H03M

Abstract:
1. A layered decoding architecture for low density parity check (LDPC) decoding comprising: a variable-to-check message magnitude memory configured to store obtained magnitudes of channel values as initial or later calculated variable-to-check message magnitudes; an A Posteriori Probability (APP) calculation unit electrically coupled to the variable-to-check message magnitude memory and configured to sum a variable-to-check message (Q) and a check-to-variable message (R), APP=Q+R; an APP sign routing network unit electrically connected to the APP calculation unit so as to route updated APP signs to each corresponding variable node; an APP sign memory electrically connected to the APP sign routing network unit so as to retrieve routed and updated APP signs; an APP routing network unit electrically connected to the APP calculation unit so as to route updated APP values to corresponding check nodes; a variable-to-check message calculation unit electrically connected to the APP routing network unit; a variable-to-check message sign memory electrically connected to the APP calculation unit and to the variable-to-check message calculation unit so as to provide corresponding stored variable-to-check message signs and store variable-to-check message signs obtained from the variable-to-check message calculation unit; and a check-node processor electrically connected to the APP calculation unit and to the variable-to-check message calculation unit, wherein the APP calculation unit updates the APP values for all related variable nodes j connected to the check nodes i in the check-node layer being processed after all these variable nodes j are updated according to the following APP equation: where f (i, j) represents the check node which performs the final check-to-variable message delivery together with the variable node j prior to the check node i being processed, Q