Patent ID: 7154808
Filing Date: 2006-12-26
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a plurality of cell blocks; block controllers for activating or precharging word lines of each of the cell blocks according to an external active command and a precharge command; a sense amplifier for sensing a fine voltage shared by bit lines and complementary bit lines of the cell blocks; sense amplifier controllers for activating or precharging the sense amplifier according to the external active command and the precharge command, and outputting a bit line isolation signal that controls the connection between the sense amplifier and the cell block; a block address decoder for decoding external block addresses in normal mode to output a block select signal for selecting one cell block, and outputting a block select signal for selecting even or odd cell blocks according to one of the external block addresses in test mode; and a control block for outputting a bit line isolation control signal for controlling the bit line isolation signal and a sense amplifier enable signal according to a test mode signal, a bank active signal and a sense enable start signal.