Patent ID: 8324019
Filing Date: 2012-12-04
Classification: H01L,H05K

Abstract:
1. A method of minimizing crosstalk in a package of an integrated circuit, comprising the steps of: (A) routing a first signal of a first full-duplex channel between two or more first pads of a plurality of external pads and a first trace layer within said package in a congested area of said package, wherein (i) said external pads are disposed on an integrated circuit side of said package and (ii) said first trace layer is proximate said integrated circuit side; (B) routing said first signal between said first trace layer and a second trace layer within said package in a non-congested area of said package, wherein (i) said second trace layer is proximate a pin side of said package and (ii) said pin side is opposite said integrated circuit side; (C) routing said first signal between said second trace layer and two or more first pins of a plurality of external pins in said non-congested area, wherein said external pins are disposed on said pin side of said package; (D) routing a second signal of said first full-duplex channel between two or more second pads of said external pads and said first trace layer in said congested area of said package; (E) routing said second signal between said first trace layer and said second trace layer in said congested area of said package; and (F) routing said second signal between said second trace layer and two or more second pins of said external pins in said non-congested area, wherein (i) all of said first pins and said second pins are arranged along a first line in a first direction and (ii) said first pins are offset from said second pins by a gap in said first direction of at least two inter-pin spaces.