Patent ID: 7809930
Filing Date: 2010-10-05
Classification: G06F

Abstract:
1. An apparatus for processing data, said apparatus comprising: a physical set of registers; register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set; and mapping control circuitry, coupled to said register renaming circuitry and responsive to a current state of said apparatus, configured to control said register renaming circuitry in respect of a register specifier of said architectural set of register specifiers for an instruction either: (i) to suppress performance of a mapping operation thereby preserving an existing mapping from said register specifier to a register of said physical set of registers; or (ii) to generate a mapping from said register specifier to a register of said physical set of registers, wherein said current state includes whether said register of said physical set of registers mapped by said existing mapping is allocated to storing a value still required for at least some outcomes of one or more other instructions, wherein said mapping control circuitry does not suppress performance of said mapping operation if said register of said physical set of registers mapped by said existing mapping is allocated to storing a value still required for at least some outcomes of one or more other instructions, and said mapping control circuitry suppresses performance of said mapping operation if said register of said physical set of registers mapped by said existing mapping is not allocated to storing a value still required for at least some outcomes of one or more other instructions.