Patent ID: 6339346
Filing Date: 2002-01-15
Classification: H03K

Abstract:
A timing signal generation circuit for generating a timing signal having a predetermined number of critical transitions from a plurality of input timing signals, comprising:a) an input differential buffer for each said critical transition of said timing signal, each said buffer having first and second input terminals and an output terminal, each said buffer further having a first response between its said first input terminal and its said output terminal and a second response between its said second input terminal and its said output terminal, said first response providing a generally lower skew than said second response, and wherein two different ones of said input timing signals are applied to said first and second input terminals of each said buffer to generate a critical edge timing signal at an output terminal of each said buffer indicative of a lowest skew path for a particular one of said predetermined number of critical transitions of said timing signal; and b) a logic circuit coupled to each said buffer through the respective output terminals for each said buffer.