Patent ID: 6169307
Filing Date: 2001-01-02
Classification: G11C,H01L

Abstract:
A nonvolatile semiconductor memory device having an array of memory cells arranged in columns and rows over a well region of a semiconductor substrate, each said memory cell comprising: a memory transistor including: a first gate insulating film, which is formed on the semiconductor substrate and has such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode, which is formed on the first gate insulating film and where charges are storable; an interelectrode insulating film formed on the floating gate electrode; and a control gate electrode formed on the interelectrode insulating film; a select transistor including a second gate insulating film formed on the semiconductor substrate, and a select gate electrode formed on the second gate insulating film, the select transistor being disposed on the semiconductor substrate to be spaced apart from the memory transistor; an intermediate diffusion layer formed in a region of the semiconductor substrate and located between the memory transistor and the select transistor; and source/drain diffusion layers formed in the semiconductor substrate to interpose a region underlying the memory transistor, a region underlying the select transistor and the intermediate diffusion layer therebetween, wherein the source/drain diffusion layers and the intermediate diffusion layer have an equal dopant concentration.