Patent ID: 6651161
Filing Date: 2003-11-18
Classification: G06F

Abstract:
A processor comprising:a store to load forward (STLF) predictor coupled to receive an indication of dispatch of a first load memory operation, wherein said STLF predictor is configured to indicate a dependency of said first load memory operation on a first store memory operation responsive to information stored within said STLF predictor indicating that, during a previous execution, said first store memory operation interfered with said first load memory operation; and an execution pipeline coupled to said STLF predictor, wherein said execution pipeline is configured to inhibit execution of said first load memory operation prior to said first store memory operation responsive to said dependency, and wherein said execution pipeline is configured to detect a lack of said dependency during execution of said first load memory operation, and wherein said execution pipeline is configured to generate an untrain signal responsive to said lack of said dependency; wherein said STLF predictor is coupled to receive said untrain signal and is configured to update said information stored therein to not indicate that said first store memory operation interfered with said first load memory operation during said previous execution; and wherein said execution pipeline includes a store queue, and wherein said execution pipeline is configured to detect said lack of dependency if forwarding of data from said store queue for said first load memory operation does not occur.