Patent ID: 7117295
Filing Date: 2006-10-03
Classification: G11C

Abstract:
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each said memory cell including a storage element holding binary data of n bits based on 2 said threshold levels respectively corresponding to ordered data obtained by rearranging a data set of said binary data of n bits in a procedure equivalent to steps of: a cell selection circuit collectively selecting a plurality of said memory cells from said memory cell array in response to an address signal; a data read/write circuit performing a read/write operation of storage data on said selected plurality of memory cells on the basis of (2 a data input/output circuit for transferring said storage data between the outside of said nonvolatile semiconductor memory device and said memory cells as binary data through k input/output nodes by every k bit (k: natural number), wherein