Patent ID: 6812799
Filing Date: 2004-11-02
Classification: G11C,H03K,H03L

Abstract:
A method for generating a delayed clock signal having a delay relative to an applied clock signal, the method comprising:in response to a start signal, generating a plurality of counting clock signals, one of the counting clock signals designated a reference counting clock signal and the remaining counting clock signals having a delay relative to the reference counting clock signal; in response to the start signal, counting a number of clock cycles of the reference counting clock signal until a transition of the applied clock signal subsequent to the start signal; counting the same number of clock cycles responsive to a transition of the reference counting clock signal subsequent to the transition of the applied clock signal; determining a fine delay that is based on the states of the counting clock signals at the time of the transition of the applied clock signal; and generating the delayed clock signal having a delay relative to the applied clock signal that is equal to the time for counting the number of clock cycles in response to the start signal, for counting the same number of clock cycles responsive to the transition of the reference counting clock signal, and the fine delay.