Patent ID: 7687331
Filing Date: 2010-03-30
Classification: H01L

Abstract:
1. A method of fabricating a semiconductor device, the method comprising: forming a lower transistor on a semiconductor substrate; forming a lower interlevel insulation film on the semiconductor substrate, the lower interlevel insulation film covering the lower transistor; forming an upper transistor on the lower interlevel insulation film over the lower transistor, wherein forming the upper transistor comprises; forming an upper interlevel insulation film on the lower interlevel insulation film, the upper interlevel insulation film covering the upper transistor; forming a first contact plug connected to a source or drain region of the upper transistor and penetrating the upper interlevel insulation film; and forming a second contact plug connected to a drain or source of the lower transistor and penetrating the upper and lower interlevel insulation films and electrically connected to the first contact plug.