Patent ID: 6259290
Filing Date: 2001-07-10
Classification: H03K,H03L

Abstract:
A delay locked loop comprising:a voltage-controlled delay section configured to receive a reference signal and a delay control signal, including,a plurality of voltage controlled delay circuits connected in series, each voltage controlled delay circuit having a delay time, and configured to delay sequentially the reference signal in accordance with the delay control signal, thereby to output a first delayed signal through an (n-1).sup.th delayed signal to an n.sup.th delayed signal that are sequentially delayed in time;a phase comparator configured to receive the first delayed signal and the n-1.sup.th delayed signal, detect a phase difference between the first and n-1.sup.th delayed signals and output an error signal representing the phase difference detected;a filter circuit configured to receive the error signal from the phase comparator, extract a direct-current component from the error signal, and supply the direct-current component, as the delay control signal, to the voltage controlled delay circuit; anda mis-lock detecting circuit configured to generate a plurality of pulse signals, each pulse signal having a width corresponding to a difference in a delay time between adjacent delay signals of the first to n.sup.th delayed signals, to add the pulse signals to generate a sum signal, and to compare the sum signal with the reference signal in terms of a number of pulses contained in the sum signal and reference signal per unit time, thereby detecting a mislocked state of the voltage-controlled delay section.