Patent ID: 8954907
Filing Date: 2015-02-10
Classification: G06F

Abstract:
1. A method of emulating a logic block in an integrated circuit (IC) design, comprising: identifying a plurality of smaller logic elements that are connectable to emulate the logic block, wherein the logic block includes a one time programmable (OTP) block, and wherein the plurality of smaller logic elements cannot form a physical OTP block; flagging each of the plurality of smaller logic elements; connecting the plurality of logic elements to receive input signals and perform logic functions associated with the logic block converting the integrated circuit design from a first data structure relating to a first integrated circuit device to a second data structure relating to a second integrated circuit device; identifying that the logic block is needed in the integrated circuit design but does not exist in physical form among a plurality of logic elements available for the second integrated circuit device, wherein the plurality of smaller logic elements are included in the plurality of logic elements; and placing a boundary around the plurality of smaller logic elements to form an emulated logic block based on the logic block, wherein at least one method operation is executed through a processor.