Patent ID: 7473989
Filing Date: 2009-01-06
Classification: H01L

Abstract:
1. A flip-chip package comprising: a) a substrate having: b) a dummy die being a silicon substrate having no electrically calculating function, connected to the bottom substrate surface and aligned with the substrate opening, and having a redistribution layer, the redistribution layer having a plurality of flip-chip pads and a plurality of connecting pads connected by an integrated circuit trace, the plurality of flip-chip pads and the plurality of connecting pads are located on a top surface of the dummy die below the substrate opening, the plurality of connecting pads of the redistribution layer are electrically connected to the substrate, wherein the dummy die has an exposed surface located on a bottom thereof, the exposed surface having a metal thermal-conducting layer directly formed thereon to substantially cover the exposed surface located on the bottom of the dummy die, the metal thermal conducting layer beina a non-patterned layer, the metal thermal conducting layer being electrically isolated from the redistribution layer; and c) a chip located in the opening and having a plurality of bumps electrically connected to the plurality of flip-chip pads of the redistribution layer.