Patent ID: 7127651
Filing Date: 2006-10-24
Classification: H03H

Abstract:
1. A sampling rate converter comprising: a chain of N cells, N being an integer greater than or equal to unity, each cell having a first, a second, a third and a fourth input of digital values, and having a first, a second, a third and a fourth output of digital values; the first and second outputs of a cell other than a last cell of the chain, and the third and fourth inputs of the said cell being connected respectively to the first and second inputs of a next cell along the chain, and to the third and fourth outputs of the said next cell, the first and second outputs of the last cell of the chain being connected respectively to the third and fourth inputs of the said last cell, the first input of a first cell of the chain for receiving successive digital input sampling values according to an input frequency, the second input of the said first cell for receiving a zero value, the fourth output of the said first cell then delivering successive digital output sampling values according to an output frequency; each cell comprising two multipliers connected by first respective inputs to an element for storing multiplicative coefficients, and connected by respective outputs of the said multipliers to first inputs of two respective adders, outputs of the said adders being linked respectively to the second and fourth outputs of the said cell, and second inputs of the said multipliers being linked respectively to the first and third outputs of the said cell; second inputs of the two multipliers of each cell furthermore linked respectively to the first and third inputs of the said cell by first respective pathways each comprising one and the same specified number of first flip-flops connected in series and oriented towards the corresponding multiplier; and second inputs of the two adders of each cell linked respectively to the second and fourth inputs of the said cell by second respective pathways each comprising second flip-flops connected in series according to the said specified number and oriented towards the corresponding adder.