Patent ID: 7724028
Filing Date: 2010-05-25
Classification: G06F,H03K

Abstract:
1. A method for clock insertion delay compensation, comprising: embedding a hardwired core in a host integrated circuit; operating a first clock domain in the hardwired core with a first frequency that is equal to or greater than a second frequency of operation of a second clock domain in the host integrated circuit but external to the hardwired core; interfacing programmable resources with one or more flip-flops in the second clock domain with the hardwired core; the host integrated circuit including a phase-locked loop (“PLL”) that is located external to the hardwired core, the PLL coupled to receive a reference clock signal and configured to generate a first plurality of clock signals; sending a first clock signal of the first plurality of clock signals associated with the second clock domain to the programmable resources; sending a second clock signal of the first plurality of clock signals associated with the first clock domain to the hardwired core; and making the second clock signal appear to be produced earlier in time than the first clock signal with respect to the hardwired core to compensate for a first clock insertion delay of the hardwired core; wherein the making of the second clock signal to appear to be produced earlier in time includes delaying edges of the first clock signal; and wherein a clock-to-output time associated with the one or more flip-flops at least approximates zero.