Patent ID: 6271093
Filing Date: 2001-08-07
Classification: H01L

Abstract:
In a trench-bounded buried-channel p-MOSFET which exhibits anomalous narrow channel behavior, a method for reducing anomalous narrow channel behavior comprising:providing a substrate having an n-well bounded by a shallow trench isolation;forming a buried p-channel in the n-well by implanting boron ions into the n-well; andperforming a rapid thermal oxidation (RTO) at a temperature from about 1025.degree. C. to about 1075.degree. C. to form a gate oxide on the substrate, wherein the RTO reduces the migration of boron ions in the buried p-channel toward sidewalls of the shallow trench isolation while the gate oxide is formed in order to reduce anomalous narrow channel behavior so that the gate threshold voltage remains nearly constant as device width is reduced below 2 um without the need of performing an anneal after formation of the n-well and before formation of the gate oxide.