Patent ID: 9048103
Filing Date: 2015-06-02
Classification: H01L

Abstract:
1. A method for producing a semiconductor device which includes: a semiconductor substrate, a hetero semiconductor area configured to contact a first main face of the semiconductor substrate and different from the semiconductor substrate in band gap, a gate electrode configured to contact, via a gate insulating film, a part of a junction part between the hetero semiconductor area and the semiconductor substrate, a source electrode configured to connect to the hetero semiconductor area, a drain electrode configured to make an ohmic connection with the semiconductor substrate, and a source drawing area formed on a shallow area of the surface of the hetero semiconductor area to exhibit a first electrical conductivity type different from a second electrical conductivity type of the hetero semiconductor area and to have a surface contact the source electrode, the method comprising the following sequential operations: forming the hetero semiconductor area on the first main face of the semiconductor substrate; forming the source drawing area formed on the shallow area of the surface of the hetero semiconductor area; etching a part of the hetero semiconductor area and the source drawing area; forming the gate insulating film on the hetero semiconductor area and the source drawing area that are etched and the semiconductor substrate that is exposed after etching; and nitriding the gate insulating film after having formed the gate insulating film, so as to decrease both an interface level of an interface defined between the gate insulating film and the semiconductor substrate and an interface level of an interface defined between the gate insulating film and the hetero semiconductor area with the source drawing area, while decreasing an interface level of an interface, which connects both the interface between the gate insulating film and the semiconductor substrate and the interface between the gate insulating film and the hetero semiconductor area with the source drawing area, defined between the semiconductor substrate and the hetero semiconductor area.