Patent ID: 8426922
Filing Date: 2013-04-23
Classification: H01L

Abstract:
1. A CMOS structure, comprising a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed next to the P-well region and the NMOS portion respectively, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region, the pad structure further comprising: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone interfaces the N-well region with P-type dopants, the contact zone includes an inner dopant area formed with N-type dopants and an outer dopant area formed with the P-type dopants.