Patent ID: 6381704
Filing Date: 2002-04-30
Classification: G01R

Abstract:
A method for operating an integrated circuit, wherein the integrated circuit has a plurality of latches which operate in response to set of non-overlapping clock signals, the method comprising:selecting a first non-overlap time by setting a control signal to a first value; forming a first clock signal of the set of non-overlapping clock signals internally to the integrated circuit in response to an input clock signal, the first clock signal having a latching edge; forming a second clock signal of the set of non-overlapping clock signals internally to the integrated circuit in response to the input clock signal, the second clock having a driving edge, wherein the driving edge is delayed by the first non-overlap time after the latching edge; latching a data value in a first latch of the plurality of latches in response to the latching edge of the first clock signal to form a latched data value; and driving the latched data value from the first latch in response to the driving edge of the second clock signal.