Patent ID: 6044457
Filing Date: 2000-03-28
Classification: G06F

Abstract:
A method of operating a state machine controller which can produce a result per clock pulse, schedule new data for processing before completion of processing of previous data to provide a continuous and uninterrupted flow of data in a data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, comprising:a. providing a repository of data sets;b. providing a process list of parallel sets of bits in a data pipeline, wherein each parallel set of bits indicates which data sets to process, and each bit represents whether or not to process a particular data set;c. loading a set of bits into a register and advancing the data pipeline to the next parallel set of bits;d. providing a wait/no wait input signal which indicates whether or not the data outputted by the state machine controller can proceed to the next process and an empty signal which indicates when there are no more data sets to be processed; ande. detecting when there are only one or no bits left to be processed in the set of bits currently stored in the register, and when the wait/no wait signal indicates wait, causing the same set of bits to remain in the register, and when the wait/no wait signal indicates no wait and the empty signal indicates there are more data sets to process, then entering another parallel set of bits from the process list and advancing the data pipeline to the next parallel set of bits.