Patent ID: 6975976
Filing Date: 2005-12-13
Classification: G01R,G06F

Abstract:
1. A method of verification for a design, comprising: providing a description of said design; specifying correctness criteria for said design, wherein said correctness criteria are expressed as one or more correctness properties; abstracting said design description to provide an abstract model of said design; generating a witness graph for said one or more correctness properties based on a deterministic analysis of said abstract model where the deterministic analysis serves to modify the abstract model by iteratively refining and pruning states and transitions which capture all witnesses or counterexamples demonstrating said one or more correctness properties; and when the deterministic analysis does not produce a conclusive result, generating a testbench automatically from said witness graph for performing simulation with said testbench, where the testbench generates simulation test vectors for the simulation that target states and transitions in the witness graph when searching for a concrete witness or counterexample with respect to said correctness criteria.