Patent ID: 8823152
Filing Date: 2014-09-02
Classification: H01L

Abstract:
1. A semiconductor package comprising: a generally planar die pad defining opposed top and bottom surfaces and multiple peripheral edge segments; a plurality of first leads which are segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a plurality of second leads which are segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a semiconductor die attached to the die pad and to portions of the first leads, the semiconductor die covering the entirety of the top surface of the die pad and being electrically connected to at least one of each of the first and second leads; and a package body defining a bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that at least portions of the bottom surface of the die pad and portions of the first leads are exposed in the bottom surface of the package body, and portions of at least some of the second leads protrude from at least one of the side surfaces of the package body.