Patent ID: 8318574
Filing Date: 2012-11-27
Classification: H01L

Abstract:
1. A method comprising: providing a silicon-on-insulator substrate comprised of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer, where the silicon-on-insulator substrate includes a trench that extends through the top silicon layer and at least partially into the insulation layer, where the trench includes a trench wall and exposes a contact of a capacitor disposed at least partially in the insulation layer; forming at least one spacer in the trench against the trench wall; removing a portion of the at least one spacer to expose a portion of the insulation layer in the trench, where the removed portion of the at least one spacer is less than all of the at least one spacer; forming at least one device disposed at least partially on the top silicon layer, where forming the at least one device comprises doping a portion of the top silicon layer; performing an etch to remove a portion of the insulation layer and create an undercut in the insulation layer, where the undercut underlies the doped portion of the top silicon layer and abuts the contact of the capacitor; and epitaxially depositing first and second materials, where the first epitaxially-deposited material at least partially fills the undercut and electrically couples the contact of the capacitor to the doped portion of the top silicon layer, where the second epitaxially-deposited material at least partially overlies the top silicon layer and at least partially overlies the first epitaxially-deposited material.