Patent ID: 8035231
Filing Date: 2011-10-11
Classification: H01L,H05K,Y10T

Abstract:
1. A semiconductor device comprising: a first interconnect layer including first interconnects; a semiconductor chip mounted on a first surface of said first interconnect layer; a second interconnect layer provided on a second surface of said first interconnect layer opposite to said first surface; plural first conductive plugs provided in said first interconnect layer, said first conductive plugs extending from respective ones of said first interconnects to said first surface of said first interconnect layer; and plural second conductive plugs provided in said second interconnect layer, said second conductive plugs extending from respective ones of said first interconnects to a surface of said second interconnect layer opposite to said first interconnect layer; wherein end faces of said first conductive plugs facing said second interconnect layer are smaller in area than the opposite end faces of said first conductive plugs; wherein end faces of said second conductive plugs facing said first interconnect layer are smaller in area than the opposite end faces of said second conductive plugs; and wherein a resin constituting said first interconnect layer has a higher thermal decomposition temperature than a resin constituting said second interconnect layer; and wherein a minimum interval between said first conductive plugs is narrower than a minimum interval between said second conductive plugs.