Patent ID: 6512394
Filing Date: 2003-01-28
Classification: G05F,H03K

Abstract:
An integrated circuit logic device having supply and reference voltage lines thereof, said device comprising:an internal supply voltage node selectively couplable to said supply voltage line in response to an input signal supplied to a gate terminal of a first MOS transistor, said first MOS transistor having a back gate coupled to said supply voltage line; an internal reference voltage node selectively couplable to said reference voltage line in response to a complement of said input signal supplied to a gate terminal of a second MOS transistor, said second MOS transistor having a back gate coupled to said reference voltage line; a third MOS transistor in parallel with said first MOS transistor between said supply voltage line and said internal supply voltage node, said third MOS transistor having a gate terminal coupled to said supply voltage line and a back gate coupled to said internal supply voltage node; a fourth MOS transistor in parallel with said second MOS transistor between said reference voltage line and said internal reference voltage node, said fourth MOS transistor having a gate terminal coupled to said reference voltage line and a back gate coupled to said internal reference voltage node; and a logic circuit comprising a plurality of logic gates coupled between said internal supply voltage node and said internal reference voltage node.