Patent ID: 6600337
Filing Date: 2003-07-29
Classification: G11C,H03K

Abstract:
A programmable logic device comprising:a first plurality of logic array blocks arranged contiguously; a plurality of segmentation buffers arranged contiguously and along a side of the first plurality of logic array blocks, a second plurality of logic array blocks arranged contiguously and along a side of the plurality of segmentation buffers away from the first plurality of logic array blocks; a plurality of stitch buffers arranged contiguously and along a side of the second plurality of logic array blocks away from the plurality of segmentation buffers; a third plurality of logic array blocks arranged contiguously and along a side of the plurality of stitch buffers away from the second plurality of logic array blocks; a fourth plurality of logic array blocks arranged contiguously and along a side of the third plurality of logic gates away from the plurality of stitch buffers; a first plurality of interconnect lines programmably coupled to the first plurality of logic array blocks and coupled to the plurality of segmentation buffers; a second plurality of interconnect lines programmably coupled to the second plurality of logic array blocks, and coupled to the plurality of segmentation buffers and to the plurality of stitch buffers; and a third plurality of interconnect lines programmably coupled to the third plurality of logic array blocks and the fourth plurality of logic array blocks, and coupled to the plurality of stitch buffers, wherein the plurality of segmentation buffers are capable of being configured to drive signals from the first plurality of interconnect lines to the second plurality of interconnect lines, or to drive signals from the second plurality of interconnect lines to the first plurality of interconnect lines, or to provide an open circuit between the first plurality of interconnect lines and the second plurality of interconnect lines.