Patent ID: 6675252
Filing Date: 2004-01-06
Classification: G06F

Abstract:
A circuit arrangement configured to communicate with an Accelerated Graphics Port (AGP)-compatible device over an AGP bus, the circuit arrangement comprising:(a) a first circuit block including a first logic circuit configured to handle an address phase of a multiplied AGP fast write transaction using a Peripheral Component Interconnect (PCI)-type signal protocol, the first logic circuit including an address path configured to store AGP fast write address information for transmission over the AGP bus; (b) a second circuit block including a second logic circuit, the second logic circuit configured to handle a data phase of the multiplied AGP fast write transaction using an AGP-type signal protocol, the second logic circuit including a multiplied data path configured to store multiplied AGP fast write data information for transmission over the AGP bus; and (c) a control signal path coupled between the first and second logic circuits to permit the first logic circuit to initiate the data phase of the multiplied AGP fast write transaction in the second logic circuit after initiating the address phase in the first logic circuit.