Patent ID: 8917133
Filing Date: 2014-12-23
Classification: G06F,H03K,H04L

Abstract:
1. A clock generation method, comprising the steps of: a pulse recognition step, where an input pulse signal is first filtered to remove a shorter signal; then, a width digitization calculation is conducted on the remaining pulse signal; subsequently, based on the regularity of the input pulse signal and the result of the width digitization calculation, a signal conforming to the regularity and having identical width is recorded and a period of the recorded signal is determined; and the value of the period is delivered to a gain module; a step for verifying the input value to digital-to-analog (D/A) converter, where two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator; the gain module then, based on a proportional value between the oscillator's output value and the input values, determines a desired input value from the gain module to the D/A converter based on the proportional value and a multiple of the period; a pulse generation step, where the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock; and a power noise compensation step, where power noise is detected, the detected power noise is converted into a current signal or a voltage signal, and is delivered to the oscillator for the oscillator to adjust output accordingly.