Patent ID: 8264058
Filing Date: 2012-09-11
Classification: H01L

Abstract:
1. A JFET device, comprising: a gate contact, a drain contact, and a source contact; a first gate region of semiconductor material, said first gate region having a top surface adjacent said gate contact and one or more interior surfaces; a second gate region of semiconductor material surrounding each of the one or more interior surfaces of said first gate region, said first gate region and said second gate region forming a first p-n junction between said first gate region and said second gate region such that a single p-n junction is formed between said gate contact and said second gate region; a channel region of semiconductor material adjacent said source contact, said channel region and said second gate region forming a second p-n junction between said second gate region and said channel region, the first p-n junction and the second p-n junction being located between said gate contact and the channel region; wherein said first p-n junction has a depletion width that is adjustable based at least in part on a gate voltage applied to said gate contact, said second p-n junction has a depletion width that is adjustable based at least in part on the gate voltage, wherein when the gate voltage is greater than a threshold voltage for the first p-n junction, the depletion width of said second p-n junction decreases as the depletion width of said first p-n junction increases.