Patent ID: 6455366
Filing Date: 2002-09-24
Classification: H01L

Abstract:
A method of forming a junction region in a semiconductor device, comprising the steps of:forming gate electrodes at a cell area and a peripheral circuit area, respectively, which are defined in a semiconductor substrate; forming gate spacers at side walls of each of the gate electrodes and forming a nitride film only at said peripheral circuit area; selectively forming a doped epitaxial silicon layer on said semiconductor substrate in the cell area; performing source/drain implantation process to the peripheral circuit area covered with the nitride film and then performing thermal process for activating ion implanted dopants to forming a source/drain junction only at the peripheral circuit area, so that, during the thermal processing process, the dopants within said doped epitaxial silicon layer are diffused to form an elevated source/drain junction at the cell area; and removing any nitride film remaining at said peripheral circuit area to form an interlayer insulation film.