Patent ID: 6094462
Filing Date: 2000-07-25
Classification: G11B

Abstract:
A data demodulator comprising:M input ports (where M is a positive integer and M.gtoreq.2) for inputting n-tuple speed data (where n is a positive integer), which are sent out in a digital form from an information supply source sequentially;M serial-in/parallel-out shift registers for inputting the n-tuple speed data in series in synchronism with an n-tuple speed sampling clock sequentially via the M input ports to store therein, and then outputting the n-tuple speed data in parallel every period of an M.multidot.n-tuple speed frame clock;a parallel-in/serial-out shift register capable of storing data from the whole of the M serial-in/parallel-out shift registers, for inputting the n-tuple speed data together in parallel which are output from the M serial-in/parallel-out shift registers respectively, and then demodulating the n-tuple speed data into M.multidot.n-tuple speed data in synchronism with an M.multidot.n-tuple speed sampling clock and outputting the M.multidot.n-tuple speed data in serial; andan output port for outputting the M.multidot.n-tuple speed data which are output from the parallel-in/serial-out shift register;wherein a period of time which is required by the M serial-in/parallel-out shift registers from a start of inputting the n-tuple speed data to an end thereof is set within one period of the M.multidot.n-tuple speed frame clock.