Patent ID: 6744838
Filing Date: 2004-06-01
Classification: H03D,H03L

Abstract:
A detector for indicating when an oscillating signal output by a phase-locked-loop (PLL) is locked to a reference signal input to the PLL, the PLL having a phase frequency detector (PFD) that outputs an up signal and a down signal, the up and down signals having pulse widths, the pulse widths being equal when the oscillating signal is locked to the reference signal, the detector comprising:a dropped lock detection circuit that indicates when the up and down signals output by the PFD are not equivalent; a first pulse latch that latches indications during a first portion of each of a number of time periods that the up and down signals are not equivalent; a second pulse latch that latches indications during a second portion of each of the number of time periods that the up and down signals are not equivalent; and an output stage that outputs a lock status signal that indicates whether indications that the up and down signals are not equivalent have been captured by the first pulse latch or the second pulse latch.