Patent ID: 8650230
Filing Date: 2014-02-11
Classification: G06F

Abstract:
1. An integrated circuit comprising: a plurality of regions of logic array block circuitry, each of which includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal, and (2) a redundant form carry bit signal, and each of the subregions including ripple carry adder circuitry for adding (a) a ripple carry bit signal output by a less arithmetically significant ripple carry adder circuitry, (b) the redundant form sum bit signal produced by said each subregion, and (c) the redundant form carry bit signal produced by a less arithmetically significant subregion; and each of the regions including (i) a first register for registering a ripple carry bit signal selected from among the ripple carry bit signals of said each region, and (ii) a second register for registering a redundant form carry bit signal selected from among the redundant form carry bit signals of said each region.