Patent ID: 6046610
Filing Date: 2000-04-04
Classification: H03K

Abstract:
A differential receiver cell circuit for a CMOS chip comprising:a differential receiver cell having a bias switch circuit between a voltage source and ground comprising a first PFET (T115) having its source connected to the voltage source, its drain connected to a self biasing network composed of a second PFET (T106) and a first NFET (T107) as input transistors to said bias switch circuit and having an output of said first PFET (T115) connected to control a current controlling device of said receiver cell circuit provided by a second NFET (T118) whose drain is connected to a common node (NA) and whose source is coupled to ground;said differential receiver cell further having a first data input along a first input line to the gate of a first input NFET (T117) whose source is connected to said common node (NA), and said differential receiver cell also has a second data input provided by a second input line to the gate of a second input NFET (T116) whose source is also connected to said common node (NA), said common node (NA) being connected to the drain of said current controlling device provided by said second NFET (T118) whose source is connected to ground;and wherein said differential receiver cell also has a first current mirror device PFET (T114) and a second current mirror device PFET (T113) connected to a second common node (NB) which is connected to said self biasing network, and having the drain of said first input NFET (T117) connected to the drain of said first current mirror device PFET (T114) at a self biasing network out node (AAA), and the drain of the second input NFET (T116) is connected to the drain of said second current mirror device PFET (T113) at an output node (000); andwherein voltage signals present at both the first data input and second data input are complementary so that if a signal present on said first input line is a high level signal then the signal present on said second input line is a low level signal, and when a re-enable signal is a high level logical signal equivalent to the output node (000) source voltage and a complementary re-enable input pin is at a low level logical signal equivalent to the output node (000) voltage at ground then the input NFET AND PFET transistors of said self biasing network are turned ON and the first PFET (T115) of said bias switch circuit is turned OFF to bias the differential receiver cell circuit at the first and second input lines.