Patent ID: 6385122
Filing Date: 2002-05-07
Classification: G11C

Abstract:
A memory circuit, comprising:a plurality of memory cells organized into an array of N rows and N columns, said array having a first diagonal portion and a second diagonal portion; a control logic block operable with an access control signal to effectuate one of a row access operation and a column access operation; each memory cell having first and second read ports and first and second write ports, said first read and write ports being operable with respect to said row access operation and said second read and write ports being operable with respect to said column access operation, wherein said first and second read ports are tied together and said first and second write ports are tied together for each diagonally placed memory cell in one of said first and second diagonal portions of said array; a decoder circuit block for generating at least one a horizontal wordline select signal and a vertical wordline select signal responsive to a plurality of address signals and a control signal provided by said control logic block, said horizontal wordline select signal for selecting a particular horizontal word with respect to said row access operation and said vertical wordline select signal for selecting a particular vertical word of said array for said column access operation; and an input/output (I/O) block common for said row and column access operations for effectuating data input for a write operation and data output for a read operation.