Patent ID: 7807480
Filing Date: 2010-10-05
Classification: G01R,G11C,H01L

Abstract:
1. A method of fabricating an integrated circuit chip, the method comprising: forming a first active region on a portion of a test wafer using an integrated circuit fabrication line; forming a second active region substantially parallel to the first active region on the portion of the test wafer; forming a third active region substantially parallel to the first and second active regions on the portion of the test wafer; forming a fourth active region formed between the first and second active regions on the portion of the test wafer; forming a fifth active region formed between the second and third active regions on the portion of the test wafer, wherein the fourth and fifth active regions are formed adjacent to opposite end portions of the second active region, and wherein the fourth and fifth active regions are formed substantially perpendicular to the second active region; examining the portion of the test wafer to detect and localize defects; adjusting the integrated circuit fabrication line based on the examination of the portion of the test wafer; fabricating integrated circuit dice on a production wafer using the adjusted integrated circuit fabrication line; dicing the integrated circuit dice on the production wafer into integrated circuit chips; and packaging the integrated circuit chips; the method further including: forming a first selection line segment disposed over a portion of the fourth active region; forming a second selection line segment disposed over a portion of the fifth active region, wherein the first and second selection line segments run substantially parallel to the first, second, and third active regions; forming a first sense line segment disposed over first end portions of the first, second, and third active regions; forming a second sense line segment dispose over second end portions of the first, second, and third active regions, wherein the first and second end portions are opposite ends of the first, second, and third active regions, wherein the first and second sense line segments run substantially perpendicular to the first and second selection line segments; and forming a bus line segment disposed over middle portions of the first, second, and third active regions, wherein the bus line segment runs between the first and second sense line segments; wherein: a first transistor is defined by the first active region, the second active region the fourth active region, the first selection line segment, portions of the first and second sense lines, and a portion of the bus line segment; and a second transistor is defined by the second active region, the third active region, the fifth active region, the second selection line segment, portions of the first and second sense lines, and a portion of the bus line segment.