Patent ID: 6243283
Filing Date: 2001-06-05
Classification: G11C,H01L

Abstract:
A low latency data storage and acquisition system for computers comprising:one or more DRAM devices for storing data and having first data access time;one or more SRAM devices directly connected to a DRAM device in a stacked relation for storing data, said SRAM device having second data access time faster than said first data access time;a shared address bus for carrying address signals to both said DRAM and SRAM devices for accessing data therefrom;an output data bus associated with each said SRAM and DRAM device; and,control means for simultaneously activating said DRAM and said SRAM devices for delivering data to a respective output data bus, said SRAM delivering one or more stored data bytes according to an address signal in a first time interval, said DRAM device delivering one or more stored data bytes according to said address signal in a second time interval following said first time interval, and in succeeding second time intervals thereafter.