Patent ID: 6480982
Filing Date: 2002-11-12
Classification: G06F,G11C

Abstract:
A method of reducing errors in a random access memory, said random access memory comprising an array of DRAMs arranged in at least one chip row, wherein said method is at least partially carried out by executing central processor unit millicode instructions, further wherein data is fetched from said DRAMS in said chip row in parallel and each said DRAM in said chip row corresponds to a different bit position in said fetched data, comprising:scrubbing each storage location in said random access memory during a first mode of operation, said scrubbing being performed on a chip row basis, wherein said first mode includes counting for each bit position the single bit errors corrected by said first mode scrubbing operation, ignoring multiple bit errors detected during said first mode scrubbing operation, sparing a DRAM corresponding to a bit position for which the error count exceeds a predetermined threshold at the end of said first mode of operation; and scrubbing the storage locations in said random access memory during a second mode of operation in response to said error counter exceeding said predetermined threshold during said first mode of operation, and storing a SPUE tag to storage locations detected as containing multiple bit errors during said second mode scrubbing.