Patent ID: 9188822
Filing Date: 2015-11-17
Classification: G02F,G09G

Abstract:
1. A chip on glass type liquid crystal display device, comprising: a first substrate including a display area and a non-display area surrounding the display area, the non-display area including first, second, third, and fourth non-display areas; gate and data lines in the display area on the first substrate and crossing each other to define pixel regions; switching thin film transistor at each crossing portion of the gate and data lines and connected to the gate and data lines; a pixel electrode in each pixel region and connected to the thin film transistor; first testing thin film transistors in the second non-display area and connected to the data lines, the first testing thin film transistors being spaced apart from each other with a constant interval therebetween; first, second, and third data testing lines connected to one ends of the data lines through the first testing thin film transistors, the first data testing line being connected to (3n-2) first, second, and third data testing pads respectively connected to the first, second, and third data testing lines; data link lines in the first non-display area and directly respectively connected to the other ends of the data lines in the display area; second testing thin film transistors in the first non-display area and connected to the data link lines; gate link lines connected to the gate lines; third testing thin film transistors connected to the gate link lines; gate testing lines connected to the gate lines through the third testing thin film transistors; gate testing pads connected to the gate testing lines; a common testing line and a common pad in the non-display area; a second substrate spaced apart from the first substrate; a color filter layer and a common electrode sequentially formed on an inner surface of the second substrate, the common electrode being connected to the common testing line; a liquid crystal layer between the first and second substrates; fourth testing thin film transistors connected to the gate link lines, wherein the gate link lines include first, second, third, and fourth gate link lines, wherein the third testing thin film transistors are connected to the first and second gate link lines, wherein the fourth testing thin film transistors are connected to the third and fourth gate link lines, wherein a driving IC is attached in the first non-display area, wherein a single data testing line is connected to source electrodes of all the second testing thin film transistors, wherein a single data enable line is connected to gate electrodes of all the second testing thin film transistors, wherein the display area has a rectangular shape consisting of first, second, third, and fourth sides with the first and second sides being opposite to each other and with the third and fourth sides being opposite to each other, and the first, second, third, and fourth non-display areas correspond to the first, second, third, and fourth sides, respectively, wherein the second testing thin film transistors and the driving IC are disposed in the first non-display area, wherein the data lines extend in a direction from the first non-display area to the second non-display area, wherein the other ends of the data lines are disposed between the one ends of the data lines and the driver IC, wherein the first testing thin film transistors are at an opposite end of the display area from the second, third, and fourth testing thin film transistors, and wherein each data line is respectively connected to one of the first testing thin film transistors at one end and to one of the second testing thin film transistors at an opposite end.