Patent ID: 8443322
Filing Date: 2013-05-14
Classification: G06F

Abstract:
1. A method for using layout enumeration to facilitate integrated circuit development, the method comprising: defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer or layers of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating by generating, according to the initial set of design ground rules, only all possible legal design layouts allowed by the initial set of design ground rules for a given layer of the integrated circuit device in the initial region of interest; running, using a computer, a manufacturing simulation of the resulting enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, performing a triage assessment by further determining whether the one or more failing layouts are removable by changes in technology parameters and/or updated ground rules; and upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment operations.