Patent ID: 6160729
Filing Date: 2000-12-12
Classification: G11C

Abstract:
An associative memory, comprising:a plurality of identical memory cells;a respective memory cell being formed only of a series circuit of a regular, first PMOS transistor and of a second PMOS transistor with a floating gate, a first terminal of the first PMOS transistor being connected to a supply voltage, and, for associative storing, a second terminal of the first PMOS transistor being connected via the second PMOS transistor to a respective terminal for a bit signal of an output vector and, for reading, being connected to a current evaluator; andin a respective memory cell, a terminal for a bit signal of a respective input vector being connected to a gate of the respective, first PMOS transistor and a terminal for a learning signal being connected to a gate of the second PMOS transistor.