Patent ID: 7741721
Filing Date: 2010-06-22
Classification: H01L

Abstract:
1. A semiconductor structure comprising: a shallow trench isolation comprising a dielectric material and located in a semiconductor substrate; a plurality of parallel conductive lines having a width of a first sublithographic dimension and located on said semiconductor substrate, wherein each of said plurality of conductive lines has a pair of sidewall surfaces that are parallel to a first vertical plane that is orthogonal to a top surface of said semiconductor substrate, wherein each adjacent pair of said parallel conductive lines is separated by a second sublithographic dimension, and wherein multiple edges of said plurality of parallel conductive lines are located substantially on a second vertical plane that is orthogonal to said top surface of said semiconductor substrate and located at a non-orthogonal angle from said first vertical plane, each of said multiple edges being directly adjoined to one of said pairs of sidewall surfaces; a first electrode contacting all of said plurality of parallel conductive lines; and a second electrode contacting only one of said plurality of parallel conductive lines.