Patent ID: 6171909
Filing Date: 2001-01-09
Classification: H01L

Abstract:
A method for forming a stacked gate, the method comprising:sequentially forming a first dielectric layer, a conductive layer and a silicon nitride layer over a substrate;patterning the silicon nitride layer, the conductive layer, the first dielectric layer and the substrate until forming a plurality of trenches in the substrate;forming an insulating layer over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer;forming a conductive spacer on sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and the conductive layer together serve as a first gate conductive layer;removing the silicon nitride layer;sequentially forming a second dielectric layer and a second gate conductive layer over the substrate; andpatterning the second gate conductive layer, the second dielectric layer and the first gate conductive layer to form a control gate, a patterned dielectric layer and a floating gate, respectively.