Patent ID: 6051505
Filing Date: 2000-04-18
Classification: H01L

Abstract:
A plasma etch method for forming a via through a silicon containing dielectric layer within a microelectronics fabrication comprising:providing a plasma reactor chamber;positioning within the plasma reactor chamber a microelectronics fabrication, the microelectronics fabrication comprising:a substrate employed within the microelectronics fabrication;a metal layer formed over the substrate;a silicon containing dielectric layer formed upon the metal layer; anda patterned photoresist layer formed upon the silicon containing dielectric layer;etching through use of a plasma etch method at a first plasma reactor chamber pressure while employing the patterned photoresist layer as a photoresist etch mask layer the silicon containing dielectric layer to form a via through the silicon containing dielectric layer while reaching and etching the metal layer to form an etched metal layer, the plasma etch method employing an etchant gas composition comprising a fluorine containing etchant gas; andpumping the plasma reactor chamber to a second plasma reactor chamber pressure lower than the first plasma reactor chamber pressure for a time sufficient to attenuate formation of a metal-fluoropolymer residue layer upon the etched metal layer.