Patent ID: 6848005
Filing Date: 2005-01-25
Classification: H04L

Abstract:
1. A computer system, comprising: a processor, and a memory coupled to said processor, said memory comprising one or more sequences of instructions for managing a plurality of data communication connections having differing data communication rates, wherein execution of the one or more sequences of instructions by said processor causes the processor to perform the steps of: A) assigning said data communication connections to a plurality of buckets that have a circular order; B) establishing a bucket of said plurality of buckets as a current bucket and establishing another bucket as a fast bucket; C) establishing a connection assigned to said current bucket as a current connection; D) communicating data over said current connection; E) in response to communicating data over said current connection, re-assigning said current connection to a different bucket of said plurality of buckets based upon where said current bucket resides in said circular order and a bandwidth estimation of said current connection; F) repeating steps (C), (D) and (E) for each connection assigned to said current bucket; G) establishing a next bucket as a new current bucket, wherein said next bucket follows said current bucket in said circular order; waiting until the earlier of (1) when any connection in the fast bucket is ready for communication or (2) when a pre-defined period of time elapses; and H) repeating step (F) and (G) for each bucket of said plurality of buckets.