Patent ID: 7465989
Filing Date: 2008-12-16
Classification: H01L

Abstract:
1. A high withstand voltage trenched MOS transistor, comprising: a trench formed on a semiconductor substrate and a gate oxidized film formed in a surface portion of the trench; a gate electrode formed on the gate oxidized film in the trench; first electric field relaxation layers one of which is formed in a surface portion of the semiconductor substrate adjacent to one side of the gate electrode, and another one of which is formed in a surface portion of the semiconductor substrate adjacent to another side of the gate electrode; second electric field relaxation layers each of which is formed along a wall of the trench in a region having the gate electrode, and is connected to one of the first electric field relaxation layers; an insulation film covering the gate electrode; and a source region and a drain region one of which is formed so as to be included in a surface portion of one of the first electric field relaxation layers provided on the side of the gate electrode, and another one of which is formed so as to be included in a surface portion of another one of the first electric field relaxation layers provided on the other side of the gate electrode.