Patent ID: 6228723
Filing Date: 2001-05-08
Classification: B82Y,H01L

Abstract:
A method for forming a split gate non-volatile memory cell in a semiconductor substrate, said semiconductor substrate having a boundary region and a cell array region adjacent to said boundary region, comprising:forming a field oxide layer supported by said semiconductor substrate;forming a gate oxide layer adjacent to said field oxide layer and supported by said semiconductor substrate;forming a first conductive layer on said field oxide layer and said gate oxide layer;forming an oxide layer on said first conductive layer;patterning said first conductive layer and said oxide layer to create a terminal edge portion on said field oxide layer overlying said boundary region;forming a second conductive layer over said semiconductor substrate;forming a first masking pattern on a selected portion of said second conductive layer, wherein said first masking pattern does not cover a portion of said second conductive layer overlying said terminal edge portion;etching and removing portions of the said second conductive layer, said oxide layer and said first conductive layer not positioned under said first masking pattern to from said split gate in said cell array region;removing said first masking pattern;forming a second masking pattern covering said split gate; andetching and removing any portion of said second conductive layer remaining in said boundary region.