Patent ID: 7542535
Filing Date: 2009-06-02
Classification: H03L,H04L

Abstract:
1. An apparatus comprising: a counter unit including a data port, a clock port and a plurality of counters, the data port to receive a serial data signal and the clock port to receive a clock signal, the serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, the plurality of counters including a first counter operable to accumulate a first count that represents a length of a first sequence of data cells in the preamble, a second counter to accumulate a second count that represents a length of a second sequence of data cells in the preamble, a third counter to accumulate a third count that represents a length of a third sequence of data cells in the preamble, and a fourth counter that represents a length of a fourth sequence of data cells in the preamble; a state machine coupled to the plurality of counters, the state machine to identify which one of the plurality of counters is to be incremented in order to accumulate a count between transitions in the preamble in response to the clock signal; and a logic unit to determine the embedded clock signal frequency by determining that the first sequence of data cells, the second sequence of data cells, the third sequence of data cells, and the fourth sequence of data cells are indicative of the preamble, to determine a preamble count including a sum of count values of the accumulated first count, the accumulated second count, the accumulated third count, and the accumulated fourth count, and to determine the embedded clock signal frequency based on the preamble count.