Patent ID: 6297672
Filing Date: 2001-10-02
Classification: H03K,H04L

Abstract:
An integrated circuit of CMOS structure comprising:a signal transmission path having an impedance in the integrated circuit;a current-input type gate having an input terminal coupled to said signal transmission path and receiving an input current via said input terminal, said current-input type gate having a low input impedance relative to said impedance of said signal transmission path and generating an output voltage depending upon the magnitude of the input current;a first current mirror circuit constituted by p-channel MOS.FETs, said first current mirror circuit connecting one of terminals which are to be connected to power supply terminals, of said current-input type gate to a positive power supply terminal; anda second current mirror circuit constituted by n-channel MOS.FETs, said second current mirror circuit connecting the other of terminals which are to be connected to power supply terminals, of said current-input type gate to a negative power supply terminal, andwherein said current-input type gate includes an inverter of CMOS structure the output end of which is connected to said input terminal, one of terminals of said inverter to be connected to power supply terminals is connected to said positive power supply terminal via said first current mirror circuit, the other of terminals of said inverter to be connected to power supply terminals is connected to said negative power supply terminal via said second current mirror circuit, and a mid point potential between the positive and negative power supply voltages is applied to the input end of said inverter.