Patent ID: 9159633
Filing Date: 2015-10-13
Classification: G03F,H01L

Abstract:
1. A method for forming an integrated circuit having a test macro using a multiple patterning lithography process, the method comprising: forming an active area of the test macro of the integrated circuit; forming a first gate region in the active area during a first step of the multiple patterning lithography process; forming a first source/drain region in the active area during a second step of the multiple patterning lithography process; forming a second source/drain region in the active area during a third step of the multiple patterning lithography process; forming a third source/drain region in the active area during a fourth step of the multiple patterning lithography process; forming a first contact configured to connect to the first gate region, a second contact configured to connect to the first source/drain region, a third contact configured to connect to the second source/drain region, and a fourth contact configured to connect to the third source/drain region; and determining if an overlay shift occurred during the multiple patterning lithography process by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.