Patent ID: 7925944
Filing Date: 2011-04-12
Classification: G11C

Abstract:
1. A semiconductor device comprising: a N-line M-stage shift register circuit including shift registers of M-stages in N lines in parallel to each other (where M and N each are an integer equal to or larger than 2), a plurality of sets of shift registers in a plurality of lines out of the N lines being formed in the N-line M-stage shift register circuit, wherein each of the sets includes: each of the sets of shift registers to which the common test pattern is input does not include shift registers in lines adjacent to each other, and one of two test patterns is input to a set of shift registers in given lines at least two lines apart from each other while the other test pattern is input to another set of shift registers in other lines at least two lines apart from each other, one of the other lines being adjacent to one of the given lines, and the two test patterns having phases opposite to each other in an arbitrary period.