Patent ID: 6482723
Filing Date: 2002-11-19
Classification: H01L

Abstract:
A method for forming a floating gate, the method comprising the steps of:forming a number of trenches in a semiconductor material of a first conductivity type, the semiconductor material having a top surface, the step including: forming a layer of pad oxide on the semiconductor material, the layer of pad oxide having a top surface, forming a layer of nitride on the layer of pad oxide, the layer of nitride having a top surface, etching the layer of nitride to form a number of exposed regions on the top surface of the layer of pad oxide, and etching the exposed regions of the layer of pad oxide and the semiconductor material to form the number of trenches in the semiconductor material; forming a layer of isolation material in the trenches to fill up the trenches; planarizing the layer of isolation material to form a number of isolation regions, the isolation regions having substantially planar top surfaces, the top surface of each isolation region lying above the top surface of the semiconductor material, the planarizing step including: planarizing the layer of isolation material until the layer of isolation material is removed from the top surface of the layer of nitride to form the number of isolation regions, the top surfaces of the isolation regions being substantially level with the top surface of the layer of nitride, and removing the layer of nitride and the layer of pad oxide to form a number of exposed regions of the semiconductor material; forming a first layer of dielectric material on the semiconductor material after the number of isolation regions have been formed, the step including: forming a layer of gate oxide on the exposed regions of the semiconductor material, etching a number of tunnel window openings in the layer of gate oxide to form a number of exposed regions, and growing a layer of tunnel oxide on the number of exposed regions; forming a first layer of conductive material over the first layer of dielectric material and the isolation regions; and planarizing the first layer of conductive material until the layer of first conductive material is removed from the top surfaces of the isolation regions, a heavily doped region of a second conductivity type being formed in the semiconductor material prior to the layer of gate oxide being formed.