Patent ID: 6107642
Filing Date: 2000-08-22
Classification: H01L

Abstract:
A thin film field effect transistor circuit on a doped silicon semiconductor substrate of a first conductivity type, said doped silicon semiconductor substrate having a surface; said transistor circuit comprising as follows:field oxide regions (31') on portions of said surface of said doped silicon semiconductor substrate (30) and a first insulating layer (32) on said surface of said doped silicon semiconductor substrate (30) between said field oxide region (31, 31') on said doped silicon semiconductor substrate (30);a first polysilicon layer (34, 34') formed only over said field oxide regions (31') and said first insulating layer 32,a buried contact opening (37) through said first polysilicon layer (34, 34') and said first gate oxide layer (32) to said surface of said doped silicon semiconductor substrate adjacent to one of said field oxide regions exposing a contact portion of said surface of said doped silicon semiconductor substrate (30),a second polysilicon layer (38, 38') formed over said first polysilicon layer (34, 34') with a patterned separate contact portion of said second polysilicon layer (38') located over said contact portion of said surface of said doped silicon semiconductor substrate extending through said buried contact opening (37) to form a buried contact (BC1) between said second polysilicon layer (34, 34') and said surface of said doped silicon semiconductor substrate (30),said first polysilicon layer (34) and said second polysilicon layer (38) being doped and being patterned into a first control gate electrode (G1) and said second polysilicon layer also being patterned into a conductor from said buried contact opening (37) and reaching through said first polysilicon layer from said buried contact,said gate electrode (G1) including a conductor line (39, 39') comprising a tungsten silicide layer formed over said second polysilicon layer (38, 38'),doped first source/drain regions (45, 46) of a first transistor formed in said doped silicon semiconductor substrate juxtaposed with said first control gate electrode with one (46) of said first source/drain regions (45, 46) formed below said buried contact opening (37) with said drain region (46) also being juxtaposed with said buried contact (BC1),an interelectrode dielectric layer (48, 48') over said first control gate electrode (G1) and said conductor line (39, 39'),said interelectrode dielectric layer (48) having a gate opening (52) therethrough down to said surface of said doped silicon semiconductor substrate within said buried contact opening (37),a second gate oxide layer (54) on said surface of said drain region (46) in said doped silicon semiconductor substrate (30) extending through said gate opening (52),a semiconductor film (60) formed over said interelectrode dielectric layer (48) and formed over said surface of said second gate oxide layer (52) and extending through said gate opening (52) through said interelectrode dielectric layer (48),a doped channel region (60C) formed in said semiconductor film (60) between second source/drain regions (60S, 60D) formed in said semiconductor film (60) above and aside from said gate opening (52) of a thin film transistor (T4) above said second gate oxide layer (54), with the doped drain region (46) below said second gate oxide layer (54) comprising a second control gate (46(G4)) of said thin film transistor (T4), andsaid second gate oxide layer (54) and said interelectrode dielectric layer (48, 48') separating said semiconductor film (60) from said drain region (46), said second polysilicon layer (38, 38') and said conductor line (39, 39').