Patent ID: 7119567
Filing Date: 2006-10-10
Classification: G01R,G11C

Abstract:
1. A testing system comprising: at least one die on a semiconductor wafer; a selector block connected to the at least one die and at least one write register, the selector block to write original data from the at least one write register onto the at least one die in response to a select signal, at least one comparator connected to the at least one die and to the at least one write register, the at least one comparator to receive read data from the at least one die, the at least one comparator to receive original data from the at least one write register, the at least one comparator to generate at least one result in response to the original data and the read data; a shift register connected to the at least one comparator, the shift register to receive the at least one result from the comparator, the shift register to generate serial data in response to the at least one result; and an error detection circuit connected to the shift register, the error detection circuit to receive the at least one result from the shift register, the error detection circuit to generate an error flag in response to the at least one result.