Patent ID: 9123784
Filing Date: 2015-09-01
Classification: H01L

Abstract:
1. A memory structure, comprising: a substrate, having therein a plurality of trenches, and having thereon an array area and a contact area apart from the array area, wherein each trench has a first portion in the contact area and a second portion in the array area, and the substrate between the first portions of the trenches is also in the contact area and has a surface lower than a surface of the substrate between the trenches outside of the contact area; a plurality of conductive lines, each buried in a trench and having an array portion in the array area and a contact portion in the contact area, wherein the contact portion is protruding above the lower surface of the substrate between the first portions of the trenches in the contact area; and an insulating layer, filling in gaps between protruding parts of the contact portions of the conductive lines in the contact area.