Patent ID: 7561483
Filing Date: 2009-07-14
Classification: G11C

Abstract:
1. A method for testing a test memory cell of a memory array, said method comprising: setting an asymmetric relationship between inverter stages of the test memory cell of said memory array, wherein said inverter stages are cross-coupled to provide a storage latch; setting a symmetric relationship between inverter stages of other memory cells of said memory array; observing an effect of said asymmetry on dynamic stability of said test memory cell as said asymmetric relationship is varied; and adjusting a leakage present at outputs of said test memory cell by changing a state of said other memory cells within said memory array having a common bitline connection with said test memory cell, and wherein said observing is performed for multiple leakage states selected by said adjusting, whereby said method determines an effect of said leakage on said dynamic stability, wherein said adjusting first changes a state of all of said other memory cells to a value matching a state of said test memory cell, and wherein said method further comprises writing another value opposite said value matching said state of said test memory cell into said test memory cell, whereby an effect of said leakage on said writing of another value is observed.