Patent ID: 6291335
Filing Date: 2001-09-18
Classification: G11C,H01L

Abstract:
A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels comprising the steps of:forming gate structures for transistors in an array region and a support region of a substrate;forming first contacts to diffusion regions, the first contacts being disposed in between the gate structures in the array region, the first contacts having a height being substantially the same for all first contacts;forming second contacts and first level bitlines in the array region and the support region, the second contacts in the array region connecting some of the first contacts to the first level bitlines, and the second contacts in the support region connecting a first metal layer to the gate structures and diffusion regions formed in the support region; andforming third contacts and second level bitlines in the array region, the third contacts connecting some of the first contacts to the second level bitlines and the third contacts connecting a second metal layer to the first metal layer in the support region.