Patent ID: 7009886
Filing Date: 2006-03-07
Classification: G11C

Abstract:
1. An integrated circuit memory device comprising: an array of memory cells arranged in a plurality of rows and columns having a plurality of row lines and a plurality of column lines, with cells arranged in the same row connected by a common row line, and cells arranged in the same column connected by a common column line; wherein each cell in said array being addressed by an address signal having a plurality of bits; a sense amplifier circuit connectable to one or more of said plurality of column lines of said array; an address input terminal for receiving said plurality of bits of said address signal in series; each of said column lines connectable to a first voltage; and a decoder circuit for receiving said address signal and for decoding said address signal as each of said plurality of bits is received and for disconnecting certain of said column lines to said first voltage in response to said decoding; and for activating said sense amplifier circuit after all of said plurality of bits of said address signal are received.