Patent ID: 6680635
Filing Date: 2004-01-20
Classification: H03L

Abstract:
A circuit for generating an output clock signal having controlled timing, comprising:a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, in which the first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit; a second delay circuit which receives the input clock signal in order to generate a second delayed input clock signal, in which the second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delay circuit; a phase blending circuit which receives the first and second delayed input clock signals and blending the phases of the first and second delayed input clock signals in order to generate a phase blended clock signal; a phase detection circuit which receives a reference clock signal and the phase blended clock signal in order to generate a phase push signal in the case that a phase of the phase blended clock signal is ahead of that of the reference clock signal, and generate a phase pull signal in the case that the phase of the phase blended clock signal is behind that of the reference clock signal; and a delay control circuit which generates the first or second delay control signal in order to increase the delay when the phase push signal is received from the phase detection circuit and decrease the delay when the phase pull signal is received from the phase detection circuit.