Patent ID: 8981815
Filing Date: 2015-03-17
Classification: H03K

Abstract:
1. A clock gating circuit, for generating a clock enable signal with respect to a clock input signal and a logic enable signal, the clock gating circuit comprising: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1; wherein one transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.