Patent ID: 9171673
Filing Date: 2015-10-27
Classification: G06F,H01G,H01L

Abstract:
1. A method for tuning an on-chip capacitor during operation of an integrated circuit electrically coupled with the on-chip capacitor, the method comprising: powering first and second ports of the on-chip capacitor with opposite polarities; selectively opening and closing a first current path coupling a first electrode with the first port using a first voltage signal supplied from a first voltage-controlled unit of the integrated circuit, wherein the first electrode has an end separated from the first port by a first gap so that the first port and the end of the first electrode lack direct physical connection to electrically isolate the first electrode from the first port; and selectively opening and closing a second current path coupling a second electrode with the second port using a second voltage signal supplied from a second voltage-controlled unit of the integrated circuit, wherein the second electrode has an end separated from the second port by a second gap so that the second port and the end of the second electrode lack direct physical connection to electrically isolate the second electrode from the second port, wherein the first and second electrodes have a parallel arrangement in a space between the first and second ports and aligned transverse to the first and second ports, and the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port than when the first and second electrodes are electrically isolated from the first and second ports.