Patent ID: 7061043
Filing Date: 2006-06-13
Classification: G11C,H01L

Abstract:
1. A non-volatile semiconductor memory device, comprising: a memory cell array including a plurality of bit lines and a plurality of memory cells arranged in a column direction and a row direction, wherein: each of the memory cells has a source region, a drain region, a channel region disposed between the source region and the drain region, a word gate disposed to face the channel region, and a non-volatile memory element provided between the word gate and the channel region; a voltage is respectively applied to the word gate, source region and drain region, when data is to be erased, read from or written to each of the plurality of memory cells; a longitudinal section of the word gate has a base, a side which is perpendicular to the base, and a curved side which connects the base to the sides; each of the plurality of memory cells has a word gate support section that is disposed on an upper layer of the drain region; a longitudinal section of the word gate support section has a base, a side that is perpendicular to the base, and a curved side that connects the base to the side; the side of the word gate support section faces the side of the word gate; the plurality of bit lines are respectively connected to the drain regions of the plurality of memory cells in each column that is arranged in the column direction; and the word gate support section is formed of an insulator.