Patent ID: 6147527
Filing Date: 2000-11-14
Classification: G06F,G11C,H03K,H03L,H04L

Abstract:
A circuit for synchronizing an internal clock signal with an externally generated clock signal, comprising:a digital delay locked loop circuit coupled to receive the externally generated clock signal and output the internal clock signal, said digital delay locked loop circuit having a plurality of unit delay circuits coupled to an associated plurality of phase detection circuits;a first switch coupled between the externally generated clock signal and one of the plurality of unit delay circuits;a second switch coupled between the externally generated clock signal and the plurality of phase detection circuits; anda switching controller coupled to said first and second switches for turning on said first and second switches responsive to a switching control signal, said switching controller is coupled to and receives said internal clock signal for turning off said first and second switches when said externally generated clock signal and said internal clock signal are in phase.