Patent ID: 7755404
Filing Date: 2010-07-13
Classification: H03L

Abstract:
1. A delay locked loop, comprising: a phase detector configured to detect a phase difference; a charge pump configured to perform a charge pumping operation based upon the detected phase difference; a low pass filter configured to filter an output from the charge pump; and a delay line having a plurality of serially-coupled delay elements, the plurality of serially-coupled delay elements including a first selectable group having a first location and a second selectable group having a second location, the second selectable group being larger than the first selectable group, wherein a first clock signal from the first selectable group is first accessed at the first location and provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second selectable group is accessed at the second location to synchronize the delay locked loop, wherein the first location and the second location are the only clock access locations in the delay line; and a selector configured to receive the first clock signal and the second clock signal, and to provide the second clock signal to the phase detector following a synchronization based upon the first clock signal.