Patent ID: 6228703
Filing Date: 2001-05-08
Classification: H01L

Abstract:
A method of fabricating a mixed-mode semiconductor device having a capacitor and a gate, comprising:providing a substrate having a gate oxide layer and a device isolation region thereon;forming a conformal first conductive layer on the gate oxide layer and the device isolation region;forming a conformal dielectric layer on the first conductive layer;patterning the dielectric layer to form an inter-poly dielectric layer covering a portion of the first conductive layer;forming a second conductive layer on the first conductive layer and the inter-poly dielectric layer;patterning the second conductive layer to leave a part of the second conductive layer over the gate oxide layer and to leave a top electrode on the inter-dielectric layer until the first conductive layer is exposed; andremoving the exposed first conductive layer until the gate oxide layer and the device isolation region are exposed.