Patent ID: 6596578
Filing Date: 2003-07-22
Classification: H01L

Abstract:
A semiconductor device comprising:a semiconductor substrate; a first line & space pattern set in which a first, a second, a third, and a fourth line pattern, each of which has a line width L and is made of a conductor, are aligned in turn via a line space S on a first region on the semiconductor substrate; a second line & space pattern set in which a fifth and a sixth line pattern, each of which has not less than the line width L and is made of a conductor, are aligned in turn via not less than the line space S on a second region on the semiconductor substrate; and a third line & space pattern set in which a seventh line pattern, which is connected to the first line pattern and the fifth line pattern and is made of a conductor, and an eighth line pattern, which is connected to the third line pattern and the sixth line pattern and is made of a conductor, are formed on a third region present between the first region and the second region on the semiconductor substrate, the second line pattern terminating at a boundary position between the first region and the third region, and the fourth line pattern terminating at a boundary position between the third region and the second region.