Patent ID: 6570512
Filing Date: 2003-05-27
Classification: H03M

Abstract:
A circuit arrangement for quantizing digital signals and filtering the quantization noise, the circuit arrangement comprising:a multiplicity of digital control loops, each of the digital control loops including a quantizer, each quantizer having a quantization-error signal output for providing a quantization-error signal and a quantized signal output for providing a quantized output signal; a first digital control loop from the multiplicity of digital control loops being configured to receive a digital signal having a first word length, the quantization error signal of each quantizer being filtered and fed back within the respective digital control loop, and the quantization error signal of the first digital control loop being fed downstream to a second digital control loop from the multiplicity of digital control loops, the quantized output signal of the first digital control loop having a third word length smaller than the first word length; and the quantized output signal of the second digital control loop being filtered by a digital filter downstream of the second digital control loop and added, in an adder, to the quantized output signal of the first digital control loop to delete quantization errors, the output signal of the adder having a second word length and being the quantized output signal of the circuit arrangement.