Patent ID: 7615386
Filing Date: 2009-11-10
Classification: H01L

Abstract:
1. A method for reducing wafer backside large particle contamination in the fabrication of an integrated circuit, comprising: (a) performing front end of line processing of a wafer to fabricate various devices on a front side of the wafer; (b) depositing a thick oxide on a backside of the wafer to a given thickness; and (c) performing back end of line processing of the wafer to establish electrical interconnections for the devices, the back end of line processing including multiple chemical mechanical polishing and cleaning steps applied to the front side of the wafer, the cleaning steps acting to etch both the front side and backside of the wafer, thereby causing reductions in the given thickness of the thick oxide; wherein the given thickness to which the thick oxide is deposited is equal to the sum of the reductions plus a predetermined remaining minimum thickness.