Patent ID: 6555453
Filing Date: 2003-04-29
Classification: H01L

Abstract:
A method of manufacturing a semiconductor device having a fully silicided gate electrode and shallow S/D extensions comprising:(a) providing a precursor semiconductor device comprising a substrate, a gate dielectric, a gate electrode and a spacer; (b) depositing a layer of &agr;-Si on the surface of the precursor semiconductor device; (c) implanting dopant ions into the &agr;-Si layer and activating to form a doped &agr;-Si layer; (d) depositing a layer of a metal capable of forming a silicide over the doped &agr;-Si layer; (e) annealing the device to form a metal silicide layer from which dopant segregates to form shallow S/D extensions; (f) removing unreacted metal, metal silicide and spacer; (g) implanting additional dopant ions and activating to form deep, highly doped S/D junctions; (h) depositing a layer of metal capable of forming a metal silicide on the device; (i) annealing the device to form a fully metal silicided gate electrode; and (j) removing unreacted metal to form a semiconductor device having fully silicided gate electrode and shallow S/D extensions.