Patent ID: 7764553
Filing Date: 2010-07-27
Classification: G11C

Abstract:
1. A semiconductor memory device comprising: a memory cell array having a normal memory cell and a redundant memory cell that is used to replace the normal memory cell when it is defective; a predecoder generating a predecode signal by predecoding a row address supplied in synchronism with an active command; a repair determining circuit determining whether the row address is a defective address; a repair address decoder generating a repair address when the repair determining circuit detects that the row address is a defective address; a word driver selecting a word line corresponding to the normal memory cell based on the predecode signal when the repair determining circuit detects that the row address is not a defective address, and selecting a word line corresponding to the redundant memory cell based on the repair address when the repair determining circuit detects that the row address is a defective address; and a signal control circuit resetting the repair address without resetting the predecode signal, in response to issuance of a precharge command.