Patent ID: 6489067
Filing Date: 2002-12-03
Classification: G03F

Abstract:
A reticle for manufacturing a semiconductor integrated circuit, comprising:a circuit pattern region for exposing a predetermined pattern to a semiconductor chip forming portion of a semiconductor wafer, said circuit pattern region being surrounded first to fourth end sides; a scribing line region for exposing a pattern of a cutting region for separating a semiconductor chip from the semiconductor wafer, said scribe line region being adjacent to only said first and second end sides among said first to fourth end sides, said first and second end sides being at right angles to each other; a light shielding region formed to surround said circuit pattern region and said scribing line region, said light shielding region being adjacent to said third and fourth end sides; first alignment measurement marks formed at predetermined portions of said scribing line region, which face said first and second end sides, respectively; concave portions formed at predetermined portions of said light shielding region, which face said third and fourth end sides, respectively; second alignment measurement marks formed in said concave portions, respectively; and light shielding film patterns for light-shielding formed, respectively, at positions where latent images due to said second alignment measurement marks caused by exposure shots to the adjacent portions are formed.