Patent ID: 9201820
Filing Date: 2015-12-01
Classification: G06F

Abstract:
1. A solid state storage device comprising: a plurality of memory controllers, each controller having a memory sequencer, a communication controller, and a plurality of memory communication channels, wherein one of the memory controllers is a master controller and remaining memory controllers are slave controllers to the master controller and the plurality of memory controllers are coupled together over at least one of the memory communication channels; and a plurality of memory devices coupled to each memory controller; wherein the memory sequencer and the communication controller of each memory controller are selectively coupled to their respective plurality of memory devices; wherein only one memory controller of the plurality of memory controllers is configured to select between an output of the memory sequencer and an output of the communication controller for output to its respective plurality of memory devices while the remaining memory controllers are configured to enable selection of only their memory sequencers for communication with their respective plurality of memory devices.