Patent ID: 6763470
Filing Date: 2004-07-13
Classification: H03F,H03G

Abstract:
A signal processing and amplifying circuit comprising:a shift register configured to receive a stream of digital data, wherein the stream of digital data comprises a digital representation of an analog input signal; a digital to analog converter configured to receive digital data output from the shift register and convert the digital data to a delayed analog signal; a multi-stage amplifier circuit having an amplifier for each stage of the circuit, each amplifier of the multi-stage amplifier circuit positioned to receive the delayed analog signal output from the digital to analog converter and output a signal to a communication channel; and a state machine having an input disposed to receive the digital representation of the analog input signal from the shift register at an interim location between the input and output of the shift register, the state machine having circuitry for using the digital representation of the analog input signal to generate control outputs that enable an amplifier in the multi-stage amplifier circuit.